1990_Toshiba_C2MOS_Logic 1990 Toshiba C2MOS Logic
User Manual: 1990_Toshiba_C2MOS_Logic
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TOSHIBA
C2MOS LOGIC
TC74AC/ACT SERIES
TC74HC/HCT SERIES
1990
C2MOS LOGIC
TC74AC/ACT SERIES
INTRODUCTION
The TOSHIBA 74AC/ACT Series of Advanced CMOS Logic (ACL) ICs match bipolar FAST* products in speed,
function and pinout. The devices are fabricated with silicon gate, double-layer metal wiring C2MOS technology which
is utilized for VLSls.
The TC74ACIACT Series has a 3.5ns propagation delay time for gate products and operates at more than 150 MHZ
for Flip-Flops. The output drive capability of 24mA (II oHl/loL) permits the TC74AC/ACT devices to drive 50n
tnl.1lsmission lines directly.
The family features of the TC74ACIACT product line include:
- Reduced simultaneous switching noise.
-Wide operating volt range (2-5.5V) (TC74AC type).
- High noise immunity of 28% of the power supply for AC types.
- Excellent ESD Protection (2KV iMIL-STD-883) and excellent latch-Up immunity.
Applications for TC74AC/ACT include industrial products, such as telecommunications, data processing and
electronic instruments.
This data book presents technical information on TOSHIBAll TC74ACIACT series.
The information contained in this data book is subject to change without notice.
*FAST is a Trademark of National Semiconductor Corp.
FEBRUARY, 1990
AC-1
1.
2.
This technical data may be controlled under U.S. Export Administration Regulations and may be subject
to the approval 0' the U.S. Department 0' Commercer.rlorto export. Any export or r..export directly or
Indirectly. In contrllY8ntion 0' the U.S. E~port Admin stration Regulations Is strictly prohibited.
LIFE SUPPORT POLICY
Toshiba producta described In this datebook are not authorized 'or use as critical components In Ille
support systems without the written con.ent 01 the appropriate orncer of Toshiba America. Inc. Llle
support systems are either systems Intended 'or surgical Implant In the body or systems w.hlch IUltaln IIle.
0'
A critical component Is any component a Ille support system whose 'allure to perform may caule a
malfunction or 'allure 01 the life support system. or may aHect Its safety or effectivene...
3.
The Information InJhls datobook has been carefully checked and Is believed to be reliable. however. no
responsibility can be assumed 'or Inaccuracies that may not heve baan caught. All Information In this
datebook Is.ubJecl to change without prior notice. Furthermore. Toahlbacannot ..sume responsibility
lor the use 0' any llCei'lse under the patent right. 0' Toshiba or any third partie••
AC-2
CONTENTS
1.
HIGH SPEED CMOS PRODUCT GUIDE .................................................................................... AC-4
2.
HIGH SPEED CMOS SELECTION GUIDE ....................................................................................... 6
3.
PRODUCT OUTLINE OF THE TC74AC SERIES .............................................................................. 7
3-1
Features .............................................................................................................................. 7
3-2
Method of Designating the TC74AC Series"""""""'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' 8
4.
EXPLANATION OF RATINGS AND STANDARDS ........................................................................ 11
4-1
Maximum Ratings ............................................................................................................... 11
4-2
Recommended Operating Conditions .................................................................................... 12
4-3
DC Characteristics ............................................................................................................... 13
4-4
AC Characteristics ............................................................................................................... 17
5.
EXPLANATION OF IEC LOGIC SYMBOL ...................................................................................... 22
5-1
Symbol Composition ............................................................................................................. 22
5-2
Qualifying symbol ............................................................................................................... 22
5-3
Dependency Notation ............................................................................................................ 26
6.
HOW TO READ MIL TYPE LOGIC SYMBOLS AND TRUTH TABLES ............................................ 28
6-1
How to Read MIL type Logic Symbols"""""""""""""""""""""""'"'''''''''''''''''''''''''''''''''' 28
6-2
How to Read Truth Tables ................................................................................................... 30
7.
COMMON ELECTRICAL CHARACTERISTICS .............................................................................. 31
7-1
Power Dissipation ............................................................................................................... 31
7-2
Standardized Capacitance Power .......................................................................................... 34
Dissipation (C PO) Test Procedure
7-3
Output Current Characteristics ............................................................................................. 38
7-4
AC Electric Characteristics .................................................................................................. 39
7-5
Temperature Parameters of Various Characteristics .............................................................. 40
8.
PRECAUTIONS IN HANDLING ...................................................................................................... 41
8-1
Electrostatic Discharge···· .. ·· .... ····· ........ · .............................................................................. 41
8-2
Precaution in Handling ........................................................................................................ 42
9.
PRECAUTIONS IN DESIGNING CIRCUITS .................................................................................... 44
9-1
Input Processing .................................................................................................................. 44
9-2
Design of Power Source ........ ·· .... ······· ........ ······ ........ ·· .... · .... · ...... · .......................................... 45
9-3
Output Short Circuit ........................................................................................................... ··45
9-4
Effect on Input of Slow Rise and Fall Time ........................................................................... 46
9-5
Wiring Precautions ............................................................................................................... 47
9-6
Interface .............................................................................................................................. 48
9-7
Latch-Up ........................................................................................................................... 52
10.
DATA SHEETS ............................................................................................................................. 55
11.
OUTLINE DRAWINGS .................................................................................................................. 307
12.
RELIABILITY DATA .. ·.................. ·· .. ·· .. · ............ · .... ·.. ·.. ··· ...... ·...... · .............................................. 315
13.
APPLICATION NOTES ..................................................................... , .. 321
13-1 Simultaneous Switching Voltage Noise .................................................... 323
14.
CROSS REFERENCE GUIDE ................................................................... 335
______________________
---------------------------------TaeHHaACOR~
AC-3
1 . TC74ACI ACT Series Product Guide.
PIN
Page
OOP/F/FN
TOOP/F/FN
02P/F/FN
T02P/F/FN
04P IF IFN
T04P/F/FN
05P/F/FN
08P/F/FN
T08P/F/FN
10P/F/FN
QUAD 2-INPUT NAND GATE
QUAD 2-INPUT NAND GATE
QUAD 2-INPUT NOR GATE
QUAD 2-INPUT NOR GATE
HEX INVERTER
HEX INVERTER
HEX INVERTER (OPEN DRAlN)
QUAD 2-INPUT AND GATE
QUAD 2-INPUT AND GATE
TRIPLE 3-INPUT NAND GATE
14
14
14
14
14
14
14
14
14
14
57
60
63
66
69
72
75
78
81
84
TlOP/F/FN
llP/F/FN
14P/F/FN
T14P/F/FN
20P/F/FN
32P/F/FN
T32P/F/FN
74P/F/FN
T74P/F/FN
86P/F IFN
TRIPLE 3-INPUT NAND GATE
TRIPLE 3·-INPUT AND GATE
HEX SCHMITT INVERTER
HEX SCHMITT INVERTER
DUAL 4-INPUT NAND GATE
QUAD 2-INPUT OR GATE
QUAD 2-INPUT OR GATE
DUAL D-FLIP-FLOP WITH PRESET AND CLEAR
DUAL D-FLIP-FLOP WITH PRESET AND CLEAR
QUAD EXCLUSIVE OR GATE
14
14
14
14
14
14
14
14
14
14
T86P IF IFN
109P IF IFN
T109P/F/FN
112P/F/FN
T1l2P/F/FN
125P/F/FN
126P/F/FN
138P IF IFN
T138P IF IFN
139P IF IFN
QUAD EXCLUSIVE OR GATE
DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR
DUAL J-K FLIP-FLOP
DUAL J-KFLIP-FLOP WITH PRESET AND CLEAR
DUAL J-K FLIP-FLOP
QUAD BUS BUFFER (3-STATE)
QUAD BUS BUFFER (3-STATE)
3-TO-8 LINE DECODER
3-TO-8 LINE DECODER
DUAL 2-T0-4 LINE DECODER
14
16
16
16
16
14
14
16
16
16
113
116
120
124
T139P/F/FN
151P IF IFN
T151P IF IFN
153P/F/FN
T153P IF IFN
157P/F/FN
T157P IF IFN
158P/F/FN
T158P IF IFN
160P/F IFN
DUAL 2-T0-4 LINE DECODER
8-CHANNEL MULTIPLEXER
8-CHANNEL MULTIPLEXER
DUAL 4-CHANNEL MULTIPLEXER
DUAL 4-CHANNEL MULTIPLEXER
QUAD 2-CHANNEL MULTIPLEXER
QUAD 2-CHANNEL MULTIPLEXER
QUAD 2-CHANNEL MULTIPLEXER(INV.)
QUAD 2-CHANNEL MULTIPLEXER(INY.)
SYNC. DECADE COUNTER WITH ASYNC. CLEAR
16
16
16
16
16
16
16
16
16
16
143
146
149
152
156
160
164
160
164
168
161P IF IFN
T161P/F/FN
162P/F/FN
163P/F/FN
T163P/F/FN
164P/F/FN
T164P/F/FN
166P/F/FN
169P/F/FN
174P/F/FN
SYNC. BINARY COUNTER WITH ASYNC. CLEAR
SYNCH BINARY COUNTER
SYNC. DECADE COUNTER WITH SYNC. CLEAR
SYNC. BINARY COUNTER WITH SYNC. CLEAR
SYNCHRONOUS BINARY CTR
8-BIT SIPO SHIFT REGISTER
8-BIT SIPO SHIFT REGSTR
8-BIT SIPO SHIFT REGISTER
4-STAGE SYNCH BIDIR COUNTER
HEX D FLIP-FLOP WITH CLEAR
16
16
16
16
16
14
14
16
16
16
168
T174PlF/FN
175P/F/FN
T175P/F/FN
191P/F/FW
240P/F/FW
T240P/F/FW
241P/F/FW
T241P/F/FW
244P/F/FW
T244P/F/FW
HEX D-TYPE FLIP-FLOP
QUAD D FLIP-FLOP WITH CLEAR
QUAD D-TYPE FLIP-FLOP
4-BIT BINARY UPIDOWN COUNTER
OCTAL BUS BUFFER(3-STATEIINY.)
OCTAL BUS BUFFER(3-STATE/INY.)
QCTAL BUS BUFFER(3-STATE)
OCTAL BUS BUFFER
OCTAL BUS BUFFER(3-STATE)
OCTAL BUS BUFFER (3-STATE)
16
16
16
16
20
20
20
20
20
20
190
194
198
202
205
202
205
202
205
245P/F/FW
T245P/F/FW
251P/F/FN
T251P/F/FN
253P IF IFN
OCTAL BUS TRANSCEIVER(3-STATE)
OCTAL BUS TRANSCEIVER(3:-STATE)
8-CHANNEL MULTIPLEXER(3-STATE)
8-CHANNEL MULTIPLEXER(3-STATE)
DUAL 4-CHANNEL MULTIPLEXER(3-STATE)
20
20
16
16
16
208
212
146
149
152
Function
TVPENO.
TC74AC
87
90
-
93
96
99
102
106
110
128
128
132
136
140
-
168
168
-
178
182
187
-
~aA~~~--~--------------~------------------------------~--------
AC-4
TYPE NO.
Function
DUAL 4-CHANNEL MULTIPLEXER(3-8TATE)
QUAD 2-CHANNEL MULTIPLEXER(3-8TATE)
QUAD 2-CHANNEL MULTIPLEXER(3-8TATE)
QUAD 2-CHANNEL MULTIPLEXER(3-STATEIINY.)
QUAD 2-CHANNEL MULTIPLEXER(3-STATEIINY.)
OCTAL D FLIP-FLOP WITH CLEAR
OCTAL D FLIP-FLOP WITH CLEAR
9-BIT PARITY CHECK/GENERATOR
9-BIT PARITY CHECK/GENERATOR
4-BIT BINARY FULL ADDER
4-BIT BINARY FULL ADDER
8-BIT PIPO SHIFT REGISTER
8-BIT PIPO SHIFT REGISTER
8-BIT PIPO SHIFT REGISTER
8-BIT PIPO SHIFT REGISTER
HEX BUS BUFFER(3-STATE)
HEX BUS BUFFER(3-STATEIINY.)
OCTAL D-TYPE LATCH(3-8TATE)
OCTAL D-TYPE LATCH(3-8TATE)
OCTAL D-TYPE FLIP-FLOP(3-8TATE)
OCTAL D-TYPE FLIP-FLOP(3-STATE)
OCTAL D-TYPE FLIP-FLOP
OCTAL D-TYPE FLIP-FLOP
DUAL DECADE COUNTER
DUAL BINARY COUNTER
8-BIT IDENTITY COMPARATOR
8-BIT IDENTITY COMPARATOR
8-BIT IDENTITY COMPARATOR
8-BIT IDENTITY COMPARATOR
OCTAL D-TYPE LATCH(3-8TATE/INY.)
OCTAL D-TYPE LATCH(3-8TATEIINY.)
OCTAL D-TYPE FLIP-FLOP(3-STATEIINY.)
OCTAL D-TYPE FLIP-FLOP(3-STATEIINY.)
OCTAL BUS BUFFER(3-8TATEIINY.)
OCTAL BUS BUFFER(3-8TATE/INY.)
OCTAL BUS BUFFER(3-8TATE)
OCTAL BUS BUFFER(3-8TATE)
OCTAL D-TYPE LATCH(3-8TATEIINY.)
OCTAL D-TYPE LATCH(3-8TATEIINY.)
OCTAL D-TYPE FLIP-FLOP(3-STATEIINY.)
OCTAL D-TYPE FLIP-FLOP(3-8TATEIINY.)
OCTAL D-TYPE LATCH(3-8TATE)
OCTAL D-TYPE LATCH(3-STATE)
OCTAL D-TYPE FLIP-FLOP(3-8TATE)
OCTAL D-TYPE FLIP-FLOP(3-8TATE)
OCTAL BUS TRANSCEIVER(3-8TATEIINY.)
OCTAL BUS TRANSCEIVER(3-8TATE)
OCTAL BUS TRANSCEIVER(3-8TATEIINY.)
OCTAL BUS TRANSCEIVER(3-STATE/INY.)
OCTAL BUS TRANSCEIVER(3-8TATE)
646P
OCTAL BUS TRANSCEIVERIREGISTER(3-8TATE)
T646P
OCTAL BUS TRANSCEIVERIREGISTER(3-8TATE)
648P
OCTAL BUS TRANSCEIVERIREGISTER(3-8TATEIINY.)
T648P
OCTAL BUS TRANSCEIVERIREGISTER(3-STATE/INY.)
.670P/F/FN 4-WORDx4BIT REGISTER FILE(3-STATE)
821P/F/FN lO-BIT D-TYPE FLIP-FLOP (3-STATE)
T821P/F/FN 10-BIT D~TYPE FLIP-FLOP (3-STATE)
823P/F/FN 9-BIT D-TYPE FLIP-FLOP
T823P/F/FN 9-BIT D-TYPE FLIP-FLOP
825P/F/FN 8-BIT D-TYPE FLIP-FLOP
T825P/F/FN 8-BIT D-TYPE FLIP-FLOP
841P/F/FN 10-BIT TRANSPARENT LATCH(3-8TATE)
T841P/F/FN 10-BIT TRANSPARENT LATCH(3-8TATE)
843P/F/FN 9-BIT TRANSPARENT LATCH
T843P/F/FN 9-BIT TRANSPARENT LATCH
T253P/F/FN
257P/F/FN
T257P/F IFN
258P/F/FN
T258P/F/FN
273P/F/FW
T273P/F/FW
280P/F/FN
T280P/F/FN
283P/F/FN
T283P/F IFN
299P/F/FW
T299P/F/FW
323P/F/FW
T323P/F/FW
367P/F/FN
368P/F/FN
373P/F/FW
T373P/F/FW
374P/F/FW
T374P/F/FW
377P/F/FW
T377P/F/FW
390P/F/FN
393P/F/FN
520P/F/FW
T520P/F/FW
521P/F/FW
T521P/F/FW
533P/F/FW
T533P/F/FW
534P/F/FW
T534P/F/FW
540P/F/FW
T540P/F/FW
541P/F/FW
T541P/F/FW
563P/F/FW
T563P/F/FW
564P/F/FW
T564P/F/FW
573P/F/FW
T573P/F/FW
574P/F/FW
T574P/F/FW
620P/F/FW
623P/F/FW
640P/F/FW
T640P/F/FW
643P/F/FW
PIN
Page
16
16
16
16
16
20
20
14
14
16
16
20
20
20
20
16
16
20
20
20
20
20
20
16
14
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
24
24
24
24
16
29
29
24
24
24
24
24
24
24
24
156
216
220
216
220
224
227
231
231
-
237
237
240
244
248
252
-
256
261
-
240
244
248
252
265
268
265
268
271
275
279
283
271
275
279
283
287
287
208
212
208
291
296
291
296
301
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOIIHI~ CDRlllDRATIGN
AC-5
2. TC74ACI ACT Series Selection Guide.
GATE
NAND
NOR
AND
OR
INVERI'ER,BUFFER
EXCLUSIVE OR
SCHMITT TRIGGER
BUS BUFFER
ACOO ACTOO ACIO ACTIO AC20
AC02 ACT02
AC08 ACT08 ACll
AC32 ACT32
AC04 ACT04 AC05 AC14
AC86 ACT86
AC14 ACT14
BUFFER
AC125 AC126 AC240 ACT240 AC241 ACT241 AC244
ACT244 AC367 AC368 AC540 ACT540 AC541 ACT541
BUS TRANSCEIVER
AC245 ACT245 AC620 AC623 AC640 ACT640
AC643 AC646 ACT646 AC648 ACT648
FLIP-FLOP
J-K FLIP-FLOP
ACI09 ACTI09 AC1l2 ACT112
D FLIP-FLOP
AC74 ACT74 AC174 ACT174 AC175 AC273 ACT273
AC377 ACT377 AC823 ACT823 AC825 ACT825
3-STATE
AC374 ACT374 AC534 ACT534 AC564 ACT564
AC574 ACT574
AC646 ACT646 AC648 ACT648 AC821 ACT821
LATCH
AC843 ACT843
3-STATE
AC373 ACT373 AC533 ACT533 AC563 ACT563
AC573 ACT573 AC841 ACT841
DECODER
AC138 ACTl38 AC139 ACT139
REGISTER
AC164 ACT162 AC166 AC299 AC323 ACT323
MULTI-PORI' AC670
COUNTER
BINARY
AC161 ACT161 AC163 ACT 163 AC169 AC191 AC393
DECADE
AC160 AC162 AC390
MULTIPLEXER
AC151 ACT151 AC153 ACT153 AC157 ACT157
DIGITAL
AC158 ACT158 AC251 ACT251 AC253 ACT253
AC257 ACT257 AC258 ACT258
PARITY TREE
AC280 ACT280
ADDER
AC283 ACT283
COMPARATOR
AC520 ACT520 AC521 ACT521
.TOIIIoII~CQI=IPOIIATION
----------------------------
AC-6
3.PRODUCT OUTLINE OF THE TC74AC SERIES
3-1
Features
High Speed Operation:
Same as Bipolar Schottky TTL
Low Power Dissipation:
Same as standard CMOS series (/I. W)
Output Drive Capability:
Symmetrical Output Impedance.
IIoHI, IOL at least 24mA.
High Noise Immunity:
AC TYPE 28"YCC (Min.)
ACT TYPE 14"YCC (Min.)
Wide Operating Voltage Range:
AC TYPE = 2Y-S.5Y
ACT TYPE =4.SY-S.SY
Wide Operating Temperature Range:-40 to + 85"C
Self-contained static electricity protective circuit:
±300V (typ.) by EIAJ method
±2000Y (typ.) by MIL STD method
(All inputs and outputs)
Ample Latch up Capacity: 'lbtal input and output ± 300 rnA or more.
Same pin connection and function as 74F series.
Wide product Line up: Over 100 types
Table 3-2 shows comparison of characteristics of various logic families.
TTL
CMOS
Parameter
~rmbol
ACL
FAST AS-TTL ALS-TTL unit TEST CONDITION
HCL
(TCl4ACXXX) TC74HCXXXA
(74F)
(74AS) (74ALS)
Propagation Delay Time tpd
4
4.1
10
6.5
ns
4.7
V =5V
BUS BUFFER(244) typo
Ta=25"C
Maximum Clock Frequency
CL=5OpF
tux 150
134
65
125
50
MHz
D-F • F(74)typ.
Quiescent Power Dissipation Po
W
0.0111
22m
32m
5m
0.0111
GATE(OO)typ.
1
1
IIH
20
over temperature
20
20
IIA
-1
-1
IlL
-600
-500
-100
and voltage range
Input Voltage
VIH
3.5
3.5
2.0
2.0
2.0
V over temp.range
VIL
1.5
1.5
0.8
0.8
0.8
Output Current
IOH
IOL
-24
24
Operating Voltage Range Vlpr • 2.0-5.5
Opereting Tempereture Range T.
-4/-6
4/6
-1/-3
20/64
-2/-3
20/64
2.0-6.0 4.75-5.25 4.5-5.5
-40-85 -40-85
0-70
0-70
-0.4/-3
8/24
rnA over temp.range
4.5-5.5
V
0-70
"C
Table 3-2 Comparison of Logic Family Characteristics
---------------------------------------------------------------~I~ ~~N
AC-7
3-2
Method of Designating the TC74AC Series
The TC74AC series is designated using the standard established by JEDEC and is as shown below;
TC74ACD
ODD
T
'~L
:36~» Other inCormation (as required)
~ Package Type (P, F, FN, FW)
Revision Level (blank Cor original)
Function
2) Type classification by JEDEC
(74AC, 74ACT)
1) TOSHIBA CMOS
(designates TOSHIBA
and process)
(Example) TC74ACT240FW:
High Speed C2MOS IC which is pin and functionally compatible with the bipolar 74F240 .
Input is designed for TTL voltage levels, and direct driving from TTL is possible.
Package type is plastic 300mil body width SOIC.
Proprietary name identifying TOSHIBA CMOS devices.
(2) Type classification (AC, ACT)
In addition to the AC devices, there are ACT types. This differentiation was made by JEDEC in order to separate
CMOS devices of the same function but with different input levels or the existence of a buffer.
TYPE
Internal stages
Input threshold voltage
AC
Two stages and above
CMOS level
ACT
Two stages and above
TTl
level
~~ ~------------------------------------------------------------
AC-8
Taking an inverter as an example. we can show the difference between these types as followtl:
TC74AC04
TC74ACT04
Logic Diagram
-{>o--{>o--[>-
-{>o--{>o--[>-
Input-Output
5~tL
Voltage transfer
characteristics
2.5V
--VIN
5VtL
1.4V
(3) Function
Functions are expressed by Arabic numbers of two to five figures.
In the case of TC74AC series. these numbers are the same as 74F series devices ha\'ing the same pin
connections and function.
(Example) 74F240-74AC240
(4) Revision Level
This symbol is used to clarify the revision of product when improvements which change the characteristics of
product are made. Normally, it is blank, however, upon revision, English characters are given successively from ''A''.
Suffix "A" of Tc74ACxxxA series would indicate the types which have refmed AC characteristics due to redesign of
IC chip but still meet JEDEC standards for the family.
---------------------------------------------------------------~I~ C~A~
AC-9
(5) Package Type
English characters showing type of package.
P .....••.• dual in line package (DIP) Plastic
F ........ ·200 mil small outline Ie (SOle) Plastic
FN ......... 150 mil small outline Ie (SOle) Plastic
FW ......... 300 mil small outline Ie (SOle) Plastic
In the TC74AC series, narrow 300 mil type 24 pin DIP package have been developed. Therefore, all P type,
14/16/20/24 pins devices have a 300 mil width (7.62 rnm).
(6) Other information
AB an example, in the case of SOIC Adhesive and Embossed Thpe and Reel specifications, the following suffixes are
added to the part number:
(TP 1) or (TP 2) (Difference in pin 1 position) Adhesive tape.
(ELP) ... Embossed Thpe and Plastic Reel.
For 150/200/300mil SOIC.
(EL) ... Embossed Thpe and Paper Reel.
For 200mil SOIG.
...
~
caFL~~~--------------------------~-----------------------------------
AC·10
4.
EXPLANATION OF RATINGS AND STANDARDS
4-1
Maximum Ratings
In general, the maximum rating value should not be exceeded in order to guarantee the life and reliability of
integrated circuit products.
The Absolute Maximum Rating should not be exceeded even for a moment.
When the device is used in excess of any maximum rating, the device may not recover, and, in many cases, permanent
damage will occur.
In designing the circuit, therefore, it is necessary to pay attention to the fluctuation of supply voltage,
characteristics of interconnecting parts, ambient temperature, and surges in input and output signal lines, so that the
maximum ratings will not be exceeded.
'Thble 4-1 indicates common absolute maximum ratings of the TC74AC series. When the maximum ratings and
common ratings differ, the former shall control. For definition of parameters, refer to 'Thble 4-2.
Table 4-1 Absolute Maximum Ratings
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
10K
VALUE
-0.5 - 6.0
-0.5 -Va;+0.5
-0.5 -Va;+0.5
±20
±50
UNIT
V
V
V
rnA
rnA
DC Output Current
lem
±50
rnA
DC Va;/Ground Current
Ia;
Power Dissipation
Storage Temperature
Lead Temperature 10sec
Po
Tstg
TL
SYMBOL
Va;
V I1Ii
VOLT
11K
± 100(For 40utputs type)
500(DIP) ./180(SOP)
-65 -150
300
I
rnA
1. For devices with more
than 4 outputs, the
maximum rating equals the
number of outputs multiplied
by +1-25mA.
2. 500mW in the range of
'Th= -40°C-65°C. From
Ta=65°C to 85°C a derating
factor or - 10mWroc shall be
applied until 300mW
mW
"C
"C
---------------------------------------------------------------~I~ C~~A~~
AC-11
Table 4-2
Parameter
Explanation
Symbol
Supply Voltage
Vee
The voltage range in which the Ie does not present breakdown,
deterioration of characteristics or reduced reliability.
DC Input Voltage
DC Output Voltage
VIN
VOUT
The voltage range in which the Ie does not present breakdown,
deterioration of characteristics or reduced reliability.
Input Diode Current
Output Diode Current
11K
10K
The current value in which the Ie does not present breakdown due to
latch-up when input or output current flows.
• Practically, a design in which De current flows is not recommended.
When a flow of current cannot be prevented, adopt a current value lower
than this.
DC Output Current
DC Vee/Ground Current
lOUT
Icc
Output current indicates the current value which can flow from one output.
As VcdGND current includes output current, in an Ie having many output
terminals, substantial Vcc/GND current can flow.
Power Dissipation
Po
Indicates power consumption, Which, if exceeded, can cause breakdown of
the device over the entire operating temperature range.
Storage Temperature
Tllg
The ambient temperature range over which deterioration of characteristics
and reliability will not occur when left for a long time in a state without
supply voltage.
Lead Temp. and Time
TL
Indicates the maximum allowable conditions permitted when soldering is
carried out after Ie mounted on printed board.
4-2 Recommended Operating Conditions
These are the conditions in which the operation of the TC74AC series is guaranteed, and when exceeded,
operation is not guaranteed even though they are within the maximum ratings of Thble 4-1.
Common recommended operating conditions of the 74AC series are shown in Thble 4-3. When
recommended operating conditions for specific devices and common recommended operating conditions
differ, the former shall control. Refer to Thble 4-4 for definitions.
Table 4-3 Common Recommended Operating Conditions
(al 74AC Type
PARAMETER
Supply Voltage
Input Voltage
Output V Qltage
Operating Temperature
Input Rise and FaU Time
SYMBOL
VALUE
Vee
VL"I
VOL'T
2 - 5.5
o -Vee
o -Vee
-40 - 85
Topr
dt/dv
oo-
lOO(Vee=3.3±0.3V)
20 (Vee= 5 ±0.5V)
UNIT
V
V
V
"C
ns/v
'TOIIMIIIA COIiUlClIUImCIN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-12
(hI 74ACT Type
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI:'>1
VOUT
Topr
dt/dv
o-
VALUE
4.5 - 5.5
o -Vee
0- Vee
-40 - 85
10(Vee=5±0. 5V)
UNIT
V
V
V
·C
ns/v
Table 4-4
Parameter
Explanation
Symbol
Supply Voltage
Vcc
The supply voltage range guaranteeing normal operation of the IC.
Input Voltage
Output Voltage
VIN
VOUT
The input/output voltage range guaranteeing normal operation of the IC.
Operating Temperature
Topr
The operating temperature range guaranteeing normal operation and
electrical characteristics of the IC.
Input Rise and Fall Time
dt/dv
The rise and fall time range of the input signal which will not cause
oscillation of the output.
4-3 DC characteristics
Thble 4-5 shows the DC characteristics of AC and ACT types. For the meaning of each parameter, refer to
Thble 4-6. Thble 4-5 is the standard DC characteristics table, and when it differs from individual
characteristics, the latter shall control. DC characteristics are established by JEDEC (Standard 20). In the
TC74AC series, all devices meet or exceed this standard.
------------------------------------------~-------------------Tt3~I~ C~~
AC-13
Table 4-5 DC Characteristics Table
74AC Type
(a)
PARAMETER
SYMBOL
High-Level
Input Voltage
VIIi
Low-Level
Input Voltage
VIL
TEST CONDITION
1m =-50,u A
High-Level
Output Voltage
Va-!
VI'" =
VlliorVIL
l
O.SVee
VOL
OUTPUTS
ENABLED
OUTPUTS
DISABLED
(2) ACT '!YPes
iv ) t
pLH • t pHL
i-----~~~---------3V
INPUT
~~---------GND
OUTPUT
-""'90""'''''''''--- VOH
11
AC-20
OL
V)
tw ,t
,t
IU
h
t r
,t rem
3ns .....
rr
3na
-.-~r
I
CLOCK
INPUT
9011
1.5V
lOll
,
I
1\
)
tw(H)
twO..J
,
th (H)
I
DATA
INPu'r
I
\
J
OUTPUT
t rem
I----<
r\.
GND
5v ee
io----o tpH L
tpLH
3.0V
~V.
SET,RESET
or PRESET
",1.5 V
GND
Inactive
Active
State
vi)
It
3.0V
Is O..J
ts (H)
~
GND
,
thO..J
~.5V
---1
3.0V
state
t pLZ ,t pHZ ,t pZL ,t pZH
t r
3ns
3na
3V
OUTPUT
DISABLE
OND
VOH
OUTPUT:
LOW TO OFF
OUTPUT:
HIGH TO
0. 5Vee
LOW
----I~'I
VOL ( .. aND)
VOH ( .. Vee)
OFF
0. 5Vee
HIGH
VOL
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
------------------------------------------------------------~~~IBACOAPQR~
AC-21
6. EXPLANATION OF IEC LOGIC SYMBOLS
&-1
Symbol composition
A symbol comprises an outline or a combination of outlines together with one or more
qualifying-symbols. The purpose of a general qualifying symbol is to accurately portray the logic
function of the device.
general quarifying sym bol
ou tline
input
lines
[
*: qualifying
5-2
(l)
**
**
* *
* *
}
o",p.'
lines
symbol locations for inputs and outputs
Qualifying Symbols
General Qualifying Symbols
symbol
definition
&
AND element
?1
OR element
=1
EXCWSIVE OR element
=
Logic identify element. If all inputs have the same logic state then. the output is at
internal loge"'" .
2K
Even element. If an even number of inputs are at internal logic "'" then the output is
at internal logic"," .
2K+l
Odd element. If an odd number of inputs are at internal logic "'" then the output is
at internal logic "1".
1
r> or ---bf
logic negation at an input. An external logic "0"("'") produces an internal logic "'"("0").
logic negation atan output. An int.rnallogic "0"("'") produces an ext.rnallogic "'"(·0").
Porlarity indicetor at an input. A "l" (low) level active.
ro----
Porlarity indicator at an output. A "l" level active.
!'d--
Porlarlty Indicator at an Input where the 81gnal flow Is from right to left.
---'1
Porlarlty Indicator at an output where the algnal flow Is from right to left.
----\>
Indicator for direction of signal flow.
Bidirectioninformation flow (alternat.).
Dynamic input
Positive logic.
O~l
Negative logic.
Porlarity indicate.
O~l
L~H
The above transitions produce the i nterna I logic active.
~
Dynamic input
Positive logic.
l~O
Negative logic.
l~O
The above transitions produce the internal logic active.
Dynamic input
Po ria ri ty indicate.
---4>
H~L
The above transitions produce the internal logic active.
~,.
~
Non.,.logic connection.
Input for analog signals.
(3) Symbols of the internal connection
symbol
definition
::£:
A logic"'" at the left-hand side produces a logic ·0" at the right-hand side.
=c
Negated internal connection. A logic .," at the left-hand side produces a logic ·0· at
the right-hand side.
:L
Dynamic internal connection. A transition from internal logic "0" to internal logic
.,. at the left -hand side produces a transistory logic"'" at the right-hand side.
-f
Internal input (virtual). This input is always at internal logic ·1" state unless this is
overridden or modified.
=:=3-
Internal output (virtual). This effect on the internal input connected to this output
must be indicated by dependency notation.
~1~.~~RATaaN---------------------------------------------------------------
AC-24
(4) Symbols inside the outline
symbol
If--1ff
definition
Delayed output. The output change is delayed until the input that indicated the
change returns to its initial external state or level.
Schmitt trigger input.
Of--
Open-drain output without internal pulled-up resistor.
s:tf--
Open-drain output with internal pulled-up resistor.
Of--
Open-source output without internal pulled-down resistor.
~f--
Open-source output with internal pulled-down resistor.
V'f--
Th ree-state output.
[>f--
Buffered output.
(The triangle points in the direction of signal flow)
---l
EN
J.K.D
R.S.T.C
Enable input.
Information inputs of disable elements.
Control inputs of disable elements.
+m.+m
Shift input. The direction of shift is to the right or down when the arrow points to the right. or
to the left. ·m·=1.2.3 .. ··• however. the number may be omitted when "m"=1.
-1+ m '-1- m
Counting input. Count-up or count-down are indicted by + and - respectively.
The number "m" is the count per command and may be omitted when "m"=1.
~: }
---1 CT =m
CT=9f--
==n
-1"1"."1"1-
Bit-grouping symbol.
Om" is the highest power of 2 in the group.
Content input.
The internal logic "1" sets the element to the value m ".
U
Content output. For example. when the input state is "1". the internal registor sets
"9" .
Line-grouping symbol. The inputs enclosed by this symbol from a single logic input.
Fixed-mode input. Fixed-state output. This input (output) is parmanently at
internal logic "1".
---------------------------------------------------------------~~ ~A~
AC-25
5-3
Dependency Notation
Dependency notation is the powerful tool that makes IEC Logic Symbols compact and yet meaningful. With
IEC symbols, the relationships between inputs and outputs are clearly illustrated without the necessity of
showing all elements and interconnections involved.
In dependency notation, the terms "affecting" and affected" are used.
(1)
These general rules applied to dependency notation:
1) The input (or output) affecting other inputs or outputs is labelled with the letter symbol that indicates
the relationship involved followed by an appropriately chosen identifying number.
2)
Each input or output affected by that affecting input (or output) is labelled with that same
number.
3)
If it is the complement of the input's (or output's) internal logic state that does the affecting,
then a bar is placed over the identifying numbers at the affected inputs or outputs.
4)
If the affected input or output has a label to denote its function, this label will have the identifying
number of the affecting input as a prefix.
5)
If two affecting inputs or outputs have the same letter and the same identifying number, they are
ORed together.
6)
If the labels denoting the function of affected inputs or outputs are numbers (example: outputs of a
coder), the identifying number of both affecting inputs and affected inputs or outputs is replaced by
another character selected to avoid ambiguity, eg., Greek letters.
7)
If an input or output is affected by more than one affecting input, each identifying number separated by a
comma will appear in the label of the affected one. The normal order of reading these numbers is the
same as the sequence of the affecting relationships.
TOSHIIIA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - , - - - . . , . - - -
AC-26
Fig, 5-1 Example Cor dependency notation
identifying
number
dependency symbol
arrected
output
arre,cting -,--. a
input
L.. b
/.
affecting
affecting
input
a
: /U':::.",d
inpu._ ,
with
dependency symbol
aHected
inputs
'->->--->-..L-
ide n t if yin g
number
d
I
identifying
number
dependency
symbol
(2) Symbols Cor dependency notation
function
AND
OR
svmbol
G
V
Imposes "'" state
Input State "0"
Imposes "0" state
Permits action
Negate
(EX-OR)
N
Complements state
No effect
Interconnection
Control
Set
Reset
Enable
Z
C
S
R
EN
Imposes action
Permits action
S=1, R=O
S=O, R=1
Permits action
Permits action
Prevents action
No effect
No effect
Prevents action of input
Mode
M
Permits action
(mode selected)
Prevents action
(mode not selected)
Address
A
Permits action
(Address selected)
Prevents action
(Address not selected)
Input State "'"
Permits action
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOSHIBA CORPORATION
AC-27
6.
HOW TO READ MIL TYPE LOGIC SYMBOLS AND TRUTH TABLES
6-1
How to read MIL type Logic Symbols
Thble 6-1 shows the MIL type logic symbols used in high-speed CMOS !C. This logic chart is based on
MIL-STD-S06B. Clocked inverters and transmission gate, employ specific symbols.
Table 6-1 MIL Logic Symbols
Logic Symbol
Circuit Function
Logical Equation or Truth Table
Inverter
A-{>-X
A-{>o-X
X=A
NAND Gate
~=C)-X
~::n-X
X=A- B=A+B
NOR Gate
~:::r>-X ~~X
X=A+B=A - B
AND Gate
~
OR Gate
A
B :::::[)- X
~=L)o-
::::[)-X
X=A- B=A+B
B~X
X=A+B=A-S
-f/J
A-{)f-X
f/J
f/J
Transmission Gate
(Note 2)
--
A
f/J
A--{)f-X
----
X
Clocked Inverter
(Note 1)
----
A4x A4x
f/J
f/J
f/J
H
H
L
f/J
H
H
L
A
H
L
X
X
L
H
Z
X:Don't Care
Z:High
Impedance
A
H
L
X
X
H
L
Z
X:Don't Care
Z:High
Impedance
--
EXCLUSIVE-OR
Gate
~:::JL>-x
X=(A +B) - (A +B)
EXCLUSIVE-NOR
Gate
~
X=(A - B)+(A - B)
S
S
D-Type
Flip-Flop
- -
:::n:>-X
n1) ~$~
CK
CKR
Q
Q
CK
KR
Q Q
R
S
H
L
L
L
L
R
L
H
L
L
L
D
X
X
H
L
X
CK
X
X
S
S
t..
Q
H
L X:Don't
Care
H 6:No
L Change
Qn6
~IBA~A~------------------------------------------------
AC-28
Table 6-1 (Cont'd)
Circuit Function
S
s
J/K TYPe
Flip'-Flop
Logical Equation or Truth Table
Logic Symbol
'0· ~o·
CK
K
CK
K R
R
Q Q
CK
K
CK
K R
Q Q
R
S
H
L
L
L
L
L
L
R
L
H
L
L
L
L
L
J
X
X
K
X
X
CK
X
X
L
L
H
H
L
H
L
H
X
X
S
S
S
S
""l
Q
H
L
Qnl'>
L
H
Qn'i7
Qnl'>
X:Don't Care
l'>:No Change
'i7:Toggle
Note 1) Clocked Inverter
A clocked inverter has the circuit shown in Fig. 6-1. In this
fIgure, Ql and Q2 are P-channel MOS FET, and Q3 and Q4
are N-channel MOS FET, and the four FET are connected in
series from Vee to GND.
If", signal. is high, Ql and Q4 tum on, and the circuit can be
regarded as simply an inverter composed of Q2 and Q3.
When'" signal. is low, both Ql and Q4 tum oft; and, regardless
of the condition of the A input, the output, B is set to a high
impedance condition cut off from both Vee and GND.
That is to say, a clocked inverter can be used as a
switch to turn off input and output.
B
Fig. 6-1 Clocked Inverter
Note 2) Transmission Gate
l¢
A transmission gate has the circuit shown in Fig. 6-2. As
Vec
shown, Ql is a P-channel MOS FET and Q2 is an N-channel
I
MOS FET which are connected in parallel.
OUTIIN
If '" signal. is high, both Ql and Q2 tum on, and a signal. can IN/OUT
be applied in either direction.
If '" signal. is low, both Ql and Q2 tum off, and no signal can
¢ GND
be passed.
Fig. 6-2 Transmission Gate
~
TQ2
--------------------~-----------TO.HIBA
AC-29
CORPORATION
6-2 How to Read Truth Table
Thble 6-2 indicates the definition of symbols described in 'Iluth Thble.
Table 6-2
Symbol
H
L
definition
High level (Indicates stationary input or output)
. Low level (Indicates stationary input or output)
S
Indicates leading edge changing from· L· to "H·.
~
Indicates trailing edge changing from" H· to "L •.
X
Don't cate (Either "H" or "L")
Z
High impedance state
a······h
Input level of stationary state of each input of A to H.
Qo
Level of Q just before the realization of input condition indicated in Truth Table.
Qn
Level of Q just before inputting of active edge (
JL
One· H' level pulse.
LJ
One" L" level pulse.
.f
or
1:.)
~~I~ ca~N----------------~----------------------------------------~---
AC-30
7.
COMMON ELECTRICAL CHARACTERISTICS
7-1 Power Disaipation
The power dissipation
or
CMOS device is composed
or
two components: one static, the other
dynamic.
The total power dissipation is the sum or static and dynamic power dissipation.
Static power dissipation is obtained by multiplying quiescent supply current by the supply voltage range
(paragraph 7-1-(1)).
Dynamic power dissipation is obtained as shown in paragraph 7-1-(2).
(1)
Static power dissipation
In the case of CMOS ICs, under the condition in which the inputs are fixed at Vee or GND level, either the
N-channel FET or P-channel FET turns off. For this reason, the. current from Vee to GND becomes only the
reverse-direction saturated current of the PN junction and the surface leakage current due to the strain in
the chip surface, and is a current of less than several nA at room temperature.
Therefore, where the inputs are driven by another CMOS, or the inputs are pulled-down to GND or
pulled-up to Veo the static power dissipation can be obtained as follows:
P d (DC) = V DC • I DC
For ACT devices where specific input pins are driven at TTL levels the following applies:
When being driven with a TTL VOH' ACT devices exhibit additional currents (..6.lee) as specified on ACT
device data sheets.
Therefore, the ACT static power dissipation is dependent on the number of inputs to which TTL VOH logic
voltage levels are applied, and can be obtained as follows:
PdCDC) = Vee' Icc + nVee ·..6. leen' dn
n : the number of inputs at 0-3AV (TTL VIH level)
d : duty cycle
..6. Icc : quiescent current when VIH
=3.4V
(Ref Thchnical data sheets)
---------------------------------------------------------------~~I~ ~~RA"~
AC-31
(2) Dynamic power dissipation
The dynamic power dissipation of aMOS IC is calculated by summing "a" and "b" below:
a) The switching current obtained by charge and discharge of each capacitance added to gate output
current when the gates in the circuit including the output buffer makes an inversion.
b)
The through current flowing when the P-channel FET and the N-channel FET which constitute
the gate during inversion time turn on briefly at the same time.
When rise and fall times of the input signal are small (about 6ns), through current of the gate is
usually negligibly small in comparison with the switching current.
For this reason, the dynamic supply current is governed by internal capacitance of the IC and the
charging and discharging current of the load capacity (C L ).
An example is given here for C L = OpF.
For the inversion of the internal gate outputs from low to high, it is necessary that the electric charge
corresponding to Ci • Vee be supplied from the Vee line to the internal capacitance Ci.
Therefore the value obtained by multiplying Ci • Vee and the output inversion frequency (Frequency = f)
within a certain period corresponds to the mean current to be supplied from the Vee line to the IC during that
period
In an actual Iq however, several gates operate simultaneously, and their respective internal capacity and
inversion frequency are different.
Therefore, dynamic supply current in an IC is as follows:
n
Icc (opr.) = Vcc • I fn • Ci n
I
fn: frequency of internal operated gate
As fn is divisible by an integer of input frequency (fIN)' the gate operating with fn/m frequency can be
considered equivalent to the capacitance of Citm.
Therefore, the above equation can be rewritten as:
n
Icc (opr.) = Vcc • fiN· I Ci/mn
I
fe..; : input frequency
m: integer
The final term is defined as CpO.
~I~ ~~ATftON---------------------------------------------------------------
AC-32
Dynamic power dissipation with load capacity is given by the following equation:
P D (opr.) = Cpo • VCC 2
•
f"., • C PD
Total dynamic power dissipation with load capacity is given by the following equation:
C L : load capacity
f 0 : output frequency
. n : integer of output
However, in specific applications such as crystal oscillators, supply current characteristics are controlled
by through current, and calculation by CpD can not be used.
---------------------------------------------------------------~~I~ca~
AC-33
1-2 Standardized Capacitance Power Dissipation (CPD ) Test Procedure
The purpose of the Cpo value is to allow the user to estimate actual power consumption of his system.
Therefore, the table has been set up to exercise each device in the same manner as it would usually be used
Devices which are separable into independent sections are measured on a "per section" basis, the
remaining are measured on a "per device" basis. Each device~ unique set up is listed in the Thble 7-1, "Cpo
'lest Conditions".
Measurements for all devices are to be made at Vee =5.0V, at Th =25°C and, if the devices are tested at an
high. enough frequency, the DC·supply current will contribute a negligible. amount to the overall power
consumption and can be ignored For this reason, the power consumption is measured at lMHz. Any device
with 3-state outputs is measured in an enabled state.
In order to determine the Cpo of a single section of a device (i.e. one offour gates or one of two fliJrfiops in
a package), the following procedures should be used:
As for the Cpo value for devices with a common clock, it can be easily obtained by measuring both the Cpo
of the device with only one portion of the device active, and the Cpo found with all portions active. The Cpo
value obtained by above two conditions should be shown.
Gates:
Switch one input while biasing the remaining input(s) so that the output(s) will
switch.
Flip-flops:
Switch the clock pin while changing the data pin(s) such that the output(s)
change with each clock cycle.
Latches:
Switch the enable and data inputs such that the latch toggles.
Decoders/
Demultiplexers: Switch one address input which changes two outputs.
Date selectors/
MUltiplexers:
Switch one address input with the corresponding data inputs at opposite logic
levels so that the output switches.
~I~ ~~~-------------------------------------------------------------
AC-34
Analog switches:
Switch one address/select input/output which changes two switches. The switch
inputs/outputs should be left open. For digital applications where the switch inputs/
outputs change between Vee and GND, the respective switch capacitance should be
added to the load capacitance as shown above.
Counters:
Switch the clock with the other inputs biased so that the device counts.
Shift registers:
Switch the clock while alternating the inputs so that the device shifts
alternation l's and O's through the register.
Transceivers:
Switch only one data input. Place transceivers in a single direction.
Monostables:
The pulse obtained with a resistor and no external capacitor is repeatedly
switched.
Parity Generators: Switch one input.
Display Drivers:
Switch one input so that approximately one-half of the outputs change state.
ALVs/ Address:
Switch the least significant bit. Bias the remaining inputs so that the device is
alternately adding OOOO(binary) or 000l(binary) to 1111(binary).
Details of each IC's pin condition are listed in Table 7-1.
-Explanation of symbolV=Vee (+5.0V)
G = GND (0 V)
H= logic 1 (Vee )
L = logic 0 (GND)
X = don't care. Vee or GND. but not switching
R = 1.0 kQ pull-up resistor to an additional5.0V supply other than Vee supply
0= open
P = 50% duty cycle input pulse (shown below)
Q = 50% duty cycle half frequency out-of-phase input pulse (shown below)
Vee
'------'~ND
P
Vee
GND
Input Pulse Waveform
----------.,.------------------,--O------TOaHIBACORPORATlDN
AC-35
" t.
Table 7-1
CPD Test Conditions
Pin
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4
TYPE
NO.
o
00
02
04
08
10
II
14
20
32
74
86
109
112
132
138
139
151
153
157
157
158
158
160
161
162
163
164
166
174
174
175
175
240
241
244
245
251
253
257
257
PHOXXOGOXXOXXV
OPLOXXGXXOXXOV
•
•
POXOXOGOXOXOXV.
PHOXXOGOXXOXXV.
PHXXXOGOXXXOHV·
• •
PHXXXOGOXXXOHV
POXOXOGOXOXOXV.
PHOHHOGOXXOXXV·
PLOXXOGOXXOXXV.
HQPHOOGOOXXXXV.
PLOXXOGOXXOXXV·
•
HHLPHOOGOOXXXXXV·
PHHHOOOGOXXXXXHV·
PHOXXOGOXXOXXV.
P L L L L HOG 0 0 0 0 0 0 0 V •
•
L P L 0 0 0 0 GOO 0 0 X X X V •
XXLHOOLGLLPXXXXV
L LXXLHOGOXXXXPXV·
•
P L H 0 L LOG 0 L .L 0 L L L V
P LHOLHOGOHLOHLLV
P L H 0 L LOG 0 L L 0 L L LV.
PLHOLHOGOHLOHLLV·
•
HPXXXXHGHHOOOOOV.
• •
HPXXXXHGHHOOOOOV.
•
HPXXXXHGHHOOOOOV.
HPXXXXHGHHOOOOOV
QHOOOOGPHOOOOV.
QXXXXLPGHXXXOXHV.
HOQXOXOGPOXOXXOV.
HOQQOQOGPOXOXXOV.
•
HOOQQOOGPOOOOOOV.
•
HOOQQOOGPOOOOOOV.
LPOXOXOXOGXOXOXOXOXV.
•
LPOXOXOXOGXOXOXOXOXV.
LPOXOXOXOGXOXOXOXOXV.
HPXXXXXXXGOOOOOOOOLV.
XXLHOOLGLLPXXXXV
LLXXLHOGOXXXXPXV
•
PLHOXXOGOXXOXXLV
•
PLHOLHOGOHLOHLLV.
I•
6'
1•
4•
4-
·· ·· ·· ·· ·· ·· · ·· ·· ·
·· ·· ·· ·· ·· ·· ·· ·· ··
· ··· ··· ··· ··· ··· ··· ··· ·· ··
·· · · ·· ·· ·· ·· · ··
·· ·· ··· ·· ·· ·· · ·· ·
· · · · · ·· ·· ·
· · ··· ··· ··· ··· ··· ·· ···
· ··· ··· ·· ·· ··· ·· ··
·· · · ·· ··· · · ··
·· ·· ·· · ·· ·· ··
·· ·· · · · ·· ··
·· ·· ·· ·· ·· · ··
· ·· ··· ··· ··· ··· ··· ··· ···
·· ·· ·· · ·· ·· ··
·· ·· ..· ·· ·· · .•.·
·· ·· ·
·· ·· ··
·· · ·· ·· ·· ·· ·· ··
· · ·· ·· ·· ·· ·· ··
~laACOAPOAAngN---------------------------------------------------
AC-36
Pin
TYPE
0 o 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2
1 234 567 8 9 0 123 4 567 8 9 0 1 2 3 4
NO.
258
258
266
273
273
279
299
323
367
368
373
373
374
374
390
393
533
533
534
534
540
540
541
541
563
563
564
564
573
573
574
574
620
623
640
643
646
648
670
·· ·· ·· ·· ·· ·· ·· ··
PLBOXXGXXOOXXV· .
· · · · ·· · · ·
HOQXOOXXOGPOXXOOXXOV
H 0 Q Q 0 0 Q Q 0 GPO Q Q 0 0 Q Q 0 V • · · ·
·· · ·
LPPOXXOGOXXXOXXV·
·
·
·
·
·· ··
HLLOOOOOHGQPOOOOOXLV.
·
HLLOOOOOHGQPOOOOOXLV
· ·· ·· ··
LPOXOXOGOXOXOXLV.
·
·
·
·
L POXOXOGOXOXOXLV.
· · · ·· ·· ·· ··
L OQXOOXXOGPOXXOOXXOV
L OQQOOQQOGPOQQOOQQOV.
L OQXOOXXOGPOXXOOXXOV. · · ·
L o Q Q 0 0 Q Q OG PO Q Q 0 0 Q Q 0 V • · · ·
···
P LOQOOOGOOOXOXXV·
·
·
·
·
·
·· ··
P L 0 0 0 0 GOO 0 0 X X V • .
·
·
·
·
·
·
L OQXOOXXOGGPXXOOXXOV
·· ·· ·· ··
L 0 QQ0 0 QQ0 GG P QQ0 0 QQ0 V
LOQXOOXXOGPOXXOOXXOV
L 0 Q Q 0 0 Q Q 0 GPO Q Q 0 0 Q Q 0 V ·
• ·· ·
· ·· ··
LPXXXXXXXGOOOOOOOOLV
·
·
L P P P P P P P P GOO 0 0 0 000 L V
· · ·· ··
LPXXXXXXXGOOOOOOOOLV· ·
L P P P P P P P P GOO 0 0 0 0 0 0 L V
····
LQXXXXXXXGPOOOOOOOOV
··
·
LQQQQQQQQGPOOOOOOOOV. · ·
·
··
LQXXXXXXXGPOOOOOOOOV
·
·
·
LQQQQQQQQGPOOOOOOOOV · .
· ··
LQXXXXXXXGPOOOOOOOOV
·
·
·· ·
LQQQQQQQQGPOOOOOOOOV
·
·
LQXXXXXXXGPOOOOOOOOV ••
·· ··
LQQQQQQQQGPOOOOOOOOV.
·
HPXXXXXXXGOOOOOOOOHV·
·
HPXXXXXXXGOOOOOOOOHV· · ·
···
P LHOXXOGOXXOXXLV
1•
4' P LHOLHOGOHLOHLLV
1•
8·
1•
8•
1•
8•
1•
8•
1•
8'
1•
8·
1•
8·
1•
8'
1•
8'
1•
81•
8'
· ·· ·· ··
HPXXXXXXXGOOOOOOOOLV
HPXXXXXXXGOOOOOOOOLV·
XLHPXXXXXXXGOOOOOOOOLXXV
XLHPXXXXXXXGOOOOOOOOLXXV
Q Q Q L P 0 0 GOO L L L P Q V •
·······
•
number
of
sections
active
-------------------------TOBHIIIA
AC-37
CORPORATION
7-3 Output Current Characteristics
The output current characteristics of TC74AC series is capable of directly driving 15 FAST, and
guarantees:
V CC -V OH :;>0. 70V. V OL:;>0.44V over the entire temperature range.
Fig. 7-2 shows supply voltage-output current character:stics oC typical device at 25"C.
VOlrVcc(V)
-5
-6
200
Ta =25"C
/'
150
I/
<:
//
s 100
II
.....o
50 II
/1/
IIf/
o
-4
-3
-2
-1
VCC=2V
VCC=5.5V
V-
J
Vee-3\':
r--
VCC=4.5V
-;1
~ /jL
LL
'-'
-l
VCC=3V
r---
V
VCC=2V
-
t-Vee 5.5"
-
234
5
.-/
Vee=4.5V
~
V
6
VI
/
o
-50
<
e
-100 ......
x
0
L
-150
Va -25"C
-200
VadV)
Fig 7-2 Typical Output Current Characteristics
TOtIHIIaA COAPOJIATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-38
7-4 AC
Load capacitance dependence
Fig 7-3 Shows the load capacitance dependance on propagation delay time at supply voltage of 3.0V and
4.5V.
.......
ACOO( Ta=25"C)
rIJ
s::
...1
:t:
Co
10 r-
~o..v
R L =500Q
....
0
t--
:z:
eLI
RL
./
...1
....Co
~.",,,,,.,,,.
Q)
./
........S
~~ ~~
"
, ...
>.
..c
Q)
5
"d
s::
/- " /
~
"
....0
~~~
--
... '
... '
-
Vcc=3.0V
(o.o26ns/ PF)
VCC=4.5V
(o.o2ns/ PF)
- - tpLH
"oj
----tpHL
-
bD
cd
00
I-<
Il<
o
50
Load
Fig. 7-3 Dependence oft pLH and t
100
150
capacity(pF)
pHL
(typical characteristics) to Load Capacitance.
-------~----------~------------
AC-39
TO.HIIIA CORIiIORATION
7-6 Temperature Parameters of Various Characteristics
In TC74AC series, operation over the wide temperature range of -40"C to 85"C is guaranteed. This
section shows how the switching time and output current are influenced by temperature.
(1) Thmperature ~rsus Output Current
Fig. 7-4 indicates temperature versus output current. In this figure, the line shows the temperature
dependence in a standard sample.
140
..
120
61
"""
..
.... r--.,
..... r-...
(~
o
Vee =4.5V
_
IQUI
_10
OUI IOUTCfa=25't)
100
so
20
Vee -4.5V
C L =50pF
120
l:I! pd = tpcP'a=2S 't) x 100
tIld
"&
I'- r-.
300V
>300V
>300V
>300V
>300V
>300V
>-300V
>-300V
>-3OOV
>-300V
>-300V
>300V
>300V
>300V
>300V
>300V
> -3OOV
>300V
>-300V
>-300V
>-300V
>-300V
>-300V
>-300V
8-2 Precautions in Handling
(1)
Transportation and Storage
As the input and output terminals of unmounted CMOS IC's are in a state of high impedance, they are apt
to receive induced charges from the surrounding charged body, space electric fields, and the human body.
For this reason, it is necessary, in transporting and storing CMOS IC's, to use dielectric mats, metal cases
or aluminum foil boxes, so that each terminal of the IC will be at same potential.
The TC74AC series devices are inserted in magazines and are given antistatic treatment at the time of
shipment. Do not remove devices from the magazines unnecessarily. Particularly; avoid the use of plastic or
vinyl containers which are apt to create static charges.
When installing CMOS IC's on the printed wiring board, it is necessary to protect the electric equipment,
work stand and assemblers from static electricity by grounding. It is advisable to ground the work stand by
placing a metal plate or spreading aluminum foil on the surface. Grounding of assemblers should be made
through a resistance of about IMO so as to prevent electric shock. Ground through a metallic ring or wrist
bands. Also, it is advisable not to wear work clothes made of chemical fibers. Further, it is necessary to
periodically check electric equipment to insure absence of electric leakage.
When shaping the leads during the packaging of IC's, it is advisable to use a pincet or similar jig, so that
stress may not be given to the device leads at the package entrance.
When storing or transporting the completely assembled printed wiring board, short circuit the terminals
of printed wiring board of cover the entire board with aluminum foil, so that the input terminals of the IC are
protected.
TOetililA .. cc::HUIOAATlDN - - - - - - - - - - - - - , . . . . - - - - - - - - - - - - - - - - -
AC-42
(3) Soldering
When soldering by use of a soldering iron, carry out the work at temperatures of 260°C or below within 10
seconds. The reliability of the TC74AC series is not affected when subjected to a temperature stress at the
lead of 260°C for 10 seconds.
Use a soldering iron having no electrical leakage at its end. It is recommended to use a class A iron having
an insulation resistance exceeding lOMO. When using a soldering tank, it is necessary to ground the tank so
as to prevent the electric potential of the soldering tank from affecting the work.
After soldering the IC's on the printed wiring board, cleaning is done to remove flux, etc. For this cleaning
use a flux removing solution or a cleaning method utilizing ultrasonic waves. Care must be taken in the
selection of the solvent so as to prevent adverse effects on the package and marking of the CMOS IC's.
In general, it is advisable to use Freon ™ cleaners.
When using ultrasonic cleaning, it is necessary to prevent stress due to signal resonance being imparted
to the IC's or printed wiring board. Because of this, it is necessary to consider a method such that the main
body becomes a shade against vibration, and to use a cleaning time of less than 30 seconds.
When making adjustments and tests after the completion of printed wiring board, it is necessary to check
for solder bridges or cracks on the printed wiring board before applying power. As CMOS systems require
only a small supply current, apply current limiting during tests by using a constant voltage power source.
Before inserting or removing printed wiring boards into or out of the test fixture, remove all power.
When inspecting the printed wiring board with a probe, care must be taken to prevent contact of the tip of
the probe with other signal or power lines. It is advisable to install a special test device for use with probes.
When a test is conducted under high power and low temperature, ensure that the constant temperature
oven is grounded.
Freon TK is a Registered 'frademark of the Dupont Corp.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T O B H I B A CORPORATION
AC-43
9 PRECAUTIONS IN DESIGNING CIRCUITS
9-1
Input Processing
(1)
Processing of unused gates.
Inputs of CMOS IC have such a high impedance that the logic level becomes undefined under open
conditions. If the input is at an intermediate level, the P-channel and N-channel transistors both tum
on, and excessive supply current flows.
Fig. 9-1 Treatment of Input
Therefore, as shown in Fig. 9-1, be sure to connect unused input lines to Vco> GND or other inputs.
In the case of CMOS, if a soldered part makes
poor or no contact, a malfunction of the system or
an increase in supply current can occur. Therefore,
care must be taken at the time of soldering.
(2)
Input processing of printed wiring boards.
C*Unused gate)
GND
When an input terminal of a printed wiring board
is connected directly to a CMOS input, that input
electrically floats. This condition is the same as a
single IC being transported or stored. It is advisable,
therefore, to connect thio;; input to Vcc or GND
through a resistance on the printed wiring board, as
shown in Fig. 9-2.
R: == lOOk Q
Fig. 9-2 Input processing
of Printed Wiring Board
TCNSHI~ ca~~~---------------------------------------------------------------
AC-44
8-2 Design of Power Source
In general, CMOS has a very small current consumption in comparison with bipolar digital IC's and,
therefore, it needs only a small capacity power supply. However, from the operational standpoint,
CMOS consumes power in the transition state. Therefore, it is necessary to keep the high frequency
impedance of the power source as low as possible.
It is advisable to make the wiring of the power source 01cd and GND lines thick and short, and
insert, as a high frequency filter, a 0.001 j.l.F to 0.1 JJ.F capacitor between Vcc and GND for each IC.
Also, it is recommended that a capacitor of about 10 j.l.F to 100 jJ.F be inserted between the power
supply entrance and GND as a low frequency filter. As mean supply current differs considerably
depending upon the operating frequency of the system, existence of capacitive load, rise and fall of the
input signal and supply voltage, attention must be given especially in the case of a simple power
source, by using a Zener diode or by battery drive. When there is overshoot or undershoot during the
transition time of the power supply use a filter, etc. so that the maximum device rating is not exceeded.
9-3 Output Short Circuit
In the TC74AC series, a buffer is added to the output, and both outflow (lOH) and inflow (loJ
current drive is possible. For this reason, excessive current flows in the CMOS output when the high
level output line is shorted to GND or the low level output line is shorted to Vcc' Particularly, when the
supply voltage is high, 10H and 10L are quite excessive and may damage the device; therefore care must
be taken not to cause an output short circuit.
It is, of course, impossible to directly connect ordinary outputs together. But in the case
of an IC which has a 3-state output, a wired OR
connection is permitted provided that no more
than two outputs are enabled simultaneously.
Fig. 9-3 Example of how to
increase drive capacity
---------------------------------------------------------------~~ ca~RA~
AC-45
9-4 Effect on Input of Slow Rise and Fall Time
When a slow rise or fall time signal is impressed on a
CMOS input, it sometimes happens that the output
tends to oscillate around VTH (threshold voltage of
device). This is because the CMOS gate becomes a
linear amplifier equivalent in the vicinity of VTH> and
minute power source ripple and noise components
are amplified and appear in the output.
Th prevent this, it is necessary to insert a high
frequency ffiter capacitor between Vee and GND of
the oscillating 10 or use a Schmitt trigger IC.
In the case of an TC74AC series, excepting
Schmitt trigger lCs, the input rise and fall time is
limited as shown in Thble 9-1.
Proper design requires that these rise and fall
time limits be observed.
F/F-2
I----ID
CK2
CLOC~K~*-
Q2
ih
_ _ _ _ _~
Q 2 - - - -.....
(a) Normal operating waveform
QI
Fig. 9-4 shows an example of a maJfunction when
a shift counter is designed by using a D-type flipflop in separate packages. In this case, the maJfunction is considered to be caused by the difference in
circuit threshold level of separate D-type flip flops.
Q2~1L-_ _
(b)
Malfunction waveform from
at the time Vth Cl)Vth C2
Ie) Malfunction waveform from
at the time Vth Cl(Vth C2
Fig ..9-4 Example of Malfunction
Let circuit threshold level of FIF-1 be Vth Cl, and that of F IF-2 be Vth C2. Then, as shown in Fig.
9-4, time difference t.t is formed when the rising waveform of the clock pulse cuts the respective
circuit threshold voltage, and thus a malfunction occurs.
The following condition is required for ensuring normal operation:
~t
< tpd (CK-Q)+tset-up
~laA~-------------------------------------------------~
AC-46
In this case, there is a possibility of malfunction even though the input signal is within the standard
value of Table 9-1. Therefore, care must be taken in design of sequence circuit clock inputs.
Table 9-1 Standard Value of Input Rise and Fall Time
(l) 74AC TYPE
Symbol
Item
Limit
Unit
0-100(Vcc =3.3±0.3V)
Input Rise and Fall Tim.
dtldv
0- 2O(VCC =
5±0.5V)
ns/V
(2) 74ACT TYPE
Item
Symbol
Input Rise and Fall Time
dtldv
Limit
0- 10(Vcc =
Unit
5±0.5V)
ns/V
9-5 Wiring Precautions
As the output impedance of the TC74AC series is very low in comparison with the conventional
standard CMOS Iq distortion is sometimes caused in the output waveform depending upon the L
component of the wiring, long output wiring or when capacitance is connected between signal lines
and Vcc or GND. Therefore, when designing the printed wiring board, take care not to make signal
wiring too long. In the case of double sided printed wiring boards, it is ideal to limit signal wire length to
aDem or less. The clock signal line is particularly prone to distortiolL
(2) Precautions for parts arrangement
The output of TC74AC series has a fast rise and fall time, and makes a full swing between Vco and
GND. Therefore it becomes a noise source to other signals. It is necessary to locate the output away
from a part which is sensitive to the noise of an analog circuit. Also, care must be taken for the
reduction of the number of loads and wiring lengths.
From its physical and electrical characteristics, the TC74AC series is apt to cause some overshoot
and undershoot, and this can lead to malfunction of the circuit or breakdown of passive IC's. These
troubles can be prevented to some extent by terminating the ends of signal lines. Fig. 9-5 indicates
examples of termination methods.
(a) Termination by CR
(b)
Termination by Diode
Fig. 9-5 Examples of Termination
_______________________________________________________________
AC-47
~I~
~~N
9-6 Interface
When interconnecting a CMOS system, an exchange of signals with external circuits or mechanisms
is usually done. These input and output signal Jines are made long in many cases, and have distributed
inductance and/or reactance. Therefore, if directly connected to CMOS, they can give rise to various
problems.
Conceivable problems can include a malfunction due to induced noise, and the destruction of the
input/output elements due to surge. Th cope with these problems, reduction of signal line impedance
(driving impedance) or insertion of a noise eliminating circuit on the receiving side is done for the
former problem, while surge protective measures are taken for the latter.
Fig. 9-6 illustrates examples of providing noise and surge protection on the input side.
Ca) and (b) show examples of absorbing noise by integrating the input waveform.
Cc) and Cd) are examples of protecting CMOS from input surge.
I
~
I r
I
(a) Noise Killer 1
(b) Noise Killer 2
(c) Surge Protection 1
(d) Surge Protection 2
Fig. 9-6 CMOS Input Protective Circuits
~I~ ~~~N---------------------------------------------------------------
AC-48
(4)
Interface with CPU
At present, 74F series TTL is used universally as the peripheral supporting logic for MOS microprocessors. Since the TC74AC series has the same speed as 74F, it can be used as microprocessor peripheral
logic. As an interface with a CMOS CPU there is no problem since both are CMOS. At present, however, the
use of NMOS CPU is greater, and the interface of NMOS to CMOS must be taken into consideration.
The output of most NMOS CPU\; rises to near Vco but as shown in Fig. 9-10, as outputs of both driving
MOS and load MOS are enhancement type, no switching takes place until near Vee. In order to carry out the
signal transfer from the NMOS CPU to the 74Aq use the 74ACT series which has a TTL level input. When
connecting the 74AC series, a pull up resistor is required as shown in Fig. 9-10.
Driving an NMOS CPU from the 74AC series can be done without difficulty. The input of NMOS is high
impedance like CMOS, and the DC fanout need not be taken into consideration.
Vee
Rp =Pull up Resistor
----1
----1
--NMOS CPU
Fig. 9-10 NMOS CPU Interface
--------------------------------TCIIIHIBA CORPORATION
AC-51
9-7 Latch-up
Latch-up is a phenomenon peculiar to CMOS, and is also called SCR (Silicon Controlled Rectifier)
Phenomenon. During the normal operation, if excessive voltage and current caused by high noise or
accidental surge is applied to the input or output terminal, or a supply source suddenly fluctuates, abnormal
current flows between Vee and GND, and this current continues to flow even though the disturbing signal is
cut ort; and, finally, damage is caused Latch-up is the name given to this phenomenon.
Once latch-up takes place, the original condition is not restored unless the power supply is cut off
(1)
Cause of latch-up
Fig. 9-11 shows as equivalent circuit with the parasitic element. NPN transistor Q2 is formed in the P-well
of NMOS side while PNP transistor Q1 is formed in the N-substrate of PMOS side, and a parasitic resistor
exists between the terminals. As shown from the current path through the medium of the parasitic element,
these parasitic elements constitute a Thyristor.
OUT
IN
VSSo--""1""""_""
R
N -Substrate
Fig. 9-11 Internal Equivalent Circuit of CMOS Ie
TDIIHIIIA COAJtORATICtN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-52
Fig. 9-7 gives examples of an output interface. There are other methods, but in any case, some
protection scheme should be provided to an interface involving long signal lines.
Vee
I
-t»--fi
(al Surge Protection
(blOutput Driver 1
VCC
I
r}-
~ 4i
i
i
(clOutput Driver 2
(dl Surge Protection 2
Fig. 9-7 Outpu t Protection/ Driving Circuits
(2) Interface between CMOS ICB
When CMOS IC's are interfaced, the input impedance is so large that the limitation of fanout may not
be so important. However, there is a need to consider the increase in propagation delay time due to the
adding effect of load capacitance and an increase in power consumption.
Input capacitance of CMOS is about 5pF per input. If 10 fan outs are taken, for example, the load
capacitance is 50pF. Further, the line capacitance of the printed wiring board must also be taken into
consideration. This shows that the processing speed of system is controlled not only by the circuit IC's
but also by fanout.
When constructing a system with CMOS Iq the designer must examine the fanout and take these
points into consideration.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T Q I I H I I I A CORPORATION
AC-49
(3) Interface with TTL
When driving TTL with the TC74AC series, input and output voltage levels can be connected
without trouble. Fanout is determined by the output current of CMOS IC and input current of the TTL.
An example is shown in Fig. 9--8.
Fig. 9-8 TC74AC ... TTL Interface
On the other hand, when driving TC74AC series with TTL, it is necessary to convert the output
voltage level of the TTL to the input level of the 74AC. Normally, TC74ACT series devices which have
same input level as FAST are used. The input current of TC74ACT series is very low like that of
TC74AC series, and no burden is imposed on the driving side 74F. Additionally, the speed falls very .
little. Therefore, it can be said to be an effective method. Another method is to use a pull up resistor as
shown in Fig. 9-9.
Vee
Rp=Pull up Resistor
TTL
HAC
(2-10KQ)
Fig. 9-9 TTL ... 74AC Interface
TOBHIIIA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-50
For example, if current flows into the N-substrate from external sources, a voltage drop takes place in the
resistor Rs of the N-substrate, and this turns on parasitic transistor QI' and current flows towards GND
from Vee through the medium of resistor Rw in the P-Well. When current flows in RW; a voltage drop takes
place at both ends of RW; Q2 turns on, and further supply current flows through Rs. As a result, the voltage
drop at both ends of Rs further increases, Q 1 and Q2 are left in the turn-on state, and the supply current
continues to increase.
In this way, if the voltage drop takes place in resistance Rw in the P-Well and in resistance RS in the Nsubstrate, latch-Up occurs, and the following events occur:
1) Input voltage goes higher than Vee
(Q6 turns on)
2)
+ VF
Input voltage goes lower than GND - VF
(Q6 turns on)
3) Output voltage goes higher than Vee
(Qa turns on)
+ VF
4) Output voltage goes lower than GND - VF
(Q4 turns on)
5) This raises supply voltage Vee above the rated value causeing breakdown.
(Directly forces current in Rw or Rs)
Here, VF is the forward voltage between base and emitter of parasitic bipolar transistor Q3 - Q4'
Fig. 9-12 illustrates a measurement example of latch-up strength. As indicated in Fig. 9-12, latch-up is
induced by forcing current into input terminal (+ injection) or forcing current out of output terminal
(- injection), and the current value at that time is measured.
--------------------------------TOIIHIBA
AC-53
CORPORATION
ICC
(a) Measurement circuit for +
Injection strength of Input
Terminal
(b) Measurement circuit for Injection strength of Input
Terminal
• : Input condition to make measured terminal high level
•• : Input condition to make measured terminal low level
-
--rcc
(c) Measurement circuit for +
Injection strength of Output
Terminal
(d) Measurement circuit for Injection strength of Output
Terminal
Fig. 9-12 Latch up Strength Measurement Circuits by Current Feeding
(3) Countermeasures
As ample margin is provided against latch-up, there is no problem in using the device within the
specifications. However, since the part has the possibility of receiving excessive current surge, it is
recommended that a protective circuit be added. Fig. 9-13 contains examples.
R
~~--II/O
R
o---+---l II 0
Fig. 9-13 Example of Latch up Prevention Methods
TaIIHI~ CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC·54
10.
DATA SHEETS
TC74AC/ACT SERIES
TC74ACOOP/F/FN
QUAD
2-INPUT
NAND
GATE
The TC74ACOO is an advanced high speed CMOS 2-INPUT
NAND GATE fabricated with silicon gate and double-layer
metal wiring C' MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit is composed of 3 stages including
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP14-P-300)
,.~ 14~
1
F(SOP14-P-300)
FEATURES:
• High Speed ................................. tp d=3.8ns (typ.) at Voc=SV
• Low Power Dissipation ............... Ioc=4IlA(Max.) at Ta=2S"C
;, High Noise Immunity··············· VNIH=VNIL =2816 Voc(Min.)
• Symmetrical Output Impedance ···1 fa; 1=Ia. =24mA(Min.)
Capability of driving SOQ
transmission lines.
• Balanced Propagation Delays ...... tpLH"TtpHL
• Wide Operating Voltage Range ... Voc (opr)=2V-5.5V
• Pin and Function Compatible with 74FOO
PIN
FN(SOL 14-P-150)
ASSIGNMENT
1A 1
1B 2
1Y 3
2A 4
28 5
14 Vee
13 4B
12 4A
4Y
10 3B
11
2Y 6
9
7
8
GND
3A
3Y
(TOP VIEW)
IEC
LOGIC
SYMBOL
lA
18
2A
28
3A
38
4A
48
TRUTH
lY
2Y
3Y
4Y
TABLE
A
B
Y
L
L
H
L
H
H
H
L
H
H
H
L
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TOSHIIIA CORPORATION
AC-57
TC74ACOOP/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage,
Input Diode Current
Output Diode Current
DC Output Current
DC Voc/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
VALUE
-0.5 -6.0
-0.5 -Voc+0.5
-O·S -Voc+0.5
±20
±50
±50
±100
500(DIP)*1l80(SOP)
-65 -150
300
Voc
Y'N
Voor
1'K
10K
loor
loc
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
SYMBOL
VALUE
2.0-5.5
0- Voc
o -Voc
-40 - 85
Voc
Y'N
Voor
Topr
dt/dv
o-
UNIT
'V
V
V
"C
lOO(Voc =3.3±0.3V)
ns/v
0- 20(Voc= 5 ±0.5V)
CHARACTERISTICS
r--
PARAMETER
SYMBOL
High-Level
Input Voltage
V,H
Low-Level
Input V.oltage
V,L
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
1,:\
loc
Ta=-40-85"C
Ta=25"C
Vcr: MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
5.5 3.85
3.85
2.0
0.50
0.50
V
0.90
3.0
0.90
5.5
1. 65
1. 65
2.0
1.9
2.0
1.9
2.9
3.0
IOH=-50UA
3.0
2.9
V,N =
4.4
4.5
4.5
4.4
V
3.0
2.48
2.58
IOH=-4mA
V,Hor V1L
3.80
IOH=-24mA
4.5 3.94
3.85
IOH=-75mA* 5.5
0.0
0.1
0.1
2.0
0;1
0.1
3.0
0.0
IOL=50U A
0.0
0.1
4.5
0.1
V
V,N=V,H
3.0
0.44
0.36
IOL=12mA
0.36
4.5
0.44
IOL=24mA
5.5
1. 65
IOL =75mA*
- ±O.l - ±1.0
5.5
Y,N =Vcr: or GND
UA
4.0
40.0
Y,N =VOC or GND
5.5
TEST CONDITION
• :This spec indicates the capability of driving 50n transmission lines,
One output should be tested at a time for a lOms maximum duration,
TOSHIBA' CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-58
TC74ACOOP I FI FN
AC ELECTRICAL CHARACTERISTICS(C L=60pF. RL =6000. Input t r =tf=3ns)
Ta-25"C
Ta- 40 -85"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
MIN. TYP. MAX. MIN. MAx.
Va;
Propagation Delay Time
Input Capacitance
t pI..!l
t pilL
3.3±0.3
5.0±0.5
CIN
-
6.6
4.9
11. 2
7.0
1.0
1.0
12.9
8.0
ns
-
5
10
-
10
pF
Power Dissipation Capacitance CPDOl
68
Note (1) C I'D is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
la;(llO=C I'D· Va;. f I" +1 a; 14(per Gate)
---------------------------------------------------------------~I~ ~
AC-59
TC74ACTOOP I FI FN
QUAD 2-INPUT
NAND GATE
The TC74ACTOO is an advanced high speed CMOS 2-INPUT
NAND GATE Cabricated with silicon gate and double-layer
metal wiring C· MOS technology.
It achieves the high speed operation. similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
This device may be used as a level converter Cor
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. \:Pd =4.0ns (typ.) at Vee =5V
• Low Power Dissipation ............... Icc=4/.lA(Max.) at Ta=25"C
• Compatible with TTL outputs ...... VII. =O.8V (Max.)
V IH =2.0V (Min.)
• Symmetrical Output Impedance ... IlOB I=IoL =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLB"'tpHL
• Pin and Function Compatible with 74FOO
1
P(DIP14-P-300)
FN(SOL 14-P-150)
F(SOP14-P-300)
PIN
ASSIGNMENT
1A
1
1B
2
13
48
1Y
3
12
4A
14 Vee
2A
4
11
4Y
2B
5
10
38
2Y
6
9
3A
GND
7
8
3Y
(TOP VIEW)
IEC
LOGIC SYMBOL
lA
18
2A
28
3A
38
4A
48
TRUTH
lY
2:'f
3Y
4Y
TABLE
A
8
Y
L
L
H
L
H
H
H
L
H
H
H
L
TOBHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-60
TC74AC02P/F/FN
QUAD 2-INPUT NOR GATE
The TC74AC02 is an advanced high speed CMOS 2INPUT NOR GATE fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit is composed oC 3 stages. including a
buffer output. which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P( 01 P14-P-300)
,.~ ,.~
1
F(SOP14-P-300)
FEATURES:
• High Speed ................................. tpd=3.7ns (typ.) at Vcc=SV
• Low Power Dissipation ............... Icc=4I1A(Max.} at Ta=2S"C
• High Noise Immunity .............. · VNIH=VNIL=28% Vcc(Min.}
• Symmetrical Output Impedance ..·Ilai I =Ia..=24mA(Min.}
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpHL
• Wide Operating Voltage Range .. · Vcc (opr}=2V-S.SV
• Pin and Function Compatible with 74F 02
FN(SOL 14-P-150)
PIN ASSIGNMENT
1Y
lA
1B
2Y
2A
2B
GND
14 Vee
13 4Y
12 4B
11 4A
10 3Y
9 3B
8 3A
2
3
4
5
6
7
(TOP VIEW)
IEC LOGIC SYMBOL
lA
18
2A
28
3A
38
4A
48
TRUTH TABLE
lY
B
Y
L
L
H
L
H
L
A
2Y
3Y
H
L
L
4Y
H
H
L
---------------------------------------------------------------TCJa.4I~ ~~ArHON
AC-63
TC74AC02P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
Voor
11K
10K
lour
lee
PD
Tstg
TL
VALUE
-0.5-6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±IOO
500(DIP)*/180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-IOmW/"C shall be applied
unti1300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
SYMBOL
dt/dv
UNIT
V
V
V
"C
VALUE
2.0-5.5
o -Vee
0- Vee
-40 - 85
Vee
VIN
Voor
Topr
0- 100(Vee =3.3±O.3V)
ns/v
0- 20(Vee= 5 ±0.5V)
CHARACTERISTICS
;---
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
Ta=25"C
Ta=-40-85"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
5.5 3.85
3.85
0.50
2.0
0.50
V
3.0
0.90
0.90
5.5
1. 65
1. 65
2.0
1.9
2.0
1.9
3.0 2.9
3.0
2.9
1ai=-50f.lA
4.5
4.4
4.5
4.4
V
VIN = V IL
2.58
3.0
2.48
Irn=-4mA
Irn=-24mA 4.5 3.94
3.80
3.85
1ai=-75mA* 5.5
0.0
0.1
2.0
0.1
3.0
0.0
0.1
0.1
Ia..= 50f.lA
VIN=
4.5
0.0
0.1
0.1
V
3.0
0.36
0.44
IoL =12mA
VIHor VIL
4.5
0.36
0.44
Ia..=24mA
5.5
1. 65
1a..=75mA*
- ±O.l
5.5
±1.0
VIN =Vee or GND
f.lA
VIN =Vee or GND
5.5
4.0
40.0
TEST CONDITION
-
-
-
High-Level
Output Voltage
Vrn
-
-
Low-Level
Output Voltage
Va..
Input Leakage Current
Quiescent Supply Current
liN
lee
-
-
-
-
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time, for a 10ms maximum duration.
TOIIHIIIA COI=IPOAATION - - - - - - - - - - - - - - - - - - - - - - - - - - - , . - - - -
AC-64
TC74ACTOOP I FI FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
VOIJI'
11K
10K
lour
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vee
Input Voltage
VIN
Output Voltage
Vour
Operating Temperature
Topr
Input Rise and Fall Time dtldv
DC
ELECTRICAL
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
Low-Level
Output Voltage
Input Leakage Current
Quiescent Supply Current
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
PARAMETER
High-Level
Output Voltage
VALUE
4.5-5.5
0- Vee
0- Vee
-40 - 85
0-10
TEST CONDITION
Irn=-50 f,tA
Irn=-24mA
Irn=-75mA*
ioL=50 ttA
VQL
IQL=24mA
VIN = VIH
IQL=75mA*
lIN
VIN =Vee or GND
lee
VIN =Vee or GND
PER INPUT:VIN -3.4V
boIce OTHER INPUT:Vee or GND
Voo
\liN =
VIHor VIL
-
Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
2.0
2.0
l
5.5
4.5
V
0.8
0.8
l
5.5
4.5
4.4
4.5 4.4
V
4.5 3.94
3.80
3.85
5.5
0.0
4.5
0.1
0.1
V
4.5
0.44
0.36
5.5
1. 65
- ±O.l - ±l.0
5.5
tt A
4.0
40.0
5.5
-
5.5
-
-
1.35
-
1.5
rnA
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a 10ms maximum duration.
____________________________________________________________
AC-61
~laA
ca~~CNM
:TC74ACTOOP I FI FN
AC ELECTRICAL CHARACTERISTICS(CL=60pF, RL =6000, Input tr=tf =3ns)
Ta-25"C
Ta--40 -85"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
MIN. TYP. MAX. MIN. MAX.
Va;
Propagation Delay Time
t
t
pLH
pl-lL
5.0±O.S
-
4.7
7.9
1.0
9.5
ns
Input Capacitance
5
CIN
10
10
pF'
Power Dissipation Capacitance cpom
23
Note (1) C PO is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
la;wo=C po. Va::. r IN +1 a:: 14(per Gate)
-
-
~IBAca~------------------~----------------------------------------
AC-62
TC74AC02P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L=60pF, RL =6000, Input t r =tf=3ns)
Ta-25"C
Ta--40 -85"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
MIN. TYP. MAX. MIN. MAX.
Vex
Propagation Delay Time
t pLl-I
t pI-IL
3.3±O.3
5.0±0.5
-
6.1
4.8
9.8
7.0
-
11.2
8.0
ns
Input Capacitance
5
CIN
10
10
pF
Power Dissipation Capacitance CPD(l)
82
Note(1) CPD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IextpO=C PD· VOC· f IN+I OC 14(per Gate)
--------------------------------TOaHIBA
AC-65
CORPORATION
TC74ACT02P/F/FN
QUAD 2-INPUT NOR GATE
The TC74ACT02 is an advanced high speed CMOS 2INPUT NOR GATE fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
This device may be used as a level converter for interfacing TTL or
NMOS to High Speed CMOS. The inputs are compatible with TTL,
NMOS and CMOS output voltage levels.
.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP14-P-300)
14Q
14~
1
F(SOP14-P-300)
FN(S0L14-P-150)
PIN ASSIGNMENT
FEATURES:
• High Speed .............................. '" ~ =4.6ns (typ.) at Vee = 5V
• Low Power Dissipation ............... Icc=4IlA(Max.) at Ta=25"C
• Compatible with TTL outputs ...... V1L =0.8V(Max.)
V1H =2V(Min.)
• Symmetrical Output Impedance ···1 1m I =1 OL =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpUi" tpHL
• Pin and Function Compatible with 74F 02
1Y
1A 2
14 Vee
13 4Y
18 3
2Y 4
2A 5
12 48
11 4A
10 3Y
28 6
9
7
8
GND
38
3A
(TOP VIEW)
IEC LOGIC SYMBOL
lA
lB
2A
2B
3A
3B
4A
4B
TRUTH TABLE
IY
2Y
A
B
Y
L
L
H
l
H
l
3Y
H
L
L
4Y
H
H
l
TCMIHIBACOA~~------------------------------------------------------------
AC·66
TC74ACT02P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Va;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Va;
VIN
VOUT
11K
10K
lOUT
Ia;
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Va; +0.5
-0.5 -V(:c+0.5
±20
±50
±50
±100
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmWI'C shall be applied
unti1300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Va;
Input Voltage
VIN
Output Voltage
VOUT
Operating Temperature
Topr
Input Rise and Fall Time dt/dv
DC
ELECTRICAL
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Va-!
Low-Level
Output Voltage
Vex..
Quiescent Supply Current
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
PARAMETER
Input Leakage Current
VALUE
4.5-5.5
o -Va;
0- Va;
-40 - 85
0-10
lIN
Ia;
..0.Icc
TEST CONDITION
100=-50 Il A
loo=-24mA
loo=-75mA*
Ja..=50p,A
VIN =
Ja..=24mA
VIIi or VIL
Iex..=75mA*
VIN =Va; or GND
VIN =Va; or GND
PER INPUT:VIN -3.4V
OTHER INPUT:Va; or GND
ViN=VIL
-
Ta=-40-85"C
Ta=25"C
Va; MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
2.0
2.0
l
5.5
4.5
V
0.8
0.8
l
5.5
4.5 4.4
4.4
4.5
V
3.80
4.5 3.94
5.5
3.85
4.5
0.0
O. 1
O. I
V
0.44
0.36
4.5
5.5
1. 65
±O.l
±1.0
5.5
p,A
5.5
4.0
40.0
5.5
-
-
1.35
-
1.5
rnA
• :This spec indicates the capability of driving 50n transmission lines.
One output should be tested at a time for a 10ms maximum duration.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T O S H I B A CORPORATION
AC-67
TC74ACT02P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L=50pF, RL =5000, Input t r =t,=3ns)
Ta--40 -85"C
Ta-25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
MIN. TYP. MAX. MIN. MAX.
Vcc
Propagation Delay Time
t pl.H
t pllL
5.0±0.5
-
5.3
8.3
1.0
9.5
ns
Input Capacitance
CIN
5
10
10
pF
Power Dissipation Capacitance CPDW
22
Note (1) C A) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCwo=C PD· Voc· fIN+I OC/4(per Gate)
~uaA~~CUM------------------------------------------------------------
AC-68
TC74AC04P/F/FN
HEX INVERTER
The TC74AC04 is an advanced high speed CMOS INVERTER
fabricated with silicon gate and double-layer metal wiring
C' MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit is composed of 3 stages including
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP14-P-300)
14~ 14~
1
F(SOP14-P-300)
FEATURES:
• High Speed ................................. tpd=3.2ns (typ.) at Vc:c=5V
• Low Power Dissipation ............... Ic:c=4 Jl A(Max.) at Ta=25"C
• High Noise Immunity··············· V \lH = VNIL =2896 Vc:c (Min.)
• Symmetrical Output Impedance ···1 Ia-r 1=1 a. =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpUi" tpHL
• Wide Operating Voltage Range ... Vc:c(opr)=2V-5.5V
• Pin and Function Compatible with 74F04
PIN
FN(SOL 14-P-150)
ASSIGNMENT
1A
Vee
13 6A
12 6Y
11 5A
10 5Y
9 4A
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND
8
7
4Y
(TOP VIEW)
IEC
LOGIC
SYMBOL
TRUTH
lA
lY
2A
3A
2Y
3Y
TABLE
A
Y
4A
4Y
L
H
SA
SY
H
L
6A
6Y
____________________
~
_ _ _ _ _ _ _ _ _ _ _ TOSHIBA CORPORATION
AC-69
TC74AC04P IFI FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Currerit
Output Diode Current
DC Output Current
DC Vc.:c/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
Vee
VI;\;
VOlJT
11K
10K
IOLT
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee +0.5
-0.5 - Vee+0.5
±20
±50
±50
±150
500(DIP )*/180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
°C
"C
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vee
o -Vee
-40 - 85
SYMBOL
Vee
VI'.;
VOLT
Topr
dt/dv
UNIT
V
V
V
"C
0- 100(Vcc =3.3±O.3V)
o -20(Vcc=
5 ±O.5V)
ns/v
CHARACTERISTICS
r--
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VII.
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
liN
lee
Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
5.5 3.85
3.85
2.0
0.50
0.50
V
3.0
0.90
0.90
5.5
1. 65
1. 65
2.0
2.0
1.9
1.9
3.0
2.9
3.0
2.9
IOIi= -50ttA
4.5
4.4
4.5
4.4
V
Ve,=VIL
3.0 2.58
2.48
Im=-4mA
3.80
Ia-l=-24mA 4.5 3.94
3.85
IaJ=-75mA* 5.5
0.0
0.1
2.0
O. I
-3.0
0.0
0.1
0.1
IOL=50tt A
O. 1
0.1
4.5
0.0
V
VI!,:=VUi
0.36
0.44
3.0
IOI.=12mA
4.5
0.44
0.36
IOL =24mA
5.5
1. 65
IOI.=75mA*
±O.l
5.5
±1.0
VI!': =Vee or GND
I1A
4.0
40.0
5.5
VI'.; =Vcc or GND
TEST CONDITION
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a lOms maximum duration.
TOSHIBA CO.APOAATION - - - - - - - - - - - - . , - - - - - - - - - - - - - - - - - -
AC-70
TC74AC04P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L=50pF. RL =5000, Input t r =tf=3ns)
Ta-25"C
Ta- 40 -85"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
MIN. TYP. MAX. MIN. MAX.
Vcx
Propagation Delay Time
t pLH
t pilL
3.3±0.3
5.0±0.5
-
6.3
4.3
15.0
6.6
1.0
1.0
17.3
7.5
ns
Input Capacitance
CII,
5
10
10
pF
Power Dissipation Capacitance CPOOl
20
Note(l) Cm is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lcx(W=C po. Vcr:,. r Il>: +1 cr:, 16(per Gate)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T O I I H I I I A CORPORAnON
AC-71
TC74ACT04P I FI FN
HEX INVERTER
The TC74ACT04 is an advanced high speed CMOS
INVERTER fabricated with silicon gate and double-layer
metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
This device may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP14-P-300)
14~ 14~
1
F(SOP14-P-300)
FEATURES:
• High Speed ................................. tpd=4.6ns (typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=4/.l A (Max.) at Ta=25"C
• Compatible with TTL outputs ............... VIL =0.8V (Max.)
VIH =2V (Min.)
• Symmetrical Output Impedance ... 1Ia; 1=1 OL=24mA(Min.)
Capability of driving SOQ
transmission lines.
• Balanced Propagation Delays ...... t pLH " tpi-lL
• Pin and Function Compatible with 74F 04
FN(SOL 14-P-150)
PIN ASSIGNMENT
1A
1Y
2A
2Y
3A
3Y
14
2
3
4
5
6
Vee
6A
6Y
11 5A
10 5Y
9 4A
8 4Y
GND
(TOP VIEW)
IEC LOGIC SYMBOL
TRUTH TABLE
IA
IY
2A
2Y
3A
3Y
4A
SA
SA
4Y
SY
6Y
A
y
L
H
H
L
TOSHIIlA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Ae-72
TC74AC05P/F/FN
HEX
INVERTER(OPEN
DRAIN)
The TC74AC05 is an advanced high speed CMOS INVERTER
fabricated with silicon gate and double-layer metal wiring
C· MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
Pin configurathion and function are the same as the TC
74AC04, but the TC74AC05 has high performance MOS Nchannel transistor( OPEN - DRAIN) outputs.
This device can, therfore, with a suitable pull-up rsistors,
be used in wired-OR, LED drive and other applications.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpz=3.4ns (typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=4#A(Max.) at Ta=25"C
• High Noise Immunity ..............• VN\H=VNIL =28~ Vcc(Min.}
• Symmetrical Output Impedance ... Ia. =24mA(Min.)
Capability of driving 50g
transmission lines.
• Wide Operating Voltage Range ..• Vcc(opr)=2V-5.5V
• Open Drain Structure.
• Pin and Function Compatible with 74F05
SYSTEM
DIAGRAM(per gate)
f
cc
1
P(0IP14-P-300)
F(SOP14-P-300)
PIN
FN(SOL 14-P-150)
ASSIGNMENT
1A
1Y
2A
2Y
3A
3Y
2
3
4
5
6
ONO
7
14 Vee
13 6A
12 6Y
11 SA
10 5Y
9 4A
8 4Y
Y
(TOP VIEW)
A 0-0--I[>o>O--->----I1
TRUTH
TABLE
IEC LOGIC SYMBOL
111
1Y
2A
3A
'Zf
3Y
411
4Y
SA
5Y
&II
6Y
A
Y
L
Z
H
L
Z:Hlgh Impedance
----------------------------------------------------------TDaHI~Ca~AA~N
AC-75
TC74AC05P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
Vcc
VIN
VOL.,.
11K
Ia<
Ioor
Icc
Po
Tstr
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
VALUE
-0.5-6.0
-0.5 -Vcc+0.5
-0.5 -Vee+0.5
±20
±50
+50
±150
500(DIP)./180(SOP)
-65 -150
300
.500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating ractor of
-lOmW/"Cahould be applied
up to300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
SYMBOL
Vee
VIN
Voor
Topr
dt/dv
UNIT
V
V
V
"C
VALUE
2.0-5.5
O-Vee
o-Vee
-40 - 85
o-lOO(Vee =3.3±0.3V)
0- 20(Vee=
na/v
5±0.5V)
CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
Low-Level
Output Voltage
Va..
TEST CONDITION
VIN =
VIH or VIL
3;"'State Output
orr-State Current
Ice
Input Leakage Current
Quiescent Su ppiy Current
lIN
lee
Ia..= 50llA
Ia.=12mA
Ia..=24mA
Ia..=75mA.
VIN = VIH or VIL
Voor =Veeor GND
VIN =Vee or GND
VIN =Vee or GND
r-Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. tJNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
5.5 3.85
3.85
2.0
0.50
0.50
V
3.0
0.90
0.90
5.5
1. 65
1.65
2.0
0.0
0.1
0.1
3.0
0.0
0.1
0.1
0.0
0.1
0.1
4.5
V
3.0
0.36
0.44
4.5
0.36
0.44
5.5
1.65
5.5
5.5
5.5
--
-
-
--
-
-
±0.5
-
±0.1
4.0
-
--
---'
-
±5.0
±1.0
40.0
J.tA
• :This spec indicates the capability of driving 5011 transmission lines.
One output should be tested at a time for a 10ms maximum duration.
~.~I8AcaRPORATlaN-------------------------------------------------------
AC-76
TC74ACT04P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Voor
11K
10K
Ioor
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±150
500(DIP) *1180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
°C
*500m W in the range of Ta=
-40"C- 65·C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
Supply Voltage
. Vee
Input Voltage
VI~
Output Vol.tage..
... , .. '. VOLT
Operating Temperature
Topr
Input Rise and Fall Time dt/dv
DC
ELECTRICAL
VALUE
4.5-5.5
0- Vee
0- Vee
-40 - 85
0-10
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
r--
PARAMETER
SYMBOL
High-Level
Input Voltage
VIN
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vai
Low-Level
Output Voltage
Va..
Input Leakage Current
Quiescent Supply Current
liN
lee
6Icc
Ta=25"C
Ta=-40-85"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
2.0
2.0
l
5.5
4.5
V
0.8
0.8
l
5.5
4.5
4.4
Ia;=-5O tL A 4.5 4.4
V
Ia;=-24mA 4.5 3.94
3.80
ViN= VIL
3.85
Iai=-75mA. 5.5
0.0
O. I
0.1
4.5
Ia..=50tLA
V
0.36
0.44
Ia..=24mA
4.5
VIN= VIH
Ia..=75mA.
5.5
l. 65
±O.I
±l.0
5.5
VIN =Vee or GND
tL A
4.0
YiN - Vee or GND
5.5
40.0
PER INPUT:VIN =3.4V
l.5 rnA
1.35
OTHER INPUT:Veeor GND 5.5
TEST CONDITION
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a !Oms maximum duration.
------------------------------------------------------------TCNIHIBA
AC-73
cORpa~aN
TC74ACT04P/F/FN
AC ELECTRICAL CHARACTERISTICS(CL=60pF. RL =6000. Input t r =tf=3ns}
Ta-25"C
Ta- 40 -85"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
MIN. TYp. MAx. MIN. MAX.
Va:;
tpLH
Propagation Delay Time
S.O±O.S
1.0
ns
5.5
7.9
9.0
t pH!.
Input Capacitance
CIN
5
10
10
pF
Power Dissipation Capacitance CPOOl
19
Note 01 C fl) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icc qw=C PO • Vcr;. f IN +I cr; /6( per Gate)
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-74
TC74AC05PIF IFN
AC ELECTRICAL CHARACTERISTICS(CL =60pF, R L =600Q, Input t r =t,=3ns}
Ta-25,,(:
'1'a=-40 -85"C UNIT
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX. Ml.N. MAX.
Vcr.
Propagation Delay Time
tpLZ
S.S±O.S
5.0±O.5
-
-
4.1
3.5
7.0
5.3
1.0
1.0
-
-
8.0
6.0
ns
5.9
9.1
1.0
10.4
4.1
6.6
1.0
7.5
Input CapaCltance
. CIN
5
10
10
pF
Output Capacitance
Coor
10
Power Dissipation CapacitlDce (;PO(1)
8
Note (1) C I'D is defined as the value or the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC tpl=C PO • Va::. f IN +I a:: 16( per Gate)
Propagation Delay Time
tp7l.
S.S±O.S
5.0±O.5
-
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - TOSHIBA CORPORATION
Ae-77
TC74AC08P/F/FN
QUAD 2-INPUT
AND
GATE
The TC74AC08 is an advanced high speed CMOS 2'-INPUT
AND GATE fabricated with silicon gate and double-layer
metal wiring C' MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit is composed of 2 stages including
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP14-P-300)
14~ ,.~
1
F(SOP14-P-300)
FEATURES:
• High Speed ................................. tpd=3.4ns (typ.) at Voc =SV
• Low Power Dissipation .............. ·loc=4J.tA(Max.) at Ta=25"C
• High Noise Immunity .............. • VNlH=VNlL =28711 Voc(Min.)
• Symmetrical Output Impedance .. ·1 Joo 1=lo,=24mA(Min.)
Capability of driving SOQ
transmission lines.
• Balanced Propagation Delays ...... tpLH .. tpHL
• Wide Operating Voltage Range ..· Voc (opr)=2V-S.5V
• Pin and Function Compatible with 74F08
PIN
FN(SOL 14-P-150)
ASSIGNMENT
lA
1B
1Y
2A
2B
2Y
GNO
14
13
12
11
2
3
4
Vee
4B
4A
4Y
10 3B
9 3A
8 3Y
5
6
7
(TOP VIEW)
IEC
LOGIC SYMBOL
1A
18
2A
28
3A
38
4A
48
TRUTH
TABLE
1Y
A
2Y
3Y
4Y
B
y
L
L
L
L
H
L
H
L
L
H
H
H
TO.aHIIIA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-78
TC74AC08P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vex;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10see
SYMBOL
Vex;
VIN
Your
11K
10K
lour
lex;
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vex;+0.5
-0.5 -Vex;+0.5
±20
±50
±50
±100
500(DlP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m W;oC shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VIN
Your
Topr
dt/dv
UNIT
V
V
V
"C
VALUE
2.0-5.5
0- Vex;
0- Vex;
-40 - 85
SYMBOL
Va;
o-100(Vex;=3.3±0.3V)
0- 20 (Vex; = 5 ±0.5V)
ns/v
CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
lIN
lex;
-
Ta=-40-85"C
Ta=25"C
Vex; MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
5.5 3.85
3.85
2.0
0.50
0.50
V
3.0
0.90
0.90
5.5
1. 65
1. 65
2.0
2.0
1.9
1.9
1oH=-50JlA
3.0 2.9
3.0
2.9
VIN =
4.4
4.5
4.4
4.5
V
IOH=-4mA
3.0
2.58
2.48
VU-l0r VIL
IOH=-24mA 4.5 3.94
3.80
3.85
lal=-75mA* 5.5
2.0
0.1
0.0
0.1
3.0
10!..=50JlA
0.0
O. I
0.1
4.5
0.0
O. I
o. I V
VIN=VIL
3.0
0.36
10!..=12mA
0.44
0.36
0.44
4.5
IOL=24mA
5.5
1. 65
IO!.. =75mA*
VIN =Vex; or GND
5.5
±0.1
±1.0
JlA
4.0
5.5
40.0
VIN =Vex; or GND
TEST CONDITION
• :This spec indicates the capability of driving 5011 transmission lines.
One output should be tested at a time for a lOms maximum duration.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Y O a H l a A CORPORATION
AC-79
TC74ACOSPIF/FN
AC ELECTRICAL CH ARACTERISTICS(C L=60pF. RL =:6000. Input tr=tf =3ns}
Ta=40 -85"(
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
Vex; MIN. TYP. MAX. MIN. MAX. UNIT
Propagation Delay Time
tpU\
t JlIIL
3.3±0.3
5.0±0.5
-
5.8
4.5
9.8
7.0
1.0
1.0
U.3
8.0
ns
Input Capacitance
C\:\
5
10
10
pF
Power Dissipation Capacitance Cpo(l)
71
NoteU) Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icx:wo.=C PD· Va::: of 1;11+1 a::: 14(per Gate)
~I~.C~N------------------------------------------------------------
AC·80
TC74ACT08P/F/FN
QUAD 2-INPUT
AND
GATE
The TC74ACT08 is an advanced high speed CMOS 2-INPUT
AND GATE Cabricated with silicon gate and double-layer
metal wiring C· MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
This device may be used as a level converter Cor
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP14-P-300)
F(SOP14-P-300)
FEATURES:
• High Speed ................................. tpd = 4.7ns (typ.) at Vee = 5V
• Low Power Dissipation ............... Icc=4.uA(Max.) at Ta=25"C
• Compatible with TTL outputs ...... VIL =0.8V (Max.)
V IH =2.0V (Min.)
• Symmetrical Output Impedance .. ·1 I oHI=IoL=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpHL
• Pin and Function Compatible with 74FOS
PIN
FN(SOL 14-P-150)
ASSIGNMENT
lA
Vce
18 2
13 48
1V 3
2A 4
28 5
12 4A
11 4V
2V 6
9
38
3A
7
8
3V
GND
10
(TOP VIEW)
IEC
LOGIC
SYMBOL
IA
18
2A
28
3A
38
4A
48
TRUTH
IY,
TABLE
B
y
L
L
L
L
H
L
A
2Y
3Y
4Y
H
L
L
H
H
H
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TOIIHIIIA CORPORATioN
AC-81
TC74ACToaP I FI FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vcr;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vcr;
VIN
Your
11K
10K
lOUT
Icr;
PD
Tstg
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
VALUE
-0.5 -6.0
-0.5 -Vcr;+0.5
-0.5 -Vcr;+0.5
±20
±50
±50
±100
500(DIP) */180(SOP)
-65 -150
300
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until300mW.
·C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vcr;
Input Voltage
VI:-J
Output Voltage
VQl;T
Operating Temperature
Topr
Input Rise and Fall Time dt/dv
DC
ELECTRICAL
VALUE
4.5-5.5
0- Vcr;
o -Vcr;
-40 - 85
0-10
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
r---
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
V(]-\
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
•
liN
Icr;
~Icc
TEST CONDITION
loo=-50/LA
Irn=-24mA
Irn=-75mA*
h=50/LA
Vn,=
IOL=24mA
VIHor \TiL
IOL=75mA*
VIN =Vcr; or GND
VIN =Vcr; or GND
PER INPUT:VIN -3.4V
OTHER INPUT:Vcr; or GND
VIN = Viii
Ta=25"C
Ta=-40-85"C
Vcr; MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
2.0
2.0
1
5.5
4.5
V
0.8
0.8
1
5.5
4.5
4.4
4.5 4.4
V
3.80
4.5 3.94
5.5
3.85
0.0
4.5
0.1
0.1
V
0.36
4.5
0.44
5.5
1. 65
- ±O.l - ±1.0 p,A
5.5
5.5
4.0
40.0
-
5.5
-
-
1.35
-
1.5
mA
. .
..
..
:Tlus spec mdicates the capabilIty of drivmg 500 transIDlSslOn lines .
One output should be tested at a time for a 10ms maximum duration.
TOaHllIA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-82
TC74ACT08P I FI FN
AC ELECTRICAL CHARACTERISTICS(CL=&OpF. RL =6000. Input t r =t,=3ns)
Ia--40 -85"C
'l'a-25"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
MIN. TYP. MAX. MIN. MAX.
Vex::
Propagation Delay Time
t pLH
t IiiL
S.O±O.S
-
5.4
8.7
1.0
10.0
ns
Input Capacitance
CIN
5
10
10
pF
Power Dissipation Capacitance Cpo(l)
21
Note (1) Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icc~=C po. VOC· f IN+I OC /4(perGate)
---------------------------------------------------------------~I~ C~~A~TWON
AC-83
TC74AC10P/F/FN
TRIPLE 3-INPUT
NAND
GATE
The TC74AClO is an advanced high speed CMOS 3-INPUT
NAND GATE fabricated with silicon gate and double-layer
metal wiring C' MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit is composed of 3 stages including
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP14-P-300)
,,~ 14~
1
F(SOP14-P-300)
FEATURES:
• High Speed ................................. tpd=5.0ns (typ.) at Vc:c=5V
• Low Power Dissipation ............... Icc=4 JL A(Max.) at Ta=25"C
• High Noise Immunity ...... ·.... · .. · Vl'llI-l =VNlL =28% Vcc(Min.)
• Symmetrical Output Impedance ... , loti , =1 OL =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpHL
• Wide Operating Voltage Range .. · Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F10
PIN
FN(SOL 14-P-150)
ASSIGNMENT
1A
1B
2A
2B
2C
2Y
1
2
3
GND
7
14 Vee
13 lC
12 IV
11 3C
10 3B
9 3A
8 3V
4
5
6
(TOP VIEW)
IEC
LOGIC
SYMBOL
TRUTH
TABLE
lA
lB
lC
A
B
C
y
X
X
H
L
X
L
2C
3A
3B
X
X
X
L
H
H
H
H
L
3C
X : Don't Care
2A
2B
H
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-84
TC74AC11P/F/FN
TRIPLE
3-INPUT
AND
GATE
The TC74AC11 IS an advanced high speed CMOS 3INPUT AND GATE fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit is composed of 4 stages including
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits
against static discharge or transient excess voltage.
P(DIP14-P-300)
F(SOP14-P-300)
FEATURES:
• High Speed ................................. tpd=5.3ns (typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=4#A(Max.) at Ta=25"C
• High Noise Immunity .............. · V"'IH=VNlL =28% Vcc(Min.)
• Symmetrical Output Impedance .. ·1100 1=IOL =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tplll"'tpl-lL
• Wide Operating Voltage Range .. · Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 11
FN(SOL 14-P-150)
PIN ASSIGNMENT
lA
1
14 Vee
1B
2
2A
3
13 1C
12 1Y
2B
4
11 3C
2C.
5
10 3B
2Y
6
9
3A
GND7
8
3Y
(TOP VIEW)
IEC LOGIC SYMBOL
lA
18
lC
2A
28
2C
3A
38
3C
(1)
(2)
TRUTH TABLE
"
(12)
1Y
(13)
(3)
(4)
(6)
2Y
(5)
(9)
(10)
(11)
(8)
3Y
X:
A
B
C
Y
L
X
X
L
X
L
X
L
X
X
L
L
H
H
H
H
Don't Care
------------------------------TOSHIBA
AC-87
CORPORATION
TC74AC11P/F/FN
ABSOLUTE MAXIMuM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
Vee
VI:X
VOlJr
11K
10K
IOL,'T
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Va;+0.5
-0.5 -Vee+0.5
±20
±50
±50
±lOO
500(DIP) ./180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW·
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI'C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vee
0- Va;
-40 - 85
UNIT
V
V
V
"C
0-100(Vee =3.3±0.3V)
0- 20(Va;= 5 ±0.5V)
ns/v
SYMBOL
Vee
VIN
VOlJf
Topr
dt/dv
CHARACTERISTICS
r---
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vai
Low-Level
Output Voltage
VOL
Ta=-40-85"C
Ta=25"C
UNIT
Va; MIN. TYP. MAX. MIN.
MAX.
1. 50
2.0 1. 50
V
3.0 2. 10
2.10
5.5 3.85
3.85
0.50
2.0
0.50
V
3.0
0.90
0.90
5.5
1. 65
1. 65
2.0
2.0
1.9
1.9
2.9
1oH=-50/.LA
3.0
2.9
3.0
4.5
4.4
4.5
4.4
V
VIN=Vlli
Iq.J=-4mA
3.0 2.58
2.48
3.80
lcii=-24mA 4.5 3.94
1oH=-75mA. 5.5
3.85
0.0
2.0
0.1
0.1
lOL,=50/.LA
3.0
0.0
0.1
0.1
VIN=
4.5
0.0
0.1
0.1
V
0.36
3.0
0.44
IOL=12mA
VIHor VIL
IOL=24mA
4.5
0.44
0.36
5.5
1. 65
IOL =75mA*
±0.1
5.5
±1.0
VIN =Va; or GND
/.LA
4.0
VIN =Vee or GND
5.5
40.0
TEST CONDITION
-
Input Leakage Current
Quiescent Supply Current
liN
lee
-
• :This spec indicates the capability of driving 500. transmission lines.
One output should be tested at a time for a lOms maximum duration.
TOIIHIIIA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-88
TC74AC10P I FI FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI~
Your
11K
10K
lOuT
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP) *1180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
°C
*500m W in the range of Ta=
-40'C- 65'C. From Ta=65"C
to 85'C a derating factor of
-10m WI"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Your
Topr
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vee
o -Vee
-40 - 85
Vee
VIN
dt/dv
UNIT
V
V
V
°C
o-lOO(Vee =3.3±0.3V)
ns/v
0- 20(Vee= 5 ±0.5V)
CHARACTERISTICS
-
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vai
Low-Level
Output Voltage
Vex.
Input Leakage Current
Quiescent Supply Current
11,\
Icc
..
Ta=25°C
Ta= -40-85"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
--5.5 3.85
3.85
2.0
0.50
0.50
V
0.90
3.0
0.90
5.5
1. 65
1. 65
2.0
1.9
2.0
1.9
3.0
3.0
2.9
Iai=-50I1A
2.9
VIN =
4.5
4.4
4.5
4.4
V
,. Iai=-4mA
3.0
2.58
2.48
VIIi or VIL
Ial=-24mA
4.5 3.94
3.80
3.85
Ial=-75mA* 5.5
2.0
0.0
0.1
0.1
IQL=50I1A
3.0
0.0
O. 1
O. I
4.5
0.0
O. 1
0.1
V
VIN=VII-I
0.36
3.0
0.44
10I.=12mA
0.44
0.36
4.5
IOL=24mA
5.5
1. 65
IOL=75mA.
±0.1
5.5
±1.0
V"" =Vee or GND
I1A
4.0
40.0
5.5
VI:-.J =Vee or GND
TEST CONDITION
• :Tlus spec mdlcates the capability of dnvmg 50n transmission lmes .
One output should be tested at a time for a lOms maximum duration.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T O B H I B A CORPORATION
AC-85
TC74AC1OP/F/FN
AC ELECTRICA L CHARACTERISTICS(C L=60pF. RL =6000. Input tr=tf =3n8)
Ta-25"C
Ta--40 -85"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
MIN. TYP. MAX. MIN. MAX.
Vcr
Propagation Delay Time
t pLiI
tpllL
3.3±O.3
5.0±O.S
-
7.6
6. 1
13.0
8.6
1.0
1.0
15.0
9.9
ns
Input Capacitance
5
CIN
10
10
pF
Power Dissipation Capacitance CPD(1)
70
Note (1) C I'D is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lcrq,o=C PD" VOC " f 1:\ +1 oc/3(per Gate)
~~I~ ~A~A~TMON----------------------------------------------~---------------
AC-86
TC74AC11 PI FI FN
AC ELECTRICAL CHARACTERISTICS(C L=60pF, RL =6000, Input t r =tf=3ns)
PARAMETER
Propagation Delay Time
Input Capacitance
Power Dissipation (;apacitance
SYMBOL TEST CONDITION
t pi.! I
t pili.
Vcr;
MIN.
3.3±0.3
5.0±O.5
-
-
-
CIN
CPD(l)
Ta-25"C
'l'a- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
8.0
6.0
14.0
9.0
1.0
1.0
16.0
10.2
ns
5
63
10
-
10
pF
Note (1) C I'D is defined as the value of the mternal eqUIvalent capacItance whIch IS calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icr; Q>1l=C I'D • Va:;. f IN +I a:; /3( per Gate)
------------------------------TOBHIBA
AC-89
CORPORATION
TC74AC14P/F/FN
HEX SCHMITT INVERTER
The TC74AC14 is an advauced high speed CMOS SCH~llTT
INVERTER fabricated with silicon gate and double-layer
metal wiring C MOB technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
Pin configuration and Cunction are the same as the
TC74AC04 but the inputs have hysteresis and with its
schmitt trigger Cunction, the TC74AC14 can be used as a
line receivers which will receive slow input signals.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P( DI P14-P-300)
,.~ 14~
1
FEATURES:
• High Speed ................................. tpd=5.3ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc =41l A(Max.)at 1'a=25"C
• Symmetrical Output Impedance "'1 htl=IOI.. =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpUi"tpHL
• Wide Operating Voltage Range ... Vcc(opr)=2V-5.5V
• Pin and Function Compatible with 74F14
SYSTEM DIAGRAM,WAVEFORM
F(SOP14-P-300)
FN(SOL 14-P-1&O)
PIN ASSIGNMENT
1A
1Y
2A
2Y
3A
3Y
1
2
3
4
5
6
GND
7
14
13
12
11
10
Vee
6A
6Y
5A
5Y
9 4A
8 4Y
(TOP VIEW)
TRUTH TABLE
IEC LOGI,C SYMBOL
1A
1V
2A
3A
2Y
4A
4V
5A
5V
6A
6Y
3Y
A
Y
L
H
H
L
~IBA CO~RAT10N----------------------------------------------------------
AC-90
TC74AC14P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI:-;
VOLi
11K
10K
IOLi
lee
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5 -6.0
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±50
±50
±150
500(DIP) */ 180(SOP)
-65 -150
300
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85"C a derating factor of
-lOmW/'C should be applied
up to 300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
DC
ELECTRICAL
PARAMETER
Positive
Threshold
Voltage
Negative
Threshold
Voltage
Hysteresis
Voltage
High-Level
Output Voltage
UNIT
V
V
V
VALUE
2-5.5
0- Vee
0-- Vee
-40 - 85
"C
CHARACTERISTICS
SYMBOL
Vp
V\"
VH
VCJi
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
I I\"
lee
* :Thls
SYMBOL
Vee
VI:-VOLi
Topr
spec indicates the
r--
Ta=25"C
Vcr:. MIN. TYP. MAX.
2.2
3.0
4.5
3.2
5.5
3.9
3.0 0.5
4.5 0.9
1.1
5.5
3.0 0.3
1.2
4.5 0.4
1.4
5.5 0.5
1.6
2.0
1.9
2.0
3.0 2.9
3.0
1ai=-50ItA
4.5
4.5
4.4
ViN=VIL
I(}I=-4mA
3.0 2.58
1(}I=-24mA 4.5 3.94
l(}I=-75mA. 5.5
2.0
0.0
0.1
0.0
0.1
3.0
IOL= 50ltA
0.0
0.1
4.5
Vj:-;=VIH
0.36
1QL=12mA
3.0
.
4.5
0.36
IOL=24mA
5.5
IOL =75mA.
±O.l
VI\" =Vee or GND
5.5
5.5
4.0
VI\" =Vcr:. or GND
..
..
capablhty of drlvmg 500 transmission hnes .
TEST CONDITION
-
--
--
--
--
-
---
-
Ta=-40-85"C
t:NIT
MIN. MAX.
2.2
V
3.2
3.9
0.5
V
0.9
1.1
0.3
1.2
V
0.4
1.4
0.5
1.6
1.9
2.9
4.4
V
2.48
3.80
3.85
0.1
0.1
0.1
V
0.44
0.44
1. 65
±1.0
itA
40.0
-
-
---
---
-
,
- - - - - - - - - - - - - - - - - - - - - - - - - - - - T O B H I B A CORPORATION
AC-91
TC74AC14P/F/FN
AC ELECTRICAL CHARACTERISTICS(CL=60pF. RL =6000. Input t r =t,=3na)
PARAMETER
Propagation Delay Time
Input Capacitance
Power Dissipation Cap8CItance
SYMBOL TEST CONDITION
tpLH
tpHL
_'l'a-25~
Vee
3.3±0.3
5.0±O.5
MIN.
-
TYP.
8.1
6.0
Ta--40 -85"(
MAX.
13.2
9.7
5
10
29
Note Ul C PO IS defmed as the value of the internal eqUivalent capacitance which
operating current consumption without load.
Average operating current can be obtained by the equation:
IccQxl=C po. VOC· r 1:.;+1 OC 16(per Gate)
(.;L'I;
(.;po(1)
-
MAX.
1.0
1.0
15.0
11. 0
ns
-
10
pF
-
IS
UNIT
MIN.
-
calculated from the
T08HIBAC~~-------------------------------------------------------
AC-92
TC74AC20P/F/FN
DUAL 4-INPUT NAND GATE
The TC74AC20 is an advanced high speed CMOS 4INPUT NAND GATE fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit is composed of 3 stages including
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P( 01 P14-P-300)
14~ 14~
1
F(SOP14-P-300)
FEATURES:
'0 High Speed ....................•.•.......... tpd=4.1(typ.) at Va;=5V
• Low Power Dissipation ............... Ia::=4/.tA(Max.) at Ta=25"C
• High Noise Immunity··············· VNlH=VN1L =28" Va;(Min.)
• Symmetrical Output Impedance ···110-1 1=IOL =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH "'tpl-\L
• Wide Operating Voltage Range ... Va;(opr)=2V-S.SV
• Pin and Function Compatible with 74F20
FN(SOL 14-P-150)
PIN ASSIGNMENT
lA 1
14 Vee
18 2
13 20
NC 3
12 2C
lC 4
11
10 5
10 28
lY 6
9
2A
GNO 7
8
2Y
NC
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
lA
A
B
C
0
Y
lC
L
X
X
X
H
10
X
L
X
X
H
X
X
l
X
H
X
X
X
L
H
H
H
H
H
L
18
2A
28
2C
20
X : Don't Care
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TallHIIIA CORPORATION
AC-93
TC74AC20P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Voc/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Voc
VIr->
VOLT
11K
10K
IOLT
loc
Po
Tstg
'rL
VALUE
-0.5 -6.0
-0.5 -Voc+0.5
-0.5 -Voc+0.5
±20
±50
±50
±lOO
500(DIP)*/180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vcr;
0- Vcr;
-40 - 85
SYMBOL
Vcr;
VI!'
VOLT
Topr
dt/dv
UNIT
V
V
V
"C
O-lOO(Vcr;=3.3 ±O.3V)
0- 20(Vcr;= 5 ±O.5V)
ns/v
CHARACTERISTICS
r--
PARAMETER
SYMBOL
High-Level
Input Voltage
VIII
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Low-Level
Output Voltage
Voo
VOL
Ta=25"C
Vcr; MIN. TYP. MAX.
2.0 1. 50
3.0 2. 10
5.5 3.85
2.0
0.50
3.0
0.90
5.5
1. 65
2.0
2.0
1.9
Iai=-50J,tA
3.0 2.9
3.0
VIN =
4.5
4.5 4.4
2.58
Im=-4mA
3.0
VIII or VIL
lai=-24mA 4.5 3.94
Ial=-75mA* 5.5
2.0
0.0
0.1
IOL=50J,tA
3.0
0.0
0.1
0.1
4.5
0.0
ViN=ViH
0.36
IOL=12mA
3.0
4.5
0.36
IOL=24mA
5.5
IOL =75mA*
- ±O.l
5.5
VIN =Vcr; or GND
VIl" =Vcr; or GND
5.5
4.0
TEST CONDITION
-
Input Leakage Current
Quiescent Supply Current
liN
Icr;
-
Ta=-40-85"C
UNIT
MIN. MAX.
1. 50
V
2.10
3.85
0.50
V
0.90
1. 65
1.9
2.9
4.4
V
2.48
3.80
3.85
0.1
0.1
0.1
V
0.44
0.44
1. 65
- ±1.0 p.A
40.0
-
-
-
-
• :This spec indicates the capability of driving 50n transmission lines.
One output should be tested at a time for a lOms maximum duration.
~I~CO~~~----------------------------------------------------------
AC-94
TC74AC20P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L =60pF.R L =6000.lnput t r =t,=3ns)
Ta-25"C
Ta--40 -85"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vcr;
MIN. TYP. MAX. MIN. MAX.
Propagation Delay Time
t pLll
t !tIL
3.3±0.3
5.0±0.5
-
6.0
4.8
10.0
7.0
1.0
1.0
11.4
8.0
ns
Input Capacitance
CIN
5
10
10
pF
Power Dissipation Capacitance
CpD(l)
66
Note(1) Cm is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icr;QJIl=C PD • Va; • fiN +1 a; 12(per Gate)
--------------------~-----------TaIIHIIIA
AC-95
CORPORATION
TC74AC32P/F/FN
QUAD 2-INPUT
OR
GATE
The TC74AC32 is an advanced high speed CMOS 2-'-INPUT
OR GATE fabricated with silicon gate and double-layer
metal wiring C' MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit is composed of 2 stages including
buffer output. which provide high noise immunity arid ,
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP14-P-300)
,.~ ,,~
1
F(SOP14-P-300)
FEATURES:
• High Speed ................................. tpd,=4.1ns (typ.) at Voc=5V
• Low Power Dissipation ............... Ioc=4 #A(Max.) at Ta=25"C
• High Noise Immunity .............. · VNIH=VNIL =28" Voc(Min.)
• Symmetrical Output Impedance .. ·1 Jai 1=Ia.=24mA(Min.)
Capability of driving SOQ
transmission lines.
• Balanced Propagation Delays ...... tpLH .. tpHL
• Wide Operating Voltage Range'" Voc(opr)=2V-"5~5V
• Pin and Function Compatible with 74F32
PIN
FN(SOL 14-P-150)
ASSIGNMENT
1A
18
1Y
2A
28
2Y
GND
1
2
3
4
14
13
12
11
10
5
6
9
7
8
Vee
48
4A
4Y
38
3A
3Y
(TOP VIEW)
IEC
LOGIC SYMBOL
lA
lB
2A
2B
3A
3B
4A
4B
TOIIHIIIA CDAPOAATIGN
TRUTH
IV
2Y
3V '
4V
TABLE
A
B
Y
H
H
H
L
H
H
H
L
H
L
L
L
-------------~---------------
AC-96
TC74AC32P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
Voor
11K
I(l(
loor
lee
Po
Ta&g
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5-6.0
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP)./180(SOP)
-65 -150
300
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VALUE
Supply Voltage
2.0-5.5
Vee
Input Voltage
O-Vee
VIN
Output Voltage
o -Vee
Voor
Operating Temperature
Topr
-40 - 85
Input Rise and Fall Time
DC
dtldv
.500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
UNIT
V
V
V
"C
o-IOO(Vee =3.3±0.3V)
o-20(Vee= 5 ±O.5V)
ns/v
ELECTRICAL CHARACTERISTICS
;----
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vai
Low-Level
Output Voltage
Va.
Input Leakage Current
Quiescent Supply Current
lIN
lee
Ta=25"C
Vee MIN. TYP. MAX.
2.0 1. 50
3.0 2.10
5.5 3.85
0.50
2.0
0.90
3.0
1. 65
5.5
2.0 1.9
2.0
3.0
1ai=-5IlJ,tA
3.0 2.9
4.5
4.5 4.4
VIN=VIH
lai=-4mA
3.0 2.58
1ai=-24mA 4.5 3.94
1a-t=-75mA. 5.5
0.0
0.1
2.0
0.1
0.0
Ia.=5IlJ,tA
3.0
VIN=
4.5
0.0
0.1
0.36
3.0
1a.=12mA
VIHorVIL
0.36
4.5
Ia.=24mA
Ia.=75mA.
5.5
- ±0.1
VIN =Vrr. or GND
5.5
4.0
5.5
VIN =Vee or GND·
TEST CONDITION
-
-
Ta=-40-85"C
UNIT
MIN. MAX.
1. 50
V
2.10
3.85
0.50
V
0.90
1. 65
1.9
2.9
4.4
V
2.48
3.80
3.85
0.1
0.1
0.1
V
0.44
0.44
1. 65
- ±1.0
#A
40.0
• :This spec indicates the capability of driving 500 tranamissIon lines.
One output should be tested at a time for a lOms maximum duration.
----------------------------------------------------------~HIBA ~POAA~N
AC~97
TC74AC32P I FI FN
AC ELECTRICAL CHARACTERISTICS(CL=60pF, RL =6000, Input t T =t,=3ns)
Ta-25,,(
Ta- 40 -85"(
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vcr;
MIN. TYP. MAX. MIN. MAX.
Propagation Delay Time
t pili
tpliL
a.a±o.a
S.O±O.S
-
6.1
5.2
10. a
7.4
1.0
1.0
11. 9
8.5
-
-
ns
Input Capacltance
CIN
5
10
10
pF
_Power Dissipation Capacitance
64
Note(l) CIn is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icc~=C po. Va;. £ IN+I cr;/4(per Gate)
cpom
~~~----------------------------------------------------------
AC-98
TC74ACT32P/F/FN
QUAD
2-INPUT
OR
GATE
The TC74ACT32 is an advanced high speed CMOS 2-INPUT OR
GATE fabricated with silicon gate and double-layer metal wiring
OlMOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
This device may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd =4.5ns (typ.) at Vee =5V
• Low Power Dissipation ............... Icc=4IlA(Max.) at Ta=25"C
• Compatible with TTL outputs ...... VIL =O.8V (Max.)
V IH =2.0V (Min.)
• Symmetrical Output Impedance ... II ou I=IOL =24mA(Min.)
Capability of driving SOQ
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpHL
• Pin and Function Compatible with 74F32
1
P( 01 P14-P-300)
F(SOP14-P-300)
PIN
FN(S0L14-P-150)
ASSIGNMENT
lA
16
lY
2A
26
14 Vee
13 46
12 4A
11 4Y
10 36
2
3
4
5
2Y 6
9
3A
7
8
3Y
GND
(TOP VIEW)
IEC
LOGIC
SYMBOL
lA
18
2A
28
3A
38
4A
48
TRUTH
1Y
2v
3Y
4Y
TABLE
y
A
B
H
H
H
L
H
H
H
L
H
L
L
L
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T C l i l H l l I A COIUlOAATlaN
AC-99
TC74ACT32P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature.
Lead Temperature 10sec
SYMBOL
Vee
VIN
VOlJr
11K
10K
IOlJI,
lee
Po
Tstg
TL
VALUE
-0.5-6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP)*/180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vee
Input Voltage
VIN
Output Voltage
Vour
Operating Temperature
Topr
Input Rise and Fall Time dt/dv
DC
ELECTRICAL
VALUE
4.5-5.5
0- Vee
0- Vee
-40 - 85
0-10
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
r--
PARAMETER
SYMBOL
High-Level
Input Voltage
VIII
Low-Level
Input Voltage
VII.
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
lIN
lee
blcc
TEST CONDITION
YiN=
VIHor VIL
Irn=-50J,tA
Irn=-24mA
Irn=-75mA.
loL=50J,tA
IOL=24mA
IOI.=75mA.
VIN =Vee or GND
VIN =Vee or GND
PER INPUT:VIN =3. 4V
OTHER INPUT:Vee or GND
VIN = VIL
Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. L"NIT
4.5
V
2.0
1 2.0
5.5
4.5
V
0.8
0.8
1
5.5
4.5 4.4
4.5
4.4
V
3.80
4.5 3.94
3.85
5.5
0.0
4.5
0.1
0.1
V
0.36
4.5
0.44
5.5
1. 65
- ±0.1 - ±1.0
5.5
J1.A
5.5
4.0
40.0
5.5
-
-
1.35
-
1.5
rnA
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a 10ms maximum duration.
TClIIHIIIA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AG-100
TC74ACT32P/F/FN
AC ELECTRICAL CHARACTERISTICS(CL =60pF, R L =600Q, Input t r =tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Propagation Delay Time
tpLH
t pHI.
Input Capacitance
Power Dissipation Capacitance
CIN
V/X
MIN.
5.0±0.5
-
Ta-25"C
Ta- 40 .......S5"C
UNIT
TYP. _MAX. MIN. MAX.
5.2
7.9
5
10
1.0
9.0
ns
10
pF
-
(;PD(l)
22
Note (1) C FD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
I/Xt¢=C PD· Voc· fIN+I oc/4(per Gate)
------------------------------TOIIHIBA COAJIiIOAATIDN
AC-101
TC74AC74PI FI FN
DUAL D-TVPE FLIP FLOP PRESET AND CLEAR
r-------------------------,
The TC74AC74 is an advanced high speed CMOS DFLIP FLOP fabricated with silicon gate and double-layer
metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The signal level applied to the D INPUT is transferred
to Q OUTPUT during the positive going transition of the
CK pulse.
.
CLR and PR are independent of the CK and are accomplished by
setting the appropriate input low.
P(DIP14-P-300)
,,~ 14~
1
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ...............................•. fmu =200MHz(typ.} at Vcc=5V
• Low Power Dissipation ............... Icc=4ILA(Max.) at Ta=25"C
• High Noise Immunity·· .. · .. · .. ·· .. · V:,\IH=VNIL=28% Vcc(Min.)
• Symmetrical Output Impedance ···1100 1=IOL=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays .•.... tpUI '" tpliL
• Wide Operating Voltage Range .. · Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 74
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
14 Vee
1 CLR
10 2
13
2CLR
1 CK 3
12
20
1 PR 4
11
2CK
105
10
2PR
10 6
9
20
GND 7
8
20
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
INPUTS
OUTPUTS
CLR
PR
0
L
H
X
CK
X
H
L
X
X
L
L
H
X
X
H
L
H
H
H
H
X
S
S
l
H
0
L
H
H
L
H
0
H
L
H
H
L
On
On
FUNCTION
CLEAR
PRESET
-
lPR
lCK
10
lCLR
2PR
2CK
20
2CLR
10
10
20
20
NO CHANGE
X: Don't care
TCMSHlaAC~N------------------------------------------------------------
AC-102
TC74AC74P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Vour
11K
10K
loor
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee+O.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vee
0- Vee
-40 - 85
SYMBOL
Vee
VIN
VOl;T
Topr
dtldv
UNIT
V
V
V
"C
0-100(Vee =3.3±0.3V)
0- 20(Vee= 5 ±0.5V)
ns/v
CHARACTERISTICS
,--
PARAMETER·
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
liN
lee
Ta=25"C
Ta=-40-85"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2. 10
2.10
5.5 3.85
3.85
2.0
0.50
0.50
- . 0.90 V
0.90
3.0
5.5
1. 65
1. 65
2.0
1.9
2. 0
1.9
2.9
3.0 2.9
IOH=-50tLA
3.0
Vlr\=
4.5
4.4
4.5
4.4
V
3.0
2.58
2.48
IOH=-4mA
VIHor VIL
!oo=-24mA 4.5 3.94
3.80
3.85
!oo=-75mA* 5.5
2.0
0.0
0.1
0.1
3.0
0.0
0.1
0.1
IOL=50tLA
VI;II=
4.5
0.1
0.0
0.1
V
0.36
3.0
IOL=12mA
0.44
VIHor VII,
0.36
4.5
0.44
10I,=24mA
5.5
1. 65
10I,=75mA*
5.5
±O.l
±1.0
VIN =Vee or GND
tL A
5.5
VII' =Vee or GND
4.0
40.0
TEST CONDITION
-
-
• :ThIs spec indicates the capability of driving 50n transmission lines.
One output should be tested at a time for a IOms maximum duration.
------------------------------TallHIBA
AC-103
CORPORATION
TC74AC74P/F/FN
SYSTEM DIAGRAM
1113
o
Q
o
(>0--: :
CK~
TIMING REQUIREMENTS(lnput tr=tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Va:;
Ta=25"C
TYP.
LIMIT
Ta=-40-85"C UNIT
LIMIT
3.3±0.3
5.0±0.5
-
7.0
5.0
7.6
5.0
tW(L)
3.3±0.3
5.0±0.5
-
7.0
5.0
7.0
5.0
Minimum Set-up Time
ts
3.3±0.3
5.0±0.5
-
6.0
3.5
6.0
3.5
Minimum Hold Time
th
3.3±0.3
5.0±0.5
-
1.0
1.0
1.0
1.0
trem
3.3±0.3
5.0±0.5
-
4.0
2.0
4.0
2.0
Minimum Pulse Width
(CK)
Minimum Pulse Width
(CLR. PR)
tW(L)
tw(H)
-
Minimum Removal Time
(CLR. PR)
-
ns
~laACORPa~-------------------------------------------------------
AC-104
TC74AC74P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L=60pF. RL =6000. Input t r =t,=3ns)
Ta--40 -85"C
'l'a-25"C
UNIT
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX. MIN. MAX.
Vex
Propagation Delay Time
(CK-Q. Q)
t pUI
t I~!I.
3.3±0.3
5.0±0.5
Propagation Delay Time
(CLR. PR-Q. Q)
t \lUi
t pilL
3.3±0.3
5.0±0.5
Maximum Clock Frequency
f:v1AX
3.3±0.3
5.0±0.5
-
8.2
6.1
13.9
8.7
1.0
1.0
16.0
10.0
-
8.0
5.7
13.1
8.2
1.0
1.0
15.0
9.4
60
100
120
160
-
60
100
-
-
ns
-
-
-
MHz
Input Capacitance
10
CIN
5
10
pF
Power Dissipation Capacitance
77
CPDW
Note(l) C/u is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
la;tpO=CPD - Va;- fl:\+1 a;12(per F/F)
------------------------------------------------------------TCNIHlaA ~~~
AC-105
TC74Atn4P/F/FN
DUAL D-TVPE FLIP FLOP PRESET AND CLEAR
r-----------------------~
The TC74ACT74 is an advanced high speed CMOS DFLIP FLOP fabricated with silicon gate and double-layer
metal wiring c2Mos technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
This device may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,~MOS and CMOS output
voltage levels.
The signal level applied to the D INPUT is transferred
to Q OUTPUT during the positive going transition of the
CK pulse.
CLR and PR are independent of the CK and are accomplished by
setting the appropriate input low.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. fmax =180:ViHz(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=4t.tA(Max.) at Ta=25"C
• Compatible with TTL outputs ...... Vu. =O.8V (Max.)
VU1=2V (Min.)
• Symmetrical Output Impedance · .. 1Iail =101. =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpu,'" tpilL
• Pin and Function Compatible with 74F 74
P( DI P14-P-300)
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
1 CLR
14 Vee
1D 2
13
2CLR
1 CK 3
12
2D
1 PR 4
11
2CK
10 5
102M
10
6
9
20
GND 7
8
20
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
INPUTS
OUTPUTS
FUNCTION
CLR
PR
D
CK
Q
Q
L
H
H
CLEAR
L
H
L
PRESET
L
L
X
X
X
L
H
X
X
X
H
H
H
H
L
L
H
H
H
H
H
L
-
H
X
Qn
Qn
NO CHANGE
H
S
S
L
-
lPR
lCK
10
lCLR
2PR
2CK
20
2CLR
10
1'0
20
2'0
X : Don't care
~HI8AC~RA~------------------------------------------------------------
AC-106
TC74AC'n4P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Your
11K
10K
Iwr
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP) *1l80(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40·C- 65"C. From Ta=65"C
to 85"C a derating factor of
-IOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
SYMBOL
Vee
VIN
VOlJf
Topr
dt/dv
VALUE
4.5-5.5
0- Vee
0- Vee
-40 - 85
0-10
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
r--
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Ou tpu t Voltage
VOH
Low-Level
Output Voltage
Va.
Input Leakage Current
*
Vee
Ta=-40-85"C
Ta=25"C
UNIT
MIN. TYP. MAX. MIN. MAX.
4.5
liN
lee
Quiescent SuppiyCurrent
TEST CONDITION
t:.1cc
1
2.0
-
-
2.0
-
V
I
-
-
0.8
-
0.8
V
4.4
3.94
4.5
-
-
4.4
3.80
3.85
-
V
0.0
0.1
0.36
-
5.5
4.5
5.5
4.5
IOH=-5O tt A
VIN=
IOH=-24mA
4.5
VIHor VIL
IOH=-75mA* 5.5
4.5
1oL=50 tt A
YiN=
Ia.=24mA
4.5
VIHor VIL
5.5
Ia.=75mA*
5.5
VIN =Vee or GND
VIN =Vee or GND
5.5
PER INPUT:VIN -3.4V
5.5
OTHER INPUT:Veeor GND
-
-
-
-
-
-
±0.1
4.0
-
1.35
-
-
0.1
0.44
1. 65
±1.0
40.0
V
tt A
1.5 rnA
:This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a lOms maximum duration.
------------------------------------------------------------TCNIHIBACDAPO~TMON
AC-107
TC74Acn4P I FI FN
SYSTEM DIAGRAM
o
Q
(/I
i
1>--: :
CK~
TIMING REQUIREMENTS(lnput tr=tr=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vcr.
Ta=25"C
TYP.
LIMIT
Ta=-40-85"C UNIT
LIMIT
Minimum Pulse Width
(CK)
tW(L)
twan
5.0±0.5
-
5.0
5.0
Minimum Pulse Width
(CLR. PR)
tW(L)
5.0±0.5
-
5.7
6.5
Minimum Set-up Time
ts
5.0±0.5
-
3.5
3.5
Minimum Hold Time
111
5.0±0.5
-
1.5
1.5
Minimum Removal Time
(CLR. PR)
trem
5.0±0.5
-
2.0
2.0
ns
~18AcaRPG~-----------------------------------------------------
AC-108
TC74AC'n4P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L =50pF. R L =500Q, Input t r =t,=3ns)
Ta- 40 -85°C
Ta-25"C
UNIT
PARAMETER
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
Propagation Delay Time
(CK-Q. Q)
t pLH
t pHL
5.0±0.5
-
6.1
9.2
1.0
10.5
ns
Propagation Delay Time
(CLR. PR-Q. Q)
t
Maximum Clock Frequency
f~
pLH
t pHL
5.0±0.5
-
6.5
10.5
1.0
12.0
5.0±0.5
95
160
-
95
-
MHz
Input Capacitance
Cr..:
5
10
10
pF
-Power Dissipation Capacitance CPDm
35
Note (l) C H) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCq,o=CPD oVOC oC r,+Ioc / 2(perF/F)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TaSHIBA CORPORATION
AC-109
TC74AC86P/F/FN
QUAD
EXCLUSIVE
OR
GATE
The TC74AC86 is an advanced high speed CMOS QUAD
EXCLUSIVE OR GATE fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit includes an output buffer, which provides
high noise immunity and stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=4.4ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=4/.tA(Max.) at Ta=25"C
• High Noise Immunity··············· VNIH=VNIL =28" Vcc(Min.)
• Symmetrical Output Impedance ···1 lOB 1=IOI.=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpl.H" tpHL
• Wide Operating Voltage Range ... Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 86
P(DIP14-P-300)
F(SOP14-P-300)
PIN ASSIGNMENT
1A
1
14 Vee
1B
2
13 4B
1Y
3
12 4A
2A
4
11 4Y
2B
5
6
103B
9 3A
GND7
8 3Y
2Y
(TOP
IEC LOGIC SYMBOL
lA
18
2A
28
3A
38
4A
48
(1)
(2)
(9)
(10)
(12)
(13)
VIEW)
TRUTH TABLE
=1
(3)
1Y
A
(4)
(5)
FN(SOL 14-P-150)
(6)
(8)
(11)
2Y
3Y
4Y
B
Y
L
L
L
L
H
H
H
L
H
H
H
L
~18A CORP~----------------------------__------------------------------
AC-110
TC74AC86P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
Vour
11K
10K
lOUT
lee
Po
Tstg
TL
VALUE
-0.5-6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP)*/180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-IOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time·
DC
ELECTRICAL
dtldv
UNIT
V
V
V
"C
VALUE
2.0-5.5
0-- Vee
0-- Vee
-40 -- 85
SYMBOL
Vee
VIN
Voor
Topr
0-lOO(Vee =3.3±0.3V)
nslv
0- 20(Vee= 5 ±0.5V)
CHARACTERISTICS
c---
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Ta=25"C
Ta=-40-85"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
3.85
5.5 3.85
2.0
0.50
0.50
V
3.0
0.90
0.90
5.5
1. 65
1. 65
2.0 1.9
2.0
1.9
Ioo=-50ttA
3.0 2.9
2.9
3.0
VIN=
4.5 4.4
4.5
4.4
V
3.0 2.58
2.48
Ioo=-4mA
VIHor ViL
Ioo=-24mA 4.5 3.94
3.80
3.85
Ioo=-75mA* 5.5
2.0
0.0
0.1
0.1
0.0
0.1
0.1
3.0
loL=50.uA
VIN=
4.5
0.0
0.1
0.1
V
0.36
3.0
IOL=12mA
0.44
VIHor VIL
4.5
0.36
IOL=24mA
0.44
5.5
1. 65
Ia.=75mA*
- ±0.1 - ±1.0
5.5
VIN =Vee or GND
.u A
5.5
4.0
VIN =Vee or GND
40.0
TEST CONDITION
-
-
-
Low-Level
Output Voltage
VOL
-
Input Leakage Current
Quiescent Supply Current
111\
lee
-
-
-
-
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a 10ms maximum duration.
-----------------------------TOaHIIIA CORPORATION
AC-111
TC74AC86P/F/FN
AC ELECTRICAL CH ARACTERISTICS(C L=&OpF.
PARAMETER
Propagation Delay Time
SYMBOL TEST CONDITION
tplJi
tpHL
RL =&000.
Vex:
3.3±0.3
5.0±O.5
Input t r =tf=3ns)
Ta--40 -85"e
Ta-25"C
UNIT
MIN. TYP. MAX. MIN. MAX.
-
7.6
5.6
12.3
8.3
1.0
1.0
-
14.0.
9.5
ns
Input Capacitance
5
CIN
10
10
pF
Power Dissipation Capacitance Cpom
56
Note (1) C I'D 15 defmed as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icc q,o=C pO • Va:;. fIN +1 a:; 14(per Gate)
-
TCHIHI~ca~~N------------------------------------------------------------
AC-112
TC74ACT86P/F/FN
QUAD
EXCLUSIVE
OR
GATE
The TC74ACT86 is an advanced high speed CMOS QUAD
EXCLUSIVE OR GATE fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL. NMOS and CMOS output voltage levels. The internal
circuit includes an output buffer, which provides high noise
immunity and stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd =5.0ns (typ.) at Vee =5V
• Low Power Dissipation ............... Icc=4.uA(Max.) at Ta=25"C
• Compatible with TTL outputs ...... VIL =O.8V(Max.)
VIH=2.0V(Min.)
• Symmetrical Output Impedance .. ·lloH I =IQL=24mA(Min.)
Capability of driving Sog
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpHL
• Pin and Function Compatible with 74F 86
1
P( DIP14-P-300)
14Q
14~
1
F(SOP14-P-300)
FN(S0L14-P-150)
PIN ASSIGNMENT
1A
14 Vee
1B
2
13 4B
12 4A
1Y
3
2A
4
11 4Y
2B
5
103B
2Y
6
9 3A
GND 7
8 3Y
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
lA
18
2A
28
3A
38
4A
48
(1)
(2)
(4)
(6)
(9)
(10)
(12)
(13)
=1
(3)
1Y
A
(6)
(8)
(11)
2Y
3Y
4Y
B
Y
L
L
L
L
H
H
H
L
H
H
H
L
- - - - - - - - - - - - - - - - - - - ' - - - - - ' - - - - - - - - - T O S H I B A CORPORATION
AC-113
•TC74ACT86P I FI FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Va;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
Va;
VIN
Voor
11K
I(]{
loor
Ia;
PD
Tstg
TL
VALUE
-0.5 '-6.0
-0.5 -Va; +0.5
-0.5 -Va;+0.5
±20
±50
±50
±100
500(DIP)*/180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C ...... 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
PARAMETER
High-Level
Input Voltage
Low-Level
Input Voltage
High-Level
Output Voltage
Low-Level
Ou tpu t Voltage
Input Leakage Current
Quiescent Supply Current
SYMBOL
Va;
VIN
Vou•
Topr
dt/dv
VALUE
4.5-5.5
0 ...... Va;
O-Va;
-40 - 85
0-10
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
-
Ta=-40-85"C
Ta=25"C
Va; MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
VIH
2.0
2.0
l
5.5
4.5
V
0.8
0.8
l
VIL·
5.5
4.5
4.4
loo=-50JLA
4.5 4.4
YiN=
V
loo=-24mA 4.5 3.94
3.80
Voo
VIHor VIL
3.85
Ioo=-75mA* 5.5
4.5
0.0
0.1
0.1
Iot..=50JLA
YiN=
V
IQL=24mA
0.36
4.5
0.44
VOL
VIHor VIL
5.5
1. 65
Iot..=75mA*
- ±O.l - ±1.0
5.5
VIN =Va; or GND
liN
/lA
.la;
VIN =Va; or GND
5.5
4.0
40.0
PER INPUT:VIN -3.4V
1.5 rnA
1.35
~Icc OTHER INPUT:Va;or GND 5.5
SYMBOL
TEST CONDITION
-
-
-
-
-
-
• :This spec indicates the capability of driving 500 tranamission lines.
One output should be tested at a time for a lOms maximum duration.
TOeHIIIA CQIIUIIORATION
---------~-------------------
AC-114
TC74ACT86P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L=60pF, RL =600Q, Input t r =t,=3ns)
Ta- 40 -85"C
Ta-25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
MIN. TYP. MAX. MIN. MAX.
Vee
Propagation Delay Time
tpUi
t pilL
5.0±0.5
-
5.7
10.5
1.0
12.0
ns
Input Capacitance
5
CIN
10
10
pF
Power Dissipation Capacitance CPDm
23
Note (1) Cit> is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ieeq,,)=C PD· Va;. fIN +1 a; 14(per Gate)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOSHIBA CORPORATION
AC-115
TC74AC109P/F/FN
DUAL
J-K
FLIP FLOP WITH PRESET AND CLEAR
The TC74ACI09 is an advanced high speed CMOS
DUAL J-K FLIP FLOP fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
In accordance with the logic level on the J and K inputs this
device ~s state on the positive going transition of the clock
pulse. CLEAR and PRESET are independent of the clock and
accomplished by a low logic level on the corresponding input.
~~----------------------~
1
P(DIP16-P-300A)
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
F(SOP16-P-300)
FEATURES:
• High Speed ................................. fMAX =200MHz(typ.) at Va:;=5V
• Low Power Dissipation •.•............ Ia:;=4IlA(Max.) at Ta=25"C
• High Noise Immunity··· ............ V Nil I = VNIL =28" Va:; (Min.)
• Symmetrical Output Impedance ···1 JOII 1=101.. =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ....•. tpU-l"'tpl1L
• Wide Operating Voltage Range •.. Va:;(opr.)=2V-5.5V
• Pin and Function Compatible with 74FI09
FN(SOL 16-P-150)
PIN ASSIGNMENT
Vee
2CLR
lClR 1
16
1J 2
15
1K 3
14 2J
1CK 4
13 2K
1PR 5
12 2CK
10 6
11 2PR
1Q 7
10 20
GND 8
9
2Q
(TOP VIEW)
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS
CLR
L
H
L
H
H
H
H
H
PR
H
L
L
H
H
H
H
H
OUTPUTS
J
X
X
X
K
CK
a
a
X
X
X
X
X
X
L
H
H
H
L
H
L
L
H
H
H
L
H
L
X
x
.r an an
.r L H
.r H L
.r an an
1.
an an
FUNCTION
CLEAR
PRESET
NO CHANGE
TOGGLE
NO CHANGE
X : Don't care
TOeHI8Aca~~------------------------------------------------------------
AC-116
TC74AC109P I FI FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
VOlJT
11K
10K
lour
lee
PD
TsLg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
VALUE
-0.5 -6.0
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±50
±50
±IQO
500(DIP) ./180(SOP)
-65 -150
300
.500mW in the range of 'ra=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Vex
VIN
VOlJT
Topr
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vee
0- Vex
-40 - 85
SYMBOL
dt/dv
UNIT
V
V
V
"C
0-100(Vc:c=3.3±O.3V)
ns/v
0- 20(Vex = 5 ±0.5V)
CHARACTERISTICS
-
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Val
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
lex
Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
5.5 3.85
3.85
2.0
0.50
0.50
V
0.90
0.90
3.0
5.5
1. 65
1. 65
2.0
1.9
1.9
2.0
3.0
2.9
2.9
Ial=-50tLA
3.0
VIN =
4.5
4.4
4.5
4.4
V
2.58
2.48
3.0
Ial=-4mA
VIHor VIL
3.80
4.5 3.94
Ia-1=-24mA
3.85
!m=-75mA* 5.5
2.0
0.0
0.1
0.1
3.0
0.0
0.1
0.1
IOL= 50ttA
VIN=
0.1
4.5
0.0
0.1
V
0.36
3.0
0.44
IOL=12mA
Vlllor VIL
4.5
0.36
0.44
IOL=24mA
IOL =75mA.
5.5
1. 65
5.5
±0.1
±1.0
VI!I/ =Vee or GND
tL A
5.5
4.0
40.0
VIN =Vex or GND
TEST CONDITION
-
liN
..
-
-
-
• :This spec indicates the capabihty of driving 500 transmission Unes .
One output. shouid be tested at a time for a lOms maximum duration.
- - - - - T a e H I B A CORPORATION
AC-117
TC74AC109P/F/FN
SYSTEM DIAGRAM
CLR
PR
J
CK
~""'9I---t[>)O-.- - :
TIMING REQUIREMENTS(lnput t r=tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vcr;
Ta-25"C
TYP.
LIMIT
Ta=-40-85"C UNIT
LIMIT
Minimum Pulse Width
(CK)
twO,)
tW(li)
3.3±O.3
5. O±O. 5
-
-
8.0
5.0
8.0
5.0
Minimum Pulse Width
(CLR. PR)
two.)
3.3±O.3
5. O±O, 5
-
7.0
5.0
7.0
5.0
Minimum Set-Pulse Time
ts
3.3±O.3
5. O±O. 5
-
-
9.0
5.0
9.0
5.0
Minimum Hold Time
In
3.3±O.3
5.0±O.5
-
0.0
0.0
0.0
0.0
Minimum Removal Time
(CLR. PR)
trem
3.3±O.3
5.0±O.5
-
3.0
2.0
3.0
2.0
-
-
ns
~HI8AcaRPOAATMON-------------------------------------------------------
AC-118
TC74AC109P I FI FN
AC ELECTRICAL CHARACTERISTICS(C L=60pF. RL =6000. Input t,=tl=3ns)
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX.
Vee
3.3±0.3
8.2
13.9
Propagation D~lay Time tpLlI
(CK-Q, Q)
5.0±0.5
6.1
8.7
t pilL
Pro~tion
Delal: Time
(CLR, PR-Q, Q)
tpLiI
t pilL
3.3±0.3
5.0±0.5
-
8.5
6.4
14.4
9.1
Ta--40-85"C
UNIT
MIN. MAX.
1.0
16.0
1.0
10.0
ns
16.6
1.0
1.0
10.5
- MHz
120
55
160
100
Input Capacitance
5
10
10
C!:\
pF
Power Dissipation Capacitance CPD(1)
82
Note (1) C R) is deCined as the value oC the internal equivalent capacitance which is calculated Crom the
operating current consumption without load.
Average operating current can be obtained by the equation:
IccQJO=C I'D • Va;. f 11'< +1 a; 12(per F/F)
Maximum Clock Frequency
fM/\x
3.3±0.3
5.0±0.5
55
100
--------------------------------TOaHIIIA
AC-119
CORPORATION
TC74AClM09P/F/FN
DUAL
J-i< FLIP FLOP WITH PRESET AND CLEAR
~-----------------------.
The TC74ACTI09 is an advanced high speed CMOS
DUAL J-K FLIP FLOP fabricated with silicon gate and
double-layer metal wiring dMOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
These devices may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
In accordance with the logic level applied to the J and K
inputs, the output changes state on the positive going
transition of the clock pulse. CLEAR and PRESET are
independent of the clock and are accomplished by a low logic
level on their inputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. fMAJ(=l85MHz (typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=4JlA(Max.) at Ta=25"C
• Compatible with TTL outputs ...... VIL =0.8V(Max.)
V1H=2V(Min.)
• Symmetrical Output Impedance ... , JOB' =IOL=24rriA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpHL
• Pin and Function Compatible with 74F 109
1
P(DIP16-P-300A)
F(SOP18-P-300)
FN(SOL 18-P-150)
PIN ASSIGNMENT
1m
18
Vee
lJ 2
1& 2m
Ii<
3
14 2J
lCK 4
13 2K
lj5j!j &
12 2CK
10 8
11 2j5j!j
10 7
10 20
GND 8
8
2'0
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
OUTPUTS
INPUTS
CLR
L
H
L
H
H
H
H
H
PR
H
L
L
H
H
H
H
H
J
K
CK
a
a
X
X
X
X
X
X
X
X
X
L
H
H
H
L
H
L
L
H
H
H
L
H
L
X
x
.r an an
.r L H
.r H L
.r an an
l. an an
FUNCTION
CLEAR
PRESET
NO CHANGE
TOGGLE
NO CHANGE
X : Don't care
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-120
TC74ACT109P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
VQ!l[
11K
10K
lOOT
lee
PD
Tstg
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
VALUE
-0.5 -6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP) *1180(SOP)
-65 -150
300
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-lOmW/'Cshould be applied
up to 300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
SYMBOL
High-Level
Input Voltage
VIII
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
Va.
Quiescent Supply Current
Vee
VIN
VOlJI'
Topr
dt/dv
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
PARAMETER
Input Leakage Current
VALUE
4.5-5.5
O-Vee
0- Vee
-40 - 85
0-10
SYMBOL
liN
lrr
~Icc
-
Ta=25"C
Ta=-40-85"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
2.0
2.0
1
5.5
4.5
V
0.8
0.8
1
5.5
4.5
IOH=-50ttA 4.5 4.4
4.4
VIN=
- 3.80
V
la-I=-24mA 4.5 3.94
VIHor VIL
3.85
IOH=-75mA* 5.5
- 0.1
4.5
0.0
0.1
Ia. =50ttA
VIN=
- 0.44 V
4.5
Ia. =24mA
0.36
VIHorVII.
5.5
1. 65
la.=75mA*
±O.l
5.5
±1.0
VIN =Vrr or GND
A
VIN =Vcr. or GND
5.5
4.0
40.0 tt
PER lNPUT:Vee=3. 4V
1. 35
1.5 mA
OTHER lNPUT:Vcr. or GND 5.5
TEST CONDITION
-
-
-
..
-
-
-
-
..
'" :Thls spec indicates the capablhty oC driVing 50 Q transmiSSion hnes .
One output should be tested at a time Cor a 10ms maximum duration.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T O B H I B A CORPORATION
AC-121
Te74ACT109P IF IFN
SYSTEM DIAGRAM
CK
~___-I[>>O-.- - ~
'------
,
TIMING REQUIREMENTS(lnput tr=tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vcr.
Ta-25"C
TYP.
LIMIT
Ta--40-85"C UNIT
LIMIT
Minimum Pulse Width
(CK)
two.)
twOi)
5.0±O.5
-
5
5
Minimum Pulse Width
(CLR,PR)
tW(L)
5.0±O.5
-
5
5
Minimum Set-up Time
ts
5.0±O.5
-
5
5
Minimum Hold Time
tn
5.0±O.5
-
2
2
tram
5.0±O.5
-
3
3
Minimum Removal Time
(CLR,PR)
ns
TO. . .IBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-122
TC74ACT109P/F/FN
AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL =500Q, Input t r=t,=3ns)
PARAMETER
SYMBOL TEST CONDITION
Ta=25"C
V(£
MIN.
Propagation Delay Time
(CK-Q.Q)
tpLH
tpHl,.
5.0±0.5
Propagation Delay Time
(CLR.PR-Q.Q)
tpLH
tpHl,.
5.0±0.5
-
Maximum Clock Frequency
fMAX
5.0±0.5
85
n=-40-85"t::_ UNIT
MIN. ;MAX.
'l"U".
MAX.
6.1
10.4
1.0
11.4
6.3
9.6
1.0
11.0
160
-
85
-
ns
-
MHz
Input {';apacitance
(,;IN
5
10
10
pF
fower llissipatioD lo:apwtance (,;PD(1)
30
Note(l) Cm ill defIned &II the value or the mternal equIvalent capacitance which is calculated from the
operating current consumption without load,
Average operating current can be obtained by the equation:
Icctp)=CPD 0 Va; 0 flN+1 a;/2(per F/F)
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - T O S H I B A CORPORATION
AC-123
TC74AC112P I FI FN
DUAL J-K FLIP FLOP WITH PRESET AND
CLEA,.:.;R~_ _ _ _ _ _ _ _--,
The TC74AC1l2 is an advanced high speed CMOS
DUAL J-K FLIP FLOP fabricated with silicon gate and
double-layer metal wiring c2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
In accordance with the logic level on the J and K inputs this
device ~s state on the negative going transition of the clock
pulse. CLEAR and PRESET are independent of the clock and
accomplished by a low logic level on the corresponding input.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. fMAX=170MHz(typ.) at Vw5V
• Low Power Dissipation •....•......... Icc=4#A(Max.) at Ta=25"C
• High Noise Immunity··············· VNIH=VNIL =28111 Vcc(Min.)
• Symmetrical Output Impedance ···11oH I=IOL =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpi-IL
• Wide Operating Voltage Range ... Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 112
P(DIP16-P-300A)
1.~1.~
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
1CK 1
16 Vee
1K 2
15 1CLR
1J 3
14 2~
11"R 4
13 2CK
1Q 6
12 2K
1Q 6
11 2J
2(1 7
10 2PR
GND 8
9
2Q
(TOP VIEW)
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS
CLR
L
H
L
H
H
H
H
H
PR
H
L
L
H
H
H
H
H
J
K
CK
X
X
X
X
X
X
X
X
X
L
L
H
H
L
H
L
H
"l..
X
x
1.
1.
1.
.1
OUTPUTS
a Q
L
H
H
H
L
H
an an
L
H
H
L
an
an
an
an
FUNCTION
CLEAR
PRESET
NO CHANGE
TOGGLE
NO CHANGE
X : Don't care
TOSHIBA COAPOAATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-124
TC74AC112P I FI FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage 'rem perature
Lead Temperature 10sec
SYMBOL
VALUE
Vee
VI:'>:
VOUT
IOLT
Icc
PD
-0.5 -6.0
-0.5 -Vee +0.5
-0.5 -Vc.:c+O.5
±20
±50
±50
±lOO
500(DIP )*/180(SOP)
Tstg
-65 -150
TL
300
11K
10K
UNIT
V
V
V
rnA
rnA
rnA
mA
rnW
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
unti1300mW.
°C
°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
VALUE
Vcc
VI\
VOUT
2.0-5.5
0- Vcc
0- Vcc
-40 - 85
Topr
dtldv
UNIT
V
V
V
°C
0-10O(Vcc =3.3±0.3V)
ns/v
0- 20(Vee= 5 ±0.5V)
DC
ELECTRICAL
CHARACTERISTICS
r---
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
TEST CONDITION
VI\=
VOI-l
VIHor VIL
VI\=
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Cur~ent
I IN
Icc
IOI-j=-50uA
IOI-I=-4rnA
IOI-j=-24rnA
IOI-j=-75rnA*
IOL=50uA
IOL=12rnA
IOL =24rnA
IOL =75rnA*
VI:'I =Vcc or GND
VI:-.i =Vee or GND
Vlflor V,,_
Ta=25°C
Vcc MIN.
2.0 1. 50
3.0 2. 10
5.5 3.85
Ta=-40-85°C
TYP. MAX. MIN. MAX.
1. 50
2. 10
3.85
2.0
3.0
5. 5
-
-
0.50
0.90
1. 65
-
0.50
0.90
1. 65
2.0
3.0
4.5
l.9
2.9
4.4
2.0
3.0
4.5
-
1.9
2.9
4.4
-
3.0
4.5
5.5
2.0
3.0
4.5
2.58
3.94
-
-
0.1
O. 1
O. I
3.0
4.5
5.5
5.5
5.5
-
-
-
-
2.48
3.80
3.85
0.0
0.0
0.0
0.1
0.1
O. I
-
0.36
0.36
--
-
-
-
-
±O.l
4.0
0.44
0.44
1. 65
±1.0
40.0
UNIT
V
V
V
V
UA
• :ThIS spec mdlCates the capabilIty of dnvmg 50n tranSITnSSlOn hnes.
One output should be tested at a time for a lOms maximum duration.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T Q S H I B A CORPORATION
AC-125
TC74AC112P/F/FN
SYSTEM DIAGRAM
CLR
PR
Q
K
Q
J
CK
~~I--IC>>O---;
.....
------~
TIMING REQUIREMENTS(lnput tr =tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Va:.
Ta=25"C
TYP.
LIMIT
Ta=-40-85"C UNIT
LIMIT
Minimum Pulse Width
(CK)
tW(L)
tW(I-n
3.3±0.3
5.0±O.5
-
-
7.5
5.0
7.5
5.0
Minimum Pulse Width
--(CLR, PR)
tW(L)
3.3±0.3
5.0±O.5
-
7.0
5.0
7.0
5.0
Minimum Set-up Time
ts
3.3±0.3
5.0±0.5
-
11.0
6.0
11.0
6.0
Minimum Hold Time
th
3.3±0.3
5.0±0.5
-
-
0.0
0.0
0.0
0.0
Minimum Removal Time
(CLR, PR)
trem
3.3±0.3
5.0±0.5
-
3.0
2.0
3.0
2.0
--
TOSHIBA CORPORATION
-
ns
--.,..-~------------.,....--~--.,..-----
AC-126
TC74AC112P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L =60pF, RL =6000, Input t r =t,=3ns)
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX.
Propagation Delay Time
tplJI
3.3±0.3
9.1
15.5
5.0±0.5
t pilL
6.5
9.4
(CK-Q.Q)
Propagation Delay Time
(CLR. PR-Q. Q)
tpllL
Maximum Clock Frequency
f MAX
tl~.11
3.3±0.3
5.0±0.5
-
3.3±0.3
5.0±0.5
45
80
8.6
5.8
90
150
5
85
14.6
8.3
-
-
Ta--40-85"C
UNIT
MIN. MAX.
17.8
1.0
1.0
to.8
ns
1.0
16.8
1.0
9.6
45
- MHz
80
10
pF
-
Input Capacitance
CIN
10
Power DissipauonCapacitance Cpom
Note(l) Cpo is defined as the value of the internal equivalent capacitance which is calculated from
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCQlll=C I'D • Va::. r 1:,\ +1 a:: 12(per F/F)
the
------------------------------TOSHIIIA CORPORATION
AC-127
TC74AC125P/F/FN, TC74AC126P/F/FN
TC74AC126P/F/FN QUAD BUS BUFFER
TC74AC126P/F/FN QUAD BUS BUFFER
The TC74AC125/126 are advanced high speed CMOS
QUAD BUS BUFFERs fabricated with silicon gate and
double-layer metal wiring CIMOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
_
The TC74AC125 requires the 3-state control input G to
be set high to place the output into the high impedance
state. whereas the TC74AC126 requires the control input
to be set low to place the output into high impedance.
All inputs are equipped with protection circuits against
. static discharge or transient excess voltage.
P(DIP14-P-300)
14~ 14~
1
FEATURES:
• High Speed ................................. tpd=4.7ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=8JtA(Max.) at Ta=2S"C
• High Noise Immunity .............. • Vl\'H=VNIL =28" Vcc(Min.)
• Symmetrical Output Impedance ..·1 1m I =Ia..=24mA(Min.)
Capability of driving SOQ
transmission lines.
• Balanced Propagation Delays ...... tl~JI..,tl.IL
• Wide Operating Voltage Range'" Vcc (opr)=2V......S.SV
• Pin and Function Compatible with 74F 125/1~6
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
TC74AC125
14 V cc
1'0
1A
2
13 40
2Y
3
12 4A
2(3
4
11 4Y
2A
I
10 30
2Y
•
• 3A
GND7
IEC LOGIC SYMBOL
• 3Y
(TOP VIEW)
TC74AC126
14V
cc
13
4G
12 4A
1G
TC74AC125
TC74AC126
1A
1Y
1Y
2Y
2Y
2Y
2G
3Y
3Y
2A
4Y
4Y
2Y
2
3
4
11
I
10
•
•
•
GND 7
4Y
3G
3A
3Y
(TOP VIEW)
TOSHIIIA CORPORATION - - - - - . ; . - - - - - - - - - - - - - - - - - - - - - - - -
AC·128
TC74AC125P/F/FN, TC74AC126P/F/FN
TRUTH TABLE
TC74AC12&
INPUTS
A
H
X
L
L
L
H
G
TC74AC126
OUTPUTS
y
Z
L
INPUTS
A
L
X
H
L
H
H
G
H
X : Don't Care
Z : High Impedance
OUTPUTS
Y
Z
L
H
X : Don't Care
Z : High Impedance
----------------------------------------------TOSHIBACORPORAnON
AC-129
TC74AC125P/F/FN,TC74AC126P/F/FN·
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
Voor
11K
10K
Ioor
lee
Po
Tstg
TI.
UNIT
V
V
V
mA
mA
mA
mA
mW
OC
OC
VALUE
-0.5 -6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP)*1180(SOP)
-65 -150
300
*500m W in the range or Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating·ractor or
-10m W/"C should be applied
up to 300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output 'Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2.0-5.5
O-Vee
O-Vee
-40 - 85
SYMBOL
Vee
VIN
VOl.".
Topr
dt/dv
O-lOO(Vcc=S.S±O.SV)
SYMBOL
High-Level
Input Voltage
V IH
Low-Level
Input Voltage
High-Level
Output Voltage
Low-Level
Output Voltage
-
Ta=25OC
Vee MIN. TYP. MAX.
2.0 1.50
S.O 2.10
5.5 3.85
2.0
0.50
3.0
0.90
5.5
1. 65
2.0
1.9
2.0
3.0
3.0 2.9
Ja.I=-50ttA
4.5 4.4
4.5
3.0 2.58
!ai=-4mA
JO.i=-24mA 4.5 3.94
1CH=-75mA* 5.5
2.0
0.0
0.1
3.0
0.0
0.1
Iot.=50ttA
4.5
0.0
0.1
3.0
0.36
Iot.=12mA
4.5
0.36
Iot.=24mA
5.5
Iot.=75mA*
TEST CONDITION
--
VII.
V(}{
VJN=
V IH or VII.
VIN=
VOl.
VUIOrVl1.
3-State Output
Off-State Current
Ice
VIN=VIH or VII.
Voor=Vee or GND
5.5
Input Leakage Current
Quiescent Supply Current
liN
lee
VIN=Vee or GND
VIN=Vee or GND
5.5
5.5
* :Thls
ns/v
0- 20(Vee= 5 ±0.5V)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
UNIT
V
V
V
OC
--
----
--
---
--
--
--
±0.5
-
±O.I
8.0
-
Ta=-40-85OC
UNIT
MIN. MAX.
1. 50
V
2.10
3.85
0.50
:V
0.90
1. 65
1.9
2.9
4.4
V
2.48
3.80
3.85
0.1
0.1
0.1
V
0.44
0.44
1. 65
--
-
---
-
---
±5.0
±1.0
80.0
tt A
spec indicates the capability or driYlng 50n transmission bnes.
One output should be tested at a time Cor a IOms maximum duration.
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-130
TC74AC125P/F/FN, TC74AC126P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L=60pF. RL =6000. Input t r =t,=3ns)
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
MiN.
TYJ:". MAX.
Vcr.
S.S±O.S
10.5
t
PiJi
6.4
Propagation Delay Time
t pli!.
7.0
5.0±0.5
4.7
Output Enable Time
tpZL
tpZH
S.3±0.3
5.0±0.5
tpLZ
tllHZ
CIN
3.3±0.S
5.0±0.5
-
7.1
5.0
12.3
7.9
Ta=-40-85"C UNIT
MIN. MAX.
1.0
12.0
8.0
1.0
1.0
1.0
14.0
9.0
ns
5.1
8.8
1.0
10.0
4.6
6.6
1.0
7.5
Input Capacltance
5
10
10
Output CaDacitance
l,;OUT
10
pF
Power Dissipation Capacitance cpom
24
Note (1) Of!) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ic:c~O PO • VCC· fIN +ICC 14(per Gate)
Output Disable Time
-
-
-----------------------------TDSHIBA
AC-131
-
CORPORATION
TC74AC138PI FI FN
3-TO-8 LINE DECODER
The TC74AC138 is an advanced high speed CMOS 3-to-8
DECODER fabricated with sillicon gate and double--Iayer
metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
When the device is enabled. 3 Binary Select inputs (A.B
and C) determine which one of the outputs (YO- Y7) will
go low.
When enable input Gl is held low or either G2A or G2B
is held high. decoding function is inhibited and all outputs
go high.
Gl. G2A. and G2B inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1.
P(DIP16-P-300A)
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
FEATURES:
• High Speed """"""""""""""",,. tp d=5.9ns(typ.) at Vcc=5V
• Low Power Dissipation ""." .. ".". Icc=8.uA(Max.) at Ta=25°C
• High Noise Immunity··············· V:\IH =V:\IL =2896 VcdMin.)
• Symmetrical Output Impedance ···I/a 1 I =1 (~_ =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays " .... tpLH" tpHL
• Wide Operating Voltage Range ... Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 138
A
1
B
2
15 VO
C
3
14 VI
G2A
4
13 V2
G2B
5
12 V3
Gl
V1
GNO
16 Vee
•
11 V4
7
10 Vi
8
9 V&
(TOP VIEW)
IEC LOGIC SYMBOL
A
I
e
YO
Yl
V2
V3
Y4
A
B
e
(1)
(2)
(3)
DMUX
O} G.!..
2
7
YO
Yl
Y2
Y3
Y4
Gl
;;6
Gl
V&
G2A
021
Y6
Y7
G2A
02B
Y8
Y7
~.HI~ C~~AA~N--------------------------------------------------------~-----
AC-132
TC74AC138P I FI FN
ABSOLUTE MAXIMUM RA TlNGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vex:/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vex:
VIN
Your
11K
10K
lour
lex:
~)
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vex:+0.5
-0.5 -Vex:+0.5
±20
±50
±50
±200
500(DIP)*/180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vex:
0- Vex:
-40 - 85
SYMBOL
Vex:
VIN
Your
Topr
dt/dv
UNIT
V
V
V
"C
0-lOO(Vex:=3.3 ±0.3V)
0- 2O(Vex:= 5 ±0.5V)
ns/v
CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vm
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
liN
lex:
-
Ta=-40-85"C
Ta=25"C
Vex: MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
3.85
5.5 3.85
2.0
0.50
0.50
V
0.90
0.90
3.0
5.5
1. 65
1. 65
2.0
1.9
2.0
1.9
lai=-50#A
3.0
2.9
3.0
2.9
VIN =
4.5
4.4
4.4
4.5
V
lai=-4mA
3.0 2.58
2.48
VIHor VIL
3.80
Ioo=-24mA 4.5 3.94
3.85
Ioo=-75mA* 5.5
2.0
0.0
0.1
0.1
IOL=50#A
3.0
0.1
0.0
0.1
VIN=
0.1
0.1
0.0
4.5
V
0.36
3.0
0.44
IOL=12mA
Villor VIL
0.36
0.44
IOL=24mA
4.5
5.5
1. 65
IOL =75mA*
- ±0.1 - ±1.0
5.5
VIN =Vex: or GND
#A
VIN =Vex: or GND
5.5
8.0
80.0
TEST CONDITION
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a lOms maximum duration.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOSHIIIA CORPORATION
AC-133
TC74AC138P/F/FN
TRUTH TABLE
INPUTS
ENABLE
OUTPUTS
SELECTED OUTPUT
SELECT
C
B
A
YO
Y1
Y2
Y3
Y4
Y5
Y6
L
X
X
X
X
X
H
H
H
H
H
H
H
H
NONE
X
H
X
X
X
X
H
H
H
H
H
H
H
H
NONE
X
X
H
X
X
X
H
H
H
H
H
H
H
H
NONE
H
L
L
L
L
L
L
H
H
H
H
H
H
H
YO
H
L
L
L
L
H
H
L
H
H
H
H
H
H
Y1
H
H
L
L
L
H
H
L
H
H
H
Y2
L
H
H
H
H
L
H
H
H
Y3
·H
H
H
H
L
L
H
L
H
H
H
H
L
H
H
Y4
L
L
H
L
L
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
L
L
H
Y6
L
.L
H
H
L
H
H
H
H
H
H
L
H
Y6
L
L
H
H
H
H
H
H
H
H
H
H
L
Y7
G1
G2A G2B
Y7
X : DON'T CARE
LOGIC DIAGRAM
15
14
13
12
SELECT
INPUTS
11
10
9
EN.BLE
INPUTS
I
7
G2.
G2B
G1
YO
Y1
Y2
Y3
Y4
DATA
OUTPUTS
Y6
Y6
Y7
4
6
6
~1"caAPOA~--------------------------------------------------~
AC-134
TC74AC138P I FI FN
AC ELECTRICAL CHARACTERISTICS(C L=60pF. RL =6000. Input t r =tf=3ns)
Ta- 40 -85°C
Ta-25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
3.3±0.3
8.5
14.2
1.0
16.3
Propagation Dell!Y Time tpLH
(A,S,C-Y)
S.0±0.5
6.4
9.2
t p/;IL
1.0
10.5
Propagation D.!J.ay Time
(G1-Y)
Propagati~
D..!.lay Time
(G2-Y)
-
t pLH
t I~-{L
3.3±0.3
5.0±0.5
-
tpLH
3.3±0.3
5.0±0.5
-
.tP/;-{L
-
7.5
6.1
12.8
8.9
1.0
1.0
14.7
10.2
8.8
7.2
5
143
15.0
10.5
10
1.0
1.0
17.3
12.0
10
ns
Input Capacitance
C\\
pF
Power Dissipation Capacitance CPDm
Note(l) CR) is defined as the value of the internal eqUivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iccm;=C PD • Va:. f e,\"'1 a:
------------------------------TOSHIBA
AC-135
CORPORATION
TC74ACT138P/F/FN
3-TO-8 LINE DECODER
The TC74ACTl38 is an advanced high speed C:\IOS 3-to-8
Ll~E DECODER fabricated with sillicon gate and double
-layer metal wiring C2:\t10S technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
C:\olOS low power dissipation.
This device may be used as a level converter for
interfacing TTL or ~MOS to High Speed C:\010S. The
inputs are compatible with TTL.:\:\lOS and C:\10S output
voltage levels.
When the device is enabled. 3 Binary Select inputs (A.B
and C) determine which one of the outputs (YO-'ll) will
go low.
When enable input Gl is held low or either G2A or G2B
is held high. decoding function is inhibited and all outputs
go high.
Gl, G2A. and G2B inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=6.0ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=8IlA(Max.) at Ta=25"C
• Compatible with TTL outputs· .. ·.. V lL =O.8V (Max.)
V IH =2.0V (Min.)
• Symmetrical Output Impedance .. ·1 I oHI =loL =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLII'=itpHL
• Pin and Function Compatible with 74Fl38
P ( 0 I P16- P-300A)
1.~1.~
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
A
1
16
B
2
15 YO
Vee
VI
V2
C
3
14
G2A
4
13
G2B
5
12 Y3
Gl
6
11 Y4
Y7
7
10 Y5
GND
8
9 Y6
(TOP VIEW)
lEe LOGIC SYMBOL
A
YO
A
B
VI
B
e
V2
V3
Y4
Vi
Y8
V7
e
Gl
G2A
G2B
Gl
G2A
G2B
VO
VI
V2
V3
V4
Vi
V8
V7
TOIIHIIIA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-136
TC74ACT138P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Va:
VI">:
VOL'T
11K
10K
lour
Ia:
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Va:+0.5
-0.5 -Va:+O.5
±20
±50
±50
±200
500(DIP)*/180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40·C- 65"C. From Ta=65"C
to 85'C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vee
Input Voltage
VI:-J
Output Voltage
VOLT
Operating Temperature
Topr
Input Rise and Fall Time dt/dv
DC
VALUE
4.5-5.5
0- Va:
0- Va:
-40 - 85
0-10
UNIT
V
V
V
"C
ns/v
ELECTRICAL ,CHARACTERISTICS
PARAMETER
SY~BOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Va;
Low-Level
Output Voltage
VCL
Input Leakage Current
Quiescent Supply Current
liN
Ia:
t:..1cc
TEST CONDITION
lor--50p.A
I(}I=-24mA
iar--75mA*
h=50p,A
h=24mA
VI"I= VIL
Ia.=75mA*
VIN =Va: or GND
VIN =Va: or GND
PER INPUT:VIN =3.4V
OTHER INPUT:Va: or GND
V\:\j=
VIHor VIL
Ta=25"C
Ta=-40-85"C
Va: MIN. TYP. MAX. MIN. MAX. UNiT
4.5
V
2.0
2.0
l
5.5
4.5
V
0.8
0.8
l
5.5
4.5 4.4
4.5
4.4
V
4.5 3.94
3.80
5.5
3.85
4.5
0.0
0.1
0.1
V
4.5
0.44
0.36
5.5
1. 65
5.5
±0.1
±1.0
p,A
5.5
8.0
80.0
-
-
-
5.5
-
-
1.35
-
1.5
rnA
• :This spec indicates the capability of driving 500 transmission lines,
One output should be tested at a time for a 10ms maximum duration.
----------------------------------------------------------~IBA COAPO~
AC-137
TC74ACT138P/F/FN
TRUTH TABLE
INPUTS
ENABLE
G1
OUTPUTS
SELECT
SELECTED OUTPUT
C
B
A
YO
Y1
Y2
Y4
Y5
Y8
Y7
X
X
X
X
X
X
H
H
H
H
H
H
H
H
NONE
H
H
H
H
H
H
H
H
NONE
H
X
X
X
H
H
H
H
H
H
H
H
NONE
L
L
L
L
L
H
H
H
H
H
H
H
YO
L
L
L
L
H
H
L
H
H
H
H
H
H
Y1
H
L
L
L
H
L
H
H
L
H
H
H
H
H
Y2
H
L
L
L
H
H
H
H
H
L
H
H
H
H
Y3
H
L
L
H
L
L
H
H
H
H
L
H
H
H
Y4
H
L
L
H
L
H
H
H
H
H
H
L
H
H
Y5
H
L
L
H
H
L
H
H
H
H
H
H
L
H
Y8
H
L
L
H
H
H
H
H
H
H
H
H
H
L
Y7
G2A G2B
L
X
X
X
H
X
X
X
H
L
H
Y3
X : DON'T CARE
LOGIC DIAGRAM
15
14
13
12
SELECT
INPUTS
11
10
9
7
YO
Y1
Y2
Y3
Y4
DATA
OUTPUTS
Y5
Y8
Y7
ENABLE [ .'A
INPUTS
G2B
G1
~IIIA
COAPOAATION - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-138
TC74ACT138P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L =60pF,R L =600Q,lnput t r =tf=3ns}
Ta-25"C
Ta--40 -85"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vee MIN. TYP. MAX. MIN. MAX.
Propagation Delay Time
(A,S,C-'l)
tpLii
tpfiL
5. O±O. 5
-
6.7
10.1
1.0
1l.5
Propagation Delay Time
tpLIl
tpHL
o. O±O. 5
-
6.8
10.5
1.0
12.0
(GI-Y)
ns
Propagation Delay Time
(G2-'l)
tpLiI
1.0
p. O±O. 5 6.9
11. 0
12.5
tPl-lL
Input Capacitance
C 1:\
5
10
10
pF
Power Dissipation Capacitance
CrD(!)
55
Note (1) C PO is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icc q,o =C PD· Va;. fl:\ +Ia;
--------------------------------TaSHIBA
AC-139
CORPORATION
TC74AC139P/F/FN
DUAL 2-TO-4 LINE DECODER
The TC74AC139 is an advanced high speed CMOS 2 to 4
LINE DECODER/DEMULTIPLEXER Cabricated with
silicon gate and double-layer metal wiring C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The active low enable input can be used Cor gating or it
can be used as a data input Cor demultiplexing
applications.
When the enable input is held high, all four outputs are
fixed at a high logic level independent of the other inputs.
All inputs are equipped with protection circuits against
static discharge or trasient excess voltage.
FEATURES:
• High Speed .............................. tpd=5.9ns(typ.}at Vee=5V
• Low Power Dissipation ............ l ee =8ttA(Max.}at Ta=25OC
• High Noise Immunity .. ·· .......... · V!'!
Icc
VIN =VCC or GND
VIN =Vcc or GND
5.5
5.5
-
YiN=
VIHor VIL
VIN=
VIHor VIL
..
..
• 1 . thiS spec Indicates the capability of dnvmg 500 transmission lmes .
-
-
±0.5
-
±0.5
±O.l
8.0
-
±1.0
80.0
.uA
One output should be tested at a time for a lOms maximum duration .
• 2 :for TC74ACl53
only
-----------=---------------------TOeHIIIA
AC-153
CORPORATION
TC74AC153P/F/FN,TC74AC253P/F/FN
SYSTEM DIAGRAM
:;.0..---
so
:>0-- SO
.:>0---- S1
:>0-- S1
.:>0---- S2
" ' - - S2
:>o----S3
S3
TC74AC153
TC74AC253
1-----,
1.-----1
1CO 6
1CO 6
1C1 5\
1C1 5\
7 1Y
SO
\
I
I
\
1C2
I
1C3
S3
1G
\
S3
I
-----~
'--------~
2CO f : 0 -------~2Y
2C1 11
2C2 ~ Same as above block
::3 ::;
I
i
~-------~
fR -------
2CO
J2Y
2C1 11
2C2 _1_ Same as above block
::' :1 _______
J
~~CDAPOAMnON--------------------------------
AC-154
TC74AC153P/F/~,TC74AC253P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L=50pF. RL =6000. Input t r =t,=3ns)
Ta--'-40 -85"C
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
MIN. TYP. MAX. MIN. MAX.
Vrx
Propagation Delay Time
(Cn-Y)
t pLiI
t pilL
3.3±0.3
5.0±0.5
-
7.6
5.0
14.5
9.0
1.0
1.0
16.5
10.3
Propagation Delay Time
(A,B-Y)
t 1~.11
t pilL
3.3±0.3
5.0±0.5
-
-
10.5
6.6
20.5
10.5
1.0
1.0
23.4
12.0
Propagation Delay Time
(G-Y)
•
tpLH
t pilL
3.3±0.3
5.0±0.5
-
6.8
4.4
13.3
8.0
1.0
1.0
15.2
9.1
Output Enable Time
tpZL
t JQII
3.3±0.3
5.0±0.5
-
6.6
4.4
13.3
8.0
1.0
1.0
15.2
9.1
tpLZ
t pHZ
3.3±0.3
5.0±0.5
-
5.5
5.0
fI.O
7.5
1.0
1.0
10.3
8.5
-
5
10
10
-
-
••
Output Disable Time
••
Input Capacitance
Output Capacitance ••
CIN
COLT
Power Dissipation Capacitance
C PD (1)
Note (1) C PD is defined as the value of the internal equivalent
operating current consumption without load.
Average operating current can be obtained by the equation:
Irxq,o=C PD· Va:;. f IN +1 a:;
(2)
• for TC74ACl53 only
•• for TC74AC253 only
ns
10
pF
54
capacitance which is calculated Crom the
.. C~~
------------------------------------------------------------~I
AC-155
TC74ACT153P I FI FN, TC74ACT253P I FI FN
TC74ACT153P/F/FN DUAL 4-CHANNEL MULTIPLEXER
TC74ACT253P/F/FN DUAL 4-CHANNEL MULTIPLEXER WITH 3-STATE OUTPUT
The TC74ACT153 and TC74ACT253 are advanced high
speed CMOS DUAL 4-CHANNEL MULTIPLEXERs
fabricated with silicon gate and double-layer metal
wiring C2MOS technology.
Both achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipations.
These devices may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
The designer has a choice of complementary output
CACT153) or 3-state output CACT253).
Each of the data input groups (lCO-lC3, 2CO-2C3) is
selected by the two address inputs A and B.
Separate strobes (la. 20) are provided for each of the two
four-line sections.
.
The strobe CO) can be used to inhibit the data output; the
output of ACT153 is held low and the output of ACT253 is
held in the high impedance state unconditionally, while the
strobe input is held low.
All inputs are equipped with protection circuit against
static discharge or transient excess voltage.
FEATURES:
• High Speed ............ '" .................. ~d = 5.4ns (typ.) at Vco = 5V
• Low Power Dissipation ............... Icc=8/.LA(Max.) at Ta=25"C
• Compatible with TTL outputs······ V lL =O.8V (Max.)
V lH =2.0V (Min.)
• Symmetrical Output Impedance ···1 I OH I=IOl.=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH!qtpHL
• Pin and Function Compatible with 74F153/253
TRUTH TABLE
DATA INPUTS
STROBE
OUTPUT Y
B
A
CO
C1
C2
C3
G
ACTI53
X
X
X
X
X
X
H
L
Z
L
L
L
X
X
X
L
L
L
16~1.~
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
7
16
15
14
13
12
11
10
8
9
IG
B
IC3
IC2
ICI
ICO
lY
GND
2
3
4
5
6
Vee
2G
A
2C3
2C2
2Cl
2CO
2Y
(TOP VIEW)
H
L
L
H
X
X
X
L
H
H
X
L
X
X
L
L
L
L
H
X
H
X
X
L
H
H
H
L
X
X
L
X
L
L
L
H
L
X
X
H
X
L
H
H
H
H
X
X
L
L
L
L
H
H
X
X
H
Impedans
L
H
H
X
X
:High
TC74ACT153
TC74ACT253
ACT253
L
care
P(DIP16-P-300A)
IEC LOGIC SYMBOL
SELECT
INPUTS
X:Don t
1
~laAca~R~N------------------------------------------------------------
AC-156
TC74ACT153P/F/FN,TC74ACT253P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Your
11K
10K
lour
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP)·/180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vee
Input Voltage
VI:-1
Output Voltage
Your
Operating Temperature
Topr
Input Rise and Fall Time dtldv
DC
ELECTRICAL
VALUE
4.5-5.5
0- Vee
0- Vee
-40 - 85
0-10
CHARACTERISTICS
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Veti
YiN=
VIHor VIL
Low-Level
Output Voltage
VOL
YiN=
VIHor VIL
a-State Output * 2
Off-eState Current
~
VIN=Vlli or VIL
Vour=Vee orGND
Quiescent Supply Current
-
Ta=-40-S5"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
2.0
2.0
l
5.5
4.5
V
O.S
O.S
l
5.5
4.5 4.4
4.4
4.5
Irn=-50 tt A
V
3.80
4.5 3.94
Irn=-24mA
Irn=-75mA* 1 5.5
3.S5
4.5
0.0
0.1
0.1
loi..=50 J.lA
V
IOL=24mA
0.44
0.36
4.5
1. 65
IOL=75mA* 1 5.5
PARAMETER
Input Leakage Current
UNIT
V
V
V
"C
ns/v
TEST CONDITION
VIN =Vee or GND
VIN =Vee or GND
PER INPUT:V 1:\ -3. 4V
~Icc
OTHER INPUT:Vee or GND
liN
lee
5.5
-
-
±0.5
5.5
5.5
-
-
-
-
±O.l
8.0
5.5
1.35
-
±0.5
±1.0
So. 0
1.5
J.lA
rnA
• 1 : This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a lOms maximum duration.
• 2 :£or TC74ACT253 only
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOIIHIIIA CORPGAATlON
AC-157
TC74ACT153P/F/AN,TC74ACT253P/F/RN
SYSTEM DIAGRAM
;>0----
so
""-- so
;>o----S1
S1
:»----
S2
S2
: x > - - - - S3
" ' - - S3
TC74ACT253
TC74ACT153
,-----1
1.-----1
1CO 6
1CO 6
1C1
1C1
5\
7 1Y
51
SO
I
I
I
1C2
\
I
1C3
\
S3
1G
L...-- _ _ _ _ _
I
S3
~
I
-----~
2CO f - : 0 - - - - - - - ~2Y
2C1 11
2C2 ~ Same as above block
:' :j _______ J
2CO~0 - - - - - - - ] 2 Y
2C1 11
2C2 E-
Same as above block
:;~-----j
TCMIHIBA CaIiUIOAATION - - - - - - - - - - - - - - - - - - - - - - - - -
AC-158
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74ACT153P/F/FN
TC74ACT253P/F/FN
AC ELECTRICAL CHARACTERISTICS(CL=60pF, RL =6000, Input t r =tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vee
MIN.
I 'l'a- 40 -85"C
Ta=25"C
UNIT
TYP. I MAX. MII~. Mj\X.
!
Propagation Delay Time
(Cn-Y)
t pLH
t pHI..
5.0±0.5.
-
6.1
9.7
1.0
11.0
Propagation Delay Time
(A.B-Y)
tpLH
tpHL
5.0±0.5
-
7.8
11.8
1.0
13.5
Propagation Delay Time
tpLH
tpHI..
5.0±0.5
-
5.6
9.7
1.0
11.0
Output Enable Time
..
tpZL
tpZH
5.0±0.5
-
5.3
8.3
1.0
9.5
..
tpLZ
tpHZ
5.0±0.5
-
5.4
7.5
1.0
8.5
(a-y)
•
Output Disable Time
-
-
ns
Input Capacitance
Cr,
5
10
10
OUtput Capacitance ..
10
pF
COLT
Power Disslpallon capacitance • l,;p!)(l)
47
Power Dissi~atioo Caoacitance.. CP!)(l)
50
Note III Cm is defmed as the value of the mternal equivalent capacitance Which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lccWll=C PO' Va:' fJ:,\+I a:
(2)
• for TC74ACT153 only
•• for TC74ACT253 only
-
-
-----------------------------TDSHIBA
AC-159
-
CORPORATION
TC74AC157P/F/FN, TC74AC158P/F/FN
TC74AC167P/F/FN
TC74AC168P/F/FN
QUAD 2-CHANNEL MULTIPLEXER
QUAD 2-CHANNEL MULTIPLEXER INVERTING)
The TC74AC157 and the TC74AC158 are advanced high
speed CMOS QUAD 2-CHANNEL MULTIPLEXER's
fabricated with silicon gate and double-layer metal
wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low Power dissipation.
These devices consist of four 2-input digital
mUltiplexers with common select and strobe inputs.
The TC74AC158 is an inverting multiplexer while the TC
74AC157 is a non-inverting multiplexer.
When the STROBE input is held high, selection of the data
is inhibited and all the outputs go low in the case of the 157
and high in the case of the 158.
The SELECT decoding determines whether the A or B
inputs get routed to their corresponding Y outputs.
All inputs are equipped with protection circuits llgainst
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=4.Sns(typ.) at Vcc=SV
• Low Power Dissipation ............... Icc=8ttA(Max.) at Ta=2S"C
• High Noise Immunity .............. • V?\lH=VNIL =28% Vcc(Min.)
• Symmetrical Output Impedance ·.. 1bi 1=Ia.=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tlll.Ii" tpHL
• Wide Operating Voltage Range .. · Vcc (opr)=2V-S.SV
• Pin and Function Compatible with 74FlS7/158
1
P(DIP16-P-300A)
I.~I.~
F(SOP16-P-300)
F L(SOL 16-P-150)
PIN ASSIGNMENT
TC74AC157
SELECT 1
1A
1B
1Y
18 Vee
2
15
14
3
4
if
4A
13
4B
12
4Y
2B
5
8
11
3A
2Y
7
10
3B
GND
8
9
3Y
2A
(TOP VIEW)
TRUTH TABLE
TC74AC158
OUTPUT
INPUTS
ST
H
L
SELECT
X
L
A
X
L
B
X
X
Y(157)
L
L
SELECT 1
Y(158)
1A
1B
H
1V
H
L
L
H
X
H
L
L
H
X
L
L
H
L
H
X
H
H
L
2A
18 Vee
2
3
4
15
14
if
13
4B
12
4V
4A
2B
5
6
2V
7
11 3A
10 3B
GND
8
9
3'1
(TOP VIEW)
X: Don't Care
~IBA~~A~----------------------------------------------------------
AC-160
TC74AC157P/F/FN,TC74AC158P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI:"
VOLT
11K
10K
IOl,T
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee +0.5
-0.5 -Vcc+0.5
±20
±50
±50
±100
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vee
0- Vee
-40 - 85
SYMBOL
Vee
VI~
VCJl;T
Topr
dt/dv
UNIT
V
V
V
"C
0-100(Vee =3.3±0.3V)
ns/v
0- 20(Vee= 5 ±0.5V)
CHARACTERISTICS
,-
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Input Voltage
VOi
Low-Level
Input Voltage
VOL
Input Leakage Current
Quiescent Supply Current
liN
lee
Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
2.10
3.0 2.10
3.85
5.5 3.85
2.0
0.50
0.50
V
0.90
0.90
3.0
1. 65
1. 65
5.5
2.0
1.9
2.0
1.9
2.9
3.0
2.9
3.0
Iat=-50tLA
VIN =
4.5
4.4
4.5
4.4
V
- 2.48 lOi=-4mA
3.0 2.58
VIHor VIL
- 3.80 lOi=-24mA 4.5 3.94
3.85
IOi=-75mA* 5.5
2.0
0.0
0.1
0.1
0.1
0.1
IOl,= 50tLA
3.0
0.0
VIN=
4.5
0.0
0.1
0.1
V
3.0
0.44
0.36
10l,=12mA
VIHor VIL
0.36
0.44
10l, =24mA
4.5
1. 65
5.5
10l,=75mA*
- ±O.l - ±1.0
5.5
VI" =Vee or GND
tL A
8.0
80.0
VIN =Vee or GND
5.5
TEST CONDITION
• :This spec indicates the capability of driving 50n transmission lines.
One output should be tested at a time for a lOms maximum duration.
------------------------------TOBHIBA
AC-161
CDRPDRATION
TC74AC157P/F/FN,TC74AC158P/F/FN
IEC LOGIC SYMBOL
TC74AC157
TC74AC158
SELECT
1A
18
2A
28
(4)
1A
18
2A
28
1Y
7
2Y
9
3Y
12
4Y
SYSTEM DIAGRAM
TC74AC158
TC74AC157
SELECT~
-
ST
15
1A
1A
18
18 ...:3_-+....""\
2A
2A ...:5_-+....""\
28
28 ..;.6_-+....",,\
3A
3A ...:..;11;"'-'-+-1"'\
38
38 ..:.:'0;...-.-+..........
4A
4A ...:..;14;...-.-+-..;-,,\
48
48 "",13,---+-;-,,\
-
+
+
ty
3'1
TOIIHIIIA CGIIIPORATIaN - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-162
TC74AC157P/F/FN,TC74AC158P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L=50pF, RL =5OOQ, Input t r =t,=3ns)
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX.
Voc
3.3±0.3
7.2
12.2
Propagation Delay Time tpLiI
(A, B-Y) •
7.9
5.0±0.5
5.5
tl~IL
Propagation Delay Time
(A, B-Y) ••
tpLiI
3.3±0.3
5.0±0.5
-
tl~11.
Propagation Delay Time
(SELECT-Y)
tpLIl
tpliL
3.3±0.3
5.0±0.5
-
Propagation Delay Time tplJI
3.3±0.3
(ST-Y)
5.0±0.5
tpl [I.
Input Capacitance
CN
Power Dissipation
CIU(l) TC74AC157
Capacitance
TC74AC158
Note (I) C FD is defined as the value of the internal equivalent
operating current consumption without load.
Average operating current can be obtained by the equation:
IcctpO=C FD • Voc' fl,'; +IOC 14(per bit)
(2).
for TC74AC157 only
•• for TC74ACl58 only
-
-
Ta--40-85"C
UNIT
MIN. MAX.
1.0
14.0
1.0
9.1
7.3
5.7
12.4
8.2
1.0
1.0
14.3
9.4
8.5
6.3
14.5
9.1
1.0
1.0
16.7
10.5
ns
-
14.6
8.6
1.0
16.8
9.2
6.4
1.0
10.6
5
10
10
93
pF
98
capacitance which is calculated from the
---------------------------------------------------------------~I~ ~R~N
AC-163
TC74ACT157P/F/FN, TC74ACT158P/F/FN
TC74ACT167P/F/FN QUAD 2-CHANNEL MULTIPLEXER
TC74ACT168P/F/FN QUAD 2-CHANNEL MULTIPLEXER INVERTING)
The TC74ACT157 and the TC74ACT158 are advanced high
speed CMOS QUAD 2-CHANNEL MULTIPLEXER's
fabricated with silicon gate and double-layer metal
wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low Power dissipation.
These devices may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
These devices consist of four 2-input digital
multiplexers with common select and strobe inputs.
The TC74ACTl58 is an inverting multiplexer while the
TC74ACT157 is a non-inverting multiplexer.
When the STROBE input is held high, selection of the data
is inhibited and all the outputs go low in the case of the
ACT157 and high in the case of the ACT158.
.. t'he- SELECT decoding determines whether the A or B
inputs get routed to their corresponding Y outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. ~d = 5.lns (typ.) at Vee = 5V
• Low Power Dissipation ............... Icc=8.uA(Max.) at Ta=25"C
• Compatible with TTL outputs .. · .. · VIL =O.8V (Max.)
V IH =2.0V (Min.)
• Symmetrical Output Impedance .. ·11 oHI=IoL=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpllL
• Pin and Function Compatible with 74F157/158
1
P(DIP16-P-300A)
1.~16~
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
TC74ACT157
SELECT 1
16
lA
2
15
ST
lB
3
14
4A
Vee
1Y
4
13
4B
2A
5
12
4Y
2B
6
11
3A
2Y
7
10
3B
GND
8
9
3Y
SELECT 1
16
Vee
lA
2
15
ST
lB
3
14
4A
lY
4
13
4B
2A
6
12
4Y
2B
6
11
3A
2Y
7
10
3B
GND
8
9
3Y
(TOP VIEW)
TRUTH TABLE
TC74ACT158
INPUTS
OUTPUT
ST
SELECT
A
B
H
X
X
X
Y(157) Y(158)
L
H
L
L
L
X
L
H
L
L
H
X
H
L
L
H
X
L
L
H
L
.H
X
H
H
L
(TOP VIEW)
X: Don't Care
~IBA ca~~aN------------------------------------------------------------
AC-164
TC74ACT157P/F/FN, TC74ACT158P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vex/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vex
VIN
Vem
11K
I()(
lem
lex
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee +0.5
-0.5 -Vex+0.5
±20
±50
±50
±100
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
°C
"C
*500mW in the range of Ta=
-40·C- 65"C. From Ta=65"C
to 85·C a derating factor of
-lOmWrC shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vex
Input Voltage
VIN
Output Voltage
VOUT
Operating Temperature
Topr
Input Rise.and Fall Time dt/dv
DC
ELECTRICAL
VALUE
4.5-5.5
o -Vee
0- Vex
-40 - 85
0-10
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Va-!
Low-Level
Output Voltage
VCL
Input Leakage Current
liN
lex
Quiescent Supply Current
•
.6Icc
TEST CONDITION
100=-50/1 A
loo=-24mA
loo=-75mA*
Ia..=50JlA
YiN=
ICL=24mA
VIHor VIL
ICJL=75mA*
VIN =Vex or GND
VIN =Vex or GND
PER INPUT: V IN = 3. 4V
OTHER INPUT:Vex or GND
VIN =
VIHor VIL
Ta=-40-85"C
Ta=25"C
Vex MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
2.0
2.0
1
5.5
4.5
V
0.8
0.8
1
5.5
4.5 4.4
4.5
4.4
V
3.80
4.5 3.94
5.5
3.85
4.5
0.0
0.1
0.1
V
4.5
0.36
0.44
5.5
1. 65
- ±O.l. 5.5
±1.0
JlA
5.5
8.0
80.0
5.5
-
-
1.35
-
1.5
rnA
1 This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a 10ms maximum duration.
-------------------~------...;....---TO.HI8A
AC-165
CORPORATION
TC74ACT157P/F/FN, TC74ACT158P/F/FN
IEC LOGIC. SYMBOL
TC74ACT157
TC74ACT158
(4)
lA
18
2A
lY
7
2Y
9
3Y
12
4Y
1Y
SYSTEM DIAGRAM
TC74ACT157
TC74ACT158
SELECT~
-
ST
15
'"
lA
18
-
'"
3
IV
6
2'(
2A
2Y
28
3A
38
4A
48
11
10
3'(
14
13
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-166
TC74ACT157P/F/FN, TC74ACT158P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L=60pF, RL =6000, Input t r =t,=3ns)
PARAMETER
SYMBOL TEST CONDITION
Th=25°C
Vee
MIN.
TYP.
MAX.
Th = -40-85°C
UNIT
MIN.
MAX.
Propagation Delay Time
(A, B-Y) *
tpLH
tpHL
5.0±0.5
-
5.5
8.0
1.0
9.1
Propagation"'pelay Time
(A,B-y) **
tpLH
tpHL
5.0±0.5
-
5.8
8.6
1.0
9.8
Propagation Delay ]'ime
(SELECT-Y, Y) *
~LH
tpHL
5.0±0.5
-
6.9
11.4
1.0
13.0
Propagation Delay ]'ime
(SELECT-Y, Y) **
~LH
tpHL
5.0±0.5
-
7.4
11.9
1.0
13.5
Propa&illon !?elay Time
(ST-Y, Y) *
tpLH
tpHL
5.0±0.5
-
6.8
10.8
1.0
12.3
PrOPa&illolL Delay Time
(ST-Y) **
tpLH
tpHL
5.0±0.5
-
7.2
11.3
1.0
12.8
Input Capacitance
CIN
-
5
50
51
10
-
10
-
-
Power Dissipation
Capacitance
ns
CPD (1) TC74ACT157
TC 74ACT 158
-
pF
Note (1) Cro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iccq,o=CR) • Vo:;. f"" +10:; 14(per bit)
(2).
for TC74ACTl57 only
•• for TC74ACT158 only
------------------------------TQ8HIIIA
AC-167
CORPORATION
•"/4""". our Irlrl1, •
\'/4""".O"lr Irlrl1,
TC74AC162P/F/FN, TC74AC163P/F/FN
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
TC74AC160P/F/FN DECADE, ASYNCHRONOUS CLEAR
TC74AC161P/F/FN BINARY... ASYNCHRONOUS CLEAR
TC74AC162P/F/FN DECADe, SYNCHRONOUS CLEAR
TC74AC163P/F/FN BINARY SYNCHRONOUS CLEAR
The TC74AC160, 161, 162 and 163 are advanced high
speed
CMOS
SYNCHRONOUS
PRESETT ABLE
COUNTERs fabricated with silicon gate and double-layer
metal wiring C2M OS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The TC74AC160/162 are BCD decade counters and the
TC74AC161/163 are 4 bit binary counters.
The CK input is active OIl the rising edge. Both LOAD and CLR
inputs are active when low.
Presetting of all four IC's is synchronous to the rising
edge of CK.
The clear function of the TC74AC1621163 is synchronous to CK, while the TC74AC160/161 are cleared
asynchronously.
Two enable inputs (ENP and ENT) and CARRY
OUTPUT are provided to enable easy cascading of
counters, which facilitates easy implementation of n-bit
counters without using external gates.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. f MAX =170MHz(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=8ttA(Max.) at Ta=25"C
• High Noise Immunity ............... VNIH=V~IL=28% Vcc(Min.)
• Symmetrical Output Impedance .. ·11cH 1=101.. =24mA(Min.)
Capability of driving SOQ
transmission lines.
• Balanced Propagation Delays ...... tpLH '" tpHI..
• Wide Operating Voltage Range'" Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 160/1611162/163
1
P(DIP16-P-300A)
1.~1.~
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
CLRI
16Vcc
CARRY
15 OUTPUT
140"
CK2
A3
DATA
IN
64
1308
C5
120c
06
OUTPUTS
110D
ENP7
10ENT
GN08
9 LOAD
(TOP VIEW)
IEC LOGIC SYMBOL
TC74AC160
TC74AC161
TC74AC162
TC74AC163.
TCJSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-168
TC74AC160P/F/AN,TC74AC161P/F/FN,
TC74AC162P/F/AN, TC74AC163P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Va;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Va;
VIN
Your
11K
10K
lour
Ia;
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Va;+0.5
-0.5 -Va;+0.5
±20
±50
±50
±125
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65°C
to 85"C a derating factor of
-lOmW/"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
o -Va;
o -Va;
-40 - 85
SYMBOL
Va;
VIN
Your
Topr
dt/dv
UNIT
V
V
V
"C
0-lOO(Va;=3.3±0.3V)
0- 20(Va;= 5 ±0.5V)
ns/v
CHARACTERISTICS
,---
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vrn
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
liN
Ia;
Ta=25"C
Ta=-40-85"C
UNIT
Va; MIN.
TYP. MAX. MIN. MAX.
2.0 1. 50
1. 50
V
3.0 2.10
2.lO
5.5 3.85
3.85
2.0
0.50
0.50
V
3.0
0.90
0.90
5.5
1. 65
1. 65
2.0
1.9
2.0
1.9
Irn=-50#A
3.0
2.9
3.0
2.9
VIN =
4.5
4.4
4.5
4.4
V
Irn=-4mA
3.0 2.58
2.48
VIHor VIL
Irn=-24mA 4.5 3.94
3.80
Irn=-75mA* 5.5
3.85
2.0
0.0
0.1
0.1
IOL= 50#A
3.0
0.0
0.1
O. I
VIN=
4.5
0.0
0.1
O. I
V
IOL=12mA
3.0
0.36
0.44
VIHor VIL
IOL=24mA
4.5
0.36
0.44
5.5
IOL =75mA*
1. 65
- +l.0
YiN =Va; or GND
5.5
+0.1
#A
VIN =Va; or GND
5.5
8.0
80.0
TEST CONDITION
• :Thls spec indicates the capability of driving 50n transmission lines.
One output should be tested at a time for a lOms maximum duration.
-------------------~----------TOSHIBA
AC-169
CDRPDRATION
TC74AC16OP IF I FN,TC74AC161P I FI FN,
TC74AC162P/F/FN,TC74AC163P/F/FN
TRUTH TABLE
TC74AC160/161
TC74AC162/163
INPUTS
INPUTS
CLR
L
LD
X
H
L
X
X
H
H
X
L
H
H
H
L
X
H
H
X
X
H
ENP ENT CK CLR
X
X
X
L
Note X
H
H
S
S
S
S
X
L
LD
X
L
OUTPUTS
Qc
QD
L
L
L
L
A
C
D
B
NO CHANGE
NO CHANGE
COUNT UP
NO CHANGE
QA
ENP ENT CK
X
X S
X
X
H
H
X
L
H
H
H
H
L
H
H
X
X
X
X
S
S
S
S
L
X
FUNCTION
QB
RESET TO "0·
PRESET DATA
NO COUNT
NO COUNT
COUNT
NO COUNT
: Don't care
A, B, C, D : Logic Level of Data Inputs
Carry
: CARRY=ENT·Q,,·QB·Qc·Qo······(TC74AC160/162)
CARRY=ENT·Q,,·QB·Qc·Qo·· .... (TC74AC161/163)
TIMING CHART (TC74AC160/162: DECADE COUNTER)
CLR
LOAi)
A
DATA
INPUTS
DON'T CARE UNTIL LOAD GOES LOW
B
C
~#//##$$#ff$4W'~
0
~ff##$~
CK
ENP
ENT
QA
wi
Os
~ LJI~--.-
Qc
~~------------~Ir--------------
OUTPUTS
OD
I
~~
,
CARRY OUTPUT
:
I
I
I,
I,
'
,,8
___....
'I
1:,---,
I
:7
!
!
I
I
::
, II
!,
!
9
I,
I~_--~~~~r------------------1
2
3 I
0
. 1....- - - C O U N T - - - . j . I - - - - I N H I B I T - - -
ASYNC SYNC PRESET
CLEAR CLEAR
(160) (162)
~IIIA CQIIUIQIIIATION - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-170
TC74AC160P/F/FN,TC74AC161P/F/AN,
TC74AC162P/F/FN,TC74AC163P/F/AN
TIMING CHART (TC74AC161/163:BINARY COUNTER)
CLR
LOAD
A
DATA
INPUTS
DON'T CARE UNTIL LOAD GOES LOW
B
C
0
CK
I
I
ENP
ENT
1
I
I
irl-+----------------,
--~I~--~I
~----~
I
Ir-~--------------_T--------~
I
II
I
QA
I
~ __-+I---i
I
I
I
I
Qs
~?J
Qc
~~
OUTPUTS
I
1
QD
CARRY OUTPUT
~LJ
I 1I 1I
I
,
I
1
I
I
1
,
'12
I
I
.. • •
1
1
I!
I
I
1
1
I
I
I
I
1
1
1
I
I
I
I
I
I
I
1
1
113
14
n
15
,
,
0
I
I•
COUNT
/\SYNC SYNC PRESET
CLEAR CLEAR
(161) (163)
1
21
I
I
".
INHIBIT
-------------------------------------------------~HIBACaAPOAAnON
AC-171
TC74AC160P/F/FN,TC74AC161P/F/FN,
TC74AC162P/F/FN,TC74AC163P/F/FN
SYSTEM DIAGRAM
TC74AC160ITC74AC162
C~~1
__~__________________- - ,
ENT 10
7 -n......J
ENP-
CARRY
;::=:::...!:.--..______-+L~t-<1>-=15 OUT
A 3
1--+-cL:>-1_2
Oc
1-----o-.~
LE'
CK
.-+
-_.-
__ J
~~
---~
~
AC74AC166PI FI FN
TIMING
REQUIREMENTS (Input t r =t, =3ns)
PARAMETER
SYMBOL
TEST CONDITION
Vee
Ta 25"C
Ta 40-85"C
UNIT
TYP.
LIMIT
LIMIT
Minimum Pulse Width
(CK)
t\\{H)
t\\{L)
3. 3±0. 3
5. O±O. 5
-
7.0
5.0
7.0
5.0
Minimum Pulse Width
(CLR)
t\\{L)
3. 3±0. 3
5. O±O. 5
-
8.0
5.0
8.0
5.0
Minimum Set-up Time
(SI,PI)
t5
3. 3±0. 3
5. O±O. 5
-
8.0
4.0
8.0
4.0
Minimum Set-up Time
(S/L)
t5
3. 3±0. 3
5.0±0.5
-
7.0
4.0
7.0
4.0
Minimum Hold Time
(SI,PI)
th
3. 3±0. 3
5.0±0.5
-
-
0.5
0.5
0.5
0.5
Minimum Hold Time
(S/L)
th
3. 3±0. 3
5. O±O. 5
-
1.0
1.0
1.0
1.0
Minimum Removal Time
(CLR)
trem
3.3±0.3
5. O±O. 5
-
4.0
1.5
4.0
1.5
AC
ELECTRICAL
CHARACTERISTICS (C L =50pF,R L =500Q,lnput
PARAMETER
SYMBOL
TEST CONDITION
Vee
ns
tr =t, =3ns)
Ta 25"C
Ta 40-85"C
UNIT
MIN. TYP. MAX. MIN. MAX.
Propagation Delay Time
(CK-QH)
t pLH
tpHL
3. 3±0. 3
5. O±O. 5
-
9.4
6.6
16.1
10.0
1.0
1.0
18.3
11.4
Propagation Delay Time
(CLR-QH)
tpl-JL
3. 3±0. 3
5. O±O. 5
-
~.2
6.4
15.2
9.6
1.0
1.0
17.4
10.9
Maximum Clock
Frequency
£MAX
3. 3±0. 3
5. O±O. 5
55
90
105
150
-
55
90
-
Input Capacitance
CIN
-
5
10
-
-
ns
-
-
10
-
MHz
pF
CPD(()
Power Dissipation Capacitance
67
Note(() C PD IS defmed as the value of the mternal equIvalent capacItance whIch IS calculanted from the
operating current consumption without load.
Averating operating current can be obtained by the equation:
~IIIA COIlUlOAATlON ---------~-------------------
AC-186
TC74AC174P I FI FN
HEX D-TVPE FLIP FLOP WITH CLEAR
The TC74AC174 is an advanced high speed CMOS HEX
D-TYPE FLIP FLOP fabricated with silicon gate and
double-layer metal wiring C2 MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL, while maintaining the CMOS low
power dissipation.
Information signals applied to D inputs are transferred to the Q
outputs on the positive going edge of the clock pulse.
When the CLR input is held low, the Q outputs are in the low logic
level independent of the other inputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. f~1AX=180MHz(typ.) at Vo::,=5V
• Low Power Dissipation ............... Icc =8.uA(Max.) at Ta=25"C
• High Noise Immunity .. " .......... · V:-.JIH=VNIL =2896 Vcc(Min.)
• Symmetrical Output Impedance .. ·!IoH! =IoL=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH '" tpi-lL
• Wide Operating Voltage Range .. · Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 174
1
P( DIP16-P-300A)
1.~1.~
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
CLR 1
16 Vee
01 2
1506
01 3
14 06
02 4
13 05
02 5
12 05
03 6
11 04
03 7
10 04
GNO 8
9 CK
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
INPUTS
OUTPUT
FUNCTION
CLR
D
CK
a
L
x
X
L
CLEAR
H
L
J
L
-
H
H
J
H
-
H
X
1..
an
NO CHANGE
erR
CK
01 (3)
02 (4)
(2) 01
(5) 02
03
04
05
06
(7) 03
(10) 04
(6)
(11)
(13)
(14)
(12) 05
(15) 06
AC-187
~
~
C
~
_____________________ TCMa...
I
________________________________________
~
X : Don't care
TC74AC174P I FI FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Vour
11K
10K
lOUT
lee
PI)
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±50
±50
±200
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-40·C- 65·C. From Ta=65·C
to 85°C a derating factor of
-10m W/·C shall be applied
until300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vee
0- Vee
-40 - 85
UNIT
V
V
V
°C
o -lOO(Vee =3.3±O.3V)
o - 20(Vee= 5 ±O.5V)
ns/v
SYMBOL
Vee
VIN
Your
Topr
dt/dv
CHARACTERISTICS
r--
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOl
Input Leakage Current
Quiescent Supply Current
lIN
lee
Ta=25°C
Ta= -40-85"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2. 0 1. 50
1.50
V
2. 10
3.0 2. 10
5. 5 3.85
3.85
2.0
0.50
0.50
V
0.90
3.0
0.90
5. 5
1. 65
1. 65
2.0
2.0
1.9
1.9
IQH=-50ttA
3.0
2.9
3.0
2.9
Vu,;=
4.5
4.4
4.5
4.4
V
IQH=-4mA
3.0
2.58
2~ 48
VIHor VIL
IQH=-24mA 4.5 3.94
3.80
3.85
IQH=-75mA* 5. 5
2. 0
0.0
0.1
0.1
0.1
0.0
0.1
3.0
IOl=50tt A
VIN=
4.5
0.0
0.1
0.1
V
3.0
IOl=12mA
0.44
0.36
VIHor VIL
0.36
4.5
0.44
IOl=24mA
5. 5
1. 65
IOl=75mA*
- ±0.1 - ±1.0
5.5
VIN =Vee or GND
tt A
5.5
8.0
VIN =Vee or GND
80.0
TEST CONDITION
• :This spec indicates the capability of dnvmg 50n tranSIlliSSlOn Imes.
One output should be tested at a time for a lOms maximum duration.
TO.HIIIA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-188
TC74AC174P I FI FN
SYSTEM DIAGRAM
D2
D1
D4
D3
D6
D6
CK
15
06
TIMING REOUIREMENTS(lnput tr=tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vee
Ta-25"C
TYP.
LIMIT
Ta--40-85"C
UNIT
LIMIT
Minimum Pulse Width
(CK)
tW(L)
tW(H)
3.3±O.3
5.0±0.5
-
7.0
5.0
7.0
5.0
Minimum Pulse Width
(CLR)
tW(L)
3.3±0.3
5.0±0.5
-
7.0
5.0
7.0
5.0
Minimum Set-up Time
ts
3.3±0.3
5.0±0.5
-
7.0
4.0
7.0
4.0
Minimum Hold Time
th
3.3±0.3
5.0±0.5
-
1.0
1.0
1.0
1.0
Minimum Removal Time
(CLR)
trem
3.3±0.3
5.0±0.5
-
6.0
3.5
6.0
3.5
AC ELECTRICAL CHARACTERISTICS(C L =50pF, RL =5000, Input t r =tf=3ns)
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX.
Vee
Propagation Delay Time tpUi
3.3±0.3
8.5
14.4
tpHL
5.0±0.5
6.7
9.6
(CK-Q)
Propagation Delay Time
(CLR-Q)
tpliL
3.3±0.3
5.0±0.5
--
-
8.2
6.3
13.9
9.0
ns
Ta--40-85"C
UNIT
MIN. MAX.
1.0
16.6
11.0
1.0
ns
16.0
1.0
1.0
10.4
- MHz
110
60
150
90
Input {;apacitance
5
(;IN
10
10
pF
Power Dissipation Capacitance Cpo(1)
74
Note (1) C I'D is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC tp}=C PD • V:U~T:...:S~_ _ _ _ _ _ _ _ _ _ _--,
The TC74ACT240, 241 and 244 are advanced high speed
CMOS OCTAL BUS BUFFERs fabricated with silicon
gate and double-layer metal wiring C2MOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The 74ACT240 is an inverting a-state buffer having two
active-low output enables. The TC74ACT241 and
TC74ACT244 are non-inverting a-state buffers that differ
only in that the 241 has one active-high and one activelow output enable, and the 244 has two active-low output
enables.
These devices are designed to be used with a-state
memory address drivers, etc.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P( DIP20-P-300A)
m~,.~
1
1
F(SOP20-P-300) FW(SOL20-P-300)
TRUTH TABLE
FEATURES:
• High Speed ................................. tpd=5.0ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=8IlA(Max.) at Ta=25"C
• Compatible with TTL outputs .. · .. • V IL =O.8V (Max.)
V IH =2.0V (Min.)
• Symmetrical Output Impedance ···1 I oHI =IoL=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays •••••. tpLH"o tpHL
• Pin and Function Compatible with 74F240/244
G
L
L
H
INPUTS
GA
H
H
L
OUTPUTS
An
Vn
yn......
L
L
H
Z
H
.L
Z
H
X
: for TC74ACT241 only
At:.. : for TC74ACT240 only
X
: Don't Care
Z
: High Impedance
t:..
PIN ASSIGNMENT(TOP VIEW)
"(3
TC74ACT244
.TC74ACT241
TC74ACT240
20 Vee
lG
20 Vee
lG 1
20 Vee
lAl 2
192G
2Y4 3
18 tv1
4
'--'-.,-,-" 172M
lAl 2
192G
1A1 2
192G
2Y4 3
18 lY1
2Y4 3
18 tvl
'L-rl 17 2A4
4
172A4
1A2
2Y3 5
161Y2
2Y3 5
16 tv2
2Y3 5
161Y2
lA3 6
152A3
1A3 6
152A3
lA3 6
152A3
2Y2 7
14 1Y3
2Y2 7
14 lY3
2Y2 7
14 tv3
lA48
132A2
lA4 8
132A2
1A4 8
132A2
1A2
4
\...L......
1A2
2Yl 9
121Y4
2Yl 9
12 1Y4
2Y1 9
12 tv4
GND 10
11 2Al
GND 10
11 2Al
GND 10
11 2Al
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOSHIBA CORPORATION
AC-205
TC74ACT240P IFIFW, TC74ACT241PIF/FW, TC74ACT244P IFIFW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
Voor
11K
I(l(
Ioor
lee
Po
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5-6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±200
500(DIP)*/180(SO?)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C should be applied
up to300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage·
Vee
Input Voltage
VIN
Output Voltage
Voor
Operating Temperature
Topr
Input Rise and Fall Time dt/dv
DC
ELECTRICAL
VALUE
4.5-5.5
0- Vee
0- Vee
-40 - 85
0-10
CHARACTERISTICS
PARAMET)J:R
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
VIN=
VIHorVu.
Low-Level
Output Voltage
Va.
ViN=
VUior VIL
3-State Output
OfC-State Current
ICE
VIN=VIH or VIL
Voor =Vee or GND
Input Leakage Current
lIN
lee
Quiescent Supply Current
.1Icc
TEST CONDITION
UNIT
V
V
V
"C
ns/v
-
Ta=25"C
Ta=-40-85"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
2.0
2.0
l
5.5
4.5
V
0.8
0.8
l
5.5
4.5 4.4
4.5
4.4
V
4.5 3.94
3.80
5.5
3.85
4.5
0.0
0.1
0.1
- 0.36
V
4.5
0,44
5.5
1. 65
-
Ioo=-:50p.A
Ioo=-24mA
Ioo=-75mA.
Ia.=50J,tA
Ia.=24mA
la.=75mA.
VIN =Vee or GND
VIN =Vee or GND
PER INPUT:VIN =3.4V
OTHER INPUT:Vee or GND
..
capablbt)'
-
-
-
--
-
-
--
5.5
5.5
5.5
5.5
-
-
-
±0.5
-
-
±O.l
8.0
-
1.35
---
--
±5.0
±1.0
80.0
1.5
J.tA
rnA
• :This spec indicates the
or driving 500 transmission lines.
One output should be tested at a time ror a 10ms maximum duration.
TOSHIBA COAPOIIIATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-206
TC74ACT240P IF IFW, TC74ACT241 PIF IFW, TC74ACT244PIF/FW
IEC LOGIC SYMBOL
1A1WI_"':;"_~
1A2
1A3
1M
TC74ACT244
TC74ACT241
TC74ACT240
1Y1
1Y1
1'2
1Y3
1'i'4
2Y1
2'2
2V3
2V4
1Y2
1Y3
1Y4
1A4
20
2G
2A1
2A2
2A3
2M
2A1
2Y1
~ J!L---.lr----l__~~L ~
2A4 (I
2Y4
AC ELECTRICAL CHARACTERISTICS(C L=60pF, RL =6000, Input t r=t,=3ns)
Ta=25"C
Ta- 40 -85"C UNIT
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX. MIN. MAX.
Vex
Propagation Delay Time
t pLH
t p1-IL
5.0±0.5
-
5.7
B.O
1.0
9.0
Output Enable Time
tl17L
ttmi
5.0±0.5
-
6.0
9.0
1.0
10.5
Output Disable Time
tpLZ
tl1HZ
5.0±0.5
-
5.9
8.5
1.0
10.0
ns
Input Capacitance
CIN
5
10
10
Carr
Output Capacitance
10
pF
Power DlssipationC_apacitance ' 9_PDUl
25
Power Dissipation Capacitance" CPDm
29
Note (I) Cro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IextpD=CPD • Va;oCIN+I a;/8(per bit)
(2)'
for TC74ACT240 only
•• Cor TC74ACT2411244
-
-
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOSHIBA CORPORATION
AC-207
TC74AC245P I FI FW, Tl;14ACti40P I FI FR,
TC74AC643P IFf FW
OCTAL BUS TRANSCEIVER
TC74AC245P/F/FW 3-STATE. NON-INVERTING
TC74AC840P/F/FW 3-STATE.INVERTING
...
TC74AC643P/F/FW 3-STATE.INVERTING AND·NON~INVERTINGr-_~_ _ _ _-",,_ _ _ _---,
The TC74AC245, 640 and 643 are advanced high :spefKl
CMOS OCTAL BUS TRANSCEIVERs fabricated with·
silicon gate and double-layer metal wiringC 2 MOS
technology.
They achieve the high speed opel'ation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
.
They are intended for two-way asynchronous
communication between data bu·sses. The direction of ·t··
data transmission is determined by the level of the DIIl~.
input.
The enable input (0) can be used to disable the device
so that the busses are effectively isolated.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP20-P-300A)
.;"~m~
1
·1
F(SOP20-P-300)
FW(SOL20-P-300)
APPLICATION NOTES
FEATURES:
• High Speed ................................. tpd=3.9ns(typ.) at Vcc";5V
• Low Power Dissipation ............... Icc=8JlA(Max;) at Ta=25"C
• High Noise Immunity .... ·........ ·· V N1H =VNIL=28!16 Vcc(Min.)
• Symmetrical Output Impedance ... \ Irn \ =IOL=24mA(Min.) .
Capability of driving SOQ
transmission lines,
• Balanced Propagation Delays ...... tpLH"'tpHL
• Wide Operating Voltage Range .. • Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F: 245/640/643
1) Do not apply a signal to any
bus timninal when it is in the out
. ,put mode. Damage may result.
2) All floating (high impedance)
bus terminals must have their
input levels fixed by means of pull
up or pull down resistors or bus
terminator IC's such as the
TOSHIBA TC40117BP.
PIN ASSIGNMENT(TOP VIEW)
TC74AC245
OIR
Al
20 Vee
2
TC74AC643
TC74AC640
19
G
OIR
DIR
Al.2
Al
A2 3
18 B 1
A2 3
A3 4
17 B2
A3
A4 5
16 B3
A4
A5 6
15 B4
A5
A6 7
14 B5
A6 .7
A7 8
13 B6
A8 9
12 B7
2
A2 3
18 B 1
A3 4
17 B2
'A4 5
16 B3
A5 6
15 B4
14 B5
A6 7
14 B5
A7 8
1386
A7 8
13 B6
A8 9
1287
A8 9
12B7
18 B 1
16 B3
Ii
11 B8
11 B8
11 B8
TOIIHIIIA CQRIiIOIIIATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-208
TC74AC245PI FI AN, TC74AC640PI FI AN,
TC74ACI43P I FI AN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vex:/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vex:
VIN
Voor
11K
I(](
loor
lex:
Po
Ta'c
TL
VALUE
-0.S-6.0
-O.S -Vex: +0.5
-O.S -Vex:+0.5
±20
±SO
±SO
±200
5OO(DIP)./180(SOP)
-6S -ISO
300
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
*500mW in the range of Ta=
-40·C- 65"C. From Ta=65·C
to 85"C a derating factor of
-lOmWI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITI"
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
dt/dv
UNIT
V
V
V
"C
VALUE
2.0-S.S
o-Vex:
0- Vex:
-40 - 85
SYMBOL
Vex:
VIN
Voor
Topr
0-UI0(Va;=3.3±0.3V)
ns/v
0- 2O(Vex:= 5 ±0.5V)
CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
V IH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VCli
VIN =
V IH or VIL
-
Ta=25"C
Vex: MIN. TYP. MAX.
2.0 1. 50
3.0 2.10
5.5 3.85
2.0
0.50
0.90
3.0
1. 65
5.5
2.0 1.9
2.0
3.0 2.9
3.0
bi=-SOIlA
4.5 4.4
4.5
3.0 2.58
bt=-4mA
bJ=-24mA 4.5 3.94
lcJi=-7SmA. 5.5
0.0
2.0
O. I
Ia,=SOIlA
3.0
O. I
0.0
4.5
O. I
0.0
0.36
3.0
!a. = 12mA
0.36
4.5
Ia.=24mA
5.5
Ia.=7SmA.
TEST CONDITION
-
VIN=
Low-Level
Output Voltage
Va.
3-State Output
Off-State Current
ICE
VIN=VIH or VIL
Voor=Vex: or GND
5.5
liN
VIN =V ex: or GND
VIN=Vex:orGND
5.5
5.5
Input Leakage Current
Quiescent Supply Current
VIH or VIL
lex:
• :This spec indicates the capability of driving 500 tranamiulon Unes.
One output should be tested at a time for a IOms maximum duration.
-
Ta=-40-85"C
UNIT
MIN. MAX.
1. 50
V
2.10
3.85
0.50
V
0.90
1. 65
1.9
2.9
4.4
V
2.48
3.80
3.85
O. I
O. I
O. I
V
0.44
0.44
1. 65
-
±0.5
-
±5.0
-
±O.l
8.0
-
±1.0
80.0
-
-
/lA
--------'----------------------TaBHIBA CORPORATION
AC-209
TC74AC245P I FIFW, TC74AC640Pl F1M,
TC74AC643P I FI FW
IEC LOGIC SYMBOL
TC74AC245
TC74AC640
TC74AC643
TRUTH TABLE
INPUTS
FUNCTION
OUTPUTS
G
DIR
A BUS
BBUS
AC245
AC640
AC643
L
L
OUTPUT
INPUT
A=B
A-B
A-B
L
H
INPUT
OUTPUT
B=A
B=A
B=A
H
X
Z
Z
Z
High Impedance
X : "H" or "L"
Z : High Impedance
~1"caRPa~-----------------------------------------------------
AC-210
TC74AC245P I FI FW, TC74AC640P I FI FW,
TC74AC643P/F/FW
AC ELECTRICAL CHARACTERISTICS(C L =60pF, R L =600Q, Input t r =tf=3ns)
'1'a-25"C
PARAMETER
SYMBOL TEST CONDITION
Vcr;
MIN. TYP. MAX.
3.3±0.3
7.0
t pLli
10.9
Propagation Delay Time*
5.0±0.5
7.5
5.0
t l~lL
'1'a- 40-85"C
UNIT
MIN. MAX.
12.4
1.0
1.0
8.5
Propagation Delay Time
t~.1l
t ~lL
3.3±0.3
5.0±0.5
-
6.4
4.8
10.0
7.0
1.0
1.0
11.4
8.0
Output Enable Time
tpZL
tPll-l
3.3±0.3
5.0±0.5
-
9.3
7.1
15.3
10.5
1.0
1.0
17.4
12.0
t plZ
3.3±0.3
5.0±0.5
-
**
ns
7.1
11.4
1.0
13.0
5.9
8.7
1.0
10.0
Input Capacitance
C!:'\
DlR. G
5
10
10
CliO An, Bn
Bus Input Capacitance
13
pF
TC74AC245
38
Power Dissipation
CpD(l)
Capacitance
TC74AC640/643
36
Note (1) C ro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icr; (pD=C PD • Va:;. f IX + I a:; /8( per bit)
(2) 0 : for TC74AC245/643 only.
00 : for TC74AC640 only
Output Disable Time
tpHZ
-
------------------------------------------------------------~laA C~~
AC-211
TC74ACT245PI FI FW, TC74ACT640P I FI FW
OCTAL BUS TRANSCEIVER
TC74ACT245P/F/FW
3-STATE. NON-INVERTING
TC74ACT640P/F/FW
3-STATE.INVERTING
The TC74ACT245 and 640 are advanced high speed
CMOS OCTAL BUS TRANSCEIVERs fabricated with
silicon gate and double-layer metal wiring C 2 MOS
technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These devices may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
They are intended for two-way asynchronous
communication between data busses. The direction of
data transmission is determined by the level of the DIR
input.
The enable input (G) can be used to disable the device
so that the busses are effectively isolated.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd = 4.7ns (typ.) at Vcc = 5V
• Low Power Dissipation ............... Icc=8IlA(Max.) at Ta=25"C
• Compatible with TTL outputs ...... VIL =O.8V (Max.)
V IH =2.0V (Min.)
• Symmetrical Output Impedance .. ·1 I oHI =IoL=24mA(Min.)
Capability of driving SOQ
transmission lines.
• Balanced Propagation Delays ...... tpLH"otpHL
• Pin and Function Compatible with 74F245/640
P(DIP20-P-300A)
,.~,.~
1
1
F(SOP20-P-300)
FW(SOL20-P-300)
APPLICATION NOTES
1) Do not apply a signal to any
bus terminal when it is in the out
put mode. Damage may result.
2) All floating (high impedance)
bus terminals must have their
input levels fixed by means of pull
up or pull down resistors or bus
terminator IC's such as the
TOSHIBA TC40117BP.
PIN ASSIGNMENT(TOP VIEW)
TC74ACT245
DIR
TC74ACT640
20 Vee
DIR
19G
Al
A2 3
18 B 1
A2 3
18 Bl
A3 4
17 B2
A3 4
17 B2
A4 5
16 B3
A4 5
16 B3
A5 6
15 B4
A5 6
15 B4
A6 7
14 B5
A6 7
14 B5
A7 8
13 B6
A7 8
13 B6
A8 9
12 B7
A8 9
12 B7
Al
2
11 B8
20 Vee
2
19 G
11 B8
TOIIHI-.A CClIllIilClAATlDN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-212
TC74ACT245P/F/RN,TC74ACT840P/F/RN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vcr;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vcr;
VIN
Vour
11K
10K
lour
Icr;
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vcr;+0.5
-0.5 -Vcr;+0.5
±20
±50
±50
±200
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85·C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vcr;
Input Voltage
VIN
Output Voltage
VOUT
Operating Temperature
Topr
Input Rise and Fall Time dt/dv
DC
ELECTRICAL
VALUE
4.5-5.5
0- Vcr;
0- Vcr;
-40 - 85
0-10
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
r---
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
YiN=
VIHor VIL
Low-Level
Output Voltage
Va.
YiN=
VIHor VIL
3-State Output
Off -State Current
~
VIN=VIH or VIL
Vour =Vcr; orGND
Input Leakage Current
Quiescent Supply Current
TEST CONDITION
Vcr;
4.5
l
2.0
-
-
2.0
-
V
l
-
-
0.8
-
0.8
V
4.4
3.94
-
4.5
-
4.4
3.80
3.85
-
--
V
5.5
4.5
Im=-5O ttA
Im=-24mA
Im=-75mA*
Ia..=50,uA
Ia.=24mA
Ia.=75mA*
VIN =Vcr; or GND
VIN =Vcr; or GND
PER INPUT:VIN -3.4V
~lcc
OTHER INPUT:Vec or GND
liN
lcr;
Ta=-40-85"C
Ta=25"C
UNIT
MIN. TYP. MAX. MIN. MAX.
5.5
4.5
4.5
5.5
4.5
4.5
5.5
5.5
5.5
5.5
5.5
-
-
-
-
-
O. I
0.36
-
±0.5
-
±O.l
8.0
0.0
-
-
-
1.35
-
-
-
0.1
0.44
1. 65
V
±0.5
±1.0
80.0
1.5
,uA
rnA
• :This spec indicates the capability of driving 500 transmission lines.
One output should be ttsted at a time for a 10ms maximum duration.
--------------------~---------TO~IIIA CQR~
AC-213
TC74ACT245P/F/RN,TC74ACT640P/F/RN
IEC LOGIC SYMBOL
TC74ACT245
TC74ACT640
G\!!L~",,----,
OIR
TRUTH TABLE
INPUTS
FUNCTION
OUTPUTS
G
OIR
A BUS
BBUS
L
L
OUTPUT
INPUT
A=B
A=B
L
H
INPUT
OUTPUT
B=A
B=A
H
X
Z
Z
High Impedance
ACT245 ACT640
x : "H" or"L·
Z : High Impedance
~IBACO~--------~----------------------------------------~-----
AC-214
TC74ACT245P/F/RN,TC74ACT640P/F/RN
AC ELECTRICAL CHARACTERISTICS(CL=50pF. RL =5000. Input t r =t f =3ns)
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX.
Vee
• t pUI
Propagation Delay Time
5.0±0.5
5.0
8.0
t pl-IL
••
Propagation Delay Time
tpLH
t pHI.
5.0±0.5
-
Output Enable Time
trill.
trill-l
5.0±0.5
Output Disable Time
t pLZ
tpl-lZ
5.0±0.5
Ta-. 40-85"C
UNIT
MIN. MAX.
1.0
9.0
1.0
9.5
5.7
8.5
-
7.3
12.3
1.0
14.0
-
6.3
9.7
1.0
11.0
ns
Input Capacitance
DIR. G
5
10
10
CIN
CliO
Bus Input Capacitance
An,Bn
13
pF
TC74ACT245
38
Power Dissipation
CPD(l)
Capacitance
43
TC74ACT640
Note (1) C PO is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icctvo=CPD VocoflN+I oc/8(perbit)
(2) • : for TC74ACT245 only .
•• : for TC74ACT640 only
0
---------------------------------------------------------------~I~ c~~~
AC-215
TC74AC257P/F/FN,TC74AC258P/F/FN
TC74AC257P/F/FN 2-CHANNEL MUL TIPLEXER(3-STATE)
TC74AC258P/F/FN 2-CHANNEL MULTIPLEXER(3-STATE,INVERTING
The TC74AC257 and TC74AC258 are advanced high
speed CMOS MULTIPLEXERs fabricated with silicon
gate and double-layer metal wiring C2MOS technolgy.
They achieve the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
Each is composed of four independent 2-channel
multiplexers with common SELECT and OUTPUT
ENABLE(OE).
The TC74AC257 is a non-inverting multiplexer, while the
TC74AC258 is inverting.
If OE is set low, the outputs are held in a
high-impedance state. When SELECT is set low, "A"
data inputs are enabled.
Conversely, when SELECT is high, "B" data inputs are
enabled.
All inputs are equipped with protection citcuits against
static discharge or transient excess voltage.
1
P( DIP16-P-300A)
1.~1.~
F(SOP16-P-300)
FN(SOL 16-P-150)
TRUTH TABLE
FEATURES:
• High Speed ................................. tpd=3.6ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=8,u A(Max.) at Ta=25"C
• High Noise Immunity .............. · VNIH=VNIL =28% Vcc(Min.)
• Symmetrical Output Impedance .. ·1 1m I =IOL =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH";tpliL
• Wide Operating Voltage Range .. · Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 257/258
INPUTS
OUTPUTS
OE
SELECT
A
B
H
X
X
X
Z
Z
L
L
L
X
L
H
L
L
H
X
H
L
L
H
X
L
L
H
H
X
H
H
L
L
X : Don't Care
Z : High Impedance
PIN ASSIGNMENT
TC74AC257
SELECT 1
lA 2
lB 3
lY 4
2A 5
2B 6
2Y 7
TC74AC258
SELECT 1
lA 2
lB 3
IV 4
2A 5
2B 6
16 Vee
15 OE
14 4A
13 4B
12 4Y
11 3A
10 3B
9 3Y
GND 8
2V
16
15
14
13
12
Vee
OE
4A
4B
4Y
11 3A
10 3B
9 3Y
7
GND 8
(TOP VIEW)
(TOP VIEW)
TOSHIBA CORPORATION
AC·216
Y(257) Y(258)
TC74AC257P/F/AN,TC74AC258P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Voor
11K
10K
lour
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP)*/180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
OC
OC
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-lOmW/'C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
Vcr;
VIN
Your
Topr
dt/dv
UNIT
V
V
V
OC
VALUE
2.0-5.5
0- Vee
0- Vee
-40 - 85
SYMBOL
0-lOO(Vee =3.3±O.3V)
ns/v
0- 20(Vee= 5 ±0.5V)
CHARACTERISTICS
r--
PARAMETER
SYMBOL
High-Level
Input Voltage
V IH
Low-Level
Input Voltage
V IL
High-Level
Output Voltage
Vm
Ta=-40-85OC
Ta=25OC
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 l. 50
l. 50
V
2.10
3.0 2.10
5.5 3.85
3.85
0.50
2.0
0.50
V
0.90
3.0
0.90
5.5
1. 65
1. 65
2.0
2.0
l.9
1.9
3.0
2.9
lai=-50IlA
3.0 2.9
4.5
4.4
4.5
4.4
V
- 2.48 lai=-4mA
3.0 2.58
lai=-24mA 4.5 3.94
3.80
- 3.85 lai=-75mA* 5.5
2.0
0.0
0.1
0.1
IQL=50IlA
0.0
3.0
O. I
0.1
0.0
4.5
0.1
0.1
V
3.0
0.44
0.36
Ia..=12mA
0.36
lQL=24mA
4.5
0.44
1. 65
5.5
IQL=75mA*
TEST CONDITION
-
VIN =
V IH or V IL
VIN=
-
Low-Level
Output Voltage
VOL
3-State Output
orr-State Current
I(E
VIN=VUi or VIL
Vour=Vee or GND
5.5
11:->
VIN=Vee or GND
VIN=Vee or GND
5.5
5.5
Input Leakage Current
Quiescent Supply Current
VIH or VIL
Icc
-
-
±0.5
-
±0.1
8.0
-
• :This spec indicates the capability of driving 50n transmission lines.
One output should be tested at a time for a lOms maximum duration.
____________________________________________________________
AC-217
-
±5.0
±1.0
80.0
Il A
~IBACOAPO~ATK3N
TC74AC257P/F/FN,TC74AC258P/F/AN
IEC LOGIC SYMBOL
TC74AC258
TC74AC257
De
De
SELECT
SELECT
1A
16
2A
26
3A
38
1A
16
1Y
2A
2Y
26
3A
3Y
36
4A
48
4Y
SYSTEM DIAGRAM
TC74AC257
TC74AC258
SELECT
IA
lA
IB
18
2A
2A
2B
31.
3B
'A
'B
•
11
10
I.
13
15
IY
2Y
28
3A
3B
.A
'B
OE
11
3Y
10
"
,y
13
--:1.:..5_-l
::>o-----------.J
TOaHIIIA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-218
TC74AC257P/F/FN,TC74AC258P/F/RN
AC ELECTRICAL CHARACTERISTICS(C L=&OpF. RL =6000. Input t r =t,=3ns)
Ta-25"C
Ta--40 -85"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vex MIN. TYP. MAX. MIN. MAX.
3.3±0.3
14.3
16.3
7.0
1.0
Propagation Dell!l Time t pLlI
(A, a-yo Y)
t pHI.
5.0±0.5
4.7
7.5
1.0
8.5
Propagation Delay1:ime
(SELECT-Y, Y)
Output Enable Time
t pUl
t pilL
3.3±0.3
5.0±0.5
-
8.6
5.5
17.2
9.1
1.0
1.0
19.6
10.4
t p7l.
3.3±0.3
5.0±0.5
-
7.3
5.0
14.0
7.9
1.0
1.0
16.0
9.0
tJ01
tpLZ
-
5.6
1.0
11.0
9.6
5.1
7.9
1.0
9.0
Input Capacitance
CIN
5
10
10
Output Capacitance
10
pF
Coor
Power Dissipation Capacitance CpDW
28
Note (1) C FD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Output Disable Time
3.3±0.3
5.0±0.5
-
ns
tpllZ
Ia::tp)=CPD
0
-
Va;ofl1,,+I a;
------------------------------------------------------------T08HI&ACORPDA~
AC-219
TC74ACT257P/F/FN,TC74ACT258P/F/FN
TC74ACT257P/F/FN 2-CHANNEL MULTIPLEXER 3-STATE)
TC74ACT268P/F/FN 2-CHANNEL MULTIPLEXER 3-STATE,INVERTING
The TC74ACT257 and TC74ACT258 are advanced high
speed CMOS MULTIPLEXERs fabricated with silicon
gate and double-layer metal wiring C2MOS technolgy.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These devices may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
Each is composed of four independent 2-channel
multiplexe~ with common SELECT and OUTPUT
ENABLE(OE).
The TC74ACT257 is a non- inverting multiplexer, while
the TC74ACT258 is an inverting.
If OE is set low, the outputs are held in a
high-impedance state. When SELECT is set low, "An
data inputs are enabled.
Conversely, when SELECT is high, "B" data inputs are
enabled.
All inputs are equipped with protection citcuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd= ns(typ.) at Va;=5V
• Low Power Dissipation ............... Ia;=8.uA(Max.) at Ta=25"C
• Compatible with TTL outputs ...... VIL =O.8V(Max.)
VIH =2.0V(Min.)
• Symmetrical Output Impedance ···Ila; I =IOL=24mA(Min.)
Capability of driving 50g
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpHL
• Pin and Function Compatible with 74F 2571258
1
P(DIP16-P-300A)
,.~,.~
F(SOP16-P-300)
FN(SOL 16-P-150)
TRUTH TABLE
INPUTS
OE SELECT
H
OUTPUTS
A
X
B
L
L
X
L
L
L
H
X
X
L
H
X
L
L
X
X
H
X: Don't Care
Z : High Impedance
H
PIN ASSIGNMENT
TC74ACT257
SELECT 1
1A 2
1B 3
1Y 4
2A 5
2B 6
2Y 7
TC74AC T 258
SELECT 1
1A 2
1B 3
,-y- 4
2A 5
2B 6
16
15
14
13
12
Vce
OE
4A
4B
4Y
11 3A
10 3B
9 3Y
GND 8
iv
16
15
14
13
12
7
(TOP VIEW)
-rc:a.H11IA CORPORATION
AC-220
Of
4A
4B
4Y
11 3A
10 3B
9 3Y
GND 8
(TOP VIEW)
Vee
Y(2571 Y(2581
Z
Z
L
H
H
L
L
H
H
L
TC74ACT257P/F/FN,TC74ACT258P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vcc
VIN
Vour
11K
10K
I()l;T
Icc
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-40"C~ 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
4.5-5.5
0- Vee
0- Vcc
-40 - 85
0-10
SYMBOL
Va:;
VIr-;
VOLT
Topr
dtldv
"C
ns/v
CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VUI
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
VIN=
VIHor VIL
Low-Level
Output Voltage
VOL
YiN=
VIHor VIL
3-State Output
Off -State Current
~
VIN=VIH or VIL
Vour =Vcc orGND
Input Leakage Current
liN
Icc
Quiescent Supply Current
UNIT
V
V
V
~Icc
TEST CONDITION
Ia-I=-50,uA
IOi=-24mA
IOi=-75mA*
h=50p.A
IOL=24mA
IOL=75mA*
VIN =Va:; or GND
VIN =VCC or GND
PER INPUT:VIN -3.4V
OTHER INPUT:Vcc or GND
-
Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
2.0
2.0
l
5.5
4.5
V
0.8
0.8
l
5.5
4.5 4.4
4.5
4.4
V
4.5 3.94
3.80
5.5
3.85
4.5
0.0
O. 1
O. 1
V
4.5
0.36
0.44
5.5
1. 65
5.5
-
-
±0.5
-
±0.5
5.5
5.5
-
-
±O.l
8.0
-
±1.0
80.0
-
1.35
5.5
-
-
1.5
f.lA
rnA
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a lOms maximum duration.
------------------------------------------------------------TOaHIBAcaAPa~
AC-221
TC74ACT257P/F/FN, TC74ACT258P/F/FN
IEC LOGIC SYMBOL
TC74ACT258
TC74ACT257
OE
SELECT
OE
SELECT
1A
1B
2A
2B
3A
1A
1B
2A
1Y
2Y
28
3A
3Y
38
4A
48
4Y
SYSTEM DIAGRAM
TC74ACT257
SELECT
TCT4ACT258
I
IA
IA
18
18
2A
2A
28
28
SA
38
4A
48
II
10
14
13
15
3A
38
4A
48
11
10
14
13
o E ~1::.5_-I ~o------------I
TOaHIBACa~---------------~----------------------------------------
AC-222
TC74ACT257P/F/FN,TC74ACT258P/F/FN
AC ELECTRICAL CHARACTERISTICS(C L=50pF. RL =5000. Input t r =tf=3ns)
Ta- 40 -85"C
Ta-25"C
UNIT
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX. MIN. MAX.
Vee
Propagation Del¥ Time
(A, B-Y, )
t plJI
t pili.
5.0±0.5
-
1.0
Propagation Delay..:!:ime
tpLH
tpHL
5.0±0.5
-
1.0
Output Enable Time
t JVL
t pZI-I
5.0±0.5
-
1.0
Output Disable Time
tp12
tpl-lZ
5.0±0.5
-
1.0
(SELECT-Y, Y)
ns
Input Capacitance
CIN
5
10
10
Output Capacitance
pF
COllr
10
Power Dissipation Capacitance
CPD(l)
Note (1) Cm is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IcctpO=CPD • Va;' fiN +1 a;
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TOSHIBA CORPORATION
AC-223
TC74AC273P I FI FW
OCTAL D-TVPE FLIP FLOP WITH CLEAR
The TC74AC273 is an advanced high speed .CMOS
OCTAL D-TYPE FLIP FLOP fabricated with silicon g.te
and double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
.
Information signals applied to D inputs are transferred
to the Q outputs on the positive going edge of the clock
pulse.
When the CLR input is held low, the Q outputs are at a low logic
level independent of the other inputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. fMNr170MHa (typ.) It Va:=5V
• Low Power Dissipation .......... ·· .. ·la:=8#A{Max.) at T.=25'(:
• High Noise Immunity ............... V~IH=VNIL =28. Vcc(Min.)
• Symmetrical Output Impedance .. ·11ai I =Ia.=24mA(Min.)
Capability or drivinr SOQ
transmission lines.
• Balanced Propagation Delays ...... tpLH .. tpH!.
• Wide Operating Voltage Range .. • VCC {opr)=2V.....S.5V
• Pin and Function Compatible with 74F 273
P(DIP20-P-300A)
.~a~
1
F(S0P20-P-300)
1
FW(SOL20-P-300)
91N ASSIGNMENT
CLR 1
Q
20 Vee
19 Q8
18 D 8
1 2
D1 3
D2 4
17 D7
16 Q7
Q2 5
Q3 6
15 Q6
D3 7
14 06
13 05
D4 8
Q4 9
GND 10
12 Q5
11 CK
(TOP VIEW)
lEe LOGIC SYMBOL
TRUTH TABLE
INPUTS
CUi
OUTPUTS
CLR
D
CK
Q
L
X
X
L
H
L
L
H
H
H
X
S
S
L
FUNCTION
Clear
H
-
Qn
No change
CK
Dl
D2
D3
X : Don't care
01
02
03
D4
Q4
D5
os
D6
07
D6
07
Q6
Q8
TOaHIIIA COIRPORATIDN - - - - - - - - - - , . . . . . - - - - - - - - - - - - - - - - - -
AC-224
TC74AC273P I FI FW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vo:;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Yo:;
VIN
Voor
'1 1K
10K
loor
10:;
PD
Tstg
TL
VALUE
-,0.,5 -6.0
-0.5 -Yo:;+0.5
-0.5 -Voo+:0.5
±20
±50
±50
±200
500(DrP);"/180(SOP)
-65 -150
300
,
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmWI"C shall be applied
until 300m W.
RECOMMENDED OPERATING COf;:OITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
·0 -, Yo:;
0- Yo:;
-40 - 85
SYMBOL
Yo:; "
VIN
Voor
Topr
dt/dv
UNIT
V
V
V
"C
0-100(Vo:;=3.3±0.3V)
0- 20 (Vo:;=5 ±0.5V)
ns/v
CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VlH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
VIN=
V/Hor VIL
VIN=
Low-Level
Output Voltage
VOL '
Input Leakage Current
Quiescent Supply Current
10:;
VIHor VII:'
liN
VIN =Vo:;
VIN =Vo:;
-
Ta=25"C
MIN. TYP. MAX.
2.0 1. 50
3.0 2.10
5.5 3.85
2.0
0.50
0.90
3.0
5.5
1. 65
2.0
1.9
2.0
1a-!=-50JLA
3.0 2.9
3.0
4.5
4.5 4.4
loo=-4mA
3.0 ,2.58
1ai=-24mA 4.5 3.94
la-!=-75mA* 5.5
2.0
0.0
0.1
IQL= 50JLA
3.0
0.0
O. I
4.5
0.0
0.1
0.36
3.0
IQL=12mA
.IQL=24mA " '4.5
0.36
5.5
IQL=75mA*
5.5
±0.1
orGND
or GND
5.5
8.0
TEST CONDITION
Yo:;
Ta=-40-85"C
UNIT
MIN. MAX.
1. 50
V
2.10
3.85
0.50
V
0.90
1. 65
1.9
2.9
4.4
V
2.48
3.80
3.85
0.1
0.1
0.1
V
0.44
0.44
1. 65
±1.0
JLA
80.0
-
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a 10ms maximum duration.
------------------------------------------------------------~IBA~~~N
AC-225
TC74AC273P/F/FW
SYSTEM DIAGRAM
TIMING REQUIREMENTS(lnput t r =tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Va:;
Ta=25"C
TYP.
LIMIT
Ta=-40 -85"C UNIT
LIMIT
tW(L)
tW(H)
3.3±0.3
5.0±0.5
-
-
8.0
5.0
8.0
5.0
Minimum Pulse Width
(CLR)
tW(L)
3.3±0.3
5.0±0.5
-
7.5
5.0
7.5
5.0
Minimum Set-up Time
ts
3.3±0.3
5.0±0.5
-
8.5
4.5
8.5
4.5
Minimum Hold Time
tt,
3.3±0.3
5.0±0.5
-
0.0
0.0
0.0
0.0
trem
3.3±0.3
5.0±0.5
-
-
7.0
3.5
7.0
3.5
Minimum Pulse Width
(CK)
Minimum Removal Time
(CLR)
AC ELECTRICAL CHARACTERISTICS(C L =50pF, R L =5000, Input t r =tf=3ns)
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX.
Va:;
Propagation Delay Time tpLH
3.3±0.3
9.0
15.8
9.6
tpHL
(CK-Q)
6.5
5.0±0.5
Propagation Delay Time
(CLR-Q)
t pliL
3.3±0.3
5.0±0.5
-
8.0
5.9
14.0
9.2
ns
Ta- 40-85"C
UNIT
MIN. MAX.
1.0
1.0
18.0
11.0
1.0
1.0
16.0
10.5
ns
- MHz
110
55
150
90
Input Capacitance
CIN
5
10
10
pF
Power Dissipation Capacitance Cpo(1)
40
Note (1) C ID is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia:;QJol=C PO • Va;. f IN+I a; 18{per F/F)
And the total C ID when n pes. of Flip Flop operate can be gained by the following eqution:
CPO (total) =29+11· n
Maximum Clock Frequency
fMAX
3.3±0.3
5.0±0.5
TCIIIHIBA CORPORATION
AC-226
55
90
TC74ACT273P/F/FVV
OCTAL D-TVPE FLIP FLOP WITH CLEAR
The TC74ACT273 is an advanced high speed CMOS
OCT AL D-TYPE FLIP FLOP fabricated with silicon gate
and double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These devices may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL, NMOS and CMOS output
voltage levels.
.
Information signals applied to D inputs are transferred
to the Q outputs on the positive going edge of the clock
pulse.
When the CLR input is held low, the Q outputs are at a
low logic level independent of the other inputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. fMAX=170MHz (typ.) at \tt=5V
• Low Power Dissipation ............... 1a:;=8IlA(Max.) at Ta=25"C
• Compatible with TTL outputs ...... V'L =O.8V(Max.)
Vu,=2V(Min.)
• Symmetrical Output Impedance .. ·1 ~JH 1=101, -=24mA(Min.)
.
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpL,.,"'t pIIL
• Pin and Function Compatible with 74F 273
TRUTH TABLE
,.~,.~
1
1
F(SOP20-P-300)
FW(SOL20-P-3DD)
PIN ASSIGNMENT
Ci:R
1
2
20 Vee
19 Q8
01 3
18 08
17 07
Ql
02
Q2
Q3
03
4
5
16 Q7
15 Q6
6
7
14
13
12
11
04 8
Q4 9
GNO 10
06
05
Q5
CK
(TOP VIEW)
IEC LOGIC SYMBOL
INPUTS
CUi
OUTPUTS
FUNCTION
CLR
D
CK
0
L
X
X
L
Clear
H
L
L
-
H
H
H
-
H
P( 0IP20-P-300A)
X
S
S
L
On
No change
X: Don't care
OK
01
02
03
D4
OS
Ql
Q2
Q3
Q4
D6
Q5
Q6
07
Q7
D8
Q8
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T O S H I B A CORPORATION
AC-227
TC74ACT273PIFIFW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
"ct.
VI:-;
Va.T
11K
10K
Ia.T
lee
PD
Tstg
TL
VALUE
-0.5-6.0
-0.5...:...Vee+0•5
-0.5 -Vee+0.5
±20
±50
±50
±200
500(DIP) */ 180(SOP}
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating ractor or
-lOmW/"Cshould be applied
up to300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
Va.
Input Leakage Current
Quiescent Supply Current
110
VALUE
4.5-5.5
0- Vee
o -Vee
-40 - 85
0-10
SYMBOL
Vee
VI:-;
Va.T
Topr
dt/dv
liS
Icc
IlIee
UNIT
V
V
V
"C
ns/v
-
Ta=25"C
Vee MIN. TYP. MAX.
4.5
2.0
l
5.5
4.5
0.8
l
5.5
Ja.1=-50 p. A 4.5 4.4
4.5
Vl"=
1ai=-24mA 4.5 3.94
VIHor ViL
1CH=-75mA* 5.5
0.1
Ia.=50p.A
4.5
0.0
VI:-;=
4.5
0.36
Ia.=24mA
VIHorVIL
5.5
Ia.=75mA*
5.5
±O.I
VJ:-; =Vcc or GND
VI:-; =Vee or GND
5.5
8.0
PER INPUT:Vee=3.4V
1. 35
OTHER INPUT:Vee or GND 5.5
TEST CONDITION
-
-
-
---
--
-
..
capability
-
..
drlVlng
--
Ta=-40-85"C
L"NIT
MIN. MAX.
2.0
-
V
-
0.8
V
-
4.4
3.80
3.85
--
V
-
--
0.1
0.44
1. 65
±1.0
80.0
-
--
-
1.5
V
p.A
rnA
:Thls spec mdlcates the
of
500 transmiSSion lines.
One output should be tested at a time for a IOms maximum duration.
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-228
TC74ACT273P/F/FVV
SYSTEM DIAGRAM
Q1
Q2
Q3
QS
Q4
Q6
Q7
Q8
TIMING REQUIREMENTS(lnput tr=tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vcr.
Ta-25"C
TYP.
LIMIT
Ta--40 -85"C
LIMIT
Minimum Pulse Width
(CK)
two.)
tW(H)
5.0±0.5
-
5.0
5.0
Minimum Pulse Width
(CLR)
two.)
5.0±0.5
-
5.0
5.0
Minimum Set-up Time
ts
5.0±0.5
-
3.5
3.5
Minimum Hold Time
th
5.0±0.5
-
1.5
1.5
trem
5.0±O.5
-
3.0
3.0
Minimum Removal Time
(CLR)
AC ELECTRICAL CHARACTERISTlCS(C L=60pF, RL =600Q, Input t r =tf=3ns)
'l'a=25"C
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX.
Va;
Propagation Delay Time t plJ-1
5.0±; =Va:, or GND
VI" =Vrr. or GND
5.5
5.5
-
-
-
±0.5
±O.l
8.0
Ta=-40-85"C
UNIT
MIN. MAX.
1. 50
V
2.10
3.85
0.50
V
0.90
1. 65
l.9
2.9
4.4
V
2.48
3.80
3.~li
-
--
-
-
0.1
0.1
0.1
0.44
0.44
1. 65
V
±5.0
±1.0
80.0
IJ.A
• :This spec indicates the capability of driving 500 transmission Jines.
One output should be tested at a time for a 10ms maximum duration.
TOIIHIIIA COIUIOIfIIATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-232
TC74AC299P/F/FW,TC74AC323P/F/FW
TRUTH TABLE
INPUTS
MODE
S1
L
~LEAR
CK
FUNCTION SELECT OUTPUT CONTROL
CLR
H
L
L
G1*
SO
H
X
G2*
(299)
X
X
X
L
L
L
L
L
L
X
SERIAL
(323)
S
.r
.r
SL
X
SR
X
X
X
INPUTSI
OUTPUTS
OUTPUTS
A/aA
aA'
Z
L
HfaH
aH'
Z
L
L
L
L
L
L
L
L
aHO
aAO
aHO
aGn
H
aGn
aGn
L
aGn
H
aBn
H
L
aBn
L
h
a
h
the high impedance
X
X
L
X,
L
L
X
X
X
X
aAO
H
L
L
X
H
H
RIGHT
H
L
H
L
L
X
L
L
SHIFT
H
H
L
L
L
H
X
aBn
L
aBn
LEFT
H
H
L
L
L
X
LOAD
H
H
H
X
X
X
X
a
When one or both output controls are high, the eight input/output terminals are in
* state; however sequential or clearing of the register is not affected.
Z High Impedance
anO =The level of An before the indicated steady-state input conditions were established.
ann=The level of an before the most recent active transition indicated by ~ or t.
a,h =The level of the steady-state inputs A, H, respectively.
X :Don't care
HOLD
SHIFT
L
H
H
X
L
L
.r
.r
.r
.r
.r
TIMING CHART
CLOCK
{SO
MODE
CONTROL
INPUTS
S1
CLEAR
SERIAL
DATA
INPUTS
r
R
SL
OUTPUTS QA'
A/QA
BlOB
CIDC
INPUTS
lOUT PUTS
D/QD
E/QE
.'~"l-;
j
F/QF
G/QG
H/QH
OUTPUTS
QH'
.
299
,
I
ASYNC SYNC LOAD
CLEAR CLEAR
SHIFT LEFT
SHIFT RIGHT
•
HOLD
ASYNC SYNC
CLEAR CLEAR
323
299
323
---------------------------------------------------------------TCMBHI~ c~pa~~
AC-233
TC74AC299P/F/RN,TC74AC323P/F/RN
SYSTEM DIAGRAM(TC74AC299)
SO
51
~~
lIE Equivalent Circuits
SL
1~8__C-~____- - - - - - - - - - - - - - - - - - - - - - - - ,
SR 11
OA'
ArQA
sros
croc
OraD
EIOE
F/QF
G/QG
H/QH QH'
SYSTEM DIAGRAM(TC74AC323)
SO
51
19
01
(;2
3iE Equivalent Circuits
SL 18
9~-++-t-t---~--~--*--4-CKI2~--+-H-I---llJL~-n-~~* i 1* __ .I: L 11* __
CLii
__
OA'
AfOA
srOB
* __
llllE __ 1 _
--6-tC-i.:rH=-irITisrH=--4rcroc
OraD
ErQE
FrOF
GroG
TOIIHIIIA COAPCJIiiIATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-234
TC74AC299PI FI AN, TC74AC323P/F/AN
TIMING RECOMMENDED OPERATING CONDITIONS(lnput t r =tf=3ns)
PARAMETER
snlBOL TEST CONDITION
Ta-25°C
TYP.
LIMIT
Vee
Minimum Pulse Width
(CK)
tlnllJ
tlnL)
3. 3±0. 3
5. O±O. 5
-
Minimum Pulse Width
(CLR)*
tl\"(L)
~. 3±0. 3
-
~. O±O. 5
-
Minimum Set-up Time
(SL,SR,A-H)
ts
p. 3±0. 3
-
O±O. 5
Minimum Set-up Time
(SO,Sl)
ts
p. 3±0. 3
Minimum Set-up Time
(CLR)**
Ta- 40 -85"C
UNIT
LIMIT
8.0
5.0
8.0
5.0
7.0
5.0
7.0
5.0
-
6.0
4.0
6.0
4.0
~. O±O. 5
-
11. 9
7.0
13.6
7.0
ts
p. 3±O. 3
-
~. O±O. 5
-
5.0
3.5
5.0
3.5
Minimum Hold Time
(SL,SR,A-H)
th
p. 3±0. 3
-
~. O±O. 5
-
1.0
1.0
1.0
1.0
Minimum Hold Time
(SO,Sl)
th
p. 3±0. 3
-
0.0
0.0
0.0
0.0
Minimum Hold Time
(CLR)**
th
p. 3±0. 3
~. O±O. 5
-
1.5
1.5
1.5
1.5
trem
p. 3±0. 3
-
5.0
3.0
5.0
3.0
Minimum Removal Time
(CLR)*
~.
~.
O±O. 5
~. O±O.
5
-
-
-
ns
Note:* TC74AC299 only
• * TC74AC323 only
-------------------------------------------------------~BHIBACDRPORAnDN
AC-235
TC74AC299P I FI FW, TC74AC323P I FI FW
AC
ELECTRICAL CHARACTERISTICS (Cl =60pF,Rl =600Q,tr =tf =3n8)
TEST
SYMBOL CONDITION
PARAMETER
Ta -40-85"C UNIT
Ta-25"C
MIN. TYP. MAX. MIN. MAX.
3.3±0.3
10.6 18.4
1.0 21. 0
5.0±0.5 6.8 10.5
1.0 12.0
Voc
-
Propagation Delay Time
(CK-QA'QH')
tpLH
tpllL
Propagation Delay Time
(CLR-QA'QH')
tpI-IL
3.3±0.3
5.0±0.5
Propagation Delay Time
(CK-QA-QH)
tpLIi
tpHL
3.3±0.3
5.0±0.5
Propagation Delay Time
(CLR-QA-QH)
tpliL
3.3±0.3
5.0±0.5
Output Enable time
tpZL
tP?Ji
3.3±0.3
5.0±0.5
Output Disable time
tplZ
tpHZ
Maximum Clock Frequency
fMAX
Input Capacitance
Bus Input Capacitance
Power Dissipation Capacitance
CIN
-
ClIO
-
-
8.1
6.1
14.0
9.2
1.0
1.0
16.0
10.5
10.9
7.3
19.3
10.5
1.0
1.0
22.0
12.0
9.8
6.7
16.7
10.9
1.0
1.0
19.0
12.4
-
9.9
6.6
17.5
9.6
1.0
1.0
20.0
11. 0
3.3±O.3
5.0±0.5
-
8. 1
6.4
14.0
9.6
1.0
1.0
16.0
11. 0
3.3±0.3
5.0±0.5
45
80
90
140
5
13
137
-
45
80
-
10
-
-
-
10
-
-
-
-
CPf)(l)
-
ns
MHz
pF
Note(1) C PD is deCined as the value of the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IOCtpD=C PD • V OC • f1N+[OC
* TC74AC299
** TC74AC323
only
only
TOa.4laA ~~------------------------------------------------------------
AC-236
TC74AC367P/F/FN, TC74AC368P/F/FN
HEX BUS BUFFER
NON-INVERTED. 3-STATE OUTPUTS
INVERTED. 3-STATE OUTPUTS ,--_ _ _ _ _ _ _ _ _ _ _ _ _----,
TC74AC387P/F/FN
TC74AC388P/F/FN
The TC74AC367 and 368 are advanced high speed CMOS
HEX BUS BUFFERs fabricated with silicon gate and double
-layer metal wiring C2MOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
They contain six buffers; four buffers are controlled by an
enable input (01), and the other two buffers are controlled by
enable input (02), The outputs of each buffer group are enabled
when 01 and/or 02 inputs are held low; if held high, these outputs
are in a high impedance state.
The TC74AC367 is a non-inverting output type, while
the TC74AC368 is an inverting output type.
All inputs are equipped with protection circuits against
static discharge or tansient excess voltage.
1
P( 01 P16-P-300A)
F(SOP16-P-300)
FN(S0L16-P-150)
PIN ASSIGN MENT
TC74AC367
FEATURES:
• High Speed ................................. tpd=3. 7ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=8f.tA(Max.} at Ta=25°C
• High Noise Immunity .............. · Vr\IH=VI'\I!_=28% Vcc(Min.}
• Symmetrical Output Impedance ... \ IaJ \ =IoL =24mA(Min.}
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpHL
• Wide Operating Voltage Range'" Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 3671368
16
Vee
lA 2
15 G2
lY 3
14
6A
2A "
13
6Y
2Y 5
12
5A
3A 6
11
5Y
3Y 7
10
'A
9
'Y
1
16
Vee
lA 2
15
G2
lY 3
14
6A
2A
13
6Y
GND8
TRUTH TABLE
(TOP
V lEW)
TC74AC368
Gl
INPUTS
OUTPUTS
G
A
L
L
L
H
L
H
H
L
H
X
Z
Z
Y(367) Y(368)
X:Don't care
Z:High Impedance
,
2Y 5
12
SA
3A 6
11
SY
3Y 7
10
4A
9
iY
GND8
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TOaHIBA CORPORATION
AC-237
TC74AC367P/F/FN,TC74AC368P/F/FN
ABSOLUTE MAXIMUM RATINGS
VALUE
PARAMETER
SYMBOL
Supply Voltage Range
-0.5
-6.0
Vee
DC Input Voltage
-0.5
-Vee
+0.5
VIN
DC Output Voltage
-0.5
-Vee+0.5
Vour
Input Diode Current
±20
lu<
Output Diode Current
±50
10K
DC Output Current
±50
loor
DC Vee/Ground Current
±200
lee
Power Dissipation
PD
500(DIP) */180(SOP)
Storage Temperature
-65 -150
Tstg
Lead Temperature 10sec
300
TL
RECOMMENDED OPERATING CONDITIONS
PARAMETER
VALUE
SYMBOL
Supply Voltage
2.0-5.5
Vee
Input Voltage
0-- Vee
VIN
Output Voltage
0-- Vee
Voor
Operating Temperature
Topr
-40 -- 85
Input Rise and Fall Time
DC
ELECTRICAL
dtldv
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lO'mW/"C shall be applied
until 300m W.
UNIT
V
V
V
"C
0c-lOO(Vee =3.3±0.3V)
ns/v
0;...., 20(Vee= 5 ±0.5V)
CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
V Ui
Low-Level
Input Voltage
V IL
-
VIN =
High-Level
Output Voltage
Vm
Low-Level
Output Voltage
VOL
-
Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
5.5 3.85
3.85
2.0
0.50
0.50
V
0.90
3.0
0.90
5.5
1. 65
1. 65
2.0
1.9
1.9
2.0
3.0 2.9
3.0
2.9
Im=-50ttA
4.5
4.4
4.5
4.4
V
3.0 2.58
2.48
loH=-4mA
loH=-24mA 4.5 3.94
3.80
3.85
loH=-75mA* 5.5
2.0
0.0
O. I
0.1
0; 1
3.0
0.0
0.1
IOL=50ttA
4.5
0.0
0.1
0.1
V
0.36
3.0
0.44
IOL=12mA
0.36
0.44
4.5
IOL=24mA
5.5
1. 65
IOL=75mA*
TEST CONDITION
V IH or V IL
VIN=
VU1 or VIL
-
~
3-State Output
Ofr -State Current
ICE
VIN=VIH or VI!.
Voor=Vee or GND
5.5
-
Input Leakage Current
Quiescent Supply Current
I IN
lee
VIN=Vee or GND
VI,,=V eeor GND
5.5
5.5
-
-
-
-
±0.5
-
±5.0
±O.l
8.0
-
±1.0
80.0
-
tt A
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a lOms maximum duration.
TOSHIBA c::ORPOAATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-238
TC74AC367P/F/FN,TC74AC368P/F/FN
IEC LOGIC SYMBOL
TC74AC367
TC74AC368
AC ELECTRICAL CHARACTERISTICS(CL=50pF. RL =5000. Input t r =tf=3ns}
Ta= 40 -85"C
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Va:;
MIN. TYP. MAX. MIN. MAX.
-
Propagation Delay Time-
tpLH
t pHL
3.3±0.3
5.0±0.5
-
6.5
4.5
11.0
7.0
1.0
1.0
12.5
8.0
Propagation Delay Time·
tpL(i
tpHL
3.3±0.3
5.0±0.5
-
6.1
4.3
10.5
7.0
1.0
1.0
12.0
7.5
Output Enable Time
tIl'lL
tJil,H
3.3±0.3'
5.0±0.5
-
7.9
5.5
13.2
8.7
1.0
1.0
15.0
10.0
Output Disable Time
tplZ
tpHZ
3.3±0.3
5.0±0.5
-
6.3
5.2
10.5
7.9
1.0
1.0
12.0
9.0
ns
Input Capacitance
Output Capacitance
5
10
10
10
pF
TC74AC367
28
Power Dissipation Capacitance CPOIll
TC74AC368
25
Note(1) CR) is defined as the value. of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
1cc~=CPD -Va:::-fIN+I a:::/6(per bit)
(2) • for TC74AC367 only
•• for TC74AC368 only
(,;IN
Carr
__________________________________________________________
AC-239
TCNIHI~
ca~~aN
TC74AC373P I FI FW, TC74AC533P I FI FW
OCTAL D-TVPE LATCH WITH 3-STATE OUTPUT
TC74AC373P/F/FW
NON-INVERTING
TC74AC633P/F/FW
INVERTING
The TC74AC373 and TC74AC533 are advanced high
speed CMOS OCTAL LATCH with 3-STATE OUTPUT
fabricated with silicon gate and double-layer metal
wiring C2MOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These 8-bit D-type latches are controlled by a latch
enable input (LE) and a output enable input (OE).
When the OE input is high, the eight outputs are in a
high impedance state.
The TC74AC373 has non-inverting outputs, and
TC74AC533 has inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP20-P-300A)
20~ a~
1
F(SOP20-P-300)
1
FW(SOL20-P-300)
PIN ASSIGNMENT (TOP VIEW)
FEATURES:
• High Speed ................................. tp d=4.8 ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=8ttA(Max.) at Ta=25"C
• High Noise Immunity··············· VNIH=VNIL=28% Vcc(Min.)
• Symmetrical Output Impedance ···1 1m 1=IOL=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...•.. tpLH"'tpHL
• Wide Operating Voltage Range ... Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 373/533
TRUTH TABLE
TC74AC373
OE 1
00 2
DO 3
01 4
01 5
02 6
02 7
03 8
03 9
GNO 10
20
19
18
17
16
15
14
13
12
Vee
11
LE
20
19
18
17
16
15
14
13
12
Vee
07
07
06
06
05
05
04
04
TC74AC533
Ofl
INPUTS
OUTPUTS
OE
LE
0
Q(373)
Q(533)
H
X
Z
Z
L
L
X
X
L
H
L
On
L
On
H
L
H
H
H
L
x : Don't Care
;J:Ilgh ImAlldance
On (On) : 0 (0) outputs are latched at the time
when the LE input is taken to a low
logic level.
Z
00 2
DO 3
01 4
01 5
02 6
02 7
03 8
03 9
GN010
07
07
06
06
05
05
04
04
11 LE
~~ ~RP~~----------------------------------------------------------
AC-240
TC74AC373P/F/RN,TC74AC533P/F/RN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC O~tput Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
VALUE
-0.5 -6.0
-0.5 -Vex; +0.5
-0.5 -Vee+0.5
±20
±50
±50
±200
500(DIP) */180(SOP)
-65 -150
300
SYMBOL
Vex;
VIN
Vour
11K
10K
lour
lee
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-IOmWI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vee
o -Vee
-40 - 85
SYMBOL
Vee
VIN
VOL'T
Topr
dt/dv
UNIT
V
V
V
"C
0-100(Vee =3.3±0.3V)
ns/v
0- 20(Vee= 5 ±0.5V)
CHARACTERISTICS
-
Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 l. 50
l. 50
V
3.0 2.10
2.10
5.5 3.85
3.85
2.0
0.50
0.50
V
0.90
3.0
0.90
5.5
l. 65
l. 65
2.0
2.0
l.9
l.9
2.9
3.0
2.9
Ioo=-50IlA
3.0
4.5
4.4
4.5
4.4
V
!rn=-4mA
3.0 2.58
2.48
3.80
!rn=-24mA 4.5 3.94
3.85
!rn=-75mA* 5.5
2.0
0.0
0.1
0.1
0.1
101.. = 50llA
3.0
0.0
0.1
4.5
0.0
0.1
0.1
V
0.36
3.0
0.44
IOI..=12mA
0.36
4.5
0.44
IOI..=24mA
5.5
l. 65
IOI..=75mA*
PARAMETER
SYMBOL
TEST CONDITION
High-Level
Input Voltage
V IH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vrn
Low-Level
Output Voltage
VOL
3-State Output
Off-State Current
I(1l
VIN=VIH or VIL
Vour=Vee or GND
5.5
Input Leakage Current
Quiescent Supply Current
IIr>:
VIN=VeeOr GND
VIN=Vee or GND
5.5
5.5
VIN =
V IH or V IL
VIN=
VIH or VIL
lex;
-
-
-
-
±0.5
±O.l
8.0
-
±5.0
±1.0
80.0
Il A
• :This spec indicates the capability of driving 50n transmission lines.
One output should be tested at a time for a lOms maximum duration.
------------------------------------------------------------~IBAcaAPa~
AC-241
TC74AC373P/F/AN,TC74AC533P/F/RN
IEC LOGIC SYMBOL
TC74AC533
TC74AC373
Of
OE
LE
LE
DO
ao
00
Co
01
02
03
01
02
03
D4
OS
Q4
01
02
03
04
01
02
03
04
Q6
OS
06
07
07
Q5
as
Q6
07
SYSTEM DIAGRAM
TC74AC373
TC74AC533
~"CaAPaA~-----------------------------------------------------
AC-242
TC74AC373P/F/RN,TC74AC533P/F/RN
TIMING REQUIREMENTS(lnput t r =t,=3ns)
PARAMETER
SYMBOL TEST CONDITION
Va;
Ta=2s"C
TYP.
LIMIT
Ta=-40-8s"C
LIMIT
Minimum Pulse Width
(LE)
tW(ll)
3.3±O.3
s.O±O.s
-
-
7.0
5.0
7.0
5.0
Minimum Set-up Time
ts
3.3±O.3
s.O±O.s
-
6.0
3.5
6.0
3.5
Minimum Hold Time
th
3.3±O.3
s.O±O.s
-
-
1.0
1.0
1.0
1.0
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L=50pF. RL =5000. Input t r =t,=3ns)
Ta- 40 -85"C
Ta ....25"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Va;
MIN. TYP. MAX. MIN. MAX.
Propagation Delay Time
(LE-Q,Q)
t pLH
t pHL
3.3±O.3
s.O±O.s
-
7.7
6.1
13.2
8.7
1.0
1.0
15.0
10.0
Propagation Delay Time
(Dn-Q,Q)
tpLH
t pilL
3.3±O.3
s.O±O.s
-
7.6
5.8
12.9
8.3
1.0
1.0
14.7
9.5
Output Enable Time
tpZL
tPl/i
3.3±O.3
5.0±O.s
-
7.6
6.1
12.9
8.7
1.0
1.0
14.7
10.0
Output Disable Time
tp12
tpHZ
3.3±O.3
s.O±O.S
-
7.0
5.4
11.0
7.5
1.0
1.0
12.5
8.5
ns
Input Capacitance
CIN
5
10
10
pF
Output Capacitance
Cotrr
10
Power Dissipation Capacitance Cpo(l)
38
Note(1) Cm is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia; q,o=C PO • Vex;. f IN + I ex; /8( per Latch)
And the total C PO when n pes. of Latch operate can be gained by the following equation:
Cpo (total)=26+12· n
------------------------------TallHIIIA
AC-243
CORPORATION
TC74ACT373P I FI FW,TC74ACT533P I FI FW
OCTAL D-TVPE LATCH WITH 3-STATE OUTPUT
TC74ACT373P/F/FW NON-INVERTING
TC74ACT633P/F/FW
INVERTING
The TC74ACT373 and TC74ACT533 are advanced high
speed CMOS OCTAL LATCH with 3-STATE OUTPUT
fabricate\i with silicon gate and double-layer metal
wiring C2MOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These devices may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
These 8-bit D-type latches are controlled by a latch
enable (LE) and a output enable input (OE).
When the OE input is high, the eight outputs are in a
high impedance state.
The TC74ACT373 has non-inverting outputs, and TC74
ACT533 has inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd =5.2ns (typ.) at Vee =5V
• Low Power Dissipation ............... Icc=8#A(Max.) at Ta=25"C
• Compatible with TTL outputs· .. ·.. V IL =0.8V (Max.)
V IH =2.0V (Min.)
• Symmetrical Output Impedance .. ·1 I oHI=loL=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpHL
.• Pin and Function Compatible with 74F373/533
TRUTH TABLE
P(DIP20-P-300A)
20~ a~
1
1
F(SOP20-P-300) FW(SOL20-P-300)
PIN ASSIGNMENT (TOP VIEW)
TC74ACT373
OE 1
00
DO
01
01
02
02
03
03
2
3
4
5
6
7
8
9
GNO 10
20
19
18
17
16
15
14
13
12
11
Vee
07
07
06
06
20
19
18
17
16
15
14
13
12
11
Vce
07
07
06
06
as
05
04
04
LE
TC74ACT533
INPUTS
X
OE
OUTPUTS
OE
LE
0
H
X
0(373)
Z
0(533)
L
L
X
X
Z
an
an
L
H
L
L
H
L
H
H
H
L
: Don't
Care
Z ;Jjlgh Immtdance
an (an) : a (a) outputs are latched at the time
when the LE imput is taken to a low
logic level.
00 2
DO 3
014
aT 5
Q2 6
02 7
03 8
Q3 9
GNO 10
as
05
04
04
LE
~~ ~----------------------------------------------------------
AC-244
TC74ACT373P/F/RN,TC74ACT533P/F/RN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vex;
VIN
VOlJr
11K
10K
loor
lex;
PD
Tstg
TL
VALUE
-0.5-6.0
-0.5 -Vex;+0.5
-0.5 -Vex;+0.5
±20
±50
±50
±200
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500m W in the range of Ta=
-40·C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vex;
Input Voltage
VIN
Output Voltage
Voor
Operating Temperature
Topr
Input Rise and Fall Time dt/dv
DC
ELECTRICAL
VALUE
4.5-5.5
0- Vex;
0- Vee
-40 - 85
0-10
CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
V(li
YiN=
VIHor VIL
100=-50 (J. A
loo=-24mA
loo=-75mA.
Low-Level
Output Voltage
VOl.
YiN=
VIHor VIL
10I.=50JJ,A
10I.=24mA
Ia.=75mA.
3-State Output *
Off-State Current
~
VIN=VlH or VIL
Voor=Vee orGND
Input Leakage Current
lIN
Quiescent Supply Current
UNIT
V
V
V
"C
nsh
TEST CONDITION
Vex;
Ta=-40-85"C
Ta=25"C
UNIT
MIN. TYP. MAX. MIN. MAX.
4.5
l
2.0
-
-
2.0
-
V
1
-
-
0.8
-
0.8
V
4.4
3.94
4.5
-
4.4
3.80
3.85
0.0
-
-
0.1
0.36
-
--
V
--
-
0.1
0.44
1. 65
V
5.5
-
-
±0.5
±5.0
5.5
5.5
-
-
±0.1
8.0
-
5.5
4.5
VIN =Vex; or GND
lex;
VIN =Vee or GND
PER INPUT:Vm -3.4V
t.1cc
OTHER INPUT:Vee or GND
5.5
4.5
4.5
5.5
4.5
4.5
5.5
5.5
-
-
1.35
±1.0
80.0
1.5
JJ,A
rnA
• :This spec indicates the capability of driving 500 transmission Jines.
One output should be tested at a time for a lOms maximum duration.
----------------------------------------------------------TCMSHIBA ca~N
AC-245
TC74ACT373P I FI FW, TC74ACT533P I FI FW
lEe LOGIC SYMBOL
TC74ACT533
TC74ACT373
OE
lE
ao
00
01
01
02
02
03
os
03
D4
05
06
07
07
Q4
Q5
SYSTEM DIAGRAM
TC74ACT373
ao
01
02
03
Q4
Q5
Q6
07
TC74ACT533
~IIIA COAJtaIllATlQN - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-246
TC74ACT373P/F/RN,TC74ACT533P/F/RN
TIMING REQUIREMENTS(lnput t r=tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vex;
Ta=25"C
TYP.
LIMIT
Ta=-40 -85"C UNIT
LIMIT
Minimum Pulse Width
(LE)
tW(lU
5.0±O.5
-
5.0
5.0
Minimum Set-up Time
ts
5.0±O.5
-
2.0
2.0
Minimum Hold Time
til
5.0±O.5
-
3.0
3.0
AC ELECTRICAL CHARACTERISTICS(C L=50pF, RL =5000, Input t r =tf=3ns)
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
Vex;
MIN. TYP. MAX.
ns
Ta- 40-85"C
UNIT
MIN. MAX.
Propagation Delay Time
(LE-Q, Q)
tpLH
t pHI.
5.0±0.5
-
5.8
9.2
1.0
10.5
Propagation Delay Time
(Dn-Q,Q)
tpLH
t pHI.
5.0±O.5
-
5.9
9.6
1.0
11.0
ns
Output Enable Time
Output Disable Time
t~
tpZH
tpLZ
t pHZ
5.0±0.5
-
6.5
10.5
1.0
12.0
5.0±0.5
-
5.5
7.8
1.0
9.0
Input Capacitance
ClN
5
10
10
pF
Output Capacitance
COl.iT
10
Power Dissipation Capacitance Cpo(l)
32
Note (1) C ro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icc Qxl=C PD· Voc· f l:" +1 OC /8( per Latch)
And the total Cpo when n pcs. of Latch operate can be gained by the following equation:
CPD (total)= + • n
------------------------------TOBHIIIA
AC-247
COAPaAATION
TC74AC374P IFI FW, TC74AC534P IFIFW
OCTAL D-TVPE FLIP-FLOP WITH 3-STATE OUTPUT
TC74AC374P/F/FW NON-INVERTING
TC74AC634P/F/FW INVERTING
The TC74AC374 and TC74AC534 are advanced high
speed CMOS OCTAL FLIP-FLOP with 3-STATE
OUTPUT fabricated with silicon gate and double-layer
metal wiring C2MOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These 8--bit D-type flip-flops are controlled by a clock input
. eCK) and an output enable input (OE),
When the· OE input is high, the eight outputs are in a
high impedance state.
The TC74AC374 has non-inverting outputs, and TC74A
C534 has inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP20-P-300A)
20~ 20~
1
1
F(SOP20-P-300)
FW(SOL20-P-300)
PIN ASSIGNMENT (TOP VIEW)
FEATURES:
• High Speed .......•..............•.......... f MAX =200MHz(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=8IlA(Max.) at Ta=25"C
• High Noise Immunity· ...... ·.... ·.. VNIH=VNIL=28% Vcc(Min.)
• Symmetrical Output Impedance ·.. 11a-! I =IOL=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH~tpHL
• Wide Operating Voltage Range .. · Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 374/534
TC74AC374
OE
ao
DO
01
1
2
20 Vee
19 a7
18 07
3
4
al 5
a2 6
02 7
17 06
16 a6
15 as
14 05
13 04
12 a4
11 CK
03 8
a3 9
GN010
TRUTH TABLE
TC74AC534
OE 1
INPUTS
OE CK
OUTPUTS
0
0(374)
0(534)
H
X
X
Z
Z
L
L
S
S
X
On
L
L
On
H
H
H
L
L
L
0'0 2
DO 3
01 4
01 5
02 6
02 7
03 8
x : Don't Care
03 9
GNO 10
Z .!.!figh Impedanca
: No Canga
a.(an )
20 Vee
19 Q7
18 07
17 06
16 06
15
14 05
13 04
12 Q4
11 CK
aS
~I~.~CNM--------------------------~--------------------------------
AC-248
TC74AC374P I FI At, TC74AC534P I FI At
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
Supply Voltage Range
-0.5 -6.0
Vcr;
DC Input Voltage
-0.5 -Vcr;+0.5
VIN
DC Output Voltage
-0.5 -Vcr;+0.5
Vour
Input Diode Current
±20
11K
Output Diode Current
±50
10K
DC Output Current
±50
lour
DC Vcr;/Ground Current
Icr;
±200
Power Dissipation
500(DIP) */180(SOP)
Po
Storage Temperature
-65 -150
Tslg
Lead Temperature 10sec
300
TL
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VALUE
Su pply Voltage
2.0-5.5
Vcr;
Input Voltage
0- Vcr;
VIN
Output Voltage
0- Vcr;
Vour
Operating Temperature
Topr
-40 - 85
Input Rise and Fall Time
DC
ELECTRICAL
dt/dv
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
UNIT
V
V
V
"C
0- 10O(Vcr;=3.3±O.3V)
o-
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
ns/v
20(Vcr;= 5 ±0.5V)
CHARACTERISTICS
r---
PARAMETER
SYMBOL
High-Level
Input Voltage
V IH
Low-Level
Input Voltage
VIL
High-Level
Ou tpu t Voltage
Va-!
Ta=-40-85"C
Ta=25"C
Vcr; MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
2.10
3.0 2.10
5.5 3.85
3.85
2.0
0.50
0.50
V
0.90
3.0
0.90
1. 65
5.5
1. 65
2.0
1.9
2.0
1.9
!oo=-50,uA
3.0
2.9
3.0
2.9
4.5
4.4
4.5
4.4
V
2.48
3.0 2.58
1oH=-4mA
-. 3.80 la;=-24mA 4.5 3.94
3.85
!oo=-75mA* 5.5
2.0
0.0
0.1
0.1
IOL=50,uA
0.0
0.1
3.0
0.1
4.5
0.1
0.0
0.1
V
0.36
3.0
0.44
IOL=12mA
0.44
0.36
4.5
IOL=24mA
5.5
1. 65
IOL=75mA*
TEST CONDITION
-
V IN =
V IH or V IL
-
-
VIN=
-
Low-Level
Output Voltage
VOL
a-State Output
Off-State Current
ICE
VIN=VIH or VIL
Vour=Vcr; or GND
5.5
Input Leakage Current
Quiescent Supply Current
liN
Icr;
VIN=V cr; or GND
VIN=V cr;or GND
5.5
5.5
VIH or VIL
-
-
-
±0.5
-
±5.0
±O.I
8.0
-
±1.0
80.0
,uA
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a lOms maximum duration.
----------------------------------------------------------~... caRP~~
AC-249
TC74AC374P/F/FW,TC74AC534P/F/FW
IEC LOGIC SYMBOL
TC74AC634
TC74AC374
OE
Of
CK
CK
aD
01
02
03
00
01
02
03
D4
Q4
OS
06
as
as
07
07
00
Co
01
D2
03
D4
OS
01
02
03
Q4
Cis
Cis
07
SYSTEM DIAGRAM
TC74AC374
TC74AC534
00
01
02
D3
D4
05
D6
07
CK--I~
t pLH
tpl-D..
3.3±0.3
5.0±0.5
t~
t pZH
Output Disable Time
Maximum Clock Frequency
Output Enable Time
Ta--40 -85"C UNIT
LIMIT
ns
Ta--40~85"C
MIN.
MAX.
-
-
8.5
6.1
15.8
8.7
1.0
1.0
18.0
10.0
3.3±0.3
5.0±0.5
-
7.5
6.1
14.0
8.7
1.0
1.0
16.0
10.0
tpLZ
tpHZ
3.3±0.3
5.0±0.5
-
5.5
4.7
12.3
7.0
1.0
1.0
14.0
8.0
fMAX
3.3±0.3
5.0±0.5
55
100
120
160
-
-
55
100
-
UNIT
ns
MHz
Input Capacitance
CIN
5
10
10
pF
Output Capacitance
Coor
10
Power Dissipation Capacitance Cpo(1)
37
Note (1) C A) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iccq,o=C po. Va;. f IN +1 a; 18(per F/F)
And the total Cpo when n pes. of F/F operate can be gained by the following equation:
CPO (total)= 25+ 12· n
AC-2S1
TC74ACT374P/F/RN,TC74ACT534P/F/RN
OCTAL D-TVPE FLIP-FLOP WITH 3-STATE OUTPUT
TC74ACT374P/F/FW NON-INVERTING
TC74ACT634P/F/FW INVERTING
The TC74ACT374 and TC74ACT534 are advanced high
speed CMOS OCTAL FLIP-FLOP with 3-STATE
OUTPUT fabricated with silicon gate and double-layer
metal wiring C2MOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These devices may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL.NMOS and CMOS output
voltage levels.
These 8-bit D-type flip-flops are controlled by a clock input
eeK) and an output enable input COE).
When the OE input is high. the eight outputs are in a
high impedance state.
The TC74ACT374 has non-inverting outputs. and TC74
ACT534 has inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ......... ........•......... fMAX = 180MHz (typ.) at Vcc = 5V
• Low Power Dissipation ............... lcc=8ttA(Max.) at Ta=25"C
~ Compatible with TTL outputs ...... V1L =Q.8V(Max.)
ViH=2V(Min.)
• Symmetrical Output Impedance ... , 1m' =IOL =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH"'t pHL
• Pin and Function Compatible with 74F 374/534
P( 0IP20-P-300A)
20~ 20~
1
F(SOP20-P-300)
1
FW(SOL20-P-300)
PIN ASSIGNMENT (TOP VIEW)
TC74ACT374
OE
00 2
DO 3
01
4
01
5
02 6
02 7
03 8
03 9
TRUTH TABLE
GNO 10
20
19
18
17
16
15
14
13
12
11
Vee
20
19
18
17
16
15
14
13
12
11
Vee
07
07
07
07
06
06
05
05
04
04
CK
TC74ACT534
INPUTS
OE 1
OUTPUTS
00 2
DO 3
OE
CK
0
0(374)
0(634)
H
X
X
X
Z
Z
01
4
On
01
5
L
L
L
L
S
S
L
L
On
H
H
H
L
'02 6
02 7
x : Don't
03 8
Care
Z .;Jtigh Impedance
On(On) : No Change
03 9
GN010
06
06
05
05
04
04
CK
~IBACa~A~N------------------------------------------------------------
AC-252
TC74ACT374P/F/RN,TC74ACT534P/F/RN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
VOlJf
11K
10K
IOlJf
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -V<.."'C+0.5
-0.5 -Vee+0.5
±20
±50
±50
±200
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vee
Input Voltage
VIN
Output Voltage
VOlJf
Operating Temperature
Topr
Input Rise and Fall Time dt/dv
DC
ELECTRICAL
VALUE
4.5-5.5
0- Vee
0- Vee
-40 - 85
0-10
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
ViN=
VIHor VIL
Low-Level
Output Voltage
VOL
VIN=
VIHor VIL
3-State Output
Off-State Current
1m
VIN=VIH or VIL
VOlJf =Vee orGND
Input Leakage Current
lIN
lee
100=-50 IJ. A
Ioo=-24mA
lai=-75mA*
IOL=5O IJ. A
IOL=24mA
IOL=75mA*
VIN =Vee or GND
VIN =Vee or GND
Quiescent Supply Current
PER INPUT:VIN -3.4V
LIce OTHER INPUT:Vee or GND
* :This spec indicates the capability of driving son transmission lines.
Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
2.0
2.0
l
5.5
4.5
V
0.8
0.8
l
5.5
4.5 4.4
4.4
4.5
V
4.5 3.94
3.80
5.5
3.85
4.5
0.0
0.1
0.1
V
4.5
0.44
0.36
5.5
1. 65
5.5
-
-
±0.5
-
±0.5
5.5
5.5
-
-
±O.l
8.0
-
±1.0
80.0
5.5
-
-
1.35
-
1.5
IJ.A
rnA
One output should be tested at a time for a IOms maximum duration.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T C H I H I I I A CORPORATION
AC-253
TC74ACT374P I FI FW, TC74ACT534P1 FI FW
IEC LOGIC SYMBOL
TC74ACT534
TC74ACT374
OE
OE
CK
CK
ao
00
01
02
03
D4
05
as
OS
Q6
07
07
Co
00
01
02
03
D4
05
01
02
03
04
01
02
03
04
Os
06
07
SYSTEM DIAGRAM
TC74ACT374
02
01
D4
05
D4
05
OS
07
02
TC74ACT534
00
01
D2
03
OS
07
~~-----------------------------------------------------
AC-254
TC74ACT374PI FI AN, TC74ACT534P/F/AN
TIMING REQUIREMENTS(lnput tr=tt=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vee
Ta=25"C
TYP.
LIMIT.
Ta=-40 -85"C
UNIT
LIMIT.
Minimum Pulse Width
(CK)
tW(li)
tW(L)
5.0±O.5
-
5.0
5.0
Minimum Set-up Time
t8
5.0±O.5
-
3.0
3.0
Minimum Hold Time
th
5.0±O.5
-
2.0
2.0
AC ELECTRICAL CHARACTERISTICS(C L=50pF. RL =5000. Input t r =tf=3ns)
Ta-25"C
PARAMETER
SYMBOL .TEST CONDITION
MIN. TYP. MAX.
Vee
ns
Ta- 40-85"C
UNIT
MIN. MAX.
Propagation Delay Time
(CK-Q. Q)
t pLH
t pHL
5.0±O.5
-
6.1
9.6
1.0
11.0
Output Enable Time
tpZL
tpZH
5.0±O.5
-
6.2
10.1
1.0
11.5
Output Disable Time
tp(2
tpHZ
5.0±O.5
-
5.6
7.9
1.0
9.0
Maximum Clock Frequency
f~1AX
5.0±O.5
95
160
-
95
-
ns
MHz
Input Capacitance
5
Cn'..;
10
10
pF
Output Capacitance
COl;T
10
Power Dissipation Capacitance CPD(l)
34
Note (1) C ro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
leeq,o=C PD" VCC" fIN+I cc/8(per F/F)
And the total Cpo when n pcs. of F/F operate can be gained by the following equation:
Cpo (total)= + "n
------------------------------------------------------------TCHIHIBA~CHM
AC-255
TC74AC390P I FI FN
DUAL DECADE COUNTER
The TC74AC390 is an advanced high speed CMOS DUAL
DECADE COUNTER fabricated with silicon gate and
double-layer metal wiring dMOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
It consists of two independent 4-bit counters. each
composed of a divide-by-two and a divide-by-five
counter. The divide-by-two counter· is incremented on the
negative going transition of clock A(CKA). The divideby-five counter is incremented on the negative going
transition of clock B(CKB). The counter can be cascaded
to form decade. bi-quinary. or various combinations up
to a divide- by-lOO counter .. When the CLEAR input is set
high. the Q outputs are set low independent of the clock
inputs.
All inputs are equipped with protection circuits against
static dischage or transient excess voltage.
FEATURES:
• High Speed ................................. fMAX=160MHz(typ.) at Vcc=5V
• Low Power Dissipation ....•..•....... Icc=8.ttA(Max.) at Ta=25"C
• High Noise Immunity···· .. ········· VNlH=VNIL=2896 Vcc(Min.)
• Symmetrical Output Impedance ···1 1m 1=IOL=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH" tpliL
• Wide Operating Voltage Range ... Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74HC390
IEC LOGIC SYMBOL
1
P( DIP16-P-300A)
1.~"~
F(SOP16-P-300)
PIN ASSIGNMENT
lCKA 1
lCLR 2
16 vee
15 2CKA
lQA 3
14 2CLR
lCKB 4
13 2QA
12 2CKB
lQs 5
lQc 6
11 2QB
lQo 7
10 2Qe
9 2Qo
GND
8
(TOP
VIEW)
BLOCK DIAGRAM
CKA
ICKS
FN(SOL 16-P-150)
lOA
las
lac
lQo
CLR
1,15
BINARY
COUNTER
2.14
I
4.12
QUINARY
COUNTER
3.13 .
5,11
CKB
20A
20s
20c
200
6.10
7.9
QA
QB
QC
QD
L-J
Vcc=16.GND=8
~.HI~CO~~N---------------------------------------------------------------
AC-256
TC74AC390P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Vour
11K
10K
Ioor
lee
Po
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±50
±50
±200
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 55·C. From Ta=55·C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vee
0- Vee
-40 - 85
SYMBOL
Vee
VIN
VOLT
Topr
dtldv
UNIT
V
V
V
"C
0- 100(Vee =3.3±0.3V)
o-
CHARACTERISTICS
-
PARAMETER
SYMBOL
High-Level
Input Voltage
V IH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOi
Low-Level
Output Voltage
Va..
Input Leakage Current
Quiescent Supply Current
nslv
20(Vee= 5 ±0.5V)
Inx
lee
Ta=25"C
Vee MIN. TYP. MAX.
2.0 1. 50
3.0 2.10
5.5 3:85
2.0
0.50
0.90
3.0
5.5
1. 65
2.0
2.0
l.9
2.9
3.0
3.0
la-i=-50I1A
VIN=
4.5
4.4
4.5
3.0 2.58
V IH or VIL la-i=-4mA
la-i=-24mA 4.5 3.94
lai=-75mA* 5.5
2.0
0.0
0.1
3.0
0.0
O. 1
h.=50I1A
VIN=
O. 1
4.5
0.0
3.0
0.36
VIH or VIL Ia..=l2mA
0.36
IQL=24mA
4.5
5.5
IQL=75mA*
5.5
±O.l
VIN=V cc or GND
8.0
5.5
VIN=V cc or GND
TEST CONDITION
Ta=-40-85"C
UNIT
MIN. MAX.
1. 50
V
2.10
3.85
0.50
V
0.90
l. 65
l.9
2.9
4.4
V
2.48
3.80
3.85
O. 1
O. 1
O. 1
V
0.44
0.44
l. 65
±l.O
I1A
80.0
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a lOms maximum duration.
------------------------------TOIIHIBA
AC-257
CORPORATION
TC74AC390P I FI FN
TRUTH TABLE
INPUTS
CKB
CKA
~
X
X
X
~
X
OUTPUTS
CLR
H
L
L
I
I
QA
L
OB
L
J
I
OC
L
J
I
QD
L
BINARY COUNT UP
QUINARY COUNT UP
SYSTEM DIAGRAM
CKA
CLR
CKB
lD
1/15
QJ
3/13
CK R Q
"V
QA
'i
~'"'
h· DQ-
4/12
r5/11
CK RQ
~
QB
Y
lcD
Q-
CKRQ
..r-.
6/10
-v
QC
~
~D
CKRQ
7/9
QD
Y
TOSHIIIA CORPORATION
--------------~----------
AC-258
TC74AC390P/F/FN
TIMING CHART
m8CD
COUNT SEQUENCE-
CKA
CLR
QA
Q8
QC
QD
-.,
I
--,
I
-,
-ll
2
CLR
•
(2)81-QUINARY
4
3
8
10
9
11
o
12
2
connected to CK8
QA
COUNT
SEQUENCE-'
CK8
Jl~
CLR
____________________________
Q8
QC
QD
QA
-,_J
-,_J
Jl
CLR
2
3
QD
4
I
8
9
10
11
12
I
0
2
connected to CKA
----------------------------TaIlHIEIA
AC-259
CORPORATION
TC74AC390P I FI FN
TIMING REQUIREMENTS (Input tr=tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vee
Ta-25"C
TYP.
LIMIT
Minimum Pulse Width
(CLOCK)
tW(H)
tW(L)
3. 3±0. 3
5. O±O. ~
Minimum Pulse Width
(CLR)
tW(H)
3. 3±0. 3
5. O±O. 5
-
Minimum Removal Time
t rem
3. 3±0. 3
~. O±O. 5
-
-
Ta- 40 -85"C
UNIT
LIMIT
7.0
5.0
7.0
5.0
7.0
5.0
7.0
5.0
7.0
3.5
7.0
3.5
ns
AC ELECTRICAL CHARACTERISTICS(CL=50pF,RL=500Q,lnput tr=tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vee
MIN.
-
Propagation Delay Time
(CKA-QA)
tpLH
tpHL
~. 3±0. 3
Propagation Delay Time
(CKA-QC)
tpLH
tP/-IL
QA connected to 3±0. 3
CKB
~. O±O. 5
p.
-
Propagation Delay Time
(CKB-QB,QD)
tpU-I
tpHL
Propagation Delay Time
(CKB-QC)
Ta=25°C
Ta=-40 -85"C
UNIT
TYP. MAX. MIN. MAX.
8.2
5.5
14.0
8.4
1.0
1.0
16.0
9.6
-
17.0
10.5
30.0
17.5
1.0
1.0
34.0
20.0
'3. 3±0. 3
5. O±O. ~
-
8.8
6.0
14.9
9.4
1.0
1.0
17.0
10.7
tpLH
tpHL
3. 3±0. 3
5. O±O. 5
-
11. 0
7.1
18.8
11.3
1.0
1.0
21. 5
12.8
Propagation Delay Time
(CLR-Qn)
tpHL
3. 3±0. 3
5. O±O. 5
-
7.7
5.7
12.5
8.5
1.0
1.0
14.3
9.7
Maximum Clock Frequency
(CKA)
hlAx
~. 3±0. 3
60
p. O±O. 5 100
120
180
-
60
100
-
Maximum Clock Frequency
(CKB)
f~x
~. 3±0. 2
~. O±O. ~
90
140
-
45
90
~.
O±O. ~
45
90
-
-
ns
MHz
-
Input Capacitance
eli':
5
10
10
pF
Power !)issipation Capacitance CPD(1)
40
Note (1) C PD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lee WD =CPD • Vo:;. f[\ +10:; 12(per Counter)
-
-
-
~18A~~aN--------~------------------------------------------------
AC-260.
TC74AC393P/F/FN
DUAL BINARY COUNTER
The TC74AC393 is an advanced high speed CMOS 4-BIT
BINARY COUNTER fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
It contains two independent counter circuits in one
package, so that counting or frequency division of eight
binary bits can be achieved with one IC.
This device changes state on the negative going
transition of the CLOCK pulse. The counter can be reset
to "0" (QO-Q3="L") by a high at the CLEAR input
regardless of other inputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. fMAX= MHz(Typ.)at Va;=5V
'. Low Power Dissipation ............ Ia;=8ttA(Max.)at Ta=25°C
• High Noise Immunity··············· V:\[I-/=VNlL28% Va; (Min.)
• Symmetrical Output Impedance ... 1101-1 I =IOL =24mA(Min.}
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLI-I""tpHL
• Wide Operating Voltage Range ... Va; (opr.}=2V-5.5V
• Pin and Function Compatible with 74HC393
P( 01 P14-P-300)
14~14~
1
F(SOP14-P-300)
FN(S0L14-P-150)
PIN ASSIGNMENT
14 Vee
lCK
lCLR 2
13 2CK
lOA
lOB
12 2CLR
4
11
20A
10 20B
lOC
100 6
9
20C
OND 7
8
200
(TOP VIEW)
IEC LOGIC SYMBOL
CTRoIV16
lCLR
+
lCK
2CLR
2CK
c{
lOA
lOB
lOC
100
20A
12
208
20C
13
200
--------------------------------Ta8HIBA
AC-261
CORPORATION
TC74AC393PI FI FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vex/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Voor
11K
ICJK
Ioor
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±200
500(DIP) */180(SOP)
-65 -150
300
UNIT
V
V
V
mA
mA
mA
mA
mW
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmWrC shall be applied
until300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
Vee
VIN
Voor
Topr
dtldv
UNIT
V
V
V
"C
VALUE
2.0-5.5
0- Vee
0- Vee
-40 - 85
SYMBOL
o-
10O(Vee =3.3±0.3V)
ns/v
0- 20(Vee= 5 ±O.5V)
CHARACTERISTICS
r--
Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
1. 50
2.0 1. 50
High-Level
V
2.10
V IH
3.0 2.10
Input Voltage
3.85
5.5 3.85
2.0
0.50
0.50
Low-Level
V
0.90
0.90
V
3.0
IL
Input Voltage
1. 65
1. 65
5.5
2.0
2.0
1.9
1.9
loH=-50f,tA
3.0 2.9
3.0
2.9
VIN =
4.5
4.4
4.5
4.4
High-Level
V
VOH
Output Voltage
3.0 2.58
2.48
V IH or V IL IoH =-4mA
3.80
loH=-24mA 4.5 3.94
3.85
I{)I!=-75mA* 5.5
2.0
0.0
O. I
0.1
0.0
IOL=50f,tA
3.0
O. I
0.1
VIN=
4.5
0.0
0.1
0.1
Low-Level
V
VOL
Output Voltage
3.0
0.44
0.36
IOL=12mA
VIH or VIL
0.36
0.44
4.5
IOL=24mA
5.5
1. 65
IOL =75mA*
- ±I.O
5.5
Input Leakage Current
±0.1
VIN=Vee or GND
lIN
f,tA
Quiescent Supply Current
8.0
80.0
5.5
VIN=Vee or GND
lee
..
.
.
..
• :This spec mdICates the capability of dnvmg 500 translUlSSlon Imes .
PARAMETER
SYMBOL
TEST CONDITION
-
-
One output should be tested at a time for a lOms maximum duration.
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-262
TC74AC393P I FI FN
TRUTH TABLE
INPUTS
CLR
H
L
1:.
L
S
CK
X
OA
L
I
I
OUTPUTS
OB I OC
L
I L
COUNT UP
NO CHANGE
I
I
OD
L
X : Don't care
TIMING CHART
CK
CLR
QA
QB
QC
QO
··
·:
,
,
SYSTEM DIAGRAM
o
o
_
CK
o
1/13
.>-----1 CK R Q 1---+---1 CK R Q 1---+---1 CK R Q 1---+----1 CK R Q
5/9
QA
QB
6/8
QC
QO
--------------------------------~---------------~HIBAcaRPOR~aN
AC-263
TC74AC393P/F/FN
TIMING REQUIREMENTS (Input t r =t,=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vee
Ta-25"C
TYP.
LIMIT
Minimum Pulse Width
(CK)
tW(I!)
tW(L)
~. 3±O. 3
~. O±O. 5
-
Minimum Pulse Width
(CLR)
tW(I!)
~. 3±O. 3
~. O±O. 5
-
Minimum Removal Time
t rem
~. 3±O. 3
~. O±O. 5
-
Ta--40 -85"C
UNIT
LIMIT
ns
AC ELECTRICAL CHARACTERISTICS(CL=50pF,RL=5000 Input tr=tt=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vee
MIN.
Ta=-40 -85"C
Ta=25"C
UNIT
TYP. MAX. MIN. MAX.
Propagation Delay Time
(CK-QA)
tpLH
tpHL
3. 3±O. 3
J. O±O. 5
-
1.0
1.0
Propagation Delay Time
(CK-QB)
tpLH
tpl1L
~. 3±O. 3
~. O±O. 5
-
1.0
1.0
-
-Propagation Delay Time
(CK-QC)
i1,LH
tpllL
~. 3±O. 3
~. O±O. 5
-
1.0
1.0
Propagation Delay Time
(CK-QD)
~H
~. 3±0. 3
tpiiL
~. O±O. 5
-
1.0
1.0
Propagation Delay Time
(CLR-Qn)
tpliL
j. 3±O. 3
5. O±O. 5
-
1.0
1.0
Maximum Clock Frequency
fMAX
3. 3±O. 3
J. O±O. 5
-
I
-
ns
MHz
Input Capacitance
CIN
5
10
10
pF
Power Dissipation Capacitance
CPD(l)
Note (1) Cm is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iccqm=C pD • Va::. f 1:\ +Ia:: /2(per circuit)
TOSHIBA CORPORATUON------------------------------------------------------------
AC-264
TC74AC540P/F/RN, TC74AC541P/F/RN
OCTAL BUS BUFFER
TC74AC640P/F/FW INVERTING.3-STATE OUTPUTS
TC74AC641P/F/FW NON-INVERTING.3-STATE,...::O""'U""-'-T.....
P....,U.....,T'-'S=<--_ _ _ _ _ _---,
The TC74AC540/TC74AC541 are advanced high speed
CMOS OCTAL BUS BUFFERs fabricated with silicon
gate and double-layer metal wiring C2MOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The TC74AC540 is a non-inverting type, and the TC74A
C541 is an inverting type.
When either G1 or G2 are high, the terminal outputs are
in the high-impedance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P( DIP20-P-300A)
F(SOP20-P-300)
FEATURES;
• High Speed .............................. tpd = 4.0ns (typ.) at Vee = 5V
• Low Power Dissipation ............ Ia:;=8.uA(Max.)at Ta=25"C·
• High Noise Immunity··············· VNIH=V!,\IL28% Va:; (Min.)
• Symmetrical Output Impedance ... I IOH I =IOL =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH~tpHL
• Wide Operating Voltage Range ... Va:; (opr)=2V -5.5V
• Pin and Function Compatible with 74F540/541
FW(SOl20-P-300)
TRUTH TABLE
INPUTS
OUTPUTS
Yn*
Yn*
G1
G2
An
H
X
X
X
H
X
Z
Z
Z
Z
l
L
H
H
L
L
L
L
L
H
x : Don't Care
Z
*
: High Impedance
; Yn······AC541
Vn······AC540
PIN ASSIGNMENT
TC74AC540
TC74AC541
G1 1
20 Vee
G1
20 Vee
A1 2
19- G2
A1 2
19 G2
A2 3
18 Y1
A2 3
18 Y1
A3 4
17 Y2
A3 4
17 Y2
A4 5
16 Y3
A4 5
16 Y3
A5 6
15 Y4
A5 6
15 Y4
A6 7
14 Y5
AU 7
14 Y5
A7 8
13 Y6
A7 8
13 Y6
A8 9
12 Y7
AS 9
12 Y7
GND 10
11 Y8
GND 10
11 Y8
(TOP
VIEW)
TOSHIBA CORPORATION
AC-265
TC74AC540P/F/FW,TC74AC541P/F/FW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Va;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Va;
VIN
Vour
11K
10K
lour
Ia;
Po
Tstg
TI,
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5 -6.0
-0.5 -Va; +0.5
-0.5 -Va;+0.5
±20
±50
±50
±200
500(DIP) ./180(SOP)
-65 -150
300
*500m W in the range of Ta=
-40'C- 65·C. From Ta=65"C
to 85"C a derating factor of
-lOmWI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
Va;
VIN
Vour
Topr
dt/dv
UNIT
V
V
V
"C
VALUE
2.0-5.5
0- Va;
o -Va;
-40 - 85
SYMBOL
0-lOO(Va;=3.3±0.3V)
ns/v
0- 20(Va;= 5 ±0.5V)
CHARACTERISTICS
r----
PARAMETER
SYMBOL
High-Level
Input Voltage
V1H
Low-Level
Input Voltage
V1L
High-Level
Output Voltage
TEST CONDITION
YiN=
VOH
VIHor V1L
VIN=
IOH=-50JlA
Iar--4mA
Iar--24mA.
Iar-- 75mA *
IOL =50JlA
Ta=-40-85"C
Ta=25"C
Va; MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
5.5 3.85
3.85
2.0
0.50
0.50
V
0.90
0.90
3.0
5.5
1. 65
1. 65
2.0
1.9
2.0
l.9
3.0 2.9
3.0
2.9
4.5 4.4
4.5
4.4
V
3.0 2.58
2.48
4.5 3.94
3.80
5.5
3.85
2.0
0.0
0.1
0.1
3.0
0.0
0.1
0.1
4.5
0.0
O. I
0.1
0.36
3.0
0.44
V
4.5
0.44
0.36
1. 65
5.5
Low-Level
Output Voltage
VOL
3-State Output
Off-State Current
Iai:
VIN=VIH or VIL
. Vour=Va; orGND
5.5
Input Leakage Current
Quiescent Supply Current
liN
Ia;
VIN =Va; or GND
VIN =Va; or GND
5.5
5.5
VIHor VIL
IOL=12mA
IOL=24mA
IOL=75mA.
-
-
±0.5
±0.1
8.0
-
±0.5
±1.0
80.0
JlA
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a lOms maximum duration.
,-oIIH11IA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-266
TC74AC540P/F/RN,TC74AC541P/F/AW
IEC LOGIC SYMBOL
TC74AC540
TC74AC541
Gl
G2
Gl
G2
Al
A2
A3
A4
AS
A6
A7
Aa
VI
V2
Y3
Y4
Y5
Y6
V7
va
Al
A2
A3
A4
A5
A6
A7
Aa
VI
V2
V3
V4
V5
V6
V7
va
AC ELECTRICAL CHARACTERISTICS(C L=50pF. RL =5000. Input t r =t,=3ns)
Ta--40-85"C
Ta-25"C
UNIT
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX. MIN. MAX.
Vcr
tpLH
3.3±0.3
10.5
6.8
1.0
12.0
Propagation Delay Time*
tpHL
7.0
5.0±0.S
1.0
4.7
8.0
3.3±0.3
11.4
6.8
1.0
13.0
tpLH
Propagation Delay Time*' tpHL
S.0±0.5
7.5
1.0
8.5
4.7
ns
tpZl.
3.3±0.3
9.6
1.0
15.8
18.0
Output Enable Time
tpZl-i
1.0
5.0±0.5
6.4
10.0
11.4
tpLZ
3.3±0.3
12.3
1.0
7.7
14.0
Output Disable Time
tpHZ
5.0±0.5
9.3
1.0
6.4
10.5
Input Capacitance
CN
10
10
5
CQ.;T
Output Capacitance
10
pF
Power Dissipation
25
CF!) (1) TC74AC540
Capacitance
TC74AC541
28
Note (1) C F!) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC(opr.)=CF!) - Vcr- fl.'\ +1 cr 18(per bit)
{21. for TC74AC540 only
•• for TC74AC541 only
------------------------------------------------------------TOaHIBA ~POR~
AC-267
TC74ACT540P/F/RN,TC74ACT541P/F/RN
OCTAL BUS BUFFER
TC74ACT640P/F/FW
TC74ACT641P/F/FW
INVERTING,3-STATE OUTPUTS
NON -I NVE RTI NG,3-ST A,r-T-=E.....:=O~UwTwP....:U!:!..T~S_ _ _ _ _ _..,
The TC74ACT540/TC74ACT541 are advanced high speed
CMOS OCTAL BUS BUFFERs fabricated with silicon
gate and double-layer metal wiring C2MOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These devices may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL, NMOS and CMOS output
voltage levels.
The TC74ACT540 is a non-inverting type, and the TC74
ACT541 is an i~verti~ type.
When either Gl or G2 are high, the terminal outputs are
in the high-impedance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P( DIP20-P-300A)
m~m~
1
F(SOP20-P-300)
1
FW(SOL20-P-300)
TRUTH TABLE
FEATURES:
• High Speed .............................. 11>d = 4.3ns (typ.) at Vee = 5V
• Low Power Dissipation ............ Icc =8.uA(Max.)at Ta=25"C
• Compatible with TTL outputs······ V IL =O.8V (Max.)
V IH =2.0V (Min.)
• Symmetrical Output Impedance ... I IOH I =101. =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH'" tpHL
• Pin and Function Compatible with 74F540/541
INPUTS
OUTPUTS
Yn*
Yn*
X
Z
Z
Z
Z
L
H
H
L
L
L
L
H
G2
An
H
X
X
X
H
L
L
G1
x : Don't Care
Z
: High Impedance
*
: Yn······ACT541
Vn······ACT540
PIN ASSIGNMENT
TC74ACT540
TC74ACT541
G1 1
20 Vee
G1 1
20 Vee
A1 2
19 (32
A1 2
19 G2
A2 3
18 Y1
A2 3
18 Y1
A3 4
17
17 Y2
16
Y2
Y3
Y4
V5
V6
V7
A3 4
A4 5
A4 5
16 Y3
A5 6
15 Y4
A6 7
14 Y5
A7 8
13 Y6
A8 9
12 Y7
GND 10
11 Y8
A5 6
15
A6 7
14
A7 8
13
A8 9
12
GND10
11 VB
(TOP VIEW)
~IBA CO~RA~N-----------------------------------------------------------
AC-268
TC74ACT540P/F/RN,TC74ACT541P/F/RN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
V,:-.i
VOUT
1'K
10K
Ioor
lee
PD
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±50
±50
±200
500(DIP) *1l80(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmWI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
SYMBOL
VALUE
4.5-5.5
o -Vee
0- Vee
-40 - 85
0-10
Vee
V,:-;
Vour
Topr
dt/dv
UNIT
V
V
V
°C
ns/v
CHARACTERISTICS
,--
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VII.
High-Level
Output Voltage
va;
YiN==
Vn10r Vn.
Low-Level
Output Voltage
VOL
Yil\=
Vni or Vn.
3-State Output
Off-State Current
lal
V'1'<=VIH or VII.
Voor =Vee orGND
Input Leakage Current
l,N
lee
Quiescent Supply Current
~Icc
TEST CONDITION
Im=-50t.tA
Im=-24mA
IOi=-75mA*
IOL=50tLA
IOL=24mA
IOL=75mA*
VI:', =Vcr, or GND
V,:-i =Vcr, or GND
PER INPUT:V,:-I -3.4V
OTHER INPUT:Vcr, or GND
Ta==-40-85"C
Ta=25°C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
4.5
V
2.0
2.0
I
5.5
4.5
V
0.8
0.8
I
5.5
4.5 4.4
4.5
4.4
V
4.5 3.94
3.80
3.85
5.5
4.5
0.0
0.1
O. I
V
0.36
0.44
4.5
1. 65
5.5
5.5
5.5
5.5
5.5
-
-
±0.5
-
±5.0
-
-
±0.1
8.0
-
±1.0
80.0
-
-
1.35
-
1.5
J1A
rnA
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a lOms maximum duration.
-------------------~----------TOBHIBA
AC-269
CORPORATION
TC74ACT54OP/F/FW,TC74ACT541P/F/FW
IEC LOGIC SYMBOL
TC74ACT540
TC74ACT541
(;1
01
02
<32
A1
A2
A3
A4
A5
A6
A7
AS
"1
"2
Y3
Y4
A1
A2
A3
A4
Y4
"6
"6
Y7
A5
A6
A7
A8
Y5
Y6
Y7
YS
V8
Y1
Y2
Y3
(9)
(11)
AC ELECTRICAL CHARACTERISTICS(C L =50pF, RL =500Q, Input t r =t,=3ns)
Ta-25OC
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX.
Va:.
tpLH
tpi-lL
5.0±0.5
-
Propagation Delay Time*' tpLH
tpilL
5.0±0.5
tpZL
tpZH
Propagation Delay Time*
Output Enable Time
Output Disable Time
tpLZ
tpl-{Z
CIN
COlf
Ta- 40-85OC
UNIT
MIN. MAX.
5.0
8.3
1.0
9.5
-
5.0
8.3
1.0
9.5
5.0±0.5
-
7.3
11.4
1.0
13.0
5.0±0.5
-
5.9
9.2
1.0
10.5
Input Capacitance
Output Capacitance
Power Dissipation
CR) (I) TC74ACT540
Capacitance
TC74ACT541
Note (1) C R) is defined as the value of the internal equivalent
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC(opr.)=CR) • Va:.. fIN +1 a:. 18(per bit)
(2). for TC74ACT540 only
•• for TC74ACT541 only
-
-
ns
-
5
10
10
10
pF
24
27
capacitance which is calculated from the
~~I~ C~~~"ON---------------------------------------------------------------
AC-270
TC74AC563P/F/RN,TC74AC573P/F/RN
OCTAL D-TVPE LATCH WITH 3-STATE OUTPUT
TC74AC563P/F/FW
INVERTING
TC74AC573P/F/FW
NON-INVERTING
The TC74AC563 and TC74AC573 are advanced high
speed CMOS OCTAL LATCH with 3-STATE OUTPUT
fabricated with silicon gate and double-layer metal
wiring C~OS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These 8-bit D-type latches are controlled by a latch enable input
(LE) and an output enable input (OE).
When the OE input is high, the eight outputs are in a
high impedance state.
The TC74AC563 has inverting outputs, and TC74AC573
has non-inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP20-P-300A)
2~ m~
1
F(SOP20-P-300)
1
FW(SOL20-P-300)
PIN ASSIGNMENT
FEATURES:
• High Speed ................................. tpd=6.0 ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=8ttA(Max.) at Ta=25"C
• High Noise Immunity ...... ·........ Vi\IH=VNIL =28% Vcc(Min.)
• Symmetrical Output Impedance .. ·1 Ia; 1=IQL=24mA(Min.)
Capability of driving 50g
transmission lines.
• Balanced Propagation Delays ...... tpLH"tpHL
• Wide Operating Voltage Range .. · Vcc (opr)=2V-5.5V
• Pin and Function Compatible with 74F 563/573
TRUTH TABLE
TC74AC563
OE
DO
01
02
03
04
05
06
07
GNO
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vee
20
19
18
17
16
15
14
13
12
11
Vee
-00
01
02
03
04
05
06
07
LE
TC74AC573
INPUTS
OE
LE
OE
OUTPUTS
0
0(573)
0(563)
H
X
X
Z
Z
L
L
X
an
an
L
H
L
L
H
L
H
H
H
L
x : Don't Care
Z
1
DO 2
;Jjigh Imp.§.dance
outputs are latched at the time
when the LE input is taken to a low
logic level.
an (an) : a ca)
01
02
03
04
05
06
07
GNO
3
4
5
6
7
8
9
10
00
01
02
03
04
05
06
07
LE
TOSHIBA CORPORATION
AC-271
TC74AC563P I FI FW, TC74AC573P I FI FW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Va:;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Va:;
VIN
Voor
11K
10K
IOllr
I a:;
PD
Tstg
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
VALUE
-0.5 -6.0
-0.5 -Va:;+0.5
-0.5 -Va:;+0.5
±20
±50
±50
±200
500(DIP)*/180(SOP)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
SYMBOL
Va:;
VIN
Voor
Topr
dt/dv
VALUE
2.0-5.5
0- Va:;
0- Va:;
-40 - 85
UNIT
V
V
V
"C
O-100(Va:;=3.3±0.3V)
ns/v
0....... 20(Va:;= 5 ±0.5V)
CHARACTERISTICS
,.--
PARAMETER
SYMBOL
High-Level
Input Voltage
V IH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Ta=-40-85"C
Ta=25"C
Va:; MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
3.85
5.5 3.85
2.0
0.50
0.50
V
3.0
0.90
0.90
5.5
1. 65
1. 65
2.0
1.9
2.0
1.9
3.0
2.9
3.0
Irn=-50tlA
2.9
4.5
4.4
4.5
4.4
V
lQH=-4mA
3.0 2.58
2.48
lQH=-24mA 4.5 3.94
3.80
3.85
Jm=-75mA* 5.5
2.0
0.0
0.1
0.1
3.0
0.1
0.0
1oL=50tlA
0.1
4.5
0.0
0.1
0.1
V
0.36
3.0
0.44
1oL=12mA
0.36
4.5
IOL=24mA
0.44
5.5
1. 65
IOL=75mA*
TEST CONDITION
VIN=
V IH or V IL
-
Low-Level
Output Voltage
VIN=
VOL
VIH or VIL
-
-
a-State Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
1(Jl
liN
Ia:;
VN=VIH or VIL
Vexrr=Va:; or GND
5.5
VIN=V cc or GND
VIN=Va:; or GND
5.5
5.5
-
-
-
±0.5
±O.l
8.0
-
±5.0
±1.0
80.0
tl A
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a 10rns maximum duration.
~I~ CCMR~~N----------------------------------------------------------
AC-272
TC74AC563P/F/RN,TC74AC573P/F/RN
IEC LOGIC SYMBOL
TC74AC563
TC74AC573
OE
LE
00
CO
01
02
03
04
05
01
02
03
04
05
D6
as
07
07
SYSTEM DIAGRAM
TC74AC573
TC74AC563
-----------------------------TOaHIBA
AC-273
CORPORATION
TC74AC563P/F/AN,TC74AC573P/F/AN
TIMING REQUIREMENTS(lnput t r =tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vee
Ta-25"C
TYP.
LIMIT
Ta--40-85"C
LIMIT
Minimum Pulse Width
(LE)
twO\)
3.3±O.3
5.0±0.5
-
7.0
5.0
7.0
5.0
Minimum Set-up Time
ts
3.3±0.3
5.0±O.5
-
7.0
4.0
7.0
4.0
Minimum Hold Time
th
3.3±0.3
5.0±0.5
-
1.0
1.0
1.0
1.0
-
UNIT
ns
AC ELECTRICAL CHARACTERISTlCS(C L =50pF. RL =5000. Input t r =tf=3ns)
Ta--40 -B5"C
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
MIN. TYP. MAX. MIN. MAX.
Vee
Propagation Delay Time
(LE-Q. Q)
t pLH
t pHL
3.3±0.3
5.0±O.5
-
9.4
6.6
15.4
9.9
1.0
1.0
17.6
11. 3
Propagation Delay Time
(Dn-Q.Q)
t pLH
t pilL
3.3±O.3
5.0±0.5
-
9.4
6.2
16.0
B.9
1.0
1.0
1B.2
10.2
-
ns
Output Enable Time
tpZL
tpZH
3.3±0.3
5.0±0.5
-
-
9.0
6.3
15.2
9.2
1.0
1.0
17.3
10.5
Output Disable Time
tpLZ
t p1-1Z
3.3±0.3
5.0±O.5
-
7.0
6.0
12.3
B. B
1.0
1.0
14.0
10.0
Input Capacitance
CIN
5
10
10
pF
Output Capacitance
Carr
10
Power Dissipation Capacitance CPD(1)
32
Note (1) C I'D 1S defmed as the value of the mternal equ1valent capaCItance wh1ch 1S calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lee q,o=C PD ° Va:: ° f IN + I a:: IS( per Latch)
And the total CPD when n pcs. of Latch operate can be gained by the following equation:
CpD (total) =21 +11 ° n
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-274
TC74ACT563P/F/FVV, TC74ACT573P/F/FVV
OCTAL D-TVPE LATCH WITH 3-STATE OUTPUT
TC74ACT663P/F/FW INVERTING
TC74ACT673P/F/FW NON-INVERTING
The TC74ACT563 and TC74ACT573 are advanced high
speed CMOS OCTAL LATCH with 3-STATE OUTPUT
Cabricated with silicon gate and double-layer metal
wiring C2MOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These devices may be used as a level converter Cor
interCacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
These 8-bit D-type latches are controlled by a latch
enable (LE) and a output enable input (OE).
When the OE input is high, the eight outputs are in a
high impedance state.
The TC74ACT573 has non-inverting outputs, and the
TC74ACT563 has inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=5.5ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=8.uA(Max.) at Ta=25"C
• Compatible with TTL outputs ...... VIL =O.8V (Max.)
V IH =2.0V (Min.)
• Symmetrical Output Impedance .. ·11 oHI=loL=24mA(Min.)
Capability of driving 50£1
transmission lines.
• Balanced Propagation Delays ...... tpLH .. tpHL
• Pin and Function Compatible with 74F563/573
TRUTH TABLE
P(DIP20-P-300A)
2~ 20~
1
1
F(SOP20-P~300)
FW(SOI.20-P-300)
PIN ASSIGNMENT (TOP VIEW)
TC74ACT563
OE
1
20 Vee
DO
2
19
-00
01
3
02
03
4
5
18 01
17 '02
16 '03
04
05
6
7
15 '04
14 05
06
8
13 06
07 9
GNO 10
12 07
11 LE
TC74ACT573
INPUTS
OUTPUTS
OE
1
DO
2
OE
LE
0
H
X
Z
Z
01
3
L
L
X
X
Qn
Qn
L
I-L
H
L
L
H
02
03
4
5
H
H
H
L
04
0(573)
0(563)
X : Don't Care
Z;"tligh ImlUldance
an (an) : a (a) outputs are latched at the time
when the I.E input is taken low.
20 Vee
19 00
18 01
6
17 02
16 03
15 04
05
7
14
05
06
8
13
06
07 9
GNO 10
12 07
11 LE
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T O B H I B A CDRPDRATION
AC-275
TC74ACT563PIF IFW, TC74ACT573PIF IFW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI:>':
Va.T
11K
Ia<
Ia.T
lee
Po
Tstg
TL
VALUE
-O.S -6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±200
500(DlP)*/180(SOP)
-65 -ISO
300
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10mWI"C should be applied
up to300mW.
RECOMMENDED OPERATING CONDITIONS
VALUE
4.5-5.5
0- Vee
0- Vee
-40 -' 85
0-10
PARAMETER
SYMBOL
Supply Voltage
Vee
Input Voltage
VI:>':
Output Volt'age
Vcx.T
Operating Temperature
Topr
Input Rise and Fall Time dtldv
DC
ELECTRICAL
PARAMETER
CHARACTERISTICS
SYMBOL
TEST CONDITION
"'H
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
V(}f
"':>.:=
VIHorVIL
Low-Level
Output Voltage
Va.
\'r:..=
VIHor VIL
3-State Output
OCC-State Current
lcz
VI:,,=VIH or VIL
Va.T =Vee or GND
Input Leakage Current
II:"
lee
Alee
-
Ta=2S"C
Vee MIN. TYP. MAX.
4.S
2.0
1
5. S
4.S
0.8
1
5. S
4.S 4.4
4.5
4.5 3.94
5.5
4.5
0.0
0.1
4.5
0.36
5.5
-
High-Level
Input Voltage
Quiescent Supply Current
UNIT
V
V
V
"C
nslv
Iar--SO#A
ICJi=-24mA
Iar--75mA.
Icx.=50 JlA
Icx.=24mA
Icx.=75mA*
VI:" =Vee or GND
VI:" =Vee or GND
PER INPUT:VI:" =3.4V
OTHER INPUT:Vee or GND
-
-
--
---
5. S
-
5.5
5.5
-
5.5
-
-
-
--
±0.5
±O.l
8.0
1. 35
Ta=-40-8S"C
UNIT
MIN. MAX.
2.0
-
V
-
0.8
V
4.4
3.80
3.85
---
V
0.1
0.44
1. 65
V
---
±S.O
±1.0
80.0
1.5
JlA
mA
:This spec indicates the capability oC dnving 500 transmission lines.
One output should be tested al a lime Cor a lOms maximum duration.
TDSHIBA CORPORATIDN - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-276
TC74ACT563P IFIFW, TC74ACT573P IF IFW
IEC LOGIC SYMBOL
TC74ACT563
TC74ACT573
OE
OE
LE
LE
Co
DO
01
02
03
01
02
03
04
Os
06
D4
OS
Q4
D6
Q6
07
07
07
CO
01
02
03
as
SYSTEM DIAGRAM
TC74ACT573
DO
02
OS
TC74ACT563
---------------------------------------------------TOSHIBACDRPDRAnDN
AC-277
TC7 4ACT563P IF IFW, TC7 4ACT573P IF IFW
TIMING REQUIREMENTS(lnput tr=t,=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vrr.
Ta=2S"C
TYP.
LIMIT
Ta=-40 -85"C UNIT
LIMIT
Minimum Pulse Width
(LE)
tW(H)
S.O±O.S
-
5
5
Minimum Set-up Time
ts
S.0±0.5
-
3
3
Minimum Hold Time
til
5.0±0.S
-
2
2
ns
AC ELECTRICAL CHARACTERISTlCS(C L=50pF, RL =5000, Input t r =t,=3ns)
PARAMETER
SYMBOL TEST CONDITION
Va;
MIN.
Ta-25"C
TYP. MAX.
'1'a=-40-85"C
UNIT
MIN. MAX.
Propagation Delay Time
(LE-Q. Q)
t pLH
t pI-IL
S.0±0.5
-
6.3
10.5
1.0
12.0
Propagation Delay Time
(Dn-Q.Q)
t pLH
t pliL
5.0±0.5
-
6. 2
9.6
1.0
11. 0
Output Enable Time
tp7.L
tpZH
5.0±0.5
-
6. 5
10.0
1.0
11.5
Output Disable Time
tpl2;
tpHZ
S.O±0.5
-
6.5
8.B
1.0
10.0
ns
Input (. apacltance
Output Capacitance
5
10
10
pF
10
Power Dissipation Capacitance Cpo (1)
22
Note (1) eft) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia; q,c=C PO • Va::' r IN + I a:: 18( per Latch)
And the total CpD when n pes. of Latch operate can be gained by the following equation:
CpD (total)=6+16' n
GIN
Cem
-
-
-
-
TO.HIIIA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TC74AC564P/F/RN,TC74AC574P/F/RN
OCTAL D-TVPE FLIP-FLOP WITH 3-STATE OUTPUT
TC74AC564P/F/FW
INVERTING
TC74AC674P/F/FW
NON-INVERTING
The TC74AC564 and TC74AC574 are advanced high
speed CMOS OCTAL FLIP-FLOP with 3-STATE
OUTPUT fabricated with silicon gate and double-layer
metal wiring C~OS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These 8-bit D-type flip-flops are controlled by a clock input (CK)
and an output enable input (OE).
When the OE input is high. the eight outputs are in a
high impedance state.
The TC74AC564 has inverting outputs. and TC74AC574
has non-inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. fMAx=180MHz(typ.) at Vee=5V
• Low Power Dissipation ............... Iee=8J.tA(Max.) at Ta=25"C
• High Noise Immunity ............... V NIH = V!\IL =28" Vee (Min.)
• Symmetrical Output Impedance .. ·1 1m 1=IQL=24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH"'tpI-IL
• Wide Operating Voltage Range ... Vee (opr)=2V-5.5V
• Pin and Function Compatible with 74F 564/574
TRUTH TABLE
P(OIP20-P-300A)
20~ ~~
1
F(SOP2C-P-300)
1
FW(SOL20-P-300)
PIN ASSIGNMENT (TOP VIEW)
TC74AC564
OE 1
DO 2
01
02
03
04
05
06
07
3
4
5
6
7
8
9
GNO 10
20
19
18
17
16
15
14
13
12
11
Vee
20
19
18
17
16
15
14
13
12
11
Vee
-00
01
02
03
04
05
06
07
CK
TC74AC574
INPUTS
OE
CK
D
0(574 )
0(564 )
H
X
Z
Z
L
LS
S
X
X
an
an
L
L
H
H
H
L
L
L
x
OE 1
DO 2
OUTPUTS
01
02
03
04
05
06
07
3
4
5
6
7
8
9
GNO 10
:Oon1Care
Z ~igh Impedance
an (an) : No Change
00
01
02
03
04
05
06
07
CK
TOSHIBA CORPORATION
AC-279
TC74AC564P/F/RN,TC74AC574P/F/RN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
VOlJT
11K
10K
Ioor
lee
Po
Tstg
TL
VALUE
-0.5 -6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±200
500(DIP)·/180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
°C
OC
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m Wrc shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2.0-5.5
0- Vee
0- Vee
-40 - 85
SYMBOL
Vee
VIN
Vour
Topr
dt/dv
UNIT
V
V
V
OC
0-lOO(Vee =3.3±0.3V)
ns/v
0- 20(Vee= 5 ±0.5V)
CHARACTERISTICS
r---
Ta=25OC
Ta=-40-85OC
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
5.5 3.85
3.85
2.0
0.50
0.50
V
3.0
0.90
0.90
5.5
1. 65
1. 65
2.0
1.9
2.0
1.9
3.0
loH=-50J,tA
3.0
2.9
2.9
4.4
4.5
4.4
4.5
V
3.0 2.58
2.48
Irn=-4mA
3.80
Irn=-24mA 4.5 3.94
3.85
Irn=-75mA* 5.5
2.0
0.0
O. 1
0.1
IOL=50J,tA
3.0
0.0
0.1
O. I
0.0
0.1
4.5
0.1
V
3.0
0.44
0.36
IOL=12mA
0.36
0.44
4.5
IOL=24mA
5.5
1. 65
IOl,=75mA*
PARAMETER
SYMBOL
TEST CONDITION
High-Level
Input Voltage
V IH
Low-Level
Input Voltage
V IL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
VOL
3-State Output
orr-State Current
ICE
VIN=VUi or VIL
Voor=Vee or GND
5.5
Input Leakage Current
Quiescent Supply Current
I I:1i
lee
VIN=Veeor GND
VI:II=Vee or GND
5.5
5.5
VIN =
V IH or VIL
VIN=
VIH or VIL
-
-
±0.5
-
±5.0
-
-
±O.l
8.0
-
±I.O
80.0
-
-
-
IJ.A
• :This spec indicates the capability of driving 50(l transmission lines.
One output should be tested at a time for a lOms maximum duration.
TOSHI-.A CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-280
TC74AC564P I FI FW, TC74AC574P I FI FW
IEC LOGIC SYMBOL
TC74AC564
TC74AC574
OE
CK
00
00
01
as
01
02
03
04
05
00
01
02
03
04
05
Cis
D6
as
07
07
02
03
04
07
SYSTEM DIAGRAM
TC74AC574
TC74AC564
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T O S H I B A CORPORATION
AC-281
TC74AC564P I FI FW, TC74AC574P I FI FW
TIMING REQUIREMENTS(lnput t r =tf=3ns)
PARAMETER
SYMBOL TEST CONDITION
Vee
Ta=2S"C
TYP.
LIMIT
Ta=-40-85"C
LIMIT
Minimum Pulse Width
(CK)
tW(H)
tW(L)
3.3±0.3
S.O±O.S
-
-
7.0
5.0
7.0
5.0
*
Minimum Set-up Time
ts
3.3±0.3
S.O±O.S
-
10.0
5.5
10.0
5.5
**
Minimum Set-up Time
ts
3.3±0.3
S.O±O.S
-
9.0
4.5
9.0
4.5
Minimum Hold Time
th
3.3±0.3
S.O±O.S
-
1.0
1.0
1.0
1.0
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L=50pF. RL =5000. Input-t r =tf=3ns)
Ta-2S"C
Ta- 40 -8S"C
UNIT
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX. MIN. ·MAX.
Vex
Propagation Delay Time
(CK-Q. Q)
t pLH
tpHL
3.3±0.3
S.O±O.S
Output Enab1e-Time
t pLH
tpHL
3.3±0.3
S.O±O.S
Output Disable Time
tpZL
tpZH
fMAX
Maximum Clock Frequency
-
9.8
6.1
16.7
9.2
1.0
1.0
19.0
10. S
-
9.2
6.1
lS.8
9.3
1.0
1.0
18.0
10.6
3.3±0.3
S.O±O.S
-
6.6
5.8
11. 0
8.8
1.0
1.0
12.5
10.0
3.3±0.3
S.O±O.S
50
95
100
160
-
50
95
-
-
-
ns
MHz
Input Capacitance
CI;-\
5
10
10
pF
Output Capacitance
Coor
10
Power Dissipation Capacitance CPDW
36
Note (!) C FD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lex q,o=C PO • Va::. f IN + I a:: IS( per Latch)
And the total Cpo when n pes. of Latch operate can be gained by the following equation:
Cpo (total)=26+10· n
* :for TC74AC564 Only.
*:for TC74AC574 Only.
-
*
no.HIRA CO~AT10N------------------------------------------------------------
AC-282
TC74ACT564 PI F/FVV, TC74ACT574P/F/FVV
OCTAL D-TVPE FLIP-FLOP WITH 3-STATE OUTPUT
TC74ACT564P/F/FW INVERTING
TC74ACT574P/F/FW NON-INVERTING
The TC74ACT564 and TC74ACT574 are advanced high
speed CMOS OCT AL FLIP-FLOP with 3-STATE
OUTPUT fabricated with silicon gate and double-layer
metal wiring C2MOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These devices may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
These 8-bit D-type flip-flops are controlled by a clock
input (CK) and an output enable input (OE).
When the OE input is high, the eight outputs are in a
high impedance state.
The TC74ACT564 has inverting outputs, and TC74ACT
574 has non-inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. f MAX =180MHz(ty,p.) at Vcc=5V
• Low Power Dissipation ............... Icc=8IlA(Max.) at Ta=25"C
• Compatible with TTL outputs ...•.. V1L 9l.8V(Max.)
'lJ1i=2V(Min.)
• Symmetrical Output Impedance ···1 1m 1=101. =24mA(Min.)
Capability of driving 50 Q
transmission lines.
• Balanced Propagation Delays ...... tpl.li '=; tpHL
• Pin and Function Compatible with 74F 564/574
TRUTH TABLE
P( DIP20-P-300A)
2~ 20~
1
1
F(SOP20-P-300)
FW(SOL20-P-300)
PIN ASSIGNMENT (TOP VIEW)
TC74ACT664
OE
DO 2
01
02
03
04
05
06
07
3
4
5
6
7
8
9
GNO 10
20
19
18
17
16
15
14
13
12
11
Vee
20
19
18
17
16
15
14
13
12
11
Vee
00
01
02
03
04
05
06
07
CK
TC74ACT574
OE
INPUTS
OE
CK
H
X
L
L
L
L
S
I
OUTPUTS
0
X
X
Q(674)
00
01
02
03
04
05
06
07
0(684)
Z
Z
Qn
Qn
L
L
H
H
H
L
x : Don't Care
Z .2...tIigh Impedance
On(On) : No Change
GNO
2
3
4
5
6
7
8
9
10
00
01
02
03
04
05
06
07
CK
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOSHIBA CORPORATION
AC-283
TC74ACT564P IFIFW, TC74ACT574PIFIFW
IEC LOGIC SYMBOL
TC74ACT564
TC74ACT574
OE
CK
DO
01
02
03
D4
05
06
07
QO
Ql
Q2
Q3
Q4
as
Q6
Q7
SYSTEM DIAGRAM
TC74ACT574
TC74ACT564
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - -
AC-284
TC7 4ACT564P IF IFW, TC74ACT574PIF IFW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipatio~n
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI:,\
VOl,T
11K
101(
IOl,T
lee
Po
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
·C
·C
VALUE
-0.5 -6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±200
500(DIP) ",/l80(SOP)
-65 -150
300
"'500mW in the range of Ta=
-40·C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C should be applied
up to300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vee
Input Voltage
VI:,\
Output Voltage
VOl,T
Operating Temperature
Topr
Input Rise and Fall Time dt/dv
DC
ELECTRICAL
VALUE
4.5-5.5
0- Vee
0- Vee
-40"'" 85
0'7" 10
UNIT
V
V
V
"C
ns/v
CHARACTERISTICS
r----
TEST CONDITION
PARAMETER
SYMBOL
High-Level
Input Voltage
\1H
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vrn
\1:'\=
VIHor VIL
Low-Level
Output Voltage
Va.
Vi:'\=
VIHor VIL
3-State Output
Off-State Current
Iaz
V(:,\=VIH or VIL
Va.T=Vee orGND
Input Leakage Current
11:,\
lee
Quiescent Supply Current
.6.I cc
Ta=25"C
Vee MIN. TYP. MAX.
4.5
2.0
1
5.5
4.5
0.8
1
5.5
4.5 4.4
4.5
4.5 3.94
5.5
4.5
0.0
0.1
4.5
0.36
5.5
-
100=-50 J,t A
loo=-24mA
loo=-75mA.
Ia.=50J,tA
Ia.=24mA
IOl,=75mA.
VI:,\ =Vee or GND
VI:,\ =Vcc or GND
PER INPUT:VI:,\ -3.4V
OTHER INPUT:Vee or GND
5.5
5.5
5.5
5.5
-
-
-
--
-
-
-
-
±0.5
±O.l
8.0
1. 35
Ta=-40-85"C
MIN. MAX.
~U'NIT
2.0
-
V
-
0.8
V
4.4
3.80
3.85
--
V
-
0.1
0.44
1. 65
V
--
-
±5.0
±1.0
80.0
1.5
J,tA
rnA
.:This spec indicates the capability oC driving SOO transmission lines.
One output should be tested at a time Cor a IOms maximum duration.
------------------------------------------------------------TQSHIBA CORPORATION
AC-285
TC74ACT564P/F/FVV, TC74ACT574P/F/FVV
TIMING REQUIREMENTS(lnput tr=t,=3ns)
PARAMETER
SYMBOL TEST CONDITION
twCH)
Vcr;
Ta-25"C
TYP.
LIMIT.
Ta--40 -85"C UNIT
LIMIT.
Minimum Pulse Width
(OK)
two.)
5.0±O.5
-
5
5
Minimum Set-up Time
t.
5.0±0.5
-
3
3
Minimum Hold Time
til
5.0±O.5
-
2
2
ns
AC ELECTRICAL CHARACTERISTICS(C L=60pF, RL =6000, Input t r=t,=3ns)
PARAMETER
SYMBOL TEST CONDITION
Ta
Ta=25"C
40·85"0
Vcr;
MIN.
TYP.
MAX.
MIN.
MAX.
Propagation Delay Time
(CK-Q,Q)
tpLH
tpHL
5.0±O.5
-
6.2
10.1
1.0
11.5
Output Enable Time
tPlJ,.
tl0i
5.0±0.5
-
6.3
10.5
1.0
12.0
Output Disable Time
tplZ
tJJI-Q:
5.0±0.5
-
6.6
9.6
1.0
11. 0
Maximum Clock Frequency
fMAX
5.0±O.5
85
160
-
85
-
-
UNIT
ns
MHz
Input Capacitance
l,;/N
5
10
10
pF
Output Capacitance
Coor
10
Power Dissipalion Capacitance Cpom
33
NoteUl Cro is defined as the value of the internal equivalent capacitance which IS calculated Crom the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icr;Q>Il=C po. Va:. f IN +1 a: 18(per F/F)
And the total Cpo when n pcs. or F/F operate can be gained by the rollowingequation:
Cpo (total)=21+12· n
-
TDSHIBA CORPORATION
-
----------------------------~
AC-286
TC74AC620P/F/RN, TC74AC623P/F/RN
OCTAL BUS TRANSCEIVER
TC74AC620P/F/FW
3-STATE.INVERTING
TC74AC623P/F/FW
3-STATE.NON-INVERTING
The TC74AC620 and 623 are advanced high speed CMOS
OCTAL BUS TRANSCEIVERs fabricated with silicon
gate and double-layer metal wiring C 2MOS technology.
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
These IC's are intended for two-way asynchronous
communication between data buses,and direction of data
transmission is determined by GAB, GBA. GAB and
GBA inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP20-P-300A)
~~~~
1
F(SOP20-P-300)
1
FW(SOL20-P-300)
APPLICATION NOTES
FEATURES:
• High Speed ..............•.....•............ tlXl=3.9ns (typ.) at Vcc=SV
• Low Power Dissipation ............... Icc=8IlA(Max.) at Ta=2S"C
• High Noise Immunity·· .... · ........ VNIH=Vt'o-rt>--- ~
SIA
o----i>ort>-- ~
L£>o-t>o- • A
L£>o-t>o- ••
....,.-ac::J---~~1-o1t
iL._. ----.. . . .--------
A. o-r=.
I
I
iAM~ AS
ABOY..:E:.-_.=:.30 ••
Nota: In ca.. of TC74AC.... output InVlnar markad • at A bu. and • bu. an .lImlnatad.
TOIIHIBA COAJIOAATlON - - - - - - - - - - - - - - - - - - - - - - - - - -_ _
AC-292
TC74AC646p, TC74AC648P
TIMING REQUIREMENTS(lnput tr=t,=3na)
PARAMETER
SYMBOL TEST
CONDITION
'1'a-25"(
LIMIT
'1'Yt'.
va;
Ta= 40 -85"C UNIT
. LIMIT
3.3±O.3
5.0±O.5
-
7.0
5.0
7.0
5.0
t,
3. 3±O. 3
5. O±O. 5
--
5.0
3.0
5.0
3.0
tb
3. 3±O. 3
5.0±0.5
-
2.0
2.0
2.0
2.0
Minimum Pulse Width
(CLOCK)
tw(L)
Minimum Set-up Time
Minimum Hold Time
tw(H)
ns
AC ELECT.RICAL CHARACTERISTICS(CL=&OpF,RL=&OOQ,lnput t r =tf=3na)
I TEST
CONDITION
PARAMETER
SYMBOL
Propagation Delay Time
(BUS-BUS) •
tpLH
~
3.3±0.3
.5.0±0.5
Propagation Delay Time
(CAB,CBA-BUS) •
tpLH
tp.n.
3.3±0.3
5. O±O. 5
Propagation Delay Time
(SAB,SBA-BUS) •
tpLH
tp.n.
3. 3±0. 3
5. O±O. 5
Propagation Delay Time
(BUS-BUS) ••
tpLH
3. 3±0. 3
5.0±0.5
Propagation Delay Time
(CAB,CBA-BUS) ••
tpLH
tp.n.
3.a±0.3
5. O±O. 5
Propagation Delay Time
(SAB,SBA-BUS) ••
tpLH
tp.n.
OutpU.lEnable time
(O,DIR-BUS)
Va;
MIN.
-
Ta- 40 -85"C
Ta=25"C
TYP. MAX. MIN; ; MAX. UNIT
9.2
6.0
14.9
8.7
1.0
1.0
17.0
10.0
11.3
7.5
19.3
11.4
l.O
1.0
22. 0
13.0
10.4
6.9
17.5
10.5
1.0
1.0
20.0
12. 0
8.4
5.8
14.0
8.7
1.0
1.0
16.0
10.0
-
10.8
6.9
18.4
10.5
1.0
1.0
21.0
12.0
3. 3±0. 3
5. O±O. 5
-
10.1
6.4
16.7
10.1
1.0
1.0
19.0
11.5
tl1/1.
~
3. 3±0. 3
5. O±O. 5
-
10.5
6.7
17.5
10.5
1.0
1.0
20.0
12.0
Output Disable time
(o,DIR-BUS)
:su
3. 3±0. 3
5.0±0.5
--
8.5
6.8
14.0
9.6
1.0
1.0
16.0
11. 0
Maximum Cicek FrequlIlcy
fMAX
3.3±0.3
5.0±0.5
55
75
55
75
--
tp.a.
pHZ
-
-
85
130
5
-
-
-
-
-
-
ns
MHz
Input Capacitance
CIN
10
10
\jour
OutDut Capacitance
13
pF
CPO
Power Dissipation Capacitance
Note(AC646)
21
CPO
NoteC AC648)
Power DissiDatioD CaDacitance
19
Note (1) CPO is deCined as the value of the internal equivalent capacitance which is calculated trom the
operating current consumption without load.
Average operating curent can be obtained by the equation:
I~= Cpo. Vex. tIN + Ia; 18(per.bit)
.:for TC74AC646 only
.. :ror TC74AC648 only
-
-
-----------------------------------------------------~aHlaACORPORATHON
AC-293
TC74AC646p, TC74AC648P
TRUTH TABLE
TC74AC.... (Th. truth tabl. for TC74ACM8 I. the ..m•• but with the output. Inv.rt.d)
G DIR CAB CBA SAB SBA
H
X
X
X
X
X
I
I
X
X
A
B
Function
INPUTS INPUTS Thl output function. of A and B Bu ....
ar. di.ablld.
Z
Z
X
Both A and B Bu.... Ir. u..d I I Inputa to the
Int.rnal flip-flop •• Data on the Bu. will b•
• tor.d on tli. rl.lng Idg. of the Clock.
X
INPUTS OUTPUTS
L
H
L
H
L
H
Th. data on thl A bu. arl dl.play.d on the B
bu••
X
L
H
L
H
Th. dlta on thl A Bu. arl dl.play.d on the B
Bu •• and Ir••torld Into the A .torag. flip-flop.
on the rl.lng .dg. of CA.B.
H
X
X
Qn
Th. dlta In the A .torag. fIlp-flop. Irl dl.pllyld on
thl B Bua.
H
X
L
H
L
H
Thl data on thl A Bu. Ira .torld Into thl A .toragl
flip-flopa on thl riaing edg. of CAB. Ind the .torld
dlta propagltl directly onto thl B Bu••
X
X·
L
X
I
X·
L
X
X·
I
X·
OUTPUTS INPUTS
L
L
L
H
L
H
Th. data on the B bu. art dl.play.d on thl A
bu••
L
L
H
L
H
Thl data on the B Bu. art dlapllYld on thl A
Bu •• and Ir••lorld Into thl B .toragl flip-flop.
on thl rl.lng Idg. of CBA.
X
H
Qn
X
Thl dlta In thl I .toragl flip-flopa art dl.pllyed on
the A BUI.
X
H
L
H
L
H
Thl dlta on thl B Bu. Irt Itorld Into thl B ltoragl
flip-fiopi on thl riling Idgl of CIA. Ind the Itorld
data proPltlatl directly onto the A BUI.
X·
X
X
L
X·
I
X
X·
X
X·
I
Not..: X: Don't Car.
Qn: Thl data .torld Into thl Intlrnal flip-flop. by mOlt reclnt low to high trln.ltlon of thl
cloak Inputa.
.
Z: High Impedanal
• Th. clock. Irl not Intlrnilly gltld with lithlr'O or DIR. Thlrfo,.. dlta on thl A Indlor
B Bu.... mlY bl clocked Into thl .toragl flip-flop. at Iny tim ••
~IBA CDAPO~~~~~------------------------------------------------------
AC-294
TC74AC646p, TC74AC648P
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Volta&'e Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vcc/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
300
UNIT
V
V
V
mA
mA
mA
mA
mW
'C
'C
VALUE
2.0-5.5
0- Vex:
0- Vex:
-40"" 85
UNIT
V
V
V
'C
VALUE
-0.5-8.0
-0.5 -Vcc+0.5
-0.5 -Vcc+0.5
±20
±50
±50
±200
500(DIP)./ISO(SOP)
-85 -150
SYMBOL
Vex:
VIN
Varr
11K
.lex
ICLT
Icc '
PD
Tete
Ti.
*500mW in the l'anse of Ta-40"C- 85"C. From Ta"85"C
to 85"C a daratine factor of
-lOmW/"C .hould be applied
upto3QOmW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output VOltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vex:
VIN
Varr
Topr
0-1OO(Vcc ==3.3±O.3V)
0- 2O(Vex:== 5 ±O.5V)
dt/dv
ns/v
DC ELECTRICAL CHARACTERISTICS
Ta-25'C
Vex: MIN. TYP. MAX.
2.0 1.50
3.0 2.10
5.5 3.85
2.0
0.50
3.0
- 0.90
5.5
1.85
2.0 1.9
2.0
bi~-50JtA
3.0 2.9 ' 3.0
VIN4.5 .4.4
4.5
3.0
2.58
bt--4mA
VDi or VIL
!Qi--24mA 4.5 3.94
1Qi--75mA* 5.5
2.0
0.0
0.1
0.0
0.1
3.0
Ia.=50JtA
VIN4.5
0.0
0.1
0.38
3.0
VIH or VIL !a,.-12mA
0.38
4.5
!ci:-24mA
I(i=75mA* 5.5
VIN-VIH or VIL
±0.5
5.5
VOIJI'=VCC or GND
5.5
±0.1
VIN-Vex:or GND
VIN-V ex: or GND
5.5
S.O
~
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Low-Level
Output Voltage
3-State Output
Off-State Current
Input Leakage Current
QUiesclDt Supply CurreDt .
Vat
Va.
ICE
..
lIN
Ice
TEST CONDITION
--
---
.
.
--
--
-
--
-
-
-
-
--
--
--
-
Ta--40-S5'C
MIN. MAX.
1.50
.2.10
3.S5
0.50
0.90
1. 85
1.9
2.9
4.4
2.4S
3. SO
3.85
0.1
0.1
0.1
0.44
0.44
. 1. 85
--
--
--
--
--
lJ'NIT
V
V
V
-
--
V
-
--
±5.0
±1.0
SO. 0
itA
• :Thls spec mdlcates tile capabIlity of driving 500 tranb.nISSIOnlme8 .
One outnut should be tested at a time for a IOms maximum duration.
-----------------------------------------------------~SHIBACaAPOAA~
AC-295
TC74ACT646p, TC74ACT648P
OCTAL BUS TRANSCEIVER/REGISTER
TC74ACT848P
NON-INVERTING
TC74ACT848P
INVERTING
The TC74ACT646/ ACT648 are advanced high speed CMOS
OCTAL BUS TRANSCEIVER/REGISTERs fabricated
with silicon gate and dovble-Iayer metal wiring C2MOS
technology .
They achieve the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
Their inputs are compatible with TTL, NMOS, and
CMOS output voltage levels.
These devices are bus transceivers with 8-state outputs,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
internal registers.
The TC74ACT646 is a non-inverting output type while
the TC74ACT648 is of the inverting output type.
All inputs are equipped with protection circuits against
static dischage or transient excess voltage.
FEATURES:
• High Speed .............................. £MAX=l60MHz(Typ.)at Vo:=5V
• Low Power Dissipation ............ Icx:=8IlA(Max.)at Ta=25"C
• Compatible with TTL Output ......... VIH =2V(Min.)V IL =O.8V(Max.)
• Symmetrical Output Impedance '''1 Iail =101. =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpUi" tpHl.
• Pin and Function Compatible with 74LS646/648
P(DIP24-P~300)
PIN ASSIGNMENT
CAl 1
24 Vee
SAl 2
DIR 3
A1 4
AZ I
A3 I
A4 7
. 23 CIA
22 alA
21 G
ZO 11
,.12
18 13
17 14
AI 8
AI I
A7 10
,.
..
1185
1417
13 ..
A8 "
GND 12
(TOP VIEW)
IEC LOGIC SYMBOL
TC74ACT841
APPLICATION NOTES
TC74ACT848
1) Do not apply a signal to any
bus terminal when it is in the out
put mode. Damage may result.
2) All floating (high impedance)
bus terminals must have their
input levels fixed by means of pull
up or pull down resistors or bus
terminator IC's such as the
TOSHIBA TC40117BP.
TaIlHIIIA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-296
TC74ACT646p, TC74ACT648P
TIMING REQUIREMENTS(lnput tr=t,=3n.)
PARAMETER
SYMBOL TEST CONDITION
Ta=25"C
LIMn'
TYP.
Vcr;
'1'a--40 -85"C UNIT
LIMn'
Minimum Pulse Width
(CLOCK)
twCL)
tW(H)
5.0±0.5
-
5
5
Minimum Set-up Time
t.
5.0±0.5
-
3
3
Minimum Hold Time
th
5.0±0.5
-
2
2
n.
AC ELECTRIcAL CHARACTERISTICS(CL=60pF.RL =6000.lnput t r =t,=3ns}
PARAMETER
SYMBOL
Propagation Delay Time
(BUS-BUS)
Propagation Delay Time
(CAB, CBA-BUS)
Propagation Delay Time
(SAB, SBA-BUS)
Output Enable time
(DIR, G-BUS)
Output Enable time
(DIR, G-'BUS)
:Maximum Clock Frequency
I
TEST
CONDITION
Ta=25,(
I Ta=-40 -85"C
TYP. MAX. MIN. MAX. UNIT
Va;
MIN.
tlliJi
tpHL
5.0±0.5
-
6.0
9.7
1.0
11.0
tlliJi
tpHL
.5.0±0.5
-
6.9
11.8
1.0
13.5
t\lLH
tpHL
tlilJ,.
tp'ZH
5.0±0.5
-
6.7
11.0
1.0
12. 5
5. O±O. 5
-
7.1
11.4
1.0
13.0
tpLZ
tpKl;
5. O±O. 5
-
6.9
9.7
1.0
11. 0
CMAX
5.0±0.5
75
145
-
75
-
---
--
.--
Input CapacItance
Uutput CapacItance
n.
MHz
CIN DlR, G, SAB SBA CAB CBA
5
10
10
COOl' An Bn
13
pF
20
Power Dissipaliou CapacitlDcI CR>(l) TC74ACT646
TC74ACT648
19
Note (U Cpo ie defined u the value of the internal equivalent capacitance which ie calculated from th
-
-
-
eoperatin, current consumption without load.
Avera,. operatin, CUrrent caD be obtained by the equation:
I cx:~CPD • Vee. fIN +Iee 18(per bit)
-----------------------------------------------------~HIBACORPO~ION
AC-297
TC74ACT646p, TC74ACT648P
TIMING CHART
TC74ACT841
G
DIR
II.I ---~
III.
CAl - - - - '
I
I-
A : Output
I : Input
A : Input
I : Output
• I
Z
Z : High Imped__
: Don', care
No..: Th_ timing c:h.rt for TC74ACT848 I, the ,.m•• but with the output. InHrted,
SYSTEM DIAGRAM
TC74ACTl48
CAI~-C>-~----------~
CIA~~~~~>--------~--~--~
II.I
o--(>o-rl>o--- ~
IIA
o--J>o-rt>-- ~
Y>-t>--+A
I...{>o-t>o- +.
~-<:~----+-~
i~. ____ .____~~~~l----~
or·
I
AI
Not.: In
C8H
----SAM.E AS ABOYE_ _ _
It
.=:30 II
of TC74ACT848 output InHrter m.rk.d ••t Abu, .nd • bu••,. .lImln.t.d.
TCMaHIBAC~RATIDN---------------------------------------------------------
AC·298
TC74ACT646p, TC74ACT648P
TRUTH TABLE
TC74ACT848(The truth tlble for TC74ACT848 I. the •• me, but with the output. Invert.d)
G
DIR CAB CBA SAB SBA
X·
H
X·
A
B
Function
INPUTS INPUTS
X
X
X
I
I
X
X
X·
X·
L
X
Z
Z
X
X
The output funclon. of A .nd B Bu .... ere
dl •• bled.
Both A .nd B Bu ..... r. u..d •• Input. to the
Intern.1 flip.-flop •• D.tI on the Bu. will be
.tored on the rl.lng edge of the Clock.
INPUTS OUTPUTS
L
H
L
H
L
H
The d.t. on the A but .re dl.pllyed on the B
but
I
X·
L
X
H
L
H
The d.t. on the A BUI ere dltpl.yed on the B
BUI, .nd ere Itored Into the A .tor.ge fIIp-fiopl
on the riling edge of CAB.
i(
~
H
X
X
On
The dltl In the A Itor.g. fIIp-flopl Ir.
dilpl.yed on the B But.
I
x·
H
X
L
H
L
H
X'
X·
X
L
X- I
X
X'
L
The d.te on the A Bu•• re .tored Into the A .tor.ge
flip-flopi on the rl.lng edge 01 CAB, .nd the .tored
d.te propag.te directly onto the B Bu••
OUTPUTS INPUTS
L
L
X
X' I
Not.. :
L
H
L
H
The d.tI on the B bUI ere dl.pllyad on the A
bu••
L
L
H
L
H
Tha dltl on the B BUI Ir. dlapllyed on the A
BUI, Ind Ir. Itor.d Into the B .torlg. fIIp-fiopl
on the rl.lng edge of CBA.
X
H
On
X
The dltl In the B .torlg. flip-fiopi .re
dl.pl.ved on the A BUI.
X
H
L
L
H
H
The d.tI on the B BUI .re Itored Into the B .tor.g.
flip-flop. on the rI.lng edg. of CIA, .nd the .tored
date propag.t, directly onto the A Bu••
X: Don't C.re
On: The dltl Itorad Into the internal flip-flop. by mo.t rec.nt low to high trlnlltlon of
the clock Inputl
Z: High Imp.dlnce
• The clock Ire not Internally gated with either G or DIR. Therfore, dati on the A .nd
lor B Bu .... m.y b. clocked Into the .tor.ge flip-flopt It Iny tim ••
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T O B H I B A CORPORATION
AC-299
TC74ACT646p, TC74ACT648P
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC V(X/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
V(X
VIN
Vour
11K
ICl(
lour
lee
Po
Tat&'
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
VALUE
-0.5-6.0
-0.5 -V(X+0.5
-0.5 -V(X+0.5
±20
±50
±50
±2OO
500(DIP)*/180(SOP)
-65 -150
300
*500mW in the ran,. of Ta-40"C- 65"C. From Ta-8S"C
to 85"C a derating factor of
-lOmW/"Cahould be applied
upto300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VIN
Vror
Topr
dtldv
UNIT
V
V
V
"C
na/v
VALUE
4.5-5.5
O-Vee
O-Vee
-40 - 85
0-10
DC ,ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VII..
High-Level
Output Voltage
Vat
Low-Level
Output Voltage
Va.
3-State Output
Off-State Current
Iaz;
IDput Leakage CurreDt
lIN
I(X
QuiesceDt Supply CurreDt
t.Icc
r--
Ta=25"C
Vee MIN. TYP. MAX.
4.5
2.0
l
5.5
4.5
.,.
0.8
I
5.5
4.5
1ai=-50uA 4.5 4.4
1ai=-24mA 4.5 3.94
1ai=-75mA* 5.5
0.0
Ia..=50JiA
4.5
0.1
Ia.=24mA
4.5
0.38
IQ.=75mA* 5.5
TEST CONDITION
-
-
-
VIN=
VDior ViL
ViN=
VDiOrV1I..
-
--
VIN -VJH orVIL
Vror -Vee orOND
VIN =Vee or GND
VIN =Vee or GND
PER INPUT:Vee=3. 4V
OTHER INPUT:Vee or GND
--
-
-
-'
V
-
0.8
V
4.4
3.80
3.85
-
V
0.1
0.44
1.65
V
--
-
-
5.5
5.5
5.5
1. 35
-
2.0
--
- - ±0.5
- - ±0.1
8.0
5.5
Ta=-40-85"C
UNIT
MIN. MAX.
±5.0
±1.0
80.0
1.5
p,A
mA
* :1'IU8 SJlE"C' mdlcates t.he capability of driving 50n tnUlsmission lines.
Om~
output shOUld be
rf'stl~d
at a timE." for a 10018 maximum duration.
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-300
TC74AC670P/F/FN
TC14AC610P/F/FN
4-WORDx4-BIT
REGISTER
The TC74AC670 is an advanced high speed 4-WORDx4BIT REGISTER FILE Cabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieve the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The register file is organized as 4 words oC 4 bits· each
and separate on -chip decoding is provided Cor addressing
the four word locations to either write-in or retrieve data.
This permits simultaneous writing into one location and
reading from another word location.
Four data inputs are available which are used to supply
bit word to be stored. Location of the word is detennined by the A
and B inputs. When the WRITE-ENABLE input is high, the data
inputs are inhibited and their levels can cause no change in the
. information stored in the internal latches. When the READENABLE input is high, the data outputs are inhibited and go into
the high-impedance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tJXI=6.7ns(typ.)at Vee=5V
• Low Power Dissipation ............ Iee =8IlA(Max.)at Ta=25"C
• High Noise Immunity··············· VNIH =VNIL 28% Vee (Min.)
• Symmetrical Output Impedance •.. I Ia; I =IOL. =24mA(Min.)
Capability of driving 50Q
transmission lines.
• Balanced Propagation Delays ...... tpLH "" tpHL
• Wide Operating Voltage Range ... Vee (opr)=2V -5.5V
• Pin and Function Compatible with 74HC670
FILE (3-STATE)
1
P(OIP16-P-300A)
1.~1.~
F(SOP16-P-300)
FN(S0L16-P-150)
PIN ASSIGNMENT
02 1
16 V
03 2
15 01
04 3
14 WA
RB 4
13 WB
RA 5
12 WRITE
Q4 6
11 linD
Q3 7
10 Ql
9 Q2
mm
mm
GNO 8
(TOP VIEW)
IEC LOGIC SYMBOL
RAM4x4
WA
WB
RA
RB
WE
RE
01
02
03
04
O}
lA.D.
1
3
O}
1
2A.D.
3
C4 [WRITE)
EN [READ)
~!E:::M~oooITi 01
02
--------------------------------TaBHIBA
AC-301
03
04
CORPORATION
TC74AC670P/F/FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
Your
11K
10K
IOL'T
lee
PD
Tstg
TL
VALUE
-0.5-6.0
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±50
±50
±100
500(D1P) */180(SOP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
VALUE
2,ti-5.5
o -Vee
0- Vee
-40 - 85
SYMBOL
Vee
VIN
Your
Topr
dt/dv
UNIT
V
V
V
"C
0-100(Vee =3.3±0.3V)
ns/v
0- 20(Vee= 5 ±0.5V)
CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
Viii
Low-Level
Input Voltage
V IL
High-Level
Output Voltage
TEST CONDITION
YiN=
Vm
VIHor VIL
VIN=
Im=-50ttA
1rn=-4mA
Irn=-24mA
IOF-75mA*
I(L =50ttA
Ta=-40-85"C
Ta=25"C
Vee MIN. TYP. MAX. MIN. MAX. UNIT
2.0 1. 50
1. 50
V
3.0 2.10
2.10
5.5 3.85
3.85
2.0
0.50
0.50
V
3.0
0.90
0.90
5.5
1. 65
1. 65
2.0
1.9
2.0
1.9
3.0
2.9
3.0
2.9
4.4
4.5
4.4
4.5
V
3.0 2.58
2.48
4.5 3.94
3.80
5.5
3.85
2.0
0.0
O. I
0.1
3.0
0.1
0.0
0.1
0.0
0.1
4.5
0.1
V
3.0
0.36
0.44
4.5
0.36
0.44
5.5
1. 65
Low-Level
Output Voltage
VeL
3-State Output
Off -State Current
I(E
VIN=VIH or VIL
Vour=Vee orGND
5.5
-
-
±0.5
Input Leakage Current
Quiescent Supply Current
liN
lee
VIN =Vee or GND
VIN =Vee or GND
5.5
5.5
-
-
-
-
±0.1
8.0
VIHor VIL
1(L=12mA
Ia.=24mA
I(L=75mA*
-
±0.5
±1.0
80.0
tt A
• :This spec indicates the capability of driving 500 transmission lines.
One output should be tested at a time for a lOms maximum duration.
TCMSHI~ca~~~--------------------------------------------------------~--
AC-302
TC74AC670P I FI FN
TRUTH
TABLE
READ FUNCTION TABLE
WRITE FUNCTION TABLE
WORDS
WRITE INPUTS
READ INPUTS
OUTPUTS
WB
WA
WE
0
1
2
3
RB
RA
RE
01
02
03
04
L
L
L
O=D
00
00
00
L
L
L
WOBl
WOB2
WOB3
WOB4
W1B4
L
H
L
00
O=D
00
00
L
H
L
W1Bl
W1B2
W1B3
H
L
L
00
00
O=D
00
H
L
L
W2Bl
W2B2
W2B3
W2B4
H
H
L
00
00
00
O=D
H
H
L
W3Bl
W3B2
W3B3
W3B4
X
X
H
00
00
00
00
X
X
H
Z
Z
Z
Z
NOTES l.X:DON'T CARE Z:HIGH IMPEDANCE
2.(O=D)=THE FOUR SELECTED
INTERNAL FLIP-FLOP OUTPUTS WILL ASSUME
THE STATES APPLIED TO THE FOUR EXTERNAL DATA INPUTS.
3.00=THE LEVEL OF 0 BEFORE THE INDICATED INPUT CONDITIONS WERE ESTABLISHED.
4.WOB1=THE FIRST BIT OF WORD O,etc.
BLOCK
DIAGRAM
WRITE
READ
ENABLE
ENABLE
LATCH
DATE
IN
ADDRESS
SELECT
DECODER
4-WORD
3-STATE
BUFFER
DATE
OUT
x4-BIT
ADDRESS
(2-BIT)
IN
ADDRESS IN
(2-BIT)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TOSHIIIA CORPORATION
AC-303
iI
I
01
-,
15
(I)
-<
(I)
~
m
~
o
C)
>
10
a
0,
L ___
I
'-+L_ _
02~
f)
w
o
"'"
Same
as
1
=1
03~
Same
as
04~
Same
a s
WA
abo v e
b I
0 C
b I
0 C
b I
.=::rm
k
-
1abo v e
abo v e
WE
k
02
=JTIJ
k
03
0 C
04
RA
RE
:t
Q
.....
I: G>
:lI
i
~
.....
I~
."
-n
-n
::2
TC74AC670P/F/FN
TIMING REQUIREMENTS(lnput t r =t,=3ns)
PARAMETER
SYMBOL TEST CONDITION
Ta-25°C
TYP.
LIMIT
Vee
Minimum Pulse Width
(WE)
tll"lI.)
i3.3~0·~1
5.0:!:0.:J
Minimum Set-up Time
(Dn-WE)
ts
3.3±0.31
5.0±0.5
Minimum Set-up Time
(WA.WB-WE)
ts
I
3.3±0.3
Ta--40 -85°C
UNIT
LIMIT
-
7.0
5.0
7.0
5.0
-
9.0
5.0
9.0
5.0
-
4.5
3.5
4.5
3.5
0.0
0.0
0.0
0.0
5.0~0.5
-
th
3.3±0.3
5.0±0.5
-
Minimum Hold Time
(WA.WB-WE)
th
3.3±0.3
5.0±0.5
-
3.5
1.5
3.5
1.5
Minimum Latch Time
(WE-RA.RB)
tlatch
3.3±0.3
5.0±0.5
-
4.0
3.0
4.0
3.0
Minimum Hold Time
(Dn-WE)
(1
I
I
-
-
ns
t latch IS the time allowed for the mternal output of the latch to assume the state of new data. ThiS IS
important only when attempting to read from a location immediately after that location has receive new
data.
AC ELECTRICAL CHARACTERISTICS(C L =50pF. RL =5000. Input t r =t,=3ns)
Ta--40~85"C
Ta-25°C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vee MIN. TYP. MAX. MIN. MAX.
Note(I):
3.3~0.3
Propagation Delay Time
(RA.RB-Qn)
t pUI
t pHL
5.0±0.5
-
Propagation Delay Time
(WE-Qn)
t pLH
t pHL
3.3±0.3
5.0±0.5
-
Propagation Delay Time
(Dn-Qn)
t pUI
t pilL
3.3±0.3
Output Enable Time
Output Disable Time
5.0~0.5
12.9
8.6
22.3
13.3
1.0
1.0
25.4
15.1
ll.l
7.4
19.0
ll.3
1.0
1.0
21.7
12.9
-
14.7
9.9
25.3
15.3
1.0
1.0
28.8
17.4
ILl
1.0
1.0
12.7
9.5
1.0
1.0
15.0
13.1
I
I
tpZL
3.3~0.3
t
pZIl
5.0±0.5
-
6. B
4.9
t pLZ
tplll
3.3±0.3
5.0±0.5
-
9.0
Input Capacitance
CI\"
Output Capacitance
COLT
Power Dissipation Capacitance CrD(l)
Note (l) C m IS defmed as the value of the mternal eqUivalent
operating current consumption without load.
Average operating current can be obtained by the equation:
Ic.'Ctl'P=C PI)· Va:. fiN +1 a:
B.5
8.3
13.2
1l.5
-
5
10
10
160
capacitance which
ns
-
IS
10
pF
calculated from the
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOSHIBA CORPORATION
AC~305
TC74AC670P/F/FN
SWITCHING
CHARACTERISTICS
TEST WAVEFORM
Vee
50%
WA/WB
GNO
Vee
On
50%
GNO
Vee
50%
WE
GNO
tw(L)
tlateh
Vee
RA/RB
GNO
VOH
an
50%
VOL
Vee
On
50%
50%
GNO
Vee
50%
50%
WE
tpLH
GNO
VOH
an
50%
50%
50%
r
50%
VOL
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - -
AC-306
11.
OUTLINE DRAWINGS
TC74AC/ACT SERIES
DIP 14PIN OUTLINE DRAWING (DIP14-P-300)
Unit in mm
~::::::i] ~IT(~::0/
..!9.25±O.2
Ir---------------~~-:
+,
..,
~
Note) Package width and length do not include mold protrusion.
DIP 16PIN OUTLINE DRAWING (DIP16-P-300A)
Unit in mm
O.9HO.1
Note) Package width and length do not include mold protrusion.
--------------------------------------------------------------TOIIHIBA
AC-309
CORPORATION
DIP 20PIN OUTLINE DRAWING (DIP20-P-300A)
Unit in mm
C::::::::I]{m:;
24.6±O.2
O.81TVP
Note) Package width and length do not include mold protrusion.
DIP 24PIN OUTLINE DRAWING (DIP24-P-300)
O.9lTVP
Unit in mm
O.HO.I~
Note) Package width and length do not include mold protrusion.
TOSHIBA COAlllORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-31 0
SOP l4PIN (200mil BODY) OUTLINE DRAWING (SOP14-P-300)
Unit in mm
1.34TYP
'l~
.A=o~
Note) Package width and length do not include mold protrusion.
SOP l6PIN (200mil BODY) OUTLINE DRAWING (SOP16-P-300)
Unit in mm
IO.3±O.2
~'fL~
"',
.
C>
O.S±O.2
Note) Package width and length do not include mold protrusion.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOSHIIIA CORPORATION
AC-311
SOP 20PIN (200mil BODY) OUTLINE DRAWING (SOP20-P-300)
'"
c
><
frrlnnt:ntDr~ ~
o 0.1
~!
.,;
Unit in mm
_o~
~'tt=
~
O.B±O.Z
Note) Package width and length do not include mold protrusion.
~IBACO~------------------------------------------------------------
AC-312
SOP 14PIN (160mil BODY) OUTLINE DRAWING (SOL14-P-160)
Unit in mm
O.SISTYP
on
r-
.;
Note) Package width and length do not include mold protrusion.
SOP l6PIN (160mil BODY) OUTLINE DRAWING (SOL 16-P-150)
I
I
9.9±0.1
Unit in mm
0-8"
8
O.SOSTVP
~
110.42±O~11$10.2!i/.M)1
~S"
~~l il~
.;
~~
::
;;
0.7±D.3
+I
on
r-
.;
Note) Package width and length do not include mold protrusion.
...
----------------------------------------------------------~
AC-313
~~~~
SOP 20PIN (300mil BODY) OUTLINE DRAWING (SOL20-P-300)
O-BO
12.B±0.1
N
-:=l&
-
~
::E
00
o
+I
M
l"-
o
N N
00.1
Unit in mm
~
+.
4S
II>
O
,IIO.9±0.3
N
o
Note) Package width and length do not include mold protrusion.
~~~----------------------------------------------------------
AC-314
12.
RELIABILITY DATA
TC74AC/ ACT SERIES
Intrinsic Failure Rate Estimation from Life Test Results
Device
2390
60°C Equivalent Device Hours
Ea=0.8V
308.42 x 106
Failure
Failure Rate at 60°C
(Fit)
2
10.1
*60% confidence level.
Reliability Test Results
(1) Long Life Test
Thst
Condition
Device
Hours
1000
Equivalent
Device Hours
@ 60°CEa=0.8eV
Failures
Steady
State
Operation
Th= 125°C
Vcc= 6V
1020
50
2000
0
High Thrnp.
Th= 125°C
Vcc= 6V
880
50
1000
2000
0
0
DC Bias
Th= 150°C
Vcc= 6V
250
1000
High Thrnp.
Storage
Th= 150°C
320
1000
High Thmp.
Humidity
Bias
Th= 85°C
RH= 85%
Vcc= 6V
1590
1000
Low Thrnp.
DC Bias
Th= -30°C
Vcc= 6V
0
106.96 x 106
DIP
201.46
X
106
2*
-
0
0
SOlC
100
1000
680
1000
0
-
0
*ICC Leak
(2) Thermal Environmental Test Results
Thst
Soldering
Heat
Thrnperature
Cycle
Thermal Start
Condition
T sol = 260°C
10 sec. once
- 65°C~25°C~ 150°C~25°C
(30') (5') (30') (5')
+---
100·C(5')
l~--
DIP-14
DIP-l 6
DIP-20
0/22
0/22
0/22
0/100
0/100
0/100
0/22
0/22
0/22
0/22
0/22
0/22
300 cycles
_ O°C
(5')
1 ~-- 30cydes
MIL-STD-883C
Method 1004 10 cycles
+----
Moisture
Resistance
------------------------------TaSHIIIA
AC-317
CORPORATION
(3) MechanicallHt Results
DIP-14
DIP-l6
DIP-20
0122
0122
0122
100-2000- 100Hz, 20G
4 min. 3 orientations
4 times each
0/22
0122
0/22
Mechanical
Shock
1500G, 0.5rns .
4 orientations
3 times each
0/22
0/22
0/22
Constant
Acceleration
20000 G, 6 orientations
1 min. each
0/22
0/22
0/22
Test
Condition
Vibration
Fatigue
60 ± 20Hz, 20G
3 orientation
Variable
Vibration
Freq.
32 Hrs.
(4) Other Test Results
DIP-14
DIP-16
DIP-20
Solderability
T sol = 230·C
5 sec. once
0122
0/22
0/22
Lead
Integrity
Weight = 250g
Bending 3 times
O· -90· _0·
0/22
0/22
0/22
Salt Mist
5% salt atmosphere
35·C, 24 Hrs.
0/22
0/22
0/22
Pressure
Cooker
2.5 atm. 127·C, 100%
100 Hrs.
0/180
0/220
0/60
Test
Condition
(5) Thermal Environmental 'RIst Results (SOle)
Test
Soldering
Heat
Temperature
Cycle
Condition
T sol = 260·C
10 sec. once
- 65·C-25·C- 150·C-25·C
(30') (5') (30') (5')
4-----
l~--+
300 Cycles
• O·C
(5')
(5')
I ~--+ 30cycles
MIL-STD-883C
Method 1004 10
14-PIN
200mil
16-PIN
20-PIN
150mil
14-PIN 16-PIN
300mil
20-PIN
0/22
0/22
0/22
0/22
0/22
0/22
0/50
0/50
0/50
0/50
0/50
0/50
0/22
0/22
0/22
0/22
0122
0/22
0/22
0/22
0/22
0/22
0/22
0122
IOO·C-
Thermal Shock
Moisture
Resistance
---
TCl8HIIIA COIIiUICIIIIATlON - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-318
(6) MechanlcallHt Results (SOle)
'Thst
Condition
200mil
16-PIN
20-PIN
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0122
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
14-PIN
200mil
16-PIN
20-PIN
60 ± 20Hz, 200
3 orientations, 32 Hrs.
100-2000- 100Hz, 200
4 min. 3 orientations
4 times each
Vibration
Fatigue
Variable
Vibration
Freq.
15000, 0.5ms.
4 orientations
3 times each
20000 O. 6 orientations
1 min. each
Mechanical
Shock
Constant
Acceleration
150mil
14-PIN 16-PIN
14-PIN
300mil
20-PIN
(7) Other ~st Results (SOle)
'Thst
Condition
150mil
14-PIN 16-PIN
300mil
20-PIN
Solderability
Tsol = 230°C
5 sec. once
0/22
0/22
0122
0/22
0122
0/22
Lead
Integrity
Weight = 250g
Bending 3 times
0° -90° _0°
0/22
0/22
0/22
0/22
0122
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/80
0/60
0/90
0/60
0/60
0/60
5% salt atmosphere
35°q 25 Hrs.
2.5 atm. 127°q 100%
100 Hrs.
Salt Mist
Pressure
Cooker
(8) Moisture Resistance After Vapor Phase Soldering (V.P.S.)
: Ta =85°C, RH =85% 20 Hrs.
: Ta = 215°C, 1 min x 2 times
: 2.5atm Ta =127"C, RH =100%
1. Treatment
2. v'P.S.
3. Pressure Cooker
Body Size
150mil
200mil
300mil
Device
150
300
100
20Hrs.
0
0
0
50Hrs.
0
0
0
100Hrs.
0
0
0
(9) Moisture Resistance after Solder dipping (200mll SOle)
: Ta =85°C, RH =85% 20 Hrs.
: Ta = 260·C, 10 sec. dip
: 2.5atm Ta =127°C, RH =100%
1. Treatment
2. Dipping
3. Pressure Cooker
Device
300
20HrIl.
50Hrs.
lOOHrs.
o
o
o
-----------------------------TOIIHIIIA
AC-319
COAPOAATION
NOTES
13.
APPLICATION NOTES
TC74ACI ACT SERIES
13-1. SIMULTANEOUS SWITCHING VOLTAGE NOISE-ADVANCED CMOS LOGIC IC'S
By Dennis Benjamin and Hiroji Tsuchihashi
'lbshiba America Electronic Components, Inc.
1. INTRODUCTION
In the early days of bipolar integrated circuits, noise, particularly that noise caused by the voltage generated
by the simultaneous switching of multiple inputs, was not a factor in logic design. In fact, the early, slower, low
output versions of CMOS logic caused little concern in the design community. However, with the advent of the
Advanced CMOS Logic (ACL) and its inherent high output drive current (24mA) and fast edge rates compared
with previous CMOS families, noise generation, particularly that created by simultaneous switching voltage
(ground bounce), becomes a problem. Additionally, these high voltages can cause errant switching of follow-on
devices.
Thshiba Advanced CMOS Logic provides greatly reduced simultaneous switching voltage and, consequently,
reduced noise generation. This reduction was obtained by use of modified pre-buffer and buffer circuits. The
result is a reduction in the gradient (ill) of the Vcc to ground path current.
dt
1-1 Definitions
Ground Bounce. When n-l N channel buffers of a device having n inputs are operated simultaneously, current
flows as shown in fig. 1-1. This current Ci1 +i2 + .... + in - 1) flows through the inductance created by the
leadframe, bondwire, etc. If the n input is held at ground, the output will "bounce" due to this current flow.
Vcc Bounce. A similar action except that the P channel buffers are operated simultaneously and the n input
is held at Vcc .
...... '£T
PIlhFET
~-------~----
........... .
L is mainly lead inductance
di = ~ + i 2 + .... +in-1
Fig. 1-1
----------------------------------------------------~I~ C~~R~
AC-323
TOSHIBA'S SIMULTANEOUS
SWITCHING VOLTAGE
TEST BOARD
.".' .
.
'
.. .....
•
••••• ......
••••
.
'
·
'"
....
..... ...
..·......\--.'.....'.,'"...
.' .'
.'\~:'
'~'.'
.......
•
•
.'.~'.'
TOP METAl
VIEWED FROM MOVE
\.AVER 2
VIEWED FROM ASOVE
\.AVERa
VIEWED FROM MtNE
BOTTOM METAl
VIEWED FROM mow
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-324
2. MEASURING SIMULTANEOUS SWITCHING NOISE
2-1 Test Description
2-1-1 Test Circuit
The test board used by Thshiba is a small, multilayer printed circuit board figs. (2-1,2-2). Fig. 2-3 shows the
connection and test equipment used. All leads are kept as short as possible and the probes are grounded as
close to the device under test (DUT). All resistors and capacitors as well as the DUT are soldered to the board.
Oscilloscope connections are made to the unswitched output as well as to one of the switched outputs. This
allows for timing comparisons. The unswitched input is held at either ground or Vcc depending on the part
type and whether measurement of VOLP or VOHV is being measured. The values of CL and RL are determined by
the test requirements.
HP541100
08CUOSCOPE
IWtI>WIOTH - I GHz
PROBEs: HP5400IA
r-=1i.i4Z--1f·1f·3M
lD:1.11kl.2pF
2
VH-Vac
I
I
BANOWIOTH
1Ifl·0N)
~
7ClOMHz
OUT 18 8OI.DEREO
DIRECTLY TO THE PCB.
PROBE. ARE GROUNDED
MUllHAYER
PC BOARD
.1
M (;lOR: M I'08lIIIII.£
TO OUT.
~~
f
OUT
Fig. 2-3
2-1-2 Output Waveforms
When an input pulse (Thshiba uses a 1 MHz pulse with tr =tf =3ns) is applied to n-l inputs of a device having
n inputs, the nth output is observed on the oscilloscope along with one of the switched outputs (1 to n-l). A
typical waveform is shown in fig. 2-4. Depending on the input level on the nth input and the device type, only
the Vcc or GND waveform will appear in addition to the waveform for the switched output.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOSHIBA CORPORATION
AC-325
PC Board for ACL Switching Measurement
TOP VIEW
BNC Connecter
(lNPUTA)
BNC Connecter
(INPUTB)
C - 47pF (Chip Capacitance)
RI-Sl00
BNC
(Vee)
BOTTOM VIEW
INPUT SIGNAL LINE
TOSHIBA CORPORATION - - - - - - - - - - - - - - - - - - - - - - -
AC-326
As can be seen from the table, VOHV has a larger value on the "L to H" transition than on the "H to L"
transition. VOLP has a larger value on the "H to L" transition than on the "L to H" transition. Fig. 2-5 shows the
reason for this.
VOHV (L to H) is generated by dil and di2 .
dt
dt
VOHV (H to L) is generated by dil .
dt
V
OLP
(H to L) is generated by di3 and di4.
dt
dt
VOLP (L to H) is generated by di3 .
dt
Fig 2-5
2-2-2 Package Type Dependence
In its evaluation of simultaneous switching noise, 'Ibshiba determined that this noise is package type
dependent. 'Ibshiba provides octal devices in both a Dual In-line Package (DIP) and Small Outline Integrated
Circuits (sore)~Upon evaluation of ground bounce test results, it was found that the sore showed a noise level
that was 30% lower than that measured for the DIP. The reason for this is easy to see; because of its size, the
sore has a substantially smaller lead frame with shorter leads. This reduces the lead inductance and the
ground bounce voltage. See fIg. 2-6 for a comparison of DIP to SOIC. Using the industry accepted defacto
standard corner pin configuration, 'Ibshiba can provide sore with very low ground bounce voltage.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TOSHIBA CORPORATION
AC-327
Vee
output from circuits 1, 2.... n-1
GND
Vee
OutpU1 from circuit n
GND
Fig. 2-4
2·2 1Ht Results
2-2-1 Pin Dependence
One of the critical measurements made by Thshiba is switching voltage noise based on which output is held
steady. This is called "pin dependence." Thble 2-1 show pin dependence simultaneous switching noise voltage
for a TC74AC244P.
Switched
Output
PiiIs
5,7,9,12,14,16,18
3,7,9,12,14,16,18
3,5,9,12,14,16,18
3,5,7,12,14,16,18
3,5,7,9,14,16,18
3,5,7,9,12,16,18
3,5,7,9,12,14,18
3,5,7,9,12,14,16
VOHV
Unswitched
Ou!:put
Pm
LtoH
3
5
7
9
12
14
16
18
-1.33
-1.40
-1.33
-1.33
-1.46
-1.43
-1.39
-1.20
VOLP
HtoL
--{l.53
--{l.57
--{l.45
--{l.74
--{l.58
--{l.53
--{l.48
--{l.43
LtoH
HtoL
0.44
0.36
0.31
0.32
0.28
0.34
0.40
0.55
1.18
1.22
1.17
0.80
1.15
1.28
1.28
1.17
Thst Conditions: Vee =5V, tr =tf =3ns, CL =50pF, RL = 500'"
Thble 2-1
"L to H" is the transition of the switched output pins from low (GND) to high (Vee). The P channel FET is
turned on. "H to L" is the transition of the switched output pins from high to low and the N channel FET is
turned on.
TCHIHIBAca~ATWON---------------------------------------------------------
AC-328
The results of'lbshlba's capacitance dependence tests are shown in fig. 2-7. The device tested was a
TC74AC244P. The test was conducted at load capacitances of OpF, 12pF, 50pF, lOOpF and 150pF. A 100pF load
capacitance eCL) will reduce ground bounce voltage when compared to a 50pF capacitance. Thls is due to the
fact that CL acts as a filter.
2·2·4 Vendor Comparisons
In order to provide a complete study of the ground bounce situation, 'lbshlba evaluated several other
manufacturers' ACL. The DUT in all cases was a 74AC244 DIP device. In addition, a 74F244 DIP and a'lbshlba
TC74HC244AP were also tested for comparison. All tests were conducted using 'lbshlba's multilayer test
board. The test configuration in all cases was as described in paragraph 2-1-1 above. The test results are
graphlcally shown in figs. 2-8 and 2-9.
3. Conclusions
Based on the above tests results, it appears that, with good design procedures, 'lbshibas ACL will fulfill the
requirements needed in todays new hlgh speed applications. Careful design of'lbshlba's TC74AC series
ensures the lowest possible ground bounce. By maintaining the standard corner pin configuration, 'lbshlba has
ensured that the customer can continue to design with tools already available.
'lbday, there is a trend toward SOlC. When using 'lbshiba's package, ground bounce can be reduced 30% over
the already very low DIP simultaneous switchlng noise voltage level. For octal bus buffer applications, using a
100pF load capacitance will additionally reduce the ground bounce when compared to a 50pF load
capacitance.
In order to keep noise at the absolute minimum, 'lbshlba recommends that the designer use multilayer PC
boards to reduce Vcc and Ground line inductance and that a O.lILF capacitor be placed between Vcc and
Ground at every device.
-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TOSHIBA CORPORATION
AC·329
OtT. II U
SIMULTANEOUS SWITC.INa NOISE EVALUATION
14 A C 2 "
D JP
I
~
~
I
CI1. 2
•
T1 .. b, • • •
IIL-SOOIl
V S. SOP
':..
....... ~
VCC-5V
CL-50pF
~
""- ~ ~ f"
-
K _ ,.../
\.000 •• ItI/OIV
2.00 nl/dh
V
P .. ·D I P
IIV
rW"·3tO.}I~Or
p.IIV
r"·299 .. llsor
O.14V
'--------------------------------------------TOSHIBA
Fig. 2-6
2-2-3 Load Capacitance Dependence
Another factor which determines noise voltage value is the load capacitance CL . As mentioned above, noise
voltage can be expressed as:
.0.V=Lill
(1)
i = C dV
dt
(2)
:. 6 V = L ill = LC d 2 V
dt
dt 2
(3)
dt
TOSHIBA CORPORATION - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
AC-330
SIMULTANEOUS SWITCHING NOISE EVALUATION
Vcc-SV
Ch.I-IV/dtv.
tr-tl-3ns
Ch.2-IV/dtv.
CL Dependence RL-S00ohm
Ttmebase-Sns/dtv.
SRMPLE:TC74RC244P Ipc
(VOLP-0.72V,VOHV-I.06V)
STABLE CL-BpF'
STABLE
SWITCHI NG
I.-..,..".-~-I-~I---+--f- OUTPUT
OUTPUT
r -
:r .-.- ......................OV
1""'-
"
~ OV
OUTPUT
~
II
I/r
sv
,..... v
OV L
.........
_L
.-f\'
1\
l ; - t....
!--
.....
-
,...-- --- --- ...........
----- --./
""
CL-SBpF'
~
"""
~ III
/1"'-0..
..I
\
(VOLP-I.24V,VOHV-l.SBV)
""'"
......
./
1
t-..
Ir-
\\.
\
\
--
r
I""'--..
/
r--..,.
,- t:::--.,
10---.
-
r--
/
~
. / f"""-...
1L
--- ~-- ---
~
~
--- --- ---
I""
CL-1BBpF'
"""
/
\"
\.
eVOLP-l.16V,VOHV-l.36V)
"\.
CL-15BpF'
""" '\
./
~
[""-.."
/'
--"""
/ V
~-
--
--- --- --- ---
,/
.... 1-'"
(VOLP-l.BSV,VOHV-l.24V)
......
\..
"Fig. 2·7
-- --
/
r. / r-
./
/'
-
/'
...-,-
L
/
."
/ ./
~
"'--- T --- --- --- --./
-----------------------------------------------------~HIBACaRPORAnaN
AC·331
SIMULTANEOUS SWITCHING NOISE EVALUATION
Sample Dependence
Vcc-SV
t .. -tf-3ns
CL-5I21pF'
RL-SBBohm
GND Bounce
SHITCHING
OUTPUT
TC74AC244P
STABLE
OUTPUT
,v
"""
/
/'
\
ev
"'- r-
......
/,
\
./
CONDITION---------------
-
-
Ch.l
- IVl'dly.
Ch.2
- IV/dly.
Tlmebase - Sns/dly.
VENDOR C
"\
II
J
ev
\
\
"
./
./
VOLP-2.1214V
VOLP-I.3BV
VENDOR A
TC74HC244AP
r-- ~
"'\
A\
./
\
/'
........
\
I-' /" .......
\
\
./
\
-
......
1\
\
-
t-,.....o'
VOLP-e.SBV
VOLP-2.12V
74F244
VENDOR B
./
\
1/
\
\
..., ,
\
"r-....
-
-
,
./
\
./
/
VOLP-2.34V
VOLP-B.9SV
Fig. 2-8
TOSHIBA CO~PORATION - - - - - - - - - - - - - . , - - - - - - - - - - - - -
AC-332
SIMULTRNEOUS SWITCHING NOISE EVRLURTION
Sample Dependence
CONDITION - - - - - - - - . .
Ch.l
- IV.... d·tv.
Ch.2
- IV .... dtv.
Ttmebaae - Sn ..... dtv.
Vcc-SV
t.,,-t.f-3na
CL-SBpF'
RL-SBBohm
Vee Bounce
INITcHJNG
~T
TC74RC244P
.T....'
~~~T-~~~~~o~~
VENDOR, C
,
/
/
-
.......
.........
-- -
7
VOHV-2.1BV
VOHV-I.S4V
VENDOR R
,
,
\
,
"-
/'
"-
YI/
~
'"
TC74HC244RP
--
.,.... ......
/'
,
/
-
..
/'
VOHV-l.BSV
VOHV-2.12V
74F'244
VENDOR B
/'
,,
,
\
V
I-""
""-
'"
....-
1/
/
J
-
.....
/.
VOHV-2.B2V
VOHV-l.BBV
Fig. 2-9
- - - - - - - - - - - - - - - - - - - - - - - - T C H I H I I I A calUlOIIUIImDN
AC-333
NOTES
14.
CROSS REFERENCE GUIDE
TC74AC/ACT SERIES
CROSS REFERENCE GUIDE
TOSHIBA
--
HARRIS
NATIONAL
MOTOROLA
HITACHI
TC74ACOO
TC74AC02
TC74AC04
TC74AC05
TC74AC08
CD74ACOO
CD74AC02
CD74AC04
CD74AC05
CD74AC08
74ACOO
74AC02
74AC04
MC74ACOO
MC74AC02
MC74AC04
74AC08
MC74AC08
HD74AC08
TC74ACIO
TC74ACll
TC74AC14
TC74AC20
TC74AC32
CD74ACIO
CD74AC14
CD74AC20
CD74AC32
74AClO
74ACll
74ACl4
74AC20
74AC32
MC74AClO
MC74ACll
MC74AC14
MC74AC20
MC74AC32
HD74ACIO
HD74ACll
HD74AC14
HD74AC20
HD74AC32
TC74AC74
TC74AC86
TC74ACI09
TC74ACll2
TC74AC125
CD74AC74
CD74AC86
CD74AClO9
CD74AC1l2
74AC74
74AC86
74ACI09
74AC1l2
MC74AC74
MC74AC86
MC74AClO9
HD74AC74
HD74AC86
HD74AClO9
HD74AC1l2
HD74AC125
CD74AC138
CD74AC139
CD74AC151
CD74ACl53
74ACl38
74ACl39
74AC151
74ACl53
MC74ACl38
MC74AC139
MC74AC151
MC74ACl53
HD74ACl38
HD74ACl39
HD74AC151
HD74AC163
TC74ACl57
TC74AC158
TC74AC160
TC74ACl61
TC74AC162
CD74AC157
CD74AC158
74ACl57
74ACl58
74ACl60
74ACl61
74AC162
MC74AC157
MC74ACl68
MC74ACl60
MC74ACl61
MC74ACl62
HD74AC157
HD74AC158
TC74AC163
TC74AC164
TC74ACl66
TC74AC169
TC74AC174
CD74AC163
CD74AC164
CD74AC166
74AC163
74ACl64
MC74AC163
74ACl69
74ACl74
MC74ACl69
MC74ACl74
HD74AC163
HD74ACl64
HD74AC166
HD74AC169
HD74AC174
TC74ACl75
TC74AC191
TC74AC240
TC74AC241
TC74AC244
CD74AC175
MC74ACl75
MC74ACl91
MC74AC240
MC74AC241
MC74AC244
HD74AC175
CD74AC240
CD74AC241
CD74AC244
74ACl76
74AC191
74AC240
74AC241
74AC244
TC74AC245
TC74AC251
TC74AC253
TC74AC257
TC74AC258
CD74AC245
CD74AC251
CD74AC253
CD74AC257
CD74AC258
74AC245
74AC251
74AC253
74AC257
74AC258
MC74AC245
MC74AC251
MC74AC253
MC74AC257
MC74AC258
HD74AC245
HD74AC251
HD74AC253
HD74AC257
HD74AC258
TC74ACl26
TC74ACl38
TC74AC139
TC74AC151
TC74ACl53
CD74AC161
CD74AC174
HD74ACOO
HD74AC02
HD74AC04
HD74AC240
HD74AC241
HD74AC244
-----------------------------------------------------TO&HIBACDAPOA~N
AC-337
CROSS REFERENCE GUIDE
TOSIDBA
HARRIS
1'0700259
TC7OO273
TC7OO280
1'0700283
TC7OO299
CANCELLED
CD7OO273
CD74AC280
CD7OO283
CD7OO299
1'0700323
TC7OO367
1'0700368
1'0700373
TC7OO374
CD7OO323
CD7OO373
CD7OO374
1'0700377
1'0700390
1'0700393
1'0700520
1'0700521
NATIONAL
700273
MOTOROLA
MC74AC273
700299
MC7OO299
74AC323
MC74AC323
74AC373
700374
MC74AC373
MC7OO374
74AC377
MC74AC377
HD7OO377
700520
700521
MC74AC520
MC7OO521
HD74AC393
CD7OO533
CD7OO534
CD7OO540
CD74AC541
CD7OO563
74AC533
74AC534
74AC540
74AC541
74AC563
MC74AC533
MC74AC534
MC74AC540
MC74AC541
MC7OO563
TC74AC564
TC7OO573
1'0700574
TC7OO620
1'0700623
CD74AC564
CD7OO573
CD74AC574
74AC564
74AC573
700574
MC7OO564
MC74AC573
MC74AC574
700640
74AC643
700646
700648
MC7OO640
MC74AC643
MC74AC646
MC7OO648
74AC821
700823
700825
74AC841
700843
MC74AC825
HD74AC540
HD74AC541
HD74AC573
HD7OO574
CD7OO623
CD7OO646
CD7OO648
TC7OO821
TC7OO823
TC7OO825
1'0700841
1'0700843
TC74ACTOO
1'07OOT02
TC7OOT04
1'074ACTOS
TC74ACTI0
HD74AC273
HD74AC280
HD7OO283
HD7OO367
HD7OO368
HD74AC373
HD74AC374
TC7OO533
TC7OO534
1'0700540
TC7OO541
1'0700563
1'0700640
TC74AC643
1'0700646
1'0700648
TC7OO670
HITACID
CD7OOTOO
CD7OOT02
CD74ACT04
CD74ACTOS
CD74ACTIO
74ACTOO
74ACT04
74ACT08
HD74AC646
HD74AC648
HD7OO670
MC74AC843
MC74ACTOO
MC7OOT02
MC74ACT04
MC74ACT08
MC74ACTIO
HD74ACTOO
HD74ACT04
TQIIHIIIA COAIItOAATION - - - - - - - - - - - - - - - - - - - - - - - - - -
AC-338
CROSS REFERENCE GUIDE
TOSHIBA
HARRIS
NATIONAL
MOTOROLA
HITACHI
HD74ACT14
TC74ACT14
TC74ACT32
TC74ACT74
TC74ACT86
TC74ACT109
CD74ACT14
CD74ACT32
CD74ACT74
CD74ACT86
CD74ACTlO9
74ACT14
74ACT32
74ACT74
MC74ACT14
MC74ACT32
MC74ACT74
74ACTI09
MC74ACT109
HD74ACT74
HD74ACT86
HD74ACTI09
TC74ACT1l2
TC74ACT138
TC74ACT139
TC74ACT151
TC74ACT153
CD74ACTll2
CD74ACT138
CD74ACT139
CD74ACT151
CD74ACT153
74ACT138
74ACT139
74ACT151
74ACT153
MC74ACT138
MC74ACT139
MC74ACT151
MC74ACT153
HD74ACTll2
HD74ACT138
HD74ACT139
HD74ACT151
HD74ACT153
TC74ACT157
TC74ACT158
TC74ACT161
TC74ACT163
TC74ACT164
CD74ACT157
CD74ACT158
CD74ACT161
CD74ACT163
CD74ACT164
74ACT157
74ACT158
74ACT161
74ACT163
MC74ACT157
MC74ACT158
MC74ACT161
MC74ACT163
HD74ACT157
HD74ACT158
HD74ACT161
HD74ACT163
HD74ACT164
TC74ACT174
TC74ACT175
TC74ACT240
TC74ACT241
TC74ACT244
CD74ACT174
CD74ACT175
CD74ACT240
CD74ACT241
CD74ACT244
74ACT174
74ACT175
74ACT240
74ACT241
74ACT244
MC74ACT174
MC74ACT175
MC74ACT240
MC74ACT241
MC74ACT244
HD74ACT174
TC74ACT245
TC74ACT251
TC74ACT253
TC74ACT257
TC74ACT258
CD74ACT245
CD74ACT251
CD74ACT253
CD74ACT257
CD74ACT258
74ACT245
74ACT251
74ACT253
74ACT257
74ACT258
MC74ACT245
MC74ACT251
MC74ACT253
MC74ACT257
MC74ACT258
HD74ACT245
HD74ACT251
HD74ACT253
HD74ACT257
HD74ACT258
TC74ACT273
TC74ACT280
TC74ACT283
TC74ACT323
TC74ACT373
CD74ACT273
CD74ACT280
CD74ACT283
CD74ACT323
CD74ACT373
74ACT273
MC74ACT273
HD74ACT273
HD74ACT280
HD74ACT283
74ACT323
74ACT373
MC74ACT323
MC74ACT373
TC74ACT374
TC74ACT377
TC74ACT520
TC74ACT521
TC74ACT533
CD74ACT374
CD74ACT533
74ACT374
74ACT377
74ACT520
74ACT521
74ACT533
MC74ACT374
MC74ACT377
MC74ACT520
MC74ACT521
MC74ACT533
TC74ACT534
TC74ACT540
TC74ACT541
TC74ACT563
TC74ACT564
CD74ACT534
CD74ACT540
CD74ACT541
CD74ACT563
CD74ACT564
74ACT534
74ACT540
74ACT541
74ACT563
74ACT564
MC74ACT534
MC74ACT540
MC74ACT541
MC74ACT563
MC74ACT564
HD74ACT240
HD74ACT241
HD74ACT244
HD74ACT373
HD74ACT374
HD74ACT377
HD74ACT540
HD74ACT541
HD74ACT563
HD74ACT564
-----------------------------------------------------~IBACaRPOAA~
AC-339
CROSS REFERENCE GUIDE
TOSHIBA
TC74ACT573
TC74ACT574
TC74ACT640
TC74ACT646
TC74ACT648
TC74ACT821
TC74ACT823
TC74ACT825
TC74ACT841
TC74ACT843
HARRIS
CD74ACT573
CD74ACT574
NATIONAL
74ACT573
74ACT574
74ACT640
MOTOROLA
MC74ACT573
MC74ACT574
MC74ACT640
CD74ACT646
CD74ACT648
,
HITACHI
HD74ACT573
HD74ACT574
HD74ACT646
HD74ACT648
74ACT821
74ACT823
74ACT825
74ACT841
74ACT843
MC74ACT825
MC74ACT843
The above is provided for infonnation only and was gathered from the latest data available. However, the accuracy of this
data cannot be guaranteed and 'lbshiba makes no warranty as to the correctness of this information.
T08HIIIA CGlllIIOIItATlON - - - - - - - - - - - - - - - - - - - - - - - - -
AC-340
C2MOS LOGIC
TC74HC/HCT SERIES
INTRODUCTION
During the last several years, the scale of integration of LSI's has increased rapidly.
Because of this progress, heat radiation has become a big problem, similar to the way
that bipolar LSI's have been struggling for many years. It is well known that only
CMOS technology can reduce this problem. The use of CMOS technology has been
increasing in the field of LSI's such as high performance microprocessors and large
capacity memories. Additionally, high speed CMOS devices utilizing microlithography technology have been developed as general purpose logic IC's interfacing with
these high performance LSI's.
Since the introduction of the TC74HCxxx series as a high speed CMOS logic family
as a new generation in 1982, TOSHIBA has produced 176 type numbers to the
present time for use a variety of applications. Because the 74HC series is a CMOS
design, it is susceptible to latch-up; and because of a thin gate oxide structure,
electrostatic discharge (ESD) is also a problem. TOSHIBA has been working on
development of CMOS devices which overcome these problems.
In response to the latch-up and ESD issues, and, as a consequence of improvements in design rules and processes, TOSHIBA has revised the TC74HCxxx series
and now produces the TC74HCxxxA series. This revision has ample capacity for
handling ESD as well as the elimination of latch-up in normal applications. The
TC74HCxxxA series also provides an increased speed of operation of 20% to 30%
over the original series. The original TC74HCxxx series will be replaced with the ''A''
revision series which is upward compatible. Presently, TOSHIBA produces 169
TC74HCxxxA part types and will have more than 210 part types.
This book provides technical information on TOSHIBA's TC74HCxxxA series of
high speed C2MOS devices. In addition, this book contains technical information on
TC74HCxxx products for which the ''A'' versions are still under development.
The information contained in this data book is subject to change without notice.
February, 1990
TOSHIBA CORPORATION
HC-1
1.
2.
This technical data may be controlled under U.S. ExportAdmlnistration Regulations and may be subject
10 the approval 01 the U.S. Department 01 Commerce prior to export. Any export or re-export directly or
indirectly. in contravention of the U.S. Export Administration Regulations is strictly prohibited.
LIFESUPPORTPOLICY
Toshiba producta described in this databook are not authorized lor use as critical components In life
support systems without the written consent 01 the appropriate officer 01 Toshiba America. Inc. Life
support systems are ellher systems intended lor surgical implant In the body or systems which sustain life.
A critical component is any component of a life support system whose failure to perform may cause a
malfunction or faiture of the life support system. or may affect its safety or effectiveness.
3.
The inlormation In this dl\tabook has been carefully Checked and Is belieVed to be reliable. however. no
responsibility can be assumed for Inaccuracies that may not have been caught. All information in this
databook is subject to change without prior notice. Furthermore. Toshiba cannot assume responsibility
lor the use of any ticense under the patent rights of Toshiba or any third parties.
HC-2
CONTENTS
--------------------HC4
1.
HIGH SPEED CMOS PRODUCT GUIDE
2.
HIGH SPEED CMOS SELECTION GUIDE
12
3.
PRODUCT OUTLINE OF THE TC74HCxxxA SERIES
3-1
Features
Method of Designating the TC74HC Series
3-2
48
51
52
4.
EXPLANATION OF RATINGS AND STANDARDS
4-1
Maximum Ratings
4-2
Recommended Operating Conditions
4-3
DC Characteristics
AC Characteristics
4-4
55
55
EXPLANATION OF IEC LOGIC SYMBOL - - - - - - - - - - - - - - - - - - 5-1
Symbol Composition - - - - - - - - - - - - - - - - - - - - - - 5-2
Qualifying Symbol - - - - - - - - - - - - - - - - - - - - - - 5-3
Dependency Notation
66
6.
HOW TO READ MIL TYPE LOGIC SYMBOLS AND TRUTH TABLES
6-1
How to read MIL type Logic Symbols
6-2
How to Read Truth Tables
72
72
74
7.
COMMON
7-1
7-2
7-3
7-4
7-5
75
75
5.
ELECTRICAL CHARACTERISTICS
Power Dissipation
Standardized Capacitance Power Dissipation ( Cpo) Test Procedure
Output Current Characteristics - - - - - - - - - - - - - - - - - - - AC Electrical Characteristics - - - - - - - - - - - - - - - - - - - - Temperature Parameters of Various Characteristics
56
57
61
66
66
70
78
85
87
90
8.
PRECAUTIONS IN HANDLING
8-1
Electrostatic Discharge
8-2
Precaution in Handling
91
91
92
9.
PRECAUTIONS IN DESIGNING CIRCUITS
9-1
Input Processing
9-2
DeSign of Power source
9-3
On Output Short-Circuit
9-4
Effect on Inp~t of Slow rise and Fall Time
9-5
Wiring Precautions
94
94
95
95
96
97
N
~~
9-7
9-8
Latch-Up - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 3
Metastable Characteristics - - - - - - - - - - - - - - - - - - - - - 107
~
10. DATASHEETS - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 0 9
11. OUTLINE DRAWINGS - - - - - - - - - - - - - - - - - - - - - - - - - 811
12. CROSS REFERENCE GUIDE - - - - - - - - - - - - - - - - - - - - - - - - - - - 819
HC-3
1. HIGH SPEED CMOS PRODUCT GUIDE
Type Number
TC74HC
TC74HC
TC74HC
TC74HC
TC74HC
Function
OOAP/AF/AFN
TOOAP/AF
02AP/AF/AFN
T02AP/AF
03AP/AF/AFN
04AP/AF/AFN
T04AP/AF/AFN
U04AP/AF/AFN
05AP/AF
07AP/AF
QUAD 2-INPUT NAND GATE
QUAD 2-INPUT NAND GATE
QUAD 2-INPUT NOR GATE
08AP/AF/AFN
T08AP/AF
09AP/AF
10AP/AF/AFN
11AP/AF/AFN
14AP/AF/AFN
20AP/AF/AFN
21AP/AF/AFN
27AP/AF/AFN
30AP/AF/AFN
QUAD 2-INPUT AND GATE
QUAD 2-INPUT AND GATE
32AP/AF/AFN
T32AP/AF
42AP/AF/AFN
51 AP/AF/AFN
73AP/AF
74AP/AF/AFN
T74AP/AF
75AP/AF
76AP/AF
77AP/AF
QUAD 2-INPUT OR GATE
QUAD 2-INPUT OR GATE
85AP/AF/AFN
86AP/AF/AFN
T86AP/AF
107AP/AF/AFN
109AP/AF/AFN
112AP/AF/AFN
113AP/AF
123AP/AF/AFN
125AP/AF/AFN
126AP/AF
4-BIT MAGNITUDE COMPARATOR
131AP/AF
132AP/AF/AFN
133AP/AF
137AP/AF
T137AP/AF
138AP/AF/AFN
T138AP/AF/AFN
139AP/AF/AFN
T139AP/AF
147AP/AF
3-TO-8 LINE DECODER I LATCH
QUAD 2-INPUT SCHMITT NAND GATE
QUAD 2-INPUT NOR GATE
QUAD 2-INPUT NAND GATE (OPEN DRAINl
HEX INVERTER
HEX INVERTER
HEX INVERTER
HEX BUFFER (OPEN DRAIN)
HEX BUFFER (OPEN DRAIN)
QUAD 2-INPUT AND GATE (OPEN DRAIN)
TRIPLE 3-INPUT NAND GATE
TRIPLE 3-INPUT AND GATE
HEX SCHMITT INVERTER
DUAL 4-INPUT NAND GATE
DUAL 4-INPUT AND GATE
TRIPLE 3-INPUT NOR GATE
8-INPUT NAND GATE
BCD TO DECIMAL DECODER
DUAL 2W-21 AND lOR INVERT GATE
DUAL J-K fLIP-FLOP WITH CLEAR
DUAL 0 FLIP-FLOP WITH PRESET AND CLEAR
DUAL 0 FLIP-FLOP WITH PRESET AND CLEAR
4-BIT D-TYPE LATCH
DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR
4-BIT D-TYPE LATCH
QUAD EXCLUSIVE OR GATE
QUAD EXCLUSIVE OR GATE
DUAL J-K FLIP-FLOP WITH CLEAR
DUAL J-R FLIP-FLOP WITH PRESET AND CLEAR
DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR
DUAL J-K FLIP-FLOP WITH PRESET
DUAL MONOSTABLE MULTIVIBRATOR (tw out = 1.0· Cx . R.l
QUAD BUS BUFFER (3-STATE)
QUAD BUS BUFFER (3-STATE)
13·INPUT NAND GATE
3-TO-8 LINE DECODER I LATCH
3-TO-8 LINE DECODER I LATCH
3-T0-8 LINE DECODER
3-TO-8 LINE DECODER
DUAL 2-T0-4 LINE DECODER
DUAL 2-TO-4 LINE DECODER
10·TO·4 LINE PRIORITY ENCODER
HC-4
PIN
Page
14
14
14
14
14
14
14
14
14
14
111
114
118
121
125
128
131
134
137
140
14
14
14
14
14
14
14
14
14
14
143
146
150
153
156
159
162
165
168
171
14
14
16
14
14
14
14
16
16
14
174
177
181
185
189
193
197
201
205
209
16
14
14
14
16
16
14
16
14
14
213
219
16
14
16
16
16
16
16
16
16
16
251
255
258
261
266
272
276
280
283
287
'"
222
226
230
235
239
247
247
Type Number
TC74HC
TC74HC
TC74HC
TC74HC
TC74HC
Function
148AP/AF/AFN
151AP/AF/AFN
153AP/AF/AFN
154AP
155AP/AF/AFN
157AP/AF/AFN
T157AP/AF
158AP/AF/AFN
T158AP/AF
160AP/AF
8-TO-3 LINE PRIORITY ENCODER
161AP/AF/AFN
162AP/AF
163AP/AF/AFN
164AP/AF/AFN
T164AP/AF
165AP/AF/AFN
166AP/AF/AFN
173AP/AF
174AP/AF/AFN
T174AP/AF
SYNCHRONOUS BINARY COUNTER WITH ASYNC. CLEAR
175AP/AF/AFN
181P
182AP/AF
190AP/AF
191AP/AF
192AP/AF
193AP/AF/AFN
194AP/AF
195AP/AF
221AP/AF/AFN
237AP/AF
238AP/AF
240AP/AF/AFW
T240AP/AF/AFW
241AP/AF
T241AP/AF
242AP/AF
243AP/AF
244AP/AF/AFW
T244AP/AF/AFW
245AP/AF/AFW
T245AP/AF/AFW
251AP/AF
253AP/AF/AFN
257AP/AF/AFN
T257AP/AF
258AP/AF
T258AP/AF
259AP/AF/AFN
266AP/AF
8-CHANNEL MULTIPLEXER
DUAL 4-CHANNEL MULTIPLEXER
4-TO- 16 LINE DECODER
DUAL 2-TO-4 LINE DECODER
QUAD 2-CHANNEL MULTIPLEXER
QUAD 2-CHANNEL MULTIPLEXER
QUAD 2-CHANNEL MULTIPLEXER (INVERTED)
QUAD 2-CHANNEL MULTIPLEXER (INVERTED)
SYNCHRONOUS DECADE COUNTER WITH ASYNC. CLEAR
SYNCHRONOUS DECADE COUNTER WITH SYNC. CLeAR
SYNCHRONOUS BINARY COUNTER WITH SYNC. CLEAR
8-BIT SIPO SHIFT REGISTER
8-BIT SIPO SHIFT REGISTER
8-BIT PISO SHIFT REGISTER
8-BIT PISO SHIFT REGISTER
QUAD D-TYPE REGISTER (3-STATE)
HEX 0 FLIP-FLOP WITH CLEAR
HEX 0 FLIP-FLOP WITH CLEAR
QUAD 0 FLIP-FLOP WITH CLEAR
ALiTHMETIC LOGIC UNIT
LOOK AHEAD CARRY LOGIC
BCD UP, DOWN COUNTER
4-BIT BINARY UP, DOWN COUNTER
SYNCHRONOUS UP I DOWN DECADE COUNTER
SYNCHRONOUS UP, DOWN BINARY COUNTER
4-BIT PIPO SHIFT REGISTER
4-BIT PIPO SHIFT REGISTER
DUAL MONOSTABLE MULTIVIBRATOR (tw out • 1.0' Cx . Rx)
3-TO-8 LINE DECODER' LATCH
3-TO-8 LINE DECODER
OCTAL BUS BUFFER (3-STATE 'INVERTED)
OCTAL BUS BUFFER (3-STATE I INVERTED)
OCTAL BUS BUFFER (3-STATE)
OCTAL BUS BUFFER (3-STATE)
QUAD BUS TRANSCEIVER (3-STATE 'INVERTED)
QUAD 8US TRANSCEIVER (3-STATE)
OCTAL BUS BUFFER (3-STATE)
OCTAL BUS BUFFER (3-STATE)
OCTAL BUS TRANSCEIVER (3-STATE)
OCTAL BUS TRANSCEIVER (l-STATE)
B-CHANNEL MULTIPLEXER (3-STATE)
DUAL 4-CHANNEL MULTIPLEXER (3-STATE)
QUAD 2-CHANNEL MULTIPLEXER (3-STATE)
QUAD 2-CHANNEL MULTIPLEXER (3-STATE)
QUAD 2-CHANNEL MULTIPLEXER (3-STATE 'INVERTED)
QUAD 2-CHANNEL MULTIPLEXER (3-STATE 'INVERTED)
8-BIT ADDRESSABLE LATCH
QUAD EXCLUS.IVE NOR GATE
HC-5
PIN
Page
16
16
16
24
16
16
16
16
16
16
291
296
300
304
308
312
316
312
316
320
16
16
16
14
14
16
16
16
16
16
320
320
320
330
*
334
340
346
351
*
16
24
16
16
16
16
16
16
16
16
355
359
370
376
376
384
384
392
398
404
16
16
20
20
20
20
14
14
20
20
412
417
421
425
421
425
429
429
421
425
20
20
16
16
16
16
16
16
16
14
433
437
441
300
445
449
445
449
453
458
Type Number
TC74HC
TC74HC
TC74HC
TC74HC
TC74HC
Function
273AP/AF/AFW
T273AP/AF/AFW
279AP/AF
280AP/AF
283AP/AF/AFN
298AP/AF
299AP/AF
323AP/AF
352AP/AF
353AP/AF
OCTAL 0 FLIP-FLOP WITH CLEAR
354AP/AF
356AP/AF
365AP/AF
366AP/AF
367AP/AF/AFN
368AP/AF/AFN
373AP/AF/AFW
T373AP/AF/AFW
374AP/AF/AFW
T374AP/AF/AFW
B-CHANNEL MULTIPLEXER ( REGISTER
375AP/AF
377AP/AF
386AP/AF
390AP/AF/AFN
393AP/AF/AFN
423AP/AF
533AP/AF
T533AP/AF
534AP/AF
T534AP/AF
OCTAL 0 FLIP-FLOP WITH CLEAR
QUAD
S-il
LATCH
9-BIT PARITY GENERATOR (CHECKER
4-BIT BINARY FULL ADDER
QUAD 2-CHANNEL MULTIPLEXER ( REGISTER
B-BIT PIPO SHIFT REGISTER
B-Blt PIPO SHIFT REGISTER
DUAL 4-TO-l MULTIPLEXER
DUAL 4-TO-l MULTIPLEXER (3-STATE)
B-CHANNEL MULTIPLEXER (REGISTER
HEX BUS BUFFER (3-STATE)
.HEX BUS BUFFER (3-STATE (INVERTED)
HEX BUS BUFFER (3-STATE)
HEX BUS BUFFER (3-STATE (INVERTED)
OCTAL D-TYPE LATCH (3-STATE)
OCTAL D-TYPE LATCH (3-STATE)
OCTAL D-TYPE FLIP-FLOP (3-STATE)
OCTAL D-TYPE FLIP-FLOP (3-STATE)
QUAD 0-TYPE LATCH
OCTAL D-TYPE FLIP-FLOP
QUAD EXCLUSIVE OR GATE
DUAL DECADE COUNTER
DUAL BINARY COUNTER
DUAL MONOSTABLE MULTIVIBRATOR (twout
e
1.0·Cx ·Rx)
OCTAL D-TYPE LATCH (3-STATE (INVERTED)
OCTAL D-TYPE LATCH (3-STATE (INVERTED)
OCTAL D-TYPE FLIP-FLOP (3-STATE (INVERTED)
OCTAL D-TYPE FLIP-FLOP (3-STATE (INVERTED)
540AP/AF/AFW
T540AP/AF/AFW
541AP/AF/AFW
T541 AP/AF/AFW
563AP/AF
T563AP/AF
564AP/AF
T564AP/AF
573AP/AF/AFW
T573APIAFI AFW
OCTAL BUS BUFFER (3-STATE (INVERTED)
574AP/AF/AFW
T574AP/AF
590AP/AF
592P
593AP/AF
595AP/AF/AFN
597AP/AF
620AP/AF
623AP/AF
640AP/AF
OCTAL 0-TYPE FLIP-FLOP (3-STATE)
OCTAL BUS BUFFER (3-STATE (INVERTED)
OCTAL BUS BUFFER (3-STATE)
OCTAL BUS BUFFER (3-STATE)
OCTAL D-TYPE LATCH (3-STATE (INVERTED)
OCTAL D-TYPE LATCH (3-STATE'INVERTED)
OCTAL D-TYPE FLIP-FLOP (3-STATE (INVERTED)
OCTAL D-TYPE fliP-FLOP (3-STATE 'INVERTED)
OCTAL D-TYPE LATCH (3-STATE)
OCTAL D-TYPE LATCH (3-STATE)
OCTAL D-TYPE FLIP-FLOP (3-STATE)
B-BIT BINARY COUNTER I REGISTER (3-STATE)
B-BIT REGISTER I BINARY COUNTER
B-BIT REGISTER I BINARY COUNTER (3-STATE)
B-BIT SHIFT REGISTER I LATCH ()-STATE)
B-BIT LATCH I SHIFT REGISTER
OCTAL BUS TRANSCEIVER (3-STATE 'INVERTED)
OCTAL BUS TRANSCEIVER (3-STATE)
OCTAL BUS TRANSCEIVER (3-STATE'INVERTED)
HC-6
PIN
Page
20
20
16
14
16
16
20
20
16
16
461
465
469
473
477
481
485
485
491
491
20
20
16
16
16
16
20
20
20
20
495
501
507
507
511
511
515
519
523
527
16
20
14
16
14
16
20
20
20
20
531
535
53.9
542
548
552
515
519
523
527
20
20
20
20
20
20
20
20
20
20
560
564
560
564
568
572
576
580
568
572
20
20
16
16
20
16
16
20
20
20
576
580
586
593
*
601
607
613
613
433
Type Number
TC74HC
TC74HC
TC74HC
TC74HC
TC74HC
Function
T640AP/AF
643AP/AF
T643AP/AF
646AP
T646AP
648AP
T648AP
651AP
T651AP
652AP
OCTAL BUS TRANSCEIVER (3-STATE'INVERTED)
T652AP
670AP/AF
688AP/AF
T688AP/AF
690AP/AF
691AP/AF
692AP/AF
693AP/AF
696P
697P
OCTAL BUS TRANSCEIVER' REGISTER (3-STATE)
698P
699P
4002AP/AF
4016AP/AF
4017P/F
4020AP/AF/AFN
4022AP/AF
4024AP/AF
4028AP/AF
4040AP/AF/AFN
UP (DOWN DECADE COUNTER (REGISTER (3-STATE)
4049AP/AF/AFN
4050AP/AF/AFN
4051AP/AF
4052AP/AF
4053AP/AF/AFN
4060AP/AF
4066AP/AF/AFN
4072AP/AF
4075AP/AF
4078AP/AF
HEX BUFFER (INVERTED)
4094AP/AF/AFN
40102P
40103P
40105AP/AF
4316AP/AF
4351AP/AF
4352AP/AF
4353AP/AF
4511AP/AF
4514AP
OCTAL BUS TRANSCEIVER (3-STATE)
OCTAL BUS TRANSCEIVER (3-STATE)
OCTAL BUS TRANSCEIVER' REGISTER (3-STATE)
OCTAL BUS TRANSCEIVER (REGIS'TER (3-STATE)
OCTAL BUS TRANSCEIVER (REGISTER (3-STATE 'INVERTED)
OCTAL BUS TRANSCEIVER' REGISTER (3-STATE 'INVERTED)
OCTAL BUS TRANSCEIVER (REGISTER (3-STATE ( INVERTED)
OCTAL BUS TRANSCEIVER' REGISTER (3-STATE 'INVERTED)
OCTAL BUS TRANSCEIVER (REGISTER (3-STATE)
4-WORD
x
4-BIT REGISTER FILE (3-STATE)
8-81T EQUALITY COMPARATOR
8-81T EQUALITY COMPARATOR
DECADE COUNTER REGISTER (3-STATE)
4-BIT BINARY COUNTER REGISTER (3-STATE)
DECADE COUNTER REGISTER (3-STATE)
4-BIT BINARY COUNTER REGISTER (3-STATE)
UP (DOWN DECADE COUNTER' REGISTER (3-STATE)
UP (DOWN 4-81T BINARY COUNTER (REGISTER (3-STATE)
UP (DOWN 4-BIT BINARY COUNTER' REGISTER (3-STATE)
DUAL 4-INPUT NOR GATE
QUAD BILATERAL SWITCH
DECADE COUNTER' DIVIDER
14-STAGE BINARY COUNTER
OCTAL COUNTER' DIVIDER
7-STAGE BINARY COUNTER
BCD TO DECIMAL DECODER
12-STAGE BINARY COUNTER
HEX BUFFER
B-CHANNEL ANALOG MULTIPLEXER
DUAL 4-CHANNEL ANALOG MULTIPLEXER
TRIPLE 2-CHANNEL ANALOG MULTIPLEXER
14-STAGE BINARY COUNTER (OSCILLATOR
QUAD BILATERAL SWITCH
DUAL 4-INPUT OR GATE
TRIPLE 3-INPUT OR GATE
8-INPUT OR' NOR GATE
8-BIT SIPO SHIFT REGISTER' LATCH (3-STATE)
DUAL BCD PROGRAMMABLE DOWN COUNTER
8-BIT BINARY PROGRAMMABLE DOWN COUNTER
4-BIT
x
16-WORD FIFO REGISTER
QUAD BILATERAL SWITCH
8-CHANNEL ANALOG MULTIPLEXER
DUAL 4-CHANNEL ANALOG MULTIPLEXER
TRIPLE 2-CHANNEL ANALOG MULTIPLEXER
BCD TO 7 SEGMENT LATCH' DECODER ( DRIVER
4-TO-16 LINE DECODER' LATCH
He-7
PIN
Page
20
20
20
24
24
24
24
24
24
24
437
433
437
617
623
617
623
628
634
628
24
16
20
20
20
20
20
20
20
20
634
639
645
20
20
14
14
16
16
16
14
16
16
672
672
684
16
16
16
16
16
16
14
14
14
14
710
710
714
714
714
721
726
730
733
736
16
16
16
16
16
20
20
20
16
24.
739
745
745
756
*
649
649
649
649
661
661
*
687
693
698
702
706
693
*
*
*
*
763
770
Type Number
TC74HC
TC74HC
4515AP
4518P
4520P/F
4538AP/AF/AFN
4543AP/AF
T7007AP/AF
7240AP/AF
7241 AP/AF
7244AP/AF
7266AP/AF
7292P
7294P
7640AP/AF
7643AP/AF
7645AP/AF
Function
4-TO-16 LINE DECODER (LATCH (INVERTED)
DUAL DECADE COUNTER
DUAL 4-BIT BINARY COUNTER
DUAL MONOSTABLE MULTIVIBRATOR
BCD TO 7 SEGMENT LATCH ( DECODER I DRIVER
HEX BUFFER
OCTAL BUS BUFFER (3-STATE I INVERTED)
OCTAL BUS BUFFER (3-STATE)
OCTAL BUS' BUFFER (3-STATE)
QUAD EXCLUSIVE NOR GATE
PROGRAMMABLE DIVIDER I TIMER
PROGRAMMABLE DIVIDER I TIMER
OCTAL BUS TRANSCEIVER (3-STATE I INVERTED)
OCTAL BUS TRANSCEIVER (3-STATE)
OCTAL BUS TRANSCEIVER (3-STATE)
I All 24pin DIP products are provided in the 300mil narrow package.
I
* denotes products under development.
HC-8
PIN
Page
24
16
16
16
16
14
20
20
20
14
770
774
774
781
789
794
797
797
797
458
16
16
20
20
20
801
801
*
*
*
CHANGE-OVER TO THE NEW ENHANCED VERSION
By the end of March, 1989, we have successfully changed-over
Since 1982 TOSHIBA has been producing 176 types of
TC74HCxxx series, which are well accepted in the world-wide
PHASE II
the first group of 100 part numbers.
The second group, 32 types are listed in the table below, are
market place.
In 1987, applying enhanced design and process technology,
projected to be discontinued by the end of March, 1990.
TOSHIBA developed the "An version of that series.
TOSHIBA would like customers to consider those enhanced
The new enhanced TC74HCxxxA series offers higher AC
types and cooperate in the change-over from the old version.
performance, ESDS, reliability, and so on, while maintsining the
TOSHIBA believes that the new, enhanced version will con-
compatibility with the old version and JEDEC standard
tribute to the achievement of better performance of the final
specification.
equipment.
TOSHIBA recommends customers replace the TC74HCxxx
series with the new TC74HCxxxA series.
DISCONTINUED TYPE LIST [Ph-II]
TYPE NAME
TC74HC
30PIF
86P/F
107PIF
113PIF
1&3P/F
173P/F
192P/F
193PIF
194PIF
FUNCTION
REPLACEMENT
8-INPUT NAND GATE
QUAD EXCLUCIVE OR GATE
DUAL J-K FLIP-FLOP WITH CLEAR
DUAL J-K FLIP-FLOP WITH PRESET
DUAL 4-CHANNEL MULTIPLEXER
QUAD D-TYPE REGISTER (3-STATE)
SYNC. UP I DOWN DECADE COUNTER
SYNC. UP I DOWN BINARY COUNTER
4-BIT PIPO SHIFT REGISTER
4-BIT PIPO SHIFT REGISTER
TC74HC
3-TO-8 LINE DECODER I LATCH
DUAL 4-CH MULTIPLEXER (3-STATE)
8-BIT ADDRESSABLE LATCH
QUAD S-R LATCH
8-CHANNEL MULTIPLEXER I REGISTER
8-CHANNEL MULTIPLEXER I REGISTER
HEX BUS BUFFER (3-STATE)
HEX BUS BUFFER (3-STATE IINV.)
OCTAL D-TYPE FLIP-FLOP
14-STAGE BINARY COUNTER
TC74HC 237AP/AF
TC74HC 4040AP/AF/AFN
4049AP/AF/AFN
4072PIF
4078P/F
4094PIF
4514P
4515P
12-STAGE BINARY COUNTER
HEX BUFFER CINV.)
HEX BUFFER
14-STAGE BINARY COUNTERIOSCILATOR
QUAD BILATERAL SWITCH
DUAL 4-INPUT OR GATE
8-INPUT OR I NOR GATE
8-BIT SIPO SHIFT REGISTER I LATCH
4-TO-16 LINE DECODER I LATCH
4-TO-16 LINE DECODER I LATCH (lNV.)
TC74HC 4538PIF
4543P/F
DUAL MONOSTABLE MULTIVlBRATOR
BCD '1'07 SEG. LATCH/DECODElUDRIVER
TC74HC 4538AP/AF/AFN
4543AP/AF
195P/F
TC74HC
237P/F
253PIF
259PIF
279P/F
.354PIF
356P/F
365P/F
366PIF
377P/F
4020P/F
TC74HC
4040P/F
4049P/F
4050P/F
4060P/F
4066P/F
HC-9
30AP/AF/AFN
86AP/AF/AFN
107AP/AF/AFN
113AP/AF
153AP/AF/AFN
173AP/AF
192AP/AF
193AP/AF/AFN
194AP/AF
195AP/AF
253AP/AF/AFN
259AP/AF/AFN
279AP/AF
354AP/AF
356AP/AF
365AP/AF
366AP/AF
377AP/AF
4020AP/AF/AFN
4050AP/AF/AFN
4060AP/AF
4066API AFIAFN
4072AP/AF
4078AP/AF
4094AP/AF/AFN
4514AP
4515AP
DISCONTINUED TYPE LIST .[ Ph- I ]
TYPE NAME
1989 March.-
FUNCTION
REPLACEMENT
QUAi> 2-INPUT NAND GATE
QUAD 2-INPUT NOR GATE
QUAD 2-INPUT.-I\IAND GATE (OPEN DRAIN)
HEX INVERTER
HEX INVERTER
HEX INVERTER
QUAD 2-INPUT AND GATE
TRIPPLE 3-INPUT NAND GATE
TRIPPLE 3-INPUT AND GATE
HEX SCHMITT INVERTER
TC74HC
TC74HC 20P/F
21P/F
27P/F
32P/F
42P/F
51P/F
73P/F
74P/F
75P/F
76P/F
DUAL 4-INPUT NAND GATE
DUAL 4-INPUT AND GATE
TRIPPLE 3-INPUT NOR GATE
QUAD 2-INPUT OR GATE
BCD TO DECIMAL DECODER
DUAL 2W-21 AND' OR INVERT GATE
DUAL J-K FLIP-FLOP WITH CLEAR
DUAL 0 FLIP-FLOP WITH PRESET AND CLEAR
4-BIT D-TYPE LATCH
DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR
TC74HC
TC74HC 77P/F
85P/F
lO9P/F
125P/F
126P/F
131PIF
132P/F
133P/F
137P/F
138P/F
4-BIT D-TYPE LATCH
·4-BIT MAGNITUDE COMPARATOR
TC74HC
TC74HC
OOP/F
02P/F
03P/F
04P/F
T04P/F
U04P/F
08P/F
10P/F'
llP/F
14P/F
TC74HC T138P/F
139P/F
151P/F
154P
155P/F
157P/F
158P/F
160P/F
161P/F
162P
TC74HC
163P/F
164P/F
165P/F
166P/F
174P/F
175P/F
238P/F
240P/F
T240P
241P/F
DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR
QUAD BUS BUFFER (3-STATE)
QUAD BUS BUFFER (3-STATE)
3-TO-B LINE DECODER' LATCH
QUAD 2-INPUT SCHMITT NAND
13-INPUT NAND GATE
3-TO-8 LINE DECODER' LATCH
3-TO-B LINE DECODER
OOAP/AF/AFN
02AP/AF/AFN
03AP/AF/AFN .
04AP/AF/AFN
T04AP/AF/AFN
U04AP/AF/AFN
08AP/AF/AFN
10AP/AF/AFN
llAP/AF/AFN
14AP/AF/AFN
20AP/AF/AFN
21AP/AF/AFN
27AP/AF/AFN
32AP/AF/AFN
42AP/AF/AFN
51AP/AF/AFN
73AP/AF
74AP/AF/AFN
75AP/AF
76AP/AF
77AP/AF
85AP/AF/AFN
109AP/AF/AFN
125AP/AF/AFN
126AP/AF
131AP/AF
132AP/AF/AFN
133AP/AF
137AP/AF
138AP/AF/AFN
3-TO-8 LINE DECODER
DUAL 2-T04. LINE DECODER
8-CHANNEL MULTIPLEXER
4-TO-16 LINE DECODER
DUAL 2-TO-4 LINE DECODER
QUAD 2-CHANNEL MULTIPLEXER
QUAD 2-CHANNEL MULTIPLEXER (INV.)
SYNC. DECADE COUNTER WITH ASYNC. CLEAR
SYNC. BINARY COUNTER WITH ASYNC. CLEAR
SYNC. DECADE COUNTER WITH SYNC. CLEAR
TC74HCT 138AP/AF/AFN
SYNC. BINARY COUNTER WITH SYNC. CLEAR
8-BIT SIPO SHIFT REGISTER
8-81T PISO SHIFT REGISTER
8-BIT PISO SHIFT REGISTER
HEX 0 FLIP-FLOP WITH CLEAR
QUAD 0 FLIP-FLOP WITH CLEAR
3-TO-8 LINE DECODER
OCTAL 8US BUFFER (3-STATE 'INV.)
OCTAL BUS BUFFER (3-STATE 'INV.)
OCTAL BUS BUFFER (3·STATE)
TC74HC 163AP/AF/AFN
164AP/AF/AFN
HC-10
139AP/AF/AFN
151AP/AF/AFN
154AP
155AP/AF/AFN
157AP/AF/AFN
158AP/AF/AFN
160AP/AF
161AP/AF/AFN
162AP/AF
165AP/AF/AFN
166AP/AF/AFN
174AP/AF/AFN
175AP/AF/AFN
238AP/AF
240AP/AF/AFW
T240AP/AF/AFW
241AP/AF
1989 March.-
DISCONTINUED TYPE LIST [Ph- I ]
TYPE NAME
TC74HC T241P/F
244P/F
T244PIF
245PIF
T245P/F
251P/F
257P/F
258P/F
273P/F
280P/F
TC74HC
283P/F
298PIF
299P
323P
367P/F
368PIF
373PIF
374PIF
T374P/F
375P/F
TC74HC
386PIF
390PIF
TC74HC
FUNCTION
REPLACEMENT
TC74HC T241AP/AF
244AP/AF/AFW
OCTAL BUS BUFFER (3-STATE)
OCTAL BUS BUFFER (3-STATE)
T244AP/AF/AFW
245API AFIAFW
T245AP/AF/AFW
OCTAL BUS BUFFER (3-STATE
OCTAL BUS TRANSCEIVER (3-STATE)
OCTAL BUS TRANSCEIVER (3-STATE)
B-CHANNEL MULTIPLEXER (3-STATE)
251AP/AF
QUAD 2·CHANNEL MULTIPLEXER (3-STATE)
257AP/AF/AFN
QUAD 2-CHANNEL MULTIPLEXER (3-STATE IINV.)
258AP/AF
273AP/AF
280AP/AF
OCTAL 0 FLIP-FLOP WITH CLEAR
9-BIT PARITY GENERATOR I CHECKER
TC74HC
4-81T BINARY FULL .AOOER
283AP/AF/AFN
298AP/AF
299AP/AF
323AP/AF
QUAD 2-CHANNEL MULTIPLEXER I REGISTER
8-BIT PIPO SHIFT REGISTER
8-BIT PIPO SHIFT REGISTER
367 AP/AF/AFN
368AP/AF/AFN
373APIAFtAFW
374AP/AF/AF'W
T374AP/AF/AFW
HEX BUS BUFFER (3-STATE)
HEX BUS BUFFER (3-STATE IINV.)
OCTAL OoTYPE LATCH (3-STATE)
OCTAL 0 FLIP-FLOP (3-STATE)
OCTAL 0 FLIP-FLOP (3-STATE)
375AP/AF
QUAD OoTYPE LATCH
TC74HC
QUAD EXCLUSIVE OR GATE
386AP/AF
DUAL DECADE COUNTER
390AP/AF/AFN
393PIF
DUAL BINARY COUNTER
533PIF
OCTAL OoTYPE LATCH (3-STATE IINV.)
393AP/AF/AFN
533AP/AF
534P/F
OCTAL 0 FLIP-FLOP (3-STATE IINV.)
540PIF
OCTAL BUS BUFFER (3-STATE IINV.)
541P/F
563P/F
564P/F
OCTAL BUS BUFFER (3-STATE)
541AP/AF/AFW
OCTAL OoTYPE LATCH (3-STATE IINV.)
573P/F
OCTAL OoTYPE LATCH (3-STATE)
563AP/AF
564AP/AF
573AP/AF/AFW
534AP/AF
540AP/AF/AFW
OCTAL 0 FLIP-FLOP (3-STATE IINV.)
TC74HC
574P/F
OCTAL 0 FLIP-FLOP (3-STATE)
595P
B-BIT SHIFT REGISTER ILATCH (3-STATE)
574AP/AF
595AP/AF/AFN
597P/F
8-BIT LATCH I SHIFT REGISTER
597AP/AF
640PIF
OCTAL BUS TRANSCEIVER (3-STATE IINV.)
640AP/AF
T640P/F
643P/F
OCTAL BUS TRANSCEIVER (3-STATE IINV.)
T640AP/AF
OCTAL BUS TRANSCEIVER (3-STATE)
643AP/AF
T643PIF
646P
T646P
648P
OCTAL BUS TRANSCEIVER (3-STATE)
T643AP/AF
646AP
T646AP
648AP
TC74HC T648P
65lP
T651P
652P
T652P
688P/F
4002P/F
4075PtF
T7007PIF
7266P/F
OCTAL BUS TRANSCEIVER IREGISTER (3-STATE)
OCTAL BUS TRANSCEIVER !REGISTER (3-STATE)
OCTAL BUS TRANSCEIVER IREGISTER (3-STATE IINV.)
OCTAL BUS TRANSCEIVER IREGISTER (3-STATE IINV.)
OCTAL BUS TRANSCEIVER IREGISTER (3-STATE IINV.)
OCTAL BUS TRANSCEIVER IREGISTER (3-STATE I INV.)
OCTAL BUS TRANSCEIVER IREGISTER C3-STATE)
OCTAL BUS TRANSCEIVER !REGISTER (3-STATE)
8-BIT EQUARITY COMPARATOR
TC74HC
T648AP
651AP
T651AP
652AP
T652AP
688AP/AF
4002AP/AF
4075AP/AF
DUAL 4-INPUT NOR GATE
TRIPLE 3-INPUT OR GATE
T7007AP/AF
7266AP/AF
HEX 8UFFER
QUAD EXCLUSIVE NOR GATE
HC-11
2.
HIGH
GATE
SPEED
CMOS
SELECTION
GUIDE
HCOOA HCTOOA HC03A HCIOA HC20A HC30A HCl32A HCl33A
HC02A HCT02A HC27A HC4002A HC4078A
AND
HC08A HCT08A HC09A HCllA HC21A
OR
HC32A HCT32A HC4072A HC4075A HC4078A
INVERTER, BUFFER
HC04A HCT04A HCU04", HC05A HC07A HCl4A HC4049A
HC4050A HCT7007A
EXCLUCIVE OR I NOR HC86A HCT86A HC266A HC386A HC7266A
SCHIMITT TRIGGER
HCl4A HC132A
MULTI FUNCTION
HC51A
LEVEL SHIFTER
HC4049A HC4050A
NAND
NOR
FLlp·FLOP
BUS BUFFER
HC125A HC126A HC240A HCT240A HC241A HCT241A HC244A
HCT244A HC365A HC366A HC367A HC368A HC540A HCT540A
HC541A HCT541A HC7240A HC7241A HC7244A
BUS TRANSCEIVER
HC242A HC243A HC245A HCT245A HC620A HC623A HC640A
HCT640A HC643A HCT643A HCG46A HCT646A HC648A HCT648A
HC651A HCT651A HC652A . HCT652A HC7640A HC7643A HC7645A
J-K FLIP-FLOP
HC73A
D FLIP-FLOP
HC74A HCT74A HC174A HCT174A HC175A HC273A HCT273A HC377A
3-STATE
LATCH
HC76A
HCI07A HCI09A HC1l2
HC1l3A
HC374A HCT374A HC534A HCT534A HC564A HCT564
HC574A HCT574 HC646A HCT64GA HC648A HCT648A
HCG51A HCTG51A HC652A HCT652A
HC75A HC77A HC259A HC279A HC375A
3-STATE
HC373A HCT373A
HC573A HCT573
HC533A
HCT533A HC5G3A HCT563
MULTI VIBRATOR
HC4538A
DECODER
HC42A HC131A HC137A HCT137 HC138A HCT138A HC139A
HC154A HC155A HC237A HC238A HC4028A HC4514A HC4515A
7-SEGMENT
HC123A HC221A HC423A
HC45llA HC4543A
ENCODER
HC147A HC148A
REGISTER
HC164A
HC299A
COUNTER
MULTIPLEXER
HCTIG4A HC165A HC16GA HC173A HC194A HC195A
HC323A HC595A HC597 A HC4094A HC670A HC40105A
BINARY
HC161A HC163A HC191A HC193A HC393A HC590A HC592
HC593A HC69 1 HCG93 HC697 HCG99 HC4520
DECADE
HC160A HC162A HC190A HC192A
HC696 HC698 HC4518
DIVIDER
HC4017 HC4020A HC4022 HC4024A
HC40102 HC40103 HC7292 HC7294
ANALOG
HC4051A
DIGITAL
HC151A HC153A HC157A HCT157A
HC253A HC257A HCT257A HC258A
HC353A HC3S4A HC356A
HC4052A
ANALOG SWITCH
HC4016A HC4066A
COMPARATOR
HC85A HC688A
ADDER
HC283A
ALU
HC181
PARITY TREE
HC283A
HC4053A
HC390A HC690
HC692
HC4040A HC4060A
HC4351A
HC4352A
HC4353A
H0158A HCT158A
HCT258A H0298A
H0251A
HC352A
HC4316A
HCT688A
HC182A
Including under development type number
HC-12
GATE
Type
74HC 00
74HC TOO
74HC 03
74HC 10
74HC 20
74HC 30
74HC 133
74HC 02
74HC T02
74HC 27
74HC4002
74HC4078
74HC 08
74HC T08
74HC 09
74HC 11
74HC 21
74HC 32
74HC 32
74HC4075
74HC4072
74HC4078
74HC 04
74HC T04
74HC U04
74HC 05
74HC 51
74HC 86
74HC T86
74HC 266
74HC7266
74HC 386
74HC 14
74HC 132
Equivalent
Function
Number
LSTTL
Equivalent
CMOS.
LSOO
4011, 7400
QUAD 2-INPUT NAND GATE
4011, 7400
LSOO
QUAD 2-INPUT NAND GATE
LS03
QUAD 2-INPUT NAND GATE (OPEN DRAIN)
*40107,*5029
TRIPLE 3-INPUT NAND GATE
LSI0
4023
DUAL 4-INPUT NAND GATE
LS20
4012
8-INPUT NAND GATE
LS30
4068
13-INPUT NAND GATE
LS133
L502
4001
QUAD 2-INPUT NOR GATE
LS02
4001
QUAD 2-INPUT NOR GATE
LS27
4025,*4000
TRIPLE 3-INPUT NOR GATE
4002
*LS25
DUAL 4-INPUT NOR GATE
8-INPUT OR/NOR GATE
4078
QUAD 2-INPUT"AND GATE
LS08
4081
QUAD 2-INPUT AND GATE
LS08
4081
4081
QUAD 2-INPUT AND GATE (OPEN DRAIN)
LS09
4073
TRIPLE 3-INPUT AND GATE
L$l1
4082
DUAL 4-INPUT AND GATE
LS21
LS32
4071
QUAD 2- INPUT OR GATE
LS32
4071
QUAD 2-INPUT OR GATE
4075
TRIPLE 3-INPUT OR GATE
4072
DUAL 4-INPUT OR GATE
4078
8-INPUT OR/NOR GATE
LS04
HEX INVERTER
*4069U
HEX INVERTER
LS04
*4069U
HEX INVERTER (SINGLE STAGE)
*LS04
4069U,7404U
HEX INVERTER (OPEN DRAIN)
*LS04
*4069U
DUAL 2W-2I AND/OR INVERT GATE
LS51
*4085
4030
QUAD EXCLUSIVE OR GATE
LS86,LS386
LS88,LS386
4030
QUAD EXCLUSIVE OR GATE
4077
QUAD EXCLUSIVE NOR GATE (OPEN DRAIN)
LS266
4077
QUAD EXCLUSIVE NOR GATE
*LS266
QUAD EXCLUSIVE OR GATE
LS86,LS386
4030
4584
HEX SCHMITT INVERTER
LS14
QUAD 2-INPUT SCHMITT NAND
LS132
4093
* Suggested alternative
GATE
QUAD 2-INPUT NAND GATE
00
TOO
Positive logic
VOC 4.B
1A
1B
4A
1Y
y = AB
4y 3B 3A
2A
2B
2Y
QUAD 2-INPUT NOR GATE
02
T02
Positive logic
3y
GND
HC-13
Y = A+B
Pin
·Number
14
14
14
14
14
14
16
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
·14
GATE (Continued)
QUAD 2-INPUT NAND GATE WITH OPEN DRAIN HEX INVERTER
OUTPUT
04
05
03
T04
U04
Positive logic: Y AS
Positive logic:
vee
4.8
4A
4Y
38
3A
Y
3Y
1A
1Y
2A
2Y
3A
3y
GND
---·---·---------+----------------1
QUAD 2-INPUT AND GATE
TRIPLE 3-INPUT NAND GATE
08 09
T08
10
Positive logic:
vee
lA
4A
lB
lY
Y = AB
Positive logic:
4,Y 3B
3A 3Y
2A
2Y GND
2B
vee
1A
Y = ABC
1e
1Y
3e
1B
2A
2B
TRIPLE 3-INPUT AND GATE
HEX SCHMITT INVERTER
11
14
Positive logic:
vee
1Y
Y ABC
3e
3B
3A
Positive logic:
vee 6A
3Y
lA
HC-14
lY
3B
20
3A
2y
3Y
GND
Y=A
6Y
5A
2A
2y
5y 4A
:!Y
4Y
OIID
GATE (Continued)
·DUAL 4-INPUT NAND GATE
DUAL 4-INPUT AND GATE
20
21
Positive logic;
Ne
1A
Positive logic:
Y = ABCD
1B Ne Ie
2B
2A
2Y
1D 1Y
OND
vee 2D
1A
2e
1B Ne
TRIPLE 3-INPUT NOR GATE
8-INPUT NAND GATE
27
30
1A
113
vee
3B
2B
2C
2Y
vee
4B 4A
4Y
3B
2A
:elY
10
1Y
OND
1D
Ne
H
G
NO
Ne
Y
ABeDEFOND
OND
QUAD 2-INPUT OR GATE
32
T32
Positive logic: Y = A+B
Ne 2B
Positive logic: Y = ABCDEFGH
Positive logic: Y = A+B+C
Ie
Y = ABCD
DUAL 2 WIDE-2 INPUT AND/OR INVERT GATE
51
Positive logic: lY=lA·1B·1C+1D·1E·1F
2Y=2A·2B+2C·2D
3A 3Y
HC-15
vee 10
1B
1A
2B. 20
2A
IF
IE'
ID
lY
2D
2Y
OND
GATE (Continued)
QUAD 2-INPUT EXCLUSIVE-OR GATE
86
T86
Y=A~B=AB+AB
Positive logic:
vee
45
4A
4,Y
15
1Y
35
QUAD 2-INPUT SCHMITT NAND GATE
132
Positive logic: Y = AS
vee
!lA 3Y
45 4A
lA
1A
2A
25
2Y
A
5
LKJ
e
D
E·
G
386
veo
45
]A
15
4A
lY
4Y
2Y
3Y
25
GND
QUAD 2-INPUT EXCLUSIVE-NOR GATE
7266
Positive logic:
vee
45
lA
15
4A
Y=A~B=AB+AB
4Y
3Y
3S
3A
2Y
2A
25
GND
eND
QUAD 2-INPUT EXCLUSIVE-OR GATE
Positive logic:
2A
3A
266
IHY
F
lY
35
GND
13-INPUT NAND GATE
133
Positive logic: Y=ABCDEFGHIJKLM
VCC)/
15
4Y
Y=A~B=AB+AB
lY
DUAL 4-INPUT NOR GATE
4002
Positive logic: Y=A+B+C+D
3Y
35
3A
vee
2Y
2A
25
GND
lY
lA
HC-16
15
Ie
2e
20
NO
10
Ne
GND
GATE (Continued)
DUAL 4-INPUT OR GATE
4072
Positive logic: Y=A+8+C+D
vee
1Y
2D
1A
1B
20
2B
10
TRIPLE 3-INPUT OR GATE
4075
Positive logic: Y=A+8+C
2A
NO
VOO
NO
aND
2A
8-INPUT NOR GATE
4078
Positive logic: Y=A+8+C+D+E+F+G+H
vee
Y
x
H
0
F
E
NO
ABO
D
NO
OND
HC-17
30
3B
3A
3y
1A
1B
10
2Y
lY
20
OND
BUFFER
Type
Number
Equivalent
LSTTL
Function
74HC
07
74HCT7007
74HC4049
74HC4050
74HC 125
74HC 126
74HC 240
74HCT240
74HC 241
74HCT241
74HC 244
74HCT244
74HC 365
74HC 366
74HC 367
74HC 368
74HC 540
74HCT540
74HC 541
74HCT541
74HC7240
74HC7241
74HC7244
74HC 242
74HC 243
74HC 245
74HCT245
74HC 620
74HC 623
74HC 640
74HCT640
74HC 643
74HCT643
74HC7640
74HC7643
74HC7645
HEX BUFFER
HEX BUFFER
HEX BUFFER (INVERTING)
HEX BUFFER
QUAD BUS BUFFER
QUAD BUS BUFFER
OCTAL BUS BUFFER (INVERTING)
OCTAL BUS BUFFER (INVERTING)
OCTAL BUS BUFFER
OCTAL BUS BUFFER
OCTAL BUS BUFFER
OCTAL BUS BUFFER
HEX BUS BUFFER
HEX BUS BUFFER
(INVERTING)
HEX BUS BUFFER
HEX BUS BUFFER
(INVERTING)
OCTAL BUS BUFFER (INVERTING)
OCTAL BUS BUFFER (INVERTING)
OCTAL BUS BUFFER
OCTAL BUS BUFFER
OCTAL BUS BUFFER (SCHMITT IN)
OCTAL BUS BUFFER (SCHMITT IN)
OCTAL BUS BUFFER (SCHMITT IN)
QUAD BUS TRANSCEIVER (INVERTING)
QUAD BUS TRANSCEIVER
OCTAL BUS TRANSCEIVER
OCTAL BUS TRANSCEIVER
OCTAL BUS TRANSCEIVER (INVERTING)
OCTAL BUS TRANSCEIVER
OCTAL BUS TRANSCEIVER (INVERTING)
OCTAL BUS TRANSCEIVER (INVERTING)
OCTAL BUS TRANSCEIVER
OCTAL BUS TRANSCEIVER
OCTAL BUS TRANSCEIVER (INVERTING)
OCTAL BUS TRANSCEIVER
OCTAL ~US TRANSCEIVER
Equivalent
CMOS.
LS07
*LS07
LS125
LS126
LS240
LS240
LS241
LS241
LS244
LS244
LS365A
LS366A
LS367A
LS368A
LS540
LS540
LS541
LS541
LS240
LS241
LS244
LS242
LS243
LS245
LS245
LS620
LS623
LS640
LS640
LS643
LS643
LS640
LS643
LS245
4049
4050
5024
5025
5012
Pin
Number
14
14
16
16
14
14
20
20
20
20
20
20
16
16
16
16
20
20
20
20
20
20
20
14
14
20
20
20
20
20
20
20
20
20
20
20"
* Suggested alternative
BUFFER
HEX BUFFER
QUAD~BUS
07
T7007
125
Positive logic : Y = A
Vee CIA
C!Y
SA
4.A
BUFFER
Positive logic : Y = A
4.Y
1'0 ,lA 1Y - 2'0 2A 2Y OND
HC-18
BUFFER (Continued)
QUAD BUS BUFFER
OCTAL BUS BUFFER (INVERTING)
126
Positive logic: Y A
10 lA lY
20 2A
240
T240
2Y GND
OCTAL BUS BUFFER
QUAD BUS TRANSCEIVER (INVERTING)
241
T241
242
GAB
NO
lA
QUAD BUS TRANSCEIVER
OCTAL BUS BUFFER
243
244
T244
2A
2B
8B
SA
t.A
OND
lYl 2M lY2 2AS lY8:wa l"tf, 2Al
GAB NO
lA
2A
SA
t.A
HC-19
BUFFER (Continued)
OCTAL BUS TRANSCEIVER
245
T245
G
B1
DlR A1
.... 2
1&2
B3
B4.
HEX BUS BUFFER
365
B.5
B6
B7
B8
All
A7
A8
GND
lA
A4
lY
HEX BUS BUFFER (INVERTING)
HEX BUS BUFFER
366
367
Vvc ii2
6A
Veo
6Y
G2
2A 2Y
3A
3Y GND
SA
SY
5A
5Y
4A 4Y
lY
2A
2Y
3A
aND
OCTAL BUS BUFFER (INVERTING)
540
T540
HEX BUS BUFFER (INVERTING)
368
Veo G2 Yi Y2 Y3 Y4. Y5 Y6 Y7 is
6
iil
1A
2A
iY
3A
A2
GND
HC-20
A3 A4 A5
1
A6 A7 A8 GND
BUFFER (Continued)
OCTAL BUS BUFFER
OCTAL BUS TRANSCEIVER (INVERTING)
541
T541
620
ENABLE GSA
CIT
A1
y1 Y2 y3
Y~
A2 A3 A4
A5 A6 A7 AB GND
OCTAL BUS TRANSCEIVER
Y5 Y6 Y7 YB
Vee
I
B6
B1 B2
B7
BB
OCTAL BUS TRANSCEIVER (INVERTING)
623
640
T640
BNABLE GAB
G
B1
B2
B3
B4
B6
B6
B7
BB
DIR A1
A2
A3
A4
A5
AS
A7
AB
OIID
OCTAL BUS TRANSCEIVER
HEX BUFFER/CONVERTER (INVERTING)
643
T643
4049
Vee
HC-21
1Y
1A
2Y
2A
3y
3A
OIID
BUFFER (Continued)
HEX BUFFER/CONVERTER
OCTAL BUS BUFFER (INVERTlNG)
4050
7240
Veo
lY
lA
ay
IA
3Y
:!A
GIlD
OCTAL BUS BUFFER
OCTAL BUS BUFFER
7241
7244
Vee
IG lYl lA' I n 2A3 lY:! 2A2 I n IAl
Vee 10 lYl lA' 1 Y2 aM lY3 lAB In. &Al
lAl I n lA2 aY3 lA:! In· lA' an GND
10 lAl ay, lAI 2Y3 lA3 an lA' In GND
OCTAL BUS TRANSCEIVER (INVERTING)
OCTAL BUS TRANSCEIVER
7640
7643
Vee
0
Bl
B8
B3
B'
B6
BO
B?
B8
Veo
0
Bl
B2
B3
B4
B5
Be
DIR
Al
A2
A3
A4
A6
NJ
A?
A8
GND
DIR
Al
A2
A3
A'
A3
AS
A?
B?
B8
AS !lND
BUFFER (Continued)
OCTAL BUS TRANSCEIVER
7645
Veo
0
B1
Ba
sa
I!&
ill
a.
B'P
DIR
A1
All
A3
A&
All
A'
A"
AI ctMD
•
HC·23
FLIP-FLOP
Type
74HC
74HC
Equivalent
Function
Number
73
76
14
16
WITH CLEAR
WITH PRESET
LS107A,LS73A
14
WITH PRESET
LS76A,LS112A 4027,7476
74HC 74
74HC T74
74HC 174
74HCT174
74HC 175
74HC 273
74HCT273
74HC 377
74HC 374
74HCT374
74HC 534
74HCT534
74HC 564
74HCT564
74HC 574
74.HCT574
74HC 646
74HCT646
74HC 648
74HCT648
74HC 651
74HCT651
74HC 652
74HCT652
DUAL D F/F WITH PRESET AND CL~AR
DUAL D F/F WITH PRESET AND CLEAR
HEX D FLIP-FLOP WITH CLEAR
HEX D FLIP-FLOP WITH CLEAR
QUAD D FLIP-FLOP WITH CLEAR
OCTAL D FLIP-FLOP WITH CLEAR
OCTAL D FLIP-FLOP WITH CLEAR
OCTAL D-TYPE FLIP-FLOP
OCTAL D-TYPE FLIP-FLOP (3-STATE)
OCTAL D-TYPE FLIP-FLOP (3-STATE)
OCTAL D-TYPE FLIP-FLOP (3-STATE/INV. )
OCTAL D-TYPE'FLIP-FLOP (3-STATE/INV. )
OCTAL D-TYPE FLIP-FLOP (3-STATE/INV.)
OCTAL D-TYPE FLIP-FLOP (3-STATE/INV. )
OCTAL D-TYPE FLIP-FLOP (3-STATE)
OCTAL D-TYPE FLIP-FLOP (3-STATE)
OCTAL BUS TRANSCEIVER/REGISTER
OCTAL BUS TRANSCEIVER/REGISTER
OCTAL BUS TRANSCEIVER/REGISTER (INV .)
OCTAL BUS TRANSCEIVER/REGISTER (INV .)
OCTAL BUS TRANSCEIVER/REGISTER (INV .)
OCTAL BUS TRANSCEIVER/REGISTER (INV. )
OCTAL BUS TRANSCEIVER/REGISTER
OCTAL BUS TRANSCEIVER/REGISTER
WITH PRESET
LS109A
16
LS113A
4013
4013
40174
40174
40175
LS374,LS574
LS374,LS574
LS534
LS534
LS564
L8564
LS374,LS574
LS374,LS574
LS646
LS646
LS648
LS648
LS651
LS651
LS652
LS652
DUAL D FLIP-FLOP WITH PRESET AND
CLEAR
73
IQ
10 GND
2K
20
'2Q
74
T74
vec 2CLR 2D
20K
2PR
20
2Q
1CLR 1D
'iPR
10
10
GND
10K
14
14
16
16
16
20
20
20
20
20
20
20
20
20
20
20
24
24
24
24
24
24
24
24
Suggested alternative
FLIP-FLOP
DUAL J-K FLIP-FLOP WITH CLEAR
16
14
LS74A
LS74A
LS174
LS174
LS175
LS273
LS273
*
1J
Number
LS73A,LS107A
LS76A,LS112A 4027,7476
74HC 113
74HC 112
Pin
WITH CLEAR
WITH PRESET
DUAL J-K FLIP-FLOP
DUAL J-K FLIP-FLOP
AND CLEAR
DUAL J-K FLIP-FLOP
DUAL J-K FLIP-FLOP
AND CLEAR
DUAL J-K FLIpwFLOP
AND CLEAR
DUAL J-K FLIP-FLOP
74HC 107
74HC 109
Equivalent
CMOS.
LSTTL
FLIP-FLOP (Continued)
DUAL J-K FLIP-FLOP WITH PRESET AND
CLEAR
DUAL J-K FLIP-FLOP WITH CLEAR
107
76
1Q
10 ONO 2K
2Q
2CLR 2CK 2J
2J
B
1Q
1J
lK
2Q
GNO
DUAL J-K FLIP-FLOP WITH PRESET AND
CLEAR
DUAL J-K FLIP-FLOP WITH PRESET AND
CLEAR
109
112
VCC 1CLR 2CLR iii 2K 2J
1CLii 1J
lit 10K
1PR
1Q
1Q
1CK
ONO
1K. 1J
IPR lQ
iii
DUAL J-K FLIP-FLOP WITH PRESET
HEX D FLIP-FLOP WITH CLEAR
113
174
Tl74
vee 2iiK
2K
ICK
1J
1K
ffi
lQ
iii
GNO
vee
6Q
ClEAR lQ
HC-25
6D
10 20
2Q OND
CLOCK
2Q
3D
3Q
GND
FLIP-FLOP (Continued)
QUAD D FLIP-FLOP-WITH CLEAR
175
vec 4.Q
CLEAR lQ
4.a
40
Hi 10
so
sa
20 211
OCTAL D FLIP-FLOP WITH CLEAR
273
T273
SQ OLOOE
vee
BQ
BO 'l'0
'l'Q
6Q 60
50
2Q aND
OCTAL D FLIP-FLOP (3-STATE)
374
T374
OCTAL D FLIP-FLOP
377
vee BQ Bo 'l'0 'l'Q
OCTAL D FLIP-FLOP (3-STATE/INV.)
534
T534
6Q
60 50 5Q~
OCTAL D FLIP-FLOP (3-STATE/INV.)
564
T564
HC-28
OCTAL BUS TRANSCEIVER REGISTER
(3-STATE)
574
T574
646
OCTAL BUS TRANSCEIVER REGISTER
(3-STATE/INV. )
OCTAL BUS TRANSCEIVER REGISTER
(3-STATE/ INV.)
648
T648
651
T651
OCTAL BUS TRA.NSCEIVERS REGISTER
(3-STATE)
652
T652
SBLBOT.
oUlCl[~
Voo SA
&lA Bl B2 S5 84. B5 B8 rn sa
I
HC~27
LATCH
Type
Function
Number
74HC 75
74HC 77
74HC 259
74HC 279
74HC 375
74HC 373
74HCT373
74HC 533
74HCT533
74HC 563
74HCT563
74HC 573
74HCT573
Equivalent
Equivalent
LSTTL
CMOS.
LS75
LS77
LS259
LS279
LS375
LS373,LS573
LS373,LS573
LS533
LS533
LS563
LS563
LS373,LS573
LS373,LS573
4-BIT D-TYPE LATCH
4-BIT D-TYPE LATCH
8-BIT ADDRESSABLE LATCH
QUAD S-R LATCH
QUAD D-TYPE LATCH
OCTAL D-TYPE LATCH (3-STATE)
OCTAL D-TYPE LATCH (3-STATE)
OCTAL D-TYPE LATCH (3-STATE/INV. )
OCTAL D-TYPE LATCH (3-STATE/INV. )
OCTAL D-TYPE LATCH (3-STATE/INV.)
OCTAL D-TYPE LATCH (3-STATE/INV. )
OCTAL D-TYPE LATCH (3-STATE)
OCTAL D-TYPE LATCH (3-STATE)
Pin
Number
*4042
*4042
*4099
*4043,*4044
16
14
16
16
16
20
20
20
20
20
20
20
20
* Suggested alternative
LATCH
4-BIT LATCH
4-BIT LATCH
75
77
FUNCTION TABLE
OUTPUTS
INPUTS
Q;
Q.
G
D
L
H
H
H
X
L
10
20
FUNCTION TABLE
INPUTS
CUTPUTS
D
Q.
G
Q.
X:DON'T
CARE
L
H
L
H
Q.n
L
H
H
H
H
Q;n
X
L
Q.n
2Q 01·2
OND
3Q 30 40
10
L
X:DON'T
CARE
H
L
Q;n
2001.2 OND NO
3Q
1
10
10
10 2003·4 Vee 30 400
200304 Vee 3D 4.0 4.'0
8-BIT ADDRESSABLE LATCH
QUAD S-R LATCH
259
279
FUNCTION TABLE
OUTPUT
INPUTS
8'" R
Q.
H
H
H
Q.n
H
L
L
L
L
H
L
H
* FOR
LATCHES WITH
DOUBLE S INPUTS:
H=BOTH S INPUTS
HIGH
L=ONE OF BOTH
INPUTS LOW
40'S' 4.'Ii 400 352351
ABC
00
01
Q2
NO
3R 30
03 OND
1R lSl 182 10 aR a8 20 GND
HC-28
LATCH (Continued)
OCTAL LATCH (3-STATE)
373 NON INVERTED DATA OUTPUTS
T373
O?
06 06 05 05
QUAD LATCH
375
04
10
Oil
00
00 01 01
02 02 03
OCTAL LATCH (3-STATE)
533 HlVERTED DATA OUTPUTS
T533
O?
06 06
Q5
iQ"
10 01·2 20
20
20
ONO
Q3 OND
OCTAL LATCH (3-STATE)
563 INVERTED DATA OUTPUTS
T563
05 04 Q4 LE
1
iiE
OCTAL LATCH (3-STATE)
573 NONINVERTED DATA OUTPUTS
T573
00
OE
01
02
Q3
04
05 06
00 01
02
03 04 05
os
O? QND
HC-29
00
01
02
03
04
P5
06
07 OND
MULTIVIBRATOR
Type
74HC 123
74HC 221
74HC 423
74HC4538
DUAL
DUAL
DUAL
DUAL
HONOSTABLE
HONOSTABLE
HONOSTABLE
HONOSTABLE
Equivalent
Equivalent
LSTTL
Function
Number
HULTIVIBRATOR
HULTIVIBRATOR
HULTIVIBRATOR
HULTIVIBRATOR
CMOS.
LS123
LS221
LS423
*LS423
1rc4538.*4528
*4538.*4528
*4538.*4528
4538. 4528
Pin
Number
16
16
16'
16
*Suggested alternative
MUlTIVIBRATOR
DUAL RETRIGGERABlE MONOSTABlE MUlTIVIBRATOR
123
DUAL MONOSTABlE MUlTIVIBRATOR
221
FUNCTION TABLE
INPUTS
FUNCTION TABLE
OUTPUTS
CLEAR
A
B
Q.
Q.
L
H
H
H
H
X
H
X
L
X
X
L
L
L
L
H
H
H
S
H
L
H
DON T CARE
'1.
S
X.
Jl
INPUTS
v
J\.
V
J\.
"lJ"
OUTPUTS
Q.
B
Q
X
L
X
L
H
H
H
X
L
H
H
X
L
L
H
H
L
j
l'l
V
J'l.
H
H
V
"l.
.n. 'IJ'
S
H
L
X • DON T CARE
1l\V'ox
veo
lOx 2Q iQ 20LR 28
CLEAR
A
,
8
2Cx2~ OIID
18
iCLR iQ
DUAL RETRIGGERABlE MONOSTABlE MUlTIVIBRATOR
DUAL RETRIGGERABLE MONOSTABlE MUlTIVIBRATOR
423
4538
FUNCTION TABLE
INPUTS
A
CLEAR
B
L
X
X
X
H
H
X
L
H
H
I
H
H
X • DON T CARE
t
1l\V'ex
veo
iA
lOx
18 rcLii
FUNCTION
OUTPUTS
1Q
20 2cLii
iQ
2Q
TABLE
INPUTS
OUTPUTS
Q.
Q.
Cli
A
li
Q.
L
L
L
J1.
l'l
H
H
H
V
V
L
H
H
H
H
X
H
X
L
X
X
L
L
L
L
11.
l'l
28
.r
1.
H
X : DON T CARE
Voe 20fl 2'1'2 2Cii ~
2A
HC-30
Q.
H
H
H
V
V
I
2i
2Q
~
DECODER
Type
Number
Equivalent
LSTTL
Function
74HC 42
74HC 131
74HC 137
74HCTl37
74HC 138
74HCT138
74HC 139
74HC 154
74HC 155
74HC 237
74HC 238
74HC4028
74HC4514
74HC4515
74HC4511
74HC4543
BCD TO DECIMAL DECODER
3-TO-8 LINE DECODER/LATCH
3-TO-8 LINE DECODER/LATCH
3-TO-8 LINE DECODER/LATCH
3-TO-B LINE DECODER
3-TO-8 LIN~ DECODER
DUAL 2-TQ-4 LINE DECODER
4-TO-16 LINE DECODER
DUAL 2-TO-4 LINE DECODER
3-TO-8 LINE DECODER/LATCH
3-TQ-8 LINE DECODER
BCD-TO DECIMAL DECODER
4-TO-16 LINE DECODER/LATCH
4-TO-16 LINE DECODER/LATCH
BCD TO 7 SEGMENT L/D/D(LED)
BCD TO 7 SEGMENT L/D/D (LCD)
Equivalent
CMOS.
LS42
LS131
LS137
LS137
LS138
LS138
LS139
LS154
LS155
*4028
4556,*4555
*4515
*4556,*4555
*LS154,*LS159
*LS154,*LS159
tS47 ,tS48JS49
*~f>47,LS48,LS4
*
* f9
4028
4514
4515
4511
4543
I
Pin
Number
16
16
16
16
16
16
16
24
16
16
16
16
24
24
16
16
* Suggested alternative
DECODER (Continued)
BCD TO DECIMAL DECODER
3-TO-8 LINE DECODER/LATCH
42
131
OIID
YO
A
3-TO-8 LINE DECODER/LATCH
137
Y1
i2
ABe
OL
vee YO
Y3
02
Y4.
01
01
B
3-TO-8 LiNE DECODER
138
T138
Y"{;
17
vee YO
Y6
A
OIID
HC-31
B
Y1
e
Y2
Y3 n
02A 028 01
Y5
Y6
Y7
OND
DECODER (Continued)
4-TO-16 LINE DECODER
154
DUAL 2-TO-4 LINE DECODER
139
2Yii 2Yl 2Y2 ffl
vee
20
IG
1A 1B lYC lYl lY2lY3 OND
2A
2B
:;
W Yi. y.a "iii "Y' "'i5jS Y? "il"W"m
3-TO-8 LINE DECODER/LATCH
DUAL 2-TO-4 LINE DECODER
3-TO-8 LINE DECODER
155
237
yl
le
IG
ABe
B lY3 lY2 lYl lYC OND
Yl
ABe
Y2 Y3
02A
y2
y3 Y4.
OL
y:;
01 Y7 GND
BCD-TO-DECIMAL DECODER
4028
3-TO-8 LINE DECODER
238
Vee YO
eN)
n
G2B Cll
Y:; Y6
Y3 Yl
BeD
Y2
Y7 Y9
A
Ys
Y7 ClND
Y40
HC-32
YO
Y5
Y6 GIlD
DECODER (Continuea)
BCD TO 7 SEGMENT LATCH/DECODER/DRIVER 4-TO-16 LINE DECODER/LATCH
4511
4514
.B
e
gab
0
d
8
iii
D
A
OND
LT
LB
4-TO-16 LINE DECODER/LATCH
4515
INHIBIT
Veo
STROBE. A
8lO all 8s Sg 8]4, S15 8]2 8]3
D
0
B
8'7 86 85 a, 8a 81 S2 BO GND
BCD-TO-7 SEGMENT LATCH/DECODER/LCD
DRIVER
4543
LD
HC-33
0
B
D
A
PI!
Bl
GND
ENCODER
Type
Number
Equivalent
LSTTL
Function
74HC 147 10-TO-4 LINE PRIORITY ENCODER
74HC 148 8-TO-3 LINE PRIORITY ENCODER
LS147
LS148
Equivalent
CMOS.
*4532
Pin
Number
16
16
* Suggested alternative
ENCODER
10-TO-4 LINE PRIORITY ENCODER
147
~---,,-'-:--.,..
8-TO-3 LINE PRIORITY ENCODER
148
OUTPUT
INPUTS
HC-34
REGISTER
c
Illl
t
Equivalent
LSTTL
Function
74HC 164
74HCTl64
74HC 165
74HC 166
74HC 173
74HC 194
74HC 195
74HC 299
74HC 323
74HC 595
74HC 597
74HC 670
74HC4094
8-BIT SIPO SHIFT REGISTER
8-BIT SIPO SHIFT REGISTER
8-BIT PISO SHIFT REGISTER
8-BIT PISO SHIFT REGISTER
QUAD D-TYPE REGISTER (3-STATE)
4-BIT PIPO SHIFT REGISTER
4-BIT PIPO SHIFT REGISTER
8-BIT PIPO SHIFT REGISTER
8-BIT PIPO SHIFT REGISTER
8-BIT SHIFT REGISTER/LATCH (3-STATE)
8-BIT LATCH/SHIFT REGISTER
4 WORD x 4-BIT REGISTER FILE (3-STATE)
8-BIT SIPO SHiFT REGISTER/LATCH
(3-STATE)
Equivalent
CMOS.
LS164
*4034
LS164
*4034
LS165
*4014,*4021
LS166
*4014,*4021
LS173
4076
LS194A 40194,*40104
LS195A
*4035
LS299
*4034
LS323
*4034
LS595
LS597
LS670
4094
Pin
Number
14
14
16
16
16
16
16
20
20
16
16
16
16
* Suggested alternative
REGISTER
8-BIT SERIAL-IN/PARALLEL-OUT SHIFT
REGISTER
164
Tl64
8-BIT PARALLEL-IN/SERIAL-OUT SHIFT
REGISTER
165
SERIAL
B
QlI
.OG
OF
QIi"
A
INPUT QH
CLEAR 0L00lC
QC
QD
8-BIT PARALLEL-IN/SERIAL-OUT SHIFT
QUAD "0 FLIP-FLOP (3-STATE)
166
173
DATA IiIIABLB
l'
SBRIAL A
IN
B
IlDIm"
-----II
B
N
1Q
OIlTPllT CONTROL
He-3S
INPU'1'S
.-----
20 30
4.D
02
1)1
2Q 3Q
'Q ClDCll:ClID
REGISTER (Continued)
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT
REGISTER
194
QA
~c
';"
QD CLOCK 81
4-BIT PARALLEL-IN/PARALLEL-OUT SHIFT
REGISTER
195
vce
So
QA
OB
QC
CD
Qi'l CLOOK ~~~~/
9
3
CLEAR
ABC
SHIFT
D SHIFT
LEFT
21/0
B J.>B A=B A<.8 OIID
QASat.D& IIlPllTS
G pO 00 p1 01 P2 02 p3 03 OIID
OIl'l'Pirrs
ADDER
Type
Number
74HC 283
Equivalent
LSTTL
Function
4-BIT BINARY FULL ADDER
LS283,LS83
ADDER
4-BIT BINARY FULL ADDER
283
B2
A2
A1
B1
co
OIID
HC-46
Pin
Number
Equivalent
CMOS.
4008
..
16
ALU
Type
Number
Equivalent
LSTTL
Function
74HC 181 ARITHMETIC LOGIC UNIT
74HC 182 LOOK AHEAD CARRY LOGIC
Equivalent
CMOS.
Pin
Number'
24
16
L8181
L8182
ALU
ARITHMETIC LOGIC UNIT/FUNCiION
GENERATOR
*:
181
LOCK AHEAD CARRY GENERATOR
182
OPIiN DRAIN OUTPUT
Vee
Pi ii2
OD OlltxOD+y
Q
OD+1I
16
AD a:s
S2
81
BO
OD
Y
i6 iiI ii
OND
PARITY TREE
Type
Number
Function
74HC280
9-BIT PARITY GENERATOR/CHECKER
Equivalent
LSTTL
PARITY TREE
9-BIT ODD/EVEN PARITY GENERATOR/
CHECKER
280
, HC-47
L8280
Equivalent
CMOS.
*4531
Pin
Number
14
3.
PRODUCT OUTLINE OF THE TC74HCxxxA SERIES
The TC74HCxxxA series is an improved High Speed Logic development of TOSHIBA. Some of these
improvements are outlined below:
(l)
Increased Speed of Operation:
Over 20 companies now manufacture the 74HC series worldwide. The JEDEC JC40.2 comJ;llittee
has standardized the electrical characteristics of this series in JEDEC Standard 7A. This permits
interchangeability of devices between manufacturers for greater end-user convenience. Increasing
the speed of the TC74HCxxxA series by an average of 20% to 30% ensures compatibility with Standard
7A as well as with most other worldwide 74HC products. TOSHIBA achieved the higher speed by
using a thinner gate oxide layer and by decreasing the effective channel length and the internal
parasitic capacitance to increase transconductance (gm) per unit channel width by 30% over that of the
original series.
(2) Latch-up Strength:
TOSHIBA had previously improved the TC74HC series to make it latch-up resistant. By using the
same process, the TC74HCxxxA revision also has a high resistance to latch-up; TOSHIBA high
speed C~OS products can be used in applications in which noise and surges often occur.
Table 3-1 shows the results of latch-up tests.
Ta'ble 3-1 Results of Latch-up Tests ••
TC74xxx series
TC74xxxA series
method
pin
TC74HCOOP
TC74HC74P
Current Injection
(static trigger)
Input
>±70mA.
>±70mA.
>±300mA
>±300mA
Output
>±300mA
Charge Injection
(dynamic trigger)
TC74HCOOAP TC74HC74AP
>±3OOmA
>±300mA
>±3OOmA
Input
>±250V
>±250V
>±250V
>±250V
Output
>±250V
>±250V
>±250V
>±250V
Power supply
>±250V
>±250V
>±250V
>±250V
• Input protection resistor limits current
•• See Fig. 9-14 Latch-up s'trength measurement system in Sect. 9-7.
HC-48
(3) Electrostatic Discharge:
In the original TC74HCxxx series. TOSHIBA designed in an input protective circuit which
combines silicon diodes with a polysilicon series resistor (Fig. 3-1(a». This circuit suppresses
excess current flow in the input terminal when the input voltage is higher than Vr:r, or lower than
GND. This circuit is effective for increased latch-up protection. but the electrostatic discharge
protection. measured using the MIL-STD method (I00pF/1.5kohms). was about ±2.0kV maximum.
Anything above this caused bur.n damage to the polysilicon resistor or increased breakdown of the
oxide film directly under the polysilicon.
As there is no latch-up problem with the TC74HCxxxA series. TOSHIBA uses a protective circuit composed of high
thermal capacity silicon diodes and a resistor constructed by diffusion (Fig. 3-1(b) . According to MIL-STD. any product not
reaching a :t 2.0kV level must carry an ESD Sensitive (ESDS) label. TOSHIBA's TC74HCxxxA series far surpasses this level
with a 2.0kV or greater rating using the MIL method.
Table 3-2 shows the Electrostatic Discharge Test Results.
Fig. 3-1 The Input Protective Circuits
Input
(a)
(b)
TC74HCxxx series
TC74HCxxxA series
HC-49
Table 3-2 ESD Teat Reault
(al MIL Method (C=lOOpF ,R= 1.5KC)
TC74 HCOOP
TCT4HCOOAP
x
x
2K
lK
(b)
EIAJ Method (C=200pF ,R=OC)
TC74HCOOP
TC14HCOOAP
Destruction
• Normal
• Destruction
..t. Discharge stopped
(el Teat Circuit
He-50
voltage
3-1 Feature.
High Speed Operation:
Same as LSTTL
Low Power DissipatiQn:
Same as standard CMOS series ( p. W)
Output Drive Capability: Capable of directly driving 10 LSTTL loads (Standard output type).
Capable of directly driving 15 LSTTL loads (Buffer output type).
Hi~h
Noise Immunity'
HC/HCU Type ... 45l\! Vee (Typ.)
HCT Type ......... 25l\! Vee (Typ.)
Wide Operating Voltage Range:
'HC/HCU Type ... 2to 6V
.
HCT Type .. ;.. ~ ... 4.5 to 5.5V
Wide Operating Temperature Range:-40 to + 85"C
Self-contained static electricity protective circuit:
±500V (typ.) by EIAJ method
±3000V (typ.) by MIL STD method
(All inputs and outputs)
Ample Latch up Capacity: Total input and output ±300 mA and above.
Based on the same pin connection and function with LSTTL.
and line up with CMOS original version.
Wide product
Li~e
up: Over 200 types
Table a-2 shows' C\!lmparrson of characteristics of various logic families.
HCL
(TC74HCxxxA)
Parameter
Propagation Dalay Time
6ns typ
(Cl =16pF)
GATE
Maximum Clock Frequency 80MHz typ
J/KF' F (Cl=16pF)
Qul_nt Power Di"ipetion O.Olp.W typ
(GATE)
Input Voltage
O",tput Current
VIH
a.5V min
Vll
1.5V max
IIOHI
4mA minol
IOl
4mAmin
Operating Voltage Range
2-6V
Operetlng Tempereture Ring,
-40-85"C
LSTTL
HS-C2MOS
(TC40Hxxx)
CZMOS
(TC4xxx)
9ns typ
15ns typ
65ns typ
45MHz typ
20MHz typ
2MHz typ
8mW typ
0.01 p. W typ
2.0V min
4.0V min
a.5V min
D-70"C
-40-85"C
-40-85"C
Condition
Vee=5,OV
Ta=25"C
0.01 p.W typ Over temperature
and voltage range
Vee =5.0V
Over temperature
0.8V max
1.0V max
1.5V max range
0.4mA min.2 O.36mA min.a 0.42mA min.a .1 Vee=4.5V
.2 Vee=4.75V
·a Vce=5V
4mAmin
O.SmA min 0.42mA min Over
temD. rana
" 2-8V ~
4.75-6.25V
a-18V
Table a-2 Comparison of Logic Family Characteristics
He-51
3-2
Method of Designating the TC74HC Series
The TC74HC series Is designated by using the standard established by JEDEC and is as shown below;
TC74HCD
L-=:J 0
0
0
1~
6) Other information (as required)
5) Package Type (P,F,FN,FW)
4) Revision Level (blank for original)
3) Function
2) Type classification by JEDEC
(74HC. 74HCU, 74HCT)
1) TOSHIBA CMOS
(designates TOSHIBA
and process)
(ExampJe) TC74HCT240AP
High Speed C2MOS IC which is pin and functionally compatible with the bipolar 74LS24,O
Input is designed for TTL voltage levels. and direct driving from LSTTL is possible.
Package type is plastic Dual Inline Package (DIP).
(1)
"TC·
Proprietary name identifying TOSHIBA CMOS devices.
(2) Type classification (HC, HCU, HCT)
In addition to the HC devices, there are HCU and HOT types. These differentiations were made by JEDEC in order to
separate CMOS devices of the same function by with different input levels or the existence of a buffpr
TYPE
Internal stages
Input threshold voltage
HC
Two stages and above
CMOS level
HCU
One stage
CMOS level
HCT
Two stages and above
TTL
He-52
level
Taking an inverter as an example. we can show the difference between these types as follows:
Logic Diagram
Input-Output
Voltage transfer
eha raeteristies
TC74HC04A
TC74HCU04A
--{>--{:>o-{>-
--I>-
TC74HCT04A
--{>--{:>o-{>-
'itL 'tL 'VL
2.5V
2.5V
-VIN
1.4V
(3) Function
Functions are expressed by Arabic numbers of two to five figures.
In the case of TC74HC series. these numbers are the same as LSTTL and 4OOOB/4500B devices having
the same pin connections and function.
00-999
......... Product with same pin connections and function as 74LS series.
(Example) 74LS240-74HC240
4000-40199 ......... Product with same pin connection and function standard
4500-4599
CMOS 4OOOB/4500B series.
(Example) 40102B-74HC40102
4300-4399 ......... Function unique to 74HC series.
7000-7999
However. some function approaches LSTTL or 4000B series.
(Example) Same function with 74HC7266A-74LS266.
However. output is of normal buffer structure (Not open drain).
(4) Revision Level
This symbol is used to clarify the revision of product when improvements which change the characteristics of product are
made. Normally, it is blank, however, upon revision, English characters are given successively from ''A''. Suffix ''A'' of
TC74HCxxxA series indicates the types which have refmedAC characteristics due to redesign ofIC chip but still meetJEDEC
standards for the family.
He-53
IS) Package Type
English characters showing type or Package.
P ..•••••.• dual in line package (DIP) Plastic
F········· 200 mil small outline Ie (SOIC) Plastic
FN •.•.....• 150 mil small outline Ie (SOle) Plastic
FW •.••• •••• 300 mil small outline IC (SOIC) Plastic
In the TC74HC series, narrow 300 mil type 24 pin DIP package have been developed. Therefore all P type. 14116120124 pins
devices have a 300 mil width (7.62 rom).
(6) Other information
As an example, in the case of SOIC 'Illpe and Reel specifications, the following suffixes are added to the part number.
(TP 1) or (TP 2)
Adhesive 'Illpe and Reel (Difference in pin 1 position)
(EL)
Embossed'Illpe and Paper Reel.
(ELP)
Embossed 'Illpe and Plastic Reel for 15012001300 nlu SOIC
He-54
4.
EXPLANATION OF RATINGS AND STANDARDS
4-1 Maximum Ratingl
In general, the maximum rating value should not be exceeded in order to guarantee the life and
reliability of integrated circuit products.
The Absolute Maximum Rating should not be exceeded even for a moment.
When the device is used in-excess of any maximum rating, the device may not recover, and, in many
cases, permanent damage will occur.
In designing the circuit, tilerefore, it is necessary to pay attention to the fluctuation of supply
voltage, characteristics of interconnecting parts, ambient temperature, and surges in input and
output signal lines, so that the maximum ratings will not be exceeded.
Thble 4-1 indicates common absolute maximum ratings of the TC74HC series. When the maximum ratings and common
ratings differ, the former shall control. For definition of parameters, refer to Thble 4-2.
Table 4-1 Absolute Maximum Ratinge
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
SYMBOL
Vee
V IN
Voor
11K
Ia<
DC Output Current
Ioor
DC Vee IGround Current
lee
Power Dissipation
Storage Temperature
Lead Temperature 10sec
Po
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25 (standard type)
±35 (buffer type)
±50 (standard type)
±75 (buffer type)
500(DIP)*/180(SOIC)
-65 -150
300
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
* SOOm W in the range of Ta=-40"C- 65"C. From Ta=65"Cto 85"C
a derating factor of-10m WI"C shall be applied until 300m W.
He-55
Table 4-2
Parameter
Explanation
Symbol
Supply Voltage
Vee
The voltage range In which the IC does not present breakdown, deterioration
of characteristics or reduced reliability.
DC Input Voltage
DC Output Voltage
VIN
VOUT
The voltage range in which the IC does not present breakdown, deterioration
of characteriatics or reduced reliability.
Input Diode Current
Output Diode Current
11K
10K
DC Output Current
DC Vee/Ground Current
lOUT
lee
Output current indicates the current value which can flow from one output.
As VcdGND current includes output current, in an IC having many output
terminals, substantial VcclGND current can flow.
Power Dissipation
Po
indicates power consumption which exceeded can cause breakdown of the
device over the entire operating temperature range.
Tllg
The ambient temperature range over which deterioration of characteristics
and reliability will not occur when left for a long time In a state without
aupply voltage.
Storage Temperature
Lead Temp. and Time
4-2
TL
The current value at which the IC does not present breakdown due to latchup when input or output current flows.
• Practically, a deaign in which DC current flows is not recommended. When
a flow of current cannot be prevented, adopt a current value lower than this.
Indicates the maximum allowable conditions permitted when soldering Is
carried out after IC mounted on printed board.
Recommended Operating Conditions
These are the conditions in which the operation of the TC74HC series is guaranteed, and when exceeded, operation is not
guaranteed even though they are within the maximum rating of 'Th.ble 4-1.
Common, recommended operating conditions of the 74HC series are shown in 'Th.ble 4-3. When recommended operating
conditions for specific devices and common recommended operating conditions differ, the former shall control. Refer to 'Th.ble
4-4 for defmitions.
Table 4-3 Common Recommended Operating Conditions
(a)
74HC Type
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Yo:;
VIN
Voor
Topr
tr , tr
VALUE
2-6
0- Yo:;
0- Yo:;
-40 - 85
0- 1000(Vo:;=2.0V)
0- 500(Vo:;=4.5V)
0- 400(Vo:;=6.0V)
He-56
UNIT
V
V
V
"C
ns
(b) 74HCT Type
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Va:;
VIN
VCXJT
Topr
t r , tr
VALUE
4.5 - 5.5
0- Va:;
0- Va:;
-40 - 85
0-500
UNIT
V
V
V
"C
ns
Table 4-4
Parameter
Symbol
Explanation
Supply Voltage
Vee
The supply voltage range guaranteeing normal operation of the IC.
Input Voltage
Output Voltage
VIN
VOUT
The input/output voltage range guaranteeing normal operatiori of the IC.
Operating Temperature
Topr
The operating temperature range guaranteeing normal operation and
electrical characteristics of the IC.
Input Rise and Fall Time
tr . tf
4-3
DC
id
The rise and fall time range of the input signal which will not cause
oscillation of the output.
characteristics
Thble 4-5 shows the DC characteristics of HC types. For the meaning of each parameter, refer to Thble 4-7. Thble 4-5 is a
standard DC characteristics table, and when it differs from individual characteristics, the later shall control. DC characteristics are established by JEDEC (Standard 7A). Thble 4-6 indicates characteristics table standardized by JEDEC.
He-57
Table 4-5 TC74HC series DC Characteristics Table
PARAMETER
High~Level
InpJlt Voltage
SYMBOL
VIH
Low-Level • •
Input Voltage
VIL
High-Level • •
Output Voltage
Vm
Low-Level
Output Voltage
Va.
.3 -/State Output
Off State Current
ICE
input Leakage Current
lIN
Quiescent Supply Current·
TEST CONDITION
lee
VIN=
VlHorVIL
VIN=
VIHorVIL
1m =-20IlA
rn --4 m~
1m =-5.2m~
Ia. =20 Il A
Ia. =4 rnA·
Ia. =5.2mA·
V IN V IH or V IL
Voor -Vee or GND
VIN -Vee or GND
I GATE
VIN=
IFF
VeeorGND
I MSI
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
6.0
60
Note) • Buffer Type assumes 1.5 times value, respectively.
(1100 1=1oL=6mA, 7,8mA)
•• Items guaranteed to exceed JEDEC standard 7A.
He-58
Ta 250C , ..... Ta. 40 ,,:,,85"C UNIT
MIN. TYP. MAXi MJN. ,MA.~.
1. 5..
, l,,,p. ,',
y.
3.15
3.15
4.2
4.2
0.5
0.5
V
1. 35
L 35
1.8
J.8.
1.9
2.0
1.9
4.4
4.4
4.5
6.0
5.9
.V
5.9
4.13, ,
4.31
4.18
5.80
5.63
5.68
0.0
0.1
0.1
0.0
0.1
0.1
V
0.0
0.1
111
0.17
;0.26
3~
.•. O. 33
0.18
0.26
±0.5
.;t,S,O
,
':',
;;'"
- ". 0:
+0.1
1.0
2.0
40
.:
+1.0
0'" " Ilf..
20.0
" 40<0 "'1, .;.,'.'
"10~
Table 4-1 .rIDle Standard No.7A (DC EI!ICtrical characteristics)
PARAMETER
SYMBOL
TEST CONDITION
Hich-Level
Input Voltap
VIH
Low-Level
Input Volt...
VIL
Hich-Level
Output Voltap
VOl
VIN=
VIHorVIL
Low-Level
Output Voltap
Va.
VIN=
VlHorVIL
a-State Output
Off-S&ate Current
Input ..... eulftllt
1m
q.u.m.....,c.n.t
Icc
11]\1
101 =-20/l A
1101 --4 rnA·
101 =-5. 2rnA
1(1. =20 /lA
1(1. =4 rnA
1(1. =5.2rnA·
VIN ",:VIH or VIL
Varr =Vcc orGND
~IN -'\fCC or UNlJ
GATE
VIN=
FF
VccorGND
MSI
Vcc
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
6.0
60
Note) • Buffer Type ....m.. l.& times value. respectively.
<11ot1-Ia.=tmA.7.8mA)
He-59
Ta 25t:
Ta
40 -85"C UNIT
MIN. TYP. MAx. MI.l'I_. MAX.
1.5
1.5
V
3.15
3.15
4.2 -4.2
0.3
0.3
V
0.9
0.9
12
1.2
1.9
1.9
4.4
4.4
V
5.9
5.9
3.98
3.84
5.48
5 34
0.1
0.1
0.1
0.1
V
0.1
0.1
0.26
0.33
0.26
0.33
-
-
-
-
-
-
±0.5
+0.1
2.0
4.0
80
-
-
-
±5.0
+1.0
20 0
40 0
so. 0
/lA
Table 4-7
Paranieter
Symbol
Explanation
High-Level
Input Voltage
VIH
The input voltaga capable of setting the Input of the IC to a high level, and: the
minimum value is guaranteed.
Low-Level
Input Voltage
VIL
The Input voltage capable of setting the Input of the IC to a low level, and the
maximum value Is guaranteed.
High-Level
Output Voltege
VOH
The output voltage such that when each Input terminal Is connected to VIH or VIL, the
corresponding output level goes high. There Is guaranteed a minimum value of
output voltage obtainable when the specified output current (loH) flows.
Low-Level
Output Voltage
VOL
The output voltege such that when esch Input terminal Is connected to VIH or VIU the
corresponding output level goes low. In this case, thltre Is guaranteed a maximum
value of output voltage obtainable when the specified .output current loJ flows.
Input Leakage
Current
liN
This is the current flowing at the input terminel when a voltage is impressed on
the input terminal of IC. Normally, this current is 80 small that meaiurement is
made with the maximum value of supply voltags.
3-State Output
Off-State Cu rrent
loz
The leakage current flowing at the output terminal when the output Is In a high
Impedance state, the device having a three ltate or open drain, output.
Quiescent Supply
Current
Icc
The current flowing from the Vce terminal Into the IC when the Vee or GND level Is
held constant without changing the input voltage. The maximum value under all
theoretical conditions allowable for the measurttd IC Is guaranteed.
He-60
4-4
AC Characteristics
AC characteristics guarantee the transient characteristic of products.
In general, impressed input waveform is set so as to have an amplitude of Vcr; to GND and rise and
fall time of 6ns.
Table 4-8 explains the meaning of each parameter of the AC characteristics, Fig. 4-1 shows the
output connection diagrams for measurement and Fig. 4-2 illustrates the measured waveforms.
Table 4-8
Parameter
Symbol
Explanation
Output Transition Time
tTlH
tTHl
Indicates the time during which the output voltage (VOH' VoJ rises
from 10% to 90%, and the time during which the output voltage falls
from 90% to 10%.
Propagation Time
tplH
tpHl
Indicates the time between input Signal application and output
responae detection. XLH is the case in which the output changes from
low level to high leve , and tpHL is the case in Which the output
changes from high level to low.
Output Disable Time
tplZ
tpHZ
Indicates the time between when a signal is applied to the output
control terminal and when the 3 state output is set to a high
impedance state.
Output Enable Time
tpZl
tpZH
Indicates the time, between when a signal is applied to the output
control terminal and when the 3 state output switches go a low or high
level from the high Impedance state.
",..imum Clock Frequlney
fMAX
Indicate. the maximum frequency at which the IC operate.
normally.
Timing requirements are a prerequisite to the normal function of devices. (See Table 4-9)
He-61
Drawing NO.
HC
HCT
( i)
(iv)
(iii)
(vi)
(if)
(v)
Table 4-9
Parameter
Drawl", NO.
He HeT
Explenation
Symbol
Minimum Set-up Time
ta
Regarding certain data, Indicates the time which the data muat be
applied and held before the Input regarding that data (clock, ate.)
changes. For example, when the data Is read In at a rise of next
clock pulse, It Is necessary to apply andhold that data before the
rising edge of the clock pulse, to a value at IHat equal to the
minimum value of ta.
Minimum Hold Time
h
Regarding certain data, Indicates the time which the data muat be
held after the Input regarding that data (clock, atc.) has changed.
Minimum Removal Tim.
t rem
Indicates the minimum time betwean releasing of an asynchronous
Input (clear, preset, etc.) and application of next Input (clock, etc.).
Minimum Pul.. Width
tw
Indicates the minimum pulse width that a clock input, etc. i.
acceptable as· a normal signal.
(II)
f
Clock Frequency
Perameter
(v)
Indicates the clock frequency .that i. operated the Ie normally.
Symbol
Explanation
Input Capacitance
CIN
Indicates the capacitance between input and GND.
Output Capacitance
COUT
Indicates the capacitance associated with a 3 state output or a open drain output
in the.high impedance state.
Fig. 4-1 Output Connection Diagram
Measurement
Point
Vee
Vee
Measurement
Point
0
To output
Terminal
-1
lCL
CMOS Output
Note)
., fRL
RL Measurement
Point
To output
Terminal
To output
Terminal
lCL
Open Drain Output
CL includes the capacitance
of probe, etc.
He-62
lCL
3 State Output
!RL
Fig. 4-2 Switching Characteristics Thst Wavefonns
(1) HC '!YPes
i)
t
TLH. ; t THL
Ir
• t pLH
• t pHL
Sns
'INPUT
GND
INVERTING
OUTPUT
He-S3
iii )
t pLZ
,t pHZ
,t pZL
,t pZH
- n-
~o"
OUTPUT
DISABLE
-r
90"~
tpLZ
TO
OFF
GND
VOH
~
LOW
TO
Vee
tpZL
,
~
HIG H
OUTPUTS
ENABLED
50"
~
VOL (,.GND)
tpZH
tpHZ
OUTPUT:
HIGH TO
tr6ns
1oiii
.....l
OUTPUT:
LOW TO OFF
-
J
OUTPUTS
DISABLED
VO H "(Vee)
~O"
VOL
OUTPUTS
ENABLED
(2) HCT 1YPes
iv)
tTLH
,tTHL
,t pLH
,t pHL
i-----~~~----------3V
INPUT
" ' - - - - - - - GND
OUTPUT
~--+-~-~---------VOL
He-54
V)
6ns ....
Ir
T THe
,
6ns
90"
CLOCK
INPUT
I
l.3V
DATA
INPUT
Ih(}-l)
,
J
th (L)
1\ 1.3V
--..J
Is (}-l)
Is (L)
-IjtTLH
.,.
Tto-
I--<
l.3V
IpLH
OL
IpHL
3.0V
Jr\.3V
GND
Inactive
Active
Stale
vi)
GND
V
"'\,
SET,RESET
or PRESET
3.0V
ITHL
10"
--=
~
Jt
90"
"'
OUTPUT
t rem
GND
Iw(}-l)
tw(L)
,
a·Dev
"' ~
.IO~
state
t pLZ ,t pHZ ,t pZL ,t pZH
Ir
6ns
6ns
3V
OUTPUT
DISABLE
GND
VOH
OUTPUT:
LOW TO OFF _L;;",,;,O..
W_...._'1
l.3V
OUTPUT:
HIGH TO
L3V
VOL ( .. GND)
VOH ( .. Vee)
OFF
HIGH
OUTPUTS
ENABLED
OUTPUTS
DISABLED
He-55
OUTPUTS
ENABLED
6. EXPLANATION OF IEC LOGIC SYMBOLS
&-1 Symbol composition
A symbol comprises an outline or a combination of outlines together with one or more
qualifying-symbols. The purpose of a general qualifying symbol is to accurately portray the logic
function of the device.
general quarifyi.ng symbol
outline
input
!ilkS
{
*: qualifying
**
**
* *
* *
} output
lines
symbol locations for inputs and outputs
&-2 Qualifying Symbols
(1)
General Qualifying Symbols
symbol
definition
&
AND element
).1
OR element
=1
EXCLUSIVE OR element
=
Logic identify element. If all inputs have the same logic state then the output is et
internal loge "'" .
2K
2K+1
1
[> or
definition
Logic nagation at an input. An external logic "0"("1") productS an internal logic "1"("0").
Logic nagation at an output. An internal logic "0" (",") productS an external logic "'" ("0").
Porlarity indicator at an input. A "L" (Low) level active.
Porlarity indicator at an output. A "L" level active.
Porlarlty Indicator at an Input where the signal flow Is from right to left.
Porlarlty Indicator at an output where the signal .flow Is from right to left.
Indicator for di rection of signal flow.
Bidirection inlormation flow (alternate).
Dynamic input
Positive logic.
O--.r-1
Negative logic.
Porlarity indicate.
O~1
L--.r- H
Tha above transitions produce the internal logic active.
--cp.
Dynamic input
Positive logic.
1~O
Negative logic.
1--.r-°
The above transitions produce the internal logic active.
Dynamic input
-4>
Porlarity indicate.
H~L
The above transitions produce the internal logic active.
~
Non-logic connection.
~
Input for analog signals.
(3) Symbols of the internal connection
symbol
:::c:
=r
:I:
£=:
=:J
definition
A logic "1" at the left-hand side produces a logic "0" at the right-hand side.
·Negated internal connection. A logic "I" at the left-hand side produces a logic "0" at
the right-hand side.
DynamiC internal connection. A transition from internal logic "0" to internal logic
"1" at the left -hand side produces a transistory logic "'" at the right~hand side.
Internal input (virtual). This input is always at internal logic "1" state unless this is
overridden or modified.
Internal output (virtual). This effect on the internal input connected to this output
mUlt be indicated by dependency notation.
He-68
(4) Symbols inside the outline
symbol
il--Lff
definition
Delayed output. The output change is delayed until the input that indicated the
change returns to its initial external state or level.
Schmitt trigger input.
O~
Open-drain output without internal pulled-up resistor.
~~
Open-drain output with internal pulled-up resistor.
O~
Open-source output without internal pulled-down resistor.
~~
Open-source output with internal pulled-down resistor.
Vf--
ThrH-'state output.
l>f----1 EN
J.K.D
R.S.T.C
Buffered output.
(The triangle pOints in the direction of signal flow)
Enable input.
Information inputs of disable elements.
Control inputs of disable elements.
+m.+m
Shift input. The direction of shilt is to the right or down when the arrow points to the right. or
to the left. "m .. =1.2.3 .. ··• however. the number may be omitted when "m"=1.
-j+m,-j-m
Counting input. Count-up or count-down are indicted by + and - re.pectively.
The number "m" is the count per command and may be omitted when "m"='.
~: }
--\CT=m
CT=9f--
==1]
-1"1","1"1-
Bit-grouping symbol.
"m" is the highest power of 2 in the group.
Content input.
The internal logic"'" sets the element to the value" m" .
.Content output. For example. when the input state is "'., the internal ragistor sets
"9" .
Line-grouping symbol. The inputs enclosed by this symbol from a singlillogic input.
Fixed-mode input. Fixed-state output. This input (output) is permanently at
internal logic "'" .
5-3 Dependency Notation
Dependency notation is the powerful tool that makes IEC Logic Symbols compact and yet meaningful. With IEC symbols, the
relationships between inputs and outputs are clearly illustrated without the necessity of showing all elements and
interconnections involved.
In dependency notation, the terms "affecting" and "affected" are used.
(1)
These general rules applied to dependency notation:
1) The input (or output) affecting other inputs or outputs is labelled with the letter symbol that indicates the relationship
involved followed by an appropriately chosen identifying number.
2)
Each input or output affected by that affecting input (or output) is labelled with that same
number.
3)
If it is the complement of the input's (or output's) internal logic state that does the affecting,
then a bar is placed over the identifying numbers at the affected inputs or outputs.
4)
If the affected input or output has a label to denote its function, this label will have the identifying
number of the affecting input as a prefix.
5)
If two affecting inputs or outputs have the same letter and the same identifying number, they are
ORed together.
6)
If the labels denoting the function of affected inputs or outputs are numbers (example: outputs of a coder), the identifying
number of both affecting inputs and affected inputs or outputs is replaced by another character selected to avoid ambiguity,
e.g., Greek letters.
7)
If an input or output is affected by more than one affecting input, each identifying number separated by a comma will appear in
the label of the affected one. The normal order of reading these numbers is the same as the sequence of the affecting
relationships.
HC-70
Fig. 5-1 Example for dep'endency notation
identifying
number
dependency symbol
affected
output
affe.cting --,--. a
Input
L..,. b
/.
affecting
:
affected
inputs
(2)
........>--................
)ut:~ftected
input_ c
with
dependency symbol
identifying
number
d
!
identifying
number
dependency
symbol
Symbols for dependency notation
function
AND
OR
symbol
G
V
Input State "1"
Permits ection
Imposes "1" state
Input State "0·
Imposes "0" state
Permits action
Negate
(EX-OR)
N
Complements state
No effect
Interconnection
Control
Set
Re..t
Enable
Z
C
S
R
EN
Imposes action
Permits action
S=1, R=O
S=O, R=1
Permits action
Permits action
Prevents action
No effect
No effect
Prevents action of input
Mode
M
Permits action
(mode selected)
Prevents action
(mode not selected)
Addresa
A
Permits action
(Address aelected)
Prevents action
(Addreaa not selected)
HC-71
6.
HOW TO READ MIL TYPE LOGIC SYMBOLS AND TRUTH TABLES
6-1
How to read MIL type Logic Symbols
Table 6-1 shows the MIL type logic symbols used in high-speed CMOS IC. This logical chart is based on MIL-STD-806B.
Clocked inverters and transmission gates employ specific symbols.
Table 6-1 MIL Logic Symbols
Circuit Function
Logic Symbol
Logical Equation or Truth Table
Inverter
A-<{>--X
A--{>o-X
X=A
NAND Gate
~=D-X
~::D--x
X=A oB=A+B
NOR Gate
~:::r:::»-x ~ ::::o-x
X=A+B=A oB
AND Gate
A
::::[)--X
B
~~X
,X=A 0 B=A+B
OR Gate
A
B
A
B:::::3:J-X
X=A+B=A
::D-x
-
Clocked Inverter
(Note 1)
Transmission Gate
(Note 2)
----
-----
r/>
A-{>f-X
r/>
r/>
H
H
L
A
H
L
X
X
L
H
Z
A4x A4x
r/>
H
H
L
A
H
L
X
X
H
L
Z
r/>
A-t>f-X
r/>
r/>
r/>
0
B
X:Don'tCare
Z:High
Impedance
.'" Care
X:Don't
Z:High
Impedance
--
EXCLUSIVE-OR
Gate
~::lD-x
X=(A+B)
EXCLUSIVE-NOR
Gate
~
X=(A 0 B)+(A 0 B)
D-Type
Flip-Flop
S
D~ ~=$~
CK
~Q
Q CK
(A+B)
- -
:::ll>--x
S
0
KR Q
R
HC·72
Q
S
H
L
L
L
L
R
L
H
L
L
L
D
X
X
H
L
X
CK
X
X
S
S
t..
Q
H
X:Don't
L
Care
H 6:No
Change
L
IQn6
Table 6-1 (Cont'd)
Circuit Function
Logic Symbol
S
s
'0'
J/K Type
Flip-Flop
CK
K
CK
K R
R
Logical Equation or Truth Table
Q Q
~QQ
CK
K
CK
K R
Q Q
R
S
H
L
L
L
L
L
L
R
L
H
L
L
L
L
L
J
X
X
L
L
H
H
X
K
CK
X
X
L
H
L
H
X
X
X
S
S
S
S
t..
Q
H
L
Qn6
L
H
Qn'V
Qn6
X:Don't Care
6:No Change
'V: Toggle
Note 1) Clocked Inverter
A clocked inverter has the circuit shown in Fig. 6-1. In this figure, Ql
and Q2 are P-channel MaS FET, and Q3 and Q4 are N-channel MaS
FET, and the four FET are connected in series from Vee to GND.
If 0 signal is high, Ql and Q4 tum on, and the circuit can be regarded
as simply an inverter composed of Q2 and Q3. When 0 signal is low,
both Ql and Q4 tum off, and, regardless of the condition of the A input,
A~
B
the output, B is set to a high impedance condition cut off from both Vco
andGND.
That is to say, a clocked inverter can be used as a
switch to turn off input and output.
Fig. 6-1 Clocked Inverter
Note 2) Transmission Gate
A transmission gate has the circuit shown in Fig. 6-2. As shown, Ql is a
P-channel MaS FET and Q2 is an N-channel Mas FET which are
connected in parallel.
Vee
14>
I
~
If 0 signal is high, both Ql and Q2 tum on, and a signal can be applied I N / O U T .
in either direction.
If 0 signal is low, both Ql and Q2 tum off, and no signal can be
passed.
OUT/IN
TQ2
¢>
GND
Fig. 6-2 Transmission Gate
HC-73
8-2 How to Read Truth Table
Table 6-2 indicates the definition of symbols described in Truth Table.
Table 6-2
Symbol
definition
H
High level (Indicates stationery input or output)
L
Low level (Indicates stationary input or output)
S
Indicates leading edge changing from "L" to "H" .
~
Indicates trailing edge changing from" H· to "L".
X
Don'tcate (Either"W or "L")
Z
High impedance state
a······h
Input level of stationary state of each input of A to H.
Qo
Level of Q just before the realization of input condition indicated in Truth Table.
Qn
Level of Q just before inputting of active edge
.sL
One" H· level pulse.
LJ
One "L" level pulse.
HC-74
( .f
or
1.)
7.
COMMON ELECTRICAL CHARACTERISTICS
7-1
Power Dissipation
The power dissipation of CMOS device is composed of two components: one static, the other
dynamic.
The total power dissipation is the sum of static and dynamic power dissipation.
Static power dissipation is obtained by multiplying quiescent supply current by the supply voltage
range (Paragraph 7-1-(1).
Dynamic power dissipation is obtained as shown in paragraph 7-1-(2).
(I)
Static power dissipation
In the case of CMOS ICs, under the condition in which the inputs are fIxed at Vee or .GNDlevel,eitherthe
N-channel FET or P-channel FET turns off. For this reason, the current from V CC to GND
becomes only the reverse-direction saturated current of the PN junction and the surface leakage
current due to the strain in the chip surface, and is a current of less than several nA at room
temperature.
Therefore, where the inputs are driven by another CMOS, or the inputs are pulled-down to GND or pulled-up to Vcc the
static power dissipation can be obtained as follows:
P d (DC) = V CC • ICC
For HCT devices where specific input pins are driven at LSTTL levels the following applies:
When being driven with a TTL VOH ' HCT devices exhibit additional currents
(~Icc)asspecifIedon
HCT device data sheets.
Therefore, the HCT static power dissipation is dependent on the number of inputs to which TTL VOHlogic
voltage levels are applied and can be obtained as follows:
Pd(DC)=V cc • ICC +nVcc • len • dn
n : the number of input at 0-2.4V (TTL VIH level)
d: duty cycle
~Icc:
quiescent current when V1H = 2.4V
(Ref. Technical data sheets)
HC-75
(2) Dynamic power dissipation
The dynamic power dissipation of aMOS IC is calculated by summing "a" and "b" below:
a)
The switching current obtained by charge and discharge of each capacitance added to gate output
current when the gate in the circuit including the output buffer makes an inversion.
b)
The through current flowing when the P-channel FET and the N-channel FET which constitute
the gate during inversion time turn on briefly at the same time:
When rise and fall times of the input signal are small (about 6ns), through current of the gate is
usually negligibly small in comparison with the switching current.
For this reason, the dynamic supply current is governed by internal capacitance of the IC and the
charging and discharging current of the load capacity (C L).
An example is given here for C L
= OpF.
For the inversion of the internal gate outputs from low to high, it is necessary that the electric charge corresponding to Ci •
Vcc line to the internal capacitance Ci.
Therefore the value obtained by multiplying Ci • Vcc and the output inversion freguency (Frequency
=f) within a certain
period corresponds to the mean current to be supplied from the Vee line to the IC during that period.
In an actual IC however, several gates operate simultaneously, and their respectiw internal capacity and inversion frequency
are different.
Therefore, dynamic supply current in an IC is as follows:
Icc (opr.)
= Vcc
n
• 1: fn • Ci n
I
fn: frequency of internal operated gate
As fn is divisible by an integer of input frequency (fll,), the gate operating ",;th fn/m frequency can be considered equivalent
to the capacitance of Cilm.
Therefore, the above equation can be rewritten as:
ICC (opr.) = V CC of
n
r'·
1:I Citmn
.
fE\ : input frequency
m: integer
The final term is defined as CpD .
HC-76
Dynamic power dissipation with load capacity is given by the following equation:
PD (opr.) = Cpo. Va;2 • fIN • Cpo
Total dynamic power dissipation with load capacity is given by the following equation:
C L : load capacity
f 0 : output frequency
n : integer of output
However, in specific applications such as crystal oscillators, supply current characteristics are controlled by through
current, and calculation by Cpo can not be used.
HC-77
7-2 Standardized Capacitance Power Dissipation (CPD) Talt Procedure
The purpose of the CpD value is to allow the user to estimate actual power consumption of his system. Therefore, the
table has been set up to exercise each device in the same manner as it would usually be used. Devices which are
separable into independent sections are measured on a "per section" basic, the remaining are measured on a "per
device" basis. Eac,h device's unique set up is listed in the Thble 7-1, "CPO Test Conditions".
Measurements for all devices are to be made at Vee =5.0V at Th = 25'C and, if the devices are tested at a high
enough frequency, the DC supply current will contribute a negligible amount to the overall power consumption and
can be ignored. For this reason, the power consumption is measured at IMHz. Any device with 3-state outputs is
measured in an enabled state.
In order to determine the Cpo of a single section of a device (Le. one of four gates or one of two flip-flops in a package), the
following procedures should be used:
As for the Cpo value for devices with a common clock, it can be easily obtained by measuring both the Cpo of the device with
only one portion of the device active, and the Cpo found with all portions active. The Cpo value obtained by above two
conditions should be shown.
Gates:
Switch one input while biasing the remaining input(s) so that the output(s) will
switch.
Flip-flops:
Switch the clock pin while changing the data pin(s) such that the output(s)
change with each clock cycle.
Latches:
Switch the enable and data inputs such that the latch toggles.
Decoders/
Demultiplexers:
Switch one address input which changes two outputs.
Date selectors/
Multiplexer,,'
Switch one address input with the corresponding data inputs at opposite logic
levels so that the output switches.
HC-78
Analog switches:
Switch one address/select input/output which changes two switches. The switch inputs/outputs
should be left open For digital applications where the switch inputs/outputs change between Vee
and GND, the respective switch capacitance should be added to the load capacitance as shown
above.
Counters:
Switch the clock with the other inputs biased so that the device counts.
Shift registers:
Switch the clock while alternating the inputs so that the device shifts
alternation l's and O's through the register.
Transceivers:
Switch only one data input. Place transceivers in a single direction.
Monostables:
The pulse obtained with a resistor and -no external capacitor is repeatedly
switched.
Parity Generators: Switch one input.
Display Drivers:
Switch one input so that approximately one-half of the outputs change state.
ALUsI Address:
Switch the least significant bit. Bias thil remaining inputs so that the device is
alternately adding OOOO(binary) or 000l(binary) to l11l(binary).
Details of each Ie's pin condition are listed in Table 7-1.
-Explanation of symbolV = Vee (+5.0V)
G =GND (0 V)
H = logic 1 (Vee )
L = logic 0 (GND)
X = don't care. Vee or GND. but not switching
R = 1.0 kQ pull-up resistor to an additional5.0V supply other than Vee supply
0= open
P = 5001 duty cycle input pulse (shown below)
Q = 50" duty cycle half frequency out-of-phase input pulse (shown below)
Vee
L-----'~ND
p
Vee
J
Q
GND
Input Pulse Waveform
HC-79
Table 7-1
C pD Test Condition
Pin
Type
No.
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4
00
02
03
04
08
10
11
14
20
21
27
30
32
42
51
PHOXXOGOXXOXXV·
•
• •
OPLOXXGXXOXXOV.
P HRXXOGOXXOXXV·
P OXOXOGOXOXOXV.
P H 0 X X- e- G 0 X X 0 X X V •
PHXXXOGOXXXOHV·
• •
• •
PHXXXOGOXXXOHV·
P 0 XO X 0 G 0 X 0 X 0 X V •
PHOHHOGOXXOXXV·
PHOHHOGOXXOXXV
PLXXXOGOXXXOLV·
•
PHHHHHGOOOHHOV·
PLOXXOGOXXOXXV·
o 000 0 0 0 GOO 0 L L L P V •
•
PXXXXOGOLLLHHV·
PHHVXXXOOXGOOH·
•
HQPHOOGOOXXXXV.
•
•
0 Q X X V X X 0000 G P.O 0 0
PHHHVXXXXOOXGOOH·
QXXVXXOOOOGPOO
•
LHPHOOOGLLLLLLLV·
PLOXXOGOXXOXXV
HOOHOOGXXXXPHV
HHLPHOOGOOXXXXXV
•
PHHHOOOGOXXXXXHV·
PHHHOOGOOXXXXV
• •
LHPOOOOGXXXOOORV
•
73
74
75
76
77
85
86
107
109
112
113
123
125
126
131
132
133
137
138
139
147
148
151
153
··· ··· ·· ·· ··· ·· ··· ··· ···
··· ··· ·· ·· ··· ··· ··· ·· ··
·· ·· ·· ·· ·· ·· ·· ·· ·
··
·
·
·
·
·
·
·
·
· ·· · · · · · · · ·
·· ··· ··· ··· ··· ··· ··· ··· ··
·· ·· ··· ··· ··· ··· ··· ··· ·
· · ·· · · · ·
· · ·· ·· ·· ·· ·· ··
· · · · · ·· · ·· ··
·· ·· ·· ··· ··· ·· ··· ·· ·· ···
· ·· ·· ·· ·· ·· ·· ·
······· ·
····· ··
HPOXXOGOXXOXXV·
HPOXXOGOXXOXXV· · · · · · · · · ·
· · ·· ·· ·· ·· ·· ·· ··
QLLPLHOGOOOOOOOV.
PHOXXOGOXXOXXV·
· · ·· ·· ·· ·· ·· ·· ··
PHHHHHHGOHHHHHHV·
PLLLLHOGOOOOOOOV·
•
PLLLLHOGOOOOOOOV· · · · · · ·
······
LPLOOOOGOOOOXXXV· ·
• ·• • ·• ·
HHHHHOOGOHPHHOOV·
• •
HHHHLOOGOPHHHOOV· · · · · ·
·
XXLHOOLGLLPXXXXV· · · · · · ·
·
LLXXLHOGOXXXXPXV.
· ·· ·· ·· ·• ·· ··
He-aD
Pin
Type
No.
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4
154
155
157
157
158
158
160
161
162
163
164
165
166
173
173
174
174
175
175
181
182
190
191
192
193
194
195
221
0 000 0 000 0 0 0 GOO 0 0 0 L L L L L P V
L L L 0 0 0 0 GOO 0 0 P L LV.
P L H 0 LLOGOLLOLLLV·
P L H 0 LHOGOHLOHLLV
P L H 0 L LOG 0 L L 0 L L LV.
P L H 0 LHOGOHLOHLLV·
HPXXXXHGHHOOOOOV·
HPXXXXHGHHOOOOOV·
HPXXXXHGHHOOOOOV·
HPXXXXHGHHOOOOOV·
QHOOOOGPHOOOOV.
HPXXXXOGOQXXXXLV.
QXXXXLPGHXXXOXHV.
LLOOOOPGLLXXXOLV.
L L 0 0 0 0 P G L L Q Q Q Q LV.
HOQXOXOGPOXOXXOV.
H 0 Q Q 0 Q 0 GPO Q 0 Q Q 0 V •
HOOQXOOGPOOXXOOV.
H 0 0 Q Q 0 0 GPO 0 Q Q 0 0 V •
PHHLLHHLOOOGOBOOO LHLHLHV
HLHLHLOGOOOOPHLV
XOOHPOOGXXHOOLXV·
XOOLLOOGXXHOOPXV·
XOOHPOOGXXHOOLXV.
XOOHPOOGXXHOOLXV.
HQXXXXXGHLPOOOOV.
HHLXXXXGHPOOOOOV·
LHPOOOOGXXXOOORV
237
238
240
241
242
243
244
245
251
253
257
1•
4•
1•
4•
1•
4•
I•
6•
1•
4•
·· ·· ·· ·· · ·· ·
· · ·· ·· ·· ··· ·· ···
·· · · · · · ·
·· ·· ·· ·· ·· ·· ··
· ·
·· ··· ·· · ··· ·· ··
· · · · ·· ·· · ·· ··
··· ··· ··· ··· ··· ··· ··
· ·· ·· ·· ·· · ···
·· · · · · ·· ·
·······
· ·· ·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ·· ··
· ·· ·· ·· ·· ·· ·· ··
PLLLLHOGOOOOOOOV·
· ·· · ·· · ·· ··
PLLLLHOGOOOOOOOV·
· ·· · ·
·
LPOXOXOXOGXOXOXOXOXV.
LPOXOXOXOGXOXOXOXOXV.
···
LOPXXXGOOOOOLV·
·
·
LOPXXXGOOOOOLV· · · · · · · ·
·
·
· · · · · ·· · ··
•
·
·
·
·· ·· · ·· · ·· ··
·· ····
LPOXOXOXOGXOXOXOXOXV.
HPXXXXXXXGOOOOOOOOLV.
XXLHOOLGLLPXXXXV·
•
LLXXLHOGOXXXXPXV·
•
1 • PLHOXXOGOXXOXXLV·
*
number of sections active
HC-81
Pin
Type
No.
257
258
258
259
266
273
273
279
280
283
298
298
299
323
352
353
354
356
365
366
367
368
373
373
374
374
375
377
377
386
390
393
423
533
533
534
534
540
540
o
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 222 2
1 234 5 6 7 8 9 0 1 2 3 456 7 8 9 0 1 234
··· ··· ··· ··· ··· ··· ···
LLLOOOOGOOOOQPHV
·· ·· ·· ·· ·· ·· ·· ··
PLBOXXGXXOOXXV·
·
HOQXOOXXOGPOXXOOXXOV.
·· ·· ·
HOQQOOQQOGPOQQOOQQOV.
·
LPPOXXOGOXXXOXXV·
·
·
·
·
·
·
·
LLOLOOGPLLLLLV.
· · · · · ·· ·· ·· ··
OHLOPHLGOOHLOLHV·
·· ·· ·· · · · ·
LLHLLLLGLQPOOOOV
·
LLHHLLHGHQPOOOOV.
· · · · · ·· ··
HLLOOOOOHGQPOOOOOXLV
HLLOOOOOHGQPOOOOOXLV.· ·
·· ·· ··
LLXXLHOGOLLXXPXV·
·
·
·
·
LLXXLHOGOLLXXPXV·
· · · · ·· ·· ·
XXXXXXLHLGLLLPLLHOOV·
·
XXXXXXXQPGLLLLLLHOOV.
·
·
·
L POX 0 X 0 G 0 X 0 X 0 XLV.
LPOXOXOGOXOXOXLV· · · · · · · ·
· ·· ·· ·· ·· ·· ·
LPOXOXOGOXOXOXLV·
·
LPOXOXOGOXOXOXLV·
· · · · ·· ·· ···
LOQXOOXXOGPOXXOOXXOV.
L OQQOOQQOGPOQQOOQQOV.
LOQXOOXXOGPOXXOOXXOV. · · ·
· ·· ·
LOQQOOQQOGPOQQOOQQOV
·
·
··
QOOPOOQGXOOXOOXV·
·
·
·
·
·
·
LOQXOOXXOGPOXXOOXXOV.
· ·· ··
LOQQOOQQOGPOQQOOQQOV
·
·
PLOOXXGXXOOXXV·
· · ·· ·· ·· ·· ·· ·· ··
PLOQOOOGOOOXOXXV.
PLOOOOGOOOOXXV·
· · ·· ·· ·· ·· ·· ·· ··
LPHOOOOGXXXOOORV·
LOQXOOXXOGGPXXOOXXOV
·· ·
LOQQOOQQOGGPQQOOQQOV. · · ·
L 0 Q X 0 0 X X 0 GPO XX 0 0 X X 0 V •
· ·· ·
4- PLHOLHOGOHLOHLLV·
1-
PLHOXXOGOXXOXXLV·
4 - PLHOL~OGOHLOHLLV.
1-
8-
1•
4-
1-
81-
81-
8'
1• •
8'
1•
LOQQOOQQOGPOQQOOQQOV.
L P X XX X X X X GOO 0 0 0 0 0 0 LV.
8' L P P P P P P P P G.O 0 0 0 0 0 0 0 LV.
81-
* number
of sections active
HC-82
·· ·· ··
·
· ·
,..------- ---_._ .. --------_._._------_.-
1J~.e
541
541
563
563
564
564
573
573
574
574
590
592
593
595
597
620
623
640
643
646
648
651
652
670
688
690
691
692
693
696
697
698
699
4002
4016
4017
4020
4022
4024
4028
Pin
0 o 0 0 0 0 000 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4
1•
8•
1•
8•
1•
8·
1•
8•
1•
8•
·· ·· ·· ··
·· ·· ··· ···
·· · ·
· ·· ·· ·
·· ·· ··
·· ·· ·· ·· ·· ·· ···
· · · · ·· ·· ··
· · ·· ·· ·· ··
· ·· · ··
· · ·· ·
L PXXXXXXXGOOOOOOOOLV
L P P P P P P P P GOO 0 0 0 0 0 0 L V
L QXXXXXXXGPOOOOOOOOV.
L QQQQQQQQGPOOOOOOOOV
L QXXXXXXXGPOOOOOOOOV
L QQQQQQQQGPOOOOOOOOV.
L QXXXXXXXGPOOOOOOOOV
L QQQQQQQQGPOOOOOOOOV.
L QXXXXXXXGPOOOOOOOOV.
L Q Q Q Q Q Q Q Q GPO 0 0 0 0 0 0 0 V •
0 OOOOOOGOHPHPLOV·
XXXXXXXGOHPHXHXV·
OOOOOOOOHGOHPLHXHLHV·
o0 0 0 0 0 0G0HP P LQ0 V •
XXXXXXXGOHPXHQXV.
•
HPXXXXXXXGOOOOOOOOHV
HPXXXXXXXGOOOOOOOOHV
HPXXXXXXXGOOOOOOOOLV·
HPXXXXXXXGOOOOOOOOLV
XLHPXXXXXXXGOOOOOOOOLXXV
XLHPXXXXXXXGOOOOOOOOLXXV
XLHPXXXXXXXGOOOOOOOOHXXV
XLHPXXXXXXXGOOOOOOOOHXXV
Q Q Q L P 0 0 GOO L L L P Q V •
L P L L L L L L L G L L L L L L L L 0 V
HPXXXXHHXGLLHHOOOOOV
HPXXXXHHXGLLHHOOOOOV·
HPXXXXHHXGLLHHOOOOOV
HPXXXXHHXGLLHHOOOOOV·
HPXXXXLHXGLLHLOOOOOV·
•
HPXXXXLHXGLLHLOOOOOV·
HPXXXXLHXGLLHLOOOOOV
•
•
HPXXXXLHXGLLHLOOOOOV
OPLLLOGOXXXXOV.
OOOOXXGOOOOXPV.
o 0 0 0 0 0 0 GOO 0 0 L P LV.
o 0 0 0 0 0 0 GOP L 0 0 0 0 V •
o 0 0 0 0 0 0 GOO 0 0 L P LV.
PLOOOOGOOOOOOV· ~
OOOOOOOGOPXXXOOV·
* number
· · · ·· ·· ·· ··
· ·· ·· ··
· ·· ·· ··
· ·
·
·· · ··· ··
.. · · · · · · · ·
· · · · · ·· · ·
·· ·· ·· ·· · ·· ··
· ··· ··· ··· ··· ··· ··· ···
of sections active
He-S3
Pin
}rg.e
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4
4040
4049
4050
4051
4052
4053
4060
4066
4072
4075
4078
4094
4316
4351
4352
4353
4511
4514
4515
4518
4520
4538
4543
7007
7240
7241
7244
7266
7292
7294
7640
7643
7645
40102
40103
40105
0
V
V
0
0
0
0
0
0
P
·· ·· ·· ·· ·· ·· ··
·· ·· ·· ·· · · · ·
· ·· ·· ·· ··· ··· ··· ···
· ·· ··· ··· ··· ··· ··· ··· ··
. ·· · · · · · · · ··
· ·· ·· ·· ·· ·· ·· ·· ··
· · · · ·· ·· ·
· · ··
· · · · ·· ·· ··
·· ·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ·· ·· ·
· · · · · ·· ·· ·· ···
· ··· ·· ··
· · ·· ·· ·· ·· · ·· ··
· · · · ·· · ·
·· ··· ···
·· ·· ·· ·· ·· ·· ·· ··
········
0 OOOOOGOP L o 0 0 0 V •
0 POXOXGXOXOOXOO·
OPOXOXGXOXOOXOO
000 OLGGLL P 000 OV
0 o 0 0 L G G L P 0 000 0 V
0 o 0 0 L GG L L P o 0 0 0 V •
0 000 0 0 GOO P L 0 0 0 V •
0 OOXXGOOOOXPV·
P LLLOGOXXXXOV.
LXXXOGLOOXXXV
o P L L LOG 0 L L L L o V •
H Q P 0 0 0 0 GOO 0 0 0 0 H V
o 0 0 OPXLGGOOOOXXV·
0 o 000 0 L HOG H P L 0 L 0 0 0 0 V •
0 o 0 0 0 0 L HOG H P L 0 0 0 0 0 0 V •
0 o 0 0 0 0 L HOG H P L 0 L 0 0 0 0 V •
L L H H L LPG 0 0 0 0 0 0 0 V •
H P L 0 0 0 0 0 0 0 0 GOO 0 0 0 0 0 0 L L L V
H P L 0 0 0 0 000 0 GOO 0 000 0 0 L L L V
P H 0 0 0 0 L G X X 0 0 0 OXV.
PHOOOOLGXXOOOOXV.
GRHPHOOGOOXXLOGV
HLLHLPLGOOOOOOOV
P OXOXOGOXOXOXV.
L P OXOXOXOGXOXOXOXOXV
L P OXOXOXOGXOXOXOXOXV.
L P OXOXOXOGXOXOXOXOXV
P L OOXXGXXOOXXV.
H L OPLOOGOLHO o L LV.
H L OPLOOGOOHO o L LV.
HPXXXXXXXGOO o 0 0 0 0 0 LV.
HPXXXXXXXGOO o 0 0 0 0 0 LV.
HPXXXXXXXGOO 0 o 0 0 0 0 LV·
PHLLLLLGHLLL LOHV
PHLLLLLGHLLLLOHV
LOP Q Q Q Q G L 0 0 0 0 0 P V
HC-84
7-3 Output Current Characteristics
The output current characteristics of TC74HC series can be divided into standard and buffer types.
An IC of the standard type is capable of directly driving 10 LSTTL, and guarantees
V CC -V OH :;;;O.37V, VOL :;;;O.33V over the entire temperature range. The buffer type, is capable of
directly driving 15 LSTTL under the same conditions.
Fig. 7-2 shows the standard output current characteristics of each type when used at the 4.5V.
Note) The solid line shows standard characteristics. Because there are variations depending upon the samples, use the
broken line and separate standard values when making design.
High level output current
characteristics
Low level output current
characteristics
High level output voltage VOH-Vee (V)
-e
Vee =4.5V
~
-5
-4
-2
-3
~
0
-1
1
-<
<=
0
'" II
-
.,,"
10
/
j... ..
:r:
0
<=
......'"
:>
.!
./
40
. / I--j
30
I
;;
10 /
J
T
- -- - -
Ta=85"C(MIN.)
-"
",""
f-.
-
~.
;t
0
bD
T T
7
20
>
T
V
0
~
Vee =4.5V
....l
0
'"
;;
>
.!
I--'"
Ta=25"C (TYP.)
~
"
:s
30
40
-;
20 :s
0
./
~
Ta=25"C (TYP.)
...
:s
"
-;
'"
/
Ta=85"C (MIN.)
e
~~
<
00
...:l
2
I
p::
3
4
5
Low level output voltage VOL (V)
(i) Standard Type
Low level output current
characteristics
High level output current
characteristics
High level output voltage VOH - Vee (V)
~
-5
-4
-3
-I
-2
0
"
" I
II
-
... ...
I
I
Ta=85"C(MIN)
/
/
Ta=25"C(T~
I
I
k "'"
~
0
<
- e
<=~
"...
10 ~.9
20
-30
-;"
= . V _
_ "
10
.!
-40 .!
f-+/-I-t-f-+'Ta=85"C (MIN ) - - -
:s
o
0
I T r , __
Ta=25"C(TYP)
....l
0
"
I
./
<=~
"
...
45
50~r-'--r-+-.~~~~~L+-4
I
I
11.'
~
-50
Vee =4.5V
bD
iii
Low level output voltage VOL (V)
(ii) Buffer Type
Fig. 7--2 Standard Output Current Characteristics
He-85
When the structure of the device has been determined, the current flowing in the MOS FET is obtained using the gate
voltage VGS and the voltage Vos between source and drain. In an actual Ie, the gate voltage of output step MOS FET becomes
nearly Vee and GND level. Therefore, if I VGS I = Vee is considered, the following equation is realized in non-saturation zone:
If Va:; is made constant, I a:; is proportional to Vcc -VT
= K (V GS
Ia:;
In the saturation zone:
•
- V T)2
Thus, los is proportional to (Vee - VT )2 not to Vos. Here, VT is the threshold voltage proper to the MOS FET's, and is set to
a value of about O.7V in TC74HC series.
Fig. 7-3 shows supply voltage-output c1,1rrent characteristics of standard type outputs. This figure
shows standard values. Note that the variation of output current at low supply voltage becomes large
in comparison with that at 4.5V.
-7
-6
-5
VOH -Vee (V)
-4
-3
-2
-I
-0
Ta=25"C
60r---~--~---+--~----r-~~.~--~
-10
5.5V
-20
5.0V
-30
<
S
<
S
-40
..J
:J:
o
0
-50
-60
VOL (V)
'!OL Characteristics
IOH Characteristics
Fig. 7-3 Standard Output Current Characteristics
He-86
7-4 AC Electrical Characteristics
(1)
Supply voltage dependence
'1ransient characteristics of IC's such as propagation delay time and maximum operating frequency are determined by
delay time of the inner gate or rise and fall time of the output buffer.
Internal delay is considered to be chiefly due to the integral effect of the on resistance of the MOS FET. Load capacitance
does not remarkably depend upon supply voltage, the drain current characteristics of MOS FET determine the dependence
of AC electrical characteristics to supply voltage.
Fig. 7-4 shows the dependence of propagation delay time on supply voltage in a representative gate IC.
In JEDEC Standard 7A, the coefficient of dependance on supply voltage is determined as follows: In the worst case, adopt
the broken line indicated in Fig. 7-4 which was made on the basis of the JEDEC standard.
Table 7-1 Calculation of AC Standard Value
Table 7-2 Calculation of fMAX Standard Value
(excepting f....,J
Vee
2.0
4.5
6.0
Ta=25"C
5.00X
Ta= - 40-85"C
Vee
5.00Y
2.0
X
0.85X
Y=1.25X
0.85Y
4.5
6.0
Ta=25"C
0.20X
Ta= - 40-85"C
X
1.18X
Y=0.80X
1.18Y
.,
OJ"
.
.,
.:=
!
.
CD
5
Supply voltage Vee
(V)
Fig. 7-4 Dependance of Propagation Delay Time on Supply Voltage
He-87
O.20Y
(2) Load capacitance dependence
In the TC74HC series, output current has been greatly improved in comparison with the conventional 4000B/4500B
series; a capacitive load can be driven at high speed.
However, since the output impedance is determined when supply voltage is selected, the rise and fall time of the output
waveform or propagation delay time will increase in proportion to an increase in load capacitance.
Fig. 7-5 indicates the load capacitance dependence on output rise and fall time at a supply voltage
of 4.5V. Fig. 7-6 shows the load capacitance dependence on propagation delay time.
Buffer Type
Standard Type
-;
.5..J
:x:
20
S
.,
VCC=4.SV
Ta=25"C
.5..J
:x:
VCC=4.5V
Ta=25'C
20
S
:x:
:x:
S
S
..J
..J
"6
....
10
~
...c
.
"~
.~
....
0
;;
V
"'c"
.,""
.~
100
V
......
0
i.--"
50
0
"
2-
Load Capacity CL (pF)
"
0
....
.... f-'""'"
10
~
V
50
0
2-
"e
'"
100
Load Capacity CL
"
0
(pF)
Fig. 7-5 Load Capacitance Dependence of tTLH ,tTHL (standard characteristics)
Standard Type
'"c
_Co
20
..J
:x:
_Co
_Co
I---"
"e
»
....
10
I---"
"
."
C
......
.~
~
0.
Vee =4.5V
Ta=25'C
c
:x:
..J
~
(HC240A)
.,
Vee =4.5V
Ta=2S'C
~..J
:x:
Buffer Type
(HCOOA)
20
:x:
..J
f-- I-"
.e
_Co
»
--
10
"
0;
"'c"
-I-"
.~
.....
as
0
0
.
100
50
Load Capacity CL(pF)
0
0.
0
0
SO
100
Load Capacity CL(pF)
Fig. 7-6 Load Capaci.tance Dependence of tpLH ,tpHL (standard characteristics)
He-88
In the TC74HC series, AC characteristics are guaranteed using a load capacitance of 5OpF.
Propagation delay time usinga load capacitance, other than this value is obtained by the following
equation:
(Example) High level propagation delay time in the case of load capacitance of XpF.
tpLH (X) = A (X - 50) + tpLH (50)
A: High level propagation delay time increase rate per unit load capacitance(ns/pF)
Table 7-3 Load Capacitance Dependence of AC Electrical Characteristics (ns/pF)
Vee
Standard Output
Typical value
Limit value
Buffer Output
Typical value
Limit value
(Ta=25"C)
(Ta=25"C)
(Ta=25"C)
(Ta=25"C)
tTLH, tTHL
2.0
4.5
6.0
0.33
0.12
0.09
0.83
0.24
0.16
0.22
0.08
0.06
0.55
0.16
0.11
tpLH, tpHL
2.0
4.5
6.0
0.17
0.06
0.043
0.43
0.12
0.077
0.13
0.05
0.038
0.33
0.10
0.068
Table 7-3 shows increase rate per unit capacity of AC electrical characteristics having load
capacitance dependence.
In the case of a heavy capacitive load, it is necessary to make the calculation using the limit values
in this table.
In TC74HCxxxA series, AC characteristice of 15pF load capacitance (standard output,
V CC =5.0V) or 150pF load capacitance (buffer output, V cc =2, 4.5, 6V) is guaranteed. (See the
technical data seets)
He-89
7-6 Temperature Parameters of Various Characteristics
In TC74HC series, operation over the wide temperature range of -4O"C to 85"C is guaranteed. This
section shows how the switching time and output current are influenced by temperature.
(1)
Thmperature versus Output Current
Fig. 7-7 indicates temperature versus output current. In this rlgure, the solid line shows the temperature dependence in a
standard sample. When designing, use the broken line as it is the worst case.
Vee -4.5V
140
IOUI
140
Vee -4.5V
C L =50pF
120
_
tlla
"'tpd -IpJfa- 25 't)X 100
"'lOUT = IOUT(fa=251::)" 100
...
8
;,0
.............. r100
<1
-- - -- ::::-
~
-
f'::::::
80
20
40
'&
500V
> -500V
> 500V
> -500V
TC74HC02AP
> 500V
> -500V
> 500V
> -500V
TC74HC74AP
> 500V
> -500V
> 500V
> -500V
TC74HC139AP
>SOOV
> -500V
>SOOV
> -500V
TC74HC240AP
>500V
> -500V
> 500V
> -500V
TC74HC373AP
>500V
> -500V
> 500V
> -500V
8-2
(I)
Precautions in Handling
Transportation and Storage
AB the input and output tenninals of unmounted CMOS 1O's are in a state of high impedance, they are apt to receive
induced charges from the surrounding charged body, space electric fields, and the human body.
For this reason, it is necessary, in transporating and storing CMOS IC's, to use dielectric mats, metal cases or aluminum foil
boxes, so that each tenninaJ of the 10 will be at same potential.
TC74HC series devices are inserted in magazines and are given antistatic treatment at the time of shipment. Do not
remove devices from the magazines unnecessarily. Particularly, avoid the use of plastic or vinyl containers which are apt to
create static charges.
(2) Assembling
When installing CMOS IC's on the printed wiring board, it is necessary to protect the electric equipment, work stand and
assemblers from static electricity by grounding. It is advisable to ground the work stand by placing a metal plate or
spreading aluminum foil on the surface. Grounding of assemblers should be made through a resistance of about
IMfi so as to prevent electric shock. Ground through a metallic ring or wrist bands. Also, it is advisable not to wear work
clothes made of chemical fibers. Further, it is necessary to periodically check electric equipment to insure absence of
electric leakage.
When shaping the leads during the packaging of IC's, it is advisable to use a pincet or similar jig, so that stress may not be
given to the device leads at the package entrance.
When storing or transporting the completely assembled printed wiring board, short circuit the terminals of printed wiring
board or cover the entire board with aluminum foil, so that the input terminals of the 10 are protected.
HC-92
(3)
Soldering
When soldering by use of a soldering iron, carry out the work at temperatures of 260·C or below within 10 seconds. The
reliability of TC74HC series is not affected when subjected to a temperature stress at the lead of 260·C for 10 seconds.
Use a soldering iron having no electrical leakage at its end. It is recommended to use a class A iron having an insulation
resistance exceeding 10MO. When using a soldering tank, it is necessary to ground the tank so as to prevent the electric
potential of the soldering tank from affecting the work.
After soldering the IC's on the printed wiring board, cleaning is done to remove flux, etc. For this cleaning use a flux
removing solution or a cleaning method utilizing ultrasonic waves. Care must be taken in the selection of the solvent so as to
prevent adverse effects on the package and marking of the CMOS IC.
In general, it is advisable to use Freon" cleaners.
When using ultrasonic cleaning, it is necessary to prevent stress due to signal resonance being imparted to the IC's or
printed wiring board. Because of this, it is necessary to consider a method such that the main body becomes a shade against
vibration, and also to use a cleaning time of less than 30 seconds.
(4) Adjustment, Test
When making adjustments and tests after the completion of printed wiring board, it is necessary to check for solder
bridges or cracks on the printed wiring board before applying power. As CMOS systems require only a small supply current,
apply current limiting during test by using a constant voltage power source.
Before inserting or removing printed wiring boards into or out of the test fixture, remove all power.
When inspecting the printed wiring board with a probe, care must be taken to prevent contact of the tip of the probe with
other signal or power lines. It is advisable to install a special test device for use with probes.
When a test is conducted under high power and low temperature, it is necessary to ensure that the constant temperature
oven is grounded.
}o'reon'l':.I is REGISTERD TRADEMARK or DUPONT CORP.
HC-93
9 PRECAUTIONS IN DESIGNING CIRCUITS
9-1
Input Processing
(1)
Processing of unused gate
Inputs of CMOS IC have such a high impedance that the logic level becomes undefined under open conditions. If the input
is at an intermediate level, the P-channeJ and N-channel transistors both tum on, and excessive supply current flows.
Therefore, as shown in Fig. 9-1, be sure to connect unnecessary
Fig. 9-1 Treatment of Input
input lines to Vco GND or other inputs.
In the case of CMOS, if a soldered part makes poor or no contact,
a malfunction of the system or an increase in supply current can
occur. Therefore, care must be taken at the time of soldering.
(·Unused gate)
Vss
When an input terminal of a printed wiring board is connected
directly to a CMOS input, that input electrically floats. This condition is the same as a single IC being transported or stored. It is
advisable, therefore, to connect this input to Vee or GND through a
resistance on the printed wiring board, as shown in Fig. 9-2.
R:::IOOkQ
Fig. 9-2 Input processing
of Printed Wiring Board
HC-94
8-2 Design of Power Source
In general, CMOS has a very small current consumption in comparison with bipolar digitallC's and, therefore, it needs
only a small capacity power supply. However, from the operational standpoint, CMOS consumes power in the transition state,
and therefore it is necessary to keep the high frequency impedance of the power source as low as possible.
It is advisable to make the wiring of the power source (Vcc) and GND lines thick and short, and insert, as a high frequency
filter, a O.OOIjl.F to O.I ....F capacitor between Vcc and GND for each Ie.
Also, it is recommended that a capacitor of about lO ....F to lOO ....Fbe inserted between the power supply entrance and GND
as low frequency filter. As mean supply current differs considerably depending upon the operating frequency of the system,
existence of capacitive load, rise and fall of the input signal and supply voltage, attention must be given especially in the case
of a simple power source, by using a Zener diode or by battery drive. When there is overshoot or undershoot during the
transition time of the power supply, use a filter, etc. so that the maximum device rating is not exceeded.
Output Short circuit
In the TC74HC series, a buffer is added to the output, and both outflow (I0H) and inflow (IorJ current drive is possible. For
this reason, excessive current flows in the CMOS output when the high level output line is shorted to GND or the low level
output line is shorted to Vcc. Particularly, when the supply voltage is high, 10H and IOL are quite excessive and may damage
the device; therefore care must be taken not to cause an output short curcuit.
It is, of course, impossible to directly connect ordinary outputs
together. But in the case of an IC which has a 3-state output, a
wired OR is permitted provided that no more than two outputs are
enabled simultaneously.
Further, in order to improve drive capacity, it is possible to
connect the gates in the same package as shown in Fig. 9-3.
Fig. 9-3 Example of how to increase
of drive capacity
HC-95
9-4
Effect on Input of Slow Rise and Fall Time
When a slow rise on fall time signal is impressed on a CMOS
F/F-2
input, it sometimes happens that the output tends to oscillate
I--,..,.-~.D
around VTH (threshold voltage of the device). This is because the
Q2
CMOS gate becomes a linear amplifier equivalent in the vicinity of
VTH' and minute power source ripple and noise components are
amplified and appear in the output.
CLOC~K~4-
__________-J
'Ib prevent this, it is necessary to insert a high frequency filter
." n
n n n n
capacitor between Vee and GND of the oscillating Ie, or use a CLOC~ LJ LJ LJ LJ L
---1
L~
Schmitt trigger IC.
In the case of the TC74HC series, excepting HCU types or
QI
Schmitt trigger IC's, input rise and fall time is limited as shown in
Q2 _____....J
'Thble 9-1.
la) Normal operating waveform
Proper design requires that these rise and fall time limits be
observed.
Fig. 9-4 shows an example of a malfunction when a shift counter
is designed by using aD-type flip-flop in separate packages. In this
QI
case, the malfunction is considered to be caused by the difference
Q2~~
in circuit threshold level of separate D-type flip flops.
Ib) Malfunction waveform from
at the time Vth Cl>Vth C2
Malfunction waveform from
at the time Vth Cl-.JtNr-+--I I/O
Fig. 9-15 Example of Latch-up Prevention Methods
HC-106
9 - 8 Metastable Characteristics
When the set-up or hold-time of a flip-flop is violated, the device output response is uncertain. When an asynchronous
signal is input to a flip-flop which is clocked by the internal clock of a synchronous system, the system designer cannot
guarantee that the set-up and hold-time specifications associated with the flip-flop will not be violated.
hold-time specifications associated with the flip-flop will not be violated.
ASYNCHRONOUS INPUT
____t~D~_Q.Jr"''"'"..,'"oo'''''
CP
CLOCK
ts>min.
_
th>min.
-
--
ts11
thl1
ASYNCHRONOUS DATA
CLOCK
OUTPUT
-
tpd:>;max.
-1-----
tpd11
Fig. 9-16 Metastable Timing Diagram
The metastable state is defined as that time period when the output logic level is not at "I", nor at "0", but in the state of
between 30% and 70% of Vcc.
This metastability is illustrated in the timing diagram of Fig. 9-16.
HC-107
NOTES
He-lOB
10.
DATA SHEETS
TC74HC/HCT SERIES
TC74HCOOAP/AF/AFN
QUAD 2-INPUT
NAND
GATE
The TC74HCOOA is a high speed CMOS 2-INPUT
NAND GATE fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 3 stages including
buffer output. which. provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=6ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=lJlA(Max.)at Ta=25"C
• High Noise Immunity .............. · V:"IH =VX1L =28% Vcc(Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance "'1100 1=Ia. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH"'tpHL
• Wide Operating Voltage Range .. · Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LSOO
1
P(DIP14-P-300)
F(SOP14-P-300)
PIN
FN(SOL 14-P-150)
ASSIGNMENT
1A
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND
14 Vee
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
7
(TOP VIEW)
IEC
LOGIC
SYMBOL
lA
18
2A
28
3A
38
4A
48
TRUTH
TABLE
lY
A
B
Y
2Y
L
L
H
L
H
H
H
L
H
H
H
L
3Y
4Y
HC-111
TC74HCOOAP/AF/AFN--------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
SYMBOL
Supply Voltage Range
-0.5-7
Vee
DC Input Voltage
-0.5 -Vee +0.5
V/:,\
DC Output Voltage
-0.5 -Vcc+0.5
I VOLT
Input Diode Current
±20
! I/K
Output Diode Current
±20
10K
DC Output Current
±25
lOll'
DC Vee/Ground Current
±50
Icc
Power Dissipation
500(DIP)
*1I80(MFP)
~)
Storage Temperature
-65 -150
Tstg
Lead Temperature lOsec
300
TL
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Vcc
V/:,\
VOLl'
Topr
Input Rise and Fall Time
I
t r • tr
VALUE
2-6
0- Vcc
0- Vcc
-40 - 85
0-- 1000(Vce =2.0V)
0- 500(Vec =4.5V)
0- 400(V('('=6.0V)
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85"C a derating factor of
-lOmWI'C shall be applied
unti1300mW.
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
SYMBOL
I
High-Level
Input Voltage
V",
Ii
Low-Level
Input Voltage
V".
PARAMETER
!
i
i
High-Level
Output Voltage
I
I
V(l/
I
i
I
Low-Level
Output Voltage
Va.
Input Leakage Current
Quiescent Supply Current
1/:\
Icc
I
I
I
I
,
TEST CONDITION
Vee
2.0
4.5
6.0
I 2.0
4.5
6.0
2.0
la/ =-20IlA 4.5
V/:,\=
6.0
V/HorV". 1m --4 rnA 4.5
1011 =-5.2mA 6.0
2.0
Ia. =20 Il A 4.5
V/:'\=
' 6.0
V,,/orV/ L
101.. -4 rnA 14.5
101. =5.2mA I 6.0
V,:\ =Vcc or GND
I 6.0
i 6.0
V/:'\ =V('(' or GND
HC-112
Ta-25"C
Ta--40 -85"C UNIT
TYP. MAX. MIN. I MAX.
1.5
V
3. 15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
(4
4.4
4.5
V
6.0
5.9
5.9
4.18
4.31
4.13
5.68
5.80
5.63
O. 1 I
0.1
0.0
0.1
0.1
0.0
V
0.1
0.1
0.0
0.33
0.26
0.17
0.18 I 0.26
0.33
- I ±0.1 ±1.0
A
10.0 Il
i 1..0 I
MIN.
1.5
3. 15
4.2
---------------TC74HCOOAP/AF/AFN
AC ELECTRICAL CHARACTERISTICS(C l =15pF ,Vcc=5V ,Ta=25 C. Input t r =t,=6ns)
D
PARAMETER
Output Transition Time
Propagation Delay Time
!SYMBOL!
I
I
II
I
tTI.II
tTllL
tpl.Il
t ~ II.
TEST CONDITION
MAX.
MIN.
TYP.
-
4
8
-
6
12
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C l =50pF,lnput t r ::;t,=6ns)
: Ta--40 -85"C
Ta-25"C
PARAMETER
snlBOL TEST CONDITION
UNIT
Vee MIN. TYP. MAX.Il\UN. MAX.
2.0
25
i5 !
95
tTl.l1
Output Transition Time
4.5
i
15 I 19
tTIlL
6.0
6
13
16
ns
2.0
2i
i5 I 95
tpUI
Propagation Delay Time
4.5
9
15
19
tpllL
6.0
8
13 I 16
Input Capacitance
CI\
5
10 i 10
pF
- I Power Dissipation Capacitance CI'I)(l)
20
I Note!!} em is defined as the value of the internal equh'alent capacitance which is calculated from the
operating current consumption without load.
A"erage operating current can be obtained by the equation:
ICC (Il';=C 1'1). Va:· f 1\ +1 (C /.1(per Gate)
I
I
I
TC74HCTOOAP/AF------QUAD 2-INPUT NAND GATE
The TC74HCTOOA is a high speed CMOS 2-INPUT
NAND GATE fabricated with silicon gate C' MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 3 stages including a
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd =lOns(Typ.)at Vee = 5V
• Low Power Dissipation ............ Icc=IJlA(Max.)at Ta=25"C
• Compatible with TTL outputs ...... VIH=2V(Min.)
VIL=0.8V(Max.)
• Wide Interfacing ability .... ••• .. LSTTL,NMOS,CMOS
• Output Drive Capability'" ......... 10 LSTTL Loads
• Symmetrical Output Impedance .. ·1100 1=IOL=4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Pin and Function Compatible with 74LSOO
1
P(OIPI4-P-300)
14~
1
F(SOPI4-P-300)
PIN
ASSIGNMENT
1A
16
1Y
2A
26
2Y
GND
14 Vee
13 46
12 4A
11 ' 4Y
10 36
9 3A
8 3Y
1
2
3
4
5
6
7
(TOP VIEW)
IEC
LOGIC
SYMBOL
lA
18
2A
28
3A
38
4A
48
TRUTH
lY
TABLE
B
y
L
L
H
L
H
H
H
L
H
H
H
L
A
2Y
3Y
4Y
HC-114
- - - - - - - - - - - - - - - - - - TC74HCTOOAP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI~
VOLT
11K
ICf(
1mI'
lee
Po
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) *1180(SOIC)
-65 -150
300
*500mW in the range of Ta=
-40·C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
VALUE
Vee
VI:>;
VOLT
Topr
tr. tr
4.5 - 5.5
0- Vee
0- Vee
-40 - 85
0- 500
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOI-I
Low-Level
Output Voltage
TEST CONDITION
l
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
4.4
4.5
-
4.4
V
4.13
-
-
0.1
l
55
Va.
II~
Icr
Quiescent Supply Current
MIN.
55
4.5
VI:>; =
VIHorVIL
Ioo=-20JlA
Alec
4.5
loH=-4 rnA
4.5
4.18
4.31
-
Ia.=20 JlA
4.5
-
0.0
0.1
rnA
4.5
-
0.17
0.26
=Vee or GND
-Vee or GND
PER INPt:T: VIN =0. 5V or 2.4V
5.5
5 5
-
-
-
-
VI~=
VIHorVIL
Ia.=4
Input Leakage Current
Ta=-40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
Vee
4.5
VI~
V~
OTHERINPt:T:Vcc orGND
HC-115
5.5
V
-
0.33
-
+l.0
JlA
10 0
rnA
2.9
+01
10
2.0
TC74HCTOOAP/AF - - - - - - - - - - - - - - - - - AC ELECTRICAL CHARACTERISTICS(C L =15pF,VcC =5V,Ta=25"C.lnput t r =t,=6ns)
PARAMETER
SYMBOL
Output Transition Time
t1LH
t'J1iL
tpLH
tnHL
Propagation Delay Time
MIN.
TEST CONDITION
-
MAX.
TYP.
4
8
10
20
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L=50pF,lnput t r =t,=6ns)
'1'a--40 -85"C
Ta=25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Voc MIN. TYP. MAX. Mi!li.MA"...
Output Transition Time
t1Ui
t'J1iL
4.5
5.5
Propagation Delay Time
tpLH
tpH1.
4.5
5.5
-
-
8
7
15
14
13
12
19
17
~
-
-
19
18
ns
24
21
input Capacitance
CIN
5
10
10
pF
Power Dissipation Capacitance Cpom
19
Note (1) C A) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IOCtpD=C PD" Voc o flN+1 oc/4(per Gate)
HC-116
-
NOTES
rC74HC02AP tAFt AFN·
QUAD 2-INPUT NOR GATE
The TC74HC02A is a high speed CMOS 2-INPUT NOR
GATE fabricated with silicon gate dMOS technology.
It achieves the high speed operation similar' to
.equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 3 stages. including a
buffer output. which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP14-P-300)
14~ 14~
t
1
FEATURES:
• High Speed ................................. tpd=6ns(typ.)at Vcc=5V
• Low Power Dissipation ............... I cc =1ttA(Max.)at Ta=25"C
• High Noise Immunity· .............. VN1H =VN1L =28" Vcc(Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance .. ·1 Ia-d=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH"tpHL
• Wide Operating Voltage Range ... Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LS02
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
1Y 1
lA 2
16
3
2Y
2A
28
GND
4
14 Vee
13 4Y
12 46
11 4A
10 3Y
9 38
8 3A
5
6
7
(TOP VIEW)
IEC LOGIC SYMBOL
1A
18
2A
28
3A
38
4A
48
TRUTH TABLE
1Y
A
B
Y
2Y
L
L
H
L
H
L
3Y
H
L
L
4Y
H
H
L
HC-118
- - - - - - - - - - - - - - TC74HC02AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
Vee
VI\
VOLT
111\
IClI\
Iocr
Icc
Pr,
Tstg
TJ.
VALUE
-0.5-7
-0.5 -V(.'(..+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */ 180(MFP)
-65 -150
300
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
VALUE
2-6
0- V('(..
0- Vee
-40 - 85
o - 1000(Vce=2.0V)
0- 500(Vee =4.5V)
0- 400(Vee =6.0V)
SYMBOL
Vee
VI\
VOLT
Topr
Input Rise and Fall Time
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VUI
Low-Level
Input Voltage
VII.
High-Level
Output Voltage
V(~I
TEST CONDITION
I
I
I
I
Low-Lel'el
Output Voltage
V(~.
Input Leaka~ Current
11\
Quiescent Suppl!' Current
Icc
VI\=
VUJorVIL
VI\=
VIlJorVIL
I
IUJ =-20 tl A
IaJ --4 mA
1m =-5.2mA
lex. =20 tl A
Icx. -4 mA
I(~. =5.2mA
VI\ -Vee or GND
VI\ ""Vee or GND
HC-119
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6:0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
Ta-25"C
Ta--40 -85"C IUNIT
TYp. MAX. MIN. MAX. I
1.5
V
3.15
4.2
0.5
0.5
V
I. 35
I. 35
1.8
1.8
2.0
1.9
I. 9 '
4. 5
4.4
4.4
V
6.0
5.9
5.9
4.31
4.13 II 4.18
5.80 . 5.63 i, 5.68
0.0
O. I I
O. I
0.0
O. I
O. I
V
O. I
0.0
! O. I
O. 17
0.33
0.26
0.33
0.18
0.26
±O.I
=1.0
A
10.0 tl
I 1.0
I
MIN.
1.5
3.15
4.2
I
I
TC74HC02AP/AF/AFN - - - - - - - - - - - - - -
AC ELECTRICAL CHARACTERISTICS(C L =15pF,Vcc =6V,Ta=25"C.lnput t r =t,=6ns}
PARAMETER
SYMBOL
Output Transition Time
Propagation Delay Time
MIN.
TYP.
tTUI
tml.
-
4
8
tl~.11
-
6
12
t
TEST CONDITION
)111
MAX.
UNIT
ns
AC EL'ECTRICAL CHARACTERISTICS(C L =60pF,lnput t r =tf=6ns}
Ta-25"C
Ta--40 -85"C
PARAMETER
UNIT
SYMBOL TEST CONDITION I V<:c
MIN. I TYP. MAX. MIN. MAX.
25
75
95
t·n.1I
.0
1 2
Output Transition Time
4.5
7
15
19
t'nu.
6.0
6
13
16
I
ns
2.0
27
75
95
tpUI
Propagation Delay Time
4.5
9
15
19
t plU.
8
13
6.0
16
Input Capacitance
C I\
10
10
I 5
pF
Power Dissipation Capacitance CJ'I)(1)
! 21
Note (1) C In IS defined as the value of the internal equivalent capacitance which IS calculated from the
operating current consumption without load.
A"erage operating current can be obtained by the equation:
I(:Cl~xI =CPD • Voc· fl\ +Ioc 14(per Gate)
~
I
I
-
HC-120
-------TC74HCT02AP/AF
QUAD 2-INPUT NOR GATE
The TC74HCT02A is a high speed CMOS 2-INPUT
NOR GATE fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
The internal circuit is composed of a stages, including a
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpa= 9ns(Typ.)at V cc = 5V
• Low Power Dissipation ............... Icc=l/.tA(Max.)at Ta=25"C
• Compatible with TTL outputs ...... VIH =2V(Min.)
VIL =O.8V(Max.)
• Wide Interfacing ability· ........ LSTTL,NMOS,CMOS
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance ..·IIrnl=IQl.=4mA(Min.)
• Balanced Propagation Delays ...... tpLH .. tpHL
• Pin and Function Compatible with 74LS02
1
P(DIP14-P-300)
14~
1
F(SOP14-P-300)
PIN ASSIGNMENT
lY
14 Vee
1A 2
13
4Y
1B 3
12
4B
4
11
4A
2Y
2A
5
10
3Y
2B
6
9
3B
GND
7
8
3A
(TOP VIEW)
IEC LOGIC SYMBOL
lA
18
TRUTH TABLE
IV
A
B
Y
L
L
H
L
H
L
2A
2B
2Y
3A
3B
3Y
H
L
L
4Y
H
H
L
4A
4B
HC-121
TC74HCT02AP/AF - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC OUtput Voltage
Input Diode Current
OUtput Diode Current
DC OUtput Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
VOUT
11K
10K
lour
lee
Po
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)*/180(SOIC)
-65 -150
300
UNIT
V
V
V
mA
mA
mA
mA
mW
*500m W in the range of Ta=
-40"C- 65'C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
VALUE
Vee
VIN
VOUT
Topr
tr. tc
4.5 - 5.5
o-Vee
O-Vee
-40 - 85
0-500
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Low-Level
OUtput Voltage
Input Leakalre Current
Quiescent Supply Currmt
TEST CONDITION
MIN.
l
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
4.4
4.18
4.5
4.31
0.0
0.17
-
4.4
4.13
-
V
5.5
4.5
Voo
VOL
lIN
lee
AI ••
Ta-25,,(
Ta--40 -85"C
UNIT
TYp. M.AX. MIN. MAX.
Vee
4.5
l
5.5
4.5
4.5
4.5
4.5
5 5
5 5
VIN=
1100 --20tt A
V1HorVIL 1m --4 mA
VINIOL -20 ttA
VlHorVIL 101. =4 mA
VIN -Vee or GND
VIN =Veeor GND
PER INPUT: VL" =0. 5V or 2. 4V
5.5
OTHER INPUT:Vee or GND
HC-122
-
-
-
0.1
0.26
±O 1
1.0
2.0
-
-
0.1
0.33
±l 0
10 0
2.9
V
ttA
mA
- - - - - - - - - - - - - - - - - - TC74HCT02AP/AF
AC ELECTRICAL CHARACTERISTICS(CL =16pF. Vcc=6V .Ta=26"C. Input tr=t,=Bns)
PARAMETER
SYMBOL
MIN.
TEST CONDITION
MAX.
TYP.
UNIT
-
tTUi
4
12
tTIiL
ns
tpUi
Propagation Delay Time
9
15
tDHL
AC ELECTRICAL CHARACTERISTICS(CL=60pF.lnput tr=t,=Bns)
Ta=-40 -85"C UNIT
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
Yo;; MIN. TYP. MAx. M1.L~. MAX.
Output Transition Time
Output Transition Time
tTUi
tnn..
4.5
5,5
Propagation Delay Time
tpUi
tpHL
4.5
5.5
-
8
7
15
13
12
11
5
17
18
16
10
Input (.;apacitance
CIN
Power Dissipation I,;apacitance (.;PD(l)
Note (1) Cro IS defmed as the value of the internal equivalent capacitance which
operating current consumption without load.
Average operating current can be obtained by the equation:
1o;;(:vO=CPD • Vo;;. fIN +10:: 14(per Gate)
HC-123
--
-
18
19
16
23
20
10
ns
pF
calculated from the
NOTES
-----TC74HC03AP/AF/AFN
QUAD 2-INPUT NAND GATE (OPEN DRAIN)
The TC74HC03A is a high speed CMOS 2-INPUT
NAND GATE fabricated with silicon gate C 2 MOS
technology .
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Pin configuration and function are the same as the TC74
HCOOA. But the TC74HC03A has, as its outputs, high
performance MOS N-channel transistors. (OPENDRAIN outputs) This device can, therfore, with a suitable
pull-up resistors, be used in wired-AND, LED driver
and other application.
All. inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. t.,z =5ns(Typ. )at Vee =5V
• Low Power Dissipation ............ lee=l.uA(Max.)at Ta=25"C
• High Noise Immunity· .. ·· .. · .. · .... VNIH=VNIL28% Vee (Min.)
• Output Drive Capability ........ ·· .. 10 LSTTL Loads
• Wide Operating Voltage Range ... Vee (opr.)=2V-6V
• Open Drain Structure
• Pin and Function Compatible with 74LS03
1
P(DIP14-P-300)
14~ 14~
1
FN(SOL14-P-150) I
F(SOP14-P-300)
PIN ASSIGNMENT
1A
1B
Vee
2
1Y 3
2A 4
2B 5
2Y 6
9
7
8
GND
(TOP VIEW)
IEC LOGIC SYMBOL
lA
18
TRUTH TABLE
&
lY
2A
28
2Y
3A
38
4A
48
3Y
4Y
"A-
B
Y
L
L
Z
L
H
Z
H
L
Z
H
H
L
Z : High Impedance
HC-125
4B
4A
4Y
38
3A
3Y
TC74HC03AP/AF/AFN--------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vcr;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
, UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
°C
°C
VALUE
-0.5 -7
-Q.5 -Vcr; +0.5
-0.5 -Vcr;+0.5
±20
±20
+25
±50
500(DIP) *1I80(MFP)
-65 -150
300
SYMBOL
Vcr;
V,:\
VOLT
11K
10K
IOLT
Icr;
PD
Tstg
TL
*500m W in the range of Ta=
-4Q"C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m Wj'C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vcr;
0- Vcr;
-40 - 85
o - 1000(Vcc =2.0V)
0- 500(Vcr;=4.5V)
0- 400(Vcr;=6.0V)
SYMBOL
Vcr;
V/\
VOLT
Topr
t r • tr
I
UNIT
V
V
V
I
OC
I
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
V1L
Low-Level
Output Voltage
Va.
Output
orr -State Current
I(l1;
Input Leakage Current
Quiescent Supply Current
11:\
lcr;
TEST CONDITION
VI:\=
VIHorVIL
Ia. =20J,tA
10/. -4 rnA
Ia. =5.2mA
VI:\ =V'HorV Il•
Va.T =Vcr;
V 1:\ -'Vcr; or GND
VI:\ -Vcr; or UND
Vcr;
2. 0
4. 5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
HC-126
Ta-25°C
Ta--40 -85°C
UNIT
MIN. TYP. ! MAX. MIN. i MAX.
1.5 I
1.5!
V
3.15 I 3.15 I i
4.2 ! 4.2 I
- iI 0.5 I 0.5 I
V
1. 35
1. 35
- I 1.8
1.8
- i O. 1
0.0 i O. 1
- I O. 1
I 0.0 I O. J
- I o 0 i 0.1
- ! 0.1 \ V
0.26
0.33
0.17
O. 18
O. 26
0.33
I
I
I
I
I
I
I
I
-
-
-
-
i
! ±0.5
I
:
::to. 1
I 1.0
-
-
I
±5.0
.J1,A
, ±1. 0 I
10.0 I
I
- - - - - - - - - - - - - - TC74HC03AP/AF/AFN
AC ELECTRICAL CHARACTERISTlCS(C L =15pF. Vcc=5V .Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTHL
Propagation Delay Time
tp!2
Propagation Delay Time
tpZL
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
RL=lkQ
-
5
12
Rt=lkQ
-
5
12
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =t,=6ns)
Ta--40 -85"C
Ta-25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
2.0
30
75
95
tTLH
Output Transition Time
4.5
8
19
15
tTHL
6.0
7
13
16
2.0
20
75
95
Propagation Delay Time
ns
tp!2
4.5
RL=lkQ
10
15
19
6.0
9
13
16
2.0
24
75
95
Propagation Delay Time
RL=lkQ
8
tpZL
4.5
15
19
6.0
7
13
16
Input Capacitance
5
10
10
C",\
Output Capacitance
Cu,T
pF
10
Power Dissipation Capacitance
CPD(1)
5
Note (J) C fl) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lee (l>!l=CPD • VCC· fIN +ICC 14(per Gate)
HC-127
TC74HC04AP/AF/AFN----HEX INVERTER
The TC74HC04A is a high speed CMOS INVERTER
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 3 stages. including
buffered output. which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=6ns(typ.) at Va:-=5V
• Low Power Dissipation ............... I a: =1 /.t A(Max. )at Ta=25"C
• High Noise Immunity ............... V:\II~=V:\,L=28" Va:(i~in.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance ... 11001 =1 0 . =4mA(Min.)
• Balanced Propagation Delays ...... tpl..l'" t pI~L
• Wide Operating Voltage Range .. • Va:(opr)=2V-6V
• Pin and Function Compatible with 74LS04
1
P(DIP14-P-300)
14~ 14~
1
F(SOP14-P-300)
PIN
FN(SOL 14-P-150)
ASSIGNMENT
1A
lY
2A
2Y
3A
3Y
GND
14
13
12
11
10
1
2
3
4
S
6
9
7
8
(TOP VIEW)
IEC
LOGIC SYMBOL
TRUTH
lA
lY
2A
2Y
3A
3Y
4A
TABLE
A
V
4Y
L
H
SA
SY
H
L
SA
6Y
HC-128
Vee
6A
6Y
SA
SY
4A
4Y
--------------TC74HC04AP/AF/A.FN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Yoltage Range
DC Input Yoltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI,\
VOLT
111\
101\
Io!:r
Icc
PI)
Tstg
TI.
VALUE
-0.5-7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
UNIT
V
V
i
! V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-4O'C- 65"C. From Ta=65'C
to 85'C a derating factor of
-10m WI"C shall be applied
until300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
Vex
VOLT
Topr
tr • tr
,
VALUE
2-6
o -Vee
0- Vee
-40 - 85
o - 1000(Vee =2.0V)
0- 500(Vl;e=4.5V)
0- 400(Vcc =6.0V)
I
I
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Le\'el
Input Voltage
VIH
Low-Le\'el
Input Voltage
VII.
High-Level
Output Yoltage
V is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IcctpFCPD • Va;. fl~ +Ia; 14(per Gate)
-
-
HC-1S2
-
TC74HC10AP/AF/AFN
TRIPLE
3-INPUT
NAND
GATE
The TC74HCI0A is a high speed CMOS a-INPUT
NAND GATE fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of a stages including
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP14-P-300)
14~14~
1
FEATURES:
• High Speed ................................. tpd=6ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc =1/1. A(Max.)at Ta=25"C
• High Noise Immunity··············· V,,;jH=V:\lL=28% Vcc(Min.)
• Output Drive Capability············ 10 LSTTL Loads
• Symmetrical Output Impedance ... 11 00 1=101.. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH"'tpHL
• Wide Operating Voltage Range ... Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LSI0
F(SOP14-P-300)
PIN
FN(SOL 14-P-150)
ASSIGNMENT
14
lA
1B 2
2A 3
2B 4
2C 5
11
3C
10
3B
2Y 6
9
7
8
3A
3Y
GND
(TOP VIEW)
IEC
LOGIC SYMBOL
TRUTH
lA
lB
TABLE
y
2A
A
L
X
X
H
2B
X
l
X
H
lC
2C
B
C
X
X
L
H
3B
H
H
H
L
3C
X : Don't Care
3A
HC-153
Vee
13 lC
12 1 Y
TC74HC10AP/AFIAFN----------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
Vee
VI:\
VOLT
i
i
UNIT
V
VALUE
-0.5-7
-0.5 -VCt· +0.5
-0.5 -Vc(+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
SYMBOL
11K
10K
Iot: r
lee
PD
Tsl g
TI.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
VALUE
iSYMBOL
Supply Voltage
2-6
i Vee
Input Voltage
V
:\
0- Vce
l I
! VOLT
Output Voltage
0- Vce
Operating Temperature
I Topr
-40 - 85
:
0- 1000(Vec =2.0V)
Input Rise and Fall Time j tr • tr
0- 500(Ve(=4.5V)
o- 400(Vcc=6.0V)
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
unti1300mW.
\'
V
rnA
rnA
rnA
rnA
mW
°C
"C
UNIT
\'
V
V
"C
ns
I
DC ELECTRICAL CHARACTERISTICS
PARAMETER
High-Level
Input Voltage
Low-Le\'el
Input Voltage
TEST CONDITION
SYMBOL
VIII
I
High-Level
Output Voltage
VII.
I
I
Val
I
I
I
1
Low-Level
Output Voltage
Input Leakage Current
Vcc
2.0
4.5
6.0
I 2.0
II 4.5
6.0
2.0
101 =-20J.tA 4.5
VI:\=
6.0
VlllorV". II(xl --4 rnA 4.5
=-5.2mA 6.0
I 2.0
lex. =20 J.t A 4.5
VI:\=
i 6.0
V"lorV". lex. =4 rnA 4.5
1(». =5.2mA 6.0
6.0
VI:\ -V(·c or GND
1 6.0
V 1'1: -Vec or GND
liar
I
VOL
II
Quiescent Supply Current !
11:\
ICC
I
I
I
HC-154
Ta-25"C
Ta- 40 -85"C UNIT
TYP. I MAX. :MIN. MAX.
1.5
t
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
- i 1.8 I
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0 I 5.9
4.13
4.18
4.31
5.68
5.80
5.63
0.0
0.1
0.1
0.1
0.0 t 0.1
I 0.0
V
O. 1
0.1
I 0.17 I 0.26
0.33
! 0.18 I 0.26
0.33
- ! =1.0
I ±0.1 '
J.tA
10.0
i ""'
i 1.0 i -
1\1I1\".
1.5
3.15
4.2
1
I
I
I
I
- - - - - - - - - - - - - - - TC74HC10AP/AF/AFN
AC ELECTRICAL CHARACTERISTICS{C L =15pF.Vcc =5V.Ta=25"C, Input t r =tf=6ns>
PARAMETER
SYMBOL
Output Transition Time
t·rI.l 1
Inll.
II~.H
Propagation Delay Time
t
~ II.
I
I
TEST CONDITION
I
MIN.
TYP.
-
4
8
-
6
12
UNIT
MAX.
--l
I
I
ns
AC ELECTRICAL CHARACTERISTICS{C L =50pF.lnput t r =tf=6ns>
Ta--40 -85"C
Ta-25"C
PARAMETER
UNIT
SYMBOL! TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
75
95
25
2.0 !
t'l"l.Il
Output Transition Time
4.5 ! 7
15
19
trilL
6.0 i 13
16
6
ns
I
2.0
27
75
95
t rul
Propagation Delay Time
4.5
15
19
9
Ipi II.
6.0
8
13
16
Input Capacitance
10
10
5
I C I\ I
pF
Power Dissipation Capacitance [ CI'D(!) I
23
Note (1) C I'D is defined as the "alue of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC t111l=C I'D· Va::. f 1\ + I cc / 4( per Gate)
I
I
i
I
I
HC-155
TC74HC11 AP/AF/AFN
TRIPLE 3-INPUT AND GATE
The TC74HCllA is a high speed CMOS 3-INPUT AND
GATE fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 4 stages including a
buffer output, which provide high noise immunity and
staple output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd =7ns(Typ.)at Vee=5V
• Low Power Dissipation ............ lee =1 tl A(Max.)at Ta=25"C
• High Noise Immunity··············· V:\IH =VN1L 28% Vee (Min.)
• Output Drive Capability······ ...... 10 LSTTL Loads
• Symmetrical Output Impedance "'1 IOH 1=101.. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range ... Vee (opr. )=2V -6V
• Pin and Function Compatible with 74LSll
1
P( DIP14-P-300)
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
1A
18
2A
28
2C
2Y
GND
14
13
12
11
10
2
3
4
6
9
1C
lY
3C
38
3A
7
8
3Y
5
(TOP VIEW)
IEC
LOGIC SYMBOL
lA
18
lC
2A
28
TRUTH TABLE
A
L
IV
2V
2C
3A
38
3V
HC-156
Y
L
B
C
X
X
X
L
X
X
X
L
L
L
H
H
H
H
X : Don't Care
3C
Vee
TC74HC11 AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)*/180(MFP)
-65 -150
300
SYMBOL
Vee
VI:>;
VOLT
11K
10K
IOLT
lee
PD
Tstg
TI.
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-40"C- 65·C. From Ta=65"C
to 85·C a derating factor of
-IOmW/"C shall be applied
until 300m W.
OC
OC
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vcc=6.0V)
SYMBOL
Vee
VI:>;
VOLT
Topr
Input Rise and Fall Time
tr , tr
UNIT
V
V
V
OC
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
Vill
Low-Level
Input Voltage
VIL
TEST CONDITION
I
High-Level
Output Voltage
VOI- I
I
V.=
[lOll =-20/.lA,
I:>;
i
i
VIHorVIL I
4
A
al m
1011 =-5. 2mA
r
I
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
I I:>;
IC:C
Il
=20 /.lA,
VI:>; =
, cl.
!
VlllorVII .
lIe}. -4 rnA I
; Ill. =5.2mA I
VI:>; -Vee or GND
I
VI:>; -Vee or GND
i
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-157
Ta--40 -85OC
Ta-25OC
UNIT
TYP. MAX. I MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
-4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
- , 5.63
5.68
5.80
0.1
0.0 i 0.1
i
0.1
0.1
0.0
V
0.1
0.0
0.1
O. Ii ! 0.26
0.33
0.18 I 0.26
0.33
=1.0
i ±0.1 i JJ.A
- I 1.0
10.0
MIN.
1.5
3.15
4.2
I
I
TC74HC11 A P / A F / A F N - - - - - - - - - - - - - - -
ACELECTRICAL CHARACTERISTICS(C L =16pF, Vcc=5V, Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTL11
tT1l1.
tplJ-1
Propagation Delay Time
TEST CONDITION
till-II.
MIN.
TYP.
MAX.
-
4
8
-
7
14
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =50pF,lnput t r =t,=6ns)
Ta--40 -85"C
Ta-25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
2.0
75
I
25
95
Output Transition Time I tTLII
4.5
7
15
19
I tonll.
6
13
16
6.0
ns
2.0
30
85
105
tplJ I
Propagation Delay Time
10
17
21
4.5
tpili.
9
6.0
14
18
I
Input Capacitance
5
10
10
CI~
pF
Power Dissipation Capacitance i CpD(l)
32
Note (l) C I'D is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC~=C po. Va;. f I~ +1 a; 13(per Gate)
I
I
HC-158
TC74HC14AP/AF/AFN
HEX SCHMITT INVERTER
The TC74HC14A is a high speed CMOS SCHMITT
INVERTER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Pin configuration and function are the same as the
TC74HC04A but the inputs have 25% Vc£ hysteresis and
with its schmitt trigger function, the TC74HC14A can be
used as a line receiver which will receive slow i.nput
signals.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=l1ns(typ.) at Vc£=5V
• Low Power Dissipation ............... IC£=IIlA(Max.)at Ta=25"C
• High Noise Immunity .. · .. · ........ · VH=1.1V at Vc£=5V
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance ···1 I rn 1=101.. =4mA(Min.)
• Balanced Propagation Delays ...... t pLH '" t li1L
• Wide Operating Voltage Range ... VC£(opr)=2V-6V
• Pin and Function Compatible with 74LS14
SYSTEM DIAGRAM,WAVEFORM
I
P(DIP14-P-300)
14Q14~
1
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
14 Vee
13 6A
12 6Y
11 5A
10 5Y
9 4A
8 4Y
1A
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND
7
(TOP VIEW)
IEC LOGIC SYMBOL
TRUTH TABLE
IA
IY
2A
2Y
3Y
4Y
5Y
6Y
3A
4A
SA
6A
HC-159
A
Y
L
H
H
L
TC74HC14AP/AF/AFN-------------~
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
VALUE
-0.5 -7
-0.5 -Vcc+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)*1180(MFP)
-65 -ISO
300
SYMBOL
Vee
VI-;
i
I
VOLT
11K
10K
IOLT
lee
PD
Tstg
TI.
UNIT
V
V
V
rnA
rnA
, rnA
rnA
mW
*500mW in the range of Ta=
-40"C- 65"C. 'From Ta=65"C
to 85"<: a derating factor of
-10m WI"C shall be applied
untiI300mW.
"C
"C
I
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
ISYMBOL
i
J
Vee
VI-;
I
VOLT
Topr
I
I
I
VALUE
2-6
UNIT
V
J V
V
I
!
"C
0- Vee
0- Vee
-40 - 85
DC ELECTRICAL CHARACTERISTICS
,
TEST CONDITIO~
PARAMETER SYMBOL t
Ta-25"C
Ta--40 -85"C IUNIT
Vee MIN. i TYP. MAX. MIN. JMAX.j
positive
2.0
1. 0 I I. 25
I. 5
I. 0
1. 5! V
Threshold
Vp ,
4. 5
2. 3 i 2.;
3. 15
2. 3 , 3.15
Voltage,
6. 0
3. 0 I 3. 5
4. 2
3. 0
4.2
Negative:
2.0
0.3 I 0.65
0.9
0.3! 0.9 !
2.0
V
Tht'eshold
V-; i
4.5
11. ~3
!.6
2.0
1.13
3
...V..;...::;ol:..:;ta:;sg<.:e'--_ _-+-__--'-________-+-..;6",.. .;;.0-+---;. ::l I~.
2.6
I. 5 J 2.6 i
2. 0
([3"! O. 6
1. 0 I o. 3 I 1. 0 ,i
Hysteresis
V
! 4. 5
O. 6 I 1. 1
I. 4 II O. 6 II 1. 4
Voltage
I
I
I
I
I
High-Level
Output Voltage
!
V(JJ
6. O!
2. 0
O. 8
1. 9
2. 0
I
V,OI.
I
I. 2
2. 0
l.i
= I
O. 8
1. 9
I.;
I I -
I
II
:
4.5
4.4 i 4.5
4.4
: "1-; =V II: f.-_--;-_---.-t---76.~0=_+----75.:..;;9:.".__1_1_6".,..;;.0-;-1__-_-+1----=;5""'.9;-".-+-_-_-1' V
,
1m --4 rnA 4.5
4.18 I 4.31
I, 4.13
!
;
1m =-5.2mA 6.0
5.68 i 5. 80 ~--=--c__+_.::::5.c.::6.::..3-i1--:c--c__+_1__ -j
I
Low-Level
Output Voltage
I
i
I
I
IIIai =-20tl A
I
'I
Vlv =VI'1
!
101. =20 tl A 1 4. 51
6.0
101. -4 rnA; 4.5'
II(x. =5.2mA I 6.0 I
, 'i
HC-160
-
-_
!
i
II,'
O. 0
O. 0
0 0
00:. 11-8/
O. I
O. I
0 I
26
00:. 2
6
I -
i
I
-
I -
![
II
-
,
, -
II,
o. I
o. I
0 I
0: 33
0.33
:
,I
i
i
V
--------------TC74HC14AP/AF/AFN
AC ELECTRICAL CHARACTERISTICS(C L =16pF. Vcc=6V .Ta=26"C)
PARAMETER
SYMBOL
Output Transition Time
tTLII
tTilI.
tpl.H
t r)IIL
Propagation Delay Time
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
11
21
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =tf=6ns)
Ta- 40 -85"C
Ta-25"C
PARAMETER
ISYMBOL TEST CONDITION Vec !I MIN. ! TYP. MAX. MIN. MAX. UNIT
75
95
30
2.0 !
tlUI
Output Transition Time
19
8
15
I
4.5
6.0
16
7
13
! tTHL
ns
2.0
125
155
42
tpUI
Propagation Delay Time
4.5
25
31
14
tplIl.
6.0
21
26
12
Input Capacitance
10
10
5
i C 1:\
pF
Power Dissipation Capacitance I Cp[)(l)
28
Notell) CI~) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lCCl\w=CPD • Va:. £1:\ +IU: 16(per Gate)
I
I
I
HC-161
TC74HC20AP/AF/AFN----DUAL 4-INPUT NAND GATE
The TC74HC20A i!! a high !!peed CMOS 4-INPUT NAND
GATE fabricated with !!ilicon gate C2MOS technology.
It achieve!! the high !!peed operation !!imilar to
equivalent LSTTL while maintaining the CMOS low power
di!!!!ipation.
The in"ternal circuit i!! compo!!ed of 3 !!tage!! including a
buffer output, which provide high noi!!e immunity and
!!table output.
All input!! are equipped with protection circuit!! again!!t
!!tatic di!!charge or tran!!ient exce!!!! voltage.
FEATURES:
• High Speed .....•...•.................... t(Xl=8ns(Typ.)at Vee=5V
• Low Power Di!I!!ipation ............ Iee=1JlA(Max.)at Ta=25"C
• High Noise Immunity .............. · VNIH=Vl\:IL28% Vee (Min.)
• Output Drive Capability .... · .... · .. 10 LSTTL Load!!
• Symmetrical Output Impedance "'1 Ia-J 1=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH '" tpHL
• Wide Operating Voltage Range'" Vee (opr)=2V -6V
• Pin and Function Compatible with 74LS20
1
P(DIP14-P-300)
14~14~
1
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
lA
14 Vee
18 2
13 20
NC 3
12 2C
lC 4
11 NC
10 5
10 28
lY 6
9
2A
GND7
8
2Y
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
lA
18
lC
A
B
C
D
Y
L
X
X
X
H
10
X
L
X
X
H
X
X
L
X
H
X
X
X
L
H
H
H
H
H
L
2A
28
2C
20
X : Don't Care
HC-162
---------------TC74HC20AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Va:r
11K
10K
IOlT
lee
PD
Tstg
TL
VALUE
-0.S-7
-O.S -Vee+O.S
-O.S -Vee+0.5
±20
±20
±2S
±SO
500(DIP) */180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m W/"C shall be applied
until 300m W.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI1\
VOUT
Topr
tr. tr
VALUE
2-6
0- Vee
o -Vee
-40 - 85
o - 1000(Vee =2.0V)
0- SOO(Vee =4.SV)
0- 400(Vee =6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIIi
Low-Level
Input Voltage
VII.
High-Level
Output Voltage
Vai
Low-Level
Output Voltage
Va.
Input Leakage Current
Quiescent Supply Current
11:\
Ic:e
TEST CONDITION
Vee MIN.
2.0
1.S
4.5
3. IS
6.0
4.2
2.0
4.5
6.0
2.0
1.9
laOI =-2011 A 4.S
4.4
VI1\=
6.0 I 5.9
VlliorVIL 1m --4 rnA
4.5
4.18
1m =-5.2mA 6.0
5.68
2.0
101.
=20
I1A 4.5
VIN =
6.0
VlllorVIL
10L -4 rnA 4.5
IOL =5.2mA 6.0
V IN -Vee or GND
6.0
6.0
VIN -Vee or GND
HC-163
Ta-2S"C
Ta--40 -85"C UNIT
TYP. MAX. MIN. MAX. I'
- I
1.S
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
4.5
4.4
V
6.0
5.9
4.31
4.13
5.80
5.63
0.0
0.1
0.1
0.0
O. I
O. I
V
O. I
0.0
0.1
0.17
0.26
0.33
0.18
0.26
0.33
±1.0
±O.l
I1A
10.0
1.0
TC74HC20AP/AF/AFN--------_-----
AC ELECTRICAL CHARACTERISTICS(CL =16pF.Vcc=6V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTlJi
tmL
tpLH
tnHI
Propagation Delay Time
TEST CONDITION
MIN.
TYP.
MAX.
-
5
8
-
8
15
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =60pF,lnput t r =tf=6ns)
Ta--40 -85"C
Ta-25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vo;:. MIN. TYP. MAX. MIN. MAX.
2.0
75
95
30
tlLH
Output Transition Time
4.5
15
19
8
tTliL
6.0
13
16
i
ns
2.0
44
90
115
tpUl
Propagation Delay Time
4.5
18
11
23
tJi-1L
6.0
9
15
20
Input Capacitance
C IN
10 ... pF
5
10
Power Dissipation Capacitance CPOW
29
Note(1) Cro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Io;:.~ =c PO • Vcr;. fiN +Icr; 12(per Gate)
HC-164
TC74HC21AP/AF/AFN
DUAL 4-INPUT AND GATE
The TC74HC21A is a high speed CMOS 4-INPUT AND
GATE fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 3 stages, including
a buffer output, which provide high noise immunity and
stable output.
I
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ............. <•••••••••••••••• tpd =10ns(Typ.)at Vee=5V
• Low Power Dissipation ............ Icc=1JlA(Max.)at Ta=25"C
• High Noise Immunity··············· V:\IH =V1\IL 2S% Vee (Min.)
• Output Drive Capability······ ...... 10 LSTTL Loads
• Symmetrical Output Impedance ... 1100 1=Ia.. =4mA(Min.)
• Balanced Propagation Delays ...... tpu-I" tpliL
• Wide Operating Voltage Range ... Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS21
P(DIP14-P-300)
14Q14~
1
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
lA
1"
18 2
13 20
NC 3
12 2C
1C
11 NC
"
10 5
Vee
10 28
lY 6
9
2A
ONO 7
8
2Y
(TOP VIEW)
IEC
LOGIC
SYMBOL
TRUTH TABLE
Outputs
Inputs
lA
18
lC
10
2A
28
2C
20
(13)
A
B
C
D
y
L
X
X
X
L
X
L
X
X
L
X
X
L
X
L
X
X
X
L
L
H
H
H
H
H
X : Don't Care
HC-165
TC74HC21AP/AF/AFN---------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Va/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Va:;
VIN
Vour
11K
10K
lour
I a:;
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Va:;+0.5
-0.5 -Va:;+0.5
±20
±20
±25
±50
500(DIP) *1l80(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40·C- 65·C. From Ta=65·C
to 85'C a derating factor of
-10m WI"C shall be applied
unti1300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Va:;
VI~
V~T
Topr
tr • tr
VALUE
2-6
0- Va:;
o -Vee
-40 - 85
o- 1000(Vcc =2.0V)
0- 500(Vee =4.5V)
o - 400(Va:;=6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vm
Low-Level
Output Voltage
VOl.
Input Leakage Current
Quiescent Supply Current
II:"
lee
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
1m =-20# A 4.5
VI!\: =
6.0
VII10rVIL
1m --4 rnA 4.5
1m =-5. 2mA 6.0
2.0
101.. =20 # A 4.5
Vr,=
6.0
VII10rVIL
101.. -4 rnA 4.5
101.. =5.2mA 6.0
6.0
VI,\ -Va:; or GND
I 6.0
VI:" -Va:; or GND
HC-166
Ta-25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4. 13
4.18
5.68
5.80
5.63
0.1
0.1
0.0
O. 1
0.1
0.0
V
0.1
O. 1
0.0
0.26
0.33
0.17
0.26
O. 18
0.33
±1.0
±0.1
#A
1.0
10.0
MIN.
1.5
3.15
4.2
-----------------------------TC74HC21 AP/AF/AFN
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=6V.Ta=26"C)
PARAMETER
SYMBOL
Output Transition Time
tn.H
t'nlL
tpLH
Propagation Delay Time
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
10
17
UNIT
ns
tDllL
AC ELECTRICAL CHARACTERISTICS(C L =60pF .Input t r =tf=6ns)
Ta-25"C
Ta- 40 -85"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vcc MIN. TYP. MAX. MIN. MAX.
2.0
75
95
30
tTU-I
Output Transition Time
4.5
8
15
19
tTHL
6.0
7
13
16
ns
2.0
125
40
100
tpU-I
Propagation Delay Time
4.5
13
20
25
tpl-lL
6.0
17
21
11
Input Capacitance
C IN
5
10
10
pF
Power Dissipation Capacitance
Cpo(J)
25
Note (1) C m is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC (xJD=C po. VOC· f 1:'1 +I OC /2( per Gate)
HC-167
TC74HC27AP/AF/AFN
TRIPLE 3-INPUT NOR GATE
The TC74HC27A is a high speed CMOS 3-INPUT NOR
GATE fabricated with silicon gate C~OS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 3 stages including
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=7ns(typ.)at Vee=5V
··Low Power Dissipation ............... Iee=1J./A(Max.)at Ta=25"C
• High Noise Immunity .............. · V:-;IH=V:-;IL=2896 Vee (Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance .. ·1 1m 1=10\.. =4mA(Min.)
• Balanced Propagation Delays ...... tpUi"'tpHL
• Wide Operating Voltage Range ... Vee (opr)=2V-6V
• Pin and Function Compatible with 74LS27
P(DIP14-P-300)
14~14~
1
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
1A
14 Vee
13 1 C
12 1 Y
18 2
2A 3
28 4
11 3C
10 38
2C 5
2Y 6
GND
7
9
3A
8
3Y
(TOP VIEW)
lEe LOGIC SYMBOL
TRUTH TABLE
IA
IB
A
B
C
Y
H
X
X
L
2B
X
H
X
L
2C
3A
X
X
H
L
3B
L
L
L
H
3C
X: Don't Care
Ie
2A
HC-168
-----------------------------TC74HC27AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 ~-I50
300
SYMBOL
Vee
VI\
VOLT
11K
10K
IOLT
Icc
Po
Tstg
TJ.
UNIT
V
V
V
rnA
rnA
rnA
rnA
m\V
°C
°C
*500m W in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAl\1ETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Ris, Md Fan Tim'
SY~IBOL
I
Vee
VI\;
VOLT
Topr
It"
"
,
I
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500'(Vee=4.5V)
o - 400(Vee =6.0V)
UNIT
V
V
V
°C
ns
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
High-Level
Input Voltage
Low-Level
Input Voltage
,i
VIII
,
I
High-Level
Output Voltage
VII.
VC~1
I
i
Low-Level
Output Voltage
Input Leakage Current
Quiescent Supply Current
I
!
VOL
II\;
ICC
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
I 6.0
2.0
ICli =-20t.t A 4.5
VI\; =
6.0
VlllorVIl .
IOH - 4 rnA 4.5
I(ll =-5.2mA 6.0
2.0
IoJ. =20 t.t A 4.5
VI\; =
6. 0
VlllorVIl .
i I(~. -4 rnA 4.5
I(~. =5.2mA
6.0
I \'I\; -Vee or GND
6. 0
6.0
I VI\; =V ce or GND
HC-169
Ta--40 -85°C
Ta-25°C
UNIT
TYP. ,MAX, l\lIN. MAX.
I
1.5
1.5
,
V
i
3. 15
3.15
4.2
4.2
i I 0.5
0.5
I V
iI 1. 35
1. 35
i 1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
5. 9
6.0
5.9
I V
4.13
4.18
4.31
5.63
5.68
5.80
0.0
O. 1
0.1 I
0.1 I 0.1 I
0.0
0.1 j V
I 0.0 i 0.1 ! I 0.17 I 0.26
0.33 i
0.26
0.33 i
i 0.18
±1. 0 ' A
I ±O.l
I
10.0 t.t
I 1.0
MIN.
I
I
I
TC74HC27AP/AF/AFN--------------
AC ELECTRICAL CHARACTERISTICS(CL =15pF. Vcc=5V. Ta=25"C. Input t r =t,=6ns)
PARAMETER
Output Transition Time
Propagation Delay Time
SYMBOL
TEST CONDITION
!
I
t'l't.II
tTIII.
t pt.ll
t pili.
MIN.
TYP.
MAX.
-
4
8
-
7
15
IUNIT
I ns
I
AC ELECTRICAL CHARACTERISTICS(CL=50pF.lnput t r =t,=6ns)
Ta-25"C
Ta- 40 -85"C IUNIT
PARAMETER
SYMBOL TEST CONDITION ! V
, cc MIN. TYP. I MAX. MIN. MAX.l •
2.0
25
75
95
t'l.H
Output Transition Time
4.5
7
15
19
t1lfL
6.0
6
13
16
ns
2.0
30
90
115
I
tlll..l-I
Propagation Delay Time
4.5
10
18
23
tl~iL
6.0
9
15
20
.Input Capacitance
5
C 1\
10 i 10 I pF
- I - 1
Power Dissipation Capacitance cpom
25
Note(l) C R) is defined as the value of the internal equi\'alent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC(lld=CPD· Vcc·fl\ +Icc /3(per Gate)
~
I
I
I
HC-170
-
I
TC7 4HC30AP I AF I AFN
8-INPUT NAND GATE
The TC74HC30A is a high speed CMOS S-INPUT
NAND GATE fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 5 stages including
buffered outputs, which provide high noise immunity aI\d
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd=12ns(typ.)at Vo:;=5V
• Low Power Dissipation .....•...... 10:;=1 ttA(Max.)at Ta=25"C
• High Noise Immunity··············· V:\Ui=V1\IL2S% Vo:;(Min.)
• Output Drive Capability············ 10 LSTTL Loads
• Symmetrical Output Impedance ···1 Iai 1=101. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range ... Yo:; (opr.)=2V-SV
• Pin and Function Compatible with 74LS30
1
P( DIP18-P-300A)
F(SOP18-P-300)
PIN ASSIGNMENT
A 1
B 2
C 3
0 4
E 5
F 6
14 Vee
13 NC
12 H
11 G
10 NC
9 NC
8 y
GND7
NC:No
Connection
TRUTH TABLE
IEC LOGIC SYMBOL
A
FN(SOL 16-P-150)
&
Inputs
B
Outputs
C
o
All Inputs High
E
L
.--
F
G
All Other Combinations
H
HC-171
H
TC74HC30AP/AF/AFN - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
V!:'-.J
VOLT
11K
10K
1000T
Icc
PD
Tstg
TL
VALl'E
-0.5-7
-0.5 -Vcc+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)*/180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
o -Vee
0- Vee
-40 - 85
o- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
SYMBOL
Vee
VI"
Vcx.,T
Topr
t r , tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
V1H
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
V(L
Input Leakage Current
Quiescent Supply Current
II"
lee
TEST CONDITION
VI" =
VIHorVIl .
VI" =
VIHorVIl•
IOH =-201l A
IOH --4 rnA
lai =-5.2mA
I(L =20 IlA
Ia. -4 rnA
la. =5.2mA
VI" -Vee or GND
VI" =V cc or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-172
Ta- 40 -85"C 'NIT
Ta-25"C
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
-V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.1
0.1 ,
0.0
0.0
O. I
0.1
V
O. I
O. I
0.0
0.26
0.33
0.17
0.33
0.26
0.18
_1.0
±O.I
IlA
. 1.0
10.0
MIN.
1.5
3.15
4.2
-
-
- - - - - - - - - - - - - - TC74HC30AP/AF/AFN
AC ELECTRICA L CH ARACTERISTICS(C L =15pF. Vcc=5V, Ta=25"C. Input tr=tf =6n8)
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTHL
tpLH
tpHL
Propagation Delay Time
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
12
19
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =60pF,lnput t r =tf=6n8)
Ta-25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
75
95
30
tTLH
Output Transition Time
15
19
8
tTIiL
7
13
16
ns
45
115
145
tpLH
Propagation Delay Time
29
15
23
tpHL
20
25
13
Input Capacitance
5
10
10
C'N
pF
Power Dissipation Capacitance
CPD(l)
20
Note (1) C R) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iex;QJIj=C po. Va;. {,:-: +Ia;
PARAMETER
SYMBOL TEST CONDITION
Vex;
2.0
4.5
6.0
2.0
4.5
6.0
HC-173
MIN.
TC74HC32AP/AF/AFN----QUAD
2-INPUT
OR
GATE
The TC74HC32A is a high speed CMOS 2-INPUT OR
GATE fabricated with silicon gate C2MOStechnology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 2 stages including
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=6ns(typ.)at Vcc=5V
• Low Power Dissipation ............... Icc =IIlA(Max.)at Ta=25'C
• High Noise Immunity ............... V~1I1 =V~IL =28111 Vcc(Min.)
• Output Drive Capability············ 10 LSTTL Loads
• Symmetrical Output Impedance ···II OH 1=10. =4mA(Min.)
• Balanced Propagation Delays ... tpUi ""tpHL
• Wide Operating Voltage Range ... Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LS32
1
P(DIP14-P~300)
14~'4~
1
F(SOP14-P-300)
PIN
FN(SOL 14-P-150)
ASSIGNMENT
lA
1B
1Y
2A
2B
2Y
GND
14
13
12
11
10
2
3
4
5
6
9
7
8
(TOP VIEW)
IEC
LOGIC
SYMBOL
IA
IB
2A
2B
3A
3B
4A
4B
TRUTH
IY
2Y
3Y
4Y
HC-174
TABLE
A
B
Y
H
H
H
L
H
H
H
L
H
L
L
L
Vee
4B
4A
4Y
3B
3A
3Y
--------------TC74HC32AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
!SYMBOLI
I Vee
I Vr,
I VOLT
I u.;
,i
I(~.;
i
IOL.,.
I
I
I
I
i
I
Icc i
PD i
! Tstg
i
I TL I
I
II
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5 -7
-0.5 -VCC+0.5
-0.5 -Vcc+0.5
±20
±20
±25
±50
500(DIP) */ 180(MFP)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65'C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
!SYMB0L[
i Vee
I
iI
I
VI:-.:
VOLT
I
I Topr
i
I
It,. tr I
Input Rb, and Fall T;m,
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vcc =2.0V)
0- 500(Vcc =4... 5V)
o - 400(Vce =6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
SYMBOL
I
High-Level
Input Voltage
VIII
I
Low-Level
Input Voltage
ViI.
High-Le\'el
Output Voltage
Val
PARAMETER
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
I
lUi =-20Jl A 4.5
VI:-':=
6.0
VlllorVIL
11m --4 rnA 4.5
,1011 =-5.2mA 6.0
2.0
101. =20 Jl A 4.5
"1:-':=
i 6.0
"Ul orV". I(x. =4 rnA 4.5
II(x. =5.2mA 6.0
i 6.0
"1:-': -\ec or GND
I 6.0
VI:-': -Vee or GND
I
I
I
Low-Level
Output Voltage
Input Leakage Current
Quiescent Supply Current
VOL
I
i
11:-,:
IcC
!
HC-175
Ta-25"C
Ta- 40 -85"C 'UNIT
MIN. I TYP. i MAX. MIN. MAX ..
:
1.5
1.5
i
V
3.
15
3.15 .
- Ii - I
4.2
4.2
0.5
0.5
- II 1. 35
V
1. 35
1.8 !
I 1.8
2.0
1.9
1.9
!
,
- II!
4.4
4.4
4.5 I - i V
5.9
6.0
5.9
4.31 II 4. 13
4.18
5.63
5.68
5.80 : 0.0 i 0.1
0.1
0.0
0.1
0.1
V
0.1
0.0
0.1
I
0.26
0.33
0.17
I
I
I
0.18
0.26
0.33 !
I
- ! ::0.1
±1. 0 '
:
10.0 1 /.lA
- i - , 1.0
-
I
I
I
I
i
I
-
I
I
-
i
TC74HC32AP/AF/AFN--------------
AC ELECTRICAL CHARACTERISTICS(C L =15pF, Vcc=5V ,Ta=25"C. Input t r =tf=6ns)
PARAMETER
snlBOL
Output Transition Time
tT1.I1
Jm.
Propagation Delay Time
I
I
TEST CONDITION
TYP.
MAX.
-
4
8
-
6
12
UNIT
ns
tl~.I1
t
MIN.
I
~IL
I
AC ELECTRICAL CHARACTERISTICS(C L =50pF,Input t r =tf=6ns)
Ta-25"C
i Ta- 40 -85"C UNIT
PARAMETER
SYMBOL' TEST CONDITION
Vee WN. TYP. MAX. MIN. MAX.
2.0
25
75
95
Output Transition Time I trLlI
4.5
7
15
19
6.0
13
6
16
I tTllL
ns
I
2.0
24
75
95
I
tl~.I1
Propagation Delay Time
4.5
8
15
19
tl~IL
'6.0
7
13
16
Input Capacitance
5
10 i
10
I (;1:\
I
pF
Power Dissipation Capacitance I Cpt)! 11
I
I
i 21
Note III C I~) is, defined as the ,'alue of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IcC(IlI"=C I~)· V(l'. f" +1 (C 14(per Gate)
I
I
-
I
J
I
I
HC-176
-
-------TC74HCT32AP/AF
QUAD 2-INPUT
OR
GATE
The TC74HCT32A is a high speed CMOS 2-INPUT OR
GATE fabricated with silicon gate c2Mos technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL,NMOS and CMOS output
voltage levels.
· All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd=9ns(typ.)at Vcr;=5V
• Low Power Dissipation ............ Icr;=l.uA(Max.)at Ta=25"C
• Compatible with TTL outputs· .... • VIH =2V(Min)
VIL =0.8V(Max.)
• Wide interfacing ability .. ·· .. ··• LSTTL,NMOS,CMOS
• Output Drive Capability········· 10 LSTTL Loads
• Symmetrical Output Impedance ···1 Iail=IOL =4mA(Min.)
• Balanced Propagation Delays ..•... tpLH"tpHL
• Pin and Function Compatible with 74LS32
1
P(DIP14-P-300)
14~
1
F{SOP14-P-300)
PIN
ASSIGNMENT
1A
14 Vee
18
2
13
48
lY
3
12
4A
2A
4
11
4Y
28
5
10
38
2Y
6
9
3A
GND
7
8
3Y
{TOP VIEW)
IEC
LOGIC
SYMBOL
lA
18
2A
28
3A
38
4A
48
TRUTH
TABLE
lY
A
B
Y
2Y
H
H
H
L
H
H
3Y
H
L
H
4Y
L
L
L
HC-177
TC74HCT32AP/AF - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Va;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Va;
VI"
VCJl,j
11K
10K
ICJl,j
Ia;
Po
Tstg
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
VALUE
-0.5-7
-0.5 -Va; +0.5
-0.5 -Va;+O.5
±20
±20
±25
±50
500(DIP) */180(SOIC)
-65 -150
300
*500m W in the range of Ta=
-40'C";'" 65'C. From Ta=65·C
to 85'C a derating factor of
-lOmW/'C shall be applied
until 300m W.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Va;
VIX
VCJl,j
Topr
tr, tr
VALUE
UNIT
V
V
V
4.5 - 5.5
0- Va;
O-Va;
-40 - 85
0-500
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Low-Level
Output Voltage
Input Leakage Current
Quiescent Supply Cumnt
TEST CONDITION
MIN.
1
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
--
4.4
4.13
-
V
5.5
4.5
Voo.
VCJl,
II!"
Ia;
dIce
Ta= 40 -85"C
Ta=25"C
UNIT
TYP. MAX. MIN. MAX.
Va;
4.5
1
5.5
4.5
4.5
4.5
4.5
5.5
5 5
YIN =
100 - 20 Jl A
VIHorVIL 100 =-4 mA
ICJl, -20 Jl A
YINVIHorVIL 1CJl, -4 mA
VI:-J =Vccor GND
VI:>: =Va;or GND
PER INPGT: VI" =0. 5V or 2.4V
5.5
OTHER INPGT:Va; or GND
HC-178
4.4
4.18
-
4.5
4.31
0.0
0.17
-
-
0.1
0.26
±O.l
1.0
2.0
-
0.1
0.33
±1.0
10 0
2.9
V
JlA
mA
- - - - - - - - - - - - - - - - - TC74HCT32AP/AF
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc =5V.Ta=25"C.lnput t r =t,=6ns}
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTHL
tpLH
toHL
Propagation Delay Time
TEST CONDITION
MIN.
TYP.
MAX.
-
6
12
-
10
16
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =t,=6ns}
Ta=-40 -85"C UNIT
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
Vee MIN. TYP. MAx. MIN. MAX.
Output Transition Time
tTLH
tTHL
4.5
5.5
-
-
8
7
15
13
Propagation Delay Time
tpLH
tpHL
4.5
5.5
-
13
20
18
10
-
11
5
CI~
Power Dissipation (;apacitance Cpo(l)
23
Note (!) Cpo IS defmed as the value of the internal equivalent capacitance which
operating current consumption without load.
Average operating current can be obtained by the equation:
leeq,o=C po· Va; of I~+I a; 14(per Gate)
Input Capacitance
HC-179
-
-
IS
-
19
16
-
25
23
10
ns
pF
calculated from the
NOTES
-----TC74HC42AP/AF/AFN
BCD-TO-DECIMAl DECODER
The TC74HC42A is a high speed CMOS BCD-toDECIMAL DECODER fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
A BCD code applied to the four inputs (A-D)' sets a low
level at one of ten decoded outputs. A illegal BCD code
such as eleven thru fifteen sets all outputs high. This
device can be used as 3-to-8 LINE DECODER when input
D is held low.
This device is useful for code conversion, address
decoding, memory selection, multiplexing, or readout
decoding.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP16-P-300A)
F(SOP16-P-300)
FN(SOL16-P-150)
PIN ASSIGNMENT
FEATURES:
• High Speed .............................. tpd=13ns(Typ.)at Vcc=5V
• Low Power Dissipation ............ Icc=4IlA(Max.)at Ta=25"C
• High Noise Immunity .............. · V:-':IIi =V:-':IL=2896 Vcc(Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance "'1 Ioo 1=IOI.=4mA(Min.)
• Balanced Propagation Delays ...... tpul "'tpilL
• Wide Operating Voltage Range'" Vcc(opr)=2V-6V
• Pin and Function Compatible with 74LS42
YO
Vl
16
2
Y2 3
..
14 8
V3
13 C
1(..
5
12 0
V5 6
11 V9
V6 7
10 V8
GND 8
9
(TOP VIEW)
IEC LOGIC SYMBOL
BCD/DEC
(I) Vo
2 VI
V2
V3
A
B
V4
C
'i&
'i8
'i7
'i8
'is
o
HC-181
Vee
16 A
V7
TC74HC42AP/AF/AFN - - - - - - - - - - - - - -
TRUTH
TABLE
CODE
0
0
L
L
L
L
L
L
L
L
H
H
H
H
1
2
3
4
5
6
7
a
9
x;
SYSTEM
BCD INPUTS
No.
C
L
L
L
L
H
H
H
H
L
L
X
H
B
L
L
H
H
L
L
H
H
L
L
H
X
DECIMAL OUTPUTS
A
L
H
L
H
L
H
L
H
L
H
X
X
YO
Yl
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
Y2
H
H
L
H
H
H
H
H
H
H
H
H
Don't care
DIAGRAM
HC-182
Y3
H
H
H
L
H
H
H
H
H
H
H
H
Y4
H
H
H
H
L
H
H
H
H
H
H
H
Y5
H
H
H
H
H
l
H
H
H
H
H
H
Y6
H
H
H
H
H
H
L
H
H
H
H
H
Y7
ya
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
Y9
H
H
H
H
H
H
H
H
H
L
H
H
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC42AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vac/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Va:.
VI:\
VOCT
11K
10K
10l:r
Icc
PD
Tstg
TJ.
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 - Va:. +0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
UNIT
V
V
-V
mA
mA
mA
mA
mW
"C
"C
*500m W in the range of Ta=
-4Q'e- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
VALUE
2-6
0- Vac
0- Vac
-40 -- 85
o -- 1000(Vee =2.0V)
0- 500(Vac =4.5V)
0- 400(Vac =6.0V)
SYMBOL
Vac
VI:\
VOLT
Topr
Input Rise and Fall Time
t r • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
High-Level
Input Voltage
!SYMBOL I
I
I
TEST CONDITION
VIII
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VI:\=
Vall i Vll1or'V
n•
I
I
I
I
I
Low-Level
Output Voltage
Vell•
I V)",=
I VI;lorV1L
!
Input Leakage Current I
Quiescent Supply Current
11:\
Icc
I
!
1m =-20IJ. A
1m - 4 mA
101i =-5.2mA
IelL =20 IJ.A
la. -4 mA
ICli. =5.2mA
VI'; -Vee or GND
V1:\ -Vee or GND
Va:.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-183
Ta-25"C
Ta--40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5 1
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.4
4.5
V
6.0
5.9
5.9
4.18
4.31
4.13
5.80
5.63
5.68
O. I
0.0
O. I
O. I
0.0
0.1
V
0.1
0.0
O. I
0.33
0.17
0.26
0.33
0.18
0.26
±O.I
±1.0
IJ.A
40.0
! 4.0
MIN.
1.5
3.15
4.2
TC74HC42AP/AF/AFN - - - - - - - - - -......- - -
AC ELECTRICAL CHARACTERISTICS(CL =15pF,Vcc =5V,Ta=25"C.lnput t r =t,=6ns)
PARAMETER
SYMBOL
Output Transition Time
tTLH
trilL
tpl.H
tpllL
Propagation Delay Time
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
13
25
-
II
I
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(Cl =50pF,lnput t r =t,:;:6ns)
Ta-25"C
Ta- 40 '-85"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vee MIN. ! TYP. i MAX. MIN. MAX.
2.0
75
95
30 I
t'l.H
Output Transition Time
4.5
8
15
19
tTlll
6.0
7
13
16
ns
48 I 145
180
2.0
I
tpt.H
Propagation Delay Time
4.5
16 I 29
36
tP/iL
6.0
14 i 25
31
Input Capacitance
5 i
CI:'\
10
10
pF
Power Dissipation Capacitance CPDm
68 I
Note(!) C m IS defmed as the value of the mternal equivalent capacitance which IS calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCtW =C I'D· Va;. fl:,\ +Ia; 14(per Gate)
I
i
HC-184
I
-----TC74HC51AP/AF/AFN
DUAL 2 WIDE-2 INPUT AND/OR INVERT GATE
,------------------------,
The TC74HC51A is a high speed CMOS 2-WIDE
2-INPUT/3-INPUT AND/OR/INVERT GATE fabricated
with silicon gate C2MOS technology:.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It contains a 2-WIDE 2-INPUT AND/ORIINVERT
GATE and a 2-WIDE 3-INPUT AND/ORIINVERT
GATE.
The internal circuit is composed of 3 stages (2-INPUT)
or 5 stages (3-INPUT) including buffer outputs. which
provide high noise immunity and stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP14-P-300)
14~14~
1
F(SOP14-P-300)
FEATURES:
• High Speed .............................. tp:j= 10 ns(Typ.)atVee=5V
• Low Power Dissipation ............... Iee=1 ttA(Max.)atTa=25"C
• High Noise Immunity··············· V\iIH=V"IL=28" Vee(Min.)
• Output Drive Capability'" ......... 10 LSTTL Loads
• Symmetrical Output Impedance "'1 I(l-l 1=101.. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH""tpHL
• Wide Operating Voltage Range ... Vee (opr)=2V -6V
• Pin and Function Compatible with 74LS51
FN(S0L14-P-150)
PIN ASSIGNMENT
1A
14
2
13 lC
28
3
12 18
2C
4
11 IF
20
5
10 IE
2Y
6
9 10
GNO 7
8
(TOP VIEW)
IEC LOGIC SYMBOL
IA
IB
IC
IV
ID
IE
IF
2A
2B
2V
2C
2D
HC-185
V~
2A
lY
TC74HC51 AP/AF/AFN - - - - - - - - - - - - - - -
TRUTH TABLE
INPUTS
OUTPUT
1A 18 1C 1D 1E 1F
1Y
H H H X X X
L
X X X H H H
L
All other combinations
H
INPUn
OU1PUT
2A
2C
2D
2Y
28
H
H
X
L
X
X
X
H
L
H
All other combinations
H
X:Don't care
X:Don't care
SYSTEM DIAGRAM
1A
1B
1C
8 1Y
10
1E
1F
2A
2B
6 2Y
2C
20
HC-186
- - - - - - - - - - - - - - TC74HC51AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Vour
11K
10K
lOUT
lee
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5-7
-0;5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
*500m W in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee=6.0V)
SYMBOL
Vee
VI:\
VOlrr
Topr
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Va;
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
11:\
lee
TEST CONDITION
VI:\ =
VIHorVIL
VI:--;=
VIHorVIL
Iai =-20/1. A
Ia; - 4 rnA
Ial =-5.2mA
101.
=20 /1. A
-4 rnA
lor. =5.2mA
V I:-; -'Vee orGND
V 1:-': -Vee or GND
I(~.
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-187
MIN.
1.5
3. 15
4.2
1.9
4.4
5.9
4. 18
5.68
-
-
Ta-25"C
Ta--40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
- II V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
'1.8
1.8
2.0
1.9
4.5
4.4
V
6.0
5.9
4.31
4. 13
5.80
5.63
.0.1
0.1
0.0
0.1
0.0
0.1
V
, 0.0
O. 1
0.1
0.26
0.33
0.17
0.33
0.26
0.18
±O.l
±1.0
/1. A
10.0
1.0
-
TC74HC51AP/AF/AFN - - - - - - - - - - - - - -
AC ELECTRICAL CHARACTERISTICS(C L =16pF. Vcc=6V.Ta=26"C. Input .t r =tf=6ns)
PARAMETER
Output Transition Time
Propagation Delay Time
SYMBOL
TEST CONDITION
tTLH
tnll.
tpLH
tpHL
MIN.
TYP.
MAX.
-
4
8
-
10
17
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =60pF.lnput t r =tf=6ns)
Ta-~40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
75
30
95
tTLIi
Output Transition Time
8
15
19
tl1iL
7
13
16
ns
39100
125
tpLH
Propagation Delay Time
13
20
25
tpHL
11
17
21
Input Capacitance
5
CI~
10
10
pF
Power Dissipation Capacitance CPD(l)
35
Note(l) em is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lee q,o =C PD • Voc • f I~ + Ioc /2(per Gate)
PARAMETER
SYMBOL TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
HC·188
MIN.
TC74HC73APIAF
DUAL J-K FLIP FLOP WITH CLEAR
. The TC74HC73A is a high speed CMOS DUAL J-K FLIP
FLOP fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Depending on the logic levels applied to J and K input,
this device changes state on the negative going transition
of clock input pulse (CK).
The clear function is accomplished independently of the
clock condition when the clear input (CLR) is taken low.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. f~=55MHz(Typ.)Vee=5V
• Low Power Dissipation .•............. Iee =2.uA(Max.)Ta=25"C
• High Noise Immunity··············· V:'1H=V:\IL =28" Vee (Min.)
• Output Drive Capability·'· ......... 10 LSTTL Loads
• Symmetrical Output Impedance "'1100 1=Ia.. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH ... tpllL
• Wide Operating Voltage Range ... Vee (opr)=2V-6V
• Pin and Function Compatible with 74LS73
1
P(DIPI4-P-300)
14~
1
F(SOPI4-P-300)
PIN ASSIGNMENT
TRUTH TABLE
OUTPUTS
INPUTS
CLR
J
K
L
x
X
H
L
L
H
H
L
H
L
H
H
H
H
H
X
X
X : Don't Care
CK
X
1..
1..
1.
1..
.r
a
L
an
L
H
an
an
a
H
an
H
L
an
an
lCK
IClR 2
1K 3
FUNCTION
Clear
No Change
-
Vec
4
2CK
2ClR
2J
5
6
7
Toggle
No Change
(Top View)
IEC LOGIC SYMBOL·
lJ
lCK
lK
lC L R
2J
2CK
2K
2CL R
(14)
(1) ....
(3)
(2) •
lJ
Cl
lK
R
(12)
10
(13)
(7)
(9)
(5) ....
(10)
(6)
(8)
HC-189
14 lJ
13 10
12 10
11 GND
10 2K
9 20
8 20
20
TC74HC73AP/AF--------------------------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipatiori
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
Voor
11K
10K
loor
lee
PD
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)*/180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range" of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
UNIT
V
V
V
"C
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vee =2.0V)
0- 500(Vee =4.5V)
0- 400(Vee =6.0V)
SYMBOL
Vee
VIN
VOlrr
Topr
t r • tr
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
Vu.
High-Level
Output Voltage
Va--r
Low-Level
Output Voltage
Vor.
Input Leakage CUlTent
Quiescent Supply Current
1,:-.:
lee
TEST CONDITION
VI:>: =
VIHorVIL
VI:-<=
VuiorVIL
la--r =-20 It A
Ia--r - 4 rnA
la--r =-5.2mA
lor. =20 It A
lor. -4 rnA
lor. =5.2mA
VI:" -Vee or uND
VI:X -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-190
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
l.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.18
4.31
4.13
5.68
5.80
5.63
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.0
0.1
0.33
0.26
0.17
0.33
0.18
0.26
±0.1
±1.0
itA
20.0
2.0
MIN.
1.5
3. 15
4.2
-
-
- - - - - - - - - - - - - - - - TC74HC73AP/AF
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
two,,)
twan
Minimum Pulse Width
(CLR)
tW(L)
Minimum Set-up Time
ts
Minimum Hold Time
tb
Minimum Removal Time
(CLR)
Clock Frequency
trem
f
Vcc
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C
LIMIT,
TYP.
75
15
13
75
15
13
75
15
13
0
0
0
75
15
13
6
30
35
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
95
ns
19
16
0
0
0
95
19
16
5
MHz
24
28
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
Output Transition Time
Propagation DeiaLTime
(CLOCK-Q.Q)
Propagation De19 Time
(CLR-Q.Q)
Maximum Clock Frequency
SYMBOL
TEST CONDITION
tTLH
tTHl
tpLH
tpHL
tpLH
tnHL
f MAX
MIN.
TYP.
MAX.
-
6
12
-
11
21
-
15
25
35
75
UNIT
ns
MHz
AC ELECTRICAL CHARACTERISTlCS(C L =60pF.lnput t r =t,=6ns)
Ta- 40 -85"(;
Ta-25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vcc MIN. TYP. MAX. MIN. MAX.
2.0
30
75
95
t1LH
Output Transition Time
4.5
8
15
19
tTJ-IL
6.0
7
13
16
2.0
42
125
155
Propagation DeiaLTime
tpLH
ns
4.5
14
25
31
(CLOCK-Q. Q)
tpJ-IL
6.0
12
21
26
2.0
54
145
180
Propagation Del!>, Time
tpLH
4.5
18
29
36
(CLR-Q.Q)
tpHL
6.0
25
15
31
-2.0
6
15
5
Maximum Clock
MHz
f
4.5
w.
x
24
30
60
Frequency
6.0
35
80
28
Input Capacitance
C 1:-;
5
10
10
pF
Power Dissipation Capacitance CI'D(l)
35
Note (1) C R) IS defmed as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IcctpO=CR) • Va:.. fLN +Ia:. 12(per F/F)
HC-191
TC74HC73AP/AF-----------------
SYSTEM DIAGRAM
CK
--t>o-r-t>o--{>
L-£>o-;
.;>o---Q
.;>0--- Q
K
J
HC-192
-----TC74HC74AP/AF/AFN
DUAL D-TVPE FLIP FLOP PRESET AND CLEAR
r---------------------------,
The TC74HC74A is a high speed CMOS D FLIP FLOP
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The signal level applied to the D INPUT is transferred
to Q OUTPUT during the positive going transition of the
CLOCK pulse.
CLEAR and PRESET are independent of the CLOCK
and are accomplished by setting the appropriate input
low.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .................................
f~HX=77MHz(typ.)at
Vcc=5V
• Low Power Dissipation ............... I cc =2t.tA(Max.)at Ta=25"C
• High Noise Immunity··············· V!,\IH =V!,\IL =28% Vcc(Min.)
• Output Drive Capability············ 10 LSTTL Loads
• Symmetrical Output Impedance ... 11 00 HOI.. =4mA(Min.)
• Balanced Propagation Delays ... tpLH"'tpHL
• Wide Operating Voltage Range ... Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LS74
1
P(DIP14-P-300)
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
1 CLR 1
14 Vee
1D 2
13
2CLR
1 CK 3
12
2D
1 PR ."
11
2CK
105
10
2PR
(0
6
9
20
GND 7
8
20
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
INPUTS
CLR
PR
L
H
H
L
OUTPUTS
FUNCTION
CK
a
a
X
L
H
CLEAR
X
H
L
PRESET
X
L
L
D
X
X
X
H
H
-
H
H
L
S
L
H
-
H
H
H
S
H
L
H
H
X
L
an
an
x : Don't care
-
NO CHANGE
HC-193
lPR
lCK
10
lClR
2PR
2CK
20
2ClR
lQ
10
2Q
20
TC74HC74AP/AF/AFN _________________iIiooioiiioo
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range.
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC VeelGround Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
UNIT
V
V
\'
mA
mA
mA
mA
mW
"C
"C
VALUE
-0.5-7
-0.5 -Vcc+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) ./180(MFP}
-65 -150
300
SYMBOL
Vee
VI:\
VOLT
III';
10K
lovl'
Icc
~)
Tslg
TI.
*500m W in the range of Ta=
""40t;- S5t;. From Ta=65t;
to 85t; a derating factor of
-10m WIt; shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vce =2.0V)
0- 500(Vcc =4.5V )
0- 400(Vce =6.0V)
SYMBOL
Vee
VI:\
VOLT i
Topr
tr , tc
I
i
UNIT
V
V
\'
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIII
Lo\\'-Level
Input \'oltage
VII.
High-Level
Output Vol1lage
V(XI
Lo\\'-Level
Output Voltage
V(x.
Input Leakage Current
Quiescent Supply Current
Ta--40 -85"(;
Ta-25"C
UNIT
TYP. I MAX. MIN. MAX.
1.5
! 2.0
i
- I V
3.15
4.5
4.2
6.0
0.5
0.5
I 2.0
- II - 1 1. 35
V
4.5
1. 35
I 6.0
1.8
1.8
2.0
2.0 I -1.9
1.9
1m =-20tl A 4.5
4.4
4.4
4.5
VI:\=
I
V
6.0
5.9
6.0 I 5.9
Vlllor\'II. I()I 4 mA 4.5
4.18
4.31 i
4.13
lai =-5.2mA 6.0
5.68
5.80
5.63
- I 0.0
0.1
0.1
2.0
- I 0.0
0.1
0.1
I . =20 tl A 4.5
VI:\=
V
0.1
6.0
0.0
0.1
VII IorVIl• 1 , -4 mA
4.5
0.26
0.33
O. 17
01
I(~. =5.2mA
0.33
0.18
0.26
6.0
6.0
±O.l
±1.0
VI:\ -Vee or GND
A
VI\ -Vee or GND
2.0
20.0 tl
6.0
TEST CONDITION
I Vee
I
MIN.
1.5
3. 15
4.2
i
I
I
1[:\
Icc
Ila
HC-194
i
---------------TC74HC74AP/AF/AFN
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
ISYMBOL
TEST CONDITION
Minimum Pulse Width! tIn!.!
(CLOCK)
! tWCII)
Minimum Pulse Width
(CLR, PRj
I tl\"(\.·'
I
Minimum Set-up Timel
Minimum Hold Time
Minimum Removal Time
(CLR. PRj
Clock Frequency
ts
I
i
1
t
I
I
I
I
th
I
1
I
t rem
I
f
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta~-40
Ta-25"C
LIMIT
75
IS
13
75
15
13
75
15
13
0
0
0
25
5
TYP~
Vee
-
-
I
-.
-
-
I
-
iI
-
-
,
I
95
19
16
95
19
16
95
19
16
0
0
0
30
I
-
i
LI~IIT
i
85'CJUNIT
"
I
I!
I
I
I
I
6
1
4
5
6
31
36
5
i,
25
29
.I
i
ns
i
IMHz
AC ELECTRICAL CHARACTER1STICS(C L =15pF. Vcc=5V .Ta=25"C)
PARAMETER
Output Transition Time
,I'SYMBOL
TEST CONDITION
I t'tT1.I1
nlL
!
i
i
Propagation D,!lay Time I tpLiI
(CLOCK-Q. Q)
; t ~IL
Propagation Delay Time i tl'LlI
(CLR. PR-Q. Q)
tPlII
}Iaximum Clock Frequency I f\~I,\:
MIN.
TYP.
i
12
!
IUNIT
i
6
I
-
13
i
26
I ns
-
14
I
26
!
1
i
:\IAX.
-
,
i
i
36
77
I
I
i
IMHz
-
AC ELECTRICAL CHARACTERISTICS(C L =60pF.lnput t r =tf=6ns)
I
PARAMETER
iSYMBOL
TEST CONDITION
1
Output Transition Time
II
I
Propagation Delay Time
(CLOCK -Q. Q)
i
!
2.0
t·n.ll
t·l1l1.
~.5
6.0
2.0
4.5
6.0
2.0
tpLlI
tpili.
I
Propagation Delay Time
(CLR. PR-Q. Q)
1
I
tpul
tplli.
I
Maximum Clock
Frequency
I
4.5
I
I
I
C\m.:
Vee
MIN.
-
-
-
6.0
2.0
-
4.5
31
36
6.0
6
Ta-25'C
TYP. MAX.
30
75
8
15
i
13
48
150
16
30
13
26
51
150
17
30
26
15
21
63
67
5
10
Input Capacitance
! CIX
l'oll'erUissipallon Capacitance i (,;1'1>(1)
~4
~ote II' C m IS defined as the value oC the internal equin,lent capacitance which
operating current consumption without load.
A\'erage operating current can be obtained by the equation:
[CC'I'" =C ln • Vee' Cl\ +I<.C 12(per F/F)
HC-195
Ta--.tQ -85°C
IvlIN.
-
-
-
-
5
25
29
-
:\1AX.
UNIT
95
19
16
190
38
32
190
38
32
ns
-
MHz
10
pF
-
is calculated from
the
TC74HC74AP/AF/AFN------------------------------
SYSTEM DIAGRAM
(l/2package)
CLR
PR
--.,...---+-------,
o
Q
o
He-1g6
- - - - - - - TC74HCT74AP/AF
DUAL D-TYPE FLIP FLOP WITH PRESET AND Cr-L::..:E::.....A.:...R~_ _ _ _ _ _-,
The TC74HCT74A is a high speed CMOS D FLIP FLOP
fabricated with silicon gate C'MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The signal level applied to the D INPUT is transferred
to Q OUTPUT during the positive going transition of the
CLOCK pulse.
CLEAR and PRESET are independent of the CLOCK
and are accomplished by setting the appropriate input low.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. fMAX=51MHz(Typ.)at Vcc=5V
• Low Power Dissipation ............ Icc =2.uA(Max.)at Ta=25"C
• Compatible with TTL outputs ...... VIH=2V(Min.)
VIL=0.8V(Max.)
• Wide Interfacing ability ........ • LSTTL,NMOS,CMOS
• Output Drive Capability ...... · .... · 10 LSTTL Loads
• Symmetrical Output Impedance .. ·1 IOH 1=Ia.=4mA(Min.)
• Balanced Propagation Delays ...... tpLH" tpHL
• Pin and Function Compatible with 74LS74
1
P(DIPI4-P-300)
14~
1
F(SOPI4-P-300)
PIN ASSIGNMENT
14 Vee
1 CLR
1D 2
13
2CLR
1 CK 3
12
2D
lPR 4
11
2CK
1Q 5
10
2PR
106
9
2Q
GND 7
8
20
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
INPUTS
OUTPUTS
CLR
PR
D
CK
a
a
FUNCTION
L
H
X
X
L
H
CLEAR
H
L
X
H
L
PRESET
X
H
H
L
H
H
L
an
an
L
L
X
X
H
H
L
.H
H
H
S
S
H
X
t.
H
x : Don't care
-
-
NO CHANGE
HC-197
lPR
10K
10
lClR
2PR
2CK
20
2ClR
lQ
10
2Q
20
TC74HCT74AP/AF - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Supply Voltage Range
Vee
DC Input Voltage
VI:':
DC Output Voltage
Voor
Input Diode Current
11K
Output Diode Current
lex<
DC Output Current
lOUT
DC Vee/Ground Current
lee
Power Dissipation
Po
Storage Temperature
Tstg
Lead Temperature 10sec
TL
UNIT
V
V
V
mA
mA
mA
mA
-roW
"C
"C
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(SOIC)
-65 -150
300
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VALUE
Supply Voltage
Vee
4.5-5.5
Input Voltage
O-Vee
VI:':
Output Voltage
O-Vee
Voor
Operating Temperature
Topr
-40 - 85
Input Rise and Fall Time tr • tr
0-500
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300mW.
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High Level
Output Voltage
Low.,-Level
Output Voltage
Input Leakage Current
Quiescent Supply Current
Voo
VOl..
II"
lee
Alec
TEST CONDITION
Ta=25"C
Vee
4.5
l
5.5
4.5
l
5.5
100 --20 J,tA 4.5
VI:,\V1HorV1L 100 =-4 mA 4 5
Vn,,=
101.. -20 J,tA 4.5
VIHorVIL 101.. -4 mA 4 5
VIX-Vcc orGND
5.5
Vlx-Vee or GND
5.5
PER INPUT: V1;-; =0. 5V or2. 4V
5.5
OTHER INPVT:Vccor GND
HC-198
Ta--40 -85"(
UNIT
MIN. MAX.
MIN.
TYP.
MAX.
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
4 4
4 18
4.5
4.31
0.0
0.17
-
4.4
4 13
-
V
-
-
-
0.1
0.26
+0.1
2.0
2.0
-
-
0.1
0.33
±1.0
20.0
2.9
V
J,tA
mA
- - - - - - - - - - - - - - - - - - TC74HCT74AP/AF
TIMING REQUIREMENTS(lnput tr=tf=8ns)
PARAMETER
SYMBOL TEST CONDITION
Vcc;
Ta -40 -85OC
UNIT
L1MIT
T_a-25OC
TYP.
LIMIT
Minimum Pulse Width
(CLOCK)
tW(L)
tW(H)
4.5
5.5
-
15
14
19
16
Minimum Pulse Width
(CLR,PR)
tW(L)
4.5
5.5
-
15
14
19
17
Minimum Set-up Time
ts
4.5
5.5
15
14
19
17
Minimum Hold Time
%
4.5
5.5
trem
Minimum Removal Time
(CLR,PR)
Clock Frequency
f
-
ns
0
0
0
0
4.5
5.5
-
5
5
6
5
4.5
5.5
-
27
30
22
24
MHz
MAX.
UNIT
AC ELECTRICA L CHARACTERISTICS(C L =15pF, Vcc=5V, Ta=25°C)
PARAMETER
SYMBOL
Output Transition Time
tn.H
tTIiL
tpLH
tcHL
tpLH
toHL
Propagation D.!lay Time
(CLOCK-Q, Q)
Propagation Delay Time
(CLR, PR-Q, Q)
Maximum Clock Frequency
TEST CONDITION
MIN.
f\;lAX
TYP.
-
6
12
-
17
28
-
15
25
53
29
ns
I Mtiz
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =tf=8ns)
Ta-25OC
Ta 40 -85OC
PARAMETER
UNIT
SYMBOL TEST CONDITION
Va; MIN. TYP. MAX. MIN. MAX.
Output Transition Time
tTI.H
tTIiL
4.5
5.5
Propagation D.!1ay Time
(CLOCK-Q, Q)
tpLH
tpHL
4.5
5.5
Propagation Delay Time
(CLR, PR-Q, Q)
tpLH
tpHL
4.5
5.5
Maximum Clock
Frequency
fw.x
4.5
5.5
-
8
7
15
13
-
21
19
33
30
-
18
15
30
27
27
30
48
53
-
-
-
Input Capacitance
CL-;
5
10
Power Dissipation Capacitance Cpo(})
32
Note(l) Cm IS defmed as the value of the internal equivalent capacitance which
operating current consumption without load.
Average operating current can be obtained by the equation:
iCCtp);=C m oVa;ofL'\: +Ia; 12(per F/F)
HC-199
-
41
37
-
38
35
22
24
-
MHz
-
10
pF
-
-
IS
19
16
ns
calculated from the
TC74HCT74AP/AF - - - - - - - - - - - - - - - - - -
SYSTEM DIAGRAM
(l/2package)
Q
CK~:
HC-200
------TC74HC75API AF
4-BIT 0 TYPE LATCH
The TC74HC75A is a high speed CMOS D-TYPE LATCH
fabricated with silicon gate C 2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It contains two groups of 2-bit latches controlled by an
enable input (Gl .2 or G3· 4) and 'each group can be used
in different circuits.
Da~ applied to the data inputs are transferred to the Q
and Q outputs when the enable input is high.When the
enable input is low,the outputs are not affected.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. t)Xl =IOns(typ.)at Va;=5V
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
• Low Power Dissipation ............... Icc =2/l A(Max. )at Ta=25°C
• High Noise Immunity··············· V:\lIf=V:\IL =28% Va;(Min.)
• Output Drive Capability············ 10 LSTTL Loads
• Symmetrical Output Impedance ···1 lao I=IOL =4mA(Min.)
• Balanced Propagation Delays ... tpLli"'tpfl.
• Wide Operating Voltage Range ... Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LS75
10 1
10 2
20 3
G3.4 4
16
15
14
13
12
11
Vee 5
3D 6
40 7
40 8
OUTPUTS
G
a
L
H
L
H
-
H
H
H
L
-
X
L
an
an
LATCH
I
a
FUNCTION
0
X:Don't care
HC-201
30
9 40
IEC LOGIC SYMBOL
INPUTS
GNO
10 30
(TOP VIEW)
TRUTH TABLE
10
20
20
Gl • 2
TC74HC75AP/AF---------------------------------
ABSOLUTE MAXIMUM RATINGS
PARAl\IETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
V[\
VOLT
11K
I(~(
IOlT
Icc
PI)
Tstg
TL
VALUE
-0.5 - i
-0.5 -V0: +0.5
-0.5 -Vce+0.5
±20
±20
±25
±50
500(DIP) */ 180(MFP)
-65 -150
300
!
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
I
i
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vce=2.0V)
0- 500(Vee =4.5V)
0- 400(Vee =6.0V)
SYMBOL
Vee
VI:\
VOLT
Tapr
-i"
tr , tr
II
I
UNIT
V
-V
V
"C
ns
I
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIII
Low-Le\'el
Input Voltage
VII.
High-Level
Output Voltage
V(ll
Low-Level
Output Voltage
V(l.
Input Leakage Current
Quiescenl Supply Current
11:\
Icc
TEST CONDITION
II(ll =-20,uA
VI:\=
VlllorVIl .
Ilal ---\ rnA
1m =-5. 2mA
VI:\=
"II Ior VII.
la. =20 ,uA
lo!. -4 rnA
I(l. =5.2mA
VI:\ -Vee or GND
\'1:\ =Vcc or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
ti. 0
6.0
HC-202
Ta--40 -85°C
Ta-25"C
UNIT
TYP. :\IAX. MIN. l\lAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
.!,4
4.4
4.5
V
5.9
5.9
6.0
4.18
4.31
4.13
5.68
5.80
5.63
0.0
0.1
O. I
O. I
0.0
0.1
V
0.0
0.1
O. I
O. Ii
0.26
I 0.33
0.18
0.26
! 0.33
I
-0.1
=1.0 ,uA
2.0
I 20.0
MIN.
1.5
3.15
4.2
I
I
--------------------------------TC74HC75AP/AF
TIMING REQUIREMENTS(lnput tr=tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(G)
t\\'(II)
Minimum Set-up Time
ts
Minimum Hold Time
th
Vee
2.0
4.5
6.0
2.0
4.5
6.0 I
2.0 I
4.5
6.0
I
i
I
i
I
Ta--40 -85"C
UNIT
LIMIT
95
19
16
65
ns
13
II
30
6
5
Ta-25"C
LIMIT
TYP.
75
15
13
50
i
10
!I
9
25
5
5
AC ELECTRICAL CHARACTERISTlCS(C L =15pF, Vcc=5V, Ta=25°C)
PARAl\IETER
SYMBOL
Output Transition Time
tTl.! I
l\HN.
TEST CONDITION
-
tT11I.
Propagation Delay Time
(DATA-Q. Q)
Propagation Delay Time
(G-Q.Q)
tpl.Il
t ~IL
tpLiI
t ~ II.
TYP.
I
I
MAX.
4
8
I
-
10
18
I
-
10
21
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =tf=6ns)
Ta-25"C
Ta--40 -85"C
PARAl\IETER
SYMBOL TEST COXDITION
UNIT
Vee MIX. TYP. Il\1AX. MIN. MAX.
2.0
25 I i5
95
trLlI
Output Transition Time
4.5
7
15
19
tTIIi.
6.0
6
13 I
16
f-.
ns
2.0
36
110
140
I
Propagation D~ay Time
tpl.Il
4.5
22
12
28
( DATA-Q.Q)
tplli.
6.0
10
19
24
40
125
155
2.0
Propagatign Delay Time
tpl.ll
4.5
13
25
31
( G-Q.Q)
tpllL
6.0
21
26
11
Input Capacitance
CI:\
10
10
5
pF
Power Dissipation Capacitance . ' CI~)(l)
30
~ote iii C m i~ defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
A"erage operating current can be obtained by the equation:
IcCllm =CPIl • V(c· fl,\ +Iu:: /4(per Latch)
I
I
i
HC-203
I
TC74HC75AP/AF-'- - - - - - - - - - - - - - - - - - - -
SYSTEM DIAGRAM
G1.2~O
G3.4~O
I-I.
1D~
10
1Q
3D~
HL
UNIT
ns
AC ELECTRICAL CHARACTERISTlCS(C L =50pF,lnput t r =tf=6ns)
PARAMETER
Output Transition Time
Propagation Delay Time
(DATA-Q)
SYMBOL I TEST CONDITION
tTW
tTllL
tpLH
tpl IL
r---'
Propagation Delay Time
(G-Q)
tpUI
tpill.
I
Vce
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.n
MIN.
-
-
-
Ta--40 -85OC
Ta-25OC
UNIT
TYP. MAX. MIN. MAX.
30
75
95
8
15
19
I
13
16
7
I
39
125
100
ns
25
13
20
17
21
II
39
125
100
13
25
20
I
I
11
17
-
21
Input Capacitance
CI:'\
10
10
I 5
pF
Power Dissipation Capacitance
CpD(J)
20
Note (II C I'D is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC (p,,=C 1'1) • Vee' f 1:,\ + I Q' 14(per Gate)
-
HC-211
TC74HC77AP/AF--------------------------_______
SYSTEM DIAGRAM
G1.2~+a
G3.4~+.b
_
L---+a
10 1
~~----4r~~~~o---10 3D 5
Vcc:4 . GND:11
HC-212
. L-ct>-- +b
9
30
8
40
-----TC74HC85AP/AF/AFN
4-BIT MAGNITUDE COMPARATOR
The TC74HC85A is a high speed CMOS 4 BIT
MAGNITUDE COMPARATOR fabricated with silicon
gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HC85A compares two 4-bit words applied to
inputs AO-A3 and BO-B3,and provides a high voltage
level on one of three outputs:A> B, A B IN 4
13 A2
A>B OUT 5
12 Al
A=B OUT 6
11 Bl
AB
BO
Bl
82
B3
}
<
>
COMP
PQ
]0
HC-213
FN(SOL 16-P-150)
(7)
(6)
(5)
AB
VIEW)
TC74HC85AP/AF/AFN - - - - - - - - - - - - - - -
TRUTH TABLE
CASCADING
INPUTS
COMPARING INPUTS
A3>B3
A3=B3
A3=B3
A3=B3
X
X
X
A2>B2
A2=B2
A2=B2
A3=B3
A2=B2
A3=B3
A3=B3
A3=B3
A3Bl
Al=Bl
.
X
X
X
AO>BO
A>B
AB
A--_1::l;;1R
B2
A2 I,!
:D
i
G)
~ I!1~1::~~;;=..~~~:=jt:ljj
~
Al
Bl
BO
n
~
r=t>F=fF:[»-lr-_-4b~~5
"-[>o-II9C>c~
~~[>____-J
A0 10
~IA4,__________________-==::t:>
~ A=B 3~________________
Z A>B
A>B] 0c
r------H~~~o.~~6 A=B ~
."
c
-4
en
HC-214
=
c
A -Vex; or GND
V 1:,\ -Vex; or GND
6.0
HC-215
Ta-25"C
Ta--40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4. 13
4.18
5.68
5.63
5.80
.0.0
0.1
0.1
0.1
0.0
0.1
V
0.1
0.1
0.0
0.33
0.26
0.17
O. 18
il.26
0.33
±0.1
±1.0 ,uA
4.0
40.0
MIN.
1.5
3. 15
4.2
TC74HC85AP/AF/AFN - - - - - - - - - - - - - -
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc =5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tn.1-l
tnll.
tpLl-l
toHL
tpLl-l
tpl-lL
Propagation Delay Time
(A, B-OUT)
Propagation Delay Time
(CASCADE-OUT)
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
22
34
-
10
18
UNIT.
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =t,=6ns)
Ta-25"C
Ta- 40 -85"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Va: MIN. TYP. MAX. MIN. MAX.
2.0
75
95
30
tTUi
Output Transition Time
4.5
8
15
19
tTI-IL
6.0
16
7
13
2.0
245
90
195
Propagation Delay Time
tpLH
4.5
ns
26
39
49
(A, B-OUT)
tpl-lL
6.0
22
42
33
2.0
40
110
140
Propagation Delay Time
tpLl-l
4.5
22
28
13
(CASCADE-OUT)
tpLl-l
6.0
24
II
19
Input Capacitance
CIN
5
10
10
pF
Power Dissipation Capacitance
Cpo (I)
25
Note(1) Cru is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia:~=CPD • Vcr;. fiN +Icr;
HC-216
--------------TC74HC85AP/AF/AFN
TYPICAL APPLICATION
N-BIT CASCADING CONNECTION
(A) DATA
(LaB)
AOA1 A2A3
(MSB)
-------- An
A4A5 A8A7
A>BIN
A=BIN
ABQUT
A=BOUT
A (B)
CASCADING INPUT
A>B
A=B
AB
H
H
L
L
L
OUTPUT·
A=B
A--Q
~-Q
K
J
HC-225
TC74HC109AP/AF/AFN---DUAL
J-K FLiP-FLO'P WITH PRESET AND CLEAR
.-----------------------~
The TC74HC109A is a high speed CMOS J-K FLIP FLOP
fabricated with silicon gate c2Mos technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
In accordance with the logic level applied to the J and K
inputs,the outputs change state on the positive going
transition of the clock pulse.
CLEAR !lnd PRESET are independent of the clock and
are accomplished by a low logic level on the corresponding
input.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP16-P-300A)
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
FEATURES:
• High Speed .............................. nIAlF63MHz(Typ.)at Vc'C=5V
• Low Power Dissipation ............ Icc=4,uA(Max.)at Ta=25°C
• High Noise Immunity .............. · V;I;IH=V:-';IL28% Vcc(Min.)
• Output Drive Capability'" ......... 10 LSTTL Loads
• Symmetrical Output Impedance .. ·1 IOH I=IOL=4mA(Min.)
• Balanced Propagation Delays ...... tpLH"< tpHL
• Wide Operating Voltage Range'" Vcc(opr)=2V-6V
• Pin and Function Compatible with 74LSI09.
lClR
1
1J
2
16 Vee
15 2ClR
lK
14 2J
lCK
4
13 2K
lPR
5
12 2CK
10
6
11 2PR
10
7
10 20
GND
8
9
iil
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
INPUTS
CLR PR J' K
L
H
X
X
H
L
X
X
L
L
X
X
H
H
L
H
H
H
L
L
H
H
H
H
H
H
H
L
H
H· X
OUTPUTS
CK
a
a
X
X
X
L
H
H
H
L
H
.r an an
.r L L
.r H L
.r an an
x 1. an an
FUNCTION
CLEAR
PRESET
10
NO CHANGE
20
TOGGLE
NO CHANGE
X:Don't care
HC-226
2Q
--------------TC74HC109AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
--=:
DC Output Voltage
--:;---------Input Diode Current
Output Diode Current
-= DC Output Current
DC Vee/Ground Current
VALUE
-0.5 -7
-0.5 -Vcc+0.5
-0.5 :"Vcc+O.5
±20
±20
±25
±50
500(DIP)_~/180e MFP)
-65 -150
300
iSYMBOL i
Vee
VI\
---'-
---~
Power Dissipation
Storage Temperature
Lead Temperature lOsec
f--
BOLT
I!1L
10K
II
IOLT
I Ice
=t;Pn
Tstg
I
TT~i-
UNIT
V
V
V
mA
mA
mA
mA
mW
°C
"C
*500mW in the range of Ta=
-40'C- 65·C. From Ta=65'C
to 85'C a derating factor of
-10m W
shall be applied
until300mW.
'"
rc
RECOMMENDED OPERATING CONDITIONS
'--PARAMETER
Supply Voltage
f-=---------Input Voltage
r.:--'-Output Voltage
Operating Temperature
I Vee
_+;VI~_f-_
V-
Vee
0- Vee
-40 - 85
o - 1000eVee=2.0V)
0- 500(Vee =4.5V)
0- 400eVee=6.0V)
r •
Ri," =d Fall Tim,
UNIT
V
a-
I VOLT
I Topr
,
I
I t tr I
I
I
f----
1'0'"'
VALUE
2-6
jSYMBOL
V
°C
--~
--
ns
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
High-Level
Input Voltage
TEST CONDITION
~.O
II
Viii
f-----------+---~---L
L I
ow- eve
Input Voltage
r---
---
V
It
I
---r-----
Ollf
-------l
,I
High- Level
r
Output Voltage
;
Low- Level
Output Voltage
I
I
~ _ _ _ _ _ _ _~
InputLeakageCurrent I
--Quiescent Suppiy Current
V
01.
I
I
I"
Icc
Vee
I
i
4.5
MIN.
1.5
3.15
Ta-25°C
Ta- 40 -85"C UNIT
TYP. I MAX. MIN. MAX.
-
-
1.5
3.15
V
6~.0~~4~.2~~-----~~-~+-~4.~2~~~-~-r--_;
20
O. 5
O. 5
4' 5
1 35
1 35
V
. I .
.
6. 0 +-.=n-+--;:;---,:-+-=-I:..:.8'--!--:;---,;--+-::;1...::8~__- t
----1-;2::-'--.0;,- 1. 9 I 2.0
1. 9
VI\ =
I(~I =-20 tL A
V
V ~I
'IHor IL 1011 --4 mA
1011 =-5. 2mA
4.5
4.4
4.5
4.4
V
6.0
5.9
6.0
5.9
4.5
4.18
'4.31
4.13
6.0
5.68
5.80
5.63
!
2-'-.cO:-+---=-:---"--'----+--::-O.:.-;O~~O:-.-=-1-+--'-'--'--'---+-"""'0"".1--11----1
1 101. =20 tL A
4.5
0 0
O. I
0.1
\r _
1\ 6. 0
O' 0 I 0 1
0 I
V
VIHorVU h-------.+~_+---_+-:i'.'-7;;_+'-:i"~:_+----+~~';';'
. I lex. =4 mA I 4.5, 0.17
O. 26
~
0.33
-~JQi. =5. 2mA _,-::-6'-.:.0:-+1__-__--'--=-0.:...:1:.=.8-+--=0~-_-----+--70'-7.3:-=;3:+-__'--1
V" =Vcc orGND
16.0 I i - I ±O.II
±1.0
_~,
T-=-~+----+-=~ tL A
V I\ ~Vec orGND
6.0
2.0
20.0
HC-227
TC74HC109AP/AF/AFN -------------~
TIMING REQUIREMENTS(lnput t r =tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
tW(1.)
t\r(H)
Minimum Pulse Width
--(PR,CLR)
t\l"(1.)
Minimum Set-up Time
ts
Minimum Hold Time
tt,
Minimum Removal Time
(PR,CLR)
Clock Frequency
trem
f
Va:.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
95
ns
19
16
0
0
0
65
13
11
5
MHz
25
29
Ta-25"C
TYP.
i LIMIT
i
75
i
15
! 13
75
i
15
i
13
75
!
15
,i
13
!
0
I
0
I
l
-
!
-
:
-
,
-
I
!
-
i
-
o.
50
10
9
6
31
36
AC ELECTRICAL CHARACTERISTICS(C L =15pF, Vcc=5V, Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
Propagation DelaLTime
(CLOCK-Q,Q)
Prop!G:~tion Delay_Time
(PR,CLR-Q,Q)
Maximum Clock Frequency
MIN.
TYP.
MAX.
tTLII
tlliL
tpl.l1
tpHL
tpUi
tpHL
-
6
12
-
13
26
-
13
26
f~IAX
33
63
-
TEST CONDITION
UNIT
ns
MHz
AC ELECTRICAL CHARACTERISTICS(CL =50pF.lnput t r =tf=6ns)
Ta-25"C
Ta- 40 -85"C IUNIT
PARAMETER
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
2.0
30
75
95
tTLlI
Output Transition Time
4.5
8
15
t,.1-I1.
19
6.0
7
13
16
2.0
50
150
190
Propagation Delay Time
tpl..!1
ns
4.5
16
30
38
(CLOCK -Q, Q)
tplil.
6.0
26
32
13
- I 50
2.0
150
190
Prop~tion Delay!ime
tpl.H
I
4.5
16
30
38
(PR,CLR-Q, Q)
tl~ II.
6.0
13
26
32
2.0
6
5
Ii
Maximum Clock
- IMHZ
f:vt,\x
31
25
59
4.5
Frequency
- I
6.0
36 11 67
29
Input Capacitance
Ct'';
5
10 I
10 i pF
!
Power Dissipation Capacitance Cpo(i)
! 41
!
I
.'
Note (]) em IS defmed as the value of the mternal equivalent capacitance which
IS calculated from
the
operating current consumption without load.
'Average operating current can be obtained by the equation:
1eew~=Cfn • VCC' fl\: +ICC 12(per F/F)
!
~
I
i
HC-228
I
- - - - - - - - - - - - - - TC74HC109AP/AFI AFN
SYSTEM DIAGRAM (1/2 package)
CLOC~
¢
¢
Q
K
Q
J
HC-229
TC74HC112AP/AF/AFN-----DUAL J-K FLIP-FLOP WITH PRESET AND CLE,;-A;.;..R_ _ _ _ _-=:--_--,
The TC74HC112A is a high speed CMOS DUAL J-K
FLIP FLOP fabricated with silicon gate C2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
In accordance with the logic level applied to the J and K
inputs, the outputs change state on the negative going
transit.ion of the clock pulse.
CLEAR and PRESET are independent of the clock and
are actived by a low logic level on the corresponding input.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
'8~
1
P( DI P16-P-300A)
'8~'8~
F(SOP16-P-300)
FL(SOL 16-P-160)
PIN ASSIGNMENT
FEATURES:
• High Speed .............................. fMAx=63MHz(Typ.)at Vcc=5V
• Low Power Dissipation ............ Icc =2 Il A(Max.)at Ta=25"C
• High Noise Immunity ........ · .... ·· VNIH =VNIL 2896 Vcc(Min.)
• Output Drive Capability .. ·· ........ 10 LSTTL Loads
• Symmetrical Output Impedance .. ·1 101-1 I=IQL=4mA(Min.)
• Balanced Propagation Delays ...... tpLH" tpHL
• Wide Operating Voltage Range'" Vcc(opr)=2V-6V
• Pin and Function Compatible with 74LS112.
lCK
18 Vee
1K
2
15 lCLR
1J
3
14 2'C'L'R
1PR
4
13 2CK
1Q
6
12 2K
1Q
8
11 2J
20
7
10
2PR
8
2Q
GND 8
(TOP VIEW)
TRUTH TABLE
INPUTS
K
J
CLR PR
L
H
X
X
H
L
X
X
L
L
X
X
H
H
L
L
H
H
L
H
H
H
H
L
H
H
H H
H
H
X
X
IEC LOGIC SYMBOL
OUTPUTS
CK
a
a
X
X
X
L
H
H
H
L
H
1. an an
1. L H
1. H L
1- an an
.r an an
FUNCTION
CLEAR
PRESET
NO CHANGE
TOGGLE
NO CHANGE
X:Don't care
HC-230
- - - - - - - - - - - - - - - - TC74HC112AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
VOlJT
11K
10K
IOlJT
lee
Po
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)*/180(SOIC)
-65 -150
300
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
·C
*500m W in the range of Ta=
-40"C- 65·C. From Ta=65"C
to 85'C a derating factor of
-lQmWrC shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Input Rise and Fall Time
tr • tr
Vee
VIN
VOL'T
Topr
UNIT
V
V
V
VALUE
2-6
0- Vee
o-Vee
-40 - 85
o - lOOO(Vee =2.0V)
0- 500(Vcc =4.5V)
0- 400(Vee =6.0V)
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
liN
lee
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
IOH =-20tL A 4.5
VIN=
6.0
VIHorVIL
IOH - 4 mA 4.5
IOH =-5.2mA 6.0
2.0
IOL =20 tL A 4.5
VIN=
6.0
VIHorVIL
IOL -4 mA 4.5
IOL =5.2mA 6.0
V IN -Vee or liND
6.0
YIN -'Yee or GND
6.0
HC-231
Ta-- 40 -85·C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.4
4.5
V
5.9
6.0
5.9
4.18
4.31
4.13
5.63
5.80
5.68
0.0
0.1
0.1
0.1
0.0
0.1
V
0.1
0.1
0.0
0.26
0.33
0.17
0.26
0.18
0.33
+1.0
+0.1
p.A
2.0
20.0
MIN.
1.5
3.15
4.2
-
-
-
TC74HC112AP/AF/AFN - - - - - - - - - - - - - - - TIMING REQUIREMENTS(lnput tr =t,=6ns)
PARAMETER
Minimum Pulse Width
(CLOCK)
SYMBOL TEST CONDITION
tW(L)
tw(H)
Minimum Pulse Width
(CLR,PR)
tW(L)
Minimum Set-up Time
t5
Minimum Hold Time
%
Vcr;
2.0
4.5
, 6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Minimum Removal Time
(CLR,PR)
Clock Frequency
2~0
4.5
tram
6.0
2.0
4.5
6.0
f
'l'a=-4o -85"C
UNIT
_LIM!T
95
19
16
95
19
16
95
ns
19
16
0
0
0
60
12
'i'a-25"C
LIMIT
TYP.
75
15
13
75
15
13
75
15
13
0
0
0
50
10
9
8
40
47
-
-
-
11
6
32
38
MHz
MAX.
UNIT
AC ELECTRICAL CHARACTERISTICS(CL =15pF. Vcc=5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTHL
tpLH
toHL
tpLH
toHl
fMAX
Propagation Delay5ime
(CLOCK-Q,Q)
Propagation DelaLTime
(CLR,PR-Q,Q)
Maximum Clock Frequency
TEST CONDITION
MIN.
TYP.
-
4
8
-
13
21
-
14
22
40
63
-
ns
IMHz
AC ELECTRICAL CHARACTERISTICS(CL=50pF .Input t r =t,=6ns)
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
75
95
30
tTLH
Output Transition Time
15
19
4.5
8
tTHL
6.0
16
7
13
2.0
64
125
155
Propagation Delay Time
tPLH
ns
25
31
4.5
16
(CLOCK-Q, Q)
tpHL
6.0
14
21
26
2.0
135
170
68
Propagation Delay Time
tPLH
4.5
17
27
34
(CLR,PR-Q, Q)
tpHL
6.0
14
23
29
2.0
6
8
16
Maximum Clock
f:vlA)(
MHz
4.5
32
40
63
Frequency
6.0
47
79
38
Input Capacitance
(.;t:-;
10
5
10
pF
Power Dissipation Capacitance cpom
33
Note(!) eft) IS defmed as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCq,o=Cft) • Va:. eN +Ia: 12(per F/F)
PARAMETER
SYMBOL TEST CONDITION
Vcr;
2.0
MIN.
-
-
-
-
-
HC-232
-
- - - - - - - - - - - - - - - - - TC74HC112AP/AF/AFN
SISTEM
DIAGRAM
CK
--t>o
(1/2
package)
Lt=t>=:
K
:)1-+-1--4..----1 '>_--<1
J
HC-233
>-- a
NOTES
TC74HC113API AF
DUAL J-K FLIP FLOP WITH PRESET
The TC74HC113A is a high speed CMOS DUAL J-K
FLIP FLOP fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power
dissipation.
In accordance with the logic level applied to the J and K
inputs, the outputs change state on the negative going.
transition of the clock pulse.
PRESET is independent of the clock and is accomplished
by a low logic level on the input.
All inputs are 'equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP14-P-300)
14~
F(SOP14-P-300)
FEATURES:
• High Speed .............................. rMHz=71~mz(Typ.)at VC£=5V
• Low Power Dissipation ............ Ic£=2.u A(Max.)at Ta=25"C
• High Noise Immunity .............. · V:-;Ul =V\IL2896 Vc£ (Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance "'1101 1=IOL =4mA(Min.}
• Balanced Propagation Delays ...... tpLII '" tpllL
• Wide Operating Voltage Range'" Vc£(opr.}=2V-6V
• Pin and Function Compatible with 74LS113
PIN ASSIGNMENT
lCK
14 Vee
lK 2
132CK
lJ 3
122K
lPR ..
11 2J
10 5
10 2PR
lQ 6
9 20
GND 7
8 20
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
INPUTS
OUTPUTS
PR
J
K
CK
a
a
FUNCTION
L
x
X
X
H
L
PRESET
H
L
L
H
L
H
H
H
L
H
H
H
H
X
X
L
L
L
L
S
an an
L
H
H
L
an an
an an
NO CHANGE
TOGGLE
NO CHANGE
X : Don't care
HC-235
lPR
lJ
lCK
lK
2PR
2J
2CK
2K
10
10
20
2'0
TC74HC113AP/AF - - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Gro~nd Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI~
VOLT
11K
10K
lOLl'
lee
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vcc+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
rnW
"C
"C
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI~
VOI.:r
Topr
tr • tr
UNIT
V
V
V
"C
VALUE
2-6
0- Vee
0-- Vee
-40 -- 85
o - 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o - 400(Vee=6.0V)
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
Va.
Input Leakage Current
Quiescent Supply Current
IL'\
lee
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
Ia-l =-20/.l A 4.5
VI:\=
6.0
VIHorV". I -l--4 rnA
4.5
a
1011 =-5. 2mA 6.0
2.0
Ia. =20 /.lA 4.5
VI:\=
6.0
VIHorV". Ia. -4 rnA 4.5
Ia. =5.2mA 6.0
Vl,\ -Vee or GND
6.0
6.0
VI:\ -Vee or GND
HC-236
Ta-25"C
I Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4. 13
4.18
5.68
5.80
5.63
0.0
0.1
0.1
0.0
0.1
0.1
V
I 0.1
0.1
0.0
0.17
0.26
0.33
0.18
0.33
0.26
±0.1
±1.0
uA
2.0
20.'
MIN.
1.5
3.15
4.2
I
I
-
- - - - - - - - - - - - - - - TC74HC113AP/AF
TIMING REQUIREMENTS(lnput t r =tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
two.)
t won
Minimum Pulse Width
(PR)
tW(L)
Minimum Set-up Time
ts
Minimum Hold Time
th
Minimum Removal Time
Clock Frequency
Vcr;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2. O·
4.5
6 0
2.0
4.5
6 0
2.0
4.5
6.0
t rem
f
Ta-25"C
LIMIT
TYP.
75
15
13
75
15
13
75
15
13
0
0
0
5
5
5
8
40
47
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
95
ns
19
16
0
0
0
5
5
5
6
32
MHz
38
-
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc =5V.Ta=25"C)
PARAMETER
Output Transition Time
Propagation DeiaL Time
(CLOCK-Q,Q)
Propagation Delay Time
(PR-Q,Q)
Maximum Clock Frequency
MIN.
TYB.
MAX.
tTLH
tlliL
tpLH
tol-lL
tpLH
tol-lL
-
6
12
-
13
21
-
13
21
f:vtAX
43
71
SYMBOL
TEST CONDITION
UNIT
ns
MHz
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =tf=6ns)
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
30
75
95
tTLH
Output Transition Time
8
15
19
tTHL
7
13
16
46
125
155
Propagation Delay Time
tpLH
ns
25
16
31
(CLOCK -Q,Q)
tpHL
12
21
26
125
48
155
Propagation Delay Time
tpLI-I
25
31
16
(PR-Q,Q)
tpHL
21
26
13
6
8
16
Maximum Clock
- MHz
40
32
f :vtAX
63
Frequency
47
38
79
Input Capacitance
CI:-i
5
10
10
pF
Power Dissipation Capacitance CPDW
32
Note (1) C ro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icc q,o=C PD • Vcr;' f 1:\ + I cr; 12(per F IF)
PARAMETER
SYMBOL TEST CONDITION
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
HC-237
MIN.
-
-
TC74HC113AP/AF--------------------------------
SYSTEM DIAGRAM
(1/2 package)
CLOCK~:
K
:»----/ . : : 0 - - - J
HC-238
Q
TC74HC123API AFI AFN
DUAL RETRIGGERABLE MONOSTABLE MUL TIVIBRATOR
The TC74HC123A is a high speed CMOS MONOSTABLE
MULTIVIBRATOR fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation simlar to equivalent
LSTTL while maintaining the CMOS low power
dissipation.
There are two trigger inputs, A input (Negative edge),
and B input (Positive edge). These inputs are valid for a
slow rise/fall time signal (tr=tf=lsec.) as they are
schmitt trigger inputs. This device may also be triggered
by using CLR input (Positive edge).
After triggering, the output stays in a MONOSTABLE
state for a time period determined by the external resistor
and capacitor (Rx, Cx). A low level at the CLR input
breaks this state. In the MONOSTABLE state, if a new trigger is applied, it extends the MONOSTABLE period (retrigger mode).
Limits for Cx and Rx are:
External capacitor, Cx······No limit
External resistor, Rx······Vcc<3.0V more than 5kQ
Vcc~3.0V more than 1kQ
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. '1:xl=25ns(Typ.)at Vee=5V
• Low Power Dissipation
Standby State ............ Iee=4J.tA(Max.)at Ta=25"C
Active State .................. I ee =700/lA(Max.)at Ta=25"C
• High Noise Immunity··············· V:\IH=V:\IL28% VcdMin.)
• Output Drive Capability············ 10 LSTTL Loads
• Symmetrical Output Impedance ... / IOH / =IoL=4mA(Min.)
• Balanced Propagation Delays ...... tpLH '" tpHL
• Wide Operating Voltage Range ... Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS123
P(DIP16-P-300A)
F(SOP16-P-300)
FN(S0L16-P-150)
PIN ASSIGNMENT
lA
16 Vee
lB 2
lCLR 3
lQ 4
20 5
2Cx6
2Rx/Cx 7
GND 8
151Rx/Cx
14 lCx
13 10
122Q
11 2CLR
10 2B
9 2A
(TOP VIEW)
IEC LOGIC SYMBOL
(13) lQ
(6) 2Q
HC-239
TC74HC123AP/AF/AFN - - - - - - - - - - - - - TRUTH TABLE
INPUT
OUTPUT
NOTE
A
L
B
CLR
Q
Q
JL LJ
H
H
X
L
H
L
H
H
X
H
L
H
S
L
L
H
X
X
INHIBIT
INHIBIT
JL LJ
JL LJ
H
S
L
L
OUTPUT ENABLE
H
...OUTPUT ENABLE
OUTPUT ENABLE
INHIBIT
X:Don't Care
BLOCK DIAGRAM
Ox
Ox
r-t-r-.,
Cx
+:
:
..---1"-1 t-+--'W~......Rx
+
Cx
r~-;
1
I
..---t-1H-'IIv.,-.....- Vee
Vee
A-,--~-....
A
B--","",,--,,
B
5
a
12
a
9
_IO_"","-"D..~
11
erR
erR
Notes: (1) Cx, Rx, Dx are external.
Capacitor, Resistor, and Diode, respectively.
(2) External clamping diode, Dx;
The external capacitor is charged to Vcc level in the wait state, i.e. when no trigger is applied.
1£ the supply voltage is turned off, Cx is discharges mainly through the internal (parasitic)
diode. If Cx is sufficiently. large and Vcc drops rapidly, there will be some possibility of
damaging the IC through in rush current or latch-up. If the capacitance of the supply voltage
filter is large enough and Vcc drops slowly, the in rush current is automatically limited and
damage to the IC is avoided.
The maximum value of forward current through the parasitic diode is ±20mA.
In the case of a large Cx. the limit of fall time of the supply voltage is determined as follows:
tr
~(Vcc-0.7)
Cx/20mA
(tr is the time between the supply voltage turn off
and the supply voltage reaching 0.4 Vcc.)
In the event a system does not satisfy the above condition. an external clamping diode (Dx) is
needed to protect the IC from in rush current.
HC-240
- - - - - - - - - - - - - - TC74HC123AP/AF/AFN
SYSTEM
DIAGRAM
Vee
Rx/Cx
Cx----~
A
ii
~---a
TIMING
CHART
n
_ _ _ _ _ _ _ _.J
B
t rr
t--1
V1H
n
U n---
'-_ _ _ _ _ _ _ _ _ _ _1
I~----VIL
r---------~~------------------+-~-------VIH
---VIL
r--------I-+----- VIH
---VIL
Rx/Cx
a
,VOH
tw
tw
HC-241
'------!,-tw+trr
.
VOL
TC74HC123AP/AF/AFN - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
(J)Stand-by State
The external capacitor (Cx) is fully charged to Vcc in the stand-by state. That means, before
triggering, the Qp and QN transistors which are connected to the Rx/Cx node are in the off
state. Two comparators that relate to the timing of the output pulse, and two reference voltage
supplies turn off. The total supply current is only leakage current.
(2) Trigger operation
Trigger operation is effective in any of the following three cases. First, the condition where the
low, and the Binput has a rising signal; second, where the B input is high, and the
Ainput has a falling signal; and third, where the A input is low and the B input is high, and the
CLR input has a rising signal.
After a trigger becomes effective, comparators Cl and C2 start operating, and QN is turned
.on. The external capacitor discharges through QN. The voltage level at the Rx/Cx node drops. If
the Rx/Cx voltage level falls to the internal reference voltage Vref L, the output of Cl becomes
low. The flip-flop is then reset and QN turns off. At that moment Cl stops but C2 continues
operating.
After QN turns off, the voltage at the Rx/Cx node starts rising at a rate determined by the
time constant of external capacitor Cx and resistor Rx.
Upon triggering, output Q becomes high, following some delay time of the internal F/F and
gates. It stays high 'even if the voltage of Rx/Cx changes from falling to rising. When Rx/Cx
reaches the internal reference voltage Vref H, the output of C2 becomes low, the output Q goes
low and C2 stops its operation. That means, after triggering, when the voltage level of the Rx/Cx
node reaches Vref H, the IC returns to its MONOSTABLE state.
With large values of Cx and Rx, and ignoring the discharge time of the capacitor and internal
delays of the IC, the width of the output pulse, tw (OUT), is as follows:
tw (OUT)=l.O Cx Rx
A input is
(3) Retrigger operation
When a new trigger is applied to either input A or B while in the MONOST ABLE state, it is
effective only if the IC is charging Cx. The voltage level of the Rx/Cx node then falls to Vref L
level again. Therefore the Q output stays high if the next trigger comes in before the time period
set by Cx and Rx.
If the new trigger is very close to previous trigger, such as an occurrence during the discharge
cycle, it will have no effect.
The minimum time for a trigger to be effective 2nd trigger, trr(Min.), depends on Vcc and Cx.
'(4) Reset operation
In normal operation, the CLR input is held high. If CLR is low, a trigger has no effect because
the Q output is held low and the trigger control F/F is reset. Also, Qp turns on and Cx is
charged rapidly to Vcc.
This means if CLR is set low, the IC goes into a wait state.
HC-242
- - - - - - - - - - - - - - TC74HC123AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Supply Voltage Range
Vee
DC Input Voltage
VIN
DC Output Voltage
VOLT
Input Diode Current
11K
Output Diode Current
10K
DC Output Current
Iocr
DC Vee/Ground Current
lee
Power Dissipation
PD
Storage Temperature
Tstg
Lead Temperature 10sec
TL
VALUE
-0.5 -7
-0.5 -Vcc+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) *1l80(SOIC)
-65 -150
300
UNIT
V·
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
(CLR Only)
External Capacitor
External Resistor
SYMBOL
Vee
VI:,\
VOLT
Topr
tr , tr
Cx
Rx
VALUE
2-6
o -Vee
o -Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o-400(Vee =6.0V)
No Limitation *
~
~
5K (Vec<3. OV) *
lK (Vee~3. OV) *
UNIT
V
V
V
"C
ns
F
Q
• The maximum allowable values of Cx and Rx are a function of leakage
of capacitor Cx, the leakage of TC74HCl23A, and leakage due to board
layout and surface resistance.
Susceptibility to externally induced noise signals may occur for Rx>lM
Q.
HC-243
*500mW in the range of Ta=
-40"C- 65·C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until300mW.
TC74HC123AP/AF/AFN - - - - - - - - - - - - - -
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
(Q,Q)
Vai
Low-Level
Output Voltage
(Q,Q)
Va.
Input Lea~age Current
Rx/Cx Terminal
Off-State Current
I Quiescent Supply Current
Active-State 0
Supply Current
II:"
TEST CONDITION
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
1m =-20fJ. A 4.5
VI:" =
6.0
VlllorVll .
Iai --4 rnA 4.5
IaJ =-5. 2mA 6.0
2.0
la. =20 fJ.A 4.5
VI:" =
6.0
VlllorVIL
la. -4 rnA 4.5
Ia. =5.2mA 6.0
VI:" =Vcc orGND
6.0
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
-4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
1.9
2.0
4.5
4.4
4.4
V
5.9
6.0
5.9
4.13
4.18
4.31
5.63
5.68
5.80
0.0
0.1
0.1
0.0
0.1
0.1
V
0.1
0.1
0.0
0.33
0.17
0.26
0.18
0.26
0.33
±0.1
±1.0
MIN.
1.5
3.15
4.2
-
-
±O.l
45
400
0.7
4.0
200
500
1 0
II;\;
VI:" =Vcc or GND
6.0
Icc
VI:" -'Vcc or GND
6.0
2.0
4.5
6 0
-
Vcr.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C .
LIMIT
TYP.
75
15
13
75
15
13
325
108
78
5.0
1.4
1.2
VI:" =Vcc or GND
Rx/Cx=O. 5Vcc
Icc
-
-
±1.0
fJ.A
-
40.0
260
650
1.3
fJ.A
fJ.A
rnA
0: per circuit
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
tW(L)
tW(H)
:Minimum Clear Pulse Width
tW(L)
Rx=lKQ
Cx=lOOpF
Minimum Retrigger TimE trr
Rx=lKQ
Cx=O.OlfJ.F
HC-244
Ta--40 -85"C
UNIT
LIMIT
95
19
16
95
ns
19
16
-
-
fJ.s
-----------------------------TC74HC123AP/AF/AFN
AC E LECTRICA L CH ARACTERISTICS(C L =15pF, Vcc=5V, Ta=25"C)
PARAMETER
Output Transition Time
Propagation Delay Time
CA, B-Q. "Q")
Propagation Delay Tim.!!.
(CLR TRIGGER-Q, Q)
Propagation DeiaL Time
(CLR-Q, Q)
SYMBOL
TEST CONDITION
MIN.
tTI.H
trw
tplJl
tl~il.
tpLiI
t~iL
TYP.
MAX.
-
4
8
-
25
36
-
26
41
-
16
27
tpLH
t,~IL
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =t,=6ns)
PARAMETER
SYMBOL
Output Transition Time
t TLil
tTH!.
Propagation Delay Time
(A,B-Q,Q)
tpUI
t'lI-ll.
Propagation Delay Time
(CLR TRIGGER-Q,Q)
tpLH
tpllL
Propagation Delay Time
(CLR-Q,Q)
tpLH
tpHL
Output Pulse Width
tWOLT
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
. 6.0
2.0
4.5
6.0
2.0
4.5
6.0
Cx=28PF
2.0
Rx=6KQ(Vcc =2V) 4.5
Rx=2K Q(VCC =4.5V .6V) 6.0
2.0
Cx=O.Olp.F
4.5
Rx=lOKQ
6.0
2.0
Cx=O.lp.F
4.5
Rx=lOKQ
6.0
MIN.
-
-
-
-
-
90
95
95
0.9
0.9
0.9
Ta-25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
30
75
95
8
19
15
7
13
16
102
210
265
29
42
53
22
36
45
ns
102
295
235
31
47
59
23
40
50
68
160
200
20
32
40
16
27
34
700
2500
2000
250
ns
400
500
210
425
340
90
110
130
130
105
115
95
p.s
115
105
115
95
115
1.0
1.2
0.9
1.2
1.0
1. 1
ms
0.9
l.l
1.0
1.1
0.9
1.1
Output Pulse Width Error
Between Circuits
%
±1
.o.twOl
(In same Package)
Input Capacitance
5
CI:'\
10
10
pF
CPD(l}
Power Dissmation C~acitance
162
Note (!) Cm is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC q,o=C PD· Vcr;. f II, +1 cr; , • Duty/IOO+lcr; 12(per circuit)
Ocr; ':Active Supply Current)
(Duty:%)
-
HC-245
TC74HC123AP/AF/AFN - - - - - - - - - - - - - - - - OUTPUT PULSE WIDTH CONSTANT K-SUPPLY VOLTAGE (TYPICAL)
(EXTERNAL RESISTOR(Rx)=IOkO;twOU-r=K • ex. Rx)
~
!Z«
C!-o.Oh'F
t; 1.1
z
o
":x:t-
C~=O.I~~
o
i
1.0
bX·h~
w
en
..J
::.
a..
!; 0.9
a..
t::.
o
2
3
4
5
6
SUPPL Y VOLTAGE Vee (V)
tWOUT
t rr -Vee CHARACTERISTICS (TYP.)
-Cx CHARACTERISTICS (TYP.)
Vcc=4.5V
CL =50pF
T.-Z5'C
Rx=IMQ
/
10' ,
10
V
!I:
!
-
l-
:=)
•
:t
~
10·
Rx·'00kQ
/
V
i=
w
e
C)
C)
w
en
..J
:=)
a..
RX=10kO
10
/
1
a:
I-
V
./
V
l-
......
:=)
a..
./
t-
:=)
0
1
:E
RX=1kO
:i
10-'
0.1
0
10'
10'
10'
EXTERNAL CAPACITOR Cx (pF)
I
2
3
SUPPLY VOLTAGE
HC-246
.......
'"
z
/
Cx=O.01~F-
I---r--
r'~r'" .. ... .. . c:J
w
a:
:E
:=)
.........
a:
l-
i
'""-
w
:E
'/
./
0
4
Vcc(V)
5
8
TC74HC125API AF I AFN
TC74HC126API AF
TC74HC125APt AFt AFN
TC74HC126APt AF
QUAD BUS BUFFER
QUAD BUS BUFFER
The TC74HC125A/126A are high speed CMOS QUAD
BUS BUFFERs fabricated with silicon gate C2 MOS
technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
_
The TC74HC125A requires the 3-state control input G to
be set high to place the output into the high impedance
state, whereas the TC74HC126A requires the control.input
to be set low to place the output into high impedance.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P( 01 P14-P-300)
14~ 14~
1
FEATURES:
• High Speed .............................. tIXl =lOns(Typ.)at Vee=5V
• Low Power Dissipation ............... lee=4/lA(Max.)atTa=25"C
• High Noise Immunity··············· V,IH=V"IL=28% Vee(Min.)
• Output Drive Capability··· ......... 15 LSTTL Loads
• Symmetrical Output Impedance ···1101-\1 =IOL =6mA(Min.)
• Balanced Propagation Delays ...... tpLH""tpi-IL
• Wide Operating Voltage Range ... Vee (opr)=2V -6V
• Pin and Function Compatible with 74LS125/126
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
TC74HC126A
1G
cc
14 V
4G
1A
2
"
2Y
3
12 4A
2G
4
2A
Ii
"
2Y
•
10 3G
•
•
GN07
IEC LOGIC SYMBOL
4Y
(TOP
3A
3Y
VIEW)
TC74HC126A
14 V
1G
TC74HC126A
TC74HC126A
1Y
1Y
2Y
(11)
1A
2Y
3Y
4Y
3Y
2Y
2G
2A
2Y
2
3
"12
.
11
6
10
•
8
4G
4A
4Y
3G
3A
• 3Y
GN0 7
(TOP
HC-247
cc
VIEW)
TC74HC125AP/AF/AFN _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC126API AF
TRUTH TABLE
TC74HC12&A
INPUTS
A
H
X
L
L
L
H
G
TC74HC126A
OUTPUTS
Y
INPUTS
A
L
X
H
L
H
H
G
Z
L
H
OUTPUTS
Y
Z
L
H
X:Don't Care
X:Don't Care
Z: High
Z: High
Impedance
HC-248
Impedance
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC125AP/AF/AFN
TC74HC126API AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI:"
VOUT
11K
10K
lOUT
lee
PD
Tstg
TL
UNIT
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vcc+0.5
±20
±20
±35
±75
500(DIP) *1180(MFP)
-65 -150
300
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Input Rise and Fall Time
tr • tr
UNIT
V
V
V
"C
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vee =2.0V)
0- 500(Vee =4.5V)
0- 400(Vee=6.0V)
Vee
VI;>;
VOl-T
Topr
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
VOL
3-State Output
Off-State Current
I~
Input Leakage Current
Quiescent Supply Current
IN
lee
TEST CONDITION
VI:" =
VIHorVIL
VI;>; =
VIHorVIL
IOi =-20J.l A
IOi =-6 rnA
1m =-7.8mA
IOL =20 J.lA
IOL -6 rnA
IOL =7.8mA
VI;>; -VIH or V IL
VOLT =Vee or GND
VI;>; -Vee or GND
VI;>; -Vee or GND
Ta--40 -85"C UNIT
Ta-25"C
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.5
4.4
4.4
V
5.9
5.9
6.0
4.31
4.13
4.18
5.80
5.63
5.68
0.0
0.1
0.1
0.0
0.1
0.1
V
0.0
0.1
0.1
0.17
0.26
0.33
0.33
0.26
0.18
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
MIN.
1.5
3.15
4.2
6.0
-
-
±0.5
-
±5.0
6.0
-
-
+0.1
4.0
-
+1.0
40.0
-
HC-249
-
J.lA
TC74HC125AP/AF/AFN ________----__-------------TC74HC126API AF
AC ELECTRICAL CHARACTERISTICS(lnput t r =t,=6ns)
Ta- 40 -85"C
TEST
Ta-25"C
UNIT
PARAMETER
SYMBOL
CONDITION CL
Vee MIN. TYP. MAX. MIN. MAX.
2.0
20
75
60
tTI.H
Output Transition Time
4.5
12
15
50
6
tTIiL
6.0
13
5
10
2.0
30
90
115
50
4.5
11
18
23
6.0
10
tpUI
15
20
Propagation Delay Time
2.0
42
130
165
tpilL
150 4.5
14
26
33
6.0
12
22
28
ns
2.0
30
90
115
50 4.5
11
18
23
6.0
10
tpZl.
20
15
Output Enable time
RL = 1 kQ !
2.0
42
tJUj I
130
165
150 4.5
14
26
33
6.0
12
22
28
2.0
24
100
125
tpL7;
Output Disable time
R L = 1 kQ
4.5
12
50
20
25
tpHZ
6.0
10
17
21
Input Capacitance
10
5
10
C!:'\
Output Capacitance
pF
10
COLT
Power Dissipation Capacitance
CroUl
41
Note(l) Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IeeU>l}=CPD Va: fl\ +Ia: /4(per Gate)
I
0
0
HC-250
TC74HC131AP/AF
3-TO-8 LINE DECODER/LATCH
The TC74HC131A is a high speed CMOS 3-to-8 LINE
DECODER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintainiqg the CMOS low power
dissipation.
It is composed of 3·-bit input register with a common
CLOCK input and 3-to-8 line decoder with enable inputs
Gl and G2. The 3-bit binary data is stored into input
register on the positive going transition of the clock pulse.
The value of the binary data determines which one of
outputs will go to low.
When enable input G1 held low or G2 is held high, the
decoding function is inhibited and all outputs go high ..
These enable inputs are provided for cascade connection
and for use as an address d.ecoder for memory systems.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
FEATURES:
• High Speed .............................. tpd=22ns(typ.)at Vee=5V
• Low Power Dissipation ............ Iee =4t.tA(Max.)at Ta=25"C
• High Noise Immunity .......... · .... V:"lH=V="IL =28111 Vee(Min.)
• Output Drive Capability ........ · .. · 10 LSTTL Loads
• Symmetrical Output Impedance'" I IOH I =101.. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range'" Vee (opr.)=2V-6V
A 1
B
C
CLOCK
(;2
Gl
Y7
2
3
4
5
6
7
GND 8
16
15
14
13
12
11
10
YO
Yl
Y2
Y3
Y4
V5
9
Y6
Vee
(TOP VIEW)
IEC LOGIC SYMBOL
CLOCK
A
B
C
Gl
02
(4)
C8
80
BIN/OCT
1
2
4
EN
YO
Yl
Y2
Y3
Y4
Y5
Y6
Y7
CLOCK
A
B
C
Gl
02
HC-251
(4)
(1)
C8
80
DMUX
:IGt
YO
Yl
Y2
Y3
Y4
Y5
Y6
Y7
TC74HC131AP/AF-------------------------------TRUTH TABLE
INPUTS
E.NABLE
G1
G2
CLOCK
OUTPUTS
SELECT
C
B
SELECTED OUTPUT
A
VO
V1
V2
V3
V4
V5
V6
V7
L
X
X
X
X
X
H
H
H
H
H
H
H
H
NONE
X
H
X
X
X
X
H
H
H
H
H
H
H
H
NONE
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
L
H
H
H
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
YO
V1
Y2
V3
Y4
V5
Y6
Y7
H
L
J
J
J
J
J
J
J
J
1..
X
X
X
NO CHANGE
X : DON'T CARE
SYSTEM DIAGRAM
ENABLE {G2
INPUTS G1....!6!-----L..J
CLOCK 4
A
VO
'11
SELECT
INPUTS
V2
B
'13
C
'15
V6
'17
HC-252
DATA
OUTPUTS
- - - - - - - - - - - - - - - - TC74HC131AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
-::-Input Diode Current
Output Diode Current
DC Output Current
DC V(:c/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI:--:
VOLT
11K
10K
10\:1'
I(:c
1=\)
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) *1180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
rnW
"C
"C
*500mW in the range of Ta=
-40·C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Vee
VI:--:
VOLT
Topr
Input Rise and Fall Time
tr , tc
VALUE
2-6
o -Vee
0- Vee
-40.- 85
0- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o - 400(Vee=6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Le\'el
Input Voltage
ViI.
High:- Level
Output Voltage
!
TEST CONDITION
I
Val
I
Low-Level
Output \'oltage
Va.
Input Leakage 'Current
Quiescent Supply Current
11:--:
Icc
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
100 =-20JlA 4.5
VI:--:=
6.0
VlllorVIL
1011 - 4 rnA 4.5
100 =-5. 2rnA 6.0
2. (l
Ia. =20 JlA 4.5
VI:--:=
6.0
VlllorVII• la. -4 rnA
4.5
I Ia. =5.2mA 6.0
VI,\ -Vee or GND
6.0
6.0
V 1:--: -Vec orGND
HC-253
Ta--40 -85"C UNIT
Ta-25"C
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.13
4.31
4.18
5.68
5.80
5.63
0.0
0.1
0.1,
0.1
0.0
0.1
V
0.1
0.1
0.0
0.33
0.17
0.26
0.33
0.26
0.18
±O.l
±1.0
JlA
40.0
4.0
MIN.
1.5
3.15
4.2
-
-
-
TC74HC131AP/AF-..........- - - - - - - - - - -...- -
TIMING REQUIREMENTS(lnput tr=tf=6ns}
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
t\\"(L)
t\\"\1-{)
Minimum Set-up Time
(A, B, C)
ts
Minimum Hold Time
(A, B, C)
th
Vee
2.0
4.5
6.0
2.0
4.5
6.0
I· 2.0
4.5
6 0
I
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
65
ns
13
Ta-25"C
LIMIT
TYP.
75
15
13
50
10
9
0
0
0
11
0
0
0
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTHL
tpUl
tlXiL
tpl.H
t IXiL
Propagation Delay Time
(CLOCK-\')
Propagation De~ Time
(Gl, G2- )
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
22
35
-
12
24
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =t f =6ns}
Ta- 40 -85"C
Ta-25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
2.0
30
75
95
tTLH
Output Transition Time
4.5
8
15
19
tTHL
6.0
7
13
16
2.0
200
240
78
Propagation Delay Time
tpl.H
ns
4.5
26
40
48
(CLOCK-\')
tpl-IL
6.0
22
34
41
2.0
175
60
140
Propagation Delay Time
tpLlI
4.5
15
28
35
(Gl, G2-Y)
tpHL
6.0
13
24
30
Input Capacitance
Cl~
10
5
10
pF
Power Dissipation Capacitance Cpo(l)
37
Note (!) C I'D is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating Current can be obtained by the equation:
lccQxl=CI'D • VCC· rl~ +lcc
-
-
-
HC-254
----TC74HC132AP/AF/AFN
QUAD 2-INPUT SCHMITT NAND GATE
The TC74HC132A is a high speed CMOS 2-INPUT NAND
SCHMITT TRIGGER GATE fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Pin configuration and function are the same as the
TC74HCOOA but the inputs have 25% V cc hysteresis and
with its schmitt trigger inputs. the TC74HC132A can be
used as a line receiver for slow input signals.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=l1ns(typ.)at Vcc=5V
• Low Power Dissipation ............... Icc =1 t.tA(Max.)at Ta=25"C
• High Noise Immunity··············· Vii = 1.1 V at Vcc=5V
• Output Drive Capability············ 10 LSTTL Loads
• Symmetrical Output Impedance ···1101·11=101.. =4mA(Min.)
• Balanced Propagation Delays ...... tpLIi"'tpHL
• Wide Operating Voltage Range ... Vcc(opr)=2V-SV
• Pin and Function Compatible with 74LS132
SYSTEM DIAGRAM.WAVEFORM
P( DIP14-P-300)
14~ 14~
1
F(SOP14-P-300)
FN(SOL 14-P-150)
PIN ASSIGNMENT
14 Vee
1A
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
(TOP VIEW)
IEC LOGIC SYMBOL
IA
IB
2A
2B
3A
3B
4A
4B
TRUTH TABLE
IY
2Y
3Y
4Y
HC-255
Y
A
B
L
L
H
L
H
H
H
L
H
H
H
L
TC74HC132AP/AF/AFN--------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL!
Vcc
VI\
VOLl'
Iu.;
10K
IOLT
Icc
~)
Tstg
TI.
VALUE
-0.5 -7
-0.5 -Vee "'"0.5
-0.5 -Vce+0.5
±20
±20
±25
±50
500( DIP) */180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85·C a derating factor of
-lOmWrc shall be applied
until 300m W.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Vcc
VI\
VOLT
Topr
VALUE
2-6
0- Vee
0- Vee
-40 - 85
UNIT
V
V
V
"C
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Positil'e
Threshold
Voltage
Negative
Threshold
Voltage
SYMBOL
I VI'
V\
Hysteresis
Voltage
VII
High-Level
Output Voltage
VOl
Low-Level
Output Voltage
V(~.
Input Leakage Current
Quiescent Supply Current
11\
Icc
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
I
6.0
2.0
Ial =-20p. A 4.5
VI\=
6.0
VUIOrVII. 101 4 rnA 4.5
101-1 =-5. 2mA 6.0
2.0
101. =20 p.A 4.5
VI\=
6.0
"UlorVII. 101. -4 rnA 4.5
I(~. ==5.2mA
6.0
VI\ -Vee or GND
6.0
VI\ -Vee orGND
6.0
HC-256
Ta-25"C
Ta--40 -85"C UNIT
TYP. MAX. MIN. MAX.
1. 25
1.5
1.0
1.5
V
2.7
3. 15
2.3
3.15
3.0
3.5
4.2
4.2
0.9
0.65
0.9
0.3
V
2.0
2.0
1.6
1.13
2.6
2.3
2.6
1.5
1.5
0.3
0.6
1.0
0.3
1.0
V
0.6
1.4
0.6
1.4
1.1
0.8
1.2
1.7
0.8
1.7
2.0
l.9
1.9
4.4
4.4
4.5
V
5.9
5.9
6.0
4.13
4. 18
4.31
5.63
5.68
5.80
0.1
0.0
0.1
0.1
0.1
0.0
V
0.1
0.0
0.1
0.26
0.33
O.li
0.18
0.33
0.26
±0.1
±1.0 p.A
10.0 I
1.0
MIN.
1.0
2.3
3.0
0.3
1.13
- - - - - - - - - - - - - - TC74HC132AP/AFI AFN
AC ELECTRICAL CHARACTERISTlCS(C L =15pF,Vcc =SV,Ta=2S·C)
PARAMETER
SYMBOL
Output Transition Time
tT1.I1
tT1l1.
tpl.Il
t"llI,
Propagation Delay Time
TEST CONDITION
TYP.
MIN.
-
i
fUNIT
~
4
I
MAX.
11
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =t,=6ns)
Ta-25"C
Ta--40 -85 cC iUNIT
PARAMETER
SYMBOL TEST CONDITION
Vee MIN. I TYP. MAX. MIN. MAX. I '
i
2.0
75
95
30
tT1.I1
Output Transition Time
4.5
19
8
15
t'nll.
!
6.0
7 I
13
16
ns
2.0
42
110
1-10 I
tpl.II
Propagation Delay Time
4.5
22
28
14
tplll.
6.0
12
19
24
;
Input Capacitance
C I\
i
10
5 I
10 I
i pF
i
Power DissipalionCapacitance CmU)
I
I 29 I
Note (I) CI~) is defined as the "alue of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ieu:Prl=C m • Vee- fl\ +Icc I~(per Gate)
I
I
I
1
HC-257
I
I
I
"TC7 4HC133API AF
13-INPUT NAND
GATE
The TC74HC133A is a high speed CMOS l3-INPUT
NAND GATE fabricated with silicon gate C 2MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 7 stages, including a
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd =13ns(Typ. )at Vcc=5V
'. Low Power Dissipation .•..••...... Icc =lttA(Max.)at Ta=25°C
• High Noise Immunity ............... V~IH=V~IL28% Vcc(Min.)
• Output Drive Capability'" ..•...... 10 LSTTL Loads
• Symmetrical Output Impedance "'1 Iail =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH "" tpHL
• Wide Operating Voltage Range .•. Vcc (opr.)=2V-6V
• Pin and Function Compatible with 74LS133
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
A
1
16 Vee
B
2
15
C
3
14
L
o
4
13
K
E
5
6
12
11
J
F
10
H
9
Y
G 7
GND 8
M
(TOP VIEW)
IEC LOGIC SYMBOL
A
B
C
4
0
5
E
F
TRUTH TABLE
&
6
Inputs
Outputs
Inputs High
L
All Other Combinations
H
All
G
H
I
J
K
L
M
HC-258
- - - - - - - - - - - - - - - - TC74HC133AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI\:
VOLT
11K
10K
IOLT
lee
~)
Tstg
TI.
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) *1180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
rnW
"C
"C
*500mW in-the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m W/'C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI\:
VOLT
Topr
tr • tc
VALUE
2-6
o-Va;
0- Vee
-40 - 85
o- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o- 400(Va;=6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
High-Level
Input Voltage
Low-Level
Input Voltage
High-Level
Output Voltage
Low-Level
Output Voltage
Input Leakage Current
Quiescent Sup~ly Current.
!SYMBOL
TEST CONDITION
Va;
2.0
4.5
Viti
6.0
2.0
4.5
VII.
6.0
2.0
lal =-20Jl A 4.5.
VI\:=
Veli
6.0
VlllorVn.
lell --4 rnA 4.5
la·, =-5.2mA 6.0
2.0
Ia. =20 JlA 4.5
VI\:=
Vo .
6.0
VII_lorVIL
I c}. -4 rnA 4.5
lex. =5.2rnA 6.0
6.0
I I\:
VI\: -Vee or GND
lee ! VI\: -Vee or GND
6.0
HC-259
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
6.0
5.9
5.9
4.31
4.13
4.18
5.80
5.63
5.68
0.1
0.0
0.1
-.
0.0
0.1
0.1
V
0.0
0.1
0.1
0.33
0.17
0.26
0.33
0.18
0.26
- L ±0.1
~~:OO i Jl A
1.0 I i .. -
MIN.
1.5
3.15
4.2
1
TC74HC133AP/AF--------------------------------
AC ELECTRICAL CHARACTERISTlCS(C L =15pF. Vcc=5V. Ta=25"C. Input t r =tf=6ns)
PARAMETER
SYMBOL
Output Transition Time
t11_11
t11-l1.
tpl.1-!
tlll!1.
Propagation Delay Time
TEST CONDITION
MIN.
TYP.
-
4
8
-
13
22
MAX.
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =tf=6ns)
Ta- 40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
2.0
25
75
95
tTU'1
Output Transition Time
4.5
7
15
19
t TlII •
'6.0
16
6
13
ns
2.0
I 42
130
165
I
tpl.H
Propagation Delay Time
4.5
26
33
16
tpl'lL
6.0
22
28
14
Input, Capacitance
- I
5
10
10
C I:\
pF
, Power Dissipation Capacitance
- I 29
CPDW
Note(l) C m is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
PARAMETER
SYMBOL TEST CONDITION
Vee
MIN.
1
lCCQ>o=C PD· Va;. r 1:\ +1
a::
HC-260
------TC74HC137AP/AF
3-TO-8 LINE DECODER/LATCH
The TC74HC137A is a high speed CMOS 3-to-8 LINE
DECODER ADDRESS LATCH fabricated with silicon
gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It is composed of a 3-bit input latch with a common
GL enable input and a 3-to-8 line decoder with enable
inputs G1 and 02. The 3-bit binary data is stored into the
input latch on the high level of GL. The value of this data
determines which one of the outputs will go low. When the
enable input G1 is held low or 02 is held high, decoding
function is inhibited and all the 8 outputs go high. The
two enable inputs are provided to ease cascade connection
and permits the application of address decoder for
memory system.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP16-P-300A)
16~
1
F(SOP16-P-300)
PIN ASSIGNMENT
FEATURES:
• High Speed .............................. tpd=17ns(typ.)at Vee=5V
• Low Power Dissipation ............ Iee =4ttA(Max.)at Ta=25"C
• High Noise Immunity ............... v:"'IH=V~IL28% Vee (Min.)
• Output Drive Capability······ ...... 10 LSTTL Loads
• Symmetrical Output Impedance ... 1101-1 I =101.. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range ... Vee (opr. )=2V -6V
• Pin and Function Compatible with 74LS137
A
16 Vee
B
2
16 VO
C
3
14 V1
GL
4
13 V2
(32
6
12 V3
G1
6
11 V4
;;7
7
10 V6
9
GNO
(TOP VIEW)
IEC LOGIC SYMBOL
GL
A
B
e
GI
02
YO
YI
GL
V2
V3
V.
V5
V6
B
A
e
GI
02
'(7
YO
YI
V2
V3
V.
V5
V6
'(7
HC-261
V6
TC74HC137AP/AF-------------------------------TRUTH TABLE
INPUTS
ENABLE
OUTPUTS
SELECTED OUTPUT
ADDRESS
GL
G2
G1
C
B
A
YO
Y1
Y2
Y3
Y4
Y5
X
X
L
X
X
X
H
H
H
H
H
H
H
H
NONE
X
H
X
X
X
X
H
H
H
H
H
H
H
H
NONE
L
L
H
L
L
L
L
H
H
H
H
H
H
H
YO
L
L
H
L
L
H
H
L
H
H
H
H
H
H
Y1
L
L
H
L
H
L
H
H
L
H
H
H
H
H
Y2
L
L
H
L
H
H
H
H
H
L
H
H
H
H
Y3
L
L
H
H
L
L
H
H
H
H
L
H
H
H
Y4
L
L
H
H
L
H
H
H
H
H
H
L
H
H
Y5
L
L
H
H
H
L
H
H
H
H
H
H
L
H
Y6
L
L
H
H
H
H
H
L
H
X
X
X
X:Don't
Y6
Y7
H
H
H
H
H
H
H
L
Y7
OUTPUTS are latched at the ti'me when GL is taken High level.
care
SYSTEM DIAGRAM
A
ADDRESS B
DATA
INPUTS
OUTPUTS
c
ENABLE
02
INPUTS
HC-262
--------------------------------TC74HC137AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee I
VI\
VOLT!
11K
1m:
IOLT !
Icc
i
I-J)
Tstg
TI.
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vce+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
I
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-40·C- 65"C. From Ta=65'C
to 85"C a derating factor of
-10m Wrc shall be applied
unti1300mW.
"C
°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
-=--:
Input Voltage
Output Voltage
Operating Temperature
I SYMBOL
I Vee I
I VI\ Ii
i
!
VOLT
Topr I
I
Input Rise and Fall Time
I tr • tr
I
VALUE
2-6
aa-
Vee
Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vce =4.5V)
o - 400(Vee =6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAl\-1ETER
High-Level
Input Voltage
Low-Level
Input Voltage
High-Level
Output Voltage
VIII
i
I VII.
I
V(~I
Ta- 40 -85"C iUNIT
Ta-25"C
I
Vee ! MIN. TYP. MAX. MIN. MAX.]
I
1.5
! 2. a 1.5
II V
3.15
3. 15
i 4.5
I
4.2
I 6. a 4.2
I
2. a '
0.5 I
0.5
V
4.5
1. 35
1. 35
6. a
1.8
1.8
2. a
2.0
1.9
1.9
Ia-J =-20tl A 4.5
4.5
4.4
4.4
VI\ =
V
6. a
5. 9
6.0
5.9
VlllorVIl .
4.31
4.13
laJ - 4 rnA 4.5
4. 18
1m =-5. 2mA 6. a ! 5.68
5.80
5.63
0.0
0.1
0.1
2. a
IOL =20 tl A 4.5
O. a
O. 1
O. 1
VI\ =
V
o.
a
0.1
0.1
6.
a
i
VII IorVIl .
10 . -4 rnA 4.5
0.26
0.17
0.33 I
i
0.18
la. =5.2mA 6. a ! 0.26
0.33 I
±0.1 . ! 6. a
VI\ -Vee or GND
±1. 0 I A
I
40.0 I tl
VI\ -Vel' orGND
6.0 I 4.0 I i
TEST CONDITION
I
I
I
I
I
I
I
I
I
Low-Level
Output Voltage
Input Leakage Current
Quiescenl Supply Currenl
V(~_
I II,
Icc
I
I
HC-263
TC74HC137AP/AF---------------TIMING REQUIREMENTS(lnput tr=tf=6ns)
PARAMETER
Minimum Pulse Width
(GL)
SYMBOL TEST CONDITION
tW(1.)
Minimum Set-up Time
(A. B. C-GL)
ts
Minimum Hold Time
(A. B. C-GL)
th
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C
TYP.
LIMIT
75
-
I
-
15
13
i
Ta--40 -85"C
UNIT
LIMIT
95
19
16
65
ns
13
11
30
6
5
~-+
25
-
~
i
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25°C.lnput t r =tf=6ns)
Output Transition Time
tTI.H
tml.
-
4
tl~.11
-
11
19
-
12
19
-
18
29
-
17
28
(G2-Y)
Propagation Delay Time
(GL-Y)
Propagation Del!!y Time
(A. B. C-Y)
tllliL
tpLH
tul-II.
tlLH
toilL
tpLH
tul-II.
MIN.
TYP.
MAX.
SYMBOL
Propagation Delay Time
(GI-Y)
Propagation Delay Time
TEST CONDITION
I
PARAMETER
i
I
UNIT
8
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =tf=6ns)
Ta- 40 -85°C
Ta-25"C
UNIT
PARAMETER
SYMBOL TEST CONDITION
Va: MIN. TYP. MAX. MIN. MAX.
2.0
75
95
30
tTLII
Output Transition Time
4.5
8
19
15
tnlL
6.0
7
13
16
2.0
145
45
115
Propagation Delay Time
tpUi
4.5
29
14
23
(GI-Y)
tpilL
6.0
25
12
20 , ,
- I 145
2.0
50
115
Propaga~n ~Iay Time
ns
23
29
4.5
15
! tpllL
(G2-Y)
tlllil.
I
25
13
20
6.0
70
170
215
2.0
Propagation D.!lay Time
tpllL
-.
22
43
4.5
34
(GL-Y)
tplil.
6.0
37
19
29
205
2.0
70
165
Propagation Delay Time
tpllL
4.5
21
33
41
(A. B. C-Y)
tplil.
28
35
6.0
18
Input Capacitance
C I:\
5
10
10
pF
Power Dissipation Capacitance CpDm
56
Note (J) C H) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
A\'erage operating current can be obtained by the equation:
I CCt1lli=C 1'1)· Vex:. f 1:\+1 ex:
I
HC-264
----------------TC74HC137AP/AF
TYPICAL APPLICATION
STROBE
DECODER
ENABLE
XO
X1
X2
GL
C
I
B A
G2 G1
YO Y1 Y2 Y3 Y4 Y5 Y8 Y7
INPUT
ADDRESS
'1''1''1' '1''1'
,
TO FIVE
OTHER
DECODERS
X3
X4
X5
I
I
GL
C
B A
I
A
G2 G1
GL
I
I
C
I
B A
G2 G1
YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
IIYII'I''I'I
01234587
II'(IIIIY
8
9 10 11 12 13 14 15
A
GL
1
I
C
B A
G2 G1
YOY1 Y2 Y3 Y4 Y5 Y6 Y7
II III
r 'I' 'I'
16 17 18 19 20 21 22 23
OUTPUTS
8 L.ine to 84 Line Decoder with Input Address Storage
HC-265
I
TC74HCTI37AP/AF-----3-TO-8 LINE DECODER/LATCH
The TC74HCT137A is a high speed CMOS 3-to-S LINE
DECODER ADDRESS LATCH fabricated with silicon
gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
It is composed of a 3-bit input latch with a common GL
1
P(DIP16-P-300A)
16~
enable i!Ylut, and a 3-to-8line decoder with enable inputs
Gl and G2. The 3-bit binary data is stored into the input
latch on the high level of GL. The value of this data
determines which one of the o.!!tputs will go low. When the
enable input Gl is held low or G2 is held high, the decoding
function is inhibited and all the 8 outputs go high. The two
enable inputs are provided to ease cascade connection and
permits the application of address decoder to memory
systems.
F(SOP16-P-:300}
PIN ASSIGNMENT
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
A
FEATURES:
• High Speed .............................. tlXl=17ns(typ.)at Vee=5V
• Low Power Dissipation ............ Iee =4#A(Max.)at Ta=2S"C
• Compatible with TTL outputs ...... VIH =2V(Min.)
V 1L =O.SV(Max.)
• Output Drive Capability ........ •.. · 10 LSTTL Loads
• Symmetrical Output Impedance "'1 IOH 1=101. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH" tpHL
• Wide Operating Voltage Range'" Vee (opr.)=2V -6V
• Pin and Function Compatible with 74LS137
18 Vee
B
2
16 VO
3
14
4
13 V2
02
&
12 V3
Gl
8
11 V4
V7
7
10 V6
8
8
GND
(TOP VIEW)
IEC LOGIC SYMBOL
or
A
B
e
or
YO
Yl
V2
V3
A
B
e
01
iii
YO
Yl
V2
V3
'14
'14
V,
Ve
01
02
'17
HC-266
VI
C
GL
V.
Ve
"17
V8
- - - - - - - - - - - - - - - - - TC74HCT137AP/AF
TRUTH TABLE
INPUTS
ENABLE
OUTPUTS
SELECTED OUTPUT
ADDRESS
GL
G2
G1
C
B
A
va
'11
V2
V3
'14
V5
va
V7
x
X
L
H
H
H
H
H
H
NONE
X
H
H
H
H
H
H
H
H
NONE
L
L
L
L
L
H
H
H
H
H
YO
L
L
L
H
H
L
H
H
H
L
H
H
X
X
L
H
H
X
X
H
X
X
X
H
H
H
H
H
Y1
L
L
H
L
H
L
H
H
L
H
H
H
H
H
Y2
L
L
H
L
H
H
H
H
H
L
H
H
H
H
Y3
L
L
H
H
L
L
H
H
H
H
L
H
H
H
Y4
L
L
H
H
L
H
H
H
H
H
H
L
H
H
Y5
L
L
H
H
H
L
H
H
H
H
H
H
L
H
ya
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
X
X
X
X:Don't
Y7
OUTPUTS are latched at the time when GL is taken High level.
care
SYSTEM DIAGRAM
A
ADDRESS B
INPUTS
DATA
OUTPUTS
c
ENABLE
INPUTS
'02
-GL~
., ''_v~
_
_ _::
HC-267
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Voor
11K
10K
Ioor
lee
Po
Tstg
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+O.5
±20
±20
±25
±50
500(DIP)*1180(MFP)
-65 -150
300
*500m W in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-lOmW/'C shall be applied
until 300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
VALUE
Vee
4.5 - 5.5
0- Vee
0- Vee
-40 - 85
0-500
VI"
VOLT
Topr
t r • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VlH
Low-Level
Input Voltage
VlL
High Level
Output Voltage
Low-Level
Output Voltage
Input Leakage Current
Va;
MIN.
TYf'.
MAX.
I
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
4.4
4.18
4.4
4.13
-
-
V
-
4.5
4.31
0.0
0.17
Va;
10l
-
-
~Icc
I
Ia; - 20u A
VINVlHorVlL 100 --4 rnA
Vl;-';=
10l -20 uA
VlHorVlL 101. -4 rnA
Vl:-i =Vee or GND
Vl:-i -Vee or GND
PER INPCT:Vl:-i=O.5Vor2.4V
OTHER INPCT:Vee or GND
Ta- 40 -85"C
UNIT
MiN. MAx.
Vee
4.5
5.5
4.5
ll~
Quiescent Supply Current
Ta-25"C
TEST CONDITION
5.5
4.5
4.5
4.5
4.5
5.5
5.5
5.5
HC-268
-
-
0.1
0.26
±0.1
4 0
2.0
-
-
0.1
0.33
+1.0
40 0
2.9
V
UA
rnA
- - - - - - - - - - - - - - - - - TC74HCT137AP/AF
TIMING REQUIREMENTS(lnput t r =tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Ta -40 -85"C
'ra-25_"G_
TYP.
LIMIT
Vcr:.
-
Ll~lT
Minimum Pulse Width
(GL)
tW(L)
4.5
5.5
-
10
9
13
11
Minimum Set-up Time
(A, B, C-GL)
ts
4.5
5.5
-
10
9
13
Minimum Hold Time
(A, B, C-GL)
th
4.5
5.5
5
5
5
5
-
UNIT
ns
11
AC ELECTRICAL CHARACTERISTICS(C L =15pF. Vcc=5V.Ta=25"C. Input t r =tf=6ns)
PARAMETER
Output Transition Time
Propagation Delay Time
(Gl-Y)
Propagation Delay Time
(G2-Y)
Propagation Delay Time
(GL-Y)
Propagation Del!l Time
(A, B, C-Y)
SYMBOL
TEST CONDITION
MIN.
tn.H
tniL
tpLH
tpHL
tpLH I
toHl
tpLH
tnHT
tpLH
toHl
MAX.
TYP.
-
6
12
-
15
23
15
23
22
32
21
32
-
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =tf=6ns)
Ta--40 -85"(
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vee I MIN. TYt'. l\iA~· ~. ~A~.
Output Transition Time
tTLH
tniL
4.5
5.5
Propagation Delay Time
(GI-Y)
tpLH
tpHL
4.5
5.5
Time
tpHL
tpHL
4.5
5.5
Propagation D..,!lay Time
tpHL
tpHL
4.5
5.5
Propagati9n
~lay
(G2-Y)
(GL-Y)
I -
-
15
13
18
16
27
24
19
17
29
26
26
20
38
34
-
-
-
19
16
34
31
36
33
ns
48
43
25
48
38
23
43
34
Input Capacitance
5
CI\' I
10
!
10
pF
Power Dissipation Capacitance Cpo(J) I
56
Note (1J C ro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption "..ithout load.
Average operating current can be obtained by the equation:
Icc q,o=C po· Vex:. f I\, .... I ex:
Propagation Delay Time
(A. B. C-'Y)
4.5
5.5
tpHL
tpHL
HC-269
I
-
8
7
-
-
-
TC74HCT137AP/AF - - - - - - - - - - - - - - - - TYPICAL APPLICATION
STROBE
DECODER
ENABLE
XO
X1
X2
OL
I
C B A
0201
VO V1 V2 V3 V4 V5 VB V7
INPUT
ADDRESS
III II
I
TO FIVE
OTHER
DECODERS
X3
X4
X5
I
I
OL
C B A
G2G1
)..
OL
T
I
C B A
T
G2 G1
)..
GL
r
I
C B A
1
G2 01
VO V1 V2 V3 V4 V5 VB V7
VO V1 V2 V3 V4 V5 V8 V7
VO V1 V2 V3 V4 V5 V8 V7
I0 1
Y 2Y3IIII
I
4587
IIIYIIIY
8 9 10 11 12 13 14 15
18 17 18 18 20 21 22 23
11II rlTT
OUTPUTS
8 Line to 64 Line Decoder with Input Addre.. Storage
HC-270
NOTES
TC74HC138APt AFt AFN
3-TO-8 LINE DECODER
The TC74HC138A is a high speed CMOS 3-to-8
DECODER fabricated with
silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
When the device is enabled, 3 Binary Select inputs (A,B
and C) determine which one of the outputs (VO-VI) will
go low.
Whim enable input Gl is held low or either G2A or G2B
is held high, decoding function is inhibited and all outputs
go high.
'
Gl, G2A, and G2B inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP16-P-300A)
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
A
FEATURES:
• High Speed .............................. tpd=16ns(Typ.)at Vee =5V
• Low Power Dissipation ............ Iee =4/LA(Max.)at Ta=25"C
• High Noise Immunity .............. · V!l:IH=V-;IL 2896 Vee(Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance ... I IOH I=Ia. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage"Range'" Vee (opr)=2V -6V
• Pin and Function Compatible with 74LS138.
B
16
2
C
Vee
15 VO
14 Yl
G2A
4
13 Y2
G2B
5
12 Y3
Gl
6
11 V4
V7
7
10 V6
GND
8
9
V6
(TOP VIEW)
IEC LOGIC SYMBOL
A
B
C
01
G2A
028
A
VO
VI
V2
V3
V4
V6
B
e
va
V7
HC-272
VO
VI
V2
V3
V4
Gl
Y6
G2A
028
va
V7
- - - - - - - - - - - - - - TC74HC138AP/AF/AFN
TRUTH TABLE
INPUTS
ENABLE
G1
OUTPUTS
SELECT
G2A GZB
SELECTED OUTPUT
C
B
A
YO
Y1
-Y2
Y3
Y4
X
X
X
X
X
X
H
H
H
H
H
H
H
H
NONE
H
H
H
H
H
H
H
H
NONE
H
H
H
H
H
H
H
H
NONE
-
Y5
-
Y6
'(7
L
X
X
X
H
X
X
X
H
X
X
X
H
L
L
L
L
L
L
H
H
H
H
H
H
H
YO
H
L
L
L
L
H
H
L
H
H
H
H
H
H
Y1
H
L
L
L
H
L
H
H
L
H
H
H
H
Y2
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
Y3
H
L
L
H
L
L
H
H
H
H
L
H
H
H
Y4
H
L
L
H
L
H
H
H
H
H
H
L
H
H
Y5
H
L
L
H
H
L
H
H
H
H
H
H
L
H
Y&
H
L
L
H
H
H
H
H
H
H
H
H
H
L
Y7
X : Don't Care
LOGIC DIAGRAM
15 Yo
14 Yl
1a Y2
12Ya
11 Y4
10 Ys
A 1
l
SELECT!
INPUTS
B 2
C a
ENABLEj
INPUTS
4
G2A
5
G2 B
6
G1
HC-273
DATA
~OUTPUTS
9 -
I
I
7
J
~6
Y7
TC74HC138AP/AF/AFN--------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DlP) *1180(MFP)
-65 -150
300
SYMBOL
Vee
VI\
VOLT
11K
10K
IOLT
lee
PD
Tstg
TI.
I
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
°C
*500mW in the range of Ta=
-4Q'C- 65·C. From Ta=65'C
to 85"C a derating factor of
-10m Wf"C shall be applied
unti1300mW.
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Vee
VI:\
VOlT
Topr
I
Input Rise and Fall Time
VALUE
2-6
0- Vee
o-Vee
-40 - 85
o- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
0- 400(Va;=6.0V)
SYMBOL
I
Itr , tr I
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
Low-Level
Input Voltage
High-Level
Output Voltage
TEST CONDITION
VIII
I
VII.
V(Jl
VI:\=
VIIIorVII•
laJ =-20JL A
lUI
1011
Low-Level
Output Voltage
Ve~.
Input Leakage Current
Quiescenl Supply Currenl
11:\
Ice
VI:\=
VII·lorVII •
= 4 rnA
=-5. 2mA
loJ. =20 JLA
lex. -4 rnA
I(~. =5.2mA
VI:\ -Vee or GND
V 1:\ -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
~. 0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-274
Ta-25°C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3. 15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
1.9
2.0
4.5
4.4
4.4
V
6.0
5.9
5.9
4.31
4.18
4.13
5.68
5.63
5.80
0.0
O. 1
O. 1
0.1
0.0
O. 1
V
O. 1
0.0
0.1
O. Ii
0.26
0.33
0.26
0.33
0.18
±1.0
=0.1
JLA
.J-.O I
40.0
MIN.
1.5
3.15
4.2
-
- - - - - - - - - - - - - - TC74HC138AP/AF/AFN
AC ELECTRICAL CHARACTERISTICS(C L =15pF, Vc c=5V, Ta=25"C)
PARAl\lETER
Output Transition Time
SYMBOL
!I
tTLII
t'rln,
Propagation De~y ~t"LI!
(A,8,C-Y)
t,,1I1.
PropagatioE. D!!ay Time
t"LI!
(G,G-Y)
t >111.
TEST CONDITION
'
MIN.
TYP.
MAX.
4
8
16
26
15
25
UNIT
ns
AC ELECTRICAL CHARACTERISTlCS(C L =50pF,lnput t r =tf=6ns)
Ta--40 -85"C
Ta-25OC
PARAl\IETER
SYMBOL TEST CONDITION
UNIT
Vee MIN. TYP. MAX. MIN. MAX.
75
I 2.0
95
30
tTLI!
Output Transition Time
15
4.5
19
8
tl1lL
6.0
13
16
7
2.0
70
150
190
Propagation Delay Time
tpl.f!
4.5
ns
30
19
38
(A,8,C-Y)
tpl !L
6.0
26
32
16
145
180
2.0
65
Propagation Delay Time
tpLI!
18
29
36
4.5
(G,G-Y)
tpLH
25
6.0
15
31
Input Capacitance
5
10
10
C!\
pF
Power Dissipation Capacitance
CPD(l)
47
~ote (1) em is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consu'mption without load,
Average operating current can be obtained by the equation:
ICCq",=C I'll· Vo:;. fl\ +10:;
-
HC-275
-
TC74HCT138AP/AF/AFN
3-TO-8 LINE DECODER
The TC74HCT138A is a high speed CMOS 3-to-8
LINE DECODER fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are
compatible with TTL,NMOS and CMOS output voltage levels.
When the device is enabled, 3 Binary Select inputs (A,B
and C) determine which Olle of the outputs (YO- Y1) will
go low.
When enable input G1 is held low or either G2A or G2B
is held high, decoding function is inhibited and all outputs
go high.
G1, G2A, and G2B inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd=17ns(Typ.)at Vcc=5V
• Low Power Dissipation ............ Icc=4t.tA(Max.)at Ta=25"C
• Compatible with TTL outputs········· V IH =2V (Min.)
VIL =0.8V(Max.)
• Wide interfacing ability········· LSTTL,NMOS,CMOS
• Output Drive Capability········· ... 10 LSTTL Loads
• Symmetrical Output Impedance ···1 IOH I=IOL=4mA(Min.)
• Balanced Propagation Delays ...... tpLH'i tpHL
• Pin and Function Compatible with 74LS138.
1.
P(DIP16-P-30M)
1.~16~
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
A
16 Vee
B
2
C
3
14 Y1
G2A
4
13 Y2
G2B
5
12 Y3
G1
6
11 Y4
Y7
7
10 Y6
GND
8
9 YB
15 YO
(TOP VIEW)
IEC LOGIC SYMBOL
A
B
e
01
G2A
G2B
A
B
e
YO
Yl
Y2
Y3
Y4
Y6
Y6
Y7
DMUX
(1)
(2)
(3)
:}o f
&
01
G2A
G2B
HC-276
YO
Yl
Y2
Y3
Y4
Y6
Y6
Y7
- - - - - - - - - - - - - - TC74HCT138AP/AF/AFN
TRUTH TABLE
INPUTS
ENABLE
G1
OUTPUTS
SELECTED OUTPUT
SELECT
G2A G2B
C
B
A
VO
-Y1
\12
V3
V4
\15
\16
\17
L
X
X
X
H
H
H
H
H
H
H
H
NONE
H
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
NONE
X
X
H
X
X
X
H
H
L
L
L
H
H
H
H
H
NONE
L
H
H
H
L
H
H
H
H
H
L
H
YO
H
L
L
L
H
H
L
H
H
H
H
Y1
L
L
L
L
H
H
H
L
H
H
L
H
H
H
H
H
H
Y2
H
L
L
L
H
H
H
H
H
H
H
Y3
L
H
H
H
L
H
H
H
Y4
L
H
L
L
L
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
Y5
H
L
L
H
H
L
H
H
H
H
H
H
L
H
Y6
H
L
L
H
H
H
H
H
H
H
H
H
H
L
Y7
X : Don't Care
LOGIC DIAGRAM
1 S Yo
A
SELECT
INPUTS
14 Yl
1
13 Y2
2
12Y3
C 3
11 Y4
10YS
B
9 Y6
7 Y7
G2A 4
ENABLE! G2B s
6
INPUTS
Gl
HC-277
DATA
OUTPUTS
TC14HCT138AP/AF/AFN----------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI:o\
VOLT
11K
10K
IOLT
lee
PD
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(MFP2
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500m W in the range of Ta=
:"40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fa1i Time
SYMBOL
VALUE
Vee
VIX
VOLT
Topr
tr, tr
4.5 - 5.5
o -Vee
O-Vcc
-40 - 85
0-500
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
ViH
Low-Level
Input Voltage
VII.
High-Level
Output Voltage
High-Level
Output Voltage
Input Leakal!e Current
Quiescent Supply Curren
TEST CONDITION
vee
4.5
MIN.
1
2.0
5.5
4.5
Va-!
VOL
Ilx
Icc
L:>Ioo
1
10.1-:-20 /.LA
VIX =
V IH orVIL Ja.F-4 rnA
VIX =
h-20/.L A
VIIi orVIL h=4 rnA
Vlx·=Vccor GND
VIX =Veeor GND
PER INPl:T:\\\=O. 5V or 2.4V
OTHER INPl:T:Veeor GND
5.5
4.5
4.5
4.5
4.5
5.5
5.5
5.5
HC-278
4.4
4.18
Ta- 40 -85"(;
'l'a-25"C
UNIT
TYP. I MAX. MIN. MAX.
-
I
- I
-
4.5
4.31
0.0
0.17
-
-
I
-
I
-
-
-
2.0
-
V
0.8
.-
0.8
V
4.4
4.13
-
i
V
0.1
0.26
±0.1
4.0
-
-
0.1
0.33
±1.0
40.0
2.0
-
2.9
-
V
/1. A
rnA
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HCT138AP/AF/AFN
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
t",H
t11il
t plJ1
tpHL
tplil
toili.
tpLH
toHI,
Propagation Delay Time
(A,B,C-Y)
Propagation ~elay Time
(GI-Y)
Propagation Delay Time
(G2-Yl
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
17
28
-
15
25
-
17
28
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =50pF.lnput t r =t,=6ns)
Ta-25"C
Ta--40 ~85"C
UNIT
P ARA~'1ETER
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
Output Transition Time
tTLH
t"·IL
4.5
5.5
-
Propagation D~ay Time
(A,B·,C-Y)
tpLH
t'*IL
4.5
5.5
Propagation .!?elay Time
(GI-Y)
tplJI
tpHL
4.5
5.5
Propag~on .Qelay
tpLH
tpHL
4.5
5.5
(G2-Y)
Time
8
7
15
14
-
-
21
18
33
30
-
44
40
-
19
17
30
27
-
38
34
22
20
33
30
I
-
i
-
41
37
-
-
Ii
-
-
-
-
I
19
18
ns
Input Capacitance
10
CI:\
5
10
I
pF
Power Dissipation Capacitance
CpD(l)
55
I
Note (1) C PD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
iccq,.,=C 1D • Va:. £[\ +la:
HC-279
TC74HC139AP/AF/AFN
DUAL 2-TO-4 LINE DECODER
The TC74HC139A is a high speed CMOS 2 to 4 LINE
DECODER/DEMULTIPLEXER fabricated with silicon
gate C2MOS technology.
.
It achieves the high speed operation similar. to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The active low enable input can be used for gating or it
can be used as a data input for demultiplexing
applications.
When the enable input is held "H". all four outputs are
fixed at a high logic level independent of the other inputs.
All inputs are equipped with protection circuits against
static discharge or trasient excess voltage.
FEATURES:
• High Speed ................................. tpd=16ns(typ.)at Vr:x;=5V
P(DIP16-P-300A)
F(SOP16-P-300)
FN(S0L16-P-150)
PIN ASSIGNMENT
• Low Power Dissipation ............... I cc=41l A(Max. )at Ta=25"<;
• High Noise Immunity··············· V:-;IH =V :\IL =2896 Vr:x;(Min.)
• Output Drive Capability'" ......... 10 LSTTL Loads
1<3
• Symmetrical Output Impedance ,.. 11 00 1=1 01• =4mA(Min.)
• Balanced Propagation Delays ...... tpLl-l"'tpHL
• Wide Operating Voltage Range ... Vr:x;(opr)=2V-6V
1B 3
·16 Vee
1A 2
15
14
13
12
11
10
9
lYO 4
lYl 5
lY2
lV3
• Pin and Function Compatible with 74LS139
6
7
GND 8
2<3
2A
2B
2YO
2Yl
2Y2
2Y3
(TOP VIEW)
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS
IA
IB
10
2A
2B
20
lY'o
1'9"1
IVO
IA
IB
1<3
lY1
lY2
~I
2A
'iY2
2B
20
IY3
ffil
2VI
2V2
fY2
1Y3
ffil
M
M
OUTPUTS
SELECTED
ENAIU SELECT -YO -Y1 -Y2
Y3 OUTPUT
G
B
A
H
X
X
H
H
H
H
NONE
L
L
L
L
H
H
H
L
L
H
H
L
H
H
YO
Y1
·L
H
L
H
H
L
R
"«2
L
H
H
H
H
H
L
Y3
X: Don't
HC-2BO
care
--------------TC74HC139AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI:-J
Your
11K
10K
Icx.!,.
lee
PD
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
-
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
.PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
o -Vee
0- Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
0- 400(Vcc =6.0V)
SYMBOL
. Vee
VI]\;
VOLT
Topr
t r , tc
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
100 =-20p. A
VIN=
VIHorVIL
110H --4 rnA
100 =-5.2mA
Low-Level
Output Voltage
VOL
VI!\'=
VIHorVII•
Input Leakage Current
Current
I I"
lee
Quie~nt Supply
IOL =20 p.A
IOL =4 rnA
101. =5.2mA
V 1:,\ -Vee or GND
VI" -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6-.0
6.0
HC-281
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.5
4.4
4.4
V
5.9
5.9
6.0
4.31
4.13
4.18
5.68
5.80
5.63
0.1
0.0
0.1
0.1
0.1
0.0
V
0.1
0.1
0.0
0.33
0.26
0.17
0.33
0.26
0.18
+0.1
+1.0 p.A
40.0
4.0
MIN.
1.5
3.15
4.2
-
TC74HC139AP/AFlAFN - - - - - - - - - - - - - -
AC ELECTRICAL CH ARACTERISTICS(C L=16pF, Vcc=6V. Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTLfI
t1'l-l1.
tpLH
toHL
tpLH
tPl:tL
Propagation Delay Time
(A,B-Y)
Propagation Delay Time
(G-Y)
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
12
22
-
10
18
UNIT
ns
AO ELECTRICAL CHARACTERISTICS(CL =50pF.lnput t r =t,=6ns)
Ta- 40 -85"('
Ta-25"C
UNIT
PARAMETER
SYMBOL TEST CONQITION
Vex MIN. TYP. NiAX. MIN. MAX.
2.0
75
30
95
tTLH
Output Transition Time
4.5
15
19
8
tTHL
6.0
7
13
16
2.0
130
165
45
Propagation Delay Time
tpLH
ns
26
33
4.5
15
(A,B-Y)
tpHL
6.0
22
13
28
2.0
lIO
140
39
P.!:.opagation Delay Time
tpLH
4.5
22
28
13
(G-Y)
tpHL
6.0
24
19
11
Input Capacitance
10
10
CIN
5
pF
Power Dissipation Capacitance Cpo(l}
46
Note(l) Cro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lextp}=Cro • Vex· fN +Ia; 12(per Decoder)
HC-282
- - - - - - - TC74HCT139AP/AF
DUAL 2-10-4 LINE DECODER
The TC74HCT139A is a high speed CMOS 2 to 4 LINE
DECOPER/DEMULTIPLEXER fabricated with silicon
gate CMOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL.NMOS and CMOS output
voltage levels.
The active low enable input can be used for gating or it
can be used as a data input for demultiplexing applications.
1
P(DIP16-P-300A)
16~
1
When the enable input is held high, all four outputs ~re
set to a high logic level independent of the other inputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=17ns(typ.)at Vcc=5V
• Low Power Dissipation ............... Icc =4tt A(Max.)at Ta=25"C
• Compatible with TTL outputs ...... V1H =2V(Min.)
V1L =0.8V(Max.)
• Wide Interfacing ability········· LSTTL.NMO$.CMOS
• Output Drive Capability·.· .. ··•··.· 10 LSTTL Loads
• Symmetrical Output Impedance .. ·1 Iool=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH .. tpHL
• Pin and Function Compatible with 74LS139
F(SOP16-P-300)
PIN ASSIGNMENT
1(3
IA
IB
IVO
IVI
I
2
16 Vee
3
·14 2A
4
5
13 2B
IS 2(3
12 2Yo
IY2 6
11 2YI
IV3
7
10 2Y2
GND 8
9 2Y3
(TOP VIEW)
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS
lYe
lYo
lY1
lY'l
lY3
iVl
m
1VJ
2B
ffil
2V1
2V2
2V3
OUTPUTS
SELECTED
~ SELECT YO Yl Y2 Y3 OUTPUT
G
B
A
H
X
X
H
H
H
H
NONE
ffil
L
L
L
L
H
H
H
ffl
2Y2
2V3
L
L
H
H
L
H
H
VO
VI
L
H
L
H
H
L
R
Y2
L
H
H
H
H
H
L
V3
X: Don't care
HC-283
TC74HCT139AP/AF - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
P01"er Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VII'(
VOLT
11K
10K
Ioor
lee
PD
Tstg
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
VALUE
-0.5-7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(SOIC)
-65 -150
300
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-lOmW/'C shall be applied
until 300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperrature
SYMBOL
VALUE
\TCC
Input Rise and Fall Time
tr • tr
4.5 - 5.5
0- Vee
0- Vee
-40 - 85
0-500
VIX
VOLT
Topr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High Level
Output Voltage
Low-Level
Output Voltage
Input Leakage Current
Va-!
VOL
111\
~Icc
Ta=-40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
Vee
4.5
MIN.
l
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
4.4
4.18
-
4.5
4.31
0.0
0.17
-
5.5
4.5
lee
Quiescent Supply Current
TEST CONDITION
l
5.5
4.5
4.5
4.5
4.5
5 5
5.5
VIl~Ia-! =-20 tl A
VIHorVIL la-! - 4 rnA
VINIOL -20 tl A
VIHorVIL IOL =4 rnA
VI:'>J -Vee or GND
VI:,\ =Veeor GND
PER INPUT:VII'(=O. 5V or 2. 4V
5.5
OTHER INPUT:Vee or GND
HC-284
-
4.4
4.13
-
0.1
0.26
±O.l
4.0
-
2.0
-
-
V
0.1
0.33
±1.0
40.0
2.9
V
tl
A
mA
- - - - - - - - - - - - - - - - - TC74HCT139AP/AF
AC ELECTRICAL CHARACTERISTICS(C L =l&pF, Vcc =&V,Ta=2&"C)
PARAMETER
Output Transition Time
Propag~on
Delay Time
(A,B-Y)
P.!.opagatlon Delay Time
(G-Y)
SYMBOL
TEST CONDITION
MIN.
t1l.H
t.n..n .
tpUi
toHL
tpUi
toHL
MAX.
TYP.
-
4
12
15
25
-
14
23
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =60pF,lnput t r =t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Vee
MIN.
'l'a-25"C
Ta= 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
Output Transition Time
t1l.H
tTHL
4.5
5.5
-
8
7
15
14
-
Propag~ion
Delay Time
(A, B-Y)
tpLH
tpHL
4.5
5.5
-
19
16
30
27
-
P.r.opagation Delay Time
(G-Y)
tpLH
tpHL
4.5
5.5
-
17
14
27
25
-
-
-
19
17
38
35
ns
34
31
Input Capacitance
10
5
10
CIN
Power Dissipation Capacitance Cpo(l)
- pF
40
Noten) Cro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iccq,o=Cro "V0::" fIN +10:: 12(per Decoder)
-
HC-285
-
NOTES
TC74HC147AP/AF
10-TO-4 LINE PRIORITY ENCODER
The TC74HC147 A is a high speed CMOS LINE ENCODER
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HC147A is lO-to-4 line priority encoder.
All data inputs and outputs o(HC147A are active when
low.
The HC14 7A detects a low on the highest order among nine input
signals and outputs the corresponding signal position in BCD. The
implied decimal zero condition requires no input condition, as zero is
encoded when all nine data lines are high.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. t pd=15ns(Typ.)at V rx =5V
• Low Power Dissipation ............ ICl:=4IlA(M~x.)at Ta=25"C
• High Noise Immunity"""'"'''''' Vr':IH =V"IL 28%· Vrx(Min.)
• Output Drive Capability"""""" 10 LSTTL Loads
• Symmetrical Output Impedance ... I Iou I=1OL. =4mA(Min.)
• Ba1anced Propagation Delays ...... tptH" tpHt
,. Wide Operating Voltage Range'" Vrx (opr)=2V-6V
• Pin and Function Compatible with 74LS147.
16~
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
4
6
15
NC
14
0
4
13
3
8
5
12
2
C
6
11
GND
NC:NO
HPRJ/BCD
4
5
6
4
8
HC-287
Vee
3
B
IEC LOGIC SYMBOL
16
10
8
(TOP VIEW)
CONNECTION
9
A
TC74HC147AP/AF - - - - - - - - - - - - - - - -
TRUTH
TABLE
OUTPUTS
INPUTS
LOGIC
.-
1
H
2
H
3
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
H
5
H
6
7
H
H
X
X
X
X
X
X
X
X
X
X
L
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
8
H
L
H
DIAGRAM
3
HC-288
9
H
L
H
H
H
H
H
H
H
H
0
H
L
L
H
H
H
H
H
H
H
C
B
A
H
H
H
H
H
H
H
L
L
L
L
L
H
L
L
H
H
L
H
H
L
L
H
H
L
H
H
L
H
L
X:Don't Care
----------------TC74HC147AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI:\
VOLT
11K
10K
IOLT
lee
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)'/180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
rnW
"C
"C
*500m W in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
unti1300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI:\
VOLT
Topr
tr • tr
VALUE
2-6
0- Vee
0- Vee
-40 - 85
0- 1000(Vee.=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIIi
Low-Level
Input Voltage
VII_
High-Level
Output Voltage
Va-I
Low-Level
Output Voltage
VOL
InpUt Leakage Current
I Quiescent SlIJlIlh' Current
I 1:\
IlL
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
Ia-J =-20 IL A 4.5
VI:\=
6.0
VIHorVIL
100 --4 rnA 4.5
100 =-5.2mA 6.0
2.0
Ia.. =20 ILA 4.5
VI:\=
6.0
VIHorVIL
Ia.. -4 rnA 4.5
Ia.. =5.2mA 6.0
VI:\ -Vee or GND
6.0
VL\ -Vee or GND
60
HC-289
MIN,
1.5
3. 15
4.2
1.9
4.4
5.9
4.18
5.68
-
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
4.5
4.4
V
6.0
5.9
4.31
4.13
5.80
5.63
0.1
0.0
0.1
0.1
0.0
0.1
V
0.0
0.1
0.1
0.17
0.26
0.33
0; 18
0.33
0.26
+0 1
+1.0
ILA
40
40 0
TC74HC147AP/AF----------------------------------
AC ELECTRICAL CHARACTERISTlCS(C L =15pF,Vcc=5V,Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
t·rI.H
tTIiL
-
4
8
tpL~1
-
15
25
Propagation Delay Time
TEST CONDITION
toHI.
MIN.
TYP.
MAX.
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =tf=6ns)
Ta-25"C
Ta--40 -85"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
TYP. MAX. MIN. MAX.
Vee MIN.
2.0
30
75
95
tTLH
Output Transition Time
4.5
8
15
19
tn-IL
6.0
7
16
13
ns
2.0
60
190
150
tpl.H
Propagation Delay Time
4.5
18
30
38
tpHL
6.0
26
15
33
Input Capacitance
CI;\
5
10
10
pF
Power Dissipation Capacitance CPD(I)
24
Note (1) C H:l is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icctpp =C PO • Va;. f l:-; +Ia;
HC-290
TC7 4HC148AP I AF I AFN
8-TO-3 LINE PRIORITY ENCODER
The TC74HC148A is a high speed CMOS 8-00-3 LINE
ENCODER fabricated with silicon gate C' MOS technology.
It achieves the high spee~ operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
All data inputs and outputs of these encoders are active
when low.
The encoder detects a low on the highest order among eight input
signals and outputs the corresponding signal position in binary code.
Enable Input EI and Enable Output EO are used to easily
cascade without using external circuits.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd=15ns(Typ.)at Vcc=5V
• Low Power Dissipation ............ Icc=4/l A(Max.)at Ta=25"C
• High Noise Immunity ........ · .. •.. · \Nm=VNIL=28" Vcc(Min.}
• Output Drive Capability ........ · .. · 10 LSTTL Loads
• Symmetrical Output Impedance ... , IOIII=Iol.=4mA(Min.)
• Balanced Propagation Delays ...... tpl.,,'" tplll.
• Wide Operating Voltage Range'" Vcc(opr)=2V-6V
• Pin and Function Compatible with 74LS 148
1
P(DIP16-P-300A)
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
16 Vee
4
5
2
15
EO
6
3
14
GS
7
4
13
3
EI
5
12
2
A2
6
11
A1
7
GND 8
(TOP VIEW)
IEC LOGIC SYMBOL
0
1
2
3
4
6
6
7
HPRI/BIN
10 >1
11
12
13
14
15
16
17
18
(15) EO
(14) GS
AO
Al
A2
EI
HC-291
10
0
9
AO
TC74HC148AP/AF/AFN _ _ _ _ _ _ _ _ _ _ _ _ _!!!!!!!!!!!I!!I""""
TRUTH TABLE
OUTPUTS
AD
GS
INPUTS
EI
0
1
2
3
4
5
6
7
A2
A1
H
X
H
X
X
X
X
X
X
X
L
X
H
X
X
X
X
X
X
L
H
X
H
X
X
X
X
X
X
H
X
X
X
X
L
H
H
H
X
H
X
X
X
X
H
X
X
L
H
H
H
H
H
X
H
X
L
H
H
H
H
H
H
X
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
I
H
H
L
L
L
L
L
L
L
L
H
H
H
L
L
L
H
L
H
H
H
H
L
EO
X:Don't Care
H
L
H
H
H
H
H
H
H
H
LOGIC DIAGRAM
EI
o
10
2
11
12
3
13
HC-292
4
6
2
6
7
--------------TC74HC148AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI:,\
VOLT
11K
10K
IOLT
Icc
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 --Vcx;+0.5
±20
±20
±25
±50
500(DIP) '/180(SOIC)
-65 -150
300
UNIT
Y.
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta =65"C
to 85"C a derating factor of
-lOmWI"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o- 1000(Vee =2.0V)
0- 500(Vcx;=4.5V)
o - 400(Vee =6.0V)
SYMBOL
Vee
VI:,\
VOLT
Topr
tr , tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Va-l
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
111\
lee
TEST CONDITION
VI~=
VIHorVIL
VI:'; =
VIHorVIL
V 1:,\
V 1:,\
100
=-20u A
100
100
--4 rnA
=-5. 2mA
IOL =20 u A
lex. -4 rnA
IOL =5.2mA
-Vee or GND
-Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-293
Ta- 40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.4
4.5
V
5.9
6.0
5.9
4.31
4.13
4.18
5.63
5.68
5.80
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.1
0.0
0.26
0.33
0.17
0.26
0.33
0.18
±0.1
±1.0
UA
40.0
4.0
MIN.
1.5
3. 15
4.2
TC74HC148AP/AF/AFN·--------------
AC ELECTRICAL CHARACTERISTlCS(C L =15pF,Vcc=5V,Ta=25"C)
PARAMETER
Output Transition Time
Propagation Delay Time
(IN-AO,Al,A2)
Propagation Delay Time
(IN-EO,ES)
Propagation Delay Time
(EI-EO)
Propagation Delay Time
(EI-GS)
Propagation Delay Time
(EI - AO,Al,A2)
SYMBOL
MIN.
TEST CONDITION
t11.11
tTHL
tpUl
tpliL
tpl.II
tol-ll.
tpLH
tol-lL
tpl.H
tpHL
tplJl
MAX.
TYP.
-
4
8
-
IS
25
-
15
25
-
11
19
-
11
19
-
11
19
UNIT
ns
tllHl
AC E LECTRICA L CH ARACTER ISTICS(CL=60pF ,Input tr=tf =6ns)
PARAMETER
SYMBOL TEST CONDITION
Output Transition Time
t11.H
tTHL
Propagation Delay Time
(IN - AO,Al,A2)
tpLH
tpHL
Propagation Delay Time
(IN-EO,GS)
tpLH
tpHL
Propagation Delay Time
(EI-EO)
tpLH
tpHL
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
! Ta=-40 -85"C
Ta=25"C
,-
MIN.
-
-
-
-
TYP.
30
8
7
52
19
15
52
19
I
15
! 40
14
11
I
!
MAX. MIN.
75
15
13
I
ISO
30
26
ISO i
30 iI
26 I -
i
I
I
115
;
23
20
115
23
20
115
23
20
!
I
j
-
-
MAX.
95
19
16
190
38
33
190
38
33
145
29
25
145
29
25
145
29
25
10
UNIT
ns
I
40
Propagation Delay Time
!
tPLH
14
(EI-GS)
tpHL
!
, 12
II
40
I
Propagation Delay Time
tpl.li
I
, 14
(EI - AO,Al,A2)
: tpHL
12
Input Capacitance
CI:,
10 , 5
pF
- I
Power Dissipation Capacitance
CpD
55
Note (1) Cm is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCilJij=Cm ,Voc·fL,+IOC
HC-294
-
- - - - - - - - - - - - - - - TC74HC148AP/AF/AFN
TYPICAL APPLICATION
4-bit CASCADE CONNECTION
15
14
13 12
11
10
9
8
76543210
EO
EI
k ) - -.......- - Q
El
GS
EO
GS
A2
Al
AO
EO="L"
With IN="W
TC74HC08A
Priority
Flag
A3
HC-295
A2
Al
AO
TC74HC151AP IAF/AFN----8-CHANNEL MULTIPLEXER
The TC74HC151A is a high speed CMOS 8-CHANNEL
MULTIPLEXER fabricated with silicon gate C 2 MaS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
One of eight date input signals (DO-D7) is selected by
decoding of the three-bit address input (A. B. C). The
selected data appears on two outputs: non-inverting (Y)
and inverting (W).
The strobe input provides two output conditions; a low
level on the strobe input transfers the selected data to the
outputs. A high level on the strobe input sets the Y output
low and the W output high without regard to the data or
select input conditions.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd =15ns(typ. )at Vee=5V
• Low Power Dissipation ............ Iee=4IlA(Max.)at Ta=25"C
• High Noise Immunity··············· VN1H =V!':II.28% Vee (Min.)
• Output< Drive Capability'" ......... 10 LSTTL Loads
• Symmetrical Output Impedance ... I IOH I =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpl-lL
• Wide Operating Voltage Range ... Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS151
1
P(0IP16-P-300A)
,.~,.~
F(SOP16-P-300)
FN(S0L16-P-150)
PIN ASSIGNMENT
03
16 Vee
02 2
15 04
01 3
1405
DO 4
1306
Y 6
1207
W 6
llA
ST 7
10 B
GNO 8
9 C
(TOP VIEW)
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS
SELECT
C
X
L
L
L
L
H
H
H
H
B
X
L
L
H
H
L
L
H
H
OUTPUTS
STROBE
A
X
L
H
L
H
L
H
L
H
ST
H
L
L
L
L
L
L
L
L
y
W
L
H
DO
DO
01
02
03
04
05
06
07
01
02
03
04
05
06
07
X : Don't care
HC-296
MUX
EN
:}G~
o
1
y
2
W
3
4
6
6
7
- - - - - - - - - - - - - - TC74HC151AP/AF/AFN
SYSTEM DIAGRAM
5T
7
W
Y
DO
4
50
01
3
51
02
2
15
53
14
13
12
57
B
C
55
56
56
A
54
55
55
07
53
54
54
06
52
53
03
05
Sf
51
52
52
04
50
50
56
57
57
11
10
9
HC-297
TC74HC151AP/AF/AFN--------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
Vee
VI\
VOLT
11K
10K
IOLT
lee
PD
Tstg
TI.
I
UNIT
V
V
V
I
rnA
I rnA--
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 - Vec+0.5
±20
±20
±25
±50
500(DIP) '1I80(MFP)
-65 -150
300
SYMBOL
I
*500m VI' in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmWI"C shall be applied
until300mW.
!
rnA
rnA
mW
I
OC
°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
!SYMBOL
Vee
VI:\
0- Vee
0- Vee
-40 - 85
o - 1000(Vec=2.0V)
0- 500(Vcc =4.5\')
o - 400(Vee =6.0V)
VOLT
Topr
tr
UKIT
V
V
V
2-6
i
, tc
I
OC
ns
I
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
Ta-25OC
1 Ta- 40 -85OC UNIT
Vee MIN. i TYP. I MAX. : MIN. I MAX.
2.0
1. 5
V
4.5
3.15
!
i 4.2 I
6.0, 4.2
TEST CONDITION
High-Level
Input Voltage
2. 0
Low-Level
Input Voltage
High-Level
Output Voltage
= i
=
Vn.
I
1m =-20 Ii A
\ ' IIlor \7II. I
1011
1(1'1
Input Leakage Current
Quiescent Supply Current I
Va.
11:\
Icc
VI:\ =
1 101.
~: ~
!: ~
i II
I
-
O. 5
!
-
: 0. 5
1. 35
1. 8
i:l
-
!
-
~: ~ I =
!
!: ~ I
°°
--4 rnA I 4.5 1 4.18
=-5.2mAi 6. i 5.68
4.31 I
5.80 I
4.13 i
15.63!
=20 IJ. A
I(~. -~
2.
4{j .. 50
! O. 0
I
Ii
-_
II
0.0
~:~j
I
I
-
O. 1
0.1
i
rnA
I
I
°
I
He-298
V
-
I
0. 1
0.1
-
~:~6! = : ~:;3
,
V
-
,
4.5!
,
i
I IOL =0. ~mA
6. I 1
O. 18
0.2(j
V 1:\ -V cc or G N L,_..;::6,...;;0,...-r-'_-_._ir--_-_+--=;±c-:0;;-:-.o..l,;.__-_
V I:\ -Vee ormm
: 6.0
i
4.0!
VlllorVIL
1. 35
1. 8
I
~. .,.5~.9;-,;.-t--6:;:-.,.;:0-;--+1__
-_t-11....:5:;:-•.::-9;;--t1___--l
.,...4....~-;
I
!
Low-Level
Output Voltage
=
°
"1:\ =
I1'
-
4. 5
6.
~: ~51 =
0.33
V
.....:±7i-'1.~0'-l IJ. A
___+_'
I 40.0
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC151AP/AF/AFN
AC ELECTRICAL CHARACTERISTICS(C L =1SpF.Vcc =SV.Ta=2S·C}
PARAMETER
SYMBOL
Output Transition Time
t·I1 •1I
t111L
tpLiI
tolil.
tplJ I
tolii.
trHI
tH.
tpl.11
tnilL
trHl
tpili.
tpLiI
tpilL
Propagation Delay
(D-Y)
Propagation Delay
(D-W)
Propagation Delay
(ST-Y)
Propagation Delay
(ST-W)
Propagation Delay
(A. B. C-Y)
Propagation Delay
(A. B. C-W)
Time
Time
Time
Time
Time
Time
TEST CONDITION
MI~.
TYP.
-
4
8
-
15
24
15
24
-
10
17
-
10
17
-
19
31
-
19
31
I
I
I
MAX.
UNIT
ns
AC ELECTRICAL CHARACTERISTlCS(C L =SOpF.lnput t r =tf=6ns}
Ta-25°C
Ta--40 -85"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vee MIN. I TYP. MAX. MIN. MAX.
2.0
75
95
i 30
tTLII
Output Transition Time
4.5
8
15
19
i
tTI1L
,I
6.0
i
13
16
2.0
,I 65
140
175
Propagation Delay Time
tpLiI
I
4.5
28
18
35
i
(D-Y)
tpilL
6.0
i 15
24
30
140
2.0
65
175
Propagation Delay Time I tpLil
! 18
I
28
4.5
35
(D-W)
t pl1l.
I
6.0
24
15
30
2.0
100
36
125
Propagation Delay Time
tpl.H
ns
12
4.5
20
25
(ST-Y)
I tpilL
17
6.0
10
21
2.0
36
100
125
Propagation Delay Time
tr~."
20
4.5
12
25
(ST-W)
tpilL
17
6.0
10
21
2.0
80
180
225
Propagation Delay Time
tpUI
36
4.5
45
(A.B.C-Y)
,, 23
tr~IL
I
6.0
19
31
38
!
! 80
2.0
180
225
Propagation Delay Time
tpU!
I
23
36
4.5
45
(A. B. C-W)
t"HI.
! 19
.38
6.0
31
Input Capacitance
CI'\
5
10
10
i
pF
Power Dissipation Capacitance CI'/)(!) i
- I 69
Note (I) C Jl) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
A"erage operating currl'nt can be obtained by the equation:
icc",r=C 1'1)' "CC' f 1,\ ~i CC
I
:
I
I
I
I
I
I
I
I
HC-299
TC74HC153AP/AF/AFN
TC74HC253AP/AF/AFN
TC74Hc.153AP/AF/AFN DUAL 4-CHANNEL MULTIPLEXER
TC74HC253API AF/AFN DUAL 4-CHANNEL MULTIPLEXER WITH 3-STATE OUTPUT
The TC74HC153A and TC74HC253A are high speed
CMOS DUAL 4-CHANNEL MULTIPLEXERs fabricated
with silicon gate C2M08 technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HCl53A has standard outputs, while the
TC74HC253A has 3-state outputs.
Input data (lCO-lC3,2CO-2C3) are selected by the two
address inputs, A and B.
Separate strobe inputs (l0, 20) are provided for each of
the two four-line sections. They can be used to inhibit the
data outputs. The output of the HC153A is set low, and the
HC253A output is set to the high impedance state, when
the strobe inputs are low.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP16-P-300A)
F(SOP16-P-300)
FEATURES:
• High Speed .............................. tpd=12ns(Typ.)at Vee=5V
• Low Power Dissipation ............ lee=4#A(Max.)at Ta=25"C
• High Noise Immunity ........ · ...... V"IH=VNlL28% Vee (Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance'" I 100i I =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
·0 Wide Operating Voltage Range'" Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS153,74LS253
FN(S0116-P-150)
16 Vee
15 2G
14 A
13 2C3
lG 1
B 2
lC3 3
lC2 4
lCl 5
12 2C2
11 2Cl
lCO 6
lV7
10 2CO
GND 8
9
(TOP
IEC LOGIC SYMBOL
TC74HC253A
TC74HC153A
A
B
A
B
1G
10
1CO
1C1
1C2
1C3
1CO
1C1
1C2
1C3
20
20
2CO
2C1
2C2
2C3
2CO
2C1
2C2
2C3
He-300
VIEW)
2Y
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC153AP/AF/AFN
TC74HC253API AF I AF N
SYSTEM DIAGRAM
74HC253A
74HC153A
A 14
B 2
lCO 6
lCO 6
lCl 5
lCl 5
lC2 4
lC2 4
lC3 3
lG 1
2C0 1O
lC3 3
lG 1
2CO 10
2Cl 11
2Cl 11
2C2 12
2C2 12
2C3 13
2G 15
2C3 13
2G 15
2Y
TRUTH TABLE
SELECT
INPUTS
B
A
CO
Cl
X
X
X
L
L
L
L
L
H
X
X
X
L
H
L
H
X
X
X
X
X
X
H
L
H
L
H
H
H
H
STROBE
OUTPUT Y
C3
G
HC153A HC253A
X
X
X
X
X
X
X II
L ,i
H I
H
L
L
L
L
L
H
H
L
L
L
L
H
H
DATA INPUTS
H
C2
X
X
X
X
X
X
X
X
X
H
X
X
L
I
L
!
i
Z
L
L
L
L
H
H
L
L
L
L
H
H
HC-301
X : Don't care
Z : High Impedance
TC74HC153AP/AF/AFN
TC74HC253AP/AF/AFN----------------------------ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Va;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Va;
VIN
VOlJr
11K
10K
IOl;T
Ia;
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5-7
-0.5 -Va; +0.5
-0.5 -Va;+0.5
±20
±20
±25
±50
500(DIP) */180(SOIC)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65·C. From Ta=65"C
to 85"C a derating factor of
-lOmW rc shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
UNIT
V
V
V
"C
VALUE
2-6
0- Va;
0- Va;
-40 - 85
0- 1000(Va;=2.0V)
0- 500(Va;=4.5V)
o -- 400(Va;=6.0V)
SYMBOL
Va;
VIN
VOl;T
Topr
tr • tr
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Va-!
Low-Level
Output Voltage
VOL
3 State Output
Off-State Current
ICE
Input Leakage Current
Quiescent Supply Current
II:';
la;
TEST CONDITION
VI:-<=
VIHorVII•
VIN =
VIHorVIL
*
IOH =-20J,tA
IOH --4 rnA
IOH =-5. 2mA
IOL =20 J,tA
IOL -4 rnA
101. =5.2mA
VI:'; -VIH or V IL
VOLT =Va; or GND
VI:'; -'Va; or GND
VI:" -Va; or GND
* TC74HC253A
Ta-25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1.35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
6.0
5.9
5. 9
4.31
4.13
4. 18
5.68
5.80
5.63
0.0
0.1
0.1
0.0
0.1
0.1
V
0.0
0.1
0.1
0.17
0.26
0.33
0.18
0.26
0.33
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
MIN.
1.5
3. 15
4.2
6.0
-
6.0
6.0
only
HC-302
-
-
±0.5
-
±O.l
4.0
-
±S.O
±1.0
40.0
J,tA
TC74HC153APIAF I AF N
--------------TC74HC253AP/AF IAFN
AC ELECTRICAL CHARACTERISTICS(C L =15pF, Vcc=5V ,Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTHL
t pLH
toHL
tpLH
toHL
tpUi
tol-JL
tJfl.
t oZJ-l
Propagation Delay Time
(Cn-Y)
Propagation Delay Time
.
(A,B-Y)'
Propagation Delay Time
(G-Y)
3-State <2!!tput Enable Time
(G-Y)
*
**
MIN.
TEST CONDITION
TYP.
MAX.
-
4
8
-
12
19
-
17
26
-
8
16
-
9
16
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =tf=6ns)
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
30
i5
95
2.0
tTLH
Output Transition Time
8
15
19
4.5
tTHL
6.0
7
13
16
115
145
48
2.0
Propagation Delay Time
tpLH
23
29
4.5
15
tpH[.
(Cn-Y)
6.0
20
12
25
150
190
68
2.0
Propagation Delay Time
tpLH
4.5
20
30
38
(A,B-Y)
tpH[.
6.0
16
26
33
ns
120
31
95
2.0
Propagation Delay Time
tpLH
19
24
4.5
11
(G-Y)
tpHL
6.0
9
20
16
36
100
125
2.0
3-State Output Enable Time tJfl.
12
20
25
4.5
(G-Y)
t!0i
6.0
9
Ii
21
22
115
145
2.0
3-State Output Disable Time tplZ
29
23
4.5
13
(G-Y)
tpHZ
6.0
25
11
20
Input Capacitance
C,;>.:
5
10
10
pF
TC74HC153A
58
Power Dissipation Capacitance cpom
TC74HC253A
59
Note (J) C fD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current. consumption without load.
Average operating current can be obtained by the equation:
ICCq,o=C po· Va:. f ,:-;+1 a:
PARAMETER
SYMBOL TEST CONDITION
Vcc
*
**
**
*
**
for TC74HC153A only
for TC74HC253A only
He-3D3
MIN.
TC74HC154AP - - - - - - - - - - - - 4 -TO- 1 6
LINE
DECODER
The TC74HC154A is a high speed CMOS 4 to 16 LINE
DECODER/DEMULTIPLEXER fabricated with silicon
gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
A binary code applied to the four inputs A thru D is
decoded within the device. Depending on the binary code,
one of sixteen outputs goes low, when both the
strobe inputs, (}1 and (}2, are held low. When either
strobe input is held high, the decoding function is
inhibited to keep all outputs high. The strobe function
makes it easy to expand the decoding lines through
cascading, and simplifies the design of address decoding
circuits in a memory control system.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
24
P(DIP24-P-300)
PIN ASSIGNMENT
YO
Y1
V2
V3
Y4
Y5
V6
V7
V8
V9
V10
GND
FEATURES:
• High Speed .............................. tpd =15ns(typ. )at Vee=5V
• Low Power Dissipation ............ Iee =4.uA(Max.)at Ta=25°C
• High Noise Immunity··············· V:\IH =V:\ IL 28% Vee (Min.)
• Output Drive Capability······ ...... 10 LSTTL Loads
• Symmetrical Output Impedance ... I IOH I =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH "" tpflL
• Wide Operating Voltage Range ... Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS154
24 Vee
23 A
2
3
22B
21 C
20 0
19 <32
1801
17 V16
16 V14
15 V13
14 V19
13 Y11
4
5
6
7
8
9
10
11
12
(TOP VIEW)
IEC LOGIC SYMBOL
X/Y
DMUX
~ 1m °3) G~
A (23)
B (22)
C (21)
o (20)
o
HC-304
(20)
------------------------------------TC74HC154AP
TRUTH TABLE
I
INPUT
SELECTED
~G=I-,~G~2-,--D---rl--C-,--B--~-A~_~1__0_U_T_P_U_T_(L_)~
X:Don't care
~ I~ ~
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
I
L
L
H
I
L
L
H
L
L
H
L
H
L
L
L
HI
L
H
H
L
L
H I
H
L
L
L
L
H
H
L
L
H
X
~ I
X
X
H
Lll-~-~-+-.1I
I
i
i
I
I
H
H
L
L
H
H
L
L
L
L
Y4
L
H
I
'1'6
H
L
I
H
H!
Y6
Y7
I
Y8
Y9
YIO
YII
L
H
YI2
YI3
YI4
YI5
H
H
H
X
X
YO
YI
Y2
Y3
x
X
X
X
I
I
NONE
NONE
SYSTEM DIAGRAM
Yo
YI
Y2
Y3
Y4
A
Y6
Y6
B
Y7
YB
Y9
C
Y 10
YII
D
Y 12
Y 13
Y 14
Y 15
HC-305
TC74HC154AP---------------------------------ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vc-c/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
\'ee
VI:\
VOLT
11K
10K
IOLT
Icc
PI)
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vcc+0.5
-0.5 -Vcc+0.5
±20
±20
±25
±50
500*
-65 -150
300
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-lOmWrC shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
DC
ELECTRICAL
PARAMETER
SYMBOL
Vill
Low-Level
Input Voltage
VIL
Low-Level
Output Voltage
Input Leakage Current
Quiescent Supply Current
UNIT
V
V
V
"C
0-1000(Vee =2.0V)
0- 500(Vec=4.5V)
0- 400(Vcc=6.0V)
ns
Vee
VI:\
VOLT
Topr
tr ,tr
CHARACTERISTICS
High-Level
Input Voltage
High-Level
Output Voltage
VALUE
2-6
0- Vc-c
0- Vee
-40 - 85
SYMBOL
TEST CONDITION
VI:\=
VI:\=
11:\
Icc
~nx.
1.5
3. 15
4.2
lul =-4 rnA
1(lJ=-5.2mA
4.5
6.0
4.l8
5.68
l(x.=20,uA
2.0
4.5
6.0
-
IOL=4 mA
h=5.2mA
4.5
6.0
6.0
6.0
Im=-20,uA
Va.
VIII or VII.
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Val
VIII or VIL
-
VI:\ =\'cc or GXD
\'1:\ =\'cc 01' GXD
HC-306
-
-
1.9
4.4
5.9
-
Ta=-40-85"C
Ta=25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1.35
1.8
1.8
2.0
1.9
4.5
4.4
5.9
6.0
V
4.31
4. 13
5.63
5.80
0.0
0.0
0.0
0.1
O. I
0.1
-
-
0.17
O. 18
0.26
0.26
-
-
±O.l
4.0
-
-
-
0.1
O. I
O. 1
V
0.33
0;33
±1.0
40.0
,uA
-----------------------------------TC74HC154AP
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25°C}
PARAMETER
Output Transition Time
Propagation Delay Time
(A. B. C, D- Y)
Propagation Delay Time
(Gl, G2-Y)
TEST CONDITION
SYMBOL
I
t TUI
t·llli.
tpl..ll
tjJ/jl.
tplJl
tDIlL
I
MIN.
TYP.
MAX.
-
4
8
-
15
-
14
!
30
U~IT
,
ns
28
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =t,=6ns}
Ta--40 -85"C
Ta-25"C
U~IT
TYP. MAX. MIN. MAX.
.2.0
i5
95
30
tTl.li
Output Transition Time
4.5
8
19
15
tTI·11.
6.0
7
13
16
2.0
220
65
175
Propagation Delay Time
tpl.H
4.5
ns
19
35
44
(A,B,C,D-Y)
tpHI.
6.0
37
16
30
2.0 ! -200
55
160
Propagation Delay Time
tpl.H
17
32
40
4.51
(Gl. G2-Y)
tpHL
6.0
15
27
34
Input Capacitance
CI:"
5
10
10
pF
Power Dissipation Capacitance
Cpo(l)
57
Note (t) C It> is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lee q,o=C PI)' Va:.' f ['\ +1 a:.
PARAMETER
SYMBOL' TEST
CO~DlTIO~
Vee
He-3~?
MIN.
TC7 4HC155 AP IAFI AF N
DUAL 2-TO-4 LINE DECODER/DUAL 3-TO-8 LINE DECODER
,------------------------,
The TC74HC155A is a high speed CMOS DUAL 2-to-4
LINE DECODER fabricated with silicon gate C 2MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
It features dual I-to-4 line demultiplexers with individual
strobe inputs,(IG and 2G),individual data inputs(IC and
2C)and common binary address inputs(A and B).
When both decoders are enabled by the strobes,the inverted
output of lC data and non-inverted output of 2C data will
be brought to the selected output pins of each section.
A I-to-8 line demultiplexer can be easily built up by
providing a data signal to both the lC and 2C inputs;the
output order will be lY3(MSB),IY2,IYl,IYO,2Y3,2Y2,2Y
l,2YO(LSB).
This device can be used as a 2-to-4 line decoder or a 3-to
-8 line decoder when lC is held high and 2C is held low.
~ll inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP16-P-300A)
F(SOP16-P-300)
FN(S0L16-P-150)
PIN ASSIGNMENT
FEATURES:
• High Speed ................................. tp:l =12ns(Typ.)at Vcc=5\'
• Low Power Dissipation ............... Iee=4J.tA(~lax.)at Ta=25'C
• High Noise Immunity·················· V\lH=V\lL =2896 Vee (:\iin.)
• Output Drive Capability'" ............ 10 LSTTL Loads
• Symmetrical Output Impedance ...... 11 011 1=1 01 • =4mA(Min.)
• Balanced Propaation Delays ......... tpi.1i "'tpliL
~,
• Wide Operating Voltage Range ...... Vee (opr)=2V -6V
• Pin and Function Compatible with 74LS155
1C
1G
2
B
1Y3
16
Vee
15
ic
14
20
13 A
1Y2
5
12
2Y3
1Y1
6
11
2Y2
1YO
10 2Y1
ivo
(TOP VIEW)
TRUTH TABLE
INPUTS
OUTPUTS
OUTPUTS
INPUTS
B
A
iG
lC
lYO
lYl
lY2
lY3
B
A
2G
2C
2Y~
2V1
iV3
2Y3
X
X
H
X
H
H
H
H
X
X
H
X
H
H
H
H
L
L
H
H
H
L
H
H
H
L
H
H
L
H
L
H
L
L
L
L
L
H
H
L
L
H
L
L
H
L
H
H
H
L
L
H
H
H
L
H
H
L
L
L
H
H
L
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
X
X
X
L
H
H
X
L
H
H
X
L
X
H
H
H
H
X
X
DON'T CARE
He-30B
DON'T CARE
- - - - - - - - - - - - - - T C 7 4 H C 1 5 5 AP/AF/AFN
IEC LOGIC SYMBOL
A
B
IG
Ie
IYO
IVI
IV2
IV3
2VO
2YI
2Y2
2Y3
2G
2<:
SYSTEM DIAGRAM
7
lG
1'10
6
lC
1'(1
5
1'12
B
3
4
9
A
2'11
16
11
iG
2'(0
13
10
2C
1'(3
2'(2
14
12
He-30g
2'(3
TC74HC155AP/AF/AFN - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI:\
VOLT
11K
10K
IOLT
Icc
~)
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vcc+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
UNIT
V
V
!
V
rnA
rnA
rnA
rnA
*500mW in the range of Ta=
-40·C- 65·C. From Ta=65"C
to 85·C a derating factor of
-10m W
shall be applied
until300mW.
rc
mW
"C
"C
RECOMMENDED OPERATING CONDITIONS
• PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI:\
VOLT
Topr
Itr ,
tr
I
VALUE
2-6
o -Vee
0- Vee
-40 - 85
0- JOOO(Vcc=2.0V)
0- 500(\ce=4.5V )
0- 400(Vee=6.0V)
I
I
UNIT
V
l
V
V
I
"C
I
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
ISYMBOL
High-Level
Input Voltage
VIIi
Low-Level
Input Voltage
VII.
High-Level
Output Voltage
I
Vm
I
Low-Level
Output Voltage
VOl.
Input Leakage Current
Quiescent Supply Current
11:\
Icc
TEST CONDITION
2.0
4.5
6.0
2.0
4.5
I 6.0
2.0
lal =-20J.l.A 4.5
VI:\=
6.0
VII_lorVIl .
I(ll --4 rnA 4.5
1m =-5.2mA 6.0
2.0
/1. A 4.5
lex.
=20
VI:\=
6.0
VlllorVIl .
i(x. -4 mAl 4.5
la. =5.2rnA 6.0
6.0
V 1:\ -Vee or GND
6.0
VI:\ -Vee or GND
HC-310
Ta-25"C
I Ta--40 -85"C UNIT
TYP. I MAX. ! l\llN. i M~
- I 1.5
V
3. 15 i 4.2 : 0.5
i 0.5
- I 1. 35 V
1. 35
- i 1.8
1.8
2.0 I 1.9 i 1.9
4.4
4.5
4.4 I V
5.9
6.0
5.9
4.13
4.18
4.31
5.80
5.63
5.68
0.0
O. I
O. I
O. 1
0.0 I 0.1
V
0.1
0.0 i 0.1
0.33
O. Ii ! 0.26
0.33
0.18 I 0.26
i ~O.l
±1.0
J.l.A
I
,, 4.0
40.0
MIN.
1.5
3.15
4.2
! Vee
I
I
I
I
I
I
I
I
I
I
I
I
--------------TC74HC155AP/AF/AFN
AC ELECTRICAL CHARACTERISTlCS(C L =15pF, Vcc=5V, Ta=25°C. Input t r =tf=6ns)
MIN.
TYP.
MAX.
Output Transition Time
I tTLII
I tTIlL
-
4
8
P ropagatlOn
. De Iay T'ime
II
-
12
22
PARAMETER
!SYMBOL
TEST CONDITION
UNIT
ns
tt pL11
pilL
AC ELECTRICAL CHARACTERISTlCS(CL =50pF,lnput t r =tf=6ns)
Ta- 40 -85OC
Ta-25°C
PARAMETER
SYMBOL TEST CONDITION I Vee MIN. TYP. MAX. l\HN. MAX. UNIT
30
75
95
!I
I 2.0
Output Transition Time I tTLlI
4.5
15
19
I 8
I tTl II. I
i 6.0
I 7
13
16
ns
45
130
165
! 2.0
I
tpLlI
Propagation Delay Time
33
i 4.5
15 I 26
tr~ II.
22
28
6.0 , 13 i
Input Capacitance
10
10
I
5
C I\
pF
Power Dissipation Capacitance I CI'D(\)
(Note 1)
53 I
Noten) C m is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating curren! can be obtained by the equation:
icc(llrl =C I'D • VCt:· f" +icc
I
i
I
HC-311
TC74HC157 API AFI AFN
TC74HC158AP/ AFt AFN
TC74HC157API AFI AFN QUAD 2-CHANNEL
TC74HC158APIAF/AFN QUAD 2-CHANNEL
MUL TIPLEXER
MUL TIPLEXER(INVERTlNG)
The TC74HC157 A and TC74HC158A are high speed
CMOS 2-CHANNEL MULTIPLEXERs fabricated with
silicon gate C~OS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low
power dissipation.
The TC74HC158A is an inverting multiplexer while
the TC74HC157A is a non-inverting.
When STROBE is held high, selection of data is
inhibited and all the outputs become low in the
case of HC157A or high in the case of HC158A.
The SELECT decoding determines whether the A or
B inputs get transferred to their corresponding Y
(Y') outputs.
All inputs are equipped with protection circuits
against static discharge or transient excess voltage.
1
P( 01 P16-P-300A)
I.yl.~
F(SOP16-P-300)
FN(SOL 16-P-150)
TRUTH TABLE
INPUTS
FEATURES:
• High Speed ................................. tpd=10ns(typ.)at Vcc=5V
• Low Power Dissipation ............... Icc =4IlA(Max.)at Ta=2SOC
• High Noise Immunity··············· V:"IH=V N1L=28% Vcc (Min.)
• Output Drive Capability··· ......... 10 LSTTL Loads
• Symmetrical Output Impedance ···1 Ia; 1=101.. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH"'tpHL
• Wide Operating Voltage Range ... Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LS157/158
OUTPUTS
ST
SELECT
A
B
H
X
X
X
L
H
L
L
L
X
L
H
L
L
H
X
H
L
L
H
X
L
L
H
H
X
H
H
L
L
Y(157A} Y(158A}
X: Don't Care
PIN ASSIGNMENT
TC74HC167A
SELECT1
TC74HC168A
SELECT1
16 Vee
16 Vee
ST
1A
2
15
ST
1A
2
15
18
3
14
4A
18
3
14
4A
1Y
4
13
48
1Y
4
13
48
2A
5
12
4Y
2A
5
12
4Y
28
6
11
3A
28
6
11
3A
2Y
7
10
38
2Y
7
10
38
GNO
8
9
3Y
GNO
8
9
3Y
(TOP VIEW)
(TOP VIEW)
HC-312
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC157 AP/AF/AFN
TC74HC158API AFI AFN
IEC LOGIC SYMBOL
TC74HC158A
TC74HC157A
IT
SELECT
SELECT
lA
18
2A
28
3A
38
4A
48
MUX
(4)
(7)
(9)
12
lY
2Y
3Y
4Y
HC-313
lA
18
2A
28
3A
38
4A
48
1'1
2Y
3Y
TC74HC157 AP/AF/AFN
TCi4HC1S8API AF IAFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
Vee
VI:>:
V()l;T
11K
10K
IOLT
lee
PI)
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
DC
*500m W in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85"C a derating factor of
-lOmW/'C shall be applied
untiI300mW.
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI:>:
VOl,T
Topr
tr • tc
VALUE
2-6
0- Vee
o-Vee
-40 - 85
o- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o- 400(Vee=6.0V )
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOl I
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescenl Supply Current
I I:>:
lee
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
IOH =-20/.1. A 4.5
VI:>: =
6.0
VIHorVIL
IOH --4 rnA 4.5
IOH =-5.2mA 6.0
2.0
lOt.. =20 /.1. A 4.5
VI:>: =
6.0
VIUorVIL
101 • -4 rnA 4.5
lOt.. =5.2mA 6.0
6.0
VI:>: -Vee or GND
6.0
VI:>: -Vee or GND
HC-314
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.18
4.31
4.13
5.68
5.80
5.63
0.0
O. I
O. I
O. I
0.0
O. I
V
0.0
0.1
0.1
0.26
0.33
0.17
0.26
0.33
0.18
±I.O
±O.I
IJ.A
40.0
4.0
MIN.
1.5
3.15
4.2
-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC157AP/AF/AFN
TC74HC158APIAF I AFN
AC ELECTRICAL CHARACTERISTICS(C L =16pF,Vcc=6V,Ta=26"C)
PARAMETER
SYMBOL
Output Transition Time
tTLlI
tTHL
tpUl
tpHI.
tpLH
t11l-11.
tpUI
tpHL
Propagation Delay Time
(A,B-Y)
Propagation Delay Time
(SELECT-Y)
Propagation Delay Time
(STOROBE-Y)
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
10
16
13
21
10
19
-
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =60pF,lnput t r =tf=6ns)
Ta- 40 -851:
Ta=25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vcc MIN. TYP. MAX. MIN. MAX.
2.0
30
75
95
tTLH
Output Transition Time
4.5
8
15
19
tTHL
6.0
7
13
16
2.0
36
100
125
Propagation Delay Time
tpLH
4.5
12
20
25
(A,B-Y)
tpHL
6.0
10
17
21
ns
2.0
125
155
50
Propagation Delay Time
tpLH
4.5
16
25
31
(SELECT-Y)
tpHL
6.0
21
26
14
2.0
36
115
145
Propagation Delay Time
tpLH
4.5
12
23
29
(STOROBE-Y)
tpliL
6.0
10
20
25
Input Capacitance
CI!\:
5
10
10
pF
TC74HC157A
57
Power Dissipation Capacitance CPOOl
TC74HC158A
53
Note (1) C ro IS defmed as the value of the mternal eqUivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
1cctpO=Cro • Vo:: ofl'\ +10:: 14(per bit)
HC-315
TC74HCT157AP/AF
TC74HCT158API AF
TC74HCT157API AF
TC74HCT158API AF
QUAD 2-CHANNEL
QUAD 2-CHANNEL
MULTIPLEXER
MUL TIPLEXER(INVERTING)
The TC74HCT157A and TC74HCT158A are high speed
CMOS 2-CHANNEL MULTIPLEXERs fabricated with
silicon gate CIMOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low
power dissipation.
The TC74HCT158A is an inverting multiplexer while
the TC74HCT157A is non-inverting.
When STROBE is held high, selection of data is
inhibited and all the outputs become. low in the
case of HCT157A or high in the case of HCTI58A.
The SELECT decoding determines whether the A or
B inputs get transferred to their corresponding Y
(Y) outputs.
All inputs are equipped with protection circuits
against static discharge or transient excess voltage.
1.~
1
P(DIPI6-P-300A)
16~
1
F(SOPI6-P-300).
TRUTH TABLE
FEATURES:
• High Speed .............................. tJXI =8ns(Typ.)at Vcc=5V
• Low Power Dissipation ............ Icc =lttA(Max.)at Ta=25"C
• Compatible with TTL outputs ...... VIH=2V(Min,.)
VIL =0.8V (Max.)
• Wide Interfacing ability ......... LSTTL,NMOS.CMOS
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance .. ·1 IOH 1=IOL=4mA(Min.)
• Balanced Propagation Delays ...... tpLH"'tpHL
• Pin and Function Compatible with 74LS157/158
INPUTS
ST SELECT
H
X
B
A
X
X
L
L
L
L
L
H
L
H
X
X
X
L
L
H
X
H
X : Don't Care
PIN ASSIGNMENT
TC74HCT167A
SELEcn
1A
1B
1Y
2A
2B
2Y
GND
TC74HCT168A
18
16
14
13
12
11
10
2
3
4
ST
4A
4B
4Y
3A
38
9 3Y
5
6
7
8
18
16
14
13
12
11
10
SELECT1
Vee
(TOP VIEW)
1A
1B
1V
2A
2B
2V
2
3
4
GND
8
ST
4A
4B
4V
3A
38
9 3V
5
6
7
(TOP VIEW)
HC-316
Vee
OUTPUTS
Y(I57A) IY(ISlA)
L
H
L
H
L
H
H
L
H
L
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HCT157AP/AF
TC74HCT158AP/AF
IEC LOGIC SYMBOL
TC74HCT158A
TC74HCT157A
Sf
SELECT
1A
1B
2A
2B
3A
3B
.A
.B
1T
1V
2V
3V
.V
HC-317
SELECT
1A
1B
2A
2B
3A
3B
.A
.B
lY
2Y
3Y
TC74HCT157AP/AF ______- - - - - - - - - - - - _
TC7 4HCT158APIAF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
VALUE
Vee
VIN
VOLT
Topr
tr • tr
4.5 - 5.5
0- Vee
0- Vee
-40 - 85
0- 500(Vee =4.5V>.
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5
-7
Vee
-0.5 -Vee+0.5
VIN
-0.5 -Vee+0.5
VOLT
±20
11K
±20
10K
±25
loor
±50
lee
PD
500(DIP)*1180(SOIC)
-65 -150
Tstg
300
TL
RECOMMENDED OPERATING CONDITIONS
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
TEST CONDITION
Vee
4.5
MIN.
l
2.0
5 5
4.5
IIl'1i
lee
~Icc
VI~=
VIHorVIL
-
-
-
2.0
-
V
V
-
-
-
0.8
-
0.8
5 5
IOH =-20J,tA
4.5
4.4
4.5
-
4.4
-
IOH =-4 rnA
4.5
4.18
4.31
-
4.13
-
IOL =20 fJ.A
4.5
-
0.0
0.1
-
0.1
IOL =4 rnA
4.5
0.17
0.26
-
0.33
-
+0 1
4.0
-
+1.0
40.0
J,tA
-
2.0
-
2.9
rnA
l
VIN=
VIHorVIL
Ta=-40 -85"C UNIT
Ta-25"C
TYP. MAX. MIN. MAX.
VI:" -Vcr:. orGND
VI:O\ -Vee or GND
PER INPUT: V1:-; =O.5V or 2.4V
OTHER INPL'T:Vcc or GND
HC-318
5.5
5.5
-
5.5
-
-
V
V
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HCT157AP/AF
TC7 4HCT158AP I AF
AC ELECTRICA L CH ARACTERISTICS(C L =15pF, Vcc=5V, Ta=2S·C)
PARAMETER
SYMBOL
Output Transition Time
tn.H
tTHJ
tpLH
tpHL
tpLH
toHL
tpLH
tpHL
tpLH
tpHL
Propagation Delay Time
(A,B-Y,Y)
Propagation Delay Time
(STOROBE-Y,Y)
Propagation Dalay Time
• (SELECT-Y,Y)
Propagation Delay Time
"(SELECT-Y,Y)
MIN.
TEST CONDITION
TYP.
MAX.
-
4
8
19
30
-
19
30
-
21
32
-
23
35
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF ,Input t r =tf=6ns)
Ta- 40 -85"C
Ta-25°C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vee MUi· T~ MAX. MIN. !MAX.
-
Output Transition Time
tTLH
tTHL
4.5
5.5
Propagation Delay Time
(A,B-Y,Y)
tpLH
tpHL
4.5
5.5
-
Propagation Delay Time
(STOROBE-Y,Y)
tpLH
tpHL
4.5
5.5
Propagation Delay Time
(SELECT-Y,Y)
tpLH
tpHL
4.5
5.5
Propagation Delay Time
** (SELECT-Y,Y)
Input Capacitance
tpLH
tpHL
4.5
5.5
Power Dissipation Capacitance
CPD(1)
*
Note (j)
*
**
8
-
19
18
7
15
14
23
20
35
32
-
44
40
-
23
20
35
32
-
44
40
-
25
21
37
-
27
25
40
36
-
-
-
-
34
-
-
-
ns
46
42
50
45
5
10
10
pF
TC74HCT157A
59
TC74HCT158A
56
C ro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
iCC(prl=Cro • Va:.' fN +Ia:. /4(per bit)
TC74HC157A only.
TC74HC157A only.
CIN
-
He-319
TC74HC160AP/AF 'TC74HC161 AP/AF/AFN
TC74HC162APIAF ·TC74HC163AP IAF IAFN - - SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
TC74HC160AP/AF
DECADE. ASYNCHRONOUS CLEAR
TC74HC161AP/AF/AFN BINARY. ASYNCHRONOUS CLEAR
TC74HC162AP/AF
DECADE. SYNCHRONOUS CLEAR
TC74HC163AP/AF/AFN BINARY SYNCHRONOUS CLEAR
The TC74HCI60A, 161A, 162A and 163A are high speed
CMOS SYNCHRONOUS PRESETTABLE COUNTERs
fabricated with silicon gate C 2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The 74HCl60A/162A are BCD decade counters and the
TC74HC161AI163A are 4 bit binary counters.
The CLOCK input is active on the rising edge. Both
LOAD and CLEAR inputs are active on low logic level.
Presetting of all four IC's is synchronous to the rising
edge of CLOCK.
The clear function of the TC74HCl62A/l63A is synchronous to CLOCK, while the TC74HCl60A/161A are cleared
asynchronously.
Two enable inputs (ENP and ENT) and CARRY
OUTPUT are provided to enable easy cascading of
counters, which facilitates easy implementation of n-bit
counters without using external gates.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. f MAx=63MHz(typ.)at Vcc=5V
• Low Power Dissipation ............ Icc =4tlA(Max.)at Ta=25OC
• High Noise Immunity .............. · V"IH =VNIL =28% Vcc(Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance "'1100 I =1 OL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH"'tpHL
• Wide Operating Voltage Range .. · Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LS160-163
1.~
1
P(DIP16-P-300A)
"~16~
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
CLEAR 1
16Vcc
CARRY
15 OUTPUT
CLOCK2
DATA
IN
A3
140A
B4
1308 OUT120c PUTS
C5
06
11 0 0
ENABLE P7
10 ENABLE T
GN08
9 LOAD
(TOP VIEW)
IEC LOGIC SYMBOL
TC74HC161A
TC74HCl60A
TC74HC163A
TC74HC162A
CUi'
_9
LOAO
!CT.,
CARRY
0.
CARRY
Mo.
.6J
41
00
~
4
[8)
XT"S
O.
o.
01 0c
O.
Oc
00
:0.
00
HC-320
01 CARRY
TC74HC160AP/AF 'TC74HC161 AP/AF/AFN
-------------TC74HC162AP/AF·TC74HC163AP/AF/AFN
TRUTH TABLE
TC74HC160Al161A
TC74HC162A1163A
INPUTS
INPUTS
CLR
LD
L
X
H
L
H
H
H
H
H
H
IENP IENT I CK
!
I
Note
I0
OA
X
X
is
I Oe
L I X
.L
i
H I L
X
X IS
A
I
II
__ ~_JS
H I H
H I H
X
LjI
B
C
NO CHANGE
L
X
is
NO CHANGE
NO COUNT
1
H
H
COUNT UP
COUNT
X
X
NO CHANGE
NO COUNT
L
!
H ! H
X I X : X
H
FUNCTION
X I X I X
X I X 'I
CLRI LD
I X --l--~
i
OUTPUTS
X
IS
H
I"""L
X
I
ENP ENTi CK
HIS
X L
Oc
L
L
i
I
0
L
RESET TO "0"
D
PRESET DATA
NO COUNT
..
-
: Don't care
A, B, C, D : Logic Level of Data Inputs
Carry
: CARRY=ENT'QA'Qe'Qc'Qo·"···(TC74HC160A/162A)
CARRY=ENT·QA·Qe· Qc· Qo······(TC74HC161A1163A)
TIMING CHART (TC74HC160A/162A:DECADE COUNTER)
A
OATA
INPUTS
f
DON'T CARE UNTIL LOAD GOES LOW
B
C
~ff$/00W$//fft00W"&
~ffff//$$////~
lO
CLOCK
ENABLE P
ENABLE T
I
I
I
--~!~~~!I'-----------------~--------~
I
I
:
:Ir ------------------~--------,
---+~---I~·
~-------
~'
OUTPUTS
QB
~ ~'-----------.....
I
Qc
~LJI
I
QD
~~
I
I
I
CARRY OUTPUT
I
I
I
I
'-----------------rl------------------I
I
1
I
I
II
I
I
---T:~:--~I~~!~~r-l~--~~~~Ir-----------------I
I
:7
18 9
0
2
3 :
••
0\
l----COUNT
ASYNC SYNC PRESET
CLEAR CLEAR
(160A) (162A)
HC-321
--I.II-----INHIBIT·---
TC74HC160AP/AF'TC74HC161AP/AF/AFN
TC74HC162APiAF·TC74HC163AP/AF/AFN - - - - - - - - - - - - -
TIMING CHART (TC74HC161A/163A: BINARY COUNTER)
~
1
:
I
u
A
DATA
INPUTS
DON'T CARE UNTIL LOAD GOES LOW
B
C
o
CLOCK
ENABLE P
ENABLE T
0 ..
I
Oa
~~
Oc
~~
OUTPUTS
I
~I
CARRY OUTPUT
1
I
I
I
I
!
1
2--.J
I
I
1
I
I
1
I
I
I
...
.
112
I
I!
1
1
I
1
I
I
1
I
1
1
I
1
1
113
1
I•
14
n
15
0
COUNT
ASYNC SYNC PRESET
CLEAR CLEAR
(161A) (163A)
HC-322
1
1
1
1
I
I
I
I
I
1
I
21
1
1
I
INHIBIT
_ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC160AP/AF'TC74HC161AP/AF/AFN
TC74HC162APIAF 'TC74HC163AP/AF/AFN
SYSTEM DIAGRAM
TC7 4HC160AlTC7 4HC 162A
CLEAR~l--~--~----------------~
ENT
~10~
______________.......,
ENP _7--'1...J
LOAD -=9~---k~15 OUT
CARRY
A3
B 4
~~>-';..:;..3aB
o ..,::6-D¢--+-IH-+__-+---,--,
2
CLOCK ':"-_~-cD_----------l
TC74HC160A
'TRUTH TABLE OF INTERNAL F/F
P CKr~rQ LQ
TC74HC162A
. _0 CK R
"aTa
X~ iLl' L i H I X i.J L:I LiH
~ ~ i H i L ! H II L!.J H II ~ I ~
H ,.J ! H I ~11 H I'.J H il liJ L
I
l
X I L! H !iNOCHANGEji l
HC-323
I
L
H i'NOCHANGE
X : Don't Care
TC74HC160AP/AF'TC74HC161AP/AF/AFN _ _ _ _ _ _ _ _ _ _ _ __
TCi4HC162AP/AF 'iC74HC163APIAFiAFN
SYSTEM DIAGRAM
TC74HC161A/TC74HC163A
___1'__~~~________________- ,
CLEAR
10
ENT~~--------------,
ENP-7--t....r
LOAD --=9'---<0-+-(;>0-_
A ..::.3-0<>---1--,
4
1--I------____~
'TRUTH TABLE OF INTERNAL F/F
TC74HC161A
I'
TC74HC163A
DJ2~R-r OJJl II Djc~f!I~9.
X ! X !L I L I H
rs I L !I L I H
Lis! H ,I L ! H II L !J I H!i L I H
H iJ I H !L..!:!-l L J H S' H Ii H i L
Tx
x Il...
H
INOCHANGE I L l...1
HC-324
H
I[NOCHANGE
X : Don't Care
TC74HC160AP/AF 'TC74HC161 AP/AFIAFN
-------------TC74HC162AP/AF·TC74HC163AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Gdrrent
DC Output Current
DC Va:.IGround Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vcr
VI:"
VOLT
11K
10K
IOLT
Ia:.
PD
Tstg
TL
VALUE
-0.5-7
-0.5 -Va:. +0.5
-0.5 -Va:.+0.5
±20
±20
±25
±50
500(DIP) ./180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-IOmW/"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
VALUE
2-6
0- Va:.
0- Va:.
-40 - 85
o - 1000(Va:.=2.0V)
0- 500(Va:.=4.5V)
o - 400(Va:.=6.0V)
iSYMBOL
I
Vee
VI:"
VOLT
Topr
I
Input Rise and Fall Time I t r • tc
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
Va.
Input Leakage Current
Quiescent Supply Cumnt
II:"
la:.
TEST CONDITION
VI:" =
VIHorVIL
VI:" =
VIHorVIL
IOH =-20p.A
IOH --4 mA
IOH =-5.2mA
IOL =20 p.A
Ia. -4 rnA
Ia. =5.2mA
VI:" -Va:. orGND
VI:" -'Va:. or GND
Va:.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-325
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
l.5
V
3.15
4.2
0.5
0.5
V
1. 35
l. 35
l.8
l.8
2.0
l.9
l.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.0
0.1
0.33
0.26
0.17
0.26
0.18
0.33
±0.1
±l.0 p.A
4.0
40.0
MIN.
l.5
3.15
4.2
-
-
-
-
TC74HC160AP/AF •TC74HC161 AP/AF/AFN
TC74HC162AP!AF 'TC74HC163AP/AF/AFN
TIMING REQUIREMENTS(lnput tr=tf=6ns)
PARAMETER
Minimum Pulse Width
(CLOCK)
SYMBOL TEST CONDITION
tW(1I)
two.)
Fig. I
Minimum Pulse Width
(CLEAR) *
t\\,o.)
Minimum Set-up Time
(LOAD, ENP, ENT)
ts
Fig. 2,3
Minimum Set-up Time
(A,B,C,D)
ts
Fig. 2
Minimum Set-up Time
(CLEAR) **
ts
Fig. 5
:-'1inimum Hold Time
q,
Fig. 2,3.5
Minimum Removal Time
(CLEAR) *
Clock Frequency
trem
Fig. 4
Fig. 4
f
Va:.
!' 2.0
4.5
I 6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta= 40 -85"(
UNIT
LIMIT
95
19
16
95
19
16
125
25
21
95
ns
19
16
95
19
16
0
0
0
65
13
Ta=25"C
I 'LIMIT
TYP.
75
15
13
i
75
15
13
, 100
iI
20
1
i
17
75
! 15
13
75
15
13
0
-
I
-
I
I
-
I
-
I
-
i
-
Ii
-
0
0
50
10
9
6
31
36
11
5
25
29
MHz
MAX.
UNIT
AC ELECTRICAL CHAR.ACTERISTICS(CL =15pF.Vcc=5V.Ta=25"C)
PARAMETER
Output Transition Time
Propagation Delay Time
(CLOCK-Q)
Propagation Delay Time
(CLOCK -CARRY)
(Count Mode)
Propagation Delay Time
(CLOCK-CARRY)
[Preset Mode)
Propagation Delay Time
(ENT-CARRY)
Propagation Delay Time·
(CLEAR-Q)*
Propagation Delay Time
(CLEAR-CARRY) *
~Iaximum Clock Frequency
SYMBOL
t TUI
tmL
tpLH
tollL
TEST CONDITION
TYP.
MIN.
Fig. I
-
4
Fig. I
-
13
tpLlI
Fig. I
tpllL I
-
16
26
tPLl!
-
18
30
20
35
Fig. 6
-
10
17
tl~IL
Fig. 4
-
17
tpllL
Fig. 4
-
tpllL
tpLiI
tnHI.
Fig. 2
f~t\x
36
* : for TC74HC160A/16lA only
** : for TC74HC162A/163A only
HC-326
8
I
I
20
i
II
i
63
I
I
21
ns
26
35
!MHz
_ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC160AP/AF 'TC74HC161 AP/AF/AFN
TC74HC162APIAF •TC74HC163APIAF I AFN
AC ELECTRICAL CHARACTERISTICS(C L =60pF,lnput t r =tf=6ns}
Ta- 40 -85"C
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vee MIN. TYP. MAX. MIN. MAX.
2.0
25
75
95
tTLH
Output Transition Time
4.5
7
15
19
tTHL
6.0
6
13
16
2.0
48
125
155
Propagation Delay Time
t pLl -1
Fig. I
25
4.5
16
31
(CLOCK-Q)
tpl-IL
6.0
21
14
26
Propagation Delay Time
2.0
57
150
190
tpLH
(CLOCK -CARRY)
Fig. 1
4.5
19
30
38
tpHL
[Count Mode)
6.0
26
16
33
2.0
175
220
66
Propagation Delay Time
Fig. 2
4.5
22
35
44
tpUI
6,0
37
19
30
(CLOCK -CARRY)
ns
72
2.0
200
250
24
40
4.5
50
tpHL
(Preset Mode)
6.0
20
34
43
2.0
39
100
125
Propagation Delay Time
tpLH
Fig. 6
20
4.5
13
25
(ENT-CARRY)
tpHL
6.0
11
17
21
2.0
60
150
190
Propagation Delay Time
Fig. 4
4.5
20
30
38
tpHL
(CLEAR-Q) •
6.0
17
26
33
200 ,250
2.0
72
Propagation Delay Time
Fig. 4
4.5
24
40
50
tpHL
(CLEAR-CARRY) *
6.0
20
34
43
2.0
6
18
5
)"laximum Clock Frequency
MHz
4.5
31
53
25
f\1AX
I 6.0
36
62
29
Input Capacitance
5
10
10
Cl:"
pF
Power Dissipation Capacitance
CPD(I)
(tE 1)
34
Note (J) C f{) is defined as the value of the internal equ ivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
leettm =C ffi • Va;' f[\ +Ia;
When the outputs drive a capacitive load. total current consumption is the sum of Cf{). and D. Ice which is
obtained from the following formula:
In case of TC74HCl60A/162A:
_
D.lce -feK' Vce
(~~~~Cco)
2
+
5
-I-
10
-I-
10
+III
In case of TC74HC161A/163A:
,_
DIce -fCK' Vce
(~~i1L~Cm)
2 + 4 + 8 + 16 + 16
CQA-CQDand Coo are the capacitances at QA-QD and CARRY OUT. respectively.
fCK is the input frequency of the CLOCK.
(2)
*
for TC74HC160A/161A only
HC-327
TC74HC160AP/AF •TC74HC161 AP/AF/AFN
TC74HC162AP/AF'TC74HC163APiAF/AFN - - - - - - - - - - - - - -......-
SWITCHING CHARACTERISTICS TEST WAVEFORM
(Fig. 1)
COUNT MODE
CLEAR MODE (TC74HC160A/161A)
(Fig. 4)
'-
,..-_ _ _ _ _ _ Vee
CLOCK
f--------
GND
GND
Q,
CLOCK
CARRV _-+_..rl
-4---+-J
GND
1,...
~~---r-----_V~
Q,
CARRV
' - - - - - ' - - - - - - Vo~
(Fig. 2)
PRESET MODE
CLEAR MODE (TC74HC162A/I63A)
GND
(Fig. 5)
Vee
CLEAR
A-D
GND
Vee
Vee
CLOCK
CLOCK
GND
GND
VOH
CARRV
CARRV _ _ _ _J
V~
CASCADE MODE
(Fig. 3)
COUNT ENABLE MODE
VOH
\
Q,
Q,
VOL
(Fig. 6)
(Fix Maximum Count)
, -_ _-.. _ _ _ _ Vee
Vee
ENP
ENT
ENT
+---GND
CLOCK
CARRV
GND
Q
X
:
VOH
VOL
HC-328
'----GND
V~
_ _- - - - - - - - - - - TC74HC160AP/AF'TC74HC161AP/AF/AFN
TC74HC162AP/AF 'TC74HC163APIAF/AFN
TYPICAL APPLICATION
PARALLEL CARRY N-BIT COUNTER
H: COUNT
L : DISABLE
INPUTS
,
1 I BCD
I I I
H : COUNT
L : DISABLE
-
LD A
ENP
'--
ENT
CARRY
-
CLR O. Oa Q c Q o
,
I I I I,
OUTPUTS
CARRY
LD A
'--
ENP
t---
ENT
-
CK
CLR Q. Q a Q c Q o
.
I I I I,
OUTPUTS
CREAR
CLOCK
HC-329
,
LI I I I
C
ENP
ENT
-
CK
INPUTS
..
1 I BI I 0I
LD A
'--
INPUTS
,
BCD
CARRY
CK
CLR Q. Q a Oc Q o
..
I I I I
'
OUTPUTS
-
NEXT STAGE
TC74HC164AP/AF/AFN
8-BIT SHIFT REGISTER(S-IN., P-OUT)
The TC74HC164A is a high speed CMOS 8-BIT SERIAL
-IN PARALLEL-OUT SHIFT REGISTER fabricated
with s.ilicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It consists of a serial-in, parallel-out 8-bit shift
register with a CLOCK input and an overriding CLEAR
input. Two serial data inputs (A, B) are provided so that
one may be used as a data enable.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P( DIP14-P-300)
14~14~
1
F(SOP14-P-300)
FEATURES:
• High Speed .............................. ~\IAX=58).1Hz(typ.)at Vcc=5V
: Low Power Dissipation ............ lee=4.u A(Max.)at Ta=25"C
• High Noise Immunity .............. · \T"IH=V:\IL=28:J6 Vee(Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance "'1 lOll 1=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH ~ tpl-lL
• Wide Operating Voltage Range'" Vee (opr)=2V-6V
• Pin and Function Compatible with 74LS164
FN(SOL 14-P-150)
PIN ASSIGNMENT
A
14 Vee
B
2
13 OH
OA
3
12 OG
OB
4
11 OF
100E
OC
OD
9
6
ClR
8 CK
GND 7
(TOP VIEW)
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS
CLR
CK
L
H
H
H
OUTPUTS
SERIAL IN
A
B
X
X
X
t...
X
X
.r
.r
.r
H
X: Don t Care
OA
OB
L
L
...
...
OH
L
NO CHANGE
L
X
L
OAn
...
OGn
X
L
L
OAn
...
OGn
H
H
H
OAn
...
OGn
OAn-OGn: The level of OA-OG. respectively. before the most recent
positive edge of the clock.
HC-330
CK
A
B
(3)
(4)
(6)
(6)
(10)
(11)
(12)
(13)
OA
OB
OC
OD
OE
OF
OG
OH
- - - - - - - - - - - - - - TC74HC164AP/AF/AFN
SYSTEM DIAGRAM
m
j
A 1
SERIAL
INPUTS 8 2
CK
OA
OS
OC
OE
00
OF
OG
OH
TIMING CHART
CLR
SERIAL
INPUTS
CK
l:
,,
OA --------.;-'------~
,
08
,
--------+----------'
,
,
OC --------.;-'---------~
OUTPUT
:::~:~::l
~r----U
... _-----:
I
______
1------I
n
\ - 1_ _ _ __
OF --------.;.-'
-----------------'
._~
OG
OH
______ ;
rll-_____
::::::::1
~ CLEAR
~ CLEAR
HC-331
TC74HC164AP/AF/AFN--------------
ABSOLUTE MAXIMUM RATINGS
PARAj\'lETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
VALUE
-0.5 -7
-0.5-Vec+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) ./180(MFP)
-65 -150
300
SYMBOL
Vee
VI:,\
VOLT '
111\
101\
I
I Ol: r
Icc
~)
Tstg
TI.
UNIT
V
V
I V
! rnA
frnx,
i
*500mW in the range of Ta=
-40'(- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
until 300m \V.
rnA
rnA
mW
"C
°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vec=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
SYMBOL'
Vee
VI:,\
VOLT
Topr
I tr • tc
I
Input Rise and Fall Time
UNIT
V
V
V
"C
i
ns
I
DC ELECTRICAL CHARACTERISTICS
PARAMETER
'
Ii SYMBOL
TEST CONDITION
.:.
I
i
I Vee I MIN.
I
Ta-25"C
Ta- 40 -85"( :UNIT
TYP. MAX. l\UN. I MAX. i
I
I
;
High - Level
2. O! 1. 5 "
1. 5
Input Voltage, VIII
4.5
3.15 I 3. 215 I V
~-----------+'-----r----------___---_+'1~6~.~0~,~4~.~2-+,--.----+-~-~~-4~.~ ,~-~~--~
Low-Level
i
2.0
i
0.5
- To.5
Input Voltage
VII.
' 4.5 I 1. 35
1. 35
V
6.0 j 1.8
L8
1.9
2.0
1. 9 I 2.0
IaJ =-20/L A 4.5 i 4. 4 I 4.5
4. 4
High-Level
V
B.O
6.0 I 5.9
5.9
Output Voltage
4.31
4.13
Ial --4 rnA 4.5 jl 4.18
I(ll =-5.2mA 6.0
5.68
5.80
5.63
O. 1
0.1
0.0
2.0: 0.1
0.0
0.1
'
V"
=
la.
=20
/L
A
4.5
Low-Level
V
0.1 I
0.1
0.0
Output Voltage
VlllorVIl. I
4
A ' 64.05 : _ t
0.33
0.17 I 0.26 !
o. mi·
! 0.33
I lex. =5.2mA : 6.0
! 0.18 i 0.26 i
Input Leakage Current I
±O.1 t
=1.0 /LA
Quiescent Suppl)' Current I Icc!
! 40.0
VI:,\=VecorGND
'B.O .• 4.0
I,'
I - l -
I'
I -
Ii,
I
- I
- I
i
i
I,
I
I = :
I
'1'
HC-332
I
--------------TC74HC164AP/AF/AFN
TIMING REQUIREMENTS(lnput t r =tl=6n5)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
t\\'(I.)
t\\'(ln I
I!
t\\"(1.)
Minimum Pulse Width
(CLEAR)
Ta-25°C
TYP.
LIMIT
Va;
2.0
4.5
60
2:0
I
I
-
=
75
15
13
80,'
4.5
-
16
6.0
-
9
2. 0
4.5
6.0
2.0
-
5
,5
5
5
5
Ta--40 -85°C IUNIT
LIMIT
I
95
19
16
1
I',
-----'IO::..:.O---~'
20
i
11
i
~-------~--+--------+~6~.0~----=---l1--.~14~_~1'--~61~57-~,
Minimum Set-up Time
2.0
50
I
(A. B)
ts
4.5
10
I
13
I
Minimum Hold Time
(A. B)
Minimum Removal Time
(CLEAR)
t rem
Clock Frequency
i
I
~5
6.0
2.0
4.5
6.0
I
SYMBOL!
Output Transition Time
Propagation Delay Time
(CLOCK-Qn)
Propagation Delay Time
(CLEAR-Qn)
:\-laximum Clock Frequency
I
tT1.1i
tTllL
tpl.li
tPlIL
TEST CONDITION
I
II
I
I
I
MIN.
i
6
31
I
36!
5
25
29
-
33
,
I
I
I
I
I
TYP_
ns
II
5
5
5
5
i,
5
II
tl*IL
f\l-\x
55
ii'
i
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
t
I
i
;MHz
I
iI MAX.
IUNIT
i
!
I
I
I
I
4
15
iI
16
58
8
i
2 - ; t ns
30
I
-
IMHz
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =t l =6n5)
Ta-25°C
i Ta--40 -85°C i r.
PARAMETER
SYMBOL I TEST CONDITION I V
,
cc MIN. I TYP. [MAX. I MIN. MAx. iI.NIT
i
25 ,I 75
95
2.0
tTUI I
i 7
Output Transition Time
, 4.5
15
19 I
tTilL
I
I 6
6.0
13 I 16
57 I 160 I 200
2.0
Propagation Delay Time
tpLlI
ns
19 I 32
40
4.5
(CLOCK-Qn)
tpl-n. I
- i 16
6.0
!
27
34 I
60 ! 175 ,,
220
2.0
Propagation Delay Time
;
20 i
35 i 44
4.5
tl~
II.
(CLEAR-Qn)
I 37
6.0
17
30
;
6 i 18
2.0
Maximum Clock
I 255
31 I 53
f~t\_\
4.5
IMHZ
!
! 29
Frequency
6.0
36 I 62
I
Input Capacitance
Cr, I
5 !
10 ;
10 ! pF
I
I
Power Dissipation Capacitance CPD(ll I
I
I 107
i
~ote (ll C In is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCil"'=C I'D' VU:' f 1\ +1 CC
I
i
I
i
I
I
i
I
I
HC-333
1
I
I
I
I
I
I
i
I
1
TC74HC165AP/AF/AFN----=-.. . . . . . . . . . .
8-BIT SHIFT REGISTER (P-IN,S-OUT)
The TC74HC165A is a high speed CMOS 8-BIT
PARALLELI SERIAL-IN, SERIAL-OUT SHIFT REGISTER
fabricated with silicon gate dMOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low
power dissipation.
It consists of parallel-in or serial-in, serial-out 8-bit
shift register with gated clock inputs. When the SHIFTI
LOAD input is held high,the serial data input is enabled
and the eight flip-flops
perform serial shifting with
each clock pulse.
When the SHIFT ILOAD input is held low, the parallel
data is loaded asynchronously into the register at positive
going transition of the clock pulse.
The CLOCK-INHIBIT input should be shifted high only
when the CLOCK input is held high.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. CMAX=56MHz(typ.)at Vcc=5V
• Low Power Dissipation ............... Icc=4#A(Max.)at Ta=25"C
• High Noise Immunity··············· VNIH=VNIL=28% Vcc(Min.)
• Output Drive Capability'" ......... 10 LSTTL Loads
• Symmetrical Output Impedance .. ·lIoHI =IoL=4mA(Min.)
• Balanced Propagation Delays .. · tpLH.. tpHL
• Wide Operating Voltage Range ." Vcc(opr)=2V-6V
• Pin and Function Compatible with 74LSl65
1
P(DIP16-P-300A)
t'~t6~
F(SOP16-P-300)
FN(S0L16-P-150)
PIN ASSIGNMENT
SIT
CK 2
E 3
F
16
15
14
13
12
11
Vee
CK INH
0
C
B
A
10 SI
4
G 5
H 6
QH 7
GND 8
9
(TOP VIEW)
IEC LOGIC SYMBOL
S/l
CK INH
CK
SI
A
B
C
1
>=L.-I"-~-'
o
E
F
G
H
HC-334
QH
- - - - - - - - - - - - - - TC74HC165AP/AF/AFN
TRUTH
TABLE
INPUTS
INTERNAL
OUTPUTS
OUTPUTS
SHIFTI
LOAD"
CLOCK
INH
CLOCK
SERIAL
IN
PARALLEL
A······· .. H
OA
08
OH
L
X
X
X
a········· h
a
b
h
h
H
L
~
H
X
H
OAn
OGn
OGn
H
L
X
L
OAn
QGn
OGn
~
~
L
L
H
H
X
H
OAn
OGn
QGn
H
~
L
L
X
L
OAn
OGn
OGn
H
X
H
X
H
X
X
X
H
,
OH
No change
-X
No change
X:Don t Care
a······h
:The level of steady input voltage at inputs A through H respectively.
QAn-QGn:The level of QA-QG,respectively,before the most recent positive transition of the CLOCK.
TIMING
CHART
CLOCK
CLOCK
SERIAL
INHIBIT
INPUT
SHIFT/LOAD
A
DON'
CARE UNTIL S/L GOES"L"
B
C
PARALLLEL
INPUTS
D
E
F
G
H
OUTPUT QH
OUTPUT QH
SERIAL
SERIAL
SHIFT
HC-335
SHIFT
rn
-<
rn
-I
m
!:
A
C
B
E
D
F
G
!2
I~
H
:D
l>
3:
~
.....
~
%
()
..r.
G)
U'I
>
......
>
."
......
>
."
"
9 -H
SERIAL
INPUT
7-
~H
CLOCK
::J:
(")
CLOCK
INHIBIT
W
U)
en
SHIFT
1i:iiA5
PD
~Qn
r---+ !-l-I>o-+
CK 1
Jp>o-:+L_
I
• +L
+
+
Z
- - - - - - - - - - - - - - TC74HC165AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee.IGround Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
Vee.
VIN
Voor
11K
10K
Ioor
lee.
PD
Tstg
TI.
VALUE
-0.5-7
-0.5 -Vee.+0.5
-0.5 -Vee.+0.5
±20
±20
±25
±50
500(DIP)*/180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee.
VIN
VOLT
Topr
t r • tr
VALUE
2-6
0- Vee.
0- Vee.
-40 - 85
0-- 1000(Vee.=2.0V)
0- 500(Vee.=4.5V)
o -- 400(Vee.=6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
ViI!
Low-Level
Input Voltage
VII,
High-Level
Output Voltage
I Val
I
Low-Level
Output Voltage
1
Va..
i
Input Leakage Current :
Quiescent Supply Current I
1[,\
lee.
TEST CONDITION
Vee.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
Iai =-20 It A 4.5
VI~=
6.0
VlIlOrVl1.
Iai - 4 rnA 4.5
lai =-5.2mA 6.0
2.0
Ia.. =20 j1A 4.5
VI"=
6.0
VII IorVII,
Ia.. -4 rnA 4.5
Ia.. =5.2mA 6.0
V 1:,\ -Vee. or GND
6.0
V 1:,\ -Vee. or GND
6.0
HC-337
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1..9
2.0
1.9
4.5
4.4
4.4
V
5.9
6.0
5.9
4.13
4.18
4.31
5.80
5.68
5.63
0.0
0.1
0.1
0.0
0.1
0.1
V
0.0
0.1
0.1
0.17
0.26
0.33
0.18
0.26
0.33
±1.0
±0.1
itA
40.0
4.0
MIN.
1.5
3.15
4.2
-
-
-
TC74HC165AP/AF/AFN - - - - - - - -.........-
..................- -
TIMING RECOMMENDED OPERATING CONDITIONS(lnput tr=t,=6ns)
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
LIMIT
TYP.
Vcr
2.0
75
Minimum Pulse Width tWQi)
4.5
15
(CK. CK INH)
tW(L)
6.0
13
2.0
75
Minimum Pulse Width
tW(L)
15
4.5
(S/L)
6.0
13
2.0
75
Minimum Set-:!1p Time
4.5
ts
15
(PI-S/L)
6.0
13
2.0
75
Minimum Set-up Time
ts
4.5
15
(SI-CK.CK INH)
6.0
13
2.0
75
Minimum Set-up Time
ts
4.5
15
(S/L-CK,CK INH)
6.0
13
2.0
0
Minimum Hold Time
4.5
0
Ih
(PI-S/L)
6.0
0
2.0
0
Minimum Hold Time
4.5
0
Ih
(SI-CK.CK INH)
0
6.0
2.0
0
Minimum Hold Time
0
4.5
in
(S/L-CK.CK INH)
6.0
0
Mmimum Removal Time
2.0
75
(CK INH-CK)
4.5
15
trem
(CK-CK INH)
6.0
13
2.0
7
Clock Frequency
f
4.5
30
6.0
41
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
95
19
16
95
19
16
-
95
19
16
ns
0
0
0
0
0
0
0
0
0
95
19
16
6
24
28
MHz
AC ELECTRICAL CHARACTERISTICS(CL =16pF,Vcc=6V,Ta=26"C)
PARAMETER
SYMBOL
Output Transition Time
t1Ui
tnn.
tpUi
tPHL
tpLH
toHL
tpLH
tpHL
-
4
8
-
15
25
-
15
25
-
14
26
fMAX
35
56
-
Propagation Delay TIme
(CK.CK INH-QH.QH)
Propaga~on Dely Time
(S/L-QH,QH)
Propagation DeJ!!.y Time
(H-QH,QH)
Maximum Glock t'requency
TEST CONDITION
He-338
MIN.
TYP.
MAX.
UNIT
ns
MHz
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC165AP/AF/AFN
AC ELECTRICAL CHARACTERISTICS(CL =50pF,lnput t r =t,=6ns}
Ta- 40 -85"C
Ta-25"C
UNIT
PARAMETER
SYMBOL TEST CONDITION
Vcc MIN. TYP. MAX. MIN. MAX.
2.0
75
25
95
t'rI.1l
Output Transition Time
4.5
15
19
8
t1llL
6.0
13
7
16
2.0
150
190
55
Propagation Delay Time
tpLH
4.5
18
30
38
(CK,CK INH-QH,"QH) tJiIL
6.0
26
33
15
ns
2.0
165
205
60
Propaga~on Del!!:y Time
tpLH
4.5
19
33
41
(S/L-QH,QH)
tpilL
6.0
28
16
35
2.0
135
170
52
Propagation Delay Time
4.5
tpllL
17
27
34
(H-QH,QH)
6.0
23
29
14
2.0
7
14
6
Maximum Clock
- MHz
r~x
4.5
24
30
46
Frequency
6.0
28
41
65
Input Capacitance
CI:\
5
10
10
pF
Power Dissipation Capacitance CpDW
55
Note (1) Cm is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load,
Average operating current can be obtained by the equation:
ICCtpD=Cro • Va:.. fl'\ +Ia:.
HC-339
TC74HC166AP/AF/AFN---...o.-8'"'"BIT SHIFT REGISTER (P-IN,S-OUT)
The TC74HC166A is a high speed CMOS 8 BIT
PARALLEL/SERIAL-IN, SERIAL-OUT SHIFT REGISTER
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It consists of parallel-in or serial-in, serial-out 8-bit
shift register with a gated clock input and an overriding
clear input. The parallel-in or serial-in modes are
controlled by the SHIFT ILOAD input. When the SHIFT I
LOAD input is held high, the serial data input is enabled
and the eight flip-flops perform serial shifting on each
clock pulse. When held low, the parallel data inputs are
enabled and synchronous loading occurs on the next clock
pulse. Clocking is accomplished on the low-to-high
tragsition of the clock pulse. The CLOCK-INHIBIT input
should be shifted high only while the CLOCK input is held
high. A direct clear input overrides all other inputs,
including the clock, and sets all the flip-flops to zero.
Functional details are shown in the truth table and the
timing charts.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ·• .... · .. ·.. ··· .. · .. · ...... ·.. 1MAx=57MHz(Typ.)at Va;=5V
• Low Power Dissipation ............ Ia;=4.uA(Max.)at Ta=25"C
• High Noise Immunity .............. · VN1H =VN1L 28" Va;(Min.)
• Output Drive Capability'" ......... 10 LSTTL Loads
• Symmetrical Output Impedance "'1 IOII=Ia. =4mA(Min.}
• Balanced Propagation Delays ...... tpLH"o--+L
"E;
J
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC166AP/AFI AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
!
I
I
I
i
Vee
VI\
VOLT
i
11K
I
I
I
10K
IOLT
Icc
Po
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
VALUE
-0.5 - i
-0.5 -Vee +O.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
SYMBOL
I
1
I
*500mW in the range of Ta=
-40'C- 65"C. From Ta=65'C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
"C
"C
RECOMMENDED OPERATING CONDITIONS
ISYMBOL !
I Vee L
! VI\ I
I VOLT !
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
i
Topr
UNIT
V
V
V
cC
VALUE
2-6
0- Vee
0- Vee
-40 - 85
I
o-
Input Risa and Fall Timal t" " i
JOOO(~ee=2.0V)
ns
0- 500(Vec =4.5V)
0- 400(Vee =6.0V)
I
DC ELECTRICAL CHARACTERISTICS
PARAMETER
High-Level
Input Voltage
SYMBOL
I
VII' I
Ii
TEST CONDITION
I
I
Low-Level
Input Voltage
VIL
i
High-Level
Output Voltage
VOl I
Low-Level
Output Voltage
VOl.
Input Leakage Current
Quiescent Supply Current
11\
ICC
I
I
I
i
!/ 1
V
\ =
I VillorV1L
I
:: ~ I
2.0
4.5
6.0
I
!1011
Ta-25"C
Ta- 40 -85°C UNIT
TYP. MAX. MIN. MAX.
I
1.5 ! V
3.15 I 4.2
I
0.5 i
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4. 18
4.13
4.31 I
5.68
5.80 I 5.63
..0.0
0.1
0.1 I
0.0
0.1 I
O. I
0.0 I 0.1
0.1 i V
O.
Ii
,
0.26
0.33
I
0.33
0.18 ! 0.26
±0.1
-1.°I.u A
- I 40.0 ,
4.0
Vee MIN.
2.0 i 1.5
4.;) t 3.15
6.0 I 4.2
I 2.0 I -
=-20.u A
I'I Of!
- 4 m A 4. 5
II(]I =-5. 2mA 6.0
2.0
1
1101. =20 .u A 4.5
VI\=
6.0
VlllorVIL
i I(l. -4 rnA 4.5
: 101. =5.2rnA 6.0
!
' 6.0
V I\ -Vee or GND
I
V I\ -Vee or GND
6.0
I
HC-343
I
I
I
I
I
I
TC74HC166AP/AF/AFN - - - - - - - - - - - - - - -
TIMING REQUIREMENTS(lnput tr =tf=6ns)
PARAMETER
; SYMBOL TEST CO)[DlTIO)[
Minimum Pulse Width
(CLOCK)
Vec
2.0
4.5
t,,',1f)
two.)
I
I
I
Ta-25°C
TYP.
I
I
-
I
-
Ta- 40 -85°C U)[IT
LIMIT
' LIMIT
75
15
95
19
75
15
95~
... I
:
r---------------~-----r-------------r~6~.0~t-------~--~13~~----~16
Minimum Pulse Width ,'I
(CLEAR)
. tm,Ll
2.0
4.5
6.0
I
I
-
I
19
13
16
~---------------~-----4------------~-72~0-r-1------~--~~---~----9~~~--41
~linimum Set-up Time:
(SI,PI)
,
.
4.5
6.0
2.0
ts
;
Minimum Set-up Time'
I
2.0
I
I 2.0
:
6.0
I
Minimum Hold Time
(SI,PI)
:
Minimum Hold Time
(S/L)
t rem
4.5
6.0
I
! 2.0
I
f
4.5
i 6.0
75
15
13
75
I
I
I
--
1
u
19
16
95
19
I
15
13
o
o
o
o
0
0
50
10
-
i
i
i
I
I
o
65
13
9
6
31
36
I
ns
o
0
0
II
.
16
0
0
-I
4.5 !
6.0 i
2.0
Clock Frequency
-
--
4.5 i
6.0 I
th
Minimum Removal Time'
(CLEAR)
I
4.5
(SiL)
-
11
5
I
25
29
MHz
U)[IT
AC ELECTRICAL CHARACTERISTICS(C L =15pF. Vcc=5V. Ta=25"C)
PARAMETER
Output Transition Time
Propagation Delay Time
(CLOCK-QH)
Propagation Delay Time
(CLEAR-QH)
Maximum Clock Frequency
:SBIBOL
TEST CONDITION
I
MIN.
tTW
tTl II.
-
t"LlI
tI'l II.
-
t,,111.
-
I
!
I
MAX.
4
8
,
,
16
I
15
57
I
j
i
33
HC-344
I
I
I
i
I
I
i
f\t\\
i
TYP.
!
I
26
ns
24
-
MHz
--------------TC74HC166AP/AF/AFN
AC ELECTRICAL CHARACTERISTICS{C L =60pF,lnput t r =tf=6ns)
Ta- 40 -85"C
Ta-25"C
milT
TYP. MAX. MIN. MAX.
2.0
30
75
95
t ·11.11
Output Transition Time
4.5
8
15
19
ton II.
6.0
7
13
16
2.0
70
150
190
Propagation Delay Time
tpl.l1
ns
4.5
38
20
30
(CLOCK-QH)
tl~ II.
6.0
32
26
16
2.0
135
170
60
Propagation Delay Time
4.5
27
34
18
t l~ II.
(CLEAR-QH)
6.0
23
29
14
2.0
6
14
i 5
I
Maximum Clock
- IMHz
4.5
f~L\X
25
31
50
Frequency
6.0
36
29
63
Input Capacitance
5
10
! 10
CI"
pF
Power Dissipation Capacitance
CI'D(1l
60
Note (j) Cln is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCq)jj=CIl) • VCC· f", +ICC
PARAMETER
SYMBOL TEST
CO~DITIO~
Vex
MIN.
I
I
I
HC-345
TC74HC173API AF~-----QUAD D-TVPE REGISTER(3-STATE)
The TC74HC173A is a high speed CMOS D-TYPE
REGISTER fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power
dissipation.
It contains a 4-bit register consisting of D-type flipflops and 3-state buffers. The four flip-flops are
controlled by a common clock input (CLOCK) and a
common clear input (CLEAR).
Signals applied to the data inputs (DI-D4) are stored
in the respective flip-flops on the positive going transition
of CLOCK when clock control inputs (Gl, G2) are held
low.
The clear function is asynchronous to CLOCK and
active on a high level. The stored data are enabled to each
outputs when output control inputs (M, N) are held low,
else the outputs are high impedance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEA'I'URES:
• High Speed .............................. tpd=47~Hz(Typ.)at Vee =5V
• Low Power Dissipation ............ l ee =4.uA(Max.)at Ta=25"C
• High Noise Immunity .............. · V:\IH =V:\IL2896 Vee (Min.)
• Output Drive Capability'" ......... 15 LSTTL Loads
• Symmetrical Output Impedance "'110111 =IOL =6mA(Min.)
• Balanced Propagation Delays ...... tpLH"'tpHL
• Wide Operating Voltage Range'" Vee (opr.)=2V -6V
• Pin and Function Compatible with 74LS173
IEC LOGIC SYMBOL
~--'~--l:...fl4110
20
30
40
HC-346
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
M1
16 Vee
15 CLEAR
N2
103
1410
204
1320
30 5
40 6
1140
CLOCK 7
10 G2
GND 8
9 G1
1230
(TOPVIEWl
----------------------------------TC74HC173AP/AF
TRUTH TABLE
DATA
ENABLE
CLEAR CLOCK
On
OUTPUT
CONTROL
N
M
X
H
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
Gl
G2
X
X
X
X
H
X
X
X
X
X
X
L
L
L
L
L
1..
X
X
X
X
X
X
..r
..r
..r
..r
H
X
X
X
H
X
L
L
L
L
H
L
On
Z
Z
L
X : Don't Care
Z : High Impedance
00
00
00
H
L
SYSTEM DIAGRAM
CLEAR
CLOCK
H-1---D---1I--=-3-
10
4H-I---I >--1_.:..
20
H-1---D--iI--=-5-
30
H---j >---ir--..:;.6_ 4Q
">0---
G
.>c>----G
M
N
HC-347
TC74HC173AP/AF-----------------.....ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage R.ange
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
Voor
11K
10K
IU,T
lee
PD
Tstg
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP)*/180(SOIC)
-65 -150
300
*500mW in the range oC Ta=
.-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
. Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
UNIT
V
V
V
"C
VALUE
2-6
0- Vee
O-Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
0- 400(Vee =6.0V)
SYMBOL
Vee
VIN
Voor
Topr
tr , tf:
-
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Va-t
Low-Level
Output Voltage
Va.
3 -State Uutput
'OCC-State Current
10l
Input Leakage Current
Quiescent Supply Current
liN
Ia:;
TEST CONDITION
VIN=
VIHorVIL
VIl~=
VIHorVIL
la-t =-20/lA
la-t --6 mA
la-t =-7. SmA
Ia. =20 /lA
la. -6 mA
lOt. =7. SmA
V I1\: -VIH or V IL
VU,T =Vee or GND
YIX -' Vee or GNp
VI:'\ -'Va:; or GND
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.S
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.18
4.31
4.13
5.68
5.80
5.63
0.0
0.1
0.1
0.1
0.1
0.0
V
0.1
0.1
0.0
0.33
0.26
0.17
0.33
0.26
O.lS
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
MIN.
1.5
3.15
4.2
6.0
-
6.0
6.0
-
HC-348
-
-
±0.5
-
±5.0
+0.1
4.0
-
+1.0
40.0
-
/lA
- - - - - - - - - - - - - - - - TC74HC173AP/AF
TIMING REQUIREMENTS{lnput t r =tf=6ns}
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
{CLOCK}
tW(L)
tW(H)
Minimum Pulse Width
(CLEAR)
twoo
Minimum Set-up Time
CGl, G2)
ts
Minimum Set-up Time
CD)
ts
Minimum Hold Time
(Gl, G2, D)
th
Minimum Removal Time
(CLEAR)
Clock Frequency
trem
f
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6 0
HC-349
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
100
20
17
75
15
13
0
0
0
5
5
5
9
43
51
I
I
I
I
Ta--40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
125
25
21
ns
95
19
16
0
0
0
5
5
5
7
MHz
34
40
TC74HC173AP/AF------------------
AC ELECTRICAL CHARACTERISTICS(lnput t r =tf=6ns)
TEST
Ta-25"C
Ta- 40 -85"C
PARAMETER
UNIT
SYMBOL
CONDITION CL
Vee MIN. TYP. MAX. MIN. MAX,
2.0
20
60
75
tTLH
Output Transition Time
4.5
12
50
15
6
tTliL
6.0
10
13
5
2.0
50
115
145
4.5
50
23
29
15
Propagation Delay Time
6.0
tpU1
20
12
25
2.0
65
155
195
(CLOCK-Q)
tpHL
150 4.5
20
31
39
6.0
26
16
33
2.0
50
115
145
4.5
50
23
29
15
p
Propagation Delay Time
6.0
12
20
25
ns
tpHL
2.0
63
155
195
(CLEAR-Q)
150 4.5
20
31
39
6.0
26
16
33
2.0
50
115
145
.50 4.5
15
23
29
6.0
tpZL
12
20
25
Output Enable time
RL = 1 kQ
2.0
tpZH
63
115
195
150 4.5
20
31
39
6.0
26
16
33
2.0
36
135
170
tpLZ
Output Disable time
R L= 1 kQ
4.5
50
27
17
34
tpHZ
6.0
23
29
15
9
7
2.0
20
- MHz
Maximum Clock Frequency
fMAl(
50 4.5
43
67
34
6.0
51
84
40
Input Capacitance
C e.;
5
10
10
Output Capacitance
pF
C OlIT
10
Power Dissipation Capacitance Cpf)W
45
Note(I) Cro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ieeq,o=Cro • Vo::.. fl:' +10::.
And the total Cro when n pes of Flip Flop operate can be gained by the following equation:
Cro(total)=28+17. n
-
HC-350
-----TC74HC174AP/AF/AFN
HEX D-TVPE FLIP FLOP WITH CLEAR
The TC74HC174A is a high speed CMOS D-TYPE FLIP
FLOP fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Information signals applied to the D inputs are
transferred to the Q outputs on the positive going edge of
the clock pulse.
When the "C"L-;:E"A"R" input is held low. the Q outputs are in
the low logic level independent of the other inputs. .
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. fMAX=71MHz(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=4.uA(Max.) at Ta=25"C
• High Noise Immunity ............... V~IH=VNIL =28% Vcc(Min.)
• Symmetrical Output Impedance ···1 Ia-t 1=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH"tpHL
• Wide Operating Voltage Range .. ' Vcc (opr.)=2V-6V
• Pin and Function Compatible with 74LS174
1
P(DIP16-P-300A)
"~1.~
F(SOPI6-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
CLEAR 1
16 Vee
01 2
15 06
01 3
1406
02 4
1305
02 5
12 05
03 6
11 04
03
1004
9 CLOCK
GNO 8
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
OUTPUT
INPUTS
FUNCTION
CLEAR
D
CLOCK
0
L
X
X
L
CLEAR
H
L
..r
L
H
H
J
H
-
H
X
1..
On
NO CHANGE
X : Don't care
HC-351
TC74HC174AP/AF/AFN - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI:\
Voor
11K
10K
len
lee
PD
Tstg
TI-
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)*/180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Inp~t
VALUE
2-6
0- Vee
o -Vee
-40 - 85
0-- 1000(Vcc=2.0V)
0- 500(Vee =4.5V)
o -- 400(Vee=6.0V)
SYMBOL
Vee
VI:"
VOlJT
Topr
Rise and Fall Time
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
I
PARAMETER
SYMBOL I
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
TEST CONDITION
I
I!
!
I
I
1
!
High-Level
Output Voltage
!
VDH
I
I
VI:\ =
VUlorVIL
I
I
Low-Level
Output Voltage
VOL
=
I VUlorV
U.
VI:\
I
!
Input Leakage Current
Quirseenl Supply Current
11:\
Icc
I
la-l =-20/.1. A
IDH - 4 rnA
IDH =-5. 2mA
la. =20 /.I. A
-4 rnA
IOL =5.2mA
V I:\ -Vee orGND
V[\ -Vee orGND
101.
Ta-25"C
Ta- 40 -85"(;
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
I
I
V
1. 35
1. 35
i
1.8
1.8
I
I
2.,0
,I. 9
I 1.9
I
4.5
4.4
I 4.4
V
: 5.9
5.9
6.0
4.18
4.31
4.13
I 5.68 5.80 5.63
O. I
0.1
0.0
!I 0.1
0.1
0.0
, V
0.1
0.1
0.0
i
- I 0.17 0.26
0.33
0.33
0.26
1 0.18
±1.0
I
I ±0.1 /.I. A
40.0
! 4.0
I
!
Vee
2.0
4. 5
6.0
2.0
4.5
6.0
2.0
4.5
6.0,
4.5
6.0
2.0
4.5
6,0
4.5
6.0
6.0
6.0
HC-352
I r-.UN.
! 1.5
I 3.15
i 4.2
-
- - - - - - - - - - - - - - - TC74HC174AP/AF/AFN
TIMING REQUIREMENTS(lnput tr=t,=6ns)
SYMBOL
PARAMETER
Minimum Pulse Width
(CLOCK)
Minimum Pulse Width
(CLEAR)
I t,,'(H)
tIro.)
i
Minimum Set-up Timel
I
Minimum Hold Time
I
Minimum Removal Time
(CLEAR)
Clock Frequency
TEST CONDITION
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
I
tW(L)
ts
th
t rem
I
Vee
f
Ta-25"C
LIMIT
TYP.
75
15
13
75
15
13
75
15
13
0
0
0
25
5
4
6
33
38
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
95
ns
19
16
0
0
0
30
6
5
4
MHz
26
30
-
I
AC ELECTRICAL CHARACTERISTlCS(C L =15pF,Vcc =5V,Ta=25°C)
PARAMETER
Output Transition Time
ISYMBOL
I
i
TEST CONDITION
MIN.
tTLH
tTl-II
tpLH
toHL
Propagation Delay Time
(CLOCK-Q)
Propagation Delay Time I
(CLEAR-Q)
! tpHL
).Iaximum Clock Frequency I f\l\X
TYP.
MAX.
-
4
8
-
14
26
-
15
26
39
71
-
UNIT'
ns
MHz
AC ELECTRICAL CHARACTERISTICS(CL =50pF,lnput t r =t,=6ns)
Ta- 40 -85"C
Ta-25"C
PARAMETER
UNIT
ISYMBOL TEST CONDITION
Vee MIN. I TYP. MAX. MIN. MAX.
- I 27
i
2.0
75
! 95
tTLII
Output Transition Time
4.5
8
15
19
tlliL
6.0
7
13
16
2.0
68
150
190
~ropagation Delay Time
tpLH
ns
4.5
17
30
38
(CLOCK-Q)
I tpHL
- I 14
6.0
;
26
32
2.0
72
150
190
Propagation Delay Time
4.5
tpHL
18
30
38
(CLEAR-Q)
~
I
6.0
15
26
32
6
4
15
2.0
Maximum Clock
MHz
4.5
33
f\t\x
59
26
Frequency
38
i 6.0
71
30
Input Capacitance
Ce\
5
10
10
pF
Power Dissipation Capacitance C PD (1)
- I 40
Note (1) C I'D IS defmed as the value of the mternal equivalent capacitance whICh 15 calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCq,Il=Cro Vcr fl'\ +Ia.: 16 (per Flip Flop)
And the total Cp[) when n pcs. of Flip Flop operate can be gained by ·the following equation:
q~,(total)=28+12 0 n
I
I
I
I
I
i
0
0
HC-353
I
I
I
TC74HC174AP/AF/AFN - - - - - - - - - - - - - -
SYSTEM DIAGRAM
D1
D2
D3
CLOCK
He-354
D4
D5
D6
-----TC74HC175AP/AF/AFN
QUAD
D-TYPE
FLIP
FLOP
WITH
CLEAR
The TC74HC175A is a high speed CMOS D-TYPE FLIP
FLOP fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Information signals applied to D inputs are transferred
to the Q and Q outputs on the positive going edge of the
clock pulse.
When the CLEAR input is held low, the Q outputs are at
the low logic level and the Q outputs are at the high logic
level independent of the other inputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P( DIP16-P-300A)
"~16~
F(SOP16-P-300)
FEATURES:
• High Speed ................................. fMAJr 63MHz(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=4#A(Max.) at Ta=25"C
• High Noise Immunity··············· VNIH=VNIL =28% Vcc(Min.)
• Symmetrical Output Impedance ···11oH I=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH '" tpHL
• Wide Operating Voltage Range ... Vcc (opr.)=2V-6V
• Pin and Function Compatible with 74LS175
FN(SOL 16-P-150)
PIN ASSIGNMENT
16
15
14
13
12
11
10
CLEAR 1
10
2
10
10
3
4
20
5
20:
20
6
7
GNo 8
Vee
40
40:
40
3D
30:
3Q
9 CLOCK
(TOPVIEWI
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLEAR
D
CLOCK
a
a
L
x
X
L
H
Clear
H
L
L
H
-
H
H
H
L
-
H
X
S
S
L
an On
No change
X : Don't care
HC-355
ClR
ClK
10
10
10
20
TC74HC175AP/AF/AFN - - - - - - - - - - - - - -
SYSTEM DIAGRAM
CLOCK
10
10
20
HC-356
20
30 30
4Q
40
TC7 4HC175API AF I AF N
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vc'C/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
VALUE
-0.5-7
-0.5 -Vo:+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)·/180(MFP)
-65 -150
300
SYMBOL
Vee
VI:\
VOLT
11K
10K
IOL1·
lee
PD
Tstg
TL
I
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW I"C shall be applied
until 300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
VALUE
2-6
0- Vee
o -Vee
-40 - 85
0- 1000(Vee =2.0V)
0·- 500(Vee =4.5V)
o - 400(Vee =6.0V)
SYMBOL
Vee
VI:\
VOLT
Topr
Input Rise and Fall Time
tr , tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
SYMBOL
P ARAl\lETER
High-Level
Input Voltage
Low-Level
Input Voltage
Input Leakage Current
Quiescenl Supply Current
Vee
2.0
4.5
VIII
6.0
I
2.0
4.5
VII.
6.0
2.0
=
-20
Il A 4.5
VI:\=
I
V(ll
6.0
VlllorVIl.
II<'Jli - 4 mA 4.5
110< =-5.2mA 6.0
2.0
101• =20 Il A 4.5
VI:\=
V(l.
6.0
VlllorVIl . I l(x. -4 mA
4.5
I
I(x. =5.2mA 6.0
VI:\ -Vee or GND
6.0
11:\
6.0 !
\'1:\ -Vee or GND
lex:
1rc~'1
High-Level
Output Yoltage
Low-Le\'el
Output Voltage
TEST CONDITION
I
I
I
I
I
I
I
I
HC-357
Ta-25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
6.0
5.9
5.9
4.13'
4.18
4.31
5.68
5.80
5.63
0.0
0.. 1
0.1
0.1
0.1
0.0
- I 0.0
V
0.1
0.1
0.17
0.26
0.33
O. 111
0.33
0.26
±O.1
±1.0
A
4.0
40.0 Il
MIN.
1.5
3. 15
4.2
I
TC74HC175AP/AF/AFN - - - - - - - - - - - - - - -
r
TIMING REQUIREMENTS(lnput t =tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
t\\"(L)
t\\",.I,",
I
I
Minimum Pulse Width
(CLEAR)
t\\"(1. 1
Minimum Set-up Time
t5
Minimum Hold Time
th
't rem
Minimum Removal Time
f
Clock Frequency
I
I
.d-
Ta- 40 -85"C
UNIT
LIMIT .
95
19
16
95
19
16
95
ns
19
16
0
0
0
95
19
16
5
25
MHz
29
Ta-25"C
Vee' -- TYP.
LIMIT
2.0
75
4.5
15
6.0
_;13
- -2.0
75
4.5
15
6.0
13
2.0
75
4.5
15
6.0
13
2.0
0
4.5
0
6.0
0
2.0
i5
4.5
15
6.0
13
2.0
6
4.5
31
6.0
36
I
I
I
I
I
AC ELECTRICAL CHARACTERISTICS(C L =15pF. Vcc=5V. Ta=25"C)
PARAMETER
!SYMBOL I
Output Transition Time
Propagation DelaLrime
(CLOCK-Q, Q)
Propagation De1ay....'!'ime
(CLEAR-Q, Q)
:Maximum Clock Frequency i
I
tT1.I1
tTl II
tpl.H
t )IIL
tpl.Il
t )Ill
Ii
f\l\"
I
TEST CONDITION
I
I
!
MIN.
I
I
-
I
Ii
TYP.
MAX.
4
8
-
!
i
16
24
i
-
13
21
I
36
I
I
I
!UNIT
ns
'MHz
63
AC ELECTRICAL CHARACTERISTICS(CL =50pF.lnput t r =tf=6ns)
Ta-25"C
: Ta= 40 -85"C
PARAMETER
snlBoLi TEST CONDITION
UNIT
I
Vcc l\HN. TYP. l\-IAX. ! MIN. MAX.
I
2.0
75 i
95
I, 30
tTUI II
Output Transition Time
4.5
I
8
15 II
19
I
t·nn. I
I 7
6.0
13 I
16 I
2.0
70
140
175
I
Propagation Delay Time
tpl.l1
ns
4.5
I
19 I 28
35
(CLOCK-Q, Q)
tpHI. !
- 6.0
16 ! 24 I 30 I
,
2.0 ! I
50
125 I 160
Propagation Delay....'!'ime
tpLI! I
!
I
4.5
25
32
16
(CLEAR-Q, Q)
tpllL
6.0
22
27
i
12
2.0
6
5
14
II
Maximum Clock
- MHz
4.5
25
31
53
£\1..\"
Frequency
6.0
29
36
63
Input Capacitance
Ce, I
5
10
I
J~- i pF
! 53 I - ! Power Dissipation Capacitance
Cpo(1) I
Note (J) C R) IS defmed as the value of the mternal equivalent capacitance which IS calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icc (pl=CH) .VC'C.f!': +1((' /4(perFlipFlop)
And the total C H) when n pes. of Flip Flop operate can be gained by the following equation:
Cm(total)=32-21 • n
I
I
I
I
I
I
I
i
HC-358
I
!
I
I
I
I
--------TC74HC181P
TC74HC181P
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
The TC74HC18l is a high speed CMOS ARITHMETIC LOGIC UNIT(ALU)/FUNCTION GENERATORS
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent LSTTL while maintaining
the CMOS low power dissipation.
This circuit perform 16 binary arithmetic operations on two 4-bit word as shown in
Tables 1 and 2.
These operations are selected by the four function-select lines (SO,
51, 52, 53) and include addition, subtraction, decrement, and straight transfer.
When performing arithmetic manipulations, the internal carries must be enabled by
applying a low-level voltage to the mode control input (M).
A full carry look ahead
scheme is made available in these devices for fast, simultaneous carry generation be
means of two cascade-outputs (pins 15 and 17) for the four bits in the package.
When used in conjunction with the TC74HC182, full carry look-ahead circuits, highspeed arithmetic operations cart be performed.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
FEATURES:
• High Speed
t pd=30ns(Typ.) at VCC=5V
• Low Power Dissipation ••••••
ICC=4~A(Max.)
at Ta=25°C
• High Noise Immunity ••••••••• VNIH=VNIL=28% VCC(Min.)
• Output Drive Capability •••.•••••••••• 10 LSTTL Loads
• Symmetrical Output Impedance •••• !IOH!=IOL=4mA(Min.)
• Balanced Propagation Delays •••••••••••••••
tpLH~tpHL
• Wide Operating Voltage Range •••••• VCC(Opr.)=2V
• Pin and Function Compatible with 74LS18l
HC-359
~
6V
DIP24(3D24A-P)
TC74HC181P
PIN ASSIGNMENT
SCi
1
24
VCC
AO
2
23
Al
S3
3
22
Bl
S2
4
21
A2
SI
5
20
B2
SO
6
19
A3
Cn
7
18
B3
M
8
17
G
FO
9
16
Cn+4
Fl
10
15
P
F2
11
14
A=B*
GND
12
13
F3
(TOP VIEW)
*: Open drain Output Structure
PIN DESIGNATIONS
Designations
Pin No.
AO, AI, A2, A3
2, 23, 21, 19
Word A Inputs
BO, B1, B2, B3
SO, Sl, S2, S3
Cn
M
I, 22, 20, 18
6, 5, 4, 3
7
8
Word B Inputs
Function Select Inputs
Inv. Carry Input
Mode Control Input
FO, F1, F2, F3
A=B
9, 10, 11, 13
14
Function Outputs
Comparator Outputs
Carry Propagate Output
Inv. Carry Output
P
Cn+4
G
Vce
GND
15
16
17
24
12
Function
Carry Generate Output
Supply Voltage
Ground
He-360
TC74HC181P
FUNCTIONAL DESCRIPTION
The HC18l will accomodate active-high or active-low data, if the pin designations are interpreted as show below.
Pin Number
2
Active-low data (Table 1)
Active-high data(Table 2)
1 23 22 21 20 19 18 9 10 11 13 7
16
15 17
AO BO Al Bl A2 B2 A3 B3 FO Fl F2 F3 Cn Cn+4 P G
AO BO Al Bl A2 B2 A3 B3 FO F1 F2 F3 Cn 1Cn+4 X Y
Subtraction is accomplished by l's complement addition where the l's complement
of the subtrahend is generated internally. The resultant output is A-B-l, which
requires an end-around or forced carry to produce A-B.
The HC18l also be utilized as a comparator. The A=B output is internally decoder from the function outputs (FO, Fl, F2, F3) so that when two words of equal
magnitude are applied at the A and B inputs, it will assume a high level to indicate
equality (A=B). The ALU should be in the subtract mode with Cn=H when performing
this comparison. The A=B output is open-drain so that it can be wire-AND connected
to give a comparison for more than four bits. The carry output (Cn+4) can also be
used to supply relative magnitude information. Again, the ALU should be placed in th
subtract mode by placing the function select input S3, S2, Sl, SO at L, H, H, L,
respectively.
Input
Cn
Output
Cn+4
Active-low data
(Figure 1)
Active-high data
(Figure 2)
H
H
A~B
MB
H
L
AB
L
H
A>B
A--C>(~
82
83
G
4
p----t::>o--c>o-=:;;..
On+4.
3
l5
p
Ai
111'2
Hi
10_
1'1
Cn ~{>o-~~----------~~)r-------+-i>~
M
14
HC-364
TC74HC181P
INPUT and OUTPUT EQUIVALENT CIRCUIT
Vee
Vee
--1
vee
I
~
OUTPUT
OUTPUT
INPUT
I
X
I
GND
GND
_J
ONLY OUTPUT A=B
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
SYMBOL
DC Input Voltage
DC Output Voltage
VCC
VIN
---
Input Diode Current
Output Diode Current
VALUE
-0.5", 7
VOUT
t--IIK
---
10K
-- t - - - - - -
DC Output Current
DC Vcc/Ground Current
-=-----------Power Dissipation
lOUT
ICC
PD
--
UNIT
V
V
V
-0.5", VCc+O. 5
-0.5 ",VCc;+0.5
±20
±20
rnA
rnA
±2S
rnA
±50
rnA
500*
mW
-65'" 150
300
·C
·C
LIMIT
UNIT
-----
Storage Temperature
Lead Temperature 10sec
Tstg
TL
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SY~lBOL
VCC
VIN
VOUT
Topr
2"'6
0", VCC
0", Vce
-40'" 85
t r , tf 0"'1000 (VCC=2. OV
o ",SOO(Vec=4.SV
o '" 400 (VCC=6. OV)
He-365
V
V
V
·C
ns
*
500mW in the range of
Ta=-40·C '" 6S oC and from
Ta=65°C up to 85°C
derating factor of
-lOmW/oC shall be
applied until 30OmW.
TC74HC181P
DC ELECTRICAL CHARACTERISTICS
Ta=25°C
~
PARAMETER
SYMBOL
TEST CONDITION
~CC MIN.
2.0
High-Level
Input Voltage
Low-Level
Input Voltage
VIL
VOH
Any output
except A=B
VIN=V IH
IOZ
Input Leakage
Current
lIN
-
-
1.5
-
0.5
-
0.5
1.35
-
1.35
-
1.8
-
3.15
4.2
1.9
4.4
-
5.9
6.0
-
5.9
-
~.5
4.18
4.31
4.13
-
IOH=-5.2mA 6.0
5.68
5.80
-
5.63
-
2.0
-
~.5
0.00
0.00
0.00
0.1
0.1
0.1
-
-
0.1
0.1
0.1
0.17
0.26
-
0.33
0.18
0.26
-
0.33
IOH=-4mA
1.8
IOL=4mA
~.5
IOL=5.2mA
6.0
-
6.0
-
..,.
±0.5
-
±5.0
6.0
-
-
±0.1
-
±1.0
6.0
UNIT
V
-
-
VIN=V IL or VIH
Output OffState Current
MAX.
2.0
4.5
I OH =-20IJA ~.5
6.0
-
MIN.
-
Low-Level
VOL
-
MAX.
1.9
4.4
6.0
2.0
IOL=20IJA
Output Voltage
4.2
TYP.
-
4.5
VIN=VIH
or VIL
High-Level
Output Voltage
~.5
6.0
2.0
VIH
1.5
3.15
Ta=-4Q'\.85°C
V
V
V
IJA
VOUT=VCC
VIWVCC or GND
IJA
Quiescent
Supply Current
ICC
6.0
VIN=VCC or GND
HC-366
-
-
4.0
-
40.0
TC74HC181P
AC ELECTRICAL CHARACTERISTICS (CL-50pF
, Input t r =tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Output Transition Time
Propagation Delay Time
tTLH
tTHL
tpLH
tpHL
(1)
Propagation Delay Time
(2)
tpLH
Propagation Delay Time
tpLH
(3)
tpHL
tpHL
Propagation Delay Time
(4)
tpLH
tpHL
Propagation Delay Time
tpLH
tpHL
(5)
tpLH
Propagation Delay Time
(6)
tpHL
Propagation Delay Time
tpLH
(7)
tpHL
tpLR
Propagation Delay Time
(8)
tpHL
Propagation Delay Time
tpLH
(9)
tpHL
Propagation Delay Time
(10)
tpLH
Propagation Delay Time
tpLH
(11)
3-State Output
Enable Time
tpHL
(12)
3-State Output
Disable Time
tpHL
(12)
tpZL
RL=lkS"l
tpLZ
RL=lkn
He-367
Ta 25°C
r---
VCC
MIN.
2.0
4.5
6.0
2.0
4.5
6.0
2:0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0.
2.0
4.5
6.0
-
-
-
-
-
-
-
-
-
-
-
TYP.
30
8
7
68
17
14
124
31
26
120
30
26
112
28
24
116
29
25
116
29
25
108
27
23
108
27
23
136
34
29
136
34
29
112
28
24
124
31
26
140
35
30
Ta -4O'V85°C
MAX.
75
15
13
135
27
23
240
48
41
235
47
40
215
43
37
225
45
38
220
44
37
210
42
36
210
42
36
265
53
45
265
53
45
215
43
37
240
48
41
260
52
44
MIN.
-
-
-
-
-
-
-
"-
-
UNIT
MAX.
95
19
16
170
34
29
300
60
51
295
59
50
270
54
46
280
56
48
275
55
47
265
53
45
265
53
45
330
66
56
330
66
56
270
54
46
300
60
51
325
65
55
ns
TC74HC181P
AC ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL TEST CONDITION ~
PARAMETER
Ta=25°C
Input Capacitance
CIN
-
TYP.
5
Power Dissipation
Capacitance
CpD(l)
-
216
Note(l):
MIN.
Ta=-40'V85°C
MAX.
MIN.
MAX.
10
-
10
-
-
-
pF
CpD is defined as the value of internal equivalent capacitance of IC which
is calculated from the operating current consumption without load (refer to
Test Circuit).
Average operating current can be obtained by the equation hereunder.
ICC(Opr.) = CpD • VCC • fIN + ICC
PROPAGATION DELAY TIME TEST CONDITIONS
TEST NO.
UNIT
FROM (INPUT)
TO (OUTPUT)
TEST CONDITIONS
(1)
Cn
Cn+4
(2)
Any A or B
Cn+4
M=GND, SO=S3=VCC, Sl=S2=GND (SUM mode)
(3)
Any
A or B
Cn+4
M=GND, SO=S3=GND, SI=S2=VCC (DIFF mode)
AnyF
M=GND
(4)
(SUM or DIFF mode)
(5)
Any A or 13
(6)
Any
(7)
Any A or 13
(8)
Any
(9)
Ai or Bi
M=GND, SO=S3=VCC, SI=S2=GND (SUM mode)
(10)
Ai or Bi
M=GND, SO=S3=GND, SI=S2=VCC (DIFF mode)
(11)
Ai or Bi
M=Vcc (Logic mode)
(12)
Any A or 13
M=GND, SO=S3=VCC, SI=S2=GND (SUM mode)
A or B
M=GND, SO=S3=GND, SI=S2=VCC (DIFF mode)
M=GND, SO=S3=VCC, SI=S2=GND (SUM mode)
A or B
M=GND, SO=S3=GND, Sl=S2=VCC (DIFF mode)
A=B
M=GND, SO=S3=GND, Sl=S2=VC C (DIFF mode)
HC-368
TC74HC181P
ICC(opr.) TEST CIRCUIT
BO
INPUT CONDITION
OUTPUT OPEN
Cl
o
U)
AO ,Al,A2, A3,SO, 53 ,Cn=VDD
* INPUT
Bl, B2, 53, Sl, S2, M- GND
WAVEFORM IS THE BAME AS THAT
I N CAS E OF SWITCHING CHARACTER 1ST ICS
TEST.
SWITCHING CHARACTERISTICS TEST WAVEFORM
6ns
6ns
INPUT
OUTPUT
(AT POSITIVE PULSE)
OUTPUT
(AT NEGATIVE PULSE)
He-36g
TC74HC182AP/AF------LOOK AHEAD CARRY LOGIC
The TC74HCl82A is a high speed CMOS FUNCTION
LOOK AHEAD CARRY GENERA TOR fabricated with
silicon gate C' MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
These circuits are capable of anticipating a carry across
four binary adders or group of adders. They are cascadable
to perform full look-ahead across n-bit adders. Carry,
generate-carry, and propagate-carry functions are provided
as shown in the pin designation table.
When used in conjunction with the HCl8lA arithmetic
logic unit, these generators provide high-speed carry look
-ahead capability for any word length. Each HC182A
generates the look-ahead (anticipated carry)across a
group of four ALU's and, in addition, other carry lookahead circuits may be employed to anticipate carry across
sections of four look-ahead packages up to n-bits. The
method of cascading circuits to perform multi-level lookahead is illustrat-Jd under typical application data.
Carry input and output of the ALU's are in their true
form, and the carry pr~pagate(P) and carry generate(G)
are in negated form; therefore, the carry functions(inputs,
output, generate, and propagate) of the look-ahead
gen~rators are implemented in the compatible forms for
direct connection to the ALU. Reinterpretation of carry
functions as explained on the HCl81A data sheet are also
applicable to and compatible with the look-ahead generator.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
G1
P1
GO
PO
G3
P3
1
2
3
4
5
6
p
7
16
15
14
13
12
11
10
GND 8
9
(TOP VIEW)
FEATURES:
• High Speed .............................. tpd=14ns(Typ.)at Vcc=5V
• Low Power pissipation ............ Iee =4/LA(Max.)at Ta=25"C
• High Noise Immunity··· .... ········ VNIH =V:-';IL2896 Vee (Min.)
• Output Drive Capability···· ........ 10 LSTTL Loads
• Symmetrical Output Impedance ··'1 IOH 1=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH '" tpl-lL
• Wide Operating Voltage Range ... Vee ( opr. ) =2V -6V
• Pin and Function Compatible with 74LS182
HC-370
Vee
P2
G2
Cn
Cn+x
Cn+y
G
Cn+z
TC74HC182API AF
Pin Designation
Active" L"
GO,G1,G2,G3
PO,P1,P2.P3
Cn
Cn+z,Cn+y
Cn+z
Active" H"
GO,G1,G2,G3
PO,P1,P2,P3
Cn
Cntx,Cn+y
Cn+z
Y
X
G
P
Function
Pin No.
3,1. 14,5 Carry Generate Inputs
4,2, 15, 6 Carry Propagate Inputs
13
Carry Input
12, 11 , 9
10
7
16
8
Vcc
GND
Ce rry Outputs
Ca rry Generate Output
Carry Propagate Output
Sup~ll': Voltage
Ground
TRUTH TABLE
FOR
G OUTPUT
FOR
INPUTS
OUTPUT
G
G3
G2
G1
GO
P3
P2
P1
L
X
X
X
X
X
X
L
X
L
X
X
L
X
X
L
X
X
L
X
L
L
X
L
X
X
X
L
L
L
L
L
INPUTS
P3
L
OUTPUT
I P2 I P1 I
IL I L I
PO
L
All other combinations
P
L
H
H
All other combinations
FOR Cn+x OUTPUT
FOR Cn+z OUTPUT
INPUTS
OUTPUT
G2
G1
GO
P2
P1
PO
Cn
Cn+z
H
L
X
X
X
X
X
X
L
X
L
X
X
X
X
X
L
L
L
X
X
X
X
X
L
L
L
H
X
P OUTPUT
FOR Cn+y OUTPUT
INPUTS
OUTPUT
GO
P1
PO
OUTPUT
PO
Cn
Cn+x
H
L
X
X
H
H
X
L
H
H
H
All other combinations
L
L
All other combinations
G1
INPUTS
GO
Cn
Cn+y
Cn+x=GO+POCn
Cn+y=G1+P1GO+P1POCn
Cn+z=G2+P2G1+P2P1GO+P2P1POCn
G-G3+P3G2+P3P2G1+P3P2P1GO
P-P3P2P1PO
L
X
X
X
X
H
X
L
L
X
X
H
or
X
X
L
L
H
H
Cn+x- YO( XO+Cn)
Cn+y- Y1[X1+YO(XO+Cn)]
Cn+z-Y2(X2+Y1[X1+YO(XO+Cn)]}
Y=Y3( X3+ Y2)( X3+ X2+ Y1) (X3+ X2+ X 1+YO)
X=X3+X2+X1+XO
All other combinations
X:Don't care
L
HC-371
TC74HC182AP/AF - - - - - -.....--------~
IEC LOGIC SYMBOL
CPG
CPG
COO
(12) Cn+x
COl
(l1)Cn+y
C02
(9) Cn+z
Cn (13)
Zl
1,2 >1
3
1,2.4 >1
3,4
6
1,2,4,6 >1
3,4,6
6,6
7
10,4,6,8
(12)
(11)
Cn+x
Cn+y
(9) Cn+z
(7)
is
(10)(;
lOGIC DIAGRAM
P
iii
Pi
10
G
Gi
Pi
Gi
Cn+z
Pi
Cn+y
Cn
HC-372
- - - - - - - - - - - - - - - - TC74HC182AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
VOLT
11K
10K
IOLT
lee
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vcc+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)*/180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-40·C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vee
0- Vee
-40 - 85
0- 1000(Vee=2.0V)
0- 500(Vcc =4.5V)
o - 400(Vee=6.0V)
SYMBOL
Vee
VI:>!
VOUT
Topr
tr , tc
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vm
Low-Level
Output Voltage
Va.
Input Leakage Current
IQuiescent Supply Current
Ill..:
lee
TEST CONDITION
VI!, =
VIHorVIL
VI:,\=
VIHorVIL
Ia-J =-20.u A
1m --4 rnA
1m =-5.2mA
Ia. =20
.u A
Ia. -4 rnA
Ia. =5.2mA
VI:\ =Vee orGND
VI:\ =Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2;0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-373
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.18
4.13
4.31
5.68
5.80
5.63
0.1
0.0
0.1
0.0
0.1
0.1
V
0.0
0.1
0.1
0.26
0.33
O. 17
0.26
0.18
0.33
+0.1
+1.0
.u A
4.0
40.0
MIN.
1.5
3.15
4.2
TC74HC182AP/AF---------------------------------
AC ELECTRICAL CHARACTERISTICS(CL =15pF.Vcc=5V.Ta=25"C)
SYMBOL
PARAMETER
TEST CONDITION
MIN.
TYP.
MAX.
Output Transition Time
tTLH
tTIiL
-
4
8
Propagation Delay Time
(~O.~.~2 _ cn+x.Cn+y)
PO. Pl. P2.
Cn+z
tpLH
tpHt
-
14
24
( ~,G 1~2,G3 _ G )
Pl.P2,P3
tpl.H
tpHl.
-
16
21.
Propagation Delay Time
(PO,Pl,P2,P3-P)
tpl.1I
tpHt
-
14
24
Pr:;opagation Delay Time
(Cn-Cn+x,Cn+y,Cn+z)
tpl.H
tplit
-
14
24
Propa~tion_Delay
Time
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L=50pF.lnput t r =t,=6ns)
Ta-25"C
Ta--40 -85"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vee MIN. TYP. MAX. MIN. MAX,
30
15
95
2.0
tTtH
Output Transition Time
8
4.5
15
19
tmt
6.0
1
13
16
Propagation Delay Time
62
135
110
2.0
tpl.H
11
(GO,Gl,G2_ Cn+x,Cn+y)
4.5
21
34
tpHL
PO,Pl,P2 Cn+z
6.0
13
23
29
Propagation Delay Time
12
150
190
2.0
tpl.H
19
ns
4.5
30
38
(GO,Gl,G2,G3 _
tpHL
Pl,P2,P3
6.0
14
26
33
62
110
135
2,0
Propagation Delay Time
tpl.H
17
21
34
4.5
(PO,Pl,P2,P3-P)
tpHL
13
6.0
29
23
62
135
110
2.0
Propagation Delay Time
tpl.1I
11
34
4.5
21
(Cn-Cn+x,Cn+y,Cn+z)
tpHt
6.0
13
29
23
Input Capacitance
CI:,
5
10
10
pF
. Power Dissipation Capacitance CpDW
61
Note (1) C PD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iccq,o=C PD' Va;. f I~ +1 ex:
G)
HC-374
TC74HC182API AF
TYPICAL
APPLICATION
/r---------------------------------- 111A - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - {
C.
Cn
18ZA
Cn+x
L---------------------__
61
-;Cn
112A
84-BIT ALU. FULL-CARRY LOOK-AHEAD IN THREE LEVELS
HC-375
Cn
18ZA
PI
Cn+y
T,C74HC190API AF ___________
TC74HC191 AP/AF
TC74HC190AP/AF BCD UP/DOWN COUNTER
TC74HC191AP/AF 4-BIT BINARY UP/DOWN COUNTER
The TC74HCI90A and TC74HC191A are high speed
CMOS 4-BIT UP/DOWN COUNTERs fabricated with
silicon gate c2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HC190A is BCD up/down counter and the
TC74HC191A is 4-bit binary up/down counter.
They have an asynchronous load input (LOAD) which is
active low.
The direction of counting is determined by the level of
DOWN/UP. When D/U is low, the counter counts up;
when D/U is high, it counts down. Counting occurs on the
positive going transition of the clock input.
Enable input (ENABLE) and two carry inputs
(RIPPLE CLOCK OUT, MAX/MIN) are provided to
permit easy cascading of the counters, which facilitates
easy implementation of N-bit counters without using
external gates.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. f\'l-\X=48MHz(Typ.)at Vcr,=5V
• Low Power Dissipation ............ Icc =4.uA(Max.)at Ta=25"C
• High Noise Immunity .... · .......... Y,\IH=V:,\IL=2896 Vcr,(Min.)
• Output Drive Capability'" .. , ...... 10 LSTTL Loads
• Symmetrical Output Impedance ... I Ion I =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH" tpHL
• Wide Operating Voltage Range ... Vcr, (opr)=2V-6V
• Pin and Function Compatible with 74LS190/191
1
P(DIPI6-P-300A)
16~
F(SOPI6-P-300)
PIN ASSIGNMENT
B
16 Vee
Os
2
15
OA
3
14
ENABLE 4
DOWN/UP 5
12 M~f/MIN
Oc
OD
~
6
7
10
C
GND 8
9
0
11 LOAD
(TOP VIEW)
IEC LOGIC SYMBOL
TC74HC191A
TC74HC190A
(12)
MAXIMIN
(3 )
(2)
(4
(8)
(1)
(2)
(2)OA
(6)OB
(7) Oc
(8)
aD
HC-376
A
CLOCK
13 RIPPLE
TC74HC190API AF
TC74HC191 API AF
TRUTH TABLE
INPUTS
ENABLE
DIU
LOAD
L
H
H
H
H
X
X
L
L
H
L
H
X
X
X
OUTPUTS
CLOCK
OA
X
a
I OB I OC I OD
I b I c I d
UP COUNT
DOWN COUNT
NO CHANGE
NO CHANGE
L
FUNCTION
PRESET DATA
UP COUNT
DOWN COUNT
NO COUNT
NO COUNT
NOTE X:DON'T CARE
a-d:lnputs Level of A-D
TIMING
CHARJ(TC74HC190~)
7
890
12
2
2
o
LOAD
DATA [ :
INPUTS
:
DON'T CARE UNTIL LOAD GOES"L"
CLOCK
DOWNIUP
ENABLE
OA
OB
OC
OD
MAXIMIN
RIPPLE
CLOCK
HC-377
9
8
7
TC74HC190AP I AF
TC74HC191 API AF - - - - - - - - - - - - - - - - -...........................==="""""
TIMING
CHART(TC74HC191A)
13
LOAD
-
I:
s
DATA
INPUTS
:
S
s
CLOCK
-
14
15
0
I
---- t:
-
i--
~
2
2
1
0
15
14
13
I
T I
DON'T CARE UNTIL LOAD GOES"L"
~
I
I-
DOWN/UP
1 2
I I
I
fl-JlSl-f1...f tuu L l.Jl...IlSLf1I
ENABLE
OA
OB
OC
OD
MAX/MIN
RIPPLE
CLOCK
--
I--
I--
--.
---- I----
I--
I--
f--
~
f-~
f--
f--
---
-------
t--
;
~
I--
L
He-37B
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC190AP/AF
TC74HC191 API AF
LOGIC DIAGRAM(TC14HC190A)
I~
I~
HC-379
TC74HC190AP/AF _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC191 API AF
LOGIC 01 AGRAM
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___.
TC74HC19.~c.:.A:..<)
::
I~
~
;!:
""0
t)
..J
t)
He-38O
I~
I=>
2;
I~
~
Z
i
X
co:
::;
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC190AP/AF
TC74HC191 API AF
ABSOLUTE MAXIMUM RATINGS
. snmOL I
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
CNIT
V
V
V
rnA
-rnA
rnA
VALUE
-0.5-7
-0.5 -Vec+0.5
-0.5 -Vcc+0.5
±20
±20
±25
±50
500(DIP) */ 180(SOIC)
-65 -150
300
Vee
VI\
VOLT
11K
10K
lOLl'
Icc
~)
Tstg
TL
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-lOmWI'C shall beapplied
until 300m W.
rnP::rnW
"C
°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Vee
VI\
VOLT
Topr
Input Rise and Fall Time
tr ,
I
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o- 1000(Vec=2.0V)
0- 500(Vcc =4.5V)
0- 400(Vee =6.0V)
SYMBOL
tc
I
:
I
I
I
UNIT
V
V
-V
°C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIII
Low-Level
Input Voltage
VII.
II
TEST CONDITION
i
High-Level
Output Voltage
i VI\ =
I VIHorVn.
i
!
!Ial =-20# A
Vee
2.0
4.5
6.0
2. 0
4. 5
6.0
Ta-25°C
Ta--40 -85"C !UNIT
MIN.! TYP. I MAX. MIN. MAX.:
1.5
1.5 I 3.15
-: V
3.15
I 4.2
4.2
0.5 :
i - ! O. 5
, I
1. 35
1. 35 i V
1.8 1
- ! - I 1. 8
I -
I
!: ~ !: :
6. 0
I -
5. 9
!
:
~: ~ Ii =
-
6. 0
I
!: :
! 5. 9
V
I al-- 4 m A 4.5 I 4. 18 I 4.31 I',·
4 13
100 =-5.2mA 6. 0
5. 68 I 5. 80
5. 63
i
I 2. 0
! O. 0 ! o. I
O. 1
I V __
I(x. =20 # A 4.5
; 0.0 i O. 1 ! O. 1
Low-Level
!
1\ - ,
I
6. 0
I o. 0
O. 1 ! O. 1
V
Output Voltage
V"jOrvlI. Illx. -4 rnA 4.5,
I 0.17 O.26! 0.33
i
I lex. =5.2mA 6.0
O. 18: 0.26 i 0.33
~J~np~u_tL_e~~_a~ge~C~WT
__en_t~~I~I'~·~i__.\~TI~'__
-~\'~l~c_o~r~G~N~D__~~6~.0~i______! ____~:~~~0~.~I~i____-+~~~I~.~0 #A
Quiescent Supply Current
Icc i V 1\ - Vcc or G ND
6. 0
-, , 4. 0 , 40. 0
I .
I -
I
I
I -
HC-381
TC74HC190API AF
TC74HC191 API AF - - - - - - - - - - - - - - - - - - - - - - - -
TIMING REQUIREMENTS(lnput t,.=tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
tW(l)
t\\,(H)
Minimum Pulse Width
(LOAD)
tW(L)
Minimum Set-up Time
(ENABLE.D/U)
ts
Minimum Set-up Time
(DATA-LOAD)
ts
Minimum Hold Time
(ENABLE.D/U)
th
Minimum Hold Time
(DATA-LOAD)
th
Minimum Removal Time
Clock Frequency
t rem
f
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6 0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C
TYP.
LIMIT
100
20
17
75
15
13
150
30
26
50
10
9
0
0
0
0
0
0
50
10
9
5
25
29
Ta--40 -85"C
UNIT
LIMIT
125
25
21
95
19
16
190
38
33
65
13
ns
11
0
0
0
0
0
0
65
13
11
4
20
24
MHz
MAX.
UNIT
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tlLH
tTHl
tpLH
teliL
tplJ-l
tpHl
tpLll
tel"IL
tpLH
telil
tpLH
tpHL
tpUl
tJtIL
tpl.H
tail.
tpl.H
tpili.
-
4
8
-
18
31
-
10
20
-
23
42
-
21
35
-
17
30
-
11
17
-
17
31
-
15
27
f~t·\x
27
48
Propagation Delay Time
(CLOCK-Q)
Propagation D~'8'oTime
(CLOCK)
Propagation Delay Time
(CLOCK - MAXIMIN)
Propagation Delay Time
(LOAD-Q)
"
Propagation Delay Time
(DATA-Q)
Pro~~ation De~6ime
(ABLE
iJ
Propagat~n D~ay Time
(D/U-R 0)
Propafjation Delay Time
(DI -MAXIMIN)
Maximum Clock Frequency
TEST CONDITION
HC-382
MIN.
TYP.
ns
MHz
TC74HC190APIAF
- - - - - - - - - - - - - - - - TC74HC191 AP/AF
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =tf=6ns)
Ta 25"C
Ta 40 -85"C
UNIT
PARAMETER
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
30
75
95
2.0
tTLH
Output Transition Time
8
19
15
4.5
tml.
7
6.0
13
16
88
225
180
2.0
Propagation Delay Time
tpUl
22
36
45
4.5
(CLOCK-Q)
tpilL
6.0
19
31
38
52
120
150
2.0
Propagation Delay Time
tpl.H
13
24
30
4.5
(CLOCK-RCO)
tpHL
6.0
11
20
26
108
240
300
2.0
Propagation Delay Time
tplJ-I
27
4.5
48
60
(CLOCK-MAXIMIN)
tpHL
6.0
23
41
51
100
205
255
2.0
Propagation Delay Time
tplJ-l
25
ns
4.5
41
51
(LOAD-Q)
tpHL
22
6.0
35
43
84
175
220
2.0
Propagation Delay Time
tpl.H
21
4.5
35
44
(DATA-Q)
tpi-iL
6.0
18
30
37
56
105
130
2.0
Propagation Delay Time
tpLH
14
21
26
4.5
(ENABLE-RCO)
tpHL
12
6.0
18
22
84
180
225
2.0
Propagation Delay Time
tpLH
21
36
45
4.5
(D/U-RCO)
tpHL
18
6.0
31
38
72
200
160
2.0
Propagation Delay Time
tpLH
18
4.5
32
40
(DIU - MAXIMIN)
tpHL
15
6.0
27
34 !
5
11
4
2.0
Maximum Clock
tpLH
25
20
44
MHz
4.5
Frequency
tpi-lL
52
24
6.0
29
Input Capacitance
10
5
10
CI:\
TC74HC19OA
pF
104
Power Dissipation Capacitance Cpo {1J
TC74HC191A
101
Note(l) CA) is defmed as the value of the mternal equlvalent capacltance whlch IS calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iccq,c=C PD • Vex:. f I:>; +1 ex:
He-3S3
TC74HC192AP I AF
TC74HC193API AFI AFN
TC74HC192AP/AF
SYNCHRONOUS UP/DOWN DECADE COUNTER
TC74HC193AP/AF/AFN SYNCHRONOUS UP/DOWN BINARY COUNTER
The TC74HCI92A/TC74HCI93A are high speed CMOS
SYNCHRONOUS 4-BIT UP/DOWN COUNTER fabricated
with silicon gate C2MOS technology.
They achieve the high. speed operationsirililar to
equivalent LSTTL while ·maintaining the CMOS low power
dissipation.
They have a clear input (CLEAR). a load input
(LOAD). load data inputs (A-D). two clock inputs
(COUNT UP. COUNT DOWN). four count data outputs
(QA-QO). and other outputs (CARRY. BORROW).
CLEAR is active high and forces QA thru Qo outputs low
independent of the other inputs.
CARRY and BORROW outputs are provided in order to
make a cascade connection without external circuitry.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............•............•... CMAX=54MHz(typ.)at Vcr:;=5V
-LOw Power Dissipation ............ Icr:;=4J.tA(Max.)at Ta=25"C
• High Noise Immunity··············· VNIH=VNlL28" Vcr:; (Min.)
- Output Drive Capability············ 10 LSTTL Loads
• Symmetrical Output Impedance "'1 IOH 1=IOL =4mA(Min.)
• Balanced Propagation Delays '" .,. tpUi" tpHL
• Wide Operating Voltage Range ... Vcr:; (opr.)=2V-6V
• Pin and Function Compatible with 74LS1921193
1
P(DIP16-P-300A)
F(SOP16-P-300)
FN (SOL 16-P-150)
PIN ASSIGNMENT
B
16 Vee
as
2
OA
3
15 A
14 CLEAR
13 BORROW
12CARRY
11 LOAD
10 C
88~~l 4
5~UNT
Oc
5
6
00 7
GND 8
9 0
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
TC74HCl92A
INPUTS
TC74HCl93A
COUNT COUNT LOAD CLEAR FUNCTION
UP DOWN
.r
H
H
L
H
H
X
X
HC-384
J
L
X
X
H
H
H
H
L
X
L
L
L
L
L
H
COUNT UP
NO COUNT
COUNT DOWN
NO COUNT
PRESET
RESET
TC7 4HC192AP I AF
- - - - - - - - - - - - - - TC74HC193AP/AF/AFN
TIMING CHART(TC74HC192A}
.,
=
COUNT
CLEAR
LOAD
DATA
INPUT
7
0
~
.J
CJ
DB
00
~
2
3
4
3
2
1
0
8
9
7
6
5
4
2
3
1
"L"
~---
---L it
I
_.
_. -- r--
-.
OC
1
OON'T CARE UNTIL LOAD GOES
~---
,---,..---
0
OA
0
!---!---
BJ
COUNT DOWN
9
~---
['J
COUNT UP
8
11- rL 11-11-11-
L
- r-- - ~ -
-~
~
~
~
t!: rt- "Lr- J: r--n: rt- t!: 1- 0::IL- ):
~
~
- f=
-r-
--
f--
-
-
i
BORROW
~
I
~
I
...
I
I
TIMING CHART(TC74HC193A}
COUNT
.,
F
0
-
CLEAR
LOAD
B
----
L __ •
I!----
OA
OB
OC
DO
CARRY
BORROw
3
4
5
6
5
4
3
2
1
0
F
E
0
C
B
A
9
DON'T CARE
--
UNTIL LOAD GOES
"L"
L._-_-:.-
'L __
~
r-rt.. rL it rL IL "l.
COUNT UP
COUNT DOWN
2
'---
.J
C ...J
o
1
U, ___
A...J
DATA
INPUT
0
_.
- - ~- -
------ -
~
~
-- -
I-- I--
I--
- r-- -
l
I
L
t!: rt.r--IL
- rt. ~
- "l. }: ~2:ILQ: rt. "l.
...- ==
- =r-- - ~
r-- -I
I--
""-
I
He-385
~
TC74HC192API AF
TC74HC193API AFI AFN
o
o
~
...
.....
'"
"..
o
F
"~"
TI r
"
a
:,.0
..
.....
rl
u
...
~a:
10
"'P..T'Y
~ ~
I
.
.....
51
.,10..
-V
o
1"
I
~.
N
o
ID
..:
o
...
Ii!!
k
-a!a:
...
~a:
~
,...
~R[
~~
~
...
ID
nu=
(;
A
o
u
t
4
-V
o
~
10
~
.. u
"'~
~
-1
I Y
f
I~
0
10
0
u
ill',
r-«
-'
0,
L
'-
tu=
A
....-
.......
~
4
",p-.
a:
L.:.J
~
rl
Ir
1::...-
UJ
.tl
'1
~
...
W
He-3S6
w
~
~~
...
...
I~
-
CO)
II
TC74HC192AP/AF
- - - - - - - - - - - - - - TC74HC193AP/AF/AFN
SYSTEM DIAGRAM TC74HC193A
o
o
.....
o
...
..,oL
~':f',o·tl~~
i
..........
0,
iC--I=
1
A.
(.)
o
'"
(.)
S!
o
~a:
...
1
10
~ ~ ~
T
.Joo.
u>p...
I Y
-v
CD
o
...
-
Mia;.
R
I
10
~a:
"'P-
~l~
-v
l
"
....
- Iy
«
o
...
:2
.A.
~
1W-
.A.
o
CD
~
rl
101......
J""
°Ll
f~
.......
.......
~
4
1}
H
W
0
10
0
.(.)
fl)P-
a:
~
r
L..:........
L...J
~
'"
....
Z ...
:::1:::1
8
HC-387
.
u.
1 j~
/.I.J
"
~7
~
~
I~
~
II
TC74HC192APt AF
TC74HC193APt AFt AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DChput Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI:\
VOLT
11K
10K
IOLT
Icc
PD
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
-c
-c
*500m W in the range of Ta=
-40'C- 65"('. From Ta=65'C
to 85'C a derating factor oC
-lOmW/'C shall beapplied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
UNIT
V
V
V
-c
VALUE
'2 - 6
0- Vee
0-: Vee
-40 - 85
o - 1000(Vee =2.0V)
0- 500(Vee =4.5V )
o - 400(Vee=6.0V)
SYMBOL
Vee
VI:\
VOlT
Topr
tr • tr
.ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Low-Level
Output Voltage
Input Leakage Current
Quiescent Supply Current
Vai
VOl
IJ~
Icc
TEST CONDITION
1m =-201l A
VI:\=
VIHorVII• 1m --4 rnA
IaJ =-5.2mA
VI:\=
VIHorVIL
IOl =20 Il A
lex. -4 rnA
Ia. =5.2mA
V I:\ -Vee orGND
VI:\ -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
He-388
MIN.
Ta-25-c
Ta- 40 -85-c UNIT
TYP. MAX. MIN. I MAX.
1.5
3.15
4.2
-
l. 5
3.15
4.2
-
0.5
l. 35
l.8
-
-
-
-
l.9
4.4
5.9
4.18
5.68
2.0
4.5
6.0
4.31
5.80
0.0
0.0
0.0
0.17
0.18
-
-
-
-
-
-
j
-
-
-
0.1
0.1
0.1
0.26
0.26
+0.1 !
4.0
-
I
I -
-
0.5
l. 35
l.8
l.9
4.4
5.9
4.13
5.63
-
-
-
0.1
0.1
0.1
0.33
iI 0.33
+l.0
! 40.0
V
V
V
V
Il A
TC74HC192APIAF
- - - - - - - - - - - - - - TC74HC193AP/AF/AFN
TIMING REQUIREMENTS(lnput t r-tf=6ns)
PARAMETER
SYMBOL TEST
Minimum Pulse Width
(CLOCK)
tW(li)
tW(J,)
Minimum Pulse Width
(LOAD)
tW(L)
Minimum Hold Time
(CLEAR)
tWOi)
Minimum Set-up Time
(DATA-LOAD)
ts
Minimum Hold Time
(DATA-LOAD)
th
Minimum Removal Time
(LOAD)
trem
Minimum Removal Time
(CLEAR)
trem
Clock Frequency
£
CO~DITIO~
Va:
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
He-38g
Ta 25"C
TYP.
LIMIT
-
-
-
100
20
17
75
15
13
100
20
17
75
15
13
0
0
0
50
10
9
50
10
9
5
25
29
'fa
40 -85"C
LIMIT
125
25
21
95
19
16
125
25
21
95
19
16
0
0
0
65
13
10
65
13
U~IT
ns
10
4
20
24
MHz
TC74HC192AP/AF,
TC74HC193AP/AF/AFN
;
.,'
AC ELECTRICAL CHARACTERISTICS(C L =15pF, Vcc =5V,Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tlLH
t11iL
-
6
12
Propagation Delay Time
(UP ,DOWN -Q)
tpLH
tpi-lL
-
16
33
Propagation Delay Time
(UP-CARRY)
tpLH
tpI-fL
-
10
22
Propagation Delay Time
(DOWN-BORROW)
tpLH
tpI-fL
-
10
22
Propagation Delay Time
(LOAD-Q)
tpl,l-!
tpi-lL
-
21
38
Propagation Delay Time
(LOAD-CARRY)
tpl,l-!
tpI-fL
-
25
44
Propagation Delay Time
(LOAD-BORROW)
tpLH
tpi-lL
-
26
44
Propagation Delay Time
(DATA IN-Q)
tpLH
tpi-lL
-
21
33
Propagation Delay Time
(DAT A IN-CARRY)
tpLH
tpHL
-
29
44
Propagation Delay Time
(DATA IN-BORROW)
tpU-j
tpi-lL
-
26
44
Propagation Delay Time
(CLEAR-Q)
tpI-fL
-
25
39
Propagation Delay Time
(CLEAR-CARRY)
tpLH
-
30
44
Propagation Delay Time
(CLEAR-BORROW)
tpI-fL
-
30
44
~aximum
f~1AX
27
52
-
Clock Frequency
TEST CONDITION
.
He-3g0
MIN.
TYP.
MAX.
UNIT
ns
MHz
TC74HC192APIAF
- - - - - - - - - - - - - - TC74HC193AP/AF/AFN
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =t,=6ns)
Ta 25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
30
75
95
tTLH
Output Transition Time
8
15
19
tTHL
7
13
16
65
190
240
Propagation Delay Time
tpLH .
20
38
48
tpHL
(UP,DOWN-Q)
16
32
41
40
130
165
Propagation Delay Time
tpLH
26
13
33
(UP-CARRY)
tpHL
22
28
11
40
130
165
Propagation Delay Time
tpLH
13
26
33
(DOWN-BORROW)
tpHL
22
28
11
220
275
85
Propagation Delay Time
tpLH
25
44
55
(LOAD-Q)
tpHL
20
37
47
110
250
315
Propagation Delay Time
tpLH
50
30
63
(LOAD-CARRY)
tpHL
25
43
54
250
110
315
Propagation Delay Time
tpLH
ns
30
50
63
(LOAD-BORROW)
tpHL
25
43
54
190
240
80
Propagation Delay Time
tpLH
25
38
48
(DATA IN-Q)
tpliL
20
32
41
120
250
315
Propagation Delay Time
tpLH
34
50
63
(DATA IN-CARRY)
tpHL
28
43
54
110
250
315
Propagation Delay Time
tpLH
31
50
63
(DATA IN-BORROW)
tpHL
25
43
54
100
225
280
Propagation Delay Time
30
45
56
tpHL
(CLEAR-Q)
25
38
48
120
250
315
Propagation Delay Time
35
50
tpLH
63
(CLEAR-CARRY)
29
43
54
250
120
315
Propagation Delay Time
35
50
63
tpHL
(CLEAR-BORROW)
29
43
54
5
4
12
- MHz
Maximum Clock Frequency
25
20
48
fMAX
29
24
55
Input Capacitance
CIN
5
10
10
TC74HC192A
pF
68
Power Dissipation Capacitance
CPD (1)
TC74HC193A
67
Note(1) Cfl) IS defmed as the value of the Internal equIvalent capacItance whIch is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icr; q,o=C PD • V0:;. f 1:\ + I 0::
PARAMETER
SYMBOL TEST CONDITION
Vcr;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
HC-391
MIN.
TC74HC194AP/AF-----4-BIT PIPO SHIFT REGISTER
The TC74HC194A is a high speed CMOS BIDIRECTIONAL
SHIFT REGISTER fablicated with silicon gate C 2 MOS
technology .
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It consists of a parallel in,parallel out 4 bit register with
SHIFT RIGHT and SHIFT LEFT input. In the parallel
mode, data bits A-D are shifted into the internal flipflops on the positive transition of CLOCK.
SHIFT RIGHT and SHIFT LEFT inputs are inhibited
during parallel. operating mode. In the shift right(shift
left)mode, data from SHIFT RIGHT(SHIFT LEFT)input
is shifted to the right(left)by 1 bit, synchronously with the
positive transition of CLOCK.
/< direct CLEAR input overrides all other inputs,
including CLOCK, and sets all flip-flops to low.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. f\IA.,\=70MHz(typ.)at Va;=-5V
• Low Power Dissipation .......•.... Icc=4J.tA(Max.)at Ta=25"C
• High Noise Immunity··············· Y,\lIl=V:\IL =28% Va;(Min.)
• Output Drive Capability'" ......... 10 LSTTL Loads
• Symmetrical Output Impedance ... \ lOll I =1 01 • =4mA(Min.)
• Balanced Propagation Delays ...... tpU I"" tpHL
• Wide Operating Voltage Range ... Vee (opr)=2V -6V
• Pin and Function Compatible with 74LS194
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
SRG4
O}M.Q.
3
C4
1+/2+
SR
A
8
C
0
SL
1,40
340
40
340
3.40
240
HC-392
~I~~i
2
3
150A
A
B
4
130C
C
5
120D
1408
11 CLOCK
10 S 1
9 SO
(TOP VIEW)
R
I
16 Vee
D 6
SHIFT
LEFT 7
GND 8
IEC LOGIC SYMBOL
CLR
SO
SI
CK
CLEAR 1
OA
08
OC
00
- - - - - - - - - - - - - - - - TC74HC194AP/AF
TRUTH TABLE
--CLEAR
L
H
H
H
H
H
H
H
MODE
S1
SO
X
X
H
L
L
H
H
L
X
X
H
H
H
L
L
L
INPUTS
SERIAL
CLOCK
SL SR
X
L-1
-1
-1
-1
-1
X'
X
X
X
X
X
H
L
X
X
X
X
H
L
X
X
X
OUTPUTS
PARALLEL
D
A
B
C
QA
QB
QC
QD
X
X
a
X
X
X
X
X
L
QAo
a
H
L
QBn
QBn
QAo
L
QBo
b
QAn
QAn
QCn
QCn
QBo
L
QCo
c
QBn
QBn
QDn
QDn
QCo
L
QDo
d
QCn
QCn
H
L
QDo
X
X
b
X
X
X
X
X
X
X
c
X
X
X
X
X
X
X
d
X
X
X
X
X
X:Don't Care
a-d:The level of steady state input voltage at input A-D respectively.
QAo-QDo:No change.
QAn-QDn:The level of QA, QB, QC, QD, respectively, before the most-recent positive transition
of the clock.
TIMING CHART
CLOCK
MODE
{ SO
CONTROL
INPUTS
Sl
CLEAR
SERIAL
DATA
INPUTS
fR
SL
A
PARALLEL
DATA
INPUTS
B
C
0
OA
OB
OUTPUTS
00
CLEAR LOAD
SHIFT LEFT
SHIFT RIGHT
HC-393
INHIBIT
CLEAR
TC74HC194AP/AF - - - - - - - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Supply Voltage Range
Va;
DC Input Voltage
VIN
DC Output Voltage
VOL']"
Input Diode Current
11K
Output Diode Current
10K
DC Output Current
lOLl'
DC Vee/Ground Current
Ia;
Power Dissipation
~)
Storage Temperature
Tstg
Lead Temperature lOsec
TL
VALUE
-0.5 -7
-0.5 -Va;+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(SOIC)
-65 -150
300
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vee
0- Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
SYMBOL
Vee
VI\"
VOLT
Topr
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
V"l
Low-Level
Input Voltage
VII.
High-Level
Output Voltage
V()-l
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
I I\"
Icc
TEST CONDITION
VI:'II=
V"-lorVIL
VI\"=
V"lorVn.
Iat =-201L A
I at - 4 mA
I(ll =-5. ~mA
l(x. =20 ILA
lex. -4 mA
l(l. =;5.2mA
VI\" -Vee or GND
VI\" -V(;C or GND
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-394
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.18
4.31
4.13
5.63
5.68
5.80
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
O. 1
0.0
0.17
0.33
0.26
0.33
0.26
O. 18
±1.0
±0.1
ILA
40.0
4.0
MIN.
1.5
3.15
4.2
- - - - - - - - - - - - - - - - TC74HC194AP/AF
SYSTEM
DIAGRAM
SR
C
B
A
2
D
6
SL
7
CLOCK~1~1f.X~-Uo--------4--+-~-----4--+--1-----4--+-~----~
CLEAR ---', ..........--':>0------------4-__+-______-4-__+-______-+..__+-______--'
14
15
OA
OB
HC-395
TC74HC194AP/AF - - - - - - - - - - - - - - - - - - -
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
tW(L)
tW(H)
Minimum.Pulse Width
(CLEAR)'
tW(Ll
Minimum Set-up Time
(SI,PI)
t8
Minimum Set-up Time
(SO,SI)
t8
Minimum Hold Time
tb
Minimum Removal Time
Clock Frequency
trem
f
Vex;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta--40 ......85"C
UNIT
LIMIT
95
19
16
95
19
16
95
ns
19
16
95
19
16
0
0
0
5
5
5
5
MHz
25
30
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
75
15
13
75
15
13
0
0
0
5
5
5
6
31
37
AC ELECTRICAL CHARACTERISTICS(C L =15pF,Vcc =5V,Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTI-IL
tpLH
tDHL
-
4
8
-
12
18
tpHL
-
14
21
fMAX
34
70
-
Propagation Delay Time
(CLOCK-Q)
Propagation Delay Time
(CLEAR Q)
Maximum Clock Frequency
TEST CONDITION
HC-396
MIN.
TYP.
MAX.
UNIT
ns
MHz
TC74HC194APIAF
AC ELECTRICAL CHARACTERISTICS{CL =50pF.lnput t r =tf=6ns)
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
30
75
95
tTLH
Output Transition Time
8
15
19
tlllL
7
16
13
48
115
145
Propagation Delay Time
tpLll
ns
23
29
15
(CLOCK-Q)
tpilL
13
20
25
52
125
155
Propagation Delay Time
25
31
17
tpilL
(CLEAR-Q)
15
21
26
5
6
18
Maximum Clock
- MHz
31
25
64
fMAX
Frequency
37
30
77
Input Capacitance
CIl\;
5
10
10
pF
Power Dissipation Capacitance Cpo(l)
87
Note (1) C PI) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lee QlI}=C PO • Va.:. f 1:\ +I a.:
PARAMETER
SYMBOL TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
HC-397
MIN.
TC74HC195APIAF-----4-BIT PIPO SHIFT REGISTER
The TC74HC195A is a high speed CMOS 4-BIT SHIFT
REGISTER fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power
dissipation.
The HC195A consists of parallel inputs, parallel outputs,
two serial inputs (J,K), and a SHIFT/LOAD input to
control the device. When S/L is held low, the parallel data
inputs are enabled, synchronous loading occurs and these
data appear at the outputs on the next positive going edge
of CLOCK.
When SiL is held high, the serial data inputs are
enabled, and the four flip-flops perform serial shifting on
the positive going edge of each clock pulse.
The CLEAR input overrides all other inputs, including
the clock, and sets all flip-flops low.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
16~
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
CLEAR 1
16 Vee
J
2
15 aA
K
3
14 aB
A
B
4
13 ac
12 aD
c
5
6
0
7
10 CLOCK
GND 8
9 SHIFTI
FEATURES:
• High Speed .............................. ~\1Ax=68MHz(Typ.)at Vee=5V
• Low' Power Dissipation ............ Iee=4IlA(Max.)at Ta=25"C
• High ~oise Immunity .............. · VNIH=V:-;n.28% Vee (Min.)
• Output Drive Capability .. · ........ · 10 LSTTL Loads
• Symmetrical Output Impedance "'1 IOH 1=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range'" Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS195
LOAD
(TOP VIEW)
IE.C LOGIC SYMBOL
CUi
1
SRG4
SIt
CK
J
K
A
aA
aB
B
C
ac
o
aD
aD
He-39B
11 aD
- - - - - - - - - - - - - - - - TC74HC195AP/AF
TRUTH TABLE
INPUTS
OUTPUTS
SERIAL PARALLEL
SHIFT!
CLEAR
CLOCK
aA
aB
ac aD aD
J K A B C 0
LOAD
L
X
L
X
X X X X X X
L
L
L
H
H
d
-r X X a b c d a
b
c
d
L
H
X
X X X X X X aAO aBO aco aco aDO
- r L H X X X X aAn aAn aBn aCn aCn
H
H
- r L L X X X X L aAn aBn aCn aCn
H
H
.-r- H H X X X X H aAn aBn aCn aCn
H
H
.-r- H L X X X X aAn aAn aBn aCn aCn
H
H
X : Don't care
OAO-ADO : No change
QAn-ODn : The level of OA, OS, OC, respectively, before the most-recent positive
transition of the clock.
a . . . d, d: The level of steady state input voltage at inputs A-D respectively.
---
TIMING CHART
LJ
SHIFT I
LOAD
c--
-.J
J
I--
A
B
C
I-
r-
_U
J Ir--
D
OA -
OB OC -
-l
-
r iL-JL
.ILJ" I
JLJ l
iL---JL
r
I
OD -
FUNCTION
r-h
-
!CLEAJ LOAD
(FIRST STAGE)
SHIFT
i
(RESET)
(SET)
HC-399
~ I-
-+14
I
(TOGGLE)
(NO CHANGE)
TC74HC195AP/AF--------------------------------
SYSTEM DIAGRAM
A
---Oo-------4r--._
B---I:>O--++-+--r""o
--I :>0--00-- OC
C - - - I ::>0--++4--r....
"»--00
0----1"»-+-1--1-_.........
:::>0--1:>0---00
CLOCK ---'"'-.
,.)Io--+-H-------.J
SHIFT/LOAD
HC-400
...............-
.......- - - - - - - - - - - - - TC74HC195AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
-DC Va;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Va;
VI:\
VOLT
11K
10K
IOLT
lee
PD
Tstg
TL
VALUE
-0.5 ~ 7
-0.5 -Vcc+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta =
-40"C- 65"C. From Ta=65°C
to 85°C a derating factor of
-IOmWrC shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Input Rise and Fan Time
t r • tr'l
Vee
VI:\
VOLT
Topr
VALUE
2-6
0- Vee
0- Vee
-40 - 85
0- 1000(Vee =2.0 V )
0- 500(Vcc =4.5V)
o- 400(Vee=6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIII
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
1m =-20tl A 4.5
VI:\ =
6.0
VII I orVIL
Ial --4 rnA 4.5
1m =-5. 2mA 6.0
2.0
Ia. =20 tl A 4.5
VI:\=
6.0 I
Vll1orV1L
Ia. -4 rnA 4.5 ,
Ia. =5.2mA 6.0
6.0 i
V 1:\ -Vee or GND
V I:\ -Vee or GND
6.0 i
I
Low-Level
Output Voltage
Va.
Input Leakage Current
Quiescent Supply Current
11:\
Icc
HC-401
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
I 1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.5 1. 4.4
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.0
0.1
0.1
0.1
0.0
0.1
V
0.1
0.0
O. 1
0.33
0.17 I 0.26
0.18 i; 0.26
0.33
- ; ±0.1
"':"'1. 0 '
A
40.0 tl
l 4.0
MIN.
1.5
3.15
4.2
I
TC74HC195AP/AF - - - - - - - - - - - - - - - -
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
tW(L)
tWO-I)
Minimum Pulse Width
(CLEAR)
tW(L)
Minimum Set-up Time
(A,B,C,D)
ts
Minimum Set-up Time
(J, K. S/L)
ts
Minimum Hold Time
th
Minimum Removal Time
Clock Frequency
trem
f
Voc
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
95
19
16
ns
95
19
16
0
0
0
5
5
5
6
MHz
30
35
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
75
15
13
75
15
13
0
0
0
5
5
-.
5
7
38
45
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
SYMBOL
MIN.
TYP.
Output Transition Time
t l1•H
tlllL
tpLH
tPHL
tpLH
tcHl
-
4
8
-
13
21
-
14
21
fMAX
41
68
Propagation Delay Time
(CLOCK -Qn, QDJ
ProCaFtion Delay Time
( L AR-Qn,"QD)
Maximum Clock Frequency
TEST CONDITION
HC-402
MAX.
UNIT
ns
MHz
TC74HC195API AF
AC ELECTRICAL CHARACTERISTICS(C L =50pF,IJ1put t r =tf=6ns)
Ta"": 40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
30
75
95
2.0
tTLH
Output Transition Time
8
15
19
4.5
tTHL
6.0
7
13
16
47
125
155
2.0
Propagation Delay Time
tpUl
n5
16
25
31
4.5
(CLOCK-Q)
tpHL
6.0
21
26
13
125
49
155
2.0
Propagation Delay Time
25
4.5
17
31
tpHL
(CLEAR-Q)
6.0
21
26
14
7
6
15
2.0
Maximum Clock
38
30
MHz
4.5
60
f~1AX
Frequency
6.0
45
35
75
C[,
Input Capacitance
5
10
10
pF
Power Dissipation Capacitance
CPD(ll
76
Note (1) C A) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icc WlMQ.
HC~408
- - - - - - - - - - - - - - TC74HC221 AP/AF/AFN
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VII'
Low-Level
Input Voltage
VII_
High-Level
Output Voltage
(Q,Q)
VOH
Low-Level
Output Voltage
(Q,Q)
VOL
Input Leakage Current
Rx/Cx Terminal
Off-State Current
I Quiescent Supply Curren
Active-State.
Supply Current
I,,,
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
IOH
=-20/L
A
4.5
V,,,=6.0
VII,orVII .
I a -, --4 mA 4.5
la, =-5.2mA 6.0
2.0
IOL =20 /LA 4.5
V,,, =
6.0
VII,orVIl•
IOL -4 mA 4.5
IOL =5.2mA 6.0
V,,, =Vcc orGND
6.0
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.5
4.4
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.80
5.63
5.68
0.0
O. I
O. I
O. I
O. I
0.0
V
0.0
0.1
O. I
0.17
0.26
O. 33
0.26
O. 18
0.33
±1,0
±O.I
MIN.
1.5
3.15
4.2
-
-
±0.1
6.0
2.0
4.5
6 0
-
45
400
O. 7
4.0
200
500
1.0
Vee
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
II"
V\'\ =Vcc or GND
6.0
lee
V,,, -Vee or GND
Icc
V,,, =Vcc or GND
Rx/Cx =0. 5V cc
-
±1,0
/LA
-
40.0
260
650
1.3
/LA
-
/LA
mA
.: per Clrcult
TIMING REQUIREMENTS{lnput tr=t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
tll'(\.)
t\\,(l1)
Minimum Clear Width
tll'(L)
HC-409
Ta--40 -85"C
UNIT
LIMIT
95
19
16
ns
95
19
16
TC74HC221 AP/AF/AFN - - - - - - - - - - - - - -
AC ELECTRICAL CHARACTERISTICS(C L =15pF,Vcc =5V,Ta=25"C)
PARAMETER
Output Transition Time
Propagation Delay Time
(A,B-Q,Q)
P~ation Delay Tim.!.
( LR TRIGGER-Q,Q)
Propagation Delay Time
TCLR-Q,Q)
SYMBOL
TEST CONDITION
tT.1.1I
tTHL
t(1l.11
t llI·n
tpl.1i
tl1llL
tpLlI
t O/IL
MIN.
TYP.
MAX.
-
4
8
-
25
36
-
25
41
-
16
27
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =t,=6ns)
Ta--40 -85"C
Ta-25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
30
75
95
2.0
tTLIi
Output Transition Time
8
19
15
4.5
tTllL
7
6.0
13
16
102
210
265
2.0
Propag~on Del~ Time
tl~.H
30
42
53
4.5
(A,B-Q,Q)
t"'IL
24
6.0
36
45
ns
102
295
235
2.0
Propagation Delay Time
t",.11
30
4.5
47
59
(CLR TRIGGER-Q,Q) tpl-lL
6.0
24
40
50
67
160
200
2.0
Propagation Delay Time
tpLH
20
32
4.5
40
(CLR-Q,Q)
t(1lll.
6.0
16
27
34
700
2000
Cx=28pF
2500
2.0
250
400
Rx=6KQ(Vcc =2V) 4.5
ns
500
210
340
Rx=2KIl(Vcc=4.5V,6V) 6.0
425
90
130
90
130
110
2.0
Cx=O.Ol/.lF
Output Pulse Width
tWQT
95
115
95
105
115
4.5
/.ls
Rx=lOKQ
6.0
105
95
95
115
115
1.0
1.2
0.9
0.9
1.2
2.0
Cx=O.l/.l F
1.0
ms
1.1
0.9
4.5
0.9
1.1
Rx=lOKQ
6.0
1.0
1.1
0.9
0.9
1.1
Output Pulse Width Error.
Between Circuits
%
I1twOL
±1
(In same Packag-e)
Input Capacitance
C!:,
5
10
10
pF
Power Dissipation Capacitance CI'D(l)
174
Note(1) Cln IS defmed as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Icctw=C 1'1) • Va;' f 1:'-: +1 a;' • Duty/lOO+la: 12(per circuit)
(Ia:' : Active Supply Current)
(Duty:%)
HC-410
- - - - - - - - - - - - - - - - TC74HC221AP/AF/AFN
OUTPUT PULSE WIDTH
CONSTANT K-SUPPLY VOLTAGE
(EXTERNAL RESISTOR (Rx)=lOkC; IWOUl =K. Cx. Rx)
...
!Z
C~=O.OI ~IF
1.1
i8
C~.O.I~~
:c
l:i
I
1.0
Cx=1pF
iii
234
SUPPL Y VOLTAGE
6
Vcc(V)
IWQUT- CX CHARACTERISTICS (TYP.)
Vcc=4.5V
CL =50pF
j.-Rx~IMC
•
10
.
V
V
V
V
./
W
Rx~IOOItC
~
I-
V
10'
~
0
~
:c
V
IQ
iii
w
RX·'Ok C /
10
'"::>-'
Rx=lkC
Q.
./
I-
::>
V
Q.
l-
::>
i/
I
C)
10-'
10'
10'
10'
EXTERNAL CAPACITOR Cx (pF)
HC-411
6
(TYPICAL)
3-TO-8 LINE DECODER/LATCH
The TC74HC237 A is a high speed CMOS 3-to-8 LINE
DECODER ADRESS LATCH fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It is composed'of 3-bit input latches with a common
GL enable input and 3-to-8 line decoder with enable
inputs Gl and G2. The 3-bit binary data is stored into the
input latch on the high level of GL. The value of this data
determines which one of outputs will go to low.
When the enable input Gl is held low or G2 is held high,
decoding function is inhibited and all 8 outputs go high.
The two enable inputs are provide to ease cascade
connection and permits the application address decoder
for memory system.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIPI6-P-300A)
16~
F(SOPI6-P-300)
PIN ASSIGNMENT
A
FEATURES:
• High Speed .............................. tJXl=12ns(typ.)at Vee=5V
• Low Power Dissipation ...•........ Iee =4ttA(Max.)at Ta=25"C
• High ~oise Immunity··············· V:\II-1=V:\IL2896 Vee (Min.)
• Output Drive Capability··· ......... 10 LSTTL Loads
• Symmetrical Output Impedance ···1 IOH 1=Ia.. =4mA(Min.)
• Balanced Propagation Delays ...... tpU-l'" tpliL
• Wide Operating Voltage Range ... Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS237
16 Vee
B
2
C
3
14 VI
GL
4
13 V2
G2
5
12 V3
Gl
8
11 V4
V7
1
10 V5
GNO
8
9
15 VO
(TOP VIEW)
IEC LOGIC SYMBOL
(15)
GL
A
8
1
1
2
2
e
4
4
Gl
02
5
EN
•
YO
Yl
Y2
Y3
Y4
YI
GL
VI
02
A
8
e
Gl
Y7
HC-412
YO
Yl
Y2
Y3
Y4
YI
YI
Y7
V8
- - - - - - - - - - - - - - - - TC74HC237AP/AF
TRUTH TABLE
INPUTS
OUTPUTS
ENABLE
SELECT
GL
G2
Gl
C
B
A
YO
Yl
Y2
Y3
Y4
Y5
Y6
Y7
X
X
X
H
L
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
X
Depends upon the address previously applied
while GL was at a low level
H
L
H
X
X
-
I
I
X : Don't Care
SYSTEM DIAGRAM
YO
A
YI
SELECT
Y2
B
Y3
Y4
C
YS
va
Y7
ENABLE
INPUTS
G2
Gt:
~:
HC-413
DATA
OUTPUTS
TC74HC237AP/AF - - - - - - - - - - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
,Lead Temperature 10sec
SYMBOL
Vee
VI;>;
VOlT
11K
10K
IOLT
Icc
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m W/"C shall be applied
until 300m W.
'
,
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Input Rise and Fall Time
tr • tr
VALUE
2-6
0- Vee
0- Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
Vee
VI;>;
Von
Topr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VII 'I
Low-Level
Input Voltage
VIL
High-Level
Output Vciltage
VOH
Low-Level
Output Voltage
VOL
"
Input Leakage Current
Quiescent Supply Current
II;>;
lee
TEST CONDITION
VI;>; =
VII IorVu.
VI;>; =
VlllorVIL
I(ll =-20/.LA
Ial - 4 rnA
l(lj =-5. 2rnA
Ia. =20 /.LA
lot -4 rnA
la. =5.2rnA
VI;>; -Vee or G!'l'D
VI;>; -Vee or GND
,
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-414
Ta-25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.18
4.31
4.13
5.68
5.80
5.63
0.0
0.1
0.1
0.0
O. 1
0.1
V
0.0
0.1
0.1
0.17
0.26
0.33
0.18
0.26
0.33
±0.1
±1.0
/.LA
4.0
40.0
MIN.
1.5
3.15
4.2
- - - - - - - - - - - - - - - - TC74HC237AP/AF
TIMING REQU'IREMENTS(lnput tr=t,=6ns)
,
Ta 25"C
1'a 40 -85"C
PARAMETER
!SYMBOL TEST CO~DlTIOX r--.-;V"-eef--mT""Y"'P'=-.":':'--'=';LnI""'M"'ImT-t-'LnIfi'MTIlmTF--::...;U~IT
i
2.0
4.5
Minimum Set-up Time!
(A.B.C-GL)
6.0
2.0
4.5
6.0
Minimum Hold Time
(A.B.C-GL)
4.5
6.0
Minimum Pulse Width
tW(I.)
(GL)
;
I
-
2.0
;
-
75
15
95
19
13
50
10
9
16
65
13
11
25
5
5
30
5
5
ns
cc
AC ELECTRICAL CHARACTERISTlCS(C L =15pF,V =:5V,Ta=25"C)
PARAMETER
I
; SYMBOL.
TEST CONDITION
MIN.
TYP.
I
MAX.
ILH
I t'tTHL
-
4
8
tiltH
tnHl
Time
tpLH
; tnHL
Time i tpLI-l
I tllHL
Time ! tol.J-I
! tnl-IL
-
12
24
-
12
24
-
17
33
-
15
31
Output Transition Time
UNIT
I
Propagation Delay
(Gl-Y)
Propagation Delay
(G2-Y)
Propagation Delay
(GL-Y)
Propagation Delay
(A.B.C-Y)
Time
i
i
i
ns
AC ELECTRICAL CHARACTERISTlCS(C L =50pF,lnput t r =t,=6ns)
I
1'a-25"C
Ta- 40 -85"C
PARAMETER
U~IT
: SYMBOL TEST CO~DITIOX I Vee
MIN. TYP. MAX. MIN. MAX.
!
!
30
75
95
2.0
tTLlI
Output Transition Time
8
4.5
15
19
t'I'I-IL
6.0
7
13
16
45
140
175
2.0
Propagation Delay Time !,, tPLI-I
,
4.5
28
15
35
(GI-Y)
iI tollL
6.0
13
24
30
,
45
140
175
! 2.0
Propagation Delay Time I tpLIl
ns
4.5
15
28
35
I tl~ II.
(G2-Y)
6.0
24
13
30
65
190
240
2.0
Propagation Delay Time !I tpLli
21
38
48
I tpHt
4.5
(GL-Y)
i
6.0
18
32
41
60
180
225
I 2.0
Propagation Delay Time I tiltH
19
36
1
45
! 4.5
(A.B.C-Y)
I
6.0
I, tpl-lL
16
31
38
Input Capacitance
CI:"\
5
10
10
pF
Power Dissipation Capacitance i Cf'I)(1)
52
Kote (1) C m IS defmed as the value of the mternal eqUivalent capacitance which IS calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
i
I
icCa"'=C I'D· VCC" f 1:"\ +1 CC
HC-415
tC74HC237AP/AF--------------------------------
TYPICAL APPLICATION
STROBE
DECODER
ENABLE
XO
Xl
I
X2
GL
C B A
Gl G2
"
YO Yl Y2 Y3 Y4 Y5 YI Y7
INPUT
ADDRESS
TTT 1
I
TO FIVE
OTHER
DECODERS
X3
X4
,
XS
GL
,
1
I
I
C B A
01 G2
).,
GL
I
I
C B A
Gl G2
YO Yl V2 Y3 V4 YS va V7
YO Yl Y2 Y3 Y4 VS Y8 Y7
I II I I I I I
I I I I I I I I
8 9 10 11 12 13 14 15
01234567
A
I
GL
C B A
YOYI Y2 Y3 Y4 YS
ya Y7
I I I I I I I I
16 17 18 19 20 21 22 23
OUTPUTS
• Line to 64 Line Decoder with Input Address Storage
HC-416
I
Gl G2
------TC74HC238API AF
3-TO-8 LINE DECODER
The TC74HC238A is a high speed CMOS 3-to-8
DECODER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
When the device is enabled,3 Binary Select inputs(A,B
and C)determine which one of the outputs(YO-Y1 ) will go
high.
When enable input G1 is held low or either G2A or G2B
is held high,decoding function is inhibited and all the
outputs go low.
G1,G2A,andG2B inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
16~
1
P(DIPI6-P-300A)
16~
F(SOPI6-P-300)
PIN ASSIGNMENT
FEATURES:
• High Speed .............................. tpd=14ns(Typ.)at Vcc=5V
• Low Power Dissipation ........•... Icc=4IlA(Max.)at Ta=25"C
• High Noise Immunity··············· V"IH =V"IL=28" Vcc{Min.)
• Output Drive Capability'·' '" ...... 10 LSTTL Loads
• Symmetrical OUtput Impedance ···1 100 1=IQI..=4mA(Min.)
• Balanced Propagation Delays······ tpLH .. tpHL
• Wide Operating Voltage Range ... Vcc(opr)=2V-6V
• Pin and Function Compatible with 74LS238
A
B
C
G2A
1
2
16
3
4
G2B
Gl
6
Y7
7
10 Y5
GND
8
9
8
(TOP VIEW)
IEC LOGIC SYMBOL
A
B
C
1)
(2)
(3)
BIN/OCT
1
(1&) YO
2
A
B
C
(14) Yl
(1
(2)
I}
(3)
2'
01 (e)
G2A (4)
G2B (I)
II
e
o
(II) YO
(14) Yl
2
(13) Y2
(12) Y3
12) Y3
(11) Y4
(11) YC'
(10) Y&
EN
~MUX
07
(13) Y2
Y6
01
-
Y7
G2B
e)
4
~2A (I)
HC-417
VCC
15 YO
14 Yl
13 Y2
12 Y3
11 Y4
II
(10) Y6
•
(I)
Y8
Y7
Y8
TC74HC238AP/AF---------------TRUTH
TABLE
INPUTS
ENABLE
OUTPUTS
SELECTED OUTPUT
SELECT
C
B
A
X
X
X
X
X
X
H
X
X
X
X
X
X
H
X
X
X
YO
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
Gl
L
H
H
H
H
H
H
H
G2A G2B
H
L
H
H
L
L
L
H
L
L
L
H
H
L
H
H
L
H
H
H
L
L
L
Yl
L
L
L
L
H
Y2
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
Y3
L
L
L
L
L
L
H
L
L
L
L
Y4
L
L
L
L
L
L
L
H
L
L
L
Y5
L
L
L
L
L
L
L
L
H
L
L
Y8
L
L
L
L
L
L
L
L
L
Y7
L
L
L
L
L
L
L
NONE
NONE
NONE
YO
Yl
Y2
Y3
Y4
Y5
Y8
Y7
L
H
L
L
L
H
X:Don't care
SYSTEM DIAGRAM
Yo
Yl
Y2
Y3
SELECT
INPUTS
Y4
Y6
Y6
ENABLE
INPUTS
{~2A
G2B
Y7
4
5
G1
HC-418
DATA
OUTPUTS
TC74HC238APIAF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
Vr\·
VOLT
11K
10K
IOLT
I(;C
~)
i Tslg
TI.
VALUE
-0.5 -7
-0.5 -Vec+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
rnW
"C
"C
*500m W in the range of Ta=
-40"C- 65·C. From Ta=65·C
to 85·C a derating factor of
-IOmW/"c; shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Vee
VI\
VOLT
I Topr
Input Rise and Fall Time
I tr • tr
SYMBOL
I
!
VALUE
2-6
0- Vee
0- Vee
-40 - 85
0- 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
UNIT
V
V
,
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Ta--40 -85"C
Ta-25"C
UNIT
Vee MIN. TYP. MAX. MIN. MAX.
1.5
i 2.0 1.5 I
VIH I
V
I 4.5
3.15
3.15
4.2 I 4.2
6.0
0.5
2.0
0.5
I
V
4.5
1. 35
1. 35
VII.
6.0
1.8
1.8
I
2.0 I 1.9
2.0
1.9
1011 =-20 tL A 4.5
4.4
4.5
4.4
VI\=
V
5.9 i 6.0
5.9
6.0
VOl I
VlllorVII•
1011 --4 rnA. 4.5
4.18
4.31
4.13
1011 =-5.2mA! 6.0
5.68
5.80
5.63
-.
0.1
0.0
O. I
2.0
. 101. '7'20 tL A 4.5
0.0
0.1
0.1
VI:, =
V
0.0
0.1
6.0 i O. I
VOl.
VlllorVIL
0.17
0.33
0.26
lot. =4 rnA 4.5 I I(~. =5.2mA
0.33
0.26
O. 18
6.0 i ±0.1
±1.0
VI\ -Vee or GND
11\
~ 6.0
A
,
V I\ -Vee or GND
6.0 i 40.0 tL
4.0
lee .
SYMBOL!
TEST CONDITION
I
High-Level
Input Voltage
I
Low-Level
Input Voltage
High-Level
Output Voltage
I
I
I
I
Low-Level
Output Voltage
Input Leakage Current
Quiescent Supply Current
I
I
HC-419
TC74HC238API AF
.
.
AC ELECTRICAL CHARACTERISTICS(Cl =15pF Vcc=5V Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTI.H
tTHI
tpl.H
tpl_11..
tpLH
toll!
Propagation Delay Time
(A,B,C-Y)
Propagation Delay Time
.(G,G-V')
TEST CONDITION
,
MIN.
-
TYP.
I
MAX.
4
8
-
14
26
-
14
26
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput tr=t;=6ns)
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
2.0
30
i5
95
tTLIl
Otltput Transition Time
4.5
8
15
19
tnu_
6.0
7
13
16
ns
, 2.0
190
50
150
Propagation Delay Time
tpLH
4.5
Ii
30
38
(A,B,C-Y)
tpilL
6.0
26
32
15
2.0
50
150
J90
Propagatiol!...Pelay Time
tpLH
4.5
17
30
38
(G,G-Y)
tpilL
6.0
26
32
15
Input Capacitance
, 10
CI\
5
10
pF
Power Dissipation Capacitance CPD(l)
53
Note(l) Cm is defined as the value o£ the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
PARAMETER
la;(~
SYMBOL TEST CONDITION
=c PI)
•
Va;
Va;. £1:\ +la;
HC-420
MIN.
TC74HC240APIAFI AFW
---------- TC74HC241 API AF
TC7 4HC244API AFI AFW
OCTAL BUS BUFFER
TC74HC240API AFI AFW
TC74HC241API AF
TC74HC244API AF/AFW
INVERTED. 3-STATE OUTPUTS
NON-INVERTED. 3-STATE OUTPUTS
NON IN VE RTE D 3-ST A TE 0i-'U,,-T.!..!..P~U~T,-!S~_ _ _ _ _ _ _ _ _---,
The TC74HC240A, 241A and 244A are high speed CMOS
OCTAL BUS BUFFERs fabricated with silicon gate
dMOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The 74HC240A is an inverting 3-state buffer having two
active-low output enables. The TC74HC241A and
TC74HC244A are non-inverting 3-state buffers that differ
'only in that the 241A has one active-high and one activeiow output enable, and the 244A has two active-low output
enables.
These devices are designed to be used with 3-state
memory address drivers, etc.
All inputs are equipped with protection circuits against
static discharge or tansient excess voltage.
FEATURES:
• High Speed .................................
~d=lOns(typ.)
P( DIP20-P-300A)
m~m~
1
F(SOP20-P-300)
TRUTH TABLE
INPUTS
G'"
An
L
H
L
L
H
H
at Vcc;=5V
• Low Power Dissipation ............... Icc;=4ttA(Max.)
a~
1
FW(SOL20-P-300)
G
Ta=25"C
• High Noise Immunity··············· V:\IH=V:\IL=2S'6 Vcc;(Min.)
• Output Drive Capability'" ......... 15 LSTTL Loads
H
• Symmetrical Output Impedance ···1 la-d =1 a.. =6mA(Min.)
• Balanced Propagation Delays ...... tpLH"otpHL
• Wide Operating Voltage Range ... Vcc;(opr)=2V-6V
X
L
H
H
L
Z
Z
e:.
: for TC74HC241A only
~
: for TC74HC240A only
: Don't Care
: High Impedance
X
Z
• Pin and Function Compatible with 74LS240/241/244
L
OUTPUTS
Yn Yn"''''
PIN ASSIGNMENT(TOP VIEW)
1(3
tAl 2
TC74HC244A
TC74HC24tA
TC74HC240A
20 Vee
192(3
1(3
t(3 1
20 Vee
tAt 2
192G
lAl 2
20 Vee
192(3
2Y4 3
18'Yl
2Y4 3
18 tVt
2Y4 3
18 lVl
tA2 4
172A4
tA2 4
172A4
lA2 4
172A4
2V3 5
16 tV2
2V3 5
16 lY2
2V3 5
16 tY2
tA3 6
152A3
tA3 6
152A3
lA3 6
152A3
2V2 7
141V3
2V2 7
14 tY3
2Y2 7
141Y3
tA4 8
132A2
tA4 8
132A2
lA4 8
132A2
2Vt 9
12 tV4
2Vt 9
121Y4
2Yl 9
121V4
GNO 10
11 2At
112Al
GNO 10
11 2Al
HC-421
TC74HC240API AFI AFW
TC74HC241 AP/AF
TC74HC244API AFI AFW
IEC LOGIC SYMBOL
TC74HC240A
2Al (IV
2A2 ll~
2A3 (I~
2A4 (In
TC741tfC244A
TC14HC241A
2Al Oll
2A2 0
» 1----1
Og
2A3
2M
"ii:unnl----I
HC-422
(9) 2Yl
7)
((~~»
2Y2
2Y3
(3) 2Y4,
TC74HC240API AF I AFW
- - - - - - - - - - - - - - T C 7 4 H C 2 4 1 AP/AF
TC74HC244AP I AF I AFW
ABS.O.LUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/GroundCurrent
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL,
Vee
VI:-.i
VOLT
11K
10K
IOLT
lee
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP)*/180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40·C- 65"C. From Ta=65·C
to 85"C a derating factor of
-10m Wf"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vee =2.0V)
0- 500(Vee=4.5V)
o - 400(Vee =6.0V)
SYMBOL
Vee
VI:\
VOl;T
Topr
Input Rise and Fall Time
tr , tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VII.
High-Level
Output Voltage
Low-Level
Output Voltage
3-State Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
TEST CONDITION
i
I
I
Voo
VI:\=
VII-IOrVIL
VI:\=
VIHorVIL
VOL
I~
!
11:\
!
lee
!
100
=-20J.tA
--6 rnA
Iaol =-7.8mA
100
IOL =20 J.tA
lot.. -6 rnA
lot.. =7.8mA
V I:\ -VIII or VII.
VOLT =Vee or GND
VI:\ -Vee or GND
VI:\ -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
MIN.
1.5
3.15
4.2
-
-
-
Ta-25"C
TYP. MAX.
-
-
-
-
-
0.5
1. 35
1.8
-
-
-
Ta-~40
MIN.
1.5
3.15
4.2
-85"C
UNIT
MAX.
-
V
-
0.5
1. 35
1.8
V
1.9
4.4
5.9
4.13
5.63
-
-
-
2.0
4.5
6.0
4.31
5.80
0.0
0.0
0.0
0.17
0.18
0.1
O. 1
0.1
0.26
0.26
-
0.1
0.1
0.1
0.33
0.33
6.0
-
-
±0.5
-
±5.0
6.0
6.0
-
-
±0.1
4.0
-
±1.0
40.0
HC-423
1.9
4.4
5.9
4.18
5.68
-
-
-
-
-
-
V
-
V
J.tA
TC74HC240API AF I AFW
TC74HC241 AP/AF
TC74HC244API AF I AFW
--------------
AC ELECTRICAL CHARACTERISTICS(lnput t r =tf=6ns)
TE::;T
Ta- 40 -85"C
Ta-25"C
UNIT
PARAMETER
SYMBOL
CONDITION CL Va:; MIN. TYP. MAX. MIN. MAX.
2.0
25
60
75
tn.H
Output Transition Time
12
50 4.5
7
15
trnL
6.0
6
10
13
2.0
36
90
115
18
23
50 4.5
12
tpUi
6.0
15
20
10
Propagation Delay Time
2.0
51
130
165
150 4.5
17
26
33
tpHL
28
6.0
14
22
ns
125
2.0
48
155
tpZL
50 4.5
16
25
31
21
26
6.0
14
Output Enable time
R L= 1 kQ
2.0
63
165
205
150 4.5
21
33
41
tpZli
!
28
6.0
18
35
2.0
32
125
155
tpLZ
Output Disable time
RL = 1 kQ
50
4.5
25
15
31
tpliZ
6.0
26
14
21
Input Capacitance
5
10
CI:\
10
Output Capacitance
10
COUT
pF
TC74HC240A
31
Power Dissipation Capacitance Cm(!)
TC74HC241A/244A
33
Note(1) CPD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
I a:;QJIl=C PD • Va:. fl.'\ +Ia: 18(per bit)
I
I
i
HC-424
TC7 4HCT240AP I AF I AFW
----TC74HCT241 AP/AF
TC7 4HCT244AP I AF I AFW
OCTAL BUS BUFFER WITH TTL INPUT LEVEL
TC74HCT240A PI AF I AFW IN VERTE D.3-ST ATE OUTPUTS
TC74HCT241API AF
NON-INVERTED.3-STATE OUTPUTS
TC74HCT244AP/AF/AFW NON-INVERTED.3-STATE OUTPUTS
The TC74HCT240A, HCT241A and HCT244A are high
speed CMOS OCTAL BUS BUFFERs fabricated with
silicon gate C2MOS technoligy.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Their inputs are compatible with TTL, NMOS, and
CMOS output voltage levels.
The TC74HCT240A is an inverting 3-state buffer having
two active-low output enables. The TC74HCT241A and
TC74HCT244A are non-inverting 3-state buffers that
differ only in that the HCT241A has one active-high and
one active-low output enable, and the HCT244A has two
active-low output enables.
These devices are designed to be used with 3-state
memory address drivers,etc.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
~_ _ _ _ _ _ _ _ _ _ _ _~
P(DIP20-P-300A)
F(SOP20-P-300)
FW(SOL20-P-300)
TRUTH TABLE
FEATURES:
• High Speed ................................. t pd=13ns(typ.)at Vcc=5V
• Low Power Dissipation ............... Icc =4.uA(Max.)at Ta=25"C
• Compatible with TTL outputs ...... VIL =O.8V(Max.),VIII =2.0V(Min.)
• Wide Interfacing ability'" ......... LSTTL, NMOS, CMOS
• Output Drive Capability'" ............ 15 LSTTL Loads
• Symmetrical Output Impedance"'1 Iml =Ia, =6mA(Min.)
• Balanced Propagation Delays ...... t pLl1 " tpl_lI.
• Wide Operating Voltage Range ... Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LS240/2411244
INPUTS
G'"
G
OUTPUTS
An
Yn
yn.o..a
H
L
H
L
L
L
H
H
H
L
H
L
X
Z
Z
A
: TC74HCT241A
AA : TC74HCT240A
X
Z
Only
Only
: Don't Care
: High Impedance
PIN ASSIGNMENT(TOP VIEW)
TC74HCT241A
TC74HCT240A
fa
20 Vee
fa
20 Vee
1<3
20 Vee
1A1 2
192<3
1A1 2
192G
1A1 2
192<3
2Y4 3
181Y1
2Y4 3
18 1Y1
2Y4 3
18 1Y1
1A2 4
172A4
1A2 4
172A4
1A2 4
172A4
2Y3 5
161Y2
2Y3 5
16 1Y2
2Y3 5
16 1Y2
1A3 6
152A3
1A3 6
152A3
1A3 6
152A3
2Y2 7
14 1Y3
2Y2 7
141Y3
2Y2 7
14 1Y3
1A4 8
132A2
1A4 8
132A2
1A4 8.
132A2
2Y1 9
121Y4
2Y1 9
121Y4
2Y1 9
12 1Y4
11 2A1
GND10
11 2A1
11 2A1
HC-425
TC74HCT240AP I AFI AFW
TC74HCT241 AP I AF
TC74HCT244AP I AFI AFW
IEC LOGIC SYMBOL
TC74HCT244A
TC74HCT241A
TC74HCT240A
1Yl
lY2
lY3
1Y4
l--=-"""':"L
2'71
1'7) 2'12
tv3
t'74
2M
HC-426
TC74HCT240AP/AF/AFW
- - - - - - - - - - - - - - - - TC74HCT241AP/AF
TC7 4HCT244API AF I AFW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI\
VOLT
11K
10K
IOLT
lee
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP) */180(MFP)
-65 -150
300
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
unti1300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperrature
SYMBOL
VALUE
Vee
VI\
VOLT
Topr
Input Rise and Fall Time
tr • tr
4.5 - 5.5
0- Vee
0- Vee
-40 - 85
0-500
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
High-Level
Input Voltage
Low-Level
Input Voltage
VIH
I
VIL
High _. Level
Voo
Output Voltage
Low-Level
I
VOL
Output Voltage
3-State Output
1{Jl
Off-State Current
Input Leakage Current
11\
Icc
Quiescent Supply Current
.6. Icc
TEST CONDITION
i
Vee
4.5
I. I
I 5.5
II 4. 5
I
I 5.5
Vr, IOH --20/1 A
VIHorVII . 1011 --6 rnA
101 • -20 /1 A ;
VI\VII-{orVIl. 101. -6 mAl
Vr,-VIH or VII.
!
VI\=Vee or GND
VI\-V ee or GND
VI\-VCCOr GND
Per input: VI\ -0. 5V or 2.4V i
Other input:V(.'Cor GND I
4.5
4.5
4.5
4.5
MIN.
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
-
V
4.4
4. 18
5.5
-
5.5
5. 5
-
5. 5
-
HC-427
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
4.5
4.31
0.0
0.17
-
-
4.4
4.13
-
0.1
0.26
0.1
0.33
V
±0.5
-
±5.0
-
±0.1
4.0
-
+1. 0
40.0
/1 A
-
2.0
-
2.9
rnA
'-
i
I
I
TC74HCT240~P I AF I AFW
TC74HCT241~P/AF
-------------
TC7 4HCT244AP I AFt AFW
I
I
AC ELECTRICAL CHARACTERISTICS(lnput
t r =tf=6ns)
,
SYMBOL
PARAMETER
Output Transition Time
,TEST
CONDITION
CL
tn.H
tTHL
50
tpl_H
50
tpHL
150
tpLH
50
tpHL
150
Propagation Delay Time
*
Propagation Delay Time
**
3-State Output
Enable Time
tpZL
R L= 1 kQ
tpZH
50
150
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
12
4.5
7
15
5.5
6
11
14
22
28
4.5
15
13
20
25
5.5
21
4.5
30
38
16
27
5.5
34
25
4.5
15
31
22
13
28
5.5
ns
21
4.5
33
41
29
5.5
18
37
17
4.5
30
38
14
27
5.5
34
23
38
48
4·5
20
34
5.5
43
16
30
4.5
38
13
27
5.5
34
10
5
10
13
pF
33
31
equivalent capacitance which is calculated from the
Vcc
MIN.
3-State Output
tpLZ
R L = 1 kQ
50
Disable Time
tpHZ
Input Capacitance
DIR,G
C):'\
Bus Input Capacitance
An
CliO
Power Dissipation Capacitance
*
Cm
(Note 1)
**
Note I: C PD is defined as the value of the internal
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCWll =C PO • Vcc· f 1:'\ +Icc 18(per bit)
Note 2:
*=TC74HCT240A
* *=TC74HCT241A/HCT244A
HC-428
-
TC74HC242API AF
------TC74HC243API AF
QUAD BUS TRANSCEIVER
TC74HC242AP/AF 3-STATE,INVERTING
TC74HC243API AF 3-STATE,NON-INVERTING
The TC74HC242A and TC74HC243A are high speed
CMOS QUAD TRANSCEIVER fabricated with silicon gate
C2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
These devices are intended for two-way asynchronous
communication between data busses, and the directioI). of
data transmission is determined by GAB, GBA.
All inputs are equipped with protection circuits against
static discharge or tansient excess voltage.
1
P(DIP14-P-300)
14~
1
F(SOP14-P-300)
FEATURES:
• High Speed ................................. tpd=9ns(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=4/L A(Max.) at Ta=25't
PIN ASSIGNMENT(TOP VIEW)
TC74HC242A
• High Noise Immunity .. · .. · .. · ...... V"'IH =V:\IL =28% Vcc(Min.)
• Output Drive Capability .... · .. ·.... 15 LSTTL Loads
• Symmetrical Output Impedance ·.. 1IOH 1=IOI.=6mA(Min.)
• Balanced Propagation Delays ...... tpLll '" tpHL
• Wide Operating Voltage Range .. · Vcc(opr)=2V-6V
• Pin and Function Compatible with 74LS242/243
GAB 1
14 Vee
NC 2
13 GBA
1A 3
12 NC
2A 4
11 1B
3A
102B
4A 6
93B
GND
84B
TRUTH TABLE
(TOP
VIEW)
TC74HC243A
GAB 1
INPUTS
GAB
GBA
FUNCTION
A BUS
B BUS
14 Vee
OUTPUTS
HC242A
HC243A
H
H
OUTPUT
INPUT
A=B
A=B
L
L
INPUT
OUTPUT
B=A
B=A
H
L
HIGH IMPEDANCE
Z
Z
L
H
HIGH IMPEDANCE
Z
Z
NC 2
13 GBA
1A 3
12 NC
2A 4
11 1B
3A 5
102B
4A 6 ,,,'------1".....
84B
GND 7
Z
93B
HIGH IMPEDANCE
(TOP
NC
HC-429
:NO
VIEW)
CONNECTION
TC74HC242AP/AF _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC243AP I AF
IEC LOGIC SYMBOL
74HC242A
74HC243A
HC-430
TC74HC242API AF
- - - - - - - - - - - - - - - - . TC74HC243AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
Bus Terminal Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VII'
VI/O
11K
10K
IOLT
lee
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP)*/180(SOIC)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Bus Terminal Voltage
Operating Temperature
SYMBOL
Input Rise and Fall Time
tr • tr
Vee
VIl\
VI/O
Topr
VALUE
2-6
0"" Vee
0- Vee
-40"" 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee=6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
vee
2.0
High-Level
VIH
4.5
Input Voltage
6.0
2.0
Low-Level
VIL
4.5
Input Voltage
6.0
2.0
Ia;
=-20tt
A
4.5
High-Level
VIN=
Va;
6.0
Output Voltage
VIHorVIL Ia; --6 rnA
4.5
Ia; =-7. 8mA 6;0
2.0
Ia., =20 tt A 4.5
Low-Level
VIN=
Va.,
6.0
Output Voltage
V1Hor:VIL Ia., -6 rnA
4.5
Ia., =7.8mA 6.0
3-State Output
V IN -VIH or V IL
lao:
6.0
Off-State Current
VOLT =Vee or GND
Input-Leakage Current
VIl\ -Vee or GND
6.0
liN
Quiescent Supply Current
VN -'Vee or GND
6.0
lee
* Applicable only to GAB. GRA
HC-431
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.0
0.1
0.1
0.1
0.1
0.0
V
0.1
0.1
0.0
0.33
0.26
0.17
0.33
0.26
0.18
MIN.
1.5
3.15
4.2
-
-
-
-
-
-
±0.5
-
±5.0
±0.1
4.0
-
±1.0
40.0
ttA
TC74HC242API AF
TC74HC243AP/AF - - - - - - - - - - - - - - - - - - - - - -
AC ELECTRICAL CHARACTERISTICS(lnput t r =tf=6ns)
TEST
Ta--40 -85"C
Ta-25"C
PARAMETER
UNIT
SYMBOL
CONDITION CL
Vcc MIN. TYP. MAX. MIN. MAX.
2.0
20
75
60
tTJ..H
Output T~ansition Time
50
4.5
7
12
15
tTHL
6.0
6
10
13
2.0
38
90
115
50 4.5
12
18
tpLH
23
6.0
10
15
20
Propagation Delay Time
2.0
54
145
180
150 4.5
tpHL
29
17
36
6.0
31
14
25
ns
2.0
180
55
145
50
4.5
tpZL
17
29
36
6.0
15
25
31
Output Enable time
RL = 1 kQ
2.0
73
185
230
tpZH
150 4.5
22
37
46
6.0
17
39
31
2.0
42
150
190
tpLZ
Outpul Disable time
RL = 1 kQ
50
4.5
19
30
38
tpHZ
6.0
15
26
33
Input Capacitance
5
10
10
CI:>I
Output Capacitance
COl;"r
10
- pF
TC74HC242A
28
Power Dissipation Capacitance Cm(l)
TC74HC243A
32
Note(1) Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
I.CCbll}=C PD • Va;. fIN +Ia; 14(per bit)
-
-
HC-432
TC74HC245AP I AF I AFW
--------TC74HC640APIAF
TC74HC643AP/AF
OCTAL BUS TRANSCEIVER
TC74HC245AP/AF
3-STATE. NON-INVERTING
TC74HC640AP/AF 3-STATE.INVERTING
TC74HC643AP/AF 3-STATE.INVERTING AND NON-INVERTlN,:=G'--_ _ _ _ _ _ _ _ _ _ _---,
The TC74HC245A, 640A and 643A are high speed CMOS
OCTAL BUS TRANSCEIVERs fabricated with silicon
gate C2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low
power dissipation.
They are intended for two-way asynchronous
communication between data busses. The direction of
data transmission is determined by the level of the DIR
input.
The enable input (0) can be used to disable the device
so that the busses are effectively isolated.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP20-P-300A)
a~a~
1
F(SOP20-P-300)
FEATURES:
• High Speed ....................................... tpd=10ns(typ.)at Vex;=5V
1
FW(S0L20-P-300)
APPLICATION NOTES
• Low Power Dissipation ....•...........•. Icc=4ttA(Max.)at Ta=25't
1) Do not apply a signal to any
• High Noise Immunity············ .. ······· VNII·FV"IL=28" Vex; (Min.)
• Output Drive Capability·.. ·· .. ··········· 15 LSTTL Loads
• Symmetrical Output Impedance ······1 Ja.I 1=Ia.,=6mA(Min.)
• Balanced Propagation Delays ......... tpLH"'t;,HL
• Wide Operating Voltage Range ......... Vcc(opr)=2V ......6V
• Pin and Function Compatible with 74LS245,640,643
bus terminal when it is in the out
put mode. Damage may result.
2) All floating (high impedance)
bus terminals must have their
input levels fixed by means of pull
up or pull down resistors or blJs
terminator IC's such as the
TOSHIBA TC40117BP.
PIN ASSIGNMENT(TOP VIEW)
TC74HC245A
TC74HC643A
TC74HC640A
DIR 1
.20 Vee
DIR 1
20 Vee
DIR
Al
19 G
Al
19G
Al
A2 3
1881
A2 3
1881
A2 3
A3 4
17 82
A3 4
17 82
A3 4
17 82
A4 5
1683
A4 5
1683
A4 5
1683
2
2
20 V~
2
19 G
1881
A5 6
1584
A5 6
1584
A5 6
1584
A6 7
14 85
A6 7
1485
A6 7
14 85
A7 8
1386
A7 8
1386
A7 8
1386
A8 9
1287
A8 9
1287
A8 9
1287
GND10
11 88
GND 10
11 88
GND 10
11 88
HC-433
TC74HC245APIAFI AFW
----------------TC74HC640AP/AF
TC74HC643AP/AF
IEC LOGIC SYMBOL
TC74HC245A
TC74HC640A
TC74HC643A
TRUTH TABLE
INPUTS
FUNCTION
OUTPUTS
G
DIR
A BUS
BBUS
l
l
OUTPUT
INPUT
A=B
A==8
A=B
l
H
INPUT
OUTPUT
S=A
B=A
S-A
H
X
Z
Z
Z
High Impedance
X : "HO or "l"
Z : High Impedance
HC-434
HC245A HC640A HC643A
TC74HC245AP I AF I AFW
- - - - - - - - - - - - - - TC74HC640AP/AF
TC74HC643API AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI:'-i
VOCT
11K
10K
IOLT
lee
PD
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5·
±20
±20
±35
±75
500(DIP )·/180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI"
VOLT
Topr
tr , tf
VALUE
2-6
0- Vee
0- Vee
-40 - 85
0- IOOO(Vee =2.0V)
0- 500(Vee =4.5V)
0""'" 400(Vee=6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
3-State Output
orr-State Current
ICE
Input Leakage Current
Quiescent Supply Current
II!\
lee
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
IOH =-20j.l A 4.5
VI:, =
6.0
VIHorVIL
IOH --6 rnA 4.5
IOH =-7.8mA 6.0
2.0
IOL =20 j.lA 4.5
VI!\=
6.0
VIHorVIL
IOL -6 rnA 4.5
IOL =7.8mA 6.0
VI!\ -VIH or VII.
6.0
VOLT =Vee or GND
6.0
VI!\ -Vee or GND
VI!\ -Vee or GND
6.0
HC-435
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3. 15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
5.9
6.0
4.18
4.31
4.13
5.68
5.80
5.63
0.1
0.0
0.1
0.1
0.0
0.1
V
0.1
0.0
0.1
0.26
0.33
0.17
0.26.
O. 18
0.33
MIN.
1.5
3.15
4.2
-
-
±0.5
-
-
±0.1
4.0
-
-
±5.0
±1.0
40.0
j.lA
TC74HC245AP I AFI AFW
TC74HC640AP/AF
---------------------------TC14HC643AP I AF
AC ELECTRICAL CHARACTERISTICS(C l =50pF.lnput t r =tf=6ns)
TEST
Ta-25"C
Ta--40 -85"C
PARAMETER
SYMBOL
UNIT
CONDITION CL Va:; MIN. TYP. MAX. MIN. MAX,
2.0
25
60
75
tn.H
Output Transition Time
50 4.5
7
12
15
tTI-lL
6.0
13.
10
6
2.0
33
90
115
12
18
23
50 4.5
tpLH
6.0
20
10
15
Propagation Delay Time
2.0
48
120
150
24
30
150 4.5
16
tpHL
6.0
14
20
26
ns
190
2.0
48
150
16
30
38
50 4.5
tpZL
3-State Output
26
32
6.0
14
RL = 1 kQ
Enable Time
2.0
63
180
225
tpZH
21
36
150 4.5
45
6.0
18
31
38
2.0
37
150
190
3-State Output
tpLZ
R L= lkQ
4.5
30
38
50
17
Disable Time
tpHZ
6.0
32
15
26
Input Capacitance
DIR,G
5
10
10
CIN
Bus. Input Capacitance
An,Bn
13
Ca..'T
pF
TC74HC245A
39
Power Dissipation Capacitance
CFI)(Il
TC74HC640A/643A
37
Note(1) Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia:;QlIl=C PO ' VOC,CF\ +ICC 18(perbit)
-
-
HC-436
TC74HCT245AP I AF I AFW
------TC74HCT640AP/AF
TC7 4HCT643AP I AF I AFW
OCTAL BUS lfRANSCEIVER
TC74HCT245APt AFt AFW 3-STATE.NON-INVERTING
TC74HCT640APt AF
3-STATE.INVERTING
TC74HCT643APt AFt AFW 3-STATE.INVERTING AND NON-INVj-!E:..:R..:..T.:..;I'-=-'N:..::G=--_ _ _ _ _ _ _ _ _--,
The TC74HCT245A. HCT640A and HCT643A are high
speed CMOS OCTAL BUS TRANSCEIVERs fabricated
with silicon gate C2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Their inputs are compatible with TTL, NMOS, and
CMOS output voltage levels.
They are intended for two-way asynchronous
communication between data busses. The direction of date
transmission is determined by the level of the DIR input.
The enable input «}) can be used to disable the device
so that the busses are effectively isolated.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP20-P-300A)
a~a~
1
1
F(SOP20-P-300)
FW(SOL20-P-300)
APPLICATION NOTES
FEATURES:
• High Speed ................................. tpd=10ns(typ.)at Vcc=5V
1) Do not apply a signal to any
bus terminal when it is the output
mode. Damage may result.
• Low Power Dissipation ............... Icc =4.uA(Max.)at TA=25"C
• Combatible with TTL outputs ...... V1L =O.8V(Max.). VIH =2.0(Min.)
• Wide Interfacing ability······ ...... LSTTL. NMOS, CMOS
• Output Drive Capability .............. · 15 LSTTL Loads
2) All floating (high impedance)
bus terminals must have their
input levels fixed by means of pull
up or down resistors or bus
terminator IC's such as the
TOSHIBA TC40117BP.
• Symmetrical Output Impedance "'1 Irnl=IQL =6mA(Min.)
• Balanced Propagation Delays ...... tpu;'" tpHL
• Pin and Function Compatible with 74LS245,640.643
PIN ASSIGNMENT(TOP VIEW)
TC74HCT640A
TC74HCT245A
DIR
Al
20 Vee
2
A2 34
A3
'-='-++-="'-1-119
G
~~Q§[~1817 B2
B1
DIR 1
Al
A2
2
TC74HCT64;3A
20 Vee
~--t+=.-l..h 19
3~~~::;:J...hI8
A3 4
G
81
DIR
20 Vrid
A 1 2 u........oo-H:::,...-,
19
17 Q2
A2 3
A3 4
G
~~I:P:iJJt:! 18
81
1782
A4 5
16 B3
A4 5
16 83
A4 5
1683
A5 6
15 B4
A5 6
15 84
AS 6
15 84
A6 7
14 85
A6 7
14 85
A6 7
14 85
A78
1386
A78
1386
A7 8
1386
A8 9
1287
A8 9
1287
A8 9
1287
GND 10
11 88
GND 10
11 B8
GND 10
11 88
HC-437
TC74HCT245AP I AF I AFW
TC74HCT640AP/AF
------------TC74 HCT643AP I AF I AFW
IEC LOGIC SYMBOL
TC74HCT245A
TC74HCT640A
TC74HCT643A
A3
A4 15
AS 16
~6 (7)
A7 18
MIS
TRUTH TABLE
INPUTS
FUNCTION
OUTPUTS
G
OIR
A BUS
BBUS
l
l
OUTPUT
INPUT
A=B
A=B
A=B
l
H
INPUT
OUTPUT
B=A
B=A
B=A
H
X
Z
Z
Z
High Impedance
X : "H" or "l"
Z : High Impedance
HC-438
HCT245A HCT640A HCT643A
TC7 4HCT245AP I AF I AFW
TC74 HCT640AP I AF
TC7 4HCT643AP I AF I AFW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
Vee
VI,\
VOLT
11K
10K
IOLT
Icc
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5·
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
°C
°C
*500mW in the range of Ta=
-40'C- 65°C. From Ta=65'C
to 85°C a derating factor of
-10m WI'C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SnmOL
Supply Voltage
Vee
VI,\
Input Voltage
Output Voltage
VOLT
Operating Temperature
Topr
Input Rise and Fall Time
tr• tf
VALUE
4.5-5.5
O-Vee
a-Vee
-40-85
0-500
UNIT
V
V
v
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
Vil.
High Level
Output Voltage
Low-Level
Output Voltage
3-State Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
TEST CONDITION
Ta-25°C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
Vee
4.5
MIN.
I
2.0
-_.
-
2.0
-
V
-
-
0.8
-
0.8
V
5.5
4.5
VOH
VOL
1m
11,\
Icc
6. lcc
I
VI'\IOH - 20/1 A
V1HorVIL 10; - 6 rnA
VI,\ -.
IOL -20 /1 A
VIHorVIL 101 • ~6 rnA
VI,\-VIH or VIL
VOLT=Vee or GND
VI,\ - Vee or GND
VI,\-Vec or GND
Per input:V I,\ -0. 5V or 2. 4V
Other input:Vccor GND
5. 5
4.5
4.5
4.5
4.5
5.5
4.4
4.18
-
O. 1
0.26
-
0.1
0.33
V
-
-
±0.5
-
±5.0
/1 A
-
±O.l
4.0
-
±1.0
40.0
/1 A
-
2.0
-
2.9
rnA
-
5.5
5.5
5.5
HC-439
-
4.5
4.31
0.0
0.17
-
4.4
4. 13
V
TC74HCT245APIAF I AFW
TC74HCT640APIAF
TC74HCT643APIAF I AFW
AC ELECTRICAL CHARACTERISTICS(lnput t r =t f =6ns)
TEST
Ta-25"C ,
Ta--40 -85"C
PARAMETER
SYMBOL
UNIT
CONDITION CL Vex; MIN. TYP. MAX. MIN. MAX.
7
12
15
4.5
tTLH
Output Transition Time
50
5~ 5
6
II
14
tlliL
22
13
28
4.5
tpLH
50
5.5
20
25
11
Propagation Delay Time
18
30
38
4.5
ISO
tpHL
27
16
34
5.5
ns
30
38
4.5
19
tpZL
50
3-State Output
16
27
34
5.5
RL= I kQ
Enable Time
48
4.5
24
38
tpZH
150
22
34
43
5.5
3-State Output
38
17
30
4.5
tpLZ
RL= 1 kQ
50
Disable Time
tpHZ
27
34
5.5
16
Input Capacitance
DIR,G
10
10
5
CI~
Bus Input Capacitance
An,Bn
13
CI/a
pF
TC74HCT245A
41
Power Dissipation Capacitance
CR)(l)
'rc74HcT640A/T643A
39
Note (1): Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
oPllrating current consumption without load.
Average operating current can be obtained by the equation:
Iex;tpr} =C po • Va:;. £N +Ia:; 18(per bit)
HC-440
------TC74HC251 AP/AF
8-CHANNEL MULTIPLEXER (3-STATE)
The TC74HC251A is a high speed CMOS 8-CHANNEL
MULTIPLEXER fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
One of eight data input signals (DO-D7) is selected by
decoding of the address inputs (A, B, C). The selected
data appears on two outputs: non-inverting (Y) and
inverting (W).
When the strobe input is held high, both outputs are in
the high-impedance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ..•..•••.............•........ tpd =15ns(typ. )at Vcc=5V
• Low Power Dissipation ............ ICC =4/.tA(Max.)at Ta=25"C
• High Noise Immunity··············· Y."JIH=VNI L28% Vcc(Min.)
• Output Drive Capability············ 10 LSTTL Loads
• Symmetrical OUtput Impedance ... I IOH I =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range ... Vcc ·(opr.)=2V-6V
• Pin and Function Compatible with 74LS251
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
03 1
16 Vee
02 2
16 04
01 3
14 06
DO 4
13 08
Y 6
12 07
W 8
11.A
ST 7
10 B
GNO 8
9 C
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
INPUTS
SELECT
C
B
A
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
X : Don't care
OUTPUTS
STROBE
ST
H
L
L
L
L
L
L
L
L
y
MUX
W
EN
Z
Z
DO
DO
01
02
03
04
05
06
07
01
02
03
04
05
06
07
Z : High Impedance
HC-441
O} G ~7
2
0
1
2
.3
4
5
8
7
V
V
Y
W
TC74HC251AP/AF---------------------------------
HC-442
- - - - - - - - - - - - - - - - TC74HC251AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI:"
VOUT
11K
10K
lOLl'
lee
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)·/180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40·C- 65"C. FI'om Ta=65·C
to 85"C a derating factor of
-lOmWrC shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
o -Vee
o -Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
SYMBOL
Vee
VI:"
VOL"!'
Topr
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL.
3 State Off Leak
Current
lev.
Input Leakage Current
QuiHCenl Supply Currenl
11:-1
lee
TEST CONDITION
VI:>; =
VIHorVIL
VI:-I=
VIHorVIL
IOH =-201L A
IOH --4 rnA
IOH =-5.2mA
IOL =20 IL A
IOL. -4 rnA
IOL =5.2rnA
VI:" -VIH or VII.
VOLT=Veeor GND
VI:" -Vee or GND
VI:" -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
HC-443
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
5.9
6.0
4.31
4.13
4.18
5.68
5.80
5.63
0.1
0.1
0.0
0.0
0.1
0.1
V
0.0
O. 1
0.1
0.26
0.33
0.17
0.26
0.33
0.18
±0.5
±5.0
MIN.
1.5
3.15
4.2
-
-
-
-
±0.1
4.0
-.
±1.0
40.0
ILA
TC74HC251 API AF
AC ELECTRICAL CHARACTERISTICS(C L =16pF,vcc=6V,Ta=25"C)
MIN.
TYP.
t11.H
tTHL
-
4
8
Time
tpU-j
-
14
24
Time
toHL
tpLH
-
15
24
-
19
31
-
19
31
-
10
18
PARAMETER
SYMBOL
Output Transition Time
Propagation Delay
(D-Y)
Propagation Delay
(D-W)
Propagation Delay
(A B C-Y)
Propagation Delay
(A. B C-W)
TEST CONDITION
tlli-IL
Time
tpLH
toHL
Time
3-State Output Enable Time
tpU-I
toHL
tPZi.
tpZH
MAX.
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =60pF,lnput t r =tf=6ns)
Ta-25"C
Ta- 40 -85"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vex; MIN. TYP. MAX. MIN. MAX.
2.0
75
95
30
t11.H
Output Transition Time
8
15
19
4.5
tTIlL
6.0
7
13
16
2.0
65
140
175
Propagation Delay Time
tpLH
4.5
17
28
35
(D-Y)
tp(-IL
6.0
24
14
30
2.0
70
140
175
Propagation Delay Time
tpLH
18
28
35
4.5
(D-W)
tp(-lL
24
6.0
15
30
225
2.0
80
180
Propagation Delay Time
tpLH
ns
23
4.5
36
45
(A.B.C-Y)
tp(-IL
60
19
31
38
225
2.0
80
180
Propagation Delay Time
tpLH
4.5
23
36
45
(A. B. C-W)
tp(-IL
38
6.0
19
31
40
105
130
2.0
t~
3-State Output Enable Time
21
26
4.5
13
tpZH
22
19
6 0
10
25
105
130
2.0
tpLZ
3-State Output Disable Time
21
26
4.5
13
tlli-lZ
19
22
6 0
11
Input Capacitance
5
10
10
CN
- pF
Power Dissipation Capacitance Cpo(l)
69
Note(1) CID is deCined as the value of the internal equivalent. capacitance which is calculated from the
operating current .consumption without load.
Average operating current can be obtained by the equation:
lex; tp}=C po' Va:;' f IN +I a:;
-
HC-444
TC7 4HC257 AP I AF I AF N
----TC74HC258AP/AF
TC74HC257API AFI AFN
TC74HC258API AF
The TC74HC257A and TC74HC258A are high speed
CMOS MULTIPLEXERs fabricated with silicon gate
C2MOS technolgy.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Each is composed of four independent 2-channel
multiplexe~ with common SELECT and OUTPUT
ENABLE(OE).
The TC74HC257A is an inverting multiplexer, while the
TC74HC258A is non-inverting.
If OE is set low, the outputs are held in a
high-impedance state. When SELECT is set low, A"
data inputs are enabled.
Conversely, when SELECT is high, "B" data inputs are
enabled.
All inputs are equipped with protection citcuits against
static discharge or transient excess voltage.
P(DIP16-P-300A)
1.~16~
U
F(SOP16-P-300)
FN(SOL 16-P-150)
TRUTH TABLE
FEATURES:
• High Speed .........................•....... tpd =10ns(typ.)at Vcc=5V
• Low Power Dissipation ............... Icc=4.uA(Max.)at Ta=25"C
• High Noise Immunity .... ······· .. ····· VNlH =VN1L =28" Vcc(Min.)
• Output Drive Capability .... ·, .. ··· .... 15 LSTTL Loads
• Symmetrical Output Impedance '''1 IrnI=IOL =6mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range'" Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LS2571258
INPUTS
OE SELECT
A
OUTPUTS
B
H
X
X
X
Z
Z
L
L
L
X
L
H
L
L
H
X
H
L
L
H
X
L
L
H
H
X
H
H
L
L
X : Don't Care
Z : High Impedance
PIN ASSIGNMENT
TC74HC257A
SELECT 1
TC74HC258A
16
15
14
13
12
1A 2
18 3
1Y 4
2A 5
28 6
2Y 7
SELECT 1
Vee
OE
4A
48
4Y
11 3A
10 38
9 3Y
GND 8
(TOP VIEW)
1A
18
fY-
16
15
14
13
12
2
3
4
5
6
Vee
OE
4A
48
4Y
11 3A
10 38
9 3Y
2A
28
2Y 7
GND 8
(TOP VIEW)
HC-445
Y(257A) Y(258A
TC74HC257AP/AFI AFN _ - - - - - - - - - - - - TC7 4HC258AP I AF
IEC LOGIC SYMBOL
TC,74HC258A
TC74HC257A
OE
OE
SELECT
SELECT
1A
16
2A
26
3A
36
4A
46
1A
1Y
16
2A
2Y
26
3A 1
3Y
36 1
4A
4Y
46
HC-446
1Y
2Y
3Y
4Y
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC257AP/AF/AFN
TC74HC258AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Supply Voltage Range
Vee
DC Input Voltage
VI"
DC Output Voltage
VOLT
Input Diode Current
11K
Output Diode Current
10K
DC Output Current
IOLT
DC Vee/Ground Current
lee
Power Dissipation
PD
Storage Temperature
Tstg
Lead Temperature lOsec .
TL
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5:
±20
±20
±35
±75
500(DIP) */ l80(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65·C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vcc
o -Vcc
-40 - 85
o- 1000(Vcc=2.0V)
0- 500(Vcc =4.5V)
o - 400(Vcc =6.0V)
SYMBOL
Vee
VI"
VOLT
Topr
t r • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
High-Level
Input Voltage
VIIi
Low-Level
Input Voltage
Vu.
High-Level
Output Voltage
Vm
Low-Level
Output Voltage
VOL
3-State Output
Off-State Current
I
Input Leakage Current
Quiescent Supply Current
I I I"
I Icc
!
lat
TEST CONDITION
VI" =
VlliorVII•
VI" =
VIHorVIL
100 =-20/J.A
lUi --6 rnA
100 =-7. SmA
IOL =20 /J.A
IOL -6 rnA
IOL =7. SmA
VI" -VII-I or V IL
VOLT =Vcc or GND
VI" -'Vcc or GND
VI" -Vcc or GND
Vcc
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
HC-447
Ta-25"C
Ta--40 -85"C UNIT
TYP. MAX. MIN. I MAX.
, 1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
l.S
l.S
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
US
4.31
4.13
5.68
5. SO
5.63
0.0
0.1
0.1
il. 0
0.1
0.1
V
0.1
0.0
0.1
0.26
0.33
0.17
0.26
0.33
O.IS
±0.5
±5.0
A
±0.1
±1.0 /J.
40.0
4.0
MIN.
1.5
3.15
4.2
-
-
TC74HC257 AP I AFI AFN
TC74HC258AP/AF
-------------------------------
AC ELECTRICAL CHARACTERISTICS(lnput t r =t,=6ns)
TEST
Ta-25"C
Ta- 40 -85"C
SYMBOL
UNIT
PARAMETER
CONDITION CL
Va; MIN. TYP. MAX. MIN. MAX.
2.0
20
60
75
tll.H
Output Transition Time
4.5
50
6
12
15
tmL
6.0
5
10
13
2.0
100
125
45
50
4.5
20
13
25
tpLH
Propagation Delay Time
6.0
17
21
11
2.0
62
140
175
(A, B-Y, Y)
150 4.5
28
18
35
tpHL
24
6.0
15
30
100
125
2.0
45
50 4.5
20
25
tpLH
13
Propagation Delay Time
6.0
11
17
21
ns
2.0
62
140
175
(SELECT- Y, Y)
150 4.5
28
18
35
tpl-/L
24
30
6.0
15
2.0
110
140
40
tpZL
50 4.5
22
28
12
3-State Output
6.0
10
19
24
R L= lkQ
Enable Time
2.0
150
190
57
tpZH
38
150 4.5
17
30
6.0
14
26
33
2.0
28
140
175
3-State Output
tpLZ
RL = 1 kQ
4.5
50
14
28
35
Disable Time
tpHZ
6.0.
13
24
30
Input Capacitance
5
10
10
C'1\
i Output Capacitance
10
Ca.'T
pF
TC74HC257A
47
Power Dissipation Capacitance
CFD(1)
TC74HC258A
47
Note (1): Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia;tpO=C PD • Voc· fN +Ioc 14(per bit)
-
HC-448
---------------------------TC74HCT257AP/AF QUAD
TC74HCT257AP/AF
TC74HCT258API AF
2-CHANNEL MULTIPLEXER(3-STATE)
rT-=.C7:....:4~H-=.C..:..;T2=5c=.:8Ac..:..:P~/..:..;A:..:..F-'Q::..:U::..:Ac..:..:D:::....--=-2----'C::...:H..:...:A..:..:N.=..:N.=..:E=-=L=-:..:.:M-=.U.=L..:..;T.:..:,.IP-=L:..:;E XER (3-8T ATE. 1NVERTIN G)
The TC74HCT257A and TC74HCT258A are high speed
CMOS MULTIPLEXERs fabricated with silicon gate
C2MOS technolgy.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Each is composed of four independent 2-channel
multiplexe~ with common SELECT and OUTPUT
ENABLE(OE).
The TC74HCT257A is an inverting multiplexer, while
the TC74HC258A is non-inverting.
If OE is set low, the outputs are held iii a
high-impedance state. When SELECT is set low, "A"
data inputs are enabled.
Conversely, when SELECT is high, "B" data inputs are
enabled.
All inputs are equipped with protection citcuits against
static discharge or transient excess voltage.
1.~
1
P(DIPI6-P-300A)
16~
F(SOPI6-P-300)
TRUTH TABLE
FEATURES:
• High Speed ................................. tpd =16ns(typ.)at Vee =5V
• Low Power Dissipation ............... Icc=4f.lA(Max.)at Ta=25"C
• Compatible with TTL outputs ...... VIL=O.8V(Max.), Vlw2.OV(Min.)
• Wide Interfacing ability··············· LSTTL,NMOS,CMOS
• Output Drive Capability········· ...... 15 LSTTL Loads
• Symmetrical Output Impedance ·········1 Iml=IOL=6mA(Min.)
• Balanced Prop~gation Delays ...... tpLI-P t pHL
• Pin and Function Compatible with 74LS257/258
INPUTS
OE SELECT
OUTPUTS
A
B
H
X
X
X
Z
Z
L
L
L
X
L
H
L
L
H
X
H
L
L
H
X
X
L
L
H
H
H
L
L
H
X: Don't Care
Z : High Impedance
PIN ASSIGNMENT
TC74HCT257A
TC74HCT258A
SELECT 1
16 Vce
SELECT 1
16 Vee
lA
2
15 OE
lA
15 OE
lB
3
14
4A
lB
3
14
lY
4
13
4B
lY
4
13
4B
2A
5
12
4Y
2A
5
12
4Y
2
4A
2B
6
11
3A
2B
6
11
3A
2Y
7
10
3B
2Y
7
10
3B
GND 8
9
3Y
GND 8
9
3Y
(TOP VIEW)
(TOP VIEW)
HC-449
Y(257A) Y(258A)
TC74HCT257AP/AF _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HCT258AP! AF
IEC LOGIC SYMBOL
TC74HCT258A
TC74HCT257A
Oe
OE
SELECT
SELECT
1A
18
2A
28
SA
38
48
1A
1Y
18
2A
2Y
28
SA
38
3Y
4A
4Y
48
HC-450
1Y
2Y
3Y
4Y
TC74HCT257 API AF
----------------TC74HCT258AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIr-;
VOLT
11K
10K
lOOf
lee
Po
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP) */180(SOIC)
-65 -150
300
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperrature
Input Rise and Fall Time
SYMBOL
Vee
VI'"
VOUT
Topr
tr • tr
VALUE
4.5 - 5.5
0- Vee
0- Vee
-40 - 85
0-500
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Low-Level
Output Voltage
3-State Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
TEST CONDITION
MIN.
I
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
5.5
4.5
Vm
Vex.
Iaz
Ie,;
lee
L'l.lcc
I
VIN101-1 =-20/1. A
VIHorVIL 1m --6 rnA
VIN lex. -20 /1. A
VIHorVIL lex. -6 rnA
Vlr\-VIH or VIL
VIN=Vee or GND
VIN-Veeor GND
VIN-VeeorGND
Per input: VI:>! -0. 5V or 2. 4V
Other input:Veeor GND
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
Vee
4.5
5.5
4.5
4.5
4.5
4.5
5.5
4.4
4.18
-
4.5
4.31
0.0
0.17
-
-
5.5
5.5
5.5
HC-451
-
4.4
4.13
V
0.1
0.26
-
0.1
0.33
V
±0.5
-
±5.0
±O.l
4.0
-
-
-
-
-
2.0
±1.0
40.0
-
2.9
/1. A
rnA
TC74HCT257AP/AF _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HCT258API AF
AC ELECTRICAL CHARACTERISTICS(lnput t r =tf=6ns)
TEST
Ta--40 -85"C
. Ta-25"C '.
PARAMETER
UNIT
SYMBOL
CONDITION CL Va:. MIN. TYF. MAX. MIN. MAX.
7
tTLH
4.5
12
15
Output Transition Time
50
tTIiL
5.5
6
11
14
4.5
30
19
38
tpLH
50
5.5
27
16
34
TC74HCT257 A
38
48
4.5
24
tpHL
Propagation Delay Time
150
20
5.5
35
44
4.5
27
34
17
(A,B-Y,Y)
tpLH
50
14
5.5
25
31
TC74HCT258A
4.5
22
35
44
150
tpHL
5.5
18
32
40
ns
4.5
20
30
38
Propagation Delay Time
tpLH
50
5.5
17
27
34
4.5
25
38
48
(SELECT-Y,Y)
150
tpHL
5.5
21
35
44
4.5
18
30
38
50
tpZL
3-State Output
5.5
15
27
34
RL = 1 kQ
Enable Time
4.5
23
38
48
150
tpZH
5.5
19
35
44
3-State Output
tpLZ
4.5
30
38
16
RL = 1 kQ
50
Disable Time
tpHZ
5.5
27
13
34
Input Capacitance
C IN
5
10
10
Output Capacitance
10
Carr
pF
Power Dissipation Capacitance
TC74HCT257A
34
Cit)
(Note 1)
TC74HCT258A
33
Note I: Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia:. q,o =C po • Vc:c ofJ."\ +Ic:c 14(per bit)
HC-452
----TC74HC259AP/AF/AFN
8-BIT ADDRESSABLE LATCH
The TC74HC259A is a high speed CMOS ADDRESSABLE LATCH fabricated with silicon gate C2 MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power
dissipation.
The respective bits are controlled by address inputs A,
B, and C. When CLEAR input is held high and enable
input G is held low, the data is written into the bit selected
by address inputs, the other bits hold their previous
conditions. When both CLEAR and G held high, writing
of all bits is inhibited regardless of address inputs, and
their previous conditions are held. When CLEAR is held
low and G is held high, all bits are reset to low regardless
of the other inputs. When both of CLEAR and G held low,
all bits not selected by address inputs are reset to low.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P( DIP18-P-300A)
"~1.~
F(SOP18-P-300)
FN (SOL 18-P-150)
PIN ASSIGNMENT
A
B
C
00
01
Oz
03
FEATURES:
• High Speed ." ........................... tpcFI5ns(Typ,)at Vcx;=5V
• Low Power Dissipation ............ Icx;=4#A(Max.)at Ta=25"C
• High Noise Immunity· .............. VNIH=VNII.28" Vcx;(Min.)
• Output Drive Capability .... •.. •.... 10 LSTTL Loads
• Symmetrical Output Impedance "'1100 1=10. =4mA(Min.)
• Balanced Propagation Delays ...... tpU{" tpHL
• Wide Operating Voltage Range'" Vcx;(opr.)=2V-6V
• Pin and Function Compatible with 74LS259
1
18 Vee
1& CLEAR
2
3
4
14 G
13 DATA. IN
12 07
11 O.
10 01
9 04
&
6
7
GND8
(TOP VIEW)
IEC LOGIC SYMBOL
A 1
8 Z
g
DATA
IN
CLEAii
GO
1i.TA
M.TR
•• 30
10.1'R
.40
1O.'iR
' •• 0
10.TR
'.10
".TR
1i.TR
HC-453
Q1
QZ
Q3
TC74HC259AP/AF/AFN - - - - - - - - - - - - - -
TRUTH TABLE
INPUTS
CLEAR
G
H
L
H
H
L
L
L
H
OUTPUT OF
ADDRESSED
LATCH
SELECT INPUTS
C
B
A
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
0
OiO
0
L
EACH OTHER
OUTPUT
OiO
OiO
L
L
LATCH
ADDRESSED
00
01
02
03
04
05
06
07
FUNCTION
ADDRESSABLE LATCH
MEMORY
8-LlNE DEMULTIPLEXER
CLEAR ALL BITS TO NL·
o : The level at the data input.
QiO : The level before the indicated steady-state
input conditions were established (i = 0,1, ···7)
SYSTEM DIAGRAM
DATA IN13
I
-----~
CLEAR 15
G _14-,~.,.,-,>o_ _ _ _--.,
THE SAME AS ABOVE
THE SAME AS ABOVE
04
05
06
07
HC-454
- - - - - - - - - - - - - - TC74HC259AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
Vee
VI\
VOLT
11K
10K
lOLl'
lee
PD
Tstg
TI.
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m Wrc shall be applied
until 300m W.
RECOMMEND.ED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Vee
VI\
VOLT
Topr
Input Rise and Fall Time
tr • tf
VALUE
2-6
0- Vee
0- Vee
-40 - 85,
0- 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vcc =6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VII.
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOl.
Input Leakage Current
Quiescent Supply Current
11\
ICC
TEST CONDITION
Vcc
2.0
4.5
6. 0
2. 0
4. 5
6.0
2.0
I
I(~l =-20/1 A 4.5
I VI\=
6.0
VIHorV", IOH =-4 rnA
4.5
Ial =-5. 2iliA 6.0
2.0
Ia. =20 tl A 4.5
VI\ =
6.0
V",o rVII. la, -4 rnA 4.5
I(~. =5.2rnA
6.0
VI\ -Vee or GND
6. 0
VI\ -Vee or GND
6.0
J-
HC-455
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3. .15
4.2
O. 5
0.5
V
L 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
5.9
6.0
4.13
4.18
4.31
5.63
5.68
5.80
0.1
0.0
O. 1
O. 1
0.0
0.1
V
0.1
0.0
o. 1
0.33
0.17
0.26
0.33
0.18 I 0.26
±1.0
±O.l
A
I
40.0 tl
4.0
MIN.
1.5
3. 15
4.2
TC74HC259AP/AF/AFN - - - - - - - - - - - - - -
TIMING REQUIREMENTS(lnput tr=tf=6ns)
PARAMETER
Minimum Pulse Width
SYMBOL
(G)
twO.)
Minimum Pulse Width
(CLEAR)
t\\'(I.)
Minimum Set-up Time
(DATA)
t8
Minimum Set-up Time
(A, B, C)
t8
Minimum Hold Time
(DATA)
th
Minimum Hold Time
(A, B, C)
th
TEST
CO~DITION
Va:
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6 0
Ta- 4C -85"C
milT
LIMIT
95
19
16
95
19
16
60
ns
12
Ta-25"C
. LIMIT
TYP.
75
15
13
75
15
13
50
10
9
25
5
5
25
5
5
0
0
0
11
30
6
5
30
6
5
0
0
0
MHz
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
Output Transition Time
Propagation Delay Time
(DATA-Q)
Propagation Delay Time
(A, B, C-Q)
PropagatiQ.n Delay Time
(G-Q)
Propagation Delay Time
(CLEAR-Q)
SYMBOL
TEST CONDITION
tTLH
tTH\..
tpl..H
t oIiL
tpI..H
t oI-Il
tplJi
MIN.
HC-456
MAX.
-
4
8
-
15
22
-
21
32
-
16
28
-
13
23
toHL
tpHL
TYP.
U~IT
ns
--------------TC74HC259AP/AF/AFN
AC ELECTRICAL CHARACTERISTlCS(C L =50pF,lnput t r =tf=6ns)
Ta--40 -85"C
Ta-25"C
milT
TYP. MAX. MIN. MAX.
30
75
95
t11.H
Output Transition Time
8
19
15
tnil
7
16
13
130
165
56
Propagation Delay Time
tpl.H
26
33
18
(DATA-Q)
tP/il
22
28
15
185
230
83
Propagation Delay Time
tplH
ns
25
37
46
(A. B. C-Q)
tpl-Il
21
31
39
67 .
205
165
Propagation Delay Time
tpLH
20
33
41
(G-Q)
tp/il
35
17
28
170
52
135
Propagation Delay Time
27
16
34
tpHl
(CLEAR-Q)
23
29
14
Input CapaGitance
10
CIN
5
10
pF
Power Dissipation Capacitance CPD(l)
35
Note(l) em is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
la:,q,o=C PD' Va:.' fl~+I a:./4(per Latch)
PARAMETER
SYMBOL TEST CONDITION
Va:,
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
MIN.
-
HC-457
TC74HC266AP I AF
TC7 4HC7266AP i AF
TC74HC266API AF
TC74HC7266API AF
QUAD EXCLUSIVE NOR GATE
QUAD EXCLUSIVE NOR GATE
(OPEN DRAIN)
The TC74HC266A17266A are high speed CMOS QUAD
EXCLUSIVE NOR GATE Cabricated with silicon gate
C2l\lOS technology ..
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HC266A has a high-performance MOS Nchannel transistor (OPEN-DRAIN output).
Therefore, with suitable output pullup resistors, this
device can be used in wired-AND application.
The TC74HC7266A has an output buffer which is CMOS
structure.
All inputs are equipped with protection circuits against
static dischage or transient excess voltage.
FEATURES:
• High Speed ·•·•·•·•·•·········•···· ... ···1p,j=10ns{typ.)at Va;=5V
• Low Power Dissipation ............ Ia;=4ttA(Max.)at Ta=25"C
• High Noise Immunity··············· VNIH=VNIL2896 Va; (Min.)
• Output Drive Capability··· ......... 10 LSTTL Loads
• Symmetrical Output Impedance ···1 IOH 1=IOL =4mA(Min.)
• Balanced Propagation Delays .•.... tpLH" tpHL
• Wide Operating Voltage Range ... Va; ( opr. ) =2V -6V
• Pin and Function Compatible with 74LS266
1
P(DIP14-P-300)
14~
1
F (SOP 14-P-300)
PIN ASSIGNMENT
lA I
14 Vee
18 2
13 48
lY 3
12 4A
II 4Y
2Y 4
SYSTEM DIAGRAM
10 3Y
2A 5
28 6
GN.D7
9
38
8
3A
(rOp VIEW)
IEC LOGIC SYMBOL
TC74HC286A
TRUTH TABLE
TC74HC7266A
Y
A
8
L
L
L
H
H
7266A
266A
H
Z
H
L
L
L
L
L
H
H
Z
Z:Hlgh Impedance
HC-458
TC74HC266API AF
-------------------------------TC74HC7266AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vcc
VI:"\
VOLT
11K
10K
100T
lee
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5 -7
-0.5 -Vcc+0.5
-0.5 -Vce+0.5
±20
±20
±25
±50
500(DIP)*/180(MFP)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85'C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI:"\
VOlT
Topr
tr , tc
VALUE
2-6
0- Vee
0- Vee
-40 - 85
0- 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee=6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
Output
Off-State Current
ICE
Input Leakage Current
Quiescent Supply Current
11:"\
Icc
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
VI:"\=
IOH =-20.u A 4.5
VIHorV IL
6.0
(TC74HC
IOH =-4 rnA 4.5
7266A)
IOH =-5. 2mA 6.0
2.0
IOL =20 .u A 4.5
VI:"\=
6.0
VIHorVIL
loJ. -4 rnA 4.5
IOL =5.2mA 6.0
VI:"\ =VIHorVII•
VOLT =Vee
5.5
(TC74HC266A)
VI:"\ -Vee or GND
6.0
V 1:"\ -Vee or GND
6.0
HC-459
Ta-25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3. 15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
6.0
5.9
5.9
4.31
4.13
4.18
5.63
5.68
5.80
0.0
0.1
0.1
0.0
0.1
0.1
V
0.1
0.0
0.1
0.26
0.17
0.33
0.26
0.33
O. 18
MIN.
1.5
3.15
4.2
-
-
±0.5
-
±0.5
.u A
±0.1
4.0
±1.0
40.0
TC74HC266APIAF
TC74HC7266APiAF
AC ELECTRICAL CH ARACTERISTICS(C L =15pF. Vcc=5V .Ta=25"C)
PARAMETER
TEST CONDITION
SYMBOL
Output Transition Time
Propagation Delay Time
•
Propagation Delay Time
••
Propagation Delay Time
••
t11.1i
tOil-I!.
tpLli
tpflL
,
MIN.
TYP.
MAX.
-
4
8
-
10
17
UNIT
ns
tpl2
RL=lkQ
-
11
17
trVl.
R!.=lkQ
-
10
17
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =t,=6ns)
Ta-25"C
Ta--40 -85"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
2.0
75
95
30
t11.H
Output Transition Time
4.5
8
15
19
tniL
6.0
7
13
16
2.0
40
100
125
tp[.H
Propagation Delay Time
4.5
12
25
20
• tpHL
6.0
10
17
21
ns
26
100
125
2.0
Propagation Delay Time
RL=lkQ
tp[2
12
20
25
4.5
••
6.0
11
17
21
2.0
40
100
125
Propagation Delay Time
RL=lkQ
12
20
4.5
25
t~
••
10
17
21
6.0
Input Capacitance
5
CI:\
10
10
Output Capacitance
3
COLT
pF
16
Power Dissipation Capacitance CpDW TC74HC266A
TC74HC7266A
30
Note (1) C ID 15 defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IeetpO=C pD - Va:;- fl:,\ +Ia:; 14(per Gate)
-
• for TC74HC7266A only
•• for TC74HC266A only
HC-460
----TC74HC273API AF I AFW
OCTAL D-TYPE FLIP FLOP WITH CLEAR
The TC74HC273A is a high speed CMOS OCTAL D
TYPE FLIP FLOP fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissi pation.
Information signals applied to D inputs are transfered
to the Q outputs on the positive going edge of the clock
pulse.
When the CLEAR input is held "L", the Q outputs are
at a low logic level independent of the other inputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. fMAJr 48MHz(typ.)at Vcr;=5V
• Low Power Dissipation ............... Icr;=4I.tA(Max.)at Ta=25"C
• High Noise Immunity .............. · VNIH =V NIL =2896 Vcr;(Min.)
• Output Drive Capability .. · .... ····· 10 LSTTL Loads
• Symmetrical Output Impedance ·.. 1Iool=IOL =4mA(Min.)
• Balanced Propagation Delays ...... t pLH '" tpHL
• Wide Operating Voltage Range'" Vcr;(opr)=2V-6V
• Pin and Function Compatible with 74LS273
P(OIP20-P-300A)
a~a~
1
F(SOP20-P-300)
1
FW(SOL20-P-300)
PIN ASSIGNMENT
CLEAR
01 2
01 3
02 4
02 5
03 6
03 7
04 8
04 9
GND10
20 Vee
19 OS
18 08
17 07
1607
15 06
14 06
13 05
12 05
11 CLOCK
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
INPUTS
OUTPUTS
FUNCTION
CLEAR
D
CLOCK
a
L
x
X
L
H
L
L
-
H
H
H
-
H
X
S
S
L
an
Clear
No change
ClR
ClK
01
02
03
D4
Q4
OS
06
Q6
07
08
X: Don't care
HC-461
01
Q2
Q3
Q5
Q7
Q8
TC74HC273AP/AF/AFW---------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
VQl,i
11K
10K
loor
lee
PD
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)·/180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
rnW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to S5"C a derating factor of
-lOmW/"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Outpu t Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
o -Vee
o-Vee
-40 - 85
o - 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o- 400(Vee=6.OV)
SYMBOL
Vee
VIN
Voor
Topr
t r • tf
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
V()i
Low-Level
Output Voltage
Voc
Input Leakage Current
Quiescent Supply Current
liN
lee
TEST CONDITION
VIN=
VIHorVIL
VIN=
VIHorVIL
I()i =-20J.lA
I()i - 4 mA
Idi =-5. 2mA
IOL =20 J.lA
loc -4 mA
IOL =5.2mA
VIN -Vee or GND
VIN -Vcr:. or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-462
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
l.5
V
3.15
4.2
0.5
0.5
V
l. 35
l. 35
l.8
l.8
l.9
2.0
l.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.1
0.0
0.1
0.10.1
0.0
V
0.1
0.1
0.0
0.26
0.17
0.33
0.33
0.26
0.18
+0.1
+l.0
J.lA
4.0
40.0
MIN.
l.5
3.15
4.2
- - - - - - - - - - - - - - TC74HC273AP/AF/AFW
TIMING REQUIREMENTS(lnput t r=tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
tW(L)
tW(H)
Minimum Pulse Width
(CLEAR)
tW(L)
Minimum Set-up Time
ts
Minimum Hold Time
th
Minimum Removal Time
(CLEAR)
trem
Clock Frequency
f
Voc
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
95
ns
19
16
0
0
0
65
13
11
5
MHz
24
28
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
75
15
13
0
0
0
50
10
9
6
30
35
AC ELECTR ICAl CH ARACTERISTICS(C L =15pF. Vcc=5V. Ta=25"C)
PARAMETER
Output Transition Time
Propagation Delay Time
(CLOCK-Q)
Propagation Delay Time
(CLEAR-Q)
Maximum Clock Frequency
SYMBOL
TEST CONDITION
t1U{
t"\liL
tpUi
toHL
tpUi
toHL
fMAX
MIN.
TYP.
MAX.
-
4
8
-
15
25
-
16
27
40
67
UNIT
ns
MHz
AC ELECTRICAL CHARACTERISTICS(CL =50pF.lnput t r =tf=6ns)
Ta-25"C
Ta- 40 -85"C
PARAMETER·
SYMBOL TEST CONDITION
UNIT
Voc MIN. TYP. MAX. MIN. MAX.
2.0
25
75
95
tTI.H
Output Transition Time
4.5
7
15
19
tTi-n.
6.0
6
13
16
2.0
145
180
54
Propagation Delay Time
tpUi
ns
4.5
18
29
36
(CLOCK-Q)
tpHL
6.0
15
25
31
2.0
200
60
160
Propagation Delay Time
tpUi
4.5
20
32
40
(CLEAR-Q)
tpHL
6.0
17
27
34
2.0
6
18
5
Maximum Clock
- MHz
4.5
fMAX
24
30
56
Frequency
6.0
28
35
66
Input Capacitance
CIN
5
10
10
pF
Power Dissipation Capacitance CPD(l)
43
CR) IS defmed as the value of the mternal eqUivalent capacitance which IS calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ioc(P}=CR) • VOC· fLN +Ia; 18(per Flip Flop)
And the total eR) when n pcs. of Flip Flop operate can be gained by the following equation:
Cm(total)=32+li· n
HC-463
TC74HC273AP/AF/AFVV-------------------------------
SYSTEM DIAGRAM
01
02
01
03
02
04
03
05
04
HC-464
06
05
07
06
08
07
08
-----TC74HCT273AP/AF/AFW
OCTAL D-TVPE FLIP FLOP WITH CLEAR
The TC74HCT273A is a high speed CMOS OCTAL D
TYPE FLIP FLOP fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Their inputs are compatible with TTL, NMOS, and
CMOS output voltage levels.
Information signals applied to D inputs are transferred
to the Q outputs on the positive going edge of the clock
pulse.
When the CLEAR input is held low, the Q outputs are
at a low logic level independent of the other inputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. f\1Ax=76MHz(typ.)at Vcc=5V
• Low Power Dissipation ............... Icc=4# A(Max.)at Ta=25"C
• Compatible with TTL outputs ......... VIH = 2V(Min.)
VIL =O.8V(Max.)
• Wide interfacing ability ........ · LSTTL, NMOS, CMOS
• Output Drive Capability ............ 15 LSTTL Loads
• Symmetrical Output Impedance ... , Irnl=IOL =6mA(Min.)
• Balanced Propagation Delays ...... tpLH"'tpHL
• Pin and Function Compatible with 74LS273
P(DIP20-P-300A)
~~~~
1
1
F(SOP20-P-300)
FW(SOL20-P-300)
PIN ASSIGNMENT
CLEAR 1
20 Vee
a1
19 a 8
18 08
17 07
2
3
4
5
6
7
8
01
02
a2
a3
03
04
a4 9
16 a7
15 a6
14 06
13 05
12 a5
GN010
11 CLOCK
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
INPUTS
OUTPUTS
FUNCTION
CLEAR
D
CLOCK
0
L
X
X
L
Clear
H
L
S
L
-
H
H
S
H
-
H
X
L
On
No change
X : Don't care
HC-465
ClR
ClK
01
02
03
D4
Ql
Q2
Q3
Q4
os
as
D6
07
08
Q6
Q7
Q8
TC74HCT273AP/AF/AFW - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature IOsec
SYMBOL
Vee
VI:"
VOLT
11K
10K
IOLT
lee
PD
Tstg
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP)*/180(SOIC)
-B5 -150
300
*500m W in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-lOmW/'C shall be applied
until 300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
InputRise and Fall Time
SYMBOL
VALUE
Vee
VI:>;
4.5 - 5.5
0- Vee
0-- Vee
-40 - 85
0-500
VOLT
Topr
t r , te
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
1'1lgh - Level
Output Voltage
Low Level
Output Voltage
3 -titate Uutput
Off-State Curren
lnput Leakage Current
Quiescent Supply Current
TEST CONDITION
MIN.
1
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
4 4
4 18
4 5
4 31
o0
0.17
-
V
5.5
4.5
VOO
Va..
ICE
II:"
lee
~Icc
1
VI:'; =VIH or VIL
VOl,;T =Vcc or GND
VI:" -Vee or GND
VI:>; =Vcc or GND
PER INPCT:VI:" =O.5V or 2. 4V
OTHER INPCT:VI:>; or GND
Ta= 40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
Vee
4.5
5 5
4 5
4 5
4 5
4.5
5.5
-
-
5.5
5 5
-
5;5
-
-
HC-466
o1
o 26
±0.5
+0.1
4 0
2.0
4 4
4.13
-
o1
o 33
V
±5.0
Il A
+1.0
40 0
Il A
2.9
mA
- - - - - - - - - - - - - - - - TC74HCT273AP/AF/AFW
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
Minimum Pulse Width
(CLOCK)
SYMBOL TEST CONDITION
tW(L)
Vcr.
-
4.5
5.5
tw(H)
Minimum Pulse Width
(CLEAR)
tW(L)
4.5
5.5
Minimum Set-up Time
ts
4.5
5.5
Minimum Hold Time
~
4.5
5.5
trem
4.5
5.5
-
4.5
5.5
-
Minimum Removal Time
(CLEAR)
Clock Frequency
f
Ta
Ta-25"C
LIMIT
TYP.
-
-
40 -85"C UNIT
LiMIT
15
14
19
17
15
14
19
17
10
10
13
13
5
10
6
13
10
9
13
12
30
35
24
28
MHz
MAX.
UNIT
ns
AC E LECTRICA L CHARACTERISTICS(C L =15pF, Vcc=6V, Ta=26"C)
PARAMETER
SYMBOL
Output Transition Time
tn.H
tTI-lL
tpLH
tDHL
tpLH
tDHL
-
4
8
-
15
25
-
18
28
~\1AX
40
90
Propagation Delay Time
(CLOCK-Q)
Propagation Delay Time
(CLEAR-Q)
Maximum Clock Frequency
TEST CONDITION
MIN.
TYP.
ns
Mtlz
AC ELECTRICAL CHARACTERISTICS(CL =50pF,lnput t r =t,=6ns)
Ta-25"C
-,!,a 40 -85"C UNIT
PARAMETER
SYMBOL TEST CONDITION
Vcc MIN. TYP. MAX. MIN .._MAX.
Output Transition Time
tn.H
t11-JL
4.5
5.5
Propagation Delay Time
(CLOCK-Q)
tpLH
tpHL
4.5
5.5
Propagation Delay Time
(CLEAR-Q)
tpLH
tpHL
4.5
5.5
-
-
-
9
8
15
14
19
17
30
27
22
18
32
29
-
-
19
18
38
34
ns
40
36
- MHz
24
71
28
81
i
Input Capacitance
C,;>;
5
10
10
pF
Power Dissipation Capacitance CpDm
~
29
Note(l) em IS defmed as the value of the mternal equivalent capacitance which IS calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCml=Cm Voc o fN +IOC 18(per Flip Flop)
And the total em when n pcs. of Flip Flop operate can be gained by the following equation:
CroCtotal)=18+11 n
Maximum Clock
Frequency
4.5
5.5
fMAX
0
0
HC-467
30
35
-
-
-
TC74HCT273AP/AF/AFW - - - - - - - - - - - - - - - - SYSTEM DIAGRAM
01
02
01
03
02
04
03
05
04
HC-468
06
05
07
06
08
07
08
- - - - - - T C 7 4 HC279API AF
QUAD
S-R
LATCH
The TC74HC279A is a high speed CMOS QUAD S-R
LA TCH fabncated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Each latch has an independent Q output and Set and
Reset inputs. S and It are active low. When S input is low,
the Q output goes high and when It input is low, the Q
output goes low. When both S and It are low, Stakes
precedence resulting Q=low. When both of S and It are
held high,Q output doesn't change.
All inputs are equipped with protection circuits against
static discharge or trasient excess voltage.
1
P(DIPI6-P-300A)
16~
F(80PI6-P-300)
FEATURES:
• High Speed ..•.••........................... tpcF12ns(typ.)at Vcc=5V
• Low Power Dissipation •.•.•..•••.•.•• Icc=2t.tA(Max.)at Ta=25"C
• High Noise Immunity··· .. •·······•• VNIH=Vf>;lL=28" Vcc(Min.)
• Output Drive Capability'·' .....•... 10 LSTTL Loads
• Symmetrical Output Impedance ···1 Ia;I=Ia., =4mA(Min.)
• Balanced Propagation Delays .•••.• tpLH"'tpHI.
• Wide Operating Voltage Range .•• Vcc(opr)=2V-6V
• Pin and Function Compatible with 74LS279
PIN ASSIGNMENT
lR
16 Vee
1
1548
181 2
182 3
144R
10 4
1340
2R 5
12 352
28
6
11 351
20 7
103R
GND 8
9 30
(TOP
TRUTH TABLE
VIEW)
IEC LOGIC SYMBOL
INPUT
OUTPUT
SI
R
a
H
H
an
L
H
H
H
L
L
L
L
H
NOTE:
an - - The level of a before the indicated input
condition wera established.
#
- - For latches with dobla II input.
H=Both II input high
L=One of both inputs low
HC-469
TC74HC279AP/AF--------------------------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vcr;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10see
SYMBOL
Vcr;
VIN
Vcm
11K
10K
Icm
Icr;
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vcr; +0.5
-0.5 -Vcr;+0.5±20
±20
±25
±50
500(DIP)*/180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
o-Vcr;
o -Vcr;
-40 - 85
o - 1000(Vcr;=2.0V)
0- 500(Vcr;=4.5V)
0- 400 (Vcr;=6.0V)
SYMBOL
Vcr;
VIN
Vcm
Topr
t r • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
V(li
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
liN
Icr;
TEST CONDITION
VIN=
VlHorVIL
VIN=
VlHorVIL
l(li =-20/.LA
l(li - 4 rnA
l(li =-5.2mA
IOL =20 /.LA
IOL -4 rnA
IOL =5.2mA
VIN -Vcr; or GND
VIN -Vee or GND
Vcr;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-470
Ta-25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.18
4.31
4.13
5.68
5.80
5.63
0.1
0.1
0.0
0.0
0.1
0.1
V
0.1
0.1
0.0
0.33
0.26
0.17
0.33
0.26
0.18
+0.1
+1.0
/.LA
2.0
20.0
MIN.
1.5
3.15
4.2
--__----------------------------TC74HC279AP/AF
AC ELECTRICAL CHARACTERISTICS(CL=15pF,Vcc=5V,Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTHL
-
4
8
Propagation.1?elay Time
(Sl,S2-Q)
tpLH
tpHL
-
12
22
Propagatio!! Delay Time
(S-Q)
tpLH
tpHL
-
9
17
PropagatioE. Delay Time
(R-Q)
tpLH
tpHL
-
11
20
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
ns
AC ELECTRICAL CHARACTERISTlCS(C L =50pF,lnput t r =t,=6ns)
Ta-25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
2.0
30
75
95
tTLH
Output Transition Time
4.5
8
15
19
tTIiL
6.0
7
13
16
2.0
45
130
165
Propagation..Qelay Time
tpLH
4.5
26
33
15
ns
(Sl,S2-Q)
tpHL
6.0
13
22
28
2.0
125
38
100
Propagation Delay Time
tpLH
4.5
12
20
25
(S-Q)
tpHL
6.0
17
21
10
2.0
42
120
150
Propagation Delay Time
tpLH
4.5
24
30
14
(R-Q)
tpHL
6.0
26
12
20
Input Capacitance
CIN
10
5
10
pF
Cpo(l)
Power Dissipation Capacitance
18
Note(l) Cm is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
la:;tpll=Cm • Va;" f~ +10:; 14{per circuit)
PARAMETER
SYMBOL TEST CONDITION
Vcr;
HC-471
MIN.
TC74HC279AP/AF--------------------------------
SYSTEM
DIAGRAM
3R -""------1-..-/
28
6
2R
5
HC-472
------TC74HC280AP/AF
8-CHANNEL MULTIPLEXER
The TC74HC280A is a high speed CMOS 9-BIT
PARITY GENERATOR fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HC280A is composed of nine data inputs A
thru I and odd/even parity outputs LODD and LEVEN.
The odd parity output is high when an odd number of
data inputs are high. The even parity output is high when
an even number of data inputs are high.
The word-length capability is easily expanded by
cascading.
All inputs are equipped with protection circuits aainst
static discharge or transient excess voltage.
1
P(DIP14-P-300)
14~
1
F (SOP 14-P-300)
PIN ASSIGNMENT
FEATURES:
• High Speed .............................. ~=22ns(typ.)at Vee=5V
• Low Power Dissipation ............ I cc =4flA(Max.)at Ta=25"C
• High Noise Immunity··············· VN1 H=VXIL28% Vee (Min.)
• Output Drive Capability'" ......... 10 LSTTL Loads
• Symmetrical Output Impedance '" I 100 I =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH"otpHL
• Wide Operating Voltage Range '" Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS280
Vee
G
H
2
F
NC
3
E
4
0
5
10 C
lODD 6
9 B
7
B A
I EVEN
GND
(TOP VIEW)
NC : No Connection
TRUTH TABLE
Number of inputs
IEC LOGIC SYMBOL
Outputs
A
B
A through I that are High
C
IEVEN
IOOO
0
E
F
0,2,4,6,8
H
L
1,3,5,7,9
L
H
HC-473
G
H
I
(I)
2K
(I)
(10)
(11)
(12)
(13)
(1)
(2)
(4)
(5)
1:
EVEN
(6)
1:
ODD
TC74HC280AP/AF---------------------------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI"
VOLT
11K
10K
IOLT
lee
PI)
Tstg
TI.
UNIT
V'
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)·/180(MFP)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65·C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee=4.5V )
o -- 400(Vee =6.0V)
SYMBOL
Vee
Vlx
I
VOLT
Topr
tr • tc
I
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
VOl.
Input Leakage Current
Quiescent Supply Current
I I"
ICC
TEST CONDITION
VI:" =
VIHorVIL
VI" =
VNiorVIL
100 =-20Jl A
la-I --4 rnA
Iell =-5. 2rnA
lex. =20 IJ.A
I Ol. -4 rnA
101. =5.2mA
VI" -Vee or GND
VI" -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-474
Ta-25"C
Ta- 40 -85"C UNIT
·TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
5.9
6.0
4.31
4. 13
4.18
5.63
5.68
5.80
0.1
0.1
0.0
0.1
0.0
0.1
V
0.1
0.1
0.0
0.26
0.33
0.17
0.33
0.26
0.18
±1,0
+0.1
JlA
40.0
4.0
MIN.
1.5
3.15
4.2
----------------TC74HC280AP/AF
AC ELECTRICAL CHARACTERISTlCS(C L =16pF, Vcc=6V, Ta=26"C)
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTHL
tpLH
t >HL
Propagation Delay Time
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
22
35
UNIT
ns
AC ELECTRICAL CHARACTERISTlCS(C L =50pF,lnput t r =t,=6ns)
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
95
75
30
tTLH
Output Transition Time
8
15
19
tTHL
7
16
13
ns
250
80
200
tpLH
Propagation Delay Time
26
40
50
tpHL
22
34
43
Input Capacitance
5
10
10
C1"l
pF
Power Dissipation Capacitance
CpDW
61
Note (1) C AJ is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
1ee (:P,,=C PD· VCC· f 1:\ +1 CC
PARAMETER
SYMBOL
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
HC-475
MIN.
TC74HC280AP/AF---------------SYSTEM
DIAGRAM
H
F
G
E
1000
o
c
I EVEN
HC-476
B
A
-----TC74HC283AP/AF/AFN
4-BIT BINARY FULL ADDER
The TC74HC283A is a high speed CMOS 4-BIT
BINARY FULL ADDER fabricated with silicon gate
C~OS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Sum (~) outputs are provided Cor each bit and a
resultant carry (C4) is obtained from the Courth bit.
This adder features full internal look-ahead across all
four bits.
A 4 X n bit binary adder is easily built up by cascading
the HC283A without any additional logic.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd=17ns(Typ.)at Vcc=5V
• Low Power Dissipation ............ Icc =4IlA(Max.)at Ta=25"C
• High Noise Immunity··············· VI\1H =Vl\IL =28% Vcc(Min.)
• Output Drive Capability'" ....... ,. 10 LSTTL Loads
• Symmetrical Output Impedance "'IIm I=Ia.=4mA(Min.)
• Balanced Propagation Delays······ tpLH '" tpHL
• Wide Operating Voltage Range ... Vcc (opr)=2V-6V
• Pin and Function Compatible with '14LS283
1
P(DIP16-P-300A)
F(SOP16-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
I2
B2
A2
16 Vce
15 B3
14 A3
2
3
4
13 I3
12 A4
II
A1
B1
5
6
11
CO
7
10 I4
GND
8
C4
B4
(TOPVIEWI
TRUTH TABLE(l bit)
BLOCK DIAGRAM
INPUTS
OUTPUTS
Bn
An
cn-1
In
en
L
L
L
L
L
L
L
H
H
L
L
H
L
H
L
L
H
H
L
H
H
L
L
H
L
H
L
H
L
H
H
H
L
L
H
H
H
H
H
H
CARRY
C4
B4--------+-4-4--r~~
A4----r---+-;-;-~~~
B3--------+-4---~~~
A3----r---+-;---~~~
B2--------;------i~~
A2----r---+------L~~
Bl--------------~~~
Al----r----------L~~
CO
HC-477
TC74HC283AP/AF/AFN - - - - - - - - - - - - - SYSTEM DIAGRAM
84
C4
A4
BS
:E4
AS
:ES.
B2
A2
:E2
Bl
HC-478
--------------TC74HC283AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vex:;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vex:;
VIN
VOL'T
11K
10K
lOUT
lex:;
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vex:;+0.5
-0.5 -Vex:;+0.5
±20
±20
±25
±50
500(DIP)·/180(MFP)
-65 -150
300
UNIT ,
*500mW in the range of Ta=
V
-40"C- 65"C. From Ta=65"C
V
to 85"C a derating factor of
V
-lOmW/"C shall be applied
until300mW.
rnA
rnA
rnA
rnA
mW
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
O-Vex:;
O-Vex:;
-40 - 85
o - 1000(Vex:;=2.0V)
0- 500(Vex:;=4.5V)
0- 400(Vex:;=6.0V)
SYMBOL
Vex:;
VIN
Vour
Topr
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Va;
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
lIN
lex:;
TEST CONDITION
VIN=
VuiorVIL
VIN=
VIHorVIL
Ia; =-20J,tA
Ia; - 4 rnA
Ia; =-5.2mA
lot =20 J,tA
IOL -4 rnA
IOL =5.2mA
VIN -'Vex:; or UND
VIN -Vex:; or GND
Vex:;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HG-479
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
1.5
V
3. 15
3.15
4.2
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.18
4.31
4.13
5.68
5.80
5.63
0.0
0.1
0.1
0.1
0.0
0.1
V
0.1
0.1
0.0
0.33
0.26
0.17
0.26
0.33
0.18
±O.l
±1.0 J,tA
4.0
40.0
MIN.
-
-
TC74HC283AP/AF/AFN - - - - - - - - - - - - - -
AC ELECTRICAL CHARACTERISTICS(CL =16pF,Vcc=6V,Ta=26"C)
PARAMETER·
Output Transition Time
Propagation Delay Time
(Co-:En)
. Propagation Delay Time
(Co -C 4 )
Propagation Delay Time
(An,Bn- :En)
Propagation Delay Time
(An,Bn-C4)
SYMBOL
TEST CONDITION
tTLH
tTHL
tpLH
toHL
tpLH
toHL
tpLH
toHL
tpLH
toHL
MIN.
TYP.
MAX.
-
4
8
-
17
26
-
17
26
-
23
37
-
21
34
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =tf=6ns)
Ta-25"C
Ta--40 -85"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Va:, MIN. TYP. MAX. MIN. MAX.
2.0
75
30
95
tTLH
Output Transition Time
4.5
8
15
19
tlliL
6.0
7
13
16
2.0
150
190
60
Propagation Delay Time
tpLH
4.5
30
38
20
(Co-:En)
tpHL
6.0
26
32
17
2.0
150
190
60
Propagation Delay Time
tpLH
4.5
30
38
ns
20
(C O-C 4 )
tpHL
6.0
26
32
17
2.0
95
210
265
Propagation Delay Time
tpLH
4.5
27
42
53
(An,Bn- :En)
tpHL
6.0
22
36
45
2.0
80
195
245
Propagation Delay Time
tpLH
25
4.5
39
49
(An,Bn-C 4 )
tpHL
20
6.0
33
42
Input Capacitance
C IN
5
10
10
pF
Power Dissipation Capacitance CPOW
126
Note(1) Cpo IS defmed as the value of the mternal equivalent capacitance which IS calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia:,~=CPO • Va:,. fr.: +Ia:,
HC-480
------TC74HC298API AF
QUAD 2-CHANNEL MULTIPLEXER WITH OUTPUT REGISTER
~------------------------,
The TC74HC298A is a high speed CMOS 2-CHANNEL
MULTIPLEXER fabricated with silicon gate C2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It contains a 4-bit 2-channel multiplexer and a 4-bit
output register. When the word select input{W.S.) is held
low.the data of word I(Al.Bl.Cl.Dl)is selected and is
applied to the registers. When W.S. is held high.the data
of word 2(A2.B2.C2.D2)will be applied to the registers.
This selected data is transferred to the output(QA.QB.
QC.QD)on the negative going transition of CLOCK.
All inputs are equipped with protection circuits against
static dischage or transient excess voltage.
16~
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
FEATURES:
• High Speed .............................. ~'AAX"'73MHz(Typ.)at Vee=5V
• Low Power Dissipation ............ Iee =4ttA(Max.)at Ta=25"C
• High Noise Immunity ............... V~IH=V!'.lL28" Vee (Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance .. , 1100 I =10.. =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range •.. Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS298
B2
16
2
15 QA
A1
B1
3
4
14 QB
C2
5
12 QD
6
11 CK
01
7
10 W.S.
(TOP
W.S.
(10)
MUX
Gl
CK
Al
A2
Bl
B2
Cl
C2
01
02
HC-481
(15)
OA
(14)
OB
(13)
OC
(12)
00
13 QC
02
GND 8
IEC LOGIC SYMBOL
Vee
A2
9
VIEW)
C1
TC74HC298AP/AF---------------TRUTH TABLE
INPUTS
WORD
SELECT
L
H
X
OUTPUTS
CK
aA
aB
ac
aD
,.",
a1
82
aAO
b1
b2
aBO
c1
c2
aDO
d1
d2
aDO
""l...
.r
X
: Don't care (Including transition)
a1, a2········· : The Level of steady-state Input at A 1. A2. etc.
aAO. aBO··· : The level of aA, as. etc. entered on the most
recent negative transition of the clock input.
SYSTEM DIAGRAM
WORD
SELECT
A1
0
A2
B1
B2
4
1
C1
9
C2
6
01
7
02
6
CK
11
HC-482
Q
--------------------------------TC74HC298AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
. DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vex;
VI:"
Vex.T
11K
10K
100T
lex;
PD
Tstg
TI.
VALUE
-0.5 -7
-0.5 -Vex; +0.5
-0.5 -Vex;+0.5
±20
±20
±25
±50
500(DIP)'/180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
mA
mA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 85"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Vex;
VI:"
VOlT
Topr
Input Rise and Fall Time
t r • tc
VALUE
2-6
0- Vee
o -Vee
-40 - 85
o- 1000(Vex;=2.0V)
0- 500(Vee =4.5V)
o- 400(Vee =6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VII-I
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
Vex.
Input Leakage Current
Quiescent Supply Current
I I:"
lex;
TEST CONDITION
10-1 =-20p A
VI:" =
VIHorVIL 100 --4 rnA
100 =-5.2mA
VI:" =
VIHorVIL
Ia.. =20 p.A
Ia.. -4 rnA
Ia.. =5.2mA
VI:" -Vee or GND
VI:" -Vex; or GND
Vex;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-483
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.1
O. I
0.0
0.1
0.1
0.0
V
O. I
0.1
0.0
0.33
0.26
0.17
0.33
0.26
0.18
±0.1
±l.O p.A
40.0
4.0
MIN.
1.5
3.15
4.2
-
TC74HC298AP/AF--------------------------------
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CK)
twCl,>
tW(}i)
Minimum Set-up Time
(A, B, C, D)
ts
Minimum Set-up Time
(W. S.)
ts
vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6~0
Minimum Hold Time
(A,B,C,D)
tb
Minimum Hold Time
(W. S.)
tb
Clock Frequency
f
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6 0
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
65
13
11
95
19
ns
16
30
6
5
0
0
0
6
27
MHz
33
Ta-25"C
LIMIT
TY.t'.
75
15
13
50
10
9
75
15
13
25
5
5
0
0
0
7
35
41
-
-
AC ELECTR ICA L CH A RACTERISTICS( C L =15pF. Vcc=5V. Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
-
4
8
Propagation Delay Time
(CK-Q)
tTLH
tlllL
tpLH
tpHL
-
12
21
Maximum Clock Frequency
fMAX
38
73
-
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =50pF.lnput t r =t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Output Transition Time
Propagation Delay Time
(CK-Q)
tpLH
tpHL
MaXimum Clock
Frequency
f~1AX
Vee
MIN.
7
35
41
-
Ta-25"C
Ta= 40 -85"C UNIT
TY.t'. MAX. MiN. MAx.
30
75
95
8
15
19
7
13
16
45
125
155
ns
15
25
31
13
21
26
22
667
28
79
33
5
10
10
pF
C!!,\
Input 9apacitance
Power Dissipation Capacitance Cpo(l)
~
Note(l) Cm is deCined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCtpl=C PD VOCo fe, +10:: 14(per bit)
And the total Cpo when n-bits operate can be gained by the following equation:
CpO (total)=27+12 n
-
0
0
HC-484
-
-
-
_ _ _ _ _ _ TC74HC299AP/AF
TC74HC323AP/AF
TC74HC299AP/AF
TC74HC323AP/AF
8-BIT PIPO SHIFT REGISTER
8-BIT PIPO SHIFT REGISTER
The TC74HC299A and TC74HC32SA are high speed CMOS
8-BIT PIPO SHIFT REGISTER fabricated with silicon
gate C~OS technology.
They achieve the high speed operation similar to
equivalent LSTTL ·while maintaining the CMOS low power
dissipation.
They have four modes (HOLD, SHIFT LEFT. SHIFT
RIGHT and LOAD DATA) controlled by the two selection
inputs (SO, S1).
When one or both enable (01, (2) are high, the eight
110 outputs are forced to the high-impedance state;
however, sequential operation or clearing of the register is
not affected. Clear function on the TC74HC299A is
asynchronous to CLOCK, while the TC74HC32SA is
cleared synchronous to CLOCK.
All inputs are equipped with protection circuits against
static discharge or transient· excess voltage.
FEATURES:
• High Speed .............................. fMAJ(=42MHz(typ.)at Voc=5V
• Low Power Dissipation •.••.••.•.•• IOC =4#A(Max.)at Ta=25"C
• High Noise Immunity··············· V;"lH=VN1L =28111 Voc(Min.)
• Output Drive Capability············ 15 LSTTL Loads For QA-QH
10 LSTTL Loads For QA',QH'
• Symmetrical Output Impedance ..•
lloi I=IOL =6mA(Min.) For QA-QH
lloil =IOL =4mA(Min.) For QA', QH'
• Balanced Propagation Delays ....•• tpLH'" tpHL
• Wide Operating Voltage Range .•• Voc (opr)=2V-6V
• Pin and Function Compatible with 74LS299/323
IEC LOGIC SYMBOL
TC7.HC299A
WITH ASYNCHRONOUS CLEAR
WITH SYNCHRONOUS CLEAR
20
1
P(DIP20-P-300A)
20~
1
F(SOP2O-P-300)
PIN ASSIGNMENT
SO
G1
G2
G/OG
E/OE
1
20 Vee
2
3
4
5
19 S1
18 SL
17 QH'
16 H/OH
15F/OF
140/00
13 BlOB
12 CK
11 SR
C/OC 6
A/OA 7
OA'8
CLR 9
GND10
(TOP VIEW)
APPLICATION NOTES
TC7.HC323A
QA·
HC-485
1) Do not apply a signal to any
bus terminal when it is in the out
put mode. Damage may result.
2) All floating (high impedance)
bus terminals must have their
input levels fixed by means of pull
up or pull down resistors .or bus
terminator IC's such as the
TOSHIBA TC40117BP.
TC74HC299APIAF
TC74HC323AP/AF .....- - - - - - - - - - - - - - - TRUTH TABLE
INPUTS
MODE
CLR
CK
G2* (299A) (323A)'
FUNCTION SELECT OUTPUT CONTROL
SO
S1
H
z
G1·
SERIAL
SL
SR
INPUTSI
OUTPUTS
OUTPUTS
A/aA
aA'
H/aH
aH'
L
X
X
L
Z
L
Z
X
X
X
X
H
L
L
L
X
L
L
L
L
X
X
X
L
.J
~LEAR
L
L
X
X
L
L
X
X
L
L
L
L
.J
HOLD
H
X
X
X
aAO
aHO
aAO
aHO
X
L
L
L
L
SHIFT
H
X
H
H
aGn
H
aGn
L
L
L
H
.J
RIGHT
H
L
X
L
L
aGn
L
aGn
L
H
L
.J
SHIFT
H
H
H
X
aBn
H
aSn
L
H
L
L
.J
LEFT
H
aSn
I
aSn
H
L
L
X
L
L
L
.J
LOAD
H
X
h
X
X
H
a
a
h
H
X
.J
When one or both outp ut controll are hi gIh, the eight input/output terminals are in the high impedance
* state; however sequential or clearing of the register is not affected,
Z :High Impedance
anO:The level of An before the indicated steady-state input conditions were established,
Qnn:The level of an before the most recent active transition indicated by ~ or t,
a,h :The level of the steady-state inputs A, H, respectively,
X :Don't care
TIMING CHART
CLOCK
MODE
{S 0
CONTROL
INPUTS
S1
CITAii
SERIAL
DATA
INPUTS
r
R
SL
OUTPUTS DA'
AIDA
BlOB
CIDC
INPUTS
IDUTPUTS
DIDO
E/DE
F/OF
G/OG
H/OH
OUTPUTS DH'
m
:wi,;
~;,'
~ ., ..,
ASYNC SYNC LOAD
CLEAR CLEAR
299A
323A
SHIFT LEFT
SHIFT RIGHT
HOLD
,
...
ASYNC SYNC
CLEAR CLEAR
299A
323A
HC-486
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC299AP/AF
TC74HC323AP/AF
SYSTEM DIAGRAM(TC74HC299A)
•
OA·
A/OA
BlOB
C/OC
0/00
EIOE
Equl.. I"'t Clrculll
FIOF
G/OG
SYSTEM DIAGRAM(TC74HC323A)
SO
51
131
G2
lIE Equivalent Clreulll
.
CUi
~9---+-++r+------.-!J-..
4. 4. 4.
~-++t-!- lljLjLl.
••
~~'··fi·;.tt=·st-CiiT
.. i i•.. II •.. i I•.. J-k. i .
··crOA·
A/OA
13
BlOB
C/OC
HC-487
0/00
E/OE
F/OF
G/OG
H/OH OW
TC74HC299AP/AF _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC323AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Supply Voltage Range
Vee
DC Input Voltage
Vr'\
DC Output Voltage
VeLT
Input Diode Current
I'K
Output Diode Current
101<
( Q • )
DC Output Current
H
ICLT
(QA -Q )
DC Vee/Ground Current
lee
Power Dissipation
~)
Storage Temperature
Tstg
Lead Temperature 10sec
TL
UNIT
V
V'
V
mA
mA
VALUE
-0.5-7
-0.5 -Vcc+0.5
-0.5 -Vee+0.5
±20
±20
±25
±35
±75
500(DIP)*/180(MFP)
-65 -150
300
*500mW in the range of Ta=
-40OC- 65"C. From Ta=65"C
to 85"C a derating factor of
-IOmW/OC shall beapplied
until 300m W.
mA
mA
mW
"C
"C
RECOMMEND.ED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Input Rise and Fall Time
tr • tc
Vee
V,,\
VOLT
Topr
UNIT
V
V
V
"C
VALUE
2-6
0- Vee
o-Vee
-40 - 85
o- 1000(Vcc =2.0V)
0- 500(Vee =4.5V)
o- 400(Vee=6.0V)
.os
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIIi
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VCJi
TEST CONDITION
Vee
' 2.0
4.5
6.0
2.0
1 4. 5
6.0
2.0
VI:\=
101; =-20 IJ, A 4.5
V'HorV'L
6.0
,Ia; --4 mA 4.5
QA' .QH· lOll =-5. 2mA 6.0
101 , =-6 mA 4.5
QA-Q" 101-, =-7.8mA 6.0
2.0
V,,\ =
IOL =20 IJ, A 4. 5
V'HorV'L
6.0
IOL -4 mA 4.5
QA' .Q/i' IOL =5.2mA 6.0
I 101. =6 mA 1 4. 5
Q... -Q" i lQL =7. SmA i 6.0
:
I
V,:" -V"I or V 11_
6.0
VOLT =Vcc or GND
V,,, -Vee or GND
! 6.0
V,,, -Vee or GND
I 6.0
I
I
Low-Level
Output Voltage
3-State Output
orC-State Current
Input Leakage Current
Quiescent Supply Current
VOIL
ICE
I,,,
lee
I
HC-488
MIN.
1.5
3.15
4.2
-
-
1.9
4.4
5.9
4.18
5.68
4. 18
5.68
-
-
-
-
Ta- 40 -85°C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
l. 35
1. 35
1.8
1.8
2.0
l.9
4.5
4.4
5.9
6.0
V
4.31
4. 13
5.80
5.63
4.31
4.13
5.80
5.63
O. I
O. 1
0.0
0.0
O. I
O. I
0.0
O. 1
O. 1
V
0.17
0.26
0.33
0.18
0.26
0.33
0.33
0.17
0.26
0.26
0.18
0.33
I
-
I
I
I -
-
±0.51
-
-
-
±O.I
4.0 I
-
-
-
i ±5.0
±1.0
! 40.0
IJ,A
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC299AP/AF
TC74HC323API AF
TIMING RECOMMENDED OPERATING CONDITIONS(lnput tr =tf=6ns)
Ta-25"C
PARAMETER
SYMBOL TEST COXDlTIO~
LIlVIIT
TYP.
Va;
75
2.0
Minimum Pulse Width tWO-I)
15
4.5
(CK)
t\l"(l.)
13
6 0
75
2.0
Minimum Pulse Width
t\\,(U
15
4.5
(CLR)*
13
6.0
100
2.0
Minimum Set-up Time
20
ts
4.5
(SL,SR,A-H)
17
6.0
2.0
100
Minimum Set-up Time,
ts
4.5
20
(SO,Sl)
I
6.0
17
2.0
0
Minimum Set-up Time
4.5
ts
0
(CLR)**
6.0
0
2.0
0
Minimum Hold Time
0
th
4.5
(SL,SR,A-H)
0
6.0
0
2.0
Minimum Hold Time
0
4.5
th
(SO,Sl)
0
6.0
0
.2.0
Minimum Hold Time
0
th
4.5
(CLR)**
0
6.0
50
2.0
Minimum Removal Time
trem
10
4.5
(CLR)*
8
6.0
6
2.0
Clock Frequency
f
30
4.5
35
6 0
Ta'" 40 -85"C
U~IT
LIMIT
95
19
16
95
19
16
125
25
21
125
25
21
0
ns
0
0
0
0
0
0
0
0
0
0
0
65
13
10
5
MHz
24
23
Note:* TC74HC299A only
** TC74HC323A only
AC ELECTRICAL CHARACTERISTICS(CL =15pF. Vcc=5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
(QA',QH')
Propagation Delay Time
(CK-QA',QH')
Propagation Delay Time
(CLR-QA' ,QH')
Maximum Clock Frequency I
I
tTLH
tTl II
tpl.H
tollL
tpLH
t )111.
TEST CONDITION
I
f\I!\X
HC-489
MIN.
TYP.
MAX.
-
4
8
-
19
30
-
17
30
35
73
-
U~IT
ns
MHz
TC74HC299AP/AF ________________________________
TC74HC323AP/AF
AC ELECTRICALCHARACTERISTICS(lnput t r =tf=6ns)
TEsT
Ta-25"C
Ta- 40 -85"C U)lIT
SYMBOL
PARAMETElt
CONDITION CL Vee. MIN. I TYP. MAX. MIN. MAX.
75
2.0
25
60
Output Transition Time
tTLH
50 4.5
15
12
7
(QA-QH)
tTHL
13
6.0
6
10
2.0
30
75
95
Output Transition Time
tn.1i
50 4.5
8
15
19
(QA',QH')
t1111.
7
6.0
13
16.
2.0
85
liO
215
Propagation Delay Time
tpLil
50 4.5
23
34
43
(CK-QA'QH')
tpHL
29
6.0
18
37
85
175
220
2.0
Pro~tion Delay Time
24
50 4.5
35
44
tplJL
(CLR-QA' ,QH')**
18
37
6.0
30
2.0
80
160
20
!
50 4.5
21
32
40
Propagation Delay Time
tpLH
6.0
li
27
34
(CK-QA-QH)
2.0
tpHL
250
100
200
150 4.5
ns
26
50
40
6. 0
21
43
34
2.0
240
85
190
50 4.5
24
38
48
Propagation Delay Time
6.0
38
18
30
tJl!iL
(CLR-QA-QH)**
2.0
105
90
230
150 4.5
29
58
46
6.0
22
36
46
2.0
60
130
165
I 17
50 4. 5
26
33
6.0
28
13
22
tll7l..
Output Enable time
RL= 1 kQ
I 2.0
tp7.H
78
215
liO
150 4.5
23
43
34
6.0
29
36
17
2.0
54
150
190
tp[.Z
Output Disable time
RL= 1 kQ
50 4.5
19
30
38
tpj-1Z
6.0
26
16
33
2.0
6
12
5
- MHz
Maximum Clock Frequency
50 4.5
30
58
24
r~1AX
6.0
28
35
80
Input (;apacitance
(;1:"
5
10
10
pF
(;cx.T
Output Capacitance
13
Power Dissipation Capacitance Cpo(1)
170
Note(l) Cm 15 defmed as the value of the internal eqUlvalent capacitance Wh1Ch is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IcctpO=CPD • VOC· f1'\ +ICC
* TC74HC299A only
*. TC74HC323A only
I
-
HC-490
TC74HC352AP I AF
------TC74HC353AP/AF
TC74HC352APlAF DUAL 4-CHANNEL MULTIPLEXER
TC74HC353AP/AF DUAL 4-CHANNEL MULTIPLEXER WITH 3-STATE OUTPUT
The TC74HC352A and TC74HC353A are high speed
CMOS DUAL 4-CHANNEL MULTIPLEXERs fabricated
with silicon gate C2MOS technology.
They achieve the high speed -operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HC352A is an inverted output version of the
TC74HC153A (normal outputs), and the TC74HC353A is
an inverted output version of TC74HC253A (3-state
outputs).
Input data (lCO-le3, 2CO-2C3) are selected by the two
address inputs A and B.
Separate strobe inputs (lG, 2G) are provided for each of
the two four-line sections. They can be used to inhibit the
data outputs: The output of HC352A is set low, and the
HC353A output set is to the high impedance state, when
the strobe input is held low.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tlXl=12ns(Typ.)at, Vee=5V
• Low Power Dissipation ............ Iee =4IlA(Max.)at Ta=25"C
• High Noise Immunity .. · .. · .. ·• .... · V;"IH=VNIL28% Vee (Min.)
• Output Drive Capability· ...... · .... 10 LSTTL Loads
• Symmetrical Output Impedance ... I IOH I =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range'" Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS352,74LS353
1
P(DIP16-P-300A)
l6~
1
F(SOP16-P-300)
PIN ASSIGNMENT
10
18 Vee
B 2
1& 20
1C3 3
14 A
1C2 4
13 2C3
1Ct &
t2 2C2
tCO 8
11 2Ct
tV 7
GND 8
(TOP
VIEW)
IEC LOGIC SYMBOL
TC74HC363A
TC14HC352A
A
B
1a
1G
1CO
tCl
tC2
1C3
lCO
1Cl
tC2
tC3
2G
2G
2CO
2CO
2Cl
2C2
2Cl
2C2
2C3
2C3
HC-491
2'(
to
2CO
9
2V
TC74HC352APIAF
TC74HC353AP/AF--------------SYSTEM DIAGRAM
74HC353A
74HC352A
A 14
B 2
6
1CO 6
1CO
1C1 5
1C1
1C2 4
1C2 4
1C3 3
1C3 3
1~
5
1V
1~
1
2CO 10
1
2CO 10
2C1 11
2C1 11
2Y
2C2 '2
2Y
2C2 12
2C3 13
2C3 '3
2~ 15
2~
15
TRUTH TABLE
SELECT
INPUTS
~TROBE OUTPUTY
DATA INPUTS
B
A
X
X
CO
X
C1
X
C2
X
L
L
L
X
X
X
L
L
X
X
X
L
H
H
L
L
H
H
H
X
X
X
X
X
X
L
X
X
L
H
H
H
H
C3
X
H
X
X
X
L
X
X
H
X
X
X
X
X
L
H
G
H
L
L
L
L
L
L
L
L
HC-492
HC352A HC353A
H
Z
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X : Don't care
Z : High Impedance
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC352AP/AF
TC74HC353APIAF
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Supply Voltage Range
Vcr;
DC Input Voltage
VIN
DC Output Voltage
VOLT
Input Diode Current
11K
Output Diode Current
I()(
DC Output Current
ICl.,T
DC Vee/Ground Current
Icr;
Power Dissipation
Po
Storage Ter.nperature
Tstg
Lead Temperature 10sec
TL
VALUE
-0.5-7
-0.5 -Vcr;+0.5
-0.5 -Vcr;+0.5
±20
±20
±25
±50
500(DlP)*1180(SOIC)
-65 -150
300
UNIT
V.
V
V
rnA
rnA
rnA
rnA
rnW
"C
"C
*500mW in the range of Ta=
-40"C- 85"C. From Ta=65"C
to 85"C a derating factor of
-10mW/'C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vcr;
VIN
Voor
Topr
tr •
tr
UNIT
V
V
V
VALUE
2-6
0- Vcr;
0- Vcr;
-40 - 85
o- 1000(Vct=2.0V)
0- 500 (Vcr; =4.5V)
0- 400(Vcx;=6.0V)
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
3-State Output
Off-State Current
Input Leakage Current
11K
Quiescent Supply Current
Icr;
Iaz *
*
Ta-25"C
TEST CONDITION
Vcr;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
IOH =-201L A 4.5
VI" =
6.0
VIHorVIL
IOH --4 rnA 4.5
IOH =-5. 2rnA 6.0
2.0
IOL =20 ILA 4.5
VI1\=
6.0
VIHorVIL
IOL -4 rnA 4.5
IOL =5.2rnA 6.0
VIN -VIH or V IL
6.0
VOLT =Vcr; or GND
VI:\ -Vcr; or UND
6.0
VIN -Vcr; or GND
6.0
for TC74HC353A only
HC-493
MIN.
1.5
3.15
4.2
·TYP.
MAX.
-
-
-
-
-
1.9
4.4
5.9
4.18
5.68
-
-
-
-
-
-
0.5
1. 35
1.8
-
2.0
4.5
6.0
4.31
5.80
0.0
0.0
0.0
0.17
0.18
0.1
O. I
0.1
0.26
0.26
-
±0.5
-
-
±O.l
4.0
Ta- 40 -85"C
UNIT
MIN. MAX.
1.5
V
3.15
4.2
0.5
V
1. 35
1.8
1.9
4.4
V
5.9
4.13
5.63
0.1
0.1
V
0.1
0.33
0.33
-
-
±5.0
±1.0
40.0
ILA
TC74HC352AP/AF
TC74HC353AP/AF---------------
AC ELECTRICAL CHARACTERISTICS(C L =1&pF,vcc=6V ,Ta=26"C)
PARAMETER
SYMBOL
T~ansition
t1Ui
t TIlL
·tpLH
Output
Time
Propagation Delay Time
(Cn-Y)
Propagation D~ay Time
"(A.B-Y)
PropagaHgn.J)elay Time
(G-Y)
3-State OutP.l!t Disable Time
(O-Y)
*
**
MIN.
TEST CONDITION
tpHL
tpLH
tpHL
tpLH
tliiL
tpLZ
tDHZ
TYP.
MAX.
-
4
8
-
12
19
-
18
29
-
9
16
-
9
16
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =60pF,lnput t r =tf=6ns)
'1'a--40 -85"C UNIT
. Ta-25"C
TYP. MAX .. MIN. MAX.
30
75
95
2.0
t1Ui
Output Transition Time
8
19
4.5
15
t11iL
6.0
7
13
16
145
48
115
2.0
Propagation Delay Time
tpLH
4.5
23
29
15
tpHL
(Cn-Y)
6.0
12
20
25
72
170
215
2.0
Propagation Delay Time
tpLH
4.5
22
34
43
(A.B-Y)
tllliL
6.0
29
37
18
ns
120
36
95
2.0
Propagation Delay Time
~
4.5
24
12
19
(G-Y)
tpHL
6.0
9
20
16
100
125
36
2.0
3-State Output Enable Time tPlL
4.5
20
25
12
(G-Y)
tJ:2H
6.0
9
17
21
145
22
115
2.0
3-State Output Disable Time tpLZ
4.5
23
29
13
tpHZ
(G-Y)
6.0
25
20
11
Input Capacitance
CIN
10
10
5
.,.
pF
TC74HC352A
63
Power Dissipation Capacitance CPDUl
TC74HC353A
62
Note III Cm is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lex; q,.}=C PD • Va:' fIN +1 a:
PARAMETER
SYMBOL TEST CONDITION
Va;
MIN.
-
-
*
**
**
*
**
for TC74HC352A only
for TC74HC363A only
HC-494
-
- - - - - - T C 7 4 HC354API AF
8-CHANNEL MULTIPLEXER WITH INPUT REGISTER
The TC74HC354A is a high speed CMOS 8-CHANNEL
MULTIPLEXER fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
This device contains an 8 channel digital multiplexer
with an8-bit input data register(DO-D7), a 3-bit address
input register(SO-S2)and 3-state outputs.
Data from one of the eight inputs will be shifted onto
the Y output (non-inverted)and the W output (inverted)
pins as determined by the address data.
-1ts ~uts go into a high-impedance state when either
Gl or G2 is held high or G3 is held low.
In the TC74HC354A, the data enable input (DC) controls
transparent latches that pass data to the outputs when DC
is high, and latchs in new data when DC is low.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=24i1s(typ.)at Vcc=5V
• Low Power Dissipation ............... Icc =4 Il A(Max.)at Ta=25"C
• High Noise Immunity··· .. ····•····· VNIH =V:-';IL =28" Vcc(Min.)
• Output Drive Capability············ 15 LSTTL Loads
• Symmetrical Output Impedance ... !IOH! =IOL =6mA(Min.)
• Balanced Propagation Delays ,.• tpLH" tpHL
• Wide Operating Voltage Range ... Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LS354
20
1
P(DIP20-P-300A)
~~
1
F(SOP20-P-300)
PIN ASSIGNMENT
20 Vee
19 y
18 W
17 G3
16 G2
15 G1
14 SO
13 51
12 52
11 SC
07
06
05
04
03
02
01
1
2
3
4
5
6
7
DO 8
DC 9
GNO 10
(TOP VIEW)
IEC LOGIC SYMBOL
01
112
03
s,c
SO
SI
S2
G...!!...
7
i)C
DO
01
02
03
04
05
06
07
~1
HC-495
TC74HC354AP/AF---------------------------------
TRUTH
TABLE
INPUTS
S2
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
OUTPUTS
SELECT'
S1
SO
X
X
X
X
X
X
X
X
X
OUTPUT ENABLES
01
02
03
H
X
X
X
H
X
X
X
L
L
L
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
Ii
H
DC
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
W
Y
Z
Z
Z
Z
Z
Z
DO
DOn
01
01n
02
02n
03
03n
04
D4n
06
D5iI
01
DIn
157
-D7n
DO
DOn
01
D1n
02
02n
03
03n
04
04n
06
06n
01
DIn
07
07n
X:Oon't care
Z:Hlgh Impedance
00n·· .. ··07n:The level of steady-state Inputs at Input 00 through 07,
respectively, before the most recent-L-to-H-translstor of data
control.
#:This columu shows the input address setup with se low.
HC-496
--------------------------------TC74HC354AP/AF
SYSTEM DIAGRAM
G3
---{)
TRUTH TABLE OF INTERNAL LATCH
J'oo..
n
-V
G2
tC>-:
G1
so
D
UD
51
_ST
-D
52
-"
-V
_5T
ST
a
INPUTS
a
a
a
D
~
a
roo
~
r-r-
D
a
~ 5T
"----
-D
04
a
....., ST
-
fJ
5T
r---
D
06
f07
a
L
H
H
H
H
x
L
H
On
On
~~
r---
03
05
a
L
L
p u Is.
fJ
.... 5T
02
5T
'---
5T
01
OUTPUTS
D
X: Don 'I Care
On:Deta s to red 01 Iha Irailing
edge 01 1 h. wast recent ST
a
~
DO
a
a
ST
'---
r--D
a
" - ST
~
"----
HC-497
~
.1
f-W
y
TC74HC354AP/AF---------------------------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
Voor
11K
10K
lour
lee
Po
Tstg
TL
VALUE
-0.5°-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP)'/180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
rnW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vee
o -Vee
-40 - 85
0- 1000(Vcc=2.0V)
0- 500(Vcc=4.5V)
0- 400(Vee =6.0V)
SYMBOL
Vee
VIN
Vour
Topr
t r • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vm
100 =-20JlA
VIN=
VIHorVIL 100 --6 mA
100 =-:[. 8mA
Low-Level
Output Voltage
VOL
VIN=
VIHorV1L
3-State Output
Off-State Current
laz
Input Leakage Current
Quiescent Supply Current
11:,\
lee
IOL =20 JlA
IOL -6 mA
IOL =7.8mA
V IN -V 11-1 or V IL
VWf =Vee or GND
VIN -Vee or UND
VIN -Vee orGND
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
l. 35
1.8
1.8
2.0
1.9
1.9
4.5
4.4
4.4
V
6.0
5.9
5.9
4.18
4.31
4.13
5.68
5.80
5.63
0.1
0.1
0.0
0.1
0.0
0.1
V
0.1
0.1
0.0
0.33
0.26
0.17
0.33
0.26
0.18
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
MiN.
1.5
3.15
4.2
6.0
-
-
±0.5
-
±5.0
6.0
6.0
-
-
±0.1
4.0
-
±1.0
40.0
He-4g8
-
JlA
- - - - - - - - - - - - - - - - TC74HC354AP/AF
AC ELECTRICAL CHARACTERISTICS(lnputt r =tf =6nll)
PARAMETER
TEST
SYMBOL CONDITION
Minimum Pulse Width
(DC)
tw 0.)
Minimum Pulse Width
(SC)
tw (L)
Minimum Set-up Time
(Dn)
ts
Minimum Set-up Time
(Sn)
Minimum
Hold
(Dn)
Time
Minimum
Hold
(Sn)
Time
ts
th
th
~
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
HC-499
Ta 25"C
LIMIT
TYP.
-
-
-
-
75
15
13
75
15
13
50
10
9
50
10
9
5
5
5
5
5
5
Ta
40-85"C
LIMIT
UNIT
95
19
16
95
19
16
65
13
11
65
13
11
5
5
5
5
5
5
ns
TC74HC~54AP/AF--........- - _ -_ _- - - - - - -
AC
ELECTRICAL
CHARACTERISTICS
PARAMETER
Output Transition Time
Propagation Delay Time
(Dn-Y,W)
(I nput t r =t I =6ns)
TEST
SYMBOL CONDITION
CL
t1l.H
tTI-O..
50
50
tpLH
tpHL
150
Propagation Delay Time
(DC-Y,W)
50
tpLH
tpHL
150
Propagation Delay Time
(Sn-Y,W)
50
tpLH
tpHL
150
Propagation' Delay Time
-
(SC-Y.W)
50
tpLH
tpHL
150
50
Output Enable time
tPlL
ti01
RL =lkQ
150
Output Disable time
tlll.'z
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
C IN
Carr
CPD(1
tpHZ
RL =lkQ
50
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2,0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
MIN.
---~
-
-
-
-
-
--
Ta 25"C
TYP. MAX.
25
7
6
83
26
21
99
31
25
83
26
21
99
31
25
98
30
25
114
35
29
102
31
27
118
36
31
44
14
12
60
19
16
42
20
17
5
10
77
60
12
11
210
42
36
250
50
43
210
42
36
250
50
43
260
52
44
300
60
51
270
54
46
310
62
53
125
25
21
165
33
28
155
31
26
10
-
-
Ta 40-85"C
UNIT
MIN. MAX.
-
-
-
.-
--
--
--
75
15
13
265
53
45
315
63
54
265
53
45
315
63
54
325
65
55
375
75
64
340
68
58
390
78
66
155
31
26
205
41
35
195
39
33
10
-
Note(l) :Cpois defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia;QJd=C PO .Va; .CIN+la;
He-soD
ns
pF
------TC74HC356AP/AF
8-CHANNEL MULTIPLEXER WITH INPUT REGISTER
The TC74HC356A is a high speed CMOS 8-CHANNEL
MULTIPLEXER fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
This device contains an 8 channel digital multiplexer
with an 8-bit input data register(DO-D7), a 3-bit address
input register(SO-S2)and 3-state outputs.
Data from one of the eight inputs will be shifted onto
the Y output (non-inverted)and the W output (inverted)
pins as determined by the address data.
.-1ts outputs go into a high-impedance state when either
Gl or G2 is held high or G3 is held low.
In the TC74HC356A, the data is stored into the 8-bit flip
-flop at the positive going transition of the clock input
(CLOCK).
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=25ns(typ.}at Va;=5V
• Low Power Dissipation ............... Ia;=4ttA(Max.}at Ta=25"C
• High Noise Immunity··············· VNIH =V:-';IL =28" Va;(Min.)
• Output Drive Capability············ 15 LSTTL Loads
• Symmetrical Output Impedance ···1 IOH I =IOL =6mA(Min.)
• Balanced Propagation Delays .. , tpLH >; tpHL
• Wide Operating Voltage Range ... Va;(opr)=2V-6V
• Pin and Function Compatible with 74LS356
20
1
P(DIP20-P-300A)
w~
1
F(SOP20-P-300)
PIN ASSIGNMENT
20 Vee
19 y
18 W
17 G3
16. G2
15 G1
14 SO
13 S1
12 S2
11 SC
07
06
05
04
03
02
01
2
3
4
5
6
7
DO 8
CLOCK 9
GNO 10
(TOP VIEW)
IEC LOGIC SYMBOL
<31
"G2
G3
8C
80
81
82
CK
G£.
7
DO
01
02
03
04
05
06
07
.. 1
J>
90
90
90
90
90
90
2
3
4
6
6
7
HC-501
V
V
(19) Y
(18)W
TC74HC35.6AP/AF - - -.......- - - - - - - - - - - -
TRUTH TABLE
INPUTS
S2
SELECT'
S1
SO
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
OUTPUTS
OUTPUT ENABLES
G1
G2
G3
W
Y
X
X
X
H
X
X
X
H
X
X
X
L
Z
Z
Z
Z
Z
Z
-.r
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
DO
DOn
DO
DOn
01
01n
02
02n
03
03n
CLOCK
~
S
t-
-.r
t-.r
t-.r
t-
....r
t-
-.r
t..-
S
~
L
L
L
L
L
L
L
L
L
L
L
Di
01n
02
02n
03
03n
04
D4n"
06
.06n
06
06n
07
07n
D4
04n
06
06n
06
06n
07
07n
X:Oon't care
Z:High Impedance
00n······07:The level of steady-state inputs at inputs DO through 07,
respectively, before the most recentML MtoMHMtransition of
data control.
#:This column shows the input address setup with SC low.
HC-502
----------------TC74HC356AP/AF
SYSTEM DIAGRAM
G3
--"1,;"-""""
TRUTH TABLE OF INTERNAL LATCH
G1 --------'
----------t
INPUTS
0
L
H
X
SI
FLOP)
fi
G2 ------~D-~LJ~~>-----_.
SO
ST
H
H
L
II
OUTPUTS
a
L
H
an
a
H
L
an
X:Don't cere
On:DATA STORED AT THE TRAILING
EDGE OF THE MOST RECENT ST
PULSE,
S2
TRUTH TABLE OF
INTERNAL LATCH (FLIP-
x
0
CK
L
H
X
S
a
L
H
an
L
:Oon't care
an :No change
SC --~,r--
CK
DO
--------+-i
01
.,
I
W
02
03
y
04
05
06
01
HC-503
TC74HC356AP/AF------------------------------ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Voc/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Voc
VIN
VCliT
11K
I(l{
ICliT
Ioc
Po
Tstg
TL
VALUE
-0.5-7
-0.5 -Voc+0.5
-0.5 -Voc+0.5
±20
±20
±35
±75
500(DIP)*1180(SOIC)
-65 -150
300
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"G. From Ta=65"C
85"C a derating factor of
-IOmW/"C shall be applied
until 300mW.
to
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Input Rise and Fan Time
tr • tr
VALUE
2-6
O-Voc
O-Voc
-40"" 85
o"'" 1000(Voc =2.0V)
0- 500(Voc =4.5V)
0"" 400(Voc =6.0V)
Voc
VI~
VCliT
Topr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Low-Level
Output Voltage
V(}I
VOL
3 State Output
orf-State Current
Iaz
Input'Lsakage Current
Quiescent Supply Current
II:>;
lee
Ta-25'C
TEST CONDITION
VIN=
VIHorVIL
VIN=
VIHorVIL
I(}I =-20 tl A
I(}I - 6 mA
I(}I =-7.8mA
IOL =20 tlA
IOL -6 mA
IOL =7.8mA
VI" -VIH or VII:'
VOLT =Voc or GND
VI" -Voc or uND
VI" -Vee or GND
Voc
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
MiN.
1.5
3.15
4.2
TYP.
MAX.
-
-
-
-
0.5
1. 35
1.8
-
-
-
2.0
4.5
6.0
4.31
5.80
0.0
0.0
0.0
0.17
0.18
0.1
0.1
0.1
0.26
0.26
6.0
-
-
±0.5
-
±5.0
6.0
6.0
-
-
±0.1
4.0
-
±1.0
40.0
HC-504
1.9
4.4
5.9
4.18
5.68
-
-,
Ta- 40 -85"C UNIT
MiN. MAX.
1.5
V
3.15
4.2
0.5
V
1. 35
1.8
1.9
4.4
V
5.9
4.13
5.63
0.1
0.1
V
0.1
0.33
0.33
-
-
-
-
tl A
--------------------------------TC74HC356AP/AF
AC ELECTRICAL CHARACTERISTICS(lnputt r =t
PARAMETER
~YMBOL TEST
CONDITION
Minimum Pulse Width
(CLOCK)
tw (H)
tw (L)
Minimum Pulse Width
(SC)
tw (I.)
Minimum Set-up Time
(Dn)
t5
Minimum Set-up Time
(Sn)
t5
Minimum
Hold
(Dn)
Time
Minimum
Hold
(Sn)
Time
Clock Frequency
th
th
f
-
f
=6ns)
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
He-50S
Ta 25"C
TYP.
LIMIT
75
15
13
75
15
13
50
10
9
50
10
9
5
5
5
5
5
5
6
31
36
-
Ta
40-85"C
UNIT
LIMIT
95
19
16
95
19
16
65
13
11
ns
65
13
11
5
5
5
5
5
5
5
24
MHz
28
TC74HC356AP/AF--------------------------------
AC
ELECTRICAL CHARCTERISTICS (Input tr =tf =8n.)
Ta 25"C
TEST
PARAMETER
SYMBOL CONDITION
CL Va;
MIN. TYP. MAX.
Output Transition Time
Propagation Delay Time
(CLOCK-Y.W)
Propagation Delay Time
(Sn-Y.W)
tTLH
tTHL
50
50
tpLH
tpHL
150
50
tpLH
t pHL
150
Propagation Delay Time
-
(SC-Y.W)
50
tpLH
tpHL
150
50
Output Enable time
tid
t!0t
RL =lkQ
150
Output Disable time
tpl2
tpHZ
Maximum Clock Frequency
(MAX
input Capacitance
Output Capacitance
Power Dissipation Capacitance
CIX
Ca.,
CPD(l)
RL =lkQ
50
50
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6;0
2.0
4.5
6.0
2.0
4.5
6.0
--
--
-
-6
31
36
-
25
7
6
99
28
22
117
33
26
III
32
24
128
37
28
115
33
25
132
38
29
48
14
11
65
19
15
43
18
16
20
80
32
5
10
59
Ta 40-85"C
UNIT
MIN. MAX.
60
12
-
240
48
41
280
--
11
56
48
260
52
44
300
60
51
270
54
46
310
62
53
125
25
21
165
33
28
155
31
26
10
-
-
-
-
75
15
13
300
60
51
350
70
60
325
65
55
375
75
64
340
68
58
390
78
66
155
31
26
205
41
35
195
39
33
5
24
28
-
-
-
-
10
Note(l) :C;>ois defined as the value of the intel'nal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
[a;tpD=C pD • Va; • £IN+[ CC
He-506
ns
pF
------------------------------HEX BUS BUFFER
TC74HC365API AF
TC74HC366API AF
TC74HC365API AF
TC74HC366API AF
NON-INVERTED
INVERTED
The TC74HC365A and TC74HC366A are high speed
CMOS 3-ST ATE BUFFERs fabricated with silicon gate
C2MOS technology.
They achieve th~ high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HC365A is an inverting type. while the
TC74HC366A is non-inverting.
All six buffers are controlled by the combination of two·
enable inputs (ch and (2); the outputs of these buffers
are enabled only when both Gl and G2 inputs held low.
and at the other combinations. these outputs are disabled
to the high impedance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd =9ns( typo )at VCC'=5V
• Low Power Dissipation ............ Icc =4#A(Max.)at Ta=25"C
• High )J"oise Immunity··············· V:,IH =V:'-:IL28% Vcc (Min.)
• Output Drive Capability'" ......... 15 LSTTL Loads
• Symmetrical Output Impedance "'1 la-II =I oL =6mA(Min.)
• Balanced Propagation Delays ...... tpLH '" tpHL
• Wide Operating Voltage Range ... Vee (opr.)=2V-6V
• Open Drain Structure
• Pin and Function Compatible with 74LS365/366
1
P(DIP16-P-300A)
16~
F (SOP 16~P-300)
PIN ASSIGNMENT
TC74HC365A
Gl 1
16 Vee
lA 2
15 <32
lY 3
14 6A
2A 4
13 6Y
2Y 5
12 5A
3A 6
11 5Y
3Y 7
10 4A
GND 8
TRUTH TABLE
9
4Y
(TOP VIEW)
TC74HC366A
INPUTS
G1
G2
OUTPUTS
An
L
L
H
L
L
L
H
X
X
H
X
X
X : Don't care,
Yn(365A) Yn(366A)
L
H
Z
Z
H
L
Z
Z
Z: High Impedance
Gl
16 Vee
lA 2
15
14 6A
2A 4
13
2'15
12 5A
3A 6
11
3'1 7
10 4A
GND 8
9
(TOP VIEW)
He-50?
G2
lY 3
6Y
5Y
4Y
TC74HC365AP/AF _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC366API AF
IEC LOGIC SYMBOL
TC74HC365A
TC74HC366A
01
02
Al
A2
A3
A4
AS
A6
Al
A2
A3
A4
AS
A6
VI
V2
V3
V4
V5
V6
He-50S
VI
Y2
Y3
Y4
YS
Y6
_______________________________ TC74HC365AP/AF
TC74HC366APIAF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
Vee
VIN
Voor
11K
10K
1000r
lee
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP) */180(SOIC)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VIN
Vour
Topr
tr • tr
UNIT
V
V
V
"C
VALUE
2-6
o -Vee
o -Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
0- 400(Vee =6.0V)
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
VOL
3 State Output
Off-State Current
Iaz:
Input Leakage Current
Quiescent Supply Current
In_
lee
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
Iai =-20J.tA 4.5
VIN=
6.0
VIHorVIL
100 --6 rnA 4.5
100 =-7. 8mA 6.0
2.0
IOL =20 J.tA 4.5
VIN=
6.0
VlliorVIL
IOL -6 rnA 4.5
IOL =7.8mA 6.0
V IN -V IH or V II.
6.0
VOL'T =Vee or GND
VI:\: -Vee or GND
6.0
VI" -Vee or GND
6.0
HC-509
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
O. 5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.0
0.1
0.1
0.1
0.0
O. I
V
O. I
0.0
O. I
0.33
0.17
0.26
0.18
0.26
0.33
MIN.
1.5
3.15
4.2
-
-
±0.5
±O.l
4.0
-
±5.0
±1.0
40.0
J.tA
TC74HC365AP/AF ________________________________
TC74HC366API AF
AC ELECTRICAL CHARACTERISTICS(lnput t r =t f =6ns)
TEST
CONDITION
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTHL
50
tpLH
50
tpHL
150
tpZL
50
CL
Propagation Delay Time
Output Enable time
RL = 1 kQ
150
tpZH
Output Disable time
tpLZ
tpHZ
R L = 1 kQ
50
Ta-25°C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
20
60
75
12
6
15
5
10
13
38
90
115
12
18
23
20
10
15
51
130
165
17
26
33
-14
22
28
ns
56
130
165
17
26
33
13
22
28
69
170
215
22
34
44
17
29
37
42
130
165
18
26
33
15
22
28
-5
10
10
-pF
10
25
equivalent capacitance which is calculated from the
Vcc
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
MIN.
Input Capacitance
CIN
Output Capacitance
Cour
Power Dissipation Capacitance Cffi(l)
Note (1) CPD is defined as the value of the internal
operating current consumption without load.
Average operating current can be obtained by the equation:
I ccq,o=C PD • Va:,' fIN +Ia:, 16(per Date)
HC-510
TC7 4HC367 AP IAF IAF N
----TC74HC368AP/AF/AFN
HEX BUS BUFFER
TC74HC367AP/AF/AFN
TC74HC368API AFI AFN
NON-INVERTED
INVERTED
The TC74HC367A and TC74HC368A are high speed
CMOS 3-STATE BUS BUFFERs fabricated with silicon
gate C2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
They contain six buffers; four buffers are controlled by enable
input cal), and the other two buffers are controlled by enable input
c(2), The inputs of each buffer group are enabled when al and/or a2
inputs are held low; if held high, these outputs are in a high impedance
state.
The TC74HC367A is a non-inverting output type, while
the TC74HC368A is an inverting output type.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP16-P-300A)
,,~,,~
F(SOP16-P-300)
PIN
FEATURES:
• High Speed .............................. tpd =llns(Typ.)at Vee=5V
• Low Power Dissipation ............ Iee =4IlA(Max.)at Ta=25"C
• High Noise Immunity .. · ............ VNlH=VNIL28% Vee (Min.)
• Output Drive Capability· .......... · 15 LSTTL Loads
• Symmetrical Output Impedance ... I IOH I =IOL =6mA
• Balanced Propagation Delays ...... tpLH"';tpHL
• Wide Operating Voltage Range'" Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS367/368
F N(SOL 16-P-150)
ASSIGNMENT
TC74HC367A
G1
16 Vee
1A 2
15 G2
1Y 3
14 6A
2A 4
13 6Y
2Y 5
12 5A
3A
6
11 5Y
3Y
7
10 4A
GND 8
9 4Y
(TOP VIEW)
TRUTH
TABLE
TC74HC368A
OUTPUTS
INPUTS
G1
16 Vee
1A 2
15 G2
G
An
Y(367A)
Y(368A)
1Y 3
14 6A
L
L
L
H
2A 4
13 6Y
L
H
H
L
2Y 5
12 5A
H
X
Z
Z
3A
6
11 5Y
3Y 7
10 4A
GND 8
9 4'1
X:DON'T
CARE
Z:HIGH
IMPEDANCE
(TOP VIEW)
HC-S11
TC74HC367 API AFI AFN
TC74HC368AP/AF/AFN--------------
IEC LOGIC SYMBOL
TC74HC367A
TC74HC368A
HEX BUS BUFFER
(3-STATE/INV.)
HEX BUS BUFFER
(3-:STATE)
ell
lA
2A
3A
4A
6A
HC-512
4
I---"';.......;~Iol
lY
2Y
3Y
4Y
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC367AP/AF/AFN
TC74HC368API AFI AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI>':
VOLT
11K
10K
IOlT
lee
PD
Tstg
Tl
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP)'/180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor .of
-lOmW/"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee=6.0V)
SYMBOL
Vee
VIN
VWf
Topr
tr •
tc
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
Vll
TEST CONDITION
1m =-20J].A
High-Level
Output Voltage
Vm
Low-Level
Output Voltage
VOL
3-State Output
Off-State Current
ICE
Input Leakage Current.
Quiescent Supply Current
lIN
lee
Vh\l =
VIHorVIL
1m --6 rnA
1m =-7.8mA
VI!" =
VIHorVIL
IOL =20 J].A
IOL -6 rnA
IOL =7.8mA
VI:\ =VIH or VIL
VOLT=Vee orGND
VI:\ -Vee orGND
VI:\ -Vee orGND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
HC-513
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
1.9
2.0
4.5
4.4
4.4
V
5.9
5.9
6.0
4.13
4.18
4.31
5.68
5.80
5.63
0,1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.1
0.0
0.26
0.33
0.17
0.26
0.33
0.18
±0.5
±5.0
MIN.
1.5
3.15
4.2
-
-
-
±0.1
4.0
-
-
±1.0
40.0
J].A
TC74HC367AP/AF/AFN _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC368API AFI AFN
AC ELECTRICAL
PARAMETER
Output Transition
Time
Propagation Delay
Time
Output Enable
Time
Output Disable
Time
CHARACTERISTICS
(Input tr =tf =6n8)
SYMBOL TEST CONDITION
tn.1l
tl1iL
Vcc
2.0
50 4.5
6.0
CL
50
2.0
4.5
6.0
150
2.0
4.5
6.0
50
2.0
4.5
6.0
150
2.0
4.5
6.0
50
2.0
4.5
6.0
tpLH
tpllL
t Pll•
tp7.H
tplZ
tpHZ
RL =lk Q
RL =lk Q
MIN.
-
Ta=-40-85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
25
60
75
7
12
15
6
10
13
36
95
120
12
19
24
20
10
16
40
16
14
36
12
10
-
-
-
165
33
28
120
24
20
-
150
30
26
40
160
32
16
27
14
35
120
24
15
13
20
5
10
10
36
30
capacitance which
Input Capacitance
CI:-<
C()I;T
Output Capacitance
TC74HC367A
Power Dissipation
CpDm
Capacitance
TC74HC368A
Note(l) Cpo IS defmed as the value of the mternal eqUivalent
the operating current consumption without load.
Average operating current can be obtained by the equation:
ICC WI' =c PO • V CC • £1:\+ ICC /6( per bit)
HC-514
130
26
22
-
IS
I
ns
200
40
34
150
30
26
10
-
pF
calculated from
TC7 4HC373AP I AF I AFW
------------------ TC74HC533AP/AF
OCTAL D-TVPE LATCH WITH 3-STATE OUTPUT
TC74HC373AP/ AF
NON-INVERTING
TC74HC533AP/ AF
INVERTING
The TC74HC373A and TC74HC533A are high speed
CMOS OCT AL LATCH with 3-ST A TE OUTPUT
fabricated with silicon gate C2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissi pation.
These 8-bit D-type latches are controlled by a latch
enable input (LE) and a output enable input (OE).
When the OE input is high, the eight outputs are in a
high impedance state.
The TC74HC373A has non-inverting outputs, and
TC74HC533A has inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. tpd=l1ns(typ.)at Vcc=5V
P(0IP20-P-300A)
20~ 20~
1
F(SOP20-P-300)
1
FW(SOL20-P-300)
PIN ASSIGNMENT
TC74HC373A
• Low Power Dissipation ............... I cc =4IlA(Max.)at Ta=25°C
• High Noise Immunity .. · .. ······· .. · VNIH=VNIL =28% Vcc(Min.)
• Output Drive Capability .... ·.. · .... 15 LSTTL Loads
00 2
20 Vcc
19 07
• Symmetrical Output Impedance .. ·1 IOI-d=IOL =6mA(Min.)
DO 3
18
07
01
4
17
06
01
5
16
06
02 6
15
05
02 7
14
05
03 8
13
04
03 9
12
04
GNO 10
11
LE
• Balanced Propagation Delays ...... tpLH""t pHL
• Wide Operating Voltage Range .~. Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LS373/533
OE 1
TRUTH TABLE
TC74HC533A
INPUTS
20 Vec
OE
OUTPUTS
O(HC373A) O(HC533A)
00 2
DO 3
19 Gi7
18
07
01
4
17
06
01
S
16 06
15 aS
OE
LE
0
H
X
X
Z
Z
L
L
X
Qn
Qn
L
H
L
L
H
02 6
L
H
H
H
L
02 7
14
05
03 8
13
04
03 9
12 04
GNO 10
11
x : Don't Care
Z ;jjlgh ImpJ!.dance
an (an) : a (a) outputs are latched at the time
when the LE input is taken to a low
logic level.
HC-515
LE
TC74HC373AP/AF/AFW _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC533API AF
IEC LOGIC SYMBOL
TC74HC533A
TC74HC373A
OE
OE
LE
LE
DO
00
01
02
03
04
05
OS
07
00
01
02
03
04
OS
D6
07
00
01
02
03
04
05
01
02
03
04
05
06
07
Os
07
SYSTEM DIAGRAM
TC74HC373A
DO
01
02
03
D4
05
D6
01
02
03
04
05
06
07
TC74HC533A
00
HC-516
07
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC373AP/AF/AFW
TC74HC533AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI!':
VOl:T
11K
10K
Ioor
lee
PD
TSlg
TL
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP)*/180(MFP)
-65 -150
300
UNIT
V·
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vee
0-- Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
0- 400(Vee =6.0V)
SYMBOL
Vee
VIN
VoUr
Topr
tr ,
tc
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
P AR.(\METER
SYMBOL
TEST CONDITION
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Va-r
la-r =-20/.1. A
VI!" =
VIHorV1L . la-r --6 mA
la-r =-7.8mA
Low-Level
Output Voltage
VOL
VI:>; =
VIHorVIL
3-State Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
l(]l
111'\
lee
IOL =20 /.I. A
IOL -6 rnA
IOL =7.8mA
Vir', -VIH or VIL
VOL". =Vee or GND
VIii: -Vee orGND
VI:>; -Vee or UND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
-
He-51?
Ta= 40 -85"(
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.5
4.4
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.1
0.0
0.26
0.33
0.17
0.33
0.26
0.18
±0.5
±5.0
/.I. A
±0.1
±1.0
40.0
4.0
MIN.
1.5
3.15
4.2
-
-
TC74HC373AP/AF/AFW _ _ _ _ _ _ _ _ _ _ _ _ __
TC74 HC533APIAF
TIMING REQUIREMENTS(lnput t r=tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(LE)
tWOiJ
Minimum Set-up Time
(Data)
ts
Minimum Hold Time
(Data)
th
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C
TYP.
LIMIT
75
15
13
50
10
9
5
5
5
Ta--40 -85"C
UNIT
LIMIT
95
19
16
65
ns
13
11
5
5
5
AC ELECTRICAL CHARACTERISTICS(lnput t r =tf=6ns)
TEST
Ta-25"C
Ta- 40 -85"C
PARAMETER
SYMBOL
UNIT
CONDITION CL Vee MIN. TYP. MAX. MIN. MAX.
2.0
20
60
75
tlLH
Output Transition Time
50 4.5
12
15
6
t1lJL
6.0
10
13
5
2.0
42
125
155
4.5
50
14
25
31
tpLH
Propagation Delay Time
6.0
12
21
26
220
2.0
57
175
(LE-Q,Q)
150 4.5
19
35
44
tpHL
16
37
6.0
30
2.0
42
125
155
4.5
50
14
25
31
tpLH
Propagation Delay Time
6.0
12
21
26
ns
2.0
57
175
220
(D-Q,Q)
150 4.5
19
35
44
tpHL
6.0
16
30
37
39
125
2.0
155
50 4.5
13
25
31
tpZL
21
6.0
11
26
Output Enable time
RL = 1 kQ
2.0
54
175
220
tpZH
150 4.5
18
35
44
15
30
6.0
37
2.0
30
125
155
tpLZ
Output Disable time
R L= 1 kQ
50 4.5
14
25
31
tpHZ
6.0
13
21
26
Input Capacitance
Cn..:
10
5
10
Output Capacitance
pF
10
Celli"
Power Dissipation Capacitance CPD(l)
38
Note(1) CR) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
leetp,FCR) • Va;. fN +Ia; 18(per Latch)
And the total CR) when n pes. of Latch operate can be gained by the following equation:
Cm(totai)=22+16. n
HC-518
TC74HCT373AP tAFt AFW
----TC74HCT533AP t AF
OCTALD-TYPE LATCH WITH 3-STATE OUTPUT
NON-INVERTING
TC74HCT373API AFI AFW
TC74HCT533AP/AF
INVERTING
The TC74HCT373A and HCT533A are high speed CMOS
OCT AL LATCH with 3-STATE OUTPUT fabricated with
silicon gate C 2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissi pation.
Their inputs are compatible with TTL, NMOS, and
CMOS output voltage levels.
These 8-bit D-type latches are controlled by a latch
enable input (LE) and an output enable input (OE).
When the OE input is high, the eight outputs are in a
high impedance state.
The TC74HCT373A has non-inverting outputs, and
TC74HCT533A has inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd =17ns(Typ.)at Vee =5V
• Low Power Dissipation ............ Iee =4ttA(Max.)at Ta=25"C
• Compatible with TTL outputs ... V IH =2V (Min.)
V 1L =O.8V (Max.)
• Wide interfacing ability············ LSTTL, NMOS, CMOS
• Output Drive Capability··· ......... 15 LSTTL Loads
• Symmetrical Output Impedance ···1 100 1=Ia. =6mA(Min.)
• Balanced Propagation Delays······ tpLH .. tpHL
• Pin and Function Compatible with 74LS373/533
P(DIP20-P-300A)
2~ 20~
1
1
F(SOP20-P-300) FWCSOL20-P-300)
PIN ASSIGNMENT
TC74HCT373A
OE
QO
DO
01
Ql
Q2
02
03
Q3
20 Vcc
2
3
4
19
18
17
16
15
14
13
12
11
5
6
7
8
9
GNO 10
TRUTH TABLE
Q7
07
06
Q6
Q5
05
04
Q4
LE
TC74HCT533A
INPUTS
OUTPUTS
OE
LE
0
H
X
X
X
L
L
L
H
L
H
Q(T373A) Q(T533A)
Z
Z
Qn
Qn
L
L
H
H
H
L
x : Don't Care
Z
;J:!lgh
Im~dance
Qn (Qn) : Q CQ} outputs are latched at the time
when the LE Input is taken to a low
logic level.
HC-519
OE
'00
DO
01
01
02
02
03
03
1
2
3
4
5
6
7
8
9
GNO 10
20
19
18
17
16
15
14
13
12
Vec
07
07
06
06
05
D5
04
04
11 LE
TC74HCT373AP/AF/AFW _ _ _ _ _ _ _ _ _ _ _ __
TC74HCT533AP I AF
IEC LOGIC SYMBOL
TC74HCT533A
TC74HCT373A
OE
OE
LE
LE
00
QO
00
Co
01
D2
03
D4
Ql
Q2
01
02
Q3
D3
Q4
D4
Ql
Q2
Q3
Q4
OS
D6
as
Q6
OS
D6
07
Q7
07
as
Ci6
Q7
SYSTEM DIAGRAM
TC74HCT373A
00
01
QO
D2
QI
03
Q2
D4
Q3
05
Q4
as
Q6
TC74HCT533A
00
01
02
03
HC-520
D4
05
D6
07
Q7
TC74HCT373APIAFIAFW
TC74HCT533APIAF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vex;/Ground Curr.ent
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vex;
VI"
VOL".
11K
101(
leur
lex;
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vex; +0.5
-0.5 -Vex;+0.5
±20
±20
±35
±75
500(DIP)*/180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
- iOm WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vex;
VIN
VOliT
Topr
tr. tr
VALUE
4.5 - 5.5
0- Vex;
0- Vex;
-40 - 85
0-500
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Low-Level
Output Voltage
3-State Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
Va-!
_.
VOL
ICE
lIN
lex;
L::.lcc
TEST CONDITION
Vex;
4.5
l
5.5
4.5
l
5.5
VIN =
Ia-! --20 f.l.A 4.5
VlHorVIL IOH --6 rnA 4.5
VIN lex. -20 f.l.A 4.5
VUiorVIL lex. -6 rnA 4.5
VIN-Vlli or VIL
5.5
VOLT = Vex; or GND
VI~-'-VCC orGND
5.5
Vr', - Vex; or GND
5.5
PER INPUT: VI~ =0. 5V or2. 4V
5.5
OTHER INPtiT:VI:\or GND
HC-521
MIN.
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
4.4
4.18
-
-
-
4.5
4.31
0.0
0.17
-
4.4
4.13
-
0.1
0.26
-
-
-
V
0.1
0.33
V
-
±0.5
±5.0
f.l.A
-
-
-
±O.l
4.0
-
±1.0
40.0
f.l.A
-
2.0
-
2.9
rnA
TC74HCT373AP/AF/AFW _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HCT533API AF
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
Minimum Pulse Width
(LE)
Minimum Set-up Time
(Data)
Minimum Hold Time
(Data)
SYMBOL TEST CONDITION
tW(H)
ts
Va;
4.5
5.5
4.5
5.5
Ta-25"C
TYP.
LIMIT
-
4.5
5.5
tb
15
14
10
9
Ta--40 -85"C
UNIT
LIMIT
19
17
13
12
5
5
5
5
-
ns
AC ELECTRICAL CHARACTERISTICS(lnput t r =t,=6ns)
TtJl:lT
Ta- 40 -85"C UNIT
Ta-25"C
PARAMETER
SYMBOL
CONDITION {;L Va; MIN. TYP. MAX. MIN. MAX.
7
t1LH
12
15
Output Transition Time
50 4.5
6
t1lU..
14
5.5
11
Propagation Delay Time
(LE-Q, "Q)
tpLH
tJlHL
Propagation De'!!y Time
(D-Q,Q)
tPLH
tJilL
Output Enable time
tpZL
t!0i
50
150
50
150
50
RL = 1 kQ
150
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
-
-
-
-
19
16
30
27
24
22
38
34
20
18
30
27
25
22
38
34
19
16
24
22
30
27
38
34
-
-
-
38
34
48
43
38
34
48
43
ns
38
34
48
43
38
34
10
20
30
18
27
Input Capacitance
5
10
Output Capacitance
CClJI
10
pF
CPD(l) TC74HCT373A
Power Dissipation Capacitance
36
Power Dissipation Capacitance
C (l) TC74HCT533A
35
Note(1) Cpo is defined as tJij value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia;q,o=CPO • VCC· fIN +ICC /8(per Latch)
And the total Cpo when n pes. of Flip Flop operate can be gained by the following equation:
CPO(total) =19+ 17 • n (TC74HCT373A)
Cpo (total) ",21 +14. n (TC74HCT533A)
Output Disable time
tplZ
tpHZ
CI:-l
RL = 1 kQ
50
4.5
5.5
HC-522
-
_ _ _ _ TC74HC374AP/AF/AFW
TC7 4HC534API AF
OCTAL D-,:TYPE FLIP-FLOP WITH 3-STATE OUTPUT
TC74HC374API AFI AFW NON-INVERTING
TC74HC534API AF
INVERTING
The TC74HC374A and TC74HC534A are high speed
CMOS OCTAL FLIP-FLOP with 3-ST ATE OUTPUT
fabricated with silicon gate C~OS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
These 8-bit D-type flip-flops are controlled by a clock
input (CK) and a output enable input (OE).
When the OE input is high, the eight outputs are in a
high impedance state.
The TC74HC374A has non-inverting outputs, and TC74
HC534A has inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
P(DIP20-P-300A)
20~ 20~
1
1
F(SOP20-P-300)
FW(SOL20-P-300)
PIN ASSIGNMENT
• High Speed ................................. f MAX =77}.1Hz(typ.)at Vcc=5V
• Low Power Dissipation ............... Icc =;4ttA(Max.)at Ta=25"C
• High Noise Immunity·················· VN1H =V:\IL =28% Vcc(Min.)
• Output Drive Capability··············· 15 LSTTL Loads
• Symmetrical Output Impedance ···1 Ioo 1=IOL =6mA(Min.)
• Balanced Propagation Delays ...... tpLH"" tpHL
• Wide Operating Voltage Range ... Vcc (\?pr) =2V-6V
• Pin and Function Compatible with 74LS374/534
TRUTH TABLE
TC74HC374A
OE 1
00 2
20 Vee
19 07
DO 3
18
07
01
4
17
06
01
5
16
06
02 6
15
05
02 7
14
05
03 8
13
04
03 9
12
04
GN010
11
CK
TC74HC634A
OE 1
INPUTS
OE
H
CK
X
00 2
DO 3
OUTPUTS
0
X
Q(HC374A tci(HC534A
Z
Z
L
L
X
an
an
L
S
L
L
H
L
.J
H
H
L
x : Don't
Care
Z .;JIigh Impedance
On(On) : No Cange
18
07
01
4
17
06
01
5
16 06
02 6
15
as
02 7
14
05
03 8
13
04
03 9
12 04
11 CK
GNO 10
HC-523
20 Vee
19 07
TC74HC374AP/AF/AFW _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC534APIAF
IEC LOGIC SYMBOL
TC74HC534A
TC74HC374A
DE
CK
DE
00
01
02
03
D4
05 1
06 1
07
ao
DO
01
02
03
04
01
02
03
D4
05
06
07
as
06
07
00
01
02
03
04
05
Os
07
SYSTEM DIAGRAM
TC74HC374A
00
01
ao
02
01
03
02
D4
03
05
Q4
06
as
07
Q6
TC74HC534A
00
01
02
03
HC-524
D4
05
06
07
07
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC374AP/AF/AFW
TC74HC534API AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
. Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI:"
VOLT
11K
10K
lOUT
lee
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP) *1180(MFP)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
unti1300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Input Rise and Fall Time
tr • tf
UNIT
V
V
V
"C
VALUE
2-6
o-Vee
0- Vee
-40 - 85
o - 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o- 400(Vee=6.0V)
Vee
VI:"
VOLT
Topr
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
VOL
3 State Output
Off-State Current
Irn
Input Leakage Current
Quiescent Supply Current
Iel/
lee
TEST CONDITION
VI:" =
VIHorVIL
VI:" =
VIHorVIL
100 =-20tt A
100 - 6 rnA
100 =-7.8mA
IOL =20 tt A
IOL -6 rnA
IOL =7.8mA
VI:" -VIH or V IL
VOLT =Vee or GND
VI:" -Vee or GND
VJ:" -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
HC-525
Ta- 40 -85"C UNIT
Ta-25"C
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
5.9
6.0
4.18
4.31
4.13
5.80
5.63
5.68
0.1
0.0
0.1
O. I
0.0
0.1
V
0.1
O. I
0.0
0.26
0.33
0.17
0.33
0.26
0.18
±0.5
±5.0
MIN.
1.5
'3.15
4.2
-
-
±O.I
4.0
-
±1.0
40.0
tt A
TC74HC374AP1AF1AFW __________________
TC74HC534APIAF
TIMING REQUIREMENTS(lnput tr=tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CK)
tW{l-l)
tW(L)
Minimum Set-up Time
(Dn)
ts
Minimum Hold Time
(Dn)
th
Clock Frequency
f
Vcc
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
0
0
0
6
31
36
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
95
ns
19
16
0
0
0
5
MHz
25
29
AC ELECTRICAL CHARACTERISTICS(lnput t r =tf=6ns)
TEST
Ta--40 -85"C
Ta-25"C
PARAMETER
UNIT
SYMBOL
CONDITION CL
Vcc MIN. TYP. MAX. MIN. MAX.
2.0
20
60
75
tTLH
Output Transition rime
50
4.5
6
12
15
t11-lL
6.0
5
10
13
2.0
45
140
175
4.5
50
15
28
35
tpLH
Propagation Delay Time
6.0
24
13
30
2.0
60
190
240
(CK-Q,Q)
150 4.5
20
38
48
tPHL
17
32
6.0
41
2.0
39
135
170
50 4.5
13
27
tpZL
34
6.0
23
29
11
Output Enable time
ns
RL = 1 kQ
2.0
54
185
230
150 4.5
18
37
46
tPlH
6.0
15
31
39
2.0
30
135
170
tpLZ
Output Disable time
RL = 1 kQ
4.5
50
13
27
34
tpHZ
6.0
12
23
29
2.0
18
6
5
50 4.5
31
75
25
Maximum Clock
29
6.0
36
90
fMAX
2.0
4
16
3
Frequency
22
17
150 4.5
54
26
62
20
6.0
Input CapacItance
5
10
10
CIN
Output Capacitance
pF
10
COUI'
Power Dissipation Capacitance Cpo (l)
47
Note (1) C Fl) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCq,p=Cro • VOC· fN +IOC 18(per Flip Flop)
And the total Cro when n pcs. of F/F operate can be gained by the following equation:
Cro( total) =30+ 17 • n
HC-526
_ _ _ _ TC74HCT374AP/AF/AFW
TC74HCT534AP/AF
OCTAL D-TYP-E FLIP-FLOP WITH 3-STATE OUTPUT
TC74HCT374AP/AF/AFW NON-INVERTING
TC74HCT534API AF
INVERTING
The TC74HCT374A and HCT534A are high speed CMOS
OUTPUT
OCTAL FLIP-FLOPs with 3-STATE
fabricated with silicon gate C~OS technology.
They achieve the high speed operation similar .to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Their inputs are compatible with TTL, NMOS, and
CMOS output voltage levels.
These 8-bit D-ty'pe flip-flops are controlled by a clock
input (CK) and an output enable input (OE).
'
The TC74HCT374A has non-inverting outputs, and the
TC74HCT534A has inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. f.'Mx=41MHz(Typ.)at Vcc=5V
• Low Power Dissipation ............ Icc=4IlA(Max.)at Ta=25"C
• Compatible with TTL outputs'" VIH=2V (Min.)
V 1L =O.8V (Max.)
• Wide interfacing ability .. •• .... · .. · LSTTL, NMOS, CMOS
• Output Drive Capability ............ 15 LSTTL Loads
• Symmetrical Output Impedance "'1 1001 =IOL =6mA(Min.)
• Balanced Propagation Delays ...... tpLH '" tpI-IL
• Pin and Function Compatible with 74LS374/534
P(DIP20-P-300A)
20~ 20~
1
F(SOP20-P-300)
PIN ASSIGNMENT
TC74HCT374A
OE I
00 2
DO 3
01
4
01
5
02 6
02 7
03 8
03 9
GNO 10
TRUTH TABLE
1
FW(SOL20-P-300)
20
19
18
17
16
15
14
13
12
11
Vee
07
07
06
06
05
05
04
04
CK
TC74HCT534A
OE 1
INPUTS
OUTPUTS
OE CK
0
X
X
X
Z
Qn
Z
Qn
L
L
H
H
H
L
H
L
L
L
S
S
L
00 2
DO 3
01 4
Q(T374A) Q(T&34A)
01 5
02 6
02 7
03 8
x : Don't Care
Z .!..-High Impedance
On(On) : No Change
03 9
GNO 10
HC-527
20
19
18
17
16
15
14
13
12
11
Vee
07
07
06
06
05
05
04
04
OK
TC74HCT374AP/AF/AFW _________________
TC74HCT534AP/AF
IEC LOGIC SYMBOL
TC74HCT534A
TC74HCT374A
OE
CK
ao
00
01
02
03
D4
05
D6
07
as
00
01
02
03
D4
05
as
06
07
07
01
02
03
04
Cio
SYSTEM DIAGRAM
TC74HCT374A
00
01
ao
02
01
03
02
04
03
05
Q4
D6
as
07
Q6
TC74HCT534A
00
01
02
03
HC-528
D4
05
06
07
07
_ _ _ _ _ _ _ _ _ _ _ _ _ TC74HCT374AP/AF/AFW
TC74HCT534APIAF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
Vi:"
VOLT
11K
10K
IOlJT
lee
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP)*/180(MFP)
-65 -150
300
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VL'\I
Vour
Topr
tr. tr
VALUE
4.5 - 5.5
o -Vee
0- Vee
-40 - 85
0-500
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Low-Level
Output Voltage
3-State Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
Vm
VOL
1(Jl
liN
lee
boice
TEST CONDITION
Vee
4.5
l
5.5
4.5
l
5.5
1m --20 IlA 4.5
VIN=
VIHorVIL 1m --6 mA 4.5
IOL -20 IlA 4.5
Vl'lIVIHorVIL 101.. -6 mA 4.5
VI~-VIH or VIL
5.5
VOI.:r=Vee or GND
VIC\! ...:Vee or UNlJ
5.5
VN-Vee orGND
5.5
PER INPUT:VIN=O.5V or2.4V
5.5
OTHER INPUT:VINor GND
HC-529
MIN.
Ta- 40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
4.4
4.18
-
4.4
4.13
-
V
-
4.5
4; 31
0.0
0.17
0.1
0.26
0.1
0.33
V
-
-
±0.5
±5.0
IlA
±1.0
40.0
IlA
2.9
rnA
-
-
±0.1
4.0
2.0
-
-
TC74HCT374AP/AF/AFW _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HCT534API AF
TIMING REQUIREMENTS{lnput t,=t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width tW(H)
(CK)
tW(L)
Minimum Set-up Time
ts
(Dn)
Minimum Hold Time
th
(Dn)
Clock Frequency
f
Vcc
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
T.a-25"C
LIMIT
TYP.
15
14
15
14
0
0
31
37
Ta- 40 -85"C
UNIT
LIMIT
19
17
19
ns
17
0
0
25
30
MHz
AC ELECTRICAL CHARACTERISTICS(lnput t,=t,=6ns)
TEST
Ta":' 40 -85"(;
Ta-25"C
PARAMETER
SYMBOL
UNIT
CONDITION CL Vcc MIN. TYP. MAX. MIN. MAX.
7
tTLH
12
15
Output Transition Time
50 4.5
tTHL
6
5.5
11
14
'20
4.5
30
38
50
Propagation Delay Time
5.5
17
25
31
tPlil
(CK-Q. Q)
tllHL
4.5
25
38
48
150
5.5
22
41
33
4.5
17
30
38
50
ns
5.5
25
tp7L
14
31
Output Enable time
RL=lkQ
trJZH
4.5
25
38
48
150
5.5
19
33
41
tpLZ
35
16
28
Output Disable time
RL= 1 kQ
50 4.5
tpHZ
5.5
14
24
30
Maximum Clock
4.5
31
50
25
f MAX
50
Frequency
37
5.5
59
30
Input Capacitance
{.;IN
5
10
10
Output Capacitance
pF
CaJr
10
Power DissiDation CaD8.citance
C~ll
48
Note(1} Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCq,D=CPO • VOCofN +Ioc /8(per bit)
And the total Cpo when n pcs. of Flip Flop operate can be gained by the following equation:
Cpo (total) =30+18 • n
-
-
HC-530
------TC74HC375API AF
4-;-BIT 0 TYPE LATCH
The TC74HC375A is a high speed CMOS D-TYPE LATCH
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It contains two groups of 2-bit latches controlled by an
enable input (Gl • 2 or G3. 4) and each group can be used
in different circuits.
Data applied to the data inputs are transferred to the Q
and Q outputs when the enable inputs is high. When the. enable input is low,the outputs are not affected.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1.~
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
FEATURES;
• High Speed ................................. tpd=14ns(typ.)at Vcc=5V
• Low Power Dissipation .......•...•..• Icc =4ttA(Max.)at Ta=25"C
• High Noise Immunity··············· VNltFVNlL =2B"VcdMin.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance "·IIQiI=Ia. =4mA(Min.)
• Balanced Propagation Delays ...... tpUf"itpHL
• Wide Operating Voltage Range '" Vcc(opr)= 2 V -6V
• Pin and Function Compatible with 74LS375
PIN ASSIGNMENT
10
1. Vee
lei 2
111 40
1Q
3
14
G1·2
4
13 40
2Q
II
2li
•
11 3Q
7
10
3Ci
8
•
30
20
GNO
4'lr
12 03·4
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
INPUTS
OUTPUTS
D
G
0
0
L
H
L
H
H
H
L
X
X:
H
On
L
On
FUNCTION
LATCH
Don't eare
HC-531
1D
Q1·2
2D
3D
03·4
4D
10
10
ZQ
ZQ
3Q
3Q
4Q
4Q
TC74HC375AP/AF _ _ _ _ _ _ _ _ _ _ _ _ _ __
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Supply Voltage Range
Vex::
DC Input Voltage
VIN
DC Output Voltage
Voor
Input Diode Current
11K
Output Diode Current
10K
DC Output Current
loor
DC Vee/Ground Current
lex::
Power Dissipation
PD
Storage Temperature
Tstg
Lead Temperature 10sec
TL
VALUE
-0.5-7
-0.5 -Vex::+0.5
-0.5 ....,.Vex::+0.5
±20
±20
±25
±50
SOO(DIP)*1180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
rnW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 65"C a derating factor of
-lOmW/"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
UNIT
V
V
V
"C
VALVE
2-6
O-Vex::
O-Vex::
-40 - 85
o- l000(Vex::=2.0V)
0- 500(Vex::=4.5V)
0"'" 400(Vex::=6.0V)
SYMBOL
Vex::
VIN
VOfJI'
Topr
tr • tr
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
Va.
Input Leakap Current
Quieant Supply Current
liN
lex::
TEST CONDITION
VIN=
VIHorVIL
VIN=
VlHorVIL
100 =-20lt A
100 --4 mA
100 =-5. 2mA
lex.. =20 itA
lex.. -4 mA
lex.. =5.2mA
VII'; -'Vex:: or GND
VIN -'Vex:: or GND
Vex::
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-532
Ta-.25"C
'l'a- 40 -85"C
TYP. MAX. MiN. MAX. [uNIT
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.1
0.1
0.0
0.0
0.1
0.1
V
0.1
0.1
0.0
0.26
0.33
0.17
0.33
0.26
0.18
±O.l
±1.0
itA
4.0
40.0
MiN.
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
TC74HC375APIAF
TIMING REQUIREMENTS (Input tr=tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(G)
twOi)
Minimum Set-up Time
t8
Minimum Hold Time
th
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
0
0
0
1'a- 40 -85"C
UNIT
LIMIT
95
19
16
95
DS
19
16
0
0
0
AC ELECTRICAL CH ARACTERISTICS(C L =16pF, Vcc=6V, Ta=26"C)
PARAMETER
Output Transition Time
Propagation Delay_TIme
(DATA-Q.Q)
Propagation De~y Time
(G-Q.Q)
SYMBOL
MIN.
TEST CONDITION
t1U{
tTI-II.
tpLH
tDIiL
tpLH
toHL
TYP.
MAX.
-
4
8
-
14
20
-
13
20
UNIT
DS
AC ELECTRICAL CHARACTERISTICS(CL =60pF,lnput t r =t,=6ns)
Ta- 40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
2.0
30
75
95
t1U{
Output Transition Time
19
4.5
8
15
tnn.
6.0
7
13
16
2.0
60
120
150
Propagation Dela~Time
tpLH
DS
4.5
17
24
30
(DATA-Q.Q)
tJilL
6.0
20
26
15
2.0
56
120
150
Propagation D~y Time
tpLH
4.5
16
24
30
(G-Q.Q)
tp-iL
6.0
20
26
14
Input Capacitance
GIN
5
10
10
pF
Power Dissipation Capacitance Cpom
55
Note (1) Cm is deCined as the value of the internal equivalent capacitance which 1S calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia;~=C PO • Va:' fIN +Ia: 14(per Latch)
PARAMETER
SYMBOL TEST CONDITION
Va;
MIN.
-
-
-
HC-533
TC74HC375AP/AF - - - - - - - - - - - - - - - -
SYSTEM DIAGRAM
G1.2~L_ _""
I-I ~
30
lO~_-:: ~--::
q,
HC-534
------TC74HC377API AF
OCTAL D-TVPE FLIP-FLOP
The TC74HC377A is a high speed CMOS OCTAL
D-TYPE FLIP- FLOP fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintainiI)g the CMOS low power
dissipation.
These 8-bit D-type flip-flops are controlled by a clock
input (CK) and an output enable input (G).
The signal level applied to the D inputs are transferred
to Q outputs during the positive going transition of CK.
When the G is high, the eight outputs are in a high
impedance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. f~l.u=73~HZ(typ.)at Va;=5V
• Low Power Dissipation ............ Icc=4ttA(Max.)at Ta=25"C
• High Noise Immunity··············· V:,\IH =V:,\IL =28% Vcc(Min.)
• Output Drive Capability··· ......... 10 LSTTL Loads
• Symmetrical Output Impedance ···1 Ia-Ji =IOL =4mA(Min.)
• Balanced Propagation Delays······ t pU-I '" t pHL
• Wide Operating Voltage Range ... Vcc (opr)=2V-6V
• Pin and Function Compatible with 74LS377
P(DIP20-P-300A)
20~
1
F(SOP20-P-300)
PIN ASSIGNMENT
ENABLE
G
1
20 Vee
10 2
19 80
10 3
18 80
20 4
17 70
20
5
16 70
30 6
15 60
3D
7
14 60
40 8
13 50
40 9
12 50
GN010
1.1 CLOCK
(TOP
TRUTH TABLE
VIEW)
IEC LOGIC SYMBOL
G
INPUTS
OUTPUTS
CK
G
CLOCK
DATA
0
H
X
X
No Change
L
L
03
H
H
X
No Change
04
05
L
L
X
S
S
L
X : Don·' care
HC-535
01
01
02
02
03
04
05
06
Ci6
07
08
08
07
TC74HC377AP/AF - - - - - - - - - - - - - - - -
SYSTEM DIAGRAM
10
20
3D
40
50
60
70
80
CLOCK ~1~1~____;_~----;_~----;_+-----+_+-----T_+-----T_~----~
10
20
40
.~-:
HC-536
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC377AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
VOIJI'
11K
10K
IOlJf
lee
PD
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)·/180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-tOm WI"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VIN
VOlJf
Topr
tr • tr
VALUE
2-6
o -Vee
o -Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
lee
II~
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
1m =-20JlA 4.5
VIN=
6.0
VIHorVIL
IOH - 4 rnA 4.5
1.0-1 =-5. 2mA 6.0
2.0
IOL =20 JlA 4.5
VIN=
6.0
VIHorVIL
1 01 • -4 rnA 4.5
IOL =5.2mA 6.0
6.0
VIN -Vee or GND
VIN -Vee or GND
6.0
He-537
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.18
4.31
4.13
5.68
5.80
5.63
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.1
0.0
0.26
0.33
0.17
0.26
0.33
0.18
+1.0
+0.1
JlA
4.0
40.0
MIN.
1.5
3. 15
4.2
-
TC74HC377AP/AF - - - - - - - - - - - - - - - -
TIMING REQUIREMENTS(lnput tr=tr =6n8)
PARAMETER
SYMBOL
Minimum Pulse Width
(CLOCK)
tW(H)
tW(L)
Minimum Set-up Time
(D-CK)
ts
Minimum Set-up Time
(O-CK)
ts
Minimum Hold Time
th
Clock Frequency
f
-
TEST CONDITION
Ta=25"C
Vee
TYP.
2.0
4.5
6,0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6:.0
2.0
4.5
6.0
Ta=-40 - 85"C
-
LIMIT
75
15
13
75
15
13
-
75
-
-
15
13
0
0
0
7
36
42
-
-
LIMIT
95
19
16
95
19
16
95
19
16
0
0
0
6
29
34
t:XIT
ns
MHz
AC ELECTRICAL CHARACTERISTICS(C L=15pF, Vcc=5V, Ta=25"C)
PARAMETER
Output Transition Time
Propagation Delay Time
(CLOCK-Q)
Maximum Clock FreQuency
SYMBOL
TEST CONDITION
tn.H
tTI-lL
tpLH
toHL
MIN.
TYP.
MAX.
-
4
8
-
14
24
73
-
fMAX
38
AC ELECTRICAL CH ARACTERISTICS(CL=50pF ,Input tr=tf =6n8)
PARAMETER.
SYMBOL TEST CONDITION
Ta=25"C
r--
UNIT
ns
Ta=-40 -85"C
MHz
UNIT
TYP. MAX. MIN. MAX.
2.0
30
75
95
t11..H
4.5
Output Transition Time
8
15
19
tTHL
6.0
7
16
13
ns
2.0
175
57
140
Propagation Delay Time
tpLH
4.5
17
28
35
(CLOCK-Q)
tpHL
6.0
13
24
30
2.0
7
6
18
Maximum Clock
- MHz
fMAX
4.5
29
36
59
Frequency
6.0
42
77
34
Input Capacitance
Cil"
10
10
5
pF
Power Dissipation Capacitance
CPD
32
Note(1) Cro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia:.(W=Cro • Vcr;. f~ +Icr; /8(per Frip Flop)
And the total Cro when n pes.of Flip Flop operate can be gained by the following equation:
Cro(total)=22+10·.n (PF)
Va:.
HC-538
MIN.
------TC74HC386AP/AF
QUAD EXCLUSIVE OR GATE
The TC74HC386A is a high speed CMOS EXCLUSIVEOR GATE fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is includes on output buffer. which
provide high noise immunity and stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd =10ns(typ.)at Vex=5V
• Low Power Dissipation ............ Icc=1 tt A(Max.)at Ta=25"C
• High Noise Immunity··············· V"'IH =V\IL2896 Vex (Min.)
• Output Drive Capability······ ...... 10 LSTTL Loads
• Symmetrical Output Impedance ... I IOH I =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpU"1 "" tpHL
• Wide Operating Voltage Range ... Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS386
1
P(DIP14-P-300)
14~
1
F(SOP14-P-300)
PIN ASSIGNMENT
14 Vee
lA
18
2
13
48
lY
3
12
4A
2Y
4
11
4Y
2A
5
10
3Y
28
6
9
38
GND
7
8
3Y
(TOP VIEW)
IEC LOGIC SYMBOL
II.
lB
21.
2B
31.
3B
41.
4B
TRUTH TABLE
IY
2Y
3Y
4Y
HC-539
A
B
Y
L
L
L
L
H
H
H
L
H
H
H
L
TC74HC386AP/AF - - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC. Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vcc/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vcc
VI:\
VOLT
11K
10K
IOLT
Icc
PD
Tstg
TL
VALUE
-0.5-7
-0.5 -Vcc+0.5
-0.5 -Vcc+0.5
±20
±20
±25
±50
500(DIP) *1180(MFP)
-65 -150
300
UNLT
V
V
V
rnA
rnA
rnA
rnA
mW
cC
*500mW in the range of Ta=
-40·C- 65"C. From Ta=65"C
to 85°C a derating factor of
-lOmWI"C shall be applied
until 300m W.
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
InputV6ltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
I
Vcc
VI:\
VOLT
Topr.
t r , tr
VALUE
2-6
0- Vcc
0- Vcc
-40 - 85
0- 1000(Vcc =2.0V)
0- 500(Vee =4.5V)
o - 400(Vcc =6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
High-Level
Input Voltage
Low-Level
Input Voltage
High-Level
Output Voltage
Low-Level
Output Voltage
SYMBOL
TEST CONDITION
Vee
2.0
VIH
4.5
6. 0
2.0
VIL
4.5
6.0
2.0
IOH
=-2011.
A
4.5
VI:\ =
6.0
Val
VlllorVIL
la-l =-4 rnA 4.5
100 =-5.2rnA 6.0
2.0
la. =20 tt A 4.5
\h VI:\=
6.0
VlllorV". la. -4 rnA I 4.5
I
la. =5.2rnA 6.0
6.0
11:\
I VI:\ -Vee or GND
Icc i V I:\ -VCC or GND
6.0
I
I
Input Leakage Current
QuieSCtnt Supply Currenl
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3. 15
4.2
0.5
0.5
V
1. 35
1. 35
- , 1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.13
4.31
4.18
5.68
5.80
5.63
O. I
O. 1
0.0
O. 1
O. 1
0.. 0
V
0.1
0.1
0.0
0.26
0.33
, 0.17
! 0.18
0.26
0.33
±O.l
±1.0
A
- I
10.0 tt
1.0
MIN.
1.5
3. 15
4.2
-
TC74HC386APIAF
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
t TI•H
tniL
tpLH
teloo.
Propagation Delay Time
TEST CONDITION
MIN.
TYP.
-
4
8
-
10
17
MAX.
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =tf=6ns)
Ta--40 -85"C
Ta-25"C
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vee MIN. TYP. MAX. MIN. MAX.
2.0
75
95
30
tTUI
Output Transition Time
4.5
8
15
19
tTilL
6.0
7
13
16
ns
2.0
48
100
125
tplJi
Propagation Delay Time
4.5
12
20
25
tpliL
6.0
11
17
21
Input Capacitance
5
10
10
C 1:'\
pF
Power Dissipation Capacitance cpom
31
Note(I) CR) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IcctpFC po. Vcr;. f 1:,\+1 cr;/4(per Gate)
HC-541
TC74HC390API AF I A F N - - - DUAL DECADE COUNTER
The TC74HC390A is a high speed CMOS DUAL
DECADE COUNTER LATCH fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It consists of two independent 4-bit counters, each
composed of a divide-:-by-two and a divide-by-five
counter. The divide- by-two counter is incremented on the
negative going transition of clock A(CKA). The dividedby-five counter is incremented on the negative going
transition of clock B(CKB). The counter can b.e cascaded
to form decade, bi-quinary, or various combinations up
to a divide-by-lOO counter. When the CLEAR input is set
high, the Q outputs are set to low independent of the clock
inputs.
All inputs are equipped with protection circuits against
static dischage or transient excess voltage.
FEATURES:
• High Speed .............................. fMAX=84MHz(typ.}atVee=5V
• Low Power Dissipation ............ lee=4ttA(Max.}at Ta=25"C
• High Noise Immunity .............. · VNIH =VNIL 2896 Vee (Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance "'1100 1=101.. =4mA(Min.)
• Balanced Propagation Delays ...... tpl.H'TtpHL
• Wide Operating Voltage Range'" Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS390
IEC LOGIC SYMBOL
1
P(DIP16-P-300A)
F(SOP16-P-300)
PIN ASSIGNMENT
lCKA 1
lCLR 2
16 Vee
lOA 3
leKB 4
lOa 5
14 2CLR
15 2CKA
1320A
12 2CKB
11 20e
10 20e
10c 6
10D 7
GND 8
9 20D
(TOP VIEW)
BLOCK DIAGRAM
CKA
ICKe
FN(SOL 16-P-150)
lOA
IOe
lac
100
CLR
1.15
BINARY
3.13
COUNTER
2.14
I
5.11
CKB
20A
20e
20c
200
4.12
QUINARY
COUNTER
---.J
VCC=16.GND=8
HC-542
QA
6.10
7.9
QB
QC
QD
- - - - - - - - - - - - - - TC74HC390AP/AF/AFN
TRUTH TABLE
CKA
INTPUTS
CKB
l:.
X
X
X
X
'l.
OUTPUTS
OA I OB I OC I OD
L
I L I L I L
BINARY COUNT UP
OUINARY COUNT UP
CLR
H
L
L
SYSTEM DIAGRAM(1/2 package)
Lo
CK R Q
CKA
CLR
oj
OA
?
-t>
1n
CK8 --c£>-{)~
'"V"
O~ t--
D
CK
R
Q
08
Y
LD
0"""'
CK R Q
-"
..."....
OC
..r-..
00
Y
~o
CKRQ
y
HC-543
"V"
TC74HC390AP/AF/AFN - - - - - - - - - - - - - -
(1)BCD COUNT SEQUENCE·
CKA
CLR
-,
QB
....
' -t+--;
QC-'
,---H--+--!---'
Z I
CLR
3 1 •
1
,1,
• QA connected to CKB
(2)BI-QUINARY COUNT SEQUENCE··
CLRJIl~
______________________________________
QB -,
QC -,
_1-++--,
QD -,
-J--++---1!----+--..,..~
QA -j
]1,
CLR
2
.. QD connected to CK A
HC-544
TC74HC390APIAF I AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI~
VOLT
11K
10K
lOUT
lee
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vcc+0.5
±20
±20
±25
±50
500(DIP)*/180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*5OOmW in the range of Ta=
-40"C- 65"C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI!"
VOlJf
Topr
tr , tr
VALUE
2-6
0- Vee
0- Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o - 400(Vee=6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Va-!
Low-Level
Output Voltage
Vex..
Input Leakage Current
Quiescent Supply Current
1,"1
lee
TEST CONDITION
Vee
·2.0
4.5
6.0
2.0
4. 5
6.0
2.0
I OH =-20tl A 4.5
VI'" =
6.0
VIHorVIL
IOH --4 rnA 4.5
IOH =-5. 2mA 6.0
2.0
lex.. =20 I1A 4.5
VI:"; =
6.0
VII_lorVII•
lex.. -4 rnA 4. 5
lex.. =5.2mA 6.0
6. 0
VI" -Vee or GND
VI:'''; -Vee or GND
6.0
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
l.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
l.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.0
0.1
0.1
0.1
0.0
0.1
V
0.0
0.1
0.1
0.17
0.26
0.33
0.26
0.18
0.33
+0.1
+1.0
I1A
4.0
40.0
MIN.
1.5
3.15
4.2
TC74HC390APt AFt AFN
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
tWOi)
tW(L)
Minimum Pulse Width
(CLR)
tWOi)
Minimum Removal Time
trem
Clock Frequency
(CKA)
f
Clock Frequency
(CKB)
f
Vcr:
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6 0
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
25
5
5
6
32
38
6
31
36
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
30
6
ns
5
5
26
31
5
25
29
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
t11.H
tTI:JL
~
tDHL
tpu.J
tpHL
tpu.J
tpHL
tpu.J
tpHL
Propagation Delay Time
(CKA-'-QA)
Propagation Delay Time
(cKA-QC-)
Propagation Delay Time
(CKB-QB,QD)
Propagation Delay Time
(CKB-QC)
Propagation Delay Time
(CLR-Qn)
Maximum Clock Frequency
(CKA)
Maximum Clock Frequency
(CKB)
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
10
20
-
29
51
-
12
22
-
17
32
tpHL
-
12
26
fMAX
35
84
-
f MAX
33
65
-
QA connected to CKB
HC-546
UNIT
ns
MHz
- - - - - - - - - - - - - - TC74HC390AP/AF/AFN
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =t,=6ns)
Ta-25"C
Ta--40 -85"C
UNIT
TYP·. MAX. MIN. MAX.
75
95
30
tnll
Output Transition Time
15
19
8
tTHL
7
13
16
39
120
150
Propagation Delay Time
tpLH
24
13
30
tpHL
(CKA-QA)
20
26
11
102
290
365
QA connected to
Propagation Delay Time
tpt.H
34
58
73
tpHL
(CKA-QC)
CKB
29
62
49
ns
45
130
165
Propagation Delay Time
tpLH
33
15
26
tpliL
(CKB-QB.QD)
13
22
28
63
185
165
Propagation Delay Time
1pt.H
21
37
33
tpHL
(CKB-QC)
18
31
28
45
150
190
Propagation Delay Time
tpHL
15
30
38
(CLR-Qn)
26
32
13
6
5
20
Maximum Clock Frequency
fMAX
32
77
26
(CKA)
- MHz
38
90
31
6
5
15
Maximum Clock Frequency
25
fMAX
31
60
(CKB)
29
36
70
Input Capacitance
5
10
10
C'N
pF
Power Dissipation Capacitance
CpDW
44
Note (I) Cm is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
leeq,o=CpD - Va;- f ,,\+Ia; 12(per Counter)
PARAMETER
SYMBOL TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
He-54?
MIN.
~
TC74HC393AP/AF/AFN----DUAL BINARY COUNTER
The TC74HC393A is a high speed CMOS 4-BIT
BINARY COUNTER fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It contains two independent counter circuits in one
package, so that counting or frequency division of eight
binary bits can be achieved with one IC.
This device changes state on the negative going
transition of the CLOCK pulse. The counter can be reset
to "0" (QO-Q3="L") by a high at the CLEAR input
regardless of other inputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. fMAX =72MHz(Typ.)at Vcr;=5V
• Low Power Dissipation ............ Icr;=4.uA(Max.)at Ta=25"C
• High Noise Immunity··············· V:->IH=VNlL28% VcC - - - - i CK R Q 1--"'---1 CK R Q t - - . - - - i CK R Q 1--.......--1 CK R Q
CLR
QA
Q8
HC-549
QC
QO
TC74HC393AP/AF/AFN - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI~
VOLT
11K
10K
IOLT
Icc
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 - Vee+0.5
±20
±20
±25
±50
500(DIP)*/180(MFP)
-65 -ISO
300
UNIT
V
V
V
mA
mA
mA
mA
mW
°C
OC
*500m W in the range of Ta=
-40·C- 65"C. From Ta=65·C
to 85·C a derating factor of
-10m Wrc shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI~
VOLT
Topr
tr • tr
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
UNIT
V
V
V
OC
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vorl
TEST CONDITION
Vee
2.0
4.5
6.0
, 2.0
4.5
6.0
2.0
Irn =-20 tl A 4.5
VI~=
6.0
VlliorVIL
Irn --4 mA 4.5
lrn =-5. 2mA 6.0
2.0
IOL =20 /1.A 4.5
VI~=
6.0
VlliorVU• Ia. -4 rnA
4. 5
la. =5.2mA 6. 0
6.0
VI~ -Vee or GND
6.0
VI~ -Vee or GND
I
Low-Level
Output Voltage
Va.
Input Leakage Current
Quiescent Su pply Current
lex;
II~
HC-550
Ta-25OC
Ta--40 -85OC UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
6.0
5.9
5.9
4.13
4.18
4.31
5.68
5.80
5.63
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.1
0.0
0.26
0.33
0.17
0.26
0.33
0.18
±0.1
±1.0
/1. A
4.0
40.0
MIN.
1.5
3.15
4.2
-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC393AP/AF/AFN
AC ELECTRICAL CHARACTERISTICS(C L =16pF,Vcc =6V,Ta=26"C)
PARAMETER
Output Transition Time
Propagation Delay Time
(CLOCK-QA)
Propagation Delay Time
. (CLOCK -QB)
Propagation Delay Time
. (CLOCK -QC)
Prop~a%oC Delay Time
-(i L
K-QD)
Propagation Delay Time
·(CLEAR-Qn)
Maximum Clock Frequency
SYMBOL
t Tl •H
tmL
tpLH
tllHl.
tp(.Ji
tpl1L
tpl..l1
tpili.
tpl.H
tpl1L
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
12
20
-
16
31
-
21
38
-
25
46
tpliL
-
15
26
f~'IAX
35
72
-
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF ,Input t r =t,=6ns)
Ta- 40 -85"C
..'!'a-25"C
UNIT
TYP. MAX. MIN. MAX.
2.0
25
75
95
tTLI-I
Output Transition Time
4.5
7
15
19
tmL
6.0
6
13
16
2.0
120
45
150
Propagation Delay Time
tpLH
4.5
15
24
30
(CLOCK-QA)
tllliL
6.0
20
26
13
2.0
60
180
225
Propagation Delay Time
tcul
4.5
20
36
45
tpilL
(CLOCK-QB)
38
6.0
17
31
2.0
80
220
275
Propagation Delay Time
tpLll
55
ns
4.5
25
44
(CLOCK-QC)
~IL
6.0
21
37
47
2.0
260
325
100
Propagation Delay Time
tnLH
4.5
52
30
65
tpHL
(CLOCK-QD)
6.0
26
44
55
2.0
55
150
190
Propagation Delay Time
tpHL
4.5
18
30
38
(CLEAR-Qn)
6.0
26
33
15
6
5
2.0
22
Maximum Clock Frequency
4.5
32
67
27
~"IAX
6.0
38
77
32
Input Capacitance
CI:-;
5
10
10
pF
Power Dissipation Capacitance CPD(1)
40
Note (1) C I~) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC ulll=C PD • Vcr;. r 1:-; +Icr;
PARAMt.rER
SYMBOL TEST CONDITION
Vee
HC-551
MIN.
TC74HC423API A F - - - - - - - DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR
The TC74HC423A is a high speed CMOS MONOSTABLE
MULTIVIBRATOR fabricated with silicon gate C'MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low powe~
dissipation.
There are two trigger inputs, A input (Negative edge),
and B input (Positive edge). These inputs are valid for a
slow rise/fall time signal (tr=t£=lsec.) as they are
schmitt trigger inputs.
After triggering, the output stays in a MONOSTABLE
state for a time period determined by the external resistor
and capacitor (Rx, Cx). A low level at the CLR input
breaks this state. In the MONO STABLE state, if a new
trigger is applied, it extends the MONOSTABLE period
(retrigger mode).
Limitations for Cx and Rlt are:
External capacitor Cx .... No limit
External resistor Rx .... Vcc<2.0V more than 5fi
VCC2::3.0V more than lkfi
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
16~
1
P(DIP16-P-300A)
16~
1
F(SOP16-P-300)
PIN ASSIGNMENT
1A 1
1B 2
1CLR 3
16 Vee
151Rx/Cx
14 1CX
10 4
FEATURES:
• High Speed .............................. tpd=25ns(typ.)at Vcc=5V
• Low Power Dissipation
Standby State Icc =4ttA(max.)at Ta=25"C
Active State
Icc=700ttA(max.)at Ta=25"C
• High Noise Immunity .•............• VX(H=VNfL28~ Vcc(min.)
• Output Drive Capability······ ...... 10 LSTTL Loads
• Symmetrical Output Impedance ... I IOH I =IOL =4mA(min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range ..• Vcc (opr.)=2V -6\tc
• Pin and Function Compatible with 74LS423
20 6
2CX 6
2Rx/Cx 7
GND 8
11 2CLR
10 2B
9 2A
(TOP VIEW)
IEC LOGIC SYMBOL
----------------TC74HC423AP/AF
TRUTH TABLE
INPUT
A
OUTPUT
NOTE
B
CLR
Q
Q
H
·H
-IL
--u-
X
L
H
L
H
INHIBIT
H
X
H
L
H
INHIBIT
H
-IL
--u-
L
L
H
L
L
S
X
X
OUTPUT ENABLE
OUTPUT ENABLE
INHIBIT
X:Don't Care
BLOCK DIAGRAM
D.
Dx
r--M--i
c. +,
r-+l--,
,
Cx
+
I
:
Voo
15
R.
13 0
B
5 0
B
40
12 _
0
11
CiJi
Notes: (l)Cx,Rx,Ox are external.
Capacitor ,Resistor, and Diode ,respectively .
CiJi
(2)External clamping diode,Ox;
The external capacitor is charged to Vcc level in the wait state, i. e. when no trigger is applied.
If the supply voltage is turned off, Cx is discharges mainly through the internal (parasitic) diode.
If Cx is sufficiently large and Vcc drops rapidly, there will be some possibility of damaging the
IC through in rush current or latch-up. If the capacitance of the supply voltage filter is large
enough and Vcc drops slowly, the in rush current is automatically limited and damage to the
IC is avoided.
The maximum value of forward current through the parasitic diode is ±20mA.
In the case of a large Cx, the limit of fall time of the supply voltage is determined as follows:
t f
~(Vcc-O. 7)
Cx/20mA
(t f is the time between the su pply voltage turn off
and the supply voltage reaching O. 4 Vcc.)
In the event a system does not satisfy the abo\'e condition,an external clamping diode (Ox) is
needed to protect the IC from rush current.
HC-553
TC74HC423APIAF
SYSTEM DIAGRAM
Vee
I'tx/ex
----+-t
ex
----+----'
Q ......
A
F/F
~---Q
m
TIMING
CHART
Irr
r-t
n
A
nJl
n
--VIH
Vll
VIH
B
Vll
vee
Rx/ex
-
Vr.fH
Vrefl
GND
ClR
VIH
-
I
Vll
n=VOH
Q
Q
VOL
I
I
~
I
I.
IW
I
.1
HC-554
u=VOH
IW+lrr
VOL
TC74HC423API AF
FUNCTIONAL DESCRIPTION
(!)Stand-by State
The external capacitor Cx is fully charged to Vcc in the stand-by state. That means, before triggering,
the Qp and QN transistors which are connected to the Rx/Cx node are in the off state. '!\vo comparators that
relate to the timing of the output pulse, and two reference voltage supplies turn off. The total supply
current is only leakage current.
(2lTrigger operation
Trigger operation is effective in either of the following two cases. First. the condition where
the A input is low. and the B input has a rising signal; second. where the B input is high. and the
A input has a falling signal.
After a trigger becomes effective. comparators Cl and C2 start operating. and QN is turned on.
The external capacitor discharges through QN . The voltage level of the Rx/Cx node drops.
If the Rx/Cx voltage level falls to the internal reference voltage Vref L. the output of Cl becomes
low. The flip-nop is then reset and QN turns off. At·that moment Cl stops but C2continues operating.
After QN turns off. the voltage at the Rx/Cx starts rising at a rate determined by the time
constant of external capacitor Cx and resistor Rx.
Upon the triggering. output Q becomes hjgh. following some delay time of the internal F/F
and gates. It stays high even if the voltage of Rx/Cx changes from falling to rising. When
Rx/Cx reaches the internal reference \'oltage Vref H. the output of C2 becomes low. the output Q
goes low and C2 stops its operation. That means. after triggering. when the voltage level of the
Rx/Cx reaches Vref H, the IC returns to its MONO STABLE state.
With large value of Cx and Rx. and ignoring the discharge time of the capacitor and .internal
delays of the IC. the width of the output pulse tw(OUT) is as follows:
tw(OUT)=l.OCx Rx
(3lRetrigger operation
When a new trigger is applied to input A or B while in the MONO STABLE state. it is effective
only if the IC is charging Cx. The voltage level of the Rx/Cx node then falls to Vref L level again.
Therefore the Q output stays high if the next trigger comes in before the time period set by Cx
and Rx.
If the 2nd trigger is very close to previous trigger. such as an occurrence during the discharge
cycle. it will have no effect.
The minimum time for a trigger to be effective 2nd trigger, trr(Min). depends on Vcc and Cx.
(4lReset operation
In normal operation,CLR input is held high. If CLR is low. a trigger has no effect because the
Q output is held low and trigger control F/F is reset. Also Qp turns on and Cx is charged rapidly
to·Vcc.
This means if CLR input is set low. the IC goes into a wait state.
HC-555
TC74HC423AP/AF--------------------------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI:>:
V(1T
11K
10{
I(n
lee
PD
Tstg
TI.
VALUE
-0.5-7
-0.5 -Vl :c +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)*/180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
(CLR Only)
External Capactior
External
Resistor
SYMBOL
Vee
VI:\:
V(1T
Topr
tr, tr
Cx
Rx
VALUE
2-6
o -Vee
o -Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
0-- 400(Vcc =6.0V)
No Limitation·
~5K· (Vcc<2.0V)
~ 1K· (Vcc;;:,3.0V)
UNIT
V
V
V
"C
ns
F
Q
• The maximum allowable values of Cx and Rx are !i function of leakage
of capacitor Cx, the leakage of TC74HC423A, and leakage due to board
layout and surface resistance.
Susceptibility to externally induced noise signals may occur for Rx> 1M Q.
HC-556
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating ractor of
-lOmW/"C shall be applied
until 300m W.
TC74HC423AP/ AF
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VII1
Low-Level
Input Voltage
VIL
High-Level
Output V~tage
VOH
(Q.Q)
Low-Level
Output V~tage
VOL
(Q.Q)
Input Leakage Current
Rx/Cx Terminal
Off-State Current
! Quiescent Supply Curren
Active-State.
Supply Current
11:\
TEST CONDITION
Vee
2. 0
4. 5
6. 0
2. 0
4. 5
6.0
2. 0
lell =-20tL A 4.5
VI:\=
6. 0
VIHorVIl.
1011 =-4 rnA 4. 5
101 I =-5. 2mA 6.0
2.0
4. 5
10L =20 tL A
V[\;=
6.0
VIHorVIL
I lOt ~4 rnA 4. 5
i 1o. =5.2mA 6. 0
VI:\ =Vcc orGND
6. 0
11:\
V I:\ =Vcc or GND
6.0
Icc
V I:\ =Vee or GND
6, 0
2. 0
4. 5
6.0
VI:\ =Vee or GND
Rx/Cx =0. 5Vcc
Icc
Ta--40 -85°C
Ta-25°C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4. 2
O. 5
0.5
_.
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4. 4
4. 4
4.5
V
5.9
5. 9
6.0
4. 13
4.18
4.31
5.BO
5.63
5.68
0.1
0.0
O. I
O. 1
O. \
O. 0
V
0.1
O. 0
0.1
0.26
0.33
0.17
0.18
0.26
0.33
±1.0
±O.l
MIN.
1.5
3.15
4. 2
-
-
-
±0.5
-
-
-
45
400
0.7
4.0
200
500
1.0
-
-
-
±5.0
tL A
-
40.0
260
650
1.3
tL A
Il A
rnA
-
-
.: per CIrcuIt
TIMING REQUIREMENTS(lnput t r =tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
tW(J.)
tW(H)
Minimum Clear Width
tW(L)
Minimum Clear Removal
Time
t rem
4.5
Rx=lKQ
Cx=100pF
Minimum Retrigger Time
Vcc
2.0
4.5
6.0
2.0
4.5
6.0
2.0
trr
Rx=lKQ
Cx=O.OlpF
6.0
2.0
4.5
6.0
2.0
4.5
6.0
He-55?
Ta-25°C
TYP.
LIMIT
75
15
13
75
15
13
5
5
5
325
lOB
78
5. 0
1.4
1.2
Ta--40 -85°C
UNIT
LIMIT
95
19
16
95
19
16_ _
ns
5
5
5
-
-
Il S
TC74HC423API AF
AC ELECTRICAL CHARACTERISTICS(C L =15pF,Vcc=5V,Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
Propag~on Del~
Time
(A.B-Q.Q)
Propagation Del9 Time
(CL-Q.Q")
TEST CONDITION
t1LH
tUll
tpLH
t ,lIll.
t pI.1i
t ~-II.
MIN.
TYP.
MAX.
-
4
8
-
25
36
-
16
27
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =tf=6ns)
Ta'-25"C
Ta- 40 -85"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Va:. MIN. TYP. MAX. MIN. MAX.
30
75
95
2.0
tTU-I
Output Transition Time
8
15
4.5
19
tUll
6.0
7
13
16
102
210
265
2.0
Propagation Delay Time
tplJI
29
ns
4; 5
42
53
(A.B-Q.Q)
tpl'll
22
6.0
36
45
68
200
160
2.0
Propagation Delay Time
tplJI
20
32
40
4.5
(CL-Q.Q)
t'~-II.
6.0
16
27
34
700
Cx=28pF
2000
2500
2.0
Rx=6KQ(Vcc =2V) 4.5
250
ns
500
400
210
Rx=2K Q(Va:. =4.5V.6V) 6.0
425
340
130
90
90
130
110
2.0
Cx=O.Ol/1.F
Output Pulse Width
95
115
95
105
115
4.5
tWOl:r
/1.s
Rx=lOKQ
105
6.0
115
95
95
115
0.9
1.0
1.2
0.9
1.2
2.0
Cx=O.l/1. F
ms
4.5
0.9
1.0
1.1
0.9
1.1
Rx=lOKQ
6.0
0.9
1.0
0.9
1.1
1.1
Output Pulse Width Error
Between Circuits
!1tWQL"l
±l
%
(In same Pack8.£e)
Input Capacitance
C,,,
5
10
10
pF
Power Dissipation Capacitance CPl)(l)
Note (l)
162
Note (1) Cft) 18 defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IcCQJl\=C PD· Vo:;.fl:x+ I 0:;'. Duty/lOO+I 0:; /2(percircuit)
(10:; • :Active Supply Current)
-
(Duty:")
He-558
- - - - - - - - - - - - - - - - - - TC74HC423AP/AF
OUTPUT PULSE WIDTH
CONSTANT K-SUPPLY
VOLTAGE
(TYPICAL)
(EXTERNAL RESISTOR (Rx)=101<
.1
I.
CX=O.OI ~F
I-
z 1.1
'"t;;
z
0
C~=O.h~
u
:c
l - 1.0
e
I
CX=1 ~F
i
.....
'"-':::>
"- 0.9
I-
:::>
":::>
I-
345
0
SUPPL Y VOLTAGE
6
Vcc(V)
tWOUT - Cx CH ARACTERISTICS (TYP.)
Vc:c=4.5V
CL =50pF
,
I'
V
j
-.......
Ta=25'C
Rx=IMQ
10
c;;
t rr -Vee CHARACTERISTICS (TYP)
Rx=I00JtQ
10
10
/
V
/
~
0
>=
e
i
.....
Rx= 1 OkQ
10
/
-'
'"
:::>
./
I-
:::>
"I:::>
1
/
.....
"-
RX=1kQ
"-
1
---
CxzO.OhF-
"'"
I'
V
l-
"-
]:
:::0
~
:c
,
'"...
V
0.1
........
. . . . . ·r
,OOOp
~ .........
j-
l:l
Cx=I00pF
0
10- 1
0
10'
10'
10'
EXTERNAL CAPACITOR Cx (pF)
1
2
3
SUPPLY VOLTAGE
HC-559
4
Vt;I; (V)
5
6
TC74HC540AP/AF/AFW
--------------------TC74HC541AP/AF/AFW
OCTAL BUS BUFFER
TC74HC540AP/AF/AFW
INVERTING,3-STATE OUTPUTS
r--_T!.-'C=-=...;74:!.!H,-,-C=54~1...A;;:..:...P....
1 Ao::.:...F..:../..::A!.!F-'W:.:......_.:.:N'-=O~N"'--......:...:1N~V-"E,,-!R..:..T~IN:.z..=;G 3-ST T 0 U T PUTS
The TC74HC540A/TC74HC541A are high speed CMOS
OCTRAL BUS BUFFERs fabricated with silicon gate
C2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the Cl\lOS low power
dissipation.
The TC74HC540A is a non-inverting type, and the TC74
HC54lA is an inverting type.
When either Gl or G2 are high, the terminal outputs are
in the high-impedance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
P(DIP20-P-300A)
a~,.~
1
F(SOP20-P-300)
FEATURES:
• High Speed .•............................ tpd=10ns(typ.)at Va.;=5V
• Low Power Dissipation ............ Ia.;=4ttA(Max.)at Ta=25"C
• High Noise Immunity··············· V,"IH =V:"IL28% Va.; (Min.)
• Output Drive Capability······ ...... 15 LSTTL Loads
• Symmetrical Output Impedance ... IIOH I =IOL =6mA(Min.)
• Balanced Propagation Delays ...... tpLH" tpHL
• Wide Operating Voltage Range ... Va.; (opr)=2V-6V
• Pin and Function Compatible with 74LS540/541
1
FW(SOL20-P-300)
TRUTH TABLE
INPUTS
OUTPUTS
G1
G2
An
Yn*
H
X
X
X
H
X
Z
Z
L
L
H
H
L
L
L
L
L
H
x : Don't Care
Z
*
: High Impedance
: Yn······HC541A
Yn ...... HC540A
PIN ASSIGNMENT
TC74HC540A
TC74HC541A
G1 1
20 Vee
G1 1
20 Vee
A1 2
19- G2
A1 2
19 G2
A2 3
18 V1
A2 3
18 V1
A3 4
17 V2
A3 4
17 V2
A4 5
16 V3
A4 6
16 Y3
A5 6
15 V4
A5 6
15 Y4
AU 7
14 V5
A6 7
14 V6
A7 a
13 V6
A7 a
13 V6
Aa 9
12 V7
Aa 9
12 V7
GND 10
11 VB
GND 10
11 va
(TOP
VIEW)
HC-560
Yn*
Z
Z
TC74HC540AP I AF I AFW
TC74HC541AP I AF I AFW
IEC LOGIC SYMBOL
TC74HC540A
TC74HC541A
G1
G2
A1
A2
A3
A4
A5
A6
A7
AS
A1
A2
A3
A4
A5
A6
A7
AS
HC-561
8)
(12)
(9)
(11)
V1
V2
V3
V4
V5
V6
V7
VS
TC74HC540AP/AF/AFW _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC541API AF I AFW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
V[,\
VOLT
11K
10K
Ia.T
lee
PD
Tstg
TL
UNIT
V·
V
V
mA
mA
mA
mA
mW
"C
"C
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP) *1l80(MFP)
-65 -150
300
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
SYMBOL
Vee
VCIi
VOUT
Topr
tr , tr
UNIT
V
V
V
"C
ns
D.C ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
Vex.
3-State Output
Off -State Current
10l
Input Leakage Current
Quiescent Supply Current
I I:\:
Icc
TEST CONDITION
VI:>; =
VIHorVn.
VI:\: =
VIHorVIL
100 =-20p.A
IOH --6 mA
100 =-7.8mA
Ia. =20 p.A
lex. -6 mA
lex. =7.8mA
VI:\: -VIH or V IL
Vex.T =Vcc or GND
VI:\: -Vcc or GND
VI:\: -Vcc or GND
Vcc
2. 0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
HC-562
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3. 15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
6.0
5.9
5.9
4. 13
4.18
4.31
5.68
5.80
5.63
0.1
0.0
0.1
0.1
0.1
0.0
V
0.1
0.1
0.0
0.26
0.33
0.17
0.26
0.18
0.33
±0.5
±5.0
MIN.
1.5
3.15
4.2
-
-
-
-
±0.1
4.0
-
±1.0
40.0
p.A
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC540AP/AF/AFW
TC74HC541APIAF I AFW
AC ELECTRICAL CHARACTERISTICS(lnput t r =t,=6ns}
TEST
Ta-25"C
Ta- 40 -85"C
PARAMETER
SYMBOL
UNIT
CONDITION CL
Vee MIN. TYP. MAX. MIN. MAX.
2.0
60
75
25
tTLH
Output Transition Time
4.5
12
50
7
15
t'niL
6.0
6
10
13
2.0
36
90
115
4.5
12
18
23
50
tpLH
6.0
20
10
15
Propagation Delay Time
130
2.0
51
165
17
26
33
150 4.5
tpHL
14
22
28
6.0
ns
45
125
155
2.0
25
31
50 4.5
14
tpZL.
12
21
26
6.0
Output Enable time
RL = 1 kQ
205
2.0
60
165
tpZl-j
150 4.5
19
33
41
28
6.0
l6
35
2.0
125
40
155
tpLZ
Output Disable time
R L= 1 kQ
4.5
16
25
31
50
tpHZ
6.0
26
14
21
Input Capacitance
10
CN
5
10
Output Capacitance
Coor
10
pF
32
TC74HC540A
Power Dissipation Capacitance C,u(l}
35
TC74HC541A
Note (1) CpD is defined as the. value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
I eetpl=C PD • Vee of!.' +Iee 18(per bit)
HC-563
TC74HCT540AP/AF/AF.W _ _ _ _,
TC74HCT541AP/AF/AFW
OCTAL BUS BUFFER WITH TTL INPUT LEVEL
TC74HCT640API AFI AFW INVERTING,3-STATE OUTPUTS
TC74HCT641API AFI AFW NON-INVERTING,3-STATE OUTPUTS
The TC74HCT540A/TC74HCT541A are high speed
CMOS OCTRAL BUS BUFFERS fabricated with silicon
gate C2MOS technology.
These devices may be used as a level converter for
interfacing TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL, NMOS and CMOS output
voltage levels.
They achieve the high speed operatjon similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HCT540A is anon-inverting type, and the TC
74HCT541A is an inverting type.
When either Gl or G2 are high, the terminal outputs are
in the high-impedance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd = lOns( typo )at Vcc=5V
• Low Power Dissipation ............ Icc=4.ttA(Max.)at Ta=25"C
• Compatible with TTL outputs ...... VIL=O.8V(Max.),VUF2.0V(Min.)
• Wide Interfacing ability ........ · LSTTL,NMOS,CMOS
• Output Drive Capability ............ 15 LSTTL Loads
• Symmetrical Output Impedance'" I IOH I =IOL=6mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Pin and Function Compatible with 74LS540/541
P(DIP20-P-300A)
F(SOP20-:P-300)
FW(SOL20-P-300)
TRUTH TABLE
INPUTS
x
Z
*
OUTPUTS
G1
G2
An
Vn*
H
X
X
X
H
X
Z
Z
L
L
H
H
L
L
L
L
L
H
: Don't Care
: High Impedance
: Vn ...... HCT541A
yn .... ··HCT540A
PIN ASSIGNMENT
TC74 HCT640A
TC74HCT641A
G1 1
20 Vee
'G1 1
20 Vee
A1 2
19 '02
A1 2
19 G2
A2 3
18 Y1
A2 3
18 V1
A3 4
17 Y2
A3 4
17 V2
A4 5
16 Y3
A4 5
16 V3
A5 6
1S Y4
A5 6
15 Y4
A6 7
14 YS
A6 7
14 VS
A7 8
13 V6
A7 8
13 Y6
A8 9
12 V7
A8 9
12 V7
GND 10
11 Y8
GND 10
11 V8
(TOP
VIEW)
HC-564
Vn*
Z
Z
TC74HCT540AP/AF/AFW
TC74HCT541 AP/AF/AFW
IEC LOGIC SYMBOL
TC74HCT540A
TC74HCT541A
A1
A2
A1
A2
A3
A4
A3
AS
AI
AS
AI
A4
A7
A7
AI
AI
HC-565
VS
VI
V7
VI
TC74HCT540AP/AF/AFW _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HCT541AP/AF/AFW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vex/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vex
VI"
VOL".
11K
Ia<
IOli
lex
PD
Tstg
TL
UNIT
V'
VALUE
-0.5 -7
-0.5 -Vex +0.5
-0.5 -Vex+0.5
±20
±20
±35
±75
500(DIP)*/180(SOIC)
-65 -150
300
V
V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-40·C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Ternperrature
Input Rise and Fall Time
SYMBOL
VALUE
Vex
5.5
0- Vex
0- Vex
-40 - 85
0-500
VI'"
VCX;i
Topr
tr • tr
UNIT
V
V
V
4.5 -
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High Level
Output Voltage
Low-Level
Output Voltage
3-State Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
TEST CONDITION
MIN.
l
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
-
V
0.1
0.33
V
5.5
4.5
V(H
VOL
Ice;
Ie\
lex
t:..1cc
l
VI1\:IOH - 20tl A
VIHorVIL IOH --6 rnA
VI,,IOl -20 tl A
VIHorVIL IOl -6 rnA
VIN-VIH or VII.
VIN=Vex or GND
VI:\ - Vex or G ND
VIN-Vexor GND
Per input: VI:'; -0. 5V or 2.4V
Other input:Vexor GND
Ta<=25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MiN. MAX.
Vex
4.5
5.5
4.5
4.5
4.5
4.5
5.5
4.4
4.18
-
5.5
5.5
5.5
HC-566
-
4.5
4.31
0.0
0.17
0.1
0.26
-
±0.5
-
±0.1
4.0
-
2.0
-
4.4
4.13
-
±5.0
A
±LO
40.0
tl
2.9
rnA
TC74 HCT 540AP/AF/AFW
TC74HCT541 AP/AF/AFW
AC ELECTRICAL CHARACTERISTICS(lnput t r =t,=6ns)
TEIST
Ta-25"C
Ta- 40 -85"C
UNIT
PARAMETER
SYMBOL
CONDITION CL
Vee MIN. TYP. MAX. MIN. MAX.
Output Transition Time
tTlJI
tTHL
50
4.5
5.5
-
7
6
12
11
-
15
14
tpLH
50
4.5
5.5
-
12
9
20
18
-
25
23
tpHL
150
4.5
5.5
-
17
14
26
24
tpLH
50
4.5
5.5
-
14
11
23
21
tpHL
150
4.5
5.5
-
19
16
29
27
tpZL
50
4.5
5.5
18
16
30
27
150
4.5
5.5
-
23
21
36
33
50
4.5
5.5
-
18
16
30
27
Propagation Delay Time
TC74HCT54OA
Propagation Delay Time
TC74HCT541A
Output Enable time
-
-
Output Disable time
tpLZ
t plJZ
Input Capacitance
Output Capacitance
CI;\
COLT
RL= 1 kQ
-
-
-
-
33
30
29
27
ns
R L = 1 kQ
tpZl-l
-
-
-
-
-
-
36
33
38
35
45
41
38
35
10
10
5
10
pF
TC74HCT540A
35
Power Dissipation Capacitance Cm(l)
TC74HCT541A
31
Note (1) CPD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
I CCtvO=C PD ° Voc o f[\ +Ioc /B(per bit)
-
He-567
TC74HC563AP/AF
TC74HC573AP/AF/AFW
OCTAL D-TVPE LATCH WITH 3-STATE OUTPUT
TC74HC&63AP/AF
INVERTING
TC74HC573AP/AF/AFW
NON-INVERTING
The TC74HC563A and TC74HC573A are high speed
CMOS OCTAL LATCH with 3-ST ATE OUTPUT
fabricated with silicon gate C2MOS technology.
They achieve the high speed operation similar ~
equivalent LSTTL while maintaining the CMOS low power
dissipation.
These 8-bit D-type latches are controlled by a latch
enable input (LE) and a output enable input(OE).
When the TIE input is high. the eight outputs are in a
high impedance state.
The TC74HC563A has inverting outputs. and
TC74HC573A has non-inverting outputs.
All inputs are equipped with protection circuits against
static dischage or transient excess voltage.
FEATURES:
• High Speed .............................. tpd =13ns(Typ.)at Va;=5V
• Low Power Dissipation .....•..•.•• Ia;=4IlA(Max.)at Ta=25"C
• High Noise Immunity··············· VlIIIH=VNII.2876 Va; (Min.)
• Output Drive Capability······ .•••.• 15 LSTTL Loads
• Symmetrical Output Impedance ... I IOH I =IOL =6mA(Min.)
• Balanced Propagation Delays ..••.• tplH '" tpHl.
• Wide Operating Voltage Range ... Va; (opr . ) =2V -6V
• Pin and Function Compatible with 74LS563/573
P(0IP20-P-300A)
20~ 20~
1
F(SOP20-P-300)
1
FW(SOL20-P-300)
PIN ASSIGNMENT
TC74HC563A
OE
20 Vee
DO 2
01
19 00
18 01
3
02 4
03 5
04 6
17 02
16 03
15 04
14 05
13 06
05 7
06 8
07 9
12 07
GNO 10
11
LE
TRUTH TABLE
TC74H'C673A
OE
INPUTS
OUTPUTS
DO
20 Vee
2
19 00
18 01
17 Q2
OE
LE
D
H
X
L
L
X
X
Z
Qn
Z
Qn
01 3
02 4
03 5
16
03
L
H
L
L
H
04
15
04
L
05 7
06 8
07 9
14
13
05
06
12
07
GND10
11
LE
L
H
H
O(HC573A O(HCI3A)
H
x . Don't Care
Z : High Imp.dance
0n(U;;) : Q(ll) Ol,ltputs are la.tched {It the
tim. wh.n the LE Input IS tak.n
to a low logic l.v.1.
He-568
TC74HC563AP/AF
- - - - - - - - - - - - - - TC74HC573AP/AF/AFW
IEC LOGIC SYMBOL
TC74HC573A
TC74HC563A
OE
LE
OE
LE
Qo
01
02
DO
01
02
03
D4
OS
D6
07
DO
QO
01
02
03
D4
OS
D6
07
01
02
03
Q4
05
as
07
SYSTEM DIAGRAM
TC74HC563A
DO
01
02
03
D4
05
D6
07
LE-1)
OE
Co
01
02
03
04
Os
06
07
TC74HC573A
DO
01
02
03
D4
02
03
OS
D6
07
LE-1)
00
01
HC-569
Q4
05
Q6
07
TC74HC563AP/AF
TC74HC573API AFI AFW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
Vee
VI~
VOLT
11K
I(l(
IOLT
lee
Po
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5-7
-0.5 -Vee+0.5
-0.5 -Vee+0.5·
±20
±20
±35
±75
SYMBOL
500(DIP)~/180(MFP)
-65 -150
300
*500m W in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
o -Vee
o -Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
0- 400(Vee=6.0V)
SYMBOL
Vee
VI~
VOLT
Topr
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
High-Level
Input Voltage
SYMBOL
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vm
Low-Level
Output Voltage
VOL
3-State Output
orC-State Current
.Input Leakage Current
Quiescent Supply Current
TEST CONDITION
I~
11:\
lee
VI:\=
VUiorVIl•
VI:\=
VIHorVIL
1m =-20,u A
1m - 6 mA
1m =-7.8mA
IOL =20 ,u A
IOL -6 rnA
IOL =7.8mA
V I:\ -VIH or VII.
VOLT =Vee or GND
VI:\ -Vee or GNU
VI:\ -Vee or GND
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.5
4.4
4.4
V
6.0
5.9
5.9
4.18
4.31
4.13
5.80
5.63
5.68
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.1
0.0
0.17
0.33
0.26
0.33
0.26
0.18
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
MIN.
1.5
3.15
4.2
6.0
-
6.0
6,0
HC-570
-
-
~
-
±0.5
±0.1
4.0
-
±5.0
-
±1.0
40.0
,uA
TC74HC563AP/AF
TC74HC573AP/AF/AFW
TIMING REQUIREMENTS{lnput t r =t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(LE)
tW(H)
Minimum Set-up Time
(Data)
ts
Minimum Hold Time
(Data)
th
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C
TYP.
LIMIT
75
15
13
50
10
9
5
5
5
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
65
ns
13
11
5
5
5
AC ELECTRICAL CHARACTERISTICS(lnput t r =t,=6ns)
TE:;T
Ta-25"C
Ta- 40 -85"C
PARAMETER
UNIT
SYMBOL
CONDITION CL Va; MIN. TYP. MAX. MIN. MAX.
2.0
20
60
75
tTLH
Output Transition Time
4.5
50
12
15
6
tTHL
6.0
13
10
5
2.0
50
115
145
4.5
50
23
29
tpLH
15
Propagation Delay Time
6.0
20
25
13
2.0
60
155
195
(LE-Q. Q)
150 4.5
tpHL
20
39
31
6.0
17
26
33
2.0
42
110
140
4.5
50
14
28.
22
tpLH
Propagation Delay Time
6.0
12
24
19
ns
2.0
57
150
190
(D-Q. Q)
150 4.5
19
tpHL
30
38
6.0
16
26
32
2.0
140
175
55
50 4.5
tpZL
17
28
35
6.0
24
14
30
RL = 1 kQ
Output Enable time
2.0
66
180
225
150 4.5
tpZH
22
36
45
6.0
19
31
38
2.0
125
155
40
tpLZ
Output Disable time
RI. = 1 kQ
4.5
50
25
31
17
tpHZ
6.0
21
26
15
Input Capacitance
Cr,
5
10
10
Output Capacitance
COLT
10
pF
Power Dissipation
TC74HC563A
49
C PD(l)
Capacitance
TC74HC573A
51
Note (1) Cm IS defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iccwo=C m • Va;. f[\ +Ia; /8(per Latch)
And the total C m when n pes. of Latch operate can be gained by the following equation:
Cm(total)=33+16. n (TC74HC563A)
Cm(total)=33+18. n (TC74HC573A)
HC-571
TC74HCT563APIAF
TC74HCT573AP/AF/AFW----OCTAL D-TVPE LATCH WITH 3-STATE OUTPUT
TC74HCT&63AP/AF
INVERTING
TC74HCT673AP/AF/AFW NON-INVERTING
The TC74HCT563Aand TC74HCT573A are high speed
CMOS OCTAL LA TCH with 3-STATE OUTPUT
fabricated with silicon gate C2MOS technology.
They achieve the high speed operation similar to equivalent LS'fTL while maintaining the CMOS low power
dissipation.
Their inputs are compatible with TTL, NMOS, and
CMOS output voltage levels.
These 8-bit D-type latches are controlled ~a latch
enable input CLE) and an output enable input COE).
When the OE input is high, the eight outputs are in a
high impedance state.
The TC74HCT563A has inverting outputs, and the
TC74HCT573A has non-inverting outputs.
All inputs are equipped with protection circuits against
static dischage or transient excess voltage.
P(0IP20-P-300A)
2~ 20~
1
1
F(SOP20-P-300) FW(SOL20-P-300)
PIN ASSIGNMENT
FEATUilES:
• High Speed .............................. tpd =18ns(Typ.)at Vcc=6V
• Low Power Dissipation .....•...... Icc =4J.tA(Max.)at Ta=25"C
• Compatible with TTL outputs ••••••••••.• VIH =2.0V(Min.),
VIL =O.8V(Max.)
• Output Drive Capability'" '" .•.... 15 LSTTL Loads
• Symmetrical Output Impedance .. , I IOH I =IOL =6mA(Min.)
• Balanced Propagation Delays ...... tpLH '" tpHL
• Pin and Function Compatible with 74LS563/573
TC74HCT563A
Oe
TRUTH TABLE
Vee
00
01
02
03
04
05
06
07
LE
TC74HCT573A
OE
INPUTS
OE LE
OUTPUTS
0
H
X
X
L
L
L
H
X
L
L
H
H
Q(HCTmA) Q(HCT5I3A)
Z
Qn
Z
Qn
L
H
H
L
x . Don't Care
Z
20
19
18
17
16
15
14
13
12
11
DO 2
01 3
02 4
03 5
04 6
06 7
06 8
07 9
GND10
: High Impedance
oier;;) : Q(U)
Ol,ltput$ are la.tched lit
time when the LE Input IS
to a low logic level.
the
taken
HC-572
00
01
02
03
04
06
06
07
20 Vee
2
3
4
5
6
7
8
9
GND 10
19
18
17
16
15
14
13
12
11
00
01
02
03
04
05
06
07
LE
TC7 4HCT563AP I AF
TC74HCT573API AFI AFW
IEC LOGIC SYMBOL
TC74HCT673A
TC74HCT663A
OE
OE
LE
LE
DO
00
01
02
03
04
05
06
07
01
02
03
04
05
06
07
QO
Ql
Q2
Q3
Q4
as
Q6
Q7
SYSTEM DIAGRAM
TC74HCT 563A
00
01
02
03
04
05
06
07
00
01
02
03
04
05
06
07
Q2
Q3
TC74HCT573A
QO
Ql
HC-573
Q4
as
06
Q7
TC74HCT563AP/AF
TC74HCT573AP I AF I AFW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VII'I
Vour
11K
101(
lour
lee
Po
Tst&"
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5-7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP) */180(SOIC)
-65 -150
300
*500m W 'in the range of Ta=
-4Q'C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vee
Input Voltage
VIN
Output Voltage
Your
Operating Temperature
Topr
Input Rise and Fall Time
tr. tc
VALUE
4.5-5.5
O-Vee
O-Vee
-40-85
O-SOO
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Low-Level
Output Voltage
3-State Output
Ofr-State Current
Input Leakage Current
Quiescent Supply
Current
Va;
VOL
Iaz
liN
lee
Alee
TEST CONDITION
Ta=-40-85"C
Ta=25"C
UNIT
TYP.
MAX.
MIN. MAX.
MIN.
Vee
4.5
- 2.0
V
1 2.0
5.5
4.5
- 0.8 V
- 0.8
1
5.5
4.4
4.5
4.5 4.4
V
- 4.13 4.5 4.18 4.31
- 0.1 V
- 0.0 0.1
4.5
- 0.17 0.26
0.33
4.5
-
la;= -20uA
la;- -6 rnA
Ia. =20 u A
VIN =
VIH orVIL Ia. =6 rnA
VIN = VIH orVIL
5.5
VIN =Vee or GND
5~ 5
VIN =Vee or GND
5.5
Vll'~ =Vee or GND
Per input:V"" =0. 5V or 2. 4V 5.5
Other inpui:Veeor GND
VIN =
VIH orVIL
HC-S74
-
-
-
-
-
±5.0
±O.l
4.0
-
-
2.0
-
2.9
±0.5
±1.0
UA
40.0
rnA
TC74HCT563API AF
- - - - - - - - - - - - - - - TC74HCT573AP/AF/AFW
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Ta -40 -85"C
-,!,a-2~
Vr£
Minimum Pulse Width
(LE)
twan
4.5
5.5
Minimum Set-up Time
(Data)
t.
4.5
5.5
Minimum Hold Time
(Data)
th
4.5
5.5
TYP.
-
-
-
LIMiT
~
15
14
19
17
10
9
13
5
5
5
5
UNIT
ns
11
AC ELECTRICAL CHARACTERISTICS(lnput t r =t,=6ns)
PARAMETER
SYMBOL
Output Transition Time
t1Ul
tTHL
Propagation Delay Time
(LE-Q.Q)
Propagation Delay Time
(D-Q. Q)
bg~~ITION .(.;_~
vr£
MiN.
50
4.5
5.5
-
tpUi
50
4.5
5.5
tpHL
150
4.5
5.5
tpLH
50
4.5
5.5
tpHL
150
4.5
5.5
tp1l.
50
4.5
5.5
150
4.5
5.5
R L= 1 kQ
Output Enable time
tpZH
-
-
-
-
-
Ta=25"C
L'!'a -40 -85"C UNIT
TYP. MAX. MIN. MA~.
7
6
12
19
17
29
26
24
22
37
34
17
14
26
23
22
20
34
31
18
15
27
24
23
20
35
32
11
-
-
-
-
15
14
36
33
46
43
23
21
ns
43
39
34
30
44
40
24
30
18
22
28
16
Input Capacitance
L:IN
10
10
5
Output Capacitance
Ca.rr
10
pF
Power Dissipation
37
CpoU) TC74HCT563A
Capacitance
TC74HCT573A
38
Note(1) Cro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Jcctpl=Cro .Vo:::.fN +10::: 18(perLatch)
And the total Cro, when n pes. of Latch operate can be gained by the following equation:
Cro(totalj=25+12 • n (TC74HC563A)
Cro(total)=25+13. n (TC74HC573A)
Output Disable time
tpLZ
tpHZ
RL=lkQ
50
4.5
5.5
HC-575
-
-
TC74HC564AP I AF
TC74HC574API AF IAFW
OCTAL D-TVPE FLIP-FLOP WITH 3-STATE OUTPUT
TC74HC564AP/AF
INVERTING
TC74HC574AP/AF/AFW
NON-INVERTING
The TC74HC564A and HC574A are high speed CMOS
FLIP-FLOPs with
3--STATE
OUTPUTS
OCTAL
, fabricated with silicon gate C2MOS technology.
They achie1(e the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
These 8-bit D-type flip-flops are controlled by a clock
input (CK) and an output enable input (OE).
The TC74HC564Ahas inverting outputs, and the TC74
HC574A has non-inverting outputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed •.......••..•................. ~x=62MHz(Typ.)at Vee=5V
• Low Power Dissipation ............ l ee =4.uA(Max.)at Ta=25"C
• Hig;h Noise Immunity··············· VNIH=V:'<:IL28% Vee (Min.)
• Output Drive Capability······ ...... 15 LSTTL Loads
• Symmetrical Output Impedance "'1100 I =IOL =6mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range .. , Vee (opr)=2V-6V
• Pin and Function Compatible with 74LS564/574
P(DIP20-P-300A)
,.~,.~
1
F(SOP20-P-300)
1
FW(SOL20-P-300)
PIN ASSIGNMENT
TC74HC564A
OE 1
20 Vee
DO
19 00
18 01
2
01 3
02 4
03 5
17 02
16 03
15 04
04 6
05 7
06 8
14 05
13 06
07
12 07
9
GND10
TRUTH TABLE
11
CK
TC74HC674A
INPUTS
OE CK
D
'H
X
X
Z
Z
L
L
X
an
an
L
S
S
L
L
H
H
H
L
L
OE
OUTPUTS
DO 2
01 3
02 4
03 5
Q(574A) Q(564A)
x : Don't Care
Z
: High Impedance
On(On) : No Change
17
02
16
03
04 6
05 7
06 8
15
04
14
05
06
07
12
11
9
GNO 10
HC-576
20 Vee
19 00
18 01
13
07
CK
TC74HC564AP/AF
- - - - - - - - - - - - - - TC74HC574AP/AF/AFW
IEC LOGIC SYMBOL
TC74HC574A
TC74HC564A
DE
CK
ao
00
01
02
03
D4
05
06
07
03
04
05
Ci6
00
01
02
03
D4
co
05
as
06
07
Q7
Ql
Q2
Q3
Q4
Q6
SYSTEM DIAGRAM
TC74HC564A
00
01
02
03
04
05
06
07
TC74HC574A
00
01
02
03
He-577
04
05
06
07
TC74 HC564APlAF
TC74HC574APIAFlAFW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
YIX
YOLT
11K
10K
Icx,T
Ia::
Po
Tstg
TL
UNIT
V
Y
Y
mA
mA
mA
mA
mW
"C
"C
VALUE
-0.5-7
-0.5 -Yee+0.5
-0.5 "';'Yee+0.5·
±20
±20
±25
±50
500(DIP)*/180(MFP)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-IOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Input Rise and Fall Time
tr, tr
UNIT
V
V
V
"C
VALUE
2-6
0- Va::
0- Va::
-40 - 85
o- 1000(Ya::=2.0Y)
0- 500(Va::=4.5V)
0- 400(Va::=6.0Y)
Va::
VI'"
Your
Topr
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
YIH
Low-Level
Input Voltage
V1L
High-Level
Output Voltage
TEST CONDITION
1m =-20p.A
Yoo
Low-Level
Output Voltage
Vex.
3-State Output
orr-State Current
Input Leakage Current
lIE
Quiescent Supply CarreJlt
Ia::
ICI:
YIX=
YIHorYIL
100 =-6 mA
100 =-7.8mA
YIX=
YIHorVIL
lex. =20 p.A
lex. -6 mA
lex. =7.8mA
VI~ -VIH or YIL
Ya.T =Yee or GND
VIX -'Va:: or GND
V[,\ -'Vee or GND
Va::
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4~ 5
6.0
Ta- 40 -85"(
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
",4.4
4.5
4.4
Y
5.9
6.0
5.9
4.18
4.31
4.13
5.68
5.80
5.63
0.1
0.0
0.1
0.1
0.1
0.0
V
0.1
0.1
0.0
0.33
0.26
0.17
0.33
0.26
0.18
MIN.
1.5
3.15
4.2
6.0
6.0
-
HC-578
-
-
-
-
-
-
-
-
±0.5
-
±5.0
±0.1
4.0
-
+1.0
40.0
p.A
TC74HC564APIAF
- - - - - - - - - - - - - - TC74HC574AP/AF/AFW
TIMING REQUIREMENTS(lnput tr=t,=8nl)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CK)
tW:
lcr;
~Icc
4.5
1
5.5
VINICli =-20UA 4.5
VIHorVIL I(li --6 mA 4.5
Vl"l
IOL -2Q u.A 4.5
VIHorVIL IOL =6 mA 4.5
VIN =VIH or VIL
5.5
Your =Vcr; or GND
VI'" =vcr; or liND
5.5
VIN =Vcr; or liND
S;5
PER INPGT: VIN=O. 5V o~V 5.5
OTHER INPUT: Vcr; or G
HC-582
-
-
-
o1
o 26
±0.5
+0 1
40
2.0
-
-
-
o1
o 33
V
I./. A
±1.0
40 0
UA
2.9
mA
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HCT564AP/AF
TC74HCT574AP/AF
TIMING REQUIREMENTS(lnput tr=t,='nl)
PARAMETER
SYMBOL TEST CONDITION
Vcr.
Ta=25"C
LIMIT
TYP.
-
Ta- 40 -85"C
UNIT
LIM!T
Minimum Pulse Width
(CK)
tW(H)
tW(L)
4.5
5.5
-
15
14
19
17
Minimum Set-up Time
(Dn)
t.
4.5
5.5
-
15
14
17
Minimum Hold Time
(Dn)
th
4.5
5.5
-
0
0
0
0
Clock Frequency
f
4.5
5.5
31
34
25
27
-
19
ns
MHz
AC ELECTRICAL CHARACTERISTICS(lnput t r =t,=6ns)
PARAMETER
Output Transition Time
Propagation Delay Time
(CK-Q. Q)
Output Enable time
SYMBOL
~~~1ITION
tTLH
t11iL
Vcc
50
4.5
5.5
50
4.5
5.5
150
4.5
5.5
50
4.5
5.5
-
150
4.5
5.5
50
4.5
5.5
-
50
4.5
5.5
tpUi
tpHL
tpZL
tlflH
Output Disable time
tp12
tpHZ
Maximum Clock
Frequency
f:-lAX
Input Capacitance
Output Capacitance
C(!\
COLi
R L = 1 kQ
R L = 1 kQ
MIN.
CL
-
Ta-25"'(
'l'a--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
-
7
6
12
19
16
30
27
24
21
40
35
19
16
30
27
24
21
40
35
-
-
19
16
30
27
-
38
34
-
50
60
31
34
--
25
27
-
-
-
-
-
-
11
-
-
-
-
15
14
38
34
48
44
38
34
ns
48
44
5
10
10
10
pF
TC74HCT564A
65
Power Dissipation Capacitance Cro(1)
TC74HCT574A
62
Note (1) CPD IS defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCWrl =C PD • Va::. ff.'( +Ia:: /8(per bit)
And the total CPD when n pes. of Flip Flop operate can be gained by the following equation:
CPD(total)=51+14· n(TC74HCT564A)
CPD(total)=47+15. n(TC74HCT574A)
-
-
HC-583
-
NOTES
NOTES
TC74HC590AP I AF - - - - - a-BINARY COUNTER/REGISTER WITH 3-STATE OUTPUTS
~-----------------------.
The TC74HC590A is a high speed CMOS 8-BIT COUNTER/
REGISTER fabricated with silicon gate CZMOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal counter counts on the positive going edge of
Counter Clock (CCK) when Counter Clock Enable
(CCKEN) is low. When Counter Clear (CCLR) is low. the
internal counter is cleared asynchronously to the clock.
Data in the internal counter are loaded into the register
at positive going edge of Register Clock (RCK). and the
register outputs are countrolled by enable input (0) .
All inputs .are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. f~=62MHz(Typ.)at Voc=5V
• Low Power Dissipation ............... Ioc=4IlA(Max.)at Ta=2S'C
• High Noise Immunity·················· Vl\lH=V1\lL=28" Voc(~lin.)
• Output Drive Capability'" ....... ,.... 15 LSTTL Loads For QA-QH
10 LSTTL Loads For RCO
• Symmetrical Output Impedance ······1 Ia; 1=IQL=6mA(Min.)
ForQA-QH
1Ja; 1 =IQL=4mA(Min.)
For RCO
• Balanced Propaation Delays······ .•. tpLH" tpHL
• Wide Operating Voltage Range ...... Vcc (opr)=2V-6V
• Pin. and Function Compatible with 74LS590
1
P(DI P16-P-300A)
16~
1
F(SOP16-P-300)
PIN ASSIGNMENT
Qs
1
Qc
2
15 QA
QD
3
14
QE
4
13 RCK
12 CCKEN
16 Vcc
G
QF
6
Qo
8
11 CCK
QH
7
10 CCLR
GND 8
RCO
(TOP VIEW)
TRUTH TABLE
INPUT
FUNCTION
G
RCK
CCLR CCKEN CCK
H
X
X
X
X
Q OUTPUTS DISABLE
X
L
X
X
X
Q OUTPUTS ENABLE
X
X
X
X
COUNTER DATA IS STORED INTO REGISTER.
l'
X
X
X
X
REGISTER STATE IS NOT CHANGED.
1X
X
L
X
X
COUNTER CLEAR
X
X
H
L
l' ADVANCE ONE COUNT.
X
X
H
L
1- NO COUNT
X
X
H
H
X
NO COUNT
X:Don't care
RCO-~Q~A~·.-Q~B~·~·~Q~C~·.-.Q~D~·.~Q~E~·-.~Q=F~~.~Q~G~'-'~Q~H'
(QA'-QH':lnternal outputs of the counter)
HC-586
________________________________ TC74HC590AP/AF
TIMING
CHART
255
3
0
CCK
RCK
CCiJi
CcKEN
G
OA
LJ
OB
OC
00
OE
OF
OG
OH
RCO
L-J
•
I
COUNTER CLEAR
COUNT
IEC
LOGIC
INHIBIT
SYMBOL
CTRS
(CT=255)Z4
He-58?
!HlGH
, IMPEDANCE
COUNT
TC74HC590AP I AF
LOGIC DIAGRAM
C~~
~CCK
RCK
--.0::=
CCKEN
CCK
CCK
+B
TA
+B
TB
TC
+C
TO
+C
TE
+D
TF
+0
TG
TH
+E
+E
+F
+F
+G
+G
4>H
+H
HC-588
TC74HC590AP I AF
BLOCK
DIAGRAM
CCK _ _1:.:.1-1
CCLR _ _I:.:.0:
lex;
Ire =-20p. A
- 4 mA
=-5.2mA
--6 mA
=-7.8mA
1ex.=20 p.A
Iex.-4 mA
lex. =5. 2mA
lex. =6 mA
QA-QH 1(1=7 SmA
IX =VIH or VIL
Vex.T =Vex; or GND
VI:>: =Vex; or UND
VI:>: -'Vex; or UND
RCO
Ta=25"C
Yfr. _MIN.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
4.5
6,0
2.0
4.5
6.0
4.5
6.0
4.5
60
6.0
6.0
HC-590
-
1.5
3.15
4.2
1.9
4.4
5.9
4.18
5.68
4.18
5.68
--
-
TYP.
--
2.0
4.5
6.0
4.31
5.80
4.31
5.80
0.0
0.0
0.0
0.17
0.18
0.17
o 18
-
MAX.
--
0.5
1. 35
1.8
--
-
0.1
0.1
0.1
0.26
0.26
0.26
o 26
±0.5
±0.1
4.0
'1'a--40 -85"C
UNIT
MiN. MAX.
1.5
V
3.15
4.2
0.5
V
1. 35
1.8
1.9
4.4
5.9
V
4.13
5.63
4.31
5,63
0.1
0.1
0.1
V
0.33
0.33
0.33
o 33
±5.0
p.A
±1.0
40.0
-
-
--
-
-
--
- - - - - - - - - - - - - - - TC74HC590API AF
TIMING REQUIREMENTS(lnput t r =tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CCK,RCK)
tWO-I)
t\\'(L)
Minimum Pulse Width
(CCLR)
tW(L)
Minimum Set-up Time
(CCKEN-CCK)
ts
Minimum Set-up Time
(CCK-RCK)
ts
Minimum Hold Time
tit
Minimum Removal Time
(CCLR)
Clock Frequency
trem
f
Vc£
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
HC-591
Ta 25"C
TYP.
LIMIT
75
15
13
75
15
13
100
20
17
200
40
34
0
0
0
75
15
13
6
33
39
-
--'!'a -40 -85"C UNIT
LIMIT
95
19
16
95
19
16
125
25
21
ns
250
50
43
0
0
0
95
19
16
5
MHz
26
31
TC74HC590AP I AF
AC ELECTRICAL CHARACTERISTICS(C L =15pF,Vcc=6V,Ta=26"C)
PARAMETER
SYMBOL
Output Transition Time
(RCO)
Propagation na~b Time
(CCK)
Propl,lgation De~y Time
(CCK-R 0)
.Maximum Clock Frequency
tru-J
tTHL
tpLH
tPHL
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
18
28
tpL/-1
-
20
30
f MAX
32
62
-
UNIT
ns
IMHz
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =t,=6ns)
TEST
CONDITION CL
PARAMETER
SYMBOL
Output Transition Time
(Qn)
tTU-J
tTHL
50
Output Transition Time
(RCO)
tTl..H
tTHL
50
Propagation Delay Time
(CCK-RCO)
tpLH
tpHL
50
Propagation Delay Time
(CCLR-RCO)
tpLH
50
Propagation Delay Time
(RCK-Qn)
tpLH
tpHL
50
150
50
Output Enable time
tpZL
tpZH
R L= 1 kQ
150
Output Disable time
tpLZ
tpHZ
Maximum Ciock Frequency
fMAX
R L = 1 kQ
50
50
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6 0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
MIN.
-
-
-
6
30
35
Ta--40 -85"(
Ta-25"C
UNIT
TYt'. MAX. MIN. MAx.
60
75
25
12
15
7
10
13
6
75
30
95
15
8
19
7
13
16
75
163
205
22
33
41
28
17
35
220
78
175
44
23
35
30
37
18
180
62
145
ns
29
36
19
25
31
15
230
78
185
37
46
24
19
31
39
43
105
130
26
14
21
22
12
18
190
58
150
38
19
30
16
26
33
33
105
130
21
26
16
12
22
18
5
12
- MHz
24
51
28
80
5
10
10
pF
-
-
-
Input Capacitance
CN
Power Dissipation Capacitance
Note (1) C I'D is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
1a;{W=C ro • Va;' f['( +la;
cpom
HC-592
TC74HC592P
TC74HC592P
8-BIT BINARY COUNTER WITH INPUT REGISTER
The TC74HC592 is a high speed CMOS 8-bit register/counter fabricated with silicon
gate C2MOS technology.
It achieve the high speed operation similar to equivalent LSTTL while maintaining the
CMOS low power dissipation.
The internal counter counts at positive edge of Counter Clock (CCK) when Counter Clock
Enable (CCKEN) is held "L" level.
If Counter clear (CCLR) is held "L", the internal counter is cleared asynchronous to
clock.
Input A'\, H are loaded to register at positive edge of Register Clock (RCK), and
register outputs are loaded to Counter when Counter Load (CLOAD) is held "L" level.
All inputs are equipped with protection circuits against static discharge or transient
excess voltage.
FEATURES
• High Speed ••••••••••••••• f MAX=38MHz(Typ.) at VCC=5V
r-------------------------~
Low Power Dissipation •••.•• ICC=4~A(Max.) at Ta=25°C
• High Noise Immunity ......... VNIH=VNIL=28% VCC(Min.)
Output Drive Capability .•...........• 10 LSTTL Loads
Symmetrical Output Impedance •••• I IOHI=IOL=4rnA(Min.)
Balanced Propagation Delays •••••••••••••••
tpLH~tpHL
Wide Operating Voltage Range ••••••• VCC(Opr.)=2V'\,6V
Pin and Function Compatible with LSTTL(74LS592)
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
-----DC Output Voltage
Input Diode Current
Output Diode Current
f------------
DC Output Current
DC Vcc/Ground Current
~------------Power Dissipation
DIP16(3Dl6A-P)
SYMBOL
VCC
VIN
VOUT
11K
10K
lOUT
ICC
PD
VALUE
-0.5 '\, 7
UNIT
V
-0 . 5 '\, VCc+O . 5
V
-0 . 5 '\, VCC+O .. 5
±20
±20
V
mA
rnA
,~
Tstg
TL
B
1
16
VOO
o
2
15
A
D
3
14
OLOAD
±25
rnA
±50
mA
E
4
13
ROK
mW
F
5
12
OOKEN
G
6
11
OOK
H
7
10
OOLR
GND
8
9
ROO
500 1'
f - - - - - - - - - - - - ---
Storage Temperature
Lead Temperature 10sec
PIN ASSIGNMENT
-65 '\, 150
300
°c
°c
500mW in the range of Ta=-40°C'\,65°C and from Ta=65°C
up to 85°C derating factor of -lOmW/oC shall -be applied
unt i 1 300mW.
HC-593
(TOP VIEW)
TC74HC592P----------------------------------
TRUTH TABLE
INPUTS
ROK
o LOAD
OOLR
OOKEN
FUNOTION
OOK
X
L
H
X
X
REG I STER DATA IS LOADED INTO OOUJITBll..
X
H
L
X
X
J
H
H
X
X
OOUNTER CLEAR
;;~T~~~~ OF A THRU H INPUTS IS STORllD INTO
REGISTER STATE IS NOT OHANGED.
L-
H
H
X
X
X
H
H
L
X
H
H
L
S
L
NO OOUNT
X
H
H
H
X
NO COUNT
OOUNTER ADVANOES THE COUNT.
X: Don't care
RCO=QA' • QB' • QC' • QD' • QE' • QF' • QG' • QH'
(QA' '" QH'; Internal outputs of the counter)
BLOCK DIAGRAM
IMPUTS
ABODEJ'GH
ROK---oIOil-l
a-BIT REGISTER
O O K - - - - -....
'CO'LR __.:lD=d
0'CiKEN
---"=it:!
CLoiD _ _...:1:,::4Cj
a-BIT BINARY
OOUNTER
9
HC-594
TC74HC592P
LOGIC DIAGRAM
A
D
ROIt U - - - - . . J OK
TA
OOK
ocK'
OOK'
B lJ"----'--'
TB
TA
_B
TB
0
D
CK
SAME AS
II
TO
I
r/lc
TO
1...--
TD
_0
SAME AS ABOVE
D
t/JD
r-I
E
D
_I!:
r/lE
Cit
r-I
I
P
D
Cit
SAME AS
I
L __
I
TP
_P
r/lF
....I -I
0
D
CK
I
I
I
IL __
_0
r-I
I
H
D
CK
_H
r/lE
HC-595
0
G>
:r:
::z:
CCK
RCK
n
--D~
__________________________
-I
-I
......
:s:
......
:c
);>
;;0
-I
~
~
0
(J1
(0
I\)
"0
A
B
C
D
E
:c
F
('")
U,
<0
0>
G
H
CCLR
CCKEN
CLOAD
RCO
252
RESISTER
STORE
253
DATA LOAD
TO COUNTER
254,
255
o
1
2
3
o
-1
COUNTER CLEAR
252
2531
253
COUNT HOLD
253
------------------------------------TC74HC592P
INPUT and OUTPUT
EQUIVALENT CIRCUIT
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
SYMBOL
Vee
V1N
Input Voltage
Output Voltage
VOUT
Operating Temperature
Topr
Input Rise and Fall Time
tr,tf
LIMIT
2 'V 6
o 'V
o 'V
UNIT
vee
Vee
Vee
,
V
-40.'V 85
O'VIOOO(Vce=2.0V)
o 'V 500 (Vce=4. 5V)
o 'V 400 (VCC=6. OV)
INP~
°e
ns
- --
'I"
GND
7~
:Ot~~
u'"tL
DC ELECTRICAL CHARACTERISTICS
PARAMETER
High-Level
Input Voltage
SYMBOL
TEST CONDITION
VIH
1-------LO\~-Level
Input Voltage
VIL
I OH =-20)JA
High-Level
Output Voltage
VOH
or Vn
Low-Level
Output Voltage
VIN=VIH
VIN=VIH
VOL
or VIL
_._-----
Input Leakage
Current
Quiescent
Supply Current
TOH =-4mA
I OH =-5.2mA
I OL =20)JA
IOL=4mA
I OL =5.2mA
lIN
VIN=Vee or GND
-- 1 - - - - _ . _ - - - ICC
r------
VCC
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta=25°C
Ta=-4O'V85°e
UNIT
MIN. TYP. MAX. MIN. MAX.
1.5
3.15
4.2
-
-
-
-
1.5
3.15
4.2
0.5
1.35
1.8
-
0.5
1.35
1.8
-
-
-
-
.-
-
2.0
4.5
6.0
-
-
1.9
4.4
5.9
4.5
1.9
4.4
5.9
4.18
4.31
-
4.13
6.0
5.68
-
5.63
2.0
4.5
6.0
-
5.80
0.0
0.0
0.0
0.1
0.1
0.1
-
0.1
0.1
0.1
4.5
0.17
0.26
0.18
0.26
-
±0.1
-
0.33
6.0
-
±1.0
6.0
-
-
4.0
-
40.0
6.0
-
-
-
0.33
~--~-.----.-
VIN=Vee or GND
He-59?
V
)JA
TC74HC592P--------------------------~--~~
AC ELECTRICAL CHARACTERISTICS (t r =tf=6ns • CL=50pF)
....-TEST
PARAMETER
Output Transition Time
SYMBOL
CONDITION
tTLH
tTHL
Propagation Delay Time
(CCK - RCO)
tpLH
tpHL
Propagation Delay Time
(CLOAD - RCO)
tpLH
tpHL
Propagation Delay Time
(CCLR - RCO)
tpLH
Propagation Delay Time
(RCK - RCO)
tpLH
tpHL
Maximum Clock Frequency
fMAX
Minimum Pulse Width
(CCK, RCK)
tw(H)
tw(L)
Minimum Pulse Width
(CCLR)
tw(L)
Minimum Pulse Width
(CLOAD)
tw(L)
Minimum Removal Time
(CCLR)
trem
Minimum Removal Time
(CLOAD)
t rem
Minimum Set-up Time
(CCKEN - CCK)
ts
Minimum Set-up Time
(RCK - CLOAD)
ts
Minimum Set-up Time
(A-v H - RCI<)
ts
CLOAD="L"
VCC MIN.
2.0
4.5
6.0
2.0
4.5
6.0
2'.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4
4.5
22
6.0
26
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
---
-
-
-
He-5gB
Ta=25°C
Ta=-4{)!\'85°C
UNIT
TYP. MAX. MIN. MAX.
30
75
95
15
8
19
16
13
7
116
225
- 280
45
29
56
25
38
48
164
315
395
ns
41
63
79
67
54
35
128
305
245
32
61
49
52
27
42
188
450
360
47
72
90
40
61
77
3.5
9
... MHz
34
18
42
21
40 100
125
10
20
25
9
17
21
108
210
265
27
42
53
23
36
45
128
250
315
32
50
63
43
27
54
5
5
5
5
5
5 ns
20
75
95
2
10
13
2
11
9
32
75
95
8
15
19
17
16
7
150
190
64
16
30
38
14
26
32
65
16
50
4
10
13
11
3
9
-
-
--
-
--
.-
-
-
-
-
-
-
-
-
-
-
--------------------------------~~C74HC592P
AC ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
SYMBOL
TEST
CONDITION
-VCC
MIN.
Minimum Hold Time
th
Input Capacitance
CIN
-
Power Dissipation
Capacitance
CPD(l
-
Note (1):
2.0
4.5
6.0
Ta=25°C
TYP.
--
Ta=;-4()<\.o85°C UNIT
MIN. MAX.
25
30
5
6
ns
5
5
10
10
pF
MAX.
-
5
-
44
-
-
CPD is defined as the value of internal equivalent capacitance of IC which
is calculated from the operating current consumption without load (refer to
Test Circuit). Average operating current can be obtained by the equation
hereunder.
ICC(Opr.) =CPD· VCC· fIN+ICC
SWITCHING CHARACTERISTICS TEST WAVEFORM
+-___________ aND
6ns
6ns
Vee
eLOAD
eeKEN
VOH
VOL
eeK
vee
6ns
6ns
OND
6ns
6ns
Vee
Vee
ReK
eeK
aND
aND
Vee
Jr"---..-t----vee
aND
aND
vOH
VOL
trem
Vee
eeK
aND
HC-599
6ns
6ns
TC74HC592P--------------------------------___
SWITCHING CHARACTERISTICS TEST WAVEFORM
ens
(Continued)
ens
ens
CCK,RCK
ens
VOO
A-H
GND
GND
t LH
VOH
9
ROO
ROK
5O'.fj
1
tTHL
VOL
GND
tw Cw twCU
Icc{Opr.) TEST CIRCUIT
A
H
P.G.
1-_ _--/
*
HC-600
----TC74HC595AP/AF/AFN
8-BIT SHIFT REGISTER/LATCH(3-STATE)
The TC74HC595A is a high speed 8- BIT SHIFT
REGISTER/LATCH fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HC595A contains an S-bit static shift register
which feeds an S':"bit storage register.
Shift operation is accomplished on the positive going
transition of the SCK input. The output register ·is loaded
with the contents of the shift register on the positive going
transition of the RCK input. Since RCK and SCK signal
are independent, parallel outputs can be held stable
during the shift operation. And, since the parallel outputs
are 3-state, it can be directly connected to S-bit bus. T~is
register can be used in serial-to-parallel conversion, data
receivers, etc.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. fMAX=55MHz(Typ.)at Va;=5V
• Low Power Dissipation ............... Ia;=4,t.tA(Max;)at Ta=25"C
• High Noise Immunity ............ ·.... · VNIH=Vi\1L=28" Va;(Min.)
• Output Drive Capability .............. · 15 LSTTL Loads For QA-QH
10 LSTTL Loads For QH'
• Symmetrical Output 'Impedance ...... 1100 1=Icx.=6mA(Min.)
ForQA....QH
1ht 1=Icx.=4mA(Min.)
ForQH'
• Balanced Propaation Delays ......... tpLH!oftpHL
• Wide Operating Voltage Range ...... Vcc(opr)=2V-6V
• Pin and Function Compatible with 74LS595
1
P(DIP16-P-300A)
1.~16~
F(SOP18-P-300)
FN(SOL 16-P-150)
PIN ASSIGNMENT
Qs
18 Vee
Qe
2
16 OA
OD
3
14 SI
Qe
4
13
QF
5
12 RCK
OG
6
11 SCK
QH
7
10 SCLR
OND 8
9
tr
Ow
(TOP VIEW)
TRUTH TABLE
SI
SCK
X
X
X
X
X
X
L
H
X
X
X
.r
.r
INPUTS
SCLR
X
X
RCK
G
H
L
L
X
X
X
H
X
X
H
X
X
X
X
X
X
1..
H
X
X
X
X
.r
1..
X
FUNCTION
QA thru QH outputs disable
QA thru QH outputs enable
Shift register is cleared.
First stage of S.R. becomes ML M. Other stages store the
data of previous stage. respectively.
First stage of S.R. becomes MHM. Other stages store the
data of previous stage. respectively.
State of S.R. is not changed .
S.R. data is stored into storage register.
Storage register state is not changed.
X : DON'T CARE
HC-601
TC74HC595AP/AF/AFN - - - -_ _ _ _ _ _ _ _ __
TIMING CHART
RCK---~
SClR
~-----QA
Qa
QC
Qo
Qe
____________________________
~r-l~
IEC LOGIC SYMBOL
~ OJ
RCK 02J
-niem------,
C2
SClR
SCK
81
201> 3v
051
111 0A
(21 QS
(31 0C
t---t----l_ .(41
00
151 0e
161 OF
20 I> 3V
HC-602
171 0 0
181 0H
QW
______________________
r-------------------------------------------------------------------~----------------__,10
~
o
~
m
~
o
~
Q
~
~
~
o
a
o
o
a
o a
a
o
o
a
a
o
o
Q
Q
z
C')
§
-t
o-...
.a:a.
:I:
oc.n
6
15
OA
OB
Oc
00
aE
OF
aG
QH
CD
c.n
»
"'tJ
.......
»
"'11
.......
»
"'11
Z
TC74HC595AP/AF/AFN - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
SYMBOL
VALUE
Vee
V I\
-0.5 - i
-0.5 -VecTO.5
-0.5 -\'ee+0.5
±20
±20
VoL'r
11K
10K
DC Output Current ( QII' )
(Q.\QII)
DC Vce/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
IOCT
Icc
~)
T stg
TI.
UNIT
V
V
V
rnA
rnA
±25
±35
:::!:::i5
500(DIP)'/180(:-'lFP)
-65 -150
300
*500m W in the range of Ta=
-40'C-65°C. From Ta=65'C
to 85'C a derating factor of
-10m \V I'C shall be applied
until300mW.
rnA
rnA
rnW
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
VALUE
2-6
Vee
VI\
UXIT
V
V
V
0- Vee
0- Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vec =.t·5V)
0- 400(\'ce=6.0\')
VOCT
Topr
tr • te
°C
ns
DC ELECTRICAL CHAR·ACTERISTICS
PARAMETER
SYMBOL
High- Le\'el
Input Voltage
VIII
Low-Level
Input Voltage
VII.
TEST CONDITION
VI\=
VlllOrVl1.
High - Le\'el
Output \'oltage
\'Cli
3-State Output
Off -State Current
Input Leakage Current
QuieSCfnl Suppl~' Current
VOl.
ICv.
11\
Icc
=-20/1. A
--4 rnA
ICII =-5.2mA
lUI =-6 rnA
Q.,-QII
101 =-i.8mA
~i
VI\=
VlllOrVl1.
Low-Level
Output Voltage
1m
,
1011
10 .=20 /1. A
lex. -4 rnA
Ic~. =5. 2mA
I(x.=6 rnA
IQ\-QIl I(x.=i.8mA
V 1\ -VIII or VII.
VOLT =Vcc orGND
. VI.\' -Vce or GXD
VI\ -\'l'c or GXD
i
Qlj
Vee
2.0
4.5
6.0
2.0
.t.5
6.0
2.0
4.5
6.0
4.5
6.0
4.5
6.0
2.0
-1.5
6.0
4.5
6.0
4.5
6.0
MIl'.
1.5
3. 15
.!.2
6.0
-
6.. 0
-
HC-604
-
1.9
4.4
5.9
4.18
5.68
4.18
5.68
-
-
-
Ta-25"C
Ta- 40 -85"C
l:XIT
TYP. MAX. MIN. l\-lAX.
1.5
V
3.15
.:I ?
0.5
0.5
\'
1. 35
1. 35
1.8
1.8
1.9
2.0
4.5
4. -1
5.9
6.0
V
4.13
4.31
5.80
5.63
4.31
4.31
5.80
5.63
0.1
0.0
0.1
0.0
0.1
0.1
0.1
0.0
0.1
V
O. Ii
0.33
0.26
0.33
0.26
O. 18
O. Ii
0.33
0.26
0.26
0.33
0.18
--
=0.5
-
±5.0
-
:::!:::1.0
40.0
_0.1
-
-
to
/1. A
I
i
- - - - - - - - - - - - - - TC74HC595AP/AF/AFN
TIMING REQUIREMENTS(lnput t r =tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(SCK,RCK)
tW(H)
Minimum Pulse Width
(SCLR)
tW(L)
Minimum Set-up Time
(SI-SCK)
ts
Minimum Set-up 'l'ime
(SCK-RCK)
ts
Minimum Set-up Time
(SCLR-RCK)
ts
Minimum Hold Time
%
Minimum Removal Time
(SCLR)
trem
Clock Frequency
f
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
He-60S
. Ta-25°C
TYP.
LIMIT
75
15
13
75
15
13
50
10
9
75
15
13
100
20
17
0
0
0
50
10
9
6
30
35
-
Ta--40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
165
13
11
95
19
16
125
25
21
0
0
0
65
13
ns
11
5
25
28
MHz
TC74HC595AP/AF/AFN - - - - - - - - - - - - - -
AC ELECTRICAL CHARACTERISTICS(CL =16pF.Vcc=6V.Ta=26"C)
TEST CONDITION
MIN.
TYP.
PARAMETER
SYMBOL
Output Transition Time
(QI·I')
Propagation Delay Time
(SCK-QIl')
Propag~ion Delay Time
(S LR-QIl')
Maximum Clock Frequency
MAX.
tTLH
tm!.
tpLH
tpHI.
tpLH
toll!.
-
4
8
-
12
21
-
15
30
f\lAX
35
77
UNIT
ns
MHz
AC ELECTRICAL CHARACTERISTICS(C L =60pF.lnput tr=t,=6ns)
TEST
Ta-25"C
Ta--40 -85"C
PARAMETER
SYMBOL
UNIT
CONDITION cL
Vee MIN. TYp. MAX. MiN. MAX.
2.0
60
75
25
Output Transition Time
tll.H
50
12
4.5
15
7
(Qn)
tm!.
6.0
10
13
6
2.0
30
75
95
Output Transition Time
t1l.H
4.5
50
8
15
19
(QH')
tmL
6.0
7
13
16
2.0
45
125
155
Propagation Delay Time
tpLH
50 4.5
25
15
31
(SCK-QH')
tpHL
6.0
13
21
26
2.0
60
175
220
Propagation Delay Time
tpLH
4.5
50
18
35
44
(SCLR-Qln
tpHI.
6.0
15
30
37
2.0
60
150
190
ns
50 4.5
20
30
38
Propagation Delay Time
6.0
17
26
32
tpll1
(RCK-Qn)
2.0
75
190
240
tpHL
150 4.5
25
38
48
22
32
6.0
41
2.0
45
135
170
50 4.5
27
15
34
6.0
tpZL
13
23
29
Output Enable time
RL = 1 kQ
2.0
tpZH
175
60
220
150 4.5
20
35
44
6.0
17
30
37
,
2.0
30
150
190
tpLZ
Output Disable time
R L= 1 kQ
4.5
50
15
30
38
tpI-JZ
6.0
14
26
33
2.0
6
17
5
- MHz
Maximum Cicek Frequency
fw,x
50 4.5
30
50
25
6.0
35
59
28
InDut CaDacitance
CI:\
5
10
10
pF
Power Dissipation Capacitance CPD(l)
184
Note (1) C R) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCq,~=C Il.l • V cc • fro; +ICC
-
-
He-606
-~----TC74HC597AP/AF
a-BIT LATCH/SHIFT REGISTER(3-STATE)
The TC74HC597A is a high speed CMOS 8-BIT
P ARALLEL-IN/SERIAL-IN SERIAL-OUT LATCHI
SHIFT REGISTER fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar . to
equivalent LSTTL while maintaining the CMOS low power .
dissipation.
It consists of an 8-bit data register feeding an 8-bit
shift register. The parallel data on the A-H 'inputs is
stored in the input register on the positive going transition
of RCK. When the SLOAD input is held low, the input
register data is passed into the shift registers. Whim
SLOAD input is held high, the serial data input (SI). is
enabled and the eight flip-flops perform serial shifting
the positive transition of SCK. A direct clear input (SCLR)
sets the 8-bit shift register to zero.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIPI6-P-300A)
16~
on
FEATURES:
• High Speed .............................. f\1AX=60~mz(Typ.)at Vee=5V
• Low Power Dissipation ............ Iee =4,t.tA(Max.)at Ta=25."C
• High Noise Immunity··············· V:\IH=V:\IL2896 Vee (Min.)
• Output Drive Capability'" ......... 10 LSTTL Loads
• Symmetrical Output Impedance ... I Iail =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH" tpHL
• Wide Operating Voltage Range ... Vee (opr)=2V-6V
• Pin and Function Compatible with 74LS597
F(50PI6-P-300)
PIN ASSIGNMENT
B
16 VCC
C
2
15 A
0
3
14 SI
E
4
13·SLOAD
F
5
12 RCK
G 6
11 SCK
H
10 SCLR
7
GND 8
(TOP
9
QH'
VIEW)
TRUTH TABLE
51
X
X
L
INPUTS
FUNCTION
5CK 5CLR SLOAD RCK
X
L
H
X
5. R. is cleared to -L"
H
X
L
X
Input register data is stored into S. R.
First stage of S. R. become -L". Other stages store the data of previous
H
H
X
S
stage, respectively.
H
S
H
H
X
X
X
1.
H
X
X
DON'T
H
X
X
X
S
1.
X
X
X
X
First stage of 5. R. become "H". Other stages store the data of previous
stage, respectively.
State of S. R. is not cha nged.
Input data on A-H line is stored into input register
Storage register state is not changed.
CARE
He-507
TC74HC597 API AF
TIMING CHART
SCK
SI
L
RCK
A
8
H
~.
C
h
I
L
H
I
D
I
H
E
h
F
G
N
OH'
L
I
H
n
L
U.
..,
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
I
I
H
~H
H
L
l..!:..JH1.!:. 'Ii
f-j:r
L
L'H
L
ilL
H
CLEAR
SERIAL
SERIAL SHIFT
SERIAL SHIFT
SHIFT
SHIFT
REGISTER
LOAD
PARALLEL LC>AD
LOAD
PARALLEL LOAD PARALLEL LOAD
INPUT REGISTER SHIFT REGISTER
INPUT REGISTER SHIFT REGISTER SHIFT REGISTER
IEC LOGIC SYMBOL
SCLR
(10)
R
SRG8
SCK
SLOAD
RCK
SI
A
B
C
D
E
F
G
H
OW
He-60B
H
L
L
SERIAL SHIFT
PARALLEL LOAD
INPUT REGISTER AND
SHIFT REGISTER
TC74HC597AP/AF
SYSTEM DIAGRAM
81
A
B
C
o
E
F
G
H
QH'
RCK
SL'ii'Ai) 13
ScUi
SCK
He-60g
TC74HC597AP/AF--------------------------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
I
Vee
V,\
VOLT
11K
10K
IOLT
Ice
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vce+0.5
-0.5 -Vq;+0.5
±20
±20
±25
±50
500(DIP) */180(FMP)
-65 -150
300
! UNIT
i
I
I
I
!
!
!
,
I
I
i,
V
V
V
rnA
rnA
rnA
rnA
mW
°C
OC
*500mW in the range of Ta=
-40·C- 65·C. From Ta=65·C
to 85·C a derating factor of
-10m Wrc shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
VALUE
2-6
0- Vee
0- Vc:e
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
0- 400(Vcc =6.0V)
SYMBOL
Vee
V,\
VOCT
Topr
tr, tr
Input Rise and Fall Time
! UNIT
I V
V
i
!
V
i
°C
I
I
I
ns
I
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMB0L
TEST CONDITION
,
High-Level
Input Voltage
V,,_,
Low-Level
Input Voltage
V'L
High-Level
Output Voltage
Va-!
Low-Level
Output Voltage
VOL.
Input Leakage Current
Quiescent Supply Current
1,\
Icc
V,\=
V'HorVn.
V,\=
I Vn1orV'L
I
,
Ia-! =-20 p. A
Ia-! - 4 rnA
101-' =-5.2mA
IOL. =20 p.A
101 . -4 rnA
101. =5.2mA
V,\ -Vee or GND
V,\ -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-610'
Ta--40 -85OC
Ta-25°C
UNIT
MIN.! TYP. MAX. MIN. MAX.
1.5 i
1.5
V
3.15
3.15 I 4.2 I 4.2
0.5
0.5
!
iI
V
1. 35
1. 35
1.8
1.8
! 1.9 ! 2.0
1.9
4.4
4.5
4.4
V
5.9
B.O
5.9
4.13
4.18 I 4.31
5.63
5.68 I 5.80
0.0
0.1
0.1
0.1
0.0
0.1
I
V
0.0
0.1
0.1
0.26
0.33
0.17
0.26
O. 18
0.33
I
±O.l
+1.0 p.A
4.0
40.0
! -
I
i
I
- - - - - - - - - - - - - - - - TC74HC597AP/AF
TIMING REQUIREMENTS(lnput t r =tf=6ns)
PARAMETER
SYMBOL TEST CO)l'DITIO)l'
Minimum Pulse Width
(SCK,RCK)
t\\"o I)
tW(I.)
Minimum Pulse Width
(SCLR)
two.)
Minimum Pulse Width
(SLOAD)
tW(L)
Minimum Set-up Time
(RCK-SLOAD)
ts
Minimum Set-up Time
(SI-SCK)
t6
Minimum Set-up Time
(PI-RCK)
t6
Minimum Hold Time
th
Min,imum Removal Time
(SCLR, SLOAD)
Clock Frequency
Vcr;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6 0
2.0
4.5
6.0
2.0
4.5
6.0
trem
f
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
95
19
16
125
25
21
ns
95
19
16
95
19
16
0
0
0
95
19
16
5
MHz
24
28
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
75
15
13
100
20
17
75
15
13
75
15
13
0
0
0
75
15
13
6
30
35
AC ELECTRICAL CHARACTERISTICS(CL =15pF,Vcc=5V,Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tn.H
t11-l1
tpLH
tpliL
tpLH
tDHL
tpLH
tDHL
tpLH
tDHL
Propagation JJelay Time
(SCK-QH')
Propagation Delay Time
(SCLR-QH')
Propagation Delay Time
(SLOAD-QH')
Propagation Delay Time
(RCK-QH')
Maximum 1,;1ock l"requency
TEST CONDITION
SLOAD ="L"
f~1AX
HC-611
MIN.
TYP.
MAX.
-
5
8
-
16
25
-
20
32
-
18
30
-
25
37
30
59
UNIT
ns
IMHz
TC74HC597AP/AF---------------------------------
AC ELECTRICAL CHARACTERISTICS(CL =50pF,lnput tr=t(=6ns)
Ta- 40 -85"C
Ta-25"C
U~IT
TYP. MAX. MIN. MAX.
32
95
2.0
75
t l1.H
Output Transition Time
19
4.5
8
15
ton-IL
7
13
16
6.0
2.0
78
145
180
Propagation Delay Time
tpLH
20
29
4.5
36
(SCK-QH')
tpHL
16
25
31
6.0
90
175
220
2.0
Propagation Delay Time
tpLH
ns
4.5 I 24
35
44
(SCLR-QH')
tpHL
20
30
37
6.0
I
80
175
220
2.0
Propagation Delay Time
tpLl-1
22
4.
5
35
44
(SLOAD-QH')
tpHL
18
30
37
6.0
112
210
265
2.0
Propagation Delay Time
tpLIl
SLOAD ="L"
42
4.5
30
53
(RCK-QH')
tpHL
24
45
6.0
36
12
2.0
6
5
Maximum Clock
MHz
f).t'\x
48
24
4.5
30
Frequency
35
50
28
6.0
Input Capacitance
5
Ce\
10
10
pF
Power Dissipation Capacitance
CPD(1)
60
- (11 CpD is defined as the value of the internal equivalent capacitance which is calculated from the
Note
operating current consumption without load.
Average operating current can be obtained by the equation:
lectpV=Cffi • Va:. fl\ +1("(;
PARAMETER
SYMBOL
TEST
CO~DITIO~
I
Vee
I MIN.
I
I
I
HC-612
TC74HC620API AF
- - - - - - T C 7 4 HC623API AF
OCTAL BUS TRANSCEIVER
TC74HC620API AF
3-STATE, INVERTING
TC74HC623AP/AF
3-STATE, NON-INVERTING
The TC74HC620A and TC74HC623A are high speed
CMOS QUAD TRANSCEIVERS fabricated with silicon
gate C2MOS technology.
They achieve. the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low
power dissipation.
These ICs are intended for two-way asynchronous
communication between data buses,and direction of data
transmission is determined by GAB,GBA.
GAB and GBA inputs are equipped with protection
circuits against static discharge or transient excess voltage.
20
1
P(DIP20-P-300A)
~~
FEATURES:
• High Speed ....................................... tpd=10ns(typ.)at Vee=5V
• Low Power Dissipation ..................
Iee=4tlA(~-lax.)at
1
F(SOP20-P-300)
Ta=25'C
• High Noise Immunity ...... ·.............. V:-,: II;=V:-':IL=28% Vee (~1in.)
• Output Drive Capability· ...... · .......... 15 LSTTL Loads
APPLICATION NOTES
1) Do not apply a signal to any
bus terminal when it is in the out
put mode. Damage may result.
2) All floating (high impedance)
bus terminals must have their
input levels fixed by means of pull
up or pull down resistors or bus
terminator IC's such as the
TOSHIBA TC40117BP.
• Symmetrical Output Impedance ...... I IOH I=IOl..,;,6mA(Min.)
• Balanced Propagation Delays ......... tpl.H '" lpIiL
• Wide Operating Voltage Range ......... Vee(opr)=2V-6V
• Pin and Function Compatible with 74LS620,623
PIN ASSIGNMENT(TOP VIEW)
TC74HC620A
GAB 1
A1
2
TC74HC623A
20 Vee
GAB
20 Vee
19 GBA
Al
A2 3
1881
A2 3
A3 4
1782
A3 4
17 B2
A4
5
16 B3
A4
16 B3
A5 6
15 B4
A5 6
15 B4
A6
7
14 B5
A6 7
1485
A7 8
13 B6
A7 8
13 B6
A8 9
12 B7
A8 9
12 B7
GND 10
11 B8
GND10
11 B8
HC-613
2
5
19 GBA
18 Bl
TC74HC620AP/AF ____________------------------TC74HC623API AF
IEC LOGIC SYMBOL
TC74HC620A
TC74HC623A
TRUTH TABLE
INPUTS
GAB
GBA
L
H
L
H
FUNCTION
A BUS
B BUS
L
OUTPUT
INPUT
H
INPUT
OUTPUT
H
High Impedance
L
High Impedance
Z:Hlgh Impedance
HC-614
OUTPUTS
HC620A
HC623A
A=B
A=B
B=A
B=A
Z
Z
Z
Z
TC74HC620API AF
TC74HC623API AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Va;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Va;
VIN
Vour
11K
10K
lour
Ia;
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Va;+0.5
-0.5 -Va;+0.5
±20
±20
±35
±15
500(DIP) '/180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Bus Terminal Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Va;
0- Va;
-40 - 85
o - 1000(Va;=2.0V)
0- 500(Va;=4.5V)
o - 400(Va;=6.0V)
SYMBOL
Va;
VIN
VI/O
Topr
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
V(l-{
Low-Level
Output Voltage
VOL
3-State Output
Off-State Current
I(E
Input Leakage Current
Quiescent Supply Current
I I'.;
Ia;
TEST CONDITION
VI;>; =
VIHorVIL
VI:,\=
VIHorVIL
I(l-{ =-20 tl A
I(l-{ =-6 rnA
I(l-{ =-7. 8mA
IOL =20 tl A
IO!. -6 rnA
IO!. =7.8mA
VI~ =V 1H orV 1L
Vour =Va; or GND
VI!, -Va; or GND
VI!" -Vcr. or GND
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
HC-615
Ta--40 -85"C UNIT
Ta-25"C
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
6.0
5.9
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.0
0.1
0.1
0.0
0.1
0.1
V
0.0
O. 1
0.1
0.33
0.17
0.26
0.33
0.26
0.18
±0.5
±5.0
+0.1
+1.0 tl A
40.0
4.0
MIN.
1.5
3.15
4.2
-
TC74HC620AP/AF
TC74HC6,23API AF
.f
AC ELECTRICAL CHARACTERISTICS(CL=50pF.lnput t r =tf=6ns)
TEST
Ta-25"C
! Ta40 -85"(:
UNIT
PARAMETER
SYMBOL
CONDITION CL Vcc MIN. TYP. MAX. MIN. MAX.
2.0
25
60
75
tTUi
Output Transition Time
4.5
7
50
12
15
tTHL
6.0
6
11
13
2.0
42
100
125
50 4.5
13
20
tpLH
25
6.0
17
11
21
Propagation Delay Time
TC74HC620A
2.0
58
140
175
150 4.5
tpHL
18
28
35
6.0
15
24
30
2.0
38
8.5
105
12
50 4.5
17
21
tpLH
10
6.0
14
18
ns
Propagation Delay Time
TC74HC623A
2.0
54
125
155
150 4.5
17
25
31
tpHL
6.0
14
21
26
2.0
48
150
190
tpZL
50 4.5
19
30
38
3-State Output
6.0
26
16
33
RL= 1 kQ
Enable Time
2.0
240
61
190
tpZH
150 4.5
24
38
48
6.0
20
32
41
2.0
45
150
190
3-State Output
tpLi
RL= 1 kQ
4.5
50
20
30
38
Disable Time
tpHZ
6.0
18
26
33
hlput Capacitance
CIN
GAB,GR
5
10
10
I Bus Input Capacitance CI/O
An,Bn
. 13
- pF
TC74HC620A
31
Power Dissipation Capacitance
Cro(I)
TC74HC623A
34
Note (1) Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCtp)=CPD .Vo:;. f['l; +10:; 18(per bit)
-
-
-
-
-
-
-
HC-616
___________ TC74HC646AP
TC74HC648AP
OCTAL BUS TRANSCEIVER/REGISTER
TC74HC646AP NON-INVERTING
TC74HC648AP INVERTING
The TC74HC646A/648A are high speed CMOS OCTAL
BUS TRANSCEIVER/REGISTERs fabricated
with
silicon gate C2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
These devices are bus transceivers with 3-state outputs,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
internal registers.
When the direction input (DIR) is held high, the Al
thru A8 become inputs and the Bl thru B8 become
outputs. When tlie DIR input is held low, the Al thru A8
become outputs and the Bl thru B8 become inputs.
The enable input G is held high, both the A Bus and· B
Bus become high impedance.
The select inputs (SAB, SBA) can multiplex stored and
real-time (transparent mode) data.
Data on the A Bus or B Bus can be clocked into the
registers on the positive going transition of either CAB or
CBA clock inputs, respectively.
The TC74HC646A is a non-inverting output type while
the TC74HC648A is of the inverting output type.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. ~\1Ax=73~1Hz(typ.}at Vcc=5V
• Low Power Dissipation ............ l ee =4ttA(Max.}at Ta=25"C
• High Noise Immunity .............. · V!'o-rI>-- ~
L{>o-{>o--. +A
o-----{::>o-r-{ +a
~+8
Al
o-h+----D><>-r--1
A8o-£:--
1--r-oC1----+--+o
81
_----::.;SA..;.;M~E AS ABOV..::E'--___ ~
88
Note: In case of TC74HC646A oulput inverler marked. at A bus and B bus are eliminated.
HC-619
TC74HC646AP
TC74HC648AP
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP)*
-65 -150
300
SYMBOL
Vee
V,:\
VOL,
I'K
10K
IOl"
lee
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
O-Vee
O-Vee
-40 - S5
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
SYMBOL
Vee
V""
Vou,
Topr
tr • tr
UNIT
V
V
V
·C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
V'H
Low-Level
Input Voltage
V'L
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
VOL
3 State Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
ICE
1,:-:
lee
TEST CONDITION
V'N=
V'HorV'L
V'N=
V'HorV'L
100 =-20/1. A
100 --6 rnA
101-, =-7. SmA
lOL =20 /1. A
lOL -6 rnA
lOL =7. SmA
YIN -V'H or V'L
VOL, =Vee or GND
V,:\ -Vee or GND
V,:\ -Vee or GND
Ta-25"C
Ta--40 -S5"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
I.S
1.S
1.9
1.9
2.0
4.4
4.5
4.4
V
6.0
5.9
5.9
4. IS
4.31
4.13
5.6S
5.63
5. SO
0.0
0.1
0.1
0.1
0.0
0.1
V
0.1
0.0
0.1
0.26
0.33
O. 17
0.26
0.33
O.IS
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6~ 0
MIN.
1.5
3. 15
4.2
6.0
-
-
±0.5
-
±5.0"
6.0
6.0
-
-
-
±0.1
4.0
-
±1.0
40.0
HC-620
-
/1. A
___________________________________ TC74HC646AP
TC74HC648AP
TIMING REQUIREMENTS (Input tr = t, = 6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
tW(U
tW(H)
Minimum Set-up Time
ts
Minimum Hold Time
th
Clock Frequency
f
Va:;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C
TYP.
LIMIT
75
15
13
50
10
9
5
5
5
6
31
36
Ta- 40 -85"C
UNIT
LIMIT
95
19
16
65
ns
13
11
5
5
5
5
MHz
25
29
AC ELECTRICAL CHARACTERISTICS(lnput t r =tf=6ns)
PARAMETER
SYMBOL
Output Transition Time
t11..H
t1l-lL
Propagation Delay Time
(BUS-BUS)
Propagation Delay Time
(CAB,CBA-BUS)
Propagation Delay Time
(SAB,SBA-BUS)
Output Enable time
(G,DIR-BUS)
Output Disable time
(G,DIR-BUS)
TEST
CONDITION
CL
50
50
tpLH
tpHL
150
50
tpLH
tpHL
150
50
tpLH
tpHL
150
50
tpZL
tp7J-I
R L= 1 kQ
150
tp12
tpHZ
RL = 1 kQ
50
Va:;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
HC-621
MIN.
-
-
-
-
-
-
-
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
60
75
25
12
15
7
10
13
6
74
150
190
21
30
38
18
26
32
91
190
240
26
38
48
22
32
41
210
98
265
28
42
53
24
36
45
250
116
315
33
50
63
28
43
54
ns
81
170
215
23
34
43
20
29
37
210
98
265
28
42
53
24
36
45
175
220
84
24
35
44
20
30
37
102
215
270
29
54
43
25
37
46
175
220
60
23
35
44
20
30
37
TC74HC646AP _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC648AP
AC ELECTR.ICAL CHARACTERISTICS(lnput tr=tr=6ns)(Cont'd)
Ta- 40'?""'85"C
Ta-25"C
TEST
PARAMETER
SYMBOL CONDITION
UNIT
CL Vee MIN. TYP. MAX. MIN. MAX.
6
5
2.0
19
Maximum Clock Frequency
MHz
4.5
31
25
50
67
f~1AX
6.0
36
29
79
Input Capacitance
CIN
10
10
5
Output Capacitance
pF
CCXJT
13
Power Dissipation Capacitance
Cm
(11: 1 )
39
Note (I) C PD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
leeQxl=CPD • VOC· fN +IOC /8(per bit)
HC-622
TC74HCT646AP
TC74HCT648AP
OCTAL BUS TRANSCEIVER/REGISTER
TC74HCT646AP
NON-INVERTING
TC74HCT648AP
INVERTING
The TC74HCT646A/HCT648A are high speed CMOS
OCTAL BUS TRANSCEIVER/REGISTERs fabricated
with silicon gate C~OS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Their inputs are compatible with TTL, NMOS, and
CMOS output voltage levels.
These devices are.bus transceivers with 3-state outputs,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
internal registers.
The TC74HCT646A is a non-inverting output type while
the TC74HCT648A is of the inverting output type.
All inputs are equipped with protection circuits against
static dischage or transient excess voltage.
FEATURES:
• High Speed .....•.••..•.•.•.....•......•• (\1AX=60MHz(Typ.)at Va;=5V
• Low Power Dissipation ............ Ia;=4J.tA(Max.)at Ta=25"C
• Compatible with TTL Output ......... VIH =2V(Min.)V IL =O.8V(Max.)
• Output Drive Capability ............ 15 LSTTL Loads
• Symmetrical Output Impedance "'1 IOH 1=Ia. =6mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Pin and Function Compatible with 74LS646/648
24
P(DIP24-P-300)
PIN ASSIGNMENT
CAB 1
24 Vee
SAB 2
23 CBA
DIR 3
22 SBA
G
A1 4
21
A2 5
20 B1
A3 8
,. B2
A4 7
18 B3
A5 8
17 B4
AI 8
11 B5
15 B8
14 B7
13 B8
(TOP VIEW)
IEC LOGIC SYMBOL
TC74HCT648A
APPLICATION NOTES
TC74HCT848A
1) Do not apply a signal to any
bus terminal when it is in the out
put mode. Damage may result.
2) All floating (high impedance)
bus terminals must have their
input levels fixed by means of pull
up or pull down resistors or bus
terminator IC's such as the
TOSHIBA TC40117BP.
HC-623
TC74HCT646AP
TC74HCT648AP
TRUTH TABLE
TC74HCT646A(The truth table for TC74HCT648A is the same, but with the outputs inverted)
G
DIR CAB CBA SAB SBA
X·
H
X·
X
X
X
I
I
X
X
X·
X·
L
X
I
X-
L
x"
X·
I
x"
A
B
Function
INPUTS INPUTS
Z
Z
X
X
The output funcions of A and B Busses are
disabled.
Both A and B Busses are used as inputs to the
internal flips-flops. Data on the Bus will be
stored on the rising edge of the Clock.
INPUTS OUTPUTS
L
H
L
H
L
H
The dllta on the A bus are displayed on the B
bus
X
L
H
L
H
The data on.the A Bus are displayed on the B
Bus, and are stored into the A storage flip-flops
on the rising edge of CAB.
H
X
X
an
The data in the A storaga flip-flops are
displayed on the B Bus.
X·
H
X
L
H
L
H
The data on the A Bus are stored into the A storage
flip-flops on the riSing edge of CAB, and th.e stored
data propagate directly onto the B Bus.
x"
X
L
x" I
X
x"
OUTPUTS INPUTS
L
L
X
x" I
Notes:
L
H
L
H
The data on the B bus are displayed on the A
bus.
L
L
H
L
H
The data on the B Bus are displayed on the A
Bus, and are stored into the B storage flip-flops
on the rising edge of CBA.
X
H
an
X
The data in the B storage flip-flops are
displayed on the A Bus.
X
H
L
H
L
H
The data on the B Bus are stored into the B storage
flip-flops on the rising edge of CBA, and the stored
data propagate directly onto the A Bus.
X: Don't Care
an: The data stored into the internal flip-flops by most recent low to high transition of
the clock inputs
Z: High Impedance
The clock are not internally gated with either G or DIR. Therfore, data on the A and
lor B Busses may be clocked into the storage flip-flops at any time.
HC-624
TC74HCT646AP
---------------------------------TC74HCT648AP
TIMING CHART
TC74HCT646A
G --------------------------------------------------------~
OIR
SAl ------~
I
I-
A : OutpUt
I: Input
A : Input
I : Output
~
: Don't care
Z : High Impedance
Note: The timing chart for TC74HCT648A is the same, but with the outputs inverted.
SYSTEM DIAGRAM
TC74HCT646A
CAl
CIA~~~~~~--------~--_+~
SAl
o---{>orI>o-- ~
Y>o--l>-- +A
SBA~~
4>0-£>0- +8
A 1 cr+r+-----t·~MIl
____..;;S;,;..A~M_E AS ABO~E~____ ~ .8
Note: In case of TC74HCT646A output inverter marked. at A bus and 8 bus are eliminated.
HC-625
8:Z
TC74HCT646AP
TC74HCT648AP---------------------------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER·
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI:VOLT
11K
10K
IQT
lee
Po
Tstg
TI-
UNIT
V
V
V
rnA
rnA
rnA
rnA
VALliE
-0.5-;
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±35
±;5
500(DIP)*
-65 -150
300
*500mW in tlierange of Ta=
-40"C- 65"C. From Ta=65"C
to85"C a derating factor of
-10m W/"C shall be applied
until 300m W.
mW
"C
"C.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vee
Input Voltage
VI:-\
Output Voltage
VOLT
Topr
Operating Temperature
Input Rise and Fall Time
lr.lr
VALUE
4.5-5.5
O-Vee
O-Vee
-40-85
0-500
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
High-Level
Input Voltage
Low-Level
Input Voltage
High-Level
Output Voltage
Low-Level
Output Voltage
3-State Output
Off-State Current
Input Leakage Current
Quiescent Supply
Current
Ta=25"C
Vee MIN. TYP. MAX.
4.5
VIH
1 2.0
! 5.5
4.5
0.8
Vu.
1
5.5
1m = - 20 ,u A . 4.5 4.4
4.5
VI:-\ =
Vm
VIIi orVIL 1oo=-6,uA 4.5 4.18 4.31
0.0
0.1
lot. =20 ,uA 4.5 VI:-\ =
Va.
VIH orVII• lot. =6 ,uA 4.5
- 0.17 0.26
VI:-\ =VIH orVII.
5.5
±0.5
lev.
V,x =Va; or GND
.
±O.1
5.5
VIX =Vee or GND
11:-\
4.0
5.5
lee
VI:-\ =Vee or GND
.
Per
input:V
:-\=0.5Vor2.4V
I
5.5
b.1cc
2.0
Other input:Veeor GND
SYMBOL
TEST CONDITION
-
-
-
HC-626
Ta=-40-85"C
milT
MIN. MAX.
2.0
-
V
-
0.8
V
4.4
4.13
-
V
0.1
0.33
V
-
±5.0
±1.0
,uA
40.0
2.9
rnA
I
TC74HCT646AP
TC74HCT648AP
TIMING REQUIREMENTS(lnput tr=tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Vee
Minimum Pulse Width
(CLOCK)
tW([.)
tW(J-1)
4.5
5.5
Minimum Set-up Time
t8
4.5
5.5
Minimum Hold Time
th
4.5
5.5
Clock Frequency
r
4.5
5.5
.
Ta-25,,(
TYP.
LIMIT
. Ta
40 -85"C UNIT
LIMIT
-
15
14
19
17
-
-
10
9
13
12
-
5
5
5
5
-
31
37
25
30
ns
MHz
AC ELECTRICAL CHARACTERISTICS(lnput t r =tf=6ns)
TEST
Ta--40 -85"(
'1'a-25"(
PARAMETER
UNIT
ISYMBOL CONDITION
CL Vee MIN. TYP. MAX. MIN. MAX.
t TiJi
4.5
7
12
15
Output Transition .Time
50
5.5
6
tTHL
11
14
-
Propagation Delay Time
(BUS-BUS)
Propagation Delay Time
(CAB, CBA-BUS)
Propagation Delay Time
(SAB, SBA-BUS)
,Output Enable time
(DIR, G-BUS)
Output Enable time
(DIR. G-BUS)
tpLH
50
4.5
5.5
tpHL
150
4.5
5.5
tpLH
50
4.5
5.5
tptlL
150
4.5
5.5
tpLH
50
4.5
5.5
-
tptil.
150
4.5
5.5
-
tPZL
50
4.5
5.5
150
4.5
5.5
50
4.5
5.5
R L= lkg
tl0l
tpl7.
tpHZ
RL = 1 kg
-
-
-
20
17
30
27
25
22
38
34
29
26
44
40
34
31
52
47
24
21
34
31
29
26
42
38
26
23
38
34
-
31
28
46
41
-
26
23
35
32
-
-
-
-
38
34
48
43
55
50
65
59
ns
43
39
53
46
48
43
58
52
44
40
- MHz
4.5
31
55
25
5.5
37
61
30
Input lApacitance
CL'I;
DIR, G, SAB, SBA, CAB, CBA
5
10
10
Output Capacitance
COlT
An Bn
13
pF
40
Power Dissipation Capacitance Crn(l) TC74HCT646A
TC74HCT648A
39
Note (1) CPD is deCined as the value or the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
I CC ~=CPD • Va;. fL'l; +Ia; 18(per bit)
Maximum Clock Frequency
f~AX
50
-
He-627
-
-
TC74HC651AP _ _ _ _ _ __
TC74HC652AP
OCTAL BUS TRANSCEIVER/REGISTER
TC74HC651AP INVERTING
V
The TC74HC651A/652A are high speed CMOS OCTAL
BUS TRANSCEIVER/REGISTERs fabricated with
silicon e-ate CMOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while ·maintaining the CMOS low power
dissipation .
.These devices are bus transceivers with 3-state outputs.
D-type flip-flops. and control circuiry arranged for
multiplexed transmission of data directly from the
internal registers.
.
__
When the enable inputs GAB and GBA are held high. the
At thru AS become inputs and the Bl thru B8 become
outputs. When the GAB and GBA are held low. the Al
thru AS become outputs and the Bl thrU BS become
inputs, When GAB is low and GBA is high. the outputs
functions .of the A and B Busses are disabled.
The select. inputs (SAB.SBA) can multiplex stored and
real-time(transparent mode)data.
Data: on the A Bus or B Bus can be clocked into the
registers on the positive going Itransition of either CAB or
CBA~clock inputs. respectively.
The TC74HC651A is of the inverting output type while
the TC74HC652A. is Ii non-inverting output type.
AU inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. f:\OIA.'F73~fHz(typ.)at \tc=5V
• Low Power Dissipation ............ Icc=4.1lA(Max.)at Ta=25"C
• High Noise Immunity· .... ·· ...... ·· V\lH=V:-;IL2S" Vcc(Min.)
• Output Drive Capability ... · .... ·· .. · 15 LSTTL Loads
• SymmetricalOutput Impedance ... 1100 I =IQL=6mA(Min.)
• Balanced Propagation Delays ...... tpLH"tpHL
• Wide Operating Voltage Range ... Vee (opr. )=2V -6V
• Pin and Function Compatible With 74LS6511652.
IEC LOGIC SYMBOL
24
P(DIP24-P-300)
PIN ASSIGNMENT
CAB 1
24 Vee
SAB 2
23 CBA
GAB 3
A1 4
A2 6
22 SBA
A3
21 GBA
20 B1
e
19 B2
A4 7
18 B3
AS 8
17 B4
AI 9
11 B5
A7 10
15 B6
AI 11
GND 12
14 B7
13 B8
(TOP VIEW)
APPLICATION NOTES
1)- Do not apply a signal to :any
bus terminal when it is in the out
put mode. Damage may result.
2) All floating (high impedance)
bus terminals must have their
input levels fixed by means of pull
up or pull down resistors or bus
terminl;ltor Ie's such as the
TOSHIBA TC40117BP.
CIA
SIA
CAl
SAl
AI
AI
HC-628
___________________________________ TC74HC651AP
TC74HC652AP
TRUTH TABLE
TC74HC652A
(Th8'truth table for TC74HC651A is the same, but with the outputs inverted)
~AB GBA CAB CBA SAB SBA
A
B
INPUTS INPUTS
L
H
X' X'
X
X
Z
Z
S
X
X
X
X
S
Function
The output functions of the A and B Busses
a re disabled.
Both A and B Busses are used as inputs to the
internal flip-flops. Data on the Bus will be
stored on the rising edge of the Clock.
OUTPUTS INPUTS
L
L
L
H
L
H
The data on the B bus are displayed on the A
bus.
L
L
H
L
H
The data on the B Bus are displayed on the A
Bus, and are stored into the B storage flip-flops
on the rising edge of CBA.
X
H
an
X
The data in the B storage flip-flops are
on the A Bus.
X
H
L
H
L
H
The data on the B Bus are stored into the B storage
flip-flops on the rising edge of CBA, and the stored
data propagate directly onto the A Bus.
X' X'
X
L
X'
S
X
X'
X'
X' S
displaya~
INPUTS OUTPUTS
H
H
L
H
L
H
The data on the A bus are displayed on the B
bus.
X
L
H
L
H
The data on the A Bus are displayed on the B
Bus, and are stored into the A storage flip-flops
on the rising edge of CAB.
H
X
X
an
The data in the A storage flip-flops are displayed on
the B Bus.
H
X
L
H
L
H
The data on the A Bus are stored into the A storage
flip-flops on the rising edge of CAB, and the stored
data propagate di reclly onto the B Bus.
X' X'
L
X
X'
L
X' X'
X'
S
S
OUTPUTS OUTPUTS
H
L
X'
X'
H
H
an
an
The data in the A storage flip-flops are displayed on
the B Bus, and the data in the B storage flip-flops
are displayed onthe A
Notes: X: Don't Care
an: The data stored into the internal flip-flops by most recent low to high
transition of the clock inputs.
Z: High Impedance
• The clocks are not internally
gated with either Output Enables or Select Inputs. Therfore, data on the A and/or B Busses
may be clocked into the storage flip-flops at any time.
HC-629
TC74HC651AP _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC652AP
TIMING CHART
TC74HC6&2A
OA8 ____________________________- - ,
GiA----~--~------------------~
LJ1J Vl//J//i//1/1/////2;'////77//1////
lAB ______-..I
A
8
A : Input
I·
A : Output
8: Output
8: luput
.~ ~n'tC8re
Note:The timing chart for TC74HC661A 18 the lam •• but with the outputl Inverted.
SYSTEM DIAGRAM
TC74HC651A
GAI~-{>-~--i>--------------------~-,
GiA ........--ct>-.-o----------------,
CAI ........-1.>-~J~---------,
CIA ........~>-~~--------~----r__,
IAI~+A
~+A
llA
o.-.-f>o.r-I>-- +1
~+B
AI <>-tI-t----t;>t>-T"'i
II
,!L......... __________~~~Kr------~_____
AI 0-£":=___S.;..,;A..;.M..:.!= AS ABOy...;E;;.....___ ~
No'~:
B8
In case of TC74HC852A output Inverter marked • at A bus and B bus areeliminated.
He-630
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC651AP
TC74HC652AP
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
Vee
VI),:
VOLT
11K
10K
Io\;T
lee
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
UNIT
V'
V
V
mA
mA
mA
mA
mW
"C
"C
±~5
±75
500(DlP)*
-65 -150
300
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until 300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Vee
V(lI:
VOl;T
Topr
Input Rise and Fall Time
tr • tr
VALUE
2-6
0- Vee
0- Vee
-40 - 85
0- 1000(Vee =2.0V)
0- 500(Vee=4.5V)
0- 400(Vee=6.0V )
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
High-Level
Input Voltage
Low-Level
Input Voltage
VIH
\'IL
I
High-Level
Output Voltage
Va;
Low-Level
Output Voltage
VOL
3-State Output
Off -State Current
Input Leakage Current
Quiescent Supply Current
TEST CONDITION
lev.
i
.-.
II:,
Icc
!
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
IaJ =-20p. A 4.5
VI:-';=
6.0
VlliorVIL
101-1--6 mA 4.5
IElIJ =-7.8mA 6.0
2.0
IOL =20 p.A 4.5
VI:' =
6.0
VlliorVIL
IOL -6 mA 4.5
IOL =7.8mA, 6.0
VI~ -VIII or V IL
6.0
VOLT =Vee or GND
VI),: -Vee or GND
6.0
VI),: -Vee or GND
6.0
HC-631
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.18
4.31
4.13
5.68
5.80
5.63
0.0
0.1
0.1
0.0
0.1
0.1
V
0.0
0.1
0.1
0.26
0.33
0.17
0.26
O. 18
0.33
MIN.
1.5
3.15
4.2
-
-
-
-
±0.5
-
±5.0
=0.1
4.0
-
±1.0
40.0
-
p.A
TC74HC651AP
TC74HC652AP-----------------
TIMING REQUIREMENTS(lnput tr=t,=8ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
tW(L)
tw(tu
Minimum Set-up Time
ts
Minimum Hold Time
tb
Clock Frequency
f
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C
LIMIT
TYP.
75
15
13
50
10
9
5
5
5
6
31
36
-
Ta--40 -85"C
UNIT
LIMIT
95
19
16
65
13
11
5
5
5
5
25
29
-
ns
MHz
AC ELECTRICAL CHARACTERISTICS(lnput t r =t,=8ns)
TEST
Ta=-40 -85"C
Ta-25"C
PARAMETER
SYMBOL
UNIT
CONDITION CL
Vee MIN. TYP. MAX. MIN. MAX.
2.0
60
75
25
t11.H
Output Transition Time
4.5
15
50
12
7
tTIlL
6.0
13
10
6
2.0
190
74
150
4.5
50
38
21
30
Propagation Delay Time
tplJi
6.0
32
18
26
tp~n.
2.0
91
240
190
(BUS-BUS)
150 4.5
26
38
48
6.0
22
32
41
98
210
265
2.0
28
50 4.5
42
53
Propagation Delay Time
tpLH
24
36
45
6.0
tpHL
250
116
315
2.0
(CAB.CBA-BUS)
50
150 4.5
33
63
28
43
6.0
54
ns
2.0
170
215
81
4.5
50
23
34
43
Propagation Delay Time
tpLH
6.0
29
37
20
tpHL
2.0
210
265
98
(SAB.SBA-BUS)
150 4.5
42
28
53
6.0
24
36
45
2.0
220
175
74
50 4.5
21
35
44
Output Enable time
tpZL
6.0
37
18
30
R I.= lkQ
tpZH
2.0
270
91
215
(GAB.GBA-BUS)
150 4.5
26
54
43
6.0
46
22
37
2.0
220
50
175
Output Disable time
tpLZ
RL = 1 kQ
4.5
50
21
44
35
tpHZ
(GAB.GBA-BUS)
6.0
37
18
30
-
I
-
HC-632
__________________________________ TC74HC651AP
TC74HC652AP
AC ELECTRICAL CHARACTERISTICS(lnput tr=tf=6ns)(Cont'd)
PARAMETER
Maximum Clock Frequency
Input Capacitance
OUtput (.;apacitance
l'ower Dissipation Capacitance
TEST
SYMBOL CONDITION
CL
Vee
50
2.0
4.5
6.0
fMAX
MIN.
-
-
CIN
(.;oor
Ta-25"C
TYP. I MAX.
19 I
6
67
79
5
13
39
31
36
10
Ta--40-85"C UNIT
MIN. MAX.
-
5
25
29
10
MHz
pF
(l:t 1 )
Notem Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia;qw=CPD • Voc< fN +Ioc /8(per bit)
Cm
HC-633
TC74HCT651AP _ _ _ _ _ __
TC74HCT652AP
OCTAL BUS TRANSCEIVER/REGISTER
TC74HCT661AP
NON-INVERTING
TC74HCT662AP
INVERTING
The TC74HCT651A/HCT652A are high speed CMOS
OCT AL BUS TRANSCEIVER/REGISTERs fabricated
with silicon gate C2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
Their inputs are compatible with TTL, NMOS, and
CMOS output voltage levels.
These devices are bus transceivers with 3-state outputs,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission· of data directly from the
internal registers.
The TC74HCT651A is of the inverting output type while
the TC74HCT652A is a non-inverting output type.
ALL inputs are equipped with protection circuits
against static dischage or transient excess voltage.
FEATURES:
• High Speed •· ..... ···· .. ·· ...... ·........ ~=60MHz(Typ.)at Vcc=5V
• Low Power Dissipation .. · .. · .... ·~Icc=4.uA(Max.)at Ta=25"C
• Compatible with TTL Output .... ,.... V1H =2V (Min.) VIL =O.8V (Max.)
• OUtput Drive Capability·· .......... 15 LSTTL Loads
• Symmetrical Output Impedance "'1 IOH 1=Ia. =6mA(Min.)
• Balanced Propagation Delays ...... tpLH '" tpliL
• Pin and Function Compatible with 74LS6511652
24
P(DIP24-P-300)
PIN ASSIGNMENT
CA8 1
24 Vee
SA8 2
23 CBA
GA8 3
22 SBA
AI 4
21 G8A
A2 5
20 81
A3 6
19 B2
A4 7
18 B3
A5 8
17 B4
A6 9
16 B5
A7 10
15 B6
A8 11
14 B7
13 88
(TOP VIEW)
IEC LOGIC SYMBOL
TC74HCT8I!1A
APPLICATION NOTES
TC74HCT652A
1) Do not apply a signal to any
bus terminal when it is in the Qut
put mode. Damage may result.
2) All floating (high impedance)
bus terminal must have their
input levels fixed by means of pull
up or pull down resistors or bus
terminator IC's such as the
TOSHIBA TC40117BP.
iiiA
........
.,
0 ...
c ...
c ...
HC-634
_________________________________ TC74HCT651AP
TC74HCT652AP
TRUTH TABLE
TC74HCT852A(The truth for TC74HCT851A is the same, but with the outputs inverted)
GAB GBA CAB CBA SAB SBA
X·
L
X·
A
B
Function
INPUTS INPUTS
X
X
H
S
S
X
X
X·
)(
L
X
S
X·
L
x"
)(
S
x"
Z
Z
X
X
The output funcions of A and B Busses are
disabled.
Both A and B Busses are used as inputs to the
internal flips-flops. Data on the Bus will be
stored on the rising edge of the Clock.
INPUTS OUTPUTS
H
H
L
H
L
H
The data on the A bus are displayed on the B
bus
X
L
H
L
H
The data on the A Bus are displayed on the B
Bus, and are stored into the A storage flip-flops
on the rising edge of CAB.
H
X
X
On
X·
H
X
L
H
L
H
x"
X
L
X- S
X
x"
X·
x"
S
The data in the A storage flip-flops are
displayed on the B Bus.
The data on the A Bus are stored into the A storage
flip-flops on the rising edge of CAB, and the stored
data propagate directly onto the B Bus.
OUTPUTS INPUTS
L
L
L
H
L
H
The data on the B bus are displayed on the A
bus.
L
L
H
L
H
The data on the B Bus are displayed on the A
Bus, and '.Ire stored into the B storage flip-flops
on the rising edge of CBA.
X
H
On
X
The data in the B storage flip-flops are
displayed on the A Bus.
X
H
L
H
L
H
The data on the B Bus are stored into the B storage
flip-flops on the rising edge of CB A, and the stored
data propagate directly onto the A Bus.
OUTPUTS OUTPUTS
H
Notes:
L
X·
X·
H
H
On
On
The data stored to the internal flip-flops are
displayed at the A and B bus respectively.
X: Don't Care
On: The data stored into the internal flip-flops by most recent low to high transition of
the clock inputs
Z: High Impedance
The clock are not internally geted with either GAB or GBA. Therfore, data on the A
and/or B Busses may be clocked into the storage flip-flops at any time.
HC-635
TC74HCT651AP
:rC.74HCT652AP - - - - - - - - - - - - . . - - - -......
TIMING CHART
TC74HCT852A
GAI ________________________________
iii ________________________________
A : Input
~
Don't
~
~
B: Output
A : Output
,1
I: Input
c.,.
Note: The timing chart for TC74HCT651A is the same, but with the outputs inverted.
SYSTEM DIAGRAM
TC74HCT851A
GAI~-{~~>--D~----------------------_,
Gii~~>_-i~----------------,
CAI~-;~~>_----------_,
CIA
~__1)O-_cl>-----------__1f_--+__,
SAB
---t>o-r-t>-- ~
L.[>a--C>o- • A
SBA~.B
L.£>o.-(>o.- • B
Bl
AI
....r=-
________
SAME AS ABOV_E_ _ _ _
=.3-0
B8
Note: in case of TC74HCT652A output inverter marked. at A bus and. B bus are eliminated.
HC-636
_________________________________ TC74HCT651AP
TC74HCT652AP
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Supply Voltage Range
Vee
DC Input Voltage
VI:>;
DC Output Voltage
VOLT
Input Diode Current
11K
Output Diode Current
10K
DC Output Current
IOCT
DC Vee/Ground Current
Icc
Power Dissipation
PI)
Storage Temperature
Tstg
Lead Temperature lOsec
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5 -7
-0.5 -Vcc+0.5
-0.5 -Vcc+0.5
±20
±20
±35
±75
500(DIP)*
-65 -150
300
*500mW in the range of Ta=
-40"C- 6S"C. From Ta=6S"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Supply Voltage
Vee
Input Voltage
VI:"
Output Voltage
Va,T
Operating Temperature
Topr
Input Rise and Fall Time
tr; tr
UNIT
V
V
V
"C
ns
VALUE
4.5-5.5
O-Vee
O-Vee
-40-85
0-500
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIIi
Low-Level
Input Voltage
V IL
High-Level
Output Voltage
Low-Level
Output Voltage
3-State Output
Orr~State Current
Input Leakage Current
Quiescent Supply
Current
V(l-(
Va,
ICll
II:-J
Icc
.6.lcc
TEST CONDITION
Ta=~40-85"C
Ta=25"C
IDlIT
Vee MIN. TYP. MAX. MIN. MAX.
4.5
- 2.0
V
1 2.0
5.5
4.5
V
- 0.8
0.8
1
5.5
4.5 4.4
4.5
4.4
V
- 4.13 4.5 4.18 4.31
4.5
0.0
0.1
0.1
- 0.33 V
4.5
0.17 0.26
-
101= -20JlA
VI:>; =
Viii orVIL IaI=-6JlA
Ia. =20 JlA
VI:>; =
VII-! orVII, Ia. = 6 JlA
VI:>; = VIII orVIL
VI:>; =Vcc or GND
VI:>; =Vcc or GND
VI:>; =Vee or GND
Per input: VI:>; =0. 5V or 2.4 V
Other inpui:Vccor GND
He-63?
5.5
5.5
5.5
5.5
-
-
±0.5
±O.l
4.0
2.0
-
±5.0
±1.0
JlA
40.0
2.9
rnA
TC74HCT651 AP _ _- - - - . - - - - - - - - - - TC74HCT652AP
TIMING REQUIREMENTS(lnput tr =t,=6ns)
PARAMETER
SYMBOL TEST
CO~mITIO~
Vcr.
Ta-25"C
TYP.
LIMIT
-
Ta--40 -85"C
LIMIT
Minimum Pulse Width
(CLOCK)
t\\'(L)
twO!)
4.5
5.5
-
15
14
19
17
Minimum Set-up Time
ts
4.5
5.5
-
10
9
13
12
Minimum Hold Time
th
4.5
5.5
-
5
5
5
5
Clock Frequency
f
4.5
5.5
-
31
37
25
20
-
I
ns
MHz
AC ELECTRICAL CHARACTERISTICS(lnput t r =t,=6ns)
T.I!;ST
Ta-25"C
Ta--40 -85"C
SYMBOL
PARAMETER
CONDITION CL
Vcc MIN. TYP. MAX. MIN. MAX.
- I 7
4.5
12
15
t 11J-l
Output Transition Time
50
5.5
6
tTHI.
11
14
Propagation Delay Time
(BUS-BUS)
Propagation Delay Time
(CAB. CBA-BUS)
Propagation Delay Time
(SAB. SBA-BUS)
Output Enable time
tpLH
50
4.5
5.5
tpliL:
150
4.5
5.5
tpUi
50
4.5
5.5
.,tpHL
150
4.5
5.5
tpLH
50
4.5
5.5
tpHL
150
4.5
5.5
tlill,.
50
4.5
5.5
150
4.5
5.5
50
4.5
5.5
RL = 1 kQ
(GAB. GBA-BUS)
tJ1lli
Output Enable time
(GAB. GBA-BUS)
tplZ
tpHZ
R L=lkQ
-
-
20
i7
30
27
-
38
34
25
22
38
34
-
48
43
29
26
44
40
34
31
52
47
24
21
34
31
29
26
42
38
-
22
20
33
30
-
27
24
41
37
24
22
35
32
-
-
-
-
-
-
U~IT
U~IT
55
50
65
59
ns
43
39
53
48
41
37
51
46
44
40
-
4.5
31
55
25
- MHz
5.5
37
61
30
Input Capacitance
CI~
GAB, GHA. SAB. SBA. CAB. CBA
5
10
10
Uutput CapaCItance
- i 13
CO\..T
An Bn
pF
TC74HCT65IA
38
I
Power Dissipation Capacitance Cro(l)
TC74HCT652A
! 39
Note (1) Cro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
I cc(W=C ro • Va;. f~ +Ia; 18(per bit)
Maximum Clock Frequency
r MAX
50
-
HC-638
-
-
-
------TC74HC670API AF
4 WORDx 4 BIT REGISTER FILE( 3 -STATE)
The TC74HC670A is a high speed CMOS 4-WORDs x 4BITs REGISTER FILE fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The register file is organized as 4 words of 4 bits each.
Separate read and write address inputs (RA, RB, and
WA, WB) and enable inputs (RE, WE) are available
permitting simultaneous writing into one word location
and reading from another location.
Four data inputs (DO D3) are provided to store the 4-bit
words.
The write address inputs (WA, WB) determine the
location of the stored word in the register. When write
Enable(WE)is held low, the data is entered into addressed
location. When WE is held high, data and address inputs
are inhibited. The data acquisition from thp. four registers
is made possible by the read address inputs (RA. RB)
when the Read Enable (RE) is held low. When RE is held
high the data outputs are in the high impedance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd=23ns(Typ.)at Vcc=5V
• Low Power Dissipation ............ Icc=4/.LA(Max.)at Ta=25"C
• High Noise Immunity .. ·· .... · .... ·· V:-'lH =V:\IL =28% Va;(Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance ... , I ai , =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH '" tpI-U..
• Wide Operating Voltage Range'" Va;(opr.)=2V-6V
• Pin and Function Compatible with 74LS670
1.~
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
15 01
04 3
14 WA
RB 4
04 6
13 WB
WRITE
12 ENABLE
11 R~
ENABLE.
03 7
10 01
ONO 8
9
(TOP VIEW)
WA
WB
RA
RB
WE
RE
01
02
03
Q4
He-S39
16 Vee
03 2
RA 6
IEC LOGIC SYMBOL
01
02
03
04
02
02
TC74HC670AP/AF---------------------------------
TRUTH TABLE
WRITE FUNCTION TABLE
WRITE INPUTS
WB WA WE
L
L
L
L
H
L
H
L
L
H
H
L
X
H
X
NOTES 1. X :
0
O=D
00
00
00
00
DON~T
READ FUNCTION TABLE
WORDS
2
00
00
O-D
00
00
O=D
00
00
00
00
1
CARE
3
00
00
00
O=D
00
READ INPUTS
RB
RA
RE
L
L
L
L
H
L
L
L
H
H
H
L
X
H
X
01
WOB1
W1B1
W2B1
W3B1
Z
OUTPUTS
02
03
WOB2 WOB3
W1B2 W1B3
W2B2 W2B3
W3B2 W3B3
Z
Z
04
WOB4
W1B4
W2B4
W3B4
Z
Z : HIGH IMPEDANCE
2. (O=D)=THE FOUR SELECTED INTERNAL FLIP-FLOP OUTPUTS WILL .ASSUME THE
STATES APPLIED TO THE FOUR EXTERNAL DATA INPUTS.
3. OO=THE LEVEL OF a BEFORE THE INDICATED INPUT CONDITIONS WERE ESTABLISHED.
4. WOB1=THE FIRST BIT OF WORD O.etc.
BLOCK DIAGRAM
WRITE ENABLE
READ ENABLE
LATCH
4-WORD
x4-BIT
DATA
IN
ADDRESS IN
(2-BIT)
ADDRESS
SELECT
DECODER
ADDRESS IN
(2-BIT)
HC-640
3-STATE
BUFFER
DATA
OUT
r0
-I
D1
I~
>
G)
:n
L_
D2
D3
:r:
0,
(")
::t
D4
D
JCK
-~
~
or
10
CK
rl CK
I~
I
rlCK
-~---.
I--THE
SAME
I-
~
~
01
JD
AS
THE
SAME
-1lTI
I
AS
Q2
ABOVE
ABOVE
03
--rrn
rTHE
SAME
AS
ABOVE
04
-I
o
~
oIiIo
::t
o
0)
~
WA
WB
WE
RB
RA
11
o
RE
"tJ
~
.....
~
"
TC74HC670AP/AF--------------------------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI"
Voor
11K
10<
ICX;T
lee
Po
Tatg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP)./180(SOIC)
-65 -ISO
300
*50QmW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI;';
VCX;T
Topr
UNIT
V
V
V
"C
VALUE
2-6
o -Vee
o -Vee
-40 ....... 85
o- 1000(Vee -2.0V)
0- 500 (Vee=4.5V)
0- 400(Vee=6.0V)
tr • tr
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Val
Low-Level
Output Voltage
Va.
3-State Output
OCf-State Current
Input Leakage Current
1(1:
Quiescent Supply Current
II"
lee
TEST CONDITION
VI" =
VlliorVIL
VI" =
VlllorV1L
Ial =-20J,t A
Ial --4 rnA
Ial =-5. 2mA
Ia. =20 J,tA
Ia. -4 rnA
Ia. =5.2mA
VI;'; =VIH or VIL
Vo..T =Vee or GND
VI" -Vee or GND
VI;'; -Vee or GND
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. ·MIN .• MAX.
1. 5.
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.4
4.5
V
5.9
6.0
5.9
4. 18
4.31
4.13
5.68
5.80
5.63
0.0
0.1
0.1
0.0
0.1
0.1
V
0.1
0.0
0.1
0.17
0.26
0.33
0; 18
0.26
0.33
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
MIN.
1.5
3.15
4.2
6.0
-
6.0
6.0
HC-642
-
-
-
-
-
I
I
-
-
±0.5
±0.1
4.0
-
±5.0
±1.0
40.0
J,tA
----------------TC74HC670APIAF
TIMING REQUIREMENTS(lnput tr =tf=6ns)
Ta--40 -85"C
Ta-25"C
UNIT
TYP.
LIMIT
LIMIT
2.0
75
95
Minimum Pulse Width
4.5
t\\'(L)
15
19
(WE)
6.0
13
16
2.0
50
65
Minimum Set-up Time
4.5
t s
10
13
(Dn-WE)
6.0
9
11
2.0
0
0
Minimum Set-up Time
4.5
0
0
t s
(WA.WB-WE)
6.0
0
0
ns
2.0
5
5
Minimum Hold Time
4.5
5
5
th
(Dn-WE)
5
5
6.0
2.0
0
0
Minimum Hold Time
th
4.5
0
0
(WA.WB-WE)
6.0
0
0
2.0
75
95
Minimum Latch Time
Note(l)
tlatch
4.5
19
15
(WE-RA.RB)
6.0
13
16
Note(l):tlatch is the time allowed for the internal output of the latch to assume the state of new data.
This is important only when attempting to read from a loction immediately after that location
has received new data:
PARAMETER
SYMBOL TEST CONDITION
Vee
AC ELECTRICAL CHARACTERISTICS(C L =16pF.Vcc=6V.Ta=26"C)
PARAMETER
SYMBOL
Output Transition Time
tTUi
tTHL
tpLH
tpHL
tpUi
Propagation Delay Time
(RA.AB-Qn)
Propagation Delay Time
(WE-Qn)
Propagation Delay Time
(Dn-Qn)
3-State Output
Enable Time
3-State Output
Disable Time
TEST CONDITION
t~HL
tpLH
toHL
tpZL
tdlH
tpLH
tpHl
MIN.
TYP.
MAX.
-
4
8
-
23
34
-
24
38
-
22
32
ns
RL
=1 k Q
-
11
18
RL
=1 k Q
-
11
15
HC-643
UNIT
TC74HC670AP/AF--------------------------------
AC ELECTRICAL CHARACTERISTICS(CL =50pF,lnput t r =tf=6ns)
'l~a-25"(;
Ta--40 -85"(;
UNIT
TYP. MAX. MIN. MAx.
30
75
95
tTI.H
Output Transition Time
8
15
19
tTl-II.
7
13
16
90
195
245
Propagation Delay Time
tpLH
27
39
49
(RA.AB-Qn)
tpfil.
22
33
42
220
95
275
Propagation Delay Time
tpLH
28
44
55
(WE-Qn)
tPllL
22
37
47
ns
185
230
90
Propagation Delay Time
tpLH
26
37
46
(Dn-Qn)
tpflL
39
20
31
140
46
110
tpZH
RL=lkQ
Output Enable time
22
28
14
tpZL
24
12
19
120
25
95
tpLZ
RL=lkQ
Output Disable time
24
14
19
tpHZ
20
12
16
Input Capacitance
Cf:,
10
5
10
pF
Output Capacitance
COLT
10
Power Dissipation Capacitance CPD(l)
101
Note (1) C ro is defined as the value of the internal equivalent capacitance which is calculated Crom the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iex;q,o=Cro • Va;. fN +Ia:: /8(per bit)
PARAMETER
SYMBOL TEST CONDITION
Vex;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6 0
2.0
4.5
6 0
HC-64.4
MIN.
-
------TC74HC688AP/AF
8-BIT eQUALITY COMPARATOR
The TC74HC688A is a high speed cmos 8-BIT
EQUALITY COMPARATOR fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HC688A compares two 8-bit binary or BCD
words applied inputs Po -Pi. and inputs QO-Qi. and
indicates whether or not they are equal.
A signal active low enable is provided to facilitate
cascading of several packages to compare of words
greater than 8 bits
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .......•.•..•... , ............. tJXI =17ns(typ.)at Vee=5V
• Low Power Dissipation .•..•.•.•..• lee=4/l A(Max. )at Ta=25"C
• High Noise Immunity··············· V1\IH =V:\IL28% Vee (Min.)
• Output Drive Capability······ ...... 10 LSTTL Loads
• Symmetrical Output Impedance ... IIOH I=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH '" tpHL
• Wide Operating Voltage Range ... Vee (opr.)=2V-6V
• Pin and Function Compatible with 74LS688
20
1
P(DIP20-P-300A)
oo~
1
F(SOP20-P-300)
PIN ASSIGNMENT
G
20 Vee
PO 2
19 P=Q
18 Q7
QO 3
Ql 5
17 P7
16 Q6
PI 4
P2 6
15 P6
Q2 7
14 Q5
P3 8
13 P6
Q3 9
12 Q4
GND 10
11 P4
(TOP VIEW)
TRUTH TABLE
INPUTS
OUTPUT
P,O
G
P=O
P=O
L
L
P",O
L
H
X
H
H
X : Don't care
HC-645
TC74HC688AP/AF-------------------------------SYSTEM DIAGRAM
G
PO
Q7
00
,P7
P1
08
01
P8
P2
06
02
P6
P3
04
03
P4
p=o
IEC LOGIC SYMBOL
P
P=Q
7
o
Q
HC-646
(19) P=Q
--------------------------------TC74HC688AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature IOsec
VALUE
-0.5-7
-0.5 -V(:c+0.5
-0.5 - Vee+0.5
±20
±20
±25
±50
500(DIP)*1180(MFP)
-65 -150
300
SYMBOL
Vee
VI:-.:
VOLI
11K
I(J\
IOl.T
Icc
PD
Tslg
TI.
UNIT
V
V·
V
mA
mA
mA
mA
mW
"C
"C
.500m W in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'Ca derating factor ~f
-IOmW/'C shall be applied
unti1300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Suppl~' Voltage
Input Voltage
Output Voltage
Operating Temperature
VALUE
2-6
o-Vee
o -Vee
-40 - 85
o - 1000(V(:e=2.0V)
0- 500(Vee =4.5V)
o- 400(Vcc=6.0V)
SYMBOL
f-=----7
Vee
VI:-.:
VOLT
Topr
I--"- -
Input Rise ar..d Fall Time
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
High-Level
Input Voltage
Lo\\'-Level
Input Voltage
High-Level
Output Voltage
TEST CONDITION
VIII
I
VII.
II
I
VeJI
I
VI:-':=
VII10rVIL
I
I
Low-Level
Output Voltage
Input Leakage CUlTent
Quiescent Supply Current
VI:-':=
VlllorVIL
Vex.
i
1 1:-,:
I
I lee ,
V 1:-':
V 1:-':
1m =-20p.A
lUI - 4 mA
Inl =-5. 2mA
I
IOL =20 p. A
lex. -4 mA
I(x. =5.2mA
-Vee or GND
-Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
He-547
1'a-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
5.9
6.0
4.31
4.13
4.18
5.68
5.63
5.80
0.1
0.1
0.0
0.1
0.1
0.0
V
O. I
0.0
0.1
0.17
0.33
0.26 I 0.33
0.18
0.26 i ±1.0 p.A
±0.1 I
40.0
4.0
i -
MIN.
1.5
3.15
4.2
- I
TC74HC688AP/AF---------------------------------
AC ELECTRICAL CHARACTERISTICS(C L =15pF,Vcc =5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tn.1i
tnl\'
t",.11
Propagation Delay Time
_{Pn,Qn- P=Q)
Propagation Delay Time
(G-P=Q)
TEST CONDITION
~I\'
t",.11
tuHl.
MIN.
TYP.
MAX.
-
4
8
-
17
29
-
10
18
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =tf=6ns)
. Ta-25"C
1 Ta- 40 -85"C
UNIT
PARAMETER
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. I MIN. MAX.
95
75
30
2.0
trw
I 4.5
Output Transition Time
19
8
15
tTllL
6.0
7
16
13
2.0
215
60
170 ~
Propagation Delay Time
tpLiI
4.5
ns
43
21
34 I (Pn, Qn-P=Q)
tpHL
6.0
17
29 1 37
2.0
140
40
110
Propagation Delay Time
tpLH
28
4.5
22
13
(G-P=Q)
t"';L
24
6 0
10
19 I Input Capacitance
C['\
10
5
10 I
pF
Power Dissipation Capacitance CpDUl
I
32
Note(l) Cm is defined as the value of the Internal equ1valent capacitance which 1S calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCQ:>ol=C PD· VOC· f 1:\+1 OC
I
-
I
I
I
HC-648
TC74HC690AP/AF· TC74HC691AP/AF
TC74HC692AP/ AF· TC74HC693AP/AF
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER WITH OUTPUT REGISTER
(MULTIPLEXED 3-STATE OUTPUTS)
TC74HC690API AF DECADE, ASYNCHRONOUS CLEAR
TC74HC691AP/AF BINARY, ASYNCHRONOUS CLEAR
TC74HC692AP/AF DECADE, SYNCHRONOUS CLEAR
TC74HC693AP/AF BINARY, SYNCHRONOUS CLE~A.;..:,R..:--_ _ _ _ _ _ _---,
The TC74HC690A -693A are high speed CMOS
COUNTERIREGISTERS fabricated with silicon gate
C2MOS technology.
They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power
dissipation.
The 690Al692A are BCD DECADE COUNTERS, and
the 69W693A are 4-BIT BINARY COUNTERS. These
devices have output registers.
If the LOAD input is held low, the data inputs (A-D)
are loaded into an internal counter on the positive edge of
counter clock (CCK). In the counter mode, the internal
counter counts up on the positive edge of counter clock.
Counter clear input (CCLR) is active low. The counter
clear function of the 692A1693A is synchronous to CCK,
while the 690Al691A are cleared asynchronously.
The internal counter's output is stored in the output
register on the positive edge of register clock (RCK).
Register clear input (RCLR) is active low. The register
clear function of the 692A1693A is synchronous to RCK,
while the 690Al691A are cleared asynchronously. At this
point, the internal counter outputs do not change. The
outputs (QA -QD) are selected as intern.!!l counter outputs
or register outputs by output select (RIC).
Two enable inputs (ENT and ENP) and carry output
(RCO) are provided to enable easy cascading of counters
without using external gates.
All inputs are equipped with protection circuits
against static discharge or transient excess voltage.
FEATURES:
• High Speed ................................. fMAX=63MHz(Typ.)at Vcc=5V
• Low Power Dissipation ............... Icc=4pA(Max.)at Ta=25"C
• High Noise Immunity .................. \Nnr-\NIL=28" Vcc(Min.)
• Output Drive Capability ............... 15 LSTTL Loads For QA ...QD
10 LSTTL Loads For ReO
• Symmetrical Output Impedance ...... I10H I=IOL=6mA(Min.)
ForQA ...QH
I 10HI =10L=4mA(Min.)
For ReO
• Balanced Propagation Delays '" tpLH'" tpHL
• Wide Operating Voltage Range ...... Vcc(opr)=2V -6V
• Pin and Function Compatible with 74LS690-693
HC-649
20
1
P(DIP20-P-300A)
ro~
1
F(SOP20-P-300)
PIN ASSIGNMENT
CCLR
1
20
Vee
CCK
2
19
RCO
A
3
18 OA
8
4
17 08
C
5
16
OC
D
6
15
OD
ENP
7
14
ENT
FiCI.R 8
13
LOAD
RCK
9
12
G
GND
10
11
Ric
(TOP VIEW)
TC74Hca90AP/AF·TC74Hca91AP/AF
TC74HCa92AP/AF·TC74HCa93AP/AF
IEC LOGIC SYMBOL
TC74HC891A
TC74HC690A
G
G
MUX
RCK
1
LOAD
CCLR
LOAD
ENT
ENP
CCK
ENT
ENP
CCK
A
C
D
1
A
B
C
D
OA
OB
OC
OD
B
G
TC74HC693A
G
MUX
RIC
RCiJi
RCK
1
CCiJi
C
D
MUX
1
LOAD
ENT
ENP
CCK
B
1
RIC
RCLR
RCK
LOAD
A
OA
OB
OC
OD
8
TC74HC692A
CCiJi
MUX
R~~~
RIC
RCiJi
RCK
CCiJi
1
ENT
ENP
ccit
A
B
C
D
OA
OB
OC
OD
HC-650
[1]
•
OA
OB
OC
OD
_ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC690AP/AF·TC74HC691AP/AF
TC74HC692AP I AF· TC7 4HC693AP I AF
CClR lOAD
X
L
H
X
X
L
H
H
H
H
X
H
H
H
X
X
X
X
X
X
ENP
INPUTS
690A/691A
ENT RClR CCK RCK
X
X
X
X
X
X
X
L
X
H
X
X
X
X
L
H
X
X
X
X
X
X
H
H
X
X
X
X
J
J
J
J
X
1-
X
L
X
X
X
X
OUTPUTS
692A/693A
CCK RCK RIC
X
X
X
X
J
J
J
J
J
X
X
X
X
X
X
X
X
L
G
H
X
L
X
L
L
X
X
L
L
L
H
L
L
L
L
L
L
X
X
1-
X
X
J
X
J
J
1-
X
1-
H
H
FUNCTION
QA
QB
QC
CD
Z
L
a
Z
L
b
Z
L
c
Z
L
d
NO CHANGE
COUNT UP
NO CHANGE
L
L
L
a'
b'
c'
NO CHANGE
L
d'
HIGH IMPEDANCE
COUNTER CLEAR
LOAD DATA
COUNT DISABLE
NO CHANGE
COUNT UP
NO COUNT
REGISTER CLEAR
LOAD REGISTER
NO CHANGE
X : DON'T CARE
Z : High Impedance
a - d : The level of steady state input voltage at inputs A - D respectively.
a' - d' :The level of internal counter outputs respectly .before the most recent postive edge of the register clock.
HC690A/692A ; RCO=QA • QD • ENT
HC691A/693A ; RCO=QA • QB. QC. QD. ENT
CCK
L'OAo
CC'i:'R
RCK
R'Ci:R
Ric
13
A
8
3
4
DATA
C
D
ENP
18
4-81T
REGISTER
5
4-81T
COUNTER
OA
OUTPUT
17
8UFFER
08
(3-STATE)
1. OC
8
15
OD
~----------------------------------RCO
ENT
HC-651
TC74HC690APIAF·TC74HC691APIAF _ _ _ _ _ _ _ _ _ _- - TC74HC692APIAF·TC74HC693APIAF
TIMING
CHART (TC74HC690A/692A ; DECADE COUNTER)
~~~----------------------------------------rOAD----+-.....,
A
8
DATA
INPUTS
C
o
CCK
ENP
ENT
RIC
RCK
iiCtR
G
OA
08
OUTPUTS
OC
00
RCO
234
•
.•
PRESET
SYNC. CLEAR(I82A)
SYNC. CLEAR(I82A)
SYNC. CLEAR(I8OA)
SYNC. CLEAR(880A)
HIGH
IMPEDANCE
COUNTER OUTPUT
HC-652
REGISTER OUTPUT
COUNTER
OUTPUT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC690AP/AF·TC74HC691AP/AF
TC74HC692AP/AF·TC74HC693AP/AF
TIMING
CHART (TC74HC691A1693A; BINARY COUNTER)
ENP
ENT
RIC
RCK
RCLii
G
QA
Qa
OUTPUTS
QC
QD
RCD
13
14
1&
0
2
&
I
PRESET
SYNC. CLEAR(lnA)
SYNC. CLEAR(lnA)
SYNC. CLEAR(111A)
SYNC. CLEAR(111A)
HIGH
IMPEDANCE
COUNTER OUTPUT
HC-653
REGISTER OUTPUT
COUNTER
OUTPUT
TC74HC690API AF· TC7 4HC691AP I AF
TC74HC692AP/AF·TC74HC693AP/AF - - - - - - - - - - - - SYSTEM
DIAGRAM
TC74HC690A/TC74HC692A
CCK
C'Ci:ii
1
RCK
R/C~~
-
-
{ HC.80A ••••.• ASYNCHRONOUS CLEAR
HC882A.. •• .. SYNCHRONOUS CLEAR
L{)o-RC
HC-654
_ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC690AP/AF·TC74HC691AP/AF
TC7 4HC692AP I AF· TC7 4HC693AP I AF
SYSTEM
DIAGRAM
TC74HC691A/TC74HC693A
ENT
ENP
P,--+E
E
)---------t------+L
r
R/C~~
-
-
L..{>o-- RC
{ HC691A ...... ASYSCHRONOUS CLEAR
HC693A······SYSCHRONOUS CLEAR
HC-655
TC74HC690AP/AF·TC74HC691AP/AF _ _ _ _ _ _ _ _ _ _ _- TC7 4HC692API AF· TC74HC693API AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Supply Voltage Range
Vee
DC Input Voltage
VIN
DC Output Voltage
VOUT
Input Diode Current
11K
Output Diode Current
10K
(RCO)
DC Output Current (QA-QH) lour
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
lee
PD
Tstg
TL
UNIT
V
V
V
mA
mA
VALUE
-0.5-7
-0.5 --Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±35
±75
500(DIP)./180(SOIC)
-65 -150
300
*500mW in the range of Ta=
-40'0- 65"C. From Ta=65"C
to 85"C a derating factor of
-IOmW/"C shall be applied
until 300mW.
mA
mA
mW
-C
-C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Vee
VIN
Voor
Topr
Input Rise and Fall Time
tr • tr
UNIT
V
V
V
-C
VALUE
.2-6
O-Vee
O-Vee
-40 - 85
o-- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
0- 400(Vee=6.0V)
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
High-Level
Input Voltage
Low-Level
Input Voltage
High-Level
Output Voltage
SYMBOL
TEST CONDITION
VIH
VIL
VI!I/=
VIHorVIL
VOH
IQl
RCO ICli
ICli
~-QH
1m
VIN =
VIHorVIL
Low-Level
Output Voltage
Vex.
3 -State Output
orr-State Current
Ia:
Input Leakage Cumnt
Quiescent Supply Currmt
11:\
lee
lei! =-20p.A
- 4 mA
=-5.2mA
=-6 mA
=-7 8mA
lex. =20 p. A
lex. =4 mA
IOL=5.2mA
Iex.=6 mA
QA-QH Iex.=7 8mA
V IN =V IH or VIL
Voor =Vee or GND
VI!\! =Vee or UNlJ
VIN -'Vee Or GND
RCO
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
4.5
60
2.0
4.5
6.0
4.5
6.0
4.5
60
6.0
6.0
-
He-656
MIN.
1.5
3.15
4.2
-
1.9
4.4
5.9
4.18
5.68
4.18
5 68
-
-
I '1'a--40 -85-C
Ta=25"C
UNIT
TYt'. MAx. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1.35
1. 35
1.8
1.8
l.9
2.0
4.4
4.5
5.9
6.0
V
4.31
4.13
5.80
5.63
4.31
4.31
5 63
5 80
0.1
0.0
0.1
0.1
0.1
0.0
0.1
0.1
0.0
V
0.33
0.26
0.17
0.33
0.26
0.18
0.26
0.33
0.17
o 18 o 26
o 33
±0.5
±5.0
p.A
+0.1
±1.0
4.0
40.0
-
-
-
-
-
-
-
-
-
_ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC690AP/AF·TC74HC691AP/AF
TC7 4HC692AP I AF· TC7 4HC693AP I AF
TIMING REQUIREMENTS(lnput t r =t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CK)
tW(H)
tW(L)
Minimum Pulse Width
(CCLR,RCLR) *
tW(L)
Minimum Set-up Time
(CCLR,RCLR) **
ts
Minimum Set-up Time
(LOAD.ENT,ENP)
ts
Minimum Set-up Time
(A,B,C,D)
ts
Minimum Set-up Time
(CCK-RCK)
ts
Minimum Hold Time
tb
Minimum Removal Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6 0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
trem
*
Clock Frequency
Vee
f
Ta- 40 -85°C
UNIT
LJ..MIT
95
19
15
95
19
15
125
25
20
190
38
25
ns
155
31
25
155
31
25
0
0
0
65
13
10
3.5
MHz
18
21
Ta-25°C
TYp.
LIM~T
75
15
12
75
15
12
100
20
16
150
30
24
125
25
20
125
25
20
0
0
0
50
10
8
4
22
26
-
-
-
AC ELECTRICAL CHARACTERISTlCS(CL=16pF.Vcc=6V.Ta=26°C)
PARAMETER
SYMBOL
Output Transition Time
(RCO)
Propagation Delay Time
(CCK-RCO)
Propagation Delay Time
(ENT-RCO)
Propaga8on Delay Time
(C LR-RCO) *
Ylaximum Clock Frequency
tTU-I
tTHT
tpLH
toHI
tpLH
toHL
-
4
8
18
32
8
15
tpLH
-
19
34
fMAX
24
58
-
TEST CONDITION
*: for TC74HC690A/691A only
** : for TC74HC692A/693A only
He-657
MIN.
TYP.
MAX.
UNIT
ns
IMHz
TC74HC690AP/AF·TC74HC691AP/AF _ _ _ _ _ _ _ _ _ _ _ __
TC74HC692AP/AF·TC74HC693AP/AF
AC ELECTRICAL CHARACTERISTICS(CL=50pF,lnput t r =tf=6ns)
T,I!;t)T
PARAMETER
SYMBOL
Output Transition Time
(Q)
t1U!
tTIiL
50
Output Transition Time
(RCO)
t1U!
tTIiL
50
Propagation Delay Time
(CCK-Q)
tpLH
tpHL
CONDITION CL
50
150
50
Propagation Delay Time
(RCK-Q)
tpLH
tpHL
150
PropagationJlelay Time
(R/C-Q)
50
tpLH
tpHL
150
Propagation Delay Time
(CCLR-Q)*
50
tpHL
150
50
Propagation Delay Time
(RCLR-Q)*
tpHL
150
Propagation Delay Time
(CCK-RCO)
tpLH
tpHL
50
Propagation Delay Time
(ENT-RCO)
tpLH
tpHL
50
Propagatioa:Delay Time
(CCL -RCO)*
tPHL
50
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
60
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
60
2.0
4.5
60
2.0
4.5
6.0
2.0
4.5
60
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
60
2.0
4.5
60
*: for TC74HC160A/160A only
HC-658
MIN.
-
-
.-
--
-
-
Ta--40 -85"C UNIT
Ta 25"C
Tl!'o MAX. MIN. MAx.
75
25
60
12
15
7
13
10
6
95
75
30
19
15
8
16
7
13
270
215
84
54
27
43
43
34
22
320
255
99
64
32
51
51
26
41
270
215
84
54
28
43
43
22
34
320
255
99
51
64
33
51
26
41
215'63
170
21
34
43
17
27
A
210
265
78
ns
42
53
26
34
42
21
250
315
93
50
63
31
25
40
50
290
365
108
58
73
36
29
46
58
250
315
90
30
50
63
24
40
50
290
365
105
35
58
73
28
58
46
230
72
185
23
37
46
37
19
30
120
36
95
12
19
24
19
10
15
75
245
195
25
49
39
39
20
31
---
-
-
-
_ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC690AP/AF·TC74HC691AP/AF
TC74HC692AP I AF· TC7 4HC693API AF
AC ELECTRICAL CHARACTERISTICS(CL=60pF,lnput tr=tf=6ns)
PARAMETER
SYMBOL
50
Output EI,!!-ble time
(G-Q)
tpZL
tpZH
RL =lkQ
150
Output
D~able
(G-Q)
time
tplZ
tPHZ
Maximum Ciock Frequency
fMAX
Input Capacitance
Output Capacitance
Power Dissioation Caoacitance
CIN
Caur
RL =lkQ
Ta
'l'a-25"C
Tl!Il:lT
CONDITION CL
50
50
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
60
MIN.
-
-
-
4
22
26
-
cpom
TYP.
MAX.
48
16
13
63
21
17
34
18
14
17
52
65
5
13
63
120
24
19
160
32
26
145
29
23
10
-
40 -85"C UNIT
MlN.MAx..
-
-
3.5
18
21
-
150
30
24
200
40
32
180
36
29
10
-
ns
MHz
Note (1) C R> is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCtpl=C R> • Va;' fIN +Ia;
He-65g
pF
NOTES
_______________ TC74HC696P
TC74HC697P
TC74HC696P
TC74HC697P
U/D DECADE COUNTER/REGISTER (3-STATE)
U/D 4-BIT BINARY COUNTER/REGISTER (3-STATE)
The TC74HC696/697 are high speed CMOS up/down counters fabricated with silicon
gate C2MOS technology. They achieve the high speed operation similar to equivalent
LSTTL while maintainin~ the CMOS low power dissipation. TC74HC696 is BCD DECADE
COUNTER, and TC74HC697 is 4-BIT BINARY COUNTER. Both devices have registers respectively. They count at positive edge of counter clock input (CCK) when selected at
"Counter Mode". If input uID is held "H", internal counter counts up, and held "L",
counts down. Internal counter's outputs are memoried in output register at positive
edge of register clock (RCK). . The outputs (QA'" QD) are selected internal counter
outputs or register outputs respectively by output select input (R/~. Their clear
func.tion are cleared asynchronously to clock. Al1 inputs are equipped with protection
circuits against static discharge or transient excess voltage.
FEATURES
• High Speed ••••••••••••••• f MAX=33MHz(Max.) at VCC=5V
• Low Power Dissipation •••••• ICC=4~A(Max.) at Ta=25°C
• High Noise Immunity ••••••••• VNIH=VNIL=28% VcC---_;================~--__,
A
ItB
B
'
1
THE SAME
AS
ABOVE
I
1 16 no
..
L _____ -'
C
5
-------,
THE SAME
AS ABOVE
1 15
1 - - ltD
______ ...1
_6
D-~6~~--------~~=======-~~-----l------~
~
ji
~
W'D
iiiP
.,
j;
~
LOAD
13
gNT
14.
is
HC-664
____~~---------------------------TC74HC696P
TC74HC697P
TIMING CHART
TC74HC696
LJ
A
B
/I{I/IIA
VI////////T/ZT/Tl/flIIIIIIllIZTl/I//////Z
V///lflfl/TIIIZ//fl/ / /I/Il///flIl//l/VIZ
I
C
WillA
I
D
Vl////7flfl//flfl//I/II/////lT////IT/lI/Z
7/T1!21
1
CCK
________________~r--l~__________________
~____________~r-l~~__________________
~
ENP
ENT
RCK
-+____~--~n~------~--~~rtJl~-----1
1
1
,
I
Q.A
I
1
-iL-_---'~I--""---!r--+----Ll-1 b:z: z
1
Q.B
--t-_ _
~/Tl
I
Q.C
Q.D
1
17 : ~ 7/
I
1
~
~--~1Tl~------------~----~--------~~~·~:~;~;~2
1
-1L-__
-+--r'--II
I
Vz:z:
:2
I
"
J.i
I
1
RCO
1. 1 /
1 1
1
17 I
COUNT OF) I
( INTERNAL I
COUNTER
1
,
~
l
CLEAR
L--.J
8
9
0
1
2
1
1
1
I
I
1
LJ
o
9
I
8
1 7
6
I
COUNT UP
I
1
PRESET''-I'~----"-=-=~=------I-"I
INHIBIT
,I
I
1
HIGH IMPEDANCE
1-'....,..,C=O.=UN=T-"D=OW=N--'-_ _ _ __
I
,...I_-=-IN=H=IB=I-=-T....
'
,
I
_ _ _ _-----'C~O~UNTER
OUTPU_T
-----r;.
HC-665
.:cR=EG=I=ST=ER~OU"_=_T~PU"_!,T.~QO=U~NT=ER~OU"-'T~PU"-!.-T
TC74HC696P
TC74HC697P--------------------~------~--~
TUlING CHART
1
LOAD
TC74HC697
L-J
VI/ITIT/Z pol; ;CfJiE U(N~I~ toe ~o~s :ujw ZZ/J/JZZ/Z
VllTllflT/I/lJT/Z/T/////Z7J/JTJZZZ2/Z
VIm//lJ'//Z//17/I///T/ZZ//J77I/1/J/Z
1 ~I
________________~11
I
1
1
I
11
I·
I
I
-+____~~__~rl~~.------r---+-~~
I
rul
I
I
I
I
I
I
I
~---~
Lh
1
I
I
1 1
(COUNT 01')
INTERNAL
COUNTER
1~
1
•
OLEAR
1l4.
LJ
lI5
0
I
2
~!!~
0
15
I
COUNT UP
I
1
I
1
PRESET
LJ
I
1
1 I
...
~:~LZ
I
~:~2U
I
E2~
I !ZJ', 27,
I
ROO
I
·1
I I
11--INHIBIT I
·1_
I
I
I
I
14
COUNT DOWN
13
I
12
1
I
I HIGH
I
: Z2
.IMPEDANCE
I
I
_ _ _ _--=.O=OU:..::Nc.:..T=ER::...-=.;OU:<.:Tc.:..P:::...:UT'--_ _ _~.I;...;
..RE==GI=ST=ER:.:...=OU=T~:Q!!NTER OUTPUT
1
I
He-666
_ _ _ _ _ _ _ _ _ _ _ _ _.....;.._ _ _'TC74HC696P
TC74HC697P
AC ELECTRICAL CHARACTERISTICS
r
PARAMETER
SYMBOL
Output Transition Time
tTLH
(Q)
tTLH
Propagation Delay Time
(CCK - Q)
tpLH
Propagation Delay Time
tpLH
tpHL
Propagation Delay Time
(Ric - Q)
tpLH
tpHL
Propagation Delay Time
(ENT - RCO)
tpLH
tpHL
Propagation Delay Time
(CCLR - Q)
tpHL
Propagation Delay Time
(CCLR - RCO)
tpHL
Maximum Clock Frequency
fMAX
(CCK, RCK)
Minimum Pulse Width
(CCLR)
-
-
tpHL
tpLH
tpHL
-
-
-
tw(H)
tw(L)
-
tw(L)
-
Minimum Removal Time
(CCLR)
Minimum Set-up Time
(LOAD, ENP, ENT)
Ta=25°C
VCC MIN.' TYP.
25
2.0
4.5
7
6
6.0
2.0
30
4.5
8
6.0
7
2.0
136
4.5
34
6.0
29
2.0
116
4.5
29
25
6.0
160
2.0
4.5
40
6.0
34
,..
2.0
100
4.5
25
21
6.0
2.0
- 116
4.5
29
6.0
25
2.0
148
4.5
37
6.0
31
172
2.0
43
4.5
6.0
37
2.0
4
8
4.5
20
30
6.0
24
35
2.0
30
4.5
8
6.0
7
2.0
30
4.5
8
6.0
7
2.0
4.5
6.0
2.0
96
24
4.5
20
6.0
r-
-
tTHL
Propagation Delay Time
(CCK - RCO)
Minimum Pulse Widht
-
tTHL
Output Transition Time
(RCO)
(RCK - Q)
,
TEST
CONDITION
t rem
ts
-
He-667
-
Ta=-4(}V85°C
UNIT
MIN. MAX.
60
75
15
12
10
13
75
95
15
19
16
13
325
260
65
52
44
55
280
225
56
45
48
38
305
380
61
76 ns
52
65
225
195
49
39
42
33
280
225
45
56
48
38
285
355
71
57
60
48
405
325
81
65
69
55
3
MHz
- 16
19
75
95
15
19
16
13
75
95
15
19
16 ns
13
5
5
5
5
5
5
225
280
56
45
48
38
MAX.
-
-
-
-
-
-
-
-
TC74HC696P _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....
TC74HC697P
INPUT and OUTPUT
EQUIVALENT CIRCUIT
RECOMMENDED OPERATING CONDITIONS
PARAMET~R
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
VCC
VIN
VOUT
Topr
tr,tf
LIMIT
2 'V 6
o 'V VCC
o 'V VCC
-40 'V 85
O'VIOOO (VCC=2. OV)
o 'V 500 (VCC=4. 5V)
o 'V 400(VCC=6.0V)
,
UNIT
Vee
-1
vee
V
I OUTPUT
t--+I -c:
I------VOH
Q.
RoO
F-------VOL
VOL
ICC(Opr.) TEST CIRCUIT
-__1'--
VOO=5V
QA
QB
QO
p.G.
QD
ROO
A
c:o
B
III
o
D
HC-671
TC74HC698P _ _ _- - - - TC74HC699P
TC74HC698P U/O
COUNTER/REGISTER (3-STATE)
OECAO~
TC74HC699P
U/O 4-BIT BINARY COUNTER/REGISTER (3-STATE
The TC74HC698/699 are high speed CMOS up/down counters fabricated with silicon
gate C2 MOStechno1ogy. They achieve the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation. TC74HC698 is BCD DECADE
COUNTER. and TC74HC699 is 4-BIT BINARY COUNTER. Both devices have registers respectively. They count at positive edge of counter clock input (CCK) when selected at
"Counter Mode". If input U/D is held "H". internal counter counts uP. and held "L".
counts down. Internal counter's outputs are memoried in output register at positive
edge of register clock (RCK). The outputs (QA '" QD) are selected internal counter
outputs or register outputs respectively by output select input (R/C). Their clear
function are cleared synchronously to clock. All inputs are equipped with protection
circuits against static discharge or transient excess voltage.
FEATURES
• High Speed •••••••••••••••••• fMAX=3lMHz(Max.) at VCC=SV
• Low Power Dissipation •••••••••
ICC=4~A(Max.)
at Ta=2SoC
• High Noise Immunit"y ••••••••••• VNIH=VNIL=28% VCC(Min.).----------------'
• Output Drive Capability ••••••• 10 LSTTL Loads (For RCO)
IS LSTTL Loads (For QA '" QD)
• Symmetrical Output Impedance ••••••• IIOHI=IOL=6rnA(Min.)
F6r QA '" QD Output
IIOHI=IOL=4rnA(Min.)For RCO Output
• Balanced Propagation Delays •••••••••••••••••• tpLH~tpHL
• Wide Operating Voltage Range •••••••••• Vcc(Opr.)=2V"'6V
• Pin and Function Compatible with LSTTL (74LS698/699)
ABSOLUTE MAXIMUM RATiNGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DIP20 (SD20AP)
SYMBOL
VCC
VIN
VOUT
IlK
VALUE
-O"S '" 7
-O.S "'VCc+O.S
-0. S '" VCc+O.S
±20
10K
±20
±3S (QA "'QD)
±2S (RCO)
±70
DC Output Current
lOUT
DC VCC/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10 sec
ICC
*
PD
Tstg
TL
SOO*
-6S '" ISO
300
UNIT
V
V
V
rnA
rnA
ASSIBN~lENT
rnA
rnA
mW
"c
·C
SOOmW in the range of Ta=-40°C '" 65°C and from Ta=6S·C
up to 8SoC derating factor of -lOmW/oC shall be applied.
until 300mW.
HC-672
PIN
(TOP VIEW)
__________________________________ TC74HC698P
TC74HC699P
TRUTH TABLE
OUTPUTS
INPUTS
LOAD
ENP
X
X
L
X
H
L
CCLR
ENT
CCK
X
X
X
X
X
S
X
X
IVa G
QA
QB
QC
FUNOTION
QD
U/'D
RCK
X
X
X
H
Z
Z
Z
Z
HIGH
x
x
X
L
L
L
L
L
L
CLEAR
X
L
L
a
b
c
d
LOAD OOUNTER
H
H
H
X
S
S
X
X
L
L
H
H
X
H
S
X
X
L
L
NO CHANGE
NO
IMPEDANCE
COUNTER
COUNT
H
H
L
L
S
H
X
L
L
COUNT UP
COUNT
H
H
L
L
S
L
X
L
L
COUNT DOWN
COUNT DOWN
H
X
X
X
L-
X
X
L
L
NO CHANGE
NO
X
X
X
X
X
X
S
H
L
X
-L
H
L
X
.X
X
X
X
a / ·,.
b'
c'
d'
NO CHANGE
UP
COUNT
'LOAD REGISTER
NO
LOAD
X: Don't care
Z: High Impedance
a'" d
The level of steady state inputs at inputs A through D respectively.
a' '" d ': The level of steady state outputs at internal counter outputs QA' through
QD' respectively.
RCO Function
TC74HC698
TC74HC699
m!-
RCO= (UP -.QA - QD - ENT + UP - QA ENT)
RCO=(UP-QA-QB-QC-QD-ENT + UP-QA-QB-QC-QD-ENT)
BLOCK DIAGRAM
LOAD CCK CCLR uh
RCK
(}
IVa
u
A
DATA
B
C
D
:5
18
4
1'7
Q,B
16
~C
15
Q,D
4-BIT
5
COUNTER
6
Q,A
19
ENT
L---------------------------------RCO
ENP
HC-673
TC74HC698P________________________________
~_
TC74HC699P
LOGIC QIAGRAM
G
TC74HC698
II
~~~~~==================~
ROK~9~>o--~~----------------------------~
Ocna~8~i>--~~----------------------------~
OOK~2~~__-C~--~----------------~
B
4.
D
r------l·
~
I THB 8AII.
CK
o
AS ABOV. I
'- _____ ...J
1e
~O
5
-------,
THB BAli.· 1 15
AB ABOV. ,--- ~D
______ ..J
"'>-______--=1~1I 1iiii
6
D
Q
41e
D
h
R ~
CltQ;
IV'D"
EIIP
LOAD
iiiT
7
1S
l4.
is
HC-674
TRUTH TABLB OF INTBRNAL F/1"
R
D
Cit
~
li)
L
X
S
L
B
H
HSH
H
L
S
L
H
H
X
L
L
HO OhaIlS_
__________________________________ TC74HC698P
TC74HC699P
LOGIC DIAGRAM TC74HC699
~~~~==================~
RO&~~)o--~~----------------------------~
OCK~~~~--t>~_t------------------,
II.B
B
4.
r-- ----I
I
CK
L
C
THB SAMB
AS
ABOVB
111
I
_ _ _ _ _ ,J
11.0
5
-------,
.-----l
D-~~~S_----_t~======--=-~
,,0
,,0---<"1 "')___
O
--------..;:1~9 liCo
TRUTH TABLE OF INTERNAL P~
ii
ii
t1,ID
D
C&Q;
.
j3
h
m
7
LiiAii"13
iiiT 140
R II.
~
i8
HC-675
R
D
C&
II.
l~)
L
X
S
L
iii
H
H
HSH
L
L
L
H
H
X
S
L.
No Change
TC74HC698P __------------------------------TC74HC699P
TIMING CHART
TC74HC698
~
LOAD
.fZ1Z17/
IIT/lftfl///1/1///
W/I!////lfl/////1lfl//J/ZIflZ;ZIZ////lff/l/Z
v/ff///J/////fl/2lJllfl/ft///Tlllfl/lT/I//J'/J
V/fl/J////I/J//fl//I/I//IT//fl/lfl////fl//fl//
A
a
VIZ/A
C
IjJfl//J
D
1fIJ'////1
DON'T OARE UNTIL LOAD ·OOES LOW
CCK
~
ENP
____________
~~r-l~
_________________
1
~------------~r-l~--r-----------------
ENT
iVo
OOK
----~~-7--------------~~--~
----T-~~----~rl~--------~--_+~I--~~--------, 1
I
1
:
QB
QC
QD
1
I
---T~fTl~--------~
1
I
I
I
I
~#27
__~:~~~~------------_.----~~--------~~~~~}~~~2~2
~
I
I
I
fZ:Va
1 I
1
I
I·
. COUNT OF
I
. I!iTERNAL COUNTERI
~I
17 1 8
A
9
0
1
II
I
1 I
2
1 I
1 I
1
.
LJ
A
I
COUNT UP
1~
..--....::c;.-=--:":'-~--"'1.1
I
CLEAR PRESET 1
INHIBIT
I
I
I
I
I•
-I
INHIBIT
1
I
~
0
9
8
7
6
I
I
l
..
I
HIGH IMPEDANCE
I
• I•
II
COUNT DOWN
1
COUNTER OUTPUT
HC-676
.;
REGISTER OUTPUT
j.
COUNTER OUTPUT
TC74HC698P
----------------------------------TC74HC699P
TIMIrlG CHART
TC74HC699
L--1
LOAD
VII///)
I7m41?ZDON'T CARE UNTIL LOADOOES
C
7/////A
711////1
VI/////flfl//II//////111///////////l////I//I/Z
V///Il/////1//1//7////1///1/11/////II1II//1//4
D
7//////1
Vlflfl////ff!l//J'T//ff/////////II/fl/////1/lIZ
A
B
Low7//IIff;7ffffA
{){)K
~
ENP
________
~r-l~
______________
~----------~r-l~~----------------_
ENT
,
RCK
n
---r--t--c---~
QA
I
!
1
QB!
I
QC
'_',--_I
nn
+--_-+I
LJ ,-+_____
L-_ _ _ _
I
:
IZ z/III
,
I
I
~~,-----,
I
I
I
I
I
4-1_ _ _- ,
L - -_ _ _ _~_ _~
12
, :z77/j
QD~!
,I
I
RCO
I 1
:
COUNT OF
INTERNAL COUNTER:
,:
~
CLEAR
'14.
13'
"
""
PRESET
LJ
15
0
1
COUNT UP
'
,
,
"
I
2
I
I
~I·--------------~.,
,1
INHIBIT
1
I
LJ
o
,
1
151
l ' : 13
I
12
I
.1
1 HIGH
IWPEDANCB
I
I
"
: INHIBIT
I..
I
~.lIEOI STER
COUNTER OUTPUT
HC-677
COUNT DOWN
I
OUTPUT:
COUNTER OUTPUT
TC74HC698P___________________________________
TC74HC699P
INPUT and. OUTPUT
EQUIVALENT CIRCUIT
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
VCC
VIN
VOUT
Topr
Input Rise and Fall Time
tr,tf
LIMIT
2",6
o"'VCC
o "'VCC
-40'" 85
0'1.1000 (VCC=2. OV)
o '" 500 (VCC..4. 5V)
0'" 400 (VCC=6. OV)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High.,.Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
TEST CONDITION
VIN=VIH
IOH=-20]JA
or VIL
High-Level
Output Voltage
VOH
QA"'QD
Output Voltage
VIN=VIH
or VIL
3-State Output
Off-State
Current
Input Leakage
Current
Quiescent
Supply Current
VOL
IOH=..,7.8mA
IOH=-4111A
I OH=-5.2mA
RCO
Low-Level
I OH=-6mA
I OL=20)JA
UNIT
V
°c
ns
-
MIN. TYP.
1.5
3.15 4.2
-
4.5
6.0
2.0
4.5
6'.0
4.18 4.31
5.68 5.80
0.0
0.0
- 0.0
- 0.17
0.18
QA"'QD
I OL =6mA
I OL =7.8mA
4.5
6.0
Rca
IOL=4mA
I OL=5.2mA
4.5
6.0
IOZ
VOUT"'VCC or GND
6.0
lIN
VIN=VCC or GND
6.0
ICC
VIN""VCC
~r
6.0
GND
HC-678
~a=-40"'85°C
Ta=25°C
VCC
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
-
-
-
1.9
4.4
5.9
4.18
5.68
2·9
4.5
6.0
4.31
5.80
-
-
-
-
MAX.
-
0.5
1.35
1.8
-
-
0.1
0.1
0.1
0.26
0.26
0.17 0.26
0.18 0.26
MIN.
1.5
3.15
4.2
MAX.
-
-
0.5
1.35
1.8
1.9
4.4
5.9
4.13
5.63
--
4.13
5.63
-
-
-
-
-
0.33
0.33
±5.0
±O.l
4.0
-
40.0
±0.5
-
V
0.1
0.1
0.1
0.33
0.33
-
-
UNIT
±l.0
)JA
TC74HC698P
---------------------------------TC74HC699P
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Output Transition Time
(Q)
Output Transition Time
TEST
CONDITION
CL=50pF)
Propagation Delay Time
(CCK - Q)
Propagation Delay Time
(RCK - Q)
Propagation Delay Time
(CCK - RCO)
Propagation Delay Time
Q)
Propagation Delay Time
(ENT - RCO)
Maximum Clock Frequency
(CCK, RCK)
Minimum Pulse Width
(CCK, RCK)
Minimum Set-up Time
(A, B, c, D)
Ta--40'V85°C
VCC
MIN.
TYP.
MAX.
MIN.
MAX.
tTLH
tTHL
2.0
4.5
6.0
-
25
7
6
60
12
10
-
75
15
-
13
tTLH
2.0
4.5
30
8
7
75
15
-
13
-
95
19
16
124
31
26
100
25
240
48
41
-
6.0
2.0
4.5
6.0
2.0
4.5
tpLH
tpHL
tpLH
tpHL
6.0
2.0
4.5
6.0
tpLH
tpHL
2.0
4.5
6.0
tpLH
tpHL
2.0
4.5
6.0
2.0
tpLH
tpHL
f MAX
4.5
6.0
2.0
4.5
tw(H)
tw(L)
6.0
2.0
4.5
6.0
Minimum Set-up Time
(LOAD, ENP, ENT)
Ta-25°C
r--
tTHL
(RCO)
(RIC -
SYMBOL
(tr~tf~6ns,
ts
2.0
4.5
6.0
ts
HC-679
-
-
-
195
39
-_.
21
144
36
31
33
275
92
23
175
35
30
190
38
32
3.5
18
21
7
28
33
44
-
-
20
96
24
20
55
47
-
-
9
100
20
17
84
21
18
200
40
34
16
4
3
50
10
9
11
-'
-
2.5
14
16
-
UNIT
300
60
51
245
49
42
345
69
59
ns
220
44
37
240
48
41
-
MHz
125
25
21
250
50
43
65
13
11
ns
TC74HC698P _____________________________________
TC74HC699P
AC ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
SYMBOL
Minimum Set-up Time
(CCLR)
Minimum Set-up Time
(U/D)
Minimum Set-up Time
(CCK - RCK)
Minimum Hold Time
TEST
CONDITION
ts
ts
ts
th
3-State Output
tpZL
Enable Time
tpZH
3-State Output
tpLZ
-
Ta=25°C
VCC
MIN.
2.0
4.5
6.0
-
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
Disable Time
tpHZ
Input Capacitance
CIN
Output Capacitance
CoUT
-
Power Dissipation
Capacitance
CpD (1
-
Note (1):
RL=lkSl
RL=lkfl
Ta=-40'l.85°C
TYP.
12
3
2.5
MAX.
MIN.
MAX.
SO
10
9
65
13
60
15
ISO
30
26
125
25
21
25
5
-
13
48
12
10
-
-
-
5
-
56
14
12
80
20
17
llO
22
19
145
2.9
25
-
5
10
10
ll3
-
- - -
UNIT
II
190
38
32
160
32
27
36
6
5
140
28
24
180
36
31
ns
10
-
pF
CPD is defined as the value of internal equivalent capacitance of Ie which is
calculated from the operating current consumption without load (refer to Test
Circuit).
Average operating current can be obtained by the equation hereunder.
Iee(Opr·)=CpD • Vec' fIN+Iee
He·680
_____________________________________ TC74HC698P
TC74HC699P
SWITCHING CHARACTERISTICS TEST WAVEFORM
6ns
6ns
6ns
r----::--::LI:,----"\
r--- Vee
A-D
\.-..""""''---'{ 11O'-,---..J ....- - - aND
eeK
Yee
eeK
aND
fleK
aND
6ns
6ns
Q
YOL
1"1<-_ _ _ aND
pHL
6ns
eeLR
6ns
- - Yee
GND
6ns
Lr':=--'
6ns
+---
Veo
i"l'----
aND
----vee
eeK
'----aND
HC-681
,----Ycc
eeK
---aND
TC74HC698P
TC74HC699P-.- - - - - - - - - - - - - - - - -
SWITCHING CHARACTERISTICS TEST WAVEFORM (Continued)
VOO
OaK
GND
6ns
6ns
VOO
C
Q
Q
GND
VOH
VOL
VOH
EiiT
1mP
Q
VOL
OaK
U
ROO
HC-682
GND
C
VOH
J
VOL
__________________________________TC74HC698P
TC74HC699P
ICC(Opr.) TEST CIRCUIT
- _ - VCC=5V
lvi)
QA
QB
QC
QD
P.O.~~---i
RCO
c:o
A
on
B
C
D
OND
HC-683
TC74HC4002AP I AF -------------.............
DUAL 4-INPUT NOR GATE
The TC74HC4002A is a high speed CMOS 4-INPUT NOR
GATE fabricated with sillicon gate C2MOS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
· The internal circuit is composed of 3 stages including a
buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIPI4-P-300)
FEATURES:
• High Speed ..•.................•......... tpd=10ns(Typ.)at Vc:c=5V·
1
F(SOPI4-P-300)
• Low Power Dissipation ............ 1c:c=lIlA(Max.)at Ta=25"C
• High Noise Immunity .... ·•·· .. ·· .. • Vl\:IH=V:\IL28" Vc:c(Min.)
• Output Drive Capability··· .. · ...•.. 10 LSTTL Loads
• Symmetrical Output Impedance .•. 1100 I=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpUj" tpHL
• Wide Operating Voltage Range ..• Vc:c(opr)=2V-6V
• Pin and Function Compatible with 4OO2B.
PIN ASSIGNMENT
IV
14 Vee
lA
2
13 2V
lB
3
12 2A
lC
4
11 2B
10
5
10 2C
NC
6
9 20
GNO 7
8 NC
(rOp VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
lA
(2)
>1
A
B
C
D
Y
H
X
X
X
L
X
H
X
X
L
X
X
H
X
L
(11)
X
X
X
H
L
(10)
L
L
L
L
H
1B
lC
10
tA
2B
2C
20
X : Don't Care
(9)
HC-684
---------------TC74HC4002AP/AF
ABSOLUTE MAxIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Gurrent
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+O.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
SYMBOL
Vee
VI:"
VOLT
11K
10K
100: r
lee
PD
Tstg
TI.
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40·C- 65·C. From Ta=65"C
to 85·C a derating factor of
-10m WI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
tr
,
UNIT
V
V
V
"C
V:ALUE
2-6
0- Vee
0- Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee=6.0V)
Vee
VIN
VOLT
Topr
tr
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VOH
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
lIN
lee
TEST CONDITION
Iw =-20/.LA
VI:" =
fr-.
VU-lOrVIL IOH --4 rnA
IOI-l =-5.2mA,
VI:" =
VUiorVIL
IOL =20 /.LA
IOL -4 rnA
IoJ. =5.2mA
VI:" -Vee or GND
VI:"" -Vee or GND
!
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
He-685
Ta-25°C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
l.5
V
3.15
4.2
0.5
"0.5
V
l. 35
l. 35
l.8
l.8
2.0
l.9
l.9
4.4
4.4
4.5
V
5.9
6.0
5.9
4.31
4.13
4.18
5.63
5.68
5.80
0.0
0.1
0.1
0.1
0.0
0.1
V
O. I
0.1
0.0
0.33
0.26
0.17
0.26
0.33
0.18
±0.1
±l.0
/.LA
l.0
10.0
MIN.
l.5
3.15
4.2
I
AC ELECTRICAL CHARACTERISTICS(C L =16pF,Vcc =6V,Ta=26"C.lnput t r =t,=6ns)
PARAMETER
SYMBOL
Output Transition Time
tTLIi
tTIIl.
tpLII
tpHi.
Propagation Delay Time
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
10
17
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =50pF,lnput t r =t,=6ns)
Ta-25"C
Ta--40 -85"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Va::: MIN. TYP. MAX. MIN. MAX.
75
2.0
30
95
tlLJj
Output Transition Time
4.5
8
15
19
t1liL
6.0
7
13
16
ns
2.0
40
100
125
tpLH
Propagation Delay Time
4.5
13
20
25
tP/iL
6.0
17
21
11
Input Capacitance
C,:-;
5
10
10
pF
Power Dissipation Capacitance Cpo(1)
22
Note (1) C F{) is defined as the: value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia:::q,o=C po. Va:. £,:-; +Ia::: 12(per Gate)
-
-
HC-686
-------TC74HC4017P/F
TC74HC4017P/F DECADE COUNTER/DIVIDER
The TC74HC 4017 is a high speed CMOS DECADE JOHNSON COUNTER fabricated with
silicon C2MOS technology. It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation. It contains 5-stage dividedby-lO Johnson counter with 10 decoded output (QO - QlO) and carry-out bit.
This counter is advanced on the positive edge of clock signal when CE input is held
low, or it is advanced on the negative edge of the clock enable signal (CE) when CLOCK
input is held high, and selected one of ten outputs goes high. Holding high the CLEAR
input, this counter is cleared to its zero state without regard to ~he other input
conditions.
.
All inputs are equipped with protection circuits against static discharge or transient
excess voltage.
FEATURES:
High Speed •••••.•••.•.•••. fMAx=45MHz(Typ.} at VCC=5V
Low Power Dissipation ••••••
ICC=4~A(Max.)
at Ta=25°C
• High Noise Immunity •••••••.• VNIH=VNIL=28% Vcc(Min.)
Output Drive Capability •••••.•.•.•..•• 10 LSTTL Loads
• Symmetrical Output Impedance .•••• !IOH!=IOL=4rnA(Min.)
Balanced Propagation Delays •..••.•••••••••
tpL~~tpHL
1
DIPI6(3DI6A-P)
• Wide Operating Voltage Range .•••••• VCC(opr. )=2V '" 6V
16~
Pin and Function Compatible with 40l7B
1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Vol~age Range
DC Input Voltage
DC Output Voltage
SYMBOL
VCC
VIN
VOUT
Input Diode Current
,..--Output Diode Current
11K
DC Output Current
DC VCc/Ground Current
Power Dissipation
lOUT
ICC
PD
Storage Temperature
Lead Temperature lOsec
Tstg
TL
10K
VALUE
-0.5", 7
-0.5", VCC+O. 5
~O . 5
'" VCC+O • 5
±20
±20
±25
:!:50
500(DIP)*
l80(MFP)
-65'" 150
300
UNIT
V
V
V
rnA
mA
rnA
mA
rnW
°c
°c
MFPI6(FI6GC-P)
PIN ASSIGNMENT
Q.5 1
l6 VCC
Q.l 2
15 CLEAR
Q.O 3
14 CLOCK
Q.2 4
13
BE
Q.6 5
12
CARRY
OUT
Q.7 6
11 Q.9
Q.3 7
10 Q.4
9
GND 8
* SOOrnW in the range of Ta=-40o '" 65°C and from Ta=65°C
up to 85°C derating factor of -lOmW/oC shall be applfed
until 300rnW.
He-687
('ro P VIEW)
Q.8
Tc74Hc4m7P/F--------------------------------TRUTH TABLE
GE
OLEAR
DEOODE OUTPUT
X
X
H
Q,O
L
X
L
Q,n
H
L
Q,n
L
L
OLOOK
X
.J
L
L
(H)
X : DON'T OARE
Q,n: NO OHANGE
Q,n+l
L
'Q,n
H
....r
L
Q,n
H
L
L
Q,n+l
LOGIC DIAGRAM
Q,O
Q,6
Q,5
Q,l
Q,2
Q,8
Q,4
CE ..::1:..::3~:>-o
OLOCK .:1:.;:4_-.J
OLEAR =:;15=--_ _1~.....
HC·688
Q,7
Q,3
Q, 9
CARRY
OUT
-
......- -......------------TC74HC4017P/F
TIMING DIAGRAM
r--
CLEAR
CLOCK
J ~f-fU
CE
f--
'loO
'lol
'lo3
t----
r---
I--
'lo2
ru-
r--
r-r--
r-r--
'lo4
r-
r--
f--
'lo5
r--
'loS
r--
'lo7
r--
'loB
r--
'lo9
CARRY OUT
INPUT and OUTPUT
EQUIVALENT CIRCUIT
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
LIMIT
2 '\,6
VIN
VOUT
Topr
o '\, Vee
o '\, Vee
-40'\, 85
tr. tf o'\, 1000 (Vee=2. OV
o '\, 500 (Vee=4. 5V
o '\, 400 (Vee=6. OV
UNIT
V
V
-,
I
*
V
I
°e
I OUTPUT
INPUT
I
f
_J
ns
GND
He-689
T C 7 4 H C 4 0 1 7 P / F - - - - - - - - - - - - - -......-
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High':"Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
TEST CONDITION
VIN=VIH
VOH
or VIL
MIN.
2.0
4.5
6.0
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
2.0
4.5
6.0
-
-
-
0.5
1. 35
1.B
-
0.5
1. 35
1.B
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
5.9
IOH=-4mA
4.5
4.1B
5.68
4.31
5.80
-
-
IOH=-20)JA
2.0
4.5
6.0
0.1
0.1
0.1
-
IOH=-5.2mA 6.0
Low-Level
Output Voltage
Input Leakage
Current
Quiescent
Supply Current
VOL
Ta=25°C
tr'a--40",B5°C
UNIT
TYP. MAX. MIN. MAX.
VCC
VIN=VIH
2.0
4.5
6.0
-
IOL=20)JA
-
0.0
0.0
0.0
or VIL
IOL=4mA
IOL=5.2mA
4.5
6.0
-
0.17 0.26
0.18 0.26
-
4.13
5.63
-
-
V
-
-
0.1
0.1
0.1
V
..
V
V
0.33
0.33
lIN
VIN=VCC or GND
6.0
-
-
±O.l
-
±1.0
ICC
VIN=VCC or GND
6.0
-
-
4.0
-
40.0
)JA
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Output Transition Time
(CL-50pF
, INPUT tr=tf-6ns)
-
SYMBOL TEST CONDITION
tTLH
tTHL
Propagation Delay Time
tpLH
(CLOCK, CE - Q, CARRY) tpHL
Propagation Delay Time
tpLH
(CLEAR - Q, CARRY)
tpHL
VCC
MIN.
2.0
4.5
6.0
2.0
4.5
6.0
-
2.0
4.5
6.0
HC-690
-
-
-
-
Ta=25°C
Ta=-40"'B5°·C
UNIT
TYP. MAX. MIN. MAlt.
30
B
7
100
75
15
13
25
21
195
39
33
100
25
21
195
39
33
-
-
95
19
16
-
245
-
49
42
-
245
49
42
ns
----------------------------------Tc74Hc4m7P/F
AC ELECTRICAL CAHRACTERISTICS (Continued)
PARAMETER
SYMBOL TEST CONDITION
Maximum Clock
Frequency
fMAX
Minimum Pulse Width
(CLOCK)
tw(L)
tw(H)
'
Minimum Pulse Width
(CLEAR)
tw(H)
Minimum Set-up Time
ts
. Minimum Hold Time
Minimum Removal Time
(CLEAR)
VCC
2.0
4.5
6.0
MIN.
5
25
29
2.0
4.5
6.0
..
2.0
-
4.5
6.0
2.0
4.5
6.0
2.0
th
4.5
6.0
2.0
4.5
6.0
trem
-
-
-
-
Input Capacitance
CIN
-
Power Dissipation
Capacitance
CpD(l)
-
Note (1)
Ta=25°C
Ta=-40"'85°C
UNIT
TYP. MAX. MIN. MAX.
10
4
41
20
MHz
24
48
95
30
75
19
15
8
16
13
7
95
75
30
19
15
8
16
13
7
0
0
ns
0
0
0
0
30
75
95
19
7
15
6
16
13
95
25
75
19
15
6
5
16
13
-
-
5
10
74
-
-
10
pF
-
CPD is defined as the value of internal equivalent capacitance of IC which is
calculated from the operating current consumption without load (refer to Test
Circuit).
Average operating current can be obtained by the equation hereunder.
ICC(opr.) = CpD • VCC • fIN + ICC
HC-691
Tc74HC4m7P/F---------------------------------SWITCHING CHARACTERISTICS TEST WAVEFORM
VCC
CLEAR
CLOCK
GND
GND
VOH
VOH
Q.n
Q,l -
Q.9
VOL
VOL
VOH
Q.O,
CARRY
OUT
CLOCK
50%
OND
VOL
VOH
CARRY
OUT
VOL
f5CY1;
CLOCK
--
't8
- - -..... - - - - - - - VCC
GND
' - - - - - - - GND
VCC
.I 50%
j
VCC
__J
.r
VCC
CLOCK
~~----+~-----GND
GND
th
t8
r-- ---
, ' - - - - - VOH
/
Q.n
'th
Q.n
I
______...J-'I______ VOL
ICC(opr.) TEST CIRCUIT
P.G
*
*
I----~
CLOCK
CE
I
: OUTPUTS
I
CLEAR
HC-692
INPUT WAVE~ORM IS THE SAME AS
THAT IN CASE OF SWITCHING
CHARACTERISTICS TEST.
TC74HC4020API AF I AFN
----TC74HC4040AP/AF/AFN
TC74HC4020APt AFt AFN
TC74HC4040APt AFt AFN
14-STAGE BINARY COUNTER
12-ST AGE BIN AR Y CO,.-=U:..,:.N:..;T:-:E::.:.R-=--_ _ _ _ _ _----.
The TC74HC4020A/TC74HC404OA are high speed CMOS
BINARY COUNTER/DIVIDERs fabricated with silicon
gate C 2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS
dissipation.
The TC74I:IC4020A is a 14-STAGE BINARY
COUNTER, and the TC74HC4040A is a 12-STAGE
BINARY COUNTER.
Setting CLEAR to high resets the counter to low.
A negative transition on the CLOCK input brings one
increment into the counter.
The TC74HC4020A provides 12 divided outputs: 1;st
stage and stage 4 thru stage 14. At Q14, a 1116384 divided
frequency will be output.
The TC74HC4040A provides all divided output stages,
and at Q12, a 1/4096 divided frequency will be output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P( 01 P16- P-300A)
1.~16~
F(SOP16-P-300)
FN(SOL 16-P-150)
TRUTH TABLE
CLOCK CLEAR OUTPUT STATE
FEATURES:
• High Speed .............................. (\v.x=60MHz(Typ.)at Vee=5V
• Low Power Dissipation ....•....... Iee =4IlA(Max.)at Ta=25't
• High Noise Immunity .. ···········•· V:-,:IH =V:-':IL2896 Vee (Min.)
• Output Drive Capability'·' ......... 10 LSTTL Loads
• Symmetrical Output Impedance ... , 100' =IOL =4mA(Min.)
• Balanced Propagation Delays •..... tpl.H" tpliL
• Wide Operating Voltage Range ... Vee (opr)=2V-6V
• Pin and Function Compatible with 4020B/4040B
X
H
ALL OUTPUTS
ML·
.r
L
NO CHANGE
1..
L
ADVANCE TO
NEXT STATE
=
X : DON'T CARE
PIN ASSIGNMENT
TC74HC4020A
TC74HC4040A
012
1
16
Vee
012
1
16
013
2
15 011
06
2
15 011
014
3
14 010
05
3
14 010
06
4
13 08
07
4
13 08
05
5
12 09
04
5
12 09
07
6
11 CLEAR
03
6
11
04
7
10 CLOCK
02
7
10 CLOCK
GND
8
9
GND 8
01
(TOP VIEW)
HC-693
9
Vee
CLEAR
01
TC74HC4020API AF I AFN
TC74HC4040AP/AF/AFN - - - - - - - - - - - - - -
IEC LOGIC SYMBOL
TC74HC4020A
TC74HC4040A
R,CTR 14
RCTR 12
(11)
CT=O
CLR
(10)
CK
0
01
3
04
4
05
0
(11)
04
07
05
(10)
CK
09
13
03
06
as
+ CT
CT=O
CLR
01
02
06
+ CT
07
010
as
011
09
012
010
013
all
11
014
HC~694
012
TC74HC4020API AF I AFN
- - - - - - - - - - - - - TC74HC4040AP/AF/AFN
SYSTEM DIAGRAM
TC74HC4020A
01
04
07
08
0&
CiJiCi( ...,;1:.:,.0--cc:--t
CLEAR
11
012
013
014
TC74HC4040A
010
011
02
03
08
O'
0&
CLEAR -'1.....
1 -D-I::>--+
012
all
010
HC-695
01
07
08
TC74HC4020AP/AF1AFN _ _ _ _ _ _TC7 4HC4040AP I AF I AFN
_ _ _ _ _ _ _-
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
V~
Vcx:r
11K
10K
Iex.T
lee
Po
Tstg
TL
RECOMMENDED.OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL I
,
Vee :
VI:\ I
Vex.T I
Topr I
tr , tr
II
*500mW in the range of Ta=
-40'C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
_.
VALUE
2-6
o-Vee
o -Vee
-40 - 85
0- 100O(Vee =2.0V)
0- SOO(Vee =4.5V)
o - 400(Vcc=6.0V)
I
Input Rise and Fall Time
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
VALUE
-0.S-7
-O.S -Vee+0.5
-O.S -Vee+O.S
±20
±20
±2S
±SO
SOO(DIP) */180(MFP)
-65 -ISO
300
Vee
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
ViL
High - Lev.el
Output Voltage
Voo
Low-Level
Output Voltage
Vex.
TEST CONDITION
VI:\ =
VIHorVIL
VI:\=
VIHorVIL
100 =-20tl A
100 - 4 rnA
100 =-5.2mA
lex. =20 tl A
lex. -4 rnA
=S.2mA
V 1:\ =Vee or GND
V,:\ -Vee or GND
I lex.
Input Leakage Current
Quiescent Supply Current
11:'\
lee
I
Vee
2.0
4. S
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4. S
6.0
4.5
6.0
6.0
6.0
HC~696
Ta--40 -8S"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
O. S
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4,5
4.4
4.4
V
6.0
5.9
5.9
4.13
4.18
4.31
- I
S.68
5.80
5.63
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.1
0.0
0.17
0.33
0.26
0.33
0.18
0.26
±1.0
±0.1
A
40.0 tl
4.0
MIN.
1.5
3.1S
4.2
-
-
-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC4020AP/AF/AFN
TC74HC4040API AF I AFN
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
tW(L)
t\\,(I-I)
Minimum Pulse Width
(CLEAR)
tW(I-I)
Minimum Removal Time
Clock Frequency
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
trem
f
Ta--40 -85"C
UNIT
LIMIT
95
19
16
95
ns
19
16
30
6
5
5
MHz
24
28
Ta-25"C .
TYP.
LIMIT
75
15
13
75
15
13
25
5
5
6
30
35
-
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTU-I
tTIiL
tpLH
toHL
tpLH
toHL
tpLfj
tPHL
-
4
8
-
16
24
-
5
14
-
14
24
f:l.1AX
33
73
-
Propagation Delay Time
(CLOCK-Ql)
Propagation Delay Time
(Qn-Qn+l)
Propagation Delay Time
(CLEAR)
Maximum Clock Frequency
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
ns
MHz
AC ELECTRICAL CHARACTERISTlCS{CL =50pF.lnput t r =t,=6ns)
Ta- 40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
30
2.0
95
75
tTU-I
Output Transition Time
8
19
4.5
15
tTIiL
7
6.0
13
16
70
2.0
145
180
Propagation Delay Time
tpLH
20
4.5
29
36
(CLOCK-Ql)
tpHL
17
6.0
25
31
ns
20
2.0
75
95
Propagation Delay Time
tpLH
6
19
4.5
15
(Qn-Qn+l)
tpHL
4
6.0
13
16
55
2.0
140
175
Propagation Delay Time
tpLH
17
4.5
28
35
(CLEAR)
tpHL
14
30
6.0
24
6
17
5
2.0
Maximum Clock
- MHz
fMAX
66
24
4.5
30
Frequency
78
6.0
28
35
Input Capacitance
CIN
5
10
10
TC74HC4020A
pF
27
Power Dissipation Capacitance
Cpo(l)
TC74HC4040A
37
Note (1) C fl) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption'without load.
Average operating current can be obtained by the equation:
ICC{ptl=Cfl) • Va;. fl.'\ +Ia;
PARAMETER
SYMBOL TEST CONDITION
Vee
HC-697
MIN.
TC74HC4022AP/AF-----------~
OCTAL COUNTER/DIVIDER
The TC74HC4022A is a high speed CMOS OCTAL
COUNTER DIVIDER fabricated with silicon gate C· MOS
technology.
It achieves the high speed operation similar to equiv-
alent LSTTL while maintaining the CMOS low power
dissipation. It contains 4-stage divide-by-8 Johnson counter with 8 decoded outputs (QO-Q7) and a carry-out bit.
This counter is advanced on the positive edge of clock
signal when CLOCK ENABLE input is held low, or it is
advanced on the negative edge of clock enable signal when
CWCK input is held high, and the selected one of eight
outputs goes high. By holding the CLEAR input high, the
counter is cleared to its zero state without regard to the
other input conditions.
1
P(DIPI6-P-SOOA)
16~
1
F(SOPI6-P-300)
All inputs are equipped with protection circuits against
static discharge or tansient excess voltage.
PIN ASSIGNMENT
FEATURES:
• High Speed ................................. fMAX=57MHz(typ.) at Vcc=5V
• Low Power Dissipation ............... Icc=4#A(Max.) at Ta=25"C
• High Noise Immunity .............. · VNlH=VNIL=28711 Vcc(Min.)
• Output Drive Capability ...........• 10 LSTTL Loads
• Symmetrical Output Impedance .. ·1 IOHI =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH"otpHL
• Wide Operating Voltage Range ..• Vcc(opr)=2V-6V
• Pin and Function Compatible with 4022B
01 1
16 Vcc
15 CLEAR
00 2
02 3
05 4
06 5
14 CLOCK
13 CE
12 g~~RY
11 04
10 07
9 NC
NC 6
03 7
GND 8
(TOP VIEW)
TRUTH TABLE
IEC LOGIC SYMBOL
CLOCK
INPUTS
CE
X
X
CLEAR
H
L
X
L
X
H
L
~
L
L
~
L
L
H
~
L
H
~
L
DE.CODE OUTPUT(H)
00
On
On
On+1
On
On
On+1
X:DON'T CARE
Qn:NO CHANGE
He-698
CTR DIV 81
OCT
00
01
02
03
04
06
06
07
co
- - - - - - - - - - - - - - - - - TC74HC4022AP/AF
SYSTEM DIAGRAM
04
03
01
06
07
02
CARRY
OUT
TIMING CHART
CLEAR
CLOCK
CLOCK ENABLE
I
I
LSLll- L.ILILll- L L.
QO
Q1
Q2
Q3
Q4
Q5
-
I
!
rS
r--
-
I I
---- r--I
-
I
r--
Q6
H
Q7
I
CARRY OUT
HC-699
r---
I
slrW-r-rur--
I
-
I
I I I
I
I
--
I I
I
,
"--
-
TC74HC4022AP/AF - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input :Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground CurreJlt
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Voor
11K
10K
I(X;'T
lee
Po
Tstg
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
VALUE
-0.5-7
-0.5 -Vee+0.5
-0·5 -Vee +Q·5
±20
±20
±25
±50
500(DIP)·/180(SOIC)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
Vc;c
VIN
Voor
Topr
Input Rise and Fall Time
tr • tr
UNIT
V
V
V
VALUE
2-6
O-Vee
O-Vee
-40 - 85
o- IOOO(Vee -2.0V)
0- 500(Vee =4.5V)
0- 400(Vee =6.0V)
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
VOL
Input Leakage Current
Quiescent Supply Current
llll,
lee
TEST CONDITION
100 =-20JJ,A
VI!II=
VIHOrVIL 1100 =-4 mA.
100 =-5. 2mA
VI" =
VIHorVIL
IOL =20 p.A
IOL -4 mA
IOL =5.2mA
YIN "'Vee or GND
V1:-l =Vee or GND
Vee
2.0
4.5
6.0
2.0
4~ 5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
He-700
Ta 40 -85"(
Ta-25"C
UNIT
TYP. MAX. MIN. 1MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.4
4.5
V
5.9
5.9
6.0
4.13
4.18
4.31
5.63
5.80
5.68
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.1
0.0
0.17
0.33
0.26
0.26
0.33
0.18
±1.0 p.A
±0.1
40.0
4.0
MIN.
1.5
3.15
4.2
-
-
-
-
--
-
-
-
-
-
-
-
--
- - - - - - - - - - - - - - - - - TC74HC4022AP/AF
TIMING REQUIREMENTS(lnput tr=tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
twHI.
tpUl
toHL
fMAX
Propagation Delay Time
(CLOCK,CE-Q,CARRY)
Propagation Delay Time
(CLEAR-Q,CARRY)
~1aximum Clock Frequency
MIN.
TEST CONDITION
-
33
MAX.
TYP.
4
8
17
27
15
25
UNIT
ns
MHz
57
AC ELECTRICAL CH ARACTERISTICS(C L =50pF ,Input t,=tf=6ns)
Ta 40 -85"C
Ta=25"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Va; MIN. TYP. MAX. MiN. MAX.
2.0
95
30
75
t1U!
Output Transition Time
8
4.5
19
15
t11iL
6.0
7
16
13
2.0
200
160
71
Propagation Delay Time
tpUl
ns
4.5
32
40
21
(CLOCK,CE-Q,CARRY) tpHL
6.0
27
34
16
2.0
180
69
145
Propagation Delay Time
tpUl
4.5
29
36
19
(CLEAR-Q,CARRY)
tpHL
6.0
31
25
15
5
2.0
11
6
Maximum Clock
- MHz
4.5
fM.A.X
25
31
51
Frequency
6.0
29
36
63
input Capacitance
10
5
10
CJ:\
pF
_Power Dissipation Capacitance cpom
53
Note (J) C fl) IS defmed as the value of the mternal eqUivalent capacitance which IS calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia;Qxj=Cro • Vex: oflN +Iex:
-
-
-
-
-
-
HC-701
-
-
-
TC74HC4024API AF - - - - - 7-STAGE BINARY COUNTER
.The TC74HC4024A is a high speed CMOS 7-STAGE
BINARY COUNTER fabricated with silicon gate C· MaS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
A negative transition on the CLOCK input brings one
increment to ~he counter. .
.
A CLEAR input is used to reset the counter to the all
low level state .. A high level at CLEAR accomplishes the
reset function.
All divided output stages are provided. and at the last
stage. 11128 divided frequency will be obtained.
All inputs are equipped with protecti~n circuits against
static discharge or transient excess voltage.
1
P(DIPI4-P-300)
14~
1
F(SOPI4-P-300)
PIN ASSIGNMENT
FEATURES:
.• High Speed ................................. fN1.A.X=70MHz(typ.)at Vcc=5V
• Low Power Dissipation .......... ;.... Icc=4JlA(Max.)at Ta=25"C
• High Noise Immunity··············· V:"IH=V:\IL=28% Vcc(Min.)
• Output Drive Capability'" ......... 10 LSTTL Loads
• Symmetrical Output Impedance "'IIOHI=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH"tpHL
• Wide Operating Voltage Range ... Vcc(opr)=2V-6V
• Pin and Function Compatible with 4024B
CLOCK 1
14 Vee
CLEAR 2
13
12
11
10
NC
9
8
03
07 3
0& 4
05 6
04 6
GND 7
(TOP
TRUTH TABLE
01
02
NC
NC
VIEW)
IEC LOGIC SYMBOL
INPUTS
OUTPUT STATUS
CLOCK
CLEAR
X
H
ALL OUTPUTS=-L·
L
NO CHANGE
L
ADVANCE TO NEXT STAGE
S
L
X:Don't care
HC-702
01
02
03
04
0&
0&
07
----------------TC74HC4024AP/AF
SYSTEM DIAGRAM
He-703
TC74HC4024AP I AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
Vour
11K
10K
Iollr
lee
Po
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)·/180(SOIC)
-65 -150
300
UNIT
v·
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85'C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
o -Vee
o -Vex;
-40 - 85
o- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
0- 400(Vee =6.0V)
SYMBOL
Vee
VIN
Vour
Topr
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
100 =-20J.tA
VIN=
VlHorVIL
100 --4 rnA
100 =-5.2mA
Low-Level
Output Voltage
VOL
VIN=
VlHorVIL
Input Leakage Current
Quiescent Supply Current
liN
Icc
IOL =20 J.tA
IOL -4 rnA
IOL =5.2mA
VI:'II -Vee or GND
VIN -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-704
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
l.5
V
3.15
4.2
0.5
0.5
V
l. 35
l. 35
l.8
l.8
l.9
2.0
l.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.1
0.1
0.0
0.1
0.1
0.0
V
O. 1
0.1
0.0
0.26
0.33
0.17
-0.33
0.26
0.18
±O.l
±l.0
J.tA
4.0
40.0
MIN.
1.5
3.15
4.2
-
-
TC74HC4024API AF
TIMING REQUIREMENTS(lnput t r =t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pu.lse Width
(CLOCK)
tW(U
twO;)
Minimum Pulse Width
(CLEAR)
twO;)
Minimum Removal Time
trem
Clock Frequency
f
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta- 40 -85"(;
UNIT
LIMIT
95
19
16
95
ns
19
16
30
6
5
5
MHz
25
29
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
25
5
5
6
31
36
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTHI.
tpLH
toHI.
Propagation Delay Time
(·CLOCK -Ql)
Propagation Delay Time
(Qn-Qn+l)
Propagation Delay Time
(CLEAR-Qn)
Maximum Clock Frequency
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
13
20
atpd
-
4
9
tpLH
tpHL
fMAX
-
13
20
34
70
-
UNIT
ns
MHz
AC ELECTRICAL CHARACTERISTICS(CL =50pF.lnput t r =tf=6ns)
Ta-25"(;
Ta- 40 -85"(;
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vee MIN. TYP. MAX. MIN. MAX.
2.0
95
30
75
tTLH
Output Transition Time
4.5
8
19
15
tn-n.
6.0
7
16
13
2.0
150
60
120
Propagation Delay Time
tpLH
4.5
30
16
24
(CLOCK-Ql)
tpHL
6.0
26
13
20
ns
2.0
75
24
60
Propagation Delay Time
4.5
atpd
6
15
12
(Qn-Qn+l)
6.0
5
13
10
150
2.0
120
50
Propagation Delay Time
tpLH
30
16
24
4.5
(CLEAR-Qn)
tpHL
26
6.0
20
13
2.0
5
6
17
Maximum Clock
MHz
4.5
fMAX
31
63
25
Frequency
6.0
29
36
73
Input (Japacitance
10
CIN
5
10
pF
Power Dissipation Capacitance CPD(1)
36
Note (l) CPD IS defmed as the value of the mternal equIvalent capacItance whIch IS calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
leet1>lFCPD • Va::. fN +Ia::
-
He-705
TC74HC4028AP/AF-----BCD-TO-DECIMAL DECODER
The TC74HC4028A is a high speed CMOS BCD-toDECIMAL DECODER fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
A BCD code applied to the four inputs (A-D) sets a high
level at one of ten decoded outputs. A illegal BCD code
such as eleven thru fifteen sets all outputs low. This
device can be used as 3-to-8 LINE DECODER when input
D is held high.
This device is useful for code conversion. address
decoding. memory selection. multiplexing. or readout.
decoding.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIPI6-P-300A)
16~
F(SOPI6-P-300)
PIN ASSIGNMENT
FEATURES:
• High Speed .............................. tpd=18ns(Typ.)at Vcc=5V
• Low Power Dissipation ............ Icc=4ttA(Max.)at Ta=25"C
• Higli Noise Immunity •.............. V~IH =V~IL=28" Vcc(Min.)
• Output Drive Capability'·' ......... 10 LSTTL Loads
• Symmetrical Output Impedance ···1 100 1=IOL=4mA(Min.)
• Balanced Propagation Delays ...... tpLH ... tpHL
• Wide Operating Voltage Range ... Vcc(opr)=2V-6V
• Pin and Function Compatible with 4028B
Y4 1
Y2 2
YO 3
16Vee
15Y3
14Yl
Y7 4
Y9 5
13 B
Y5 6
Y6 7
110
GND
12 C
10 A
a
9
(TOP
IEC LOGIC SYMBOL
BCD/DEC
A ~
(13) 1
B
C
o
mE
(11
2
4
8
0
1
2
3
4
5
6
7
8
9
He-706
3
~
ff
ff5
~
i6"
fJ
7
ft
f5
'""-
YO
Yl
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
VIEW)
ya
-------------------------------TC74HC4028AP/AF
TRUTH
TABLE
INPUTS
D
L
C
L
L
L
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
H
H
H
H
H
L
L
L
L
H
X
H
H
H
X
A
L
H
L
H
L
H
L
H
L
H
X
X
X:Don't
care
L
H
SYSTEM
B
YO
Yl
Y2
Y3
OUTPUTS
Y4 Y5 Y6
Y7
Y8
Y9
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
SELECTED OUTPUT
YO
Y1
Y2
V3
V4
V5
V6
Y7
L
va
V9
NOTE
NOTE
DIAGRAM
~--"'-
VO
V1
V2
B
M+~~r-~~,,~--- V3
"'----'- V4
Y5
.... ""~--'''''''--------'~ V6
~----:"IJ~--~~
D
V7
va
L--L~~_~iJ~~lr-".,...------"~
HC-707
V9
TC74HC4028AP/AF------------------------------
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vex;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vex;
VIN
Voor
11K
10K
loor
lex;
Po
Tstg
TL
VALUE
-0.5-7
-0.5 -Vex; +0.5
-0.5 -Vex;+0.5
±20
±20
±25
±50
500(DIP) */180(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
:
*50DmW in the range of Ta=
-'40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m W/"C shall be applied
until 300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vex;
0- Va;
-40 - 85
o - lOOO(Va;=2.0V)
0- 500(Vex;=4.5V)
0- 400(Vex;=6.0V)
SYMBOL
Vex;
VIN
Voor
Topr
tr •
tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
V(Ji
Low-Level
Output Voltage
Va..
Input Leakage Current
Quiescent Supply Current
11:'1:
lex;
TEST CONDITION
VIN=
VIHorVIL
VIN=
VIHorVIL
1(Ji =-20p. A
100 --4 rnA
I(Ji =-5. 2mA
Ia.. =20 p. A
Ia.. -4 rnA
Ia.. =5.2mA
V IN -'Vex; or GND
V IN -Vex; or GND
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
He-70B
Ta-25"C
Ta--40 -85"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.5
4.4
4.4
V
5.9
6.0
5.9
4.13
4.31
4.18
5.80
5.63
5.68
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.1
0.0
0.26
0.33
0.17
0.33
0.26
0.18
±0.1
±1.0 p.A
40.0
4.0
MIN.
1.5
3.15
4.2
-
-------------------------------TC74HC4028AP/AF
AC ELECTRICAL CHARACTERISTICS(CL =16pF. Vcc=6V .Ta=26"C, Input t r =tf=6ns)
PARAMETER
SYMBOL
Output Transition Time
tTLH
tTHL
tpLH
tpHL
Propagation Delay Time
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
18
34
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =60pF.lnput t r =tf=6ns)
Ta- 40 -85"C
Ta-25"C
UNIT
PARAMETER
SYMBOL TEST CONDITION
Vex MIN. TYP. MAX. MIN. MAX.
2.0
75
95
30
t1Ui
Output Transition Time
8
15
19
4.5
tTI-JL
6.0
7
13
16
ns
2.0
225
80
180
Propagation Delay Time
tpLH
4.5
22
36
45
tpHL
(A.B.C.D-Y)
6.0
18
31
38
Input Capacitance
C IN
5
10
10
pF
Power Dissipation Capacitance CpDm
44
Note(l) C m 1S defmed as the value of the mternal equivalent capacitance wh1ch is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iextp}=CPD· Vo:;of IN +10:;
He-70g
TC74HC4049API AFI AFN
TC7 4HC4050AP I AF I AFN
TC74HC4049AP/AF/AFN
TC74HC4050AP/AF/AFN
HEX BUFFER CONVERTER(INVERTING)
HEX BUFFER CONVERT,.:-E;::..R'-"---,-_ _ _ _ _ _----.
The TC74HC4049A and TC74HC4050A are high speed
CMOS HEX BUFFERs fabricated with silicon gate
C2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
The TC74HC4049A is an inverting buffer, while the TC74
HC4050A is a non-inverting buffer. The internal circuits
are composed of 3-stages (HC4049A) or 2-stages (HC405
OA) of inverters, which provide high noise immunity and
stable output.
Input protection circuits are different from those of
other high speed CMOS IC's. They eliminate the diodes on
the Va; side thus providing of logic-level conversion from
high-level voltages up to 15V to low-Ieve.! voltages.
They are useful for battery back up circuits, because
input voltage can be applied on IC's which are not biased
by Va;.
FEATURES:
• High Speed .....................•..•....• tpd=9ns(Typ.)at Va;=5V .
• Low Power Dissipation ......•...•. Ia;=lJlA(Max.)at Ta=25"C
• High Noise Immunity··············· V;"IH = V"IL 28% Va; (Min.)
• Output Drive Capability'" ........• 15 LSTTL Loads
• Symmetrical Output Impedance "'1 IOH 1=IOL =6mA(Min.)
• Balanced Propagation Delays'" ... tpLH '" tpHL
• Wide Operating Voltage Range ... Va; (opr) =2V -6V
• Pin and Function Compatible with 40496/4050B
1
P( 01 P16-P-300A)
F(SOP16-P-300)
TRUTH TABLE
A
Y(4049A)
L
H
L
H
L
H
PIN ASSIGNMENT
TC74HC4050A
TC74HC4049A
16 Ne
Vee
Vee
1
16 Ne
1Y
2
156Y
1Y
2
15 6Y
1A
3
146A
1A
3
14 6A
2Y
4
13 Ne
2Y
4
13 Ne
2A
5
125Y
2A
5
12 5Y
3Y
6
11 5A
3Y
6
11 5A
3A
7
104Y
3A
7
10 4Y
GNO 8
9 4A
GNO 8
9 4A
(Top View)
NC : No Connection
HC-710
FN(SOL 16-P-150)
Y(4050A)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC4049AP/AF/AFN
TC74HC4050API AFI AFN
IEC LOGIC SYMBOL
TC74HC4049A
lA
TC74HC4050A
lY
(2)
lA
(5)
lY
2A
2Y
2A
3A
3Y
3A
2Y
(6) 3Y
tl0 ) 4Y
4A
4Y
4A
6A
6Y
5A
6Y
6A
6Y
6A
6Y
9)
INPUT and OUTPUT EQUIVALENT CIRCUIT
TC74HC4049A
TC74HC4050A
---:
I
!
f
y
A __~~+-~~~+:--y
L.--+__
HC-711
~....-I-O-
t
__ '
TC74HC4049AP/AF/AFN _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC40S0API AFI AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
VOUT
11K
10K
lotrr
lee
PD
Tstg
TL
VALUE
-0.5-7
-0.5- 18*
-0.5 -Vee+0.5
-20
±20
±35
±75
500(DIP)**/180(SOIC)
-65 -1,50
300
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
Note)
* DC input voltage (V IN )
specified is measured to
GND and is not related to
Vee·
Recommended operating
range is OV to lSV and it is
possible to convert logiclevels from lSV to SV or SV
to2V.
**500mW in the range of Ta=
-40'C- 6S'C. From.Ta=6S'C
to 8S'C a derating factor of
-10m W/'C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0-15
0- Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
0- 400(Vee=6.0V)
SYMBOL
Vee
VIl'>
VQl,T
Topr
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
Vu.j
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
Vot.
Input Leakage Current
Quiescent Supply Current
II'"
lee
TEST CONDITION
VI'\:=
VIHorVIL
VI:I:=
VIHorVIL
100 =-20/.LA
100 --6 mA
1m =-7.8mA
lot. =20 /.LA
lot. -6 mA
lot. =7.8mA
V ,:I: -"Vee or GND
VIC, -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-712
Ta-25"C
Ta--40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.1
0.1
0.0
O. 1
0.1
0.0
V
0.1
0.1
0.0
0.33
0.26
0.17
0.26
0.33
O. i8
±0.1
±1.0
/.LA
1.0
10.0
MIN.
1.5
3.15
4.2
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC4049AP/AF/AFN
TC74HC40SOAPI AFI AFN
AC ELECTRICAL CHARACTERISTICS(lnput t r =t f =6ns)
TEST
Ta--40 -85"C
Ta-25"C
UNIT
PARAMETER
SYMBOL
CONDITION CL Va:: MIN. TYP. MAX. MIN. MAX.
2.0
25
75
60
tn.1i
Output Transition Time
50 4.5
12
15
6
tn-lL
6.0
5
10
13
2.0
75
95
30
ns
50 4.5
10
15
19
tpLH
6.0
13
16
8
Propagation Delay Time
2.0
tpHL
45
100
145
150 4.5
20
29
15
6.0
17
25
13
Input Capacitance
CI;'\
5
10
10
pF
CFu(l)
Power Dissipation Capacitance
26
Note (1) Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Iccq,o=CPD o Va:; fIN +Ia:; /6(perGate)
0
HC-713
TC74HC4051 AP/AF
TC74HC4052APl AF
TC7 4HC4053AP I AFI AF N
TC74HC4061AP/AF
a-CHANNEL ANALOG MUL TIPLEXER/DEMUL TIPLEXER
TC74HC4052AP/AF
DUAL 4-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
TC74HC4063AP/AF/AFN TRIPLE 2-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
The TC74HC4051A/4052A/4053A are high speed CMOS
ANALOG MULTIPLEXER/DEMULTIPLEXER fabricated
with silicon gate C2MOS technology. They achieve the high
speed operation similar to equivalent LSTTL while
maintaining the CMOS low power dissipation.
The TC74HC4051A has an 8 channel configuration, the
TC74HC4052A has a 4 channel X 2 configuration and the
TC74HC4053A has a 2 channel X 3 configuration.
The digital signal to the control terminal turns ·ON"
the corresponding switch of each channel a large
amplitude signal (V a;-V EE) can then be switched by the
small logical amplitude (Va;-GND) control signal.
For example, in the case of Va;=5V, GND=OV, V EE=
-5V, signals between -5V and + 5V can be switched from
the logical circuit with a single power supply of 5V. As
the ON-resistance of each switch is low, they can be
connected to circuits with low input impedance.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ..................... t p!F15ns(typ.)atVa;=5V,VEE =OV
• Low Power Dissipation .•...• Ia;=4J.tA(Max.)at Ta=25"C
• High Noise Immunity .. •·•• VNIH=VNlL =28% Va;(Min.)
• Low ON Resistance ......... R(lII=50Q(typ.)at Va;-VEE=9V
• High Degree of Linearity··· THD=O.021(i(typ.)at Va;-V EE=9V
• Pin and Function Compatible with 405114052/4053B
1.~
1
P(DIP16-P-300A)
"~16~
F(SOP16-P-300)
PIN ASSIGNMENT
.... '"
8
x
> .....
TRUTH TABLE
CONTROL INPUTS
INHIBIT C* B
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
A
L
H
L
H
L
H
L
H
X
·ON" CHANNEL
HC4051 A HC4052A
0
1
2
3
4
5
6
7
NONE
OX,OY
1X,1Y
2X,2Y
3X,3Y
-----
NONE
HC4053A
OX,OY,OZ
1X,OY,OZ
OX,1Y,OZ
lX,lY,OZ
OX,OY,1Z
1X, OY, lZ
OX, 1Y, lZ
lX, 1Y, 1Z
NONE
X: DON'T CARE, •. : Except HC4052A
HC-714 .
FN(SOL 16-P-150)
-
....
»:i:»:r:"'c
0
.....
8""
~::~
>-
:i: :i:
o
0
I~::::::: :1
>~N8~~~~
N
TC74HC4051 AP/AF
- - - - - - - - - - - - - - TC74HC4052AP/AF
TC7 4HC4053APIAF IAF N
SYSTEM DIAGRAM
COM
TC74HC4051A
~
A
~
Ii
0
E
B
....
j
....
C
INH
.X-COM
OX
TC74HC4052A
A
Ii
1X
i
2X
l
3X
t:
0
B
...."
j
OV
..J
2V
INH
3V
V-COM
V-COM
X-COM
A
~
B
0
Ii
>
i
"
C
..J
j
OX
1X
OV
1V
OZ
1Z
Z-COM
INH
HC-715
TC74HC4051 AP/AF
TC74HC4052API AF
TC74HC4053APIAF I AF N
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Supply Voltage Range
Vee
Supply Voltage Range
Vee-VEE
Control Input Voltage
V1:\
Switch I/O Voltage
VI/a
Control Input Diode Current
ICK
I/O Diode Current
I 10K
Switch through Current
IT
DC Veeor GND Current
lee
Power Dissipation
PI)
Storage Temperature
Tstg
Lead Temperature 10sec
TL
VALUE
-0.5 - 7
-0.5-13
-0.5 -Vee +0.5
VEE -0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
UNIT
V
V
V
V
rnA
rnA
rnA
rnA
mW
*500m W in the range of Ta=
-4Q'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m Wf'C shall be applied
until300mW.
"C
°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage Range
Supply Voltage Range
Supply Voltage Range
Control Input Voltage
Switch 1/0 Voltage
Operating Temperature
SYMBOL
Vee
VEE
Vee-VEE
V1:\
VI/a
Topr
Control Input Rise and Fall Time tr • tf
VALUE
2-6
-6 - 0
2 - 12
0- Vee
VEE - Vec
-40 - 85
o - 1000(Vee =2.0V)
0- 500(Vc.,'c=4.5V)
o - 400(Vc;c=6.0V)
UNIT
V
V
V
V
V
°C
ns
IEC LOGIC SYMBOL
TC74HC4051A
TC74HC4052A
A ~1}
~I)
B (9)
C
INH (6)
HC-716
TC74HC4053A
TC74HC4051 AP I AF
- - - - - - - - - - - - - - T C 7 4 HC4052AP/AF
TC74HC4053APIAFI AFN
DC ELECTRICAL CHARACTERISTICS
TEST
PARAMETER
SYMBOL
CONDITION
High - Level Control
Input Voltage
Low- Level Control
Input Voltage
ON Resistance
VEE
Vex
2.0
4.5
\ Ville
6.0
2.0
VII.c
4.5
6.0
VI\=VILC or VIlIC GND 4.5
\1/0= Vce to VEE -4.5 4.5
11/0 ~2mA -6.0 6.0
Ro:\ V V
V;
GND 2.0
1,= ILC or IHC\GND 4.5
Vl/o=Vcc or VEE -4 5 4.5
11: 0 ~2mA
6: 0 6.0
V,,-VILC or VlHC GND 4.5
.6.Ro:\ Vi/o= Vce to VEE -4.5 4.5
11.'0 :=;;2mA -6.0 6.0
Vos-VccorGND
GND 6.0
I OFF IVls=GND or Vee -6.0
6.0
~,,=VILC or VlIIC
I
1-
Difference of
ON Resistance
Between Switches
Input/Output
Leakage Current
(SWITCH OFF)
Switch Input
Leakage Current
(SWITCH ON)
Control Input Current
~uiescent
Supply Current
lIZ
11:\
roc
Vos=Vccor GND GND
~1\=VILe or VIHC -6.0
6.0
6.0
V,,- Vccor GND GND
GND
V,,=Vccor GND
-6.0
6.0
6.0
6.0
HC-717
MIN.
1.5
3.15
4.2
-
-
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
3.15
4.2
V
0.5
0.5
1. 35
1. 35
I
1.8
1.8
225
180
85
120 I 150
55
125
50
100
150
70
150
190
Q
125
100
! 50
45
80
100
35
10
30
12
15
5
12
5
10
I
I
-
-
± 60
±100
-
± 600
±lOOO
-
-
± 60
±100
-
± 600
±1000
±0.1
4.0
8.0
-
±1.0
40.0
80.0
-
-
-
-
-
nA
IJ.A
TC74HC4051 AP/AF
TC74HC4052API AF
TC74HC4053AP I AF I AF N
AC ELECTRICAL CHARACTERISTICS(C L =50pF,lnput t r =tf=6ns,GND=OV)
TEST
Ta-25OC
Ta- 40 -85OC
PARAMETER
SYMBOL
UNIT
CONDITION Vcc Vee MIN . TYP. MAX. MIN. MAX.
.GND 2.0
25
60
75
4.5
12
15
Phase difference
6
cP
I/O ALL TYPES GND
6.0
13
between Input and Output
5
10
GND
I. -4.5 4.5
4
GND 2.0
225
280
64
GND 4.5
45
56
18
*1 4051 GND 6.0
15
38
48
-4.5 4.5
18
GND 2.0
225
280
64
GND 4.5
18
45
56
tpZl.
Output Enable Time
*1 4052 GND 6.0
tpZH
15
38
48
-4.5 4.5
18
IGND 2.0
225
50
280
IGND 4.5
14
45
56
ns
*1 4053 iGND 6.0
12
38
48
-4.5 4.5
14
GND 2.0
100
250
315
GND 4.5
63
33
50
*1 4051 ,GND 6.0
28
54
43
1-4.5 4.5
29
100
250
315
!GND 2.0
4.5
33
50
63
tpLZ
Output Disable Time
*1 4052 IGND 6.0
28
43
54
tpHZ
GND
-4.5 4.5
29
280
2.0
95
225
GND
56
"
GND 4.5
30
45
*1 4003 !GND 6.0
26
38
48
-4.5 4.5
26
Control Input Capacitance· Cin
ALL TYPES 5
10
10
4051
36
70
70
COMMON Terminal
40
4052 -5.0 5.0
19
40
GIS
Capacitance
-4053
11
20
20
15
4051 I
7
15
SWITCH Terminal
C cs
4052 i -5.0 5.0
7
15
15
Capacitance
pF
4053
7
15
15
2
4051
0.95
2
Feedthrough Capacitance CICS
2
4052 -5.0 5.0
0.85
2
O. 75
2
2
4053
4051
70
Power Dissipation
71
Cro
*2 4052 GND 5.0
Capacitance
4053
67
I
I
I
I
*
*
I: RL =lkQ
2: CPO is defined as the value of the internal equivalent capacitance of Ie which is calculated from
the operating current consumption without load.
A\·erage operating current can be obtained by the equation:
Icc QJil=CPO • Vcc· f[\ +ICC
HC-718
TC74HC4051
AP I AF
_ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74
HC4052AP/AF
TC7 4HC4053AP I AF I AF N
ANALOG SWITCH CHARACTERISTICS(GND=OV.Ta=26"C)
PARAMETER
TEST CONDITION
SYMBOL
Sine Wave Distortion
VII" =4. OVp-p
V I:\ =8. OVp- p
VI:" =11. OVp-p
RL=IOkQ
C L=50pF
fr, =lkHz
(T.H.D)
*1
*2
Frequency
. Response
(Switch ON)
Feedthrough
Attenuation
(Switch OFF)
Crosstalk
(Control Input to
Signal Output)
Crosstalk
f MAX
Adjust fl:'l! Voltage to obtain OdBm at Vos
Increase fiN Frequency until dB Meter
reads-adB
R L=50Q, CL=10pF
fIN=IMHz, Sine Wave
*1
*2
*1
*2
Vin is centered at(Vee - VEt:> /2
Adjust input for OdBm
RL=600Q, C L=50pF
flN=lMHz, Sine Wave
R L =600Q, C L=50pF
fiN =lMHz, Square Wave (tr=tr 6ns)
Adjust V I\ to obtain OdBm at Input
(Between any
switches)
*
*
ALL
4051
4052
4053
ALL
4051
4052
4053
ALL
4051
4052
4053
RL =600 Q, CL =50pF
f r..; =lMHz, Sine Wave
1: Input COMMON Termmal, and measured at SWITCH Terminal.
2: Input SWITCH Terminal. and measured at COMMON Terminal.
NOTE:These characteristics are determined by design of devices.
HC-719
TYP. UNIT
Vee
Vee
-2.25
2.25
0.025
-4.5
4.5
0.020
--6.0
6.0
0.018
-2.25
2.25
-4.5
4.5
-6.0
6.0
-2.25
2.25
-50
%
~
45
70
95
190
-m MHz
110
150
~
85
140
190
-4.5
4.5
-50
-6.0
6.0
-50
-2.25
2.25
60
-4.5
4.5
140
-6.0
6.0
200
-2.25
2.25
-50
-4.5
4.5
-50
-6.0
6,0
-50
dB
mV
dB
TC74HC4051 API AF
TC74HC4052APIAF
TC74HC4053AP I AF I AFN
SWITCHING CHARACTERISTICS TEST CIRCUITS
6ns
Vee
6ns
Voo
GNO
from -+~---,
VOIl
P.G
2.
(SI-VOO • Sz-G_N_O_>J......JI
CROSSTALK (CONTROL INPUT-SWITCH OUTPUT)
ftn=1MHz duty-!iO% tr-tf-6ns
5.
CROSSTALK (BETWEEN ANY TWO SWITCHES)
6.
FREQUENCY RESPONSE (SWITCH ON)
Voo
~NO .1~
from
P.G
a
Vee!
C
r--+~::' :>I-"....-t--r--r<>
fj!
3.
FEEDTHROUGH ATTENUATION
4.
CIOS. CIS. Cos
Coos
r--------il------~
vee:
I
I
I
:
SWITCH :
I
--4---..,
C
Voo
I
I
I
I
: COMMON
He-720
------TC74HC4060API AF
14-STAGE BINARY COUNTER/OSCILLATOR
The TC74HC4060A is a high speed CMOS 14-ST AGE
BINARY COUNTER fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low
power dissipation.
The
oscillator
configuration
allows
designs
using either RC or crystal oscillator circuits.
or an external clock may be used.
The clear input resets the counter to a low
level on all outputs and disables the oscillator.
A high CLEAR accomplishes this reset function.
A negative transition on the clock input ( r/J I)
increments the counter. Ten levels of divided
output are provided; 4 stage thru 10 stage and 12
stage thru 14 stage. At the last stage (Q14). a
1/16384 divided frequency is obtained.
The if> I input and CLEAR input are equipped with
protection
circuits
against
static
discharge
or
transient excess voltage.
FEATURES:
• High Speed .......................... ~...... fMAX=58MHz(typ.)at Vcx;=5V
• Low Power Dissipation ............... Icx;=4ttA(Max.)at Ta=25"C
• High Noise Immunity· .... ··· ...... • VNIH=VNIL=2B1IlVcx;(Min.)
• Output Drive Capability·· .. ·.. ·.. •· 10 LSTTL Loads
• Symmetrical Output Impedance .. ·1 IOHI=IOL=4mA(Min.)
• Balanced Propagation Delays ...... tpLH"'tpHL
• Wide Operating Voltage Range .. · Vcx;(opr)=2V- 6 V
• Oscillator Configuration ............... RC or Crystal Oscillator
• Pin and Function Compatible with 4060B
TRUTH TABLE
+1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
012
013
014
06
06
07
04
2
3
4
6
6
7
GND 8
10
16
14
13
12
11
Vee
010
08
09
.,
CLEAR
10
+0
9
+0
IEC LOGIC SYMBOL
INPUTS
CLEAR
Function
Counter Is ro..t to zero stste
X
1
H
+0 output g_ to high 1....1.
+0 output goes to low 1....1.
04
Q&
08
07
08
Q8
L
L
Count up one step.
S
L
NO change
HC-721
010
012
013
014
TC74HC4060AP/AF---------------ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VIN
Your
11K
10K
lOUT
lee
PD
Tstg
TL
UNIT
V
yo
V
rnA
rnA
rnA
rnA
mW
't
't
VALUE
-0.5-7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)*/180(SOIC)
-65 -150
300
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
o -Vee
0- Vee
-40 - 85
o- 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o- 400(Vcc=6.0V)
SYMBOL
Vee
VIN
Voor
Topr
tr , tr
UNIT
V
V
V
't
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
(Qn)
Voo
High-Level
Output Voltage
(rpo ~o)
Voo
VIN=
VIHorVIL
Low-Level
Output Voltage
(Qn)
Vex.
VIN=
VIHorVIL
Low-Level
Outpu~..voltage
(rpo, rpo)
Vex.
Input Leakage Current
Quiescent Supply Current
lIN
lee
100 =-20 II A
VIN=
VIHorVIL
100 --4 rnA
100 =-5.2mA
100 =-20ll A
Ia.. =20Jl A
lex. -4 rnA
101. =5.2mA
VIN=
lex. =20Jl A
VIHorVIL
VIN -Vee or GND
VIN -Vee or GND
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
6.0
6.0
HC-722
Ta-25't
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.5
4.4
4.4
5.9
6.0
5.9
4.18
4.31
4.13
V
5.68
5.63
5.80
2.0
1.8
1.8
4.0
4.5
4.0
5.5
5.9
5.5
0.0
0.1
0.1
0.1
0.0
0.1
0.0
0.1
0.1
0.26
0.33
0.17
V
0.26
0.33
0.18
0.2
0.0
0.2
0.5
0.0
0.5
0.1
0.5
0.5
±O.l
±1.0
JlA
4.0
40.0
MIN.
1.5
3.15
4.2
-
-
-
-
-
-
-
TC74HC4060API AF
TIMING REQUIREMENTS (Input t,. = t, = 6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(CLOCK)
tW(L)
tW()-l)
Minimum Pulse Time
(CLEAR)
tW()-l)
Minimum Removal Time
trem
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
f
Clock Frequency
Vcr
Ta--40 -85"C
UNIT
LIMIT
95
19
16
95
ns
19
16
125
25
21
5
MHz
24
28
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
100
20
17
6
30
35
AC ELECTRICAL CH ARACTERISTICS(C L =15pF, Vcc=5V :ra=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTUi
t1liL
tpUi
tpHL
Propagation Delay Time
(CLOCK-Q4)
Propagation Delay Time Difference
(Qn-Qn+l)
Propagation Delay Time
(CLEAR)
Maximum Clock Frequency
TEST CONDITION
MIN.
TYP.
MAX.
-
4
8
-
36
53
-
6
14
tpUi"
-
19
34
fMAx
33
58
-
.1.tpd
CL =15pF(Qn.Qn+l)
~L
UNIT
ns
MHz
AC ELECTRICAL CHARACTERISTICS(CL =50pF,lnput t r =tf=6ns)
Ta-25"C
Ta- 40 -85"(
PARAMETER
SYMBOL TEST CONDITION
UNIT
Vrx MIN. TYt'. MAX. MIN. MAX.
2.0
30
75
95
tTUi
Output Transition Time
8
19
4.5
15
tTIiL
6.0
16
7
13
2.0
170
300
375
Propagation Delay Time
tpLH
4".5
75
41
60
(CLOCK-Q4)
tpHL
6.0
64
30
51
ns
32
95
75
Propagation Del~ Time Difference .1.tpd C L • SOpF(Qn.Qn+l) 2.0
7
4.5
15
19
(Qn- n+l)
6.0
5
13
16
2.0
85
195
245
Propagation Delay Time
tpLH
4.5
23
39
49
(CLEAR)
tpHL
6.0
42
17
33
2.0
6
5
12
Maximum Clock
- MHz
fMAX
4.5
30
50
24
Frequency
6.0
35
65
28
Input Gapacitance
CIN
10
5
10
pF
Power lJissipation Capacitance GPO(l)
27
Note (1) C PO is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
-
-
Irxa..l=CPO • Va;. hI! +Ia;
When CR or Crystal oscillation circuit is adopted,the dynamic power·aissipation will be greater than the
above calculation.because these oscillation circuits spend much supply current.
HC-723
TC74HC4060AP/AF - - - - - - - - - - - - - - - SYSTEM DIAGRAM
04
06
06
07
TYPICAL CLOCK DRIVE CIRCUITS
External Clock Drive
Typical RC Circuit
.JUL~
4{---J
Rs
R.
open
Cx
Rs: 2Rx-10Rx
HC-724
Typical Crystal Circuit
TC74HC4060API AF
SWITCHING CHARACTERISTICS TEST WAVEFORM
VOH
Vee
CLEAR
50%
50%
On
GND
VOL
Vee
50%
CLOCK
GND
VOH
On+1
VOL
fltp
V OH
VOH
On+1
On
VOL
fltpd
Q4-Q14
Vee
GND
VOH
VOL
CR
Oscillator
Characteristics
(Typical)
fosc""1/2.2 ex. Rx
2Rx~Rs;
5
10
10
pF
Power Dissipation Capacitance CPDm
27
Note(1) C m is defmed as the value of the mternal equivalent capacitance Which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICC (;pO=C I'D· Va:. f I:>; + I a: 13(per Gate)
He-735
TC74HC4078API A F - - - - - 8-INPUT ORINOR GATE
l'he TC74HC4078A is a high speed CMOS 8-INPUT
ORINOR GATE fabricated with silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power
dissipation.
Output X is an 8-INPUT NOR, output Y is an 8INPUT OR.
Each output has a buffer, which provide high noise
immunity and stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd;=13ns(Typ.)at Va;=5V
• Low Power Dissipation ............ Ia;=lttA(Max.)at Ta=25"C
• High Noise Immunity··············· VNIH =V"'IL28% Va; (Min.)
• Output Drive Capability········· ... 10 LSTTL Loads
• Symmetrical Output Impedance "'1100 1=IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpUi'" tpHL
• Wide Operating Voltage Range .. , Va; (opr.)=2V;...,6V
• Pin and Function Compatible with 4078B
1
P(DIP14-P-300)
14Q
1
F(SOP14-P-300)
PIN ASSIGNMENT
Y 1.
14 Vee
A 2
13 X
B 3
12 H
C 4
llG
o
5
10 F
NC 6
9
GND 7
e
8 NC
(TOP VieW)
NC:No Connection
TRUTH TABLE
IEC LOGIC SYMBOL
A
B
c
0
E
F
G
(2)
~
~
~
~
(12)
H -"=-
~1
rill-v
~x
HC-736
out uta
Inputs A through H
X
Y
All inputs L
H
L
All other combinations
L
H
TC74HC4078API AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VI"
VQl;T
11K
10K
lOLl'
lee
PD
Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee+0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP)*1l80(SOIC)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmW/"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI:\
Vwr
Topr
tr , tr
UNIT
V
V
V
"C
VALUE
2-6
0- Vee
o -Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
o - 400(Vee =6.0V)
nB
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
Va..
Input Leakage Current
Quiescent Supply Current
11:\
lee
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
lai =-20p.A 4.5
VI" =
6.0
VlIlorVIL
lOll --4 rnA 4.5
100 =-5. 2mA 6.0
2.0
IOL =20 p.A 4.5
VI" =
6.0
VlllorVIL
Ia.. -4 rnA 4.5
Ia.. =5.2mA 6.0
6.0
VI" -Vee or GND
6.0
VI" -Vee or GND
HC-737
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
l. 35
1.8
1.8
2.0
1.9
l.9
4.5
4.4
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.0
0.1
0.1
0.0
0.1
0.1
V
0.0
0.1
0.1
0.17
0.26
0.33
0.18
0.26
0.33
±0.1
±1.0 p.A
'.' 1.0
10.0
MIN.
1.5
3.15
4.2
~
TC74HC4078API AF
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc=5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tll.H
tnll.
tpLH
Propagation Delay Time
TEST CONDITION
tnl~1.
MIN.
TYP.
MAX,
-
4
8
-
13
22
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(C L =50pF.lnput t r =tf=6ns)
Ta-25"C
Ta- 40 -85"C
PARAMETER
UNIT
SYMBOL TEST CONDITION
Vee MIN. TYP. MAX. MIN. MAX.
2.0
75
95
30
tTLH
Output Transition Time
4.5
15
8
19
tTHI..
6.0
7
13
16
ns'
2.0
50
130
165
tpLH
Propagation Delay Time
4.5
26
16
33
tpHI..
6.0
22
14
28
Input Capacitance
C IN
5
10
10
pF
Power Dissipation Capacitance CPD(1)
40
Note (l) C ro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lee tpO =C PD "Va:;. fIN +Ia:;
HC-738
----TC74HC4094AP/AF/AFN
a-BIT SHIFT AND STORE REGISTER(3-STATE)
The TC74HC4094A is a high speed 8-BIT SHIFT AND
STORE REGISTER fabricated with .silicon gate C 2 MOS
technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low power
dissipation.
It consists of an 8-bit shift register and an 8-bit latch
with 3-state output buffers. Data is shifted serially
through the shift register on the positive 'going transition
of the CLOCK input., The output of the last stage (Qs) can
be used to cascade several devices. Data on the Qs output
is transferred toa second output (Q's) on the following
negative transition of the CLOCK input. The data in each
stage of the shift register is provided to a corresponding·
latch, on the negative going transition of the STROBE
input. When STROBE is held high, data propagates
through the latch to a 3-state output buffer. This buffer is
enabled when OUTPUT ENABLE input is set high.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. fw •x=73:MHz(Typ.)at Vee=5V
• Low Power Dissipation ............ Iee =4IlA(Max.)at Ta=25"C
• High Noise Immunity .............. · V:\IH =V~IL28% Vee (Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance "'1 Ia; 1=101.. =4mA(Min.}
• Balanced Propagation Delays ...... tpLH'" tpl-IL
• Wide Operating Voltage Range'" Vee (opr}=2V-6V
• Pin and Function Compatible with 4094B
P(DIP16-P-300A)
1.~"~
F(SOP16-P-300)
PIN ASSIGNMENT
STROBE 1
ST ---.l.L,..,.".----....
----,u;.g,L-.,
CK
SI
01
02
03
(14
06
06
07
1---t===~L
I
08
OS
1----'='- o·s
He-73g
16 Vee
SERIAL IN 2
15 OE
CLOCK 3
14 05
01
4
13 06
Q2
5
12 07
03
6
11 08
04
7
10
GND
8
9
(TOP VIEW)
IEC LOGIC SYMBOL
OE
FN(SOL 16-P-150)
a's
as
TC74HC4094AP/AF/AFN - - - - - - - - - - - - TRUTH TABLE
PARA.OUT
CK
OE
8T
81
.1
.1
.1
.1
1..
1..
H
H
L
L
H
H
H
H
an
an-l
an-l
H
L
NC
•
*
•
NC
L
Z
Z
H
•
•
NC
NC
z
Z
L
*
al
*
SERI.OUT
as
a7
a7
a7
a7
a's
NC
NC
as
as
NC
NC
NC
NC
X : DON'T CARE
NC : NO CHANGE
Z : HIGH IMPEDANCE
TIMING CHART
CLOCK
SERIAL
IN
JlJl.JlJ1.J1JlJULfU1J lIll11L!lflSlJlJlIlJ1-!LfUL
-'~ILU-i~~U:l J I
Q2
Q3
Q4
-
r--
--f--
~r-~
-,-- -::
--11r!
--
--
I-I--
06
07
08
0,
Q',
:--
I
f--
r- -f--
I--
r~~.~QI'I.I'(C.J
r= W, fit'/; /;/
r-f--
-
I--
V/, fit'/; /;)
r--- -- -- I-- -- -~ V/; I'h
--- -- ------ --- - ~ YI- jl'h
r-- -.- -r-- -- -- -- --- -V/, 'l"J V/J
- -- -- - -- -- '::'"
-Vi I'/; jl'1f= I-- - r--- ---- --- --- --- -- ---- -- ---- -- --- -- -- .--- r-- r-- r-- I-- ~ ~ ~
r-- - -- --- ---- -- -- -- -- -- -- - - - -- -- ~U- ~U- [U- fL]J
----
f--
0&
i
!
-
I--
ILWlLw
I
r- -
STROBE
OUTPUT
ENABLE
Q 1
LU-~
-
----
f--
'--
r--
-
-f-f--
I--
,.--
f--
=
'---
f--
He-740
-
rrI-
f--
I-f--
r-
-
-
f=
f-- f--
- f--
- I--
-
Ur L Lr
I-- I-
TC74HC4094API AFIAFN
SYSTEM DIAGRAM
'"
o
'"
.,
,....
..
0
...0
.
0
OD
0
...0
...
0
...
0
o
I
"....
8
...w
o
..........
I-
;:)z
II:
u
'"
HC-741
I-w
;:)
I-C
Ow
TC74HC4094AP/AF/AFN - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI:\
VOLT
11K
10K
IOLT
lee
PD
Tstg
TL
VALUE
-0.5-7
-0.5 -Vee +0.5
-0.5 -Vee+0.5·
±20
±20
±25
±50
500(DIP) *1l80(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85'C a derating factor of
-lOmWI"C shall be applied
unti1300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vee
VI:\
VOl;T
Topr
tr • tr
VALUE
2-6
0- Vee
0""';' Vee
-40 - 85
o - 1000(Vee=2.0V)
0- 500(Vee =4.5V)
0- 400(Vee =6.0V)
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Val
Low-Level
Output Voltage
Va.
3-State Output
Ofr -State Current
Input Leakage Current
Quiescent Supply Current
I~
11:\
lee
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
Ia-l =-20IJ. A 4.5
VI:\=
6.0
VIHorVIL
101-1 =-4 rnA 4.5
1m =-5.2mA 6.0
2.0
IOL =20 IJ.A 4.5
VI:\=
6.0
VII IorVIL
IOL -4 rnA 4.5
IOL =5.2mA 6.0
V",; -VIII or VII.
6.0
VOLT =Vee or GND
VI:\ -Vee or GND
6.0
VI:\ -Vee or GND
HC-742
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
1.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
U8
4.31
4.13
5.63
5.68
5.80
0.0
O. I
0.1
O. I
0.1
0.0
V
0.1
0.0
O. I
0.26
0.33
0.17
0.26
0.33
0.18
MIN.
1.5
3.15
4.2
-
-
±0.5
-
±5.0
±O.l
4.0
-
±1.0
40.0
IJ.A
TC7 4HC4094API AF I AF N
TIMING REQUIREMENTS(lnput tr=tf=6ns)
PARAMETER
SYMBOL
,
t\\\111 I
t\nL) I
Minimum Pulse Width
(CLOCK)
Minimum Pulse Width
(STROBE)
I
I t\\"(H)
I
Minimum Set-up Timei
(SERIAL)
ts
Minimum Set-up Timel
(STROBE)
ts
I
Minimum Hold Time
(SERIAL)
Minimum Hold Time
(STROBE)
Clock Frequency
I TEST CONDITION
I
I
!I
i
I)
j
th
I
I
i
!I
i
I
th
!
I
f
!,
!
i
I
Vee
: 2.0
I 4.5
! 6.0
! 2.0
4.5
6.0
! 2.0
i 4.5
! 6.0
2.0
i
! 4. 5
i 6.0
I
2. a
I
I
, 4.5
6.0
I
2.0
! 4.5
i 6.0
2.0
4.5
-6.0
i
HC-743
~
I
I
I
I
I
I
Ta-25°C
TYP.
I, LIMIT
75
I
!
15
iI
13
I
75
II
15
!
I
13
I
75
I
i
15
! 13
i 100
,
20
,
17
-
i
-
!
-
I
-
!
I
I
!
a
a
a
0
a
0
6
30
35
I Ta- 40 -85°C
LIMIT
!
95
I
19
I
16
!
95
II
19
16
i
95
I
!
19
16
I
!
125
I
I
25
I
i
21
1
I
i;
i
,
i
!
!
a
a
0
0
0
:UNIT
i'
;
I
!
I
i
I
!
! ns
i
,
;
,
a
5
24
28
:\1 Hz
TC74HC4094AP/AF/AFN - - - - - - - - - - - - - -
AC ELECTRICAL CHARACTERISTICS(CL =15pF,Vcc =5V,Ta=25"C)
PARAMETER
Output Transition Time
Propagation Delay Time
(CLOCK-Qn)
Propagation Delay Time
(CLOCK -QS,Q'S)
Propagation Delay Time
(STROBE-Qn)
3-State Output
Enable Time
Maximum Clock Frequency
SYMBOL
TEST CONDITION
tTUf
tTl-II.
tptH
toHl
tpLH
tnHL
tpLH
tnHL
tpa.
toZH
fMAX
RL=lKQ
MIN.
TYP.
MAX.
-
4
8
-
22
35
-
16
25
-
16
27
-
13
25
33
73
-
UNIT
ns
MHz
AC ELECTRICAL CHARACTERISTICS(CL=50pF,lnput t r =t,=6ns}
Ta-25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
30
75
95
tTLH
Output Transition Time
8
15
19
tTHL
7
13
16
92
200
250
Propagation Delay Time
tPLH
26
40
50
(CLOCK-Qn)
tpHL
20
34
43
65
150
1~0
Propagation Delay Time
tPLI-I
30
19
38
(CLOCK-QS,Q'S)
tpl1L
15
26
32
ns
75
160
200
Propagation Delay Time
tpLH
20
32
40
(CLOCK-Qn)
tpHL
27
34
16
58
150
190
3-State Output
tpa.
RL=lKQ
16
30
38
Enable Time
tp7J-I
32
13
26
190
35
150
3-State Output
tpLZ
RL=lKQ
30
38
16
Disable Time
tpHZ
32
13
26
6
16
5
Maximum Clock
- MHz
fyV\x
24
30
66
Frequency
28
35
80
Input Capacitance
C I:\
10
5
10
Bus Input Capacitance
pF
Ca.T
10
Cpo(l)
Power Dissipation Capacitance
140
Note (1) ern IS defmed as the value of the internal equIvalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
leetpV=C rn • Va:. f[\ +Ia:
PARAMETER
SYMBOL TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
HC-744
MIN.
TC74HC40102P
-------TC74HC40103P
TC74HC40102P DUAL BCD PROGRAMMABLE DOWN COUNTER
TC74HC40103P 8-BIT.BINARY PROGRAMMABLE DOWN COUNTER
The TC74HC40102 and TC74HC40103 are high speed CMOS PROGRAMMABLE DOWN COUNTER
fabricated with silicon gate C2MOS technology.
They operate ten times as fast as that of metal-gate C2MOS IC (40102/40103B) with
the same power dissipation. Output terminal CO/ZD is placed in active mode at "L"
level when the contents of count become zero. As the TC74HC40102 adopts BCD binary
coded decimal notation, setting up to 99 counts is possible. The 74HC40103 with
8-bits binary construction, can set up to 255 counts. Each type has CI/cE inhibiting
clock, APE asynchronous preset control input, SPE synchronous preset control input
and CLR control input setting counter to maximum counting mode.
All inputs are equipped with protection circuits against static discharge or transient
excess voltage.
FEATURES:
• High Speed ••••••••••••••• fMAX=36MHz(Typ.) at VCC=5V
• Low Power Dissipation ••••••
ICC=4~A(Max.)
at Ta=25°C
• High Noise Immunity ••••••••• VNIH=VNIL=28% VCC(Min.)
r-----------------------~
• Output Drive Capability •••••••••••••• 10 LSTTL Loads
• Symmetrical Output Impedance ••••• IIOHI=IOL=4rnA(min.)
• Balanced Propagation Delays •••••••••••••••
tpLH~tpHL
• Wide Operating Voltage Range ••••••• ·VCC(Opr.)=2V '" 6V
• Pin and Function Compatible with 40102B, 40103B
ABSOLUTE MAXIMUM RATINGS
PARAt-IETER
Supply Voltage Range
SYMBOL
VALUE
-0.5", 7
VCC
---VIN
DC Input Voltage
-0.5'" VCC+O. 5
---_._._-DC Output Voltage
VOUT
-0.5 ",VCc+0.5
.. __ .. _~--"-.-Input Diode Current
±20
11K
1------_._-----_._-- t--::-±20
Output Diode Current
10K
-- I--1-------±25
TOUT
~Output Current
DC VCe/Ground Current
±50
ICC
----_._._--------_._----- r--_---Power Dissipation
PD
500*
Tstg
Storage Temperature
- - . -.....- -TL
Lead Temperature 10sec
-65 '" 150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
°e
°c
DIPl6( 3DI6A-P)
PIN ASSIGNMENT
OLOOK
1~
16
VOO
CLEAR 2
15
SPE
OI/OE 3
14
Oq/ZD
30 4
13
J7
Jl 5
12
J6
J2 6
11
J5
~10
34
~
APE
J3 7
I
GND S[
* 500mW
in the range of Ta=-40°C'V65°C and from Ta=65°C
up to 85°C derating factor of -lOmW/oC shall be applied
until 300mW.
HC-745
(TOP VIEW)
9
TC74HC40102P ________--________________________
TC74HC40103P
TRUTH TABLE
CLEAR
H
CONTROL INPUT
MODE
CI!CE'
APE
SPE
H
H
H
Count inhibit
H
H
H
L
H
H
L
X
H
L
X
X
L
X
X
X
Note 1.
2.
FUNCTIONAL DESCRIPTION
Even if clock is given, no count is
made.
Down count at rising edge of clock.
Data of PI terminal is preset at
rising edge of clock.
Data of PI terminal is asynchronously
preset to clock.
Counter is set to maximum count.
Regular count
SYt).chronous
preset
Asynchronous
preset
Clear
X: Don't care
Maximum count: "99" for TC74HC40102 and "255" for TC74HC40103.
TIMING CHART
CLOCK
n..n..f1..JlJ""L!l-rl-f"l-JlJLJ~
--.I
r1
II
I
I
-.J
I
I
L~
I
I
II
I I I
;16
I
I
Co7ZD
(TC74HC40~02 )
I
I
I
'-SIB
3
2
~
0
99
255 254
3
2
~
0
2551
99
I I I
I
I
I I I
II I! I
I
I
I
II
I I I
I I I
I
I
I
I
I I
;13
;15
I
I
II I
;12
I
98
97
6
5
4
:3
254
253
6
5
4
3
99
98
97
'Number of Count
(TC74HC40~03 )
HC-746
255 254 253
>-3
()
"
.I>-
JO
~
J2
J1
J3
J5
J4
J6
.l>-
J7
e
e
i-'
4
,15 .....
~
9 ...
5
n
Ul
,ill
r-J
FO
~
.......
TE
'--r--
C
1-,,X>--q,;
2
C
c
I
r- J F2
J
":J:
T
1
'"'-..J-
r-J
Q;
I
Q:
j
11
W
.- J
F4
TE
1
13
w
G)
.....
("")
o
.....
)::>
G)
~
A
W
F3
TE
12
11
110
W
ii
TE
1
Il~r-
10
L
I I
Q;
TE
~
w..
IL~
F1
Q;
7
.-I)
'7
,-J
:c
(")
6
,o
F5
!Eli,
LLL
L:.'
-
J
,1'-
F6
ii
TE
1
ill
F7
TE
T
~
J
Q:
T
1
.4
'1
CO/ZD
,3
,/
~
1
p
~
f-
n~
fT
~
-1-1
00
~~
~~
:::J::::J:
00
~~
99
00
WI\)
"'0"'0
t-:l
C')
......
.t:-
JO
Jl
4,
J2
J3
6
7
5
-_,,15....
~
9 ....
r--1>
'7
I
Jl
C":I
~
OL
-J
Fl
FO
TID
ii
TID
-r-
'-I
T
1
1
OL
c-J
F2
TE Q.
00
L
LL..
r-J
r--J
::J:
J
ill
Q.
10
W
W
,
Q.
I
::r:
("")
C
b
13
N
II
ill
F5
TE Q;
Q;
:r
I
I
-Ll..
r-J
-
,J
F6
Q.
TID
T
Jl
F7
TID
Q.
T
I
4,
"
3
'ii7
'ii7
~
rJ?
JT
>--
~~
:e:e
~~
99
""
2
,....,
~
............
WI\)
007ZD
01
.....
~
-1-1
00
00
-J
F4,
TID
"i
12
C')
o
J7
G)
.....
.t:-
OA
r-J
F3
J6
11
r-
TID
1
J5
11n
2,
~
J4,
r0
lhl
1
--
£, __1
-~
____________________________________ TC74HC40102P
TC74HC40103P
D
SPE
CK
R
Q.
Q.
;r
SPE
CLR
APE
TE 0
CC=TE
INPUT
CLEAR APE SPE J
TE
SPEO
r=;o:SPE
SPE
CK
OUTPUT
TE CLOCK
Q.n+ 1
L
L
X
X
X
X
X
H
X
L
X
X
L
H
L
L
X
H
X
X
H
H
H
X
H
L
L
L
H
H
X
H
H
L
X
X
H
H
H
X
L
S
S
L
S
H
H
H
X
H
X
L
H
Q.n
'l.n
'l.n
FUNCTIONAL DESCRIPTION
The TC74HC40l02 and TC74HC40l03 are 8-stage preset table synchronous down counters.
Carry Out/Zero Detect (CO/ZD) is output at the "L" level for the period of 1
bit when the readout becomes "0".
The TC74HC40102 adopts binary coded decimal nota-
tion, making setting up to 99 counts possible.
While the TC74HC40103 adopts 8-bit
binary counter and can set up to 255 counts.
COUNT OPERATION
At the "H" level of control input of CLEAR, SPE and APE, the counter carries out
down count operation one by one at the rise of pulse given to CLOCK input.
Count
operation can be inhibited by setting Carry Input/Clock Enable (CI/CE) to the "H"
level.
HC-749
TC74HC40102P __________________________________
TC74HC40103P
(Continued)
CO/ZD is output at the "L" level when the readout becomes "0", but is not output even
if the readout becomes "0" when CI/CE is at the "H" level, thus maintaining the "H"
level.
Synchronous cascade operation can be carried out by using CI/CE input and CO/ZD
output.
The contents of count jump to maximum count (99 for the TC74HC40102 and 255 for the
TC74HC40103) if clock is given when the readout is "0".
Therefore, operation of 100-
frequency division and that of 256-frequency division are carried out for the
TC74HC40102 and TC74HC40103, respectively, when clock input alone is given without
various kinds of preset operations.
PRESET OPERATION AND RESET OPERATION
When Clear (CLEAR) i?put is set to the "L" level, the readout is set to the
maximum count independently of other inputs.
When Asynchronous Preset Enable (APE)
input is set to the "L" level; readouts given on JO to J7 can be preset asynchronously
to counter independently of inputs other than CLEAR input.
When Synchronous Preset
Enable (SPE) is set to the "L" level, the readouts given on JO to J7 cim be preset to
counter synchronously with the rise of clock.
As to these operation modes, refer to the truth table.
INPUT and OUTPUT
EQUIVALENT CIRCUIT
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
SYMBOL
Vce
VIN
VOUT
Topr
LIMIT
2"'6
0", Vee
0", Vee
-40'" 85
t r • tf o-qOOO (Vee=2. OV
o '" 500 (Vee=4. 5V)
o '" 400 (Vec=6. ov
HC-750 -
UNIT
V
V
V
°e
ns
-,
I
INPUT
*
I
OUTPUT
TC14HC40102P
----------------TC74HC40103P
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYHBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
VIN=VIH
VOH
Low-Level
Output Voltage
Input Leakage
Current
Quiescent
Supply Current
TEST CONDITION
VOL
or VIL
IOH=-20lJA
MIN.
2.0
4.5
6.0
1.5
3.15
4.2
-
-
-
2.0
4.5
6.0
-.
-
-
0.5
1. 35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
2.0
4.5
6.0
-
1.9
4.4
5.9
4.18
4.31
5.68
5.80
-
0.0
0.0
0.0
0.1
0.1
0.1
4.5
IOW- 4mA
IOH=-5.2mA 6.0
VIN=VIH
IOL=2011A
2.0
4.5
6.0
or VIL
IOL=4mA
IOL=5.2mA
4.5
6.0
-
-
-
0.17 0.26
0.18 0.26
1.5
3.15
4.2
-
0.5
1. 35
1.8
V
V
4.13
-
5.63
-
-
0.1
0.1
0.1
-
0.33
0.33
-
-
VIN=VCC or GND
6.0
-
-
±0.1
-
±1.0
ICC
VIN=VCC or GND
6.0
-
-
4.0
-
40.0
PARAMETER
SYHBOL TEST CONDITION
VCC
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
tTHL
Propagation Delay Time
2.0
tTLH
(CLOCK - CO/ZD)
V
lJA
(CL=50pF , Input t r =tf=6ns)
Output Transition Time
Propagation Delay Time
V
-
lIN
AC ELECTRICAL CHARACTERISTICS
(APE - CO/ZD)
Ta=25°C
Ta--40",85°C
UNIT
TYP. MAX. MIN. MAX.
VCC
tpLH
tpHL
tpLH
tpHL
HC-751
MIN.
-
Ta 25°c'
Ta--4O'V85°C
UNIT
TYP. MAX. MIN. MAX.
30
75
8
7
128
32
27
156
39
33
15
13
245
49
42
300
60
51
-
95
19
16
305
61
52
375
75
64
ns
TC74HC40102P
TC74HC40103P----------------
AC ELECTRICAL CHARACTE RI STICS
PARAMETER
Propagation Delay Time
(CLEAR - CO/ZD)
Propagation Delay Time
(CI/cE - CO/ZD)
(Continued)
SYMBOL TEST CONDITION
tpLH
tpLH
tpHL
Maximum Clock Frequency fMAX
Minimum Pulse Width
(CLOCK)
tW(H)
tw(L)
Minimum Pulse Width
(CLEAR, APE)
Minimum Removal Time
(CLEAR, APE)
tw(L)
Minimum Set up Time
(CI/CE - CK)
Minimum Set up Time
(In - CK)
ts
is
ts
Minimum Set up Time
(In - APE)
ts
Minimum Hold Time
(All Inputs)
Input Capacitance
Power Dissipation
Capacitance
th
CIN
CPD(l)
74HC40102
74HC40103
HC-752
'Ta=25°C
Ta=-4*
5<>*
10\6
VCC
VOH
CLOCK
GND
VOL
tpLH
CQ/Zl)
VOL
WAVEFORM 4
WAVEFORM 3
6ns
c
D~:
VOR
6ns
6ns
6ns
VCC
VCC
CJ;/CE
GND
GND
VCC
VOH
CLOCK
GND
VOR
VOL
HC-753
CO/ZD
VOL
tpHL
pLH
TC74HC40102P _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC40103P
SWITCHING CHARACTERISTICS TEST WAVEFORM
(Continued)
WAVEFORM 6
WAVEFORM 5
vee
In
aND
Vee
~~
APE,
CLOCK
CLOCK
aND
~
vee
aND
Vee
,/£
aND
I ts
>C
**
F/F OUTPUT
( ** F/F
**
F,/F OUTPUT
>C
output is interna.l signa.l 01: IC)
ICC(Opr.) TEST CIRCUIT
5V
P. a
Input transition time is
the same as that in case
of switching characteristics
test.
1-..----1
c::o
10
HC-754
__________________________________ TC74HC4m02P
TC74HC4m03P
EXAMPLE OF TYPICAL APPLICATION
PROGRAMMABLE DIVIDE-BY-N COUNTER
VCC
fIN
• fOUT= N+1
JO
• Timing chart when N="3"
(JO, Jl=VCC, J2"'J7=GND)
N
J7
COUNT
1/2 to 1/100 are
dividable.
1/2 to 1/256 are
dividable.
• TC74HC40102P
• TC74HC40103P
PARALLEL CARRY CASCADING
CLOCK
INHIBIT
'CJ7Ci'
CLOOK
CCVZDI-----1 CVCi" CO)ZD 1-----fiil7CE CCVZD I--_r-....
CLOCK
CLOCK
CLOCK o-~--------------~---------~-------~
*At synchronous cascade connection, huzzerd occurs at CO output after its second
stage when digit place changes, .due to delay arrival. Therefore, take gate from
TC74HC32 or the like, not from CO output at the rear stage directly.
PROGRAMMABLE TIMER
ts
VCC
SET
JO
OLEAR
OUT
SPE
N
OUT
..
J7
fIN
-r-rIJ
..JI-
tw
L
'I
N
tw = (fIN + t s )
Note: The above formula does not take
into account the phase of clock
input. Therefore, the real pulse
width is the distance between the
above formu1a-1/fIN'" the above
formula.
HC-755
TC74HC40105AP/AF-----TENTATIVE
FIFO 4 Bit X 16 Word REGISTER
The TC74HC40105A is a high speed CMOS 4bit x 16 word
first-in, first-out (FIFO) Storage register fabricated with
silicon gate C2MOS technology.
It achieves the high speed operation while maintaining
the CMOS low power dissipation.
The device is capable of handling 16 four-bit words and
it is possible to handle the input and output data at
different shifting rates.
Wh'm the DATA-IN-READY (DIR) is high, data is
written into the registers by a low to high transition of the
SHIFT IN (SI) input. And when DATA-OUT-READY
(DOR) is high, data is read out of the registers by a high
to low transition of the SHIFT OUT (SO) input.
If the MASTER RESET (MR) is high, the DIR goes
high and DOR goes low. The data in the internal registers
are not changed but are declared invalid.
The TC74HC40105A can be cascaded to form longer
registers or wider words.
The DATA OUTPUTs (qn) are 3-State Outputs. When
OUTPUT ENABLE (OE) is held high, the Qn's are in
high impedance state.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP16-P-300A)
16~
F( SOP 16-P-300)
PIN AS!)IGNMENT
OE 1
16 Vee
15 SO
OIR 2
SI 3
1400R
004
13 00
01 5
12 01
1>26
1102
0]7
10 03
9 MR
GNO 8
FEATURES:
• High Speed ................................. fMAX=25)..!Hz(typ.)at Vcc=5V
• Low Power Dissipation ···············4 tt A(Max. )at Ta=25"C
• High Noise Immunity·················· VI\1H=V:XIL =28" Vcc(Min.)
• Output Drive Capability············ ... 10 LSTTL Load
{ lO(For DIR, DOR)
15(For Qo-Q 3)
• Symmetrical Output Impedance .•.
{ lIm I=IOL =4mA(Min.)(For DIR, DOR)
lIm I=IOL =6mA(Min.)(For QO-Q3)
• Balanced Propagation Delays ...... t pLH " tpI-JL
• Wide Operating Voltage Range ....•. Vcc (opr)=2V-6V
HC-756
(TOP VIEW)
TC74HC401 OSAP I AF
SYSTEM DIAGRAM
...
SI
Go
Q,
--
_,
_..
I
_3
1
L _ _ """I
a,
~------4·RU~----a,
Word l'
TIMING DIAGRAM
1V///hfll\lALIM VUM
SHIFT"
C*"
0
~IN
A
II
1-fl-Illl--1l J
=-
=-
II Vcc· 4.5V
alVCG-4.5V
DATA INPUT
READY
......
DATA OUTPUT
OATAIN
CDo)
-
DATAOUt'
cOn)
r r-
~
rh- I-J
1
I
0
1
1
~
..... J
jdJ
n.
1
1
0
~
0
~
~iL wo
1
0
!
I
~ ~
h- f-~
II
o
W..::WY&ff~ff.&6.
0
1
~
IL~
UN KNOWN
Z : High Imped.nce
HC-757
1
I
INVALID
TC74HC4010SAP/AF - - - - - - - - - - - - - - -
BLOCK DIAGRAM
SHiFt IN
CLOCK
SHIFT OUT
CLOCK
'i:
MASTER
RESET
(MR)
r
0,
DATA
0.
03
9
_--L-
-
CONTROL
LOGIC
~/
5
4X16
6
DATA
REGISTER
7
'I
2
DATA-INPUT-READY
(DIR)
14
DATA-OUTPUT-READY
(DOR)
1
I
-\
r/
13
OUtpUT
BUFFER
(3-STATE)
OUTPUT ENABLE
(OE)
00
12
0,
11
a.
10
OJ
FUNCTIONAL DESCRIPTION
1) WRITING DATA
Data can be written into the FIFO whenever DIR is high and a low to high transition occurs on the SI pin.
DIR will toggle momentarily until the data has been transferred to the second word register.
SI must be toggled before the next 4-bit word can be written. The first and subsequent words will
automatically ripple to the output end of the device even if there is not a full 16 words of input data. When all 16
words are filled with data. DIR will go low and additional data cannot be written into the device.
2)
READING DATA
When a data word appears in the sixteenth data register (just before the output buffer). DOR goes high and. if
OE is low. data can be output on the high to low transition of SO.
The data remaining in the registers now ripples to the next higher word position opening the first word
position for new data. DIR goes high and additional data can be written in. During the output of data. DOR
toggles momentarily after each read. When the data registers become empty. DOR goes low and SO is ignored.
3)
MASTER REST
When a high is input to MR. the internal control logic is initiallized. This causes DIR to go high and DOR to
go low. The contents of the data registers are not changed. but are invalid and will be written over when the
first word is loaded.
4) CASCADING
The TC74HC40105A can be cascaded to form longer registers simply by connecting DOR of the first device to
SI of the second and DIR of the second device to SO of the first. Additional devices may be cascaded by
repeating the above. Of course. the Qn outputs of the first device must be connected to the Dn inputs of the
second.
In this mode. an MR pulse must be applied after the supply voltage is turned on. For words wider than 4bits. the DIR and DOR outputs from each FIFO must be ANDed respectively and the SI and SO inputs must each
be paralleled.
HC-758
TC74HC40105AP/AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Uutput Current
(DIR,DOR)
'(QO-Q3)
DC Vcr;/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vcr;
VIr>;
VOlJr
11K
10K
VALUE
-0.5-7
-0.5 -Vcr; +0.5
-0.5 -Vcr;+0.5
±20
±20
UNIT
V
±25
±35
±75
rnA
IQl;T
Icr;
Po
Tstg
TL
,v
V
rnA
rnA
500(DIP)*/180(SOIC)
rnA
mW
-65 -150
300
"C
"C
*5()()m W in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-10m WI'C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
0- Vcr;
0- Vcr;
-40 - 85
0- 1000(Vcr;=2.0V)
0- 500(Vcr;=4.5V)
0- 400(Vcr;=6.0V)
SYMBOL
Vcr;
VIN
VOlJr
Topr
tr , tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
TEST CONDITION
VIN=
VIHorVn.
VOH
(DIR) 101 --4 rnA
DOR 101 =-5. 2mA
IOH --6 rnA
QO-Q3
VIN =
VIHorVIL
Low-Level
Outp?t Voltage
VOL
3 State Output
Off-State Current
1(Jl
Input Leakage Current
Quiescent Supply Current
11:,\
Icr;
la~ =-20Jl.A
1~=-7.8mA
lOt. =20 Jl. A
(DIR) 10. -4 rnA
DOR la. =5.2mA
101 • -6 rnA
QO-Q3
IOL =7.8mA
V 1:,\ -v IH or V IL
VWf =Vcr; or GND
V 1:,\ -Vcr; or GND
V 1:,\ -Vcr; orGND
Ta--40 -85"C
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
4.5
4.4
6.0
5.9
V
4.31
4.13
5.80
5.63
4.31
4.13
5.8d
5.63
0.0
0.1
0.1
0.0
O. 1
0.1
0.0
0.1
0.1
V
0.33
0.17
0.26
0.26
0.33
0.18
0.26
0.33
O.p
0.26
0.33
0.18
Vcr;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
4.5
6.0
MIN.
1.5
3.15
4.2
6.0
-
-
6.0
6.0
-
-
HC-759
-
1.9
4.4
5.9
4.18
5.68
4.18
5.68
-
-
-
±0.5
-
±5.0
±O.l
4.0
-
±1.0
40.0
-
Jl.A
TC74HC40105AP/AF - - - - - - - - - - - - - - -
TIMING REQUIREMENTS(lnput tr=tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(SI)
tW(L)
tW(H)
Minimum Pulse Width
(SO)
tW(L)
tW(H)
Minimum Pulse Width
(MR)
tW(L)
twO i )
Minimum Set-up Time
(DATA-SI)
ts
Minimum Hold Time
(DATA-SI)
In
Minimum Removal Time
(MR-SI)
t rem
Clock Frequency
f
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta-25"C
LIMIT
TYP.
75
15
13
75
15
13
75
15
13
0
0
0
100
20
17
50
10
9
3
15
18
Ta- 40 -85"C UNIT
LIMIT
95
19
16
95
19
16
95
19
16
ns
0
0
0
125
25
21
65
13
11
24
MHz
12
13
AC ELECTRICAL CHARACTERISTICS(CL=15pF,Vcc=5V,Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
(DIR,DOR)
Propagation Delay Time
(SO,MR-DOR)
Propagation Delay Time
(SO-DIR)
Propagation Delay Time
(SI,DOR)
Propagation Delay Time
(SI-DIR)
Propagation Delay Time
(MR-DIR)
tTLH
TEST CONDITION
MIN.
TYP.
-
4
8
tpHL
-
22
39
tpLH
-
242
365
tpLH
-
187
300
tpHL
-
22
35
tpLH
tcHL
-
25
39
tTHL
He-760
MAX.
UNIT
ns
TC74HC40105AP IAF
AC ELECTRICAL CHARACTERISTICS(lnput t r =tf=6ns)
Ta 40 -85t:
TEST
Ta 25t:
PARAMETER
SYMBOL
UNIT
CONDITION CL
Va; MIN. TYP. MAX. MIN. MAX.
Output Transition Time
(Qo-Qa)
tll.H
tTIiL
50
Output Transition Time
(DIR,DOR)
tll.H
tTIiL
50
Propagation Delay Time
(SO,MR-DOR)
tpHL
50
Propagation Delay Time
(SO-DIR)
tpLH
50
Propagation Delay Time
(SI-DOR)
tpLH
50
Propagation Delay Time
(SI-DIR)
tpHL
50
Propagation Delay Time
(SO-Qn)
Propagation Delay Time
50
tpUf.
tpHL
150
50
(SI-Qn)
tpLH
tpHL
Propagation Delay Time
(MR-DIR)
tpLH
tpHL
Output Enable time
tpZL
tpZH
150
50
50
RL = 1 kQ
150
Output Disable time
tpLZ
tpHZ
RL = 1 kQ
50
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
HC-761
-
-
-
-
-
21
7
6
24
8
7
84
28
24
798
266
226
624
208
177
78
26
22
156
52
44
171
57
48
612
204
173
627
209
178
87
29
25
45
15
13
60
20
17
32
16
14
60
12
10
75
15
13
225
45
38
2000
400
340
1650
330
280
200
40
34
400
80
68
440
88
75
1500
300
255
1540
308
262
225
45
38
125
25
21
165
33
28
125
25
21
-
-
-
-
-
-
-
-
-
75
15
13
95
19
16
280
56
48
2500
500
425
2060
412
350
250
50
43
500
100
85
550
110
94
1875
375
319
1925
385
327
280
56
48
155
31
26
205
41
35
155
31
26
ns
TC74HC401 05AP I AF
AC ELECTRICAL CHARACTERISTICS(lnput t r =tf=6ns}(Cont'd)
TEST
Ta-25"C
Ta- 40 -85"C
PARAMETER
SYMBOL
UNIT
CONDITION CL Va:; MIN. TYP. MAX. MIN. MAX.
2.0
3
7
2.4
50 4.5
22
12
15
Maximum Clock
6.0
26
14
18
MHz
f MAX
.2.0
2.6
6
2
Frequency
150 4.5
20
13
10
6.0
15
24
12
2.0
95
Output Pulse Width
tW(H)
50 4.5
25
(DIR)
tw(L)
6.0
21
ns
95
2.0
Output Pulse Width
tW(H)
25
50 4.5
(DOR)
tW(L)
21
6.0
Input Capacitance
5
10
10
CIN
Output Capacitance
pF
10
COLT
CR)
(a: 1)
300
Power Dissipation ClIJIacitance
Note (l) Cpo is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia:;q,d=CPD • Va:;' fN +Ia:;
HC-762
------TC74HC4511AP I AF
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER
The TC74HC4511A is high _speed CMOS BCD-TO-7
SEGMENT LATCH/DECODER/DRIVER fabricated with
silicon gate C 2l\10S technology.
It achieves the high speed operation similar to
equi\'alent LSTTL while maintaining the CMOS low power
dissipation.
The segment output driver, which is of CMOS
construction, has a large 1011 capability which permits the
device to drive cathod.e common LED directly.
When lamp test (LT) is held low, all segment outputs
will go high, and when the blanking input (BI) is held low
and LT is held high, all segment outputs will go low.
These functions are independent of other inputs and used
to test the display.
BI is used to pulse-modulate the brightness of the
display.
When error code (over 10) is applied to BCD inputs, all
segment outputs will go to low (turn off).
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
1
P(DIP16-P-300A)
16~
F(SOP16-P-300)
PIN ASSIGNMENT
B 1
16 Vee
C 2
15
LT 3
FEATURES:
• High Speed .............................. tpd=23ns(Typ.)at Vee=5V
• Low Power Dissipation ............ Iee =4I1A(Max.)at Ta=25°C
• High ~oise Immunity .. ··· .... · .... · V:-\JWV:\JL =28% VceUl'1in.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance ... I IOH I =20mA
• Wide Operating Voltage Range'" Vee (opr.)=2V-6V
• Pin and Function Compatible with TC4511B
Bi
14 9
4
13 a
LE 5
12 b
o
6
11 c
A 7
10 d
GND 8
9 e
(TOP VIEW)
lEe LOGIC SYMBOL
BCOI7·SEG t>
[T]
VII
DISPLAY MODE
Bi
Gl0
LE
C9
A
90
.10.11
bl0.ll
cl0.ll
dl0.11
.10.11
110.11
g10.11
[T] :
HC-763
(13)
(12) :
(11)
(10) ~
9
e
f
9
TC74HC4511AP/AF - - - - - - - - - - - - - - -
BLOCK DIAGRAM
B
C
a
....
A
....
iii
...
I
b
z
::r:
e::
w
we::
o::!!w
....U
.... " 0
IwO
OcnU
w
U
d
e::
e
0
III ,... 0
0
9
Bi
LE
LT
TRUTH TABLE
OUTPUTS
INPUTS
DISPLAY
MODE
LE
BI
LT
D
C
B
A
a
b
c
d
e
r
g
*
*L
*L
L
*
*L
*
*L
H
H
H
H
H
H
8
L
L
L
L
L
L
BLANK
H
*
*L
L
H
*
*L
H
H
H
H
H
H
H
H
L
0
L
H
H
L
L
L
H
L
H
H
L
L
L
L
1
L
H
H
L
L
H
L
H
H
L
H
H
L
H
2
L
H
H
L
L
H
H
H
H
H
H
L
L
H
3
L
H
H
L
H
L
L
L
H
H
L
L
H
H
4
L
H
H
L
H
L
H
H
L
H
H
L
H
H
5
L
H
H
L
H
H
L
L
L
H
H
H
H
H
6
L
H
H
L
H
H
H
H
H
H
L
L
L
L
7
L
H
H
H
L
L
L
H
H
H
H
H
H
H
8
H
H
H
H
L
L
H
H
9
*
*
*
L
L
L
L
L
L
L
BLANK
L
L
L
L
L
L
BLANK
L
H
H
H
L
L
L
H
H
H
L
H
L
H
H
H
H
H
H
H
*
*
*
*
*
Don't care
,
L
Hold the stage at the leading edege or LE
HC-764
TC74HC4511AP/AF
LOGIC DIAGRAM
..
c
.a
u
W
..J
()
HC-765
TC74HC4511AP/AF - - - - - - - - - - - - - - - ABSOLUTE MAXlMUM RATINGS
I SYMBOL
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
~;Lead Temperature 10sec
Vee
VI\
VO\,T
11K
10K
IOLT
lee
PI)
Tstg
TL
VALUE
-0.5 -7
-0.5 -V(,'(;+0.5
-0.5 -Vee+0.5
±20
±20
+25(Sinc)/-35(Source)
+150(I ee )/-50(l c;\D)
500(DIP)*1lB0(SOIC)
-65 -150
300
UNIT
\',
V
V
rnA
rnA
rnA
rnA
rnW
I
*500m W in the range of Ta =
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
- 10m WI"C shall be applied
untiI300mW.
"C
°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
SYMBOL
tr, tr
Input Rise and Fall Time
UNIT
V
V
V
°C
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o- 1000(Vee =2.0V)
0- 500(Vee =4.5V)
o- 400(Vee=6.0V )
Vee
VI\
VO\,T
Topr
ns
i
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VII.
TEST CONDITION
IOH =-20# A
High-Level
Output Voltage
V[,,=
VIHorVII .
Val
I
Low-Level
Output Voltage
3 State Output
Off -State Current
Input Leakage Current
Quiescent Supply Current
VClL
lev.
11\
Icc
VI\=
VIHorVII .
Ial --4 rnA
Ia; =-20 rnA
Ia; =-7. 2rnA
10\, =20 #A
IClL -4 rnA
Ia. =5.2rnA
V I\ -VIH or V IL
VO\,T =Vcc or GND
VI\ -Vee or GND
V 1\ -Vee or GND
Ta-25°C
Ta- 40 -85"C IUNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.5
4.4
4.4
6.0
5.9
5.9
V
-4.31
4. 13
4.18
- !
3.20
3.80
2.90
5.68
5.63
5.80
I
0.0
0.1
0.1
0, 1
0.0
0.1
0.0
0.1
O. 1 I V
0.17
0.26
0.33
0.18
0.26
0.33
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
4.5
6.0
2.0
4. 5
6.0
4. 5
6. 0
MIN.
1.5
3.15
4.2
6.0
-
-
±0.5
-
6.0
6.0
-
-
±O.I
4.0
-
HC-766
I
I
-
-
i
±5.0
±1.0i#A
40.0 i
TC74HC4511AP/AF
TIMING REQUIREMENTS(lnput t r =tf=6ns)
PARAMETER
SYMBOL
Minimum Pulse Width
(LE)
tW(L)
f--
Minimum Set-up Time
ts
Minimum Hold Time
th
TEST CONDITION
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta--40 -85"C
UNIT
LIMIT
95
19
16
95
ns
19
16
0
0
0
Ta-25"C
TYP.
LIMIT
75
15
13
75
15
13
0
.0
0
AC ELECTRICAL CHARACTERISTICS(C L =15pF ,Vcc=5V ,Ta=25"C)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
Output Transition Time
t11.H
-
4
8
Output Transition Time
t 11-11.
-
4
8
Propagation Delay Time
(BCD-Segment)
Propa~tion Delay Time
(BI -Segment)
Propaf¥ion Delay Time
( T-Segment)
Propagation Delay Time
(LE-Segment)
tpLH
tpi-lL
tpLH
tpHL
-
28
45
-
18
31
tpu-i
-
12
21
-
26
44
tpI-IL
tpLH
toHL
HC-767
UNIT
ns
TC74HC4511AP/AF - - - - - - - - - - - - - - - -
AC ELECTRICAL CHARACTERISTlCS(C L =50pF,lnput t r =t,=6ns)
Ta-25"C
Ta- 40 -85"C
PARAMETER
U~IT
SYMBOL TEST CO~DITIO~
Vee MIN. TYP. MAX. MIN. MAX.
25
60
75
2.0
Output Transition Time
7
12
tT1.I1
4.5
15
Low to High
6.0
6
13
11
30
75
95
2.0
Output Transition Time
8
4.5
15
19
t111L
High to Low
6.0
7
13
16
125
255
320 I
2.0
Propagation Delay Time
tlll.lI
33
51
4.5
'64
(BCD-Segment)
tpJlL
6.0
23
43
54
ns
70
175
220
2.0
Propagation Delay Time
tpUI
22
4.5
35
44
(BI-Segment)
tpilL
6.0
30
17
37
120
60
150
2.0
Propagation Delay Time
tpLiI
4.5
15
24
30
(LT-Segment)
tpHL
6.0
12
20
26
95
240
300
2.0
Propagation Delay Time
tpLiI
4.5
32
48
60
(LE-Segment)
t(lHL
6.0
23
41
51
Input Capacitance
C!:'..;
10
10
5
pF
Power Dissipation Capacitance
CPD(l)
Note (l)
95
Note (1) C rD is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
ICCq,o=C PD' VOC· f 1,\ +1 OC
HC-768
TC74HC4511AP/AF
APPLICA TlON CIRCUIT
Static Display Circuit
Recommended Resistance R
""1""---'--- 5V ± 10%
LED Display
Vee
,----l
I
t-<
a
LT
L-(Bi
B~~
Rx7
b
0----., A
e
~
d
1
e
I ..
o----lLE
~
1----'lM---t.-~-.!.'r-;
~
I
GND
9
I
~.
f
LE
.
.::
~
J
,
I
R
DISPLAY
,Jr
TLR358T
Red
TLR362T
"
14.2
TLR332T
/I
7.6
TLR342T
"
TLG358T
Green
TLG362T
/I
13.4mm
10.9
13. 4mm
14.2
I
L __ J
HC-769
390r!
TLG332T
II
7.6
TLG342T
"
10.9
160r!
TC74HC4514AP
TC74HC4515AP------TC74HC4514AP 4-TO-16 LINE DECODER/LATCH
TC74HC4515AP 4-TO-16 LINE DECODER/LATCH (IN V.)
The TC74HC4514A/TC74HC4515A are high speed CMOS
4- LINE TO 16-LINE DECODER WITH LATCHED
INPUTs fabricated with silicon gate C 2MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOSlow power
dissipation.
The selected output is enabled by a low on the inhibit
input (INHIBIT). A binary code stored in the four input
latches (A thru D) is decided and provides a high level
(HC4514A) or a low level (HC4515A) at the corresponding
one of sixteen outputs. When the INHIBIT is held low. all
outputs are kept low (HC4514A) or high (HC4515A).
however. the latch function is available.
The data applied to the data inputs are transferred to
the outputs of-latches when the strobe input is held high.
When the strobe input is taken low. the data is retained at
the output of the latches.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed .............................. tpd =18ns(typ.)at Va.; =5V
• Low Power Dissipation ............ 1a.;=4ttA(Max.)at Ta=25"C
• High Noise Immunity ............ · .. Vi\!IH =VNIL2896 Va.; (Min.)
• Output Drive Capability .. ·· ........ 10 LSTTL Loads
• Symmetrical Output Impedance ... , IOH' =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpLH'" tpHL
• Wide Operating Voltage Range'" Va.; (opr.)=2V-6V
• Pin and Function Compatible with 4514B/4515B
24
P(DIP24-P-300)
PIN ASSIGNMENT
STROBE 1
24
A 2
B 3
S7 4
S6
21 C
20
6
S5 6
ST (1) CZO
18
S3 8
17 S9
SI 9
16 S14
S2 10
16 S15
so 11
14 S12
GND 12
13 S13
(TOP VIEW)
TC74HC4515A
ST
(1)
czo
XIV
ST
A
A
B
C
B
C
o
iNH
o
He-770
(1)
sa
S4 7
NOTE: In case of TC74HC4515A SO-SI5
TC74HC4514A
OMUX
S10
19 Sl1
IEC LOGIC SYMBOL
XIV
Vcc
23 INHIBIT
22 0
czo
OMUX
ST
(1)
czo
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC4514AP
TC74HC4515AP
TRUTH TABLE
INPUTS
SELECTED OUTPUTS
INHIBIT
A
B
C
D
TC74HC4514A-" W
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
So
~o
OX: Don't Care
51
51
52
o STROBE=" H"; REFER TO
52
53
53
H
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
H
H
H
H
X
X
X
X
H
TC74HC4515A-"L"
54
54
55
56
55
55
57
51
TRUTH TABLE
o STROBE="H"
tn~l
--'14-1'-I
tn
STROBE
Sa
sa
59
59
Data at the negative going transition
510
"S10
of strobe shall be provided on each
511
"S11
output while strobe is held low.
512
513
"S12
"S13
514
"S14
515
515
ALL OUTPUrL"
ALL OUTPUT"W
SYSTEM DIAGRAM
INHIBIT
TC74HC4514A
23
11
50
51
A
10
52
53
54
B
55
5&
57
II
C
17
0
STROBE
--L-{>o
51
59
20
510
19
14
511
512
13
513
16
514
515
~ - - - - - - - - - - - - - ..J"
NOTE: In case of TC74HC4515A
HC-771
r--------------,
I
--
~50-515
L _____________ .J
TC74HC4514AP _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC4515AP
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vcr:,/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature 10sec
VALUE
-0.5 -7
-0.5 -Vcr:,+0.5
-0.5 -Vcr:,+0.5
±20
±20
±25
±50
500(DIP)*
-65 -150
300
SYMBOL
Vcr:,
VIN
Voor
11K
10K
lour
lcr:,
PD
Tstg
TL
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-lOmWI"C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
UNIT
V
V
V
"C
VALUE
2-6
o -Vcr:,
o -Vcr:,
-40"" 85
o - 1000(Vcr:,=2.0V)
0- 500(Vcr:,=4.5V)
o - 400(Vcr:,=6.0V)
SYMBOL
Vcr:,
VIN
VCJljT
Topr
tr, tr
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Vm
Low-Level
Output Voltage
VOL
InDut Leakagl! Current
Quiescent Supply Current
lIN
Icc
TEST CONDITION
VIN=
VIHorVIL
VIN =
VIHorVIL
1m =-20/.lA
1m --4 rnA
1m =-5.2rnA
IOL =20 /.lA
IOL -4 rnA
IOL =5.2rnA
VIN -Vcr:, or GND
"It\: =VCC or GND
Vcr:,
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
60
6.0
HC-772
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
l. 35
1.8
1.8
l.9
2.0
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.31
4.13
4.18
5.68
5.80
5.63
0.1
0.1
0.0
0.1
0.1
0.0
V
0.1
0.0
0.1
0.17
0.33
0.26
0.18
0.33
0.26
+0 1
+1 0
/.lA
4.0
40.0
MIN.
l.5
3.15
4.2
-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TC74HC4514AP
TC74HC4515AP
TIMING REQUIREMENTS(lnput tr=t,=6ns)
PARAMETER
SYMBOL
Minimum Pulse Width
(STROBE)
tW(H)
Minimum Set-up Time
(DATA)
ts
Minimum Hold Time
(DATA)
th
TEST CONDITION
Vcr.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta--40 -85"C
UNIT
LIMIT
95
19
16
65
ns
13
Ta-25"C
LIMIT
TYP.
75
15
13
50
-
10
11
9
5
5
5
5
5
5
AC ELECTRICAL CHARACTERISTICS(C L =15pF. Vcc=5V. Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tID!
tTl-IL
tpLH
toHL
tpLH
tDHL
tpUi
t ol·ll.
Propagation Delat Time
(DATA-Sn, Sn)
Propagation Delay Time
(STROBE-Sn, Sn)
Propagation Delay Time
(lNHIBIT-Sn Sn)
TEST CONDITION
MIN.
TYP.
MAX.
;-
4
8
-
18
30
-
20
30
-
16
30
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(lnput t r =t,=6ns)
TEtlT
Ta- 40 -85"C
Ta-25"C
PARAMETER
SYMBOL
UNIT
CONDITION CL
Vcr. MIN. TYP. MAX. MIN. MAX.
2.0
75
95
30
tID!
Output Transition Time
4.5
50
8
15
19
tTIiL
6.0
7
13
16
2.0
220
65
175
Propagation Delay Time
tpUi
4.5
50
22
44
35
(DATA-Sn, Sn)
tpHL
6.0
19
30
37
ns
2.0
220
75
175
Propagation Delay Time
tpLH
4.5
50
24
35
44
(STROBE-Sn, Sn)
tpHL
6.0
20
30
37
2.0
60
175
220
Propagation Delay Time
tpUi
.50
4.5
20
35
44
(INHIBIT-Sn, Sn)
tpHL
6.0
37
17
30
Input Capacitance
CIN
5
10
10
pF
Power Dissipation Capacitance Cro(l)
61
Note (1) C ro is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
iccWIFCro • Vcr.. fIN +Ia:
HC-773
TC74HC4518P
TC74HC4520P/F
TC74HC4518P/F DUAL BCD COUNTER
TC74HC4520P/F DUAL 4-BIT BINARY COUNTER
The TC74HC4518 and. TC74HC4520 are high speed CMOS DUAL BCD/4-BIT BINARY COUNTER
fabricated with silicon gate C2MOS technology.
It operates ten times as fast as that of metal-gate C2MOS IC (45l8B/4520B) with the
same power dissipation.
Since both of TC74HC4518 and TC74HC4520 contain two independent circuits of counters
with the same functions in one package, counting or frequency division of two BCD
digits or eight binary bits can be achieved with one IC. The counters can be reset
to "0" (Qo '" Q3="L") by giving "H" level signal to CLEAR input regardless of other
inputs. The counting condition is changed by the positive going transition of CLOCK
input if CE="H" or by the negative going transition of CE i f CLOCK="L".
All inputs are equipped with protection ·circuits against static discharge or transient
excess voltage.
FEATURES:
• High Speed ••••••••••••••• fMAX=53MHz(Typ.) at VCC=5V
• Low Power Dissipation ••••••. ICC=4~A(Max.) at Ta=25 0 C r---------------------------~
• High Noise Immunity ••••••••• VNIH=VNIL=28% VCC(Min.)
• Output Drive Capability •••.•.•.•.•••• 10 LSTTL Loads
• Symmetrical Output Impedance .•••• IIOHI=IOL=4mA(Min.)
• Balanced Propagation Delays •••••.•••••••••
tpLH~tpHL
• Wide Operating Voltage Range ••••••• VCC(Opr.)=2V '" 6V
1
l6Y
DIP16(3D16A-P)
• Pin and Function Compatible with 45l8B/4520B
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
SYMBOL
VCC
VIN
DC Input Voltage
- - - - - - " ---DC Output Voltage
VOUT
-Input Diode Current
11K
Output Diode Current
10K
_.-1-----
VALUE
-0.5",7
-0.5 '\. VCc+O. 5
-0.5'\.VCc+O· 5
±20
±20
±25
DC Output Current
lOUT
---- t - - DC Vcc/Ground Current
:t50
ICC
.-- f---=----- Power Dissipation
PD
500(DIP)*
l80(MFP)
.. _--------Tstg
-65 '\. 150
Storage Temperature
f--=----.- _.
TL
300
Lead Temperature lOsec
-_
*
UNIT
V
V
V
mA
rnA
rnA
rnA
mW
°c
°c
500mW in the range of Ta=-40° '" 65°C and from Ta=65°C
up to 85°C derating factor of -lOmW/oC shall be applied
unti 1 300mW.
HC-774
1
MFP16(FI6GC-P)
PIN ASSIGNMENT
lOLOCK 1
16 VCC
lCLOCK 2
ENABLE
l(iO
15 2CLEAR
14 2(i3
13 2(i2
l(i2
12 2(il
11 2(iO
lOLEAR 7
{O 2CLOCK
ENABLE
2CLOCK
9
(TOP VIEW)
TC74HC4518P
---------------------------------TC74HC4520P/F
TRUTH TABLE
CLOCK
INPUTS
CLOCK ENABLE
I
L
"LX
H
L
INCLEMENT COUNTER
~
X
L
INCLEMENT COONTER
L
NO CHANGE
S
L
NO CHANGE
L
NO CHANGE
L
S
H
X
FUNCTION
CLEAR
L
X
L
NO CHANGE
H
QO THRU
X
DON'T CARE
Q3~L
TIMING CHART
TC74HC4518
a 1
CLOCK
-
2
3
4 5
7 8
6
o
9
1
1
1
2
rt1 rL1 rtL 1 ru1 rtL L 1
4 5
:3
7
6
8
8 8
II
-
CLEAR
CLOCK
ENABLE
QO
rS lJ S LrlJ lJU- J Lr
II
-
-
Q1
I--
- r- I--
-
I--
r--
I--
-
I--
I-- '--
I
-
0
8
I--
I--
'--
I-- I - -
-
I-I--
-
I--
Q2
I-- I--
Q3
-
TC74HC4520
012345678
CLOCK
9 1 10 11 11 11
_rtllrLilrtill nJlIlrLn
CLEAR
Ql
:<
2
2
2
0
II
r----
r S JU- S sVUlnr
II
-
-
r--,
I--
-
r- '-r- r-I-- I--
Q2
1
0
I
CLOCK
ENABLE
QO
12 13 14 15
r-
r-
I
I--
-
I--
I
!
Q3
I
-
rI--
r-I
I
-
II
HC-775
- -
,
-
f
I
III
: i
I
I
I
I
I
r--
TC74HC4518P
TC74HC4520P/F
LOGIC DIAGRAM
1/2 TC74HC4518
CLOCK
ENABLE
CLOCK
CLEAR
7(15)
R
D
3{11)
Q.O
Q.
OK
(4(12)
R
Q.
>----
Q.l
5(13)
R
Q.
~-..... >-~~Q,2
6(14)
>----
HC-776
Q.3
I:
_________________________________ TC74HC4518P
TC74HC4520P/F
LOGIC DIAGRAr'l (Continued)
1/2 TC74HC4520
2(10)
CLOCK
ENABLE
CLOCK
CLEAR
7 (15)
R
D
Q.O
+-t-0---0
eo
TIMING CHART
trr
rt=
H
f1Jl
A
VIL
II
8
T2
VIH
VIH
VIL
t
~
vee
-
VrefH
VrefL
Vss
VIH
- . VIL
I
n=VOH
0
VOL
0
Lt WOUT
I
I
~
HC-783
U=VOH
I
IWOUT +t rr
I
-
VOL
TC74HC4538API AF I AFN
FUNCTIONAL DESCRIPTION
!1lStand-by State
The external capacitoris fully charge to Vcc in the stand-by state. That means. befor triggering.
Qpand QN transistors which are connected to the T2 node are in the off state. Two comparators
that relate to the timing of the output pulse, and two reference voltage supplies stop their operation.
The total supply current is only leakage current.
(2lTrigger operation
Trigger operation is effective in either of the following two cases. One is the condition where the
A input is low, and the B input has a falling signal. The other. where the B input is high, and the
A input has a rising signal.
After trigger becomes effective, comparators Cl and C2 start operating, and QN is turned on.
The external capacitor discharges through QN. The voltage level of the T2 node drops. If the T2
voltage level falls to the internal reference voltage Vref L. the output of Cl becomes'low. The flip
-flop is then reset and QN turns off. At that moment Cl stops but C2 continues operating.
After QN turns off, the voltage at T2 start rising at a rate determined by the time constant of
external capacitor Cx and resistor Rx.
After the triggering, output Q becomes high, follo\\ing some delay time of the internal F/F and
gates. It stays high even if the voltage of T2 changes from falling to rising. When T2 reaches the
internal reference voltage Vref H, the output of C2 becomes low. the output Q goes low and C2
stops its operation. That means,. after triggering, when the voltage level of T2 reaches Vref H.
the IC returns to its MONO STABLE STATE.
In the case of large value of ex and Rx. and ignoring the discharge time of the capacitor and in
ternal delays of the IC, the width of the output pulse tw (OUT)is as follows:
tw (OUT)=O. JOCx Rx
(3)Retrigger operation
When another new trigger-is applied to input A or B while in the MONO STABLE STATE, it
is effective only if the IC is charging Cx. The voltage level of T2 then falls to Vref L level again.
Therefore the Q output stays high if the next trigger comes in before the time period set by Cx
and Rx.
If the 2nd trigger is very close to previous trigger. such as appI4.cation during the discharge cycle,
the 2nd trigger will not be effective.
The minimum time for effecti\'e 2nd trigger, trr(Min). depends on Vcc and Cx.
(4)Reset operation
In 'normal operation, CD input is held high. If CD is low, a trigger has no effect because the Q
output is held low and trigger control F/F is reset. Also Qp ,turns on and Cx is charged rapidly
to Vcc.
This means if CD input is set low. the IC goes into a wait state.
HC-784
- - - - - - - - - - - - - - TC74HC4538AP/AF/AFN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
.Power Dissipation
Storage Temperature
Lead Temperature 10sec
SYMBOL
Vee
VI;>;
VOLT
11K
10K
IOLT
lee
PI)
Tsig
TL
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DlP) *1180(SOIC)
-65 -150
300
UNIT
V
V
V
mA
mA
mA
rnA
mW
*500mW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-lOmW/'C shall be applied
until300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
(CD Only)
SYMBOL
Vee
VI;>;
VOLT
Topr
tr • tf
External Capactior
Cx
External Resistor
Rx
VALUE
2-6
0- Vee
0- Vee
-40 - 85
o- 1000(Vee =2.0V)
0- 500(Vee =4.5V )
o - 400(Vee =6.0V)
No Limitation *
~5K*(Vee<3.0V)
~IK.(V ~3.0V)
UNIT
V
V
V
"C
ns
F
Q
The maximum allowable values of Cx and Rx are a function of leakage of capacitor Cx.
the leakage of TC74HC4538A. and leakage due to board layout and surface resistance.
Susceptibility to externally induced noise signals may occur for Rx>lMQ.
He-78S
TC74HC4538AP/AF/AFN - - - - - - - - - - - - - -
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VII.
High-Level
Output Voltage
(Q,Q)
Voo
Low-Level
Output Voltage
(Q,Q)
Va.
Input Leakage Current
R/C Terminal
,Input Leakage Current
Quiescent Supply Curren
Active-State *
Supply Current
II:"
TEST CONDITION
Vcc
2.0
4.5
6.0
2.0
4.5
6.0
2.0
ICJi =-20#A 4.5
VI:'; =
6.0
VIHorVU•
1m --4 rnA 4.5
IOH =-5.2mA 6.0
2.0
lex.. =20 #A 4.5
VI:" =
6.0
VIHorVIL
lex.. -4 rnA 4.5
la. =5.2mA 6.0
VI:" =Vcc orGND
6.0
II:"
VI:" =Vee or GND
6.0
Icc
VI:" --'Vee or GND
Icc
VI:" =Vee or GND
Rx/Cx ext=O. 5Vcc
6.0
2.0
4.. 5
6 0
Ta--40 -85"(
Ta-25"C
UNIT
TYP. MAX. MIN. MAX.
1.5
V
3.15
4.2
0.5
0.5
V
1. 35
1. 35
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4. 13
4.18
4.31
5.68
5.80
5.63
0.0
0.1
0.1
0.0
0.1
0.1
V
0.0
0.1
0.1
0.26
0.33
0.17
0.18
0.26
0.33
±0.1
±1.0
MIN.
1.5
3.15
4.2
-
-
±0.1
-
40
0.2
o3
4.0
120
0.3
o6
-
-
±1.0
#A
-
40.0
160
0.4
o8
#A
rnA
rnA
-
*: per Circuit
TIMING REQUIREMENTS(Input t r =t,=6ns)
PARAMETER
SYMBOL TEST CONDITION
Minimum Pulse Width
(A,B)
tW(L)
tW(H)
Minimum Clear Width
(CD)
tW(L)
Minimum Clear Removal
Time
trem
Rx=lKQ
Cx=lOOpF
Minimum Retrigger Time
trr
Rx=lKQ
ICx=O.OlpF
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6 0
2.0
4.5
6.0
HC-786
'!'a-25"C
TYP.
LIMIT
75
15
13
75
15
13
15
5
5
380
92
72
6.0
1.4
12
Ta--40 -85"C
UNIT
LIMIT
95
19
16
95
19
16
ns
15
5
5
-
#5
- - - - - - - - - - - - - - TC74HC4538API AFI AFN
AC ELECTRICAL CHARACTERISTICS(C L =15pF.Vcc =5V.Ta=25"C)
PARAMETER
SYMBOL
Output Transition Time
tTLH
t 1111.
t "'.11
t nlll.
tpl.H
t nlll.
Propagation Delay Time
(A,B-Q.Q)
Propagation Del!), Time
(CD-Q.Q)
TEST CONDITION
MIN.
TYP.
MAX.
-
6
12
-
25
44
-
21
34
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =50pF,lnput t r =tf=6ns)
Ta- 40 -85"C
Ta-25"C
UNIT
PARAMETER
SYMBOL TEST CONDITION
Voc MIN. TYP. MAX. MIN. MAX.
30
75
95
2.0
tn.H
Output Transition Time
8
15
19
4.5
tTI-lI.
6.0
7
13
16
120
250
315
2.0
Propagation Delay Time
tpLll
ns
30
50
63
4.5
tpHL
(A.B-Q.Q)
6.0
25
54
43
245
100
195
2.0
Propagation Delay Time
tpLH
4.5
25
39
49
(CD-Q.Q)
tpHL
6.0
42
20
33
Cx=o
540
1200
1500
2.0
Rx=SKQ(Voc =2V) 4.5
ns
320
250
180
Rx=lKQ(Voc=4.5V,6V) 6.0
260
150
200
70
70
96
83
96
2.0
Cx=O.olp.F
Output Pulse Width
69
77
85
69
85
tWOLT
4.5
fJ.s
Rx=10KQ
6.0
69
69
85
77
85
0.67
O. 75
0.83
0.67
0.83
2.0
Cx=O.lp. F
rns
0.77
0.67
O. 77
4.5
0.67
O. 73
Rx=10KQ
6.0
0.67
O. 73
O. 77
0.67
0.77
Output Pulse Width Error.
±1
%
Between Circuits
t:..tWQL;
(In same Package)
Input Capacitance
5
10
10
C"
pF
Power Dissipation Capacitance CPD(J)
70
Note (I) C PI) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
IcctiW=C PD' Vee' f I" +Iee' • Duty/lOO+l ee 12(per Circuit)
(Ici:Active Supply Current)
(Duty:16)
HC-787
TC74HC4538APt AFt AFN - - - - - - - - - - - - - -
OUTPUT PULSE WIDTH CONSTANT,K-SUPPLV VOLTAGE(TVP.)
(EXTERNAL RESISTOR(Rx)=10kQ;twOUT=K.Cx.Rx)
~
I
I-
z
0.9
<
I-
en
Z
0
(,)
:J:
I-
0.8
a
~
w
en
...J
::::>
0.7
0..
"'-
...............
Cx=O.OtpF-
"'-..
...........
-
Cx=O.tpF -
-
Cx=t.OpF
I-
::::>
0..
I-
2
3
SUPPLY VOLTAGE
::::>
0
4
Vcc(V)
II
5
twOUT-Cx CHARACTERISTICS(TVP.)
6
trr-Vcc CHARACTERISTICS(TVP.)
Vcc-4.5V
CL 50pF
en
'"
~
Ta=25'C
•
/
to
10
Rx=tMO /
;;;
,.
::::>
0
!
:t:
l-
e
to•
/
/
Rx=tOOItO /
a::
(I)
..J
to
/
Rx=t OkO /
Rx=tkO
::::>
Q.
V
::::>
t
V
.....
a::
,/
a::
::<
i
--t=t~r-
I
~~ Lt~J_
:::>
~
z
/
-
........
"""- "-
I-
w
I
I-
Cx=O.OlpF-
"- I--
1
C>
C>
"
V
l-
0
.......
w
w
0..
"
w
::<
;::
z
~
::::>
'\.
~
~
0.1
L.
II
to-I
10'
EXTERNAL
a
10'
10'
CAPACITOR Cx(pF)
1
2
SUPPLY
He-l88
3
4
VOLTAGE
5
Vcc(V)
6
------TC74HC4543API AF
BCD-TO-7 SEGMENT LATCH/DECODER/LCD DRIVER
r----------------------------,
The TC74HC4543A is a high speed CMOS BCD-TO-7
SEGMENT DECODER with LCD DRIVER fabricated
with sillicon gate C 2M OS technology.
It achieves the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low
power dissipation.
This device consists of BCD-TO-7 segment decoder
with a BCD input latch and a 7-segment driver for the
liquid crystal display (LCD).
When an error code (over 10) is applied to BCD inputs
or, when blanking input (BI) is held high, all segment
outputs will go low (turn off).
When driving LCD, a common square wave signal
should be applied not only to the PH input of this device
but also to the electrically common backplane of the
display.
For other types of readouts, such as light emitting
diodes (LED), some additional drivers, such as a
transistor array, is required.
All inputs are equipped with protection circuits
against static discharge or transient excess voltage.
1
P(DIP16-P-300A)
16~
1
F (SOP 16-P-300)
PIN ASSIGNMENT
LD 1
FEATURES:
• High Speed .............................. t w =6ns(Typ.)at Vee =5V
• Low Power Dissipation ............ Iee=4IlA(Max.)at Ta=25"C
• High Noise Immunity .............. · VNIH=V NIL =28" Vee (Min.)
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance "'1 IOHI=IOL=4mA(Min.)
• Balanced Propagation Delays ...... tpLH" tpHL
• Wide Operating Voltage Range'" Vee (opr)=2V -6V
• Pin and Function Compatible with 4543B
A
B
C
0
1
5)
(3 )
(2 )
(4 )
PH (6)
BI
(7)
C9
BCOI7SEG
(Tl 810
BO.l
bl0
BO.2
cl0
BO.4
dl0
BO.8
.10
Nl0
110
EN
g10
He-78g
14 9
13 e
12 d
o 4
A 5
PH 6
11 e
10 b
BI 7
GND 8
9
(TOP VIEW)
IEC LOGIC SYMBOL
LO
16 Vee
15 f
C 2
B 3
(B)
(10)
(11)
12)
8
b
c
d
(13)
(15)
f
(14)
g
8
TC74HC4543AP/AF - - - - - - - - - - - - - - - -
TRUTH TABLE
X
BI
H
PH
L
0
X
X
X
X
L
H
L
L
L
L
L
L
H
OUTPUTS
e d e
b
L· L
L
L
H H H H
H
L
L
L
L
L
H
L
H
H
L
L
L
L
H
L
H
H
L
L
L
L
H
H
H
H
L
L
L
H
L
L
H
L
L
L
H
H
L
L
L
H
H
L
L
L
H
H
L
L
H
L
L
H
L
L
H
L
H
L
L
H
X
H
L
L
H
H
X
L
L
L
X
X
X
t
t
H
INPUTS
LD
C
B
A
a
H
g
L
L
f
L
DISPLAY
BLANK
0
H
L
L
L
L
H
L
H
H
L
H
2
H
H
H
L
L
H
L
H
H
L
L
H
H
3
4
L· H
H
L
H
H
L
H
H
5
H
L
H
L
H
H
H
H
H
6
H
H
H
H
H
L
L
L
L
7
L
H
H
H
H
H
H
H
8
L
H
H
H
H
H
L
H
H
9
H
X
L
L
L
L
L
L
L
BLANK
X
X
L
L
L
L
L
L
L
BLANK
1
###
###
INVERSE OF ABOVE OUTPUT LEVEL DISPLAY AS ABOVE
t
X:Don't care
t:SAME AS ABOVE COMBINATIONS
###:DEPENDS UPON THE BCD CODE PREVIOUSLY APPLIED WHEN LD=-W
DISPLA Y MODE
tI - I
el - Ie
a
g
0
I-I
I_I
2
3
I :1 J
11- _I
4
6
uI L_I
6
d7
b
7 SEGMENT DISPLAY
8
9
L -I U LI
I_I I I_I _I
HC-790
10
11
12
13
14
16
TC74HC4543API AF
SYSTEM
DIAGRAM
Q
...J
Q
...J
HC-791
I~
TC74HC4543AP/AF - - - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL
Vee
VIN
Vcx,'T
11K
10K
1cx,'T
lee
Po
Tstg
TL
VALUE
-0.S-7
-O.S -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
SOO(DlP)·/180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
"C
"C
*500mW in tli~ r~ge ~fTa=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-10m WI"C shall be applied
until300mW.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
VALUE
2-6
o -Vee
o -Vee
-40 -- 85
0- 1000(Vee =2.0V)
0- SOO(Vee =4.SV)
0- 400(Vee=6.0V)
SYMBOL
Vee
VIN
Your
Topr
tr • tr
UNIT
V
V
V
"C
ns
DC ELECTRICAL CHA.RACTERISTICS
PARAMETER
SYMBOL
High-Level
Input Voltage
VIH
Low-Level
Input Voltage
VIL
High-Level
Output Voltage
Voo
Low-Level
Output Voltage
Va.
Input Leakage Current
Quiescent Supply Current
11:-;
Icc
TEST CONDITION
VII'~=
100 =-20p.A
VIHorVIL 100 --4 rnA
100 =-S.2mA
VI:-;=
VIHorVIL
Ia. =20 p.A
Ia. -4 mA
Ia. =5.2mA
VIN -Vee or GND
VI!'< =Vcc orGND
Vee
2.0
4. S
6.0
2.0
4. S
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
HC-792
Ta-25"C
Ta--40 -8S"C
UNIT
TYP. MAX. MIN. MAX.
I.S
V
3. IS
4.2
0.5
0.5
V
1. 3S
1. 3S
...,.
1.8
1.8
2.0
1.9
1.9
4.4
4.5
4.4
V
5.9
6.0
5.9
4.13
4.18
4.31
5.68
5.80
5.63
0.1
0.1
0.0
0.1
0.1
0.0
V
O. I
0.1
0.0
0.26
0.33
0.17
0.33
0.26
0.18
±0.1
±1.0 p.A
4.0
40.0
MIN.
I.S
3. IS
4.2
-
--------------------------------TC74HC4543AP/AF
TIMING REQUIREMENTS(lnput tr=t, =6n8)
,--
PARAMETER
-,'
,SYMBOL
Minimum Pulse Width
(LD)
TEST CONDITION
tW(II)
Minimum Set-up Time
ts
Minimum Hold Time
th
Ta=25"C
Vee
TYP.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
-
-
Ta=-40 - 85"C
LIMIT
75
15
13
75
15
13
0
0
0
LIMIT
t:XIT
95
19
16
95
19
16
0
0
0
ns
MAX.
UNIT
AC ELECTRICAL CHARACTERISTlCS{C L =15pF, Vcc=5V, Ta=25"C)
PARAMETER
Output Transition Time
Propagation Delay Time
(BCD-OUT)
Propagation Delay Time
(BI-OUT)
Propagation Delay Time
-(PH-OUT)
Propagation Delay Time
(LD-OUT)
SYMBOL
TEST CONDITION
MIN.
tTLH
tTI-IL
tpUi
tpHL
tpw
tpHL
tpLH
tpHL
tpLl-J
tpHL
TYP.
-
4
8
-
32
53
-
18
30
-
13
22
-
26
46
ns
AC ELECTRICAL CHARACTERISTICS{CL =50pF,lnput t r =tf=6n8)
Ta-25"C
Ta- 40 -85"C
UNIT
TYP. MAX. MIN. MAX.
30
75
95
trw
Output Transition Time
8
15
19
tTliL
7
13
16
160
300
375
Propagation Delay Time
tpLH
40
60
75
(BCD-OUT)
tpliL
:30
51
64
80
175
220
Propagation Delay Time
tpLH
ns
23
35
44
(BI-OUT)
tpliL
17
30
37
58
130
165
Propagation Delay Time
tpLH
17
26
33
(PH-OUT)
tpHL
22
14
28
130
265
335
Propagation Delay Time
tpl.H
35
53
66
(LD-OUT)
tpHL
16
45
56
Input Capacitance
CI:\
5
10
10
pF
Power Dissipation Capacitance
CPf)
115
Note (1) C A) is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
Ia;wo=Cfl) • Va:.. f[\ +Ia:.
PARAMETER
SYMBOL TEST CONDITION
Va;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
HC-793
MIN.
TC74HCT7007 A P / A F - - - - HEX BUFFER
The TC74HCT7007A is a high speed CMOS BUFFER
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
This device may be used as a level converter for
interfacing .TTL or NMOS to High Speed CMOS. The
inputs are compatible with TTL, NMOS and CMOS output
voltage levels.
The internal circuit is composed of 4 stages including a
buffer output, which provides high noise immunity and
stable output.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
FEATURES:
• High Speed ..•..•.......••.............•. tpd =l1ns(Typ.)at Vcc=5V
• Low Power Dissipation .•...•...... Icc =I#A(Max.)at Ta=25"C
• Compatible with TTL outputs·· .. ·· V1H =2V(Min.)
V 1L =0.8V(Max.)
• Wide Interfacing ability ...... ·.. LSTTL,NMOS,CMOS
• Output Drive Capability ............ 10 LSTTL Loads
• Symmetrical Output Impedance ... I IOH I =IOL =4mA(Min.)
• Balanced Propagation Delays ...... tpl.J-I'" tpHL
• Pin and Function Compatible with 74LS07
1
P(DIP14-P-300)
14~
1
F(SOP14-P-300)
PIN ASSIGNMENT
1A
14 Vee
lY
2
13
2A
3
12
6Y
2Y
4
11
5A
3A
5
10
5Y
3y 6
9
4A
7
8
4Y
GND
(TOP VIEW)
lEe
LOGIC SYMBOL
TRUTH TABLE
lA
IV
2A
'l:f
A
y
3A
4A
SA
6A
3V
4Y
SY
6V
L
H
L
H
HC-794
6A
TC74HCT7007 APIAF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsec
SYMBOL.
Vee
VI:"
VOLT
11K
10K
l(lLT
lee
~)
I Tstg
TL
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±25
±50
500(DIP) */180(MFP)
-65 -150
300
UNIT
V
V
V
rnA
rnA
rnA
rnA
mW
*500mW. in the range of Ta=
-40"C- 65"C. From Ta=65"C
to 85"C a derating factor of
-IOmW/"C shall be applied
unti1300mW.
"C
"C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SnmOL
Supply Voltage
Vee
Input Voltage
VI:"
V(JLT
Output Voltage
Topr
Operating Temperature
Input Rise and Fall Time
tr. tr
UNIT
V
V
V
"C
ns
VALUE
4.5-5.5
O-Vee
O...... Vee
-40-85
0-500
DC ELECTRICAL CHARACTERISTICS
r--
PARAMETER
High-Level
Input Voltage
Low-Level
Input Voltage
High-Level
Output Voltage
Low-Level
Output Voltage
Input Leakage Current
Quiescent Supply
Current
sn1BOLI
I
I
VIIi
VII.
TEST CONDITION
II
Vee
4.5
l
I
5.5
4.5
i
5.5
4.5
4.5
4.5
4.5
5.5
5.5
!
IOI=-20p.A
i{ll= -4 p.A
Ia. =20 p.A
=
VI:"
V(JL
VlllorVII . I(JL = 4
p.A
II:"
VII-t=VII. orGND
Icc
VIII = VII. orGND
PER
INPUT: VI:" =0. 5Vor2. 4V 5.5
t.1cc OTHER
INPUT:Vee orGND
VOi
I
Ta=-40-85"C
Ta=25"C
UNIT
MIN. TYP. MAX. MIN. MAX.
VI:" =
VlllorVIL
HC-795
2.0
-
-
2.0
-
V
-
-
0.8
-
0.8
V
4.4
4.18
4.5
4.31
0.0
0.17
-
4.4
4.13
-
0.1
0.26
±O.l
1.0
-
-
-
I
-
2.0
-
0.1
0.33
±1.0
10.0
2.9
V
V
p.A
rnA
TC74HCT7007AP/AF - - - - - - - - - - - - - - -
AC ELECTRICAL CHARACTERISTICS(C L =16pF. Vcc=6V. Ta=26"C)
PARAMETER
SYMBOL
Output Transition Time
tll.11
tTlII.
t,lU-1
t 1/-11.
Propagation Delay Time
TEST CONDITION
I
I
MIN.
TYP.
MAX.
-
6
12
-
11
17
UNIT
ns
AC ELECTRICAL CHARACTERISTICS(CL =60pF.lnput t r =tf=6ns)
PARAMETER
SYMBOL TEST CONDITION
Ta~25"C
Vee
Output Transition Time
tll.H
tTl-II.
4.5
5.5
Propagation Delay Time
tpl.!1
tliiL
4.5
5.5
Input Capacitance
MIN.
-
I
! -
TYP.
MAX.
8
7
14
12
15
14
,
23
21
Ta--40 -85"C
UNIT
MIN. MAX.
-
-
19
18
ns
28
26
C I:\
5
10
10
pF
Cpo(l)
22
Notem C m is defined as the value of the internal equivalent capacitance which is calculated from the
operating current consumption without load.
Average operating current can be obtained by the equation:
lee Wll=C I'D • Va::' f 1:\ +1 a:: 16C per Gate)
Power Dissipation Capacitance
HC-796
TC74HC7240AP/AF
--------TC74HC7241 API AF
TC7 4HC7244AP I AF
OCTAL BUS BUFFER (WITH SCHMITT TRIGGER INPUTS)
TC74HC7240AP/AF
TC74HC7241AP/AF
TC74HC7244AP/AF
INVERTED. 3-STATE OUTPUTS
NON-INVERTED. 3-STATE OUTPUTS
NON-INVERTED 3-STATE 0r-:U:,.T.:....:...P."U'-'T:...:S=--_ _ _ _ _ _ _ _ _ _-,
The TC74HC7240A17241A17244A are high speed CMOS
OCT AL BUS BUFFERs with silicon gate C 2 MOS
technology.
They achieve the high speed operation similar to
equivalent LSTTL while.maintaining the CMOS low power
dissipation.
The TC74HC7240N7241N7244A have same pin configuration
and function as the TC74HC240Al241A/244A. And they
have hystereis characteristics on each input, so
TC74HC7240N7241N7244A can be used as a line receiver, etc.
The TC74HC7240A is an inverting 3-state buffer having
two active low output enables. The TC74HC7241A and
HC7244A are non-inverting 3-state buffers that differ only in
that the HC7241A has one active-high and one active-low
output enable; and the HC7244A has two active low output
enables.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
20
1
P(DIP20-P-300A)
~~
1
F(SOP20-P-300)
TRUTH TABLE
INPUTS
FEATURES:
• High Speed ................................. tpd=15ns(typ.) at Vcc=5V
• Low Power Dissipation ······ .. ·······1cc=4t.tA(Max.) at Ta=25"C
• High Noise Immunity ............ ·.. VH=1.1V(typ.)at Vcc=5V
• Output Drive Capability .... ·...... · 15 LSTTL Loads
• Symmetrical Output Impedance .. ·1 IOH 1=IOL =6mA(Min.)
• Balanced Propagation Delays ...... tpLH"'tpHL
• Wide Ope~ating Voltage Range· .. Vcc(opr)=2V-6V
• Pin and Function Compatible with 74LS240/2411244
OUTPUTS
G
G"
An
Yn
Yn""
L
H
L
L
H
L
H
H
H
H
X
L
L
X
Z
Z
: for TC74HC7241A only
: for TC74HC7240A only
: Don't Care
Z
: High Impedance
Do
~
PIN ASSIGNMENT(TOP VIEW)
TC74HC7244A
TC74HC7241A
TC74HC7240A
lG
20 Vee
20 Vee
lG 1
20 Vee
lAl 2
192G
lAl 2
192G
lAl 2
2'(4 3
181'(1
2Y4 3
18 lYl
2Y4 3
18 lYl
lA2 4
172A4
lA2 4
172M
1A2 4
172M
2'(3 5
161'(2
2Y3 5
16 1Y2
2Y3 5
161Y2
lA3 6
152A3
1A3 6
152A3
lA3 6
152A3
2'(2 7
141'(3
2Y2 7
141Y3
2Y2 7
141Y3
lA4 8
13 2A2
1A4 8
132A2
1A4 8
132A2
2'(1 9
121'(4
2Y1 9
12 1Y4
2Y1 9
12 1Y4
GND 10
11 2A1
GND 10
11 2A1
GND 10
11 2A1
lG
HC-797
192G
TC74HC7240API AF
TC74HC7241 A P / A F - - - - - - - - - - - - - - -
TC74HC7244API AF
IEC LOGIC SYMBOL
TC74HC7240A
2Al (1~
2,., O~
2A2 ruO.!~_ _
2A3 tii°51~
'[
2M
_01)_ _ __
__
_...1
.r
TC74HC7244A
TC74HC7241A
2A2 01)
!AS O~
2M
(9) 2Yl
t-:;:";"--''"L~7
(5
2Y2
(3) 2Y3
on
2Y4
He-7gB
TC74HC7240API AF
- - - - - - - - - - - - - - - TC74HC7241AP/AF
TC74HC7244API AF
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Range
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC Vee/Ground Current
Power Dissipation
Storage Temperature
Lead Temperature lOsee
SYMBOL
Vee
V\:\
VClLT
I\K
10K
IOLT
lee
~)
Tstg
TL
UNIT
V
V
V
mA
mA
mA
mA
mW
"C
"C
VALUE
-0.5 -7
-0.5 -Vee +0.5
-0.5 -Vee+0.5
±20
±20
±35
±75
500(DIP)·/180(SOIC)
-65 -150
300
*5OOmW in the range of Ta=
-40'C- 65'C. From Ta=65'C
to 85'C a derating factor of
-IOmW/'C shall be applied
until 300m W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
VALUE
2-6
0- Vee
0- Vee
-40 - 85
SYMBOL
Vee
V\:\
VOLT
Topr
UNIT
V
V
V
"C
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Positive
Threshold
Voltage
Negative
Threshold
Voltage
SYMBOL
Vp
V:\
Hysteresis
Voltage
VH
High-Level
Output Voltage
Va-I
Low-Level
Output Voltage
3 State Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
TEST CONDITION
VOl..
ICE
1\:\
kx:
V\:\=
V\HorV\L
V\:\ =
V\HorV\L
Ia-I =-20tl A
Ia-I - 6 mA
Ia-I =-:7. SmA
101.. =20 tl A
la. -6 mA
la. =7.8mA
V\:\ -V\H or V\L
VOLT =Vo:; or GND
V\:\ -Vee or GND
V\:\ -Vee or GND
Yo:;
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
).0
MIN.
1.0
2.3
3.0
0.3
1.13
1.5
0.3
0.6
0.8
1.9
4.4
5.9
4.18
5.68
6.0
6.0
-
HC-799
-
-
Ta-25"C
Ta- 40 -85"C UNIT
TYP. MAX. MIN. MAX.
1. 25
1.5
1.0
1.5
V
3.15
2. 7
2.3
3.15
3.5
4.2
3.0
4.2
0.65
0.9
0.3
0.9
V
1.6
2.0
1.13
2.0
2 6
2.6
1.5
2.3
0.6
1.0
0.3
1.0
V
1.4
0.6
1.4
1.1
0.8
1.2
1.7
1.7
2.0
1.9
4.5
4.4
V
6.0
5.9
4.31
4.13
5.63
5.80
0.0
0.1
0.1
0.0
0.1
0.1
V
0.0
0.1
0.1
0.26
0.17
0.33
0.18
0.33
0.26
-
±0.5
-
±5.0
±0.1
4.0
-
±1.0
40.0
tl
A
TC74HC7240API AF
TC74HC7241AP/AF--------------TC74HC7244AP I AF
AC ELECTRICAL CHARACTERISTICS(lnput t r =tf=6ns)
TEST
CONDITION CL
PARAMETER
SYMBOL
Output Transition Time
t11.1-1
t11IL
50
tpLI-I
50
Propagation Delay Time
tpHL
150
tpZL
50
Output Enable time
RL = 1 kQ
tpZl_1
Output Disable time
tpLZ
tpt-rZ
Input Capacitance
Output Capacitance
CIN
COl;T
Power Dissipation Capacitance
Cro(l)
150
RL = 1 kQ
50
Vee
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
TC74HC7240A
TC74HC7241A17244A
MIN.
-
-
-
-
-
-
-
Ta-25"C
Ta--40 -85"C UNIT
TYP. MAX. MIN. MAX.
60
75
25
7
12
15
13
6
10
50
125
155
15
25
31
21
26
13
205
67
165
20
33
41
28
17
35
ns
68
150
190
21
30
38
16
26
32
84
165
230
26
37
46
20
31
39
48
150
190
21
30
38
19
26
32
5
10
10
10
pF
33
34
Note (1) CPO is defined as the value of the internal equivalent capacitance which is calculated from
operating current consumption without load.
Average operating current can be obtained by the equation:
I eetpO=C PD • Vee· fN +Iee 18(per bit)
He-800
the
_______________ TC74HC7292P
TC74HC7294P
TC74HC7292P
TC74HC7294P
PROGRAMMABLE DIVIDER/TIMER
PROGRAMMABLE DIVIDER/TIMER
The TC74HC7292 and TC74HC7294 are high speed CMOS PROGRAMMABLE DIVIDER/TIMER
fabricated with silicon C2MOS technology.
They achieve the high speed operation similar to equivalent LSTTL while maintaining
the CMOS low power dissipation.
These devices are programmable frequency divider. Both types have two clock inputs,
either one may be used for clock gating. (See the function table (1».
The TC74HC7292 can divide from 22 to 231 , and the TC74HC7294 can divide from 22 to 215.
Both types feature an active-low clear input to initialize the state of all flip-flops.
To facilitate incoming inspection, test points are provided. (TPl, TP2 and TP3 on the
74HC7292 and TP on the 74HC7294).
All inputs are equipped with protection circuits against static discharge or transient
excess voltage.
FEATURES:
• High Speed
50MHz [7292]
........................ fMAX=60MHz [7294] (Typ.) at VCC=5V
• Low Power Dissipation ••••••••••••••
ICC=4~A(Max.)
at Ta=25°C
• High Noise Immunity •••••••••••••••• VNIH=VNIL=28% VCC(Min.)
• Output Drive Capability •••••••••••• 10 LSTTL Loads
• Summetrical Output Impedance ••••••• IIOHI=IOL=4wA(Min.)
• Balanced Propagation Delays ••••••••
tpLH~tpHL
Wide Operating Voltage Range ........ VCC(Opr.)=2V'" 6V
• Pin and Function Compatible with 74LS292/294
PIN ASSIGNMENT
TC74HC7292
TC74HC7294
B
1
16
VOO
B
1
16
VOO
E
2
15
0
A
2
15
0
TP1
3
1..
D
TP
3
1 ..
D
OK1
..
13
TP3
OKlo
..
13
NO
OK2
5
12
NO
OK2
5
12
NO
TP2
6
11
CLR
6
11
..,
NO
OLR
10
A
Q.
..,
10
NO
NO
GND
8
9
NO
GND
8
(TOP VIEW)
(TOP VIEW)
NO: NO OONNECTION
HC-801
16
DIP16(3Dl.6A-P)
TC74HC7292P _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TC74HC7294P
TRUTH TABLE
CLEAR
CLOCK1
CLOCK2
Q OUTPUT MODE
L
X
X
Oleared to L
S
H
H
L
UP Oount
S
L
H
H
X
H
X
H
NO Ohange
TC74HC7292
FR~UENOY
PROGRAMMING
INPUTS
E
D 0
B
A
BINARY
DIVISION
DECIMAL
BINARY
TP2
TP2
TP1
Q.
DECIMAL
BINARY
DECIMAL
BINARY
DECIMAL
Inhibit
L
L
L
L
L
Inhibit
Inhibit
Inhibit
Inhibit
Inhi bit
Inhibit
Inhibit
L
L
L
L
H
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
L
L
L
H
L
22
4
29
512
Inhibit
217
L
L
L
H
H
23
8
29
512
Inhibit
131,072
224
16,777,216
217
131,072
224
16,777,216
131,072
224
16,777,216
L
L
H
L
L
24
16
29
512
217
L
L
H
L
H
25
32
29
512
217
131,072
224
16,777,216
L
L
H
H
L
26
64
29
512
217
131,072
224
16,777,216
L
L
H
H
H
27
128
29
512
217
131,072
224
16,777,216
L
H
L
L
L
28
256
29
512
217
131,072
22
L
H
L
L
H
29
512
29
512
217
131,072
2~
4
L
H
L
H
L
2 10
1,024
29
512
217
131,072
24
16
L
H
L
H
H
211
2,048
29
512
217
131,072
24
16
L
H
iI
L
L
212
4,096
29
512
217
131,072
26
64
L
H
H
L
H
'2 13
8,192
512
217
131,072
26
64
L
H
H
H L
214
16,384
29
'29
28
256
L
H
H
H H
2 15
32,768
29
512 Dieatil.ed Low
65,536
29
512
23
512 Disabled LOW
28
4
256
L
L
L
L
2 16
H L
L
L
H
217
131,072
29
512
23
8
2 10
1,024
H
L
L
H
L
2 18
262,144
29
512
25
32
212
4,096
H
L
L
H H
2 19
524,288
29
512
25
32
212
4,096
H
L
H L
L
220
1,048,576
29
512
27
128
214
16,384
H
L
H L
H
221
2,097,152
29
512
27
128
214
16,384
H
L
H H
L
222
4,194,304 Dieabled Low
29
512
2 16
65,536
H
L
H
H H
223
8,388,608 Dieablad Low
29
512
2 16
65,536
H 'H
L
L
L
224
16,777,216
23
2,048
2 18
262,144
H
H
L
L
H
23
8
211
2,048
H
L
H
L
2 25
226
33,554,432
H
67,108,864
25
32
2 13
8,192
2 18
220
1,048,576
H H
L
H
H
227
134,217,728
25
32
2 13
8,192
2 20
1,048,576
H
H
H
L
L
228
268,435,456
27
128
2 15
32,768
222
4,194,304
H
H H
L
H
229
536,870,912
27
128
2 15
32,768
222
4,194,304
H
H
H
H
L
2 30 1,073,741,824
29
512
217
131,072
224
16,777,216
H
H
H H
H
2 31 2,147,483,648
29
512
217
131,072
224
16,777,216
H
8
HC-802
211
8
2 10
1,024
262,144
_________________________________ TC74HC7292P
TC74HC7294P
TRUTH TABLE
TC74HC7294
FREQUENCY DIVISION
PROGRAMMING
INPUTS
D
L
L
L
L
L
L
L
L
e
L
L
L
L
B
L
L
TP
Q
A
L
BINARY
DEeIMAL
Inhibit
Inhibit
H
Inhibit
Inhibit
H
L
22
4
H
H
8
H
L
L
23
24
H
H
H
H
H
H
L
H
L
H
L
BINARY
Inhibit
Inhibit
DECIMAL
Inhibit
Inhibit
29
29
512
512
16
29
512
32
29
29
512
L
25
26
H
27
128
L
L
L
H
28
29
512
22.
23
1,024
24
16
2,048
25
32
26
27
128
28
29
512
H
L
H
L
H
L
H
H
2 10
211
64
256
H
H
L
L
212
4,096
H
H
L
H
8,192
H
H
H
L
2 13
214
16,384
H
H
H
H
2 15
32,768
4
8
64
256
INPUT and OUTPUT
EQUIVALENT CIRCUIT
ABSOLUTE MAXIMUM RATINGS
PARAHETER
Supply Vo ltage Range
512
Disabled. Low
SYMBOL
VALUE
-0.5", 7
UNIT
V
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
VCC
VIN
-0.5'" VCc+O.5
VOUT
11K
10K
-0 . 5 '" Vcc+O • 5
±20
±20
V
V
rnA
rnA
DC Output Current
DC Vcc/Ground Current
Power Dissipation
rOUT
ICC
PD
±25
rnA
:t50
500*
rnA
mW
Storage Temperature
Lead Temperature 10sec
Tstg
TL
-65 "'ISO
300
·C
·C
* 500mW in the range of Ta=-40·C", 65·C and from Ta=65·C
up to 85·C derating factor of -lOmW/·C shall be applied
until 300mW.
He-803
Vee vee
IOUTPUT
*
_.J
TC74HC7292P
TC74HC7.294P----------------LOGIC DIAGRAM
TC74HC7292
I~
.
"
HC-804
R
.
.
_________________________________ TC74HC7292P
TC74HC7294P
LOGIC DIAGRAM
TC74HC7294
HC-805
TC74HC7292P
TC74HC7294P--------------------------------RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input'Voltage
Output Voltage
Operating Temperature
SYMBOL
VCC
VIN
VOUT
Topr
Input Rise and Fall Time
tr,tf
LIMIT
2 'V 6
o 'V VCC
o 'V VCC
UNIT
-40 'V 85
O'VlOOO(VCC=2.0V)
O'V 500 (VCC=4. 5V)
o 'V 400 (VCC=6. OV)
°c
V
ns
DC ELECTRICAL CHARACTERISTICS
PARAMETER
High-Level
Input Voltage
SYMBOL
TEST CONDITION
VIH
t-------
Low-Level
Input Voltage
VIL
I OH =-20IJA
High-Level
Output Voltage
VOH
VIN=VIH
IOH=-4mA
I OH=-5.2mA
or VIL
-Low-Level
Output Voltage
,
VIN=VIH
VOL
or VIL
; 10L=2OIJ A
I
I
IOL=4mA
IOL=5.2mA
r--
VCC
NIN.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
1.5
3.15
4.2
6.0
2.0
4.5
6.0
1.9
4.4
5.9
4.18
2.0
4.5
6.0
4.31
5.68
6.0
Input Leakage
Current
lIN
VIN=VCC or GND
6.0
-
Quiescent
Supply Current
ICC
VIN=VCC or GND
6.0
-
-------_.
He-806
-
-
-
4.5
Ta=25°C
TYP.
MAX.
-
-
1.5
3.15
4.2
-
-
-
-
1.9
4.4
5.9
4.13
-
5.80
0.0
0.0
0.0
0.17
-
0.5
1.35
1.8
5.63
-
0.1
0.1
0.1
-
0.1
0.1
0.1
0.26
-
0.33
O.le
0.26
-
0.33
-
0.5
1.35
1.8
Ta=-4O'V85°C
UNIT
NIN. MAX.
-
-
-
±O.l
-
.t1.0
4.0
-
40.0
V
lJA
__________________________________ TC74HC7292P
TC74HC7294P
.
AC ELECTRICAL CHARACTERISTICS (t r =tf=6ns CL-50pF)
.-PARAMETER
SYMBOL
Output Transition Time
TEST CONDITION
tTLH
tTHL
(Q)
Output Transition Time
(TP)
tTLH
tTHL
Propagation Delay Time
(CLOCK - Q)
tpLH
B="H"
tpHL
A=C=D=E="L"
Propagation Delay Time
(CLOCK - Q)
tpLH
tpHL
B="H"
A=C=D="L"
Propagation Delay Time
(CLEAR - Q)
*
tpHL
*
**
Propagation Delay Time
(CLEAR -
Q)
Maximum Clock
**
*
Frequency
tpHL
fMAX
**
Maximum Clock Frequenc} fMAX
Minimum Pulse Width
(CLOCK)
Minimum Pulse Width
(CLEAR)
Minimum Pulse Width
(CLEAR)
tw(H)
tw(L)
tw(L)
*
**
tw(L)
Minimum Removal Time
(CLEAR)
t rem
Input Capacitance
CIN
Power Dissipation
Capacitance
CpD (l)
,
Ta=25°C
VCC
MIN.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
6
32
38
7
32
44
-
-
74HC7292
74HC7294
He-80l
TYP.
30
8
7
132
33
28
264
66
56
236
59
50
224
56
48
204
51
43
12
48
56
14
55
65
36
9
8
60
15
13
72
18
15
5
22
23
MAX.
75
15
13
255
51
43
500
100
85
455
91
77
425
85
72
390
78
66
-
100
20
17
150
30
26
175
35
30
5
5
5
10
-
Ta=-40'V85°C
UNiT
MIN. MAX.
95
19
16
320
64
54
625
125
106
ns
- 570
114
97
530
106
90
490
98
83
5
26
MHz
31
6
30
35
125
25
21
190
ns
38
32
- 220
44
37
5
5
5
10
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
TC74HC7292P
TC74HC7294P--------~-----------------------
Note(l) :
(2) :
CpD is defined as the value of internal equivalent capacitance of IC which
is calculated from the operating current consumption without load (refer to
Test Circuit). Average operating current can be obtained by the equation
hereunder.
ICC<0pr. )=CPD • VCC • fIN + ICC
* ; for TC74HC7292
**; for TC74HC7294
SWITCHING CHARACTERISTICS TEST WAVEFORM
ena
ena
- - -.... ---- v00
OLOCK
aND
loW
lopLH
90"
50"
10"
Q,TP
tTLH
ena
loTHL
ena
Jr___________________________ VCO
0I::'iA"R
1---------------- aND
1.
w
jr-----VOO
~_----aND
CLOaK
r--- VOH
Q,TP
50"
' - - - - -________________- - i I_ ___ VOL
lopHL
He-808
TC74HC7292P
----------------------------------'TC74HC7294P
Icc(Opr.) TEST CIRCUIT
TC74HC7294
TC74HC7292
B
vcc
CLR
fIN
TPl
CK2
A
E
*
CKl
Q.
CK2
A
TP2
C
D
vcc
OLR
Q.
CKl
fIN
B
TP _
C
D
TP3
GND
GND
Input transition time is the same as that in case of switching
characteristics test.
He-80g
NOTES
11.
OUTLINE DRAWINGS
TC74HC/HCT SERIES
DIP 14PIN OUTLINE DRAWING (DIP14-P-300)
Unit in mm
Note) Package width and length do not include mold protrusion.
DIP 16PIN OUTLINE DRAWING (DIP16-P-300A)
Unit in mm
0.95:1;0.1
~
;;;
0.735TYP
.110.5=~~_0.25MI
Note) Package width and length do not include mold protrusion.
HC-813
DIP 20PIN OUTLINE DRAWING (DIP20-P-300A)
Unit in mm
C::::::::I]~rre;
2•. 6±O.2
I~IAIJ:l AP'JUU~ ~ J ~ ~
UlUI UU~ -t- ~
I
O.87TVP
I
I
""'"
([EJ
V
~~
Note) Package width and length do not include mold protrusion.
DIP 24PIN OUTLINE DRAWING (DIP24-P-300)
Unit in mm
C::::::::::I] ~.~~
1.!!
I
12
29.B±O.Z
1.4= 0.1
O.5±O.I~
Note) Package width and length do not include mold protrusion.
HC-814
b
SOP l4PIN (200mil BODY) OUTLINE DRAWING (SOP14-P-300)
Unit in mm
Note) Package width and length do not include mold protrusion.
SOP l6PIN (200mil BODY) OUTLINE DRAWING (SOP16-P-300)
'"
r-----------,-~ ~
on
~
-I
chi
+,
_IE
;~t=
o
Note) Package width and length do not include mold protrusion.
HC-815
O.8±O.2
Unit in mm
SOP 20PIN (200mil BODY) OUTLINE DRAWING (SOP20-P-300)
~~
~ft=
;
Note) Package width and length do not include mold protrusion.
HC-816
. O.8±O.2
Unit in mm
SOP 14PIN (150mil BODY) OUTLINE DRAWING (SOL 14-P-150)
Unit in mm
Note) Package width and length do not include mold protrusion.
SOP 16PIN (150mil BODY) OUTLINE DRAWING (S0116-P-150)
Note) Package width and length do not include mold protrusion.
HC-817
Unit in mm
SOP 20PIN (300mil BODY) OUTLINE DRAWING (SOL20-P-300)
Unit in mm
0-8·
-::g~45.
aa
+I
'"o
aO.1
~
N
o
Note) Package width and length do not include mold protrusion.
HC·818
IIO.9±0.3
12.
CROSS REFERENCE GUIDE
TC74HC/HCT SERIES
CROSS REFERENCE GUIDE
TOSHIBA
TC74HCOOA
TC74HCTOOA
TC74HC02A
TC74HCT02A
TC74HC03A
TC74HC04A
TC74HCU04A
TC74HCT04A
TC74HC05A
TC74HC07A
TC74HC08A
TC74HCTOSA
TC74HC09A
TC74HClOA
I TC74HCllA
TC74HCl4A
TC74HCroA
TC74HC21A
TC74HC27A
TC74HC30A
TC74HC32A
TC74HCT32A
TC74HC42A
TC74HC51A
TC74HC73A
TC74HC74A
TC74HCT74A
TC74HC75A
TC74HC76A
TC74HC77A
TC74HC85A
TC74HC86A
TC74HCT86A
TC74HCI07A
TC74HCI09A
TC74HC1l2A
TC74HC1l3A
TC74HCI23
TC74HCI23A
TC74HCl25A
TC74HCI26A
TC74HCl31A
TC74HCl32A
TC74HCI33A
TC74HCl37A
I
i
MOTOROLA
TI
MC74HCOO
SN74HCOO
MC74HC02
SN74HC02
MC74HCOO
MC74HC04
MC74HCU04
MC74HCT04
MC74HC05
SN74HC03
SN74HC04
SN74HCU04
MC'l4HC08
SN74HC08
SIGNETICS
NATIONAL
SEMICONDUCTOR
MM74HCOO
MM74HCTOO
MM74HC02
CD74HCOO
CD74HCTOO
CD74HC02
CD74HCT02
CD74HCOO
CD74HC04
CD74HCU04
CD74HCT04
PC74HCOO
PCi4HCTOO
PC74HC02
PC74HCT02
PC74HCOO
PC74HC04
PC74HCU04
PC74HCT04
CD74HCOS
CD74HCT08
PC74HCOS
PC74HCTOS
MM74HCOS
CD74HCIO
CD74HCll
CD74HCl4
CD74HCroCD74HC21
CD74HC27
CD74HC30
CD74HC32
CD74HCT32
CD74HC42
PC74HCIO
PC74HCll
PC74HCl4
PC74HCro
PC74HC21
PC74HC27
PC74HC30
PC74HC32
PC74HCT32
PC74HC42
MM74HClO
MM74HCll
MM74HCl4
MM74HCro
CD74HC73
CD74HC74
CD74HCT74
CD74HC75
PC74HC73
PC74HC74
PC74HCT74
PCi4HC75
CD74HC85
CD74HC86
CD74HCT86
CD74HCI07
CD74HCI09
CD74HC1l2
PC74HC85
PCi4HC86
PC74HCT86
PCi4HCI07
PC74HCI09
PC74HC1l2
CD74HCI23
PC74HCl23
MM74HCOO
MM74HC04
MM74HCU04
MM74HCT04
SN74HC05
MC74HC27
MC74HC30
MC74HC32
SN74HC09
SN74HClO
SN74HCll
SN74HC14
SN74HCro
SN74HC21
SN74HC27
SN74HC30
SN74HC32
MC74HC42
MC74HC51
MC74HC73
MC74HC74
SN74HC42
SN74HC51
SN74HC73
SN74HC74
MC74HC75
MC74HC76
MC74HC85
MC74HC86
SN74HC75
SN74HC76
SN74HC77
SNi4HC85
SN74HC86
MC74HClO7
MC74HCI09
MC74HC1l2
MC74HCU3
SN74HCI07
SN74HCI09
SN74HC1l2
SN74HC1l3
MC74HCIO
MC74HCll
MC74HCl4
MC74HCro
RCA
MC74HCI23A
MC74HCl25
MC74HCI26
SN74HCI25
SN74HCI2li
MC74HCl32
MC74HCI33
MC74HC137
SN74HCI33
SN74HC137
CD74HCl25
CD74HCI26
I
PC74HCl25
PC74HCI26
CD74HCl32
PC74HCl32
CD74HC137
PC74HCl37
HC-821
MM74HC27
MM74HC30
MM74HC32
MM74HC42
MM74HC51
MM74HC73
MM74HC74
MM74HCT74
MM74HC75
MM74HC76
MM74HC85
MM74HC86
MM74HCI07
MM74HCI09
MM74HC1l2
MM74HC1l3
MM74HCI23A
MM74HCI25
MM74HCl26
MM74HCl32
MM74HCI33
MM74HC137
CROSS REFERENCE GUIDE
TOSHIBA
TC74HCT137A
TC74HCl38A
TC74HCTl38A
TC74HCl39A
TC74HCTl39A
TC74HC147A
TC74HCl48A
TC74HC151A
TC74HCl53A
i'C74HCl54A
TC74HCl55A
TC74HC157A
i TC74HCT157A
! TC74HCl58A
I TC74HGTl58A
TC74HCi60A
TC74HC161A
I
ITC74~C162A
TC74HCl63A
I TC74HCl64A
TC74HCTl64A
. TC74HCl65A
: TC74HCl66A
TC74HC173A
TC74HC174A
TC74HCT174A
i TC74HC175A
! TC74HC181A
I TC74HC182A
I TC74HCl90A
I TC74HC191A
i TC74HC192A
TC74HCl93A
! TC74HCl94A
TC74HC195A
TC74HC221
TC74HC221A
TC74HC237A
TC74HC238A
TC74HC240A
TC74HCT240A
I TC74HC241A
I TC74HCT241A
i TC74HC242A
TC74HC243A
I
I
I
i
!
i
MOTOROLA
MC74HCl38
MC74HCl39
TI
SN74HCT137
SN74HCl38
SN74HCTl38
SN74HCl39
MC74HC151
MC74HCl53
MC74HCl54
SN74HC147
SN74HC148
SN74HC151
SN74HCl53
SN74HCl54
MC74HC157
SN74HC157
MC74HCl58
SN74HCl58
MC74HCl60
MC74HC161
MC74HC162
MC74HCl63
MC74HCl64
SN74HCl60
SN74HC161
SN74HC162
SN74HCl63
SN74HCl64
MC74HCl65
MC74HCl66
MC74HC173
MC74HC174
SN74HCl65
SN74HCl66
SN74HC173
SN74HC174
MC74HC175
MC74HC181
MC74HC182
MC74HCl90
MC74HC191
MC74HC192
MC74HCl93
MC74HC194
MC74HC195
SN74HC175
MC74HC147
MC74HC221A
MC74HC237
MC74HC240
MC74HCT240
MC74HC241
MC74HCT241
MC74HC242
MC74HC243
SN74HCl90
SN74HC191
SN74HC192
SN74HCl93
SN74HC194
SN74HC195
SN74HC237
SN74HC238
SN74HC240
SN74HCT240
SN74HC241
SN74HCT241
SN74HC242
SN74HC243
RCA
SIGNETICS
CD74HCT137
CD74HCl38
CD14HCTl38
CD74HCl39
CD74HCTl39
CD74HC147
PC74HCT137
PC74HCl38
PC74HCTl38
PC74HCl39
PC74HCTl39
PC74HC147
CD74HC151
CD74HCl53
CD74HCl54
PC74HC151
PC74HCl53
PC74HCl54
CD74HC157
CD74HCT157
CD74HCl58
CD74HCTl58
CD74HCl60
CD74HC161
CD74HC162
CD74HCl63
CD74HCl64
CD74HCTl64
CD74HCl65
CD74HCl66
CD74HC173
CD74HC174
CD74HCT174
CD74HC175
CD74HC181
CD74HC182
CD74HCl90
CD74HC191
CD74HC192
CD74HCl93
CD74HCl94
CD74HC195
CD74HC221
PC74HC157
PC74HCT157
PC74HCl58
PC74HCTl58
PC74HCl60
PC74HC161
PC74HC162
PC74HCl63
PC74HCl64
PC74HCTl64
PC74HCl65
PC74HCl66
PC74HC173
PC74HC174
PC74HCT174
PC74HC175
PC74HC181
PC74HC182
PC74HCl90
PC74HC191
PC74HC192
PC74HCl93
PC74HCl94
PC74HC195
PC74HC221
CD74HC237
CD74HC238
CD74HC240
CD74HCT240
CD74HC241
CD74HCT241
CD74HC242
CD74HC243
PC74HC237
PC74HC238
PC74HC240
PC14HCT240
PC74HC241
PC74HCT241
P<;i4HC242
PC74HC243
HC-822
NATioNAL
SEMICONDUCTOR
MM74HCl38
MM74HCTl38
MM74HCl39
MM74HC147
MM74HC151
MM74HCl53
MM74HCl54
MM74HCl55
MM74HC157
MM74HCT157
MM74HCl58
MM74HCTl58
MM74HCl60
MM74HC161
MM74HC162
MM74HCl63
MM74HCl64
MM74HCTl64
MM74HCl65
MM74HC173
MM74HC174
MM74HC175
MM74HC181
MM74HC182
MM74HCl90
MM74HC191
MM74HCl92
MM74HCl93
MM74HCl94
MM74HCI95
MM74HC221A
MM74HC237
MM74HC238
MM74HC240
MM74HCT240
MM74HC241
MM74HCT241
MM74HC242
MM74HC243
CROSS REFERENCE GUIDE
TOSHIBA
TC74HC244A
TC74HCT244A
TC74HCZ45A
TC74HCT245A
TC74HC251A
TC74HC253A
TC74HC257A
TC74HCT257A
TC74HC258A
I TC74HCT258A
i TC74HC2.i9A
TC74HC266A
TC74HC273A
TC74HCT273A
TC74HC279A
TC74HC280A
TC74HC283A
TC74HC298A
TC74HC299A
TC74HC323A
TC74HC352A
TC74HC353A
TC74HC354A
TC74HCJ56A
TC74HC365A
TC74HC366A
TC74HC367A
TC74HC366A
TC74HC373A
TC74HCT373A
TC74HC374A
TC74HCT374A
TC74HC375A
TC74HC377A
TC74HC386A
TC74HC390A
TC74HC393A
TC74HC423
TC74HC423A
TC74HC5.33A
I TC74I-1CT533A
TC74HC534A
I TC74HCT534A
TC74HC5-IOA
! TC74HCT540A
~
I
MOTOROLA
I MC74HC244
MC74HCT244
I MC74HC245
MC74HCT245
MC74HC251
MC74HC253
MC74HC257
TI
I
I SN74HC244
SN74HCT244
I SN74HC245
SN74HCT245
I SN74HC251
SN74HC253
SN74HC257
I
SN74HC258
~jC74HC259
SN74HC259
SN74HC266
SN74HC273
MC74HC266
MC74HC273
MC74HC280
MC74HC283
MC74HC298
MC74HC299
SN74HC280
I
I
MC74HC393
11C74HC533
MC74HCT533
MC74HC534
MC74HCT534
MC74HC540
MC74HCT540
SN74HC533
SN74HCT533
SN74HC534
SN74HCT534
SN74I-1C540
SN74HCT540
IMC74HC390
NATIONAL
SEMICONDUCTOR
MM74HC244
MM74HCT244
MM74HC245
MM74HCT245
MM74HC251
MM74HC253
MM74HC257
MM74HCT257
SIGNETICS
CD74HC244
CD74HCT244
CD74HC245
CD74HCT245
CD74HC251
CD74HC253
CD74HC257
CD74HCT257
CD74HC258
CD74HCT258
CD74HC259
PC74HC244
PC74HCT244
PC74HC245
PC74HCT245
PC74HC251
PC74HC253
PC74HC257
PC74HCT257
PC74HC258
PC74HCT258
PC74HC259
CD74HC273
CD74HCT273
PC74HC273
PC74HCT273
CD74HC280
CD74HC283
PC74HC280
PC74HC283
CD74HC299
PC74HC299
CD74HC354
CD74HC356
CD74HC365
CD74HC366
CD74HC367
CD74HC368
CD74HC373
CD74HCT373
CD74HC374
CD74HCT374
PC74HC354
PC74HCJ56
PC74HC365
PC74HC366
PC74HC367
PC74HC368
PC74HC373
' PC74HCT373
PC74HC374
PC74HCT374
CD74HC377
PC74HC377
CD74HC390
CD74HC393
CD74HC423
PC74HC390
PC74HC393
PC74HC423
CD74HC533
CD74HCT533
CD74HC534
CD74HCT534
CD74HC540
CD74HCT540
PC74HC533
PC74HCT533
PC74HC534
PC74HCT534
PC7.4HC540
PC74HCT540
I SN74HC298
SN74HC352
SN74HC353
SN74HC354
SN74HC356
SN74HC365
SN74HC366
SN74HC367
SN74HC368
SN74HC373
SN74HCT373
SN74HC374
SN74HCT374
SN74HC375
Sl'i74HC377
SN74HC386
SN74HC390
SN74HC393
MC74HC354
MC74HC356
MC74HC365
MC74HC366
MC74HC367
MC74HC368
MC74HC373
MC74HCT373
MC74HC374
MC74HCT374
RCA
I MM74HC259
MM74HC266
MM74HC273
MM74HCT273
MM74HC280
I MM74HC283
MM74HC298
MM74HC299
MM74HC323
MM74HC354
MM74HC356
MM74HC365
MM74HC366
I MM74HC367
I
t
MM74HC368
MM74HC373
MM74HCT373
MM74HC374
MM74HCT374
I
MM74HC390
MM74HC393
MM74HC423A
HC-823
~lM74HC533
MM74HCT533
I MM74HC534
MM74HCT534
MM74HC540
MM74HCT540
I
--
CROSS REFERENCE GUIDE
TOSHIBA
TC74HC541A
TC74HCT54IA
TC74HC563A
TC74HCT563A
TC74HC564A
TC74HCT564A
TC74HC573A
TC74HCT573A
TC74HC574
TC74HCT574
TC74HC590A
TC74HC592A
TC74HC593A
TC74HC595A
TC74HC597A
TC74HC620A
TC74HC623A
TC74HC640A
TC74HCT640A
TC74HC643A
TC74HCT643A
TC74HC646A
TC74HCT646A
TC74HC648A
TC74HCT648A
TC74HC651A
TC74HCT651A
TC74HC652A
TC74HCT652A
TC74HC670A
TC74HC688A
TC74HCT688A
TC74HC690A
TC74HC691A
TC74HC692A
TC74HC693A
TC74HC696A
TC74HC697A
TC74HC698A
TC74HC699A
TC74HC4002A
I TC74HC4016A
TC74HC4017A
TC74HC4020A
TC74HC4022A
I
I
MOTORO~MC74HC541
MC74HCT541
MC74HC563
MC74HC564
MC74HC~73
MC74I-lC574
MC74HC595
MC74HC597
MC74HC620
MC74HC623
MC74HC640
MC74HCT640
MC74HC643
MC74HCT643
MC74HC646
MC74HCT646
MC74HC648
MC74HC651
MC74HC652
MC74HC670
--MC74HC688
TI
: ~N74HC541
i SN74HCT541
SN74HC563
SN74HCT563
SN74HC564
SN74HCT564
SN74HC573
SN74HCT573
SN74HC574
SN74HCT574
I
SN74HC620
SN74HC623
SN74HC640
SN74HCT640
SN74HC643
SN74HCT643
SN74HC646
SN74HCT646
SN74HC648
SN74HCT648
SN74HC651
SN74HCT651
SN74HC652
SN74HCT652
SN74HC688
RCA
CD74HC541
CD74HCT541
CD74HC563
CD14HCT563
CD74HC564
CD74HCT564
CD74HC573
CD74HCT573
CD74HC574
CD74HCT574
SIGNETICS
PC74HC541
PC74HCT541
PC74HC563
PC74HCT563
PC74HC564
PC74HCT564
PC74HC573
PC74HCT573
PC74HC574
; PC74HCT574
I
CD74HC597
PC74HC597
CD74HC640
CD14HCT640
CD74HC643
CD74HCT643
CD74HC646
CD74HCT646
CD74HC648
CD74HCT648
PC74HC640
PC74HCT640 PC74HC643
PC74HCT643
PC74HC646
PC74HCT646
PC74HC648
PC74HCT648
CD74HC670
CD74HC688
CD74HCT688
PC74HC670
PC74HC688
PC74HCT688
NATIONAL
SEMICONDUCTOR
MM74HC541
MM74HCT541
MM74HC563
MM74HCT563
MM74HC564
MM74HCT564
MM74HC573
MM74HCT573
MM74HC574
MM74HCT574
MM74HC590
MM74HC592
MM74HC593
MM74HC595
MM74HC597
MM74HC640
MM74HCT640
MM74HC643
MM74HCT643
MM74HC646
MM74HC648
MM74HC668
MM74HCT688
I
i
MC74HC4002
MC74HC40l6
MC74HC4017
MC74HC4020
I SN74HC4002
SN74HC4017
SN74HC4020
SN74HC4022
CD74HC4002
CD74HC4016
CD74HC4017
CD74HC4020
! PC74HC4002
IPC74HC4020
~~~:~~:;
I
HC-824
MM74HC4002
MM74HC4016
MM74HC4017
MM74HC4020
CROSS REFERENCE GUIDE
i!
TOSHIBA
!
i
TCi4HC4024A
TC74HC4028A
TCi4HC4040A
TC74HC4049A
TC74HC4050A
PC74HC4024
NATIONAL
SEMICONDUCTOR
..
MM14HC4024
CD74HC4040
CD14HC4049
CD74HC4050
CD74HC4051
CD74HC4052
CD74HC4053
CD74HC4060
CD74HC4066
PC74HC4040
PC74HC4049
PC74HC4050
PC74HC4051
PC74HC4052
PC74HC4053
PC74HC4060
PC74HC4066
MM14HC4040
MM14HC4049
MM74HC4050
MM74HC4051
MM74HC4052
MMi4HC4053
MM74HC4060
MM74HC4066
CDi4HC4075
PC74HC4075
MM74HC4075
MM74HC4078
CD14HC4094
CD74HC40102
CD74HC40103
CD74HC40105
CD74HC4316
CD74HC4351
CD74HC4352
CD74HC4353
CD74HC4511
CD74HC4514
CD74HC4515
CD74HC4518
CD74HC4520
CD74HC4538
CD74HC4543
PC74HC4094
PC74HC40102
PC74HC40103
PC74HC40105
PC74HC4316
PC74HC4351
PC74HC4352
PC74HC4353
PC74HC4511
PC74HC4514
PC74HC4515
PC74HC4518
PC74HC4520
PC74HC4538
PC74HC4543
TI
RCA
MCi4HC4024
SN74HC4024
CD14HC4024
~IC74HC4040
SN14HC4040
MC74HC4049
MCi4HC4050
MC74HC4051
MC74HC4052
MCi4HC4053
MC74HC4060
MC74HC4066
SN74HC4060
SN74HC4066
MC74HC4075
MC74HC4078
SN74HC4075
SN74HC4078A
SIGNETICS
-
I
ITC74HC4051A
TC74HC4052A
TC74HC4053A
TC74HC4060A
TC74HC4066A
TC74HC4072A
TC74HC4075A
. TC74HC4078A
TC74HC4094A
, TCi4HC40102A
TC74HC40103A
TC74HC40105A
TCi4HC4316A
TC74HC4351A
TC74HC4352A
TC74HC4353A
TCi4HC4511A
TC74HC4514A
TC74HC4515A
TCi4HC4518A
TC74HC4520A
TC74HC4538A
TC74HC4543A
TC74HCT7007A
. TC74HC7240A
! TCi4HC7241A
TC74HC7244A
I TC74HC7266A
TC74HC7292A
i TC74HC7294A
TC74HC7640A
TC74HC7643A
TCi4HC7645A
MOTOROLA
I
I
MC74HC4316
MC74HC4351
MC74HC4352
MC74HC4353
MC74HC4511
MC74HC4514
SN74HC4514
SN74HC4515
I
I
I
I
I
MC74HC4538
MC74HC4543
MC74HC7266
SN74HC7266
CD74HC7266
I
I
I.
I
HC-825
.MM74HC4316
MM74HC4511
MM74HC4514
MM74HC4518
MM74HC4520
MM74HC4538
MM74HC4543
NOTES
Source Exif Data:
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