1990_VTI_Computer_Products 1990 VTI Computer Products

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•

VLSI TECHNOLOGY, INC.

COMPUTER
PRODUCTS
DATA MANUAL

FEBRUARY 1990

Logic Products Division

bbd ELECTRONICS, INC.
TORONTo-HEAil 0Ff1CE CANADA
6685- 1 Mmcreek Drive,
TEL: (416) 821-7600
Mississauga, Ontario,
FJ>:t.: (416~821-4541
Canada L5N 5M5

ROCHESlER. NEW YORK-HEAD 0FF1CE. U.SA
820 Cross Keys Office Park,
Ta (716) 425-4101
Fairport, New Yorl<,
FJ>:t.: (71~) 425-1112
U.SA 14450

411 Roosevett Ave, Ste. 20 1, onawa, Ontano K2A SX9
298 Lakeshore Ad, SUte 203, Pt>i:1te Clare, Que, H9S 4L3
200- 12165 Hams Rd., Pitt Meadows, B.C. V3Y lZ2

TELi613) 729-0023 FAX:(613) 729-42~
TEL~514) 697-0801 FJ>:t.~5t4) 697-0277
TEL:(604) 465-6892 FJ>:t.~604) 465-9841 . /

$10.00

•

VLSI TECHNOLOGY, INC.

COMPUTER
PRODUCTS
DATA MANUAL
FEBRUARY 1990

logic Products Division

•

VLSI TECHNOLOGY, INC.

The information contained in this document has been carefully checked and is believed to be reliable. However, VLSI
Technology, Inc., (VLSI) makes no guarantee or warranty concerning the accuracy of said information and shall not be
responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, it. VLSI does not guarantee
that the use of any information contained herein will not infringe upon the patent or other rights of third parties, and no patent or
other license is implied hereby.
This document does not in any way extend VLSI's warranty on any product beyond that set forth in its standard terms and
conditions of sale. VLSI Technology, Inc., reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
LIFE SUPPORT APPLICATIONS
VLSI Technology, Inc., products are not intended for use as critical components in life support appliances, devices, or systems in
which the failure of a VLSI Technology product to perform could reasonably be expected to result in personal injury.
'© 1990 VLSI Technology, Inc. Printed in U.S.A.

•

VLSI TECHNOLOGY, INC.
PREFACE

This manual provides the reader with an in-depth technical reference on the VlSI Technology,
Inc. families of computer product chip sets and devices. In the body of the text all devices are
treated as individuals so that the electrical characteristics of each can be clearly defined. A
"Selector Guide" in the front of this manual defines which devices should be selected to form a
chip set that meets his or her system performance specifications. If the system designer requires
performance or functions not included in this manual, h.e or she should contact their local VlSI
Technology Design Center or Sales office. Most of the devices in this manual were designed
with VlSI's tools, and are available for ASIC designs if the designer wishes to design derivative
product.
Since computer technology is extremely fast-moving, it is planned that VlSI's logic Products
Division will revise, update, and publish this manual often. This will allow rapid publication of
data on new products, as well as improvements on existing ones. The most current information
may also be obtained from your local VlSI Technology, Inc. Sales Office, Representative, or the
logic Products Division in Tempe, Arizona.
Readers are encouraged to send their comments, corrections, or suggestions to:
Manager, Technical Communications
VLSI Technology, Inc.
8375 South River Parkway
Tempe, AZ 85284

iii

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VLSI TECHNOLOGY, INC.
PREFACE

•

VLSI TECHNOLOGY, INC.
CONTENTS
PAGE
NUMBER

SECTION 1. INTRODUCTION

Computer Products Data Manual ........................................................................................................................................... 1-3
General .................................................................................................................................................................................1-3
Megacells ............................................................................................................................................................................... 1-3
Megacell-Based Design Rationale ......................................................................................................................................... 1-4
Current Family of Megacells ................................................................................................................................................... 1-4
Designing a Circuit Using Megacells ...................................................................................................................................... 1-4
Additional Logic for Test Simplification ................................................................................................................................... 1-4
Test Program Development .................................................................................................................................................... 1-4
Completing the Design ........................................................................................................................................................... 1-5
Summary ................................................................................................................................................................................ 1-5

SECTION 2. ORDERING AND PACKAGING INFORMATION
General .................................................................................................................................................................................2-3
Package Considerations ........................................................................................................................................................2-4
Dual-In-Line Packages ...........................................................................................................................................................2-4
Small-Outline Integrated Circuits ............................................................................................................................................2-4
Chip Carriers ..........................................................................................................................................................................2-4
Chip-On-Board Mounting .......................................................................................................................................................2-5
Pin Grid Array .........................................................................................................................................................................2-5
Flatpack .................................................................................................................................................................................2-5
System Considerations ...........................................................................................................................................................2-5
Conclusion ..............................................................................................................................................................................2-6
Thermal Considerations .........................................................................................................................................................2-6

SECTION 3_ SELECTOR GUIDE
VL82CPCAT (12 MHz, 0/1 WS) .............................................................................................................................................3-3
VL82CPCAT-16 (16 MHz, 0/1 WS) ........................................................................................................................................3-3
VL82CPCPM-16 (16 MHz, Page-Mode) ................................................................................................................................ 3-4
VL82CPCAT-20 (20 MHz, 0/1 WS) ........................................................................................................................................ 3-4
VL82CPCPM-20 (20 MHz, Page-Mode) ................................................................................................................................ 3-5
VL82C106 PC/AT-, Super XT-Compatible Combo I/O Chip .................................................................................................. 3-5
VL82C286-SET '286/'386SX Chip Set (TOPCAT) ................................................................................................................3-6
VL82C386-SET '386 Chip Set (TOP CAT) .............................................................................................................................3-6

•

VLSI TECHNOLOGY, INC.
CONTENTS
PAGE
NUMBER

SEcnON 4. PClAT-compatlble Devices

VL82C100 CMOS PC/AT-Compatible Peripheral Controller ................................................................................................. 4-3
VL82C101B CMOS PC/AT-Compatible System Controller .................................................................................................4·25
VL82C102A CMOS PC/AT-Compatible Memory Controller ...•••.•....•••.......•.......•............................•......•............................. 4-49
VL82C103A CMOS PC/AT·Compatible Address Buffer ....•................................................................................................. 4-65
VL82C104 CMOS PC/AT·Compatible Data Buffer ..............................................................................................................4·77
VL82C201 CMOS PC/AT-Compatible High Speed System Controller .....•......................................................................... 4·87
VL82C202 CMOS PC/AT-Compatible High Speed Memory Controller .................................•.........•................................4·113
VL82C203 CMOS PC/AT-Compatible High Speed Address Buffer ..•.......•...........................•.................•.........................4·131
VL82C204 CMOS PC/AT-Compatible High Speed Data Buffer ........................................................................................ 4-143
VL82C205A CMOS PC/AT-Compatible Page·Mode Access Controller ............................................................................4·157
VL82C286·SET '286f386SX Chip Set (TOPCAT Preview) ...............................................................................................4·173
VL82C386·SET '386 Chip Set (TOPCAT Preview) ........................................................................................................... 4·174
SEcnON 5. Supar XT·Compatlble Devices
VL82C031 CMOS Super XT·Compatible System Controller ................................................................................................. 5-3
VL82C032 CMOS Super XT-Compatible I/O Controller ...................................................................................................... 5·29
SEcnON 6. Peripherals
VL 16C450 • VL82C5OA • VL82C50 CMOS Asynchronous Communications Elements ....................................................... 6-3
VL16C451 • VL16C451B CMOS Asynchronous Communications Element With Parallel Port ........................................... 6·23
VL16C452· VL16C452B CMOS Dual Asynchronous Communications Element With Parallel Port .................................. 6·51
VL16C550 CMOS Asynchronous Communications Element With FIFO ............................................................................. 6·75
VL 16C551 CMOS Asynchronous Communications Element With Parallel Port and FIFO ................................................. 6·97
VL 16C552 CMOS Dual Asynchronous Communications Element With Parallel Port and FIFO ....................................... 6·127
VL82C037 CMOS Video Graphics Controller (VGA) .........................................................................................................6·151
VL82C106 CMOS PC/AT·, SuperXT-Compatible Combo 110 Chip .................................................................................. 6·185
VL82C37A CMOS Direct Memory Access (DMA) Controller ............................................................................................ 6·221
SEcnON 7. PACKAGE OUTUNES...................................................................................................................................7-3
SEcnON 8. SALES OFFICES, DESIGN CENTERS, AND DISTRIBUTORS.................................................................... 8·3

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VLSI TECHNOLOGY, INC.
CONTENTS

DEVICE
NUMBER

DESCRIP'nON

PAGE
NUMBER

VL16C450
VL16C4511B
VL16C452IB
VL16C550
VL16C551
VL16C552
VL82C031
VL82C032
VL82C037
VL82C100
VL82C101B
VL82C102A
VL82C103A
VL82C104
VL82C106
VL82C201
VL82C202
VL82C203
VL82C204
VL82C205A
VL82C286-SET
VL82C37A
VL82C3B6-SET

CMOS Asynchronous Communications Elements ...............................................................•.............•....... 6-3
CMOS Asynchronous Communications Element Wrth Parallel Port ......................................•...•............. 6-23
CMOS Dual Asynchronous Communications Element With Parallel Port ................................................ 6-51
CMOS Asynchronous Communications Element With FIFO .................................................................... 6-75
CMOS Asynchronous Communications Element With FIFO ...............................................•...•................ 6-97
CMOS Dual Asynchronous Communications Element With FIFO .......................................•..........•...... 6-127
CMOS PS/2 Model30-Compatible System Controller .............................•.............................•................... 5·3
CMOS PS/2 Model30-Compatible I/O Controller ............•...................•.................................•................. 5-29
CMOS PS/2 Model30-Compatible Video Graphics Controller (VGA} ..........................•......................... 6-151
CMOS PC/AT-Compatible Peripheral Controller •.............•......................................................................... 4-3
CMOS PC/AT-Compatible System Controller ....•................................................................•.....•............•.4-25
CMOS PC/AT-Compatible Memory Controller ...•.............••.....•......•..••..................................................... 5-49
CMOS PC/AT-Compatible Address Buffer ...•...•••..••.............•................................................................... 4-65
CMOS PC/AT-Compatible Data Buffer .....................................................................................................4-77
CMOS PC/AT-, PS/2-Compatible Combo VO Chip (Preview) ...........................•..................•................. 6-185
CMOS PC/AT-Compatible High Speed System Controller .................................................•....................4-87
CMOS PC/AT-Compatible High Speed Memory Controller .......................•........................................... 4-113
CMOS PC/AT-Compatible High Speed Address Buffer .........................................................................4-131
CMOS PC/AT·Compatible High Speed Data Buffer ...............................................................................4-143
CMOS PC/AT-Compatible Page-Mode Access Controller ..................................................................... 4-157
'286f386SX Chip Set (TOPCAT Preview) .....•.............•.......................................................................... 4-173
CMOS Direct Memory Access (DMA) Controller ..••.............••.........•....................................................... 6-221
'386 chip Set (TOPCAT Preview) ................................................•.......................................•..................4-174

vii

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VLSI TECHNOLOGY, INC.
CONTENTS

viii

•

VLSI TECHNOLOGY, INC.
CONTENTS

INTRODUCTION

ORDERING AND PACKAGING INFORMATION

SELECTOR GUIDE

PC/AT-COMPATIBLE DEVICES

SUPER XT-COMPATIBLE DEVICES

PERIPHERALS

PACKAGE OUTLINES

EI
•

III

II
all
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SALES OFFICES, DESIGN CENTERS, AND DISTRIBUTORS •

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VLSI TECHNOLOGY, INC.

•

VLSI TECHNOLOGY, INC.

SECTION 1

INTRODUCTION

Logic Products Division

•

VLSI TECHNOLOGY, INC.

•

VLSI TECHNOLOGY, INC.
INTRODUCTION

COMPUTER PRODUCTS DATA MANUAL
GENERAL
The primary business objective of VLSI
Technology, Inc., (VLSI) is to provide
systems designers with total application-specific integrated circu~ (ASIC)
solutions. To accomplish this, ~ has
created a unique blend of expert design
tools, leading-edge process technologies, state-of-the-art fabrication
facilities, and a wide range of products,
including a variety of "catalog" devices.
The Logic Products Division of VLSI
Technology is responsible for the
manufacture and marketing of a diverse
logic-based product line that encompasses both innovative and proven, well
established catalog devices. This line
includes microprocessors and
coprocessors, peripheral circu~s, and
products for data communications and
telecommunications applications.
Unlike other suppliers of such devices,
however, VLSI is also a recognized
leader in ASICs. As such, ~ not only
possesses the design, process, and
fabrication capabilities necessary to
produce the highest-quality off-the-shelf
components, but is also able to treat ~s
logic products as an integral part of a
complete solution. The primary

vehicles for accomplishing this are the
megacell and cores; many of the
functions represented by individual
devices are implemented as megacells
in VLSl's software libraries and used for
semicustom circuit design and functions
developed as megacells for specific
applications can be tumed into catalog
products. Most other functions are
available as high integration cores
which can be utilized by VLSI to create
variations of these standard products
for specific customer requirements.
MEGACELLS
The megacell is a relatively new
concept in the world of IC and system
design. As such ASIC companies as
VLSI offer better tools for IC design,
simulation, and testing, it becomes
necessary for systems manufacturers to
design custom ICs to keep up with their
competition. Megacells help decrease
design time by providing large building
blocks that are equivalents of standard
off-the-shelf products. By using megacells and VLSl's design tools, manufacturers can have a custom IC design
capability without all of the normal
custom development costs.

The VLSI Technology family of megacells represents commonly used
peripherals that are good candidates for
integration as parts of customer-driven
designs, which can be either customerspecific or market-specific. In customer-specific designs, it is possible, for
example, to combine these integration
elements with other megacells and logic
to become single-chip equivalents of
computer systems that are already in
production. This increased level of
integration provides cost and space
reduction that can keep the system
designs competitive. In a marketspecific design, upward-eompatible
enhancements that meet the needs of
many customers can be added and the
device offered as a new standard
product.
VLSl's megacells are designed to have
a fixed height and variable widths,
offering the best trade-off between
unusable internal space and placement
ease. As shown in Figure 1, they can
be configured to make a very dense
final design with a minimum of wasted
silicon real estate.

FIGURE 1. VLSI TECHNOLOGY MEGACELLS ARE OF A FIXED HEIGHT, WITH VARIABLE WIDTHS.

VSS

STO
CELLS

MEGACELL

VOO

V
1/0 INTERCONNECT

1-3

•

VLSI TECHNOLOGY, INC.
INTRODUCTION

Of equal importance with the physical
layout format of the cells is the structure
of the interconnect bus. This bus must
be generic enough to allow a wide
variety of functions to be connected
uniformly and efficiently, and must be
fast enough to not itself become a
limiting factor as system performance
increases.
The internal structure of the bus created
by VLSI for use with its megacells
contains an m-bit data bus and an n-bit
address bus, both of which are expandable in width to accommodate changes
in system requirements. The bus
operates synchronously at a rate of 3
million transfers a second, which is
equivalent to the performance of a 10
MHz 8086 or 12 MHz 68000 microprocessor. The bus definition allows for
internal access times of 50 ns and cycle
times in the 200 ns range. With
standard pad drivers, external loads
can be driven while supporting a 3 MHz
bus frequency; faster speeds can be
obtained by using faster pad drivers.
To create a standard product from a
megacell, an interface circuit is incorporated that exactly matches the slower
timing of the extemal bus to the internal
bus.
MEGACELL-BASED DESIGN
RAnONALE
There are many reasons why megacells
make sense for new designs, including
reduced board space, lower power,
increased reliability and reduced design
times.
Typical applications that can benefit
from the use of megacells are those
that contain three or four LSI components and a handful of "glue" components. All of these components can be
combined into a single component if the
functions can be partitioned into logical
groups with a reasonable number of LO
pins. In this type of application, the
total pin count might be reduced from
300 pins for a discrete solution to less
than 100 pins, and the circuit board
area reduced from approximately 20
square inches to 2 square inches.
The power consumption of megacell
designs can be very small in comparison with the HMOS designs they
replace, since all of the VLSI Technology megacell family is implemented in

high speed, low power, two-micron and
1.5-micron CMOS technology. In
addition, because several functions can
be put on one piece of silicon, the
interconnect capacitance and inductances are minimized, thereby reducing
the power to a fraction of what was
needed in previous designs.
The reliability of a megacell-based
design is typically better than the
collection of discrete components it
replaces because there are fewer pins,
fewer bonding wires and lower total
power consumption. In most systems,
the largest contributor to reliability
problems is IC pin connections, with
such other factors as die temperature
and die size being secondary. The
more functional blocks that can be
combined on a single piece of silicon,
the fewer the number of interconnections that have to be bonded to package pins, resulting in higher overall
reliability of the component and system
using it.
Since megacells can be used as high
level building blocks, overall design
times can be reduced significantly by
taking existing designs using standard
products and integrating additional
support logic directly onto the chip. An
example of this technique would be the
integration of a VL68C45 CRT controller with a memory interface and video
shift registers to form a single-<:hip
video adapter. An additional option
might be to include character ROMs or
RAM arrays, although the addition of
these commodity components is not
always cost effective.
CURRENT FAMILY OF MEGACELLS
Megacells are designed by very
carefully studying the data sheets and
systems implementations of the original
part vendors, but an important part of
validating a megacell design is to
subject it to many different hardware
and software environments. Only after
a part has been tested in several
applications can a vendor feel confident
that the megaceU exactly emulates the
original function, induding all of the
undocumented "features". The VLSI
Technology philosophy is to offer
members of the megacell family as
standard products as well as cells so
that this validation can take place very
quickly after the introduction of the

1-4

standard product. Since customerspecific design times typically take from
two to four months, megacell designs
can be started before the standard
product validation has been done. This
lead time allows customers to get a
head start introducing designs.
DESIGNING A aRCUIT USING
MEGACELLS
The design process is started by using
a megacell schematic "icon" as part of
the schematic entry of the user"s
design. Provided with the megacell
icon is a data sheet detailing the
internal timing requirements of the
megacell. The designer works from this
data sheet as if using an off-the-shelf
standard product, except that the logic
and timing of the bus are somewhat
easier to use.
ADDInONAL LOGIC FOR TEST
SIMPLlFICAnON
In all cases, some additional logic will
be necessary to facilitate testing the
megacells. This additional logic
consists of multiplexers on pins to allow
all of the connections of the megacell to
be accessed from the periphery of the
circuit. This dictates that all designs be
contained in packages having at least
as many pins as the most pin-intensive
megacell used internally. To enable the
test mode, an illegal condition on the
interface is often used, such as Read
Strobe and Write Strobe being asserted
together while the chip is selected. This
would normally never occur in an
application, so it is a safe combination
to use. When enabled, the LO pads of
a specific megacell are connected to
the LO pins of the component, and the
standard product test program run to
verify the functionality of the core.
TEST PROGRAM DEVELOPMENT
Test vectors are provided for all
megacells with high fault coverage.
These test programs can be integrated
with the rest of the chip's test program
using VLSlvector. VLSI provides these
"canned" test programs with each
megacell so that it will not be necessary
to spend time trying to develop a test
for megaeells used in the design.
These test programs ensure that he
megacells have been fabricated
correctly and are functioning within their
specifications. They are developed with
a focus on very high fault coverage.

•

VLSI TECHNOLOGY, INC.
INTRODUCTION

In fact, there is no need to simulate
these test programs, except for a final
verification that the test isolation
circuitry has been properly connected.
Instead designers can devote additional
design verification time to the nonmegacell portions of the circuit and the
interfaces between the megacell and
the rest of the circuit.

COMPLETING THE DESIGN
When simulation is complete and the
design works satisfactorily, the layout
process can begin. In most cases,
designers are interested in minimizing
design time and associated costs, so
they pick standard cells for the additional blocks of logic that will surround
the megacell cores. Cells are individually compiled, placed and routed to
create blocks of logic until the entire
non-megacell portion 01 the design is
complete. For the best layout efficiency, the additional logic is either put
into a block having the same height as
a megacell, or it is put around the
megacells to fill in the voids. When
each portion of the design is completed,
these blocks can be placed and

interconnected using a tool called Chip
Compiler, which is an automated
arbitrary block place and route system.
This editor assists in interconnecting
blocks of cells and optimizing both the
placement and interconnection of cells.
The overall goal of placing blocks to
form the chip is to get the ratio of the X
and Y dimensions (the aspect ratio) as
close to 1:1 as possible. The resulting
square die gives the packaging
engineer the most flexibility in package
selection.
When the entire layout process is
complete, a netlist 01 interconnections is
extracted from the physical data base to
allow comparison of what was intended
to be with what actually was implemented. Once the extraction is
complete and the netlist comparison
between schematic and layout is
successful, the device can be resimulated in software with more accuracy,
since values of expected capacitance
are extracted along with the connectivity information. Finally, the layout is
checked for design rule violations using
the design rule checker (ORC) program.

1-5

When all 01 this has been successfully
completed, the data base is sent to a
design center, where the actual
physical layout of the megacells is
included in the data base. When
everything checks out properly, a mask
set is created and silicon is started.
From this point, the fabrication time
typically takes eight weeks for the first
pass prototypes.

SUMMARY
Megacells offer a way to quickly design
chips that replace today's board level
function, while at the same time oIfering
competitive costs, increased reliability,
increased performance and reduced
board space. The design process
requires a wide range of design tools,
including standard cells, cell compilers,
simulators, routers, test program .
generators, and libraries of designs.
VlSI Technology, Inc. specializes in
offering these kinds 01 tools in addition
to complete wafer services to provide a
total solution to systems designers.

•

VLSI TECHNOLOGY, INC.
INTRODUCTION

1-6

•

VLSI TECHNOLOGY, INC.

SECTION 2
ORDERING AND
PACKAGING
INFORMATION

Logic Products Division

•

VLSI TECHNOLOGY, INC.

•

VLSI TECHNOLOGY, INC.
ORDERING AND PACKAGING INFORMATION

GENERAL
VLSI Technology, Inc., Logic Products devices are available in a variety of plastic packages - including f1atpacks, chip carriers,
and pin grid arrays - and in different temperature ranges. Specific information on the packages and temperature ranges for
particular devices is coded into the part number portion of the order information included in each data sheet.
The information is organized as follows:
V

9999999

T
Temperature Code
Package Code

Corporate Code
"Logic" Products

Speed Code (Optional)
Base Part Number

Package Codes:

C - Sidebrazed Ceramic
F - Plastic Flatpack
G - Pin Grid Array
L - Leadless Ceramic Chip Carrier
P - Plastic Dual In-Line
Plastic Leaded Chip Carrier

Temperature Codes:

A - Automotive
C - Commercial
I - Industrial
M - Military

(-40°C to +85°C)
(O°C to +70°C)
(refer to spec.)
(--55°Cto +125°C)

2-3

•

VLSI TECHNOLOGY, INC.
ORDERING AND PACKAGING INFORMATION

ORDERING AND PACKAGING INFORMATION
PACKAGE CONSIDERATIONS
DUAL IN-LINE PACKAGES
The dual in-line package (DIP) has
been in high-volume production for
nearly twenty years, and is estimated to
have been the package of choice for
over 80% of all integrated circuits
shipped in 1985. Some 1986 usage
estimates are as high as 18 billion units
worldwide. Generally, devices in DIPs
can be purchased in two types of
ceramic (cerdip and side-brazed) and in
the very-familiar molded plastic package. Over 85% of all DIPs, or over 12
billion, sold worldwide in 1985 were
plastic.
The ceramic side-brazed package is
relatively expensive and is frequently
imported. It has excellent mechanical
characteristics, including the ability to
survive extreme temperatures, salt
water, and corrosive atmospheres.
However, as the cost of the integrated
circuit it houses becomes less and less
expensive, the relative cost of the
ceramic DIP becomes a major concern.
In a large number of applications, this
package is several times more expensive than the chip within it. As would be
expected, this package is very popular
in military electronics and in other
potentially harsh mechanical environments. The side-brazed package, while
representing less than 2% of all DIP
packages shipped in 1985, represents a
higher percentage of DIP revenue, due
to its comparatively high average selling
price (ASP).

The cerdip is a "sandwich" of two
ceramic parts that are joined together
by a cement-like epoxy. The die itseH is
mounted on a lead frame, and enjoys
many of the cost economies associated
with this approach. The cerdip has
some of the mechanical advantages of
the side-brazed ceramic at a lower cost.
The cerdip represented about 14% of
all DIP shipments in 1985.
The plastic DIP has been the catalyst
for the computer revolution. The
dramatic reduction in the cost of microprocessors, microprocessor peripherals, communications devices, and
memories has been passed along to
the manufacturers and the final users
because plastic packaging has remained extremely inexpensive. In
addition, reliable automated 16-pin and
14-pin DIP insertion equipment has dramatically reduced manual "board
stuffing" costs of DIPs. The plastic DIP
itself is easy to manufacture. The die is
mounted on a copper-alloy lead frame
and the plastic material is molded
around it. It is usually branded by a
printing method with an epoxy-based
ink but, recently,laser-scribing the
number into the plastic body is gaining
popularity, reducing costs even further.
Mechanically, the DIP has proven to be
an extremely utilitarian package in most
applications. Its short, stiff leads on
2.54 mm (0.1 inch, or 100 mil) centers
allow reasonably easy insertion for both
test and production by both manual and

2-4

automatic techniques. While more
expensive DIPs are placed in sockets,
the overwhelming majority are soldered
directly into the printed circuit board.
The 64-pin DIP, the largest DIP in highvolume production, is used to house
VlSI's Vl2010 and Vl2044 Multiplier!
Accumulators. DIP configurations with
higher pin counts tend to exhibit unacceptable mechanical problems, such as
extremely high insertion and extraction
forces.
DIPs are available, in even-pin-count
steps, in packages as low as two pins.
A variation of the DIP that has gained
some acceptance is the SIP, or single
in-line package. The SIP, mounted
lying on its edge, uses very little printed
circuit board space and frequently
contains a number of memory die in
high-density memory applications.
However, as desirable as the SIP may
seem, it is not the major evolutionary
path of the DIP. The SIP allows little air
circulation for cooling, it is hard to
handle, and is not generally accepted
as a standard. The DIP evolution lies in
surface mounting the device.

SMALL-OUTLINE INTEGRATED
CIRCUITS
The small-outline integrated circuit
(SOle) is a descendant of the DIP.
Sometimes called the "Swiss" outline
integrated circuit in honor of its country
of origin, this package solves many of
the problems of the DIP, while retaining
many of its advantages. The gull-wing

•

VLSI TECHNOLOGY, INC.
ORDERING AND PACKAGING INFORMATION

lead rests on top of the printed circuit
board rather than going through it. For
most types, its leads are exactly half the
length that the DIPs are, and it maintains the same basic rectangular
package aspect ratio of the DIP. This,
however, becomes a disadvantage in
high-pin-count applications. For more
than 28 pins, many designers prefer the
square aspect of the plastic leaded chip
carrier (PLCC) to the SOIC. The small
package mass of the SOIC does not
allow the same thermal dissipation that
can be expected in a standard DIP,
which becomes a minor problem as
more chips are made in the generally
lower power consuming CMOS
process. Most importantly, the SOIC
consumes only about 30% of the real
estate consumed by the standard DIP.
It is estimated that nearly 1.5 billion
SOIC units will be shipped in 1986.
CHIP CARRIERS
Chip carriers have been around for
several years in various forms, and are
just now coming into widespread usage.
Generally, the terminal spacing of chip
carriers is 1.27 mm (50 mils), but several special types have 1.0 mm (40 mil)
spacing for use by companies engaged
in the pocket pager business. Some
variations are available in 0.64 mm (25
mils) also. The ceramic versions of
chip carriers have become very popular
in military applications for the same
reason the ceramic side-brazed DIP
has: their mechanical ruggedness.
Frequently, ceramic lead less chip
carriers (LCCs) are soldered in; others
use connectors, while still others have
their own leads and are inserted as a
leaded device. Due to the dissimilar coefficient of expansion of materials
(package alumina and printed circuit
board fiberglass) and the lack of pins on
the leadless versions to provide
flexibility or compliance, the ceramic
lead less chip carriers should be soldered to a material that has the same
thermal expansion characteristics as
they have. This has become very
popular in military applications where
weight and space are at a premium
and, generally, cost is not the primary
consideration.
The plastic leaded chip carrier (PLCC)
has very quickly become the most
popular of all the chip carriers. The

PLCC represented about 61% of the
chip carriers shipped in 1985 (approximately 400 million units). Although
there is debate on the issue of board
space consumption, the PLCC and
SOIC consume about the same amount
of board space in the 24- to 28-pin configurations. In lower pin count applications, the SOIC seems to be more
space-effective; when over 24 pins or
so, the PLCC seems to have the edge
in most applications. In applications
over 28 pins, the PLCC is the surfacemount package of choice. Its square
aspect ratio allows many chip placements that the highly rectangular
package of the SOIC does not. In
addition, there are rectangular PLCCs
to accommodate such rectangular die,
such as memories.
CHIP-ON-BOARD MOUNTING
The ultimate in low-cost chip mounting
is achieved by the chip-on-board (COB)
technology, in which no discrete
package is actually employed. The die
is soldered onto a copper pad on a
printed circuit board. Bonding wires
connect the die to small bonding pads
around the die. The die and wires are
then covered by a dollop of epoxy. This
technique, while inexpensive, is not
generally accepted in industrial or
business equipment. It has been
extensively employed in video game
cartridges, and seems to work quite
well there.
PIN GRID ARRAY
The pin grid array (PGA), or "bed of
nails,' has only been around for ten
years, but had a usage of about 5
million in 1985, and its popularity is
growing rapidly. This major package
variation allows very high pin counts in
relatively small spaces with excellent
mechanical and thermal characteristics.
The 149-pin VL82C389 Message
Passing Coprocessor (MPC) for Multibus" II systems is a prime example of
PGA high-density trends. The major
disadvantage of the PGA is its high
cost. Virtually all of the 5 million PGA
units shipped in 1985 were ceramic.
Plastic pin grid arrays are well along in
development, and will provide reliable,
inexpensive packaging for the many
high-pin-count ASIC, memory, and
other circuits coming into wide usage.

2-5

FLATPACK
The flatpack holds less than 1% of the
IC package market. True to its name, it
is flat, small, and has flat leads usually
in the same place as the package body.
. It is generally harder to handle and test
-than the other package types, but
provides a surface mounting alternative
to the pin grid array in very-high-pincount applications. It is usually surface
mounted, ·socketed,· or suspended
through a cut-out hole in the printed
circuit board.
SYSTEM CONSIDERATIONS
In the extremely competitive computer
market that now exists, every repetitive
cost, no matter how small, comes under
close scrutiny. Drilling a hole in a
printed circuit board costs about
$0.001, a fairly small amount until it is
multiplied by the thousands of holes
that frequently occur in each board.
This becomes a significant consideration at the system level. Even though
re-tooling costs are high, many companies are converting (some at least
partially) to surface-mounting equipment. Surface mounting allows more
chips in a much smaller area, but not all
functions are yet available in surfacemount packages. Some companies
have solved this problem by designing
both through-the-board and surfacemount devices onto the same board.
Others continue to use the older
technology until they can re-tool for
100% surface mount.
Application-specific integrated circuits
(ASICs) and their support devices are
requiring packages with ever-increasing
pin counts. The pin count domain
diagram graphically depicts the typical
domain of pin counts for five basic
package types. While there is a good
deal of overlap, chip carriers and pin
grid arrays will become the package of
choice in future systems containing
devices of high pin count. Since the
PGA device does not support surfacemount technology, chip carriers or
flatpack technology will have to be
implemented as pin counts exceed 170
using surface-mounts systems.

•

VLSI TECHNOLOGY, INC.
ORDERING AND PACKAGING INFORMATION

CONCLUSION
There will be no panacea package that
will exclude the use of all others in the
future. While there are several criteria
for the system designer, Table 1
examines some of the characteristics of
packages that will probably occupy the
overwhelming majority of printed
circuits boards in the future. Leadless
chip carriers will be especially popular
in military and harsh industrial applications. The DIP, with many billions
already in use, will not disappear, but its
percentage of market will decrease
steadily. Pin grid arrays will remain and
increase in popularity as very large
devices become more popular and
plastic PGAs become readily available.
Surface mounting is definitely a wave of
the future for many systems. SOIC
packaging will increase rapidly for devices of 28 terminals and under, while
the mid-range and higher terminal count
devices will be housing in PLCCs or
flatpacks.

THERMALCON~DERATIONS

The devices in this data book have
undergone thorough evaluation and
characterization to ensure their operation over the specified temperature
ranges. While safety margins are used
for all parametric tests over the temperature range, the designer should not
exceed the temperature limits, even for
extremely short intervals. The following
notes are presented to ensure a reliable, long-lived system using VLSl's
products:

The ambient temperature (TA)
specification refers to the air on the
surface of the device. The printed
circuit board design should be
open enough to permit free air flow
around the devices.

Avoid layouts that place NMOS,
HMOS, or CMOS devices near
such heat sources as power
regulators and devices requiring
heat sinks. "the design demands
such proximity. ensure that the
specified temperature range is not
exceeded.

Ensure that the power supply
voltage is within the specified
range. Both low and high voltages
beyond the specified limits may
cause device overheating.

While few designs subject devices

to extreme cold, such conditions
may cause the devices to operate
outside of their normal specified
ranges. Therefore, the minimum
operating temperature specification
must be observed as well as the
maximum operating temperature.

2-6

•

VLSI TECHNOLOGY, INC.

SECTION 3
SELECTOR GUIDE

Logic Products Division

•

VLSI TECHNOLOGY, INC.

VLSI TECHNOLOGY, INC.
SELECTOR GUIDE
VLSI'S POPULAR 12 MHz CHIP SET
VL82CPCAT-QC (12 MHz 0/1 WS)
VL82C100-QC

VL82C103A-QC

II
II

VL82C1 01 B-QC

VL82C102A-QC

VL82C104-QC

FEATURES
• 100% PC/AT-Compatible

•

• 1 ws/120 ns DRAM, 0 wsl80 ns DRAM
• 8 MHz Backplane with External Clock Modulation PAL

VLSI'S FASTER 16 MHz CHIP SET
VL82CPCAT-16QC (16 MHz, 0/1 WS)

I
I

VL82C10Q-QC

VL82C203-16QC

II
II

VL82C201-16QC

VL82C204-16QC

II
I

FEATURES
• 100% PC/AT-Compatible
• 1 ws/80 ns DRAM, 0 ws/60 ns DRAM
• Shadow RAM Feature
• 8 MHz Backplane 110 Operation
• On-board EMS 4.0 Memory

3-3

VL82C202-16QC

•

VLSI TECHNOLOGY, INC.
SELECTOR GUIDE

VLSI'S FASTER ENHANCED 16 MHz CHIP SET
VL82CPCPM-16QC (16 MHz, PAGE-MODE)
I

VL82C100-QC

I VL82C201-16QC I

I VL82C202-16QC I

I VL82C203-16QC I

I VL82C204-16QC I

I VL82C205A-16QCI

FEATURES
• 100% PC/AT-Compatible
• Page-mode 0.6 ws with 100 ns DRAM
• Shadow RAM Feature
• 8 MHz Backplane I/O Operation
• On-board EMS 4.0 Memory

VLSI'S HIGH-SPEED 20 MHz CHIP SET
VL82CPCAT-20QC (20 MHz, 0/1 WS)
I VL82C100-20QC

VL82C203-20QC

II
II

VL82C201-20QC

VL82C204-20QC

II
I

VL82C202-20QC

FEATURES
• 100% PC/AT-Compatible
• 1 ws/80 ns DRAM
• Shadow RAM Feature
• 10 MHz Backplane VO Operation
• On-board EMS 4.0 Operation

3-4

•

VLSI TECHNOLOGY, INC.
SELECTOR GUIDE

VLSI'S HIGH-SPEED ENHANCED 20 MHz CHIP SET
VL82CPCPM-2QQC (20 MHz, PAGE-MODE)

VL82C100-2OQC

II
I

I VL82C203-20QC I

VL82C201-20QC

VL82C204-2QQC I

I VL82C202-2OQC

I VL82C205A-20QCI

FEATURES
• 100% PC/AT-Compatible
• 0.6 wslSO ns DRAM
• Shadow RAM Feature
• 10 MHz Backplane 110 Operation
• On-board EMS 4.0 Operation

VLSI'S HIGH-INTEGRATION PC/AT-COMPATIBLE DEVICES
COMBO
(RTC, KEYBOARD CONTROLLER,
DUAL UART, CENTRONICS, IDE
INTERFACE) PAGE 6-185

VL82C10S-QC

UART PAGE 6-3

VL 1SC450-QC

PAGE 6-75

UART/CENTRONICS PAGE 6-23
I VL 1SC451 B-QC
PAGE 6-51

VL 1SC550-QC

VL1SC452B-QC

PAGE 6-97

VL 1SC551-QC

PAGE 6-127

VL 1SC552-QC

Note: In addition to the commercial (OC) temperature range, TA = O·Cto +70·C, the 16 MHz and 20 MHz PCAT-compatible
chip sets are also available in the industrial (01) temperature range of TA = -40·C to +S5·C.

3-5

•

VLSI TECHNOLOGY, INC.
SELECTOR GUIDE

VLSI'S 286/386SX (TOPCAT) CHIP SET
VL82C286·SET

VL82C320-FC

VL82C331-FC

FEATURES
• 100% '286-based MPU PC/AT-Compatible
• Optimized Two Chip Design and Packaging Solution for '286-based Systems
• Up to 25 MHz System Clock Speeds
• ·Sleep· Modes Support Low-Power and Laptop Designs
• Full LIM EMS 4.0 Specification over Entire 32 Mbyte Memory Map
• Buih-in Three-state Control for Board level Testing
• Programmable DRAM and Slot Interface Drive Optimizes System for Actual load Conditions

VLSI'S 386DX (TOPCAT) CHIP SET
VL82C386·SET

VL82C33O-FC

VL82C331-FC

VL82C332-FC

FEATURES
• 100% '386-based MPU PC/AT-Compatible
• Optimized Three Chip Design and Packaging Solution for '386-based Systems
• Up to 33 MHz System Clock Speeds
• ·Sleep· Modes Support Low-Power and Laptop Designs
• Full LIM EMS 4.0 Specification over Entire 32 Mbyte Memory Map
• Built-in Three-state Control for Board level Testing
• Programmable DRAM and Slot Interface Drive Optimizes System for Actual load Conditions

3-6

•

VLSI TECHNOLOGY, INC.

SECTION 4
PC/AT-COMPATIBLE DEVICES

Logic Products Division

•

VLSI TECHNOLOGY, INC.

•

VLSI TECHNOLOGY, INC.
VL82C100
PC/AT-COMPATIBLE PERIPHERAL CONTROLLER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The VL82C100 PC/AT-Compatible
Peripheral Controller replaces two
82C37A Direct Memory Access
Controllers, two 82C59A Interrupt
Controllers, an 82C54 Programmable
Counter, a 74LS612 AT Memory
Mapper, two 74ALS573 Octal ThreeState Latches, a 74ALS138 3-to-8
Decoder, and five other less-complex
integrated circuits. Using this internal
functionality, the VL82C100 provides all
24 address bits for 16M bits of DMA
address space. It also interfaces
directly to the CPU to handle all

• Replaces 19 logic devices
Supports up to 20 MHz system clock
Device is available as "cores" for
user-specific designs
• Seven DMA channels
• 14 external interrupt requests
• Three timer/counter channels
• Designed in CMOS for low power
consumption

interrupts. Timing for refresh cycles,
and arbitration, between refresh and
DMA hold requests, are also controlled
by the VL82C100.
The device is manufactured with VLSl's
advanced high-performance CMOS
process and is available in JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
VL82C100 is part olthe PC/AT-compatible chip sets available from VLSI.
Please refer to the Selector Guide in the
front of this manual.

BLOCK DIAGRAM
;--SELECT
-MASTER -----DACK7

XMEMR
AND
READY
CONTROL

-XMEMR

CJ ....
XAO-XA3

.....
.......

HOLD REQUEST
....To ARBITER

UDMAREADY

... -

XA16

......-

HLDA
ROY

-XIOR.
-XIOW. -XMEMR.
-XMEMW.

......
XA10-16
r

r--)(A9.

ADSTB

HLDA FROM
ARBITER

lOCHROY

f-I
I EOP

ORO5ORO7

8237

XAl·XAS....

XDO-XD7

....
....

XA16
-XIOR
-XIOW
PAGE
REGISTERS
LS612

4-8

.....

A17·A23

•

VLSI TECHNOLOGY, INC.
VL82C100

TABLE 2. DMA CONTROLLER REGISTERS ADDRESSES
Hex Address
DMA2

DMA1

OCO

000

Channel 0 Base and Current Address Register

OC2

001

Channel 0 Base and Current Word Count Register

0C4

002

Channel t Base and Current Address Register

Ocs

003

Channel 1 Base and Current Word Count Register

OC8

004

Channel 2 Base and Current Address Register

OCA

005

Channel 2 Base and Current Word Count Register

OCC

006

Channel 3 Base and Current Address Register

OCE

007

Channel 3 Base and Current Word Count Register

000

008

Read Status RegisterlWrite Command Register

002

009

Write Request Register

004

OOA

Write Single Mask Register Bit

006

OOB

Write Mode Register

008

OOC

Clear Byte Pointer Flip-Flop

OOA

000

Read Temporary RegisterlWrite Master Clear

OOC

OOE

Clear Mask Register

ODE

OOF

Write All Mask Register Bits

register will readlwrite to the high byte
of the 16 bit register and the byte
pointer flip-flop will toggle back to a
zero. Refer to the 8237 data sheet for
more information on programming the
8237 megaeell.
The 8237 OMA controller megacells
allow the user to program the active
level (low or high) of the ORa and
-DACK signals. Sinee the two megacells are cascaded together internally
on the chip, these signals should
always be programmed with the ORa
signals active high and the -DACK
signals active low.
When programming the 16 bit channels
(channels 5, 6, and 7) the address
which is written to the base address
register must be the real address
divided by two. Also, the base word
count for the 16 bit channels is the
number of 16 bit words to be transferred, not the number of bytes as is the
case for the 8 bit channels.

It is recommended that all internal
locations, especially the mode registers,
in the 8237 megacells be loaded with
some valid value. This should be done
even if the channels are not used.
MIDDLE ADDRESS BIT LATCHES
The middle address bits of the 24 bit
address range are held in two sets of 8
bit registers, one register for each OMA
controller. The OMA controller will drive
the value to be loaded onto the data
bus and then issue an address strobe
signal to latch the data bus value into
these registers. An address strobe is
issued at the beginning of a OMA cycle
and any time the lower 8 bit address
increments across the 8 bit subpage
boundary during block transfers. These
registers cannot be written to or read
externally. They are loaded only from
the address strobe signals from the
megacells and the outputs go only to
the XA8-XA16 pins.

4-9

PAGE REGISTERS
The equivalent of a 74LS612 is used in
the VL82C1 00 to generate the page
registers for each OMA channel. The
page registers provide the upper
address bits during a OMA cycle. OMA
addresses do not increment or decrement across page boundaries. Page
boundaries for the 8 bit channels
(channels 0 through 3) are every 64
kilobytes and page boundaries for the
16 bit channels (channels 5, 6, and 7)
are every 128 kilobytes. There are a
total of 16 eight bit registers in the
74LS612 megacell. The page registers
are in the 110 address space as shown.
Page Register
OMA channel 0
OMA channel 1
OMA channel 2
OMA channel 3
OMA channelS
OMA channel 6
OMA channel 7
Refresh

Hex 110 Address
087
083
081
082
08B
089
08A
08F

These registers must be written to
select the correct page for each OMA
channel before any OMA operations are
performed. The other address locations
between 080 and 08F that are not
shown, are not used by the OMA
channels but can be read or written to
by the CPU. Address 08F is used to
drive a value onto the upper address
bits A 17-A23 of the CPU's address bus
during a refresh cycle.
ADDRESS GENERATION
The OMA addresses are setup such
that there is an upper address portion,
used to select a specific page, a middle
address portion, used to select a block
within the page, and a lower address
portion.
The upper address portion is generated
by the page registers, in the 74LS612
equivalent megaeell. The page
registers for each channel must be
setup by the CPU before a OMA
operation. OMA addresses do not
increment or decrement across page
boundaries. Page sizes are 64 kilobytes for 8 bit channels (channels 0
through 3) and 128 kilobytes for 16 bit
channels (channels 5, 6, and 7). The

•

VLSI TECHNOLOGY, INC.
VL82C100

TABLE 3. ADDRESS SOURCE GENERATION
Outputs from 74LS612 Page Registers

OMA page register values are output on
A 17-A23 and XA 16 for 8 bit channels,
and A 17-A23 for 16 bit channels.

Outputs from Middle Address Latches
Address Outputs from 8237

The middle address portion, used to
select a block within the page, is
generated by the 8237 megacells at the
beginning of a OMA operation and any
time the OMA address increments or
decrements through a block boundary.
Block sizes are 256 bytes for 8 bit
channels (channels 0 through 3) and
512 bytes for 16 bit channels (channels
5, 6, and 7). This middle address
portion is output by the 8237 megacells
onto the data bus during state S1. The
internal middle address bit latches will
latch in this value. The middle address
bit latches are output on XA8-XA15 for
8 bit channels, and XA9-XA 16 for 16 bit
channels.

8 Bit OMA Address Bits
16 Bit OMA Address Bits
M7

A23

A22

A21

A20

A19

A18

A17

XA16
07

XA15

The lower address portion is generated
directly by the 8237 megacells during
OMA operations. The lower address
bits are output on XAO-XA7 for 8 bit
channels, and XA1-XA8 for 16 bit channels. XAO is forced low during 16 bit
OMA operations.

XA16

XA14 . XA15

XA13

XA12

XA13

XA11

XA12

XA10

XA11

XA9

XA10

XA8

XA9

XA7

XA8

XA6

XA7

XA14

XA5

XA6

XA4

XA5

XA3

XA4

XA2

XA3

XA1

XA2

XAO

XA1

VSS

---

XAO

Table 3 is shown to illustrate the source
for all address bits during both 8 and 16
bit transfers.
READY CONTROL
The ready input to each of the 8237
megacells is driven from the same
source within the ready control logic.
To maintain an AT-compatible design,
the VL82C100 ready control logic forces
one wait state on every OMA transfer.
The external signal IOCHROY goes into
the ready control logic to extend
transfer cycles to longer than one wait
state if needed. To add extra wait
states, an external device should pull
lOCH ROY low within the setup time
before the second phase of the internal
OMA clock during the forced wait state.
The current OMA cycle will then be
extended by inserting wait states until
lOCH ROY is returned high. lOCH ROY
going high must meet the setup time
before the second phase of a wait state
cycle or an extra wait state will be
inserted before the OMA controller
transitions to state S4 (see timing
diagrams).

4-10

•

VLSI TECHNOLOGY, INC.
VL82C100

XMEMRDELAY
To maintain an AT-compatible design,
the VL82C100 inserts a DMA clock
cycle delay in the falling edge of the
-XMEMR signal. -XMEMR will go low
one DMA clock (two SYSCLK's) later
than the -MEMR signal coming out of
the 8237 megacell. The rising edge is
not altered and will go high at the same
time the -MEMR signal from the
megacell goes high.

DMA controller's HLDA input. When
one of the VL82C1 OO's seven channels
is programmed in cascade mode and
that channel is acknowledged the
VL82C100 will not drive the data bus,
the command signals, or the XA
address bus. However, the upper
address bits A17-A23 will be driven with
the value programmed into the page
register for the channel programmed in
cascade mode.

buses while the cascaded channels
-DACK signal is active. Also, the
VL82C100 will force the upper address
bits A 17-A23 to a high impedance state
while -MASTER is held low.

EXTERNAL CASCADING
An external DMA controller or bus
master can be attached to an ATcompatible design through the
VL82C100's DMA controllers. To add
an external DMA controller, one of the
seven available DMA channels must be
programmed in cascade mode. That
channel's DRO signal should then be
connected to the external DMA
controller'S HRO output. The corresponding -DACK signal for that channel
should be connected to the external

An external device can become a bus
master and control the system address,
data, and command buses in much the
same manner. One of the DMA channels must be programmed in cascade
mode. The external device then asserts
the ORO line for that channel. When
that channel's -DACK line goes active,
the external device can then pull the
-MASTER signal low to force the
system buses to a high impedance
state. As in the DMA controller cascading, the VL82C1 00 will not drive the X

INTERRUPT CONTROLLER
SUBSECTION
The interrupt controller subsection is
made up of two 8259 megacells with
eight interrupt request lines each for a
total of 16 interrupts. The two megacells are cascaded internally on the
VL82Cl00 and one of the interrupt
request inputs is internally connected to
an output of the 8254 counterltimer
megacell. This allows a total of 14
external interrupt requests.
A typical interrupt sequence would be
as follows. Any unmasked interrupt will
generate the INTR signal to the CPU.
The interrupt controller megacells will
then respond to the -INTA pulses from
the CPU. On the first -INTA cycle the

FIGURE 2. INTERRUPT CONTROLLER SUBSECTION

8259

...
...

-XIOR
XAO

IR02
SP/EN

~VDD

-AD
-WR

...

-XIOW

INT

INTERRUPT
CONTROLLER 1

..... XDO-XD7 . .

IR03-IR07,
IROI

XDO-XD7

.....

8259
INT

-INTA

.....
.
..:
...

IR08-IR015

CASO ' - - CASI
r-CAS2 ,.-

-AD

SP/EN

-WR
AO

INTERRUPT
CONTROLLER 2

XDO-XD7 . .

-INTA

4-11

CASO I CAS1
ICAS2 I -

.1VSS

INTR

VLSI TECHNOLOGY, INC.
VL82C100
TABLE 4. WRITE OPERATIONS
HaxAddrass
Register Function

XD4

XD3

020

OAO

Write ICW1

021

OA1

WritelCW2

021

OA1

WritelCW3

021

OA1

Write ICW4 (If Needed)

INT1

INT2

Before nonnal operation can begin,
each 8259 megacell must follow an ini·
tialization sequence. The sequence is
started by writing Initialization Com·
mand Word 1 (ICW1). After ICW1 has
been written the 8259 megace/I expects
the next writes to follow in the sequence
ICW2, ICW3, and ICW4 if it is needed.
The Operation Control Words (OCW)
can be written at any time after initiali·
zation.

021

OA1

WriteOCW1

020

OAO

WriteOCW2

020

OAO

WriteOCW3

In the standard 8259 megacell ICW3 is
optional. But since the two 8259's in
this chip are cascaded together, they
should always be programmed in
cascade mode and ICW3 will always be
needed. Refer to the 8259 data sheet
for more information on programming
the 8259 megacell.

TABLES. READ OPERATIONS
Hex Address
Register Function

INT1

1NT2

020

OAO

Interrupt Request Reg., In·Service Reg., or Poll Command

021

OA1

Interrupt Mask Register
should never be programmed to
operate in the buffered mode.

cascading priority is resOlved to deter·
mine which of the two 8259 megacells
will output the interrupt vector onto the
data bus. On the second -INTA cycle
the appropriate 8259 megacell will drive
the data bus with the correct interrupt
vector for the highest priority interrupt.

INTERRUPT CONTROLLER
INTERNAL REGISTERS
The internal registers of the 8259
megacells are written to in the same
way as In the standard part. Table 4
shows the correct addrassing for each
of the 8259 registers.

Because the two megacells are cas·
caded internally on the VL82C100, they

When reading at address 020 or OAO
hex, the register read will depend on
how Operation Control Word 3 was
setup prior to the read.
nMEWCOUNTERSUBSECTION
The timer subsection consists of one
8254 counterllimer megacell configured
as shown in the diagram. The clocks
for each of the three internal counters
are tied to the single input pin MHZ119.
The gate inputs of Counters 0 and 1 are
tied high to enable those Counters at all
times. The gate input of Counter 2 is
tied to the output of a flip·fiop inside the

FIGURE 3. nMEWCOUNTER SUBSECTION
VDD
MHZ119

XDO

-PORTBWR
-XIOW
-XIOR
XDO·XD7
XAO·XA1

.....
....

D
,.. C

- a-

..
....
....

.....

8254
CLKO
GATO

OUTO

---.

CLK1
GAT1

OUT1

CLK2
GAT2

OUT2

---.

-WR
-AD

........
4-12

COUNTER
TIMER

TO INTERRUPT
CONTROLLER
TO HOLD
ARBITER
OUT2

•

VLSI TECHNOLOGY, INC.
VL82C100

TABLE 6. TIMER/COUNTER REGISTERS
Hex Address

-XIOR

-XIOW
0

040

Read Latched Count or Status from Counter ="

Note.: 1. The OMA channel used for requesting control of the bus by a new bus master must be programmed in cascade
mode. The new master should not pull -MASTER low until it has received the corresponding -OACK signal.

2. The timing shown is assuming one of the 16 bit OMA channels is used. There will be extra cycles between ORO and
CPUHRO before and after the request cycle when using an 8 bit OMA channel. These extra cycles are caused by
the cascade delay from the slave 8237 through the master 8237.

-REFRESH llMING WAVEFORM

SYSCLK

CPUHRa

CPUHLOA

-REFRESH

IOCHROY

A17-A23

Note.: 1. A refresh pulse is normally three SYSCLK cycles long (with no wait states). Refresh pulses will be four SYSCLK
cycles if a hold request is pending from the OMA controllers.
2. -REFRESH cycles can be extended by inserting wait states using lOCH ROY.

4-22

•

VLSI TECHNOLOGY, INC.
VL82C100

AC TESTING -INPUT, OUTPUT WAVEFORM
INPUT

3.5V

0.2 V

001PUT~

----r~~*_1.5V
~

AC TEST

POINTS:--~~

AC testing inputs are driven at 3.5 V for a logic 1 and 0.2 V for a logic o. Clock inputs SYSCLK and MHZ119 are driven at
4.3 V and 0.2 V. Timing measurements are made at 1.5 V for both a logic 1 and o.
AC TESTING - LOAD CIRCUIT

+5.0 V

. - DEVICE UNDER TEST

CL"

"Includes scope and jig capacitance.

AC TESTING - LOAD VALUES
Test Pin

CL(pF)

-REFRESH

100

All -DACKs, TIC

100

All Other I/O and Output Pins

R 1 (0)
1K

4-23

•

VLSI TECHNOLOGY, INC.
VL82C100

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

OC~0·Cto+70·C

01 - -40·C to +85·C
Storage Temperature -65·C to + 150·C
Supply Voltage to
Ground Potential

-0.5 V to +7.0 V

Applied Input
Voltage

-0.5 V to +7.0 V

Power Dissipation

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those
indicated

500mW

DC CHARACTERISTICS:

=QC: o·c to +70·C, at: -400C to +85·C, VDD =5 V ±5%, VSS = 0 V

Symbol

Parameter

Min

VOH

Output High Voltage

2.4

VOL1

Output Low Voltage

VOL2

Output Low Voltage

VIH

Input High Voltage

Max

2.0

VIL

Input Low Voltage

-0.5

VIHC

Input High Voltage

3.8
-0.5

Unit

10H ~ -400 !LA

0.45

IOL = 20 mA, -REFRESH

0.45

IOL = 2 mA, All Other Pins

VDD+0.5
0.8
VDD+0.5

TTL

RESET, SYSCLK, MHZl19
RESET, SYSCLK, MHZl19

VILC

Input Low Voltage

0.6

Output Capacitance

Input Capacitance

CIO

Input/Output Capacitance

ILOL

Three-state Leakage Current

Input Leakage Current

III

Input Leakage Current

ICC

Power Supply Current

CondHlon

Note:

in this data sheet is not implied. Exposure to absolute maximum rating
conditions for extended periods may
affect device reliability.

100

!LA

-0.5

VIN = 0.45 V, All IRO & DRO Inputs

!LA

All Other Inputs

Note

-100

-10

VIN - VDD or GND, VDD = 5.25 V, outputs unloaded.

4-24

•

VLSI TECHNOLOGY, INC.
VL82C1018
PC/AT·COMPATIBLE SYSTEM CONTROLLER

FEATURES

DESCRIPTION

Fully compatible with IBM PC/AT-type
designs

The VL82C101B PC/AT-Compatible
System Controller replaces an 82C284
Clock Controller and 82C288 Bus
Controller (both are used in '286-based
systems), an 82C84A Clock Generator
and Driver, two PAl16L8 devices (used
for memory decode), and approximately
31 other less complex integrated
circuits used as Wait State logic. When
used in 12 MHz systems utilizing 80 ns
DRAMs, the device provides the
required one wait state for a "write"
operation, and zero wait states for a
"read" operation. A 12 MHz system
using 120 ns DRAMs will be provided
with one wait state for ·write" and one

• Replaces 36 integrated circuits on the
PC/AT-type board
• Supports up to 12 MHz system clock
• Device is available as "cores" for
user-specific designs
• Sink 20 mA on slot driver outputs
• Designed in CMOS for low power
consumption

BLOCK DIAGRAM
POWERGOOD}
RC
XTAL1(1)
XTAL1(2)
XTAL2(1)
XTAL2(2)

-SO} -

RESCPU
RESET
-READY
PROCCLK
SYSCLK
PCLK
-PCLK
OSC
MHZ119
-ENAS

8284
82284
CLOCK
GENERATION
AND READY
CONTROL

READY

DT/-R

-S1

BUS
CONTROL

82268

AO-A1

BUS
CONTROL

MI_IO}
CPUHLDA
FASTMODE
-ERROR
-BUSY287

{

BUS
~MMANDS

{

-LMEGCS
ARDYEN

RO~~}
RAMWTST
-ROMCS
-REFRESH }
IOCHRDY

-IOCS16
F16}
. -MEMCS18
-MASTER
-AEN2
-AEN1

XAO,XA3,
XA5-XA9

WAIT
STATE
LOGIC

-lOR
-lOW
-MEMR
-MEMW
-1NTA

{ ~:=

BUFFER

-XMEMW

-XIOR
-XIOW
Q1

-MEMR
REFRESH
CONTROL

I
I

-REFEN

•

{

DATA
CONVERSION

-DENLO
-DENHI
ALE
RAS
-BUSY268
RAMALE
ENDRAS

DMA
CONTROL

DIR245
GATE245
CNTLOFF

SAO

-DMAAEN

287 AND
PERIPHERAL
CONTROL

4-25

{

RESET287
-NPCS
-PPICS
XDATADIR

wait state for "read". The device
accepts both the 24 MHz crystal to
control the system clock as well as the
_14.318 MHz crystal to control the video
clock. It also supplies reset and clock
signals to the 110 slots.
The device is manufactured with VLSl's
advanced high-performance CMOS
process and is available in a JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
VL82C101 B is part of the PC/ATcompatible chip sets available from
VLSI. Please refer to the Selector
Guide in the front of this manual.

ORDER INFORMATION
Part
Number
VL82C101B-QC

Package
Plastic Leaded Chip
Carrier (PLCC)

Note: Operating temperature is
O·C to +70·C.

•

VLSI TECHNOLOGY, INC.
VL82C1018

PIN DIAGRAM
A1

-I?~S

MI-IO
RC

-S1

l-SO

CHRDY

XTAL
1(2)

XTAL
2(2)

VDD

XAO

;~D~ 1 ~1~L 1 VSS 1~~L Ipg~~1
5

-WSO
-ROMCS

XA5

XA7

XA31 XA6 1 XA8

1 84 83 82 81 80 79 78 77 76 75

•

XA9

-AEN1

-AEN2

-REFRESH

FASTMODE

-lMEGCS

ROMWTST

-MEMCS16

-MASTER

-BUSY287

-ERROR

OSC

ENDRAS

-READY

F16

VL82C1018

RAMWTST

TOP VIEW

MHZ119
-XBHE

RAMALE

-NPCS

-PPICS

RESET287

XDATADIR

-DENHI

CNTLOFF

-DENLO

GATE245

VSS

DT/-R

DIR245

ALE

RAS

-REFEN

-oMAAEN

-ENAS

VDD

M~~D~~~~~~"~~Q~~W~~~

RES I-XMEMI
-X I-MEM
RE I CLK
SYS I SAO l-SMEMI
PCLK
CPU
R
lOR
W I - lOW I-BUSY
286 I SET
R
-XMEM
W

-X
lOW

VSS

-MEM
R

-lOR

-INTA

4-26

PROC
CLK

VSS -SMEM
W

-PCLK

•

VLSI TECHNOLOGY, INC.
VL82C101B

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Type

Signal
Description

XTAL1(2)

Crystal 1 Output 2 - A parallel resonant fundamental mode crystal should
be attached across XTAL 1 (1) and XTAL1 (2). This is the crystal output.

XTAL1(l)

Crystal 1 Input 1 - A parallel resonant fundamental mode crystal should be
attached across XTAL1(1) and XTAl1 (2). This input drives the internal
oscillator and determines the frequency of OSC.

lOCH ROY

110 Channel Ready - This input is generated by an 110 device. When low, it
indicates a not ready condition. This is used to extend memory or I/O
accesses by inserting wait states. When high, this signal allows normal
completion of a memory or 110 access by an I/O device.

CPUHlOA

CPU Hold Acknowledge - This input indicates ownership of the local CPU
bus. When high, this signal indicates that the CPU has three-stated its bus
drivers in response to a hold request. When low, it indicates that the CPU
bus drivers are active.

-Sl

Status 1 - An active low inputlpull-up from the CPU in combination with -SO
and M/-IO determine which type of bus cycle to initiate. -S1 going active
indicates a read cycle unless -SO also goes active. Both status inputs
active indicate an interrupt acknowledge cycle or halt/shutdown operation.

-SO

Status 0 - An active low input/pull-up from the CPU in combination with -Sl
and M/-IO determine which type of bus cycle to initiate. -SO going active
indicates a write cycle unless -S1 also goes active. Both status inputs
active indicate an interrupt acknowledge cycle or a halt/shutdown operation.

M/-IO

Memory or 110 Select - This input indicates the type of bus cycle to be
performed. If high. a memory cycle or halVshutdown cycle is started. If
low. then an I/O cycle or an interrupt acknowledge cycle will be initiated.

This active low input signal will force a CPU reset when active. It is
generated by the keyboard controller.

CPU Address Bus Bit 1 - This input is used to determine when to initiate a
shutdown operation. A shutdown will be started when A1 is low. M/-IO is
high. and both -SO and -S1 go low.

-IOCS16

110 Chip Select 16 - This active low input is generated by an I/O device for
a 16-bit data bus access.

-WSO

Wait State 0 - This active low input signal should have an external pull-up.
A peripheral device can pull this signal low to force a zero wait state cycle.

-ROMCS

ROM Chip Select - This active low input is a signal generated from
-LCSOROM and -lCS1 ROM and is used to indicate a ROM memory
access.

F16

This input indicates a word memory access. It is used to inhibit command
delays during a 16 bit memory access.

CPU Address Bus Bit 0 - This input is used to generate enable signals for
the data bus transceivers.

FASTMOOE

This active high input enables the generation of an early ALE signal. called
RAMALE. from the edge of -MEMR or -MEMW. If FASTMOOE is desired.
this pin must be held low until after the first memory read cycle. RAMALE
is equal to ALE when FASTMOOE is inactive.

4-27

•

VLSI TECHNOLOGY, INC.
VL82C101B

SIGNAL DESCRIPTIONS (Cont.)
Signal
Nama

Pin
Number

ROMWTST

ROM Wait State - This input is used to select the desired number of ROM
access wait states. ROMWTST m 0 indicates two waits while RAMWTST =
1 indicates one wait state. If two wait state mode is required, this pin must
be set high when CPUHLOA (pin 5) is high.

RAMWTST

RAM Wait State - This input is used to select the desired number of RAM
access wait states. RAMWTST - 0 indicates zero waits while RAMWTST
- 1 indicates one wait state.

-BUSY287

Busy 287 - A busy status input that is asserted by the 80287 to indicate
that it is currently executing a command.

OSC

This is the buffered output of XTAL1 oscillator.

MHZ119

This output is the OSC output clock divided by 12. It is used by the
Peripheral Controller device for the timer controller.

-XBHE

110

Transfer Byte High Enable - This active low 110 is used to allow the upper
data byte of be passed through the data bus transceivers.

-NPCS

Numerical Processor Chip Select - This active low output is the chip select
for the 80287 numerical processor.

RESET287

Reset 287 - This active high output is used to reset the 80287 numerical
processor.

-OENHI

Oata Bus Enable High - This active low output is used to enable the data
bus transceiver on the high byte of the data bus.

-OENLO

Oata Bus Enable Low - This active low output is used to enable the data
bus latch byte accesses.

OTI-R

Data TransmitlReceive - An output that determines the data direction to
and from the local data bus. A high indicates a write bus cycle and a low
indicates a read bus cycle. OTI-R is high when no bus cycle is active.
-OENLO and -OENHI are always inactive when OT/-R changes state.

ALE

Address Latch Enable - A positive edge output that controls the address
latches which hold the address during a bus cycle. ALE is not issued for a
halt bus cycle.

RAS

This output will go active anytime a memory read or memory write command is iSSUed.

-OMAAEN

OMA Address Enable - An active low output that is active whenever an 1/0
device is making a OMA access to the system memory.

RESCPU

Reset CPU - This is the active high output system reset for the CPU. It is
generated from POWERGOOO, RC or when a shut down status is generated by the CPU.

-XMEMW

Peripheral Bus Memory Write - An active low 110 that is the memory write
command to and from the peripheral bus. This pin is configured as an
output when -OMMEN is high and an input when -OMAAEN is low.

-XMEMR

Peripheral Bus Memory Read - An active low I/O that is the memory read
command to and from the peripheral bus. This pin is configured as an
output when -OMMEN is high and an input when -OMAAEN is low.

-XIOW

110

Peripheral Bus InputlOutput Write - This active low I/O is the read command to and from t!'le peripheral bus. This pin is configured as an output
when -OMMEN is high and an input when -OMAAEN is low.

Signal·
Typa

Signal
Description

4-28

•

VLSI TECHNOLOGY, INC
VL82C1018

SIGNAL DESCRIPTIONS (Cont.)
SIgnal
Nama

PIn
Number

Signal
Type

Signal
DescrIption

-x lOR

110

Peripheral Bus InputJOutput Read - This active low I/O is the read command to and from the peripheral bus. This pin is configured as an output
when -OMMEN is high and an input when -DMMEN is low.

-MEMW

110

Memory Write - This active low 110 is the memory write command from the
bus controller portion of the chip. It will be three-stated when CPUHLDA is
asserted and CNTLOFF is inactive.

-MEMR

110

Memory Read - This active low 110 is the memory read command from the
bus controller portion of the chip. It will be three·stated when CPUHLDA is
asserted and CNTLOFF is inactive. -MEMR is also active during a refresh
cycte.

-lOW

110

InputlOutput Write - This is the active low 110 write command from the bus
controller portion of the chip. It will be three-stated when CPUHLDA is
asserted and CNTLOFF is inactive.

-lOR

110

Input/Output Read - This is the active low I/O read command from the bus
controller portion of the chip. It will be three-stated when CPUHLDA is
asserted and CNTLOFF is inactive.

-BUSY286

Processor 286 Extension Busy - This output goes to the -BUSY input of
the 80286. If pulled low, this signal stops the 80286 program execution on
all WAIT and some ESC instructions until it returns inactive (high).

-INTA

Interrupt Acknowledge - This active low output that is three-stated, is the
interrupt acknowledge command from the bus controller portion of the chip.
It will be three-stated when CPUHLDA is asserted and CNTLOFF is
inactive.

RESET

Reset - This active high output signal is the system reset generated from a
POWERGOOD. It is synchronized to PROCCLK.

PROCCLK

Processor Clock - This output is the processor clock for the CPU and
coprocessor. It is equal to the crystal frequency on crystal oscillator input

SYSCLK

System Clock - This output is the main system clock. It is equal to half the
PROCCLK frequency and is synchronized to the processor's T-states.

XTAL2.

SAO

System Address Bus Bit 0 - A three-stated output.

-SMEMW

Memory Write - An active low three-stated output that is the memory write
command to the expansion bus. Drives when -LMEGCS is low.

-SMEMR

Memory Read - An active low three-stated output that is the memory read
command to the expansion bus.

-PCLK

Peripheral Clock Complement Phase - This output is the complement
phase of the peripheral clock. It is equal to half the PROCCLK frequency
and is used for clocking peripheral devices.

PCLK

Peripheral Clock True Phase - This output is the true phase of the periph·
eral clock. It is equal to half the PROCCLK frequency and is used for
clocking peripheral devices.

-ENAS

Enable Address Strobe - This active low output is used to enable the
address strobe on the real time clock. It will go low the first time -SO is
asserted after a system reset.

-REFEN

Refresh Enable - An active low output. It will be asserted when a refresh
cycle is needed for the DRAMs. It is used to clock a refresh counter which
provides addresses during the refresh cycle.
4-29

•

VLSI TECHNOLOGY, INC.
VL82C1018

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

This active high output will go active during the second phase of a CPU
bus cycle following the T-state. It is used by other devices to generate the
address strobe for the real time clock.

DIR245

Direction 245 - This output determines the direction of the data bus
transceiver which does conversions from high to low byte or low to high
byte for 8-bit peripherals.

GATE245

Gate 245 - This output enables the data bus transceiver which does
conversions from high to low byte or low to high byte for 8-bit peripherals.

CNTLOFF

Control Off ~ This output is used to enable the lower byte data bus latch
during byte accesses.

XDATADIR

Transfer Data Direction - This output controls the direction of data flow
through the transceiver between the X data bus and the lower byte of the S
data bus. A high indicates data flow from the S bus to the X bus. A low
indicates data flow from the X bus to the S bus.

-PPICS

Programmable Peripheral Interface Chip Select - This active low output is
used to generate the chip select for the keyboard controller.

RAMALE

RAM Address Latch Enable - This output is used in the FASTMODE of
operation. When FASTMODE is inactive RAMALE is equal to ALE.

-READY

Ready - When active, indicates that the current bus cycle is to be completed. -READY is an open drain output requiring an external pull-up
resistor.

ENDRAS

An output that is used to complete a memory readlwrite cycle.

-ERROR

Error - An error status input from the 80287. This reflects the ES bit of the
80287 status word and indicates that an unmashed error condition exists.

-MASTER

Master - This active low input is asserted low by devices on the expansion
bus. A low indicates that another device is active.

-MEMCS16

Memory Chip Select 16 - A low on this pin indicates that the off-board
memory is 16-bits wide.

-lMEGCS

Lower Megabyte Chip Select - This input indicates that the lower memory
address space (0-1 megabyte) is selected. When low, it enables the threestate drivers on -8MEMR and -8MEMW.

-REFRESH

Refresh - This active low input is used to initiate a refresh cycle for the
dynamic RAMs.

-AEN2

Address Enable 2 - This active low input is from the DMA controllers and is
used to enable the address latches for 16 bit data transfers.

-AEN1

Address Enable 1- This active low input is from the DMA controllers and is
used to enable the address latches for 8 bit data transfers.

XA5-XA9

78-74

Peripheral Address Bus Bits 5-9 - These inputs are used to decode chip
select and reset signals for the coprocessor.

XA3

Peripheral Address Bus Bit 3 - This input is used in control of the
coprocessor reset and chip select signals.

XAO

Peripheral Address bus bit 0 - This input is used in control of the coprocessor and 8/16-bit data conversions.

POWERGOOD

System Power-on Reset - This input signal indicates that power to the
board is stable. A Schmitt-trigger input is used so the input can be
connected directly to an RC network.
4-30

•

VLSI TECHNOLOGY, INC.
VL82C1018

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

XTAL2(1)

XTAL2(2)

VDD

32,54,82

System Power: 5 V

VSS

1,27,38,
48,59

System Ground

Crystal 2 Input 1- A parallel resonant fundamental mode crystal should be
attached across XTAL2(1) and XTAL2(2). This input drives the internal
oscillator and determines the frequency for PROCCLK.

Crystal 2 Output 2 • A parallel resonant fundamental mode crystal should
be attached across XlAL2(1 ) and XTAL2(2). This is the crystal output.

FUNCTIONAL DESCRIPTION
The VL82C1 01 B chip generates all the
major clocks for an AT-compatible
system design along with the command
and control signals for both the system
and peripheral buses. It interfaces with
the CPU to determine the type of bus
cycle to execute and generates the
-READY signal to indicate that the
current bus cycle can be terminated. It
also contains logic to make conversions
between 16 bit and 8 bit data accesses.
Finally, it generates some of 1he control
signals necessary for the 80287
Numerical Processor.
CLOCKGENERATlON
The VL82C1 01 B contains two oscilla·
tors to generate the clocks for an ATcompatible design. Both oscillators are
designed to use an external, parallel
resonant fundamental mode crystal.
The first oscillator is used to generate
the video clock output (OSC) and
MHZ119 which is the clock for the 8254
timer in the Peripheral Controller
device. A 14.318 MHz crystal should
be used on this oscillator to maintain
compatibility. The OSC output is
generated directly from this oscillator for
the system bus and the MHZ119 output
is derived from the OSC output divided
by 12. To guarantee sufficient drive
and a clean signal on the slots it is
recommended that the OSC output be
buffered before driving the expansion
CQIlneC!ors.
The second oscillator is used to
generate the system clocks. The
crystal frequency for this oscillator
should be twice the operating frequency
of the CPU. For a 12 MHz system, a 24
MHz oscillator should be used. This

FIGURE 1 OSCILLATOR CIRCUIT
XTAL2(1)

20124 MHz

_L-

300FT

,.....
11
-'-

5-50
pFVAR

XTAL2(2)

10pF

T
XTAL1(1)

14.318 MHz

oscillator is used to generate four clock
outputs. PROCCLK is generated
directly from the oscillator and will have
the same frequency as the crystal input.
This output is connected directly to the
CPU and Numerical Processors clock
inputs. PCLK and -PCLK are used to
clock the keyboard controller. These
outputs are free running clock signals
with a frequency of haH the PROCCLK
frequency. The last clock output is
SYSCLK. This clock is also at half the
PROCCLK frequency, but it will be held
low during RESET and will not begin
running until the first bus cycle is
initiated by the CPU. It will then make
its first low to high transition on the
falling edge of PROCCLK during the

4-31

XTAL1(2)

start of the first TC cycle (see timing
waveforms). This synchronization is
done to ensure that the system clock is
synchronized with the 80286 internal
system clock. The SYSCLK output is
used to drive the Peripheral Controller
device directly and should be buffered
externally before driving the expansion
connectors to guarantee sufficient drive
and a clean signal on the slots.
RESET AND READY CONTROL
The 82284 megacell along with some
support logic is used to control the
system reset signals and -READY
signal for the CPU. Two basic reset
signals are generated for the system.
RESET is the system reset out of the
82284 megacell and is synchronized to

•

VLSI TECHNOLOGY, INC.
VL82C101B

PROCCLK. It is generated from the
POWERGOOD input signal. RESCPU,
the other reset output, is connected to
the input on the 80286 processor.
RESCPU will be active anytime RESET
is active. It can also be generated from
two other possible sources. The first is
the RC input from the keyboard
controller. RESCPU will go active
within 4 to 18 PROCCLK cycles after.
RC is asserted and will go inactive 16
PROCCLK cycles later or 16
PROCCLK cycles after RC is negated.
RESCPU will also be generated if a
shutdown command cycle is decoded
from the CPU. As with the RC input,
RESPCU will go active within 4 to 18
PROCCLK cycles of detecting the
shutdown command and will be
negated 16 PROCCLK cycles later.
The POWERGOOD pin has a Schmitttrigger input so that an RC network can
be used to generate the reset signals.
The -READY output is synchronized
and controlled by the 82284 megacell.
-READY is an open drain output
connected directly to the CPU and
requires an external pull-up resistor. A
resistor value of 700 n is recommended for 10 or 12 MHz operation.
Bus cycle length is controlled by the
-READY output. Bus cycles are
lengthened and shortened intemally by
the VL82C1 01 B depending on the type
of bus cycle being executed. The
length of a bus cycle can be shortened
externally by pulling the -WSO input
low or lengthened by pulling the
IOCHRDY input low. If IOCHRDY is
pulled low the bus cycle will not be
terminated untillOCHRDY is returned
high.
COMMAND AND BUS CONTROL
The VL82C1 01 B contains an 82288
bus controller megacell to generate all
the bus command and control signals.
The 82288 megacell generates the
-MEMR, -MEMW, -lOR and -lOW
command signals and the DT/-R
control signal. The DEN output from
the megacell is split into -DENLO and
-DENHI for enables on the upper and
lower bytes of the data bus. Internal
circuitry is used to insert one
PROCCLK cycle of command delay for
all VO cycles and off-board 8 bit
memory cycles. Refer to the 82288

data sheet for complete operation of
the 82288 megacell.
OPERAT1NG MODES
The VL82C1 01 B operates in four basic
modes. First, and most common, is the
CPU mode. This mode is active any
time the input CPUHLDA is low. While
in CPU mode the VL82C1 01 B will drive
both the CMD (-MEMR, -MEMW,
-lOR, -lOW) bus and XCMD
(-XMEMR, -XMEMW, -XIOR, -XIOW)
bus.
The other modes can only be active
when CPUHLDA is high. Then the
VL82C101B can be in DMA mode,
-MASTER mode, or -REFRESH
mode. If the inputs -AEN1 or -AEN2
are active, the VL82C101B is in DMA
mode and the CMD bus is driven from
the inputs on the XCMD bus. If the
-MASTER input is active, the
VL82C1 01 B is in -MASTER mode and
the XCMD bus is driven from the inputs
on the CMD bus. When the
-REFRESH mode is active the -MEMR
output will be driven to generate the
refresh for the DRAMs but -MEMW,
-lOR and -lOW will be in a high impedance state. The XCMD pins will be
configured as outputs driving whatever
value is on the CMD pins.
SYSTEM BOARD MEMORY
CONTROL
Memory control on the system board is
accomplished with three signals,
RAMALE, RAS, and ENDRAS.
The system board memory controls can
operate in two different modes. While
in CPU mode with the FASTMODE
input set low or in non-CPU mode,
RAMALE will look the same as ALE
and RAS will be generated from
-MEMR and -MEMW. In this mode
the memory timing wililoak the same
as an AT-compatible design. If the
FASTMODE input is set high, the
RAMALE and RAS signals are
changed during CPU mode accesses
to allow for more DRAM access time.
RAMALE is used by both the Memory
Controller and Address Buffer devices
to latch in current address values to
generate both address and enable
signals for the DRAMs. In FASTMODE
the RAMALE signal is changed so that

4-32

it will only go low when a memory read
or write command is active. This
guarantees that the memory address
and chip select signals will remain valid
during the entire memory cycle and
allows RAMALE to return high as soon
as possible to transmit through the new
address for the next cycle.
The RAS output is changed in
FASTMODE so that it will go active one
PROCCLK cycle sooner during a
memory read cycle to allow more read
access time. The RAS output will look
the same as non-FASTMODE timing for
write cycles. This was done to allow for
zero wait state cycles on memory
reads. RAS could not be moved up on
memory writes because the data from
the CPU would not be valid in time to
be written into the DRAMs.
ENDRAS is used to terminate the RAS
signals to the DRAMs withoutterminating the memory access. This allows for
the required RAS precharge time before
the next memory access. It will
normally be high and make a high to
low transition to terminate the RAS
signals to the DRAMs on the third
PROCCLK after RAS goes active.
ENDRAS will then remain low until RAS
returns low, which will cause ENDRAS
to return high. The exception to this
timing is for a zero wait state RAM read.
In this case, ENDRAS will make the
high to low transition two PROCCLK
cycles after RAS instead of three.
WAIT STATE LOGIC
Wait states can be controlled from a
number of different sources within the
VL82C101 B. It is intemally programmed to generate the wait states
shown in Table 1 based on the appropriate input signals.
Any of these programmed values can
be overridden by the inputs IOCHRDY
and -WSO. IOCHRDY can be used to
extend any bus cycle. When IOCHRDY
is pulled low the current bus cycle will
be maintained until it is returned high.
A low on -WSO will terminate the
current bus cycle as soon as it is
recognized by the VL82Cl 01 B. These
inputs need only be pulled low to modify
the values shown in Table 1.
IOCHRDY and -WSO are mutually
exclusive and only one of them should

•

VLSI TECHNOLOGY, INC.
VL82C1018

be pulled low within a given bus cycle.
Refer to the timing diagrams for setup
and hold requirements.
REFRESH CONTROL
The VL82C1 01 B contains circuitry to
control a refresh cycle in an AT-compatible design. When the input
-REFRESH is pulled low the
VL82C1 01 B will issue -REFEN to clock
the refresh counter and enable the
refresh addresses onto the memory
address bus. It will also issue a
-MEMR command. For correct operation -REFRESH should not be pulled
low unless CPUHLDA is active.
DATA CONVERSION
A state machine for controlling the
conversion between 16 bit data accesses from the CPU and 8 bit peripherals is contained in the VL82C1 01 B.
This state machine will generate the

control signals DIR245, GATE245, and
CNTLOFF to the Data Buffer chip to
route the data correctly for both read
and write conversions. The conversion
logic will signal the wait state logic to
hold the CPU and start the read/write of
the low data byte. It will then latch the
low byte for a read operation, negate
the bus control signals, switch SAO to a
high, and then perform the readlWrite
operation for the high data byte. The
VL82C1 01 B also uses the DIR245 and
GATE245 during 8-bit DMA cycles to
route the lowe'r byte on the system data
bus to or from the high or low byte of
on-board memory.
NUMERICAL PROCESSOR AND
PERIPHERAL CONTROL
The VL82C1 01 B generates a RESET
signal and chip select signal for the
80287 Numerical Processor. The signal

RESET287 is used to reset the 80287
and can be activated by a system reset
or an 110 write to address OF1 hex.
-NPCS is used as a chip select for the
80287 and is decoded at addresses
OF8-0FF hex.
The VL82C1 01 B also controls the
-BUSY286 signal sent to the 80286
from the Numerical Processor. The
80287 will assert -BUSY287 whenever
it is performing a task. This signal is
passed to the 80286 by asserting the
-BUSY286 output. Normally
-BUSY286 will follow -BUSY287.
However, if the -ERROR signal is
asserted while the ~USY287 signal is
active, the -BUSY286 output will be
latched low and will remain active until
cleared by an 110 write cycle to address
OFO hex or OF1 hex.

TABLE 1. WAIT STATES
Access Type

RAMWTST

ROMWTST

F16

INTACycles

8 Bit 110

-MEMCS16

-IOCS16

Number of Walts

16 Bit 110

Off-board 8-Bit Memory

Off-board 16-Bit Memory

On-board ROM Read

On-board RAM Write

On-board RAM Read

4-33

•

VLSI TECHNOLOGY, INC.
VL82C101B

AC CHARACTERISTICS: TA = DOC to +70°C, VDD =5 V ±5%, VSS = D V
PROCCLK MODE TIMING

Min

Max

Unit

250

239

237

PROCCLK Rise Time

1.0 V to 3.6 V, CL s 150 pF

PROCClK Fall Time

3.6 V to 1.0 V, Cl .. 150 pF

Symbol

Parameter

PROCCLK Period

PROCCLK High Time

PROCCLK Low Time

Condition
24 MHz Crystal Oscillator

PROCCLK TIMING WAVEFORMS

PROCClK

AC measurement characteristics from PROCCLK going low:
4.0 V
PROCCLK
(OUTPUl)

4.0V

3.6V

1.0V
---------'

0.45 V

The PROCClK (from '284 Megacell) is the main reference point for most of the AC signals. PROCClK has a guaranteed VOH of
4.0 V and a VOL of 0.45 V. However, all AC measurements referenced to PROCCLK going low are from the 1.0 V point. At 24
MHz the transition time from 3.6 V to 1.0 V (and 1.0 V to 3.6 V) is guaranteed to be 8 ns or less.

4-34

•

VLSI TECHNOLOGY, INC.
VL82C1018

CPU MODE llMING
Symbol

Parameter

tSU6

POWERGOOD to PROCCLK Setup Time

Min

Max

Note 1

tH7

POWERGOOD from PROCCLK Hold Time

Note 1

!D8

RESET from PROCCLK Delay

tD9

SYSCLK, PCLK, -PCLK from PROCCLK Delay

tD10

RESCPU from PROCCLK Delay

tSU11

M/-IO, A1 to -50, -51 Setup Time

t12

OSC RiselFall Time

113

MHZ119 Rise/Fall Time

tD14

MHZ119 from OSC Delay

tSU15

-50, -51 to PROCCLK Setup Time

tH16

-50, -51 from PROCCLK Hold Time

tD17

ALE Valid from PROCCLK Delay

tD18

DT/-R Low from PROCCLK Delay

tD19

DT/-R High from PROCCLK Delay

24
22

Unit

ns
ns

CL= 100 pF

CL=100pF

tD20

DTI-R High from -DENHI, -DENLO High Delay

!D21

-DENLO, -DENHI Active from PROCCLK Delay

tD22

-DENLO, -DENHI Inactive from PROCCLK Delay

tD23

-READY Active from PROCCLK Delay

!D24

-READY Inactive from PROCCLK Delay

CondHlon

20
3

ns
ns

tD25

-lOR, -XIOR Valid from PROCCLK Delay

!D26

-lOW, -XIOW Valid from PROCCLK Delay

!D27

XDATADIR Valid from PROCCLK Delay

tSU28

-IOCS16 PROCCLK Setup Time

tH29

-IOCS16 PROCCLK Hold Time

tSU30

IOCHRDY to PROCCLK Setup Time

tD31

-ENAS Valid from PROCCLK Delay

tD32

RAMALE Valid from PROCCLK Delay

Note 2

Notes: 1. POWERGOOD is an asynchronous input. This specification is given for testing purposes only, to assure recognition
at a specific PROCCLK edge.
2. -READY is an open drain output and requires a pull-up resistor that pulls the signal high within two PROCCLK
cycles. We recommend 700 n for the pull-up resistor for 10 MHz and 12 MHz systems.

4-35

•

VLSI TECHNOLOGY, INC.
VL82C101B

CPU MODE T1M1NG (Cont.)

Symbol

Parameter

tD33

RAS High from PROCCLK Delay

Min

Max

Unit

Note 3
FASTMODE -1. MEM
Read Only

tD34

RAS High from PROCCLK Delay

tD35

RAS Low from PROCCLK Delay

tD36

ENDRAS Low from PROCCLK Delay

tD37

ENDRAS High from PROCCLK Low Delay

ns
ns

tD38

ENDRAS High from RAS Low Delay

tD39

-MEMR. -XMEMR. -8MEMR Valid from
PROCCLK Delay

tD40

-MEMW. -XMEMW. -8MEMW Valid from
PROCCLK Delay

tSU41

-WSO to PROCCLK Setup Time

tH42

-WSO from PROCCLK Hold Time

tSU43

F16 to PROCCLK Setup Time

tH44

F16 from PROCCLK Hold Time

tSU45

-MEMCS16 to PROCCLK Setup Time

tH46

-MEMCS16 from PROCCLK Hold Time

tSU47

AO to PROCCLK Setup Time

tD48

SAO from PROCCLK Delay Time

ns
35

tSU49

-XBHE to PROCCLK Setup Time

tDoo

Q1 from PROCCLK Delay Time

tD51

CNTLOFF from PROCCLK Delay Time

tD52

DIR245 from PROCCLK Delay Time

tD53

GATE245 from PROCCLK Delay Time

tD54

-INTA Valid from PROCCLK Delay Time

Notes: 3.

FASTMODE - 1. MEM write only. FASTMODE - O. MEM read only.

DIR245 goes low for a write cycle. It will remain high for read cycles.

4-36

Condition

Note 4

•

VLSI TECHNOLOGY, INC.
VL82C101B

RESET AND CLOCK nMiNG WAVEFORMS

/ / \J\...JLrV / /

PROCClK
tH7-

~--~----;-~r-~-------//------------//;----

POWERGOOD
NOTE
RESET

~--+-~--~-------//------------//;----

A1, M/-IO

r--

VALID

tH16

tSU11

rr-------//~//;----

-51, -50

-ENAS
~--r-------//------------//;----

V/~/

SYSCLK

RESCPU

1010

~/~O

t09

//~~

PCLK

t09
-PCLK

//~/--F

OSC

MHZ119

Nota:

POWERGOOD is an asynchronous input. This specification is given for testing purposes only, to assure
recognition at a specific PROCClK edge.

4-37

•

VLSI TECHNOLOGY, INC.
VL82C101B

110 TIMING WAVEFORM

4TW
CYCLES
PROCCLK

-SO,-S1

'-+-~---//~-r--~-+------

ALE

~~+---//--~--+-~-----

~--r-~//--~--+-~J

DTI-R

-DENLO,
-DENHI

'-+--I~--//

--+-~I--+-'

~+-~--~//--~--~

-READY

-IOR,XIOR

//
-IOW,XIOW

//
t027

XDATADIR

//
//

-IOCS16

10CHRDY

Note:

tSU30

-READY is an open drain output and requires a pull-up resistor that pulls the signal high within two PROCCLK cycles.
We recommend 700 n for the pull-up resistor for 10 MHz and 12 MHz systems.

4-38

•

VLSI TECHNOLOGY, INC.
VL82C101B

MEMORY TIMING WAVEFORM

Ma----READ--~~~------------

WRITE

-----------------"1
2TW

vv-........-- CYCLES
PROCCLK

//
~----r---~/-~------r__r--

-SO.-Sl

ALE

RAMALE
FASTMODE=O
RAMALE
FASTMODE =1

RAS
FASTMODE

RAS
FASTMODE =1
ENDRAS
DTI-R

-DENLO.
-DENHI
-MEMR.
-XMEMR.
-SMEMR

L-~----r-----//_~--------I\~--1038

------.--.:.--"""11

LJ~--~------7/_~-----r~-U--+--------~/_------~r_--

~~-+--------//-~----_r---
~tD40

-MEMW.
-XMEMW.
-SMEMW

-WSO

F16

-MEMCS16

4-39

•

VLSI TECHNOLOGY, INC.
VL82C1018

CONVERSION TIMING WAVEFORM

3TW
CYCLES

PROCClI<

ALE

SAO

-XBHE

~~~~~---//----~--~-----r---//~--~~-----

-lOR.
-lOW.

-MEMR.
-MEMW
Q1

//~-----+------

CNTLOFF

tD52

DIR245

GATE245

------+-~r---~//------------------~

-wso

F16

-IOCS16

Note:

>~~<--------------------------~,~~<------------------

DIR245 goes low for a write cycle. It will remain high for read cycles.

4-40

•

VLSI TECHNOLOGY, INC.
VL82C101B

INTA TIMING WAVEFORM

PROCCLK

ALE

t054
-INTA

OT/-R

-OENLO

t027
XOATAOIR

~tD27

4-41

VLSI TECHNOLOGY, INC.
VL82C101B
DMA MODE TIMING
Symbol

Parameter

Max

Unit

tD55

-OMMEN Delay

Min

Note 1
From-XIOR

tD56

XDATADIR Delay

1057

-lOR, -lOW Delay

1058

-XBHEDelay

1059

DIR245 Delay

1060

-MEMW, -MEMR, -5MEMW, -5MEMR Delay

1061

RAS Delay

tD62

GATE245 Delay

Condition

Note 2

-AEN10nly

Notes: 1. Either -AEN1 or -AEN2 forces -OMMEN low.
2. During -AEN2, -XBHE is low; during -AEN1, -XHBE follows XAO inverted.

DMA MODE TIMING WAVEFORMS
-AEN1,
-AEN2

-OMMEN

~-t\~---------------------------~I
~-t

-XIOR,
-XIOW

XDATADIR

-lOR,
-lOW
i
I
I

4-42

•

VLSI TECHNOLOGY, INC.
VL82C1018

DMA MODE llMING WAVEFORMS (Cont.)

XAO

."~D
-----------~~

-XBHE

---------------~\~---~--

HJ..._________

-XMEMW.
-XMEMR

DIR245

-MEMW. __________________~----~

'----11--_ _

-ME MR.

-SMEMW.
-SMEMR

RAS

-XMEMW.
-XMEMR.
-XIOR

GATE245

1f4"-

1D62

rID~~~
)

------------~\~-----------

4-43

•

VLSI TECHNOLOGY, INC.
VL82C1018

BUS MASTER MODE TIMING

Symbol

Parameter

t063

-XMEMR, -XMEMW from -MEMR, -MEMW Delay

Min

Max

Unit

250

t064

-5MEMR, -5MEMW from -MEMR, -MEMW Delay

239

t065

RAS from -MEMR, -MEMW Delay

237

tD66

-XIOR, -X/oW from -lOR, -lOW Delay

t067

XDATADIR from -lOR, -lOW Delay

BUS MASTER MODE TIMING WAVEFORM

-MEMR,
-MEMW

-XMEMR,
-XMEMW

-SMEMR,
-5MEMW

tD63

t064

tD65
RAS

-lOR,
-lOW
-XIOR,
-X/oW
XDATADIR

t066

tD67

Note: XDATADIR goes low only for -lOR when XA9, XA8 are low and -NPCS is not active.

Condition

•

VLSI TECHNOLOGY, INC.
VL82C1018

REFRESH TIMING
Symbol

Parameter

Min

Max

UnH

tSU68

-REFRESH to PROCCLK Setup Time

t069

-REFEN from PROCCLK Delay Time

t070

-MEMR. -XMEMR. -SMEMR from PROCCLK
Delay Time

REFRESH TIMING WAVEFORM
PROCCLK

SYSCLK

-REFRESH

-REFEN

-MEMR.
-XMEMR.
-SMEMR

_ _ _ _ _ _ _--Ir-'-_tD_7_0_ _ _

~/~ tD70

4-45

Condition

•

VLSI TECHNOLOGY, INC.
VL82C1018

NUMERICAL PROCESSOR INTERFACE TIMING

Max

Unit

Symbol

Parameter

tD71

-BUSY286 from -BUSY287 Delay

tH72

-ERROR from -BUSY287 Hold lime

tSU73

-ERROR to -BUSY287 Setup Time

tD74

-BUSY286 from -lOW Delay

t075

RESET287 from -lOW Delay

Min

tSU76

XA Inputs to -lOW Setup Time

tH77

XA Inputs from -lOW Hold Time

t078

XA Inputs to -NPCS Delay

tD79

XA Inputs to -PPICS Delay

Condition

NUMERICAL PROCESSOR INTERFACE TIMING WAVEFORM
-BUSY287

-ERROR

-J

tS~r-~72-=r ~
tD71

-BUSY286

\,-------,'
\~

______________

tD71

~,r---------------------------

tD74

-lOW

tSU76
XAS-9.
XA3.XAO

RESET287

VALID

--------------------------------~

-NPCS

-PPICS

4-46

•

VLSI TECHNOLOGY, INC.
VL82C1018

AC TESTING -INPUT, OUTPUT WAVEFORM

INPUT

3.5V

rx
~ ~CTESTPOINTS'--~~

----t
0.2V

cmror~

'.5V

,*,_
V1.5

AC TESTING - LOAD CIRCUIT

c>_D_E_V_IC_E_U_N_D_ER_TE_S_T_ _ _ _---.

Cl·

·Includes scope and jig capacitance.

AC TESTING - LOAD VALUES
Test Pin

CL(pF)

200

39-42,46,50,51,65

150

20-22,31,34-37,45,47,

100

All Others

4-47

•

VLSI TECHNOLOGY, INC.
VL82C101B

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

Storage Temperature -65·Cto+150·C
Supply Voltage to
Ground Potential
Applied Input
Voltage

-D.5 V to +7.0 V
-D.5 Vto + 7.0 V

Power Dissipation

500mW

DC CHARACTERISTICS:

TA =

o·c to +70·C, VDD =5.0 V ±5%, VSS =0 V

Symbol

Parameter

MIn

VOH

Output High Voltage

2.4

VOL1

Output Low Voltage

Max

Un"

IOH =-3.3 mA

0.45

IOL = 20 mA, Note 1

10L = 8 mA, Note 2

Output Low Voltage

0.45

VOL3

Output Low Voltage

0.45

VIH

Input High Voltage

2.0

VIL

Input Low Voltage

-D.5

VIHS

Input High Voltage

4.0

VDD + 0.5
0.8
VDD + 0.5

10L = 2 "mA, All Other Pins
V

Output Capacitance

Input Capacitance

-100

100

Input Leakage Current

-10

IllS

Input Leakage Current

-D.5

0.01

ILIX

Input Leakage Current

I1A
I1A
I1A
I1A

Input/Output Capacitance

ILOL

Three-state Leakage Current

III

Notes: 1.
2.
3.
4.

Power Supply Current

Except POWERGOOD

CIO

Condition

VOL2

ICC

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

O·C to +70·C

POWERGOOD, Schmitt-trigger

Except-SO, -S1, XTAL1 (2), XTAL2(2)
-SO, -S1, Note 3
XTAL1(2), XTAL2(2)
Note 4

Pins 39-42 and 49-51.
Pins 20-22, 31, 34-37, 45-47 and 65.
-S1 and -SO have small pull-up resistors to VDD and source up to 0.5 mA when pulled low.
Inputs = VSS or VDD, outputs not loaded.

4-48

•

VLSI TECHNOLOGY, INC.
VL82C102A
PC/AT-COMPATIBLE MEMORY CONTROLLER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The VL82C102A PC/AT-Compatible
Memory Controller generates the row
and column decodes necessary to
support the dynamic RAMs used in PC/
AT-type systems. In addition, the
device allows five motherboard memory
options for the user, up to a full 4M-byte
system. Four of the five options allow a
full 640k-bytes user area to support the
disk operating system (DOS). In
addition, the VL82C102A provides the
upper addresses to the 110 slots, the
chip select for the ROM and RAM

• Completely performs memory control
function in IBM PC/AT-compatible
systems
• Replaces 20 integrated circuits on
PC/AT-type motherboard
• Support 12 MHz system clock
• Device is available as ·cores· for
user-specific designs
• Designed in CMOS for low power
consumption

BLOCK DIAGRAM

memory, and drives the system's
spe_aker.
The device is manufactured with VLSl's
advanced high·performance CMOS
process and is available in a JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
VL82C102A is part of the PC/ATcompatible chip sets available from
VLSI. Please refer to the Selector
Guide in the front of this manual.

ORDER INFORMATION

-OM::: . .f--------~:~I::~" I. .

I--_ _ _ _ _

Part
Number

Package

SAO

VL82C102A-OC

Plastic Leaded Chip
Carrier (PLCC)

A17-A23

1-......- - - - -

SA17·SA19

1----+----...

AEN

CPUA20
A20GATE

CPUHLDA

ALE

-MASTER
LA17·LA23

RAMALE

!f.~~~:t:k!L~~l=: MA~MA9

-E~R~~~ ~--------'[~===:111

{F~r

ADDRSEL
REFBrr9

CASO
CAS1

RESET
OUT2

{-LMEGCS
-LCSOROM

XDO-XD7

t - - - - - -...

PORTBRD

XA~~p~~
}
-ENAS
Q1
-XIOR

-XIOW

~~~Rr?M

PORT B

NMI

ENRAMPCK
ENIOCK
_ _.....

SPKRDATA

PORTBWR

1"-------------{ RTCAS

R'i~~2

1.._ _

RTCRJ-W

4-49

Note: Operating temperature range is
O·C to +70·C.

•

VLSI TECHNOLOGY, INC.
VL82C102A

PIN DIAGRAM

-10
CHCK

RE
SET

ALE

VDD

RAM
SELO

-x

-P
PICS -XIOW

MEMR

RAM1 I XA4 I-XIOR I
A20 I OUT2 I-DMA
GATE
AEN I-RE
FRESH I-PAR
ERROR I VSS I SEL

-E
NAS
IADDR
SEL

•

CPUHLDA
CPUA20
-MASTER

REFBIT9
73

RTCAS

RTCDS

RAMALE

RTCRI-W

RAMSEL2

-CS8042

VSS

NMI

SPKRDATA

MA9

MA8
VSS

VSS

VL82C102A

F16
RASO
RAS1

TOP VIEW

CASO
CAS1

-LMEGCS

LA23

-LCSOROM

LA22

-MDBEN

LA21

VSS

LA20

SAO

LA19

XAO

VSS

AEN

LA18

VSS

LA17

VDD

SA19

XDO

SA18

~~~~~~~~~~"~~U~~~~~

XD1

I XD3 I XD5 I XD7 I A23 I A21
XD2

XD4

XD6

VSS

A22

I A19 I A17
A20

4-50

A18

I VDD

-LdS1
ROM

IPARENI XA16
SA17

VSS

•

VLSI TECHNOLOGY, INC.
VL82C102A

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Type

Signal
Description

No Connect

-PARERROR

Parity Error - A low true input used to indicate that a memory parity error
has occurred.

-REFRESH

Refresh - An active low input used to initiate a refresh cycle for the dynamic
RAMs.

ALE

Address Latch Enable - This is a positive edge input that controls the
address latches which hold the address during a bus cycle. ALE is not
issued for a halt bus cycle.

-DMMEN

DMA Address Enable - This is an active low input. It is active whenever an

VO device is making a DMA access to the system memory.
RESET

Reset - This active high input signal is the system reset generated from a
POWERGOOD. It is synchronized to PROCCLK.

OUT2

Out 2 - The output of the timer controller. It can be read by the CPU on
PortB.

-IOCHCK

Channel Check - This active low input is asserted by devices on the
expansion bus. It will generate a non-maskable interrupt if NMI is enabled.
-IOCHCK can be read by the CPU on Port B.

A20GATE

A20GATE - Used to select the proper value for address bit 20. CPUA20 is
transmitted out as A20 if A20GATE is high. otherwise A20 is forced low.

CPUHLDA

CPU Bus Hold Acknowledge - This input indicates ownership of the local
CPU bus. When high. this signal indicates that the CPU has three-stated
its bus drivers in response to a hold request. When low. it indicates that
the CPU bus drivers are active.

CPUA20

CPU Address Bus Bit 20 -It is transmitted out as A20 if A20GATE is high.

-MASTER

Master - An active low input. It is asserted low by devices on the expansion bus. A low indicates that another device is active.

RAMALE

RAM Address Latch Enable - Used in the FASTMODE of operation. When
FASTMODE is inactive RAMALE is equal to ALE

RAMSEL2

RAM Select 2 - Used with RAMSELO and RAMSEL 1 to select the system
RAM configuration.

F16

An output that indicates a word memory access. It is used to inhibit
command delays during a 16 bit memory access.

RASO

RAM Address Select 0 - An active high output that is the select signal for
the lower address bank of RAM.

RAS1

RAM Address Select 1 - An active high output that is the select signal for
the upper address bank of RAM.

CASO

An active high output that is the select signal for the lower bank of RAM.

CAS1

An active high output that is the select signal for the upper bank of RAM.

-LMEGCS

Lower Megabyte Chip Select - An active low output that indicates that the
lower memory address space (0-1 megabyte) is selected.

-LCSOROM

Latched Chip Select 0 for ROM - An active low output that is the latched
chip select for the ROM address space.

4-51

•

VLSI TECHNOLOGY, INC.
VL82C102A

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

-MDBEN

Memory Bus Enable - An active low output that controls the direction of
data flow between the system and memory data buses. When -MDBEN is
high data flows from memory to system. When low, data flows from
system to memory. .

SAO

110

System Address Bus Bit 0 - This signal will be an output with the value of
XAO when -OMMEN is low. It will be an input and drive XAO when
-OMMEN -1.

XAO

110

Peripheral Address Bus Bit 0 - This signal is an output driven by SAO when
-OMMEN - 1, and an input driving SAO when -OMMEN _ o.

AEN

Address Enable - This is an output signal for the expansion bus. It will go
low when master is active or HLDA is inactive.

XDO-XD3

32-35

110

Peripheral Data Bus Bits 0-3 - These are data bits for the peripheral bus.
They are outputs when Port B is being read; otherwise they are inputs.

XD4·XD6

36-38

Peripheral Data Bus Bits 4-6 - These are data bits for the peripheral bus.
They are driven as outputs when Port B is being read, otherwise threestated.

XD7

110

Peripheral Data Bus Bit 7 - An output when Port B is read, and an input
which enables NMI during an NMICS.

A17-A23

47-41

110

CPU Bus Bits 17-23 - These are the upper bits of the CPU address bus.
Outputs when -MASTER is low, inputs when -MASTER is high.

-LCS1ROM

Latched Chip Select 1 for ROM - The active low latched chip select output
for the high ROM address space.

PAREN

Parity check Enabled - Logical OR of CASO and CAS1, indicates a memory
access so parity check is enabled.

SA17-SA19

50,54,55

System Address Bus Bits 17-19 - A17-A19 are latched by ALE and transmitted out on these outputs when CPUHLDA is inactive. They are driven
directly by A17-A19 when CPUHLDA is active and -MASTER is inactive.
They are three-stated when -MASTER is active.

XA16

LA17, LA18,
LA19-LA23

56,57
59-63

110

System Address Bus Bits 17-23 - These are the upper bits of the system
address bus to the expansion slots. These pins are configured as outputs
when -MASTER is high, and as inputs when -MASTER is low.

MA8, MA9

65,66

DRAM Memory Address Bus Bits 8-9 - These outputs are the 8th and 9th
bit of the DRAM memory address. They are located on the VL82C102A to
allow system address mapping. REFBIT9 is multiplexed into MAS during a
refresh cycle.

SPKRDATA

Speaker Data - Output to be buffered by the 754n and sent to the
speaker.

NMI

Non-maskable Interrupt - This output is the non-maskable interrupt signal
for the CPU.

-CS8042

Chip Select signal for the Keyboard Controller - This active low output is
the chip select signal for the keyboard controller programmable interface
device.

Peripheral Address Bus Bit 16 - This switches between -LCSOROM and
-LCS1ROM.

4-52

•

VLSI TECHNOLOGY, INC.
VL82C102A

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

-RTCRIW

Real Time Clock Signal for ReadoWrite - This is the readlwrite select output
signal for the real time clock. A high indicates a read operation and a low
write operation.

RTCDS

Real Time Clock Data Strobe - This is the data strobe for the real time

clock.

RTCAS

Real Time Clock Address Strobe - This is the address strobe for the real
time clock.

REFBIT9

Refresh Bit 9 - The carry out of the refresh counter. It is used to generate
a refresh for 1M DRAMs. It is multiplexed out as MA8 when -REFRESH is
active.

ADORSEL

Address Select - This input is a multiplex row/column select for the Memory
Address Bus drivers.

-ENAS

Enable Address Strobe - This active low input is used to enable the
address strobe on the real time clock. It will go low the first time -SO is
asserted after a system reset.

Goes active during the second phase of a CPU bus cycle following the TS
state. It is used by the VL82C102A chip to generate the address strobe for
the real time clock.

-XIOW

Input/Output Write - The active low input command to and from the
peripheral bus. Used to generate selects for the keyboard controller, real
..
time clock. and Port B.

-XIOR

InputlOutput Read - The active low input command to and from the
peripheral bus. Used to generate selects for the keyboard controller, real
time clock. and Port B.

-PPICS

Programmable Peripheral Interface Chip Select - An active low input used
to generate the chip select for the keyboard controller.

XA4

Peripheral Address Bus Bit 4 - An input used to generate selects for the
keyboard controller, real time clock, and Port B.

-XMEMR

Memory Read - An active low input command to and from the peripheral
bus. This pin is used to determine the direction of data on the memory
data bus and to clock in parity check results.

RAMSEL1

RAM Select 1 - This input is used with RAMSELO to designate the system
RAM configuration.

RAMSELO

RAM Select 0 - This input is used with RAMSEL 1 to designate the system
RAM configuration.

VDO

4,31,49

System Power: 5 V

VSS

1, 17, 26, 30,
40, 52, 58, 64,
69

System Ground

4-53

•

VLSI "TECHNOLOGY, INC.
VL82C102A

FUNCTIONAL DESCRIPTION
The VL82C102A Memory Controller
provides address buffering for the upper
address bits on the system and CPU
address buses. It generates chip selects
for the two possible RAM banks and the
two possible ROM banks. The
VL82C102A also contains the Port B
register logic to control the Non-Maskable Interrupt signal and the speaker. It
also generates chip select decodes for
the keyboard controller and real time
clock.
MEMORY DECODES
The upper address bits A 17-A23 and
XA16 are used to decode chip selects for
all on-board memory. The three option
inputs RAMSEL2, RAMSEL1, and
RAMSELO are used to select one of five
possible memory mapping options.
Refer to Figure 1.
RAM SELECTS
The memory mapping options shown in
Figure 1 are used to generate the enable
signals for the RAS and CAS pulses to
the DRAMs. RASO and CASO are the
enables for Bank o. RAS1 and CAS1
are the enables for Bank 1. These
signals will be active anytime the decode
on address bits A 17-A23 fall in the
ranges shown in the memory maps. The
signals are latched by the input signal
RAMALE. The latches will be transparent while RAMALE is high and hold the
value in the latch while RAMALE is low.
The latch clocks will also be forced high
when CPUHLDA is active making the
latches transparent during all hold
acknowledge operations.
When -REFRESH is active, address bits
A17-A23 are ignored and both RASO and
RAS1 are forced active (high) while
CASO and CAS1 are forced inactive
(low).
MA8 AND MA9
A 17-A23 are also used to generate four
address bits for the upper address bits of
the DRAM memory space. These
address bits are also latched by the
combination of RAMALE and CPUHLDA
as described for the RAM selects. The
four latched address bits are then

multiplexed out on MA8 and MA9. MA9
is needed only if a memory mapping
option using 1M-bit DRAMs is selected.
REFBIT9 is multiplexed out onto MA8
during refresh cycles.
ROM SELECTS
The ROM address space is decoded
from A17-A23 and latched by ALE.
These latches are also forced transparent when CPUHLDA is active in the
same manner as the latches for the RAM
chip selects. This latched value is then
split into the two signals -LCSOROM and
-LCS1ROM using theXA16 input. If two
banks of 32K by 16-bit words of ROM
are used, the XA16 input must by tied to
the XA16 signal on the system board to
select the proper bank based on the
valueonXA16. IfXA16 is low,
-LCSOROM will go active any time the
ROM address space is decoded. If
XA16 is high, -LCS1ROM is decoded.
In this configuration -LCSOROM selects
the address space from OE 0000 to OE
FFFF while -LCS1 ROM selects the
address space OF 0000 to OF FFFF.
When only using one bank of 16K, 32K,
or 64K by 16-bit words of ROM, the
XA16 input can be tied high and
-LCS1 ROM used to select the bank. In
this configuration -LCSOROM will always
remain inactive while -LCS1 ROM
selects the address space OE 0000 to OF
FFFF.
The ROM address space is duplicated at
FE 0000 to FF FFFF and the chip selects
will go active in the same manner as
described above in this address space.
UPPER ADDi'tESS BUFFERS
The VL82C102A provides buffer drive
capability to drive the card slots on the
110 signals LA17-LA23 and SA17-SA19.
The values on A17-A23 are passed
directly through to the LA17-LA23
outputs if -MASTER is high. If
-MASTER is low LA17-LA23 become
inputs and pass the value on those pins
to the A17-A23 bus.
A17-A19 are latched by ALE and driven
onto the SA17-SA19 bus whenever
CPUHLDA is low. When CPUHLDA is

4-54

high and -MASTER is high, the latch is
bypassed and A17-A19 is driven directly
to SA17-SA19. SA17-SA19 will be left
floating when CPUHLDA is high and
-MASTER is low.
ADDRESS BIT 20
Address bit 20 is handled differently than
the other address bits. The A20 signal
will be generated directly from CPUA20
(which should be connected to A20 on
the 80286 CPU) if the input A20GATE is
high. If A20GATE is low, the A20 signal
is forced low.
ADDRESS BIT 0
A buffer transceiver between XAO and
SAO is also provided on the VL82C102A.
If the input -OMAAEN is high, signal flow
is from SAO to XAO. If -DMAAEN is low,
signal flow is from XAO to SAO.
PORTB
The Port B register in an AT-()()mpatible
design is located on the VL82C102A. It
can be read or written to with an 1/0
command to address 61 hex. Port B is
used to control the speaker and mask
out NMI sources. It can be read to find
status of -REFRESH, speaker data, and
possible sources of NMI.

110 DECODES
The VL82C102A provides the chip select
signals for the on-board I/O peripherals
(keyboard controller and real time clock).
NMILOGIC
The logic necessary to control the NonMaskable Interrupt (NMI) signal to the
processor is contained in the
VL82C102A. An NMI can be caused by
a parity error from the system board
DRAM or if an 110 adapter pulls the input
IOCHCK low. These two possible
sources can be individually enabled to
cause an NMI by setting the appropriate
bits in the Port B register. At power-up
time, the NMI signal is masked off. NMI
can be masked on by writing to I/O
address 070 hex with bit 7 low, or
masked off by writing to 1/0 address 070
hex with bit 7 high.

•

VLSI TECHNOLOGY, INC.
VL82C102A

FIGURE 1. MEMORY MAP OP11ONS
128K BYTES

SYSTEM BOARD RAM 512K

SYSTEM EXPAN. TO 640K
GRAPHICS DISPLAY BUFFER

~===:' ,~===:
100000

110 ADAPTERS ROM
SYSTEM BOARD ROM

1=====1' '1=====1

~ ~ ~::::::---i::~

~~~~~

II
18X256K

000

I I

I L-I_----'

18 X 256K
18X64K

18 X 256K
18 X 256K

18X 1M

001

010

011

4-55

18X 1M
18X 1M
100

DUPLICATE ASSIGNMENT
FOR SYSTEM BOARD ROM
BANKOEII
BANK1-

RAMSEL2, RAMSEL1, RAMSELO

•

VLSI TECHNOLOGY, INC.
VL82C102A

AC CHARACTERISTICS: TA = O°C to +70°C, VDD =5 V ± 5%, VSS = 0 V
PERIPHERAL CONTROL TIMING
Symbol

Parameter

tD1

SPKRDATA Output Delay

Min

Max

Unit

Condition

CL=50pF

tD2

NMI Output Delay

CL=100pF

tD3

RTCDS, -RTCRIW, -CS8042 Output Delays

CL=50pF

tD4

RTCAS Output Delay

CL=50pF

PERIPHERAL CONTROL TIMING WAVEFORMS
OUT2
-ENAS
Q1

-PPICS
XA4,XAO
-XIOW
-XIOR

\ /
J \.

...
~

RTCDS
-RTCRIW
-OS8042

tD3

...

Jf\.
tD4

...
\/

RTCAS

J\.

~~_-_-___
tD1~_-_-_~~~--------

_________
SPKRDATA

-XIOW
-PARERROR
-1I0CHCK
________

NMI

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

~ tD2~_-_~~----------------

_ _ _ _ _ _ _ _ _ __ _ _ _

4-56

VLSI TECHNOLOGY, INC.
VL82C102A
XD BUS TIMING
Symbol

Parameter

tD5

XD Bus Delay

tH6

XD Bus Hold Time

Min

Max

Unit

XD = Output

Condition

tSU7

XD Bus Setup Time

XD = Input

tH8

XD Bus Hold Time

XD = Input

XD BUS TIMING WAVEFORMS

Output
-XIOW
XA4
-PPICS
~---tD5--"'"

XDBUS
(OUTPUT)

HIGHZ

Input
-XIOR

~ICS

\ ' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~~:~~ --------------f ~~:DDATAIN ~

4-57

lHaj_____

•

VLSI TECHNOLOGY, INC.
VL82C102A

ADDRESS CONTROL nMiNG
Symbol

Parameter

Max

Unit

tD9

F16 Output Delay

Cl=50pF

tD10

RASOI1, CASO/1 Delay from A 17-A23

Cl = 50 pF, RAMAlE High

tD11

RASOI1, CASOI1 Delay from RAMALE

tD12

-lMEGCS Delay from ALE

Clz50pF

Min

Condition

tD13

-lCS1 ROM, -LCSOROM Delay from ALE

Cl.50pF

tD14

-lCS1 ROM, -LCSOROM Delay from A 16

Cl.50pF

tD15

MDBEN Output Delay

Cl=50pF

1016

AEN Output Delay

Cl = 150 pF

Note: RAMSElO, RAMSEL 1, and RAMSEl2 are assumed setup one processor clock before the user generates any memory
control signals. These inputs are normally strapped to VDD or VSS in a system.

ADDRESS CONTROL nMING WAVEFORMS
A17-A23
-REFRESH

4 - - tD9 --I"~
F16

RASO/1

-----------+----~}~-----------I..
...

~r-------

tD10---"'~

CASO/1
----------....:....-----------'
(WITH RAMAlE
HIGH)

\-------

RAMALE

RASO/1
CASO/1

4-58

•

VLSI TECHNOLOGY, INC.
VL82C102A

ADDRESSCONTROl TIMING WAVEFORMS (Cont.)

ALE

~t---- 1012

....
-LMEGCS

-LCSOROM
-LCS1ROM

-.1

1_ - - - - - - - - - - - - - - -

PL-----

=t~~:::::~tD~1-3=====~L--------.

>i IDI4~l---_

XA16

-LCSOROM
-LCS1ROM

-XMEMR

mI.

-MOBEN

CPUHLOA
-MASTER

AEN

>t lDl.~l:--_
4-59

•

VLSI TECHNOLOGY, INC.
VL82C102A

ADDRESS BUS TIMING
Min

Max

Unit

CL=150pF

Note, CL = 150 pF

-REFRESH=O

Condition

Symbol

Parameter

tD17

MA8, MA9 Delay from RAMALE

tD18

MA8, MA9, Delay from ADDRSEL

tD19

MA8 Delay from REFBIT9

tSU20

A 17-A23 Setup to ALE, RAMALE

tH21

A17-A23 Hold

tD22

XAOISAO Delay

CL - 50 pF SAO, CL -100 pF XAO

tD23

SA17-SA19 Delay

CL - 200 pF, CPUHLDA .. 1, -MASTER _ 1

tD24

SA17-5A19 Delay from ALE

CL = 200 pF, CPUHLDA .. 0

tD25

LA17-LA23 Delay

CL = 200 pF, -MASTER = 1

tD26

A 17-A23 Delay

CL = 50 pF, -MASTER - 0

Note: ID18 delay may be derated by a factor of .04 nslpF for heavier loads.
ADDRESS BUS TIMING WAVEFORMS

_W17~ .~_ _ _ _ _ _ _ _ _ _ _ __

->K

MA8, MA9

ADDRSEL

MA8, MA9

VALID ADDRESS

( ID1'~~-V-A-Ll-D-A-D-D-R-E-SS~---------------------\\..---

REFBIT9
(-REFRE::':S""'H""'.-O""'j--~

~ID19

1 = - - - - = - - t D 1 9~------------~~--~

MAS
Note: ISU20 is specified with respect to the falling edge of RAMALE to guarantee the correct address decodes will be latched
in. tSU20 is shown with respect to the rising edge of RAMALE to show time required for address decodes such that
propagation delays tD17 and tD11 will be valid. The time does not have to be met with respect to the rising edge for
correct functionality.
4-60

•

VLSI TECHNOLOGY, INC.
VL82C102A

ADDRESS BUS TIMING WAVEFORMS (Cont.)

~~~UT)------------E=_i_________
VAliD

(-OMMEN", 1)

XAO
___________________
(OUTPU-:2

~_ _ _ _ _ _ ___

~~UT)------------E'D22_I>K_________

(-DMAAEN • 0)

(OUTPU'2.

SAO
A17-A19

VALID

====~-;.==~----...-:-------------------=

______

__--tD23
VALID

SA17-SA_19_ _ _ _ _ _ _ __

~~---

ALE

SA17-SA19

A17-A23_ _ _ _ _ _t =_______________________________

~~,:~;fER=l)

tD2~=*~

LA17-LA23

~~~

(-MASTER = 0)

t=1D26~

-_
-_
--_
-_
--_A17.A23:__
__
__

_ _ _ _ _ _ _ _ _ _ _ __
VALID ADDRESS

_ _ _ _ _ _ _ _ _ _ _ __

~V~A~LI~D~A~D~DR~E~S~S~_ _ _ _ _ __

4·61

•

VLSI TECHNOLOGY, INC.
VL82C102A

ADDRESS BUS TIMING WAVEFORMS (Cont.)

LA17-LA23
(INPUT)
(-MASTER ~ 0)

VALID ADDRESS

A17-A23

MISCELLANEOUS INPUT TIMING

Max

Unit

Symbol

Parameter

Min

t27

Min High (Active) Time on RESET

100

t28

Min Low time for -XMEMR

MISCELLANEOUS INPUT TIMING WAVEFORMS

RESET
-XMEMR

t27
t28

4-62

Condition

•

VLSI TECHNOLOGY, INC.
VL82C102A

AC TESTING -INPUT, OUTPUT WAVEFORM

INPUT

3.5V
-----frY1SV

0.2V

AC TEST

*~1'5V

POINTS--~~ ~

AC TESTING - LOAD CIRCUIT

DEVICE UNDER TEST

~L"
"Includes scope and jig capacitance.

AC TESTING - LOAD VALUES

Test Pin

CL(pf)

27, 29, 50, 54-57, 59-63

200

65,66

150

28,32-39

100

All Others

4-63

•

VLSI TECHNOLOGY, INC.
VL82C102A

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature
Storage Temperature

0·Cto+70·C
-65.Cto+150.C

Supply Voltage to
Ground Potential
Applied Input
Voltage

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

indicated in this data sheet is not
implied. Exposure to absolute maximum
rating conditions for extended periods
may affect device reliability.

-0.5 V to 7.0 V
-0.5 V to +7.0 V

Power Dissipation

500mW

DC CHARACTERISTICS:

TA = o·c to +70·C, VDD =5V ±5%, VSS = 0 V

Symbol

Parameter

Min

VOH

Output High Voltage

2.4

VOL1

Output Low Voltage

VOl2

Max

Unh

Condhlon

IOH =-3.3 mA

0.45

SAO, SA17-SA19, AEN, LA17-LA23,
IOL=20mA

Output Low Voltage

0.45

MAS, MA9, F16, XAO, XDO-XD7,
IOL=SmA

VOL3

Output Low Voltage

0.45

All Other Pins, IOL • 2 mA

VIH

Input High Voltage

Except -REFRESH

-REFRESH, Schmitt-trigger

0.6

-REFRESH, Schmitt-trigger

2.0

VIL

Input Low Voltage

-0.5

VIHS

Input High Voltage

3.5

VILS

Input Low Voltage

-0.5

Output Capacitance

Input Capacitance

CIO

Input/Output Capacitance

ILOL

Three-state Leakage Current

III

Input Leakage Current

ICC

Power Supply Current

VDD+0.5
O.S
VDD+0.5

-100
-10

Note: Inputs = VSS or VDD, outputs are not loaded.

4-64

100
10

JLA
JLA

Note

•

VLSI TECHNOLOGY, INC.
VL82C103A
PC/AT-COMPATIBLE ADDRESS BUFFER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The VL82C103A PC/AT-Gompatible
Address Buffer provides the system
with a 16-bit address bus input from the
CPU to 41 buffered drivers. The
buffered drivers consist of 17 bidirectional system bus drivers, each capable
of sinking 20 mA (50 'LS loads) of
current and driving 200 pF of capacitance on the backplane; 16 bidirectional
peripheral bus drivers, each capable of
sinking 8 mA (20 'LS loads) of current;
and eight memory bus drivers, also
capable of sinking 8 mA of current. Onchip refresh circuitry supports both

• Completely performs address buffer
function in IBM PC/AT-compatible
systems
• Replaces several buffers, latches and
other logic devices
Supports up to 12 MHz system clock
• Device is available as "cores· for
user-specific designs
• Designed in CMOS for low power
consumption

0
SA()'SA16

LATCH
A1-16
ALE
CPUHLDA

XA1-XA16

RESET + H - - f - - f CLR
9BIT
COUNTER
+H~--q

MA()'MA7
ADDRSEL++-+4---------------~~_f~

-REFRESH _rt-t~'?'=====;rl_r--M
RAMALE -11-[=--:;:":':':'_.....1

L.....t_f------------. REFBIT9

J-----------t-t-----------~BALE

-BHE

Part
Number
VL82C103A-QC

GATE
ENABLE

-DMAAEN ~~------------~~----++--.

-REFEN

The device is manufactured with VLSl's
advanced high-performance CMOS
process and is available in a JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
VL82C103A is part of the PC/ATcompatible chip sets available from
VLSI. Please refer to the Selector
Guide in the front of this manual.

ORDER INFORMATION

BLOCK DIAGRAM
A1-A16

256K-bit and 1M-bit DRAMs. The
VL82C103A provides addressing for the
110 slots as well as the system.

LATCH
-XBHE
GATE2
ENABLE

-SBHE

-B~::!~R _______________~~ DECODE 11-____________•• IRQ13
4-65

Package
Plastic Leaded Chip
Carrier (PLCC)

Note: Operating temperature range is
O·C to +70·C.

•

VLSI TECHNOLOGY, INC.
VL82C103A

PIN DIAGRAM

RAMALE
-BUSY
287

A10

•

-BHE
AS

XA9

XA10

XA11

XA12

XA13

XA14

VL82C103A

A3
A2
A1

TOP VIEW

VSS

XA15

XA16

-XBHE

VSS

ALE

MA7

CPUHLOA

MA6

-OMMEN

MAS

-REFRESH

MA4

-REFEN

MA3

AODRSEL

MA2

RESET

MA1

-ERROR

MAO

REFBIT9

VDD

VOD

BALE

-5BHE

VSS

M~$U~~~~~~~~~U~~~~~

VSS

SA15

SA16

SA13

SA14

VSS

SA12

SA10

SA11

SAS

SA9

4-66

VDD

SA7

SA6

SAS

SA4

VSS

SA3

SA2

SA1

53
SAO

•

VLSI TECHNOLOGY, INC.
VL82C103A

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Type

Signal
Description

A1-A8,
A9-A16

20-13
9-2

CPU Address Bus Bits 1-16 - The lower 16 bits of the CPU address
bits. These are multiplexed the System Address Bus for the slots SA1SA16, the Memory Address Bus MAO-MA7 and the Peripheral Address Bus
XA1-XA16.

RAMALE

RAM Address Latch Enable - This positive edge input controls the address
latch for the Memory Address bus outputs (MAO-MA7). When used with
the System Controller Chip, in FASTMOOE, RAMALE will open the
memory address latches at the same time a -MEMR or a -MEMW is
generated. If FASTMOOE is not used, RAMALE is the same as ALE. The
memory address latches are open when RAMALE is in the high state.

-BUSY287

Busy 287 - A busy status input that is asserted by the 80287 to indicate
that it is currently executing a command.

-BHE

Bus High Enable - This is the active low input signal from the 80286 microprocessor which is used to indicate a transfer of data on the upper byte on
the data bus, 08-015.

ALE

Address Latch Enable - This positive edge input oontrols the address
latches which hold the address during a bus cycle. ALE is not issued for a
halt bus cycle. All latches are open when ALE is in the high state.

CPUHLOA

CPU Hold Acknowledge - This active high input indicates ownership of the
local CPU bus. When high, this signal indicates that the CPU has threestated its bus drivers in response to a hold request. When low, it indicates
that the CPU bus drivers are active.

-OMAAEN

OMA Address Enable - This is an active low input which is active whenever
an 110 devic~ is making a OMA access to the system memory.

-REFRESH

Refresh - An active low input which is used to initiate a refresh cycle for the
dynamic RAMs. It is used to clock a refresh counter which provides
addresses during the refresh cycle.

-REFEN

Refresh Enable - An active low input that will be asserted when a refresh
cycle is needed for the DRAMs.

AOORSEL

Address Select - This is a multiplex select for the Memory Address Bus
drivers. When AOORSEL is low, the lower order address bits are selected.
When high, the high order address bits are selected.

RESET

Reset - This active high input signal is the system reset generated from a
POWERGOOO. It is synchronized to PROCCLK and used to reset the
refresh counter.

-ERROR

Error - This is an active low input which indicates an error has occurred
within the 80287 coprocessor.

REFBIT9

Refresh Bit 9 - This is the MSB of the refresh counter. When used with the
Memory Controller chip a refresh address will be generated for 1M byte
DRAMs.

-SBHE

110

System Bus High Enable - This is the system I/O signal used to indicate
transfer of local data on the upper byte on the local data bus, 08-015.
-SBHE is active low and will be in input mode during bus hold acknowledge.

SAO-SA16

53-50, 48-45
43-40, 38-34

System Address Bus Bits 0-16 - SAO will be active only during a
refresh cycle otherwise it will be three-stated (input mode).

4-67

•

VLSI TECHNOLOGY, INC.
VL82C103A

SIGNAL DESCRIPTIONS (Cont.)
Signal

Signal

Signal
Description

Name

Pin
Number

Type

BALE

Buffered Address Latch Enable - An active high output that is used to latch
valid addresses and memory decodes from the 80286. System addresses
SAO-SA 16 are latched on the falling edge of BALE. During a DMA cycle
bale is forced active high.

MAO·MA7

57·64

DRAM Memory' Address Bus Bits 0-7 - This 8-bit output is multiplexed
using ADDRSEL to give a full 16-bit address.

XA1-XA16

83-76,74-67

Peripheral Address Bus Bits 1-16 - These I/os are used to control the
coprocessor, keyboard, ROM memory and the DMA controllers.

-XBHE

Transfer Byte High Enable - This is an active low VO used to allow the
upper data byte to be transferred through the bus transceivers.

IR013

This is an active high output which indicates an error has occurred within
the 80287 coprocessor.

VDD

1,31,44,56

System Supply: 5 V

VSS

21, 33, 39, 49,
54,65,75

System Ground

FUNCTIONAL DESCRIPTION
The VL82Cl03A is part of a five chip
set which together perform all of the onboard logic required to construct an IBM
PC/AT-compatible system. The PC/ATCompatible Address Buffer replaces
several bus transceivars and address
data latches located within the PC/ATtype system. The DRAM refresh
circuitry is also located on this device.
The primary function of the Address
Buffer is to multiplex the 80286 microprocessor address lines (A l-A16) to the
system address bus (SA1-SA16), the
peripheral address bus (XA1-XA16),
and the memory address bus (MAOMA7). This is accomplished through
two sets of 16-bit wide, positive edge
triggered latches and a group of data
multiplexors. The two groups of latches
can be seen in the block diagram of the
device. One set of latches have their
output enabled with CPUHLDA and are
gated with ALE. This set of latches
drive the SA and XA bus outputs.
Another parallel set of latches are
multiplexed into the MA lines and are
gated with RAMALE. RAMALE is an
early ALE signal which is generated

inside the System Controller chip.
When FASTMODE is enabled,
RAMALE becomes active as soon as a
-MEMR or -MEMW signal is generated
(typically one PROCCLK earlier than
ALE). This allows more setup time for
the address to be multiplexed to the
DRAMs. If FASTMODE is not enabled,
RAMALE and ALE are identical signals.
Hthe VL82Cl 03A is not used in
conjunction with the other PC/ATdevices, RAMALE and ALE should be
wired together to provide maximum
PC/AT-compatibility.
The device also provid!,s for address
flow between the SA, XA, and MA
buses and the -XBHE and -SBHE
signals. This control flow is arbitrated
with the CPUHLDA, -DMAAEN, and
-REFEN inputs and is shown in
Tablel.
Memory addresses are multiplexed
from the SA and A bus sources and are
controlled via the CPUHLDA,
-REFRESH, and ADDRSEL inputs.
The mapping and control is shown in
Table 2.

4-68

A 9-bit refresh counter is provided on
this device. This allows support for
DRAMs of up to 1M-bit in size. The
refresh counter is clocked on the rising
edge of the -REFRESH input. A
latched register inside the counter
latches in the current state of the
counter on the falling edge of -REFEN
and transfers this value to the internal
bus which routes to the SA and MA bus
outputs. The SAO output is provided
only for refresh purposes and is driven
only during this time. During a refresh
the SA and MA bus outputs are driven
from the output of the refresh counter
latch 00-08. Refer to Table 3 for the
mapping of the refresh counter to the
bus lines.
Note that all SA bus lines are driven
during a refresh cycle. ADDRSEL is not
normally toggled during a refresh cycle
but is shown in Table 3 for completeness of the logic implementation. The
REFBIT9 signal is the 08 output of the
refresh counter. This is output to the
Memory Controller chip which controls
the upper MA address lines. This is
required only for the refresh of 1M-bit
DRAMs. .

•

VLSI TECHNOLOGY, INC.
VL82C103A

TABLE 1. INTERNAL BUS CONTROL DECODE
-DMAAEN

CPUHLDA

-REFEN

-XBHE

-SBHE

I = Input Mode

o = Output Mode
TABLE 2. MEMORY ADDRESS MAPPING
Mux Control Input
CPUHLDA

-REFRESH

MABus
ADDRSEL

MA7

MAO·MA6

SA8

SM-SA7

SA16

SA9-SA15

A1-A7

A16

A9-A15

X= Don't Care

TABLE 3. REFRESH ADDRESS MAPPING
Mux Control Input

MABus

CPU
HLDA

-REF
EN

ADDR
SEL

MA7

AC CHARACTERISTICS:

SA Bus
SAgSA15

SAO·
SA8

01-07

00-08

MAOMA6

TA = O°C to +70°C, VDD = 5 V ± 5.%, VSS = 0 V

CPU MODE TlMING
Symbol

Parameter

Min

Max

Unit

CPUHLDA to SA Bus from High Z to Valid Add Out

CPUHLDA to SA Bus High Z State

CPUHLDA to -SBHE from High Z to Valid Output

Condition

CPUHLDA to -SBHE High Z State

ALE to SA Bus Valid Address

CL= 200 pF

ALE to XA Bus Valid Address

CL= 100 pF

ALE to -SBHE Bus Valid Address

CL= 150 pF

4-69

•

VLSI TECHNOLOGY, INC.
VL82C103A

CPU MODE TIMING WAVEFORMS

CPUHLDA
14---t1

----I~

HIGHZ

SA BUS

VALID ADDRESS

HIGHZ

....--t3----t~
HIGHZ

-5BHE

VALID OUTPUT

HIGHZ

I-

ALE

...

-.\V

SA BUS

....
~

\V
J f\.

XABUS

-5BHE

VALID ADDRESS

Jf\.

VALID ADDRESS

-"I_.:~~~~~~~_t7_-_-_-_-_-_-_~~~,
A\

_ _VALID
_ _OUTPUT
_ _ _ _ _ _ _ _ _ _ _ __

SYSTEM BUS MODE TIMING
Symbol

Max

Unit

SA Bus In to XA Bus Out

CL z 100pF

SA Bus In to MA Bus Out

CL= 150 pF

Parameter

Min

Condition

SYSTEM BUS MODE TIMING WAVEFORM

SA BUS

--I,~-------------------------------"'~----t8 ---t~
..

XABUS

__-+________

MABUS

____

--JJ,~

______________________________

~I.:~~~_t9_____>K~-----------------------------4-70

•

VLSI TECHNOLOGY, INC.
VL82C103A

DMA MODE TIMING
Symbol

Parameter

Max

Unit

110

-OMMEN 10 XA Bus High Z Siale

Min

Condition

111

-OMMEN 10 XA Bus from High Z 10 Valid Add Out

112

-OMMEN 10 -XBHE High Z Slate

113

-OMAAEN 10 -XBHE from High Z 10 Valid Output

114

XA Bus 10 SA Bus Oul

115

XA Bus In to MA Bus Out

CL = 150 pF

116

-XBHE In to -SBHE Out

CL=150pF

CL =200 pF

DMA MODE TIMING WAVEFORMS
-OMMEN

110
VALID
OUTPUT

VALID OUTPUT

XABUS

112

XABUS

.-/\.

114

115

MABUS

-SBHE

..
\V
/1\

SA BUS

-XBHE

VALID
OUTPUT

VALID OUTPUT

-XBHE

116

~
~
4-71

III

•

VLSI TECHNOLOGY, INC.
VL82C103A

REFRESH nMiNG

Symbol

Parameter

tt7
'118

Min

Max

Unit

-REFEN to XA Bus Valid Add Out

CL=100pF

-REFEN to SA Bus Valid Add Out

CL_200pF

t19

-REFEN to MA Bus Valid Add Out

CL-150 pF

120

-REFEN to SA Bus from High Z to Valid Add Out

121

-REFEN to SA Bus High Z Out

Condition

REFRESH nMiNG WAVEFORMS
-REFEN

\
....

117

..
'V

XABUS

/1\

....

118

...

'V
/1\

SA BUS

____~1~.~~~~~::-t1-9~~~~~~~~)k~~--------------------------MABUS

-REFEN
....- - - - 120 -----4..
SA BUS

HIGHZ

VALID ADDRESS

4-72

HIGHZ

•

VLSI TECHNOLOGY, INC.
VL82C103A

ADDRESS nMiNG
Symbol

Parameter

122

ADDRSEL 10 MA Bus Out

Note:

Min

Max

Unit

Condition
CL= 150 pF

122 delay may be deraled by a factor of .04 ns/pF for heavier loads.

ADDRESS nMING WAVEFORM

ADDRSEL~

________________________________________________________

MAO-7

~~~~~~~~~~~~_12_2_-_--_-_-_-_~)\(~1

_- ____
-1

___________________________________

SETUP & HOLD nMING
Symbol

Parameter

ISU23

A Bus 10 RAMALE and -SHE 10 ALE Selup Timing

IH24

A Bus 10 RAMALE and -SHE to ALE Hold Timing

Min

SETUP & HOLD nMING WAVEFORM

RAMALE,
ALE

------J/

A BUS,
-SHE

4-73

Max

Unit

Condition

•

VLSI TECHNOLOGY, INC.
VL82C103A

RAMALE, BALE & IRQ1311MING

Symbol

Min

Parameter

Max

Unit

Condition

t25

RAMALE 10 MA Bus Oul

CL-150 pF

t26

ALE,. CPUHLDA 10 BALE Out

CL= 200 pF

t27

-ERROR, -BUSY287 10 IRQ13 Out

CL=50pF

128

-XBHE Valid from ALE

CL= 100 pF

RAMALE TIMING WAVEFORM

MAO-7

BALE llMING WAVEFORM

ALE,
CPUHLDA

BALE

_____________________________________________________

.~------126------~)\(~~

_______________________________

IRQ13 TIMING WAVEFORM

-ERROR~
-BUSY28~

IRQ13

___________________________________________________

.~------127------~)\(~~

______________________________

-XBHE TIMING WAVEFORM

\1....-_-

ALE

-XBHE

4-74

•

VLSI TECHNOLOGY, INC.
VL82C103A

AC TESTING -INPUT, OUTPUT WAVEFORM

OUTPUT~

INPUT

3.5V

0.2 V

f_
-------,t<1::mT~lNffi
1 5V
.

AC TESTING - LOAD CIRCUIT
DEVICE UNDER TEST

CL*

·· c apacitance.
"Includes scope and Jig

AC TESTING - LOAD VALUES
Test Pin

CL(pF)

32, 34-38, 40-43, 45-48, 50-53, 55

200

57-64,66

150

67-74, 76-83

100
75

84,30

4-75

VLSI TECHNOLOGY, INC.
VL82C103A
ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature
Storage Temperature

O·C to +70·C
-65.C to + 150.C

Supply Voltage to
Ground Potential

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

-0.5 V to 7.0 V

Applied Input
-0.5 V to +7.0 V

Voltage
Power Dissipation

500mW

DC CHARACTERISTICS:

TA = o·c to +70·C, VDD = 5 V ± 5%, VSS = 0 V

Symbol

Parameter

Min

VOH

Output High Voltage

2.4

Max

Unit

Condition

IOH =-3.3 mA

VOL1

Output Low Voltage

0.45

IOL = 8 mA, Notes 1 & 3

VOL2

Output Low Voltage

0.45

IOL = 20 mA, Notes 2 & 3

VIH

Input High Voltage

VIL

Input Low Voltage

-0.5

VIHC

Input High Voltage

3.8

VILC

Input Low Voltage

-0.5

Output Capacitance

Input Capacitance

CIO

Input/Output Capacitance

ILOL

Three-state Leakage Current

III

Input Leakage Current

ICC

Power Supply Current

VDD + 0.5

2.0

0.8
VDD+0.5

-100
-10

V
V
V

ALE,RAMALE

0.6

ALE, RAMALE

100
10

JJA
JJA

Notes: 1. Pins 57-64, 66-74, and 76-83.
2. Pins 32, 34-38, 40-43, 45-48, and 50-53, 55.
3. Output low current on all other outputs not mentioned in Note 1 or 2 have IOL (max) - 2 mAo

4-76

•

VLSI TECHNOLOGY, INC.
VL82C104
PC/AT·COMPATIBLE DATA BUFFER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The V182C104 PC/AT-Compatible Data
Buffer provides a 16-bit CPU data bus
VO as well as 40 buffered drivers. The
buffered drivers consist of 16 bidirectional system data bus drivers, each
capable of sinking 20 mA (50 'LS loads)
of current; eight bidirectional peripheral
bus drivers, each capable of sinking 8
rnA (20 'LS loads) of current; and 16
memory data bus drivers, each capable
of sinking 8 mA (20 'LS loads) of
current. The VL82C104 also generates
the parity error signal for the system.

• Completely performs data buffer
function in IBM PC/AT-compatible
systems
• Replaces several buffers, latches and
other logic devices
• Supports up to 12 MHz system clock
• Device is available as ·cores" for
user-specific designs
• Designed in CMOS for low power
consumption

BLOCK DIAGRAM

ORDER INFORMATION

00-07

OT/-R

-..-

OIR

ENABLE

-OENlO

f-c

--"'

SDO-S07

LATCH

f- SEl

- """"f- f-

ClK

~ B

-MOBEN

MDO-M07

OIR
ENABLE

MOPOUTO

MOPINO
Pdt

-XMEMR

fXOATADIR
AEN

B
A
OIR
ENABLE

XDO-X07

~ PARITY
ERROR

-PARERROR

PAREN

I.,. A

Soa-5015

ENABLE

GATE245

......- .. A

OIR
-OENHI - - - < ENABLE
-XBHE

OIR

01R245

08-015

Package
Plastic Leaded Chip
Carrier (PLCC)

Note: Operating temperature range is
O·C to +70·C.

XAO -<

Part
Number
VL82C104-QC

BUFFER

CNTLOFF

The device is manufactured with VLSl's
advanced high-perforrnance CMOS
process and is available in a JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
Vl82C104 is part of the PC/ATcompatible chip sets available from
VLSI. Please refer to the Selector
Guide in the front of this manual.

A ...-

OIR
ENABLE

PARITY

'--<
MOPOUT1

4-77

M08-M015

MOPINl

•

VLSI TECHNOLOGY, INC.
VL82C104

PIN DIAGRAM

014
07
015

•

84 83 82 81 80 79 78

76 75

X01

XOO

VSS

-XMEMR

M015

CNTLOFF

M014

-DENLO

M013

-DENHI

M012

01R245

M011

GATE245

M010

M09

VL 82C104

TOP VIEW

OT/-R
-MOBEN

M08

-PARERROR

VSS

XAO

M07

-XBHE

M06

MOPOUTO

M05

MOPOUT1

M04

MOPINO

M03

MOPIN1

M02

XOATAOIR

M01

AEN

MOO

PAREN

VOO

34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

S07

S05

VSS

S02

SOO

4-78

SOB

S010

VSS

S013

S015

•

VLSI TECHNOLOGY, INC.
VL82C104

SIGNAL DESCRIPTIONS
Signal
Type

Signal
Description

Signal
Name

Pin
Number

CNTLOFF

CNTLOFF - This input is used as a.clock to latch the current data on the
low byte of the system data bus. Data is latched on the rising edge of
CNTLOFF and is independent of the status of DT/-R, XAO, or -DENLO.

DTI-R

Data Transmit (high)/Receive (low) - This input is a signal from the
82C288. It establishes the direction of data flow to or from the system data
bus.

-DENLO

Data Enable Low - An active low input that enables a low byte data transfer
on the CPU data bus low byte transceiver.

XAO

Peripheral Address Bus Bit 0 - This is the LSB of the peripheral address
bus. The signal is used throughout the system to indicate low or high byte
data transfers. It is used to enable the low byte memory data transceiver
and to select latched or immediate data out of the CPU low byte bus
transceiver. It is also used to enable low byte parity checking.

-MDBEN

Memory Data Bus Enable - An active low input that is used to set the
direction of the memory data bus transceiver. -MDBEN = 0 indicates a
memory write cycle while -MDBEN = 1 is a memory read cycle.

XDATADIR

Transceiver Data Direction - This input is used to select the direction of the
peripheral data bus transceiver. XDATADIR = 0 indicates a DMA write to
the system data bus while XDATADIR = 1 is used for a DMA read from the
system data bus.

AEN

Address Enable - An active high input that is used to disable the DMA data
bus transceiver while the DMA controller is using the peripheral data bus
for address information.

DIR245

Direction 245 - An input control signal used to set the direction of the high/
low system data bus transceiver. This is used for high to low, or low to
high data byte moves.

GATE245

Gate 245 - An active low input that enables the highl10w system data
transceiver.

-DENHI

Data Enable High - An active low input that enables a high byte data
transfer on the CPU data bus high byte transceiver.

-XBHE

Transfer Bus High Enable - An active low that indicates a transfer of data
on the upper byte of the memory data bus. It is used to enable the high
byte memory data tranceiver and to enable high byte parity checking.

-XMEMR

Memory Read Enable - An active low input signal that indicates when a
memory read cycle is occurring. It is used to disable the MDPOUTx
signals during a memory write and to latch in the detected parity error
signal during a memory read.

MDPOUTO

Memory Data Parity Out 0 - An active high input that is the output of the
stored memory parity data. It is checked for parity errors with the low byte
of data read from memory.

MDPOUT1

Memory Data Parity Out 1 - An active high input that is the output of the
stored memory parity data. It is checked for parity errors with the high byte
of data read from memory.

MDPINO

Memory Data Parity In 0 - An active high output that is the parity input to
the system board memory. It is generated from the current low byte data
on the memory data bus.

4-79

•

VLSI TECHNOLOGY, INC.
VL82C104

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

MDPIN1

Memory Data Parity In 1 - An active high output that is the parity input to
the system board memory. It is generated from the current high byte data
on the memory data bus.

PAREN

-PARERROR

Parity Error - An active low output that is used to indicate that a memory
parity error has occurred. This signal is latched by -XMEMR and is valid
until the next memory access.

Parity Enable - This active high input is used to enable the parity data latch.
It is used to prevent false parity errors when ROM memory access ooeur.

MDO-MD15

55-62,64-71

DRAM Memory Data bus bits 0-15 - These are I/O signals.

XDO-XD7

73-80

Peripheral Data Bus Bits 0-7 -ItO's used to control the coprocessor, keyboard, ROM memory and the DMA controllers.

00-015

82,84,2,4,
7,9,11,13
83,1,3,5,8
10,12,14

CPU Data Bus Bits 0-15 - This is a bidirectional bus controlled by the
DT/-R input.

SDO-SD15

42-39, 37-34
44-47,49-52

System Data Bus Bits 0-15 - These are I/O signals.

VDD

43,54,81

System Power: 5 V

VSS

6,33,38,48
53,63,72

System Ground

FUNCTIONAL DESCRIPTION
The VL82C1 04 is part of a five chip set
which together perform all of the onboard logic required to construct an IBM
PC/AT-compatible system. The PC/ATCompatible Data Buffer replaces
several bus transceivers and a CPU
lower byte data latch located within the
PC/AT-type system.
The primary function of the Data Buffer
is to multiplex the 80286 microprocessor data lines 00-015 to the system
data bus SOO-S015, the peripheral data
bus XD-X017 and the memory data bus
MDO-MD15. This is accomplished
through six sets of 8-bit wide data
multiplexors. The lower data byte of the
CPU data bus transceiver has a byte
wide register which is clocked by the
rising edge of CNTLOFF. The data is
latched in the direction from the System
Data Bus to the CPU Oata bus only.
XAO is used to control data flow to the

CPU Data Bus. When XAO = 0, real
time data is passed to the CPU data
bus. When XAO = 1, latched data is
passed to the CPU Data Bus. The six
groups of transceivers can be seen in
the block diagram of the device. The
data parity encoder/decoder logic is
also located within this device. All data
present upon the memory data bus
passes through the parity logic. The
outputs of the parity encoder/decoders,
MDPINO and MDPIN1, are enabled via
PAREN to prevent decoding a ROM
access and are gated with -XMEMR.
The -PARERROR signal is fed back to
the Memory Controller chip where it is
gated with other logic to produce the
NMI signal for the 80286.
The logic controlling the bus transceivers has been optimized for speed and
as such there are no provisions to
prevent internal bus collisions. In a

4-80

standard PC/ATtype application using
the full VL82CPCAT chip set this is not
a problem as the control signals which
enable the transceivers are decoded in
such a fashion as to prevent this from
happening. In the case where only the
VL82C104 is used care must be taken
as to ensure that the control signals will
not cause an internal bus collision.
From the block diagram it can be seen
that every bus transceiver has an A and
B 110 port. The OIR input to the
transceiver controls the direction of data
flow through the transceiver. A high (1)
input into the OIR pin causes data to
flow from A to B. A low (0) causes data
to flow from B to A. Alltransceiver
enables are low true causing the output
of the particular transceiver to be active.

•

VLSI TECHNOLOGY, INC.
VL82C104

AC CHARACTERISTICS:

TA = o·c to +70·C, VDD

=5 V ±5%, VSS = 0 V

DATA BUS 110 MODE TIMING
Symbol

Parameter

Min

Max

Unit

Condition

SO Bus In to MO Bus Out

Cl=lOOpF

SO Bus In to 0 Bus Out

Cl=50pF

SO Bus In to XO Bus Out

Cl=lOOpF

SO Bus In to MOPINO and MOPINl Out

Cl=50pF

o Bus In to MO Bus Out
o Bus In to SO Bus Out
o Bus In to XO Bus Out
o Bus In to MOPINO and MOPINl Out

Cl= 100 pF

Clm 200 pF

Cla 100 pF

Cl=50pF

MO Bus In to 0 Bus Out

Cl=50pF

tlO

MO Bus In to SO Bus Out

Cl= 200 pF

tll

MO Bus In to XO Bus Out

Cl= 100 pF

t12

XO Bus In to 0 Bus Out

Cl=50pF

t13

XO Bus In to SO Bus Out

Cl= 200 pF

t14

XO Bus In to MO Bus Out

Cl= 100 pF

t15

XD Bus In to MOPINO. MOPINl Out

Cl = 50 pF. Note

t6
t7

Note:

This function is not available in a standard PC/AT system. It is specified here because the system can be configured to
accommodate this function. although it is not tested for.

DATA BUS I/O MODE TIMING WAVEFORMS
System Data Bus Timing Waveform
SO BUS

~V
---1 \.

...

MOBUS

...

Jf\.

o BUS

...

·\V
Jf\.
•
\,/
JI\.

XOBUS

...
MOPINO
MOPIN1

·\V

•
\,/

J\.
4-81

•

VLSI TECHNOLOGY, INC.
VL82C104

DATA BUS 1/0 MODE TIMING WAVEFORMS (Coni.)
CPU Data Bus Input TIming Waveform

DBUS

---1 [\

...

.
\V

MDBUS

Ir\.

l..o

SDBUS

XDBUS

...

\V
1[\

1[\

...

MDPINO
MDPIN1

Ir\.

Memory Data Bus Inpul Timing Waveform

MDBUS

---1[\

DBUS

...-

1[\

t10

...

SDBUS

XDBUS

1[\

t11

\V
1[\

4-82

•

VLSI TECHNOLOGY, INC.
VL82C104

DATA BUS 1/0 MODE TIMING WAVEFORMS (Cont.)
Peripheral Data Bus Input Timing Waveform
XDBUS

--./ 1\

t12

\/
/ \

DBUS

t13

t14

MDBUS

t15

MDPINO,
MDPIN1
Nota:

\V
/ 1\

SDBUS

..
..
\
/

V
1\

\
/

V
i\

NOTE

This function is not available in a standard PC/AT system. It is specified here because the system can be configured to
accommodate this function, although it is not tested for.

LOW BYTE TO HIGH BYTE CONVERSION MODE TIMING
Symbol

Parameter

Max

Unit

t16

SD Low to SD High Data Out

Cl = 200 pF

t17

SD Low to D Bus High Data Out

Cl=50pF

t18

SD Low to MD Bus High Data Out

Cl=100pF

Min

LOW BYTE TO HIGH BYTE CONVERSION TIMING WAVEFORM
SDBUS
lOW

--.I \

t16

SDBUS

\/
/\

HIGH

......

t17

DBUS

.....

....
MDBUS

t18

\/
/ \
4·83

Condition

•

VLSI TECHNOLOGY, INC.
VL82C104

XAO BUS MODE TIMING
Symbol

Parameter

Max

Unit

Condition

t19

XAO to D Bus Data Out

CL=50pF

t20

XAO to MD Bus Low Byte Out to High Z

t21

XAO to MD Bus Low Byte Out from High Z

Min

XAO BUS TIMING WAVEFORM
XAO

...

-1

•

t19

DBUS

11\
t20

MDBUS
LOW BYTE

XAO

LOW BYTE

..
\
/

HIGHZ

~.-

•

MDBUS
LOW BYTE

t21

HIGHZ

MEMORY READ MODE TIMING
Symbol

Parameter

Min

t22

-XMEMR High to -PARERROR Out

tSU23

Setup PAREN to -XMEMR High

Max

Unit

Condition

CL.50pF

MEMORY READ MODE TIMING WAVEFORM
-XMEMR

--.l

.....
t - - - t 2 2 - - - - - l..
~
-PARERROR

PAREN
tSU23 _ _-.t

-XMEMR

4-84

•

VLSI TECHNOLOGY, INC.
VL82C104

AC TESnNG -INPUT, OUTPUT WAVEFORM

INPUT

3.5V

0.2V

----r~'----*_1.5V
~ TESTPOINTS--~""
AC

AC TESnNG - LOAD CIRCUIT

DEVICE UNDER TEST

CL'

'Includes scope and jig capacitance.

AC TESnNG - LOAD VALUES

Test Pin

CL(pF)

34-37, 39--42, 44-47, 49-52

200

55-62, 64-71, 73-80

100

1-5,7-14,23,28-29

4-85

•

VLSI TECHNOLOGY, INC.
VL82C104

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

0·Cto+70·C

Storage Temperature

-65·C to + 150·C

Supply Voltage to
Ground Potential

-0.5 V to +7.0 V

Applied Input
Voltage

-0.5 V to +7.0 V

Power Dissipation

indicated in this data sheet is not
implied. Exposure to absolute maximum
rating conditions for extended periods
may affect device reliability.

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

500mW

DC CHARACTERISTICS:

TA =o·c to +70·C, VDD =5.0 V ±5%, VSS =0 V

Symbol

Parameter

Min

VOH

Output High Voltage

2.4

Max

Unit

VOL1

Output Low Voltage

0.45

VOL2

Output Low Voltage

0.45

VIH

Input High Voltage

2.0

VIL

Input Low Voltage

-0.5

VIHC

Input High Voltage

3.8

VILC

Input Low Voltage

-0.5

Output Capacitance

Input Capacitance

CIO

Input/Output Capacitance

ILOL

Three-state Leakage Current

III

Input Leakage Current

ICC

Power Supply Current

VDD + 0.5
0.8
VDD + 0.5
0.6

Condition

IOH=-3.3 mA

IOL - 8 mA, Notes 1 & 3

IOL = 20 mA, Notes 2 & 3

V
V
V

CNTLOFF

-100

100

I1A

-10

!LA

100

Notes: 1. Pins 55-62, 64-71, and 73-80.
2. Pins 34-37, 39-42, 44-47, and 49-52.
3. Output low current on all other outputs not mentioned in Note 1 or 2 have IOL (max) = 2 mAo

4-86

•

VLSI TECHNOLOGY, INC.
VL82C201
PC/AT-COMPATIBLE SYSTEM CONTROLLER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The VL82C201 PC/AT-Compatible
System Controller replaces an 82C284
Clock Controller and an 82C288 Bus
Controller (both are used in '286-based
systems), an 82C84A Clock Generator
and Driver, two PAL16L8 devices (used
for memory decode), and approximately
30 other less complex integrated
circuits used as wait state logic. The
device accepts a user supplied
PROCCLK or generates its own using
an internal clock modulation circuit. It

• Replaces 36 integrated circuits on the
PC/AT-type board
• Supports 20 MHz system clock
• Device is available as "cores· for
user-specific designs
• Sink 24 mA on slot driver outputs
• Designed in CMOS for low power
consumption

BLOCK DIAGRAM

also accepts a 14.318 MHz crystal to
control the video clock and supplies
reset and clock signals to the I/O slots.
The device is manufactured with VLSI's
advanced high-performance CMOS
process and is available in a JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
VL82C201 is part of the PC/ATcompatible chip sets available from
VLSI. Please refer to the Selector
Guide in the front of this manual.

ORDER INFORMATION

•
EN~~ --------~lof----,.I--MO~'L?~~OR

PROCCLK

}

POWERGOOD}
SWRST
XTAL1(1)
XTAL1(2)
PROCCLKIN

CLOCK
GENERATION
AND READY
CONTROL

MHZ7

~119

-ENAS
READY

-SO} -

-81
AO·A1

BUS
CONTROL

62288

BUS
CONTROL
Mi-lO }
CPUHLDA
-ROMCS

-WSO
-REFRESH}
IOCHRDY

WAIT
STATE
LOGIC

XA3.}

XA5-XA9

-lOW
{-lOR
-MEMR
-MEMW
-INTA

-8MEMW

BUFFER

~MEMR
~MEMW
~IOR
~IOW

~~~~~~ I

-REFEN

-IOC~;: }

-BUSY267
-ERROR

CAS
-ERAMW

-MEMR

-MEMCS16
-MASTER

-AEN2 }
-AEN1

RAS

BUS
COMMANDS

rARDYEN

RAMWRWT

-OENLO
-OENHI
ALE
RAMALE

I-

-LMEGCS

ROMWTST}
RAMRDWT

{-~

RESET
-READY
SYSCLK

6284
62284

...
DATA
CONVERSION

{DIAm
GATE245
CNTLOFF
SAO
-OMMEN

DMA
CONTROL

~BHE

J
-,

287 AND
PERIPHERAL
CONTROL

{

RESET287
-NPCS
-PPICS
XDATADIR
-BUSY266

4-87

Part Number

System
Clock
Fraq.

Package

VL82C201-160C
VL82C201-1601

16 MHz

Plastic Leaded Chip
Carrier (PLCC)

VL82C201-200C
VL82C201-2001

20 MHz

Plastic Leaded Chip
Carrier (PLCC)

Nota: Operating temperature:
OC = O·C to +70·C
01 = -40·C to +85·C.

•

VLSI TECHNOLOGY, INC.
VL82C201

PIN DIAGRAM
A1

Ml-IO

-81

10
XTAL
CHRDY 1(2)

-I?~S ~X!r l-so 1.r~~A ~1~L
1

-WSO
-ROMCS
F16

PROC
CLKIN

Ipg~D1

1 VSS
2

•
1

VDD

RAM
WRWT

XA5

XA7

FCLK 1 XA31 XA6 1 XAS

84 83 82 81 80 79 78 77 76 75
74

XA9

-AEN1

-AEN2
-REFRESH

ENMODL

-LMEGCS

ROMWTST

-MEMCS16

-MASTER

-ERROR

-ERAMW

RAS

VL82C201

RAMRDWT
-BUSY287
OSC

TOP VIEW

MHZ119
-XBHE

CAS

-NPCS

-PPICS

RESET287

XDATADIR

-DENHI

CNTLOFF

-DENLO

GATE245

VSS

DT/-R

DIR245

ALE

RAMALE

-REFEN

-DMAAEN

-ENAS

VDD

VOD

~~$~~~~~~~«~~Q~~~~~

RES j-XMEM\ -X
CPU
R
lOR
-XMEM
W

-X
lOW

\-MEM \-lOW \-BUSY
W
286
VSS

-MEM
R

-lOR

RE \ SYS \ SAO \-8MEM\ MHZ7
SET
CLK
R

-INTA

4-88

PROC
CLK

VSS -8MEM -READY
W

•

VLSI TECHNOLOGY, INC.
VL82C201

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Type

Signal
DescrIption

XTAL1(2)

Crystal 1 Output 2 - A parallel resonant fundamental mode crystal should
be attached across XTAL 1(1) and XTAL1 (2). This is the crystal output.
Typical load - 33 pF.

XTAL1(1)

Crystal 1 Input 1 - A parallel resonant fundamental mode crystal should be
attached across XTAL1(1) and XTAL1 (2). This input drives the internal
oscillator and determines the frequency of OSC. Typical load = 33 pF.

IOCHRDY

110 Channel Ready - This input is generated by an 110 device. When low, it
indicates a not ready condition. This is used to extend memory or 110
accesses by inserting wait states. When high, this signal allows normal
completion of a memory or 110 access.

CPUHLDA

CPU Bus Hold - This input indicates ownership of the local CPU bus.
When high, this signal indicates that the CPU has three-stated its bus
drivers in response to a hold request. When low, it indicates that the CPU
bus drivers are active.

-51

Status 1 - An active low input/pull-up from the CPU in combination with -50
and MI-IO determine which type of bus cycle to initiate. -51 going active
indicates a read cycle unless -50 also goes active. Both status inputs
active indicate an interrupt acknowledge cycle or halt/shutdown operation.

-50

Status 0 - An active low inputlpull-up from the CPU in combination with -51
and MI-IO determine which type of bus cycle to initiate. -50 going active
indicates a write cycle unless -51 also goes active. Both status inputs
active indicate an interrupt acknowledge cycle or a halt/shutdown operation.

M/-IO

Memory or 110 Select - This input indicates the type of bus cycle to be
performed. If high, a memory cycle or halt/shutdown cycle is started. If
low, then an 110 cycle or an interrupt acknowledge cycle will be initiated.

SWRST

This active high input signal will force a CPU reset when a low to high
transition is detected.

CPU Address Bus Bit 1 - This input is used to determine when to initiate a
shutdown operation. A shutdown will be started when A1 is low, MI-IO is
high, and both -50 and -51 go low.

-IOCS16

110 Chip Select 16 - This active low input is generated by an 110 device for
a 16-bit data bus access. This signal is used to determine the number of
wait states and whether data conversion is necessary for 110 accesses.

-WSO

Wait State 0 - This active low input signal should have an external pull-up.
A peripheral device can pull this signal low to force a zero wait state cycle.

-ROMCS

ROM Chip Select - This active low input is a signal generated from
-I..CSOROM and -I..CS1 ROM and is used to indicate a ROM memory
access.

F16

This input indicates an on-board memory access. It is used along with
-ROMCS to determine whether a memory access is to ROM, on-board
RAM or off-board RAM. It is also used to inhibit a command delay for
memory accesses.

CPU Address Bus Bit 0 - This input is used to generate enable signals for
the data bus transceivers.

ENMODL

Enable Modulation - Is an input used to control the clock modulator on the
VL82C201. When this signal is high, normal clock modulation can occur.
When ENMODL is low, clock modulation is disabled and PROCCLK is
forced to 1/4 the frequency of FCLK.
4-89

•

VLSI TECHNOWGY, INC.
VL82C201

SIGNAL DESCRIPTIONS (Cont.)
Pin

Signal
Name

Number

Signal
Type

Signal
Description

ROMWTST

ROM Wait State· This input is used to select the desired number of ROM
access wait states. ROMWTST low indicates two waits while ROMWTST
high indicates three wait states.

RAMROWT

RAM Read Wait State - This input indicates the number of wait states to be
used for on-board RAM read cycles. A high indicates one wait state reads
while a low indicates zero wait state reads. RAMROWT also controls the
timing on RAS and CAS during memory read cycles.

-BUSY287

Busy - A busy status input that is asserted by the 80287 to indicate that it is
currently executing a command.

OSC

MHZ119

o
o

-XBHE

Transfer Byte High Enable - This active low I/O is used to enable -DENHI
and determine when a 16-bit to 8-bit data conversion is needed. -XBHE is
driven as an output during all OMA cycles. It is forced low if -AEN2 is
active and it is driven as the inversion of SAO if -AEN1 is active.

-NPCS

Numerical Processor Chip Select· This active low output is the chip select
for the 80287 numerical processor.

RESET287

Rese1287 - This ective high output is used to reset the 80287 numerical
processor.

-OENHI

Data Bus Enable High - This active low output is used to enable the data
bus transceiver on the high byte of the data bus.

-DENLO

Data Bus Enable Low - This active low output is used to enable the data
bus transceiver on the low byte of the data bus.

OTl-R

Data TransmitlReceive - An output that determines the data direction to
and from the local data bus. A high indicates a write bus cycle and a low
indicates a read bus cycle. OT/-R is high when no bus cycle is active.
-OENLO and -DENHI are always inactive when OT/-R changes state.

ALE

Address Latch Enable - A positive edge output that controls the address
latches which hold the address during a bus cycle. ALE is not issued for a
halt bus cycle.

RAMALE

RAMALE is used to latch RAM address buffers. It is forced high at the end
of any bus cycle. This allows the address for the next bus cycle to be
passed to the system memory sooner than the ALE signal. RAMALE will
go back low at the end of the status cycle for any bus cycle to latch the
memory address until the end of the bus cycle.

-OMAAEN

OMA Address Enable - An active low output that is active whenever an VO
device is making a OMA access to the system memory. It will go low
anytime -AEN1 or -AEN2 go low.

RESCPU

Reset CPU - This is the active high output system reset for the CPU. It is
generated from POWERGOOO, SWRST or when a shut down status is
generated by the CPU.

-XMEMW

Peripheral Bus Memory Write· An active low I/O that is the memory write
command to and from the peripheral bus. This pin is configured as an
output when -OMAAEN is high and an input when -OMMEN is low.

-XMEMR

Peripheral Bus Memory Read - An active low I/O that is the memory read
command to and from the peripheral bus. This pin is configured as an
output when -DMAAEN is high and an input when -OMAAEN is low.

This is the buffered output of the XTAL 1 oscillator.
This output is the OSC output clock divided by 12.

4-90

•

VLSI TECHNOLOGY, INC.
VL82C201

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

-XIOW

Peripheral Bus InputlOutput Write - This active low 110 is the read command to and from the peripheral bus. This pin is configured as an output
when -OMMEN is high and an input when -OMMEN is low.

-XIOR

110

Peripheral Bus InputlOutput Read - This active low 110 is the read command to and from the peripheral bus. This pin is configured as an output
when -OMMEN is high and an input when -OMMEN is low.

-MEMW

110

Memory Write - This active low 110 is the memory wr~e command from the
bus controller portion of the chip. It will be three-stated when CPUHLDA is
asserted and CNTLOFF is inactive.

-MEMR

Memory Read - This active low 110 is the memory read command from the
bus controller portion of the chip. It will be three-stated when CPUHLOA is
asserted and CNTLOFF is inactive. -MEMR is also active during a refresh
cycle.

-lOW

Input/Output Write - This is the active low VO write command from the bus
controller portion of the chip. It will be three-stated when CPUHLDA is
asserted and CNTLOFF is inactive.

-lOR

110

Input/Output Read - This is the active low 110 read command from the bus
controller portion of the chip. It will be three-stated when CPUHLDA is
asserted and CNTLOFF is inactive.

-BUSY286

Processor Extension Busy - This output goes to the -BUSY input of the
80286. Hpulled low, this signal stops the 80286 program execution on all
WAIT and some ESC instructions until it returns inactive (high).

-INTA

Interrupt Acknowledge - This active low output that is three-stated is the
interrupt acknowledge command from the bus controller portion of the chip.
It will be three-stated when CPUHLDA is asserted and CNTLOFF is
inactive.

RESET

Reset - This active high output signal is the system reset generated from a
POWERGOOO. It is synchronized to PROCCLKIN.

PROCCLK

Processor Clock - This is the output of the on-board clock modulator.
When the clock modulator is enabled the frequency of PROCCLK will be
FCLK12 except for I/O cycles, off-board memory cycles, and DMA cycles.
The frequency of PROCCLK will switch to FCLKl4 during those cycles.

SYSCLK

System Clock - This output is the main system clock. It is equal to half the
PROCCLKIN frequency and is synchronized to the processor's T-states.

SAO

110

System Address Bus Bit 0 - SAO is driven as an output anytime CPUHLDA
is low, and will be an input at all other times. It is used internally to control
the data bus enable signals and to determine the state of -XBHE during 8bit DMA cycles.

-SMEMW

Memory Write - An active low three-stated output that is the memory write
command to the expansion bus. Drives when -LMEGCS is low.

-SMEMR

Memory Read - An active low three-stated output that is the memory read
command to the expansion bus. Drives when -LMEGCS is low.

-READY

Ready - When active, indicates that the current bus cycle is to be completed. -READY is an open drain output requiring an external pull-up
resistor.

MHZ?

This output is the OSC output divided by 2. It is generated to provide a
fixed clock frequency for the keyboard controller and 80287 coprocessor.

4-91

•

VLSI TECHNOLOGY, INC.
VL82C201

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

-ENAS

Enable Address Strobe - This active low output is used to enable the
address strobe on the real time clock device. It will go low the first time
-80 is asserted after a system reset.

-REFEN

Refresh Enable - An active low output. It will be asserted when a refresh
cycle is needed for the DRAMs. It is used to clock a refresh counter which
provides addresses during the refresh cycle.

DIR245

Direction 245 - This output determines the direction of the data bus
transceiver which does conversions from high to low byte or low to high
byte for 8-bit peripherals.

GATE245

Gate 245 - This output enables the data bus transceiver which does
conversions from high to low byte or low to high byte for 8-bit peripherals.

CNTLOFF

Control Off - This output is used to latch the lower byte data bus during
high byte to low byte conversions.

XDATADIR

-PPICS

Programmable Peripheral Interface Chip Select - This active low output is a
decode of the XA bus. The decode is for address space 060 to 09F.
-PPICS can only go active if CPUHLDA is low or -MASTER is low.

CAS

This is the output used to control the timing of the CAS signal to the
DRAMs. CAS will go active (high) one clock cycle after RAS if a zero wait
state cycle is selected, or 1 112 clock cycles if a one wait state cycle is
selected. CAS will go back low at the end of the bus cycle.

RAS

This is the output used to control the timing of the row address strobe
signal to the DRAMs. RAS will go high during the second phase of any
memory status cycle. It will go back low two clock cycles later if a zero wait
state cycle is selected or three clocks later if a one wait state cycle is
selected.

-ERAMW

Early RAM Write - It is used to get an early write enable signal to the
DRAMs to support zero wait state write cycles. It will go low during the
second phase of any memory write status cycle. -ERAMW returns high at
the end of the bus cycle.

-ERROR

Error - An error status input from the 80287. This reflects the ES bit of the
80287 status word and indicates that an unmasked error condition exists.

-MASTER

Master - This active low input is asserted by devices on the expansion bus
to get control of the bus.

-MEMCS16

Memory Chip Select 16 - A low on this pin indicates that the off-board
memory is 16-bits wide.

-LMEGCS

Lower Megabyte Chip Select - This input indicates that the lower memory
address space (0-1 megabyte) is selected. When low, it enables the threestate drivers on -8MEMR and -8MEMW.

-REFRESH

Refresh - This active low input is used to initiate a refresh cycle for the
dynamic RAMs.

This active high output will go active during the second phase of a CPU
bus cycle following the Ts state.

4-92

•

VLSI TECHNOLOGY, INC.
VL82C201

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

-AEN2

Address Enable 2 - This active low input is from the DMA controllers and is
used to generate -DMMEN, control-XBHE, and disable the clock
modulator.

-AEN1

Address Enable 1 - This active low input is from the DMA controllers and is
used to generate -DMMEN, control -XBHE, and disable the clock
modulator.

XAS-XA9

78-74

Peripheral Address Bus Bits 5-9 - These inputs are used to decode chip
select and reset signals for the coprocessor.

XA3

Peripheral Address Bus Bit 3 - This input is used in control of the coprocessor reset and chip select signals.

RAMWRWT

RAM Write Wait State - Indicates the number of wait states to be used for
on-board RAM write cycles. A high indicates one wait state writes while a
low indicates zero wait state writes. RAMWRWT also controls the timing
on RAS and CAS during memory write cycles.

FCLK

This is the fast clock input to the clock modulator circuit. It should be
driven from an external crystal oscillator at twice the frequency of the
desired PROCCLK output.

POWERGOOD

System Power-on Reset - This input signal indicates that power to the
board is stable. A Schmitt-trigger input is used so the input can be
connected directly to an RC network.

PROCCLKIN

This is the main clock input to the VL82C201 and should be connected to
the Signal that drives the 80286 CLK pin. It can be connected to the
PROCCLK output (Pin 46) if the internal clock modulator is used or can be
connected to an externally generated clock.

VDD

32,54,82

System Power: 5 V

VSS

1,27,38,
48,59

System Ground

Signal
Type

Signal
Description

FUNCTIONAL DESCRIPTION
The VL82C201 chip generates all the
major clocks for an AT-compatible
system design along with the command
and control signals for both the system
and peripheral buses. It interfaces with
the CPU to determine the type of bus
cycle to execute and generates the
-READY signal to indicate that the
current bus cycle can be terminated. It
also contains logic to make conversions
between 16-bit and 8-bit data accesses.
Finally, it generates some of the control
signals necessary for the 80287
Numerical Processor.
CLOCK GENERATION
The VL82C201 contains a clock
modulator to control the processor clock
signal and an oscillator to generate the
OSC, MHZ7 and MHZ119 signals.

The oscillator is designed to use an
external parallel resonant fundamental
mode crystal. A 14.318 MHz crystal
should be used to maintain compatibility
and connected as shown in Figure 1.
The variable capacitor is optional. It is
used to make slight adjustments to the
output frequency. The OSC output is
generated directly from this oscillator for
the system bus. The MHZ? output is
the oscillator frequency divided by 2
and can be used to drive the 8042
keyboard controller. The MHZ119
output is the oscillator frequency divided
by 12 and is used by the Peripheral
Controller chip.
The clock modulator portion of the
VL82C201 is designed to gracefully
switch the speed of the processor clock

4-93

based on which type of bus cycle is
going to be performed. The FCLK input
to the modulator should be driven from
an external crystal oscillator at a
frequency that is two times the desired
PROCCLK frequency. The clock
modulator can be disabled by driving
the input signal ENMODL low. When
the clock modulator is disabled the
PROCCLK output will be 1/4 the
frequency of the FCLK input.
The clock modulator circuit uses the
CPU status signals -SO, -S1, and
M/-IO along with the signal F16 from
the Memory Controller chip to determine which type of bus cycle is needed.
Normally the PROCCLK output will be
running at 112 the frequency of FCLK.
When the processor signals an 110

•

VLSI TECHNOLOGY, INC.
VL82C201

cycle, INTA cycle or off-board memory
cycle the modulator will switch the
processor clock to 1/4 the frequency of
FCLK. The transition is made such that
during the second phase of the status
cycle PROCCLK will be three FCLK
cycles long and all subsequent
PROCCLK cycles will be four FCLK
cycles long. If the bus cycle is an offboard memory access, the clock
modulator will sample -READY to
determine when to return PROCCLK to
112 the frequency of FCLK. If the bus
cycle is an 110 access, the clock
modulator will remain at the slow rate
until a memory cycle occurs. The clock
modulator will then speed up when it
samples -READY at the end of the
memory cycle.
The inputs -AEN1 and -AEN2 are also
sampled by the clock modulator and
PROCCLK is slowed to FLCKl4 anytime
either of these signals are active.
To reduce clock skew and increase
flexibility for the user the PROCCLKIN
input is provided. This input should be
connected to the same signal that is
used to drive the CLK input of the
processor. This guarantees that the
VL82C201 is referenced to the same
clock as the processor with no internal
skews. The user can connect this input
to the PROCCLK output if the clock
modulator is to be used. PROCCLKIN
can also be driven from a user supplied
source if the clock modulator is not
needed.
The SYSCLK output is derived from the
PROCCLKIN input and is 112 the
frequency of PROCCLKIN .. SYSCLK.is
held low during reset and will not begin
running until the first bus cycle is
initiated by the CPU. It will then make
its first low to high transition on the
falling edge of PROCCLKIN during the
start of the first TC cycle (see timing
waveforms). This synchronization is
done to ensure that the system clock is
synchronized with the 80286 internal
system clock.
RESET AND READY CONTROL
The 82284 megacell along with some
support logic is used to control the
system reset signals and -READY
signal for the CPU. Two basic reset
signals are generated for the system.

FIGURE 1. OSCILLATOR CIRCUIT

30 pF

14.318 MHz

II---t~F5-i'r:::;';R~--iIII-I--I""---10-p-F--I

XTAL1(1}

XTAL1 (2)

RESET is the system reset out of the
82284 megacell and is synchronized to
PROCCLK. It is generated from the
POWERGOOD input signal. The
POWERGOOD pin has a Schmitttrigger input so that an RC network can
be used to generate the reset signals.
RESCPU, the other reset output, is
connected to the input on the 80286
processor. RESCPU will be active
anytime RESET Is active. It can also be
generated from two other possible
sources. The first is the SWRST input
from the Memory Controller chip. A low
to high transition is detected on this pin.
When this occurs, RESCPU will go
active after a minimum delay of 6.72
microseconds. RESCPU will also be
generated if a shutdown command is
issued from the CPU. In either case,
the RESCPU output will pulse high for
16 PROCCLKIN cycles.
The -READY output is synchronized
and controlled by the 82284 megacell.
-READY is an open drain output
connected directly to the CPU and
requires an external pull-up resistor. A
resistor value of 330 n is recommended. Bus cycle length is controlled
by the -READY output. Bus cycles are
lengthened and shortened internally by
the VL82C201 depending on the type of
bus cycle being executed. The length
of a bus cycle can be shortened
externally by pulling the -WSO input low
or lengthened by pulling the lOCH ROY
input low. If IOCHRDY is pulled low the
bus cycle will not be terminated until
lOCH ROY is returned high.
COMMAND AND BUS CONTROL
The VL82C201 contains an 82288 bus
controller megacell to generate all the
bus command and control signals. The
82288 megacell generates the -MEMR,
-MEMW, -lOR, and -lOW command
signals and the DTI-R control signal.
4-94

The DEN output from the megacell is
split into -DENLO and -DENHI for
enables on the upper and lower bytes of
the data bus. Internal circuitry is used
to insert one PROCCLK cycle of
command delay for all 110 cycles and
off-board 8-bit memory cycles. Refer to
the 82288 data sheet for complete operation of the 82288 megacell.
OPERATING MODES
The VL82C201 operates in four basic
modes. First, and most common, is the
CPU mode. This mode is active any
time the input CPUHLDA is low. While
in CPU mode the VL82C201 will drive
both the CMD (-MEMR, -MEMW,
-lOR, -lOW) bus and XCMD
(-XMEMR, -XMEMW, -XIOR, -XIOW)
bus. While in CPU mode, the outputs
-MEMR, -MEMW, -SMEMR, and
-5MEMW are disabled from going low
for on-board memory accesses. They
will go low for off-board memory cycles
only. The outputs -XMEMR and
-XMEMW will still go active for any
memory cycle.
The other modes can only be active
when CPUHLDA is high. Then the
VL82C201 can be in DMA mode,
-MASTER mode, or REFRESH mode.
If the inputs -AEN1 or -AEN2 are
active, the VL82C201 is in DMA mode
and the CMD bus is driven from the
inputs on the XCMD bus. If the
-MASTER input is active, the
VL82C201 is in -MASTER mode and
the XCMD bus is driven from the inputs
on the CMD bus. When the
-REFRESH mode is active the -MEMR
output will be driven to generate the
refresh for the DRAMs but -MEMW,
-lOR, and -lOW will be in a high impedance state. The XCMD pins will be
configured as outputs driving whatever
value is on the CMD pins.

•

VLSI TECHNOLOGY, INC.

SYSTEM BOARD MEMORY
CONTROL
Timing control for the system board
memory is controlled by four signals:
RAMALE, RAS, CAS, and -ERAMW.
RAMALE is used by both the Memory
Controller and Address Buffer chips to
latch in current address values for
generating address and chip select
signals for the DRAMs. The RAMALE
signal is forced high during reset to
pass through the first address from the
CPU. At the end of the first status cycle
RAMALE will go low and will remain low
until-READY is sampled low. After the
first memory access RAMALE will
always go high at the end of any bus
cycle, when -READY is sampled low.
RAMALE will go low latching in the
current address at the end of any status
cycle. This configuration will leave the
RAMALE signal high during CPUHLDA
cycles to allow addresses and chip
select decodes to pass directly to the
DRAMs for DMA or -MASTER accesses.
The RAS signal is used to generate the
timing control for the DRAMs. It is an
active high signal and should be gated
w~h the RASO and RAS1 chip select
signals out of the Memory Controller
chip to generate the RAS signals to the
DRAMs. The timing of RAS is controlled by the RAMWRWT, RAMRDWT,
and CPUHLDA inputs.
The VL82C201 samples RAMRDWT
during memory read cycles and
RAMWRWT during memory wr~e
cycles to determine whether the cycle
should be a zero or one wait state
access. A low on these inputs selects
zero wait states, while a high will select
one wait state. Whenever CPUHLDA is
low (inactive) RAS will always go active
during the second phase of any
memory access status cycle. If the
current memory access should be a
zero wait state cycle, RAS will return
low two PROCCLKIN cycles later. For
a one wait state access, RAS will return
low three PROCCLKIN cycles later.
This is done to generate timing that will
meet specifications for the slower
DRAMs typically used in one wa~ state
designs. When CPUHLDA is high, the
memory control logic samples the
inputs on -XMEMR and -XMEMW for

VL82C201

DMA cycles, or -MEMR and -MEMW
for -MASTER cycles. RAS will go high
on the first falling edge of PROCCLKIN
when any memory read or wr~e
command is sampled active. RAS will
return low two or three PROCCLKIN
cycles later depending on the states of
RAMRDWT and RAMWRWT as
described above for the CPU accesses.
The CAS signal is also used to generate timing control for the DRAMs. It is
an active high signal and should be
gated with CASO and CAS1 chip select
signals out of the Memory Controller
chip to generate the CAS signals to the
DRAMs. The timing of CAS is controlled by the RAMWRWT and
RAMRDWT inputs.
RAMRDWT and RAMWRWT function
the same as described above for the
RAS signal to determine whether the
current memory access should be zero
or one wa~ states. For a zero wait state
access CAS will go active one
PROCCLKIN clock cycle after RAS
goes active. During a one wait state
access CAS will go active 1 112 PROCCLKIN clock cycles after RAS goes
active. This is done to allow more row
address hold time for the slower
DRAMs that can be used in a one wait
state system. CAS goes inactive (low)
at the same time for both zero and one
wait state accesses. When CPUHLDA
is low, CAS will return inactive at the
end of the bus cycle when -READY is
sampled low. When CPUHLDA is high,
CAS will return inactive on the falling
edge of the first PROCCLKIN cycle
when all the memory read and write
commands are sampled inactive.
-ERAMW is an early write signal for the
DRAMs to make sure the write signal is
present before CAS. It will go low
during the second phase of any
memory write status cycle. -ERAMW
returns high at the end of the bus cycle.
Note: Although RAMRDWT and
RAMWRWT can be changed dynamically for each memory cycle, care must
be taken to never allow RAMRDWT to
be high and RAMWRWT to be low at
the same time for more than 60 ns.
This results in zero wait state write
cycles and one wait state read cycles.
This was determined to be an unrealistic operating mode and is used to put

4-95

the VL82C201 into a test mode that will
disrupt normal system operation.

WAiTSTATELOGIC
Wait states can be controlled from a
number of different sources within the
VL82C201. It is internally programmed
to generate the wait states shown in
Table 1 based on the appropriate input
signals.
Any of these programmed values can
be overridden by the inputs IOCHRDY
and -WSO. IOCHRDY can be used to
extend any bus cycle. When
IOCHRDY is pulled low the current bus
cycle will be maintained until it is
returned high. A low on -WSO will
terminate the current bus cycle as soon
as it is recognized by the VL82C201.
These inputs need only be pulled low to
modify the values shown in Table 1.
IOCHRDY and -WSO are mutually
exclusive and only one of them should
be pulled low within a given bus cycle.
Refer to the timing diagrams for setup
and hold requirements.

REFRESH CONTROL
The VL82C201 contains circuitry to
control a refresh cycle in an AT-compatible design. When the input
-REFRESH is pulled low, the
VL82C201 will issue -REFEN to clock
the refresh counter and enable the
refresh addresses onto the memory
address bus. It will also issue a -MEMR
command. For correct operation
-REFRESH should not be pulled low
unless CPUHLDA is active.

DATA CONVERSION
A state machine for controlling the
conversion between 16-bit data accesses from the CPU and 8-bit peripherals is contained in the VL82C201.
This state machine will generate the
control signals DIR245, GATE245, and
CNTLOFF to the Data Buffer chip to
route the data correctly for both read
and write conversions. The conversion
logic will signal the wait state logic to
hold the CPU and start the read/write of
the low data byte. It will then latch the
low byte for a read operation, negate
the bus control signals, switch SAO to a
high, and then perform the read/write
operation for the high data byte. The
VL82C201 also uses the DIR245 and
GATE245 during 8-bit DMA cycles to
route the lower byte on the system data

•

VLSI TECHNOLOGY, INC.

bus to or from the high or low byte of
on-board memory.
NUMERICAL PROCESSOR AND
PERIPHERAL CONTROL
The VL82C201 generates a reset signal
and chip select signal for the 80287
Numerical Processor. The signal
RESET287 is used to reset the 80287
and can be activated by a system reset

VL82C201

or an
write to address OFl hex.
-NPCS is used as a chip select for the
80287 and is decoded at addresses
OF8-0FF hex.
The VL82C201 also controls the
-BUSY286 signal sent to the 80286
from the Numerical Processor. The
80287 will assert -BUSY287 whenever
it is performing a task. This signal is

passed to the 80286 by asserting the
-BUSY286 output. Normally
-BUSY286 will follow -BUSY287.
However, if the -ERROR signal is
asserted while the -BUSY287 signal is
active, the -BUSY286 output will be
latched low and will remain active until
cleared by an I/O write cycle to address
OFO hex or OFl hex.

TABLE 1. WAIT STATES
Access Type

RAM
RDWT

RAM
WRWT

WTST

ROM
F16

-MEM
CS16

INTACycles

8-Bit ItO

l6-Bit 110

-10

Number
of Walts

Command
Delay

Yes

C516

Off-board 8-Bit Memory

Off-board l6-Bit Memory

On-board ROM Read

On-board RAM Write

On-board RAM Read

4-96

•

VLSI TECHNOLOGY, INC.
VL82C201

AC CHARACTERISTICS:

=QC: O°C to +70°C, QI: -4Q°C to +85°C, VDD =5 V ±5%, VSS =0 V

CPU MODE TIMiING
16 MHz
Min

20 MHz

Max

Min

Max

Symbol

Parameter

UnH

PROCCLKIN Period

PROCCLKIN High Pulse Width

PROCCLKIN Low Pulse Width

PROCCLK Rise Time

1.0 V 10 3.6 V, CL

PROCCLK Fall Time

3.6 V to 1.0 V, CL ~ 75 pF

FCLK Period

FCLK High Pulse Widlh

FCLK Low Pulse Width

OSC RiselFall Time

1010

MHZ7 from OSC Delay

1011

MHZ119 from OSC Delay

1012

PROCCLK from FCLK Delay

ISU13

-SO, -51 to PROCCLKIN Setup Time

IH14

-SO, -51 from PROCCLKIN Hold Time

tSU15

M/-IO to PROCCLKIN Selup Time

CondHlon

tH16

M/-IO from PROCCLKIN Hold Time

tSU17

F16 to PROCCLKIN Setup Time

tH18

F16 from PROCCLKIN Hold Time

ISU19

POWERGOOD to PROCCLKIN
SelupTime

Nole 1

IH20

POWERGOOD 10 PROCCLKIN
Hold Time

Note 1

1021

RESET from PROCCLKIN Delay

1022

RESCPU from PROCCLKIN Delay

1023

SYSCLK from PROCCLKIN Delay

1024

-ENAS from PROCCLKIN Delay

M/-IO, A110 -50, -51 Setup Time

tSU26

SWRST 10 PROCCLKIN Selup Time

t27

SWRST Pulse Width

1028

ALE from PROCCLKIN Delay

75 pF

tSU25

Nole 1

Notes: 1. POWERGOOD and SWRST are asynchronous inpuls. This specification is given for lesting purposes only, 10 assure
recognition at a specific PROCCLKIN edge.

4-97

•

VLSI TECHNOLOGY, INC.
VL82C201

CPU MODE nMING (Con\.)
20 MHz

16 MHz

Max

Min

Max

Unit

Condition

Symbol

Parameter

tD29

DT/-R Low from PROCCLKIN Delay

tD30

DT/-R High from PROCCLKIN Delay

tD31

-DENLO, -DENHI Low from
PROCCLKIN Delay

Write Cycles

tD32

-DENLO, -DENHI Low from
PROCCLKIN Delay

Read Cycles

tD33

-DENLO, -DENHI High from
PROCCLKIN Delay

Read and Write Cycles

1034

-READY Active from PROCCLKIN
Delay

1035

-READY Inactive from PROCCLKIN
Delay

1036

XDATADIR from PROCCLKIN Delay

tSU37

-IOCS16 to PROCCLKIN Setup Time

tH38

-IOCS 16 from PROCCLKIN Hold Time

tSU39

IOCHRDY to PROCCLKIN Setup Time

tH40

IOCHRDY from PROCCLKIN Hold
Time

1041

-CMD, -XCMD, -SCMD from
PROCCLKIN Delay

tSU42

-WSO to PROCCLKIN Setup Time

tH43

5
35

ns
35

-WSO from PROCCLKIN Hold Time

tSU44

-MEMCS16 to PROCCLKIN Setup
Time

tH45

-MEMCS16 from PROCCLKIN Hold
Time

tSU46

AO to PROCCLKIN Setup Time

1047

SAO from PROCCLKIN Delay

tSU48

-XBHE to PROCCLKIN Setup Time

tD49

-DENLO, -DENHI from PROCCLKIN
Delay

tD50

-CMD, -XCMD, -SCMD from
PROCCLKIN Delay

tD51

Q1 from PROCCLKIN Delay

Note 2

Note 3

25
15
Note 4
Note 4

Notes: 2. -READY is an open drain output and requires a pull-up resistor that pulls the signal high within two PROCCLKIN
cycles. A 330 n resistor is recommended. This specification for -READY inactive indicates when the VL82C201
stops driving the output. It does not indicate that -READY has reached a certain voltage level.
3. -CMD refers to the signal pins -MEMR, -MEMW, -lOR, and -lOW. -SCMD refers to the signal pins -SMEMR and
-SMEMW. -XCMD refers to the signal pins -XMEMR, -XMEMW, -XIOR, and -XIOW.
4.

Caused by CNTLOFF during 16 to 8 bit conversions.

4-98

VLSI TECHNOLOGY, INC.
VL82C201
CPU MODE TIMING (Cont.)
16 MHz
Symbol

Parameter

t052

CNTLOFF from PROCCLKiN Delay

Min

Max

20 MHz
Min

Max

Unit

t053

DiR245 from PROCCLKIN Delay

t054

GATE245 from PROCCLKIN Delay

tSU55

-ROMCS to PROCCLKIN Setup Time

tH56

-ROMCS from PROCCLKIN Hold Time

tSU57

ROMWTST to PROCCLKiN Setup Time

tH58

ROMWTST from PROCCLKIN Hold
Time

tSU59

RAMRDWT. RAMWRWT to
PROCCLKIN Setup Time

tH60

RAMRDWT. RAMWRWT from
PROCCLKIN Hold Time

t061

RAMALE from PROCCLKIN Delay

t062

-ERAMW from PROCCLKIN Delay

Condition

t063

RAS from PROCCLKIN Delay

t064

CAS High from PROCCLKIN Low Delay

o Wait State Only

tD65

CAS High from PROCCLKIN High
Delay

1 Wait State Only

t066

CAS Low from PROCCLKIN Low Delay

o and 1 Wait State

t067

-INTA from PROCCLKIN Delay

t068

-BUSY286 from -BUSY287 Delay

tH69

-ERROR form -BUSY287 Hold Time

tSU70

-ERROR to -BUSY287 Setup Time

t071

-BUSY286 from -lOW Delay

t072

RESET287 from -lOW Delay

tSU73

XA Input to -lOW Setup Time

tH74

XA Inputs from -lOW Hold Time

tD75

XA Inputs to -NPCS Delay

t076

XA Inputs to -PPICS Delay

4-99

•

VLSI TECHNOLOGY, INC.
VL82C201

DMA MODE TIMING
20 MHz

16 MHz
Symbol

Parameter

1079

-OMMEN from -AEN1. -AEN2 Delay

1080

XOATAOIR from -XIOR Delay

Min

Max

Unit

Max

Min

t081

-CMO. -SCMO from -XCMD Delay

1082

-XBHE from SAO Delay

1083

DIR245 from -XMEMR Delay

1084

GATE245 from -XMEMR. -XMEMW.
or -XIOR Delay

Note:

Condition

Note

During -AEN2. -XBHE is low. During -AEN1. -XBHE follows SAO inverted.

BUS MASTER MODE TIMING
16 MHz
Symbol

Parameter

1085

-XCMD from -CMD Delay

t086

-SCMD from -CMD Delay

1087

XDATADIR from -lOR Delay

Min

20 MHz

Max

Min

Max

Unit

CondHlon

REFRESH MODE TIMING
16 MHz

20 MHz

Symbol

Parameter

tSUSS

-REFRESH to PROCCLKIN Setup TiITll

tOS9

-REFEN from PROCCLKIN Delay

t090

-MEMR. -XMEMR. -SMEMR from
PROCCLKIN Delay

Min

Max

Min

Max

Unit

CondHlon

During -REFRESH

MEMORY CONTROL TIMING DURING DMA OR MASTER MODES
16 MHz

20 MHz

Symbol

Parameter

tSU91

-MEMR. -XMEMR. -MEMW.
-XMEMW 10 PROCCLKIN Setup Time

tH92

-MEMR. -XMEMR. -MEMW.
-XMEMW to PROCCLKIN Hold Time

tSU93

F16 to -MEMR. -XMEMR Setup Time

tH94

F16 from -MEMR. -XMEMR Hold Time

t095

DT/-R from -MEMR. -XMEMR Delay

tD96

-DENLO from SAO Delay

tD97

-DENHI from -XBHE Delay

Min

Max

Min

Max

4-100

Unit

Condition

•

VLSI TECHNOLOGY, INC.
VL82C201

PROCCLK TIMING WAVEFORMS

PROCCLKIN

CLOCK MODULATION WAVEFORM

F16
tSU15~

M/-IO

-SO,-Sl

ALE

_____________~~r------------------~r-'_______________________

-READY

Note:

Timing is shown for an off-board memory cycle. The same clock transitions will occur if MHO is sampled low, regardless
the state of F16.

CRYSTAL DERIVED CLOCK WAVEFORMS

OSC

MHZ7

MHZl19

4-101

•

VLSI TECHNOLOGY, INC.
VL82C201

RESET AND CLOCK TIMING WAVEFORMS

PROCCLKIN
tH20

~-~--~~-~----//-----~//~--

RESET
~--+--+--4--------//----------~//_+_--

A1, M/-IO

-51,-50

tSU13

//-+---

-ENAS
----------~-//-+---

SYSCLK

RESCPU

________~c:~__tD_~

_________________

PROCCLKIN

~_tS_U_2_6

SWRST
(NOTE)
SYSCLK

RESCPU

Note:

//----------~~/~

____________________

//----~------~

--------------------------~//---~

POWERGOOD and SWRST are asynchronous inputs. This specification is given for testing purposes only, to
assure recognition at a specific PROCCLKIN edge.

4-102

•

VLSI TECHNOLOGY, INC.
VL82C201

110 TIMING WAVEFORM

-------8 BIT------_~

t . - - - - - 16 B I T - - - -. . . .

XTW

-4~I-TC-II~-

--t~t--- CYCLES--t~t_-_t~t_

(4 MIN)
PROCCLKIN

-80,-81

r-~----+//---r--;--+------

ALE

~r_----+//--~--+-~-----

~-----+//--~--+-~~

DTI-R

-DENLO,
-DENHI

'"+-----+// --+---II--t---'
~r_----+//--;---~

-READY
-lOR,
-XIOR
~--+//---r----~

-lOW,
-XIOW

r-----~----_+//---r-----+-----tD36

--.I

XDATADIR

tD36

-.J )--_
~--+//--~----~

r-------------~//---r------------

-IOCS16

IOCHRDY
NOTE 2
Notes: 1. -READY is an open drain output and requires a pull-up resistor that pulls the signal high within two PROCCLK cycles.
A 300 n resistor is recommended.
2.

IOCHRDY is sampled for the first time in the middle of the first wa~ state. If it is sampled high, 16-bit bus cycles will
terminate with only one wait state. From then on IOCHRDY is sampled at the end of each wait state cycle. When
IOCHRDY is sampled high, the bus cycle will terminate one wait state cycle later.
For 8-bit bus cycles IOCHRDY is sampled for the first time at the end of the third wait state cycle. If it is sampled
high, the bus cycle will terminate in four wait states. Otherwise, the bus cycle will be extended untillOCHRDY is
sampled high.

4-103

•

VLSI TECHNOLOGY, INC.
VL82C201

OFF-BOARD MEMORY llM1NG WAVEFORM

----------8

14--16 BIT--. . . .
NOTE 1

BIT--------I~

2TW
CYCLES
PROCCLKIN

-50,-51

ALE
DTI-R

-DENLO,
-DENHI
-MEMR,
-XMEMR,
-SMEMR

t041

-MEMW,
-XMEMW,
-5MEMW

-wso
F16
tSU44
-MEMCS16

Notes: 1. This 16-bit cycle is shown as zero wait states terminated by the -WSO input. Normal off-board memory cycles are
one wait state.
2. A command delay is shown on the a-bit write cycle. Command delays will exist for both reads and writes on the a bit
cycles. A command delay is not generated for 16-bit reads or writes.

4-104

•

VLSI TECHNOLOGY, INC.
VL82C201

CONVERSION nMING WAVEFORM

4TW

3TW
CYCLES

CYCLES

PROCCLKIN

ALE

~~~~.~-------+--+-~------~----//-------+-~-------

AO
t047

SAO

-XBHE

r---~---//------r-+-------

~~~LJLJ---//------+~------+----

-DENLO,
-DENHI

~__~N~O~T~E~3__+--r~~~r-
NOTE 2

IOR,IOW,
MEMR,
MEMW

/ /'-----t--lf---'
t051

//--------If-------

CNTLOFF

DIR245

GATE245

-------r----~~//------------------~

-MEMCS16

F16

-IOCS16

~~~~~~~~---t~:~~~~7-----------------------------7~~~t------------~~~~t~H~3rr.8

Notes: 1. The first transition shown here is for write cycles. The -DEN signals will go active one PROCCLKIN cycle later for
read cycles.
2.

The first transition shown here is for read cycles. The -DEN signals will go inactive one PROCCLKIN cycle later for
write cycles.

3. -OENLO will not go active during the second half of a conversion cycle for I/O write or memory write commands.
4.

DIR245 goes low for a write cycle. It will remain high for read cycles.

4-105

•

VLSI TECHNOLOGY, INC.
VL82C201

ON-BOARD MEMORY TIMING

o WAIT RAM

2 WAITROM

1 WAIT RAM

"'TS __ ~TC-'" ~ TS"'~ TC-... . . . TW", ~". ___ m
PROCCLKIN

-Vl.Fu\) V1)"",L(\.Flfl)"" W'.FVlrF
~

tSU1 3

-50,-51
tSU

17-.1 ~
wgj

F16

ROMWTST
tSU59 _
RAMROWT,
RAMWRWT
(NOTE)

H
\

1061
RAMALE

r--

...--- r

t- tH~:!I

RAS

OT/-R

...

tH58 ....

f! r- t-

1--- j4- 1062

\
~1063-...

t06t

j.- 10631

-... I+-

-...

Ib66

1065

j4-

-(VOH)

-OENLO,
-OENHI

\
1034-...

Note:

I*- tD62

1064-... j4" ';66~

1032-...

-REAOY

j..

---

tSU59

-...
t- ___

•

tSU57 ~
tH60

tH56 ___

1061

-ERAMW

+t ~

tSU55

\
tH1l

1-'" ~ 1-'" ~

1063 -...

tH1j

~ ~
/

ISU55
-ROMCS

CAS

__ ~__

-----'/

1033

-1

~33~l\1031

-...
/

j+-I-'"
/

1032

t033-'"

1034

Although RAMRDWT and RAMWRWT can be changed dynamically for each memory cycle, care must be taken to never
allow RAMRDWT to be high and RAMWRWT to be low at the same time for more than 60 ns. This results in zero wait
state write cycles and one wait state read cycles. This was determined to be an unrealistic operating mode and is used
to put the VL82C201 into a test mode that will dis[upt normal system operation.

4-106

•

VLSI TECHNOLOGY, INC.
VL82C201

INTA TIMING WAVEFORM

PROCCLKIN

ALE

-INTA

DT/-R

-DENLO

XDATADIR

-;r'-_ ____...Jr=

___
to_36_-.__

t036

NUMERICAL PROCESSOR INTERFACE TIMING WAVEFORM

\'----------',
tD71

-lOW
tSU73

XAS-9,
XA3, XAO
RESET287

-----------------1

-NPCS

-PPICS

4-107

•

VLSI TECHNOLOGY, INC.
VL82C201

DMA MODE TIMING WAVEFORMS
-AEN1,
-AEN2

-OMMEN

-XIOR,
-XIOW

XOATAOIR

~\--:079~----~~79t
\~----------------=I
---------r'L_______I~

-lOR.
-lOW

SAO

-XBHE

--~

\~------

~~82)L--

-XMEMW,
-XMEMR

t083
OIR245

-MEMW,
--'
-MEMR, _ _ _ _ _ _ _ _ _ _ _ _ _ _ t081-.!
_- - . \
-SMEMW,
-SMEMR

tD81

)J--------

\..._ _ __

-XMEMW,
-XMEMR
-XIOR

GATE245

4-108

•

VLSI TECHNOLOGY, INC.
VL82C201

BUS MASTER MODE TIMING WAVEFORM
-MEMR,
-MEMW

-XMEMR,
-XMEMW

-SMEMR,
-SMEMW

t08S

tOBS

j+- tOBS
'--___....1

-lOR,
-lOW
tOBS

-XIOR,
-XIOW

tOB7

XOATAOIR

Note:

tOBS

XOATAOIR goes low only for -lOR when XA9, XAB are low and -NPCS is not active.

REFRESH TIMING WAVEFORM
PROCCLKIN

SYSCLK

-REFRESH

-REFEN

-MEMR,
-XMEMR,
-SMEMR

---'r-

_ _ _ _ _ _----\t'--_tO_9_0_ _ _

4·109

t090

•

VLSI TECHNOLOGY, INC.
VL82C201

MEMORY CONTROL TIMING WAVEFORMS DURING DMA OR MASTER MODES
PROCCLKIN
-MEMR.
-XMEMR
-MEMW.
-XMEMW
RAMRDWT.
RAMWRWT

RAS

CAS

-ERAMW

BUS CONTROL TIMING WAVEFORMS DURING DMA OR MASTER MODES

F16
-MEMR.
-XMEMR

l,,"93~
\

~Ui

f4=.,,'j

OT/-R
SAO

\
j.-t096-+j

-DENLO

-XBHE

-J

/.-t09S-.j
\

(:-1-

\
\

f-- i-

j.-t097-+j
-OENHI

W97

4-110

•

VLSI TECHNOLOGY, INC.
VL82C201

AC TESTING -INPUT, OUTPUT WAVEFORM

INPUT

OUTPUT~

3.SV -----rfx15V

*_1.SV

~ TESTPOINTS--~""

0.2 V

+5.0 V

AC TESTING - LOAD CIRCUIT

DEVICE UNDER TEST

CL·

·Includes scope and jig capacitance.

AC TESTING - LOAD VALUES
Test Pin
20, 39-42, 45, 47, 49-51

CL(pF)
200

46,52

21-26,28-31,33-37,43,
44, 53, 55-58, 60-66

4-111

Test Pin

R1 (0)

600

34-37, 39-42, 44,
SO,51

10K

VLSI TECHNOLOGY, INC.
VL82C201
ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

QC - O·C to + 70·C

QI = -40·C to +85·C
Storage Temperature

-65·C to + 1500C

Supply Voltage to
Ground Potential

-0.5 V to +7.0 V

Applied Input
Voltage

-0.5 Vto +7.0 V

Power Dissipation

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

indicated in this data sheet is not
implied. Exposure to absolute maximum
rating conditions for extended periods
may affect device reliability.

500mW

DC CHARACTERISTICS:

= QC:

o·c to +70·C, QI:

Symbol

Parameter

Min

VOH

Output High Voltage

2.4

VOl1

Output Low Voltage

VOL2

Output Low Voltage

-40·C to +8S·C, VDD
Max

Unit

= S V ±5%, VSS = 0 V

Condition

IOH=-3.3mA

0.45

IOL = 24 mA, Note 1

0.45

IOL = 8 mA, Note 2

Except POWERGOOD, PROCCLKIN

VDD+0.5

VIH

Input High Voltage

2.0

VIL

Input Low Voltage

-0.5

VIHS

Input High Voltage

4.0

VDD + 0.5

POWERGOOD, Schmitt-trigger

VIHC

Input High Voltage

3.8

VDD+0.5

PROCCLKIN

VILC

Input Low Voltage

-0.5

0.6

PROCCLKIN

0.8

Output Capacitance

Input Capacitance

CIO

InpuUOutput Capacitance

ILOL

Three-state Leakage Current

-100

100

III

Input Leakage Current

-10

!1A
!1A

Except -S1, -SO, XTAL 1(1)

IllS

Input Leakage Current

-0.5

0.01

/LA

-S1, -SO, Note 3

ILiX

Input Leakage Current

-40

!1A

XTAl1(1)

ICC

Power Supply Current

Note 4

Notes: 1.
2.
3.
4.

Pins 20, 39-42, 45, 47, 49-52.
All other pins.
-S1 and -SO have small pull-up resistors to VDD and source up to 0.5 mA when pulled low.
Inputs VSS or VDD, outputs are not loaded.

4-112

•

VLSI TECHNOLOGY, INC.
VL82C202
PC/AT-COMPATIBLE MEMORY CONTROLLER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The VL82C202 PC/AT-Compatible
Memory Controller generates the row
and column decodes necessary to
support the dynamic RAMs used in
PC/AT-type systems. In addition, the
device allows six motherboard memory
options for the user, from S12K-bytes
up to a full8M-byte system. In addition,
the Vl82C202 provides the chip select
for the ROM and RAM memory, and
drives the system's speaker. The
optional Shadow RAM feature allows up
to 384K-bytes of memory space to be

• Completely performs memory control
function in IBM PC/AT-<:ampatible
systems
Replaces 20 integrated circuits on
PC/AT-type motherboard
• Supports up to 20 MHz system clock
• Device is available as "cores' for
user-specific designs
• Designed in CMOS for low power
consumption

copied to and executed out of high
speed DRAM instead of slower
EPROM.
The device is manufactured with VLSl's
advanced high-performance CMOS
process and is available in a JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
VL82C202 is part of the PC/ATcompatible chip sets available from
VLSI. Please refer to the Selector
Guide in the front of this manual.

ORDER INFORMATION

BLOCK DIAGRAM

Part Number
A16·A23

1-......--------. SA17·
SA19

CPUA20

System
Clock
Freq.

Package

VL82C202-160C
VL82C202-1601

16MHz

Plastic Leaded Chip
Carrier (PLCC)

VL82C202-200C
VL82C202-2001

20 MHz

Plastic Leaded Chip
Carrier (PLCC)

CPUHLDA

Note: Operating temperature range:
OC = O·C to + 70·C
01 = --40·C to +8S·C.

ALE

-MASTER

1--+------_.-

AEN

HH--------.

F16

RAMALE

::~~~}
~~~~

MAS. MAD

~------------,

SHDWRAMMAP

~EN

-REFRESH}
ADDRSEL
_
REFBIT9
RESET
OUT2
Xf)O.XD7

{ CASO

'=======:::::;t=t;;===l1'n--'

RASl

CASl
-LMEGCS
{ -LCSOROM
-LCS1ROM

A200A~} ------------------t

FASTA20GATE
-SPKRDATA
SWRST

-IOCHCK}

...pA:E~~~

XAl·XA5
XA16 }
-PPICS

-ENAS
Ql

-li"':~=_=_=_=_=_~_-_-_-_-_-_-_-_--=~-.-:-IL-_-_-_-_-___-_-_-_-_____-_______
_
-~
..,~----------

CPUHLDA, -MASTER_

......- - - t D 1 6 - - -....
:

AEN

-ERAMW

r-CASO, CAS1

.....

-LCSxROM

tD17~

X
tD18-

..a.I

4-124

•

VLSI TECHNOLOGY, INC.
VL82C202

ADDRESS BUS TIMING
16 MHz
Min

20 MHz

Symbol

Parameter

Max

Min

Max

UnH

Condition

tD20

MA8, MA9 Delay from RAMALE

1021

MAS, MA9 Delay from ADDRSEL

Note

tD22

MAS Delay from REFBIT9

-REFRESH = 0

tSU23

A 16-A23 Setup to ALE, RAMALE

tH24

A16-A23 Hold

1025

XAO/SAO Delay

CL = 200 pF SAO,
CL = 100 pF XAO

1026

SA17-SA19

CL = 200 pF SAO,
CPUHLDA= 1,
-MASTER= 1

1027

SA17-SA19 Delay from ALE

CPUHLDA =0

A20 Delay

CL=50pF

1028
Note:

1021 delay may be derated by a factor of .04 nsJpF for heavier loads.

ADDRESS BUS TIMING WAVEFORMS
RAMALE

A16-A23

~~~====_tD_2_0~~~~_i~ .~------------------_

_________________

MA8, MA9

VALID ADDRESS

1C '==>k! •.------"~-=

ADDRSEL

1D2

MA8, MA9

VALID ADDRESS

r
-, r-

REFBIT9 (-REFRESH = 0)

ID22

MA8
Note:

tSU23 is specified with respect to the falling edge of RAMALE to guarantee the correct address decodes will be latched
in. tSU23 is shown with respect to the rising edge of RAMALE to show time required for address decodes such that
propagation delays 1020 and tD13 will be valid. The time does not have to be met with respect to the rising edge for
correct functionality.
4-125

•

VLSI TECHNOLOGY, INC.
VL82C202

ADDRESS BUS nMiNG WAVEFORMS (Cont.)

SAO (INPUT)

=====~~~~~~~~~-~~~~----t_D-25--:>k~______V_A_Ll______
D
__

(-OMMEN .. 1)

XAO (OUTPUT)
XAO (INPUT)

======~~~~~~~_~..:...~_~~~-_tD-~25--:>k---_-_-_-_-_-_-..,:V:A-L_I-_D -_-_-_-_-_-_

(-OMMEN .. 0)

SAO (OUTPUT)
A17-A19

_-_>K-=--I~====tD=26:::-_=-~~~-1-._==

---~~1~___
. t_D2_6~~~~~~~1__~V:A~LI~D__~~_______~
__>K_________- _-_-

SA17-SA19

---1

ALE
SA17-SA19

,,'--------

tD27--x!1__________________

(WITH CPUHLDA
~______
tD28--.. SK~
. ~_________
A20GATE,
CPUA20 0) __===============-=->K
A20 (OUTPUT)
a

4-126

•

VLSI TECHNOLOGY, INC.
VL82C202

MISCELLANEOUS INPUTnMlNG
16 MHz

Max

20 MHz

Symbol

Parameter

Min

Max

Unit

t26

Min High (Active) Time on RESET

100

t27

Min Low Time for -XMEMR

Condition

MISCELLANEOUS INPUT nMING WAVEFORMS
RESET
t26

-XMEMR
f=t27-t

FASTA20GATE nMING
16 MHz

Symbol

Parameter

Min

tD28

FASTA20GATE Delay from -XIOW

tD29

FASTA20GATE Delay from A20GATE

Max

20 MHz

Min

Max

Unit

Condition

I/O Write to Port A.
CL=50pF

CL=50pF

FASTA20GATE nMiNG WAVEFORMS
-XIOW

",-__~l.-tD28
r ~

FASTA20GATE

_ _ _ _ _ _ _ _ _ _ _ _ _~H>29~ - - - - - - - - A20GATE

4-127

•

VLSI TECHNOLOGY, INC.
VL82C202

AC TESTING -INPUT, OUTPUT WAVEFORM

INPUT

3.5V

0.2V

OUTWT~

~~'5V
~

AC TESTING - LOAD CIRCUIT

'k~1.5V

AC TEST

POINTS--~-'" ~

DEVICE UNDER TEST

[>-----.l
CL"

"'ncludes scope and jig capacitance.

AC TESTING - LOAD VALUES
Test Pin

CL(pF)

27,29,50,54,55

200

65,66

150

28,32-39

100

All Others

4-128

•

VLSI TECHNOLOGY, INC.
VL82C202

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

OC O·C to +70·C
01 = -40·C to +85·C

Storage Temperature -65·C to +150·C
Supply Voltage to
Ground Potential

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

indicated in this data sheet is not
implied. Exposure to ebsolute maximum
rating conditions for extended periods
may affect device reliability.

-0.5 V to +7.0 V

Applied Input
Voltage

-0.5 V to +7.0 V

Power Dissipation

500mW

DC CHARACTERISTICS:

TA:: QC; O·C to +70·C, QI; -40·C, to +85·C, VDD :: 5 V ±5%, VSS :: 0 V

Symbol

Parameter

Min

VOH

Output High Voltage

2.4

Max

Unit

Condition

IOH=-3.3 mA

VOU

Output Low Voltage

0.45

SAO, SA17-SA19, AEN,
CL = 200 pF, IOL = 20 mA

VOl2

Output Low Voltage

0.45

MAS, MA9, CL", 150 pF, IOL = S mA

VOL3

Output Low Voltage

0.45

F16, XAO, XDO-XD7, CL = 100 pF,
IOL=SmA

VOL4

Output Low Voltage

0.45

All Other Pins, CL = 50 pF, IOL = 2 mA

VIH

Input High Voltage

3.8

VIL

Input Low Voltage

-0.5

VIHC

Input High Voltage

2.0

VILC

Input Low Voltage

-0.5

Output CapaCitance

Input Capacitance

CIO

InpuVOutput Capacitance

ILOL

Three-state Leakage Current

III

Input Leakage Current

ICC

Power Supply Current

Note;

VDD + 0.5

ALE, RAMALE

All Other Pins

O.S

All Other Pins

0.6
VDD+0.5

-100

100

-10

f.lA
f.lA

Inputs = VSS or VDD, outputs are not loaded.

4-129

Note

•

VLSI TECHNOLOGY, INC.
VL82C202

NOTES:

4·130

•

VLSI TECHNOLOGY, INC.
VL82C203
PC/AT-COMPATIBLE ADDRESS BUFFER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The Vl82C203 PC/AT-Compatible
Address Buffer provides the system
with a 16-bit address bus input from the
CPU to 41 buffered drivers. The
buffered drivers consist of 17 bidirectional system bus drivers, each capable
of sinking 24 mA (60 'lS loads) of
current and driving 200 pF of capacitance on the backplane; 16 bidirectional
peripheral bus drivers, each capable of
sinking 8 mA (20 'lS loads) of current;
and eight memory bus drivers, also
capable of sinking 8 mA of current. Onchip refresh circuitry supports both

• Completely performs address buffer
function in IBM PC/AT-compatible
systems
• Replaces several buffers, latches and
other logic devices
Supports up to 20 MHz system clock
Device is available as "cores" for
user-specific designs
• Designed in CMOS for low power
consumption

BLOCK DIAGRAM
Al-A16

ALE
CPUHLDA

System
Clock

0
SAOSA16

LATCH
Al-A16
GATE
ENABLE

XA1XA16
CLR
9 BIT
COUNTER

-REFEN
MAOMA7

AOORSEL
-REFRESH
RAMALE

-BHE

The device is manufactured with VlSI's
advanced high-performance CMOS
process and is available in a JEDECstandard 84-pin plastic leaded chip
carrier (PlCC) package. The
Vl82C203 is part of the PC/ATcompatible chip sets available from
VlSI. Please refer to the Selector
Guide in the front of this manual.

ORDER INFORMATION

-OMMEN

RESET

256K-bit and 1M-bit DRAMs. The
Vl82C203 provides addressing for the
I/O slots as well as the system.

REFBIT9
BALE

fio;--I-.......---!.~
LATCH
-XBHE

GATEl
GATE2
ENABLE

-SBHE
-TEST-BUSY287 ------~~r;:D;;;:E-;::CO~O;:;;E;]1
-ERROR -------~,

1 - :- - - - - -. . .

IR013

4-131

Part Number

Freq.

Package

Vl82C203-16QC
Vl82C203-16Q1

16MHz

Plastic leaded Chip
Carrier (PlCC)

Vl82C203-200C
Vl82C203-2001

20 MHz

Plastic leaded Chip
Carrier (PlCC)

Note: Operating temperature range:
OC = O·C to + 70·C
01 = --40·C to +85·C.

•

VLSI TECHNOLOGY, INC.
VL82C203

PIN DIAGRAM

RAMALE

A10

A9
10

A11

-BHE

•

84 83 82 81 80 79 78 77 76 75
74

XA9

XA10

XA11

XA12

XA13

XA14

A8
A7

VL82C203

A3
A2
A1

TOP VIEW

VSS

XA15

XA16

-XBHE

VSS

ALE

MA7

CPUHLDA

MA6

-OMAAEN

MA5

-REFRESH

MA4

-REFEN

MA3

AOORSEL

MA2

RESET

MA1

-ERROR

MAO

REFBIT9

VOO

-TEST

BALE

-SBHE

VSS

~~~~~~~~~~"~~Q~~~~~

vss

SA15

SA16

SA13

SA14

VSS

SA12

SA10

SA11

SA8

SA9

4-132

VOO

SA7

SA6

SA5

SA4

VSS

SA3

SA2

SA1

53
SAO

•

VLSI TECHNOLOGY, INC.
VL82C203

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Type

Signal
Description

A1-A16

20-13,
9-2

CPU Address Bus Bits 1-16 - The lower 16 bits ofthe CPU address
bits. These are multiplexed to the system address bus for the slots SA 1SA16, the memory address bus MAO-MA7, and the peripheral address bus
XA1-XA16.

RAMALE

RAM Address Latch Enable - RAMALE is used to latch RAM address
buffers. lt is forced high at the end of any bus cycle. This allows the
address for the next bus cycle to be passed to the system memory sooner
than the ALE signal. RAMALE will go back low at the end of the status
cycle for any bus cycle to latch the memory address until the end of the bus
cycle. The memory address latches are open when RAMALE is in the high
state.

-BUSY287

Busy 287 - This active low input is asserted by the 80287 to indicate that it
is currenty executing a command.
..

-BHE

Bus High Enable - This is the active low input signal from the 80286 microprocessor which is used to indicate a transfer of data on the upper byte on
the data bus, 08-015.

ALE

Address Latch Enable - This positive edge input controls the address
latches which hold the address during a bus cycle. ALE is not issued for a
halt bus cycle. All latches are open when ALE is in the high state.

CPUHLDA

-DMAAEN

DMA Address Enable - This is an active low input which is active whenever
an 110 device is making a DMA access to the system memory.

-REFRESH

Refresh - An active low input which is used to initiate a refresh cycle for the
dynamic RAMs. It is used to clock a refresh counter which provides
addresses during the refresh cycle.

-REFEN

Refresh Enable - An active low input that will be asserted when a refresh
cycle is needed for the DRAMs.

ADDRSEL

Address Select - This is a multiplex select for the memory address bus
drivers. When ADDRSEL is low, the lower order address bits are selected.
When high, the high order address bits are selected.

RESET

Reset - This active high input signal is the system reset generated from a
POWERGOOD. lt is synchronized to PROCCLK and used to reset the
refresh counter.

-ERROR

Error - This is an active low input which indicates an error has occurred
within the 80287 coprocessor.

REFBIT9

Refresh Bit 9 - This is the MSB of the refresh counter. When used with the
Memory Controller chip a refresh address will be generated for 1M byte
DRAMs.

-TEST

Test - This is an active low input which is used to three-state all outputs of
the V182C203 device. This is for system level test where it is necessary to
overdrive the outputs of the VL82C203. When -TEST is low, all outputs
and bidirectional pins of the VL82C203 will be three-stated. This pin
should be pulled up via a 10K n pull-up resistor in a standard system
configuration.

4-133

•

VLSI TECHNOLOGY, INC.
VL82C203

SIGNAL DESCRIPTIONS (Cont.)
Signal

Signal

Name

Number

Type

Signal
Description

-SBHE

110

System Bus High Enable - This is the system I/O signal used to indicate
transfer of local data on the upper byte on the local data bus, D8-D15.
-SBHE is active low and will be in input mode during bus hold acknowledge.

SAO·SA16

53-50,48-45
43-40,38-34

System Address Bus Bits 0-16 - SAO will be active only during a refresh
cycle otherwise it will be three-stated (input mode).

BALE

Buffered Address Latch Enable - An active high output that is used to latch
valid addresses and memory decodes from the 80286. System addresses
SAO-SA16 are latched on the falling edge of BALE. During a DMA cycle
BALE is forced active high.

MAO-MA7

57-64

DRAM Memory Address Bus Bits 0-7· This 8-bit output is multiplexed
using ADDRSEL to give a full 16-bit address.

XA1-XA16

83-76,74-67

110

Peripheral Address Bus Bits 1-16 - These IlOs are used to control the
coprocessor, keyboard, ROM memory and the DMA controllers.

-XBHE

110

Transfer Byte High Enable - This is an active low 110 used to allow the
upper data byte to be transferred through the bus transceivers.

IRQ13

This is an active high output which indicates an error has occurred within
the 80287 coprocessor.

VDD

1,44,56

System Supply: 5 V

VSS

21,33,39
49,54,65,75

System Ground

FUNCTIONAL DESCRIPTION
The VL82C203 is part of a five chip set
which together perform all of the onboard logic required to construct an IBM
PC/AT·compatible system. The PC/AT·
Compatible Address Buffer replaces
several bus transceivers and address
data latches located within the PC/ATtype system. The DRAM refresh
circuitry is also located on this device.
The primary function of the Address
Buffer is to multiplex the 80286 microprocessor address lines (A1-A16) to the
system address bus (SAO-SA16), the
peripheral address bus (XA1-XA16),
and the memory address bus (MAOMA7). This is accomplished through
positive edge triggered latches and a
group of data multiplexers. The two
groups of latches can be seen in the
block diagram of the device. One set of
latches have their output enabled with
CPUHLDA and are gated with ALE.
This set of latches drive the SA and XA
bus outputs. Another parallel set of
latches are multiplexed into the MA

TABLE 1. INTERNAL BUS CONTROL DECODE
HLDA

-DMA
AEN

-REF
EN

MA -XBHE

CPU

-5BHE

I • Input Mode
O. Output Mode
X - Don'tCare

lines and are gated with RAMALE.
RAMALE is an early ALE signal. This
allows more setup time for the address
to be multiplexed to the DRAMs. If the
VL82C203 is not used in conjunction
with the other PC/AT-devices, RAMALE
and ALE should be wired together to
provide maximum PC/AT-compatibility.

4-134

The device also provides for address
flow between the SA, XA, and MA
buses and the -XBHE and -SBHE
signals. The -XBHE signal is gated
with the RAMALE input while the
-SBHE is gated with the ALE input.
This control flow is arbitrated with the
CPUHLDA, -DMAAEN, and -REFEN
inputs and is shown in Table 1.

•

VLSI TECHNOLOGY, INC.
VL82C203

Memory addresses are multiplexed
from the SA and A bus sources and
are controlled via the CPUHLDA.
-REFRESH. and ADDRSEL inputs.
The mapping and control is shown in
Table 2.
A 9-b~ refresh counter is provided on
this device. This allows support for
DRAMs of up to 1M bit in size. The
refresh counter is clocked on the rising
edge of the -REFRESH input. A
latched register inside the counter
latches in the current state of the
counter on the falling edge of -REFEN
and transfers this value to the internal
bus which routes to the SA and MA
bus outputs. The SAO output is
provided only for refresh purposes and
is driven only during this time. During
a refresh the SA and MA bus outputs
are driven from the output of the
refresh counter latch OO-OS. Refer to
Table 3 for the mapping of the refresh
counter to the bus lines.
Note that all SA bus lines are driven
during a refresh cycle. ADDRSEL is
not normally toggled during a refresh
cycle but is shown in Table 3 for completeness of the logic implementation.
The REFBIT9 signal is the
output
of the refresh counter. This is required
only for the refresh of 1M b~ DRAMs.

AC CHARACTERISTICS:

TABLE 2. MEMORY ADDRESS MAPPING
Mux Control Input
CPUHLDA

-REFRESH

MABus
ADDRSEL

MA7

MAO-MA6

SAS

SA1-SA7

SA16

SA9-SAI5

Al-A7

A16

A9-A15

x= Don't Care
TABLE 3. REFRESH ADDRESS MAPPING
MABus

Mux Control Input
CPU
HLDA

-REF
EN

AD DR
SEL

MA7

MAOMA6

The -TEST pin has been added to
enhance system level testing of the
VLS2CPCAT-I6/-20 chip sets. When
this pin is active (0). all outputs and bidirectional pins are placed in three-state.

TA = QC:

o·c to +70·C, QI:

SA Bus
SA9SA15

SAOSAS

01-07

OO-OS

This allows a board level test system to
overdrive outputs of the VLS2C203
without damage to the device. When
-TEST is active. the internal bus is
driven to the state of the system
address bus (SAO-SA 16).

-40·C to +85·C, VDD

=5 V ± 5%, VSS =0 V

CPU MODE llMING
20 MHz

16 MHz

Max

Unit

CPUHLDA to SA Bus High Z State

CPUHLDA to -5BHE from High Z to Valid Out

CPUHLDA to -5BHE High Z State

Symbol

Parameter

Min

CPUHLDA to SA Bus from High Z to Valid Add Out

t2
t3
t4

Max

Min

Condition

ALE to SA Bus Valid Address

CL= 200 pF

ALE to XA Bus Valid Address

CL~

ALE to -5BHE Bus Valid Address

CL = 200 pF

4-135

100 pF

•

VLSI TECHNOLOGY, INC.
VL82C203

CPU MODE TIMING WAVEFORMS

CPUHLDA

14---11 - - - - l..
VALID ADDRESS

HIGHZ

SA BUS

HIGHZ

14---13---t~

ALE

VALID OUTPUT

HIGHZ

-SBHE

...

\V
/1\
....

SA BUS

.....

VALID ADDRESS

XABUS

-SBHE

HIGHZ

VALID ADDRESS

__ ~I_.~~~~~~~~_a_-_-_-_-_-_-_~~~,
.A\__________________
VALID OUTPUT

SYSTEM BUS MODE TIMING
16 MHz
Symbol

Parameter

SA Bus In

10 XA Bus Oul

SA Bus In to MA Bus Out

Min

20 MHz

Max

Min

Max

Unit

Condition

CL-100pF

CL =300 pF

SYSTEM BUS MODE TIMING WAVEFORM

SA BUS

~ 11\

...

14--- 18 --~.~
XABUS

__~---------J/,~-------------------------------

__~~~~~_19_-_-_-_-_~)\(~____________________
I.

MABUS

4-136

•

VLSI TECHNOLOGY, INC.
VL82C203

DMA MODE TIMING
16 MHz

Symbol

Parameter

Min

20 MHz

Max

Min

Max

Unit

tl0

-OMMEN to XA Bus High Z State

tll

-OMMEN to XA Bus from High Z to Valid Add Out

Condition

t12

-OMMEN to -XBHE High Z State

t13

-OMMEN to -XBHE from High Z to Valid Output

t14

XA Bus to SA Bus Out

CL= 200 pF

t15

XA Bus In to MA Bus Out

CL= 300 pF

t16

-XBHE In to -5BHE Out

CL= 200 pF

•

VLSI TECHNOLOGY, INC.
VL82C203

REFRESH TIMING
16 MHz
Min

Max

20 MHz

Symbol

Parameter

Max

Unit

t17

-REFEN to XA Bus Valid Add Out

Min

Condition

t18

-REFEN to SA Bus Valid Add Out

CL = 200 pF

t19

-REFEN to MA Bus Valid Add Out

CL= 300 pF

t20

-REFEN to SA Bus from High Z to Valid
Add Out

t21

-REFEN to SA Bus High Z Out

CL= 100 pF

REFRESH TIMING WAVEFORMS

-REFEN

\
...

t17

XABUS

J \.

t18

\/
I\.

SA BUS

t19

MABUS

-REFEN

SA BUS

t20
HIGHZ

V~ID~ t. ~1 ~
4-138

HIGHZ

•

VLSI TECHNOLOGY, INC.
VL82C203

ADDRESS TIMING
16 MHz
Symbol

Parameter

t22

ADDRSEL to MA Bus Out

123

A Bus to MA Bus Out

Note:

Min

20 MHz

Max

Min

Max

Unit

Condition

CL = 300 pF

CL=300 pF

122 delay may be derated by a factor of .04 nsJpF for heavier loads.

ADDRESS TIMING WAVEFORM

ADDRSEl~~______________________________________________________
--J

MAO-MA7

122----~)k~

_______________________________

SETUP & HOLD TIMING
16 MHz
Min

Symbol

Parameter

tSU24

A Bus to RAMALE and -BHE to ALE Setup Timing

tH25

A Bus to RAMALE and -BHE to ALE Hold Timing

SETUP & HOLD TIMING WAVEFORM

RAMALE, __________
ALE

A BUS,
-BHE

4-139

Max

20 MHz
Min

Max

Unit

Condition

•

VLSI TECHNOLOGY, INC.
VL82C203

RAMALE, BALE& IRQ1311MING

16 MHz
Min

Symbol

Paramatar

126

RAMALE 10 MA Bus Out

Max

20 MHz
Min

Condition

Max

Unit

CL=300 pF

127

ALE, CPUHLDA to BALE Oul

CL .. 200 pF

128

-ERROR 10 IRQ13 Oul

CL=50pF

129

-BUSY287 10 IRQ13 Oul

CL=50pF

130

RAMALE 10 -XBHE

CL= 100pF

RAMALE llMING WAVEFORM

RAM ALE

----'

.......t - - - 126 ---i"~

MAO-MA7

--------4----------J/~~--------------------------

__________~I_.:~~~~~_~_O_-_-_-_-_~~~~~_____________________________

-XBHE

BALE TIMING WAVEFORM

CPUHLDA
ALE,

_________________________________________________

.~-----127----i)K~

BALE

_ _ _ _ _ _ _ _ _ _ _ _ _ ____

IRQ1311MING WAVEFORM

-BUSY28

--.J

-ERROR ~

•

128

...

•
IRQ13

129

I~
4-140

•

VLSI TECHNOLOGY, INC.
VL82C203

AC TESTING -INPUT, OUTPUT WAVEFORM

INPUT

3.5V

----r

OOTPUT~
'.5V

'k_

~ TESTPOINTS;--~-.t

0.2V

AC TESTING - LOAD CIRCUIT

DEVICE UNDER TEST

[>------,CL"l
'Includes scope and jig capacitance.

AC TESTING - LOAD VALUES

Test Pin

CL (pF)

32, 34-38, 40-43, 45-48, 50-53, 55

200

57~

300

66-74,76-83

100

84,30

4-141

1.5V

•

VLSI TECHNOLOGY, INC.
VL82C203

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

QC - OOC to +70·C

QI = -400C to +85"C
Storage Temperature

-65"C to + 150"C

Supply Voltage to
Ground Potential

-0.5 V to +7.0 V

Applied Input
Voltage

...{l.5 Vto +7.0 V

Power Dissipation

indicated in this data sheet is not
implied. Exposure to absolute maximum
rating conditions for extended periods
may affect device reliability.

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

500mW

DC CHARACTERISTICS:

TA = oc: D·C to +7D"C, 01: -40"C to +8S"C, VDD

Symbol

Parameter

Min

VOH

Output High Voltage

2.4

VOl1

Output low Voltage

Max

Unit

0.45

VOL2

Output low Voltage

VIH

Input High Voltage

2.0

Vil

Input low Voltage

-0.5

0.45

VIHC

Input High Voltage

3.8

VllC

Input low Voltage

-0.5

VDD+0.5
0.8
VDD+0.5
0.6

=5 V ±S%, VSS = D V
Condition

IOH =-3,3mA

IOl - 8 mA, Notes 1 & 3

IOl = 24 mA, Notes 2 & 3

V
V
V

ALE, RAMAlE

Output Capacitance

Input Capacitance

CIO

InpuVOutput Capacitance

IlOl

Three-state leakage Current

-100

100

/-LA

III

Input leakage Current

-10

/-LA

ICC

Power Supply Current

@ 1 MHz Test Rate

Notes: 1. Pins 57-64,66-74, and 76-83.
2. Pins 32, 34-38, 40-43, 45-48, and 50-53, 55.
3. Output low current on all other outputs not mentioned in Note 1 or 2 have IOl (max) .. 2 mAo

4-142

•

VLSI TECHNOLOGY, INC.
VL82C204
PC/AT-COMPATIBLE DATA BUFFER
DESCRIPTION

FEATURES

The VL82C204 PC/AT-Compatible Data
Buffer provides a 16-bit CPU data bus
110 as well as 24 buffered drivers. The
buffered drivers consist of 16 bidirectional system data bus drivers, each
capable of sinking 24 mA (60 'LS loads)
of current; eight bidirectional peripheral
bus drivers, each capable of sinking 8
mA (20 'LS loads) of current. The
VL82C204 also generates the parity
error signal for the system.

Fully compatible with IBM PC/AT-type
designs
Completely performs data buffer
function in IBM PC/AT-compatible
systems
• Replaces several buffers, latches and
other logic devices
• Supports up to 20 MHz system clock
Device is available as "cores· for
user-specific designs

The device is manufactured with VLSl's
advanced high-performance CMOS
process and is available in a JEDECstandard 68-pin plastic leaded chip
carrier (PLCC) package. The
VL82C204 is part of the PC/ATcompatible chip sets available from
VLSI. Please refer to the Selector
Guide in the front of this manual.

Designed in CMOS for low power
consumption

ORDER INFORMATION

BLOCK DIAGRAM
00-07

SOOS07

OT/-R - r - OIR
-DENlO -

ENABLE
LATCH

1'8

BUFFER
XAO
CNTlOFF

.....
-

r- SEl
r- ClK

MOPOUTO

ENABLE
PARITY

XMEMR

....

Part Number

I-AEN

.....

PAREN

0lR245
GATE245
08-015

... r--- It

A
B
OIR
ENABLE

A
OIR

ENABLE
A

~
L
ERROR

16 MHz

Plastic Leaded Chip
Carrier (PLCC)

VL82C204-200C
VL82C204-2001

20 MHz

Plastic Leaded Chip
Carrier (PLCC)

Note: Operating temperature range:
OC = O·Cto +70·C
01 _ -40·C to +85·C.
MOPINO

XOO-X07

-PARERROR
S08-S015

....

'-- OIR

-OENHI

ENABLE

MOPINI

PARITY
ENABLE

-XBHE
MOPOUTI
8

Package

VL82C204-160C
VL82C204-1601

-XMEMR
XOATAOIR

System
Clock
Freq.

-TEST_

4-143

•

VLSI TECHNOLOGY, INC.
VL82C204

PIN DIAGRAM
MOP
IN1

9
CNTLOFF

01R245

GATE245

OT/-R

-TEST

-PARERROR
XAO
-XBHE

014

012

010

68 67 66 65 64 63 62 61

•

VOO

MOPOUTO

VSS

X07

VL82C204

TOP VIEW

VOO

X06

-XMEMR

X05

-OENLO

X04

-OENHI

X03

XOATAOIR

X02

AEN

X01

PAREN

XOO

VSS

S07

S015

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

SOS

VSS

S02

SOO

S08

4-144

S010

VSS

S013

•

VLSI TECHNOLOGY, INC.
VL82C204

SIGNAL DESCRIPTIONS
Signal

Signal

Name

Number

Type

CNTLOFF

This input is used as a clock to latch the current data on the low byte of the
system or peripheral data bus. Data is latched and output to 00-07 on the
rising edge of CNTLOFF and is independent of the status of DT!-R, XAO,
or-DENlO.

DTI-R

Data Transmit (high)/Receive (low) - This input is a signal from the bus
controller. It establishes the direction of data flow to or from the system
data bus.

-TEST

Test - This is an active low input which is used to three-state all outputs of
the VL82C204 device. This is for system level test where it is necessary to
overdrive the outputs of the Vl82C204. When -TEST is low, all outputs
and bidirectional pins of the Vl82C204 will be three-stated. This pin
should be pulled up via a 10K n pull-up resistor in a standard system
configuration.

-DENLO

Data Enable low - An active low input that enables a low byte data transfer
on the CPU data bus low byte transceiver. When -DENlO is inactive, low
byte parity is disabled.

XAO

Peripheral Address Bus Bit 0 - This is the lSB of the peripheral address
bus. The signal is used throughout the system to indicate low or high byte
data transfers. It is used to select latched or immediate data out of the
CPU low byte bus transceiver. It also enables low byte parity checking.

XDATADIR

Transceiver Data Direction - This input is used to select the direction of the
peripheral data bus transceiver. When XDATADIR is low, it indicates an
110 read from the XD bus or an interrupt acknowledge cycle. When
XDATADIR is high, it indicates data on the SO bus should be placed on XD
bus.

AEN

Address Enable - An active high input that is used to disable the peripheral
data bus transceiver while the DMA controller is using the peripheral data
bus for address information.

DIR245

Direction 245 - An input control signal used to set the direction of the high!
low system data bus transceiver. This is used for high to low, or low to
high data byte moves.

GATE245

Gate 245 - An active low input that enables the highllow system data
transceiver.

-DENHI

Data Enable High - An active low input that enables a high byte data
transfer on the CPU data bus high byte transceiver. When -DENHI is
inactive, high byte parity is disabled.

-XBHE

Transfer Bus High Enable - An active low that indicates a transfer of data
on the upper byte of the memory data bus. It also enables high byte parity
checking.

-XMEMR

MDPOUTO

Memory Data Parity Out 0 - An active high input that is the output of the
stored memory parity data. It is checked for parity errors with the low byte
of data read from memory.

MDPOUT1

Memory Data Parity Out 1 - An active high input that is the output of the
stored memory parity data. It is checked for parity errors with the high byte
of data read from memory.

Signal
Description

4-145

•

VLSI TECHNOLOGY, INC.
VL82C204

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

MDPINO

Memory Data Parity In 0 - An active high output that is the parity input to
the system board memory. It is generated from the current low byte data
on the memory data bus.

MDPIN1

Memory Data Parity In 1 - An active high output that is the parity input to
the system board memory. It is generated from the current high byte data
on the memory data bus.

PAAEN

-PAAEAAOA

Parity Error - An active low output that is used to indicate that a memory
parity error has occurred. This signal is latched by -XMEMA and is valid
until the next memory access.

XDO-XD7

46-53

110

Peripheral Data Bus Bits 0-7 - liD's used to control the coprocessor, keyboard, ADM memory, and the DMA controllers.

DO-D15

56-59,61-64
68, 1-7

CPU Data Bus Bits 0-15 - This is a bidirectional bus controlled by the
DT/-A input.

SDO-SDI5

34-31,29-26,
36-39,41-44

110

System Data Bus Bits 0-15 - These are 110 signals.

VDD
VSS

Parity Enable - This active high input is used to enable the parity data latch.
It is used to prevent false parity errors when ADM memory access occurs.

18,35,60
9, 25, 30, 40,
'45,54,66

System Power: 5 V
System Ground

FUNCTIONAL DESCRIPTION
The VL82C204 is part of a five chip set
which together perform all of the onboard logic required to construct an IBM
PC/AT-compatible system. The PC/ATCompatible Data Buffer replaces
several bus transceivers and a CPU
lower byte data latch located within a
PC/AT-type system.
The primary function of the Data Buffer
is to multiplex the 80286 microprocessor data lines DO-D15 to the system
data bus SDO-SD15 and the peripheral
data bus XDO-XD7. This is accomplished through four sets of 8-bit wide
data multiplexors. The lower data byte
of the CPU data bus transceiver has a
byte wide register which is clocked by
the rising edge of CNTLOFF. The data
can be latched to the lower byte of the
CPU data bus only. XAO is used to
control data flow to the CPU data bus.
When XAO = 0, real time data is passed
to the CPU data bus. When XAO = 1,
latched data is passed to the CPU data

bus. The four groups of transceivers
can be seen in the block diagram of the
device. The data parity encoder/
decoder logic is also located within this
device. All data present upon the CPU
data bus passes through the parity
logic. The outputs of the parity encoder/decoders, MDPINO and MDPIN1,
are enabled via PAAEN to prevent
decoding a ADM access and are gated
with -XMEMR. The -PAAEAROA
signal is fed back to the Memory
Controller where it is gated with other
logic to produce the NMI signal for the
80286.

fashion as to prevent this from happening. In the case where only the
VL82C204 is used, care must be taken
as to ensure that the control signals will
not cause an internal bus collision.
From the block diagram it can be seen
that every bus transceiver has an A and
B 110 port. The DIA input to the
transceiver controls the direction of data
flow through the transceiver. A high (1)
input into the DIA pin causes data to
flow from A to B. A low (0) causes data
to flow from B to A. All transceiver
enables are low true causing the output
of the particular transceiver to be active.

The logic controlling the bus transceivers has been optimized for speed and
as such there are no provisions to
prevent internal bus collisions. In a
standard PC/AT-type application using
the full 16 or 20 MHz, the VL82CPCAT16/-20, chip sets this is not a problem
as the control signals which enable the
transceivers are decoded in such a

The VL82C204 should be used with
either the VL82CPCA1"-16 or
VL82CPCAT-20 chip sets as it implements a changed architecture from the
original system. In order to speed up
the memory access, the MD bus (memory data) has been moved to the CPU
Data Bus. The VL82C204 has been designed to accommodate this change.

4-146

•

VLSI TECHNOLOGY, INC.
VL82C204

The -TEST pin has been added to
enhance system level testing of the chip
sets. When this pin is active (0), all
outputs and bidirectional pins are

AC CHARACTERISTICS:

placed in three-state. This allows a
board level test system to overdrive
outputs of the VL82C204 without
damage to the device. In addition to

three-stating the outputs, all bus control
inputs are ignored to prevent internal
bus collisions and the internal bus
follows the state of the system data bus
(SDO-SD15).

TA = oc: O°C to +70°C, 01: -40°C to +85°C, VDD

= 5 V ±5%, VSS = 0 V

CPU DATA BUS 110 MODE TIMING
16 MHz

Unit

CL = 200 pF

CL=100pF

D High Byte In to SD High Byte Out

CL = 200 pF

D High Byte In to SD Low Byte Out

CL= 200 pF

D High Byte In to XD Bus Out

CL = 100 pF

Parameter

D Low Byte In to SD Low Byte Out

D Low Byte In to XD Bus Out

Min

Max

20 MHz

Max

Symbol

CPU DATA BUS 110 MODE TIMING WAVEFORMS

DLOW
BYTE

--.I \.

....

..
\,/

SDLOW
BYTE

...

Ji\.

\,/
J\.

XDBUS

DHIGH
BYTE

--.I

K
t3

\';-

SD HIGH
BYTE

SDLOW
BYTE

..
.

J\.

•

\,/
J\.
t5

XDBUS

\,;J\.
4-147

Min

Condition

VLSI TECHNOLOGY, INC.
VL82C204
SYSTEM LOW BYTE DATA BUS 110 MODE TIMING

16 MHz
Symbol

Parameter

Max

Unit

SO Low Byte In to 0 Low Byte Oul

SO Low Byte In 10 0 High Byte Oul

CL=120pF

SO Low Byte In 10 SO High Byte Oul

CL = 200 pF

SO Low Byte In 10 XO Bus Oul

CL= 100 pF

Min

Max

20 MHz

SYSTEM LOW BYTE DATA BUS 110 MODE TIMING WAVEFORMS
SOLOW

BYTE

--I r\-

...

\V
/1\

o LOW
BYTE

...

\/
1\

o HIGH
BYTE
04

...

\/
1\

SO HIGH

BYTE
04
XOBUS

11\

4-148

Min

CondHlon
CL=120pF

•

VLSI TECHNOLOGY, INC.
VL82C204

SYSTEM HIGH BYTE DATA BUS 110 MODE TIMING
16 MHz
Min

Max

20 MHz

Symbol

Parameter

Max

Un"

t10

SD High Byte In to D High Byte Out

t11

SD High Byte In to SD Low Byte Out

CL = 200 pF

t12

SD High Byte In to XD Bus Out

CL= 100 pF

SYSTEM HIGH BYTE DATA BUS 1/0 MODE TIMING WAVEFORMS
SD HIGH

BYTE

--.l 1\

•

t10

\V
JI\.

DHIGH

BYTE

...

t11

XDBUS

\V
Jr--...

SDLOW

BYTE

t12

\V
/1\

4·149

Min

Condition
CL=120pF

VLSI TECHNOLOGY, INC.
VL82C204
PERIPHERAL DATA BUS 1/0 MODE TMING
16 MHz
Min

Max

20 MHz

Symbol

Paramatar

Max

Unit

t13

XO Bus In to 0 Low Byte Out

CL=120pF

t14

XO Bus In 10 0 High Byte Out

CL=120pF

115

XO Bus In 10 SO Low Byte Out

CL= 200 pF

116

XO Bus In 10 SO High Byta Out

CL= 200 pF

PERIPHERAL DATA BUS 1/0 MODE nMING WAVEFORM
XOBUS

o LOW
BYTE

o HIGH
BYTE

~I
~\

•

113

\1
J\

t14

\1
t15

BYTE

.
p

SOLOW

SO HIGH

J\.
-II

BYTE

•

116

\/
J\.

4-150

Min

Condition

•

VLSI TECHNOLOGY, INC.
VL82C204

MEMORY WRITE MODE TIMING

16 MHz
Symbol

Parameter

Min

20 MHz

Max

Min

Max

Unit

Condition

t17

D Bus In to MDPINO, MDPIN1 Out

CL=50pF

t18

SD Bus In to MDPINO, MDPIN1 Out

CL=50pF

t19

XD Bus In to MDPINO, MDPIN1 Out

CL=50pF

MEMORY WRITE MODE TIMING WAVEFORM
DBUS

MDPINO,
MDPIN1

SDBUS

~ t17=1~~_
~___________________________________________________
_- _
-_
-_
J
_

MDPINO,
MDPIN1

~~~~===============__.t_18~~~~~~~~~~~~~~~~~~-------------

XOBUS

~___________________________________________________

MDPINO,
MDPIN1

_-_
-_
-_
J
_:

~~:~~~~~~~~~~ t_19~_-~~_-~~~~~.::~
___

4-151

________________________

•

VLSI TECHNOLOGY, INC.
VL82C204

MEMORY READ MODE TIMING
16 MHz

Min

tSU20

D Bus Setup to -XMEMR High

tH21

D Bus Hold to -XMEMR High

-4

tSU22

PAREN Setup to -XMEMR High

tH23

PAREN Hold to -XMEMR High

tSU24

XAO Setup to -XMEMR High

tH25

XAO Hold to -XMEMR High

tSU26

-XBHE Setup to ..,.XMEMR High
-XBHE Hold to -XMEMR High

128

-XMEMR High to -PARERROR Out

Min

Max

Unit

Parameter

tH27

Max

20 MHz

Symbol

Condition

CL=50pF

MEMORY READ MODE TIMING WAVEFORM
DBUS

tSU20

-XMEMR

PAREN

/ ..

tSU22

-XMEMR

XAO
-XBHE

VALID

...

\
\ ..

tSU24

tSU26

J
.. ....
/
.. ..... ....
..-

-PARERROR

4-152

tH21

.. !\

tH23

--..

V
.. V

tH25

tH27

128

•

VLSI TECHNOLOGY, INC.
VL82C204

CPU LOW BYTE DATA BUS LATCH AND SELECT TIMING

16MHz
Symbol

Parameter

tSU29

SD Low Byte Setup to CNTLOFF High

tH30

SD Low Byte Hold to CNTLOFF High

tSU31

XD Bus Setup to CNTLOFF High

tH32

XD Bus Hold to CNTLOFF High

t33

XAO to D Low Bus Out

Min

20 MHz

Max

Min

Max

Unit

Condition

CL=120pF

CPU LOW BYTE DATA BUS LATCH AND SELECT TIMING WAVEFORMS

SDLOW
BUS

~/
~\

...

XDBUS

...

tSU29

~/
~\

...

/\
tH30

CNTLOFF ______________________________

...
\

VALID
tSU31

XAO

VALID

--. .~

tH32

....

-J~

--------'~I4.---t33 ----~~~I ~
)K

DBUS

4-153

_ _ __
LOW BYTE

VLSI TECHNOLOGY, INC.
VL82C204
AC TESTING -INPUT, OUTPUT WAVEFORM

INPUT

----r~_ _ _ _ _ _

3.5V

0.2 V

*_1.5V

AC TEST

POINTS--~~

AC TESTING - LOAD CIRCUIT

DEVICE UNDER TEST

[>-----.l
CL·

·Includes scope and jig capacitance.

AC TESTING - LOAD VALUES

Test Pin

CL (pF)

26-29,31-34,36-39,41-44

200

1-7,56-59,61-64,68

120

46-53

100

8,15,65

4-154

•

VLSI TECHNOLOGY, INC.
VL82C204

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

OC = o·c to +70·C
01 = -4O·C to +85·C

Storage Temperature

-65·C to + 150·C

Supply Voltage to
Ground Potential

-0.5 V to +7.0 V

Applied Input
Voltage

-0.5 V to +7.0 V

Power Dissipation

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

500mW

DC CHARACTERISTICS:

TA = QC:

o·c to +70·C, QI:

Symbol

Parameter

Min

VOH

Output High Voltage

2.4

VOL1

Output Low Voltage

VOL2

Output Low Voltage

VIH

Input High Voltage

2.0

VIL

Input Low Voltage

-0.5

VIHC

Input High Voltage

3.8

VILC

Input Low Voltage

Output Capacitance

Input Capacitance

CIO

Input/Output Capacitance

ILOL

Three-state Leakage Current

III

Input Leakage Current

ICC

Power Supply Current

-40·C to +85·C, VDD

Max

Unit

Condition

IOH =-3.3 mA

0.45

IOL = 8 mA, Notes 1 & 3

0.45

IOL = 24 mA, Notes 2 & 3

VDD+ 0.5

V
V

0.8
VDD + 0.5

-0.5

=5 V ±50/0, VSS =0 V

CNTLOFF

0.6

CNTLOFF

-100

100

(.lA

-10

(.lA

@ 1 MHz Test Rate

Notes: 1. Pins 1-7, 46-53, 56-59, 61-64, 68.
2. Pins 26-29, 31-34, 36-39, 41-44.
3. Output low current on all other outputs not mentioned in Note 1 or 2 have IOL (max) = 2 mAo

APPLICATION NOTE
In order to ensure correct function of
bus transfers when using the VL82C204
as a stand-alone part (not part of the
chip set), the following conditions must
be met:

For SD high byte in to SD low byte out,
ensure that either -DENHI = 1 or DT/-R
=0.
For SD low byte in to SD high byte out,
ensure that either -DENLO = 1 or
DTI-R = 0 and AEN 1 or XDATADIR
= 1.

4-155

When using the VL82C204 along with
the remaining chips in the chip set,
these conditions are virtually excluded.

•

VLSI TECHNOLOGY, INC.
VL82C204

NOTES:

4-156

•

VLSI TECHNOLOGY, INC.
VL82C205A
PAGE-MODE/INTERLEAVE CONTROLLER

FEATURES
• Less than 0.6 wait state average
DRAM performance

• Supports 16 MHz 80286 operation
with 100 ns DRAMs, 20 MHz with 80
ns DRAMs

• Low power CMOS technology

• Supports two bank interleaved pagemode DRAM accesses for PC/ATcompatible systems

• 68-pin PLCC package
• Backward compatible with VL82C205

• Speed upgrades to 20 MHz

DESCRIPTION

• Companion to VL82CPCAT-16 and
VL82CPCAT-20, 16120 MHz PC/ATcompatible chip sets

The VL82C205A is a page-mode
memory controller for the VlSI
VL82CPCAT-16 and VL82CPCAT-20,
16120 MHz PC/AT-compatible chip sets.

13 chip PC/AT implementation (nonmemory chips)

PIN DIAGRAM

This chip, in addition to the other five
chips from the VLSI chip sets, allows
two bank interleaved page-mode
memory cycles to be run. This allows a
16 MHz processor to use page-mode
100 ns DRAMs and still have less than
0.6 wait states performance.
When using page-mode, accesses to
each bank that are within 512 bytes of
the last access are performed with zero
wait states. Accesses that are outside
that range are performed in two wait
states.

BLOCK DIAGRAM
VL82C205A

Ala

A12

A13 A15

A17

A19

A21 A22

OSC

RASr----.-(

CPUHLDA

RAMRDWT
-RAMWA

-80
-81

-RAMWB

vss

W-IO
-READY
PROCCLK
VSS

ADDSEL
VDD
-RASOA
-RASOB

RAMWRWT
F16

RAMWRWT

RAMRDWT

r::::;r.====~-.JU-... -wso
H..,...,+-+

IOCHRDY

t------'~-+--+-+

-RAMWx

(---+++

ADDSEL

vss
-RASIA
-RASIB
-CASOL
-CASOH
-CASlL

-MEMR
-MEMW
-REF

CASO
CASI
RASO
RASI
VDD

vss
-CASIH
XA9

-80.-81
-MEMR
-MEMW

1.41-10
-IREF
-READY
PROCCLK
F16
-PAGE

CPUHLDA

XAO
AD
-XBHE
-SHE
CASD,CASI
RASD,RASI
-INTLVEN

ORDER INFORMATION
Clock
Freq.

Package

VL82C205A-160C

16 MHz

Plastic Leaded Chip Carrier (PLCC)

VL82C205A-200C

2DMHz

Plastic Leaded Chip Carrier (PLCC)

Part
Number

t--_->,4.-+ -IRASxy

1-_--''''4'-+ -CASxy

XAS
A9
RESET

Note: Operating temperature is D·C to +70·C.

4-157

-IROB

-------1.:>-------- -RESET

-----{!»------.

IROS

•

VLSI TECHNOLOGY, INC.
VL82C205A

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Type

Signal

A9-A23

9-6,4-1,
68-64,
62,61

Upper Address Bits from the CPU - These inputs are latched any time the
-RASxy signals go active. On any following memory reads, the address
bits are compared to the latched value to determine if a page hit has
occurred.

CPUHLDA

CPU Hold Acknowledge - This input is used to determine which signals are
used to initiate and terminate memory cycles. When CPUHlDA is low, the
status signals -SO, -S1 and M/-IO along with -READY are used to control
memory cycles. When CPUHlDA is high, the inputs -MEMR and -MEMW
are used to generate the DRAM control signals.

-SO

Status 0 - This input is used along with -S1 and M/-IO to determine which
type of bus cycle is being requested by the CPU.

-S1

Status 1 - This input is used along with -SO and M/-IO to determine which
type of bus cycle is being requested by the CPU.

M/-IO

Memory or I/O select - This input is used along with -SO and -S1 to determine which type of bus cycle is being requested by the CPU.

-READY

An input used to determine when to terminate the current memory access
to the DRAMs.

PROCClK

This is the main clock input to the Vl82C205A and should be connected to
the same signal that drives the 80286 ClK pin.

RAMWRWT
RAMRDWT

17
60

The wait select inputs control the number of wait states to be used for
memory accesses when the -PAGE input is high. HRAMRDWT is low,
zero wait state read cycles are generated. HRAMWRWT is low, zero wait
state write cycles are generated. H either signal is high, one wait state
memory cycles are generated for the read or write. These are normally
jumpers and are common to the Vl82C201 pins. They should be held high
in page-mode operation (-PAGE-low).

F16

The F16 input comes from the memory controller chip and is used to
indicate that the current address is in the on-board memory address space.

-MEMR

Memory Read - An input which is used to determine when memory read
accesses to the DRAMs should occur if CPUHlDA is high.

-MEMW

Memory Write - An input which is used to determine when memory write
accesses to the DRAMs should occur if CPUHlDA is high.

-REF

Refresh - The -REF input is used by the Vl82C205A to force the ADDSEl
output low.

CASO

CAS Enable Input for Bank 0 - This input is used along with CAS1, RASO,
and RAS1 to determine which bank of DRAM should be accessed.

CAS1

CAS Enable Input for Bank 1 - This input is used along with CASO, RASO,
and RAS1 to determine which bank of DRAM should be accessed.

RASO

RAS Enable Input for Bank 0 - This input is used along with RAS1, CASO,
and CAS1 to determine which bank of DRAM should be accessed.

RAS1

RAS Enable Input for Bank 1 - This input is used along with RASO, CASO,
and CAS1 to determine which bank of DRAM should be accessed.

~scrlptlon

4-158

•

VLSI TECHNOLOGY, INC.
VL82C205A

SIGNAL DESCRIPTIONS (Cont.)
Signal

Signal

Name

Number

Type

SHDWRAMMAP

Signal
Description
Shadow RAM Map - An active high input that indicates the system is using
the shadow mode (see the VLS2C202 description for complete discussion
of shadow mode). This signal is used to generate RAS and CAS outputs
while doing memory writes during the copying of ROM into shadow RAM.
This is needed because the F16 signal is inhibited during the writes.

RESET

This input is the main reset signal for the page-mode controller chip.

-RESET

This output is the logical inversion of the RESET input.

AO is an input signal from the CPU. It is used when CPUHLDA is low to
enable the appropriate low byte -CAS output during a memory cycle.

-BHE

Byte High Enable - An input signal from the CPU. It is used when
CPUHLDA is low to enable the appropriate high byte -CAS output during a
memory cycle.

XAO

XAO is sampled when CPUHLDA is high to enable the appropriate low byte
-CAS output during a memory cycle.

-XBHE

-XBHE is sampled when CPUHLDA is high to enable the appropriate high
byte -CAS output during a memory cycle.

OSC

The OSC clock input is used as a fixed frequency to determine when a
RAS precharge is required.

-IROS

This input is the active low interrupt request from the real-time clock. It is
inverted and sent out as IROS.

IROS

-PAGE

This output is the logical inversion of the -IROS input.
The -PAGE input controls the type of memory accesses to be performed
for CPU requests. When -PAGE is low, the VLS2C205A will generate zero
wait state page-mode accesses on page hits. When -PAGE is high, the
VLS2C205A will sample RAMWRWT or RAMRDWT to generate normal
zero or one wait state memory accesses.

-INTLVEN

Interleaving - -INTLVEN is used to enable two bank interleaving when
page-mode is active.

-TEST

An active low input which should be pulled high through an external pull-up
resistor. When pulled low, it will force the page-mode controller to put all
output pins into a high impedance state to isolate it from other parts in the
system.

-WSO

Wait State 0 - An active low output which is pulled low any time the pagemode controller wants the current bus cycle to be a zero wait state cycle. It
requires an external 300 ohm pull-up resistor.

IOCHRDY

VO Channel Ready - An output which is pulled low when the controller
wants to entend the memory cycle. It requires an external 300 ohm pull-up
resistor.

XA9

-CAS1H

XA9 is sampled when two bank interleave is active and CPUHLDA is high
to enable the appropriate -RASxy output.

Column Address Strobe 1 High - This active low column address strobe
should be connected directly to the DRAMs for the high byte of the upper
bank. It is enabled for memory accesses to bank 1 when -BHE is low in
CPU mode or when -XBHE is low in non-CPU mode.

4-159

VLSI TECHNOLOGY, INC.
VL82C205A
SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

-CAS1L

Column Address Strobe 1 Low - This active low column address strobe
should be connected directly to the DRAMs for the low byte of the upper
bank. It is enabled for memory accesses to bank 1 when AO is low in CPU
mode or when XAO is low in non-CPU mode.

-CASOH

Column Address Strobe 0 High - This active low column address strobe
should be connected directly to the DRAMs for the high byte of the lower
bank. It is enabled for memory accesses to bank 0 when -BHE is low in
CPU mode or when -XBHE is low in non-CPU mode.

-CASOL

Column Address Strobe 0 Low - This active low column address strobe
should be connected directly to the DRAMs for the low byte of the lower
bank. It is enabled for memory accesses to bank 0 when AO is low in CPU
mode or when XAO is low in non-CPU mode.

-RASOA
-RASOB

54,53,

Row Address Strobes for Bank 0 - These are the active low row address
strobes to be connected directly to the DRAMs in the lower bank. RAS
timing will vary depending on the operating mode. Refer to the functional
description and AC timing diagrams for timing.

-RAS1A
-RAS1B

51,50

Row Address Strobes for Bank 1 - These are the active low row address
strobes to be connected directly to the DRAMs in the upper bank. RAS
timing will vary depending on the operating mode. Refer to the functional
description and AC timing diagrams for timing.

ADDSEL

Address Select - An output used to switch from row to column addresses.
It will always follow the -RASxy outputs by half a PROCCLK cycle if in
page-mode. In non page-mode, (-PAGE = 1, or CPUHLDA = 1) it follows
the -RASxy outputs by half a PROCCLK cycle unless zero wait state is
selected. During zero wait state cycles ADDSEL follows -RASxy on the
same PROCCLK edge but is delayed. ADDSEL is forced low during
refresh cycles. In zero wait state applications, additional external delay
may be required to insure proper address hold time depending on the
DRAM specifications.

-RAMWB

RAM Write B - Used to get an early write enable signal to the DRAMs to
support page-mode timing and zero wait state write cycles. It will go low
during the second phase of any memory write cycle. -RAMWB will return
high at the end of the bus cycle when -READY is sampled low. -RAMWB
is functionally identical to -RAMWA. Each output provides sufficient drive
for a single 18-bit bank.

-RAMWA

RAM Write A - Used to get an early write enable signal to the DRAMs to
support page-mode timing and zero wait state write cycles. It will go low
during the second phase of any memory write cycle. -RAMWA will return
high at the end of the bus cycle when -READY is sampled low. -RAMWA
is functionally identical to -RAMWB. Each output provides sufficient drive
for a single 18-bit bank.

VSS

16, 39, 46, 52,
57,63

System Ground

VDD

5,26,42,55

System Power: 5 V

4-160

•

VLSI TECHNOLOGY, INC.
VL82C205A

FUNCTIONAL DESCRIPTION
The VL82C205A consists of several
major blocks, including the page hit
detection logic, bank select logic, RAS
and CAS generation, RAS time-out
detection, non-page-mode timing
support, time base generation and gluecollection. For a more detailed understanding of the VL82C205A, refer to the
block diagram.

PAGE-MODE CONTROLLER
In this discussion, the following terms
are used:
• Page refers to a block of 512 bytes,
for which only the lower nine address
bits change.
• Bank refers to 18 bits of DRAM (16bit word plus two parity bits).
• HighlLow Byte refers to the upper or
lower 8 bits of a 16-bit word.
The VL82C205A controller may be used
in either page-mode or non page-mode,
as chosen by input -PAGE. In pagemode, any read access within the same
page of the previous memory access is
performed with zero wait states.
Internal latches track the successive
address references permitting the
shorter cycles to be used automatically.
For references on page, the DRAM row
addresses do not change. Therefore,
the RAS lines remain asserted continuously between DRAM cycles. (The
DRAM column lines are effectively
mapped to the lower nine bits of the
address space.)

An access outside of the 512-byte page
or a write operation forces two wait
states. Under that condition, the RAS
lines are de-asserted for the required
precharge time.
With the controller's page-mode operation enabled, an average of 0.6 wait
states is used.

PAGE-MODE OPERATION WITH
TWO BANK INTERLEAVE
When page-mode operation is selected
and two 18-bit banks of DRAM are
installed, it is possible to utilize the two
bank interleave capability of the
VL82C205A. This feature allows pagemode accesses to two disjointed pages,
one in each DRAM bank. Interleaving
is accomplished using the A9, XA9,
CASO and CAS1 input signals.
RASiCAS GENERATION
Four RAS and CAS signals are brought
to supply sufficient drive for nine bits of
DRAM without the need for off-chip
buffering and allows for equal loading.
The controller attempts to generate
RAS at the earliest time possible. A
number of conditions are monitored by
the chip, which could preclude early
RAS. The RAS precharge timing logic
then generates RAS and CAS based on
them.
When page-mode and two bank
interleave are active, the CASOx,
RASOx, and CAS1x, RAS1x outputs are

used to select the appropriate DRAM
bank. At all other times, the four RAS
outputs are identical. The CASxH and
CASxL outputs are used to select the
appropriate high or low byte within a
bank.
RAS-~CTIVE TIMEOUT WARNING
An internal counter monitors RAS to
detect maximum RAS active time. After
approximately 10 !ls, a RAS precharge
is performed.

Input OSC is used to monitor RAS. A
maximum of 72 consecutive read
operations at 16 MHz to the same page
can take place before a false page miss
is inserted to do the RAS precharge.

WAIT STATE GENERATION
IOCHRDY and -WSO are the outputs
that indicate how many wait states are
in the current cycle. -WSO is pulled low
for all page hits. Other zero wait state
cycles are handled by the VL82C201.
This is an open-drain output and a 300
ohm pull-up resistor is required.
IOCHRDY is pulled low for all two wait
state cycles. This is a three-state
output. When IOCHRDY goes high
(inactive), the VL82C205A drives the
signal for half a PROeCLK cycle (15
ns), then goes into three-state (see the
logic below). A 300 ohm pull-up resistor
is required to hold the signal high and to
pull-up the other system open-drain
outputs connected to IOCHRDY.

FIGURE 1. IOCHRDY GENERATION
FLIP-FLOP

d
INTERNAL IOCHRDY

Q~----+-------------+-------~
PROCCLI

CL'

.. capacitance .
'Includes scope an d Jig

AC TESTlNG - LOAD VALUES

Test Pin

CL(pF)

41,43,58,59

200

45,47-51. 53, 54

100

All Others

4-171

•

VLSI TECHNOLOGY, INC.
VL82C205A

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

-1 O·C to +70·C

Storage Temperature -65·C to + 150·C
Supply Voltage to Ground
Potential
-0.5 V to +0.3 V
Applied Output
Voltage

-0.5 V to +0.3 V

Applied Input
Voltage

-0.5 V to +7.0 V

Power Dissipation

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

500mW

DC CHARACTERISTICS: TA = D·C to +7D·C, VDD =5 V ± 5%, VSS =D V
Symbol

Parameter

Min

VOH

Output High Voltage

2.4

VOL1

Output Low Voltage

VOL2

Max

Unit

Condition

IOH.-3.3 mA

0.45

-WSO, IOCHRDY, CL = 200 pF,
IOL=24mA

Output Low Voltage

0.45

-RAMWA, -RAMWB, CL = 200 pF,
IOL-BmA

VOL3

Output Low Voltage

0.45

-RASxy, -CASxy, CL = 100 pF,
IOL= BmA

VOL4

Output Low Voltage

0.45

All Other Pins, CL = 50 pF, IOL = B mA

VIH

Input High Voltage

2.0

VIL

Input Low Voltage

-0.5

VIHC

Input High Voltage

Output Capacitance

Input Capacitance

CIN

Input Pin Capacitance

III

Input Leakage Current

3.6

VDD+0.5
O.B
VDD+0.5
16

V
V
V
pF

XA9

Per MHz Operating Frequency

ilL

Input Low Current

100

19B

Standby Supply Current

100

IJ.A
IJ.A
IJ.A

ICC

Operating Supply Current

2·

Note:

-10

Inputs = VSS or VDD, outputs are not loaded.

4-172

PROCCLK

XA9 Input High

•

VLSI TECHNOLOGY, INC.

PIRHEl~M~INlARY

VL82C286
TOPCAT 286/386SX CHIP SET
FEATURES
Built-in ·sleep· mode features,
including use of slow refresh DRAMS
in power critical operations

• Two chip PC/AT-compatible chip set
capable of use in 286- or 386SXbased systems up to 25 MHz

• EMS hardware supports full LIM EMS
4.041 spec over entire 32M byte
memory map with backfill to 256K includes two sets of 36 mapping
registers each

• Both chips are 160 quad flatpacks,
1.0- and 1.5-micron CMOS
• Memory control of one to four banks
of 16 bit DRAM using 256K, 1M, or
4M components allowing 32M bytes
on system board

• Shadow RAM support in 16K increments over entire 640K to 1M range

• Page mode DRAM operation on any
number of banks

• Support for 287 or 387SX numerical
coprocessors

Twolfour-way interleaving or direct
access on system board memory

• Software coprocessor reset can be
disabled

Programmable option for block or
word interleave
Programmable DRAM timing parameters
• Remap option allows logical reordering of system board DRAM banks
• System board refresh optionally
decoupled from slot bus refresh
Staggered refresh minimizes power
supply load variations .

• Internal switching and programmable
CLK2 support for slow and ''turbo"
modes
• Programmable drive on DRAM and
slot bus interface signals allows direct
drive tailored to system size
• Asynchronous or synchronous slot
bus operation w~h programmable bus
clock divider

BLOCK DIAGRAM

r<-l

r:=::J

32 KHz OSC

-ROMB-'>

-BHE,BLElAQ"

SLOT STAT/CTRL

Integrated peripheral functions:
Two 82C37A DMA controllers
Two 82C59A interrupt controllers
One 82C54 timer
One 82C018 real time clock
• Supports 8- or 16-b~ wide BIOS
ROMs

• 110 decode programmable for 10- or
16-bit addresses
• Separate parity generators/checkers
lor high speed operation
• Designed for systems w~h up to 12
MHz backplane operation
• Three-state control pins added for
board level testabil~
Compatible w~h Lotus 1-2-3" version
3.0 in 1M systems

ORDER INFORMATION
VL82C2861386SX Chip Set

~ LA23-lA17
VL82C331
... KEYBO, 5PKR
ISA BUS
r--_-P:..:A.::.R::::ER:..::R,::O::.!)lR... CONTROLLER ....,.,S:::;A:.:;1g.::::5~A~0..,S~B::..lH5.E_...,

2861~86~

Bus "quiet" mode assures that slot
bus signal lines are driven only
during slot accesses

,,,,,

Part Number

I 1_ II
~

Package

1 - VL82C320-FC

Plastic Flatpack

1 - VL82C331-FC

Plastic Flatpack

L
0
T

Note: Operating temperature range is
O·C to +70·C.

X07·XOO
-BHE,BLElAO,.
~ DATA CONTROL

MAl a·MAO,
-RAMW

VL82C320
SYSTEM

RAS3·RASO

CONTROLLER

~~----------------~
CA57·CASO

....5015·500
A20, TURBO,
RESET

PAR1·PARO

fTClK2l
~1,"'1t

LJCl.Ka
-ROMCS
BIOS
ROM
"

~SAl8-SAO

'--"S-BIT ROM IS ON XO BUS

2S6I-SX ~

...._ _ _...

~~
I~
~~
~~

VL82Cl 06
COMBO

~ -..!!?E- L - _ - - - l
4-173

Lotus 1-2-3" is a registerd trademark of
IBM Corp.
LIM EMS 4.0" is a registered trademark of Lotus Development Corp., Intel
Corp. and Microsoft Corp.

...
~

•

VLSI TECHNOLOGY, INC.

PRlEl~M~INlARY

VL82C386
TOPCAT 386DX CHIP SET
FEATURES
• Three chip PC/AT-compatible chip set
capable of use in 386DX-based
systems up to 33 MHz VL82C330 System Controller,
VL82C331 ISA Bus Controller,
VL82C332 Data Buffer

• Built-in 'sleep' mode features,
including use of slow refresh DRAMS
in power critical operations

• Bus "quiet" mode assures that slot
bus signal lines are driven only during
slot accesses

• Hardware supports full LIM EMS 4.0"
spec over entire 64 Mbyte memory
map

• Integrated Peripheral Functions:

• Tw6128-pin and one 160-pin
(VL82C331) quad flatpacks, 1.0- and
1.5-micron CMOS

• DMA expanded to allow transfers
over 64 Mrange
• Shadow RAM support in 16K increments over entire 640K to 1 M range

• Memory control of one to four banks
of 32-b~ DRAM using 256K, 1M, or
4M components allowing 64 Mbytes
on system board

Support for 387DX and Weitek 3167
numerical coprocessors allows use of
either or both

• Page mode DRAM operation on any
number of banks

• Coprocessor software reset can be
disabled

• Twolfour-way interleaving or direct
access on system board memory

• Internal switching and programmable
CLK2 support for PC/AT-compatible
and "urbo" modes

• Programmable option for block or
word interleave

• Programmable drive reduces the
need for external buffering on DRAM
and slot bus interface signals

• Programmable DRAM timing parameters
• Remap option allows logical reordering of system board DRAM banks
• System board refresh optionally decoupled from slot bus refresh

• ISA Bus Control of 386DX-based
PC/AT-compatibles. Capable of
asynchronous or synchronous bus
operation to 16 MHz

• Staggered refresh minimizes power
supply load variations

• Compatible w~h Lotus 1-2-3'" version
3.0 in 1M systems

BLOCK DIAGRAM
r-3B6DX

-READVO

A31. A2B. A2f1.A2

VLII2C33O
SYSTEM
CONTROLlER

-BE3·-BEO
D31.()O

-ROMCS

' - - - OTHER

CASBK LBE

R~ADYIN

'---f-:E
387DXI
3167

READY
LOGIC

A25-A2

RASBJ<3.

RASBKO
-CAS15. -CASO

ON
BOARD
DRAM

MAIO-MAO
PAR3-PARO

-"'
-

BIOS
ROM
'---

,
VL62C331
ISABUS
CONTROLLER

COPROCINTF

'--

MD15·Moo

SAI6-SAO

.~
DEMUX

Two 82C59A Interrupt Controllers
One 82C54 Timer
One 82C018 Real Time Clock
• Additional 64 bytes of battery backed
RAM in RTC provides for non-volatile
storage of VL82C386 chip set configuration data and user specHic
information
• Supports 8- or 16-bit wide BIOS
ROMs
• Cache support for posted writes
• System Memory on MD or D bus in
non-cached systems
• Separate parity generation/checkers
for high speed operation
• Internal ItO programmable for 10- or
16-bit decode
• Three-state control pins added for
board level testability

ORDER INFORMATION

RESCPU. NPXINT
-RDYSYS

Two 82C37A DMA Controllers w~h
extended 74LS612 Page Register

VL82C386DX Chip Set

A20 TURBO RESET

S
L
0
T
S

MHzOSC
BUSCLKI
SLOTSTA ICTRL

Part Number

Package

1 - VL82C330-FC

Plastic Flatpack

1 - VL82C331-FC

Plastic Flatpack

1 - VL82C332-FC

Plastic Flatpack

Note: Operating temperature range is
O·C to +70·C.

LA23-LA17
SAlIl-SAO. BHE
KEYBD SPK
XD7·Xoo

-ROMS
2r-

~
OSC

,
CACHE
CONTROL
MD31·Moo

VL82C332
DATA
BUFFER

8015-500
E
X COMl_
T COM2_
E LPn_
R
KYBDN
IDE_
A

4-174

H
VL82Cl08
COMBO

Lotus 1-2-3'" is a registerd trademark of
IBM Corp.
LIM EMS 4.0'" is a registered trademark of Lotus Development Corp., Intel
Corp. and Microsoft Corp.

•

VLSI TECHNOLOGY, INC.

SECTION 5
SUPER XTCOMPATIBLE
DEVICES

Logic Products Division

•

VLSI TECHNOLOGY, INC.

•

VLSI TECHNOLOGY, INC.
VL82C031
SUPER XT-COMPATIBLE SYSTEM CONTROLLER

FEATURES

DESCRIPTION

• Supports 8086 or V30 CPU at 8 MHz
or 10 MHz zero wait state using
150 ns DRAMs

The VL82C031 provides the XT-compatible system with dual speed control.
8 MHz or 10 MHz. to operate the
system at peak performance. The
device also controls memory. 1/0.
parity. address paths. and data paths
as well as handling four channels of
direct memory access. The VL82C031
is available from VLSI Technology. Inc.
in an industry-standard plastic 100-pin
flatpack.

Provides either DRAM or SRAM
control
Supports up to 8M bytes of expanded
memory
Supports 256K or 1M bit DRAMs on
EMS memory
• Arbitrates the system bus among the
CPU. DMA. math coprocessor. and
DRAM memory refresh cycles
Provides four channels of 8 MHz DMA
as well as burst mode
RAM pin available to select static or
dynamic memory interface
Power down mode for low power
standby operation

The CMOS VL82C031 is the System
Controller device in the two-chip VLSI
XT-compatible chip set. The other
device is the VL82C032 1/0 Controller.
The chip set integrates logic on XTcompatible systems. Further. while
offering complete compatibility with the
Super XT architecture. the VLSI chip
set improves system performance by

allowing 10 MHz operation with no
''wait states· (using 150 ns DRAMS).
supports an additional 8M bytes of
memory using EMS (Expanded
Memory Specification) 4.0. controls
system speed as necessary for
optimum performance. and supports a
16-bit memory data bus.
The chip can be brought to a powerdown mode to conserve power. The
chip can then be woke up from powerdown mode by an external interrupt.
A third device. the VL82C037 VGA.
Video Graphics Controller. can also be
used in the Super XT-compatible
system and provides high resolution
graphics of up to 800 x 600 pixels with
16 colors. Graphic capabilities with this
resolution are usually found only on
more expensive systems.

BLOCK DIAGRAM
TIMER2 --------.r.iiiSClliiiNEc5Usl
HOINS -------~~~~~

SAOo.
SAD19

OREao. ---.....J'-------l
OREQ3
TSTDMA

-----,,--t
----tf--t

I-----,v

E=~J:===:::

CACKOCACK3
AEN
TC

"""":"'-"''--''''''---,

MA1-MA10
SRCSo.SRCS9

RAM256

RAS& ERAS

------ic+-=--l

SRA 14-SRA 19
CASH. CASl
SWEH,SWEL
ROMeS

So.s2 _ _""".....J....!....J....I't..... BHE
RESET
DACKE
INTA
NMI
SRDY
ALE
MDIR
MRO
MWR

J====~=======-~

SRE
PARO. PAR1
MREF
J:EAO
MRAS

CLKINO---toj
CLKIN1-----,

'-----'

lORD
IOWA

CMDEN
PCDIA
PCENH

PCENl
PCAlE
SELO, SEL1

ORDER INFORMATION
Part
Number

Package

VL82C031-FC

Plastic Flat ack

Note: Operating temperature range is O°C to +70°C.
5-3

•

VLSI TECHNOLOGY, INC.
VL82C031

SUPER XT-COMPATIBLE SYSTEM DIAGRAM (WITH VGA)

PC DATA
(8) BUS

VIDEO OUTPUT

SERIAL 1/0
PARALLEL 1/0
KEYBOARD
MOUSE

DISK DRIVE

-----t:=.:..:..:..:.::J

5-4

•

VLSI TECHNOLOGY, INC.
VL82C031

PIN DlAG RAM

[When pin 55 (RAM) is tied low, SRAM configuration.]

VL82C031

NP\NT
-NPBUSY
NMI
SRDY
SAD19
SAD18
SAD17
SAD16
SAD15
SAD14
VCC
SAD13
SAD12
SAD11
SAD10
GND
SAD9
SAD8
SAD7
SAD6
VCC
SAD5
SAD4
SAD3
SAD2
SAD1
SADO
-RO/GTl
-RO/GTO
AO
-BHE

100 99
1
2
3
4
5
6
7
8
9
10
11

SI
98

ClK
INO

SYS
ClK

CPU
CfK

TIM
Ei2

I G,D

ClK
INl

-RSTIN

I-HiINS I
91

RESET

J~tD

SElO

-CMDEN

I-INTA

I SE f l

1-IOrK I

81
80

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57

56
55
54
53

JSR~18 JSR~16 JSRl14 J-SR1CS1J G~D

MdlR
SRA19

PCAlE
-PCENH
-PCENl
PCDIR
-MRAS
-DACK1
-DACK2
-DACK3

78
77
76
75

TOP VIEW

ALE

12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
29
30
31

lOCH
RDY

SRA17

VCC
AEN
TSTDMA
INTR
DROl
DR02
DR03
GND
-ROMCS
-SRE
RAM
-MREF
-PARO
PARl
-DACKE

-S0E~\

}sRbs4JSRhs6J-SRbS8J
SRA15 -SRCSO -SRCS2 -SRCS3 -SRCS5 -SRCS7 -SRCS9

5-5

52
51
50

GND
TC
-MWR
-MRD
-lORD
-IOWR

WEH

VLSI TECHNOLOGY, INC.
VL82C031
PIN DIAGRAM

[When pin 55 (RAM) Is tied high, DRAM configuration.]

VL82C031

NPINT

-NPBUSY
NMI
SRDY
SAD19
SAD18
SAD17
SAD16
SAD15
SAD14
VCC
SAD13
SAD12
SAD11
SAD10
GND
SAD9
SAD8
SAD7
SAD6
VCC
SAD5
SAD4
SAD3
SAD2
SADl
SADO
-RO/GTl
-RO/GTO
AO
-BHE

I TI

100 99

SYS
ClK

CPU
CIK

CLK
INO

I ~r2 I

CLK
INl

RESET

SELO

INS

I~ICK I

SEll

lOCH
ROY

-eMDEN

I-Hi I~~~D I~NIA I

GjD

-ASTIN

81
80
79
78
77
76
75
74
73
72
71
70
69
68
67

1
2
3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MdlR

TOP VIEW

66
65
64
63
62
61
60
59
58
57

66
55
54
53
52

I-ER~S21-ER~SO

-ERAS3

I-Also I

-ERASl -RASl

MAl

~21

JND I

MA3

5·6

MA4

JA51
MA6

JA71
MA8

51
50

JA91-elsH I
MAlO -eASl

ALE
PCAlE
-PCENH
-PCENl
PCDIR
-DACKO
-DACKl
-DACK2
-DACK3
GND
TC
-MWR
-MRD
~ORD

-IOWR
VCC
AEN
TSTDMA
DROO
DROl
DR02
DR03
GND
-ROMCS
RAM256J1M
RAM
-MREF
PARO
PARl
-DACKE

•

VLSI TECHNOLOGY, INC.
VL82C031

SIGNAL DESCRIPTIONS [With Pin 55 (RAM) tied to low, SRAM configuration]
Signal
Name

Pin
Number

Signal
Type

-NPBUSY

NMI

Signal
Description
Busy - Is an active low signal connected directly to the -BUSY Signal of
NP8087 which is normally connected to the -TEST signal of the 8086
CPU. It is examined by the bus arbitrator logic internally to the VL82C031.

Non Maskable Interrupt - Is an active high signal to the CPU that there is
an exception caused by one of the following:
- memory parity error,

- 110 channel check signaled from the PC bus,
- 8087 interrupts (an unmasked exception has occurred).
SRDY

System Ready - This is an active high signal that acknowledges to the
CPU or 8087 at t3 or tW before t4 time that a data transfer for either
memory or 110 is complete.

SAD19-SAD16

4-7

I/O

Address Bus - These lines are the four most significant address lines for
memory operation. They are input lines when the CPU or 8087 is in
control. The chip starts driving these lines during DMA address time.

SAD15-SADO

8, 9, 11-14,
16-19,
21-26

I/O

Address and Data Bus - These lines are a time multiplexed address and
data bus corresponding to the AD15-ADO of 8086 and 8087 bus. The
VL82C031 monitors these lines during the time the CPU or 8087 is in
control of the bus. It will drive these lines during DMA address time.

-RQ/GTl

I/O

Request Grant Channell - Is an active low pulse signal connected directly
to -RQ/GTl of the 8087. This signal is used by the chip to request the bus
from the 8087. If the 8087 is not controlling the bus at that time, the
request will relay through -RQ/GTO of the 8087 which is connected to
-RQ/GTl of the CPU.

-RQ/GTO

I/O

Request Grant Channel 0 - Is an active low pulse signal connected directly
to -RQ/GTO of the CPU. This signal is used by the chip to request the bus
from the CPU if there is no 8087, otherwise it is inactive.

Address Line 0 - Is the latched version of address o. It is used along with
-BHE signal to distinguish 8/16 bit and odd/even byte operation.
-BHE

o
o

o
1
o

1
1

Operation
Word
(D15-DO)
Odd Byte (D15-D8)
Even Byte (D7-DO)
Not Used

-BHE

I/O

Byte High Enable - This is an active low signal used to enable data to the
most significant half of the data bus (D15-D8). It is an input line when the
CPU or 8087 is in control. The chip drives this signal during DMA time.

MDIR

Memory Direction - Controls memory write enable of memory devices and
also the data direction of the transceiver between the CPU and system
memory bus.

SRA16-SRA19

35-32

SRAM Address Bits 16-19 - If RAM is low, these bits drive an SRAM
address decoder for the Expanded Memory option. The combination of
SRA 16-SRA 19 is capable of selecting one of 15 32K X 8 SRAM banks
organized as a word wide for a total of 960K bytes (15 banks of 64K each).
Expanded memory is not selected if SRA 16-SRA19 are 1111.

SRA14, SRA15

37,36

SRAM Address Bits 14, 15 - If RAM is low, these are the two most significant address bits of the 32K X 8 SRAM.

5-7

•

VLSI TECHNOLOGY, INC.
VL82C031

SIGNAL DESCRIPTIONS
Signal
Name
-SRCSO- -SRCS9

-SWEH, -SWEL

Pin
Number
38-40,
42-48

50, 49

(SRAM Configuration Cont.)
Signal
Type

Signal
Description

Static RAM Chip Select Bits 0-9 - H RAM is low, these are Static RAM
Memory Chip Selects (active low). Each signal selects a bank of two 32K
X 8 SRAM chips for a total of 640K bytes of system memory.

Signal

Memory Space

-SRCSO
-SRCSl
-SRCS2
-SRCS3
-SRCS4
-SRCS5
-SRCS6
-SRCS7
-SRCS8
-SRCS9

00000 - OFFFF
10000 - 1FFFF
20000 - 2FFFF
30000 - 3FFFF
40000 - 4FFFF
50000 - 5FFFF
60000 - 6FFFF
70000 - 7FFFF
80000 - 8FFFF
90000 - 9FFFF

SRAM Write Enable (High & Low) - HRAM is low, these are active low
write enable signals for SRAM:
- -SWEH for odd byte,
- -SWEL for even byte.

-DACKE

DACK Enable - Is an active low control signal to enable either -DACK2 or
-DACK3 to the on-board floppy and hard disk controllers respectively. This
is a programmable signal based on the content of Chip Select Control Port
0065 (hex).

PARO, PARl

53,52

110

Parity Bits 0-1 - Are the memory parity bits (odd type) for even and odd
bytes of memory bank. Each parity bit is generated and written during a
memory write operation. Each parity bit is checked and errors are reported
by NMI to the system at the end of each memory cycle. PARO is the
memory parity bit for even bytes. PARl is the memory parity bit for odd
bytes.

-MREF

Memory Refresh - Is an active low signal indication of the refresh cycle. It
is inhibited when RAM is low.

RAM

RAM Select - Is an input signal which indicates the memory type used in
the system:
- RAM - low ~ Static RAM,
- RAM = high = Dynamic RAM.

-SRE

SRAM Read Enable - H RAM is low, it is an active low read enable signal
for SRAM memory.

-ROMCS

ROM Chip Select - Is an active low signal used to enable the ROM BIOS to
output data to the data bus.

DRal-DRa3

61-59

DMA Request Bits 1-3 - Are asynchronous active high channel request
inputs used by peripheral devices to obtain DMA service. -DACK will
acknowledge the recognition of DRa signals. These signals are compatible with the DRa signals of the 8237 DMA controller.

INTR

Interrupt Signal - Is a positive edge signal to release the system from an
idle state for power management.

TSTDMA

Test DMA Function - This signal is used for testing purposes of the internal
DMA controller. It should be tied low.
5-8

•

VLSI TECHNOLOGY, INC.
VL82C031

SIGNAL DESCRIPTIONS (SRAM Configuration Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

AEN

Address Enable - Is an active high signal during the DMA cycle to disable
any 1/0 devices from the 1/0 channel to allow DMA transfers to take place.

-IOWR

I/O Write Command - Is an active low signal to instruct an 1/0 device to
read the data present on the data bus.

-lORD

1/0 Read Command - Is an active low signal to instruct an 1/0 device to
drive its data on the data bus.

-MRD

Memory Read Command - Is an active low signal to instruct the memory to
drive its data on to the data bus.

-MWR

Memory Write Command - Is an active low signal to instruct the memory to
store the data present on the data bus.

I/O

Terminal Count - Is an active high pulse signal when any DMA transfer is
completed. It can be driven from the 1/0 channel to terminate a current
DMA cycle.

DMA Acknowledge Bits 1-3 - Are active low signals to notify the requesting
peripherals when one has been granted a DMA cycle. These signals are
compatible with the OACK signals of the 8237 OMA controller.

-DACK1- -DACK3

74-72

-MRAS

Memory Signal Timing - Is an active low control signal to indicate a system
memory cycle.

PCDIR

PC Data Bus Direction - Is the direction signal to the data transceiver between the CPU and PC data bus:
- high means the CPU drives the PC data bus (write cycle).
- low means the PC drives the CPU data bus (read cycle).

-PCENl

PC Data Byte low Bus Enable - Is the active low control signal to enable
the data buffer (07-00) between the CPU and PC data bus.

-PCENH

PC Data Byte High Bus Enable - Is the active low control signal to enable
the data buffer (015-08) between the CPU and PC data bus.

PCAlE

PC Address latch Enable - Is an active high pulse active during t1 of any
bus cycle. It is similar to the ALE signal except that this signal is active
high throughout the OMA cycle.

ALE

Address latch Enable - Is an active high pulse active during t1 of any bus
cycle including OMA and memory refresh cycles. The CPU address
should be latched using the ALE falling edge.

10CHRDY

1/0 Channel Ready - Is an active high ready signal from an 1/0 channel.
Memory or I/O devices can pull this signal low to lengthen memory or I/O
cycles. For every system clock cycle this signal is low. one wait state is
added.

-lOCK

110 Channel Check - This signal should be pulled low for at least two
system clock cycles to indicate an uncorrectable error on an 1/0 channel.
This signal causes a Non Maskable Interrupt if NMI is enabled.

-CMOEN

Command Enable - Is the active low control signal to enable the command
buffer going to the 1/0 channel bus (PC Bus). It is used to prevent bus
contention between the 1/0 devices that share the same address space in
the X bus and in the 1/0 channel bus.

5-9

•

VLSI TECHNOLOGY, INC.
VL82C031

SIGNAL DESCRIPTIONS (SRAM Configuration Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

SElO,SEl1

85,84

Select Function (0·1) - These are special select decoders for address
range according to the following table:
SEl1

SElO

o
1
o

o
o
1
1

Range
Don't Care
A15-A10 = 0 (I/O)
ROM
Video RAM

-INTA

Interrupt Acknowledge - This pin is an active low signal used to enable the
interrupt controller's interrupt-vector data on to the data bus.

RESET

Reset - Is an active high signal synchronized to the system clock to reset
the CPU and system.

PWRGOOD

Power Good - Is an active high Schmitt Trigger input signal (TTL level of
2.4 to 5.25 Vdc during normal operation, or an inactive level of 0.0 to 0.4
Vdc) coming from a power supply to indicate that power is stable.

-RSTIN

Reset Input - Is an active low signal which is used to generate the RESET
signal. The Vl82C031 provides a Schmitt Trigger input so that an RC
connection can be used to establish the power on reset of proper duration.

-HDINS

Hard Disk Installed - Is the status signal that the hard disk is installed on
the system. This can be read at 1/0 port 62 bit 2.

ClKIN1

Clock Input 1 - Is a 30 MHz TTL clock input with 40/60% duty cycle. It is
used for a system clock with the CPU running at 10 MHz. It should be
pulled high if there is no clock source to this pin.

ClKINO

Clock Input 0 - A 24 MHz TTL clock input with 40/60% duty cycle. It is
used for the system clock with the CPU running at 8 MHz, internal DMA
control, and memory refresh timing.

TIMER2

Timer2 Status - Is the status signal on the 8253 Timer Channel 2 which
comes from Vl82C032. This is can be read at 1/0 port 62 bit 5.

SYSClK

System Clock - Is the MOS driven clock signal to the 8087 and system. It
has a 33% duty cycle (67-low, 33-high).

CPUClK

CPU Clock - Is a MOS driven clock signal to 8086 or NEC V30 CPU. The
clock speed can be selected through a special register. The duty cycle of
CPU clock is 33% (67-low, 33-high).

S2·S0

99·97

System Status - These are Schmitt Trigger input signals used to decode
different CPU or 8087 operations.
S2-S0

Operation
Interrupt Acknowledge

000
001
010
011
100
101
110
111

110 Read
110 Write
Halt
Memory Read (fetch)
Memory Read (data)
Memory Write
Passive

5-10

•

VLSI TECHNOLOGY, INC.
VL82C031

SIGNAL DESCRIPTIONS (sRAM Configuration Cont.)
Signal
Name

Pin
Number

NPINT

100

BOB7 Numerical Processor Interrupt - An active high signal that indicates
that an unmasked exception' has occurred during numeric instruction
execution when BOB7 interrupt is enabled.

VCC

65,20,10

Power-+5 V

GND

92,71,41,
5B, 15

Ground

Signal
Type

Signal
Description

SIGNAL DESCRIPTIONS

[For pins which operate differently in DRAM configuration (Pin 55 tied high)]

Signal
Name

Pin
Number

Signal
Type

Signal
Description

-ERASO- -ERAS3

35-32

EMS Row Address Strobe Bits 0-3 - If RAM is high, these are active low
-RAS signals for Expanded Memory option to the system:
Pin

Odd

Even

-ERASO

256K (1M)

-ERAS1

256K (1M)

-ERAS2

256K (1M)

-ERAS3

256K (1M)

-RASO, -RAs1

37,36

Row Address Strobe Bits 0-1 - If RAM is high, these are active low control
signals to the 640K byte DRAM system memory to inform the memory that
a row address is present on the address bus. -RASa is for the first 128K
and -RAS1 is for the next 512K of memory.

MA1-MA10

3B-40,
42-4B

Memory Address Bit 1-10 -If RAM is high, these are time multiplexed row
and column memory address lines for 1M memory chips (for 256K memory
chips MA 10 is not used.)

-CASH- -CASL

49 ,50

Column Address Strobe (High & Low) - If RAM is high, these are active low
control signals to the on-board DRAM system and EMS memory to signal
that a column address is present on the address bus:
- -CASH for odd byte [0(15-8)],
- -CASL for even byte [0(7-0)].

-MREF

RAM

Memory Refresh - Is the active low signal indication of the refresh cycle. It
is inhibited when RAM is low.
RAM Select - Is an input signal to tell the chip of the memory type used in
the system:
- RAM = low = Static RAM,
- RAM = high = Dynamic RAM.

RAM256/1M

256K or 1M - If RAM is high, this is the signal which informs the chip of the
memory type used in expanded memory:
- low means 1M chips,
- high means 256K chips.

5-11

•

VLSI TECHNOLOGY, INC.
VL82C031

SIGNAL DESCRIPTIONS (DRAM Configuration Cont.)
Signal
Name

Pin
Number

DROO-DR03

62-59

-DACKO- -DACK3

75-72

Signal
Type

Signal
Description

DMA Request B~s 0-3 - Are asynchronous active high channel request
inputs used by peripheral devices to obtain DMA service. -DACK will
acknowledge the recognition of DRO signals. These signals are compatible with the ORO signals of the 8237 DMA controller.

DMA Acknowledge Bits 0-3 - Are active low signals to notify the requesting
peripherals when one has been granted a DMA cycle. These signals are
compatible with the DACK signals of the 8237 DMA controller.

FUNCTIONAL DESCRIPTION
SYSTEM MEMORY AND 110 MAP
The 80861V30 supports 16-bit operations with 20-bit addressing to directly
access up to 1M byte of memory space.
The system memory and an On-board
Expanded Memory (if H's enabled) are
byte and/or word accessible. Memory
is mapped in Table 1.

support either 256K or 1 M byte memory
chips depending on how the RAM256/
1M input signal is strapped. The EMS
logic will control on-board memory up to
2M bytes if 256K memory is used and
up to 8M bytes if 1M chips are used
(see RAM256/1 M input definition in the
VL82C031 Signal Descriptions).

MEMORY CONTROL UNIT
VL82C031 offers either Dynamic or
Static RAM memory control depending
on the RAM input signal with zero wa~
states for 150 ns memory access.

If the "RAM" pin is strapped low (to
Ground), the VL82C031 will generate
SRAM memory control. It supports
640K bytes of system memory using
32K X 8 SRAM chips. It also supports
an EMS SRAM up to 960K (1 M minus
64K) bytes of 32K X 8 type memory. It
provides four address lines (SRA 16SRA 19) that can select one out of 15
banks of memory (64K bytes each).
When EMS SRAM is not accessed,
SRAI6-SRAI9 will be all l's so only 15
banks can be selected.

If the "RAM" pin is strapped high (to
VCC), the VL82C031 will generate onboard DRAM memory control signals. It
supports 640K bytes of system memory
using 64K X 4 DRAM for the first 128K
bytes and 256K X 1 DRAM for the next
512K bytes of memory. In addition to
640K bytes, the VL82C031 also
supports EMS 4.0 which makes multitasking possible. The EMS logic will

The Memory Control Unit has the
following five functions:
1.
2.
3.
4.
5.

System Memory Control
EMS Control
Memory Refresh Control
Memory Parity Check and Generator
Rowand Column Address Generator

SYSTEM MEMORY CONTROL
FOR DRAM CONTROL: The system
memory controller generates RAS
signals for 640K of readlwrite memory:
- -RASO is for the first 128K of
memory,
- -RASI is for the next 512K of
memory.
FOR SRAM CONTROL: The system
memory controller generates 10 SRAM
chip selects (-SRCSO-SRCS9) as
shown in Table 2 and readlwrite control
signals (-SRE, -SWEH, -SWEL).

TABLE 1. FUNCTIONS

TABLE 2. MEMORY

Hex Address

Description

Signal

Memory Space

00000 - 1FFFF
20000 - 2FFFF
30000 - 3FFFF
40000 - 4FFFF
50000 - 5FFFF
60000 - 6FFFF
70000 - 7FFFF
80000 - 8FFFF
90000 - 9FFFF
AOOOO - BFFFF
COOOO - EFFFF
FOOOO - FFFFF

128K
64K
64K
64K
64K
64K
64K
64K
64K
128K
192K
64K

-SRCSO
-SRCS1
-SRCS2
-SRCS3
-SRCS4
-SRCS5
-SRCS6
-SRCS7
-SRCS8
-SRCS9

00000 10000 20000 30000 40000 50000 60000 70000 80000 90000 -

byte:
byte:
byte:
byte:
byte:
byte:
byte:
byte:
byte:
byte:
byte:
byte:

1st bank #1 .....
2nd bank #2
2nd bank #3
2nd bank #4
640K
2nd bank #5
System
2nd bank #6
Memory
2nd bank #7
2nd bank #8
2nd bank #9
Video Buffe-(
Reserved for BIOS on I/O Channel.
System ROM
5-12

OFFFF
1FFFF
2FFFF
3FFFF
4FFFF
5FFFF
6FFFF
7FFFF
8FFFF
9FFFF

•

VLSI TECHNOLOGY, INC.
VL82C031

The controller can allocate system
memory through the Planar RAM
Control Register at Port 006B. If the
first 128K bytes of memory are not
installed or bad, the system can remap
the next 512K bytes over. Also, each
64K block of the second bank (except
the first two blocks) can be enabled or
disabled so the system can allocate
memory between system memory and
expanded memory.
If bit a of the Planar RAM register is 0,
-RASa or -8RCSO-SRCSI will be
active at memory space 00000 - 1FFFF
(128K bytes), and -RASI or-SRCS2-SRCS9 will be active at memory space
20000 - 9FFFF (512K byte) for 640K
bytes of system memory.
If bit a is 1, memory bank a is disabled
(-RASa or -SRCSO- -SRCS1), and the
physical memory at addresses 80000 9FFFF will be mapped to memory
space 00000 -IFFFF. Thus, -RASI or
-SRCS2- -SRCS9 will be active in
memory space 00000 - 7FFFF for 512K
bytes of system memory.
The format of the Planar RAM Cantrall
Status Register is as follows:
Planar RAM Control Register: I/O Port
006B (hex) RN-J:
Bit
7

6
5
4
3
2
1
a

Function
Parity Check Pointer
1 = Lower 128K failed
a = Upper 512K failed
DIS/EN- RAM, 90000 - 9FFFF
DIS/EN- RAM, 80000 - 8FFFF
DIS/EN- RAM, 70000 - 7FFFF
DISIEN- RAM, 60000 - 6FFFF
DISIEN- RAM, 50000 - 5FFFF
DIS/EN- RAM, 40000 - 4FFFF
MAP/UNMAP- Low Memory
At power-on or reset, this port
is 00.

If the EMS memory happens to be
selected in the system memory space,
-RASa and -RAS 1 or -SRCSO-SRCS9 will be blocked. Both -RASa
and -RASI will be asserted during REFRESH. REFRESH is inhibited if
"RAM" is low.
Bit 7 of Planar RAM Control Register
will be set (1) or clear (0) according to
the most recent parity bit error:

parity error, bit 7 will be set.
- If the current memory read cycle is in
the next 512K memory and caused
a parity error, bit 7 will be cleared.
- If there is no parity error, bit 7 will
remain unchanged.
- Writing a 1 to bit 7 of this port will
reset this bit. Writing a a to this bit
has no effect.
This feature is primarily intended for use
in memory testing and is not particularly
useful for post-mortem diagnostics.
EMS CONTROL
The EMS Control consists of EMS
Current Map, EMS Alternate Map, and
the EMS RAS generator.
The Current and Alternate Maps are 36
word by 10 bit register files each
containing an enable bit and the
physical address bits 22-14 of the EMS
memory. The memory space is
logically broken down to 64 blocks of
16K bytes each. However, the first
256K of system memory (00000 3FFFF), Video memory (40000 BFFFF), and ROM BIOS (FOOOO FFFFF) are reserved. That leaves two
areas of memory: 40000 - 9FFFF and
COOOO - EFFFF mappable to EMS.
Each block of 16K bytes can be
mapped to any of n blocks of EMS
memory. (If RAM256/1 M is high, n =
128. If RAM256/1M is low, n = 512.)
EMS can access up to 2M or 8M bytes
of DRAM depending on the state of
RAM256/1M.

If SRAM is used (i.e. Pin 55 is tied low)
the maximum EMS memory will be 1M
minus 64K (960K) bytes of SRAM, that
is n = 60.
The EMS Current Map is a 36 word by
10 bit register file that translates A 14A 19 during memory cycles to an EMS
memory address. The EMS Current

Memory Map can be accessed through
three 110 ports:
CMPR - Current Map Pointer Register
8-bit 110 RN-J
CMDR - Current Map Data Register
16-bit 110 RN-J
The CPU performs an 1/0 write to
CMPR with a pointer to the current
map. After that, the CPU performs I/O
reads or writes to CMDR.
The CMPR and CMDR formats are:
CMPR: I/O Port 0011
Bit
7,6
5-0

CMDR: I/O Port 0012
access only:
Bit
15-10
9
8
7
6
5
4
3
2

0
1
1

256/1M

X
a
1

Type of Memory
32K X8SRAM
1M DRAM
256K DRAM

X = Don~ Care

- If the current memory read cycle is in
the first 128K memory and caused a
5-13

RN-J word

Function
Not Used
Map Address 22 for EMS
Memory
Map Address 21 for EMS
Memory
EN/DISMap Address 20 for EMS
Memory
Map Address 19 for EMS
Memory
Map Address 18 for EMS
Memory
Map Address 17 for EMS
Memory
Map Address 16 for EMS
Memory
Map Address 15 for EMS
Memory
Map Address 14 for EMS
Memory

The type of memory and map address
bits used in EMS are determined by the
RAM and RAM256/1 M input pins as
shown in Table 3.

TABLE 3_ MEMORY CONFIGURATION OPTIONS
RAM

RIW:

Function
Not Used
Current Map Panter

Map Bits Used
14-19
14-22
14-20

•

VLSI TECHNOLOGY, INC.
VL82C031

When RAM is low, and during EMS
memory access, SRA14-SRA19 are
identical to the map address. SRA14SRA 19 are all high if the access is not
in EMS memory.
CMDR bit 7: EN/DIS- is used to enable
or disable mapping of the logical
memory address space to the EMS
memory area. If this bit is set to 1, it will
use the map address 21-14 during the
memory access time to map to the EMS
memory, otherwise it will be unmapped
and either system memory or memory
on the 110 channel will be accessed.

Bit
15-10
9
8
7
6
5
4
3

Current Map and/or Akernate Map to
function. Otherwise, the EMS memory
is not accessible. However, the EMS
Current and Alternate Memory Maps
are always accessible. If both bit 0 and
1 are set to 1's, the Current Memory
Map will be used. See Table 4.

If one of the maps is selected but the
EN/DIS- bit for the current page is 0,
the memory access will go to CPU
system memory, or the 110 channel if
that address space is disabled through
the Planar RAM Control Register.
The EMS RAS signals are always
generated during memory refresh. At
power-on or reset, bits 0 and 1 are O's.

The EMS Alternate Map is a 36 word by
10-bit register file that translates A 14A19 during DMA memory cycles to the
EMS memory. The EMS Alternate
Memory Map can be accessed through
three 110 ports:

AMPR - Alternate Map Pointer Register
8-bit 110 RIW
AMDR - AHernate Map Data Register
16-bit I/O RIW

The type of memory and map address
bits used in EMS are determined by the
same system as with the current map.
See Table 3.

The CPU performs an 110 write to
AMPR with a pointer to the alternate
map. After that, the CPU performs 110
reads or writes to AMDR.

The EMSEN 110 port enables or disables the EMS Current or Alternate
Memory Map during CPU or NPU
accesses:

The AMPR and AMDR formats are:

EMSEN:

AMPR: 110 Port 0015

Bit
7-2
1

Bit

7, 6
5-0

RIW:

Function
Not Used
Alternate Map Pointer

AMDR: 110 Port 0016
access only:

RlWword

110 Port 0010

o
o
1
1

o
1

EMDMA
Bit
7
6
5
4

RIW:
3

Function
Not Used
EN/DIS- Alternate Map
EN/DIS- Current Map

Bit 0 and 1 of this port are Master EMS
Enable bits used to enable or disable
the EMS memory access function
during the CPU or NPU memory access
cycles. Writing a 1 to the EMSEN port
bit 0 and/or bit 1 enables the EMS

TABLE 4. GLOBAL EMS MAPPING
EMSEN Bit
1
0

EMDMA is an 110 port used to tag any
DMA channel to the Current or Alternate Map access during the DMA cycle:

110 Port

0014

There are four pairs of bits: 0,4; 1,5;
2,6; 3,7 that are related directly to each
channel of the DMA in map selection

TABLE 5. EMS DMA ASSIGNMENT
EMDMA Bits

Map of EMS Memory Access
During CPU or NPU Access cycles

0,4; 1,5; 2,6; 3,7

None
Current Map
Alternate Map
Current Map

0,0
1,0
0, 1
1,1

Map of Memory Access
During DMA Cycles
None (map to system
memory or 110 channel)
Alternate Map
Current Map
Alternate Map

At power-on or reset, EMDMA = 00.

5-14

RIW:

Function
EMCDMA3 : EN/DIS- Current
Map during DMA Channel 3.
EMCDMA2: EN/DIS- Current
Map during DMA Channel 2.
EMCDMA1 : EN/DIS- Current
Map during DMA Channel 1.
EMCDMAO : EN/DIS- Current
Map during DMA Channel O.
EMADMA3 : EN/DIS- Alternate
Map during DMA Channel 3.
EMADMA2 : EN/DIS- Alternate
Map during DMA Channel 2.
EMADMA1 : EN/DIS- Alternate
Map during DMA Channel 1.
EMADMAO : EN/DIS- Alternate
Map during DMA Channel O.

•

VLSI TECHNOLOGY, INC.
VL82C031

during each DMA cycle. The function of
those bits are defined in Table 5.
If one of the maps is selected but the
ENID IS- bit for the current page is 0,
the memory access will go to CPU
system memory, or the 110 channel if
that address space is disabled through
the Planar RAM Control Register.
The EMS RAS Generator takes the
content of CMDR or AMDR during
memory access and generates the
EMS RAS signals:
-

ERASO:
ERAS1:
ERAS2:
ERAS3:

For EMS
For EMS
For EMS
For EMS

Bank O.
Bank 1.
Bank 2.
Bank 3.

Bit
7
6
5
4
3

1/0 Port 0018

o
EMST:
Bit
7
6
5

EMST: The EMS Parity Status Port
Register is an eight bit 110 read only
port used to identify the source of EMS
parity errors if the EMS function is
enabled:
EMST:

3
2

Read:

Function
EMSERR: EMS memory
parity error.
Not Used
ODD BYTE : Odd byte is bad, if
EMS ERR is set.
EVEN BYTE : Even byte is
bad, if EMSERR is set.
EMSBNK3 : EMS memory
bank 3 is bad, :~ EMSERR is
set.

EMSBNK2 : EMS memory
bank 2 is bad, if EMSERR is
set.
EMSBNK1 : EMS memory
bank 1 is bad, if EMS ERR is
set.
EMSBNKO : EMS memory
bank 0 is bad, if EMS ERR is
set.

1/0 Port 0018

Write:

Function
ENID IS- : EMS memory parity
error.
Not Used
ENID IS- : Odd parity byte, if
EMS ERR is set.
ENID IS- : Even parity byte, if
EMS ERR is set.
ENID IS- : EMS memory parity
bank 3, if EMSERR is set.
ENID IS- : EMS memory parity
bank 1, if EMS ERR is set.
ENID IS- : EMS memory parity
bank 1, if EMSERR is set.
ENID IS- : EMS memory parity
bank 0, if EMSERR is set.

Writing 0 to these bits will reset the
corresponding parity bits to O.
At power-on or reset, EMST = 00.
The mapping registers are implemented
internally as static RAM register files,
and can be disabled to reduce power

VL82C031 1/0 MAP
110 Address

Function

Response

0000 - OOOF

DMA Controller

RIW

0010 - 001 F

System Control and Status Group 1

RlW

Planar RAM Control

RIW

006B
0081 - 0087
03BO - 03DF

DMA Page Registers

RIW

Video System

On-Board
Decoder

5-15

consumption for applications such as
laptop computers. This is done by
writing a 1 to 110 Port IEh to enable the
funtion, and then writing a 1 or 0 to 110
Port 1Ch to enable or disable the
register banks, respectively. Reading II
Port 1Ch at this point will disable the
register banks and stop the CPUCLK
output. An active signal on the INTR
input (pin 62) will then restart the CPU
clock. During the shutdown period the
SYSCLK output continues to run.

CLOCK CONTROL
The speed and duty cycle of the clock
outputs can be controlled through the
Clock Control Register which resides at
1/0 Port 19h.
Clock Control: 1/0 Port 0019
Bit
7-3
2

R/W:

Function
Not Used
CPUCLK Duty Cycle - 0 = 33%,
1 =50%
Divider Select - 0 = +6, 1 = +3
Clock Select - 0 = CLKINO, 1 =
CLKIN1

Both of the clock outputs (CPUCLK and
SYSCLK) are affected by clock input
and clock divider selection. Only the
CPUCLK is affected by duty cycle
selection.

•

VLSI TECHNOLOGY, INC.
VL82C031

FIGURE 1_ EMS MAPPING REGISTERS
EMS Memory (8M)

CPU Address Space (1 M)

Page 1FF
64K

Page 1FE
Mapping Registers

Page 1FD
Index 3B

12
PAGES
(192K)
I

Index 31

I - - - - - - - i C4000-C7FFF

Index 30

COOOO-C3FFF

128K

512
Pages

Index 27
Index 26
Index 25

24
PAGES
(384K)

48000-4BFFF

Index 12

44000-47FFF

Index 11

40000-43FFF

Index 10

256K
Page 001
Page 000

""-";;;;;"';-'-"'__~ 0-3FFFF

5-16

•

VLSI TECHNOLOGY, INC.
VL82C031

MEMORY REFRESH CONTROL
The Memory Refresh Timer generates a
request every 15.6 ILs to the Refresh
Controller. Once the Refresh Controller
grants the cycle (-MREF is asserted), it
outputs the ALE, PCAlE, and -MRD
signals. The minimum refresh cycle is
five system clocks for a system running
at 8 MHz or six system clocks for a
system running at 10 MHz.
The Memory Refresh Address Generator drives all 20 address lines through
the CPU bus during memory refresh
cycle time (-MREF is low). Address 08 comes from a 9-bit binary counter
(which will increment at the end of the
cycle), and A9-A19 is driven low during
the memory refresh cycle.

DMACONTROL
DMA Control consists of two blocks:
- 8237-Compatible DMA Controller
- DMA Page Registers
The DMA Controller is a four channel
DMA operating at 8 MHz which supports byte (8-bits) transfer operations
between memory and peripherals. Its
function is equivalent to the 8237 DMA
chip. The DMA channels are assigned
as shown in Table 6.
Each channel can transfer data
throughout the 1M byte system address
space up to 64K bytes at a time. The
following figure shows address generation for the DMA channels.
Source

DMA Page Registers

Address

A19-4

•

Three DMA channels (1, 2, 3) are
available on the 110 channel. The 8237
DMA controller command code addresses are shown in Table 8.
DMA PAGE REGISTER
DMA Page Registers can be accessed
through four 8-bit 110 ports. These
ports are read/write and only data bits
0-3 are significant. Table 7 shows the
addresses for the page registers.
Addresses for all DMA channels cannot
increase or decrease through page
boundaries (64K bytes).

Controller

A16 A1S ..... AO

Note: The addressing signal, 'byte high
enable' (-BHE), is generated by
inverting address line AO.

TABLE 7. PAGE REGISTERS

TABLE 6. DMA CHANNELS
Channel
ChannelO:
Channell:
Channel2:
Channel3:

Assignment
DROO
DROl
DR02
DR03

Reserved
Not Used
Diskette
Fixed Disk

Page Register

I/O Address
(In Hex)

DMA Channel 0
DMA Channell
DMA Channel 2
DMA Channel 3

0087
0083
0081
0082

TABLE 8. DMA CONTROLLER REGISTER FUNCTIONS
110 Address (In Hex)
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
OOOA
OOOB
OOOC
0000
OOOE
OOOF

Register Function
Channel 0 Base and Current Address Register
Channel 0 Base and Current Word Count
Channell Base and Current Address Register
Channell Base and Current Word Count
Channel 2 Base and Current Address Register
Channel 2 Base and Current Word Count
Channel 3 Base and Current Address Register
Channel 3 Base and Current Word Count
Read Status Register/Write Command Register
Write Request Register
Write Single Mask Register Bit
Write Mode Register
Clear Byte Pointer Flip-Flop
Read Temporary Register/Write Master Clear
Clear Mask Register
Write All Mask Register Bits .

5-17

•

VLSI TECHNOLOGY, INC.
VL82C031

REGISTER BIT DIAGRAMS
PLANAR RAM CONTROL REGISTER
Address=OOSBh (ReadlWrite)
171 sis 1 4 1 3 1 2 1 1 1 0 1
Map/Unmap Low Memory
DIS/EN 40000-4FFFF
DIS/EN SOOOO-SFFFF
DIS/EN SOOOO-SFFFF
DIS/EN 70000-7FFFF
DIS/EN 80000-8FFFF
DIS/EN 90000-9FFFF
Parity Check Bit

CURRENT MAP POINTER REGISTER
Address=0011 h (ReadIWrite)
171sIs141312111 0 1

~---

Current Map Pointer
Not Used

CURRENT MAP DATA REGISTER LOW
Address=0012h (Read/Write)
171 sis 1 4 1 3 1 211 1 0 1

'------

L - .- - - - - - - - -

Map Address Bits 14-20
EN/DIS

CURRENT MAP DATA REGISTER HIGH
Address=0013h (Read/Write)
171sIs141312111 0 1

L - .- - - - - -

Map Address Bits 21 & 22
Not Used

ALTERNATE MAP POINTER REGISTER
Address=001Sh (ReadlWrtite)
. 171 sis

I4 I3 1 2 I 1 1 0 1

- - - - Alternate Map Pointer
Not Used

5-18

•

VLSI TECHNOLOGY, INC.
VL82C031

L--____

L - .- - - - - - - - -

Map Address Bits 14-20
ENID IS

ALTERNATE MAP DATA REGHISTER HIGH
Address=0017h (Read/Write)
17161514131211101

L - Map Address Bits 21 & 22

I
L - .-

Not Used

EMS ENABLE REGISTER
Address=0010h (Read/Write)
17161514131211101

IL
L--_ _ _ _ _ _

ENID IS Current Map
ENIDIS Alternate Map
Not Used

EMS DMA ASSIGNMENT REGISTER
Address=0014h (Read/Write)

II I I '--

17161514131211101

L--_ _ _ _ _ _
L - -_ _ _ _ _ _ _

L--_ _ _ _ _ _ _ _ _

",mat,

ENiOIS
M.p Qu,'ng Chaon,' OMA
ENIDIS Alternate Map During Channell DMA
ENIDIS Alternate Map During Channel'2 DMA
ENIDIS Alternate Map During Channel 3 DMA
ENIDIS Current Map During Channel 0 DMA
ENIDIS Current Map During Channell DMA
ENIDIS Current Map During Channel 2 DMA
ENIDIS Current Map During Channel 3 DMA

5-19

•

VLSI TECHNOLOGY, INC.
VL82C031

17161514131211101

II [ I '- ~:;~: ~~~ ::::: :

Parity, EMS Bank 2
Parity, EMS Bank 3
Parity, Even Byte
' - - - - - - - - Parity, Odd Byte
L -_ _ _ _ _ _ _ Not Used
L -_ _ _ _ _ _ _ _ EMS Parity Error

EMS PARITY ENABLE REGISTER
Address=0018 (Write Only)

17161514\31211101

Enable Parity, EMS Bank 0
Enable Parity, EMS Bank 1
Enable Parity, EMS Bank 2
Enable Parity, EMS Bank 3
Enable Parity, Even Byte
Enable Parity, Odd Byte
Not Used
Enable EMS Parity Error

CLOCK CONTROL REGISTER
Address=0019h (ReadIWrite)

171 61 5 14 13 1211 1 0 1

IL=

Clock Select
Divider Select
CPUCLK Duty Cycle
Not Used

STANDBY ENABLE REGISTER
Address=001 Eh (Read/Write)

171 6 I 5 14 I 3 12 I 1 10 1
1
L

Standby Enable Bit
....- - - - - - Not Used

STANDBY CONTROL REGISTER
Address=001 Ch (Read/Write)

17161514131211101
1
L
1 . . . .-

Standby Control Bit
Not Used

5·20

•

VLSI TECHNOLOGY, INC.
VL82C031

AC CHARACTERISTICS:

= O°C to +70°C, VCC = S V ±S%, GND = 0 v

Symbol

Parameter

Min

tCYC

SYSCLK, CPUCLK Cycle Time

100

tCl

CLKINO Cycle Time

24 MHz

Max

Unit

Condition

tC2

CLKINl Cycle Time

30 MHz

tC3

SYSCLK High Time

33% Duty Cycle

tC4

SYSCLK Low Time

tCS

tC6

CPUCLK High Time

CPUCLK Low Time

33% Duty Cycle

50% Duty Cycle

33% Duty Cycle

50% Duty Cycle

SYSCLK to Command

lO8

SYSCLK Low to ALE, PCALE High

tD9

SYSCLK High to ALE, PCALE Low

lOl0

SYSCLK to SRDY

lOll

SYSCLK Low to Address on I/O Channel

tSU12

Data Valid before t4 during Read

tH13

Data Invalid after End of t3 during Read

lO14

Data from End of tl during Write

lO15

Memory Row Address Valid from SYSCLK Low

100

lO16

Memory Column Address Valid from SYSCLK Low

lO17

SYSCLK to -RAS

tD18

SYSCLK to -CAS

tD19

Memory Data Valid from -RAS

155

tD20

Memory Data Valid from -CAS

tSU21

Memory Data Valid before t4

20
20

ns
75

tH22

Memory Data Invalid after -CAS

lO23

Memory Data Valid after SYSCLK Low during Write

tH24

Memory Data Hold Time after -CAS

ns
ns
#5

ns
ns

lO25

Request/Grant from SYSCLK Low

lO26

Refresh after SYSCLK Low

lO27

PCALE after SYSCLK High during Refresh

tD28

Memory Refresh Address after PCALE

lO29

-RO/GT Request from DRO

t30

DRO Hold Time after -DACK

lO31

PCALE High from -RO/GT Grant

25
2tCYC

5-21

ns
ns

•

VLSI TECHNOLOGY, INC.
VL82C031

AC CHARACTERISTICS:

(Cont.)

Symbol

Parameter

tH32

Data Hold Time from t4 SYSCLK High during Write

tD33

PCALE Low from End of DMA Command

tD34

AEN High from -RQ/GT Grant

tD35

AEN Low from End of DMA Command

tD36

-DACK Low from AEN

tD37

-DACK High from End of DMA Command

tD38

DMA Address Valid from AEN

tD39

-MRD, -lORD Active from AEN

tD40

-MWR, -IOWR Active from -MRD, -lORD

Unit

t41

-MWR, -IOWR Command Width

4tDCY

t42

-MRD, -lORD Command Width

6tDCY

tD43

Max

Min

21/2 tDCY
+35

1/2 tDCY
+35

21/2 tDCY
+35

3tDCY
+70

112tDCY
+40

3tDCY
+30

31/2 tDCY
+35

2tDCY

tDCY=DMA Cycle Time
Min 125 ns

ns
ns
2tDCY'

End of DMA Command to -RQ/GT Release

Condition

MAXIMUM OUTPUT CAPACITANCE LOADING
Pinout
CPUCLK
SYSCLK
RESET

Capacitance
Loading (pF)
20

Capacitance
Loading (pF)

Pinout
-MRO

Pinout

Capacitance
Loading (pF)

-ERAS1

20
20

-lORD

-ERAS2

200

-IOWR

-ERAS3

200

MOIR

-SHE

-INTA

AEN

SELO

-ROMCS

SEL1

-MREF

200

-CMDEN

PARO

100

-RQ/GTO

ALE

PARi

100

-RQ/GT1·

PCALE

-OACKE

SA019-SADO

-PCENH

-CASL

SROY

-PCENL

-CASH

NMI

PCDIR

MA1-MA10

200

-RASO

-RAS1

-MWR

-ERASO

-OACK3- -OACKO

5-22

•

VLSI TECHNOLOGY, INC.
VL82C031

TIMING CHARACTERISTICS
FIGURE 2. CLOCK TIMING
~tC1/tC2

CLKINO/CLKIN1
SYSCLK {+6)------"=I
tC3
1,--- \

SYSCLK (+3) _

CPUCLK (+6, 33%) CPUCLK (+6, 50%)

----=

~1L-_ _ _ _~11

I'---j--~\\~------------- I

ir--+--r-i-ll'__+-__

tC5

tC6

--I

CPUCLK {+3, 33%)-----..::J b==~"lct-------="';"j
tC5

tC6

b~t------::-;F
CPUCLK (+3, 50%) - . £
1-

•

5·23

•

VLSI TECHNOLOGY, INC.
VL82C031

FIGURE 3. READ CYCLE TIMING DIAGRAM FOR 1/0 CHANNEL

CPUCLK
PCALE _ _+-'I
-MRD
-lORD - - - - 1 - - - - - - , 1
(MEMORY OR 1/0 READ)
I'-----------+-----t--IJ
SRDY _ _-+-________________~

ADDRESS----~~--_rrrrTr~~~~rrm~~~._--_+------

(ON 1/0 CHANNEL)------J1'-----V.!.1A""L"'ID<..!.A""D""D"-'R""ES"'S"-'O""N"--"-'I/O~C""HC!!A""N",-,N""E-'=.L- - - + - - - - - - - DATA--------------------~

(ON 1/0 C H A N N E L ) - - - - - - - - - - - - - - - - - - - - . J

FIGURE 3. WRITE CYCLE TIMING DIAGRAM FOR 110 CHANNEL

lJ ~16~ I

CPUCLK
108--0

PCALE

;:t.~1091
I

-.J

~.
1010 ~.1010~
lt

117

-MWR
-IOWR
(MEMORY OR 1/0 WRITE )

SRDY

ADDRESS
(ON 1/0 CHANNEL)
DATA
(ON 1/0 CHANNEL)

-I

VALID ADDRESS ON 1/0 CHANNEL

~tH32
VALID DATA ON 1/0 CHANNEL

5-24

•

VLSI TECHNOLOGY, INC.
VL82C031

FIGURE 5. READ CYCLE TIMING DIAGRAM FOR ON-BOARD MEMORY (0 WAIT, 150 NS DRAM)

I.-

IC4 11

CPUCLK

rma1..7f-

ALE

~4 IC3~

~->t<

1---1015-- ~ID1~

MAO·MA9
(MEMORY
ADDRESS)

AD~:'SS
~

COLUMN ADDRESS

ID17

-RAS
1018 ---..j

-CAS

1018

1020-

T
I

ISU21

ID19
MDO·MD15
(MEMORY DATA
AND PARITY)

VALID DATA
4 - ID10

SRDY

IH22

~1010
T

7f-

FIGURE 6. WRITE CYCLE TIMING DIAGRAM FOR ON-BOARD MEMORY (0 WAIT, 150 NS DRAM)

12
CPUCLK
tD8
ALE
MAO·MA9
(MEMORY
ADDRESS)
-RAS

--1X

'D98
-'i<
-1015--

~
"OW

ADDRESS

ID17

COLUMN ADDRESS

:=t

tD17

tD18

-GAS
i+--tD23MDO·MD15
(MEMORY
DATA AND
PARITY)
SRDY

_ _ _ _1
i4-tD10

5-25

ID18

---f-

~tD24

VALID DATA

~tD10

i__

•

VLSI TECHNOLOGY, INC.
VL82C031

FIGURE 7. MEMORY REFRESH CYCLE TIMING DIAGRAM

CPUClK

-RQlGT
PCAlE

REFRESH
(110 CHANNEL)
-MRD
(1/0 CHANNEL)
ADDRESS
(1/0 CHANNEL)

FIGURE S. DMA TIMING DIAGRAM

SYSCLK
(1/0 CHANNEL)

DRO

(1/0 CHANNEL)

-ROIGT
PCALE

I-=ID29-;'"

....:f-

1D25t lD25~

lD251-~

...

~ lD43
~

1--1D31
I+-

1+--I1D33

~ID34--

1+--11035
T

AEN
1-1D36+ lH30
-DACK
ADDRESS

HID37

A D

ADATA HAS

lD39

142

-IOWR,-MWD

lD40
-IORD.-MRD

141---<0
1\

5-26

:----

•

VLSI TECHNOLOGY, INC.
VL82C031

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature
Storage Temperature

-1 O·C to +70·C
-65·C to + 150·C

Supply Voltage to
Ground Potential -0.5 V to VCC +0.3 V
Applied Output
Voltage
Applied Input
Voltage

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

-0.5 V to VCC +0.3 V
-0.5 V to +7.0 V

DC CHARACTERISTICS:

= o·e to +7o·e, vee =5 V±5%, GND = 0 v

Symbol

Parameter

Min

VOH

Output High Voltage

2.4

VOL

Output Low Voltage

VOL
VOL

Max

Unit

Condition

IOH =400 J.LA

0.45

IOL = 20 mA, Note 1

Output Low Voltage

0.45

IOL = 12 mA, Note 1

Output Low Voltage

0.45

IOL = 8 mA, Note 1

VOL

Output Low Voltage

0.45

IOL = 4 mA, Note 1

VOL

Output Low Voltage

0.45

IOL = 2 mA, Note 1

VIH

Input High Voltage

2.0

VCC+ 0.5

TIL

-0.5

0.8

TIL

VIL

Input Low Voltage

Output Capacitance

Input Capacitance

CIO

Input/Output Capacitance

III

Input Leakage Current

-10

OLi

Output Leakage Current

-10

ICC

Operating Supply Current

Note 1: Output Current Driving Capabilities.
IOH

IOL

VL82C031 Pins

-3.3 mA

20mA

RESET,-DACK1, --DACK3, AEN, -MREF

-1 mA

SmA

PARO, PARl

-200 J.LA

4mA

CPUCLK, SYSCLK, MDIR, -ERAS3 - -ERASO,
-RAS1, -RASO, -CASH, -CASL, MAl-MAlO,
SADO-SAD19, AO, ALE, -DACKO/-MRAS, -MWR,
-MRD, -IOWR, -lORD, RAM256/1 M, -ROMCS

- 2OO I1A

2mA

-INTA, SELO, SELl, -CMDEN, NMI, SRDY,
-RQ/GTO, -RQ/GT1, -BHE, PCALE,
-PCENH, -PCENL, PCDIR, TC, -DACKE

5-27

J.LA

250

•

VLSI TECHNOLOGY, INC.
VL82C031

NOTES:

5-28

•

VLSI TECHNOLOGY, INC.
VL82C032
SUPER XT-COMPATIBLE 1/0 CONTROLLER

FEATURES

DESCRIPTION

• Controls PS/2~- and PC/AT~
compatible system keyboard and
mouse

The VL82C032 provides the XT-compatible system with control of both the
keyboard and the pointing device
("mouse"), control of two serial communication channels, a real-time clock, as
well as controlling both the disk storage
and display functions. It also provides
the chip select logic for the functions it
controls. The VL82C032 is available
from VLSI Technology, Inc. in an industry-standard plastic 100-pin flat pack.

Further, while offering complete compatibility with the Super XT system, the
VLSI chip set improves system performance by allowin9 10 MHz operation wnh
no "wait states· (using 150 ns DRAMS),
supports an additional 8M bytes of
memory using EMS (Expanded Memory
Specification) 4.0, controls system
speed as necessary for optimum
performance, and supports a 16-bit
memory data bus.

The CMOS VL82C032 is the Input!
Output Controller device in the two-chip
VLSI XT-compatible chip set. The other
device is the VL82C031 System
Controller.

A third device, the VL82C037 VGA,
Video Graphics Controller, is also used
in the XT-compatible system and provides high resolution graphics of up to
800 x 600 elements with 16 colors.
Graphic capabilities of this resolution
are usually found only on more expensive systems.

Integrates the following functions on a
single device:
-8253-compatible timer/counter
-Dual 8250-compatible serial communications controller
-Bidirectional parallel port controller
-8259-compatible interrupt controller
-58167-compatible real-time clock
Decodes subsystems for floppy disk,
hard disk, and video
Provides chip select logic for seriaV
parallel ports, disk controllers, and
real-time clock.

The chip set integrates logic and
functions on XT-compatible systems.

BLOCK DIAGRAM
SAQRe·
SAOR9

ORDER INFORMATION
-XBFRD
-SELHDK

ADSELO, AOSEl1
-Xl0RO
-XIOWR

-FLPCS

-A03FO
-AE3F1
-PRE

-XMEMAD
-REFRESH
-DACK2
-DACK3
-HIGDNTV
PCAEN

Part
Number

Package

VL82C032-FC

Plastic Flatpack

DRVTVPE

DATAO-DATA7

Notes: Operating temperature range is O°C to +70°C.
PS/2 and PC/AT are registered trademarks of
IBM Corp.

INTR

IROO·IA07
-INTA
TIMEROUT2
SPKOUT

esc

eSC2

VOCRTe
RTClKlN

ATCLKOUT

I/'---";r__--'----_

-ATSt
-DTAt

..oCD'

TXDt

-RINt
-DSA1
-CTS1

RXD,

I/'---";r__--'----_

-ATS2
-OTR2
TX02

-DCD2

-RIN2
-DSR2
-CTS2
RXD2

v·~"r__--v·~, PDQ.PD?

PTPEAR
-ACK
-ERROR
-SLCT

-BUSY

r-------r-1/'--"'=
________
'---'=-'-....._

-STROBE
-INIT
-AUTOFD
-SELIN
J1DATA
J1ClOCK
J20ATA
J2ClOCK

SADRO· - - - - - - - " " ' "
SADR9 - - - - - - - , / 1
ADSELO, -XIORD
ADSEL1
-XIOWR
-XMEMRD
-DACK2
-REFRESH
-DACK3
-HIGDNTY
PCAEN

-lEO
KEYLOCK
RESET
PWRGOOD
CHPTEST

5-29

=======3~

ADDRESS
DECODE

~~~~~~~~~
- - - - - - - - L___.J

-XBFRD
-SELHDK
-FlPCS
-RD3FO
-RE3F1
-PRE
DRVTYPE

•

VLSI TECHNOLOGY, INC.
VL82C032

PIN DIAGRAM
VL82C032

~rE
-DACK2
-DACK3
-HIGDNTY
-SELHDK
-LED
DATA7
DATA6
GND
DATA5
DATA4
DATA3
DATA2
DATA1
DATAO
GND
J2DATA
J2CLOCK
J1DATA
J1CLOCK
SADR9
SADR8
SADR7
VCC
SADR6
SADR5
SADR4
SADR3
SADR2
SADR1
SADRO

-PRE

-RD3FO

I-RD

100 99
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

1 I
97

;f~
96

SPK
OUT
I
95

TIMER
OUT2

GND

INTR

0jC IADiEU IADiELO
94

l-r

IRQ7

IRQ5

A IIR 6 I'Ri4

CHP
TEST

IRQ3

I'Ri21

76
75
74
73

72
71
70
69
68

67
66
65
64

TOP VIEW

63
62
61
60
59
58
57
56
55

28
29
30
31

81
80
79
78

53
52
51
~

I-R~S1 I TXb1

KEt
I-DdD1 I-DSIR1
LOCK
RXD1
-RIN1
-CTS1

-DTR1

I Rxb2
VCC

5-30

I-RIN21-C~S21-D~R21 OSb2

-DCD2

-DSR2

-RTS2

TXD2

RESET

-REFRESH
PCAEN
-XBFRD
-BUSY
-SLCT
-ERROR
-SELIN
VCC
-AUTOFD
-ACK
PD7
PD6
PD5
PD4
GND
PD3
PD2
PD1
PDO
-INIT
PTPERR
-STROBE
GND
POWERGD
RTCLKIN
RTCLKOUT
VDDRTC
-XMEMRD
-XIOWR
-XIORD

•

VLSI TECHNOLOGY, INC.
VL82C032

SUPER XT-COMPATIBLE SYSTEM DIAGRAM (WITH VGA)

PC DATA
(8) BUS

VIDEO OUTPUT

SERIAL 110
PARALLEL 1/0
KEYBOARD
MOUSE

DISK DRIVE ~----C:':":":":"::::J

5-31

•

VLSI TECHNOLOGY, INC.
VL82C032

SIGNAL DESCRIPTIONS
Signal

Name

Number

Signal
Type

Signal
Description
DMA Acknowledge 2 - Used to notify the floppy controller that it has been
granted a DMA cycle.

-DACK2
-DACK3

-HIGDNTY

-SELHDK

-LED
DATA7-DATAO

DMA Acknowledge 3 - Used to notify the on-board hard disk controller that
it has been granted a DMA cycle.
High Density - An active low signal that a high density floppy is being used.
Hard Disk Select - Used to select on-board hard disk drive.

o
o

6,7

1/0

Data Bus - Bidirectional data lines tolfrom the CPU or 110 channel.

LED Output - Turns on an LED and is programmable through 1/0 Port D7h
BitO.

9-14
J2DATA

1/0

J2 Connector Data - A bidirectional data line for either a keyboard interface
or pointing device.

J2CLOCK

J2 Connector Clock - A bidirectional clock for either a keyboard interface or
pointing device.

J1DATA

1/0

J1 Connector Data - A bidirectional data line for either a keyboard interface
or pointing device.

J1CLOCK

J1 Connector Clock- A bidirectional clock for either a keyboard interface or
pointing device.

SADR9-SADRO

20-22
24-30

Address Bus - From 1/0 channel. This determines which 110 device the
CPU is accessing.

KEYLOCK

Key Lock - Indicates whether the keyswitch has been locked or not. The
state of this input can be read at Port 66h Bit 3.

RXD1

Receive Data 1 - Input pin for serial data to UART1.

-DCD1, -DCD2

33,42

Carrier Detect - Notifies UART1 or UART2 that a carrier signal has been
detected.

-RIN1, -RIN2

34,43

Ring Indicator - Notifies UART1 or UART2 that a telephone ringing signal
has been detected by a modem or data set.

-DSR1, -DSR2

35,44

Data Set Ready - Handshake signal for UART1 and UART2, that the
modem or data set is ready to transfer data.

-CTS1, -CTS2

36,45

Clear To send - Handshake signal which notifies a modem or data set that
UART1 or UART2 is ready to receive data.

-RTS1, -RTS2

37,46

Request To Send - Handshake signal which notifies a modem or data set
that UART1 or UART2 is ready to transmit data.

-DTR1, -DTR2

38,47

Data Terminal Ready - Notifies a modem or data set that UART1 or UART2
is ready to transfer characters.

TXD1

Transmit Data 1 - Output pin for serial data from UART1.

RXD2

TXD2

Transmit Data 2 - Output pin for serial data from UART2.

OSC2

Oscillator 2 - Is a 14.318 MHz TTL level clock input signal used to generate
the clock for the 8253 internally.

RESET

Reset - An active high signal which is used to reset the internal logic of the
VL82C032.

Receive Data 2 - Input pin for serial data to UART2.

5-32

•

VLSI TECHNOLOGY, INC.
VL82C032

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

-XIORD

VO Read Command - Instructs the internal 110 device to drive its data on to
the data bus.

-XIOWR

110 Write Command - Instructs the internal 110 device to read the data
present on the data bus.

-XMEMRD

Memory Read Command - Instructs the external memory to drive its data
on to the data bus.

VDDRTC

Real Time Clock Supply - Isolated power supply input for real-time clock.

RTCLKOUT

Oscillator Output - 32.768 KHz real-time clock output to crystal.

RTCLKIN

PWRGOOD

Power Good - Indicates that power to the board is stable.

-STROBE

Printer Strobe - This pin is the "strobe" signal to a printer. Programmable
through 110 Port 37Ah Bit O.

PTPERR

-INIT

Printer Initialize - Initializes the printer. Programmable through 110 Port
37Ah Bit 2.

PDO-PD7

62-65
67-70

Parallel Port Data Bus - Bidirectional data lines to the parallel port device.
When printer mode is selected, these lines are used as output lines.
When input mode is selected, these lines are used as input lines.

-ACK

-AUTOFD

Printer Auto Feed - Causes a printer to generate a line feed automatically
after each line is printed. Programmable through I/O Port 37Ah Bit 1.

-SELIN

Printer Select In - Used to select the printer. Programmable through 110
Port 37Ah Bit 3.

-ERROR

-8LCT

Oscillator Input - 32.768 KHz real-time clock crystal or oscillator input.

Printer Paper End - Indicates that an end of paper has been detected.
Readable at 110 Port 379h Bit 5.

Printer Acknowledge - Indicates that data has been received by a printer.
Readable at I/O Port 379h Bit 6.

Printer Error - Indicates that a printer error has occurred. Readable at 110
Port 379h Bit 3.
Printer Select - Indicates that the printer has been selected. Readable at

VO Port 379h Bit 4.
-BUSY

-XBFRD

PCAEN

Address Enable - Disables I/O devices from the I/O channel to allow DMA
transfers to take place. .

-REFRESH

Memory Refresh Request - Indicates that the system is in a memory
refresh cycle.

CHPTEST

Chip Test Mode - When this signal is high, the VL82C032 is in a test
mode. During normal operation, this pin should be tied to ground.

IR02-IR07

82-87

Interrupt Request Inputs - Asynchronous inputs which are the interrupt
request signals to the internal 8259 interrupt controller.

-INTA

Interrupt Acknowledge - Enables the internal 8259 controller to vector data
onto the data bus by a sequence of interrupt acknowledge pulses issued
by the CPU.

Printer Busy - This pin indicates whether the printer is able to receive data.
Readable at 110 Port 379h Bit 7.

Buffer Read - Controls the direction of an external data buffer. When this
signal is low: data is read from the internal bus to the 110 channel. When
this signal is high, data is written from the 1/0 channel to the internal bus.

5-33

•

VLSI TECHNOLOGY, INC.
VL82C032

SIGNAL DESCRIPTIONS

(Cont.)

Signal
Name

Signal
Type

Signal
Description

Interrupt Request - Interrupts the CPU. Generated whenever a valid IRQ is
received.

Pin
Number

INTR

ADSELO, ADSEL 1

90,92

Address Select - Address range signals from the VL82C031, according to
the following table:
ADSEL1

ADSELO
0
1
0
1

0
0
1
1

TIMEROUT2

OSC

Range
Don't Care
A15-Al0 = 0 (110)
ROM
Video RAM

Timer Channel 2 Output - Provides a precision timer clock to the
VL82C031.
OSC Input - A 24 MHz clock input.

SPKOUT

-FLPCS

96
97

-RD3F1

-PRE

a
a
a
a

Floppy Select - Chip select for a 765A floppy controller.

-RD3FO

Drive Type - Used to control the data rate for the floppy controller (765A).

Speaker Data Output - Should be connected to a speaker driver to drive
the speaker or beeper.

Read Port A - A gate signal activated by a read from 1/0 Port 3FOh.
Read Port B - A gate signal activated by a read from 1/0 Port 3Fl h.
Precomp - Used to select whether write precompensation is enabled in the
765A floppy controller. Programmable through 1/0 Port 3F7h Bit 2.

DRVTYPE

100

GND

8,15,58,
66,91

System Ground

VCC

23,40,73

System Power: +5 V

FUNCTIONAL DESCRIPTION
SYSTEM MEMORY AND 1/0 MAP
The 8086N30 supports 16-bit operations with 20-bit addressing to directly
access up to 1M byte of memory space.
The system memory and an on-board
Hex Address

Description

00000 - 1FFFF
20000 - 2FFFF
30000 - 3FFFF
40000 - 4FFFF
50000 - 5FFFF
60000 - 6FFFF
70000 - 7FFFF
80000 - 8FFFF
90000 - 9FFFF
AOOOO - BFFFF
COOOO - EFFFF
FOOOO - FFFFF

128K
64K
64K
64K
64K
64K
64K
64K
64K
128K
192K
64K

expanded memory (if it's enabled) are
byte andlor word accessible. Memory
is mapped as follows:

byte: 1st bank #1
byte: 2nd bank #2
byte: 2nd bank #3
byte: 2nd bank #4
640K
byte: 2nd bank #5
System
Memory
byte: 2nd bank #6
byte: 2nd bank #7
byte: 2nd bank #8
byte: 2nd bank #9
byte: Video Buffer
byte: Reserved for BIOS on 1/0 Channel.
byte: System ROM

5-34

•

VLSI TECHNOLOGY, INC.
VL82C032

VL82C032 110 MAP
I/O Address

Function

Response

PC Bus
Response

0020 - 0021

Interrupt Control

RIW

None

0040-0043

System Timer

RIW

None

0060

System Data Port

RIW

None

0061

System Control

RIW

None

0062

System Status Register

RIW

None

0063

Interrupt Control

RIW

None

0065

Chip Select Control

RIW

None

0066 - 006A

Interrupt Diagnostic /Keyboard/Mouse

RIW

None

OOAO - OOAF

Interrupt Extended Status

RIW

None

OOBO - OOBF

Rea~ Time

RIW

None

0000 - OODF

System Control and Status Group 2

RIW

None

OOEO - OOEF

Real-Time Clock

RIW

None

02FS-02FF

Serial Comm. Control 2

RIW

None

0320 - 032F

Fixed Disk Control

RIW*

RIW

037S - 037A

Parallel Port

RIW

None

03FO - 03F7

Floppy Disk Control

RIW*

RIW

03FS - 03FF

Serial Comm. Cantrall

RIW

None

Clock

"Note: The peripheral is external to the VLS2C032. It can be enabled or disabled through the Chip Select Control Register Port.

TABLE 1. INTERRUPT REQUEST LEVEL REGISTER
Level

VL82C032 Chip

System Board

I/O Channel

IROO
IROl

Timer Channel 0
Keyboard Interface Pointing
Device and Real-Time Clock
Not Used
Serial Port 2
Serial Port 1
Not Used
Not Used
Parallel Port

Not Available
Not Available

Video (VL82C037)
Not Used
Not Used
Fixed Disk
765A Floppy Controller
Not Used

Available
Available
Available
Available
Available
Available

IR02
IR03
IR04
IR05
IR06
IR07

5-35

•

VLSI TECHNOLOGY, INC.
VL82C032

TABLE 2. MODE FUNCTIONS
Address

W/R

Functions

0020
0021

W
W

••• Initialization Mode···
Initialization Command Word ICW1
Initialization Command Word ICW2, ICW2, ICW3, ICW4

0021
0020

W
W

••• Operation Mode •••
Operation Control Word OCW1
Operation Control Word OCW2, OCW3

0021
0020

R
R

••• Read Status Register (Operation Mode) •••
Interrupt Mask Register (IMR)
Interrupt Request Register (IRR) and
Interrupt Service Register (ISR), IRR and ISR is selected through bO and b1 in OCW3

INTERRUPT CONTROL LOGIC
The interrupt control logic includes one
Intel 8259A-compatible interrupt
controller, one interrupt vector register
and two interrupt extension registers.
The interrupt controller has eight levels
of interrupt that are handled according
to priority in the VL82C032 chip. Table
1 shows the hardware interrupts and
their availability to the 110 channel (PC
bus).
The 110 address for each register in the
interrupt controller is defined in Table 2.
During initialization mode, when the
vector address is written into ICW2
register, the same vector address will
be written into the interrupt vector
register. The content of interrupt vector
register can be read through an 110
read from address 063h. In order to
read this register, 110 Port 69h Bit 6
must be set to 1. By writing to 110 Port
63h any of the IRO lines can be
activated or the NMIline as shown in
the following table:
I/O Port 63h (Write)
Bit
7
6
5
4
3
2
1
0

Function
IR07
IR06
IR05
IR04
IR03
IR02
Not Used
NMI

To write this port 110 Port 69h Bit 7 must
first be set to 1. You must set Port 69h
Bit 2 to 1 to allow NMI activation. To

start the initialization mode of the
interrupt controller, a command is
issued with Bit 4 =1 to 110 address 020h
which it is interpreted as ICW1. The
content of the interrupt vector register is
reset to 0 after power-up reset.
Regardless of the vector address initialized in ICW2, the vector address
generated by interrupt IR01 is always
hex 71. The interrupt acknowledge
cycle only requires one wait state for
8 MHz or 10 MHz CPU 8086.
For detailed instructions on how to
program the 8259A-compatible interrupt
controller, see the VL82C59A data
sheet.
TIMER CONTROLLER
This timer controller is compatible with
the Intel 8253. It is a programmable
interval timer/counter. The functions of
the timer controller are to generate a
constant system time and control the
tone of the speaker. This controller
contains three timer channels. Each
channel is described as follows:
Channel 0:
This channel is a general purpose timer
providing a constant time base for the
operating system. The input clock runs
a~ 1.19 MHz. The enable clock input is
always enabled after power-up. The
output of this channel is connected to
interrupt channel 0 (IROO)of the
interrupt controller (8259A).
Channel 1:
This channel is for diagnostic purposes.
During power-up test, the system BIOS
will use this channel to check the
5-36

functions of the timer controller. The
system BIOS also uses this channel to
check the frequency of memory refresh.
The input clock runs at 15.61J.s per
cycle. The enable clock input is always
enabled after power-up. The output of
this channel is not connected anywhere,
so CLKOUT1 is not an available pin on
the VL82C032.
Channel 2:
This channel is used to control the tone
of the speaker. The input clock runs at
1.19 MHz frequency. The enable clock
input is turned on or off by bit 0 of
system control register 061 h. When
bit 0 of 110 PORT 061 h is set to 1, the
frequency of the tone is controlled by
the number in counter register 2. The
output of this channel is connected to
the speaker driver. After power-up
reset, bit 0 of 110 port 061 h is reset to O.
More detailed information is available in
the system control register section
(061h).
The 110 address for each register in the
timer controller is defined in Table 3.
The control mode register is to select
the operation mode for each channel in
the timer controller. There are six

TABLE 3. REGISTERS
Address W/R
0040
0041
0042
0043

W/R
W/R
W/R
W

Functions
Counter Register 0
Counter Register 1
Counter Register 2
Control Mode Register

•

VLSI TECHNOLOGY, INC.
VL82C032

different modes that can be selected.
They are listed as follows:
- mode 0: interrupt on terminal count
- mode 1: programmable one-shot
- mode 2: rate generator
- mode 3: square wave rate generator
- mode 4: software triggered strobe
- mode 5: hardware triggered strobe
REAL TIME CLOCK
A real-time clock is integrated in the
VL82C032 chip. Its functions are fully
compatible with the National 58167A
real-time clock. However, the
VL82C032 is much faster than the
58167A. It can complete a read or write
cycle at normal 110 speed (four wait
states) in a System 30, so it is not
necessary to generate the
10CHRDY to the 110 Channel. The
functional block has an independent
power (VDDRTC) pin which is isolated
from the normal power (VCC) pin of the
VL82C032 chip.
This real-time clock includes an addressable counter, eight bytes of RAM,
and two interrupt outputs. A powerdown input allows the real-time clock to
be powered from battery power and
continue its operation independently
during power-down mode. The time
base is derived from a 32,768 Hz
crystal oscillator.

CMOSSRAM
There are 16 bytes of CMOS static
RAM in the VL82C032, powered by the
standby battery. This can be used for
storing system configuration information.

stop bits. A prioritized interrupt system
controls transmit, receive, error, and
line status as well as data-set interrupt.
The clock applied to the serial controller
is 1.84 MHz which is derived from the
system clock.

The RAM can be accessed by writing
an index value (O-F) to 1/0 Port D4h and
then writing or reading 1/0 Port D5h.

Each serial port will provide the
following RS232 signals:

The PWRGOOD input will block the
chip select signal and 110 read or write
signals during power-up or hardware
reset. It prevents any non valid 1/0
access to the RAM.
An auto reset will be generated when
VCC switches from 0.0 V to 2.0 V,
which will reset the content of the
SRAMto o.
SERIAL CONTROLLER
The VL82C032 chip incorporates two
serial communication controllers which
are fully compatible with the NS8250A.
A programmable baud-rate generator
allows operation from 50 baud to 9600
baud. These controllers support 5-, 6-,
7- and 8-bit characters with 1, 1.5 or 2

Address

The PWRGOOD input will block the
chip select signal and 110 read or write
signals during power-up or hardware
reset. It prevents any non-valid 1/0
access to the real-time clock.
The 110 address for each register and
RAM in the real-time clock is defined in
Table 4.

00B5
00B6
OOBF
OOEO
OOEI
00E2
00E3
00E4
00E5
00E6
00E7
00E8
00E9
OOEA
OOEB
OOEC
OOED
OOEE
OOEF

An auto reset will be generated in the
internal logic of the real-time clock when
VCC switches from 0.0 V to operating
Voltage. This reset signal will reset the
content of RAM and the content of the
interrupt registers to o.

The interrupt from serial controller 1 is
connected to IRQ4 of the interrupt
controller in the VL82C032. The 110 .'
address for each register in serial··
controller 1 is defined in Table 5.
The interrupt from serial controller 2 is
connected to IRQ3 of the interrupt
controller in the VL82C032. The 1/0
address for each register in serial
controller 2 is defined in Table 6.

TABLE 4. W/R FUNCTIONS
OOBO
OOBI
00B2
00B3
00B4

The interrupt from the real-time clock is
connected to IRQl of the interrupt
controller. IRQl is also shared with the
keyboard and pointing device interlace.
The interrupt from the real-time clock
can be reset by reading the interrupt
status register (110 Port BO hex).

- RXD: Receive Data
- CTS: Clear To Send
- DSR: Data Set Ready
- DCD: Data Carry Detect
- RI: Ring Indicator
- TXD: Transmit Data
- DTR: Data Terminal Ready
- RTS: Request To Send

WtR

R
W

W
W
R
W
W
W
W/R
W/R
W/R
WtR
WtR
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R

5-37

Functions
Interrupt Status Register
Interrupt Control Register
Counters Reset (Data = FFH)
RAM Reset (Data = FFH)
Status Bit, dO = 1, Counter Is Rippling
The content of counters are invalid; reread.
Go Command (Data = XXH)
Standby Interrupt (1 = Enable, 0 = Disable)
Enable Test Mode
Counter - Ten Thousandths of Seconds
Counter - Hundredths and Tenths of Seconds
Counter - Seconds
Counter - Minutes
Counter - Hours
Counter - Day of Week
Counter - Day of Month
Counter - Month
RAM - Ten Thousandths of Seconds
RAM - Hundredths and Tenths of Seconds
RAM - Seconds
RAM - Minutes
RAM- Hours
RAM - Day of Week
RAM - Day of Month
RAM - Month

VLSI TECHNOLOGY, INC.
VL82C032
PARALLEL PORT CONTROLLER
The parallel port controller can be
configured to be one of two modes.
The first is "printer mode". The second
is "input mode," which allows the
parallel port to receive data from
external devices. The input mode of the
parallel port controller is selected by
writing a 0 to bit 7 of the peripheral
select control register 065h.
There are two output ports and three
input ports in the parallel port controller.
The following is a detailed description of
each port.
Data Port:
378h
The data port is an 8-bit port for both
the printer mode and input mode. For
the printer mode, a write operation to
this port immediately presents data to
the connector pins. A read operation
from this port in the printer port produces the data that was last written to
it.
In the input mode, a write operation to
this port will not affect the output of the
data port. A read operation in the input
mode produces the current data on the
connector pins from external devices.
Status Port:
379h
The status port is a read-only port for
either mode. When an interrupt is
pending the interrupt status bit is set to
o. The following is the bit definition of
the status port:
Bit Function
7 -BUSY: When this bit is 0, the
printer is busy and cannot accept
data.
6 -ACK: When this bit is 0, the
printer is ready to accept data.
5 PE: When this bit is 1, the printer
has detected the end of the paper.

4
3

SLCT: When this bit is 1, the
printer has been selected.
-ERROR: When this bit is 0, the
printer has detected an error
condition.
-IRQ: When this bit is 0, the
printer has acknowledged the
previous transfer using the "-ACK"
signal.

37Ah
Output Control Port:
The Output Control Port is a read or
write port. The following shows the bit
definition of the Output Control Port:
Bit Function
IRQEN: When this bit is set to 1,
4
the interrupt logic is enabled.
3
SlCTIN: This bit controls the
-SELIN signal on the Vl82C032
pin 74. When this bit is set to 1,
the printer is selected.
2 -IN IT: This bit controls the "-IN IT"
signal on the VL82C032 pin 61.
When this bit is set to 1, the printer
starts.
AUTOFO: This bit controls the
"-AUTOFO" signal on the
Vl82C032 pin 72. When this bit is
set to 1, the printer will automatically line feed after each line is
printed.
o STROBE: This bit controls the
"-STROBE" signal on the
Vl82C032 pin 59. When this bit is
set to 1, data is pulse-clocked into
the printer.
The interrupt from the parallel port
controller is connected to IRQ7 of the
interrupt controller in the Vl82C032.
The VO address for each register in the
parallel port controller is defined in
Table 7.

KEYBOARD INTERFACE AND

POINTING DEVICE INTERFACE
There are two interfaces (J1 and J2)
which can be used for either keyboard
or pointing device. The keyboard
interface is fully compatible with the
enhanced AT keyboard, and is implemented as hardware logic instead of the
8042 microcontroller. The pointing
device interface is also fully compatible
with IBM PS/2 mouse devices. The
system BIOS will handle the following
tasks:
- initialization of the interface after
power-up
- define which device (keyboard or
pointing device) has been connected
to each interface (J1 andJ2)
- receive interrupt and parity errors
- translation between keyboard scan
code and ASCII code
- transmission sequences
The hardware will handle the following
tasks:
- initialize both interface registers to
default value after power-up reset
- generate protocol sequences (data
line and clock line) between system
and keyboard or mouse
- detect incoming data (start bit) from
keyboard or mouse
- generate the receive interrupt and
check parity error
- generate the parity bit during
transmission
- handle asynchronous conditions
between transmit and receive
There are two signal lines used for each
interface. They are the data line and
the clock line. During a receive or
transmit cycle, the clock will be generated by the keyboard or pointing device.

TABLE 5. SERIAL CONTROLLER. 1
1/0 ADDRESSES

TABLE 6. SERIAL CONTROLLER 2
1/0 ADDRESSES

Address

W/R

Functions

Address

W/R

Functions

03F8
03F8
03F9
03FA
03FB
03FC
03FD
03FE
03FF

W
R
W/R
R
W/R
W/R
R
R
W/R

Transmitter Holding Register
Receive Buffer Register
Interrupt Enable Register
Interrupt Identification Register
line Control Register '
Modem Control Register
line Status Register
Modem Status Register
Scratch Register

02F8
02F8
02F9
02FA
02FB
02FC
02FD
02FE
02FF

W
R
W/R
R
W/R
W/R
R
R
W/R

Transmitter Holding Register
Receive Buffer Register
Interrupt Enable Register
Interrupt Identification Register
line Control Register
Modem Control Register
line Status Register
Modem Status Register
Scratch Register

5-38

•

VLSI TECHNOLOGY, INC.
VL82C032

The system only drives the clock line for
handshake purposes.
The communication protocol used by
the keyboard and mouse ports is
compatible with the Intel 8042 chip,
although the programming interface is
different. Data transmission to and from
the external device consist of an 11-bit
data stream transferred over the data
line. The clock is generated by the
external device to synchronize the
transmission, and is implemented as a
"wire OR" signal so either the external
device or the system may pull it low.
The format of each data element is as
follows:
1 Start Bit (Always 0)
8 Data Bits, LSB First
1 Parity Bit (Odd Parity)
1 Stop Bit (Always 1)
The eight data bits plus the parity bit
always have an odd number of 1's. The
external device begins transmitting
information by pulling the data line low
for one clock cycle, which indicates the
start bit. The system can terminate the
transmission at any time during the first
10 clock cycles by pulling the clock low.
I! the transmission has progressed
beyond the tenth clock, the system
must receive the data to prevent data
loss. The system may transmit data to
the external device by first pulling the
clock low to inhibit the external device,
then pulling the data line low and
releasing the clock line. The external
device then reoognizes the first clock
pulse as a start bit transmitted from the
system and receives the rest of the
data. Table 8 summarizes the functions
of the clock and data signals for the two
interfaces.
The definitions of each register for
interface are described as follows.
KEYBOARD/POINTING DEVICE
DATA REGISTER (060h)
RIW
This register is for user interface
(application) at the system BIOS level.
I! is a dummy register, and does not
relate to the hardware logic on any
particular interface. When information
is to be transmited to the keyboard or
pointing device, writing the data to this
register and the system BIOS will take
the content of this register and transmit
it to the keyboard or pointing device.
When either interface receives data
from an external device (keyboard or

pointing device), the system BIOS will
check any parity error and copy the
data from the receive register to this
data register.
This register will be reset to 0 at powerup reset.
KEYBOARD/POINTING DEVICE
TRANSMIT/RECEIVE REGISTERS
(067h AND 068h)
Register OS7h is the transm it/receive
register for interface J1. Register OS8h
is the transmit/receive register for
interface J2. These are eight-bit
registers. Reading these registers will
not affect any logic state on the
interfaces. These registers can be read
at any time, and will return the data
from the receive buffers for their
respective interfaces.
When writing to these registers, the
data will be stored in the transmit
buffers and generate a parity bit.
Writing the data to these registers will
not start the transmit sequence. To
start the transmit sequence on interface
J1, bit 3 of the transmit control register
(OS9h) must be toggled (0-> 1->0)
before writing the data to the transmit
register (OS7h). To start the transmit

sequence on interface J2, bit 4 of the
transmit control register (OS9h) must be
toggled (0-> 1->0) before writing the
data to the transmit register (OS8h).
The purpose of toggling bit 3 or bit 4 of
the transmit control register is to ensure
the clock line on the interface (J 1 or J2)
is in a quiescent state.
The receive buffers and transmit
buffers will be reset to 0 after power-up
reset.
Bit 3 of this register is for initializing the
transmission logic for interface J1. Bit
4 of this register is for initializing the
transm ission log ic for interface J2.
These two bits ensure the clock lines
are in the quiescent state. If the
external device (keyboard or pointing
device) is sending data to the system
before transmission starts, the transmit
sequence will not be started until bit 4
or bit S of the receive control register
(OSSh) is toggled (0->1->0). When
either interface receives data from an
external device the hardware logic will
pull the clock line low to prevent
contiguous data transmission by the
external device. Toggling bit 4 of the
receive control register (OSSh) will

TABLE 7. OUTPUT AND PRINTER REGISTER
Address

W/R

Functions

0378
0379

W/R
R

Data Output Register
Printer Status Register
b7 ~ Printer Busy (1 = Not Busy, 0 = Busy)
bS = Printer Acknowledge (1 = No -ACK, 0 -ACK)
b5 = End of Paper (1 = No Paper, 0 = Paper ok)
b4 c Printer Selected (1 = Selected, 0 c Not Selected)
b3 = Printer Error (1 = No -ERROR, 0 -ERROR)
b2 - bO = Not Used
Printer Control Register
b7 - b5 = Not Used
b4 = EnablelDisable Interrupt (1 = Enable, 0 = Disable)
b3 = Select Printer Device (1 = Select, 0 Not Select)
b2 Start Printer Device (1 = Stop, 0 = Start)
b1 = Enable Line Feed (1 = Enable, 0 ~ Disable)
bO = Data Strobe (1 = Data Valid, 0 c Data Invalid)
g

037A

W/R

TABLE 8. TRANSMIT DECODE
Clock
Line

Data
Line

1
1

o
1

Functions
No Transmit or Receive
System Transmit Data to Keyboard or Mouse
Keyboard or Mouse Transmit Data to System

5-39

•

VLSI TECHNOLOGY, INC.
VL82C032

cause the clock line on interface Jl to
become quiescent. Toggling bit 6 of the
receive control register (066h) will
cause the clock line on interface J2 to
become quiescent. If the clock line is
kept low for any reason, the transmit
cycle should not be started until the
clock line becomes quiescent.

When bit 5 is set to 0, the clock line on
interface Jl will be forced to o. When
bit 7 is set to 0, the clock line on
interface J2 will be forced to o. At
power-up reset, these two bits are reset
to
External devices cannot send any
data to the system until these two bits'
are setto 1.

The bit definitions of the transmit control
register are shown in Table 9.

When bit 4 is set to 1, it clears the
indication of parity errors and interrupts
on interface J 1. When bit 6 is set to 1, it
clears the indication of parity errors and
interrupts on interface J2. When these
two bits are 1, the clock line will not be
forced low after receiving data from an
external device. Normally, these two
After receiving
bits should be set to
data from an external device, bit 4 or bit
6 should be toggled to clear any parity
error or interrupt. These bits will be
reset to 0 on power-up reset.

Toggling bit 3 or bit 4 of the transmit
control register will reset any parity error
indication (bit 0 or bit 1 of the receive
control register - 066h).
Bit 7, bit 6 and bit 2 of the transmit
control register are for interruptlNMI diagnostics. These bits are described in
the section covering the interrupt
controller.
Reading this register will not affect the
hardware logic. These bits will be reset
to 0 after power-up reset.
KEYBOARD/POINTING DEVICE
RECEIVE CONTROL REGISTER
(066h)
This register controls the receive logic
for both interfaces. This register also
indicates which interface (J2 or J2) has
been connected to the keyboard, and if
any parity error has occurred during a
receive cycle. The bits are defined in
Table 10.

Bit 3 indicates whether the keyboard
has been connected to interface Jl.
The keyboard connection is not
detected by the hardware logic on the
the interface J 1. It is done by the
system BIOS, so the system BIOS
should set or reset this bit. When this
bit is set to 1, the keyboard is connected to interface Jl. When this bit is
0, the keyboard is connected to
interface J2. This bit will be reset to 0
at power-up reset.

TABLE 9. TRANSMIT CONTROL REGISTER

Bit 0 and bit 1 indicate parity errors.
When bit 0 is set to 1, it indicates a
parity error occurred on interface Jl
during a receive cycle. Bit 0 can be
cleared by writing one to bit 4 of this
register or bit 3 of the transmit control
register (069h). Bit 1 can be cleared by
writing 1 to bit 6 of this register or bit 4
of the transmit control register (069h).
These two bits are reset to 0 at powerup reset.
Bit 2 indicates whether the system
keyswitch has been locked or not.
When this bit is 0, the system keyswitch
is locked.
KEYBOARD/POINTING DEVICE
RECEIVE STATUS REGISTER (06Ah)
Bit 5 and bit 2 of this register indicate
whether data has been received from
an external device or not for interface
Jl and J2, respectively. When bit 5 is
1, data has been received from
interface J 1. Bit 5 can be cleared by
setting bit 4 of the receive control
register (066h) or bit 3 of the transmit
control register (069h). When bit 2 is 1,
data has been received from interface
J2. Bit 2 can be cleared by setting bit 6
of the receive control register (066h) or
bit 4 of the transmit control register
(069h). After power-up reset, these bits
are reset to o.
The bits in this register are defined in
Table 11.

Bit 0 indicates what type of floppy disk
drive has been connected to the
system. When this bit is set to 0, a high
density drive (1.44M bytes) has been
selected. When this bit is set to 1, a low
density drive (720K bytes) has been
selected. This bit reflects the state of
the -HIGDNTY input (pin 3) of the
VL82C032.

TABLE 10. RECEIVE CONTROL REGISTER

INTERRUPT EXTENDED CONTROL
REGISTER (OA1h)
The purposes of this register is to mask
out incoming interrupts from the
keyboard, pointing device or real-time
clock. The bit definitions for this
register are described in Table 12.

Address

W/R

Functions

0069

W/R

b7 = Enable Diagnostic Through Reg. 63h
b6 Blocks Reg. 63h Read
b5 - Disable Jl and J2 Clock (1 _ Disable)
b4 = Toggle for System to Transmit Data Through J2
b3 - Toggle for System to Transmit Data Through Jl
b2 = Enable NMI Diagnostic Through Reg. 63h
bl = Not Used
bO = Not Used

Address

W/R

Functions

0066

W/R
W/R
W/R
W/R
W/R

b7 = System Drives the Clock on J2
b6 _ Toggle for System to Receive Data Through J2
b5 = System Drives the Clock on Jl
b4 = Toggle for System to Receive Data Through Jl
b3 Jl Has Keyboard Connection
b2 = Key lock (0 - Key Is Locked)
bl = J2 Parity Error Indication
bO. Jl Parity Error Indication

R
R

5-40

When bit 3 is set to 1, interrupts from
interface J2 will be masked out. When
bit 2 is set to 1, interrupts from interface
Jl will be masked out. When bit 0 is set
to 1, interrupts from the real-time clock
wil be masked out.

•

VLSI TECHNOLOGY, INC.
VL82C032

Setting the bits in register OAl will not
affect the indications on bit 2 and bit 3
of the interrupt extended status register
(OAOh) and bit 2 and bit 5 of the
keyboard/pointing device receive status
register (06Ah). These bits are reset to
o at power-up reset.
INTERRUPT EXTENDED STATUS
REGISTER (OAOh)
IRQl (hardware interrupt) of the
interrupt controller is shared by three
devices; real-time clock, Jl interface
and J2 interface. This register determines which device generated the
IRQ1.

The bit functions of this register are
described in Table 13.
When bit 3 is 1, it indicates a pending
interrupt from interface J2 (keyboard or
pointing device). Bit 3 can be reset by

toggling bit 6 of register 066h or bit 4 of
register 069h. When bit 2 is I, it
indicates a pending interrupt from
interface Jl (keyboard or pointing
device). Bit 2 can be reset by toggling
bit 4 of register 066h or bit 3 of register
069h. When bit 0 is I, it indicates a
pending interrupt from the real time
clock. Bit 0 can be reset by reading the
interrupt status register (OBOh) on the
real time clock. These bits are reset to
o at power-up reset.
SYSTEM CONTROL REGISTER
The system control register (061 h) is
used as speaker control, enables the
parity check on the I/O Channel and
memory parity check on the system
board. This register is read/write. The
bits in this register are defined in Table
14.

006A

W/R

Functions
b7
b6
b5
b4
b3
b2
bl
bO

s Not Used
= J2 Status (0 = Receive in Progress)
= Jl Receive Buffer Full (Interrupt Status)
= Not Used
= Jl Status (0 = Receive in Progress)
= J2 Receive Buffer Full (Interrupt Status)
= Not Used
= High Density Floppy Media (0 _ High Density)

TABLE 12. INTERRUPT EXTENDED CONTROL REGISTER
Address

W/R

Functions

OOAI

W/R

b7
b6
b5
b4
b3
b2
bl
bO

= Not Used
Not Used
= Not Used
= Not Used
= Mask Out Interrupt from J2
Mask Out Interrupt from Jl
= Not Used
= Mask Out Interrupt from Real Time Clock

=
=

TABLE 13. INTERRUPT EXTENDED STATUS REGISTER
Address
OOAO

W/R

Functions
b7
b6
b5
b4
b3
b2
bl
bO

When bit 4 is set to I, it stops a
memory parity from generating an NMI.
When cleared, an NMI is generated
whenever a memory parity error is
sensed.
Bit 1 is used as speaker data. This bit
gates the output of timer 2. It is used to
disable the timer's sound source or
modify its output. When set to I, it
enables the output. When cleared, it
forces the output to o.
Bit 0 is routed to the timer input at
GATE 2. When this bit is cleared, the
timer operation is halted. This bit and
bit 1 (speaker data) control the operation of the sound source.
At power-up reset, the contents of this
register are reset to o.

TABLE 11. RECEIVE STATUS REGISTER
Address

When bit 5 is set to I, it stops 10CHCK
from generating an NMI. When
cleared, an NMI is generated when
10CHCK goes active.

= Not Used
= Not Used
= Not Used
= Not Used
= IRQl from J2
= IRQl from Jl
= Not Used
= IRQl from Real Time Clock

SYSTEM STATUS REGISTER (062h)
This port returns status and configuration information about the planar card.
The bits are defined in Table 15.

Bit 7 - Parity Error status bit, is used to
indicate that a memory error has
been detected. This bit is read
only and is cleared by a reset.
Bit 6 - I/O Channel Error status bit, is
used to indicate the state of the
10CHCK pin. This bit is read
only and is cleared by a reset.
Bit 5 - Timer 2 Output status bit, is
used to reflect the current state
of the output of timer channel 2.
This bit is read only.
Bit 4 - Reserved, read as 0, and should
be written as o.
Bit 3 - Reserved, read as 0, and should
be written as o.
Bit 2 - Hard Disk Installed status bit,
when set (1) indicates the hard
disk drive is missing, and when
reset (0) the hard disk is
installed. This bit is set by the
BIOS and defaults to 1 on reset.
Bit 1 - Coprocessor Installed status bit,
when set (1) indicates that the
coprocessor is installed, and
when reset (0) indicates the

5-41

•

VLSI TECHNOLOGY, INC.
VL82C032
coprocessor is missing. This bit
is set by the BIOS. This bit
defaults to 0 on reset.

Bit 0 - Reserved, read as 0, and should
be written as O.
PERIPHERAL SELECT CONTROL
REGISTER (06Sh)
This register controls the following
peripherals on the system board:
- Serial Controllers
- Floppy Controller
- Video Controller
- Parallel Controller
- Fixed Disk Controller
The bits in this register are defined in
Table Hi.
When a bit is set to 1, that peripheral is
enabled. When the peripheral is
enabled, the chip select signal is
generated to start a read or write
operation, and the read or write signal
to the I/O channel is blocked. When the
peripheral is disabled, the chip select
signal is not generated and all read and
write operations are directed to the va
channel. See Table 16.
After power-up reset, all the bits of this
register are reset to O.
ADDRESS DECODE FOR FLOPPY
CONTROLLER
VL82C032 has the capability to decode
the 110 address for an on-board floppy
controller and generates the select
signal for the floppy controller. From
the system point of view, the floppy
controller. and its associated registers
inside the VL82C032 are on the same
bus (110 extended bus). The VL82C032
can control the data buffers between
the I/O extended bus and the 110
channel during 110 cycles or DMA
cycles for the floppy controller.
Two buffer enable signals (-RD3FO and
-RD3F1) are decoded for this purpose.
The bits in these buffers should be connected as shown in Table 17.

ADDRESS DECODE FOR HARD DISK
CONTROLLER
VL82C032 has the capability to decode
the 110 address for the on-board hard
disk controller and generates the select
signal for the controller. From the
system point of view, the hard disk
controller and its associated registers
reside on the same bus (Va extended
bus) as the VL82C032. VL82C032 can
control the data buffers between the va
extended bus and the I/O channel
during I/O cycles or DMA cycles for the
hard disk controller. The 1/0 address
range for the hard disk controller is
between 320h and 327Fh. Accessing
these addresses will activate the
-5ELHDK output (pin 4). It uses DMA
channel 3 for DMA access.
EXTENDED CONTROL AND
DIAGNOSTICS
There are several extended control and
diagnostic features incorporated into
the VL82C032. These include a power
management function for reduced
power consumption in standby mode,
DMA diagnostics for hard disk controllers, and control of an extemal LED
driver signal.
POWER MANAGEMENT REGISTERS
(01 E AND 01 C)
The VL82C032 contains circuitry which
allows it to be placed in a "standby"
mode where any internal circuits which
operate in a dynamic manner are
placed into a static state, thereby
reducing power consumption. This
feature is intended primarily for use the
VL82C032 system controller, but can
be implemented in a stand-alone 110
controller under the right circumstances. To place the chip in standby
mode, first write a 1 to register 1Eh,
then perform a read from register 1Ch.
As long as the 1/0 read line and chip
select remain active, and the address
remains valid, the chip will be in
standby mode. When the read cycle is
terminated, the chip resumes normal
operation.

5-42

MISCELLANEOUS CONTROU
STATUS REGISTER (000)
This register is related to the operation
of the built in floppy decode logic, the
real-time clock, and serial port 2. The
bit assignments in this register are as
follows:
Bit 7 - DRVTYPE control bit. This bit
controls the state of the
DRVTYPE output signal of the
VL82C032 (Pin 100).
Bit 6 - RTC Clock Status. This bit
indicates the current state of the
internal 58167 compatible RTC
input clock, and is read only.
Bit 5 - Enable Serial Port 2. When set
to 1, this bit enables the
operation of the second 8250
serial va controller.
Bit 4 - This bit, when set, forces
DACK2 active.
Bit 3 - RTC Reset Status. This bit
reflects the state of the reset
signal to the internal 58167
compatible real-time clock, and
is read only.
Bits 2-0 - Not Used
HARD DISK DIAGNOSTIC REGISTER
(001)

This register allows diagnostics of DMA
transfers and selection of the address
range for the hard disk chip select. The
bit assignments for this register are as
follows:
Bits 7-2 - Not Used
Bit 1 -

0 = IBM IDE address range, 1
~ XT controller address range.

Bit 0 -

1 ~ Force DACK3 active.

LED CONTROL REGISTER (007)
This register controls the state of the
LED output of the VL82C032. A 1 in bit
o turns on the LED, and a 0 turns it off.
The remaining bits are not used.

•

VLSI TECHNOLOGY, INC.
VL82C032

TABLE 14. SYSTEM CONTROL REGISTER
Address

W/R

Functions

0061

W/R

b7
b6
b5
b4
b3
b2
b1
bO

=
=
=
=
=
=
=
=

Not Used (0).
Not Used (0).
10CHCK, PC·Bus Memory Parity Check (1 = Disable, 0 = Enable)
On·Board Memory Parity Check (1 = Disable, 0 = Enable)
Not Used (0).
Not Used (0).
Speaker Data, EnablelDisable Output of 8253·Timer 2 (1 = Enable, 0 = Disable)
Enable/Disable 8253·Timer 2 (1 = Enable, 0 = Disable)

TABLE 15. SYSTEM STATUS REGISTER
Address

W/R

Functions

0062

W/R

b7 = Parity Error (RIO)
b6 = 110 Channel Error (RIO)
b5 = Timer 2 Output (RIO)
b4 = Reserved (0)
b3 = Reserved (0)
b2 = No Hard Disk (1)
b1 = Coprocessor Installed (0)
bO = Reserved (0)

TABLE 16. PERIPHERAL SELECT CONTROL REGISTER
Address

W/R

Functions

065

W/R

b7 = Parallel Port Output Enable
b6 = Reserve (0)
b5 = Reserve (0)
b4 = Serial Port 1 Select
b3 = Floppy Controller Select
b2 = Video Select
b1 = Parallel Port Select
bO = Hard Disk Select

5·43

•

VLSI TECHNOLOGY, INC.
VL82C032

TABLE 17. FLOPPY CONTROL LOGIC 1/0 ADDRESSES
Address

W/R

Functions

03FO

RASA Port
b7= IR06
b6= DR02
b5 = Step (Latched)
b4= Track 0
b3 = Head 1 Select
b2 = Index
b1 = Write Protect
bO = Direction

03F1

RAS B Port
b7 = Not Used
b6 = Drive Select 1
b5 = Drive Select 0
b4 = Write Data (Latched)
b3 = Read Data (Latched
b2 = Write Enable (Latched)
b1 = Drive Select 3
bO = Drive Select 2

PARALLEL PORT STATUS REGISTER
Address=0379h (Read Only)

17161514131211101

L--_ _ _ _ _

J2 Transmit/Receive Data

CMOS SRAM INDEX REGISTER
Address=00D4h (Read/Write)

1111,---c=--

1
Not Used
.....- - - - Printer Error
Printer Selected
End of Paper
Printer Acknowledge
' - - - - - - - - - - Printer Busy
.

17161514131211101

PARALLEL PORT CONTROL REGISTER
Address=-037Ah (Read/Write)

1 - - - - Index Pointer
.....- - - - - - - Not Used

17161514131211101

II I I

CMOS SRAM DATA PORT
Address=00D5h (Read/Write)

L--_ _ _ _ _

CMOS Data

PARALLEL PORT DATA REGISTER
Address=0378h (ReadlWrite)

~:!~~..: Food

KEYBOARD/MOUSE DATA REGISTER
Address=0060h (ReadlWrite)

17161514131211101
1 - 1_ _ _ _ _

Start Device
Select Printer
EN/DIS Interrupt
'--_ _ _ _ _ _ _ Not used

17161514131211101

17161514131211101
Port Data

' - - _ _ _ _ _ Keyboard/Mouse Data

5-44

•

VLSI TECHNOLOGY, INC.
VL82C032

INTERRUPT EXTENDED CONTROL REGISTER
Address=OOA 1h (Read/Write)

17161514131211101

17161514131211101
J1 Transmit/Receive Data

1-.-_ _ _ _ _

J2 TRANSMIT/RECEIVE REGISTER
Address=0068h (Read/Write)

III

M,,' RTC

lo",,"~

Not USed
Mask J1 Interrupt
Mask J2 Interrupt
' - - - - - - - - - Not Used

17161514131211101
1....-_ _ _ _

J2 Transmit/Receive Data

INTERRUPT EXTENDED STATUS REGISTER
Address=OOAOh (Read Only)

17161514131211101
TRANSMIT CONTROL REGISTER
Address=0069h (Read/Write)

I I~
.

1-.-_ _ _ _ _ _ _
1-.-_ _ _ _ _ _ _ _ _

Not Used
Enable NMI Diagnostic
J1 Transmit Toggle Bit
J2 Transmit Toggle Bit
J1/J2 Clock Disable
Block I/O 63h Read
Enable Interrupt Diagnostic

RECEIVE CONTROL REGISTER
Address=006Sh (Read/Write)

171s15141312111 01
II

'- J1J2 Parity
P.my Err.,
(RIOI
Error (R/O)

Key Lock Status (R/O)
Keyboard Connected
J1 Receive Toggle Bit
' - - - - - - - - J1 Clock Control Bit
1-.-_ _ _ _ _ _ _ _ J2 Receive Toggle Bit
1-.-_ _ _ _ _ _ _ _ _ J2 Clock Control Bit

KEYBOARD/MOUSE RECEIVE STATUS REGISTER
Address=OOSAh (Read Only)

171s15141312111 01
II

I I '-

~L
L-

IRal (RTC)
Not Used
IRa1 (J1)
IRa1 (J2)
' - - - - - - - - - Not Used

17161514131211101

Floppy HIGHDNTY lopm

Not Used
J2 Receive Buffer Full
J1 Status (O=ln Progress)
Not Used
1-.-_ _ _ _ _ _ J1 Receive Buffer Full
1-.-_ _ _ _ _ _ _ _ J2 Status (O=ln Progress)
' - - - - - - - - - - - Not Used

5-45

•

VLSI TECHNOLOGY, INC.
VL82C032

STANDBY ENABLE REGISTER
Address=001 Eh (ReadlWrite)

17161514131211101

II TIL E~ISB2~T;m~'

ENIDIS Speaker Data
Not Used
ENIDIS On-Board Parity Check
ENIDIS IOCHCK
Not Used

1 . . . .-

Standby Enable Bit
Not Used

SYSTEM STATUS REGISTER
Address=00S2h (ReadlWrite)

T il

STANDBY CONTROL REGISTER
Address=001 Ch (Read Only)

17161514131211101

L- Reserved, 0

Coprocessor Installed
Hard Disk Installed
L
Reserved,O
' - - - - - - - - Timer 2 Output Status (RIO)
1--_ _ _ _ _ _ _ _ IOCHCK Status (RIO)
_____

1 - .- - - - -

Standby Control Bit
Not Used

' - - - - - - - - - - - Parity Error Status (RIO)

HARD DISK CONTROUDIAGNOSTIC REGISTER
Address=00D1 h (ReadlWrite)
171s15141312111 0 1

1 - .- - - - - - -

Force to Detect DACK
Controller Type Select
Not Used

IDREGISTER
Address=00D6h (Read Only)

MISCELANEOUS CONTROUSTATUS REGISTER
Address=OODOh (ReadlWrite)

17161514131211101

' - - - - - - - VL82C032 ID Code

I LlNmu,oo

LED CONTROL REGISTER
Address=00D7h (ReadlWrite)

1..-_ _ _ _ _ _
1--_ _ _ _ _ _ _

17161514131211101

1--_ _ _ _ _

1--_ _ _ _ _ _ _ _ _

LED Output State
Not Used

5-46

RTC Reset Status (RIO)
Force DACK2 Active
Enable Serial Port 2
RTC Clock Status (RIO)
DRVTYPE Control Bit

•

VLSI TECHNOLOGY, INC.
VL82C032

AC CHARACTERISTICS:
Symbol

=DoC to +70°C, VCC =5 V ±5%, GND =0 V

Parameter

Min

Max

Unit

tSU1

Address Setup Time before Command

tH2

Address Hold Time after Command

tSU3

ADSEL Setup Time before Command

tH4

ADSEL Hold Time after Command

tH5

Read Data Invalid from End of Read

tH6

Write Data Hold Time

tD7

Real Time Controller Data Valid from Read

ns
160

tSUB

Real Time Controller Write Data Setup Time

109

Asynchronous Controller Data Valid from Read

tSU10

Asynchronous Controller Write Data Setup Time

1011

Timer Controller Data Valid from Read

160

1012

Timer Controller Data Valid from ADDR

260

110

tSU13

Timer Controller Write Data Setup Time

1014

Internal Registers Data Valid from Read

tSU15

Internal Registers Write Data Setup Time

tD16

Interrupt Controller Data Valid from Read

tSU17

Interrupt Controller Write Data Setup Time

tD1B

Interrupt Vector from Interrupt Acknowledge

1019

Interrupt Vector Invalid after Acknowledge

100

ns
ns

140
160

160

100

ns
150

100

5-47

ns
ns

150
5

ns
ns

Condition

•

VLSI TECHNOLOGY, INC.
VL82C032

FIGURE 1. "READ TIMING DIAGRAM FOR TIMER CONTROLLER (8253)

SADR

VALID ADDRESS
~tSU1~

ADSELO,
ADSEL1

I+-tH2_

VALID SELECTS

'~SU3"

!--tH4-

-XIOWR

~tH5

tD11
DATA

VALID DATA

tD12

FIGURE 2. "WRITE TIMING DIAGRAM FOR TIMER CONTROLLER (8253)

ADSELO,
ADsEL1----")Kr----------------~V~A~L~ID~A=D~DR=E~S=S------------~)KIr---------SADR----'II'~t-S-U-1------------~~~~~=----------~~I'----------

-tH2

-'k"

-XIOWR

____

I
LI+-----tSU13----~--~J tH6
DATA ________________________fi*~
~V~A~L1~D~D~A~T~A~_fil~____________

FIGURE 3. "READ TIMING DIAGRAM FOR ASYNCHRONOUS SERIAL COMMUNICATIONS CONTROLLER (8250A)

SADR ~
ADSELO,
ADSEL1

VALID ADDRESS

~FtSU1~

_tH2_

VALID SELECTS

t tSU3

-tH4-

-XIOWR
tD9
1

DATA

~tH5
VALID DATA
)K.

FIGURE 4. "WRITE TIMING DIAGRAM FOR ASYNCHRONOUS SERIAL COMMUNICATIONS CONTROLLER (8250A)

SADR
ADSELO,
ADSEL1

--)I(

VALID ADDRESS

tSU1

==f
I

VALID SELECTS

+--tH2~

+--tH4-

tSU3

-XIOWR
DATA

*
I

tSU10
VALID DATA

"Note: Data Lines· Output Loading = 40 pF.
5-48

tH6

•

VLSI TECHNOLOGY, INC.
VL82C032

FIGURE 5. ·READ TIMING DIAGRAM FOR INTERRUPT CONTROLLER (8259)

SADR
ADSELO,
ADSEL1

VALID ADDRESS

)I(

J;::tSU1_

i4-tH2_
VALID SELECTS

)I(

tSU3

-XIORD

~tH4-

tD16

DATA

~tH5

VALID DATA

)j(

FIGURE 6. "WRITE TIMING DIAGRAM FOR INTERRUPT CONTROLLER (8259)

SADR -;K
j;"tSU1_
ADSELO, ~
ADSEL1
~I tSU3

VALID ADDRESS
~tH2_

VALID SELECTS
!+-tH5-

-XIOWR

I'-

t=~_tD17
DATA

VALID DATA

)j(

tH6

FIGURE 7. "INTERRUPT ACKNOWLEDGE TIMING DIAGRAM FOR INTERRUPT CONTROLLER (8259)

1:==

-INTA

DATA _ _ _ _ _ _ _ _ _1_0_18:_-_-_-_-_"'*VALID VECTOR

AD~I_D_l_9- - - - -

FIGURE 8. ·READ TIMING DIAGRAM FOR INTERNAL REGISTERS

SADR

VALID ADDRESS

)j(

~tSU1--'
ADSELO, - ' - x
ADSEL1

f4--tH2_
VALID SELECTS

tSU3

f4--tH5-

-XIORD
tD14
DAtA

~tH5
VALID DATA

"Note: Data Lines - Output Loading = 40 pF.

5-49

)I(

•

VLSI TECHNOLOGY, INC.
VL82C032

FIGURE 9. 'WRITE TIMING DIAGRAM FOR INTERNAL REGISTERS

VALID ADDRESS

)I(

SADR

_tH2_

J;;:tSU1 ....

ADSELO,
ADSEL1

VALID SELECTS
tSU3

-tH4-

-XIOWR

~tH6

.t:=tSU15
VALID DATA

DATA

)I(

FIGURE 10. "TIMING DIAGRAM FOR FLOPPY OR HARD DISK CHIP SELECT

SADR

VALID ADDRESS

)I(

j-tSU1-:::::-.J

ADSELO,
ADSEL1

~ tH2

VALID SELECTS

~ tH4

BtSU3
-FLPCS,
-SELHDK

"*"

FIGURE 11. 'READ TIMING DIAGRAM FOR REAL TIME CLOCK (58167A)

SADR
ADSELO,
ADSEL1

VALID ADDRESS
tSU1
VALID SELECTS

~tSU3

-'I<-

-XIORD

t07

DATA

VALID DATA

VALID ADDRESS

)I(

ItSU1
ADSELO,
ADSEL1
-XIOWR
DATA

VALID SELECTS

)I(

~ tH2

~ tH4

BtSU3

"*"

tH4

~tH5

FIGURE 12. 'WRITE TIMING DIAGRAM FOR REAL TIME CLOCK (58167A)

SADR

tH2

J~=::::;,tSU8 _____ i::j
)j(

VALID DATA

'Note: Data Lines - Output Loading = 40 pF.
"Note: FLPCSH· Output Loading = 20 pF. -SELHDK· Output Loading = 20 pF.

5-50

)I(

tH6

•

VLSI TECHNOLOGY, INC.
VL82C032

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

-1 O·C to +70·C

Storage Temperature

-65·C to + 150·C

Supply Vo~age to
Ground Potential -0.5 V to VCC +0.3 V

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Applied Output
Vo~age

-0.5 V to VCC +0.3 V

Applied Input
Voltage

-0.5 V to +7.0 V

DC CHARACTERISTICS:

= o·c to +70·C, VCC =5 V ±5%, GND = 0 V

Symbol

Parameter

Min

VOH

Output High Voltage

2.4

VOL

Output Low Voltage

VIH

Input High Voltage

2.2

VCC+0.5

Pins 16-19,49,94

VIH

Input High Voltage

2.0

VCC+ 0.5

All Other Inputs·

-0.5

0.8

TTL

Max

0.45

Unit

Condition

Note

VIL

Input Low Voltage

Output Capacitance

Input Capacitance

CIO

Input/Output Capacitance

III

Input Leakage Current

-150

Pins 82-87
All Other Inputs·

III

Input Leakage Current

-10

OLi

Output Leakage Current

-10

ICC

Operating Supply Current

Note: Output Current Driving Capabilities for VOH and VOL DC Parameters
IOL

VL82C032 Pins

-400~

20mA

-LED, PDO-PD7

-400~

16mA

J1DATA, J2DATA, J1CLOCK, J2CLOCK

-400~

10mA

-IN IT, -STROBE, -SELIN, -AUTOFD

-400~

SmA

XDO-XD7, KEYLOCK, -SELHDK

-400~

4mA

INTR, SPKOUT, -FLPCS, -XBFRD, TXD1, TXD2, -DTR1, -DTR2, -RTS1, -RTS2

-400~

2mA

DRVTYPE. -PRE, -RD3FO, -RD3Fl. - TIMER2

IOH

• RTCLKIN (Pin 56) is a crystal input and is not intended to conform to typical TTL input levels. For testing purposes it is driven
to 4.0 V and 0.2 V for a logic high and low respectively.

5-51

•

VLSI TECHNOLOGY, INC.
VL82C032

NOTES:

5-52

•

VLSI TECHNOLOGY, INC.

SECTION 6
PERIPHERALS

Logic Products Division

•

VLSI TECHNOLOGY, INC.

•

VLSI TECHNOLOGY, INC.
YL16C450·YL82C50A·YL82C50
ASYNCHRONOUS COMMUNICATIONS ELEMENT

FEATURES

DESCRIPTIONS

• Full double buffering

The VL16C450 is an asynchronous
communications element (ACE) that is
functionally equivalent to the
VL82C50A, but is an improved specification version of that part. The
improved specifications provide
ensured compatibility with state-of-theartCPUs.

the CPU. The complete status of the
ACE can be read at any time during
functional operation by the CPU. The
information obtained includes the type
and condition of the transfer operations
being performed, and error conditions
involving parity, overrun, framing, or
break interrupt.

The VL 16C450, VL82C50A, and
VL82C50 ACEs serve as serial data
inpuVoutput interfaces in microcomputer
systems. They perform serial-toparallel conversion on data characters
received from peripheral devices or
modems, and parallel-to-serial conversion on data characters transmitted by

A programmable baud rate generation
is included that can divide the timing
reference clock inftut by a divisor
between 1 and (2 6_ 1).

• Independent control of transmit,
receive, line status and data set
interrupts
• Modem control signals include -CTS,
-RTS, -DSR, -DTR, -RI and -DCD
Programmable serial interface
characteristics:
- 5-,6-, 7- or 8-bit characters
- Even-, odd-, or no-parity bit
generation and detection
- 1-, 1 1/2- or 2-stop bit generation
- Baud rate generation (DC to 56K
baud)
Full status reporting capabilities

The VLSI family of ACEs is available
packaged in a plastic leaded chip
carrier as well as a plastic DIP .. .'

• Three-state TTL drive capabilities for
bidirectional data bus and control bus
-OCO'

PIN DIAGRAMS
VL16C450
VL82C50A
VL82C50

VL16C450
VL82C50A
VL82C50

VCC

-AI

-OCO"
-OSR
-CTS

04
05

06
07

-OUT1
-DTR

RCLK
SIN
SOUT
CSO
CS1
-CS2
-BAUOOUT
XTAL1
XTAL2
-DOSTR
OOSTR
VSS

654

05
06
07
RCLK
SIN
N.C.
SOUT
CSO
CSl
-CS2
-BAUCOUT

-ATS

3 2 1 44 4342 41 40

7
8
9
10
11
12
13
14
15
16
17

•

39
38
37
36
35
34
33
32
31
30
29

-OUT2
INTRPT
N.C.
XTAl2

AO
A1
A2

OOSTR

-ADS
CSOUT
OOIS
OISTR
-OISTR

"On the VL82C50, Pin 38 (Pin 42 on
the PLCC package) is also called
-ALSO.

N.C.

-COSTA

CSOUT

-OISTR
OISTR

ORDER INFORMATION
Part
Number

Clock
Frequency

Package

VL16C450-PC
VL 16C450-QC

3.1 MHz

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)

VL82C50A-PC
VL82C50A-QC

3.1 MHz

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)

VL82C50-PC
VL82C50-QC

3.1 MHz

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70·C.
6-3

MR
-OUTl
-OTR
-RTS
-OUT2
N.C.
INTRPT
N.C
AO
Al
A2

•

VLSI TECHNOLOGY, INC.
YL16C450·YL82C50A·YL82C50

BLOCK DIAGRAM

SIN

RCLK

A2
(15)
-BAUDOUT
CSO
TRANSMITIER
TIMING

CS1

-CS2

CONTROL
-AOS
MR
DlSTR

SELECT
&

CONTROL
LOGIC
SOUT

-DISTR
DOSTR

-RTS

-DOSTR

-CTS

DDIS
MODEM
CONTROL
LOGIC

CSOUT
XTAL1

-DTR
-DSR
-DCD

XTAI2
-RI
(34)
(40)
POWER
(20)
SUPPLY

••

-OUT1
+5V

(31)
-OUT2

GND
(30)

INTRPT

Note: Applicable pin numbers (DIP) are included within parentheses.

6-4

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

SIGNAL DESCRIPTIONS
Pin

Signal
Name

Signal
Type

Signal

Number (DIP)

00·07

1·8

110

Data Bits 0 through 7 • The Data Bus provides eight, three·state I/O lines
for the transfer of data, control and status information between the ACE
and the CPU. These lines are normally in a high·impedance state except
during read operations. DO is the least significant bit (LSB) and is the first
serial data bit to be received or transmitted.

RCLK

Receive Clock Input· The external clock input to the ACE receiver logic
(16X SIN data rate).

SIN

Serial Data Input· The serial data input moves information from the
communication line or modem to the ACE receiver circuits. A mark (1) is
high, and a space (0) is low. Data on serial data input is disabled when
operating in the Loop Mode.

SOUT

CSO, CS1,
-CS2

12·14

-BAUOOUT

XTAL1

Crystal Input Pin 1 • Input for external timing reference input or pin of
crystal (See Basic Configuration).

XTAL2

Crystal Input Pin 2· Input for pin of crystal (See Basic Configuration).

-OOSTR

Write Strobe· This is an active low input which causes data from the data
bus (00·07) to be input to the ACE.

Description

Serial Data Output· This line is the serial data output from the ACE's trans·
mitter circuitry. A mark (1) is a logic "one" (high) and space (0) is a logic
''zero· (low). SOUT is held in the mark condition when the transmitter is
disabled, reset is true, the Transmitter Register is empty, or when in the
Loop Mode.
Chip Selects· The Chip Select inputs act as an enable for the device.
When -CS2 is low and CSO and CSI are both high, the chip is selected.

Baud Rate Output· This output signal for the transmitter section is equal to
the internal reference frequency, divided by the selected divisor.

OOSTR

Write Strobe· Same as -OOSTR, but uses an active high input.

VSS

Ground (0 V).

-OISTR

Read Strobe· This is an active low input which causes the ACE to output
data to the data bus (00·07).

OISTR

Read Strobe· Same as -OISTR, but uses an active high input.

DOIS

Driver Disable· This pin goes low whenever the microprocessor is reading
data from the ACE. This signal may be used to disable an external trans·
ceiver.

CSOUT

Chip Select Out· A high on this pin indicates that the chip has been
selected by the chip select input pins.

-ADS

Address Strobe Input· When this pin is low, the state of the Register Select
and Chip Select pins is latched internally.

AO·A2

28·26

Address Lines AO·A2 • The address lines select the internal registers
during CPU bus operations.

INTRPT

No Connection.

Interrupt Output· This pin goes high (when enabled by the Interrupt
Enable Register) whenever a Receiver Error Flag, Received Data Avail·
able, Transmitter Holding Register Empty, or Modem Status condition is
detected.

6·5

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number (DIP)

Signal
Type

Signal
Description

-OUT2

Output 2 - User defined output that can be set to an active low by program·
ming bit 3 of the Modem Control Register to a high level. This signal is
cleared (high) by writing a logic 0 to the OUT2 bit (MCR) or whenever a
reset occurs.

-RTS

Request to Send· The -RTS pin is set low by writing a logic 1 to MCR bit 1
of the ACE's Modem Control Register. The -ATS pin is reset high by
reset. A Iowan the -RTS pin indicates that the ACE has data ready to
transmit.

-DTR

Data Terminal Ready· The -OTR pin can be set (low) by writing a logic 1
to MCR, Modem Control Register bit 0 of the ACE. This signal is cleared
(high) by writing a logic 0 to the DTR bit (MCR) or whenever a reset occurs.
When active (low), the -DTR pin indicates that the ACE is ready to receive
data.

-OUT1

Output 1 - A user defined output that can be set to an active low by programming bit 2 of the Modem Control Register to a high level. This signal
is cleared (high) by writing a logic 0 to the OUT1 bit (MCR) or whenever a
reset occurs.

Master Reset - When high, the reset input forces the ACE into an idle
mode in which all data activities are suspended. The Modem Control
Register (MCR) along with its output, is cleared. The Line Status Register
(LSR) is cleared except for the THRE and TEMT bits, which are set. All
functions of the device remain in an idle state until programmed to resume
activities.

-CTS

Clear to Send - The logical state of the -CTS pin is reflected in the CTS bit
of the (MSR) Modem Status Register [CTS is bit 4 of the MSR, written
MSR(4)] of the ACE. A change of state of the -CTS pin, since the previous
reading of the MSR, causes the setting of DCTS in the Modem Status
Register.

-DSR

Data Set Ready - The logical state of the -DSR pin is reflected in MSR(5)
of the Modem Status Register. DDSR MSR(1) indicates whether the -DSR
pin has changed state since the previous reading of the MSR.

-DCD (-ALSD)

Data Carrier Detect (Receive Line Signal Detect) - -DCD (-RLSD) is a
modem input whose condition can be tested by the CPU by reading
MSR(7) (DCD or RLSD) of the Modem Status Register. MSR(3) (DDCD or
DRLSD) of the Modem Status Register indicates whether the -DCD
(-RLSD) input has changed since the previous reading of the MSR. -DCD
(-RLSD) has no effect on the receiver.

-RI

Ring Indicator Input - The -AI signal is a modem control input whose
condition is tested by reading MSR(6) (RI) of the ACE. The Modem Status
Register output TERI MSR(2) indicates whether the RI input has changed
from high to low since the previous reading of the MSR.

VCC

Power Supply - The power supply requirement is 5 V ±5%.

6-6

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

REGISTERS
Three types of internal registers are
used in the serial channel of each ACE.
They are used in the operation of the
device, and are the control, status, and
data registers. The control registers are
the Bit Rate Select Register DLL
(Divisor Latch LSB) and DLM (Divisor
Latch MSB), Line Control Register,
Interrupt Enable Register, and the
Modem Control registers, while the
status registers are the Line Status
Registers and the Modem Status
Register. The data registers are the
Receiver Buffer Register and the
Transmitter Holding Register. The
Address, Read, and Wr~e inputs are
used in conjunction with the Divisor
Latch Access Bit in the Line Control
Register [LCR(7)] to select the register
to be written or read (see Table 1).
Individual b~s within these registers are
referred to by the register mnemonic
and the bit number in parenthesis. As
an example, LCR(7) refers to Line
Control Register Bit 7.
The Transmitter Buffer Register and
Receiver Buffer Register are data
registers that hold from five to eight b~s
of data. If less than eight data bits are
transmitted, data is right justified to the
LSB. Bit 0 of a data word is always the
first serial data bit received and transmitted. The ACE data registers are double-

buffered so that read and write operations may be performed when the ACE
is performing the parallel-to-serial or
serial-to-parallel conversion.
LINE CONTROL REGISTER
The format of the data character is
controlled by the Line Control Register.
The contents of the LCR may be read.
The contents of the LCR are described
below in Figure 1.
LCR(O) and LCR(l) Word Length Select
bit 1: The number of bits in each serial
character is programmed as shown in
Figure 1.
LCR(2) Stop Bit Select: LCR(2) specifies the number of stop bits in each
transm~ed character. If LCR(2) is a
logic 1 when a S-bit word length is
selected, I.S stop bits are generated.
If LCR(2) is a logic 1 when either a 6-,
7-, or a-bit word length is selected, two
stop bits are generated. The receiver
always checks for one stop bit.
LCR(3) Parity Enable: When LCR(3) is
high, a parity bit between the last data
word bit and stop bit is generated and
checked.
LCR(4) Even Parity Select: When
parity is enabled [LCR(3)-1], LCR(4)=O
selects odd parity, and LCR(4)=1
selects even parity.

TABLE 1. SERIAL CHANNEL INTERNAL REGISTERS
DLAB A2

Mnemonic

RBR

Receiver Buffer Register (read only)

THR

Transmitter Holding Register (write only)

IER

Interrupt Enable Register

IIR

Interrupt Identification Register (read only)

LCR

Line Control Register

MCR

Modem Control Register

LSR

Line Status Register

MSR

Modem Status Register

SCR

Scratch Register

DLL

Divisor Latch (LSB)

DLM

Divisor Latch (MSB)

X = "Don't Care"

0= Logic Low

1 = Logic High

Note: The serial channel is accessed when CSO is low.
6-7

LCR(S) Stick Parity: When parity is
enabled [LCR(3)-1], LCR(S)-1 causes
the transmission and reception of a
parity bit to be in the opposite state from
the value of LCR(4). This allows forced
parity to a known state and the receiver
to check the parity bit in a known state.
LCR(6) Break Control: When LCR(6) is
set to a logic 1, the serial output (SOUT)
is forced to the spacing (logic 0) state.
The break is disabled by setting LCR(6)
to a logic o. The Break Control bit acts
only on SOUT and does not effect the
transm~er logic. If the following
sequence is used, no invalid characters
will be transmitted because of the break.
1. Load all "O"s pad character in
response to THRE.
2. Set the break in response to the next
THRE.
3. Wait for the transmitter to be idle
(TEMT=1), then clear the break when
the normal transmission has to be
restored.
LCR(7) Divisor Latch Access Bit (DLAB);
LCR(7) must be set high (logic 1) to
access the Divisor Latches DLL and
DLM of the Baud Rate Generator during
a read or write operation. LCR(7) must
be input low to access the Receiver
Buffer, the Transm~er Holding, or the
Interrupt Enable Registers.
LINE STATUS REGISTER
The Line Status Register (LSR) is a
single register that provides status
indications.
The Line Status Register shown in Table
2 is described below:
LSR(O) Data Ready (DR): Data Ready is
set high when an incoming character has
been received and transferred into the
Receiver Buffer Register. LSR(O) is
reset low by a CPU read of the data in
the Receiver Buffer Register.
LSR(l) Overrun Error (OE): Overrun
Error indicates that data in the Receiver
Buffer Register was not read by the CPU
before the next character was transferred into the Receiver Buffer Register,
overwriting the previous character. The
OE indicator is reset whenever the CPU
reads the contents of the Line Status
Register.

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

FIGURE 1. UNE CONTROL REGISTER

IL~R IL~R IL~RI L;R IL~R IL~R IL~R IL~R I

Word
Length
Select

0 1
1 0
1 1

Stop
0
Bit Select 1

5 Data
6 Data
7 Data
8 Data

Bits
Bits
Bits
Bits

= 1 Stop Bit
= 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits If 6, 7, 8 Data Bits Selected

-'"

.
..

Parity
Enable

o = Parity Disabled

Even
Parity
Select

o = Odd Parity

Stick
Parity

o = Stick Parity Disabled

1
1

= Parity Enabled
= Even Parity

= Stick Parity Enabled

Break
."" Control

o = Break Disabled
1 = Break Enabled

o = Access Receiver Buffer

Divisor
Latch
Access
Bit

1 = Access Divisor Latches

LSR(2) Parity Error (PE): Parity Error
indicates that the received data charac·
ter does not have the correct even or
odd parity, as selected by the Even
Parity Select bit LCR(4). The PE bit is
set high upon detection of a parity error,
and is reset low when the CPU reads
the contents of the LSR.

LSR(1 )·LSR(4) are the error conditions
that produce a Receiver Line Status
interrupt (priority 1 interrupt in the
Interrupt Identification Register (IIR)
when any of the conditions are detected.
This interrupt is enabled by setting
IER(2).1 in the Interrupt Enable
Register.

LSR(3) Framing Error (FE): Framing
Error indicates that the received charac·
ter did not have a valid stop bit. LSR(3)
is set high when the stop bit following
the last data bit or parity bit is detected
as a zero bit (spacing level). The FE
indicator is reset low when the CPU
reads the contents of the LSR.

LSR(5) Transmitter Holding Register
Empty (THRE): THRE indicates that the
ACE is ready to accept a new character
for transmission. The THRE bit is set
high when a character is transferred
from the Transmitter Holding Register
into the Transmitter Shift Register.
LSR(5) is reset low by the loading the
Transmitter Holding Register by the
CPU. LSR(5) is reset low by the loading
of the Transmitter Holding Register by'
the CPU. LSR(5) is not reset by a CPU
read of the LSR.

LSR(4) Break Interrupt (BI): Break
Interrupt is set high when the received
data input is held in the spacing (logic 0)
state for longer than a full word transmission time (start bit + data bits + parity
+ stop bits). The BI indicator is reset
when the CPU reads the contents of the
Line Status Register.

When the THRE interrupt is enabled
IER(1). THRE causes a priority 3
interrupt in the IIR. If THRE is the

6·8

interrupt source indicated in IIR,
INTRPT is cleared by a read of the IIR.
LSR(6) Transmitter Empty (TEMT):
TEMT is set high when the Transmitter
Holding Register (THR) and the Transmitter Shift Register (TSR) are both
empty. LSR(6) is reset low when a
character is loaded into the THR and
remains low until the character is
transferred out of SOUTo TEMT is not
reset low by a CPU read of the LSR.
LSR(7): This bit is always o.
MODEM CONTROL REGISTER
The Modem Control Register (MCR)
controls the interface with the modem or
data set as described in Figure 2. MCR
can be written and read. The -RTS and
-DTR outputs are directly controlled by
their control bits in this register. A high
input asserts a low (true) at the output
pins. MCR Bits 0, 1, 3, and 4 are shown
as follows:

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

TABLE 2. LINE STATUS REGISTER BITS

LSRBITS
LSR(O) Data Ready (DR)

Ready

Not Ready

LSR(1) Overrun Error (OE)

Error

No Error

LSR(2) Parity Error (PE)

Error

No Error

LSR(3) Framing Error (FE)

Error

No Error

LSR(4) Break Interrupt (BI)

Break

No Break

LSR(5) Transmitter Holding Register Empty (THRE)

Empty

Not Empty

LSR(6) Transmitter Empty (TEMT)

Empty

Not Empty

LSR(7) Not Used

MCR(O): When MCR(O) is set high, the
-DTR output is forced low. When
MCR(O) is reset low, the -DTR output is
forced high. The -DTR output of the
serial channel may be input into an
inverting line driver in order to obtain the
proper polarity input at the modem or
dataset.
MCR(1): When MCR(1) is set high, the
-RTS output is forced low. When
MCR(1) is reset low, the -ATS output is
forced high. The -RTS output of the
serial channel may be input into an
inverting line driver in order to obtain the
proper polarity input at the modem or
data set.
MCR(2): When MCR (2) is set high
-OUT1 is forced low.
MCR(3): When MCR(3) is set high, the
-OUT2 is forced low.
MCR(4): MCR(4) provides a local
loopback feature for diagnostic testing
of the channel. When MCR(4) is set
high, Serial Output (SOUT) is set to the
marking (logic 1) state, and the receiver
data input Serial Input (SIN) is discon·
nected. The output of the Transmitter
Shift Register is looped back into the
Receiver Shift Register input. The four
modem control inputs (-CTS, -DSR,
-DCD (-RLSD), and -AI) are disconnected. The modem control outputs
(-DTR, -RTS, -OUT1 and -OUT2) are
internally connected to the four modem
control inputs. The modem control
output pins are forced to their inactive
state (high) on the VL 16C450.
In the diagnostic mode, data transmitted
is immediately received. This allows the
processor to verify the transmit and

receive data paths of the selected serial
channel.
Bits MCR(5)-MCR(7) are permanently
set to logic O.
MODEM STATUS REGISTER
The MSR provides the CPU with status
of the modem input lines from the
modem or peripheral devices. The MSR
allows the CPU to read the serial
channel modem signal inputs by
accessing the data bus interface of the
ACE in addition to the current status
information, four bits of the MSR
indicate whether the modem inputs have
changed since the last reading of the
MSR. The delta status bits are set high
when a control input from the modem
changes state, and reset low when the
CPU reads the MSR.
The modem input lines are -CTS,
-DSR, -RI, and -DCD (-RLSD).
MSR(4)-MSR(7) are status indications
of these lines. A status bit = 1 indicates
the input is a low. A status bit = 0

indicates the input is high. If the modem
status interrupt in the Interrupt Enable
Register is enabled [IER(3)], an interrupt
is generated whenever MSR(O)-MSR(3)
is set to a one. The MSR is a priority 4
interrupt. The contents of the Modem
Status Register are described in Table

3.
MSR(O) Delta Clear to Send (DCTS):
DCTS displays that the -CTS input to
the serial channel has changed state
since it was read last by the CPU.
MSR(1) Delta Data Set Ready (DDSR):
DDSR indicates that the -DSR input to
the serial channel has changed state
since the last time it was read by the
CPU.
MSR(2) Trailing Edge of Ring Indicator
(TERI): TERI indicates that the -RI
input to the serial channel has changed
state from low to high since the last time
it was read by the CPU. High to low
transitions on -RI do not activate TERI.
MSR(3) Delta Data Carrier Detect rDDCD
(DRLSD)]: DDCD (DRLSD) indicates
that the -OCD (-RLSD) input to the
serial channel has changed state since
the last time it was read by the CPU.
MSR(4) Clear to Send (CTS): Clear to
Send (CTS) is the complement of the
-CTS input from the modem indicating
to the serial channel that the modem is
ready to receive data from the serial
channel's transmitter output (SOUT). If
the serial channel is in Loop Mode
[(MCR(4)-1J, MSR(4) reflects the value
of RTS in the MCR.
MSR(5) Data Set Ready (DSR): Data
Set Ready (DSR) is the complement of

TABLE 3. MODEM STATUS REGISTER BITS
MSR Bit

Mnemonic

Description

MSR(O)
MSR(1)
MSR(2)
MSR(3)
MSR(4)

DCTS
DDSR
TERI
DDCD (DRLSD)

Delta Clear To Send
Delta Data Set Ready
Trailing Edge of Ring Indicator
Delta Data Carrier Detect
Clear To Send

MSR(5)
MSR(6)
MSR(7)

6-9

-CTS
-DSR

Data Set Ready

-RI
-DCD (-RLSD)

Ring Indicator
Data Carrier Detect

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

FIGURE 2. MODEM CONTROL REGISTER

Data
0 = -DTR Output High (Inactive)
Terminal 1 = -DTR Output Low (Active)
Ready
"-_ _.... Request 0 = -RTS Output High (Inactive)
To Send 1 = -RTS Output Low (Active)
' - - - - -.... OUT1

0 = -OUT1 Output High

1 = -OUT1 Output Low
" - - - - - -.... OUT2
" - - - - - - - - - - . . LOOP

0 = -OUT2 Output High
1 = -OUT2 Output Low
0 =

LOOP Disabled
1 = LOOP Enabled

" - - - - - - - - - - - -. . Bits are Set to Logic "0".

the -DSR input from the modem to the
serial channel which indicates that the
modem is ready to provide received
data to the serial channel receiver
circuitry. Ifthe channel is in the loop
mode [MCR(4)=1], MSR(5) reflects the
value of DTR in the MCR.
MSR(S) Ring Indicator (RI): Is the
complement of the -RI input (pin 39). If
the channel is in the Loop Mode
(MCR(4)=1), MSR(S) reflects the value
of -OUT1 in the MCR.
MSR(7) Data Carrier Detect (DCD)I
Receive Line Signal Detect (RLSD):
Data Carrier DetectlReceive Line Signal
Detect indicates the status of the Data
Carrier Detect/Receive Line Signal
Detect (-DCD/-RLSD) input. If the
channel is in the Loop Mode
(MCR(4)=1), MSR(2) reflects the value
of -OUT2 in the MCR.
Reading the MSR register will clear the
delta modem status indications but has
no effect on the other status bits.
For LSR and MSR, the setting of status
bits is inhibited during status register
read operations. If a status condition is
generated during a read -DISTR
operation, the status bit is not set until
the trailing edge of the read.
If a status bit is set during a read
operation, and the same status condition occurs, that status bit will be
cleared at the trailing edge of the read
instead of being set again.

DIVISOR LATCHES
The ACE serial channel contains a
programmable Baud Rate Generator
(BRG) that divides the clock (DC to 3.1
MHz) by any divisor from 1 to 216-1 (see
also BRG description). The output
frequency of the Baud Generator is 1SX
the data rate [divisor # _ clock + (baud
rate x 1S)]. Two a-bit divisor latch
registers store the divisor in a 16-bit
binary format. These Divisor Latch
registers must be loaded during initialization. Upon loading either of the
Divisor Latches, a 16-bit baud counter is
immediately loaded. This prevents long
counts on initial load.
RECEIVE BUFFER REGISTER
The receiver circuitry in the serial
channel of the ACE is programmable for
5, S, 7, or a data bits per character. For
words of less than a bits, the data is
right justHied to the least significant bit
LSB = Data Bit 0 [RBR(O)]. Data Bit 0
of a data word [RBR(O)] is the first data
bit received. The unused bits in a
character less than a bits are O's.
Received data at the SIN input pin is
shifted into the Receiver Shift Register
by the 16X clock provided at the eLK
input. This clock is synchronized to the
incoming data based on the position of
the start bit. When a complete character is shifted into the Receiver Shift
Register, the assembled data bits are
parallel loaded into the Receiver Buffer
Register. The DR flag in the LSR
register is set.
6-10

Double buffering of the received data
permits continuous reception of data
without losing received data. While the
Receiver Shift Register is shifting a new
character into the serial channel, the
Receiver Buffer Register is holding a
previously received character for the
CPU to read. Failure to read the data in
the RBR before complete reception of
the next character results in the loss of
the data in the Receiver Register. The
DE flag in the LSR register indicates
the overrun condition.
TRANSMITTER HOLDING REGISTER
The Transmitter Holding Register (THR)
holds character data until the Transmitter Shift Register is empty and ready to
accept a new character. The transmitter and receiver word lengths are the
same. If the character is less than eight
bits, unused bits bus are ignored by the
transmitter.
Data Bit 0 [THR(O)] is the first serial
data bit transmitted. The THRE flag
[LSR(5)] reflects the status of the THR.
The TEMT flag [LSR(5)] indicates if
both the THR and TSR are empty.
SCRATCHPAD REGISTER
(VL16C450 Only)

Scratch pad Register is an a-bit Readl
Write register that has no effect on
either channel in the ACE. It is
intended to be used by the programmer
to hold data temporarily.

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

INTERRUPT IDENTIFICATION
REGISTER
In order to minimize software overhead
during data character transfers, the
serial channel prioritizes interrupts into
four levels. The four levels of interrupt
conditions are as follows:
1. Receiver Line Status (priority 1)
2. Received Data Ready (priority 2)
3. Transmitter Holding Register Empty
(priority 3)
4. Modem Status (priority 4)
Information indicating that a prioritized
interrupt is pending and the type of
interrupt is stored in the Interrupt
Identification Register (IIR). The IIR
indicates the highest priority interrupt
pending. The contents of the IIR are
indicated in Table 4 and are described
below:
IIR(O): IIR(O) can be used to indicate
whether an interrupt is pending. When
. IIR(O) is low, an interrupt is pending.
IIR(l) and IIR(2) are used to identify the
highest priority interrupt pending as
indicated in Table 4.
IIR(3)-IIR(7): These five bits of the IIR
are logic o.

INTERRUPT ENABLE REGISTER
The Interrupt Enable Register (IER) is
used to independently enable the four
serial channel interrupt sources which
activate the interrupt (INTRPT) output.
All interrupts are disabled by resetting
IER(0)-IER(3) of the Interrupt Enable
Register. Interrupts are enabled by
setting the appropriate bits of the IER
high. Disabling the interrupt system
inhibits the Interrupt Identification
Register and the active (high) INTRPT
output. All other system functions
operate in their normal manner, including the setting of the Line Status and
Modem Status Registers. The contents
of the Interrupt Enable Register is
described in Table S and below:
IER(O): When set to one, IER(O)
enables the Received Data Available
interrupt.
IER(l): When setto one, IER(l)
enables the Transmitter Holding
Register Empty interrupt.

IER(2): When set to one IER(2) enables
the Receiver Line Status interrupt.
IER(3): When set to one, IER(3)
enables the Modem Status Interrupt.
IER(4)-IER(7): These four bits of the
IER are logic O.

TRANSMITTER
The serial transmitter section consists of
a Transmitter Holding Register (THR),
Transmitter Shift Register (TSR), and
associated control logic. The Transmitter Holding Register Empty (THRE) and
Transmitter Empty (TEMT) are two bits
in the Line Status Register which
indicate the status of THR and TSR.
The microprocessor should perform a
write operation to the THR only if THRE
is one. This causes THRE to be set to
zero. The THRE is set high when the
word is automatically transferred from
the THR to the TSR during the transmission of the start bit.
TEMT remains low for the duration of
the transmission of the data word.
Since the data word cannot be transferred from the THR to the TSR until the
TSR is empty, THRE remains low until
the TSR has completed sending the
word.

RECEIVER
Serial asynchronous data is input into
the SIN pin. The ACE continually
searches for a high to low transition from
the idle state. When the transition is
detected, a counter is reset, and counts
the 16X clock to 71/2, which is the
center of the start bit. The start bit is
valid if the SIN is still low. Verifying the
start bit prevents the receiver from assembling a false data character due to a
low going noise spike on the SIN input.
The Line Control Register determines
the number of data bits in a character
(lCR(O), lCR(l», if parity is used
lCR(3), and the polarity of parity
lCR(4). Status for the receiver is
provided in the Line Status Register
when a full character is received,
including parity and stop bits, the Data
Received indication in lSR(O) is set
high. The CPU reads the Receiver
Buffer Register which resets lSR(O). If
the character is not read prior to a new
character transfer from the RSR to the
RBR, the overrun error status indication

6-11

is set in lSR(l). If there is a parity error,
the parity error is set in lSR(2). H a stop
bit is not detected, a framing error indication is set in lSR(3).

If the data into SIN is a symmetrical
square wave, the center of the data cells
will occur within ±3.12S% of the actual
center, providing an error margin of
46.87S%. The start bit can begin as
much as one 16X clock cycle prior to
being detected.

BAUD RATE GENERATOR (BRG)
The BRG generates the clocking for the
UART function, providing standard
ANSI/CCln bit rates. The oscillator
driving the BRG is provided by an
external clock into ClK.
The data rate is determined by the
Divisor latch registers Dll and DlM
and the external frequency. The bit rate
is selected by programming the two
divisor latches, Divisor latch Most
Significant Byte and Divisor latch least
Significant Byte. Setting Dll - 1 and
DlM = 0 selects the divisor to divide by
1 (divide by 1 gives maximum baud rate
for a given input frequency at the ClK
input).
The BRG can use any of three different
popular frequencies to provide standard
baud rates. These frequencies are
1.8432 MHz, 2.4576 MHz, and 3.072
MHz. With these frequencies, standard
bit rates from SO to 38.Sk bps are
available. Tables 6,7 and 8 illustrate
the divisors needed to obtain standard
rates using these three crystal frequencies.

MASTER RESET
After power up, the ACE MR input
should be held high for one microsecond to reset the ACE circuits to an idle
mode until initialization. A high on MR
causes the following:
1. Initializes the transmitter and receiver
internal clock counters.
2. Clears the Line Status Register
(lSR), except for Transmitter Shift
Register Empty (TEMT) and Transmit Holding Register Empty (THRE),
which are set. The Modem Control
Register (MCR) is also cleared. All
of the discrete lines, memory
elements and miscellaneous logic

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50
associated with these register bits
are also cleared or turned off. The
Line Control Register (LCR), Divisor
Latches, Receiver Buffer Register,
Transmitter Buffer Register are not
effected.

Following removal of the reset condition
(reset low), the ACE remains in the idle
mode until programmed.
A hardware reset of the ACE sets the
THRE and TEMT status bit in the LSR.
When interrupts are subsequently
enabled, an interrupt occurs due to
THRE.

PROGRAMMING'
The serial channel of the ACE is programmed by the control register LCR,
IER, DLL and DLM, and MCR. These
control words define the character
length, number of stop bits, parity, baud
rate, and modem interface.
While the control register can be written
in any order, the IER should be written
to last because it controls the interrupt
enables. Once the serial channel is
programmed and operational, these
registers can be updated any time the
ACE serial channel is not transmitting or
receiving data.

SOFTWARE RESET
A software reset of the serial channel is
a useful method for returning to a
completely known state without a
system reset. Such a reset consists of
writing to the LCR, Divisor Latches, and
MCR registers. The LSR and RBR
registers should be read prior to
enabling interrupts in order to clear out
any residual data or status bits which
may be invalid for subsequent operation.

A summary of the effect of a reset on
the ACE is given in Table 9.

TABLE 4. INTERRUPT IDENTIFICATION REGISTER
Interrupt Identification

Interrupt Set And Reset Functions
Interrupt
Source

None

First

Receiver
Line Status

OE,PE
FE, or BI

LSRRead

Second

Received Data
Available

RBRRead

Third

THRE

IIR Read if THRE is the
Interrupt Source or THR Write

Fourth

Modem Status

-CTS,-DSR
-RI, -DCD (-ALSO)

MSRRead

Bit 1

Bit 0

Priority
Level

Interrupt
Reset Control

Interrupt
Flag

BIt2

X = Not Defined.

6-12

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

TABLE 5. SERIAL CHANNEL ACCESSIBLE REGISTERS
Register Bit Number
Address

Bit 7

BH6

Bit 5

Bit 4

Bit 3

Bit2

Bit 1

Bit 0

RBR
(Read Only)

Data
Bit 7
(MSB)

Data
Bit 6

Data
BitS

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
Bit 0

THR
(Write Only)

Data
Bit?

Data
Bit 6

Data
BitS

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
Bit 0

DLL

Bit?

Bit 6

BitS

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DLM

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

BitS

IER

(EDSSI)
Enable
Modem
Status
Interrupt

(ELSI)
Enable
Receiver
Line
Status
Interrupt

(ETBEI)
Enable
Transmitter
Holding
Register
Empty
Interrupt

(ERBFI)
Enable
Received
Data
Available
Interrupt

IIR
(Read Only)

Interrupt
ID
Bit (1)

Interrupt
ID
Bit (0)

"0" tf
Interrupt
Pending

LCR

(DLAB)
Divisor
Latch
Access
Bit

Set
Break

Stick
Parity

(EPS)
Even
Parity
Select

(PEN)
Parity
Enable

(STB)
Number
of Stop
Bits

(WLSB1)
Wont
Length
Select
Bit 1

(WLSBO)
Word
Length
Select
Bit 0

MCR

Loop

Out 2

Out 1

(RTS)
Request
To
Send

(DTR)
Data
Terminal
Ready

LSR

(TEMn
Transmitter
Empty

(THRE)
Transmitter
Holding
Register
Empty

(BI)
Break
Interrupt

(FE)
Framing
Error

(PE)
Parity
Error

(OE)
Overrun
Error

(DR)
Data
Ready

MSR

(DCD)
Data
Carrier
Detect

(RI)
Ring
Indicator

(DSR)
Data
Set
Ready

(CTS)
Clear
to
Send

(DDCD)
Delta
Data
Carrier
Detect

(TERI)
Trailing
Edge
Ring
Indicator

(DDSR)
Delta
Data
Set
Ready

(DCTS)
Delta
Clear
to
Send

SCR

Bit?

Bit 6

BitS

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

'DLAB = 1
., VL 16C450 Only

6-13

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

TABLE 6. BAUD RATES (1.8432 MHz CLOCK)
Desired
Baud Rate

50
75
110
134.5
150

300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

Divisor Used

2304
1536
1047
857
768
384
192
96
64
58

Percent Error
Difference Between
Desired and Actual

0.026
0.058

0.69

48
32
24
16
12
6
3
2

2.86

TABLE 7. BAUD RATES (2.4576 MHz CLOCK)
Desired
Baud Rate

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

Divisor Used

3072
2048
1396
1142
1024
512
256
128
85
77

64
43
32
21
16
8

Percent Error
DHference Between
Desired and Actual

0.026
0.0007

0.392
0.260
0.775

1.587

6-14

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

TABLE 8. BAUD RATES (3.072 MHz CLOCK)
Desired
Baud Rate

Divisor Used

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

Percent Error
Difference Between
Desired and Actual

3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5

0.026
0.034

0.312
0.628
1.23

TABLE 9. MASTER RESET
Register/Signal

Reset Control

Interrupt Enable Register
Interrupt Identification
Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register

Reset
Reset

SOUT
Intrpt (RCVR Errs)
Intrpt (RCVR Data Ready)
Intrpt (THRE)
Intrpt (Modem Status Changes)

Reset
Read LSRlReset
Read RBR/Reset
Read IIRllNrite THRlReset
Read MSRlReset
Reset
Reset
Reset
Reset

-OUT2
-RTS
-DTR

-OUT1

Reset
Reset
Reset
Reset

6-15

Reset

All Bits Low (0-3 Forced and 4-7 Permanent)
Bit 0 is High. Bits 1 and 2 Low
Bits 3-7 Are Permanently Low
All Bits Low
All Bits Low
All Bits Low. Except Bits 5 and 6 Are High
Bits 0-3 Low
Bits 4-7 Input Signal
High
Low
Low
Low
Low
High
High
High
High

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50
AC CHARACTERISTICS: TA =ooe to +7ooe, vee =5 V ±5% (Note 1)
VL16C450
Min

Max

VL82C50A
Min

Max

VL82C50
Min

Max

Unita

Conditlona

Symbol

Parameter

lADS

Address Strobe Width

lAS

Address Setup TIme

IAH

Address Hold Time

tCS

Chip Select Setup TIme

tCH

Chip Select Hold Time

tDIW

-DISTRIDISTR Strobe Width

125

175

tRC

Read Cycle Delay

175

500

Read Cycle = tAR(l) +tDIW
+tRC

360

755

tOO

-DISTRIDISTR to Drive
Disable Delay

100 pF Load
Note 3

tODD

Delay from -DISTRIDISTR
to Data

125

175

100 pF Load

tHz

-DISTRIDISTR to Floating
Data Delay

100 pF Load
Note 3

tDOW

-DOSTRIDOSTR Strobe
Width

tWC

100

175

Write Cycle Delay

200

500

Write Cycle = lAW + tDOW
+tWC

360

755

100

tDS

Data Setup Time

tDH

Data Hold TIme

tCSC

Chip Select Output Delay
from Select

tRA

Address Hold Time from
-DISTRIDISTR

tRCS

Chip Select Hold TIme from
-DISTRIDISTR

IAR

-DISTRIDISTR Delay from
Address

tCSR

100pF Load

Note 2

-DISTRIDISTR Delay from
Chip Select

Note 2

tWA

Address Hold TIme from
-DOSTRIDOSTR

Note 2

tWCS

Chip Select Hold TIme from
-DOSTRIDOSTR

Note 2

lAW

-DOSTRIDOSTR Delay
from Address

Note 2

tCSW

-DOSTRIDOSTR Delay from
Select

Note 2

tMRW

Master Reset Pulse Width

JjS

tXH

Duration of Clock High Pulse

140

tXL

Duration of Clock Low Pulse

140

100

125

Notes: 1. All timings are referenced to valid 0 and valid 1. (See AC Test Points.)
2. Applicable only when -ADS is tied Low.
3. Charge and discharge time is determined by VOL, VOH and the external loading.
6-16

External Clock
(3.1 MHz Max)

•

VLSI TECHNOLOGY, INC.
VL16C450·VL82C50A·VL82C50
VL16C450

Symbol

Parameter

Min

Max

VL82CSOA
Min

Max

VL82C50
Min

Max

Units

Conditions

Transmitter
tHR1

Delay from Rising Edge of
-DOSTR/DOSTR (WR THR)
10 Reset Interrupt

175

1000

N/A

100 pF Load

IHR2

Delay from Falling Edge of
-DOSTR/DOSTR (WR THR)
to Reset Interrupt

N/A

1000

100 pF Load

tlRS

Delay from InitiallNTR
Reset Interrupt

-BAUDOUT
CYCLES

tSI

Delay from Initial Write to
Interrupt

-BAUDOUT
CYCLES

tSS

Delay from Stop to Next
Start

tSTI

tlR

100

Delay from Start Bit Low to
Interrupt (THRE) High

-BAUDOUT
CYCLES

Delay from -DISTRIDISTR
(RD IIR) to Reset Interrupt
(THRE)

250

1000

100 pF Load

Modem Control
tMDO

Delay from -DOSTR/DOSTR
(WR MCR) to Output

250

1000

100 pF Load

tSIM

Delay to Set Interrupt from
Modem Input

250

1000

100 pFLoad

tRIM

Delay to Reset Interrupt from
-DISTR/DISTR (RS MSR)

250

1000

100 pF Load

Baud Generator
1

216_1

Baud Divisor

tBLD

Baud Output Negative
Edge Delay

125

250

100 pF Load

tBHD

Baud Output Positive
Edge Delay

125

250

100 pF Load

tLW

Baud Output Down Time

425

fX = 2 MHz. +2.
100 pF Load

tHW

Baud Output Up Time

330

fX = 2 MHz. +2.
100 pF Load

Receiver
tSCD

Delay from RCLK to
Sample Time

j.IS

tSINT

Delay from Stop to Set
Interrupt

RCLK

100 pF Load

tRINT

Delay from -DISTRIDISTR
(RD RBRIRDLSR) to Reset
Interrupt

j.IS

100 pFLoad

Note: 1. All timings are referenced to valid

a and valid

1. (See AC Test Points.)

6-17

•

VLSI TECHNOLOGY, INC
VL 16C450 • VL82C50A • VL82C50

TIMING DIAGRAMS
READ CYCLE
-ADS

~--~ ~----------~~~M-.-------r------

A2. A1. AD

-CS2. CS1. CSO

_tRCSJ------t-------CSOUT

----_I4-----+----RC-------+_~
~_---tRC--~

-DISTRIDISTR
I~--------~(~~.

----------------+-----+-----------~.~

-DOSTRIDOSTR

DDIS

DATA
DO-D7

• Applicable only when -ADS is tied low.

BAUDOUT
XTAL1

tBLD....-.I
-BAUDOUT
(+1)

\4- .....j I+- tHW

U1J1J1J1JL
~ j4-tBHD

.....j r-tL~

~ j4-tBLD

!.-.ItLW

-BAUDOUT
(+2)

~ j4-tBHD
--l1-4-tBLo1
-BAUDOUT
(+3)
--l j4-tBLD1
-BAUD OUT
(+N, N>3)

HtHW

tBHD

f---I

tHWH-4-tLW--j

,tHW = (N - 2) XTAL1 CYCLES

-L...----....Ir~
6-18

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

nl.t~_____ 11

RECEIVER
RCLK

-1 ~

L--<

.1 14- tSCD

8CLKS

~M~E

CLK

~MPLE

~~~

I·

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

~~~~~L~--~~I~~I~=~~

r.'~

(DATA READY OR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
RCVRERR)
-DISTRIDISTR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,

(NO~~

(READREC
DATA BUFFER
ORRDLSR)

__________________

TRANSMITTER

SERIAL
OUT (SOUT)

S:L
~

DATA (5-8)

DsTOP
PARITY

IIRS

INTERRUPT
(THRE)

(1_2)fs~T_A~RLT------~

ISTI
_ _ _ _- ,

~-------

11::-"

(WRTHR)
-DOSTR/DOSTR
(NOTE 1)

tlR

-DISTR/DISTR
(RDIIR) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
(NOTE 2)

Notes: 1 See WRITE Timing ~iagram.
See READ Timing Diagram.

6-19

•

VLSI TECHNOLOG'l; INC. Vl16C450. Vl82C50A • Vl82C50

WRITE CYCLE
-ADS

A2., A1, AO

--=;'*------=---t-~;WA·

mcs~'----+---

-CS2, CS1, CSO

CSOUT

----~~--~~----r_-WC--------j-~
__~~-----tWC------~1

-DOSTRIDOSTR

'-----------tr----tR

- - - - f -____:::

-DISTRIDISTR

.~---

=¥ACTIVE

tDS 14----l~--~tDH
DATA
00-07

----------------------"1

VALID DATA

• Applicable only when -ADS·IS rIedlow.
MODEM CONTROLS
-DOSTRIDOSTR

I'MOO=f-r-

~ ~_( tMDO

(WR MCR)-.J
____________
-ATS, -DTR
-OUT1 , -OUT2

-CTS, -DSR, -DCD

INTERRUPT

--------

---------r----

-DISTRIDISTR
(RD MSR) ______________
(NOTE 2) _ _ _ _ _ _ _ _ _ _ _ _---,
-AI

" -_________

6-20

•

VLSI TECHNOLOGY, INC.
VL 16C4S0 • VL82CSOA • VL82CSO

AC TESTING INPUT/OUTPUT WAVEFORMS
EXTERNAL CLOCK INPUT (3.1 MHz MAXIMUM)

AC TEST POINTS

Note: All timings are referenced to valid 0 and valid 1.

TEST CIRCUIT

2.54 V

Device Under Test

6800

82 pF*
* Includes Scope and Jig
Capacitance

BASIC CONFIGURATION
VL16C450.VL82C50A.VL82C50
TYPICAL COMPONENT VALUES

CPU

BUS

-MEMW OR -IIOW
INTR
RESET
AO
A1

RX2

3.072 MHz

1 Mn

l.SKn

10-30pF

40-90pF

1.843MHz

1 Mn

1.SKn

10-lSpF

6S-100pF

Crystal

$OUT
-MEMR OR -IIOR

EIA
DRIVERS

-OISTR
-OOSTR
INTRPT
MR

TO RS232
INTERFACE

VL 16C450 (-ALSO)
VLB2C50A
-OCO
VLB2C50

AO
A1

A2
-ADS

XTAL1

DOSTR
0

DlSTR

-CS2

c::J

XTAL2
RX2

CS1

csa
C2I

6-21

-_.

- -

IC1

•

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature
Storage Temperature

-65·C to + 150·C

Supply Voltage to
Ground Potential -0.5 V to VCC +0.3 V
Applied Output
Voltage

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

-1 O·C to +70·C

-0.5 V to VCC +0.3 V

Applied Input
Voltage

-0.5 V to +7.0 V

Power Dissipation

500mV

DC CHARACTERISTICS: TA = o·c to +70·C, VCC = S V ±S%
VL16C4S0

VL82CSOA

VL82CSO

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Units

VILX

Clock Input Low Voltage

-0.5

0.8

-0.5

0.8

-0.5

0.8

VIHX

Clock Input High Voltage

2.0

VCC

2.0

VCC

2.0

VCC

VIL

Input Low Voltage

-0.5

0.8

-0.5

0.8

-0.5

0.8

VIH

Input High Voltage

2.0

VCC

2.0

VCC

2.0

VCC

VOL

Output Low Voltage

0.4

VOH

Output High Voltage

ICC
(Ave)

Average Power Supply
Current (VCC)

ilL
ICL

0.4
2.4

2.4

10L 1.6 mAon All
IOH =-1.0 mA
VCC = 5.25 V, No
Loads on SIN, -DSR
-RLSD, -CTS, -DCD.
-RI • 2.0 V. All Other
Inputs = 0.8 V. Baud
Rate Generator at
4 MHz. Baud Rate at
56K.

Input Leakage

±10

I1A

VCC=5.25 V
VSS=OV
All ~her Pins Floating

Clock Leakage

±10

:110

I1A

VIN = 0 V, 5.25 V
VCC=5.25 V
VSS =0 V
VOUT = 0 V, 5.25 V
Chip Deselected
2 Chip and Write
Mode selected

10Z

Three-State Leakage

±20

I1A

VILMR

MR Schmitt VIL

0.8

VIHMR

MR Schmitt VIH

2.0

CAPACITANCE
Symbol

Conditions

Parameter

Input Capacitance

CIO

110 Capacitance

COC

Output Capacitance

Min.

Max.

Units

Crystal

All Others

Crystal

All Other

pF
6-22

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 8
PARALLEL/ASYNCHRONOUS
COMMUNICATIONS ELEMENT

FEATURES
Programmable serial interface
characteristics;
- 5-, 6-, 7- or S-bit characters
- Even-, odd- or no-parity bit
generation and detection
- 1, 1 112 or 2 stop bit generation

• IBM PC/AT-<:ampatible and National
NS 16450-compatible
VL16C450 with on-board Centronics
printer interface
• VL 16C451 B is completely pin- and
upward-<:ampatible with the Dual
Serial Channel VL 16C451
Direct drive of interrupt request
signals on slot-bus
• Enhanced bidirectional parallel data
port (VL16C451 B only)
Crystal and oscillator clock inputs
(VL16C451 B only)
• General purpose input/output port
(VL16C451 B only)
• Three-state control pin and in-circuittest feature for board level testability
(VL16C451 B only)

information obtained includes the type
and condition of the transfer operation
being performed, and error conditions.
It is fully pin- and upward-compatible
with the dual serial channel VL 16C4521
VL16C452B.

• Three-state TIL drive for the data
and control bus

DESCRIPTION
The VL 16C451 B is an enhanced version
of the popular VL 16C450 asynchronous
communications element (ACE). The
serial channel performs serial-to-parallel
conversion on data characters received
from peripheral devices or modems, and
parallel-to-serial conversion on data
characters transmitted by the CPU. The
complete status of the ParalieVAsynchronous Communications Element
(PlACE) can be read at any time during
functional operation by the CPU. The

The VL 16C451 B also provides the user
with a fully bidirectional parallel data
port that fully supports the parallel
Centronics interface. The parallel port,
together with the serial port, provide
IBM PC/AT-compatible computers with
a single device to serve the two system
ports.
A programmable baud rate generator is
included that can divide the timing
reference clock input by a divisor
between 1 and (216 -1).
The VL16C451NL16C451B is housed
in a 6S-pin plastic leaded chip carrier.

BLOCK DIAGRAM

PIN DIAGRAM
VL16C451/VL16C451 B

-CTS
-DSR

-RTS
-OrR

sour

-AI
(-Rl.SD) -DCD

VL16C150

lIAR!

SIN
-GSO
(NC)

·ICTAL.
·ICTA12 - - - - I
DBO-DB7 --:1--r"L--......J

(NCI
-ouT2
INT>

-EMODEA
(NC)

-EMOOEB
(NC)

INIl)
-OlIT2"

.....IN

GPl04
(NC)
GPOUT5

PQO.P07

POl

PD4

-IllS

POS
POS
PD7

-DTR

INTO

BOUT

BOO

VQDR

GPINO"
GPIN'·
GPIN2"

GPI03"
GPI04·

-€MODEA· - - + - - \
-€MODE.. - - + - I

GI'OUT5.
GPOUT6"
GPOUT7"

(NC)

M-KJ.

ORDER INFORMATION
Part
Maximum
Number
Clock Frequency

---=;,.<..j

-iCNI---i
-IOR---i
-RES---i

CHIP
SELECT

AND

TESTING
LOGIC

T R I · - - - L_ _......J

Package

VL16C451-QC

3.1 MHz

Plastic Leaded Chip Carrier (PLCC)

• VL 16C451 B only
VL 16C451 pin names are in parenthesis.

VL 16C451 B-QC

SMHz

Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is
O·C to +70·C.

6-23

VLSI TECHNOLOGY, INC.
VL 16C451 NL 16C451 B
SIGNAL DESCRIPTIONS (VL16C451 signal names are shown in parenthesis.)
Signal
Name

Pin
Number

Signal
Type

Signal
Description

-RTS

Request To Send output (three·state, active low)· This signal is asserted
to indicate the UART is ready to transmit data to an external modem. In
haH duplex applications the -RTS line is used to control the transmission
direction. The signal is negated on reset.

-DTR

Data Terminal Ready output (three-state, active low) - This signal is
asserted to indicate the UART is ready to receive data. The signal is
negated on reset.

SOUT

Serial Output (three-state, active low) - SOUT is the data output of the
UART. This signal is negated whenever the transmitter is disabled, -RES
is active, the Transmitter Register is empty, or the UART is in Loop Mode.

-CTS

Clear To Send input (active low) - This signal is a status line from the
external modem to indicate that it is ready to transmit data. A change is
status of this line sets the Delta CTS bit in the Modem Status Register.

-DSR

Data Set Ready input (active low) - -DSR is a status line indicating that the
external modem is ready to transfer data tolfrom the UART. A change in
status of this line sets the. Delta DSR bit in the Modem Status Register.

-DCD (-RLSD)

Data Carrier Detect input (active low) - This signal is used to indicate that
the external modem has detected a carrier. H the -RI line changes state
while the modem status interrupts are enabled, an interrupt will be generated.

-RI

Ring Indicator input (active low) - This signal is used to indicate that the
telephone ring signal has been detected by an external modem. The
modem status register TERI bit is used to indicate that a Trailing Edge of
the Ring Indicator has been detected. If modem status interrupts are
enabled when this occurs, an interrupt will be generated.

SIN

Serial Input (active low) - This is the data input to the UART. This input is
ignored when Loop Mode is enabled.

INTO

Gated Interrupt Request (three-state, active high output) - This signal is
asserted whenever the UART attempts to generate an interrupt. This
signal is negated upon an interrupt being serviced. This signal is enabled!
three-stated by setting the Interrupt Enable (bit 3) signal in the Modem
Control Register. This signal is suitable for directly driving the SIRQ signal
on the slot-bus of the PC!AT.

-eSO

Chip Select input (active low) - -eSO is used to indicate that an access is
being made to the UART registers.

-OUT2(NC)

Output - User defined output for modem control logic that can be set to an
active low by programming bit 3 of the Modem Control Register to a high
level. This signal is cleared (high) by writing a logic 0 to the -OUT2 bit
(MCR) or whenever a reset occurs. In PC!AT or PS/2 applications, this
signal normally indicates that the SIO interrupts have been enabled for
system level interrupts.

105

Printer data port bit 0 - These signals, PDO-PD7 provide a bidirectional
eight-bit VO port usually connected to a printer. These lines are driven
when the PEMD signal is negated (low) or whEIn PEMD is asserted and the
direction control bit is set to 0 (write).

PARALLEL PRINTER PORT:
PDO
53

PD1

105

Printer data port bit 1.

PD2

105

Printer data port bit 2.

6-24

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C4518

SIGNAL DESCRIPTIONS (Cont_)
Signal
Name

Pin
Number

Signal

Type

Signal
Description

P03

105

Printer data port bit 3.

P04

105

Printer data port bit 4.

P05

105

Printer data port bit 5.

P06

105

Printer data port bit 6.

P07

105

Printer data port bit 7.

-INIT

Printer Command Initialize - This is an active low, open drain signal that is used
to issue an initialize command to the printer.

-AFO

Printer Command Autofeed - This is an active low, open drain signal that is
used to issue an autofeed command to the printer.

-8TB

Printer Command Data Strobe - This is an active low, open drain signal that is
used to latch the parallel data into the printer.

-SLIN

Printer Command Select - This is an active low, open drain signal that is used
to issue a select command to the printer.

-ERR

Printer Status Error input - This signal is used to monitor the printer for error
reporting. This pin will float high with no input connected.

SLCT

Printer Status Select input - SLCT is used to indicate when the printer is on-line
(selected). This pin will float high with no input connected.

BUSY

Printer Status Busy input - BUSY is used to indicate when the printer is busy
and cannot receive data. This pin will float high with no input connected.

Printer Status Paper Empty input - PE is used to indicate that·the printer is out
of paper. This pin will float high with no input connected.

-ACK

Printer Status ACK input - This signal is used as a handshake signal from the
printer indicating the last transaction has completed. An interrupt is generated
by a low-to-high transition on this signal. This pin will float high with no input
connected.

INT2

Printer Interrupt Request (three-state, active high output) - This signal is
asserted whenever the -ACK signal is asserted. This signal is enabledlthreestated by setting the Interrupt Enable (bit 4) signal in the Printer Control
Register. This signal is suitable for directly driving the INT2 signal on the slotbus of the PC/AT. This pin is also used during Test Mode. (See the description of the TEST signal below.)

PEMO

Printer Enhancement Mode - When asserted (high) this signal enables the
bidirectional printer port capabilities. When negated (low) the printer port is
output only (PC/AT-compatible).

(-LPTOE)

(VL16C451 only) Parallel Data Output Enable - When low, this signal enables
the Write Data Register to the POQ-P07 lines. A high puts the POQ-P07 lines in
the high-impedance state allowing them to be used as inputs. -LPTOE is
usually tied low for printer operation.

-CS2

Parallel Port Select input - -CS2 is used to indicate that an access is being
directed to the printer port registers.

-EN IRQ (NC)

Parallel Port Interrupt Source Mode Selection - When negated (low), the AT
mode of interrupts is selected. In this mode, the -ACK input is internally
connected to the INT2 output. H the -EN IRQ input is tied high, the interrupt
source will be held in a latched state until the Status Register is read which will
then reset the INT2 output.

6-25

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

SIGNAL DESCRIPTIONS (Cont.)
Signal
Type

Signal
Description

COMMON CONTROL SIGNALS:
-lOR
37

va Read Strobe input (active-low) is used to drive data from the
VL160451 B to the data bus (OBO-OB7). The output data depends on the
register selected by the address inputs AO, A1, A2 and the Chip Selects
(CSO for the UART, and CS2 for the Printer Port).

-lOW

va Write Strobe input (active low) - This signal is used to latch data into the
VL160451 B from the data bus (OBO-OB7). The input data depends on the
register selected by the address inputs AO, A1, A2 and the Chip Selects
(CSO for the UART, and CS2 for the Printer Port).

OBO

106

Oata I/O Bits 0-7 (three-state, active high) - These are lines used to
interface to the slot bus. These signals are normally high impedance
except during read cycles. Oata bit 0 is the least significant bit.

OB1

106

Oata I/O signal.

OB2

106

Oata I/O signal.

OB3

106

Oata I/O signal.

OB4

106

Oata I/O signal.

OB5

106

Oata I/O signal.

OB6

106

Data I/O signal.

Signal
Name

Pin
Number

OB7

107

Data I/O signal (MSB).

Address line inputs - AO-A2 are used to decode which register is selected
during CPU accesses to the VL 160451 B.

Address line input.

XTAL1 (CLK)

Crystal Input 1 or External Clock input - This is used for the UART baud
rate generator.

XTAL2 (NC)

Crystal Input 2 - XTAL2 may be tied to VCC, GNO or left open if an
external clock source is tied to XTAL1.

-RES
(-RESET)

Reset input (active low) - This signal is used to force the VL 16C451 B into
an idle state with all serial transfers suspended. The Modem Control
Register and Line Status Register are both initialized.

BOO (NC)

Bus Drive Output (three-state, active high) - BOO is used to indicate to
external octal transceivers that the VL160451 B is driving the data pins. It
can be directly connected to the direction pin of a 74LS245.

-EMOOEA
(NC)

Enhanced Mode Select A - This input signal is used in conjunction with the
-EMOOEB signal to configure the General Purpose VO port. The GPIO
port can be configured as follows:

GPI04

GPINOGPIN2

GPI03

EMODE

OUT

6-26

GPOUTSGPOUT7

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name
-EMODEB
(NC)

Pin
Number

Signal
Type

Signal
Description

Enhanced Mode Select B input.

GENERAL PURPOSE 110 PORT:
GPINO (NC)

General Purpose Input Port Bit 0 (LSB) - This signal if enabled as an input
via the -EMODEA and -EMODEB configuration inputs can be read at bit 0
of the General Purpose 110 (PGIO) Port Register. It can be tied to GND,
VCC or left open if not used. This pin will float high with no input connected.

GPIN1 (NC)

General Purpose Input Port Bit 1 - Read at bit 1 GPIO Port Register if
enabled.

GPIN2 (GND)

General Purpose Input Port Bit 2 - Read at bit 2 GPIO Port Register if
enabled.

GPI03(NC)

105

General Purpose InpuVOutput Port Bit 3 - This signal can be configured to
be an input or an output control bit via the -EMODEA and -EMODEB
configuration inputs. If the signal is configured as an output it is initially
reset to a 0 (low) state when -RES is asserted. It can be set high by
programming bit 3 of the GPIO Port Register to a 1. It will be set low by
programming bit 3 to a o. H configured as an input, it can be read at bit 3 of
the GPIO Port. H the bit is changed from an output port to an input port
and then subsequently back to an output port, its initial state will always be
reset to a logical 0 (low).

GPI04 (NC)

105

General Purpose InpuVOutput Port Bit 4 - Set or read at bit 4 of the GPIO
Port.

GPOUT5 (NC) 13

General Purpose Output Port Bit 5 - This signal is configured as an output
control bit via the -EMODEA and -EMODEB configuration inputs. H the
signal is configured as an output it is initially reset to a 0 (low) state when
-RES is asserted. It can be set high by programming bit 5 of the GPIO
Port Register to a 1. It will be set low by programming bit 5 to a O.

GPOUT6 (GND)

04
General Purpose Output Port Bit 6 - This bit is set or cleared by
writing bit 5 of the GPIO Port Register.

GPOUT7 (NC) 62

General Purpose Output Port Bit 7 (MSB) - This bit is set or cleared by
writing bit 7 of the GPIO Port Register.

POWER BUSSING:
The power connections to the VL16C451 B are split into an internal supply for the logic, and a ring supply for the 110 drivers. Each
supply should be individually bypassed with decoupling capacitors.
VDDR

23,64

VDDI

Ring Power Supply - +5 V
Internal Power Supply - +5 V

GNDR

22,42,61

Ring Ground

GNDI

9,27

Internal Ground

TEST MODE PINS:
The three test modes which are supported by the VL 16C451 Bare:
Component

The Component Test Mode is selected when -lOW and -lOR are simultaneously taken low when DBO is low,
DB1 is high and TRI is high. The mode is used to put the VL16C451B into a component level test mode.

In-Circuit

The In-circuit Test Mode is selected when -lOW and -lOR are simultaneously taken low when DB1 is low, DBO
is high and TRI is high. This mode is normally used to confirm that the VL16C451 B has been physically attached to the printed circuit board.
6-27

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL 16C451 8

SIGNAL DESCRIPTIONS (Cont.)
Three-State

The Three-state Test Mode is entered when the TRI input is taken high. This mode is used to control the threestate control of all I/O and output pins. When this mode is selected, all
and outputs become high impedance,
allowing board level testers to drive the outputs without overdriving internal buffers.

Each of these test modes are selected by driving a combination of pins into the desired mode.
Signal
Name

Pin
Number

Signal
Type

Signal
Description

TRI (GND)

This pin is used to control the three-state control of all I/O and output pins.
When this pin is asserted, all
and outputs become high impedance,
allowing board level testers to drive the outputs without overdriving internal
buffers. This pin is level sensitive. This pin is pulled down with an internal
resistor that is approximately 5 kn, and is a CMOS input.

IN·CIRCUIT·TEST DESCRIPTION:
During In-circuit-test (ICT) all of the inputs except TRI and -RES can toggle one or more outputs. This allows for a board level
tester to test the solder connections for each signal pin.

The sequence for enabling ICT is as follows:
1. Tester drives TRI signal to 1.
2. Tester drives DBO to DBl and DB1-0.
3. Tester pulses -lOR and -lOW low for 100 ns (minimum).
4. Tester drives TRI signal to 0 (outputs now enabled).
5. VL 16C451 B is now in ICT mode.
The
1.
2.
3.
4.
5.

sequence for disabling ICT is either assertion of the -RES signal or the sequence as follows:
Tester drives TRI signal to 1.
Tester drives both DBO and DBl to 1 or both to O.
Tester pulses -lOR and -lOW low for 100 ns (minimum).
Tester drives TRI signal to 0 (outputs now enabled).
VL16C451 B is now out of ICT mode.

Functionally ICT can be entered and exited as shown in Figure 1.

FIGURE 1.

TRI

100 NS MIN

-lOR
-lOW
DBO
DBl
ICTMODESET
Note:

ICT MODE RESET

ICT Mode is set by an illegal combination of -lOR, -lOW, DBl and DBO, while TRI is asserted. ICT Mode can be reset
by either the -RES pin or the same combination but with DBO and DB 1 set = 0 or 1.

6-28

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

TABLE 1. PIN MAPPING FROM INPUT TO OUTPUT (VL16C451 B ONLY)
INPUT

OUTPUT

Signal

Type

Signal

Type

-PEMD

GPI03

110

GPINO

GPI04

I/O

GPIN1

GPOUT5

GPIN2

-RTS

-EMODEA

-DTR

-EMODEB

SOUT

-CS2

GPOUT6

-CTS

BDO

-DCD

INTO

-RI

21
46

DB7
PD7

I/O
I/O

-DSR

20
47

DB6
PD6

110
I/O

-CSO

19
48

DB5
PD5

I/O
I/O

18
49

DB4
PD4

110
I/O

17
50

DB3
PD3

I/O
110

16
51

DB2
PD2

I/O
I/O

-lOW

15
52

DB1
PD1

110
110

-lOR

14
53

DBO
PDO

I/O
I/O

SIN

-STB

-ENIRQ

-AFD

-ERR

-IN IT

SLCT

-SUN

BUSY

INT2

-OUT2

-ACK

GPOUT7

6-29

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

TABLE 2. PINS NOT MAPPED (VL16C451B ONLy)
Signal

Type

TRI

GNOI

GND

GNOR

GND

VOOR

PWR

GNOI

GNO

-RES

VDOI

PWR

GNOR

GNO

GNDR

GND

VDOR

PWR

1/0 LEGEND

(0 = Output, I = Input, 10 = InputlOutput)

No.

rnA

Type

01
02
03
04
05
06
07
11
12
13
14
101
102
103
104
105
106

10
24
10
12
10
24
2

TTL
TTL
TTL-OO
TTL-OOP
TTL-TS
TTL-TS
TTL-TS
TTL
CMOS
TTL
CMOS
TTL-TS
TTL-TS
TTL-OO
TTL-OD
TTL-TSP
TTL-TS

10
24
10
24
12
4

Comments

Open Drain (collector)
Open Drain with Three kn Pull-up
Three-state
Th ree-state
Three-state

With 20 kQ Pull-up Resistor
With 1 kn Pull-down Resistor
Bidirectional, Three-state
Bidirectional, Three-state
Bidirectional, Open Drain
Bidirectional, Open Drain
Bidirectional, Three-state
Bidirectional, Three-state

6-30

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

FUNCTIONAL DESCRIPTION
SERIAL CHANNEL REGISTERS
Three types of internal registers are
used in the serial channel of the
VL 16C451 B. They are used in the
operation of the device, and are the
control, status, and data registers. The
control registers are the Baud Rate
Select Register DLL (Divisor Latch
LSB) and DLM (Divisor Latch MSB),
Line Control Register, Interrupt Enable
Register, and the Modem Control
registers, while the status registers are
the Line Status Registers and the
Modem Status Register. The data
registers are the Receiver Buffer
Register and the Transmitter Holding
Register. The Address, Read, and
Write inputs are used in conjunction
with the Divisor Latch Access Bit in the
Line Control Register [LCR(7)] to select
the register to be written or read (see
Table 3). Individual bits within these
registers are referred to by the register
mnemonic and the bit number in
parenthesis. An example, LCR(7)
refers to Line Control Register Bit 7.
The Transmitter Buffer Register and
Receiver Buffer Register are data
registers holding from five to eight bits
of data. H less than eight data bits are
transmitted, data is right justified to the

LSB. Bit 0 of a data word is always the
first serial data bit received and
transmitted. The VL16C451B data
registers are double-buffered so that
read and write operations can be
performed at the same time the ACE is
performing the parallel-to-serial and
serial-to-parallel conversion.
LINE CONTROL REGISTER
The format of the data character is controlled by the Line Control Register.
The contents of the LCR may be read,
eliminating the need for separate
storage of the line characteristics in
system memory. The contents of the
LCR are described in Figure 2.
LCR (0) and LCR(l) word length select
bit 1: The number of bits in each serial
character is programmed as shown in
Figure 2.
LCR(2) Stop Bit Select: LCR(2)
specifies the number of stop bits in each
transmitted character. If LCR(2) is a
logic 0, one stop bit is generated in the
transmitted data. If LCR(2) is a logic 1
when a S-bit word length is selected, 1.S
stop bits are generated. HLCR(2) is a
logic 1 when either a 6-, 7-, or a-bit word
length is selected, two stop bits are
generated. The receiver checks for one
stop bit.

TABLE 3. SERIAL CHANNEL INTERNAL REGISTERS
DLAB

Mnemonic

RBR

Receiver Buffer Register (read only)

THR

Transmitter Holding Register (write only)
Interrupt Enable Register

IER

IIR

Interrupt Identification Register (read only

LCR

Line Control Register

MCR

Modem Control Register

LSR

Line Status Register

MSR

Modem Status Register

SCR

Scratch Register

DLL

Divisor Latch (LSB)

DLM

Divisor Latch (MSB)

X = "Don't Care"

0= Logic Low

1 = Logic High

Note: The serial channel is accessed when -eSO is low.
6-31

LCR(3) Parity Enable: When LCR(3) is
high, a parity bit between the last data
word bit and stop bit is generated and
checked.
LCR(4) Even Parity Select: When
parity is enabled [LCR(3)=1], LCR(4)=0
selects odd parity, and LCR(4)Rl
selects even parity.
LCR(S) Stick Parity: When parity is
enabled [LCR(3)=1], LCR(S)=l causes
the transmission and reception of a
parity bit to be in the opposite state from
the value of LCR(4). This allows the
user to force parity to a known state and
for the receiver to check the parity bit in
a known state.
LCR(6) Break Control: When LCR(6) is
set to a logic "1", the serial output
(SOUT) is forced to the spacing (logic
0) state. The break is disabled by
setting LCR(6) to a logic "0". The Break
Control bit acts only on SOUT and has
no effect on the transmitter logic. If the
following sequence is used, no erroneous or extraneous characters will be
transmitted because of the break.
1. Load an all nons pad character in
response to THRi::.
2. Set break in response to the
nextTHRE.
3. Wait for the transmitter to be
idle (TEMT= 1), and clear
break when normal transmission has to be restored.

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

FIGURE 2. LINE CONTROL REGISTER

IL~R IL~R IL~R IL~R I IL~R IL~R IL~R I
L;R

Word
Length
Select

o
o

0
5 Data Bits
6 Data Bits
1
10= 7 Data Bits
1 1
8 Data Bits

Stop
o = 1 Stop Bit
Bit Select 1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected
Parity
o = Parity Disabled
Enable
1 = Parity Enabled

Even
Parity
Select

Stick
Parity

Break
Control

Divisor
Latch
Access

Odd Parity
1 = Even Parity

Stick Parity Disabled
1 = Stick Parity Enabled
Break Disabled
1 = Break Enabled
Access Receiver Buffer
1 = Access Divisor Latches

Bit

LCR(7) Divisor Latch Access Bit
(DLAB): LCR(7) must be set high (logic
"I") to access the Divisor Latches DLL
and DLM of the Baud Rate Generator
during a read or write operation.
LCR(7) must be input low to access the
Receiver Buffer, the Transmitter
Holding, or the Interrupt Enable
Registers.

LINE STATUS REGISTER
The Line Status Register (LSR) is a
single register that provides status
indications.
The contents of the Line Status
Register shown in Table4 are described
below:
LSR(O) Data Ready (DR): Data Ready
is set high when an incoming character
has been received and transferred into
the Receiver Buffer Register. LSR(O) is
reset low by a CPU read of the data in
transferred into the Receiver Buffer
Register.
LSR(1) Overrun Error (OE): Overrun
Error indicates that data in the Receiver

Buffer Register was not read by the
CPU before the next character was
transferred into the Receiver Buffer
Register, overwriting the previous
character. The OE indicator is reset
whenever the CPU reads the contents
of the Line Status Reg ister.
LSR(2) Parity Error (PE): Parity Error
indicates that the received data
character does not have the correct
even or odd parity, as selected by the
Even Parity Select bit (LCR(4). The PE
bit is set high upon detection of a parity
error, and is reset low when the CPU
reads the contents of the LSR.
LSR(3) Framing Error (FE): Framing
Error indicates that the received
character did not have a valid stop bit.
LSR(3) is set high when the stop bit
following the last data bit or parity bit is
detected as a zero bit (spacing level).
The FE indicator is reset low when the
CPU reads the contents of the LSR.
LSR(4) Break Interrupt (BI): Break
Interrupt is set high when the received

6-32

data input is held in the spacing (logic
0) state for longer than a full word
transmission time (start bit + data bits +
parity + stop bits). The BI indicator is
reset when the CPU reads the contents
of the Line Status Register.
LSR(1) - LSR(4) are the error conditions
that produce a Receiver Line Status
interrupt (priority 1 interrupt in the
Interrupt identification Register (UR»
when any of the conditions are detected. This interrupt is enabled by
setting IER(2)=1 in the Interrupt Enable
Register.
LSR(5) Transmitter Holding Register
Empty (THRE): THRE shows that the
serial channel is ready to accept a new
character for transmission. The THRE
bit is set high when a character is
transferred from the Transmitter Holding
Register into the Transmitter Shift
Register. LSR(5) is reset low by the
loading of the Transmitter Holding
Register by the CPU. LSR(5) is not
reset by a CPU read of the LSR.

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C4518

TABLE 4. LINE STATUS REGISTER BITS
0

LSRBITS
LSR (0) Data Ready (DR)

Ready

Not Ready

LSR (1) Overrun Error (OE)

Error

No Error

LSR (2) Parity Error (PE)

Error

No Error

LSR (3) Framing Error (FE)

Error

No Error

LSR (4) Break Interrupt (BI)

Break

No Break

LSR (5) Transmitter Holding Register Empty (THRE)

Empty

Not Empty

LSR (6) Transmitter Empty (TEMT)

Empty

Not Empty

LSR (7) Not Used
When the THRE interrupt is enabled
[IER(1 )=1]. THRE causes a priority 3
interrupt in the fiR. If THRE is the
interrupt source indicated in IIR,
INTRPT is cleared by a read of the IIR.
LSR(6) Transmitter Empty (TEMT):
TEMT is set high when the Transmitter
Holding Register (THR) and the
Transmitter Shift Register (TSR) are
both empty. LSR(6) is reset low when a
character is loaded into the THR and
remains low until the character is
transferred out of SOUTo TEMT is not
reset low by a CPU read of the LSR.
LSR(7): This bit is always O.
Note: The Line Status Register may be
written. However, this function is
intended only for factory test. It should
be considered READ ONLY by applications software.
MODEM CONTROL REGISTER
The Modem Control Register (MCR)
controls the interface with the modem
or data set as described in Figure 3.
The MCR can be written and read. The
-RTS and -OTR outputs are directly
controlled by their control bits in this
register. A high input asserts a low
(true) at the output pins. MCR Bits 0, 1,
3, and 4 are shown below:
MCR(O): When MCR(O) is set high, the
-OTR output is forced low. When
MCR(O) is reset low, the --OTR output is
forced high. The -OTR output of the
serial channel may be input into an
inverting line driver in order to obtain
the proper polarity input at the modem
or data set.
MCR(1): When MCR(1) is set high, the
-RTS output is forced low. When

MCR(1) is reset low, the -HTS output is
forced high. The -RTS output of the
serial channel may be input into an
inverting line driver in order to obtain
the proper polarity input at the modem
or data set.
MCR(3): When MCR(3) is set high, the
INT output is enabled.
MCR(4): MCR(4) provides a local
Ioopback feature for diagnostic testing
of the channel. When MCR(4) is set
high, Serial Output (SOUT) is set to the
marking (logic "1") state, and the
receiver data input Serial Input (SIN) is
disconnected. The output of the
Transmitter Shift Register is looped
back into the Receiver Shift Register
input. The three modem control inputs
(-CTS, -OSR, -OCO (-RLSO) and -RI)
are disconnected. The modem control
outputs
(-OTR, OUT2 and -RTS) are internally
connected to -CTS, -OCO (-RLSO)
and -OSR. -RI is connected to
-MCR(2). The modem control output
pins are forced to their inactive state
(high). In the diagnostic mode, data
transmitted is immediately received.

This allows the processor to verify the
transmit and receive data paths of the
selected serial channel.
. Bits MCR(5) - MCR(7) are permanently
set to logic O.
MODEM STATUS REGISTER
The MSR provides the CPU with status
of the modem input lines from the
modem or peripheral devices. The
MSR allows the CPU to read the serial
channel modem signal inputs by
accessing the data bus interface of the
VL 16C451 B. In addition to the current
status information, four bits of the MSR
indicate whether the modem inputs
have changed since the last reading of
the MSR. The delta status bits are set
high when a control input from the
modem changes state, and reset low
when the CPU reads the MSR.
The modem input lines for the channel
are -CTS, -DSR, -RI, and -DCO
(-RLSO). MSR(4) - MSR(7) are status
indications of these lines. A status
bit=1 indicates the associated signal is
low, a bit=o indicates a high. Hthe
modem status interrupt in the Interrupt
Enable Register is enabled [IER(3)], an
interrupt is generated whenever MSR(O)
is set to a one. The MSR is a priority 4
interrupt. The contents of the Modem
Status Register are described in Table

3.
MSR(O) Delta Clear to Send (OCTS):
OCTS indicates that the -CTS input to
the serial channel has changed state
since the last time it was read by the
CPU.
MSR(1) Delta Data Set Ready (ODSR):
DOSR indicates that the --OSR input to
the serial channel has changed state
since the last time it was read by the
CPU.

TABLE 5. MODEM STATUS REGISTER BITS
MSRBit
MSR(O)
MSR(1)
MSR(2)
MSR(3)
MSR(4)
MSR(5)
MSR(6)
MSR(7)

Mnemonic
OCTS
ODSR
TERI
DDCD
CTS
DSR
RI
-DCD

6-33

Description
Delta Clear to Send
Delta Data Set Ready
Trailing Edge of Ring Indicator
Delta Data Carrierl Detect
Clear To Send
Data Set Ready
Ring Indicator
Data Carrier Detect

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C4518

FIGURE 3. MODEM CONTROL REGISTER
Modem Control Register (MCR)

Data
. 0 = -DTR Output High (Inactive)
Terminal 1 = -DTR Output Low (Active)
Ready
'--_ _~ Request
To Send
'-----~NC

'------------~ INT

'----------------. . LOOP

0 = -RTS Output High (Inactive)
1 = -RTS Output Low (Active)

Not Connected

INT Disabled
1 - INT Enabled

o=
1 =

LOOP Disabled
LOOP Enabled

' - - - - - - - - - - - - - -. . These Bits are Permanently Set to Logic "0".
MSR(2) Trailing Edge of Ring Indicator
(TERI): TERI indicates that the -AI
input to the serial channel has changed
state from low to high since the last time
it was read by the CPU. High to low
transitions on -RI do not activate TERI.
MSR(3) Delta Data Carrier Detect
(DDCD): DDCD indicates that the
-DCD input to the serial channel has
changed state since the last time it was
read by the CPU.
MSR(4) Clear to Send (CTS): Clear to
Send (CTS) is the complement of the
-CTS input from the modem indicating
to the serial channel that the modem is
ready to receive. data from the serial
channel's transmitter output (SOUT). If
the serial channel is in Loop Mode
[MCR(4)=1], this bit reflects the value of
-RTS in the MCR.
MSR(5) Data Set Ready (DSR): Data
Set Ready (DSR) is the complement of
the -DSR input from the modem to the
serial channel which indicates that the
modem is ready to provide received
data to the serial channel receiver
circuitry. I! the channel is in the Loop
Mode [MCR(4)=I], this bit reflects the
value of -DTR in the MCR.
MSR(6) Ring Indicator: Is the complement of the RI input (pin 39). If the
channel is in the Loop Mode
[MCR(4)=1], this bit reflects the state of
MCR(2).

MSR(7) Data Carrier Detect/Receive
Line Signal Detect: Data Carrier
Detect indicates the status of the Data
Carrier Detect (-DCD) input. If the
channel is in the Loop Mode
[MCR(4)=1], this bit reflects the state of
INTO of the MCR.
The modem status inputs (-RI, -DCD
(-RLSD), -DSR, and ~TS) reflect the
modem input lines with any change of
status. Reading the MSR register will
clear the delta modem status indications but has no effect on the other
status bits.
For LSR and MSR, the setting of status
bits is inhibited during status register
read operations. If a status condition is
generated during a read operation, the
status bit is not set until the trailing edge
of-lOR.

I! a status bit is set during a read
operation, and the same status condition occurs, that status bit will be
cleared at the trailing edge of -lOR
instead of being set again.
Note: In Loop Back Mode, when
Modem Status interrupts are enabled,
the ~TS, -DSR, -RI and -DCD input
pins are ignored. However, a Modem
Status interrupt may still be generated
by writing to MSR7-MSR4. This is
considered a test mode only. Applications software should not write to the
Modem Status Register.

6-34

DIVISOR LATCHES
The V116C451 B serial channel
contains a programmable Baud Rate
Generator (BRG) that divides the clock
(DC to 3.1 MHz) by any divisor from 1
to 2 16-1 (see also BRG description).
The output frequency of the Baud
Generator is 16X the data rate [divisor #
- clock + (baud rate x 16)]. Two 8-bit
divisor latch registers store the divisor in
a 16-bit binary format. These Divisor
Latch registers must be loaded during
initialization. Upon loading either of the
Divisor latches, a 16-bit baud counter is
immediately loaded. This prevents long
counts on initial load.
RECEIVE BUFFER REGISTER
The receiver circuitry in the serial
channel of the VL 16C451 B is programmable for 5, 6, 7, or 8 data bits per
character. For words of less than 8 bits,
the data is right justified to the least
significant bit LSB = Data Bit 0
[RBR(O)]. Data Bit 0 of a data word
[RBR(O)] is the first data bit received.
The unused bits in a character less than
8 bits O's.
Received data at the SIN input pin is
shifted into the Receiver Shift Register
by the 16X ciock provided at the RCLK
input. This clock is synchronized to the
incoming data based on the position of
the start bit. When a complete character is shifted into the Receiver Shift
Register, the assembled data bits are

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

parallel loaded into the Receiver Buffer
Register. The DR flag in the LSR
register is set.
Double buffering of the received data
permits continuous reception of data
without losing received data. While the
Receiver Shift Register is shifting a new
character into the serial channel, the
Receiver Buffer Register is holding a
previously received character for the
CPU to read. Failure to read the data in
the RBR before complete reception of
the next character result in the loss of
the data in the Receiver Register. The
OE flag in the LSR register indicates
the overrun condition.
TRANSMITTER HOLDING REGISTER
The Transmitter Holding Register (THR)
holds the character until the Transmitter
Shift Register is empty and ready toaccept a new character. The transmitter and receiver word lengths are the
same. Hthe character is less than eight
bits, unused bits are ignored by the
transmitter.
Data Bit 0 [THR(O)) is the first serial
data bit transmitted. The THRE flag
[LSR(5)j reflect the status of the THR.
The TEMT flag [LSR(5)] indicates if
both the THR and TSR are empty.
SCRATCH PAD REGISTER
Scratchpad Register is an a-bit Readl
Write register that has no effect on
either channel in the VL 16C45l B. It is
intended to be used by the programmer
to hold data termporarily.
INTERRUPT IDENTIFICATION
REGISTER
In order to minimize software overhead
during data character transfers, the
serial channel prioritizes interrupts into
four levels. The four levels of interrupt
conditions are as follows:
1. Receiver Line Status (priority 1)
2. Received Data Ready (priority 2)
3. Transmitter Holding Register Empty
(priority 3)
4. Modem Status (priority 4)
Information indicating that a prioritized
interrupt is pending and the type of
interrupt is stored in the Interrupt
Identification Register (IIR). The IIR
indicates the highest priority interrupt
pending. The logic equivalent of the
interrupt control circuit is shown in
Figure 3. The contents of the IIR are

indicated in Table 4 and are described
below.
UR(O): UR(O) can be used to indicate
whether an interrupt is pending. When
UR(O) is low, an interrupt is pending.
UR(l) and IIR(2) are used to identify the
highest priority interrupt pending as
indicated in Table 2.
UR(3) - UR(7): These five bits of the UR
are 10gicO.
INTERRUPT ENABLE REGISTER
The Interrupt Enable Register (IER) is a
Write register used to independently
enable the four serial channel interrupt
sources which activate the interrupt
(INTRPT) output. All interrupts are
disabled by resetting IER(O) - IER(3) of
the Interrupt Enable Register. Interrupts are enabled by setting the
appropriate bits of the IER high.
Disabling the interrupt system inhibits
the Interrupt Identification Register and
the active (high) INTRPT output. All
other system functions operate in their
normal manner, including the setting of
the Line Status and Modem Status
Registers. The contents of the Interrupt
Enable Register is described in Figure 2
and below:
IER(O): When set to one, IER(O)
enables Received Data Available
interrupt.
IER(l): When set to one, IER(l)
enables the Transmitter Holding
Register Empty interrupt.
IER(2): When set to one, IER(2)
enables the Receiver Line Status
interrupt.
IER(3): When set to one, IER(3)
enables the Modem Status Interrupt.
IER(4) - IER(7): These four bits of the
IER are Logic O.
TRANSMITTER
The serial transmitter section consists
of a Transmitter Holding Register
(THR), Transmitter Shift Register
(TSR), and associated control logic.
The Transmitter Holding Register
Empty (THRE) and Transmitter Empty
(TEMT) are two bits in the Line Status
Register which indicate the status of
THR and TSR. The microprocessor
should perform a write to the THR only
if THRE is one. This causes the THRE

6-35

to be reset to O. THRE is set high when
the word is automatically transferred
from the THR to the TSR during the
transmission of the start bit.
TEMT remains low for at least the
duration of the transmission of the data
word. Since the data word cannot be
transferred from the THR to the TSR
until the TSR is empty, THRE remains
low until the TSR has completed
sending the word.
RECEIVER
Serial asynchronous data is input into
the SIN pin. A start bit detect circuit
continually searches for a high to low
transition from the idle state. When the
transition is detected, a counter is reset,
and counts the l6X clock to 7 1/2,
which is the center of the start bit. The
start bit is valid if the SIN is still low.
Verifying the start bit prevents the
receiver from assembling a false data
character due to a low going noise
spike on the SIN input.
The Line Control Register determines
the number of data bits in a character
[LCR(O), LCR(l)], if parity is used
LCR(3), and the polarity of parity
LCR(4).
Status for the receiver is provided in the
Line Status Register. When a full character is received including parity and
stop bit, the Data Received indication in
LSR(O) is set high. The CPU reads the
Receiver Buffer Register which resets
LSR(O). Hthe character is not read
prior to a new character transfer from
the RSR to the RBR, the overrun error
status indication is set in LSR(l). H
there is a parity error, the parity error is
set in LSR(2). If a stop bit is not
detected, a framing error indication is
set in LSR(3).

Hthe data into SIN is symmetrical
square wave, the center of the data
cells will occur within ±3.l25% of the
actual center, providing an error margin
of 46.875%. The start bit can begin as
much as one l6X clock cycle prior to
being detected.
BAUD RATE GENERATOR (BRG)
The BRG generates the clocking for the
UART function, providing standard
ANSIICCITI bit rates. The oscillator
driving the BRG is provided by an
external clock into eLK.

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

The data rate is determined by the
Divisor Latch registers DLL and DLM
and the external frequency. The bit rate
is selected by programming the two
divisor latches, Divisor Latch Most
Significant Byte and Divisor Latch Least
Significant Byte. Setting DLL=1 and
DLM=O selects the divisor to divide by 1
(divide by 1 gives maximum baud rate
for a given input frequency at the CLK
input).
The BRG can use any of three different
popular frequencies to provide standard
baud rates. These frequencies are
1.8432 MHz, 3.072 MHz, and 8 MHz.
With these frequencies, standard bit
rates from 50 to 512K bps are available.
Tables 5, 6 and 7 illustrate the divisors
needed to obtain standard rates using
these three crystal frequencies.
RESET
After power up, the VL16C451B -RES
input should be held low for 500 ns to
reset the VL 16C451 B circuits to an idle
mode until initialization. A low on
-RES causes the following:
1. Initializes the transmitter and
receiver internal clock counters.

2. Clears the Line Status Register
(LSR), except for Transmitter Shift
Register Empty (TEMT) and
Transmit Holding Register Empty
(THRE), which are set. The Modem
Control Register (MCR) is also
cleared. All of the discrete lines,
memory elements and miscellaneous logic associated with these
register bits are also cleared or
turned off. The Line Control
Register (LCR), Divisor Latches,
Receiver Buffer Register, Transmitter Buffer Register are not affected.
Following removal of the reset condition
(Reset high), the VL16C451 B remains
in the idle mode until programmed.
A hardware reset of the VL 16C451 B
sets the THRE and TEMT status bit in
the LSR. When interrupts are subsequently enabled, an interrupt occurs
due to THRE.
A summary of the effect of a reset on
the VL16C451 B is given in Table 8.
PROGRAMMING
The serial channel of the VL 16C451 B is
programmed by the control registers

LCR, IER, DLL and DLM, and MCR.
These control words define the character length, number of stop bits, parity,
baud rate, and modem interface.
While the control register can be written
in any order, the IER should be written
to last because it controls the interrupt
enables. Once the serial channel is
programmed and operational, these
registers can be updated any time the
VL 16C451 B serial channel is not transmitting or receiving data.
SOFTWARE RESET
A software reset of the serial channel is
a useful method for returning to a
completely known state without a
system reset. Such a reset consists of
writing to the LCR, Divisor Latches, and
MCR registers. The LSR and RBR
registers should be read prior to
enabling interrupts in order to clear out
any residual data or status bits which
may be invalid for subsequent operation.
CLOCK INPUT OPERATION
The maximum input frequency of the
external clock of the VL 16C451 B is
8 MHz. For VL 16C451, the maximum
input frequency of the external clock is
3.1 MHz.

TABLE 4. INTERRUPT IDENTIFICATION REGISTER
INTERRUPT IDENTIFICATION

INTERRUPT SET AND RESET FUNCTIONS
Interrupt
Flag

Interrupt
Source

None

First

Receiver
Line Status

OE. PE
FE, or BI

LSRRead

Second

Received Data
Available

RBR Read

Third

THRE

IIR Read if THRE is the
Int!'lrrupt Source or THR Write

Fourth

Modem Status

-CTS, '-DSR
-RI,-DeD

MSRRead

Bit 2

BH 1

Bit 0

Priority
Level

X = Not Defined.
6-36

Interrupt
Reset Control

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

FIGURE 3. INTERRUPT CONTROL LOGIC
DR (LSR BIT 0)
ERBFI (IER BIT 0)

THRE (LSR BIT 5)
ETBEI (IER BIT 1)
DE (LSR BIT 1)
PE (LSR BIT 2)
FE (LSR BIT 3)
BI (LSR BIT 4)
ELSI (IER BIT 2)
DCTS (MSR BIT 0)
DDSR (MSR BIT 1)
TERI (MSR BIT 2)
DDCD (MSR BIT 3)
EDSSI (IER BIT 3)
INTERRUPT ENABLE (MCR BIT 3)

TABLE 5. BAUD RATES (1.8432 MHz CLOCK)
Desired
Baud Rate

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

Divisor Used

2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12

Percent Error
Difference Between
Desired and Actual

0.026
0.058

0.69

6
3

2.86

6·37

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451B

TABLE 6. BAUD RATES (3.072 MHz CLOCK)
Desired
Baud Rate

Divisor Used

Percent Error
Difference Between
Desired and Actual

3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

0.026
0.034

0.312
0.628
1.23

TABLE 7. BAUD RATES (8 MHz CLOCK)
Baud Rate
Desired

Divisor Used
to Generate
16 x Clock

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000

1000
6667
4545
3717
3333
1667
833
417
277
250
208
139
104
69
52
26
13
9
4
2
1

Percent Error
Difference Between
Desired and Actual

0.005
0.010
0.013
0.010
0.020
0.040
0.080
0.080

0.160
0.080
0.160
0.644
0.160
0.160
0.160
0.790
2.344
2.344
2.400

6-38

•

VLSI TECHNOLOGY, INC.
VL 16C451NL16C451 B

TABLE 8_ RESET
Reset Control

Reset

Interrupt Enable Register
Interrupt Identification
Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register

Reset
Reset

SOUT
Intrpt (RCVR Errs)
Intrpt (RCVR Data Ready)
Intrpt (THRE)
Intrpt (Modem Status Changes)
-OUT2
-RTS

Reset
Read LSAlReset
Read RBAlReset
Read IIRlWrite THAlReset
Read MSRlReset
Reset
Reset
Reset
Reset

All Bits Low (0-3 Forced and 4-7 Permanent)
Bit 0 is High, Bits 1 and 2 Low
Bits 3-7 Are Permanently Low
All Bits Low
All Bits Low
All Bits Low, Except Bits Sand 6 Are High
Bits 0-3 Low
Bits 4-7 Input Signal
High
Low
Low
Low
Low
High
High
High
High

Reset
Reset
Reset
Reset

-DTR
-OUT1

DEVICE APPLICATION

TYPICAL COMPONENT VALUES
Crystal

RX2

8 MHz

1 Mn

1.SKn

10-30pF

40-90pF

3.072 MHz

1 Mil

1.SKn

10 - 30 pF

40-90pF

1.843 MHz

1 Mil

1.SKn

10-1SpF

6S-100pF

VL16C451IVL16C451B

SERIAL
CHANNEL 0
BUFFERS

DATA
BUS

AOOR
BUS
CTL
BUS

9-PINOR
25·PIN
"0CONN

"XTAl1

OPTION
JUMPERS

ACE AND
PRINTER
PORT

c:::J
"Vl16C451B only

"XTAl2
RX2
C2I

PARALLEL
PORT
RIC NET

6-39

IC1

25-PIN
"0"
CONN

[II

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C4518

TABLE 9. SERIAL CHANNEL ACCESSIBLE REGISTERS
Register Bit Number
Register
Mnemonic

Bit 7

Bit 6

BitS

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RBR
(Read Only)

Data
Bit 7
(MSB)

Data
Bil6

Data
BitS

Data
Bil4

Data
Bil3

Data
Bit 2

Data
Bil1

Data
BiiO
(LSB)"

THR
(Write Only)

Data
Bit 7

Data
Bil6

Data
BitS

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
BiiO

DLL

Bit 7

Bit 6

BitS

Bil4

Bit 3

Bit 2

Bit 1

Bit 0

DLM

Bit 15

Bit 14

Bit 13

Bit 12

Bil11

Bit10

Bil9

Bit 8

IER

(EDSSI)
Enable
Modem
Status
Interrupt

(ELSI)
Enable
Receiver
Line
Status
Interrupt

(ETBEI)
Enable
Transmitter
Holding
Register
Empty
Interrupt

(ERBFI)
Enable
Received
Data
Available
Interrupt

IIR
(Read Only)

Interrupt
ID
BiI(1)

Interrupt
ID
Bit (0)

"0· If
Interrupt
Pending

LCR

(DLAB)
Divisor
Latch
Access
Bil

Set
Break

Stick
Parity

(EPS)
Even
Parity
Select

(PEN)
Parity
Enable

(STB)
Number
of Stop
Bils

(WLSB1)
Word
Length
Select
Bit 1

(WLSBO)
Word
Length
Select
Bit 0

MCR

Loop

INT

(RTS)
Request
To
Send

(DTR)
Data
Terminal
Ready

LSR

(TEMT)
Transmitter
Empty

(THRE)
Transmitter
Holding
Register
Empty

(BI)
Break
Interrupt

(FE)
Framing
Error

(PE)
Parity
Error

(OE)
Overrun
Error

(DR)
Data
Ready

MSR

(DCD)
Data
Carrier
Detect

(RI)
Ring
Indicator

(DSR)
Data
Ready
Set

(CTS)
Clear
to
Send

(DDCD)
Delta
Data
Carrier
Detect

(TERI)
Trailing
Edge
Ring
Indicator

(DDSR)
Delta
Data
Set
Ready

(DCTS)
Delta
Clear
to
Send

SCR

Bil7

Bil6

BitS

Bit 4

Bil3

Bit 2

Bil1

BiiO

*LSB Data Bit 0 is the first bit transmitted or received.

6-40

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL 16C451 8

PARALLEL PORT REGISTERS
The VL l6C45l B's parallel port interfaces the device to a Centronics-style
printer. When Chip Select 2 (-CS2) is
low, the parallel port is selected. Table
10 shows the registers associated with
this parallel port. The read or write
function of the register is controlled by
the state of the read (-lOR) and write
(-lOW) pin as shown. The Read Data
Register allows the microprocessor to
read the information on the parallel bus.
The Read Status Register allows the
microprocessor to read the status of the
printer in the five most significant bits.

The parallel port is completely compatible with the parallel port implementation used in the IBM SerialIParaliel
Adaptor when -PEMD (pin 1) is held
low. (VL l6C45l B only.)

The status bits are Printer Busy
(BSY). Acknowledge (-ACK) which is a
handshake function. Paper Empty (PE).
Printer Selected (SLCT). and Error
(-ERR). The Read Control Register
allows the state of the control lines to be
read. The Write Control Register sets
the state of the control lines. They are
Interrupt Enable (IRQ ENB). Select In
(-SUN), Initialize the Printer (-IN IT).
Autofeed the Paper (-AFD) and Strobe
(-STB). The Write Data Register allows
the microprocessor to write a byte to the
parallel bus.

The following two paragraphs apply to
the VL16C451 only.
Figure 4 describes the operation of the
-LPTOE input. When -LPTOE goes
Low. the internal data latch is enabled
to the PDO-PD7 lines. PDO-PD7 will
then contain the same information as
the latch.
When -LPTOE goes gigh. the internal
data latch is disabled from the PDO-P07
lines. An external device can place
data on the PDO-P07 lines. and reading
the data reads the POO-P07 lines.

TABLE 10. PARALLEL PORT REGISTERS
Register

Bit 6

Bit 5

PD7

P06

P05

Read Status

-BSY

-ACK

Read Control

IRQENB

P07

P06

P05

P04

P03

IRQENB

SUN

Read Port

Write Port
Write Control

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

P04

P03

P02

POl

POO

SLCT

-ERR

SUN

-INIT

AFO

STB

P02

POI

POO

-INIT

AFO

STB

TABLE 11. PARALLEL PORT REGISTER SELECT
Control Pins

-lOR
0

-lOW
1

-CS2
0

AI
0

AO
0

0
0

1
1

0
1

1
0

Read Status
Read Control

0
1
1

1
0
0

0
0
0
0
0

1
0
0

1
0
1

Invalid
Write Port
Invalid

Write Control

Invalid.

Read Port

FIGURE 4. -LPTOE FUNCTION
(VL16C451 ONLY)
READ - - - - - - ,
DATA
OE

WRITE
DATA - - - - - - ,

-LPTOE _ _ _--'

• See General Purpose 110 Register Description (VL l6C451 B only).
6-41

PDQ·PDl

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

THE FOLLOWING TWO PAGES
PERTAIN TO VL16C451B ONLY.
Line Printer Port:
The Line Printer Port contains the
functionality of the port included in the
VL 16C451, but offers a hardware
programmable Extended Mode,
controlled by the Printer Enhancement
Mode (-PEMD) pin. This enhancement
is the addition of a Direction Control Bit,
and an Interrupt Status Bit.

Register 1 Read· Line Printer Status
Register:
The Line Printer Status (LPS) Register
is a read-only register that contains
interrupt and printer status of the LPT
connector pins. In the table below (in
the Default column) are the values of
each bit in the case of the printer being
disconnected from the port. The bits
are described as follows:

Register 0 • Line Printer Data
Register:
The Line Printer (LPD) port is either
output-only or bidirectional, depending
on the state of the Extended Mode pin
and Data Direction Control bits.

Bit
0
1
2

3
4
5

Description
Reserved
Reserved
-PIRO
-ERR
SLCT
PE
-ACK
-BSY

Default
1
1
1
1
1
1
1
0

Compatibility Mode (-PEMD pin-O):
Reads to the LPD register return the
last data that was written to the port.
Write operations immediately output
data to the PDO-PD7 pins.

Bits 0 and 1 - Reserved, read as 1's.

Extended Mode (-f'EMD pin-1):
Read operations return either the data
last written to the LPT Data Register if
the Direction Bit is set to Write (low) or
the data that is present on PDO-PD7 if
the direction is set to Read (high).
Writes to the LPD register latch data
into the output register, but only drive
the LPT port when the Direction Bit is
set to Write.

Bit 2 - Printer Interrupt (-f'IRO, active
low) Status bit, when set (low) indicates
that the printer has acknowledged the
previous transfer with an -ACK handshake (bit 4 of the control register must
be set to 1). The bit is set to 0 on the
active to inactive transition of the -ACK
signal. This bit is set to a 1 after a read
from the status port. The default (power
on reset) value for this bit is 1.

The table below summarizes the
possible combinations of Extended
Mode and the Direction control bit.

Bit 3 - Error (-ERR, active low) Status
bit corresponds to -ERR input.

-PEMD DIR

PDO-PD7 Function
PC/AT Mode - Output
PS/2 Mode - Output
PS/2 Mode • Input

In either case, the bits of the LPD
Register are defined as follows:
Bit

PDO
PD1
PD2

3
4
5

PD3
PD4
PD5

PD6
PD7

Bit
0
1
2

3
4
5
6

Bit 4 • Select (SLCT) Status bit corresponds to SLCT input.
Bit 5 - Paper Empty (PE) Status bit
corresponds to PE input.
Bit 6 - Acknowledge (-ACK, active low)
Status bit corresponds to -ACK input.
Bit 7 - Busy (-BSY, active low) Status·
bit corresponds to BUSY input.

Description
STB
AFD
-INIT
SUN
PIROEN
DIR (write only)
Reserved (1)
Reserved (1)

Bit 0 - Printer Strobe (STB) Control bit,
when 1 the strobe signal is asserted on
the LPT interface. When 0 the signal is
negated.
Bit 1 - Auto Feed (AFD) Control bit,
when 1 the -AFD signal will be asserted
on the LPT interface. When 0 the
signal is negated.
Bit 2 - Initialize Printer (-IN IT) Control
bit, when 1 the -INIT signal is negated.
When 0 the INIT signal is asserted on
the LPT interface.
Bit 3 - Select Input (SUN) Control bit,
when 1 the SUN signal is asserted, on
the LPT interface. When 0 the signal is
negated.
Bit 4 - Interrupt Request Enable (PIRO
EN) Control bit, when 1 enables
interrupts from the LPT port whenever
the -ACK signal is asserted. When 0
disables interrupts.
Bit 5 - Direction (DIR) Control bit (only
used when -PEMD is high), when 1 the
output buffers in the LPD port are
disabled, allowing data driven from
external sources to be read from the
LPDport.

Description

1
2

Register 2 • Line Printer Control
Register:
The Line Printer Control (LPC) Register
is a readlWrite port that is used to
control the PDO-PD7 direction and drive
the Printer Control lines. Write operations set or reset these bits, while read
operations return the state of the last
write operation to this register (except
for bit 5 which is write only). The bits in
this register are defined as follows:

6-42

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

GPIO - General Purpose 110 Register:
The General Purpose 110 (GP/O)
Register is an additional register in the
VL16C451 B which is used to control the
general purpose 110 signals. This
register can be accessed when -CS2 is
asserted low, AO and A1 are high and
the enhanced mode control signals
have configured the GPIO signals.

Reads to those bits programmed as
outputs will return the state of the last
write operation to that bit. Writes to
those bits programmed as inputs will
not have any affect. The bits in the
register are defined as follows:

Bit
0
1
2
3

4
5

6
7

Description
GPINO
GPIN1
GPIN2
GPI03
GPI04
GPOUT5
GPOUT6
GPOUT7

AC CHARACTERISTICS (VL16C451 B ONLV): TA= O'C to +70'C, VDD= 5 V ±5% (Note 4)
Min

Max

Units

Conditions

Symbol

Parameter

tDIW

-lOR Strobe Width

125

Read Cycle = tAR(1 )+tDIW+tRC

280

tODD

Delay from -lOR to Data

tHZ

-lOR to Floating Data Delay

tOOW

-lOW Strobe Width

100

Write Cycle = tAW+tDOW+TVC

280

tOS

Data Setup Time

tOH

Data Hold Time

tRA

Address Hold Time from -/OR

Note 1

tRCS

Chip Select Hold Time from -lOR

Note 1

tAR

-lOR Delay from Address

Note 1

tCSR

-lOR Delay from Chip Select

Note 1

tWA

Address Hold Time from -/OW

Note 1

tWCS

Chip Select Hold Time from -lOW

Note 1

tAW

-/OW Delay from Address

Note 1

tCSW

-lOW Delay from Select

Note 1

tRW

Reset Pulse Width

f.Ls

ns
ns
110

100 pFLoad

100

100 pF Load, Note 3

tXH

Duration of Clock High Pulse

External Clock (8 MHz Max.)

tXL

Duration of Clock Low Pulse

External Clock (8 MHz Max.)

tRC

Read Cycle Delay

125

tWC

Write Cycle Delay

150

Notes:

1. The internal address strobe is always active.
2. RCLK = tXH and tXL.
3. Charge and discharge time is determined by VOL, VOH and the external loading.
4. All timings are referenced to valid 0 and valid 1.
(See AC Test Points.)

6-43

---- -----------------

-~~--

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

AC CHARACTERISTICS (VL16C451 ONLY):

TA= o·c to +70·C, VDD: 5 V ±5% (Note 4)
Min

Max

Units

Symbol

Parameter

tDIW

-lOR Strobe Width

125

Read Cycle

360

Conditions

tODD

Delay from -lOR to Data

tHZ

-lOR to Floating Data Delay

IDOW

-lOW Strobe Width

100

Write Cycle

360

IDS

Data Setup lime

tDH

Data Hold lime

tRA

Address Hold Time from -lOR

Note 1

tRCS

Chip Select Hold Time from -lOR

Note 1

tAR

-lOR Delay from Address

Note 1

tCSR

-lOR Delay from Chip Select

Note 1

tWA

Address Hold lime from -lOW

Note 1

tWCS

Chip Select Hold Time from -lOW

Note 1

tAW

-lOW Delay from Address

Note 1

tCSW

-lOW Delay from Select

Note 1

tRW

Reset Pulse Width

j.ls

tXH

Duration of Clock High Pulse

140

External Clock

tXL

Duration of Clock Low Pulse

140

External Clock

Notes:

1.
2.
3.
4.

125

100 pF Load

100

100 pF Load, Note 3

The internal address strobe is always active.
RCLK = tXH and tXL.
Charge and discharge time is determined by VOL, VOH and the external loading.
All timings are referenced to valid 0 and valid 1.
(See AC Test Points.)

6-44

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C451 B

AC CHARACTERISTICS (Cont.):
Symbol

TA = O°C to +70°C, VDD = 5 V ±5% (Note 4)

Parameter

Min

Max

Units

Conditions

175

100 pFload

Transmitter
tHR1

Delay from Rising Edge of -lOW
(WR THR) To Reset Interrupt

tlRS

Delay from Initial INTO Reset to Transmit Start

tSI

Delay from Initial Write to Interrupt

tSTI

Delay from Stop to Interrupt (THRE)

tlR

Delay from -lOR (RD IIR)
to Reset Interrupt (THRE)

ClK
Cycles

Note 2

ClK
Cycles

Note 2

ClK
Cycles

Note 2

250

100 pF Load

Modem Control
tMDO

Delay from -lOW
(WR MCR) to Output

250

100 pF load

tSIM

Delay to Set Interrupt from Modem Input

250

100 pF load

tRIM

Delay to Reset Interrupt from
-lOR (RS MSR)

250

100 pF load

Receiver
tSINT

Delay from Stop to Set Interrupt

ClK
Cycles

tRINT

Delay from -lOR
(RD RBRIRD lSR) to Reset Interrupt

I1s

Notes:

1.
2.
3.
4.

The internal address strobe is always active.
RClK = tXH and tXL.
Charge and discharge time is determined by VOL, VOH and the external loading.
All timings are referenced to valid 0 and valid 1 (see AC Test Points).

6-45

Note 2

100 pF load

•

VLSI TECHNOLOGY, INC.
VL 16C451 /VL 16C451 B

WRITE CYCLE TIM_IN_G_ _ _----:;-;:;-;-;;-_ _ _-:
A2. A1 AO

VALID

-CS

.---0_
~

WC-___________~~_I

-----ICSW

~--~wl~-~~r~==~r-~----~~---~

ACTIVE

-lOW

~R
-lOR

-------------------------t--------N2------tACTIVE

IDH~I
)~----------------

IDS
DATA - - - - - - - - - - - - - - - - . , ( VALID DATA
DBO-DB7

READ CYCLE TIMING
A2 A1 AO

VALID

---CS

VALID

)K
...

IRA

I'"--IRC~

ICSRr--

-lOR

....

......

RC~IDIW~

\ - \.

ACTIVE) f-

~tACTIVE_
A

-lOW

VCTIVE_

------------=l~~~
1000--

--.-

......

1HZ

DATA
DBO-DB7

.
6-46

)\..-1·_ _-

•

VLSI TECHNOLOGY, INC.
VL 16C451/VL16C4518

RECEIVER TIMING

(RECEI~~
\
INPUT

START G T A BITS (5-8)

DATA)
SAMPLE
CLK
INTERRUPT
(DATARCVRERR)
READY OR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

-lOR ----------------~----,\

ACTIVE

TRANSMITTER TIMING

S:/
_L
_______

SERIAL
OUT (SOUT)

DATA (5-8)

tlRS

DSTOP
PARITY

(1_2){STA~RT tSTI
~
_ _ _ _---,

INTERRUPT
(THRE)

~RTHR)~~~==~~~
-<'

ODIS

DATA
00-07
• Applicable only when -ADS is tied low.

BAUDOUT TIMING

14
XTALl

tBLO....j j4- ....j 14- tHW
n n n n n

-BAUOOUT - ,
(+1)
UUUUUL

~j4-.tBHO

~ r-tL~

~ I--tBLO

!....J

tLW

-BAUOOUT

(<2)

~ j4-tBHO

HtHW

....jj.-tBLo1r- tBHO

IHW~tlW~

-BAUDOUT

(+3)
~ I4-IBHO

.-.j I4-IBLO II

-BAUOOUT
(+N,N>3)

~IHW=(N-2)XTALl

L---....-...Jr~
6-90

CYCLES

ACTIVE

VLSI TECHNOLOGY, INC.
VL16C550
RECEIVER TIMING

L-.l~_ _-1L

RClK

------~-J

1'4

14n
1 L

ISCD

SAMPLE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ClK

16C:~:~
Mode

(RECEIVER
INPUT
DATA)

SAMPLE
ClK

)

START ~TA BITS (!HI
.
_

L_~_-.J_---1.I;-:---1I=_""'-----(~(~
"'NT

--'----1----11--

(DATAREADYOR
INTO,INT2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
RCVRERR)

J~~NT}-

-lOR - - - - - - - - - - - - - - - - - - - - \

ACTIVE

TRANSMITTER TIMING
SERIAL
OUT (SOUT)

DSTOP
L--_ _ _ _ _ PARITY

-----"""""'\1

INTO,INT2
(THRE)

(1_2){STA~RT

ISTI

----,
~-.tlR

(WRTHR)
-DOSTR/DOSTR
(NOTE 1)

--=____________________

-DISTR/DISTR _ _ _
(RDIIR)
(NOTE 2)

Notes: 1. See Write Ti.mi.ng.
2. See Read Tlmmg.

6-91

•

VLSI TECHNOLOGY, INC.
VL16C550

WRITE TIMING
-ADS

A2, Al, AD

m~l'------t----

-CS2, CS1, CSO

14---:..:.::..::..:..:......_---1..--__, _ w c - - - - - i - ,
~~---tWC--__I~

-DOSTRIDOSTR

ACTIVE
OR

-DISTRIDISTR

-~-----1--:;:=~
IDS 14---I~-"'1IDH

DATA
DO-D7

• Applicable only when -ADS is tied low.

MODEM TIMING

~OW~

\---~--t

(WR MCR) ___
-RTS, -DTR

-CTS, -DSR, -DCD

INTO,INT2

IMDO

--------t---

-lOR _ _ _ _ _ _ _~
(RDMSR)
- R I - - - - - - - - - - - - , L . _ __

Notes: 1. See Write Ti.mi.rig.
2. See Read TIming.

6·92

•

VLSI TECHNOLOGY, INC.
VL16C550

RCVR FIFO FIRST BYTE (This seta RDR.)

SIN~~
\

STOP

I I Inl I I I I I I

SAMPlE CLOCK

(FIFO AT OR ABOVE
/ -_ _ _ _ _ _ _--.-;_ _ _ TRIGGER LEVEL)
INTO,INT2
(TRIGGER LEVEL
INTERRUPT)
(FCR6, 7.1l, 0)
INTO,INT2
(LSR INTERRUP1)

-lOR

j:;-

----------,-+-'1

(FIFO BELOW
TRIGGER LEVEL)

IRINT

----------'1
----------~

(ROLSR)

-lOR

-------------------"'1

(RORBR)

ACTIVE

RCVR FIFO FIRST BYTE (RDR fs already set.)
SIN~r-

~STOPV

I I I I I I I

SAMPLE CLOCK

(TIMEOUT
OR
INTO.1NT2
TRIGGER LEVa
INTERRUPT)

(FIFO AT OR ABOVE
TRIGGER lEVa)

~~
Note 2

-----+

INTO, tNT2 -

(FIFO BELOW
TRIGGER LEVa)

ISINT

(LSR INTERRUPT) _

-~R-----~-~

(ROLSR)

-tOR
(RORBR)

ACTIVE
PREV~BYTE

READ FROM FIFO

TRANSMITTER READY (PIN 24)-MODE 0
-DOSTR,OOSTR - - - - . . .

~R~R)
SOUT

r---..J

,-----<\1---------\~---------

DATA

-TXRDY

Notes: 1. This is the reading of the last byte in the FIFO.
2. If FCRO=1, then tSINT=3 RCLKs. For a timeout interrupt, tSINT=8 RCLKs.

6·93

•

VLSI TECHNOLOGY, INC.
VL16C550

TRANSMITTER READY (PIN 24)-MODE 1
-DOSTR.DOSTR - - - - . . .

~--....

,----H----------

(WRTHR) _ _- - ' " ' - - _ - - ' I ' - -_ _- - { { -_ _ _ _ _ _ _ __

SOUT

-TXADY

RECEIVER READY (PIN 29)-MODE 0

-DISTR, OISTR
(RORBR)

-----~\ { - - - - - - - - . . .

\ ~_ _ _ _- - '

1'-----'

SIN~
(FIRST BYTE) --.../ STOP " ' - - - -

SAMPLE eLK _ _- - J_ _--L_ _

~x~ ~t--------+..J

tRINT

Note 2

RECEIVER READY (PIN 29)-MODE 1
-OISTR,OISTR - - - - - - - ( , { - - - - - - ' "
(RORBR)
, 1--_ _ _ _- - '

1----"
Note 1

SIN
(FIRST BYTE THAT ~
REACHES THE - - . / STOP ' - - - TRIGGER lEVEL)

SAMPLE ClK - - - - ' - -..........- -

~~v ~Tt--------If-'

tRlNT

Note 2

Notes: 1. This is the reading of the last byte in the FIFO.
2. If FCRO= 1, then tSINT=3 RCLKs. For a timeout interrupt, tSINT=8 RCLKs.
6-94

•

VLSI TECHNOLOGY, INC.
VL16C550

AC TESTING INPUT/OUTPUT WAVEFORMS
EXTERNAL CLOCK INPUT (8.0 MHz MAXIMUM)

AC TEST POINTS

Note: All timings are referenced to valid 0 and valid 1.

TEST CIRCUIT

Device Under Tesl
680U

........ ""'po ........ pP
Capacitance

FIGURE 3. BASIC CONFIGURATION

SOUT
-MEMR OR -lIOR
-MEMW OR-lIOW
INTR
RESET
CPU
BUS

AD
Al
A2

-DISTR
-ilOSTR

-RTS

INTRPT

-OTR

-DSR

EIA
DRIVERS
TORS232
INTERFACE

TYPICAL COMPONENT VALUES

VLI8C550
A1

-CTS

-ADS

XTALIN

Crystal

RX2

8.0 MHz

lMn

1.5KU

10·30 pF

3.072 MHz

lMn

1.5KU

10 - 30 pF

40-90 pF

1.843 MHz

lMn

1.5KU

10 ·15 pF

65-100pF

40- 90 pF

-TXRDY
-RXRDY

-CS2

RP
XTALOUT

CSI
CSO
DOSTR

r=J

RX2
-BAUDOUT

021

RCLK

DISTR

6·95

IC1

•

VLSI TECHNOLOGY, INC.
VL16C550

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

-10·C to +70·C

Storage Temperature -ss·C to + 150·C
Supply Voltage to
Ground Potential -0.5 V to VCC +0.3 V
Applied Output
Voltage

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

-0.5 V to VCC +0.3 V

Applied Input
Voltage

-0.5 Vto +7.0 V

Power Dissipation

500 mV

DC CHARACTERISTICS:

=o·c to +70·C, VCC =S V ±S%

Symbol

Parameter

Min

VILX

Clock Input Low Voltage

VIHX

Clock Input High Voltage

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

Max

Units

-0.5

0.8

2.0

VCC

-0.5

0.8

VCC

0.4

2.0

IOL 1.6 mA on All

2.4

Conditions

IOH =-1.0 mA

VCC=S.25 V. No Loads on outputs. SIN. -DSR.
-CTS. -DCD. -AI = 2.0 V.
All Other Inputs = 0.8 V.
Baud Rate Generator at 8 MHz.
Baud Rate at 256K.

Input Leakage

±10

VCC=5.25 V
VSS=OV
All Other Pins Floating

ICL

Clock Leakage

±10

VIN = 0 V. 5.25 V
All Other Pins Floating

IOZ

Three-State Leakage

±20

itA

VCC = 5.25 V
VSS=OV
VOUT _ 0 V. 5.25 V
1) Chip Deselected
2) Chip and Write Mode Selected.

VILMR

MR Schmitt VIL

0.8

VIHMR

MRScnmittVIH

ICC
(Ave)

Average Power Supply
Current (VCC)

ilL

CAPACITANCE:

TA = 2S·C, VCC

2.0

= vss = 0 V

Symbol

Parameter

Typ

Max

Unit

CXTAL2

Clock Input Capacitance

Min

CXTAL1

Clock Output Capacitance

fc = 1 MHz
Unmeasured pins returned to VSS

Input Capacitance

Output Capacitance

6-96

Conditions

•

VLSI TECHNOLOGY, INC.
VL 16C551
ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

FEATURES
• Hardware and software compatible
with Vl16C451 and Vl16C451B

operations being performed, and error
conditions.

DESCRIPTION

In addition to its communications
interface capabilities, the VL 16C551
provides the user with a fully bidirectional parallel data port that fully
supports the parallel Centronics type
printer. The parallel port, together with
the two serial ports, provide IBM PCI
AT- compatible computers with a single
device to serve the three system ports.

• IBM PC/AT-compatible
• Enhanced Bidirectional Line Printer
Port
• 16-byte FIFO reduces CPU interrupts
• Independent control of transmit,
receive, line status and data set
interrupts on each channel
Individual modem control signals for
each channel
• Programmable serial interface
characteristics for each channel:
- 5-,6-, 7- or 8-bit characters
- Even-, odd- or no-parity bit
generation and detection
- 1, 1 112 or 2 stop bit generation
• Three-state TIL drive for the data and
control bus on each channel

The VL 16C551 is an enhanced version
of the popular VL 16C550 asynchronous
communications element (ACE). The
device serves as a serial input/output
interface in microcomputer- or microprocessor-based systems. It performs
serial-to-parallel conversion on data
characters received from peripheral
devices or modems, and parallel-toserial conversion on data characters
transmitted by the CPU. The complete
status of the ACE can be read at any
time during functional operation by the
CPU. The information obtained includes
the type and condition of the transfer

PIN DIAGRAM

The Vl16C551 is housed in a
68-pin plastic leaded chip carrier.

BLOCK DIAGRAM
-eTS
-DSR -----10-{

VL16C551
GPl03 GPIN1

A programmable baud rate generator is
included that can divide the timing
reference clock input by a divisor
between 1 and (216 _1).

XTAL1

TRI

-ACK

BUSY VDDR

-111====1

GP0UT7

-oem

SIN -----1""\
-eoo -----1""\

VL16C450

UART

..fITS
-DTR
SOUT
INTO
-ClUT2

XTALI - - - - - I
XTAL2 -----10-{
-EMOOEA

-olJT2

-EMOOEB

INn

GPIa.

-:-SLiN

GPOUT5

-INIT

DBO

OBI

-STB

082

GPOUT8

DBa

PDO

DB4

POI

DBS
DBS

PD2
PD.

DB7

PD4

-neRDY

PDS

VDoR

PD6

-RTS

PD7

-DTR

INTO

SOUT

BDO

~~B7~7f~~--------J
POO.p07
-ERR ----+ 3 ) ! .

--.J!

tHW = (N - 2) XTAL 1 CYCLES

L-

L...-_ _

6-144

•

VLSI TECHNOLOGY, INC.
VL16C552

RECEIVER TIMING

L..(~~_ _ _IL
I4--ISCD
BClKS ------..,~ n

RClK

SAMPLE
ClK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

VL16C450 Mode

(RECEIV~~
\
INPUT

START W T A BITS

(~)

DATA)
SAMPLE
ClK

...L_--L_---L-_??

~t= ..",
(DATAINTERRUPT
READY OR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

tAINT.!

RCVR ERoRR) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\
-I

4
J
Ct-

ACTIVE
.

TRANSMITTER TIMING
SERIAL
OUT (SOUT)

INTERRUPT
(THRE)

DsTOP

_ _ _ _ _ PARITY

-----~

(1-2)fsTA~RT ISTI

----,'

(wRi~~~~~_______~________________~
-lOR
(RDIIR)

6-145

•

VLSI TECHNOLOGY, INC.
VL16C552

WRITE TIMING
A2, A1, AO

-CS2, CS1,

~ I"\,? VAllO

2.f

~ VAllO......

cso

~tAW

tCSW

~m;~

~
~

4-tDOW

-lOW

'tWA

ACTIVE]

.....

tWC

~K ACTIVE
tR

-lOR
tOS

--~

.... tOH

~VALlOOAT~

OATA
00-07

MODEM TIMING

-IOW~

(WR MCR) _ _\_ _ __ _ttMDO
-RTS, -OTR

-CTS, -OSR, -OCO

INTRPT
~OR

IMoo

---------1r-_______

(ROMSR)

6-146

•

tACTIVE

•

VLSI TECHNOLOGY, INC.
VL16C552

RCVR FIFO FIRST BYTE (This sets RDR.)
SIN~

V ---...:l\ DATA(5-8)~
-\~

SAMPLE CLOCK

TRIGGER LEVEL
INTERRUPT
(FCR6, 7=0, 0)

STOP

I I Inl I I I I I I

,1---------...,.,..---

j:-

---------_f_'

(FIFO AT OR ABOVE
TRIGGER LEVEL)
(FIFO BELOW
TRIGGER LEVEL)

tRINT

LSI INTERRUPT _ _ _ _ _ _ _ _ _~

tRINT

(RD~~~ --------------,~--~OR -------------------~I
(RDRBR)

ACTIVE

RCVR FIFO FIRST BYTE (RDR Is already set.)
SIN

SAMPLE CLOCK

I I I I I I I
(FIFO AT OR ABOVE
TRIGGER LEVEL)

TIMEOUT
OR - - - - - i TRIGGER
LEVEL
INTERRUPT

(FIFO BELOW
TRIGGER LEVEL)

Note 2
tSlNT
tRINT

LSI INTERRUPT

-IOR-----t--,.
(RDLSR)

-lOR
,(RDRBR)

ACTIVE

PREVIOUS BYTE
READ FROM FIFO

TRANSMITTER READY (PIN 24)-MODE 0
-lOW
(WRTHR)

SOUT

-TXRDY

Notes: 1. This is the reading of the last byte in the FIFO.
2. If FCRO=1, then tSINT=3 RCLKs. For a trigger change level interrupt, tSINT=8 RCLKs.

6·147

•

VLSI TECHNOLOGY, INC.
VL16C552

TRANSMITTER READY (PIN 24)-MODE 1
-IOW---,
(WRTHR)

SOUT

BYTE #16

DATA

tSXA
-TXRDY

RECEIVER READY (PIN 29)-MODE 0
-lOR
(RORBR)
SIN

(FIRSTBYTE)

------<, r-----~
~

SAMPLE eLK

-RXROY

. t-----+_"

tRXI

Note 2

RECEIVER READY (PIN 29)-MODE 1
-lOR
(RDRBR)

------i,t--------....

ACTIVE
Note 1

SIN
(FIRST BYTE THAT ~
REACHES THE -.J STOP ' - TRIGGER LEVEL)

SAMPLE CLK - - - - ' ' - - - - - ' - - -

-RXRDY

~I .~_____-+--/
~T

tRXI

Note 2

Notes: 1. This is the reading of the last byte in the FIFO.
2. If FCRO= 1, then tSINT=3 RCLKs. For a trigger change level interrupt, tSINT-8 RCLKs.

6-148

•

VLSI TECHNOLOGY, INC.
VL16C552

AC TESTING INPUT/OUTPUT WAVEFORMS
EXTERNAL CLOCK INPUT (8.0 MHz MAXIMUM)

AC TEST POINTS

Note: All timings are referenced to valid 0 and valid 1.

TEST CIRCUIT

Device Under Test

6800

• '''''",,", .......... Jlg "pP
Capacitance

FIGURE 3. BASIC CONFIGURATION
VL16C552

SERIAL
DATA r---------'~
BUS

ADDR
BUS

CTL
BUS

CHANNEL 0
BUFFERS

DUAL
ACE AND
PRINTER
PORT

9-PIN
"D"
CONN

SERIAL
CHANNEL 1
BUFFERS

9-PIN
"D"
CONN

OPTION
JUMPERS
PARALLEL
PORT
RIC NET

6-149

25-PIN

liD"

CONN

•

VLSI TECHNOLOGY, INC.
VL16C552

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

-1 O·C to +70·C

Storage Temperature -65.C to + 150.C
Supply Voltage to
Ground Potential -0.5 V to VDD +0.3 V
Applied Output
Voltage

Stresses above those listed may cause
permanent damage to the device.

~hese are st~ess rati~gs o~ly. Functional operation of thiS deVICe at these
or any other conditions above those

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

-0.5 V to VDD +0.3 V

Applied Input
Voltage

-0.5 V to +7.0 V

Power Dissipation

500 mW

DC CHARACTERISTICS·.

=D·C to +70·C VDD =5 V ±5%

S~mbol

Parameter

Min

VILX

Clock Input Low Voltage

-0.5

0.8

VIHX

Clock Input High Voltage

2.0

VDD

VIL

Input Low Voltage

-0.5

0.8

VIH

Input High Voltage

2.0

VDD

VOL

Output Low Voltage

VOH

Output High Voltage

IDD

Power Supply Current

ilL
ICL

Max

0.4

2.4

Units

Conditions

10L = 4.0 mA on DBO - DB?
10L = 12 mA on PDO - PD?
10L = 10 mA on -INIT, -AFD, -STB,
and -SUN (see Note 1)
10L = 2.0 mA on all other outputs

10H = -0.4 mA on DBO - DB?
10H = -2.0 mA on PDO - PD?
10H = -0.2 mA on -INIT, -AFD, -STB,
and-SUN
10H = -0.2 mA on all other outputs

VDD = 5.25 V. No loads on SINO,I ;
-DSRO,1 ; -DCDO,1 ; -CTSO, 1. -RIO,
-RII = 2.0 V. Other inputs = 0.8 V. Baud
rate generator = 8 MHz. Baud rate = 56K

Input Leakage

±10

!iA

VDD = 5.25 V, GND = 0 V.
All other pins floating.

Clock Leakage

±10·

!iA

VIN = 0 V, 5.25 V

±20

!iA

VDD = 5.25 V, GND = 0 V.
VOUT = 0 V, 5.25 V
1) Chip deselected
2) Chip and write mode selected

0.8

10Z

3-State Leakage

VIL(RES)

Reset Schmitt VIL

VIH(RES)

Reset Schmitt VIH

2.0

6-150

•

VLSI TECHNOLOGY, INC.
VL82C037
IBM VGA®-COMPATIBLE VIDEO GRAPHICS CONTROLLER

FEATURES

DESCRIPTION

• Single-chip VGA video graphics
device that is completely compatible
in the following systems:
-IBM PC/AT-compatible
-IBM PCn1sI''j'i j'1 1

DE REGISTER
.
MO Index __ 4 (ReadlWnte)
MEMORY
=03C5
Address
Reserved
Shift Load

cr:
L..=

71S151413~T =v.~ "'mo~

",Dote""",

Dot Clock
Shift 4

Screen Off
Reserved

6-170

Odd/Even
Chain 4

----_.

Reserved

•

VLSI TECHNOLOGY, INC.
VL82C037

CRT CONTROLLER REGISTERS
CRT CONTROLLER ADDRESS REGISTER
Address
(ReadlWrite)

START HORIZONTAL RETRACE REGISTER
Address =
Index (Read/Write)

03?5 4
17161514131211101

=03?4

17161514131211101

L . . l- - -

CRTC Address
Test Bit

Start Horizontal Retrace

Reserved
END HORIZONTAL RETRACE REGISTER
Address =
Index (Read/Write)

HORIZONTAL TOTAL REGISTER
Address =
Index (ReadlWrite)

03?5 0
17161514131211101
1

03?5 5
17161514131211101

End Horizontal Retrace

Horizontal Retrace Delay
I _
L--________ End Horizontal Blanking, Bit 5

Horizonatal Total Minus 5

1 - 1-

VERTICAL TOTAL REGISTER
Address =
Index (Read/Write)

03?5 6
17161514131211101

HORIZONTAL DISPLAY ENABLE END REGISTER
Address =
Index (ReadlWrite)

03?5 1
17161514131211101

Vertical Total Minus 2

Total Displayed
Characters Minus 1

PRESET ROW SCAN REGISTER
Address =
Index 8 (ReadlWrite)

03?5
17161514131211101

START HORIZONTAL BLANKING REGISTER
Address =
Index (ReadlWrite)

03?5 2
17161514131211101

L . . I-

L -_ _ _ _ _ _ _ _

Starting Row Scan Count
After Vertical Retrace

03?5
17161514131211101

03?5 3
17161514131211101

MAXIMUM SCAN LINE REGISTER
Address =
Index = 9 (ReadlWrite)

END HORIZONTAL BLANKING REGISTER
Address =
Index (ReadlWrite)

1 - 1-

Byte Panning Control
'--_ _ _ _ _ _ _ _ Reserved

Horizontal Blanking Start
Character Count

End Blanking
Display Enable Skew Control
Test Bit

IL--I_I___I____

6-171

~g;;~~:::;oo

•

VLSI TECHNOLOGY, INC.
VL82C037

CRT CONTROLLER REGISTERS (Cont.)

OVERFLOW REGISTER
Address = 031S Index 7 (ReadJWrite)
17161s14131211101

III

V._T.,.m"

Vertical Display Enable End Bit 8
Start Vertical Retrace Bit 8

Start Vertical Blank Bit 8
'--_ _ _ _ _ Line Compare Bit 8
'--_ _ _ _ _ _ Vertical Total Bit 9
'--_ _ _ _ _ _ _ Vertical Display Enable End Bit 9
'--_ _ _ _ _ _ _ _ Start Vertical Retrace Bit 9

CURSOR START REGISTER
Address = 031S Index = A (Read/Write)

11 .

17161514131211101
1 - - - Cursor Start Scan Line
Cursor Off

Reserved

CURSOR END REGISTER
Address =0315 Index = B (ReadJWrite)

CURSOR LOCATION HIGH REGISTER
Address = 031S Index = E (ReadJWrite)

17161s14131211101

..
IT

1 - - - Cursor End Scan Line
_
Cursor Skew Control
'--_ _ _ _ _ _ _ _ Reserved

START ADDRESS HIGH REGISTER
Address =0315 Index =C (ReadJWrite)

CURSOR LOCATION LOW REGISTER
Address = 031S Index = F (ReadJWrite)
17161s14131211101

17161514131211101
1

High Order 8-Bits of
Cursor Location

High Order 8-Bits of
Start Address

Low Order 8-Bits of
Cursor Location

START ADDRESS LOW REGISTER
Address = 031S Index = D (ReadJWrite)

START VERTICAL RETRACE REGISTER
Address = 031SIndex = 10 (Read/Write)

17161s14131211101

Low Order 8-Bits of
Start Address

6-172

Low Order 8-Bits of Vertical
Retrace Start Position

•

VLSI TECHNOLOGY, INC.
VL82C037

CRT CONTROLLER REGISTERS (Cont.)
END VERTICAL RETRACE REGISTER
Address = 03?5 Index = 11 (ReadlWrHe)

TIl

17161514131211101

--I--- Vertical Retrace Pulse Width

0 = Clear Vertical Retrace Interrupt

o =Enable Vertical Retrace Interrupt
Not Used

VERTICAL DISPLAY ENABLE END REGISTER
Address = 03?5 Index = 12 (ReadlWrite)

END VERTICAL BLANKING REGISTER
Address = 03?5 Index = 16 (ReadlWrite)

17161514131211101

Low Order Vertical Display
Enable End Minus 1

OFFSET REGISTER
Address = 03?5lndex

= 13 (ReadlWrite)

CRTC MODE CONTROL REGISTER
Address = 03?5 Index = 17 (ReadlWrite)

17161514131211101

1'-_ _ _ _ Logical Line Width
of the Screen

III LL=~:

ill'

I0 I

Row",",

'--_____ Address Wrap
Scan Line Where Underline Will Occur

' - - - - - - - - - Word/Byte Mode
Hardware Reset

1..._ _ _ _ _ _ _ _

_ _ _ _ _ _ Count by 4
_ _ _ _ _ _ Double Word Mode
_ _ _ _ _ _ Reserved

START VERTICAL BLANKING REGISTER
Address = 03?5 Index = 15 (ReadlWrite)

LINE COMPARE REGISTER
Address = 03?5lndex = 18 (ReadlWrite)

17161514131211101

~"~,

Horizontal Retrace Select
Count by 2
Reserved

UNDERLINE LOCATION REGISTER
Address = 03?5lndex = 14 (ReadlWrite)
171 61 514131211

End Vertical Blanking
Position

Start Vertical Blanking
Position Minus 1

6-173

Line Compare Target

•

VLSI TECHNOLOGY, INC.
VL82C037

GRAPHICS CONTROLLER REGISTERS
GRAPHICS ADDRESS REGISTER
Address = 03CE (ReadlWrlte)

READ MAP SELECT REGISTER
Address =03CF Index =4 (ReadlWrite)

17161514131211101

SET/RESET REGISTER
Address =03CF Index =0 (ReadlWrite)

~ Map Select Bits (See Table 18)

1 - - - Graphics Register Index
Reserved

L..._ _ _ _ _ _

L..._ _ _ _ _ _ _

GRAPHICS MODE REGISTER
Address = 03CF Index = 5 (ReadIWrite)
17161514131211101

III

17161514131211101

III L

.... '
~ SO""oooo
Set/Reset Map 1

W,HeMode_T_19j
Reserved
Read Type

Set/Reset Map 2
Set/Reset Map 3
'--_ _ _ _ _ _ Reserved

l..-_ _ _ _ _ _
L...-_ _ _ _ _ _ _
L...-_ _ _ _ _ _ _ _

ENABLE SET/RESET REGISTER
Address =03CF Index = 1 (ReadlWrite)
17161514131211101

III L

17161514131211101

E . - ."'"..., Mop ,

Enable Set/Reset Map 1

Enable Set/Reset Map 3
Reserved

COLOR COMPARE REGISTER
Address =03CF Index =2 (ReadlWrite)

L..._ _ _ _ _ _

Col"

C'",,~ Mop'

L..
________

~L Map 0 =Don't Care
~

Map 1 • Don't Care
Map 2 = Don't Care
Map 3 = Don't Care
'--_ _ _ _ _ _ Reserved

Color Compare Map 3
Reserved

BIT MASK REGISTER
Address =03CF Index =8 (ReadlWrite)
17161514131211101

17161514131211101

Odd/Even
Memory Map Select (See Table 20)
Reserved

Color Compare Map 1

DATA ROTATE REGISTER
Address =03CF Index =3 (ReadlWrite)

G,._ ....,

COLOR DON'T CARE REGISTER
Address = 03CF Index 7 (ReadlWrlte)

Color Compare Map 2
L...-_ _ _ _ _ _

[I I

17161514131211101

III L

OddlEven
Shift Register Mode
256 Color Mode
Reserved

MISCELLANEOUS REGISTER
Address = 03CF Index = 6 (ReadlWrite)

Enable Set/Reset Map 2
L...-_ _ _ _ _ _

Reserved

Rotate Count

....
1 - - - - - 8-Bit Data Mask

Function Select (See Table 16)
Reserved

6-174

•

VLSI TECHNOLOGY, INC.
VL82C037

ATTRIBUTE CONTROLLER REGISTERS
ATTRIBUTE ADDRESS REGISTER
Address =03CO (ReadlWrite)

HORIZONTAL PEL PANNING REGISTER
Address = 03CO (Write), 03C1 (Read) Index = 13

17161514131211101

1 - - - Attribute Register Index
Palette Address Source

L l- - -

L.._ _ _ _ _ _ _

Video Data Shift Count
Reserved

Reserved

PALETTE REGISTER
Address =03CO (Write), 03C1 (Read) Index =O-F

COLOR SELECT REGISTER
Address =03CO (Write), 03C1 (Read) Index

1716151413121110\

LI- - - -

17161514131211101

Color Register Address
Reserved

III LCOO'~~4
~

\7\6\5\4\3\211\0\

G'....;aAl'han""'"rio Mode

Mono Emulation
Enable Line Graphics Character Code
Select Background Intensity
or Enable Blink

'--_ _ _ _ _ Reserved
'--_ _ _ _ _ _ PEL Panning Compatibility
'--_ _ _ _ _ _ _ PEL Width
'--_ _ _ _ _ _ _ _ PS/P4 Select

OVERSCAN COLOR REGISTER
Address = 03CO (Write), 03C1 (Read) Index = 11
17161514131211101
1

Border Color Palette Index

COLOR PLANE ENABLE REGISTER
Address = 03CO (Write), 03C1 (Read) Index = 12
17161s14131211101

-~ -~ III I

EM1*>

Color Select Bit 5

Color Select Bit 6
Color Select Bit 7
'--_ _ _ _ _ _ Reserved

ATTRIBUTE MODE CONTROL REGISTER
Address = 03CO (Write), 03C1 (Read) Index = 10

III I

= 14

Co,,, '''"'' 0

Enable Color Plane 1
Enable Color Plane 2

Enable Color Plane 3
'--_ _ _ _ _ Video Status MUX (See Table 22)
'--_ _ _ _ _ _ _ Reserved

6-175

•

VLSI TECHNOLOGY, INC.
VL82C037

EXTENDED REGISTERS
EXTENSION ADDRESS REGISTER
Address =03DE (ReadIWrite)

17161514131211101

1 - - - Extension Register Index
Reserved

BANDWIDTH CONTROL REGISTER
Address =03DF Index =D (ReadIWrite)

17161514131211101

Reserved
Bandwidth Control (See Table 25)
Clock Select Bit 2 (See Table 5)
'--_ _ _ _ _ _ _ Reserved
L . . ._ _ _ _ _ _

1/0 TRAP CONTROL REGISTER
Address =03DF Index = E (Read/write)

17/61514131211101

., Enable VO Trap Interrupt
Backward Compatibility Mode (See Table 26)
'--_ _ _ _ _ Reserved

'--_ _ _ _ _ _ _ _ Graphics Latch Read Compatibility

NMI DATA CACHE REGISTER
Address =03DF Index =F (Read Only)
17/61514131211101
1

AddresslData from Trapped I/O

DIP SWITCH READ REGISTER
Address =03DF Index = 10 (Read Only)
17/61514131211101
1

Dip Switch Data

6-176

•

VLSI TECHNOLOGY, INC.
VL82C037

AC CHARACTERISTICS: TA = o·c to +70·C, VCC = 5 V ±5%, GND = 0 V
110 READIWRITE, DAC READIWRITE, SWITCH READ (See Figures 1, 2, 8, 9 & 10.)
Min

Max

Address Setup Time

ASEL Setup Time

200
20

Read Data Valid Delay

120

Read Data Hold Time

Min

Max

Units

Symbol

Parameter

tSU1
tSU2
tH3

Address Hold Time

tH4

ASEL Hold Time

Command Pulse Width

tD6

Write Data Delay

tH7

Write Data Hold Time

tDS

-EDBUF and -EABUF Delay

109
tH10
tD11

Read to DIR Delay

1012

Read to DAC Read Delay

tD13

Write to DAC Write Delay

tD14

Read to Switch Read Delay

Units

Conditions

Note

Note: 200 ns when VCLKO = 25 MHz; otherwise, three clocks +SO ns.

MEMORY READIWRITE (See Figures 3 & 4.)
Symbol

Parameter

tSU15

Address Setup Time

tSU16

ASEL Setup Time

tH17

Address Hold Time

tH1S

ASEL Hold Time

1019

Write Data Delay

tH20

Write Data Hold Time

1021

-EDBUF and -EABUF Delay

tD22

Read to DIR Delay

tD23

Command to CPURDY Low Delay

tH25

Valid RD Data Hold lime

6-177

Conditions

•

VLSI TECHNOLOGY, INC.
VL82C037

AC CHARACTERISTICS

(Cont.)

DRAM READ/WRITE (See Figures 6 & 7.)
Symbol

Parameter

Max

Min

Units

3(tClK)
10

tSU26

Row Address Setup

tH27

Row Address Hold Time

128

-RAS low Time

4(tClK)-10

t29

-RAS High Time

tSU30

Column Address Setup Time

.5(tClK)-2

tH31

Column Address Hold Time

tClK

t32

-CAS low lime

4.5(tClK) -10

t33

-CAS High Time

2.5(tClK) -10

tD34

-RAS to -OE Delay

2.5(tClK) -10

tD35

-RAS to -WE Delay

2.5(tClK) -10

tD36

-WE to -RAS High

tClK

tD37

-RAS to -CAS Reference

1.5(tClK) -10

tClK

Min

Max

Units

tSU38

Data to -WE Setup Time

tH39

Data to -WE Hold lime

Conditions

ns
ns

CLOCK AND VIDEO (See Figure 5.)
Symbol

Parameter

tClK

ClKIN Cycle

tD40

PO-P7 Delay

-BLANK Delay

tD41

tD42

HSYNCNSYNC Delay

tD43

ClKIN to PClK Delay

6-178

Conditions

•

VLSI TECHNOLOGY, INC.
VL82C037

TIMING DIAGRAMS
FIGURE 1. 1/0 READ TIMING

tSU1

ADDRESS

ASEL _ _ _ __

-lORD

RD DATA

=-______+______

-EDBUF

-EABUF

-------=.r-toi~

DIR

-------i-=-:--:-

FIGURE 2. 1/0 WRITE TIMING

ADDRESS

ASEL _ _ _ _.,

-IOWR

WR DATA

--------r--

-EDBUF

-EABUF

------4;!ma-

6·179

•

VLSI TECHNOLOGY, INC.
VL82C037

FIGURE 3. MEMORY READ TIMING

tSU15
ADDRESS

ASEL

-VMRD

RDDATA

-EDBUF
-EABUF

CPURDY

DIR -------~~

FIGURE 4. MEMORY WRITE TIMING

ADDRESS

ASEL

-VMWR

WR DATA

=------t----~

-EDBUF
-EABUF _ _ _ _ _ _ _,

CPURDY

6-180

•

VLSI TECHNOLOGY, INC.
VL82C037

FIGURE 5. CLOCK AND VIDEO TIMING
tClK
ClKIN

7 f-

7 f~tD40~

P7-PO

lX
I4--tD41 ~

-BLANK
~1042~

HlVSYNC

IX
H.tD43

PClK

-7f

FIGURE 6. DRAM READ TIMING

MD31-MDO

----11\

COlADDR

READ DATA

11\
tH27-

tSU26
-RASO-RAS3

ROW AD DR

128

r
tS37

-CAS

-OE

~tSU30" 4tH31 ..

129

133

132
.,-

-7f

------------------------~------~/r----------------134

FIGURE 7. DRAM WRITE TIMING

MD31-MDO

ROW ADDRESS

COL ADDRESS

WRITE DATA

tH27_

tSU26

t28
-RASO-RAS3

tH31 ____

~tSU30

129
-,

t037
t33

tD36

t32

-CAS

....

tH39
~

-WE
6-181

-1

~tSU38

1035

•

VLSI TECHNOLOGY, INC.
VL82C037

FIGURE 8. DAC READ llMING
tSU1
ADDRESS

ASEL _ _ _---;
tH4
-lORD

-DACR

-EDBUF

-EABUF

-------=;ltOa~

DIR

------ir:::-:-

FIGURE 9. DAC WRITE llMING

ADDRESS

ASEL

1 4 - - - - - 15 - - - - " ' l
-IOWR

-DACW

-EDBUF

-EABUF

------~;r_IDs

6·182

_______

•

VLSI TECHNOLOGY, INC.
VL82C037

FIGURE 10. SWITCH READ TIMING

ADDRESS

ASEL _ _ _--;
tH4
-lORD

-SWTR

-EDBUF

-EABUF

-------=it-IDa

DIR

-------r~~

6·183

VLSI TECHNOLOGY, INC.
VL82C037
ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

O·C to +70·C

Storage Temperature

-40·C to + 125·C

Supply Voltage to
Ground Potential -0.5 V to VCC +6.0 V
Applied Input
Voltage

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

-0.5 V to VCC +0.5 V

± 20 mA

DC Input Current

300·C

Lead Temperature

DC CHARACTERISTICS: TA = o·e to +7o·e, vee = 5 V±5%, GND = 0 V
Symbol
Parameter
Min
Max
VIH

Units

Conditions

Input High Voltage

2.0

VCC

VCC-5.25 V

VIL

Input Low Voltage

-0.5

0.8

VCC = 5.25 V

VOH

Output High Voltage

2.4

IOH (See Note 2)

VOL

Output Low Voltage

0.4

IOL (See Note 1)

liN

Input Leakage Current

-10

IJ.A

VIN - VCC/GND

IOZ

3-State Output Leakage Current

-10

VOUT = VCC/GND

100

100 Dynamic Current

rnA

VCC =5.25 V

Note 1: 2 mA Output Pads:

-EABUF, -EDBUF, DIR, -CRTINT, -NMI, CPU ROY, -SWTR,
HSYNC, VSYNC, -BLANK, -DACR, -DACW, PCLK
P7-PO, DA7-DAO, MD31-MDO.
4 mA Output Pads:
-RASO-RAS3, -WE
8 mA Output Pads:
12 mA Output Pads: -OE
20 mA Output Pads: -CAS

Note 2: -200

Output Pads: -EABUF, -EDBUF, DIR, -CRTINT, -NMI, CPURDY, -SWTR,
HSYNC, VSYNC, -BLANK, -DACR, -DACW, P7-PO, DA7-DAO,
MD31-MDO, PCLK
-1 mA Output Pads: -RASO, -RAS1, -RAS2, -RAS3, -WE
-3.3 mA Output Pads:-OE, -CAS

6-184

•

VLSI TECHNOLOGY, INC.
VL82C106
PCIAT COMBO 110 CHIP

FEATURES
Combines the following PC/A-p'!>
Peripheral Chips:
COM1:
VL 16C450 UART
VL 16C450 UART
- COM2:
Parallel Printer Port
LPT1:
Keyboard/Mouse Ctrl. - KBD
Real Time Clock
Serial ports fully 16C450 compatible
Bidirectional line printer port
• Software control of PS/2<11>-compatible
enhancements (LPT Port, Mouse)
CMOS direct drive of Centronics-type
parallel interface
• PC/AT- or PS/2-compatible keyboard
and mouse controller
• 146818A-compatible Real Time
Clock (RTC)
• 16 bytes of additional standby RAM
(66 bytes total)
• IDE bus control signals included (two
external 74LS245 and one 74ALS244
- or equivalent - buffers are required)
Seven battery-backed programmable
chip select registers for auto configuration
• Preprogrammed default chip selects

• Programmable wait state generation
• 5!lA standby current for RTC, RAM,
and chip select registers
• Single 128-pin plastic quad flatpack

DESCRIPTION
The VL82C106 Combo chip replaces
with a single 128-pin chip, several of
the commonly used peripherals found in
PC/AT-compatible computers. This
chip when used with the VLSI PC/ATcompatible chip set allows designers to
implement a very cost effective,
minimum chip count motherboard
containing functions that are common to
virtually all PCs.
The on-chip UARTs are completely
software compatible with the VL 16C450
ACE.
The bidirectional parallel port provides a
PS/2 software compatible interface
between a Centronics-type printer and
the VL82C106. Direct drive is provided
so that all that is necessary to interface
to the line printer port is a resistor capacitor network. The bidirectional
feature (option) is software programmable for backwards PC/AT-compatibility.

ORDER INFORMATION
Part
Number

Package

VL82C106-FC

Plastic Quad Flatpack

The keyboard/mouse controller is
selectable as PC/AT- or PS/2-compatible.
The Real Time Clock is 146818Acompatible and offers a standby current
drain of 5 !lA at 3.0 V.
Included is the control logic necessary
for the support of the Integrated Drive
Electronics (IDE) hard disk bus interface.
The Combo 110 chip also includes
seven programmable chip selects, three
internal and four external. Each chip
select has a programmable 16-bit base
address and a mask register that allows
the number of bytes corresponding to
each chip select to be programmed
(e.g. 3F8H-3FFH has a base address
of 3F8H and a range of 8 bytes). Each
chip select can be programmed for
number of wait states (0-7) and 8- or
16-bit operation. 16-bit decoding is
used for all 110 addresses. A default
fixed decode is provided on reset for
the on-chip serial ports, printer port, and
off-chip floppy and hard disk controllers,
which may be changed to batterybacked programmable chip selects via
a control bit.

INTERNAL FUNCTIONAL DIAGRAM
VL16C450
ASYNCHRONOUS
COMMUNICATIONS
ELEMENT

PARALLEL
PRINTER
PORT

Note: Operating temperature range is O·C to +70·C.
VL16C450
ASYNCHRONOUS
COMMUNICATIONS
ELEMENT

REAL
TIME
CLOCK

SCRATCHPAD
RAM

PROGRAMMABLE
CHIP SELECTS

INTEGRATED
DRIVE
ELECTRONICS
INTERFACE

KEYBOARD/
MOUSE
CONTROLLER

PC/A-p'!> and PS/2<11> is the registered trademark of IBM Corporation.
6-185

•

VLSI TECHNOLOGY, INC.
VL82C106

BLOCK DIAGRAM

KCM
KKSW
KRSEL

KIO
Kll
KI2
KI3
KI5

AEN

-00

--001

RTCMAP
SAO-SA15

VBAT
-8TBy
32.768 KHz

rlWl

PSI-RC

DOWN
WRITE
PRO.E9T

SOO-SO 7

-lOR
RES
ALE

PORT
ADDRESS
DECODE

TEST
LOGIC

-TRI
-ICT

-CTSA
-DSRA
-DCDA
-AlA
SINA

.r.c~
-+I

f--'

WAITSTATE'1
GENERATOR

EXTENDED
MODE

....
....

1.8432 MHz

VLI8C452B
DUALUART
II
PARALLEL
PRINTER PORT

IDE_EN

6-186

S
r--

L
-'
--I

Xl:AL 118.432 MHz
Xl:AL2

XDIRS
XDIRX

-XDEN
IOCHRDY
-IOCS16
-ATSA
-DTRA
SOUTA
-DUT2A
IRCA

-ATSB
-DTRB
SOUTB

-OUT2B
lAOS
-INIT
-AFD

-8TB
-$lIN
IROP,-IROE
PD()'PD7

-HCSI
-IDENH
-IDENL

IDE LOGIC

U-t-

....

-ERR
SLCT
BUSY

IDINT
-DC

~l ....
r-r-

--....

-r-

XDATA

-CTSB
-DSRB
-DCDB
-AlB
SINB

PJ ~

DIVIDERS

esc

6.144
MHz

-CS4
r---

SELECT
DEFAULT
DECOD~

SYSCLK

-ACK

-CS4
-CS5 .
-CS6,-CS7

pciiiT,

=r 1

IROR

'--

r-Ir- CHIP
CHIP SELECT
REGISTERS

V1.82CDI8A REAL
liME CLOCK

PS/2
EXT.
MODE

KA20
KRES
KHSE
KSRE
IRQK
IROM

........

--L

16 BYTE
SeRATCHPAD RAM

....

....,

RTe EXTENDED
REGISTER DECODE

CONTROL REGISTERS

-10W

xcDIR
-CDAK4

PC/AT, PS/2
MOOE

KCLK
KDAT

r
Yl.82C042
KEYBOARD.t.IOUSE
CONTROlLER

IRQI
IDB7

•

VLSI TECHNOLOGY, INC.
VL82C106

PIN DIAGRAM
VL82C106
-ICT

RES

VDD

S02

SD4

VSS

S07

KID

KI2

128127126 125124 123 122 121120 119118 117116115114113112 111 110109 108107 106105 104103 102101 100 99 98

•

VSS
-IDENH
-IDENL

KI3
KI5
KRSEL

-XOEN

KKSW
KCM

XOIRS
XOIRX

KA20

-CS4

KRES

-CS5

-CTSB

-CS6

-OSRB

-CS7

-DCOB

-lOR

-RIB

-lOW

SINS

AEN

VSS

TOP VIEW

ALE

XTAl2

VOO

XTAl1

VOO

SAO

VSS

SA1

-CTSA

SA2

-OSRA

SA3

-OCOA

-RIA

SINA

-ACK

SA7

SA8

BUSY

SA9

$lCT

SA10

-ERR

SA11

VBAT

SA12

PSI-RC

SA13
SA14

oseo
osel

SA15

-sTBY

IRQK

IRQR

VSS

IROP

PD6

6-187

PD4

P03

P01

VSS

-AFO

-sLIN

•

VLSI TECHNOLOGY, INC.
VL82C106

SIGNAL DESCRIPTIONS
Signal
Type

Signal
Description

COMMUNICATIONS PORT A
-RTSA
44

Request to Send, Port A

-DTRA

Data Terminal Ready, Port A

SOUTA

Serial Data Output, Port A

-CTSA

Clear to Send, Port A

-DSRA

Data Set Ready, Port A

-DCDA

Data Carrier Detect, Port A

-RIA

Ring Indicator, Port A

SINA

Serial Input, Port A

IROA

Interrupt Request, Port A

-OUT2A

Output 2, Port A

COMMUNICATIONS PORT B
-RTSB
47

Request to Send, Port B

-DTRB

Data Terminal Ready, Port B

SOUTB

Serial Data Output, Port B

-CTSB

Clear to Send, Port B

-DSRB

Data Set Ready, Port B

-DCDB

Data Carrier Detect, Port B

-RIB

Ring Indicator, Port B

SINB

Serial Input, Port B

IROB

Interrupt Request, Port B

-OUT2B

Signal
Name

Pin
Number

Output 2, Port B

PARALLEL PRINTER PORT
PDO
59

105

Printer Data Port, Bit 0

PD1

105

Printer Data Port, Bit 1

PD2

105

Printer Data Port, Bit 2

PD3

105

Printer Data Port, Bit 3

PD4

105

Printer Data Port, Bit 4

PD5

105

Printer Data Port, Bit 5

PD6

105

Printer Data Port, Bit 6

PD7

105

Printer Data Port, Bit 7

-IN IT

Initialize Printer Signal

-AFD

Autofeed Printer Signal

-STB

Data Strobe to Printer

-SUN

Select Signal to Printer

-ERR

Error Signal from Printer

SLCT

Select Signal from Printer

6-188

•

VLSI TECHNOLOGY, INC.
VL82C106

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Type

Signal
Description

BUSY

Busy Signal from Printer

Paper Error Signal from Printer

-ACK

Acknowledge Signal from Printer

IROP

Printer Interrupt Request Output

-IROE

Printer Interrupt Request Enabled Signal

REAL TIME CLOCK PORT
VBAT
69

Standby Power - Normally 3 V to 5 V, battery backed.

-STBY

Power Down Control

OSCI

Crystal Connection Input - 32 KHz

OSCO

Crystal Connection Output - 32 KHz

PS/-RC

Power SenselRAM Clear Input

IROR

Real Time Clock Interrupt Request Output

RTCMAP

121

High - RTC is mapped to 70H and 71 H, low - RTC is mapped to 170H and
171H.

KEYBOARD CONTROLLER PORT
103
104
KClK

Keyboard Clock

KDAT

104

Keyboard Data

KCM

General purpose input, normally color/monochrome.

KKSW

General purpose input, normally keyboard switch.

KA20

General purpose output, normally A20 Gate.

KRES

General purpose output, normally reset.

KHSE

101

011104

General purpose input, normally speed select.

KSRE

100

011104

General purpose output, normally shadow RAM enable.

IROK

Keyboard Interrupt Request

IROM

Mouse Interrupt Request

KRSEl

General purpose input, normally RAM select.

KIO

General purpose input, bit o.

Kll

General purpose input, bit 1.

KI2

General purpose input, bit 2.

KI3

General purpose input, bit 3.

KI5

General purpose input, bit 5.

IDE BUS 110
-IDENH

IDE Bus Transceiver High Byte Enable

-IDENl

IDE Bus Transceiver low Byte Enable

IDINT

122

IDE Bus Interrupt Request Input

IDB7

119

106

IDE Bus Data Bit 7

-DC

123

Floppy Disk Change Signal

-HCSl

124

IDE Host Chip Select 1

-IROI

IDE Interrupt Request Output
6-189

[II

•

VLSI TECHNOLOGY, INC.
VL82C106

SIGNAL DESCRIPTIONS
Signal
Name

Signal
Type

Signal
Description

COMMON BUS 110
115
SDO

102

System Bus Data, Bit 0

114

102

System Bus Data, Bit 1

SD1

Pin
Number

SD2

111

102

System Bus Data, Bit 2

SD3

110

102

System Bus Data, Bit 3

SD4

109

102

System Bus Data, Bit 4

SD5

108

102

System Bus Data, Bit 5

SD6

106

102

System Bus Data, Bit 6

SD7

105

102

System Bus Data, Bit 7

SAO

System Bus Address, Bit 0

SA1

System Bus Address, Bit 1

SA2

System Bus Address, Bit 2

SA3

System Bus Address, Bit 3

System Bus Address, Bit 4

SA5

System Bus Address, Bit 5

SA6

System Bus Address, Bit 6

SA7

System Bus Address, Bit 7

SA8

System Bus Address, Bit 8

SA9

System Bus Address, Bit 9

SA10

System Bus Address, Bit 10

SA11

System Bus Address, Bit 11

SA12

System Bus Address, Bit 12

SA13

System Bus Address, Bit 13

SA14

System Bus Address, Bit 14

SA15

System Bus Address, Bit 15

XTAL1

Crystal/Clock Input - 18.432 MHz

XTAL2

Cystal/Clock Output - 18.432 MHz

-lOR

System Bus 110 Read

-lOW

System Bus 110 Write

RES

125

System Reset

AEN

System Bus Address Enable

ALE

System Bus Address Latch Enable

-IOCS16

116

System Bus 110 Chip Select 16
System Bus 110 Channel Ready

lOCH ROY

118

SYSCLK

128

System Clock - Processor clock divide by 2.

-CS4

Chip Select 4 - Normally for external floppy disk controller.

-CS5

Chip Select 5 - Normally -HCSO for IDE.

6-190

•

VLSI TECHNOLOGY, INC.
VL82C106

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Type

Signal
Description

-CS6

Chip Select 6 - Normally for external floppy disk controller.

-CS7

Chip Select 7 - Normally for external floppy disk controller.

-CDAK4

102

DMA Acknowledge forces -CS4 active.

XDDIR

120

X Data Bus Transceiver Direction

XDIRS

Modified X Data Bus Transceiver Direction Control Signal - Excludes real
time clock and keyboard controller decodes.

XDIRX

X Data Bus Transceiver Control Signal - Includes all CS decodes generated on chip.

-XDEN

X Data Bus Transceiver Enable

-TRI

126

Three-state Control Input - For all outputs to isolate chip for board tests.

-ICT

127

In Circuit Test Mode Control

POWER, GROUND, & UNCOMMITTED
VDD
15,16,50,
81,113
1,38,55,
60,80,84,
107,112,117

VSS

System Power: +5 V
System Ground

1/0 LEGEND
mA

Type

Comment

TTL

TTL-OD

Open drain, weak pull-up, no VDD diode

TTL-TS

Three-State

TTL-TS

Three-State

TTL-OD

Open drain, fast active pull-up

TTL

CMOS

TTL

30k n pull-up

TTL

Schmitt-trigger

102

TTL-TS

Three-State

104

TTL-OD

Open drain, slow turn-on

105

TTL-TS

Three-State

106

TTL-TS

Three-State, 30k n pull-up

6-191

•

VLSI TECHNOLOGY, INC.
VL82C106

FUNCTIONAL DESCRIPTION
Below is a detailed explanation of each
of the major building blocks of the
VL82Cl06 Combo chip. The following
functional blocks are covered:
• 16C450 Serial Ports
• Parallel Printer Port
• 146818A-Compatible Real Time
Clock
• Keyboard Controller
• Control and Chip Selects
IDE Interface
SERIAL COMMUNICATIONS PORTS
The chip contains two UARTs, based
on the VL16C450 Megacell core. Each
of these UARTs share a common baudrate clock, which is the XTAL1 input
(18.432 MHz) divided by ten. The
18.432 MHz signal is shared with the
keyboard controller, which divides it by
three to get an approximate 6 MHz
reference clock. Please refer to the
VL 16C452B data sheet for the register
descriptions and timing parameters for
the UARTs.

Port. Write operations immediately
output data to the LPT Port.
Extended Mode (-EMODE bit = 0) Read operations return either the data
last written to the LPT Data Register if
the Direction Bit is set to output ("0") or
the data that is present on the pins of
the LPT Port if the direction is set to
input ("1"). Write operations latch data
into the output register, but only drive
the LPT Port when the Direction Bit is
set to output.
In either case, the bits of the LPT Data
Register are defined as follows:

Bit

Description

Data Bit 0

Data Bit 1

Data Bit 2

Data Bit 3

COMA is accessed via internally generated CS1, while COMB uses internally
generated CS2.

Data Bit 4

Data Bit 5

LINE PRINTER PORT
The Line Printer Port contains the
functionality of the port included in the
VL 16C452B, but offers a software
programmable Extended Mode, which
include a Direction Control Bit and
Interrupt Status Bit. These features are
disabled on initial power-up, but may be
turned on by clearing the -EMODE bit
of Control Register 0 (RTC Register
69H in AT or PS/2 mode or
PORT
102H in PS/2 mode). When the
-EMODE bit is set, the part functions
exactly as a PC/AT-compatible printer
port.

Data Bit 6

Data Bit 7

Register 1 - LPT Port Status
The LPT Status Register is a read-only
register that contains interrupt status
and real time status of the LPT connector pins. The bits are described as
. follows:

The Line Printer Port is accessed via
internally generated programmable chip
select CS3.
Register 0 - Line Printer Port Data
The Line Printer (LPT) Port is either unior bidirectional, depending on the state
of the Extended Mode and Data
Direction Control bits.
Compatibility Mode (-EMODE bit - 1) Read operations to this register return
the last data that was written to the LPT

Bit

Description

Reserved

-IRQ

-ERROR

SLCT

-ACK

-BUSY

Bits 0 and 1 - Reserved, read as "l's".

6-192

Bit 2 - Interrupt Status bit, a "0" indicates that the printer has acknowledged
the previous transfer with a ACK
handshake (bit 4 of the control register
must be set to "1").
When in AT mode, bit 1 RTC Register
6AH - 1, the IRQP output follows the
-ACK input if enabled. When in PS/2
mode, IRQP is set during the inactive
transition of the -ACK signal, and
cleared following a read of the LPT
status register.
Bit 3 - Error Status bit, a "0" indicates
that the printer has had an error. A "1"
indicates normal operation. This bit
follows the state of the -ERR pin.
Bit 4 - Select Status bit, indicates the
current status of the SLCT signal from
the printer. A "0" indicates the printer is
currently not selected (off-line). A "1"
means the printer is currently selected.
Bit 5 - Paper Empty Status bit, a "0"
indicates normal operation. A "1"
indicates that the printer is currently out
of paper. This bit follows the state of
the PE pin.
Bit 6 - Acknowledge Status bit, a "0"
indicates that the printer has received a
character and is ready to accept
another. A "1" indicates that the last
operation to the printer has not been
completed yet. This bit follows the state
of the -ACK pin.
Bit 7 - Busy Status bit, a"O indicates
that the printer is busy and cannot
receive data. A "1" indicates that the
printer is ready to accept data. This bit
is the inversion of the BUSY pin.
Register 2 - LPT Port Control
This port is a read/write port that is
used to control the LPT direction as well
as the Printer Control lines driven from
the port. Write operations set or reset
these bits, while read operations return
the status of the last write operation to
this register (except for bit 5 which is
write only and is always read back as a
"1"). The bits in this register are
defined as follows:
Bit 0 - Printer Strobe Control bit, when
set ("1") the STROBE signal is asserted
on the LPT interface, causing the

•

VLSI TECHNOLOGY, INC.
VL82C106
Bit

Description

STROBE

AUTO FDXT

-INIT

SLCTIN

IRQ EN

DIR (Write Only)

Reserved

printer to latch the current data. When
reset ("0") the signal is negated.
Bit 1 - Auto Feed Control bit, when set
("1") the AUTO FD XT signal will be
asserted on the LPT interface, causing
the printer to automatically generate a
line feed at the end of each line. When
reset ("0") the signal is negated.
Bit 2 - Initialize Printer Control bit, when
set ("1") the signal is negated. When
reset ("0") the INIT signal is asserted to
the printer, forcing a reset.
Bit 3 - Select Input Control bit, when set
("1") the SLCT IN signal is asserted,
causing the printer to go "on-line".
When reset ("0") the signal is negated.
Bit 4 - Interrupt Request Enable Control
bit, when set ("1") enables interrupts
from the LPT Port whenever the -ACK
signal is asserted by the printer. When
reset ("0") interrupts are disabled.
Bit 5 - When EMODE = 1, Direction
(D IR) Control bit, when set ("1") the
output buffers in the LPT Port are
disabled, allowing data driven from
external sources to be read from the
LPT Port. When reset ("0"), the output
buffers are enabled, forcing the LPT
pins to drive the LPT pins. The poweron-reset value of this is cleared ("0").
When -EMODE = 1, this write only bit
has no effect and should be read as "1".
Bits 6 and 7 - Reserved, read as "1's".
REAL TIME CLOCK
The Real Time Clock (RTC) is the
equivalent of the Motorola MC146818A
Real lime Clock component. It is also
compatible with the Dallas Semiconductor DS1287A RTC when an external

battery and crystal are provided. Clock
functions include the following:
•
•
•
•

Time of Day Clock
Alarm Function
100 Year Calendar Function
Programmable Periodic Interrupt
Output
• Programmable Square Wave Output
• 50 Bytes of User RAM
User RAM Preset Feature
RTC PROGRAMMERS MODEL
The RTC memory consists of ten RAM
bytes which contain the time, calendar,
and alarm data, four control and status
bytes, and 50 general purpose RAM
bytes. The address map of the real
time clock is shown below.
Add.

Function

Range

00-09

Time Regs.

0-99

RTC Register A

(R/W)

RTC Register B

(R/W)

RTC Register C

(RO)

RTC Register D

(RO)

OE-3F

User RAM
(Standby)

All 64 bytes are directly readable and
writable by the processor program
except for the following:
1) Registers C and 0 are read only.
2) Bit 7 of Register A is read only.
The RTC is normally accessed via
internally decoded PORT 070H (RTC
register address) and PORT 071 H
(RTC data readtwrite).
The RTC address and data ports can
be moved to Port 170H, Port 171 H by
pulling the RTCMAP pin (121) to
ground. This pin can be left not connected or tied high for normal port
addressing.
The RTC address map also includes
additional standby RAM, plus control
registers for Combo chip configuration
and chip select control. The RAM and
Chip Select control registers are
powered via the VBAT power supply for

6-193

battery-backed operation.
Add. (HEX)

Function

OO-OD

Time Portion of RTC

OE-3F

RAM Portion of RTC

40-4F

Additional Standby RAM

50-68

Reserved

69-7F

Chip Select/Control
Registers

The total address map is shown below:
The processor program obtains time
and calendar information by reading the
appropriate locations. The program
may initialize the time, calendar, and
alarm by writing to these RAM locations. The contents of the ten time,
calendar, and alarm bytes may be
either binary or binary-coded decimal
(BCD).
Time of Day Register
The contents of the Time of Day
registers can be either in Binary or BCD
format. They are relatively straightforward, but are detailed here for
Add.
0

Function

Range

Seconds (Time)

0-59

Seconds (Alarm)

0-59

Minutes (Time)

0-59

Minutes (Alarm)

0-59

Hours (Time)

1-12,
12 Hr
Mode

Hours (Time)

0-23,
24Hr
Mode

Hours (Alarm)

0-23

Day of Week

1-7

Date of Month

1-31

Month

1-12

Year

0-99

•

VLSI TECHNOLOGY, INC.
VL82C106

completeness. The address map of
these registers is shown next:
Address 0 - Seconds (Time): The
range of this register is 0-59 in BCD
mode, and D-3BH in Binary mode.
Address 1 - Seconds (Alarm): The
range of this register is 0-59 in BCD
mode, and D-3BH in Binary mode.
Address 2 - Minutes (Time): The range
of this register is 0-59 in BCD mode,
and 0-3BH in Binary mode.
Address 3 - Minutes (Alarm): The
range of this register is 0-59 in BCD
mode, and 0-3BH in Binary mode.

RTC CONTROL REGISTER
The RTC has four registers which are
accessible to the processor program.
The four registers are also fully accessible during the update cycle.

3.90625

7.8125

Function

Type

RTC Register A

RIW

122.070

f1S

RIW

244.141

f1S

488.281

f1S

976.562

f1S

1.953125

3.90625

7.8125

OB
OC
00
OE-3F

RTC Register B
RTC Register C
RTC Register 0
User RAM (Standby)

RIW

1-12

BCD

81-92

BCD

01H-OCH

Binary

RegIster A
This register contains control bits for the
selection of Periodic Interrupt, Input
Divisor, and the Update In Progress
Status bit. The bits in the register are
defined as follows:

81H-8CH

Binary

Bit

DescriptIon

Abbr.

Rate Select Bit 0

Rate Select Bit 1

OAH

15.625

OBH

31.25

OCH

62.5

ODH

125

RSO

OEH

250

RSl

OFH

500

Range

Mode

Time

Rate Select Bit 2

RS2

1-12

BCD

Rate Select Bit 3

RS3

81-92

BCD

Divisor Bit 0

DVO

01H-OCH

Binary

Divisor Bit 1

DVl

81H-8CH

Binary

Divisor Bit 2

DV2

Update In Progress

UIP

Address 8 - Month: The range of this
register is 1-12 in BCD mode, and 1OCH in Binary mode.

None

Time

Address 7 - Date: The range of this
register is 1-31 in BCD mode, and 11FH in Binary mode.

Add.

Mode

Address 5 - Hours (Alarm): The range
of this register is:
Address 6 - Day of Week: The range of
this register is 1-7 in BCD mode, and 17H in Binary mode.

Periodic Interrupt
Rate

Range

Address 4 - Hours (Time): The range of
this register is:

RS
Value

Bits 0 to 3 - The four rate selection bits
(RSO to RS3) select one of 15 taps on
the 22-stage divider, or disable the
divider output. The tap selected may
be used to generate a periodic interrupt.
These four bits are readlwrite bits which
are not affected by RESET. The
Periodic Interrupt Rate that results from
the selection of various tap values is as
follows:

Bits 4 to 6 - The three Divisor Selection
bits (DVO to DV2) are fixed to provide
for only a five-state divider chain, which
would be used with a 32 KHz external
crystal. Only bit 6 of this register can
be changed allowing control of the reset
for the divisor chain. When the divider
reset is removed, the first update cycle
begins one-haH second later. These
bits are not affected by power-on reset
(external pin).
DV
Value

Condition

Operation Mode, Divider
Running

Reset Mode, Divider in
Reset State

Bit 7 - The Update In Progress (UIP) bit
is a status flag that may be monitored
by the program. When UIP is a "1", the
update cycle is in progress or will soon
begin. When UIP is a "0", the update
cycle is not in progress and will not be
for at least 2441J.S. The time, calendar,
and alarm information in RAM is fully
available to the program when the UIP

Address 9 - Year: The range of this
register is 0-99 in BCD mode, and 063H in Binary mode.

6-194

•

VLSI TECHNOLOGY, INC.
VL82C106

bit is "0". The UIP bit is a read-only bit,
and is not affected by reset. Writing the
SET bit in Register B to a "1" will inhibit
any update cycle and then clear the U IP
status bit.
Register B
Register B contains command bits to
control various modes of operations
and interrupt enables for the RTC. The
bits in this register are defined as
follows:
Bit
0

Description

Abbr.

Daylight Savings
Enable

DSE

24112 Mode

24/12

Data Mode (Binary
or BCD)

Not Used

Update End Interrupt
Enable

UIE

Alarm Interrupt
Enable

AlE

Periodic Interrupt
Enable

PIE

Set Command

SET

Bit 0 - The Daylight Savings Enable
(DSE) bit is a readlwrite bit which
allows the program to enable two
special updates (when DSE is ·1 j. On
the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM.
On the first Sunday in October when
the time first reaches 1:59:59 AM it
changes to 1:00:00 AM. These special
updates do not occur when the DSE bit
is a ''0". DSE is not changed by any
internal operations or reset.
Bit 1 - The 24/12 control bit establishes
the format of the hours bytes as either
the 24-hour mode ("1") or the 12-hour
mode ("0"). This is a readlwrite bit,
which is affected only by software.
Bit 2 - The Data Mode (DM) bit indicates whether time and calendar
updates are to use binary or BCD
formats. The DM bit is written by the
processor program and may be read by
the program, but is not mod Hied by any
internal functions or reset. A ·1" in OM
signifies binary data, while a "0" in OM
specifies binary-coded-decimal (BCD)
data.

Bit 3 - This bit is unused in this version
of the RTC, but is used for Square
Wave Enable in the Motorola
MC146818.
Bit 4 - The UIE (Update End Interrupt
Enable) bit is a read/write bit which
enables the Update End Interrupt Flag
(UF) bit in Register C to assert an IRQ.
The reset pin being asserted or the SET
bit going high clears the UIE bit.
Bit 5 - The Alarm Interrupt Enable (AlE)
bit is a readlwrite bit which when set to
a "1" permits the Alarm Interrupt Flag
(AF) bit in Register C to assert an IRQ.
An alarm interrupt occurs for each
second that the three time bytes equal
the three alarm bytes (including a "don't
care" alarm code of 11XXXXXXb).
When the AlE bit is a "0", the AF bit
does not initiate an IRQ signal. The
reset pin clears AlE to "0". The internal
functions do not affect the AlE bit.
Bit 6 - The Periodic Interrupt Enable
(PIE) bit is a readlwrite bit which allows
the Periodic Interrupt Flag (PF) bit in
Register C to cause the IRQ pin to be
driven low. A program writes a "1" to
the PIE bit in order to receive periodic
interrupts at the rate specified by the
RS3, RS2, RS1, and RSO bits in
Register A. A "0" in PIE blocks IRQ
from being initiated by a periodic
interrupt, but the Periodic Interrupt Flag
(PF) bit is still set at the periodic rate.
PIE is not mod Hied by any internal
functions, but is cleared to "0" by a
reset.
Bit 7 - When the SET bit is a "0", the
update cycle functions normally by
advancing the counts once-par-second.
When the SET bit is written to a "1", any
update cycle in progress is aborted and
the program may initialize the time and
calendar bytes without an update
occurring in the midst of initializing.
SET is a readlwrite bit which is not
mod Hied by reset or internal functions.
Register C
Register C contains status information
about interrupts and internal operation
of the RTC. The bits in this register are
defined as follows:

Bit

Description

Abbr.

Not Used, Read
asO

Not Used, Read
as 0

Not Used, Read
asO

Not Used, Read
as 0

Update End
Interrupt Flag

Alarm Interrupt Flag

Periodic Interrupt
Flag

IRQ Pending Flag

IRQF

Bits 0 to 3 - The unused bits of Status
Register 1 are read as ·O's", and cannot
be written.
Bit 4 - The Update Ended Interrupt Flag
(UF) bit is set after each update cycle.
When the UIE bit is a "1", the "1" in UF
causes the IRQF bit to be a "1",
asserting IRQ. UF is cleared by a
Register C read or a reset.
Bit 5 - A ·1" in the AF (Alarm Interrupt
Flag) bit indicates that the current time
has matched the alarm time. A "1" in
the AF causes the IRQ pin to go low,
and a "1" to appear in the IRQF bit,
when the AlE bit also is a ·1". A reset
or a read of Register C clears AF.
Bit 6 - The Periodic Interrupt Flag (PF)
is a read only bit which is set to a "1"
when a particular edge is detected on
the selected tap of the divider chain.
The RS3 to RSO bits establish the
periodic rate. PF is set to a ·1" independent of the state of the PIE bit. PF
being a "1" initiates an IRQ signal and
sets the IRQF bit when PIE is also a
"1". The PF bit is cleared by a reset or
a software read of Register C.
Bit 7 - The Interrupt Request Pending
Flag (IRQF) is set to a "1" when one or
more of the following are true:
PF = PIE = 1
AF = AlE = 1
UF = UIE = 1
The logic can be expressed in equation
form as:
IRQF = PF • PIE + AF • AlE + UF • UIE

6-195

•

VLSI TECHNOLOGY, INC.
VL82C106

Any time the IROF bit is a "1", the IRO
pin is asserted. All flag bits are cleared
after Register C is read by the program
or when the reset pin is asserted.
Register 0
This register contains a bit that indicates the status of the on-chip standby
RAM. The contents of the registers are
described as the following:

Bit

Description

Not.Used, Read
as 0

Not Used, Read
as 0

Not Used, Read
asO

Not Used, Read
as 0

Not Used, Read
asO

Not Used, Read
as 0

Vaild RAM Data
and Time

Abbr.

GENERAL RTC NOTES
Set Operation
Before initializing the internal registers,
the SET bit in Register B should be set
to a "1" to prevent time/calendar
updates from occurring. The program
initializes the ten locations in the
selected format (binary or BCD), then
indicates the format in the Data Mode
(OM) bit of Register B. All ten time,
calendar, and alarm bytes must use the
same Data Mode, either binary or BCD.
The SET bit may now be cleared to
allow updates. Once initialized the RTC
makes all updates in the selected Data
Mode. The Data Mode cannot be
changed without reinitializing the ten
data bytes.
BCD vs Binary Format
The 24/12 bit in Register B establishes
whether the hour locations represent 1to-12 or 0-to-23. The 24112 bit cannot
be changed withou1 reinitializing the
hour locations. When the 12-hour
format is selected, the high-order bit of
the hours byte represents PM when it is
a "1".

VRT

Bits 0 to 6 - The remaining bits of
Register 0 are unused. They cannot be
written, but are always read as "O's".
Bit 7 - The Valid RAM Data and Time
(VRT) bit indicates the condition of the
contents of the RAM, provided the
power sense (PS) pin is satisfactorily
connected. A "0" appears in the VRT
bit when the power-sense pin is low.
The processor program can set the
VRT bit when the time and calendar are
initialized to indicate that the RAM and
time are valid. The VRT is a read only
bit which is not modified by the reset
pin. The VRT bit can only be set by
reading Register D.
Pulling the PS/-RC pin low for a
minimum of 2 ~s also sets all RAM
bytes from address OE through 3F to all
ones.
CMOS STANDBY RAM
The 66 general purpose RAM bytes are
not dedicated within the RTC. They
can be used by the processor program,
and are fully available during the update
cycle.

Update Operation
The time, calendar, and alarm bytes are
not always accessible by the processor
program. Once-per-second the ten
bytes are switched to the update logic
to be advanced by one second and to
check for an alarm condition. If any of
the ten bytes are read at this time, the
data outputs are undefined. The
update 10ckou1 time is 1948 ~ for the
32.768 KHz time base. The Update
Cycle section shows how to accommodate the Update Cycle in the processor
program.
Alarm Operation
The three alarm bytes may be used in
two ways. First, when the program
inserts an alarm time in the appropriate
hours, minutes, and seconds alarm
locations, the Alarm Interrupt is initiated
at the specified time each day if the
alarm enable bit is high. The second
usage is to insert a "don't care" state in
one or more of three alarm bytes. The
"don't care" code is any byte from OCOH
to OFFH. An Alarm Interrupt each hour
is created with a "don't care" code in the
hours alarm location. Similarly, an
alarm is generated every minute with
"don't care" codes in the hours and
minutes alarm bytes. The "don't care"
6-196

codes in all three alarm bytes create an
interrupt every second.
Interrupts
The RTC plus RAM includes three
separate fully au10matic sources of
interrupts to the processor. The Alarm
Interrupt may be programmed to occur
at rates from one-per-second to one-aday. The Periodic Interrupt may be
selected for rates from half-a-second to
30.517 ~s. The Update Ended Interrupt
may be used to indicate to the program
that an update cycle is completed.
The processor program selects which
interrupts, if any, it wishes to receive.
Three bits in Register B enable the
three interrupts. Writing a "1" to an
interrupt-enable bit permits that
interrupt to be initiated when the event
occurs. A "0" in the interrupt-enable bit
prohibits the IRO pin from being
asserted due to the interrupt cause.

/! an interrupt flag is already set when
the interrupt becomes enabled, the IRO
pin is immediately activated, though the
interrupt initiating the event may have
occurred much earlier. Thus, there are
cases where the program should clear
such earlier initiated interrupts before
first enabling new interrupts.
When an interrupt event occurs, a flag
bit is set to a "1" in Register C. Each of
the three interrupt sources have
separate flag bits in Register C, which
are set independent of the state of the
corresponding enable bits in Register B.
The flag bit may be used with or without
enabling the corresponding enable bits.
Divider Control
The Divider Control bits are fixed for
only 32.768 KHz operation. The divider
chain may be held in reset, which
allows precision setting of the time.
When the divider is changed from reset
to an operating time base, the first
update cycle is one-half a second later.
The Divider Control bits are also used
to facilitate testing the RTC.
Periodic Interrupt Selection
The Periodic Interrupt allows the IRO
pin to be triggered from once every 500
ms to once every 30.517 ~s. The
Periodic Interrupt is separate from the
Alarm Interrupt which may be output
from once-per-second to once-per-day.

•

VLSI TECHNOLOGY; INC.
VL82C106

KEYBOARD CONTROLLER
The keyboard controller on-chip ROM
contains the code that is required to
support the PC/AT and PS/2 command
sets and 128 bytes of conversion code.
Keyboard serial I/O is handled with
hardware implementations of the
receiver and transmitter. Both functions
depend on an 8-bit timer for time-out
detection. Enhanced status reporting is
provided in hardware to simplify error
handling in software. This logic is
duplicated for the mouse interface.
User RAM support is provided. The
program writes a command 20-3FH
(read) or SO-7FH (write) with the lower
five bits representing the RAM address.
Data from a read or for a write are
accessed through port SOH DBB.
Parallel Port 1 (input) is provided and
Parallel Port 2 (output) has defined
functions depending on whether the
controller is in PC/AT or PS/2 mode.
Support for PORT SOH DBB (reads and
writes) and Status Register (reads and
writes) is provided in hardware for
interface to the PC host.

KEYBOARD CONTROLLER
INTERFACE TO PC/AT
The interface to the PC/AT consists of
one register pair (PORT SOH/64H) for
the keyboard and mouse.

The PORT SOH read operations output
the contents of the Output Buffer to 0007 and clears the status of the Output
Buffer Full (OBF/Status Register bit 0)
bit.
Status read operations output the
contents of the Status Register to 0007. No status is changed as a result of
the read operation.
The PORT SOH write operations cause
the Input Buffer DBB to be changed.
The state of the C/O bit is cleared
(Status Register bit 3, "0" indicates
data) and the Input Buffer Full (IBF/
Status Register bit 1) bit is set ("1").
Command write operations are to
PORT 64H. The C/O bit will be set to
("1") when a valid command has been
written to PORT S4H.

KEYBOARD PORT INTERFACE
PROTOCOL
Data transmission between the controller, the keyboard, and mouse consist of
a synchronous bit stream over the data
and clock lines. The bits are defined as
follows:
Bit

Function

Start Bit (Always 0)

Data Bit 0 (LSB)

3-8
9

Data Bits 1-S
Data Bit 7 (MSB)

Parity Bit (Odd)

Stop Bit (Always 1)

S-197

PROGRAMMER INTERFACE
The programmer interface to the
keyboard controller is quite simple,
consisting of four registers:

RIW

110

Status

64H

Command

64H

Output Buffer

60H

Input Buffer

60H

The behavior of these registers differ
according to the mode of operation (PC/
AT or PS/2). There exists only one
mode register and one Status Register
with different bit definitions for PC/AT
mode and PS/2 mode. The bit definitions for each register in each mode
follows.

•

VLSI TECHNOLOGY, INC.
VL82C106

FIGURE 1. PC/AT MODE REGISTER (READ PORT 60H AFTER WRITE COMMAND 20H TO PORT 64H)
7

KCC

KBD

DKB

INH

SYS

I I I I I I I I I
0

EKI

ENABLEKBDINTERRUPT
o = INT DISABLED
1 ~ INT ENABLED

RESERVED. SET TO 0

SYSTEM FLAG
o = SETS STATUS REG (2) = 0
1 = SETS STATUS REG (2) = 1

KEY LOCK INHIBrr OVERRIDE
o = ENABLE KEY LOCK FUNCTION
1 = DISABLE KEY LOCK FUNCTION

DISABLE KEYBOARD
0= ENABLED
1 - DISABLED

KEYBOARD TYPE
o = AT STYLE KEYBOARD
1 = PC STYLE KEYBOARD

KEYCODE CONVERSION
o = NO CONVERSION OF KEYCODES
1 - CONVERSION ENABLED

RESERVED. SET TO 0

PC/AT MODE REGISTER
Bit 0 • Enable Keyboard Interrupt (EKI).
when set ("1") causes the controller to
generate a keyboard interrupt whenever
data (keyboard or controller) is written
into the output buffer.

to indicate a switch from virtual to real
mode when set.
Bit 3 • Inhibit Override (INH), when set
("1") disables the keyboard lock function
(KKSW Input).

Bit 1 • Reserved, should be written as
110".

Bit 4 - Disable Keyboard (DKB), when
set ("1") disables the keyboard by
holding the -KCKOUT line low.

Bit 2 • System Flag (SYS), when set
("1 ") writes the System Flag bit of the
Status Register to "1". This bit is used

Bit 5 - Keyboard Type (KBD), when set
("1 i allows for compatibility with PC-

6-198

style keyboards. In this mode, parity is
not checked and scan codes are not
converted.
Bit 6 - Keycode Conversion (KCC),
when set ("1") causes the controller to
convert the scan codes to PC format.
When reset, the codes (AT keyboard)
are passed along unconverted.
Bit 7 - Reserved, should be written as
"0".

•

VLSI TECHNOLOGY, INC.
VL82C106

FIGURE 2. PS/2 MODE REGISTER (READ PORT 60H AFTER WRITE COMMAND 20H TO PORT 64H)
7
I

6
KCC

OMS

DKB I

3
0

2
SYSI EMI

EKI

ENABLE KBD INTERRUPT

o = INT DISABLED
1 = INT ENABLED

ENABLE MOUSE INTERRUPT

o = INT DISABLED
1 = INT ENABLED

SYSTEM FLAG
0= SETS STATUS REG (2) = 0
1 =SETS STATUS REG (2) =1
RESERVED =0

DISABLE KEYBOARD
0= ENABLED
1 = DISABLED

DISABLE MOUSE
0= ENABLED
1 =DISABLED
KEYCODE CONVERSION

o = NO CONVERSION OF KEYCODES
1 = CONVERSION ENABLED

RESERVED. SET TO 0

PS/2 MODE REGISTER
Bit 0 - Enable Keyboard Interrupt (EKI).
when set ("1") causes the controller to
generate a keyboard interrupt whenever
data (keyboard or command) is written
into the output buffer.
Bit 1 - Enable Mouse Interrupt (EM I).
when set ("1 ") allows the controller to
generate a mouse interrupt when
mouse data is available in the output
register.

Bit 2 - System Flag (SYS). when set
("1") writes the System Rag bit of the
Status Register to "1". This bit is used
to indicate a switch from virtual to real
mode when sel.
Bit 3 - Reserved. ''0".
Bit 4 - Disable Keyboard (OKB). when
set ("1") disables the keyboard by
holding the -KCKOUT low.

6-199

Bit 5 - Disable Mouse (OMS). when set
("1") disables the mouse by holding the
-MCKOUT low.
Bit 6 - Keycode Conversion (KCC).
when set ("1") causes the controller to
convert the scan codes to PC formal.
When reset. the codes (PS/2 keyboard)
are passed along unconverted.
Bit 7 - Reserved. "0".

•

VLSI TECHNOLOGY, INC.
VL82C106

FIGURE 3. PC/AT STATUS REGISTER (READ ONLY - PORT 64H)
7

PERR

RTIM

TTIM

KBEN

CID

SYS

I I I I I I I I I
IBF

OBF

OUTPUT BUFFER FULL
0= EMPTY
1 = FULL
INPUT BUFFER FULL
O=EMPTY
1 = FULL
SYSTEM FLAG

o= COLD RESET
1 = HOT RESET
COMMAND/DATA
0= DATA OR IDLE
1 = COMMAND OR BUSY
KEYBOARD ENABLE SWITCH
O=DISABLED
1 = ENABLED
TRANSMIT TIME-OUT
O=NORMAL
1 = TIME-OUT OCCURRED
RECEIVE TIME-OUT
O=NORMAL
1 = TIME-OUT OCURRED
RECEIVE PARITY ERROR
0= NORMAL
1 = PARITY ERROR

PCIAT Status Register
Bit 0 - Output Buffer Full (OBF). when
set ("1") indicates that data is available
in the controller Data Bus Buffer. and
that the CPU has not read the data yet.
CPU reads to PORT 60H to reset the
state of this bit.
Bit 1 - Input Buffer Full (IBF). when set
("11 indicates that data has been
written to PORT 60H or 64H. and the
controller has not read the data.
Bit 2 - System Flag (SYS). when set
("11 indicates that the CPU has
changed from virtual to real mode.

Bit 3 - Command/Data (CD). when set
("11 indicates that a command has
been placed into the Input Data Buffer
of the controller. The controller uses
this bit to determine if the byte written is
a command to be executed.
Bit 4 - Keyboard Enable (KBEN).
indicates the state of the "keyboard
inhibit" switch input (KKSW). "0"
indicates the keyboard is inhibited.
Bit 5 - Transmit TIme- 84-S7)

Poll in Port High
(P14-P17 -> 84-S7)

Write Output Port

21-3F

Read Keyboard Controller
RAM (Byte 1-31)

Write Keyboard Output Buffer

Write Mode Register

Write Mouse Output Buffer

61-7F

Write Keyboard Controller
RAM (Byte 1-31)

Write to Mouse

Self Test

The following is a description of each
command:

KBD Interface Test

Diagnostic Dump

Disable Keyboard

Enable Keyboard

Read Input Port (P1 O·P17)

Read Output Port (P20-P27)

Write Output Port

Read Test Inputs (TO, T1)

FO-FF

Pulse Output Port (P20-P27)

Note: If data is written to the data
buffer (PORT 60H) and the command preceding it did not expect
data from the port (PORT 60H)
the data will be transmitted to
the keyboard.

Read the keyboard controller's
Mode Register (PC/AT and PSI
2) - The keyboard controller
sends its current mode byte to
the output buffer (accessed by a
read of PORT 60H).

that the password is installed,
and F1 H means that it is not.
AS

Load Password (PS/2 only) This command initiates the
password load procedure.
Following this command, the
controller will take data from the
input buffer port (PORT 60H)
until a OOH is detected or a full
eight byte password including a
delimiter (e.g. .

Enable Password (PS/2 only) This command enables the
security feature. The command
is valid only when a password
pattern is written into the
controller (see AS command).
No other commands will be
"honored" until the security
sequence is completed and
command A6 is cleared.

Disable Mouse (PS/2 only) This command sets bit S of the
Mode Register which disables
the mouse by driving the
-MCKOUT line low.

Enable Mouse (PS/2 only) - This
command resets bit S of the
Mode Register, thus enabling
the mouse.

Mouse Interface Test (PS/2
only) - This command causes
the controller to test the mouse
clock and data lines. The
results are placed in the output
buffer (the OBF bit is set) and
the KIRQ line is asserted (if the
EKI bit is set). The results are
as follows:

21-3F Read the keyboard controller's
RAM (PC/AT and PS/2) - Bits
04-00 specify the address.
60

Write the keyboard controller'S
Mode Register (PC/AT and PSI
2) - The next byte of data
written to the keyboard data port
(PORT 60H) is placed in the
controller's mode register.

61-7F Write the keyboard controller's
RAM (PC/AT and PS/2) - This
command writes to the internal
keyboard controller RAM with
the address specified in bits 04DO.
A4

Test Password Installed (PS/2
only) - This command checks if
there is currently a password
installed in the controller. The
test result is placed in the output
buffer (the OBF bit is set) and
KIRQ is asserted (if the EKI bit
is set). Test result - FAH means

6-203

-~--

Data

Meaning

No Error

Mouse Clock Line Stuck Low

Mouse Clock Line Stuck High

Mouse Data Line Stuck Low

Mouse Data Line Stuck High

•

VLSI TECHNOLOGY, INC.
VL82C106

Self Test command (PC/AT and
PS/2) - This commands the
controller to perform internal
diagnostic tests. A 55H is
placed in the output buffer nno
errors were detected. The OBF
bit is set and KIRQ is asserted
(if the EKI bit is set).
Keyboard Interface Test (PC/AT
and PS/2) - This command
causes the controller to test the
keyboard clock and data lines.
The test result is placed in the
output buffer (the OBF bit is set)
and the KIRQ line is asserted (if
the EKI bit is set). The results
are as follows:

Poll Input Port high (PS/2 only) P1 bits 4-7 are written into
.
Status Register bits 4-7 until a
new command is issued to the
keyboard controller.

Read Output Port (PC/AT and
PS/2) - This command causes
the controller to read the P2
output port and place the data in
its output buffer. The definitions
of the bits are as follows:

Bit

PC/AT
Mode

PS/2
Mode

Write Mouse Output Buffer (PS/
2 only) - The next byte written to
the data buffer (PORT 60H) is
written to the output buffer as if
initiated by the mouse [the OBF
bit is set ("1 j and MIRQ will be
set if the EMI bit is set ("1 "ll.

Write to Mouse (PS/2 only) The next byte written to the data
buffer (PORT 60H) is transmitted to the mouse.

Read Test Inputs (PC/AT and
PS/2) - This command causes
the controller to read the TO and
T1 input bits. The data is placed
in the output buffer with the
following meanings:

Data

Meaning

P20

-RC

No Error

P21

A20Gate

A20 Gate

Bit

PClATMode

PS/2 Mode

Keyboard Data

Keyboard Clock

Mouse Clock

3-7

Read asO's

Read as O's

Keyboard Clock Line Stuck Low

Keyboard Clock Line SttJck High

Keyboard Data Line Stuck Low

Keyboard Data Line Stuck High

P24

Diagnostic Dump (PC/AT only,
Reserved on PS/2) - Sends 16
bytes of the controller's RAM, the
current state of the input port,
and current state of the output
port to the system.

P25

P26

-KCKOUT

P27

KOOUT

-KDOUT

Keyboard Disable (PC/AT and
PS/2) - This command sets bit 4
of the Mode Register to a "1".
This disables the keyboard by
driving the clock line (-KCKOUT)
high. Data will not be sent or
received.

Keyboard Enable (PC/AT and
PS/2) - This command resets bit
4 of the mode byte to a ·0". This
enables the keyboard again by
allowing the keyboard clock to
free-run.

Read P1 Input Port (PC/AT and
PS/2) - This command reads the
keyboard input port and places it
in the output buffer. This
command overwrites the data in
the buffer.

Poll Input Port low (PS/2 only) P1 bits 0-3 are written into Status

2
3

P22

Speed Sal

-MOOUT

P23

Shadow
Enable

-MCKOUT

Output
Buffer Full

KIRQ
MIRQ

Note: P22 (bit 2) is the speed control
pin used by Award BIOS, and
this is different from what is
used by Phoenix and AMI.
01

Write Output Port (PC/AT and
PS/2) - The next byte of data
written to the keyboard data port
(PORT 60H) will be written to
the controller's output port. The
definitions of the bits are as
defined above. In PC/AT mode,
P26 and P27 are not modified.
In PS/2 mode, P22, P23, P26
and P27 are not modified.

Write Keyboard Output Buffer
(PS/2 only) - The next byte
written to the data buffer (PORT
60H) is written to the output
buffer (60H) as if initiated by the
keyboard [the OBF bit is set ("1 ")
and KIRQ will be set if the EKI
bit is set ("1")].

6-204

FO-FF Pulse Output Port (PC/AT and
PS/2) - Bits 0-3 of the controller's output port may be pulsed
low for approximately 611S. Bits
0-3 of the command specify
which bit will be pulsed. A ·0"
indicates that the bit should be
pulsed; a "1" indicates that the
bit should not be modified. FF is
treated as a special case (Pulse
Null Port). In PC/AT mode, bits
P26 and P27 are not pulsed. In
PS/2 mode, bits P26, P27, P22
and P23 are not pulsed.

•

VLSI TECHNOLOGY, INC.
VL82C106

IDE Bus Interface Control
Integrated Drive Electronics bus
interface control signals are provided by
the VL82C10S Combo chip. The timing
and drive for these lines are consistent
with the Conner Peripherals CP342
Integrated Hard Disk Manual.

-IDENl

A set of signals are used for this
interface when the Vl82C1 OS Combo
chip is configured to support the IDE
interface via IDE_EN, bit S of Control
Register 1 (RTC Register SAH).

IDINT

This allows a simple implementation for an IDE bus
that includes both the hard
disk controller and the
floppy disk controller.
IRQI

This is the three-state
interrupt request to the
CPU. It is normally tied
directly to the IRQ14 signal
of the system. It reflects the
state of the IDINT input and
is enabled by writing bit 1 =
o of 1/0 3FSH as long as
IDE_EN_1. Resetor
disabling the IDE system
three-states IRQI.

-IOCS1S

The Vl82C106 Combo chip
has multiple sources for this
signal. It is driven active
(low) when:

This signal indicates an
interrupt request to the
system. It is used to
generate IRQI.

Output Signals:
-CS4

-CSS

-HCS1

-IDENH

Chip Select 4. This signal
is used as the floppy disk
chip select. The default
decode is 03F4H-03FSH,
but may be redefined as described in the section on
Combo Chip Control
Registers. The IDE_EN
control bit of Control
Register 1 has no effect on
this signal. -CS4 is also
active when -CDAK4 is
active.
Chip Select S. This signal
is used as the -HOST CSO
of the IDE bus. The default
decode is 01 FOH-01 F7H,
but may be redefined as described in the section on
Combo Chip Control Registers. The IDE_EN control
bit of Control Register 1 has
no effect on this signal.
This signal is active (low)
for address 03FSH-03F7H
and is used as -HOST
CS1 of the IDE bus.
This signal is used to drive
the -OE pin of an external
74lS245 buffering bits 8-1S
of the IDE data bus to the
SO bus. It is active (low)
when:

This signal is used to drive
the -OE pin of an external
74lS24S buffering bits O-S
of the IDE data bus. It is
active (low) when:
-CSS is active OR SAOSAg = 3FS OR 3F7.

The Combo chip has duplicated bit 1 of
the "Fixed Disk Register" (110 3FSH) to
enable IRQI.
Input Signals:

SD7 -> IDB7 at all other
times when IDE EN=1,
three-stated (with internal
pull-up) if IDE_EN=O.

-CSS is active AND SA2SAO - 000.

(-CSS is active AND SAOSA2 = 000 AND IDE_EN =
1 AND {(CS_MODE = 0)
OR (CS_MODE = 1 AND
1S-bit operation selected for
CSS)}) OR (any other CS is
active with 1S-bit operation
selected AND CS_MODE =
1) OR (IDE_EN = 0 AND
CSS is active AND 1S-bit
operation is selected AND
CS_MODE = 1).

Combo Chip Control Ports:
Contained in the Vl82C1 OS are a set of
2S registers used for programming
peripheral chip select base addresses,
chip select address ranges, and
enabling options. Each base address
register is a 1S-bit register with bits
corresponding to address bits A1S-AO.
In addition to base address registers,
there is an address range register that
can be used to "don't-care" bits (AO-A4)
used in the address range comparison,
effectively controlling the address space
occupied by the chip select from 1 to 32
bytes. There are also programmable
bits to selectively generate wait states,
and assert -IOCS1S whenever the
corresponding address range is
present. These registers are used in
groups of three per chip select, and are
defined as shown below:
Base Address Register (lSB):
Bit

Description

Base Address, Bit AO

Base Address, Bit A 1

Base Address, Bit A2

Base Address, Bit A3

Base Address, Bit A4

Base Address, Bit AS

Base Address, Bit A7

Base Address Register (MSB):

Bidirectional Signals:
IDB7, -DC The control for the transceiver between IDB7, -DC,
and SD7 is as follows:
IDB7 -> SD7 when:
(-CSS is active OR SAOSAg = 3FS) AND -lOR is
active AND IDE_EN = 1
AND NOT SAO-SA9 =
3F7H.
-DC -> SD7 when SAOSAg = 3F7H AND -lOR is
active AND IDE_EN = 1.

S-20S

Bit

Description

Base Address, Bit A8

Base Address, Bit A9

Base Address, Bit A 10

Base Address, Bit A 11

Base Address, Bit A12

Base Address, Bit A 13

Base Address, Bit A 14

Base Address, Bit A 1S

•

VLSI TECHNOLOGY, INC.
VL82C106

Range Register:
Bit

Description

Don't Care, Bit AO

Dont' Care, Bit A1

Don't Care, Bit A2

Don't Care, Bit A3

Don't Care, Bit A4

Wait State 0

Wait State 1

8116 Bit 1/0

The only bits that need detailed
descriptions are those contained in the
Range Register. These bits are defined
as follows:
Bits 0 to 4 - Don't Care Bits, when set
("1") causes that corresponding bit to be
ignored during the chip select generation, effectively allowing the chip select
signals to correspond to a range or
ranges of addresses in the space from
Base Address + 0 to Base Address +
31.
Bits 5 & 6 - Wait State 0 and 1, these
bits determine the number of wait states
that will be generated whenever the
corresponding chip select signal is
generated. They generate wait states
according to the following table:
Walt States·

WS1

WSO

Note: Programmed wait states can
only extend the 110 cycle set
by the system architecture.
Bit 7- S/16 Bit I/o, this bit is used to selectively assert -IOCS16 whenever the
corresponding chip select signal is
generated. When set ("1"), the access
is defined as an S-bit access, and
-IOCS 16 is not asserted •

Default Chip Selects
The VLS2Cl06 Combo chip also has
several hard-wired default chip selects
for the serial ports, line printer port,
floppy disk chip select and hard disk
chip select. These default chip selects
are used after a reset until the batterybacked programmable values are
enabled via bit 3 of the second control
register (RTC register 6AH). The wait
state and non IDE -IOCS16 values are
also disabled in this mode. This allows
the Combo chip to function normally
withoUt the need for programming. The
default chip selects are:
Select!
Device
COMA

COMB

LPT

Addr

Usage

Control Register O·

Control Register 1·

CS1 COMA Base Add LSB

CS1 COMA Base Add MSB

CS1 COMA Range

CS2 COMB Base Add LSB

CS2 COMB Base Add MSB

CS2 COMB Range

CS3 LPT Base Add LSB

Address

CS3 LPT Base Add MSB

3FSH-3FFH
(Bit 3 of RTC Reg 69H =1)
2FSH-2FFH
(Bil 3 of RTC Reg 69H = 0)

CS3 LPT Range

CS4 FOC Base Add LSB

CS4 FOC Base Add MSB

CS4 FOC Range

2FSH-2FFH
(Bit 3 of RTC Reg 69H =1)
3F8H-3FFH
(Bit 3 of RTC Reg 69H = 0)
03BCH-03BFH
(Bil 5, 6 of RTC Reg 69H = 0, 0)
0378H-037BH
(Bit 5, 6 of RTC Reg 69H = 1, 0)
027SH-027BH
(Bi15, 6 of RTC Reg 69H = 0,1)

CS5 HOC Base Add LSB

CS5 HOC Base Add MSB

CS5 HOC Range

CS6 Base Add LSB

CS6 Base Add MSB

-eS4

03F4H-03F5H

CS6 Range

-eS5

01 FOH-Ol F7H

CS7 Base Add LSB

-eS6

03F2H AND -lOW is Active

CS7 Base Add MSB

-eS7

03F7H AND -lOW Is Active
7F

CS7 Range

Note: Note that on reset, COMA,
COMB, LPT, and -eS4 through -CS7
are enabled and set to the hard-wired
values. -eS6 and -CS7 are only
qualified by -lOW when the hard-wired
decodes are enabled. By writing values
to control registers 7Ah through 7Fh
and enabling these values via bit 3 of
Control Register 1, the -lOW qualification is removed. -eS6 and -CS7 then
become general purpose chip selects
usable for read and write cycles.

• Number of wait states = number of
SYSCLK cycles lOCH ROY is forced
inactive (low) by the Combo chip.

6-206

Combo Chip Control Register
The VL82C106 Combo chip contains a
number of programmable options,
including peripheral base address and
chip select "hole" size. The registers
used to provide this control are located
in the upper bytes of the RTC address
space. They are defined as follows:
• Note:

Control Register 0 and 1 are
not battery-backed via the
VBAT supply.

•

VLSI TECHNOLOGY, INC.
VL82C106

This register can also be accessed at
address 102H, for PS/2 compatibility.
The contents of the register are detailed
below:

Bit 4 - Line Printer Port Enable (LPT
EN) Control bit, when set ("1") enables
the LPT port (CS3). When reset (''OJ
disables the LPT port.
Bit 5 & 6 - Line Printer Default bits 0
and 1 (LPT DEF 0 and 1) Control bits,
set the Line Printer Base hard-wired
address defauks as shown below:

Usage

Value After
Reset

SYS BD EN

Enabled

(1)

FDCS EN
(CS4)

Enabled

(1)

Bit
6

Bit

Address Range

COMA EN
(CS1)

Enabled

(1)

03BCH-03BFH

037SH-037BH

027SH-027BH

Reserved

Bit

COMADEF

COM1

(1)

LPT EN (CS3)

Enabled

(1)

LPT DEFO

Paralled
Port 1

LPT DEF 1

Disabled

(0)

-EMODE

Compat.
Mode

(1)

(0)

Bit 0 - System Board Enable (SYS BD
EN) Control bit, when set ("1") allows
bits 1, 2, and 4 to enable and disable
their respective devices. When reset
(''OJ the floppy disk chip select (CS4),
COMA (CS 1), and the LPT port (CS3)
are disabled regardless of the contents
of bits 1, 2, and 4.
Bit 1 - Floppy Disk CS Enable (FDCS
EN) Control bit, when set ("1") allows
the FD CS signal (CS4) to be asserted
to an external floppy disk controller
chip. When reset ("0") prevents the
assertion of this chip select.
Bit 2 - Communications Port A Enable
(COMA EN) Control bit, when set ("1")
allows the internal COMA (CS1) port to
be accessed. When reset ("0") COMA
is disabled.
Bit 3 - Communications Port A Defauk
Address (COMA DEF) Control bit, when
set ("1") forces the hard-wired defauk
base address to COMA to correspond
to (3FSH-3FFH) and COMB to (2FSH2FFH). When reset ("0") forces the
COMA hard-wired address to (2FSH2FFH) and COMB to (3FSH-3FFH).
The base address will be the programmed values if bit 3 of control
register 1 (RTC register 6AH) is set.

Setting bit 3 of RTC register 6AH
changes the base address to that set in
the program address registers for LPT
(CS3).
Bit 7 - Line Printer Extended Mode
(EMODE) Control bit, when set ("1 j
disables the Extended Mode and forces
PC/AT compatibility. When reset ("0"),
the Extended. Mode is enabled, allowing
the printer port direction to be controlled.
Control Register 1 (RTC Register
6AH) Bits
This register is used to control peripheral chip selects that are not included in
Control Register O. The bits in this
register are defined as follows:

Usage

Value After
Reset

COMB EN

Enabled

(1 )

ATIPS2 KBD

(1)

PRIVEN

Enabled

(1 )

CS MODE

Hard-wire

(0)

Bit

HDCSEN

Enabled

(1 )

IDE EN

Enabled

(1)

CS6EN

Enabled

(1 )

CS7EN

Enabled

(1)

Bit 0 - Communication Port B Enable. A
"1" enables COMB (CS2). A zero ("0")
disables COMB.

6-207

Bit 1 - AT or PS/2 Compatible Keyboard. A "1" selects PC/AT type
keyboard controller functions, while a
"0" places the keyboard controller in
PS/2 mode.
Bit 2 - Private Controls Enable. When
in AT mode (ATIPS2_KBD = 1), this bit
is used to latch the values of the
keyboard controller's output signals
KHSE, KSRE, and IROM to the
VLS2Cl06 output pins. When "1",
these outputs follow the keyboard
controller's outputs. When "0·, these
outputs held at that value regardless of
the keyboard controller's outputs.
When in PS/2 mode (AT/PS2_KBD =
0), this bit has no effect on the KHSE,
KSRE, and IROM output pins. The.'
Combo chip outputs follow the keyboard controller's outputs.
Bit 3 - Chip Select Decode Mode. When
"0", CS1-CS7 decodes revert to the
hard-wired address decoding and non
IDE -IOCS16 and lOCH ROY generation is disabled. A "1" enables the
address decoding, wait state generation
and S/16-bit operation as programmed
into the RTC registers 69H-7FH. (See
sections on Default Chip Selects and
Combo Chip Control Register.)
Bit 4 - Hard Disk Chip Select Enable. A
"1" enables the Hard Disk Chip Select
signal (-CS5), while a "0" disables the
chip select.
Bit 5 - Integrated Drive Electronics
Enable. A "1" enables the IDE functions of outputs -IDENH, -IDENL, IROI,
-IOCS16, and IDB7 as described in
IDE Bus Interface Control section.
Bit 6 - Chip Select 6 Enable. When "0",
the -eS6 output is disabled. A "1"
enables the address decoding, wait
state generation and S/16-bit operation
as programmed into the RTC registers
7A-7CH. (See sections on Default Chip
Selects and Combo Chip Control
Registers.)
Bit 7 - Chip Select 7 Enable. When ·0",
the -eS7 output is disabled. A "1"
enables the address decoding, wait
state generation and S/16-bit operation
as programmed into the RTC registers
7D-7FH. (See sections Default Chip
Selects and Combo Chip Control
Register.)

•

VLSI TECHNOLOGY, INC.
VL82C106

Miscellaneous Control Signals
This input signal is
XDDIR
normally generated by the
system. It is inactive (low)
when data is transferred
from the XD bus to the SD
bus, i.e., interrupt acknowledge cycles and I/O read
accesses to addresses
OOOH-oFFH.
XDIRS

XDIRX

-XDEN

-CDAK4

This input will directly
produce an active low on
-CS4 when active low
itself and is used by the
IDE logic.

-IOCS16

This output signal is used
to indicate to the system
that the peripheral being
accessed is a 16-bit
device. It is set active
(low) when a programmed
chip select, which specifies
16-bit I/o, is decoded or
for certain IDE functions.
(See sections on Combo
Chip Control Ports and
IDE Bus Interface Control.)

This output signal is to
control the direction pin of
a transceiver between the
XD bus and the SD bus
when the Combo chip is
on the SD bus. Since the
architecture assumes the
RTC and Keyboard
Controller are on the XD
bus, this signal is set
active (high) when XDDIR
is high or either the RTC or
the Keyboard Controller is
selected.
This output signal is to
control the direction pin of
the transceiver between
the XD bus and the SD
bus when the Combo chip
is on the XD bus. Since
the architecture assumes
the peripherals other than
the RTC and Keyboard
Controller are on the SD
bus, this signal is inactive
(low) when the XDDIR is
low or when -lOR is low
and any chip select (CS1CS7) is generated.
This output signal is used
to enable the XD bus
transceiver when the
VL82Cl06 Combo chip is
placed on the XD bus and
DMA's are desired for
peripherals controlled by
the Combo chip selects. It
is the AND of -lOR and
-lOW (active low when
either -lOR or -lOW are
active).

When 16-bit programmed
chip select operation is
selected, -IOCS16
becomes active on the
leading edge of ALE and
inactive on the trailing
edge of -lOW or -lOR.
For 8-bit operation or
default chip select operation, -IOCS16 is inactive
during -lOW or -lOR
active.
IOCHRDY

This output signal is used
to the lengthen I/O cycle to
the peripheral being
accessed. It is set inactive
(low) for the programmed
number of wait states
when a programmed chip
select, which specifies
one, three, or seven wait
states, is decoded. (See
the section IDE Bus
Interface Control.)
IOCHRDY transitions
inactive at the falling edge
of -lOW or -lOW, if
enabled, and returns high
at the falling edge of
SYSCLK after the appropriate number of wait
states (SYSCLK cycles).

6-208

Note:

Programmed wait states
can only extend the I/O
cycle, i.e., if the system
architecture provides four
wait states for 8-bit I/o,
programming 1 or 3 has no
effect.

XTAL1

This pin is the input to the
on-board 18.432 MHz
crystal oscillator. This pin
may also be driven by an
external CMOS clock
signal at 18.432 MHz.

XTAL2

This pin is the output pin of
the internal crystal
oscillator and should be
left open and unloaded if
an external clock signal is
applied to the XTAL1 pin.
This pin is not capable of
driving external loads other
than the crystal.

-TRI

This pin is used for incircuit testing. When low,
all outputs and I/O pins are
placed in the high impedanee state.

-ICT

This pin, when strobed
low, places the VL82Cl06
into test mode, determined
by the data on the SDO
through SD3 pins. The
chip will remain in this
mode until RES is asserted. Test mode may be
changed by strobing this
pin low again with different
data on the SDO-SD3 pins.

•

VLSI TECHNOLOGY, INC.
VL82C106

AC CHARACTERISTICS:

= ooe to +70 oe, vee = 5 V ±5%, GND = 0 V

Parameter

Conditions

I/O ReadlWrite Fiaures 6 7
tSU1

Address Setup lime

tH2

Address Holdlime

tSU3

AEN Setup lime

tH4

AEN Hold lime

Command Pulse Width

125

tSU6

Write Data Setup

tH7

Write Data Hold

t08

Read Data Delay

130

CL=200 pF

tH9

Read Data Hold

CL=50pF

Write Cycle

280

Read Cycle

280

Chip Select Timing (Hard-wired) Figures 8 10
t011

Chip Select Delay from Address

CL=50 pF

t012

-CS6, -CS7 Delay from -lOW

CL=50 pF

t013

-IOCS16 Active from Address

CL=200 pF

tD14

-CS4 Delav from -CDAK4

CL=50pF

Chip Select Delay from Address

CL=50 pF

tD13

-IOCS16 Active from Address

CL-200 eF

tD14

-CS4 Delay from -CDAK4

CL=50 pF

Chip Select Timing (Programmable) Figures 8 10
tD11

-IOCS16110CHRDY Timing Figures 9 10
t015

IOCHRDY Inactive from Command

CL=200 pF

t016

lOCH ROY Active from SYSCLK

CL=200 pF

tD17

-IOCS16 Inactive from Command

CL=200 pF

SYSCLKlALE Timing Figures 9 10
t18

SYSCLK Period

t19

SYSCLK Pulse Width Low

t20

SYSCLK Pulse Width High

t21

ALE Pulse Width Hiah

Note:

-IOeS16, IOCHRDYare open-drain outputs with an active pull-up for approximately 10 ns. These parameters are
measured at VOH = 1.5 V with a 300 ohm pull-up. Actual performance will vary depending on system configuration.

6-209

•

VLSI TECHNOLOGY, INC.
VL82C106

AC CHARACTERISTICS (Cont.): TA = o·c to +70·C, VCC =5 V ±50/0, VSS = 0 V
Symbol

Parameter

Un"

Conditions

IDE Interface Timing Figure 11
1018

IRQI Delay from IDINT

CL=100 pF

tD19

IDENHIIDENL Delay from Address

CL=50 pF

CL=200 pF

tD20

IDB7 Delay from SD7 InplJi

tD21

SD7

Dela~from

IDB7

Inp~t

tD22

SD7 Delay from -DC Input

CL=200 pF

1023

SD7 Delay from -lOR During IDE Access

CL.200pF

tH24

SD7 Hold from -lOR Inactive

CL=50 pF

1025

IDB7 Delay from -lOR Inactive

CL=200pF

IH26

IDB7 Hold from -lOR Active

CL=50 pF

XDATA Control Timing Figure 12
tD27

-XDIRS/-XDIRX Delay from -XDDIR

CL=50 pF

1028

-XDIRX Delay from -lOR

CL=50 pF

1029

-XDEN Delay from Command

CL=50 pF

Real Time Clock Timing Figure 18
IPSPW

Power Sense Pulse Width

I.I.S

tPSD

Power Sense Delay

tVRTD

VRTBit Delay

tSBPW

-STBY Pulse Width

2
2

6-210

J.lS
J.lS

•

VLSI TECHNOLOGY, INC.
VL82C106

AC CHARACTERISTICS (Cont.):
Symbol

TA = o·c to +70·C, VCC

= 5 V ±5%, GND = 0 V

Parameter

Conditions

SERIAL, PRINTER
Transmitter Figure 13
tHR1

Delay from Rising Edge of -lOW
(WR THR) To Reset Interrupt

IIRS

Delay from THRE Reset to Transmit Start

tSI

Delay from Write to THRE

tSTI

Delay from Stop to Interrupt (THRE)

IIR

Delay from -lOR (RD IIR)
to Reset Interrupt (THRE)

175

ClK
Cycles

Note 2

ClK
Cycles

Note 2

ClK
Cycles

Note 2

250

100 pF load

Modem Control Figure 14
tMDO

Delay from -lOW
(WR MCR) to Output

250

100 pF load

tSIM

Delay to Set Interrupt from MODEM Input

250

100 pF load

tRIM

Delay to Reset Interrupt from
-lOR (RS MSR)

250

100 pF Load

Receiver Figure 12
tSINT

Delay from Stop to Set Interrupt

ClK
Cycles

tRINT

Delay from -lOR
(RD RBRlRDlSR) to Reset Interrupt

ILs

100pF load

Note 2

Parallel Port Figure 15
Data Time

ILs

Software Controller

tSB

Strobe Time

ILs

Software Controller

tAD

Acknowledge Delay (Busy Start to Acknowledge)

ILs

Defined by Printer

tAKD

Acknowledge Delay (Busy End to Acknowledge)

ILs

Defined by Printer

tAK

Acknowledge Duration Time

ILs

Defined by Printer

tBSY

Busy Duration Time

ILs

Defined by Printer

Busy Delay Time

ILs

Defined by Printer

tOT

tBSD
Notes:

500

1. All timing specifications apply to pins on both serial channels (e.g. RI refers to both RIO and RI1).
2. ClK cycle refers to external 18.432 MHz clock divided by 10, e.g. 1.8432 MHz.

6-211

•

VLSI TECHNOLOGY, INC.
VL82C106

BUS TIMING

-*----------WC----------==J_____
SA

SA VAllO
tH2

~------

t5------~I_--_+--~

-lOW

so __________1

/
_____
_

tSU3

AEN

FIGURE 7. READ CYCLE

1 . - - - - - - RC-----------,~I
SA

SA VAllO
...~------- t5
tSU1

tH2
l----t---~

- - - -.....-L....I-I~

-lOR

t08

tH9

SO------t----~~__~_
tSU3

AEN

6-212

•

VLSI TECHNOLOGY, INC.
VL82C106

CHIP SELECT TIMING

RGU:=t-t-D1-1--1---:S::-A::VA;;-L~ID~----1 mIt OO~
~

-HCS1!

~~
DAK4

-C
-CS4

1t
-

I'
tD14

,--_ _ __

j r-

1014

-----r~

'---

--~X'-

___

-=S::..:.A..:..:.
VA.:.::.LI_D_ _ _ _~X

___

-lOW

1012
-CS6,
-CS7
(HIW)

Note: Except -eS6 , -CS7 hard-wired.

6-213

•

VLSI TECHNOLOGY, INC.
VL82C106

lOCH ROY TIMING
FIGURE 9.

----I

t18

I--

t20

----I I--

----I I-- t19

SYSCLK
-lOW/-lOR
(COMMAND)

' -__

tD15

--j

IOCHRDY

-csx

r: ®* --j r-

_ _____

tD16

\=S~G1: ~ ~ ~ J®~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~/0

_______________________________

• Programmed number of wait states. 0 - 0 wait state, 1 - 1 wait states, etc.

IOCS16 TIMING
FIGURE 10.

SYSCLK

----I
ALE

t21

I--

r - - - \\~_______________________

--------~I

SA ____________~)(~____S_A_V_A_Ll_D__________________

-lOW/-lOR
(COMMAND)
-CSX

I-- tD13

----I I--

-IOCS16

6-214

to .17

•

VLSI TECHNOLOGY, INC.
VL82C106

IDE INTERFACE TIMING
FIGURE 11. _ _ _ _ _ _ _ _ _~\
~_ _ _ _ _ _ _ _ __

IDINT

~
IRQI

I--tD18

----------~\~--------

SA VALID

-CS5
tD19
-IDENH,
-IDENL

-lOR
SD7
(INPUT)
tD25

-l

tD20

tH26

IDB7
(OUTPUT)

IDB7
(INPUT) _ _ __

-DC
SD7 _ _ _ ,
'--_
(OUTPUT)

-lOR

IDB7

~tD23
~

_ _ _ _ __

6-215

•

VLSI TECHNOLOGY, INC
VL82C106

XDATA CONTROL TIMING
FIGURE 12.
-XDDIR

W27

-XDIRX,
-XDIRS

-CSX

-1

t028
-XDIRX

-XDEN

IID27

-lOR

-lOW/-lOR

t~)

t
t

-1

IID28

I--- ID29
~

6·216

•

VLSI TECHNOLOGY, INC.
VL82C106

RECEIVER TIMING
AGURE 13.

?-____

SIN \
dDATABITS (!HI)
(RECEIVERS
-..:.:TA_R_TL_-l
1
INPUT
\..
DATA)

ClK
SAMPLE

JL--.l-~-~~L--L--~~G~;-~~-~=

INTERRUPT
(DATA READY OR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
RCVRERR)

-lOR

TRANSMITTER TIMING
FIGURE 14.
SERIAL
OUT (SOUT)

DATA (5-8)

'---1.______ PARITY STOP (1-2)

INTERRUPT
(THRE)

(WRTHR)~~~~~~~
-DW

~
-1~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _•

-lOR
(RDIIR)

MODEM TIMING
FIGURE 15.
-lOW ---..

..JL

\---~--t!MOO

(WR MeR) _ _
-RTS, -DTR

\ ff
~OO~

-CTS,-DSR,-DCD _ _ __

-INTERRUPT ----t-~

-lOR
(RDMSR)

-RI

6·217

•

VLSI TECHNOLOGY, INC.
VL82C106

PARALLEL PORT TIMING
FIGURE 16.

DATA

-=f.J~--¥~1=

-STB

-ACK
BUSY

~1.~----tAD----~~
tAK:l==tAK~1

KEYBOARD CONTROLLER TIMING
FIGURE 17.
RECEIVE
• (KSRE (pin 100)) - In PS/2 Mode
KCLK (pin 103)
• (KHSE (pin 101)) - In PS/2 Mode
KDAT (pin 104)

tHOLD 52 Periods of XTAL 1 Input
(2.8 jJ.S @ XTAL1 =18.432 MHz)

• (KSRE - PS/2)
KCLK
• (KHSE - PS/2)
KDAT
tPD = 18 Periods of XTAL1 Input
(976 ns @ XTAL 1 = 18.432 MHz)

Min.

52 Periods of XTAL1 Input
(2.8 jJ.S @ XTAL1 =18.432 MHz)

Max.

• Note: Specifications are identical for KHSE (pin 101) with respect' to KSRE (pin 100) in PS/2 Mode.
6-218

•

VLSI TECHNOLOGY, INC.
VL82C106

REAL TIME CLOCK TIMING
FIGURE 18.

VOO
VBAT Pin

r---------------~/~r----------------------------

~
~

PS Pin

I--tVRTO

CD~______/~r

CDr--------------------

VRT Bit

CD The VRT bit is set to a "1" by reading Register O.

The VRT bit can only be cleared by

pulling the PS pin low (see REGISTER 0 ($00».

-STBY

CRYSTAL OSCILLATOR CONFIGURATIONS
FIGURE 19.

32.768 KHz

18.432 MHz

CIN = COUT = 10·22 pF
CIN may be a trimmer for precision timekeeping applications.

CIN = 10 pF
COUT=30pF

RECOMMENDED CRYSTAL PARAMETERS
Rs:s;son
Co:s; 7pF
CI:S;20pF
Parallel Resonance

Rs (max) :s; 40k n
Co (max):s; 1.7 pF
CI (max):s; 12.S pF
Parallel Resonance

6·219

•

VLSI TECHNOLOGY, INC.
VL82C106

ABSOLUTE MAXIMUM RATING
Ambient Temperature

-1 O·C to + 70·C

Storage Temperature

-65·C to 150·C

Supply Voltage to
Ground Potential -0.5 V to VDD +0.3 V
Applied Output
Voltage
Applied Input
Voltage

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only. Functional operation of this device at these
or any other conditions above those

-0.5 V to VDD +0.3 V
-0.5 V to +7.0 V

Power Dissipation

500 mW

DC CHARACTERISTICS:

=G·C to +70·C, VDD =5 V ±5%, VSS = G V

Symbol

Parameter

Min

VIL

Input Low Voltage
Input Types (All except 12)
Input Type 12

-0.5
-0.5

VIH

Input High Voltage
Input Types 11, 13, 14, 102, 104, lOS, 106
Input Type 12
Input Type 15

VOL

Output Low Voltage
Output Type 01
Output Type 06
Output Type 04, 104, 105
Output Type 02,07,08,102,106

VOH

Output High Voltage
Output Type 01,06
Output Type 105
Output Type 02, 102, 106

IIH

Input High Current
Input Types 11, 13, 14, 15

IlL

Input Low Current
Input Types 11, 15
Input Types 14, 106

ILOL

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Three-State Leakage Current
1/0 Output Types 06, 07,
102, 104, 105

2.0
VOO*0.7
2.4

Max

Units

0.8
VOO*0.2

V
V

VOO+0.5
VOO+0.5
VOO+0.5

V
V
V

0.4
0.4
0.4
0.4

V
V
V
V

10L= 2.0 mA
IOL=4.0mA
IOL-12.0 mA
IOL=24.0 mA

V
V
V

IOH--O.8mA
10H =-2.0 mA
IOH--2.4 mA

2.4
2.4
2.4

-10
-500

IIA

VIN =VOO

-50

IIA
IIA

VIN = VSS + 0.2
VIN = 0.8 V All other pins floatin g.

IIA
IIA

VSS+0.2
VOO

-1.0

V - 0.8 V

-50

100L

Open-Orain Off Current
1/0 Output Type 04

Output Capacitance

Input

CIO

InpuVOutput Capacitance

100
IBAT

-5.0

Operating Supply Current
VBAT Supply Current, Standby Mode

Conditions

5.0
50.0

IIA
IIA

VBAT=3.OV
VBAT=5.0V

Note: For pin types, refer to the Legend and Pin Descriptions on pages 188-191 of this data sheet.
6-220

•

VLSI TECHNOLOGY, INC.
VL82C37A
CMOS DIRECT MEMORY ACCESS (DMA) CONTROLLER

FEATURES

DESCRIPTION

• Low-power CMOS version of popular
8237A DMA controller

The VL82C37A Direct Memory Access
(DMA) Controller serves as a peripheral
interface circuit for microprocessor
systems, and is designed to improve
system performance by allowing
external devices to directly transfer
information from the system memory.
Memory-to-memory transfer capability is
also provided. The VL82C37A DMA
Controller offers many programmable
control features that enhance data
throughput and system performance.
Dynamic reconfiguration is permitted
under program control.

• Four DMA channels
• Individual enable/disable control of
DMA requests
• Directly expandable to any number of
channels
• Independent auto-initialize feature for
all channels
• High performance 8 MHz version
available
• Transfers may be terminated by endof-process input

such as the 8282. In addition to the four
independent channels, the VL82C37A is
expandable to any number of channels
by cascading additional controller
devices.
Three basic transfer modes allow the
user to program the types of DMA
service. Each channel can be individually programmed to auto-initialize to its
original condition following an end-ofprocess (EOP) input. Each channel
also has a 64K address and word count
handling ability.
The VL82C37A DMA Controller is
available in 8 MHz clock frequency.

The VL82C37A is designed to be used
with an external 8-bit address register

• Software controlled DMA requests
• Independent polarity control for
DREQ and DACK signals

PIN DIAGRAMS
VL82C37A

VL82C37A
-MEMW

-lOR
-lOW
-MEMR
-MEMW
VCC
READY
HLDA
ADSTB
AEN
HAQ

1
2
3
4
5
6
7
8

9
10

-CS

CLK
RESET
DACK2
DACK3
DREQ3
DREQ2
DREQ1
DREQO
GND

12
13
14
15
16
17
18
19
20

A7
A6

AS
A4
-EOP
A3
A2
A1
AO
VCC
DBO
DB1
DB2
DB3
DB4
DACKO
DACK1
DB5
DB6
DB7

5 4 3 2 1 44 434241 40

•

7
8
9
10
11
12
13
14
15
16

N.C.
N.C.
HlDA
AOSTB
AEN
HRQ
-CS
ClK
RESET
DACK2
N.C.

39
38
37
36
35
34
33
32
31
30

A2
Al
AO

vee
DBO
DBl
DB2
DB3
DB4
N.C.

lB 1920 21 22 23 24 2526 27 2B

DRE02

ORDER INFORMATION
Part
Number
VL82C37 A-08PC
VL82C37 A-08QC

Clock
Frequency
8MHz

Package
Plastic DIP
Plastic L~aded Chip Carrier (PLCC)

Note: Operating temperature range is O·C to +70·C.
6-221

•

VLSI TECHNOLOGY, INC.
VL82C37A

BLOCK DIAGRAM
-EOP
RESET

-CS
READY
ClK
AEN
ADSTB

DECREMENTER

INC/DECREMENTER

TEMP WORD
COUNT REG (16)

TEMP ADDRESS
REG (16)

TIMING
AND
CONT

16 BIT BUS
16 BIT BUS

-MEMR
-MEMW

READ BUFFER

-lOR

BASE:
BASE
ADDR : WORD CNT

-lOW

CURRENT: CURRENT
ADDR: WORD CNT

4
DREOO-DREQ3~ PRIORITY

HlDA~ ENCODER
AND
HRO
ROTATING
PRIORITY
DACKO-DACK3
lOGIC

TABLE 1. INTERNAL REGISTERS
Name

Size

Number

Base Address Registers

16 bits

Base Word Count Registers

16 bits

Current Address Registers

16 bits

Current Word Count Registers

16 bits

Temporary Address Register

16 bits

Temporary Word Count Register

16 bits

Status Register

B bits

Command Register

B bits

Temporary Register

Bbits

Mode Registers

6 bits

Mask Register

4 bits

Request Register

4 bits

6-222

COMMAND
CONTROL

•

VLSI TECHNOLOGY, INC.
VL82C37A

SIGNAL DESCRIPTIONS
Signal
Name

PIn
tlImber

CLK

Clock Input - Controls the internal operations of the VL82C37A DMA Controller and its rate of data transfers. This input may be driven at up to 8
MHz for the VL82C37A-08.

-CS

Chip Select - An active low input used to select the VL82C37A as an 110
device during the idle cycle, allows CPU communication on the data bus.

RESET

Reset - An active high input that clears the Command, Request, and Temporary Registers, clears the first/last flip-flop, and sets the Mask Register.
The device is in the idle cycle following a RESET signal.

READY

Ready - An input that extends the memory read and write pulses from the
VL82C37A accommodating slow memories or 110 peripheral devices.
During its specified setup/hold time, READY must not make transitions.

HLDA

Hold Acknowledge - This active high signal from the CPU indicates that it
has relinquished control of the system buses.

DREOO-DRE03

19-16

DMA Request - These lines are individual asynchronous channel request
inputs. Peripheral circuits use these lines to obtain DMA service. In fixed
priority, DREOO has the highest priority and DRE03 has the lowest priority.
Activating the DREO line of a channel generates a request. DACK then
acknowledges the recognition of DREO signal. Polarity of DREO is programmable. RESET initializes theS1illines to active high. DREO must be
sustained until the corresponding DACK becomes active.

DBO-DB7

30-26,
23-21

-lOR

Signal
Type

Signal

Description

110

Data Bus - These lines are bidirectional, three-state signals that connect to
the system data bus. The outputs are enabled in the program condition
during the 110 read to output the contents of an Address Register, a Status
Register, the Temporary Register, or a Word Count Register to the CPU.
The outputs are disabled and the inputs are read during an 110 Write cycle
when the CPU is programming the VL82C37A control registers. During
DMA cycles the most significant eight bits of the address are sent onto the
data bus and are strobed into an external latch by ADSTB. In memory-tomemory operations, data from the memory comes into the VL82C37A on
the data bus during the read-from-memory transfer. In the write-to-memory
transfer, the data bus outputs determine the placement of the data, not the
new memory location.

110

I/O Read - This is a bidirectional, active low, three-state line. In the idle
cycle, it is an input control signal used by the CPU to read the control
registers. In the active cycle, it is an output control signal used by the
VL82C37A to access data from a peripheral during a DMA Write transfer.

-lOW

I/O

110 Write - This signal is a bidirectional active low, three-state line. It is
used by the CPU to load information into the VL82C37A DMA Controller.
In the active cycle, it is used as an output control signal used by the
VL82C37A to load data to the peripheral during a DMA read transfer.

-EOP

I/O

End of Process - This is an active low bidirectional signal, which provides
data on the completion of DMA services and is available at the bidirectional
-EOP pin. The VL82C37A allows an external signal to terminate an active
DMA service, by pulling the -EOP input low with an external -EOP signal.
The VL82C37A also generates a pulse when the terminal count (TC) for
any channel is achieved. This generates an -EOP signal that is active on
the -EOP line. When -EOP is received, either internally or externally, it will
cause the VL82C37A to terminate the service, reset the request, and, if
auto-initialize is enabled, to write the base registers to the current registers

6-223

•

VLSI TECHNOLOGY, INC.
VL82C37A

SIGNAL DESCRIPTIONS (ConL)
Signal
Name

PIn
~mber

Signal
Type

SIgnal
Description
of that channel. The mask bit and TC bit in the status word will be set for
the currently active channel by -EOP, unless the channel is programmed
for auto-initialize. In that case, the mask bit remains unchanged. During
memory-to-memory transfers, -EOP will be output when the TC for
channel 1 occurs. To prevent erroneous end-of-process inputs, -EOP
should be tied high with a pull-up resistor if it is not used.

AO-A3

32-35

The four least significant address lines - These lines are bidirectional threestate signals. In the idle cycle, they are inputs used by the CPU to
address the register to be loaded or read. In the active cycle they are
outputs that provide the lower four bits of the output address to the system.

A4-A7

37-40

The four most significant address lines - These lines are three-state
outputs that provide four bits of address. They are enabled only during the
DMA service.

HRO

Hold Request - This is the hold request to the CPU. It is used to request
control of the system bus. If the corresponding mask bit is clear, the
presence of any valid DREO causes the VL82C37A to issue the HRO
signal. After HRO is asserted, at least one clock cycle (TCY) must occur
before HLDA can be valid.

DACKO - DACK3

25,24,14,
15

DMA Acknowledge - This signal is used to notify an individual peripheral
when it has been granted a DMA cycle. The sense of these lines is
programmable; RESET initializes them to an active low.

AEN

Address Enable - This active high line enables the 8-bit latch containing the
upper eight address bits onto the system address bus. It can also be used
to disable other system bus drivers during DMA transfers.

ADSTB

Address Strobe - This active high is used to strobe the upper address byte
into an external latch.

-MEMR

Memory Read - This active low signal is a three-state output used to
access data from a selected memory location during a DMA read or
memory-to-memory transfer.

-MEMW

Memory Write - This signal is an active low three-state output used to write
data to a selected memory location during a DMA write or memory-tomemory transfer.

VCC

5,31

+5 V ±5% power supply

GND

Ground.

6-224

•

VLSI TECHNOLOGY, INC.
VL82C37A

FUNCTIONAL DESCRIPTION
The internal registers and major logic
blocks of the Vl82C37A are shown in
the block diagram. Data interconnection
paths are also shown, but the various
control signals between the blocks are
not. The Vl82C37 A contains 344 bits of
internal register memory. Table 1 describes these registers and shows them
by size. A complete description of the
registers and their functions can be
found in the Register Descriptions
section.
The Vl82C37A contains three basic
control logic blocks. The Timing Control
block generates internal timing and
external control signals for the
Vl82C37A. The program command
control block decodes the various
commands given to the VL82C37A by
the microprocessor before servicing a
DMA Request. Further, it decodes the
mode control word used to select the
type of DMA during the servicing. The
priority encoder block settles priority
contention between DMA channels
requesting service at the same time.
DMA OPERATION
The VL82C37A is designed to operate
in two major cycles: the idle and active.
Several states are contained in each
device cycle. The Vl82C37A supports
seven separate states, each being one
full clock period. State I (SI), the
inactive state, is entered when the
VL82C37A has no valid DMA requests
pending. While in SI, the DMA controller
is inactive but may be in the program
condition, being programmed by the
processor. State 0 (SO) is the first state
of a DMA service. The VL82C37A has
requested a hold, but the processor has
not yet responded with an acknowledge.
The Vl82C37A may still be programmed DA from the CPU. An acknowledge from the CPU signals that
DMA transfers may begin. S1, S2, S3
and S4 are the functional states of the
DMA service. If more time is needed to
complete a transfer than is available
with normal timing, wait states (WS) can
be placed between S2 or S3 and S4 by
using the Ready line on the VL82C37 A.
The data is transferred directly from the
VO device to memory (or vice versa)
with -lOR and -MEMW (or -MEMR and
-lOW) being active simultaneously. The
data is not read into or driven out of the

Vl82C37A during I/O-to-memory or
memory-to-VO DMA transfers.
To complete memory-to-memory
transfers requires a read-from and a
write-to-memory. The states, which
resemble the normal working states, use
two-digit numbers for identification.
Eight states are needed for each
transfer: the first four states (S11, S12,
S13, S14), are used for read-frommemory and the last four states (S2t,
S22, S23, S24), for the write-to-memory
of the transfer.

IDLE CYCLE
When no channels are requesting
service, the Vl82C37A enters the idle
cycle and performs Sl states, sampling
the DREQ lines every clock cycle to
determine if any channel is requesting a
DMA service. The device also samples
-eS, looking for an attempt by the
microprocessor to write or read to the
internal registers of the VL82C37A.
When -eS is low and HlDA is low, the
Vl82C37A initiates the program
condition. The CPU now establishes,
changes or inspects the internal
definition of the part by reading from or
writing to the internal register. Address
lines AO-A3 are inputs to the device.
They select registers that will be read or
written. The -lOR and -lOW lines are
used to select and time reads or writes.
Because of the number and size of the
internal registers, an internal flip-flop is
used to generate one more bit of
address. This bit is used to determine
the upper or lower byte of the 16-bit
address and Word Count Registers.
This flip-flop can be reset by a separate
software command.
Special software commands executed in
the Vl82C37A during the program
condition are decoded as sets of
addresses with the -CS and -lOW
signals. The commands do not use the
data bus. Clear FirsVLast Flip-Flop and
Master Clear instructions are included.

ACTIVE CYCLE
When the Vl82C37A is in the idle cycle
and a nonmasked channel requests a
DMA service, the device outputs an
HRQ to the microprocessor and then
enters the active cycle. During this
cycle the DMA service takes place, in
one of four modes.

6-225

In the single transfer mode, the device is
programmed to make only one transfer.
The word count is decremented and the
address decremented or incremented,
foHewing each transfer. When the word
count is completed from zero to FFFFH,
a Terminal Count (TC) causes an autoinitialize if the channel has been so
programmed.
The DREQ signal must be held active
until DACK becomes active, in order to
be recognized. If DREQ is held active
for the entire single transfer, HRQ will
become inactive and release the bus to
the system. It again goes active and,
upon receipt of a new HLDA, another
single transfer is performed. In 8080A,
8085AH, 8088, or 8086 systems this ,:
insures one full machine cycle execution
between DMA transfers. Details of
timing between the VL82C37A and
other bus control protocols depends
upon the characteristics of the microprocessor involved.
In the block transfer mode, the device is
activated by the DREQ signal to
continue making transfers during the
service until a TC, caused by word count
going to FFFFH, or an external end of
process (-EOP) is encountered. DREQ
need only be held active until DACK
becomes active. An auto-initialization
will occur at the end of the service, if the
channel has been programmed for it.
In the demand transfer mode the device
is programmed to continue making
transfers until a TC or external -EOP is
encountered or until the DREQ signal
goes inactive. Transfers may continue
until the 1/0 device has exhausted its
data capacity. After the I/O device has
caught up, the DMA service is reestablished by a DREQ signal. During
the interval between services, when the
microprocessor is operating, the
intermediate values of address and
word count are stored in the Vl82C37A
Current Address and Current Word
Count Registers. Only an -EOP can
cause an auto-initialize at the end of the
service. -EOP is generated either by
TC or by an external signal.
The fourth mode cascades multiple
Vl82C37As together for easy system
expansion. The HRQ and HlDA signals

•

VLSI TECHNOLOGY, INC.
VL82C37A

from additional VL82C37As are connected to the DREO and DACK signals
of a channel of the primary VL82C37 A.
This permits the DMA requests of the
additional device to propagate through
the priority network circuitry of the
preceding device. The priority chain is
not broken, and the new device waits for
its turn to acknowledge requests. As the
cascade channel of the primary
VLB2C37A is used only to prioritize the
additional device, it does not produce
any address or control signals of its
own, which could conflict with the
outputs of the active channel in the
added device. The VL82C37A responds
to the DREO and DACK signal, but all
other outputs except HRO are disabled.
Figure 8 shows two devices cascaded
into a primary device using two of the
previous channels. This forms a twolevel DMA system. More VL82C37A's
could be added at the second level by
using the remaining channels of the first
level. More devices can also be
cascaded into the channels of the
second level devices, forming a third
level.
TRANSFER TYPES
Each of the three modes of active
transfer can perform three different
types of transfers: read, write and
verily. Write transfers move data from
an 1/0 device to the memory by activating -MEMW and -lOR; read transfers
move data from memory to an 110
device by activating -MEMR and -lOW.
Verily transfers are pseudo routines:
the VLB2C37A DMA Controller operates
as in read or write transfers generating
addresses, and responding to -EOP,
and other operations. The memory and
1/0 control lines remain inactive. The
Verify Mode is not permitted during
memory-to-memory operation.
To perform block moves of data from
one memory address space to another
with a minimum of programming, the
VLB2C37A includes a memory-tomemory transfer feature. Programming
a bit in the Command Register selects
channels 0 and 1 to operate as memoryto-memory transfer channels. The
transfer is initiated by setting the
software DREO for channel o. The
VL82C37A requests a DMA device as
usual. After HLDA is true, the device,

using eight-state transfers in block
transfer mode, reads data from the
memory. The channel 0 Current
Address Register is the source for the
address, and is decremented or
incremented as usual. The data byte
read from the memory is then stored in
the VL82C37A internal Temporary
Register. Channell writes the data
from the Temporary Register to memory
using the address in its Current Address
Register and incrementing or decrementing it as usual. The channel 1
current word count is decremented.
When the word count goes to FFFFH, a
TC is generated causing an -EOP
output terminating the service.
Channel 0 may be programmed to hold
the same address for all transfers, which
permits a single word to be written to a
block of memory.
The VL82C37A responds to external
-EOP signals during memory-tomemory transfers. In block search
schemes data comparators may use this
input on finding a match. The timing of
memory-to-memory transfers is shown
in Figure 10. Memory-to-memory
operations can be detected as an active
AEN signal with no DACK outputs.
A channel may be set up to autoinitialize by setting a bit in the Mode
Register. During initialization, the
original values of the Current Address
and Current Word Count Registers are
automatically restored from the Base
Address and Base Word Count Registers of that channel following -EOP.
The base registers and the current
registers are loaded at the same time.
They remain unchanged thoughout the
DMA service. The mask bit is not set
when the channel is in auto-initialize.
Following auto-initialize, the channel is
prepared to perform another DMA
service, without CPU action, as soon as
a valid DREO is detected.
The VL82C37A has two types of priority
encoding available as software-selectable options. The fixed priority
option sets the channels in priority order
based upon the descending value of
their number. The channel with the
lowest priority is 3, then 2, 1 and the
highest priority channel is o. After
recognizing anyone channel for service,
the other channels are prevented from

6-226

interferring with that service until it is
completed.
In the rqtating priority option, the last
channel to get service becomes the
lowest priority channel with the others
rotating in order.
Rotating priority allows a single chip
DMA system. Any device requesting
service is guaranteed to be recognized
after no more than three higher priority
services have occurred. This prevents
anyone channel from dominating the
system.
To achieve even greater throughput
where system characteristics permit, the
VL82C37A DMA Controller can compress the transfer time to two clock
cycles. 8tate 83 is used to extend the
access time of the read pulse. By
removing state 83, the read pulse width
is made equal to the write pulse width,
and a transfer consists only of state 82
to change the address and state 84 to
perform the readlwrite. 81 state still
occurs when AB-A 15 need updating
(see the Address Generation section.)
To reduce pin count, the VL82C37A
multiplexes the eight higher order
address bits on the data lines. State 81
is used to output the higher order
address bits to an external latch, where
they may be placed on the address bus.
The falling edge of the Address Strobe
(ADSTB) is used to load these bits from
the data lines to the latch. Address
Enable (AEN) is used to enable the bits
onto the address bus through a threestate enable. The lower order address
bits are directly sent by the VL82C37A.
Lines AO-A7 are connected to the
address bus.
During block and demand transfer mode
services, including multiple transfers, the
addresses generated will be in order.
During a large number of transfers the
data held in the external address latch
will not change. This data will change
when a carry or borrow from A7 to A8
takes place in the normal order of
addresses. To expedite transfers, the
VL82C37A DMA Controller executes S1
states only when needed to update A8A15 in the latch. For long services, S1
states and address strobes may occur
only once every 256 transfers, a savings
of 255 clock cycles for each 256
transfers.

•

VLSI TECHNOLOGY, INC.
VL82C37A

REGISTER DESCRIPTION
Current Address Register: Each
channel has a 16-bit Current Address
Register. This register holds the value
of the address used during DMA
transfers. The address is automatically
incremented or decremented after each
transfer and the intermediate values of
the address are stored in the Current
Address Register throughout the
transfer. The microprocessor reads this
register in successive B-bit bytes. It may
also be reinitialized by an auto-initialize
to its original value which takes place
only after an -EOP.
Current Word Register: Each channel
has a 16-bit Current Word Count
Register that determines the number of
transfers to be performed. The actual
number of transfers is one more than
the number programmed in the Current
Word Count Register; programming a
count of 100 will result in 101 transfers.
The word count is decremented after
each transfer; the intermediate value of
this word count is stored in the register
during the transfer. When the value in
the register goes from 0 to FFFFH, a TC
is generated. The register is then
loaded or read in successive B-bit bytes
by the microprocessor in the program
condition. Following the end of a DMA
service, it may also be reinitialized by an
auto-initialization to its original value
which occurs only on -EOP. H it is not
auto-initialized, this register has a count
of FFFFH after TC.
Base Address and Base Word Count
Registers: Each channel has a pair of
16-bit Base Address and Base Word
Count Registers that store the original
value of their associated current
registers. Throughout auto-initialization
these values are used to restore the
current registers to their original values.
The base registers are written at the
same time with their corresponding
current register in B-bit bytes in the
program condition by the microprocessor. These registers cannot be read by
the microprocessor.
Command Register: This B-bit register
controls the operation of the VlB2C37A,
is programmed by the microprocessor in
the program condition and is cleared by
reset or a master clear instruction.
Figure 2 lists and describes the function
of the command bits.

Mode Register: All channels have a 6bit Mode Register. When the register is
being written to by the microprocessor in
the program condition, bits 0 to 1
determine which channel the Mode
Register is to be written.
Request Register: The VlB2C37A can
responds to requests for DMA service
that are initiated by software as well as
by a DREQ signal. Each channel has a
request bit associated with it in the 4-bit
Request Register. These are nonmaskable and can be prioritized by the
priority encoder network.
Each register bit is set or reset separately under software control, or is
cleared upon generation of a TC or
external-EOP. The entire register is
cleared by a Reset. To set or reset a
bit, the software loads the correct form
of the data word. Table 2 shows
register address coding. To make a
software request, the channel must be in
block mode.
Mask Register: Each channel has an
associated mask bit that can be set to
disable the incoming DREQ signal. A
mask bit is set when its associated
channel produces an -fOP, if the
channel is not programmed for autoinitialize. Any bit of the 4-bit Mask
Register may also be set or cleared
separately under software control. The
entire register is set by a reset, which
disables all DMA requests until a clear
Mask Register instruction allows them to
occur. This instruction to separately set
or clear the mask bits is similar in form
to that used with the Request Register.
Status Register: The Status Register is
available to be read out of the
VlB2C37A DMA Controller by the
microprocessor and contains information
about the status of the devices at this
point. This information includes which
channels have reached a terminal count
and which channels have pending DMA
requests.
Bits 0-3 are set each time a TC is
reached by that channel or an external
-EOP is applied and are cleared upon
reset and on every status read. Bits 4
through 7 are set whenever their
corresponding channel is requesting
service.

6-227

Temporary Register: The Temporary
Register is used to hold data during
memory-to-memory transfers. The last
word moved can be read by the microprocessor in the Program Condition
following the completion of the transfers.
The Temporary Register always
contains the last byte transferred in the
previous memory-to-memory operation,
unless cleared by a reset.
Software Commands: These additional
special software commands can be
executed in the program condition and
do not depend on any specific bit pattern
on the data bus.
The clear firsVlast flip-flop command is
executed prior to writing or reading new
address or word count information to the
VLB2C37A. This initializes the flip-flop
to a known state so that subsequent
accesses to register contents by the
microprocessor will address upper and
lower bytes in the correct sequence.
The Master Clear software instruction
has the same effect as the hardware
reset. The Command, Status, Request,
Temporary, and Internal FirsVlast FlipFlop Registers are cleared and the Mask
Register is set. The VLB2C37 A enters
an idle cycle.
The Clear Mask Register command
clears the mask bits of all four channels,
enabling them to accept DMA requests.
PROGRAMMING
The VlB2C37A DMA Controller accepts
programming from the host processor
any time that HLDA is inactive, even if
the HRQ signal is active. The host must
assure that programming and HLDA are
mutually exclusive. A problem can
occur if a DMA request occurs, on an
unmasked channel while the VLB2C37A
is being programmed.
For example, the CPU may be starting
to reprogram the two-byte Address
Register of a channel when that channel
receives a DMA request. If the
VlB2C37A is enabled (bit 2 in the
command register is 0) and that channel
is unmasked, a DMA service will occur
after one byte of the Address Register
has been reprogrammed. This can be
avoided by disabling the controller
(setting bit 2 in the command register) or
masking the channel before programming another register. Once the

•

VLSI TECHNOLOGY, INC.
VL82C37A

programming is complete, the controller
can be enabled (unmasked).

After power-up all internal locations,
including the Mode Registers, should

be loaded with a valid value. This
should be done to unused channels as
well.

When the processor replies with a HLDA
signal, the VL82C37A takes control of
the address, data, and control buses.
The address for the first transfer
operation is output in two bytes - the
least significant eight bits on the eight
address outputs, and the most significant eight bits on the data bus. The
contents of the data bus are then

latched into the 8282 8-bitlatch to
complete the full 16 bits of the address
bus. The 8282 is a high-speed, 8-bit,
three-state latch in a 20-pin DIP
package. After the initial transfer takes
place, the latch is updated only after a
carry or borrow is generated in the least
significant address byte. Four DMA
channels are available when one
VL82C37A DMA Controller is used.

APPLICATION
Figure 1 shows a convenient method for
configuring a DMA system with the
VL82C37A DMA Controller and an
8080Al8085AH microprocessor system.
Whenever there is at least one valid
DMA request from a peripheral device,
the multimode VL82C37A DMA Controller issues a HRC to the processor.

FIGURE 1. SYSTEM INTERFACE

I\.

ADDRESS BUS AO·A15

L';:..
AS-A15

.........

-OE
STB

AO-A15
BUSEN
HlDA
HOLD

CPU

AEN
HlDA
HRO

AO-IU

A4-A7

-CS

VL82C37A

RESET-MEMW

-lOW

DACKO-3

8282
8-BITLATCH
L.

ADSTB
DBODB7

A --'\

-r-V

ClK I-MEMRI -lOR I DREOO-3 I
CLOCK
RESET

f4 i4

}~~

-MEMR
-MEMW

BUS

-lOR
-lOW
DBO-DB7

'-.7

I\.

SYSTEM DATA BUS

6-228

•

VLSI TECHNOLOGY, INC.
VL82C37A

FIGURE 2. COMMAND REGISTER
7

4 3

0 ~ Bit
Number

111111111

0
1

Memory-to-memory disable
Memory-to-memory enable

0
1
X

Channel 0 address hold disable
Channel 0 address hold enable
IfbitO=O

0
1

Controller enable
Controller disable

0
1
X

Normal timing
Compressed timing
IfbitO=1

0
1

Fixed priority
Rotating priority

0
1
X

Late write selection
Extended write selection
Ifbit3K1

0
1

DREO sense active high
DREO sense active low

0
1

DACK sense active low
DACK sense active high

FIGURE 3. MODE REGISTER
76543210~

I I I I I I I I I

Bit
Number

00
01
10
11

Channel 0 Select
Channel 1 Select
Channel 2 Select
Channel 3 Select

00
01
10
11
XX

Verify transfer
Write transfer
Read transfer
Illegal
Ifbits6and7=11

Auto-initialization disable
Auto·initialization enable

o
1

Address increment select
Address decrement select

00
01
10
11

Demand mode select
Single mode select
Block mode select
Cascade mode select

6·229

•

VLSI TECHNOLOGY, INC.
VL82C37A
FIGURE 6. MASK REGISTER (SELECT MODE)

FIGURE 4. REQUEST REGISTER

Bit

7 6 5 4 3 2 1 0 + - - B1t
Number

765432104--Numbar

I I I I I I I I I

I I I

I
Don't
care

-r-

Select channel 0
Select channel 1
Select channel 2
Select channel 3

00
01
10
11

Don't
care

Clear mask bit
Set mask bit

FIGURE 7. MASK REGISTER (MASK MODE)

7 6 5 4 3 2 1 0 + - - Bit
Number

O+-- Bit

IE!

01 Select channel 1 mask bit
10 Select channel 2 mask bit
11 Select channel 3 mask bit
1

FIGURE 5. STATUS REGISTER

00 Select channel 0 mask bit

Reset request bit
Set request bit

111111111

Number

Channel 0 has reached TC
Channel 1 has reached TC
Channel 2 has reached TC
Channel 3 has reached TC
Channel
Channel
Channel
Channel

t:=

Don'!
care

0 request
1 request
2 request
3 request

TABLE 2. REGISTER CODES
Signals
Register

Operation

Command

Write

-CS

-lOR -lOW
1

Mode

Write

Request

Write

Mask

SetlReset

Mask

Write

Temporary

Read

Status

Read

6·230

0
1

Clear channel 0 mask bit
Set channel 0 mask bit

0
1

Clear channel 1 mask bit
Set channel 1 mask bit

0
1

Clear channel 2 mask bit
Set channel 2 mask bit

0
1

Clear channel 3 mask bit
Set channel 3 mask bit

•

VLSI TECHNOLOGY, INC
VL82C37A

TABLE 3. SOFTWARE COMMAND CODES
Signals
A3

Operation'

-lOR

-lOW

Read Status Register

Write Command Register

Illegal

Write Request Register

Illegal

Write Single Mask Register Bit

Illegal

Write Mode Register

Illegal

Clear Byte Pointer Flip/Flop

Read Temporary Register

Master Clear

Illegal

Clear Mask Register

Illegal

Write All Mask Register Bits

FIGURE 8. CASCADED Vl82C37A CONTROLLERS
2ND LEVEL

MICROPROCESSOR

Vl82C37A

1ST LEVEL
HRQ

DREQ

HLDA

DACK

1f-----

DREQ

HRQ

DACK

f----

HLDA

Vl82C37A

INITIAL DEVICE

Vl82C37A

ADDITIONAL DEVICES

6-231

VLSI TECHNOLOGY, INC.
VL82C37A
TABLE 4. WORD COUNT AND ADDRESS REGISTER COMMAND CODES
Channel

Signals

Operation

Base and Current Address

Write

0
0

1
1

Current Address

Read

0
0

Base and Current Word Count

Write

Current Word Count

Internal
Flip-Flop

Data Bus
DBD-DB7

0
0

0
1

AO-A7
A8-A15

0
0

1
1

0
0

0
1

AO-A7
A8-A15

0
0

1
1

0
0

1
1

0
1

WO-W7
W8-W15

Read

0
0

1
1

0
0

1
1

0
1

WO-W7
W8-W15

Base and Current Address

Write

0
0

1
1

0
0

1
1

0
0

0
1

AO-A7
A8-A15

Current Address

Read

0
0

1
1

0
0

1
1

0
0

0
1

AO-A7
A8-A15

Base and Current Word Count

Write

0
0

1
1

0
0

1
1

0
1

WO-W7
W8-W15

Current Word Count

Read

0
0

1
1

0
0

1
1

0
1

WO-W7
W8-W15

Base and Current Address

Write

0
0

1
1

0
0

1
1

0
0

0
1

AO-A7
A8-A15

Current Address

Read

0
0

1
1

0
0

1
1

0
0

0
1

AO-A7
A8-A15

Base and Current Word Count

Write

0
0

1
1

0
0

1
1

0
0

1
1

0
1

WO-W7
W8-W15

Current Word Count

Read

0
0

1
1

0
0

1
1

0
0

1
1

0
1

WO-W7
W8-W15

Base and Current Address

Write

0
0

1
1

0
0

1
1

0
0

0
1

AO-A7
A8-A15

Current Address

Read

0
0

1
1

0
0

1
1

0
0

0
1

AO-A7
A8-A15

Base and Current Word Count

Write

0
0

1
1

0
0

1
1

0
1

WO-W7
W8-W15

Current Word Count

Read

0
0

1
1

0
0

1
1

0
1

WO-W7
W8-W15

-CS

-lOR -lOW

6-232

•

VLSI TECHNOLOGY, INC.
VL82C37A

TABLE 5. DMA MODE AC CHARACTERISTICS
Symbol

Parameter

Vl82C37A·OS
Max
Min

Unit
ns

TAEl

AEN High from ClK Low (Sl) Delay lime

105

TAET

AEN low from ClK High (Sl) Delay lime

TAFAB

ADR Active to Float Delay from ClK High

TAFC

Read or Write Float from ClK High

135

TAFDB

DB Active Float Delay from ClK High

TAHR

ADR from Read High Hold lime

TCY·75

TAHS

DB from ADSTB low Hold lime

TAHW

ADR from Write High Hold lime

TCY·50

DACK Valid from ClK low Delay lime (Note 7)

105

-EOP High from ClK High Delay lime (Note 10)

105

-EOP low from CLK High Delay lime

105

TASM

ADR Stable from ClK High

105

TASS

DB to ADSTB low Setup lime

TCH

Clock High lime (Transitions s; 10 ns)

TAK

TCl

Clock Low lime (Transitions S; 10 ns)

TCY

ClK Cycle lime

TOCl

ClK High to Read or Write low Delay (Note 4)

120

TDCTR

Read High from ClK High (54) Delay lime (Note 4)

115

TOCTVI<

Write High from ClK High (S4) Delay (Note 4)

TOOl
TOO2

HRO Valid from ClK High Delay lime (Note 5)

TEPS

-EOP low from ClK low Setup lime

TEPW

-EOP Pulse Width

TFAAB

ADR Float to Active Delay from ClK High

TFAC

Read or Write Active from ClK High

TFADB

DB Float to Active Delay from ClK High

THS

HlDA Valid to ClK High Setup lime

TIDH

125

135

ns
100

110

Input Data from -MEMR High Hold lime

TIDS

Input Data to -MEMR High Setup lime

TODH

Output Data from -MEMW High Hold lime

TODV

Output Data Valid to -MEMW High

TOS

DREO to ClK low (51,54) Setup lime

TRH

ClK to READY low Hold lime

TRS

READY to ClK low Setup lime

TSTl

ADSTB High from ClK High Delay lime

110

TSTT

ADSTB low from ClK High Delay lime

Explanatory notes follOW DC Characteristics Table.

6·233

•

VLSI TECHNOLOGY, INC.
VL82C37A

FIGURE 9. OMA TRANSFER TIMING (SEE TABLE 5.)

eLK

OREQ

HRQ
HI..DA

~>-C~rUL~':~':~{:~':~~d,: ~~~~,
fLJ, roa __

Jf"

THS~

IIIJ

\~ \1\ \ \ ~

roa-..-

~
TAEl

,--

"-~STl
,.lADS

...

I-

~Tsn

I....

"""'- --""

OBO-OB7

....

.... ~m

TAFDB

DACK
lFAC
-IOR.-MEUR

TASM

11.

.c-~
~

TOOTW

~
TDCll4(FOR EXTENDED WRITE)
INT/-EOP

TAET

I~TAFAB

TAHW

IJDC~

TOOTR

I--TAI<

TAHW

ADDRESS VALID

.~TAHR

~W.-.MEMW

ADDRESS VAliD

M-A7

TEPS

TASS
TAHS

:AI-A15

lFla

14-

,\ \ l\ \ \ \ \ \ \ \ \

... U
f't

AEN

M~ ~,
r-

~TAHR

TDCTR

4- ~'---. 4-TAFC

TOOTW

f4-

:t,

r--t

r----...

14- f-

TAK

~ r--TAl<

TEPW

\\\\\\\\\\\

EXT/-EOP
TAEL
AEN'

~////////, '///
.....

TAET

.ft

• tn 'Cascade Mode the AEN signal returns low in the 54 cycle one cycle earlier than when in single transfer mode.

6-234

•

VLSI TECHNOLOGY, INC.
VL82C37A

FIGURE 10. MEMORY-TO-MEMORY TRANSFER nMING (SEE TABLE 5)

811

812

813

821

814

AD8TB

AO-A7

DBO-DB7

-MEMR

-MEMW

-EOP
EXT rEOP --..........-......."'"

6-235

822

823

824

•

VLSI TECHNOLOGY, INC.
VL82C37A

TABLE 6. PERIPHERAL MODE AC CHARACTERISTICS
VLB2C37A-08
Symbol

Parameter

Min

Max

Unit

TAR

ADR Valid or -CS Low to Read Low

TAW

ADR Valid to Write High Setup TIme

TCW

CS Low to Write High Setup TIme

TOW

Data Valid to Write High Setup TIme

TRA

ADR or CS Hold from Read High

TRDE

Data Access from Read Low (Note 3)

TRDF

DB Reat Delay from Read High

TRSTD

Power Supply High to RESET Low Setup TIme

TRSTS

RESET to Rrst -IOWR

TRSTW

120

500

2TCY

RESET Pulse Width

300

TRW

READ Width

155

TWA

ADR from Write High Hold TIme

TWC

CS High from Write High Hold Time

TWO

Data from Write High Hold Time

TWWS

Write Width

100

Explanatory notes follow DC Characteristics

FIGURE 11. SLAVE MODE WRITE TIMING (SEE TABLE 6)

TCW

-CS

TWWS
-lOW

..
Ao-A3

TWA
lAW
INPUT VALID

TOW
080-087

INPUT VAllO

6-236

•

VLSI TECHNOLOGY, INC.
VL82C37A

FIGURE 12. SLAVE MODE READ TIMING (SEE TABLE 6)

-CS

AD-A3

~
..TA

-lOR

~14----

_ _______
DBo-DB7

ADDRESS MUST BE VALID

TRA

~Jt
I

TRW

~~~~~-_==-_==-_=~_TR-_-D~E~~-_=~-_=~-_=~~.;t---.--~"1---TRDF-4
1
=tDATA OUT VALID

FIGURE 13. READY TIMING (SEE TABLE 5)

ClK
-READ

----------+--_
TDCl - -......~~

-WRITE

....--t....-TDCl

TDCTW

--------~I__-__i..

EXTENDED~' ..... _ _ _
WRITE
TRH

-.~----t------+---+-.J

READY

6·237

•

VLSI TECHNOLOGY, INC.
VL82C37A

FIGURE 14. COMPRESSED TRANSFER TIMING (SEE TABLE 5)

ClK

AO-A?

-READ

-WRITE

READY

INT/-EOP
TEP5

14--~
~--TEPW--......

EXT/-EOP

FIGURE 15. RESET TIMING (SEE TABLE 6)

vcc _____/

rt------

...

TR5TD

------~.~I

........1 - - - TRSTW

---~...~

\<-

RESET

~---------

~:R:TS~
I

---------------------~I

-lOR OR -lOW

~---

6-238

•

VLSI TECHNOLOGY, INC.
VL82C37A

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
-0.5 to 7.0 V
Input Voltage
-0.5 to 5.5 V
Output Voltage
-0.5 to 5.5 V
Operating Temperature O°C to + 150°C
Storage Temperature -65°C to + 150°C

Stresses above those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any

other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device
reliability.

DC CHARACTERISTICS:
Symbol
VOH

Parameter

Min

Typ (1)

Max

Unit

Test Conditions

2.4

10H = -200 I1A

3.3

10H = -100 !LA (HRQ Only)

10L = 2.0 mA (data bus) -EOP
10L z 3.2 mA (other outputs) (8)
10L = 2.5 mA (AOSTB) (8)

Output High Voltage

450

VOL

Output Low Voltage

VIH

Input High Voltage

2.2

VIL

Input Low Voltage

-0.5

0.8

III

Input Load Current

±10

!LA

ILO

Output Leakage Current

±10

I1A

0.45 V s VOUT ~ VCC

ICC

VCC Supply Current

Clk. Freq. = S MHz

Output Capacitance

Input Capacitance

CIO

I/O Capacitance

VCC+0.5

OV~VIN~VCC

1.0 MHz, Inputs = 0 V

AC and DC Characteristics Notas:
1. Typical values are for TA = 25°C, nominal supply voltage, and nominal processing parameters.
2. Input timing parameters assume transition times of 20 ns or less. Waveform measurement points for both input and
output signals are 2.0 V for high and 0.8 V for low, unless otherwise noted.
3. Output loading is one TTL gate plus 150 pF capacitance, unless otherwise noted.
4. The net -lOW or -MEMW pulse width for normal write will be TCY-100 ns and for extended write will be 2TCY-100 ns.
The net -lOR or -MEMR pulse width for normal read will be 2TCY-50 ns and for compressed read will be TCY-50 ns.
5. TOQ is specified for two different output high levels: TOQ1 is measured at 2.0 V, TOQ2 is measured at3.3 V. The value
for TOQ2 assumes an external 3.3 kn pull-up resistor connected from HRQ to VCC.

6. OREQ should be held active until OACK is returned.
7. OREQ and OACK signals may be active high or active low. Timing diagrams assume the active high mode.

S. Successive read and/or write operations, by the external processor, to program or examine the controller must be timed
to allow at least 250 ns for the VL82C37A-08, as recovery time between active read or write pulses.

9. -EOP is an open-collector output. This parameter assumes the presence of a 2.2 kn pull-up resistor to VCC.
10. Pin 5 is an input that should always be at a logic high level. An internal pull-up resistor will establish a logic high when
the pin is left floating. It is recommended, however, that pin 5 be tied to VCC.

6-239

•

VLSI TECHNOLOGY, INC.
VL82C37A

NOTES:

6-240

•

VLSI TECHNOLOGY, INC.

SECTION 7
PACKAGE
OUTLINES

Logic Products Division

•

VLSI TECHNOLOGY, INC.

•

VLSI TECHNOLOGY, INC.
PACKAGE OUTLINES

PACKAGE OUTLINES:
28-PIN PLASTIC DUAL IN-UNE

[:::::::::: ]5::=
tH
j
I.

1.300 (33.020)
REF

.165 (4.191)
.135 (3.429)

1.470 (37.338)

.015 (0.381)

MAX

~MIN

M~~

200

08)

.100 (2.540)
TYP

~11~.060(1.524)J
~C

TYP

-.i

SEATING
PLANE

.140(3.656)
.120(3.048)

.023 (0.584)
.015 (0.381)

.620(15.748)
MAX

b,OS'
90'

3-.

L·650 (16.510)
TYP

015 (0.381)

.008 (0.203)

NOTES: UNLESS OTHERWISE SPECIFIED.
LEAD FINISH: MATTE TIN PLATE OR LEADITIN SOLDER.
LEAD MATERIAL: ALLOY 42 OR COPPER.
PACKAGE LENGTH DOES NOT INCLUDE END FLASH BURR WHICH IS .010 (0.254) MAX. AT EACH END.
TOLERANCE TO BE ± .005 (0.127) UNLESS OTHERWISE NOTED.
ALL METRIC DIMENSIONS ARE IN PARENTHESES.
PIN 1 INDEX MARK MAY VARY IN SIZE AND SHAPE.

1.
2.
3.
4.
5.
6.

28-PIN PLASTIC LEADED CHIP CARRIER

'rTf

~
~

0 0

~ 460~~X684)

1~ Fr 'E.495 ~~ J
('i'Ei"i"2.S7'TE'fi
3)

MAX

4' ALL SIDES

.028(0.711)

-- r-...
.07~~iOS) 'r-I----*-..........-L...T1

.049 (1.244)

-LL~~n_t
.020 (-Is-oa- )
~I 1~--II-.032(0.aI2) .185(4.699)
MIN

.050 (1.270)
TYP

MAX

.021 (.533)
.013 (.330)

NOTES: UNLESS OTHERWISE SPECIFtED.

1. TOLERANCE TO BE ± .005 (0.127).
2. LEADFRAME MATERIAL: COPPER.
3. LEAD FINISH: MATTE TIN PLATE OR Sn Pb SOLOER DIP.
4. SPActNG TO BE MAINTAINED BETWEEN FORMED LEAD AND MOLDED PLASTIC ALONG
FULL LENGTH OF LEAD.
5. MOLDED PLASTIC DIMENSION DOES NOT INCLUDE SIDE FlASH BURR, WHICH IS 010
(0.254) MAX ON FOUR SlOES.
6. ALL METRIC DIMENSIONS ARE IN PARENTHESES.

7-3

•

VLSI TECHNOLOGY, INC.
PACKAGE OUTLINES

PACKAGE OUTLINES (Cont.):
40- PIN PLASllC DUAL IN-LINE
NOTES: UNLESS OTHERWISE SPEaFIED.
1. TOLERANCE 10 BE ± DOS (0.127).
2. LEADfRAME MATERIAL: COPPER.
3. LEAD FINISH: MATTE TIN PUffE OR SOLDER DIP.
4. SPACING 10 BE MAINTAINED BETWEEN FORMED LEAD AtO MOLDED PLASTIC ALONG
RLL LENGTH OF LEAl>.
S. MOLDED PLASTIC DIMENSION DOES NOT INCI.IJIlE SIDE FLASH BURR, WHICH IS .eno
(0.254) MAX ON FOUR SIDES.
&. ALL METRIC DIMENSIONS ARE IN PARENTHESES.

.165(4.191)
.135 (3.429)

.620 (15.748)

'1.015 (0.381)

2.080 (52.832) MAX

rrMAX~

~MIN

.200 (5.080)
MAX

J L ~~'08~~p52~
.100 (2.540)

.023 (0.584)
.015 (0.381)

TYP

.075 (1.905)-

(40

SEATING
PLANE

.140 (3.656)
.120(3.048)

6,::
90'

3-,015(0,381)
.008 (0.203)

L.6S0 (16.510)
TYP

.090 (2.288)
MAX

.028(0.711)
ALL SIDES

MAX

t r~ffilHHt-tHH!IHHl~-~
I

.020(0.762)

.185(4.899)

MAX

Iqr

44-PlN PLASTIC LEADED CHIP CARRIER

.880 (16.764)
MAX

.185 (4.699)
MAX

NOTES: UNLESS OTHERWISE SPECIFIED.
1. TOLERANCE TO BE ± .005 (0.127).
2. LEADFRAME MATERIAL: COPPER.
3. LEAD ANISH: MATTE TIN PLATE OR SOLOER DIP.
4. SPACING TO BE MAINTAINED BETWEEN FORMED LEAD AND MOLDED PLASTIC AUlNG
FULL LENGTH OF LEAD.
5. MOLDED PLASTIC DIMENSION DOES NOT INCLUDE SIDE FLASH BURR, WHICH IS .010
(0.254) MAX ON FOUR SIDES.
6. ALL METRIC DIMENSIONS ARE IN PARENTHESES.

7-4

•

VLSI TECHNOLOGY, INC.
PACKAGE OUTLINES

PACKAGE OUTLINES

(Cont.):

68-PIN PLASTIC LEADED CHIP CARRIER
.048 (1.219)
.042 (1.066)

j
PIN 1 INDEX
MAY VARY IN
SIZE AND
LOCATION

.960 (24.384)
MAX

1 a oouo
\1..
.•_ _ _ _ .995~":/73)' _ _ _ _- ,

•
7-5

•

VLSI TECHNOLOGY, INC.
PACKAGE OUTLINES

PACKAGE OUTLINES (Cont.):
84-PIN PLASTIC LEADED CHIP CARRIER

PIN 1 INDEX
MAY VARY IN
SIZEAND"'LOCATION

1.158 (29.41)
1.150 (29.21)

I~.--------:: :l~ :~: --------.1
~LIS~

DETAIL A

.010 (0.254)
.008 (0.203)

.032 (0.813)
.026 (0.660)
.049 (1.244)

-!-~~~~~~~~!~

.008 (0.203) RAD

1,075 (1.905) MAX

.005 (0.127)
AFTER
LEAD FINISH

}020 (0.508) MIN
.130 (3.30)
.090 (2.29)

.200(5.08)
.165(4.19)

.050 (1.27)

TYP

.035 (0.889) RAD

SEE DETAIL A

1 - - - - - - - - :::l~::: - - - - - - - - 1

.044 (1.117)

NOTES: UNLESS OTHERWISE SPECIFIED.
1. TOLERANCE TO BE +/·.005 (0.127).
2. LEADFRAME MATERIAL: COPPER.
3. LEAD FINISH: MATTE TIN PLATE OR SOLDER DIP.
4. SPACING TO BE MAINTAINED BETWEEN FORMED LEAD AND MOLDED PLASTIC ALONG FULL LENGTH OF LEAD.
5. MOLDED PLASTIC DIMENSION DOES NOT INCLUDE SIDE FLASH BURR, WHICH IS .010 (0.254) MAX ON FOUR SIDES.
6. CONTROLLING DIMENSIONS ARE METRIC, ALL METRIC DIMENSIONS ARE IN PARENTHESES.

7·6

•

VLSI TECHNOLOGY, INC.
PACKAGE OUTLINES

PACKAGE OUTLINES (Cont.):
100-PIN PLASTIC FLATPACK

.715 (18.15
(17.40)

.685

555

14.10

033 (.83):J ~
.084 (2.125)
.065 (1.65)

008 (.203)

.113 (2.87)
.101 (2.57)

1:0~4

(!3~6

. 014
.002 (.05)
. 026 (.65)

TYP

lJl

C-;Y;o.

.037 (.95)
.026 (.65)

.016 (.40)
.008 (.20)

1$1.006 (.15) Typ@1

DETAIL -A-

NOTES~ONTROLLING
1.
7-7

(.10)

DIMENSION IS MM.

•

VLSI TECHNOLOGY, INC.
PACKAGE OUTLINES

NOTES:

7-8

•

VLSI TECHNOLOGY, INC.

SECTION 8
SALES OFFICES,
DESIGN CENTERS,
AND
DISTRIBUTORS

Logic Products Division

•

VLSI tECHNOLOGY, INC.

•

VLSI TECHNOLOGY, INC.
SALES OFFICES, DESIGN CENTERS, AND DISTRIBUTORS

VLSI CORPORATE OFFICES
CORPORATE HEADQUARTERS. ASIC AND MEMORY PRODUCTS· VLSI Technology, Inc.· 1109 McKay Drive· San Jose, CA 95131 ·408-434-3100
LOGIC AND GOVERNMENT PRODUCTS· VLSI Technology, Inc.· 8375 Soum River Parkway· Tempe, AZ 85284·602-752-8574
VLSI SALES OFFICES
AND TECH CENTERS
ARIZONA
8375 South River Parkway
Tempe, AZ 85284
602-752-6450
FAX 602·752-6001
CALIFORNIA
2235 Qume Dr
San Jose, CA 95131

408-922-5200
FAX 408·943-9792
TELEX 278807
MAIL
1109 McKay Drive
San Jose, CA 95131
6345 Balboa Blvd, Ste. 100
EnCinO, CA 91316
818-609-9981
FAX 818·609·0535
30 Corporate Park, Stes. 1OO~ 102
Irvine, CA 92714
714-250-4900
FAX 714·250-9041

FLORIDA
2200 Park Central N , Ste. 600
Pompano Beach, FL 33064
305-971-0404
FAX 305-971·2086
GEORGIA
2400 Pleasant HIli Rd., Ste 200
Duluth. GA 30136
404·476·8574
FAX 404-476-3790
tLLlNOIS
3100 HigginS Rd, Ste. 155
Hoffman Estates, IL 60195
708-884-0500
FAX 708·884-9394
MARYLAND
124 Maryland Rle 3 N
Millersville, MO 21108
301-987-8777
FAX 301-987-8779
MASSACHUSETTS
261 Ballardvale St
Wilmington, MA 01887
508-658·9501
FAX 508-658-0423
NEW JERSEY
311C EnterpnseDr
Plainsboro, NJ 08536
609-799·5700
FAX 609·799-5720
TEXAS
850 E. Arapaho Rd ,Ste 270
Richardson, TX 75081
214-231·6716
FAX 214·669·1413
WASHINGTON
405 114th Ave SE, Ste 300
Bellevue, WA 98004
206-453-5414
FAX 206-453-5229
FRANCE
2,AlIee des Garays
F-91124 Palalseau Cedex
France
1-64470479
TELEX vlSlfr 600 759 F
FAX 1·6447 04.80

GERMANY
Rosenkavaherplatz 10
0-8000 Muenchen 81
West Germany
89·9269050
TELEX 521 4279 vlSld
FAX 89·92690545

VLSI AUTHORIZED
DESIGN CENTERS
COLORADO
SIS MICROELECTRONICS, INC

longmont, 303-776-1667
MAINE
QUADIC SYSTEMS, INC

HONG KONG
ShUi On Centre 28/12
8 Harbor Road
Hong Kong
852·5-865·3755
FAX 852-5-865·3159

South Portland, 207-871-8244

PENNSYLVANIA
INTEGRATED CIRCUIT SYSTEMS, INC
King of Prussia, 215-265-8690

JAPAN
Shuwa-Klolcho TBR Bldg, Room 101
5~7 KOllmachi, Chlyoda-Ku
Tokyo, Japan 102
81-3·239-5211
FAX 81·3·239·5215
UNITED KINGDOM
486-488 Midsummer Blvd.
Saxon Gate West, Central Milton
Keyes, MK9 2ED
United Kingdom
0908155 75 95
TELEX vlsluk 825 135
FAX 09 08/67 DO 27

VLSI SALES OFFICES
ALABAMA
2614 Artie St ,Ste 36
Huntsville, AL 35805
205·539·5513
FAX 205·536-8622

EIRE AND U.K.
PA TECHNOLOGY
Herts, 76·3-61222
FRANCE
CETIA
Toulon Cedex, 9~42-12005
SOREP
Chateaubourg,

99~623955

NORWAY
NORKRETS AS
Oslo, 47-236067718
SWEDEN
NOROISK ARRAYTEKNIK AB
Solna, 8-7349935

VLSISALES
REPRESENTATIVES
CALIFORNIA
CENTAUR CORP
Irvine, 714-261-2123
CENTAUR CORP
Calabasas, 818-704-1655

CONNECTICUT
60 Church St., Ste 16
YaleSVille, CT 06492
203-265·6698
FAX 203·265·3653

CENTAUR CORP.
San Diego, 619-278-4950
EMERGING TECHNOLOGY
San Jose, 408-263-9366

FLORIDA
5955 T G Lee Blvd., Ste 170
Orlando, FL 32822
407·240·9603
FAX 407·240-9605

EMERGING TECHNOLOGY
Orangevale, 916-988-4387
COLORADO
LUSCOMBE ENGINEERING
Longmont, 303-772-3342

MINNESOTA
5871 Cedar Lake Rd , Ste. 9
St LoUIS Park, MN 55416
612-545-1490
FAX 612·545·3489

IOWA
SELTEC SALES
Cedar Rapids, 319-364-7660

NORTH CAROLINA
1000 Park Forty Plaza, Ste 300
Durham, NC 27713

919'544·1891/92
FAX 919-544·6667
OHIO
4 Commerce Park Sq.
23200 Chagrin Blvd., Ste 600
Cleveland, OH 44122
216-292-8235
FAX 216-464-7609

MARYLAND
DELTA III
Columbia, 301-730-4700
NEW YORK
bbd ELECTRONICS
Rochester, 716-425-4101
OREGON
MICRO SALES
Beaverton, 503-645-2841

OREGON
10300 S.W Greenburg Rd ,Ste 365
Portland, OR 97223
503'244-9882
FAX 503·245-0375
TEXAS
9600 Great Hills Trail, Ste 150W
Austin, TX 78759
512'343·8191
FAX 512·343·2759

UTAH
LUSCOMBE ENGINEERING
Salt Lake City, 801·565·9B85
WASHINGTON
MICRO SALES
Bellevue, 206-451-0568
ISRAEL
ROT ELECTRONICS
Tel AVIV, 3-483211-9
SINGAPORE
DYNAMIC SYSTEMS PIE, LTO
Singapore, 011-65-742-1986

VLSI DISTRIBUTORS
Umted States represented by
SCHWEBER ELECTRONICS except

where noted
ALABAMA
HuntSVIlle, 205-895-0480
ARIZONA
Tempe. 602·431-0030
CALIFORNIA
Calabasas, 818-880-9686
IrVine, 714~863~0200
Sacramento, 916-364-0222
San Diego, 619-495-0015
San Jose, 408~432~7171
COLORADO
Englewood, 303-799~0258
CONNECTICUT
Oxford,203-264-4700
FLORIDA
Altamonte Springs, 407-331-7555
Pompano Beach, 305-977-7511
Tampa. 813-541-5100
GEORGIA
Norcross, 404-449-9170
ILLINOIS
Elk Grove Village, 312-569-3650
IOWA
Cedar Rapids, 319-373-1417
KANSAS
Overland Park, 913-492-2921
MARYLAND
Gaithersburg, 301-596-7800
MASSACHUSETTS
Bedford,617-275-5100
MICHIGAN
LIvonia, 313-525-8100

MINNESOTA
Eden Pralre, 612-941-5280
MISSOURI
Earth City, 314·739·0526
NEW HAMPSHIRE
Manchester, 603-625-2250
NEW JERSEY
Fallileld,201-227-7880
NEW YORK
Rochester, 716-424-2222
Westbury, 516-334-7474
NORTH CAROLINA
Raleigh, 919-876-0000
OHIO
Beachwood,216-464-2970
Dayton, 513·439·1800
OKLAHOMA
Tulsa. 918-622-8003
OREGON
ALMAC ELECTRONICS CORP
Beaverton, 503-629-8090
PENNSYLVANIA
Horsham, 215-441-0600
Plttsburgh,412-963·6804
TEXAS
Austln,512-339-0088
Oalias, 214·247-6300
Houston, 713-784-3600

AUSTRALIA
ENERGY CONTROL

Brisbane, 61 +376-2955
AUSTRIA
TRANSISTOR GmbH
VIenna, 222-8294010

BELGIUM AND LUXEMBURG

MCAtromx
Angleur, 41-674208
DENMARK
INTERELKO
Karlslunde,

3~ 140700

EIRE AND U.K.
HAWKE COMPONENTS
Sunbury-on-Thames. 1~9797799
QUARNOON ELECTRONICS
Derby, 332-32651
FtNLAND
OY COMOAX
Helslnkl,0-670277
FRANCE
ASAPs.a.
Montlgny~le-Bretonneux,' 1-3043 82

GERMANY
DATA MODUL GmbH
MUnlch,89-4180070
SPEZIAL-ELECTRONIC KG
Bueckeburg, 5722-2030
HONG KONG
LESTINA INTERNATIONAL. LTD
TSlmshatsul,852-3-7351736
ITALY
INTER-REP SPA
Torino, 11-2165901
JAPAN
ASAHI GLASS CD LTD
Tokyo, 81·3·218·5854
TEKSEL COMPANY, LTD
Tokyo, 81-3-461-5311
TOKYO ELECTRON, LTD
Tokyo, 81-423-33·8009
KOREA
ANAM VLSI DESIGN CENTER
Seoul. 82-2-553·2106
EASTERN ELECTRONICS
Seoul,82-2-464-0399
NETHERLANDS
DIODE
Houten, 3403-91234
SWEDEN AND NORWAY
TRACO AB
Farsta, 8-930000
SOUTH AMERtCA - BRAZIL
INTERNATIONAL TRADE
DEVELOPMENT
Palo Alto, 415-856-6686
SPAIN AND PORTUGAL
SEMICONOUCTORES s.a
Barcelona, 3-217-23 40
SWITZERLAND
FABRIMEX AG
Zunch, 1-2512929
TAIWAN
PRINCETON TECH CORP
Talpel,886-2-717-1439

WASHINGTON
ALMAC ELECTRONICS CORP
Bellevue, 206-643-9992
Spokane. 509-924·9500
WISCONSIN
New Berlin, 414-784-9020
11189

The information contained in this document has been
carefully checked and Is believed to be reliable. However.
VlSI Technology, Inc .• (VLSI), makes no guarantee or
warranty concerning the accuracy of said Information and
shall not be responsible for any loss or damage of whatever
nature resuh.ing from the use of, or reliance upon, it. VLSI
does not guarantee that the use of any information
contained herein will not infringe upon the patent or other

rights of third parties. and no patent or other license is
irrplied hereby.
This document does not in any way extend VLSI's warranty
on any product beyond that set forth In h.s standard terms
and condh.ions of sale. VLSI Technology, Inc., reserves the
right to make changes in the products or specifications, or
both, presented in this publication at any time and without
notice.

8-3

LIFE SUPPORT APPLICATIONS
VLSI Technology, Inc., products are not intended for use as
critical components in life suppon appliances, devices, or
systems in which the failure of a VlSI Technology product
to perform could reasonably be expeded to result In
personal injury.
e>1990 VLSI Technology, Inc.. Printed In U.S.A.
835O-4oo295-0D2 10M

•

VLSI TECHNOLOGY, INC.
SALES OFFICES, DESIGN CENTERS, AND DISTRIBUTORS

8-4

•

VLSI TECHNOLOGY, INC.

VLSI Technology, Inc.
Logic Products Division
8375 South River Parkway
Tempe , AZ 85284
602·752·8574

e 1990 VLSI Technology, Inc., Printed in U.S.A., 10M 400295·002

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