1990_WSI_CMOS_Memory_and_High_Performace_VLSI 1990 WSI CMOS Memory And High Performace VLSI
User Manual: 1990_WSI_CMOS_Memory_and_High_Performace_VLSI
Open the PDF directly: View PDF 
.
Page Count: 508
| Download | |
| Open PDF In Browser | View PDF |
High Pedormance CMOS Memory
and Programmable VLSI
1990 Data Book
PROMslRPROMs
EPROMs
Programmable System™ Devices
WAFERSCALE INTEGRATION, INC
riterio~
manufacturers representative
(408) 988-6300
3350 ScoN Blvd. Bldg. #44· Santa Clara. CA 95054-3120
WAFERSCALE INTEGRATION, INC.
HIGH PERFORMANCE
CMOS MEMORY AND PROGRAMMABLE VLSI
DATABOOK
1990
Copyright © 1990 WaferSca/e Integration, Inc.
(All rights reserved.)
47280 Kato Road, Fremont, california 94538
415-656-5400 Facsimile: 415-657-5916 Telex: 289255
Printed in U.S.A.
----------------------~JF;----------------------
--
!r====~=:
.......
r====..a
==
~~~ ~ -----------------------------------------------------------------WAFERSCALE INTEGRATION, INC.
GENERAL INFORMATION
1
SECTION INDEX
GENERAL INFORMATION
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ................ .1-1
Company Profile ......................................................................... 1-5
WSI CMOS Technology and Patents .......................... "
.....
. . . . . . . . . . . . . . . .. . 1-9
Technical Brief 001 .............................................................. . ...... 1-11
Article Reprints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..... 1-15
Product Summary. . . . . . . . . . . . . . . . . . . . . . .. ....................... .....
. .............. 1-23
Numerical Product Listing ................................................................ 1-27
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . .. .. ........................ . ..
. ........ 1-31
Cross Reference. . . . . . . . . . .. ........ .... ............................... ..... . ...... 1-33
Advance Information/Preliminary/Final Defined ....
. ............ 1-37
For additional information,
call 800-TEAM-WSI (800-832-6974)_
In California, call 800-562-6363.
-----------------------~Jri~---------------------
== ===
:r
==
..-~-
--~~
~~
TABLE OF CONTENTS
-==-----------------------------
~
IE
~~~~
!!!!:......!!--~!!-ii'-=
----
-.-.. ~
WAFERSCALE INTEGRATION, INC.
GENERAL INFORMATION
Table of Contents ........................................................................ 1-1
Company Profile ......................................................................... 1-5
WSI CMOS Technology and Patents ......................................................... 1-9
Technical Brief 001 ...................................................................... 1-11
Article Reprints ......................................................................... 1-15
Product Summary ....................................................................... 1-23
Numerical Product Listing ................................................................ 1-27
Ordering Information ..................................................................... 1-31
Cross Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ................................... 1-33
Advance Information/Preliminary/Final Defined ................................................ 1-37
PROMIRPROM MEMORY PRODUCTS
PROM/RPROM Selection Guide . ..................................................... 2-1
WS57C191B/291B
High Speed 2K x 8 CMOS PROM/RPROM ............................... 2-3
WS57C43B
High Speed 4K x 8 CMOS PROM/RPROM ............................... 2-9
WS57C43C
High Speed 4K x 8 CMOS PROM/RPROM ............................... 2-15
WS57C45
High Speed 2K x 8 Registered CMOS PROM/RPROM ..................... 2-19
WS57C49B
High Speed 8K x 8 CMOS PROM/RPROM .............................. 2-27
WS57C49C
High Speed 8K x 8 CMOS PROM/RPROM .............................. 2-33
WS57C51B
High Speed 16K x 8 CMOS PROM/RPROM .............................. 2-37
WS57C71C
High Speed 32K x 8 CMOS RPROM ................................... 2-43
EPROM MEMORY PRODUCTS
64K EPROM Selection Guide ........................................................ 3-1
WS27C64F
Military 8K x 8 CMOS EPROM ......................................... 3-3
WS27C64L
8K x 8 CMOS EPROM ................................................ 3-9
WS57C64F
High Speed 8K x 8 CMOS EPROM ..................................... 3-15
WS57C65
High Speed 4K x 16 CMOS EPROM .................................... 3-21
128K EPROM Selection Guide ...................................................... 3-27
WS27C128F
Military 16K x 8 CMOS EPROM ....................................... 3-29
WS27C128L
16K x 8 CMOS EPROM .............................................. 3-35
WS57C128F
High Speed 16K x 8 CMOS EPROM .................................... 3-41
1-1
II
Table of Contents
EPROM MEMORY PRODUCTS (Cont.)
256K EPROM Selection Guide ...................................................... 3-47
WS27C256F
High Speed 32K x 8 CMOS EPROM ................................... 3-49
WS27C256L
32K x 8 CMOS EPROM .............................................. 3-55
WS57C256F
High Speed 32K
WS57C257
High Speed 16K x 16 CMOS EPROM ................................... 3-67
x 8 CMOS EPROM ................................... 3-61
512K EPROM Selection Guide ...................................................... 3-73
x 8 CMOS EPROM .................................... 3-75
WS27C512F
High Speed 64K
WS57C512F
High Speed 64K x 8 CMOS EPROM ................................... 3-81
WS27C512L
64K x 8 CMOS EPROM .............................................. 3-85
1 Meg EPROM Selection Guide . .................................................... 3-91
x 8 CMOS EPROM ............................................. 3-93
WS27C010L
128K
WS57C010M
1 Meg (128K x 8) CMOS EPROM Module ............................... 3-99
WS27C010F
1 Meg (128K x 8) CMOS EPROM ..................................... 3-105
WS27C210L
1 Meg (64K x 16) CMOS EPROM ..................................... 3-109
WS57C210M
1 Meg (64K
x 16) CMOS EPROM Module ............................... 3-115
WS27C210F
1 Meg (64K
x 16) CMOS EPROM ..................................... 3-121
2 Meg EPROM Selection Guide ....... ............................................. 3-125
WS27C020L
2 Meg (256K
x 8) CMOS EPROM ..................................... 3-127
WS27C220L
2 Meg (128K
x 16) CMOS EPROM .................................... 3-133
4 Meg EPROM Selection Guide .................................. .................. 3-139
x 8) CMOS EPROM ..................................... 3-141
WS27C040L
4 Meg (512K
WS27C240L
4 Meg (256K x 16) CMOS EPROM .................................... 3-147
PROGRAMMABLE SYSTEM™ DEVICES (PSD)
Introduction to Programmable System Devices . ..................................... 4-1
MAP168/PSD301
Introduction
User-Configurable Peripheral with Memory ................................ 4-3
MAP168
User-Configurable Peripheral with Memory ................................ 4-7
PSD301
User-Configurable Peripheral with Memory ............................... 4-25
PAC1000 Introduction
User-Configurable Microcontroller ...................................... 4-29
PAC1000
User-Configurable Microcontroller ~ ...................................... 4-31
SAM448 Introduction
User-Configurable Microsequencer ..................................... 4-79
SAM448
User-Configurable Microsequencer ..................................... 4-81
Electronic Bulletin Board ............................................................... .4-103
------------------------~Jr;-----------------------
1-2
Table of Contents
MEMORY PROGRAMMING AND PSD DEVELOPMENT SYSTEMS
Introduction. . . . . . . . . . . . . . . . . .. . ........................................................ 5-1
Data 1/0 Programming Support ............................................................. 5-3
Memory Programming System ................... . ........................................ 5-5
PAC1000 -
PSD Development Systems ..................................................... 5-9
MAP168 -
PSD Development Systems .. "
SAM448 -
PSD Development Systems .... , ................................................ 5-17
.............................................. 5-13
WS6000 MagicPro™ Programmer and Package Adaptors. . . . . . . . . . . . . . . . . .. . .................. 5-21
CMOS LOGIC PRODUCTS
WS5901
CMOS 4-Bit High-Speed Microprocessor Slice ............................. 6-1
WS59016
CMOS 16-Bit High-Speed Microprocessor Slice ........................... 6-11
WS59032
CMOS 32-Bit High-Speed Microprocessor Slice ........................... 6-23
WS5910A/B
CMOS Microprogram Controller ........................................ 6-35
WS59510
Multilevel Pipeline Register ........................................... 6-45
WS59520/521
Multilevel Pipeline Register ........................................... 6-53
WS59820/820B
Bi-Directional Bus Interface Registers ................................... 6-57
MILITARY PRODUCTS .................................................................... 7-1
QUALITY AND RELIABILITY . ............................................................. 8-1
PACKAGE INTRODUCTION ........................................................ ..
..9-1
Package Information (By Drawing Number) . . . . . .. . .......................................... 9-2
Package Information (By Pin Count) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..................... 9-3
Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . ................................ 9-5
SALES REPRESENTATIVES AND DISTRIBUTORS . ........................................ 10-1
------------------------~Jri----------------------1-3
II
~
1-4
_______________________ f;.'-E _________________________
~#;
-
~==~=
-~~
~~SJAr
____________________C_O_M_P._~_N_Y_P_R_O_F_'L_E
WAFERSCALE INTEGRATION, INC.
INTRODUCTION
WaferScale Integration, Inc. (WSI) designs and produces the world's broadest and fastest families of CMOS PROMs,
RPROMs, EPROMs, and Programmable System™ Devices (PSD). These product families target the needs of system
designers who must reduce system development time and deliver market competitive products in continuously shorter
periods of time. WSI's programmable VLSI products additionally enable higher system performance from smaller,
more compact end products due to higher levels of system integration at the chip level.
WSI's mission is clear - to build a great company by serving its customers with a portfoliO of high-performance
programmable VLSI products that enable designers to achieve faster time to market with new, advanced electronic
systems.
The company's patented self-aligned, split-gate EPROM technology forms the core of WSI's programmable products
and delivers higher performance and greater density than competing "stacked gate" EPROM technologies. This core
technology has enabled WSI to be first in the industry with numerous breakthroughs in speed, density, process and
packaging. WSI has leveraged this technology into the broadest family of CMOS PROMs, RPROMs, and EPROMs
available.
WSI's new "off the shelf" user-configurable PSDs provide system level building blocks on a single chip that enable
quick implementation of application specific controllers and peripherals. They are the first to integrate high-performance
EPROM, SRAM and logic and deliver a performance and integration breakthrough to the programmable products
market. PSDs are user-configurable on a PC or compatible and can be tailored for use in a variety of system applications.
As a result, WSI has established itself as a leading supplier of high-performance programmable VLSI solutions to
a broad customer base that includes some of the world's largest and most technologically advanced electronics
companies.
Founded in 1983, WSI is headquartered in a 66,000 square foot facility in Fremont, California and has more than
125 employees. Through a long-term equity, manufacturing and technology license agreement with Sharp Corporation
of Japan, WSI produces its products in a world-class production facility that guarantees the highest quality at competitive
costs.
MARKETS AND APPLICATIONS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
WSI's high-performance non-volatile memory and PSD products are used by the world's leading suppliers of highperformance electronic systems in communications, data processing, military and industrial markets. Customer end
products cover a broad spectrum and typically include cellular telephones, workstations, DSP computers, navigation
controllers, T1 multiplexers, modems, image processors, missiles, LAN controllers, high density disk drives and the
like. Customer applications include image processing, digital signal processing, bus control, LAN data and file control,
real time process control, graphics processing, hard disk control, flight simulators, DMA control, and others. WSI
products are ideally suited for these applications where designers are faced with increasingly shorter product life
cycles and must develop new, competitive high-performance products in short periods of time.
1·5
(I
Company Profile
PRODUCTS ___________________________________________________
Memory Products
EPROMs
WSI offers the broadest line of CMOS EPROM products available featuring architectures ranging from 8K x 8 to
128K x 8, plus several x16 products, with speeds ranging from 40 to 200 ns. Commercial, industrial and MILSTD-883C/SMD products are available. A wide variety of package selections are available including plastic and hermetic,
through-hole and surface mount types.
"L" Family
WSI's "I.:' family memory products are the industry's fastest, low power JEDEC pinout EPROMs and meet the
requirements of many mainstream system applications. With speeds ranging from 90 to 200 ns and architectures
from 8K x 8 to 128K x 8 including several x16 products, "I.:' family EPROMs are ideal for high-performance
personal computers and workstations. Taking advantage of its split-gate EPROM technology, WSI uses a
conservative 1.2 micron lithography to achieve world-class memory densities that traditionally require lower yielding
sub-micron technologies.
"F" Family
The "F" family is WSI's fastest line of EPROMs, featuring speeds ranging from 40 to 110 ns and architectures
from 8K x 8 to 32K x 8, plus several x16 products. The high speed and word width options of the "F" family
EPROMs make them attractive for use in high-end engineering and scientific workstations, data communications
and other high-performance applications.
RPROMs
RPROMs provide bipolar PROM pin-out with matching speed and CMOS low power operation. The RPROM (ReProgrammable Read Only Memory) product series includes architectures ranging from 2K x 8 to 32K x 8 with speeds
ranging from 25 to 70 ns.
Commercial, industrial and MIL-STD-883C/SMD configurations are available in a variety of hermetic and plastic
package styles.
Programmable System™ Devices (PSDs)
WSI's family of Programmable System Devices (PSDs) represent a new class of programmable VLSI products, achieving
unparalleled levels of performance, configurability and integration. Offering a significantly higher level of integration
over programmable logic, PSDs are the first programmable VLSI products to integrate high-speed EPROM, SRAM
and logic on a single chip thereby providing complete system solutions to the design engineer. PSDs are off-the-shelf
system building elements that can be quickly configured and programmed for a variety of system applications thus
enabling system designers to shorten system development time.
The PSD is a new solution for system designers who build high-end systems around embedded controllers and
advanced microprocessors. These new systems require faster, more highly integrated and lower cost VLSI solutions
as well as rapid design cycles. WSI's new PSD family meets this demanding set of needs.
The initial members of WSl's PSD family includes:
• The PAC1000 User-Configurable Microcontroller
• The MAP168 User-Configurable Peripheral with Memory
• The PSD301 User-Configurable Peripheral with Memory
• The SAM448 User-Configurable Microsequencer
Design Tools and Support
WSI's development tools minimize the time required for designers to program PSDs for use in a variety of system
applications. PSDs are supported with complete easy-to-use program development, simulation and programming
software, the PC hosted MagicPro™ Memory and PSD Programmer, a dial-in applications bulletin board and WSI's
team of factory and field applications engineers. As a result, WSI customers achieve their goal of shorter system
development time and reach new markets sooner.
S'==f .,~
---------------------------------~.,,-------------------------------1-6
Company Profile
PRODUCTS (Cont.) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Custom Circuits
To serve the needs of its customers with unique requirements, WSI offers its custom circuit capability using its cell
based library of EPROM, static RAM and logic functions. Standard products described in this catalog can usually
be modified on a custom basis to serve particular requirements. New customer defined custom products that incorporate
high-performance non-volatile memory, SRAM and logic can be produced that deliver significant speed or system
integration advantages. Contact your local WSI sales office for additional information.
MANUFACTURING _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
A key ingredient for success in leading-edge semiconductors is a world-class fabrication facility that ensures high
volume capacity and prompt delivery of highly reliable and high yielding VLSI circuits. To this end, WSI has licensed
its proprietary CMOS EPROM and logic process technology to Sharp Corporation of Osaka, Japan. This long term
alliance ensures high quality, high-volume production, competitive costs and fast delivery. The Sharp facility in
Fukuyama, Japan employs the most advanced sub-micron VLSI integrated circuit manufacturing equipment available
including ion implantation, reactive ion etch, and wafer stepper lithographic systems.
QUALITY AND RELIABILlTY _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
WSI is deeply committed to product excellence. This begins with proper management attitude and direction and with
this focus, the Quality and Reliability Program is able to operate efficiently. As a result, product quality becomes part
of each employee's responsibility.
Quality and Reliability begin with the proper product and process designs and is supported by material and process
controls. Examples are products manufactured on an epitaxial silicon layer to reduce latch-up sensitivity, all pins are
designed to withstand >2,000 volts ESDS, numerous ground taps are used which increases product noise immunity,
metal traces are deSigned to carry a current density of >2.0 x 105 ampslcm 2 , top passivation extends over into the
scribe lane to seal the die edges, data retention is performed 100% on re-programmable products (TA = + 225°C,
72 hours), automated die attach and bonding is used extensively, wafers are fabricated in a Class 10 clean room,
T
raw materials, chemicals and gases are inspected before use, and statistical controls are used to keep the process
on course.
=
Product and process introductions or changes are routinely evaluated for worthiness. Life tests are conducted at higher
than typical stress levels (TA = +150°C, Vee = +6.5V) and even at these stress levels, WSI products have
demonstrated low failure rates (see the Quality and Reliability section in this databook).
WSI is active in Military programs and its Quality and Reliability System supports Compliant Non-Jan products. WSI
also supports DESC's (Defense Electronics Supply Center) Standardized Military Drawings (SMD) program. As of
October, 1989, WSI has eighteen products on SMDs with additional products pending. Several additional products
not on SMDs are available per MIL-STD-883C. See Section 7 (Military Products) in this databook.
SALESNETWORK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
WSI's international sales network includes regional sales managers, field applications engineers, manufacturers
representatives and many of the leading component distributors in the United States, Europe and Asia. See Section 10
in this catalog.
United States
Direct sales and field applications engineering offices in Boston, Chicago, Huntsville, Philadelphia, Los Angeles areas
and Fremont, CA; more than 25 manufacturers' representatives for major national accounts; national distributors
including Schweber Electronics, Time Electronics and Wyle Laboratories; and regional distributors.
International
Distributors in West Germany, England, France, Italy, Sweden, Finland, Denmark, Norway, Spain, Belgium, Luxembourg,
the Netherlands, and Israel. Distributors for the Asia/Pacific Rim region in Japan, Korea, Taiwan, Hong Kong and
Australia.
---------------------~~i--------------------1-7
II
~1_8------------'---------~Jr;----------------------
..... ==
- ==- ==IE
....--=
--.. !!-!!!!!!!!l-!!!!!i'-=
_--iii
~
- . r . . . . - r ___________________________________________________________________
1!r
WSI CMOS TECHNOLOGY AND PATENTS
WAFERSCALE INTEGRATION, INC.
Each generation of systems involved with data processing, communications, military and industrial control historically
requires faster and more efficient system functions to accomplish greater productivity. Issues of performance, reliability,
design time, system integration, power, and cost must be successfully treated to insure the market success of competitive
end products. WSI's CMOS technology forms the foundation of a portfolio of programmable VLSI integrated circuits
that are used by leading systems manufacturers worldwide to address the above issues and retain their competitive
edge.
WSI's core technology begins with its patented self-aligned, split-gate single transistor EPROM cell (U.S. patents
#4,639,893 and 4,795,719). The self-aligned, split-gate EPROM cell pioneered by WSI is the only major EPROM
technology/architecture innovation since 1972. This advancement beyond the traditional "stacked gate" EPROM cell,
when coupled with several memory array design enhancements, provides WSI with a broad product line of highperformance PROMs, RPROMs, EPROMs and Programmable System™ Devices.
The WSI self-aligned, split-gate EPROM cell will not program in the reverse direction. This feature has enabled the
development of a high density virtual ground array EPROM architecture that has resulted in smaller EPROM die sizes
than competitive products even when fabricated with less aggressive photolithography.
WSl's 1.2 micron double metal/double poly N-well CMOS process enables the combining of high-performance EPROM
memory, static random access memory and logic all on the same low power circuit. This capability has enabled the
development of the Programmable System Devices product family. These standard product integrated circuits shorten
system development time by enabling the design engineer to quickly configure and program them for use in various
portions of the system. Their high level of integration and versatility enable designers to develop end products faster
and reach markets ahead of their competition.
WSI's use of epi wafers and design innovations result in products that exhibit immunity to latch-up and provide ESD
protection far in excess of that specified by MIL-STD-883C.
Technology and design patents held by WSI are listed below. Several additional patents are pending.
#4,328,656
Non-Volatile EPROM with Increased Efficiency
#4,361,847
Non-Volatile EPROM and EEPROM with Increased Efficiency
#4,409,723
Non-Volatile EPROM and EEPROM with Increased Efficiency
#4,639,893
A Self-Aligned, Split-Gate EPROM
#4,649,520
A Single Layer Polycrystalline Floating Gate
#4,758,869
Non-Volatile Floating Gate Transistor Structure
#4,763,184
Input Circuit for Protecting Against Damage Caused by Electrostatic Discharge
#4,795,719
A Self-Aligned, Split-Gate EPROM
1-9
II
-1_1~O----------------------~Jr;------------------------
TECHNICAL BRIEF 001
W AFERSCALE INTEGRA TlON, INC.
EPROMs FOR MODERN TIMES
HIGH SPEED EPROMs:
Early generations of microprocessors (e.g., 6809, 8085, 8086, etc.) and microcontrollers (8048,8051,6805, etc.) operated
at frequencies in the 1-5 MHz range. At these operating frequencies, memory access time requirements varied from
200-500 ns. The EPROM technology available at the time was well suited for such applications. This technology,
based upon a single transistor "stacked gate" EPROM cell (see Figure 1), was optimized for programmability and
density, not speed. Many manufacturers were quite successful with this technology and manufactured EPROMs from
16K bits up to 1 Mbit.
However, today's generation of high performance microprocessors (80286, 80386, 68000, 68020, etc.), microcontrollers
(8096, etc.) and dedicated DSP processors (TMS320xx, MC56000, etc.) operate in the 12-40 MHz range and require
memories with access times well below 100 ns (see Table 1).
Table 1
MEMORY ACCESS TIME REQUIREMENTS
PART #
FREQUENCY
MEMORY ACCESS
80386
16 MHz
70 ns
68020
20 MHz
70 ns
32020
20 MHz
75 ns
56000
20 MHz
55 ns
320C25
40 MHz
40 ns
As will be shown, the traditional single transistor "stacked gate" approach is not able to provide such high speeds.
As a result, system designers are forced into alternatives such as down loading from slow EPROM into fast SRAM,
which provides non-volatility and high speed. Unfortunately, these techniques result in higher system costs (board
space, components, power, etc.).
Semiconductor manufacturers are attempting to solve this problem at the I.C. level with various approaches. This
article explains the various techniques for achieving high speed EPROMs and allows the reader to determine which
technique is best suited for their application and which technique provides the best path for the future.
HIGH SPEED NVM: A GENERAL DISCUSSION
Memory arrays are laid out in two-dimensional row and column formats. These are referred to as word lines and bit
lines, respectively. Selecting a word line determines which row of cells in the array has been chosen to provide the
programmed output. The bit line, or column, is used to determine which of the selected cells in the row is to be read
from an output. Although this technique singles out a particular EPROM cell for reading, the output of the selected
EPROM is still connected to the outputs of several non-selected EPROM cells which share the same column, or bit
line. Each of these non-selected cells adds some capacitance to the bit line. This capacitance must be overcome
by the selected cell before the proper state ("1" or "0") can be sent to the output. The selected cell must have enough
drive to be able to discharge the combined bit line capacitance. Higher drive, or read current, results in a faster capacitive
discharge and, therefore, faster reading. Lower bit line capacitance and/or increasing read current are the fundamental
goals associated with developing high speed, dense EPROMs. Lowering bit line capacitance is easily achieved by
reducing the number of memory cells. Although this results in a speed improvement, it severely limits density.
The main problem to solve, therefore, is how to manufacture an EPROM cell which can provide high read current
(for speed), high density (for small size), high reliability and ease of programming.
The following paragraphs discuss four approaches for developing a fast, dense, reliable and programmable EPROM
memory.
1-11
II
Technical Brief 001
SINGLE TRANSISTOR ("STACKED GATE")
The industry standard single transistor stacked gate EPROM cell (Figure 1) is optimized for efficient programming
and high density. It is not well suited for high speed because of its low read current. The typical read current for
a single unprogrammed stacked gate EPROM cell is between 20-50 microamps and the total bit line capacitance
for a typical EPROM can be as high as 3-5 pF. Consequently, at 40 microamps of worst-case read current, it would
take a "stacked gate" EPROM cell 70 ns to discharge the bit line by enough voltage to detect an unprogrammed
condition. Address decoding and output buffers add another 25-50 ns (depending upon technology). Clearly, this
makes it very difficult to achieve a worst-case total access time which will allow an EPROM to run with today's generation of processors (see Table 1). Several semiconductor manufacturers are looking for alternatives to surmount the
inherent limitations of the older single transistor "stacked gate" EPROM.
"STACKED GATE"
EPROM CELL
(INDUSTRY STANDARD)
'--_ _ _ _ _ _ _ _ _ _ ____'\
~NROL
I
FLOATING
GATE
~-----------------------'
c-
Figure 1
TWO TRANSISTOR FAST CELL ("STACKED GATE" EPROM)
In this approach each bit consists of two stacked gate EPROM cells in a differential pair. With this architecture, it
is possible to employ a differential sensing technique which allows a programmed or unprogrammed state ("0" or
"1") to be detected with a very small voltage swing. As a result, a memory cell can be read much faster than with
a standard sensing technique. However, this incurs the penalty of twice the area of the single cell memory array as
well as implications of lower yields, higher costs and lower reliability than a single cell approach.
FOUR TRANSISTOR FAST CELL ("STACKED GATE" EPROM)
In this approach, the differential sensing technique is also used. However, each half bit is constructed with two
transistors, one of which is optimized for programming efficiency while the second transistor is optimized to give high
read current (typically 150 microamps). This makes it possible to achieve very high speeds. However, a four transistor
cell results in a very large memory array resulting in problems more severe than those of the two transistor approach
(again, low yields, high costs and low reliability). Consequently, this technique is limited to low density devices.
STACKED GATE SUMMARY
MEMORY TYPE
RELATIVE SPEED
RELATIVE DIE SIZE
Single Transistor
Slow
Small
Two Transistor
Fast
Large
Four Transistor
Fastest
Larger
-------------------------~Jri~---------------------1-12
Technical Brief 001
SINGLE TRANSISTOR FAST CELL ("SPLIT GATE" EPROM)
WaferScale Integration Inc. (WSI) has developed a proprietary technology which embodies all of the benefits of the
single transistor "stacked gate" (ease of programming, reliability, and density) and conquers the fundamental problem
of low read current. This patented technology is known as the "split gate" EPROM (see Figure 2).
II
WAFERSCALE'S PATENTED
"SPLIT GATE"
EPROM CELL
CONTROL
GATE
I
~--------------~
FLOATING
GATE
Figure 2
The "split gate" cell uses a single transistor per bit and, although it is nearly the same size as the "stacked gate,"
each cell provides a read current of at least 160 microamps under worst-case voltage and temperature conditions.
This allows the design of very high density and very fast memory products. As an example of the capabilities of the
"split gate," WaferScale has introduced families of EPROM products varying in density from 16K to 1 Mbits and in
speed ranging from 25-200 ns, all manufactured with the same EPROM technology.
SPLIT GATE SUMMARY
MEMORY TYPE
RELATIVE SPEED
RELATIVE DIE SIZE
Single Transistor
Fastest
Small
As is seen from the table above, the WSI split gate EPROM technology provides the high density capability of the
single transistor "stacked gate" and the fast speed of the four transistor solution.
REQUIRED FEATURES
Although speed and density are necessary EPROM attributes, they alone are not sufficient for today's memory
requirements. Reliability and ease of programming play an equally important role in determining the usefulness of
a memory product.
SUMMARY
Although the single transistor "stacked gate" EPROM technology is very well suited for its intended use (slow, dense
NVM), it is not well suited for today's high performance memory requirements. Brute force techniques, such as using
multiple transistor memory cells, can provide high performance; however, the penalty paid in die size and resultant
higher costs limits these techniques to relatively low densities.
WaferScale's patented "split gate" technology combines all of the attributes of the single transistor "stacked gate"
(reliability, ease of programming and density) with the speed of the multi-transistor memory cell. The result is a family
of dense, high speed EPROM based products. Also, since WaferScale's technology is well suited for device scaling,
the technology path for future products is already in place. This will result in products with higher density that utilize
both standard and application specific architectures.
-----------------------~Jri·-----------------------1-13
~1-1~4----------------------~~/------------------------
Article Reprint
COVER FEATURE
PACKING ALL THE MAJOR BLOCKS OF A
MICROPROGRAMMABLE SYSTEM, A CMOS IC EASES
EMBEDDED CONTROLLER DESIGNS
CONFIGURABLE CHIP EASES
CONTROL-SYSTEM DESIGN
DAVE BURSKY
nyone who has ever designed a high-performance controller subsyst'm using highspeed
microprogrammed
building
blocks, programmable
logic devices, gate arrays, or discrete logic
realizes the difficulties in integrating
the complete solution. In such a system,
the chip count escalates, the operating
power rises, and the development
schedule lengthens.
By integrating all these functions
and resources onto one high-speed
CMOS chip-the PACIOOO microcontroller-WaferScale Integration Inc.
has drastically reduced the chip count
from the typically required 50 or so ICs
to just one. At the same time, the
PACIOOO slashes the power consumption from tens of watts to less than 1.5
Wand cuts development time.
The PACIOOO can solve many highend embedded control applications and
is the only available circuit that can
tackle system, data, and event control
tasks. A C-like language and PC-hosted
system-development tools simplify the
creation of the control software. Users
can configure the circuit as a microprocessor peripheral or as a standalone
controller to meet the unique requirements of high-performance system,
data, or event controllers. Each of the
chip's two bidirectionall6-bit buses, its
individual I/O lines, and interrupt inputs can, if necessary, be redefined during each 50-ns instruction cycle.
Repnnted WIth permiSSIOn from ELECTRONIC DESIGN· October 27. 1988
At the heart of the PACIOOO's flexibility lies an internal microprogrammable architecture, including a 16-bit CPU,
a fast 10-bit microsequencer, a 32-wordby-16-bit register file, and a lkword-by64-bit high-speed EPROM. As product
planning manager Yoram Cedar explains, since the circuit executes any of
its instructions in one clock cycle, the
controller delivers a raw throughput of
Copynght 1988 VNU Business PublicationS, Inc
-----------------------------------------rjfAr~~----------------------------------------1-16
- - Ie
Article Reprint
COVER: USER·CONFIGURABLE
CONTROLLER
20 MIPS.
Every instruction of the PAC1000
can perform as many as three simultaneous operations: program control, CPU functions, and output control, with all possible combinations
allowed. Cedar claims the more powerful instruction format, combined
with the higher clock speed, yields a
five- to tenfold performance improvement, compared with other
one-chip microcontrollers. The high
throughput suits many tasks well. It
has already found homes in radar,
communications, video-graphics,
110 subsystems, bus and DMA controllers, and disk-drive-controllers.
Besides the CPU, register file, and
sequencer, the chip includes an auxiliary Q-register for double-word operations, an 8-input interrupt controller, 16 output control lines, 8 bi-
THE PAC1000
Clock
Host address
Host data bus and data bus
Reset
Extended·precision
register for 64·blt
operations
loop counter
I BreakpOint register I
Program counter
CASE logic
User
output
Test logIC
Interrupt
logIC
16
User·definable Condillon·
output
code
lines
sense
inputs
Interrupt
inputs
110 lines
Address
1. PACKING AI6-bit microp"'"
grammable central processor with a 32word register file, a l-kword-by~-bit
microcode UV EPROM, sequencer, and
other configurable resources, the
PAClOOO user-configurable
microcontroller from WaferScale
Integration delivers a raw instrucfion
throughput of 20 MIPS at 20 MHz (top).
Designers can add or alter various blocks
to customize versions for high-volume
users (left).
directional 110 lines, scan-test an
CASE program test logic, and a 22bit external address bus (Fig. 1, top).
Also, Cedar emphasizes, the circuit deals much more rapidly with interrupts than most controllers do,
and that serves embedded control
applications well. The chip changes
program flow in either of two ways.
First, it has four user-definable interrupt input lines plus four dedicated internal interrupts that require
just 100 ns, at most, to alter the program flow. Second, another set of input lines-22 condition-code inputs
(8 external and 14 internal)-let the
processor alter the program flow
with condition calls and program
jumps in just one 5O-ns instruction
cycle.
And if on-chip resources don't
quite match an application's requirements, chip modifications can be
done for large-volume users. The circuit was designed with the company's standard-cell library, and many
of the chip's sections are actually
cells in WaferScale's library (Fig. 1,
left). Noticeable on the chip's left
side are the large cells that include
the 64-kbit EPROM block on the bottom and the 16-bit CPU on the upper
left. On the chip's right side, random
logic performs the control and interface functions; small standard cells
are used to create those circuits.
For every instruction, a dedicated
field specifies the bit pattern on the
output lines. Also, designers can individually program eight II 0 lines as
inputs or outputs or to perform special functions under the control of
the chip's mode and 110 registers.
The special functions turn the 110
lines into control signals that allow
various features and flags to indicate several status conditions. In addition to the eight 110 lines, the circuit has two 16-bit bidirectional buses that go on and off the chip: One
links with the host; the other is the
upper 16 bits of the address/data
bus. Another 16 lines are dedicated,
user-programmable latched output
lines. These can be changed on a cycle-by-cycle basis.
Thanks to all its buses and control
signals, the PAC1000 microcontroller operates as either a memory-
-------------------------------rIIJr~-------------------------------......
1-17
11
Article Reprint
COVER: USER·CONFIGURABLE
CONTROLLER
mapped peripheral to a microprocessor to offload the CPU (Fig. 2a) or as
a standalone controller running
from its own internally or externally
stored program (Fig. 2b). As a peripheral, the chip ties into the host
with a straightforward bus interface-a 16-bit data bus and a 6-bit address bus to access the internal resources of the PACI000-and the
standard Chip Select, Read, and
Write control lines. In the standalone
mode, the chip typically runs the application program from its internal
memory and uses its 16-bit output
bus and 8-bit I/O port to control the
application and communicate to a
host system.
To handle multiple operations in
parallel, the chip internally takes advantage of a long-64-bit-microcode word so that each word can control multiple sections of the circuitry. The on-chip microcode storage
area consists of a fast, reprogrammabie UV EPROM, organized as 1
kword by 64 bits. Since the EPROM
is read only by the on-chip logic, it
doesn't need high-current output
buffers, which slow down the memory access. Thus, the EPROM contents can be read very quickly-the
chip's 20-MHz version accesses
memory in just 30 ns, well within the
CPU's 50-ns instruction cycle time.
The memory is also secure. Users
can program a security bit to prevent
an external system from extracting
the code from the memory array.
Besides its own program memory,
the chip also has a separate address/
data bus that can be programmed for
either 16 or 22 address lines (with 64kword or 4-Mword off-chip addressing ranges, respectively). The address generator for the bus is separate from the sequencer that addresses the program memory. The
PAC1000 can therefore execute a
program while it's using the address
bus to move data from memory into
the on-chip register file or to an externally controlled device.
The address bus, in fact, can serve
as a simple direct-memory-access
controller when used with the onchip 22-bit address counter and 16-bit
block counter. This DMA controller
can transfer data from external
memory to the on-chip register file or
to an external device.
An eight-word FIFO register lets
a host microprocessor asynchronously load commands or data into
the controller. The 22-bit word
length in the FIFO register is employed, so that if data values are to
be loaded into the register file, the
lower 16 bits of the 22-bit word sent
over the host data bus represent the
data, and the next five bits-the lower five bits of the host-interface address bus-represent the register location into which the data will be
loaded (RO to R31). The sixth bit of
the host-interface address bus signifies whether the word loaded into the
FIFO register is a command or data
word. If it's a command, the lower 10
bits of the host-data bus are used as a
branch address to one of the 1024
memory locations in the EPROM.
The 10-bit sequencer addresses
the 1,024 words of program memory
and has a 15-level stack that permits
multiple subroutine calls to occur
without forcing the program to go
back to a higher level before calling
the next subroutine. Besides having
more levels in the stack than WaferScale's 5910 microsequencer, the
enhanced sequencer block has a 10bit loop counter that cuts overhead in
programs for loops and nested loops.
The application program can load the
counter with a constant or a value
calculated in the CPU.
Because programming fast, embedded controllers can get complicated, the company includes on-chip
programming and test features to
ease system development. For starters, a 1O-bit breakpoint register simplifies real-time debugging. It can be
loaded from either of two sources-a
value stored in a CPU register or a
constant value specified in the program memory. When the program
memory address matches the register contents, the register issues an
interrupt, which a service routine in
memory could then react to.
Test and CASE logic on the chip
also aids program and hardware
testing. The condition-code logic responds to 22 different program test
conditions that can be tested for true
PERIPHERAl OR STANDAlONE
Address
Address
I
Microprocessor
r -'
I
I
I
t
r I
t- PAC100 -
Host
interiace
I
";'p;;;l;;;;de -
t
1
.._ .......
I
CPU
r--C t I
-t
on ro
I
I
lal
Memory
Data
-
-
I-- I
let
on ro I
!
I
-
Status/
..J intenupts
Data·path
element,
high·speed
processor,
fast bus, etc.
I
-I - PACWOO CPU
I
I
Control
Host and
dala
interiace
..,
I Data
:
: f
Control
I
IStatus/interrupts
:
I
L ______ -'
Standalone mode
Memory
I
Data·path
element,
high·speed
processor,
fast bus._etc.
Ibl
1 2. MULTIPLE BUSES, AN ON-CHIP ADDRESS GENERATOR,
and sequencer blocks let the microcontroller operate as
a memory-mapped peripheral to offload the host microprocessor (a). Or it can he'operated as a standalone controller (b).
-------------------------~Jr;-------------------------
1-18
Article Reprint
COVER: USER·CONFIGURABLE
CONTROLLER
[I
SAMPLE PROGRAM FOR PAC1000 MICROCONTROlLER
r control memory read/write based on ceo *'
segment memcon ,
enmem equ h'0002' ,
dlsmem equ
/* output control constants
'/
/* enable memory
'/
'/
'/
'/
'/
h'0040' ,
wr
equ h'OOOO' :
rd
equ h'tOOO' ,
start
IF ceo, OUT enmem ;
FOR6,AOR ~ RO + R1 ,OUTwr,
AOR ~AOR+4,OUTrd,
ENDFOR , OUT wr ,
ELSE, OUT dlsmem 1
ENDIF,
end,
I * store begm addr mADA and loop
j* inC addr by 4 and do rdJwr
/. end loop body
/* disable mem If
ceo 15 not true
1 3, THE HIGH-LEVEL LANGUAGE
developed by WaferScale employs C'
language-like structures to let designers easily develop complex configuration microcode.
or not-true results. Up to four conditions can be tested simultaneously.
Tests can check for the state of various flags or register contents.
The processor handles two types
of CASE operations: standard and
priority. A CASE group consists of a
combination of four test conditions
that can be tested in a single cycle. In
that same cycle, the PACI000
branches to anyone of 16 locations,
depending on the status of the four
inputs to the CASE group being tested. The priority CASE instruction operates on internal and external interrupt conditions and treats interrupts
as prioritized test conditions. The priority encoder generates a branch to
the highest-priority condition.
Thanks to all its on-chip resources,
the PACIOOO is a powerful one-chip
controller, housed in a windowed, 88lead pin-grid-array package or an 84lead ceramic leaded chip carrier. An
84-lead plastic leaded chip carrier
package (the one-time-programmable version) is also available. Because the chip employs an EPROM
to hold the program, revisions to the
code are nO'more difficult than repro-
gramming a standard EPROM. Prototype systems and production products can benefit from the ability to
revise the code at the last minute.
To alleviate the complexity of microcode program development, WaferScale has assembled a series of
PC-hosted system-development
tools (PAC-SDT). These make the
PAClOOO as easy to program as any
one-chip microcontroller. A simple
example of a multiple-command expression in the C-Iike language lets
designers combine operations such
as FOR6,AOR=RO+Rl,OUT WR
(loop for six cycles, add the contents
of registers RO and Rl and store the
result in the AOR register, output
the value WR) in one word (Fig. 3).
The toolset has a system-entry language, a functional simulator, and a
device programmer (MagicPro). The
system-entry, language software is
the most critical part. The high-level
language uses a structure similar to
C's and practically eliminates writing routines in machine or assembly
code. But designers who are more
comfortable working on that level
can write machine-code routines.D
---------------------~~i--------------------1-19
Article Reprint
WSI Launches
The Programmable System Device;
A new class of user-configurable products;
a higher standard in functionality,
integration, and perfonnance.
PSD:™ n Programmable System Device.™
1) A user-configurable system-on-a-chip,
integrating high-performance EPROM, SRAM, and
Logic; 2) User configurable with a menu-driven,
familiar "C"-like language and lliM-PC®-hosted
system development tools; 3) A standard product
first launched in 1988 by WSI.
WSI's PSDTMProducts: A Major Advance in user-configurability
System Integration
Level of
Functionality
1988
Not just programmable logic, but programmable logic and memory-progra11Jmable systems.
WAFERSCALE INTEGRA nON. INC
47280 Kato Road
Fremont, California 94538
800/331·1030, extension 234
In California call:
800/323-3939, extension 234
Programmable System DeYlCe,PSD,and MAPl68 are tradernarXs of WaferScale lJlaegratlOll, Inc
PAL lSa f'CglStered trademadr. of Advanced MlCfO DevICeS, Inc; IBM PC lSa rcJ!SWed trademark oflJUernatwnai BuSiness MacIuI'lCS Corporauon
ecopynght 1988 by WaferScaie Integration, Inc All nshlSresened
-----------------------------------------------~Jr;-.--------------------------------------------1-20
-
NEW INTEL CHIP NUKES THE WORK·STATION MARKET/25
NONVOLATILE TECHNOLOGY TAKES ON A STRATEGIC ROLE/SO
Electronics"
SEMICOIIHCTOIS
A 'DISADVANTAGE' LUDS
TO A FAST 4-M81T EPROM
B
y making an advantage out of what a
lot of companies would
consider a serious
drawback, WaferScale
Integration Inc. has
come up with a 4-Mbit
erasable programmable
read-only memory in a
die size the same as or
smaller than memories
one fourth its density-and with access
times as fast or faster. Moreover, the
Fremont, Calif., company fabricated the
CMOS EPROM with the same tried-and-
tested process that it
used in its earlier 256Kbit and 1-Mbit designs.
Actually, WaferScale
more or less had to use
the same process-unlike most other EPROM
companies, it doesn't
have its own fabrication facilities, relying
instead on outside foundries. That could
be a serious disadvantage, but WaferScale
turns it into a boon. "We do not have the
luxury of playing around with the pro-
STlGGEIED GATES GIVE GREATER DEism
w............ staggered-contact,
staggered-gate architecture enables It to make a 4-Mblt
EPROM with Its old 1.2-,um process technology and still achIeve 9O-ns access times.
cess every time we want to improve the
speed, increase the density, or reduce the
die size," says Boaz Eitan, director of
device technology and memory design.
"Instead, working within very precise
limits, we must rely on circuit and architecture improvements to get the speed
and density enhancements we want."
By making those kinds of improvements, WaferScale could use its 1.2-,.m
process to build the new EPROM and still
achieve a 90- to 120-ns read-access time-as fast as any 1-Mbit EPROM available
and twice as fast as any of the 4-Mbit
EPROMs now being offered as samples.
The average cell size is only 9.5 I'm' and
the die area only 320 mil'. Competitive 4Mbit EPROMs available as samples from
such companies as Intel, NEe, and Toshiba require much tighter 0.8- to I-I'm
design rules to achieve die sizes ranging
from 375 to 385 mil'.
WaferScale's initial parts, specified at
100 to 120 ns, will be available in sample
quantities by midyear, with faster
parts-90 ns-arriving before the end of
the year.
WaferScale expects the new part will
find eager users among the manufacturers of high-performance 32-bit processors, in both reduced- and complex-instruction-set systems, says Dale Prull, director of marketing communications.
"Currently, systems designers have
had to make a choice when considering
memory for program or code storage:
low-density, sub-256-Kbit, sub-100-ns
EPROMs with no wait states, or 1-Mbit
designs with access times anywhere from
100 to 150 ns," he says. "Alternatively, if
both speed and density were required, designers had to sacrifice nonvolatility and
use static random-access memories in
combination with some form of nonvolatile memory."
STAGGERING. The improvements that
WaferScale made to boost performance,
says Syed Ali, manager of memory design, were largely circuit-design enhancements to the company's proprietary splitgate architecture [Electronics, July 9,
1987, p.65]. The enhancements include a
staggered-contact architecture that reduces the number of contacts in an array
by almost 25 times, and a staggered-cell
design that further improves packing
density by alternating the floating gates
and reducing bit-line area.
(over)
-------------------------~Jri------------------------1-21
III
Article Reprint
In addition, some tinkering with the
process resulted in a fieldless array that
allows devices to be moved closer together while at the same time increasing the
effective channel width. Although the bitline capacitance of this design is much
higher due to the longer continuous n+
bit lines, says Eitan, this disadvantage is
offset by the fact that the EPROM cell is
capable of generating read currents of
about 140 to 160 /LA at 5 V, about twice
what is possible with current EPROMs.
To improve the speed of the device, designers can employ a number of techniques. Chief among them are a differential-balanced amplifier design employing
address-transition detection, along with a
dual-function column multiplexer and decoder scheme.
The improvements give WaferScale a
decided advantage, Eitan says. At most
of the companies making EPROMs, circuit designers are running into a brick
wall as they try to improve density and
speed through scaling. The industry-standard ground-array architecture, with one
contact every two cells, limits the scalability of the cell.
WaferScale, by contrast, has eliminated this limitation with its proprietary
staggered virtual-ground-array architecture combining staggered contacts and
staggered cells. In effect, says Ali, the architecture allows significant reductions in
both cell and array size without pushing
the lithography.
-Bernard C. Cole
Reprinted With permiSSion from ELECTRONICS - March 1989
COPYright 1989 VNU Business Publications. Inc.
---------------------~Jr;~-----------------1-22
===,:~
--....
~~~~=~srAr _______________
C_M_O_S_P_R_O_D_U_C_T__S_U_M_M_A_R_Y
WAFERSCALE INTEGRA TION. INC.
PART NO.
DESCRIPTION
TEMP
SPEED (ns)
II
PACKAGES
PROMIRPROM Memory Products
WS57C191B
2K x 8 CMOS PROM/RPROM
C
I
M
35/45
45
45/55
24
28
24
28
WS57C291B
2K x 8 CMOS PROM/RPROM
C
I
M
35/45
45
45/55
24 Pin Plastic DIP, 0.3"
24 Pin CERDIp, 0.3"
WS57C43B
4K x 8 CMOS PROM/RPROM
C
I
M
35/45/55/70
45/55
45/55/70
WS57C43C
4K x 8 CMOS PROM/RPROM
-
25/30
Advance Information
WS57C45
2K x 8 Registered CMOS
PROM/RPROM
C
M
25/35
35/45
24
28
24
24
Pin CERDIp, 0.3"
Pad CLLCC
Pin Ceramic Flatpack
Pin Plastic DIP, 0.3"
WS57C49B
8K x 8 CMOS PROM/RPROM
C
I
M
35/45/55/70
45
45/55/70
24
28
24
24
28
24
24
Pin CERDIP, 0.6"
Pin PLDCC
Pin Plastic DIP, 0.6"
Pin CERDIp, 0.3"
Pad CLLCC
Pin Plastic DIP, 0.3"
Pin Ceramic Flatpack
WS57C49C
8Kx8CMOSPROMffiPROM
-
WS57C51B
16K x 8 CMOS PROM/RPROM
C
M
40/45/55/70
45/55/70
28
32
28
32
Pin CERDIp, 0.6"
Pin CLDCC
Pin CERDIP, 0.3"
Pad CLLCC
WS57C71C
32K x 8 CMOS RPROM
C
M
40/45/55
55
28
32
28
32
Pin CERDIP, 0.6"
Pin CLDCC
Pin CERDIP, 0.3"
Pad CLLCC
25/30
24
28
24
24
28
Pin CERDIp, 0.6"
Pin PLDCC
Pin Plastic DIP, 0.6"
Pad CLLCC
Pin CERDIP, 0.6"
Pin PLDCC
Pin Plastic DIP, 0.3"
Pin CERDIp, 0.3"
Pad CLLCC
Advance Information
EPROM Memory Products (Bytewide)
WS27C64F
Military 8K x 8 CMOS EPROM
M
90/100
WS27C64L
8K x 8 CMOS EPROM
C
I
M
90/120/150/200
120
120/150/200
32 Pad CLLCC
28 Pin CERDIp, 0.6"
28
28
32
28
Pin
Pin
Pin
Pin
CERDIP, 0.6"
CERDIP, 0.3"
PLDCC
Plastic DIP, 0.6"
1-23
CMOS Product Summary
CMOS PRODUCT SUMMARY (Cant.)
PART NO.
DESCRIPTION
TEMP
SPEED (ns)
PACKAGES
EPROM Memory Products (8ytewide) (Cont.)
WS57C64F
8K x 8 CMOS EPROM
C
I
M
55/70
70
70
WS27C128F
Military 16K x 8 CMOS EPROM
M
90
WS27C128L
16K x 8 CMOS EPROM
C
I
M
90/120/150
WS57C128F
16K x 8 CMOS EPROM
120
120/150/200
C
I
M
55/70
70
70
WS27C256F
32K x 8 CMOS EPROM
C
M
45/55/70
70/90
WS27C256L
32K x 8 CMOS EPROM
C
I
M
90/120/150
120/150/200
1201150
28 Pin CERDIp, 0.6"
32 Pad CLLCC
32 Pin PLDCC
32 Pad CLLCC
28 Pin CERDIp, 0.6"
28
32
28
28
Pin
Pin
Pin
Pin
CERDIP, 0.6"
PLDCC
Plastic DIP, 0.6"
CERDIP, 0.3"
28 Pin CERDIP, 0.6"
32 Pad CLLCC
28 Pin CERDIp, 0.6"
32 Pad CLLCC
32 Pin CLDCC
28
28
32
32
32
28
Pin CERDIp, 0.6"
Pin CERDIp, 0.3"
Pad CLLCC
Pin PLDCC
Pin CLDCC
Pin Plastic DIP, 0.6"
WS57C256F
32K x 8 CMOS EPROM
C
I
M
40/55/70/90
70/90
55/70/90
28 Pin CERDIP, 0.6"
32 Pad CLLCC
32 Pin CLDCC
WS27C512F
64K x 8 CMOS EPROM
C
M
90
90/120
32 Pad CLLCC
28 Pin CERDIP, 0.6"
55/70/90
Advance Information
WS57C512F
64K x 8 CMOS EPROM
-
WS27C512L
64K x 8 CMOS EPROM
C
M
100/120/150
150/200
28
32
32
32
Pin CERDIp, 0.6"
Pin PLDCC
Pad CLLCC
Pin CLDCC
WS27C010L
128K x 8 CMOS EPROM
C
I
M
100/120/150/200
120/150
120/130/150/200
32
32
32
32
32
Pin CERDIP, 0.6"
Pin CLDCC
Pad CLLCC
Pin PLDCC
Pin Plastic DIP, 0.6"
WS57C010M
128K x 8 CMOS EPROM
-
55/70
Advance Information
WS27C010F
Advance Information
128K x 8 CMOS EPROM
-
55/70/901100
WS27C020L
256K x 8 CMOS EPROM
-
120/150/170/200
Advance Information
WS27C040L
512K x 8 CMOS EPROM
C
M
120/150/170/200
150/170/200
32 Pin CERDIP, 0.6"
32 Pad CLLCC
__________________________________
1-24
__________________________________
r6'~E
Ells;;
CMOS Product Summary
CMOS PRODUCT SUMMARY (Cant.)
PART NO.
DESCRIPTION
SPEED (ns)
TEMP
PACKAGES
EPROM Memory Products (Wordwide)
WS57C65
4K x 16 CMOS EPROM
C
55/70
44 Pad CLLCC
40 Pin CERDIP, 0.6"
WS57C257
16K x 16 CMOS EPROM
C
I
M
55/70
70/90
70/90
40 Pin CERDIp, 0.6"
44 Pad CLLCC
44 Pin CLDCC
WS27C210L
64K x 16 CMOS EPROM
C
M
100/120/150/200
120/150/200
WS57C210M
64K x 16 CMOS EPROM Module
C
M
55/70/90
70/90
WS27C210F
64K x 16 CMOS EPROM
-
55/70/90/100
Advance Information
WS27C220L
128K x 16 CMOS EPROM
-
120/150/170/200
Advance Information
WS27C240L
256K x 16 CMOS EPROM
-
120/150/170/200
Advance Information
MAP168
User-Configurable Peripheral
with Memory
C
M
PSD301
User-Configurable Peripheral
with Memory
-
PAC1000
User-Configurable Microcontroller
C
12/16/20 MHz
I
12/16 MHz
M
12/16 MHz
C
I
M
20/25/30 MHz
20 MHz
20 MHz
40
44
44
44
Pin CERDIp, 0.6"
Pin PLDCC
Pad CLLCC
Pin CLDCC
40 Pin Ceramic SIB, 0.6"
Programmable System Devices
SAM448
User-Configurable Microsequencer
40/45/55
45/55
120/150/200
44
44
44
44
Pad CLLCC
Pin PLDCC
Pin CLDCC
Pin CPGA
Advance Information
100 Pin Ceramic Quad
Flatpack, Gull Wing
100 Pin Plastic Quad
Flatpack, Gull Wing
88 Pin CPGA
28
28
28
28
Pin
Pin
Pin
Pin
PLDCC
CLDCC
Plastic DIP, 0.3"
CERDIP, 0.3"
CMOS Logic Products
WS5901
CMOS 4-Bit High-Speed
Microprocessor Slice
C
M
C/D
C/D
40 Pin Plastic DIP, 0.6"
40 Pin CERDIP, 0.6"
WS59016
CMOS 16-Bit High-Speed
Microprocessor Slice
C
M
C/D
C/D
64 Pin Ceramic SIB, 0.9"
68 Pin PLDCC
68 Pin CLDCC
WS59032
CMOS 32-Bit High-Speed
Microprocessor Slice
C
M
DIE
DIE
101 Pin CPGA
WS5910NB
CMOS Microprogram Controller
C
M
20/30 MHz
20/30 MHz
=-1iE~ ~=-
40 Pin Plastic DIP, 0.6"
40 Pin CERDIp, 0.6"
------------------------------------~~~----------------------------------1-25
II
CMOS Product Summary
CMOS PRODUCT SUMMARY (Cont.)
PART NO.
DESCRIPTION
TEMP
SPEED (ns)
PACKAGES
CMOS Logic Products (Cont.)
WS59510
CMOS 16 x 16 Multiplier
Accumulator
C
M
30/35/40/50 ns
40/50 ns
68 Pin PLDCC
68 Pin CPGA
64 Pin Plastic DIP, 0.9"
WS59520/521
CMOS Multilevel Pipeline
Register
C
M
22 ns
24 ns
24 Pin Plastic DIP, 0.3"
24 Pin CERDIp, 0.3"
WS59820
CMOS Bidirectional Bus
Interface Registers
C
M
23 ns
25 ns
68 Pin PLDCC
68 Pin CPGA
WS59820B
CMOS Bidirectional Bus
Interface Registers
C
M
23 ns
25 ns
68 Pin PLDCC
68 Pin CPGA
System Development Tools
Memory-Silver
WSI EPROM/PROM-RPROM/Flash Programming Software, User's Manual, WSI-Support
Memory-Gold
Memory-Silver, WS6000 MagicPro Programmer, WSI-Support
PAC1000-Silver
PAC1000 Software, Software User's Manual, WSI-Support
PAC1000-Gold
PAC1000-Silver, WS6000 MagicPro Programmer, WSI-Support
MAP168-Silver
MAP168 Software, Software User's Manual, WSI-Support
MAP168-Gold
MAP168-Silver, WS6000 MagicPro Programmer, WSI-Support
SAM448-Silver
SAM448 Software, Software User's Manual, WSI-Support
SAM448-Gold
SAM448-Silver, WS6000 MagicPro Programmer, WSI-SuP8ort
WSI-Support
12-Month Software Update Service, 24-Hour Bulletin Board, Applications Hotline
WS6000
Memory and PSD Programmer
WS6001
MagicPro Adaptor, 28 Pin CLLCC Package, Memory
WS6003
MagicPro Adaptor, 44 Pin PLDCC/CLDCC/CLLCC Package, MAP168
WS6008
MagicPro Adaptor, 28 Pin 0.3" DIP, SAM448
WS6009
MagicPro Adaptor, 28 Pin PLDCC/CLDCC/CLLCC Package, SAM448
WS6010
MagicPro Adaptor, 88 Pin PGA Package, PAC1000
WS6011
MagicPro Adaptor, 44 Pin PGA Package, MAP168
WS6012
MagicPro Adaptor, 32 Pin CLDCC Package, Memory
WS6013
MagicPro Adaptor, 100 Pin Quad Flatpack Package, PAC1000
WS6014
MagicPro Adaptor, 44 Pin CLDCC/PLDCC Package, MAP168/PSD301
WS6015
MagicPro Adaptor, 44 Pin PGA Package, MAP168/PSD301
---------------------~Jr;~-----------------1-26
iFEE
__
-~-
,:~
~
~~~~~~aJAr
____________N
__
UM
__ER_I_C_A_L_P_R_O_D_U_C_T_L_I_ST_'_
N_G
WAFERSCALE INTEGRATION, INC.
PART NO.
DESCRIPTION
TEMP
SPEED (n5)
C
M
40/45/55
45/55
MAP168
User-Configurable Peripheral
with Memory
MAP168-Silver
MAP168-Gold
MAP168 Software, Software User's Manual, WSI-Support
MAP168-Silver, WS6000 MagicPro Programmer, WSI-Support
PSD301
User-Configurable Peripheral
with Memory
-
1201150/200
SAM448
User-Configurable Microsequencer
C
I
M
20/25/30 MHz
20 MHz
20 MHz
SAM448-Silver
SAM448-Gold
SAM448 Software, Software User's Manual, WSI-Support
SAM448-Silver, WS6000 MagicPro Programmer, WSI-Support
PAC1000
User-Configurable Microcontroller
C
12/16/20 MHz
I
12/16 MHz
M
12/16 MHz
PACKAGES
44
44
44
44
Pad CLLCC
Pin PLDCC
Pin CLDCC
Pin CPGA
Advance Information
28
28
28
28
Pin
Pin
Pin
Pin
PLDCC
CLDCC
Plastic DIP, 0.3"
CERDIP, 0.3"
100 Pin Ceramic Quad
Flatpack, Gull Wing
100 Pin Plastic Quad
Flatpack, Gull Wing
88 Pin CPGA
PAC1000-Silver
PAC1000-Gold
PAC1000 Software, Software User's Manual, WSI-Support
PAC1000-Silver, WS6000 MagicPro Programmer, WSI-Support
WS27C64F
Military 8K x 8 CMOS EPROM
M
90/100
WS27C64L
8K x 8 CMOS EPROM
C
I
M
90/120/150/200
120
120/150/200
28
28
32
28
Pin
Pin
Pin
Pin
WS57C438
4K x 8 CMOS PROM/RPROM
C
I
M
35/45/55/70
45/55
45/55/70
24
28
24
24
28
Pin CERDIP, 0.6"
Pin PLDCC
Pin Plastic DIP, 0.3"
Pin CERDIp, 0.3"
Pad CLLCC
WS57C43C
4Kx8CMOSPROMffiPROM
-
25/30
Advance Information
WS57C45
2K x 8 Registered CMOS
PROM/RPROM
C
M
25/35
35/45
24
28
24
24
Pin CERDIP, 0.3"
Pad CLLCC
Pin Ceramic Flatpack
Pin Plastic DIP, 0.3"
WS57C498
8K x 8 CMOS PROM/RPROM
C
35/45/55/70
45
45/55/70
24
28
24
24
28
24
24
Pin CERDIp, 0.6"
Pin PLDCC
Pin Plastic DIP, 0.6"
Pin CERDIP, 0.3"
pad CLLCC
Pin Plastic DIP, 0.3"
Pin Ceramic Flatpack
I
M
WS57C49C
8K x 8 CMOS PROM/RPROM
-
25/30
32 Pad CLLCC
28 Pin CERDIp, 0.6"
CERDIP, 0.6"
CERDIP, 0.3"
PLDCC
Plastic DIP, 0.6"
Advance Information
1-27
Numerical Product Listing
NUMERICAL PRODUCT LISTING (Cont.)
PART NO.
DESCRIPTION
TEMP
SPEED (ns)
PACKAGES
WS57C51B
16K x 8 CMOS PROM/RPROM
C
M
40/45/55/70
45/55/70
WS57C64F
8K x 8 CMOS EPROM
C
I
M
55/70
70
70
28 Pin CERDIP, 0.6"
32 Pad CLLCC
32 Pin PLDCC
WS57C65
4K x 16 CMOS EPROM
C
55/70
44 Pad CLLCC
40 Pin CERDIp, 0.6"
WS57C71C
32K x 8 CMOS RPROM
C
M
40/45/55
55
WS5901
CMOS 4-Bit High-Speed
Microprocessor Slice
C
M
C/O
C/D
40 Pin Plastic DIP, 0.6"
40 Pin CERDIP, 0.6"
WS5910A/B
CMOS Microprogram Controller
C
M
20/30 MHz
20/30 MHz
40 Pin Plastic DIP, 0.6"
40 Pin CERDIp, 0.6"
WS6000
Memory and PSD Programmer
WS6001
MagicPro Adaptor, 28 Pin CLLCC Package, Memory
WS6003
MagicPro Adaptor, 44 Pin PLDCC/CLDCC/CLLCC Package, MAP168
WS6008
MagicPro Adaptor, 28 Pin 0.3" DIP, SAM448
WS6009
MagicPro Adaptor, 28 Pin PLDCC/CLDCC/CLLCC Package, SAM448
WS6010
MagicPro Adaptor, 88 Pin PGA Package, PAC1000
WS6011
MagicPro Adaptor, 44 Pin PGA Package, MAP168
WS6012
MagicPro Adaptor, 32 Pin CLDCC Package, Memory
WS6013
MagicPro Adaptor, 100 Pin Quad Flatpack Package, PAC1000
WS6014
MagicPro Adaptor, 44 Pin CLDCC/PLDCC Package, MAP168/PSD301
WS6015
MagicPro Adaptor, 44 Pin PGA Package, MAP168/PSD301
WS27C010F
128K x 8 CMOS EPROM
-
WS27C010L
128K x 8 CMOS EPROM
C
I
M
100/1201150/200
120/150
1201130/150/200
32
32
32
32
32
WS27C020L
256K x 8 CMOS EPROM
-
120/150/170/200
Advance Information
WS27C040L
512K x 8 CMOS EPROM
C
M
120/150/170/200
15011701200
32 Pin CERDIP, 0.6"
32 Pad CLLCC
WS27C128F
Military 16K x 8 CMOS EPROM
M
90
32 Pad CLLCC
28 Pin CERDIP, 0.6"
55/70/90/100
28
32
28
32
28
32
28
32
Pin CERDIp, 0.6"
Pin CLDCC
Pin CERDIp, 0.3"
Pad CLLCC
Pin CERDIp, 0.6"
Pin CLDCC
Pin CERDIp, 0.3"
Pad CLLCC
Advance Information
Pin CERDIp, 0.6"
Pin CLDCC
Pad CLLCC
Pin PLOCC
Pin Plastic DIP, 0.6"
------------------------~Jr;-----------------------1-28
Numerical Product Listing
NUMERICAL PRODUCT LISTING (Cont.)
PART NO.
WS27C128L
DESCRIPTION
16K x 8 CMOS EPROM
TEMP
SPEED (ns)
C
I
M
90/120/150
120/150/200
55/70/90/100
120
PACKAGES
28
32
28
28
Pin
Pin
Pin
Pin
CERDIp, 0.6"
PLDCC
Plastic DIP, 0.6"
CERDIP, 0.3"
WS27C210F
64K x 16 CMOS EPROM
-
WS27C210L
64K x 16 CMOS EPROM
C
M
100/120/150/200
120/150/200
40
44
44
44
WS27C220L
128K x 16 CMOS EPROM
-
120/150/170/200
Advance Information
WS27C240L
256K x 16 CMOS EPROM
-
120/150/170/200
Advance Information
WS27C256F
32K x 8 CMOS EPROM
C
M
45/55/70
70/90
28 Pin CERDIp, 0.6"
32 Pad CLLCC
32 Pin CLDCC
WS27C256L
32K x 8 CMOS EPROM
C
I
M
90/120/150
120/150
120/150/200
WS27C512F
64K x 8 CMOS EPROM
C
M
90/120
100/120/150
150/200
90
Advance Information
28
28
32
32
32
28
Pin CERDIP, 0.6"
Pin PLDCC
Pad CLLCC
Pin CLDCC
Pin CERDIp, 0.6"
Pin CERDIp, 0.3"
Pad CLLCC
Pin PLDCC
Pin CLDCC
Pin Plastic DIP, 0.6"
32 Pad CLLCC
28 Pin CERDIp, 0.6"
WS27C512L
64K x 8 CMOS EPROM
C
M
WS57C010M
128K x 8 CMOS EPROM Module
-
55/70
Advance Information
WS57C128F
16K x 8 CMOS EPROM
C
I
M
55/70
28 Pin CERDIP, 0.6"
32 Pad CLLCC
C
I
M
35/45
45/55
C
55/70/90
M
70/90
C
I
M
40/55/70/90
70/90
55/70/90
WS57C191B
WS57C210M
WS57C256F
2K x 8 CMOS PROMIRPROM
64K x 16 CMOS EPROM Module
32K x 8 CMOS EPROM
70
70
45
28
32
32
32
24
28
24
28
Pin CERDIP, 0.6"
Pin PLDCC
Pad CLLCC
Pin CLDCC
Pin CERDIp, 0.6"
Pin PLDCC
Pin Plastic DIP, 0.6"
Pad CLLCC
40 Pin Ceramic SIB,
0.6"
28 Pin CERDIP, 0.6"
32 Pad CLLCC
32 Pin CLDCC
------------------------~Jr;-----------------------1-29
Numerical Product Listing
NUMERICAL PRODUCT LISTING (Cant.)
PART NO.
DESCRIPTION
TEMP
SPEED (ns)
PACKAGES
WS57C257
16K x 16 CMOS EPROM
C
I
M
55/70
70/90
70/90
40 Pin CERDIP, 0.6"
44 Pad CLLCC
44 Pin CLDCC
WS57C291B
2K x 8 CMOS PROM/RPROM
C
I
M
35/45
45
45/55
24 Pin Plastic DIP, 0.3"
24 Pin CERDIp, 0.3"
WS57C512F
64K x 8 CMOS EPROM
-
55/70/90
WS59016
CMOS 16-Bit High-Speed
Microprocessor Slice
C
M
CID
C/D
64 Pin Ceramic SIB, 0.9"
68 Pin PLDCC
68 Pin CLDCC
WS59032
CMOS 32-Bit High-Speed
Microprocessor Slice
C
M
DIE
DIE
101 Pin CPGA
WS59510
CMOS 16 x 16 Multiplier
Accumulator
C
M
30/35/40/50
40/40
68 Pin PLDCC
68 Pin CPGA
64 Pin Plastic DIP, 0.9"
WS59520/521
CMOS Multi-Level Pipeline Register
C
M
22
24
24 Pin Plastic DIP, 0.3"
24 Pin CERDIp, 0.3"
WS59820
CMOS Bidirectional Bus Interface
Registers
C
M
23
25
68 Pin PLDCC
68 Pin CPGA
WS59820B
CMOS Bidirectional Bus Interface
Registers
C
M
23
25
68 Pin PLDCC
68 Pin CPGA
Memory-Silver
WSI EPROM/PROM-RPROM/Flash Programming Software, User's Manual, WSI-Support
Memory-Gold
Memory-Silver, WS6000 MagicPro Programmer, WSI-Support
WSI-Support
12-Month Software Update Service, 24-Hour Bulletin Board, Applications Hotline
Advance Information
----------------------~Jri---------------------1-30
===~~
--....,
-------r~
............
ORDERING INFORMATION
~~
WAFERSCALE INTEGRA110N, INC.
HIGH-PERFORMANCE CMOS PRODUCTS
WS57C----'-.,-'
-35
II
B
D
L
Basic Part Number
Manufacturing Process:
(Blank)
=
B
= MIL·STD·883C Manufacturing Flow
WSI Standard Manufacturing Flow
Operating Temperature Range:
(Blank)
= Commercial:
0° to +70°C
Vee: +5V ± 5%
= Industrial: -40° to +85°C
Vee: +5V ± 10%
M
=
Military: -55° to +125°C
Vee: +5V ± 10%
Package:
Window
A
B
C
D
F
G
H
No
No
Yes'
Yes
Yes'
No
No'
No'
No'
Yes'
No'
No
No'
Yes
No
Yes
J
K
L
N
P
Q
R
S
T
W
X
Y
Z
= PPGA Plastic Pin Grid Array
= 0.900" Size Brazed Ceramic DIP
= CLLCC Ceramic Leadless Chip Carrier
= 0.600" CERDIP
= Ceramic Flatpack
= CPGA Ceramic Pin Grid Array
= Ceramic Flatpack
= Plastic Leaded Chip Carrier
= 0.300" Thin CERDIP
= CLDCC Ceramic Leaded Chip Carrier
= CLDCC Ceramic Leaded Chip Carrier
= 0.600" Plastic DIP
= Plastic Quad Flatpack
= Ceramic Side Brazed
= 0.300" Thin Plastic DIP
= 0.300" Thin CERDIP
= Waffle Packed Dice
= Ceramic Pin Grid Array
= 0.600" CERDIP
= CLLCC
Yes
No
No
Speed:
-35 = 35 ns
-55 = 55 ns
-70 = 70 ns
Etc.
• Surface Mount
1·31
~1_3~2----------------------~Jri------------------------
Product Cross Reference
PRODUCT CROSS REFERENCE (Cont.)
NATIONAL
878321
93Z665C
93Z667C
DM778321
DM878291
DM878291A
DM878291B
DM878321
DM878R191
DM878R193
NMC27C256
NMC27C512A
NMC27C1023
NMC27C1024
VM27C256
WSI
W857C43/43B
W857C49/49B
W857C49/49B
W857C43/43B
W857C291B
W857C291B
W857C291B
W857C43/43B
W857C191B
W857C191B
W827C256L,F
W827C512L
W827C010L
W827C210L
W827C256L,F
WSI
W859510
W859510
NEC
27HC65
M27C256
I-lPB429
I-lPB429
I-lPD27C256
I-lPD27C512D
I-lPD27C1024
WSI
W857C49/49B
W827C256L,F
W857C191B
W857C291B
W857C256F
W827C512L
W827C210L
MATRA-HARRIS
M82010
WSI
W859510
OKI
M8M27C256
M27512
WSI
W827C256L,F
W827C512L
MITEL
M27C256
M27256
M5L27256
WSI
W827C256L,F
W827C256L,F
W827C256L,F
MITSUBISHI
M5L27C128
M5L27256K
M27C512
WSI
W827C128L
W827C256L,F
W827C512L
RAYTHEON
29671
29671 A
29681
29681A
29683A
39VP864
WSI
W857C43/43B
WS57C43/43B
W857C291B
W857C291B
W857C191B
W857C49/49B
SANYO
LA7620
WSI
W857C64F
MMI
5383281
6381681
6381681A
6381681A
6383281
631681
WSI
W857C43/43B
W857C191B
W857C191B
W857C291B
W857C43/43B
W857C291B
SEEQ
36C16
36C32
36816
27C256
2764
27256
WSI
W857C191B
W857C43/43B
W857C291B
W857C256L,F
W857C64F
W857C256L,F
MOTOROLA
MCM76
MCM76160
MCM76161
WSI
W857C191B
W857C291B
W857C291B
SHARP
LH5749
LH5763
LH57127
LH57191
LH57256
8H5762
WSI
W857C49/49B
W857C64F
W857C51/51B
W857C191B
W857C256F
W857C49/49B
lOT
IDTT421 0
IDT39C01
IDT39C1 0
IDT49C401
29FCT521
WSI
W859510
W85901
W859510A/B
W859016*
W859520/521
INTEL
1M29C510
27C128/A
27C256
27010
27210
27512
WSI
W859510
W827C128L
W827C256L,F
W827C010L
W827C210L
W827C512L
LOI
LMA1010
LMA2010
L29C520
L29C521
L429C01
WSI
W859510
W859510
W859520/21
W859520/21
W85901
LSI LOGIC
L64010
L64012
.,,====
1-34
rnl"i
Product Cross Reference
PRODUCT CROSS REFERENCE (Cont.)
SIGNETICS
27C256
27C512
27HC641
27HC642
N82H8321
N82H8641
N82H81281
N828191
N828191
N828191A
N828191A
N828191B
N828191B
N828641
WSI
W857C256L,F
W827C512L
W857C49/49B
W857C49/49B
W857C43/43B
W857C49/49B
W857C51/51B
W857C191B
W857C291B
W857C191B
W857C291B
W857C191B
W857C291B
WS57C49/49B
SPRAGUE
SCM27C256
WSI
WS27C256L,F
SSI
8S1203
WSI
W857C49/49B
THOMSON
JBP388165
JBP38S165
TS27C256
WSI
W857C191B
WS57C291B
WS27C256L, F
* Functional
TI
388165
388165
8MJ27C128
8MJ27C256
8MJ27C512
8N74HCT9510
TICPAL1010
TM827C128
TM827C256
TM827C292
TM827C292
TMS278C49
WSI
W857C191B
W857C291B
W827C128L
W827C256L,F
W827C512L
W859510
W859510
W827C128L
W827C256L,F
W857C191B
W857C291B
WS57C49/49B
TOSHIBA
TMM27256
TMM27512D
WSI
WS27C256L,F
WS27C512L
TRW
TMC2210
WSI
W859510
WEITEK
WTL1010
WTL2010
WTL2245
WSI
WS59510
WS59510
WS59510
Equivalent
------------------------~Jri-----------------------1-35
II
~1-3=6-----------------------~Jr;-------------------------
WAFERSCALE INTEGRATION, INC.
ADVANCE INFORMATION/PRELIMINARY/
FINAL DEFINED
ADVANCE INFORMATION:
A WSI product data sheet marked "Advance Information" on its cover page describes a
product that is in the planning stages at WSI at the time this book went to press. Design
parameters and objectives are included in the data sheet but are subject to change
before the actual product is formally introduced. Please contact your WSI Sales
Representative or Distributor for availability status.
PRELIMINARY:
A WSI product data sheet marked "Preliminary" on its cover page describes a product
that requires further characterization testing. Functional parameters are "frozen" but
certain electrical limits may be subject to slight change before the data sheet is "Final."
Please contact your WSI Sales Representative or Distributor for price and availability.
FINAL:
A WSI product data sheet without either "Advance Information" or "Preliminary" on the
cover page describes a product that has completed all characterization and reliability
testing. All functional and electrical parameters are "frozen." Please contact your WSI
Sales Representative or Distributor for price and availability.
-----------------------~Jri----------------------1-37
---~------~~~~--
1'1
~1-3~8----------------------~Jr;------------------------
- - - - - - - - - - - - ------------
WAFERSCALE INTEGRATION, INC.
PROMIRPROM MEMORY PRODUCTS
'9~-f~{~*uiI
~:";~:~~~::,IN:-,:':,;f:C~:. . .
2
SECTION INDEX
PROMIRPROM MEMORY PRODUCTS
PROM/RPROM Selection Guide . ..................................................... 2-1
WS57C191B/291B
High Speed 2K x 8 CMOS PROM/RPROM ............................... 2-3
WS57C43B
High Speed 4K x 8 CMOS PROM/RPROM ............................... 2-9
WS57C43C
High Speed 4K x 8 CMOS PROM/RPROM ............................... 2-15
WS57C45
High Speed 2K x 8 Registered CMOS PROM/RPROM ..................... 2-19
WS57C49B
High Speed 8K x 8 CMOS PROM/RPROM .............................. 2-27
WS57C49C
High Speed 8K x 8 CMOS PROM/RPROM .............................. 2-33
WS57C51B
High Speed 16K x 8 CMOS PROM/RPROM .............................. 2-37
WS57C71C
High Speed 32K x 8 CMOS RPROM ................................... 2-43
For additional information,
call 800-TEAM-WSI (800-832-6974).
In California, call 800-562-6363.
-------------------------------rJr§~~------------------------------~._.s
WAFERSCALE INTEGRATION, INC.
PROMIRPROM SELECTION GUIDE
ARCHITECTURE
32Kx 8
I
WS57C71C
I
I
8Kx8
IWS57C49C
I
IWS57C43C
I
WS57C51B
I
8Kx8
4Kx8
I
I
16Kx 8
WS57C49B
I
WS57C43B
I
I
4Kx8
I
I
2Kx8
(REGISTERED)
I
WS57C45
I
I
I
I
I
2Kx8
WS57C191B
2Kx8
WS57C291B
I
25
30
I
35
!
!
I
!
I
I
40
45
50
55
60
65
70
ACCESS TIME (ns)
2-1
~2_2---------------------~Jr;----------------------
-.. _--==- ....
~
:r
::=
-~-
...--~
==;;;:
------- - -
WS57C191BI291B
r..-~.-_
~~
.-.
WAFERSCALE INTEGRATION, INC.
x 8 CMOS PROMIRPROM
HIGH SPEED 2K
KEY FEATURES
• Ultra-Fast Access Time
-
• Pin Compatible with AM27S191/291
and N82S191 Bipolar PROMs
35 ns
• Low Power Consumption
• Immune to Latch-Up
• Fast Programming
-
up to 200 mA
• ESD Protection Exceeds 2000V
• DESC SMD Nos. 5962-87650/5962-88734
GENERAL DESCRIPTION
The WS57C191B/291B is an extremely HIGH PERFORMANCE 16K UV Erasable Electrically Re-Programmable Read
Only Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM speeds
while consuming only 25% of the power of its Bipolar counterparts.
A further advantage of the WS57C191B/291B over Bipolar PROM devices is the fact that it utilizes a proven EPROM
technology. This allows the entire memory array to be tested for switching characteristics and functionality after
assembly. Unlike devices which cannot be erased, every WS57C191B/291B is 100% tested with worst case test patterns
both before and after assembly.
The WS57C191B/291B is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for
systems which are currently using Bipolar PROMs.
PIN CONFIGURATION
MODE SELECTION
~s
MODE
TOP VIEW
CS11
V pp
CS2
CS3
Vcc
OUTPUTS
CERDIP/Plastic DIP
Chip Carrier
Read
V IL
V IH
V IH
Vee
DouT
Output
Disable
V IH
X
X
Vee
High Z
Output
Disable
X
Program
V pp
X
X
Vee
DIN
Program
Verify
V IL
V IH
V IH
Vee
DouT
Output
Disable
X
VIL
X
X
VIL
Vee
Vee
High Z
High Z
NC
A5AS A71Vcc Aa Ag
-
,.......-, r - -
A7 ~ 1
~J~' l2J~j~~~~~~
1
A,
5
A,
6
A,
A,
Ao
NC
00
7
8
9
10
11
0
A.~2
25[= A,o
A5~3
24~:
A4 (4
23[=
22,:
21,:
20 [=
19,:
12 13 1415161718
CSlIVpp
CS2
CS3
NC
07
0.
r'1 r'1 r -. .. ., ,.....,,..., ,....,
I
I,
II
"',"','
0,0, INC 0,°4 0,
GND
-
24 ~ Vee
23~A.
22pA 9
21~AlO
A, ~ 5 0 2 0 ~ CS1IVpp
A,~ 6
19 ~ CS2
A,~ 7
18 CS3
Ao[ 8
17 0 7
00 ~ 9
16 ~ o.
0, ~ 10
15 ~ 0,
0, [ 11
14 0 4
GND [ 12
13 0,
P
P
P
P
PRODUCT SELECTION GUIDE
PARAMETER
WS57C191 8/291 8-35
WS57C191 8/291 8-45
WS57C1918/2918-55
Address Access Time (Max)
Output Enable Time (Max)
35 ns
45 ns
55 ns
20 ns
20 ns
20 ns
2-3
WS57C191B1291B
ABSOLUTE MAXIMUM RATINGS·
*Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ......... - 65°C to + 150°C
Voltage on Any Pin with
Respect to Ground ............. - 0.6V to + 7V
Vpp with Respect to Ground ...... -0.6V to + 14V
ESD Protection ....................... > 2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
Commercial
O°C to +70°C
+5V ± 5%
Industrial
-40°C to +85°C
+5V ± 10%
Military
-55°C to +125°C
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL = 16 mA
V OH
Output High Voltage
IOH = -4 mA
ICCl
Vcc Active Current (CMOS)
Notes 1 and 3
MIN,
MAX
0.4
Comm'l
30
Military
35
Comm'l
40
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
VIN = 5.5V or Gnd
-10
10
ILo
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
inputs: GNO ± O.3V or Vee
2. TTL inputs: V 1L .. O.8V, V 1H " 2.0V.
± O.3V.
3. Add 3
rnA/MHz
V
2.4
Icc2
NOTES: 1. CMOS
UNITS
Military
mA
40
ItA
for A.C power component.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
SYMBOL
57C191 B/291 B-35
MIN
MAX
57C191B/291B-45
MIN
MAX
57C191B/291B-55
MIN
MAX
Address to Output Delay
tACC
35
45
55
CS to Output Delay
tCE
20
20
20
Output Disable to Output Float
tOF
20
20
20
Address to Output Hold
tOH
0
0
UNITS
ns
0
-----------------------~Jri----------------------2-4
WS57C191B1291B
AC READ TIMING DIAGRAM
ADDRESSES
~
--
k-
VALID
.'"1
lAce
~
tes
OUTPUTS
CAPACITANCE(4)
TA = 25°C, f
SYMBOL
--
I--
t OH
/
-
fI
VALID
tOF
I-
1 MHz
PARAMETER
CONDITIONS
Typ(5)
MAX
UNITS
VIN = OV
4
6
pF
CIN
Input Capacitance
COUT
Output Capacitance
VOUT = OV
8
12
pF
CvPp
Vpp Capacitance
Vpp = OV
18
25
pF
NOTES:
4. ThiS parameter is only sampled and is not 100% tested.
5 TYPical values are for T A = 25°C and nominal supply voltages.
TEST LOAQ
(High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0 and 3V
9S0
2.0tv~
D.U.T.~ 30pF
I=
Reference Levels: 1.5V
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
----------------------------~Jr~---------------------------2-5
WS57C191B1291B
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 +
-
5°C, Vee
PARAMETER
= 5.50V +-
5%, Vpp
= 13.5 +-
0.5V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
(V IN = Vee or Gnd)
'l
-10
10
IlA
Vpp Supply Current During
Programming Pulse
Ipp
60
mA
Vee Supply Current
lee
V IL
25
mA
Input Low Level
-0.1
0.8
V
Input High Level
V IH
2.0
Vee + 0.3
V
Output Low Voltage During Verify
(lOL = 16 mAl
VOL
0.45
V
Output High Voltage During Verify
(IOH = -4 mAl
VOH
NOTE:
2.4
6. Vpp must not be greater than 14 volts Including overshoot.
AC CHARACTERISTICS
(TA = 25 -+ 5°C, Vee = 5.50V -+ 5%, Vpp = 13.5 ± 0.5V)
SYMBOLS
MIN
Address Setup Time
PARAMETER
tAS
2
Chip Disable Setup Time
tOF
2
Data Setup Time
tos
Program Pulse Width (Note 7)
TYP
MAX
UNIT
IlS
30
ns
IlS
tpw
1
Data Hold Time
tOH
2
Chip Select Delay
tes
Vpp Rise and Fall Time
tRF
NOTE:
V
3
10
IlS
30
1
ms
ns
IlS
7. For programmers utilizing a one shot programming pulse, a 10 ms pulse width should be used.
PROGRAMMING WAVEFORM
V,H
ADDRESSES
X
- - -....
V'L - - - . . . .
ADDRESS STABLE
,,------------------------
~tAS~
------------------------~Jr;-----------------------2-6
WS57C191B1291B
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C1918-35D
WS57C1918-35J
WS57C1918-35P
WS57C1918-45CM8
WS57C1918-45D
WS57C1918-45DI
WS57C1918-45DM8
WS57C1918-45J
WS57C1918-45P
WS57C1918-55CM8
WS57C1918-55DM8
WS57C2918-35S
WS57C2918-35T
WS57C2918-45S
WS57C2918-45T
WS57C2918-45TI
WS57C2918-45TM8
WS57C2918-55T
WS57C2918-55TM8
35
35
35
45
45
45
45
45
45
55
55
35
35
45
45
45
45
55
55
PACKAGE
TYPE
24
28
24
28
24
24
24
28
24
28
24
24
24
24
24
24
24
24
24
Pin CERDIp, 0.6"
Pin PLDCC
Pin Plastic DIP, 0.6"
Pad CLLCC
Pin CERDIp, 0.6"
Pin CERDIP, 0.6"
Pin CERDIp, 0.6"
Pin PLDCC
Pin Plastic DIP, 0.6"
Pad CLLCC
Pin CERDIP, 0.6"
Pin Plastic DIP, 0.3"
Pin CERDIp, 0.3"
Pin Plastic DIP, 0.3"
Pin CERDIp, 0.3"
Pin CERDIp, 0.3"
Pin CERDIp, 0.3"
Pin CERDIp, 0.3"
Pin CERDIp, 0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
D1
J3
P2
C1
D1
D1
D1
J3
P2
C1
D1
S1
T1
S1
T1
T1
T1
T1
T1
Comm'l
Comm'l
Comm'l
Military
Comm'l
Industrial
Military
Comm'l
Comm'l
Military
Military
Comm'l
Comm'l
Comm'l
Comm'l
Industrial
Military
Comm'l
Military
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
MIL-STD-883C
Standard
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
MIL-STD-883C
-----------------------~Jr;-----------------------2-7
~2-8~-------------------~~;----------------------
---------
5F==~E
---._--
------- ---
WS57C43B
r~'-'-_
~~
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 4K x 8 CMOS PROMIRPROM
KEY FEATURES
• Ultra-Fast Access Time
• Low Power Consumption
• Pin Compatible with AM27S43 and
N82S321 Bipolar PROMs
• Immune to Latch-Up
• Fast Programming
• Available in 300 Mil Dip
-
35 ns
-
up to 200 mA
GENERAL DESCRIPTION
The WS57C43B is an extremely HIGH PERFORMANCE 32K UV Erasable Electrically Re-Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM speeds
while consuming only 25% of the power required by its Bipolar counterparts.
A further advantage of the WS57C43B over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology.
This allows the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike
devices which cannot be erased, every WS57C43B is 100% tested with worst case test patterns both before and
after assembly.
The WS57C43B is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for systems
which are currently using Bipolar PROMs. It also uses the same programming algorithm as its predecessor the
WS57C43.
MODE SELECTION
PIN CONFIGURATION
TOP VIEW
~
CS11
Chip Carrier
CS2
Vcc
OUTPUTS
VIL
V IH
Vee
DouT
VIH
X
Vee
High Z
A4 =~5
A2 :~7
A1 :~8
Ao :]9
MODE
V pp
Read
Output
Disable
Output
Disable
X
VIL
Vee
High Z
Program
V pp
X
Vee
DIN
Program
Verify
V IL
V IH
Vee
DOUT
CERDIP/Plastic DIP
NC
A, A. A; -I-vee A. A.
A3 :,6
A7~
" , " 'I""'"
4-' 3" 2.J~J282726
1
0
25[: A'0
24[: CS1Npp
23~:
A"
22 C: CS,
21 [: NC
20L: 0 7
NC :J10
19 ~- o.
0 0 :J11
12 13 1415161718
rl il fir"] rifi r1
° °.
INC 3 0,
GND
0,0,
..-----. r -
1
A.~2
A,~3
A.[4
A3 ~ 5
A,~ 6
A, ~ 7
Ao[ 8
oo~ 9
0, ~ 10
o~ ~ 11
GND [ 12
~
0
24~Vcc
23~A.
22~A9
21PA,o
20 ~ CS1Npp
19 ~ A"
18 ~ CS,
17 P 0 7
16 ~ o.
15 ~ 0,
14 ~ 0.
13p 0 3
PRODUCT SELECTION GUIDE
PARAMETER
WS57C43B-35
WS57C43B-45
WS57C43B-55
WS57C43B-70
Address Access Time (Max)
35 ns
45 ns
55 ns
70 ns
Output Enable Time (Max)
20 ns
25 ns
25 ns
25 ns
2-9
WS57C43B
ABSOWTE MAXIMUM RATINGS*
·Notice: Stresses above those listed under ''Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to + 150°C
Voltage on Any Pin with
Respect to Ground .............. -0.6V to +7V
V pp with Respect to Ground ....... -0.6V to +14V
ESD Protection ........................ > 2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
0° to +70°C
+5V ± 5%
Industrial
-40° to +85°C
+5V ± 10%
Military
-55° to +125°C
+5V ± 10%
Comm'l
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range. (See Above)
PARAMETER
TEST CONDITIONS
= 16 mA
= -4 mA
VOL
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
ICCl
Vcc Active Current (CMOS)
Notes 1 and 3
Icc2
Vcc Active Current (TIL)
Notes 2 and 3
III
I~put
VIN
ILO
Output Leakage Current
Load Current
PARAMETER
MAX
0.4
UNITS
V
2.4
Comm'l
30
Military
35
Comm'l
40
Military
mA
40
= 5.5V or Gnd
Your = 5.5V or Gnd
NOTES: 1. CMOS inputs: GND ± D.3V or Vee ± D3V.
2 TTL Inputs. V1L " DBV, V1H ;" 2.DV.
AC READ CHARACTERISTICS
MIN
-10
10
-10
10
!!A
3. Add 3 rnA/MHz for A.C. power component.
Over Operating Range. (See Above)
SYMBOL
57C43B-35
MIN
MAX
57C43B-45
57C43B-55
57C43B-70
MIN
MIN
MIN
MAX
MAX
MAX
Address to Output Delay
tACC
35
45
55
70
CS to Output Delay
tcs
20
25
25
25
Output Disable to Output Float
tOF
25
25
25
25
Address to Output Hold
tOH
0
0
0
UNITS
ns
0
-------------------------------~Jr~---------------------------2-10
WS57C43B
AC READ TIMING DIAGRAM
ADDRESSES
~,-..==:-;V.:;~;;LlD-===;j""jj]('-_ _ _ __
-oJ
T.
lACe
•
'-1
IOH
cs --------.."\.1..
_
/
1"---+_../
les
OUTPUTS
VALID
-
CAPACITANCEl4)
IDF
I--
TA = 25°C, f = 1 MHz
SYMBOL
PARAMETER
C IN
Input Capacitance
C OUT
Output Capacitance
C vPp
Vpp Capacitance
CONDITIONS
TYP(5)
MAX
UNITS
= OV
VOUT = OV
V pp = OV
4
6
pF
8
12
pF
18
25
pF
V IN
NOTES:
4. This parameter Is only sampled and is not 100% tested.
5. Typical values are for TA = 250C and nominal supply voltages.
TEST LOAD
(High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0 and
980
2.01V~
D.U.T·~30PF
I-=-
~
Reference Levels: 1.5V
(INCWDING SCOPE
AND JIG
CAPACITANCE)
-----------------------~~i·----------------------2·11
WS57C438
PROGRAMMING INFORMATION
DC CHARACTERISTICS
(TA
= 25
± 5°C, Vee
PARAMETER
= 5.50V
= 13.5
± 5%, Vpp
± 0.5V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
VIN = Vee or Gnd
III
-10
10
~
Vpp Supply Current During
Programming Pulse
Ipp
60
rnA
Vee Supply Current (Notes 2 and 3)
Icc
30
rnA
0.8
V
Input Low Level
VIL
-0.1
Input High Level
V IH
2.0
Output Low Voltage During Verify
(lOL = 16 rnA)
VOL
Output High Voltage During Verify
(lOH = -4 rnA)
VOH
NOTE:
Vee
+ 0.3
V
0.45
V
2.4
V
6. Vpp must not be greater than 14 volts Including overshoot.
AC CHARACTERISTICS
(TA
= 25
PARAMETER
± 5°C, Vee
= 5.5V ±
5%, Vpp
SYMBOLS
MIN
Address Setup Time
tAS
2
Chip Disable Setup Time
tOF
tos
2
Program Pulse Width
tpw
1
2
Data Hold Time
tOH
tes
Vpp Rise and Fall Time
tRF
TYP
± 0.5V)
MAX
UNIT
~s
30
Data Setup Time
Chip Select Delay
= 13.5
ns
~s
3
10
ms
~s
30
ns
1
~
NOTE: A single shot programming algorithm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
VIH---""X
V'L _ _ _-_<. .__
~,~~ ~ ~
'"~
~-----D.'I-:r.-i\-IN-----.....
~l'.
-
.
D_A_:rA_O_U_T_ _
V,H
CSl/V pp
CS.
----------------------------~Jri~------------------2-12
WS57C43B
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C43B-350
WS57C43B-35J
WS57C43B-35S
WS57C43B-35T
WS57C43B-45CMB
WS57C43B-450
WS57C43B-4501
WS57C43B-450MB
WS57C43B-45J
WS57C43B-45S
WS57C43B-45T
WS57C43B-45TI
WS57C43B-45TMB
WS57C43B-45Y
WS57C43B-55CMB
WS57C43B-550
WS57C43B-550MB
WS57C43B-55TI
WS57C43B-55TMB
WS57C43B-55Y
WS57C43B-700
WS57C43B-70TMB
35
35
35
35
45
45
45
45
45
45
45
45
45
45
55
55
55
55
55
55
70
70
PACKAGE
TYPE
24
28
24
24
28
24
24
24
28
24
24
24
24
24
28
24
24
24
24
24
24
24
Pin CEROIp, 0.6"
Pin PLOCC
Pin Plastic DIP, 0.3"
Pin CEROIp, 0.3"
Pad CLLCC
Pin CEROIp, 0.6"
Pin CEROIP, 0.6"
Pin CEROIP, 0.6"
Pin PLOCC
Pin Plastic DIP, 0.3"
Pin CEROIp, 0.3"
Pin CEROIp, 0.3"
Pin CEROIp, 0.3"
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
Pin CEROIp, 0.6"
Pin CEROIP, 0.3"
Pin CEROIP, 0.3"
Pin CEROIp, 0.6"
Pin CEROIp, 0.6"
Pin CEROIp, 0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
01
J3
S1
T1
C1
01
01
01
J3
S1
T1
T1
T1
Y3
C1
01
01
T1
T1
Y3
01
T1
Comm'l
Comm'l
Comm'l
Comm'l
Military
Comm'l
Industrial
Military
Comm'l
Comm'l
Comm'l
Industrial
Military
Comm'l
Military
Comm'l
Military
Industrial
Military
Comm'l
Comm'l
Military
Standard
Standard
Standard
Standard
MIL-STO-883C
Standard
Standard
M IL-STO-883C
Standard
Standard
Standard
Standard
MIL-STO-883C
Standard
MIL-STO-883C
Standard
MIL-STO-883C
Standard
M IL-STO-883C
Standard
Standard
M IL-STO-883C
-------------------------~Jr;.------------------------2-13
fJ
~2_1~4----------------------~Jri------------------------
WS57C43C
ADVANCE INFORMATION
WAFERSCALE INTEGRATION, INC.
x 8 CMOS PROMIRPROM
HIGH SPEED 4K
KEY FEATURES
• Pin Compatible with AM27S43 and
N82S321 Bipolar PROMs
• Immune to Latch-Up
• Ultra-Fast Access Time
-
25 ns
• Low Power Consumption
-
• Fast Programming
up to 200 mA
• Available in 300 Mil Dip
GENERAL DESCRIPTION
The WS57C43C is an extremely HIGH PERFORMANCE 32K UV Erasable Electrically Re-Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM speeds
while consuming only 25% of the power required by its Bipolar counterparts.
A further advantage of the WS57C43C over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology.
This allows the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike
devices which cannot be erased, every WS57C43C is 100% tested with worst case test patterns both before and
after assembly.
The WS57C43C is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for systems
which are currently using Bipolar PROMs. It also uses the same programming algorithm as its predecessor the
WS57C43.
MODE SELECTION
PIN CONFIGURATION
TOP VIEW
~
Chip Carrier
CS11
MODE
V pp
Read
VIL
CS2
Vcc
OUTPUTS
V IH
Vcc
DOUT
Output
Disable
VIH
X
Vcc
High Z
Output
Disable
X
VIL
Vcc
High Z
Program
V pp
X
Vee
DIN
Program
Verify
VIL
V IH
Vee
DouT
NC
A,A. A71vccAsA,
CERDIP/Plastic DIP
A7[~JVcc
A.[2
A,[3
A.[4
A, [ 5
A2 [ 6
I
0, O2 NC 0 3 0.°,
GND
23JAs
22JA,
21JA,o
020
A, [ 7
Ao[8
0o[ 9
0, [ 10
O2 ~ 11
GND [ 12
19
J CS1N pp
J
A"
18 ~ CS2
17J07
16 J o.
15 J 0,
14 ~ 0.
13 J 0 3
PRODUCT SELECTION GUIDE
PARAMETER
WS57C43C-25
WS57C43C-30
Address Access Time (Max)
25 ns
30 ns
Output Enable Time (Max)
15 ns
20 ns
2-15
WS57C43C
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature ........... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .............. -0.6V to +7V
V pp with Respect to Ground ....... -0.6V to +14V
ESD Protection ........................ > 2000V
'Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
0° to +70°C
+5V ± 5%
Industrial
-40° to +85°C
+5V ± 10%
Military
-55° to +125°C
+5V ± 10%
Comm'l
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
TEST CONDITIONS
PARAMETER
= 16 mA
= -4 mA
VOL
Output Low Voltage
IOL
V OH
Output High Voltage
IOH
Icc1
Vcc Active Current (CMOS)
Notes 1 and 3
lec2
Vce Active Current (TTL)
Notes 2 and 3
III
Input Load Current
VIN
ILO
Output Leakage Current
NOTES:
MIN
0.4
UNITS
V
2.4
Comm'l
30
Military
35
Comm'l
40
mA
40
Military
= 5.5V or Gnd
VO UT = 5.5V or Gnd
1. CMOS inputs: GND ± O.3V or Vee ± O.3V.
2. TTL inputs: V1L .;; O.BV, V1H " 2.0V.
MAX
-10
10
-10
10
J.lA
3. Add 3 mAIM Hz for A.C. power component.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
Address to Output Delay
SYMBOL
WS57C43C·25
MIN
MAX
WS57C43C·30
MIN
MAX
tACC·
25
30
CS to Output Delay
tcs
15
20
Output Disable to Output Float
tDF
20
25
Address to Output Hold
tOH
0
UNITS
ns
0
------------------------------------~Ar.=----------------------------------2-16
_,=,JI!JI!f.,
WS57C43C
AC READ TIMING DIAGRAM
ADDRESSES
~
-
VALID
.. '
lACe
10H
J.
/
f.-
les
-
OUTPUTS
CAPACITANCE(4)
SYMBOL
TA
VALID
f.-
1OF
= 25°G, f = 1 MHz
PARAMETER
GIN
Input Capacitance
COUT
Output Capacitance
Cvpp
V pp Capacitance
NOTES:
f.-
CONDITIONS
Typ(5)
MAX
UNITS
= OV
VOUT = OV
V pp = OV
4
6
pF
8
12
pF
18
25
pF
V IN
4. This parameter is only sampled and is not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages.
TEST LOAD (High Impedance Test Systems)
Input Levels: 0 and 3V
98Q
2.0W
TIMING LEVELS
o--V-----!
D.U.T.~ 30pF
I-=-
Reference Levels: 1.5V
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
---------------------
-----------------------~Jr;~.
2-17
WS57C43C
PROGRAMMING INFORMATION
DC CHARACTERISTICS
(TA
= 25 ±
5°C, Vee
PARAMETER
= 5.50V ±
= 13.5 ±
5%, Vpp
0.5V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
VIN = Vee or Gnd
III
-10
10
~A
V pp Supply Current During
Programming Pulse
Ipp
60
mA
30
mA
Vee Supply Current (Notes 2 and 3)
Icc
Input Low Level
V IL
-0.1
0.8
V
Input High Level
V IH
2.0
Vee + 0.3
V
Output Low Voltage During Verify
(lOL = 16 mA)
VOL
0.45
V
Output High Voltage During Verify
(loH = -4 mA)
VOH
2.4
V
NOTE: 6. Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS
(TA
= 25 ±
PARAMETER
5°C, Vee
= 5.5V ±
5%, Vpp
SYMBOLS
MIN
Address Setup Time
tAS
2
Chip Disable Setup Time
tOF
Data Setup Time
tos
2
Program Pulse Width
tpw
1
Data Hold Time
tOH
2
Chip Select Delay
tes
Vpp Rise and Fall Time
tRF
= 13.5 ±
0.5V)
TYP
MAX
UNIT
30
ns
10
ms
30
ns
~s
~s
3
~s
1
~s
NOTE: A single shot programming algorithm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
X
VIH - - -.....
ADDRESSES
V'L _ _ _oJ
DATA :::
ADDRESS STABLE
' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
r-
'AS
~
~
I
DATA
>-<. .__
IN
I'"1
'. ~,J -I'~ - r'~i
'.
CS1N
pp
V,L
---(I
I '
es.
V'L
DA_JA_OU_T_ _
-
Ie.
I-I
/ ~~1"'1'-----'R_
~
'R_
'I
_......c~~~~;::,Q~~~~~~~~~~::.a.~~oQC~~~
_ _ _ _ __
------------------------~Jr;------------------------
2-18
='====
-.............
_
-- ......
-- -
~~
~
--------..
~
~J:::
WS57C45
~
~~
WAFERSCALE INTEGRATION, INC.
HIGH-SPEED 2K
x 8 REGISTERED CMOS PROMIRPROM
KEY FEATURES
• OESC SMO Nos. 5962-88735/5962-87529
• Ultra-Fast Access Time
-
25 ns Setup
12 ns Clock to Output
• Low Power Consumption
• Pin Compatible with AM27S45 and
CY7C245
• Immune to Latch-Up
• Fast Programming
• ESO Protection Exceeds 2000V
• Programmable Synchronous or
Asynchronous Output Enable
• Programmable Asynchronous
Initialize Register
-
fI
up to 200 mA
GENERAL DESCRIPTION
The WS57C45 is an extremely HIGH PERFORMANCE 16K UV Erasable Registered CMOS RPROM. It is a direct
drop·in replacement for such devices as the AM27S45 and CY7C245.
To meet the requirements of systems which execute and fetch instructions simultaneously, an 8-bit parallel data register
has been provided at the output which allows RPROM data to be stored while other data is being addressed.
An asynchronous initialization feature has been provided which enables a user programmable 2049th word to be
placed on the outputs independent of the system clock. This feature can be used to force an initialize word or provide
a preset or clear function.
A further advantage of the WS57C45 over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology.
This enables the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike
devices which cannot be erased, every WS57C45 RPROM is 100% tested with worst case test patterns both before
and after assembly.
PIN CONFIGURATION
TOP VIEW
Chip Carrier
CERDIP/Plastic DIPI
Flatpack
NC
AsA6 A71VccAaAg
A4 =~5
0
~'~'
ci ~J ~~~~k~
1
A, _~6
A2 -~ 7
A, -~ 8
Ao ~ 9
NC :~10
Vee
A,
A,
25~= A,o
24~_
INIT/V pp
20~-
0,
21
23 ~ = OEioEs
22 ~ CPfPGM
21 ~ NC
0 0 ~~11
OffOfs
CPfPGM
0,
0,
19 ~= 0 6
12 13 1415161718
0,0,
A,o
INIT/v pp
0,
0,
I NCO,O,O,
' -_ _- ' 0 ,
GND
PRODUCT SELECTION GUIDE
PARAMETER
WS57C45-45
WS57C45-25
WS57C45-35
Set Up Time (Max)
25 ns
35 ns
45 ns
Clock to Output (Max)
12 ns
15 ns
25 ns
2-19
WS57C45
ABSOLUTE MAXIMUM RATINGS·
'Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to +150°C
Voltage on Any Pin with
Respect to GND ................ -0.6V to +7V
Vpp with Respect to GND ......... -0.6V to +14V
ESD Protection ........................ >2000V
OPERATING RANGE
RANGE
Comm'l
TEMPERATURE
Vcc
0° to +70°C
+5V + 5%
Industrial
-40° to +85°C
+5 + 10%
Military
-55° to +125°C
+5V + 10%
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range. (See Above)
PARAMETER
TEST CONDITIONS
=
=
VOL
VOH
Output Low Voltage
IOL
Output High Voltage
IOH
Icc1
Vcc Active Current (CMOS)
Notes 1 and 3
Icc2
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
ILO
Output Leakage Current
= 5.5V or Gnd
VO UT = 5.5V or Gnd
MIN
16 mA
UNITS
0.4
V
2.4
-4 mA
Comm'l
20
Mili~ary
30
Comm'l
25
Military
VIN
NOTES: 1. CMOS inputs: GND ± 0.3V or Vee ± 0.3V.
2. TIL inputs: VIL " O.BV, VIH ;;. 2.0V.
MAX
mA
35
-10
10
-10
10
J.lA
3. Add 2 mA/MHz for A.C. power component.
4. ThiS parameter is only sampled and IS not 100% tested.
CAPACITANCE(4)
PARAMETERS
TEST CONDITIONS
DESCRIPTION
C IN
Input Capacitance
C OUT
Output Capacitance
AC READ CHARACTERISTICS
PARAMETER
Address Setup to Clock HIGH
TA = 25°C, f
Vcc = 5.0V
MAX
= 1 MHz
Over Operating Range. (See Above)
SYMBOL
WS57C45-25
WS57C45-35
WS57C45-45
MIN
MIN
MIN
MAX
MAX
25
35
45
tHA
0
0
0
Clock Pulse Width
tco
t pwc
15
20
20
OEs Setup to Clock HIGH
tSOEs
12
15
15
tHOEs
5
5
5
Clock HIGH to Valid Output
OEs Hold From Clock HIGH
Delay From INIT to Valid Output
INIT Recovery to Clock HIGH
pF
8
tSA
Address Hold From Clock HIGH
UNITS
5
12
15
20
tDI
MAX
UNITS
25
20
ns
35
tRI
15
20
INIT Pulse Width
tpWI
15
20
20
Active Output From Clock HIGH
t LZC
15
20
30
Inactive 0 ;tput From Clock HIGH
t HZC
15
20
30
Active Output From OE LOW
t LZOE
15
20
30
Inactive Output From OE HIGH
t HzoE
15
20
30
25
------------------------------~JrJr-----------------------------2-20
WS57C45
BLOCK DIAGRAM
INIT -----D~------------___,
ROW
64 x 256
DECODER
PROGRAMMABLE
ARRAY
1 OF 64
1-+-t.:;»O- o.
1-+--[>0--0,
8-BIT
EDGETRIGGERED
REGISTER
COWMN
DECODER
r---------'
1-+--[>0--0.
1-+-1.>0- O.
I-+-t.:>o--O.
1 OF 32
1-+-1.>0- 0,
PROGRAMMABLE
MULTIPLEXER
CP---,.-.............,
TEST LOAD (High Impedance Test Systems)
97.5n
Input Levels: 0 and 3V
2.01V~
D.U.T.
~ 30 pF
I=
TIMING LEVELS
Reference Levels: 0.8 and 2.0V
(INCWDING SCOPE
AND JIG
CAPACITANCE)
AC READ TIMING DIAGRAM
Ao-A,.
OEs
CP
0.-07
ILZOE
OE
INIT
---------------------~~i--------------------2-21
WS57C45
FUNCTIONAL DESCRIPTION
The WS57C45 is an electrically programmable read only memory produced with WSI's patented high-performance
self-aligned split-gate CMOS EPROM technology. It is organized as 2048 x 8 bits and is pin-for-pin compatible with
bipolar TTL fuse link PROMs. The WS57C45 includes aD-type 8-bit data register on-chip which reduces the complexity
and cost of microprogrammed pipelined systems where PROM data is held temporarily in a register. The circuit features
a programmable synchronous (OEs) or asynchronous (OE) output enable and asynchronous initialization (INIT).
The programmed state of the enable pin (OEs or OE) will dictate the state of the outputs at power up. If OEs has
been programmed, the outputs will be in the OFF or high impedance state. If OE has been programmed, the
outputs will be OFF or high impedance only if the OE input is HIGH. Data is read by applying the address to
inputs A1O-AO and a LOW to the enable input. The data is retrieved and loaded into the master section of the 8-bit
data register during the address set-up time. The data is transferred to the slave output of the data register at the
next LOW to HIGH clock (CP) transition. Then the output buffers present the data on the outputs (0 7-0 0),
When using the asynchronous enable (OE), the output buffers may be disabled at any time by switching the enable
input to a logic HIGH. They may be re-enabled by switching the enable to a logic LOW.
When using the synchronous enable (OE s), the outputs revert to a high impedance or OFF state at the next
positive clock edge following the OEs input transition to a HIGH state. The output will revert to the active state
following a positive clock edge when the OEs input is at a LOW state. The address and synchronous enable inputs
are free to change following a positive clock edge since the output will not change until the next low to high clock
transition. This enables accessing the next data location while previously addressed data is present on the outputs.
To avoid race conditions and simplify system timing, the 8-bit edge triggered data register clock is derived directly
from the system clock.
The WS57C45 has an asynchronous initialize input (INIT). This function can be used during power-up and time-out
periods to implement functions such as a start address or initialized bus control word. The INIT input enables the
contents of a 2049th 8-bit word to be loaded directly into the output data register. The INIT input can be used to
load any 8-bit data pattern into the register since each bit is programmable by the user. When unprogrammed, activating
INIT will result in clearing the register (outputs LOW). When all bits are programmed, activating INIT results in
PRESETting the register (outputs HIGH).
When activated LOW, the INIT input results in an immediate load of the 2049th word into both the master and slave
sections of the output register. This is independent of any other input including the clock (CP) input. The initialize
data will be present at the outputs after the asynchronous enable (OE) is taken to a LOW state.
Programming Information
Apply power to the WS57C45 for normal read mode operation with CP/PGM, OEIOE s and INITIVpp at V1H . Then
take INITIVpp to Vpp. The part is then in the program inhibit mode operation and the output lines are in a high
impedance state. Refer to figure 5. As shown in figure 5, address, program and verify one byte of data. Repeat this
sequence for each location to be programmed.
When intelligent programming is used, the program pulse width is 1 ms in length. Each address location is programmed
and verified until it verifies correctly up to and including 5 times. After the location verifies, an additional programming
pulse should be applied that is X1 times in duration of the sum of the previous programming pulses before proceeding
on to the next address and repeating the process.
Initialization Byte Programming
The WS57C45 has a 2049th byte of data that can be used to initialize the value of the data register. This byte contains
the value "0" when it is shipped from the factory. The user must program the 2049th byte with a value other than
"0" for data register initialization if that value is not desired. Except for the following details, the user may program
the 2049th byte in the same manner as the other 2048 bytes. First, since all 2048 addresses are used up, a super
voltage address feature is used to enable an additional address. The actual address includes Vpp on A1 and V1L on
A2 . Refer to the Mode Selection table. The programming and verification of the Initial Byte is accomplished
operationally by performing an initialize function.
-------------------------------~~~------------------------------2-22
--------------
WS57C45
Synchronous Enable Programming
The WS57C45 contains both a synchronous and asynchronous enable feature. The part is delivered configured in
the asynchronous mode and only requires alteration if the synchronous mode is required. This is accomplished by
programming an on-chip EPROM cell. Similar to the Initial Byte, this function is enabled and addressed by using
a super voltage. Referring to the Mode Selection table, Vpp is applied to AI followed by V IH applied to A 2 . This procedure addresses the EPROM cell that programs the synchronous enable feature. The EPROM cell is programmed
with a 10 ms program pulse on CP/PGM. It does not require any data since there is no selection as to how
synchronous enable may be programmed, only if it is to be programmed.
Synchronous Enable Verification
The WS57C45's synchronous enable function is verified operationally. Apply power for read operation with OE/OE s
and INITNpp at V IH and take the clock (CP/PGM) from V IL to V IH . The output data bus should be in a high impedance
state. Next take OE/OE s to VIL . The outputs will remain in the high impedance state. Take the clock (CP/PGM)
from V IL to V IH and the outputs will now contain the data that is present. Take OE/OE s to VIH . The output should
remain driven. Clocking CP/PGM once more from VIL to V IH should place the outputs again in a high impedance state.
Blank Check
Upon delivery from WaferScale Integration, Inc. or after each erasure (see Erasure section), the WS57C45 has all
2048 bytes in the '0' state. "1 's" are loaded into the WS57C45 through the procedure of programming.
MODE SELECTION
MODE
I
I READ OR OUTPUT DISABLE
PIN FUNCTION
A2
CP/PGM
(OE/OEs)IVFY
INITlVpp
Al
OUTPUTS
Read(6)
X
X
VIL
V IH
X
Data Out
Output Disable
Program(S,7)
X
X
V IH
VIH
X
High Z
X
VIL
V IH
Vpp
X
Data In
Program Verify(S,7)
X
V IH
VIL
Vpp
X
Data Out
Program Inhibit(S,7)
X
V IH
V IH
Vpp
X
High Z
Intelligent Program(S,7)
X
VIL
VIH
Vpp
X
Data In
Program Synch Enable(7)
V IH
VIL
VIH
Vpp
Vpp
High Z
Program Initial Byte(7)
VIL
VIL
V IH
Vpp
Vpp
Data In
X
Vpp
V IH
V IL
X
Zeros
Blank Check
NOTES:
S.
= Don't care but not to exceed Vpp .
6 DUring read operation, the output latches are loaded on a "0" to "1" transilion of CPO
7 DUring programming and verlflcallon, all unspecified pins to be at VIL •
x
-----------------------~Jr;----------------------2-23
WS57C45
FIGURE 5. PROM PROGRAMMING WAVEFORMS
PROGRAM
OTHER BYTES
9==
V,H
ADDRESS
V,L
V,H
DATA
V'L
~
Vpp
INITIVpp
V,H
V'L
V,H
CP/PGM
V,L
V,H
(OE/OEs)IVFY
V'L
FIGURE 6. INITIAL BYTE PROGRAMMING WAVEFORMS
V,H
A,
-
V'L
Vpp
V,H
-
A,
----'
V'L
PROGRAM
1...--
I-IR
-~
II
los
V,H
IF
DATA
I-- -- IOH
\I
DATA IN
V'L
Vpp
INITIVpp
V,H
--J
IAH
! - - - IAS -
IFJk-
I-IR
V'L
!--I pw -
V,H
V,L
CP/PGM
l\....-.-..j
FIGURE 7. PROGRAM SYNCHRONOUS ENABLE
V,H
A,
V'L
V,H
V'L
Ipw
V,H
V,L
Vpp
A,
V,H
V'L
Vpp
INIT/Vpp
V,H
IF
V,L
2-24
;'11-:
~
IS
WS57C45
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA
= 25
± 5°C, Vee
PARAMETER
= 5.50V
± 5%, Vpp
= 13.5
± 0.5V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
V IN = Vee or Gnd
III
-10
10
~A
Vpp Supply Current During
Programming Pulse
Ipp
60
mA
Vee Supply Current
lee
25
mA
Input Low Level
V IL
-0.1
0.8
V
Input High Level
V IH
2.0
Vee +0.3
V
Output Low Voltage During Verify
(lOL = 16 mAl
VOL
0.45
V
Output High Voltage During Verify
(lOH = -4 mAl
VOH
2.4
V
NOTE: 8. Vpp must not be greater than 14 volts including overshoot
AC CHARACTERISTICS (TA
PARAMETER
= 25
± 5°C, Vee
=
5.50V ± 5%, Vpp
= 13.5
± 0.5V)
DESCRIPTION
MIN
MAX
UNITS
10
ms
tpw
Programming Pulse Width
0.1
t AS
Address Setup Time
1.0
~s
tos
Data Setup Time
1.0
~s
tAH
Address Hold Time
1.0
~s
tOH
Data Hold Time
1.0
~s
t R , tF
Vpp Rise and Fall Time
1.0
~s
~s
tva
Delay to VFY
1.0
tvp
VFY Pulse Width
2.0
tov
VFY Data Valid
1.0
~s
toz
VFY HIGH to High Z
1.0
~s
~s
_ ________________________________ f§§ . .~-______________________________________
~S!!F~
2-25
WS57C45
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
WS57C45-25T
WS57C45-35CMB
WS57C45-35FMB
WS57C45-35S
WS57C45-35T
WS57C45-35TMB
WS57C45-45KM B
WS57C45-45TM B
SPEED
(ns)
25
35
35
35
35
35
45
45
PACKAGE
TYPE
24
28
24
24
24
24
24
24
Pin CERDIP, 0.3"
pad CLLCC
Pin Ceramic Flatpack
Pin Plastic Dip, 0.3"
Pin CERDIP, 0.3"
Pin CERDIP, 0.3"
Pin CERDIP, 0.3"
Pin CERDIp, 0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
T1
C1
F1
S1
T1
T1
K1
T1
Comm'l
Military
Military
Comm'l
Comm'l
Military
Military
Military
Standard
MIL-STD-883C
MIL-STO-883C
Standard
Standard
MIL-STO-883C
MIL-STD-883C
MIL-STO-883C
------------------------------~JrJr.-----------------------------2-26
--...
..iF=====~
_---
. .- -i-= -==
---.:. . ...
WS57C49B
~~
WAFERSCALE INTEGRATION, INC.
HIGH SPEED BK x B CMOS PROMIRPROM
KEY FEATURES
• Pin Compatible with AM27S49 and
MB7144 Bipolar PROMs
• Immune to Latch-Up
• Ultra-Fast Access Time
-
35 ns
• Low Power Consumption
• Fast Programming
• DESC SMD 5962-87515
-
up to 200 rnA
• ESD Protection Exceeds 2000V
GENERAL DESCRIPTION
The WS57C49B is an extremely HIGH PERFORMANCE 64K UV Erasable Electrically Re-Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM speeds
while consuming only 25% of the power required by its Bipolar counterparts.
A further advantage of the WS57C49B over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology.
This allows the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike
devices which cannot be erased, every WS57C49B is 100% tested with worst case test patterns both before and
after assembly.
A unique feature of the WS57C49B is a designed-in output hold from address change. This allows the WS57C49B
to be run at a cycle time equal to the address access time. While addresses are changing, output data is held long
enough to be latched into external circuitry.
The WS57C49B is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for systems
which are currently using Bipolar PROMs.
MODE SELECTION
PIN CONFIGURATION
TOP VIEW
Chip Carrier
~
MODE
Read
CS1/v pp
Vce
CERDIP!Plastie DIP!
Flatpaek
NC
OUTPUTS
---"' r - -
As As A71VCCASAg
VIL
Vee
DouT
Output
Disable
V IH
Vee
High Z
Program
Vpp
Vee
DIN
Program
Verify
V IL
Vee
DOUT
~J ~J ~J LJ ~~~~~~
A,
A3
A,
A,
Ao
NC
00
1
:,5
:;6
=~ 7
:;8
=19
:J 10
=~ 11
25 C:
24,:
23
22,:
21 ,:
20
A"
A12
NC
07
19 ~=
o.
[=
0
c:
A,o
CS1IV pp
1213 14151617 18
ili;i-:il~-:iiii
A7 [1
~ 24 J Vee
A.[2
23JA,
As [ 3
22 J A.
A4 ~ 4
21 ~ AlO
A3 ~ 5 0 2 0 J CS1IV pp
A,[ 6
19 JA"
A, [ 7
18 J A12
Ao[8
17J07
00 ~ 9
16 ~ o.
0, [ 10
15 J Os
0, [ 11
14 20,
GND [ 12
13 0 3
P
I
0, O2 NC 0 30, Os
GND
PRODUCT SELECTION GUIDE
PARAMETER
WS57C49B-35
WS57C49B-45
WS57C49B-55
WS57C49B-70
Address Access Time (Max)
35 ns
45 ns
55 ns
70 ns
Output Enable Time (Max)
20 ns
25 ns
25 ns
25 ns
2-27
WS57C49B
ABSOLUTE MAXIMUM RATINGS·
-Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to + 150°C
Voltage on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
ESD Protection ........................ > 2000V
OPERATING RANGE
RANGE
Comm'l
TEMPERATURE
Vcc
0° to +70°C
+5V
Industrial
-40° to +85°C
+5V
Military
-55° to +125°C
+5V
± 5%
± 10%
± 10%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
PARAMETER
TEST CONDITIONS
=
=
VOL
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
Icc1
Vcc Active Current (CMOS)
Notes 1 and 3
UNITS
V
2.4
-4 mA
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
ILO
Output Leakage Current
= 5.5V or Gnd
VOUT = 5.5V or Gnd
Comm'l
30
Military
35
Comm'l
40
Military
3. Add 3 rnA/MHz for
A.C.
mA
40
VIN
1. CMOS inputs: GND ± O.3V or Vee ± O.3V.
2. TTL inputs: V 1L " O.BV, V1H " 2.0V.
MAX
0.4
Icc2
NOTES:
MIN
16 mA
-10
10
-10
10
i!A
power component.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
SYMBOL
57C49B·35
MIN
MAX
57C49B·45
57C49B·55
57C49B·70
MIN
MIN
MIN
MAX
MAX
MAX
Address to Output Delay
tACC
35
45
55
70
CS to Output Delay
tcs
20
25
25
25
Output Disable to Output Float
tDF
25
25
25
25
Address to Output Hold
tOH
0
0
0
UNITS
ns
0
--------------------------~Jr;------------------------2-28
WS57C49B
AC READ TIMING DIAGRAM
ADDRESSES
~
-
VALID
.'
lACe
I--
10H
'\l
/
Ie.
OUTPUTS
"-"-
fJ
I--
-
VALID
IDF
I-
CAPACITANce4 ) TA = 25°C, f = 1 MHz
SYMBOL
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
C vPp
V pp Capacitance
NOTES:
CONDITIONS
TYP(5)
MAX
UNITS
VIN = OV
4
6
pF
VOUT = OV
8
12
pF
V pp = OV
18
25
pF
4. This parameter IS only sampled and is not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages.
TEST WAD (High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0 and 3V
980
2.01V~
D.U.T.~ 30pF
I-=-
Reference Levels: 1.5V
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
-----------------------~Jri----------------------2-29
WS57C498
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.50V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
V IN = Vee or Gnd
III
-10
10
IlA
Vpp Supply Current During
Programming Pulse
Ipp
60
mA
35
mA
0.8
V
Vee Supply Current
lee
Input Low Level
VIL
-0.1
2.0
Input High Level
V IH
Output Low Voltage During Verify
(lOL = 16 mAl
VOL
Output High Voltage During Verify
(lOH = -4 mAl
V OH
Vee
+ 0.3
V
0.45
V
2.4
V
NOTE: 6 Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
SYMBOLS
MIN
Address Setup Time
PARAMETER
tAS
2
Chip Disable Setup Time
tOF
Data Setup Time
tos
Program Pulse Width
TYP
MAX
UNIT
IlS
30
ns
2
tpw
1
Data Hold Time
tOH
2
Chip Select Delay
tes
Vpp Rise and Fall Time
tRF
IlS
3
10
ms
Ils
30
ns
1
flS
NOTE: A single shot programming algorithm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
X
V IH - - -......
ADDRESSES
V'L _ _ _oJ
ADDRESS STABLE
' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~ IAS-1
DATA :::
»--O«
~-----D-A1:-'A-IN-----......
'OOl
DATA OUT
~~
Vpp
----------------------~~;.----------------------2·30
WS57C49B
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C49B·35D
WS57C49B·35J
WS57C49B·35P
WS57C49B·35T
WS57C49B·45CMB
WS57C49B·45D
WS57C49B-45DI
WS57C49B·45DMB
WS57C49B·45J
WS57C49B·45P
WS57C49B·45S
WS57C49B·45T
WS57C49B·45TI
WS57C49B·45TMB
WS57C49B·55CMB
WS57C49B·55D
WS57C49B·55DMB
WS57C49B·55FMB
WS57C49B·55T
WS57C49B·55TMB
WS57C49B·70CMB
WS57C49B·70D
WS57C49B·70DMB
WS57C49B·70T
WS57C49B·7OTMB
35
35
35
35
45
45
45
45
45
45
45
45
45
45
55
55
55
55
55
55
70
70
70
70
70
PACKAGE
TYPE
24
28
24
24
28
24
24
24
28
24
24
24
24
24
28
24
24
24
24
24
28
24
24
24
24
Pin CERDIp, 0.6"
Pin PLDCC
Pin Plastic DIP, 0.6"
Pin CERDIp, 0.3"
Pad CLLCC
Pin CERDIp, 0.6"
Pin CERDIP, 0.6"
Pin CERDIP, 0.6"
Pin PLDCC
Pin Plastic DIP, 0.6"
Pin Plastic DIP, 0.3"
Pin CERDIp, 0.3"
Pin CERDIp, 0.3"
Pin CERDIp, 0.3"
Pad CLLCC
Pin CERDIp, 0.6"
Pin CERDIp, 0.6"
Pin Ceramic Flatpack
Pin CERDIP, 0.3"
Pin CERDIp, 0.3"
Pad CLLCC
Pin CERDIp, 0.6"
Pin CERDIP, 0.6"
Pin CERDIP, 0.3"
Pin CERDIp, 0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
D1
J3
P2
T1
C1
D1
D1
D1
J3
P2
S1
T1
T1
T1
C1
D1
D1
F1
T1
T1
C1
D1
D1
T1
T1
Comm'l
Comm'l
Comm'l
Comm'l
Military
Comm'l
Industrial
Military
Comm'l
Comm'l
Comm'l
Comm'l
Industrial
Military
Military
Comm'l
Military
Military
Comm'l
Military
Military
Comm'l
Military
Comm'l
Military
Standard
Standard
Standard
Standard
MIL·STD·883C
Standard
Standard
MIL·STD·883C
Standard
Standard
Standard
Standard
Standard
M IL·STD·883C
STD·M IL·883C
Standard
MIL·STD·883C
MIL·STD·883C
Standard
MIL·STD·883C
MIL·STD·883C
Standard
MIL·STD·883C
Standard
MIL·STD·883C
~.......
-----------------------------',~~.----------------------------2·31
·2---3--2------------------------------------------.. ~~~-------------------------------------------------
_-
- - ===~
--..~ =: == ........
---- -.-..-.....
r
......
~
WS57C49C
~~_
ADVANCE INFORMATION
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 8K x 8 CMOS PROMIRPROM
KEY FEATURES
• Ultra-Fast Access Time
-
• Pin Compatible with AM27S49 and
MB7144 Bipolar PROMs
25 ns
• Low Power Consumption
• Immune to Latch-Up
• Fast Programming
-
up to 200 mA
• ESD Protection Exceeds 2000V
• DESC SMD 5962-87515
GENERAL DESCRIPTION
The WS57C49C is an extremely HIGH PERFORMANCE 64K UV Erasable Electrically Re-Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM speeds
while consuming only 25% of the power required by its Bipolar counterparts.
A further advantage of the WS57C49C over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology.
This allows the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike
devices which cannot be erased, every WS57C49C is 100% tested with worst case test patterns both before and
after assembly.
A unique feature of the WS57C49C is a designed-in output hold from address change. This allows the WS57C49C
to be run at a cycle time equal to the address access time. While addresses are changing, output data is held long
enough to be latched into external circuitry.
The WS57C49C is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for systems
which are currently using Bipolar PROMs.
PIN CONFIGURATION
MODE SELECTION
TOP VIEW
~
Chip Carrier
CS1/v pp
Vcc
OUTPUTS
Read
VIL
Vce
DouT
Output
Disable
V IH
Vee
High Z
Program
V pp
Vee
DIN
Program
Verify
VIL
Vee
DouT
MODE
NC
CERDIP!Plastic DIP!
Flatpack
I
As A, A7 Vee As A.
0 0 =~ 11
19 ~= 0 6
12131415161718
0,°2
I NC 0,0. Os
GND
PRODUCT SELECTION GUIDE
PARAMETER
WS57C49C-25
WS57C49C-30
Address Access Time (Max)
25 ns
30 ns
Output Enable Time (Max)
15 ns
20 ns
2-33
WS57C49C
ABSOWTE MAXIMUM RATINGS*
"Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to +150 0 C
Voltage on Any Pin with
Respect to Ground .............. -0.6V to +7V
V pp with Respect to Ground ....... -0.6V to +14V
ESD Protection ........................ > 2000V
OPERATING RANGE
RANGE
Comm'l
TEMPERATURE
Vcc
0° to +70°C
+5V
Industrial
-40° to +85°C
+5V
Military
-55° to +125°C
+5V
± 5%
± 10%
± 10%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL = 16 mA
VOH
Output High Voltage
IOH = -4 mA
Icc1
Vcc Active Current (CMOS)
Notes 1 and 3
MAX
MIN
0.4
Comm'l
30
Military
35
Comm'l
40
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
V1N = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
NOTES:
1. CMOS inputs: GND ± O.3V or Vee
2. TTL inputs: V,L '" O.BV, V ,H ;. 2.0V.
O.3V.
V
2.4
Icc2
±
UNITS
mA
40
Military
~A
3. Add 3 mAIM Hz for A.C. power component.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
WS57C49C·25
PARAMETER
SYMBOL
MIN
MAX
WS57C49C·30
MIN
MAX
25
30
tcs
15
20
tDF
20
25
Address to Output Delay
tACC
CS to Output Delay
Output Disable to Output Float
Address to Output Hold
tOH
0
UNITS
ns
0
_ __________________________________ FEI=E___________________________________
2-34
~,5F.
WS57C49C
AC READ TIMING DIAGRAM
ADDRESSES
~_
VALID
.,'
tACe
CS
"l
-
tes
OUTPUTS
CAPACITANCE<4)
SYMBOL
TA
f--
tOH
/
-
VALID
tOF
j.-
= 25°C. f = 1 MHz
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
C vPp
Vpp Capacitance
NOTES:
~
CONDITIONS
VIN
VOUT
Vpp
= OV
= OV
= OV
Typ(5)
MAX
UNITS
4
6
pF
8
12
pF
18
25
pF
4 This parameter IS only sampled and IS not 100% tested
5 Typical values are for TA = 25°C and nominal supply voltages.
TEST WAD
(High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0 and 3V
98Q
2.0Wo--V---l
D.U.T·~30PF
I-=-
Reference Levels: 1.5V
(INCWDING SCOPE
AND JIG
CAPACITANCE)
---------------------~Jr;~------------------2-35
WS57C49C
PROGRAMMING INFORMATION
DC CHARACTERISTICS
(TA
= 25 ±
5°C, Vee
= 5.50V ±
= 13.5 ± 0.5V)
5%, Vpp
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
VIN = Vee or Gnd
III
-10
10
J.LA
Vpp Supply Current During
Programming Pulse
Ipp
60
rnA
Vee Supply Current
lee
35
rnA
Input Low Level
V IL
-0.1
0.8
V
2.0
Vee + 0.3
V
0.45
V
PARAMETER
Input High Level
V IH
Output Low Voltage During Verify
(lOL = 16 rnA)
VOL
Output High Voltage During Verify
(loH = -4 rnA)
VOH
V
2.4
NOTE: 6. Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS
(TA
= 25 ±
5°C, Vee
= 5.5V ±
5%, Vpp
SYMBOLS
MIN
Address Setup Time
tAS
2
Chip Disable Setup Time
tOF
Data Setup Time
tos
2
Program Pulse Width
tpw
1
Data Hold Time
tOH
2
PARAMETER
Chip Select Delay
= 13.5 ±
TYP
tRF
MAX
UNIT
J.ls
30
ns
10
ms
J.lS
3
J.lS
30
tes
Vpp Rise and Fall Time
0.5V)
ns
1
J.lS
PROGRAMMING WAVEFORM
VIH
ADDRESSES
X
---"
V,L - - - - '
DATA :::
ADDRESS STABLE
'-------------------------
~tAs1
>_<'"__
~-----D-At-'A-IN-----....
' "1
vpp
='~~~=
D_A_:rA_O_U_T_ _
~~
---------------------------------~.".-------------------------------2-36
WS57C51B
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 16K
x 8 CMOS PROMIRPROM
KEY FEATURES
• Pin Compatible with AM27S51
• Ultra-Fast Access Time
-
40 ns
fJ
• Immune to Latch-Up
• Low Power Consumption
-
• Fast Programming
up to 200 mA
• ESO Protection Exceeds 2000V
GENERAL DESCRIPTION
The WS57C51B is a High Performance 128K UV Erasable Electrically Re-Programmable Read Only Memory. It is
manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM speeds while consuming
only 25% of the power required by its Bipolar counterparts.
A further advantage of the WS57C51 B over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology.
This allows the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike
devices which cannot be erased, every WS57C51B is 100% tested with worst case test patterns both before and after
assembly.
The WS57C51B provides a low power alternative to those designs which are committed to a bipolar PROM footprint.
It is a direct drop-in replacement for a bipolar PROM of the same architecture (16K x 8). No software, hardware or
layout changes need be performed.
PIN CONFIGURATION
MODE SELECTION
MODE
~
eSll
Vpp
eS2
eS3
eS4
Vee
OUTPUTS
Read
V IL
V IL
V IH
V IL
Vcc
DOUT
Output
Disable
V IH
X
X
X
Vee
High Z
Output
Disable
X
V IH
X
X
Vee
High Z
Output
Disable
X
X
V IL
X
Vee
High Z
Output
Disable
X
X
X
V IH
Vee
High Z
Program
Vpp
X
X
X
Vee
DIN
Program
Verify
V IL
V IL
V IH
V IL
Vee
DOUT
TOP VIEW
CERDIP
Chip Carrier
Vee
A6 A7 AaAg I A10 A11
U:"';~J:
As
A,
A,
A2
A,
Ao
NC
Qo
Q,
A9~~~Vee
:~JLJLJ
432""323130
1
:J 5
29,: A12
A"
=~ 7
27
CS1/v pp
=~ 8
26 [= CS2
=i 9
25 C= CS3
:J10
24[: CS4
:J 11
23,: NC
=J 12
22 C= Q7
:J 13
21,: Q,
14151617181920
.. ,,... ... ,-,,...,,...,,.,,... ....
"0'"
I'I
II
"
I'"
c:
I"
I
Q2NC Q,NCQ,Q.
GND
A. [ 2
27 ~ A,o
A7 [ 3
26 ~ A"
A, [ 4
25 ~ A12
As ~ 5
24 ~ A13
A, [ 6 0 2 3 ] CS1/v pp
A,[7
22]CS2
21 ]CS3
A2 [ 8
A,~ 9
20 ~CS4
Ao ~ 10
19 ] 0 7
0o[ 11
18 ] 0,
0, [ 12
17 ] 0.
02 ~ 13
16 ~ 0,
GND [ 14
15 ] 0,
PRODUCT SELECTION GUIDE
PARAMETER
WS57C518-40
WS57C518·45
WS57C518-55
WS57C518·70
Address Access Time (Max)
40 ns
45 ns
55 ns
70 ns
Output Enable Time (Max)
20 ns
20 ns
25 ns
30 ns
2-37
WS57C518
ABSOLUTE MAXIMUM RATINGS·
'Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to + 150°C
Voltage on Any Pin with
Respect to Ground .............. -0.6V to + 7V
V pp with Respect to Ground ....... -0.6V to +14V
ESD Protection ........................ > 2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
0° to +70°C
+5V ± 5%
Industrial
-40° to +85°C
+5V ± 10%
Military
-55° to +125°C
+5V ± 10%
Comm'l
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
PARAMETER
TEST CONDITIONS
= 16 mA
= -4 mA
VOL
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
Icc1
Vcc Active Current (CMOS)
Notes 1 and 3
Icc2
Vcc Active Current (TTL)
Notes 2 and 3
=
III
Input Load Current
Y,N
ILO
Output Leakage Current
VOUT
inputs: GND ± O.3V or Vee
2. TTL Inputs: V,L .;; O.BV, V,H '" 2.0v.
NOTES: 1. CMOS
±
O.3V.
MIN
3.
0.4
Add
UNITS
V
2.4
30
35
40
40
Comm'l
Military
Comm'l
Military
5.5V or Gnd
=
MAX
5.5V or Gnd
3 rnA/MHz
for
A.C.
Note
3
mA
Note
3
-10
10
-10
10
J.lA
power component.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
SYMBOL
WS57C51B-40 WS57C51B-45 WS57C51B-55 WS57C51B-70
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Address to Output Delay
tACC
40
45
55
70
CS to Output Delay
tcs
20
20
25
30
Output Disable to
Output Float
tOF
20
20
25
25
Address to Output Hold
tOH
UNITS
ns
0
0
iI_.-.iE
0
0
------------------------------------~sr6·-----------------------------------2-38
WS57C51B
AC READ TIMING DIAGRAM
ADDRESSES
~_
VALID
CS
'\.l
-
OUTPUTS
TA
SYMBOL
PARAMETER
C OUT
Output Capacitance
CvPP
Vpp Capacitance
NOTES:
VALID
t D•
f.-
= 25°C, f = 1 MHz
Input Capacitance
CIN
tOH
/
les
CAPACITANCEl4)
=f ---
.'
tACC
CONDITIONS
TYP(S)
MAX
VIN = OV
VO UT = OV
Vpp = OV
4
6
pF
8
12
pF
18
25
pF
UNITS
4. This parameter IS only sampled and is not 100% tested.
5 Typical values are for TA = 25°C and nominal supply voltages.
TEST LOAD
(High Impedance Test Systems)
98Q
TIMING LEVELS
Input Levels: 0 and 3V
2.01V~
D.U.T·~30PF
I-=-
Reference Levels: 1.5V
(INCWDING SCOPE
AND JIG
CAPACITANCE)
----------------------------~Jr~--------------------------2---39
WS57C51B
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA
= 25
± 5°C, Vee = 5.50V ± 5%, Vpp = 13.5 ± 0.5V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
V IN = Vee or Gnd
PARAMETER
III
-10
10
J.lA
Vpp Supply Current During
Programming Pulse
Ipp
60
mA
Vee Supply Current
lee
25
mA
Input Low Level
V IL
-0.1
0.8
V
Input High Level
V IH
2.0
Vee + 0.3
V
Output Low Voltage During Verify
(lOL = 16 mAl
VOL
0.45
V
Output High Voltage During Verify
(lOH = -4 mAl
VOH
2.4
V
NOTE: 6. Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA
= 25
PARAMETER
± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
SYMBOLS
MIN
Address Setup Time
tAS
2
Chip Disable Setup Time
tDF
Data Setup Time
tDS
Program Pulse Width (Note 7)
tpw
1
Data Hold Time
tDH
2
Chip Select Delay
tes
Vpp Rise and Fall Time
tRF
TYP
MAX
UNIT
J.ls
30
ns
2
J.ls
3
10
ms
J.ls
30
ns
1
J.lS
NOTE: 7. A single shot programming algorithm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
X
V IH - - - - . .
ADDRESSES
VIL _ _ _J
ADDRESS STABLE
....- - - - - - - - - - - - - - - - - - - - - - - -
~tAs1
DATA
VIH~
VIL~
DATA
IN
>----<"". .__
D_A_TA_O_U_T_ _
~l
,.~
Vpp
----------------------------------~~~----------------------------------2-40
WS57C51B
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C51 B-40D
WS57C51B-40L
WS57C51B-40T
WS57C51 B-45D
WS57C51B-45DMB
WS57C51B-45L
WS57C51 B-45T
WS57C51B-55CMB
WS57C51B-55D
WS57C51 B-55DMB
WS57C51 B-55LM B
WS57C51B-55T
WS57C51 B-55TMB
WS57C51 B-70CM B
WS57C51 B-70D
WS57C51 B-70DM B
WS57C51 B-70LMB
WS57C51 B-70T
40
40
40
45
45
45
45
55
55
55
55
55
55
70
70
70
70
70
PACKAGE
TYPE
28
32
28
28
28
32
28
32
28
28
32
28
28
32
28
28
32
28
Pin CERDIP,
Pin CLDCC
Pin CERDIP,
Pin CERDIp,
Pin CERDIP,
Pin CLDCC
Pin CERDIP,
Pad CLLCC
Pin CERDIP,
Pin CERDIP,
Pin CLDCC
Pin CERDIP,
Pin CERDIP,
Pad CLLCC
Pin CERDIP,
Pin CERDIP,
Pin CLDCC
Pin CERDIP,
0.6"
0.3"
0.6"
0.6"
0.3"
0.6"
0.6"
0.3"
0.3"
0.6"
0.6"
0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
D2
L3
T2
D2
D2
L3
T2
C2
D2
D2
L3
T2
T2
C2
D2
D2
L3
T2
Comm'l
Comm'l
Comm'l
Comm'l
Military
Comm'l
Comm'l
Military
Comm'l
Military
Military
Comm'l
Military
Military
Comm'l
Military
Military
Comm'l
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
MIL-STD-883C
MIL-STD-883C
Standard
MIL-STD-883C
MIL-STD-883C
Standard
MIL-STD-883C
MIL-STD-883C
Standard
"'lEa
----------------------------------rJrjfjP~---------------------------------2-41
:2~-4~2:--------------------------------------------~~~------------------------------------------------
===,:~
-----==
----------~
WS57C71C
r ~ ~JJ=:
~~
PRELIMINARY
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 32K x 8 CMOS RPROM
KEY FEATURES
• Immune to Latch-Up
• Ultra-Fast Access Time
-
-
40 ns
• Low Power Consumption
• Fast Programming
up to 200 mA
• ESD Protection Exceeds 2000V
GENERAL DESCRIPTION
The WS57C71C is an extremely High-Performance 256K UV erasable electrically Re-Programmable Read Only
~emory (RPROM). It is manufactured in an advanced CMOS technology and utilizes WSl's patented self-aligned
split gate EPROM cell (see WSI Technical Brief 001).
The WS57C71C was developed for High-Performance Embedded Control applications. Its very high speed enables
it to run at full speed with embedded processors such as the TMS320XX, 80960, M56/96000, etc.
The industry standard RPROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8
device as well as providing an upgrade path to 64K x 8 and 128K x 8 devices.
The WS57C71C utilizes WSI's patented split gate EPROM cell. This technology enables WSI to manufacture high
density low power CMOS EPROMs that operate at the high speed of bipolar PROMs.
For further information on WSI products, contact the nearest WSI sales office, sales representative, or call WSI at
800:fEAM-WSI (832-6974).
PIN CONFIGURATION
MODE SELECTION
TOP VIEW
~
MODE
VIL
V IH
VIL
Vee
DouT
Output Disable
VIH
X
X
Vee
High Z
Output Disable
X
VIL
X
Vee
High Z
X
X
VIH
Vee
High Z
Program
Vpp
X
VIH
Vee
DIN
Program Verify
VIL
V IH
V IL
Vee
DOUT
X
V IL
Vee
High Z
Program Inhibit Vpp
~
r--
eo
CD
8
~
CERDIP
:::
2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
Commercial
OOC to +70°C
+5V ± 5%
Industrial
-40°C to +85°C
+5V ± 10%
Military
-55°C to +125°C
+5V + 10%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
TEST CONDITIONS
PARAMETER
= 16 mA
= -4 mA
VOL
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
V 1L
Input Low Voltage
V 1H
Input High Voltage
Icc
Vcc Active Current
Note 3
III
Input Load Current
V 1N
ILO
Output Leakage Current
VOUT
NOTES:
MAX
MIN
0.4
0.8
1. CMOS inputs: GND ± O.3V or Vee ± O.3V
2. TTL Inputs: V'L .;; a.BV, V'H ;. 2.aV.
I
I
Comm'l
Military
5.5V or Gnd
=
V
2.4
2.0
=
UNITS
5.5V or Gnd
30
40
I
I
Note
3
-10
10
-10
10
V
mA
,.A
3. Add 2 mA/MHz for A.C. power component.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
Address to Output Delay
SYMBOL
57C71C-40
MIN
MAX
57C71C-45
MIN
MAX
57C71C-55
MIN
MAX
tACC
40
45
55
CS to Output Delay
tcs
20
20
20
Output Disable to
Output Float
tOF
20
20
20
Address to Output Hold
tOH
UNITS
ns
0
0
0
----------------------------~Jr~---------------------------2·44
--
~-
----
-~~
WS57C71C
AC READ TIMING DIAGRAM
ADDRESSES
~
--
VALID
..,'
t Ace
'\L
/
tes
OUTPUTS
CAPAC/TANCE(4) TA
SYMBOL
f+-
tOH
'"'"
fJ
i--
-
VALID
/
tOF
i-
= 25°C, f = 1 MHz
PARAMETER
C IN
Input Capacitance
C OUT
Output Capacitance
CvPp
Vpp Capacitance
CONDITIONS
VIN
VOUT
Vpp
= OV
= OV
= OV
TYP(S)
MAX
UNITS
4
6
pF
8
12
pF
18
25
pF
NOTES:
4. This parameter IS only sampled and IS not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages
TEST LOAD (High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0 and 3V
9Sg
2.01V~
Reference Levels: 1.5V
D.U.T.~ 30pF
I-=-
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
i!~~~E
-------------------------------------~.;r.------------------------------------2-45
WS57C71C
PROGRAMMING INFORMATION
DC CHARACTERISTICS
(TA
= 25
± 5°C, Vee
= 5.50V
± 5%, Vpp
= 12.5
± 0.5V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
V IN = Vee or Gnd
III
-10
10
J,lA
Vpp Supply Current During
Programming Pulse
Ipp
60
mA
PARAMETER
Vee Supply Current
lee
25
mA
Input Low Level
V IL
-0.1
0.8
V
Input High Level
V IH
2.0
Vee + 0.3
V
Output Low Voltage During Verify
(IOL = 16 mA)
VOL
0.45
V
Output High Voltage During Verify
(loH = -4 mA)
VOH
NOTE:
2.4
V
6. Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS
(TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 12.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN
Address Setup Time
tAS
2
Chip Disable Setup Time
tOF
Data Setup Time
tos
2
Program Pulse Width
tpw
1
Data Hold Time
tOH
2
Chip Select Delay
tes
Vpp Rise and Fall Time
tRF
TYP
MAX
UNIT
J,ls
30
ns
10
ms
J,ls
3
J,ls
30
1
ns
J.lS
PROGRAMMING WAVEFORM
______~)x(~______~---------A-D-DR-E-SS--~-A-BL-E----------------------
ADDRESSES
r- --1
IAS
VIH~
I
DMAIN
~~____DA_n__ou_T___
VIL
vpp
CS2
-1
+~--_-_- - - - - l
los I....
10H-/
ICS~
DON"i'CARE
---------------------~Jr;--------------------2-46
WS57C71C
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C71C-400*
WS57C71C-40L *
WS57C71 C-40T *
WS57C71C-45D
WS57C71C-45L
WS57C71C-45T
WS57C71C-55CM
WS57C71C-55CMB
WS57C71C-55D
WS57C71C-55DM
WS57C71C-55DMB
WS57C71C-55L
WS57C71C-55LM
WS57C71C-55LMB
WS57C71C-55T
WS57C71 C-55TM
WS57C71C-55TMB
40
40
40
45
45
45
55
55
55
55
55
55
55
55
55
55
55
PACKAGE
TYPE
28
32
28
28
32
28
32
32
28
28
28
32
32
32
28
28
28
Pin CEROIP,
Pin CLDCC
Pin CERDIP,
Pin CERDIp,
Pin CLDCC
Pin CERDIP,
Pad CLLCC
Pad CLLCC
Pin CERDIp,
Pin CERDIP,
Pin CERDIp,
Pin CLDCC
Pin CLDCC
Pin CLDCC
Pin CERDIp,
Pin CERDIP,
Pin CERDIp,
0.6"
0.3"
0.6"
0.3"
0.6"
0.6"
0.6"
0.3"
0.3"
0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
02
L3
T2
D2
L3
T2
C2
C2
D2
D2
D2
L3
L3
L3
T2
T2
T2
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Military
Military
Comm'l
Military
Military
Comm'l
Military
Military
Comm'l
Military
Military
Standard
Standard
Standard
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
*These products are Advance Information
="'-------------------------------------~~~--------------------------------
2-47
~2-4=8----------------------~Jr;------------------------
... -----.,-------- .....
..... -- =' . , . ,
J:IIE:
-
~
I'~~~-
~
WAFERSCALE INTEGRATION, INC.
EPROM MEMORY PRODUCTS
3
SECTION INDEX
EPROM MEMORY PRODUCTS
64K EPROM Selection Guide ........................................................ 3-1
WS27C64F
Military 8K x 8 CMOS EPROM ......................................... 3-3
WS27C64L
8K x 8 CMOS EPROM ................................................ 3-9
WS57C64F
High Speed 8K x 8 CMOS EPROM ..................................... 3-15
WS57C65
High Speed 4K x 16 CMOS EPROM .................................... 3-21
128K EPROM Selection Guide ...................................................... 3-27
WS27C128F
Military 16K x 8 CMOS EPROM ....................................... 3-29
WS27C128L
16K x 8 CMOS EPROM .............................................. 3-35
WS57C128F
High Speed 16K x 8 CMOS EPROM .................................... 3-41
256K EPROM Selection Guide ...................................................... 3-47
WS27C256F
High Speed 32K x 8 CMOS EPROM ................................... 3-49
WS27C256L
32K x 8 CMOS EPROM .............................................. 3-55
WS57C256F
High Speed 32K x 8 CMOS EPROM
WS57C257
High Speed 16K x 16 CMOS EPROM ................................... 3-67
...
. ... 3-61
512K EPROM Selection Guide ...................................................... 3-73
WS27C512F
High Speed 64K x 8 CMOS EPROM .................................... 3-75
WS57C512F
High Speed 64K x 8 CMOS EPROM ................................... 3-81
WS27C512L
64K x 8 CMOS EPROM .............................................. 3-85
1 Meg EPROM Selection Guide . .................................................... 3-91
WS27C010L
128K x 8 CMOS EPROM ............................................. 3-93
WS57C010M
1 Meg (128K x 8) CMOS EPROM Module ............................... 3-99
WS27C010F
1 Meg (128K x 8) CMOS EPROM ..................................... 3-105
WS27C210L
1 Meg (64K x 16) CMOS EPROM ..................................... 3-109
WS57C210M
1 Meg (64K x 16) CMOS EPROM Module ............................... 3-115
WS27C210F
1 Meg (64K x 16) CMOS EPROM ..................................... 3-121
2 Meg EPROM Selection Guide . ................................................... 3-125
WS27C020L
2 Meg (256K x 8) CMOS EPROM ..................................... 3-127
WS27C220L
2 Meg (128K x 16) CMOS EPROM .................................... 3-133
4 Meg EPROM Selection Guide . ................................................... 3-139
WS27C040L
4 Meg (512K x 8) CMOS EPROM ..................................... 3-141
WS27C240L
4 Meg (256K x 16) CMOS EPROM .................................... 3-147
For additional information,
call 800·TEAM·WSI (800·832·6974).
In California, call 800·562·6363.
________________________________
________________________________
~ss-~
~sI;
WAFERSCALE INTEGRATION, INC.
64K EPROM SELECTION GUIDE
ARCHITECTURE
4Kx16
I
WS57C65
I
==~
8Kx8
I
WS57C64F
I
I
8Kx8
I
WS27C64L
I
8Kx8
Dws27c64F'
I
\\
((
I
I
I
I
!
I
I
I
I
I
I
I
I
ACCESS TIME (ns)
3-1
~::-
3-2
______________________
f"~ i!I!JI~
WI8 - - - - - - - - - - - - - - - - -
WS27C64F
WAFERSCALE INTEGRATION, INC.
MILITARY BK x B CMOS EPROM
KEY FEATURES
• Fast Access Time
-
• EPI Processing
90 ns (Military)
-
Latch-Up Immunity Up to 200 mA
• Standard EPROM Pinout
• Industrial/Military Temperature
Operating Range
• Low Power Consumption
• OESC SMO No. 85102
GENERAL DESCRIPTION
The WS27C64F is a HIGH PERFORMANCE 64K UV Erasable Electrically Programmable Read Only Memory. It is
manufactured in an advanced CMOS technology which enables it to operate at high speeds and very low power over
the full Industrial and Military temperature operating range.
The WS27C64F is a direct drop-in replacement for the industry standard 27C64 and/or 2764 EPROMs. It was developed
specifically for this purpose and requires no board or software modifications to complete the change.
The WS27C64F is configured in the standard EPROM pinout which provides an easy upgrade path to the WS27C128F
and WS27C256F.
MODE SELECTION
PIN CONFIGURATION
TOP VIEW
~
CE
Read
VIL
V IL Vee Vee
DouT
X
V IH Vee Vee
High Z
MODE
Output Disable
OE Vpp
Vcc OUTPUTS
Standby
VIH
X
Vee Vee
High Z
Program
VIL
V IH
V pp Vee
DIN
Program Verify
X
VIL
V pp Vee
DOUT
Program Inhibit
V IH
VIH
V pp Vee
High Z
Signature"
V IL
VIL Vee Vee
Encoded
Data
X can be either VIL or VIH .
"For Signature, Ag = l2V, AD IS toggled, and all other addresses
are at TTL low. AD = VIL = MFGR 23H, AD = VIH = DEVICE ASH
Chip Carrier
r--
~
~
.0.
CERDIP
"I:;
0 0 CJi U
«c(>Z>c.Z
LJ LJ LJ I : LJ ~J LJ
4 3 2
A,
As
A.
A3
A,
A,
Ao
NC
00
L-.J
~
323130
1
29,: As
A.
27[: Al1
=J 8
26 C= NC
=~ 9
25 C= OE
:J 10
24
A,o
:J 11
23
CE
=J 12
22[= 0 7
:J 13
21,: 0,
14
171819
r, 15
.-, 16
r,.-,
,...,,...., 20
,....,
t" I, " " " " '
0,0, INC 3 Os
GND
:J 5
"O~C
:J7
c:
c:
° °.
Vpp [ l
A12 [2
A7 [ 3
A, [ 4
As~5
A.[
A, ~
A, ~
A, [
Ao[
00 ~
0, [
0,[
GND [
28p Vcc
27pPGM
26 NC
25 ~ As
24pA.
P
6 023~Al1
7
22 ~ OE
8
21 A,o
9
20 ~ CE
10
19 ~07
11
18 ~ 0,
12
17 Os
13
16 ~ 0.
14
15 0 3
P
P
b
PRODUCT SELECTION GUIDE
WS27C64F-90
WS27C64F-10
Address Access Time (Max)
90 ns
100 ns
Chip Select Time (Max)
90 ns
100 ns
Output Enable Time (Max)
30 ns
30 ns
PARAMETER
3-3
WS27C64F
ABSOWTE MAXIMUM RATINGS·
'Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ............ -65° to +150°C
Voltage on Any Pin with
Respect to GND ................ -0.6V to +7V
Vpp with respect to GND .......... -0.6V to +14V
ESD Protection ........................ >2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
Military
-55° to +125°C
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range with Vpp = Vcc.
SYMBOL
TEST CONDITIONS
PARAMETER
MAX
UNITS
0.4
V
200
J.lA
Note 2
10
mA
Notes 1 and 3
25
mA
IOL
V OH
Output High Voltage
IOH
IS61
Vcc Standby Current (CMOS)
Note 1
IS62
Vcc Standby Current (TTL)
ICC1
Vcc Active Current (CMOS)
VOL
ICC2
Vcc Active Current (TTL)
Notes 2 and 3
Ipp
Vpp Supply Current
Vpp
Vpp
V pp Read Voltage
= 5.5V or Gnd
= 5.5V or Gnd
Input Load Current
V 1N
ILO
Output Leakage Current
VOUT
1. CMOS Inputs: GND ± O.3V or Vee ± O.3V.
2. TTL Inputs: V1L .;; O.BV, V1H ~ 2.0V
2.4
V
35
mA
100
J.lA
Vcc - 0.4
Vcc
V
-10
10
-10
10
J.tA
J.tA
= Vcc
III
NOTES:
MIN
= 4 mA
= -1 mA
Output Low Voltage
3. Add 3 rnA/MHz for A.C. power component.
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vcc.
PARAMETER
SYMBOL
WS27C64F-90
MIN
MAX
WS27C64F-10
MIN
MAX
Address to Output Delay
tACC
90
100
CE to Output Delay
tCE
90
100
OE to Output Delay
tOE
30
30
Output Disable to Output Float
tDF
30
30
Address to Output Hold
tOH
0
UNITS
ns
0
---------------------~Jri~------------------3-4
WS27C64F
AC READ TIMING DIAGRAM
ADDRESSES
CE-------,..
OE--------~
OUTPUTS
CAPACITANCEf4)
SYMBOL
---------~~t~~ta~--
TA = 25°C, f = 1 MHz
PARAMETER
C IN
Input Capacitance
C OUT
Output Capacitance
C VPP
Vpp Capacitance
NOTES:
CONDITIONS
Typ(5)
MAX
UNITS
VIN = OV
4
6
pF
VOUT = OV
8
12
pF
Vpp = OV
18
25
pF
4. This parameter IS only sampled and IS not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages.
TEST WAD
(High Impedance Test Systems)
Input Levels: .45 and 2.4V
3200
2.01V
TIMING LEVELS
o--V---1
Reference Levels: .8 and 2.0V
D.U.T.~ 100 pF
I-=-
(INCWDING SCOPE
AND JIG
CAPACITANCE)
--------------------~~i~-----------------3-5
WS27C64F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ±
5°C, Vee = 5.5V ± 5%, Vpp
PARAMETER
MIN
MAX
UNIT
III
-10
10
~
60
mA
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During_ _
Programming Pulse (CE = PGM
Ipp
= VILl
Vec Supply Current (Note 3)
Icc
V IL
V IH
Input Low Level
Input High Level
Output Low Voltage During Verify
(l0L = 4 mAl
VOL
Output High Voltage During Verify
(lOH = -1 mAl
VOH
NOTES:
13.5 ± 0.5V)
SYMBOLS
50
mA
-0.1
0.8
V
2.0
Vee +0.3
V
0.45
V
2.4
V
6 Vcc must be applied either cOincidentally or before Vpp and removed either cOincidentally or after Vpp
7. Vpp must not be greater than 14 volts including overshoot. During CE = PGM = V IL ' Vpp must not be sWitched from 5 volts
to 13.5 volts or vice-versa.
8. During power up the PGM pin must be brought high ("VI H) either cOincident with or before power IS applied to Vpp.
AC CHARACTERISTICS
(TA
=
25 +
- 5°C, Vcc
PARAMETER
=
5.5V +
- 5%, Vpp
=
13.5 +
- 0.5V)
TYP
SYMBOLS
MIN
Address Setup Time
tAS
2
I-ts
Chip Enable Setup Time
tCES
2
I-tS
Output Enable Setup Time
tOES
2
I-ts
Data Setup Time
tos
2
I-ts
Address Hold Time
tAH
0
I-ts
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tOF
0
Data Valid From Output Enable
tOE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
MAX
130
130
UNIT
I-ts
ns
ns
I-tS
3
10
ms
NOTE: Single pulse programming algorithms should use one 10 ms PGM pulse per byte.
PROGRAMMING WAVEFORM
ADDRESSES
==:)!
ADDRESS STABLE
DATA~
DATA IN STABLE
+-Ios'"
HIGHZ
1-10.....
I-IoH-
Vpp
Vpp
CE
Vcc~
c=
-- ----1
-lAS ---
tAH
DATA OUT
VALID
tDF
:-Ivs-
VIH~
V'L
I-ICES---
V,H
PGM
V'L
V,H
DE
V'L
tx,
j
I--Ipw-j
_IOES 1
~
J
-----------------------~Jr;~--------------------3-6
WS27C64F
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS27C64F-90CM B
WS27C64F-900MB
WS27C64F-10CMB
WS27C64F-1 OOM B
90
90
100
100
PACKAGE
TYPE
32
28
32
28
Pad CLLCC
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
C2
02
C2
02
Military
Military
Military
Military
MIL-STO-883C
MIL-STD-883C
MIL-STD-883C
MIL-STO-883C
-"_'8S.
---------------------------------~~:-------------------------------3-7
:-:-_____________________________________________ fAfjfZFE ________________________________________________
3-8
~I;
WS27C64L
WAFERSCALE INTEGRATION, INC.
BK
X
B CMOS EPROM
KEY FEATURES
• High Performance CMOS
-
• EPI Processing
90 ns Access Time
-
• Fast Programming
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000V
• Drop-In Replacement for 27C64 or 2764
• Standard JEDEC EPROM Pinout
• 300 Mil Dip or Standard 600 Mil Dip
• DESC SMD No. 85102
GENERAL DESCRIPTION
The WS27C64L is a HIGH PERFORMANCE 64K UV Erasable Electrica"y Programmable Read Only Memory. It is
manufactured in WSI's latest CMOS EPROM technology which enables it to operate at speeds as fast as 90 ns access
time over the full operating range.
The WS27C64L can directly replace any 8K x 8 EPROM which conforms to the JEDEC standard. Examples of this
would be as follows: 2764 or 27C64. It can be easily programmed using standard EPROM programmers or the
MagicPro™ IBM PC compatible engineering programmer offered by WSI.
The WS27C64L is also available in a 300 mil Dip. The pin configuration remains the same as the 600 mil wide package
and the programming algorithms are unchanged. This allows for a simple PCB layout change to take advantage of
a 50% reduction in required board space.
The WS27C64L provides microprocessor-based systems storage capacity for portions of operating system and
application software. Its 90-ns access time provides no-wait-state operation with high-performance CPUs such as
the 16-MHz 80186, 16-MHz 68020, or 12-MHz 80386. The WS27C64L offers a single chip solution for the code storage
requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from EPROM
storage, greatly enhancing system utility.
The WS27C64L is configured in the standard EPROM pinout which provides an easy upgrade path for systems which
are currently using standard EPROMs.
The WS27C64L is one member of a high-density EPROM Family which ranges in density from 64K to 4 Megabit.
PRODUCT SELECTION GUIDE
PARAMETER
27C64L-90
27C64L-12
27C64L-15
27C64L-20
Address Access Time (Max)
90 ns
120 ns
150 ns
200 ns
Chip Select Time (Max)
90 ns
120 ns
150 ns
200 ns
Output Enable Time (Max)
30 ns
35 ns
40 ns
40 ns
."JE.4IrE
---------------------------------~~8-------------------------------3-9
WS27C64L
ABSOLUTE MAXIMUM RATINGS·
"Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to + 150°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vee Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ....................... > 2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
TOLERANCE
Commercial
O°C to +70°C
+5V
±5% or ±10%
-40°C to +85°C
+5V
+10%
-55°C to + 125°C
+5V
+10%
Industrial
Military
DC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
SYMBOL
PARAMETER
MIN
MAX
VIL
Input Low Level
TEST CONDITIONS
-0.5
0.8
V
VIH
Input High Level
2.0
V
VOL
Output Low Voltage
IOL = 2.1 mA
Vce + 1
0.4
VOH
IS 81 (3)
Output High Voltage
Vee Standby Current (CMOS)
100
IS82
Vee Standby Current
J.lA
mA
lee(l)
Vee Active Current
IOH = -400 J.lA
CE = Vee + 0.3V
CE = VIH
IF=5MHz
_
_
CE = OE = VIL F = 8 MHz
Ipp
Vpp Supply Current
Vpp = Vee
Vpp
Vpp Read Voltage
III
Input Load Current
ILO
Output Leakage Current
3.5
V
V
1
40
I
VIN = 5.5V or Gnd
VOUT = 5.5V or Gnd
UNITS
50
100
Vee -0.4
-1
Vee
1
-10
10
mA
J.lA
V
J.tA
J.lA
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vee·
SYMBOL
PARAMETER
27C64L-90
MIN
MAX
27C64L-12
MIN
MAX
27C64L-15
MIN
MAX
27C64L-20
MIN
MAX
tAee
Address to Output
Delay
90
120
150
200
teE
CE to Output Delay
90
120
150
200
tOE
OE to Output Delay
30
35
40
40
tDF(2)
Output Disable to
Output Float
30
35
40
40
tOH(2)
Output Hold From
Addresses, CE or
OE, Whichever
Occurred First
UNITS
ns
0
0
0
0
NOTES:
1. The supply current is the sum of lee and Ipp. The maximum current value is with Outputs 0 0 to 0 7 unloaded.
2. This parameter 's only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven-see timing diagram.
3. CMOS inputs: V'L = GND ± 0.3V, V'H = Vee ± 0.3V.
---------------------~Jr;'---------------------3-10
WS27C64L
A.C. WAVEFORMS
V,H
-----_
ADDRESS
VALID
ADDRESSES
VIL
------
V,H
--------11-""\.
V,H
--------11----"""\.
14----- IACC -----I
HIGH Z
HIGH Z
OUTPUT -------------+H~+_<
CAPACITANCE(4)
TA
1 MHz
SYMBOL
PARAMETER
C IN
Input Capacitance
COUT
Output Capacitance
CvPp
Vpp Capacitance
CONDITIONS
TYP(S)
MAX
UNITS
VIN = OV
4
6
pF
VOUT = OV
8
12
pF
Vpp = OV
18
25
pF
NOTES:
4. This parameter is only sampled and IS not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages.
6. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE .
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.04V
-,2.4
>
2~
TEST POINTS
0.4
0.8
<
~
~
2~
DEVICE
UNDER
TEST
0.8
I
820Q
CL
= 100pF
A.C. testing inputs are driven at 2AV for a Logic "1" and
OAV for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and O.BV for a Logic "0."
CL includes Jig Capacitance
f!;
.r Jiil5ff
--------------------~~.~-------------------3-11
WS27C64L
MODE SELECTION
The modes of operation of the WS27C64L are listed in Table 1. A single SV power supply is required in the read mode.
Table 1. Modes Selection
~
PGM
CE
-
OE
V pp
Vcc
OUTPUTS
Read
X
VIL
V IL
S.OV
S.OV
Output Disable
X
X
VIH
S.OV
S.OV
DOUT
High Z
X
High Z
MODE
Standby
S.OV
S.OV
V IL
VIH
VIL
X
Programming
V IH
Vpp
S.8V
DIN
Program Verify
VIH
V IL
V IL
Vpp
S.8V
Program Inhibit
X
VIH
X
Vpp
S.OV
DOUT
High Z
NOTES:
7. X can be V,L or V ,H .
DIP PIN CONFIGURATIONS
8 Mbil
4 Mbil
2 Mbil
A,g
A,s
A,s
XX/Vpp
A,s
A,s
XX/Vpp
A,s
A,s
XX/Vpp
A,s
A,s
Vpp
I-
A'2
A7
As
As
A.
A3
A2
A,
Ao
A'2
A7
As
As
A.
A3
A2
A,
Ao
A'2
A7
As
As
A.
A3
A2
A,
Ao
A'2
A7
As
As
A.
A3
A2
A,
Ao
A'2
A7
As
As
A.
A3
A2
A,
Ao
1-,
00
0,
00
00
00
0,
0,
0,
00
0,
°2
GND
°2
GND
O2
GND
°2
GND
O2
GND
NOTE:
27C010L 27C256L
27C256L 27C010L
Vee
Vee
XX/PGM XX/PGM
XX
A'7
A,.
A,.
A'3
A'3
As
As
Ag
Ag
Al1
Al1
OE
OE
A,o
A,o
CE
CE
07
07
Os
Os
WS27C64L
II-
II-
I- A,
I - A,
I - A,
I - Ao
l - 0.
I - 0,
I- 0,
GNO
2 Mbil
v cc- -
Vcc
A,.
A'3
A.-As
A.-Ag
A l1 - Al1
oe-- OE
A IO- A10
CE/PGM
07-07
0.-- Os
0,-05
0.-O.
0,-03
Pmn-
NC--
cr--
4 Mbil
8 Mbil
Vee
A,s
Vee
A,s
A'7
A,.
A'7
A,.
A'3
As
Ag
Al1
OE/vpp
A,o
CE/PGM
07
Os
A'3
As
Ag
Al1
OE
A10
CE/PGM
07
Os
05
05
05
05
O.
03
O.
03
O.
03
O.
03
8. Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C64L pins.
LCC PIN CONFIGURATION
PIN NAMES
,..
Iii ()
~ >&: (,)
g
z> o.z
41:( c:(
Addresses
CE
Chip Enable
OE
Output Enable
Outputs
PGM
XX
Program
Don't Care (During Read)
13
21[= 0 6
~~~~ }~g ~~~~ ~~
NOTE: Leadless or
Leaded, Plastic or
Ceramic Package
--------------------------~Jr;.----------------------------3-12
WS27C64L
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vcc
PARAMETER
5.8V ± 0.25V, Vpp
12.75 ± 0.25V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
(VIN = Vcc or Gnd)
III
-10
10
J.lA
Vpp Supply Current Durin_g_
Programming Pulse (CE, PGM = VILl
Ipp
60
mA
Vcc Supply Current, See Icc2
Icc
40
mA
Input Low Level
V IL
-0.1
0.8
V
2.0
Vcc+0.3
V
0.4
V
Input High Level
V IH
Output Low Voltage During Verify
(Iol = 2.1 mAl
VOL
Output High Voltage During Verify
(IOH = -400 J.lA)
VOH
NOTES:
3.5
V
9. Vcc must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp.
10. Vpp must not be greater than 14 volts including overshoot. DUring CE, PGM = VIL • Vpp must not be switched from 5 volts to
12.75 volts or vice-versa.
11. DUring power up the PGM pin must be brought high (;.V IH ) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS (TA
=
25 ± 5°C, Vcc
PARAMETER
=
5.8V ± 0.25V, Vpp
=
12.75 ± 0.25V)
SYMBOLS
MIN
Address Setup Time
tAS
2
J.lS
Chip Enable Setup Time
tCES
2
J.ls
Output Enable Setup Time
tOES
2
J.ls
Data Setup Time
tos
2
J.lS
Address Hold Time
tAH
0
J.lS
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
Data Valid From Output Enable
tOE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
0.1
TYP
MAX
130
130
UNIT
J.lS
ns
ns
J.ls
4
ms
PROGRAMMING WAVEFORM
ADDRESSES
DATA
v••
v••
Vee
V'H
CE
V"
V,H
PGM
V"
V,H
OE
V"
___ I
3-13
--------------------------------------~~~~-----------------------------------
WS27C64L
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
WS27C64 L-90 D/5
WS27C64L-12D
WS27C64L-12DI
WS27C64L-12DMB
WS27C64L-12J
WS27C64L-12P
WS27C64L-12T
WS27C64L-15D
WS27C64L-15DMB
WS27C64L-15J
WS27C64L-20D
WS27C64L-20DM B
WS27C64L-20J
SPEED
PACKAGE
TYPE
(ns)
90
120
120
120
120
120
120
150
150
150
200
200
200
28
28
28
28
32
28
28
28
28
32
28
28
32
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
CERDIp, 0.6"
CERDIp, 0.6"
CERDIp, 0.6"
CERDIp, 0.6"
PLDCC
Plastic DIP, 0.6"
CERDIP, 0.3"
CERDIp, 0.6"
CERDIp, 0.6"
PLDCC
CERDIp, 0.6"
CERDIP, 0.6"
PLDCC
PACKAGE
DRAWING
D2
D2
D2
D2
J4
P3
T2
D2
D2
J4
D2
D2
J4
OPERATING
RANGE
TEMPERATURE
Comm'l
Comm'l
Industrial
Military
Comm'l
Comm'l
Comm'l
Comm'l
Military
Comm'l
Comm'l
Military
Comm'l
Vee
WSI
MANUFACTURING
PROCEDURE
±5%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
____________________________________ ftiftii!_ _ __--____--__-------------------f;IAr~
3-14
-F'. . . .
-..II'''
== ==JE_______________________________________________________________
~--
==r~~
WS57C64F
~
:=
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 8K x 8 CMOS EPROM
KEY FEATURES
• Fast Access Time
-
• EPI Processing
55 ns
-
• Low Power Consumption
• DESC SMD No. 85102
Latch-Up Immunity Up to 200 mA
• Standard EPROM Pinout
• Bipolar Speeds
GENERAL DESCRIPTION
The WS57C64F is an extremely HIGH PERFORMANCE 64K UV Erasable Electrically Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar speeds while
consuming very little power.
Two major features of the WS57C64F are its Low Power and High Speed. These features make it ~n ideal solution
for applications which require fast access times, low power, and non-volatility. Typical applications include
systems which do not utilize mass storage devices and/or are board space limited. Examples of these
applications are modems, secure telephones, servo controllers, and industrial controllers.
The WS57C64F is configured in the standard EPROM pinout which provides an easy upgrade path to higher
density EPROMs.
MODE SELECTION
PIN CONFIGURATION
TOP VIEW
~
MODE
Read
PGM
CE
OE
Vpp
vee
OUTPUTS
X
VIL
VIL
5.0V
5.0V
DOUT
Chip Carrier
.c 1
8:0
CERDIP
gl~ 0
>Z>ID.Z
vpp~
A12~
" " , 'I I ' " ,,,
Output
Disable
X
X
Standby
X
VIH
X
Programming
VIL
VIL
VIH
Vpp
5.8V
DIN
Program
Verify
VIH
VIL
VIL
Vpp
5.8V
DOUT
Program
Inhibit
X
VIH
VIH 5.0V 5.0V
High Z
5.0V 5.0V
High Z
X
Vpp
5.0V
X ean be VIL or VIH .
High Z
A.
A,
A.
A,
A2
A,
A.
NC
o.
4-' '3-' '2-'LJ323130
5
1
29[=
:o::~
S
9
10
11
26 C=
25[=
24 C=
23[=
12
22 c:
13
21 ~:
14151617181920
r,,...,,.,,...,,...,,.,,.,
'"
" 'I"""
r
0, O2 INC 0,0.0,
GNO
As
Ag
Al1
NC
OE
A"
CE
07
o.
.....------.r--
1
2
28 ~vcc
27~PGM
A;~3
26~NC
A,~9
20~CE
A.[4
25~As
A.[ 5
24~Ag
A.~ 6 023~Al1
A,~ 7
22~OE
A2[8
21~A,.
A.~ 10
o.~ 11
0, [ 12
02~ 13
GNO[ 14
19 ~ 07
18 ~ o.
17 ~ 0,
16 ~ O.
15 po,
PRODUCT SELECTION GUIDE
PARAMETER
WS57C64F-55
WS57C64F-70
Address Access Time (Max)
55ns
70ns
Chip Select Time (Max)
55ns
70ns
Output Enable Time (Max)
20ns
25ns
3-15
WS57C64F
ABSOWTE MAXIMUM RATlNGS*
·Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ............ -65° to +150°C
Voltage on Any Pin with
Respect to GND ................ -0.6V to +7V
Vpp with Respect to GND ......... -0.6V to +14V
ESD Protection ........................ >2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
0° to +70°C
+5V ± 5%
Industrial
-40° to +85°C
+5V ± 10%
Military
-55° to +125°C
+5V ± 10%
Comm'l
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range with Vpp
PARAMETER
= Vcc.
TEST CONDITIONS
VOL
Output Low Voltage
VOH
Output High Voltage
IS81
Vcc Standby Current (CMOS)
IS82
Vcc Standby Current (TTL)
= 16 rnA
IOH = -4 rnA
CE = Vcc ± 0.3V (Notes 1 &3)
CE = VIH (Notes 2 & 3)
ICCl
Vcc Active Current (CMOS)
Notes 1 and 4
Icc2
Vcc Active Current (TTL)
Notes 2 and 4
Ipp
Vpp Supply Current
Vpp
Vpp
Vpp Read Voltage
III
Input Load Current
ILO
NOTES:
Address to Output Delay
UNITS
0.4
V
500
IlA
15
rnA
2.4
V
Comm'l
20
Military
30
Comm'l
25
Military
35
= Vcc
100
rnA
rnA
~A
Vcc - 0.4
Vcc
V
-10
10
-10
10
IlA
IlA
= 5.5V or Gnd
VOUT = 5.5V or Gnd
V1N
Output Leakage Current
PARAMETER
MAX
IOL
1. CMOS Inputs: GND ± O.3V or Vee ± O.3V.
2. TIL inputs: V1L '" O.8V, V1H .. 2.0V.
AC READ CHARACTERISTICS
MIN
3. Add 1 rnA/MHz for A.C. power component.
4. Add 3 rnA/MHz for A.C. power component.
Over Operating Range with Vpp = Vcc.
SYMBOL
WS57C64F-55
MIN
MAX
WS57C64F-70
MIN
MAX
tACC
55
CE to Output Delay
tCE
55
70
OE to Output Delay
tOE
20
25
Output Disable to Output Float
tOF
20
25
Address to Output Hold
tOH
10
UNITS
70
ns
10
-------------------------~Jr;------------------------3-16
WS57C64F
AC READ TIMING DIAGRAM
ADDRESSES
CE----,
OE-------~
OUTPUTS---------~~t~~!lt3~f.-tDF
CAPAC/TANCE(5) T A
SYMBOL
25°C, f
1 MHz
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
CvPp
Vpp Capacitance
NOTES:
CONDITIONS
VIN
VOUT
Vpp
= OV
= OV
= OV
TYP(6)
MAX
UNITS
4
6
pF
8
12
pF
18
25
pF
5. This parameter IS only sampled and IS not 100% tested.
6. Typical values are for TA = 25°C and nominal supply voltages.
TEST LOAD (High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0 and 3V
98Q
2.04V~
Reference Levels: 0.8 and 2.0V
D.u.T·~30PF
I-=-
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
=-- ",IE
---------------------------------------~.,Ar-------------------------------------3·17
WS57C64F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 +
- 5°C, Vee
PARAMETER
5.5V +
- 5%, Vpp
-
SYMBOLS
MIN
MAX
UNIT
III
-10
10
Il A
60
mA
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During_ _
Programming Pulse (CE = PGM
13.5 + 0.5V)
Ipp
= VILl
Vee Supply Current
lee
V IL
V IH
Input Low Level
Input High Level
Output Low Voltage During Verify
(lOL = 16 mAl
VOL
Output High Voltage During Verify
(lOH = -4 mAl
VOH
25
mA
-0.1
0.8
V
2.0
Vee +0.3
V
0.45
V
2.4
V
NOTES: 7. Vee must be applied either coincidentally or before Vpp and removed either cOincidentally or after Vpp.
8. Vpp must not be greater than 14 volts including overshoot. DUring CE = PGM = VIL , Vpp must not be sWitched from 5 volts
to 13.5 volts or vice·versa.
9. During power up the PGM pin must be brought high (?>V IH ) either coincident with or before power IS applied to Vpp.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
Chip Enable Setup Time
Output Enable Setup Time
TYP
MAX
UNIT
SYMBOLS
MIN
tAS
2
IlS
teEs
2
Il s
tOES
2
Il s
IlS
Il s
Address Setup Time
Data Setup Time
tos
2
Address Hold Time
tAH
0
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
Data Valid From Output Enable
tOE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
3
130
Il s
ns
130
ns
10
Il s
ms
NOTE: For simple, one pulse only, programming algorithms, use a 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
~
ADDRESS STABLE
1-'" ...
DATA
-----1
V••
V••
Vee - - - - - - '
ee
VIH~
DATA IN STABLE
--'0'-
HIGH Z
-'OH-
·'OE
I
-..j
,..
DATA OUT
VALID
-
tAH
'OF
K=
I--~
I--
--'v.-
V"
-'CES'"
V,H
PGM
V"
V,H
OE
v"
~
l--'OE'1
~
/
-------------------------~Jr;'-------------------------3-18
WS57C64F
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(n8)
WS57C64F·550
WS57C64F·70CMB
WS57C64F·700
WS57C64F·7001
WS57C64F·700MB
WS57C64F·70J
55
70
70
70
70
70
PACKAGE
TYPE
28
32
28
28
28
32
Pin CEROIp,
Pad CLLCC
Pin CEROIP,
Pin CEROIp,
Pin CEROIp,
Pin PLOCC
0.6"
0.6"
0.6"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
02
C2
02
02
02
J4
Comm'l
Military
Comm'l
Industrial
Military
Comm'l
Standard
MIL·STO·883C
Standard
Standard
MIL·STD·883C
Standard
---------------------~Jri~------------------3·19
~3_2=O----------------------~Jri------------------------
WS57C65
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 4K x 16 WORD WIDE CMOS EPROM
KEY FEATURES
• Fast Access Time
-
• 2 to 1 Package Reduction
55 ns
• 300/0+ Space Savings
• Low Power Consumption
• Single Chip Solution
• Ideal for 16/32 Bit Processors
-
• Compatible with JEDEC pinout
TMS320, 68000, 80386, etc.
GENERAL DESCRIPTION
The WS57C65 is a High Performance EPROM memory with a 4K x 16 architecture. It is manufactured in an advanced
CMOS process which consumes very little power while operating at speeds which rival that of bipolar PROMs.
The major features of the WS57C65 are its 4K x 16 architecture and its high speed. This combination makes the
WS57C65 an ideal solution for applications which utilize 16/32 bit data paths. Examples include systems which are
based on such processors as the TMS320 family of DSP processors as well as high performance general purpose
processors such as the MC68000 family and the 80286 and 80386 microprocessors.
The word wide architecture of the WS57C65 results in a 2 to 1 savings in EPROM component count and a minimum
30% savings in board space.
The pin configuration utilized is upward compatible with the JEDEC standard pinout for word wide EPROMs. This
allows an easy upgrade path to higher density memories such as the WS57C257. No board changes or jumper wires
are required to complete the upgrade.
PIN CONFIGURATION
MODE SELECTION
PINS
MODE
Read
Output Disable
OE
V IL
V IL Vee Vce
V IH Vee Vee
X
Standby
V IH
Program
VIL
X
V pp
vpp
Vcc OUTPUTS
CE
Vee Vee
Dour
High Z
J J J I~ J ~ ~ ~ ~ ~ ~
1
CE
0 15
High Z
VIH V pp Vee
DIN
VIL
Program Verify
X
Program Inhibit
VIH
V IH V pp Vee
Dour
High Z
Signature'
VIL
VIL Vee Vee
Encoded
Data
V pp Vee
P
vee
PGM
NC
NC
NC
NC
NC
A"
A,.
A.
GND
As
A7
As
As
X can be either V1L or V1H .
'For Signature, Ag = 12V, PvJ is toggled, and all other addresses
are at TIL low. PvJ = V1L = MFGR 0023H, PvJ = V1H =
A.
A3
A,
DEVICE OOB1H.
PRODUCT SELECTION GUIDE
PARAMETER
WS57C65-55
WS57C65-70
70 ns
Address Access Time
55 ns
Chip Select Time
55 ns
70 ns
Output Enable Time
25 ns
30 ns
3-21
WS57C65
ABSOLUTE MAXIMUM RATlNGS*
'Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ............ -65° to +150°C
Voltage on Any Pin with
Respect to GND ................ -0.6V to +7V
Vpp with Respect to GND ......... -0.6V to + 14V
ESD Protection ........................ >2000V
OPERATING RANGE
RANGE
Comm'l
Industrial
TEMPERATURE
Vcc
0° to +70°C
+5V ± 5%
-40° to +85°C
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
TEST CONDITIONS
PARAMETER
MIN
MAX
UNITS
0.4
V
VOL
Output Low Voltage
IOL = 8 mA
VOH
Output High Voltage
IOH = -2 mA
500
J.lA
20
mA
2.4
V
ISB1
Vcc Standby Current (CMOS)
Notes 1 and 3
ISB2
Vcc Standby Current (TTL)
Notes 2 and 3
Active Current (CMOS)
Notes
1 and 4
Comm'l
35
Icc1
Military
45
Vcc Active Current (TTL)
Notes
2 and 4
Comm'l
45
Icc2
Military
55
Ipp
Vpp Supply Current
Vpp = Vcc
Vpp
V pp Read Voltage
III
Input Load Current
ILO
Output Leakage Current
NOTES: 1. CMOS inputs: GND ± a.3V or Vee ± a3V
2. TTL Inputs: V'L '" a BV. V,H ;;, 2 av.
100
mA
mA
J.lA
Vcc - 0.4
Vcc
V
V IN = 5.5V or Gnd
-10
10
J.lA
VOUT = 5.5V or Gnd
-10
10
J.lA
3. Add 1 mA/MHz for A.G. power component.
4. Add 3 mA/MHz for A G. power component
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
SYMBOL
WS57C65-55
MIN
MAX
WS57C65-70
MIN
MAX
Address to Output Delay
tACC
55
70
CE to Output Delay
tCE
55
70
OE to Output Delay
tOE
25
30
Output Disable to Output Float
tOF
Address to Output Hold
tOH
___________________________________
3-22
25
0
UNITS
ns
30
0
f;;~=------------------------------------
~S's
WS57C65
AC READ TIMING DIAGRAM
ADDRESSES
CE - - - - - - .
OE-------....
OUTPUTS-----------4(ft~~tj~1-IoF
CAPACITANCE(5)
SYMBOL
TA = 25°C, f = 1 MHz
PARAMETER
C IN
Input Capacitance
C OUT
Output Capacitance
CvPp
Vpp Capacitance
NOTES:
I--
CONDITIONS
TYP(6)
MAX
UNITS
V IN = OV
4
6
pF
VO UT = OV
8
12
pF
Vpp = OV
18
25
pF
5 This parameter IS only sampled and is not 100% tested.
6. TYPical values are for TA = 25°C and nominal supply voltages.
TEST LOAD
(High Impedance Test Systems)
160n
2.01V
D.u.T.
Input Levels: 0 and 3V
0---1\,/'--]
<>---±
I
-=-
TIMING LEVELS
Reference Levels: 0.8 and 2.0V
30pF
(INCWDING SCOPE
AND JIG
CAPACITANCE)
---------------------~Jri--------------------3-23
WS57C65
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee
5.5V
PARAMETER
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During __
Programming Pulse (CE = PGM
5%, Vpp
13.5
±
0.5V)
MIN
MAX
UNIT
III
-10
10
Il A
50
mA
35
mA
Ipp
= VILl
Vee Supply Current (Note 4)
lee
V IL
V IH
Input Low Level
Input High Level
Output Low Voltage During Verify
(lOL = 8 mA)
VOL
Output High Voltage During Verify
(lOH = -2 mA)
VOH
NOTES:
±
SYMBOLS
-0.1
0.8
V
2.0
Vee +0.3
V
0.45
V
2.4
V
7. Vee must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp.
8. Vpp must not be greater than 14 volts including overshoot During CE = PGM = V ,L, Vpp must not be switched from 5 volts
to 13.5 volts or vice-versa
9. During power up the PGM pin must be brought high (;>V ,H ) either cOincident with or before power IS applied to Vpp .
AC CHARACTERISTICS (TA
= 25 +-
= 5.5V +-
5°C, Vec
5%, Vpp
= 13.5
± 0.5V)
SYMBOLS
MIN
Address Setup Time
tAS
2
IlS
Chip Enable Setup Time
teEs
2
IlS
Output Enable Setup Time
tOES
2
IlS
Data Setup Time
tos
2
IlS
Address Hold Time
tAH
0
Il s
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
Data Valid From Output Enable
tOE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
PARAMETER
TYP
MAX
130
130
UNIT
Il s
ns
ns
IlS
3
10
ms
NOTE: Single shot programming algorithms should use a single 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
~
ADDRESS STABLE
-+I
I- lAS"
DATA
-----1
DATA IN STABLE
I-- los"
Vee
CE
I-IoE ....
I-IOH -
Vpp
Vpp
HIGH Z
tAH
K=
I--
DATA OUT
VALID
-
IOF
I--
----1 4-lvs -
VIH~
V'L
-ICES'"
V,H
PGM
V'L
X
I-Ipw
V,H
DE
V'L
.¥
-I
i--IOES'I
1;
/
------------------------------~JrAr·-----------------------------3-24
WS57C65
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
WS57C65-55C
WS57C65-550
WS57C65-700
SPEED
(ns)
PACKAGE
TYPE
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
55
55
70
44 Pad CLLCC
40 Pin CEROIP, 0.6"
40 Pin CEROIp, 0.6"
C3
03
03
Comm'l
Comm'l
Comm'l
Standard
Standard
Standard
_ _______________________________ F • •
-~_·
iMl.
________________________________
3-25
~3'2~6-----------------------~Jf;-------------------------
WAFERSCALE INTEGRATION, INC.
128K EPROM SELECTION GUIDE
ARCHITECTURE
Q
16K X 8
WS27C128F
I
16K X 8
16K X 8
I
WS57C128F
I
I
I
55
I
WS27C128L
"
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
ACCESS TIME (n5)
3-27
~3-2=8-----------------------~Jr;------------------------
WS27C128F
WAFERSCALE INTEGRATION, INC.
MILITARY 16K x 8 CMOS EPROM
KEY FEATURES
• Fast Access Time
-
• EPI Processing
90 ns (Military)
-
Latch-Up Immunity Up to 200 mA
• Low Power Consumption
• Standard EPROM Pinout
• DESC SMD No. 5962-87661
• Industrial/Military Operating Range
GENERAL DESCRIPTION
The WS27C128F is an extremely HIGH PERFORMANCE 128K UV Erasable Electrically Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which enables it to operate at high speeds and very
low power over the full industrial and military temperature operating range.
The WS27C128F was specifically designed to replace standard EPROMs in industrial and military environments. No
hardware or software changes are required to replace standard military 27128 EPROMs with the WSI WS27C128F.
The WS27C128F is configured in the standard EPROM pinout which provides an easy upgrade path for the WS27C64F
and the 256K bit WS27C256F.
PIN CONFIGURATION
MODE SELECTION
TOP VIEW
~
CE
OE
V pp
Vcc OUTPUTS
Read
VIL
VIL
Vee
Vee
MODE
Chip Carrier
DouT
CERDIP
til
Q.
()I~ COl
I'...
Q. u
0 (!)
ctZ>c..<[
T'""
Output Disable
X
VIH Vee Vee
High Z
Vee Vee
High Z
V IH
V pp
Vee
DIN
Standby
VIH
X
Program
V IL
Program Verify
X
V IL
V pp
Vee
DOUT
Program Inhibit
V IH
V IH
V pp
Vee
High Z
Signature'
V IL
V IL
Vee Vee
Encoded
Data
X can be either VIL or VIH .
"For Signature, A" = 12\1, ~ is toggled, and all other addresses
are at TIL low. ~ = VIL = MFGR 23H, ~ = VIH = DEVICE ABH.
Vpp [
~J~J~J: :~J~JLJ
A,
A,
A,
A3
A2
A,
Ao
NC
00
4 3 2 ""323130
29,: As
1
5
A,
7
27 C= A"
8
26 [= NC
9
25,: OE
10
24,: A,o
11
23,: ee
12
22,: 0 7
13
21,: 0,
14151617181920
'0'"
~~:-1 ~iii ii~i
i"1
0, O2 INC 030,OS
~
1
A'2[ 2
A~ ~
28 ] vee
27 JPGM
S
3
26 A13
A , 4 2 5 As
A~[ 5
24 ] A,
A:~
6 0 2 3 JA"
A37
22]OE
A;C 8
21 JA"
A,[9
20Jee
A~~ 10
0 0 11
0, [ 12
02[ 13
GNO[ 14
S
19 07
18 0,
17 ] Os
16 ] 0,
15 j 0 3
GNO
PRODUCT SELECTION GUIDE
PARAMETER
WS27C128F-90
Address Access Time (Max)
90 ns
Chip Select Time (Max)
90 ns
Output Enable Time (Max)
30 ns
3·29
WS27C128F
ABSOWTE MAXIMUM RATINGS
Storage Temperature ............. -65° to +150°C
Voltage on Any Pin with
Respect to GND ................. -0.6V to +7V
Vpp with respect to GND ........... -0.6V to +14V
ESD Protection ......................... >2000V
"Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
OPERATING RANGE
TEMPERATURE
Vcc
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range with Vpp = Vce.
SYMBOL
VOL
PARAMETER
TEST CONDITIONS
Output Low Voltage
MIN
IOL=4mA
VOH
Output High Voltage
IOH = -1 mA
IS81
Vee Standby Current (CMOS)
Note 1
MAX
UNITS
0.4
V
200
~
2.4
V
IS82
Vee Standby Current (TTL)
Note 2
10
mA
lec1
Vee Active Current (CMOS)
Notes 1 and 3
25
mA
lec2
Vee Active Current (TTL)
Notes 2 and 3
35
mA
Ipp
Vpp Supply Current
Vpp = Vee
100
~
Vpp
Vpp Read Voltage
Vee - 0.4
Vee
V
III
Input Load Current
V IN = 5.5V or Gnd
-10
10
~
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
j.!A
NOTES:
1. CMOS Inputs: GND ± 0.311 or Vee
2. TIL inputs: V1L .; OIN, V1H ;;. 2.0y'
±
0.3Y.
3. Add 3 mA/MHz for A.C. power component.
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
PARAMETER
SYMBOL
WS27C128F-90
MIN
MAX
Address to Output Delay
tAee
90
CE to Output Delay
teE
90
OE to Output Delay
tOE
30
Output Disable to Output Float
tDF
Address to Output Hold
tOH
UNITS
ns
30
0
NOTE: Single shot programming algorithms should use one 10 ms PGM pulse per word.
------------------------------~Jr~----------------------------3-30
WS27C128F
AC READ TIMING DIAGRAM
ADDRESSES
CE-------,.
~-------,
OUTPUTS
CAPACITANCE(4) TA
SYMBOL
---------~:s3t~~ta7--
25°C, f
1 MHz
PARAMETER
C IN
Input Capacitance
COUT
Output Capacitance
CvPp
Vpp Capacitance
NOTES:
CONDITIONS
Typ(5)
MAX
UNITS
VIN = OV
4
6
pF
VOUT = OV
8
12
pF
Vpp = OV
18
25
pF
4. This parameter IS only sampled and IS not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages
TEST LOAD (High Impedance Test Systems)
TIMING LEVELS
3200
Input Levels: .45 and 2.4V
2.0Wo---V-1
Reference Levels: .8 and 2.0V
D.U.T·~100PF
I-=-
(INCWDING SCOPE
AND JIG
CAPACITANCE)
-------------------------------------r~jf~~------------------------------------3-31
iiiiiijII';jiji.-. . .
WS27C128F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 +-
5°C, Vee = 5.5V +
- 5%, Vpp
PARAMETER
SYMBOLS
MIN
MAX
UNIT
ILl
-10
10
IlA
30
mA
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During __
Programming Pulse (CE = PGM
Ipp
= VIU
Vee Supply Current
lee
VIL
V IH
Input Low Level
Input High Level
Output Low Voltage During Verify
(lOL = 4 mA)
VOL
Output High Voltage During Verify
(loH = -1 mA)
VOH
NOTES:
12.5 +
- 0.5V)
50
mA
-0.1
0.8
V
2.0
Vee +0.3
V
0.45
V
2.4
V
6. Vee must be applied either cOincidentally or before Vpp and removed either coincidentally or after Vpp .
7. Vpp must not be greater than 14 volts including overshoot. During CE = PGM = V,L, Vpp must not be sWitched from 5 volts
to 12.5 volts or vice-versa.
8. During power up the PGM pin must be brought high (",v, H) either coincident with or before power is applied to Vpp .
AC CHARACTERISTICS
(TA
= 25 +-
= 5.5V +-
5°C, Vee
PARAMETER
5%, Vpp
SYMBOLS
= 12.5 +-
MIN
0.5V)
TYP
MAX
UNIT
Address Setup Time
tAS
2
Il s
Chip Enable Setup Time
teES
2
Output Enable Setup Time
tOES
2
Il s
IlS
Data Setup Time
tos
2
Address Hold Time
tAH
0
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tOF
0
Data Valid From Output Enable
tOE
V pp Setup Time
tvs
2
PGM Pulse Width (Note 9)
tpw
1
NOTE:
Il s
Il s
130
Il s
ns
130
ns
IlS
5
ms
9. For single pulse programming algorithms, use one 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
~
~
_lAS DATA
----1
HIGH Z
DATA IN STABLE
-4-los -
/41 0E -
I+IOH -
Vpp
Vpp
CE
VCC~
c=
ADDRESS STABLE
tAH
---
- -
DATA OUT
VALID
1OF
~Ivs-
V1H~
VIL
I- ICES'"
V,H
PGM
V'L
rx,
t
I--Ipw-j
i--IOES
V,H
1
~
DE
VIL
'=~'-Iif
/
-------------------------------------~aFAF~-----------------------------------3-32
WS27C128F
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
PACKAGE
TYPE
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
WS27C128F-90CMB
WS27C128F-900MB
90
90
32 Pad CLLCC
28 Pin CEROIP, 0.6"
C2
02
Military
Military
MIL-STO-883C
MIL-STO-883C
"i=.Ji!!.~
---------------------------------~.,g-------------------------------3-33
~~---------------------------r;I~~------------------------------3-34
. . ._ -
=====.=~
--.... --'=_i-~i-;'-= ==
----
WS27C128L
~~
WAFERSCALE INTEGRATION, INC.
16K x 8 CMOS EPROM
KEY FEATURES
• High Performance CMOS
-
• 300 Mil Dip or Standard 600 Mil Dip
90 ns Access Time
• EPI Processing
• Fast Programming
• Drop-In Replacement for 27C128 or 27128
• DESC SMD No. 5962-87661
-
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000V
• Standard JEDEC EPROM Pinout
GENERAL DESCRIPTION
The WS27C128L is a HIGH PERFORMANCE 128K UV Erasable Electrically Programmable Read Only Memory. It
is manufactured in WSl's latest CMOS EPROM technology which enables it to operate at speeds as fast as 90 ns
access time over the full operating range. (If faster speeds are required, contact your WSI sales representative.)
The WS27C128L can directly replace any 16K x 8 EPROM which conforms to the JEDEC standard. Examples of
this would be as follows: 27128 or 27C128. It can be easily programmed using standard EPROM programmers or
the MagicPro™ IBM PC compatible engineering programmer offered by WSI.
The WS27C128L is also available in a 300 mil Dip. The pin configuration remains the same as the 600 mil wide package
and the programming algorithms are unchanged. This allows for a Simple PCB layout change to take advantage of
a 50% reduction in required board space.
The WS27C128L provides microprocessor-based systems storage capacity for portions of operating system and
application software. Its 90-ns access time provides no-wait-state operation with high-performance CPUs such as
the 16-MHz 80186, 16-MHz 68020, or 12-MHz 80386. The WS27C128L offers a Single chip solution for the code storage
requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from EPROM
storage, greatly enhancing system utility.
The WS27C128L is configured in the standard EPROM pinout which provides an easy upgrade path for systems which
are currently using standard EPROMs.
The WS27C128L is one member of a high density EPROM Family which ranges in density from 64K to 4 Megabit.
PRODUCT SELECTION GUIDE
27C128L-90
27C128L-12
27C128L-15
27C128L-20
Address Access Time (Max)
PARAMETER
90 ns
120 ns
150 ns
200 ns
Chip Select Time (Max)
90 ns
120 ns
150 ns
200 ns
Output Enable Time (Max)
30 ns
35 ns
40 ns
40 ns
3-35
WS27C128L
ABSOLUTE MAXIMUM RATINGS·
"Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to + 150°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vee Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ....................... > 2000V
OPERATING RANGE
RANGE
Commercial
TEMPERATURE
Vcc
TOLERANCE
±5% or ±10%
O°C to +70°C
+5V
Industrial
-40°C to +85°C
+5V
±10%
Military
-55°C to +125°C
+5V
+10%
DC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
MIN
MAX
UNITS
VIL
Input Low Level
-0.5
0.8
V
V IH
Input High Level
2.0
V
VOL
Output Low Voltage
10L = 2.1 mA
Vee + 1
0.4
VOH
IS81(3)
Output High Voltage
100
IS82
Vee Standby Current
J..lA
mA
SYMBOL
TEST CONDITIONS
PARAMETER
lee(1)
Vee Active Current
10H = -400 J..lA
CE = Vee + 0.3V
CE = V IH
_
_
IF=5MHz
CE = OE = VIL F = 8 MHz
Ipp
Vpp Supply Current
Vpp = Vee
Vpp
Vpp Read Voltage
Vee Standby Current (CMOS)
III
Input Load Current
ILO
Output Leakage Current
3.5
V
1
40
I
VIN = 5.5V or Gnd
V OUT = 5.5V or Gnd
V
50
100
Vee -0.4
-1
Vee
1
-10
10
mA
J..lA
V
J..LA
J..lA
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
SYMBOL
PARAMETER
27C128L-90
MIN
MAX
27C128L-12
MIN
MAX
27C128L-15
27C128L-20
MIN
MIN
MAX
MAX
tAee
Address to Output
Delay
90
120
150
200
teE
CE to Output Delay
90
120
150
200
tOE
OE to Output Delay
30
35
40
40
tDF(2)
Output Disable to
Output Float
30
35
40
40
tOH(2)
Output Hold From
Addresses, CE or
OE, Whichever
Occurred First
UNITS
ns
0
0
0
0
NOTES:
1. The supply current is the sum of lee and Ipp. The maximum current value is with Outputs 0 0 to 0 7 unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven-see timing diagram.
3. eMOS Inputs: V,L = GND ± 0.3V, V ,H = Vee ± 0.3V.
----------------------------------~~~---------------------------------3-36
WS27C128L
A.C. WAVEFORMS
V,H
-----_
ADDRESS
VALID
ADDRESSES
--------1~---"""
~----
I ACC
CAPACITANCE(4) TA
HIGH Z
-
Z _____
__
OUTPUT _ _ _ _ _ _HIGH
----..J
<
V,H
+
-------~"'"
~
V,H
~
------
+
V,L
25°C, f = 1 MHz
SYMBOL
PARAMETER
CONDITIONS
CIN
Input Capacitance
COUT
Output Capacitance
VOUT
CvPp
V pp Capacitance
Vpp
VIN
= OV
= OV
= OV
TYP(5)
MAX
UNITS
4
6
pF
8
12
pF
18
25
pF
NOTES:
4. This parameter is only sampled and IS not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages.
6. OE may be delayed up to tCE-t OE after the falling edge of CE without impact on tCE '
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.D1V
"'T""
2.4
>
2.0
TEST POINTS
0.8
<-
~
2.D
0.8
0.4
DEVICE
UNDER
TEST
:>»
I
8200
CL
= lDDpF
--
A.C. testing inputs are driven at 2.4V for a Logic "1" and
0.4V for a Logic "0:' Timing measurements are made at 2.0V
for a Logic "1" and O.SV for a Logic "0."
CL includes Jig Capacitance
-----------------------~Jr;-----------------------3-37
WS27C128L
MODE SELECTION
The modes of operation of the WS27C128L are listed in Table 1. A single SV power supply is required in the read mode.
Table 1. Modes Selection
~
--
-
PGM
CE
OE
Vpp
vee
OUTPUTS
MODE
Read
X
VIL
S.OV
X
X
VIL
VIH
S.OV
Output Disable
S.OV
S.OV
DOUT
High Z
Standby
X
VIH
X
S.OV
S.OV
High Z
VIH
VIL
Vpp
S.8V
DIN
Vpp
S.8V
X
V pp
S.OV
DOUT
High Z
Programming
Program Verify
VIL
VIH
Program Inhibit
X
VIL
VIL
VIH
NOTES:
7. X can be VIL or VIH •
DIP PIN CONFIGURATIONS
8 Mbil
4 Mbil
2 Mbil
27C010L 27C512L
A'9
A,s
A,s
A,.
A7
As
As
A4
A3
A.
A,
Ao
XXNpp
XXlVpp
XXNpp
A'6
A,s
A,.
A7
As
As
A4
A3
A2
A,
A'6
A,s
A,.
A7
As
As
A4
A3
A.
A,
Ao
A,s
A,.
A7
As
As
A4
A3
A.
A,
Ao
00
0,
Ao
A'6
A,s
A,.
A7
As
As
A4
A3
A.
A,
Ao
00
0,
00
0,
00
0,
00
0,
O.
GND
O.
GND
O2
GND
O.
GND
O2
GND
NOTE:
27C512L 27C010L
WS27C128L
f-'
f-,
f-
ff-
.1,-
-
-
Vee
A'4
A'3
A~
Ao
f-
-
f- A.
' - OENpp
f- Aa
f- A,
f- Ao
,-
r- o.
f- 0,
r- O.
GNO
-
-
---
Al1
A,o
CElPGM
07
Os
Os
04
03
2 Mbll
4 Mbil
8 Mbll
Vcc
Vcc
Vcc
Vcc
XXlPGM XX/PGM
A,s
A,s
XX
A'7
A'7
A'7
A'4
A'4
A'4
A'4
A'3
A'3
A'3
A'3
As
As
As
As
As
A9
As
As
Al1
Al1
Al1
Al1
OElVpp
OE
OE
OE
A,o
A,o
A,o
A,o
CE
CE
CElPGM eE/PGM
07
07
07
07
Os
0&
0&
0&
Os
Os
Os
Os
04
04
04
04
03
03
03
03
8. Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C128L pins,
PIN NAMES
LeC PIN CONFIGURATION
Addresses
CE
Chip Enable
OE
Output Enable
Outputs
PGM
Program
xx
Don't Care (During Read)
TOP
NOTE: Leadless or
Leaded, Plastic or
Ceramic Package
-----------------------~Jr;~---------------------
3-38
WS27C128L
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA
= 25
± 5°C, Vee
PARAMETER
5.8V ± 0.25V, Vpp
SYMBOLS
MIN
MAX
UNIT
III
-10
10
~A
60
mA
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During
Programming Pulse (CE, PGM
12.75 ± 0.25V)
Ipp
= VILl
Vee Supply Current
lee
40
mA
Input Low Level
V 1L
-0.1
0.8
V
2.0
Vee +0.3
V
0.4
V
Input High Level
V 1H
Output Low Voltage During Verify
(IOL = 2.1 mA)
VOL
Output High Voltage During Verify
(IOH = -400 ~A)
V OH
NOTES:
3.5
V
9. Vee must be applied either cOincidentally or before Vpp and removed either coincidentally or after Vpp .
10. Vpp must not be greater than 14 volts Including overshoot. Dunng CE, PGM = V ,L , Vpp must not be switched from 5 volts to
12.75 volts or vice-versa.
11. Dunng power up the PGM pin must be brought high (;;>V ,H ) either cOincident with or before power IS applied to Vpp .
AC CHARACTERISTICS (TA
= 25
PARAMETER
± 5°C, Vcc
= 5.8V
± 0.25V, Vpp
= 12.75
MIN
Address Setup Time
tAS
2
Jls
Chip Enable Setup Time
tCES
2
JlS
Output Enable Setup Time
tOES
tos
2
Jls
Data Setup Time
2
JlS
Address Hold Time
tAH
0
JlS
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
Data Valid From Output Enable
tOE
TYP
± 0.25V)
SYMBOLS
MAX
130
130
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
0.1
UNIT
Jls
ns
ns
Jls
4
ms
PROGRAMMING WAVEFORM
ADDRESSES
DATA
v ••
v ••
Vee
V,H
CE
V"
V,H
PGM
V"
V,H
OE
V"
-------------------------------------rjfAr~~--------------------------------------3-39
WS27C128L
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS27C128L-90D/5
WS27C128L-12D
WS27C128L-12DI
WS27C128L-12DMB
WS27C128L-12J
WS27C128L-12P
WS27C128L-12T
WS27C128L-12T1
WS27C128L-12TMB
WS27C128L-15D
WS27C128L-15DMB
WS27C128L-15TMB
WS27C128L-20DMB
WS27C128L-20TMB
90
120
120
120
120
120
120
120
120
150
150
150
200
200
PACKAGE
TYPE
28
28
28
28
32
28
28
28
28
28
28
28
28
28
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
CERDIP, 0.6"
CERDIP, 0.6"
CERDIP, 0.6"
CERDIp, 0.6"
PLDCC
Plastic DIP, 0.6"
CERDIp, 0.3"
CERDIp, 0.3"
CERDIp, 0.3"
CERDIp, 0.6"
CERDIp, 0.6"
CERDIp, 0.3"
CERDIp, 0.6"
CERDIp, 0.3"
PACKAGE
DRAWING
D2
D2
D2
D2
J4
P3
T2
T2
T2
D2
D2
T2
D2
T2
OPERATING
RANGE
TEMPERATURE Vcc
Comm'l
Comm'l
Industrial
Military
Comm'l
Comm'l
Comm'l
Industrial
Military
Comm'l
Military
Military
Military
Military
±5%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
WSI
MANUFACTURING
PROCEDURE
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
MIL-STD-883C
MIL-STD-883C
MIL-STD-883C
MIL-STD-883C
--------------------------~Jr;-------------------------3-40
~~~~~~~~
-~------~
WS57C128F
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 16K x 8 CMOS EPROM
KEY FEATURES
• Fast Access Time
-
• EPI Processing
55 ns
-
Latch-Up Immunity Up to 200 mA
• Low Power Consumption
• Standard EPROM Pinout
• OESC SMO No. 5962-87661
• Bipolar Speeds
GENERAL DESCRIPTION
The WS57C128F is an extremely HIGH PERFORMANCE 128K UV Erasable Electrically Programmable Read
Only Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar speeds
while consuming only 60mA.
Two major features of the WS57C128F are its Low Power and High Speed. These features make it an ideal
solution for applications which require fast access times, low power, and non-volatility. Typical applications
include systems which do not utilize mass storage devices and/or are board space limited. Examples of these
applications are modems, secure telephones, servo controllers, and industrial controllers.
The WS57C128F is configured in the standard EPROM pinout which provides an easy upgrade path for systems
which are currently using standard EPROMs.
MODE SELECTION
PIN CONFIGURATION
TOP VIEW
~
MODE
Read
vpp
PGM
CE
OE
X
VIL
VIL 5.0V 5.0V
vee
Chip Carrier
OUTPUTS
"'" ~ 8:0 81~ ~
«>Z>II.<
DouT
:0:::
""",
Output
Disable
X
X
Standby
X
VIH
Vpp
5.8V
DIN
VIH 5.0V 5.0V
High Z
5.0V 5.0V
High Z
Programming
VIL
VIH
VIL
Program
Verify
VIH
VIL
VIL
Vpp
5.8V
DOUT
Program
Inhibit
X
VIH
X
Vpp
5.0V
High Z
X
1",
II'
4-' 3-' '2-'LJS23130
A.
A.
A.
A,
A.
A,
A.
NC
X ean be V1L or V1H •
CERDIP
0.
5
1
29,: As
As
A"
S
26 [= NC
9
25[: OE
10
24C: A,.
11
23[:
12
22 [: 0 7
13
21 ~: 0.
14151617181920
r.,
,....,
"""""'''"1''''''''
'"
1101 " "
II I
CE
0,0, INC 0,0.0.
r--v-vppC 1
28 PVee
A,.~ 2
27 PPGM
A;~ 3
26 ~A"
As~4
25BAs
A.[5
24pA9
A.,~
6 023~A"
A,~ 7
22 QOE
A.[8
21QA,.
A,[ 9
20
A.[ 10
19 ~ 0 7
o.~ 11
18 0.
0, [ 12
17 po.
0.[ 13
16 gO.
GND[ 14
15
PCE
B
po,
GND
PRODUCT SELECTION GUIDE
PARAMETER
WS57C128F-55
WS57C128F-70
Address Access Time (Max)
55ns
70ns
Chip Select Time (Max)
55ns
70ns
Output Enable Time (Max)
25ns
25ns
3-41
WS57C128F
ABSOWTE MAXIMUM RATINGS·
"Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ............ -65° to +150°C
Voltage on Any Pin with
Respect to GND ................ -0.6V to +7V
Vpp with Respect to GND ......... -0.6V to +14V
ESD Protection ........................ >2000V
OPERATING RANGE
RANGE
Comm'l
TEMPERATURE
Vcc
0° to +70°C
+5V
Industrial
- 40° to + 85°C
+5V
Military
-55° to +125°C
+5V
± 5%
± 10%
± 10%
= Vee.
DC READ CHARACTERISTICS Over Operating Range with Vpp
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
= 16 mA
= -4 mA
MAX
UNITS
0.4
V
VOL
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
IS81
Vee Standby Current (CMOS)
Notes 1 and 3
500
J.lA
ISB2
Vee Standby Current (TTL)
Notes 2 and 3
20
mA
lec1
Active Current (CMOS)
Notes 1 and 4
lec2
Vee Active Current (TTL)
Ipp
Vpp Supply Current
Vpp
Vpp Read Voltage
III
Input Load Current
Notes 2 and 4
Vpp
2. TTL inputs: V1L
"
O.8V, V1H
~
Comm'l
25
Military
30
Comm'l
35
Military
40
= Vce
100
J.lA
V
-10
10
-10
10
J.tA
J.tA
3. Add 1 rnA/MHz for A.C. power component.
4. Add 3 rnA/MHz for A.C. power component.
AC READ CHARACTERISTICS Over Operating Range with Vpp
PARAMETER
SYMBOL
= Vec.
WS57C128F-55
WS57C128F-70
MIN
MIN
MAX
MAX
tAce
55
70
CE to Output Delay
teE
55
70
OE to Output Delay
tOE
25
Output Disable to Output Float
tOF
25
Address to Output Hold
tOH
Address to Output Delay
mA
Vec
= 5.5V or Gnd
VO UT = 5.5V or Gnd
2.0V.
mA
Vec - 0.4
VIN
Output Leakage Current
ILO
NOTES: 1. CMOS inputs: GND ± O.3V or Vee ± O.3V.
V
2.4
10
25
0
UNITS
ns
25
10
------------------------~Jr;~----------------------3-42
~-~----~
-~-
-----
WS57C128F
AC READ TIMING DIAGRAM
ADDRESSES
CE ------..
OE------------~
OUTPUTS---------4~r_;wot"i~+_-
CAPACITANCEl5)
SYMBOL
TA = 25°C, f = 1 MHz
PARAMETER
C IN
Input Capacitance
CO UT
Output Capacitance
CvPp
Vpp Capacitance
NOTES:
CONDITIONS
TYP(6)
MAX
UNITS
= OV
VO UT = OV
Vpp = OV
4
6
pF
8
12
pF
18
25
pF
V IN
5. This parameter is only sampled and is not 1000/0 tested.
6. Typical values are for T A = 25°C and nominal supply voltages.
TEST WAD
(High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0 and 3V
97.50
2.01V~
Reference Levels: 0.8 and 2.0V
D.U.T·~30PF
I=
(INCWDING SCOPE
AND JIG
CAPACITANCE)
-----------------------~Jri----------------------3-43
WS57C128F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee
PARAMETER
5.5V ± 5%, Vpp
SYMBOLS
MIN
MAX
UNIT
III
-10
10
J.lA
60
rnA
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During
Programming Pulse (CE = PGM
Ipp
= Vld
Vee Supply Current
lee
V IL
V IH
Input Low Level
Input High Level
Output Low Voltage During Verify
(lOL = 16 rnA)
VOL
Output High Voltage During Verify
(lOH = -4 rnA)
VOH
NOTES:
13.5 ± 0.5V)
30
rnA
-0.1
0.8
V
2.0
Vee +0.3
V
0.45
V
2.4
V
7 Vee must be applied either cOincidentally or before Vpp and removed either cOincidentally or after Vpp.
8. Vpp must not be greater than 14 volts Including overshoot. During CE = PGM = V'L' Vpp must not be sWitched from 5 volts
to 13.5 volts or vice-versa.
9. During power up the PGM pin must be brought high (;;>V ,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
SYMBOLS
MIN
Address Setup Time
tAS
2
J.lS
Chip Enable Setup Time
teEs
2
J.ls
Output Enable Setup Time
tOES
2
J.ls
Data Setup Time
tos
2
J.ls
Address Hold Time
tAH
0
J.lS
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
Data Valid From Output Enable
tOE
PARAMETER
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
TYP
MAX
UNIT
J.lS
130
ns
130
ns
10
ms
J.ls
3
NOTE: Single shot programming algOrithms should use a single 10 ms pulse.
PROGRAMMING WA VEFORM
ADDRESSES
~
ADDRESS STABLE
_'AS ..
DATA
-----1
I
HIGH Z
DATA IN STABLE
"-'os-
i4-
"'oE
V••
v ••
Vee
CE
------.I
-l
tAH
-
K=
I+-
~
'0' l -
4-- 'vs'"
VIH~
VOl
,H
V
PGM
VOl
,H
V
r-- 'CES'"
~
--'DES
VOl
___________________________
1
"l
OE
~~
X
"-
'OH-
--1
DATA OUT
VALID
J
fll~:---------------------------
~.
WS57C128F
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C128F-550
WS57C128F-70CI
WS57C128F-70CMB
WS57C128F-700
WS57C128F-7001
WS57C128F-700MB
55
70
70
70
70
70
PACKAGE
TYPE
28
32
32
28
28
28
Pin CEROIp,
Pad CLLCC
Pad CLLCC
Pin CEROIP,
Pin CEROIp,
Pin CEROIp,
0.6"
0.6"
0.6"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
02
C2
C2
02
02
02
Comm'l
Industrial
Military
Comm'l
Industrial
Military
Standard
Standard
MIL-STO-883C
Standard
Standard
MIL-STO-883C
---------------------------------~~~--------------------------------3-45
: - : : -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ F§§
3-46
-~
~~~ ----------------------------------------------
WAFERSCALE INTEGRATION, INC.
256K EPROM SELECTION GUIDE
ARCHITECTURE
I
16Kx 16
WS57C257
I
===1
I
32Kx8
WS27C256F
I
32Kx8
WS27C256F
32Kx8
32Kx8
WS27C256L
I
I
II
I
I
I
WS57C256F
I
I
I
I
!
I
I
I
ACCESS TIME (ns)
3-47
~34=8----------------------~Jri------------------------
iFEE ~---._-l:::""":e-==:e-s;-= E
---~
WS27C256F
~-'
PRELIMINARY
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 32K x 8 CMOS EPROM
KEY FEATURES
• EPI Processing
• Fast Access Time
-
-
45 ns
• Low Power Consumption
• DESC SMD No. 5962-86063
Latch-Up Immunity Up to 200 mA
ESD Protection Exceeds 2000V
• Standard EPROM Pinout
GENERAL DESCRIPTION
The WS27C256F is a 32K x 8 CMOS EPROM which has been speed-enhanced to 45 ns. It is based upon WaferScale's
patented CMOS Split Gate EPROM technology.
The 45 ns access time of the WS27C256F is a key parameter. Traditionally, as memory densities Increase, memory
access times become slower. This forces microprocessors to insert Wait States which negatively impact system
throughput. Real Time applications cannot afford Wait States regardless of memory density. WSI's unique memories
can keep pace with the fastest microprocessors. The combination of speed and density available in the WS27C256F
enables the use of more complex and comprehensive algorithms in real time applications.
WSI's patented CMOS Split-Gate EPROM technology not only enables the development of fast and dense memory
products, it also provides a higher level of Quality and Reliability. Tests have proven that WSI EPROM products program
very efficiently and quickly. Also, the WSI EPROM retains its data an order of magnitude better than traditional EPROM
technologies. This combination of speed, density, quality and reliability make WSI the obvious choice when selecting
a non-volatile memory supplier.
The WS27C256F is configured in the JEDEC standard EPROM pin configuration. It is also easily programmed on
popular EPROM programmers as well as the MaglcPro™ IBM PC compatible engineering programmer offered
byWSI.
PIN CONFIGURATION
MODE SELECTION
~
MODE
Read
Output Disable
Standby
CEI
PGM
VIL
VIL Vce Vee
X
V IH Vee Vee
VIH
Program
V IL
Program Verify
Program Inhibit
Signature'
OE V pp Vcc OUTPUTS
X
V IH
V IL
X
Vee Vee
V IH V pp Vee
V IL Vpp Vee
DOUT
High Z
High Z
DIN
VIH V pp Vee
DouT
High Z
VIL Vee Vee
Encoded
Data
X can be either V 1L or V 1H .
"For Signature, A;, = 12V, Ao is toggled, and all other addresses are
at TTL low. Ao = V 1L = MFGR 23H, Ao = V 1H = DEVICE EOH.
TOP VIEW
Chip Carrier
028,:
" " , 'I I ' " ' ' ,
A6
~~ 5
As :;6
A4 =~ 7
A3
A2
A1
Ao
NC
00
4~ 3~
2-' LJ 323130
1
29
[=
CERDIP
A12
A7
Ag
27 C= A11
=J 8
26 C= NC
=~ 9
25 C= OE
=~ 10
24 C= A10
:; 11
23,: CE/PGM
:~ 12
22,: 07
:~ 13
21,: 0.
14151617181920
.....
NCO
(")
~
vee
Vpp
As
Ltl
OOzzOOO
Cl
A.
As
A.
A3
A2
3
A14
A13
As
Ag
Al1
OE
A"
CE/PGM
°7
0.
Os
0•
"1..:,;~_;.;;...r-03
PRODUCT SELECTION GUIDE
PARAMETER
WS27C256F-45
WS27C256F-55
WS27C256F-70
WS27C256F-90
Address Access Time (Max)
45 ns
55 ns
70 ns
90 ns
Chip Select Time (Max)
45 ns
55 ns
70 ns
90 ns
Output Enable Time (Max)
25 ns
25 ns
30 ns
30 ns
3-49
WS27C256F
"Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those- indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
ABSOWTE MAXIMUM RATINGS
Storage Temperature ............. -65° to + 150°C
Voltage on Any Pin with
Respect to GND ................. -0.6V to +7V
Vpp with respect to GND ........... -0.6V to +13V
ESD Protection ......................... >2000V
OPERATING RANGE
TEMPERATURE
Vcc
Comm'l
O°C to +70°C
+5V + 5%
Military
-55°C to +125°C
+5V ± 10%
RANGE
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range with Vpp = Vcc.
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
ISBI
Vcc Standby Current CMOS
CE
ISB2
Vcc Standby Current TTL
Vcc Active Current(3)
Ipp
Vpp Supply Current
Vpp
Vpp Read Voltage
III
Input Load Current
ILO
Output Leakage Current
= 5.5V or Gnd
VOUT = 5J5V or Gnd
AC READ CHARACTERISTICS
PARAMETER
Address to Output Delay
3. Add 3
0.4
V
500
~
5
mA
30
mA
40
mA
100
~
Vcc - 0.4
Vcc
V
-10
10
~
-10
10
~
= Vcc
V1N
1. CMOS inputs: GND ± 0.'311 or Vee ± 0.'311.
2. TTL inputs: V1L ., o.av, V1H '" 2.0V.
UNITS
V
1)
Military
Vpp
MAX
2.4
Commercial
ICCI
NOTES:
CE
= 2.1 mA
= -400 ~
= Vcc + 0.3V (Note
= VIH (Note 2)
MIN
rnA/MHz for A.C. power component.
Over Operating Range with Vpp = Vcc.
SYMBOL
27C256F-45
MIN
MAX
27C256F-55
27C256F-70
27C256F-90
MIN
MIN
MIN
MAX
MAX
MAX
tACC
45
55
70
90
CE to Output Delay
tCE
45
55
70
90
OE to Output Delay
tOE
25
25
30
30
Output Disable to Output Float
tDF
Address to Output Hold
tOH
25
0
25
0
30
0
UNITS
ns
30
0
------------------------~Jr;,---------------------3-50
WS27C256F
AC READ TIMING DIAGRAM
ADDRESSES
CE------...
OE------------,
OUTPUTS---------~$~~t~~--
CAPACITANCf(4) TA
SYMBOL
= 25°C, f = 1 MHz
PARAMETER
CIN
Input Capacitance
COUT
CvPp
Output Capacitance
Vpp Capacitance
CONDITIONS
TYP(5)
MAX
UNITS
= OV
VOUT = OV
Vpp = OV
4
6
pF
8
12
pF
18
25
pF
VIN
NOTES: 4. This parameter is only sampled and is not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages.
TEST WAD (High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0.45 and 2.4V
2.01V~
D.U.T.
<>----i
I=
Reference Levels: 0.8 and 2.OV
100 pF
(INCWDING SCOPE
AND JIG
CAPACITANCE)
--------------------~~i'-------------------3·51
WS27C256F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ±
5.5V ± 5%, Vpp
5°C, Vee
PARAMETER
SYMBOLS
MIN
MAX
UNIT
III
-10
10
~A
60
rnA
Input Leakage Current
(VIN = Vee or Gnd)
Vee Supply Current During__
Programming Pulse (CE/PGM
Icc
= Vld
Vec Supply Current
Icc
V IL
VIH
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL = 16 rnA)
VOL
Output High Voltage During Verify
(loH = -4 rnA)
VOH
NOTES:
12.5 ± 0.5V)
35
rnA
-0.1
0.8
V
2.0
Vee +0.3
V
0.45
V
2.4
V
6. Vee must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp .
7. Vpp must not be greater than 14 volts including overshoot. During CE/PGM = V ,L, Vpp must not be switched from 5 volts
to 12.5 volts or vice-versa.
B. During power up the CE/PGM pin must be brought high (;>V ,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS
(TA
= 25 ±
5°C, Vee
PARAMETER
= 5.5V ±
5%, Vpp
= 12.5 ±
MIN
Address Setup Time
tAS
2
~s
CE High to OE High
teoH
2
~s
Output Enable Setup Time
tOES
2
~s
Data Setup Time
tos
2
~s
Address Hold Time
tAH
0
~s
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tOF
0
Data Valid From Output Enable
tOE
Vpp Setup Time/CE Setup Time
tvs/tCES
2
PGM Pulse Width
tpw
1
OE Low to CE "Don't Care"
toex
2
NOTE:
These values are for standard programming -
TYP
0.5V)
SYMBOLS
MAX
UNIT
~s
130
ns
130
ns
10
ms
~s
3
~s
actual programming algorithm may use different limitations.
PROGRAMMING WAVEFORM
ADDRESSES
DATA
V••
v••
Vee
V,H
CE/PGM
V IL
V,H
CE
VIL
-------------------~Jri~--------------------
3-52
WS27C256F
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
WS27C256F-450 *
WS27C256F-550
WS27C256F-700
WS27C256F-700MB
WS27C256F-90CMB
WS27C256F-900MB
WS27C256F-90LMB
SPEED
PACKAGE
TYPE
(ns)
45
55
70
70
90
90
90
28
28
28
28
32
28
32
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pin CERDIp,
Pin CLOCC
0.6"
0.6"
0.6"
0.6"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
02
02
02
02
C2
02
L3
Comm'l
Comm'l
Comm'l
Military
Military
Military
Military
Standard
Standard
Standard
MIL-STO-883C
M IL-STO-883C
M IL-STO-883C
MIL-STO-883C
*This product is Advance Information.
--------------------~~i-------------------3-53
~3_5~4----------------------~Jri------------------------
--
iF==:=~
-~- ~
--- - - -==
.~~
~ ~..I/IIIJ:
r
WS27C256L
~~
WAFERSCALE INTEGRATION, INC.
32K
X
8 CMOS EPROM
KEY FEATURES
• High Performance CMOS
-
• 300 Mil Dip or Standard 600 Mil Dip
90 ns Access Time
• EPI Processing
• Fast Programming
• Drop-In Replacement for 27C256 or 27256
• DESC SMD No. 5962-86063
-
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000V
• Standard JEDEC EPROM Pinout
GENERAL DESCRIPTION
The WS27C256L is a HIGH PERFORMANCE 256K UV Erasable Electrically Programmable Read Only Memory. It
is manufactured in WSI's latest CMOS EPROM technology which enables it to operate at speeds as fast as 90 ns
access time over the full operating range. (If faster speeds are required, contact your WSI sales representative.)
The WS27C256L can directly replace any 32K x 8 EPROM which conforms to the JEDEC standard. Examples of
this would be as follows: 27256, 27C256, or 27C256F. It can be easily programmed using standard EPROM programmers
or the MagicPro™ IBM PC compatible engineering programmer offered by WSI.
The WS27C256L is also available in a 300 mil Dip. The pin configuration remains the same as the 600 mil wide package
and the programming algorithms are unchanged. This allows for a simple PCB layout change to take advantage of
a 50% reduction in required board space. An upgrade path to a 512K product (WS27C512L) is provided.
The WS27C256L provides microprocessor-based systems extensive storage capacity for large portions of operating
system and application software. Its 90-ns access time provides no-wait-state operation with high-performance CPUs
such as the 16-MHz 80186, 16-MHz 68020, or 12-MHz 80386. The WS27C256L offers a single chip solution for the
code storage requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed
from EPROM storage, greatly enhancing system utility.
The WS27C256L is configured in the standard EPROM pinout which provides an easy upgrade path for systems which
are currently using standard EPROMs.
The WS27C256L is one member of a high-density EPROM Family which ranges in density from 64K to 4 Megabit.
PRODUCT SELECTION GUIDE
PARAMETER
27C256L-90
27C256L·12
27C256L·15
27C256L·20
Address Access Time (Max)
90 ns
120 ns
150 ns
200 ns
Chip Select Time (Max)
90 ns
120 ns
150 ns
200 ns
Output Enable Time (Max)
30 ns
35 ns
40 ns
40 ns
3-55
WS27C256L
ABSOWTE MAXIMUM RATINGS*
"Notice: Stresses above those listed under ''Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to +150o C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vee Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ....................... > 2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vee
TOLERANCE
Commercial
O°C to +70°C
+5V
±5% or ±10%
Industrial
-40°C to +85°C
+5V
±10%
Military
-55°C to +125°C
+5V
+10%
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range with Vpp = Vee.
PARAMETER
TEST CONDITIONS
MIN
VIL
Input Low Level
VIH
Input High Level
VOL
VOH
1581 (3)
Output Low Voltage
IOL = 2.1 mA
Output High Voltage
IOH = -400 J.tA
Vee Standby Current (CMOS)
IS82
Vee Standby Current
lee(l)
Vee Active Current
CE = Vee + 0.3V
CE = VIH
_
_
IF=5MHz
CE = OE = V IL F = 8 MHz
Ipp
Vpp Supply Current
Vpp = Vee
Vpp
Vpp Read Voltage
Input Load Current
ILO
Output Leakage Current
SYMBOL
PARAMETER
UNITS
-0.5
0.8
V
2.0
Vee + 1
0.4
V
3.5
VIN = 5.5V or Gnd
VOUT = 5.5V or Gnd
V
V
100
1
40
I
III
AC READ CHARACTERISTICS
MAX
50
100
Vee -0.4
-1
Vee
1
-10
10
J.tA
mA
mA
J.tA
V
J.tA
J.tA
Over Operating Range with Vpp = Vee.
27C256L·90
MIN
MAX
27C256L·12
MIN
MAX
27C256L·15
MIN
MAX
27C256L·20
MIN
MAX
tAee
Address to Output
Delay
90
120
150
200
teE
CE to Output Delay
90
120
150
200
tOE
OE to Output Delay
30
35
40
40
tDF(2)
Output Disable to
Output Float
30
35
40
40
tOH(2)
Output Hold From
Addresses, CE or
OE, Whichever
Occurred First
UNITS
ns
0
0
0
0
NOTES:
1. The supply current is the sum of lee and Ipp. The maximum current value is with Outputs 0 0 to 0 7 unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven-see timing diagram.
3. CMOS inputs: V1L = GND ± 0.3V, V 1H = Vee ± 0.3V.
------------------------~Jr;-----------------------3-56
WS27C256L
A.C. WAVEFORMS
V,H
-----_
ADDRESS
VALID
ADDRESSES
V ,L
------
V,H
------"""i-""\
V,H
-------!----I
(4)
DF
14----- I ACC - - - - . I
HIGH Z
OUTPUT -------------+M~+_<
CAPACITANCE(4)
TA
SYMBOL
25°C, f
HIGH Z
1 MHz
PARAMETER
C IN
Input Capacitance
COUT
Output Capacitance
CvPp
Vpp Capacitance
CONDITIONS
Typ(5)
MAX
UNITS
= OV
VO UT = OV
Vpp = OV
4
6
pF
8
12
pF
18
25
pF
VIN
NOTES:
4 This parameter IS only sampled and IS not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages
6. OE may be delayed up to tCE-tOE after the failing edge of CE without Impact on tCE '
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.01V
-r2.4
2~
;>
0.8
~
2~
~
TEST POINTS (
0.8
0.4
8200
DEVICE
UNDER
TEST
....... CL = 100 pF
I-
-
A.C. testing Inputs are driven at 2.4V for a Logic "1" and
0.4 V for a LogiC "0" Timing measurements are made at 2 DV
for a Logic "1" and D.BV for a Logic "0."
C L Includes Jig Capacitance
---------------------rAr~~~~-------------------!!!!!!!!'&'..---.
3-57
WS27C256L
MODE SELECTION
The modes of operation of the WS27C256L are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for Vpp and A9 for device signature.
::----------::
Table 1. Modes Selection
--CE/PGM
OE
A9
Ao
Vpp
Vcc
OUTPUTS
V IL
V IL
Vee
5.0V
DOUT
X
V IH
X
X
X
X
X
Vee
5.0V
High Z
Vee
Vp p(8)
5.0V
High Z
5.SV
DIN
Vp p(8)
5.SV
DOUT
MODE
Standby
V IH
X
Programming
V IL
V IH
Program Verify
X
V IL
X
X
X
X
X
Program Inhibit
V IH
V IH
X
X
Vpp(8)
5.0V
High Z
V IL
V IL
V H(8)
V IL
Vee
5.0V
23 H
V IL
VH(8)
V IH
Vee
5.0V
CO H
Read
Output Disable
Signature
Manufacturer(9)
Device(9)
V IL
NOTES:
7. X can be V1L or V1H •
8. VH = Vpp = 12.75 ± O.25V.
DIP PIN CONFIGURATIONS
8 Mbit
4 Mbit
2 Mbit
A 1S
A 16
A 1S
A12
A7
A6
As
A4
A3
A2
Al
AD
Oo
01
O2
GND
XX/V pp
A 16
A1S
A12
A7
A6
As
A4
A3
A2
Al
AD
00
01
O2
GND
XX/V pp
A16
A1S
A12
A7
A6
As
A4
A3
A2
Al
AD
00
01
O2
GND
NOTE:
27C010L 27C512L
XX/Vpp
A 16
A 1S
A12
A7
A6
As
A4
A3
A2
Al
AD
00
01
O2
GND
27C512L 27C010L
WS27C256L
A 1S
A12
A7
A6
As
A4
A3
A2
Al
AD
00
01
O2
GND
1-1VPI'
,-
1-,A1,
A14
A 13
As
Ag
All
OE/vpp
A10
IJSGM CE/PGM
07
06
Os
04
03
-
I- A.
I- As
I-
A..
I- A.
I- A,
I- Al
r- A.
I- o.
r- 0 1
11
I- 0,
GNO
4 Mbit
8 Mblt
Vee
Vee
Vee
XX/PGM XX/PGM
A 1S
XX
A17
A17
A14
A14
A14
A 13
A 13
A13
As
As
As
As
As
As
All
All
All
OE
OE
OE
A 10
A 10
A10
CE
CE
CE/PGM
07
07
07
06
06
06
Os
O.
O.
04
04
04
03
03
03
Vee
-
I- A7
2 Mbit
Vee
-
A 1S
A17
A14
A 13
As
As
All
OE/vpp
A 10
CElPGM
07
06
O.
04
03
10. Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C256L pins.
PIN NAMES
LCC PIN CONFIGURATION
,~t,,8
••
• • >z> .. c
Addresses
CE
Chip Enable
OE
Output Enable
~~
As
¥ ~~LJ~4~~~6
0
1
A5
29~: As
28r: As
A,
7
A,
10
25[: DE
24[: A,o
Outputs
Ao
Ne
11
12
23 [: CE/PGM
22:: 0 7
PGM
Program
00
13
21t: 0,
14151617181920
XX
Don't Care (During Read)
A3
A2
8
9
27::Al1
26r: NC
~-;;ir-;~-:~-;~~~-;
0..
f'j
o
Q
0
~..,
on
z zOOO
" TOP
NOTE: Leadless or
Leaded, Plastic or
Ceramic Package
---------------------~Jri--------------------3-58
WS27C256L
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ±
5°C, Vee
5.SV
±
0.25V, Vpp
=
12.75
±
0.25V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
(VIN = Vee or Gnd)
III
-10
10
llA
Vpp Supply Current During_ _
Programming Pulse (CE/PGM = Vld
Ipp
60
mA
PARAMETER
lee
V IL
40
mA
Input Low Level
-0.1
0.8
V
2.0
Vee +0.3
V
0.4
V
Vee Supply Current
Input High Level
V IH
Output Low Voltage During Verify
(lOL = 2.1 mAl
VOL
Output High Voltage During Verify
(loH = -400 llA)
V OH
NOTES:
3.5
V
11. Vee must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp.
12. Vpp must not be greater than 14 volts including overshoot. During CE/PGM = V'L' Vpp must not be switched from 5 volts
to 12.75 volts or vice-versa.
13. During power up the eE/PGM pin must be brought high (~V'H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS
(TA = 25 +
- 5°C, Vee = 5.SV +- 0.25V, Vpp = 12.75 + 0.25V)
-
MAX
TYP
UNIT
SYMBOLS
MIN
Address Setup Time
tAS
2
CE High to OE High
teoH
2
lls
Output Enable Setup Time
tOES
2
lls
lls
PARAMETER
lls
Data Setup Time
tos
2
Address Hold Time
tAH
0
IlS
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
lls
ns
Data Valid From Output Enable
tOE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
0.1
OE Low to CE "Don't Care"
toex
2
55
55
ns
IlS
4
ms
lls
PROGRAMMING WAVEFORM
ADDRESSES
==:x
C
ADDRESS STABLE
----<
DATA IN STABLE
HIGH Z
I - loH .....
I--Ios-
Vee
. 10, -
~Ic.s'"
Iocx-
V,H
V,L
V,H
OE
V'L
IOF
----1
I--I vs -
CEJPGM
tAH
DATA OUT
VALID
Vpp
Vpp
-- ---1
j4-IAS . .
DATA
rx.
-.Ii
~Ipw~
_IOES~
~
-
I - e..
ICOH
~
/
-----------------------~Jr;~---------------------3-59
WS27C256L
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
WS27C256L-90D/5
WS27C256L-90T/5
WS27C256L-12CI
WS27C256L-12CMB
WS27C256L-12D
WS27C256L-12DI
WS27C256L-12DM
WS27C256L-12DMB
WS27C256L-12J
WS27C256L-12L
WS27C256L-12LMB
WS27C256L-12P
WS27C256L-12T
WS27C256L-12T1
WS27C256L-12TMB
WS27C256L-15CI
WS27C256L-15CMB
WS27C256L-15D
WS27C256L-15DMB
WS27C256L-15J
WS27C256L-15L
WS27C256L-15L1
WS27C256L-15LMB
WS27C256L-15P
WS27C256L-20CMB
WS27C256L-20DMB
SPEED
(ns)
PACKAGE
TYPE
PACKAGE
DRAWING
90
90
120
120
120
120
120
120
120
120
120
120
120
120
120
150
150
150
150
150
150
150
150
150
200
200
28 Pin CERDIP, 0.6"
28 Pin CERDIp, 0.3"
32 Pad CLLCC
32 Pad CLLCC
28 Pin CERDIP, 0.6"
28 Pin CERDIP, 0.6"
28 Pin CERDIP, 0.6"
28 Pin CERDIp, 0.6"
32 Pin PLDCC
32 Pin CLDCC
32 Pin CLDCC
28 Pin Plastic DIP, 0.6"
28 Pin CERDIP, 0.3"
28 Pin CERDIp, 0.3"
28 Pin CERDIP, 0.3"
32 Pad CLLCC
32 Pad CLLCC
28 Pin CERDIP, 0.6"
28 Pin CERDIp, 0.6"
32 Pin PLDCC
32 Pin CLDCC
32 Pin CLDCC
32 Pin CLDCC
28 Pin Plastic Dip, 0.6"
32 Pad CLLCC
28 Pin CERDIp, 0.6"
D2
T2
C2
C2
D2
D2
D2
D2
J4
L3
L3
P3
T2
T2
T2
C2
C2
D2
D2
J4
L3
L3
L3
P3
C2
D2
OPERATING
RANGE
TEMPERATURE Vec
Comm'l
Comm'l
Industrial
Military
Comm'l
Industrial
Military
Military
Comm'l
Comm'l
Military
Comm'l
Comm'l
Industrial
Military
Industrial
Military
Comm'l
Military
Comm'l
Comm'l
Industrial
Military
Comm'l
Military
Military
±5%
±5%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
WSI
MANUFACTURING
PROCEDURE
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
MIL-STD-883C
Standard
MIL-STD-883C
Standard
MIL-STD-883C
Standard
Standard
Standard
MIL-STD-883C
Standard
MIL-STD-883C
MIL-STD-883C
_ _________________________ ·=7#E.__________________________
3-60
rnl'-
WS57C256F
PRELIMINARY
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 32K x 8 CMOS EPROM
KEY FEATURES
• EPI Processing
• Fast Access Time
-
-
40 ns
Latch-Up Immunity Up to 200 mA
• Low Power Consumption
• Standard EPROM Pinout
• DESC SMD No. 5962-86063
• Bipolar Speeds
GENERAL DESCRIPTION
The WS57C256F is a HIGH PERFORMANCE 256K UV Erasable Electrically Programmable Read Only Memory. It
is manufactured in an advanced CMOS technology which allows it to operate at speeds as fast as 40 ns Access Time.
Two major features of the WS57C256F are its Low Power and High Speed. While operating in a TTL environment
it consumes only 110 mA while cycling at full speed. Additionally, the WS57C256F can be placed in a standby mode
which drops operating current below 15 mA in a TTL environment and 500 ~A in a CMOS environment.
The WS57C256F also has exceptional output drive capability. It can source 4 mA and sink 16 mA per output.
The WS57C256F is configured in the standard EPROM pinout which provides an easy upgrade path for systems
which are currently using standard EPROMs.
PIN CONFIGURATION
MODE SELECTION
~
MODE
CEI
OE
PGM
Ag
Ao
V pp
Vcc
YIL
YIL
X
X
Yee 5.0Y
DOUT
Output
Disable
X
YIH
X
X
Yee 5.0Y
High Z
Standby
YIH
X
X
X
High Z
Programming
YIL
YIH
X
X
Yee 5.0Y
Ypp2 5.8Y
Program
Verify
X
YIL
X
X Ypp2 5.8Y
Program
Inhibit
YIH
Read
Signature 3
Chip Carrier
CERDIP
NCVee
A7A12VPP!
!A14 A13
vee
A,.
DIN
A'3
As
DOUT
A.
Al1
YIH
X
X Ypp2 5.0Y
YIL
Yee 5.0Y
23 H4
YIL
YIL YH 2 YIH
Yee 5.0Y
A8 H5
= Ypp = 12.75
3. A , -A8 , A1O-A14
=
± O.25V.
OE
High Z
YIL YH 2 YIL
NOTES:
1. X can be Y1L or V1H .
2. V H
TOP VIEW
OUTPUTS
A,a
CE/PGM
°7
I
4. Manufacturer
5. Device
0, 02 NC
GND
° °.°,
3
'"1...:,;:....-_;;;.t"
0.
0,
0.
03
V 1L .
PRODUCT SELECTION GUIDE
57C256F-40
57C256F-45
57C256F-55
57C256F-70
57C256F-90
Address Access Time (Max)
40 ns
45 ns
55 ns
70 ns
90 ns
Chip Select Time (Max)
40 ns
45 ns
55 ns
70 ns
90 ns
Output Enable Time (Max)
20 ns
20 ns
25 ns
30 ns
30 ns
PARAMETER
3-61
WS57C256F
ABSOLUTE MAXIMUM RATINGS
Storage Temperature ............ -65° to +150°C
Voltage on Any Pin with
Respect to GND ................ -0.6V to +7V
Vpp with respect to GND .......... -0.6V to +13V
ESD Protection ........................ >2000V
"Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
0° to +70°C
+5V + 5%
Industrial
-40° to +85°C
+5V ± 10%
Military
-55° to +125°C
+5V ± 10%
Comm'l
DC READ CHARACTERISTICS Over Operating Range with Vpp
SYMBOL
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
ISB1
Vee Standby Current CMOS
CE
ISB2
Vee Standby Current TTL
CE
Icc1
Vcc Active Current (CMOS)
Notes 1 and 4
Icc2
Vce Active Current (TTL)
Notes 2 and 4
Vpp
Ipp
Vpp Supply Current
Vpp
Vpp Read Voltage
III
Input Load Current
ILO
Output Leakage Current
0.4
V
V
500
J.lA
15
mA
30
Military
40
Comm'l
35
Military
45
= Vcc
AC READ CHARACTERISTICS Over Operating Range with Vpp
100
J.lA
Vec
V
-10
10
J.lA
-10
10
J.lA
-40
= Vee.
-55
-45
-70
-90
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
tAce
40
45
55
70
90
CE to Output Delay
teE
40
45
55
70
90
tOE
20
20
25
30
30
Output Disable to Output Float
tOF
Address to Output Hold
tOH
mA
Vec - 0.4
Address to Output Delay
OE to Output Delay
mA
3. Add 1 rnA/MHz for A.C. power component.
4. Add 3 rnA/MHz for A.C. power component.
O.3V.
SYMBOL
UNITS
Comm'l
= 5.5V or Gnd
VOUT = 5.5V or Gnd
±
MAX
2.4
VIN
1. CMOS inputs: GNO ± O.3V or Vee
2. TTL inputs: V'L .; O.BV, V ,H ;. 2.0V.
PARAMETER
MIN
= 16 mA
= -4 mA
= Vee ± 0.3V (Notes 1 and 3)
= V IH (Notes 2 and 3)
VOL
NOTES:
= Vee.
TEST CONDITIONS
PARAMETER
20
0
20
0
25
0
ns
30
30
0
UNITS
0
------------------------------------~~~.-----------------------------------3-62
--~=
WS57C256F
AC READ TIMING DIAGRAM
ADDRESSES
CE - - - - - , . .
O"E---------.....
OUTPUTS
CAPACITANCE(5)
SYMBOL
TA
---------~~~~Q~Z7--
25°C. f
1 MHz
PARAMETER
C IN
Input Capacitance
C OUT
Output Capacitance
C vPp
V pp Capacitance
NOTES:
CONDITIONS
V IN
VOUT
V pp
= OV
= OV
= OV
TYP(6)
MAX
UNITS
4
6
pF
8
12
pF
18
25
pF
5. This parameter IS only sampled and is not 100% tested.
6. Typical values are for TA = 25°C and nominal supply voltages.
TEST LOAD
(High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0 and 3V
98D
2.01V~
D.U.T·~30PF
I=
Reference Levels: 0.8 and 2.0V
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
----------------------~Jr;---------------------3-63
WS57C256F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 +- 5°C, Vcc
PARAMETER
5.50V + 5%, Vpp
SYMBOLS
MIN
MAX
UNIT
III
-10
10
IiA
60
mA
Input Leakage Current
(VIN = Vcc or Gnd)
Vcc Supply Current During__
Programming Pulse (CE/PGM
12.5 +
- 0.5V)
Icc
= VILl
Vcc Supply Current (Note 4)
Icc
Vil
VIH
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOl = 16 mAl
Output High Voltage During Verify
(loH = -4 mAl
35
mA
-0.1
0.8
V
2.0
Vcc+ 0.3
V
0.45
V
Val
VOH
2.4
V
NOTES: 7. Vee must be applied either coincidentally or before Vpp and removed either coincidentally or after V pp .
8. Vpp must not be greater than 14 volts including overshoot. During CE/PGM = V ,L, Vpp must not be switched from 5 volts
to 12.5 volts or vice-versa.
9. During power up the PGM pin must be brought high (;;>V ,H ) either coincident with or before power is applied to Vpp .
AC CHARACTERISTICS (TA = 25 ± 5°C, Vcc = 5.50V +- 5%, Vpp = 12.5 +- 0.5V)
PARAMETER
MIN
tAS
2
lis
tCOH
tOEs
tos
tAH
2
2
2
0
2
130
130
lis
lis
lis
lis
liS
ns
ns
10
liS
ms
CE High to OE High
Output Enable Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Chip Disable to Output Float Delay
Data Valid From Output Enable
tOH
tOF
tOE
Vpp Setup Time/CE Setup Time
PGM Pulse Width
TYP
MAX
UNIT
SYMBOLS
Address Setup Time
0
tVS/tCES
2
tpw
1
3
2
OE Low to CE "Don't Care"
tocx
NOTE: A single shot programming algorithm should use one 10 ms pulse.
lis
PROGRAMMING WAVEFORM
ADDRESSES
=:)
--1
-lAS"
DATA IN STABLE
DATA~
4-
l os -
4-
I VS'"
HIGH Z
_IOH"-
-10, -
Vpp
locx-
-ICES'"
V,H
CE/PGM
V'L
Ipw
V ,H
CE
V'L
I4-loEs
1
~
tAH
DATA OUT
VALID
Vpp
Vee - - - '
K...-.-
ADDRESS STABLE
:-
-
- IDF
I-
teoH
~
I
---------------------~Jri~------------------3-64
WS57C256F
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C256F-40D *
WS57C256F-45D *
WS57C256F-55CMB *
WS57C256F-55D
WS57C256F-55DI *
WS57C256F-55DMB *
WS57C256F-55L1 *
WS57C256F-55LM B *
WS57C256F-70CI
WS57C256F-70CMB
WS57C256F-70D
WS57C256F-70DM B
WS57C256F-70LMB
WS57C256F-90CI
WS57C256F-90CM
WS57C256F-90CMB
WS57C256F-90D
WS57C256F-90DI
WS57C256F-90DM
WS57C256F-90DMB
40
45
55
55
55
55
55
55
70
70
70
70
70
90
90
90
90
90
90
90
PACKAGE
TYPE
28
28
32
28
28
28
32
32
32
32
28
28
32
32
32
32
28
28
28
28
Pin CERDIp,
Pin CERDIP,
Pad CLLCC
Pin CERDIP,
Pin CERDIP,
Pin CERDIP,
Pin CLDCC
Pin CLDCC
Pad CLLCC
Pad CLLCC
Pin CERDIp,
Pin CERDIp,
Pin CLDCC
Pad CLLCC
Pad CLLCC
Pad CLLCC
Pin CERDIp,
Pin CERDIP,
Pin CERDIP,
Pin CERDIP,
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
D2
D2
C2
D2
D2
D2
L3
L3
C2
C2
D2
D2
L3
C2
C2
C2
D2
D2
D2
D2
Comm'l
Comm'l
Military
Comm'l
Industrial
Military
Industrial
Military
Industrial
Military
Comm'l
Military
Military
Industrial
Military
Military
Comm'l
Industrial
Military
Military
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
MIL-STD-883C
Standard
MIL-STD-883C
Standard
MIL-STD-883C
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
MIL-STD-883C
'These products are Advance Information.
-------------------------~Jr;------------------------3-65
~3_6~6-----------------------~Jri-------------------------
iFSS':.=-__--___ _____________________________________________________ __7_C:__2__5_7_
r=~~~~~~. ~ ~
~~_5
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 16K x 16
55 ns
• Simplifies Board Routing
• Low Power Consumption
• Ideal for 16/32 Bit Processors
-
EPROM
KEY FEATURES
• 16-Bit Data Bus
• Fast Access Time
-
C:MOS
• Single Chip Solution
• Compatible with JEDEC Pinout
TMS320, 68000, 80386, etc.
GENERAL DESCRIPTION
The WS57C257 is an extremely High Performance EPROM based memory with a 16K x 16 architecture. It is
manufactured in an advanced CMOS process which consumes very little power while operating at speeds which
rival that of bipolar PROMs.
The major features of the WS57C257 are its 16K x 16 architecture and its high speed. This combination makes the
WS57C257 an ideal solution for applications which utilize 16/32 bit data paths. Examples include systems which are
based on such processors as the TMS320 family of DSP processors as well as high performance general purpose
processors such as the MC68000 family and the 80286 and 80386 microprocessors.
The wordwide architecture of the WS57C257 results in a 4 to 1 savings in EPROM component count and a minimum
60% savings in board space.
The pin configuration utilized is upward compatible with the JEDEC standard pinout for word wide EPROMs. This
allows an easy upgrade path from lower density memories such as the WS57C65. No board changes or jumper wires
are required to complete the upgrade.
MODE SELECTION
INS
~
MODE
CE
Read
OE
PIN CONFIGURATION
PGM
V pp
Vcc
~
OUTPUTS
p
cf d' J'I~ J: ~ J! ~
VIL
VIL
X
Vce
Vee
Dour
Output
Disable
X
VIH
X
Vee
Vee
High Z
Standby
VIH
X
X
Vee
Vee
High Z
Program
VIL
VIH
VIL
Vpp
Vee
DIN
Program
Verify
X
VIL
X
Vpp
Vee
Dour
Program
Inhibit
VIH
VIH
VIH
Vpp
Vee
High Z
X
Vee
Vee
Encoded
Data
Signature'
X can be V'L or V'H'
'For signature. Ag = 1211. Ao is toggled, and all other addresses are
aI TIL low. Ao = V'L = MFGR 0023H, Ao = V'H = DEVICE OOB2H.
0
"""""
~ ~ ~
""''''''
7111111111111111111111139
0,. :~;"6
0,,:~~8
0'0
:~;9
'5 "4 '3 "2 : : 4443 42414o~ - A'3
y
38':::~A
37:::: A"
vpp c 1
CEc2
40 :J Vee
39:JPGM
0" e 3
O,.C4
3D NC
37::JNC
6'Ne
3 35::JA'3
34::J A,.
0·r-5
13"
O,.C6
0" e 7
o. :::10
36:::: A" O,oe 8
33::JA"
0, :::11
35:::: A'o o. e 9 0 3 2 : : J A,o
GNO ::;12
34;::: G~D o,C 10
31::J Ag
NC :::13
33~:: NC GNOC 11
30::J GNO
0 7 ::a4
32'-- A
0 7 C 12
29::J A,
0, :::15
31::: A'
0.C13
28::JA7
o. ~::;16
30::: ~ A7
Os C 14
27 ::J As
o. ::11819 2021 22 232425 26 27 2~=:: A· O. [ 15
26 J As
17i~;~~~~i!~i~:-~;~i~~I~~29 5
0 3 (16
25JA4
, 1 , "
,I"
1 1 1 1 1 1 , 1 , I 1 , 7
O2 ( 17
24 ] A3
0 0'0 cf
I~ ~ ~
c .; .r .;
0, [ 18
0 0 c 19
OE [ 20
TOP
L--_____________________
23 J A.
22 J A,
21 J As
~~~~
PRODUCT SELECTION GUIDE
PARAMETER
WS57C257-55
WS57C257-70
WS57C257-90
Address Access Time
55 ns
70 ns
90 ns
Chip Select Time
55 ns
70 ns
90 ns
Output Enable Time
25 ns
30 ns
30 ns
---------------------~Jri,--------------------3·67
WS57C257
ABSOWTE MAXIMUM RATlNGS*
"Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ............ -65° to +150°C
Voltage on Any Pin with
Respect to GND ................ -0.6V to +7V
Vpp with respect to GND .......... -0.6V to +14V
ESD Protection ........................ >2000V
OPERATING RANGE
RANGE
Comm'l
Industrial
Military
TEMPERATURE
Vce
0° to +70°C
+5V ± 5%
-40° to +85°C
+5V ± 10%
-55°C to +125°C
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range with Vpp
SYMBOL
PARAMETER
MAX
UNITS
0.4
V
Notes 1 and 3
500
I-tA
Notes 2 and 3
20
mA
Output Low Voltage
IOL
VO H
Output High Voltage
IOH
ISBI
Vcc Standby Current (CMOS)
ISB2
Vcc Standby Current (TTL)
= 8 mA
= -2 mA
2.4
V
Notes
1 and 4
Comm'l
40
Military
50
Comm'l
50
Military
60
ICCI
Active Current (CMOS)
ICC2
Vcc Active Current (TTL)
Notes
2 and 4
Ipp
Vpp Supply Current
Vpp
Vpp
Vpp Read Voltage
III
Input Load Current
ILO
MIN
TEST CONDITIONS
VOL
NOTES:
= Vec.
= Vcc
Output Leakage Current
1. CMOS inputs: GND ± O.3V or Vcc ± O.3V.
2. TTL mputs. V1L .; O.BV, V1H ;. 2.0V
mA
100
I-tA
-10
Vcc
10
I-tA
-10
10
I-tA
Vcc - 0.4
= 5.5V or Gnd
VOUT = 5.5V or Gnd
V 1N
mA
V
3. Add 1 rnA/MHz for A.C power component.
4. Add 3 rnA/MHz for A.G. power component.
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vcc.
PARAMETER
SYMBOL
WS57C257-55
MIN
MAX
WS57C257-70
WS57C257-90
MIN
MIN
MAX
MAX
Address to Output Delay
tACC
55
70
90
CE to Output Delay
tCE
55
70
90
OE to Output Delay
tOE
25
30
30
Output Disable to Output Float
tDF
25
30
30
Address to Output Hold
tOH
0
0
UNITS
ns
0
------------------------~Jri-----------------------
3-68
WS57C257
AC READ TIMING DIAGRAM
ADDRESSES
CE---__,.
O£--------~
OUTPUTS------------------~~~~~=lEtt---f--
g
tOF
CAPACITANCEl5)
SYMBOL
C IN
TA
= 25°C, f = 1 MHz
PARAMETER
Input Capacitance
C OUT
Output Capacitance
CvPp
Vpp Capacitance
NOTES:
CONDITIONS
TYP(6)
MAX
UNITS
V IN = OV
4
6
pF
VO UT = OV
8
12
pF
V pp = OV
18
25
pF
5. This parameter is only sampled and is not 100% tested.
6. Typical values are for TA = 25°C and nominal supply voltages.
TEST LOAD
(High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0 and 3V
1600
2.01V~
Reference Levels: 0.8 and 2.0V
D.U.T·~30PF
I=-
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
-------------------------~Jr;------------------------3-69
I
WS57C257
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 +
- 5°C, Vee
PARAMETER
SYMBOLS
MIN
MAX
UNIT
III
-10
10
IlA
60
mA
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During __
Programming Pulse (CE = PGM
Ipp
= VIL)
Vee Supply Current
lee
VIL
VIH
Input Low Level
Input High Level
Output Low Voltage During Verify
(l0L = 16 mAl
VOL
Output High Voltage During Verify
(loH = -4 mAl
VOH
NOTES:
12.5 ± 0.5V)
5.5V +
- 5%, Vpp
35
mA
-0.1
0.8
V
2.0
Vee +0.3
V
0.45
V
2.4
V
7. Vcc must be applied either cOincidentally or before vpp and removed either coincidentally or after Vpp.
8. Vpp must not be greater than 14 volts including overshoot. During eE = PGM = V ,L, Vpp must not be switched from 5 volts
to 12.5 volts or vice·versa.
9. During power up the PGM pin must be brought high (::.V ,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS (TA
= 25 +-
PARAMETER
Address Setup Time
5°C, Vee
= 5.5V -+
5%, Vpp
= 12.5 -+
TYP
0.5V)
MAX
UNIT
SYMBOLS
MIN
Ils
tAS
2
Chip Enable Setup Time
teEs
2
Ils
Output Enable Setup Time
tOES
2
Ils
Data Setup Time
tos
2
Il s
Address Hold Time
tAH
0
Ils
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
Data Valid From Output Enable
tOE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
3
130
Il s
ns
130
ns
10
Il s
ms
NOTE: Single shot programming algorithms should use one 10 ms pulse per word.
PROGRAMMING WAVEFORM
ADDRESSES
DATA
V pp
Vpp
Vee
V,H
CE
VIL
V,H
PGM
V'L
V,H
DE
V'L
.,;,,§
-3-70
---------------------------------,;.jF.~----------------------------------
WS57C257
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
WS57C257-550
WS57C257-70CI
WS57C257-70CMB
WS57C257-700
WS57C257-7001
WS57C257-700MB
WS57C257-70LMB
WS57C257-90CMB
WS57C257-9001
WS57C257-900MB
SPEED
(ns)
55
70
70
70
70
70
70
90
90
90
PACKAGE
TYPE
40
44
44
40
40
40
44
44
40
40
Pin CEROIp,
Pad CLLCC
Pad CLLCC
Pin CEROIP,
Pin CEROIP,
Pin CEROIp,
Pin CLOCC
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
03
C3
C3
03
03
03
L4
C3
03
03
Comm'l
Industrial
Military
Comm'l
Industrial
Military
Military
Military
Industrial
Military
Standard
Standard
M IL-STD-883C
Standard
Standard
MIL-STO-883C
MIL-STO-883C
MIL-STD-883C
Standard
MIL-STD-883C
---------------------~~;--------------------3-71
~~
3-72
______________________________ '··AFE __________________________________
';1.11_;
ifEE....
==:
_
- - - ----~~
.-,
r~...,
-"'"
~~
WAFERSCALE INTEGRATION, INC.
512K EPROM SELECTION GUIDE
ARCHITECTURE
64Kx8
WS27C512F
64Kx8
WS57C512F
64Kx8
WS27C512L
))
55
II
70
80
90
100
110
!
I
120
130
I
140
150
160
170
180
I
190
200
ACCESS TIME (ns)
3-73
~34~4-----------------------~Jr;-------------------------
.. =
"I;~
1'
__ ...
.,.~
.-
_
WS27C512F
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 64K
x
8 CMOS EPROM
KEY FEATURES
• Fast Access Time
-
• Low Power Consumption
90 ns
• Standard EPROM Pinout
• EPI Processing
-
• Bipolar Speeds
Latch-Up Immunity Up to 200 mA
GENERAL DESCRIPTION
The WS27C512F is a High Performance 512K UV Erasable Electrically Programmable Read Only Memory. It is manufactured in an advanced CMOS technology which enables it to operate at speeds as fast as 90 ns Access Time.
Two major features of the WS27C512F are its Low Power and High Speed. While operating in a TIL environment
it consumes only 64 mA while cycling at full speed. Additionally, the WS27C512F can be placed in a standby mode
which drops operating current below 2 mA in a TIL environment and 200 IlA in a CMOS environment.
The WS27C512F also has exceptional output drive capability. It can source 1 mA and sink 4 mA per output.
The WS27C512F is configured in the standard EPROM pinout which provides an easy upgrade path for systems which
are currently using standard EPROMs.
PIN CONFIGURATION
MODE SELECTION
PINS
eEl
OE!
MODE
Prui
Vpp
AI
Ao
Vee
Read
VIL
VIL
X
X
5.0V
DOUT
Output
Disable
X
VIH
X
X
5.0V
High Z
Standby
VIH
X
X
X
5.0V
High Z
Programming
VIL
Vpp 2
X
X
5.8V
DIN
Program
Verify
VIL
VIL
X
X
5.8V
DOUT
Program
Inhibit
VIH
Signature 3
-
Vpp2
X
X
VIL
VIL
VH2 VIL
VIL
VIL
VH2 VIH
NOTES:
1. X ean be V1L or VIH .
2. VH = Vpp = 12.75 ± O.25V.
OUTPUTS
TOP VIEW
Chip Carrier
NeV ee
A7 A12A1S1
IA14 A13
LJU:"JIILJULJ
4 3 2 ""323130
As :]5
1
29L As
28~:
As :] 6
A"
:~7
:~8
High Z
A3
A2 :] 9
A1 :]10
5.0V
23 H4
Ae
5.0V
AA H5
5.0V
CERDIP
:~
11
Ne :J12
00
:]
As
0 2 7 C A11
26e NC
25
OENpp
24[: Al0
c:
23 C CElPGM
22[: 0 7
13
21 [: 0 6
14151617181920
ii rl firi fir-: r1
4. Manufacturer
5. Device
A,.
Vee
A12
A14
A7
A,.
A.
Ae
At
A.
A"
A11
OENpp
A.
A2
A l0
A,
A.
O.
0,
O.
CElPGM
07
O.
O.
O.
11
GND""L.;..~_~03
3. A,-As• A,o-A'5 = V1L.
PRODUCT SELECTION GUIDE
PARAMETER
WS27C512F-90
WS27C512F-12
Address Access Time (Max)
90 ns
120 ns
Chip Select Time (Max)
90 ns
120 ns
Output Enable Time (Max)
30 ns
30 ns
3-75
WS27C512F
ABSOWTE MAXIMUM RATINGS*
·Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ............ -65° to +150°C
Voltage on Any Pin with
Respect to GND ................ -0.6V to +7V
Vpp with respect to GND .......... -0.6V to +13V
ESD Protection ........................ >2000V
OPERATING RANGE
TEMPERATURE
Vcc
Comm'l
0° to +70°C
+5V ± 5%
Military
-55° to +125°C
+5V ± 10%
RANGE
DC READ CHARACTERISTICS Over Operating Range with Vpp
SYMBOL
VOL
PARAMETER
= Vcc.
TEST CONDITIONS
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
ISBl
Vee Standby Current (CMOS)
CE
ISB2
Vee Standby Current (TTL)
CE
= 16 rnA
= -4 rnA
= Vee ± 0.3V (Note
= VIH (Note 2)
leel
Vee Active Current (CMOS)
Notes 1 and 3
lee2
Vee Active Current (TTL)
Notes 2 and 3
Ipp
Vpp Supply Current
Vpp
Vpp
Vpp Read Voltage
MIN
MAX
UNITS
0.4
V
200
ItA
2
rnA
V
2.4
1)
Comm'l
30
Military
40
Comm'l
35
Military
45
= Vee
= 5.5V or Gnd
= 5.5V or Gnd
Input Load Current
V IN
ILO
Output Leakage Current
VOUT
NOTES:
1. CMOS Inputs: GNO ± 03V or Vee
2. TTL inputs: VIL .. O.BV, VIH ~ 2.0V.
± 03V.
rnA
100
ItA
Vee
V
-10
10
~A
-10
10
~A
Vee - 0.4
III
rnA
3. Add 3 rnA/MHz for A.C. power component.
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
PARAMETER
SYMBOL
WS27C512F-90
WS27C512F-12
MIN
MIN
MAX
MAX
Address to Output Delay
tAee
90
120
CE to Output Delay
teE
90
120
OE to Output Delay
tOE
30
30
Output Disable to Output Float
tOF
30
30
Address to Output Hold
tOH
0
UNITS
ns
0
------------------------~Jr;-----------------------3-76
WS27C512F
AC READ TIMING DIAGRAM
ADDRESSES
OE--------------~
OUTPUTS
-----------~~~~d=lzt-1o,
CAPACITANCf{4) TA
SYMBOL
= 25°C, f = 1 MHz
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
CvPp
V pp Capacitance
NOTES:
f.-
CONDITIONS
TYP(5)
MAX
UNITS
V IN = OV
4
6
pF
V OUT = OV
8
12
pF
V pp = OV
18
25
pF
4. This parameter is only sampled and is not 100% tested.
5. TYPical values are for T A = 25°C and nominal supply voltages
TEST LOAD (High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0.4 and 2.4V
98ll
2.01V~
D.U.T.
I-=-
Reference Levels: 0.8 and 2.0V
30 pF
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
----------------------~Jr;---------------------3-77
WS27C512F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA
= 25 -+
5.5V ± 5%, Vpp
5°C, Vcc
PARAMETER
MIN
MAX
UNIT
ILl
-10
10
/lA
60
mA
25
mA
Input Leakage Current
(VIN = Vcc or Gnd)
Vcc Supply Current During_ _
Programming Pulse (CE/PGM
Icc
= VILl
Vcc Supply Current
Icc
VIL
VIH
Input Low Level
Input High Level
(1m
Output Low Voltage During Verify
= 16 mAl
VOL
Output High Voltage During Verify
(lOH = -4 mAl
VOH
NOTES:
12.5 -+ 0.5V)
SYMBOLS
-0.1
0.8
V
2.0
Vcc+ 0.3
V
0.45
V
2.4
V
6. Vee must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp.
7. Vpp must not be greater than 14 volts including overshoot. DUring CE/PGM = V ,L, Vpp must not be switched from 5 volts
to 12.5 volts or vice·versa.
8. During power up the CE/PGM pin must be brought high C;>V ,H ) either coincident with or before power is applied to V pp .
AC CHARACTERISTICS (TA
= 25 ±
PARAMETER
SoC, Vcc
= 5.5V ±
5%, Vpp
= 12.5 ± 0.5V)
TYP
SYMBOL
MIN
Address Setup Time
tAS
2
/ls
Vpp Hold Time
tVH
2
/ls
Data Setup Time
tos
2
/ls
Address Hold Time
tAH
0
/ls
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
Data Valid From Chip Enable
tCE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
NOTES:
MAX
UNIT
/ls
70
ns
70
ns
10
ms
/lS
A single shot programming algorithm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
DATA
V,H
OEN"
V'L
V,H
CE/PGM
Vil
_____________________________________
3·78
rAr~
..E _____________________________________
~I;
WS27C512F
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS27C512F-90CMB
WS27C512F-900
WS27C512F-900MB
WS27C512F-12CMB
WS27C512F-12DMB
90
90
90
120
120
PACKAGE
TYPE
32
28
28
32
28
Pad CLLCC
Pin CERDIp, 0.6"
Pin CERDIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
C2
02
02
C2
02
Military
Comm'l
Military
Miltary
Military
MIL-STO-883C
Standard
MIL-STO-883C
M IL-STD-883C
MIL-STD-883C
-----------------------~Jr;----------------------3-79
~3--8-0-------------------------------~aiF~----------------------------------
---==-==iE
-.
..=' _--'.-F.=I-i"'::S
~
~~
---~.-..
-
WS57C512F
ADVANCE INFORMATION
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 64K x 8 CMOS EPROM
KEY FEATURES
• Fast Access Time
-
• Standard EPROM Pinout
55 ns
• Bipolar Speeds
• EPI Processing
-
• Low Power Consumption
Latch-Up Immunity Up to 200 mA
GENERAL DESCRIPTION
The WS57C512F is a HIGH PERFORMANCE 512K UV Erasable Electrically Programmable Read Only Memory. It
is manufactured in an advanced CMOS technology which enables it to operate at speeds as fast as 55 ns Access Time.
Two major features of the WS57C512F are its Low Power and High Speed. While operating in a TTL environment
it consumes only 90 mA while cycling at full speed. Additionally, the WS57C512F can be placed in a standby mode
which drops operating current below 2 mA in a TTL environment and 500 !LA in a CMOS environment.
The WS57C512F also has exceptional output drive capability. It can source 4 mA and sink 16 mA per output.
The WS57C512F is configured in the standard EPROM pinout which provides an easy upgrade path for systems which
are currently using standard EPROMs.
MODE SELECTION
~
MODE
Read
Output Disable
PIN CONFIGURATION
CE
VIL
VIL
Vee
DOUT
X
V IH
Vee
High Z
X
Standby
VIH
Program
V IL
V pp Vee
Program Verify
V IL
V IL
Vee
Program Inhibit VIH
VIH
Vee
DOUT
High Z
Signature'
VIL
Vee
Encoded
Data
VIL
TOP VIEW
OEI
OUTPUTS
V pp Vcc
Vee
Chip Carrier
CERDIP
NCVee
A7 A12A1S1
...----...r--
1A14 A13
LJ LJ :"Jl : ~JLJ LJ
High Z
A,
A.
A.
A,
A,
A,
Ao
DIN
NC
00
X can be either V1L or V1H •
'For Signature, As = 12V, Ao is toggled, and all other
addresses are at TTL low. Ao = V1L = MFGR 23H,
Ao = V 1H = DEVICE MH.
4 3 2 ""323130
~]5
1
29[~ As
As
A11
:18
26[= NC
:~ 9
25 [: OE/Vpp
:J10
24[: A,o
:~ 11
23 [: CE/PGM
~] 12
22
07
:; 13
21 ~: 0,
14151617181920
~;: o::~
c:
~irl:-irinriil
0, 0,
INC 0,0.0.
A,.[ 1
A'2[ 2
A7[ 3
As~4
A.~5
28 ~Vee
27 pA,.
26 pA,.
25g As
24~A.
A ' [ 6 0 2 3 PA11
A, [ 7
22 g OEIVpp
A2~8
A, [
Ag[
Oo[
0, [
9
10
11
12
02~ 13
GND[ 14
21~A,o
~ CE/PGM
20
19
18
17
16
15
P07
~ 0,
~ o.
go.
] 0,
GND
PRODUCT SELECTION GUIDE
PARAMETER
WS57C512F-55
WS57C512F-70
WS57C512F-90
Address Access Time (Max)
55 ns
70 ns
90 ns
Chip Select Time (Max)
55 ns
70 ns
90 ns
Output Enable Time (Max)
25 ns
30 ns
30 ns
3-81
WS57C512F
ABSOLUTE MAXIMUM RATINGS·
"Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to +150°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +13V
ESD Protection ....................... > 2000V
OPERATING RANGE
RANGE
TEMPERATURE
Industrial
0° to +70°C
-40° to +85°C
Vcc
+5V + 5%
+5V + 10%
Military
-55° to +125°C
+5V + 10%
Comm'l
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range with Vpp = Vce.
TEST CONDITIONS
PARAMETER
= 16 mA
= -4 mA
= Vcc + 0.3V (Note
= VIH (Note 2)
VOL
Output Low Voltage
VOH
Output High Voltage
IOH
ISB1
Vce Standby Current (CMOS)
CE
ISB2
Vcc Standby Current (TTL)
CE
lec1
Vcc Active Current (CMOS)
Notes 1 and 3
Icc2
Vee Active Current (TTL)
Notes 2 and 3
Ipp
Vpp Supply Current
Vpp
Vpp
Vpp Read Voltage
IOL
VIN
ILO
VO UT
1. CMOS inputs: GND ± D.3V or Vee ± D.3V.
1)
Comm'l
UNITS
0.4
V
V
500
~A
2
mA
30
40
35
45
100
Military
Comm'l
Military
= 5.5V or Gnd
= 5.5V or Gnd
Input Load Current
Output Leakage Current
MAX
2.4
= Vcc
III
NOTES:
MIN
Vec - 0.4
-10
Vce
10
-10
10
mA
mA
~
V
~
~
3. Add 3 mNMHz for A.C. power component.
2. TIL inputs: V 1L " DIJV, V 1H " 2.DV.
AC READ CHARACTERISTICS
Over Operating Range with Vpp
= Vce.
WS57C512F-55
WS57C512F-70
WS57C512F-90
MIN
MIN
MIN
PARAMETER
SYMBOL
Address to Output Delay
tAce
55
70
70
90
CE to Output Delay
MAX
MAX
MAX
90
teE
55
OE to Output Delay
tOE
25
30
30
Output Disable to
Output Float
tDF
25
30
30
Address to Output Hold
tOH
0
0
UNITS
ns
0
-----------------------~Jr;---------------------3-82
WS57C512F
AC READ TIMING DIAGRAM
ADDRESSES
QE-------,
OUTPUTS
CAPACITANCE<4)
----------t~~;LiiDi.,~+_-
TA = 25°C, f = 1 MHz
SYMBOL
PARAMETER
C IN
Input Capacitance
C OUT
Output Capacitance
CvPp
Vpp Capacitance
NOTES:
CONDITIONS
TYP(5)
MAX
UNITS
= OV
V OUT = OV
Vpp = OV
4
6
pF
8
12
pF
18
25
pF
V IN
4. This parameter is only sampled and IS not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages.
TEST LOAD
(High Impedance Test Systems)
TIMING LEVELS
Input Levels: 0 and 3V
980
2'01V~
D.U.T.
I=
Reference Levels: 0.8 and 2.0V
30 pF
(INCWDING SCOPE
AND JIG
CAPACITANCE
------------------------~Jr;-----------------------3·83
WS57C512F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 12.5 ± 0.5V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
(V'N = Vee or Gnd)
III
-10
10
!.LA
Vpp Supply Current Duri~
Programming Pulse (CE/PGM = V,u
Ipp
60
rnA
Vee Supply Current
lee
PARAMETER
V'L
-0.1
Input High Level
V'H
2.0
Output Low Voltage During Verify
(IOL = 16 rnA)
VOL
Output High Voltage During Verify
(loH = -4 rnA)
VOH
Input Low Level
NOTES:
25
rnA
0.8
V
Vee +0.3
V
0.45
V
V
2.4
6. Vcc must be applied either cOincidentally or before Vpp and removed either COincidentally or after Vpp.
7. Vpp must not be greater than t4 volts including overshoot. During CE/PGM = V,L. Vpp must not be sWitched from 5 volts
to 12.5 volts or vice-versa.
8. DUring power up the CE/PGM pin must be brought high (;.V ,H ) either (:olncident with or before power is applied to Vpp.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee
PARAMETER
= 55V
± 5%, Vpp
= 12.5
± 0.5V)
SYMBOL
MIN
Address Setup Time
tAS
2
~s
Vpp Hold Time
tVH
2
~s
~s
Data Setup Time
TYP
MAX
UNIT
tos
2
Address Hold Time
tAH
0
~s
Data Hold Time
tOH
2
~s
Chip Disable to Output Float Delay
tOF
0
Data Valid From Chip Enable
icE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
70
ns
70
ns
10
ms
~s
NOTE: A single shot programming algor~hm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
DATA
V,H
OEIV••
V'L
V,H
CEJPGM
V'L
---------------------~~i-------------------3-84
-
-~----~-------------
-====
__
,--.,
= =:,.1-IE __________________________________________________________
WS27C512L
~=:
==r~~.,
WAFERSCALE INTEGRATION, INC.
64K
8 CMOS EPROM
X
KEY FEATURES
• High Performance CMOS
-
• 300 Mil Dip or Standard 600 Mil Dip
100 ns Access Time
• EPI Processing
• Fast Programming
• Drop-In Replacement for 27C512 or 27512
• DESC SMD #5962-87648
-
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000V
• Standard JEDEC EPROM Pinout
GENERAL DESCRIPTION
The WS27C512L is a HIGH PERFORMANCE 512K UV Erasable Electrically Programmable Read Only Memory. It
is manufactured in WSI's latest CMOS EPROM technology which enables it to operate at speeds as fast as 100 ns
access time over the full operating range.
The WS27C512L can directly replace any 64K x 8 EPROM which conforms to the JEDEC standard. Examples of
this would be as follows: 27512, 27C512, or 27C512F. It can be easily programmed using standard EPROM programmers
or the MagicPro™ IBM PC compatible engineering programmer offered by WSI.
The WS27C512L is also available in a 300 mil Dip. The pin configuration remains the same as the 600 mil wide package
and the programming algorithms are unchanged. This enables a simple PCB layout change to take advantage of
a 50% reduction in required board space.
~
The WS27C512L provides microprocessor-based systems storage capacity for portions of operating system and
application software. Its 100-ns access time provides no-wait-state operation with high-performance CPUs such as
the 16-MHz 80186, 16-MHz 68020, or 12-MHz 80386. The WS27C512L offers a single chip solution for the code storage
requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from EPROM
storage, greatly enhancing system utility.
The WS27C512L is configured in the standard JEDEC EPROM pinout which provides an easy upgrade path for systems
which are currently using standard EPROMs.
The WS27C512L is one member of a high density EPROM Family which ranges in density from 64K to 4 Megabit.
PRODUCT SELECTION GUIDE
PARAMETER
WS27C512L-10
WS27C512L-12
WS27C512L-15
WS27C512L-20
200 ns
Address Access Time (Max)
100 ns
120 ns
150 ns
Chip Select Time (Max)
100 ns
120 ns
150 ns
200 ns
Output Enable Time (Max)
30 ns
35 ns
40 ns
40 ns
-------------------~Jr;---------------------3-85
WS27C512L
ABSOWTE MAXIMUM RAT/NGS*
"Notice: Stresses above those listed under ''Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to +150°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vee Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ....................... > 2000V
OPERATING RANGE
RANGE
Commercial
Military
TEMPERATURE
Vcc
TOLERANCE
O°C to +70°C
+5V
±5% or ±10%
-55°C to +125°C
+5V
+10%
-
DC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
MIN
MAX
UNITS
VIL
Input Low Level
-0.5
0.8
V
V IH
Input High Level
2.0
VOL
Output Low Voltage
Vee + 1
0.4
V
VOH
IssP)
Output High Voltage
IOH = -400!lA
Vee Standby Current (CMOS)
CE = Vee ± 0.3V
Iss2
Vee Standby Current
lee(l)
Vee Active Current
CE = VIH
!F=5MHz
_
_
CE = OE = V IL ! F = 8 MHz
Ipp
Vpp Supply Current
Vpp = Vee
Vpp
Vpp Read Voltage
SYMBOL
TEST CONDITIONS
PARAMETER
IOL = 2.1 mA
3.5
III
Input Load Current
VIN = 5.5V or Gnd
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
V
V
100
1
40
50
100
Vee -0.4
-1
Vee
1
-10
10
!lA
mA
mA
!lA
V
!lA
!lA
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
SYMBOL
PARAMETER
27C512L-10
27C512L-12
27C512L-15
27C512L-20
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
tAee
Address to Output
Delay
100
120
150
200
teE
CE to Output Delay
100
120
150
200
tOE
OE to Output Delay
30
35
40
40
tOF(2)
Output Disable to
Output Float
30
35
40
40
tOH(2)
Output Hold From
Addresses, CE or
OE, Whichever
Occurred First
UNITS
ns
0
0
0
0
NOTES:
1. The supply current is the sum of Icc and Ipp. The maximum current value IS with Outputs 0 0 to 0 7 unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven-see timing diagram.
3. CMOS inputs: VIL = GNO ± 0.3V, VIH = Vee ± 0.3V.
------------------------~Jr;'------------------------
3-86
WS27C512L
A.C. WAVEFORMS
V,H
-----""'"
ADDRESS
VALID
ADDRESSES
V,L
------
V,H
--------1f-..,.
V,H
-------I----'"'\.
1 + - - - - tACC
------1~
HIGH Z
HIGH Z
-------------++-4i-++_<
OUTPUT
CAPACITANCE(4)
SYMBOL
25°C, f
TA
1 MHz
PARAMETER
C IN
Input Capacitance
C OUT
Output Capacitance
CvPp
V pp
CONDITIONS
Capacitance
VIN
V OUT
V pp
= OV
= OV
= OV
Typ(5)
MAX
UNITS
pF
4
6
8
12
pF
18
25
pF
NOTES:
4. This parameter is only sampled and is not 100% tested.
5. TYPical values are for TA = 25°C and nominal supply voltages
6. OE may be delayed up to tCE-tOE after the failing edge of CE without Impact on t CE '
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.0W
-r2.4
2.0
' ) TEST POINTS
0.4
0.8
<
2.0
0.8
~
DEVICE
UNDER
TEST
I
8200
CL
= 100 pF
--
A.C. testing inputs are driven at 2.4V for a Logic "1" and
O.4V for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and O.BV for a Logic "0."
C L includes Jig Capacitance
---------------------fjfjf~Ar·-------------------'r!filIfii6_
3-87
WS27C512L
MODE SELECTION
The modes of operation of the WS27C512L are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for VPP and Ag for device signature.
Table 1. Modes Selection
~S
MODE
OElV pp
CE/PGM
A9
Ao
vee
OUTPUTS
Standby
V IH
X
X
X
X
Programming
V IL
V pp (8)
X
X
X
X
Program Verify
V IL
X
X
5.SV
DOUT
V IH
VIL
V pp (8)
X
X
5.0V
High Z
V IL
V IL
V H(8)
V IL
5.0V
23 H
V IL
V H(8)
V IH
5.0V
C3 H
Read
Output Disable
Program Inhibit
Signature
Manufacturer(9)
Device(9)
V IL
V IL
X
V IH
V IL
X
5.0V
DOUT
5.0V
High Z
5.0V
High Z
5.SV
DIN
NOTES:
7. X can be VIL or VIH .
8. VH = Vpp = 12.75 ± O.2SV.
DIP PIN CONFIGURATIONS
8 Mbit
4 Mbit
2 Mbil
A 19
A 16
A 1S
A12
A7
A6
As
A.
As
A2
A1
Ao
00
01
°2
GND
XXlVpp
A 16
A 1S
A12
A7
A6
As
A.
A3
A2
A1
Ao
00
°1
°2
GND
XXlVpp
A 16
A1S
A12
A7
A6
As
A.
A3
A2
A1
Ao
00
°1
°2
GND
NOTE:
27C010L 27C256L
XXlVpp
A 16
A 1S
A12
A7
A6
As
A.
A3
A2
A1
Ao
00
°1
°2
GND
27C256L 27C010L
WS27C512L
Vpp
A12
A7
A6
As
A.
A3
A2
A1
Ao
00
°1
O2
GND
-
.,-
-j
-
-
Vee
A 10
3A13
.As
Ag
A11
OE
IVppA10
I'-c
0(
~~ ~ ~.jL1J~4~~~6
29~:
As
Outputs
PGM
Program
XX
Don't Care (During Read)
oo~~ooo
"TOP
NOTE: Leadless or
Leaded, PlastiC or
Ceramic Package
-------------------------~Jr;------------------------3-88
WS27C512L
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vcc
PARAMETER
= 5.8V ±
0.25V, Vpp
12.75
±
0.25V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
(VIN = VCC or Gnd)
III
-10
10
IlA
Vpp Supply Current During
Programming Pulse (CE/PGM = VILl
Ipp
60
mA
Vcc Supply Current, See Icc2
Input High Level
Icc
V IL
V IH
Output Low Voltage During Verify
(lOL = 2.1 mAl
VOL
Output High Voltage During Verify
(lOH = -400 IlA)
VOH
Input Low Level
NOTES:
40
mA
-0.1
0.8
V
2.0
Vcc+ 0.3
V
0.4
V
3.5
V
11. Vcc must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp .
12. Vpp must not be greater than 14 volts Including overshoot DUring CE/PGM = V,L , Vpp must not be sWitched from 5 volts
to 12.75 volts or vice·versa.
13. During power up the CE/PGM pin must be brought high (;;>V ,H ) either coincident with or before power IS applied to Vpp.
AC CHARACTERISTICS (TA
= 25 +
- 5°C, Vec = 5.8V + 0.25V, Vpp = 12.75 +- 0.25V)
-
SYMBOLS
MIN
Address Setup Time
tAS
2
IlS
Vpp Hold Time
tVH
2
Data Setup Time
Il s
Il s
PARAMETER
tos
2
Address Hold Time
tAH
0
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
Data Valid From Chip Enable
tCE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
0.1
TYP
MAX
55
55
UNIT
Il s
Il s
ns
ns
IlS
4
ms
PROGRAMMING WA VEFORM
ADDRESSES
DATA
Vpp
OE/v pp
V'L
V,H
CE/PGM
V'L
-------------------------------------~~Jr------------------------------------3-89
WS27C512L
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS27C512L-100/5
WS27C512L-120
WS27C512L-12J
WS27C512L-15CMB
WS27C512L-150
WS27C512L-150MB
WS27C512L-15J
WS27C512L-15LMB
WS27C512L-20CMB
WS27C512L-200MB
100
120
120
150
150
150
150
150
200
200
PACKAGE
TYPE
28
28
32
32
28
28
32
32
32
28
Pin CEROIp,
Pin CEROIp,
Pin PLOCC
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pin PLOCC
Pin CLOCC
Pad CLLCC
Pin CEROIp,
0.6"
0.6"
0.6"
0.6"
0.6"
PACKAGE
DRAWING
02
02
J4
C2
02
02
J4
L3
C2
02
OPERATING
RANGE
TEMPERATURE
Comm'l
Comm'l
Comm'l
Military
Comm'l
Military
Comm'l
Military
Military
Military
Vee
WSI
MANUFACTURING
PROCEDURE
±5%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
Standard
Standard
Standard
MIL-STO-883C
Standard
MIL-STO-883C
Standard
MIL-STO-883C
MIL-STO-883C
MIL-STO-883C
---------------------~Jri---------------------
3-90
WAFERSCALE INTEGRATION, INC.
1 MEG EPROM SELECTION GUIDE
ARCHITECTURE
64Kx 16
I
I
WS27C210F
I
64K x 16
I
I
WS57C210M
I
64K x 16
128K x 8
I
I
WS57C010M
I
JL
"
~L
~
WS27C010L
I
I
128K x 8
~
I
=1I
WS27C010F
I
128K x 8
WS27C210L
I
ro
~
L
00
t
~
L
m
=
I
I
m
=
I
_I
J
m
~
i
1
i
m
~
_
1
~
ACCESS TIME (ns)
3-91
~~
3-92
____________________________
f§§§F~
~#;
________________________________
===,:.=--..... __________________________________________________
__
__
r~~-=
WS27C010L
==r~~
=
~
~
~~~
WAFERSCALE INTEGRATION, INC.
128K X 8 CMOS EPROM
KEY FEATURES
• High Performance CMOS
-
• Simplified Upgrade Path
-
100 ns Access Time
V pp and PGM Are "Don't Care" During
Normal Read Operation
• Fast Programming
• Compatible with JEDEC 27010 and
27C010 EPROMs
• EPI Processing
-
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
• JEDEC Standard Pin Configuration
-
• DESC SMD No. 5962-89614
32 Pin Dip Package
32 Pin Chip Carrier
GENERAL DESCRIPTION
The WS27C010L is a high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 128 K-words of 8 bits each. Its pin-compatibility with byte-wide JEDEC EPROMs enables upgrades
through 8 Mbit EPROMs. The "Don't Care" feature during read operations allows memory expansions from 1M to
8M bits with no printed circuit board changes.
The WS27C010L can directly replace lower density 28-pin EPROMs by adding an A 16 address line and Vee jumper.
During the normal read operation PGM and V pp are in a "don't care" state which allows higher order addresses,
such as A 17 , A 18 , and A 19 to be connected without affecting the normal read operation. This allows memory upgrades
to 8M bits without hardware changes. The WS27C010L will also be offered in a 32-pin plastic Dip with the same upgrade
path.
The WS27C010L provides microprocessor-based systems extensive storage capacity for large portions of operating
system and application software. Its 100-ns access time provides no-wait-state operation with high-performance CPUs
such as the 16-MHz 80186, 16-MHz 68020, or 12-MHz 80386. The WS27C010L offers a single chip solution for the
code storage requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed
from EPROM storage, greatly enhancing system utility.
The WS27C010L is one of an eight product megabit EPROM family. Other byte-wide family members are the faster
WS27C010F, the faster WS57C010F with high bus drive and the WS57C010M EPROM module. Word-wide (64K x 16)
family members are the WS27C210L, the faster WS27C210F, the faster WS57C210F with high bus drive and the
WS57C210M EPROM module.
The WS27C010L is manufactured using WSI's advanced CMOS technology.
The WS27C010L is one member of a high density EPROM Family which ranges in density from 64K to 4 Megabit.
PRODUCT SELECTION GUIDE
PARAMETER
27C010L·10
27C010L·12
27C010L-13
27C010L-15
27C010L·20
Address Access Time (Max)
100 ns
120 ns
130 ns
150 ns
200 ns
Chip Select Time (Max)
100 ns
120 ns
130 ns
150 ns
200 ns
Output Enable Time (Max)
30 ns
35 ns
35 ns
40 ns
40 ns
-----------------------~Jrio-----------------------3-93
---
~~
--~--
~-----~
~~---~
WS27C010L
ABSOWTE MAXIMUM RATINGS*
*Notice: Stresses above those listed under '~bsolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to +125°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vce Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ....................... > 2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
TOLERANCE
Commercial
O°C to +70oC
+5V
±5% or ±10%
Industrial
-40°C to +85°C
+5V
±10%
Military
-55°C to +125°C
+5V
+10%
DC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
SYMBOL
TEST CONDITIONS
PARAMETER
V IL
V IH
Input Low Level
Input High Level
VOL
VOH
ISBP)
Output Low Voltage
Output High Voltage
Vee Standby Current (CMOS)
ISB2
Vee Standby Current
MIN
MAX
UNITS
-0.5
0.8
V
2.0
Vee + 1
0.4
V
V
100
ItA
1
rnA
IOL = 2.1 rnA
lee(l)
Vee Active Current
IOH = -400 itA
CE = Vee ± 0.3V
CE = VIH
_
_
IF=5MHz
CE = OE = VIL I F = 8 MHz
Vpp = Vee
Ipp
Vpp Supply Current
Vpp
Vpp Read Voltage
III
ILO
Input Load Current
Output Leakage Current
3.5
V
50
60
100
Vec -0.4
-1
-10
VIN = 5.5V or Gnd
VOUT = 5.5V or Gnd
rnA
ItA
V
Vee
1
10
ItA
ItA
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
SYMBOL
·10
PARAMETER
MIN
·13
·12
MAX
MIN
MAX
MIN
·15
MAX
MIN
·20
MAX
MIN
MAX
tAee
Address to Output
Delay
100
120
130
150
200
teE
CE to Output Delay
100
120
130
150
200
tOE
OE to Output Delay
30
35
35
40
40
tDF(2)
Output Disable to
Output Float
30
35
35
40
40
tOH(2)
Output Hold From
Addresses, CE or
OE, Whichever
Occurred First
UNITS
ns
0
0
0
0
0
NOTES:
1. The supply current is the sum of lee and Ipp. The maximum current value is with Outputs 0 0 to 0 7 unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven-see timing diagram.
3. CMOS inputs: V 1L = GND ± O.3V, V1H = Vee ± O.3V.
------------------------~Jr;:----------------------3-94
WS27C010L
A.C. WAVEFORMS
V'H - - - - - " " " \ .
ADDRESS
VALID
ADDRESSES
V'L------
V'H _ _ _ _ _ _----11-"""
-------+----'""\
V'H
~--------t~c------~~
HIGH Z
HIGH Z
OUTPUT -------------+H~H
CAPACITANCf(4)
TA = 25°C, f = 1 MHz
SYMBOL
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
CvPp
Vpp Capacitance
CONDITIONS
TYP(5)
MAX
UNITS
VIN = OV
4
6
pF
VOUT = OV
8
12
pF
Vpp = OV
18
25
pF
NOTES:
4. This parameter is only sampled and is not 100% tested.
5. TYPical values are for TA = 25°C and nominal supply voltages.
6. OE may be delayed up to tCE-toE after the falling edge of CE without impact on t CE '
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.0W
-r2A
>
2~
~
2~
~
TEST POINTS (
OA
0.8
0.8
8200
DEVICE
UNDER
TEST
- ' - CL
IA.C. testing Inputs are driven at 2.4V for a Logic "1" and
0.4 V for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and O.IN for a Logic "0."
= 100 pF
C L Includes Jig Capacitance
-----------------------~~;----------------------3-95
WS27C010L
MODE SELECTION
The modes of operation of the WS27C010L are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for Vpp and A9 for device signature.
Table 1. Modes Selection
::----------:S
MODE
Read
Output Disable
CE
OE
PGM
As
Ao
V pp
Vcc
V IL
VIL
X(1)
X
X
X
5.0V
DOUT
X
V IH
X
X
X
X
5.0V
High Z
OUTPUTS
Standby
V IH
X
X
X
X
X
5.0V
High Z
Programming
V IL
V IH
V IL
X
X
Vpp(B)
6.0V
DIN
Program Verify
V IL
V IL
V IH
X
X
Vpp(S)
6.0V
DOUT
Program Inhibit
V IH
X
X
X
X
Vpp(B)
5.0V
High Z
Manufacturer(9)
V IL
V IL
X
VH(B)
V IL
X
5.0V
23 H
Device(9)
V IL
V IL
X
VH(B)
V IH
X
5.0V
C1 H
Signature
NOTES:
7. X can be V1L or V 1H
S. VH = Vpp = 12.75 ± O.25V.
DIP PIN CONFIGURATIONS
8 Mbil
A,s
A,s
A,.
A'2
A7
As
As
A.
A3
A2
A,
Ao
00
4 Mbil
2 Mbil
XXNpp
XX/Vpp
x
A,s
A,.
A'2
A7
A,s
A,.
A'2
A7
f--f--f---
As
As
As
A.
A3
A2
A,
Ao
00
A.
A4
A3
A2
A,
Ao
00
A,.
A'2
A7
As
As
A4
A3
A2
A,
Ao
00
Vpp
A'2
A7
As
As
A4
A3
A2
A,
Ao
00
0,
0,
0,
0,
0,
O2
GND
O2
GND
O2
GND
O2
GND
O2
GND
NOTE:
WS27C010L
27C512L 27C256L
f-f---
f-f---
f-f---
f--G
2 Mbil
4 Mbil
8 Mbil
Vcc
XX/PGM
Vcc
Vec
A,s
A'7
A,.
A'3
As
As
Al1
A,s
A'7
A,.
A'3
As
As
Al1
27C256L 27C512L
..cIPGM
-
3-
-
,-
.i"-
-
A17
A, •
A'3
As
Ag
Al1
Vcc
Vce
A,.
A'3
As
As
Al1
A'4
A'3
As
As
Al1
OE
OENpp
OE
OE
OEtVpp
A'0
A'0
A'0
A10
A,o
CE/PGM CE/PGM
CE
CE/PGM CE/PGM
07
07
07
07
07
Os
Os
O.
Os
-Os
O.
Os
Os
O.
Os
Os
O.
Os
Os
O.
03
03
03
03
03
9. Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C010L pins.
LCC PIN CONFIGURATION
PIN NAMES
Addresses
CE
Chip Enable
OE
Output Enable
Outputs
~; ~ :'i~J~~~~~6
A7
A6
~:
A2
A,
Ao
PGM
Program
XX
Don't Care (During Read)
0,
5
1
:0
6
10
11
29~: A14
28r: A'3
~:~: ~,
24r:
OE
23~:
Ai0
22:: CE
21f: 0 7
12
13
14151617181920
~-:~~~~r-:~-;;-:;-:
TOP
NOTE: Leadless or
Leaded, Plastic or
Ceramic Package
rIll:
------------------------------------~5V.~---------------------------------
3-96
WS27C010L
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 +
- 5°C, Vee
PARAMETER
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During_ _
Programming Pulse (CE = PGM
6.0V +
- 0.25V, Vpp
12.75 -+ 0.25V)
SYMBOLS
MIN
MAX
UNIT
III
-10
10
!-IA
60
mA
Ipp
= Vld
Vee Supply Current
lee
VIL
V IH
Input Low Level
Input High Level
Output Low Voltage During Verify
(lOL = 2.1 mAl
VOL
Output High Voltage During Verify
(lOH = -400 !-IA)
VOH
50
mA
-0.1
0.8
V
2.0
Vee +0.3
V
0.4
V
3.5
V
NOTES: 10. Vcc must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp.
11 Vpp must not be greater than 14 volts Including overshoot During CE = PGM = V ,L, Vpp must not be switched from 5 volts
to 12.75 volts or vice·versa.
12. Dunng power up the PGM pin must be brought high (;>V ,H ) either cOincident with or before power
applied to Vpp.
IS
AC CHARACTERISTICS (TA = 25 +
- 5°C, Vee = 6.0V +- 0.25V, Vpp = 12.75 +- 0.25V)
PARAMETER
SYMBOLS
MIN
tAS
2
tOES
tos
tAH
2
2
0
2
Address Setup Time
Output Enable Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
tOH
tDF
tOE
Chip Disable to Output Float Delay
Data Valid From Output Enable
Vpp Setup Time/CE Setup Time
PGM Pulse Width
TYP
MAX
UNIT
55
55
!-Is
!-IS
!-IS
!-Is
!-Is
ns
ns
4
!-Is
ms
0
tvs/teEs
2
tpw
0.1
PROGRAMMING WA VEFORM
ADDRESSES
==:J
--1
_ I AS _
DATA
---<
HIGH Z
DATA IN STABLE
-los'"
I-IOH ....
I-IOE ..-
Vpp
Vpp
Vee
CE
C
ADDRESS STABLE
tAH
DATA OUT
VALID
--
IOF
f-~
f--
--1
V,H - - - - - - , _ I vs
""
VIL
-ICES'"
V,H
PGM
V,L
V,H
8
i--IOES
~
DE
VIL
______________________________
"1
J
______________________________
f;;~~
.Nih.;
3-97
WS27C010L
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
WS27C010L-10D/5
WS27C010L-10U5
WS27C010L-12C
WS27C010L-12CMB *
WS27C010L-12D
WS27C010L-12DI
WS27C010L-12DMB *
WS27C010L-12J
WS27C010L-12L
WS27C010L-12P
WS27C010L-13CMB *
WS27C010L-13DMB *
WS27C010L-15CI
WS27C010L-15CMB
WS27C010L-15D
WS27C010L-15DI
WS27C010L-15DMB
WS27C010L-15J
WS27C010L-15LMB
WS27C010L-15P
WS27C010L-20C
WS27C010L-20CMB
WS27C010L-20D
WS27C010L-20DMB
WS27C010L-20J
WS27C010L-20P
SPEED
(n8)
100
100
120
120
120
120
120
120
120
120
130
130
150
150
150
150
150
150
150
150
200
200
200
200
200
200
PACKAGE
TYPE
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Pin CERDIp, 0.6"
Pin CLDCC
Pad CLLCC
Pad CLLCC
Pin CERDIP, 0.6"
Pin CERDIp, 0.6"
Pin CERDIp, 0.6"
Pin PLDCC
Pin CLDCC
Pin Plastic Dip, 0.6"
Pad CLLCC
Pin CERDIp, 0.6"
Pad CLLCC
Pad CLLCC
Pin CERDIp, 0.6"
Pin CERDIp, 0.6"
Pin CERDIp, 0.6"
Pin PLDCC
Pin CLDCC
Pin Plastic Dip, 0.6"
Pad CLLCC
Pad CLLCC
Pin CERDIp, 0.6"
Pin CERDIp, 0.6"
Pin PLDCC
Pin Plastic Dip, 0.6"
PACKAGE
DRAWING
D4
L3
C2
C~
D4
D4
D4
J4
L3
P5
C2
D4
C2
C2
D4
D4
D4
J4
L3
P5
C2
C2
D4
D4
J4
P5
OPERATING
RANGE
TEMPERATURE
Vee
WSI
MANUFACTURING
PROCEDURE
Comm'l
Comm'l
Comm'l
Military
Comm'l
Industrial
Military
Comm'l
Comm'l
Comm'l
Military
Military
Industrial
Military
Comm'l
Industrial
Military
Comm'l
Military
Comm'l
Comm'l
Military
Comm'l
Military
Comm'l
Comm'l
±5%
±5%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
M IL-STD-883C
Standard
Standard
Standard
MIL-STD-883C
MIL-STD-883C
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
MIL-STD-883C
Standard
Standard
"These products are Advance Information.
------------------------~Jri----------------------3-98
"----~~----------------~--
WS57C010M
ADVANCE INFORMATION
WAFERSCALE INTEGRATION, INC.
1 Meg (128K x 8) EPROM MODULE
KEY FEATURES
• High-Density 1024K-bit CMOS
EPROM Module
• Fast Programming
-
• Utilizes Four WS57C256F High-Speed
CMOS EPROMs
• Ultra-High Speed Access Time
-
• EPI Processing
-
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
55 ns
• Simplified Upgrade Path From
-
30 Seconds Typical
256K EPROM (32K x 8)
512K EPROM (64K x 8)
• JEDEC Standard Pin Configuration
-
32 Pin Ceramic Side-Brazed Dip Package
GENERAL DESCRIPTION
The WS57C010M is a high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 128 K-words of 8 bits each. The WS57C010M is constructed using four high-performance WS57C256F
EPROMs in a 32-pin side-brazed multi-layer co-fired package. The WS57C256F is manufactured using WSI's advanced
CMOS split-gate EPROM technology. The 55 ns access time of the WS57C010M enables it to operate in high
performance systems.
High performance microprocessors such as the 80386 and 68020 require sub-70 ns memory access times to operate
at or near full speed. The WS57C010M enables such systems to incorporate operating systems and/or applications
software into EPROM. This in turn enhances system utility by freeing up valuable RAM space for data or other program
store and eliminating disk accesses for the EPROM resident routines.
The WS57C010M pin configuration was established to enable memory upgrades from 256K and 512K EPROMs. V pp
is "don't care" and PGM is held low during normal read operation.
The WS57C010M is part of a three product megabit EPROM module family. Other family members are the WS57C210M
(64K x 16) and the WS27C240M (256K x 16).
PRODUCT SELECTION GUIDE
PARAMETER
WS57C010M-55
WS57C010M·70
Address Access Time (Max)
55 ns
70 ns
Chip Select Time (Max)
55 ns
70 ns
Output Enable Time (Max)
35 ns
40 ns
3-99
-~~-----~~
WS57C010M
PIN NAMES
DIP PIN CONFIGURA TIONS
WS57C010M
27C512 27C256
Ao-AI6
Addresses
CE
Chip Enable
OE
Output Enable
A ,S
0 0-07 Outputs
PGM
Program Control
XX
Don't Care (During Read)
Vpp
A'2
A7
A'2
A7
As
Vpp
Vee _ _
A,.
PGM _ _
A,s
XX
A,.
A,. _ _ _
A7
A'3 _ _ _
27C256
27C512
Vee
Vee
A'4
A,.
A'4
A,.
A6
A.
A. _ _ _
As
As
As
As
As
As
Ag
Ag
A4
A4
A.
A11
A11
A11
OE
OE
OEJVpp
A.
A.
A3
A2
A2
A.
A,o
A '0
A '0
A,
A,
A,
CE---
CE
CE
Ao
Ao
Ao
0 7- - -
07
00
0,
00
0,
00
0.
Os
0,
0,
O2
°2
Os
O2
0.
O.
07
06
05
04
GND
GND
GND
0.
O.
O.
NOTE:
Compatible EPROM pin configurallOns are shown In the blocks adjacent to the
WS57C010M pins.
MODE SELECTION
~
PGM
CE
OE
V pp
Vce
Read
VIL
VIL
VIL
X
Vee
DOUT
Output Disable
VIL
X
VIH
X
Vee
High Z
Standby
VIL
VIH
X
X
Vee
High Z
Program
DIN
MODE
OUTPUTS
V IL
V IL
VIH
Vpp
Vee
Program Verify
VIH
X
V IL
Vpp
Vee
DOUT
Program Inhibit
VIH
VIH
V IH
Vpp
Vee
High Z
NOTE: X can be either V IL or VIH .
FUNCTIONAL BLOCK DIAGRAM
Ao-,.
tIS
Vee _
V•• _
Vpp
2
OE
tIS
f15
Ao-A,.
Ao-A,.
Ao-A,.
Ao-A,.
WS57C2S6F
WS57C256F
WS57C256F
WSS7C256F
1/00-7
1/00 _7
1/00 _7
I
I
-----.
CE
PGM
t 15 ,
DECODER
fE/PGM
OE
1/00 _7
I
I
i
a
1/00_7
---------------------~~i--------------------3-100
WS57C010M
"Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
ABSOWTE MAXIMUM RATlNGS*
Storage Temperature ........... -65°C to +125°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
V pp with Respect to Ground ....... LO.6V to +14V
Vee Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ........................ >2000V
NOTICE: Specifications contained within the following tables are subject to change.
OPERATING RANGE
TEMPERATURE
Vce
Comm'l
RANGE
0° to +70°C
+5V ± 5%
Military
-55° to +125°C
+5V ± 10%
READ OPERATION
DC CHARACTERISTICS Over Operating Range (See Above)
SYMBOL
PARAMETER
CONDITIONS
III
Input Load Current
ILO
Output Leakage Current
= 5.5V
= 5.5V
IpP1
V pp Load Current
ISB (TTL)
Vee Current Standby
VIN
VOUT
Vpp
';;
MIN
Vee
= VIH
CE = V IH
CE = OE = V IL
CE
ISB (CMOS)
Vee Current Standby
lee (TTL)
Vee Current Active
V IL
Input Low Voltage
-0.1
V IH
Input High Voltage
2.0
VOL
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
V pp
V pp Read Voltage
= 16 mA
= -4 mA
MAX
UNITS
10
~A
10
~
10
~A
20
mA
5
mA
200
mA
+0.8
V
Vee +1
V
0.4
V
2.4
V
-0.1
Vce+ 1
V
AC CHARACTERISTICS Over Operating Range (See Above)
SYMBOL
CHARACTERISTICS
tAee
Address to Output Delay
tCE
CE to Output Delay
tOE
tDF(l)
OE to Output Delay
tOH
TEST
CONDITIONS
CE
57C010M-70
MIN
= OE = VIL
= VIL
CE = V IL
CE = V IL
0
= OE = VIL
0
OE
OE High to Output Float
Output Hold from
Addresses CE or OE
Whichever Occurred First
57C010M-55
MIN
CE
MAX
MAX
UNITS
55
70
ns
55
70
ns
35
40
ns
40
ns
35
0
0
ns
NOTE: 1. ThiS parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven-see
timing diagram.
-------------------------~Jr;------------------------3-101
WS57C010M
AC READ TIMING DIAGRAM
V'H _ _ _ _ __
ADDRESS
VALID
ADDRESSES
V'L-----V'H
--------1--'"'\
V'H _ _ _ _ _ _----1_______
1+-----
OUTPUT
I ACC
-----11--1
HIGH Z
-------------"'t-~t_t''t'1.
HIGH Z
PGM = LOW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NOTES:
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE '
CAPACITANCE
SYMBOL
PARAMETER
C IN
Input Capacitance
COUT
Output Capacitance
CvPp
V pp
NOTE:
CONDITIONS
TYP(2,4)
MAX
UNITS
=
20
24
54
30
32
75
pF
VIN
VO UT
Capacitance
V pp
=
=
OV
OV
OV
pF
pF
4. Typical values are for TA = 25°C and nominal supply voltages, f = 1 MHz.
AC TESTING INPUT/OUTPUT WAVEFORM
AC TESTING LOAD CIRCUIT
2.0lV
T
3.0
2~
o
0.8 /
~
2~
TEST POINTS
Jf
~0.8
DEVICE
UNDER
TEST
~
~
I
980
~ OUT
CL =30pF
--
A.C. testing inputs are driven at 3.0V for a Logic "1" and
OV for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and O.BV for a Logic "0."
CL includes Jig Capacitance
-----------------------------~Jr;----------------------------
3-102
~----
-~~-------
WS57C010M
PROGRAMMING INFORMATIONl5,6,7)
DC CHARACTERISTICS (TA = 25 ± 5°C,
PARAMETER
Vee = 5.5V
±
5%, Vpp = 12.5 ± 0.5V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
(VIN = Vee or Gnd)
III
-10
10
!lA
Vpp Supply Current During_ _
Programming Pulse (CE = PGM = Vld
Ipp
60
mA
Vee Supply Current
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL = 16 mA)
.
lee
V IL
V IH
30
mA
-0.1
0.8
V
2.0
Vee +0.3
V
0.45
V
VOL
Output High Voltage During Verify
(loH = -4 mA)
V
2.4
VOH
NOTES: 5. Vee must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp.
6. Vpp must not be greater than 14 volts including overshoot. During eE = PGM = V1L , Vpp must not be switched from 5 volts
to 12.5 volts or vice·versa.
7. During power up the PGM pin must be brought high
AC CHARACTERISTICS
(~VIH)
either coincident with or before power is applied to Vpp.
(TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 12.5 ± 0.5V)
SYMBOLS
MIN
Address Setup Time
PARAMETER
tAS
2
Chip Enable Setup Time
teEs
2
IlS
Ils
Output Enable Setup Time
Data Setup Time
tOES
tos
2
2
Ils
IlS
Address Hold Time
tAH
0
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
IlS
Il s
ns
Data Valid From Output Enable
tOE
Vpp Setup Time
tvs
tpw
PGM Pulse Width
TYP
MAX
130
130
ns
4
Il S
ms
2
0.1
0.2
UNIT
NOTE: Single shot programming algorithms should use a single 4 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
DATA
Vpp
Vpp
Vee
V,H
CE
VIL
V,.
PGM
VIL
ae
V,H
VIL
-----------------------~Jr;-----------------------3-103
~3_1~M~--------------------~Jr;------------------------
WS27C010F
ADVANCE INFORMATION
WAFERSCALE INTEGRATION, INC.
1 Meg (128K x 8) CMOS EPROM
KEY FEATURES
• High Performance
-
• EPI Processing
55 ns
-
• Simplified Upgrade Path
-
Vpp and PGM Are "Don't Care" During
Normal Read Operation
Expandable to 8M Bits
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
• JEDEC Standard Pin Configuration
-
32 Pin Dip Package
• Pin Compatible with WS27C010L
GENERAL DESCRIPTION
The WS27C010F is a high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 128 K-words of 8 bits each. The 55 ns access time of the WS27C010F enables it to operate in high
performance systems. The "Don't Care" feature during read operations enables memory expansions up to 8M bits
with no printed circuit board changes.
High performance microprocessors such as the 80386 and 68020 require 55 ns memory access times to operate
at or near full speed. The WS27C010F enables such systems to incorporate operating systems and/or applications
software into EPROM. This enhances system utility by freeing up valuable RAM space for data or other program
store and eliminating disk accesses for the EPROM resident routines.
The WS27C010F pin configuration was established to enable memory upgrades to 8M bits without hardware changes
to the printed circuit board. Pins 1 and 31 are "don't care" during normal read operation. This enables higher order
addresses to be connected to these pins (see DIP Pin Configurations). When higher density memories are required,
the printed circuit board is ready to accept the higher density device with no hardware changes.
The WS27C010F is part of an eight product megabit EPROM family. Byte-wide family members (128K x 8) are the
WS27C010L, WS27C010F (described herein) and WS57C010F as the high-speed version. Word-wide (64K x 16) family
members are the WS27C210L, WS27C210F and the high-speed WS57C210F. The WS57C010M and WS57C210M are
high speed, high bus drive EPROM modules.
The WS27C010F is manufactured using WSl's advanced CMOS technology.
PRODUCT SELECTION GUIDE
PARAMETER
WS27C010F-55
WS27C010F-70
WS27C010F·90
WS27C010F·10
Address Access Time (Max)
55 ns
70 ns
90 ns
100 ns
Chip Select Time (Max)
55 ns
70 ns
90 ns
100 ns
Output Enable Time (Max)
25 ns
25 ns
30 ns
30 ns
3-105
WS27C010F
ABSOWTE MAXIMUM RATINGS*
-Notice: Stresses above those listed under ''Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Storage Temperature ........... -65°C to +125°C
Voltage on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vee Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ........................ >2000V
NOTICE: Specifications contained within the following tables are subject to change.
OPERATING RANGE
RANGE
TEMPERATURE
Vee
0° to +70°C
+5V ± 5%
Industrial
-40° to +85°C
+5V ± 10%
Military
-55° to +125°C
+5V ± 10%
Comm'l
READ OPERATION
DC CHARACTERISTICS
OOC';;; TA .;;; +70°C; Vee (Comm'I/Military) = +5V ± 10%.
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
VIN = 5.5V
10
itA
VOUT = 5.5V
10
itA
Vpp Load Current
Vpp';;; Vee
10
itA
ISBTIL
Vee Current Standby
CE = VIH
2
rnA
ISB CMOS
Vee Current Standby
CE = VIH
lee(l)
Vee Current Active
500
40(3)
rnA
Vil
Input Low Voltage
-0.1
+0.8
V
VIH
Input High Voltage
2.0
Vee +1
V
VOL
Output Low Voltage
IOl = 2.1 rnA
0.4
V
VOH
Vpp(1)
Output High Voltage
IOH = -400!lA
2.4
Vee = 5.0V ± 0.25
-0.1
III
Input Load Current
ILO
Ipp(l)
Output Leakage Current
CE = OE = V il
Vpp Read Voltage
AC CHARACTERISTICS
-55
V
Vee +1
-70
TEST
CONDITIONS
tAee
Address to Output Delay
CE = OE = Vil
55
tCE
CE to Output Delay
OE = Vil
tOE
tOF(2)
OE to Output Delay
CE = Vil
OE High to Output Float
CE = Vil
tOH
V
O°C .;;; T A';;; + 70°C
CHARACTERISTICS
SYMBOL
itA
Output Hold From
Addresses CE or OE
CE = OE = Vil
Whichever Occurred First
MIN
0
0
MAX
MIN
-90
MAX
MIN
-10
MAX
MIN
UNITS
MAX
70
90
100
55
70
90
100
25
25
30
25
0
0
25
0
0
30
30
0
ns
30
0
NOTES:
1. Vpp should be at a TIL level except during programming. The supply current would then be the sum of Icc and Ipp. The maximum current
value is with Outputs 0 0 to 0 7 unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data Is no longer driven-see timing diagram.
3. Add 2 mNMHz for A.e. power component.
---------------------~Jr;.--------------------3-106
WS27C010F
AC READ TIMING DIAGRAM
V,H-----~
ADDRESS
VALID
ADDRESSES
V,L - - - - - - - - - -
V,H
-----------~I-'"'
V,H
-------------f--------'""
~--------t~c------~~
OUTPUT _____________________
HIGH Z
CAPACITANCE(4) TA
SYMBOL
HIGH Z
~~~~
25°C, f = 1 MHz
PARAMETER
C IN
Input Capacitance
COUT
Output Capacitance
CvPp
Vpp Capacitance
CONDITIONS
TYP(5)
MAX
UNITS
VIN = OV
4
6
pF
VOUT = OV
8
12
pF
Vpp = OV
18
25
pF
NOTES:
4. This parameter IS only sampled and is not 100% tested.
5. TYPical values are for TA = 25°C and nominal supply voltages.
6. OE may be delayed up to tCE-t OE after the falling edge of CE without impact on t CE '
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.04V
-
~
2.4
TEST POINTS
0.8/
0.45
~
2.0
2.0
<
~
DEVICE
UNDER
TEST
0.8
8200
,... OUT
....... c L = 100 pF
I--
A.C. testing inputs are driven at 2.4V for a Logic "1" and
0.45V for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and O.BV for a Logic "0."
CL Includes Jig Capacitance
"--I.E
----------------------------~.,,---------------------------3-107
WS27C010F
DIP PIN CONFIGURATIONS
8 Mbil
4 Mbll
2 Mbil
A19
A1S
A15
A12
A7
As
A5
A4
A3
A2
Al
Ao
00
01
02
GND
XXlVpp
A 1S
A15
A12
A7
As
A5
A4
A3
A2
Al
Ao
00
01
02
GND
XXlVpp
A1S
A 15
A12
A7
As
A5
A4
A3
A2
Al
Ao
00
01
02
GND
27512
WS27C010F
27256
27256
Vee
XXlPGM
A15
A12
A7
As
A5
A4
A3
A2
Al
Ao
00
01
02
GND
Vpp
A12
A7
As
A5
A4
A3
A2
Al
Ao
00
01
02
GND
XX
A,.
A13
A.
As
A"
OE
A,.
CE
A.
0.
0,
0.
GND
°70.
0.
0.
0,
Vee
A14
A 13
As
Ag
All
OE
A 10
CE
07
Os
05
04
03
27512
2 Mbil
Vee
XX/PGM
A17
Vee
A14
A14
A 13
A13
As
As
Ag
Ag
All
All
OENpp
OE
A 10
Al0
CE
CE
07
07
06
Os
05
05
04
04
03
03
4 Mbil
8 Mbil
Vee
A 1S
A17
A14
A13
As
Ag
All
OE
Al0
Vee
A 1S
A17
A14
A 13
As
Ag
All
OENpp
A 10
CE
07
06
05
04
03
CE
07
06
05
04
03
NOTE: Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C010F pins.
PIN NAMES
Ao-A16
Addresses
CE
Chip Enable
OE
Output Enable
0 0-07
Outputs
PGM
Program
XX
Don't Care (During Read)
-------------------------~Jr;-------------------------3-108
WS27C210L
PRELIMINARY
WAFERSCALE INTEGRATION, INC.
1 Meg (64K
x 16) CMOS EPROM
KEY FEATURES
• Ultra-High Performance
-
• EPI Processing
100 ns
-
• Simplified Upgrade Path
-
Vpp and PGM Are "Don't Care" During
Normal Read Operation
Expandable to 8M Bits
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
• JEDEC Standard Pin Configuration
-
40 Pin Dip Package
44 Pin Chip Carrier
GENERAL DESCRIPTION
The WS27C210L is an ultra-high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 64 K-words of 16 bits each. The 100 ns access time of the WS27C210L enables it to operate in
high performance systems. The "Don't Care" feature during read operations enables memory expansions up to 8M
bits with no printed circuit board changes.
High performance microprocessors such as the 80386 and 68020 require sub-120 ns memory access times to operate
at or near full speed. The WS27C210L enables such systems to incorporate operating systems and/or applications
software into EPROM. This in turn enhances system utility by freeing up valuable RAM space for data or other program
store and eliminating disk accesses for the EPROM resident routines.
The WS27C210L pin configuration was established to allow memory upgrades to 8M bits without hardware changes
to the printed circuit board. Pins 1 and 39 are "don't care" during normal read operation. This enables higher order
addresses to be connected to these pins. When higher density memories are required, the printed circuit board is
ready to accept the higher density device with no hardware changes.
The WS27C210L is part of a high density EPROM family which spans densities from 64K to 4 Meg.
The WS27C210L is manufactured using WSl's advanced CMOS technology.
PRODUCT SELECTION GUIDE
PARAMETER
27C210L-10
27C210L·12
27C210L·15
27C210L·20
Address Access Time (Max)
100 ns
120 ns
150 ns
200 ns
Chip Select Time (Max)
100 ns
120 ns
150 ns
200 ns
Output Enable Time (Max)
30 ns
35 ns
40 ns
40 ns
3-109
WS27C210L
ABSOWTE MAXIMUM RATINGS·
·Notlce: Stresses above those listed under '~bsolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Storage Temperature ........... -65°C to + 125°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
V cc Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ....................... > 2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
TOLERANCE
Commercial
O°C to +70°C
+5V
±5% or ±10%
-55°C to +125°C
+5V
+10%
Military
DC READ CHARACTERISTICS Over Operating Range with Vpp = Vce.
SYMBOL
MIN
MAX
UNITS
V IL
Input Low Level
PARAMETER
TEST CONDITIONS
-0.5
0.8
V
V IH
Input High Level
2.0
VOL
VOH
IsBP)
Output Low Voltage
Vee + 1
0.4
V
Output High Voltage
IOH = -400 ~
Vee Standby Current (CMOS)
ISB2
Vee Standby Current
lee(l)
Vee Active Current
CE = Vee + 0.3V
CE = VIH
_
_
IF=5MHz
CE = OE = V IL F = 8 MHz
Vpp = Vee
IOL = 2.1 rnA
3.5
V
100
1
60
I
Ipp
Vpp Supply Current
Vpp
Vpp Read Voltage
III
ILo
Input Load Current
VIN = 5.5V or Gnd
Output Leakage Current
VO UT = 5.5V or Gnd
V
70
100
Vee -0.4
-1
Vee
1
-10
10
~
rnA
rnA
~
V
!lA
!lA
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
SYMBOL
PARAMETER
·10
MIN
·12
MAX
MIN
·20
·15
MAX
MIN
MAX
MIN
MAX
tAee
Address to Output
Delay
100
120
150
200
teE
CE to Output Delay
100
120
150
200
tOE
OE to Output Delay
30
35
40
40
tOF(2)
Output Disable to
Output Float
30
35
40
40
tOH(2)
Output Hold From
Addresses, CE or
OE, Whichever
Occurred First
UNITS
ns
0
0
0
0
NOTES:
1. The supply current IS the sum of Icc and Ipp. The maximum current value is with Outputs 0 0 to 0 7 unloaded.
2. This parameter is only sampled and IS not 100% tested. Output Float is defined as the pOint where data is no longer driven-see timing diagram.
3. CMOS inputs: VIL = GND ± 0.3V, V IH = Vee ± 02V.
---------------------~~i---------------------
3-110
WS27C210L
AC READ TIMING DIAGRAM
V,H
------,.
ADDRESS
VALID
ADDRESSES
V,L
------
V,H
-------if-""
------.....jf----_
V,H
D
~--------t~c------~~
HIGH Z
HIGH Z
-------------+H++-<
OUTPUT
NOTES:
4. This parameter IS only sampled and is not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages.
6. OE may be delayed up to tCE -tOE aiter the falling edge of CE without Impact on tCE
CAPACITANCEf4) TA
= 25°C. f = 1 MHz
PARAMETER
SYMBOL
CONDITIONS
TYP(5)
MAX
UNITS
VIN = OV
4
6
pF
Input Capacitance
CIN
CO UT
Output Capacitance
VO UT = OV
8
12
pF
CvPp
Vpp Capacitance
Vpp = OV
18
25
pF
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.04V
..,..
2.4
;>
OA
0.8
:>~
2.0
2.0
TEST POINTS {
0.8
DEVICE
UNDER
TEST
8200
~
I
CL
= 100pF
--
A C. testing Inputs are driven at 2.4V for a Logic "1" and
0.4 V for a Logic "0." Timing measurements are made at 2 OV
for a Logic "1" and 0.6V for a Logic "0."
=
CL
100 pF
C L Includes Jig Capacitance
---------------------~Jr;----------------------3-111
WS27C210L
DIP PIN CONFIGURATIONS
8 Mbit
4 Mbit
2 Mbit
512K
57C257
XXNpp XXlVpp XXNpp XXNpp Xx/Vpp
A,S
CeipOM CEJPGM
WS27C210L
57C65
CE
CE
CE
eE
o,s
0'5
o,s
o,s
o,s
o,s
0'4
0'4
0'4
0'4
0'4
0'4
XXN pp
-.
-.
- iCE
0,.
0,.
- c0,.
- c0,.
--
Vee
57C65
57C257
512K
2 Mbit
Vee
Vee
Vee
Vee
4 Mbit 8 Mbit
XXIPGM- Xx/PGM Xx/PGM Xx/PGM XXlPGM
.•
Ne
--
--3
Ne
Ne
Ne
A'6
Vee
Vee
A'7
A'7
A,s
Ne
Ne
Ne
A,s
A'6
A,s
Ne
Ne
A'4
A'4
A'4
A'4
Ne
A'3
A'3
A'3
A'3
A'3
Ne
A'2
Al1
A'2
Al1
Al1
A'2
Al1
A'2
Al1
A'2
Al1
A,o
A,o
A,o
A,o
A,o
Am
Ag
Ag
Ag
Ag
Ag
Ag
GND
GND
GND
GND
GND
GND
A,s
0'3
0'3
0'3
0'3
0'3
0'3
0'2
0 11
0'2
0 11
0'2
0'2
0 11
0'2
0"
0'2
0 11
0'0
Og
0'0
Og
0'0
Og
0'0
Og
0'0
Og
0'0
Og
OS
Os
Os
Os
Os
Os
- ,O.
.-
GND
GND
GND
GND
GND
GND
- GNO
0-
07
07
07
07
07
07
- I0 7
-
As
As
As
As
As
As
06
Os
0&
0&
Os
0&
-
A7
A7
A7
A7
A7
A7
Os
05
Os
Os
Os
Os
As
As
A6
As
As
04
04
04
04
04
04
- ,O.
As
As
As
As
As
As
As
03
03
03
03
03
03
- 'O.
A4
A4
A4
A4
A4
A4
O2
O2
O2
O2
O2
O2
A3
A3
A3
A3
A3
A3
0,
0,
0,
0,
0,
0,
A2
A2
A2
A2
A2
A2
00
00
00
00
00
00
A,
A,
A,
A,
A,
A,
OEN pp
1m
1m
1m
1m
O!
Ao
Ao
Au
Ao
Ao
Ao
NOTE:
0"
- ,0"
-.0,.
- IO.
- ,O.
- ,O.
- ,O.
-
0,
O.
OE
-I
.-
,-
--
Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C210L pins.
PIN NAMES
LeC PIN CONFIGURATION (TOP)
Ao-A15
Addresses
CE
Chip Enable
OE
Output Enable
0 0-0 15
Outputs
NC
No Connection
XX
Don't Care (During Read)
PGM
Program
!l
1:::&
a.
a.
8
i2 U :O':!
ooou~z>>V ,H ) either cOincident with or before power IS applied to Vpp .
8.
Vee
V pp
AC CHARACTERISTICS (TA
= 25 + 5°C, Vee = 6.2V +
- 0.25V, Vpp = 12.75 +- 0.25V)
-
PARAMETER
SYMBOLS
MIN
Address Setup Time
Output Enable Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Chip Disable to Output Float Delay
Data Valid From Output Enable
tAS
2
2
2
0
2
tOES
tos
tAH
tOH
tOF
TYP
MAX
~s
~s
~s
~s
0
tOE
Vpp Setup Time/CE Setup Time
tvs/teEs
tpw
PGM Pulse Width
UNIT
55
55
J.ls
ns
ns
4
J.ls
ms
2
0.1
PROGRAMMING WA VEFORM
ADDRESSES
~
_~
f.- lAS ..
DATA _ _
DATA
IN STABLE
HIGH Z
I-IOH ....
f.-I os -
I-IoE . .
V ••
V••
CE
vcc
K=
ADDRESS STABLE
tAH
DATA OUT
VALID
-
IDF
I-Jr--
I--
--1
VIH~ f.-I vs V'L
t- ICES"
V,H
PGM
V'L
Ipw
V,H
OE
V'L
_IOES~
~
/
-----------------------------------~~~--------------------------------------3-113
WS27C210L
MODE SELECTION
The modes of operation of the WS27C210L are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for Vpp and on As for device signature.
~S
CE
.
MODE
Read
Output Disable
Standby
Programming
Program Verify
Program Inhibit
Manufacturer(12)
Signature
Device(12)
NOTES:
II
10. X can be V1L or V1H
Table 1. Modes Selection
-OE
PGM
As
Ao
Vpp
Vcc
OUTPUTS
VIL
X
VIH
VIL
VIL
VIH
VIL
VIL
VIH
X
VIH
VIL
X
X(10)
X
X
X
X
X
X
VIL
X
X
X
Vpp
Vpp
Vpp
X
5.0V
5.0V
5.0V
6.2V
6.2V
6.2V
5.0V
DOUT
High Z
23 H
VIL
VIL
X
X
X
X
X
X
X
VH(11)
VH(11)
DOUT
High Z
VIL
X
X
VIL
VIH
X
X
VIH
X
5.0V
C9 H
High Z
DIN
11. VH = Vpp
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
WS27C210L-10D/5 *
WS27C210L-10J/5 *
WS27C210L-12CMB *
WS27C210L-12D
WS27C210L-12DMB *
WS27C210L-12J
WS27C210L-12L
WS27C210L-12LMB *
WS27C210L-15CMB
WS27C210L-15D
WS27C210L-15DMB
WS27C210L-15J
WS27C210L-15L
WS27C210L-15LMB
WS27C210L-20CMB
WS27C210L-20D
WS27C210L-20DMB
WS27C210L-20J
WS27C210L-20L
WS27C210L-20LMB
SPEED
(ns)
100
100
120
120
120
120
120
120
150
150
150
150
150
150
200
200
200
200
200
200
PACKAGE
TYPE
40
44
44
40
40
44
44
44
44
40
40
44
44
44
44
40
40
44
44
44
Pin CERDIP,
Pin PLDCC
Pad CLLCC
Pin CERDIp,
Pin CERDIp,
Pin PLDCC
Pin CLDCC
Pin CLDCC
Pad CLLCC
Pin CERDIP,
Pin CERDIp,
Pin PLDCC
Pin CLDCC
Pin CLDCC
Pad CLLCC
Pin CERDIp,
Pin CERDIP,
Pin PLDCC
Pin CLDCC
Pin CLDCC
PACKAGE
DRAWING
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
D3
J2
C3
D3
D3
J2
L4
L4
C3
D3
D3
J2
L4
L4
C3
D3
D3
J2
L4
L4
OPERATING
RANGE
TEMPERATURE
Vce
Comm'l
Comm'l
Military
Comm'l
Military
Comm'l
Comm'l
Military
Military
Comm'l
Military
Comm'l
Comm'l
Military
Military
Comm'l
Military
Comm'l
Comm'l
Military
±5%
±5%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
WSI
MANUFACTURING
PROCEDURE
Standard
Standard
MIL-STD-883C
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
MIL-STD-883C
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
MIL-STD-883C
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
'These products are Advance Information.
------------------------~Jr;--------------------3-114
--
-----
-
-~
-------
-
-
---
WS57C210M
PRELIMINARY
WAFERSCALE INTEGRATION, INC.
1 Meg (64K x 16) EPROM MODULE
KEY FEATURES
• High-Density 64K x 16 CMOS
EPROM Module
• Fast Programming
-
• Utilizes Four WS57C256F High-Speed
CMOS EPROMs
• Ultra-High Speed Access Time
-
• EPI Processing
-
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
55 ns
• JEDEC Standard Pin Configuration
• Simplified Upgrade Path From
-
15 Seconds Typical
-
WS57C65 (4K x 16 EPROM)
WS57C257 (16K x 16 EPROM)
40 Pin Ceramic Side-Brazed Dip Package
GENERAL DESCRIPTION
The WS57C210M is a high performance, 1,048,676-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 64 K-words of 16 bits each. The WS67C210M is constructed using four high-performance WS57C256F
EPROMs in a 40-pin side-brazed multi-layer co-fired package. The WS57C256F is manufactured using WSl's advanced
CMOS split-gate EPROM technology. The 55 ns access time of the WS57C210M enables it to operate in high
performance systems.
High performance microprocessors such as the 80386 and 68020 require sub-70 ns memory access times to operate
at or near full speed. The WS57C210M enables such systems to incorporate operating systems and/or applications
software into EPROM. This in turn enhances system utility by freeing up valuable RAM space for data or other program
store and eliminating disk accesses for the EPROM resident routines.
The WS57C210M pin configuration was established to enable memory upgrades from WS57C65 or WS57C257. Vpp
is "don't care" and PGM is held low during normal read operation.
.
The WS57C210M is part of a three product EPROM module family. Other family members are the WS57C010M
(128K x 8) and the WS27C240M (256K x 16).
PRODUCT SELECTION GUIDE
PARAMETER
WS57C210M-55
WS57C210M-70
WS57C210M-90
Address Access Time (Max)
55 ns
70 ns
90 ns
Chip Select Time (Max)
55 ns
70 ns
90 ns
Output Enable Time (Max)
35 ns
40 ns
40 ns
3-115
WS57C210M
PIN NAMES
DIP PIN CONFIGURATIONS
WS57C210M
WS57C257 WS57C65
Ao-A15
Addresses
CE
Chip Enable
XXNpp
r-v PP
~
CE
c
r- E
OE
Output Enable
0 0-0 15
Outputs
PGM
Program Control
0'3
0'3
No Connection
0'2
0"
0'2
0 11
0'0
Og
0'0
Og
Os
Os
GND
NC
XX
0,.
0,.
Don't Care (During Read)
WS57C65 WS57C257
XXNpp
0,.
0,.
r- 0
r-0
,.
,.
r- 0 '3
r- 0 '2
Vee
Vee
XX/PGM
XX/PGM
NC
NC
NC
NC
NC
NC
NC
NC
A'3
Ag
Ag
GND
r- 0 11
r-0 '0
r--'Og
r--'D.
f-GN D
GND
GND
07
r '0 7
As
As
06
Os
- 'O.
A7
A7
D.
D.
- 'D.
As
As
O.
A.
A.
O.
A4
A4
A3
A3
07
04
04
~,
03
03
-'
O2
O2
- 'O2
A'2
A"
A"
A10
A,o
0,
0,
- '0,
A2
A2
00
00
- '0 0
A,
A,
Of!
llE
OE
Ao
Ao
-.
NOTE: Compatible EPROM pin configurations are shown in the blocks
adjacent to the WS57e210M pins,
MODE SELECTION
~
PGM
CE
OE
Vpp
Vcc
Read
VIL
VIL
VIL
X
Vce
DOUT
Output Disable
VIL
X
V IH
X
Vee
High Z
Standby
VIL
VIH
X
X
Vee
High Z
Program
VIL
VIL
VIH
Vpp
Vee
DIN
Program Verify
VIH
X
VIL
Vpp
Vee
DOUT
VIH
VIH
VIH
Vpp
Vee
High Z
MODE
Program Inhibit
NOTE: X can be either V IL or VIH ,
OUTPUTS
FUNCTIONAL BLOCK DIAGRAM
Vee
V ••
Vpp
CE
PGM
OE
--
1
15
1
15
1
AO-A14
Ao-A'4
AO-A14
Ao-A'4
WS57C256F
WS57C256F
WS57C256F
WS57C256F
1/00_7
1/00 _7
1/0 0_7
I
I
Ao-,.
DECODER
1
'5
1
'5
~
OE
1/00-7
I
t
1/00_7
I
t
1/08-1.
---------------------~~;'--------------------3·116
WS57C210M
"Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
ABSOLUTE MAXIMUM RAT/NGS*
Storage Temperature ........... -65°C to +125°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vcc Supply Voltage with
Respect to Ground .............. -0.6V to + 7V
ESD Protection ........................ >2000V
NOTICE: Specifications contained within the following tables are subject to change.
OPERATING RANGE
TEMPERATURE
Vcc
Comm'l
RANGE
0° to +70°C
+5V ± 5%
Military
-55° to +125°C
+5V ± 10%
READ OPERATION
DC CHARACTERISTICS Over Operating Range (See Above)
SYMBOL
PARAMETER
CONDITIONS
III
Input Load Current
ILO
Output Leakage Current
= 5.5V
VOUT = 5.5V
IpP1
Vpp Load Current
ISB (TTL)
Vcc Current Standby
ISB (CMOS)
Vcc Current Standby
MIN
VIN
Vpp
CE
""
Vcc
= V IH
CE = VIH
CE = OE = VIL
MAX
UNITS
10
I-lA
10
I-lA
10
I-lA
20
mA
5
mA
200
mA
Icc (TTL)
Vcc Current Active
VIL
Input Low Voltage
-0.1
+0.8
V
VIH
Input High Voltage
2.0
Vee+ 1
V
VOL
Output Low Voltage
0.4
V
VOH
Output High Voltage
Vpp
Vpp Read Voltage
IOL
IOH
= 8 mA
= -2 mA
2.4
V
-0.1
V
V ee +1
AC CHARACTERISTICS Over Operating Range (See Above)
SYMBOL
CHARACTERISTICS
tACC
Address to Output Delay
teE
CE to Output Delay
tOE
t DF(1)
OE to Output Delay
tOH
NOTE:
TEST
CONDITIONS
CE
57C210M-70
57C210M-90
MIN
MIN
MIN
= OE = V IL
= VIL
CE = VIL
CE = VIL
0
= OE = V IL
0
OE
OE High to Output Float
Output Hold from
Addresses CE or OE
Whichever Occurred First
57C210M-55
CE
MAX
UNITS
MAX
MAX
55
70
90
ns
55
70
90
ns
35
40
40
ns
40
ns
35
0
0
40
0
0
ns
1. ThiS parameter 15 only sampled and is not 100% tested. Output Float IS defined as the pOint where data IS no longer driven-see
timing diagram.
-..,.---------------------------------~Jr~'--------------------------------3-117
WS57C210M
AC READ TIMING DIAGRAM
VIH - - - - - " " "
ADDRESS
VALID
ADDRESSES
VIL-----J
------t-"\.
VIH ~,
VIH
------+---'""""'\.
~-------t~c------~
HIGH Z
OUTPUT
HIGHZ
-------------1+H~
PGM=~W---------------------------------
CAPACITANCf(2)
PARAMETER
SYMBOL
CIN
Input Capacitance
COUT
Output Capacitance
Cvpp
Vpp Capacitance
NOTES:
CONDITIONS
TYP(3)
MAX
UNITS
VIN = OV
20
20
30
30
pF
VOUT = OV
Vpp = OV
54
75
pF
pF
2. ThiS parameter IS only sampled and IS not 100% tested.
3. Typical values are for TA = 25°C and nominal supply voltages, f = 1 MHz.
4. OE may be delayed up to tCE-tOE after the falling edge of CEO without impact on tCE'
AC TESTING INPUT/OUTPUT WAVEFORM
AC TESTING LOAD CIRCUIT
2,01V
...,...
3.0
2.0
/
o
0.8
~
>
2.0
TEST POINTS (
0,8
DEVICE
UNDER
TEST
~
i
1600
,.. OUT
CL =30 PF
--
A,C. testing inputs are driven at 3.0V for a Logic "1" and
. OV for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and O,BV for a Logic "0."
C L includes Jig Capacitance
---------------------------~Jri~--------------------3·118
WS57C210M
PROGRAMMING INFORMATIONl5,6,7)
DC CHARACTERISTICS (TA = 25 ± 5°C,
Vee
PARAMETER
5.5V
5%, Vpp = 12.5
±
0.5V)
SYMBOLS
MIN
MAX
UNIT
III
-10
10
~
120
mA
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During_ _
Programming Pulse (CE = PGM
±
Ipp
= VILl
Vee Supply Current
lee
VIL
V IH
Input Low Level
Input High Level
Output Low Voltage During Verify
(lOL = 16 mAl
Output' High Voltage During Verify
(loH = -4 mAl
60
mA
-0.1
0.8
V
2.0
Vee +0.3
V
0.45
V
VOL
VOH
2.4
V
NOTES: 5.
Vee must be applied either cOincidentally or before Vpp and removed either coinCidentally or after Vpp.
6. V pp must not be greater than 14 volts including overshoot. During CE = PGM = V IL , Vpp must not be switched from 5 volts
to 12.5 volts or vice-versa.
7. During power up the PGM pin must be brought high (~VIH) either coincident with or before power is applied to V pp •
AC CHARACTERISTICS
(TA
= 25
= 5.5V ±
-+ 5°C, Vee
PARAMETER
Address Setup Time
Chip Enable Setup Time
Output Enable Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
5%, V PP
SYMBOLS
MIN
tAS
2
2
2
2
0
2
0
teE
Chip Disable to Output Float Delay
Data Valid From Output Enable
Vpp Setup Time
tOES
tos
tAH
tOH
tDF
tOE
TYP
MAX
UNIT
IlS
IlS
IlS
IlS
IlS
130
130
2
tvs
tpw
PGM Pulse Width
= 12.5 ± 0.5V)
IlS
ns
ns
IlS
0.2
0.1
4
ms
NOTE: Single shot programming algorithms should use a single 4 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
~
ADDRESS STABLE
~
I- t.....
DATA _ _ _
v..
v..
CE
vee
V'L
V,L
V,H
DE
DATA IN STABLE
1-10.--
HIGHZ
1
'l
1+ to. +l
1+ IoH ....
--1
tAH
DATA OUT
VALID
-
IoF
K=
I+-
~
l-
---1 ~tvs""
VIH~
V,H
PGM
I
V,L
I-- tc•• +
~
I--Io.s~
~
J
---------------------~Jri~-----------------3-119
WS57C210M
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C210M-55R
WS57C210M-70R
WS57C210M-70RM
WS57C210M-70RMB
WS57C210M-90R
WS57C210M-90RM
WS57C210M-90RMB
55
70
70
70
90
90
90
PACKAGE
TYPE
40
40
40
40
40
40
40
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
SIB,
SIB,
SIB,
SIB,
SIB,
SIB,
SIB,
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
R1
R1
R1
R1
R1
R1
R1
Comm'l
Comm'l
Military
Military
Comm'l
Military
Military
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STO-883C
------------------------~Jri~--------------------3-120
iF===:~
------------
WS27C210F
,.-~~-
~---
ADVANCE INFORMATION
WAFERSCALE INTEGRATION, INC.
1 Meg (64Kx 16) CMOS EPROM
KEY FEATURES
• High Performance
-
• EPI Processing
55 ns
-
• Simplified Upgrade Path
-
V pp and PGM Are "Don't Care" During
Normal Read Operation
Expandable to 8M Bits
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
• JEDEC Standard Pin Configuration
-
40 Pin Dip Package
GENERAL DESCRIPTION
The WS27C210F is a high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 64 K-words of 16 bits each. The 55 ns access time of the WS27C21OF enables it to operate in high
performance systems. The "Don't Care" feature during read operations enables memory expansions up to 8M bits
with no printed circuit board changes.
High performance microprocessors such as the 80386 and 68020 require 55 ns memory access times to operate
at or near full speed. The WS27C210F enables such systems to incorporate operating systems and/or applications
software into EPROM. This in turn enhances system utility by freeing up valuable RAM space for data or other program
store and eliminating disk accesses for the EPROM resident routines.
The WS27C210F pin configuration was established to enable memory upgrades to 8M bits without hardware changes
to the printed circuit board. Pins 1 and 39 are "don't care" during normal read operation. This enables higher order
addresses to be connected to these pins (see DIP Pin Configurations). When higher density memories are required,
the printed circuit board is ready to accept the higher density device with no hardware changes.
The WS27C210F is part of an eight product megabit EPROM family. Byte-wide family members are: WS27C010L,
WS27C010F and WS57C010F. These three are 128K x 8 EPROMs with the WS57C010F as the highest speed member.
The 64K x 16 EPROMs are the WS27C210L, WS27C210F (described herein) and the highest speed version WS57C210F.
The WS57C010M and WS57C210M are high speed, high bus drive megabit EPROM modules.
The WS27C210F is manufactured using WSl's advanced CMOS technology.
PRODUCT SELECTION GUIDE
PARAMETER
WS27C210F-55
WS27C210F-70
WS27C210F-90
WS27C210F·10
Address Access Time (Max)
55 ns
70 ns
90 ns
100 ns
Chip Select Time (Max)
55 ns
70 ns
90 ns
100 ns
Output Enable Time (Max)
25 ns
25 ns
30 ns
30 ns
3-121
WS27C210F
ABSOWTE MAXIMUM RATINGS·
*Notice: Stresses above those listed under ''Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Storage Temperature ........... -65°C to + 125°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vee Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ........................ >2000V
NOTICE: Specifications contained within the following tables are subject to change.
OPERATING RANGE
RANGE
TEMPERATURE
Comm'l
Vcc
± 5%
± 10%
0° to +70°C
+5V
Industrial
-40° to +85°C
+5V
Military
-55° to +125°C
+5V + 10%
READ OPERATION
DC CHARACTERISTICS O°C ~ TA ~ +70°C; Vee (Comm'IIMilitary)
+5V
±
10%.
LIMITS
SYMBOL
PARAMETER
CONDITIONS
= 5.5V
VO UT = 5.5V
Vpp ~ Vee
10
J.lA
= VIH
CE = V IH
CE = OE = V IL
2
mA
500
50(3)
mA
III
Input Load Current
ILO
Ipp(l)
Output Leakage Current
ISB TTL
Vee Current Standby
MIN
MAX
UNITS
10
J.lA
10
J.lA
VIN
Vpp Load Current
ISB CMOS
Vee Current Standby
lee(l)
Vee Current Active
CE
J.tA
VIL
Input Low Voltage
-0.3
+0.8
V
V IH
Input High Voltage
2.0
Vee +1
V
VOL
Output Low Voltage
0.4
V
VOH
Vpp(l)
Output High Voltage
= 2.1 mA
= -400 J.lA
= 5.0V ± 0.25
IOL
10H
Vpp Read Voltage
Vee
2.4
V
-0.1
V ee +1
V
AC CHARACTERISTICS O°C ~ TA ~ +70°C
SYMBOL
CHARACTERISTICS
tAee
Address to Output Delay
teE
CE to Output Delay
tOE
tDF(2)
OE to Output Delay
tOH
TEST
CONDITIONS
CE
OE High to Output Float
Output Hold From
Addresses CE or OE
CE
Whichever Occurred First
·70
·55
MIN
= OE = VIL
OE = VIL
CE = VIL
CE = VIL
0
= OE = VIL
0
MAX MIN
·90
MAX
55
70
55
70
25
25
25
0
0
25
MIN
·10
MAX MIN
90
100
90
100
30
0
0
MAX
30
30
0
UNITS
ns
30
0
NOTES:
vpp should be at a TTL level except during programming. The supply current would then be the sum of Icc and Ipp. The maximum current
value is with Outputs 0 0 to 0'5 unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the pOint where data is no longer driven-see timing diagram.
3. Add 3 rnA/MHz for A.C. power component.
I.
------------------------~Jri-----------------------3-122
WS27C210F
AC READ TIMING DIAGRAM
V,H
-----_
ADDRESS
VALID
ADDRESSES
V,L
------
V,H
--------1~""
V,H
--------1~----
1+-----
I ACC
----~
HIGH Z
OUTPUT
HIGH Z
-------------+H~+<
CAPACITANCE(4) TA
1 MHz
PARAMETER
SYMBOL
C IN
Input Capacitance
COUT
Output Capacitance
CvPp
V pp Capacitance
CONDITIONS
TYP(5)
MAX
UNITS
= OV
VOUT = OV
V pp = OV
4
6
pF
8
12
pF
18
25
pF
VIN
NOTES:
4. This parameter is only sampled and IS not 100% tested.
5. Typical values are for TA = 25°C and nom mal supply voltages.
6. OE may be delayed up to tCE -tOE after the failing edge of CE without Impact on tCE '
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.04V
"""T"""
2.4
2~
;>
0.45
0.8
~
2~
~
TEST POINTS {
0.8
DEVICE
UNDER
TEST
>
I
8200
,.... OUT
CL = 100 pF
--
A.C. testing inputs are driven at 2.4V for a Logic "1" and
0.45V for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and O.BY for a Logic "0."
CL includes Jig Capacitance
------------------------~Jr;-----------------------3-123
WS27C210F
DIP PIN CONFIGURATIONS
8 Mblt
4 Mblt 2 Mblt
512K
XXlVpp XXIVpp XXlVpp
A,S
WS27C21OF
WS57C257 WS57C65
XXlVpp
XXlVpp
WS57C65 WS57C257
2 Mblt
Vee
Vee
Vee: -
Vee
Vee
MPO
XXlPGM
XX/PGM
r'°'5
r'0,.
NC
A,s, -
NC
NC
NC
NC
NC
NC
CE/Vpp
CE
CE
CE
CE
l:E
°'5
°'5
°'5
°'5
°'5
°'5
°'4
°'4
°'4
°'4
°'4
°'4
°'3
°'3
°'3
°'3
°'3
°'3
°'2
011
°'2
°'2
°'2
°'2
°'2
0"
0,.
0"
0,.
0"
0,.
0"
0,.
I- 0"
0,.
0"
0,.
09
09
09
Og
09
Og
Os
Os
Os
Os
Os
I- 0.
I- 0.
A,., -
Os
GND
GND
GND
GND
GND
GND
GND
GND-
°7
06
07
°7
06
07
07
06
06
06
°7
06
Os
Os
Os
Os
Os
Os
°4
03
04
°4
03
°4
03
°4
03
°4
03
O2
O2
03
512K
r- Vpp
r- CE
r- 0,.
r-'0"
r'0,.
A,., A", A,., A" A. -
4 Mbit 8 Mblt
Vee
Vee
A'7
A'7
A'6
A'6
A'6
NC
A,s
A,s
A,s
NC
A'4
A'4
A'4
A'4
NC
A'3
A'3
A'3
A'3
A'3
NC
A'2
A'2
A'2
A'2
A'2
A"
A,.
A"
A,.
A"
A,.
A"
A,.
A"
A,.
A"
A,.
XX/PGM XXlPGM
A9
Ag
Ag
Ag
Ag
Ag
GND
GND
GND
GND
GND
GND
I- 07
A. -
As
As
As
As
As
As
I - 0.
A7 -
A7
A7
A7
A7
A7
A7
I- Os
I- 0.
A. -
A6
A6
As
A6
A6
A6
As -
As
As
As
As
As
As
I - 0,
A. -
A4
A4
A4
A4
A4
A4
I - 0.
A3
A3
A3
A3
A3
A3
0,
°2
0,
0,
°2
0,
0,
°2
0,
I - 0,
A. A. -
A2
A2
A2
A2
A2
A2
0.
0.
0.
0.
0.
0.
I- 0.
A, -
A,
A,
A,
A,
A,
A,
ljE
OE
OE
ljE
OE
ljE
I- OE
A. -
A.
As
A.
A.
A.
A.
O2
NOTE: Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C210F pins.
PIN NAMES
Ao-A'5
Addresses
CE
Chip Enable
OE
Output Enable
0 0-0 '5
Outputs
NC
No Connection
XX
Don't Care (During Read)
---------------------~Jri--------------------3-124
WAFERSCALE INTEGRATION, INC.
2 MEG EPROM SELECTION GUIDE
ARCHITECTURE
I
128K x 16
256Kx 8
I
I
I
I
I
I
I
I
I
I
WS27C220L
~
WS27C020L
I
I
I
ACCESS TIME (ns)
------------------------~Jr;'----------------------3-125
- - - - - - - - - - - -----
----------
~------
---
~
~~
________________ UI#,. __________________
~J
WS27C020L
ADVANCE INFORMATION
WAFERSCALE INTEGRATION, INC.
2 Meg (256K x 8) CMOS EPROM
KEY FEATURES
• Compatible with JEDEC 27020 and
27C020 EPROMs
• High Performance CMOS
-
120 ns Access Time
• EPI Processing
-
• JEDEC Standard Pin Configuration
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
-
• Simplified Upgrade Path
-
32 Pin Dip Package
32 Pin Chip Carrier
Vpp and PGM Are "Don't Care" During
Normal Read Operation
GENERAL DESCRIPTION
The WS27C020L is a high performance, 2,097,152-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 256 K-words of 8 bits each. Its pin-compatibility with byte-wide JEDEC EPROMs enables upgrades
through 8 Mbit EPROMs. The "Don't Care" feature during read operations enables memory expansions up to 8M bits
with no printed circuit board changes.
The WS27C020L can directly replace lower density 28-pin EPROMs by adding an A17 address line and Vcc jumper.
During the normal read operation PGM and Vpp are in a "don't care" state which allows higher order addresses,
such as A 18 and A 19 to be connected without affecting the normal read operation. This allows memory upgrades to
8M bits without hardware changes. The WS27C020L will also be offered in a 32-pin plastic Dip with the same upgrade
path.
The WS27C020L provides microprocessor-based systems extensive storage capacity for large portions of operating
system and application software. Its 120-ns access time provides no-wait-state operation with high-performance CPUs
such as the 16-MHz 80186, 16-MHz 68020, or 12-MHz 80386. The WS27C020L offers a single chip solution for the
code storage requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed
from EPROM storage, greatly enhancing system utility.
The WS27C020L is manufactured using WSl's advanced CMOS technology.
The WS27C020L is one member of a high density WSI EPROM series which ranges in density from 64K to 4 Megabit.
PRODUCT SELECTION GUIDE
27C020L·12
27C020L·15
27C020L·17
27C020L·20
Address Access Time (Max)
120 ns·
150 ns
170 ns
200 ns
Chip Select Time (Max)
120 ns
150 ns
170 ns
200 ns
Output Enable Time (Max)
35 ns
40 ns
40 ns
40 ns
PARAMETER
-----------------------~Jr;----------------------3-127
WS27C020L
ABSOLUTE MAXIMUM RATINGS·
"Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to +125°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vee Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ....................... > 2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
TOLERANCE
Comm'l
0° to +70°C
+5V
±5% or +10%
Military
-55° to +125°C
+5V
±10%
DC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
SYMBOL
MIN
MAX
UNITS
VIL
Input Low Level
PARAMETER
-0.5
0.8
V
VIH
Input High Level
2.0
V
VOL
VOH
IsBP)
Output Low Voltage
IOL = 2.1 mA
Vee + 1
0.4
Output High Voltage
100
ISB2
Vee Standby Current
J.lA
mA
Vee Active Current
IOH = -400 J.lA
CE = Vee ± 0.3V
CE = VIH
_
_
\F=5MHz
CE = OE = VIL F = 8 MHz
Ipp
Vpp Supply Current
Vpp = Vee
Vpp
V pp Read Voltage
Vee Standby Current (CMOS)
lec(l)
III
iLO
TEST CONDITIONS
J
1
50
I
Input Load Current
VIN = 5.5V or Gnd
Output Leakage Current
Your = 5.5V or Gnd
V
V
3.5
mA
60
100
Vee -0.4
-1
Vee
1
-10
10
J.lA
V
J.tA
J.lA
At READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
SYMBOL
PARAMETER
-12
MIN
-15
MAX
MIN
-17
MAX
MIN
-20
MAX
MIN
MAX
tAec
Address to Output Delay
120
150
170
200
teE
CE to Output Delay
120
150
170
200
tOE
OE to Output Delay
35
40
40
40
tDF(2)
Output Disable to
Output Float
35
40
40
40
tOH(2)
Output Hold From
Addresses, CE or
OE, Whichever
Occurred First
UNITS
ns
0
0
0
0
NOTES:
1. The supply current is the sum of lee and Ipp. The maximum current value is with Outputs 0 0 to 0 7 unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float IS defined as the point where data is no longer driven-see timing diagram.
3. eMOS inputs: VIL = GND ± 0.3V, V IH = Vee ± 0.3V.
=-_.
-------------------------------------~~~.-----------------------------------3-128
WS27C020L
AC READ TIMING DIAGRAM
V,H - - - - - _
ADDRESS
VALID
ADDIIESSES
V,L - - - - - V,H
_ _ _ _ _ _--11-"""
V ,H
------~f----_
1 4 - - - - - tACC
OUTPUT _ _ _ _ _ _HIGH
__
Z _____
CAPACITANCE(4) TA
SYMBOL
----.j
HIGH Z
~~~~
1 MHz
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
Cvpp
Vpp Capacitance
CONDITIONS
TYP(5)
MAX
UNITS
VIN = OV
4
6
pF
VOUT = OV
8
12
pF
Vpp = OV
18
25
pF
NOTES:
4. This parameter IS only sampled and is not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages.
6 OE may be delayed up to tCE -tOE after the falling edge of CE without Impact on tCE
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.04V
T
~
DEVICE
UNDER
TEST
~
8200
~ CL = 100 pF
IA.C. testing inputs are driven at 2.4V for a Logic "1" and
0.4V for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and O.BV for a Logic "0."
-
CL = 100 pF
CL includes Jig Capacitance
---------------------~Jri--------------------3-129
WS27C020L
MODE SELECTION
The modes of operation of the WS27C020L are listed in Table 1. A single SV power supply is required in the read
mode. All inputs are TTL levels except for V pp and on A9 for device signature.
Table 1. Modes Selection
PINS
-
OE
PGM
As
Ao
V pp
Vcc
'v IL
V IL
X(7)
High Z
X
X
X
X
S.OV
V IH
X
X
X
X
X
X
X
X
DOUT
V IH
X
X
X
X
X
X
S.OV
X
S.OV
High Z
V pp (8)
6.2V
DIN
Vpp(8)
6.2V
DOUT
V pp (8)
6.2V
High Z
V H(8)
VIL
S.OV
23 H
V H(8)
V IH
X
X
S.OV
C1 H
CE
MODE
Read
Output Disable
Standby
Programming
V IL
V IH
V IL
Program Verify
V IL
V IL
V IH
Program Inhibit
V IH
X
X
X
X
Signature
NOTES:
I
I
Manufacturer(9)
V IL
V IL
Device(9)
V IL
V IL
OUTPUTS
B. VH = Vpp = 12.75 ± O.25V.
7. X can be V 1L or V1H
DIP PIN CONFIGURATIONS
8 Mbil
4 Mbil
1 Mbil
A'9
A,s
A,s
XXlVpp
A,s
A,s
XXlVpp
A,s
A,s
A,s
Vpp
A'2
A7
As
As
A4
A3
A2
A,
Ao
A'2
A7
As
As
A4
A3
A2
A,
Ao
A'2
A7
As
As
A4
A3
A2
A,
Ao
A'2
A7
As
As
A4
A3
A2
A,
Ao
A'2
A7
As
As
A4
A3
A2
A,
Ao
00
0,
00
0,
00
0,
00
0,
00
0,
O2
GND
O2
GND
O2
GND
O2
GND
O2
GND
NOTE:
WS27C020L
27C512L 27C256L
27C256L 27C512L
X
c-
r-- A,.
PGM
..-
I - A15
7-
Vee
Vee
A'4
A'4
A'3
A'3
As
As
.A9
A9
Al1
Al1
!DE
OElVpp
0A,o
A,o
; - CE/PGM CE/PGM
07
07
Os
Os
Os
Os
04
04
03
03
r-- A12
r-- A7
I - - A.
6
r-- As
,-
I - - A.
r-- A,
I--
r-I - - AD
..-
r-- 0 0
I - - 0,
I - - O.
r- GNO
1 Mbll
4 Mbil
8 Mbil
Vee
XX/PGM
XX
Vee
A,s
Vee
A,s
A'4
A'3
As
A9
Al1
OE
A10
CE
°7
Os
Os
04
03
A'7
A'7
A14
A'4
A'3
A'3
As
As
A9
A9
Al1
Al1
OE
OEN pp
A,o
A,o
CE/PGM CE/PGM
°7
Os
Os
04
03
°7
Os
Os
04
03
Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C020L pins.
PIN NAMES
LCC PIN CONFIGURATION
Addresses
CE
OE
Chip Enable
Output Enable
Outputs
PGM
Program
XX
Don't Care (During Read)
NOTE: Leadless or
Leaded, Plastic or
Ceramic Package
-----------------------
-----------------------~Jr;-.
3-130
WS27C020L
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ±
5°C, Vee = S.2V ± 0.25V, Vpp
PARAMETER
12.75 ± 0.2SV)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
(VIN = Vee or Gnd)
III
-10
10
IlA
Vpp Supply Current During_ _
Programming Pulse (CE = PGM = V1d
Ipp
SO
mA
lee
V1L
50
mA
Input Low Level
-0.1
0.8
V
Input High Level
V 1H
2.0
Vee +0.3
V
Output Low Voltage During Verify
(IOL = 2.1 mA)
VOL
0.4
V
Output High Voltage During Verify
(loH = - 400 j.tA)
VOH
Vee Supply Current
NOTES:
3.5
V
10. Vee must be applied either cOincidentally or before Vpp and removed either coincidentally or after Vpp.
11. Vpp must not be greater than 14 volts including overshoot. During CE = PGM = V IL • Vpp must not be switched from 5 volts
to 12.75 volts or vice-versa.
12. During power up the PGM pin must be brought high (:;.V IH ) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS
(TA = 25 ± 5°C, Vee = S.2V ± 0.25V, Vpp = 12.75 ± 0.25V)
PARAMETER
Address Setup Time
Output Enable Setup Time
Data Setup Time
MIN
tAS
2
IlS
tOES
los
2
IlS
2
IlS
tAH
IlS
Address Hold Time
Data Hold Time
tOH
0
2
Chip Disable to Output Float Delay
tOF
0
Data Valid From Output Enable
tOE
Vpp Setup Time/CE Setup Time
PGM Pulse Width
tvs/teEs
2
tpw
0.1
TYP
MAX
SYMBOLS
UNIT
55
IlS
ns
55
ns
4
ms
Ils
PROGRAMMING WAVEFORM
ADDRESSES
DATA
v••
v••
Vee
VIH
CE
V'L
V'H
PGM
V'L
V'H
aE
V'L
-----------------------~Jr;-----------------------3-131
:3-~13=2--------------------------~Jr;-----------------------------
-=' == == J:= E::
~~
--...,
---1i-ii=Ii-i':
II
---ii'
~~
-
WS27C220L
ADVANCE INFORMATION
WAFERSCALE INTEGRATION, INC.
2 Meg (128K x 16) CMOS EPROM
KEY FEATURES
• Ultra-High Performance
-
• EPI Processing
120 ns
-
• Simplified Upgrade Path
-
Vpp and PGM Are "Don't Care" During
Normal Read Operation
Expandable to 8M Bits
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
• JEDEC Standard Pin Configuration
-
40 Pin Dip Package
44 Pin Chip Carrier
GENERAL DESCRIPTION
The WS27C220L is an ultra-high performance, 2,097,152-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 128K-words of 16 bits each. The 120 ns access time of the WS27C220L enables it to operate in
high performance systems. The "Don't Care" feature during read operations enables memory expansions up to 8M
bits with no printed circuit board changes.
High performance microprocessors such as the 12 MHz 80386 and 16 MHz 68020 require 120 ns memory access
times to operate at or near full speed. The WS27C220L enables such systems to incorporate operating systems and/or
applications software into EPROM. This in turn enhances system utility by freeing up valuable RAM space for data
or other program store and eliminating disk accesses for the EPROM resident routines.
The WS27C220L Pin configuration was established to allow memory upgrades to 8M bits without hardware changes
to the printed circuit board. Pins 1 and 39 are "don't care" during normal read operation. This enables higher order
addresses to be connected to these pins (see DIP Pin Configurations). When higher density memories are required,
the printed circuit board is ready to accept the higher density device with no hardware changes.
The WS27C220L is part of a high density EPROM family which spans densities from 64K to 4 Meg.
The WS27C220L is manufactured using WSI's advanced CMOS technology.
PRODUCT SELECTION GUIDE
PARAMETER
27C220L-12
27C220L-15
27C220L-17
27C220L-20
Address Access Time (Max)
120 ns
150 ns
170 ns
200 ns
Chip Select Time (Max)
120 ns
150 ns
170 ns
200 ns
Output Enable Time (Max)
35 ns
40 ns
40 ns
40 ns
3-133
WS27C220L
ABSOLUTE MAXIMUM RATINGS·
"Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -S5°C to +125°C
Voltages on Any Pin with
Respect to Ground .............. -O.SV to +7V
Vpp with Respect to Ground ....... -O.SV to +14V
Vee Supply Voltage with
Respect to Ground .............. -O.SV to +7V
ESD Protection ....................... > 2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
TOLERANCE
Comm'l
0° to +70°C
+5V
+5% or +10%
Military
-55° to +125°C
+5V
±10%
DC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
SYMBOL
MIN
MAX
UNITS
VIL
Input Low Level
PARAMETER
TEST CONDITIONS
-0.5
0.8
V
V IH
Input High Level
2.0
V
VOL
VOH
ISB1 (3)
Output Low Voltage
IOL = 2.1 mA
Vee + 1
0.4
Output High Voltage
Vee Standby Current (CMOS)
ISB2
Vee Standby Current
lee(1)
Vee Active Current
IOH = -400 I!A
CE = Vee ± 0.3V
CE = V IH
_
_
IF=5MHz
CE = OE = V IL F = 8 MHz
Vpp = Vee
3.5
V
100
Ipp
Vpp Supply Current
Vpp Read Voltage
III
ILO
Input Load Current
VIN = 5.5V or Gnd
Output Leakage Current
VOUT = 5.5V or Gnd
I!A
mA
1
SO
I
Vpp
V
mA
70
100
Vee -0.4
-1
Vee
1
-10
10
I!A
V
I!A
I!A
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
SYMBOL
PARAMETER
-15
-12
MIN
MAX
MIN
-17
MAX
MIN
-20
MAX
MIN
MAX
tAee
Address to Output Delay
120
150
170
200
teE
CE to Output Delay
120
150
170
200
tOE
OE to Output Delay
35
40
40
40
tDF(2)
Output Disable to
Output Float
35
40
40
40
to H(2)
Output Hold From
Addresses, CE or
OE, Whichever
Occurred First
UNITS
ns
0
0
0
0
NOTES:
1. The supply current is the sum of lee and Ipp. The maximum current value is with Outputs 0 0 to 0 7 unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven-see timing diagram.
3. CMOS inputs: VIL = GND ± 0.3V, V IH = Vee ± 0.3V.
-------------------------------------'AjJ;~~-----------------------------------~~
~.
WS27C220L
AC READ TIMING DIAGRAM
V ,H
ADDRESS
VALID
ADDRESSES
V'L
V,H
CE
V'L
....- - I CE( 6 ) - - - J
V,H
--------1----'"'"
1 + - - - - I ACC
-----I
HIGH Z
OUTPUT
CAPAC/TANCEl4) TA
SYMBOL
HIGH Z
-------------+H+H
25°C, f
1 MHz
PARAMETER
C IN
Input Capacitance
COUT
Output Capacitance
CvPp
Vpp
CONDITIONS
Capacitance
VIN
VOUT
Vpp
= OV
= OV
= OV
TYP(5)
MAX
UNITS
4
6
pF
8
12
pF
18
25
pF
NOTES:
4. This parameter is only sampled and is not 100% tested.
5. Typical values are for TA = 25°C and nominal supply voltages.
6. OE may be delayed up to tCE -tOE after the failing edge of CE without Impact on tCE
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.04V
-r-
...
{S20Q
... ~
DEVICE
UNDER
TEST
I
CL
= 100pF
--
A.C. testing inputs are driven at 2.4V for a Logic "1" and
0.4V for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and 0.8V for a Logic "0."
CL = 100 pF
CL includes Jig Capacitance
---------------------------~~~.--------------------------3-135
WS27C220L
DIP PIN CONFIGURATIONS
8 Mblt
4 Mblt
1 Mbl!
512K
57C257
WS27C220L
57C65
XXlVpp XX/Vpp XXlVpp XXlVpp XXNpp I-XXNpp
A,S
CE/PGM CE/PGM
CE
CE
CE
CE
1--'CE
0'5
0,.
0'5
0,.
0'5
0,.
0'5
0,.
0'5
0,.
0'5
0,.
1--'0,.
1--'0,.
0'3
0'3
0'3
0'3
0'3
0'3
1---'
0'2
0'2
0'2
0'2
0'2
0'2
On
0"
0"
On
On
0'0
09
0'0
09
0'0
09
0'0
09
0'0
09
Os
Os
Os
Os
Os
GND
GND
GND
GND
07
07
07
Os
Os
Os
05
05
O.
0,.
1---'0,.
57C65
57C257
512K
1 Mblt
Vee
Vee
Vee
Vee
Vee" XXiJ5lm
..-
4 Mblt 8 Mblt
XX/PGM Xx/PGM XX/PGM XX/PGM
A,a - -
NC
NC
A,
Vee
Vee
A'7
A,s
NC
NC
A'7
A,s
NC
NC
NC
A,s
A,s
A,s
A,
NC
NC
A,.
A'4
A,.
A,.
A,
NC
A'3
A'3
A'3
A'3
A'3
A'2
An
A'2
An
A'2
A'2
An
..,-
1--'0 11
0,.
0'0 1--'
A,
NC
A,
09
I--- O.
A,
A"
A,o
A"
A,o
A,o
A,o
A"
A,o
Os
I--- O.
.-
A'2
A.
As
Ag
Ag
Ag
Ag
A9
GND
GND
I--GND
GN10--
GND
GND
GND
GND
GND
GND
07
07
07
As
As
As
As
As
As
Os
Os
f---------- 0 7
f---------- O.
A.
Os
A7
A7
A7
A7
A7
A7
05
05
05
05
I--- O.
A. -
As
As
As
As
As
As
O.
O.
O.
O.
04
As -
As
As
As
As
As
As
03
03
03
03
03
03
f---------- O.
f---------- O.
A. -
A.
A.
A.
A.
A4
A.
O2
O2
O2
02
02
O2
-
O.
-
A3
A3
A3
A3
A3
Aa
0,
0,
0,
0,
0,
0,
0,
-
A2
A2
A2
A2
A2
A2
00
00
00
00
00
00
-
O.
A,
A,
A,
A,
A,
A,
OENpp
OE
OE
OE
O!
O!
- iOE
-
Au
Ao
Ao
Ao
Ao
Ao
0"
A7
-
-
A,o
NOTE: Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C220L pins.
PIN NAMES
LCC PIN CONFIGURATION (TOP)
Ao-A16
Addresses
CE
Chip Enable
DE
Output Enable
0 0-015
Outputs
NC
No Connection
XX
Don't Care (During Read)
0,.
PGM
Program
o.
o.
==:9
=:~10
::Jll
GND
NC
0 7 ::]14
O. ~~J15
05 :::::~16
04
A11
0
3S::":
A,.
35['::-
A.
34~-=
GND
33r:: NC
32~==
31~::
30r:=.
ij]~~ 1~ ~~ ~~ ~~r,~~ ~1I,~~ ~~ ~~r ~~;i.
I
,I"
,I III
II
till
Aa
A7
Ae
As
I
---------------------~Jri~-----------------3·136
--
-----
---------
WS27C220L
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 +-
5°C, Vee = 6.2V ± 0.25V,
PARAMETER
= 12.75 +
- 0.25V)
MIN
MAX
UNIT
III
-10
10
~A
60
mA
50
mA
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During_ _
Programming Pulse (CE = PGM = VILl
Ipp
Vee Supply Current
Input High Level
lee
VIL
V IH
Output Low Voltage During Verify
(loL = 2.1 mAl
VOL
Output High Voltage During Verify
(lOH = -400 ~A)
VOH
Input Low Level
NOTES:
vpp
SYMBOLS
-0.1
0.8
V
2.0
Vee +0.3
V
0.4
V
3.5
V
7. Vee must be applied either cOincidentally or before V pp and removed either cOincidentally or after V pp.
8. Vpp must not be greater than 14 volts mcluding overshoot. DUring CE = PGM = V ,L• Vpp must not be switched from 5 volts
to 12.75 volts or vice-versa.
9. During power up the PGM pm must be brought high (~V'H) either coincident with or before power IS applied to Vpp.
AC CHARACTERISTICS
(TA = 25 ± 5°C, Vee = 6.2V ± 0.25V, Vpp = 12.75 ± 0.25V)
PARAMETER
Address Setup Time
Output Enable Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Chip Disable to Output Float Delay
SYMBOLS
MIN
tAS
2
2
2
0
2
tOES
tos
tAH
tOH
tDF
0
Data Valid From Output Enable
tOE
Vpp Setup Time/CE Setup Time
tVS/tCES
2
tpw
0.1
PGM Pulse Width
TVP
MAX
UNIT
~s
~s
~s
~s
~s
55
55
ns
ns
~s
4
ms
PROGRAMMING WAVEFORM
ADDRESSES
DATA
v••
v••
CE
Vee
V'H
V,L
V'H
PGM
V,L
V'H
aE
V,L
-----------------------~Jr;,----------------------3-137
WS27C220L
MODE SELECTION
The modes of operation of the WS27C220L are listed in Table 1. A single SV power supply is required in the read
mode. All inputs are TTL levels except for Vpp and on As for device signature.
Table 1. Modes Selection
~S
MODE
Read
Output Disable
Standby
Programming
Program Verify
Program Inhibit
.
I Manufacturer(12)
(12)
Signature
Device
I
NOTES:
.
10. X can be V1L or V1H
CE
OE
PGM
VIL
X
VIL
VIH
VIL
VIL
VIH
VIL
VIL
As
Ao
Vpp
Vcc
OUTPUTS
X(10)
X
VIH
X
X
X
X
X
X
X
X
X
X
X
DOUT
High Z
High Z
VIH
VIL
X
VIL
VIH
X
X
X
X
X
X
X
VH(ll)
VIL
Vpp
Vpp
Vpp
X
S.OV
S.OV
S.OV
6.2V
6.2V
6.2V
5.0V
DOUT
High Z
23 H
X
VH(ll)
VIH
X
5.0V
C9 H
VIL
VIL
X
DIN
11. VH = Vpp
---------------------~~i~------------------3-138
".-==
!FEE::~
~~~
E
___________________________________________________
WAFERSCALE INTEGRATION, INC.
4 MEG EPROM SELECTION GUIDE
ARCHITECTURE
256K)( 16
I
WS27C240L
512K)(S
I
WS27C040L
~
~
ro
"
"
~
1=
I
I
I
~
I
M
m
!
m
m
~
~
m
~
~
~
ACCESS TIME (ns)
3-139
~
,
#
I
U
~
~~
________________
~A
__________________
WS27C040L
PRELIMINARY
WAFERSCALE INTEGRATION, INC.
512K X 8 CMOS EPROM
KEY FEATURES
• High Performance CMOS
-
• Simplified Upgrade Path
120 ns Access Time
-
• Fast Programming
• Upward Compatible with JEDEC
EPROM Configurations
• EPI Processing
-
Vpp is a "Don't Care" During Normal
Read Operation
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
• JEDEC Standard Pin Configuration
-
32 Pin Dip Package
GENERAL DESCRIPTION
The WS27C040L is a high performance, 4,194,304-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 512 K-words of 8 bits each. Its pin-compatibility with byte-wide JEDEC EPROMs enables upgrades
through 8 Mbit EPROMs. The "Don't Care" feature on Vpp during read operations allows memory expansions from
1M to 8M bits with no printed circuit board changes.
The WS27C040L can directly replace lower density 28-pin EPROMs by adding an A16 address line and Vcc jumper.
During the normal read operation Vpp is in a "don't care" state which allows a higher order address, such as A 19 ,
to be connected without affecting the normal read operation. This allows memory upgrade to 8M bits without hardware
changes. The WS27C040L will also be offered in a 32-pin plastic Dip with the same upgrade path.
The WS27C040L provides microprocessor-based systems extensive storage capacity for large portions of operating
system and application software. Its 120-ns access time provides no-wait-state operation with high-performance CPUs
such as the 16-MHz 80186, 16-MHz 68020, or 12-MHz 80386. The WS27C040L offers a Single chip solution for the
code storage requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from EPROM storage, greatly enhancing system utility.
The WS27C040L is manufactured using WSI's advanced CMOS split gate EPROM technology.
PRODUCT SELECTION GUIDE
PARAMETER
WS27C040L-12
WS27C040L-15
WS27C040L-17
WS27C040L-20
Address Access Time (Max)
120 ns
150 ns
170 ns
200 ns
Chip Select Time (Max)
120 ns
150 ns
170 ns
200 ns
Output Enable Time (Max)
35 ns
40 ns
40 ns
40 ns
3-141
WS27C040L
ABSOLUTE MAXIMUM RATINGS*
-Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time .
may affect device reliability.
Storage Temperature ........... -65°C to +125°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vce Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ....................... > 2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
TOLERANCE
Commercial
OOC to +70°C
+5V
±5% or ±10%
-55°C to +125°C
+5V
+10%
Military
DC READ CHARACTERISTICS Over Operating Range with Vpp
Vee.
MIN
MAX
V IL
Input Low Level
-0.5
0.8
V
V IH
Input High Level
2.0
V
VOL
VOH
Output Low Voltage
10L = 2.1 rnA
Vee + 1
0.4
Output High Voltage
IssP)
Vee Standby Current (CMOS)
10H = -400 J.A
CE = Vee ± 0.3V
ISS2
Vee Standby Current
lee(l)
Vee Active Current
CE = VIH
_
_
IF=5MHz
CE = OE = V IL F = 8 MHz
Vpp = Vee
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
3.5
V
V
100
J.A
1
rnA
50
I
rnA
60
100
J.A
Ipp
Vpp Supply Current
Vpp
Vpp Read Voltage
III
Input Load Current
V IN = 5.5V or Gnd
-1
Vee
1
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
Vee -0.4
V
J.A
J.A
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vec.
SYMBOL
CHARACTERISTICS
27C040L·12
27C040L·15
27C040L·17
27C040L·20
MIN
MIN
MIN
MIN
UNITS
MAX
MAX
MAX
MAX
tAee
Address to Output Delay
120
150
170
200
teE
CE to Output Delay
120
150
170
200
tOE
OE to Output Delay
35
40
40
40
tDF(2)
OE High to Output Float
35
40
40
40
tOH(2)
Output Hold from
Addresses, CE or OE,
Whichever Occurred First
0
0
0
ns
0
NOTES:
1. The supply current is the sum of Icc and Ipp. The maximum current value is with Outputs 0 0 to 0 7 unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer drlven-see timing diagram.
3. eMOS Inputs: VIL = GND ± 0.3V, VIH = Vec ± 0.3V.
------------------------------------~~~-----------------------------------3-142
WS27C040L
A.C. WAVEFORMS
V ,H
ADDRESS
VALID
ADDRESSES
VIL
V ,H
CE
VIL
V ,H
CE
V'L
tDF (4)
HIGH Z
HIGH Z
--------------+-H+H
OUTPUT
CAPACITANCE(4) TA
SYMBOL
1 MHz
PARAMETER
C IN
CONDITIONS
TYP(S)
MAX
UNITS
= OV
VOUT = OV
Vpp = OV
4
6
pF
8
12
pF
18
25
pF
Input Capacitance
C OUT
Output Capacitance
CvPp
Vpp Capacitance
VIN
NOTES:
4. This parameter IS only sampled and is not 100% tested.
5. Typical values are for T A = 25°C and nominal supply voltages.
6. OE may be delayed up to tCE-t OE after the failing edge of CE without Impact on tCE
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.0W
""T-'
2.4
;>
0.4
0.8
«
:>~
LO
2~
TEST POINTS
0.8
DEVICE
UNDER
TEST
8200
~
I
CL
=
100pF
--
A.C. testing inputs are driven at 2.4V for a Logic "1" and
0.4V for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and O.BV for a Logic "0."
CL Includes Jig Capacitance
-----------------------~~~-------------------------3-143
WS27C040L
MODE SELECTION
The modes of operation of the WS27C040L are'listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TIL levels except for Vpp and As for device signature.
Table 1. Modes Selection
~
CE/PGM
OE
Ag
Ao
Vpp
Vcc
OUTPUTS
Read
VIL
X
VIL
VIH
X
X
X
Dour
High Z
X
X
X
X
X
5.0V
VIH
X
X
X
X
5.0V
Output Disable
5.0V
High Z
Vpp(S)
6.2V
DIN
X
X
Vpp(S)
6.2V
Vpp(S)
5.0V
Dour
High Z
VIL
X
5.0V
23 H
VIH
X
5.0V
DO H
MODE
Standby
Programming
VIL
VIH
Program Verify
X
VIL
Program Inhibit
VIH
VIH
X
X
VIL
VH(S)
VIL
VH(S)
Signature
Manufacturer(S)
VIL
Device(S)
VIL
NOTES:
7. X can be VIL or VIH
S. VH = Vpp = 12.75 ± 0.25V
DIP PIN CONFIGURATIONS
8 Mblt
A 19
A 16
A 15
A12
A7
27C010L
XXlVpp
A 16
A 15
A 16
A 15
r---
A12
A7
A12
A7
I--
r---
As
As
As
A5
A5
A4
A3
A2
Al
A5
A.t
A3
A2
Al
Ao
00
01
O2
GND
WS27C040L
2 Mblt
XX/Vpp
A.t
00
01
Aa
A2
Al
Ao
00
01
O2
GND
O2
GND
Au
vee
A,.
A17
A,.
A,.
r-r--
-
-
A.
Ao
A.
A.
A,
Au
o.
0,
O.
,--,GND
Au
Au
27C010L
2 Mblt
8 Mblt
Vee
Xx/PGM
XX
Vcc
Xx/PGM
Vcc
A14
A 13
As
A9
An
A17
A14
A 13
As
Ag
A,.
A17
A14
Ala
As
Ag
An
All
OE
OE
OElVpp
A 10
A 10
A1D
CEIPGM
CE
CE
CEtPGM
07
O.
O.
O.
O.
07
06
05
04
03
07
06
05
04
03
07
06
05
04
03
A"
OE
A,.
NOTE: 10. Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C040L pin.
PIN NAMES
Ao-A1S
Addresses
CE
Chip Enable
OE
Output Enable
0 0-0 7
Outputs
PGM
Program
XX
Don't Care (During Read)
---------------------~~;--------------------3·144
WS27C040L
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 -+ 5°C, Vee
= 6.25V +-
0.25V,
vpp = 12.75
± 0.25V)
SYMBOLS
MIN
MAX
UNIT
III
-10
10
IlA
Ipp
60
mA
50
mA
Input Low Level
lee
V1L
-0.1
0.8
V
Input High Level
V 1H
2.0
Vee +0.3
V
Output Low Voltage During Verify
(IOL = 2.1 mA)
VOL
0.4
V
Output High Voltage During Verify
(loH = -400 IlA)
VOH
PARAMETER
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During_ _
Programming Pulse (CE/PGM
= Vld
Vee Supply Current
NOTES:
3.5
V
11. Vee must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp.
12. Vpp must not be greater than 14 volts including overshoot. During CElPGM = V IL • Vpp must not be switched from 5 volts
to 12.5 volts or vlce·versa.
± 0.25V, Vpp
= 12.75
SYMBOLS
MIN
TYP
tAS
2
Il s
CE High to OE High
teoH
2
Output Enable Setup Time
tOES
2
IlS
IlS
Data Setup Time
AC CHARACTERISTICS (TA
= 25
PARAMETER
Address Setup Time
± 5°C, Vee
= 6.25V
tos
2
Address Hold Time
tAH
0
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tOF
0
Data Valid From Output Enable
tOE
Vpp Setup Time/CE Setup Time
tvs/teEs
2
PGM Pulse Width
tpw
0.05
OE Low to CE "Don't Care"
toex
2
± 0.25V)
MAX
UNIT
Il s
Ils
55
Ils
ns
55
ns
4
Il s
ms
Ils
PROGRAMMING WAVEFORM
ADDRESSES
DATA
vpp
v••
Vee
V IH
CE/PGM
VIL
V IH
OE
VIL
------------------------~Jri'-----------------------3-145
WS27C040L
PROGRAMMING/ERASURE/PROGRAMMERS
Refer to Section 5.
ORDERING INFORMATION
PART NUMBER
WS27C040L-120/5 *
WS27C040L-15C
WS27C040L-15CM *
WS27C040L-15CMB*
WS27C040L-150
WS27C040L-150MB *
WS27C040L-17C
WS27C040L-17CM
WS27C040L-17CMB
WS27C040L-170
WS27C040L-170MB
WS27C040L-20C
WS27C040L-20CM
WS27C040L-20CMB
WS27C040L-200
WS27C040L-200MB
SPEED
PACKAGE
TYPE
(ns)
120
150
150
150
150
150
170
170
170
170
170
200
200
200
200
200
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Pin CEROIp,
Pad CLLCC
Pad CLLCC
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pad CLLCC
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pad CLLCC
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
PACKAGE
DRAWING
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
04
C2
C2
C2
04
04
C2
C2
C2
04
04
C2
C2
C2
04
04
OPERATING
RANGE
TEMPERATURE Vee
Comm'l
Comm'l
Military
Military
Comm'l
Military
Comm'l
Military
Military
Comm'l
Military
Comm'l
Military
Military
Comm'l
Military
±5%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
WSI
MANUFACTURING
PROCEDURE
Standard
Standard
Standard
MIL-STO-883C
Standard
MIL-STO-883C
Standard
Standard
MIL-STO-883C
Standard
MIL-STO-883C
Standard
Standard
MI L-STO-883C
Standard
MIL-STO-883C
*These products are Advance Information.
------------------------~Jr;----------------------3-146
WS27C240L
ADVANCE INFORMATION
WAFERSCALE INTEGRATION, INC.
4 Meg (256K x 16) CMOS EPROM
KEY FEATURES
• Ultra-High Performance
-
• EPI Processing
120 ns
-
• Simplified Upgrade Path
-
Vpp is a "Don't Care" During Normal
Read Operation
Expandable to 8M Bits
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
• JEDEC Standard Pin Configuration
-
40 Pin Dip Package
44 Pin Chip Carrier
GENERAL DESCRIPTION
The WS27C240L is an ultra-high performance, 4,194,304-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 256K-words of 16 bits each. The 120 ns access time of the WS27C240L enables it to operate in
high performance systems. The "Don't Care" feature during read operations enables memory expansions up to 8M
bits with no printed circuit board changes.
High performance microprocessors such as the 80386 and 68020 require sub-120 ns memory access times to operate
at or near full speed. The WS27C240L enables such systems to incorporate operating systems and/or applications
software into EPROM. This in turn enhances system utility by freeing up valuable RAM space for data or other program
store and eliminating disk accesses for the EPROM resident routines.
The WS27C240L pin configuration was established to enable memory upgrades to 8M bits without hardware changes
to the printed circuit board. Pin 1 is a "don't care" during normal read operation. This enables higher order addresses
to be connected to this pin (see DIP Pin Configurations). When higher density memories are required, the printed
circuit board is ready to accept the higher density device with no hardware changes.
The WS27C240L is part of a high density EPROM family which spans densities from 64K to 4 Meg.
The WS27C240L is manufactured using WSI's advanced CMOS technology.
PRODUCT SELECTION GUIDE
PARAMETER
27C240L-12
27C240L-15
27C240L-17
27C240L-20
Address Access Time (Max)
120 ns
150 ns
170 ns
200 ns
Chip Select Time (Max)
120 ns
150 ns
170 ns
200 ns
Output Enable Time (Max)
35 ns
40 ns
40 ns
40 ns
3-147
WS27C240L
ABSOLUTE MAXIMUM RATINGS·
"Notice: Stresses above those listed under ''Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time
may affect device reliability.
Storage Temperature ........... -65°C to +125°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vce Supply Voltage with
Respect to Ground .............. -0.6V to + 7V
ESD Protection ....................... > 2000V
OPERATING RANGE
TEMPERATURE
Vcc
TOLERANCE
0° to +70°C
+5V
±5% or ±10%
Industrial
-40° to +85°C
+5V
±10%
Military
-55° to + 125°C
+5V
±10%
RANGE
Comm'l
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range with Vpp
Vee.
MIN
MAX
UNITS
VIL
Input Low Level
-0.5
0.8
V
V IH
Input High Level
2.0
V
VOL
Output Low Voltage
IOL = 2.1 mA
Vee + 1
0.4
VOH
IS81 (3)
Output High Voltage
Vee Standby Current (CMOS)
100
~A
IS82
Vee Standby Current
1
mA
PARAMETER
TEST CONDITIONS
lee(1)
Vee Active Current
IOH = -400 ~A
CE = Vee ± 0.3V
CE = V IH
_
_
IF = 5MHz
CE = OE = V IL F = 8 MHz
Vpp = Vee
Ipp
Vpp Slfpply Current
Vpp Read Voltage
III
Input Load Current
VIN = 5.5V or Gnd
ILO
Output Leakage Current
VO UT = 5.5V or Gnd
SYMBOL
PARAMETER
V
V
60
I
Vpp
AC READ CHARACTERISTICS
3.5
70
100
mA
~A
V
Vee -0.4
-1
Vee
1
~
-10
10
~A
Over Operating Range with Vpp = Vee.
27C240L-12
MIN
MAX
27C240L-15
27C240L-17
27C240L-20
MIN
MIN
MIN
MAX
MAX
MAX
tAee
Address to Output
Delay
120
150
170
200
teE
CE to Output Delay
120
150
170
200
tOE
OE to Output Delay
35
40
40
40
tDF(2)
Output Disable to
Output Float
35
40
40
40
tOH(2)
Output Hold From
Addresses, CE or
OE, Whichever
Occurred First(2)
UNITS
ns
0
0
0
0
NOTES:
1. The supply current is the sum of lee and Ipp. The maximum current value is with Outputs 0 0 to 0 7 unloaded.
2. ThiS parameter is only sampled and IS not 100% tested. Output Float is defined as the point where data IS no longer driven-see timing diagram.
3. CMOS Inputs: VIL = GND ± 0.3V, VIH = Vee ± 0.3V.
---------------------
----------------------~J';-.
3-148
WS27C240L
AC READ TIMING DIAGRAM
V ,H
ADDRESS
VALID
ADDRESSES
V"
V ,H
CE
V'L
V,H
-------I----""'\.
1+----- tACC ----.j
HIGH Z
HIGH Z
OUTPUT -------------~H+f_(
CAPACITANCE(4) TA
SYMBOL
1 MHz
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
CvPp
Vpp Capacitance
CONDITIONS
TYP(5)
MAX
VIN = OV
4
6
pF
V OUT = OV
8
12
pF
Vpp = OV
18
25
pF
UNITS
NOTES:
4. This parameter is only sampled and IS not 100% tested
5. TYPical values are for T A = 25°C and nominal supply voltages.
6 OE may be delayed up to tCE -tOE after the failing edge of CE without Impact on tCE '
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
2.04V
-r-
}
DEVICE
UNDER
TEST
~
8200
~ C L = 100 pF
I--
A.C. testing inputs are driven at 2.4V for a Logic "1" and
O.4V for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and O.BV for a Logic "0."
________________________
CL = 100 pF
CL includes Jig Capacitance
....,
_______________________
fJfjf~E
3-149
WS27C240L
DIP PIN CONFIGURATIONS
8 Mbit
2 Mblt
1 Mbit
512K
WS27C240L
57C257 57C65
XX/Vpp XXNpp XXNpp XX/Vpp XXlVpp -XXI Vpp
A,s
CE/PGM
CE
CE
CE
CE
CE
D,S
D,s
D,S
D,S
D,s
D,S
0,.
0,.
0,.
0,.
0,.
0,.
0'3
0'3
0'3
0'3
0'3
0'3
0'2
0'2
0'2
0'2
0'2
0"
0"
0"
0"
0"
1 - '0'2
0" I - 0"
0'0
Og
0'0
Og
0'0
Og
0'0
Og
0'0
Og
0'0
Og
r - - - 0,
Os
-CE/P
GM
- ,D,s
57C65 57C257
c-
.,7-
Vee
Vee
XXlPGM XX/PGM
512K
1 Mbit
2 Mbit
8 Mbit
Vee
Vee
Vee
Vee
XX/PGM
XX/PGM XX/PGM
NC
A,.
A'7
A,.
NC
A,s
A,s
A,s
A,.
A,.
A,.
A, •
A'3
A'3
A'3
A'3
A'2
A'2
A'2
A'2
A'2
A"
A,o
A"
A,o
A"
A10
A"
A10
A"
A,o
NC
NC
NC
NC
NC
NC
3-
NC
A'3
2-
NC
t - D.
.-
A"
A,o
.-
Ag
Ag
Ag
Ag
Ag
Ag
GND t - - - G NO
0-
GND
GND
GND
GND
GND
GND
--
As
As
As
As
As
As
.-
A7
A7
A7
A7
A7
A7
..-
A.
A.
A.
A.
As
A.
As
As
As
As
As
As
A.
A.
A.
A4
A.
A.
Aa
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A2
A,
A,
A,
A,
A,
A,
Ao
Ao
Ao
Ao
Ao
Ao
r------.0,.
r------'0'3
0'2
t - - - '0,.
.
-
,-
Os
Os
Os
Os
Os
GND
GND
GND
GND
GND
07
07
07
07
07
07
D.
D.
D.
D.
D.
D.
r - - - 07
r - - - D.
Os
05
Os
Os
Os
Os
t - 0,
O.
D.
D.
D.
D.
D.
- - -D.
03
03
03
03
03
03
r--- 03
O2
O2
O2
O2
O2
O2
- - - 02
.3- -
0,
0,
0,
0,
0,
0,
---0,
.-
00
00
00
00
00
00
---D.
,-
OE/Vpp
DE
OE
DE
DE
DE
- - - OE
.-
NC
NOTE: Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C240L pins.
PIN NAMES
LCC PIN CONFIGURATION (TOP)
Ao-A17
CE
Addresses
OE
Output Enable
0 0 -0 15
Outputs
NC
No Connection
XX
Don't Care (During Read)
PGM
Program
Chip Enable
I ~0.>~
JJcfl~~~~.fJJJ
---------------------------------------~~~-.--------------------------------------
3-150
WS27C240L
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 +
- 5°C, Vee
PARAMETER
Input Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During__
Programming Pulse (CE/PGM
6.2V +
- 0.25V, Vpp
SYMBOLS
MIN
MAX
UNIT
III
-10
10
IlA
60
mA
Ipp
= V IL)
Vee Supply Current
Input High Level
lee
V IL
V IH
Output Low Voltage During Verify
(lOL = 2.1 mAl
VOL
Output High Voltage During Verify
(lOH = -400 IlA)
VOH
Input Low Level
NOTES:
12.75 +
- 0.25V)
50
mA
-0.1
O.B
V
2.0
Vee +0.3
V
0.4
V
3.5
V
7. Vee must be applied either cOincidentally or before Vpp and removed either cOincidentally or after Vpp.
8. Vpp must not be greater than 14 volts Including overshoot. During eEIPGM = V ,L , Vpp must not be sWitched from 5 volts
to 12.75 volts or vice-versa.
AC CHARACTERISTICS (TA
= 25
+
- 5°C, Vee = 6.2V +- 0.25V, Vpp = 12.75 +- 0.25V)
SYMBOLS
MIN
TYP
MAX
UNIT
tAS
2
Ils
CE High to OE High
Output Enable Setup Time
Data Setup Time
Address Hold Time
teoH
tOES
tos
tAH
Data Hold Time
Chip Disable to Output Float Delay
Data Valid From Output Enable
tOH
tDF
tOE
2
2
2
0
2
0
PARAMETER
Address Setup Time
Vpp Setup Time/CE Setup Time
PGM Pulse Width
OE Low to CE "Don't Care"
tvs/teEs
tpw
toex
IlS
55
55
Ils
Ils
IlS
IlS
ns
ns
4
IlS
ms
2
0.05
2
Ils
PROGRAMMING WAVEFORM
ADDRESSES
DATA
Vpp
Vpp
Vee
V,H
CE/PGM
V'L
V,H
OE
V,L
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ fiiiiii 6Fliffo_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
'riNf18
3-151
WS27C240L
MODE SELECTION
The modes of operation of the WS27C240L are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for Vpp and on Ag for device signature.
~S
MODE
Table 1. Modes Selection
--OE
Ag
Ao
V pp
Vee
OUTPUTS
V IL
V IL
V IH
X
X
X
X
X
X
X
X
X
5.0V
X
5.0V
DOUT
High Z
5.0V
High Z
Vpp
6.2V
DIN
Vpp
6.2V
Vpp
6.2V
DOUT
High Z
X
X
5.0V
23 H
5.0V
C9 H
CE/PGM
Standby
V IH
X
Programming
V IL
V IH
Program Verify
X
V IL
Program Inhibit
V IH
V IH
X
X
X
X
X
X
V IL
V IL
V H(10)
V IL
V IL
V H(10)
V IH
Read
Output Disable
Manufacturer(11)
Signature:
Device(11)
NOTES: 9. X can be V1L or V1H
VIL
10. VH = Vpp
-----------------------------------~~~----------------------------------3-152
WAFERSCALE INTEGRATION, INC.
PROGRAMMABLE SYSTEM™ DEVICES (PSD)
4
SECTION INDEX
PROGRAMMABLE SYSTEM™ DEVICES (PSD)
Introduction to Programmable System Devices . ..................................... 4-1
MAP168/PSD301
Introduction
User-Configurable Peripheral with Memory ................................ 4-3
MAP168
User-Configurable Peripheral with Memory ................................ 4-7
PSD301
User-Configurable Peripheral with Memory ............................... 4-25
PAC1000 Introduction
User-Configurable Microcontroller ...................................... 4-29
PAC1000
User-Configurable Microcontroller ...................................... 4-31
SAM448 Introduction
User-Configurable Microsequencer ..................................... 4-79
SAM448
User-Configurable Microsequencer ..................................... 4-81
Electronic Bulletin Board ................................................................ 4-103
For additional information,
call 800-TEAM-WSI (800-832-6974).
In California, call 800-562-6363.
---------------------~Jri·---------------------
Programmable System™Devices
WAFERSCALE INTEGRATION, INC.
----------------------~Jri----------------------
Introduction to Programmable
System™ Devices (PSD)
WAFERSCALE INTEGRATION, INC.
Programmable System Devices, or PSDs,
are user-configurable system level building
blocks on-a-chip enabling quick
implementation of application specific
controllers and peripherals.
WSI PSDs are ideal for designers who
require fast time-to-market, low risk,
greater system integration and lower power
consumption. PSDs enable designers to
configure their microcontrollerlperipheral to
meet exact design requirements. WSI's
PSDs are unique in that they are the only
VLSI devices available today that provides
a user-configurable off-the-shelf solution at
the system level.
The user-configurability of PSDs enables
them to be used in many different
applications, including:
CI Computers (Workstations and PCs) Fixed Disk Control, Modem, Imaging,
Laser Printer Control
CI Telecommunications - Modem,
Cellular Phone, Digital PBX, Digital
Speech, FAX, Digital Signal Processing
CI Industrial - Robotics, Power Line
Access, Power Line Monitor
CI Medical Instrumentation - Hearing
Aids, Monitoring Equipment, Diagnostic
Tools
CI Military - Missile Guidance, Radar,
Sonar, Secure Communications, RF
Modems
PSDs are available in a variety of space
saving surface mount and through-hole
package configurations for commercial,
industrial, and military applications. WSI
offers windowed package options for
prototyping and low cost OTP (one-time
programmable) packages for high volume
applications. PSDs utilize WSI's proprietary
split-gate CMOS EPROM technology for
low power consumption.
There are currently four PSD family
devices in production. These include the
PAC 1000, MAP168, PSD301, and SAM448.
CI The PAC1000 is a user-configurable
microcontroller. It may be used as a
stand-alone microcontroller or as a
peripheral to microprocessors. It is ideal
for embedded control applications,
including graphics, local area network,
and disk drive control in both military
and commercial applications.
CI The MAP168 is a user-configurable
peripheral. It is used in DSP applications
including modems, motor control and
medical instrumentation. The MAP168
is ideal for DSP based applications
where fast time-to-market, small form
factor and low power consumption are
essential. When combined together in
an 8- or 16-bit system, virtually any
DSP chip (TMS320 series, etc.) and
the MAP168 work together to create a
very powerful 2-piece chip-set. This
combination provides essentially all of
the required control and peripheral
element of a DSP system.
CI The PSD301 is a user-configurable
peripheral for microcontroller applications
including disk drives, low cost modems,
and mobile phones. The PSD301 is ideal
for microcontroller based applications
where fast time-to-market, small form
factor and low power consumption are
essential. When combined together in
an 8- or 16-bit system, virtually any
microcontroller (8051, 8096, 16000, etc.)
and the PSD301 work together to create
a very powerful 2-piece chip-set. This
implementation provides the required
control and peripheral element of a
microcontroller based system peripheral
With no external "glue" logic required.
CI The SAM448 is a user-configurable
sequencer for state machine and bus
interface applications. Its flexible 110
and architecture make it ideal for use
in interfacing to both existing bus
architectures (AT, VME, MCA-bus), and
evolving bus standards (EISA, NuBUS).
4-1
Introduction to
Programmable System'" Devices (PSD)
Application specific features can be easily
programmed into the PSD EPROM array
for quick design implementation. Unlike
the current generation of programmable
gate arrays, which require the use of
unpredictable, and often time unavailable
routing resources, all PSD logic is fully
connected internally. This means that all
timing is predictable ahead of design
implementation, and routing is assured.
This greatly simplifies and reduces the
design implementation and simulation
process, and provides designers with a
significantly more reliable, lower risk path
to market. WSI PSDs also eliminate the
NRE, turn-around-time, and risks associated
with gate arrays and other ASIC solutions.
4-2
WAFERSCALE INTEGRATION, INC.
As product life cycles continue to shrink,
designers can win the race from idea to
marketable product with WSI PSDs. PSDs
are quickly configured and programmed by
the designer by using low cost, easy-touse WSI PC-based development tools. The
user-friendly menu-driven software includes
high level design entry, simulation and
programming packages for rapid system
development.
WSI supports its PSD product family with
an applications hotline and bulletin board,
as well as highly trained, technical Field
Applications Engineers. As standard
products, WSI PSDs are available from
WSl's franchised world-wide distribution
network.
-- == == ....=====
:r
..
~
~
~--
-~~
~~~~
-----~
r~.-"-~
----~....,
~
WAFERSCALE INTEGRATION, INC.
Overview
Programmable System™Device
MAPI68/PSD301 Introduction
User·Configurable
Peripheral with Memory
In 1988 WSI introduced a new concept in
programmable VLSI: the Programmable
System™ Device (PSD). The PSD is
defined as a family of User-configurable
system level building blocks on-a-chip
enabling quick implementation of application
specific control/ers and peripherals. The
first generation PSD series includes the
MAP168, a User-Configurable Peripheral
with Memory; the SAM 448, a UserConfigurable Microsequencer; and the
PAC 1000, a User-Configurable
Microcontroller.
The MAP168 is a high-performance, userconfigurable peripheral with memory. It is
used in DSP applications including
modems, motor control and medical
instrumentation. The MAP168 is ideal for
DSP based applications where fast time-tomarket, small form factor and low power
consumption are essential. When combined
together in an 8- or 16-bit system, virtually
any DSP chip (TMS320 series, etc.) and
the MAP168 work together to create a
very powerful 2-piece chip-set. This
implementation provides the core of the
required control and peripheral elements
of a DSP system.
Architecture
The MAP168 and PSD301 products
incorporate the flexibility of using discrete
memory addressing and decoding. With
the support of WSI's user friendly PSD
software called MAPLE, designers may
configure their MAP168/PSD301 subsystems
for 8 or 16 bit data paths. If the host
system uses an 8051 microcontroller, the
MAP168/PSD301 can be programmed with
an eight bit data path. A sixteen bit data
path can be programmed for
microcontrollers like Intel's 80196. The
depth of the memory organization will be
modified accordingly to accept the different
data path widths. The low cost MAPLE
software package will handle the data path
width adjustment automatically. The user
can select either 16K bytes of EPROM and
4K bytes of SRAM or 8K words of EPROM
The MAP168 contains three elements
normally associated with discrete solutions
to system memory requirements. It
incorporates EPROM and SRAM plus a
Programmable Address Decoder (PAD), all
on the same die. The MAP168 is ideal for
the systems deSigner who wishes to
reduce the board space of his final design.
By using the MAP168 in a system, five or
six EPROM, SRAM and decode logic
chips may be reduced into a single 44 pin
PLOCC, CLDCC or PGA package.
The second generation PSD301 is a userconfigurable peripheral for microcontroller
applications including disk drives, low cost
modems, and mobile phones. The PSD301
is ideal for microcontroller based
applications where fast time-to-market,
small form factor and low power
consumption
are essential.
When
combined together in an 8- or 16-bit
system, virtually any microcontroller (8051,
8096, 16000, etc.) and the PSD301 work
together to create a very powerful 2-piece
chip-set. Together, this implementation
provides all the required control and
peripheral elements of a microcontroller
based system peripheral with no external
"glue" logic required.
and 2K words of SRAM. The flexibility of
the MAP168/PSD301 products enables two
devices to be cascaded in width. It is
possible to double the memory size of a
sixteen bit system by using two MAP168
products in parallel but programmed in a
byte-wide configuration. For example, with
two MAP168 devices, 16K words of EPROM
and 4K words of SRAM may be organized
as upper and lower data bytes of a 16 bit
word. Alternately, two MAP168 chips may
expand the system memory vertically as
two word organized memory devices. A
block diagram of the MAP168 is shown in
Figure 1.
An important feature of the MAP168/PSD301
products is their ability to incorporate the
memory address decoding on-chip. One
4-3
MAP168/PSD301 Introduction
Architecture
(Cont.)
MAP168 memory peripheral can reside
with other MAP168 devices in the same
memory addressing scheme, with the onchip decoder allocating the memory blocks
to different non-conflicting segments of the
entire memory area. The decoding function
is achieved by an on-chip feature called a
Programmable Address Decoder (PAD),
which is similar to a single fuse array
programmable logic device supporting one
product term (AND gate) per output in the
MAP168 and four product terms per output
in the PSD301.
memory devices. The chip select lines
may be subdivided into ESO-ES7, active
low internal EPROM chip selects, and two
internal RAM chip selects RSO and RS1.
In byte-wide applications, eight chip select
outputs drive external pins CSO-CS7.
These can be used as external chip
selects for other MAP168 devices or
system memory. These outputs are
not available for word-wide MAP168
configurations because the CSO-CS7 output
pins carry the higher order data byte. Only
FCSO is available for external chip selection.
In the MAP168, eighteen standard chip
select outputs from the PAD are available
with one fast chip select output generally
used to select other external high speed
Figure 1 shows the organization of the
EPROM and SRAM in relation to the PAD,
for the MAP168 device.
Figure 1.
MAP168 Memory
Architecture
EPROM
2K x 8 OR lK x 16
EPROM
2K x 8 OR lK x 16
DATA BUS [8:15]
DATA BUS [0:7]
EPROM
2K x 8 OR lK x 16
ADDRESS BUS
EPROM
2K x 8 OR lK x 16
PAD
EPROM
2K x 8 OR lK x 16
ESO
ESI
EPROM
2K x 8 OR lK x 16
ES2
ES3 1 - - - - - '
ES41------'
ES5 \ - - - - - - '
EPROM
2K x 8 OR lK x 16
ES6\-----'
EPROM
ES7 1----I-~~2K~X::8~O~R:.l~K~X:.:l~6
WE/V pp
CSO[0:7]
CSO[O:7]
•
x
::>
:;;
1-----+-----..;.....;..--+-+-1
it:
OJ
>
RS11----,
f/J
FCSO
Z
EPROM
2K x 8 OR lK x 16
EPROM
2K x 8 OR lK x 16
DATA
BYTE
iii
(.)
RSO 1 - - - - - - ,
HIGH
~
...
OR
CSO
[0:7]
lOW DATA BYTE
Important Features:
•
•
•
•
4-4
40 ns EPROM/SRAM Access Time.
Byte or Word Operation, Mappable into 1M Word or 2M Byte Address Space
22 ns Chip-Select 8 Outputs, 17 ns Fast Chip Select Output.
128K EPROM Bits, 32K SRAM Bits, On-Chip Programmable Decoder, Security Bit.
WAFERSCALE INTEGRATION, INC.
MAP1681PS0301 Introduction
Figure 2.
PSD301 Family
Architecture
I
•
•
Vee
GND
RD
WRlVpp
BHE/PSEN
RESET
A,./CSI
AD a-AD 15
ADo-AD7
I
128K1256K/512K EPROM'
8 BLOCKS OF
EPROM
r--+
CONTROL
r--B
LATCH
Aa-A15
~
G3
ALE
CONFIGURATION
REGISTERS
~
+
LATCH
A
d
.&
CSEPROM
CS O-CS7
PAD
SEE
TABLE
°8- 0 15
•
PB O_ 7
•
PORT A
Do-D7/ADo-AD7
I
Ao-A7
CSRAM
•
~
'---
~
PORT B
0,-0 15
I-
16K BIT SRAM
PORT C
PCo_,
SEE
TABLE
MUX OR NON-MUX
CONTROL'
By 8 Configuration
Port A
Port B
MUX Address Data
PAO_7
"12K x 8 OR IK x 16
~ IDo-D7/ADo-AD 7
Non-MUX Address Data5
--
SEE
TABLE
By 16 Configuration
Port A
Port B
0 0 -0 7
CS O-CS 7 or
PB o-PB 7
0 0 -0 74
Ds-D'5
Ao-A74
PAo-PA 7
ADo-AD7
CS O-CS 74
PB o-PB 7
Ao-A7 4
PAo-PA 7
ADo-AD7
CS O-CS 7
PB o-PB 7
Port C
CSS-CS 106
A I6-A,s
NOTES:
I. Three MAP300 EPROM densilles.
2. Internal signal can be sel dUring programming.
3. Lalch B can be set to be transparent (not dependent on ALE)
4. Each I/O pin can be Individually sel to perform one of the two functions.
5. The non-MUX conflgurallon is compatible to MAPI68 plnoul
6 Port C is Independent of any configuration and can be chip seleci oul or address In.
Software Support
The object code generated for the support
microprocessor/microcontrolier is generated
by an assembler. This code, when
generated as an Intel MCS file, may be
easily programmed into the EPROM
section of the MAP168/PSD301 device
because the MAPLE software has been
designed to accept this standard format.
The programmable address decoder is
used to define the mapping of the various
EPROM and SRAM memory blocks. This
mapping is achieved by the designer in
the MAPLE environment. The software
provides a safeguard that prevents the
designer from inadvertently overlapping
the address selection. After selecting the
memory block assignments, the
MAP168/PSD301 device may be
programmed by the WSI MagicPro™
memory and PSD programmer.
WAFERSCALE INTEGRATION, INC.
4-5
~4_6-----------------------~Jr;------------------------
... _----...,
--.:....-ii-...ii-i-=
-==• .,.,
Programmable System™Device
~E£
~~...,.,
WAFERSCALE INTEGRATION, INC.
Features
0
MAP168
User-Configurable
Peripheral with Memory
First-generation Programmable System
Device (PSD)
User-Configurable Peripheral with
Memory
16Kx8 EPROM
4Kx8SRAM
Programmable address decoder
General
DescriptiDn
0
Byte or Word Memory Configurations
16Kx8 or 8Kx16 EPROM
4Kx8 or 2Kx16 SRAM
2Mbyte or 1 Mword address range
0
High-Speed Operation
40-nsec memory access
17-nsec fast chip select output
0
External Chip Select Outputs
8 external chip selects
1 fast chip-select output
In 1988 WSI introduced a new concept in
programmable VLSI, Programmable System
Devices (PSD). The PSD family consists of
user-configurable system-level building
blocks on-a-chip, enabling quick implementation of application-specific controilers and
peripherals. The first generation PSD series
includes the MAP168 User-Configurable
Peripheral with Memory; the SAM448, a
User-Configurable Microsequencer; and the
PAC1000, a User-Configurable Microcontroiler.
The MAP168 is the first of WSl's Programmable System Devices (PSD) product line.
The device integrates high performance,
user-configurable blocks of EPROM, SRAM,
and logic in a single circuit. The major
functional blocks include a Programmable
Address Decoder (PAD), 16K bytes of high
speed EPROM, and 4K bytes of high speed
SRAM. A block diagram is given in Figure 1.
The MAP168 device is a complete memory
subsystem that can be mapped anywhere in
a 2M-byte address space of a microprocessor or microcontroiler system. The EPROM
and SRAM memory blocks can be userconfigured in either byte-wide or word-wide
organizations. The MAP168 device signifi-
0
Programmable Security
Protects memory map
Protects program code
0
Programming Support Tools
PSD integrated software environment
PC-XT/AT/PS2 platform support
MAPLE location entry Software
MAPPRO device programming Software
MagicPro device programmer (PC-XT,
AT)
0
Military and Commercial Specifications
44-pin Ceramic Leaded Chip Carrier
package
44-pin Plastic Leaded Chip Carrier
package
44-pad Ceramic Leadless Chip Carrier
package
44-pin Ceramic Pin Grid Array package
cantly reduces the board space and power
necessary to implement memory subsystems, increases system performance, and
provides for secure data or program storage.
The device's high level of integration and
flexibility make it ideal for high-speed microprocessors, microcontroilers, and Digital
Signal Processors like the TMS320XX family.
The EPROM can be configured either as
16Kx8 or 8Kx16. The SRAM can be configured either as 4Kx8 or 2Kx16. Individual
memory blocks of 2Kx8 or 1Kx16 can be
selectively mapped anywhere in the address
space. Since the Chip Select Input (CST) can
be programmed as A20, the highest-order
address bit, the device's address range can
extend from 1M byte with CST to 2M byte
without CST.
For 16-bit microprocessors capable of byte
operations, the MAP168 device provides a
Byte High Enable input for accessing bytes
on any address boundary.
Pinout is compatible with the JEDEC
WS27C257 256K high-speed EPROM. This
pinout provides for memory expansion with
future WSI EPROM and PSD products.
The device's PAD and EPROM memory are
WAFERSCALE INTEGRATION, INC.
4-7
0
MAP168
Figure 1.
BIDCk Diagram
MAP168
DECODED EPROM
ADDRESS
-
-----"'-
Ao-A12
----v
EPROM
8Kx8
PGMH
----0
PGM
"
EOEH
OE
Ao-A19
OUTO_7
EPROM
8K x 8
PGM
OE
OUTO_7
1NO_7
>t -
L
PGML
,-----.
1N0-7
Ao-A12
r----
EOEL
I---
i----DECODED SRAM
ADDRESS
-----"'-
Ao-A12
PAD
----v
SRAM
2K x8
WEH
ROEH
OE
E/\pp OE SI/A 20 FCSO
-
~
SRAM
2Kx 8
,----t WE
WE
BHE -
Ao-A12
OUT0-7
WEL
,-----.
1NO_7
<
i-----
i'-
i-----
I---
OE
1NO_7
OUT0-7
<
t-
ROEL
f--f--f---
CON
CS0-7
'--
~t
"
r
OEL
f--
-
OEH
~
2'1
MUX
,..
2'1
MUX
-
'----
-
I
r-'i
,.
tv'!
-
V\
l
L,--,
~
tv'! 11
~'--
--.J
1/08-15 OR CSOO_7
4-8
WAFERSCALE INTEGRATION, INC.
1/0 0_ 7
1737 01
MAI'168
General
Description
(Con't,
Functional
Description
Table 1.
Pin Description
programmed using the same WSI MagicPro
programmer used to program other WSI
devices. Two software packages, MAPLE
Location Entry and MAPPRO Device Programming Software are available in the
menu-driven WISPER software environment
on an IBM" PC XT/AT or 100% compatible
platform.
For additional information on the MAP168
device, refer to Application Note No. 002,
Introduction to the MAP168 User-Configurable Peripheral with Memory. For additional
information on development and programming software for the MAP168 device, refer
to the MAP168 User-Configurable Peripheral
with Memory Software User's Manual.
The user-configurable architecture of the
MAP168 consists of an EPROM memory
block, an SRAM memory block, and a fast
Programmable Address Decoder (PAD) that
can be configured to select 2K-byte memory
blocks anywhere in a 2M-byte address
range. The device can be programmed to
operate with memory configured either in a
byte or word organization (bytes can be
addressed in word mode). A programmable
security bit prevents access to the PAD
address-decode configuration table.
Signal
Ao-19
FCSO
I/O
I
°
BHE
WENpp
DE
CSI/~
1/00-7
1/08-15, CS00-7
I/O
I/O
Description
Address Lines. For access to EPROM or SRAM.
Fast Chip-Select Output (active low). Used by the Programmable Address Decoder (PAD).
Byte High Enable (active low). Selects the high-order
byte when writing to SRAM.
Write Enable (active low) or Programming Voltage. In
normal mode, this pin causes data on the I/O pins to be
written into SRAM. In programming mode, the pin
supplies the programming voltage, Vpp'
Output Enable (active low). Enable the I/O pins to drive
the external bus.
Chip Select Input (active low) or High-Order Address.
This pin can be programmed as the bus-access chip
select or as an additional high-order address bit (~).
Low-Order Byte of EPROM or SRAM.
High-Order Byte or Chip-Select Outputs. In word mode,
these pins serve as the high-order byte (1/08-15) of
EPROM or SRAM. In byte mode, the bits serve as ChipSelect Out signals (CS00-7) for the Programmable
Address Decoder (PAD).
WAFERSCALE INTEGRATION, INC.
4-9
II
MAP168
Programmable
Address Decoder
The MAP168 device has a minimum of 20
address inputs Ao-A'9 allowing the EPROM
and SRAM memory blocks to reside anywhere in a 1M-byte address space. If the
CSI/A20 input is user-configured as an address line, the maximum addressable space
increases to 2M bytes, as shown in the
Configurations table.
The 16K bytes of EPROM and 4K bytes of
SRAM, can be configured into eight independent 2K-byte blocks and two 2K-byte
blocks respectively, as shown in the Memory
Architecture figure. The PAD is a userconfigurable address decoder that compares
input addresses to the 2K-byte address
range selected for each of the eight EPROM
blocks and two SRAM blocks. When the
input address Ao-A,o is detected to be within
one of the EPROM or SRAM address
ranges, the PAD enables an internal chip
select (ESo-ES7 or RSo-RS,) to the selected
block. If no block is selected, both the
EPROM and SRAM memories remain in a
power-down mode and the outputs are
disabled allowing other devices to drive the
Memory
Subsystem
EPROM Memory
The memory configuration of the MAP168
device includes 128K bits of WSI's patented
high-speed, split-gate, UV-erasable EPROM.
The EPROM is configured in byte mode as
16Kx8 and in word mode as 8Kx16. The
memory is organized as eight 2Kx8 or 1Kx16
blocks, as shown in the Block Diagram
figure. Each block has a separate and
independent address range that cannot
overlap. Each block is individually selected
by one of the ES o-ES 7 internal chip selects
generated by the PAD when an input address is detected within its designated
address range, as shown in the Memory
Architecture figure. If not selected, each
block of EPROM remains in a power-down
mode.
For programming, the EPROM memory
requires the WEN pp input to maintain the
programming voltage V pp'
4-10
WAFERSCALE INTEGRATION, INC.
data bus. The SRAM retains its data in the
power-down mode. The 2K-byte address
ranges for any of the eight EPROM or two
SRAM blocks may not overlap.
The PAD can also be user-configured to
generate up to eight external chip selects,
CSo-CS?, These outputs can be used to
decode the input address lines Ao-A2o and to
select other devices in the system. The
outputs CSO-CS 7 are available on the eight
higher-order 1/08-1/0'5 lines but only when
the MAP168 device is configured in the byte
mode; the lines are not available as chipselect outputs when the device is configured
in the word mode.
The CSI/A,o input is user-configurable as the
most-significant address line or as an activelow chip enable. Its function is programmed
as part of the PAD programming cycle.
The PAD also provides FSCO, a single, fast
chip-select output configurable by the user for
any address. It can overlap with any of the
internal EPROM, SRAM or external CSO
addresses.
SRAMMemory
The device also includes 32K bits of highspeed SRAM. The SRAM is configured in
byte mode as 4Kx8 and in word mode as
2Kx16. The memory is organized as two
2Kx8 or one 2Kx16 block(s), each with a
separate and independent address range that
cannot overlap. Each SRAM block is individually selected by one of the RSo-RS" shown
in the Memory Architecture figure, when an
input address is detected by the PAD within
its designated address range. When not
selected, each of the SRAM memory blocks
remains in a power down mode but does
retain all data stored.
Data can be written into the SRAM only when
the WENpp input is active low.
MAP168
Memory
Subsystem
EPROM Memory
(Con't)
Byte/Word Mode
PAD available on the eight high-order inpuV
output lines 1/08-1/0,~d enabled onto the
output bus when the OE input is low.
The PAD can be programmed to configure
the MAP168 device for either a byte or word
memory architecture. This allows the device
to be used conveniently with either 8-bit or
16-bit microcontrollers, microprocessors or
digital signal processor (DSP) systems. See
the Configurations table.
In word mode, the EPROM is organized as
8Kx16 and the SRAM as 2Kx16. The outputs
of both are tied to the 16 inpuVoutput lines
1/00-1/0 '5 and enabled onto the bus when OE
is low.
In byte mode, the EPROM is organized as
16Kx8 and the SRAM as 4Kx8. The outputs
of both are tied to the eight low-order inpuV
output lines 1/00-1/0, and enabled onto the
output bus when the OE input is low.
In word mode, the BHE input along with
address input AO allows the eight bits of any
16-bit word on an even or odd boundary to
be selected as shown in the High-Low Byte
Selection table. This is a useful feature for
16-bit processors that are not restricted to
reading or writing memory only on even-word
address boundaries.
Only when configured in byte mode are the
eight external chip selects provided by the
Mode Selection
The device's operational mode is controlled
by three inputs, CSI, OE, and WENpp. There
Table 2.
Configurations
are ten separate modes of operation, all of
which are shown the Mode Selection table.
x8 Configuration
CSI
A20
x16 Configuration
CSI
A20
Address Space
words
1M bytes
2M bytes
512K words
1M
Block Size
words
2K bytes
2K bytes
1Kwords
1K
Addressable Blocks
512
1024
512
1024
EPROM Blocks
8
8
8
8
2
2
SRAM Blocks
2
2
Chip-Select Outputs
9
9
EPROM Configuration
16Kx8
16Kx8
8Kx16
8Kx16
SRAM Configuration
4Kx8
4Kx8
2Kx16
2Kx16
1/0 Pins
8
8
16
16
Low-power Standby
yes
no
yes
no
Protected Mode
yes
yes
yes
yes
Byte Operations
yes
yes
yes
yes
WAFERSCALE INTEGRATION, INC.
4-11
MAP16B
Tablea.
Mode Selection
Table 4.
High/Low Byte
Select/on
"Cf/7JE WElVpp
Mode/Pln
Address
Read EPROM/SRAM VIL VIL
VIH
Read External
VIL VIL
VIH
Output Disable
Stand-By
X
X·
X
X
X
VIL
VIL
SRAM Selected
No SRAM
Selected
EPROM
Program Address
WriteSRAM
Write External
VIH
VIH X
VIL X
VIL X
Program EPROM
VIL VIH Vpp
Program Verify
EPROM
Program PAD
VIL VIL
Program Verify PAD
VIL VIL
VIH
VIL VIH Vpp
VIH
EPROM/SRAM
Selected
EPROM/SRAM
Not Selected
EPROM
Program Address
PAD Program
Address
PAD Program
Address
x16(FCfD)
x16 (1/00-1J
x8FCf/J, "CfDB-7
x8 (1/00-7)
CSOUT
DOUT
HighZ
CSOUT
HighZ
HighZ
X
CSOUT
CS OUT
CSOUT
CSOUT
DIN
DIN
DOUT
CSOUT
DIN
DIN
DOUT
CSOUT
DIN
x16 Configuration Only
1JfIE (Pin 1)
o
o
AD
0
o
Read Operation
Whole word
Write Operation
Whole word
Upper byte fromlto
odd address
Lower byte from/to
even address
None
Upper byte = Data Out
Lower byte = 'FF'
Whole word
Upper byte = Data Out
Lower byte = 'FF'
WR and BHE are used for SRAM functions
Table 5. Product
Select/on Guide
Parameter
Address Access Time (max)
Chip-Select Access Time (max)
Output Enable Time (max)
Chip-Select Output Time
Fast Chip-Select Output Time (max)
4-12
WAFERSCALE INTEGRATION, INC.
MAP168-40
MAP168-45
MAP168-55
40
40
18
22
17
45
45
21
25
20
55
55
23
27
22
Units
ns
ns
ns
ns
ns
---- - -
--------~-
MAP168
Table 6. DC
Characteristics
Parameter
Symbol
Test Conditions
Output Low Voltage
VOL
VOH
IOL=8 mA
IOH=-2 mA
CMOS Standby
Current
-Commercial
-Military
IS61
notes 1,3
TTL Standby
Current
-Commercial
-Military
IS62
CMOS Active Current
No Blocks Selected
-Commercial
-Military
Icc 1A
CMOS Active Current
EPROM Block Selected
-Commercial
-Military
Icc 1B
CMOS Active Current
SRAM Block Selected
-Commercial
-Military
Icc 1C
TTL Active Current
No Blocks Selected
-Commercial
-Military
Icc 2A
TTL Active Current
EPROM Block Selected
-Commercial
-Military
Icc 2B
TTL Active Current
SRAM Block Selected
-Commercial
-Military
Icc 2C
Input Load Current
III
V1N =5.5V
orGND
Output Leakage Current
ILO
VouT=5.5V
Output High Voltage
Min
Max
Units
0.5
V
2.4
V
20
30
mA
mA
30
40
mA
mA
20
30
mA
mA
35
45
mA
mA
55
65
mA
mA
30
40
mA
mA
40
50
mA
mA
65
75
mA
mA
-10
10
IlA
-10
10
IlA
notes 2, 3
notes 1,4
notes 1,4
II
notes 1,4
notes 2,4
notes 2, 4
notes 2, 4
orGND
Notes:
1. CMOS inputs: GND ± 0.3V or VCC ± 0.3V.
2. TTL inputs: V 1L ::; 0.8V, V1H ~ 2.0V.
3. Add 1.5 mA/MHz for AC power component.
4. Add 3.5 mA/MHz for AC power component.
WAFERSCALE INTEGRATION, INC.
4-13
MAI'168
Table 7. AC
Characteristics
",..,.,.,.
Read Cycle Time
Address to Output Delay
CSI to Output Delay
DE to Output Delay
Output Disable to Output Float
Chip Disable to Output Float
Address to Output Hold
Address to CSOo-7 True
Address to FCSO True
SRAM Write Cycle Time
Chip Enable to Write End
Address Setup Time
Address Hold Time
Address Valid to Write End
SRAM Write Enable Pulse Width
Data Setup Time
Data Hold Time
Write Enable to Data Float
Write Disable to Data Low Z
BHE Setup Time
BHE Hold Time
Table 8. lIafa
Retention
Characteristics
4-14
Symbol MA1'16B-40
Min Max
tRC
40
40
tACC
40
tCE
18
tOE
15
tOEF
15
tCSF
10
tOH
22
tcso
17
tFCSO
40
twc
40
~w
tAS
0
0
tAH
40
tAW
25
tpWE
tDS
20
0
tDH
18
twEF
3
tWELZ
tSHES
0
10
tSHEH
MAP16B-45
MIn Max
45
45
45
21
18
18
10
25
20
45
45
0
0
45
30
20
0
21
3
0
10
MAP16B-55
Min Max
55
55
55
23
20
20
10
27
22
55
55
0
0
55
35
30
0
23
3
0
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
".,.."",.,.
Symbol
Test Conditions
Min
Minimum Vee for Data Retention
VDR
2.0
V
Current in Data Retention Mode
ICCDR
Vcc=2.0V.
CSI ~ Vcc-o.2V.
VIN ~ Vcc-o.2V
orVIN:S; 0.2V
0
ns
tRC
ns
Chip Deselect to Data Retention
tCSDR
Recovery Time from Data Retention
tRDR
WAFERSCALE INTEGRATION, INC.
Max
Units
Units
rnA
MAP168
Absolute
Maximum Ratings
Storage Temperature ........... -65°C to +150°C
stress rating only and functional operation of
the device at these or any other conditions
above those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods of time may
affect device reliability.
Voltage to any pin with
respect to GND .......................... -0.6V to +7V
Vpp with respect to GND ....... -0.6 V to +14.0V
ESD Protection ................................... >2000V
Stresses above those listed here may cause
permanent damage to the device. This is a
Table 9. Operating
Range
Range
Temperature
Vee
Commercial
0" to +70"C
+5V± 5%
Military
_55" to +125"C
+5V ± 10%
Figure 3.
Read Cycle
Timing Diagram
tRC
ADDRESSES
~
K
14--
tACC
tCE _ _
tOH ___
tCSF -
\
/
-
~
tOE
I
DOUT
\
DATA VALID
tOEFj
~ ri4-
)
f4--- tFCSO f4--- tcso - - 1737 03
WAFERSCALE INTEGRATION, INC.
4-15
MAP168
Figure 4.
Test Load
980
2.01V~
D.U T.
30 pF
I.,.
(INCLUDING
SCOPE AND JIG
CAPACITANCE)
High-impedance test systems
Table 10.
Timing Levels
Level
Voltage
Input
o and 3V
Reference
1.SV
Figure 5.
Write Cycle
Timing Diagram
1737 04
we
ADDRESSES
~
.--1
\\\1\\\\\\\\
:1
tesw
tAW
/
\
WE
~tAS
...
tpWE
_t
tAH_
DS
____
tWEr
_
t DH
1
.\
DOUT
I
I
'I
I
V
I I
1\
I
_tWELZ
I
DATA-IN VALID
BHE
I
I
I
t BHES ...
4-16
WAFERSCALE INTEGRATION, INC.
-
BHE VALID
t BHEH -
-
\1
/1/
III
I
II
.\ \
1737 05
MAP168
Figure 6.
Memory
Architecture
DIRECT ADDRESSES
ADDRESS BUS
BLOCK
DECODE
ADDRESSES
PAD
ES0-7
1--7---+-"""
WAFERSCALE INTEGRATION, INC.
4-17
MAP168
Table 11. MAP168
Pin Assignments
44-pin CLOCC Package
44-pin PLOCC Package
44-pad CLLCC Package
Pin No.
xB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
GND
WENpp
eSI/A20
es07
esos
es0
eso.
es03
es02
5
x16
SHE
WENpp
CSI/A 20
1/°'5
11O,.
1/°'3
1/°,2
11O"
1/°,0
CSO,
CSOo
I/O g
IIO s
GND
GND
FCSO
FCSO
1/°7
I/O s
1/°5
110.
1/°3
1/° 2
11O,
1/°7
I/O s
1/°5
1/°0
OE
Ao
A,
A2
A3
A.
As
As
A7
As
A9
A,o
1/°0
OE
Ao
A,
A2
A3
A.
As
As
A7
As
A9
A,o
I/0.
11°3
1/°2
11O,
GND
GND
A"
A'2
A'3
A,.
A,s
A,s
A17
A,s
A'9
A"
A'2
A'3
A,.
A,s
A'6
A'7
A,s
A'9
Vee
Vee
WE and SHE are for SRAM functions.
4·18
WAFERSCALE INTEGRATION, INC.
_c _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
MAPt68
Table 12. MAP168
Pin Assignments
44-pin CPGA Package
Pin No.
x8
GNO
As
A,
WENpp
CSI/A20
B,
CS0 7
A3
CSOs
B3
CSOs
A2
CSO,
B2
CS03
B1
C2
CS02
C1
CS0 1
O2
CSOo
01
GNO
FCSO
E1
E2
1/°7
I/0 s
F1
I/0
F2
s
G1
11O,
G2
1/°3
H2
1/°2
G3
1/°1
H3
11°0
xt6
BHE
WENpp
CSI/A20
1/01s
11°1,
1/°13
11°12
1/°11
1/°10
1/°9
I/0 s
GNO
FCSO
1/°7
I/0 s
I/0 s
11O,
1/°3
1/°2
11°1
1/°0
G,
OE
OE
H,
Hs
Gs
Hs
Gs
H7
G7
Gs
F7
Fs
E7
Es
Os
07
Cs
C7
Bs
B7
A7
Bs
As
Bs
AD
A1
A2
A3
A,
As
As
A7
As
A9
A10
AD
A1
A2
A3
A,
As
As
A7
As
A9
A10
GNO
GNO
A11
A12
A13
A1,
A1S
A1S
A17
A1S
A19
A11
A12
A13
A1,
A1S
A1S
A17
A1S
A19
Vee
Vee
WAFERSCALE INTEGRATION, INC.
0
4·19
MAP168
Figure 7.
Pin Assignments
Programming
44 PIN PLOCC PACKAGE
6 5 4 3 2 14443424140
IIIII11I11111111111111
1_' I_I 1_' ,_I '_I I I ,_, I_I '_I ,_, '_I
]
44 PAO CLLCC OR CLOCC PACKAGE
6 5 4 3 2 14443424140
IIIII11111111111111111
c:
c:
c:
c:
c:
c:
c:
c:
c:
c:
U
8
9
10
11
12
13
14
15
16
c:
I_I 1_' 1_' I_I 1_' I I I_I '_I I_I I_I '_1
::1
39
7
38
37
36
35
34
33
32
31
30
29
8
::1
9
::.
10
11
12
13
14
15
16
::'
::'
::'
:)
::'
::'
::'
17
::.
0
'_I
c:
c:
c:
C:
c:
c:
c:
c:
c:
c:
c:
I-I I-I I-I I-I I-I I-I I-I I-I I-I '-I I-I
I-I I-I I-I I-I I-I I-I I-I I-I I-I I-I I-I
IIIII1IIIII11111111111
IIII1I1111111111111111
18192021 22232425262728
18192021 22232425262728
TOP (THROUGH PACKAGE) VIEW
TOP (THROUGH PACKAGE) VIEW
39
38
37
36
35
34
33
32
31
30
29
44 PIN CPGA PACKAGE
1 234 5 6 7 8
A
000000
s00000000
C 00
00
000
00
E 00
00
F 00
00
G 00000000
H
000000
TOP (THROUGH PACKAGE) VIEW
1737 07
Upon delivery from WSI or after each
erasure (see Erasure section), the MAP168
device has all bits in the PAD and EPROM in
the "one" or high state. Zeros are loaded
through the procedure of programming.
Information for programming the device is
available directly from WSI. Please contact
your local sales representative.
Erasure
To clear all locations of their programmed
contents, expose the device to an ultra-violet
light source. A dosage of 15W-second/cm' is
required. This dosage can be obtained with
exposure to a wavelength of 2537A and
intensity of 12001lW/cm' for 15 to 20 minutes.
The device should be about one inch from
the source and all filters should be removed
from the UV light source prior to erasure.
The MAP168 device and similar devices will
erase with light sources having wavelengths
shorter than 4000A. Although erasure times
will be much longer than with UV sources at
2537A, the exposure to fluorescent light and
sunlight will eventually erase the device; for
maximum system reliability, these sources
should be avoided. If used in such an environment, the package windows should be
covered by an opaque label or substance.
System
Development
Tools
MAP168 System Development Tools are a
complete set of PC-based development
tools. Installed on an IBM PC or compatible
computer, these tools provide an integrated,
easy-to-use software and hardware environment to support MAP168 device develop-
ment. The tools run on an IBM-XT, AT, or
compatible computer running MS-DOS
version 3.1 or later. The system must be
equipped with 640K bytes of RAM and a hard
disk.
4-20
WAFERSCALE INTEGRATION, INC.
MAP168
System
Development
Tools (Con't)
Hardware
Software
The MAP168 System Programming Hardware consists of:
The MAP168 System Development Software
consists of the following:
CJ
CJ
CJ
WS6000 MagicPro Memory and PSD
Programmer
WS6003 44-pin LCC Package Adaptor
(for 44-pin CLLCC, CLDCC, and PLDCC
packages)
WS6011 44-pin CPGA Package Adaptor
CJ
MAP PRO Software-Device Programming Software
The configuration of the MAP168 device is
entered using MAPLE software. MAPRO
software configures MAP168 devices by
using the MagicPro programmer and the
socket adaptor. The programmed MAP168 is
then ready to be used. The development
cycle is depicted in Figure 8.
The MagicPro Programmer is the common
hardware platform for programming all WSI
programmable products. It consists of the
IBM-PC plug-in Programmer Board and the
Remote Socket Adaptor Unit.
Figure 8. MAP168
Development
Cycle
WISPER Software-PSD Software
Environment
CJ MAPLE Software-MAP168 Location
Editor
CJ
pc
,-------..,
IBM
I[ l
User
Terminal
Menu Selection
I
I
I
I
I
I
I
I
PLATFORM
I
I
DOS
t
WISPER
I
I
I
I
t
Configuration Data I
MAPLE
I
I
I
I
r-r
I
t
Pr()!ll'amming Data I
MAPRO
I
I -G
0
I
I
I
DISK
--,
I
-t ----
I
----
I
Hex File
Format
~
[§]
MaglcPro Hardware
1737 08
WAFERSCALE INTEGRATION, INC.
-----
----
4-21
MAP168
System
De"elopment
Tools (Con't)
Ortlerlng
Information
SUpport
WSI provides a complete set of quality
support services to registered System
Development Tools owners. These support
services include the following:
Q 12-month Software Updates.
Q
Hotline to WSI Application ExpertsFor direct design assistance.
Q
24-Hour Electronic Bulletin BoardFor design assistance via dial-up
modem.
MAI'168
Part Number
MAP168-40C*
MAP168-40J*
MAP168-40L*
MAP168-45C
MAP168-45CM*
MAP168-45CMB*
MAP168-45J
MAP168-45L
MAP168-45LM*
MAP168-45LMB*
MAP168-45X
MAP168-45XM*
MAP168-45XMB*
MAP168-55C
MAP168-55CM
MAP168-55CMB
MAP168-55J
MAP168-55L
MAP168-55LM
MAP168-55LMB
MAP168-55X
MAP168-55XM
MAP168-55XMB
Spesd
(ns)
40
40
40
45
45
45
45
45
45
45
45
45
45
55
55
55
55
55
55
55
55
55
55
Packags
Type
44-pad CLLCC
44-pin PLDCC
44-pin CLDCC
44-pad CLLCC
44-pad CLLCC
44-pad CLLCC
44-pin PLDCC
44-pin CLDCC
44-pad CLDCC
44-pad CLDCC
44-pin CPGA
44-pin CPGA
44-pin CPGA
44-pad CLLCC
44-pad CLLCC
44-pad CLLCC
44-pin PLDCC
44-pin CLDCC
44-pin CLDCC
44-pin CLDCC
44-pin CPGA
44-pin CPGA
44-pin CPGA
*These products are advanced information.
4-22
WAFERSCALE INTEGRATION, INC.
Training
WSI provides in-depth, hands-on workshops
for the MAP168 device and System Development Tools. Workshop participants learn how
to program their own high-performance, userconfigurable mappable memory subsystems.
Workshops are held at the WSI facility in
Fremont, California.
Package
Drawing
C3
J2
L4
C3
C3
C3
J2
L4
L4
L4
X2
X2
X2
C3
C3
C3
J2
L4
L4
L4
X2
X2
X2
Operating
Temperature
Commercial
Commercial
Commercial
Commercial
Military
Military
Commercial
Commercial
Military
Military
Commercial
Military
Military
Commercial
Military
Military
Commercial
Commercial
Military
Military
Commercial
Military
Military
Manufacturing
Procedure
Standard
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
MAP76B
Olderlng
Information
System Development Tools
Part Numbsr
MAP168-GOLO
Contents
WISPER Software
MAPLE Software
User's Manual
WSI-SUPPORT
WS6000 MagicPro Programmer
MAP168-SILVER
WISPER Software
MAPLE Software
User's Manual
WSI-SUPPORT
WS6000
MagicPro Programmer
IBM PC plug-in Adaptor Card
Remote Socket Adaptor
WS6003
44-pin LCC Package Adaptor for
44-pin CLLCC, CLOCC, and PLOCC Packages.
Used with the WS6000 MagicPro Programmer.
WS6011
44-pin CPGA Package Adaptor.
Used with the WS6000 MagicPro Programme,r.
WSI-SUPPORT
Support Services including:
12-month Software Update Service
CJ
CJ
CJ
WSI-TRAINING
Hotline to WSI Application Experts
24-hour access to WSI Electronic Bulletin Board
Workshops at WSI, Fremont, CA.
For details and scheduling, call PSO Marketing, (415) 656-5400.
WAFERSCALE INTEGRATION, INC.
4-23
~4_~24----------------------~Jri------------------------
Programmable System™Device
WAFERSCALE INTEGRATION, INC.
'SD301
Preliminary
User·Configurable
Pedpheral with Memory
Key Features
o
Second Generation Programmable
System Device
o
User-Configurable Peripheral for
Microcontroller Based Applications Enables rapid design implementation and
fast time to market
o
Available in space saving surface mount
and through-hole packages
o
o
Windowed package option for prototyping
o
o
-
Selectable 8- or 16-Bit Bus Width
-
Power-Down
-
Address Inputs Can Be Latched or
Transparent
-
Latched Low-Order Address Byte
Available as Output
High-Density UV EPROM
Low cost aTP (one-time programmable)
package for high volume applications
256K Bits Configurable as 32K x 8 or
as 16K x 16
-
Divided Into Eight Equal Mappable
Blocks
CMOS for low power consumption
-
User-Configurable to Interface with Any
8- or 16-Bit Microcontroller
EPROM Block Resolution of 4K Bytes
or 2K Words
-
EPROM: Up to 120 ns Access Time
(Including PAD Decoding Time)
Programmable Address Decoder (PAD)
-
Programmable Control Signals
-
Programmable Polarity
-
Built-In Address Latches
Port Expansion/Reconstruction of Up to
16 I/O Lines
-
Applications
Multiplexed or Non-Multiplexed
Address/Data Buses
-
-
o
o
-
Individually Configurable as Output
or Input
o
o
Static RAM
-
16K Bits Configurable as 2K x 8 or
as 1K x 16
-
SRAM: Up to 120 ns Access Time
(Including PAD Decoding Time)
Addressable Range
-
1 MByte or 0.5 MWords
o
Highly Configurable, Many Operational
Modes
o
Low Power TIL-Compatible CMOS Device
o
Computers (Workstations and PCs) Fixed Disk Control, Modem, Imaging,
Laser Printer Control
o
Medical Instrumentation - Hearing Aids,
Monitoring Equipment, Diagnostic Tools
o
Telecommunications - Modem,
Cellular Phone, Digital PBX, Digital
Speech, FAX, Digital Signal Processing
o
Industrial - Robotics, Power Line
Access, Power Line Monitor
CJ Military - Missile Guidance, Radar, Sonar,
Secure Communications, RF Modems
4-25
P50301
Product
Description
In 1988 WSI introduced a new concept in
programmable VLSI, Programmable System
Devices. The PSD family consists of userconfigurable system-level building blocks
on-a-chip, enabling quick implementation
of application-specific controllers and
peripherals. The first generation PSD
series includes the MAP168, a UserConfigurable Peripheral, which is ideal for
DSP applications; the SAM448, a UserConfigurable Microsequencer for control
and interface applications, and the PAC1000,
a User-Configurable Microcontroller.
The PSD301 is a second generation PSD.
The PSD301 is ideal for microcontroller
based applications where fast time-tomarket, small form factor and low power
consumption are essential. When combined
together in an 8- or 16-bit system, virtually
any microcontroller (8051, 8096, 16000,
etc.) and the PSD301 work together to
create a very powerful 2-piece chip-set.
This implementation provides all the
required control and peripheral elements
of a microcontroller based system peripheral
with no external "glue" logic required.
The PSD301 integrates high performance
user-configurable blocks of EPROM,
SRAM, and logic in a single circuit. The
major functional blocks include a
Programmable Address Decoder (PAD),
256K bits of high speed EPROM, 16K bits
of high speed SRAM, input latches, and
output ports. The PSD301 is ideal for
applications requiring high performance,
low power, and very small form factors.
These include fixed disk control, modem,
cellular telephone, instrumentation,
computer peripherals, military and similar
applications.
The PSD301 is an optimal solution for
microcontrollers that need:
4-26
o
I/O reconstruction (microcontrollers lose
at least two I/O ports when accessing
external resources).
o
More EPROM and SRAM than the
microcontroller's internal memory.
o
Chip-select, control, or latched address
lines that are otherwise implemented
discretely.
o
An interface to shared external resources.
WAFERSCALE INTEGRATION, INC.
The PSD301 (shown in Figure 1) can
efficiently interface with, and enhance, any
8- or 16-bit microcontroller system. No
other solution provides microcontrollers
with port expansion, latched addresses, a
programmable address decoder (PAD), an
interface to shared resources, 256 kbit
EPROM, and 16 kbit SRAM on a single
chip. The PSD301 does not require glue
logic for interfacing to any 8- or 16-bit
microcontrollers.
The 8051 microcontroller family can take
full advantage of the PSD301's separate
program and address spaces. Users of the
68HCXX family of microcontrollers can
change the functionality of the control
signals and directly connect the R/W and
E signals. Users of 16-bit microcontrollers
(including the 80186, 8096, 80196, 16XXX)
can use the PSD301 in a 16-bit
configuration. Address and data buses
can be configured to be separated or
multiplexed, whichever is required by the
host processor.
The flexibility of the PSD301 I/O ports
permit interfacing to shared resources. The
user can assign the following functions to
these ports: standard I/O pins, chip select
outputs from the PAD, latched address or
multiplexed low-order address/data byte.
This enables users to design add-on
systems such as disk drives, modems,
etc., that easily interface to the host bus
(e.g., IBM PC, SCSI).
The PSD301's on-chip programmable
address decoder (PAD) enables the user
to map the I/O ports, eight segments of
EPROM (as 4K x 8, or as 2K x 16), SRAM
(as 2K x 8 or as 1K x 16), and chip select
outputs anywhere in the address space of
the microcontroller. The PAD can implement
up to 4 sum-of-product expressions based
on address inputs and control signals. This
further facilitates the interface to
microcontrollers with different boot-up
locations and I/O address mappings, e.g.,
the 8051 and 8096 microcontrollers have
the boot-up addresses in the lower half of
their memory maps; the 80186 and
68HCXX use high memory boot-up
addresses.
P50301
Figure 1.
PSD301
Architecture
ALE/AS
015-08
OCTAL
LATCH
UPPER.l LOWER
BYTE
BYTE
A1-A11
Ag~ Ifl~~}
~
. . . . . . . . . . . . . . . . . .~. .~. . . .~
2K
f~~
~
~
~.
.... 1"'""
ALEI AS
OCTAL
LATCH
~g:
A010
A011
A012
A013
~g~:
r- .....
I~
A15
A14
~1
}
~
t4!*
~
2K
~ ........;;;;EP;.,;R.;,;O;,;;M.........
~
~
~
A02
A03
A04
A 5
A06
A07
07-00
ES7
A~4
A"DD'RESS/DATA
~
2K
#L
PAD
2K
Il II
ESO
~
UPPERjLOWER
BYTE
BYTE
~
~
2K
r---""""
T~C~}.IVERS ~
2K
EPROM
PORTB
I
~ ~,~- :~
RSO
1.........11..
A~
----...
A1-A10
CSo TO Cs7
UPPER.!. LOWER
BYTE
BYTE
1K
1K
SRAM
BYTE WIDE
BUS
ISOLATION
BUFFER
,
ADO -AD71 00- 07
I
t--- PA1
t--- PA2
t--- PA3
t--- PA4
t--- PA5
t--- PA6
.... 1"'"" t--- PA7
r---...,....,:E;:,P.:.;R,;;O:::M......,..
A13
A12
A11
~ATA
~
UPPER] LOWER
BYTE
BYTE
---'L....!:"-'-!.---l
(mA13,
-
ADO-AD7
PO RTA
I"'"" ..... t-- PAD
08- 015
I
r- -
I
;::: ~R?
r-- PB2
r-- PB3
PB4
f--
L.
08-015
_ _ .....
c-PB5
r-PB6
_~PB7
CS8
PORTC
CS9
CS10 r- .....
-
---
t---PCO
t---PC1
t--PC2
....~JA16
A17
A18
..........
A16, A17, A18
OUPUTS DECODED
FROM BHEAO.
ROlE
WR/R/W
BHE/PSEN
RESET
A19/CSI
NOTES:
CONTROL AND CONFIGURATION SECTION
CONTROL BUS TO PORTS
1. RESET and CSI are not available as programmable opllons In the PAD An active RESET ensures that the PAD deselects all
of Its outputs, and a high level on CSi ensures that the PAD IS In power-down mode.
WAFERSCALE INTEGRATION, INC.
_.- - -
4-27
----------
PSD301
Figure 2.
PSD301 Port
Configurations
Figure 2 shows the PSD301's I/O port configurations.
ADs-AD 15
•
•
AD o-AD,
AL E
BHE/PSEN
•
•
•
•
RI WOR WRNpp
-A 15
110 OR Ao-A,
PA
•
ADo-AD,
•
110 or CSo-CS,
•
•
•
IE
./CSI
RESET
I--
.
A,.-A,. OR CS. -CS,o
PC
•
•
•
PSD301 configured for multiplexed
16-bit address/data bus
-A15
PA
AL E
•
BHE/PSEN
•
RI W OR WRNpp
•
RD IE
A, ./CSI
RESET
•
•
•
0 0-0,
•
•
RIW OR WR/Vpp
•
RD IE
•
A, ,/CSI
•
PB
•
0.-0, •
r-PC
-A,
•
•
PSD301 configured for nonmultiplexed 16-bit address/data bus.
A,.-A,. OR CS.-CS,o
PC
•
•
•
PA
A, ./CSI
110 or CSo-CS,
PB
•
A,.-A,. OR CS.-CS,o
PC
RESET
PSD301 configured for nonmultiplexed 8-bit address/data bus.
ADo-AD? = addresses Ao-A? multiplexed with data lines Do-D?
AD a-AD 15 = addresses Aa-A15 multiplexed with data lines Da-D 15 .
WAFERSCALE INTEGRATION, INC.
0 0-0,
-
Legend:
4-28
•
•
I--
R/W OR WRNpp
RD IE
A,.-A,. OR CS. -CS,o
110 OR CSo-CS,
PB
PSD301 configured for multiplexed
8-bit address/data bus.
BHEJPSEN
•
r--
RESET
AL E
I--
ADo-AD,
PA
BHE/PSEN
....A15
•
-A,
110 OR Ao-A,
•
•
--•
AL E
....PB
ADo-AD,
Programmable System™Device
WAFERSCALE INTEGRATION, INC.
PAC1000 Introduction
User-Configurable
Microcontroller
Overview
In 1988 WSI introduced a new concept in
programmable VLSI: the Programmable
System™ Devices (PSD). The PSD is
defined as a family of User-configurable
system level building blocks on-a-chip
enabling quick implementation of application
specific control/ers and peripherals. The
first generation PSD series includes the
MAP168, a User-Configurable Peripheral
with Memory; the SAM448, a UserConfigurable Microsequencer; and the
PAC 1000, a User-Configurable
Microcontroller.
The PAC1000 architecture is flexible and
enables the system designer to customize
the PAC1000 to optimize application
performance. The PAC1000 is composed
of three basic sections: a CPU for data
processing, a programmable instruction
control unit that determines the next
address to the microcode store through
polling condition codes or responding to
interrupts, and a host interface to
asynchronously load data from the host.
Registered inputloutputs are used to
synchronize with the system.
The PAC1000 user-configurable highperformance microcontroller is the first of
a generation of products intended for
applications in high-end embedded control
where high-speed data processing, interface
or control is needed. The PAC1000 replaces
a board full of discrete components such
as standard logic, FIFO, EPROM for
microcode store, ALU, SEQUENCER,
register files and PALJPLD/PGA. To sborten
the time-to-market for the system designer,
a high-level software development language
is used. This contrasts with the myriad
state-machine entry, schematic entry, and
place and route tools that would be
needed for a discrete design using PAL,
PLD, PGA or gate arrays.
As a result of integrating logic and EPROM
memory into the PAC1000 and defining a
high-level language for programming both,
time-to-market and board space is reduced
and reliability increased. The PAC1000 is
currently used in applications such as
Intelligent DMA controller, FOOl buffer
controller, Frame buffer controller, LAN
communications controller, disk controller,
and 1/0 controller. For further details on
the PAC1000 see Application Note 10.
4-29
I
DI
Contents
4-30
Features .......................... ,............................................................................................................. 4-31
General Description ...................................................................................................................... 4-32
Architectural Overview .................................................................................................................. 4-34
Operational Modes ........................................................................................................................ 4-36
Host Interface ................................................................................................................................ 4-37
FIFO ....................................................................................................................................... 4-37
Data 1/0 Registers .................................................................................................................. 4-39
Program Counter .................................................................................................................... 4-39
Status Register ....................................................................................................................... 4-39
Control Section ............................................................................................................................. 4-41
Parallel Operations ................................................................................................................. 4-41
Program Memory ................................................................................................................... 4-42
Security .................................................................................................................................. 4-42
15-Level Stack ....................................................................................................................... 4-42
Program Counter .................................................................................................................... 4-42
Loop Counter ......................................................................................................................... 4-43
Debug Capabilities ................................................................................................................. 4-43
Breakpoint Register ......................................................................................................... 4-43
Single Step ...................................................................................................................... 4-43
Condition Codes ..................................................................................................................... 4-43
User-Specified Conditions ............................................................................................... 4-44
CPU Flags ....................................................................................................................... 4-44
FIFO Flags ...................................................................................................................... 4-44
Stack-Full Flag ................................................................................................................ 4-44
Interrupt Flag ................................................................................................................................. 4-44
Data Register Read Flag ................................................................................................. 4-44
Counter Flag .................................................................................................................... 4-44
Case Logic ............................................................................................................................. 4-45
Case Instructions ............................................................................................................. 4-45
Priority Case Instructions ................................................................................................ 4-45
Interrupt Logic ........................................................................................................................ 4-45
Interrupt Mask Register ................................................................................................... 4-46
Output Control ........................................................................................................................ 4-47
Counters ............................................................................,.......................................................... 4-47
Address Counter .................................................................................................................... 4-47
Block Counter ......................................................................................................................... 4-48
Central Processing Unit ................................................................................................................ 4-48
Arithmetic Operations ............................................................................................................ 4-51
Logic Operations .................................................................................................................... 4-51
Shift Operations ..................................................................................................................... 4-51
Shift Right ........................................................................................................................ 4-51
Shift Left .......................................................................................................................... 4-51
Rotate Operations .................................................................................................................. 4-52
Multiple Precision Operations ................................................................................................ 4-52
1/0 and Special Functions ............................................................................................................. 4-52
Configuration Registers ................................................................................................................ 4-54
Control Register ..................................................................................................................... 4-54
1/0 Configuration Register ..................................................................................................... 4-56
Mode Register ........................................................................................................................ 4-57
State Following Reset ................................................................................................................... 4-58
Electrical and Timing Specifications ............................................................................................. 4-60
Pin Assignments ........................................................................................................................... 4-66
Instruction Set Overview ............................................................................................................... 4-70
System Development Tools .......................................................................................................... 4-75
Hardware ................................................................................................................................ 4-75
Software ................................................................................................................................. 4-75
Support ................................................................................................................................... 4-75
Training .................................................................................................................................. 4-75
Ordering Information-PAC1 000 .................................................................................................. 4-76
Ordering Information-5ystem Development Tools ..................................................................... 4-77
WAFERSCALE INTEGRATION, INC.
Programmable System™Device
PAC1000
WAFERSCALE INTEGRATION, INC.
User-Configurable
Microcontroller
Features
0
First Generation Programmable System
Device (PSD)
0
Address Generation-Up To 4 Mbytes
Address Space
0
High-Performance User-Configurable
Microcontroller-20 MHz Instruction Execution, Output Port, and Address Bus
0
High-Level Development Tools-System
Entry Language, Functional Simulator,
and Device Programmer
0
Single-Cycle Control Architecture-One
Cycle Per Instruction
0
Re-Programmable Program StoreOn-Board 1Kx64-Bit EPROM
0
16-bit CPU-Arithmetic Operations,
Logic Operations, 33 General-Purpose
Registers
0
Two Operating Modes-Host Processor
Peripheral or Stand-alone Controller
0
Security-For EPROM Program Memory
Figure 1.
PAC1000 Block
Diagram
CK
RESET
~
~
Cs
RO WR
r
I
HAD[5.0]
I
Configuration
Registers
I
HD[15:0]
I
Host Interface
t
j.
J.
Control Section
Security Bit
I
I
1S-Level
Stack
User
Output
I
tK x 64 EPROM
I
I
CPU
I
Loop Counter
BreakpOint Register
Program Counter
I
I
~
Case Logic
II Condition-Code
I Interrupt
Logic
Logic
~
Block Counter
~
I
OUTCNTL[1S:0]
CC[7:0]
INT[3.0]
1/0 & SpeCial
Function Port
f
~
1/0[7:0]
I
Address Counter
"
~
1
Address/Data
Port
f
~
I
I
-::b-
AOO[lS·0]
WAFERSCALE INTEGRATION, INC.
1738 01
4-31
II
PAC1000
General
Description
In 1988 WSI introduced a new concept in
programmable VLSI, Programmable System
Devices (PSD). The PSD family consists of
user-configurable system-level building
blocks on-a-chip, enabling quick implementation of application-specific controllers and
peripherals. The first generation PSD series
includes the MAP168, a User-Configurable
Peripheral with Memory; the SAM448, a
User-Configurable Microsequencer; and the
PAC1000, a User-Configurable Microcontroller.
up to four separate conditions and multi-way
branching in a single cycle.
The PACt 000, with its System Development
Tools, matches the development cycle and
ease of use of any standard microcontroller.
The high performance and flexibility of the
PACt 000 were previously available only to
designers who could afford the long development cycle, high cost, high power, and large
board space requirements of a building-block
solution (Le., Sequencer, Microcode Memory,
ALU, Register File, PALs, etc.)
The PAC1000 User-Configurable Microcontroller is based upon an architecture that
enables it to execute complex instructions in
a single clock cycle. Each PACt 000 instruction can perform three simultaneous operations: Program Control, CPU functions, and
Output Control, as shown in Figure 2. The
PACt 000 can also perform address generation or event counting simultaneously with instruction execution. The PACt 000 is also
capable of performing a conditional test on
Figure 2. SingleCycle Control
Architecture
The unique capabilities of PACt 000 are
easily utilized with System development
tools, which include a PACSEL C-like System
Entry Language, a PACSIM Functional
Simulator, and a MagicPro™ Device Programmer. All System Development Tools are
PC-based and will operate on an IBM-XT,
AT, PS2 or compatible machine. For more information, contact your nearest WSI sales
office or representative.
RD
CS
WR
co~~~~~ -~:--'''----c-o-ntr-''ol-u-n-it-I
Interrupts -.......,.~
HD[15 0] HAD[15'0]
28
1K x 6~iWPROM
CPU
Next Instruction
Definition
Instruction Register
ClK
~o~r;;;:;u~p~:~;u CPU Operation
Definition
20
OC[15:0]
110[7.0]
ADD[15.0]
Important Features:
• One cycle per instruction
• 20 MHz Instruction execution rate
• Every instruction executes 3 parallel operations (Control, Output. CPU)
4-32
WAFERSCALE INTEGRATION, INC.
1738 02
PACtOOO
Table 1. Pin
Description
Signal
HD[15:0)
I/O
1/0
HAD[5:0)
1/0
Description
Host Data. PAC1000 Data 1/0 Port via the Host Interface. Can also be configured to generate 16-bit address or status. Can serve as a general-purpose Data
110 Port.
Host Address. Can be configured to output the lower
six bits of the 22-bit Address Counter; can be used as a
Host Interface function address, or as a generalpurpose 16-bit port.
CS
Chip Select (active low). Used with RD and WR to
access the device via the Host Interface.
RD
Read Enable (active low). Used with CS to output Program Counter, Status Register, or Data Output Register to HD[15:0) bus lines.
WR
Write Enable (active low). Used with CS to write HD
Bus data via the Host Interface into the PAC1 000
FIFO.
II
CK
Clock.
CC[7:0)
Condition Codes. Condition-code inputs for use with
Call, Jump, and Case instructions.
INT[3:0)
Interrupts. General-purpose, positive-edge-triggered
interrupt inputs.
RESET
Asynchronous Reset (active low). Resets Input/Output
registers and counters, tri-states all 1/0, and sets the
Program Counter to O.
OUTCNTL[15:0)
0
Output Control. User-defined Output Port. May be programmed to change value every cycle.
ADD[15:0)
1/0
Address Port. Outputs data from Address Counter or
Address Output Register when configured as an
output. When configured as an input, reads data to
Address Input Register.
1/0[7:0)
1/0
Input or Output Port. Individually configurable bidirectional bus. As simple 1/0, outputs come from the 1/0
Output Register, and inputs appear in the 1/0 Input
Register. As special 1/0 functions, provides status,
handshaking, and serial 110. Alternatively, these signals
can be used to extend the OUTCNTL or ADD lines.
WAFERSCALE INTEGRATION, INC.
4-33
PAC1000
Architectural
Overview
The PAC1 000 is a user-configurable microcontroller optimized for high-performance
control systems. The primary architectural
elements, shown in Figure 3, are the Control
Section, 16-bit CPU, Host Interface, 16-bit
Address Port, 16-bit Output Control, 8-bit I/O
Port, and Configuration Registers.
The PAC1 000 can be used as a stand-alone
microcontroller or as a peripheral to a host. In
the latter case, the Host Data (HD) and Host
Address (HAD) buses, together with the CS,
RD, and WR pins allow for direct connection
to a host bus. User-defined commands to the
Control Section or data to the CPU can be
loaded through the Host Interface.
In the stand-alone mode, the Host Interface
ports can be used as additional address, data
or I/O ports using the Data Output Register
(DOR) and Data Input Register (DIR). The
ADD port can be used to generate addresses
through the Address Output Register (AOR)
or the Address Counter. A DMA channel can
be formed on the Host Interface using these
and the Block Counter (BC) register. In
addition, the ADD port can be used as a data
bus or an I/O port, depending on how the
chip is configured. Each pin in the I/O port
can be configured individually as input,
output, or special function. The special
functions allow the control of internal
PAC1000 elements (counters, I/O buffers) by
other board elements.
The 16-bit CPU is highly parallel and can
operate on operands from the 32x16-bit
4-34
WAFERSCALE INTEGRATION, INC.
register file, miscellaneous register (AOR,
AIR, DOR, DIR, Q, etc.), or constants loaded
from the internal program-store EPROM.
The internal and external operations of the
PAC1 000 are controlled by the Control
Section. The 16 Output Control (OC) lines
are general-purpose outputs. Each of them
can be changed independently every clock
cycle. They provide a very fast means to
control various processes outside the chip.
In every clock cycle, one instruction is
executed. Each instruction consists of up to
three operations in parallel:
Q
Instruction Fetch-the next instruction is
fetched from the 1Kx64 EPROM by the
Program Control.
Q
Execution-the CPU executes an instruction.
Q
Output-placed on the Output Control
(OC) lines.
Program flow can be changed through the
condition-code inputs in one clock cycle or
through the interrupt inputs after two clock
cycles. Single-cycle 16-way branches can be
done using the Case instruction, which
samples four condition codes per cycle.
Nested loops and subroutines can be carried
out with the 15-level stack and the loop
counter. The chip configuration can be
changed in any cycle by loading the Configuration Register using the Program Control
instruction portion.
PAC1000
Figure 3.
Detailed
Block Diagram
HAD
Internal
Control
Signals
Register
File +
a Register
ALU
CPU
1/0 Conflgurabon
Internal
INTR
4
INTR
Mode
Control
.£!:.15....
Configuration Registers
Reset ..
Vee
L-
16
16
16
16
?
OC
WAFERSCALE INTEGRATION, INC.
4-35
PACtOOO
Operational
Modes
The two basic modes of operation for the
PAC1000 are either as a memory-mapped
peripheral (Figure 4) or as a stand-alone
controller (Figure 5).
In the peripheral mode, the host processor
can asynchronously interface with the
PAC1000.
Figure 4.
Peripheral Mode
Address
Host Processor
Memory
Data
,-------- - - --------,
PAC1000
~:
,
,
,
CPU
Host
Interface
~:
WR
-
,
,
,
,
,
,
,
Control
--,,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Control
Data Path
Element,
High Speed
Process,
Fast Bus, Etc.
Status/Interrupts
I
• ______________________ 1
1738 04
FigureS.
Stand-alone Mode
Address
CS
RD
WR
Memory
.. ... .. .. ------_ .. _---- ..,
PAC1000
,
,
,
CPU
,
Host and
Data
Interface
Control
- - -- -
,
,
,
,
,
,
,
,
- - - - - - _ _ _ _ _ .. 1
Control
Data
Data Path
Element,
High Speed
Process,
Fast Bus, Etc.
Status/Interrupts
1738 05
4-36
WAFERSCALE INTEGRATION, INC.
PAC1000
Host Interface
The Host Interface section of the PAC1000,
shown in Figure 6, includes the Input Command/Data FIFO, Input/Output Data Registers, and the Status Register.
FIFO
When the PAC1000 serves as a peripheral to
a host, the FIFO is used to asynchronously
load commands or data into the PAC1000. In
order to write into the FIFO, CS and WR
must have low-to-high transitions. The
information written into the FIFO is specified
by the 16-bit Interface Data bus (HD) and the
6-bit Host Address bus (HAD). Since the
FIFO is used only to buffer data and commands from a host, it is inoperative when the
PAC1000 is in stand-alone mode.
Figure 6.
Host Interface
Architecture
Bit five of the HAD bus specifies whether the
input to the FIFO is command (HADS=1) or
data (HADS=O). HADS is connected to the
FICD internal Condition Code that can be
sampled by the Control Section. If a command is written, then the lower 10 bits of the
HD bus are used as the branch address for
one of the 1024 locations in the Program
Memory EPROM. At that location a user
defined command or subroutine should exist
which executes the needed operation. If the
information is data, then the lower S bits of
the HAD bus specify which CPU register is to
be loaded from the HD bus.
This method of operation allows the host to
access the PAC1 000 as a memory-mapped
peripheral.
HOIO 15]
HADI05]
Host
Interface
Decoder
16
ACL
Decoded Signals
16
6
16
DIR
DOR
Data
Input
Register
16
16
SR
Data
Output
Register
FIFO
Status
Register
.
16
8 x 16 Command
and Data
8 x 5 Register
8x1
POinter
FICO
16
5
Internal Flags
Internal Bus
To Register File
1738 06
WAFERSCALE INTEGRATION, INC.
4-37
PAC1000
Host Interface
(CDn't)
An example of FIFO usage is shown in
Figure 7. When command or data information
is available in the FIFO, the FIFO Output
Ready (FIOR) interrupt (interrupt 5) triggers.
If the FIOR interrupt is masked, then the
FIOR status may be polled under program
control. If HAD5 equals 1, the branch address location specified by MOVE is the
Program Memory Address which contains the
user specified instruction or sub-routine
which executes the command. A JUMP or
CALL FIFO control instruction performs a
jump or call to the location specified by
MOVE. If HAD5 equals 0, an RDFIFO
instruction can transfer the FIFO contents
into the register specified by HAD[4:0).
For further explanation, refer to the diagram
below. Beginning at the location specified by
MOVE, a user defined program exists which
is going to load data into CPU registers 0,1,2,
Table 2.
Host Interface
Functions
cs
RD
0
and 3 in four consecutive cycles from the
next four FIFO locations. If one of the four
FIFO locations contains a command
(FICD=1), interrupt level 7 occurs (highest
level). Loading a command into a CPU or
other data register is not allowed. If this
occurs, FIXP (FIFO exception) will be generated.
Following the execution of this routine, the
Control Section is ready for its next instruction.
The FIFO drives three internal flags which
can also be programmed to interrupt the
PAC1000. They are:
o FIIR (FIFO full) and FIXP (FIFO exception), which drive INT7.
o FIOR (FIFO output ready), which drives
INT5.
WR
HAD5
HAD[4:0]
HD[15:0]
FunctiDn
0
0
Register
Data
Write data to FIFO
0
1
X
Command
Write command to FIFO
X
Reset FIFO
X
Reset status register
Address
4-38
0
1
0
0
0
0
0
0
00100
00011
0
0
0
00010
Data
Read program counter
0
0
0
00001
Data
Read status register
0
0
0
00000
Data
Read data output register
WAFERSCALE INTEGRATION, INC.
PACtOOO
Host Interface
Data I/O Registers
(Con't)
Input and Output Data Registers are used to
communicate with the Host Data (HD) bus.
CPU Registers may be loaded directly from
the Data Input Register (DIR) without passing
through the FIFO. Similarly, the PAC1000
may be read via the Data Output Register
(DOR).
the Program Memory address bus. It can also
be used to drive external memory devices for
expansion of the Control Port.
Status Register
Program Counter
The Status Register (SR), shown in Figure 8,
monitors all internal status. Status bits can be
set only by program execution. The SR can
be read or cleared as specified in the Host
Interface Functions table.
The Program Counter may be read via the
Host Data bus. This allows a host to monitor
All SR flags are active high (1) and are
latched at the rising edge of the clock.
Figure 7.
Example
FIFO Block
Diagram and
Usage
0'
I
Write pOinter]=)
FICDto
Condition Code
Multiplexer
x
x
x
x
x
x
x
x
X
X
X
X
0
R3 Address
Data to CPU
0
R2 Address
Data to CPU
0
Rl Address
Data to CPU
0
RO Address
Data to CPU
1
X
X
I J
J
I
I
FICD
FICD
IHAD[4:0]
M
Read pOinterJ
I
IHD[15:0]
IHD[9:0]
Command to
Control Section
when FICD = "1"
MOVE
Data to CPU
when FICD = "0"
Register Address
to CPU Register
= 1 Command (actually a branch) to the Control Section
= 0 Data to CPU Register
WAFERSCALE INTEGRATION, INC.
1738 07
4-39
PACtOOO
Host Interface
(Con't)
STAT11-(DBB) Security Bit, set when
security is active:
1= Security active.
0= No security.
STAT1D-WSI Reserved.
STAT9-(FIXP) FIFO Exception, set when
the CPU receives a command or Control
Section receives data:
1= Command or data received.
0= No exception occurred.
STAT8-(FIIR) FIFO-Input Ready, set when
there is at least one vacant location in the
FIFO:
1= FIFO ready for input.
0= FIFO not ready for input.
STAT7-(CY) Carry Flag, set when a carry
(addition) or borrow (subtraction) occurs
in CPU operations:
1= Carry occurred.
0= No carry occurred.
STAT6-(Z) Zero Flag, set when the result of
a CPU operation is zero:
STAT4-(S) Sign Bit, set when the most
significant bit of the result of the previous
CPU operation is negative:
1= Result is negative.
0= Result is positive.
STAT3-(STKF) Stack Flag, set when the
•
stack is full:
1= Stack is full.
0= Stack is not full.
STAT2-(BRKPNT) Breakpoint Flag, set
when the address in the breakpoint
register is equal to the EPROM address:
1= Breakpoint occurred.
0= No breakpoint occurred.
STAT1-(8CZ) Block Counter Zero, set
when the counter decrements to all Os:
1= Block Counter reached zero.
0= Block Counter is not zero.
STATD-(ACO) Address Counter Ones, set
when the counter increments to all 1s:
1= Address Counter reached all ones.
0= Address Counter is not all ones.
1= Zero occurred.
0= No zero occurred.
STAT5-(O) Overflow Flag, set when an
overflow occurs during a two's complement operation:
1= Overflow occurred.
0= No overflow occurred.
FigureS.
Status Register
MSB
I
o
o~
LSB
I
L=
StatO
Statl
Reserved
Reserved
Stat2
Statll
Stat4
Reserved
Stat5
Stat9
StatS
StatB
Stat7
Stat3
1738 08
4-40
WAFERSCALE INTEGRATION, INC.
PAC1000
Control Section
The control section, shown in Figure 9,
consists of a number of blocks which are
concerned with the sequencing of the control
programs in the PAC1000. These are:
I.J
Case Logic
Q
Interrupt Logic
I.J
Output Control
Q
Program Memory
Each block is described in detail below.
Q
Security
Parallel Operations
Q
15-Level Stack
Q
Program Counter
Q
Loop Counter
Q
Breakpoint Register
Q
Condition Codes
The PAC1000 can perform three simultaneous operations within a single instruction
cycle, as shown in Figure 10. The ability to
fetch an instruction from the Program Memory, execute it, and output a result within 50
nsec is due to a highly parallel structure.
FigureS.
Control
Architecture
Internal Bus
16
CCiO 7] _ _ _...,8--.--t..
Internal
] Control
Signals
Inlernal CC _ _ _....,1"..3_-t-f
(from ALU)
External
Interrupts
4
----+---+-1
Internal
4
Interrupts - - - - - , r - - t - f
Program
Memory
lK x 64 EPROM
16
OCiO 15]
WAFERSCALE INTEGRATION, INC.
1738 09
4-41
PAC1000
Control Section
Program Memory
(Con't)
The Program Memory is a 1Kx64 high-speed
EPROM. This on-board-memory allows the
PAC1 000 to operate in embedded control
applications and eliminates the need for
external memory components. Using an
erasable memory allows program code to be
modified for debug and/or field upgrades.
The Program Memory is easily programmed
using the WSI MagicPro™ (Memory and
PSDTM Programmer).
Only sixteen Program Memory locations are
reserved. The rest of the 1024 locations are
available for applications.
Program memory is segmented as follows:
Thereafter, the EPROM contents cannot be
read externally. When the EPROM is erased,
the security bit is cleared.
15·Level Stack
The 15-level Stack stores the return address
following subroutine calls, interrupt service
routines and the contents of the Loop
Counter inside nested loops. When the stack
is full, the STKF condition becomes true, and
an interrupt (INT7) will occur. The interrupt
service routine will overwrite the top of the
stack.
Popping from an empty stack produces the
previous top of stack value; pushing on a full
stack overwrites the top of the stack.
Address
Function
Program Counter
OOOH
Reset pointer program
to here
000H-007H
User Defined
Initialization Routine
OOBH-OOFH
Interrupt Vector
Locations
The 1O-bit Program Counter (PC) generates
sequential addressing to the 1K word Program Memory. Upon reset the PC is loaded
with a OOOH. From this point the value of the
Program Counter is determined by program
execution or interrupts.
010H-3FFH
User-Defined
Application Programs
Upon receiving a reset, the Program Counter
is forced to address OOOH. This location may
contain a jump or call which branches to an
initialization routine. Alternatively, the first
eight locations of memory may be used as an
initialization/configuration routine.
Security
User programs may be protected by setting a
security bit during EPROM programming.
Any JUMP or Case instruction that is executed loads the Program Counter with the
destination address. CALL instructions or
interrupts cause PC + 1 to be pushed onto
the stack. The RETURN instruction loads the
Program Counter from the stack with the
value of the return address. This value may
have previously been placed on the stack by
a CALL or interrupt.
The PC can also be loaded from the Command/Data FIFO causing program execution
to commence at an address provided by the
host.
Figure 10.
Parallel
Operations
Part of Control Section
OC[O.tS]
4-42
WAFERSCALE INTEGRATION, INC.
1738 10
PAC100D
Control Section
(Con")
Loop Counter
The Loop Counter (LC) has two functions:
Breakpoint Register
The Breakpoint Register (BR) is a 10-bit
register used for real time debug of the
PAC1000 application program.
CJ
1O-bit down counter that supports the
LOOP instruction.
CJ
Branch Register that can be loaded from
the CPU Register File or Program
Memory and used as an additional
source of branching to Program Memory.
The LC can be loaded with values up to
1023. Loop initialization code places a value
in LC. Loop termination code tests the
counter for a zero value and then decrements
LC. The loop count can be a constant, or it
can be computed at execution time and
loaded into LC from the CPU. The LC
register can also be used as a CALL or
JUMP execution vector. The content of the
LC is automatically saved on (or retrieved
from) the Stack when the program enters (or
leaves) a nested loop.
A loop count will be loaded into the LC when
a FOR instruction is encountered. This count
can be a fixed value or it can be calculated
and loaded from the CPU. The ENDFOR
instruction will test the Loop Counter for a
zero value. If this condition is not met, then
the LC will be decremented by one. The
program loop will continue until the count
value equals zero. In a nested loop, the FOR
instruction will load a new value to the LC
and push the previous value to the stack.
The Breakpoint Register can be loaded from
one of two sources, either a constant value
specified in the Program Memory or a calculated value loaded from the CPU. When the
Program Memory address matches the contents of the Breakpoint Register an interrupt
(INT 6) occurs. A service routine should exist
in Program Memory which then performs the
required procedure.
Single Step
Single step is a debugging mode in which the
currently-executing program is interrupted by
interrupt 6 after the execution of every
instruction. The interrupt 6 service routine
should reside in Program Memory.
Bit 8 in the Mask Register determines
whether the PAC1000 is in a breakpoint
mode (mask-bit 8 equals 0) or in a single step
mode (mask-bit 8 equals 1).
Both breakpoint and single step use interrupt
6. The interrupt 6 service routine will typically
dump the contents of the PAC1 000 internal
registers into external SRAM devices for examination by the user.
Debug Capabilities
The PAC1000 provides breakpoint and single
step capabilities for debugging application
programs.
Condition Codes
The Condition Code (CC) logic operates on
21 individual program test conditions. Each
condition can be tested for true or not true.
The PAC1000 can also test up to four
conditions simultaneously. For this feature
refer to the section titled Case Logic.
WAFERSCALE INTEGRATION, INC.
4-43
I'AC1000
Control Section
User-Specified Conditions
(Con't)
User-Specified Conditions are treated in the
same manner as internally generated test
conditions. CCO-CC7 should be connected
directly to the corresponding PAC1000 input
pins. These signals must satisfy the required
setup time to be serviced in the next cycle.
CPU Flags
CPU flags are internally generated. They
reflect the status of the previous CPU arithmetic operation. These signals are internally
latched and are valid only for one instruction
(the instruction following their generation).
The flags for arithmetic operations are
defined as follows:
Zero (Z)-The result of the previous CPU
operation is zero (Z=1).
Carry (CY)-The result of the previous CPU
operation generated a carry (addition) or
borrow (subtraction) (CY=1).
Overflow (O)-The previous two's complement CPU operation generated an
overflow (0=1).
Sign (S)-The most significant bit of the
result of the previous CPU operation is
negative (S=1).
FIFO Flags
FIFO flags allow the user to synchronize and
monitor the operations that are performed on
the FIFO by the host or by user's program.
Upon reset the FIFO flags are cleared,
signifying an empty state. The meaning of the
flags are as follows:
FIFO Output Ready (FIOR)-There is at least
one word in the FIFO (FIOR=1).
Tab/e3.
Condition-Code
Logic
4-44
FIFO Input Ready (FIIR}-FIFO is not full
(FIIR=1). This flag can also be connected
to the host through 1/07.
FIFO Command/Data (FICD)-This flag
indicates if the contents of the FIFO is a
command or a data. This flag is generated directly from HAD5 (FICD=1 command, FICD=O data).
FIFO Exception (FIXP}-This flag indicates
that one of two events occurred: (a) FIFO
data has been read as a command, or
(b) a command has been read as data.
Stack-Full Flag
STACK FULL flag (STKF=1) indicates that
the stack is 15 levels full. This condition will
also generate an interrupt (INT7) if not
masked.
Interrupt Flag
INTERRUPT flag (INTR =1) indicates that
there is a masked interrupt pending. This flag
is cleared when the interrupt is cleared.
Data Register Read Flag
DATA REGISTER READ flag (DOR) is a
handshake flag between the host and the
PAC1000, accessible only to the PAC1 000.
The flag is reset (DOR=O) when the
PAC1000 writes into the Data Output Register. The flag is set (DOR=1) after the host
has performed a read on the Data Output
Register.
Counter Flag
Counter flags reflect the status of their
respective counters. The PAC1000 utilizes
two counters; the Address (A) counter is a
16/22-bit auto-incrementing up counter; the
Test Group
Source
Conditions and Flags
User-Specified
External
CCO-CC7
CPU
Internal
Carry (CY), Zero (Z), Overflow (0),
Sign (S)
FIFO
Internal
FIFO Command/Data (FICD), FIFO Output
Ready (FIOR), FIFO Input Ready (FIIR),
FIFO Exception (FIXP)
Counters
Internal
Address Counter Ones (ACO), Block
Counter Zero (BCZ)
Stack
Internal
Stack Full (STKF)
Interrupt
External/I nternal
Interrupt (INTR) is pending
Data register read
Internal
Data Output Register(DOR} has been read
WAFERSCALE INTEGRATION, INC.
PACtOOO
Control Section
(Can't)
Block (B) counter is an auto-decrementing
16-bit down counter. The counters' clock
input signal is the same as the PAC1000's
clock signal. Each counter can be individually
enabled or disabled. When disabled, the
output retains the last count. The counter
flags are defined as follows:
ACO-A Counter Ones, set when the A
counter has reached the value FFFFH, in
the 16-bit mode, or the value 3FFFFFH
in the 22-bit mode.
BCZ-8 Counter Zero, set when the B
counter has reached the value OOOOH.
Case Logic
THE PAC1 000 hardware implements two
basic types of Case instructions: Case and
Priority Case.
Case Instructions
Case instructions operate on anyone of four
different Case groups. Each Case group
consists of a combination of four test conditions which can be tested in a single cycle. In
that same cycle the PAC1000 will branch to
one of the addresses contained in the sixteen
memory locations following the instruction,
depending on the status of the four inputs to
the Case group being tested.
(The FIXP, ACO, STKF, FIIR, and DOR
condition codes do not fall into any of the four
Case groups.)
Priority Case Instructions
Priority Case instructions operate on the four
internal and the four external interrupt inputs.
In this mode of operation, interrupts are
treated as prioritized test conditions and the
priority encoder is used to generate a branch
to the highest priority condition. The branch
address is located in one of the nine memory
locations following the Priority Case instruction. Priorities in this mode of operation are
the same as in the Interrupt mode of operation. Once a Priority Case instruction is
executed, the occurrence of a higher priority
condition will not affect program execution
until another Priority Case instruction is
executed. For a Priority Case instruction to
be executed, MODEO of the Mask Register
must be equal to zero (MODEO=O).
Interrupt Logic
The Interrupt Logic accepts eight inputs, four
of them are generated externally and four are
dedicated for internal conditions. The four
external, user defined, inputs (INTO-INT3)
are connected to pins INTO, INT1, INT2, and
INT3. These are positive, rising-edgetriggered signals that have a maximum
latency of two cycles. Each interrupt has a
reserved area in memory that should contain
a branch to an interrupt service routine.
There are four Case Groups (sets of Case
Conditions):
Case Group 0 (CGO): CCO-CC3.
Case Group 1 (CG1): CC4-CC7.
Case Group 2 (CG2):
Z-Zero
O-Overflow
S-Sign
CY-Carry
Table 4.
Interrupt
Assignments
Case Group 3 (CG3):
INTR-Interrupt
BCZ-B Counter Zero
FIOR-FIFO output Ready
FICO-FIFO Command/Data
Interrupt
Priority
Effect
Trigger Condition
Reserved Address
INT?
Highest
Internal
FIXP+ACO+STKF+FIIR
OOFH
INT6
Internal
BRKPT
OOEH
INT5
Internal
FIOR
OODH
INT4
Internal
Software Interrupt (SWI)
OOCH
INT3
External
INT3
OOBH
INT2
External
INT2
OOAH
INT1
External
INT1
009H
External
INTO
OOSH
INTO
Lowest
WAFERSCALE INTEGRATION, INC.
4-45
PAC1000
Control Section
(Con't)
Clearing a serviced interrupt is performed
automatically. When the interrupt is serviced,
the internally generated vector is decoded to
clear the serviced interrupt. In addition, the
user can clear any pending interrupt by using
the Clear Interrupt Instruction (CLI).
When the PAC1000 is reset,the Mask Register will mask all interrupts and the Mode
Register will select the non-interrupt mode.
To select the interrupt mode the MODEO bit
(see Configuration Register section in this
document) should be set to 1 (MODEO=1).
Interrupt Mask Register
Mask8 is used to select INT6 to be either a
single-step interrupt (when Mask8=1) or a
breakpoint interrupt (when Mask8=O) .See
the section on Debug Capabilities for further
details.
The Interrupt Mask Register, shown in Figure
11, allows individual interrupts to be masked.
Setting a Mask Register bit to a 1 masks the
associated interrupt. To unmask an interrupt,
the appropriate Mask Register bit must be
reset to O.
Table 5.
Interrupt
Definitions
Interrupt
Triggered By
INT?'
FIFO Exception (FIXP)
Address Counter contains all Ones (ACO)
Stack Full (STKF)
FIFO Full (Not FIFO Input Ready, FIIR)
INT62
Breakpoint or Single Step occurrence
INT5
FIFO Output Ready (FIOR)
INT4
Always pending; triggers when unmaSked by program execution
INT3
User-defined
INT2
User-defined
INT1
User-defined
INTO
User-defined
Notes:
1. The INT? interrupt handler checks the source of the interrupt by testing the condition code.
2. See Interrupt Mask Register, Mask8.
Figure 11.
Interrupt Mask
Register
MSB
LSB
I
Mask8
Mask?
--.-J
I
I
I
L-
MaskO
Mask1
Mask6
Mask2
Mask5
Mask3
Mask4
Status After Reset
o
'738 11
4-46
WAFERSCALE INTEGRATION, INC.
PAC1000
Control Section
(Con't)
Counters
Output Control
The Output Control bus (OUTCNTL) consists
of 16 latched Output Control Signals. These
signals can be changed on a clock to clock
basis. For every Program Memory location
there is a dedicated field which specifies the
value of the Output Control bus. The
OUTCNTL Operation places this value on the
Output Control bus. The OUTCNTL Operation can be performed in parallel with any
other PAC 1000 instructions.
The PAC1000 contains a 16 or 22-bit Address Counter and a 16-bit Block Counter.
Each of these counters can change count on
a clock to clock basis or can be internally or
externally enabled or disabled on a clock to
clock basis. These counters are in addition to
the Loop and Program Counters of the
Control Section.
until the counter is loaded with a new value.
The counter will continue to count until
disabled. ACO is a condition code and a
member of a Case Group; see the Control
Section description for more details. ACO can
also generate an internal interrupt 7, if
enabled.
The OUTCNTL bus can be used to control
external events on a clock to clock basis.
In the 16-bit mode, the counter outputs (ACH)
are available through the ADD bus. The
count is gated to the ADD bus by setting the
ASEL bit (CTRL9) of the Control Register.
Address Counter
The Address Counter (AC), shown in Figure
12, is a 16- or 22-bit ascending counter that
can be loaded or read by the CPU and
enabled/disabled with the ACEN bit of the
Control Register. (This control is also available externally through the 1/01 pin; see I/O
and Special Functions). While enabled, the
counter will increment by one every rising
edge of the Clock.
The ACO flag indicates that the value of the
counter is all ones. This flag stays latched
Figure 12.
Address and
Block Counter
In the 22-bit mode, the higher 16 bits (ACH)
are available through the ADD bus and the
six low order bits (ACL) are available through
the Host Address (HAD) bus. These low
order bits are multiplexed with the host
address lines. The address lines from the
host which drives the HAD bus must be
placed in the high impedance state before the
lower 6-bits (ACL) of the Address Counter
can be read.
Inlemal Bus
AOO[O'15]
WAFERSCALE INTEGRATION, INC.
1738 12
4-47
PACtOOO
CDunters
(Con't)
Selecting the 16- or 22-bit count mode is·
performed by setting or resetting the ACS22
bit in the 1/0 Configuration Register.
The address Output Register is an alternate
source of address outputs; it is selected by
resetting the ASEL bit of the Control Register. In this mode the CPU can be used to
provide address generation and the Address
Counter can be used as an event counter.
Block Counter
The Block Counter (BC) is a 16-bit down
counter. It is enabled by the BCEN bit of the
Control Register. It is useful as a counter for
OMA transfers. The BCEN signal is (option-
Central
PrDcessing Unit
4-48
The CPU, shown in Figure 13, performs
16-bit operations in a single clock cycle. It
contains 33 general purpose registers
(RO ... R31, and Q). The Q register can be
used in conjunction with any of the RO ... R31
registers to perform double precision shift
WAFERSCALE INTEGRATION, INC.
ally) available externally through the 1/00 bit
(see 1/0 and Special Functions). While
enabled, the counter will decrement by one
every rising edge of the clock. The BCZ flag
indicates that the counter reached the zero
value. After the occurrence of an all Os
condition the Block Counter will continue
down counting until disabled. The flag is
latched and can be cleared by loading a new
value into the Block Counter. BCZ is a
condition code and a member of a Case
Group; see the Control Section description
for more details.
Both counters may be read without disabling
the count operation and loaded via the CPU.
operations. The main building blocks are the
register bank (RO ... R31), Q register, ALU,
Y -bus devices, and O-bus devices. The
register bank supplies up to two 16-bit
registers, one of which is always the destination register.
PAC1ODO
Figure 13.
CPU Block
Diagram
r---------------------------------------------,
I
I
I
I
:
I
Z Flag
I
SDATM
IN (B)
Register
Bank
(R31/RO)
CPU
I
I
I
Host
Host
ADD
Interface
Interface
Bus
Part of
1/0
Bus
I
I Control Section I
L ______ ..l
1738 13
WAFERSCALE INTEGRATION, INC.
4-49
-----~--
PAC1000
Central
Processing Unit
(Con't)
The ALU operates on up to two external
operands that are selected by its input MUX.
In every instruction, 1 of the 10 D-bus devices (AOR, SWAP, ACL, ACH, BC, FIFO,
DIR, AIR, IIR, and Program Store) or a
member of the register bank or the Q register
outputs, can be selected as an operand
source to the ALU. The possibilities are
shown in Figure 14. During ALU operations,
three options can be selected to provide the
carry-in (Cin) input: 0, 1, or the previous
latched carry-out (adequate for multiple
precision operations).
The ALU's output or a selected register can
be loaded into one of the seven V-bus
devices (lOR, AOR, LC, DOR, ACL, ACH, or
BC) every instruction cycle. This can happen
in parallel with the feedback path from the
ALU's output that is directed either to the Q
register or to the destination register of the
register bank.
Destination Only
DaR
LC
lOR
1738 14
Table 6.
CPU Operand
Mnemonics
4-50
Mnemonic
Description
ACH or ACH/ACL
16- or 22-bit Auto-incrementing Counter, or General Purpose
Registers
AIR
Address Input Register
AOR
Address Output Register
BC
Block Counter (16-bit auto-decrementing), or General Purpose
Register
Constant values in Program Storage
DIR
Data Input Register
DOR
Data Output Register
FIFO
Input Data from FIFO
IIR
1/0 Input Register
lOR
1/0 Output Register
LC
Program Loop Counter
Q
16-bit CPU Register
RO-R31
16-bit CPU Registers
SWPV
Byte Swap version of AOR
WAFERSCALE INTEGRATION, INC.
I'AC1000
Central
Processing Unit
(Con't)
CPU operations can be performed on one,
two or three operands. Each operation is performed in a single clock cycle. In two- or
three-operand instructions, one of the operands must be a CPU internal register
(RO ... R31, or a).
CPU operations are performed independently
of operations in the counters, Host Interface,
Output Control, and Program Control.
either left or right.
The CPU can perform the following shift
operations:
r:l
Single-precision, left or right, within a
general-purpose register (RO ... R31,
ora).
r:l
Double-precision, left or right, between
an RO ... R31 register and the a register.
The LSB and MSB of the general-purpose
registers are each fed by an eight-to-one
multiplexer.
Arithmetic Operations
The CPU can perform the following arithmetic operations:
r:l Addition
r:l Subtraction
The sources and destinations for shift operation are given below:
Increment
Shift Right
Zero Flag (Z)
r:l
Decrement
Carry Flag (CY)
r:l
Compare
Sign Flag (S)
r:l
Logic Operations
The CPU can perform the following logic
operations:
r:l AND
r:l OR
r:l
Invert
r:l
Exclusive OR
Binary 0 (0)
Binary 1 (1)
Least-significant bit of this register (RLSB)
Least-significant bit of the
a register (OLSB)
Serial 1/0 port (SDATM)
Exclusive NOR
Shift Operations
Single shift operations, shown in Figure 15,
can occur either to the left or to the right, with
or without the a register. Shift instructions
specify the sources that are shifted into the
corresponding registers.
r:l
All shift operations can be executed in the
same clock cycle as an arithmetic or logic operation. The arithmetic or logic operation is
executed first; the result is shifted and then
stored in the register file. The shift can be
Shift Left
Zero Flag (Z)
Carry Flag (CY)
Sign Flag (S)
Binary 0 (0)
Binary 1 (1)
Most-significant bit of this register (RMSB)
Most-significant bit of the
a register (OMSB)
Serial 1/0 port (SDATL)
Figure 15.
Shift Operations
Shift Single Precision Left/Right
Shift Double Precision Left/Right
Shift Double PreciSion Left/Right
1738 15
WAFERSCALE INTEGRATION, INC.
4-51
PACtOOO
Central
Processing Unit
(Con't)
Figure 16.
Rotate Operations
Rotate Operations
Multiple Precision Operations
The CPU can perform the following rotate operations, as shown in Figure 16:
The carry-out in each instruction can be used
in the next instruction for multiple precision
operations (e.g., ADDC). This feature enables the user to implement complex arithmetic operations such as division or multiplication in several clock cycles.
D
Single-precision, left or right, within a
general-purpose register (RO ... R31,
or 0).
D
Double-precision, left or right, between
an RO ... R31 register and the 0 register.
~"'-----Rn~
doh
Single PrecIsion Rotate RighVLeft
Double PreCision Rotate RighVLeft
1738 16
I/O and Special
Functions
4-52
The liD bus, shown in Figure 17, consists of
eight lines which can be individually programmed as inputs or outputs. These lines
can also be programmed to perform Special
Functions. The functions of these pins are
defined by the Mode Register and liD Configuration Register (see Configuration Register Section). The liD and Special Functions
map according to the table. The liD lines
must first be configured as inputs or outputs
via the liD Configuration Register; the
Special Function option can then be enabled
via the Mode Register. Individual special
WAFERSCALE INTEGRATION, INC.
function control is shown in the accompanying table.
Once a Special Function has been enabled,
the corresponding internal control function is
automatically disabled. Conversely, when a
Special Function is disabled, control of the
corresponding Internal control function is
returned to the Control Register (see Configuration Register). Because the Inputs in
the liD Register are clocked on each cycle,
the status of the special function can also be
read to the CPU.
PAC1000
Figure 17.
I/O and Special
Function Bus
MODES
FIIR
CNTl4
(ADOE)
MODE?
IOCG6
~
MUX
1/05
B
gj
'"
0
iHAOOE
CNTL3
(HADOE)
r------------I----~ '5
%
0
MODES
iii
cO
CNTL2
(HDOE)
..
::>
'"'5
Co
IIR
0
S
MODES
CK
SDATM
OMSB
ClK
SDATl
OlSB
IACEN
CNTlO
(ACEN)
MODE 3
B MUX
CNTL1
(BCEN)
CK
0
0
IBCEN
0
lOR
MODE 2
10CGO
lOWER S-BIT CPU
YBUS
1738 17
WAFERSCALE INTEGRATION, INC.
4-53
1'AC1000
Configuration
Registers
The Configuration Registers allow the user to
control and configure different operating
modes of the PAC1000. The three 10-bit
Configuration Registers are the Control
Register, 1/0 Configuration Register, and
Mode Register. Each register has an associated instruction which allows individual
register bits to be modified.
Control R,glsler
The Control Register, shown in Figure 18,
provides for internal control of key functions
within the PAC 1000 . Several of these
functions can alternatively be controlled
externally through the 1/0 bus (see 1/0 and
Special Functions). The Control Register is
modified on the falling edge of the clock.
Table 7.
uo I'lns and
Special Functions
Pin
1/07
1/06
1/05
1/04
1/03
1/02
1/01
1/00
TableS.
Special·Function
Control
4-54
Special Function
FIIR
ADOE
HADOE
HDOE
QMSB
QLSB
ACEN
BCEN
Special Function
Pin Name
FIIR
ADOE
HADOE
HDOE
1/07
QMSB
1/03
QLSB
1/02
ACEN
1/01
BCEN
1/00
1/06
1/05
1/04
WAFERSCALE INTEGRATION, INC.
Direction
output
input
input
input
bidirectional
bidirectional
input
input
Description
FIFO Input Ready. FIFO not full.
Address Output Enable
Host Address Output Enable
Host Data Output Enable
Q Register MSB
Q Register LSB
Address Counter Enable
Block Counter Enable
I/O Configuration
IOCG7=1 (output)
IOCG6=0 (input)
IOCG5=0 (input)
IOCG4=0 (input)
IOCG3=1 (output)
IOCG3=0 (input)
IOCG2=1 (output)
IOCG2=0 (input)
IOCG1=0 (input)
10CGO=0 (input)
Mode
MODE8=1
MODE7=1
MODE6=1
MODE5=1
MODE4=1
MODE4=1
MODE3 =1
MODE2 =1
PACtOOO
Configuration
Registers
(Con't)
ASEL (CTRL9)-Address Select. Selects the
source that will write to the Address bus:
1~ Address Counter.
o~
1= Output (see ASEL).
Address Output Register (AOR).
AIREN (CTRLS)-Address Input Register
Enable. Enables and disables writing to
the Address Input Register from the ADD
Port:
1~ Enable writing to Address Input
Register (AIR).
O~
1~ Output (See HDSELO and HDSEL 1).
O~
Disable writing to Data Input Register
(DIR).
HDSEL 1 (CTRL6) and HDSELO (CTRL5)Host Data Select. Select the source to be
connected to Host Data (HD) bus:
HDSEL 1 HDSELO
Selection
(CTRL6)
(CTRL5)
FIFOPeripheral
Mode
0
Input (into the FIFO).
HDOE (CTRL2)-Host Data Output Enable.
Selects Direction of Host Data (HD) bus
for next clock cycle:
1~ Enable writing to Data Input Register
(DIR).
0
Input (see AIREN).
1~ Output (driven from ACL Register).
Disable writing to Address Input
Register (AIR).
0
O~
HADOE (CTRL3)-Host Address Output
Enable. Selects direction of Host Address
(HAD) bus for next clock cycle:
O~
DIREN (CTRL7)-Data Input Register
Enable. Enables and disables writing to
the Data Input Register (DIR) from the
HD Port:
O~
ADOE (CTRL4)-Address Output Enable.
Selects direction of Address bus (ADD)
for next clock cycle:
Input (See DIREN).
BCEN (CTRL 1)-Block Counter Enable.
Enables and disables Block Counter:
1~ Enable Counting on next rising clock
edge.
O~
Disable Counting on next rising edge.
ACEN (CTRLO)-Address Counter Enable.
Enables and disables Address Counter:
1~ Enable Counting on next rising clock
edge.
O~
Disable Counting on next rising clock
edge.
Data Output
Register
0
Status
Register
Program
Counter
Figure 18.
Control Register
MSB
I
CTRL9
CTRL8
(ASEL)=.J
(AIREN)
CTRL?
(DIREN)
LSB
I
~ CTRLO
(ACEN)
CTRL 1 (BCEN)
CTRL2 (HDOE)
CTRL6 (HDSEL1)
CTRL3 (HADOE)
CTRL5 (HDSELO)
CTRL4 (ADOE)
Note: After Reset, All Bits Are Cleared to Zero.
WAFERSCALE INTEGRATION, INC.
1738 18
4-55
PAC1000
Configuration
Registers
(Con'f)
UD Configuration Register
1105 (IOCG5)-Selects direction of 1/05 pin:
The 1/0 Configuration Register, shown in
Figure 19, controls the direction of the
individual lines of the 1/0 bus as well as configuring the Address Counter. Each 1/0 pin
can be configured independently to be a
general purpose input or output, or each can
serve a special function (see 1/0 and Special
Function). The 1/0 Configuration Register is
also used to configure the Address Counter
as a 16-bit counter with a maximum count of
FFFFH or as a 22-bit counter with a maximum count of 3FFFFFH. The 110 Configuration Register is modified on the falling edge
of the clock.
ACS22 (IOCG9)-Configures Address
Counter as a 22- or 16-bit counter:
1= Output.
0= Input.
1104 (IOCG4)-Selects direction of 1/04 pin:
1= Output.
0= Input.
1/03 (IOCG3)-Selects direction of 1/03 pin:
1= Output.
0= Input.
1/02 (IOCG2)-Selects direction of 1/02 pin:
1= Output.
0= Input.
1/01 (IOCG1 )-Selects direction of 1/01 pin:
1= Output.
1= 22-bit counter.
0= Input.
0= 16-bit counter.
1/07 (IOCG7)-Selects direction of 1/07 pin:
1/00 (IOCGO)-Selects direction of 1100 pin:
1= Output.
1= Output.
0= Input.
0= Input.
1106 (IOCG6)-Selects direction of 1/06 pin:
1= Output.
0= Input.
Figure 19.
I/O Configuration
Register
MSB
IOCG9
(ACS22)
IOCG8 (Reserved)
IOCG7
IOCG6
IOCG5
I
~
LSB
I
L=
(1/07)
(1/06)
(1/05)
10CGO (1/00)
IOCG1 (1/01)
IOCG2 (1/02)
IOCG3 (1/03)
IOCG4 (1/04)
Note: After Reset, All Bits Are Cleared to Zero.
1738 19
4-56
WAFERSCALE INTEGRATION, INC.
PAC1000
Configuration
Registers
(Con't)
Mode Register
The Mode Register, shown in Figure 20,
allows the user to externally control and
monitor key elements within the PAC1000
which would (alternatively) be controlled
internally through the Control Register.
Enabling a Special Function in the Mode
Register disables the corresponding function
in the Control Register. The Special Function
input pins are shared with the general
purpose I/O pins. The direction of the appropriate pin must be set in the I/O Configuration
Register prior to programming the Mode
Register.
The Mode Register can also be used to reset
the FIFO as well as program the interrupt
controller to generate either interrupts or
Priority Test Conditions. See the discussion
on "Priority Case" in the Condition Code
section, above.
After Reset, all Mode Register bits equal
zero. The Mode Register is modified on the
falling edge of the clock.
The use of the Mode Register and I/O
Configuration register for Special Functions
is shown in the Special Function Settings
table.
FIRST (MODE9)-FIFO Reset. (If held high,
FIFO cannot receive information):
1= Initiate FIFO Reset (FIRST).
0= Complete FIFO Reset (FINRST).
FIIR (MODEB)-FIFO Input Ready:
1= 1/07 becomes output for the FIFO
Input Ready (FIIR) flag.
0= 1/07 becomes general purpose I/O
(107).
ADOE (MODE7)-Address Output Enable:
Figure 20.
Mode Register
MSB
MODES
(FIIR)
MODE7
(ADOE)
0= 1/06 becomes general purpose I/O
(106).
HADOE (MODE6)-Host Address Output
Enable:
1= 1/05 becomes input for Host Address
Output Enable (HADOE).
0= 1/05 becomes general purpose I/O
(106).
HDOE (MODE5)-Host Data Output Enable:
1= 1/04 becomes input for Host Data
bus Output Enable HDOE).
0= 1/04 becomes general purpose I/O
(104).
SIOEN (MODE4)-SeriaIIIO Enable:
1= 1/03 and 1/02 become MSB and LSB
(respectively) of the CPU's Q register
(SIO).
0= 1/03 and 1/02 become general
purpose I/O ACEN(MODE3).
ACEN (MODE3)-Address Counter Enable:
1= 1/01 becomes input for Address
Counter Enable (ACEN).
0= 1/01 becomes general purpose I/O.
BCEN (MODE2)-Block Counter Enable:
1= 1/00 becomes input for Block Counter
Enable (BCEN).
0= 1/00 becomes general purpose I/O.
Reserved (MODE1)
INTR (MODEO)-lnterruptiPriority-Case
Mode:
1= Select Interrupt mode (INTR).
0= Selects Priority Case mode (PCC).
LSB
I
MODE9 (FIRST) ~
1= 1/06 becomes input for the Address
Output Enable (AOE).
I
I
L=
MOOED (INTR)
MODE1 (Reserved)
MODE2 (BCEN)
MODE3 (ACEN)
MODE4 (SIOEN)
MODE6 (HADOE)
MODES (HDOE)
Note: After Reset, All Bits Are Cleared to Zero.
WAFERSCALE INTEGRATION, INC.
1738 20
4-57
PAC1000
State Fol/owing
Reset
Tableg.
SpeCial Function
Settings
Table 10.
Signal States
Fol/owing Reset
4-58
Whenever the PAC1000 RESET input is
driven low for at least two processor clocks,
the chip goes through reset. The next two
tables describe the PAC 1000 signal and
internal register states following reset.
Mode Sit
I/O Configuration Sit
Function
MODE8=1
IOCG7=1
FIIR flag output on 1/07
MODE7=1
IOCG6=0
ADOE provided by 1/06
MODE6=1
IOCG5=0
HADOE provided by 1/05
MODE5=1
IOCG4=0
HDOE provided by 1/04
MODE4=1
IOCG3=1
MSB of Q register output on 1/03
MODE4=1
IOCG3=0
1/03 can be shifted into MSB of Q register
or destination register
MODE4=1
IOCG2=1
LSB of Q register output on 1/02
MODE4=1
IOCG2=0
1/02 can be shifted into LSB of Q register
or destination register
MODE3=1
IOCG1=0
ACEN provided by 1/01
MODE2=1
10CGO=0
BCEN provided by 1/00
Signal
Condition
HAD[5:0]
Input
HD[15:0]
Input
10[7:0]
Input
ADD[15:0]
Input
OC[15:0]
OOOOH
WAFERSCALE INTEGRATION, INC.
----
--~--
PAC1DDD
Table 11.
Internal States
Following Reset
Component
ACH Register
ACL Register
AOR Register
AIR Register
DOR Register
DIR Register
lOR Register
IIR Register
STATUS Register
1/0 Configuration Register
CONTROL Register
Breakpoint Register
~ode
Register
PC Register (Program Counter)
MASK Register
BC Register
R31-RO Registers
Q Register
LC Register
FIFO Locations
FIFO Flags
Contents
0
0
0
0
0
0
0
0
0
0
0
0
0
0
011111111 B
FFFFH
Unknown
Unknown
Unknown
Unknown
Empty
WAFERSCALE INTEGRATION, INC.
0
4-59
PAC1000
Electrical and Timing
Specifications
Table 12.
Absolute
Maximum Ratings
Storage Temperature
-65°C to + 150°C
Voltage to any pin with respect to GND
-0.6V to +7V
Vpp with respect to GND
-0.6 V to + 14.0V
ESD Protection
>2000V
Stresses above those listed here may cause
permanent damage to the device. This is a
stress rating only and functional operation of
the device at these or any other conditions
above those 'indicated in the operational
Table 13.
Operating Range
Table 14.
DC
Characteristics
OV. O[IIII'Bting I'ange
with V,,=Vce
sections of this specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods of time may
affect device reliability.
Range
Temperature
Vee
Commercial
O"C to +70"C
+5V±5%
Industrial
-40°C to +85°C
+5V± 10%
Military
-55"C to + 125"C
+5V± 10%
Parameter
Symbol
Test Conditions
Output Low Voltage
IOL=8 mA
Output High Voltage
VOL
VOH
IOH=-4 mA
Vee Standby
Current CMOS
ISB1
note 1
65
mA
Vee Standby
Current TTL
ISB2
note 2
65
mA
Active Current (CMOS)
-Commercial
-Military
lee1
notes 1,3
80
90
mA
mA
Active Current
-Commercial
-Military
lee2
110
120
mA
mA
Max
Units
0.4
V
100
V
2.4
notes 2,3
V pp Supply Current
Ipp
Vpp=Vee
V pp Read Voltage
Vpp
notes 1,2
Vee-Q.4
Vee
IlA
V
Input Load Current
III
V 1N=5.5V
orGND
-10
10
IlA
Vour =5.5V
orGND
-10
10
IlA
Output Leakage Current
ILO
Notes:
1. CMOS inputs: GND ± 0.3V or Vee ± 0.3V.
2. TTL inputs: V1L ::; 0.8V, V1H :2: 2.0V.
3. Active current is an AC test and uses AC timing levels.
4-60
Min
WAFERSCALE INTEGRATION, INC.
PAC1000
Table 15.
AC Timing Levels
Table 16.
AC
Characteristics
Inputs:
oto 3V Reference 1.5V
Outputs:
0.4 to 2.4V
Symbol
12MHz'
Min Max
16MHz'
Min Max
20MHz2
Min Max
84
62.5
50
Clock Pulse Width High
leK
tCKH
26
24
21
Clock Pulse Width Low
leKL
26
24
21
Read Cycle Time
t RC
50
Address to Data Valid
tACC
45
35
les
tcsz
45
35
0
tpWL
20
15
tpWH
15
10
10
tSD
10
10
5
tHD
10
10
5
RESET setup
tSR
10
10
5
RESET to tristate of
ADD, HAD, HD, I/O
tRZ
25
25
20
RESET clocked to
OUTCNTLlow
tROL
30
30
25
ADDRESS TIMING
Address/Data setup
Parameter
CLOCK CYCLE
Cycle Time
HOST READ CYCLE
CS to Data Valid
CS to tristate
HOST WRITE CYCLE
Pulse width of CS and
WRLOW
Pulse width of CS and
WRHigh
Data setup to WR
Data hold to WR
40
45
0
30
35
30
30
0
!II
30
15
RESET CYCLE
tSADD
10
10
10
Address/Data hold
tHADD
8
8
5
Clocked Counter to
Address output
tCADD
43
35
30
tRADD
tADOE
43
35
30
ADOE enable to data valid
50
40
30
HADOE enable to
data valid
tHADOE
Clocked Address Register
to Address
Address output disable
tCKZ
40
50
0
25
20
30
0
WAFERSCALE INTEGRATION, INC.
16
4·61
PAC1000
Table 16.
AC
Characteristics
(Con't)
Parameter
Symbol
12MHz1
Min Max
16MHz1
Min Max
20MHz2
Min Max
DATA AND I/O TIMING
35
35
30
30
Clock to I/O Output Valid
tCKIO
Clock to HD Output
10 data hold
tCKHD
tSIO
tHIO
HD data setup
tSHD
10
10
tHHD
tHDOE
8
8
10 data setup
HD data hold
HDOE enable to data valid
Bus Output Disable
10
10
8
8
tCKZ
0
tscc
60
0
50
25
0
30
30
10
5
10
5
40
20
0
30
16
TEST AND INTERRUPT TIMING
Condition Code setup
Condition Code hold
tHCC
Clock to OUTCNTL Valid
tcov
Minimum interrupt pulse
for acceptance
tlPWA
40
0
50
0
33
25
33
15
10
10
15
0
15
0
10
0
10
0
10
0
10
0
SPECIAL FUNCTION TIMING (//0 Bus)
S015 setup
S015 hold
SOO setup
SOO hold
Clock to 00 output
Clock to 015 output
Address Counter
enable setup
tSS015
tHS015
tssoo
t HSOO
tCKOO
35
35
tCK015
tSACEN
20
15
10
tHACEN
Block Counter enable setup tSBCEN
Block Counter enable hold t HBCEN
External output enable to
data valid
tSFV
External output enable to
high impedance
tSFZ
10
20
10
5
15
5
5
10
5
Address Counter
enable hold
30
25
20
30
25
20
Notes:
1. Operating temperature range: Commercial, Industrial, Military
2. Operating temperature range: Commercial
4-62
30
30
30
30
WAFERSCALE INTEGRATION, INC.
PAC1000
Figure 21.
Clock Cycle
Timing
Figure 22.
Host Read Cycle
Timing
CK
~
=h__
Ad_d:_::_s_va_lid_ _ _
~~
_ __
tACC-
/
\
j+-tcs
-+
_tcsz .-..
/
\
I.
HD
\
Data Valid
Note: tcs is referenced from RO=D and CS=D.
1738 22
Figure 23.
Host Write FIFO
Cycle Timing
HAD
HD
1738 23
Figure 24.
Reset Cycle
Timing
CLOCK
ADD
HAD
HD
1/0
OUTCNTL
1738 24
WAFERSCALE INTEGRATION, INC.
4-63
PAC1000
Figure 25.
Data and I/O
Timing
SWItch bus from
Input to Output
(Note 1)
New Data or
Counter Output
(Note 2)
Next Data
or Count Value
Output to High
Impedance
CLOCK
1/0
Host Data
Output
HD
Notes· 1. A bus drrectlonal change (Input-to-output or output-to-input)
takes place on the failing edge of the clock
2. New data or count value is latched on the rising edge of the clock
Figure 26.
Address Timing
Switch bus from
Input to Output
(Note 2 & 3)
New Data or
Counter Output
(Note 4)
Next Data
or Count Value
1738 25
Output to High
Impedance
CLOCK
ADD
HAD
(Note 1)
Notes: 1 The Host Address (HAD) bus is used to output the lower six bits of the 22-M counter
2.A bus directional change takes place on the failing edge of the clock (Input-to-output or output-to-input)
3. Selection of the source to be output on a bus occurs on the falling edge
of the clock (I.e, counter or address register)
4. New data or count value is latched on the rising edge of the clock.
4-64
WAFERSCALE INTEGRATION, INC.
1738 26
PAC1000
Figure 27.
Test and Intellupt
Timing
CLOCK
CC[70]
OUTCNTL
INT
1'"1
----------------~
~-,IP-W-A------
Note: 1 Since condition codes are not latched,
they should be stable Isee
pnor to being tested.
1738 27
I
Figure 28.
Special Function
Timing
I
CLOCK
9
ACEN
BCEN
ao
a15
ADOE
HADOE
HOOE
ADD
HAD
HD
1738 28
WAFERSCALE INTEGRATION, INC.
4-65
PAC1000
Pin Assignments
Figure 29.
88-Pin Ceramic
P6APIn
Assignments
A
B
C
D
E
F
G
H
J
K
L
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
0
0
0
0
0
0
0
0
V05
oca
GND
OCS
OC3
OC2
OC1
1NT3
INT1
CC7
CC4
CC3
0
A
0
0
0
0
0
0
0
0
0
0
0
0
0
INTO
CC.
CCS
CC1
ceo
B
0
0
C
V07
0
CC2
V06
0
0
' '0'
1101
0
INT2
OC4 /RESET OCO
AD015 ADD14
0
0
1/02
!W9.
0
GND
0
0
0
0
0
0
0
CK
0
ADD9
0
0
0
0
ADDS AD06
0
0
ADD3 ADD4
0
OC12 OC13
0
ADDO ADD2
OC10
0
0
GND
ADD7 ADoa
PAC1000
OC1S OC14
GNO
0
ADD1l ADD10
0
0
0
ADD13 ADD12
0
/CS
0
OC.
1104
1100
iRD
OC7
Veo
0
H03
M 0
N
13
0
0
0
OCO
OC11
H02
HD4
HDB
H06
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
9
10
11
HOtO Veo
HDO
HD1
GNO
HOS
HD7
H09
H01l
1
2
3
4
5
6
7
HD14 HADC HAD1
HD12 HOt3 H01S GND
E
F
G
H
J
K
0
0
L
0
0
M
HADS Vee
0
D
HAD3 HAD4
0
0
12
13
HAD2 ADDl
N
TOP (THROUGH PACKAGE) VIEW
A
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
Voc
CC7
0
INT3
OC1
OC2
OCS
GND
Dca
A
DC'
0
0
CC'
B
C
D
E
F
G
H
J
K
L
0
CC4
0
CCO
CC1
0
0
0
CCS
0
0
1NT2
INTO
0
oeo
/RESET 004
0
OC7
0
0
0
0
0
E
0
F
1101
IlOO
0
G
GNO
0
iRD
H
0
0
J
0
0
K
0
0
L
IWA
OC13 OC12
0
OC10 GND
HAOS
0
0
0
0
0
13
12
11
ADDl HAD2 OND
0
0
0
0
Voc
HOtO
HD.
H06
HD4
HD2
OC11
OC9
0
M
0
0
0
0
0
0
0
0
N
7
6
0
HADO H014
H01S
HOt3
HD12
10
9
8
0
0
HOt 1 H09
0
0
0
HD7
HDS
GND
5
4
3
BOTTOM VIEW
WAFERSCALE INTEGRATION, INC.
D
0
OC14 OC15
0
ADD2 ACDO
Veo
0
0
ADD4 ADD3
0
11<13
0
CK
0
HD'
1/04
0
0
0
ADD6 ADDS
0
C
0
ADD8 ADD7
0
B
ICS
ADOS GND
0
0
0
1/02
ADD10 ADD11
0
1107
0
0
AOD12 ADOt3
0
0
1105
CC2
110.
HAD4 HAD3 HAD1
4·66
0
oeo
ADD14 ADD1S
M 0
N
0
cce
INTt
0
HD1
2
HOO
1
1738 29
PAC1000
Table 17.
PGAPin
Assignments
Name
Pin
Name
Pin
Name
Pin
CS
RD
RESET
WR
AD DO
ADD1
ADD10
ADD11
ADD12
ADD13
ADD14
ADD15
ADD2
ADD3
ADD4
ADD5
ADD6
ADD7
ADD8
ADD9
CCO
CC1
CC2
CC3
CC4
CC5
CC6
CC7
CK
F2
H1
B6
G1
K12
N13
E13
E12
013
012
C13
C12
K13
J12
J13
H12
H13
G12
G13
F13
813
812
82
A13
A12
811
810
A10
G2
GND
GND
GND
GND
GND
GND
HADO
HAD1
HAD2
HAD3
HAD4
HAD5
HDO
HD1
HD10
HD11
HD12
HD13
HD14
HD15
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9
H2
L1
A3
F12
N3
N11
M10
M11
N12
M12
M13
L12
N1
N2
M7
N7
N8
N9
M9
N10
M3
C1
M4
N4
M5
N5
M6
N6
1100
F1
E1
E2
01
02
A1
C2
81
89
A9
B8
A8
87
A7
L2
M2
K1
K2
J2
J1
A6
A5
85
A4
84
83
A2
M1
A11
L13
M8
1/01
1102
1/03
1/04
1/05
1/06
1/07
INTO
INT1
INT2
INT3
OCO
OC1
OC10
OC11
OC12
OC13
OC14
OC15
OC2
OC3
OC4
OC5
OC6
OC7
OC8
OC9
VCC
VCC
VCC
WAFERSCALE INTEGRATION, INC.
4-67
I'AC10D0
Figurtl30.
100-Pln Plastic lit
Ceramic QIIad
Flatpack
(SuI/wing) Pin
Assignments
13
89
I
26
76
-
64
38
39
51
63
1738 30
4-68
WAFERSCALE INTEGRATION, INC.
PAC1000
Table 18.
Plastic or
Ceramic Quad
Flatpack
(Gul/wing) Pin
Assignments
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RD
GND
GND
OC15
OC14
OC12
OC13
GND
GND
OC10
OC9
OC11
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
HD11
HD12
VCC
VCC
HD13
HD14
HD15
HADO
GND
GND
HAD1
HAD2
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
ADD7
ADD8
ADD9
GND
GND
ADD10
ADD11
ADD12
ADD13
ADD14
ADD15
CCO
CC1
CC3
CC4
CC5
VCC
VCC
CC6
CC7
INTO
INT1
INT2
INT3
OCO
76
OC1
OC2
RESET
N/C
HDO
HD1
HD2
GND
GND
HD4
HD5
HD6
HD7
HD8
HD9
HD10
N/C
HAD3
ADD1
HAD4
HAD5
VCC
VCC
AD DO
ADD2
ADD3
ADD4
ADD5
ADD6
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
N/C
OC3
OC4
OC5
OC6
GND
GND
OC7
OC8
CC2
105
107
106
HD3
104
103
102
101
CS
100
CK
WR
WAFERSCALE INTEGRATION, INC.
4-69
PACtDOD
Instruction Set
Overview
The PAC 1000 architecture can perform three
operations simultaneously in each instruction
cycle. The operations are specified in the
System Entry Language (PACSEL) using a
single statement. PACSEL instructions can
perform three operations:
Q
Program Control (PROGCNTL)
Q CPU
Output Control (OUTCNTL)
Each instruction is executed in a single cycle;
the three operations are executed in parallel.
The syntax of a PACSEL statement has a
label and three components:
Q
In some cases, the same mnemonic is used
to specify identical operations in both Macro
and Assembler level.
You may:
Q
PROGCNTL, CPU, OUTCNTL;
Q
The PROGCNTL component determines
program flow and determines the next
statement to be executed; the CPU component determines which operation is to be
performed by the CPU; the OUTCNTL
component determines the state of the
control outputs.
A comma ( , ) is used to separate the instructions and a semi-colon marks the end of a
statement. In general, each statement is
executed in a single cycle.
In PACSEL statements, the PROGCNTL,
CPU, OUTCNTL components can come in
any order or any combination of Macro or
Assembler operators. That is, you may mix
Assembler operators among Macro operators. Tables at the end of this section summarize the Macro and Assembler operators.
4-70
WAFERSCALE INTEGRATION, INC.
Specify components one at a time:
CPU;
PROGCNTL;
OUTCNTL;
Q
[label:] PROGCNTL, CPU,
OUTCNTL;
Specify all the components in the same
statement in order to perform the operations in parallel:
Use components in any combination:
PROGCNTL, CPU;
PROGCNTL, OUTCNTL;
CPU, OUTCNTL;
WSI recommends that, in general, you
maintain a consistent ordering of these
components and consistent groupings of
Assembler-level and Macro operators, e.g. in
separate files. This manual uses the
PROGCNTL, CPU, OUTCNTL ordering.
When PROGCNTL is omitted, the implied
instruction is CONTinue, that is, proceed to
the next control instruction. When CPU is
omitted, the implied instruction is NOP. When
OUTCNTL is omitted, the implied instruction
is MAINTain, that is, maintain the most
recent OUTCTL, in Assembler order.
A summary of PACSEL Assembler and
Macro statements follows.
----------
PAC1000
Table 19.
PACSEL
Assembler
Language
Summar,
Arguments
Mnemonic
The PROGCNTL Operators
Meaning
ACSIZE
<16/22>
SET A COUNTER SIZE
CALL
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:08:20 18:03:36-08:00 Modify Date : 2013:08:21 04:51:17-07:00 Metadata Date : 2013:08:21 04:51:17-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:da276db2-c11f-a343-aec0-5d60ae16c78c Instance ID : uuid:7765b376-9913-964d-bd95-312685adabd3 Page Layout : SinglePage Page Mode : UseNone Page Count : 508EXIF Metadata provided by EXIF.tools