1990_WSI_PSD_Design_and_Applications_Handbook 1990 WSI PSD Design And Applications Handbook

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Programmable System™Devices
WAFERSCALE INTEGRATION, INC.

PSO
Design and Applications Handbook

1990

~riterio~
manufacturers representative

(408) 988-6300
3350 Scott Blvd. Bldg. #44 • Santa Clara. CA 95054-3120

WAFERSCALE INTEGRATION, INC.

Programmable System™Devices
(PSD)
Design and Applications Handbook
1990

Copyright © 1990 WajerScale Integration, Inc.
(All rights reserved.)
47280 Kato Road, Fremont, California 94538
415-656-5400 Facsimile: 415-657-5916 Telex: 289255

Printed in U.S.A.

WAFERSCALE INTEGRATION, INC.

WAFERSCALE INTEGRATION, INC.

General Information

1

Section Index
General
Information

Table of Contents ......................................................... 1-1
Introduction to PSDs ....................................................... 1-3
Company Profile .......................................................... 1-5
Ordering Information ....................................................... 1-9

For additional information,
call800·TEAM·WSI (800-832-6974).
In California, call 800-562-6363.

WAFERSCALE INTEGRATION, INC.

-

rrtl .-:.::
,.,
•

-~~

••

Table of Contents

WAFERSCALE INTEGRATION, INC.

General
Information

Table of Contents ......................................................... 1-1
Introduction to PSDs ....................................................... 1-3
Company Profile .......................................................... 1-5
Ordering Information ....................................................... 1-9

PSO Product
Specifications

PSO Development
Systems

MAP168/PSD301
Introduction

User-Configurable Peripheral with Memory ................ 2-1

MAP168

User-Configurable Peripheral with Memory ................ 2-5

PSD301

User-Configurable Peripheral with Memory ............... 2-23

PAC1000 Introduction

User-Configurable Microcontroller ...................... 2-63

PAC 1000

User-Configurable Microcontroller ...................... 2-65

SAM448 Introduction

User-Configurable Microsequencer ..................... 2-113

SAM448

User-Configurable Microsequencer ..................... 2-115

MAP168 -

PSD Development Systems ....................................... 3-1

SAM448 -

PSD Development Systems ....................................... 3-5

PAC1000 -

PSD Development Systems ....................................... 3-9

WS6000 MagicPro™ Programmer and Package Adaptors ........................ 3-13

PSO Applications

Application Note 002

Introduction to the MAP168 User-Configurable
Mappable Memory Subsystem .......................... 4-1

Application Note 010

PAC1000 Introduction ................................ 4-13

Application Note 005

PAC1000 as a High-Speed Four-Channel
DMA Controller ..................................... 4-39

WAFERSCALE INTEGRATION, INC.

1-1

Table Df CDntents

PSD Applications
(Cont.)

Application Brief 006

PAC1000 as a 16 Bi-Directional Serial
Channel Controller .................................. 4-71

Application Note 008

PAC1000 User-Configurable Microcontroller with a
Built-In-Self;rest Capability ............................ 4-75

Application Note 009

In-Circuit Debugging for the PAC1000
User-Configurable Microcontroller ...................... 4-83

Application Brief 007

Hardware Interfacing'the PAC1000 as a
Micro Channel Bus Controller ......................... 4-99

Application Note 003

High-End SAM Applications Using
Microassembler Design Entry ......................... 4-105

Application Note 004

SAM Applications Using State Machine Design Entry ..... 4-127

Article Reprint

Microprogram an Embedded Controller -

Package
Information

........................................................................ 6-1

Sales
Representatives
and Distributors

........................................................................ 7-1

'-2

WAFERSCALE INTEGRATION, INC.

PAC1000 ............................. 5-1

iF===~~
--...,
.. _--r=-ii=i-i-= ==
---~ --'"

Introduction to Programmable
System™ Devices (PSD)

-

WAFERSCALE INTEGRATION, INC.

Programmable System Devices, or PSDs,
are user-configurable system level building
blocks on-a-chip enabling quick
implementation of application specific
controllers and peripherals.
WSI PSDs are ideal for designers who
require fast time-to-market, low risk,
greater system integration and lower power
consumption. PSDs enable designers to
configure their microcontrollerlperipheral to
meet exact design requirements. WSI's
PSDs are unique in that they are the only
VLSI devices available today that provides
a user-configurable off-the-shelf solution at
the system level.
The user-configurability of PSDs enables
them to be used in many different
applications, including:
Q Computers (Workstations and PCs) -

Fixed Disk Control, Modem, Imaging,
Laser Printer Control
Q Telecommunications -

Modem,
Cellular Phone, Digital PBX, Digital
Speech, FAX, Digital Signal Processing

microcontroller. It may be used as a
stand-alone microcontroller or as a
peripheral to microprocessors. It is ideal
for embedded control applications,
including graphics, local area network,
and disk drive control in both military
and commercial applications.
Q The MAP168 is a user-configurable

peripheral. It is used in DSP applications
including modems, motor control and
medical instrumentation. The MAP168
is ideal for DSP based applications
where fast time-to-market, small form
factor and low power consumption are
essential. When combined together in
an 8- or 16-bit system, virtually any
DSP chip (TMS320 series, etc.) and
the MAP168 work together to create a
very powerful 2-piece chip-set. This
combination provides essentially all of
the required control and peripheral
element of a DSP system.
Q The PSD301 is a user-configurable

Q Industrial -

Robotics, Power Line
Access, Power Line Monitor

Q Medical Instrumentation - Hearing
Aids, Monitoring Equipment, Diagnostic
Tools
Q Military -

Missile Guidance, Radar,
Sonar, Secure Communications, RF
Modems

PSDs are available in a variety of space
saving surface mount and through-hole
package configurations for commercial,
industrial, and military applications. WSI
offers windowed package options for
prototyping and low cost OTP (one-time
programmable) packages for high volume
applications. PSDs utilize WSI's proprietary
split-gate CMOS EPROM technology for
low power consumption.
There are currently four PSD family
devices in production. These include the
PAC1000, MAP168, PSD301, and SAM448.

Q The PAC1000 is a user-configurable

peripheral for microcontroller applications
including disk drives, low cost modems,
and mobile phones. The PSD301 is ideal
for microcontroller based applications
where fast time-to-market, small form
factor and low power consumption are
essential. When combined together in
an 8- or 16-bit system, virtually any
microcontroller (8051, 8096, 16000, etc.)
and the PSD301 work together to create
a very powerful 2-piece chip-set. This
implementation provides the required
control and peripheral element of a
microcontroller based system peripheral
with no external "glue" logic required.

Q The SAM448 is a user-configurable
sequencer for state machine and bus
interface applications. Its flexible 1/0
and architecture make it ideal for use
in interfacing to both existing bus
architectures (AT, VME, MCA-bus), and
evolving bus standards (EISA, NuBUS).

WAFERSCALE INTEGRATION, INC.

1·3

EI

Introduction to
Programmable System T., Devices (PSD)
Application specific features can be easily
programmed into the PSD EPROM array
for quick design implementation. Unlike
the current generation of programmable
gate arrays, which require the use of
unpredictable, and often time unavailable
routing resources, all PSD logic is fully
connected internally. This means that all
timing is predictable ahead of design
implementation, and routing is assured.
This greatly simplifies and reduces the
design implementation and simulation
process, and provides designers with a
significantly more reliable, lower risk path
to market. WSI PSDs also eliminate the
NRE, turn-around-time, and risks associated
with gate arrays and other ASIC solutions.

1-4

WAFERSCALE INTEGRATION, INC.

As product life cycles continue to shrink,
designers can win the race from idea to
marketable product with WSI PSDs. PSDs
are quickly configured and programmed by
the designer by using low cost, easy-touse WSI PC-based development tools. The
user-friendly menu-driven software includes
high level design entry, simulation and
programming packages for rapid system
development.
WSI supports its PSD product family with
an applications holline and bulletin board,
as well as highly trained, technical Field
Applications Engineers. As standard
products, WSI PSDs are available from
'WSI's franchised world-wide distribution
network.

Company Profile
WAFERSCALE INTEGRATION, INC.

Intmduction

WaferScale Integration, Inc. (WSI) designs
and produces the world's broadest and
fastest families of CMOS PROMs, RPROMs,
EPROMs, and Programmable System™
Devices (PSD). These product families
target the needs of system designers who
must reduce system development time and
deliver market competitive products in
continuously shorter periods of time. WSl's
programmable VLSI products additionally
enable higher system performance from
smaller, more compact end products due
to higher levels of system integration at
the chip level.
WSl's mission is clear - to build a great
company by serving its customers with a
portfolio of high-performance programmable
VLSI products that enable designers to
achieve faster time to market with new,
advanced electronic systems.
The company's patented self-aligned, splitgate EPROM technology forms the core of
WSI's programmable products and delivers
higher performance and greater density
than competing "stacked gate" EPROM
technologies. This core technology has
enabled WSI to be first in the Industry with
numerous breakthroughs in speed, density,
process and packaging. WSI has leveraged
this technology into the broadest family of
CMOS PROMs, RPROMs, and EPROMs
available.

Markets and
Applications

WSl's high-performance non-volatile
memory and PSO products are used by
the world's leading suppliers of highperformance electronic systems in
communications, data processing, military
and industrial markets. Customer end
products cover a broad spectrum and
typically include cellular telephones,
workstations, DSP computers, navigation
controllers, T1 multiplexers, modems,
image processors, missiles, LAN controllers,
high density disk drives and the like.

WSI's new "off the shelf" user-configurable
PSDs provide system level building blocks
on a single chip that enable quick
implementation of application specific
controllers and peripherals. They are the
first to integrate high-performance EPROM,
SRAM and logic and deliver a performance
and integration breakthrough to the
programmable products market. PSDs are
user-configurable on a PC or compatible
and can be tailored for use in a variety of
system applications. As a result, WSI has
established itself as a leading supplier of
high-performance programmable VLSI
solutions to a broad customer base that
includes some of the world's largest and
most technologically advanced electronics
companies.
Founded in 1983, WSI is headquartered in
a 66,000 square foot facility in Fremont,
California and has more than 125
employees. Through a long-term equity,
manufacturing and technology license
agreement with Sharp Corporation of
Japan, WSI produces its products in a
world-class production facility that
guarantees the highest quality at
competitive costs.

Customer applications include image
processing, digital signal processing, bus
control, LAN data and file control, real
time process control, graphics processing,
hard disk control, flight simulators, DMA
control, and others. WSI products are
ideally suited for these applications where
designers are faced with increasingly
shorter product life cycles and must
develop new, competitive high-performance
products in short periods of time.

WAFERSCALE INTEGRATION, INC.

1·5

EI

Company PronIe

Products

Memory Products
EPROMs
WSI offers the broadest line of CMOS
EPROM products available featuring
architectures ranging from 8K x 8 to
128K x 8, plus several x16 products, with
speeds ranging from 40 to 200 ns.
Commercial, industrial and MIL-STD-883CI
SMD products are available. A wide variety
of package selections are available
including plastic and hermetic, throughhole and surface mount types.

"L" Family
WSI's "t.:' family memory products are the
industry's fastest, low power JEDEC pinout
EPROMs and meet the requirements of
many mainstream system applications.
With speeds ranging from 90 to 200 ns
and architectures from 8K x 8 to 128K x 8
including several x16 products, "t.:' family
EPROMs are ideal for high-performance
personal computers and workstations.
Taking advantage of its split-gate EPROM
technology, WSI uses a conservative 1.2
micron lithography to achieve world-class
memory densities that traditionally require
lower yielding sub-micron technologies.

"F" Family
The "F" family is WSI's fastest line of
EPROMs, featuring speeds ranging from
40 to 110 ns and architectures from 8K x 8
to 32K x 8, plus several x16 products. The
high speed and word width options of the
"F" family EPROMs make them attractive
for use in high-end engineering and
scientific workstations, data communications
and other high-performance applications.

RPROMs
RPROMs provide bipolar PROM pin-out
with matching speed and CMOS low
power operation. The RPROM (ReProgrammable Read Only Memory)
product series includes architectures

1-6

WAFERSCALE INTEGRATION, INC.

ranging from 2K x 8 to 32K x 8 with
speeds ranging from 25 to 70 ns.
Commercial, industrial and MIL-STD-883CI
SMD configurations are available in a variety
of hermetic and plastic package styles.

Programmable System"" Devices (PSDs)
WSI's family of Programmable System
Devices (PSDs) represent a new class of
programmable VLSI products, achieving
unpara"eled levels of performance,
configurability and integration. Offering a
significantly higher level of integration over
programmable logic, PSDs are the first
programmable VLSI products to integrate
high-speed EPROM, SRAM and logic on a
single chip thereby providing complete
system solutions to the design engineer.
PSDs are off-the-shelf system building
elements that can be quickly configured
and programmed for a variety of system
applications thus enabling system designers
to shorten system development time.
The PSD is a new solution for system
designers who build high-end systems
around embedded controllers and
advanced microprocessors. The,se new
systems require faster, more highly
integrated and lower cost VLSI solutions
as we" as rapid design cycles. WSI's new
PSD family meets this demanding set of
needs.
The initial members of WSI's PSD family
includes:
I;J The PAC1000 User-Configurable

Microcontro"er
I;J The MAP168 User-Configurable

Peripheral with Memory
I;J The PSD301 User-Configurable

Peripheral with Memory
I;J The SAM448 User-Configurable

Microsequencer

- - - ----

--- --

-----

Company PlOfile

Products
(Cont.)

Design Tools and Support

Custom Circuits

WSl's development tools minimize the time
required for designers to program PSDs
for use in a variety of system applications.
PSDs are supported with complete easyto-use program development, simulation
and programming software, the PC hosted
MagicPro™ Memory and PSD Programmer,
a dial-in applications bulletin board and
WSl's team of factory and field
applications engineers. As a result, WSI
customers achieve their goal of shorter
system development time and reach new
markets sooner.

To serve the needs of its customers with
unique requirements, WSI offers its custom
circuit capability using its cell based library
of EPROM, static RAM and logic functions.
Standard products described in this catalog
can usually be modified on a custom basis
to serve particular requirements. New
customer defined custom products that
incorporate high-performance non-volatile
memory, SRAM and logic can be
produced that deliver significant speed or
system integration advantages. Contact
your local WSI sales office for additional
information.

Manufacturing

A key ingredient for success in leadingedge semiconductors is a world-class
fabrication facility that ensures high
volume capacity and prompt delivery of
highly reliable and high yielding VLSI
circuits. To this end, WSI has licensed its
proprietary CMOS EPROM and logic
process technology to Sharp Corporation
of Osaka, Japan. This long term alliance

ensures high quality, high-volume
production, competitive costs and fast
delivery. The Sharp facility in Fukuyama,
Japan employs the most advanced submicron VLSI integrated circuit manufacturing
equipment available including ion
implantation, reactive ion etch, and wafer
stepper lithographic systems.

Quality and
Reliability

WSI is deeply committed to product
excellence. This begins with proper
management attitude and direction and
with this focus, the Quality and Reliability
Program is able to operate efficiently. As a
result, product quality becomes part of
each employee's responsibility.
Quality and Reliability begin with the
proper product and process designs and is
supported by material and process controls.
Examples are products manufactured on
an epitaxial silicon layer to reduce latch-up
sensitivity, all pins are designed to
withstand >2,000 volts ESDS, numerous
ground taps are used which increases
product noise immunity, metal traces are
designed to carry a current density of
>2.0 x 105 ampslcm 2 , top passivation
extends over into the scribe lane to seal
the die edges, data retention is performed
100% on re-programmable products (TA =
+225°C, T = 72 hours), automated die
attach and bonding is used extensively,
wafers are fabricated in a Class 10 clean
room, raw materials, chemicals and gases

are inspected before use, and statistical
controls are used to keep the process on
course.
Product and process introductions or
changes are routinely evaluated for
worthiness. Life tests are conducted at
higher than typical stress levels (TA =
+150°C, Vcc = +6.5V) and even at these
stress levels, WSI products have
demonstrated low failure rates (see the
Quality and Reliability section in the
WSI 1990 databook).
WSI is active in Military programs and its
Quality and Reliability System supports
Compliant Non-Jan products. WSI also
supports DESC's (Defense Electronics
Supply Center) Standardized Military
Drawings (SMD) program. As of October,
1989, WSI has eighteen products on SMDs
with additional products pending. Several
additional products not on SMDs are
available per MIL-STD-883C. See Section
7 (Military Products) in the WSI 1990
databook.

WAFERSCALE INTEGRATION, INC.

1·7

II

Company Profile

Sales Network

1-8

WSI's international sales network includes
regional sales managers, field applications
engineers, manufacturers representatives

and many of the leading component
distributors in the United States, Europe
and Asia. See Section 7.

United States

International

Direct sales and field applications
engineering offices in Boston, Chicago,
Huntsville, Philadelphia, Los Angeles areas
and Fremont, CA; more than 25
manufacturers' representatives for major
national accounts; national distributors
including Schweber Electronics, Time
Electronics and Wyle Laboratories; and
regional distributors.

Distributors in West Germany, England,
France, Italy, Sweden, Finland, Denmark,
Norway, Spain, Belgium, Luxembourg, the
Netherlands, and Israel. Distributors for
the Asia/Pacific Rim region in Japan,
Korea, Taiwan, Hong Kong and Australia.

WAFERSCALE INTEGRATION, INC.

Ordering Information
WAFERSCALE INTEGRATION, INC.

High-Performance CMOS Products

---.--

WS57C-----

-35

B

D

L

Basic Part Number

Manufacturing Process:

II

(Blank) = WSI Standard Manufacturing Flow
B

= MIL-STD-883C Manufacturing Flow

Operating Temperature Range:
(Blank) = Commercial: 0° to +70°C
Vee: +5V ± 5%

= Industrial:
Vee: +5V
M

-40° to +85°C
± 10%

= Military: -55° to + 125°C
Vee: +5V ± 10%

Package:

Window

A
B
C
D
F
G
H

No
No

J
K
L
N
P
Q
R
S
T
W
X
Y

Z

= PPGA Plastic Pin Grid Array
= 0.900" Size Brazed Ceramic DIP
= CLLCC Ceramic Leadless Chip Carrier
= 0.600" CERDIP
= Ceramic Flatpack
= CPGA Ceramic Pin Grid Array
= Ceramic Flatpack
= Plastic Leaded Chip Carrier
= 0.300" Thin CERDIP
= CLDCC Ceramic Leaded Chip Carrier
= CLDCC Ceramic Leaded Chip Carrier
= 0.600" Plastic DIP
= Plastic Quad Flatpack
= Ceramic Side Brazed
= 0.300" Thin Plastic DIP
= 0.300" Thin CERDIP
= Waffle Packed Dice
= Ceramic Pin Grid Array
= 0.600" CERDIP
= CLLCC

Yes'
Yes
Yes'

No
No'
No'
No
Yes'

No'
No
No'
Yes

No
Yes
Yes

No
No

Speed:
-35 '" 35 ns
-55 = 55 ns
-70 = 70 ns
Etc.
• Surface Mount

WAFERSCALE INTEGRATION, INC.

1·9

1·10

WAFERSCALE INTEGRATION, INC.

WAFERSCALE INTEGRATION, INC.

PSIJ Product Specificatio.1

2

·····6

Section Index
PSO Product
Specifications

MAP168/PSD301
Introduction

User-Configurable Peripheral with Memory ................ 2-1

MAP168

User-Configurable Peripheral with Memory ................ 2-5

PSD301

User-Configurable Peripheral with Memory ............... 2-23

PAC1000 Introduction

User-Configurable Microcontrolier ...................... 2-63

PAC 1000

User-Configurable Microcontrolier ...................... 2-65

SAM448 Introduction

User-Configurable Microsequencer ................ _.... 2-113

SAM448

User-Configurable Microsequencer ..................... 2-115

For additIDna/lnformatiDn,
call BOO·TEAM·WS/ (BOO·B32·6974).
/n callfDmla, call BOO·562·6363.

WAFERSCALE INTEGRATION, INC.

Programmable System""Device
WAFERSCALE INTEGRATION, INC.

Overview

MAPI681PSD301Introductlon

User-ConHgurable
Peripheral with Memory

In 1988 WSI introduced a new concept in
programmable VLSI: the Programmable
System™ Device (PSD). The PSD is
defined as a family of User-configurable
system level building blocks on-a-chip
enabling quick implementation of application
specific controllers and peripherals. The
first generation PSD series includes the
MAP168, a User-Configurable Peripheral
with Memory; the SAM448, a UserConfigurable Microsequencer; and the
PAC1000, a User-Configurable
Microcontroller.
The MAP168 is a high-performance, userconfigurable peripheral with memory. It is
used in DSP applications including
modems, motor control and medical
instrumentation. The MAP168 is ideal for
DSP based applications where fast time-tomarket, small form factor and low power
consumption are essential. When combined
together in an 8- or 16-bit system, virtually
any DSP chip (TMS320 series, etc.) and
the MAP168 work together to create a
very powerful 2-piece chip-set. This
implementation provides the core of the
required control and peripheral elements
of a DSP system.

Architecture

The MAP168 and PSD301 products
incorporate the flexibility of using discrete
memory addressing and decoding. With
the support of WSI's user friendly PSD
software called MAPLE, designers may
configure their MAP1681PSD301 subsystems
for 8 or 16 bit data paths. If the host
system uses an 8051 microcontroller, the
MAP168/PSD301 can be programmed with
an eight bit data path. A sixteen bit data
path can be programmed for
microcontrollers like Intel's 80196. The
depth of the memory organization will be
modified accordingly to accept the different
data path widths. The low cost MAPLE
software package will handle the data path
width adjustment automatically. The user
can select either 16K bytes of EPROM and
4K bytes of SRAM or 8K words of EPROM

The MAP168 contains three elements
normally associated with discrete solutions
to system memory requirements. It
incorporates EPROM and SRAM plus a
Programmable Address Decoder (PAD), all
on the same die. The MAP168 is ideal for
the systems deSigner who wishes to
reduce the board space of his final design.
By using the MAP168 in a system, five or
six EPROM, SRAM and decode logic
chips may be reduced into a Single 44 pin
PLDCC, CLDCC or PGA package.
The second generation PSD301 is a userconfigurable peripheral for microcontroller
applications including disk drives, low cost
modems, and mobile phones. The PSD301
is ideal for microcontroller based
applications where fast time-to-market,
small form factor and low power
consumption
are essential.
When
combined together in an 8- or 16-bit
system, virtually any microcontroller (8051,
8096, 16000, etc.) and the PSD301 work
together to create a very powerful 2-piece
chip-set. Together, this implementation
provides all the required control and
peripheral elements of a microcontroller
based system peripheral with no external
"glue" logic required.
and 2K words of SRAM. The flexibility of
the MAP168/PSD301 products enables two
devices to be cascaded in width. It is
possible to double the memory size of a
sixteen bit system by using two MAP168
products in parallel but programmed in a
byte-wide configuration. For example, with
two MAP168 devices, 16K words of EPROM
and 4K words of SRAM may be organized
as upper and lower data bytes of a 16 bit
word. Alternately, two MAP168 chips may
expand the system memory vertically as
two word organized memory devices. A
block diagram of the MAP168 is shown in
Figure 1.
An important feature of the MAP168/PSD301
products is their ability to incorporate the
memory address decoding on-chip. One

WAFERSCALE INTEGRATION, INC.

2·1

MAl't6B/l'SD30t Intmluctlon

Architecture
(Cont.) .

MAP168 memory peripheral can reside
with other MAP16S devices in the same
memory addressing scheme, with the onchip decoder allocating the memory blocks
to different non-conflicting segments of the
entire memory area. The decoding function
is achieved by an on-chip feature called a
Programmable Address Decoder (PAD),
which is similar to a Single fuse array
programmable logic device supporting one
product term (AND gate) per output in the
MAP16S and four product terms per output
in the PSD30l.

memory devices. The chip select lines
may be subdivided into ESO-ES7, active
low internal EPROM chip selects, and two
internal RAM chip selects RSO and RS1.
In byte-wide applications, eight chip select
outputs drive external pins CSO-CS7.
These can be used as external chip
selects for other MAP168 devices or
system memory. These outputs are
not available for word-wide MAP168
configurations because the CSO-CS7 output
pins carry the higher order data byte. Only
FCSO is available for external chip selection.

In the MAP16S, eighteen standard chip
select outputs from the PAD are available
with one fast chip select output generally
used to select other external high speed

Figure 1 shows the organization of the
EPROM and SRAM in relation to the PAD,
for the MAP168 device.

Rgure ,.
MAPI68 Memory
Architecture

EPROM
2Kx80R1Kx16
EPROM
2K x 8 OR 1K x 16

EPROM
2Kx80R1Kx16
ADDRESS BUS
EPROM
2K x 8 OR 1K x 16
PAD

EPROM
2K x 8 OR 1K x 16

ESO
ES1

EPROM
2K x 8 OR 1K x 16

ES2
ES3t----'
ES4 t - - - . . . .

EPROM

ESS I------J rt--t...:2:K~X~8~0:R~1~K~X~16~
ES61----....I

WEN ••

EPROM
ES7 r-----T-~~2K~X~8~O~R~lK~X~1~6
CSO[O:7]

CSO[O:7]

1------+---------+-+-1

OR

eso

RSOI------.
RS11-----,

FCSO

HIGH
DATA
BYTE

EPROM
2K x 8 OR 1K x 16

[0:7]

EPROM
2K x 8 OR 1K x 16

Important Features:
•
•
•
•

2·2

40 ns EPROM/SRAM Access Time.
Byte or Word Operation, Mappable into 1M Word or 2M Byte Address Space
22 ns Chip-Select S Outputs, 17 ns Fast Chip Select Output.
128K EPROM Bits, 32K SRAM Bits, On-Chip Programmable Decoder, Security Bit.

WAFERSCALE INTEGRATION, INC.

MA"6BlPSD3D1 IntroductlDn

Figure 2.

PSD301 family

Architecture

...

Vee
GND
RD
WRNpp
BHEIPSEN
RESET
A,g1CSI
AD.-AD,.

I

CONFIGURATION
REGISTERS

I

AD o-APr

8 BLOCKS OF
EPROM

r-+
CONTROL

r-B
LATCH

A.-A,.

11

"-r

+

I

PORTA
Do-D7/ADo-AD7

CSRAM

~

D.-D,.

I-

16K BIT SRAM

fJ

PORTC
Pc....

SEE
TABLE

MUX OR NON·MUX
CONTROL"

By 8 ConfiguratiDn
I'DrtA
I'DrtB

MUX Address Data

P~7

SEE
TABLE

.: 2K x 8 OR lK x 16

Do-D7/ADo-AD7

Non·MUX Address Oata5

PB0-7

SEE
TABLE

D.-D,.

-

~

4

CSO-CS7

PAD

LATCH Ao-A7 ..
A

~

PORTB

CSEPROM

r-:----+

G3
ALE

128K1256K1512K EPROM'

By 16 ConfiguratlDn
I'DrtA
I'DrtB

0 0-0 7

CSO-CS7 or
PBo-PB7

0 0-074

Oa- 0 15

Ao-A74
PAo-PA7
AO o-A07

CSO-CS74
PBo-PB 7

Ao-A74
PAo-PA7
AOo-A07

CS O-CS 7
PB o-PB7

I'DrtC
CSa -CS lOS
A ls-A la

NOTES:
1. Three MAP300 EPROM densities.
2. Internal signal can be set during programming.
3. Latch B can be set to be transparent (not dependent on ALE).
4. Each 110 pin can be indiVidually set to perform one of the two functions.
5. The non·MUX configuration is compatible to MAP168 pinout.
6. Port C is independent of any configuration and can be chip select out or address in.

Software Support

The object code generated for the support
microprocessor/microcontroller is generated
by an assembler. This code, when
generated as an Intel MCS file, may be
easily programmed into the EPROM
section of the MAP168/PS0301 device
because the MAPLE software has been
designed to accept this standard format.
The programmable address decoder is
used to define the mapping of the various

EPROM and SRAM memory blocks. This
mapping is achieved by the designer in
the MAPLE environment. The software
provides a safeguard that prevents the
designer from inadvertently overlapping
the address selection. After selecting the
memory block assignments, the
MAP1681PS0301 device may be
programmed by the WSI MagicPro™
memory and PSO programmer.

WAFERSCALE INTEGRATION, INC.

2-3

2-4

WAFERSCALE INTEGRATION, INC.

Programmable System™Device
WAFERSCALE INTEGRATION, INC.

Features

0

0

0

0

General
Description

MAP168
User-Configurable
Peripheral with Memory

First-generation Programmable System
Device (PSD)
User-Configurable Peripheral with
Memory
16Kx8 EPROM
4Kx8SRAM
Programmable address decoder
Byte or Word Memory Configurations
16Kx8 or 8Kx16 EPROM
4Kx8 or 2Kx16 SRAM
2Mbyte or 1 Mword address range

0

0

0

High-Speed Operation
40-nsec memory access
17-nsec fast chip select output
External Chip Select Outputs
8 external chip selects
1 fast chip-select output

In 1988 WSI introduced a new concept in
programmable VLSI, Programmable System
Devices (PSD). The PSD family consists of
user-configurable system-level building
blocks on-a-chip, enabling quick implementation of application-specific controllers and
peripherals. The first generation PSD series
includes the MAP168 User-Configurable
Peripheral with Memory; the SAM448, a
User-Configurable Microsequencer; and the
PAC1000, a User-Configurable Microcontroller.
The MAP168 is the first of WSl's Programmable System Devices (PSD) product line.
The device integrates high performance,
user-configurable blocks of EPROM, SRAM,
and logic in a single circuit. The major
functional blocks include a Programmable
Address Decoder (PAD), 16K bytes of high
speed EPROM, and 4K bytes of high speed
SRAM. A block diagram is given in Figure 1.
The MAP168 device is a complete memory
subsystem that can be mapped anywhere in
a 2M-byte address space of a microprocessor or microcontroller system. The EPROM
and SRAM memory blocks can be userconfigured in either byte-wide or word-wide
organizations. The MAP168 device signifi-

Programmable Security
Protects memory map
Protects program code
Programming Support Tools
PSD integrated software environment
PC-XT/AT/PS2 platform support
MAPLE location entry Software
MAPPRO device programming Software
MagicPro device programmer (PC-XT,
AT)
Military and Commercial Specifications
44-pin Ceramic Leaded Chip Carrier
package
44-pin Plastic Leaded Chip Carrier
package
44-pad Ceramic Leadless Chip Carrier
package
44-pin Ceramic Pin Grid Array package

cantly reduces the board space and power
necessary to implement memory subsystems, increases system performance, and
provides for secure data or program storage.
The device's high level of integration and
flexibility make it ideal for high-speed microprocessors, microcontrollers, and Digital
Signal Processors like the TMS320XX family.
The EPROM can be configured either as
16Kx8 or 8Kx16. The SRAM can be configured either as 4Kx8 or 2Kx16. Individual
memory blocks of 2Kx8 or 1Kx16 can be
selectively mapped anywhere in the address
space. Since the Chip Select Input (CSI) can
be programmed as A20, the highest-order
address bit, the device's address range can
extend from 1M byte with CSI to 2M byte
withoutCSI.
For 16-bit microprocessors capable of byte
operations, the MAP168 device provides a
Byte High Enable input for accessing bytes
on any address boundary.
Pinout is compatible with the JEDEC
WS27C257 256K high-speed EPROM. This
pinout provides for memory expansion with
future WSI EPROM and PSD products.
The device's PAD and EPROM memory are

WAFERSCALE INTEGRATION, INC.

2·5

fJ

MAP168

Figure 1.
Block Diagram

MAP168
DECODED EPROM
ADDRESS"

-

~ AO-A12

AO-A12

-----,/

EPROM

8Kx 8

PGMH

----.

PGM

"EOEH

OE

AO-A19

OUTo-7

r

IN0-7

EPROM

8Kx8
PGM
OE

OUT0-7

IN0-7

L

PGMl
EOEl

i---

-

r-----

-

DECODED SRAM
ADDRES~

~

AO-A12

v

PAD

-----,/

SRAM

~

WE

r

OE

ROEH
OE

Ei\.!>pOE SI/A 20 FCSO -

OUTo-7

WEl
ROEl

r---r---r----

CON

-

SRAM

2Kx 8

WE

BHE

AO-A12

2Kx 8

WEH

IN 0-7

-

I-

-

I--

~S-

CS0-7~~

OUT0-7

IN0-7

OEl

I-OEH

f---

2:1
MUX

2:1

~

MUX

-

----

-

-

III

1\

'Ii

IV

lr-,

t--t---y-,

~

4-

L-

1/08-15 OR CS00-7

2·6

WAFERSCALE INTEGRATION, INC.

1737 01

MAP168

General
Description
(Con't)

Functional
Description

Table 1.
Pin Description

programmed using the same WSI MagicPro
programmer used to program other WSI
devices. Two software packages, MAPLE
Location Entry and MAP PRO Device Programming Software are available in the
menu-driven WISPER software environment
on an IBM® PC XT/AT or 100% compatible
platform.

For additional information on the MAP168
device, refer to Application Note No. 002,
Introduction to the MAP168 User-Configurable Peripheral with Memory. For additional
information on development and programming software for the MAP168 device, refer
to the MAP168 User-Configurable Peripheral
with Memory Software User's Manual.

The user-configurable architecture of the
MAP168 consists of an EPROM memory
block, an SRAM memory block, and a fast
Programmable Address Decoder (PAD) that
can be configured to select 2K-by1e memory
blocks anywhere in a 2M-byte address

range. The device can be programmed to
operate with memory configured either in a
by1e or word organization (by1es can be
addressed in word mode). A programmable
security bit prevents access to the PAD
address-decode configuration table.

Signal
A0-19
FCSO

I/O

Description
Address Lines. For access to EPROM or SRAM.

°

Fast Chip-Select Output (active low). Used by the Programmable Address Decoder (PAD).

BHE

Byte High Enable (active low). Selects the high-order
byte when writing to SRAM.

WElVpp

Write Enable (active low) or Programming Voltage. In
normal mode, this pin causes data on the 110 pins to be
written into SRAM. In programming mode, the pin
supplies the programming voltage, Vpp.

OE

Output Enable (active low). Enable the 110 pins to drive
the external bus.

CSI/A20

Chip Select Input (active low) or High-Order Address.
This pin can be programmed as the bus-access chip
select or as an additional high-order address bit (A20 )·

1/°0-7
I/Os_1s. CS°0-7

11O

Low-Order Byte of EPROM or SRAM.

11O

High-Order Byte or Chip-Select Outputs. In word mode,
these pins serve as the high-order byte (1108-15) of
EPROM or SRAM. In byte mode, the bits serve as ChipSelect Out signals (CS00-7) for the Programmable
Address Decoder (PAD).

WAFERSCALE INTEGRATION, INC.

2·7

MAP168

Programmable
Address Decoder

The MAP168 device has a minimum of 20
address inputs Ao-A'9 allowing the EPROM
and SRAM memory blocks to reside anywhere in a 1M-byte address space. If the
CSI/A20 input is user-configured as an address line, the maximum addressable space
increases to 2M bytes, as shown in the
Configurations table.
The 16K bytes of EPROM and 4K bytes of
SRAM, can be configured into eight independent 2K-byte blocks and two 2K-byte
blocks respectively, as shown in the Memory
Architecture figure. The PAD is a userconfigurable address decoder that compares
input addresses to the 2K-byte address
range selected for each of the eight EPROM
blocks and two SRAM blocks. When the
input address Ao-A20 is detected to be within
one of the EPROM or SRAM address
ranges, the PAD enables an internal chip
select (ES o-ES 7 or RSo-RS,) to the selected
block. If no block is selected, both the
EPROM and SRAM memories remain in a
power-down mode and the outputs are
disabled allowing other devices to drive the

Memory
Subsystem
EPROM Memory

The memory configuration of the MAP168
device includes 128K bits of WSI's patented
high-speed, split-gate, UV-erasable EPROM.
The EPROM is configured in byte mode as
16Kx8 and in word mode as 8Kx16. The
memory is organized as eight 2Kx8 or 1Kx16
blocks, as shown in the Block Diagram
figure. Each block has a separate and
independent address range that cannot
overlap. Each block is individually selected
by one of the ESo-ES 7 internal chip selects
generated by the PAD when an input address is detected within its designated
address range, as shown in the Memory
Architecture figure. If not selected, each
block of EPROM remains in a power-down
mode.
For programming, the EPROM memory
requires the WENpp input to maintain the
programming voltage V pp'

2-8

WAFERSCALE INTEGRATION, INC.

data bus. The SRAM retains its data in the
power-down mode. The 2K-byte address
ranges for any of the eight EPROM or two
SRAM blocks may not overlap.
The PAD can also be user-configured to
generate up to eight external chip selects,
CSo-CSr These outputs can be used to
decode the input address lines Ao-A20 and to
select other devices in the system. The
outputs CS O-CS 7 are available on the eight
higher-order 110.-1/0'5 lines but only when
the MAP168 device is configured in the byte
mode; the lines are not available as chipselect outputs when the device is configured
in the word mode.
The CSIIA 20 input is user-configurable as the
most-significant address line or as an activelow chip enable. Its function is programmed
as part of the PAD programming cycle.
The PAD also provides FSCO, a single, fast
chip-select output configurable by the user for
any address. It can overlap with any of the
internal EPROM, SRAM or external CSO
addresses.

SRAMMemory
The device also includes 32K bits of highspeed SRAM. The SRAM is configured in
byte mode as 4Kx8 and in word mode as
2Kx16. The memory is organized as two
2Kx8 or one 2Kx16 block(s), each with a
separate and independent address range that
cannot overlap. Each SRAM block is individually selected by one of the RSo-RS" shown
in the Memory Architecture figure, when an
input address is detected by the PAD within
its designated address range. When not
selected, each of the SRAM memory blocks
remains in a power down mode but does
retain all data stored.
Data can be written into the SRAM only when
the WENpp input is active low.

MAI'168

Memory
Subsystem
EPROM Memo,y
(Con")

Mode Selection

PAD available on the eight high-order input/
output lines 1/08-I/O,~d enabled onto the
output bus when the DE input is low.

'ytll/Wotd Mode
The PAD can be programmed to configure
the MAP168 device for either a byte or word
memory architecture. This allows the device
to be used conveniently with either 8-bit or
16-bit microcontrollers, microprocessors or
digital signal processor (DSP) systems. See
the Configurations table.
In byte mode, the EPROM is organized as
16Kx8 and the SRAM as 4Kx8. The outputs
of both are tied to the eight low-order input/
output lines 1/00-1/07 and enabled onto the
output bus when the DE input is low.
Only when configured in byte mode are the
eight external chip selects provided by the

In word mode, the EPROM is organized as
8Kx16 and the SRAM as 2Kx16. The outputs
of both are tied to the 16 input/output lines
1/00-1/0'5 and enabled onto the bus when DE
is low.
In word mode, the BHE input along with
address input AO allows the eight bits of any
16-bit word on an even or odd boundary to
be selected as shown in the High-Low Byte
Selection table. This is a useful feature for
16-bit processors that are not restricted to
reading or writing memory only on even-word
address boundaries.

The device's operational mode is controlled
by three inputs, CST, DE, and WENpp. There

Table 2.
Configurations

are ten separate modes of operation, all of
which are shown the Mode Selection table.

xl Configuration
A2I/
1M bytes
2M bytes

"CfI

2K bytes

2K bytes

1K words

1K

512

1024

512

1024

8
2
9
16Kx8
4Kx8

8
2

8
2

8
2

16Kx8
4Kx8

8Kx16

8Kx16

8
yes
yes
yes

8
no
yes
yes

2Kx16
16
yes
yes

2Kx16
16
no
yes

yes

yes

"CfI
Address Space
words
Block Size
words
Addressable Blocks
EPROM Blocks
SRAM Blocks
Chip-Select Outputs
EPROM Configuration
SRAM Configuration
liD Pins
Low-power Standby
Protected Mode
Byte Operations

x16 Configuration
A2I/
512K words 1M

9

WAFERSCALE INTEGRATION, INC.

2-9

MAP16B

Table 3.
Mode Selection

Mode/Pin

CSl7fE WE/Vpp Address

Read EPROM/SRAM

VIL

VIL

VIH

EPROM/SRAM
Selected

DOUT

Read External

VIL

VIL

VIH

EPROM/SRAM
Not Selected

High Z

CSOUT

Output Disable

X

X
X

X
X

High Z

CS OUT

HighZ

CS OUT

SRAM Selected

DIN

CS OUT

No SRAM
Selected

X

CS OUT

x16 (FCSlJ)
xBFCf/J, CSlJo-7
CSOUT

Write SRAM

VIH
VIH X
VIL X

Write External

VIL

X

VIL
VIL

Program EPROM

VIL

VIH

Vpp

EPROM
Program Address

DIN

DIN

Program Verify
EPROM

VIL

VIL

VIH

EPROM
Program Address

DOUT

CSOUT

Program PAD

VIL

VIH

Vpp

PAD Program
Address

DIN

DIN

Program Verify PAD

VIL

VIL

VIH

PAD Program
Address

DOUT

CS OUT

Stand-By

Table 4.
High/Low Byte
Selection

x16 (I!0o-1J
xB (1100-7)

x16 Configuration Only

BIlE (Pin 1)

o
o

Ao

Write Operation

Read Operation

0

Whole word

Whole word

Upper byte from/to
odd address

Upper byte = Data Out
Lower byte = 'FF'

Lower byte from/to
even address

Whole word

None

Upper byte = Data Out
Lower byte = 'FF'

o

WR and BHE are used for SRAM functions

Table 5. Product
Selection Guide

Parameter
Address Access Time (max)
Chip-Select Access Time (max)
Output Enable Time (max)
Chip-Select Output Time
Fast Chip-Select Output Time (max)

2-10

WAFERSCALE INTEGRATION, INC.

MAP16B-40

MAP168-45

MAP168-55

Units

40
40
18
22
17

45
45
21
25
20

55
55
23
27
22

ns
ns
ns
ns
ns

MAP168

Table 6. DC
Characteristics

Parameter

Symbol

Test Conditions

Output Low Voltage

VOL
VOH

IOL=8 mA

Output High Voltage
CMOS Standby
Current
-Commercial
-Military

1581

TIL Standby
Current
-Commercial
-Military

1582

CMOS Active Current
No Blocks Selected
-Commercial
-Military

Icc 1A

CMOS Active Current
EPROM Block Selected
-Commercial
-Military

Icc 1B

CMOS Active Current
SRAM Block Selected
-Commercial
-Military

Icc 1C

TTL Active Current
No Blocks Selected
-Commercial
-Military

Icc 2A

TTL Active Current
EPROM Block Selected
-Commercial
-Military

Icc 2B

TIL Active Current
SRAM Block Selected
-Commercial
-Military

Icc 2C

Input Load Current

III

Output Leakage Current

ILO

IOH~2mA

Min

Max

Units

0.5

V

2.4

V

notes 1,3
20
30

mA
mA

30
40

mA
mA

20
30

mA
mA

35
45

mA
mA

55
65

mA
mA

30
40

mA
mA

40
50

mA
mA

65
75

mA
mA

notes 2, 3

notes 1,4

notes 1,4

notes 1,4

notes 2, 4

notes 2, 4

notes 2, 4

V1N=5.5V
orGND

-10

10

~A

VouT=5.5V

-10

10

~

orGND
Notes:
1. CMOS inputs: GND ± 0.3V or VCC ± 0.3V.
2. TIL inputs: V1L ~ 0.8V, V1H ~ 2.0V.
3. Add 1.5 mA/MHz for AC power component.
4. Add 3.5 mA/MHz for AC power component.

WAFERSCALE INTEGRATION, INC.

2·11

MAP168

Table 7. AC
Characteristics

Address to Output Delay

Symbol MAP168-40
Min Max
40
t RC
40
tACC

CSI to Output Delay

tCE

OE to Output Delay

tOE

18

tOEF

15

I'III'IImBfBIt

Read Cycle Time

Output Disable to Output Float
Chip Disable to Output Float

tCSF

Address to Output Hold

tOH

Address to CS0o-7 True

tcso
t FCSO

Address to FCSO True
SRAM Write Cycle Time

22

25

27

ns

17

20

22

ns

40

Address Setup Time

!wc
tcsw
tAS

45

0

Address Hold Time

tAH

Address Valid to Write End

55

ns

45

55

ns

0

0

ns

0

0

0

ns

45

55

ns

30

35

ns
ns

tAW

40

SRAM Write Enable Pulse Width

tpWE

25

Data Setup Time

tos

20

20

30

Data Hold Time

tOH

0

0

0

Write Enable to Data Float

18

ns

21

23

ns

3

3

3

ns

SHE Setup Time

!wEF
tWELZ
t BHES

0

0

0

ns

SHE Hold Time

tBHEH

10

10

10

ns

Write Disable to Data Low Z

PlIPlII1IIIfBIt

Symbol

Test Conditions

Min

Minimum Vee for Data Retention

VOR

Vcc=2.0V,

2.0

Current in Data Retention Mode

ICCOR

CSI ~ Vcc-o.2V,

tCSOR
t ROR

V1N ~ Vcc-0.2V
or V1N ~ 0.2V

Chip Deselect to Data Retention
Recovery Time from Data Retention

2-12

15
10

40

Chip Enable to Write End

Table B. Data
Retention
Characteristics

40

MAP168-45 MAP168-55 Units
Min Max Min Max
45
55
ns
45
55
ns
45
ns
55
21
23
ns
18
20
ns
18
20
ns
10
10
ns

WAFERSCALE INTEGRATION, INC.

Max

Units
V
mA

0

ns

t RC

ns

MAP168

Absolute
Maximum Ratings

Storage Temperature ........... -65°C to +150°C
Voltage to any pin with
respect to GND .......................... -o.6V to +7V
Vpp with respect to GND ....... -0.6 V to +14.0V
ESD Protection ................................... >2000V
Stresses above those listed here may cause
permanent damage to the device. This is a

Table 9. Operating
Range

Range
Commercial
Military

stress rating only and functional operation of
the device at these or any other conditions
above those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods of time may
affect device reliability.

Temperature
O· to +70·C
-55· to +125·C

Figure 3.
Read Cycle
Timing Diagram

Vee
+5V±5%
+5V± 10%

1+-----tRc - - - - + I

ADDRESSES

tOE

Dour

------I-------+H

1737 03

WAFERSCALE INTEGRATION, INC.

2·13

MAP168

Flgutll4.
TIISfLlJad

98n

2.01V~
D.U.T.

30 pF
(INCLUDING
SCOPE AND JIG
.,. CAPACITANCE)

T

High-impedance test systems

Tabla 10.
Timing Levels

Level

Voltage

Input

oand 3V

Reference

1.5V

Flgutll5.
Writaeyele
Timing Dlagnim

173704

we
ADDRESSES

~

---1

\\\1\\\\\\\\
Icsw
lAW

WE

II

\
IPWE

I+----IAS

....
DOUT

lWEF[

1//

IAH-4

I---loS--t j4- IOH - .

Ji

~

...',.

I--IWELZ_

I
\l',.~~

DATA-IN VALID

BHE

,\

, \ \ \ \ ...',.
·1
IBHES -I

BHE VALID

I-

I BHEH -

II

...',....',.

I

I

,\ ,\ \ ,\

,\ \ ,\

,\

I173705

2·14

WAFERSCALE INTEGRATION, INC.

MAP168

Figure 6.
Memory
Architecture

DIRECT ADDRESSES

ADDRESS BUS
BLOCK
DECODE
ADDRESSES
PAD
ESo-7 1--+-+-1

WAFERSCALE INTEGRATION, INC.

2-15

MAPf68

Table 11. MAP168
Pin Assignments

44-pin elOee Package
44-pin PlOee Package
44-pad ellee Package
Pin No.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
·28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

x8
WENpp
CSI/A20
CS07
CS06
esos
eso.
es03
es02
es01
CSOo

x16
BHE
WENpp
CSI/A20
1/01s
1/° 1•
1/° 13
1/° 12
1/°11
1/°10
1/°9
I/Os

GND

GND

FCSO

FCSO

1/°7

1/°7

IIOs
I/Os

I/Os
I/Os

110.
1/°3
1/°2
1/° 1
1/°0

110.
1/°3
1/°2
1/° 1
1/°0

OE
AD
A1
A2
A3
A.
As
A6
A7
As
Ag
A10

OE
AD
A1
A2
A3
A.
As
As
A7
As
A9
A10

GND

GND

GND

A11
A11
A12
A12
A13
A13
A1•
A14
A1S
A1S
A16
A16
A17
A17
A18
A1S
A19
A19
Vee
Vee
WE and BHE are for SRAM functions.

2-16

WAFERSCALE INTEGRATION, INC.

--

----~

-

MAP168

Table 12. MAP168
Pin Assignments

44-pin CPGA Package
Pin No.
x8
GNO
As
WElVpp
A4
CSI/A20
B4
CS07
A3
CS06
B3
CSOs
A2
CS04
B2
CS03
Bl
C2
CS02
CS01
C1
O2
CSO o
01
GND
FCSO
El
E2
1/°7
1/06
Fl
I/Os
F2
G1
1/°4
G2
1/03
H2
1/°2
G3
1/°1
1/00
H3
OE
G4
H4
Ao
Al
Hs
Gs
~
H6
A3
G6
A4
H7
As
G7
A6
Gs
A7
F7
As
Fs
A9
E7
Ala
GNO
Es
Os
All
07
A12
A13
Ce
C7
A14
A1S
Bs
A16
B7
A17
~
A1S
B6
A19
A6
Bs
Vee

x16
BHE
WElVpp
CSI/A20
1/01s
1/°14
1/°13
1/°12
1/°11
1/°10
1/09
I/Os
GND

FCSO
1/°7
1/06
I/Os
1/°4
1/03
1/°2
1/°1
1/00
OE
Ao
Al
~
A3
A4
As
A6
A7
As

Ag
Ala
GNO
All
A12
A13
A14
A1S
A16
A17
A1S
A19
Vee

WAFERSCALE INTEGRATION, INC.

2-11

MAP168

Figure 7.
Pin Assignments
Programming

44 PIN PLOCC PACKAGE
65 4 3 2 14443424140

44 PAD CLLCC OR CLOCC PACKAGE
6 5 4 3 2 1 4443424140

1111111111111111111111
lJ U '_I I_I I_I 1 I '_I 1_' 1_' IJ '_I

7
8
9
10
11
12
13
14
15
16

:J

1111111111111111111111

I_I '_I 1_' 1_' '_I I I '_I '_I '_I '_I I_I

C:

I_I

::1
::'
::'

c:
c:
c:
c:
c:
c:
c:
c:
c:
c:

:J

::.
::'
::1

:J
-- :.

17 ::.

39
38
37
36
35
34
33
32
31
30
29

I-I I-I I-I '-I I-I .-, I-I I-I I-I I-I I-I

1111tll111111111111111

7
8
9
10
11
12
13
14
15
16
17

::1
::.
::1

:J
:]

::'

:J
:)

::'
::::'

'-'

0

":-: :-: :-: :-: :-: :-: :-: :-: :-: :-: :-:

c:
c:
c:
c:
c:
c:
c:
c:
c:
c:
c:
/

1819202122232425262728

1819202122232425262728

TOP (THROUGH PACKAGE) VIEW

TOP (THROUGH PACKAGE) VIEW

1

39
38
37
36
35
34
33
32
31
30
29

44 PIN CPGA PACKAGE
2 3 4 5 678

A
808808
B08080800
C 80
00
080
08
E 80
08
F 80
08
G 88088808
H
808800
TOP (THROUGH PACKAGE) VIEW
1737 07

Upon delivery from WSI or after each
erasure (see Erasure section), the MAP168
device has all bits in the PAD and EPROM in
the "one" or high state. Zeros are loaded
through the procedure of programming.

Information for programming the device is
available directly from WSI. Please contact
your local sales representative.

Erasure

To clear all locations of their programmed
contents, expose the device to an ultra-violet
light source. A dosage of 15W-second/cm' is
required. This dosage can be obtained with
exposure to a wavelength of 2537A and
intensity of 1200J.1W/cm' for 15 to 20 minutes.
The device should be about one inch from
the source and all filters should be removed
from the UV light source prior to erasure.

The MAP168 device and similar devices will
erase with light sources having wavelengths
shorter than 4000A. Although erasure times
will be much longer than with UV sources at
2537A, the exposure to fluorescent light and
sunlight will eventually erase the device; for
maximum system reliability, these sources
should be avoided. If used in such an environment, the package windows should be
covered by an opaque label or substance.

System
Development
Tools

MAP168 System Development Tools are a
complete set of PC-based development
tools. Installed on an IBM PC or compatible
computer, these tools provide an integrated,
easy-to-use software and hardware environment to support MAP168 device develop-

ment. The tools run on an IBM-XT, AT, or
compatible computer running MS-DOS
version 3.1 or later. The system must be
equipped with 640K bytes of RAM and a hard
disk.

2·18

WAFERSCALE INTEGRATION, INC.

MAP168

System
Dellelopment
Tools (Con't)

Hardware

Software

The MAP168 System Programming Hardware consists of:

The MAP168 System Development Software
consists of the following:

o

WS6000 MagicPro Memory and PSD
Programmer

o

WISPER Software-PSD Software
Environment

o

WS6003 44-pin LCC Package Adaptor
(for 44-pin CLLCC, CLDCC, and PLDCC
packages)

o

MAPLE Software-MAP168 Location
Editor

o

o

WS6011 44-pin CPGA Package Adaptor

MAPPRO Software-Device Programming Software

The MagicPro Programmer is the common
hardware platform for programming all WSI
programmable products. It consists of the
IBM-PC plug-in Programmer Board and the
Remote Socket Adaptor Unit.

Figure 8. MAP168
Dellelopment
Cycle

The configuration of the MAP168 device is
entered using MAPLE software. MAPRO
software configures MAP168 devices by
using the MagicPro programmer and the
socket adaptor. The programmed MAP168 is
then ready to be used. The development
cycle is depicted in Figure 8.

fJ

,-------,
IBM PC PLATFORM

I[

User
Terminal

J

Menu Selection

I
I
I
I
I
I
I
I

DOS

!
WISPER

I
I
I
I

Confl uratlon Data I
I
I
I
I
Proarammmo Data I

!
MAPLE

r----.
I

I~
0

!
MAPRO

I

I

I
I

DISK

r----->I

I - - --1- ----I
Hex File
Format

i

[§]
MaglcPro Hardware
1737 08

WAFERSCALE INTEGRATION, INC.

2-19

MAP16B

System
Development
Tools (Con't)

Ordering
Information

Support
WSI provides a complete set of quality
support services to registered System
Development Tools owners. These support
services include the following:
Q

12-month Software Updates.

Q

Hotline to WSI Application ExpertsFor direct design assistance.

Q

24-Hour Electronic Bulletin BoardFor design assistance via dial-up
modem.

MAP16B
Part Number
MAP168-40C*
MAP168-40J*
MAP168-40L*
MAP168-45C
MAP168-45CM*
MAP168-45CMB*
MAP168-45J
MAP168-45L
MAP168-45LM*
MAP168-45LMB*
MAP168-45X
MAP168-45XM*
MAP168-45XMB*
MAP168-55C
MAP168-55CM
MAP168-55CMB
MAP168-55J
MAP168-55L
MAP168-55LM
MAP168-55LMB
MAP168-55X
MAP168-55XM
MAP168-55XMB

Speed
(ns)
40
40
40
45
45
45
45
45
45
45
45
45
45
55
55
55
55
55
55
55
55
55
55

Package
Type
44-pad CLLCC
44-pin PLDCC
44-pin CLDCC
44-pad CLLCC
44-pad CLLCC
44-pad CLLCC
44-pin PLDCC
44-pin CLDCC
44-pad CLDCC
44-pad CLDCC
44-pin CPGA
44-pin CPGA
44-pin CPGA
44-pad CLLCC
44-pad CLLCC
44-pad CLLCC
44-pin PLDCC
44-pin CLDCC
44-pin CLDCC
44-pin CLDCC
44-pin CPGA
44-pin CPGA
44-pin CPGA

*These products are advanced information.

2-20

WAFERSCALE INTEGRATION, INC.

Training
WSI provides in-depth, hands-on workshops
for the MAP168 device and System Development Tools. Workshop participants learn how
to program their own high-performance, userconfigurable mappable memory subsystems.
Workshops are held at the WSI facility in
Fremont, California.

Package
Drawing
C3
J2
L4
C3
C3
C3
J2
L4
L4
L4
X2
X2
X2
C3
C3
C3
J2
L4
L4
L4
X2
X2
X2

Operating
Temperature
Commercial
Commercial
Commercial
Commercial
Military
Military
Commercial
Commercial
Military
Military
Commercial
Military
Military
Commercial
Military
Military
Commercial
Commercial
Military
Military
Commercial
Military
Military

Manufacturing
Procedure
Standard
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
MIL-STO-883C
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STO-883C
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STO-883C

MAP168

Ordering
Information

System Development Tools
Part Number

Contents

MAP168-GOLO

WISPER Software
MAPLE Software
User's Manual
WSI-SUPPORT
WS6000 MagicPro Programmer

MAP168-SILVER

WISPER Software
MAPLE Software
User's Manual
WSI-SUPPORT

WS6000

MagicPro Programmer
IBM PC plug-in Adaptor Card
Remote Socket Adaptor

WS6003

44-pin LCC Package Adaptor for
44-pin CLLCC, CLOCC, and PLOCC Packages.
Used with the WS6000 MagicPro Programmer.

WS6011

44-pin CPGA Package Adaptor.
Used with the WS6000 MagicPro Programmer.

WSI-SUPPORT

WSI-TRAINING

Support Services including:

o
o

12-month Software Update Service

o

24-hour access to WSI Electronic Bulletin Board

Hotline to WSI Application Experts

Workshops at WSI, Fremont, CA.
For details and scheduling, call PSO Marketing, (415) 656-5400.

WAFERSCALE INTEGRATION, INC.

2·21

2-22

WAFERSCALE INTEGRATION, INC.

iF==:=~
.........
..........
_-

Programmable System™Device

WAFERSCALE INTEGRATION, INC.

PSD301

Preliminary

User·Configurable
Peripheral with Memory

-=

~

i=:'-=i-iii.-.-=
---~~

Key Features

r:J Second Generation Programmable

-

Multiplexed or Non-Multiplexed
Address/Data Buses

System Device

r:J User-Configurable Peripheral for
Microcontroller Based Applications Enables rapid design implementation and
fast time to market

r:J Available in space saving surface mount

-

Selectable 8- or 16-Bit Bus Width

-

Power-Down

-

Address Inputs Can Be Latched or
Transparent

-

Latched Low-Order Address Byte
Available as Output

and through-hole packages

r:J Windowed package option for prototyping

r:J High-Density UV EPROM
-

r:J Low cost OTP (one-time programmable)
package for high volume applications

Divided Into Eight Equal Mappable
Blocks

r:J CMOS for low power consumption
r:J User-Configurable to Interface with Any
8- or 16-Bit Microcontroller
-

EPROM Block Resolution of 4K Bytes
or 2K Words
-

Programmable Address Decoder (PAD)

-

Programmable Control Signals

-

Programmable Polarity

-

Built-In Address Latches

256K Bits Configurable as 32K x 8 or
as 16K x 16

EPROM: Up to 120 ns Access Time
(Including PAD Decoding Time)

r:J Static RAM
-

16K Bits Configurable as 2K x 8 or
as 1K x 16

-

SRAM: Up to 120 ns Access Time
(Including PAD Decoding Time)

r:J Port Expansion/Reconstruction of Up to
16 I/O Lines
-

Individually Configurable as Output
or Input

r:J Highly Configurable, Many Operational

r:J Addressable Range
-

1 MByte or 0.5 MWords

r:J Low Power TTL-Compatible CMOS Device

Modes

Applications

r:J Computers (Workstations and PCs) Fixed Disk Control, Modem, Imaging,
Laser Printer Control

r:J Medical Instrumentation - Hearing Aids,
Monitoring Equipment, Diagnostic Tools

r:J Military - Missile Guidance, Radar, Sonar,
r:J Telecommunications -

Modem,
Cellular Phone, Digital PBX, Digital
Speech, FAX, Digital Signal Processing

Secure Communications, RF Modems

r:J Industrial -

Robotics, Power Line
Access, Power Line Monitor

WAFERSCALE INTEGRATION, INC.

2-23

PS0301

Product
Description

In 1986 WSI introduced a new concept in
programmable VLSI, Programmable System
Devices. The PSD family consists of userconfigurable system-level building blocks
on-a-chip, enabling quick implementation
of application-specific controllers and
peripherals. The first generation PSD
series includes the MAP168, a UserConfigurable Peripheral, which is ideal for
DSP applications; the SAM448, a UserConfigurable Microsequencer for control
and interface applications, and the PAC1000,
a User-Configurable Microcontroller.
The PSD301 is a second generation PSD.
The PSD301 is ideal for microcontroller
based applications where fast time-tomarket, small form factor and low power
consumption are essential. When combined
together in an 8- or 16-bit system, virtually
any microcontroller (8051, 8096, 16000,
etc.) and the PSD301 work together to
create a very powerful 2-piece chip-set.
This implementation provides all the
required control and peripheral elements
of a microcontrolier based system peripheral
with no external "glue" logic required.
The PSD301 integrates high performance
user-configurable blocks of EPROM,
SRAM, and logic in a single circuit. The
major functional blocks include a
Programmable Address Decoder (PAD),
256K bits of high speed EPROM, 16K bits
of high speed SRAM, input latches, and
output ports. The PSD301 is ideal for
applications requiring high performance,
low power, and very small form factors.
These include fixed disk control, modem,
cellular telephone, instrumentation,
computer peripherals, military and similar
applications.
The PSD301 is an optimal solution for
microcontrollers that need:

CJ 110 reconstruction (microcontrollers lose
at least two 110 ports when accessing
external resources).

CJ More EPROM and SRAM than the
microcontroller's internal memory.

CJ Chip-select, control, or latched address
lines that are otherwise implemented
discretely.

CJ An interface to shared external resources.

2·24

WAFERSCALE INTEGRATION, INC.

The PSD301 (shown in Figure 1) can
efficiently interface with, and enhance, any
8- or 16-bit microcontroller system. No
other solution provides microcontrollers
with port expansion, latched addresses, a
programmable address decoder (PAD), an
interface to shared resources, 256 kbit
EPROM, and 16 kbit SRAM on a single
chip. The PSD301 does not require glue
logic for interfacing to any 8- or 16-bit
microcontrollers.
The 8051 microcontroller family can take
full advantage of the PSD301's separate
program and address spaces. Users of the
68HCXX family of microcontrollers can
change the functionality of the control
signals and directly connect the R/Vii and
E signals. Users of 16-bit microcontrollers
(including the 80186, 8096, 80196, 16XXX)
can use the PSD301 in a 16-bit
configuration. Address and data buses
can be configured to be separated or
multiplexed, whichever is required by the
host processor.
The flexibility of the PSD301 110 ports
permit interfacing to shared resources. The
user can assign the following functions to
these ports: standard 110 pins, chip select
outputs from the PAD, latched address or
multiplexed low-order addressldata byte.
This enables users to design add-on
systems such as disk drives, modems,
etc., that easily interface to the host bus
(e.g., IBM PC, SCSI).
The PSD301's on-Chip programmable
address decoder (PAD) enables the user
to map the 110 ports, eight segments of
EPROM (as 4K x 8, or as 2K x 16), SRAM
(as 2K x 8 or as 1K x 16), and chip select
outputs anywhere in the address space of
the microcontroller. The PAD can implement
up to 4 sum-ol-product expressions based
on address inputs and control signals. This
further facilitates the interface to
microcontrollers with different boot-up
locations and 110 address mappings, e.g.,
the 8051 and 8096 microcontrollers have
the boot-up addresses in the lower half of
their memory maps; the 80186 and
68HCXX use high memory boot-up
addresses.

PS0301

Figure 1.
PS0301
Architecture

ALE/AS

DIS-OS

OCTAL,
LATCH
ADO
ADI
AD2
AD3
AD4
ADS
AD6
AD7

#
-~}
#-

uppER.l LOWER
BYTE
BYTE
2K
2K
EPROM

Al-Al1

~
~

-ro-

~
~
g,

-~~}
~
Att

ADS
AD9
AD10
ADll
AD12
AD13
AD14
ADIS

itt
"ill

-m

~

A15
A14
A13
A12
All

r----

~

~

M§,

PAD

~

';~F

WR
R/W

g

ESO

.....

~
~

-=---

R!L:£
ALE
A~

··
1·

f~-~}

~
~

UPPER LOWER
BYTE
BYTE
2K
2K
EPROM

I

RSO

-+

I

UPPER.I. LOWER
BYTE
BYTE
lK
lK
SRAM

e

BYTE WIDE
BUS
ISOLATION
BUFFER

-

~--,

-

ADO-AD7/ 00- 07

08 - 015

~"'-I-PBO
CSOTO CS7
I-- PBl
I-- PB2
I-- PB3
I-- PB4
I-- PBS
08.0151I-- PB6
_ _ - r - I - - PB7

-

I

-

-----

r--

~

I

PAO
PAl
PA2
PA3
PA4
PAS
PA6
.... r - - PA7

-

Il 1 II

KJ

§e§'-

-~

UPPER LOWER
BYTE
BYTE
2K
2K
EPROM

A1-Al0

P---

ADO- AD7

PORTA

r--_

POR TB

less

A~

"DATA
TRANSCEIVERS

@.
@.

&
g
&

M.L-

ADDRESS/DATA

P---

f,

.

ALE/AS
OCTAL
LATCH

07-00

ES7

I

l

CS8
PO RTC
CS9
r--CS10

- ...

--- .... -

---

PCO
PCl
PC2

A16
A17
A18

A16, A17, A18

OUPUTS DECODED
FROM BHEAO.
RD/E
WR/R/W
BHE/PSEN
RESET
A19/CSI

CONTROL AND CONFIGURATION SECTION

NOTES:

CONTROL BUS TO PORTS

1. RESET and CSI are not available as programmable options In the PAD. An active RESET ensures
that the PAD deselects all of its outputs, and a high level on CSI ensures that the PAD is In
power·down mode.
2. Details of the PAD as a programmable array decoder are given in Figure 3.

WAFERSCALE INTEGRATION, INC.

2·25

PSD301

Figure 2.
PS0301 Port
Configurations

Figure 2 shows the PS0301's I/O port configurations.
AD.-AD,.

I/O OR :&-A7
ADo-A 7

ADo-AD7

PA

AL E

•
iIii
EJPSEN
•
AIWOR WRN."
•
/E

./CSI
RESET

•

•

•

I/O or

•

CSO-CS7

•

r--

•

CS.-CS,o

•

PS0301 configured for multiplexed
16-bit address/data bus

Aa-A15

•

-A7

ALE

A ,glCSI

RESET

•
•

I/O OR CSO-cs7
PB

r-A,.-A,. OR CS.-CS,.

glCSI

PC

RESET

PS0301 configured for multiplexed
a-bit address/data bus.

A• -A,.

iIiiE/PSEN

RD/E

r--

0 0-07

PA

PB

AL E

•

0.-0,.

•

•

•

PS0301 configured for nonmultiplexed 16-bit address/data bus.

I/O or

glCSI

•

r--

PS0301 configured for nonmultiplexed a-bit address/data bus.

AO o-A0 7 = addresses Ao-A7 multiplexed with data lines 0 0-07,
AOa-A015 = addresses Aa-A15 multiplexed with data lines 0a-015'

WAFERSCALE INTEGRATION, INC.

A,.-A,. OR CS.-CS,.

PC

RESET

Legend:

2·26

CSO-CS7

PB

RIW OR WRN••
IE

A,.-A,. OR CS.-CS,o

0,,-0 7

r--

iIiiEJPSEN

r-PC

PA

-A7

f--

RIW ORWRN."

•
•

PA

RIW ORWRN."
RD/E

A'B-A,. OR

PC

---

iIii
EJPSEN

I/O OR Ao-A7
ADo-AD7

•

AL E

rPB

-A15
ADO-AD7

PSD301

Table 1. PS0301
Pin oescriptiDns

Name

'tYpe

Description

BHE/PSEN

I

When the data bus width is 8 bits (CDATA = 0), this pin is
PSEN. In this mode, PSEN is the active low EPROM read
pulse. The SRAM and 1/0 ports read signal is generated
when RD is low (CRRWR = 0), or when E and R/W are
high (CRRWR = 1). If the host processor is a member of
the 8031 family, PSEN must be connected to the
corresponding host pin. In other 8-bit host processors that
do not have a special EPROM-only read strobe, PSEN
should be tied to Vce. In this case, RD or E and R/W
provide the read strobe for the SRAM, 1/0 ports, and
EPROM. When the data bus width is configured as 16
(CDATA = 1), this pin is BHE. When BHE is low, a highorder byte is read from, or written into the PSD301,
depending on 'the operation being read or write,
respectively. In program'ming mode, this pin is pulsed
between Vpp and O.

WRlVpp or
R/WlVpp

I

In the operating mode, this pin's function is WR
(CRRWR = 0) or R/W (CRRWR = 1). When configured as
WR, a write operation is executed during an active low
pulse. When configured as R/W, with R/W = 1 and E = 1,
a read operation is executed; if R/W = 0 and E = 1, a
write operation is executed. In programming mode, this pin
must be tied to Vpp voltage.

RD/E

I

When configured as RD (CRRWR = 0), this pin provides
an active low RD strobe. When configured as E (CRRWR
= 1), this pin becomes an active high pulse, which,
together with R/W defines the cycle type. Then, if R/W = 1
and E = 1, a read operation is executed. If RtW = 0 and
E = 1, a write operation is executed.

CSIIA19

I

This pin has two configurations. When it is CSI
(CA19/CSI = 0) and the pin is asserted high, the device
is deselected and powered down. (See Tables 12 and 13
for the chip state during power-down mode.) If the pin is
asserted low, the chip is in normal operational mode.
When it is A19, (CA19/CSI = 1), this pin can be used as
an additional input to the PAD. In this mode, there is no
power-down capability.

RESET

I

This user-programmable pin can be configured to reset on
high level (CRESET = 1) or on low level (CRESET = 0).
It should remain active for at least 100 ns. See Tables 10
and 11 for the chip state after reset.

ALE or
AS

I

In the multiplexed modes, the ALE pin functions as an
Address Latch Enable or as an Address strobe and can be
configured as an active high or active low signal. The ALE
or AS trailing edge latches lines AD15/A15-ADO/AO, A16-A19,
and BHE, depending on the PSD301 configuration. See
Table 8. In the non-multiplexed modes, it can be used as a
general-purpose PAD input signal.

Legend:
NOTE:

The 1/0 column abbreviations are: I

= input;

1/0

= input/output;

P

= power.

3. All the configuration bits mentioned in Table 1 appear in parentheses and are explained in the
Configuration Register section.

WAFERSCALE INTEGRATION, INC.

2·Z7

PS0301

Table 1. PSD301
Pin Descriptions
(Cont.)

2-28

Name

Type

Description

PA7
PAB
PA5
PA4
PA3
PA2
PA1
PAO

I/O

PA7-PAD is an 8-bit port that can be configured to track
AD7/A7-ADO/AO from the input (CPAF2 = 1). Otherwise
(CPAF2 = 0), each bit can be configured separately as an
I/O or lower-order latched address line. When configured
as an I/O (CPAF1 = 0), the direction of the pin is defined
by its direction bit, which resides in the direction register. If
a pin is an I/O output, its data bit (which resides in the
data register) comes out. When it is configured as a loworder address line (CPAF1 =1), A7-AO can be made the
corresponding output through this port (e.g., PAB can be
configured to be the AB address line). Each port bit can be
a CMOS output (CPACOD = 0) or an open drain output
(CPACOD = 1). When the chip is in non-multiplexed mode
(CADDRDAT = 0), the port becomes the data bus lines
(DO-D7). See Figure 4.

PB7
PBB
PB5
PB4
PB3
PB2
PB1
PBO

I/O

PB7-PBO is an 8-bit port for which each bit can be
configured as an I/O (CPBF = 1) or chip-select output
(CPBF = 0). Each port bit can be a CMOS output
(CPBCOD = 0) or an open drain output (CPBCOD = 1).
When configured as an I/O, the direction of the pin is
defined by its direction bit, which resides in the direction
register. If a pin is an I/O output, its data (which resides in
the data register) comes out. When configured as a chipselect output, CSO-CS3 are a function of up to four
product terms of the inputs to the PAD; CS4-CS7 then are
each a function of up to two product terms. When the chip
is in non-multiplexed mode (CADDRAT = 0) and the data
bus width is 1B (CDATA = 1), the port becomes the most
significant byte of the data bus (D8-D15). See Figure B.

PCO
PC1
PC2

I/O

This is a 3-bit port for which each bit is configurable as a
PAD input or output. When configured as an input (CPCF
= 0), the bits can be latched with ALE (CADDHLT = 1) or
be transparent inputs to the PAD (CADDHLT = 0). When' a
pin is configured as an output (CPCF = 1), it is a function
of one product term of all PAD inputs. See Figure 7.

ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
ADB/AB
AD7/A7

I/O

In multiplexed mode, these pins are the multiplexed loworder address/data byte, After ALE latches the addresses,
these pins input or output data, depending on the settings
of the RD/E, WR/vpp or R/W, and BHE/PSEN pins. In
non-multiplexed mode, these pins are the low-order
address input byte.

AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

I/O

In 1B-bit multiplexed mode, these pins are the multiplexed
high-order address/data byte. After ALE latches the
addresses, these pins input or output data, depending on
the settings of the RD/E, WR/vpp or R/W, and BHE/PSEN
pins. In all other modes, these pins are the high-order
address input byte.

GND

P

Vss (ground) pin.

Vee

P

Supply voltage input.

WAFERSCALE INTEGRATION, INC.

P50301

Operating Modes

The PSD301's four operating modes allow
it to interface directly to 8- and 16-bit
microcontrollers and microprocessors with
multiplexed and non-multiplexed
address/data buses. These operating
modes are:

address/data bus (AD8/A8-AD15/A15) is bidirectional and permits latching of the
high-order address when the ALE signal is
active on the same pins. The high-order
data bus is read from or written to the
device, depending on the state of the
RD/E, BHE/PSEN, and WRlVpp or R/W
pins. Ports A and B can be configured as
in Table 2.

Cl Multiplexed 8-bit address/data bus
Cl Multiplexed 16-bit address/data bus
Cl Non-multiplexed address/data, 8-bit
data bus
Cl Non-multiplexed 16-bit address/data bus

Multiplexed 8·Bit Address/Data Bus
This mode is used to interface to
microcontrollers with an 8-bit data bus and
a 16-bit or larger address bus. The loworder address/data bus (ADO/AO-AD7/A7) is
bi-directional and permits the latching of
the address when the ALE signal is active.
On the same pins, the data is read from or
written to the device; this depends on the
state of the RD/E, BHE/PSEN, and
WRlVpp or R/W pins. The high-order
address/data bus (AD8/A8-AD15/A15)
contains the high-order address bus byte.
Ports A and B can be configured as in
Table 2.

Multiplexed 16·Bit Address/Data Bus
This mode is used to interface to
microcontrollers with a 16-bit data bus and
a 16-bit or larger address bus. The loworder address/data bus (ADO/AO-AD7/A7) is
bi-directional and permits the latching of
the address when the ALE signal is active.
On the same pins, the data is read from or
written to the device; this depends on the
state of the RD/E, BHE/PSEN, and
WRlVpp or R/W pins. The high-order

Non·Multiplexed Address/Data,
8·Bit Data Bus
This mode is used to interface to nonmultiplexed 8-bit microcontrollers with an
8-bit data bus and a 16-bit or larger address
bus. The low-order address/data bus
(ADO/AO-AD7/A7) is the low-order address
input bus. The high-order address/data bus
(AD8/A8-AD15/A15) is the high-order
address bus byte. Port A is the low-order
data bus. Port B can be configured as
shown in Table 2.

Non·Multiplexed 16·Bit Address/Data Bus
This mode is used to interface to nonmultiplexed 16-bit microcontrollers with a
16-bit data bus and a 16-bit or larger
address bus. The low-order address/data
bus (ADO/AO-AD7/A7) is the low-order
address input bus. The high-order address/
data bus (AD8/A8-AD15/A15) is the highorder address bus byte. Port A is the loworder data bus. Port B is the high-order
data bus.
Table 2 summarizes the effect of the
different operating modes on ports A, B,
and the address/data pins. The
configuration of Port C is independent of
the four operating modes.

WAFERSCALE INTEGRATION, INC.

2·29

fJ

PS0301

Table 2. PSD301
Bus and Port
Configuration
Options

Multiplexed Address/Data

Non-Multiplexed Address/Data

I/O and/or low-order address
lines or
Low-order multiplexed
address/data byte

00-07 data bus lines

8-Bft Data Bus
Port A

Port B

I/O and/or CSO-CS7

I/O and/or CSO-CS7

ADO/AO-AD7/A7

Low-order multiplexed
address/data byte

Low-order address bus byte

AD8/A8-AD15/A15

High-order address bus byte

High-order address bus byte

Port A

I/O and/or low-order address
lines or
Low-order multiplexed
address/data byte

Low-order data bus byte

Port B

I/O and/or CSO-CS7

High-order data bus byte

ADO/AO-AD7/A7

Low-order multiplexed
address/data byte

Low-order address bus byte

AD8/A8-AD15/A15

High-order multiplexed
address/data byte

High-order address bus byte

16-Bft Data Bus

Programmable
Address Decoder
(PAD)

The PSD301's programmable address
decoder (PAD) has 14 inputs and 24
outputs. All its I/O functions are listed in
Table 3 and shown in Figure 3.
The PAD is used to select all chip internal
parts and to generate external chip-selects
(see Figure 3). Pins A11-A15, RD/E,
WRlVpp or R/VIi, Reset, and ALE are fixed
functions. A16-A19 can be address inputs
or general purpose inputs to the PAD for
implementing logic functions. Internal and

2-30

WAFERSCALE INTEGRATION, INC.

external PAD select signals can override
EPROM memory whose addresses
overlap. This lets the user make more
efficient use of the address space. For
example, if the EPROM is not used
completely for program storage, the
unused EPROM address space can be
allocated to I/O ports, SRAM, or other PAD
select signals. USing WSI's MAPLE
software, any input function to the PAD
can be selected as active low, active high,
or don't care.

PSD301

Table 3. PS0301
I/O Functions

Function
PAD Inputs
CSI or A19

In CSI mode (when high), PAD deselects all of its outputs and enters
a power-down mode (see Tables 12 and 13). In A19 mode, it is
another input to the PAD.

A16-A18

These are general purpose inputs from Port C. See Figure 3, note 4.

A11-A15

These are address inputs.

RD or E

This is the read pulse or enable strobe input.

WR or R/W
ALE
RESET

This is the write pulse or R/W select signal.
This is the ALE input to the chip.
This deselects all outputs from the PAD; it can not be used in
product term equations. See Tables 10 and 11.

PAD Outputs
CSO-CS3

These chip-select outputs can be routed through Port B. Each of
them is a function of up to four product terms of the PAD inputs.

CS4-CS7

These chip-select outputs can be routed through Port B. Each of
them is a function of up to two product terms of the PAD inputs.

CS8-CS10

These chip-select outputs can be routed through Port C. See Figure 3,
note 4. Each of them is a function of one product term of the PAD inputs.

ESO-ES7

RSO
CSIOPORT

These are internal chip-selects to the 8 EPROM banks. Each bank
can be located on any boundary that is a function of one product
term of the PAD address inputs.
This is an internal chip-select to the SRAM. Its base address location
is a function of one term of the PAD address inputs.
This internal chip-select selects the I/O ports. It can be placed on
any boundary that is a function of one product term of the PAD
inputs. See Tables 6 and 7.

CSADIN

This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the input
direction of Port A. CSADIN is gated externally to the PAD by the
internal read signal. When CSADIN and a read operation are active,
data presented on Port A flows out of ADO/AO-AD7/A7. This chipselect can be placed on any boundary that is a function of one
product term of the PAD inputs. See Figure 5.

CSADOUT1

This internal chip-select, when Port A is configured as a low-order
address/data bus in track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT1 is gated externally to the PAD by the
ALE signal. When CSADOUT1 and the ALE signal are active, the
address presented on ADO/AO-AD7/A7 flows out of Port A. This chipselect can be placed on any boundary that is a function of one
product term of the PAD inputs. See Figure 5.

CSADOUT2

This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT2 must include the write-cycle control
signals as part of its product term. When CSADOUT2 is active, the
data presented on ADO/AO-AD7/A7 flows out of Port A. This chipselect can be placed on any boundary that is a function of one
product term of the PAD inputs. See Figure 5.

WAFERSCALE INTEGRATION, INC.

2·31

'50301

Figure 3.
PSD301 PAD
Description
ALE orAS~

...

~

~

RD or E

i'O--=
"S

..,

WR or R/W
"'S

~

A19

..g

...

ESO
ES1
ES2
8 EPROM Block
ES3
ES4
Select Lines
ES5
ES6
ES7
RSO _ _ SRAM Block Select
eSIOPORT-"0 Base Address
eSADIN
Track Mode
eSADOU
} Control Signals
eSADOU

:g

~

A18
"'S
~

A17

---

eSO/PBO

eSl/PB1

"
"S

..,
~

eS2/PB2

A16

..,

"'S

A15

CS3/PB3

"

'--

"S
~

A14

A13

"

~

CS4/PB4

~

CS5/PB5

..,K

eS6/PB6

..,K

eS7/PB7

..,

""S
"

""S

A12

"
"S

A11

"
""S

...
eSI
RESET

...

..,

...

...

~

~

C>oC>o-

esa/pco
eS9/PC1
CS10/pe2

NOTES: 4. CSi is a power-down signal. When high, the PAD is in stand-by mode and all its outputs become
non-active. See Tables 12 and 13.
5. RESET deselects all PAD output signals. See Tables 10 and 11.
S. Maximum PAD latency is 35 ns.
7. AlB, A17, and AIS are internally multiplexed with eSl0, eS9, and esa, respectively. Either Ala or
eSl0, A17 or eS9, and Al0 or esa can be routed to the external pins of Port e.

2·32

WAFERSCALE INTEGRATION, INC.

PS0301

Configuration
Bits

Table 4. PSD301
Non-Volatile
Configuration
Bits

The configuration bits shown in Table 4
are non-volatile cells that let the user set
the device, I/O, and control functions to
the proper operational mode. Table 5 lists
all configuration bits. The configuration bits
are programmed and verified during the

Use This Sit
CDATA

programming phase. In operational mode,
they are not accessible. To simplify
implementing a specific mode, use the
WSl's PSD301 MAPLE software to set
the bits.

To
Set the data bus width to 8 or 16 bits.

CADDRDAT

Set the address/data buses to multiplexed or non-multiplexed mode.

CRRWR

Set the RD/E and WR/vpp or RIW pins to RD and WR pulse, or to
E strobe and RIW status.

CA19/CSI

Set A19/CSI to CSI (power-down) or A19 input.

CALE

Set the ALE polarity.

CPAF2

Set Port A either to track the low-order by1e of the address/data
multiplexed bus or to select the I/O or address option. 8

CSECURITY
CRESET

Set the RESET polarity.

COMB/SEP

Set PSEN and RD for combined or separate address spaces (see
Figures 8 and 9).

CPAF1

Configure each pin of Port A in multiplexed mode to be an I/O or
address out.

CPACOD
CPBF
CPBCOD

Configure each pin of Port A as an open drain or active CMOS pullup output.
Configure each pin of Port B as an I/O or a chip-select output.
Configure each pin of Port B as an open drain or active CMOS pullup output.

CPCF

Configure each pin of Port C as an address input or a chip-select
output.

CADDHLT

Configure pins A16-A19 to go through a latch or to have their latch
transparent.

NOTE:

fI

Set the security on or off.

8. CPAFt determines whether the output

IS

1/0 or address.

WAFERSCALE INTEGRATION, INC.

2-33

PS0301

Table 5. PSD301
Configuration
Bits

Configuration
Bits

No.
of Bits

CDATA

1

8-bit or 16-bit data bus width
CDATA = 0, '8-bit data bus
CDATA = 1, 16-bit data bus

CADDRDAT

1

Address/data multiplexed or non-multiplexed (separate buses)
CADDRDAT = 0, non-multiplexed address/data bus
CADDRDAT = 1, multiplexed address/data bus

CRRWR

1

CRRWR
CRRWR

CA19/CSI

1

A19 or CSI
CA19/CSI = 0, enable power-down mode
CA19/CSI = 1, A19 input to PAD

CALE

1

Active high or active low
CALE = 0, active high
CALE = 1, active low

CRESET

1

Active high or active low
CRESET = 0, active low reset signal
CRESET = 1, active high reset signal

COMB/SEP

1

Combined or separate memory space for EPROM and SRAM
COMB/SEP = 0, combined
COMB/SEP = 1, separate

CPAF1

8

Port A I/Os or AO-A?
CPAF1 = 0, Port A pin
CPAF1 = 1, Port A pin

=
=

0, RD and WR active low strobes
1, R/W status and E active high pulse

=
=

I/O
Ai (0 .;; i .;; ?)

CPAF2

1

Port A ADO-AD? (address/data multiplexed bus)
CPAF2 = 0, address or I/O on Port A (according to CPAF1)
CPAF2 = 1, address/data multiplexed on Port A (track mode)

CPBF

8

Port B I/Os or CSO-CS?
CPBF = 0, Port B Pin = CSi (0 .;; i .;; ?)
CPBF = 1, Port B Pin = I/O

CPCF

3

Port C A16-A18 or CS8-CS10
CPCF = 0, Port C Pin = Ai (16';; i .;; 18)
CPCF = 1, Port C Pin = CSi (8';; i.;; 10)

CPACOD

8

Port A CMOS or open-drain outputs
CPACOD = 0, CMOS output
CPACOD = 1, open-drain output

CPBCOD

8

Port B CMOS or open-drain outputs
CPBCOD = 0, CMOS output
CPBCOD = 1, open-drain output

CADDHLT

1

A16-A19 latched or latch transparent
CADDHLT = 0, address latch transparent
CADDHLT = 1, address latched (ALE dependent)

CSECURITY

1

Security on or off
CSECURITY = 0, no security
CSECURITY = 1, secured part (cannot be copied)

Total Number
of Bits

45

NOTES:

2·34

Description

g. WSl's MAPLE software will gUide the user to the proper configuration choice.
10 In an unprogrammed or erased part, all configuration bits are O.

WAFERSCALE INTEGRATION, INC.

PSD301

Port Functions

Figure 4. Port A
Pin Structure

The PSD3D1 has three 1/0 ports (Ports A,
B, and C) that are configurable at the bit
level. This permits great flexibility and a
high degree of customization for specific

I
N
T
E
R
N
A
L
A
D
D
R

/
D
A
T
A

READ PIN

READ DATA
CMOS/OD
(NOTE 11)
WRITE DATA CK

ALE

KNABLE
ADDR __

G

LATCH

·

MUX

D
R
ADI/D!..READ DIR

·

j~

'-J

0
/

NOTE:

·

R

A
D

RESET

PORTA PIN

OUl.

OFF

D

B
U
S

A
D
7

applications. The following is a description
of each port. Figure 4 shows the pin
structure of Port A.

D
WRITE DIR

CK

OIR
FF

I

CONTROL

R

I
11. CMOS/DO determines whether the output is open drain or CMOS.

Port A in Multiplexed Address/Data Mode
The default configuration of Port A is 110.
In this mode, every pin can be set as an
input or output by writing into the
respective pin's direction flip flop (DIR FF,
in Figure 4). As an output, the pin level
can be controlled by writing into the
respective pin's data flip flop (DFF, in
Figure 4). When DIR FF = 1, the pin is
configured as an output. When DIR FF =
D, the pin is configured as an input. The
controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the DFF bits by accessing the READ
DATA register. Port A pin levels can be
read by accessing the READ PIN register.

Individual pins can be configured as
CMOS or open drain outputs. Open drain
pins require external pull-up resistors. For
addressing information, refer to Tables 6
and 7.
Alternatively, each bit of Port A can be
configured as a low-order latched address
bus bit. The address is provided by the
port address latch, which latches the
address on the trailing edge of ALE.
PAD-PA7 can become AD-A7, respectively.
This feature of the PSD3D1 lets the user
generate low-order address bits to access
external peripherals or memory that
require several low-order address lines.

WAFERSCALE INTEGRATION, INC.

2-35

PS0301

Port Functions
(Cont.)

Another mode of Port A (CPAF2 = 1) sets
the entire port to track the inputs
ADO/AO-AD7/A7, depending on specific
address ranges defined by the PAD's
CSADIN, CSADOUT1, and CSADOUT2
signals. This feature lets the user interface
the microcontroller to shared external
resources without requiring external
buffers and decoders. In this mode, the
port is effectively a bi-directional buffer.
The direction is controlled by using the
input signals ALE, RD/E, WR/vpp or R/W,
and the internal PAD outputs CSADOUT1,
CSADOUT2 and CSADIN (see Figure 5).
When CSADOUT1 and ALE are true, the
address on the input ADO/A7-AD7/A7 pins
flows out through Port A. (Carefully check
the generation of CSADOUT1, and ensure
that it is stable during the ALE pulse; see
Figures 22 and 23). When CSADOUT2 is

active, a write operation is performed (see
note to Figure 5). The data on the input
ADO/A7-AD7/A7 pins flows out through Port
A. When CSADIN and a read operation is
performed (depending on the mode of the
RD/E and WR/vpp or RIW pins), the data
on Port A flows out through the ADO/A7AD7/A7 pins. In this operational mode, Port
A is tri-stated when none of the abovementioned three conditions exist.

Port A in Non-Multiplexed Address/
Oata Mode
In this mode, Port A becomes the low
order data bus byte of the chip. When
reading an internal PSD301 location, data
is presented on Port A pins. When writing
to an internal PSD301 location, data
present on Port A pins is written to that
location.

Figure 5. Port A
Track Mode

WR rRfW

ADO·AD?

ALE or AS

AD8·AD15

•

A11·A15

• LATCHI--~~ PAD

CSADOUT2
(NOTE 12)

A16·A19

NOTE:

12. The expression for CSADOUT2 must Include the following write operation cycle signals:
For CRRWR = 0, CSAPOUT2 must include WR = 0.
For CRRWR = 1, CSADOUT2 must include E = 1 and R/W = 0.

Port B in Multiplexed Address/Oata
and in 8-Bit Non-Multiplexed Modes
The default configuration of Port B is I/O.
In this mode, every pin can be set as an
input or output by writing into the
respective pin's direction flip flop (DIR FF,
in Figure 6). As an output, the pin level
can be controlled by writing into the
respective pin's data flip flop (DFF, in

2·36

WAFERSCALE INTEGRATION, INC.

Figure 6). When DIR FF = 1, the pin is
configured as an output. When DIR FF =
0, the pin is configured as an input. The
controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the DFF bits by accessing the READ
DATA register. Port B pin levels can be
read by accessing the READ PIN register.

PS0301

Port Functions
(Cont.)

Individual pins can be configured as
CMOS or open drain outputs. Open drain
pins require external pull-up resistors. For
addressing information, refer to Tables 6
and 7.

Port 8 in 16·8it Non·Multiplexed
Address/Oata Mode

Alternatively, each bit of Port B can be
configured to provide a chip-select output
signal from the PAD. PBO-PB7 can provide
CSO-CS7, respectively. Each of the signals
CSO-CS3 is comprised of four product
terms. Thus, up to four ANDed expressions
can be ORed while deriving any of these
signals. Each of the signals CS4-CS7 is
comprised of two product terms. Thus, up
to two ANDed expressions can be ORed
while deriving any of these signals.

Figure 6. Port B
Pin Structure

In this mode, Port B becomes the highorder data bus byte of the chip. When
reading an internal PSD301 high-order
data bus byte location, the data is
presented on Port B pins. When writing to
an internal PSD301 high-order data bus
byte location, data present on Port B is
written to that location. See Table 9.

Accessing the I/O Port Registers
Tables 6 and 7 show the offset values with
the respect to the base address defined by
the CSIOPORT. They let the user access
the corresponding registers.

READ PIN
I
N

T
E
R
N

A
L

c

s

o

U

I
N
T
E
R
N
A
L

READ DATA
CMOS/aD
(NOTE 13)
WRITE DATA CK

D
A
T
A

D
R
DI

B

B
U

S
CSI
D

C
S

PORTB

MUX

T
U
S

~>m">

OUT

OFF

READ DIR

8

o
D
1

5

D
WRITE DIR

RESET

NOTE:

Table 6. I/O Port
Addresses in an
B·bit Data
Bus Mode

DIR
CK FF
R

CONTROL

I

13 CMOS/aD determines whether the output IS open dram or CMOS.

Register Name

8yte Size Access of the I/O Port Registers
Offset from the CSloPoRT

Pin Register of Port A

+2 (accessible during read operation only)

Direction Register of Port A

+4

Data Register of Port A

+6

Pin Register of Port B

+3 (accessible during read operation only)

Direction Register of Port B

+5

Data Register of Port B

+7

f0l.FERSCALE INTEGRATION, INC.

2·37

PSD301

Table 7. lID Port
Addresses in a
16·bit Data Bus
Mode

Word Size Access of the I/O Port
Registers Offset from the CSIOPOR1

Register Name
Pin Register of Ports B and A

+2 (accessible during read operation only)

Direction Register of Ports B and A

+4

Data Register of Ports B and A

+6

NOTES:

14. When the data bus width is 16, Port B registers can only be accessed if the BHE signal is low.
15. When accessing words, the high-order byte is connected to Port B, and the low-order byte is
connected to Port A.
16. 1/0 Ports A and B are still byte-addressable, as shown in Table 6. For 1/0 Port B register access,
BHE must be low.

Port C in All Modes
Each pin of Port C (shown in Figure 7) can
be configured as an input or output from
the PAD. As inputs, the pins are named
A16-A18. Although the pins are given
names of the high-order address bus, they
can be used for any other logic inputs to
the PAD. For example, A8-A10 can also be
connected to those pins, reducing the

Figure 7.
Port CStructure

boundaries of CSO-CS7 resolution to
256 bytes. Port C address latches can be
programmed to latch the inputs by the
trailing edge ALE or to be transparent.
Alternatively, PCO-PC2 can become
CS8-CS10 outputs, respectively, providing
the user with more external chip-select
PAD outputs. Each of the signals CS8CS10 is comprised of one product term.

++
A16j1NPUT LINE)

pca

!

LOCAL
CONF.
BIT 0

(NOTE 17)
AI6-IN

TO PAD
0-

~

I

ADDRESS
LATCH

CSS (OUTPUT LINE!

FROM PAD

I

CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL

ALE

t +
Al7 (INPUT LINE)
PCl

!

~

ADDRESS
LATCH

All-IN

CS9 (OUTPUT LINE!

TO PAD
FROM PAD

~
CONF.
BIT 1

1 t_
AIS (INPUT LINE!
PC21

ADDRESS
LATCH

AlB-IN

TO PAD

-

~~~~~~~------------FROMPAD

NOTE:

2-38

17. The CADDHLT configuration bit determines if A1B-AI6 are transparent via the latch, or if they must
be latched by the trailing edge of the ALE strobe.

WAFERSCALE INTEGRATION, INC.

PSD301

EPROM

The PSD301 has 256K bits of EPROM.
Depending on the configuration of the data
bus, the EPROM can be organized as
32K x 8 (8-bit data bus) or as 16K x 16
(16-bit data bus). The EPROM has 8 banks
of memory. Each bank can be placed in

any address location by programming the
PAD. BankO-Bank? can be selected by
PAD outputs ESO-ES?, respectively. The
EPROM banks are organized as 4K x 8
(8-bit data bus) or as 2K x 16 (16-bit data
bus).

SRAM

The PSD301 has 16K bits of SRAM.
Depending on the configuration of the data
bus, the SRAM organization can be 2K x 8

(8-bit data bus) or 1K x 16 (16-bit data
bus). The SRAM is selected by the RSO
output of the PAD.

Control Signals

The PSD301 control signals are WRlVpp
or R/VIi, ROlE, ALE, BHE/PSEN, Reset,
and A19/CSI. Each of these signals can be
configured to meet the output control signal
requirements of various microcontrollers.

falling edge of ALE latches the information
into the latches. When ALE is programmed
to be active low, a low on the pin causes
the input address latches, Port A address
latches, Port C, and A19 address latches to
be transparent. The rising edge of ALE
latches the appropriate information into the
latches. ALE is active only in the
multiplexed modes.

WRIVpp or RIW
In operational mode, this signal can be
configured as WR or R/VIi. As WR, all write
operations to the PSD301 are activated by
an active low signal on this pin. As R/VIi, the
pin works with the E strobe of the ROlE
pin. When R/VIi is high, an active high
signal on the ROlE pin performs a read
operation. When R/VIi is low, an active
high signal on the ROlE pin performs a
write operation.

ROlE
In operational mode, this signal can be
configured as RD or E. As RD, all read
operations to the PSD301 are activated by
an active low signal on this pin. As E, the
pin works with the R/VIi strobe of the
WRlVpp or RIW pin. When R/VIi is high,
an active high signal on the ROlE pin
performs a read operation. When R/VIi is
low, an active high signal on the ROlE pin
performs a write operation.

ALE or AS
ALE polarity is programmable. When
programmed to be active high, a high on
the pin causes the input address latches,
Port A address latches, and Port C
address latches to be transparent. The

BHEIPSEN
This pin's function depends on the
PSD301 data bus width. If it is 8, the pin
is PSEN; if it is 16, the pin is BHE. In 8-bit
mode, the PSEN function lets the user
work with two address spaces: program
memory and data memory (if COMB/SEP
= 1). In this mode, an active low signal on
the PSEN pin causes the EPROM to be
read. The SRAM and I/O ports read operation
are done by RD low (CRRWR = 0), or by
E and R/VIi high (CRRWR = 1).
Whenever a member of the 8031 family (or
any other similar microcontroller) is used,
the PSD301's PSEN pin must be connected
to the PSEN pin of the microcontroller.
If COMB/SEP = 0, the address spaces of
the program and the data are combined.
In this configuration (except for the
8031-type case mentioned above), the
PSEN pin must be tied high to Vee, and
the EPROM, SRAM, and I/O ports are
read by RD low (CRRWR = 0), or by E
and R/VIi high (CRRWR = 1). See Figures
8 and 9.

WAFERSCALE INTEGRATION, INC.

2-39

P50301

Table 8. Signal
Latch Status in
All Operating
Modes

AD8/A8AD15/A15

=0

8-bit data, non-multiplexed

Transparent

CDATA = 0,
CADDRDAT

=1

8-bit data, multiplexed

Transparent

CDATA = 1,
CADDRDAT

=0

16-bit data, non-multiplexed

Transparent

16-bit data, multiplexed

ALE dependent

Non-multiplexed modes

Transparent

Multiplexed modes

ALE dependent

8-bit data, PSEN is active

Transparent

16-bit data, non-multiplexed
mode, BHE is active

Transparent

CDATA = 1,
CADDRDAT

16-bit data, multiplexed
mode, BHE is active

ALE dependent

CADDHLT

A16-A19 can become logic inputs

Transparent

A16-A19 can become multiplexed
address lines

ALE dependent

ADO/AOAD7/A7

CADDRDAT

BHE/PSEN

CDATA

CADDRDAT

=0
= 1,'

CDATA
CADDRDAT

A19 and
PC2-PCO

CADDHLT

=1
=0
=1
=0

=1
=0
=1

CS

AD DRESS.

PAD
SRAM

OE
jll

INTERNAL
RD

r.

PSE!i)

-----

OE

EPROM

,
CS

I

2-40

Signal Latch
Status

CDATA = 0,
CADDRDAT

CDATA = 1,
CADDRDAT

Figure 8.
Combined
Address Space

Configuration Mode

Signal Name Configuration Bits

WAFERSCALE INTEGRATION, INC.

CS

OE

1/0 PORTS

I

PS0301

Figure 9.
B031·Type
Separate Code
and Data
Address Spaces

INTE RNAL
RD

I

I/O PORTS

•t

OE

cs

I

~

•

OE
A DDRESS~

cs
PAD

SRAM

cs
EPROM
PSEN

-

OE

In BHE mode, this pin enables accessing
of the upper-half byte of the data bus. A
low on this pin enables a write or read

Table 9.
High/Low Byte
Selection Truth
Table (in 16·Bit
Configuration
Only)

SHE

Ao

0

0

operation to be performed on the upper
half of the data bus (see Table 9).

Operation
Whole Word

0

1

Upper Byte FromlTo Odd Address

1

0

Lower Byte From/To Even Address

1

1

None

RESET
This is an asynchronous input pin that
clears and initializes the PSD301. Reset
polarity is programmable (active low or
active high). Whenever the PSD301 reset
input is driven active for at least 100 ns,

Table 10. Signal
States During
and After Reset

Signal

the chip is reset. The PSD301 must be
reset before it can be used. Tables 10 and
11 indicate the state of the part during and
after reset.

Configuration Mode

Condition

ADO/AO-AD15/A15

All

Input

PAD-PA7
(Port A)

I/O
Tracking ADO/AO-AD7/A7
Address outputs AO-A7

Input
Input
Low

PBO-PB7
(Port B)

I/O
CS7-CSO CMOS outputs
CS7-CSO open drain outputs

Input
High
Tri-stated

PCO-PC2
(Port C)

Address inputs A16-A18
CS8-CS10 CMOS outputs

Input
High

WAFERSCALE INTEGRATION, INC.

2-41

PS0301

Table 11.
Internal States
During and
After Reset

Signals

Component

All = 118

CSO-CS10

PAD

CSADIN, CSADOUT1,
CSADOUT2, CSIOPORT,
RSO, ESO-ES7

18.

}

AII.= 0 18

n/a
n/a
n/a
n/a

Data register A
Direction register A
Data register B
Direction register B
NOTE:

Contents

0
0
0
0

All PAD outputs are in a non·active state.

A191CSI
operational mode. For PSD301 states
during the power-down mode, see Tables
12 and 13.

When configured as CSI, a high on this
pin deselects, and powers down, the chip.
A low on this pin puts the chip in normal

Table 12. Signal
States During
Power-Down
Mode

Table 13.
Internal States
During
Power-Down

Signal

Configuration Mode

ADO/AO-AD15/A15

All

Input

PAO-PA7

1/0
Tracking ADO/AO-AD7/A7
Address outputs AO-A7

Unchanged
Input
A1I1's

PBO-PB7

1/0
CS7-CSO CMOS outputs
CS7-CSO open drain outputs

Unchanged
A1I1's
Tri-stated

PCO-PC2

Address inputs A16-A18
CS8-CS10 CMOS outputs

Input
A1I1's

Component
PAD

Signals

All 1's (deselected)

CSADIN, CSADOUT1,
}
CSADOUT2, CSIOPORT,
RSO, ESO-ES7

All O's (deselected)

In A19 mode, the pin is an additional input
to the PAD. It can be used as a high-order
address line or as a general-purpose logic
input. A19 can be configured as ALE

WAFERSCALE INTEGRATION, INC.

Contents

CSO-CS10

Data register A
Direction register A
Data register B
Direction register B

2-42

Condition

n/a
n/a
n/a
n/a

All
unchanged

dependent or as transparent input (see
Table 8). In this mode, the chip is always
enabled.

I'S0301

System
Applications

In Figure 10, the PSD301 is configured to
interface with Intel's 80C31, which is a
16-bit address/8-bit data bus microcontroller.
Its data bus is multiplexed with the loworder address byte. The 80C31 uses
signals RD to read from data memory and
PSEN to read from code memory. It uses
WR to write into the data memory. It also
uses active high reset and ALE signals.
The rest of the configuration bits as well
as the unconnected signals (not shown)
are application specific and, thus, user
dependent.

The configuration bits for Figure 10 are:
CRESET
CALE
CDATA
CADDRDAT
COMB/SEP
CRRWR

1

o
o
1

o or 1 (both valid)
o

All other configuration bits may vary
according to the application requirements.

Figure 10. PSD301
Interlace with
Intel's BOC31

Vee

31

-

19

ENVP
Xl

X2
9

RESET

INTO
INTl
TO
Tl
1
2
3
4
5
6
7
8

Pl0
Pll
P12
P13
P14
P1.5
P16
Pl.7

f-:L
-=

01J.1F

Microcontroller
POO
PO.l
PO.2
PO.3
PO.4
P05
P06
PO.7
P20
P21
P22
P2.3
P2.4
P25
P26
P27

AD
WR
PSEN
ALE
TXD
RXD

39
38
37
36
35
34
33
32

23
24
25
26
27
28
29
30

21
22
23
24
25
26
27
28

31
32
33
35
36
37
38
39

17
16
29
30
11
10

22
2
1
13
3

ADO/AO
AD1/Al
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

AD8/A8
AD9/A9
AD10/Al0
ADll/All
AD12/A12
AD13/A13
AD14/A14
AD15/A15

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

RD

PCO
PCl

WRNpp

BHE;PSEN
ALE
RESET

PSD301

PC2
A19/CSI

21
20
19
18
17
16
15
14
11

40
41
42
43

GND
34 12

80C31

-

WAFERSCALE INTEGRATION, INC.

2-43

PSD301

System
Applications
(Cont.)

In Figure 11, the PSD301 is configured
to interface with Motorola's 6SHC11,
which is a 16-bit address/S-bit data bus
microcontroiler. Its data bus is multiplexed
with the low-order address byte. The
6SHC11 uses E and R/IN signals to derive
the read and write strobes. It uses the
term AS (address strobe) for the address
latch pulse. RESET is an active low signal.
The rest of the configuration bits as well
as the unconnected signals (not shown)
are application specific and, thus, user
dependent.

Figure ".
PS03D1 Interface
with Motorola's
68HC11

CRESET
CALE
CDATA
CADDRDAT
COMB/SEP
CRRWR

0
0
0
1
0
1

All other configuration bits may vary
according to the application requirements.

Vee

43
45
47
49
44
46
48
50
34
33
32
31
30
29
28
27
52
51

PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC7

PDO
PD1
PD2
PD3
PD4
PD5
PEO
PE1
PE2
PE3
PE4
PE5
PE6
PE7

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

E
R!W
AS
RESET

"Xi"Ra
IRQ
MODB
MODA

VRH
VRL
XTAL

9
10
11
12
13
14
15
16

23
24
25
26
27
28
29
30

42
41
40
39
38
37
36
35

31
32
33
35
36
37
38
39

5

22

6
4
17

2
13
3

18
19
2
3

EXTAL

68HC11

In Figure 12, the PSD301 IS configured to
work directly with Intel's SOC196KB
microcontroller, which is a 16-bit address/
16-bit data bus processor. Address and
data lines multiplexed. In the example
shown, all configuration bits are set. The

WAFERSCALE INTEGRATION, INC.

t--:L

0.11lF -::-

Microcontroller
20
21
22
23
24
25

2-44

The configuration bits for Figure 11 are:

ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

E

PCO
PC1

R!WlVpp
AS

PC2
A19/CSi

i'iES"Ei'

21
20
19
18
17
16
15
14
11
10
9
8
7
6
5
4
40
41
42
43

BHE/PSEN
Vee

PSD301

GND
34 12

PSD301 is configured to use PCO, PC1,
PC2, and CSIIA19 as A16, A17, A1S, and
A19 inputs, respectively. These signals are
independent of the ALE pulse (Iatchtransparent). They are used as four
general-purpose logic inputs that take part

PS0301

System
Applications
(Cont.,

The configuration bits for Figure 12 are:

in the PAD equations implementation.

Figure 12. PS0301
Interface with
Inters
BOCI/J6KB

o
o

CRESET
CALE
CDATA
CADDRDAT
CPAF1
CPAF2

Port A is configured to work in the special
track mode, in which (for certain conditions)
PAO-PA7 tracks lines ADO/AO-AD7/A7. Port
B is configured to generate CSO-CS7. In
this example, PB2 serves as a WAIT signal
that slows down the 80C196KB during the
access of external peripherals. These 8-bit
wide peripherals are connected to the
shared bus of Port A. The WAIT signal
also drives the buswidth input of the
microcontroller, so that every external
peripheral cycle becomes an 8-bit data
bus cycle. PB3 and PB4 are open-drain
output signals; thus, they are pulled up
externally.

1
1
Don't care
1
1

CA19/CSI

o
o

CRRWR
COMB/SEP
CADDHLT
CSECURITY
CPCF2, CPCF1, CPCFO
CPACOD7-CPACODO
CPBF7-CPBFO
CPBCOD7-CPBCODO

o

Don't care
0, 0, 0
OOH
OOH
18H

+5V

ADIO

151
ADjO

'}01'F

151

ADDRESS/DATA MULTIPLEXED BUS

80C196KB

6""
=c....
~
~

~

r---::
I>----<~
L--...-'
~
T,D

L-....,;)
~

t::::S
~

8
+5V

~

XTALl

~

XTAL2

3

..-£-

~
~
16
6
5
7
4
11
10

•

,.

9

17
15
44

~
39
33
38
24
25

26
27
13

:rr

t--!L
01

'F:;:~

~

~

--..<
--..<
--..<

19
20

P30/ADO

60
59
5.
57
56
55
54
53

NMI
READY
BUSWIDTH

CDE
RESET

P31/ADl
P32/A02

POO
PO 1
P02
P03
P04
P05
P06
PO 7

P33JAD3
P34/AD4

P3 S/AD5

P3 B/AD6
P37/AD7
P401AD8

P41/AD9
P42/A010
P43/AD11
P44/A012
P4S/AD13

P20ITXD
P21/AXD
P22/EXINT
P23!T2CLK
P24!T2RST
P25/PWM

P46/AD14
P47/A015

P2 6172 UP/ON
P2 7172 CAPTR

CLKOUT
SHE/WAH

HSIO
HSll
HSI2/HSO 4
HSI3/HSO 5

WR/WAL
-

RD

ALE/ADV
INST

VAEF

VPP
ANGNO

EA

v"

V"

1

36

68

FOUR
GENERAL
PURPOSE
INPUTS

P10
P11
P12
P13
P14
P15
P16
P17

V,,

*

HSOO
HSO 1
HS02
HS03

21

}

22

PORT 1

23
30
31
32

110 PINS

AD2/A2

AD3/A3
AD4/A4
ADS/AS
AD6/A6

A07/A7

52 ADBJAB
51 AD9/A9
50

P

ADO/AD
ADl/Al

PSD301

~

~

-/1\:

48 AD12fA12
47 AD131A13
46 AD14/A14
45 AD15/A15

~
41
40
61

t±::~

ti=
~

24

AD3IA3

%

AD4/A4
ADS/AS
A06lA6

AD10/Al0

49 AD11/Al1

ADO/AO
A01/Al
AD2/A2

1'\.-

~
"-

~
~

A07/A7

AD8JA8
AD9/A9
AD10/A10
AD111Al1
AD12/A12
AD13/A13
AD141A14
ADl51A15

"

25

2.
2.

,n
32
33
~!i

37
38
~q

40
41

~

,.£1
2
22
13

,.L

44

v"

ADO/AQ
A01/Al
AD2/A2
AD3/A3
AD4/A4

ADS/AS
AD6/A6
AD7/A7
ADS/AS
AD9/A9
AD10/Al0
A011/All
AD12/A12
AD13/A13
AD14/A14
AD15/A15

T

>

01 ,F

SHARED

":'

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

PCO
PC1
PC2

BUS

.

21

20
19

,

17
16
1S
14

"/
"/

11
10
9 WAtT

~

-t=::5

•

;;>

7
6

~

i--!-

~<

i:::::5

47KQ~~47KQ
~+5V

CSl/A19
SHE/PSEN

WRN pp
AD
ALE
RESET

GND GND

44

'-----""
AL

WAFERSCALE INTEGRATION, INC.

2-45

I'SD301

Absolute
Maximum
Ratings

Symbol

Conditions

Parameter
Storage temperature

TSTG

Min

Max

Unit

-65

+150

°C

+7

V

Voltage on Any Pin

With Respect to GND

-0.6

V pp

Programming Supply Voltage

With Respect to GND

-0.6

14

V

Vee

Supply Voltage

With Respect to GND

-0.6

+7

V

>2000

V

ESD Protection
NOTE:

19. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress ratmg only and functional operation of the device at these or any other conditions
above those indicated m the operational sections of this specification IS not Implied. Exposure to
absolute maximum rating condillOns for extended periods of time may affect device reliability.

Operating Range

Recommended
Operating
Conditions

DC

Characteristics

Range

D1mperature

Vee

Tolerance

Commercial

O°C to +70°C

+5V

±5% or ±10%

Industrial

-40°C to +S5°C

+5V

±10%

Military

-55°C to + 125°C

+5V

±10%

Symbol

Conditions

Min

1YP

Max

Unit

4.5

5

5.5

V

vee

Supply Voltage

VIH

High Level Input Voltage

Vee = 4.5V to 5.5V

2

VIL

Low Level Input Voltage

Vee = 4.5V to 5.5V

0

Symbol

Parameter

VOL

VOH

2-46

Parameter

Output Low Voltage

Output High Voltage

IOL
Vee

Conditions
= 20 !lA,

= 5.5V
IOL = SmA,
Vee = 5.5V
IOH = -20 !lA,
Vee = 4.5V
IOH = -2 mA,
Vee = 4.5V

Min

V
O.S

Typ

Max Units

0.01

0.1

0.15

0.45

V

4.4

4.49

2.4

3.9

V

ISBl

Vee Standby Current
CMOS

Notes 20
and 22

Comm'l

SO

150

Military

120

250

Vee Standby Current
TTL

Notes 21
and 22

Comm'l

ISB2

O.S

1.5

Military

1.0

2

Active Current (CMOS)
No Blocks Selected

Notes 20
and 23

Comm'l

leel

35

55

Military

40

65

lee2

Active Current (CMOS)
EPROM Block Selected

Notes 20
and 23

Comm'l

35

55

Military

40

65

WAFERSCALE INTEGRATION, INC.

V

!lA
mA

mA

mA

PSD301

DC
Characteristics
(Cont.)

Symbol

Parameter

ryp

Min

Max Units

Active Current (CMOS)
SRAM Block Selected

Notes 20
and 23

Comm'l

65

105

Icc3

Military

75

120

Active Current (TTL)
No Blocks Selected

Notes 21
and 23

Comm'l

50

80

Icc4

Military

60

95

Active Current (TTL)
EPROM Block Selected

Notes 21
and 23

Comm'l

50

80

Icc5

Military

60

95

Active Current (TTL)
SRAM Block Selected

Notes 21
and 23

Comm'l

80

130

Icce

Military

90

150

III

Input Load Current

V1N = 5.5V or GND

-1

±0.1

1

~

Output Leakage Current

VOUT = 5.5V or GND

-10

5

10

/.lA

ILO
NOTES:

AC
Characteristics

Conditions

Symbol

20
21.
22.
23

rnA

mA

mA

mA

CMOS Inputs. GND ± 03V or Vee ± 0.3V
TTL Inputs· V,l .; O.BV, V,H ?:- 2.0V
AC power component IS 1 5 rnA/MHz (power = AC + DC)
AC power component IS 35 rnA/MHz (power = AC + DC).

-12
-15
·20
Units
Min Max Min Max Min Max

Parameter

T1

ALE or AS pulse width

30

40

50

ns

T2

Address set-up time

15

20

25

ns

T3

Address hold time

10

15

20

ns

T4

ALE or AS trailing edge to leading
edge of Read

12

15

20

ns

T5

ALE or AS leading edge to data valid

140

170

220

T6

Address valid to data valid

120

150

200

ns

T7

CSI active to data valid

130

160

210

ns

TB

Leading edge of Read to data valid

T9

Read data hold time

40

55
0

0

60
0

ns

ns
ns

T10

Trailing edge of Read to data high-Z

T11

Trailing edge of ALE or AS to leading
edge of Write

12

15

20

ns

T12

RD, E, PSEN, or WR pulse width

45

60

75

ns

T13

Trailing edge of Write or Read to
leading edge of ALE or AS

20

30

40

ns

35

40

45

ns

T14

Address valid to trailing edge of Write 120

150

210

ns

T15

CSI active to trailing edge of Write

130

160

200

ns

T16

Write data set-up time

20

30

40

ns

T17

Write data hold time

10

15

20

ns

T18

Port input set-up time

10

15

20

ns

T19

Port input hold time

10

20

30

ns

WAFERSCALE INTEGRATION, INC.

2-47

PSD301

AC
Characteristics
(Cont.)

Symbol

Parameter

-15
·12
·20
Units
Min Max Min Max Min Max

T20

Trailing edge of Write to port output
valid

40

T21

ADi24 or control 27 to CSOi 25 valid

20

35

25

45

30

55

ns

T22

ADi24 or control 27 to CSOi 25 invalid

20

35

25

45

30

55

ns

T23

Track mode address propagation delay:
• CSADOUT1 already true or:
• CSADOUT1 becomes true
during ALE or AS

60

ns

20

30

40

ns

40

50

60

ns

T24

Track mode address hold time

T25

Track mode Read propagation delay

T26

Track mode Read hold time

T27

Track mode Write cycle data
propagation delay

T28

Track mode Write cycle write to data
propagation delay

T29

Hold time of Port A valid during
write to CSOi trailing edge

T30

CSI active to CSOi 25 active

25

45

30

55

35

65

ns

T31

CSI inactive to CSOi 25 'inactive

25

45

25

55

35

65

ns

T32

Control 27 signal inactive to data
invalid

5

10

15

ns

15

10
20
10

20

15

20
20

40

20
30
30
30

25

50

4

2

20

30

ns
40

ns

40

ns

40

ns

60

ns

6

ns

T33

R/W active to E high

20

30

40

ns

T34

E low to R/W inactive

20

30

40

ns

T35

AS inactive to E high

15

20

25

ns

T36

Direct PAD input26 stable to leading
edge of RD, WR, or E

15

20

25

ns

NOTES:

2-48

50

24. ADI

= any address line.
25. CSOI = any of the chip-select output signals coming through Port B (CSO-CS7) or through
Port C (CSB-CS10).
26. Direct PAD mput = any of the following direct PAD input lines: CSI/A19 as transparent A19, ROlE,
WR or R/W, transparent PCO-PC2, ALE (or AS).
27. Control signals ROlE or WR or R/W

WAFERSCALE INTEGRATION, INC.

PSD301

Figure 13.
Timing of 8·Bit
Multiplexed
Address/Data Bus,
CRRWR = 0

-..

~

READ CYCLE

....

SIIA19
asCSI

7

....

36

Direct (28).:z:
PAD Input

00

STABLE INPUT
6

Multipl exed (29)
Inputs

"X;

AO/ADO- ,

WRITE CYCLE

DATA
OUT

2

.... sl-

3

rh

32

36

~~

.....
14

1,--14

~

~
.~

\

RDIE as RD

~

DATA
IN

f-

ADDRESS B
3

~

t'""""""'\

Acti ve Low'
ALE \...~

1- 32

1m KXXX

STABLE INPUT

:XXX XXX X

~-

.f2+

...

'XX XXXX

1-32

4

-- ---

15

~

ADDRESS A

~

Active High
ALE'

~

-

IXXXXJ( IXXll XXX
6

A7/AD7

32 ...

XX; 1 , - - -

~v-

~

11

~

I\-

~

f-I

5

\

BHEIPSEN
as PSEN

~

~

WRI VPP or

RiW as WR

~

~

~

x.xxxx,

Anyo f PAO- \
PA7 as 1/0 Pin ,.

XXX X

Anyo f PBO- \
PB7 as 110 Pin ,.

XXXXXXXXX

~I

Any 0 fPAO- _--,.
PA7 Pins
asAddress
'1
Outputs

19

~

~

INPUT

IX X X X X XXJ\MX XXX XXX.)\)\;

OUTPUT

INPUT

X X X X X X X X X X X X X X X X.X.)\)\;

OUTPUT

~
ADDRESS A

ADDRESS B

See referenced notes on page 2-58.

WAFERSCALE INTEGRATION, INC.
---

---~-

----

-----~

,~--,---------------------

----~--

---

2-49

----------------

'S0301

Figure 14.
Timing of 8·Bit
Multiplexed
Address/Data Bus,
CRRWR = 1

...

READ CYCLE

WRITE CYCLE

-i
32

~

SI/A19
asCSI

7

32

15

- XX ~

36

36

-32

DIrect(28):Z:
PAD Input

00

STABLE INPUT

STABLE INPUT

)C

XX XXX X
~32

IXXX XXX
,---

XXXXX XX) IXXX

~

OATA
OUT

ADDRESS A
2

14

~r-

.... al-

3

Active High r h
ASI

.XXX IXXXX

~

6

AO/ADOA7/AD7

i--

14

6

Multiple xed (29)
In puts

-

~

3

~

.f2.,.
35
12

33

f--..

~

OATA

IN

~

h

4

Acti ve Low'
AS

r-

ADDRESSB

xx:

~ II

f-.I

f\33

34

L

35

J

34

RDI E as E
5

13

~
WRN PP or

RNV asRiW

[XXXXXXX

ir

.XXXXX
~

~

20

I--

Any 0 I PAO- \
PA7as 1/0 Pin'"

XXXXXXXXX

INPUT

XXXXXXXXXXXXXXXX :XX

OUTPUT

Any 0 I PBO- \
PB7 as 1/0 Pin'"

XXXXXXXXX

INPUT

IXXXXXXXXXXXXXXXXXXX

OUTPUT

Any 0 IPAOPA7 Pins
asAddress
Outputs

-

~

23

See referenced notes on page 2-58.

2·50

i---

WAFERSCALE INTEGRATION., INC.

ADDRESS A

ADDRESS B

PSD301

Figure 15.
Timing of 16·8it
Multiplexed
Address/Data 8us,
CRRWR = 0

...

READ CYCLE

=-----'

CSI/A19
asCSI

--

7

--

36

DIrect(28)X
PAD Input

00

STABLE INPUT
6

Multiple xed(29)~
Inputs

XXXXX xX)

_

DATA
OUT

ADDRESS A
2

ALEI

--

3

Irh

Actlv e High

~I

4

'XJJ lXXXX

)eX ~

1- 32

STABLE INPUT
14

xxx

\

~r-

ADDRESS B
2

5

3

-,

foII~

...;

DATA

IN

~

Any 0 f PAO- \
PA7 as 1/0 Pm ,.

X")
I

DC

~ Ir~

--.J

I~

IL
.F

13

~
~

I~

11

W~ VPP or

Any 0 f PBOPB7 as 1/0 Pm

~

f--'

R/W asWR

I~

:XXX xxxx

.2.

-

v----

:XXX XXXX
14

~4

RDIE as RD

-- 1mKXXX

36
_32

8 __

Actl ve Low'
ALE I'-~

I-

15

lxxxx IX X) )()(~

h

AO/ADOA15 IAD15

32
--

~

6

BHEIPSE~~
a sBHE ~

WRITE CYCLE
32

~

19
~

I-20

I--

:XXXXXXXXX

INPUT

OIXXXXXXXXXXXXXXXX)(~XX

OUTPUT

.XXXXXXXXX

INPUT

:~IXX

XX XXXXX XXXXXX XX.XX

OUTPUT

~.I

Any 0f PAO- -----.
PA 7 Pms
.,
as Address
Outputs

~
ADDRESS A

ADDRESS B

See referenced notes on page 2-58.

WAFERSCALE INTEGRATION, INC.

2-51

'S03ot

Figure 16.
Timing of 16·Bit
Multiplexed
Address/Data Bus,
CRRWR = 1

~

-

READ CYCLE

WRITE CYCLE

-~
32

SIIA19
asCSI

7

32

' XX I

15

36

Direct(28l
PAD Input

Multiple xed(29l
In puts

:X ~

36

ISTABLE INPUT
6

x:

~32

xx XX

_32

~~

XXX IlXXX

STABLE INPUT
14

1.---

IXXX

XXXX

~

6

BHE/PSE~X:
asBHE

AO/ADO- A15 /AD15

--

2

-

3

Active High ~~
AS

4

DATA
OUT

~-

3

35
12

XXX

~

DATA

IN

~

h

~
33

XX

r-

ADDRESS B

12...

8i-

~~

Acti ve Low
AS

XXX

14

---I-<~AD ~

AO/ADO- ----,
A7/AD7 ~

ALE

-'

J

......~-+t'l

~

~TA

I

31

2

I

ADDRESS

)--

1'--,-------rI

W~~1:N

I

V-h

v-r---.

f4~

~r2+

I'-~

~+--./

r--

--I-

I'-------t---t'~

"""""'\
orALE

.I

RD/E as RD

4

12

_\.

I

\

DATA IN

I
_130,33)
CSOi

-

32 __

11

-~

)-

ADR

OUT

12

1_271-~

lI-----+--<{

DATA OUT

~

----------------------.,,~

~

See referenced notes on page 2-58,

WAFERSCALE INTEGRATION, INC.

2·57

PSD301

Figure 23.
Port A as
ADO-AD7 Timing
(Track Mode),
CRRWR = 1
32

READ CYCLE

-

-32

-

WRITE CYCLE

Direct(28,31)~~'T--=::-::::-::::-::-:----t\IrT-----::=:-:::-:::::::::-::----t\lI\J~7\T
PAD
INPUT STABLE
INPUT STABLE
,XXXX

21

Input

Multiplexed (32,34)~")~oocvv\lr-::IN-:P~U::T:-:S::T:-:A-:B-:-LE::-UI:
X, Xii,X';}Xv,~
X~~
X, XJtlXiit,'O\J
X~I~N::P-;-:U=T-:::S::T-:-A::BL:-:E:--1X';},VX~'O'\X,XiI,X';}~XV,~X,'UtXi'D~X\7\
PAD Inputs

2

,I

3

'I

AO/ADOA7/AD7

~I-

26_

-~r-~~~~--~~~
ADDRESS
r~TA

vt----l

Irn
AS

--'

~r--:.

ADDRESS

I'------------+--~~

I"'~

1'--

1}'f·flTEN I

- 1-

32

1/\

1~------------+_--fV

-,
35

or AS

12
33

33

v

RD/E as E

32WRNPPor
RiWas R/W

XXX :X :XXX
-e 23 ~

PAD-PA7

-k

JIXX [XXXX
24

I---

-e 23 t-

J

\

DATA
IN

,

I-

~

~

IADR'
IOUTI

II

\

r-<

I ADR'
I OUT I

-- 271-

~

DATA
OUT

__ (30,33)
CSOi

NOTES:

2·58

2B. Direct PAD input = any of the following direct PAD Input lines: CSI/A19 as transparent A19,
RD/E, WR or R/W, transparent PCO-PC2, ALE In non-multiplexed modes.
29, Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS): AO/ADO-A15/AD15,
CSi/A19 as ALE dependent A19, ALE dependent PCO-PC2.
30. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or through Port C
(CSB-CS10).
31. CSADOUT1, which Internally enables the address transfer to Port A, should be derived only from
direct PAD input signals, otherwise the address propagatIOn delay is slowed down.
32 CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively,
can be derived from any combination of direct PAD inputs and multiplexed PAD inputs.
33. The write operation signals are Included in the CSOi expression.
34. Multiplexed PAD Inputs: any of the following PAD inputs that are latched by the ALE (or AS) in
the multiplexed modes: A11!AD11-A15/AD15, CSIIA19 as ALE dependent A19, ALE dependent
PCO-PC2.
35. CSOI product terms can include any of the PAD input signals shown in Figure 3, except for reset
and CSI.

WAFERSCALE INTEGRATION, INC.

~

PS0301

Table 14. Pin
Capacitance 36

Symbol
CIN

Capacitance (for input pins only)

VIN = OV

Typical 37 Max Units
4

6

pF

COUT

Capacitance (for input/output pins)

VOUT = OV

8

12

pF

CvPp

Capacitance (for WR/vpp or R/W/Vpp)

Vpp = OV

18

25

pF

NOTES:

Figure 24.
AC Testing
Input/Output
Waveform

Conditions

Parameter

36. This parameter is only sampled and is not 100% tested.
37. Typical values are for TA = 25°C and nominal supply voltages

'::=x

fJ

Figure 25.
AC Testing
Load Circuit

--

2.01 V

~ 1950
i>

DEVICE
UNDER
TEST

I

....... C L =30pF
(Including
scope and Jig

-=-

Erasure and
Programming

To clear all locations of their programmed
contents, expose the device to ultra-violet
light source. A dosage of 15 W-second/cm 2
is required. This dosage can be obtained
with exposure to a wavelength of 2537A
and intensity of 1200 I!W/cm2 for 15 to 20
minutes. The device should be about 1
inch from the source, and all filters should
be removed from the UV light source prior
to erasure.
The PSD301 and similar devices will erase
with light sources having wavelengths
shorter than 4000A.. Although the erasure
times will be much longer than with UV
sources at 2537A, exposure to fluorescent
light and sunlight eventually erases the

capacitance)

device. For maximum system reliability,
these sources should be avoided. If used
in such an environment, the package
windows should be covered by an opaque
substance.
Upon delivery from WSI, or after each
erasure, the PSD301 device has all bits in
the PAD and EPROM in the "1" or high
state. The configuration bits are in the "0"
or low state. The code, configuration, and
PAD MAP data are loaded through the
procedure of programming
Information for programming the device is
available directly from WSI. Please contact
your local sales representative.

WAFERSCALE INTEGRATION, INC.

2·59

PSD301

PSD301
Pin
Assignments

44-Pin
PLOCCI
CLOCC
Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Ordering
Information

2-fjIJ

44-Pin
CPGA
Package

Name
BHE/PSEN
WRlVpp or RiW
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
GND
ALE or AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
RD/E

Part Number

Speed
(ns)

PSD301-12J
PSD301-12L
PSD301-12X
PSD301-15J
PSD301-15L
PSD301-15LM
PSD301-15LM
PSD301-15X
PSD301-15XM
PSD301-15XMB
PSD301-20J
PSD301-20L
PSD301-20LM
PSD301-20LMB
PSD301-20X
PSD301-20XM
PSD301-20XMB

120
120
120
150
150
150
150
150
150
150
200
200
200
200
200
200
200

WAFERSCALE INTEGRATION, INC.

A5

~
B4
A3
B3
A2
B2
B1
C2
C1
D2
D1
E1
E2
F1
F2
G1
G2
H2
G3
H3
G4

Package
Type
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin

PLDCC
CLDCC
CPGA
PLDCC
CLDCC
CLDCC
CLDCC
CPGA
CPGA
CPGA
PLDCC
CLDCC
CLDCC
CLDCC
CPGA
CPGA
CPGA

44-Pin
PLDCCI
CLDCC
Package
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Name
ADO/AO

44-Pin
CPGA
Package

PCO
PC1
PC2

H4
H5
G5
Hs
Gs
H7
G7
Ga
F7
Fa
E7
Ea
Da
D7
Ca
C7
Ba
B7
A7
Bs

A19/CSI

As

Vee

B5

AD1IA1

AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD10/A10
GND

AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

WSI
Package Operating
Drawing Temperature Manufacturing
Range
Procedure
J2
L4
X2
J2
L4
L4
L4
X2
X2
X2
J2
L4
L4
L4
X2
X2
X2

Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Military
Military
Comm'l
Military
Military
Comm'l
Comm'l
Military
Military
Comm'l
Military
Military

Standard
Standard
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C

PSD301
System

WAFERSCALE INTEGRATION, INC.

Development Tools

System
Development
Tools

The PSD301 features a complete set of
System Development Tools. These tools
provide an integrated, easy-to-use software
and hardware environment to support

PSD301 device development. To run these
tools requires an IBM-XT, -AT, or
compatible computer, MS-DOS 3.1 or
higher, 640K byte RAM, and a hard disk.

Hardware

The PSD301 System Programming
Hardware consists of:

r:I WS6014 44-pin CPGA Package Adaptor
The MagicPro Programmer is the common
hardware platform for programming all WSI
programmable products. It consists of an
IBM-PC plug-in programmer board and a
remote socket adaptor.

r:I WS6000 MagicPro Memory and PSD
Programmer

r:I WS6013 44-pin LCC Package Adaptor
(for CLDCC and PLDCC packages)

Software

The PSD301 System Development Software
consists of:

r:I WISPER, WSI's Software Environment
r:I MAPLE, the PSD301 Location Editor
Software

r:I MAPPRO, the Device Programming

The configuration of the PSD301 device is
entered using MAPLE software. MAPPRO
software uses the MagicPro programmer
and the socket adaptor to configure the
PSD301 device, which then can be used.
The development cycle is depicted in
Figure 26.

Software

Support

WSI provides a complete set of quality
support services to registered System
Development Tools owners, including:

r:I Design assistance from WSI field

r:I 12-month software updates

r:I 24-hour electronic bulletin board for

application engineers and application
group experts
design assistance via dial-up modem.

Training

WSI provides in-depth, hands-on workshops
for the PSD301 device and System
Development Tools. Workshop participants
learn how to program high-performance,

user-configurable mappable memory
subsystems. Workshops are held at the WSI
facility in Fremont, California.

WAFERSCALE INTEGRATION, INC.

2-61

PS0301

Ordering
Information System
Development
Tools

PS0301·GOLO

WS6013

U
U
U
U
U
U
U

U 44-pin LCC Package Adaptor for CLOCC

WISPER Software

and PLOCC Packages

MAPLE Software

U Used with the WS6000 MagicPro

User's Manual

Programmer

WSI Support
WS6000 MagicPro™ Programmer

WS6014

WS6013 44-pin LCC Package Adaptor

U 44-Pin CPGA Package Adaptor, Used
with WS6000 MagicPro Programmer

Two PS0301-15L Samples

WSI Support

PS0301·SILVER
U
U
U
U

Support services include:

WISPER Software

U 12-month Software Update Service
U Hotline to WSI Application Experts
U 24-hour access to WSI Electronic Bulletin

MAPLE Software
User's Manual
WSI Support

Board

WS6000

WSI Training

U MagicPro Programmer
U IBM-PC© plug-in Adaptor Card
U Remote Socket Adaptor

U Workshops at WSI, Fremont, CA

Figure 26.
PSD301
Development
Cycle

U For details and scheduling, call PSO
Marketing (415) 656-5400

IBM PLATFORM

Menu Selection

Configuration Data

Programming Data

MagicPro Hardware

2·62

WAFERSCALE INTEGRATION, INC.

Programmable System™Device
WAFERSCALE INTEGRATION, INC.

PAC1000 Introduction

User·Configurable
Microcontroller
Overview

In 1988 WSI introduced a new concept in
programmable VLSI: the Programmable
System™ Devices (PSD). The PSD is
defined as a family of User-configurable
system level building blocks on-a-chip
enabling quick implementation of application
specific controllers and peripherals. The
first generation PSD series includes the
MAP168, a User-Configurable Peripheral
with Memory; the SAM448, a UserConfigurable Microsequencer; and the
PAC1000, a User-Configurable
Microcontroller.

The PAC1000 architecture is flexible and
enables the system designer to customize
the PAC1000 to optimize application
performance. The PAC1000 is composed
of three basic sections: a CPU for data
processing, a programmable instruction
control unit that determines the next
address to the microcode store through
polling condition codes or responding to
interrupts, and a host interface to
asynchronously load data from the host.
Registered inputloutputs are used to
synchronize with the system.

The PAC1000 user-configurable highperformance microcontroller is the first of
a generation of products intended for
applications in high-end embedded control
where high-speed data processing, interface
or control is needed. The PAC1000 replaces
a board full of discrete components such
as standard logic, FIFO, EPROM for
microcode store, ALU, SEQUENCER,
register files and PALlPLD/PGA. To shorten
the time-to-market for the system designer,
a high-level software development language
is used. This contrasts with the myriad
state-machine entry, schematic entry, and
place and route tools that would be
needed for a discrete design using PAL,
PLD, PGA or gate arrays.

As a result of integrating logic and EPROM
memory into the PAC1000 and defining a
high-level language for programming both,
time-to-market and board space is reduced
and reliability increased. The PAC1000 is
currently used in applications such as
Intelligent DMA controller, FDDI buffer
controller, Frame buffer controller, LAN
communications controller, disk controller,
and 1/0 controller. For further details on
the PAC1000 see Application Note 10.

WAFERSCALE INTEGRATION, INC.

2·63

Contents

2·64

Features ...................................................................................................................................... 2-65
General Description .................................................................................................................... 2-66
Architectural Overview ................................................................................................................ 2-68
Operational Modes ...................................................................................................................... 2-70
Host Interface .............................................................................................................................. 2-71
FIFO ..................................................................................................................................... 2-71
Data I/O Registers ................................................................................................................ 2-73
Program Counter .................................................................................................................. 2-73
Status Register ..................................................................................................................... 2-73
Control Section ........................................................................................................................... 2-75
Parallel Operations ............................................................................................................... 2-75
Program Memory ................................................................................................................. 2-76
Security ................................................................................................................................ 2-76
15-Level Stack ..................................................................................................................... 2-76
Program Counter .................................................................................................................. 2-76
Loop Counter ....................................................................................................................... 2-77
Debug Capabilities ............................................................................................................... 2-77
Breakpoint Register ....................................................................................................... 2-77
Single Step .................................................................................................................... 2-77
Condition Codes ................................................................................................................... 2-77
User-Specified Conditions ............................................................................................. 2-78
CPU Flags ..................................................................................................................... 2-78
FIFO Flags .................................................................................................................... 2-78
Stack-Full Flag .............................................................................................................. 2-78
Interrupt Flag ............................................................................................................................... 2-78
Data Register Read Flag ............................................................................................... 2-78
Counter Flag .................................................................................................................. 2-78
Case Logic ........................................................................................................................... 2-79
Case Instructions ........................................................................................................... 2-79
Priority Case Instructions .............................................................................................. 2-79
Interrupt Logic ...................................................................................................................... 2-79
Interrupt Mask Register ................................................................................................. 2-80
Output Control ...................................................................................................................... 2-81
Counters ..................................................................................................................................... 2-81
Address Counter .................................................................................................................. 2-81
Block Counter ....................................................................................................................... 2-82
Central Processing Unit .............................................................................................................. 2-82
Arithmetic Operations .......................................................................................................... 2-85
Logic Operations .................................................................................................................. 2-85
Shift Operations ................................................................................................ '" ................ 2-85
Shift Right ...................................................................................................................... 2-85
Shift Left ........................................................................................................................ 2-85
Rotate Operations ............................................................................. '" ................................ 2-86
Multiple Precision Operations .............................................................................................. 2-86
I/O and Special Functions ........................................................................................................... 2-86
Configuration Registers .............................................................................................................. 2-88
Control Register ................................................................................................................... 2-88
I/O Configuration Register ................................................................................................... 2-90
Mode Register ...................................................................................................................... 2-91
State Following Reset ................................................................................................................. 2-92
Electrical and Timing Specifications ............................................................................................2-94
Pin Assignments ....................................................................................................................... 2-100
Instruction Set Overview ........................................................................................................... 2-104
System Development Tools ...................................................................................................... 2-109
Hardware ............................................................................................................................ 2-109
Software ............................................................................................................................. 2-109
Support ............................................................................................................................... 2-109
Training .............................................................................................................................. 2-109
Ordering Information-PAC1000 .............................................................................................. 2-110
Ordering Information-System Development Tools ................................................................. 2-111

WAFERSCALE INTEGRATION, INC.

='====
~iE
... --------!i-.=-ii~ ==

Programmable System™Device

~

!!r

---~~

-

WAFERSCALE INTEGRATION, INC.

PAC1000

Preliminary

Use,-Configurable
MiclOcontroller

Features

Cl

First Generation Programmable System
Device (PSD)

Cl

Address Generation-Up To 4 Mbytes
Address Space

Cl

High-Performance User-Configurable
Microcontroller-20 MHz Instruction Execution, Output Port, and Address Bus

Cl

High-Level Development Toois-System
Entry Language, Functional Simulator,
and Device Programmer

Cl

Single-Cycle Control Architecture-One
Cycle Per Instruction

Cl

Re-Programmable Program StoreOn-Board 1Kx64-Bit EPROM

Cl

16-bit CPU-Arithmetic Operations,
Logic Operations, 33 General-Purpose
Registers

Cl

Two Operating Modes-Host Processor
Peripheral or Stand-alone Controller

Cl

Security-For EPROM Program Memory

Figure 1.
PAC1000 Block
Diagram

I

CK

RESET

~

~

Cs

RD WR

HD[150]

HADI50]

I

Configurabon
Registers

I

Host Interface

r

i

•

•

Control Section

I SecUrity Bit I

I

lKx64 EPROM

I

CPU

I

Loop Counter

I Breakpoint Register I
I Program Counter I

15-Level
Stack

~

Case LogiC
User
Output

Condition-Code
LogiC

I

Interrupt
LogiC

~

Block Counter

Address Counter

~

I
OUTCNTL[15.0]

CC[7·0]

1/0 & Special
Function Port

f

~

INT[3·0]

1/0[70]

J

II

~

1

Address/Data
Port

f

~

J

I
-:!:-

ADD[15.0]
1738 01

WAFERSCALE INTEGRATION, INC.

_ _ _ _

0 _ _ _ _ _•

_

2-65

fJ

PAC1000

General
Description

In 1988 WSI introduced a new concept in
programmable VLSI, Programmable System
Devices (PSD). The PSD family consists of
user-configurable system-level building
blocks on-a-chip, enabling quick implementation of application-specific controllers and
peripherals. The first generation PSD series
includes the MAP168, a User-Configurable
Peripheral with Memory; the SAM448, a
User-Configurable Microsequencer; and the
PAC1000, a User-Configurable Microcontroller.
The PAC1000 User-Configurable Microcontroller is based upon an architecture that
enables it to execute complex instructions in
a single clock cycle. Each PAC1000 instruction can perform three simultaneous operations: Program Control, CPU functions, and
Output Control, as shown in Figure 2. The
PAC1000 can also perform address generation or event counting simultaneously with instruction execution. The PAC1000 is also
capable of performing a conditional test on

Figure 2. SingleCycle Control
Architecture

up to four separate conditions and multi-way
branching in a single cycle.
The PAC1 000, with its System Development
Tools, matches the development cycle and
ease of use of any standard microcontroller.
The high performance and flexibility of the
PAC1 000 were previously available only to
designers who could afford the long development cycle, high cost, high power, and large
board space requirements of a building-block
solution (i.e., Sequencer, Microcode Memory,
ALU, Register File, PALs, etc.)
The unique capabilities of PAC1000 are
easily utilized with System development
tools, which include a PACSEL C-like System
Entry Language, a PACSIM Functional
Simulator, and a MagicPro™ Device Programmer. All System Development Tools are
PC-based and will operate on an IBM-XT,
AT, PS2 or compatible machine. For more information, contact your nearest WSI sales
office or representative.

WR

co~:~~ -~:---r--co-n-'tro""l-un-,t--'
Interrupts

-~~

HD[1S:0] HAD[1S0]

28

1K x e':'~PROM

CPU

Next Instruction
Definition
Instruction Register

ClK

~o~~: ;u~p';;: ~;U CPU Operation
Definition

20

OC[1S'0]

1/0[7.0]

ADD[1S:0]

Important Features:

• One cycle per instruction
• 20 MHz Instruction execution rate
• Every instruction executes 3 parallel operations (Control, Output, CPU)

2·68

WAFERSCALE INTEGRATION, INC.

1738 02

PAC1000

Table 1. Pin
Description

Signal

I/O

Oescription

HD[15:0]

I/O

Host Data. PAC1000 Data I/O Port via the Host Interface. Can also be configured to generate 16-bit address or status. Can serve as a general-purpose Data
110 Port.

HAD[5:0]

I/O

Host Address. Can be configured to output the lower
six bits of the 22-bit Address Counter; can be used as a
Host Interface function address, or as a generalpurpose 16-bit port.

CS

Chip Select (active low). Used with RD and WR to
access the device via the Host Interface.

RD

Read Enable (active low). Used with CS to output Program Counter, Status Register, or Data Output Register to HD[15:0] bus lines.

WR

Write Enable (active low). Used with CS to write HD
Bus data via the Host Interface into the PAC1 000
FIFO.

CK

Clock.

CC[7:0]

Condition Codes. Condition-code inputs for use with
Call, Jump, and Case instructions.

INT[3:0]

Interrupts. General-purpose, positive-edge-triggered
interrupt inputs.

RESET

Asynchronous Reset (active low). Resets Input/Output
registers and counters, tri-states all 110, and sets the
Program Counter to O.

9

OUTCNTL[15:0]

0

Output Control. User-defined Output Port. May be programmed to change value every cycle.

ADD[15:0]

I/O

Address Port. Outputs data from Address Counter or
Address Output Register when configured as an
output. When configured as an input, reads data to
Address Input Register.

1/0[7:0]

I/O

Input or Output Port. Individually configurable bidirectional bus. As simple I/O, outputs come from the I/O
Output Register, and inputs appear in the I/O Input
Register. As special I/O functions, provides status,
handshaking, and serial I/O. Alternatively, these signals
can be used to extend the OUTCNTL or ADD lines.

WAFERSCALE INTEGRATION, INC.

2·67

PAC1000

Architectural
Overview

The PAC1000 is a user-configurable microcontroller optimized for high-performance
control systems. The primary architectural
elements, shown in Figure 3, are the Control
Section, 16-bit CPU, Host Interface, 16-bit
Address Port, 16-bit Output Control, 8-bit I/O
Port, and Configuration Registers.
The PAC1000 can be used as a stand-alone
microcontrolier or as a peripheral to a host. In
the lalter case, the Host Data (HD) and Host
Address (HAD) buses, together with the CS,
RD, and WR pins allow for direct connection
to a host bus. User-defined commands to the
Control Section or data to the CPU can be
loaded through the Host Interface.
In the stand-alone mode, the Host Interface
ports can be used as additional address, data
or I/O ports using the Data Output Register
(DOR) and Data Input Register (DIR). The
ADD port can be used to generate addresses
through the Address Output Register (AOR)
or the Address Counter. A DMA channel can
be formed on the Host Interface using these
and the Block Counter (BC) register. In
addition, the ADD port can be used as a data
bus or an I/O port, depending on how the
chip is configured. Each pin in the I/O port
can be configured individually as input,
output, or special function. The special
functions allow the control of internal
PAC1 000 elements (counters, 110 buffers) by
other board elements.
The 16-bit CPU is highly parallel and can
operate on operands from the 32x16-bit

2·68

WAFERSCALE INTEGRATION, INC.

register file, miscellaneous register (AOR,
AIR, DOR, DIR, Q, etc.), or constants loaded
from the internal program-store EPROM.
The internal and external operations of the
PAC 1000 are controlled by the Control
Section. The 16 Output Control (OC) lines
are general-purpose outputs. Each of them
can be changed independently every clock
cycle. They provide a very fast means to
control various processes outside the chip.
In every clock cycle, one instruction is
executed. Each instruction consists of up to
three operations in parallel:
D

Instruction Fetch-the next instruction is
fetched from the 1Kx64 EPROM by the
Program Control.

D

Execution-the CPU executes an instruction.

D

Output-placed on the Output Control
(OC) lines.

Program flow can be changed through the
condition-code inputs in one clock cycle or
through the interrupt inputs after two clock
cycles. Single-cycle 16-way branches can be
done using the Case instruction, which
samples four condition codes per cycle.
Nested loops and subroutines can be carried
out with the 15-level stack and the loop
counter. The chip configuration can be
changed in any cycle by loading the Configuration Register using the Program Control
instruction portion.

PACtOOO

Figule3.
Detailed
Block Diagram

HD

HAD

I

9

Register
File +

a Register
ALU
CPU

VO Configuration
Internal
INTR
4
INTR

Control

~

Configuration RegISters

Mode

16

16

16

16

oc

WAFERSCALE INTEGRATION, INC.

2-69

PAC1000

OperatiDnal
Modes

The two basic modes of operation for the
PAC1000 are either as a memory-mapped
peripheral (Figure 4) or as a stand-alone
controller (Figure 5).

In the peripheral mode, the host processor
can asynchronously interface with the
PAC1000.

Figure 4.
Peripheral Mode
Address
Host Processor

Memory

Data

,-------- -- --------,
PAC1000

~:

,
,
,

~:

~

CPU
Host
Interface
Control

,
,

~:

--,,

,
,
,
Data Path
,
Element,
,
, Control
High Speed
,
Process,
,
Fast Bus, Etc.
,
,
,
,
, Status/Interrupts

I

,
,

I . _ _ _ _ _ _ _ _ _ _ _ _ .. _ .............. ..

1738 04

Figure 5.
Stand-alone Mode
Address

Memory

Vcc

CS
RD
WR

, .. - .... ------------- ..,
PAC1000
,
,
,
CPU
,
Host and
,
,
Data
,
Interface
,
Control
,
,
,
,
,
,

-- -----

------------.1
Control

Data

Data Path
Element,
High Speed
Process,
Fast Bus, Etc.

Status/Interrupts
1738 05

2·70

WAFERSCALE INTEGRATION, INC.

PACtOOO

Host Interface

The Host Interface section of the PAC1000,
shown in Figure 6, includes the Input Command/Data FIFO, Input/Output Data Registers, and the Status Register.

FIFO
When the PAC 1000 serves as a peripheral to
a host, the FIFO is used to asynchronously
load commands or data into the PAC1000. In
order to write into the FIFO, CS and WR
must have low-to-high transitions. The
information written into the FIFO is specified
by the 16-bit Interface Data bus (HD) and the
6-bit Host Address bus (HAD). Since the
FIFO is used only to buffer data and commands from a host, it is inoperative when the
PAC1000 is in stand-alone mode.

Figure 6.
Host Interface
Architecture

Bit five of the HAD bus specifies whether the
input to the FIFO is command (HADS=1) or
data (HADS=O). HADS is connected to the
FICD internal Condition Code that can be
sampled by the Control Section. If a command is written, then the lower 10 bits of the
HD bus are used as the branch address for
one of the 1024 locations in the Program
Memory EPROM. At that location a user
defined command or subroutine should exist
which executes the needed operation. If the
information is data, then the lower S bits of
the HAD bus specify which CPU register is to
be loaded from the HD bus.
This method of operation allows the host to
access the PAC1000 as a memory-mapped
peripheral.

HAD[O 51

HD[O"151

Host
Interface

Decoder
16

,-.,-----------'

ACL

Decoded Signals

16
DIR

DOR

Data
Input
Register

Data
Output
Register

Status
Register

8 x 16 Command
and Data

8 x 5 Register
POinter

8x1

FICD

16

16
Internal Flags

Internal Bus

To Register File
1738 06

WAFERSCALE INTEGRATION, INC.

2·71

PAC1000

Host Interface
(CDn't)

Table 2.
Host Interface
Functions

An example of FIFO usage is shown in
Figure? When command or data information
is available in the FIFO, the FIFO Output
Ready (FIOR) interrupt (interrupt 5) triggers.
If the FIOR interrupt is masked, then the
FIOR status may be polled under program
control. If HAD5 equals 1, the branch address location specified by MOVE is the
Program Memory Address which contains the
user specified instruction or sub-routine
which executes the command. A JUMP or
CALL FIFO control instruction performs a
jump or call to the location specified by
MOVE. If HAD5 equals 0, an RDFIFO
instruction can transfer the FIFO contents
into the register specified by HAD[4:0].
For further explanation, refer to the diagram
below. Beginning at the location specified by
MOVE, a user defined program exists which
is going to load data into CPU registers 0,1,2,

-cs

1f1)

WR

and 3 in four consecutive cycles from the
next four FIFO locations. If one of the four
FIFO locations contains a command
(FICD=1), interrupt level? occurs (highest
level). Loading a command into a CPU or
other data register is not allowed. If this
occurs, FIXP (FIFO exception) will be generated.
Following the execution of this routine, the
Control Section is ready for its next instruction.
The FIFO drives three internal flags which
can also be programmed to interrupt the
PAC1000. They are:
r:l FiTR (FIFO full) and FIXP (FIFO exception), which drive INT?
r:l FIOR (FIFO output ready), which drives
INT5.

HA05

HAO[4:0]

HO[15:0]

0

Register

Data

0

0

0
0
0

0
0
0

0
0

X
00100
00011

Command
X
X

0
0

0
0

0
0

00010
00001

0

0

0

00000

Data
Data
Data

FunctiDn
Write data to FIFO

Address

2·72

WAFERSCALE INTEGRATION, INC.

Write command to FIFO
Reset FIFO
Reset status register
Read program counter
Read status register
Read data output register

PAC1000

Host Interface

Data I/O Registers

(Con't)

Input and Output Data Registers are used to
communicate with the Host Data (HD) bus.
CPU Registers may be loaded directly from
the Data Input Register (DIR) without passing
through the FIFO. Similarly, the PAC1 000
may be read via the Data Output Register
(DOR).

the Program Memory address bus. It can also
be used to drive external memory devices for
expansion of the Control Port.

Status Register

Program Counter

The Status Register (SR), shown in Figure 8,
monitors all internal status. Status bits can be
set only by program execution. The SR can
be read or cleared as specified in the Host
Interface Functions table.

The Program Counter may be read via the
Host Data bus. This allows a host to monitor

All SR flags are active high (1) and are
latched at the rising edge of the clock.

Figure 7.
ExampleD'
FIFO Block
Diagram and
Usage

l

Write pOinter]=;

FICDto
Condition Code
Multiplexer

HAD5

HAD[4'0]

HD[15'10]

HD[9'0]

x

x

x

x

x

x

x

x

X

X

X

X

0

R3 Address

Data to CPU

0

R2 Address

Data to CPU

0

R1 Address

Data to CPU

0

RO Address

Data to CPU

1

X

+----:l

X

I I

I

I

I
IHAD[4:0]

~

Read

pOinte~

I
IHD[15:0]

IHD[9:0]

Command to
Control Section
when FICD = "1"

MOVE

Data to CPU
when FICD = "0"
Register Address
to CPU Register

FICD = 1 Command (actually a branch) to the Control Section
FICD

= 0 Data to CPU Register

WAFERSCALE INTEGRATION, INC.

1738 07

2-73

PAC1000

Host Interface
(Con't)

STAT11-(DBB) Security Bit, set when
security is active:
1= Security active.
0= No security.
STAT10-WSI Reserved.

STAT9-(FIXP) FIFO Exception, set when
the CPU receives a command or Control
Section receives data:
1= Command or data received.
0= No exception occurred.
STATS-(FIIR) FIFO-Input Ready, set when
there is at least one vacant location in the
FIFO:

1= FIFO ready for input.
0= FIFO not ready for input.
STAT7-(CY) Carry Flag, set when a carry
(addition) or borrow (subtraction) occurs
in CPU operations:

1= Carry occurred.
0= No carry occurred.
STAT6-(Z) Zero Flag, set when the result of
a CPU operation is zero:

STAT4-(S) Sign Bit, set when the most
significant bit of the result of the previous
CPU operation is negative:
1= Result is negative.
0= Result is positive.
STAT3-(STKF) Stack Flag, set when the
stack is full:
1= Stack is full.
0= Stack is not full.
STAT2-(BRKPNT) Breakpoint Flag, set
when the address in the breakpoint
register is equal to the EPROM address:
1= Breakpoint occurred.
0= No breakpoint occurred.
STAT1-(BCZ) Block Counter Zero, set
when the counter decrements to all Os:
1= Block Counter reached zero.
0= Block Counter is not zero.
STATO-(ACO) Address Counter Ones, set
when the counter increments to all 1s:
1= Address Counter reached all ones.
0= Address Counter is not all ones.

1= Zero occurred.
0= No zero occurred.
STAT5-(O) Overflow Flag, set when an
overflow occurs during a two's comple. ment operation:
1= Overflow occurred.
0= No overflow occurred.

FigureS.
Status Register

MSB

I

o
o~
Reserved
Reserved
Statll
Reserved
Stat9
Stat8

LSB

I

IL~

StatO
Stat 1
Sta12
Stat3
Sta14
Slat5
Slat6
Sla17
1738 08

2·74

WAFERSCALE INTEGRATION, INC.

-~~------

PAC100D

Contro/Sect/on

The control section, shown in Figure 9,
consists of a number of blocks which are
concerned with the sequencing of the control
programs in the PAC1 000. These are:
a Program Memory
a Security

a
a
a

a
a

The PAC1000 can perform three simultaneous operations within a single instruction
cycle, as shown in Figure 10. The ability to
fetch an instruction from the Program Memory, execute it, and output a result within 50
nsec is due to a highly parallel structure.

a
a
a

15-Level Stack
Program Counter
Loop Counter
Breakpoint Register
Condition Codes

Case Logic
Interrupt Logic
Output Control
Each block is described in detail below.

I'tnllellJptlftltlDIIB

Figure'.

ContlD/
Architecture

Internal Bus

16

CC[O:7]

8
IS·level
Stack

IntemalCC
(from AWl

loop
Counter

13

External
Interrupts

4

Internal
Interrupts

4

},Control
Signals

Program
Memory
IK x64EPROM

16
OC[O:I5]

WAFERSCALE INTEGRATION, INC.

1738 09

2·75

PAC1000

Control Section

Program Memory

(Con't)

The Program Memory is a 1Kx64 high-speed
EPROM. This on-board-memory allows the
PAC1 000 to operate in embedded control
applications and eliminates the need for
external memory components. Using an
erasable memory allows program code to be
modified for debug and/or field upgrades.
The Program Memory is easily programmed
using the WSI MagicPro™ (Memory and
PSDTM Programmer).
Only sixteen Program Memory locations are
reserved. The rest of the 1024 locations are
available for applications.
Program memory is segmented as follows:

Address

Thereafter, the EPROM contents cannot be
read externally. When the EPROM is erased,
the security bit is cleared.

15·Level Stack
The 15-level Stack stores the return address
following subroutine calls, interrupt service
routines and the contents of the Loop
Counter inside nested loops. When the stack
is full, the STKF condition becomes true, and
an interrupt (INT7) will occur. The interrupt
service routine will overwrite the top of the
stack.
Popping from an empty stack produces the
previous top of stack value; pushing on a full
stack overwrites the top of the stack.

Function

Program Counter

OOOH

Reset pointer program
to here

000H-007H

User Defined
Initialization Routine

008H-OOFH

Interrupt Vector
Locations

The 10-bit Program Counter (PC) generates
sequential addressing to the 1K word Program Memory. Upon reset the PC is loaded
with a OOOH. From this point the value of the
Program Counter is determined by program
execution or interrupts.

010H-3FFH

User-Defined
Application Programs

Upon receiving a reset, the Program Counter
is forced to address OOOH. This location may
contain a jump or call which branches to an
initialization routine. Alternatively, the first
eight locations of memory may be used as an
initialization/configuration routine.

Security
User programs may be protected by setting a
security bit during EPROM programming.

Any JUMP or Case instruction that is executed loads the Program Counter with the
destination address. CALL instructions or
interrupts cause PC + 1 to be pushed onto
the stack. The RETURN instruction loads the
Program Counter from the stack with the
value of the return address. This value may
have previously been placed on the stack by
a CALL or interrupt.
The PC can also be loaded from the Command/Data FIFO causing program execution
to commence at an address provided by the
host.

Figure 10.
Parallel
Operations
Part of Control SectIon

OCiO 15J

2·76

WAFERSCALE INTEGRATION, INC.

1738 10

PAC1000

Control Section
(Con't)

Loop Counter
The Loop Counter (LC) has two functions:

o 1O-bit down counter that supports the
LOOP instruction.

o Branch Register that can be loaded from
the CPU Register File or Program
Memory and used as an additional
source of branching to Program Memory.
The LC can be loaded with values up to
1023. Loop initialization code places a value
in LC. Loop termination code tests the
counter for a zero value and then decrements
LC. The loop count can be a constant, or it
can be computed at execution time and
loaded into LC from the CPU. The LC
register can also be used as a CALL or
JUMP execution vector. The content of the
LC is automatically saved on (or retrieved
from) the Stack when the program enters (or
leaves) a nested loop.
A loop count will be loaded into the LC when
a FOR instruction is encountered. This count
can be a fixed value or it can be calculated
and loaded from the CPU. The ENDFOR
instruction will test the Loop Counter for a
zero value. If this condition is not met, then
the LC will be decremented by one. The
program loop will continue until the count
value equals zero. In a nested loop, the FOR
instruction will load a new value to the LC
and push the previous value to the stack.

Debug capabilities
The PAC1000 provides breakpoint and single
step capabilities for debugging application
programs.

Breakpoint Register
The Breakpoint Register (BR) is a 10-bit
register used for real time debug of the
PAC1000 application program.
The Breakpoint Register can be loaded from
one of two sources, either a constant value
specified in the Program Memory or a calculated value loaded from the CPU. When the
Program Memory address matches the contents of the Breakpoint Register an interrupt
(INT 6) occurs. A service routine should exist
in Program Memory which then performs the
required procedure.
Single Step
Single step is a debugging mode in which the
currently-executing program is interrupted by
interrupt 6 after the execution of every
instruction. The interrupt 6 service routine
should reside in Program Memory.
Bit 8 in the Mask Register determines
whether the PAC1000 is in a breakpoint
mode (mask-bit 8 equals 0) or in a single step
mode (mask-bit 8 equals 1).
Both breakpoint and single step use interrupt
6. The interrupt 6 service routine will typically
dump the contents of the PAC1 000 internal
registers into external SRAM devices for examination by the user.
Condition Codes
The Condition Code (CC) logic operates on
21 individual program test conditions. Each
condition can be tested for true or not true.
The PAC 1000 can also test up to four
conditions simultaneously. For this feature
refer to the section titled Case Logic.

WAFERSCALE INTEGRATION, INC.

- - . ----

.-~-----

_. __. . ...

..

- -.-

2·77

._------ - - - - - -

.~---

PAC1000

Control Section

User-Specified Conditions

(Con't)

User-Specified Conditions are treated in the
same manner as internally generated test
conditions. CCO-CC7 should be connected
directly to the corresponding PAC1000 input
pins. These signals must satisfy the required
setup time to be serviced in the next cycle.

CPU Flags
CPU flags are internally generated. They
reflect the status of the previous CPU arithmetic operation. These signals are internally
latched and are valid only for one instruction
(the instruction following their generation).
The flags for arithmetic operations are
defined as follows:
Zero (Z)-The result of the previous CPU
operation is zero (Z= 1).
Carry (CY)-The result of the previous CPU
operation generated a carry (addition) or
borrow (subtraction) (CY=1).
Overflow (0)-The previous two's complement CPU operation generated an
overflow (0=1).
Sign (S)-The most significant bit of the
result of the previous CPU operation is
negative (S=1).

FIFO Flags
FIFO flags allow the user to synchronize and
monitor the operations that are performed on
the FIFO by the host or by user's program.
Upon reset the FIFO flags are cleared,
signifying an empty state. The meaning of the
flags are as follows:
FIFO Output Ready (FIOR)-There is at least
one word in the FIFO (FIOR=1).

Table 3.
Condition-Code
Logic

2-78

FIFO Input Ready (FIIR)-FIFO is not full
(FIIR=1). This flag can also be connected
to the host throug h 1/07.
FIFO Command/Data (FICD)-This flag
indicates if the contents of the FIFO is a
command or a data. This flag is generated directly from HAD5 (FICD=1 command, FICD=O data).
FIFO Exception (FIXP)-This flag indicates
that one of two events occurred: (a) FIFO
data has been read as a command, or
(b) a command has been read as data.

Stack-Full Flag
STACK FULL flag (STKF=1) indicates that
the stack is 15 levels full. This condition will
also generate an interrupt (INT7) if not
masked.

Interrupt Flag
INTERRUPT flag (INTR =1) indicates that
there is a masked interrupt pending. This flag
is cleared when the interrupt is cleared.

Data Register Read Flag
DATA REGISTER READ flag (DOR) is a
handshake flag between the host and the
PAC1000, accessible only to the PAC1000.
The flag is reset (DOR=O) when the
PAC1 000 writes into the Data Output Register. The flag is set (DOR=1) after the host
has performed a read on the Data Output
Register.

Counter Flag
Counter flags reflect the status of their
respective counters. The PAC1000 utilizes
two counters; the Address (A) counter is a
16/22-bit auto-incrementing up counter; the

Test Group

Source

Conditions and Flags

User-Specified

External

CCO-CC7

CPU

Internal

Carry (CY), Zero (Z), Overflow (0),
Sign (S)

FIFO

Internal

FIFO Command/Data (FICD), FIFO Output
Ready (FIOR), FIFO Input Ready (FIIR),
FIFO Exception (FIXP)

Counters

Internal

Address Counter Ones (ACO), Block
Counter Zero (BCZ)

Stack

Internal

Stack Full (STKF)

Interrupt

External/Internal

Interrupt (INTR) is pending

Data register read

Internal

Data Output Register(DOR) has been read

WAFERSCALE INTEGRATION, INC.

PAC1000

Control Section
(Con't)

Block (B) counter is an auto-decrementing
16-bit down counter. The counters' clock
input signal is the same as the PAC1000's
clock signal. Each counter can be individually
enabled or disabled. When disabled, the
output retains the last count. The counter
flags are defined as follows:

ACO-A Counter Ones, set when the A
counter has reached the value FFFFH, in
the 16-bit mode, or the value 3FFFFFH
in the 22-bit mode.
BCZ-8 Counter Zero, set when the B
counter has reached the value OOOOH.

Case Logic
THE PAC1000 hardware implements two
basic types of Case instructions: Case and
Priority Case.

Case Instructions
Case instructions operate on anyone of four
different Case groups. Each Case group
consists of a combination of four test conditions which can be tested in a single cycle. In
that same cycle the PAC1 000 will branch to
one of the addresses contained in the sixteen
memory locations following the instruction,
depending on the status of the four inputs to
the Case group being tested.

(The FIXP, ACO, STKF, FIIR, and DOR
condition codes do not fall into any of the four
Case groups.)

Priority Case Instructions
Priority Case instructions operate on the four
internal and the four external interrupt inputs.
In this mode of operation, interrupts are
treated as prioritized test conditions and the
priority encoder is used to generate a branch
to the highest priority condition. The branch
address is located in one of the nine memory
locations following the Priority Case instruction. Priorities in this mode of operation are
the same as in the Interrupt mode of operation. Once a Priority Case instruction is
executed, the occurrence of a higher priority
condition will not affect program execution
until another Priority Case instruction is
executed. For a Priority Case instruction to
be executed, MOD EO of the Mask Register
must be equal to zero (MODEO=O).

Interrupt Logic
The Interrupt Logic accepts eight inputs, four
of them are generated externally and four are
dedicated for internal conditions. The four
external, user defined, inputs (INTO-INT3)
are connected to pins INTO, INT1 , INT2, and
INT3. These are positive, rising-edgetriggered signals that have a maximum
latency of two cycles. Each interrupt has a
reserved area in memory that should contain
a branch to an interrupt service routine.

There are four Case Groups (sets of Case
Conditions):
Case Group 0 (CGO): CCO-CC3.
Case Group 1 (CG1): CC4-CC?
Case Group 2 (CG2):
Z-Zero
O-Overflow
S-Sign
CY-Carry

Table 4.
Interrupt
Assignments

Case Group 3 (CG3):
INTR-Interrupt
BCZ-B Counter Zero
FIOR-FIFO output Ready
FICO-FIFO Command/Data

Interrupt

Priority

Effect

Trigger Condition

Reserved Address

INT?

Highest

Internal

FIXP+ACO+STKF+FIIR

OOFH

INT6

Internal

BRKPT

OOEH

INT5

Internal

FIOR

OODH

INT4

Internal

Software Interrupt (SWI)

OOCH

INT3

External

INT3

OOBH

INT2

External

INT2

OOAH

External

INT1

009H

External

INTO

008H

INT1
INTO

Lowest

WAFERSCALE INTEGRATION, INC.

2-79

PACtOOO

Control Section
(Con't)

Clearing a serviced interrupt is performed
automatically. When the interrupt is serviced,
the internally generated vector is decoded to
clear the serviced interrupt. In addition, the
user can clear any pending interrupt by using
the Clear Interrupt Instruction (CLI).

When the PAC1000 is reset, the Mask Register will mask all interrupts and the Mode
Register will select the non-interrupt mode.
To select the interrupt mode the MOOED bit
(see Configuration Register section in this
document) should be set to 1 (MODEO=1).

Interrupt Mask Register

Mask8 is used to select INT6 to be either a
single-step interrupt (when Mask8=1) or a
breakpoint interrupt (when Mask8=0) .See
the section on Debug Capabilities for further
details.

The Interrupt Mask Register, shown in Figure
11 , allows individual interrupts to be masked.
Setting a Mask Register bit to a 1 masks the
associated interrupt. To unmask an interrupt.
the appropriate Mask Register bit must be
reset to O.

Table 5.
Interrupt
Definitions

Interrupt

Triggered By

INT?1

FIFO Exception (FIXP)
Address Counter contains all Ones (ACO)
Stack Full (STKF)
FIFO Full (Not FIFO Input Ready, FIIR)

INT62

Breakpoint or Single Step occurrence

INT5

FIFO Output Ready (FIOR)

INT4

Always pending; triggers when unmasked by program execution

INT3

User-defined

INT2

User-defined

INT1

User-defined

INTO

User-defined

Notes:
1. The INT? interrupt handler checks the source of the interrupt by testing the condition code.
2. See Interrupt Mask Register, Mask8.

Figure 11.
Interrupt Mask
Register

MSB

LSB

I

MaskS
Mask?

--.J

J

l

I

L--

MaskO
Mask1

Mask6

Mask2

Mask5

Mask3

Mask4
Status After Reset

o

1738 11

2-80

WAFERSCALE INTEGRATION, INC.

PACtOOO

Control Section

Output Control

(Con't)

The Output Control bus (OUTCNTL) consists
of 16 latched Output Control signals. These
signals can be changed on a clock to clock
basis. For every Program Memory location
there is a dedicated field which specifies the
value of the Output Control bus. The

Counters

OUTCNTL Operation places this value on the
Output Control bus. The OUTCNTL Operation can be performed in parallel with any
other PAC1000 instructions.
The OUTCNTL bus can be used to control
external events on a clock to clock basis.

The PAC1000 contains a 16 or 22-bit Address Counter and a 16-bit Block Counter.
Each of these counters can change count on
a clock to clock basis or can be internally or
externally enabled or disabled on a clock to
clock basis. These counters are in addition to
the Loop and Program Counters of the
Control Section.

until the counter is loaded with a new value.
The counter will continue to count until
disabled. ACO is a condition code and a
member of a Case Group; see the Control
Section description for more details. ACO can
also generate an internal interrupt 7, if
enabled.
In the 16-bit mode, the counter outputs (ACH)
are available through the ADD bus. The
count is gated to the ADD bus by setting the
ASEL bit (CTRL9) of the Control Register.

Address Counter
The Address Counter (AC), shown in Figure
12, is a 16- or 22-bit ascending counter that
can be loaded or read by the CPU and
enabled/disabled with the ACEN bit of the
Control Register. (This control is also available externally through the 1/01 pin; see I/O
and Special Functions). While enabled, the
counter will increment by one every rising
edge of the clock.

In the 22-bit mode, the higher 16 bits (ACH)
are available through the ADD bus and the
six low order bits (ACL) are available through
the Host Address (HAD) bus. These low
order bits are multiplexed with the host
address lines. The address lines from the
host which drives the HAD bus must be
placed in the high impedance state before the
lower 6-bits (ACL) of the Address Counter
can be read.

The ACO flag indicates that the value of the
counter is all ones. This flag stays latched

Figure 12.
Address and
Block Counter

Internal Bus

16

16

16

16

16
ACH

IACEN

Address
Count
High

ACL
Address
Count
Low

AOR
AIR

-ACS22

Address
Output
Register
to HAD in
Host Interface

ADD[O.1S)

WAFERSCALE INTEGRATION, INC.

173812

2-8t

PAC1000

Counters
(Con't)

Selecting the 16- or 22-bit count mode is
performed by setting or resetting the ACS22
bit in the 1/0 Configuration Register.
The address Output Register is an alternate
source of address outputs; it is selected by
resetting the ASEL bit of the Control Register. In this mode the CPU can be used to
provide address generation and the Address
Counter can be used as an event counter.

B/ock Counter
The Block Counter (BC) is a 16-bit down
counter. It is enabled by the BCEN bit of the
Control Register. It is useful as a counter for
DMA transfers. The BCEN signal is (option-

Central
Processing Unit

2·82

The CPU, shown in Figure 13, performs
16-bit operations in a single clock cycle. It
contains 33 general purpose registers
(RO ... R31, and 0). The 0 register can be
used in conjunction with any of the RO ... R31
registers to perform double precision shift

WAFERSCALE INTEGRATION, INC.

ally) available externally through the 1/00 bit
(see 1/0 and Special Functions). While
enabled, the counter will decrement by one
every rising edge of the clock. The BCZ flag
indicates that the counter reached the zero
value. After the occurrence of an all Os
condition the Block Counter will continue
down counting until disabled. The flag is
latched and can be cleared by loading a new
value into the Block Counter. BCZ is a
condition code and a member of a Case
Group; see the Control Section description
for more details.
Both counters may be read without disabling
the count operation and loaded via the CPU.
operations. The main building blocks are the
register bank (RO ... R31), 0 register, ALU,
V-bus devices, and D-bus devices. The
register bank supplies up to two 16-bit
registers, one of which is always the destination register.

PAC1000

Figure 13.
CPU Block
Diagram

r---------------------------------------------,
I

I

IN (B)

Register

elK

Bank
(R31/RO)

CPU

r-------~===~==~----------------·
I

,---''-,=:-.L-,

1/0

I

Bus

Part of
Control Section

I

Host
Interface

Constants

r------,
I
I

I

I

Host
Interface

Host

Interface

ADD
Bus

1/0
Bus

I
Part 01
I Control Section I
L ______ --l
1738 13

WAFERSCALE INTEGRATION, INC.

2·83

PAC1000

Central
Processing Unit
(Con't)

The ALU operates on up to two external
operands that are selected by its input MUX.
In every instruction, 1 of the 10 D-bus devices (AOR, SWAP, ACL, ACH, BC, FIFO,
DIR, AIR, IIR, and Program Store) or a
member of the register bank or the Q register
outputs, can be selected as an operand
source to the ALU. The possibilities are
shown in Figure 14. During ALU operations,
three options can be selected to provide the
carry-in (Cin) input: 0, 1, or the previous

latched carry-out (adequate for multiple
precision operations).
The ALU's output or a selected register can
be loaded into one of the seven V-bus
devices (lOR, AOR, LC, DOR, ACL, ACH, or
BC) every instruction cycle. This can happen
in parallel with the feedback path from the
ALU's output that is directed either to the Q
register or to the destination register of the
register bank.

Destination Only
DOR

LC

lOR

1738 14

TableS.
CPU Operand
Mnemonics

Mnemonic
ACH or ACH/ACL
AIR
AOR
BC

DIR
DOR
FIFO
IIR
lOR
LC
Q
RQ-R31
SWPV

2-84

WAFERSCALE INTEGRATION, INC.

Description
16- or 22-bit Auto-incrementing Counter, or General Purpose
Registers
Address Input Register
Address Output Register
Block Counter (16-bit auto-decrementing), or General Purpose
Register
Constant values in Program Storage
Data Input Register
Data Output Register
Input Data from FIFO
1/0 Input Register
1/0 Output Register

Program Loop Counter
16-bit CPU Register
16-bit CPU Registers
Byte Swap version of AOR

PAC100D

Central
Processing Unit
(COR't)

CPU operations can be performed on one,
two or three operands. Each operation is performed in a single clock cycle. In two- or
three-operand instructions, one of the operands must be a CPU internal register
(RO ... R31, or 0).
CPU operations are performed independently
of operations in the counters, Host Interface,
Output Control, and Program Control.
Arithmetic Operations
The CPU can perform the following arithmetic operations:
Q Addition
Q Subtraction
Q
Increment
Q Decrement
Q
Compare
Logic Operations
The CPU can perform the following logic
operations:
Q AND
Q

OR

Q
Q

Invert
Exclusive OR

Q

Exclusive NOR

All shift operations can be executed in the
same clock cycle as an arithmetic or logic operation. The arithmetic or logic operation is
executed first; the result is shifted and then
stored in the register file. The shift can be

~
~

Rn

Q

Sign Flag (S)
Binary 0 (0)
Binary 1 (1)
Least-significant bit of this register (RLSB)
Least-significant bit of the 0 register (OLSB)
Serial I/O port (SDATM)

Shift Operations
Single shift operations, shown in Figure 15,
can occur either to the left or to the right, with
or without the 0 register. Shift instructions
specify the sources that are shifted into the
corresponding registers.

Figure 15.
Shift Operations

either left or right.
The CPU can perform the following shift
operations:
Q Single-precision, left or right, within a
general-purpose register (RO ... R31,
orO).
Q Double-precision, left or right, between
an RO ... R31 register and the 0 register.
The LSB and MSB of the general-purpose
registers are each fed by an eight-to-one
multiplexer.
The sources and destinations for shift operation are given below:
Shift Right
Zero Flag (Z)
Carry Flag (CY)

Shift Left
Zero Flag (Z)
Carry Flag (CY)
Sign Flag (S)
Binary 0 (0)
Binary 1 (1)
Most-significant bit of this register (RMSB)
Most-significant bit of the 0 register (OMSB)
Serial 1/0 port (SDATL)

~
~

Shift Single Precision left/Righi

ShIft Double Precision Left/RIghi

Shift Double PrecIsIon LeftlRighl
1738 15

WAFERSCALE INTEGRATION, INC.
- - - --- --------

z.tJ5

PACtOOO

Central
Processing Unit
{Con't}

Rotate Operations

Multiple Precision Operations

The CPU can perform the following rotate operations, as shown in Figure 16:

The carry-out in each instruction can be used
in the next instruction for multiple precision
operations (e.g., ADDC). This feature enables the user to implement complex arithmetic operations such as division or multiplication in several clock cycles.

o

Single-precision, left or right, within a
general-purpose register (RO ... R31,

ora).

o

Double-precision, left or right, between
an RO ... R31 register and the a register.

Figure 16.
Rotate Operations

~

Y"----Rn

dab
Single PrecISion Rotate Right/Left

Double Precision Rotate Right/Left
1738 16

I/O and Special
Functions

2·86

The 1/0 bus, shown in Figure 17, consists of
eight lines which can be individually programmed as inputs or outputs. These lines
can also be programmed to perform Special
Functions. The functions of these pins are
defined by the Mode Register and 1/0 Configuration Register (see Configuration Register Section). The 1/0 and Special Functions
map according to the table. The 110 lines
must first be configured as inputs or outputs
via the 1/0 Configuration Register; the
Special Function option can then be enabled
via the Mode Register. Individual special

WAFERSCALE INTEGRATION, INC.

function control is shown in the accompanying table.
Once a Special Function has been enabled,
the corresponding internal control function is
automatically disabled. Conversely, when a
Special Function is disabled, control of the
corresponding internal control function is
returned to the Control Register (see Configuration Register). Because the Inputs in
the 1/0 Register are clocked on each cycle,
the status of the special function can also be
read to the CPU.

PAC1000

Figure 17.
I/O and Special
Function Bus

MODE 8

FIIR

IADOE
CNTl4
(ADOE)

MODE?

~.

B MUX

1/05

w
~

'"

0

CNTl3
(HADOE)

"%

0

IHADOE

fJ

MODE6

iii
d:J

IHDOE
CNTl2
(HDOE)
w
~

'"

"
~

IIR
D

MODES
CK

SDATM
OMSB

ClK

SDATl
OlSB

lAC EN
CNTlO
(ACEN)

MODE3

B MUX
CNTl1
(BCEN)

CK

0

0

IBeEN

D
lOR
MODE2

10CGO
lOWER 8-BIT CPU
Y BUS
1738 17

WAFERSCALE INTEGRATION, INC.

2-87

PAC1000

Configuration
Registers

Table 7.
I/O Pins and
Special Functions

TableS.
Special-Function
Control

The Configuration Registers allow the user to
control and configure different operating
modes of the PAC1000. The three 10-bit
Configuration Registers are the Control
Register, 1/0 Configuration Register, and
Mode Register. Each register has an associated instruction which allows individual
register bits to be modified.

Control Register
The Control Register, shown in Figure 18,
provides for internal control of key functions
within the PAC1 000 . Several of these
functions can alternatively be controlled
externally through the 110 bus (see 1/0 and
SpeCial Functions). The Control Register is
modified on the falling edge of the clock.

Pin

Special Function

Direction

Description

1/07

FIIR

output

FIFO Input Ready. FIFO not full.

1/06

ADOE

input

Address Output Enable

1/05

HADOE

input

Host Address Output Enable

1/04

HDOE

input

Host Data Output Enable

1/03

QMSB

bidirectional

Q Register MSB

1/02

QLSB

bidirectional

Q Register LSB

1/01

ACEN

input

Address Counter Enable

1/00

BCEN

input

Block Counter Enable

Special Function

Pin Name

I/O Configuration

Mode

FIIR

1/07

IOCG7=1 (output)

MODE8=1

ADOE

1/06

IOCG6=0 (input)

MODE7=1

HADOE

1/05

IOCG5=0 (input)

MODE6=1
MODE5=1

HDOE

1104

IOCG4=0 (input)

QMSB

1/03

IOCG3=1 (output)

QLSB

1102

IOCG3=0 (input)

2-88

MODE4=1

IOCG2=1 (output)
IOCG2=0 (input)

MODE4=1

ACEN

1/01

IOCG1 =0 (input)

MODE3 =1

BCEN

1/00

10CGO=0 (input)

MODE2 =1

WAFERSCALE INTEGRATION, INC.

PAC1000

Configuration
Registers
(Con't)

ASEL (CTRL9)-Address Select. Selects the
source that will write to the Address bus:
1= Address Counter.

1= Output (see ASEL).

0= Address Output Register (AOR).
AIREN (CTRL8)-Address Input Register
Enable. Enables and disables writing to
the Address Input Register from the ADD
Port:
1= Enable writing to Address Input
Register (AIR).

1= Output (driven from ACL Register).
HDOE (CTRL2)-Host Data Output Enable.
Selects Direction of Host Data (HD) bus
for next clock cycle:

DIREN (CTRL7)-Data Input Register
Enable. Enables and disables writing to
the Data Input Register (DIR) from the
HD Port:

1= Output (See HDSELO and HDSEL 1).
0= Input (See DIREN).

1= Enable writing to Data Input Register
(DIR).
0= Disable writing to Data Input Register
(DIR).
HDSEL 1 (CTRL6) and HDSELO (CTRLS)Host Data Select. Select the source to be
connected to Host Data (HD) bus:
HDSEL 1 HDSELO
Selection

(CTRL5)

0

0

FIFOPeripheral
Mode

0

0= Input (see AIREN).
HADOE (CTRL3)-Host Address Output
Enable. Selects direction of Host Address
(HAD) bus for next clock cycle:
0= Input (into the FIFO).

0= Disable writing to Address Input
Register (AIR).

(CTRL6)

ADOE (CTRL4)-Address Output Enable.
Selects direction of Address bus (ADD)
for next clock cycle:

BCEN (CTRL 1 )-Block Counter Enable.
Enables and disables Block Counter:
1= Enable Counting on next rising clock
edge.
0= Disable Counting on next rising edge.
ACEN (CTRLO)-Address Counter Enable.
Enables and disables Address Counter:
1= Enable Counting on next rising clock
edge.
0= Disable Counting on next rising clock
edge.

Data Output
Register

0

Status
Register
Program
Counter

Figure 18.
Control Register

MSB

I

GTRL9

(ASEL)~

GTRLS

(AIREN)

GTRL?

(OIREN)

LSB

I

~ GTRLO

(AGEN)
CTRL 1 (BGEN)
CTRL2 (HOOE)

GTRL6 (HOSEL1)

CTRL3 (HAOOE)
CTRL4 (AOOE)

GTRL5 (HOSELO)
Note: After Reset, All Bits Are Cleared to Zero.

WAFERSCALE INTEGRATION, INC.

1738 18

2·89

PAC1000

Configuration
Registers
(Con't)

I/O Configuration Register

1/05 (IOCG5)-Selects direction of 1/05 pin:

The I/O Configuration Register, shown in
Figure 19, controls the direction of the
individual lines of the 110 bus as well as configuring the Address Counter. Each I/O pin
can be configured independently to be a
general purpose input or output, or each can
serve a special function (see I/O and Special
Function). The I/O Configuration Register is
also used to configure the Address Counter
as a 16-bit counter with a maximum count of
FFFFH or as a 22-bit counter with a maximum count of 3FFFFFH. The I/O Configuration Register is modified on the falling edge
of the clock.
ACS22 (IOCG9)-Configures Address
Counter as a 22- or 16-bit counter:

1= Output.
0= Input.
1/04 (IOCG4)-Selects direction of 1/04 pin:
1= Output.
0= Input.
1/03 (IOCG3)-Selects direction of 1103 pin:
1= Output.
0= Input.
1/02 (IOCG2)-Selects direction of 1/02 pin:
1= Output.
0= Input.
1/01 (IOCG1 )-Selects direction of 1/01 pin:
1= Output.

1= 22-bit counter.

0= Input.

0= 16-bit counter.
1/07 (IOCG7)-Selects direction of 1107 pin:

1/00 (IOCGO)-Selects direction of 1/00 pin:
1= Output.

1= Output.

0= Input.

0= Input.
1/06 (IOCG6)-Selects direction of 1/06 pin:
1= Output.
0= Input.

Figure 19.
I/O Configuration
Register

MSB

IOCG9 (ACS22)
IOCG8 (Reserved)
IOCG7
(1/07) - - - - - - - '
IOCG6
(1/06) - - - - - - - - '
IOCG5
(1/05) - - - - - - - - - '

LSB

10CGO
'----- IOCG1
' - - - - - - IOCG2
' - - - - - - - IOCG3
'-------IOCG4

(1/00)
(1/01)
(1102)
(1/03)
(1/04)

Note: After Reset, All Bits Are Cleared to Zero.
1738 19

2·90

WAFERSCALE INTEGRATION, INC.

I'AC10D0

Configuration
Registers
(CoII't)

Mode Rflllister
The Mode Register, shown in Figure 20,
allows the user to externally control and
monitor key elements within the PAC1000
which would (alternatively) be controlled
internally through the Control Register.
Enabling a Special Function in the Mode
Register disables the corresponding function
in the Control Register. The Special Function
input pins are shared with the general
purpose 1/0 pins. The direction of the appropriate pin must be set in the 1/0 Configuration
Register prior to programming the Mode
Register.
The Mode Register can also be used to reset
the FIFO as well as program the interrupt
controller to generate either interrupts or
Priority Test Conditions. See the discussion
on "Priority Case" in the Condition Code
section, above.
After Reset, all Mode Register bits equal
zero. The Mode Register is modified on the
falling edge of the clock.
The use of the Mode Register and 1/0
Configuration register for Special Functions
is shown in the Special Function Settings
table.
FIRST (MODE9)-FIFO Reset. (If held high,
FIFO cannot receive information):
1= Initiate FIFO Reset (FIRST).
0= Complete FIFO Reset (FINRST).
FIIR (MODE8)-FIFO Input Ready:
1= 1/07 becomes output for the FIFO
Input Ready (FIIR) flag.
0= 1/07 becomes general purpose 1/0
(107).
ADOE (MODE7)-Address Output Enable:

Figure2D.
Mode Register

I

MODES

(FIIR)

Enable:

1= 1/05 becomes input for Host Address
Output Enable (HADOE).
0= 1/05 becomes general purpose 1/0

(106).
HDOE (MODE5)-Host Data Output Enable:

1= 1/04 becomes input for Host Data
bus Output Enable HDOE).
0= 1/04 becomes general purpose 1/0
(104).
SIOEN (MODE4)-SeriaIIIO Enable:
1= 1/03 and 1/02 become MSB and LSB
(respectively) of the CPU's Q register
(SIO).
0= 1/03 and 1/02 become general
purpose 1/0 ACEN(MODE3).
ACEN (MODE3)-Address Counter Enable:
1= 1/01 becomes input for Address
Counter Enable (ACEN).
0= 1/01 becomes general purpose 1/0.
BCEN (MODE2)-Block Counter Enable:
1= 1/00 becomes input for Block Counter
Enable (BCEN).
0= 1/00 becomes general purpose 1/0.
Reserved (MODE1)
INTR (MODEO)-lnterruptiPriority-Case
Mode:

1= Select Interrupt mode (INTR).
0= Selects Priority Case mode (PCC).

LSB

MSB

MODE9 (FIRST) ~

1= 1/06 becomes input for the Address
Output Enable (AOE).
0= 1/06 becomes general purpose 1/0
(106).
HADOE (MODE6)-Host Address Output

I

I

(INTR)
~ MODEO
MODE1 (Reserved)
MODE2 (BCEN)

MODE7 (ADOE)
MODE6 (HADOE)
MODE5 (HDOE)

MODE3 (ACEN)
MODE4 (SIOEN)
Note: After Reset, All Bits Are Cleared to Zero.

WAFERSCALE INTEGRATION, INC.

----~------.

-------~

1738 20

2·91

PAC1000

State Following
Reset
Tableg.
Special Function
Settings

Table 10.
Signal States
Following Reset

2·92

Whenever the PAC1000 RESET input is
driven low for at least two processor clocks,
the chip goes through reset. The next two

tables describe the PAC1000 signal and
internal register states following reset.

Mode Bit

I/O Configuration Bit

Function

MODE8=1

IOCG7=1

FIIR flag output on 1/07

MODE7=1

IOCG6=0

ADOE provided by 1/06

MODE6=1

IOCG5=O

HADOE provided by 1/05

MODE5=1

IOCG4=0

HDOE provided by 1/04

MODE4=1

IOCG3=1

MSB of Q register output on 1/03

MODE4=1

IOCG3=0

1/03 can be shifted into MSB of Q register
or destination register

MODE4=1

IOCG2=1

LSB of Q register output on 1/02

MODE4=1

IOCG2=0

1/02 can be shifted into LSB of Q register
or destination register

MODE3=1

IOCG1=0

ACEN provided by 1/01

MODE2=1

10CGO=0

BCEN provided by 1/00

Signal

Condition

HAD[5:O]

Input

HD[15:0]

Input

10[7:0]

Input

ADD[15:0]

Input

0C[15:0]

OOOOH

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PAC1000

Table 11.
Intemal States
FoJlowing Reset

Component

Contents

ACH Register

0

ACL Register

0

AOR Register

0

AIR Register

0

DOR Register

0

DIR Register

0

lOR Register
IIR Register

0
0

STATUS Register

0

1/0 Configuration Register

0

CONTROL Register

0

Breakpoint Register

0

.Mode Register
PC Register (Program Counter)

0

MASK Register

0
011111111 B

BC Register
R31-RO Registers

FFFFH
Unknown

Q Register

Unknown

LC Register

Unknown

FIFO Locations
FIFO Flags

Unknown
Empty

WAFERSCALE INTEGRATION, INC.

2·93

PAC1000

Electrical and Tinring
Specifications
Table 12.
Absolute
Maxinrunr Ratings

Storage Temperature

-65°C to + 150°C

Voltage to any pin with respect to GND

-0.6V to +7V

V pp with respect to GND

-0.6 V to + 14.0V

ESD Protection

>2000V

Stresses above those listed here may cause
permanent damage to the device. This is a
stress rating only and functional operation of
the device at these or any other conditions
above those indicated in the operational

Table 13.
Operating Range

Table 14.
DC
Characteristics
ivtil' OIItII'lIting 1'lilii/ii
with V",,=Vcc

sections of this specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods of time may
affect device reliability.

Range

Temperature

Vee

Commercial

O'C to +70'C

+5V±5%

Industrial

-40°C to +85°C

+5V± 10%

Military

-55'C to +125'C

+5V± 10%

Parameter

Symbol

Test Conditions

Output Low Voltage
Output High Voltage

VOL
VOH

IOH=-4 mA

Vee Standby
Current CMOS

ISBl

note 1

65

mA

Vee Standby
Current TTL

65

mA

130
150

mA
mA

160
180

mA
mA

ISB2

note 2

Active Current (CMOS)
-Commercial
-Military

leel

notes 1,3

Active Current (TTL)
-Commercial
-Military

lee2

Max Units
0.4

IOL=8 mA
2.4

V
V

notes 2,3

V pp Supply Current

Ipp

Vpp=Vee

100

I1A

Vpp Read Voltage

Vpp

notes 1,2

Vee-0.4

Vee

V

Input Load Current

III

V 1N=5.5V
orGND

-10

10

I1A

Output Leakage Current

ILO

VouT=5.5V
orGND

-10

10

I1A

Notes:
1. CMOS inputs: GND ± 0.3V or Vee ± 0.3V.
2. TTL inputs: V 1L S 0.8V, VIH~ 2.0V.
3. Active current is an AC test and uses AC timing levels.

2·94

Min

WAFERSCALE INTEGRATION, INC.

~~-------

PAC1000

Table 15.
AC Timing Levels

Table 16.
AC
Characteristics

Inputs:

o to 3V Reference 1.5V

Outputs:

0.4 to 2.4V

Parameter

Symbol

12MHzl
Min Max

16MHzl
Min Max

20MHz2
Min Max

CLOCK CYCLE
Cycle Time

tCK

84

62.5

50

Clock Pulse Width High

tCKH

26

24

21

Clock Pulse Width Low

tCKL

26

24

21

t RC

50

HOST READ CYCLE
Read Cycle Time

40
45

30

Address to Data Valid

35

tACC

CS to Data Valid

tcs

CS to tristate

tcsz

0

Pulse width of CS and
WRLOW

tpWL

20

Pulse width of CS and
WR High

tpwH

15

10

10

Data setup to WR

tSD

10

10

5

Data hold to WR

tHD

10

10

5

RESET setup

tSR

10

10

5

RESET to tristate of
ADD, HAD, HD, I/O

tRZ

25

25

20

RESET clocked to
OUTCNTL low

t ROL

30

30

25

45
45

30

35
0

35

30
0

30

HOST WRITE CYCLE
15

15

RESET CYCLE

ADDRESS TIMING
tSADD

10

10

10

Address/Data hold

tHADD

8

8

5

Clocked Counter to
Address output

tCADD

43

35

30

tRADD
tADOE

43

35

30

ADOE enable to data valid

50

40

30

HADOE enable to
data valid

tHADOE

Address/Data setup

Clocked Address Register
to Address

Address output disable

tCKZ

40

50
0

25

20

30
0

WAFERSCALE INTEGRATION, INC.

16

2·95

PAC1000

Table 16.
AC
Characteristics
(Con't)

Parameter
DATA AND I/O TIMING
Clock to I/O Output Valid
Clock to HD Output
10 data setup
10 data hold

Symbol

12MHz'
Min Max

16MHz'
Min Max

35
35

tCKIO

10

10

8

8

HD data setup

tSHD

10

10

HD data hold

tHHD

8

HDOE enable to data valid

tHOOE

Bus Output Disable

tCKZ

TEST AND INTERRUPT TIMING
Condition Code setup
tscc
Condition Code hold
tHCC
Clock to OUTCNTL Valid
tcov
Minimum interrupt pulse
for acceptance
t lPWA

0

10
5
10
5

8

60
0

30
30

30
30

tCKHD
tSIO
t HIO

50
25

20MHz2
Min Max

0

40
20

30
16

40
0

50
0
33

0

25

33

15

10

10

15
0
15
0

10
0
10
0

10
0
10
0

SPECIAL FUNCTION TIMING (I/O Bus)

S015 setup
S015 hold
SOO setup
SOO hold
Clock to 00 output

tSS015

Clock to 015 output

tCK015

Address Counter
enable setup

tSACEN

20

15

10

tHACEN
Block Counter enable setup tSBCEN
Block Counter enable hold tHBCEN

10
20
10

5
15
5

5
10
5

tHS015
tssoo
tHSOO
tCKOO

Address Counter
enable hold

35
35

30
30

External output enable to
data valid

tSFV

30

25

20

External output enable to
high impedance

tSFZ

30

25

20

Notes:
1. Operating temperature range: Commercial, Industrial, Military
2. Operating temperature range: Commercial

2·96

30
30

WAFERSCALE INTEGRATION, INC.

I'AC1000

Figure 21.
Clock Cycle
Timing

_tCK_
CK

1738 21

Figure 22.
Host Read Cycle
Timing

~

=t=__

Ad_d:_::_sv_a_lid_ _ _

~~

_ __

tACC--

/

\
f4-tcs ....

_tcsz ......

/

\
HD

\'

Note tcs

IS

Data Valid

referenced from RD=O and CS=O
1738 22

Figure 23.
Host Write FIFO
Cycle Timing

HAD
HD

tPWL

1738 23

Figure 24.
Reset Cycle
Timing

CLOCK

ADD
HAD
HD
1/0

OUTCNTL
1738 24

WAFERSCALE INTEGRATION, INC.

Ull

PAC1000

Figure 25.
Data and I/O
Timing

SWitch bus from
Input to Output
(Note 1)

New Data or
Counter Oulput
(Note 2)

Next Dala
or Count Value

Oulpul to High
Impedance

Notes 1 A bus directional change (Input-Io-oulput or outpul-lo-Input)
takes place on the falling edge of the clock
New data or count value IS latched on the rising edge of the clock

Figure 26.
Address Timing

SWitch bus from
Input to Output
(Note 2 & 3)

New Data or
Counter Output
(Note 4)

Next Data

or Count Value

1738 25

Output to High
Impedance

CLOCK

ADD

HAD
(Note 1)

Notes 1 The Host Address (HAD) bus IS used to output the lower SIX bits of the 22·blt counter
2.A bus directional change takes place on the falling edge of the clock (Input-to-output or output·to"nput)
3 Selection of the source to be output on a bus occurs on the failing edge
of the clock (I e , counter or address register)
4. New data or counl value is latched on the rising edge of the clock

2·98

WAFERSCALE INTEGRATION, INC.

1738 26

PAC1000

Figure 27.
Test and Interrupt
Timing

CLOCK

CC[701

OUTCNTL

INT

h

----------------~

~-,IP-W-A------

Note 1 Since condition codes are not latched,
they should be stable tscc
prior to being tested
1738 27

Figure 28.
Special Function
Timing

CLOCK

ACEN
BCEN

00
015

ADOE
HADOE
HDOE
ADO
HAD
HD

1738 28

WAFERSCALE INTEGRATION, INC.

2·99

PAC1000

Pin Assignments
Figure 29.
88-Pin Ceramic
PGAPin
Assignments

A

B
C

D
E
F
G

H

J
K
L

1

2

3

4

5

6

7

8

9

0

0

0

0

0

0

0

0

0

0

DC'

GND

DCS

DC'

OC2

OCl

INT3

INTl

CC?

0

0

1/05

1107

0

0

0

CC2

DC?

DC.

0

0

0

HD'

1/06

0

0

1103

1104

0

0

1/01

1/02

0

0

1/00

0

fNR

0

IRD

0

cei2
0

GND

M 0
N

0
CC,

0

0

0

0

0

0

INT2

INTO

CC.

CCS

CCl

CCO

0

0
0

0

ADD11 ADDiO

0

GND

0

0

0

GND

ADD9

0

0

ADD7 A008

PAC1000

0

0

ADDS

ADDS

0

0

ADD3 ADD4

DGi3

0

0

0

ADOD

ADD2

0

aCiD

0

13

0
CC4

0

0

0

12

0

0

OC14

0
V~

ADDi3 ADD12

CK

0

oee

11

ADDiS ADD14

ICS

OGlS

0

OC4 IRESET

10

HADS

0

0

0

0

0

OC9

OCii

HD2

HD4

HD,

HD.

H010

0

0

0

0

0

0

0

0

v~

0

0

H014

0

HOD

HOl

GND

HDS

HD?

HD9

H01l

HDi2

HD13

1

2

3

4

5

6

7

8

9

0
V~

A

B
C

D
E
F
G

H

J
K
L

0

0

0

0

M

0

0

0

0

N

12

13

HADO HAD1 HAD3 HA04
HD15

GND

10

11

HAD2 ADDl

TOP (THROUGH PACKAGE) VIEW

13
A

0
CC,

B
C

D
E
F
G

H

J
K
L
M
N

12

0

co.

11

0
V~

10

9

8

6

5

0

0

0

0

0

0

0

0

INT1

INT3

OCl

OC2

DC'

OCS

GND

Dca

0

0

0

0

0

0

0

0

CCO

CCl

CCS

CC.

INTO

INT2

0

7

0
CC?

0

oeo

IRESET OC4

3

0

0

0

0

DC?

CC2

0

0

0

ADD12 ADDi3

0

0

AD09 GND

0

0

ADDS

ADD7

0

0

0

0
0

Vco

HADS

0

0

0

0

0

12

11

HAD2 GNO

0

0

0

HADO HD14 Vco

0

HD1S

10

0

0

9

8

HOB HD12

0

H010

0

0

HD.

0

0
HD'

0

0

HD4

0

0

HD2

0

H011

HD9

HD?

HDS

GND

7

6

5

4

3

BOTTOM VIEW

WAFERSCALE INTEGRATION, INC.

1/03

D

0

0

E

1/01

ICS

1100

0

F

0

0

G

tWR

GND

IRD

0

H

0

0

J

DGi3

Dei2

0

K

0

0

L

0

0

M

0

N

OCiO GND

0

HAD4 HAD3 HAD;

ADD1

C

1/04

0

ADD2 ADOO

0

0

OC14 GGiS

ADD4 ADD3

0

B

0

0

0

0

1/07

HD'

CK

ADDS ADDS

A

0

0

0

1

0

1/05

lID,

IID2

ADDiO ADDll

0

2

DC'

ADD14 ADDiS

13

2-100

4

DC1i

0

HOl

2

OC9
HOO

1

1738 29

PAC1000

Table 17.
PSAPin
Assignments

Name

Pin

Name

Pin

Name

Pin

CS
RD
RESET
WR
AD DO
ADD1
ADD10
ADD11
ADD12
ADD13
ADD14
ADD15
ADD2
ADD3
ADD4
ADD5
ADD6
ADD7
ADD8
ADD9
CCO
CC1
CC2
CC3
CC4
CC5
CC6
CC7
CK

F2
H1
B6
G1
K12
N13
E13
E12
D13
D12
C13
C12
K13
J12
J13
H12
H13
G12
G13
F13
B13
B12
B2
A13
A12
B11
B10
A10
G2

GND
GND
GND
GND
GND
GND
HADO
HAD1
HAD2
HAD3
HAD4
HAD5
HDO
HD1
HD10
HD11
HD12
HD13
HD14
HD15
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9

H2
L1
A3
F12
N3
N11
M10
M11
N12
M12
M13
L12
N1
N2
M7
N7
N8
N9
M9
N10
M3
C1
M4
N4
M5
N5
M6
N6

1100

F1
E1
E2
D1
D2
A1
C2
B1
B9
A9
B8
A8
B7
A7
L2
M2
K1
K2
J2
J1
A6
A5
B5

1/01
1/02
1/03
1/04
1/05
1/06
1/07

INTO
INT1
INT2
INT3
OCO
OC1
OC10
OC11
OC12
OC13
OC14
OC15
OC2
OC3
OC4
OC5
OC6
OC7
OC8
OC9
VCC
VCC
VCC

WAFERSCALE INTEGRATION, INC.

A4

B4
B3
A2
M1
A11
L13
M8

2·101

PAC1000

Figure 3D.
1oo-Pin Plastic Dr
Ceramic Quad
Flatpack
(QuI/wing) Pin
Assignments

89

13

I

(

26

76

-

64

38

39

51

63
1738 30

2·102

WAFERSCALE INTEGRATION, INC.

PACfOOO

Table 18.
PlasticDr
Ceramic Quad
Flatpack
(SuI/wing) Pin
Assignments

Pin

Name

Pin

Name

Pin

Name

Pin

Name

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

RD
GND
GND
OC15
OC14
OC12
OC13
GND
GND
OC10
OC9
OC11

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

HD11
HD12
VCC
VCC
HD13
HD14
HD15
HADO
GND
GND
HAD1
HAD2

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

ADD7
ADD8
ADD9
GND
GND
ADD10
ADD11
ADD12
ADD13
ADD14
ADD15
CCO
CC1
CC3
CC4
CC5
VCC
VCC
CC6
CC7
INTO
INT1
INT2
INT3
OCO

76

OC1
OC2
RESET

N/C
HDO
HD1
HD2
GND
GND
HD4
HD5
HD6
HD7
HD8
HD9
HD10

N/C
HAD3
ADD1
HAD4
HAD5
VCC
VCC
ADDO
ADD2
ADD3
ADD4
ADD5
ADD6

77

78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

N/C
OC3
OC4
OC5
OC6
GND
GND
OC7
OC8
CC2
105
107
106
HD3
104
103
102
101
CS
100
CK
WR

WAFERSCALE INTEGRATION, INC.

2-103

I'AC1DOO

InstructlDn Set
Overview

The PAC 1000 architecture can perform three
operations simultaneously in each instruction
cycle. The operations are specified in the
System Entry Language (PACSEL) using a
single statement. PACSEL instructions can
perform three operations:
CJ Program Control (PROGCNTL)
CJ

In some cases, the same mnemonic is used
to specify identical operations in both Macro
and Assembler level.
You may:
Specify all the components in the same
statement in order to perform the operations in parallel:

CJ

CPU

CJ Output Control (OUTCNTL)

PROGCNTL, CPU, OUTCNTL;

CJ

Each instruction is executed in a single cycle;
the three operations are executed in parallel.
The syntax of a PACSEL statement has a
label and three components:

CPU;
PROGCNTL;
OUTCNTL;

CJ
[label:J PROGCNTL, CPU,
OUTCNTL;

The PROGCNTL component determines
program flow and determines the next
statement to be executed; the CPU component determines which operation is to be
performed by the CPU; the OUTCNTL
component determines the state of the
control outputs.
A comma ( , ) is used to separate the instructions and a semi-colon marks the end of a
statement. In general, each statement is
executed in a single cycle.
In PACSEL statements, the PROGCNTL,
CPU, OUTCNTL components can come in
any order or any combination of Macro or
Assembler operators. That is, you may mix
Assembler operators among Macro operators. Tables at the end of this section summarize the Macro and Assembler operators.

2-104

WAFERSCALE INTEGRATION, INC.

Specify components one at a time:

Use components in any combination:
PROGCNTL, CPU;
PROGCNTL, OUTCNTL;
CPU, OUTCNTL;

WSI recommends that, in general, you
maintain a consistent ordering of these
components and consistent groupings of
Assembler-level and Macro operators, e.g. in
separate files. This manual uses the
PROGCNTL, CPU, OUTCNTL ordering.
When PROGCNTL is omitted, the implied
instruction is CONTinue, that is, proceed to
the next control instruction. When CPU is
omitted, the implied instruction is NOP. When
OUTCNTL is omitted, the implied instruction
is MAINTain, that is, maintain the most
recent OUTCTL, in Assembler order.
A summary of PACSEL Assembler and
Macro statements follows.

PAC1000

Table 19.
PACSEL
Assembler
Language
Summary

Mnemonic
Arguments
The PROGCNTL Operators

Meaning
SET A COUNTER SIZE

ACSIZE

<16/22>

CALL



UNCOND BRANCH SUBRTN

CALLC

 

COND BRANCH SUBRTN

CALLNC

 

INV COND BRANCH SUBRTN

CCASE

 

BRANCH SUBRTN CASEBLK

CLI



CLEAR INTERRUPT

CONT(D)

CONTINUE

CPI



DI



PRIORITIZED SUB RTN
DISABLE INTERRUPT
DISABLE SINGLE STEP MODE

DSS
EI



ENABLE INTERRUPT

JCase

 

UNCOND BRANCH CaseBLK

ESS

ENABLE SINGLE STEP MODE

JMP



UNCONDITIONAL BRANCH

JMPC

 

CONDITIONAL BRANCH
INVERT COND BRANCH

JMPNC

 

JPI



PRIORITIZED BRANCH

LDBP



LOAD BP REG

LDBPD
LDLC

LOAD BP COMP VALUE


LDLCD

LOAD COUNTER
LOAD CTR COMPUTED VAL

LOOPNZ



PLDLC



PLDLCD

REPEAT BRANCH,CNTRNZ
PUSH VALUE & LDCTR
PUSH VAL&LDCTR CM VL

POP

POP STACK

POPLC

POP STACK TO CNTR

PUSHLC

PUSH CNTR

RESTART

BRANCH TO 0

RET

RETURN

RC



CONDITIONAL RETURN

RNC



INV COND RETURN

RSTCON



RESET CONTROL REG

RSTIO



RESET I/O CON FIG REG

RSTMODE



RESET MODE REG

SETCON



SET CONTROL REG

SETIO



SET I/O CON FIG REG



SET MODE REG

SETMODE

WAFERSCALE INTEGRATION, INC.

2-105

fJ

PAC100D

Table 19.
PACSEL
Assembler
Language
Summary (Clln'tJ

Mnemonic
The CPU Operators
ADC
ADD
AND
CMP
DEC
INC
INV
MOV
NOP(D)
OR
RDFIFO
SBC
SHLRQ
SHLR
SHRRQ
SHRR
SUB
XOR
XNOR

Arguments

Meaning

  [J

ADD WITH CARRY

  [J

ADD

  [J

BITWISE AND

 

COMPARE

 [J

DECREMENT

 [J

INCREMENT

 [J

INVERT

 

MOVE SRC TODEST
NO OPERATION

  [J

BITWISE OR
READ FIFO DATA TO REG

  [J

SUB WITH CARRY

  

SHIFT LEFT REG & Q

 

SHIFT LEFT REG

  

SHIFT RIGHT REG & Q

 

SHIFT RIGHT REG

  [J

SUBTRACT

  [J

EXCLUSIVE OR

  [J

EXCLUSIVE NOR

The MACRO Operators
  
MUL
  
DIV

DIVISION
2'S COMP MULTIPLY

The OUTCNTL Operators
MAINT(D)
OUT

2-106

MAINTAIN PREV VALUE


WAFERSCALE INTEGRATION, INC.

OUTPUT

PAC10tJ0

Tab/e20.
PACSEL Macro

Language
Summar,

The PROGCNTL Operators
ACSIZE <16/22>
CALL  [ON]

[NOT]

[]

CASE n, PROGCNTL, CPU, OUTCNTL;
CLEAR  [ ... ]
CONFIGURE  [ ... ]
CONT
DISABLE  [ ... ]
ELSE
ENABLE  [ ... ]
END FOR
ENDIF
ENDPSWITCH
ENDSWITCH
ENDWHILE
FOR 
GOTO  [ON]

[NOT]

[]

IF [NOT] 
INPUT  [ ... ]
LOADBP 
OUTPUT  [ ... ]
PRIORITY m, PROGCNTL, CPU, OUTCNTL;
PSWITCH
RESET  [ ... ]
RETURN [ON]

[NOT]

[]

SET  [ ... ]
SWITCH 
WHILE [NOT] 

WAFERSCALE INTEGRATION, INC.
----

-----

----

Z·1111

PAC1000

Tab/e20.
PACSEL MaclD
Language

Summary (CDn't)

The CPU-Operator Assignment
move
 := 
arithmetic expression
 :=  <+/->  <+/-> 
logical expression
 :=   
increment, decrement, invert, unary minus
 :=  
macro expression
 :=  [* I /] 
shift RAM
 = Rx  
shift RAM and q


=

Q   Rx  

The OUTCNTL Operator
OUT  [ ... ]

2-108

WAFERSCALE INTEGRATION, INC.

PAC1000

System
Development
Tools

PAC1000 System Development Tools are a
complete set of PC-based development
tools. They provide an integrated easy-to-use
software and hardware environment to
support PAC1 000 development and programming.
The tools run on an IBM-XT, AT, PS2 or
compatible computer running MS-DOS
version 3.1 or later. The system must be
equipped with 640 Kbytes of RAM and a hard
disk.

Hardware
The PAC1000 System Programming Hardware consists of:

o

WS6000 MagicPro Memory and PSD
Programmer (XT, AT only)

o

Package Adaptors (88-Pin Ceramic PinGrid Array and 100-Pin Ceramic Quad
Flatpack-Gullwing) for the MagicPro
Remote Socket Adaptor Unit

The system design is entered into PACSEL
source program files using an editor chosen
by the user. PACSEL supports assemblylevel and high-level Macro programming.
The PACSEL Assembler produces object
code format in single or multiple modules,
which are then linked by the PACSEL Linker
into a single load file with a format suitable for
PACSIM and PACPRO.
The PACSIM functional simulator enables the
user to test and debug programs by examining the state of PAC1000 internal registers
before and during a complete functional
simulation of the device.
PACPRO software programs PAC1000
devices by using the MagicPro hardware and
the socket adapter.
The programmed PAC1000 is then ready to
be used.

Support

The MagicPro Programmer is the common
hardware platform for programming all WSI
programmable products. It consists of the
IBM-PC plug-in Programmer Board and the
Remote Socket Adaptor Unit.

WSI provides a complete set of quality
support services to registered owners. These
support services include the following:

Software
The PAC1000 System Development Software consists of the following:

o

WISPER Software-PSD Software Interface

o

IMPACT Software-Interface Manager
for PAC1000

o

PACSEL Software-System Entry
Language

o
o

PACSIM Software-Functional Simulator
PAC PRO Software-Device Programming Software

tools to be easily invoked by the user.

o

12-month Software Updates.

o

Hotline to WSI Application Experts-For
direct design assistance.

o

24-Hour Electronic Bulletin Board-For
design assistance via dial-up modem.

Training
WSI provides in-depth, hands-on workshops
for the PAC1 000 and the System Development Tools. Workshop participants will learn
how to develop and program their own highperformance microcontrollers. Workshops are
held at the WSI facility in Fremont, California.

WISPER and IMPACT software provide a
menu-driven user interface enabling other

WAFERSCALE INTEGRATION, INC.

2-109

PAC1DOO

Ordering
InfDrmatiDnPAC100D

Part Number

*.

2-110

Spsed
(MHz)

Package
Type

Package Operating
Drawing Temperature

Manufacturing
Procedure

PAC1000-12F*

12

100-Pin Ceramic
Quad Flatpack,
Gullwing

F3

Commercial

Standard

PAC1000-12FI*

12

100-Pin Ceramic
Quad Flatpack,
Gullwing

F3

Industrial

Standard

PAC1000-12FM*

12

100-Pin Ceramic
Quad Flatpack,
Gullwing

F3

Military

Standard

PAC1000-12FMB*

12

100-Pin Ceramic
Quad Flatpack,
Gullwing

F3

Military

MIL-STO-883C

PAC1000-12Q*

12

100-Pin Plastic
Quad Flatpack,
Gullwing

Q1

Commercial

Standard

PAC1000-12X

12

88-Pin Ceramic
Pin-Grid Array

X1

Commercial

Standard

PAC1000-12XI

12

88-Pin Ceramic
Pin-Grid Array

X1

Industrial

Standard

PAC1000-12XM

12

88-Pin Ceramic
Pin-Grid Array

X1

Military

Standard

PAC1000-12XMB

12

88-Pin Ceramic
Pin-Grid Array

X1

Military

MIL-STO-883C

PAC1000-16F*

16

100-Pin Ceramic
Quad Flatpack,
Gullwing

F3

Commercial

Standard

PAC1000-16FI*

16

100-Pin Ceramic
Quad Flatpack,
Gullwing

F3

Industrial

Standard

PAC1000-16FM*

16

1OO-Pin Ceramic
Quad Flatpack,
Gullwing

F3

Military

Standard

PAC1000-16FMB*

16

100-Pin Ceramic
Quad Flatpack,
Gullwing

F3

Military

MIL-STO-883C

PAC1000-16Q*

16

100-Pin Plastic
Quad Flatpack,
Gullwing

Q1

Commercial

Standard

PAC1000-16X

16

88-Pin Ceramic
Pin-Grid Array

X1

Commercial

Standard

PAC1000-16XI*

16

88-Pin Ceramic
Pin-Grid Array

X1

Industrial

Standard

PAC1000-16XM*

16

88-Pin Ceramic
Pin-Grid Array

X1

Military

Standard

PAC1000-16XMB*

16

88-Pin Ceramic
Pin-Grid Array

X1

Military

MIL-STO-883C

PAC1000-20F*

20

100-Pin Ceramic
Quad Flatpack,
Gullwing

F3

Commercial

Standard

PAC1000-20X*

20

88-Pin Ceramic
Pin-Grid Array

X1

Commercial

Standard

PAC1000-20Q*

20

100-Pin Plastic
Quad Flatpack,
Gullwing

Q1

Commercial

Standard

These products are advanced information.

WAFERSCALE INTEGRATION, INC.

PAC1000

Ordering
InformationSystem
Development
Tools

Part Number

Contents

PAC1000-GOLD

WISPER Software
IMPACT Software
PACSEL Software
PACSIM Software
PAC PRO Software
User's Manual
WSI-Support
WS6000 MagicPro Programmer

PAC1000-SILVER

WISPER Software
IMPACT Software
PACSEL Software
PACSIM Software
PACPRO Software
User's Manual
WSI-Support

WS6000

MagicPro Programmer
IBM PC plug-in Adaptor Card
Remote Socket Adaptor

WS6010

SS-Pin CPGA Adaptor
Used with the WS6000 MagicPro Programmer

WS6012

100-Pin Ceramic Quad Flatpack (Gullwing) Adaptor
Used with the WS6000 MagicPro Programmer

WSI-Support

WSI-Training

Support Services, including:
U

12-month Software Update Service

u
u

24-hour access to WSI Electronic Bulletin Board

Hotline to WSI Application Experts

Workshops at WSI, Fremont, CA
For details and scheduling, call PSD Marketing, (415) 656-5400

WAFERSCALE INTEGRATION, INC.

2-111

2-112

WAFERSCALE INTEGRATION, INC.

Programmable System™Device
WAFERSCALE INTEGRATION, INC.

SAM448 Introduction

User·Configurable Microsequencer
Overview

In 1988 WSI introduced a new concept in
programmable VLSI: the Programmable
System™ Device (PSD). The PSD is
defined as a family of User-configurable
system level building blocks on-a-chip
enabling quick implementation of application
specific controllers and peripherals. The
first generation PSD series includes the
MAP168, a User-Configurable Peripheral
with Memory; the SAM448, a UserConfigurable Microsequencer; and the
PAC 1000, a User-Configurable
Microcontroller.
The SAM448 is a microsequencer
intended for use in digital systems that
require events to be controlled at high
speed. A microsequencer is basically an
instruction oriented device executing one
internal instruction on each system cycle.
This can be done in a linear flow or the
sequencer can test the state of logic
inputs or internal events and respond to
program branching on a result. In addition,
it has the capability of driving output
signals on a cycle by cycle basis.

Microcode
EPROM
Architecture

blanking output controls for both line and
frame flyback. The device could also
control the load and shift activity in the
video output registers and supervise the
video memory address counters. All these
activities are sequential in nature so
microcode could be developed for the
SAM device and programmed into the
device's on-chip EPROM.
Prior to the development of the SAM448
Microsequencer, a designer would most
likely develop a system from discrete
EPROM or ROM plus 74LS TTL logic with
dedicated LIFO and registers. The actual
development of such a design would
escalate in chip count to eventually cover
an entire printed circuit card. With the
advent of Programmable Logic
Devices (PLDs), the development of a
microsequencing circuit became simpler.
However, a typical system still required five
to six PLDs. In addition, and EPROM was
needed to hold the microcode. Because
microcode is usually rather wide, a
number of EPROMs were needed.

The SAM448 can operate at a high clock
speed (30 MHz) so sequential operations
can be performed much faster than with
lower end microcontrollers. A classic
application of the SAM448 would be in the
generation of pulse waveforms for video
line and frame synchronization with

The SAM448 provides the optimum solution
when implementing a microsequencer of
medium complexity. It has been designed
to be cascadable in width and depth so
more complex microsequencer designs
may be achieved.

The core of the SAM448 is a microcode
EPROM organized as a 448 locations
deep and 36 bits wide. On each clock
cycle, the current 32 bit wide instruction is
clocked into the pipeline register. The 32
bit word is split into a number of fields.
The F field consists of 16 bits and drives
the output lines as user defined output
pins. The remaining 20 bits are subdivided

into one 8-bit Q field which generally
directs processing to the next address of
the EPROM. The 8-bit D field can be used
to hold a constant or direct value but it
can also be used for next address
generation. The OP field is three bits in
width and contains the current instruction
to be executed. The remaining field is the

WAFERSCALE INTEGRATION, INC.

2·113

fI

SAM448 Introduction

Microcode

EPROM
Architecture
(Cont.)

E field and performs a 3-State control
function on the pipeline register. When
HIGH, the output pins are enabled and
when LOW the outputs are in a high
impedance state. This feature enables one
SAM448 device to share the same outputs
with a second for vertical cascading.
The EPROM locations are connected such
that the first 192 locations (0 to 191) are in

a linear sequence. The remaining locations
are organized in four rows of 192 to 255.
This permits a one of four branch control.
The internal branch control logic will make
the decision as to which branch to take
depending on the state of the user defined
inputs and the value of the next state
address.

Branch
Control Logic

The branch control logic determines the
location from where the next instruction
will be fetched. The next address can
come from the Q or D field of the instruction
currently in the pipeline register, the top of

the stack or LIFO or the Branch Select
EPLD. The Branch Select EPLD can be
programmed to view inputs or the logical
combination of inputs to invoke a branch
when a logic state becomes true.

Stack

The stack or Last In First Out (LIFO)
memory is 15 locations deep and 8 bits
wide and can be used to hold the value of
a return address so successful CALL to
and RETURN from subroutines may be
invoked. A loop counter is included in the

SAM448 architecture and the stack can be
used to hold the contents of this loop
counter when nested loops are invoked.
The eight input lines may also be pushed
onto the stack to externally load the counter.

Loop Counter

To make provision for a number of
operations to be repeated a defined
number of times, a loop counter called
CREG has been included in the design.
This eight bit counter is loaded from the D

field by a dedicated instruction LOADC or
from the stack in the case of nested loops.
The counter decrements to zero and then
holds at zero. So repetitive routines may
be achieved by a LOOPNZ instruction.

Instruction Set

The instruction set for the SAM448 consists
of 12 instructions to handle multiway
branching, subroutines, nested for-next
loops and dispatch functions. With only 12
instructions a designer can become familiar

with creating SAM448 designs very quickly.
The WSI State Machine Input Language
(ASMILE) support software enables designs
to be generated quickly and efficiently.

2·114

WAFERSCALE INTEGRATION, INC.

Programmable System™Device
SAM448

WAFERSCALE INTEGRATION, INC.

User-Configurable MiclOsequencer
Features

I;J First Generation Programmable System

I;J Cascadable to Expand Outputs or States

Device

I;J Low-Power CMOS Technology

I;J User-Programmable Microsequencer for

I;J Footprint Efficient 28 Pin 300 Mil Dip or

Implementing High-Performance State
Machines

28 Lead CLDCC/PLDCC Package
I;J 30 MHz Minimum Clock Frequency

I;J On-Chip Reprogrammable EPROM

I;J High Level PC-XT/AT, PS2 or Compatible

Microcode Memory Up to 448
Words Deep
I;J 15 x 8 Stack
I;J Loop Counter
I;J Prioritized, Multi-Way Control Branching
I;J 8 General-Purpose Branch Control Inputs

Design Support Software (SAM + PLUS):
- WSI PSD Integrated Software
Environment
- State Machine Input Language
- Microcode Assembler
- Functional Simulator

I;J 16 General-Purpose Control Outputs

Description

words) is integrated with Branch Control
Logic, Pipeline Register, Stack, and Loop
Counter. This generic microcoded architecture
provides an efficient vehicle for implementing
a broad range of high performance controllers
spanning the spectrum from basic state
machines to traditional bit-slice controller
applications.

In 1988 WSI introduced a new concept in
programmable VLSI, Programmable
System1M Devices (PSD). The PSD is
defined as a family of User-configurable
system level building blocks on-a-chip
enabling quick implementation of application
specific controllers and peripherals. The first
generation PSD series includes the
MAP168, a User-Configurable Peripheral
with Memory; the SAM448, a UserConfigurable Microsequencer; and the
PAC1000, a User-Configurable
Microcontroller.
The SAM448 is a first generation PSD
and is WSI's first user programmable
microsequencer. On-Chip EPROM (up to 448

The SAM448 has eight general purpose
input pins, a clock pin and a reset pin.
It has 16 user-definable outputs packaged in
a 28-pin 300 mil Dip or 28 Lead CLDCCI
PLDCC package. One:rime-Programmable
plastic versions are available to minimize
volume production costs.

Pin Configuration
(Top View)

Leaded Chip Caflier

Dual·ln·Line

....
w

ffi

F,.
F,.

Vee
"RESET

F'2
Fll
F,o
Fo.
Fo.
GND
F07
F••
F••

F04

_N

4

0

3

2

~

c.> ...

0

.

~

1282726

I,

I.
17
F,.

0

I.

F••
F.,
F.2
F..

F,.
F,.
F'2
Fll

F••

F••
II)

""L.:.;;......_;.;;..t'F.2

II:

..:' c>

:g

s:

C

•

Cb

0

LElLlLt5ae~u:-

WAFERSCALE INTEGRATION, INC.

2·115

SAM44B

Description
(Cont.)

Programming the SAM448 device is
accomplished on a standard WSI PSD
WISPER development system installed
with the optional SAM+PLUS software
package and device adapters. New users
can purchase a separate WISPER-SAM
development system with programming
hardware included. SAM+PLUS allows
designs to be entered in either state
machine or microcoded formats.
SAM+PLUS automatically performs logic
minimization and design fitting for the
device. The design may then be simulated
or programmed directly to achieve
customized working silicon within minutes.

machines. SAM's internal EPROM memory
together with its Pipeline Register allows
storage of up to 448 unique states. SAM's
Branch Control Logic allows single clock,
multi-way branching in response to the
eight inputs, current device state, and
user-defined transition conditions. Design
entry is simplified with WSI's State Machine
Input Language (ASMILE) supported by
the SAM+PLUS development system. This
high level language uses IFTHEN-ELSE
statements to define state transitions and a
truth table to define or tri-state the outputs
on a state-by-state basis.

Using WSI's proprietary high performance
CMOS EPROM technology allows SAM448
to operate at a 25-MHz typical clock
frequency while still enjoying the benefits
of low CMOS power consumption. This
technology also facilitates 100% generic
testability which eliminates the need for
post-programming testing.

SAM's architecture has several advanced
features that enable it to be used as a
sophisticated microcoded sequencer.
SAM's on-chip EPROM (448 words) is
integrated with a microcoded sequencer
conSisting of Branch Control Logic, Stack,
and Loop Counter. The eight generalpurpose inputs, the Counter, the Stack,
and the Pipeline Register feed the Branch
Control Logic. The Branch Control Logic
gives flexible multi-way microcode branch
capability in a single clock, enhancing
throughput beyond that of conventional
controllers or sequencers.

Ideal application areas for SAM448 include
programmable sequence generators (state
machines), bus and memory control
functions, graphics and DSP algorithm
controllers, and other complex, high
performance machines. The devices may
be cascaded easily to obtain greater
output requirements (horizontal cascade)
or greater microcooe memory depth
(vertical cascade) or both.

SAM as a State Machine
The SAM448 architecture allows easy
implementation of synchronous state

Functional
DescrIption

2·116

SAM as a Microcoded Sequencer

SAM+PLUS development software offers
high level microcode entry featuring a
compact assortment of powerful instructions
(OP-codes) allowing easy implementation
of conditional branches, subroutine calls,
multiple level for-next loops, and dispatch
functions (branching to an externally
specified address).

The SAM architecture is shown in Figure 1.
The primary elements are the Microcode
EPROM, 36-bit Pipeline Register, Branch
Control Logic, 15 x 8-bit Stack, and 8-bit
Loop Counter.

Control Logic to generate the new nextstate address.

The Branch Control Logic generates the
address of the next state and applies this
address to the Microcode Memory. The
outputs of the Microcode Memory
represent the user-defined outputs ~nd
internal control values associated w th the
next state. On the leading edge of e
clock these new values are clock t:I into
the Pipeline Register and bec e the
current state. The new values in the
Pipeline Register-along with the Counter,
Stack and Inputs-are used by the Branch

The Microcode EPROM is organized into
448, 36-bit words or locations, each of
which can be viewed as a single state. 16
of these bits (the F-field) are available at
device pins as user-defined outputs.

WAFERSCALE INTEGRATION, INC.

Microcode EPROM and Pipeline Register

The other 20 bits are internal control
signals that are divided into 4 fields: the
8-bit Q-field normally provides the nextstate address; the 8-bit D-field is a general
purpose field used either as a constant or
as an alternative next-state address; the
OP-field contains the instruction; and, the

SAM448

Functional
Description
(Cont.)

E-field contains a single bit which enables
or tri-states the device outputs.

As shown in Figure 2, the Microcode
Memory is organized as 256 rows or
addresses. Addresses 0 through 191
contain a single 36-bit word which is
associated with the desired next-state. This
state information will be clocked into the
Pipeline Register on the next rising edge
of the clock and the outputs will become
valid one Tco (clock to output delay) later.

Figure 1.
SAM448 Block
Diagram

Addresses 192-255, on the other hand,
access four unique 36-bit words which
correspond to four possible next states.
(The extension .0, .1, .2, and .3 are used to
distinguish those four states.) These 64
addresses are known as Multi-Way Branch
locations and are used to perform single
clock 4-way branches. Whenever the nextstate address falls within the Multi-Way
Branch locations, the Branch Control Logic
will make the necessary 1-of-4 selection
based on the next-state address and userdefined input conditions.

ZERO

NRESET

MICROCODE
EPROM

BRANCH
CONTROL
lOGIC

INPUTS
(8)

EPlD
768 PRODUCT
TERMS
ClK

Figure 2.
SAM Microcode
Memory

ADDRESS

~

.:-NEXT STATE
ADDRESS FR=Y0M
BRANCH
CONTROL
8

:

~

MULTI-WAY BRANCH lOCATIONS

1
1 .2
194.

193.

1 OF 4 BRANCH
SELECT FROM
BRANCH
CONTROL
SYSTEM
CLOCK

_--~4L--+r==:==========~~~~~~~~~========~~~
F,-F1S OUTPUTS

WAFERSCALE INTEGRATION, INC.

2-117

SAM448

Figure 3.
SAM Branch
Control Logic

ZERO
FLAG

OPCODE

BRANCH SELECT
EPLD
ADDRESS
MULTIPLEXER

NEXT-STATE
ADDRESS

8

Branch Control Logic Block
At the heart of the high-performance
sequencing ability of the SAM family is the
Branch Control Logic. This block determines
the next-state to be clocked into the Pipeline
Register based on the current status of the
Pipeline Register, the Counter, the Stack,
and the eight input pins.
The Branch Control Logic is divided into
two segments: the Address Multiplexer and
the Branch Select EPLD.
The Address Multiplexer provides the nextstate address to the Microcoded Memory.
The next-state address can come from the
Q-field, the D-field, or the Top-of-Stack.
The selection between these three
resources is based on the instruction in
the Pipeline Register and the condition of
the Zero Flag from the Counter.
The Branch Select EPLD is used to
perform up to a 4-way branch based on
user-defined input conditions. This block is
a 768 product-term programmable logic
device with 16 inputs and four outputs.
When the next-state address falls within
the multi-way branch block of memory (any
address greater than 191) the Branch
Select EPLD performs the necessary 1-of-4
selection. When the next-state address is
less than 192, the Branch Select EPLD is
turned off since no selection is required.
The conditions controlling the multi-way
branch are defined by the user with a
simple IF, THEN, ELSE format like the
following:
IF (cond3) THEN select 201.3
ELSEIF (cond2) THEN select 201.2
ELSEIF (cond1) THEN select 201.1
ELSE
select 201.0

2-118

WAFERSCALE INTEGRATION, INC.

4

INPUTS

(10-17)

8

1-01'-4
BRANCH
SELECT

768
PRODUCT TERMS

The conditions are prioritized so that if the
first condition is not met (cond3), then
microword 201.3 will be selected and
clocked into the Pipeline Register regardless
of the results of cond2 and cond1. If none
of the three conditions are met, then the
microword 201.0 will be clocked into the
Pipeline Register.
The three conditional expressions are user
defined and may contain any logical
equation based on the inputs that can be
reduced to four product-terms. For
example, the expression

11 * 112 * 114
+13 * 114 * 115 * 116 * 117
+10
+12 * 114 * 115
contains four product-terms and is a valid
condition. There is a unique set of 12
product-terms for each of the 64 multi-way
branch locations for a total of 768 productterms. (See Figure 4.)
The SAM448 has been designed so that
the number of available product-terms
should never be the limiting factor on a
design. Prioritization provides an effective
product-term count of more than 12 per
location. A trade-off between number of
product-terms and number of possible
branches can be made by simply placing
identical state information in two locations
as shown in Figure 5.

SAM448

Figure 4.
SAM Branch
Logic for
Address 192
Through 255

PROGRAMMABLE
LOGIC

PRIORITY
ENCODER

ro-

~P

SELECT 3

g

gD-~
D

:g

SELECT 1

-DD~

-D
SELECT 0
10 11

12 13 14 15 16 17
INPUTS

J:3::)-

Figure 5.
Multi·way
Branching

4-WAY BRANCH

3-WAY BRANCH

WAFERSCALE INTEGRATION, INC.

Z-ff9

SAM448

Functional
Description
(Cont.)

Stack

Loop Counter

The Stack of the SAM448 is a Last In First
Out (LIFO) arrangement consisting of 15
8-bit words. The Top-of-Stack may be used
as the next-state address or popped into
the Counter. Values may be pushed onto
the stack either from the D-field in the
Pipeline Register or from the Counter
enabling efficient implementation of
subroutines, nested loops, and other
iterative structures. The eight input lines
may also be pushed onto the stack to
allow external address specification in a
dispatch function or to externally load the
counter.

The SAM448 contains an 8-bit Loop
Counter, referred to as the Count Register
(CREG), which is useful for controlling
timing loops and affecting a variety of
branch operations. The CREG is a down
counter and may be loaded directly from
the D-field of the Pipeline Register or from
the Top-of-Stack. The value of the CREG
may be saved and restored by pushing
and popping it to and from the Stack.

The PUSHing or POPing of the stack
occurs on the leading edge of the clock.
The stack is "zero filled" so that a POP
from an empty stack will return all eight
bits set to zero. On the other hand, a push
to an already full stack will write over the
Top-ot-Stack leaving the other 14 values
unchanged.

The CREG is loaded or decremented on
the leading edge of the clock. It is
designed so that it will not decrement
once it reaches zero to prevent roll-over. A
Zero Flag indicates when the counter has
reached zero and is used with the
LOOPNZ command to control program
flow (see Instruction Set Description).
Single instruction delay loops are easily
constructed and, in combination with the
Stack, nested loops or delays of arbitrary
length may be generated.

Instruction Set

The instruction set of the SAM448 consists
of a compact assortment of powerful
commands. Assembly language constructs
allow efficient implementation of multi-way
branching, subroutines, nested for-next
loops, and dispatch functions. The complete

instruction set is described at the end of
this d/l.ta sheet. These instructions are
only used with assembly language design
entry and are automatically supplied when
using the WSI State Machine Input
Language (ASMILE).

Output Enable
Control

Each microcode word contains an OE bit
(the E-field) which enables the outputs
when E = 1 and causes a high-impedance
when E = O. These bits are accessible

through high-level constructs in the WSI
Development Software. This capability
allows the vertical cascading of SAM448
devices to increase the number of states.

nRESET Pin

The nRESET pin acts as a master reset
for the SAM448 causing it to empty the
Stack, clear the Counter, and load the
microword found at address 0 into the
Pipeline Register. The nRESET signal is
useful for system reset or for synchronizing
several SAMs that are cascaded vertically
or horizontally.

a valid clear. A nRESET of one clock
rising edge causes the SAM448 to enter
into a supervisor mode and a nRESET of
two clock edges results in an undefined
state.

The nRESET signal must be held low for
at least three clock rising edges to perform

Horizontal and
Vertical
Cascading

2·120

Just as with memory and bit slice devices,
the SAM devices can be cascaded to
provide greater functionality. If an application
requires more output lines, two or more
SAMs can be cascaded horizontally.
Likewise, if an application requires more

WAFERSCALE INTEGRATION, INC.

The outputs of the boot address (00 Hex)
will appear at the pins from the fourth
clock edge after nRESET goes low, until
the third clock edge after nRESET returns
to high.
states, two or more SAMs can be cascaded
vertically. In either case, no speed penalty
is incurred. Designs utilizing horizontal
cascading are fully supported by the
SAM+PLUS development software. Vertical
cascading requires the designer to make
certain tradeoffs to split the design.

SAM448

Figure 6.
SAM448
Cascading

INPUTS

INPUTS
~----.-- CLOCK

SAM448

CONTROL OUTPUTS (2N)

HORIZONTAL CASCADE

INPUTS
SAM448

N

N

CONTROL
OUTPUTS
(N)

CLOCK
SAM448

N

INPUTS

VERTICAL CASCADE

Functional
Testing

The SAM448 is fully functionally tested
and guaranteed through complete testing
of each programmable EPROM bit and all
internal logic elements thus ensuring
100% programming yield.
The erasable nature of the SAM448 allows
test programs to be used and then erased
during early stages of production flow. This

Recommended
Operating
Conditions

Symbol

Parameter

facility to use application-independent,
general purpose tests is called generic
testing and is unique among user-defined
LSI logic devices. The devices also
contain on board test circuitry to allow
verification of function and AC specification
once encapsulated in non-windowed
packages.

Conditions

Min

Max

Note 6

4.75 (4.5)

5.25 (5.5)

V

0

Vee

V

0

Input Rise Time (Note 6)

Vee
500 (100)

ns

Input Fall Time (Note 6)

500 (100)

ns

vee

Supply Voltage

VI

Input Voltage

Va

Output Voltage

TR
TF

WAFERSCALE INTEGRATION, INC.
-----------

---~----------

Unit

V

2·121

-----

SAM448

DC Operating
Characteristics

Vee = 5V ± 5%, O°C to +70°C for Commercial
Vee = 5V ± 10%, -40°C to +85°C for Industrial
Vee = 5V ± 10%, -55°C to +125°C for Military

Symbol

Absolute
Maximum
Ratings
(See Design
Recommendations)

Capacitance
(Note 3)

2·122

Parameter

Conditions

Min

Typ

Max

Unit

V IH

High Level Input Voltage

2.0

Vee +0.3

V

V IL

Low Level Input Voltage

-0.3

0.8

V

VOH

High Level TTL Output
Voltage

10H

=

-8 mA DC

2.4

V

VOH

High Level CMOS
Output Voltage

10H

=

-4 mA DC

3.84

V

VOL

Low Level TTL Output
Voltage

10L = 8 mA (4 mA) DC

0.45

V

II

Input Leakage Current

VI = Vee or GND

±10

IlA

loz

3-State Output Off-State
Current

Vo = Vee or GND

±10

IlA

lee1

Vee Supply Curent
(Standby) (Note 6)

V 1 = Vee or GND
10 = 0 CLK = Vee

30

65 (90)

mA

lee2

Vee Supply Current
(Active) (Note 6)

No Load 50% CLK
f = 20 MHz

55

120 (170)

mA

Symbol
vee

Parameter

Conditions

Supply Voltage
With Respect to GND
(Note 2)

Min

Max

Unit

-2.0

7.0

V
V

Vpp

Programming Supply Voltage

-2.0

14.0

VI

DC Input Voltage

-2.0

7.0

V

leeMAx

DC Vee or GND Current

-250

250

mA

lOUT

DC Output Current, per Pin

-25

PD

Power Dissipation

25

mA

1200

mW

T STG

Storage Temperature

No Bias

-65

150

°C

TAMB

Ambient Temperature

Under Bias

-10

85

°C

Symbol

Parameter

Conditions

Typ

Unit

CIN

Input Capacitance

V IN = OV
f = 1.0 MHz

10

pF

COUT

Output Capacitance

VOUT = OV
f = 1.0 MHz

15

pF

CeLK

Clock Pin Capacitance

V IN = OV
f = 1.0 MHz

10

pF

C RST

nRESET Pin Capacitance

75

pF

WAFERSCALE INTEGRATION, INC.

SAM448

AC
Characteristics

Vcc
Vee
Vce

5V ± 5%, O°C to +70°C for Commercial
5V ± 10%, -40°C to +85°C for Industrial
5V ± 10%, -55°C to +125°C for Military (Note 7)

Symbol

Parameter

fCYC

Maximum Frequency

Conditions
C,

= 35 pF

SAM448-30

SAM448-25

SAM448-20

Min Max Min Max Min Max
30

25

MHz

tCYC

Minimum Clock Cycle

tsu

Input Setup Time

16.5

20

22

ns

tH

Input Hold Time

0

0

0

ns

tco

Clock to Output Delay

tcz

Clock to Output
Disable or Enable

tCl

Minimum Clock
Low Time

11

12

15

ns

tCH

Minimum Clock
High Time

11

12

15

ns

tSUR

nRESET Setup Time

16.5

18

18

ns

tHR

nRESET Hold Time

5

5

5

ns

C,

33.3

20

Unit

= 35 pF

40

50

ns

16.5

20

22

ns

16.5

20

22

ns

NOTES: 1. TYPical values are for T A = 25°C, Vee = 5V.
2. Minimum DC input is -0.3V. During transitions, the inputs may undershoot to -2.0V for periods
less than 20 ns.
3. Capacitance measured at 25°C. Sample tested only.
4. If the nRESET is held low for more than 3 clock edges, then the outputs associated with the boot
address (00 Hex) will remain at the pins until the third clock edge after nRESET goes high.
5. For 1.0 < V, < 3.8, the nRESET pin will source up to 200 ~A.
6. Figures In ( ) pertain to military and Industrial temperature versions.
7. The specifications noted above apply to military operating range devices. MIL-STD-883 compliant
product specifications are provided in military product drawings available on request from WSI
marketing at Tel. 415-656-5400. These military product drawings should be used for the preparation
of source control drawings.

Figure 7.
Timing
Waveforms

tFj" r--tCL~= ~tCH-=j

CLOCK

tR1 ~
\'------JV1r------..,,-

31

~

~tSU-+tH-1

INr.~~
OUTPUT
F.-F'5

==x

VALID INPUT

rI

X. . .__________

..:.I_ _ _ _ _ _ __

tc0

----1

~tcz=:i
OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Fo-F15

I

X,.-------:-I-~tcz-----j

-J)~--~H~IG~H~-~IM~P~E~DA~N~C~E~3~-S~T.~~~~E~_ _~C
.

WAFERSCALE INTEGRATION, INC.

2-123

SAM448

Figure B.
Reset Timing
Waveforms

CLOCK

~URj
"RESET \

r
1

'--1-------

1c°4

r-

OU~~~------~)(~___________I_N_VA_L_ID_O_U_T_PU_T___________J)(r--------F--(O-~--------'~NOTE4

L

COUNTER AND
STACK CLEARED

Design Security

The SAM448 contains a programmable
design security feature that controls the
access to the data programmed into the
device. If this programmable feature is
used, a proprietary design implemented in
the device cannot be copied nor retrieved.

This enables a high level of design control
to be obtained since programmed data
within EPROM cells in invisible. The bit
that controls this function, along with all
other program data, may be reset simply
by erasing the device.

Design
Recommendations

Operation of the SAM448 with conditions
above those listed under "Absolute
Maximum Ratings" may cause permanent
damage to the device. This is a stress
rating only, and functional operation of the
device at these or any other conditions
above those indicated in the operational
sections of this data sheet is not implied.
Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability. These devices contain
circuitry to protect the input against
damage to high static voltages or electric
fields; however, it is advised that normal
precautions be taken to avoid application
of any voltage higher than maximum rated
voltages to this high-impedance circuit.

be constrained to the range GND ,;;; (VIN or
VOUT) ,;;; Vee· Unused inputs must always
be tied to an appropriate logic level (e.g.,
either Vee or GND). A power supply
decoupling capacitor of at least 0.1 IlF
must be connected directly between the
Vee pin and GND.

For proper operation, it is recommended
that opaque labels be placed over the
device window. Input and output pins must

2·124

WAFERSCALE INTEGRATION, INC.

When operating in noisy environments it is
possible that a glitch on the nRESET pin
one TSUR before the clock edge could
initiate a supervisor mode. To prevent this
possibility, it is recommended to connect a
capacitor of at least 0.1 IlF from the
nRESET input to ground.
All general purpose inputs to the SAM448
should be synchronized to be guaranteed
to meet the setup time. Input tr.ansitions
which occur less than one Tsu before the
leading clock edge can cause the SAM448
to enter an undefined state.

SAM448

Figure 9. Output
Drive Current

...
~
~

C
S.

!z
II!
!!i
CJ

~

100
80
60

40

20

110110

8

6
4

:::>

o

Vee
TA

2

= S.OV
= 2S"C

o

2

4

5

Vo OUTPUT VOLTAGE (V)

InstructiDn Set
DescriptiDn

Following is a description of the instruction
set available with the SAM448. These
instructions can be used in conjunction
with the Assembly Language entry to
access the various features of the SAM448.
They are automatically supplied when
using the WSI State Machine Input
Language (ASMILE).
In the following description label1 and
label2 indicate arbitrary labels located in
the assembly (.ASM) file. These labels will
be converted by the software into the 8-bit
address of that label. The parameter
constant is any 8-bit number (0-255
Decimal, O-FF Hex) representing an
address, a mask, or a constant.
The instructions influence the control of
the Stack, the Counter, and the Address

CONTINUE simply causes execution
to continue with the next sequential
instruction found in the Assembly
Language file (.ASM).

Multiplexer. These effects are summarized
in the Instruction Table. Throughout the
examples it is assumed for simplicity that
the destination labels do not lie within the
Multi-Way Branch Block of memory so that
branching based on inputs is not
performed. It is valid, however, for any of
these labels to lie within the Multi-Way
Branch Block so that 4-way branching
based on the inputs can be performed.
See the MULTI-WAY BRANCH section at
the end of this data sheet for more details.
The SAM+PLUS development system
allows the designer to use the high level
Assembly Language without worrying
about the actual values that are placed in
the various fields.

CONTINUE

WAFERSCALE INTEGRATION, INC.
----------

---

2-125

SAM44B

Instruction Set
Description
(Cont.)

The JUMP instruction causes execution to
branch to the indicated location. If address
44 contains the instruction ~UMP label1,'
then the next state will come from label1
which in this case is located at address 73.

The CALL/RETURNTO instruction is
typically used to call a subroutine. In
general it will push the address of label2
onto the Stack and cause label1 to be the
next-state address. Leaving the RETURNTO
designation off will cause label2 to default
to the next instruction in the .ASM file. In
the example, address 44 contains the
command 'CALL label1' where label1 is
located at address 73. This causes the
address of the following instruction, in this
case 45, to be pushed onto the Stack, and
the next state to come from address 73.
The RETURN command at address 75
returns the execution to address 45.

The RETURN command is used to return
from a subroutine call or in general to
cause the next-state address to come from
the top of the Stack. In the example, the
command at address 44 CALLed the
subroutine at address 73 and PUSHed the
value 45 onto the Stack. The RETURN
command at address 75 will transfer
execution to address 45 and POP that
value off the Stack.

2-126

WAFERSCALE INTEGRATION, INC.

JUMP label1

CALL label1 RETURNTO label2

45

-0

STACK (PUSH)

RETURN

-e

STACK (POP)

SAM448

Instruction Set
Description
(Cont.)

The LOAD Counter command loads the
Counter with the value specified and
transfers execution to label1. The LOADC
command is typically used to initialize the
Counter for a repetitive loop. In the
example, address 44 has the command
'LOADC 73D GOTO label1' which causes
the decimal value 73 to be loaded into the
Counter and the next state to come from
label1. In this case label1 is located at
address 73. If the GOTO designation is left
off label1 will default to the next instruction
in the .ASM file.

The LOOP on Non-Zero/ON ZERO goto
command jumps to one of two addresses
based on the value of the Zero Flag and
decrements the Counter if not zero. This
instruction is typically used to implement
for-next loops. In the example, address 44
has the command 'LOOPNZ label1
ONZERO label2' where label1 is located
at address 42 and label2 is located at
address 73. If the Counter is not at zero
then the next state will come from address
42 and the Counter will be decremented. If
the Counter is already at zero then the
instruction at address 73 will be executed
and the Counter will stay at zero. If the
ONZERO designation is left off, the default
for label2 will be the next instruction in the
.ASM file.

The DEcrement Counter on Non-Zero
GOTO command will decrement the
Counter if it is non-zero and jump to
label1. In the example, address 44 has the
command 'DECNZ GOTO label1' where
label1 is located at address 73. The
Counter is decremented and the next
instruction comes from address 73. The
default for label1 is the next instruction in
the .ASM file.

LOADC constant GOm label1

CONST

-0

CREG (LOAD)

LOOPNZ label1 ONZERO label2

N-l

-0

CREG (DEC)

DECNZ GOTO label1

N-l

-0

CREG (DEC)

WAFERSCALE INTEGRATION, INC.

2-127

SAM448

Instruction Set
Description
(CDnt.)

The PUSH Counter LOAD Counter
command will push the current value of
the Counter onto the Stack, load a
constant into the Counter, and jump to
label1. This instruction is useful for
implementing nested for-next loops. In the
example, the instruction at address 44 is
'PUSHLOADC 153D GOTO label1' where
label1 is located at address 73. The value
in the Counter will be pushed onto the
Stack, the decimal value 153 will be
loaded into the Counter, and the next
instruction will come from address 73. The
default for label1 is the next instruction in
the .ASM file.

The POP Stack to Counter GOTO
command will pop the top of Stack into
the Counter and jump to label1. This
command is typically used in conjunction
with the PUSHLOADC to implement
nested for-next loops. In the example,
address 44 has the command 'POPC
GOTO label1' where label1 is located at
address 73. The default for label1 is the
next instruction in the .ASM file.

The PUSH constant to Stack GOTO
command will push the value constant
onto the Stack and jump to label1. In the
example, address 44 has the command
'PUSH 34D GOTO label1' where label1 is
located at address 73. The decimal value
34 is pushed onto the Stack and the next
state comes from address 73. The default
for label1 is the next instruction in the
.ASM file.

2-128

WAFERSCALE INTEGRATION, INC.

PUSHLOADC constant GOTO label1

CONST ~ CREG (LOAD)

6

I---~

STACK (PUSH)

PO PC GOTO label1

~

6

STACK (POP)

CREG (LOAD)

PUSH constant GOTO label1

CONST

-0

STACK (PUSH)

SAM448

Instruction Set
Description
(Cont.)

The PUSH Input GOTO command will push
the eight inputs (17-10) onto the Stack. In
the example address 44 has the instruction
'PUSH I GOTO label1' where label1 is located
at address 73. At the leading edge of the
clock the eight inputs are pushed onto the
Stack. In a typical example, address 73
would have a RETURN instruction which
would cause execution to jump to the
address represented by the recently
PUSHed input pins. This implements a
dispatch function. The default for label1
will be the next instruction in the .ASM file.
This instruction can also be used to load
the Counter with an externally specified
variable. In this case address 73 would
have a POPC instruction.

The AND PUSH Input GOTO command is
identical to the PUSH I command except
the inputs are first bit-wise ANDed with a
constant. This allows the masking of
irrelevant inputs before PUSHing an
address for a dispatch routine.

PUSHI GOTO label1

INPUT

l
U

STACK (PUSH)

ANDPUSHI constant GOTO label1

CONST~

""" 6
STACK (PUSH)

The POP and XOR Stack to Counter
GOTO command will pop the top of Stack,
bitwise XOR it with a constant, load the
result into the Counter, and jump to label1.
In the example, address 44 has the
command 'POPXORC 250 GOTO label1'
where label1 is located at address 73. The
top of Stack is POPed off the Stack,
XORed with the decimal number 25, and
loaded into the Counter. The next state
comes from address 73. Since a XOR
function does a comparison, this
command can be used to compare the
input to a constant and then branch based
on the result with a LOOPNZ command. If
the GOTO designation is left off the default
for label1 will be the next instruction in the
.ASM file.

POPXORC constant GOTO label1

1~1----1 CONST
73

~

0

CREG (LOAD)

WAFERSCALE INTEGRATION, INC.

2·129

SAM448

Figure 10.
Instruction Set
Summary

Instruction

Definition

Next·State
Address

Stack

Counter

CONTINUE

Continue with Next Instruction

label1

None

HOLD

JUMP

Jump to a Label

label1

None

HOLD

CALL

Call Subroutine

label1

label2

HOLD

RETURN

Return From Subroutine

STACK

POP

HOLD

LOADC

Load CREG

label1

None

Constant

LOOPNZ

Loop/Dec. on Non-Zero

label 1 or 2

None

DECREMENT

DECNZ

Decrement CREG on Non-Zero

label1

None

DECREMENT

PUSHLOADC

Push CREG to Stack and
Load CREG

label1

CREG

Constant

POPC

Pop Stack to CREG

label1

POP

STACK

PUSH

Push Constant to Stack

label1

Constant

HOLD

PUSHI

Push Inputs to Stack

label1

INPUTS

HOLD

ANDPUSHI

Push Masked Inputs to Stack

label1

INP * const

HOLD

POPXORC

XOR Stack with Constant
and Send Result to CREG

label1

POP

STACK<±)
Constant

NOTE: The value label 1 is placed

Multi-Way
Branching

In

the Q-field. The values label2 and constant are placed in the D-fleld.

The multi-way branching capability can be
super imposed upon the instruction set
providing another dimension of capability.
Figure 11 shows how this translates into
the flow diagrams. If location 44 had the
instruction 'JUMP label1' where label1 is
located at address 201, then the next-state
would come from address 201. But address
201 is within the Multi-Way Branch Block
so the Branch Select EPLO must decide
which of the four words to send to the
pipeline register. This selection is based
on user-defined functions of the inputs.
Similarly, location 44 could contain any of
the 13 available commands so that the

Figure ".
Jump to a
Multi-Way
Branch Address

201.3
201.2
201.1
201.0

2-130

WAFERSCALE INTEGRATION, INC.

mUlti-way branch capability can enhance
each instruction. If location 44 was a CALL
to a subroutine, then address 201 could
contain the starting instruction for 4 unique
subroutines. The actual routine executed
would depend on the condition of the
inputs as defined by the user.
The actual Assembly Language code
required to implement this example is as
follows:
440: [Output Spec] CALL label1;
2010: IF cond1 THEN [out 1] JUMP 1020;
ELSEIF cond2 THEN [out 2] JUMP 730;
ELSEIF cond3 THEN [out 3] JUMP 530;
ELSE [out 4] JUMP 340;

SAM448

Figure 12.
AC Test
Conditions

+5V

427Q

DEVICE
OUTPUT

TO TEST
SYSTEM

1

C, (INCWDES JIG
CAPACITANCE)

1700

~

DEVICE INPUT
RISE AND FALL
TIMES <6 no

Power supply transients can affect AC measurements; simultaneous transitions of multiple
outputs should be avoided for accurate measurement. Do not attempt to perform
threshold tests under AC conditions. Large amplitude, fast ground current transients
normally occur as the device outputs discharge the load capacitances. These transients
flowing through the parasitic inductance between the device ground pin and the test
system ground can create significant reductions in observable input noise immunity.

Figure 13.
Icc vs. FMAX

90r---------------------~
Vee = 5.0V

TA = 25°C

0:

>

...

70

1
w

>

~

II

50

10 M
1k

10 k

100 k

1M

30 M

MAXIMUM FREQUENCY (Hz)

Product Grades

Application
Commercial

Temperature Range

Marking Designator

O°C to +70°C

Industrial

-40°C to +85°C

I

Military

-55°C to + 125°C

M

MIL-STD-883C, Class B

-55°C to +125°C

MB

WAFERSCALE INTEGRATION, INC.

2-131

2·132

WAFERSCALE INTEGRATION, INC.

-- - - -....,....-----,. .....
----------.....
=~~ ==~

SAM448

~~

System
Development Tools

----~.-..

WAFERSCALE INTEGRATION, INC.

SAM system development tools are a
complete set of PC-based development
tools for the SAM448. Installed on an IBMXT, AT or compatible computer, these tools
provide an integrated easy-to-use software
and hardware environment to support
SAM448 development. These tools may be

purchased as a complete development
system or as individual software and
hardware products. SAM system
development tools contain all necessary
programming hardware and software
required to build high-performance state
machines.

I

Host
Requirements

The host system requirements for installing
and using the SAM448 system development
tools are an IBM-XT, AT, or compatible

computer running MS-DOS version 3.1 or
later. The system must be equipped with
640 Kbytes of RAM and a hard disk.

Hardware

The SAM448 system programming
hardware consists of the following:

The MagicPro Programmer is the common
hardware platform for programming all WSI
programmable products. It consists of the
IBM-PC® plug-in Programmer Board and
the Remote Socket Adaptor Unit.

• MagicPro - Memory and System
Programmer
• WS6008 - 28 Pin Dip Socket Adaptor for
MagicPro Remote Socket Adaptor Unit

fJ

• WS6009 - 28 Pin LCC Socket Adaptor
for MagicPro Remote Socket Adaptor
Unit

Software

The SAM448 System Development
Software consists of the following:
• WISPER Software - WSI Integrated
Software and Programming Environment
• SAMPLUS Software - Interface
Manager for SAM Tools
• ASMILE Software Language

The system design is entered into ASMILE
(WSI State Machine Input Language)
source program files using an editor
chosen by the user. ASMILE supports
Microcode entry and State Machine entry.
The ASMILE produces object code format
which can be loaded to SAMSIM and
SAMPRO

System Entry

• SAMSIM Software - Functional Simulator
• SAMPRO Software - Device
Programming Software
The complete SAM448 development cycle
is illustrated in Figure 1.
WISPER and SAM PLUS software provide
a menu-driven user interface enabling other
tools to be easily invoked by the user.

The SAMSIM functional simulator enables
the user to test and debug programs by
examining the state of SAM448 internal
states before and during a complete
functional simulation of the device.
SAMPRO software programs SAM448
devices by using the MagicPro hardware
and the socket adaptor.
The programmed SAM448 is then ready to
be used.

WAFERSCALE INTEGRATION, INC.
----

2·133

---------- - - - - -

SAM448

Figure 1. SAM
DevelDpment
Cycle

Documentation

WSI·Support

SAM448 Software User's Manual.

WSI provides a complete set of quality
support services (WSI-Support) to
registered system development tools
owners. These services include the
following:

• 12-Month Software update service - Upto-date software maintenance, access to
latest software and product information.
• Hotline to WSI Application Experts - Direct
system development assistance
• 24-Hour Electronic Bulletin Board Service
- Design assistance via our auto-answer
dial-up modem service.

Training
WDrkshops

2·134

WSI provides "Do-It-Yourself Systems"
Technical Training Workshops that provide
an in-depth tutorial on SAM448 and SAM
system development tools.

WAFERSCALE INTEGRATION, INC.

Workshop participants will learn how to
build their own high-performance state
machine using the SAM448. SAM
Development Training Workshops are
held at the WSI Fremont facility.

SAM448

Ordering
Information System
Development
Tools

SAM448·Gold package

consists of the

following:

• WS6008 28 Pin Dip Socket Adaptor
• WS6009 28 Pin CLLCC/CLDCC/PLDCC
Socket Adaptor

• Software
- WISPER Software
- SAMPLUS Software
- ASMILE Software
- SAMSIM Software
- SAM PRO Software
- User's Manual
- WSI-Support

WSI·Support
• Includes 12-month Software Update
Service to registered system owners

• Hardware
- WS6000 MagicPro Programmer

SAM448·Silver package

consists of the

following:

• Includes Hotline to WSI Application
experts
• Includes 24-hour access to WSl's
Electronic Bulletin Board Service

SAM Training Workshops
• Includes SAM448 Training Workshops at
the WSI Fremont facility. For details and
scheduling, contact PSD Marketing at
(415) 656-5400.

• Software
- WISPER Software
- SAMPLUS Software
- ASMILE Software
- SAMSIM Software
- SAMPRO Software
- User's Manual
- WSI-Support

WS6000 MagicPro'"

Adaptors

Memory and PSD

Programmer
• Includes IBM PC plug-in adaptor card
and Remote Socket Adaptor

Ordering
Information

Part Number

Speed
(MHz)

SAM448-20J
SAM448-20L
SAM448-20Ll
SAM448-20LM
SAM448-20LMB
SAM448-20S
SAM448-20T
SAM448-2OTI
SAM448-20TM
SAM448-20TMB
SAM448-25J
SAM44825L
SAM448-25S
SAM448-25T
SAM448-30J
SAM448-30L
SAM448-30S
SAM448-30T

20
20
20
20
20
20
20
20
20
20
25
25
25
25
30
30
30
30

Operating
WSI
Package Temperature
Manufacturing
Drawing
Range
Procedure

Package
Type
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

PLDCC
CLDCC
CLDCC
CLDCC
CLDCC
Plastic Dip, 0.3"
CERDIp, 0.3"
CERDIP, 0.3"
CERDIP, 0.3"
CERDIP, 0.3"
PLDCC
CLDCC
Plastic Dip, 0.3"
CERDIp, 0.3"
PLDCC
CLDCC
Plastic Dip, 0.3"
CERDIp, 0.3"

J3
L2
L2
L2
L2
S2
T2
T2

T2
T2
J3
L2
S2

T2
J3
L2
S2

T2

Comm'l
Comm'l
Industrial
Military
Military
Comm'l
Comm'l
Industrial
Military
Military
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l

Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard

WAFERSCALE INTEGRATION, INC.

2·135

2·136

WAFERSCALE INTEGRATION, INC.

WAFERSCALE INTEGRATION, INC.

PSD Development Systems

3

Section Index
PSD Development
Systems

MAP168 -

PSD Development Systems ....................................... 3-1

SAM448 -

PSD Development Systems ....................................... 3-5

PAC1000 -

PSD Development Systems ....................................... 3-9

WS6000 MagicPro™ Programmer and Package Adaptors ........................ 3-13

For additional information,
call 800·TEAM·WSI (800·832·6974).
In California, call 800·562·6363.

WAFERSCALE INTEGRATION, INC.

Programmable System™Device
MAP168
WAFERSCALE INTEGRATION, INC.

PSD Development System
Description

MAP168-GOLD/MAP168-SILVER is a
complete set of IBM-PC-based development
tools. They provide the integrated easy-touse environment to support the MAP168
program development and device
programming.

The tools run on an IBM-PC XT, AT or
compatible computer running MS-DOS
version 3.1 or later.

MAPLE

MAPLE is the MAP168 Locator Editor. It
has the following features:

Q Generating the PAD programming data

Q Simple Menu Driven Commands for
selecting different configurations of the
MAP168:
- Byte wide or word wide operation.
- Address or Chip Select Input (CSI)
Mode.
- PAD security option.

MAPPRO

MAPPRO is the interface software that
enables the user to program a MAP168
device on the WS6000 MagicPro™
programmer. The MAPPRO enables the
user to load the program into the
programmer and to execute the following
operations:
Q Help
Q Upload RAM from MAP

that maps the 8 segments of EPROM,
two segments of SRAM and eight Chip
Selects Outputs to the user's address
space.

Q Combining all the different files to be
programmed into the EPROM
segments.

1.1

Q Write RAM to FILE

Q Display MAP data
Q Blank test MAP
Q Verify MAP
Q Program MAP

Q Configuration
Q Quit

Q Load RAM from disk

WS6000
MagicPIO™
Programmer

The WS6000 MagicPro Programmer is an
engineering development tool designed to
program all WSI programmable products
(EPROMs, RPROMs, PAC 1000, MAP168,
PSD301 and SAM448). It is used within
the IBM-PC and compatible environment.
The MagicPro consists of a short plug-in

board and a Remote Socket Adaptor
(RSA). It occupies a short expansion slot
in the PC. The RSA has two ZIF-DIP
sockets that will support WSI's 24, 28, 32
and 40 pin standard 600 mil or slim 300
mil DIP packages without adaptors. Other
packages are supported using adaptors.

WS6003
Socket Adaptor

The WS6003 is a socket adaptor that
mounts on the MagicPro RSA and adapts

the MAP168 in 44-pin CLDCC, PLDCC or
CLLCC packages to the programmer.

WAFERSCALE INTEGRATION, INC.

3·1

MAP168

WS6011
Socket Adaptor

The WS6011 is a socket adaptor that
mounts on the MagicPro RSA and adapts

the MAP168 in a 44-pin PGA package to
the programmer.

WSI·Support

WSI provides on-going support for users of
MAP168-GOLD/MAP168-SILVER. For the
first year, software and programmer updates
are included at no charge. After that, the

user may purchase the WSI-Support
agreement to continue to receive the latest
software releases.

Ordering
Information

3-2

Product

Description

MAP168-SILVER

Contains MAP168 Software (MAPLE-MAP and MAPPRO),
Software User's Manual, WSI-Support.

MAP168-GOLD

Contains MAP168-SILVER, WS6000 MagicPro
Programmer, WSI-Support.

WSI-Support

12-Month Software Update Service, Access to WSI's
24-Hour Electronic Bulletin Board, and Hotline to WSI
System Application Experts.

WAFERSCALE INTEGRATION, INC.

MAP'68

MAP168·

GOLD

II

Contents

Q MAPLE-MAP Locator editor.

Q Software user's manual.

Q MAPPRO

Q WSI-SUPPORT agreement.

Interface software to MAP168 device
programmer (MagicPro™).

Q WS6000 MagicPro Programmer.

WAFERSCALE INTEGRATION, INC.

--------------------

--~~-

3-3

----------------

MAP168

MAP16a·

SILVER

Contents

r:J MAPLE-MAP Locator editor.
r:J MAP PRO
Interface software to MAP168 device
programmer (MagicPro™).

3-4

WAFERSCALE INTEGRATION, INC.

r:J Software user's manual.
r:J WSI-SUPPORT agreement.

~~~-

---

--~~~-

-~~~~-

Programmable System™Device
WAFERSCALE INTEGRATION, INC.

SAM448
PSD Development System

Description

SAM448-GOLD/SAM448-SILVER is a
complete set of IBM-PC-based development
tools. They provide the integrated easy-touse environment to support the SAM448
program development and device
programming.

ASM/LE

ASMILE is the SAM448 system entry
language. It has the following features:

a

SAMS/M

The tools run on an IBM-PC XT, AT or
compatible computer running MS-DOS
version 3.1 or later.

a
a

Assembly Design Entry Language.

a

Displays input and output waveforms
interactively providing such features as
multiple zoom levels, split screens and
differential time display.

a

Line disassembler converts the actual
code back into the original Assembly
source code.

a

On-line HELP available at any level.

User Definable Macros

State Machine Design Entry.

SAMSIM is an interactive functional
simulator with Virtual Logic Analyzer
Interface:

a

Clock driven functional simulator.

a

Provides trace capabilities on internal
states (Registers, Flags, Pins and
more).

SDP

The SAM Design Processor (SOP) takes
an assembly file and creates an optimized
JEDEC file for the SAM448. The SOP first
expands macros that have been defined
by the user. It then parses the design,

listing any syntax or correction errors in an
Error Log file. Next it minimizes the Boolean
expressions that define the transition
conditions. Finally, it fits the design into
the SAM448, generating a JEDEC file.

SAMPRO

SAMPRO is the interface software that
enables the user to program a SAM448
device on the WS6000 MagicPro™
programmer. The SAM PRO enables the
user to load the program into the
programmer and to execute the following
operations:

a

Load RAM from disk

a
a

Write RAM to FILE

a
a
a

Blank test SAM

SAMPLUS

a

Help

a

Upload RAM from SAM

a
a

SAM PLUS is the interface manager to the
SAM448 software tools. SAMPLUS enables
the user to access ASMILE, SAMSIM, SOp,
SAM PRO, DOS and an editor with a menu
driven interface. File specification can be

Display SAM data
Verify SAM
Program SAM
Configuration
Quit

done without extension enabling the user
to use the same name throughout the
design. A HELP window is available online giving information on all the needed
steps at each level.

WAFERSCALE INTEGRATION, INC.

3-5

EI

SAM448

WS6000
MagicPro™
Programmer

MagicPro is an engineering development
tool designed to program all WSI
programmable products (EPROMs,
RPROMs, PAC 1000, MAP168, PSD301 and
SAM448). It is used within the IBM-PC and
compatible environment. The MagicPro
consists of a short plug-in board and a

Remote Socket Adaptor (RSA). It occupies
a short expansion slot in the PC. The RSA
has two ZIF-DIP sockets that will support
WSI's 24, 28, 32 and 40 pin standard 600
mil or slim 300 mil DIP packages without
adaptors. Other packages are supported
using adaptors.

WS600B
Socket Adaptor

The WS6008 is a socket adaptor that
mounts on the MagicPro RSA and adapts

the SAM448 in a 28 pin DIP package to
the programmer.

WS6009
Socket Adaptor

The WS6009 is a socket adaptor that
mounts on the MagicPro RSA and adapts

the SAM448 in a 28-pin PLDCC/CLDCCI
CLLCC package to the programmer.

WSI·Support

WSI provides on-going support for users of
SAM448-GOLD/SAM448-SILVER. For the
first year, software and programmer updates
are included at no charge. After that, the

user may purchase the WSI-Support
agreement to continue to receive the latest
software releases.

Ordering
Information

3·6

Product

Description

SAM448-SILVER

Contains SAM448 Software (ASMILE, SAMSIM, SDp,
SAM PRO and SAM PLUS), Software User's Manual,
WSI-Support.

SAM448-GOLD

Contains SAM448-SILVER, WS6000 MagicPro
Programmer, WSI-Support.

WSI-Support

12-Month Software Update Service, Access to WSI's
24-Hour Electronic Bulletin Board, and Hotline to WSI
System Application Experts.

WAFERSCALE INTEGRATION, INC.

SAM448

SAM448·
GOLD

II
=

Contents

Q ASMILE

SAM design entry language.
Q SAMSIM

Interactive Functional simulator with
Virtual Logic Analyzer user interface.
Q SDP

SAM Design Processor Compiles the
User's program to fit into the SAM448
Device.

Q SAMPRO

Interface software to SAM448 device
programmer (MagicPro™).
Q SAMPLUS

Interface manager to SAM448
development tools.

Q Software user's manual.
Q WSI-SUPPORT agreement.
Q WS6000 MagicPro Programmer.

WAFERSCALE INTEGRATION, INC.

3·7

SAM448

SAM448·

SILVER

Contents

r:J ASMILE
SAM design entry language.

r:J SAMSIM
Interactive Functional simulator with
Virtual Logic Analyzer user interface.

r:J SOP
SAM Design Processor Compiles the
User's program to fit into the SAM448
Device.

3·8

WAFERSCALE INTEGRATION, INC.

r:J SAMPRO
Interface software to SAM448 device
programmer (MagicPro).

r:J SAMPLUS
Interface manager to SAM448
development tools

r:J Software user's manual.
r:J WSI-SUPPORT agreement.

='====
~~
................
_...... -................

Programmable System Device
1M

-----.-....

r~~~_

~

-.-.~

WAFERSCALE INTEGRATION, INC.

PACtOOO
PSD Development System

Description

PAC1000-GOLD/PAC1000-SILVER is a
complete set of IBM-PC-based development
tools. They provide the integrated easy-touse environment to support the PAC1000
program development and device
programming.

The tools run on an IBM-PC XT, AT or
compatible computer running MS-DOS
version 3.1 or later.

PACSEL

PACSEL is the PAC1000 system entry
language. It has the following features:

r:J Enables mixing of three source
language types in one instruction:
- High Level Language
- Assembler
- Microcode

r:J Enables specification of up to three
parallel operations:
- Program control operation
- CPU operation
- Out Control operation

r:J Specific instructions support unique

General Syntax:
Label: Program Control, CPU, Out Control;

PACSIM

PACSIM is a functional simulator and
software debugger. It has the following
features:

internal state of the PAC1000.

CJ Supports batch mode simulation.
CJ Provides waveform analysis.
CJ On-line HELP available at any level.

states (Registers, Flags, Pins and
more).

PAC PRO is the interface software that
enables the user to program a PAC1000
microcontroller on the WS6000 MagicPro™
programmer. The PACPRO enables the
user to load the program into the
programmer and to execute the following
operations:

CJ Help
CJ Upload RAM from PAC
CJ Load RAM from disk

IMPACT

IMPACT is the interface manager to the
PAC1000 tools. IMPACT enables the user
to access PACSEL, PACSIM, PACPRO,
DOS and an editor with a menu driven
interface. File specification can be done

r:J Links unlimited amounts of modules.

CJ Provides breakpoint capabilities on any

r:J Clock driven functional simulator.
r:J Provides trace capabilities on internal

PACPRO

PAC1000 architecture features available
in all three source language types.

CJ
CJ
CJ
CJ
CJ
CJ
CJ

Write RAM to FILE
Display PAC data
Blank test PAC
Verify PAC
Program PAC
Configuration
Quit

without extension enabling the user to use
the same name throughout the design. A
HELP window is available on-line giving
information on all the needed steps at
each level.

WAFERSCALE INTEGRATION, INC.

3-9

II

PACtOOO

WS6000
MagicPro™
Programmer

MagicPro is an engineering development
tool designed to program all WSI
programmable products (EPROMs,
RPROMs, PAC1000, MAP168, PSD301 and
SAM448). It is used within the IBM-PC and
compatible environment. The MagicPro
consists of a short plug-in board and a

Remote Socket Adaptor (RSA). It occupies
a short expansion slot in the PC. The RSA
has two ZIF-DIP sockets that will support
WSI's 24, 28, 32 and 40 pin standard
600 mil or slim 300 mil DIP packages
without adaptors. Other packages are
supported using adaptors.

WS6010
Socket Adaptor

The WS6010 is a socket adaptor that
mounts on the MagicPro RSA and adapts

the PAC1000 in an 88-pin CPGA package
to the programmer.

WS6013
Socket Adaptor

The WS6013 is a socket adaptor that
mounts on the MagicPro RSA and adapts

the PAC1000 in a 100-pin QFP package to
the programmer.

WSI·Support

WSI provides on-going support for users of
PAC1000-GOLD/PAC1000-SILVER. For the
first year, software and programmer updates
are included at no charge. After that, the

user may purchase the WSI-Support
agreement to continue to receive the latest
software releases.

Ordering
Information

3·10

Product

Description

PAC1000-SILVER

Contains PAC1000 Software (PACSEL, PACSIM,
PACPRO, and IMPACT), Software User's Manual,
WSI-Support.

PAC1000-GOLD

Contains PAC1000-SILVER, WS6000 MagicPro
Programmer, WSI-Support.

WSI-Support

12-Month Software Update Service, Access to WSI's
24-Hour Electronic Bulletin Board, and Hotline to WSI
System Application Experts.

WAFERSCALE INTEGRATION, INC.

PAC1000

PAC1ooo·

GOLD

II
"

Contents

CJ PACSEL
System design entry language and
program linker.

CJ PACSIM
Functional simulator and software
debugger.

CJ PACPRO

CJ IMPACT
Interface manager for PAC1000
microcontrolier development tools.

CJ Software user's manual.
CJ WSI-SUPPORT agreement.
CJ WS6000 MagicPro Programmer.

Interface software to PAC1000 device
programmer (MagicPro™).

WAFERSCALE INTEGRATION, INC.

3-11

PAC1000

PAC1DDD·

SILVER

Contents

r:J PACSEL
System design entry language and
program linker.

r:J PACSIM
Functional simulator and software
debugger.

r:J PACPRO
Interface software to PAC1000 device
programmer (MagicPro™).

3·12

WAFERSCALE INTEGRATION, INC.

r:J IMPACT
Interface manager for PAC1000
microcontrolier development tools.

r:J Software user's manual.
r:J WSI-SUPPORT agreement.

-------- - - -

- - - -

......----------- - - - - - - - - - - - - - - - - - - - - - - - - - -WS6000
----

WEE
-~-

=:~

r . . . . . . . . . ~~

~ ~

WAFERSCALE INTEGRATION, INC.

MAGICPRO™ MEMORY AND PSD

PROGRAMMER
KEY FEATURES
• Programs All WSI CMOS Memory
and PSD Products and All Future
Programmable Products

• Programs LCC, PGA and QFP Packaged
Product by Using Adaptors

• Programs 24, 28, 32 and 40 Pin
Standard 600 Mil or Slim 300 Mil Dip
Packages Without Adaptors

• Compatible with IBM PC/XT/AT
Family of Computers (and True
Plug-Compatible)

• Easy-to-Use Menu-Driven Software

GENERAL DESCRIPTION
MAGICPRO™ is an engineering development tool designed to program existing WSI EPROMs, RPROMs,

Programmable System Devices, and future WSI programmable products. It is used within the IBM-PC® and compatible
computers. The MAGICPRO™ is meant to bridge the gap between the introduction of a new WSI programmable
product and the availability of programming support from programmer manufacturers (e.g., Data I/O, etc.). The
MAGICPRO™ programmer and accompanying software enable quick programming of newly released WSI
programmable products, thus accelerating the system design process.
The MAGICPRO™ plug-in board is integrated easily into the IBM-PC®. It occupies a short expansion slot and its
software requires only 256K bytes of computer memory. The two external ZIF-Dip sockets in the Remote Socket Adaptor
(RSA) support 24, 28, 32 and 40 pin standard 600 mil or slim 300 mil Dip packages without adaptors. LCC, PGA
and QFP packages are supported using adaptors.

WAFERSCALE INTEGRATION, INC.

3-13

3

WS6000

Many features of the MAGICPRO™ Programmer show its capabilities in supporting WSI's future products. Some of
these are:
-

24 to 40 pin JEDEC Dip pinouts
1 Meg. address space (20 address lines)
16 data I/O lines

The MAGICPRO™ menu driven software makes using different features of the MAGICPRO™ an easy task. Software
updates are done via floppy disk which eliminates the need for adding a new memory device for system upgrading.
Please call 800:rEAM-WSI for information regarding programming WSI products not listed herein. The MAGICPRO™
reads Intel Hex format for use with assemblers and compilers.

MAGICPRO™

-

COMMANDS

Help
Upload RAM from device
Load RAM from disk
Write RAM to disk
Display RAM data
Edit RAM
Move/copy RAM
Fill RAM
Blank test device
Verify device
Program device
Select device
Configuration
Quit MagicPro™

WSI PRODUCTS
WS57C191/191B/291/291B
WS57C43/43B
WS57C49/49B
WS57C51/51B
WS27C64F/L
WS57C64F
WS57C65
WS57C66
WS27C128F/L
WS57C128F
WS27C256F/L
WS57C256F
WS57C257F
WS27C512F/L
WS27C010L
MAP168
PAC1000
SAM448
PSD301

2K x 8
4K x 8
8K x 8
16K x 8
8K x 8
8K x 8
4K x 16
4K x 16
(Mux 110, 28
16K x 8
16K x 8
32K x 8
32K x 8
16K x 16
64K x 8
128K x 8

RPROM
RPROM
RPROM
RPROM
EPROM
EPROM
EPROM
EPROM
Pin DIP)
EPROM
EPROM
EPROM
EPROM
EPROM
EPROM
EPROM

TECHNICAL INFORMATION
• Size: IBM-PC®short length card
• Port Address Location: 100H to 1FFH-default 140H (If a conflict exists with this address space, the address location
can be changed in software and with the switches on the plug-in board.)
• System Memory Requirements: 256K bytes of RAM
• Power: +5 Volts, 0.03 Amp.; +12 Volts, 0.04 Amp.
• Remote Socket Adaptor (RSA): The RSA contains two ZIF-Dip sockets that are used to program and read WSI
programmable products. The 32 pin ZIF-Dip socket supports 24, 28 and 32 pin standard 600 mil or slim 300 mil
Dip packaged product. The 40 pin ZIF-Dip socket supports all 40 pin Dip packages. Adaptor sockets are available
for LeC, PGA and QFP packages.

3-14

WAFERSCALE INTEGRATION, INC.

WS6000

ORDERING INFORMATION
The WS6000 MAGICPRO™ System contains:

MAGICPRO™ Adaptors Include:

• MAGICPRO™ IBM-PC®plug-in

• WS6001 28 Pin CLLCC Package adaptor for memory.

programmer board
• MAGICPRo™ Remote Socket Adaptor

and cable
• MAGICPRO™ Operating System Floppy Disk

and Operating Manual

• WS6003 44 Pin PLDCC/CLDCC/CLLCC package adaptor
for MAP168.
• WS6008 28 Pin 0.3" wide DIP adaptor for SAM448.
• WS6009 28 Pin PLDCC/CLDCC/CLLCC package adaptor
for SAM448.
• WS6010 88 Pin PGA package adaptor for PAC1000.
• WS6011 44 Pin PGA package adaptor for MAP168.
• WS6012 32 Pin CLDCC package adaptor for memory.
• WS6013 100 Pin QFP package adaptor for PAC1000.
• WS6014 44 Pin CLDCC/PLDCC package adaptor for
MAP168 and PSD301.
• WS601544 Pin PGA package adaptor for MAP168 and
PSD301.

II

IBM-PC'" is a registered trademark of IBM Corporation.

MAGICPRO'" is a trademark of WaferScale Integration, Inc.

WAFERSCALE INTEGRATION, INC.
---~--~---~--

~

-- ._- - - -

3-15

3·16

WAFERSCALE INTEGRATION, INC.

WAFERSCALE INTEGRATION, INC.

'.11 Applications

4

Section Index
PSD Applications

Application Note 002

Introduction to the MAP168 User-Configurable
Mappable Memory Subsystem .......................... 4-1

Application Note 010

PAC1000 Introduction ................................ 4-13

Application Note 005

PAC1000 as a High-Speed Four-Channel
DMA Controller ..................................... 4-39

Application Brief 006

PAC1000 as a 16 Bi-Directional Serial
Channel Controller .................................. 4-71

Application Note 008

PAC1000 User-Conflgurable Microcontroller with a
BUilt-ln-Self-Test Capability ........................... .4-75

Application Note 009

In-Circuit Debugging for the PAC1000
User-Configurable Microcontroller ...................... 4-83

Application Brief 007

Hardware Interfacing the PAC1000 as a
Micro Channel Bus Controller ......................... 4-99

Application Note 003

High-End SAM Applications Using
Microassembler Design Entry ........................ .4-105

Application Note 004

SAM Applications Using State Machine Design Entry ..... 4-127

For additional information,
call800·TEAM·WSI (800·832·6974).
In California, call 800·562·6363.

WAFERSCALE INTEGRATION, INC.

Programmable System™Device
Application Note 002

WAFERSCALE INTEGRATION, INC.

Introduction to the MAP168
User-Configurable Mappable
Memory Subsystem
Memory Structure

Memory configurations in microprocessor and
microcontroller systems have similar structure, irrespective of the application. (see
Figure 1.) They share basic components,
such as an EPROM (for program storage),
and an SRAM (for data storage). In addition,
a decoder circuit is required to select blocks
of memory from the address inputs applied by
the processor. A common implementation of
address decoding originally used MSI building

blocks, such as 74xx138 devices. Memoryconfiguration changes and expansions In a
fixed-logic solution required jumpers on the
printed circuit board. More recently, decoders
based on PAL ® devices have provided a more
compact and flexible solution. PAL devices
allow configuration changes to be implemented by insertion of a programmed device
and avoid jumper changes.

Figure 1. Memory
Subsystem Using
Standard Devices

Address Bus

M,cro.

RD 1----..-

processor WR

1--_ _..-

Decode
Logic and
Jumpers

eso
To Other Devices

eso

Data Bus

Both solutions involve compromises that
affect system performance, board space,
power and cost. Since the decoder is in the
memory access path, the total memory
access time is the sum of the decoder delay
and the access time of the memory itself. For
example, a 40ns total access time can be
achieved with a 12ns decoder and a 25ns
memory. This allows 3ns for on-board interconnect delay. Memory products in the 25ns

1739 01

range are expensive and therefore such a
performance entails additional cost. To be
able to integrate the programmable address
decoder with system memory, EPROM and
static RAM would offer a more flexible
approach. The resulting device would provide
board-space economy, higher performance
and less overall power consumption without
the cost of a multichip solution.

WAFERSCALE INTEGRATION, INC.

4·1

MAP168 - Application Note 002

Memory
Structure
(Con't)

The WSI-MAP family of user-configurable
mappable memory subsystem products has
been developed to significantly enhance
system performance by integrating high
density EPROM for program store, high
density SRAM for data store and high performance logic in the form of a Programmable
Address Decoder (PAD) on one chip. (See
Figure 2.) The first of these devices, with
128K bits of EPROM and 32K bits of SRAM,
is the MAP168 device. These devices are

Figure 2. Memory
Subsystem Using
theMAI'168
Device

Address Bus

ideally suited for a number of common design
applications:

"

D

High-speed Digital Signal Processor
applications (modems, analog data
filtering or analysis)

D

Expanding memory systems for
microprocessors and microcontrollers

D

Space- and power-sensitive applications
(plug-in cards, avionics, portable
systems)

ADDRESS

AD

OE

WR

WE
A

Data Bus

"

1/0

Microprocessor

Features of the
MAI'168 Device

4·2

The MAP168 device offers significant design
advantages through integration, performance
and user-configurability. It integrates both
volatile and non-volatile memory on the same
chip, along with a flexible decoding system.
The memory is structured as a series of
blocks to achieve a highly configurable circuit
for general purp.ose applications. The device
operates in one of several modes, one of
which is for normal operation and the rest are
for device configuration. At the heart of all
MAP168 device is a Programmable Address
Decoder (PAD), which is programmed during
the PAD programming mode through the
circuit's address and 1/0 pins. The PAD offers
the following features:
D

Flexible EPROM/SRAM location within
the address space

D

Memory array power-down when not
being accessed

D

Security protection of memory
configuration data to inhibit copying

WAFERSCALE INTEGRATION, INC.

MAPI68

D

--

CSO
To Other Devices
CSO

1739 02

Integrated external device mapping
through Chip Select Outputs

Memory Architecture And Technology
The memory in the MAP168 device consists
of non-volatile EPROM and volatile SRAM.
(See Figure 3.) The EPROM is subdivided
into 8 blocks and the SRAM into 2 blocks.
The blocks may be configured in either a
2Kx8 or a 1Kx16 format, allowing optimal
interaction with both 8- and 16-bit systems.
These memory blocks can be considered as
separate memories with dedicated internal
chip selects. The PAD selects the appropriate
block, decoded from the incoming address
provided at the device inputs. This architecture enables the product to be configured and
compatible with virtually any system address
map. Complicated address maps of microcontroller systems can be fully realized by
programming blocks of EPROM and SRAM in
the memory-mapping scheme of the system.

MAP168 - Application Note 002

Features of the
MAP16B Device
(Con't)

In addition to having fine control of memory
allocation, software updates which require
changes in the address map boundaries can
be easily accomplished by simply reprogramming the PAD at the same time as the
EPROM code. This means only one part
need be sent to the end-product customer to
accommodate field software changes. This
becomes a user-transparent method that
requires no change of PC board jumpers.

fast decode and reconfiguration of the same
device. The MAP168 device contains a 128Kbit UV erasable EPROM which can be
organized as 16Kx8 (byte-wide) or as 8Kx16
(word-wide) .

The EPROM is based on WSI's patented
split-gate EPROM technology for high density
and very high speed. It is also used in the
reconfigurable PAD section, permitting both

Figure 3.
Internal
Architecture

The SRAM is based on the industry standard
full CMOS 6-transistor cell. The advantages
of this cell are high speed, very low stand-by
power, high noise immunity and good data
retention when disturbed by alpha particles.
In the MAP168 device, the SRAM contains
32K bits which can be configured as 4Kx8 in
the byte mode or 2Kx16 in the word-wide
mode.

MAP168
DECODED EPROM

r--

ADDRESS~

~
~

Ao-A'2
EPROM
8Kx 8

PGMH

,---.

,.

PGM
EOEH
OE

Ao-A'9

OUT0-7

PGML

IN0-7

Ao-A'2
EPROM
8Kx8
PGM
OE

OUT0-7

t - - !-

EOEL

t--

IN0-7

•

t--

DECODED SRAM
ADDRES~

v

PAD

~
~

Ao-A'2
SRAM
2Kx8

WEH

,----.

,.

WE
ROEH
OE

BHE -

ROEL

1---0

OE -

f---e

SI/A 20 -

1---0

CON

I--

OEL

IN 0-7

•

WEL

f---e

E/Vpp _

FCSO -

OUTO_ 7

I---

'r-"

I---

r--

Ao-A'2
SRAM
2Kx8
WE
OE

OUT0-7

.

IN0-7

~

I--OEH

CS0-7

p.....

~~

>
21
MUX

21
MUX

r'

I--

•

'---

-

~

~'-

V1

An 1

n

r---

~

;-1'
-'r-

V1

~

1/08-15 OR CS00-7

WAFERSCALE INTEGRATION, INC.

1739 03

MAP16B - Application Note 002

Features of the
MAP16B Device
(Con't)

PAD Logic Implementation
The PAD uses the same non-volatile EPROM
cells as the EPROM array. (See Figure 4.) It
can be erased and configured at the same
time as the EPROM. After UV erase or with
new parts, the EPROM cells in the MAP168
device normally connect between the address
inputs and the select outputs. The EPROM
cells are disconnected by selective programming.
The PAD performs as an address
comparator. When the address configuration
previously programmed into the PAD is
detected, the internal chip-select signal to the
memory block selected by that address is
enabled. If no block is selected by the
address, neither the EPROM nor the SRAM
arrays are enabled and other devices may
drive the data bus. Independent of internal
block selection, external chip-select decoding
(known as CSOs) are programmable in the
same block resolution as the internal
memory.
Actual implementation of the PAD is similar to
that of a PAL device. (See Figure 5.) In the
erased state, all the block decode addresses
are connected to the AND plane. There is
only one output per AND gate and there is no
OR plane. Each AND gate output either
selects a block of internal memory or a
number of blocks of external memory for the
external CSOs. Only addresses A11-A2o are

Figure 4.
PAD Programming
Examples

used as block decode address. Lower-order
address lines are used only for addressing
within the internal memory arrays.
EPROM select outputs ES o-ES 7 (ES outputs)
select 1 of the 8 available EPROM blocks.
SRAM select outputs RS o-RS 1 (RS outputs)
select one of the 2 available SRAM blocks.
Because only one EPROM or SRAM block
can be active at a particular time, only one
line from either ES o-ES 7 or RS o-RS1is
allowed to be active at one time. The CSOs
are independent of the ES and RS outputs
and therefore anyone address can be
programmed to select one or more of the
CSOs, even simultaneous to the selection of
one of the ES or RS outputs. This is particularly useful for 1/0 control or address decode
for wait state generation.
Programming the decoder is similar to
programming a PAL device that has only one
product term (AND gate) per output. To
enable an output S1 as shown in Figure 4,
fuse locations A11 and A12 are left intact while
A11 and A12 are programmed. Conversely, if
A11 and A12 are programmed while their complements are left intact, then the select S
function is active when A11 = A12 = O. If all
fuse locations are programmed on a product
term, the inputs are pulled HIGH and no
select output can take place. If all fuse
locations are left intact, the S output is
permanently LOW, always selected.

S1=

A11~2

S2= An:O:;2
S3 = HARD DESELECTED = NEVER SELECTED

S5 = DON"T CARE = ALWAYS SELECTED

• = CONNECTED

X = DISCONNECTED
1739 04

WAFERSCALE INTEGRATION, INC.

MAP168 - Application Note 002

Features of the
MAP168 Device
(Con't)

Device Array Power-Down
Power dissipation on the chip is minimized
through logic in the PAD. It selectively
powers up the EPROM or SRAM arrays only
when they are being accessed. If the
EPROM is selected through the decoder, it
will draw power while the SRAM stays
powered down and vice versa. When neither
the EPROM or the SRAM is selected, both
are powered down. Note that data integrity in
a "powered down" SRAM is maintained. A
Chip Select Input (CSI) to the device is

provided for a very low-power quiescent
mode. With CSI=1, the EPROM and SRAM
are powered down but the PAD is powered
up, independent of the incoming address
signals. The CSI input pin can be connected
to a system power-down signal. If such a
signal is unavailable, addressing a location in
memory that does not select either the
EPROM or the SRAM also reduces power
drain. In this case, only the PAD is powered
up and draws a small fraction of the active
power.

Figure 5_
PAD Array
Architecture

ES O
ESt
ES 2
ES 3
ES,
ES 5
ES 6
ES 7
RS o
RS t
CSO o
CSO t

cso 2
cso 3
cso,
cso 5
cso s
cso 7
FCSO
CSI
fA 20

At9 At9 AtB AtB At? At? A tS

At6 At5 At5 At, At, At3 At3 At2 At2 Att

Att
1739 05

CSI fA20

WAFERSCALE INTEGRATION, INC.

4-5

II

MAP168 - Application Note 002

Features Of The
MAP168 Device
(Con't)

The CSIIA20 input is actually a dual function
pin. It can be an address (MSB) input, or it
can be programmed to be a chip select input
as well. As a chip select input, it will enable
the EPROM and SRAM memory when active
(LOW). If the address option A20 is chosen the
chip is always enabled.

Address Map Security
Upon entering the PAD programming mode,
the contents of the PAD are fully accessible
through the 1/0 pins. After programming is
completed, it is possible to render the PADs
programmed configuration invisible by programming the security (SEC) bit. This disables external access to the PAD and ensures that the PAD configuration can not be
copied. To further aid in securing data in the
MAP product, it is suggested that memory
blocks that are addressed in a linear block
placement be programmed in the PAD as
chip selects from product terms that are
randomly placed.

Chip Select Outputs
The MAP168 device can be user-configured
for 8-bit or 16-bit systems. In the former case,
eight unused data lines (CS00-7 ) are available
as chip select outputs, driven by the address
decoder section of the PAD. This provides the

System
Applications

The MAP168 device is designed to reduce
memory access time and board area utilization in high performance digital signal processor, microcontroller and microprocessor
systems. These systems typically have the
following requirements:

o
o
o

64K to 1 Meg address space

o

Decoding for 1/0 and memory

o

Printed circuit board area limitations

o

Multiple types of memory, including
EPROMs and SRAMs for program and
data store.

16-bit data path
Fast memory access time (1 OOns to
40ns)

The DSP System Architecture shown in
Figure 6 illustrates a typical system based

4·6

WAFERSCALE INTEGRATION, INC.

ability to integrate external devices into the
address map with no hardware overhead.
Unlike the internal memory blocks, a CSO
can be active for more than one address
combination or block. Also, groups of blocks
may overlap both each other and the internal
memory. By deselecting both the true and the
complement it is possible to make an address
line "don't care".
An external memory can therefore be selected with only one CSO. It is possible to
enable another external 128K byte memory
by programming a single CSO to be active for
that entire address range.
A CSO can be programmed to function as a
configuration bit which is always deselected
(e.g., CSO o=1) or always selected (e.g.,
CSOo=O) by programming the addresses with
"hard deselect" or with the "don't care"
patterns, respectively. This is similar in
function to a PC-board wire jumper. If unused
CSOs are programmed with all addresses
"don't care", then switching is eliminated and
power consumption reduced for those lines.
Since the PAD is always powered up when
the device is selected (CSI=O), CSOs are
always active and their state is a direct
function of the PAD configuration and current
address line inputs.
upon a 40MHz TMS320C25 digital Signal
processor. Such a system allows only 40ns
for memory access time. The access time
must be broken down into decoding time and
memory-access time. The fastest decoders
available today require approximately 1Ons to
complete their decode function. Due to this
decoding time, memory access time for both
the EPROM and SRAM must be 30ns or less.
The WSI-MAP family of products performs
decoding on-chip with no speed penalty. As a
result, the performance of a 40ns MAP168
device in the above example is equivalent to
a 1Ons decoder and a 30ns EPROM and
SRAM memory. In addition, the package
equivalent of two fast EPROMs, two fast
SRAMs and at least one decoder are combined into one MAP168 chip resulting in at
least a 5-to-1 component count reduction.

ftfAP168 - Application Note 002

System
Applications
(Con't)

High-SpeetJ, Word-Oriented Application
The MAP168 device is especially suited for
high-speed word-only microprocessors. The
TMS320C20/25 OSP family is an example of
such a microprocessor. Interfacing the
MAP168 device to a TMS320C25 operating
at 40MHz with no wait states is illustrated in
Figure 7. The TMS320C25 has two pins for
selecting Program Memory (PS) and Oata

Figure 6.
DSI'System
Architecture

Memory (OS). These functions are connected to the higher order address of the
MAP168 device. PS is connected to AlB
and OS is connected to AI7" Usually PS will
select the EPROM and OS will select the
SRAM. The PAO permits partitioning of the
MAP168 memory to accommodate virtually
any system address map. Figure 8 shows
two possibilities.

.

,....

CSTo Ports

Fast
Decoder
(PLD)

1/0 Port
Interface

EPROM

16-18
ADDRESS

.
L..t CS

,..

OE

Digital Signal

.

~ f--t AD

AD

L..t CS
RD

EPROM

OE

DATA (0 7)

DATA (0·7)

Processor,
MIcroprocessor, or
Mlcrocontroller

16

DATA
--- I
I
I

WR

1

I

BHE

-------1

~

I

.

_

.

-WR

I
I

_
SRAM
CS

I

'-----., AD

Only Where Byte
I
I
: Operallons Are Needed I
• Replaced by
MAP168 Device

DATA
(07)

L- OE

I
I

_
DATA
'-- OE (0"7)

,....
t-- f--t

.

WR
CS SRAM

'-- I-< AD

------------

1739 06

Figure 7.
TMS320C25
Interfacing
x16 Configuration

40 MHz

---

~

PS

Memory Configuration
8Kx 16 EPROM
2Kx 16 SRAM

CK

i5S

A17

Ao-AI5

-v

TMS320C25

~

-

A 19
AlB

00-015

--v

"
READY

STRB

RiW

I

>----

A I - 16
MAP168
Ao
0 0-0 15

WR
OE

~

CSI/A 20

WAFERSCALE INTEGRATION, INC.

1739 07

4-7

MAP168 - Application Note 002

System
Applications
(Con't)

When in a word-wide (x16) configuration, the
total memory available on the MAP168 device
is 8Kx16 of EPROM and 2Kx16 of SRAM.
The implementation shown in Figure 7
replaces at least five circuits:

o
o
o

One high-speed decoder (10ns)
Two 8Kx8 EPROMs (30ns)
Two 2Kx8 SRAMs (30ns)

If the system was previously implemented
using a boot EPROM, the MAP168 device
replaces ten circuits:

o
o
o
o

o

One high-speed decoder (10ns)
Two 8Kx8 EPROMs (30ns)
Two 2Kx8 SRAMs (30ns)
Two 8Kx8 slow EPROMs
Three ICs for Wait-State generation

For expanded memory requirements in a
word-wide (x16) configuration, two MAP168
devices can be interfaced directly with a
TMS320C25, as shown in Figure 9. The two
MAP168 devices provide the total system
memory. Key features of this system are:

o
o

40ns access time
16Kx16 EPROM

o 4Kx16 EPROM
o 16 general purpose programmable chip
selects
The general-purpose programmable chip
select outputs can be mapped to any location
in the address space via the PAD. These chip
selects can be used to access I/O ports,
select additional memory or control other
system functions.

Figure 8. Memory
Mapping With
MAP

a. Contiguous Mapping

4-8

WAFERSCALE INTEGRATION, INC.

b. Split Mapping

1739 DB

MAP168 - Application Note 002

Microcontrol/er
Application

The MAP168 device has two basic configurations. They are a word-wide (x16) configuration with byte operation capability and a bytewide (x8) configuration with 8 chip select
outputs.

simple interconnection of the MAP168 device
to a microcontroller. The HPC16040 operating without wait states requires a memory
access time of 65ns or beUer. This makes the
MAP168 device a good fit, since it offers an
access time of 40ns, leaving a 25ns margin.

The 128K address space (during byte operations in the word-wide mode) makes the
MAP168 device especially suited for microcontroller applications. Figure 10 illustrates a

Figure 9. DSP
with Expanded
Memory

The MAP168 device can be configured in a
byte-wide (x8) mode and can also be
doubled-up with a second device.

PS

A18

DS

40 MHz - - t

A17

...J".

Ao-A'5

[l

TMS320C25
0 0-0 ,5

--

STRS
READY

r

A1- 16
Ao' A,9' CSI

0 0-0 '5

!v-

-

SHE

r--

RiVi r--

MAP168

l

;rr---e

-

h

WE

OE

A,B
Au

MAP168

A1-16
Ao. A ,9 . CSI

~
~

v

Lf---t

0 0-0 ,5

-

SHE

-

n

WE

L...o OE
1739 09

WAFERSCALE INTEGRATION, INC.

4·9

MAP168 - Application Note 002

Microcontrol/er
Application
(Con't)

WSI·MAP Family
Development
Support

Embedded Controller Application
An embedded controller is an intelligent
section of logic, usually based around a
processor, dedicated to a particular task and
is not accessible for software alteration by the
user. Such applications are generally complex and are becoming more common in
system design. Typically, embedded controllers are high performance systems designed
under severe space/power constraints. On
the other hand, they have a limited ability to
be upgraded and limited program memory.
This makes them ideal candidates for the
WSI-MAP device implementation. The
MAP168 device has the following key features which are useful in such an application:

o

1M address space decoding

o

40ns access time

o

Byte operations in word-wide mode
(BHE)

WSI provides the development environment
needed to program the WSI-MAP family
products. A menu-driven software package
known as MAPLE is available under the
WISPER top-level software. It operates on
the popular IBM-PC® as a platform and includes extensive documentation on installation and operation. It generates configuration

Figure 10.
MicrocDntrDl/er
Interfacing

o

One output chip select when in the wordwide mode (FCSO)

o

Nine output chip selects when in the bytewide mode

o

Programmable Address Decoder (PAD)

A popular processor for embedded applications, due largely to its extensive software
library and development support, wide
availability of compatible peripherals and low
cost from volume production is the 80186
from Intel. Figure 11 shows how a MAP168
device can be interfaced to an 80186.
The UCS (Upper Chip Select) is connected to
CSI/A20 on the MAP168 device. The PAD is
programmed to locate a 1Kx16 EPROM slot
in the upper memory address space for a
reset subroutine. The rest of the memory can
be located as required by the user. Figure 12
shows one possibility.

files for use by the programming tools. These
programming tools include the MagicPro™
programmer hardware and the MAPPRO
software. They enable the user to program
the PAD and the EPROM. For additional information, consult your nearest WSI sales
representative.

Memory

Configuration
8K
2K

x16 Configuration

x 16 EPROM
x 16 SRAM

Ao- 15
MAP168
ALE

Mlcrocontroller
(HPC16000,
8096, e1e)

Vee

READY
SHE

WR r---------------------------~
RD r-----------------------------~

4-10

WAFERSCALE INTEGRATION, INC.

1739 10

MAP168 - Application Note 002

Figure 11.
Interfacing To
An 80186

~

A ,6-A '9

x16 Configuration

/1

AD0-15

A ,6-A '9

v

I

"-

~

Latch

l

G

J

I
+

ALE l -

G

AD S_ 15

I

Latch
80186

Vee

t

SRDY
ARDY

A0-7

I

v

MAP168
(x16)

BHE I -

BHE

-

CSI/A 20

UCS I -

-

WR I RD

FCSO To
-User
Port

WE

BE

I--

AD O_ 15

DO_ 15

~~

)

-

LCS
MCSQ-3

Figure 12.
Optional Memory
Mapping For An
80186

1739 11

1K x 16
EPROM Reset

Program
Store

Data
Store

Vector
Interrupt
Store
1739 12

WAFERSCALE INTEGRATION, INC.

4-11

4·12

WAFERSCALE INTEGRATION, INC.

Programmable SystemTMDevice
WAFERS(,ALE INTEGRA T/oN. INC.

Application Note 010

PAe1000 Introduction
By Chris Jay and David Fong

Abstract

The PAC1000 user configurable high
performance microcontroller, from
WaferScale Integration, is the first of a
generation of devices intended for
applications in high end embedded
control. Understanding the device
architecture and using its support tools
require some practical experience before

a full system design is attempted. This
application note is intended to introduce
the device and its architecture along with
the support software tools to the systems
designer. Finally to develop some simple
applications leveled at common problems
found in system design.

Introduction

The PAC1000 has many applications in
digital systems where high speed processing,
interface or control is required. The two
roles of the device are in a standalone
mode where the PAC1000 is programmed
to control data flow to or from other systems,
or as a high speed peripheral working with
a host microprocessor. Frequently, many
systems designers cannot find the ideal
solution to their requirements in a standard
chip. The designer may look at creating
the required function from discrete logic, a
combination of a number of PAUEPLD
devices, Programmable Gate Array (PGA)
products or standard gate array. In each
alternative, the designer is trying to reduce
the chip count of the system solution and
hence increase its reliability and reduce
assembly costs.

require some' additional chips. An alternative
solution would be to use additional
dedicated chips like FIFO, ALU and SRAM,
leaving the PLD/EPLD devices to handle
the glue, interface and small state machine
functions. The Programmable Gate Array
brings the system down to a possible
acceptable level but system logic still has
to be defined and routed in the logic cells
and a number of PGA devices have to be
designed such that they all work together.
Nevertheless, in the case of the
programmable solution, subsystems such
as STACK, ALU, REGISTER FILES etc.,
might still need to be configured in the
gates and registers of these devices. This
can cause an escalation in the quantity of
these chips used in the final system,
because PLDs and PGAs are not good
vehicles for integration at the subsystem to
system level. In a gate array design the
turn-around time is longer than the
programmable solution, and because the
device is not re-programmable there is a
high level of risk in going to a gate array
solution. Also, the high 'up front' Non
Recurring Engineering charges NRE can
rule out the use of gate array.

The discrete TTL or CMOS logic solution
to a systems design is considered by some
to be an old fashioned approach but still
popular with many digital design engineers.
However, designs using this technology
can quickly escalate in chip count as the
development progresses and once a
system is designed it is very difficult to
modify because the finished printed circuit
board contains devices that cannot be
re-programmed or altered in any way. Also,
a revision or system upgrade will require a
new printed circuit board design.
The PAUEPLD solution reduces the chip
count over a solution that uses discrete
logiC but still many devices are used
because the PAUEPLD products are not
very register intensive. Small subsystems
such as FIFO or a STACK require a number
of PAUEPLD devices and additionally

The Programmable Standalone Controller
offers the most likely solution to the
problem facing the systems designer. Very
often both the PAC1000 is used with
programmable logic devices to effect an
overall solution. For example in some
modes of operation PLDs are used for
address decoders to select and gate the
host interface control lines such as CSB,
ROB, and WRB. By bringing the package
count of the system down to its lowest

WAFERSCALE INTEGRATION, INC.

4-13

PAC1000 - Application Note 010

Introduction
(Cont.)

level the design cycle time reduces, so
minimizing the overall time to market of
the final product. The reason for this is
that the PAC1000 already contains the
subsystems necessary for a fully functional
system design, and being programmable, it
can be adapted to perform most functions
required from systems devices.
The PAC1000 comprises elements such
as FIFO, ALU, register files, STACK,
microcode store, loop and breakpoint
counters, special registers and interface
logic all interconnected by a general
purpose internal bus structure. The
instructions that control data flow are
contained in the EPROM section of the
microcontrol store. These instructions are
entered into the system by the designer as
assembly or high level language code.
There also exists a microcode entry level
for those designers who are used to

microprogrammable designs. Designing
with the PAC's software support tools is very
similar to writing code for microprocessors.
The end result is an assembled listing which
can be simulated prior to programming
into the PAC1000 device's on chip EPROM.
The difference between microprocessors,
conventional microcontrollers and the
PAC1000 device is found its ability to
execute instructions in parallel, and to
offer the designer a flexible architecture.
Microcontrollers and microprocessors
function on single operations of execution,
but the PAC1000 executes three instructions
in parallel during the current clock cycle.
In this way the PAC1000 device needs
fewer EPROM locations to store the code
which performs a given function. In addition
high functional speeds can be obtained
because the device can execute those
instructions at the clock rate of the system.

PACtOOO Device
Architecture

The PAC1000 device architecture can be
divided into three subsystems, see Figure
1a; a CPU section that is similar to those
found in microprocessors, a host interface,
and a programmable instruction control
unit. The instruction register can be clearly
identified with its three output sections of
control, output and CPU Operation
Definition. Figure 1b illustrates a more
detailed diagram of the system than

Figure 1a, clearly identifying the sub
structures of the three subsystems. The
different sections of the PAC1000 are
interconnected to each other by internal
buses and convey data and instructions to
and from each other. Communication to
and from the outside world is achieved
through various input and output registers,
and a Command/Data FIFO.

The Control Unit

The control unit is constructed around a
1K deep 64-bit wide EPROM, see Figure
1b. The 64-bit wide instructions are
programmed in the EPROM section and
are accessed and executed on each clock
cycle. The input RESET causes the
PAC1000 to access and execute the first
instruction at location OOOH of EPROM.
On each execution cycle, the Instruction
Register shown in Figure 1a will contain
three control operatives, a next address
instruction to the control section, an output
instruction and CPU instruction. The other
inputs to the control unit include interrupts
and condition codes. There are four external
and four internal interrupts that can be
enabled under programmed control. These
can generate a branch to an interrupt
service routine that results from a rising
edge applied to the external interrupt
input. For interrupts INTO, INT1, INT2, and
INT3 there are four locations OOSH, 009H

OOAH and OOSH respectively. These are
the vectored addresses at which processing
will continue in the presence of one of
these active interrupts. At the interrupt
location a jump to an interrupt service
routine should be inserted. For example,
the occurrence of INTO will divert
processing to location OOSH, that location
may contain a JMP 100H, where 100H is
the address where the service routine for
INTO should reside. The internally
generated interrupts are INT4, INTS, INT6
and INT? which divert processing to
locations OCH, ODH, OEH and OFH
respectively. Details of their allocated
function is given in the PAC1000 data
sheet. In addition there are eight condition
code inputs CC[?:O], shown alongside the
INT[3:0] inputs in Figure 1b. These inputs
can be tested individually under program
control. The combination of Next Instruction
Definition, Interrupt and Condition Code

4·14

WAFERSCALE INTEGRATION, INC.

---------- ---------

PAC1000 - ApplicatIon Note 010

The Control Unit
(Cont.)

input direct the flow of the program and
hence the execution of instructions
contained in the EPROM section. The
CASE logic is used in the controller
section to enable CASE statements to be
executed on condition code groups. The
eight condition code inputs may be divided
into two four bit groups. Case group zero
CGO comprises CCO, CC1, CC2 and CC3.
Case group 1 CG1 comprises CC4, CC5,
and CC7. A further two case groups
CG2 and CG3 test flag registers (see

Table 1). These condition code inputs may
be tested individually or tested in a group.
When tested in a four bit group, a one-ofsixteen branch will occur, as specified by
the CASE instruction.
The current status of the PAC1000 is kept
in the sixteen bit status register. STATOSTAT11 give twelve status bits with four
extra bit locations for future development.
Table 2 shows the assignment of each
register.

cca
Figure ta.
PACtOOO
Microcontroller
Single Cycle
Control
Architecture

cs RD WR

CONDITION CODES

HD[15:0] HAD[5:0]

-"""'=8----O~_;;C:;;0~NT;;R~0;:_Ll

INTERRUPTS

UNIT

NEXT INSTRUCTION
DEFINITION

CPU

.----_4_~ 1~~~~:

'--,.--,r-r---'
28

CLK
1/0[7:0]

ADD[15:0]

OC[15:0]

Figure tb.
PACtOOO
Microcontroller
Block Diagram

, ,

CLK

RESET

CONTROL 1/0 CONFIGURATION

I

MODE

RD

WR

I

I

I

HD[15:0]

ii i

I

CONFIGURATION REGISTERS

cs
I

I

HAD[5:0]

•+ •+

HOST INTERFACE

1

~

1

~

~

.1

J

I DATA INPUT J LDATA OUTPUTJ I COMMAND/DATA FIFOJ
~
CONTROL SECTION ~ BREAKPOINT REG

I

CPU

SEQUENCER

J

Il

LOOP CNTR
[PROGRAM CNTI!.I

,l

15 LEVEL
STACK

1Kx 64
PROGRAM
MEMORY

Is1

t
CASE LOGIC

I

TEST LOGIC INTERRUPT

I REGISTER
32 x 16
0I
FILE
I

Q REGISTER

J

AW

I

I OUTPUT

I

BLOCK COUNTER

I
I

l
OUTCNTL[15:0]

I I

t
ADDRESSJDATA
PORT

~

t

1/0[7:0]

ADD[15:0]

t

INT[3:0]

I

ADDRESS COUNTER

1/0 SPECIAL
FUNCTION PORT

CC[7:0]

t

I

I

t

WAFERSCALE INTEGRATION, INC.

4-15

PAC1000 - Application Note 010

Table 1.
CASE Group
Assignments

Condition Code

cco,

CASE

CC1, CC2, CC3

CASE Group 0

CC4, CC5, CC6, CC7

CASE Group 1

S, 0, Z, CY.

CASE Group 2

INTR, BCZ, FIOR, FICO.

CASE Group 3

FIXp, ACO, STKF, FIIR, DOR, INTR

Table 2. Status
Register

0

WSI
Reserved

0

S11

S10

S9

S8

N/A

S7

S6

S5

S4

S3

S2

S1

so

S11 - Security Bit, High is Active Security On, Low is No Security.
S10 - Scan Mode, High is Active On, Low is No Scan Mode.
S9 - FIXP FIFO Exception Occurs When a Command is Written, a Low Means No
Exception.
S8 - FIIR FIFO Input Ready When There is at Least One Location Vacant.
S7 - CY Set High When the Result of a CPU Operation Generated a Carry.
S6 - Z Set High When the Result of a CPU Operation is Zero.
S5 Set When an Overflow Has Occurred During a Two's Complement Operation.
S4 - S Sign Bit Set to One When the Result is a Negative Number.
S3 - Stack Full Flag. Set When the Stack is Full.
S2 - Breakpoint Flag is Set When the Address in the Breakpoint Register is Equal
to the Address in the Program Counter.
S1 - BCZ is Set When the Block Counter Reaches Zero.
SO - ACO Address Counter All Ones Flag is Set When the Address Counter Reaches
the Maximum Count.

a

The Control Unit
(Cont.)

Host Interface

4·16

A single internal counter is provided for
loop control, this is part of the control
section, and is shown in Figure 1b. If a
FORLOOP is executed the loop counter is
loaded and the instructions within that
loop are executed until the counter has
decremented to zero. The loading of this
counter is transparent to the designer in
the respect that the FORLOOP instruction
automatically performs loading and counting.

are possible because the current contents
of the loop counter is saved in the stack
when the next subsequent loop in the next
is entered. When leaving the loop the
stack is popped to return the old count
back into the loop counter thus preserving
its original contents. When the stack
becomes full a status flag STKF is set in
the sixteen bit status register and an
interrupt level 7 is generated.

A fifteen level stack is incorporated to hold
the return address of the main program
when a subroutine call or interrupt service
routine is being executed. The address of
the next sequential instruction to be
executed is pushed onto the stack. The
stack is also used for LOOP NESTING.
There is only one loop counter in the
PAC1000 but nested FOR LOOP instructions

To enable a debugging facility a register
called the breakpoint register is included
in the microcode section. When the
contents of the program counter is equal
to that of the breakpoint register an
interrupt level six is generated. For
debugging purposes a level six interrupt
service routine should be written to
perform diagnostic tests within the system.

The host interface section has been
designed to easily integrate into a CPU
based system. When the PAC1000 is used
in the peripheral mode, the flow of data or

WAFERSCALE INTEGRATION, INC.

commands to its internal registers may be
achieved through an internal FIFO. Standard
microprocessor signals of chip select CSB,
read ROB and write WRB (active LOW CS,

PAC1000 - Application Note 010

Host Interface
(Cont.)

RD and WR) are accompanied by a
sixteen bit Host Data and a six bit Host
Address bus. Table 3 gives the conditions
governing the mode setting for both
standalone and peripheral mode. The logic
condition of HDSELO and HDSEL1 in the
control register will determine the mode of
the PAC1000 operation. Bit positions in
this register can be set or reset under
program control.

powerful feature that enables dynamic
context switching of PAC1000 under
supervision of the host processor. The
FIFO exception flag FIXP will be set if the
information residing in the FIFO was
misdirected (if it were treated as a control
word when the FICD flag labeled it as
data or if the opposite condition prevailed).
Using the FIFO is the only method in
which the host can communicate with the
PAC1000 using the active LOW chip select
CSB and the write input WRB. The DOR
and DIR are Data Output and Data Input
registers and are available to convey data
to and from the internal sixteen bit bus but
do not respond to CSB and WRB. The
DIR would be used in a synchronous
system because, when it is enabled by
setting the DIREN flag (see Table 4), data
is latched on the rising edge of each clock
signal. The data contents of the DOR
register may be directed to the host data
outputs if all inputs CSB, WRB and RDB
are inactive and HDSELO and HDSEL1 are
1 and 0 respectively, see Table 3. The use
of the DIR and DOR register is intended
more for synchronous communication
whereas the FIFO is intended primarily for
asynchronous systems or synchronous
peripheral interface. The flags FIIR and
FIOR are the FIFO Input Ready and FIFO
Output Ready respectively, these flags can
be tested so no overwriting of data will
occur. Figure 3 shows the 1/0 Port and
Special Functions. The FIIR register can
be directed to the output 1/07 through a
multiplexer so it can be tested externally
by the host system.

A detailed block diagram of the PAC1000
is given in Figure 2 which illustrates the
internal structure of the control section,
processor section and interface. Data flow
from the host processor data inputs
HDO-HD15 to the internal 16-bit bus can
be achieved through the FIFO section. The
FIFO is eight locations deep and twentytwo bits wide. To transfer data words to the
registers in the CPU section the host
processor uses the chip select, write and
HAD inputs. The address of the register is
set up on the five HAD lines (this selects
one of 32 registers) then the write and
chip select lines are driven LOW. The data
on the HD lines plus the register address
is loaded into the FIFO. An additional bit
called the FICD bit is loaded through
HAD5 at the same time as address
HAD[O-4] and the host data lines HD[O-15].
This is the FIFO Command/Data bit and
must be LOW to signify that the sixteen bit
word on HD[O-15] is data. If it is set HIGH,
the least significant ten bits of that data
will be used as an address pointer to the
microcoded EPROM. In this way the host
system can direct PAC1000 processing to
a defined microcoded address. This is a

Table 3. Host
Interface
Function Table

HOSELO HOSELt CS RO WR HA05 HAO[0-4}

HO[15-0}

0

0

0

1

0

0

Register
Address

0

0

0

1

0

1

X

Command

Data

OPERATION
Write Data to FIFO
Write Command
to FIFO

0

0

0

0

1

0

00100

X

Reset FIFO

0

0

0

0

1

0

00011

X

Reset Status Register

0

0

0

0

1

0

00010

X

Read Program
Counter

0

0

0

0

1

0

00001

X

Read Status Register

0

0

0

0

1

0

00000

X

Read Data Output
Register

1

0

1

1

1

X

X

X

Data Output Register

0

1

1

1

1

X

X

X

Status Register

1

1

1

1

1

X

X

X

Program Counter

WAFERSCALE INTEGRATION, INC.

4·17

PAC100D - ApplicatlDn NDte 010

Figure 2.
PACtDOO
Detailed
Block Diagram

HAD

HD

l l

1"

f16

HOST
INTERFACE
DECODER

V~

IHDOE-

~

1

DATA
INPUT
REGISTER

DATA
OUTPUT
REGISTER

~

FIFO (8 x 22)
8x5
REGISTER
POINTER

8 x 16 COMMAND
AND
DATA FIFO

STATUS
REGISTER

~FIIR

16

DOR

6

16
SR

h6

f16

V~

16

DOR

~

IHADOE-

16

DECODED
SIGNALS

DIR

f6

6x1

~

16

INTEtNAL
FLAGS

FICD

5
REGISTER
SELECT

r8
CC
INTERNAL

cc
INTERNAL

i.....+

~ I
I
~ I
I

I

BREAKPOINT
REGISTER

INTR
CLK

CONTROL UNIT

-

~

LOOP
COUNTER

~ II

INTR
4

REGISTER
FILE AND
Q REGISTER

15-LEVEL
STACK

TEST

----.

INTERNAL
CONTROL
SIGNALS

PROGRAM
COUNTER

S

I

1Kx 64
EPROM

AW
CPU

I

BLOCK1j+
COUNTER

BC

1/0
CONFIGURATION

t

MODE

BCEN
CONTROL
CONFIGURATION REGISTERS

16

RESET

V

Vee

L-

16

16

16

6

ACH

ACL

OUTPUT CONTROL

GND

r

16

OC

I

SWAP
REGISTER

a

a
IIR

lOR

1/0
OUTPUT
REGISTER

1/0
INPUT
REGISTER

,

{.
fa

Y

1/0

4·18

16

WAFERSCALE INTEGRATION, INC.

16
AIR
ADDRESS
INPUT
REGISTER

~
AOR

ADDRESS
OUTPUT
REGISTER

iAiReN
16

I

ADDRESS
COUNT
HIGH

,

ADDRESS
COUNT
LOW

~

t

ACS22

V~ ~

t

16

ADD

PAC1000 - ApplicatlDn NDte 010

Figure 3. I/O
Port and Special
Functions
FIIR

CNTL4
(ADOE)

B MUX
Q
A S

IADOE

MODE 7

CNTL3(HADOE)

B MUX
Q
A S

IHADOE

MODE 6

CNTl2(HDOE)

B MUX
Q
A S

IHDOE

IIR

D CK
MODE 5

SDATM

II

QMSB
ClK

SDATl
QlSB

>------1-+--....----+---1 B MUX

IACEN

Q

a·BIT
INPUT
BUS

a·BIT
OUTPUT
BUS

WAFERSCALE INTEGRATION, INC.

4-19

PAC1000 - Application Note 010

Table 4.
Control Register

CTRL9 CTRL8 CTRL7
ASEL

ASEL

AIREN

-

CTRL4

CTRL3

CTRL2 CTRL1

CTRLO

HDSELO

ADOE

HADOE

HDOE

ACEN

BCEN

Selects Which Source Will Write to the Address Bus
1 = Address Counter. 0 = Address Output Register.
Enables/Disables Writing to the Address Input Register by the Address Bus.
1 = Enabled. 0 = Disabled.

DIREN

Enables/Disables Writing to the Data Input Register.
1 = Enabled. 0 = Disabled.

ADOE

-

Decoded to Select Which Source Will be Connected to the Host Data Bus
(See Table 3.).
Selects Direction of the Address Bus
1 = Output. 0 = Input.

HADOE -

Selects Direction of Host Address Bus (HAD).
1 = Output. 0 = Input.

HDOE

-

Selects Direction of Host Data Bus for Next Clock Cycle.
1 = Output. 0 = Input.

BCEN

-

EnableslDisables Block Counter Before Next Clock Edge.
1 = Enabled. 0 = Disabled.

ACEN

4·20

DIREN HDSEL1

CTRL5

AIREN

HDSEL1
HDSELO -

Central
Processing Unit

CTRL6

Enables/Disables Address Counter Before Next Clock Edge.
1 = Enabled. 0 = Disabled.

The section that deals with data processing
is the central processing unit. This
comprises a sixteen bit wide ALU with a
32 x 16 bit register file. One other special
purpose register Q and an R shifter circuit
make up this section. The Q register is
sixteen bits wide and can be used for data
shifting. Figure 4 shows the ALU and
register structure of the CPU section. The
ALU is in the path of the register outputs
such that arithmetic and logic functions
may be executed on the contents of any
one of the 32 general registers. The output
of the ALU passes data back to the
selected register through the R shifter. In
this logic circuit, data may be shifted
either left or right, one position, before
being written back into the register file.
The output of the ALU can also drive data
to registers such as the DOR register. A
multiplexer can select either the ALU or
the RO-R31 register output. The loop
counter LC can be loaded from this
multiplexer enabling the contents of a
register to determine how many program
loops are to be executed. This loop
counter can be loaded from the EPROM to

WAFERSCALE INTEGRATION, INC.

give a fixed number of loops or from a
register at program 'run time: In this
event, the number of times a loop is
executed can be made programmable.
Other registers on this bus are AOR,
Address Output Register, the lOR, Input
Output Register, the ACL and ACH low
and high address counters and the BC
Block Counter. The ACL counter has a six
bit resolution and the ACH counter has
sixteen. When enabled by ACEN, the ACH
counter will increment on the rising edge
of each clock cycle. The default value is
for a sixteen bit count. To enable a twentytwo bit count where the ACL takes on the
six least significant of the twenty-two bits.
The ACS22 flag must be set, to enable the
clocking of these counters. This is
transparent to the software because once
enabled the counters will clock at the
system clock rate. However, they can be
turned on and off from the microcoded
instruction of enable SET ACEN, or
disable RESET ACEN, also counting can
be influenced by register loading.

PAC1000 - Application Note 010

Figure 4.
PAC1000 ALU
and Registers
Structure

,---------------------------------------------,
I
I
I
I
Z FLAG

CY FLAG
SIGN FLAG

"0"
"1"
QMSB

RMSB
QMSB
SDATL

a:
w

lLl..

a:

:;:

w

~w Q I - - - - j '"o

a:

IN (B)

ClK

F O

REGISTER
BANK
(R31IRO)

QlSB

,------,

CONSTANTS

HOST
INTERFACE

HOST
INTERFACE

ADD
BUS

110
BUS

I

I

I
I

I
I

I

I

I
PART OF
I
~~~~L ~E.:r.!?~

WAFERSCALE INTEGRATION, INC.

4·21

PACtOOO - Application Note OtO

Support
Software

The PAC1000 device is supported with
development software that can run in an
IBM PC/XT or AT computer. The main
tools that the designer will use are the
assembler, the linker and the simulator.
These support programs are run from a
WSI menu called WISPER that has been
designed to make software development a
simple process. The designer can select
the assembler from the menu and assemble
his source program. After assembly the
program must be linked. The linker program
is designed for those system designers
who build their software up from a number
of modules. Figure 5 illustrates the flow
from original source code entry through
the linker to a simulated output. The linker
will take these modules and combine them

Figure 5.
Program Flow
From Assembly
Input to
Simulated
Output

into one object program. On completion of
assembly and linking the program may be
checked by the simulator. The use of the
simulator removes the need for EPROM
programming and in-circuit testing during
the design cycle and gives the designer a
fairly high level of confidence that the
program will function as intended. The
simulator will take the bit pattern format
that was generated during assembly and
apply a command and stimulus file to the
program. The result will be a series of
waveforms that appear on the screen of
the PC and is similar to that of a logic
analyzer display. A table of vectors is also
generated for those signals that are traced
from the command file. These vectors can
be printed out for analysis and verification.

.MAL

.ML

.LIS
.OB

.LIS

.STL

.ABS

' - - - - - - - - - . .OBJ

.OUT

4-22

WAFERSCALE INTEGRATION, INC.

PROGRAMMED
DEVICE

PAC1000 - Application Note 010

Microcoded
EPROM Section

A further aid to the design entry is the
ability to mix high level, assembler and
microcode mneumonics so designers can
use the entry level that they feel the most
comfortable with. Most of the applications
example given below are written in a high
level 'C' like language but some assembler
instructions are also incorporated.
In systems applications such as Direct
Memory Access (DMA), it is required to
output the contents of a counter to
address memory and then increment it.
This is implemented in the PAC1DDD high
level language syntax as:
AOR : = RD

; I*CONTENTS OF RD
GOES INTO THE AOR*!

With conventional programmable logic an
ALU function would have to be designed
or a dedicated custom chip used with the
programmable logic part used as the data.
I/O controller. The key point of this issue is
that complex logic functions are simply
written as a few single lines of statements.
Moreover, a combination of functions may
be grouped in a single line. These include
a microcontrol directive such as a branch,
call to subroutine or JUMP on condition,
an ALU function such as increment or
add, and an output control command.
There are sixteen output control lines
which can be driven active on each clock
cycle. The composite of the three
commands are:

RD:= ++RD ; I*REGISTER RD IS
INCREMENTED BY ONE*/

LABEL:

For efficiency these two instructions may
be combined into one line of code, which
is executed in one clock cycle:

The function of this line of code would be
to wait until the condition code input of
CC7 went active before the next instruction
is executed. At the same time the contents
of RD would be incremented and the
output control lines would be driven with a
sixteen bit code called HOLD. An equates
option 'equ' is used to define uniquely a
sixteen bit pattern called HOLD. The
assembler encodes an equate statement to
allow meaningful words to be used in
output control statements. Some examples
of this are:

AOR:= RD:= ++ RD;
/*COMBINING THE TWO OPERATIONS*/
The contents of RD will be passed to the
Address Output Register and will be
incremented by the ALU.
Where AOR is the address output register
and RD is one of the thirty-two, 16-bit
general purpose registers. The '/*' symbol
delimits the comment field boundary.
With a PAUEPLD/PGA approach the
designer would be required to spend much
'valuable time configuring a loadable binary
counter, with a 3-State output capability.
In applications such as digitizer/plotter
systems, x,y coordinates have to be quickly
summed or subtracted many times to
register cursor movements and position.
This requires repetitive arithmetic
operations. In this application vector
addition on two or more sixteen bit words
can be defined as two instructions:

JMPNC CC7 LABEL,
RD := RD + 1 , OUT 'HOLD' ;

HOLD equ H'FFFF' ;
1* HOLD IS SET AS HEX FFFF */
ENBL equ H'EFFF' ;
1* ENBL IS SET AS HEX EFFF *!
The equates directive should be declared
at the start of the program before any
actual code is written.

RD := RD + R1 ;
AOR:= RD;
Combining these instructions together:
AOR := RD := RD + R1 ;

WAFERSCALE INTEGRATION, INC.

4-23

PAC1000 - Application Note 010

Applications
Programs

OC[15:0j and wait for a response to a
condition code input eC[7:0j. Under
program control a conditional JUMP to a
location could result if the bit tested were
set. Otherwise linear programming could
continue.

The depth of the microcontrol store is 1K
of 64-bit wide words. One 64-bit instruction
is executed on each clock cycle. The
instruction word is subdivided into three
commands: an output control command, a
command to the processor section and a
next address command to the microcoded
memory. Figure 1a shows the Instruction
Register with its contents of control, output
and epu commands. The control unit will
also respond to condition code inputs and
interrupts. An example of output control
and response to condition codes is in a
handshake loop. The output stimulus can
be to set one of the control outputs

The first applications program below
demonstrates the use of condition code
zero eeo to test for a start condition.
When the input is LOW, the program loops
continually testing eeo. When the host
raises eeo, the program performs a
double precision addition. The sum is
available at the data output register DOR.

segment pacdesOl :
1* PROGRAi1 TO PERFOR!'l DOUBLE PF~=:CISION ADDITliJN ON THE REGISTER*/
1* CONTENTS OF FU .RO: R3.R:: THE CARRY OF THE LEAST SIGNIFICANT *1
1* "JORD ADDI nON IS CONTAINED IN THE CP REGISTEr, AND IS USED IN*I
1* THE SECOND HALF OF THE 32 BIT ADDITION.
*1

PIN FUI-lCTIONAL DESIGNATIONS.
INPUTS.

*1

CCO
(lCTIVE HIGH - START 32-BIT ADDITION
/CS - ACTIVE LOW - PAC10)O CHIP SELECT
IRD - ACTIVE LOW
READ A REGISTER FROM HOST
HAD[5:0] - INPUTS TO SELECT DOR REGISTER FRat1
HOST INTERFACE

HOLD:

Jt1PNC

CCO HOLD :

RO := H'F83,)

Rl := H'982F'
R2 :::::: H 'A309'
R"" := H'4500'
.j

I*WAIT FUR STf:lRT CONDITION

J MF'NC

DOF~

LOOP 1 :

DOH := Rl

4·24

1* LOAD MOST SIG WOFm INTO DOR *1

IJHHT FOR HOST TO READ DATA *1

l*

FIN:

JMP HOLD

I*END OF THE CYCLE*/

WAFERSCALE INTEGRATION, INC.

*J

1* WAIT FOR HOST TO HEAD DOR *1

JrlPNC DOR LOOF'2

=

*1
*/

I*LOAD DOR REGISTER*I

LOOP2:

end

*1

I*LOAD REGISTERS WITH DATA *1
/*F:(} AND R2 CONTAIN THE
*1
/*LEAST SIGNIFICANT WORD OF *1
/*THE 32 BIT LONG WORD AND '*1
I*Rl AND R3 CONTAIN THE MOST*I
!*SIGNI~ICANT WORD
*1

H5 : = Rl ~
R4 : = Re) :
DOR := RO := RO + R2
Rl := Rl ~ R3 + CP

LOOP 1 :

*1
*1
*1

PAC1000 - Application Note 010

Applications
Programs
(Cont.)

The program adds the contents of RO and
R2, then R1 and R3 and the CARRY bit.
In the next design example, double
precision subtraction is performed and this
time the CY flag will hold the borrow bit.
This design example is more practical than
the example above because instead of
performing arithmetic on fixed values the
register file may be loaded from a source.
The configuration of the PAC1000 is in the
peripheral mode and data is loaded into
the FIFO. CCO is monitored and, when
active, is a signal to the PAC1000 that data
has been loaded. The FIFO is unloaded

into the registers by the series of
instructions:
FOR 3

; !*EXECUTE THE LOOP
FOUR TIMES*!

RDFIFO ; /*UNPACK DATA FROM
THE FIFO*!
ENDFOR ; !*END THE FORLOOP *!
This section of the program performs a
read operation on the FIFO four times. In
any FORLOOP N, where N is an integer
value, the number of times the loop is
executed is N + 1 times.

seament pacdes02 ;

/ *PROCF;,:ii'1 TO PEF::FOF~i'1 DOUBLE PREC I S ION SUBTRACTI ON Qt.] REG I STEF~ * I
I *CONTEI>lTS R 1. R(I ; R3. R2 THE BORROW FLAG 1 S CONT i'l I NED I N THE * /
I*CP F;EGISTER DURING THE SECOND HALF OF A 32-BIT SUBTRACTION
*1
1*
*1
1*
PIN FUNCTIONAL DESIGNATIONS
*1
1*
INPUTS
*1
1*
CCO
i-ICTIVE HIGH - START PROGRAt"1
*1
/lOICS
ACTIVE LOW - PAC100!) CHIP SELECT
*1
1*
IWR
ACTIVE LOW - FIFO WRITE
*1
1*
IfW - ACTIVE LOW - F;EAD (~ REGISTER FROM HOST INTEF:FACE*I
1*
HAD [5: I) J - I NPUTS TO SELECT A REG I STER FF;OM THE HOST
*1
1*
INTERFACE
*1
l-lI'
HD[15:0J
['ATA INPUTS TO FIFO THROUGH HOST INTERFACE *1
1*
*1
HOLD:
JMPNC
CCO HOLD
I*WAIT FOR START CONDITION EMFTY
""1
FOR 3
I*THE FOUF; LOCATIONS OF THE FIFO
*-1
RDFIFO
I*LOADED THROUGH THE HOST INTERFACE *1
ENDFOR
I*SECTION OF THE PA(11)OO
*1
R5 : = R1 :
/*SAVE Ri CONTENTS IN R5*1
R4 : == [;:0 ;
I*SAVE RO CONTENTS IN R4*1
I*SUBTRACT LSW PROPAGATE*I
DOR : = RO :: = RO - F~2
Rl := Rl - R3 - CP ;
l*THE BORf{OW INTO THE CF-*l

DOH := HO
LOOP1:

JMF'NC DOR LOOP1 :
DOF~

LOOP2:

I*LOAD DOR WITH MSW

: = Hi

I*LOAD DOR WITH MSW

JMPNC DOR LOOP2
Jf1P HOLD :

I*END OF PROGRAM

end:

WAFERSCALE INTEGRATION, INC.

4·25

PACI00D - Application Note 010

Applications
Programs
(Cont.,

The next program shows a multiply routine.
Although there is no dedicated multiplier
in the PAC1000, multiplication can be
achieved by shifting and adding. The MUL
instruction is a MACRO command that is
expanded when assembled into a loop of
shift and add instructions. The RDFIFO

instruction is used to pass the data from
the host to the PAC, which is configured
as a peripheral. In the example the contents
of RO and R1 are multiplied and the product
is available in registers R1 and R2, where
R2 contains the most significant word and
R1 the least significant.

seqmp.nt oacdes03 :
HOLD:

LOOP1:
SELF:
end:

JMPNC
CCO HOLD
FOR 1
RDFIFO
ENDFOR
MUL R2 Rl RO :
DOR := R2
JMPNC DOR LOOPl :
DOR := Rl
JMP HOLD :

I*WAIT FOR START CONDITION EMPTY*I
I*THE TWO LOCATIONS OF THE FIFO *1
I*LOADED THROUGH THE HOST INTER-*I
I*-FACE SECTION OF THE PAC1000 *1
I*REGISTER. THE PRODUCT IN THE *1
I*DATA OUTPUT REGISTER
*1
1*

I*END OF PROGRAM

In the following example, the contents of
registers R2 and R1 is divided by the
contents of register RO. The most significant
word of the 32-bit long word is held in

*1
*1

register R2 and the least significant 16 bits
are stored in R1. The result of the divide
operation leaves the quotient in the Q
register and any remainder in register R2.

segment oacdes04 :
HOLD:

LoOP1:
SELF:
end:

JMPNC
CCO HOLD
FOR 1
RDFIFO
ENDFoR
DIV R2 Rl RO :
DOR := Q
JMPNC DOR LOOPl ;
DoR := R2
JMP SELF ;

I*WAIT FOR START CONDITION EMPTY*I
I*THE TWO LOCATIONS OF THE FIFO *1
I*LOADED THROUGH THE nCST INTER-*I
I*-FACE SECTION OF THE PAC1000 *1

The files generated so far can be entered
into the assembler and two files
.LlS and .OB may
be generated as shown in Figure 5. The
latter object file must be linked before the
final object file is available for programming
into the PAC1000's EPROM. The link
program .ML performs this
function and is shown below.
load pacdes04 ;
place pacdes04 ;
end;
This design example only used one
program but many sub-modules may be
linked together to form a single executable
program. It is possible to simulate the
design after linking. The necessary inputs

4-26

WAFERSCALE INTEGRATION, INC.

I*OUTPUT THE REMAINDER*I
I*OUTPUT THE QUOTIENT. *i
I*END OF PROGRAM
*1
to the simulator are the .OBJ,
.STL and .CMD. The
latter two files are the input stimulus file
and the input command file (see Figure 5).
The stimulus file is used to drive inputs
such as address, data and condition codes.
The command file lists which signals
should be traced for observation. Examples
of the stimulus file and command file are
given below.
The command file shown below will instruct
the simulator to set an output trace on the
Current value of the Program Counter,
CPC. The Condition Code zero input, the
write, and the chip select lines are also
traced. The simulator also enables a trace
to be invoked on registers as well as input

PAC1000 - Application Note 010

Applications
Programs
(Cont.)

or output pins. The Q register is traced
along with host data, loop counter, and
registers RO, R1, and R2. The final trace is
set on the host data output register. At the
end of the stimulus file, the run instruction

informs the simulator to run the driving
signals for 140 cycles. The final instruction
invokes a View Trace Waveform instruction,
so the waveforms may be observed on the
PC screen.

OPEN STIMULUS PACDES04
SET TRACE CPC
SET TRACE CCO
SET TRACE WRB
SEf TRACE CBB
SET TRI::;CE FmB
SET TRACE Q
SET TRACE HD
SET TRACE LC
SET TRACE F:O
SET TF:AC;::: Rl
SET TRACE R2
SET TRACE HDOR
OPEN TRACE PACDES04
FWN 14('
V T W
The stimulus file is used to apply active
signals to inputs of the design. At specific
time points conditions are established. For
example the statement:
.S

ceo 0@1

1 @40

means that the input condition code zero

ceo should

become a logic state LOW at
time point one and a logic HIGH condition
40 cycles later. A three-state condition can
be applied by typing the letter Z in place
of logic '1' or '0.' The stimulus file is
completed to drive all inputs and applied
to the simulator during run time .

. S RESETB 0 @ 1 1 @ 2 ;
1@40 ~
.S WRB 1@1 0@2 1@8 0@12 1 @19 ~
.S CBB 1@1 0@2 1@9 0@11 1@18 0@120 1@129 0@131 1@139
.S RDB 1@1 0@121 1@129 0@131 1@139
.S HAD!) 0@1 1@10 0@24 ~
.S HADI 0@1
.S HAD2 0@1
.S HAD3 0@1
• S Hf~D4 0@1
.S HAD5 0@1
# WRITE A 7 INTO RO AND 31 INTO Rl
.S HDO 0@1 1@10 Z@70
.S HDl 1@1 Z@"70
.S H02 0@1 1@10 I@70
.S HD3 0@1 1@10 Z@70
.S HDll- 0@1 1@10 Z@70
.s HD5 O@l Z@70
.S H06 0@1 Z@70
.S HD7 0@1 Z@70
=S HD8 0@1 Z@70
.S HD9 0@1 Z@70
.S HDIO 0@1 Z@70
• S HDll 0@1 Z@70
• S HDl2 0@1 Z@70
.8 HD13 0@1 Z@70
.. 8 HD14 0@1 Z@70
.S H015 0@1 Z@70
The comment field is denoted by a '#' sign.
• S CCO 0@1

WAFERSCALE INTEGRATION, INC.

4·27

PAC1000 - Application Note 010

Case Statement

Logic

The ability of the PAC1000 to perform case
statement logic has already been discussed
but the following program excerpt illustrates
how to encode the case statement. The
program will execute when condition code
7 is active high, then case group CGO is
tested for one of sixteen possible states.

CGO comprises CCO, CC1, CC2 and CC3.
Sixteen registers are initialized and the
output code is driven with zero. When CC7
goes HIGH the CGO input is tested and
the register contents that are equal to the
state of the CGO input is transferred to the
AOR outputs.

segment pacdes05 :
/* illustrate the use of

RI) := I)
Ri := 1
R2 := 2
R< := 3
R4 := 4
R5 := 5
R6 := 6
R'1 := 7
R8 := 8
R9 := 9
RIO := 10
Rl1 := 11
RI2 := 12
R13 := 13
F.:14 := 14
R15 := 15
WHILE CC'1
SWITCH CGO ;
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
C{\SE
ENDSWnCH ;
NEXT : OUT I)
ENDIIJHILE ;
[lUT h'FFFF'
LOOPX
GOTO
end ;

multiwav branching *1

~.

4·28

WAFERSCALE INTEGRATION, INC.

0

1
2
3

4

·

·

5
6
7

8
9
10

11
12

13
14

15

•

GO TO NEXT
GO TO NEXT
GOTO NEXT
GOTO NEXT
GOTo NEXT
GOTO NEXT
GOTG NEXT
GOTO NEXT
GoTo NEXT
GoTO NEXT
GOlD NEXT
GOTO NEXT
GO TO NEXT
GO TO NEXT
GOTO NEXT
GOTO NEXT

.

LOOPX

AOR := RI)
AOR :;= Ri
AOR := R2
AOR := R3
AOR := R4
AOR := R5
AOR := f~6
AOR := R7
AOR := RB
AOR := R9
AOR := RiO
AOR := Rll
AOR
R12
• AOR :=
:= R13
AOR := R14
AOR := R15

PAC1000 - Application Note 010

Simple OMA
Controller for
Memory to
Memory Transfer

The software designs discussed so far
have been based on arithmetic functions
but an important feature of how to use the
FIFO in the host interface section of the
PAC1000 for the communication of data
will enable the reader to develop ideas
into more complex programs. The FIFO
Output Ready flag is used in a loop to
read the data into the registers. The output
codes are used to create signals to control
read, write, latch, output enable and bus
acknowledge signals. A summary of these
signals is given in Table 5 each time an
instruction is executed. These signals are
generated to accompany the memory
addresses which control the DMA cycle.
Figure 6a shows a generic system solution
where the PAC1000 sits on the address
and data bus of a microprocessor and
memory interface. The PAC1000 is mapped
into the system with a PLD decoder and
an external latch is used to catch data on
read and write cycles. It is possible to use
the internal DIR and DOR for this purpose
but a faster solution would use an external

component. Also, if the bus were greater
than sixteen bits, an external latch would
be required. This mode where data does
not enter the PAC1000 device is called the
'fly by' mode.
Figure 6b shows the timing waveform
derived from the program simulation.
Active LOW WRB and CSB inputs to ADD1,
ADD2 and ADD3 will write to the registers.
The Source Address Register RO, the
Destination Address Register R1 and the
transfer counter R2 are all loaded through
the FIFO. At time point 1, the registers
become loaded. At time 2, CC7 is set
HIGH to indicate transfer can commence.
The response from the PAC1000 is an
active LOW output from output control
OC14 to inform the microprocessor that
DMA activity is taking place. This occurs
at time point 3. OC14 stays LOW during
DMA activity but goes HIGH after the
transfer is complete (at time point 4).
Three transfers have taken place and the
microprocessor is free to regain control of
the bus.

segment pacdes06;

I*THE PROGRAM ILLUSTRATES A SIMPLE DMA DESIGN WHICH *1
I*READS THE DATA FROM SUCCESSIVE MEMORy LOCATIONS
*1
I*ADDRESSED BY THE CURRENT CONTENTS OF RO THEN L-Y_E_S_

~~S~LPREV

RESET
BUSMSTR

GO TO MAIN

II

GO TO MAIN

WAFERSCALE INTEGRATION, INC.

4·59

PAC1000 - Application Note 005

Appendix 4
/************************************************************************/

/*
/*
/*
/*
/*

device to memory byte transfer
of the memory is loaded in R3
in Q • Assume that the initial
PAC has control of the bus.
block size is a multiple of 64

in the fly-by mode. The start address */
and R4 and the device number is loaded*/
protocol has been gone through and
*/
For simplicity it is assumed that the*/
and R5*64 = block size.
*/

/*****************************************************************-*******/

segment b dm byte ;
/* define equates */
bgn equ CC7
ready equ CC4
b dm byte norm equ h'OOde'
b-dm-byte-read equ h'OOd6'
b-dm-byte-write equ h'OOc6';
init b-dm-byte-:
-ACH
R3
SET ASEL ADOE HADOE
ACL := R4

:=

lOR := - Q ,
OUT b dm byte norm
Q := T LDLCD , MOV R5 R5

;

/*
/*
/*
/*
/*

bus grant (active low)
ready input
dma active w/o read/write
read (active low )
write (active low )

/* upper 16 bits address

*/
*/
*/
*/
*/

*/

/* select counter to output ,
enable ADD and HAD output, and
load lower address in ACL
*/
/* select device #
*/
/* address increment for byte
/* R5 * 64 -> block count

*/
*/

/************************************************************************/

/* start of outer transfer loop
*/
/************************************************************************/
xl: PLDLC H'3F'
;
/* push cnt to stack and load 64
in cnt
*/
/************************************************************************/
/* start inner transfer loop
*/
/************************************************************************/

y1 : JMPNC ready y1 ,
OUT b dm byte read
LOOPNZ yT
-;
ACL := ACL + Q ,
OUT b_dm_byte_write

/* wait till ready signal high

*/

/* strobe the write signal and
set up the next address
*/
/************************************************************************/
/* end inner loop
*/
/************************************************************************/
POPLC
ACH := ++ ACH ,
OUT b_dm_byte_read
/* pop stack to cnt , increment
upper address bits
*/
JMPC bgn release_bus
/* check if bus grant has been
taken away
*/
LOOPNZ xl
;
/* loop back if counter not zero*/
/************************************************************************/

/* end outer loop

*/

/************************************************************************/

done
release bus :
/************************************************************************/

4-60

WAFERSCALE INTEGRATION, INC.

PAC1000 - Application Note 005

Appendix 4 (CDnt.)
/************************************************************************/

/* device to memory word transfer in the fly-by mode. The start address */
/* of the memory is loaded in R3 and R4 and the device number is loaded*/
/* in Q . For simplicity it is assumed that the block size is a multiple*/
/* of 64 and R5*64 = block size.
*/
/************************************************************************/
segment b dm word ;
/* define equates */
bgn equ CC7
; /* bus grant (active low)
*/
ready equ CC4
; /* ready input
*/
b dm word norm equ h'OOde'
/* dma active w/o read/write */
*/
b-dm-word-read equ h'OOd6'
/* read (active low)
*/
b-dm-word-write equ h'OOc6';
/* write (active low)
init b-dm-word-:
*/
/* upper 16 bits address
-ACH
R3
SET ASEL ADOE HADOE
/* select counter to output ,
ACL := R4
enable ADD and HAD output, and
load lower address in ACL
*/
IOR := - Q ,
OUT b dm word norm
/* select device #
*/
Q := 2 /* address increment for word
*/
LDLCD , MOV R5 R5
;
/* R5 * 64 -> block size (words)*/
/************************************************************************/
/* start of outer transfer loop
*/
/************************************************************************/
xl: PLDLC H'lF'
/* push cnt to stack and load 32
in cnt
*/

:=

/************************************************************************/

/* start inner transfer loop
*/
/************************************************************************/
yl : JMPNC ready yl ,
*/
OUT b dm word read
/* wait till ready signal high
LOOPNZ yl
,
ACL := ACL + Q ,
/* strobe the write signal and
OUT b dm word write
set up the next address
*/
/************************************************************************/
/* end inner loop
*/
/************************************************************************/
POPLC
,
ACH := ++ ACH ,
/* pop stack to cnt , increment
OUT b dm word read
upper address bits
*/
JMPC bgn release_bus
/* check if bus grant has been
taken away
*/
LOOPNZ xl
;
/* loop back if counter not zero*/
/************************************************************************/

/* end outer loop
*/
/************************************************************************/
done
release bus :
/************************************************************************/

WAFERSCALE INTEGRATION, INC.

4-61

II

PAC100D - Application Note 005

Appendix 4 (Cont.)
/************************************************************************/

/* device to memory byte transfer in the fly-by mode. The start address */
/* of the memory is loaded in R3 and R4 and the device number is loaded*/
/* in Q . For simplicity it is assumed that the block size is a multiple*/
/* of 64. This code illustrates individual transfer mode (non-block mode)*/
/************************************************************************/
segment s dm byte ;
/* define equates */
bgn equ CC7
; /* bus grant (active low)
*/
ready equ CC4
; /* ready input
*/
*/
s dm byte norm equ h'OOde';
/* dma active w/o read/write
*/
s-dm-byte-read equ h'00d6';
/* read (active low)
s-dm-byte-write equ h'00c6';
/* write (active low)
*/
in it s-dm-byte-:
*/
/* upper 16 bits address
-ACH
R3
SET ASEL ADOE HADOE
/* select counter to output ,
ACL := R4
enable ADD and HAD output, and
load lower address in ACL
*/
/* load block size in to BC
*/
BC := RS
IOR .= - Q ,
*/
/* select device #
OUT s dm byte norm
*/
CMP Q-H'0001'
/* find out if device #0
JMPC Z devO
*/
/* i f device # 1
CMP Q H' 0002'
JMPC Z dev1
*/
/* i f device # 2
CMP Q H' 0004'
JMPC Z dev2
/* else i t is device # 3
/************************************************************************/
/* start transfer loop for dev#3
*/
/************************************************************************/
dev3
/* monitor bus grant
*/
;
JMPC bgn release bus
JMPNC CC3 dev3 OUT s_dm_byte_read
/* branch to check for dma request
*/
from device3
SET ACEN BCEN ,
/* start counter
*/
OUT s dm byte write
RESET-ACEN BCEN ,
*/
/* stop counter
OUT s dm byte norm
JMPNC-BCZ dev3
*/
/* loop back if not done
JMP done
;

:=

/************************************~***********************************/

/* start transfer loop for dev#2
*/
/************************************************************************/
dev2
*/
/* monitor bus grant
JMPC bgn release bus
JMPNC CC2 dev2 /* branch to check for dma request
OUT s_dm_byte_read
from device2
*/
SET ACEN BCEN ,
/* start counter
*/
OUT s_dm_byte_write

4·62

WAFERSCALE INTEGRATION, INC.

PAC1000 - ApplIcation Note 005

Appendlx4 (CDn'.)
RESET ACEN BCEN ,
OUT s dm byte norm
JMPNC-BCZ dev2
JMP done

1* stop counter
1* loop back if not done *1

*1

,
1************************************************************************1
1* start transfer loop for dev#l
*1
1************************************************************************1
devl
JMPC bgn release bus
JMPNC CCl devl OUT s_dm_byte_read
SET ACEN BCEN ,
OUT s dm byte write
RESET-ACEN BCEN ,
OUT s dm byte norm
JMPNC-BCZ devl
JMP done
;

*1

1* monitor bus grant

1* branch to check for dma request
from devicel
*1
*1

1* start counter

1* stop counter
1* loop back if not done

*1
*1

1************************************************************************1
1* start transfer loop for dev#O
*1
1************************************************************************1
devO
JMPC bgn release bus
JMPNC CC3 devO OUT s_dm_byte_read
SET ACEN BCEN ,
OUT s dm'byte write
RESET-ACEN BCEN ,
OUT s dm byte norm
JMPNC-BCZ devO

*1

1* monitor bus grant

1* branch to check for dma request
from device3
*1
1* start counter

*1

1* stop counter
1* loop back if not done

*1
*1

1************************************************************************1
done
release bus :

1************************************************************************1

WAFERSCALE INTEGRATION, INC.

4·63

II

PACtODO - Application Note 005

Appendix 4 (Cont.)
/************************************************************************/
/* code to illustrate device to memory transfer in non fly by mode.
*/
/* This is used when data bus is connected d7-dO to dlS-d8 or the
*/

/* other way around. Use counter to output addresses.Q contains device */
/* number and R3 R4 contain destination address.RS contains block size. */

/************************************************************************/
segment b dm sbyte i
/* define equates */
b dm sbyte norm equ h'00ge'
b-dm-sbyte-read equ h'0096'
b-dm-sbyte-write equ h'008e'
rdy equ CC4
bgn equ CC7
init b dm sbyte :
-BC :;;- RS ,
OUT b dm sbyte norm
SET DlREN ASEL-RADOE ADOE
ACH := R3
ACL := R4

i
i

*/
/* load block size in bcnt
counter to output,
enable had output
*/

i/* select

,

/************************************************************************/
/* start of transfer loop

*/

/************************************************************************/
b dm sbyte :
-JMPC bgn release bus
SET DIREN
srdy
JMPNC rdy srdy,
OUT b dm sbyte read
SET HDOE-HDSELO ,
AOR := DIR
DOR
OUT
SET
OUT

/* enable DIR
/* wait till source ready

*/

/* when src is ready read the data
in , enable HD output , select
DOR to output
*/

:= SWPV
,
b dm sbyte write
ACEN-BCEN -;
b_dm_sbyte_norm

RESET ACEN BCEN HDOE
JMPNC BCZ b dm sbyte

*/

/* put swapped data in DOR

*/

/* start counter , output swapped
data
*/
i

/************************************************************************/
/* end of transfer loop

*/

/************************************************************************/
done :
release bus :

/************************************************************************/

4·64

WAFERSCALE INTEGRATION, INC.

I'AC1000 - Application Note 005

Appendix 4 (Cont.)
/************************************************************************/
/* code to illustrate memory to memory transfer.Use counter to output
*/
/* both addresses.Rl,R2 contain source address and R3 R4 contain dest
*/
/* address . R5 contains block size.
*/
/************************************************************************/

segment b mm byte ;
/* define equates */
b rom byte norm equ h'00ge'
b-rom-byte-read equ h'0096' ;
b-mm-byte-write equ h'008e';
rdy equ CC4
bgn equ CC7
in it b rom byte :
-BC :-;;- R5 ,
OUT b mm byte norm
/* load block size in bcnt */
SET ASEL-HADOE ADOE
/* select counter to output ,
enable had output
*/
/************************************************************************/
/* start of transfer loop
*/
/************************************************************************/
b rom byte :
- -JMPC bgn release bus ,
ACH := Rl
/* monitor bus grant , source
address in R1
*/
SET DIREN , ACL := R2
/* enable dir, r2 <- low 6 bits */
srdy
JMPNC rdy srdy,
OUT b rom byte read
/* wait till source ready
*/
SET ACEN-HDOE-HDSELO ,
DOR := DIR
/* when src is ready read the data
in , enable HD output , select
DOR to output
*/
RESET ACEN DIREN ,R1 := ACH,
OUT b_rom_byte_norm
/* stop counter , store it back in
to registers
*/
ADD R2 ACL Q ARDREG ACH R3
/* mov ACL back to r1 and at the
same time load r3 to ach
*/
ACL := R4
/* ach,acl have dest address
*/
drdy
JMPNC rdy drdy
/* wait for destination ready
*/
SET ACEN BCEN ,
OUT b_rom_byte_write
/* when dest is ready , write the
data, increment counter , also
enable block counter
*/
RESET ACEN BCEN HDOE ,
R3 := ACH ,
OUT b_rom_byte_norm
/* stop counters , set HD to input
save dest address (upper 16) */
JMPNC BCZ b_rom_byte ,
R4 := ACL
/* loop back if block counter not
zero , also save lower 6 bits
of dest address
*/
/************************************************************************/
/* end of transfer loop
*/

/************************************************************************/
done :
release bus :
/************************************************************************/
WAFERSCALE INTEGRATION, INC.

4·65

PAC1000 - Application Note 005

Appendix 4 (Cont.)
/************************************************************************/

1* code to illustrate memory to memory transfer (word mode) .Use counter *1
1* to output both addresses.Rl,R2 contain source address and R3 R4
*1
1* contain destination address. R5 contains block size in words.
*1
/************************************************************************/

segment b mm word ;
1* define equates *1
b mm word norm equ h'00ge'
b-mm-word-read equ h'0096'
b-mm-word-write equ h'008e';
rdy equ CC4
bgn equ CC7
in it b rom word :
-BC :-;; R5 ,
OUT b mm word norm
SET ASEL-HAOOE ADOE

1* load block size in bcnt *1
1* select counter to output ,
enable had output
*1

1************************************************************************1

1* start of transfer loop

*1

/************************************************************************/

b mm word :
-JMPC bgn release bus ,
ACH := R1
srdy

SET OIREN , ACL := R2
JMPNC rdy srdy
OUT b mm word read
SET ACEN-HOOE-HOSELO ,
OOR := OIR

1* monitor bus grant , source
address in R1
*1
1* enable dir,ACL <- low 6 bits *1
1* wait till source ready

*1

1* when src is ready read the data
in , enable HO output , select
OOR to output
*1

OUT b rom word norm
RESET-ACEN OIREN ,
ADD R1 ACH Q ARDREG ACH R3
ADD R2 ACL Q AROREG ACL R4
drdy

JMPNC rdy drdy
SET ACEN BCEN ,
OUT b mm word write
RESET BCEN HOOE ,
OUT b rom word norm
RESET ACEN

R3 := ACH

JMPNC BCZ b mm word ,
R4 := ACL

1* stop counter , store ACH in to
R1 and also load ACH with R3 *1
1* store ACL in R2 and at the same
time put R4 in to ACL
*1
1* wait for destination ready
*1
1* when dest is ready , write the
data, increment counter , also
enable block counter
*1
1* stop block counter, set HO to
input
*1
1* stop add counter ,
save dest address (upper 16) *1
1* loop back if block counter not
zero , also save lower 6 bits
of dest address
*1

1************************************************************************1
1* end of transfer loop
*1
/************************************************************************/

done :
release bus :
/************************************************************************/
4·66

WAFERSCALE INTEGRATION, INC.

PAC1000 - Application Note 005

Appendix 4 (Cont.)
/************************************************************************/

1*
1*
1*
1*
1*

code to illustrate memory to memory transfer from D7-DO to D15-D8
or vice-versa. Use counter to output both addresses .Rl , R2 contain
source address and R3 R4 contain destination address.R5 contains
block size. Data is read in to AOR and byte-swpped before outputting
through DOR.

*1
*1
*1
*1
*1

/************************************************************************/

segment b mm sbyte ;
1* define equates *1
b mm sbyte norm equ h'00ge'
b-mm-sbyte-read equ h'0096'
b-mm-sbyte-write equ h'008e';
rdy equ CC4
bgn equ CC7
in it b mm sbyte :
-BC :~ R5,OUT b mm sbyte_norm;
SET ASEL HADOE-ADOE

1* load block size in bcnt *1
1* select counter to output ,
*1

enable had output

/***************************************************** *******************1

1* start of transfer loop

*1

/************************************************************************/

b mm sbyte :
-JMPC bgn release bus ,
ACH := R1
srdy

SET DIREN , ACL := R2
JMPNC rdy srdy
OUT b mm sbyte read
SET ACEN-HDOE HDSELO ,
AOR := DIR

1* monitor bus grant , source
address in R1
*1
1* enable dir, r2 <- low 6 bits *1
1* wait till source ready

*1

1* when src is ready read the data
in , enable HD output , select
DOR to output
*1

RESET ACEN DIREN,R1 := ACH
OUT b_mm_sbyte_norm

1* stop counter , store it back in
to registers
*1
ADD R2 ACL Q ARDREG ACH R3
1* mov ACL back to r1 and at the
same time load r3 to ach
*1
ACL := R4
1* ach,acl have dest address
*1
drdy
JMPNC rdy drdy,DOR := SWPV ; 1* wait for destination ready
and write swapped value
*1
SET ACEN BCEN ,
OUT b_mm_sbyte_write
1* when dest is ready , write the
data, increment counter , also
enable block counter
*1
RESET ACEN BCEN HDOE ,
R3 := ACH ,
OUT b_mm_sbyte_norm
1* stop counters , set HD to input
save dest address (upper 16) *1
JMPNC BCZ b_mm_sbyte ,
R4 := ACL
1* loop back if block counter not
zero , also save lower 6 bits
of dest address
*1
/************************************************************************/

1* end of transfer loop
*1
1************************************************************************1
done :
release bus :

1************************************************************************1
WAFERSCALE INTEGRATION, INC.

4·67

PACtOOO - Application Note 005

Appendix 4 (Cont.)
/************************************************************************/
/* code to illustrate device to device transfers in the byte as well as */
/* word mode.
source device is in rl and dest device is in r3. block
*/
/* size is in rS.
*/

/************************************************************************/
segment b dd bw ;
/* define equates */
b dd bw norm equ h'00ge'
b-dd-bw-read equ h'0096'
b-dd-bw-write equ h'008e'
rdy equ-CC4
bgn equ CC7
init b dd bw :
-SET DlREN , lOR := - Rl
OUT b dd bw norm

/* enable DlR and output source
device chip select
*/

/************************************************************************/
/* start of transfer loop

*/

/************************************************************************/
b dd byte
b-dd-word
b-dd-bw :
JMPC bgn release bus ,
lOR .= - R3,
OUT b dd bw read
SET HDOE HDSELO ,
DaR := DlR ,
OUT b dd bw norm
RESET HDOE ,
DEC RS ,
OUT b dd bw write

/* read source device and output
dest device chip select , also
monitor bus grant
*/

/* enable HD output , select DaR
to output
*/

/* HD to input , decrement count
output write strobe
*/

JMPNC Z b_dd_bw ,
lOR := - Rl ,
OUT b_dd_bw_norm

/* loop back if RS not zero , also
output src device cs
*/

/************************************************************************/
/* end of transfer loop

*/

/************************************************************************/
done
release bus :

/************************************************************************/

4·68

WAFERSCALE INTEGRATION, INC.

PAC1000 - Application Note 005

Appendix 4 (Cont.)
/************************************************************************/

/* code to illustrate device to device transfer in non fly by mode
/* This is used when data bus is connected d7-dO to d15-d8 or the
/* other way around. Source device # is in Rl and dest device # in R3

*/
*/
*/

/************************************************************************/

segment b dd sbyte :
/* define equates */
b dd sbyte norm equ h'00ge'
b-dd-sbyte-read equ h'0096'
b-dd-sbyte-write equ h'008e';
rdY equ CC4
bgn equ CC7
init b dd sbyte :
-SET DlREN , lOR .= - Rl ,
OUT b_dd_sbyte_norm
; /* enable DlR and output source
device chip select
*/
/************************************************************************/

/* start of transfer loop

*/

/************************************************************************/

b dd sbyte :
-JMPC bgn release bus ,
lOR .= - R3 ,
OUT b dd_sbyte_read
AOR := DlR
SET HDOE HDSELO ,
DaR := SWPV ,
OUT b_dd_sbyte_write
RESET HDOE ,
DEC R5 ,
OUT b_dd_sbyte_norm
JMPNC Z b dd sbyte ,
lOR := - Rl -

/* read source device and output
dest device chip select , also
monitor bus grant
*/
/* read in the data
*/
/* enable HD output , select DaR
to output , put swapped data in
DaR
*/

/* HD to input , decrement count
output write strobe
*/
/* loop back if R5 not zero , also
output src device cs
*/

/************************************************************************/

/* end of transfer loop

*/

/************************************************************************/

done
release bus :
/************************************************************************/

WAFERSCALE INTEGRATION, INC.

4·69

4·70

WAFERSCALE INTEGRATION, INC.

Programmable System™Device
Application Brief 006
WAFERSCALE INTEGRATION, INC.

PAC1000 as a 16 Bi·Directional
Serial Channel Controller
By Alye Zik/ik

Introduction

This Application Brief describes a
Communications Controller that utilizes the
PAC1000 as the board level control element
in a 16 bi-directional serial channel board.
The aggregate board throughput is around
Serialization and de-serialization of the
data is handled by eight Serial
Communication Controllers (SCC). Every

SCC has two bi-directional serial channels
with individual baud rate generator and
digital phase loop mechanism. The SCC
can handle all the customary synchronous
and asynchronous protocols as well as the
popular serial data encoding/decoding
schemes. With a 16-MHz clock, the
maximum bit rate in every individual
channel can be up to 2 Mbps.

PAC1000 Host Interface

The PAC1000 performs the low level
function of moving the data to and from
the serial devices and buffer RAM memory.
The host interface is a generic 32-bit
system. The host processor communicates
with the PAC1000 through two interrupt
lines, two status signals and a mail-box
area that resides in the buffer memory.
Prior to accessing the board, the host
drives the "system board access" signal.
The PAC1000 is interrupted (INT3) and
relinquishes control of the board's data
and address buses as long as that signal
is active (as reflected by CCO). The host

reads and/or writes into the buffer memory.
After completion of this activity, it updates
the mail-box region and then lowers the
"system board access" signal. The PAC1000
continuously monitors that signal. After
CCO is negated, the PAC1000 can raise its
"PAC1000-board master" signal and start
controlling the data/address buses and
control signals. Whenever it needs a fast
response from the host, the PAC1000
updates the mail-box portion of the shared
buffer memory, lowers the "PAC1000-board
master" signal and activates the system
interrupt.

Buffer Memory
Structure

The high speed buffer memory is composed
of 64K bytes of static RAM that can be
accessed in three ways: by bytes (during
SCC transfer operations), by words (when
accessed by the PAC1000), or by double
words (from the host side). Memory access
configuration is determined by the PAC1000
output control signals (OC port).

Whenever instructed to do so, the PAC1000
writes the image register content of a
channel into the corresponding SCC,
thereby initializing that channel for a
particular transfer mode. Buffer message
sizes are allocated by the host according
to the speed of each individual channel.
The pointers of the buffers are stored in
the mail-box area.

1 Mbyte/sec.

The buffer memory is divided into three
regions:
1) SCC control image register space that
includes copies of the SCC registers.
2) Buffer message space where the 32
buffers of the corresponding serial
channels are stored.
3) Mail-box area in which the PAC1000
exchanges command and status
information with the host. This region
also contains the pointers to the 32
channel buffers.

Every transfer takes place between the
buffer memory and the selected SCC. The
PAC1000 is acting in this design as a
32-channel DMA controller, capable also of
communicating with the host processor
through their mail-box region. Once the
board is properly configured, the only
interface of the host system is the reading
of data from the receive and mail-box
buffers and the placing of new data into
the transmit and mail-box buffers. The
PAC1000 off-loads the host processor from
maintaining the low level control of each
channel.

WAFERSCALE INTEGRATION, INC.

4-71

PAC1000 - ApplicatiDn Brief 006

PACtOOOSCC Devices
Interface

The high speed data transfers are achieved
due to the very fast response of the
PAC1000 to the channel service requests.
The SCCs are programmed to request
DMA transfers whenever they are either
ready to transmit or containing new
received characters.
The 16 received character DMA requests
are priority encoded and latched. The
encoder output is connected to the
PAC1000's CC3 pin. The 16 transmit DMA
requests are priority encoded and latched,
too. Their encoder drives the CC2 input
pin. The condition code multiplexer presents
to the CC7-CC4 the highest priority
encoded-channel-number of the pending
receiver request, or the transmitter request,
or the highest priority SCC number that is
currently requesting an interrupt service
via the CC1 pin. The receiver requests
have higher priority over the transmitter
requests. The lowest service priority is
assigned to the SCC interrupts. This
configuration ensures a very fast response

Miscellaneous

In addition to functioning as an SCC
controller, the PAC1000 can also generate
all the necessary signals for modem control
and modem interface through the SCC
control signal latch.
The PAC1000 output control (OC) port
generates various control strobes such as
data path width definition, readlwrite,
multiplexer and decoder select, etc.

4·72

WAFERSCALE INTEGRATION, INC.

time of the PAC1000 to DMA requests and
SCC interrupts. Condition code latency is
125 ns and mUlti-way branching according
to the CC7-CC4 lines requires additional
125 ns. Therefore, 250 ns after a high
priority DMA request, the service routine
will be initiated. The condition code lines
CC3, CC2 and CC1 are continuously
monitored by the PAC1000 during the time
that it is the board master. Therefore it
responds immediately when either a DMA
request or an SCC interrupt is pending.
The regular SCC interrupt lines are also
prioritized and latched by an 8 interrupt
encoder. These interrupts are requested by
erroneous SCC channels or whenever block
transfers are completed. The interrupt
priority encoder is also connected to the
condition code multiplexer. The three
encoded lines that denote the number of
the serviced SCC route the INTA signal
issued by the PAC1000 (via the 1/06 pin)
to the corresponding SCC.

PAC1000 - Application Brief 006

PAC1000 as a
16 Hi·Directional
Serial Channel
Controller
\

,

SYSTEM
32-BIT DATA BUS

SYSTEM DATA
TRANSCEIVER

\

\

HIGH ORDER
DATA BUS

,

SYSTEM LOW ORDER
SYSTEM
16 ADDRESS LINES INTERRUPT

~ DECODER
MEMORY ~

BUFFER
MEMORY
64K x 8
(CONFIG.
ALSO BY
16 OR BY
32 BITS)

\ SYSTEM ADDR.
LATCH

BRD-

-.I

16-BIT
ADDRESS BUS

SYSTEM
BOARD
ACCESS

~

BWR
16-BIT DATA BUS

~

ADD(lS-0)

SYSTEM SCC
DECODEICONTR OL
LINES

t

I

PACl000
BOARD
MASTER

TT

HIGH-OR DER
ADD'l'NES

BWI'i_ SYSTEM BOARD
DECODER

~

LOW ORDER
DATA BUS

SYSTEM

OCl

OCO

INT3

1/07

CCO

HIGH
SPEED
CONTR OL
STROB ES
(DATA
PATH
WIDTH,
SCC RE AD,
SCCW RITE,
ETC... .)

1/06

CCl

OC(lS-0)

PAC1000
CC2

,..

CC7-CC4
HADl

CC3 1/0(5-0)

!
\ CONDITION CODE \
MULTIPLEXER

HAD(S-2) HADO HD(lS-0)

'AlB

SCC CONTROL 1\
SIGNALS DECODER
SCC
\
DECODER

!

~C/O

SCC CONTROL
SIGNALS LATCH

!' ,'!' ,'!

\

~ J"~ ~
CS#l CS#2

4 ENCODED
LINES

Y

PRIO:~~Y L~~g~DER

4 ENCODED
LINES
\ TRANSMIT 16 DMA REO.
PRIORITY ENCODER
AND LATCH

I

,
,
,
,
,
,

, .. t

SCCs
81NTR
ENCODER

3 ENCODED
LINES

s:1INTA

I

RECEIVER 16 DMA REO.

INTR.
ACK
MUX

'--

,
,
,
,
,

CS#7 CS#8

8-BIT DATA BUS

FORCED DTRS INTR
ENABLE
SYNCS
AND
CLR

-

DATA
TRANSCEIVER

1_

t

CS#l

C/O

DB(7-0)

AlB

rr-

RDY1A
RDY1B

SCC #1

DTR1A
DTR1B

,

,
,
,
,

,....

INTR#l
INTA#l
T01A

RD1A

T01B

RD1B

it:' II:' jl·: )111:'

,

t

16 TRANSMIT I 16 RECEIVE SERIAL CHANNELS

WAFERSCALE INTEGRATION, INC.

4-73

4·74

WAFERSCALE INTEGRATION, INC.

Programmable System™Device
WAFERSCALE INTEGRATION, INC.

Application Note 008

PAC1000 User·Configurable Microcontroller
with a Built·ln·Self·Test Capability
By David Fong

Abstract

The objective of this Application Note is to
demonstrate the Built-In-Self-Test (BIST)
capability of the PAC1000 High-Performance

User-Configurable Microcontroller. This
article describes the basic instructions
needed to implement BIST.

Introduction

With increasing device densities on one
chip, more devices are needed for BIST to
check the functionality of the internal logic.
Current serial scan techniques for board
level verification would take too much time
and resources. The current PAC1000 will

only test the ALU and its status flags, the
address and block counter, and the
sequencer. Future versions in the WS-PAC
Family will have even larger sizes of
EPROM and may test the control EPROM.

Usage and
Limitations

The program is accessible by calling the
BIST program. The program occupies
forty-five lines of EPROM code. The
program can be reduced in size by
specifying extra CPU registers to hold the
constants h'FFFF', h'OOOO', h'AAAA', h'5555'
and h'FFF4'.

This BIST is not a panacea for system
designers. A 'PASS' condition is indicated
by a return to the main calling program.
The output control will be h'OOOO'. A 'FAIL:
condition will result in some endless loop
or jump to some portion of the program. In
the event that it does fail after about 170
clock cycles, the system must disable the
PAC1000 from the rest of the system in
some manner. Future versions of the
PAC1000 may include a watchdog timer to
interrupt and timeout the SIST.

Certain conditions must be met prior to
programming the code to ensure that this
program will work correctly. The stack
should be empty because the program
exercises the stack. In addition, location
h'3FF' must be reserved because the BIST
uses this location to verify the contents of
the stack as a '1.' The outputs should be
placed in a mode where the existing
system is not affected. The 'MAINT'
instruction will ensure that the OC is the
same throughout the program. However,
this example was not implemented in that
manner. Instead, it uses set values to
assist in debugging the program. Users
can do a global substitution of "OUT
h'xxxx' " with "MAl NT" in their word
processor to fully implement this SIST
program.

The variables that can be altered by the
user are listed at the beginning of the
BIST.mal file. The current values used will
only exercise the counters in a simple
manner. The user can modify these
variables to increase the confidence level
of the program at the expense of a longer
test cycle.

WAFERSCALE INTEGRATION, INC.

4·75

1'AC1000 - Application Note 008

Usage and
Limitations
(Cont.)

A summary of the instructions used and
the functional blocks follow below:

1*********************************************************************/
/*
/*
/*
/*
/*
/*
/*

registers destroyed : RO,Rl,R2,R3 and R4
AOR,ACH,ACL,BC,LC and stack

stack should be empty before calling this program
the block counter, address counter, ALU with register file and
flags, and the sequencer with stack and counter are tested

*/
*/
*/
*/
*/
*/
*/

/ * * /

/*
/*
/*
/*
/*
/*
/*

flags checked: BCZ,ACO,CY,Z,O,S,and STKF
ALU instructions used: ADC,AND,ADD,MOV,NOP,SHRR,SHRL,SUB
CONTROL instructions used: ACSIZE,CONT,JMPNC,JMPC,LDLCD,
LOOPNZ,PLDLC,POP,RET,RNC,RSTCON and SETCON

DATA from EPROM used: 0000, FFFF, FFF4, AAAA, 5555 ,0008 , 0010,
03FF, 0019

*/
*/
*/
*/
*/
*/
*/

/*********************************************************************/

Confidence
Level

The program executes some of the possible
internal critical paths of the PAC1000.
From tester and simulation measurements,
the test of condition codes and branching
were consistently the longest. Similarly for
the ALU, flag generation such as adding

with a carryout is considered a critical
path. The counters have a critical path in
propagating the carry. Overall, the
confidence level of this test is considered
to be high.

AnalysIs of the
Program

The currently executing program calls the
BIST program by using the 'CALL:
instruction. The instruction following 'CALL:
which is the return address is pushed to
the stack and is not destroyed by the BIST
program. See Figure 1 for the BIST
flowchart. The BIST tests the PAC1000
functional blocks in the following order:

are set and reset by instructions. The ALU
result of each cycle updates each flag on
the next rising edge of the clock. For
example, to check the zero flag (Z), some
ALU instruction forces the Z flag to zero.
See the instructions below:

1. Block Counter and flag BCZ.

zero:

2. Address Counter and flag ACO.
3. ALU with shifter and flags CY, Z, 0
and S.
4. Sequencer with stack and loop counter,
and flag STKF.
Some subtleties of programming the
PAC1000 are presented. In the ALU section,
certain flags must be forced to zero before
being tested upon, unlike the normal
microprocessors where the individual flags

Analysis of the
Simulation
Output

4·76

Looking at the block counter outputs
BC(15:0) from cycle 7 through 18, the
counter counts continuously until disabled.
The block counter contents wraps around
from h'OOOO' to h'ffff' and down. Note that
the BCZ flag remains latched until new
data is loaded to the block counter.

WAFERSCALE INTEGRATION, INC.

MOV R2 R2 , OUT h'0138' ;

1* force zero flag Z=O *1
JMPNC Z zero, AND AOR R1 ,
OUT h'0139' ;

Next, loading the loop counter from the
ALU needs special treatment. The data
must be present at the ALU output before
the instruction to load the loop counter
executes. See the instructions below:
MOV R4 short, OUT h'014B' ;
1* force ALU output to the
value of short = h'0010' * 1
LDLCD , MOV R4 R4, OUT h'014C' ;
1* load 0010 to LC *1

Because of the latched flag BCZ, there is
a minimum of two cycles before the next
instruction is executed after the loop.
Figure 2 shows the loop with the minimum
number of latency cycles before executing
the next line of program code.

PAC1000 - Application Note 008

Figure 1.
Builf·ln·Self·Test
Flowchart

NO

NO

NO

NO

NO

POP STACK
AND RETURN
TO MAIN
PROGRAM

NO

WAFERSCALE INTEGRATION, INC.

4·77

PAC1000 - Application Note 008

Figure 2.
BCI Flag:
Example
Cycle·by·Cycle
Simulation

CYCLE

BC

BCZ

CONTROL
INSTRUCTION

2

1.
2.
3.
4.
5.

3

4

5

100p1: MOV R2 h'SSSS', OUT h'012S' ;
JMPNC BCZ 100p1, OUT h'0129' ;
RESET BCEN, OUT h'012a' ;
ACSIZE 22, OUT h'012b' ;
MOV ACL long, OUT h'012c' ;

/********************************************/
/* Main calling program
/* David Fong
/* main.mal

02/03/89
Rev. 1.0

*/
*/
*/

/********************************************/
segment main ;
external bist ;
main1:

/* initialize */
/* not needed */
/* call bist program */

FORE:

CALL bist , OUT h'0123';
/* call the BrST program */
/* return to main program */
JMP FORE , OUT h'OOOO' ; /* loop forever */

end ;

/*********************************************/

/* Program to jump back to main bist program */
/* David A. Fong 02/03/89
Rev. 1.0
*/
/* jmpf.mal
*/

/*********************************************/
segment jmp ;
external jmpf ;
JMP jmpf , OUT h'FFFF' ; /* jmpf is an external address */
/* this tests branching with all l's */
end ;
4-78

WAFERSCALE INTEGRATION, INC.

PACtOOO - Application Note 008

/*****************************************************************/
/* Built-In-Self-Test Program 02/03/89
*/'
/* David A. Fang
Rev. 1.0
*/
/* bist.mal
*/
/*****************************************************************/
/* registers destroyed : RO,R1,R2,R3 and R4
*/
/*
AOR,ACH,ACL,BC,LC and stack
*/
/*
*/
/* stack should be empty before calling this program
*/
/*
*/
/* the block counter, address counter, ALU with register file and*/
/* flags, and the sequencer with stack and counter are tested
*/
/*
*/
/* flags checked: BCZ,ACO,CY,Z,O,S,and STKF
*/
/* ALU instructions used: ADC,AND,ADD,MOV,NOP,SHRR,SHRL,SUB
*/
/* CONTROL instructions used: ACSIZE,CONT,JMPNC,JMPC,LDLCD,
*/
/*
LOOPNZ,PLDLC,POP,RET,RNC,RSTCON and SETCON
*/
/*
*/
/*DATA from EPROM used: 0000, FFFF, FFF4, AAAA, 5555 ,0008 , 0010*/
/*
03FF, 0019
*/
/*****************************************************************/
segment c bist ;
entry bist,jmpf ;

/* entry points into this program */

/* define equates for user to substitute */
shorter equ h'0008' ;
short
equ h'0010'
medium
equ h'03ff'
long
equ h'fff4'
popper
equ h'0019'
/****************************/
/* test the counters and
*/
/* initialize the registers */
/****************************/
bist:

MOV R1 h'OOOO', OUT h'0124'; /*the outputs should be placed*/
/* in a non-functional mode */
MOV RO h'FFFF' , OUT h'0125' ; /* in this program it is not*/
MOV BC shorter , OUT h'0126' ;/*because it was needed to*/
SETCON h'002' , OUT h'0127' ; /*debug enable block counter */
loop1:
MOV R2 h'5555' , OUT h'0128' ;
JMPNC BCZ loop1 , OUT h'0129' ;
RSTCON h'002' , OUT h'012A' ; /* disable block counter */
/* RO = FFFF ; R1 = 0000 ; R2 = 5555 */
/* test the 22-bit address counter */
ACSIZE 22 , MOV ACH RO , OUT h'012B' ;
MOV ACL long , OUT h'012C' ;
SETCON h'OOl' , OUT h'012D' ; /* enable address counter */

WAFERSCALE INTEGRATION, INC,

4-79

PAC1000 - Application Note 008

100p2:

MOV R3 h'AAAA' , OUT h'012E' ;
JMPNC ACO 100p2 , OUT h'012F'
RSTCON h'OOl' , OUT h'0130' ; /* disable address counter */

/* RO = FFFF ; Rl = 0000 ; R2 = 5555 ; R3 = AAAA */
/* test the 16-bit address counter */
ACSIZE 16 , OUT h'0131' ;
MOV ACH long, OUT h'0132' ;
SETCON h'OOl' , OUT h'0133' ; /* enable address counter */
100p3:
MOV R4 h'OOOO' , OUT h'0134' ;
JMPNC ACO 100p3 , OUT h'0135' ;
RSTCON h'OOl' , MOV R3 R3 , OUT h'0136'
/* disable address counter */
/* and do a dummy ALU instruction so that z=o and CY=O */
/* note: a Nap instruction will force Z=l and CY=l on the */
/* following cycle*/
/* RO = FFFF ; Rl = 0000 ; R2 = 5555
/* R4 is the working register */

R3

AAAA

R4

0000 */

/****************/
/* test the ALU */
/****************/
carry:

JMPNC CY carry, ADC AOR RO , OUT h'0137' ;/*test carryout */

zero:

MOV R2 R2 , OUT h'0138';
/* force zero flag = 0 */
JMPNC Z zero, AND AOR Rl , OUT h'0139' ;/*test all the alu*/
/* outputs are zero */

over:

SUB AOR R3 R2 , OUT h'013A' ; /* test for overflow */
JMPNC a over, OUT h'013B' ; /* test for overflow */

f15:

JMPNC S f15 , ADD AOR Rl RO , OUT h'013C' ;/*test sign bit*/

/* test the alu shifting */
shftl:

SHLR R2 Z , OUT h'013D'
AND AOR R3 R2 , OUT h'013E'

/*should not loop*/
/*but fall-thru */

JMPC Z shftl , OUT h'013F' ;
shftr:

SHRR R2
AND AOR
/*
JMPNC Z

Z , OUT h'0140' ;
R3 R2 , OUT h'0141'
should not loop,but fall-thru */
shftr , OUT h'0142'

/**********************/
/* test the sequencer */
/**********************/
MOV BC short, OUT h'0143'

4·80

WAFERSCALE INTEGRATION, INC.

PAC1000 - Application Note 008

SETCON h'002' , OUT h'0144' ~ /* enable block counter */
PLDLC medium , OUT h'0145' ~
JMPNC STKF stack, OUT h'0146'~
/*exit loop when stack is full */
/* the return address will not be */
/* overwritten , only the top of stack*/
MOV BC popper , OUT h'0147' ~
RNC BCZ , OUT h'0148' ~
/*should come out of loop when empty+1*/
/* which is the return address */
POP , NOP , OUT h'0149' ~
/* pop one more time but don't pop */
/* the last return address */
RSTCON h'002' , OUT h'014A' ~ /* disable block counter */

stack:

jmpf:

/* test the loop counter */
MOV R4 short , OUT h'014B'
LDLCD , MOV R4 R4 , OUT h'014C' ~/* load 16 into the LC*/
ADC AOR R4 , OUT h'014D' ~
/* aor = aor + r4 */
LOOPNZ lp , OUT h'014E'~/*check that loop count is not zero*/

lp:

RET , OUT h'014F'

~

/* return to calling program */

end

/**********************************/
/* bist linker file
02/03/89
*/
/* David Fong
Rev. 1.0
*/
/* exbist.ml
*/
/**********************************/
place main , c_bist , jmp
load main , bist , jmpf
locate main , h'OOO' ~
locate c bist , h'Oll'
locate jmp , h'3ff' ~
end

~

/* place the segments */
/* load the .mal files */

/* locate main and in it file */
/* locate bist file after interrupt */
/* locate jmp at 3ff to test '1' from stack */

~

.T
RCCCCCCCCIIIIIIIIIIIICWRHHHHHHHHHHHHHHHHHHHHH~

ECCCCCCCCOOOOOOOONNNNSRDDDDDDDDDDDDDDDDDAAAAAADDDDDDDDDDDDDDOD
S7654321076543210T~TTBBB1111119876543210DDDDDDDDDDDDDD00000000

E
T

3210

543210

5432101111119876543210
543210

B

TIME
1

2

00000000000000000000011100000000000000000000000000000000000000
10000000000000000000011100000000000000000000000000000000000000

WAFERSCALE INTEGRATION, INC.

4-81

I'ACtOOO - Application Note 0118

*******************************************************************
OUTPUT
PAC S I M

TAB L E
Mon Feb 13 15:12:09 198

Ver. 1. 09

******************************************************************

TIME
1
2
3
4
5
6
7
8
9
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23
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26
27
28
29
30
31
32
33
34
35
36
37

U2

PPP
CCC
173
1· •
:40
8

0000
CCCC
1173
51: :
: : 40
18
2

LLL
CCC
173
1· •
:40
8

AAAA
0000
RRRR
1173
51: :
: : 40
18
2

BBBB
CCCC
1173
51::
::40
18
2

AAAA
CCCC
HHHH
1173
51::
: : 40
18
2

AA BASCOSZ RRRR RRRR
3333 2222
CC CCTY
LL ZOK
1173 1173
53
F
51:: 51: :
40
: : 40 : : 40
18
18
2
2

000
000
011
012
013
014
015
016
015
016
015
016
015
016
015
016
017
018
019
01a
01b
Ole
01b
Ole
01b
Ole
01b
Ole
01b
Ole
01b
Ole
Old
Ole
Olf
020
021

0000
0000
0123
0124
0125
0126
0127
0128
0129
0128
0129
0128
0129
0128
0129
0128
0129
012a
012b
012e
012d
012e
012f
012e
012f
012e
012f
012e
012f
012e
012f
012e
012f
0130
0131
0132
0133

000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0008
0007
0006
0005
0004
0003
0002
0001
0000
ffff
fffe
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd
fffd

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
0000
0000
0000
fff4

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
34
35
36
37
38
39
3a
3b
3e
3d
3e
3f
00
01
01
01
01

..

WAFERSCALE INTEGRATION, INC.

... .

0010000
1010000
1000001
1001001
1000001
1000010
0000000
0001001
0000000
0001001
0000000
0001001
0000000
0001001
0000000
1001001
1000000
1001001
1001001
1000010
1000010
1001001
1000010
1001001
1000010
1001001
1000010
1001001
1000010
1001001
1000010
1001001
1100010
1101001
1101001
1101001
1000010

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa
aaaa

0000
0000
0000
0000
0000
0000
0000
0000
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555
5555

RRRR RRRR
1111 0000
1173
51: :
: : 40
18
2

1173
51: :
: : 40
18
2

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
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ffff
ffff
ffff
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ffff
ffff
ffff
ffff
ffff
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ffff
ffff
ffff

Programmable System™Device
Application Note 009
WAFERSCALE INTEGRATION, INC.

In-Circuit Debugging for the PAC1000
User-Configurable Microcontrol/er
By David Fong

Abstract

This Application Note is used to illustrate
the in-circuit debugging capabilities of the

PAC1000 user-configurable microcontroller.

Introduction

With the increasing densities and
complexities of integrated circuits, the
usage of tools such as in-circuit debuggers
and emulators is greatly desired by the
heroic hardware designer. The PAC1000
supports the usage of in-circuit debuggers.

the user to use in his monitor program. SS
is useful for checking that every cycle is
executing correctly.

A review of BP (breakpoint) and SS (single
step) is discussed. SS is the method of
stepping through the program code one
instruction at a time through manual means.
In the case of the PAC 1000, there is no
manual means with a single-step switch.
Instead, an interrupt which is set internally
through the program is set. This interrupt
can then call upon an ISR (interrupt service
routine). This subroutine then dumps out
the contents of all the possible registers
that can be read out. These registers must
then be written into the system memory by

Usage and
Limitations

Either SS or BP interrupts can occur.
Because both use the same initial ISR, the
ISR will differentiate between the two by
testing for a specific data pattern that
accompanies the breakpoint/single-step
data through the FIFO. One way was to
test for a specific external condition code
but that was determined to be inflexible
since a specific condition code needed to
be dedicated for this task. Instead, two
words are written into the CPU registers.
These two registers must be reserved for
breakpoint/single-step operation. In this
example, RO and R1 are reserved.
Register R1 is the mask that is 'AND'd
with RO which is written from the FIFO to
produce the Z (zero) flag that is tested.
See Figure 1 for the data format that is
written into the FIFO and CPU register RO.
The BP state continues with its program
by reading out the contents of some
registers to the host interface bus. Note
the usage of the FIFO to read out the
contents of the register to the ADD bus.
BP reads out only the input and output
registers that can be read as source to the

On the other hand, BP is the method of
interrupting the program at a specific
program location. This allows the program
in the PAC1000 to run in real-time system
conditions. This breakpoint is passed to
the PAC1000 through the FIFO instead of
having a fixed address through the program.
BP is useful for intermittently checking the
execution of the program.
There is no preference on which method is
the best. Generally, it is determined by the
situation. If the system designer doesn't
trust their own system in the beginning of
debug, then they will use SS. After the
system becomes more debugged,
breakpoint is needed occasionally.
HD bus. Whereas, SS reads out the CPU
registers as well as the input and output
registers to ADD.
Not all the registers can be read out or if
at all with difficulty. CPU registers as was
illustrated by this program was read out
using the FIFO. However, the user could
have individually read out each register.
Unfortunately, there would have been a lot
of overhead program space taken. The
stack cannot be read out because the
contents of the stack would affect the
program flow. The interrupt mask register
and interrupt pending register cannot be
read out or to the CPU. Future PAC1000
versions may support extra functions to
allow the user to more easily access the
internal registers.
In summary, the single-step program dumps
out the following registers to the ADD bus:
CPU registers R31-RO, DIR, AIR, ACH,
ACL, IIR, and BC. Whereas, the breakpoint
program dumps out the tollowing registers
to the HD bus: DIR, AIR, AOR, ACH, ACL,
IIR, and BC.

WAFERSCALE INTEGRATION, INC.

4·83

PAC1000 - Application Note 009

Analysis of
Program

This single program incorporates essentially
two programs. One for breakpoint and one
for single-step. To differentiate between the
two programs since they use the same
interrupt INT6, the data in register RO is
tested upon and the corresponding action
is taken. If Z is true, then breakpoint will
occur, else single-step will occur. See
BREAKPOINT/SINGLE-STEP algorithm
Figure 2.
Note that the Interrupt Jump Table is
located at h'OOS' through h'OQf'. The
PAC1000 interrupt vector from the internal
interrupt jumps to these individual
locations. In addition, note that neither
conditional nor unconditional jumps were

allowed to be executed when either the
breakpoint or the single-step interrupts
occurred. This also applies to other
interrupts. The delay interval from the time
of interrupt to executing the interrupt is
two cycles. See Figure 3 for the timing
relationship of interrupt to the beginning
of execution of the interrupt service
routine (ISR).
The single-step subroutine utilizes the
FIFO to externally address the CPU dualport registers. The usage of the FIFO in
conjunction with loops reduces the size of
the control store. However, the contents of
the FIFO must be empty before using it.

Figure t. Host
to PACtOOO
Commands
(Via the FIFO)

-t+------ HD[15:0) -------~

LEGEND:
U:
User-Defined
X:
Test Bit
AlU: Breakpoint Address or User-Defined
HADS = FICD: The flag to indicate that the contents are
data FICD=O or a command FICD=1.
HAD[4:0] = The B address to the CPU register file which in this case is register RO.
HD[1S:13] = User-defined.
HD[12]

=Test bit to differentiate between breakpoint and single-step.
HD12=O for breakpoint and HD12=1 for single-step.

HD[11:10] = User-defined.
HD[9:0] = Breakpoint Address or for single-step user-defined.

4-84

WAFERSCALE INTEGRATION, INC.

I'AC1000 - Application Note 009

Figure 2.
BreakpDint!
Single-step
RDwchart

WAFERSCALE
_ _ _ _ _ _ _ _ _ _u_ • • • _. _ _ _•

_ _~

____

~

_ _ _ _ ~~

_ _ _ _ _-

INTEGRATIO~

INC.

4-IJ5

PAC1000 - Application Note 009

Figure 2.
Breakpoint!
Single-Step
Flowchart
(Cont.)

4-B6

WAFERSCALE INTEGRATION, INC.

PAC1000 - Application Note 009

Figure 3.
Sequence of
Events for
Interrupt Timing

CK

CPC
Perform
INT6 occurs.
addition
Perform
R2:= R2 + Rl. addition
R3:= R3 + Rl.
BP register

was previously
loaded with
h'07a'

INT61s
INT6 vector
latched and
occurs to
change CPC.
pending.
Push return
Perform
address of
addition
R4:= R4 + Rl. h'07c' to stack.

CPC
Select singlestep Interrupt
for INT6.

INT6 occurs
and CPC will
jump to h'07e'

INT61s
latched and
pending.

INT6 vector
occurs to
change CPC.

Perform

Push return

addition of
address of
RS:= RS + Rl. h'07f' to stack.
Note: CPC Is the name from the simulator PACSIM for currently executing

program counter.

/*****************************************/
/* BP and S8 linker file
04/03/89
/* David Fong
Rev. 1.0
/* bpss.ml

*/
*/
*/

/*****************************************/
place main, int, intserv, init, single;
/* place the segments */
load main, int, intserv, init, single; /* load the .mal files */
locate
locate
locate
locate
locate

in it , h'OOO' ;
intserv , h'008'
main , h'050'
int , h'lOO' ;
single, h'200'

/* locate the init file */
/* locate the interrupt vectors */
/* locate the main file */
/* locate the ISR */
/* locate the single files */

end ;

/*********************************/
/* INITIALIZATION
/* David Fong
/* init.mal

04/03/89
Rev. 1.0

*/
*/
*/

/*********************************/
segment init ;
external mainl
SETMODE h'OOl' , OUT h'0002'
/* switch to interrupt mode */
ENABLE INT6 , OUT h'OOOl'
JMP mainl , OUT h'OOOO' ; /* jump to main program */
end
WAFERSCALE INTEGRATION, INC.

4-87

PACtOOO - Application Note 009

/**********************************/
/* Main program
04/03/89 */
/* David Fong
Rev. 1.0
*/
/* main. mal
*/
/**********************************/
segment main ;
entry mainl
mainl
/************************************************/
/* BEGIN MAIN PROGRAM
*/
/************************************************/
/* initialize registers */
Rl := h'lOOO' , OUT h'0050' ;/* the twelveth bit Rl.12 tests for BP/SS*/
/* IF Z=l (which means Rl.l2 = 0 ) THEN run breakpoint program */
/* ELSE run single-step program */
R2 := h'OO02'
OUT h'005l'
R3 := h'OO03'
OUT h'0052'
R4 := h'OO04'
OUT h'0053'
R5 := h'0005'
OUT h'0054'
R6 := h'OO06'
OUT h'0055'
R7 := h'0007'
OUT h'0056'
R8 .- h'0008'
OUT h'0057'
R9 := h'OO09'
OUT h'0058'
RIO .- h'OOOa'
OUT h'0059'
Rll := h'OOOb'
OUT h'005a'
R12 := h'OOOc'
OUT h'005b'
Rl3 := h'OOOd'
OUT h'005c'
R14 := h'OOOe'
OUT h'005d'
R15 := h'OOOf'
OUT h'005e'
Rl6 := h'OOlO'
OUT h'005f'
Rl7 := h'OOll'
OUT h'0060'
Rl8 := h'0012'
OUT h'006l'
Rl9 := h'OOl3'
OUT h'0062'
R20 := h'00l4'
OUT h'0063'
R2l := h'0015'
OUT h'0064'
R22 := h'OOl6'
OUT h'0065'
R23 := h'0017'
OUT h'0066'
R24 .- h'00l8'
OUT h'0067'
R25 := h'OOl9'
OUT h'0068'
R26 := h'OOla'
OUT h'0069'
R27 := h'OOlb'
OUT h'006a'
R28 .- h'OOlc'
OUT h'006b'
R29 := h'OOld'
OUT h'006c'
R30 := h'OOle'
OUT h'006d'
R3l .- h'OOlf'
OUT h'006e'
ACH := R3l , OUT h'006f'
ACL := RO , OUT h'0070'
AOR .- Rl I OUT h'007l'
DOR .- Rl5 , OUT h'0072'
BC := R7 , OUT h'0073'
4·88

;
;
;
;
;

WAFERSCALE INTEGRATION, INC.

PAC1000 - ApplicatiDn NDte 009

/* all input registers are initialized to zero from RESET */
/*
/*
/*
/*

to integrate two different programs 1. BREAKPOINT 2. SINGLE-STEP*/
The result of masking RO with R1 is used to differentiate */
between BP and SS. */
IF Z = 1 Breakpoint; ELSE Z = 0 Single-Step */

/***************** READ IN FIFO AND TEST FOR BP/SS ********************/
gO: JMPC FICD gO , OUT h'0074' ; /*check that the fifo contents is data
LDBPD , RDFIFO , OUT h'007S'; /* FIFO was loaded with h'O 00 007a' */
/* first 0 is FICD ; 00 is B address ; 0 is the test bit ; */
/* 07a is the EPROM breakpoint address. */
/* Load loop counter with same data read from FIFO : LDLCD; */
/* the data written into the CPU is the same as the CPU output bus */
AND R1 RO , OUT h'0076' ; /* the Z flag is tested in the next cycle */
JMPC Z bO , OUT h'0077' ;
/* select single-step interrupt */
ESS , OUT h'0078' ;
JMP cO , OUT h'0079' ; /* skip breakpoint routine */
/**************** BREAKPOINT ***************************************/
/* perform alu operations till interrupt comes */
bO:
R2:= R2 + R1 , OUT h'007a' ; /* breakpoint on this address h'07a'
R3 := R3 + R1 , OUT h'007b' ;
R4 := R4 + R1 , OUT h'007c' ; /* breakpoint interrupt comes here */
/* return from ISR to here */
eO : JMP eO , OUT h'007d';
/* loop forever ; end of breakpoint */
/*************** SINGLE-STEP **************************************/
cO:
RS:= RS + R1 , OUT h'007e' ; /* execute till interrupt comes *i
R6 := R6 + R1 , OUT h'007f' ; /* interrupt should after here */
/* return from single-step ISR to here */
/* enable single-step interrupt and perform an operation */
ENABLE INT6 , R7 := R7 + Rl , OUT h'0080' ; /* the output for R2 */
/* should be h'1002' */
R8 := R8 + R1 , OUT h'0081' ; /* interrupt should come here */
/* return from single-step ISR to here */
fO : JMP fO , OUT h'0082' ;
end ;

/* loop forever */

/*********************************/
/*SINGLE-STEP SUBROUTINE 04/03/89*/
/* David Fong
Rev. 1.0
*/
/* single.mal
*/
/*********************************/
segment single ;
entry single1 ;
single1
/* read out the registers from the ALU */
/* use the addressing scheme from the FIFO */
WAFERSCALE INTEGRATION, INC.

4-89

PAC10DO - Application Note 009

SETCON h'OlO' , OUT h'2000' ; /* set ADD bus to output */
/* to read out AOR to ADD */
/* loop four times to address the 32 registers */
FOR 3 , OUT h'200l' ;
/* FIFO should already be full */
fO

JMPC FIIR fO , OUT h'2002' ;

/* loop till FIFO is full*/

fl

/* check that the first value in the FIFO is a data */
JMPC FICD fl , OUT h'2003' ;
/* loop eight times to empty the FIFO */
FOR 7 , OUT h'2004' ;
/*
/*
/*
/*
/*

use
the
and
the
the

the FIFO as an address pointer */
data is not needed; write the data back to CPU */
output the CPU output to AOR */
default CPU instruction is add which adds zero and */
address pointed by the FIFO which is the B address */

RDFIFO , alu src = zb , ybus_sel
OUT h'2005' ;ENDFOR , OUT h'2006'

=

y_aoreg ,

ENDFOR , OUT h'2007' ;
/* read
MOV AOR
MOV AOR
MOV AOR
MOV AOR
MOV AOR
MOV AOR

out the source registers to
DIR
OUT h'2008'
/* 0000
AIR
OUT h'2009'
/* 0000
ACH
OUT h'200a'
/* OOlf
ACL
OUT h'200b'
/* 0000
IIR
OUT h'200c'
/* 0000
BC
OUT h'200d'
/* 0007

ADD */
should come out next cyle */

*/
*/
*/
*/
*/

RET , OUT h'200e' ; /* return to ISR 6 */
end

/*********************************/
/* INTERRUPT JUMP TABLE 04/03/89*/
/* David Fong
Rev. 1.0
*/
/* intserv.mal
*/
/*********************************/
segment intserv ;
entry int_serv ;
external into,intl,int2,int3,int4,int5,int6,int7
int_serv
JMP
JMP
JMP
JMP
4-IIJ

into
intl
int2
int3

OUT
OUT
OUT
OUT

h'OO08'
h'OO09'
h'OOOa'
h'OOOb'

WAFERSCALE INTEGRATION, INC.

PACfOOO - ApplicatiDn NDte 009

JMP
JMP
JMP
JMP

int4
int5
int6
int7

OUT
OUT
OUT
OUT

h'OOOc'
h'OOOd'
h'OOOe'
h'OOOf'

end

/********************************************************/
/* Interrupt Service Routines
04/03/89
/* David Fong
Rev. 1.0
/* int.mal

*/
*/
*/

/********************************************************/
segment int ;
entry into ,int1
external single1 ;
into

int2, int3 , int4 , int5 , int6 , int7

/* clear all the external interrupts */
CLI h'OOf' , OUT h'0100'
RET , OUT h'0101' ;

int1

/* clear all the external interrupts */
CLI h'OOf' , OUT h'0102'
RET , OUT h'0103' ;

int2

/* clear all the external interrupts */
CLI h'OOf' , OUT h'0104'
RET

int3

,

OUT h'0105' ;

/* clear all the external interrupts */
CLI h'OOf' , OUT h'0106'
RET , OUT h'0107' ;

int4

/* mask that interrupt */

DISABLE INT4 , OUT h'0108'
RET , OUT h'0109' ;

int5

/* mask that interrupt */

DISABLE INT5 , OUT h'010a'
RET , OUT h'010b' ;

int6

/* Breakpoint and Single-step ISR */
/* mask that interrupt */
DISABLE INT6 , OUT h'010c'
/* mask interrupt 6 INT6 */
CLI h'Off' , OUT h'010d';
/* clear all interrupts */

/************** TEST for Breakpoint/Single-Step **************/

AND R1 RO , OUT h'010e' ;
JMPC Z aO , OUT h'OlOf' ; /* if Z=l then breakpoint,Z=O SS */
WAFERSCALE INTEGRATION, INC.
----------

4-91

PAC1000 - Application Note 009

CALL singlel , OUT h'0110' i/* call single step program */
JMP bO , OUT h'OIII' i /*finish SS ISR , return to main progr */
aO:

SET HDOE HDSELO , OUT h'0112' ; /* set HD to output */
/* select DOR to HD output bus*/
/* move out the source registers to HD */
MOV
MOV
MOV
MOV
MOV
MOV
MOV

DOR
DOR
DOR
DOR
DOR
DOR
DOR

DIR
AIR
AOR
ACH
ACL
IIR
BC

OUT
OUT
OUT
OUT
OUT
OUT
OUT

h'0113'
h'0114'
h~0115'

h'0116'
h'0117'
h'0118'
h'0119'

/*
/*
/*
/*
/*
/*
/*

0000
0000
0001
001f
0000
0000
0007

should come out next cycle*/
*/
*/
*/
*/
*/
*/

bO:
RET, OUT h'Olla'
int7
/* mask that interrupt */
DISABLE INT7 , OUT h'Olla'
RET , OUT h'Ollb' ;
end

.T
RCCCCCCCCIIIIIIIIIIIICWRHHHHHHHHHHHHHHHHHHHHH~

ECCCCCCCCOOOOOOOONNNNSRDDDDDDDDDDDDDDDDDAAAAAADDDDDDDDDDDDDDDD
S7654321076543210TTTTBBB1111119876543210DDDDDDDDDDDDDDDDDDDDDD
3210
543210
5432101111119876543210
E
T
543210
B

TIME
1
00000000000000000000011100000000000000000000000000000000000000
2
10000000000000000000011100000000000000000000000000000000000000
# bpsO.stl file for single-stepping
# write the single-step mode bit hdl2=1
20
10000000000000000000000100010000000000000000000000000000000000
21
10000000000000000000011100010000000000000000000000000000000000
# write into FIFO for single-step
55
1000000000000000000001110000000000000000000000ZZZZZZZZZZZZZZZZ
56
1000000000000000000000010000000000000000000000ZZZZZZZZZZZZZZZZ
57
1000000000000000000001110000000000000000000000ZZZZZZZZZZZZZZZZ
58
1000000000000000000000010000000000000000000001ZZZZZZZZZZZZZZZZ
59
1000000000000000000001110000000000000000000001ZZZZZZZZZZZZZZZZ
60
1000000000000000000000010000000000000000000010ZZZZZZZZZZZZZZZZ
61
1000000000000000000001110000000000000000000010ZZZZZZZZZZZZZZZZ
62
1000000000000000000000010000000000000000000011ZZZZZZZZZZZZZZZZ
63
1000000000000000000001110000000000000000000011ZZZZZZZZZZZZZZZZ
64
1000000000000000000000010000000000000000000100ZZZZZZZZZZZZZZZZ
65
1000000000000000000001110000000000000000000100ZZZZZZZZZZZZZZZZ
66
1000000000000000000000010000000000000000000101ZZZZZZZZZZZZZZZZ
67
1000000000000000000001110000000000000000000101ZZZZZZZZZZZZZZZZ
68
1000000000000000000000010000000000000000000110ZZZZZZZZZZZZZZZZ
69
1000000000000000000001110000000000000000000110ZZZZZZZZZZZZZZZZ
70
1000000000000000000000010000000000000000000111ZZZZZZZZZZZZZZZZ
71
1000000000000000000001110000000000000000000111ZZZZZZZZZZZZZZZZ
4-92

WAFERSCALE INTEGRATION, INC.

PAC1000 - Application Note 009

95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190

1000000000000000000000010000000000000000001000ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001000ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001001ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001001ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001010ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001010ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001011ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001011ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001100ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001100ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001101ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001101ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001110ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001110ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001111ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001111ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000010000ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000010000ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000010001ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000010001ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000010010ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000010010ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000010011ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000010011ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000010100ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000010100ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000010101ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000010101ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000010110ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000010110ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000010111ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000010111ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000011000ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000011000ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000011001ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000011001ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000011010ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000011010ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000011011ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000011011ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000011100ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000011100ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000011101ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000011101ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000011110ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000011110ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000011111ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000011111ZZZZZZZZZZZZZZZZ

# write into FIFO second time around for single-step
240
241
242
243
244
245
246
247

1000000000000000000001110000000000000000000000ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000000000ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000000000ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000000001ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000000001ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000000010ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000000010ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000000011ZZZZZZZZZZZZZZZZ
WAFERSCALE INTEGRATION, INC.

-----------,--'-~-,

4-93

II

PAC1000 - Application Note 009

248
249
250
255
256
257
258
259
260
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
4·94

1000000000000000000001110000000000000000000011ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000000100ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000000100ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000000101ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000000101ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000000110ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000000110ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000000111ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000000111ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001000ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001000ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001001ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001001ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001010ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001010ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001011ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001011ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001100ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001100ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001101ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001101ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001110ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001110ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000001111ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000001111ZZZZZZZZZZZZZZZZ
1000000000000000000000010000000000000000010000ZZZZZZZZZZZZZZZZ
1000000000000000000001110000000000000000010000ZZZZZZZZZZZZZZZZ
10000000000000000000000100000000000000000lOOOlZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOlOOOlZZZZZZZZZZZZZZZZ
lOOOOOOOOOOOOOOOOOOOOOOlOOOOOOOOOOOOOOOOOlOOlOZZZZZZZZZZZZZZZZ
lOOOOOOOOOOOOOOOOOOOOlllOOOOOOOOOOOOOOOOOlOOlOZZZZZZZZZZZZZZZZ
lOOOOOOOOOOOOOOOOOOOOOOlOOOOOOOOOOOOOOOOOlOOllZZZZZZZZZZZZZZZZ
lOOOOOOOOOOOOOOOOOOOOlllOOOOOOOOOOOOOOOOOlOOllZZZZZZZZZZZZZZZZ
10000000000000000000000lOOOOOOOOOOOOOOOOOlOlOOZZZZZZZZZZZZZZZZ
lOOOOOOOOOOOOOOOOOOOOlllOOOOOOOOOOOOOOOOOlOlOOZZZZZZZZZZZZZZZZ
10000000000000000000000lOOOOOOOOOOOOOOOOOlOlOlZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOlOlOlZZZZZZZZZZZZZZZZ
10000000000000000000000lOOOOOOOOOOOOOOOOOlOllOZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOlOllOZZZZZZZZZZZZZZZZ
10000000000000000000000lOOOOOOOOOOOOOOOOOlOlllZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOlOlllZZZZZZZZZZZZZZZZ
10000000000000000000000lOOOOOOOOOOOOOOOOOllOOOZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOllOOOZZZZZZZZZZZZZZZZ
10000000000000000000000lOOOOOOOOOOOOOOOOOllOOlZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOllOOlZZZZZZZZZZZZZZZZ
10000000000000000000000lOOOOOOOOOOOOOOOOOllOlOZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOllOlOZZZZZZZZZZZZZZZZ
lOOOOOOOOOOOOOOOOOOOOOOlOOOOOOOOOOOOOOOOOllOllZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOllOllZZZZZZZZZZZZZZZZ
10000000000000000000000lOOOOOOOOOOOOOOOOOlllOOZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOlllOOZZZZZZZZZZZZZZZZ
10000000000000000000000lOOOOOOOOOOOOOOOOOlllOlZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOlllOlZZZZZZZZZZZZZZZZ
10000000000000000000000lOOOOOOOOOOOOOOOOOllllOZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOllllOZZZZZZZZZZZZZZZZ
10000000000000000000000lOOOOOOOOOOOOOOOOOlllllZZZZZZZZZZZZZZZZ
100000000000000000000lllOOOOOOOOOOOOOOOOOlllllZZZZZZZZZZZZZZZZ
WAFERSCALE

INTEGRATIO~

INC.

PAC1000 - Application Note 009

.T
RCCCCCCCCIIIIIIIIIIIICWRHHHHHHHHHHHHHHHHHHHHH~

ECCCCCCCCOOOOOOOONNNNSRDDDDDDDDDDDDDDDDDAAAAAADDDDDDDDDDDDDDOD
S7654321076543210TTTTBBBlllll19876543210DDDDDDDDDDDDDD00000000
E
3210
543210
5432101111119876543210
T
543210
B

TIME
1
00000000000000000000011100000000000000000000000000000000000000
2
10000000000000000000011100000000000000000000000000000000000000
20
10000000000000000000000100000000011110100000000000000000000000
21
10000000000000000000011100000000011110100000000000000000000000
53
100000000000000000000111ZZZZZZZZZZZZZZZZ0000000000000000000000
# bps1.stl uses Z=l for breakpoint ISR; HD12=0;
*********The bpsO.out file **********
***********************************************************************

o U T PUT

TAB L E

PACSIM
Ver. 1. 09
Tue Apr 04 15:43:42 1989
***********************************************************************

TIME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

CCC
PPP
CCC
173
1· •
:40
8

0000
CCCC
1173
51: :
: : 40
18
2

A
0
0
E

AAAA
DODD
DODD
1173
51: :
: : 40
18
2

AAAA FFFIB PPP
0000 IIINR CCC
RRRR CIOTP 173
1173 DRRRT 1· •
51: :
E :40
: :40
Q 8
18
U
2
L

LLL
CCC
173
1· •
:40
8

BBBB
CCCC
1173
51: :
: : 40
18
2

000
000
000
001
002
050
051
052
053
054
055
056
057
058
059
05a
05b
05c
05d
05e
05f
060
061

0000
0000
0002
0001
0000
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
005a
005b
005c
005d
005e
005f
0060
0061

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

00001
00001
01000
01000
01000
01000
01000
01000
01000
01000
01000
01000
01000
01000
01000
01000
01000
01000
01000
01000
01000
01100
01100

000
000
001
002
050
051
052
053
054
055
056
057
058
059
05a
05b
05c
05d
05e
05f
060
061
062

WAFERSCALE INTEGRATION, INC.

II

4·95

PAC1DDD - Application Note DDS

24
25
26
27
28
29
30
31
32
33
***Due

062 0062 0 0000 0000
063 0063 0 0000 0000
064 0064 0 0000 0000
065 0065 0 0000 0000
066 0066 0 0000 0000
067 0067 0 0000 0000
068 0068 0 0000 0000
069 0069 0 0000 0000
06a 006a 0 0000 0000
06b 006b 0 0000 0000
to the length of the

01100 063 000
01100 064 000
01100 065 000
01100 066 000
01100 067 000
01100 068 000
01100 069 000
01100 06a 000
01100 06b 000
01100 06e 000
file, the rest

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
of the output is not shown ***

***********The bps1.out file *************
***********************************************************************

a

U T PUT

TAB L E

PAC S I M
Ver. 1.09
Man Apr 03 13:08:15 1989
***********************************************************************
CCC 0000 M
PPP ecce D
ccc 1173 a
173 51: : E
1· • : : 40
:40 18
8
2

CC DI BBB B HHHH
CC ON RRR R DDDD
73 RT EEE P 1173
RAAAT51::
40
KKKE : : 40
RRR Q 18
EEE U 2

..

LLL BBBB
CCC
173
1· •
:40
8

ecce

000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

1173
51::
:: 40
18
2

GGG L

..... .

973

840
TIME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

000
000
000
001
002
050
051
052
053
054
055
056
057
058
059
05a
05b
05e
05d
05e
05f
060
061

4-96

WAFERSCALE INTEGRATION, INC.

0000
0000
0002
0001
0000
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
005a
005b
005e
005d
005e
005f
0060
0061

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000

OQO
000
000
000
000
000

1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
007a
007a
007a
007a

PAC1000 - Application Note 009

24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

062
063
064
065
066
067
068
069
06a
06b
06e
06d
06e
06f
070
071
072
073
074
075
076
077
07a
07b
ODe
10e
10d
10e
10f
112
113
114
115
116
117
118
119
11a
07e
07d
07d
07d
07d
07d
07d
07d
07d

0062
0063
0064
0065
0066
0067
0068
0069
006a
006b
006e
006d
006e
006f
0070
0071
0072
0073
0074
0075
0076
0077
007a
007b
OOOe
010e
010d
010e
010f
0112
0113
0114
0115
0116
0117
0118
0119
011a
007e
007d
007d
007d
007d
007d
007d
007d
007d

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1

1

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a
07a

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
007a
OOOf
OOOf
0000
0000
1000
OOlf
0000
0000
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007

000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007
0007

WAFERSCALE INTEGRATION, INC.

II

4-111

4-98

WAFERSCALE INTEGRATION, INC.

~~~~-------

Programmable System™Device
Application Brief 007
WAFERSCALE INTEGRATION, INC.

Hardware Interlacing the PACtOOO as a
Micro Channel Bus Controller
By Arye Zik/lk

Abstract

MeA Signal
Descriptions

This application brief describes how to use
the PAC1000 High-Performance UserConfigurable Microcontroller as a Micro
Channel (MCA) bus controller.

board, or from the PS/2 mother-board (the
system) to a slave. This application brief
describes the use of the PAC1000 on a
master board and on a slave board.

The MCA bus uses asynchronous and
synchronous procedures to control and
transfer data on the bus. The data is
transferred from a master board to a slave

In both applications the PAC1000 is
handling the synchronous functions, the
asynchronous functions are implemented
by external PALs.

The bus signals described in this chapter
are the most important and essential
signals to understand the application brief.
The buffers needed per each signal are
summarized in Table 2. The timing relations
between the signals is drawn in Figure 1.

MiiO
MemoryllO, driven by the bus master and
indicates a memory or 10 cycle. MilO is
latched by the slave at the leading edge
of CMD Signal.

so, S1
AO-A23
Address bits generated by the bus master
to address memory and 10 slaves attached
to the bus. The address bits are unlatched
and must be latched by the slaves using
either the trailing edge of ADL or the
leading edge of CMD signals.

Status bits, driven by the bus master and
indicate the start of read or write cycle.
The status bits are latched by the slaves
using the leading edge of CMD.

CMD

Data bits, valid during the period CMD
signal is low. The data is driven by
bidirectional three-state drivers.

Command Signal is driven by the bus
master and defines the period data is valid
on the data bus. The leading edge of
CMD is used to latch the unlatched
signals: AO-23, MilO, SO, and S1. The
trailing edge of CMD indicates the end of
the bus cycle.

ADL

CD_SIDB'

Address Decode Latch, driven by the bus
master. The signal is used by the slaves
to latch valid address and status bits.

Card Select Feedback. When a bus master
addresses a memory or an 10 slave, the
addressed slave drives CD_SFDBK active
as a positive acknowledgement of its
presence at the specified address.

00-015

CD_DS16
Card Data Size 16, driven by 16 bit slaves
to provide an Indication to the master
about their data bus width. Eight-bit slaves
do not drive this line.

DS_16_RTN
Data Size 16 Return. A Signal generated
by the PS/2 system by AND-ing all the
CD_DS16 signals received from all the
slave connected to the bus. The signal is
provided by the PS/2 system to the bus
masters.

CD_CHRDY
Channel Ready. This line is pulled inactive
(not ready) by a slave to allow additional
time to complete a bus cycle.

CHRDYRTN
Channel Ready Return. Generated on the
PS/2 system board by AND-ing the
CD_CHRDY signals driven by all the
slaves. The signal is provided by the
system to the mastr driving the bus.

WAFERSCALE INTEGRATION, INC.

4·99

PAC1000 - Application Brief 001

MCA Signal
Descriptions
(Cont.)

ARBO-ARB3

PREEMPT

Arbitration Bus priority signals. These four
signals represent the priority levels for
masters seeking control on the bus. The
four signals represent 16 priority levels,
level 15 represents the lowest priority,
level 0 represents the highest priority and
belongs to the PS/2 system.

Used by the arbitration bus masters to
request the bus.

BURST
Indicates that the master requests the bus
for transferring a block of data.

IRO
ARB/INT
Arbitrate/Grant. When high, this signal
indicates an arbitration cycle is in process.
When low, indicates that a master has
been granted. ARB/GNT is driven by the
system.

Figure 1. Micro
'Channel Basic
Transfer Cycle

10

40

Interrupt Request is used to signal the
system that a device requires attention.

CHRESET
Channel Reset, active high reset signal
generated by the system and sent to all
the boards on the bus.

80

120

I

~~-gRESS

I 200 nsec
I

160

IJJJJJJJJ E

!-I

1 _ _ _ _ _ _----,9

I

n
I

STATUS

I

18

2

~--------------~

____~1~7-------------

1~3

CD CHRDY
CD DS16

111

15

+--------.1....

---'1

4__________

CD SFDBK

10

r"'ll-0- - - - -

I
I
I

WRDATA

JJJJJJJJJJJJL--16____________~
:

RD DATA

17

14

JJJJJJJJJJJJJJJJJJJJJJI12

r
I

I

1

Table 1. The
States Generated
MRD, fDandft

MCA Timing
Parameters

MilO

SO

S1

0
0
1
1

0
1
0
1

1
0
1
0

The PAC1000 as a bus master transfers
data on the MCA bus with a control
sequence based on the following events:
I;J The add res bus and M/IO signal

become valid.
I;J The status signals SO and S1 are valid

10 nsec minimum after (1).

4·100

WAFERSCALE INTEGRATION, INC.

I/O write.
I/O read.
Memory write.
Memory read.

I;J ADL is valid 45 nsec minimum after (1).
I;J In response to the unlatched address

decode, the selected slave responses
with CD_SFDBK (and CD_DS16 if it
is a 16 bit slave). The maximum
allowable response time of the slave is
55 nsec maximum from (1).

PAC1000 - AppllcatiDn Brief 007

MCA Timing
Parameters
(Cont.)

I;J The address bus becomes inactive

I;J In response to (1), the slave responds

after the address was latched.

with CD_CHRDY. The maximum
allowable response time is 60 nsec
maximum from (1).

I;J In response to the address change, the

slave's unlatched responses
(CD_CFDBK AND CD_DS16) are
invalid.

I;J Write data appears on the bus for the

write cycle. The data has to be valid
before the leading edge of CMD.

I;J System stays in this state until

I;J CMD becomes active and ADL inactive

typically 85 nsec minimum after (1).
The unlatched signals on the bus are
latched.

response to a read.
I;J The address and M/IO are valid for the

I;J The status signals become inactive

next cycle.

after they were latched.

Operation Modes

CD_CHRDY is ready.
I;J The slave places data on the bus in

I;J CMD goes inactive, ending the cycle.

The PAC1000 working as a MeA
controller can handle the following
functions:

Bus Slave Board

size depends on the number of address
bits it is decoding. The decoder's CS
outputs are latched by the leading edge of
CMD and are stable until the end of the
bus cycle. The decoder generates the
feedbacks to the bus, CD_SFDBK,
CD_DS16 and CD_CHRDY. These
Signals are not latched and are very time
critical. The decoder responds with these
outputs at 55 nsec maximum after the
address is stable.

On a bus slave board the PAC1000 may
be used to implement the POS registers.

Bus Master Board

I;J Bus signal generator.
I;J Card setup.

The bus arbitration logic and signal
decoding are pure asynchronous functions
and implemented by two PALs.

A master board is a board with a CPU
which requests the MCA bus. When
granted by the PS/2 system, the master
board is driving the bus signals.

The Programmable Option Select (POS)
registers main objectives are:
I;J Eliminate switches from the board.
I;J Positively identify any card connected

On a master board the PAC1000 can
handle the following functions:

to the system.
The POS registers on a PS/2 board replace
the switches by using software writeable
registers. There are eight POS registers,
each one is 8-bit wide. The POS registers
are addressed by CD_SETUP signal and
by address bits AO-2. The POS registers
are located at I/O addresses 100H to
107H. The'eight POS registers are located
in the PAC1000 and control the board's
functions.
The POS registers' interface to the MCA
is a decoder which decodes the sytem's
access to the registers and generates the
RD and WR signals to the PAC1000.

I;J POS registers (similar to the bus slave

board).
I;J Generation of the bus signals

The other functions of a bus controller are
implemented by PALs because the
functions are pure asynchronous.
The bus signals are generated by the
PAC1000 after the CPU is granted to be a
bus master. The process of getting the
bus is done in the following sequence:
I;J The CPU is requesting the bus through

one of the interface lines with the
PAC1000.

The address decoder and slave logic are
most of the circuitry needed for the slave
functions. The decoder has to decode the
address on the bus and to respond with
CD_SFDBK, CD_CHRDY and CD_DS16
signals. The address decoder might be for
memory, 110 or for both. The decoder's

I;J The PAC1000 is setting the bus

request line which is buffered by
drivers and sent to the MCA system.
I;J The system gets the request, and sets

a bus arbitration cycle which is handled
by the bus arbiter circuit (a PAL).

WAFERSCALE INTEGRATION, INC.

4-101

PAC1000 - Application Brief 007

Operation Modes
(Cont.)

r:J The bus arbiter sends the PAC1000 the
signal MASTER which tells the board
that the bus was granted and the board
may drive the bus.

r:J The PAC1000 signals the CPU that it is
the bus master.

r:J The PAC1000 is enabling the address
and data drivers, and the CPU drives
the address and data to the bus.

r:J The PAC1000 generates all the bus
signals in the right sequence and the
right timing requirements as defined by
the MCA bus standard.

PAC1000 in a
Micro Channel
Slave Board

MICRO
C HANNEL

r:J After the CPU is done, it releases the
bus request. The PAC1000 translates it
to the right signal sequence on the
MCA bus and releases the bus buffers.
On the bus master board the PAC1000
may implement a lot of control functions
and save glue logic.
For example:
The PAC1000 can handle several DMA
operations on the board, or be used as a
high speed controller for various
applications.

PAC1000

I
I
I PAC1000
I SLAVE BOARD
I
I

pas
REGISTERS
(REGISTER BANK)

-------107-0

DATAO-7
DATAO-7
ADDRO-3

ADDRO-3

pas
REGISTER
INTERFACE

HADS-O

RD_POS
RD
WFLPOS

CD_SETUP

Sii,S1

07-0

LATCHED
CONTROL
SIGNALS
TO THE
BOARD

CS

WR

OC1S-0

cs

ADD1S-0
HAD1S-0
INT3-0
CC7-0

Table 2. Driver
Requirement for
PSI2 Signals

4·102

Signal Name
A(0-23)
D(0-15)
ADL
CD_DS16
DS_16RTN
MIlO
SO, S1
CMD
CD_SFDBK
CD_CHRDY
CHRDYRTN
ARB(0-3)
PREEMPT
BURST
ARB/GNT

WAFERSCALE INTEGRATION, INC.

Driver Type
TS 24 mA (TS = Three-State)
TS 24 mA
TS 24 mA
TP 6 mA (TP = Totem Pole)
BD 24 mA (BD = Bus Driver)
TS 24 mA
TS 24 mA
TS 24 mA
TP 6 mA
TP 6 mA
BD 24 mA
OC 24 mA (OC = Open Collector)
OC 24 mA
OC 24 mA
BD 24 mA

PAC1000 - Application Brief 007

PACtOOO as a
Micro Channel
Master
I
I
MICRO
I PAC1000
CHANNEL BOARD

I
I

DO-D15

..

DO-D15

•

DATA
BUFFERS

AO-A23

DIR_BUF
EN_BUFF

AO-A23
ADDRESS
LATCHES

CMD

DILBUF
EN_BUFF

PAC1000

CMD

CPU
OC9

ADL

ADL

So

So

S1

S1

OCB

MIlO
SBHE
CHRESET

DECODER
AND
SIGNAL
DRIVERS
(PAL AND
DRIVERS)

OC7
OC6

MIlO
OC5
SBHE
OC4
INT3-0

CHRESET
CC3

ADD15-0
CHRDYRTN

CHRDYRTN
CC2

DS16 RTN

DS16 RTN

IRQ

IRQ

BUS
MASTER

CCl
OCl
OC15-10
ARBO-3

BUS REQUEST
OCO
LATCHED
CONTROL

PREEMPT
BURST

BUS
ARBITER
(ONE PAL)

107-0
MASTERISLAVE

ARBIGNT

CCO

~ rJg~~~~E

REGISTER
OUTPUTS)

DATAO-7
HD7-0
ADDRO-3

ADDRO-3
HAD5-0

CD_SETUP

POS
REGISTER
INTERFACE

RD_POS
RD
WLPOS
WR

So,S1

Cs

Cs

WAFERSCALE INTEGRATION, INC.

4·103

4-104

WAFERSCALE INTEGRATION, INC.

Programmable System™Oevice
WAFERSCALE INTEGRATION, INC.

Application Note 003

High-End SAM Applications Using
Microassembler Design Entry
Scope of This
Application Note

This Application Note describes the SAM
microsequencer design entry process utilizing
ASM microassembler input syntax and
provides illustrations of all basic concepts
needed to execute a SAM microassembler
design. Basic microassembler functionality
is reviewed, its utilization of SAM internal
resources, as well as user convenience
features. Cascading of multiple SAM devices
to address large design problems is also

covered. To illustrate a practical application
of SAM, a graphics controller application is
presented in detail along with annotated
ASM source code.

The SAM
Solution

The SAM (Stand-Alone Microsequencer)
User-Configurable device provides a unique
solution for high-performance control
functions. The combination of a microcoded
engine with a branch EPLD front-end gives
SAM the ability to handle high-complexity
tasks while still achieving high clock rates.
The basic SAM architecture is shown in
Figure 1.

Programming the SAM device for a
particular application involves specifying
multi-way branch transition specifications
for the branch EPLD, and instruction and
output strings for the required number of
microcode words in SAM's EPROM control
memory. (See the SAM448 Data Sheet for
further information). This task is eased by
the use of the SAM+PLUS development
system.

SAM+PLUS
System Overview

The SAM+PLUS PC-based design
development system provides an efficient
mechanism for entry and automatic
compilation of SAM designs. Interactive
functional simulation is provided in
SAM+PLUS to enable rapid verification of
design flows and operation. PC-compatible
programming hardware is also available to
allow device programming right at the

designer's desk. Given the fact that control
logic is frequently difficult to design, and
particularly prone to design alterations, the
ability to enter, compile, simulate and test
a design in rapid fashion results in an
effective design system.

Figure 1.
SAM448 Block
Diagram

ZERO

INPUTS
(8)

BRANCH
CONTROL
lOGIC

SAM+PLUS actually supports two design
entry methods, one using ASMILE state
machine input language, the other ASM

MICROCODED ENGINE

PlD
NRESET

The reader is referred to WSI's SAM448
Data Sheet for details concerning device
architecture and performance. A general
knowledge of SAM device architecture is
assumed as background for this
Application Note.

MICROCODE
EPROM

448 x 36
BITS
EPLD
768 PRODUCT
TERMS
ClK

OUTPUTS (16)

WAFERSCALE INTEGRATION, INC.

4-105

SAM448 - Application Note 003

SAM+PLUS
System Overview
(Cont.)

microassembler format, as shown in
Figure 2. SAM ASMILE input is described
in WSI Application Note #4, referenced
below. This Application Note will focus on
microassembler input.
Microassembler design entry begins with
the creation of a design file on the PC
using any standard text editor. Next, the
SAM Design Processor (SDP) takes the
ASM input file, automatically minimizes
transition equations and generates the
device programming code. A Utilization
Report is generated which reports total
resources consumed, absolute memory
assignments of microassembler instructions
and compiler-assigned pinouts. A standard
JEDEC file is generated to allow
programming of the device right on
the PC.

For larger designs, multiple SAM devices
may be horizontally cascaded to increase
the number of available control outputs.
The microassembler supports the
specification of a single source file for a
multiple-SAM application, and automatically
generates the separate JEDEC files for the
programming of each of the devices at
compile time. The JEDEC file, which
represents the actual template of the
specific application implemented, may be
used as input to the SAMSIM (SAM
SIMulator) program which provides
functional simulation capability. Hard-copy
output of simulation results may be
obtained, as well as on-line "logic
analyzer" viewing capability. Multi-chip
applications using horizontal cascading is
also supported by the functional simulator.

The SAM architecture supports highperformance synchronous control
applications. It is important to realize that
all outputs from SAM are asserted
synchronously with respect to the device

clock, and as such SAM implements a
classic Moore machine architecture.
Similarly, as can be seen in the SAM Data
Sheet, all inputs must obey a required setup time (Tsu) relative to the Clock input.

Figure 2.
SAM+PLUS
Block Diagram

Choosing
Appropriate
Applications
for SAM
4·106

WAFERSCALE INTEGRATION, INC.

SAM448 - Application Note 003

Choosing
Appropriate
Applications for
SAM (Cont.)

In order to obtain greater than 16 outputs
in a SAM design, the concept of horizontal
cascading may be used. Similarly, if greater
control store (microcode) depth is required,
multiple SAM devices may be vertically
cascaded, sharing a common control output
bus. Both cascading approaches may be
simultaneously used for problems requiring
increased capacity in both dimensions.

following "rules-of-thumb" derived from the
device architecture and specifications are
useful. These guidelines are for single
SAM implementations. Cascaded SAM
configurations may expand output count
and memory depth substantially. For
example, SAM + PLUS supports horizontal
cascading of up to 8 SAM448 devices, for
a total output count of 128 lines!

In order to determine whether a given
application will be suitable for SAM, the

SAM Application
Guidelines

•

Operating frequency up to specified
SAM's Fmax

• Synchronous operation
• Up to eight control inputs (exclusive of
Clock and nRESET)
• Up to sixteen control outputs (single
device)

Microassembler
Input Overview

Shown in Figure 3 is an example of the
structure of a SAM ASM input file. This file
may be created using any standard text
editor. It is important that the text editor is
used in non-document mode in order to
prevent the insertion of any spurious
format control characters which may be
detected by the ASM microassembler
parser at compile time as input errors.
Other than this constraint, input is
essentially free-form and may be structured
for readability and overall clarity.
The case of characters inserted into the
ASM file is significant, so be sure that
case significance is maintained. For
example, the names "RWB" and "rwb"
are not the same.
Comments may be inserted freely into the
source code, delimited by leading and
trailing percent signs (%).
The basic format of a SAM ASM file
consists of the following sections:
[HEADER]
PART
INPUTS
OUTPUTS
[PINS]
[DEFAULT]
[MACROS]
[EQUATIONS]
PROGRAM
END$

• Up to 256 primary microcode locations
• Up to 64 of 256 primary microcode
locations may be multi-way (external
conditional) branches (single device)
• Transition expressions reducible to four
product terms per IF ... THEN expression
Applications which satisfy this list will in all
likelihood fit into a single SAM device.
Those sections noted within brackets are
optional and may be omitted if not required.

Header
The HEADER contains user-specified
design identifier information. It may
include design title, designer's name, date,
revision information, etc.

Part
The PART section of the ASM file specifies
the target SAM device or devices the
application is intended for. By specifying
AUTO, the user permits the SAM+PLUS
software to pick the optimal device or set
of devices for the application based upon
minimal pin count. Multiple devices may
be invoked for designs requiring a larger
number of total outputs than a single SAM
device can supply, i.e., the SAM+PLUS
software supports horizontal cascading
(see SAM Data Sheet) of devices at a
source code level. This cascading
capability may be invoked by utilizing
AUTO with a design requiring high output
count as noted, or may be explicitly
defined by supplying a list of devices after
PART which the design is to be fitted into.
As shown in the example below, two
SAM448 devices are going to be used in
this application, and have been explicitly
entered. Devices may be cascaded
horizontally up to a width of 128 outputs in
a single source code listing and simulated

WAFERSCALE INTEGRATION, INC.

4·107

SAM448 - Application Note 003

Microassembler
Input Overview
(Cont.)

as one large virtual SAM. Separate JEDEC
files are generated for each device to
support programming devices when design
is complete.

Inputs
The single INPUTS section of the ASM file
defines all external inputs into the design,
as well as any required user pin
assignments. Pin assignments are specified
by the format input_name @ pin_number.
Note that since in a horizontally cascaded
design all design inputs must be common,
there will never be more inputs specified
in a source file than are available in a
single SAM device.
Only user-defined inputs should appear in
the INPUTS section: the CLOCK and
nRESET inputs to SAM, being fixedfunction pins, should not be included.

Outputs
The OUTPUTS section(s) of the ASM file
contains a list of all outputs from the
design as well as any pin assignments.
Pin assignment syntax is similar to input
pin assignments. If multiple SAMs are
specified in the PART: section of the
design file (horizontal cascading), there
will be multiple OUTPUTS sections in the
ASM file, one for each SAM component. If
AUTO parts selection is used for a
cascaded design, a single OUTPUTS
declaration may be used to specify all
required outputs. At compile time, outputs
will be assigned to the various devices
automatically.
Output names must be unique across all
OUTPUTS section declarations.
AUTO parts selection may not be used in
conjunction with user-defined pin
assignments.

Pins
The PINS section allows mapping of
external variable names onto internal
variable names for convenience. For
example, a user may have an active-low
signal in his system he has called IWR
which enters into his transition
specifications in his SAM design. To keep
the logical sense of such specifications
clear, it is wise to transform all active-low
external signals into equivalent active-high
names internally, e.g., IWR = WRint.

4-108

WAFERSCALE INTEGRATION, INC.

Default
The DEFAULT section allows the
specification of a default output combination
to be used whenever the output string is
not explicitly defined in an instruction. In a
single SAM device specification the syntax
is simply DEFAULT: [00 ... On], where 00
through On represents a binary string
corresponding to the n outputs specified
for the SAM design. Default output values
are matched to output pins in the order
they appear in the OUTPUTS declaration.
If multiple OUTPUTS sections appear in a
cascaded SAM application, the DEFAULT
specifier is increased in width to
accommodate this change as shown in the
example. Only one DEFAULT section may
appear per ASM file.

Macros
The MACROS section allows the user to
define string equivalences to be substituted
universally throughout his ASM source
code listing. For example, the user may
wish to redefine instruction mnemonics for
efficiency or clarity, or may wish to redefine
binary output strings with alphanumeric
labels. For example,
REG1TOALU = "0101111001100000"
The left hand side of this expression is
undoubtedly easier to remember and type
repeatedly into a listing than the right.
Imbedded strings are not macro substituted.
Macro instances must be delimited by
white space to be recognized. For example,
if a macro substitution is defined as
REG = "0110"
the string 0110 would be substituted into
[REG ALU OP) CONTINUE;
but not into
[BREG4 ALU OP) CONTINUE;

Equations
The EQUATIONS section of the ASM file is
available for the definition of intermediate
equations to be used later in the design.
Entry of transition specifications may be
eased by defining intermediate variables
initially, and then invoking them during the
design. For example,
EventClk = 11 */14 + 13*16*/17
might be defined in the EQUATIONS

SAM448 - Application Note 003

Microassembler
Input Overview
(Cont.)

section, and then utilized later in an
IF ... THEN ... ELSE statement or
statements, such as
IF EventClk THEN [ ] JUMP START;

Program
The PROGRAM section of the ASM file
actually specifies the sequence of
instructions to be executed and associated
outputs required from the SAM device.
The format of a basic instruction
specification in the PROGRAM section is
label: [output-spec] opcode;
label is an optional alphanumeric string
which may be used to identify the
instruction in branching expressions, etc.

END$

Multi·Way
Branch Syntax

[output-spec] represents an actual numeric
string of the correct length (in either binary,
hexadecimal or decimal notation), a Macro
substitution with numeric equivalence (as
defined above), or the special character Z
which signifies tri-state output pins.
Hexadecimal and decimal strings are
defined by a string of valid digits of correct
length, followed by H or D respectively. In
horizontally cascaded applications, all
outputs are specified in the single outputspec within brackets. The output-spec
defined in the DEFAULT statement will be
utilized whenever the output-spec has
length zero, i.e., [] implies default
output-spec.

Every SAM ASM source file must
terminate with the END$ terminator.

The syntax for multi-way branching within
the SAM ASM source file is by way of a
complex expression of the form

another, it is possible to trade-off product
term counts for number of multi-way
branch destinations. For example, it is
perfectly valid to enter

IF (expression1) THEN (instruction1)
ELSEIF (expression2)
THEN (instruction2)
ELSEIF (expression3)
THEN (instruction3)
ELSE (instruction4)

IF (expression1) THEN [ ] JUMP START;
ELSEIF (expression2) THEN [ ) JUMP START;
ELSEIF(expression3)THEN [ ]JUMP NEXT1;
ELSE [ ] JUMP NEXT2;

For example, a complex instruction of this
type might look like
IF 10*11*15*/17 + 13*14 + 16*/10 + 113*/11 THEN
[1111001110010000] CALL
label1 RETURNTO label2;
ELSEIF 13*/12 + 15*16 + 110*14*11 THEN
(1011000011100011) LOADC
255 GOTO label3;
ELSEIF 14*16*10 THEN [ ) PUSH 15
GOTO label4;
ELSE (1111111100000001) PUSHI
GOTO label5;
Each expression may be a function of any
of the eight SAM external inputs containing
up to four product terms.
If more than four product terms are needed
to define a transition from one state to

Here, expression1 and expression2 could
each be four product term expressions,
resulting in eight product terms which can
be used to specify the transition to START.
Note the inherent priority scheme in the
above statements. The SAM architecture
physically implements such a priority
scheme in the Branch Control Block: the
first occurrence of a valid expression
results in the execution of the corresponding
instruction. If the first three expressions
are all false, then instruction4 will be
subsequently executed.
Up to 64 such IF ... THEN ... ELSE
constructs may be implemented in a single
SAM program, along with 192 conventional
instructions without IF ... THEN ... ELSE.
The result is a total microcode memory
capacity of (64 x 4) + 192 = 448 words.

WAFERSCALE INTEGRATION, INC.

4-109

SAM44B - Application Note 003

Figure 3.
Circle Drawing
Routine

This Is the Circle Drawing Design

% Circle Drawing Routine for SAM %
PART: SAM448 SAM448

% SAM Control Output Lines
% A & B Fields (2901)
- 8
% 10- I 8 (2901)
- 9
% OE (2901)
- 1
% Done
- 1
% Cn (2901)
- 1
% Wr
- 1
% ALE
- 1
% Rd
- 1
% RegRd
- 1

Inputs
CO-2
CmdAtt
Sign

INPUTS: CO,Cl,C2,CmdAtt,SIgn

- 3
- 1
- 1

"
""
""
""

OUTPUTS: AO ,Al ,A2 ,A3 ,BO,Bl ,B2 ,B3, 12,11,10,15,14,13,18,17
OUTPUTS: IS,Rd,Wr,ALE,RegRd,OE,Cn,Done
DEFAULT:

[0000 0000 0000 0000 1110 0100]

MACROS:
CONT -

"CONTINUE"

% A & B Fields"
RadlusReg _ '0001"
Regl - "0001"
Reg2 - "0010"
Reg3 - "0011"
Reg4 - "0100"
Reg5 - "0101"
RegS - "0110"
Reg7 - "0111"
Reg8 - "1000"
Reg9 - "1001"
Regl0 - "1010"
Regll - "lOll"
Reg12 - "1100"
% Source Control %

AQ
AB
ZQ
ZB
ZA
DA
DQ
DZ

--=
=

"000"
"001"
·010·

"011"
"100"
'101"
'110"
"111"

% Function %

ADD = '000"
SUBR - "001'
SUBS - '010'
OR = '011'
AND - '100"
NOTRS _ "101"
EXOR - '110"
EXNOR - '1 1 1 '

4-110

WAFERSCALE INTEGRATION, INC.

%

%

%

-----------

- ----

- - - - - ----

SAM448 - Application Note 003

Figure 3.
Circle Drawing
Routine (CDnt.)

% Destination

Control %

QREG _ "000"
NOP - "001"
RAMA _ "010"
RAMF _ "011"
RAMQD - "100"
RAMD _ "101"
RAMQU - "110"
RAMU _ "111"
% Bus Cycle

%

MemWr - "10001"
RegWr _ "10011"
ALEcyc - "11100"
NoCyc _ "11000"
% Mlsc %

en - .,.
nen -

·0·

Done - .,.
nDone -

·0·

EQUATIONS:
PROGRAM:

% Processor Initializes: %
OD:[] JUMP WAIT;
% 0 Load Coloreg, Radius, XO, YO %

% 0 Issues DraWClrc Command
WAIT:

%

IF CmdAtt·CO'·Cl'·C2' THEN [ ] JUMP DOlT ;
ELSE [] JUMP WAIT

% Move parameters from buffer to 2901 Internal registers %
% Radius -> Regl (Y) %
DOlT:

[ Regl Regl AQ ADD NOP RegWr nCn nDone ] CONT
[ Regl Regl AQ ADD NOP RegWr nCn nDone ] CONT ;

% XO -> Reg2 %

[ Reg2 Reg2 AQ ADD NOP NoCyc nCn nDone
[ Reg2 Reg2 AQ ADD NOP RegWr nCn nDone
[ Reg2 Reg2 AQ ADD NOP RegWr nCn nDone

CONT
CONT
CONT

% YO -> Reg3 %
[ Reg2 Reg2 AQ ADD NOP NoCyc nCn nDone
[ Reg3 Reg3 AQ ADD NOP RegWr nCn nDone
[ Reg3 Reg3 AQ ADD NOP RegWr nCn nDone

CONT
CONT
CONT

% Load constants to 2901 registers %

%

o

->

Reg" (X) (AND 0 & anything gives 0) %
[ Reg" Reg" ZB AND RAMF NoCyc nCn nDone ] CONT

WAFERSCALE INTEGRATION, INC.

4-711

SAM448 - Application Note 003

Figure 3. Circle
Drawing Routine
(Cont.)

% 3

->

Reg5 (d) %
In Reg5 %

% Put • l '

[ Reg4 Reg5 ZA ADD RAMF NoCyc Cn nDone ] CONT

% Shift Reg5 Up one to give 2 %
Reg5 Reg5 ZB ADD RAMU NoCyc nCn nDone ] CONT
% Whl Ie we have It, preload 2 Into Reg9 %
Reg5 Reg9 ZA ADD RAMF NoCyc nCn nDone ] CONT
% Increment Reg5 to get 3

(whewl I) %

[ Reg5 Reg5 ZA ADD RAMF NoCyc Cn nDone

CONT

% 6 -> Rega (const) - Just shift 3 up one! %
% Load 1 In CREG to set-up for next Instruction %
[ Reg5 Rega ZA ADD RAMU NoCyc nCn nDone ] LOADC 10
% 10 -> Reg9 (const) %
% Start by shifting Reg9 (now contains 2) up twice to get a %
% Reg6 (Temp register) %
ClrcPlx:

[ Reg4 Reg6 ZA ADO RAMF NoCyc nCn nOone ] CONT ;
Reg1 Reg11 ZA ADO RAMF NoCyc nCn nOone ] CALL TRANS

% Reflect X to -X %
Reg4 Reg6 ZA SUBS RAMF NoCyc Cn nOone ] CONT ;
Reg1 Reg11 ZA ADO RAMF NoCyc nCn nOone ] CALL TRANS
% Swap X & y %
[ Reg1 Reg6 ZA ADO RAMF NoCyc nCn nOone ] CONT ;
[ Reg4 Reg11 ZA ADO RAMF NoCyc nCn nOone ] CALL TRANS
% Swap -X & y %
[ Reg4 Reg11 ZA SUBS RAMF NoCyc Cn nOone ] CONT ;
[ Reg1 Reg6 ZA ADO RAMF NoCyc nCn nOone ] CALL TRANS
% Reflect Y %
[ Reg1 Reg11 ZA SUBS RAMF NoCyc Cn nOone ] CONT ;
[ Reg4 Reg6 ZA ADO RAMF NoCyc nCn nOone ] CALL TRANS

% Swap -Y & X %
[ Reg1 Reg6 ZA SUBS RAMF NoCyc Cn nOone ] CONT ;
[ Reg4 Reg11 ZA ADD RAMF NoCyc nCn nOone ] CALL TRANS
% Reflect -X, -y

%

Reg4 Reg6 ZA SUBS RAMF NoCyc Cn nOone ] CONT ;
Reg1 Reg11 ZA SUBS RAMF NoCyc Cn nOone ] CALL TRANS

4-112

WAFERSCALE INTEGRATION, INC.

SAMUS - Application Note 003

Figure 3. Circle
Drawing Routine
(Cont.)

" Swap -x & -y

"

[ Regl Regs .ZA SUBS RAMF NoCyc Cn nDone ] CONT ;
[ Reg4 Regll ZA SUBS RAMF NoCyc Cn nDone ] CALL TRANS
[] RETURN;
" This routine Translates relative to xO,yO and runs the memory
update cycle"
TRANS:

[ Reg3 Regll AB ADD RAMF NoCyc nCn nDone ] CONT ;
Reg2 RegS AB ADD RAMF NoCyc nCn nDone ] LOADC 100
Regll Reg12 ZA ADD RAMF NoCyc nCn nDone ] CONT ;

" Multiply y by 1024 "
MULT1024:

Regll Regll ZA ADD RAMU NoCyc nCn nDone
LOOPNZ MULT1024

" Subtract y to get effective multiply by 1023 "
Reg12 Regll AB SUBR RAMF NoCyc Cn nDone ] CONT

DONE1024:

" Calculate address"
[ RegS Regll AB ADD RAMF NoCyc nCn nDone ] CONT
" Write pixel
RUNBUS:

In buffer RAM"

[Regll Regll ZA ADD RAMF ALEcyc nCn nDone ] CONT ;
[ Regll Regll ZA ADD RAMF Memwr nCn nDone ] RETURN;

ENDS
SHIFTRS:
"

[ RegS RegS ZA ADD RAMU NoCyc nCn nDone ]
LOOPNZ SHIFTRS ;

Increment RegS twice to get 10 "
[ Regs RegS ZA ADD RAMF NoCyc Cn nDone
[ RegS RegS ZA ADD RAMF NoCyc Cn nDone

CONT
CONT

" Initializing done I - Begin algorithm"
"d - 3 - 2*radlus Initially"
[ Regl Rege ZA ADD RAMU NoCyc nCn nDone
[ Reg5 Rege AB SUBS RAMF NoCyc Cn nDone
"

CONT
CONT

If x >- y branch to finish up "

OUTERLOOP: [ Reg4 Regl AB SUBS RAMF NoCyc Cn nDone ] CONT
IF Sign THEN [] JUMP DrawEnd ;
"Write plxela, translate origin & reflect to al I octants"
ELSE [] CALL ClrcPlx
" Test d sign,

If >_ 0, use POS "

[ Reg5 Reg5 ZA ADD RAMF NoCyc nCn nDone ] CONT
IF Sign THEN [] JUMP POS ;

WAFERSCALE INTEGRATION, INC.

~--------

----

---~~-~~-~-~-~

-~---~--~~--------

4-113

SAM44B - Application Note 003

Figure 3. Circle
Drawing Routine
(Cont.)

% compute d - d + 4°x + S %
% First 4 0 x %
ELSE [ Reg4 RegS ZA ADO RAMU NoCyc nCn nDone 1 CONT
RegS RegS ZA ADO RAMU NoCyc nqn nDone 1 CONT ;
% Add S %
RegS RegS AB ADO RAMF NoCyc nCn nDone
RegS Reg6 AB ADO RAMF NoCyc nCn nDone

CONT ,
JUMP IncX

% Compute d - d + 4°(x-y) + 10 %
% First x-y %
[ Reg1 RegS ZA ADO RAMF NoCyc nCn nDone 1 CONT ;
Reg4 RegS AB SUBS RAMF NoCYc Cn nDone 1 LOADC 10

POS:

% Then 4°(x-y) "
RegS RegS ZA ADO RAMU NoCyc nCn nDone 1
LOOPNZ SHIFTRS ;

SHIFTRS:

% Add 10 %
Reg9 RegS AB ADO RAMF NoCyc nCn nDone
RegS Reg6 AB ADO RAMF NoCyc nCn nDone

CONT
CONT

% Decrement y %
[ Regl Regl ZA SUBR RAMF NoCyc nCn nDone 1 CONT
% Increment X
IncX:

and repeat til X - Y %

[ Reg4 Reg4 ZA ADD RAMF NoCyc Cn nDone 1 JUMP OUTERLOOP

% Last pixel write / ends octant with x - Y (45 degrees) %
DrawEnd:

[] Call ClrcPlx ;
[1 LOADC lSD ;

% Issue Done to processor for lS clocks %
DoDone:

Regl Regl ZA ADO RAMF NoCyc nCn Done ]
LOOPNZ DoDone ONZERO WAIT;

%'End Main Routine %
% This routine reflects the pixel Into all octants and cal Is
routine which translates the pixel relative to xO,yO,
calculates the pixel address as addr - x + yOl023 and runs the
memory cycle. %

4-114

WAFERSCALE INTEGRATION, INC.

a

SAM448 - Application Note 003

SAM
Microassembler
Opcodes

The basic SAM device instruction set
accessible by the user through the
microassembler consists of:

PUSHLOADC (constant1) GOTO (labeI1)
CREG value is pushed onto the Stack
and CREG is reloaded with constant1.

CONTINUE
Execute next sequential instruction

PUSHI GOTO (labeI1)
The eight input lines are pushed onto
the Top-of-Stack and the instruction at
label1 is subsequently executed. May
be used to implement a "dispatch"
function in conjunction with a
subsequent RETURN instruction:
external inputs provide address of
next SAM instruction.

JUMP (labeI1)
Jump to instruction specified @ label1
LOOPNZ (labeI1) ONZERO (labeI2)
If Count Register (CREG) is zero,
execute instruction @ label2, else
decrement CREG and execute
instruction @ label1. Useful for oneinstruction timing and delay loops.
DECNZ GOTO (labeI1)
Decrement the CREG if non-zero;
execute instruction @ label1.
POPC GOTO (labeI1)
Top-of-Stack is popped into CREG and
the instruction @ label1 is executed.
POPXORC (constant1) GOTO (labeI1)
Top-of-Stack is popped, bitewise XORed
with (constant1) and loaded to CREG.
Instruction @ label1 is next executed.
Useful for comparing Top-of-Stack to a
value by subsequently testing CREG
zero-flag using a LOOPNZ instruction.
LOADC (constant1) GOTO (labeI1)
CREG is loaded with the value
constant1, and instruction @ label1 is
next executed.
RETURN
Address of the next instruction is
popped from Top-of-Stack and
subsequently executed. Used to
terminate subroutines.

An Actual
Design Example

Now that the basic syntax and elements of
a SAM ASM file have been covered, a
detailed example of a SAM application will
be presented: a high-performance Graphics
Controller. In this particular application,
two SAM devices will be horizontally
cascaded to generate the control outputs
for a graphics subsystem. This subsystem
provides graphics primitive drawing
capability for a larger microprocessorbased system.
Figure 4 shows a typical 8086
microprocessor-based system. Beneath the
Address/Data Buses is the graphics
subsystem to be controlled by the SAM
devices, the primary elements of which are

ANDPUSHI (constant1) GOTO (labeI1)
The eight input lines are bitwise
ANDed with constant1, the result is
pushed onto the Stack and the
instruction @ label1 is subsequently
executed. May be used to mask inputs
before loading to CREG or next
address.
CALL (labeI1) RETURNTO (labeI2)
Label2 is pushed onto the Stack, and
the instruction @ label1 is executed
next. Used for subroutines.
PUSH (constant1) GOTO (labeI1)
Constant1 is pushed onto the Stack
and the instruction @ label1 is next
executed.
The Branch Control Block of SAM is
invoked automatically by use of
IF ... THEN ... ELSE constructs in
conjunction with the above
instructions. This allows program flow
control based upon external inputs as
in conventional state machines and
multi-way branching in a single clock.

a 1 Megabyte high-speed static RAM video
frame buffer (giving individual pixel
addressing capability), five WS5901 bitslice elements used to construct a 20 bit
ALU/data path engine, and two SAM
devices as previously mentioned to provide
overall control within the subsystem.
This basic graphics engine represents a
user-microcodeable arrangement which
can potentially support many primitive
graphic drawing operations such as line
drawing, polygon filling, drawing of conic
sections and others. For the purposes of
this example, a single primitive drawing
operation which draws circles of arbitrary
radius and origin into the frame buffer will

WAFERSCALE INTEGRATION, INC.

4·115

SAM448 - Application Note 003

An Actual
Design
Example
(Cont.,

be discussed. The basic concept behind
this algorithm will be discussed below.

• Reflect circle pixel coordinates into
remaining seven octants

In order to execute its role of controller for
this subsystem, the pair of SAM devices
must be able to execute the following
subfunctions

• Translate pixel coordinates relative to
actual origin

• Read Commands issued by main
microprocessor

This activity is done independently of the
main microprocessor and frees it up to do
other tasks while the operation is performed.

• Perform Video Buffer write to all pixel
addresses specified
• Issue DONE interrupt to main processor

• Transfer Parameters associated with
commands to Register File in WS5901's
• Initialize Constant Registers in WS5901's
to specified values for algorithm
• Compute values for pixels on circle as
function of specified Radius for first
octant [Assume circle origin = (0,0)]
• Translate x,y coordinates into RAM
addresses

These operations fall into two general
categories of controlling bus transfers
between various elements (Registers, ALU,
RAM, etc.) and sequencing computations
performed by the WS5901 ALU in generating
the pixel addresses to be set to draw the
required circle. The structure of the SAM
microassembler code shown above
generally follows this flow.

Figure 4.
SAM448
Graphics Engine

SYSTEM ADDR BUS

20
SYSTEM DATA BUS

18

DONE

REGRD

SAM #1

SAM #2
CK

4·116

WAFERSCALE INTEGRATION, INC.

SAM448 - Application Note 003

Circle Drawing
Algorithm
Overview

The sample algorithm to be implemented
in the SAM code to draw the circle is one
based upon a methodology developed by
Bresenham. In order to speed computation,
it exploits the fundamental symmetry of a

circle, by calculating the circle points in
the first octant (see Figure 5), and then
reflecting those coordinates into the other
seven octants. For a given pixel location
(x,y) , reflection involves drawing points

Figure 5. Circle
Symmetry
Exploited by
Bresenham

(y,x)

(-y,x)

(y,-x)

(-y,-x)

(-x,-y)

(x,-y)

Figure 6. Circle
Drawing
Algorithm

Procedure Circle (radius, value:
var x.Y,d :

Integer)

Integer ;

begin
X :- 0

;

Y
raduls;
d :- 3 -2 • radius
while x

<

Y do begin
ClrcleDraw (x,y.value);
If d

<

0

then d :- d + 4 • + 6
else begin
+ 4 •

d

:- d

y

:- y -

(x-y) + 10

end
X

:- X +

1

end
If x - y then ClrcleDraw (x,Y. value)
end

WAFERSCALE INTEGRATION, INC.

4·117

SAM448 - Application Note 003

Circle Drawing
Algorithm
Overview
(Cont.)

(-x ,y) , (x.-y) , (-x.-y), as well as those points
with x and y swapped. In drawing the
points for a circle in the first octant, one
can easily see that, having just calculated
one of the pixel locations, there are only
two possible choices for the next pixel
location: increment x (horizontal move) and
increment x and y (diagonal move). The
trick is how to decide, based upon current
location, which of the two to pick next.
The entire derivation of the algorithm will
not be presented here. However, a

Timing
Considerations

The basic algorithm implemented is shown
in Figure 6.

SAM timing analysis is straightforward, as
all times are relative to the synchronous
clock input. Tsu specifies minimum set-up
time for inputs to gain recognition at the
next clock edge, while Tco specifies clockto-output delays for the user-configured
output pins. Output tri-state and enable
times are speced as Tcz, but are not
relevent in this particular application as
outputs are always enabled.
For this particular design example, the
SAM448-25-controlled graphics subsystem
is being driven by a 15 MegaHertz clock.
This implies a clock period of 66
nanoseconds. SAM control outputs will
reflect a Tco of approximately 18
nanoseconds, while inputs must obey a

Figure 7.
Primary SAM WSS901 Graphics
Controlled Timing
ow'"
SAM OUTPUTS

3

~

complete discussion of the algorithm may
be found in Foley and Van Dam (1981),
referenced below. Suffice it to say, it is
obvious that the best match between
actual pixel coordinates and the ideal
circle points can be obtained by checking
an error term equal to the difference in
distance from the circle's center to each of
the two potential next pixel choices: the
sign of the term will indicate which point to
pick to obtain the best fit.

)

18 nanosecond set-up time (Tsu) relative to
the clock edge.
High-speed Static RAM will be used for
the video frame buffer for two reasons:
one is raw speed. The memory must be
fast enough to keep up with SAM's highspeed bus cycles. The second is that
SRAM requires no refresh cycles, unlike
DRAM. Thus more time is available to
perform buffer drawing functions: no time
is lost for refresh cycles.
Memory consists of CMOS SRAM
components organized 8K x 8 with an
access time of 45 nanoseconds, and a
minimum Write Pulse width of 30
nanoseconds. The CMOS WS5901 bit-

i
:}

~~:X

---'f

PREG OE _ _ _

A, B OUTPUTS

PREG DATA

1

X

X
\

WR

WS5901 OUTPUTS

4-118

WAFERSCALE INTEGRATION, INC.

~

SAM448 - Application Note 003

Timing
Considerations
(Cont.)

slices require a 30 nanosecond
propagation delay from A and B Register
Address inputs to valid Y output, and a 10
nanosecond set-up time prior to the Clock
high-to-Iow transition on A and B inputs. A
timing diagram is shown in Figure 7.
The bus cycle uses a two clock approach.
During the first cycle, the WS5901 will
generate a pixel address to be set, and
during the second cycle, the actual write
pulse will be generated by SAM to write
the frame buffer.
Operations performed entirely within the
WS5901 slices (register transfers, ALU
operations, etc.) are all executed in a

Example Program
Listing

Figure 3 is a source listing of the basic
circle drawing process. The following
comments are worth noting before going
further:

The algorithm below uses many of the
WS5901's operations, as well as many of
the internal addressing modes. In the
following listings, standard mnemonics
have been used for the various Source,
Destination, and Operation specifiers.
These control lines for the WS5901's are
all generated by the SAM devices. These
mnemonics, and resulting WS5901
functions, may be found in the WSI
WS5901 Data Sheet.

functions utilize the Stack and
subroutining resources on SAM.
• Since the display is assumed to be
1024 x 1024 pixels, x and y pixel
coordinates must be converted to SRAM
address locations by multiplying the
y coordinate by 1023 and adding the
x coordinate.

• Two SAM devices are used in a
horizontal cascade configuration.
• Extensive MACRO definitions to ease
design entry and allow the use of userand WS5901-specified mnemonics.

Compiling the
Design

single clock cycle. Note that Carry
Lookahead circuitry is employed with the
WS5901 slices to improve arithmetic
computation times, but is not explicitly
shown in the block diagram.

• Two subroutines, CircPix and Trans, are
invoked multiple times to draw the circle
pixels. CircPix reflects the pixels into all
octants of the circle as mentioned
above, while Trans translates the pixels
relative to the actual circle origin and
runs the memory update cycle. These

• The signal CmdAtt is an input to the
SAMs from the main processor, signaling
that all parameters are loaded to the
Parameter Registers, and that a circle
drawing operation should be executed.
Donelnt is a signal from SAM to the
processor, asserted when the drawing
operation is complete.

By convention, microassembler source
files are given the extension .ASM. This
file is called CIRC.ASM. Compilation of
this design involves invoking the
SAM+PLUS software and specifying ASM
microassembler input format. A variety of
runtime options for SAM+PLUS are
available, which provide special reporting
modes and logging simulation input and
output to a special file. For detailed
descriptions of the SAM+PLUS user
interface and options, see the SAM+PLUS
User's Manual. Compilation is an automatic
process resulting in the generation of
programming "object code" for the EPLD
and EPROM blocks on SAM. In this case,
two programming files wil be generated,
since two devices are required to implement

the design. These two files are given the
extensions .JD1 and .JD2 to distinguish
them. TheseJEDEC files are not intended
to be user readable (as with any object
code). Functional simulation uses these
programming files for its modeling of SAM
operation. An additional product of the
compilation is a single Report file
(extension -.RPT) which describes the
resources which have been used in the
SAM devices, pin assignments which have
been selected and absolute locations
within SAM's microcode assigned to the
instructions entered. Figure 8 shows key
portions of the CIRC.RPT report file.
Notice the assigned pinouts for the two
devices, as well as the substitution of
absolute addresses for logical labels.

WAFERSCALE INTEGRATION, INC.

4-119

SAM448 - Application Note 003

Figure 8. Report
File for Circle
Drawing Routine

SAM Design Processor Uti I Izatlon Report
Version 1.01 7/28/87 01:57:09 38.1
***** Design Implemented successfully
.X:7
This Is the Circle Drawing Design

% Circle Drawing Routine for SAM %
SAM448
RESERVED
Gnd
Gnd
Gnd
CO
CLOCK
Vcc
nRESET
Cl
C2
CmdAtt
Sign
RESERVED
RESERVED

.---------------.
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

16
15

SAM448
RESERVED
RESERVED
RESERVED
16
Rd
Wr
ALE
GND
RegRd
OE
Cn
Done
RESERVED
RESERVED

AO
Gnd
Gnd
Gnd
CO
CLOCK
Vcc
nRESET
Cl
C2
CmdAtt
Sign
17
18

.---------------.
1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Al
A2
A3
BO
Bl
B2
B3
GND
12
11
10
15
14
13

***** DESIGN LISTING
PART:
SAM448 , SAM448
INPUTS:
CO, Cl, C2, CmdAtt, Sign
OUTPUTS:
AO, A1, A2, A3, BO, B 1, B2, 83,

I 2,

I 1,

I0 ,

OUTPUTS:
16, Rd, Wr, ALE, RegRd, OE, Cn, Done
PINS:
DEFAULT:
[000000000000000011100100J
PROGRAM:
00:
[000000000000000011100100J JUMP WAIT;
1920:
WAIT:
IF CmdAtt • CO' • C1' • C2' THEN
[000000000000000011100100J JUMP DOlT;
ELSE
[000000000000000011100100J JUMP WAIT;
10:
DOlT:
[000100010000000011001100J JUMP 20;
20:
[000100010000000011001100J JUMP 3D;
3D:
[001000100000000011100000J JUMP 40;
40:
[001000100000000011001100J JUMP 50;
50:
[001000100000000011001100J JUMP 60;
60:
[001000100000000011100000J JUMP 70;

4·120

WAFERSCALE INTEGRATION, INC.

I5 ,

I 'I ,

I 3,

I8 ,

I7

SAM448 - Application Note 003

Figure 8. Report
File for Circle
Drawing Routine
(Cont.)

70:
[001100110000000011001100] JUMP 80;
80:
[001100110000000011001100] JUMP 90;
90:
[010001000111000111100000] JUMP 100;
100:
[010001011000000111100010] JUMP 110;
110:
[010101010110001111100000] JUMP 120;
120:
[010110011000000111100000] JUMP 130;
130:
[010101011000000111100010] JUMP 140;
140:
[010110001000001111100000] LOAOC 10 GOTO SHIFTR9;
150:
SHIFTR9:
[100110011000001111100000] LOOPNZ SHIFTR9 ONZERO 160;
160:
[100110011000000111100010] JUMP 170;
170:
[100110011000000111100010] JUMP 180;
180:
[000101101000001111100000] JUMP 190;
190:
[010101100010100111100010] JUMP OUTERLOOP;
200:
OUTERLOOP:
[010000010010100111100010] JUMP 1930;
1930:
IF Sign THEN
[000000000000000011100100] JUMP OrawEnd;
ELSE
[000000000000000011100100] CALL ClrePlx RETURN TO 210;
210:
[010101011000000111100000] JUMP 1940;
1940:
IF Sign THEN
[000000000000000011100100] JUMP POS;
ELSE
[010001101000001111100000] JUMP 220;
220:
[011001101000001111100000] JUMP 230;
230:
[100001100010000111100000] JUMP 240;
240:
[011001010010000111100000] JUMP IneX;
250:
POS:
[000101101000000111100000] JUMP 260;
260:
[010001100010100111100010] LOAOC 10 GOTO SHIFTR6;
270:
SHIFTR6:
[011001101000001111100000] LOOPNZ SHIFTR6 ONZERO 280;
280:
[100101100010000111100000] JUMP 290;
290:
[011001010010000111100000] JUMP 300;
300:
[000100011000010111100000] JUMP IneX;
310:
IneX:
[010001001000000111100010] JUMP OUTERLOOP;
320:
OrawEnd:
[000000000000000011100100] CALL ClrePlx RETURNTO 330;

WAFERSCALE INTEGRATION, INC.

4·121

SAM448 - Application Note 003

Figure 8. Report
File for Circle
Drawing Routine
(Cont.)

330:
[000000000000000011100100]
340:
OoOone:
[000100011000000111100001]
350:
CI rcP Ix:
[010001101000000111100000]
360:
[000110111000000111100000]
370:
[010001101000100111100010]
380:
[000110111000000111100000]
390:
[000101101000000111100000]
400:
[010010111000000111100000]
410:
[010010111000100111100010]
420:
[000101101000000111100000]
430:
[000110111000100111100010]
440:
[010001101000000111100000]
450:
[000101101000100111100010]
460:
[010010111000000111100000]
470:
[010001101000100111100010]
480:
[000110111000100111100010]
490:
[000101101000100111100010]
500:
[010010111000100111100010]
510:
[000000000000000011100100]
520:
TRANS:
[001110110010000111100000]
530:
[001001100010000111100000]
540:
[101111001000000111100000]
550:
MULT1024:
[101110111000001111100000]
560:
OONE1024:
[110010110010010111100010]
570:
[011010110010000111100000]
580:
RUNBUS,
[101110111000000111110000]
590:
[101110111000000111000100]

LOAOC 160 GOTO OoOone;
LOOPNZ OOOone ONZERO WAIT;
JUMP 360;
CALL TRANS RETURNTO 370;
JUMP 380;
CALL TRANS RETURNTO 390;
JUMP 400;
CALL TRANS RETURNTO 410;
JUMP 420;
CALL TRANS RETURNTO 430;
JUMP 440;
CALL TRANS RETURNTO 450;
JUMP 460;
CALL TRANS RETURNTO 470;
JUMP 480;
CALL TRANS RETURNTO 490;
JUMP 500;
CALL TRANS RETURNTO 510;
RETURN;

JUMP 530;
LOAOC 100 GOTO 540;
JUMP MULT1024;
LOOPNZ MULT1024 ONZERO OONE1024;
JUMP 570;
JUMP RUNBUS;
JUMP 590;
RETURN;

ENO$

***** PART UTILIZATION
601192
31 64

Unconditional Branches
Conditional Branches

o Warnings
Fatal errors

o

4·122

WAFERSCALE INTEGRATION, INC.

31 .25">
4.69">

SAM448 - Application Note 003

Design Simulation

Figure 9.
Command File

The SAMSIM functional simulator allows
simulation of single-, as well as multipleSAM designs. Once a design has been
successfully compiled, the user can
specify input stimulus in a variety of
formats and observe the device response.
SAMSIM supports both hard-copy waveform
and tabular output, as well as interactive
"virtual logic analyzer" viewing on the PC
monitor. Split-window, multiple zoom levels,
and delta time display are a few of the
capabilities available for analyzing the
simulation results in this fashion.

SAMSIM supports both interactive and
command file input. Shown in Figure 9 is
a sample input stimulus command file for
this design. Command files are typically
given the design name with extension
.CMD. In this example, CIRC.CMD is the
name of the command file. The first line
specifies the source JEDEC files. Note
only the primary file name is given and
not the extensions. GROUP CREATE
creates a group called CF containing 3
signals (CO-C2). By creating this group,
the input pattern for the group can be

JEDEC CIRC
GROUP CREATE CF - co C1 C2
PATTERN CREATE CF _ (OH)*200
PATTERN CREATE CmdAtt - (0)*5 (1)*2 (0)*193
PATTERN CREATE Sign (0)*200
TRACE CREATE CIRC.TRC
TRACE ON
SIMULATE 200
VIEW

specified in the PATTERN CREATE CF
statement immediately following, rather
than having to enter each signal's stimulus
separately. The PATTERN CREATE
statement shows the sequential values the
given input (or group of inputs) is to take
beginning at the start of the simulation
and continuing onward. Hex format (as
shown) can be used to streamline group
pattern entry further. The notation ( )*n
indicates repeat the enclosed stimulus
pattern n times. TRACE CREATE creates a
trace buffer file CIRC.TRC into which the
state of SAM wil be dumped after each
simulation step. This information includes
internal information such as value on Topof-Stack, counter value, etc., as shown in
Figure 10. TRACE ON turns the trace
process on and may be discontinued with
a TRACE OFF command later in the
command file. SIMULATE 200 specifies a
200 clock simulation is to be run, and
finally VIEW enables interactive viewing of
the results of the simulation when complete.
Other useful commands supported by
SAMSIM, but not used in our example
include (among others):
SET - Modifies values of internal stack,
counter, etc.

RADIX - Defines default radix for all
SAMSIM input. Options are decimal,
binary and hex.
LINK - Logically links device pins for
simulation purposes.
Running SAMSIM with the above
command file gives the output shown in
Figure 11.
In reviewing the simulation output figure, a
few words of explanation are required. It is
immediately apparent that there are two
types of output displayed, two examples of
which are CmdAtt and AF. CmdAtt is an
example of a single signal waveform, in
this case corresponding to a device input.
AF corresponds to a group of four signals
(note the (4) after the name AF) which
includes AO-A3. For AF, the values in the
group are displayed in a vertical hex
notation each time any signal in the group
changes. (If an explicit value is not
displayed, it is the same as the previous
time step's value). By grouping common
signals, much more information can be
displayed in a single screen than might
otherwise be visible. In our example A (AF
= A3-AO), B (BF = B3-BO), and I outputs
(IL = 12-10, 1M = 15-13, IH = 18-16) are
viewing groups which have been formed.

WAFERSCALE INTEGRATION, INC.

4-123

SAM44B - Application Note 003

Figure 10. Trace
File Output

Sign-O OmdAtt-O c2-0 c1-0 cO-O
MULT1024: 550: [122889920] LOOPNZ MULT1024
Sign-O OmdAtt-O c2-0 c1-0 cO_O
MULT1024: 550: [122889920] LOOPNZ MULT1024
Sign-O OmdAtt-O c2-0 c1-0 cO-O
MULT1024: 550: [122889920] LOOPNZ MULT1024
Sign-O OmdAtt-O c2-0 c1-0 cO-O
MULT1024: 550: [122889920] LOOPNZ MULT1024
Sign-O OmdAtt-O c2-0 c1-0 cO-O
MULT1024: 550: [122889920] LOOPNZ MULT1024
Sign-O OmdAtt-O c2-0 c1-0 cO-O
MULT1024: 550: [122889920] LOOPNZ MULT1024
Sign-O OmdAtt-O c2-0 c1-0 cO-O
MULT1024: 550: [122889920] LOOPNZ MULT1024
Sign-O OmdAtt-O c2-0 c1-0 cO-O
MULT1024: 550: [122889920] LOOPNZ MULT1024
Sign-O OmdAtt-O c2-0 c1-0 cO-O
MULT1024: 550: [122889920] LOOPNZ MULT1024
Sign-O OmdAtt-O c2-0 c1-0 cO-O
MULT1024: 550: [122889920] LOOPNZ MULT1024
Sign-O OmdAtt-O c2-0 c1-0 cO-O
MULT1024: 550: [122889920] LOOPNZ MULT1024
Sign-O OmdAtt-O c2-0 c1-0 cO-O
OONE1024: 560: [133135060] CONTINUE
Sign-O OmdAtt-O c2-0 c1-0 cO-O
550: [70210240] CONTINUE ;

The virtual logic analyzer supports
commands which allow the order of
waveforms to be changed interactively,
arbitrary signal groups to be constructed,
among others. An on-line HELP command
gives instant explanations for all commands.
An extremely flexible interactive analysis
tool is the result.
The simulation results shown in Figure 11
correspond to the first 40 or so clocks
after the graphics controller receives a

Conclusion

4-124

The SAM device provides an efficient
solution for sophisticated control problems
such as the graphics controller just
described. SAM's capability is applicable
to a wide range of problems, including
industrial control, graphics and disk

WAFERSCALE INTEGRATION, INC.

CmdAtt signaling the beginning of a circle
drawing operation. The three RegRd
pulses correspond to reading the circles'
radius and x-y origin from the parameter
register. The single OE pulse two-thirds of
the way across the display is the point
where the CircPix routine is first entered. It
is left as an exercise to the reader to verify
the intermediate output values by following
the CIRC.ASM source file.

controllers, programmable sequence
generators and the like. The SAM+PLUS
tool set makes the design, verification and
debug of such designs straightforward.
The combination represents a winning
approach to control design.

SAM448 - Application Note 003

Figure 11.

SAMSIM
Interactive
Output

1:1--_..
..
CmdAll
~L;.!;"'!

__________

AF (4)

~o-o__ooooooooo_

BF (4)

~-O-OO-OOOo__o_OOOO_oOO-­

IL (3)

:0
~

ii
..

~

!;.'

1M (3)
IH (3)

:Il!--l~3-4-5--9__15404132_
~1-)1;-3-45-9589-6-106B~C-

;D!

10:
Po

0000-0-00-0_03434--1_04-1-4-

0-0=====

00 0 - - - 2 - 0
4
0-00-0--0_00-00-0-3-73-7-3-73-13-7--

Rd

Wr

..

ALE
RegRd

OE

.................. ~.1.............. ~ .............................................................J

Range: 1 to 200

References

Name: CIRC

Cycle: 1

Signals: 29

WSI 1990 Data Book
SAM448 Data Sheet
WSI Application Note #4: SAM
Applications Using State Design Entry

J. Foley & A. Van Dam, Fundamentals of
Interactive Computer Graphics, Addison
Wesley, 1981

WAFERSCALE INTEGRATION, INC.

4-125

4·126

WAFERSCALE INTEGRATION, INC.

Programmable System™Device
Application Note 004

WAFERSCALE INTEGRATION, INC.

SAM Applications Using
State Machine Design Entry
Scope of This
Application Note

The SAM
Solution

This Application Note is intended to
acquaint the user with ASMILE (WSI State
Machine Input Language) state machine
language syntax as used for entering
designs into the SAM448. Basic functionality
and syntax is reviewed as well as its use
of SAM internal resources. An application
utilizing ASMILE input in the form of a
68020 Microprocessor Bus Arbiter is
presented. This Application Note provides
illustrations of all basic concepts needed

WSI's SAM (Stand-Alone Microsequencer)
User-Configurable Sequencer Architecture
provides a solution for high-performance
control functions found in typical digital
systems designed today. There have been,
previously, two main approaches used in
the design of high performance state
machine/control functions in digital systems:
Logic Array-based sequencers, and
microcoded designs. Each approach has
presented the designer with a set of
benefits and drawbacks to be considered
when deciding how to implement a
specific application.
Logic Array-based sequencers have been

to execute a SAM design with ASMILE.
For information on microassembler-based
entry of SAM designs, please refer to
WSI's Application Note #3.
The reader is referred to WSI's SAM448
Data Sheet for details concerning device
architecture and performance. A general
knowledge of SAM device architecture is
assumed as background for this
Application Note.

used for very fast state machines of low-tomedium complexity which required few
outputs and relatively simple state flows or
machine "algorithms." Ability to perform
multi-way control branching in a single
clock cycle is a plus for this approach.
Devices such as conventional registered
PLDs are representative of this class.
Product term count limitations, resulting in
the inability to generate complex output
waveforms or state transitions, limits the
utility of this approach when addressing
larger control problems.
Microcoded approaches have been used
for the implementation of complex control

Figure 1.

SAM448 Block

Diagram

MICROCODED ENGINE

PlD

ZERO

NRESET
INPUTS
(8)

BRANCH
CONTROL
lOGIC

MICROCODE
EPROM

448 x 36

BITS
EPlD
768 PRODUCT
TERMS
ClK

OUTPUTS (16)

WAFERSCALE INTEGRATION, INC.

4-127

SAM448 - AppllcatlDR NDte 004

The SAM
Solution (Cont.)

functions, requiring high control output
counts. Until recently, however, the only
mechanism for implementing this approach
has been to glue together an assortment
of bit-slice component building-blocks. In
addition, the approach also did not lend
itself to rapid multi-way branching (a
strength of Logic Arrays), instead being
relegated to a serial test-and-binary-branch
mechanism.

An enhanced vehicle for state machine
implementation really requires a marriage
of these two architectures, to obtain the
high performance, mUlti-way branching
based on real-time inputs characteristics of
Logic Array-based sequencers, while having
the ability to manage complex algorithms
and generate high output counts
characteristic of microcoded approaches.
WSl's SAM448 does exactly this.

SAM+PLUS
System Overview

The versatility of the SAM architecture,
and its applicability to both State Machine
and complex Controller functions, has
necessitated the need for multiple design
input formats. WSl's SAM+PLUS PC-based
Design Software allows the designer to
enter his design in either a high-level state
machine description using WSl's ASMILE
language, or in an efficient microcode
assembler format known as ASM. A block
diagram of this system is shown in Figure 2.
Given these options, the user can employ
the design description most appropriate for
his particular problem, or which he is
personally most comfortable with.

architecture. A Utilization Report is
generated which reports total resources
consumed, any unfittable requests, and
assigned pinouts. Upon successful fitting,
a standard JEDEC file is generated to allow
programming of the device using a hardware
programming card installed in the PC.

The SAM Design Processor (SOP) takes
the input file and automatically minimizes
the transition specification logic and fits
the resultant resource requests to the SAM

Sizing·Up a
Potential
SAM Design

There are two broad categories of state
machines. Mealy and Moore machines
(see Figure 3). Given the SAM architecture,
one can see that Moore machines may
be directly implemented into a SAM
component: SAM's outputs are a function
of the currently addressed microcode
location (state). Mealy machines specify
outputs as functions of state and inputs.
However, Mealy machines can frequently
be converted to equivalent Moore machines.
The general rule for this conversion is that
for each transition into a state in the Mealy
machine with a unique set of outputs,
insert a state into the Moore machine with
that output combination. Figure 4 illustrates
this concept.
ASMILE supports the resources available
on SAM for state machine design. Additional
feaures, such as the stack and counter,
are supported in the microassembler format
which lends itself to their efficient use.
In order to determine whether a given
application is suitable for SAM, a few brief

4-128

WAFERSCALE INTEGRATION, INC.

In addition, this JEDEC file, which represents
the actual template of the specific application
implemented, may be used as input to the
SAMSIM (SAM SIMulator) program which
provides functional simulation capability
integrated into the total design environment.
Hard-copy output of simulation results may
be obtained, as well as on-line "logic
analyzer" viewing capability. The result is
a design entry, compilation and verification
system which can be iterated rapidly until
the desired functionality is obtained.

"rules-of-thumb" derived from the device
architecture and specifications can prove
helpful:
• Operating frequency less than or equal
to specified SAM device's Fmax
• Synchronous, Moore machine operation
• Up to eight state machine inputs (not
including CLOCK or RESET)
• Up to sixteen state machine Outputs
• Up to 64 Multi-Way (conditional) state
branches
• Transition expressions reducible to four
product terms per IF ... THEN
expression
• 192 or fewer unconditional state
transitions
An application which meets the above list
of requirements will probably fit into a
SAM device.

SAM448 - ApplicatiDn NDte 004

Figure 2.
SAM+PWS
System Diagram

II

Figure 3. Types
of Synchronous
State Machines

COMBINATORIAL
LOGIC

STATE
REGISTERS ......---,."

COMB.
LOGIC

OUTPUTS
!(STATE, INPUTS)

INPUTS _ _--,/1

CLOCK - - - - - - - - - - - '
MEALY STATE MACHINE

WAFERSCALE INTEGRATION, INC.

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SAM448 - Application Note 004

Figure 3. Types
of Synchronous
State Machines
(Cont.)

COMBINATORIAL
LOGIC

STATE
REGISTERS

r-----,.,

COMB.
LOGIC

OUTPUTS
f(STATE)

INPUTS

CLOCK - - - - - - - - - '
MOORE STATE MACHINE

Figure 4.
Mealy/Moore
Transformation

X*

v 10

IX*/V 1 0
IX*V + X*IY 11

IX*V + X*/V

x*v 11

MEALV MACHINE

MOORE MACHINE

4·130

WAFERSCALE INTEGRATION, INC.

I0

SAM448 - Application Note 004

ASMILE Entry

Overview

The basic format of a SAM ASMILE file
consists of the following sections:

assignments are optional and will be
assigned by SAM+PLUS if not
specified. Pin assignments are
specified by the format

[Header]
PART
INPUTS
OUTPUTS
[EQUATIONS]
MACHINE
CLOCK
STATES
Transition Specifications
END$

input_name @ pin_number

Outputs
The OUTPUTS section of the ASMILE
file contains a list of all outputs from
the design as well as any pin
assignments. Pin assignment syntax is
similar to input pin assignments.

Those sections surrounded by [ ] are
optional and may be deleted if their use is
not required in a given application.
ASMILE files may be constructed utilizing
any standard text editor in non-document
mode. Using an editor in document mode
may inject spurious format control
characters which will be detected as
syntax error by the ASMILE parser at
compile time. Other than this constraint,
input is essentially free-form and may be
structured for readability and overall clarity.
The case of characters inserted into the
ASMILE file is significant, so it is important
to insure that character case is maintained
as text is entered. For example, the names
"RWB" and "rwb" are not the same.
Comments may be inserted freely into the
source code, delimited by leading and
trailing percent signs, for example,
% This is a comment %

Header
The header contains user-specified design
identifier information. Typical information
includes:

Equations
The EQUATIONS section of the ASMILE
file is available for the definition of
intermediate equations to be used later in
the design. Entry of transition specifications
may be eased by defining intermediate
variables initially, and then invoking them
during the design. For example,
EventClk = 11*/14 + 13*16*/17
might be defined in the EQUATIONS
section, and then utilized later in an
IF ... THEN statement.

Machine
The format for the MACHINE declaration is
MACHINE: machine_name
The MACHINE section of the ASMILE file
actually specifies the state machine's state,
output, and transition definitions required
from the SAM device. There are three
subsections which are to be included:
CLOCK, STATES, and Transition
Specifications.

Clock
The CLOCK subsection specifies the clock
signal which will act as the synchronous
clock source for the state machine and the
resulting SAM device.

Designer's Name
Company
Date
Design Number
Revision
SAM Part Number
Other Comments

States
The STATES section specifies all states in
the target machine, as well as outputs
corresponding to these states. The general
form of this statement, when used in a
SAM design, is

Part
The PART section of the ASMILE file
specifies the target SAM device the
application is intended for.

STATES: [outpuLname_1 ...
output_name_n]
state_name [outpuLvalue_list]

Inputs
The single INPUTS section of the
ASMILE file defines all external inputs
into the design, as well as any
required user pin assignments. Pin

In the above, the output_names are a list
of all SAM output names used in the
design, separated by whitespace. Following
this initial declaration, a list of all

WAFERSCALE INTEGRATION, INC.

4-131

SAM448 - Application Note 004

ASMILE Entry
Overview
(Cont.,

state_names appears, each followed by a
binary string in brackets which specifies all
output values to be provided when the
machine is in that state.

Control logic block. This block allows, by
its structure, the specification of up to 64
complex branching expressions in a single
machine. [As noted above, up to 192
unconditional state transitions may be
specified for a single SAM device]. Each
IF ... THEN expression may specify a
direct branch from the current state to as
many as four other successor states,
based upon inputs to the SAM device.
This is illustrated in Figure 5. Examples
are shown below.

For example,
STATES:
SO
S1
S2
S3

[A B C 0]

[0000]
[0 1 1 0]

[1 000]
[0001]

Specifies a machine with four outputs A
through 0, State So has all outputs low, S1
takes Band C to logic one, S2 has only
output A high, etc.

In specifying IF ... THEN expressions, it
is valuable to note that the order of the
expression is important and can determine
the machine flow. Transition specifications
need not be mutually exclusive in such
expressions. For example, the expression

Transition Specification
The form of the Transition Specifications in
a SAM ASMILE design is
state_name: transition_specification

SO: IF 11*12 + 15 THEN S1
IF 15*16 + 14*/13 THEN S2
IF 14 THEN S3
S4

Every state in the machine must have a
transition_specification which will specify
successor states, either unconditionally
SO: S2

might appear ambiguous under the
condition that inputs 15 and 16 to the SAM
device become true during SO. Is S1 or S2
the next state? At this point SAM's priority
logic comes into play. Since the S1
transition is specified before the S2 in the
design definition, it will be the next state
entered. Similarly, if 14*/13 become valid,
S2 will be the next state entered in
preference over S3. This precedenceresolving capability is provided in the SAM
silicon architecture which employs a
hardware priority encoder in selecting the
next state transition. This capability
resolves conflicts, and may be exploited in
the design to prioritize transitions.

or conditionally using IF ... THEN
statements.
The first state_name encountered in the
Transition Specification section will be
defined as the initial state of the machine
coming out of Reset. As such, it has special
significance. Typically, this might be defined
as an "inactive" or passive machine state.
Other Transition Specifications have no
positional significance.

If • •• Then Statements
The SAM architecture implements in
silicon the state transition specifications
defined by a user in the chip's Branch

Figure 5. SAM
Multi·Way Branch

•
••

SAM MULTI-WAY BRANCH

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WAFERSCALE INTEGRATION, INC.

SAM448 - ApplicatlDn NDte 004

ASMILE Entry
Overview
(Cont.)

Default bnsitions
One other benefit of this approach is the
implicit "default" transition to be made. In
the example above, S4 will be the next
state entered if S1, S2, and S3 are not
selected by the appropriate conditions
being true. This feature can reduce design
effort and resource requirements
substantially, since default transitions are
frequently defined as the negation of nondefault transitions and such inverted
expressions have a tendency to consume
logic product terms or resources quickly.
For example,
SO: IF 11*12 + IS*1I7 + 10 THEN S1
IF 13 + 116*14 THEN S2
IF 12*13*14*ISII7 THEN S3
S4

Each expression (IF ... THEN) may be a
function of any of the eight SAM external
inputs, and may contain up to four product
terms after logic minimization. For most
designs, this should prove ample.
A trade-off between number of branch
destinations and product terms per
destination can be made, as multiple
IF ... THEN expressions can point to the
same destination. For example, the
expression
SO: IF (cond1) THEN S1
IF (cond2) THEN S1
IF (cond3) THEN S2
S3
provides a three-way branch, with up to
eight product terms available for the
specification of transitions to state S1.

is a valid ASMILE SAM transition
specification. If the notion of a default
transition (S4) was not in the ASMILE
syntax, and had to be explicitly defined,
we might have to specify the last transition
as (unminimized)

End$
Every SAM ASMILE source file must
terminate with the END$ terminator.

IF 1(11*12 + IS*1I7 + 10) * 1(13 + 116*14)
* 1(12*13*14*IS*II7) THEN S4

SAM ASMILE
Design Example

To illustrate SAM ASMILE input syntax in a
real example, a 68020 Microprocessor Bus
Arbiter state machine will be examined.
This machine, while not overly complex,
illustrates most of the concepts of
ASMILE entry.
Shown in Figure 7 is a state machine
diagram for the Bus Arbiter. The 68020based system runs at 2S MegaHertz, and
therefore the Bus Arbiter machine must
also run with a 40 nanosecond clock
period. To understand its operation, a
review of the bus exchange protocol used
on the 68020 bus is useful.

In the above flow description, the state
labels SO-S6 designate correspondence
between the operations shown and the
state machine diagram above.
Relating this sequence to the state diagram,
SO represents the "normal," active state of
the processor, S1 and S2 correspond to
the Grant phase, S5 and S6 the
Acknowledge phase, and S3 and S4 the
rearbitration phase if requests are pending
at the end of the current bus exchange.

Three signal lines on a 68020 bus define
the handshake required to arbitrate bus

The Design

exchanges between multiple bus masters:
Request, Grant, and Acknowledge. Given
a bus master which desires access to the
bus, the procedure is as follows (illustrated
in Figure 6):

The file shown below in Figure 8 is the
actual ASMILE file generated for the
machine from the state diagram. It
conforms to the general file outline as
described above. ASMILE source files are
given the extension .SMF (for state
machine file) when generated. In this case,
the file would be 68020ARB.SMF. Note
that in the OUTPUTS and STATES
sections, output variables OSO-OS6 have

been defined which are each valid only
during a unique state. As the design is
simulated, these will give an indication of
which state the machine is at any given
point in time.
To compile this design, the SAM+PLUS
software is invoked, specifying that ASMILE
(and not microassembler) input format is
being used. For a detailed description of

WAFERSCALE INTEGRATION, INC.

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SAM448 - AppllcatiDn NDte 004

Figure 6. 68020
Bus Arbiter
Operation

•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
PROCESSOR

• ASSERT REQUEST

SO
S1

REQUESTING BUS MASTER

&

S2

• ASSERT GRANT
EXTERNAL ARBITRATION (IF REQUIRED)
AMONG MULTIPLE REQUESTS
• WAIT FOR COMPLETION OF CURRENT CYCLE
S6 & S5

• DEASSERTS GRANT
[WAIT FOR ACK TO BE
DEASSERTED]

• NEXT BUS MASTER ASSERTS ACKNOWLEDGE
(ACK)
• NEXT BUS MASTER DEASSERTS
REQUEST

• PERFORM BUS OPERATIONS
• DEASSERT ACK
SO
• RESUME OPERATION OR
S4 & S3

RE-ARBITRATE

Figure 7. Arbiter
State Flow

RAGTX-

4-134

WAFERSCALE INTEGRATION, INC.

BUS REQUEST INPUT
BUS GRANT ACKNOWLEDGE INPUT
BUS GRANT OUTPUT
THREE-STATE CONTROL TO BUS CONTROL LOGIC
DON'T CARE

SAM448 - Application Note 004

The Design
(Cont.)

Figure 8. 68020
Bus Arbiter
State Machine
Input File
(68020ARB.sMF)

the SAM+PLUS user interface and options,
the SAM+PLUS User's Manual should be
consulted. Compilation then proceeds
automatically. Transition equations are
automatically minimized, and "object code"
generated for the EPLD and EPROM
blocks. As a result, JEDEC programming
file (.JED) is generated, as well as a
Utilization Report file (.RPT) reporting the
results of the compilation process. Functional
simulation of the design can be performed
using the .JED file as a design template

as described below. The .JED file is not
intended to be user-readable. The .RPT
file contains valuable information such as
design pin assignments and resource
utilization. Figure 9 shows key portions of
this file. All ASMILE input is transformed
into microassembler format before
subsequent processing, and the equivalent
microassembler code for the design is given
in the .RPT file as well. More information
on the interpretation of this code can be
obtained from the references shown below.

STEVE MCGRAY
WSI, INC.
6118/88

68020 Bus Arbiter for SAM
% This description uses IF ... THEN Transition Speclflcatlons%
PART: SAM448
% Pin Assignments (an option) are made by the designer %
INPUTS: REQUEST ACK82
OUTPUTS: GRANT823 TRISTATE822 OSO OS1 OS2 OS3 OS4 OS5 OS6
NETWORK:
OUT3 - CONF (OUT3,CK,VCC,VCC,VCC)
MACHINE: BUSARBITER
CLOCK: CLK
% STATES gives the output value mapping %
STATES: [GRANT TRISTATE OSO OS1 OS2 OS3 OS4 OS5 OS6]
so [0 0 100 0 0 0 0]
S1 [ 1 1 o 1 0 0 0 0 0]
S2 [ 1 1 0 0 1 0 0 0 0]
S3 [ 1
0 0 0 1 0 0 0]
S4 [ 1
0 0 0 0 1 0 0]
S5 [0
0 0 0 0 0 1 0]
S6 [0
0 o 0 0 0 0 1]
% Transition Specifications follow')(;
SO:
IF REQUEST-lACK THEN S1
IF ACK THEN S5

so
Sl:
S2
S2:
IF
S2
S3:
IF
IF
S3
S4:
S3
S5:
IF
IF
S5
S6:
S5
ENDS

IREQUEST-/ACK

+ ACK THEN S6

IREQUEST THEN S6
REQUEST-lACK THEN S2

REQUEST THEN S4
IREQUEST-/ACK THEN so

WAFERSCALE INTEGRATION, INC.

4·135

SAM448 - Application Note 004

Figure 9. 68020
Bus Arbiter
Design
Report File
(68020ARB.RPT)

SAM Design Processor Uti Ilzatlon Report
Version 1.01 7/28/87 01:57:09 38.1
Design Implemented successfully

.* ...

STEVE MCGRAY
WSI, INC.
3/18/88

68020 Bus Arbiter for SAM

SAM448
RESERVED
ACK
Gnd
Gnd
Gnd
CLOCK
Vee
nRESET
Gnd
Gnd
Gnd
REQUEST
OS6
OS5

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
GRANT
TRISTATE
GND
RESERVED
OSO
OS1
OS2
OS3
OS4

••••• DESIGN LISTING
PART:
SAM448
INPUTS:
REQUEST012, ACK02
OUTPUTS:
GRANT023, TRISTATE022, OS0019, OS1018, OS2017, OS3016,
OS4015, OS5014, OS6013
PINS:
DEFAULT:
[000000000]
PROGRAM:
00:
[001000000] JUMP SO;
1920:
SO:
68020arb.rpt
IF REQUEST * ACK'
[110100000]
ELSEIF ACK THEN
[010000010]
ELSE
[001000000]

4·136

WAFERSCALE INTEGRATION, INC.

THEN
JUMP S1;
JUMP S5;
JUMP SO;

SAM448 - Application Note 004

Figure 9.
68020 Bus
Arbiter Design
Report File
(6802oARB.RPT)
(Cont.)

10:
Sl :
[110010000] JUMP S2;
1930:
S2:
IF REQUEST' +
ACK THEN
[010000001 ] JUMP S6;
ELSE
[ 110010000] JUMP S2;
1940:
S3:
IF REQUEST' THEN
[010000001]
ELSEIF REQUEST
[110010000]
ELSE
[ 110001000]

•

JUMP S6;
ACK' THEN
JUMP S2;
JUMP S3 ;

20:
S4:
[110001000] JUMP S3;
1950:
S5:
IF REQUEST THEN
[110000100]
ELSEIF REQUEST' •
[001000000]
ELSE
[010000010]

JUMP S4;
ACK' THEN
JUMP SO;
JUMP S5;

30:
S6:
[010000010] JUMP S5;
ENO$
••••• PART UTILIZATION
4/192
41 64

o

o

Design
Simulation

Unconditional Branches
Conditional Branches

2,08%)
6,25%)

Warnings
Fatal errors

Integral to the SAM+PLUS design system
is the SAMSIM functional simulator, Once
a design has been successfully processed,
the user can specify input stimulus in a
variety of formats and observe the device
, response quickly and effectively using this
unit-delay simulator, As mentioned above,
SAMSIM supports both hard-copy and
virtual logic analyzer output formats. Splitwindow, multiple zoom-levels, and delta
time display are a few of the capabilities of
this interactive display mode.
SAMSIM supports both interactive and
command file input. Shown in Figure 11 is
a simple input stimulus command file for
our design. Typically command files are

given the design name with the extension

.CMD (for example, 68020ARB.CMD). The
first line specifies the source design
JEDEC (or .JED) file. The next two lines
illustrate logic sequences for the two
machine inputs. The PATTERN CREATE
command allows the user to specify a
sequence of input logic levels to be
applied to the indicated node or nodes.
The notation ( )*n, where n is an integer,
signifies hold the indicated logic value on
the associated input for n clocks.
SIMULATE 41 instructs SAMSIM to run the
simulation for 41 clocks, and finally
interactive display is invoked with the
VIEW command.

WAFERSCALE INTEGRATION, INC.

4-137

SAM448 - Application Note 004

Design
Simulation
(Cont.)

The initial input stimulus applied to the
SAM design shows a straightforward bus
exchange between the 68020 and another
bus master. This corresponds to the first
REQUEST/GRANT/ACK sequence. Upon
detecting a REQUEST, the 68020 asserts
its TRI-STATE line, and issues a GRANT
pulse, allowing the new bus master to
assume control. The alternate bus master
asserts ACK when it detects the fact that
the bus has been granted. When ACK
finally drops, the 68020 knows it can
resume control. The second such sequence
involves not just a single initial REQUEST
(bus master #1), but a second REQUEST
from another bus master (#2) during the
time bus master #1 has control. As a
result, the 68020 must generate a new
GRANT pulse (during S4-S2), and handover bus control to bus master #2 when
bus master #1 is finished (ACK is
dropped). When bus master #2 is finished,
and no requests are pending, the 68020
finally retakes control of the bus (TRISTATE goes low).

Some other representative SAMSIM
commands, while not used in the example,
include:
TRACE - Dumps entire state of machine
(inputs, outputs, internal registers, etc.) for
each clock executed.
GROUP - Specifies logical grouping of
signals for easy observation or input vector
specification.
SET - Modifies values of internal counter,
stack, etc.
LINK - Logically links device pins for
simulation purposes.
RADIX - Defines default radix for all
SAMSIM commands.
Options are binary, hex, and decimal.
Running the SAMSIM simulator with this
command file produces the results shown
in Figure 10. Here, on the PC screen, is
displayed the input stimulus to the SAM
arbiter design, and the resulting state
machine operation.

Figure 10.
SAMSIM
Interactive
Output

1:1

' -_ _ _ xx

REQUEST

n

ACK

~

GRANT

TRISTATE

OSO

OS1

OS2

______ xx

L.U

IT'

L-xx
~

rr

~

____________

~r--n

___~.~.-~n~-----__--_____ xx
'--_______ n

..

OS3

~------------~.~.________~rl

n

OS4

~------------~.~.--------~n

xx

~.+.------~rl

OS5

~xx

n~____~.~.----~n~____~n~------xx

OS6

····························..1. .1············...... ······ ···············t~l·········· ..·························....................................J
RANGE: 1 TO 41

4-138

WAFERSCALE INTEGRATION, INC.

NAME: 68020ARB

CYCLE: 1

SIGNALS: 11

SAM448 - Application Note 004

Figure 11.
SAMSIM
Command File
(68020ARB.CMD)

Conclusion

References

JEDEC 68020AARB
PATTERN CREATE REQUEST PATTERN CREATE ACK SIMULATE 41
VIEW

(0)*3 1 1 1 (0)*12 1 1 1 1 1 0 0 (1)*7 (0)*5
(0)*5 (1)*8 (0)*10 (1)*6 (0)*2 (1)*6 (0)*4

State machine design is a straightforward
process using the ASMILE input language
in conjunction with the SAM device. Design
entry and debug, using functional simulation,
can be readily accomplished at the user's
PC. When the design is debugged and
complete, the SAM component may be
programmed using PC-based hardware
and software in seconds. Should design
errors be detected after in-system test, a
windowed SAM device may be erased, a
design change compiled, and the device
reprogrammed in minutes.

WSI 1990 Data Book
SAM448 Data Sheet
WSI Application Note #3: High-End SAM
Applications Using Microassembler Design
Entry

WAFERSCALE INTEGRATION, INC.

4-139

4·140

WAFERSCALE INTEGRATION, INC.

WAFERSCALE INTEGRATION, INC.

Section Index
Article Reprint

Microprogram an Embedded Controller -

PAC1000 ............................. 5-1

For additional information,
call 800·TEAM·WSI (800·832·6974).
In California, call 800·562·6363.

WAFERSCALE INTEGRATION, INC.

WAFERSCALE INTEGRATION, INC.

5·1

Article Reprint

PACKING ALL THE MAJOR BLOCKS OF A
MICROPROGRAMMABLE SYSTEM, A CMOS IC EASES
EMBEDDED CONTROLLER DESIGNS

CONFIGURABLE CHIP EASES
CONTROL-SYSTEM DESIGN
DAVE BURSKY
nyone who has ever designed a high-performance controller subsyst'm using highspeed
microprogrammed
building
blocks, programmable
logic devices, gate arrays, or discrete logic
realizes the difficulties in integrating
the complete solution. In such a system,
the chip count escalates, the operating
power rises, and the development
schedule lengthens.
By integrating all these functions
and resources onto one high-speed
CMOS chip-the PACIOOO microcontrolier-WaferScale Integration Inc.
has drastically reduced the chip count
from the typically required 50 or so ICs
to just one. At the same time, the
PAClOOO slashes the power consumption from tens of watts to less than 1.5
Wand cuts development time.
The PAClOOO can solve many highend embedded control applications and
is the only available circuit that can
tackle system, data, and event control
tasks. A C-Iike language and PC-hosted
system-development tools simplify the
creation of the control software. Users
can configure the circuit as a microprocessor peripheral or as a standalone
controller to meet the unique requirements of high-performance system,
data, or event controllers. Each of the
chip's two bidirectional16-bit buses, its
individual II 0 lines, and interrupt inputs can, if necessary, be redefined during each 5O-ns instruction cycle.
Repnnted

5·2

w~h

pennossoon from ELECTRONIC DESIGN· October 27. 1988

WAFERSCALE INTEGRATION, INC.

At the heart of the PAClOOO's flexibility lies an internal microprogrammable architecture, including a 16-bit CPU,
a fast 10-bit microsequencer, a 32-wordby-l6-bit register file, and a lkword-by64-bit high-speed EPROM. As product
planning manager Yoram Cedar explains, since the circuit executes any of
its instructions in one clock cycle, the
controller delivers a raw throughput of
Copynght 1988 VNU BUSiness PublicationS, Inc

Article Reprint

COVER: USER·CONFIGURABLE
CONTROLLER
20 MIPS.
Every instruction of the PACI000
can perform as many as three simultaneous operations: program control, CPU functions, and output control, with all possible combinations
allowed. Cedar claims the more powerful instruction format, combined
with the higher clock speed, yields a
five- to tenfold performance improvement, compared with other

one-chip microcontrollers. The high
throughput suits many tasks well. It
has already found homes in radar,
communications, video-graphics,
I/O subsystems, bus and DMA controllers, and disk-drive-controllers.
Besides the CPU, register file, and
sequencer, the chip includes an auxiliary Q-register for double-word operations, an 8-input interrupt controller, 16 output control lines, 8 bi-

THE PAC1DDD
Clock

Host address
Host data bus and data bus

Reset

Register stack

Extended·precision
register for 54·bit
operations

Program counter
CASE logic
User
output

Testlogic

16

User-definable Condition·
output
code
lines
sense
inputs

Intenupt
inputs

I/O lines

Address

1. PACKING A 16-bit micropl'O'
grammable central processor with a 32·
word register file, a l-kword-b~'bit
microcode UV EPROM, sequencer, and
other configurable resources, the
PAC1000 user-configurable
microcontroller from WaferScaie
Integration delivers a raw instruction
throughput of 20 MIPS at 20 MHz (top).
Designers can add or alter various blocks
customize versions for high·volume
(left).

directional I/O lines, scan-test and
CASE program test logic, and a 22bit external address bus (Fig. 1, top).
Also, Cedar emphasizes, the circuitdeals much more rapidly with interrupts than most controllers do,
and that serves embedded control
applications well. The chip changes
program flow in either of two ways.
First, it has four user-definable interrupt illput lines plus four dedicated internal interrupts that require
just 100 ns, at most, to alter the program flow. Second, another set of input lines-22 condition-code inputs
(8 external and 14 internal)-let the
processor alter the program flow
with condition calls and program
jumps in just one 50-ns instruction
cycle.
And if on-chip resources don't
quite match an application's requirements, chip modifications can be
done for large-volume users. The circuit was designed with the company's standard-celllibrary, and many
of the chip's sections are actually
cells in WaferScale's library (Fig. 1,
left). Noticeable on the chip's left
side are the large cells that include
the 64-kbit EPROM block on the bottom and the 16-bit CPU on the upper
left. On the chip's right side, random
logic performs the control and interface functions; small standard cells
are used to create those circuits.
For every instruction, a dedicated
field specifies the bit pattern on the
output lines. Also, designers can individually program eight 1/ 0 lines as
inputs or outputs or to perform special functions under the control of
the chip's mode and I/O registers.
The special functions turn the I/O
lines into control signals that allow
various features and flags to indicate several status conditions. In addition to the eight I/O lines, the circuit has two 16-bit bidirectional buses that go on and off the chip: One
links with the host; the other is the
upper 16 bits of the address/data
bus. Another 16 lines are dedicated,
user-programmable latched output
lines. These can be changed on a cycle-by-cycle basis.
Thanks to all its buses and control
signals, the PACI000 microcontroller operates as either a memory-

WAFERSCALE INTEGRATION, INC.

5·3

Article Reprint

COVER: USER·CONFIGURABLE
CONTROLLER
mapped peripheral to a microprocessor to offload the CPU (Fig. 2a) or as
a standalone controller running
from its own internally or externally
stored program (Fig. 2b). As a peripheral, the chip ties into the host
with a straightforward bus interface-a 16-bit data bus and a 6-bit address bus to access the internal resources of the PAC WOO-and the
standard Chip Select, Read, and
Write control lines. In the standalone
mode, the chip typically runs the application program from its internal
memory and uses its 16-bit output
bus and 8-bit II 0 port to control the
application and communicate to a
host system.
To handle multiple operations in
parallel, the chip internally takes advantage of a long-64-bit-microcode word so that each word can control mUltiple sections of the circuitry. The on-chip microcode storage
area consists of a fast, reprogrammabIe UV EPROM, organized as 1
kword by 64 bits. Since the EPROM
is read only by the on-chip logic, it
doesn't need high-current output
buffers, which slow down the memory access. Thus, the EPROM contents can be read very quickly-the
chip's 20- MHz version accesses
memory in just 30 ns, well within the
CPU's 50-ns instruction cycle time.
The memory is also secure. Users
can program a security bit to prevent
an external system from extracting
the code from the memory array.

Besides its own program memory,
the chip also has a separate address/
data bus that can be programmed for
either 16 or 22 address lines (with 64kword or 4-Mword off-chip addressing ranges, respectively). The address generator for the bus is separate from the sequencer that addresses the program memory. The
PACI000 can therefore execute a
program while it's using the address
bus to move data from memory into
the on-chip register file or to an externally controlled device.
The address bus, in fact, can serve
as a simple direct-memory-access
controller when used with the onchip 22-bit address counter and 16-bit
block counter. This DMA controller
can transfer data from external
memory to the on-chip register file or
to an external device.
An eight-word FIFO register lets
a host microprocessor asynchronously load commands or data into
the controller. The 22-bit word
length in the FIFO register is employed, so that if data values are to
be loaded into the register file, the
lower 16 bits of the 22-bit word sent
over the host data bus represent the
data, and the next five bits-the lower five bits of the host-interface address bus-represent the register location into which the data will be
loaded (RO to R31). The sixth bit of
the host-interface address bus signifies whether the word loaded into the
FIFO register is a command or data

word. If it's a command, the lower 10
bits of the host-data bus are used as a
branch address to one of the 1024
memory locations in the EPROM.
The 10-bit sequencer addresses
the 1,024 words of program memory
and has a 15-level stack that permits
multiple subroutine calls to occur
without forcing the program to go
back to a higher level before calling
the next subroutine. Besides having
more levels in the stack than WaferScale's 5910 microsequencer, the
enhanced sequencer block has a 10bit loop counter that cuts overhead in
programs for loops and nested loops.
The application program can load the
counter with a constant or a value
calculated in the CPU.
Because programming fast, embedded controllers can get complicated, the company includes on-chip
programming and test features to
ease system development. For starters, a 10-bit breakpoint register sim·
plifies real-time debugging. It can be
loaded from either of two sources-a
value stored in a CPU register or a
constant value specified in the program memory. When the program
memory address matches the register contents, the register issues an
interrupt, which a service routine in
memory could then react to.
Test and CASE logic on the chip
also aids program and hardware
testing. The condition-code logic responds to 22 different program test
conditions that can be tested for true

PERIPHERAL OR STANDALONE
Address

I

Mlcloprocessol

'I

Data

Address
MemOlY

L~r~_'"-lJr.rt--jiiiiCl00-_-t-I-'I L--!-:r--l
I

I
I
I
I
I
(8)

I"'"

Host
CPU f-- I
interlace ICt I
Contml
I on 10

P;ph;.1 mode -

I

t...J Status/
-1- - interrupts

Data·path
element,
high.speed
processor,
fast bus, etc.

I

-1-

PACiiioo - -,

.1

I

1

I

I

CPU

I

I

Contml

..L Data

Host and
data
interlace

:

I
: t 1 Conkol
I
IStatus/interrupts
J
L ______ -'
Standalone mode

1 2. MULTIPLE BUSES, AN ON-CHIP ADDRESS GENERATOR,

Memory

Data·path
elemen~

high·speed
processor,
fast bus,etc.

(b)

and sequencer blocks let the microcootroller operate as
a memory-mapped peripheral to offload the host microprocessor (a). Or it can be' operated as a standalone controller (b).

54

WAFERSCALE INTEGRATION, INC.

Article Reprint

COVER: USER·CONFIGURABLE
CONTROLLER

SAMPLE PROGRAM FOR PAC1000 MICROCONTROLLER
/* control memory read/wnte based on ceo "I
segment memeDn .

enmem equ
dlsmem equ
Wf
equ
rd

equ

h'0002'
h'OO4O'
h'OOoo' •
h'1000' •
I

/* output control constants

'/

/* enable memory
/* store begin addr In ADR and loop
fit mc addr by 4 and do rd/wr
/' end loop body

'/
'/
'/
'/
'/

I

s1art
IF ceo •OUT enmem •
FOR6.AOR -RO+Rl.OUTwr.
AOR _AOR+4.0UTrd.
ENDFOR • OUT wr •
ELSE. OUT dlSmem •
ENDIF.
end,

r disable mem ceo
If

IS

not true

1 3, THE HIGH-LEVEL LANGUAGE

developed by WaferScale employs (}
lquage-Iike structures to let designers easily develop complex configuration microcode.

or not-true results. Up to four conditions can be tested simultaneously.
Tests can check for the state of various flags or register contents.
The processor handles two types
of CASE operations: standard and
priority. A CASE group consists of a
combination of four test conditions
that can be tested in a single cycle. In
that same cycle, the PACI000
branches to anyone of 16 locations,
depending on the status of the four
inputs to the CASE group being tested. The priority CASE instruction operates on internal and external interrupt conditions and treats interrupts
as prioritized test conditions. The priority encoder generates a branch to
the highest-priority condition.
Thanks to all its on-chip resources,
the PACl000 is a powerful one-chip
controller, housed in a windowed, 88lead pin-grid-array package or an 84lead ceramic leaded chip carrier. An
84-lead plastic leaded chip carrier
package (the one-time-programmable version) is also available. Because the chip employs an EPROM
to hold the program, revisions to the
code are no more difficult than repro-

gramming a standard EPROM. Prototype systems and production products can benefit from the ability to
revise the code at the last minute.
To alleviate the complexity of microcode program development, WaferScale has assembled a series of
PC-hosted system-development
tools (PAC-SDT). These make the
PACI000 as easy to program as any
one-chip microcontroller. A simple
example of a multiple-command expression in the C-like language lets
designers combine operations such
as FOR6,AOR=RO+Rl,OUT WR
(loop for six cycles, add the contents
of registers RO and Rl and store the
result in the AOR register, output
the value WR) in one word (Fig. 3).
The toolset has a system-entry language, a functional simulator, and a
device programmer (MagicPro). The
system-entry. language software is
the most critical part. The high-level
langnage uses a structure similar to
C's and practically eliminates writing routines in machine or assembly
code. But designers who are more
comfortable working on that level
can write machine-code routines. 0

WAFERSCALE INTEGRATION, INC.

5-5

Article Reprint

WSI Launches
The Programmable System Device:
,

A new class of user-configurable products;
a higher standard in functionality,
integration, and performance.
PSD:™ n Programmable System Device.™
1) A user-configurable system-on-a-chip,
integrating high-performance EPROM, SRAM, and
Logic; 2) User configurable with a menu-driven,
familiar "C"-like language and ffiM-PC®-hosted
system development tools; 3) A standard product
first launched in 1988 by WSI.
WSI's PSIYMProducts: A Major Advance in user-contigurability

System Integration
Level of
Functionality

1988

Not just programmable logic. but programmable logic and memory-programmable systems.

WAFERSCALE INTEGRA170N, INC
"tqJaUoIl,

Programmable S)'$1Cm DeVIce, PSD, and MAPl68 are 1rademaIb of WlI'erSeaJc
Inc
PALlSaregasreredlZ8ClemarkflAdvaK:edMJeroDlMc:es,Inc IBMPCuirepstmedlrlldl=mlrtoCintemallonaI8U11ra5Macbu1C1Ccxponaaon
OCopynghtl988byrafetScalclftlegrabOD,IDcAUqtnarcscncd

WAFERSCALE INTEGRATION, INC.

47280 Kato Road
Fremont, California 94538
800/331-1030, extension 234
In California call:
800/323-3939, extension 234

== ...,..:=:£
.,----r__
I11III
iii====== ====
II' ~

JIll

~~~-

WAFERSCALE INTEGRATION, INC.

Section Index
Package
Information

........................................................................ ~

For additional information.
call 800·TEAM·WSI (800·832·6974).
In California. call 800·562·6363.

WAFERSCALE INTEGRATION, INC.

Package Information
WAFERSCALE INTEGRATION, INC.

Drawing C3

44 Pad Ceramic Lead/ess Chip Carrier (CLLCC)
(Package 1Ype C)

so] l
r- g:~~ so ~ -I
0.644

I

O.350DIA

r

~

0.076
·Pin
No.1
Index

~~~ww~~ww~~·
~

0.095

___)!!I---

+ -----fiiOiiI-....L
0.050

0.008 R (44 PL)

Drawing F3

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(Package Type F)

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WAFERSCALE INTEGRATION, INC.

6-1

Package Information

Package
Information
(Cont.)

Drawing J2

44 Pin Plastic Leaded Chip Carrier (PLoCC)
(Package Type J)

Drawing J3

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WAFERSCALE INTEGRATION, INC.

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Package Information

Package
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WAFERSCALE INTEGRATION, INC.

6·3

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Package
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Drawing QI

100 Pin Plastic Quad Flatpack (PQFP), Gul/wing, Fine Pitch

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6-4

WAFERSCALE INTEGRATION, INC.

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TYP.

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Package Information

Package
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WAFERSCALE INTEGRATION, INC.

6·5

Package Information

Package
Information
(Cont.)

Drawing X1

88 Pin Ceramic PGA
(Package Type X)
1188
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WAFERSCALE INTEGRATION, INC.

Sales Representatives and Distributors

7

Section Index
Sales

Representatives

and Distributors

........................................................................ 7-1

Fo, additional Information,
call BIJIJ.TEAM·WSI (BIJIJ.B32·6974).
In California, call BIJIJ.562·6363.

WAFERSCALE

INTEGRATIO~

INC.

rIll;

Sales Representatives and Distributors

~~~ ~------------------------------------------------------------------------------

WAFERSCALE INTEGRATION, INC.

Domestic
Representatives

ALABAMA

FLORIDA

MINNESOTA

OHIO

Southern Tech. Sales
Huntsville
Tel: (205) 539-4789
Fax: (205) 539-7449

Sales Engineering
Concepts, Inc.
Fort Lauderdale
Tel: (305) 426-4601
Fax: (305) 427-7338

HMR
Minneapolis
Tel: (612) 988-2122
Fax: (612) 884-4768

Giesting & Associates
Cincinnati
Tel: (513) 385-1105
Fax: (513) 385-5069

ARIZONA
Summit Sales
Scottsdale
Tel: (602) 998-4850
Fax: (602) 998-5274

CALIFORNIA
Bager ElectrOnics Inc.
Fountain Valley
Tel: (714) 957-3367
Fax: (714) 546-2654
Bager Elecronlcs Inc.
Woodland Hills
Tel: (818) 712-0011
Fax: (818) 712-0160
Earle Assoc. Inc.
San Diego
Tel: (619) 278-5441
Fax: (619) 278-5443
Criterion
Santa Clara
Tel: (408) 988-6300
Fax: (408) 986-9039
Technology Sales
Kentfield
Tel: (415) 459-2661
Fax: (415) 459-3341

CANADA
Har-Tech Electronics, Ltd.
Toronto
Tel: (416) 665-7773
Fax: (416) 665-7290
Har-Tech Electronics, Ltd.
Montreal
Tel: (514) 694-6110
Telex: 05-822679
Fax: (514) 694-8501
Har-Tech Electronics, Ltd.
Ottawa
Tel: (613) 726-9410
Fax: (613) 726-8834

COLORADO
Waugaman Associates, Inc.
Wheat Ridge
Tel: (303) 423-1020
Fax: (303) 467-3095

CONNECTICUT
Advanced Tech Sales
Wallingford
Tel: (203) 284-0838
Fax: (203) 284-8232

MISSOURI

Sales Engineering
Concepts, Inc.
Altamonte Springs
Tel: (407) 682-4800
Fax: (407) 682-6491

John G. Macke Company
St. Louis
Tel: (314) 432-2830
Fax: (314) 432-1456

Sales Engineering
Concepts, Inc.
Tampa
Tel: (407) 682-4800
Fax: (407) 854-3127

NEW JERSEY

ILLINOIS

S.J. Associates, Inc.
Mt. Laurel, NJ 08084
Tel: (609) 866-1234
Fax: (609) 866-8627

Strategic Sales, Inc.
Teaneck
Tel: (201) 833-0099
Fax: (201) 833-0061

Sieger Associates
Schaumburg
Tel: (708) 310-8844
Telex: 206248
Fax. (708) 310-9530

NEW MEXICO
S & S Technologies
Albuquerque
Tel: (505) 255-5599
Fax: (505) 255-5944

INDIANA
Giesting & Associates
Carmel
Tel: (317) 844-5222
Fax: (317) 844-5861

NEW YORK
Tri-Tech Electronics, Inc
East Rochester
Tel: (716) 385-6500
Twx: 62934993
Fax: (716) 385-7655

IOWA
Gassner & Clark Co.
Cedar Rapids
Tel: (319) 393-5763
Twx: 62950087
Fax: (319) 393-5799

Tri'l"ech Electronics Inc.
Endwell
Tel: (607) 754-1094
Twx: 5102520891
Fax: (607) 785-4557

KANSAS
C. Logsdon & Assoc.
Prairie Village
Tel: (913) 381-3833
Fax: (913) 381-9774

TrI-Tech Electronics Inc.
Fayetteville
Tel: (315) 446-2881
Twx: 7105410604
Fax: (315) 446-3047

MARYLAND
Logical Technology, Inc.
Glen Burnie
Tel: (301) 766-7444
Fax: (301) 760-2054

Tri-Tech ElectrOnics Inc.
Fishkill
Tel: (914) 897-5611
Twx: 62906505
Fax: (914) 897-5611

MASSACHUSETTS
Advanced Tech Sales, Inc.
North Reading
Tel. (508) 664-0888
Fax: (508) 664-5503

MICHIGAN
Giesting & Associates
Livonia
Tel: (313) 478-8106
Fax: (313) 477-6908
Giesting & Associates
Coloma
Tel: (616) 468-4200
Fax: (616) 468-6511

NORTH CAROLINA
Rep, Inc.
MorriSVille
Tel: (919) 469-9997
Twx: 821765
Fax: (919) 481-3879
Rep, Inc.
Charlotte
Tel: (704) 563-5554
Twx: 821765
Fax: (704) 535-7507

Giesting & Associates
Cleveland
Tel: (216) 261-9705
Fax: (216) 261-5624

OREGON
Thorson Company
Northwest
Beaverton
Tel: (503) 644-5900
Telex: 294835
Fax: (503) 644-5919

PENNSYLVANIA
Giestlng & Associates
Pittsburgh
Tel: (412) 828-3553
Fax: (412) 828-5861

PUERTO RICO
G & A Associates
Mllaville, Rio Piedras
Tel: (809) 758-7001
Fax: 809-754-0421

TEXAS
Southwestern
Technical Sales
Dallas
Tel: (214) 369-0977
Fax: (214) 369-2903
Southwestern
Technical Sales
Austin
Tel: (512) 440-0499
Southwestern
Technical Sales
Houston
Tel: (713) 440-9200

UTAH
Butterworth Marketing
West Valley
Tel: (801) 972-5566
Fax: (801) 972-5573

WASHINGTON
Thorson Company
Northwest
Bellevue
Tel: (206) 455-9180
Twx: 9104432300
Fax: (206) 455-9185

WAFERSCALE INTEGRATION, INC.

7·1

Sales Representatives and DistributDrs

Domestic
Distributors

ALABAMA
Schweber Electronics
Huntsville
Tel: (205) 895-0480
ARIZONA
Schweber Electronics
Tempe
Tel: (602) 431-0030
Time Electronics
Tempe
Tel: (602) 967-2000
Wyle Laboratories
PhoeniX
Tel: (602) 431-0030

CALIFORNIA
Schweber Electronics
Calabasas
Tel: (818) 880-9686
Schweber Electronics
Irvine
Tel: (714) 863-0200

CANADA
Time Electronics
2798 Thamesgate Drive, #5
Mississauga,
Ontario L4T 4E8
Tel: (416) 672-5300
COLORADO
Schweber Electronics
Englewood
Tel: (303) 799-0258
Time Electronics
Englewood
Tel: (303) 799-8851
Wyle Laboratories
Thornton
Tel: (303) 457-9953

CONNECTICUT
Schweber Electronics
Oxford
Tel: (203) 264-4700

Schweber Electronics
Sacramento
Tel: (916) 364-0222

FLORIDA
Schweber Electronics
Altamonte Springs
Tel: (305) 331-7555

Schweber Electronics
San Diego
Tel: (619) 495-0015

Schweber Electronics
Largo
Tel: (813) 541-5100

Schweber Electronics
San Jose
Tel: (408) 432-7171

Schweber Electronics
North Pompano Beach
Tel: (305) 997-7511

Time Electronics
Torrance
Tel: (213) 320-0880

Time Electronics
FI. Lauderdale
Tel: (305) 974-4800

Time Electronics
Sunnyvale
Tel: (408) 734-9888

Time Electronics
Orlando
Tel: (305) 841-6565

Time Electronics
Chatsworth
Tel: (818) 998-7200
Time ElectrOniCs
San Diego
Tel: (619) 586-1331
Time Electronics
Anaheim
Tel: (714) 937-0911
Wyle Laboratories
Santa Clara
Tel: (408) 727-2500
Wyle Laboratories
Rancho Cordova
Tel: (916) 638-5282
Wyle Laboratories
Irvine
Tel: (714) 863-9953
Wyle Laboratories
Irvine
Tel: (714) 851-9953
Wyle Laboratories
Calabasas
Tel: (818) 880-9001

GEORGIA
Schweber Electronics
Norcross
Tel: (404) 449-9170
Time Electronics
Norcross
Tel: (404) 448-4448

KANSAS
Schweber Electronics
Overland Park
Tel: (913) 492-2922
ILLINOIS
Schweber Electronics
Elk Grove Village
Tel: (708) 364-3750
Time Electronics
Wooddale
Tel: (708) 350-0610

INDIANA
Schweber Electronics
Indianapolis
Tel: (317) 843-1050

Wyle Laboratories
San Diego
Tel: (619) 565-9171

7-2

WAFERSCALE INTEGRATION, INC.

IOWA
Schweber Electronics
Cedar Rapids
Tel: (319) 373-1417
MARYLAND
Schweber Electronics
Columbia
Tel: (301) 596-7800
Time Laboratories
Columbia
Tel: (301) 964-3090
Vantage Components
Columbia
Tel: (301) 720-5100
Tel: (301) 621-8555

Schweber Electronics
Hauppauge
Tel: (516) 231-2500
Schweber Electronics
Westbury
Tel: (516) 334-7555
Time Electronics
Hauppauge
Tel: (516) 273-0100
Time Electronics
Fairport
Tel: (716) 383-8853
Fax: (716) 383-8863
Time Electronics
East Syracuse
Tel: (315) 432-0355

MASSACHUSSETTS
Schweber Electronics
Bedford
Tel: (617) 275-5100

Vantage Components
Smithtown
Tel: (516) 543-2000

Time Electronics
Peabody
Tel: (508) 532-9900

NORTH CAROLINA
Schweber Electronics
Raleigh
Tel: (919) 876-0000

Wyle Laboratories
Burlington
Tel: (617) 272-7300

MICHIGAN
Schweber Electronics
Livonia
Tel: (313) 525-8100
MINNESOTA
Schweber Electronics
Edina
Tel: (612) 941-5280
Time Electronics
Edina
Tel: (612) 835-1250

MISSOURI
Schweber ElectrOniCs
Earth City
Tel: (314) 739-0526
Time Electronics
SI. Louis
Tel: (314) 391-6444

NEW HAMPSHIRE
Schweber Electronics
Manchester
Tel: (603) 625-2250
NEW JERSEY
Schweber Electronics
Pinebrook
Tel: (201) 227-7880
Time Electronics
Pinebrook
Tel: (201) 882-4611

Time Electronics
Charlotte
Tel: (704) 522-7600

OHIO
Schweber Electronics
Beachwood
Tel: (216) 464-2970
Schweber Electronics
Dayton
Tel: (513) 439-1800
Time Electronics
Dublin
Tel: (614) 761-1100

OKLAHOMA
Schweber Electronics
Tulsa
Tel: (918) 622-8000
OREGON
Time Electronics
Portland
Tel: (503) 684-3780
PENNSYLVANIA
Schweber Electronics
Horsham
Tel: (215) 441-0600
Schweber Electronics
Pittsburgh
Tel: (412) 963-6804
Time Electronics
King of Prussia
Tel: (215) 337-0900

Vantage Components
Clifton
Tel: (201) 777-4100

TEXAS
Schweber Electronics
Austin
Tel: (512) 339-0088

NEW YORK
Schweber Electronics
Rochester
Tel: (716) 424-2222

Schweber Electronics
Dallas
Tel: (214) 247-6300

----------------

Sales Representatives and Distributors

Domestic
Distributors
(Cont.,

TEXAS
Schweber Electronics
Houston
Tel: (713) 784-3600
Time Electronics
Carrollton
Tel: (214) 241-7441
Wyle Laboratories
Richardson
Tel: (214) 235-9953

International
Distributors

Wyle Laboratories
Houston
Tel: (713) 879-9953

Wyle Laboratories
West Valley
Tel: (801) 974-9953

Wyle Laboratories
Austin
Tel: (512) 834-9957

UTAH

Wyle Laboratories
Redmond
Tel: (206) 881-1150

WASHINGTON

WISCONSIN

Time Electronics
Redmond
Tel: (206) 882-1600

Schweber Electronics
New Berlin
Tel: (414) 784-9020

Time Electronics
West Valley
Tel: (801) 973-8181

AUSTRALIA

GERMANY

ISRAEL

NORWAY

Energy Control
Brisbane
Tel: 61-7-376-2955
Fax: 61-7-376-3286
Tlx: 43778

Topas Electronic GmbH
3000 Hannover 1
Tel: (0511) 13 12 17
Tlx: 9218176
Fax: (0511) 13 12 16

Vectronics
60 Medinat Hayehudim St.
P.O. Box 2024
Herzlia B 46120, Israel
Tel: 972 52 556070
Tlx: 922342579
Fax: 972 52 556508

OTE AlS
N-0617 Oslo 6
Tel: 47 2 306600
Tlx: 85678955
Fax: 47 2 321360

BELGIUM
Inelco
Brussels
Tel: 32 2 216 0160
Tlx: 84-22090
Fax: 32 2 2164606

DENMARK
Distributoren Intereiko, AlS
DK-2690 Karlslunde
Tel: 45-53-140700
Tlx: 85543507
Fax: 45-53-146805

ENGLAND
Micro Call Ltd.
Thame, Oxon OX9 3XD
Tel: 44 84 426 1939
Fax: 44 84 426 1678

FINLAND

Scantec GmbH
D-33 Planegg
Tel: (089) 859-8021
Tlx: 5213219
Fax: (089) 857-6574

HOLLAND
Maxtronix
Savannahweg 60
3542 AW UTRECHT
Tel: (31) 30-420340
Fax: (31) 30-422440

HONG KONG
Components Agent Ltd.
New Territories
Tel: 0-499-2688
Tlx: 78030398
Fax: 852 0-4136080

INDIA

Silverstar
20146 Milano
Tel: 39 2 661251
Tlx: 843332189
Fax: 39-2-66101359

Nippon Imex Corporation
Setagaya-ku, Tokyo
Tel: 321 4415
Tlx: 781 23444
Fax: 81 3 325 0021

Eastern ElectroniCS, Inc.
Sungdong-Ku, Seoul
Tel: 82 2 463-2266
Tlx: 78727381
Fax: 82 2 465-2607

Northeast

Southwest

Southeast

North Andover, MA
Tel: (508) 685-6101
Fax: 508/685-6105

Huntington Beach, CA
Tel: (714) 848-6968
Fax: 714/848-5648

Huntsville, AL
Tel: (205) 539-7406
Fax: 205/539-7449

Midwest

Mid-Atlantic

Northwest

Hoffman Estates, IL
Tel: (708) 490-5318
Fax: 708/882-1881

Trevose, PA
Tel: (215) 638-9617
Fax: 215/638-7326

Fremont, CA
Tel: (415) 656-5400
Telex: 289255
Fax: 415/657-5916

FRANCE

SWEDEN

JAPAN

Pamir Electronics Corp.
400 West Lancaster
Suite 202
Devon, PA 19333 USA
Tel: 215-688-5299
Fax: 215-688-5382
Tlx: 210656 Pamir UR

OY Comdax AB
SF-00210 Helsingfors
Tel: 358 067 02 77
Tlx: 857125876
Fax: 358 06922326

Unitronics, S.A.
28008 Madrid
Tel: 34 1 542 5204
Tlx: 83122596
Fax: 34 1 248 4228

ITALY

Kyocera Corporation
Setagaya-ku, Tokyo
Tel: 3-708-3111
Tlx: 7812466091
Fax: 81-3-708-3864

KOREA

SPAIN

Traco AB
S-123 22 Farsta
Tel: 468 930011
Tlx: 85410689
Fax: 468 947732

SWITZERLAND
Laser & Electronic
Equipment
8053 Zurich
Tel: 41 (1) 55 3330
Tlx: 816801
Fax: 41 (1) 55 3458

TAIWAN
Sertek International, Inc.
Taipei, 10479, Taiwan
Tel: 2-501-0019
Tlx: 78523756

MICROEL
Imeuble MICRO
Cedex
Tel: 33 (1) 69.07.08.24
Tlx: 692493F
Fax: 33 (1) 69.07.17.23

WSI Direct
Sales Offices

REGIONAL SALES

EUROPE SALES
Excelsiorlaan 53
1930 Zaventem
Belgium
Tel: 32-2-725-0546
Fax: 32-2-725-1146

For additional information or assistance, call 800:rEAM-WSI (800-832-6974). In California, call 800-562-6363.

11/15/89

Rev. 1.23

WAFERSCALE INTEGRATION, INC.
- - - - - - - - - - ---

--_..

7-3
-~---

LIFE SUPPORT POLICY:
WaferScale Integration, Inc. (WSI) products are not authorized for use as critical components in life support systems or devices without the express
written approval of the President of WSI. As used herein:

A) Life support devices or systems are devices or systems which 1) are intended for surgical implant into the body, or 2) support or sustain life
and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury or death to the user,
B) A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system or to affect its safety or effectiveness.
Information furnished herein by WaferScale Integration, Inc. (WSI) is believed to be accurate and reliable. However, no responsibility is assumed
for its use. WSI makes no representation that the use of its products or the interconnection of its circuits, as described herein, will not infringe
on existing patent rights. No patent liability shall be incurred by WSI for use of the circuits or devices described herein. WSI does not assume
any responsibility for use of any circUitry described, no CircUit patent rights or licenses are granted or implied, and WSI reserves the right without
commitment, at any time without notice, to change said circuitry or specifications. The performance characteristics listed in this book result from
specific tests, correlated testing, guard banding, design and other practices common to the industry. Information contained herein supersedes
previously published specifications. Contact your WSI sales representative for specific testing details or latest information.
Products in this book may be covered by one or more of the following patents. Additional patents are pending.
USA: 4,328,565; 4,361,847; 4,409,723; 4,639,893; 4,649,520; 4,795,719; 4,763,184; 4,758,869
West Germany: 3,103,160
Japan: 1,279,100
England: 2,073,484; 2,073,487
PAL is a registered trademark of Monolithic Memories, Inc.
SAM and SAM+PLUS are trademarks of Aitera Corporation.
MagicPro'· and Programmable System'· Devices are trademarks of WaferScale Integration, Inc.
ASMILE, SAMSIM and SAMPLUS are trademarks of WaferScale Integration, Inc. and Altera Corporation.
MS-DOS is a trademark of Microsoft Corporation.
IBM and IBM Personal Computer is a registered trademark of International Business Machines Corporation.
Copyright © 1989 WaferScale Integration, Inc. All Rights Reserved.
Patents Pending

Rev. 1.3

WAFERSCALE INTEGRATION, INC.
47280 Kato Road, Fremont , CA 9 4 538- 7333
4 15-656-54 00 FAX: 415-65 7-5916 TELEX- 289255
800-Tl::A M-WSI (800-832-69 74)
IN CALIFORNIA 800-562-6363

Printed in U. S.A.



File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2013:08:20 18:05:40-08:00
Modify Date                     : 2013:08:21 06:22:55-07:00
Metadata Date                   : 2013:08:21 06:22:55-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:d5eb1130-6d77-8846-a0e6-d0d32e1712d3
Instance ID                     : uuid:a09f7893-b887-4649-afa6-5179ac351325
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 336