1991_16_bit_V Series_Microprocessor_Data_Book 1991 16 Bit V Series Microprocessor Data Book
User Manual: 1991_16_bit_V-Series_Microprocessor_Data_Book
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J6-BIT V-SERIES
MICROPROCESSOR DATA BOOK
NEe
NEe Electronics Inc.
NEe
1991
16-Bit V-Series Microprocessor
Data Book
May 1991
Document No. 50054-1
©1991 NEG Electronics Inc./Printed in the U.S.A.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Electronics Inc. The information in this document is subject to change without notice. Devices sold
by NEC Electronics Inc. are covered by the warranty and patent indemnification provisions appearing in NEC
Electronics Inc. Terms and Conditions of Sale only. NEC Electronics Inc. makes no warranty, express, statutory,
implied, or by description, regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. NEC Electronics Inc. makes no warranty of merchantability or fitness for any
purpose. NEC Electronics Inc. assumes no responsibility for any errors that may appear in this document. NEC
Electronics Inc. makes no commitment to update or to keep current the information contained in this document.
NEe
ii
NEe
II
B
Selection Guides
Reliability and Quality Control
i6-Bit CPUs
i6-Bit Microcomputers
Peripherals for CPUs
Development Tools
II
Package Drawings
iii
NEe
iv
NEe
Contents
Section 1
Selection Guides
Section 2
Reliability and Quality Control (cont)
Single-Chip Microcomputers
1-3
Figure 6. NEC Quality and Reliability Targets
2-10
V-Series and RISC Microprocessors and
Peripherals
1-9
Appendix 1. Typical QC Flow
2-12
Appendix 2. Typical Reliability Assurance
Tests
2-15
Intelligent Peripheral Devices (IPD)
1-11
DSP and Speech Products
1-13
Appendix 3. New Product/Process Change
Tests
2-16
1-15
1-19
1-21
1-24
1-26
1-28
Appendix 4. Failure Analysis Flowchart
2-17
Development Tools for Micro Products
V-Series Microprocessors
75xxSeries Single-Chip Microcomputers
75xxx Series Single-Chip Microcomputers
78xx Series Single-Chip Microcomputers
782xx Series Single-Chip Microcomputers
783xx Series Single-Chip Microcomputers
DSP and Speech Products
PG-1500 Programming Adapters
1-30
1-32
Section 2
Reliability and Quality Control
Introduction
2-3
Built-In Quality and Reliability
2-3
Technology Description
2-3
Approaches to Total Quality Control
2-3
Implementation of Quality Control
2..,5
Reliability Testing
2-7
Life Distribution
2-7
Failure Distribution at NEC
2-7
Infant Mortality Failure'Screening
2-8
Long-Term Failure Rate
2-8
Accelerated Reliability Testing
2-8
Failure Rate Calculation/Prediction
2-9
Product/Process Changes
2-10
Failure Analysis
2-10
NECs Goals on Failure Rates
2-10
Summary and Conclusion
2-10
Figure 1. Quality Control System .Flowchart
2-5
Figure 2. New Product Development Flow
2-6
Figure 3. Electrical Testing and Screening
2-6
Figure 4. Reliability Life (Bathtub) Curve
2-7
Figure 5. Typical Reliability Test Results
2-9
Section 3
16-Bit CPUs
"PD70108 (V20), 70108H (V20H)
16-Bit Microprocessor:
High-Performance, ,CMOS
3a
"PD70116 (V30), 70116H (V30H)
16-Bit Microprocessor:
High-Performance, CMOS
3b
"PD70208 (V40)
8/16-Bit Microprocessor:
High-Integration, CMOS
3c
"PD70216 (V50)
16-Bit Microprocessor:
High-Integration, CMOS
3d
"PD70136 (V33)
16-Bit Microprocessor:
High-Speed, CMOS
3e
"PD70236 (V53)
16-Bit Microprocessor:
High-Speed, High-Integration, CMOS
3f
Section 4
16-Bit Microcomputers
"PD70320/70322 (V25)
16-Bit Microcomputers:
Single-Chip, CMOS
4a
"PD70330/70332 (V35)
16-Bit Microcomputers:
Advanced, Single-Chip, CMOS
4b
"PD70P322
16-Bit Microcomputer:
Single-Chip, CMOS,
With EPROM for V25N35 Modes
4c
v
NEe
Contents
Section 4
16-Bit Microcomputers (cont)
Section 5
Peripherals for CPUs (cont)
I'PD70325 (V25 Plus)
16-Bit Microcomputer:
High-Speed DMA, Single-Chip, CMOS
4d
I'PD70335 (V35 Plus)
16-Bit Microcomputer:
Advanced, High-Speed DMA,
Single-Chip, CMOS
4e
I'PD70327 (V25 Software Guard)
16-Bit Microcomputer:
Software-Secure, Single-Chip, CMOS
4f
I'PD70337 (V35 Software Guard)
16-Bit Microcomputer:
Software-Secure, Single-Chip, CMOS
49
I'PD79011
16-Bit Microcomputer:
Single-Chip, CMOS, With Bui It-In RTOS
4h
I'PD79021
16-Bit Microcomputer:
Single-Chip, CMOS, With Built-In RTOS
4i
5j
I'PD71 088
System Bus Controller
5k
I'PD71641
Cache Memory Controller
51
Section 6
Development Tools
,Section 5
Peripherals for CPUs
I'PD71 011
Clock Pulse Generator/Driver
5a
"PD71 037
Direct Memory Access (DMA) Controller
5b
I'PD71 051
Serial Control Unit
5c
I'PD71 054
Programmable Timer/Counter
5d
I'PD71 055
Parallel Interface Unit
5e
I'PD71 059
Interrupt Control Unit
5f
I'PD71 071
DMA Controller
59
I'PD71 082, 71083
8-Bit Latches
5h
I'PD71 084
Clock Pulse Generator/Driver
I'PD71 086, 71087
8-Bit Bus Buffer/Drivers
5i
CC70116
V-Series C Compi ler
6a
DDK-70320
Evaluation Board for V25 Microcomputer
6b
DDK-70330
Evaluation Board for V35 Microcomputer
6c
IE-70136
In-Circuit Emulator for pPD70136 (V33)
Microprocessor
6d
IE-70136-PC
In-Circuit Emulator for pPD70136 (V33)
Microprocessor
6e
IE-70208, IE-70216
In~Circuit Emulators for pPD70208 (V40) and
pPD70216 (V50) Microprocessors
6f
IE-70320
In-Circuit Emulator for pPD70320/70322 (V25)
Microcomputers
69
IE-70330
In-Circuit Emulator for pPD70330/70332 (V35)
Microcomputers
6h
RA70116
Relocatable Assembler Package for V20-V50
Microprocessors
6i
RA70136
Relocatable Assembler Package for V33
Microprocessor
6j
RA70320
Relocatable Assembler Package for V25N35
Microcomputers
6k
V25N35 MINI-IE Plus
In-Circuit Emulator
61
V40N50 MINI-IE
In-Circuit Emulator
vi
6m
NEe
Contents
Section 7
Package Drawings
Numerical Index
Device, I'PD
Package/Device Cross-Reference
7-3
18-Pin Plastic DIP
7-5
20-Pin Plastic DIP (300 mil)
7-5
20-Pin Plastic SOP (300 mil)
7-6
24-Pin Plastic DIP (600 mil)
7-6
28-Pin Plastic DIP (600 mil)
7-7
28-Pin PLCC
7-8
40-Pin Plastic DIP (600 mil)
7-8
44-Pin Plastic QFP (P44G-80-22)
7-9
44-Pin Plastic QFP (P44GB-80-3B4)
7-9
44-Pin PLCC
7-10
48-Pin Plastic DIP
7-11
52-Pin Plastic QFP
7-12
52-Pin PLCC
7-13
68-Pin PLCC
7-14
68-Pin Ceramic PGA
7-15
74-Pin Plastic QFP
7-16
80-Pin Plastic QFP
7-17
84-Pin PLCC
7-18
84-Pin Ceramic LCC
7-19
94-Pin Plastic QFP
7-20
120-Pin Plastic QFP
7-21
132-Pin Ceramic PGA
7-22
Addenda
I'PD70236 (V53)
16-Bit Microprocessor:
High-Speed, High-Integration,
CMOS
Addendum 1
(April 1991)
Section
70108, 70108H
70116, 70116H
70136
3a
3b
3e
70208
70216
70236
3c
3d
3f
70320
70322
70325
4a
4a
4d
70327
70330
70332
4f
4b
4b
70335
70337
70P322
4e
49
4c
71011
71037
71051
5a
5b
5c
71054
71055
71059
5d
5e
5f
71071
71082
71083
59
5h
5h
71084
71086
71087
5i
5j
5j
71088
71641
79011
5k
51
4h
79021
4i
V20, V20H
V25
V25 Plus
3a
4a
4d
V25 Software Guard
V30, V30H
V33
4f
3b
3e
V35
V35 Plus
V35 Software Guard
4b
4e
49
V40
V50
V53
3c
3d
3f
vii
Contents
viii
NEe
fttfEC
Selection Guides
1-1
II
NEe
Selection Gu ides
Section 1
Selection Guides
Part Numbering System
Single-Chip Microcomputers
1-3
V-Series and RISC Microprocessors and
Peripherals
1-9
Intelligent Peripheral Devices (IPD)
1-11
DSP and Speech Products
1-13
Development Tools for Micro Products
V-Series Microprocessors
75xx Series Single-Chip Microcomputers
75xxx Series Single-Chip Microcomputers
78xx Series Single-Chip Microcomputers
782xx Series Single-Chip Microcomputers
783xx Series Single-Chip Microcomputers
DSP and Speech Products
PG-1500 Programming Adapters
1-2
1-15
1-19
1-21
1-24
1-26
1-28
1-30
1-32
I'PD72001 L
I'P
o
72001
L
Typical microdevice part number
NEC monolithic si licon integrated circuit
Device type (D = digital MOS)
Device identifier (alphanumeric)
Package type (L = PLCC)
A part number may include an alphanumeric suffix
that identifies special device characteristics; for
example, J.lPD72001L-11 has an 11-MHz CPU clock
rating.
NEe
Single-Chip Microcomputers
4-Bit, Single-Chip CMOS Microcomputers; 75xx Series
Device
(,uPD)
Features
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X4)
I/O
Package
7502(l502A
LCD controller/driver
0.41
2.5 to 6.0
2K
128
23
QFP
64
7503(l503A
LCD controller/driver
0.41
2.5 to 6.0
4K
224
23
QFP
64
7507
General-purpose
0.41
2.5 to 6.0
2K
128
32
DIP
SDIP
QFP
40
40
52
75078
General-purpose
0.5
2.2 to 6.0
2K
128
32
SDIP
QFP
40
44
7507H
General-purpose
4.19
2.7 to 6.0
2K
128
32
DIP
SDIP
QFP
40
40
52
7508
General-purpose
0.41
2.5 to 6.0
4K
224
32
DIP
SDIP
QFP
40
40
52
75088
General-purpose
0.5
2.2 to 6.0
4K
224
32
SDIP
QFP
40
44
7508H
General-purpose
4.19
2.7 to 6.0
4K
224
32
DIP
SDIP
QFP
40
40
52
t
Pins
75CG08
Piggyback EPROM
0.41
4.5 to 5.5
2K or4K
224
32
Ceramic DIP
40
75CG08H
Piggyback EPROM
4.19
4.5 to 5.5
2K or4K
224
32
Ceramic DIP
40
7027A
FIP controller/driver
0.61
2.7 to 6.0
2K
128
35
DIP
SDIP
42
42
7528A
FIP controller/driver
0.61
2.7 to 6.0
4K
160
35
DIP
SDIP
42
42
75CG28
Piggyback EPROM; FIP
controller/driver
0.5
4.5 to 5.5
4K
160
35
Ceramic DIP
42
7533
ND converter
0.51
2.7 to 6.0
4K
160
30
DIP
SDIP
QFP
42
42
44
75CG33
Piggyback EPROM; ND
converter
0.51
4.5 to 5.5
4K
160
30
Ceramic DIP
42
7537A
FIP controller/driver
0.61
2.7 to 6.0
2K
128
35
DIP
SDIP
42
42
7538A
FIP controller/driver
0.61
2.7 to 6.0
4K
160
35
DIP
SDIP
42
42
75CG38
Piggyback EPROM; FIP
controller/driver
0.5
4.5 to 5.5
4K
160
35
Ceramic DIP
42
7554
Serial I/O; external
clock or RC oscillator
0.71
2.5 to 6.0
1K
64
16
SDIP
SOP
20
20
7554A
Serial I/O; external
clock or RC oscillator
0.71
2.0 to 6.0
1K
64
16
SDIP
SOP
20
20
75P54
Serial I/O; external
clock or RC oscillator
0.71
4.5 to 6.0
1KOTPROM
64
16
SDIP
SOP
20
20
t Plastic unless ceramic (or cerdip) is specified.
1-3
II
"',:(;' ',' "':::_,'i~'~:~
NEC
Sing le'Ch i,p 'Microcomputers
4-Bit, Single-Chip CMOS Microcomputers; 75xxSeries
Device
(poP D)
" " Features
Clock
(MHz)
Supply
Voltage',(V)
ROM,{X8),
7564j7564A
Serial I/O; ceram ic
oscillator
' 0.71
2.7 to 6.0
1K
75P64
Serial I/O; ceramic
osciHator
0.71
4.5 to'6.0
7556
Comparator; external
clock or RC oscillator
0.71
7556A
Comparator; external
clock or RC oscillator
75P56
: :i . ~. ~
RAM (X4)
I/O
Package t
Pins
,64
15
' SOIP
SOP
1KOTPROM
64
15
SDIP
SOP
20"
20:
2.5 to 6.0
1K
64
20
SDIP
SOP
24
24
0.71
2.0 to 6.0
1K
64
20
SDIP
SOP
24
24
Comparator; external
clock or RC oscillator
0.71
4.5 to 6.0
1KOTPROM
64
20
SDIP
SOP
24
24
7566j7566A
Comparator; ceramic
oscillator
0.71
2.7 to 6.0
1K
64
19
SDIP
SOP
24
24
75P66
Comparator; ceramic
oscillator
0.71.
4.,5 ,to 6.0
1KOTPFlOM
64
19
SDIP
SOP,"
24
,24
20
20
t Plastic unless ceramic (or cerdip) is specified.
4-Bit, Sing Ie-Chip CMOS Microcomputers; 75xxx Series
Device (p.PD)
Features
Clock
(MHz)
Supply
Voltage
ROM (X8)
RAM (X4)
1/0
Package t·
75004
General-purpose
4.19
2.7 to 6.0
4K
512
34
SDIP
QFP
42
44
75006
General-purpose
4.19
2.7 to 6.0
6K
512
34
-SDIP
QFP'
42
44
75008
General-purpose
4.19
2.7 to 6.0
8K
512
34
' SDIP
, QFP
42
44
75P008
General-purpose; onchip OTPROM
4.19
4.5 to 5.5
8KOTPROM
512
34
SDIP
QFP
42
44
75028
A/D c,onverter
4.19
2.7 to 6.0
8K
512
48
SDIP
QFP
64
64
75P036
A/D converter; on-chip
OTPROM
4.19
2.7 to 6.0
16KOTPROM
1024
48
SDIP
QFP
64
64
75048
A/D converter; 1K x 4
EEPROM
4.19
2.7 to 6.0
8K
512
48
SDIP
QFP
64
64
16K OTPROM
1024
48
SDIP
QFP
64
64
*
A/D converter; 1K x 4
4.19
2.7 to 6.0
EEPROM; on-chip
OTPROM
Under development; consult your NEC Sales Office for availability.
75P056
*
(V)
, Pins
75104
High-end with 8-bit
instruction
4.19
2.7 to 6.0
4K
320
"52
SDIP
QFP
64
64
75104A
High-end with 8-bit
instruction
4.19
2.7 to 6.0
4K
320
52
,QFP
64
75106
High-end with 8-bit
instruction
4.19
2.7 to 6.0
6K
320
52
SDIP
QFP
64
64
75108
High-end with 8-bit
instruction
4.19
2.7 to 6.0
8K
512
52
SDIP
QFP
64
64
75108A
High-end with 8-bit
instruction
4.19
2.7 to 6.0
8K
512
52
QFP
64
1-4
NEe
J,
.. :
,:.'
Sing1e-Ch ip Microcompu~ers
4-Bit, Single-Chip CMOS Microcomputers; 75XXX Series (cont)
Clock
(MHz)
Supply
Voltage (V)'
ROM(X8)
RAM (X4)
I/O
Package t
Pins
High-end with 8-bit
instruction; on-chip
OTPROM or UVEPAOM
A.19
4.5 to 5.5
8KOTPROM
512
52
SDIP
QFP.
64
64
8K UVEPROM
512
52
Shrink cerdip
64
75P1088
High-end with 8-bit
instruction; on-chip
OTPROM
4.19
2.7 to 6.0
8KOTPROM
512
52
SDIP
QFP
64
64
75112
High-end with 8-bit
instruction
4.19
2.7 to 6.0
12K
512
52
SDIP
QFP
64
64
75116
High-end with 8-bit
instruction
4.19
2.7 to 6.0
16K
512
52
SDIP
QFP
64
64
75P116
High-end with 8-bit
instruction; on-chip
OTPROM
4.19
4.5 to 5.5
16KOTPROM
512
52
SDIP
QFP
64
64
75206
FIP controller/driver
4.19
2.7 to 6.0
6K
369
28
SDIP
QFP
64
64
75208
FIP controller/driver
4.19
2.7 to 6.0
8K
497
28
SDIP
QFP
64
64
75CG208
FIP controller/driver;
piggyback EPROM
4.19
4.5 to 5.5
8K
512
28
Ceramic SDIP
Ceramic QFP
64
64
75212A
FIP controller/driver
4.19
2.7 to 6.0
12K
512
28
SDIP
Q,FP
64
64
75216A
FIP controller/driver;
on-chip OTPAOM
4.19
2.7 to 6.0
16K
512
28
SDIP
QFP
64
64
75CG216A
FIP c<>ntroller/driver;
piggYQack EPROM
4.19
4.5 to 5.5
16K
512
28
Ceramic SDIP
Ceramic QFP
64
64
75P216A
FIP controller/driver;
on-chip OTPROM
4.19
4.5 to 5.5
16KOTPROM
512
28
SDIP
64
75217
FIP controller/driver
4.19
2.7 to 6.0
24K
768
28
SDIP
QFP
64
64
75P218
FIP cOntroller/driver;
on-chip OTPROM or
UVEPROM
4.19
2.7 to 6.0
?2KOTPROM
1024
28
SDIP
QFP
64
64
32KUVEPROM
1024
28
Ceramic LCC
64
75268
FIP controller/driver
4.19
2.7 to 6.0
8K
512
28
SDIP
QFP
64
64
75304
LCD controller/driver
4.19
2.7 to 6.0
4K
512
32
QFP
80
75306
LCD controller/driver
4.19
2.7 to 6.0
6K
512
32
QFP
80
75308
LCD controller/driver
4.19
2.7 to 6.0
8K
512
32
QFP
80
75P308
LCD controller/driver;
on-chip OTPROM or
UVEPROM
4.19
4.75 to 5.25
8KOTPROM
512
32
QFP
80
8K UVEPROM
512
32
Ceramic LCC
80
75312
LCD controller/driver
4.19
2.7 to 6.0
12K
512
32
QFP
80
75316
LCD controller/driver
4.19
2.7 to 6.0
16K
512
32
QFP
80
75P316
LCD controller/driver;
on-chip OTPROM
4.19
4.75 "to 5.25
16KOTPROM
512
32
QFP
80
75P316A
LCD controller/driver;
on-chip OTPROM or
UVEPROM
4.19
2.7 to 6.0
16KOTPROM
512
32
QFP
80
16K UVEPROM
512
32
Ceramic LCC
80
Device
(~PD)
75P108
Features
'
,.
1-5
II
NEe
Single.. Chip Microcomputers
4-Bit, Single-Chip CMOS Microcomputers; 75xxx Series (cont)
Clock
(MHz)
Supply
Voltage
ROM (X8)
RAM (X4)
I/O
Package
LCD controller/driver;
AID converter
4.19
2.7 to 6.0
8K
512
36
QFP
80
75P328
LCD controller/driver;
AID converter; on-chip
OTPROM
4.19
4.5 to 5.5
8KOTPROM
512
36
QFP
80
75402A
Low-end
4.19
2.7 to 6.0
2K
64
22
DIP
SDIP
QFP
28
28
75P402
Low-end; on-chip
OTPROM
4.19
4.5 to 5.5
2KOTPROM
64
22
DIP
SDIP
QFP
28
28
75512
High-end; AID
converter
4.19
2.7 to 6.0
12K
512
64
QFP
80
75516
High-end; AID
converter
4.19
2.7 to 6.0
16K
512
64
QFP
80
75P516
High-end; AID
converter; on-chip
OTPROM or UVEPROM
4.19
4.75 to 5.5
16KOTPROM .
512
64
QFP
80
16KUVEPROM
512
64
Ceramic LCC
80
Device (~PD)
Features
75328
(V)
t
Pins
44
44
t Plastic unless ceramic (or cerdip) is specified.
a-Bit, Sing le-Chip CMOS Microcomputers; 78xx Series
Device (~PD)
Features
Clock
(MHz)
Supply
Voltage
ROM (X8)
RAM (X4)
1/0
Package
78C10178C10A
CMOS; AID converter
15
4.5 to 5.5
External
256
32
QUIP
SDIP
QFP
PLCC
64
64
64
68
78C11178C11A
CMOS; AID converter
15
4.5 to 5.5
4K
256
40
QUIP
SDIP
QFP
PLCC
64
64
64
68
78C12A
CMOS; AID converter
15
4.5 to 5.5
8K
256
40
QUIP
SDIP
QFP
PLCC
64
64
64
68
78C14178C14A
CMOS; AID converter
15
4.5 to 5.5
16K
256
40
QUIP
SDIP
QFP
PLCC
64
64
64
68
78CP14
CMOS; A/D converter;
on-chip OTPROM or
UVEPROM
15
4.75 to 5.25
16KOTPROM
256
40
QUIP
SDIP
QFP
PLCC
64
64
64
68
16KUVEPROM
256
40
Ceramic QUIP
Shrink cerdip
64
64
(V)
t
Pins
78CG14
CMOS; AID converter;
piggyback EPROM
15
4.5 to 5.5
4K, 81<, or 16K
256
40
Ceramic QUIP
64
78C17
CMOS; AID converter
15
4.5 to 5.5
External
1024
40
QUIP
SDIP
QFP
64
64
64
1-6
NEe
Single-Chip Microcomputers
a-Bit, Single-Chip CMOS Microcomputers; 78xx Series (cont)
Device (l'PD)
Features
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X4)
1/0
Package
78C18
CMOS; AID converter
15
4.5 to 5.5
32K
1024
40
QUIP
SDIP
QFP
64
64
64
78CP18
CMOS; AID converter;
on-chip OTPROM or
UVEPROM
15
4.75 to 5.25
32KOTPROM
1024
40
QUIP
SDIP
QFP
64
64
64
32K UVEPROM
1024
40
Ceramic LCC
64
t
Pins
t Plastic unless cerami.c (or cerdip) is specified.
8-Bit, Single-Chip CMOS Microcomputers; 782xx (K2) Series
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X4)
1/0
Package
CMOS; AID converter;
advanced peripherals
12
4.5 to 5.5
8K
384
54
SDIP
QUIP
QFP
QFP
PLCC
64
64
64
74
68
78213
CMOS; AID converter;
advanced peripherals
12
4.5 to 5.5
External
512
54
SDIP
QUIP
QFP
QFP
PLCC
64
64
64
74
68
78214
CMOS; AID converter;
advanced peripherals
12
4.5 to 5.5
16K
512
54
SDIP
QUIP
QFP
QFP
PLCC
64
64
64
74
68
78P214
CMOS; AID converter;
advanced peripherals
12
4.5 to 5.5
16KOTPROM
512
54
SDIP
QUIP
QFP
QFP
PLCC
64
64
64
74
68
16K UVEPROM
512
54
Shrink cerdip
64
78220
CMOS; analog
comparator; large I/O
12
4.5 to 5.5
External
640
71
PLCC
QFP
84
94
78224
CMOS; analog
comparator; large 110
12
4.5 to 5.5
16K
640
71
PLCC
QFP
84
94
78P224
CMOS; analog
comparator; large 110
12
4.5 to 5.5
16KOTPROM
640
71
PLCC
QFP
84
94
78233
CMOS; real-time
outputs; AID and DIA
converters
12
4.5 to 5.5
External
640
64
QFP
QFP
PLCC
80
94
84
78234
CMOS; real-time
outputs; AID and DIA
converters
12
4.5 to 5.5
16K
640
64
QFP
QFP
PLCC
80
94
84
78237
CMOS; real-time
outputs; AID and DIA
converters
12
4.5 to 5.5
External
1024
64
QFP
QFP
PLCC
80
94
84
Device (l'PD)
Features
78212
t
Pins
1-7
..
NEe
Single-Chip Microcomputers
8-Bit, Single-Chip CMOS Microcomputers; 782xx (K2) Series (cont)
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X4)
1/0
Package
CMOS; real-time
outputs; AID and D/A
converters
12
4.5 to 5.5
32K
1024
64
QFR
QFP
PLCC
80
94
84
78P238
CMOS; real-time
outputs; AID and D/A
converters
12
4.5 to 5.5
32KOTPROM
1024
64
QFP
QFP
PLCC
80
94
84
32K UVEPROM
1024
64
Ceramic LCC
94
78243
CMOS; AID converter;
EEPROM
12
4.5 to 5.5
External
512
512
EEPROM
54
SDIP
QFP
PLCC
64
64
68
78244
CMOS; AID converter;
EEPROM
12
4.5 to 5.5
16K
512
512
EEPROM
54
SDIP
QFP
PLCC
64
64
68
Device ("PD)
Features
78238
t
t
Pins
Plastic unless ceramic (or cerdip) is specified.
8/16-Bit, Sing Ie-Chip CMOS Microcomputers; 783xx (K3) Series
Device
(!1PD)
Features
Clock
(MHz)
Supply
Voltage (V)
ROM (X8)
RAM (X4)
1/0
Package
78310A
Real-time motor control
12
4.5 to 5.5
External
256
48
SDIP
QUIP
QFP
PLCC
64
64
64
68
78312A
Real-time motor control
12
4.5 to 5.5
8K
256
48
SDIP
QUIP
QFP
PLCC
64
64
64
68
78P312A
Real-time motor control
12
4.5 to 5.5
8K UVEPROM
256
48
Shrink cerdip
Ceramic QUIP
64
64
8K OTPROM
256
48
SDIP
QUIP
QFP
PLCC
64
64
64
68
t
Pins
78320
High-end; advanced
analog and digital
peripherals
16
4.5 to 5.5
External
640
55
QFP
PLCC
74
68
78322
High-end; advanced
analog and digital
peripherals
16
4.5 to 5.5
16K
640
55
QFP
PLCC
74
68
78P322
High-end; advanced
analog and digital
peripherals
16
4.5 to 5.5
16KOTPROM
640
55
QFP
PLCC
74
68
16K UVEPROM
640
55
Ceramic LCC
Ceramic LCC
68
74
78330
CMOS; real-time pulse
unit
16
4.5 to 5.5
External
768
70
QFP
PLCC
94
84
78334
CMOS; real-time pulse
unit
16
4.5 to 5 ..5
32K
768
70
QFP
PLCC
94
84
78P334
CMOS; real-time pulse
unit
16
4.5 to 5.5
32KOTPROM
768
70
QFP
PLCC
94
84
32K UVEPROM
768
70
Ceramic LCC
84
1-8
NEe
V-Series and RiSe Microprocessors and Peripherals
V-Series CMOS Microprocessors
Device,
poPD
Features
Data Bits
Clock (MHz)
Packaget
Pins
70108 (V20)
8088 compatible; enhanced
8/16
8 or 10
DIP
Ceramic DIP
QFP
PLCC
40
40
52
44
70108H (V20H)
Fully static; pin compatible with 80C88
enhanced microprocessor
8/16
10,12,16
DIP
QFP
PLCC
40
52
44
70116 (V30)
8086 compatible; enhanced
16
8 or 10
DIP
Ceramic DIP
QFP
PLCC
40
40
52
44
70116H (V30H)
Fully static; pin compatible with 80C86
enhanced microprocessor
16
10,12,16
DIP
QFP
PLCC
40
52
44
70208 (V40)
MS-DOS, V20 compatible CPU with peripherals
8/16
8 or 10
Ceramic PGA
PLCC
QFP
68
68
80
70208H (V 40H)
Fully static; low power; 80C88 compatible CPU
plus peripherals
8/16
10,12,16
Ceramic PGA
PLCC
QFP
68
68
80
70216 (V50)
MS-DOS, V30 compatible CPU with peripherals
16/16
8 or 10
PGA
PLCC
QFP
68
68
80
70216H (V50H)
Fully static; low power; 80C88 compatible CPU
plus peripherals
16
10,12,16
Ceramic PGA
PLCC
QFP
68
68
80
70136 (V33)
Hardwired, enhanced V30
8 and 16
dynamic
12 or 16
PGA
PLCC
68
68
70236 (V53)
V33 core-based; high-integration; DMA, serial
I/O, interrupt controller, etc.
8 and 16
dynamic
10,12,16
Ceramic PGA
QFP
132
120
70320 (V25)
MS-DOS compatible microcontroller; highintegration; DMA, serial I/O, interrupt controller,
etc.
8/16
50r8
PLCC
QFP
84
94
70330 (V35)
MS-DOS compatible microcontroller; highintegration; DMA, serial I/O, interrupt controller,
etc.
16
8
PLCC
QFP
84
94
70325 (V25 Plus)
MS-DOS compatible microcontroller; highintegration; high-speed DMA
8/16
8 or 10
PLCC
QFP
84
94
70335 (V35 Plus)
MS-DOS compatible microcontrol/er; highintegration; high-speed DMA
16
8 or 10
PLCC
QFP
84
94
70327 (V25
Software Guard)
MS-DOS compatible microcontrol/er; highintegration; software protection
8/16
8
PLCC
QFP
84
94
70337 (V35
Software Guard)
MS-DOS compatible microcontroller; highintegration; software protection
16
8
PLCC
QFP
84
94
70423 (V55 SC)
V25 upward-compatible, high-integration
microcontroller with full synchronous serial
support and buffer management
8 and 16
dynamic
Ceramic PGA
PPGA
QFP
132
132
120
·12.5
t Plastic unless ceramic (or cerdip) is specified.
1-9
II
NEe
V -Series and RiSe Microprocessors and Peripherals
V-Series CMOS System Support Products
Device,
Data Bits
Clock (MHz)
Packaget
Pins
20
DIP
SOP
18
20
8
10
DIP
QFP
PLCC
40
40
44
Serial Control Unit
8
8/10
DIP
QFP
PLCC
28
44
28
71054
Programmable Timer/Controller
8
8/10
DIP
QFP
PLCC
24
44
28
71055
Parallel Interface Unit
8
8/10
DIP
QFP
PLCC
40
44
44
71059
Interrupt Control Unit
8
8/10
DIP
QFP
PLCC
28
44
28
71071
DMA Controller
8/16
8/10
DIP
Ceramic DIP
QFP
PLCC
48
48
52
52
71082
Transparent Latch
8
8
DIP
SOP
20
20
71083
Transparent Latch
8
8
DIP
SOP
20
20
71084
Clock Pulse Generator/Driver
25
DIP
SOP
18
20
71086
Bus Buffer/Driver
8
8
DIP
SOP
18
20
71087
Bus Buffer/Driver
8
8
DIP
SOP
20
20
71088
System Bus Controller
8/10
DIP
SOP
20
20
71101
Complex Peripheral Unit; serial, parallel, timer,
interrupt
8
10
QFP
120
~PD
Features
71011
Clock Pulse Generator/Driver
71037
Programmable DMA Controller
71051
71641
Cache Memory Controller
8/16/32
25
PGA
132
72291
Floating Point Coprocessor for V33/V53
16
16
PGA
68
9335
Numeric Interface Adapter for V40/V50 ... i8087
8
DIP
20
t Plastic unless ceramic (or cerdip) is specified.
RISC Microprocessors and Peripherals
Device
Name
Clock
Package
Pins
pPD30310 (VR3000A)
RISC Microprocessor
25, 33, 40 MHz
PGA
175
pPD30311 (VR3010A)
Floating-Point Processor
25, 33, 40 MHz
PGA
84
pPD31311
Bus Interface Unit
25,33 MHz
PGA
208
pPD46710
16K x 10-Bit x 2 SRAM
Access time: 12,15 20 ns
PLCC
52
pPD46741
8K x 20-Bit x 2 SRAM
Access time: 12, 15, 20 ns
PLCC
68
pPD30360 (V R3600)
RISC Microprocessor
25,33 MHz
PGA
189
1-10
NEe
Intelligent Peripheral Devices (IPD)
Communications Controllers
Maximum
Data Rate
Packaget
Pins
Dual full-duplex serial channels; four DMA
channels; programmable interrupt vectors;
asychronous COP and BOP support; NMOS
1 Mb/s
DIP
40
CMOS, Advanced
Multiprotocol Serial
Communications
Controller
Functional superset of 8530; 8086/V30
interface; two full-duplex serial channels; two
DPLLs; two baud-rate generators per channel;
loop back test mode; short frame and mark idle
detection; 12.5-MHz max clock
2.5 Mb/s
DIP
QFP
PLCC
40
52
52
72002
CMOS, Advanced
Multiprotocol Serial
Communications
Controller
Low-cost, single-channel version of 72001 ;
software compatible; direct interface to 71071/
8237 DMA controllers; 12.5-MHz max clock
2.5 Mb/s
DIP
QFP
PLCC
40
44
44
72103
CMOS, HDLC Controller
Single full-duplex serial channel; on-chip DMA
controller
4 Mb/s
SDIP
PLCC
QFP
64
68
80
Device,
~PD
Name
Description
7201 A
Multiprotocol Serial
Communications
Controller
72001-11
II
Graphics Controllers
Maximum
Drawing Rate
Package t
Pins
General-purpose, high-integration controller;
hardwired support for lines, arc/circles,
rectangles, and graphics characters; 1024x1024
pixel display with four planes
500 ns/dot
Ceramic DIP
40
Graphics Display
Controller
CMOS 7220A with 2M video memory; dual-port
RAM control; write-masking on any bit;
enhanced external sync
500 ns/dot
DIP
QFP
40
52
72120
Advanced Graphics
Display Controller
High-speed graphics operations including paint,
area fill, slant, arbitrary angle rotate, up to 16x
enlargement and reduction; dual-port RAM
control; CMOS
500 ns/dot
PLCC
QFP
84
94
72123
Advanced Graphics
Display Controller II
Enhanced 72120; expanded command set;
improved painting performance; laser printer
interface controls; CMOS
400 ns/dot
PLCC
QFP
84
94
Device,
~PD
Name
Description
7220A
Hig h-Per fo rm ance
Graphics Display
Controller
72020
Advanced Compression/Expansion Engine
Device,
~PD
Name
Description
Package t
Pins
72185
Advanced Compression/
Expansion Engine
High-speed CC ITT Group 3/4 bit-map image compression/expansion
(A4 test chart, 400 PPI x 400 LPI in under 1 second); 32K-pixelline
length; 32-megabyte image memory; on-chip DMA and refresh timing
generator; CMOS
SDIP
PLCC
QFP
64
68
80
t
Plastic unless ceramic (or cerdip) is specified.
1-11
NEe
Intelligent Peripheral Devices (IPO)
Floppy-Disk Controllers
Maximum
Transfer
Rate
Package t
Pins
Industry-standard controller supporting IBM
3740 and IBM System 34 double-density
format; enhanced 765B supports multitasking
applications
500 kb/s
DIP
40
Floppy-Disk Interface
Compatible with 765-family controllers and
others; supports multiple data rates from 125 to
500 kb/s
500 kb/s
SOP
SDIP
28
30
72064
Floppy-Disk Controller
CMOS. All features of 72068 with complete AT
register set and 48-mA drivers. Pin compatible
with WD 37C65/A/B but with higher
performance DPLL and reliable multitasking
operation
500 kb/s
PLCC
QFP
44
52
72065/65B
CMOS Floppy-Disk Controller
100% 765NB microcode compatible;
compatible with 808x microprocessor families
500 kb/s
DIP
PLCC
QFP
40
44
52
72067
Floppy-Disk Controller
CMOS; 765A/B microcode compatible clock
generation/switching circuitry; selectable write
precompensation; digital phase-locked loop
500 kb/s
DIP
PLCC
QFP
48
52
52
72068
Floppy-Disk Controller
All features of the 72067 plus IBM-PC, PC/XT,
PC/AT, or PS/2 style registers; high-current
drivers
600 kb/s
QFP
PLCC
80
84
72069
Floppy-Disk Controller
All features of the 72067/68 with substitution of
high-performance analog phase-locked loop for
digital PLL
1 Mb/s
PLCC
QFP
84
100
Device,
"PO
Name
Description
765A!B
Floppy-Disk Controller
71065/66
Hard-Disk Controllers
Device,
"PO
Name
Description
Maximum
Read/Write
Clock
Package t
Pins
40
7261A!B
Hard-Disk Controller
Supports eight drives in SMD mode, four drives
in ST506 mode; error correction and detection
23 MHz
Ceramic DIP
7262
Enhanced Small-Disk
Interface (ESDI)
Controller
Serial-mode ESDI compatible; controls up to
seven drives; supports up to 80 heads; hard
and soft-sector interfacing
18 MHz
Ceramic DIP
40
72061
CMOS Hard-Disk
Controller
Supports SMD/SMD-E and ST506/412 type
drives
24 MHz
DIP
QFP
PLCC
40
52
52
72111
Small Computer System
Interface (SCSI)
Controller
Selectable 8/16 data bus width; 16 high-level
commands including multiphase commands for
reduced CPU load; 5-Mb sync/async; CMOS
16 MHz
SDIP
PLCC
QFP
64
68
74
t
Plastic unless ceramic (or cerdip) is specified.
1-12
NEe
DSP and Speech Products
Digital Signal Processors
~PD
Description
Instruction
Cycle (ns)
Instruction
ROM (Bits)
Data ROM
(Bits)
Data RAM
(Bits)
77C20A
16-bit, fixed-point DSP; CMOS
244
512 x 23
510x 13
128 x 16
DIP
PLCC
SOP
PLCC
28
28
32
44
77P20
16-bit, fixed-point DSP; CMOS
244
512 x 23
UVEPROM
510x 13
UVEPROM
128 x 16
Cerdip
28
77C25
16-bit, fixed-point DSP; CMOS
122/100
2048 x 24
1024 x 16
256 x 16
DIP
PLCC
SOP
PLCC
28
28
32
44
77P25
16-bit, fixed-point DSP; CMOS
122/100
2048 x 24
OTPROM
1024 x 16
OTPROM
256 x 16
DIP
SOP
PLCC
28
32
44
2048 x 24
UVEPROM
1024 x 16
UVEPROM
256 x 16
Cerdip
28
Device,
Package
t
Pins
77220
24-bit, fixed-point DSP; CMOS
122/100
2048 x 32
1024 x 24
512 x 24
Ceramic PGA
PLCC
68
68
77P220L
24-bit, fixed-point DSP; CMOS
122/100
2048 x 32
OTPROM
1024 x 24
OTPROM
512 x 24
PLCC
68
77P220R
24-bit, fixed-point DSP; CMOS
122/100
2048 x 32
UVEPROM
1024 x 24
UVEPROM
512 x 24
Ceramic PGA
68
77230AR
32-bit, floating-point DSP; CMOS
150
2048 x 32
1024 x 32
1024 x 32
Ceramic PGA
68
77230AR-003
32-bit, floating-point DSP; CMOS;
standard library software
150
n/a
n/a
n/a
Ceramic PGA
68
77P230R
32-bit, floating-point DSP; CMOS
150
2048 x 32
UVEPROM
1024 x 32
UVEPROM
1024 x 32
Ceramic PGA
68
77240
32-bit, advanced, floating-point
DSP; CMOS
90
64Kx 32
external
n/a
16M x32
external
PGA
132
77810
16-bit fixed-point modem DSP;
CMOS
181
2048 x 24
1024 x 16
256 x 16
Ceramic PGA
PLCC
68
68
77811
Analog front end for 2400-b/s fullduplex modem
n/a
n/a
n/a
n/a
PLCC
44
77812
2400-b/s full-duplex modem
controller
181
n/a
n/a
256 x 16
PLCC
QFP
68
74
7281
Image pipelined processor; NMOS
5-MHz clock
n/a
n/a
512 x 18
Ceramic DIP
40
72181
Image pipelined processor; CMOS
10-MHz clock
n/a
n/a
512 x 18
DIP
QFP
40
68
9305
Support device for JlPD7281
processors; CMOS
10-MHz clock
n/a
n/a
n/a
Ceramic PGA
132
t
Plastic unless ceramic (or cerdip) is specified.
1-13
II
NEe
DSP and Speech Products
Speech Processors
Name
Technology
Bit Rate
(kb/s)
77C30
ADPCM Speech Encoder/Decoder
NMOS
32
7755
ADPCM Speech Synthesizer
CMOS
16, 20, 24, 32
7756
ADPCM Speech Synthesizer
CMOS
77P56
ADPCM Speech Synthesizer
7757
Device,
Packaget
Pins
DIP
PLCC
28
44
96K
DIP
SOP
18
24
16,20,24,32
256K
DIP
SOP
18
24
CMOS
16,20,24,32
256K
OTPROM
DIP
SOP
20
24
ADPCM Speech Synthesizer
CMOS
16,20,24,32
512K
DIP
SOP
18
24
7759
ADPCM Speech Synthesizer
CMOS
16, 20, 24, 32
1024K
external RAM
DIP
QFP
40
52
77501
Speech Recording and Reproducing LSI
CMOS
12,18,24
16M
external RAM
QFP
80
~PD
t Plastic unless ceramic (or cerdip) is specified.
1-14
Data ROM
(Bits)
NEe
Development Tools for Micro Products
V-Series Microprocessors
Device
(Note 1)
Full
Emulator
Full
Emulator
Probe
Relocatable
Assembler
(Note 13)
C Complier
(Note 14)
pPD70136GJ12
IE-70136A016
DDK-70136
RA70136
CC70136
pPD70136GJ16
EP-70136L-PC
(Note 2)
DDK-70136
RA70136
CC70136
IE-70136-PC
EP-70136L-PC
DDK-70136
RA70136
CC70136
EP-70136L-A
IE-70136-PC
EP-70136L-PC
DDK-70136
RA70136
CC70136
IE-70136A016
EP-70136L-A
(Note 3)
IE-70136-PC
EP-70136L-PC
(Note 3)
DDK-70136
RA70136
CC70136
pPD70136R-16
IE-70136A016
EP-70136L-A
(Note 3)
IE-70136-PC
EP-70136L-PC
(Note 3)
DDK-70136
RA70136
CC70136
pPD70208GF-
IE-7020BA010
(Note 12)
EB-V40MINIIE
EB-7020B
RA70116
CC70116
B
pPD70208GF10
IE-70208A010
(Note 12)
EB-V40MINIIE
EB-70208
RA70116
CC70116
pPD70208L-8
IE-70208A010
IE-700002958
EB-V40MINIIE
ADAPT68PGA
68PLCC (Note
4)
EB-70208
RA70116
CC70116
pPD70208L-10
IE-70208A010
IE-700002958
EB-V40MINIIE
ADAPT68PGA
6BPLCC
(Note 4)
EB-70208
RA70116
CC70116
pPD70208R-8
IE-70208A010
IE-700002959
EB-V40MINIIE
(Note 4)
EB-70208
RA70116
CC70116
pPD70208R-10
IE-70208A010
IE-700002959
EB-V40MINIIE
(Note 4)
EB-70208
RA70116
CC70116
pPD70216GF8
IE-70216A010
EP-70320J
(Note 12)
EB-V50MINIIE
EB70216
RA70116
CC70116
pPD70216GF10
IE-70216A010
EP-70320J
(Note 12)
EB-V50MINIIE
EB70216
RA70116
CC70116
pPD70216L-8
IE-70216A010
IE-700002958
EB-V50M INIIE
ADAPT68PGA
68PLCC (Note
4)
EB70216
RA70116
CC70116
pPD70216L-10
IE-70216A010
IE-700002958
EB-V50MINIIE
ADAPT68PGA
6BPLCC (Note
EB70216
RA70116
CC70116
pPD70216R-B
IE-70216A010
IE-700002959
EB-V50MINIIE
(Note 4)
EB70216
RA70116
CC70116
pPD70216R-10
IE-70216A010
IE-700002959
EB-V50MINIIE
(Note 4)
EB70216
RA70116
CC70116
pPD70236GD10
IE-70236-BX
EV-9500GD120
(Note 1B)
DDK-70236
RA70136
CC70136
pPD70236GD12
IE-70236-BX
EV-9500GD120
(Note 18)
DDK-70236
RA70136
CC70136
Mini-IE
Emulator
Mini-IE
Probe
Evaluation
Boards
EP-70136L-A
(Note 2)
IE-70136-PC
EP-70136L-PC
(Note 2)
IE-70136A016
EP-70136L-A
(Note 2)
IE-70136-PC
pPD70136L-16
IE-70136A016
EP-70136L-A
pPD70136L-12
IE-70136A016
pPD70136R-12
EPROM
Device
4)
1-15
II
ttiEC
Deve;lopment Tools for Micro Products
V-Series Microprocessors (cont)
Relocatable
Assembler
(Note 13)
C Complier
(Note 14)
DDK-70236
RA70136
CC70136
(Note 17)
DDK-70236
RA70136
CC70136
(Note 17)
DDK-70236
RA70136
CC70136
Full
Emulator
Probe'
Device
(Note 1)'
Full
Emulator
pPD70236GD16
IE-70236-BX
EV-9$00GD.
120
(Note 1S)
pPD70236A-10
IE-70236-BX
pPD70236A·
12
IE-70236-BX
RA70136
CC70136
RA70320
CC70116
IE-P
EP-70320GJ
(Note 5)
EB-V25MINI·
IE-P
EP-70320GJ
(Note 6)
DDK-70320
RA70320
CC70116
EP-70320L
EB-V25MINI·
IE-P
(Note 7)
DDK-70320
RA70320
CC70116
IE-70320AOOS
EP-70320L
EB-V25MINIIE-P
(Note 7)
DDK-70320
RA70320
CC70116
IE-70320~
EV-9500GJ94
(Note 16)
EB-V25MINIIE-P
EP-70320GJ
(Note 6)
DDK"70320
RA70320
CC70116
EB-V25MINIIE-P
EP-70320GJ
DDK-70320
RA70320
CC70116
EB-V25MINI~
(Note 7)
DDK~70320
70P322K
(Note 10)
RA70320
CC70116
EB·V25MINIIE-P
(Note 7)
DDK-70320
70P322K
(Note 10)
RA70320
CC70116
Ep-70320GJ
(Note 5)
IE-70320·
AOOS
IE~70320~
AOOS
pPD70322GJ
EPROM
Device
DDK-70320
(Note 17)
IE-70320AOOS
pPD70320L·S
Evaluation
Boards
DDK-70236
IE-70236-BX
pPD70320GJ
pPD70320L
Mini-IE
Probe
EP-70320GJ
(Note 6)
pPD70236A-16
pPD70320GJS
Mini-IE
Emulator
AOOS
EB-V25MINI~
pPD70322GJS
IE-70320·
AO.OS
EP-70320GJ
pPD70322L
IE-70320AOOS
(Note 15)
pPD70322L-S
IE-70320AOOS
(Note 15)
pPD70325GJ·
S
IE-70325-BX
EV-9500GJ94
. (Note 16)
EB-V25MINIIE-P
EP-70320GJ
(Note 6)
DDK-70325
RA70320
CC70116
pPD70325GJ·
10
IE-70325-BX
(Note S)
EV-9500GJ·
94
(Note 16)
EB-V25MINIIE-P
EP-70320GJ
(Note 6)
DDK·70325
RA70320
CC70116
pPD70325L-S
IE-70325-BX
(Note 15)
EB-V25MINIIE-P
EP-70320GJ
,(Note 6)
DDK-70325
RA70320
CC70116
pPD70325L-10
IE-70325-BX
(Note S)
(Note 15)
EB-V25MINIIE-P
EP-70320GJ
(Note 6)
DDK-70325
RA70320
CC70116
pPD7032iGJS (Note 9)
IE-70320AOOS
EP-70320GJ
(Note 5)
EB-V25MINIIE-P
EP-70320GJ
(Note 6)
RA70320
CC70116
pPD70327L~S
IE-70230AOOS
EP-70320L
EB-V25MINIIE-P
(Note 7)
RA70320
CC70116
IE-70330AOOS
EP-70320GJ
(Note 5)
EB-V35MINIIE-P
i::P-70320GJ
(Note 6)
DDK-70330
RA70320
CC70116
pPD70330L-8
IE-70330AOOS
EP-70320L
EB-V35MINI·
IE-P
(Note 7)
DDK-70330
RA70320
CC70116
pPD70332GJS
IE-70330AOOS
EP-70320GJ
(Note 5)
EB-V35MINI·
IE-P
EP-70320GJ
(Note 6)
DDK-70330
RA70320
CC70116
pPD70332L-8
IE-70330AOOS
EP-70320L
EB-V35MINIIE-P
(Note 7)
DDK-70330
RA70320
CC70116
(Note 9)
pPD70330GJ~
S
1-16
IE-P
70P322K
(Note. 10)
~EC
Development. Tools for Micro Products
V-Series Microprocessors (cont)
Relocatable
Assembler
(Note 13)
C Compiler
(Note 14)
DDK-70330
RA70320
CC70116
EP-70320GJ
(Note 6)
DDK-70330
RA70320
CC70116
EB-V35MINIIE-P
EP-70320GJ
(Note 6)
DDK-70330
RA70320
CC70116
(Note 15)
EB-V35MINIIE-P
EP-70320GJ
(Note 6)
DDK-70330
RA70320
CC70116
IE-70330ACOB
EP-70320GJ
(Note 5)
EB-V35MINIIE-P
EP-70320GJ
(Note 6)
RA70320
CC70116
pPD70337L-B
(Note 9)
IE-70330ACOB
EP-70320L
EB-V35MINIIE-P
(Note 7)
RA70320
CC70116
pPD79011 GJB (Note 11)
IE-70320ACOB
EP-70320GJ
(Note 5)
(Note 12)
(Note 12)
RA70320
CC70116
pPD79011 L-B
(Note 11)
IE-70320ACOB
+ IE-70320RTOS
EP-70320L)
(Note 12)
(Note 12)
RA70320
CC70116
pPD79021 L-B
(Note 11)
IE-70330A008
+ IE-70330RTOS
EP-70320L
(Note 12)
(Note 12)
RA70320
CC70116
Device
(Note 1)
Full
Emulator
pPD70335GJ-
IE-70335-BX
pPD70335GJ10
Full
Emulator
Probe
Mini-IE
Emulator
Mini-IE
Probe
EV,aluation
Boards
EV-9500GJ94
(Note 16)
EB-V35MINIIE-P
EP-70320GJ
(Note 6)
IE-70335-BX
(Note B)EV9500GJ-94
(Note 16)
EV-9500GJ94
(Note 16)
EP-V35MINIIE-P
pPD70335L-B
IE-70335-BX
(Note 15)
pPD70335L-10
IE-70335-BX
(Note 8)
pPD70337GJB (Note 9)
B
EPROM
Device
Notes:
(1) Packages:
GF
GJ
K
L
R
BO-pin
74-pin
B4-pin
6B-pin
6B-pin
plastic QFP
or 94-pin plastic QFP
ceramic LCC with window
or B4-pin plastic LCC
PGA
(2) The EP-70136GL-A and EP-70136L-PC contain both a 68-pin
PLCC probe and an adapter which converts the 68-pin PLCC
probes to a 74-pin QFP footprint.
(3) 68-pin PGA parts are supported by using the EP-70136L-A
PLCC probe or EP-70136L-PC PLCC probe, plus a PLCC socket
with a PGA-pinout. A PLCC socket of this type is supplied with
the EP-70136L-A.
(4) The EB-V40 MINI-IE and EB-V50 MINI-IE support PGA packages
directly; the ADAPT68PGA6BPLCC adapter converts the PGApinout on the MINI-IE to a PLCC footprint. This adapter is
supplied with the MINI-IE.
(5) The EP-70320GJ is an adapter to the EP-70320L, which converts
B4-pin PLCC probes to a 94-pin QFP footprint. For GJ parts, both
the PLCC probe and the adapter are needed.
(6) The EP-70320GJ adapter can be used to convert the supplied
84-pin PLCC cable of the EB-V25 MINI-IE-P or EB-V35 MINI-IE-P
to a 94-pin QFP.
(7) The EB-V25 MINI-IE-P and EB-V35 MINI-IE-P are supplied with an
84-pin PLCC cable.
(8) Contact your local NEC Sales Office for the latest information on
10-MHz emulation.
(9) Development for the pPD70327 or pPD70337 can be done using
the appropriate pPD70320 or pPD70330 tools; however, debugging the programs in the Software Guard mode is not supported
at this time.
(10) ThepPD70P322K EPROM device can be used for bothpPD70322
and pPD70332 emulation. The pPD70P322K EPROM device can
be programmed by using the PA-70P322L Programming Adapter
and the PG-1500 EPROM Programmer.
(11) For emulation of pPD79011 or pPD79021 , the base emulator
(IE-70320 or IE-70330) plus Real-Time Operating System software (IE-70320-RTOS or IE-70330-RTOS) is required.
(12) This emulation option is not currently supported, but may be
available in the future. Contact your local NEC Sales Office for
further information.
1-17
..
Development Tools for Micro Products
(13) The following relocatable assemblers are available:
RA70116-D52
For V20®N30®/
(MS-DOS@)
RA70116-VVT1
V40'MN50'M
(VAXNMS'M)
RA70116-VXT1
(VAX/UNIX'M 4.2 BSD
or Ultrix'M)
RA70136-D52
(MS-DOS)
RA70136-VVT1
(VAXNMS)
RA70136-VXT1
(VAX/UNIX 4.2 BSD or
Ultrix)
RA70320-D52
(MS-DOS)
RA70320-VVT1
(VAXNMS)
RA70320-VXT1
(VAX/UNIX 4.2 8SD or
Ultrix)
(14) The following C compilers are available:
For V20®N30®/
(MS-DOS)
CC70116-D52
CC70116-VVT1 V40'MN50'M
(VAXNMS)
(VAX/UNIX 4.2 8SD or
CC70116-VXT1
Ultrix)
CC70136-D52
(MS-DOS)
CC70136-VVT1
(VAXNMS)
CC70136-VXT1
(VAX/UNIX 4.2 8SD or
Ultrix)
(15) 84-pin PLCC probe shipped with IE-70325-BX and IE-70335-8X.
(16) The EV-9500GJ-94 is an adapter that converts the 84-pin PLCC
probe to a 94-pin QFP. Target sockets must also be purchased to
mate to this adapter. Target sockets are sold in packs of five as
part number EV-92006-94x5.
(17) The IE-70236-8X is shipped with the 132-pin PGA probe.
(18) The EV-9500GD-120 is an adapter that converts the 132-pin PGA
probe to a 120-pin QFP. Target sockets must also be purchased
to mate to this adapter. Target sockets are sold in packs of five as
part number EV-9200GD-120.
1-18
NEe
NEe
Development Tools for Micro Products
75xx Series Single-Chip Microcomputers
Device (Note 1)
Emulator*
Add-on Board*
System
Evaluation
Board
IlPD7502G·12
EVAKIT·7500B
EV·7514
SE·7514·A
ASM75
IlPD7502AGF·3B8
EVAKIT·7500B
EV·7514
SE·7514·A
ASM75
IlPD7503G·12
EVAKIT·7500B
EV·7514
SE·7514·A
ASM75
IlPD7503AGF·3B8
EVAKIT·7500B
EV·7514
SE·7514·A
IlPD7507C
EVAKIT·7500B
IlPD7507CU
EVAKIT·7500B
EPROM/OTP
Device
PG·1500
Adapter
(Note 2)
Absolute
Assembler
(Note 3)
II
ASM75
IlP D78CG08E
ASM75
ASM75
IlPD7507G·00
EVAKIT·7500B
ASM75
IlPD7507BCU
EVAKIT·7500B
ASM75
IlPD7507BG B·3B 4
EVAKIT·7500B
ASM75
IlPD7507HC
EVAKIT·7500B
EV·7508H
IlPD7507HCU
EVAKIT·7500B
EV·7508H
EV·7508H
IlPD75CG08HE
ASM75
ASM75
ASM75
IlPD7507HG·22
EVAKIT·7500B
IlPD7508C
EVAKIT·7500B
IlPD7508CU
EVAKIT·7500B
ASM75
IlPD7508G·00
EVAKIT·7500B
ASM75
IlPD7508BCU
EVAKIT·7500B
ASM75
IlPD7508BGB·3B4
EVAKIT·7500B
ASM75
IlPD75CG08E
EVAKIT·7500B
IlPD7508HC
EVAKIT·7500B
EV·7508H
IlPD78CG08E
ASM75
ASM75
IlP D78CG08HE
ASM75
IlPD7508HCU
EVAKIT·7500B
EV·7508H
ASM75
IlPD7508HG·22
EVAKIT·7500B
EV·7508H
ASM75
IlPD75CG08HE
EVAKIT·7500B
EV-750SH
IlPD7527AC
EVAKIT·7500B
EV·7528
IlPD7527ACU
EVAKIT·7500B
EV-7528
IlPD7528AC
EVAKIT·7500B
EV-7528
IlPD7528ACU
EVAKIT·7500B
EV·7528
IlPD75CG28E
EVAKIT·7500B
EV·7528
IlPD7533C
EVAKlT·7500B
EV·7533
IlPD7533CU
EVAKIT·7500B
EV-7533
IlPD7533G-22
EVAKIT·7500B
EV-7533
A~M75
IlPD75CG33E
EVAKIT·7500B
EV-7533
ASM75
IlPD7537AC
EVAKIT·7500B
EV-7528
IlPD7537ACU
EVAKIT·7500B
EV·7528
IlPD7538AC
EVAKIT·7500B
EV·7528
IlPD7538ACU
EVAKIT·7500B
EV-7528
ASM75
IlPD75CG38E
EVAKIT·7500B
EV-7528
ASM75
ASM75
IlPD78CG2SE
ASM75
IlPD78CG28E
ASM75
ASM75
ASM75
ASM75
IlPD75CG33E
ASM75
ASM75
IlP D75CG38E
ASM75
ASM75
IlP D75CG38E
ASM75
* Required tools
1-19
NEe
Development Tools for Micro Products
75xx Series Sing Ie-Chip Microcomputers (cant)
Add-on Board*
System
Evaluation
Board
EPROM/OlP
Device
PG-1500
Adapter
(Note 2)
Absolute
Assembler
(Note 3)
Device (Note 1)
Emulator*
IlPD7554CS
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P54CS
PA-75P54CS
ASM75
IlPD7554G
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P54G
PA-75P54CS
ASM75
IlPD7554ACS
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P54CS
PA-75P54CS
ASM75
IlPD7554AG
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P54G
PA-75P54CS
ASM75
. IlPD75P54CS
EVAKIT-7500B
EV-7554A
IlPD75P54G
EVAKIT-7500B
EV-7554A
IlPD7556CS
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P56CS
PA-75P56CS
pPD7556G
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P56G
PA-75P56CS
ASM75
IlPD7556ACS
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P56CS
PA-75P56CS
ASM75
IlPD7556AG
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P56G
PA-75P56CS
IlPD75P56CS
EVAKIT-7500B
EV-7554A
IlPD75P56G
EVAKIT-7500B
EV-7554A
IlPD7564CS
EVAKIT-7500B
EV-7554A
SE-7554-A
pPD75P64CS
PA-75P54CS
ASM75
IlPD7564G
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P64G
PA-75P54CS
ASM75
IlPD7564ACS
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P64CS
PA-75P54CS
ASM75
pPD7564AG
EVAKIT-7500B
EV-7554A
IlPD75P64G
PA-75P54CS
IlP075P64CS
EVAKIT-7500B
EV-7554A
IlPD75P64G
EVAKIT-7500B
EV-7554A
IlPD7566CS
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P66CS
PA-75P56CS
ASM75
IlPD7566G
EVAKIT-7500B
EV-7554A
SE-7554-A
IlPD75P66G
PA-75P56CS
ASM75
IlP07566ACS
EVAKIT-7500B
EV-7554A
SE-7554-A
IlP D75P66CS
PA-75P56CS
ASM75
IlPD7566AG
EVAKIT-7500B
EV-7554A
SE-7554-A
pPD75P66G
PA-75P56CS
ASM75
IlPD75P66CS
EVAKIT-7500B
EV-7554A
ASM75
IlPD75P66G
EVAKIT-7500B
EV-7554A
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
ASM75
SE-7554-A
ASM75
ASM75
ASM75
Notes:
(1) Packages:
C
40-pin plastic DIP (,uPD7507/07H/08/08H)
42-pin plastic DIP (,uPD7527A/28A/33/37A/38A)
CS
20-pin plastic shrink DIP
(,uPD7554/54NP54/64/64A/P64)
24-pin plastic shrink DIP
(,uP 07556/56A/P56/66/66A/P66)
CU
40-pin plastic shrink DIP
(,uP D7507/07B/07H/08/08B/08H)
42-pin plastic shrink DIP
(,uP 07527A/28N33/37A/38A)
E
40-pin ceramic piggy-back DIP (,uP075CG08/08H)
42-pin ceramic piggy-back DIP (,uPD75CG28/33/38)
G
20-pin plastic SO (,uPD7554/54A/P54/64/64NP64)
24-pin plastic SO (J,tPD7556/56NP56/66/66A/P66)
52-pin plastic QFP
G-OO
64-pin plastic QFP (2.05 mm thick) (,uP07502/03)
G-12
G-22
44-pin plastic QFP (1.45 mm thick)
GB-3B4
44-pin plastic QFP (2.7 mm thick)
GF-3B8
64-pin plastic QFP (2.7 mm thick)
1-20
(2) By using the specified adapter, the PG-1500 EPROM programmer
can be used to program the OTP device.
(3) The ASM75 Absolute Assembler is provided to run under the
MS-OOS® operating system. (ASM75-D52).
NEe
Development Tools for Micro Products
75xxx Series Single-Chip Microcomputers
Device (Note 5)
Emulator'"
JiPD75004CU
IE-75000-R
EP-75008CU-R
JiPD75004GB-3B4
IE-75000-R
EP-75008GB-R
JiPD75006CU
IE-75000-R
EP-75008CU-R
JiPD75006GB-3B4
IE-75000-R
EP-75008GB-R
JiPD75008CU
IE-75000-R
EP-75008CU-R
JiPD75008GB-3B4
IE-75000-R
EP-75008GB-R
Emulation Probe'"
JiPD75POO8CU
IE-75000-R
EP-75008CU-R
JiPD75POO8GB
IE-75000-R
EP-75008GB-R
JiPD75028CW
IE-75000-R
EP-75028CW-R
JiPD75028GC-AB8
IE-75000-R
EP-75028GC-R
JiPD75P036CW
IE-75000-R
EP-75028CW-R
JiPD75P036GC-AB8
IE-75000-R
EP-75028GC-R
JiPD75048CW
IE-75000-R
EP-75028CW-R
JiPD75048GC-AB8
IE-75000-R
EP-75028GC-R
Optional Socket
Adapter. (Note 1)
EPROM/OlP
Device (Note 2)
Relocatable
Assembler
(Note 3)
Structured
Assembler
(Note 4)
JiPD75POO8CU
RA75X
ST75X
EV-9200G-44
JiPD75POO8GB
RA75X
ST75X
JiPD75POO8CU
RA75X
ST75X
JiPD75POO8GB
RA75X
ST75X
JiPD75POO8CU
RA75X
ST75X
JiPD75POO8GB
RA75X
ST75X
RA75X
ST75X
RA75X
ST75X
JiPD75P036CW
RA75X
ST75X
JiPD75P036GC
RA75X
ST75X
RA75X
ST75X
EV-9200G-44
EV-9200G-44
EV-9200G-44
EV-9200GC-64
RA75X
ST75X
JiPD75P056CW
RA75X
ST75X
JiPD75P056GC
RA75X
ST75X
RA75X
ST75X
RA75X
ST75X
JiPD75P108CW/
DW/BCW
JiPD75P116CW
RA75X
ST75X
EV-9200GC-64
EV-9200GC-64
JiPD75P056CW
IE-75000-R
EP-75028CW-R
JiPD75P056GC-AB8
IE-75000-R
EP-75028GC-R
JiPD75104CW
IE-75000-R
EP-75108CW-R
JiPD75104G-1 B
IE-75000-R
EP-75108GF-R
EV-9200G-64
JiPD75P108G
JiPD75P116GF
RA75X
ST75X
JiPD75104GF-3BE
IE-75000-R
EP-75108GF-R
EV-9200G-64
JiPD75P108G/
BGF
JiPD75P116GF
RA75X
ST75X
EV-9200GC-64
EV-9200GC-64
RA75X
ST75X
JiPD75P108CW/
DW/BCW
JiPD75P116CW
RA75X
ST75X
EV-9200G-64
JiPD75P108G
JiPD75P116GF
RA75X
ST75X
EP-75108GF-R
EV-9200G-64
JiPD75P108G/
BGF
JiPD75P116GF
RA75X
ST75X
EP-75108AGC-R
EV-9200GC-64
JiPD75104AGC-AB8
IE-75000-R
EP-75108AGC-R
JiPD75106CW
IE-75000-R
EP-75108CW-R
JiPD75106G-1 B
IE-75000-R
EP-75108GF-R
JiPD75106GF-3BE
E-75000-R
JiPD75108AG-22
IE-75000-R
JiPD75108AGC-AB8
IE-75000-R
EP-75108AGC-R
JiPD75108CW
IE-75000-R
EP-75108CW-R
JiPD75108G-1 B
IE-75000-R
EP-75108GF-R
JiPD75108GF-3BE
IE-75000-R
EP-75108GF-R
JiPD75P108BCW
IE-75000-R
EP-75108CW-R
JiPD75P108BGF
IE-75000-R
EP-75108GF-R
RA75X
ST75X
RA75X
ST75X
JiPD75P108CW/
DW/BCW
JiPD75P116CW
RA75X
ST75X
EV-9200G-64
JiPD75P108G
JiPD75P116GF
RA75X
ST75X
EV-9200G-64
JiPD75P108G/
BGF
JiPD75P116GF
RA75X
ST75X
RA75X
ST75X
RA75X
ST75X
EV -9200GC-64
EV-9200G-64
II
1-21
NEe
Development Tools for Micro Products
75xxx Series Sing Ie-Chip Microcomputers (cont)
Device (Note 5)
Emulator*
Emulation Probe*
JlPD75P108CW
IE-75000-R
EP-75108CW-R
JlPD75P108DW
IE-75000-R
EP-75108CW-R
JlPD75P108G-1 B
IE-75000-R
EP-75108GF-R
JlPD75112CW
IE-75000-R
EP-75108CW-R
JlPD75112GF-3BE
IE-75000-R
EP-75108GF-R
JlPD75116CW
IE-75000-R
EP-75108 CW-R
JlPD75116GF-3BE
IE-75000-R
EP-75108GF-R
JlPD75P116CW
IE-75000-R
EP-75108CW-R
JlPD75P116GF
IE-75000-R
EP-75108GF-R
Optional Socket
Adapter (Note 1)
EPROM/OTP
Device (Note 2)
EV-9200G-64
JlPD75P116CW
EV-9200G-64
EV-9200G-64
Relocatable
Assembler
(Note 3)
Structured
Assembler
(Note 4)
RA75X
S175X
RA75X
S175X
RA75X
S175X
RA75X
S175X
JlPD75P116GF
RA75X
S175X
JlPD75P116CW
RA75X
S175X
JlPD75P116GF
RA75X
S175X
EV-9200G-64
RA75X
S175X
RA75X
S175X
JlPD75206CW
IE-75000-R
EP-75216ACW-R
RA75X
S175X
JlPD75206G-1 B
IE-75000-R
EP-75216AGF-R
EV-9200G-64
RA75X
S175X
JlPD75206GF-3BE
IE-75000-R
EP-75216AGF-R
EV-9200G-64
RA75X
S175X
JlPD75208CW
IE-75000-R
EP-75216ACW-R
RA75X
S175X
JlPD75208G-1 B
IE-75000-R
EP-75216AGF-R
EV-9200G-64
RA75X
S175X
JlPD75208GF-3BE
IE-75000-R
EP-75216AGF-R
EV-9200G-64
RA75X
S175X
JlPD75CG208E
IE-75000-R
EP-75216ACW-R
RA75X
S175X
JlPD75CG208EA
IE-75000-R
EP-75216AGF-R
RA75X
S175X
JlPD75212ACW
IE-75000-R
EP-75216ACW-R
JlPD75P216ACW
RA75X
S175X
JlPD75212AGF-3BE
IE-75000-R
EP-75216AGF-R
RA75X
S175X
JlPD75216ACW
IE-75000-R
EP-75216ACW-R
JlPD75P216ACW
RA75X
S175X
JlPD75216AGF
IE-75000-R
EP-75216AGF-R
RA75X
S175X
JlPD75CG216AE
IE-75000-R
EP-75216ACW-R
RA75X
S175X
JlPD75CG216AEA
IE-75000-R
EP-75216AGF-R
JlPD75P216ACW
IE-75000-R
EP-75216ACW-R
JlPD75217CW
IE-75000-R
EP-75216ACW-R
JlPD75217GF-3BE
IE-75000-R
EP-75216AGF-R
JlPD75P218CW
IE-75000-R
EP-75216ACW-R
JlPD75P218GF-3BE
IE-75000-R
EP-75216AGF-R
JlPD75P218KB
IE-75000-R
EP-75216AGF-R
JlPD75268CW
IE-75000-R
EP-75216ACW-R
JlPD75P216ACW
JlPD75P216ACW
EV-9200G-64
EV-9200G-64
EV-9200G-64
EV-9200G-64
RA75X
S175X
JlPD75P216ACW
RA75X
S175X
JlPD75P218CW
RA75X
S175X
JlPD75P218GF /KB
RA75X
S175X
RA75X
S175X
EV-9200G-64
RA75X
S175X
EV-9200G-64
RA75X
S175X
JlPD75P216ACW
RA75X
S175X
EV-9200G-64
JiPD75268GF-3BE
IE-75000-R
EP-75216AGF-R
EV-9200G-64
RA75X
S175X
JlPD75304GF-3B9
IE-75000-R
EP-75308GF-R
EV-9200G-80
JlPD75P308GF/K
RA75X
S175X
JlPD75306GF-3B9
IE-75000-R
EP-75308GF-R
EV -9200G-80
JlPD75P308GF/K
RA75X
S175X
JlPD75308GF-3B9
IE-75000-R
EP-75308GF-R
EV -9200G-80
JlPD75P308G F/K
RA75X
S175X
JlPD75P308GF
IE-75000-R
EP-75308GF-R
EV -9200G-80
RA75X
S175X
JlPD75P308K
IE-75000-R
EP-75308GF-R
EV-9200G-80
RA75X
S175X
JlPD75312GF-3B9
IE-75000-R
EP-75308GF-R
EV-9200G-80
JlPD75P316GF/
AGF/AK
RA75X
S175X
JlPD75316GF-3B9
IE-75000-R
EP-75308GF-R
EV-9200G-80
JlPD75P316GF/
AGF/AK
RA75X
S175X
1-22
NEe
Development Tools for Micro Products
75xxx Series Single-Chip Microcomputers (cont)
Structured
Assembler
(Note 4)
Emulator*
Emulation Probe*
IlPD75P316GF
IE-75000-R
EP-75308GF-R
EV-9200G-80
RA75X
ST75X
IlPD75P316AGF
IE-75000-R
EP-75308GF-R
EV-9200G-80
RA75X
ST75X
RA75X
ST75X
RA75X
ST75X
RA75X
ST75X
IlPD75P402C
RA75X
ST75X
IlPD75P402CT
RA75X
ST75X
IlPD75P402GB
RA75X
ST75X
Device (Note 5)
IlPD75P316AK
IE-75000-R
EP-75308GF-R
EV-9200G-80
IlPD75328GC-3B9
IE-75000-R
EP-75328GC-R
EV-9200GC-80
IlPD75P328GC-3B9
IE-75000-R
EP-75328GC-R
EV-9200GC-80
IlPD75402AC
IE-75000-R
EP-75402C-R
IlPD75402ACT
IE-75000-R
EP-75402C-R
IlPD75402AGB-3B4
IE-75000-R
EP-75402GB-R
EV-9200G-44
EPROM/OTP
Device (Note 2)
Relocatable
Assembler
(Note 3)
Optional Socket
Adapter (Note 1)
IlPD75P328GC
IlPD75P402C
IE-75000-R
EP-75402C-R
RA75X
ST75X
IlPD75P402CT
IE-75000-R
EP-75402C-R
RA75X
ST75X
IlPD75P402GB-3B4
IE-75000-R
EP-75402GB-R
EV-9200G-44
RA75X
ST75X
IlPD75512GF-3B9
IE-75000-R
EP-75516GF-R
EV-9200G-80
IlPD75P516GF/K
RA75X
ST75X
IlPD75516GF-3B9
IE-75000-R
EP-75516GF-R
EV-9200G-80
IlPD75P516GF/K
RA75X
ST75X
IlPD75P516GF
IE-75000-R
EP-75516GF-R
EV-9200G-80
RA75X
ST75X
IlPD75P516K
IE-75000-R
EP-75516GF-R
EV-9200G-80
II
Notes:
(1) The EV-9200G-XX is an LCC socket with the footprint of the flat
package. One unit is supp lied with the probe. Additional units
are available as replacement parts in sets of five.
(2) All EPROM/OTP devices can be programmed using the NEC
PG-1500. Refer to the PG-1500 Programming Socket Adapter
Selection Guide for the appropriate socket adapter.
(3) The RA75X relocatable assembler package is provided for the
following operating system:
RA75X-D52 (MS-DOS@)
(4) The ST75X structured assembler preprocessor is provided with
RA75X.
(5) Packages:
C
CT
CU
CW
OW
E
EA
G-1B
G-22
GB-3B4
GC-AB8
GC-3B9
GF-3BE
GF-3B9
K
KB
28-pin
28-pin
42-pin
64-pin
64-pin
64-pin
64-pin
64-pin
54-pin
44-pin
54-pin
80-pin
54-pin
80-pin
80-pin
54-pin
plastic DIP
plastic shrink DIP
plastic shrink DIP
plastic shrink DIP
ceramic shrink DIP with window
ceramic piggy-back shrink DIP
ceramic piggy-back QFP
plastic QFP (2.05 mm thick)
plastic QFP (1.55 mm thick)
plastic QFP
plastic QFP (2.55 mm thick)
plastic QFP
plastic QFP (2.77 mm thick)
plastic QFP
ceramic LCC
ceram ic LCC
* Requ ired tools.
1-23
NEe
De"elopment Tools for Micro Products
78xx Series Single-Chip Microcomputers
Device (Note 1)
t
Relocatable
Assembler
(Note 9)
C Complier
(Note 9)
Emulator*
Emulation Probe*
JlPD78C10CW
IE·78C11·M
EV·9001·64
(Note 3)
RA87
CG87
JlPD78C10G18
IE·78C11·M
(Note 5)
RA87
CC87
JlPD78C10GF·38E
IE·78C11·M
(Note 5)
RA87
CC87
IE·78C11·M
(Note 7)
RA87
CC87
JlPD78C10ACW
IE·78C11·M
EV·9001·64
(Note 3)
RA87
CC87
JlPD78C10AGQ36
IE·78C11·M
(Note 4)
RA87
CC87
JlPD78C10AGF
IE·78C11·M
(Note 5)
RA87
CC87
JlPD78C10AL
IE·78C11·M
(Note 7)
RA87
CC87
JlPD78C11 CW .
IE·78C11·M
EV·9001·64
(Note 3)
JlPD78CP14CW/DW
PA·78CP14CW
RA87
CC87
JlPD78C11 G·36
IE·78C11·M
{Note 4)
JlPD78CP14G36/R
JlPD78CP14E
PA·78CP14GQ
RA87
CC87
JlPD78C11G·18
IE·78C11·M
(Note 5)
JlPD78CP14GF
PA·78CP14GF
RA87
CC87
JlPD78C11 GF·38E
IE·78C11·M
(Note 5)
JlPD78CP14GF
PA·78CP14GF
RA87
CC87
JlPD78C11L
IE·78C11·M
(Note 7)
JlPD78CP14L
PA<78CP14L
RA87
CC87
JlPD78C11ACW
IE·78C11·M
EV·9001·64
(Note 3)
JlPD78CP14CW/DW
(Note 6)
PA·78CP14CW
RA87
CC87
JlPD78C11AGQ·36
IE·78C11·M
(Note 4)
JlPD78CP14G36/R
(Note 6)
PA·78CP14GQ
RA87
CC87
JlPD78C11AGF·38E
IE·78C11·M
(Note 5)
JlPD78CP14GF
(Note 6)
pA·78CP14GF
RA87
CC87
JlPD78C11AL
IE·78C11·M
(Note 7)
JlPD78CP14L
(Note 6)
PA·78CP14L
RA87
CC87
JlPD78C12ACW
IE·78C11·M
EV·9001·64
(Note 3)
JlPD78CP14CW/DW
(Note 6)
PA·78CP14CW
RA87
CC87
JlPD78C12AGQ
IE·78C11·M
(Note 4)
JlP D78CP14G36/R
(Note 6)
PA·78CP14GQ
RA87
CC87
JlPD78C12AGF
IE·78C11·M
(Note 5)
JlPD78CP14GF
(Note 6)
PA·78CP14GF
RA87
CC87
JlPD78C12AL
IE·78C11·M
(Note 7)
JlPD78CP14L
(Note 6)
PA·78CP14L
RA87
CC87
JlPD78C14CW
IE·78C11·M
EV·9001·64
(Note 3)
JlPD78CP14CW/DW
PA·78CP14CW
RA87
CC87
JlPD78C14G·36
IE·78C11·M
(Note 4)
JlP D78CP14G36/R
JlPD78CG14E
PA·78CP14GQ
RA87
CC87
. JlPD78C10L
EPROM/OTP Device
PG·1500
Adapter (Note 2)
JlPD78C14G·18
IE·78C11·M
(Note 5)
JlPD78CP14GF
PA·78CP14GF
RA87
CC87
JlPD78C14GF
IE·78C11·M
(Note 5)
JlPD78CP14GF
PA·78CP14GF
RA87
CC87
JlPD78C14L
IE·78C11·M
(Note 7)
JlPD78CP14L
PA·78CP14L
RA87
CC87
JlPD78C14AG·A88
IE·78C11·M
(Note 5)
RA87
CC87
JlPD78CG14E
(Note 8)
IE·78C11-M
(Note 4)
RA87
CC87
JlPD78CP14CW
IE-78C11-M
EV·9001·64
(Note 3)
RA87
CC87
1·24
PA·78CP14CW
NEe
Development Tools for Micro Products
78xx Series Single-Chip Microcomputers (cant)
Device (Note 1)
t
EPROM/OTP Device
PG-1S00
Adapter (Note 2)
Relocatable
Assembler
(Note 9)
C Compiler
(Note 9)
Emulator*
Emulation Probe*
pPD78CP14DW
IE-78C11-M
EV-9001-64
(Note 3)
PA-78CP14CW
RA87
CC87
pPD78CP14G36
IE-78C11-M
(Note 4)
PA-78CP14GQ
RA87
CC87
pPD78CP14GF
IE-78C11-M
(Note 5)
PA-78CP14GF
RA87
CC87
pPD78CP14L
IE-78C11-M
(Note 7)
PA-78CP14L
RA87
CC87
pPD78CP14R
IE-78C11-M
(Note 4)
PA-78CP14GQ
RA87
CC87
pPD78C17CW
IE-78C11-M
EV-9001-64
(Note 3)
RA87
CC87
pPD78C17GQ36
IE-78C11-M
(Note 4)
RA87
CC87
pPD78C17GF
IE-78C11-M
(Note 5)
RA87
CC87
pPD78C18CW
IE-78C11-M
EV-9001-64
(Note 3)
pPD78CP18CW
(Note 6)
PA-78CP14CW
RA87
CC87
pPD78C18GQ
IE-78C11-M
(Note 4)
pPD78CP18GQ
(Note 6)
PA-78CP14GQ
RA87
CC87
pPD78C18GF
IE-78C11-M
(Note 5)
pPD78CP18GF
(Note 6)
PA-78CP14GF
RA87
CC87
pPD78CP18KB
(Note 6)
PA-78CP14KB
PA-78CP14CW
RA87
CC87
pPD78CP18CW
IE-78C11-M
EV-9001-64
(Note 3)
pPD78CP18GQ
IE-78C11-M
(Note 4)
PA-78CP14GQ
RA87
CC87
pPD78CP18GF
IE-78C11-M
(Note 5)
PA-78CP14GF
RA87
CC87·
pPD78CP18KB
IE-78C11-M
(Note 5)
PA-78CP14KB
RA87
CC87
* Required tools
t For a" pPDC1 X devices, you
may use the DDK-78C10 for
evaluation purposes.
Notes:
(1) Packages:
CW
DW
E
G-1 B
G-36
G-AB8
GF-3BE
GQ-36
KB
L
R
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
68-pin
64-pin
II
plastic shrink DIP
ceramic shrink DIP with window
ceramic piggyback QUIP
plasticQFP (resin thickness 2.05 mm)
plastic QUIP
plastic QFP (interpin pitch 0.8 mm)
plastic QFP (resin thickness 2.7 mm)
plastic QUIP
ceramic LCC with window
PLCC
ceramic QUIP with window
(2) By using the specified adapter, the PG-1500 EPROM programmer
can be used to program the EPROM/OTP device.
(3) 64-pin shrink DIP adapter which plugs into the EP-7811 HGQ
emulation probe supplied with each IE.
(4) The emulation probe for the 64-pin QUIP package (EP-7811 HGQ)
is supplied with the IE.
(5) No emulation probe available.
(6) The pPD78CP14/CP18 EPROM/OTP devices do not have pull-up
resistors on ports A, -8, and C.
(7) The optional AS-QIP-PCC-D781X QUIP-to-PLCC adapter can be
used with the EP-7811 HGQ emulation probe .supplied with each
IE.
(8) The pPD78CG14E is a piggyback EPROM device in a ceramic
QUIP package. It accepts 27C256 and 27C256A EPROMs.
(9) The fo"owi.ng relocatable assemblers and C compilers are available:
RA87-D52
(MS-DOS®)
Relocatable assemblers for 78XX
RAB7-VVn
01AX/VMS~
series
CCMSD-15DD-87
CCMSD-15DD-87-16
CCVMS-OT16-87
CCUNX-OT16-87
(MS-DOS)
(MS-DOS;
extended memory)
01AX/VMS)
01AX/UNIXTM;
4.2 BSD or UltrixOi)
C Compilers
78XX Series
for
1-25
NEe
Development Tools for Micro Products
782xx Series Single-Chip Microcomputers
Device
(Notes 1; 2)
Evaluation
Kit
(Note 3)
Designer
Kit
(Note 4)
Emulator
Kit
. (Note 5)
IlPD78212CW
EK-78K2-21X
DK-78K221XCW
IlPD78212GC
EK-78K2-21X
IlPD78212GJ
Low-End
Emulator
Emulation
System
Emulation
Probe
EPROM/OTP
Device (Note 6)
IK-78K221XCW
EB-78210-PC
IE-78240-R
EP-78240CW-R
IlPD78P214CW/DW
DI<,.78K221XGC
IK-78K221XGC
EB-78210-PC
IE-78240-R
EP-78240GC-R
(Note 9)
IlPD78P214GC
EK-78K2-21X
DK-78K221XGJ
IK-78K221XGJ
EB-78210-PC
IE-78240-R
EP-78240GJ-R
(Note 7)
IlPD78P214GJ
IlPD78212GQ
EK-78K2-21X
DK-78K221XGQ
IK-78K221XGQ
EB-78210-PC
IE-78240-R
EP-78240GQ-R
IlPD78P214GQ
IlPD78212L
EK-78K2-21X
DK-78K221XL
IK-78K221XL
EB-78210-PC
IE-78240-R
EP-78240LP-R
IlPD78P214L
IlPD78213CW
EK-78K2-21X
DK-78K221XCW
IK-78K221XCW
EB-78210-PC
IE-78240-R
EP-78240CW-R
IlPD78213GC
EK-78K2-21X
DK-78K221XGC
IK-78K221XGC
EB-78210-PC
IE-78240-R
EP-78240GC-R
(Note 9)
IlPD78213GJ
EK-78K2-21X
DK-78K221XGJ
IK-78K221XGJ
EB-78210-PC
IE-78240-R
EP-78240GJ-R
(Note 7)
IlPD78213G36
EK-78K2-21X
DK-78K221XGQ
IK-78K221XGQ
EB-78210-PC
IE-78240-R
EP-78240GQ-R
IlPD78213L
EK-78K2-21X
DK-78K221XL
IK-78K221XL
EB-78210-PC
IE-78240-R
EP-78240LP-R
IlPD78214CW
EK-78K2-21X
DK-78K221XCW
IK-78K221XCW
EB-78210-PC
IE-78240-R
EP-78240CW-R
IlPD78P214CW/DW
IlPD78214GC
EK-78K2-21X
DK-78K221XGC
. IK-78K221XGC
EB-78210-PC
IE-78240-R
EP-78240GC-R
(Note 9)
IlPD78P214GC
IlPD78214GJ
EK-78K2-21X
DK-78K221XGJ
IK-78K221XGJ
EB-78210-PC
IE-78240-R
EP-78240GJ-R
(Note 7)
IlPD78P214GJ
IlPD78214G36
EK-78K2-21X
DK-78K221XGQ
IK-78K221XGQ
EB-78210-PC
IE-78240-R
EP-78240GQ-R
IlPD78P214GQ
IlPD78214L
EK-78K2-21X
DK-78K221XL
IK-78K221XL
EB-78210-PC
IE-78240-R
EP-78240LP-R
IlPD78P214L
IlPD78P214CW
EK-78K2-21X
DK-78K221XCW
IK-78K221XCW
EB-78210-PC
IE-78240-R
EP-78240CW-R
IlPD78P214DW
EK-78K2-21X
DK-78K221XCW
IK-78K221XCW
EB-78210-PC
IE-78240-R
EP-78240CW-R
IlPD78P214GC
EK-78K2-21X
DK-78K221XGC
IK-78K221XGC
EB-78210-PC
IE-78240-R
EP-78240GC-R
(Note 9)
IlPD78P214GJ
EK-78K2-21X
DK-78K221XGJ
IK-78K221XGJ
EB-78210-PC
IE-78240-R
EP-78240GJ-R
(Note 7)
IlPD78P214GQ
EK-78K2-21X
DK-78K221XGQ
IK-78K221XGQ
EB-78210-PC
IE-78240-R
EP-78240GQ-R
IlPD78P214L
EK-78K2-21X
DK-78K221XL
IK-78K221XL
EB-78210-PC
IE-78240-R
EP-78240LP-R
IlPD78220GJ
EK-78K2-22X
DK-78K222XGJ
IK-78K222XGJ
EB-78220-PC
IE-78230-R
EP-78230GJ-R
(Note 8)
IlPD78220L
EK-78K2-22X
DK-78K222XL
IK-78K222XL
EB-78220-PC
IE-78230-R
EP-78230LQ-R
IlPD78224GJ
EK-78K2-22X
DK-78K222XGJ
IK-78K222XGJ
EB-78220-PC
IE-78230-R
EP-78230GJ-R
(Note 8)
1-26
IlPD78P224GJ
NEe
Development Tools for Micro Products
782xx Series Sing Ie-Chip Microcomputers (cont)
Device
(Notes 1,2)
Evaluation
Kit
(Note 3)
Designer
Kit
(Note 4)
Emulator
Kit
(Note 5)
pPD78224L
EK-78K2-22X
DK-78K222XL
pPD78P224GJ
EK-78K2-22X
pPD78P224L
Low-End
Emulator
Emulation
System
Emulation
Probe
EPROM/OTP
Device (Note 6)
IK-78K222XL
EB-78220-PC
IE-78230-R
EP-78230LQ-R
pPD78P224L
DK-78K222XGJ
IK-78K222XGJ
EB-78220-PC
IE-78230-R
EP-78230GJ-R
(Note 8)
EK-78K2-22X
DK-78K222XL
IK-78K222XL
EB-78220-PC
IE-78230-R
EP-78230LQ-R
pPD78233GC
EK-78K2~23X
DK-78K223XGC
IK-78K223XGC
EB-78230-PC
IE-78230-R
EP-78230GC-R
(Note 10)
pPD78233GJ
EK-78K2-23X
DK-78K223XGJ
IK-78K223XGJ
EB-78230-PC
IE-78230-R
EP-78230GJ-R
(Note 8)
pPD78233LQ
EK-78K2-23X
DK-78K223XL
IK-78K223XL
EB-78230-PC
IE-78230-R
EP-78230LQ-R
pPD78234GC
EK-78K2-23X
DK-78K223XGC
IK-78K223XGC
EB-78230-PC
IE-78230-R
EP-78230GC-R
(Note 10)
pPD78P238GC
pPD78234GJ
EK-78K2-23X
DK-78K223XGJ
IK-78K223XGJ
EB-78230-PC
IE-78230-R
EP-78230GJ-R
(Note 8)
pPD78P238GJ/KF
pPD78234LQ
EK-78K2-23X
DK-78K223XL
IK-78K223XL
EB-78230-PC
IE-78230-R
EP-78230LQ-R
pPD78P238LQ
pPD78237GC
EK-78K2-23X
DK-78K223XGC
IK-78K223XGC
EB-78230-PC
IE-78230-R
EP-78230GC-R
(Note 10)
pPD78237GJ
EK-78K2-23X
DK-78K223XGJ
IK-78K223XGJ
EB-78230-PC
IE-78230-R
EP-78230GJ-R
(Note 8)
pPD78237LQ
EK-78K2-23X
DK-78K223XLQ
IK-78K223XLQ
EB-78230-PC
IE-78230-R
EP-78230LQ-R
pPD78238GC
EK-78K2-23X
DK-78K223XGC
IK-78K223XGC
EB-78230-PC
IE-78230-R
EP-78230GC-R
(Note 10)
pPD78P238GC
pPD78238GJ
EK-78K2-23X
DK-78K223XGJ
IK-78K223XGJ
EB-78230-PC
IE-78230-R
EP-78230GJ·R
(Note 8)
pPD78P238GJ/KF
pPD78238LQ
EK·78K2-23X
DK-78K2·
23XLQ
IK-78K223XLQ
EB-78230-PC
IE-78230-R
EP-78230LQ·R
pPD78P238LQ
pPD78P238GC
EK-78K2-23X
DK-78K223XGC
IK-78K223XGC
EB-78230-PC
IE-78230-R
Ep·78230GC-R
(Note 10)
pPD78P238GJ
EK-78K2-23X
DK-78K223XGJ
IK-78K223XGJ
EB-78230-PC
IE·78230-R
Ep·78230GJ·R
(Note 8)
pPD78P238KF
EK-78K2-23X
DK-78K223XGJ
IK-78K223XGJ
EB-78230-PC
IE-78230-R
EP-78230GJ·R
(Note 8)
pPD78P238LQ
EK-78K2-23X
DK-78K223XL
IK-78K223XL
EB-78230-PC
IE-78230·R
EP-78230LQ·R
pPD78243CW
EK-78K2-24X
DK-78K224XCW
IK-78K224XCW
EB-78240-PC
IE-78240-R
Ep·78240CW-R
pPD78243GCAB8
EK-78K2-24X
DK-78K224XGC
IK-78K224XGC
EB-78240-PC
IE-78240-R
EP-78240GC·R
(Note 9)
pPD78243LP
EK-78K2-24X
DK-78K224XLP
IK-78K224XLP
EB-78240-PC
IE-78240-R
EP-78240LP-R
pPD78244CW
EK-78K2·24X
DK-78K224XCW
IK-78K224XCW
EB-78240-PC
IE-78240-R
EP·78240CW-R
pPD78244GC
EK-78K2-24X
DK-78K224XGC
IK-78K224XGC
EB-78240-PC
IE-78240·R
EP-78240GC·R
(Note 9)
..
1-27
NEe
Development Tools for Micro Products
782xx Series Sing Ie-Chip
Microcomput~rs
(cont)
Device
(Notes 1,2)
Evaluation
Kit
(Note 3)
Designer
Kit
(Note 4)
Emulator
Kit
(Note 5)
JiPD78244L
EK-78K2-24X
DK-78K224XLP
IK-78K224XLP
EB-78240-PC
Notes:
(1) The following software packages are available for the 782xx
Series.
RA78K2 Relocatable Assembler Package: RA78K2-D52
(MS-DOS®)
ST78K2 Structured Assembler Preprocessor: provided with
RA78K2
CC78K2 C-Compiler package: CC78K2-D52 (MS-DOS)
(2) Packages:
CW
DW
G36
GC
GG
GC-ABS
GJ
GJ
GQ
KF
L
LP
LQ
Emulation
'System
Low-End
Emulator
64-pin plastic shrink DIP
64-pin ceramic shrink DIP with window
64-pin plastic QUIP (uPD78213/214)
64-pin plastic QFP (uPD78212/213/214/P214/244)
80-pin plastic QFP (uPD78233/234/237/238/P238)
64-pin plastic QFP
94-pin plastic QFP (uPD78220/224/P224/233/234/
237/238/P238)
74-pin plastic QFP (uPD78212/213/214/P214)
64-pin plastic QUIP (uPD78212/P214)
94-pin ceramic LCC with window
68-pin PLCC (uPD78213/214/P214L)
84-pin PLCC (uPD78220/224/P224L)
68-pin PLCC
84-pin PLCC
(3) The JiPD782xx Evaluation Kit contains the appropriate DDB78K2-2xx Evaluation Board for the part selected, the RA78K2
Relocatable Assembler Package, and the ST78K2 Structured
Assembler Preprocessor.
IE-78240-R
Emulation
Probe
EPROM/OTP
Device (Not& 6)
EP-78240LP-R
(4) The JiPD782xx Designer Kit contains the approp'riate EB~
782xx-PC low-end emulator and emulation probe for the part
selected" the RA78K2 Relocatable Assembler Package, and the
ST78K2 Structured Assembler Preprocessor.
(5) The JiPD782xx Emulator Kit contains the appropriate IE-782xx
system and emulation probe for the part selected, the RA78K2
Relocatable Assembler Package, and the ST78K2 Structured
Assembler Preprocessor.
(6) All EPROM/OTP devices can be programmed using the NEC
PG-1500. Refer to the PG~1500 Programming Socket Adapter
Selection Guide for the appropriate programming adapter.
(7) The EP-78240GJ-R Emulation Probe is shipped with one EV9200G-74, a 74-pin LCC'socket with the footprint of the OFP
package. Additional s,ockets are available as replacement parts
in sets of five.
'
(8) The EP-78230GJ-R Emulation Probe is shipped with one EV9200G-94, a 94-pin LCC socket with the footprint of the OFP
package. Additional sockets are available as r,eplacement parts
in sets of five.
(9) The EP-78240GC-R Emulation Probe is shipped with one EV9200GC-64, a 64-pin LCC socket with the footprint of the OFP
package. Additional sockets are available as replacement parts
in set$ Of five.
(10) The EP-78230GC-R Emulation Probe is shipped with one EV9200GC-80, an 80-pin LCC socket with the footprint of the OFP
package: Additional sockets are available as:replacement parts
in sets of five.
783xx Series Single-Chip Microcomputers
Emulator Kit
(Note 4)
Evaluation
Board
Emulation
Syste",
JiPD78310ACW
IK-78K3-31 XACW
(Note 6)
DDK-78310A
IE-78310A-R
EP-7'8310CW
(Note 7)
JiPD78310AGF 3BE
IK-78K3-31 XAGF
DDK-78310A
IE-78310A-R
EP-78310GF (Note 8)
JiPD78310AGO-36
IK-78K3-31XACW
(Note 6)
DDK-78310A
IE-7831OA-R
EP-78310GO
(Note 9)
JiPD78310AL
IK-78K3-31 XAL
DDK-78310A
IE-78310A-R
EP-78310L
JiPD78312ACW
IK-7SK3-31XACW
(Note 6)
DDK-78310A
IE-78310A-R
EP-78310CW
(Note '7)
JiPD78312AGF
IK-78K3-31XAGF
DDK-78310A
IE-78310A-R
EP-78310GF (Note 8)
JiPD78P312AGF
JiPD78312AGO
IK-78K3-31XACW
(Note 6)
DDK-78310A
IE-78310A-R
EP-78310GO
(Note 9)
JiPD78P312AGO/RQ
JiPD78P312AL
Device (Notes 1, 2)
Evaluation Kit
(Note 3)
Emulation Probe
JiPD78312AL
IK-78K3-31 XAL
DDK-78310A
IE-18310A-R
EP-78310L
JiPD78P312ACW
IK-78K3-31XACW
(Note 6)
DDK-78310A
IE-78310A-R
EP-78310CW
(Note 7)
JiPD78P312ADW
IK-78K3-31XACW
(Note 6) .
DDK-78310A
IE-78310A-R
EP-78310CW
1-28
(N,01~
i)
EPROM/OTP
Device (Note 5)
JiPD78P312ACW/DW
NEe
Development Tools for Micro Products
783xx Series Single-Chip Microcomputers (cont)
Emulator Kit
(Note 4)
Evaluation
Board
Emulation
System
pPD78P312AGF
IK-78K3-31 XAGF
DDK-78310A
IE-78310A-R
EP-78310GF
(Note 8)
pPD78P312AGQ-36
IK-78K3-31 XACW
(Note 6)
DDK-78310A
IE-78310A-R
EP-78310GQ
(Note 9)
pPD78P312AL
IK-78K3-31 XAL
DDK-78310A
IE-78310A-R
EP-78310L
/.tPD78P312ARQ
IK-78K3~31XACW
DDK-78310A
IE-78310A-R
EP-78310GQ
(Note 9)
Device (Notes 1, 2)
Eval uation Kit
(Note 3)
(Note 6)
Emulation Probe
EPROM/OTP
Device (Note 5)
II
j.lPD78320GJ
EK-78K3-32X
IK-78K3-32XGJ
EB-78320PC
IE-78327-R
EP-78320GJ-R
(Note 10)
pPD78320L
EK-78K3-32X
IK-78K3-32XL
EB-78320PC
IE-78327-R
EP-78320L-R
pPD78322GJ
EK-78K3-32X
IK-78K3-32XGJ
EB-78320PC
IE-78327-R
EP-78320GJ-R
(Note 10)
pPD78P322GJ/KD
pPD78322L
EK-78K3-32X
IK-78K3-32XL
EB-78320PC
IE-78327-R
EP-78320L-R
pPD78P322L/KC
pPD78P322GJ
EK-78K3-32X
IK-78K3-32XGJ
EB-78320PC
IE-78327-R
EP-78320GJ-R
(Note 10)
pPD78P322KC
EK-78K3-32X
IK-78K3-32XL
EB-78320PC
IE-78327-R
EP-78320L-R
pPD783P322KD
EK-78K3-32X
IK-78K3-32XGJ
EB~78320-
IE-78327-R
EP-78320GJ-R
(Note 10)
PC
pPD78P322L
EK-78K3-32X
IK-78K3-32XL
EB-78320PC
IE-78327-R
EP-78320L-R
pPD78330GJ
EK-78K3-33X
IK-78K3-33XGJ
EB-78330PC
IE-78330-R
EP-78330GJ-R
(Note 11)
pPD78330LQ
EK-78K3-33X
IK-78K3-33XLQ
EB-78330PC
IE-78330-R
EP-78330LQ-R
pPD78334GJ
EK-78K3-33X
IK-78K3-33XGJ
EB-78330PC
IE-78330-R
EP-78330GJ-R
(Note 11)
pPD78P334GJ
pPD78334LQ
EK-78K3-33X
IK-78K3-33XLQ
EB-78330PC
IE-78330-R
EP-78330LQ-R
pPD78P334LQ/KE
pPD78P334GJ
EK-78K3-33X
IK-78K3-33XGJ
EB-78330PC
IE-78330-R
EP-78330GJ-R
(Note 11)
pPD78P334KE
EK-78K3-33X
IK-78K3-33XLQ
EB-78330PC
IE-78330-R
EP-78330LQ-R
pPD78P334LQ
EK-78K3-33X
IK-78K3-33XLQ
EB-78330PC
IE-78330-R
EP-78330LQ-R
Notes:
(1) The following software packages are available. for the pPD783xx
series:
RA78K3 Relocatable Assembler Package: RA78K3-D52
(MS-DOS@}
ST78K3 Structured Assembler Preprocessor: provided with
RA78K3
CC78K3 C-Compiler Package: CC78K3-D52 (MS-DOS)
1-29
NEe
Development Tools for Micro Products
(2) Packages:
CW
DW
GF-3BE .
GJ-58G
GJ-58J
GQ-36
KC
KD
KE
L
LQ
R
(5) All EPROM/OTP devices can be programmed using the NEC
PG-1500. Refer to the PG-1500 Programming Socket Adapter
Selection Guide for the appropriate programming adapter.
64-pin plastic shrink DIP
64-pin ceramic shrink DIP with window
64-pin plastic QFP (resin thickness 2.7 mm)
94-pin plastic QFP
74-pin plastic QFP (20 mm x 20 mm)
64-pin plastic QUIP
68-pin ceramic LCC with window
74-pin ceramic LCC with window
84-pin ceramic LCC with window
44-pin PLCC (pPD71 P301 L)
68-pin PLCC
(pP D7831 OA/312A/P312A L, IlPD78320/322L)
84-pin PLCC
64-pin ceramic QUIP with window
(6) The IK-78K3-31XACW is shipped with the emulation probes for
both the 64-pin shrink DIP and 64-pin QUIP packages.
(7) The emulation probe -for the 64-pin shrink DIP package (EP78310CW) is supplied with the IE.
(8) The EP-78310GF Emulation Probe is shipped with one EV-9200G64, a 64-pin LCC socket with the footprint of the QFP package.
Additional sockets are available as replacement parts in sets of
five.
(9) The emulation probe for the 64-pin QUIP package (EP-78310GQ)
is supplied with the IE.
(3) The IlPD783xx Evaluation Kit contains the appropriate EB783xx-PC evaluation board for the part selected, the RA78K3
Relocatable Assembler Package, and the ST78K3 Structured
Assembler Preprocessor.
(4) The IlPD783xx Emulator Kit contains the appropriate IE-783xx
and Emulation Probe for the part selected, the RA78K3 Relocatable Assembler Package, and the ST78K3 Structured Assembler
Preprocessor.
(10) The EP-78320GJ-R Emulation Probe is shipped with one EV9200G-74, a 74-pin LCC socket with the footprint of the OFP
package. Additional sockets are available as replacement parts
in sets of five.
(11) The EP-78330GJ-R Emulation Probe is shipped with one EV9200G-94, a 94-pin LCC socket with the footprint of the OFP
package. Additional sockets are available as replacement parts
in sets of five.
DSP and Speech Products
Device
(Note 7)
Emulator
Evaluation
Board
Assembler
(Note 1)
Simulator
(Note 2)
EPROM/OTP
Device
PG-1S00 Adapter
(Note 3)
(Note 5)
IlPD77P20D
EVAKIT-77208
ASM77
SM77C25
IlPD77C20AC
EVAKIT-77208
ASM77
SM77C25
pPD77P20D
IlPD77C20AGW
EVAKIT-77208
ASM77
SM77C25
pPD77P20D
IlPD77C20AL
EVAKIT-77208
ASM77
SM77C25
IlPD77C20ALK
EVAKIT-77208
ASM77
SM77C25
IlPD77220L
EVAKIT-77230
RA77230
SM77230,
SIM77230
IlPD77220R
EVAKIT-77230
RA77230
SM77230,
SIM77230
IlPD77P220L
EVAKIT-77230
RA77230
SM77230
SIM77230
PA-77P220L
IlPD77P220R
EVAKIT-77230
RA77230
SM77230,
SIM77230
PA-77P230R
IlPD77230AR
EVAKIT-77230
RA77230
SM77230,
S.IM77230
IlPD77P230R
PA-77P230R
IlPD77230AR-003
EVAKIT-77230
DDK-77230
RA77230
SM77230,
SIM77230
pPD77P230R
PA-77P230R
IlPD77P230AR
EVAKIT-77230
DDK-77230
RA77230
SM77230,
SIM77230
IlPD77P230R
PA-77P230R
pPD77240R
IE-77240
IE-77240
RA77240
SIM77240
pPD77C25C
EVAKIT-77C25
RA77C25
SM77C25
pPD77P25C/D
PA~77P25C
IlPD77C25GW
EVAKIT-77C25
RA77C25
SM77C25
pPD77P25GW
pPD77C25L
EVAKIT-77C25
RA77C25
SM77C25
IlPD77P25L
pPD77P25C
EVAKIT-77C25
RA77C25
SM77C25
PA-77P25C
pPD77P25D
EVAKIT-77C25
RA77C25
SM77C25
PA-77P25C
pPD77P25GW
EVAKIT-77C25
RA77C25
SM77C25
PA-77P25GW
1-30
DDK-77220
(Note 8)
DDK-77220
(Note 8)
IlPD77P220R (EPROM)
IlPD77P220L (OTP)
PA-77P230R
PA-77P25L
NEe
Development Tools for Micro Products
DSP and Speech Products (cont)
Device
(Note 7)
Emulator
Evaluation
Board
Assembler
(Note 1)
Simulator
(Note 2)
RA77C25
SM77C25
EPROM/OTP
Device
PG-1500 Adapter
(Note 3)
IlPD77P25L
EVAKIT-77C25
IlPD7755C
NV-300 System
(Note 9)
EB-7759
IlPD77P56CR
PA-77P56C
IlPD7755G
NV-300 System
(Note 9)
EB-775/NV-310
(Note 6)
IlPD77P56G
(Note 10)
PA-77P56C
IlPD7756C
NV-300 System
(Note 9)
EB-775/NV -310
IlPD77P56CR
(Note 10)
PA-77P56C
IlPD7756G
NV-300 System
(Note 9)
EB-775/NV-310
(Note 6)
IlPD77P56G
(Note 10)
PA-77P56C
JlPD77P56CR
NV-300 System
(Note 9)
EB-775/NV-310
PA-77P56C
JlPD77P56G
NV-300 System
(Note 9)
EB-775/NV-310
(Note 6)
PA-77P56C
JlPD7757C
NV-300 System
(Note 9)
EB-775/NV-310
JlPD7757G
NV-300 System
(Note 9)
EB-775/NV-310
(Note 6)
JlPD7759C
NV-300 System
(Note 9)
EB-775/NV-310
JlPD7759GC
NV-300 System
(Note 9)
EB-775/NV-310
JlPD77501 GC
NV-300 System
(Note 9)
IlP D7781 OL
IE-77810
RA7781 0
IlPD77810R
IE-77810
RA7781 0
PA-77P25L
II
Notes:
(1) The following assemblers are available:
ASM77-D52
Assembler for 7720 (MS-DOS@)
RA77C25-D52
Assembler for 77C25 (MS-DOS)
RA77C 25-VV T1 Assembler for 77C25 (VAXNMsn')
RA77230-D52
Assembler for 77230 (MS-DOS)
RA77230-VVT1 Assembler for 77230 (VAXNMS)
RA77230-VXT1 Assembler for 77230 (VAX/UNIXTM 4.2 BSD or
UltrixTM)
(2) The following simulators are available:
SIM77230-VVT1 Simulator for 77230 (VAX/UNIX)
SIM77230-VXT1 Simulator for 77230 (VAX/UNIX TI• 4.2 BSD or
Ultrix)
SM77C25
Simulator for 77C25 (IBM-PC)
SM77230
Simulator for 77220, 77230 (IBM-PC)
SIM77240
Simulator for 77240 (IBM-PC)
(3) By using the specified adapter, the NEC PG-1500 EPROM
programmer can be used to program the EPROM/OTP device.
(4) Please check with your NEC Sales Representative on the availability of a PLCC emulation probe.
(5) The IlPD77P20D can be programmed using the EVAKIT-7720B.
(6) The EB-775 comes with an emulation probe for only the 18-pin
DIP.
(7) Packages:
C
D
G
GC
L
LK
R
GW
18, 28, or 40-pin plastic DIP
28-pin ceramic DIP
24-pin plastic SOP
52-pin plastic QFP
44-or 68-pin PLCC
28-pin PLCC
68-pin ceramic PGA
32-pin SOP
(8) DDK-77220 is supported by Hypersignal Workstation/Window, a
DSP software platform from Hyperception.
(9) The NV-300 current version is Version 3.0. An upgrade from
previous versions (hardware and software) is available under the
designation NV-301.
(10) The NV-310 emulation board includes a simple 77P56 programmer module.
1-31
NEe
Development Tools for Micro Products
PG-1500 Programming Adapters
Target Chip
Socket Adapter
(Note 1)
Adapter Module
(Note 2)
Standard 27xxx EPROM Devices
IlPD27256 (21 V)
IlPD27256A (12.5 V)
IlPD27C256 (21 V)
027A Board
027A Board
027A Board
IlPD27C256A (12.5 V)
IlPD27C512
IlPD27C1000
027A Board
027A Board
027A Board
IlPD27C1001
IlPD27C1024
027A Board
027A Board
75xx Series Devices
Target Chip
Socket Adapter
(Note 1)
Adapter Module
(Note 2)
IlPD78CP14GF
IlPD78CP14L
IlPD78CP14R
PA-78CP14GF
PA-78CP14L
PA-78CP14GQ
027A Board
027A Board
027A Board
IlPD78CP18CW
IlPD78CP18GQ
IlPD78CP18GF
PA-78CP14CW
PA-78CP14GQ
PA-78CP14GF
027A Board
027A Board
027A Board
IlPD78CP18KB
PA-78CP14KB
027A Board
IlPD78P214CW
IlPD78P214GC
IlPD78P214GJ
PA-78P214CW
PA-78P214GC
PA-78P214GJ
027A Board
027A Board
027A Board
IlPD78P214GQ
IlPD78P214L
IlPD78P224GJ
PA-78P214GQ
PA-78P214L
PA-78P224GJ
027A Board
027A Board
027A Board
IlPD78P224L
IlPD78P238GC
IlPD78P238GJ
PA-78P224L
PA-78P238GC
PA-78P238GJ
027A Board
027A Board
027A Board
IlPD78P238KF
IlPD78P238LQ
PA-78P238KF
PA-78P238LQ
027A Board
027A Board
IlPD78P312ACW
IlPD78P312ADW
IlPD78P312AGF
PA-78P312CW
PA-78P312CW
PA-78P312GF
027A Board
027A Board
027A Board
IlPD78P312AGQ
IlPD78P312AL
IlPD78P312ARQ
PA-78P312GQ
PA-78P312L
PA-78P312GQ
027A Board
027A Board
027A Board
IlPD78P322GJ
IlPD78P322KC
IlPD78P322KD
PA-78P322GJ
PA-78P322KC
PA-78P322KD
027A Board
027A Board
027A Board
IlPD78P322L
IlPD78P334GJ
IlPD78P334KE
PA-78P322L
PA-78P334GJ
PA-78P334KE
027A Board
027A Board
027A Board
IlPD78P334LQ
PA-78P334LQ
027A Board
PA-70P322L
027A Board
782xx Series Devices
IlPD75P54CS
IlPD75P54G
IlPD75P56CS
PA-75P54CS
PA-75P54CS
PA-75P56CS
04A Board
04A Board
04A Board
IlPD75P56G
IlPD75P64CS
IlPD75P64G
PA-75P56CS
PA-75P54CS
PA-75P54CS
04A Board
04A Board
04A Board
IlPD75P66CS
IlPD75P66G
PA-75P56CS
PA-75P56CS
04A Board
04A Board
IlPD75POO8CU
IlPD75POO8GB
IlPD75P036CW
PA-75POO8CU
PA-75POO8CU
PA-75P036CW
04A Board
04A Board
04A Board
IlPD75P036GC
IlPD75P108BCW
IlPD75P108CW
PA-75P036GC
PA-75P108CW
PA-75P108CW
04A Board
04A Board
04A Board
IlPD75P108DW
IlPD75P108BGF
IlPD75P108G
PA-75P108CW
PA-75P116GF
PA-75P108G
04A Board
04A Board
04A Board
IlPD75P116CW
IlPD75P116GF
IlPD75P216ACW
PA-75P108CW
PA-75P116GF
PA-75P216ACW
04A Board
04A Board
04A Board
IlPD75P218CW
IlPD75P218GF
IlPD75P218KB
PA-75P216ACW
PA-75P218GF
PA-75P218KB
04A Board
04A Board
04A Board
IlPD75P308GF
IlPD75P308K
IlPD75P316GF
PA-75P308GF
PA-75P308K
PA-75P308GF
04A Board
04A Board
04A Board
IlPD75P316AGF
IlPD75P316AK
IlPD75P328GC
PA-75P308GF
PA-75P308K
PA-75P328GC
04A Board
04A Board
04A Board
IlPD77P56CR
IlPD77P56G
IlPD77P25C
PA-77P56C
PA-77P56C
PA-77P25C
04A Board
04A Board
027A Board
IlPD75P402C
IlPD75P402CT
IlPD75P402GB
(Note 3)
PA-75P402CT
PA-75P402GB
027A Board
027A Board
027A Board
IlPD77P25D
IlPD77P220R
IlPD77P230R
PA-77P25C
PA-77P230R
PA-77P230R
027A Board
027A Board
027A Board
IlPD75P516GF
IlPD75P516K
PA-75P516GF
PA-75P516K
04A Board
04A Board
Notes:
75xxx Series Devices
1-32
V-Series Devices
IlPD70P322K
Digital Signal Processors
(1) Adapters must be purchased separately.
78xx Series Devices
IlPD78CP14CW
IlPD78CP14DW
IlPD78CP14G36
783xx Series Devices
PA-78CP14CW
PA-78CP14CW
PA-78CP14GQ
027A Board
027A Board
027A Board
(2) The 27A and 04A Adapter Modules are shipped with the PG-1500.
(3) The IlPD75P402C does not require a programming socket
adapter. It can be plugged directly into the 027A board.
NEe
Reliability and Quality Control
'L1
IJ
NEe
Reli abi lity and Quality Control
Section 2
Reliability and Quality Control
Introduction
2-3
Built-In Quality and Reliability
2-3
Technology Description
2-3
Approaches to Total Quality Control
2-3
Implementation of Quality Control
2-5
Reliability Testing
2-7
Life Distribution
2-7
Failure Distribution at NEC
2-7
Infant Mortality Failure Screening
2-8
Long-Term Failure Rate
2-8
Accelerated Reliability Testing
2-8
Failure Rate Calculation/Prediction
2-9
Product/Process Changes
2-10
Failure Analysis
2-10
NEC's Goals on Failure Rates
2-10
Summary and Conclusion
2-10
Figure 1. Quality Control System Flowchart
2-5
Figure 2. New Product Development Flow
2-6
Figure 3. Electrical Testing and Screening
2-6
Figure 4. Reliability Life (Bathtub) Curve
2-7
Figure 5. Typical Reliability Test Results
2-9
Figure 6. NEC Quality and Reliability Targets
2-10
Appendix 1. Typical QC Flow
2-12
Appendix 2. Typical Reliability Assurance Tests
2-15
Appendix 3. New Product/Process Change
Tests
2-16
Appendix 4. Failure Analysis Flowchart
2-17
??
NEe
Reliability and Quality Control
Introduction
Approaches to Total Quality Control
As large-scale integration reaches a higher level of density, the reliability of individual devices imposes a more
profound impact on system reliability. Great emphasiS has
thus been placed on assuring device reliability.
TOC activities are geared towards total satisfaction of the
customer. The success of these activities is dependent
upon the total commitment of management to enhancing
employee development, maintaining a customer-first attitude, and fulfilling community responsibilities.
Conventionally, performing reliability tests and attaining
feedback from the field are the only methods by which
reliability has been monitored and measured. At these
higher levels of LSI density, however, it is increasingly
difficult to activate all of the internal circuit elements in a
device, moreover, to detect the degradation of those
elements by measuring characteristics across external
terminals. As a result, testing alone may not provide
enough information to insure today's demanding reliability
requirements. A different philosophy and methodology is
needed for reliability assurance.
In orderto guarantee and improve a high level of reliability
for large-scale integrated circuits, it is essential to build
quality and reliability into the product. Then, conventional
testing can be performed to confirm that the product
demonstrates acceptable reliability.
Built-In Quality and Reliability
NEC has introduced the concept of total quality control
(TOC) across its entire semiconductor product line for
implementing this philosophy. Rather than performing
only a few simple quality inspections, quality control is
distributed into each process step and then summed to
form a consolidated system. TOC involves workers, engineers, quality control staffs, and all levels of management in company-wide activities. Please see Figure 1 for
the quality control system flowchart. Through TOC, NEC
builds quality into the product and thus can assure high
reliability. Additionally, NEC has introduced a pre-screening
method into the production line for eliminating potentially
defective units. This combination of building quality in and
screening projected early failures out has resulted in
superior quality and excellent reliability.
Technology Description
Most large-scale integrated circuits utilize high density
MOS technology. State-of-the-art high performance has
been achieved by improving fine-line generation techniques. By reducing physical parameters, circuit density
and performance increase while active circuit power dissipation decreases. The data presented here shows thatthis
advanced technology, combined with the practice of TOC,
yields products as reliable as those from previous technologies.
10002
First, the quality control function is embedded into each
process. This method enables early detection of possible
causes of failure and immediate feedback.
Second, the reliability and quality assurance policy reflects
the beliefs and practices of the entire organization. This
enables companywide quality control activities: at NEC,
everyone is involved with the concept and methodology of
total quality control.
Third, there is an ongoing research and development effort
to set even higher standards of device quality and reliability.
Fourth, extensive failure analysis is performed periodically
and appropriate corrective actions are taken as preventative measures. Process control is based on statistical data
gathered from this analysis.
The new standard is continuously upgraded, and the
iterative process continues. The goal is to maintain the
superior product quality and reliability that has become
synonymous with the NEC name.
Zero Defect Activities. One of the activities that involves
every level of the NEC staff in quality control is the Zero
Defects (ZD) Program. As the name implies, the purpose
of the ZD program is to minimize, if not eradicate, defects
due to controllable causes. Such activities must involve
each and every worker and can be most effective when
pursued by groups of workers. The groups of workers are
organized by consideration of the following:
• A group must have a target to pursue
• Several groups can be organized to pursue the common target
• Each group must have a responsible person
• Each group is well supported
The item of the group target is to be selected among items
relating to specifications, inspections, operation standards,
and so forth. When data made in the past is available, it is
used to make a Pareto diagram which is reviewed for
selection ofthe item most conducive to quality improvement.
Records are analyzed and compared with the target, in
order to compute the numerical equivalents of the defects.
Action is then taken to control these defects as required.
2-3
2
Reliability and Quality Control
NEe
Figure 1. Quality Control System Flowchart
Manufacturing Facility
(Inspection) (Manufacturing)
Dapt
11
E
Q.
o
I
c
o
8
"0
e
Q.
iii
'C
I"0
C
I'CI
C
Cl
Daslgn Ravlaw
'cii
Spac/Eng Support
c
o
Confarenca on Mass Productlon/Sales
~
"e
Q.
ZII'CI
Praparatlon of Spac for
ManufacturlngfTestlQA
::E
Complaint
(Field Data)
In·Procass Quality Monitoring;
In·Procass Inspection;
Environment and Equipment
Control/Calibration;
Lot Control; Corrective
Actions; Data Analyslsl
Feedback; Etc.
83vO-6934B
2-4
NEe
Reliability and Quality Control
Statistical Approach. Another approach to quality control
is the use of statistical analysis. NEC has been utilizing
statistical analysis at each stage of LSI production development, trial runs, and mass production in order to build
and maintain product quality. Some of the methods for
implementing this statistical approach are:
• Design of experiments
• Control charts
• Data analysis:
• Cp, Cpk study:
Figure 2. New Product Development Flow
• Circuit Design
• Mask Pattern Layout
Manufacturing - - - - . .
• Package Design
.--'~--~----~
Variance, correlation, regression,
multivariance, etc.
VClriables and attributes data
(Normally, study is done on a
monthly basis)
Process control sheets and other QC tools are used to
monitor various important parameters such as Cp, Cpk, X,
X, X-R, electrical parameters, pattern dimensions, bond
strength, test percentage defects, etc.
The results ofthese studies are watched by the production
staff, QC Engineers, and other responsible engineers. If
any out-of-control or out-of-specification limit is observed,
quick action is taken in accordance with corrective action
procedures.
Implementation of Quality Control
Building quality into a product requires early detection of
possible causes of failure at each process step, then
immediate feedback to remove these causes. A fixed
station quality inspection is often lacking in immediate
feedback; it is therefore necessary to distribute quality
control functions to each process step-including the
conceptual stage. Following is a breakdown of the significant steps at which NEC has implemented these functions:
• Product development
• Incoming material inspection
• Wafer processing
• Chip mounting and packaging
• Electrical testing and thermal aging
• Outgoing material inspection
• Reliability testing
• Process/product changes
New Product Development Phase. The product development phase includes conception of a product, review of
the device proposal, physical element design and organization, engineering evaluation, and finally, transfer of the
product to manufacturing. Quality and reliability are considered at every step. The new product development flow
is shown in Figure 2.
83vO-6935A
2-5
NEe
Reliability and Quality Control
Design. Design plays an extremely important role in
determining the product quality and reliability. NEC believes thatthe foundation of device quality is determined at
the design stage. The four steps involved in the design of
LSI devices are circuit design, mask pattern layout, process and product manufacturing, and package design.
Design standards and the standardization of design steps
have been established to maximize quality and reliability.
Design Review. After completion of the design, a design
review is performed. In this review, the design is compared
with design standards and other factors which influence
the reliability and quality. If necessary, modification or
redesign is then performed. NEC believes that the design
review is very essential for not only newly designed products but also for product modifications.
Trial Production/Evaluation/Mass Production. When
the design passes the design review successfully, a trial
run is carried out. The trial run is evaluated forthe products'
characteristics and quality/reliability.
Thorough evaluation is carried out by generating samples
in which process conditions-ones that cause characteristic factors to change in mass production-are varied
deliberately. In addition, reliability tests are conducted for
durability, stress resistance, etc., to insure sufficient quality and reliability.
modes. The results of these inspections are used to rate
the vendors for future purchasing.
In-process Quality Inspections. Typical in-process
quality inspections done at the wafer fabrication, chip
mounting and packaging, and device testing stage are
listed in Appendix 1.
Electrical Testing and Screening. A flowchart of the
typical infant mortality screening (when required) and
electrical testing is depicted in Figure 3.
At the first electrical test, DC parameters are tested according to the electrical specifications on 1 00% of each lot.
This is a prescreening prior to any infant mortality test. At
the second electrical test, AC functional tests as well as DC
parameter tests are performed on 100% of each lot. If the
percentage of defective units exceeds the limit, the lot is
subjected to rescreen. During this time, the defective units
undergo failure analysis, the results of which are fed back
into the process through corrective actions.
Figure 3. Electrical Testing and Screening
DC Parameters
(Full AC/DC Testing
.------~~==:;r'"----'
If No 100% Burn-In)
If no problems are found at this stage, the product is
approved, after which mass production is possible.
*Whenever Required
Prior to the transfer, the production Design Department
prepares a production schedule, including the reliability
and quality control steps relating to the production. Even
after the mass-production has started, the standards for
those production and control steps are always reexamined
for improvements.
DC Parameters,
AC Functional
Incoming Material Inspection. NEC has various programs to control incoming materials. Some are:
No
• Vendor/material qualification system
• Purchasing specifications for materials
• Incoming materials inspection
• Inspection data feedback
Electrical,
Appearance, and
'-------,r--"'-~ Dimensions
• Quality meetings with vendor
• Vendor audits
If any parts or materials are rejected at incoming inspection, they are returned to the vendor with a rejection
notification form which specifies the failure items and
2-6
83vO·6936A
~EC
Reliability and Quality Control
Outgol~g Inspection. Prior to warehouse storage, lots
are subjected to an outgoing inspection according to the
following sampling plan.
.
• Electrical test:
DC parameters LTPD
Functional test LTPD
3%
3%
• Appearance:
Major LTPD
Minor LTPD
3%
FIgure 4. ReliabIlity LIfe (Bathtub) Curve
7%
Reliability Assurance Tests. Samples are continually
taken prior to shipment and subjected to monitoring reliability tests. They are tak~nfrom similar process groups, so
it may be assumed that the samples' reliability is representative of the reliability of the group.
Reliability Testing
Wearout
Period
Random Failure Period
Tlme-...
83vO·6937A
Reliability is defined as the characteristics of an item
expressed by the probability that it will perform a required
function understated conditions fora stated period of time.
This involves the concepts of probability, the definition of
required function(s), and the critical time used in defining
the reliability.
Definition of a required function, by implication, treats the
definition of a failure. Failure is defined as the termination
of the ability of a device to perform its required function. A
device is said to have failed if it shows the inability to
perform within guaranteed parameters as given in an
electrical specification.
Discussion of reliability and failure can be approached in
two ways: with respect to systems or to individual devices.
Important considerations are the constant failure period,
the early failure (infant mortality) period, and overall reliability level.
With regard to individual devices, areas of prime interest
include specific failur~ mechanisms, failures in accelerated tests, and failures in screening tests.
The accu mu lation of normal device failure rates constitutes
the expected failure rate of the system hardware: the
probability that no device failures will occur in a system is
the product of each device's probability that it will not fail.
, The failure rate of system hardware is then the sum of the
failure rates of the components used to construct the
system.
Life Distribution
The fundamental prinCiples of reliability engineering predict that the failure rate of a group of devices will follow the
well-known bathtub curve in Figure 4. The curve is divided
into three regions: infant mortality, random failures, and
wearout failures.
Infant mortality, as the name implies, represents the earlylife failures of devices. These failures are usually associated with one or more manufacturing defects.
After some period of time, the failure rate reaches a low
value. This is the random failure portion of the curve,
representing the useful portion of the life of a device.
During this random failure period, there is a decline in the
failure rate due to the depletion of potential random failures
from the general population.
'
Thewearoutfailures occur atthe end ofthe device's useful
life. They are characterized by a rapidly rising failure rate
over time as devices wear out both physically and electrically.
Thus, for a device that has a very long life expectancy
compared to the system which contains it, the areas of
concern will be the infant mortality and the random failure
portions of the ,bathtub curve.
Failure Distribution at NEe
In an effort to eliminate infant mortality failures, NEC
subjects its products to production burn-in whenever necessary. This burn-in is performed at an elevated temperature for 100 percent of the lots involved and is designed to
remove the potentially defective units.
To study the random failure population, integrated circuits
returned to NEC from the field undergo extensive failure
analysis at respective NEC Manufacturing Divisions. Failure mechanisms are identified and data fed back to cognizant Production and Engineering groups.
This data coupled with in~line dataisthen usedto introduce
corrective actions and quality improvement measures.
2-7
NEe
Reliability and Quality Control
After elimination of early device.failure·s, a system will be
left to the random failure rate of its components. Thus, in
order to make proper projections of the failure rate of the
system in the operating environment, failure rates must be
predicted for the system's components.
Infant Mortality Failure Screening
Establishing infant mortality screening requires knowledge of the likely failure mechanisms and their associated
activation energies. The most likely problems associated
with infant mortality failures are generally manufacturing
defects and process anomalies. These defeqs and anomalies generally consist of contamination, cracked chips,
wire bond shorts, or bad wire bonds. Since these describe
a number of possible mechanisms, anyone of which might
predominate at a given time, the activation energy for
infant mortality varies considerably.
Correspondingly, the effectiveness of a screening condition-preferably at some stress level in order to shorten
the screening time-varies greatly with the failure mechanism. For example, failures due to ionic contamination
have an activation energy of approximately 1.0 eV. Therefore, a 15-hou r stress at 125°G ju nctio n te mpe rature would
be the equivalent of approximately 314 days of operation
at a junction temperature of 55°G. On the other hand,
failures due to oxide defects hav~ an activation energy of
approximately 0.3 eV, and a 15-hour stress at 125°G
junction temperature would be the equivalent of approximately four day's operation at 55°Gjunction temperature.
As indicated by this situation, the conditions and duration
of infant mortality screening must be strongly dependent
on the allowable component, hence system, failures in the
field,as well as the ebonomic factors involved.
Empirical data gathered at NEG indicates that early failures (if any) occur after less than 4hours of stress at 125°G
ambient temperature. This fact is supported by the bathtub
curve created from the life test results ofthe same lots,
where the failure rate shows a random distribution as opposed to a decreasing failure rpte that runs into the random
failure region.
Long-Term Failure Rate
;
,
NEG's long-term failure rate goal, pased on the mask and
process design, is confirmed by life testing using the
following conditions:
• A minimum of 1.2 million device hours (= sample size x
test period) at 125°G should be accumulated to obtain
the accuracy necessary for predicting a failure rate of
0.02% per 1000 hours at 55°G with a 60% ponfidence
level.
• A minimumof3 million device hours at 125°G should be
accumulated to obtain the accuracy necessary for
predicting a failure rate of 0.01% per 1000 hours at 55°G
with a 60% confidence level.
Accelerated Reliability Testing
NEG performs extensive reliability testing both at, preproduction and post-production levels to insure that its
products meet the minimum expectations set by NEG.
Accelerated reliability testing results are then used to
quantitatively monitor the reliability.
As an example, assume that an electronic system contai ns
1000 integrated circuits and can tolerate 1 percent system
failures per month. The failure rate per component is:
1% Failures
= .0014 % Failures
720 Hours x 1000 Pcs.
1000 Hrs
or 14 FITs
To demonstrate this failure rate, note that 14 FITs correspond to one failure in about 85 devices during an operating test of 10,000 hours. It is quickly apparent that a test
condition is required to accelerate the time-to-failure in a
predictable and understandable way. The i~plicit requirement for the accelerated stress test is that the relationship
between the accelerated stress testing condition and the
condition of actual use be known.
Whenever necessary, NEG has adopted this initial infant
mortality burn-in at 125°G as a standard production screening proce.dure. As a result, th.e field reliability of NEG
devices is an order of magnitude higher than the goal set
for NEG's integrated circuit products.
A most common time-to-failure relationship involves the
effect of temperature, which accelerates many physiochemical reactions which may lead to device failure. Other
environmental conditions are voltage, current, humidity,
vibration, or some combination of these. Appendix 2 lists
typical reliability assurance tests performed at NEG for
molded integrated circuits. Figure 5 shows the results of
some of these tests for various process,types.
NEG believes it is imperative thaUailure modes associated
with infant mortality screens be understood and fixed atthe
manufacturing level. If such failures can be minimized or
eliminated, and countermeasures appropriately monitored,
then such screens can be eliminated.
High-Temperature Operating Life Test. This test is used
to accelerate failure mechanisms by operatir:tg devices at
an elevated temperature of ·125°G. The data ()btained is
translated to a lower temperature by using the Arrhenius
relationship.
2-8
ttiEC
Reliability and. Quality Control
Figure 5. Typical Reliability Test Results
Micro:
HTB
T/H
PCT
NMOS
7/19113
(15 FIT)
15/9315
0/11752
CMOS
3/11892 .
(5.4 FIT)
217293
8/9476
DRAM2
10/10052
(19 FIT)
0/9958
0/5880
SRAM3
1/10421
218142
0/8768
38/14300
. (115 FIT)
0/3634
1/3060
213506
(33 FIT)
1/1111
TIC
1
Memory:
[HTOl)
1 MEG DRAM4
1/2995
1/1780
In some cases, an average activation energy is assumed
in order to accomplish, a quick first order approximation.
NEC assumes an average activation energy of 0.7 eV for
such approximations. This average value has been assessed from extensive reliability test results and yields a
conservative failure rate.
Since most semiconductor failures are temperature dependent, the Arrhenius relationship is used to normalize
failure rate predictions at a system operation temperature
of 55°C. It assumes that temperature dependence is an
exponential function that defines the probability of occur-a
rence, and that the degradation of a performance parameter is linear with time. The Arrhenius model includes the
effects of temperature and activation energies of the
failure mechanisms in the following Arrhenius equation:
A
=
exp -EA (TJl - TJ2 )
Asic: 5
CMOS
ECl
0/1080
(8.4 FIT)
BiCMOS
1/895
(18 FIT)
1/4764·
0/141
0/1073
0/935
k(TJ1 ) (TJ2 )
4/2680
0/1781
Information has been extracted from NEC Report Numbers:
TRQ-89-05-0030
2TRQ-89-01-0021
3TRQ-88-09-0008
4TRQ-89-01-0020
5 TRQ-89-04-0025
1
Where:
A = Acceleration factor
EA = Activation energy
TJl = Junction temperature (in K)
at TAl = 55°C
TJ2 = Junction temperature (in K)
at TA2 = 125°C
k = Boltzmann's constant
= 8.62 x 10-5 eV/K.
High-Temperature and High-Humidity Test. Semiconductor integrated circuits are highly sensitive to the effect
of humidity causing electrolytic corrosion between biased
lines. The high-temperature and high-humidity testis performed to detect failure mechanisms that are accelerated
by these conditions, such as leakage-related problems
and drifts in device parameters due to process instability.
Because the thermal resistance and power dissipation of
a particular device type cannot be ignored, junction
temperatures (TJl and TJ2) are used instead of ambient
temperatures (TAl and T A2). We calculate junction
temperatures using the following formula:
High-Temperature Storage Test. Another common test
is the high-temperature storage test, in which devices are
subjected to elevated temperatures with no applied bias.
This test is used to detect proces.s instability and stress
migration problems.
'
In orderto estimate long ferm failure rate, the acceleration
factor must be used to determine the simulated test time.
From the high temperature operating life test results,
. failure rates can then be predicted at a 60% confidence
level using the following equation:
Environmental Tests. Other environmental tests are performed to detect problems related to the package, material, susceptibility to extremes in environment, and problems related to usage of the devices.
Failure Rate Calculation/prediction
When predicting the failure rate at a certain temperature
from accelerated life test data, the activation energies of
the failure mechanisms involved should be considered.
This is done whenever the exact cause of failures is known
through failure analyses results.
TJ = TA + (T~ermal Resistance) (Power Diss. at TA )
L =
X2 105
2T
Where:
L
*X2
= Failure rate in %/1000 hours
= The tabular value of chi-squared distribution at a
given confidence level and calculated degrees of
freedom (2f + 2, where f = number of failures)
T
=
# of equivalent device hours
(# of devices) x (# of test hours)
x (acceleration factor)
2-9
NEe
Reliability and Quality Control
*Since the failures of concern here are the random, not the
infant mortality failures (that is, the end of the downward
slope and the middle-constant-section ofthe bathtub curve
in Figure 4), X2 is determined assuming a one-sided, fixed
time test.
Another method of expressing failures is in FITs (failures
in time). One FIT is equal to one failure in 109 hours. Since
L is already expressed as %/1000 hours (10-5 failure/hr) ,
an easy conversion from %/1000 hours to FIT would be to
multiply the value of L by 104 •
EXAMPLE: A sample of 960 pieces was subjected to
1000 hours 125°C burn-in. One reject was observed.
Given that the acceleration factor was calculated to be
34.6 using the Arrhenius equation, what is the failure rate
normalized to 55°C using a confidence level of 60%?
Express the failure rate in FIT:
Solution:
For n =2f + 2 = 2(1) + 2 = 4, X2 = 4.046.
2
Then L
5
X 10
= 2T
(%/1000 hour)
5
= 0.0061
Therefore, FIT = 0.0061 • (104 )
As mentioned previously, a design review is performed for
product modifications or changes. Once the design is
approved, and processes altered (if necessary) for maximum quality, the device goes through qualification testing
to check the reliability. If the test results are acceptable,
the product is released for mass production.
Testing is also performed when only a process modification or change is made.
The typical qualification/process change tests are listed in
Appendix 3.
Failure Analysis
At NEC, failure analysis is performed not only on field failures, but also routinely on products which exhibit defects
during the production process. This data is closely checked
for correlation with the production process quality information, inspection results, and reliability test data. Information derived from these failure analyses is used to improve
product quality.
As there are a lot of failure mechanisms of LSI devices,
highly advanced analytical technologies are required to
investigate such failures in detail. The standard failure
analysis flowchart relating to the returned products from
customers is shown in Appendix 4.
X2 105
(%/1000 hr)
2 (# of dev.) (# of test hrs.) (acel. factor)
(4.046)
10
2(960) (1000) (34.6)
Product/Process Changes
(%/1000 hr)
= 61
NEe's Goals on Failure Rates
The reject rate at customer's incoming inspection, the
infant mortality rate, and the long term reliability, are all
monitored and checked against NEC's quality and reliability
targets (listed in Figure 6).
Figure 6. NEe Quality and Reliability Targets
Reject Rate at Customer's
Incoming Electrical Inspection (PPM)
Memory
EClRAM
MOS
1988
150
50
1990
100
50
2-10
Infant Mortality (RT)
...
Gate Arrays
J1COM
Year
Long Term Reliability (AT)
Memory
Gate Arrays .
J1COM
BICMOS
ECl
CMOS
EClRAM
MOS
100
1000
300
300
100
50
100
500
200
150
80
50
Memory
J1COM
Gale Arrays
BiCMOS
EClRAM MOS
Eel CMOS
BiCMOS
ECl
CMOS
100
1000
300
150
100
100
150
1000
300
400
80
500
250
100
80
100
150
500
250
300
NEe
Summary and Conclusion
As has been discussed, building quality and reliability into
products is the most efficient way to ensure product
success. NEC's approach of distributing quality control
functions to process steps, then forming a total quality
control system, has produced superior quality and excellent reliability.
Prescreening, whenever necessary, has been a major
factor in improving reliability. In addition, monthly reliability assurance tests have ensured high outgoing quality
levels.
Reliability and Quality Control
The combination of building quality into products, effective
prescreening of potential failures, and monitoring of reliability through extensive testing, has established a singularly high standard of quality and reliability for NEC's largescale integrated circuits.
Through a companywide quality control program, continuous research and development activities, extensive failure
analysis, and process improvements, this higher standard
of quality and reliability will continuously be set and maintained.
2-11
NEe
Reliability and Quality Control
Appendix 1
Typical QC Flow for CMOS Fabrication
WAFER FABRICATION PROCESS QC FLOW (CMOS)
FLOW
PROCESS MATERIAL
IN-PROCESS INSPECTION/QUALITY MONITOR
Silicon Wafer
Incoming
Inspection
Resistivity (sampling by lot)
Dimension (sampling by lot)
Visual (sampling by lot)
Wall
Formation
Oxidation
Photo LIthography
Oxide Thickness (sampling by lot)
Alignment and Etching Accuracy (sampling by lot)
Layer Resistance (sampling by day)
Ion Implantation
Field
Formation
Deposition
Photo Lithography
Deposit Thickness (sampling by lot)
Alignment and Etching Accuracy (sampling by lot)
Oxide Thickness (sampling by lot)
Oxidation
Channel Stopper
Formation
Photo Lithography
Ion Implantation
Oxidation
Alignment and Etching Accuracy (sampling by lot)
Layer Resistance (sampling by lot
Oxide Thickness (sampling by lot)
Gate
Formation
Deposition
Doping
Photo LIthography
Deposit Thickness (sampling by lot)
Layer Resistance (sampling by lot)
Alignment and Etching Accuracy (sampling by lot)
Gate Electrode Width (sampling by lot)
pIn SD Formation
Photo Lithography
Alignment and Etching Accuracy (sampling by lot)
Layer Resistance (sampling by lot)
Ion Implantation
Anneal
Contact
Hole
Deposition
Photo Lithography
Deposit Thickness (sampling by lot)
Alignment and Etching Accuracy (sampling by lot)
Metallization
Metal Deposition
Photo Lithography
Metal Thickness (sampling by run)
Alignment and Etching Accuracy (sampling by lot)
Parametric Test (sampling by lot)
Alloy
Passivation
Deposition
Photo Lithography
Deposit Thickness (sampling by lot)
Alignment and Etching Accuracy (sampling by lot)
Wafer Sort
Contact Hoie and Metallization Steps are Repeated Twice
83vQ-69398
2-12
NEe
Reliability and Quality Control
Appendix 1
Typical QC Flow for PLCC Assemblyffest
The Check of Manufacturing Conditions
Process/Materials
1
Sorted Wafers
2
Wafer Visual
3
Dicing
4
Break and Expand
5
Die Visual Inspection
Check
Items
Table Speed
DIWater
Blade Height
Wafer Break
Conditions
The Check of Manufacturing Qualities
Checked
By
Frequency
Instrument
Every
Shift
Indicators
Gauges
P.C.
Every
Shift
Indicators
Gauges
P.C.
Check
Item
Checked
By
Frequency
Instrument
Wafer Visual
100%
(Naked Eye)
Operator
Sawing
Dimensions
Before
Running
Operator
Wafer Visual
100%
Microscope
with Filter
Eyepiece
(Naked Eye)
Die
Visual
Every Lot
Sampling
(Or 100%)
Microscope
Operator
Die Visual
Epoxy
Coverage
Every
Magazine
(Naked Eye)
Operator
Every Shift
Microscope
Operator
Wafer Expand
Conditions
Lead Frames
DieAltached
Conditions
7
Die Attached
Temperature
Epoxy Cure
(Not Done for Gold
Die Attached product)
Heat
Temperature
N 2 Flow
Every
Shift
Indicators
Gauges
P.C.
Shear
Strength
Every
Shift
Dynamometer
Operator
8
Bonding
Conditions
Every
Shift
Indicators
P.C.
Visual
Every
Magazine
Microscope
Operator
Temperature
Every
Week
Thermocouple
and
Potentiometer
P.C.
Wire Pull
Test
Every
Shift
Tension
Gauge
Operator
Die
Visual
Every Lot
Sampling
(or 100%)
Microscope
Inspector
Visual
100%
(Naked Eye)
Operator
Visual
Every Lot
(Naked Eye)
Operator
6
~
Fine Wire
10
Wire Bonding
11
Pre-Seal Visual
Inspection
~
13
Molding Compound
Molding
Temperature
of Pellet,
Expiration Date
Temperature
Profile of
Die Set
Every
Shift
Every
Shift
Indicators
Thermocouple,
Potentiometer
P.C.
Thermocouple
P.C.
Every Shift Thermocou pie,
Potentiometer
P.C.
Preheat
Temperatue
Pressure
Cure Time
14
Mold Aging
Temperature
Every Shift
Indicator
P.C.
15
Deflashing
Deflashing
Conditions
Every Shift
Indicators
P.C.
Titration
Tech.
Concentration Every Week
Density
Water Jet
Pressure
0
Plating
Plating
Conditions
Every Week Density Meter
Tech.
Every Day
Gauge
Tech.
Every Day
Indicators
P.C.
Titration
Tech.
Concentration Every Week
83VQ-6914OB
2-13
II
NEe
Reliability and Quality Control
Appendix 1
Typical QC Flow for PLCC Assemblynest (Cont.)
The Check of Manufacturing Qualities
The Check of Manufacturing Conditions
Process/Materials
G
~
Check
Items
Marking Ink
Marking
20
Mark Cure
21
Lead Forming
22
Final Assembly Inspection
23
1st Electrical Sorting
Checked
By
24
Burn-In (Whenever Necessary)
25
1st Electrical Sorting
26
Reliability Assu.rance Test
In-Warehouse Inspection
Check
Item
Frequency
Instrument
Checked
By
Visual
Every Lot
(Naked Eye)
Technician
Plating
Thickness
Every Lot
X-ray
Technician
Composition
Every Lot
X-ray
Technician
Solderability
Once/Day
(Naked Eye)
Technician
Marking
Conditions
Every Shift
Indicators
P.C.
Visual
Every Lot
(Naked Eye)
Operator
Temperature
Every
Shift
Thermocouple
P.C.
Marking
Permanency
Twice/Shift
Automatic
Tester
Operator
Dimensions
Every Shift
(Before
Running)
Test Jig.
Caliper
Operator
Visual
Every lot
(Naked Eye)
'Operator
Visual
Every Lot
Magnifying
Lamp
Operator
P.M. Check
28
Instrument
Plating Inspection
19
27
Frequency
Every Day
P.M. Jig.
Operator
Sample
Check
Before
Testing
Test
Samples
Operator
Burn-In
Conditions
Every
Batch
Indicator
P.C.
Every Day
P.M. Jig.
Operator
Before
Testing
Test
Samples
Operator
Electrical
Characteristics
100%
ICTester
Operator
Electrical
Characteristics
100%
ICTester
Operator
Electrical
Characteristics
Every Lot
ICTester
Inspector
Visual (Major)
Every Lot
(Naked Eye)
and
Microscope
Inspector
Visual (Minor)
Every Lot
(Naked Eye)
Inspector
Every
Month
Every Day
P.M. Jig.
Before
Testing
Test
Samples
Warehousing
83vQ-69416
2-14
NEe
Reliability' and Quality Control
Appendix 2
Typical Reliability Assurance Tests
The life tests performed by NEC consistof high temperature
bias life (HTB), high temperature storage life (HTSL), high
temperature/high humidity (T/H) , and high humidity storage
life (HHSL) tests. Additionally, various environmental and
mechanical tests are performed. The table below shows
the conditions of the various life tests, envi ro nmental tests,
and mechanical tests.
Symbol
MIL·STD·883C
Method
High Temperature
Bias Life
HTB
1005
TA = 125"C, Voo specified per device type.
(Note 1)
High Temperature
Storage Life
HTSL
1008
TA = 150"C.
(Note 1)
High Temperaturel
High Humidity
TIH
TA =85"C, RH =85%, Voo =5.5 V.
(Note 1)
TA =85"C, RH =85%.
(Note 1)
TA = 125"C, P =2.3 atm.
(Note 1)
Test Item
High Humidity
Storage Life
HHSL
Condition
Remarks
Pressure Cooker
peT
Temperature Cycling
TIC
1010
- 65"C to 150"C, 1 hr/cycle.
(Note 1)
Lead Fatigue
C3
2004
90 0 bends. 3 bends wnhout breaking.
(Note 2)
Solderability
C4
2003
230"C, 5 sec, Rosin Base Flux.
(Note 3)
Soldering Heat!
Temperature Cyclel
Thermal Shock
C6
(Note 4)
1010
1011
260"C, 10 sec, Rosin Base Fluxl
10-1 hr cycles, -S5"C to 150"C1
15-10 min cycles, O"C to 100"C
(Note 1)
Notes:
(1) ElectriCal test per data sheet is performed. Devices that exceed the data
sheet limits are considered to be rejects.
(3) Less than 95% coverage is considered to be a reject.
(4) MIL-STD-750A, method 2031.
(2) Broken lead is considered to be a reject.
2-15
II
NEe
Reliability and Quality Control'
Appendix 3
New Product / Process Change Tests
Newly
Developed
Product
Shrink
Ole
New
Package
Wafer
Assembly
Test Item
Test Conditions
Sample Size
High Temp.
Operating Life
See Appendix 2, 1000H
20 to SO pes
X 1 t0310ts
0
0
0
0
0
High Temp.
Storage Life
T = 150"C (Plastic),
17S"C (Ceramic), 1000H
10t020 pes
X1t0310ts
0
0
0
0
0
High Temp. and
Humidity Bias Life
(Plastic Device)
See Appendix 2, 1000H
20 to SO pes
X 1 to 3 lots
0
0
0
0
0
Pressure cooker
(Plastic Device)
See Appendix 2, 288H
10to 20 pes
X 1 t0310ts
0
0
0
0
0
Thermal
Environmental
See Appendix 2
10t020 pes
X 1 to 3 lots
0
X
0
X
0
Mechanical
Environmental
(Ceramic Device)
20G, 10 to 2000 Hz
1S00G, O.S ms
20000G, 1 min
10 to 20 pes
X 1 to 3 lots
0
X
0
X
0
Lead Fatigue
See Appendix 2 .
Spes
X1t0310ts
X
X
X
Solderabil~y
See Appendix 2
Spes
X 1 to 3 lots
X
X
X
ESD
(1) C =200 pF, R =on
(2) C =100 pF, R =1.S Kn
20 pes
X1t0310ts
0
0
X
0
X
Long Term TIC
See Appendix 2, 1000 cy
10 to SO pes
X1t0310ts
0
0
0
0
0
O-Performed
2-16
X - Perform if Necessary
- - Not Performed
NEe
Reliability and Quality Control
Appendix 4
Failure Analysis Flowchart
'------INFORMATION
Failure mode:
Situation, When Failure
Appeared: etc.
II
DC/Function Testing
by Tester Curvet racer
Ves
Test correlation
May be Needed
Due to the Case: X-ray Fluoroscope,
Hermetical Test, Dew-point Test,
Curvet racer Check, etc.
Decapsulation, Internal Visual
Check, Electrical Measurement,
Circuit Analysis
Etching the PaSSivation, etc.
SEM, XMA, Cross-section, etc.
Estimation of Causes
Countermeasures
Corrective Action
83vO·6938A
2-17
Reliability and Quality Contr-ol
2-18
NEe
NEe
16·BitCPUs
3-1
NEe
16·Bit CPUs
Section 3
16-Bit CPUs
I'PD70108 (V20), 70108H (V20H)
3a
16-Bit Microprocessor:
High-Performance, CMOS
I'PD70116 (V30), 70116H (V30H)
3b
16-Bit Microprocessor:
High-Performance, CMOS
I'PD70208 (V40)
3c
8/16-Bit Microprocessor:
High-Integration, CMOS
I'PD70216 (V50)
3d
16-Bit Microprocessor:
High-Integration, CMOS
I'PD70136 (V33)
3e
16-Bit Microprocessor:
High-Speed, CMOS
I'PD70236 (V53)
16-Bit Microprocessor:
High-Speed, High-Integration, CMOS
3-2
3f
NEC
NEe Electronics Inc.
pPD70i08 (V20), 70~08H (V20H)
i6·Bit Microprocessor:
High·Performance, CMOS
Description
Ordering Information
ThepPD70108 (V20®) is a CMOS 16-bit microprocessor
with internal 16-bit arch itectu re and an 8-bit external
data bus. The pPD701 08 instruction set is a superset of
thepPD8086/8088; however, mnemonics and execution
times are different. The pPD70108 additionally has a
powerful instruction set including bit processing,
packed BCD operations, and high-speed multiplication/
division operations. The pPD70108 can also execute
the entire 8080 instruction set and comes with a
standby mode that significantly reduces power consumption. It is software-compatible with thepPD70116
16-bit microprocessor.
Part
Number
The H-series microprocessors are fully static devices
that offer operating frequencies to 16 MHz, lower
power consumption, and no restriction on minimum
clock frequency from dc to 16 MHz.
Max Frequency
of Operation
Package Type
8 MHz
40-pin plastic DIP
Standard Series
JlPD70108C8
C10
10 MHz
L8
8 MHz
L10
10 MHz
GC8
8 MHz
GC10
10 MHz
JlPD701 08HC1 0
10 MHz
H-Series
HC12
12 MHz
16 MHz
Features
HL 10
10 MHz
o
HL 12
12 MHz
D
o
o
D
o
D
D
o
o
o
o
o
o
D
o
o
o
D
D
o
V20 is a registered trademark of NEC Corporation.
52-pin plastic QFP
(P52GC-100-386)
- - - - -
HC16
Minimum instruction execution time: 250 ns
at 8 MHz, 200 ns at 10 MHz, 125 ns at 16 MHz
Maximum addressable memory: 1 Mbyte
Abundant memory addressing modes
14 x 16-bit register set
101 instructions
Instruction set is a superset of pPD8086/8088
instruction set
Bit, byte, word, and block operations
Bit field operation instructions
Packed BCD instructions
Multiplication/division instruction execution time:
2.4 to 7.1 ps at 8 MHz, 1.9 to 5.7 ps at 10 MHz
High-speed block transfer instructions:
1 Mbyte/s at 8 MHz, 1.25 Mbyte/s at 10 MHz
High-speed calculation of effective addresses:
2 clock cycles in any addressing mode
Maskable (INT) and nonmaskable (NMI)
interrupt inputs
IEEE-796 bus compatible interface
8080 emulation mode
CMOS technology
Low power consumption
Low-power standby mode
Minimum-power Stop mode (H-SeJies)
Single power supply; 5-V and 3-V specifications
Maximum operating frequencies: 8 to .16 MHz
44-pin PLCC
HL16
16 MHz
HGC10
10 MHz
HGC12
12 MHz
HGC16
16 MHz
40-pin plastic DIP
44-pin PLCC
52-pin plastic QFP
(P52GC-100-386)
Pin Configurations
40-Pin Plastic DIP
Voo
IC
A14
A15
A13
38
A16/PSO
A12
37
A17/PS1
A11
5
36
A1S/PS2
A10
6
35
A19/PS3
A9
34
lBSO [HIGH]
As
33
S/LG
AD7
AD6
10
JlPD
70108
32
RD
31
HlDRQ [Aa/AKO]
AD5
11
30
HlDAK [Aa/AK1]
AD4
12
29
WR [BUSlOCK]
AD3
13
28
IO/M [BS2]
AD2
14
27
BUFR/W [BS1]
AD1
15
26
BUFEN [BSo]
ADo
16
25
ASTB[QSo]
NMI
17
24
INTAK [QS1]
INT
18
23
POll
ClK
19
22
READY
GND
20
21
RESET
83-004104B
ED
.
NEe
pPD701 08 (V20)
Pin Configurations (cont)
Pi n Identification
Symbol
44-Pln Plastic Leaded Chip Carrier (PLCC)
Direction
IC·
Internally connected
Out
A14 - As
AD? - ADo
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
Function
In/Out
Address bus, middle bits
Address/data bus
NMI
In
Nonmaskable interrupt
input
INT
In
Maskable interrupt input
ClK
In
Clock input
Ground potential
GND
A18/PS2
40
28
A17IPS1
41
27
INTAK [OS1]
RESET
In
Reset input
A16/PSO
42
26
POll
READY
In
Ready input
A15
43
25
READY
RESET
POll
In
Poll input
GND
INTAK (QS1)
Out
Interrupt acknowledge
output (queue status bit 1
output)
ASTB (QSo)
Out
Address strobe output
(queue status bit 0 output)
BUFEN (BSo)
Out
Buffer enable output (bus
status bit 0 output)
BUFR/W (BS1)
Out
Buffer read/write output
(bus status bit 1 output)
10/M (BS2)
Out
Access is I/O 'or memory
(bus status bit 2 output)
WR (BUS lOCK)
Out
Write strobe output (bus
lock output)
HlDAK (RQ/ AK1)
Out
(In/Out)
Holdacknowledgeoutput,
(bus hold request
input! acknowledge
output 1)
HlDRQ (RQ/ AKa)
In")
(In/Out)
Hold request input (bus hold
request input! acknowledge
output 0)
Voo
44
GND
1
IC
2
0
tiP 0
70108
GND
21
A14
ClK
A13
INT
A12
NMI
A11
NC
83-0041028
52-Pin Plastic QFP
o
RD
INTAK [OS1]
S/lG
In
A16/PSo
37
POll
Small-scale/ large-scale
system input
A15
36
READY
Voo
Voo
35
RESET
lBSO (HIGH)
Out
34
GND
latched bus status output 0
(always high in large-scale
systems)
tlPD
Out
Read strobe output
ASTB [OSo]
38
A18/PS2
A17/PS1
33
GND
GND
32
NC
31
GND
A19 /PS 3 A16/ PS O
Out
IC
Address bus, high bits or
processor status output
A15
Out
Address bus, bit 15
GND
70108
A14
10
30
ClK
A13
11
29
INT
A12
12
28
NMI
A11
13
27
NC
Power supply
VDD
Notes: *
Ie should be connected to ground.
Where pins have different functions in small- and largescale systems, the large-scale system pin symbol and
function are in parentheses.
83-0041038
2
Unused input pins should be tied to ground or VDD to
minimize power dissipation and prevent the flow of potentially harmful currents.
NEe
J.lPD701 08 (V20)
Block Diagram
Inlernal Address/Data Bus
A16/PSo ~ A19/PS3
As-A15
Bus
Buffer
lBSO
BUFEN [BSo], BUFFI/W[BS1]
101M [BS2]
ASTB rOSol, INTAK [OS1]
RD, WR [BUS LOCK]
PS
Status
Control
SS
DSo
S/LG
READY
RESET
POLL
HLDRO (FlQ/AKo]
00
HLDAK [RQ/AK1]
NMI
INT
LC
L
r-
_ _S_ta_"_d_by_----I'Control
ClK
PC
Bus
Control
Unit
[BCUj
AW
Execution
Unit
[EXUj
BW
Effective Address
Generator
CW
OW
IX
IY
BP
SP
Microinstruction
Storage
29
Micro Data Bus
TC
§:
en
:I
III
co
co
o
.,
.,
:I
:I
Microsequence
Control
o
Instruction Decoder
PSW
Sub Data Bus [16]
Main Data Bus [16]
83-000072C
3
NEe
Pin Functions
Some pins of the pPD701 08 have different functions
according to whether the microprocessor is used in a
small- or large-scale system. Other pins function the
same way in either tYPE3 of system.
A15 - As [Address Bus]
For small- and large-scale systems.
The CPU uses these pins to output the middle 8 bits of
the 20-bitaddress data. They are three-state outputs
and become high impedance during hold acknowledge.
AD7 - ADo [Address/Data B.us]
For small- and large-scale systems.
. The CPU uses these pins as the time-multiplexed
address and data bus. When high, an AD bit is a one;
when low, an AD bit is a zero. This bus contains the
lower 8 bits of the 20-bit address during T1 of the bus
cycle and is used as an 8-bit data bus during T2, T3,
and T 4 of the bus cycle.
Sixteen-bit data I/O is performed in two steps. The low
byte is sent first, followed by the high byte. The ~d
dress/data bus is a three-state bus and can be at a high
or low level during standby mode. The bus will be high
impedance during hold and interrupt acknowledge.
NMI [Nonmaskable Interrupt]
For small- and large-scale systems.
This pin is used to input nonmaskable interrupt
requests. NMI cannot be masked by software. This
input is positive edge triggered and must be held high
for five clocks to guarantee recognition. Actual interrupt processing begins, however, after completion of
the instruction in progress.
The contents of interrupt vector 2 determine the
starting address for the interrupt-servicing routine.
Note that a hold request will be accepted even during
NMI acknowledge.
This interrupt will cause the pPD70108 to exit the
standby mode.
INT [Maskable Interrupt]
For small- and large-scale systems.
This pin is an interrupt request tha,.t can be masked by
software.
INT is active high level and is sensed during the last
clock of the instruction. The interrupt will be accepted
if the interrupt enable flag I E is set. The CPU outputs
the INTAK signal to inform external devices that the
interrupt request has been granted. INT must be
asserted until the interrupt acknowledge is returned.
If NMI and INT interrupts occur at the same time, NMI
has higher priority than INT and INT cannot be
4
accepted. A hold request will be accepted during INT
acknowledge.
This interrupt causes the pPD701 08 to exit the standby
mode.
ClK [Clock]
For small- and large-scale systems.
This pin is used for external clock input.
RESET [Reset]
For small- and large-scale systems.
This pin is used for the CPU reset signal. It is an active
high level. I nput of this signal has priority over all other
operations. After the reset signal input returns to a low
level, the CPU begins execution of the program starting
at address FFFFOH.
In addition to causing normal CPU start, RESET input
will cause the pPD701 08 to exit the standby mode.
READY [Ready]
For small- and large-scale systems.
When the memory or I/O device being accessed
cannot complete data read or write within the CPU
basic access time, it can generate a CPU wait state
(Tw) by setting this signal to inactive (low level) and
requesting a read/write cycle delay.
If the READY signal is active (high level) during either
the T3 or Tw state, the CPU will not generate a wait
state. READY is not synchronized internally. To
guarantee correct operation external logic must ensure
that setup and hold times relative to ClK are met.
POLL [Poll]
For small- and large-scale systems.
The CPU checks this input upon execution of the POll
'instruction.lfthe input is low, then execution continues.
If the input is high, the CPU will check the POll input
every five clock cycles until the input becomes low
again.
The POll and READY functions are used to synchronize CPU program execution with the operation of
external. devices.
RD [Read Strobe]
For small- and large-scale systems.
The CPU outputs this strobe signal d~ing data read
from an I/O device or memory. The 10/M signal is used
to select between I/O and memory.
The three-state output is held high during standby
mode and enters the high-impedance state during hold
acknowledge.
NEe
pPD70108(V20)
S/LG [Small/Large]
For small- and large-scale systems.
10/M's output is three state and becomes high
impedance during hold acknowledge.
This signal determines the operation mode of the CPU.
This signal is fixed at either a liigh or 10V,llIevei. When
this signal is a high level, the CPU will operate in smallscale system mode, and when low, in the large-scale
system mode. A small-scale system will have at most
one bus master such as a DMA controller device on the
bus. A large-scale system can have more than one bus
master accessing the bus as well as the CPU.
WR [Write Strobe]
INTAK [Interrupt Acknowledge]
For small-scale systems.
The CPU generates the INTAK signal low when it
accepts an INT signal.
The interrupting device synchronizes with this signal and
outputs the interrupt vector to the CPU via the data bus
(AD? - ADo). INTAK is a held at a high level in the
standby mode.
ASTB [Address Strobe]
For small-scale systems.
The CPU outputs this strobe signal to latch address
information at an external latch.
ASTB is held at a low level during standby mode and
hold acknowledge:
--BUFEN. [Buffer Enable]
. For small-scale systems.
This is used as the output enable signal for an external
bidirectional buffer. The CPU generates this signal during
data transfer operations with external memory or
I/O devices or during input of an interrupt vector.
This three-state output is held high during standby
mode and enters the high-impedance state during hold
acknowledge.
For small-scale systems.
The CPU generates this strobe'signal during data write
to an I/O device or memory. Selection of either I/O or
memory is performed by the 10/M signal.
.
This three-state output is held high during standby
mode and enters the high-impedance state during hold
acknowledge.
HLDAK [Hold Acknowledge]
For small-scale systems.
The HLDAK signal is ,used to indicate that the CPU
accepts the hold request signal (HLDRQ). When this
signal is a high level, the address bus, address/data
bus, and the control lines become high impedance.
HLDRQ [Hold Request]
For small-scale systems.
This input signal is used by external devices to request
the CPU to release the address bus, address/data bus,
and the control bus.
LBSO [Latched Bus Status 0]
For small-scale systems.
The CPU uses this signal along with the 10/M and
BUFR/W signals to inform an external device what the
cu rrent bus cycle is.
101M
BUFR/W
LBSO
0
0
0
0
0
1
Memory read
0
Memory write
0
Program fetch
1
1
Passive state
BUFR/W [Buffer Read/Write]
0
0
Interrupt acknowledge
For small-scale systems.
0
The output of this signal determines the direction of
data transfer with an external bidirectional bl,lffer. A
high output causes transmission from the GPU to the
external device; a low signal causes data transfer from
the external device to the CPU.
'
0
Bus Cycle
I/O read
0
I/O write
Halt
BUFR/W is a three-state output and becomes high
impedance during hold acknowledge.
IO/M [IO/Memory]
For small-scale systems.
The CPU generates this signal to specify either I/O
access or memory access. A high-level output specifies
I/O and a low-level signal specifies memory.
5
NEe
pPD70108 (V20)
A19/PS3- A16/PSO [Address Bus/Processor Status]
For small- and large-scale systems.
These pins are time multiplexed to operate as an
address bus and as processor status signals.
When used as the address bus, these pins are the high 4
bits of the 20-bit memory address. During 1/0 access,
all 4 bits output data O.
The processor status signals are provided for both
memory and 1/0 use. PS3 is always 0 in the native mode
and 1 in 8080 emulation mode. The interrupt enable
flag (IE) is on pin PS2. Pins PS1 and PS o indicate which
memory segment is being accessed.
A17 /PS I
AI 6/PS O
0
0
Data segment 1
0
1
Stack segment
0
Program segment
BS 2
BS I
BSo
0
0
0
Interrupt acknowledge
0
0
1
1/0 read
0
110 write
0
0
1
The output of these pins is three state and becomes
high impedance during hold acknowledge.
QS1, QSO [Queue Status]
For large-scale systems.
The CPU uses these signals to allow external devices,
such as the floating-point arithmetic processor chip,
(pPD72091) to monitor the status of the internal CPU
instruction queue.
Instruction Oueue Status
OSI
OSo
0
0
NOP (queue does not change)
0
1
First byte of instruction
0
Flush queue
"Subsequent bytes of instruction
The instruction queue status indicated by these signals
is the status when the execution unit (EXU) accesses
the instruction queue. The data output from these pins
is therefore valid only for one clock cycle immediately
following queue access. These status signals are
provided so that the floating-point processor chip can
monitor the CPU's program execution status and
synchronize its operation with the CPU when control is
passed to it by the FPO (Floating Point Operation)
instructions. These outputs are held at a low level in the
standby mode.
BS2 - BSo [Bus Status]
For large-scale systems.
The CPU uses these status signals to allow an external
bus controller to mon itor what the cu rrent bus cycle is.
Bus Cycle
Halt
0
0
Program fetch
0
1
Memory read
0
Memory write
Passive state
Segment
Data segment 0
6
The external bus controller decodes these signals and
generates the control signals required to perform
access of the memory or I/O device.
The output of these signals is three state and becomes
high impedance during hold acknowledge. These outputs are held at high level in the standby mode.
BUSLOCK [Bus Lock]
For large-scale systems.
The CPU uses this signal to secure the bus while
executing the instruction immediately following the
BUSLOCK prefix instruction, or during an interrupt
acknowledge cycle. It is a status signal to the other bus
masters in a multiprocessor system, inhibiting them
from using the system bus during this time.
The output of this signal is three state and becomes
high impedance during hold acknowledge. BUSLOCK
is high during standby mode except if the HALT
instruction has a BUSLOCK prefix, then it is held low.
RQ/AK1, RQ/AKo [Hold Request/Acknowledge]
For large-scale systems.
These pins function as bus hold request inputs (RQ)
and as bus hold acknowledge outputs (AK). RQ/AKo
has a higher priority than RQ/AK1.
These pins have three-state outputs with on-chip pullup resistors which keep the pin at a high level when the
output is high impedance.
Voo [Power Supply]
For small- and large-scale systems.
This pinis used for the +5 V power supply.
GN D [Ground]
For small- and large-scale systems.
This pin is used for ground.
IC [Internally Connected]
This pin is used for tests performed at the factory by
NEC. The pPD70108 is used with this pin at ground
potential.
NEe
pPD70108 (V20)
Absolute Maximum Ratings
Capacitance
TA
TA = +25°C, Voo = 0 V
= +25°C
Power supply voltage, Voo
-0.5 V to +7.0 V
Power dissipation, PDMAX
0.5W
Input voltage, VI
-0.5 V to Voo + 0.3 V
ClK input voltage, VK
-0.5 V to Voo + 1.0 V
Output voltage, Vo
-0.5 V to Voo + 0.3 V
limits
Parameter
Symbol
Min
Max
Input capacitance
C1
15
1/0 capacitance
CIO
15
Unit
Test
Conditions
fc = 1 MHz
Unmeasured pins
pF returned to 0 V
pF
Operating temperature at 5 MHz, TOPT
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
TA
= -10°C to +70°C, Voo = +5 V ± 5%
Limits
Parameter
Symbol
Min
Typ
Max
Unit
Test
Conditions
Input voltage high
VIH
2.2
Voo +0.3
V
Input voltage low
VIL
-0.5
0.8
V
ClK input voltage high
VKH
3.9
VOO + 1.0
V
ClK input voltage low
VKL
-0.5
0.6
V
Output voltage high
VOH
0.7 x Voo
V
IOH = -400 JlA
V
IOL =2.5 mA
JlA
Output voltage low
VOL
0.4
Input leakage current high
IUH
10
Input leakage current low
IUL
-10
JlA
Output leakage current high
ILOH
10
JlA
Vo = Voo
Output leakage current low
ILOL
-10
JlA
Vo =OV
Normal operation
Supply current
100
70108-8
45
80
rnA
8 MHz
6
12
mA
Standby mode
70108-10
60
100
mA
Normal operation
10 MHz
7
14
mA
Standby mode
7
NEe
pPD7 0·108. (V20)
AC Characteristics
TA = -10°C to +70°C, Voo = +5 V ± 5%
ttPD70108-8
ttPD70108-10
Symbol
MIa.
Max
Min
Max
Unit
Clock cycle
tCYK
125
500
100
500
ns
Clock pulse width high
tKKH
44
41
ns
VKH =3.0 V
Clock pulse width low
tKKL
60
49
ns
VKL = 1.5 V
Clock rise time
tKR
10
5
ns
1.5 V to 3.0 V
Clock fall time
tKF
10
5
ns
3.0 V to 1.5 V
Parameter
Conditions
Small/large Scale
READY inactive setup to ClKl
tSRYLK
-8
--:-10
ns
READY inactive hold after ClKt
tHKRYH
20
20
ns
READY active setup to ClKt
tSRYHK
tKKL - 8
tKKL -10
ns
READY active hold after ClKt
tHKRYL
20
20
ns
Data setup time to ClK l
tSDK
20
10
ns
Data hold time after ClK l
tHKD
10
10
ns
NMI, INT, POLL setup time
to ClK t
tSIK
15
15
ns
Input rise time (except ClK)
tlR
20
20
ns
0.8 V to 2.2 V
Input fall time (except ClK)
tlF
12
12
ns
2.2 V to 0.8 V
Output rise time
tOR
20
,20
ns
0.8 V to 2.2 V
tOF
12
12
ns
2.2 V to 0.8 V
48
ns
Output fall time
Small Scale
Address delay time from ClK l
tDKA
10
Address hold time from ClK l
tHKA
10
PS delay time from ClK l
tDKP
10
60
10
50
ns
PS float delay time from ClK t
tFKP
10
60
10
50
ns
Address setup time to ASTB l
tSAST
tKKL - 30
Address float delay time from
ClK l
tFKA
tHKA
ASTB t delay time from ClK l
tDKsni
50
40
ns
ASTB l delay time from ClK t
tDKSTL
55
45
ns
60
10
10
ns
ns
tKKL - 30
60
tHKA
50
ns
ASTB width high
tSTST
tKKL - 10
tKKL -10
ns
Address hold time from ASTB l
tHSTA
tKKH -10
tKKH -10
ns
8
CL = 100 pF
N'EC
JlPD701 08 (V20)
AC Characteristics (cont)
TA = -1Q°C to +70°C, Voo = +5 V ± 5%
pPD70l08-8
pPD70l08-10
Symbol
Min
Max
Min
Max
Unit
Control delay time from ClK
tOKCT
10
65
10
55
ns
Address float to RD~
tAFRL
0
RD ~ delay time from ClK ~
tOKRL
10
80
10
70
ns
t delay time from ClK ~
tOKRH
10
80
10
60
ns
tORHA
tCYK - 40
Parameter
Conditions
Small Scale (conti
RD
Address delay time from RD
t
RD width low
ns
0
ns
tCYK - 35
ns
2tCYK-40
tRR
2tCYK-50
Data output delay time from
ClK!
tOKO
10
60
10
50
ns
Data float delay time from
ClK!
tFKO
10
60
10
50
ns
tww
2tCYK-40
2tCYK-35
ns
tSHQK
20
20
ns
tOKHA
10
100
Address delay time from ClK ~
tOKA
10
60
Address hold time from ClK ~
tHKA
10
PS delay time from ClK ~
tOKP
10
60
10
50
ns
tFKP
10
60
10
50
ns
Address float delay time from
ClK ~
tFKA
tHKA
60
tHKA
50
ns
t
tORHA
tCYK - 40
WR width low
HlDRQ setup time to ClK
t
HlDAK delay time from ClK ~
10
60
ns
10
48
ns
CL = 100 pF
Bl
large Scale
t
PS float delay time from ClK
Address delay time from RD
ASTB delay time from BS ~
BS ~ delay time from ClK
t
ns
tCYK -35
15
tOBST
ns
10
15
ns
tOKBL
10
t delay time from ClK ~
tOKBH
10
RD ~ delay time from address
float
tOAFRL
0
RD ! delay time from ClK ~
tOKRL
10
80
10
70
t delay time from ClK !
tOKRH
10
80
10
60
RD width low
tRR
2tCYK-50
Date output delay time from
ClK ~
tOKO
10
60
10
50
ns
Data float delay time from
ClK!
tFKO
10
60
10
50
ns
AK delay time from ClK ~
tOKAK
BS
RD
RQ setup time to ClK
t
RQ hold time from ClK
RQ hold time from ClK
tSRQK
t
t
60
10
50
ns
65
10
50
ns
CL = 100 pF
ns
ns
ns
2tCYK-40
50
10
ns
0
40
ns
9
ns
tHKRQ
0
0
ns
tHKRQ2
30
20
ns
Q
NEe
pPD70108 (V20)
Timing Waveforms
Clock Timing
AC Test Input Waveform [Except ClK]
~::~
2.2V
=x>
2.2V
Test Points E
49·000241A
49·000242A
Write Timing [Large Scale)
Read Timing [Large Scale)
elK
elK
Alg/PS3 _ ...,.---"",-,,...--~ Ir-::.:;:.~f---+l_-+~
A16I' PSo
A,g/PS3- --~'~-~'r-------~~~,r_
A,slPSo
LBSo
LBSo
AD7- ADo
AD7-ADo
ASTB
(71088
Output)
ASTB
(71088
Output)
JI
\~____Bu_s_S_ta_tu_s___
as, - aso _ _...1-.'----_----1 '---_ _.I ' -_ _---1 '---_-----"l.I ,_
>E
A,s-Ae~
- - - " " - - - - - - - _........
49-000244A
A,s-Ae
___
J~------------------------~~
49-000243A
11
NEe
pPD70108 (V20)
Timing Waveforms (cont)
Interrupt Acknowledge Timing
ClK
ASTB
BUFR/W
101M
tOKA
BUSlOCK*
~ltFKA
A'5-AB~~-----------------------------------------------------------* : Large Scale Mode Only
Hold Request/Acknowledge Timing [Small'Scale]
lor2
ClK
HlDRQ
HlDAK
* : A,/PS 3 - A,",PS., A15 - AB, AD7 - AD.,
12
RD, lBS., 101M, BUFR/W, WR BUFEN
NEe
JiPD701 08 (V20)
Timing Waveforms (cont)
ClK
RQ/AK
Pulse 2 Ai(
Pulse 1 RQ
70108 Input
Pulse 3 RQ
70108 Input
70108 Jut ut
---------------------------------------~~----------:I_:_.__ ~----~~--------------t
::
t_FK_A__
70108
• A1 g/PS3 -A1 6/PSo, AD1 s-ADo, B~ -BSc!, RD, BUS LOCK
:
h
Coprocessor
U
83IH-5510B
13
NEe
JlPD70108 (V20)
Register Configuration
Program Counter [PC]
The program counter is a 16-bit binary counter that
contains the segment offset address of the next
instruction which the EXU is to execute.
The PC increments each time the microprogram fetches
an instruction from the instruction queue. A new
location value is loaded into the PC each time a branch,
call, return, or break instruction is executed. At this
time, the contents of the PC are the same as the
Prefetch Pointer (PFP).
Prefetch Pointer [PFP]
The prefetch pOinter (PFP) is a 16-bit binary counter
which contains a segment offset which is used to
calculate a program memory address that the bus
control unit (BCU) uses to prefetch the next byte for
the instruction queue. The contents of PFP are an
offset from the PS (Program Segment) register.
The PFP is incremented each time the BCU prefetches
an instruction from the program memory. A new
location will be loaded into the PFP whenever a branch,
call, return, or break instruction is executed. At that
time the contents of the PFP will be the same as those
of the PC (Program Counter).
Segment Registers [PS, SS, OSo, and OS1]
The memory add resses accessed by the pPD701 08 are
divided into 64K-byte logical segments. The starting
(base) address of each segment is specified by a 16-bit
segment register, and the offset from this starting
address is specified by the contents of another register
or by the effective address.
These are the four types of segment registers used.
Segment Register
Default Offset
PS (Program Segment)
PFP
SS (Stack Segment)
SP, effective address
DSo (Data Segment 0)
IX, effective address
DS1 (Data Segment 1)
IY
General-Purpose Registers [AW, BW, CW, and OW]
There are four 16-bit general-purpose registers. Each
one can be used as one 16-bit register or as two 8-bit
registers by dividing them into their high and low bytes
(AH, Al, BH, Bl, CH, Cl, DH, Dl).
Each register is also used as a default register for
processing specific instructions. The default assignments are:
AW: Word multiplication/division, word I/O, data
conversion, translation, BCD rotation.
Al: Byte multiplication/division, byte I/O, BCD
rotation, data conversion, translation
AH: Byte multiplication/division
BW: Translation
CW: loop control branch, repeat prefix
Cl: Shift instructions, rototation instructions,
BCD operations
DW: Word multiplication/division, indirect
addressing I/O
Pointers [SP, BP] and Index Registers [IX, IV]
These registers serve as base pOinters or index registers
when accessing the memory using based addressing,
indexed addressing, or based indexed addressing.
These registers can also be used for data transfer and
arithmetic and logical operations in the same manner
as the general-purpose registers. They cannot be used
as 8-bit registers.
Also, each of these registers acts as a default register
for specific operations. The default assignments are:
SP: Stack operations
IX: Block transfer (source), BCD string operations
IY: Block transfer (destination), BCD string operations
Program Status Word [PSW]
The program status word consists of the following six
status and four control flags.
Status Flags
Control Flags
• V (Overflow)
• MD (Mode)
• S (Sign)
• DIR (Direction)
• Z (Zero)
• IE (Interrupt Enable)
• AC (Auxiliary Carry)
• BRK (Break)
• P (Parity)
• CY (Carry)
When the PSW is pushed on the stack, the word images
of the various flags are as shown here.
PSW
15
M
14
13
12
11
V
10
9 8 7 6 5 4 3 2 1 0
D IBSZOAOP
DIE R
C
R
K
C
Y
The status flags are set and reset depending upon the
result of each type of instruction executed.
I nstructions are provided to set, reset, and complement
the CY flag directly.
Other instructions set and reset the control flags and
control the operation of the CPU.
The MD flag can be set/reset only by the BRKEM,
RETEM, CAllN, and RETI instructions.
1.1
NEe
pPD70108 (V20)
High·Speed Execution of Instructions
Example
Th is section high lights the major arch itectural features
that en hance the performance of the pPD701 OB.
ADD
• Dual data bus in EXU
• Effective address generator
• 16/32-bit temporary registers/shifters (TA, TB)
• 16-bit loop counter
• PC and PFP
Dual Data Bus Method
Step 1 TA-AW
TA -AW, TB -
Step2TB -
BW
AW-TA+TB
Step 3 AW -
TA + TB
To reduce the number of processing steps for instruction execution, the dual data bus method has
been adopted for the pPD7010B (figure 1). The two
data buses (the main data bus and the subdata bus) are
both 16 bits wide. For addition/subtraction and logical
and comparison operations, processing time has been
reduced by some 30% over single-bus systems.
Figure 1.
Dual Data Buses
AW,BW
;AW-AW+BW
Single Bus
Dual Bus
BW
Effective Address Generator
The Effective Address Generator (EAG) (figure 2) is a
dedicated block of high-speed logic that computes
effective addresses in two clock cycles. If an instruction
uses memory, EAG decodes the second and/or third
instruction bytes to determine the addressing mode,
initiates any bus cycles needed to fetch data required
to compute the effective address, and stores the
computed effective address in the Data Pointer (DP)
register.
Calculating an effective address by the microprogramming method normally requires 5 to 12 clock cycles.
This circuit requires only two clock cycles for
addresses to be generated for any addressing mode.
Thus, processing is several times faster.
Figure 2.
Effective Address Generator
2nd or 3rd byta of Instruction
Registers
mod
rIm
EA Ganarator
16
16
Effective Address
83IH·5535A
16/32-Bit Temporary Registers/Shifters [TA, TBl
These 16-bit temporary registers/shifters (TA, TB)
are provided for multiplication/division and shift!
rotation instructions.
These circuits have decreased the execution time of
multiplication/division instructions. In fact, these
instructions can be executed about four times faster
than with the microprogramming method.
Subdata bus
Main data bus
83-000103A
TA + TB: 32-bit temporary register/shifter for multiplication and division instructions.
TB: 16-bit temporary register/shifter for shift/rotation
instructions.
15
1:'-1
I:iiI
NEe
pPD70108 (V20)
Loop Counter [LC]
Enhanced· Stack Operation Instructions
This counter is used to count the number of loops for a
primitive block transfer instruction controlled by a
repeat prefix instruction and the number of shifts that
will be performed for a multiple bit shift/rotation instruction.
This instruction allows immediate data to be pushed
onto the stack.
The processing performed for a multiple bit rotation of
a register is shown below. The average speed is
approximately doubled overthe microprogram method.
These instructions allow the contents of the eight
general registers to be pushed onto or popped from
the stack with a single instruction.
Example
Enhanced Multiplication Instructions
RORC
AW, CL
; CL
Microprogram method
8 + (4 x 5)
= 28 clocks
=5
LC method
7 + 5 = 12 clocks
PUSH imm
PUSH R/POP R
MUL reg16,imm16/MUL mem16, imm16.
These instructions allow the contents of a register or
memory location to be 16-bit multiplied by immediate
data.
Program Counter and Prefetch Pointer [PC and PFP]
Enhanced Shift and Rotate Instructions
ThepPD70108 microprocessor has a program counter,
(PC) which addresses the program memory location of
the instruction to be executed next, and a prefetch
pointer(PFP), which addresses the program memory
location to be accessed next. Both functions are
provided in hardware. A time saving of several clocks
is realized for branch, call, return, and break instruction
execution, compared with microprocessors that have
only one instruction pointer.
SHL reg, immS/SHR reg, immS/SHRA reg, immS
These instructions allow the contents of a register tobe.
shifted bythe number of bits defined by the immediate
data.
ROL reg, immS/ROR reg, immS/ROLC reg, immSI
RORC reg, immS
Enhanced Instructions
These instructions allow the contents of a register to be
rotated by the number of bits defined by the immediate
data.
I n addition to the pPD8088/86 instructions, the
pPD70108 has the following enhanced instructions.
CHKINO reg16, mem32
Instruction
Function
PUSH imm
Pushes immediate data onto stack
PUSH R
Pushes B general registers onto stack
POP R
Pops B general registers from stack
MUL imm
Executes 16-bit multiply of register or memory contents.
by immediate data
SHL immB
SHR immB
SHRA immB
ROL immB
ROR immB
ROLC immB
RORC immB
Shifts/rotates register or memory by immediate
value
CHKIND
Checks array index against designated boundaries
INM
Moves a string from an I/O port to memory
This instruction is used to verify that index values
pointing to the elements of an array data structure are
within the defined range. The lower limit of the array
should be in memory location mem32, the upper limit
in mem32 + 2. Ifthe index value in reg16 is not between
these limits when CHKIND is executed, a BRK 5 will
occur. This causes a jump to the location in interrupt
vector 5.
Block 1/0 Instructions
OUTM OW, src-block/lNM dst-block, OW
These instructions are used to output or input a string
to or from memory, when preceded by a repeat prefix.
OUTM
Moves a string from memory to an I/O port
PREPARE
Allocates an area for a stack frame and copies previous
frame pointers
DISPOSE
Frees the current stack frame on a procedure exit
16
Check Array Boundary Instruction
Stack Frame Instructions
PREPARE imm16, immS
This instruction is used to generate the stack frames
required by block-structured languages, such as
PASCAL and Ada. The stack frame consists of two
areas. One area has a pointer that points to another
frame which has variables that the current frame can
access. The other is a local variable area for the current
procedure.
NEe
J.lPD70108 (V20)
DISPOSE
Variable Length Bit Field Operation Instructions
This instruction releases the last stack frame generated
by the PREPARE instruction. It returns the stack and
base pointers to the values they had -before the
PREPARE instruction was used to call a procedure.
This category has two instructions: INS (Insert Bit
Field) and EXT (Extract Bit Field). These instructions
are highly effective for computer graphics and highlevel languages. They can, for example, be used for
data structures such as packed arrays and record type
data used in PASCAL.
Unique Instructions
In addition to the pPD8088/86 instructions and the
enhanced instructions, the pP0701 08 has the following
unique instructions.
Instruction
Function
INS
Insert bit field
INS regS, regS/INS regS, imm4
This instruction (figure 3) transfers low bits from the
16-bit AW register (the number of bits is specified by
the second operand) to the memory location specified
by the segment base (OS1 register) plus the byte offset
(IY register). The starting bit position within this byte is
specified as an offset by the lower 4-bits of the first
operand.
~
1:"-11
EXT
Extractbit field
ADD4S
Adds packed decimal strings
SUB4S
Subtracts one packed decimal string from another
CMP4S
Compares two packed decimal strings
ROL4
Rotates one BCD digit left through AL lower 4 bits
ROR4
Rotates one BCD digit right through AL lower 4 bits
TEST1
Tests a specified bit and sets/resets Z flag
NOT1
Inverts a specified bit
After each complete data transfer, the IY register and
the register specified by the first operand are automatically updated to point to the next bit field.
CLR1
Clears a specified bit
Either immediate data or a register may specify the
number of bits transferred (second operand). Because
the maximum transferable bit length is 16-bits, only the
lower 4-bits of the specified register (OOH to OFH) will
be valid.
SET1
Sets a specified bit
Bit field data may overlap the byte bou ndary of memory.
REPC
Repeats next instruction until CY flag is cleared
REPNC
Repeats next instruction until CY flag is set
FP02
Additional floating point processor call
Figure 3.
Bit Field Insertion
Bit length
15
AW
Byte offsel (IY)
I
~
:
I
Byte boundary
Memory
t
Segment base (051)
83-00010SA
17
NEe
pPD70108(V20)
EXT reg8, regS/EXT regS, imm4
ADD4S
This instruction (figure 4) loads to the AW register the
bit field data whose bit length is specified by the
second operand of the instruction from the memory
location that is specified by the DSO segment register
(segment base), the IX index register (byte offset), and
the lower 4-bits of the first operand (bit offset).
This instruction adds the packed BCD string addressed
by the IX index register to the packed BCD string
addressed by the IY index register, and stores the
result in the string addressed by the IY register. The
length of the string (number of BCD digits) is specified
by the CL register, and the result of the operation will
affectthe overflow flag (V), the carry flag (CY), and
zero flag (2:).
After the transfer is complete, the IX register and the
lower 4-bits of the, first operand are automatically
updated to point to the next bit field.
Either immediate data or'a register may be specified for
the second operand. Because the maximum trans."
ferrable bit length is 16 bits, however, only the lower
4-bitsofthe specified register (OH to OFH) will bevalid.
Bit field data may overlap the byte boundary of memory.
Packed BCD Operation Instructions
The instructions described here process packed BCD
data either as strings (ADD4S, SUB4S, CMP4S) or
byte-format operands (ROR4, ROL4). Packed BCD
strings may be from 1 to 254 digits in length.
When the number of digits is even, the zero and carry
flags will be set according to the result of the operation.
When the number of digits is odd, the zero and carry
flags may not be set correctly in this case, (CL = odd),
the zero flag will not be set unless the upper4 bits of the
highest byte are all zero. The carry flag will not be set
unless there is a carry out of the upper 4 bits of the
highest byte. When CL is odd, the contents of the upper
4 bits of the highest byte of the result are undefined.
BCD string (IY, CL) string (IX, CL)
BCD string (IY, CL)
+ BCD
SUB4S
This instruction subtracts the packed BCD string
addressed by the IX index register from the packed
BCD string addressed by the IY register, and stores the
result in the string addressed by the IY register. The
length of the string (number of BCD digits) is specified
by the CL register,and the result of the operation will
affect the overflow flag (V), the carry flag (CY), and
zero flag (Z).
BCD string (IY, CL) String (IX, CL)
BCD string (IY, CL) - BCD
CMP4S
This instruction performs the same operation as
SU B4S except that the resu It is not stored and on Iy the
overflow (V), carry flags (CY) and zero flag (Z) are
affected.
BCD string (IY, CL) - BCD string (IX, CL)
Figure 4. Bit Field Extraction
t )
Segment base (050)
83-0001078
18
N"EC
JlPD70108 (V20)
ROL4
REPNC
This instruction (figure 5) treats the byte data of the
register or memory directly specified by the instruction
byte as BCD data and uses the lower 4-bits of the AL
register (ALL) to rotate that data one BCD digit to the
left.
This instruction causes the pPD70108 to repeat the
following primitive block transfer instruction until the
CYflag becomes set or the CW register is decremented
to zero.
Figure 5.
BCD Rotate Left (ROL4)
Floating Point Instruction
FP02
This instruction is in addition to the pPD8088/86
floating point instruction, FP01. These instructions
are covered in a later section.
Mode Operation Instructions
ROR4
This instruction (figure 6) treats the byte data of the
register or memory directly specified by the instruction
byte as BCD data and uses the lower 4-bits of the AL
register (ALL) to rotate that data one BCD digit to the
right.
Figure 6.
BCD Rotate Right (ROR4)
The pPD70108 has two operating modes (figure 7).
One is the native mode which executes pPD8088/86,
enhanced and unique instructions. The other is the
8080 emulation mode in which the instruction set of the
pPD8080AF is emulated. A mode flag (MD) is provided
to select between these two modes. Native mode is
selected when M D is 1 and emu lation mode when M D is
O. MD is set and reset, directly and indirectly, by
executing the mode manipulation instructions.
Two instructions are provided to switch operation from
the native mode to the emulation mode and back:
BRKEM (Break for Emulation), and RETEM (Return
from Emulation).
Two instructions are used to switch from the emulation
mode to the native mode and back: CALLN (Call Native
Routine), and RETI (Return from Interrupt).
Bit Manipulation Instructions
TEST1
This instruction tests a specific bit in a register or
memory location. If the bit is 1, the Z flag is reset to O. If
the bit is 0, the Z flag is set to 1.
NOT1
The system will return from the 8080 emulation mode
to the native mode when the RESET signal is present,
or when an external interrupt (NMI or INT) is present.
Figure 7.
V20 Modes
HOLD REO/HOLD ACK
This instruction inverts a specific bit in a register or
memory location.
CLR1
This instruction clears a specific bit in a register or
memory location.
SET1
This instruction sets a specific bit in a register or
memory location.
Repeat Prefix Instructions
!
t
~
~ndbY
Mode
J - - - - HOLD REO/HOLD ACK
REPC
This instruction causes the pPD701 08 to repeat the
following primitive block transfer instruction until the
CY flag becomes cleared or the CW register becomes
zero.
83-000775A
19
NEe
pPD70108(V20)
BRKEM immB
RETEM [no operand]
This is the basic instruction used to start the BOBO
emulation mode. This instruction operates exactly the
same as the BRK instruction, except that BRKEM
resets the mode flag (MO) to O. PSW, PS, and PC are
saved to the stack. M 0 is then reset and the interru pt vector
specified by the operand immB of this command is
loaded into PS and PC.
When RETEM is executed in B080 emulation mode
(interpreted by the CPU as a pPOBOBOAF instruction),
the CPU restores PS, PC, and PSW (as it would when
returning from an interrupt processing routine), and
returns to the native mode. At the same time, the
contents of the mode flag (MO) which was saved to the
stack by the BRKEM instruction, is restored to MO = 1.
The CPU is set to the native mode.
The instruction codes of the interrupt processing
routine jumped to are then fetched. Then the CPU
executes these codes as pPOBOBOAF instructions.
In BOBO emulation mode, registers and flags of the
pPOB080AF are performed by the following registers
and flags of the pP0701 OB.
Registers:
I1P08080AF
I1P070108
A
B
C
AL
CH
CL
DH
DL
BH
BL
BP
PC
CY
0
E
H
Flags:
SP
PC
C
Z
Z
S
P
AC
S
AC
In the native mode, SP is used forthe stack pointer. In the
BOBO emulation mode this function is performed by BP.
This use of independent stack pointers allows independent stack areas to be secured for each mode and
keeps the stack of one of the modes from being
destroyed by an erroneous stack operation in the other
mode.
The SP, IX, IY and AH registers and the four segment
registers (PS, SS, OSo, and OS1) used in the native
mode are not affected by operations in BOBO emulation
mode.
In the 80BO emulation mode, the segment register for
instructions is determined by the PS register (set
automatically by the interrupt vector) and the segment
register for data is the OSo register (set by the
programmer immediately before the BOBO emulation
mode is entered).
It is prohibited to nest BRKEM instructions.
20
CALLN immB
This instruction makes it possible to call the native
mode subroutines from the 80BO emulation mode. To
return from subroutine to the emulation mode, the
RETI instruction is used.
The processing performed when this instruction is
executed in the BOBO emulation mode (it is interpreted
by the CPU as pPOBOBOAF instruction), is similar to
that performed when a BRK instruction is executed in the
native mode. The immB operand specifies an interrupt
vector type. The contents of PS, PC, and PSW are
pushed on the stack and an MO flag value of 0 is saved.
The mode flag is set to 1 and the interrupt vector
specified by the operand is loaded into PS and PC.
RETI [no operand]
This is a general-purpose instruction used to return
from interrupt routines entered by the BRK instruction
or by an external interrupt in the native mode. When
this instruction is executed at the end of a subroutine
entered by the execution of the CALLN instruction,_ the
operation that restores PS, PC, and PSW is exactly the
same as the native mode execution. When PSW is
restored, however, the BOBO emulation mode value of
the mode flag (MO) is restored, the CPU is set in
emulation mode, and all subsequent instructions are
interpreted and executed as pPOBOBOAF instructions.
RETI is also used to return from an interrupt procedure
initiated by an NMI or INT interrupt in the emulation
mode.
Floating Point Operation Chip
Instructions
FP01 fp-op, mem/FP02 fp-op, mem
These instructions are used for the external floating
point processor. The floating point operation is passed
to the floating point processor when the CPU fetches
one of these instructions. From this point the CPU
performs only the necessary auxiliary processing
(effective address calculation, generation of physical
addresses, and start-up of the memory read cycle).
NEe
pPD70108 (V20)
The floating point processor always monitors the
instructions fetched by the CPU. When it interprets one
as an instruction to itself, it performs the appropriate
processing. At this time, the floating point processor
chip uses either the address alone or both theaddress
and read data of the memory read cycle executed by the
CPU. This difference in the data used depends on
which of these instructions is executed.
Note: During the memory read cycle initiated by the CPU for FP01
or FP02 execution, the CPU does not accept any read data
on the data bus from memory. Although the CPU generates
the memory address, the data is used by the floating pOint
processor.
Interrupt Operation
The interrupts used in the pPD7010B can be divided
into two types: interrupts generated by external interrupt requests and interrupts generated by software
processing. These are the classifications.
External Interrupts
(a) NMI input (nonmaskable)
(b) INT input (maskable)
The interrupt vector table is shown in figure B. The
table uses 1K bytes of memory addressesOOOH to
3FFH and can store starting address data for a
maximum of 256 vectors (4 bytes per vector).
The corresponding interrupt sources for. vectors 0
to 5 are predetermined and vectors 6 to 31 are reserved.
These vectors consequently cannot be used for
general applications.
The BRKEM instruction and CALLN instruction (in the
emulation mode) and the INT input are available for
general applications for vectors 32 to 255.
A single interrupt vector is made up of 4 bytes (figure 9).
The 2 bytes in the low addresses of memory are
loaded into PC as the offset, and the high 2 bytes are
loaded into PS as the base address. The bytes are
combined in reverse order. The lower-order bytes in
the vector become the most significant bytes in the PC
and PS, and the higher-order bytes become the least
significant bytes.
Figure 8.
Software Processing
OOOH
As the result of instruction execution
-
When a divide error occurs during execution
of the DIV or DIVU instruction
When a memory-boundary-over error is detected
by the CHKIND instruction
When V = 1 during execution of the BRKV
instruction
1-byte break instruction:
2-byte break instruction:
BRK3
BRK immB
Flag processing (Single-step)
-
Break Flag
Vector 2
NMllnput
Vector 3
BRK 3 Instruction
Vector 4
BRKV Instruction
VectorS
CHKIND Instruction
Dedicated
OOCH
014H
01SH
When stack operations are used to set the
BRK flag
}-".~.
Vector 6
07CH
Vector 31
OSOH
Vector 32
General Use
3FCH
BOBO Emulation mode instructions
-
Divide Error
Vector 1
OOSH
Unconditional break instructions
-
Vector 0
004H
010H
Conditional break instruction
-
Interrupt Vector Table
}
Vector 255
•
•
•
•
BRK ImmS Instruction
BRKEM Instruction
INT Input IExternal]
CALLN Instruction
BRKEM immB
CALLN immB
Interrupt Vectors
Starting add~esses for interrupt processing routines
are either determined automatically by a single location
of the interrupt vector table or selected each time
interrupt processing is entered.
83-000111A
Figure 9.
Interrupt Vector 0
Vector 0
OOOH
002H
:
I
001H
003H
PS <--- (OO3H, 002H)
PC <--- (OO1H, OOOH)
83-000112A
NEe
J,lPD70108(V20)
Based on this format, the contents of each vector
should be initialized at the beginning of the program.
The basic steps to jump to an interrupt processing
routine are now shown.
(SP -1, SP - 2) - PSW
(SP - 3, SP - 4) - PS
(SP - 5, SP - 6) - PC
SP +- SP - 6
IE - 0, BRK - 0, MD PS +- vector high bytes
PC +- vector low bytes
For con,ditional control transfer or branch instructions,
the number on the left side of the slash is applicable if
thetransfer or.,branch takes. place. The number on the
right side is applicable if it does not take place.
If a range of numbers is given, the execution time
depends on the operands involved.
Symbols
0
Standby Function
The pPD70116 has a standby mode to reduce power
consumption during program wait states. This mode is
set by the HALT instruction in both the native and the
emulation mode.
In the standby mode, the internal clock is supplied only
to those circuits related to functions required to
release this mode and bus hold control functions. As a
result, power consumption can be reduced to 1/10 the
level of normal operation in either native or emulation
mode.
Symbol
Meaning
acc
Accumulator (AW or AL)
disp
Displacement (8 or 16 bits)
dmem
Direct memory address
dst
Destination operand or address
ext-disp8
16-bit displacement (sign-extension byte
+ 8-bit displacement)
far_label
Label within a different program
segment
Procedure within a different program
segment
Floating point instruction operation
imm
8- or 16-bit immediate operand
The standby mode is released by inputting a RESET
signal or an external interrupt (NMI, INT).
imm3/4
3- or 4-bit immediate bit offset
imm8
8-bit immediate operand
The bus hold function is effective during standby
mode. The CPU returns to standby mode when the bus
hold request is removed.
imm16
16-bit immediate operand
mem
Memory field (000 to 111);
8- or 16-bit memory location
During standby mode, all control outputs are disabled
and the addresldata bus will be at either high or low
levels.
mem8
8-bit memory location
Instruction Set
mem16
16-bit memory location
mem32
32-bit memory location
memptr16
Word containing the destination address
within the current segment
memptr32
Double word containing a destination
address in another segment
mod
Mode field (00 to 10)
Symbols
Preceding the instruction set, several tables explain
symbols, abbreviations, and codes.
Clocks
Label withinthe current segment
In the Clocks column of the instruction set, the numbers
cover these operations: instruction decoding, effective
address calculation, operand fetch, and instruction
execution.
Procedure within the current segment
offset
Clock timings assume the instruction has been prefetched and is present in the four-byte instruction
queue. Otherwise, .add four clocks for each byte not
present.
reg
Register field (000 to 111);
8- or 16-bit general-purpose register
reg8
8-bit general-purpose register
reg16
16-bit general-purpose register
regptr
16-bit register containing a destination
address within the current segment
regptr16
Register containing a destination address
within the current segment
seg
Immediate segment data (16 bits)
shorUabel
Label between -128 and +127 bytes from
the end of the current instruction
For instructions that reference memory operands, the
number on the left side of the slash (I) is for byte
operands and the number on the right side is for word
operands.
22
Immediate offset data (16 bits)
Number of bytes to discard from the stack
NEe
pPD70108 (V20)
Symbols (cant)
Symbol
Meaning
Symbol
Meaning
sr
Segment register
IY
Index register (destination) (16 bits)
src
Source operand or address
MD
Mode flag
temp
Temporary register (8/16/32 bits)
OR V
Logical sum
tmpcy
Temporary carry flag (1 bit)
P
Parity flag
AC
Auxiliary carry flag
PC
Program counter (16 bits)
AH
Accumulator (high byte)
PS
Program segment register (16 bits)
AL
Accumulator (low byte)
PSW
Program status word (16 bits)
ANDA
Logical product
R
Register set
AW
Accumulator (16 bits)
S
BH
BW register (high byte)
Sign extend operand field
S=O No sign extension
S=1 Sign extend immediate byfu
operand
BL
BW register (low byte)
BP
Base pointer (16 bits)
S
Sign flag
BRK
Break flag
SP
Stack pointer (16 bits)
BW
BW register (16 bits)
SS
Stack segment register (16 bits)
CH
CW register (high byte)
TA
Temporary register A (16 bits)
CL
CW register (low byte)
TB
Temporary register B (16 bits)
CW
CW register (16 bits)
TC
Temporary register C (16 bits)
Carry flag
V
Overflow flag
DH
DW register (high byte)
W
Word/byte field (0 to 1)
DIR
Direction flag
X, XXX, YYY, ZZZ
DL
DW register (low byte)
Data to identify the instruction code of the
external floating pOint arithmetic chip
DSO
Data segment 0 register (16 bits)
CY
DS1
Data segment 1 register (16 bits)
DW
DW register (16 bits)
IE
Interrupt enable flag
IX
Index register (source) (16 bits)
XOR ..If
Exclusive logical sum
XXH
Two-digit hexadecimal value
XXXXH
Four-digit hexadecimal value
Z
Zero flag
()
Values in parentheses are memory contents
Transfer direction
+
Addition
Subtraction
x
Multiplication
Division
%
Modulo
Em
NEe
pPD70108 (V20)
Flag Operations
Register Selection (mod
W=l .
000
AL
AW
001
CL
CW
Set to 1
010
DL
DW
Set or cleared according to result
011
BL
BW
Undefined
100
AH
SP
Meaning
reg
(blank)
No change
o
Cleared to 0
R
Restored to previous state
Memory Addressing Modes
mem
mod = 00
000
001
11)
W=O
Symbol
x
=
101
CH
BP
110
DH
IX
111
BH
IY
mod = 01
mod = 10
BW+IX
BW + IX + disp8
BW + IX + disp16
BW+IY
BW + IY + disp8
BW + IY + disp16
sr
Segment Register
010
BP + IX
BP + IX + disp8
BP + IX + disp16
00
DS1
011
BP+ IY
BP +IY'+ disp8
BP + IY + disp16
01
PS
100
IX
IX + disp8
IX + disp16
10
SS
101
IY
IY + disp8
IY + disp16
11
DSO
110
Direct'
BP + disp8
BP + disp16
111
BW
BW + disp8
BW + disp16
t'lA
Segment Register Selection
NEe
pPD70108 (V,20)
Instruction Set
Mnemonic
Operand
0
6 5 4 3
Opcode
7 6 543 2 1 0
Clocks
Bytes
Flags
AC CY V P
S Z
Data Transfer Instructions
MOV
reg, reg
0 0 0
0 1 W
mem, reg
0
0 0 W
reg, mem
0 0 1 0
mem, imm
1 0 0 0
reg, imm
0
ace, dmem
0
1 W
reg
reg
mod
reg
mem
9/13
W
mod
reg
mem
11/15
2-4
W
mod 000
mem
11/15
3-6
reg
0 0
oW
0 0
W
dmem, ace
1
sr, reg16
0 0
0
sr, mem16
0 0
1 0
mod 0 , sr
1 0 0 0
0 0
1 1 0
sr
reg
0 0
mod 0
sr
reg16, sr
mem16, sr
0
0
0 0 0 ,1
OSO, reg16, mem32
1 1 0
sr
reg
mem
2
2-4
4
2-3
10/14
3
9/13
3
2
2
11/15
2-4
2
2
mem
10/14
2-4
0
mod
reg
mem
18/26
2-4
OS1, reg16, mem32
1 0 0 0
0 0
mod
reg
mem
18/26
2-4
AH, PSW
0 0
1
2
1
PSW, AH
0 0 1
,1
LOEA
reg16, mem16
0 0 0
0
TRANS
srctable
XCH
reg, reg
0 0 0 0
W
1 1
mem, reg
0 0 0 0
W
mod
AW, reg16
0 0
0
x x
3
mod
reg
mem
4
reg
reg
3
2
reg
mem
16/24
2-4
0
I!I
x x x
2-4
9
reg
0
2
Repeat Prefixes
REPC
0
0 0
0 1
2
REPNC
0
0 0 1 0 0
2
REP
REPE
REPZ
2
0 0
REPNE
REPNZ
1 1 1 1
o
01
0
2
Block Transfer Instructions
MOVBK
dst, src
0
0 0
CMPBK
dst, src
0
0 0
0 W
CMPM
dst
0
0
LOM
src
0
0
1 0 W
STM
dst
0
0
0
11
W
W,
+Bn
x x x x x x
x x x x x x
7 + 14n
7 + 10n
7 +9n
W
7 +4n
n = number of transfers
110 Instructions
IN
OUT
ace, imm8
0
0 W
9/13
ace, OW
0 1
0 W
8/12
W
8/12
immB, ace
0 0
OW, ace
1
INM
dst, OW
0
OUTM
OW, src
0
0
0
1 W
8/12
0 W
9+8n
2
9 +Bn
W
n = number of transfers
25
NEe
pPD70108 (V20)
Instruction Set (cont)
Mnemonic
Operand
6 5 4
~
Opcode
076543210
2
Clocks
Bytes
Flags
AC CY V P S Z
BCD Instructions
ADJBA
0'0
1 0
3
ADJ4A
0 0
3
'1
0
7
1
0 1 0
7
ADD4S
o
o
o
o
000
o
0
000 0 0
7 + 19n
SUB4S
000 0
o
o
0
000
o
7 + 19n
0
0
o
o
1 0
o
o
0
o
ADJBS
ADJ4S
CMP4S
ROL4
ROR4
reg8
o
o
0
0 0 0
0 0 0 1
1 1 0 0 0
2
7 + 19n
2
000
25
3
000
28
3-5
0
xxuuuu
x 'x u x x x
xxuuuu
x x u x x x
uxuuux
uxuuux
uxuuux
reg
mem8
00001111
mod 0 0 0 mem
reg8
000011110000029
1 1 0 0 0
reg
3
mem8
0000111100
0
0
033
mod 0 0 0 mem
n = number of BCD digits divided by 2
3-5
Data Type Conversion Instructions
o
o
o
o
CVTDB
1 0
o
CVTBW
o
o
1 0 0
2
o
4-5
CVTBD
1
CVTWL
0
0
o
1 0
o
o
0 0 0
o
0 0 0
o
0
15
2
7
2
uuuxxx
uuuxxx
Arithmetic Instructions
ADD
reg, reg
0 0 0 0 0 0 1 W
1 1
reg
reg
2
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
-x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
--------~------------------------------------------------------------------
AD DC
mem, reg
o
reg, mem
0000001W
reg, imm
o
mem, imm
000 0 0 S W
0000010W
reg, reg
mem, reg
o
o
reg, mem
mod
reg
mem
mod
reg
mem
1 1 0 0 0
reg
mod
0 0 '0
mem
16/24
2-4
11/15
2-4
4
3-4
18/26
3-6
0 0 0 W
mod
reg
mod
reg
0 0 0 0 S W
1 1 0 1 0
reg
mod 0 1 0
mem
mem, reg
o
o
reg, mem
3-6
mem
0 0
0001001W
reg, reg
3-4
18/26
mem
reg
1 0 0 0 0 0 S W
2-4
2-3
reg
0001010W
11/15
4
2
1 1
mem, imm
2-4
4
0 0 1 W
o
16/24
2
0 0
ace, imm
reg, imm
26
0 0 0 0 S W
ace, imm
reg, imm
SUB
0 0 0 0 0 0 W
2-3
2
2
2-4
0
0
0 1 W
1 1
reg
0
0
0 0 W
mod
reg
rnem
16/24
0010101W
mod
reg
mem
11/15
2-4
4
3-4
OOOOOSW
1 1 1 0 1
reg
4
reg
NEe
pPD70108 (V20)
Instruction Set (cont)
Clocks
Byles
Flags
AC CY V P S Z
18/26
3-6
x x x x x x
Opcode
Mnemonic
543
o
0 0 0 0
S W
Operand
7
5 4 3 2 1 0
Arithmetic Instructions (cont)
SUB
mem, imm
mod
0
mem
--~---------------------------------------------------------------------------
ace, imm
SUBC
reg, reg
mem; reg
INC
DEC
MULU
o
o
2
x x x x x x
mem
16/24
2-4
x x x x x x
mem
11/15
2-4
x x x x x x
1 W
1 1
reg
reg
0 0
0 W
mod
reg
1 W
mod
reg
reg, mem
0
reg, imm
0
0 0 0 S W
1 1 0
reg
4
3-4
x x x x x x
mem, imm
0
0 0 0 S W
mod
mem
18/26
3-6
x x x x x x
1
ace, imm
0
0 W
4
2-3
x x x x x x
_r_e_g8___________________1__1__~______0____
1__
1__
0__
0__
0___r_eg____2
______2
______x
_____
x__x__x__x__
mem
1
1
reg16
0
0 0 0
reg8
1
W
1
1 1 0
1 1
mod 0 0
1
1 1
1 1 W
reg16
0
0 0
reg
reg
0
reg16,mem16,imm8
reg 16, reg 16, imm16
W
1 0 1
W
1 0 1
W
o
o
o
o
o
o
o
o
reg
o
mem
reg
mem
2-4
x
x x x x
x
x x x x
2
x
x x x x
x
x x x x
x
x x x x
16/24
2-4
21-30
2
uxxuuu
1 1
0 0
reg
mod
0 0
mem
27-36
2-4
uxxuuu
1 1
0
reg
33-47
2
uxxuuu
mod
0
mem
39-57
2-4
uxxuuu
reg
reg
28-34
3
uxxuuu
1
mod
reg
mem
34-44
3-5
uxxuuu
0
1 1
reg
reg
36-42
4
uxxuuu
mod
reg
mem
46-52
4-6
uxxuuu
0
reg
mem
0
16/24
2
1 1
0
o
reg16,mem16,imm16
mem
2
0 1 1 W
reg
mod 0 0 0
reg
mem
reg16,reg16,imm8
DIV
x x x x x x
2
0 0
mem
DIVU
2-3
0 W
mem
MUL
4
0 1 0
reg
19-25
2
uuuuuu
mem
25-35
2-4
uuuuuu
1 1
reg
29-43
2
uuuuuu
W
mod
1 1
mem
35-53
2-4
uuuuuu
0 1 W
1 1
reg
reg
2
2
W
1 1
0
W
mod
1 1 0
W
Comparison Instructions
CMP
reg, reg
0 0
x x x x x x
------------------~-----------------------------------------------------------
mem, reg
0 0
0 0 W
mod
reg
mem
reg,mem
00
01 W
reg, imm
1 0 0 0 0 0 S W
1 1 1 1
mod
reg
mem
mem, imm
1 0 0 0 0 0 S W
mod
ace, imm
0 0
1 1 1
reg
mem
0 W
11/15
2-4
x x x x x x
11/15
2-4
x x x x x x
4
3-4
x x x x x x
13/17
3-6
x x x x x x
4
2-3
x x x x x x
Logical Instructions
NOT
NEG
TEST
reg
0
W 1 1 0
o reg
2
2
------------------------------------------------------------------------------W
mod 0
0 mem
16/24
2-4
mem
0
o
W
1 1 0
reg
2
2
x x x x x x
mem
1
1 0
1 W
mod 0
mem
16/24
2-4
x x x x x x
reg, reg
000 0
1 1
reg
reg
2
2
uOOxxx
mem, reg
000 0
oW
oW
mod
reg
mem
10/14
2-4
u 0 0 x x x
reg, imm
1 0
W
reg
4
3-4
reg
1 1 0 0 0
o
0 x x x
~
~
NEe
pPD70108 (V20)
Instruction Set (cont)
Mnemonic
6 5 4 3 2
' Operand
Opcode
7
o
543210
Clocks
Bytes
Flags
AC CY V P S Z
11/15
3-6
u 0 0 x x x
2
2
u 0
Logical Instructions (cont)
TEST
AND
mem, imm
0 1 1 W
XOR
mem
reg, reg
0 0
0 0 0 1 W
reg, mem
0 0 1 0 0 0 1 W
reg, imm
0 0 0 0 0 W
1 1
reg
reg
x x x
mod
reg
mem
11/15
2-4
u 0 0 x x x
reg
4
3-4
u 0 0 x x x
18/26
3-6u 0 0 x x x
---------------------------------------------------------------------------mem, reg
0 0
0
0 0 W
mod
reg
mem
16/24
2-4
u 0 0 x x x
mem, imm
OR
mod 0 0 0
---------------------------------------------------------------------------ace, imm
1
0 1 0 0 W
4
2-3
u 0 0 x x x
0 0 0 0 0 0 W
1 1 10 0
mod
1 0 0
mem
ace, imm
0 0 1 0 0 1
reg, reg
0 0 0 0 1 0 1 W
1 1
reg
reg
mem, reg
o
0 0 W
mod
reg
reg, mem
0000101W
mod
reg
reg, imm
OOOOOOW
0 0 0
W
4
2-3
2
2
mem
16/24
2-4
mem
11/15
2-4
uOOxxx
reg
4
3-4
u 0 0 x x x
18/26
3-6
u 0 0 x x x
4
2-3
1 1 0 0 1
0 0 x x x
u 0 0 x x x
mem, imm
1 0 0 0 0 0 0 W
ace, imm
00001
reg, reg
0
0 0 1 W
1 1
reg
reg
2
mem, reg
o
o
0
0 0 0 W
mod
reg
mem
16/24
2-4
u 0 0 x x x
reg, mem
o
0 1 1 0 0 1 W
mod
reg
mem
11/15
2-4
uOOxxx
o
0 0 0 0 0 W
1 1
0
reg
4
3-4
mem, imm
1 0 0 0 0 0 0 W
mod
0
mem
18/26
3-6
ace, imm
o
4
2-3
0 0
35-133
3
o
35-133
4
0
34-59
3
o
34-59
4
reg, imm
0
mod 0 0 1, mem
u 0 0 x x x
OW
0 0
0 W
0 0 0 1
reg
1 1
u 0 0 x x x
u 0 0 x x x
o
0 x x x
u 0 0 x x x
o
0 x x x
Bit Manipulation Instructions
INS
EXT
reg8, reg8
o
'1, 1
reg
o
0
reg8, imm4
00001111
1 1 0 0 0
reg
o
0
reg8,reg8
o
0 0 0 1 1 1 1
1 1
reg
reg
o
0
reg8, imm4
o
o
0
0 0 0 1 1 1 1
'leg
o
o
0
1 1 0 0 0
TEST1
SET1
t)Q
reg, CL
o
0 0 0
1 1 0 0
1 1 1
reg
000
o
0 0 W
3
3
uOOuux
mem, CL
o
0 0 0
mod 0 0
1 1 1
mem
000
o
0
W
12/16
3-5
uOOuux
reg, imm3/4
o
1 1 1
reg
000
o
0, W
4
4
uOOuux
mem, imm3/4
00001111
mod 0 0 0 mem
000
o
0 W
13/17
4-6
uOOuux
reg, CL
0000
11 0 0
111000
reg
o
oW
4
3
mem,CL
00001111000
mod 0 0 0 mem
o
oW
13/21
3-5
0 0 0
1 1 0 0
f't{EC
pPD70108 (V20)
Instruction Set (cont)
Mnemonic
Operands
Opcode
0
7
7 6 5 4 3 2
5· 4 3 2
0
Clocks
Bytes
Flags
AC CV V P S Z
Bit Manipulation Instructions (cont)
SET1
reg, imm3/4
mem, imm3/4
0 0 0 0 1
1 1 0 0 0
0 0 0 0 1 1 1 1
mod 0 0 0 mem
CY
CLR1
1
0 0
DIR
1
1 1
1 0 1
reg, CL
o
0 0 1 1 1 1
0 0 0
reg
1
NOT1
0 0
0 W
5
0 0 0
0 W
14/22
reg
4-6
2
2
o
W
3
mem, CL
0000
mod 0 0
11100
mem
o
W
14/22
reg, imm3/4
0000111100
1 1 0 0 0
reg
o
W
6
mem, imm3/4
0000
mod 0 0
W
15/27
CY
1
0 0
2
DIR
1 1 1
1 0 0
2
reg, CL
o
1 1 1
reg
0
o
o
W
4
3
mem, CL
000011110
mod 0 0 0 mem
o
o
W
18/26
3-5
reg, imm3/4
0000
1 1 0 0
1110
reg
o
W
5
4
mem, imm3/4
000011110
mod 0 0 0 mem
o
W
19/27
4-6
0 0
1 1 0
11100
mem
CY
3-5
4-6
o
x
2
Shift/Rotate Instructions
SHL
SHR
reg, 1
0
reg, CL
mem, CL
reg, imm8
0
W
1 1
0 0
0
0 0 1 W
1 1
0 0
0
0 0 1 W
mod
0
0
0 0 0 W
1 1
0 0
reg
2
2
u x x x x x
uxuxxx
---------------------------------------------------------------------------mem, 1
0
W
mod
0 0 mem
16/24
2-4
u x x x x x
reg
7+ n
2
mem
19/27 + n
2-4
uxuxxx
reg
7+n
3
uxuxxx
mem, imm8
0 0 0 0
W
mod
mem
19/27 + n
3-5
u x u x x x
reg, 1
0
0 0
W
1 1
reg
2
2
u x x x x x
reg, CL
0
0 0
W
1 1
0
reg
7+ n
2
u x u x x x
mem, CL
0 1 0 0 1 W
mod
0
mem
19/27 + n
2-4
u x u x x x
reg, imm8
0 0 0 0 0 W
1 1
0
reg
7+ n
3
u x u x x x
mem, imm8
0 0 0 0 0 W
mod
19/27 + n
3-5
uxuxxx
---------------------------------------------------------------------------mem, 1
0
0 0 0 W
mod
0
mem
16/24
2-4
u x x x x x
mem
n = number of shifts
NEe
pPD70108 (V20)
Instruction Set (cont)
Mnemonic
Operands
Opcode
7 6 5 4 3 2 1 0
o
6 5 4 3 2
Clocks
Bytes
Flags
AC CY V P S Z
Shift/Rotate Instructions (cont)
SHRA
reg, 1
1
mod
2
u x 0 x x x
16/24
2-4
u x 0 x x x
01001W
1 1
reg
7+n
2
u x u x x x
01001W
mod
mem
19/27 + n
2-4
u x u x x x
reg, immS
o
o
o
o
o
o
0 0 0 0 W
1 1
reg
7+n
3
u x u x x x
000
mod 1
mem
19/27 + n
3-5
uxuxxx
2
2
reg, 1
mem, CL
reg, imm
mem, imm
W
1 1 0 0 0
reg
0 0 0 W
mod 0 0 0
mem
16/24
2-4
x x
0
1 1 0 0 0
reg
7+n
2
x u
W
1
0 1 W
mod 0 0 0
mem
0 0 0 W
1 1 0 0 0
reg
0 0 0 W
mod 0 0 0
o
0 W
1 1 0 0
0
19/27 + n
2-4
x u
7+n
3
x u
mem
19/27 + n
3-5
x u
reg
2
2
2-4
x x
x x
x u
mem, CL
o
o
o
19/27 + n
2-4
x u
reg, immS
000 0 0 W
1 1 0 0 1
reg
7+n
3
x u
mem, immS
OOOOOW
mod 0 0 1
mem
19/27 + n
3-5
x u
reg, 1
o
o
o
o
o
o
o
o
o
o
o
o
1 1 0
0
reg
2
2
x x
0 0 0 W
mod 0
0
mem
16/24
2-4
x x
0 0
W
1 1 0
0
reg
7+n
0 0 1 W
mod 0
0
mem
19/27 + n
2-4
x u
000 0 W
1 1 0
0
reg
7+n
3
x u
0 0 0 0 W
mod 0
0
mem
0 0 0 W
1 1 0
reg
0 0 0 W
mod 0
mem
0 0 1 W
1 1 0
reg
1 0 0 1 W
mod 0
mem
000 0 W
1 1 0
reg
0 0 0 0 W
mod 0
mem
reg, CL
mem,1
reg, CL
mem,CL
reg, immS
mem, immS
reg, 1
mem, 1
reg, CL
mem,CL
reg, immS
mem, immS
0 W
mod
mem
16/24
0 0
W
1 1
reg
7+n
0 0
W
oW
o
mem
mod 0 0
x u
19/27 + n
3-5
x u
2
2
x x
16/24
2-4
x x
7+n
2
x u
19/27 + n
2A
x u
7+n
3
x u
19/27 + n
3-5
x u
1S/26
2-4
n = number of shifts
Stack Manipulation Instructions
PUSH
x x
0 0 0 W
o
o
reg, 1
mem,1
RORC
2
reg, CL
reg, CL
ROLC
reg
mem
mem,CL
mem,1
ROR
0 0 W
000 0 W
mem, immS
ROL
o
o
mem,1
mem16
1
1
1 1 1 1
reg16
0
0
o
sr
0 0 0
1 0
S/12
PSW
1 0 0 1
1 0 0
S/12
R
o
o
o
o
0 0
35/67
S 0
7/12
imm
reg
sr
0
0
mod 1 1 0
mem
S/12
2-3
NEe
pPD70108 (V20)
Instruction Set (cont)
Mnemonic
Operands
Opcode
0
7 6 5 4 3 2 1 0
7 6 5 4
Clocks
Byles
17/25
2-4
Flags
AC CY V P S Z
Stack Manipulation Instructions (cont)
POP
PREPARE
mem16
1 0 0 0
reg16
0
sr
0
PSW
R
imm16, imm8
mod 0 0 0
mem
reg
0
8/12
sr
8/12
1 0
8/12
0
0 0 1
43/75
0
0 0 0
R R R R R R
*
*imm8 = 0: 16
imm8> 1: 23 + 16 (imm8 - 1)
DISPOSE
0 0
0
1
6/10
0
0
0
16/20
3
1m
Control Transfer Instructions
CALL
near_proc
regptr
1
memptr16
1 1
1
far_proc
0 0
0
1
1 1
memptr32
RET
pop_value
pop_value
BR
0
reg
14/18
2
mod 0
0
mem
23/31
2-4
0
mod 0
mem
21/29
5
31/47
2-4
0 0 0 0
1
15/19
0 0 0 0
0
20/24
0 0
0
1
21/29
1
0 0
0
0
24/32
3
13
3
12
2
near_label
0
shorUabel
0
0
3
regptr
1 1
0 0
reg
11
2
memptr16
mod
0 0
mem
20/24
2-4
15
5
mod
0
mem
27/35
2-4
14/4
2
14/4
2
14/4
2
2
far_label
0
0
memptr32
BV
BNV
BC,BL
BNC,BNL
BE, BZ
BNE, BNZ
BNH
BH
BN
BP
BPE
BPO
BLT
BGE
1 1 0
1
shorUabel
0
0
shorUabel
0
0
shorUabel
0
0
shorUabel
0
0 0
14/4
shorUabel
0
0
14/4
2
shorUabel
0
0
14/4
2
0
0
short_label
0
0
14/4
2
shorUabel
0
0 1 1
14/4
2
0 0 0
14/4
2
0 1
14/4
2
0
14/4
2
shorUabel
1
14/4
2
shorUabel
0 0
14/4
2
shorUabel
0
14/4
2
shorUabel
0
shorUabel
0
shorUabel
0
':21
NEe
pPD70108 (V20)
Instruction Set (cont)
Mnemonic
Operand
Opcode
0
7 654321 0
6 5 4 3 2
Clocks
Bytes
Flags
AC CY V P S,Z
Control Transfer Instructions (cont)
BLE
shorUabel
0
BGT
shorUabel
0
14/4
2
1 1 1
14/4
2
0
DBNZNE
shorUabel
0 0 0 0 0
14/5
DBNZE
shorUabel
0 0 0 0 1
14/5
2
DBNZ
shorUabel
0 0 0
13/5
2
BCWZ
shorUabel
0 0 0
13/5
2
0
Interrupt Instructions
BRK
3
0 0
0 0
imm8
0 0
0 1
0 0
0
BRKV
RETI
1
reg16, mem32
0
BRKEM
imm8
0 0 0 0
38/50
2
52/3
1
0 0
CHKIND
38/50
R R R R R R
27/39
0 0 0
0
mod
reg
mem
1 1 1 1 1 1 1 1
18/26
73-76
2-4
38/50
3
CPU Control Instructions
HALT
0 1 0 0
BUSLOCK
FP01
FP02
fp_op
1
0 0 0 0
0
X X X
2
2
1 1 Y Y Y Z Z Z
2
mod Y y y
11/15
2-4
2
fp_op, mem
1
0 1 1 X X X
fp_op
0
1 0 0
X
1 1 Y y y Z Z Z
2
2
1 1 0 0
X
mod y y y
11/15
2-4
fp_op, mem
mem
mem
POLL
0 0
1 o 1 1
n = number of times POLL pin is sampled.
2+5n
NOP
0 0
0 0 0 0
3
DI
0
EI
0
0
2
2
8080 Instruction Set Enhancements
RETEM
CALLN
imm8
1
0
0
1
0
27/39
2
1
0
0
0
0
38/58
3
R R R R R R
NEe
NEe Electronics Inc.
pPD70ii6 (V30), 70ii6H (V30H)
i6·Bil Microprocessor:
High·Performance, CMOS
Description
Ordering Information
ThepPD70116 (V30®) is a CMOS 16-bit microprocessor
with an internal 16-bit architecture and a 16-bit external
data bus. The pPD70116 instruction set is a superset of
thepPD8086/8088; however, mnemonics and execution
times are different. The pPD70116 additionally has a
powerful instruction set including bit processing,
packed BCD operations, and high-speed multiplication/division operations. The pPD70116 can also
execute the entire 8080 instruction set and comes'with
a standby mode that significantly reduces power
consumption. It is software-compatible with the
pPD70108 microprocessor.
Part
Number
Max Frequency
of Operation
Package Type
8 MHz
40-pin plastic DIP
Standard Series
jiPD70116C8
C10
10 MHz
L8
8 MHz
L10
10 MHz
GC8
8 MHz
GC10
10 MHz
jiPD70116HC10
10 MHz
HC12
12 MHz
HC16
16 MHz
Features
HL 10
10 MHz
o
HL 12
12 MHz
The H-series microprocessors are fully static devices
that offer operating frequencies to 16 MHz, lower
power consumption, and no restriction on minimum
clock frequency from dc to 16 MHz.
Minimum instruction execution time:
250 ns at 8 MHz, 200 ns at 10 MHz, 125 ns at 16 MHz
o Maximum addressable memory: 1 Mbyte
D Abundant memory addressing modes
o 14 x 16-bit register set
o 101 instructions
o Instruction set is a superset of pPD8086/8088
instruction set
o Bit, byte, word, and block operations
OBit fielq operation instructions
o Packed BCD instructions
o Multiplication/division instruction execution
time: 2.4 t07.1psat8MHz, 1.9 t05.7psat10MHz
o High-speed block transfer instructions:
1 Mbyte/s at 8 MHz, 1.25 Mbyte/s at 10 MHz
o High-speed calculation of effective addresses:
2 clock cycles in any addressing mode
o Maskable (INT) and nonmaskable (NMI)
interrupt inputs
o IEEE-796 bus compatible interface
o 8080 emulation mode
o CMOS technology
o Low power consumption
o Low-power standby mode
o Minimum-power Stop mode (H-Series)
o Single power supply; 5-V and 3-V specifications
D Maximum operating frequencies: 8 to 16 MHz
V30 is a registered trademark of NEC Corporation.
44-pin PLCC
52-pin plastic QFP
(P52GC-100-386)
H-Series
HL 16
16 MHz
HGC10
10 MHz
HGC12
12 MHz
HGC16
16 MHz
40-pin plastic DIP
44-pin PLCC
52-pin plastic QFP
(P52GC-100-386)
Pin Configurations
40-Pin Plastic DIP
IC
VDD
AD14
A D 15
AD13
A16/PSO
AD12
A17/PS1
AD11
A1a/PS2
AD10
A19/PS3
UBE
AD9
ADa
33
S/LG
31
HlDRO [RO/AKol
RD
AD7
AD6
10
tLPD
70116
ADs
11
AD4
12
ADa
13
jQ/M [BS2l
AD2
14
BUFR/W [BS1l
HlDAK [RO/AK1l
WR [BUSlOCKl
AD1
15
BUFEN [BSol
ADo
16
ASTB [OSol
NMI
17
INTAK [OS1l
INT
18
POll
ClK
19
READY
GND
20
RESET
83-004104B
50029-2 (NECEL-062)
NEe
pPD70116 (V30)
Pin Configurations (cont)
Pin Identification
Symbol
44-Pin Plastic Leaded Chip Carrier (PLCC)
Internally connected
AD14 - ADo
..,en .., .., .., .., .., ..,.., ..,
a:I
,...
CD
II)
'
2.2V
~
;:)
0l~ '"
0
0
%: %:
w oo 0 w w i
a: > > a: a: z
CD
I'-
I'-
II)
I'-
I/j
""
M
I'-
N
I'-
;::::
0
I'-
en
CD
:gN :g.- :g0l~:E
:g t; :g
II)
CD
64
lORD
63
NC
A15
62
MWR
A14
61
IOWR
A13
60
BUSLOCK
A16/PSo
0
NC
A12
59
BUFR/W
All
58
BUFEN
Al0
57
CLKOUT
A9
56
Xl
X2
AS
10
55
GND
11
54
GND
NC
12
53
NC
GND
13
52
GND
AD7
14
51
[High]
AD6
15
50
ASTB
ADS
16
49
QSo
AD4
17
48
QS1
AD3
18
47
POLL
AD2
19
46
TCTL2
tiP D70208GF
AD1
20
45
TOUT2
ADD
21
44
TCLK
NC
22
43
NC
NC
23
42
INTP7
END/TC
24
41
INTP6
II)
CD
N
~ ~ ~ ~ M
o
~
o
N
°1°
PI
Q
Q
>C
>C
~ ~ ~ ~
UI>a:
TTT
~
o
~
a: ~
c( '"
c( a:
c( '"
c( a: '"
a:
'"
c( :E
:E :E :E :E :E
o ~
Q Q Q Q Q Q
a: '"
'"
:E c(
:E
Q
Q
-
Q
~
;:
;:)
r;;
~ ~
0
""
II)
o .- N M
00.. 0.. 0.. 0.. 0..
> ~ ~ ~ ~ ~
""
~ ~ ~ ~ ~
0
!:::
I~
83-0041808
3
NEe
Pin Identification
Symbol
Symbol
Function
Function
INTP1-INTP7
Interrupt request inputs
A19-A16/PS3-PSO
Multiplexed address/processor status outputs
lORD
I/O read strobe output
A15- AS
Address bus outputs
10WR
I/O write strobe output
AD7-ADo
Multiplexed address/data bus
MRD
Memory read strobe output
ASTB
Address strobe output
MWR
Memory write strobe output
BS2-BSO
Bus status outputs
NC
No connection
BUFEN
Data bus transceiver enable output
NMI
Nonmaskable interrupt input
BUFR/W
Data bus transceiver direction output
POLL
Poll input
BUS LOCK
Buslock output
QS1-QSO
CPU queue status outputs
CLKOUT
System clock output
READY
Ready input
DMAAKO
DMA channel 0 acknowledge output
REFRQ
Refresh request output
DMAAK1
DMA channel 1 acknowledge output
RESET
Reset input
DMAAK2
DMA channel 2 acknowledge output
RESOUT
Synchronized reset output
DMAAK3/TxD
DMA channel 3 acknowledge output/Serial
transmit data output
TCLK
Timer / counter external clock input
TCTL2
Timer/counter 2 control input
TOUT2
Timer / counter 2 output
Voo
+5 V power supply input
X1,X2
Crystal/external clock inputs
DMARQO
DMA channel 0 request input
DMARQ1
DMA channel 1 request input
DMARQ2
DMA channel 2 request input
DMARQ3/RxD
DMA channel 3 request input/Serial receive
data input
END/TC
End input/Terminal count output
GND
Ground
High
High-level output except during hold
acknowledge when it is placed in the
high-impedance state
HLDAK
Hold acknowledge output
HLDRQ
Hold request input
IC
Internal connection; leave unconnected
INTAKITOUT1/SRDY
Interrupt acknowledge output/Timer/counter 1
output/Serial ready output
4
NEe
pPD70208 (V40)
Pin Functions
AD7-ADo [Address/Data Bus]
A19-A16/PS3-PSO [Address/Status Bus]
These three-state pins form the active-high, time-mUltiplexed address/data bus. During T1 of a bus cycle,
ADrADo output the lower 8 bits of the 20-bit memory
or I/O address. During the T2, T3, TW, and T4 states,
ADj-ADo form the 8-bit bidirectional data bus.
These three-state output pins contain the upper 4 bits
of the 20-bit address during T1 and processor status
information during the T2, T3, TW, and T 4 states of a bus
cycle. Du ring T1 of a memory read or write cycle, these
pins contain the upper 4 bits of the 20-bit address.
These pins are forced low during T1 of an I/O bus
cycle.
Processorstatus is output during T2, T3, TW, and T4 of
both memory and I/O bus cycles. PS3 is zero during
any CPU native mode bus cycle. During any DMA,
refresh, or 8080 emulation mode bus cycle, PS 3 outputs
a high level. PS2 outputs the contents of the interrupt
enable (IE) flag in the CPU PSW register. PS1 and PSo
indicate the segment register used to form the physical
address of a CPU bus cycle as follows:
PSI
PSo
Segment
0
0
0
1
Data segment 1 (DS1)
Stack segment (SS)
0
1
Program segment (PS)
Data segment 0 (DSO)
These pins are in the high-impedance state during hold
acknowledge.
A1s-Aa [Address Bus]
These three-state pins form the middle byte of the
active-high address bus. During any CPU, DMA, or
refresh bus cycle, A1s-Aa output the middle 8 bits of the
20-bit memory or 110 address. The A1s-Aa pins enter
the high-impedance state during hold acknowledge or
an internal interrupt acknowledge bus cycle. During a
slave interrupt acknowledge bus cycle, A1O-Aa contain
the address of the selected slave interrupt controller.
The ADrADo pins enter the high-impedance state
during hold acknowledge or internal interrupt acknowledge bus cycles or while RESET is asserted.
ASTB [Address Strobe]
This active-high output is used to latch the address
from the multiplexed address bus in an external address
latch during T1 of a bus cycle. ASTB is held at a low
level during hold acknowledge.
BS2-BSO [Bus Status]
Outputs BS2-BSO indicate the type of bus cycle being
performed as follows. BS2-BSO become active during
the state preceding T1 and return to the passive state
during the bus state preceding T4.
Bus Cycle
BS2
BSI
BSo
0
0
0
0
0
0
0
1
1
o.
1
I/O write
Halt (Note 1)
0
0
1
Instruction fetch
Memory read (Note 2)
0
1
Memory write (Note 3)
Passive state
0
1
Interrupt acknowledge
I/O read
Note:
(1) BS2-BSO in a halt bus cycle returns tothe passive state oneclock
earlier than normal CPU bus cycles.
(2) Memory read bus cycles include CPU, DMA read, DMA verify,
and refresh bus cycles.
(3) Memory write bus cycles include C!='U and DMA write bus cycles.
BS2-BSO are three-state outputs and are high impedance during hold acknowledge.
5
1:'-11
I:i:a
NEe
pPD70208 (V40)
BUFEN [Buffer Enable]
BUFEN is an active-low output for enabling an external
data bus transceiver during a bus cycle. BUFEN is
asserted during T2 through T3 of a read cycle, T2
through T3 of a slave interrupt acknowledge cycle, and
T1 through T4 of a write cycle. BUFEN is not asserted
when the bus cycle corresponds to an internal peripheral, DMA, refresh, or internal interrupt acknowledge cycle. BUFEN enters the high-impedance state
during hold acknowledge.
DMAAK3/TxD [DMA Acknowledge 3]/[Serial
Transmit Data]
Two output signals multiplexed on this pin are selected
by the PF field of the on-chip peripheral connection
register.
• DMAAK3 is an active-low output and enables an
external DMA peripheral to perform the requested
DMA transfer for channel 3.
• TxD is the serial data output from the serial control
unit.
BUFR/W [Buffer Read/Write]
BUFR/W is a three-state, active-low output used to
control the direction of an external data bus transceiver during CPU bus cycles. A high level indicates
thepPD70208wili perform a write cycle and a low level
indicates a read cycle. BUFR/W enters the highimpedance state during hold acknowledge.
BUSLOCK
This active-low output provides a means for the CPU to
indicate to an external bus arbiter that the bus cycles of
the next instruction are to be kept contiguous.
BUSLOCK is asserted for the duration of the instruction
following the BUSLOCK prefix. BUSLOCK is also
asserted during interrupt acknowledge cycles and
enters the high-impedance state during hold acknowledge. While BUSLOCK is asserted, DMAL:J, RCU, and
external bus requests are ignored.
CLKOUT
CLKOUT is a buffered clock output used as a reference
for all timing. CLKOUT has a 50-percent duty cycle at
half the frequency of the input clock source.
DMAAKO-DMAAK2 [DMA Acknowledge]
This set of outputs contains the DMA acknowledge
signals for channels 0-2 from the internal DMA controller and indicate that the peripheral can perform the
requested transfer.
6
DMARQO-OMARQ2 [DMA Request]
These synchronized inputs are used by external peripherals to request DMA service for channels 0-2 from
the internal DMA controller.
DMARQ3/RxD [DMA Request 3]1[Serial Receive
Data]
Two input signals multiplexed on this pin are selected
by the PF field of the on-chip peripheral connection
register.
• DMARQ3 is used by an external peripheral to request
a DMA transfer cycle for channel 3.
• RxD is the serial data input to the serial control unit.
EN D/TC [End/Terminal Count]
This active-low bidirectional pin controls the termination of a DMA service. Assertion of END by external
hardware during DMA service causes the service to
terminate. When a DMA channel reaches its terminal
count, the DMAU asserts TC, indicating the programmed operation has completed.
END/TC is an open-drain 1/0 pin, and requires an
external 2.2-kO pull-up resistor.
NEe
pPD70208 (V40)
HLDAK [Hold Acknowledge]
INTP1-INTP7 [Peripheral Interrupts]
When an external bus requester has become the
highest priority requester, the internal bus arbiter will
assert the HLDAK output indicating the address, data,
and control buses have entered a high-impedance state
and are available for use by the external bus master.
INTP1-INTP7 accept either rising-edge or high-level
triggeredasyochronousinterrupt requests from external
peripherals. These INTP1-INTP7 inputs are internally
synchronized and prioritized by the interrupt control
unit, which requests the CPU to perform an interrupt
acknowledge bus cycle. External interrupt controllers
such as the JlPD71059 can be cascaded to increase the
number of vectored interrupts.
Should the internal DMAU or RCU (demand mode)
request the bus, the bus arbiter will drive HLDAK low.
When this occurs, the external bus master should
complete the current bus cycle and negate the HLDRQ
signal. This allows the bus arbiter to reassign the bus to
the higher priority requester.
If a higher priority internal bus master subsequently
requests the bus, the high-level width of HLDAK is
guaranteed to be a minimum of one CLKOUT period.
These interrupt inputs cause the CPU to exit both the
standby and 8080 emulation modes.
The INTP1-INTP7 inputs contain internal pull-up
resistors and may be left unconnected.
lORD [1/0 Read]
This active-high signal is assert~d by an external bus
master requesting to use the local address, data, and
control buses. The HLDRQ input is used by the internal
bus arbiter, which gives control of the buses to the
highest priority bus requester in the following order.
This three-state pin outputs an active-low I/O read
strobe during T2, T3, and TW of an I/O read bus cycle.
Both CPU I/O read and DMA write bus cycles assert
lORD. lORD is not asserted when the bus cycle
corresponds to an internal peripheral or register. It
enters the high-impedance state during hold acknowledge.
Bus Master
10WR [1/0 Write]
HLDRQ [Hold Request]
RCU
DMAU
HLDRQ
CPU
RCU
Priority
Highest (demand mode)
•
•
•
Lowest (normal operation)
INTAK/TOUT1/SRDY [Interrupt Acknowledge]1
[Timer 1 Output]/[Serial Ready]
This three-state pin outputs an active-low I/O write
strobe during T2, T3, and TW of a CPU I/O write or an
extended DMA read cycle and during T3 and TW of a
DMA read bus cycle. 10WR is not asserted when the
bus cycle corresponds to an internal peripheral or
register. It enters the high-impedance state during
hold acknowledge.
Three output signals multiplexed on this pin are
selected by the PFfield of the on-chip peripheral
connection register.
• INTAK is an interrupt acknowledge signal used to
cascade external slave JlPD71059 I nterrupt Controllers. I NTAK is asserted during T2, T3, and TW states
of an interrupt acknowledge cycle.
• TOUT1 is the output of timer/counter 1.
• SRDY is an active-low output and indicates that the
serial control unit is ready to receive the next
character.
7
I:R
m:I
NEe
pPD'70208 (V40)
MRD [Memory Read Strobe]
READY [Ready]
This three-state pin outputs an active-low memory
read strobe during T2, T3, and TW 01a memory read
bus cycle. CPU memory read, DMA read, and refresh
bus cycles all assert MRD. MRD enters the highimpedance 'state during hold acknowledge.
This active-high input synchronizes external memory
and peripheral devices with the pPD70208. Slow
memory and I/O devices can lengthen a bus cycle by
negating the READY input and forcing the BIU to insert
TW states. READY must be negated prior to the rising
edge of CLKOUT during the T2 state or by the last
internally generated TW state to guarantee recognition.
When READY is, once again asserted and recognized
by the BIU, the Biu will proceed to the T4 state.
MWR [Memory Write Strobe]
This three-state pin outputs an active-low memory
write strobe during T2, T3, and TW of aCPU memory
write or DMA extended write bus cycle and during T3
and TW of a DMA normal write bus cycle. MWR enters
the high-impedance state during hold acknowledge.
The READY input operates in parallel with the internal
pPD70208 wait control unit and can be used to insert
more than three wait states into a bus cycle.
NMI [Nonmaskable Interrupt]
REFRQ [Refresh Request]
The NMI pin is a rising-edge-triggered interrupt input
that cannot be masked by software. NMI is sampled by
CPU logic each clock cycle and when fOund valid for
one or more CLKOUT cycles, the NMI interrupt is
accepted. The CPU will process the NMI interrupt
immediately after the current instruction finishes
execution by fetching the segment and offset of the
NMI handler from interrupt vector 2. The NMI interrupt
causes the CPU to exit both the standby and 8080,
emulation modes. The NMI input takes precedence
over the maskable interrupt inputs.
REFRQ is an active-low output indicating the current
bus cycle is a memory refresh operation. REFRQ is
used to disable memory address decode logic and
refresh dynamic memories. The 9-bit refresh row
address is placed on As-Ao during a refresh bus cycle.
POLLIPolI]
The active-low POLL input is used to synchronize the
operation of external devices with the CPU. During
execution of the POLL instruction, the CPU checks the
POLL input state every five clocks until POLL is once
again asserted.
QS1-QSO [Queue Status]
The QS1 and QSo outputs maintain instruction synchronization between thepPD70208 CPU and external
devices. These outputs are interpreted as follows.
QSo
o
o
o
Instruction Queue Status
No operation
RESET is a Schmitt trigger input used to force the
pPD70208 to a known state by resetting the CPU and
on-chip peripherals. RESET must be asserted for a
minimum offourclocks to guarantee recognition. After
RESET has been released, the CPU will start program
execution from address FFFFOH in the native mode.
RESET will release the CPU from the low-power
standby mode and force it to the native mode.
RESOUT [Reset Output]
This active..,high output is available to perform a systemwide reset function. RESET is internally synchronized
with CLKOUT and output on the RESOUT pin.
TCLK
TCLK is an external clock source for the timer control
unit. The three timer/counters can be programmed to
operate with either the TCLK input or a prescaled
CLKOUT input.
First byte of instruction fetched
o
Flush queue contents
TCTL2
Subsequent byte of instruction fetched
TCTL2 is the control input for timer/counter 2.
Queue status is valid for one clock cycle after the CPU
has accessed the instruction queue.
8
RESET [Reset]
TOUT2
TOUT2 is the output of timer/counter 2.
NEe
pPD70208 (V40)
Xl, X2 [Clock Inputs]
Table 1.
These pins accept either a p'arallel resonant, fundamental mode crystal or an external oscillator input with
a frequency twice the desired operating frequency.
Symbol
In the case of an external clock generator, the X2 pin
can be either left unconnected or be driven by the
complement of the X1 pin clock source.
Pin States
Table 1 lists the output pin states during the Hold, Halt,
Reset, and DMA Cascade conditions.
Input/Output Pin States
DMA
Pin Type
Hold
Halt
Reset Cascade
A19-A16/PS3-PSO.
A15- Aa
3-state Out
Hi-Z
H/L
H/L
Hi-Z
AD7-ADo
Hi-Z
3-state 1/0
Hi-Z
H/L
Hi-Z
ASTB
Out
L
L
L
L
, BUFEN
3-state Out
Hi-Z
H
H
Hi-Z
BUFR/W
3-state Out
Hi-Z
H/L
H
Hi-Z
BUS LOCK
3-state Out
Hi-Z
HIL
H
Hi-Z
BS2-BSO
3-state Out
Hi-Z
H
H
H
CLKOUT
Out
H/L
H/L
H/L
H/L
DMAAKO-DMAAK2
Out
H
H/L
H
H/L
DMAAK3
Out
H
H/L
H
H/L
H/L
H/L
END/TC
I/O
H/L
H
H/L
H
H
HLDAK
Out
H
H/L
L
L
INTAK
Out
H
H
H
H
TOUT1
H/L
H/L
SRDY
H/L
H/L
H
TxD
H/L
H/L
lORD
3-state Out
Hi-Z
10WR
3-state Out
Hi-Z
H
H
Hi-Z
MRD
3-state Out
Hi-Z
H
H
Hi-Z
MWR
H
Hi-Z
3-state Out
Hi-Z
H
H
Hi-Z
QS1-QSO
Out
H/L
L
L
H/L
REFRQ
Out
H
H/L
H
H
,RESOUT
Out
L
H
L
TOUT2
Out
H/L
H/L
H/L
H/L
H: high level; L: low level; H/L: high or low level; Hi-Z: high
impedance.
II
NEe
pPD70208(V40)
Block Diagram
INTP1
~
INTP2
INTP3
INTP4
INTP5
~
Interrupt
Control
Unit
[ICU]
~ A19-A1slPS3-PSO
Wait
Control
Unit
[WCU]
~A15-A8 ,
~Ab7-ADO
F===>
INTP6
INTP7
BS2-BSo
QS1
QSo
TOUT2
~
Timer/
Counter
Unit
[TCU]
TOUT1
TCTL2
TCLK
POLL
Bus
Interface
Unit
[BIU]
ASTB
BUFEN
BUFR/W
BUSLOCK
DMARQO
DMAAKO
DMARQ1
DMAAK1DMARQ2
DMAAK2
DMA
Control
Unit
[DMAU]
Central
Processing
Unit
[CPU]
lORD
IOWR
MRD
MWR
READY
RESET
DMARQ3
~
RESOUT
DMAAK3
END/TC
Bus
Arbitration
Unit
[BAU]
iNTAK
NMI
X1
X2
CLKOUT
Clock
Generator
[CG]
Refresh
Control
Unit
[RCU]
-
Serial
Control
Unit
[SCU]
f----
HLDAK
HLDRQ
TxD
SRDY
RxD
REFRQ
83-004137C
NEe
pPD70208 (V40)
Absolute Maximum Ratings
DC Characteristics
TA =+25°C
TA = -10 to +lO°C, VDD = +5 V ±10% (8 MHz),
VDD = 5 V ±5% (10 MHz)
Power supply voltage, Voo
-0.5 to +7.0 V
Input voltage, VI
Limits
-0.5 to Voo + 0.3 V
ClK input voltage, VK
-0.5 to Voo + 1.0 V
Output voltage, Vo
-0.5 to Voo + 0.3 V
Operating temperature, TOPT
Storage temperature, TSTG
-65 to +150 °C
Comment: Exposure to Absolute Maximum Ratings for extended
periods may affect device reliability; exceeding the ratings could
cause permanent damage. The device should be operated within the
limits specified under DC and AC Characteristics.
Parameter
Test
Conditions
Symbol
Min
Max
Unit
Input voltage, high
VIH
2.2
VOD +
0.3
V
Input voltage, low
Vil
-0.5
O.B
V
X1, X2 input
voltage, high
VKH
3.9
VOD +
1.0
V
X1, X2 input
voltage, low
VKl
-0.5
0.6
V
V
IOH = -400pA
V
IOl =2.5 mA
Output voltage, high VOH
0.7 Voo
Capacitance
Output voltage, low
VOL
0.4
TA=+25°C, VDD=OV
Input leakage
current, high
ILiH
10
pA
VI = VOO
Input leakage
current, low
ILlPl
-300
pA
VI = 0 V, INTP
input pins
ILil
-10
pA
VI = 0 V, other
input pins
Output leakage
current, high
IlOH
10
pA
Vo = Voo
Output leakage
current, low
IlOl
-10
pA
Vo=OV
Supply current
8 MHz
100
90
20
mA
mA
Normal mode
Standby mode
10 MHz
100
120
25
mA
mA
Normal mode
Standby mode
limits
Parameter
Symbol
Min
Max
Input capacitance
CI
15
Output capacitance
Co
15
Unit
Test
Conditions
pF fc = 1 MHz;
unmeasured pins
pF
are returned to 0 V.
11
D
NEe
pPD70208 (V40)
AC Characteristics
TA = -10 to +70°C; Voo
= 5 V ±10% (8 MHz), Voo = 5 V ±5% (10 MHz), CL = 100 pF
10 MHz Limits
8 MHz Limits
Symbol
Min
Max
Min
Max
Unit
External clock input cycle time
tCYX
62
250
50
250
ns
External clock pulse width, high
tXXH
20
19
ns
VKH
External clock pulse width, low
tXXL
20
19
ns
VKL = 1.5 V
External clock rise time
tXR
10
5
ns
1.5- 3.0V
External clock fall time
tXF
10
5
ns
3.0 -1.5V
CLKOUT cycle time
tCYK
124
500
ns
CLKOUT pulse width, high
tKKH
0.5 tCYK-7
0.5 tCYK - 5
ns
VKH
CLKOUT pulse width, low
tKKL
0.5 tCYK'-- 7
0.5 tCYK - 5
ns
VKL = 1.5 V
CLKOUT rise time
tKR
7
5
ns
1.5 - 3.0 V
CLKOUT fall time
tKF
7
5
ns
3.0-1.5 V
CLKOUT delay time from external clock
tOXK
55
40
ns
Input rise time (except external clock)
tlR
20
15
ns
0.8 - 2.2 V
Input fall time (except external clock)
tlF
12
10
ns
2.2 - 0.8 V
Output rise time (except CLKOUT)
tOR
20
15
ns
0.8 - 2.2 V
tOF
12
10
ns
2.2 -
Parameter
Output fall time (except CLKOUT)
RESET setup time to CLKOUT!
tSRESK
25
RESET hold time after CLKOUT!
tHKRES
35
tOKRES
5
RESOUT delay time from CLKOUT!
READY inactive setup time to CLKOUTl
tSRYLK
READY inactive hold time after CLKOUTl
READY active setup time to CLKOUTl
500
100
20
5
ns
tHKRYL
25
20
ns
tSRYHK
15
15
ns
READY active hold time after CLKOUTl
tHKRYH
25
20
ns
NMI, POLL setup time to CLKOUTl
tSIK
15
15
ns
Data setup time to CLKOUT!
tSOK
15
15
ns
Data hold time after CLKOUT!
tHKO
10
10
Address delay time from CLKOUT!
tDKA
10
Address hold time after CLKOUT!
tHKA
10
1/0 recovery time
tAl
PS delay time from CLKOUT!
tOKP
60
60
PS float delay time from CLKOUTt
tFKP
10
tSAST
tKKL - 20
Address float delay time from CLKOUT!
tFKA
tHKA
ns
10
50
ns
10
50
ns
tHKA
A19-AO UBE
(Note 1)
ns
tKKL - 30
60
ns
ns
2tCYK - 40
10
Address setup time to ASTB!
ns
50
10
2tCYK - 50
0.8 V
ns
15
10
= 3.0 V
ns
50
15
55
= 3.0 V
ns
25
60
Test Conditions
50
ns
40
ns
45
ns
ASTBl delay time from CLKOUT!
tOKSTH
45
ASTB! delay time from CLKOUTl
tOKSTL
50
ASTB pulse width, high
tSTST
tKKL -10
Address hold time after ASTB!
tHSTA
tKKH - 20
tOKCT1
10
70
10
60
ns
(Note 2)
tOKCT2
10
60
10
55
ns
(Note 3)
Control delay time from CLKOUT
19
ns
tKKL - 10
ns
tKKH - 20
NEe
pPD70208 (V40)
AC Characteristics (cont)
8 MHz Limits
10 MHz Limits
Parameter
Symbol
Min
Max
RD! delay time from address float
tOAFRL
0
RD! delay time from CLKOUT!
tOKRL
10
75
ROt delay time from CLKOUT!
tOKRH
10
70
REFROt delay from MROt
tORQHRH tKKL - 30
Min
Max
Unit
ns
0
10
65
ns
10
60
ns
tKKL - 30
ns
Test Conditions
(Note 4)
(Note 5)
Address delay time from ROt
tORHA
tCYK - 40
tCYK - 40
ns
RD pulse width, low
tRR
2tCYK - 50
2tCYK - 40
ns
BUFR/W delay from BUFENt
tOBECT
tKKL - 20
tKKL - 20
ns
Read cycle
tOWCT
tKKL - 20
ns
Write cycle
Data output delay time from CLKOUT!
tOKO
tKKL - 20
10
60
60
Data float delay time from CLKOUT!
tFKO
10
WR pulse width, low
tww
2tCYK - 40
BS! delay time from CLKOUTt
tOKBL
10
60
60
10
55
ns
10
55
ns
ns
2tCYK - 40
10
55
ns
10
55
ns
(Note 4)
BS t delay time from CLKOUT!
tOKBH
10
HLDRO setup time to CLKOUTt
tSHQK
20
HLDAK delay time from CLKOUT!
tOKHA
10
70
10
60
ns
DMAAK! delay time from CLKOUTt
tOKHOA
10
60
10
55
ns
DMAAK! delay time from CLKOUT!
tOKLOA
10
90
10
80
ns
Cascade mode
WR pulse width, low (OMA cycle)
tWW1
2tCYK - 40
2tCYK - 40
ns
DMA extended
write cycle
WR pulse width, low (DMA cycle)
tWW2
tCYK - 40
tCYK - 40
ns
DMA normal
write cycle
RD!, WR! delay from DMAAK!
tOOARW
tKKH - 30
tKKH - 30
ns
DMAAKt delay from Rot
tORHOAH
tKKL- 30
tKKL- 30
ns
tOWHRH
5
5
ROt delay from WRt
15
TC output delay time from CLKOUTt
tOKTCL
60
TC off delay time from CLKOUTt
tOKTCF
60
TC pulse width, low
tTCTCL
TC pullup delay time from CLKOUTt
tOKTCH
tCYK -15
ns
ns
55
ns
55
ns
ns
tCYK -15
tKKH
+ tCYK -10
tKKH
+ tCYK -10
ns
END setup time to CLKOUTt
tSEOK
35
30
ns
END pulse width, low
tEOEOL
100
80
ns
DMARO setup time to CLKOUTt
tSOQK
35
30
ns
INTPn pulse width, low
tlPIPL
100
80
ns
RxD setup time to SCU internal clock!
tSRX
0.5
p's
RxD hold time after SCU internal clock!
tHRX
SRDY delay time from CLKOUT!
tOKSR
0.5
150
p's
100
ns
Notes:
(1) This is specified to guarantee a read/write recovery time for I/O
devices.
(2) Delay from CLKOUT to DMA cycle MWR/IOWR outputs.
(4) RD represents lORD and MRD. WRrepresents 10WR and MWR.
(5) This is specified to guarantee that REFRQ
MRD t at all times.
t is delayed from
(3) Delay from CLKOUT to BUFR/W, BUFEN, INTAK, REFRQ outputs and CPU cycle MWR/IOWR outputs.
1'l
NEe
pPD70208 (V40)
AC Characteristics (cont)
8 MHz limits
Parameter
Symbol
TxD delay time from TOUT1!
tOTX
Min
Max
10 MHz limits
Min
500
Max
Unit
200
ns
ns
TCTL2 setup time from CLKOUT!
tSGK
50
40
TCTL2 setup time to TCLKt
tSGTK
50
40
ns
TCTL2 hold time after CLKOUT!
tHKG
100
80
ns
TCTL2 hold time after TCLKt
tHTKG
50
40
ns
tGGH
50
40
ns
tGGL
50
40
TCTL2 pulse width, high
TCTL2 pulse width, low
TOUT output delay time from CLKOUT!
TOUT output delay time from TOUT!
ns
tOKTO
200
150
100
ns
ns
tOTKTO
150
TOUT output delay time from TCTL2!
tOGTO
120
90
ns
TCLK rise time
tTKR
25
25
ns
TCLK fall time
tTKF
25
ns
TCLK pulse width, high
tTKTKH
50
45
TCLK pulse width, low
tTKTKL
50
45
TCLK cycle time
tCYTK
124
RESET pulse width low
tRESET1
50
50
tRESET2
4 tCYK
4 tCYK
14
25
DC
100
Test Conditions
ns
ns
DC
ns
ps
After power on
During operation
NEe
pPD70208 (V40)
Clock Input Configurations
Timing Measurement Points
Crystal-Controlled Internal Clock
II
t~
1SpF
II
II
~
T
X1
4V
Input
[except Clock] 2.
X2
Output
0.4 V
=X
2.2 V
2.2 V
x=
..:0:;::.8..:V_ _ _ _ _ _:::O.8::....:...V•
~ 2.2 V
2.2 V
tr--
~..:0:;::.8~V~________:::0.8::....:...V~
External Clock 1
ClK
----t>o
d::
S3-001S16A
I
External Clock 2
ClK
Buffers are high-speed
CMOS inverters.
1~:
I
S3-00401SA
Timing Waveforms
Clock Timing
External
Clock
[Xl]
ClKOUT
83-0018448
NEe
pPD70208 (V40.)
Timing Waveforms (cont)
Reset and Ready Timing
Reset Timing
CLKOUT
~'""~,--.
-----
RESOUT
Ready Timing, No Wait States
11
T2
T3
T4
11
11
. T2
T3
TW
T4
CLKOUT
READY
Ready Timing, Wait States
CLKOUT
READY
83-002725B
16
N'EC
pPD70208 (V40)
Timing Waveforms (cont)
Poll, NMI, and Buslock Timing
CLKOUT
POLL, NMI Input Timing
POLL, NMI
_f_'S'K
CLKOUT
BUSLOCK Output Timing
83-0018318
Read/Write Recovery Time
'AI~l
•~-IA-I---_-JI
I+--_IAI_--+l}--83-0042668
NEe
pPD70208 (V40)
Timing Waveforms (cont)
Read Timing
T2
T1
T4
T3/TW
T4
CLKOUT
Processor Status
II
~
1_-----"'"
-tFKA
AD7-ADO -+---+~
tSOK~1
Data Input
tHKO
ASTB-+----
[Note 1]
tOKCT2
tOKCT2
I
MRD
lORD
[Note 1]
1+-------+-tRR -----~
tOKBL
tOKBH
Note:
[1] Except internal 110 accesses.
83-001848B
NEe
pPD70208 (V40)
Timing Waveforms (cont)
Write Timing
T4
T1
T2
T3/TW
T4
CLKOUT
A19/ PSaA1s1PSo _ _ _ _J
BUFR/W
MWR~
__________________
tOKCT2
tOKCT2
~-+
10WR
[Note 1]
~----------tww----------~
I
BS2-BSo~--~----------~----------~--~-------------------------
tOKBL
tOKBH
Note:
[1] Except internal I/O accesses.
83-0018468
NEe
pPD70208 (V40)
Timing Waveforms (cont)
Status Timing
T4
T2
T1
T4
T3/TW
CLKOUT
A19 /PS 3
-A16/ PS o _ _ _ _J
Processor Status
tSOK-j
AD7-ADO .....----1....(1
Address
I
Data Input
ASTB
tOKBH
Bus Status
tOKRH
f
QS1.QSO~~~~~-_-_-_-
tRR
.1
---------)('----------~)('----------~)(~___________ ~
83-002724 B
NEe
pPD70208 (V40)
Timing Waveforms (cont)
Interrupt Acknowledge Timing
T2
T1
T3
T4
T2
T1
T3
T1
CLKOUT
ASTB
tOKCT2
tOKCT2
-L~------------~--------[Note 2)
BUF~W
__---
_ _ _ _ _~_____________________________________________________________
-f·~
BUSLOCK
_
/
Note:
[1J Slave address when the Interrupt Is from external pP071059. Undefined when InternallCU
interrupt.
[2J Solid line when Interrupt from external pP071059. Dash line when InternallCU interrupt.
83-0018408
21
NEe
pPD70208 (V40)
Timing Waveforms (coni)
HLDRQ/HLDAK Timing, Normal Operation
I
I
T2
I
--I
TI
I
TI
T4
TI
~
~----+----+---+---
CLKOUT~
~tsHaK
1
HLDRa~
-tOKHA
HLDAK
--[tOKA
[NOTEI[
Internal Bus
Maste~,:',
---.'~
_____
[NOTE2J
.. '-._ _ _ _
(ii-I
--In-t-er-n-al-B-u-S-M""~ster
L . "-----------------+------(1
---'~r
tFKA
....
Internal
Bus Master
-~tOKA
t-------~)~t'-------------------
-I-nt-e-rn-al-B-u-s-M-a-st-er-
(
NOTES: [IJ A19/PS3-A16/PSo, ADrADo, AwAs, BUFEN,BUFR/W,MRD,IORD,MWR,IOWR
[2J BS2-BSO
83-001842B
HLDRQ/HLDAK Timing, Bus Wait
CLKOUT
HLDRQ
HLDAK
[NOTEIJ
::
-------------c'l ~___E_xt_er_n_al_B_u_S_M_8_st_e_r_ _ _ _ _ _ _ _ _ _ _ _ _..J»)--------«
Internal Bus Master
83-002732B
22
NEe
pPD70208 (V40)
Timing Waveforms (cont)
Refresh Timing
T4
T1
T2
T3/TW
T4
CLKOUT
Undefined
Row Address
AS
AD7"ADo - - - - - - - « 1
ASTB
tORQHRH
tOKeT2
,t
OKBH
aS2
= 1, aS1 = 0, aso = 1
!
83-0027318
23
NEe
pPD702'08 (V40)
Timing Waveforms (cont)
DMAU, DMA Transfer Timing
T4
T1
T2
T3/TW
T4
CLKOUT
ASTB
tOKA
Address
AD7-ADo
tOKHOA
-
tORHOAH
tOKRH
tOOARW_
~------t-tRR-----+---""""1
1,..-----
tOKen
tOOARW_1
83-0027239
24
NEe
pPD70208 (V40)
Timing Waveforms (cont)
DMA Timing
EN D/TC Timing
T2
T1
T3
T4
CLKOUT
TC
tSEDK
END
~EDl-l
-------0..-----------------------
DMA Request Timing
T2
CLKOUT
OMARan
(n=0-3)
Cascade Mode, Normal Operation
Cascade Mode, Refresh Cycle Insertion
CLKOUT
OMARa
OMAAK -----------~
83-001826C
NEe
pPD70208 (V40)
Timing Waveforms (cont)
SCU Timing
RXD\_ _~I_ _ _L
l~tSRX---'oI4Il.l---- tHRX---.j
TounJ
14---+16 or 64 Toun pulses-----+I
1 4 - - - 1 6 or 64 TOUn pulses - - - -
TxD
tOTX
CLKOUT
' ' "1
SiffiY
83-001849B
ICU Timing
INTPn
(n=1-7)
I
('''''')
"~ "J
t\'EC
pPD70208 (V40)
Timing Waveforms (coni)
TCU Timing, Internal Clock Source
CLKOUT
TCTL2
____________£'00'0 ~o"'.
TOUTn
[n = 1, 2J _ _ _ _ _ _ _ _ _ _ __
83-002722B
TCU Timing, TCLK Source
tTKR
tTKF
TCLK
TCTL2
TOUTn
----------~-;-:-~-)--~~-----:~C'~ro
[n=1,2J _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
83-001823B
NEe
Functional Description
Central Processing Unit
Refer to the pPD70208 block diagram for an overview
of the ten major functional blocks listed below.
The pPD70208 CPU functions similarly to the CPU of
the pPD70108 CMOS microprocessor. However, be:...
cause the pPD70208 has internal peripheral devices,
its bus architecture has been modified to permit
sharing the bus with internal peripherals. ThepPD70208
CPU is object code compatible with both the pPD70108/
pPD70116 and thepPD8086/pPD8088 microprocessors.
•
•
•
•
•
•
•
•
•
•
Central processing unit (CPU)
Clock generator (CG)
Bus interface unit (BIU)
Bus arbitration unit (BAU)
Refresh control unit (RCU)
Wait control unit (WCU)
Time.r/counter unit (TCU)
Serial control unit (SCU)
Interrupt control unit (ICU)
DMA control unit (DMAU)
Figure 1.
Figure 1 is the pPD70208 CPU block diagram. A listing
of the pPD70208 instruction set is in the final sections
of this data sheet.
pPD70208 CPU Block Diagram
Internal address/data bus (20)
~_ _ _ _ _ _ _ _ _ _ _ _ _~
To BIU
NMI
INT
(from ICU)
CLOCK
(from CG)
BCU
EXU
LC
pc
Effective Address
Generator
AW
Subdata bus(16)
Main data bus(16)
83-0027338
NEe
pPD70208 (V40)
Register Configuration
Program Counter [PC]. The program counter is a 16bit binary counter that contains the program segment
offset of the next instruction to be executed. The PC is
incremented each time the microprogram fetches an
instruction from the instruction queue. The contents of
the PC are replaced whenever a branch, call, return, or
break instruction is executed and during interrupt
processing. At this time, the contents of the PC are the
same as the prefetch pointer (PFP).
Prefetch Pointer [PFP]. The prefetch pointer is a
16-bit binary counter that contains the program segment offset of the next instruction to be fetched forthe
instruction queue. Because instruction queue prefetch
is independent of instruction execution, the contents
of the PFP and PC are not always identical. The PFP is
updated each time the bus interface unit (BIU) fetches
an instruction for the instruction queue. The contents
of the PFP are replaced whenever a branch, call, return
or break instruction is executed and during interrupt
processing. At this time, the contents of the PFP and
PC are the same.
Segment Registers [PS, SS, OSo, OS1]. ThepPD70216
memory address space is divided into 64K-byte logical
segments. A memory address is determined by the sum
of a 20-bit base address (obtained from a segment
register) and a 16-bit offset known as the effective
address (EA). I/O address space is not segmented and
no segment register is used. The four segment registers
are program segment (PS), stack segment (SS), data
segment 0 (DS o), and data segment 1 (DS1)' The
following table lists their offsets and overrides.
Default
Segment Register
Offset
General-Purpose Registers. The pPD70208 CPU contains four 16-bit, general-purpose registers (AW, BW,
CW, OW), each of which can be used as a pair of 8-bit
registers by dividing into upper and lower bytes (AH,
Al, BH, Bl, CH, Cl, DH, DL). General-purpose
registers may also be specified implicitly in an instruction. The implicit assignments are:
AW
Word multiplication/division, word I/O,
data conversion
Al
Byte multiplication/division, byte I/O, BCD
rotation, data conversion, translation
AH
Byte multiplication/division
BW
Translation
CW
loop control, repeat prefix
Cl
Shift/rotate bit counts, BCD operations
OW
Word multiplication/division, indirect
I/O addressing
II
Pointer [SP, BP] and Index Registers [IX, IV]. These
registers serve as base pointers or index registers
when accessing memory using one of the base,
indexed, or base indexed addressing modes. Pointer
and index registers can also be used as operands for
word data transfer, arithmetic, and logical instructions.
These registers are implicitly selected by certain
instructions as follows.
SP
Stack operations, interrupts
IX
Source block transfer, BCD string
operations, bit field extraction
IV
Destination block transfer, BCD string
operations, bit field insertion
Override
Program Status Word [PSW]
PS
PFP register
None
SS
SP register
None
SS
Effective address (SP-based)
PS, DSo, DS1
The program status word consists of six status flags
and four control flags.
DSo
Effective address (non SP-based)
PS, SS, DSl
Status Flags
DSo
IX register (1)
PS, SS, DS1
DS1
IV register (2)
None
•
•
•
•
•
•
Note:
(1) Includes source block transfer, output, BCD string, and bit field
extraction.
(2) Includes destination block transfer, input, BCD string, and bit
field insertion.
V (Overflow)
S (Sign)
Z (Zero)
AC (Auxiliary Carry)
P (Parity)
CV (Carry)
Control Flags
•
•
•
•
MD (Mode)
DIR (Direction)
IE (Interrupt Enable)
BRK (Break)
29
NEe
pPD70208 (V40)
When pushed onto the stack, the word image of the
PSW is as follows:
15
8
v
MD
DIR
I
o
7
S
IE I BRK
Figure 2. Dual Data Buses
z
o
AC
o
P
CY
The status flags are set and cleared automatically
depending upon the result of the previous instruction
execution. Instructions are provided to set, clear, and
complement certain status and control flags. Other
flags can be manipulated by using the POP PSW
instruction.
Between execution of the BRKEM and RETEM instructions, the native mode RETI and POP PSW
instructions can modify the MD bit. Care must be
exercised by emulation mode programs to prevent
inadvertent alteration of this bit.
CPU Architectural Features
The major architectural features ofthepPD70208 CPU
are:
•
•
•
•
Main data bus
Sub data bus
83-0038288
Figure 3. Effective Address Generator
Dual data buses
Effective address generator
Loop counter
PCand PFP
Dual Data Buses. To increase performance, dual data
buses (figure 2) have been employed in the CPU to
fetch operands in parallel and avoid the bottleneck of a
single bus. For two-operand instructions and effective
address calculations, the dual data bus approach is 30
percent faster than single-bus systems.
Effective Address Generator. Effective address (EA)
calculation requires only two clocks regardless of the
addressing mode complexity due to the hardware
effective address generator (figure 3). When compared
with microprogrammed methods, the hardware approach saves between 3 and 10 clock cycles during
effective address calculation.
Loop Counter and Shifters. A dedicated loop counter is
used to count the iterations of block transfer and
multiple shift instructions. This logic offers a significant
performance advantage over architectures that control
block transfers and multiple shifts using microprogramming. Dedicated shift registers also speed up the
execution of the multiply and divide instructions.
Compared with microprogrammed methods, multiply
and divide instructions execute approximately four
times faster.
30
Effective Address
83-002737A
Program Counter and Prefetch Pointer. The functions
of instruction execution and queue prefetch are decoupled in the pPD70208. By avoiding a single instruction pointer and providing separate PC and PFP
registers, the execution time of control transfers and
the interrupt response latency can be minimized.
Several clocks are saved by avoiding the need to
readjust an instruction pointer to account for prefetching before computing the new destination address.
Enhanced Instruction Set
In addition to the pPD8086/88 instruction set, the
pPD70208 has added the following enhanced instructions.
NEe
pPD70208 (V40)
Instruction
PUSH imm
PUSH R
POP R
Function
Push immediate data onto stack
Push all general registers onto stack
Pop all general registers from stack
MUL imm
Multiply register/memory by immediate data
SHL immB
SHR immB
SHRA immB
ROL immB
ROR immB
ROLC immB
RORC immB
Shift/rotate by immediate count
CHKIND
INM
OUTM
Check array index
Input multiple
Output multiple
PREPARE
DISPOSE
Prepare new stack frame
Dispose current stack frame
Packed BCD Strings. These instructions are provided
to efficiently manipulate packed BCD data as strings
(length from 1 to 254 digits) or as a byte data type with a
single instruction.
Unique Instruction Set
In addition to thepPD70208 enhanced instruction set,
the following unique instructions are supported.
Instruction
Bit field extraction (EXT) copies the bit field of specified
length (0 = 1 bit, 15 = 16 bits) from the bit field
addressed by DSO:IX:reg8 to the AW register (figure 5).
If the bit field is less than 16 bits, it is right justified with
a zero fill. The bit field length can be located in any byte
register or supplied as immediate data. The value in
rega is a bit field offset. A content of 0 selects bit 0 and
15 selects bit 15 of the word that DSO:IX points to.
Following execution, the IX and bit offset register are
updated to point to the start of the next bit field.
Function
INS
EXT
Insert bit field
Extract bit field
ADD4S
SUB4S
CMP4S
ROL4
ROR4
BCD string addition
BCD string subtraction
BCD string comparison
Rotate BCD digit left
Rotate BCD digit right
TEST1
SET1
CLR1
NOT1
Test bit
Set bit
Clear bit
Complement bit
REPC
REPNC
Repeat while carry set
Repeat while carry cleared
FP02
Floating point operation 2
Bit Fields. Bit fields are data structures that range in
length from 1 to 16 bits. Two separate operations on bit
fields, insertion and extraction, with no restrictions on
the position of the bit field in memory are supported.
Separate segment, byte offset, and bit offset registers
are used for bit field insertion and extraction. Because
of their power and flexibility, these instructions are
highly effective for graphics, high-level languages, and
data packing/unpacking applications.
Insert bit field (INS) copies the bit field of specified
length (0 = 1 bit, 15 = 16 bits) from the AW register to
the bit field addressed by DS1:IY:reg8 (figure 4). The
bit field length can be located in any byte register or
supplied as an immediate value. The value in reg8 is a
bit field offset. A content of 0 selects bit 0 and 15 selects
bit 15 of the word that DSO:IX points to. Following
execution, the IY and bit offset register are updated to
point to the start of the next bit field.
BCD string arithmetic is supported by the ADD4S,
SUB4S, and CMP4S instructions. These instructions
allow the source string (addressed by DSO:IX) and the
destination string (addressed by DS1 :IY) to be manipulated with a single instruction. When the number of
BCD digits is even, the Z and CY flags are set according
to the result of the operation. If the number of digits is
odd, the Z flag will not be correctly set unless the upper
4 bits of the result are zero. The CY flag will not be
correctly set unless there is a carry out of the upper 4
bits of the result.
The two BCD rotate instructions (ROR4, ROL4) perform
rotation of a single BCD digit in the lower half of the AL
register through the register or memory operand.
Bit Manipulation. Four bit manipulation instructions
have been added to the pPD7020a instruction set. The
abilityto test, set, clear, or complement a single bit in a
register or memory operand increases code readability
as well as performance over the logical operations
traditionally used to manipulate bit data.
Repeat Prefixes. Two repeat prefixes (REPC, REPNC)
allow conditional block transfer instructions to use the
state of the CY flag as a terminating condition. The use
of these prefixes allows inequalities to be used when
working on ordered data, increasing the performance
of searching and sorting algorithms.
Floating Point Operation Instructions. Two floating
point operation (FPO) instruction types are recognized
by thepPD7020a CPU. These instructions are detected
by the CPU, which performs any auxiliary processing
such as effective address calculationand the initial bus
cycle if specified by the instruction. It is the responsibility of the external coprocessor to latch the address
information and data (if a read cycle) from the bus and
complete the execution of the instruction.
1:'-11
m:iI
NEe
pPD70208 (V40)
Figure 4.
Bit Field Insertion
Bit length
15
AW
Bit offset
Memory
Segment base (051)
Byte boundary
83-000106B
Figure 5.
Bit Field Extraction
Bit length
Bit offset
Byte boundary
Segment base (050)
83-000107B
8080 Emulation Mode. The pPD70208 CPU can operate
in either of two modes; see figure 6. Native mode allows
the execution ofthepPD8086/88, enhanced and unique
instructions. The other operating mode is 8080 emulation mode, which allows the entire pPD8080AF
instruction set to be executed. A mode (MD) flag is
provided to distinguish between the two operating
modes. Native mode is active when M D is 1 and 8080
emulation mode is active when MD is O.
Two instructions are provided to switch from na"tive to
8080 emulation mode and return back. Break for
emulation (BRKEM) operates similarly to a BRK
instruction, except that after the PSW has been pushed
on the native mode stack, the M D flag becomes
write-enabled and is cleared.
.
During 8080 emulation mode, the registers and flags of
the 8080 are mapped onto the native mode registers
and flags as shown below. Note that PS, SS, DSo, DS1,
IX, IY, AH, and the upper half of the PSW registers are
inaccessible to 8080 programs.
32
Registers
JlJIPD8080AF
JlPD70208
A/PSW
B
C
D
ALIPSW (lower)
CH
CL
DH
DL
BH
BL
BP
PC
Cy
E
Flags
H
L
SP
PC
C
Z
Z
S
P
AC
S
P
AC
During 8080 emulation mode, the BP registerfunctions
as the 8080 stack pointer. The use of separate stack
pointers prevents inadvertent damage to the native
mode stack pointer by emulation mode programs.
NEe
The 8080 emulation mode PC is combined with the PS
register to form the 20-bit physical address. All emulation mode data references use DSO as the segment
register. For compatibility with older 8080 software
these registers must be equaL By using different
segment register contents, separate 64K-byte code
and data spaces are possible.
Either an NMI or maskable interrupt will cause the 8080
emulation mode to be suspended. The CPU pushes the
PS, PC, and PSW registers on the native mode stack,
sets the MD bit (indicating native mode), and enters the
specified interrupt handler. When the return from
interrupt (RETI) instruction is executed, the PS, PC,
and PSW (containing MD=O) are popped from the
native stack and execution in 8080 emulation mode
continues. Reset will also force a return to native mode.
The 8080 emulation mode programs also have the
capability to invoke native mode interrupt handlers by
means of the call native (CALLN) instruction. This
instruction operates like the BRK instruction except
that the saved PSW indicates 8080 emulation mode.
Figure 6.
pPD70208 (V40)
To exit 8080 emulation mode, the return from emulation
(RETEM) instruction pops the PS, PC, and PSW from
the native mode stack, disables modification of the MD
bit, and execution continues with the instruction following the BRKEM instruction. Nesting of 8080 emulation
modes is prohibited.
Interrupt Operation
TheJiPD70208 supports a number of external interrupts
and software exceptions. External interrupts are events
asynchronous to program execution. On the other
hand, exceptions always occur as a result of program
execution.
The two types of external interrupts are:
• Nonmaskable interrupt (NMI)
• Maskable interrupt (INT)
JiPD 70208 Modes
83-0038308
33
NEe
pPD70208 (V40)
The six software exceptions are:
•
•
•
•
•
•
Divide error (DIV, DIVU instructions)
Array bound error (CHKIND instruction)
Break on overflow (BRKV instruction)
Break (BRK, BRK3 instructions)
Single step (BRK bit in PSW set)
Mode switch (BRKEM, CALLN instructions)
Interrupt vectors are determined automatically for
exceptions and the NMI interrupt or supplied by
hardware for maskable interrupts. The 256 interrupt
vectors are stored in a table (figure 7) located at
address OOOOOH. Vectors 0 to 5 are predetermined and
vectors 6 to 31 are reserved. Interrupt vectors 32 to 255
are available for use by application software.
Each vector is made up of two words. The word located
at the lower address contains the new PC for the
interrupt handler. The word at the next-higher address
is the new PS value for the interrupt handler. These
must be initialized by software at the start of a program.
Nonmaskable interrupts and maskable interrupts (when
enabled) are normally serviced following the execution
of the current instruction. However, the following
cases are exceptions to this rule and the occurrence of
the interrupt will be delayed until after the execution of
the next instruction.
•
•
•
•
Moves to/from segment registers
POLL instruction
Instruction prefixes
EI instruction (maskable interrupts only)
Another special case is the block transfer instructions.
These instructions are interruptable and resumable,
but because of the asynchronous operation of the BIU,
the actual occurrence of the interrupt may be delayed
up to three bus cycles.
During standby mode, the clock is distributed only to
the circuits required to release the standby mode.
When a RESET, NMI, or INT event is detected, the
standby mode is released. Both NMI and unmaskable
interrupts are processed before controir,eturns to the
instruction following the HALT. In the case of the INT
input being masked, execution will begin with the
instruction immediately following the HALT instruction
without an intervening interrupt acknowledge bus
cycle. When maskabl~ interrupts are again enabled, the
interrupt will be serviced.
Output signal states in the standby mode are listed
below.
Output Signal
Status in Standby Mode
INTAK, BUFEN,
MRD, MWR, IOWR,
lORD
High level
BS2-BSO (Note 2)
High level
BUS LOCK
High level (low level if the
HALT instruction follows the
BUS LOCK prefix)
BUFR/W,
A19-A16/PS3-PSO,
A15- AS, AD7-ADo
High or low level
Low level
Note:
(1) Output pin states during refresh and DMA bus cycles will be as
defined for those operations.
(2) Halt status is presented prior to entering the passive state.
Figure 7.
Interrupt Vector Table
OOOH
Vector 0
Divide Error
Vector 1
Break Flag
Vector 2
NMllnput
Vector 3
BRK 3 Instruction
004H
Standby Mode
008H
The JlPD70208 CPU has a low-power standby mode,
which can dramatically reduce power consumption
during idle periods. Standby mode isentered by simply
executing a native or 8080 emulation HALT instruction;
no external hardware is required. All other peripherals
such as the timer/counter unit, refresh control unit,
and DMA control unit continue to operate as programmed.
OOCH
Dedicated
010H
Vector4
BRKV Instruction
VectorS
CHKIND Instruction
014H
018H
VectorS
07CH
},-~,
Vector 31
080H
General Use
Vector 32
3FCH
Vector 255
}
•
•
•
•
BRK imm8 Instruction
BRKEM Instruction
INT Input [External]
CALLN Instruction
83·000111A
34
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pPD70208 (V40)
Figure 9.
Clock Generator
External Oscll/ator Configuration
The clock generator (CG) generates a clock signal half
the frequency of a parallel-resonant, fundamental
mode crystal connected to pins X1 and X2. Figure 8
shows the recommended circuit configuration. Capacitors C1 and C2, required for frequency stability, are
selected to match the crystal load capacitance.
External clock sources are also accommodated as
shown in figure 9. The CG distributes the clock to the
CLKOUT pin and to each functional block of the
pPD70208. The generated clock signal has a 50percent duty cycle.
External
Clock
83-002740A
Figure 10.
RESET/READY Synchronization
Bus Interface Unit
The bus interface unit (BIU) controls the external
address, data, and control buses for the three internal
bus masters: CPU, DMA control unit (DMAU), and
refresh control unit (RCU). The BIU is also responsible
for synchronization of the RESET and READY inputs
with the clock. The synchronized reset signal is used
internally by the pPD70208 and provided externally at
the RESOUT pin as a system-wide reset. The synChronized READY signal is combined with the output of
the wait control unit (WCU) and is distributed internally
to the CPU, DMAU, and RCU. Figure 10 shows the
synchronization of RESET and READY.
CLOCK
RESOUT
To internal
circuit
To internal
circuit
83-002728A
The BIU also has the capability of overlapping the
execution of the next instruction with memory write
bus cycles. There is no overlap of instruction execution
with read or I/O write bus cycles.
Figure 8. Crystal Configuration
Xl
OSC
Oscillator
Frequency Divider
[+2]
CLKOUT
X2
o
Cl
e'ye,
= C2 = 15 to 30 pF
CLOCK (to internal circuit)
osc
I
CLOCK
(CLKOUT)
J
I
1---.-1:'. ------4}83-001822B
35
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J.lPD70208 (V40)
determine the I/O addressing, enable/disable peripherals, and control pin multiplexing. Byte I/O instructions must be used to access the system I/O area.
Bus Arbitration Unit
The bus arbitration unit (BAU) arbitrates the external
address, data and control buses between the internal
CPU, DMAU, and RCU bus requesters and an external
bus master. TheBAU bus priorities from the highest
priority requester to the lowest are:
RCU (Demand mode)
DMAU
HLDRQ
CPU
RCU (Normal mode)
Note that RCU requests the bus at either the highest or
lowest priority depending on the status of the refresh
request queue. Bus masters other than the CPU are
prohibited from using the bus when tHe CPU is
executing an instruction containing a BUSLOCK prefix.
Therefore, caution shouldbe exercised when using the
BUS LOCK prefix with instructions having a long
,execution time.
If abus master with higher priority than the current bus
master requests the bus, the BAU inactivates the
current bus master's acknowledge signal. When the
BAU sees the bus request from the current master go
inactive, the BAU gives control of the bus to the higher
priority bus master. Whenever possible, the BAU performs bus switching between internal bus masters
without the introduction of idle bus cycles, enhancing
system throughput.
liD Address
Register
Operation
FFFFH
FFFEH
FFFDH
Reserved
OPCN
OPSEL
Read/Write
Read/Write
FFFCH
FFFBH
FFFAH
OPHA
DULA
IULA
Read/Write
Read/Write
ReadlWrite
FFF9H
FFF8H
FFF7H
TULA
SULA
Reserved
ReadiWrite
Read/Write
FFF6H
FFF5H
FFF4H
WCY2
WCY1
WMB
Read/Write
Read/Write
Read/Write
FFF3H
FFF2H
FFF1H
Reserved
RFC
Reserved
Read/Write
FFFOH
TCKS
Read/Write
On-Chip Peripheral Connection Register
System 110 Area
The on~chip peripheral connection (OPCN) register
controls multiplexing of the JlPD70208 multiplexed
pins. Figure 11 shows the format of the OPCN register.
The interrupt request switch (IRSW) field controls
multiplexing of ICUinterrupt inputs INT1 and INT2.
The output of an internal peripheral or ~n external
interrupt source can be selected as the INTland INT2
inputs to the ICU.
The I/O address space from addresses FFOOH to
FFFFH is reserved for use as the system I/O area.
Located in this area are the 12 JlPD70208 registers that
The pin function (PF) field in the OPCN selects one of
four possible states for the DMARQ3/RxD, DMAAK3/
TxD, and INTAK/TOUT1/SRDY pins. Bit 0 of the
Figure 11.
OpeN Register Format
21
I - I- I- I- I
IRSW
I
PF
OPCN
L
p;" F,"oIi,"
DMAR03/RxD
DMAAK3/TxD
00
DMAR03
DMAAK3
INTAK
01
DMAR03
DMAAK3
TOUT1
10
RxD
TxD
INTAK
11
RxD
TXD
SRDY
Interrupt Request Switch
00
INTAK/SRDY/TOUT1
INT1
INTP1 Pin
INTP2 Pin
INT2
01
SCU
INTP2 Pin
10
INTP1 Pin
TOUn
11
SCU
TO un
83-0018276
36
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pPD70208 (V40)
Internal Peripheral Relocation Registers
OPCN controls the function of the INTAK/TOUT1/
SRDY pin. If cleared, INTAK will appear on this
output pin. If bit 0 is set, either TOUT1 or SRDY will
appear at the output depending on the state of bit 1. If
bit 1 is cleared, DMA channel3110 signals will appear
on the DMARQ3/RxD and DMAAK3/TxD pins. If the
SCU is to be used, bit 1 of the PF field must be set.
The five internal peripheral relocation registers (figure
13) are used to fix the 110 addresses of the DMAU, ICU,
TCU, and SCU. The on-chip peripheral high-address
(OPHA) register is common to all four internal peripherals and fixes the high-order byte of the 16-bit I/O
address. The individual DMAU low-address (DULA)
register, ICU low-address (IULA) register, TCU lowaddress (TULA) register, and the SCU low-address
(SULA) register select the low-order byte of the I/O
addresses for the DMAU, ICU, TCU, and SCU peripherals.
On-Chip Peripheral Selection Register
The on-chip peripheral selection (OPSEL) register is
used to enable ordisable theJlPD70208 internal peripherals. Figure 12 shows the format of the OPSEL
register. Any of the four (DMAU, TCU, ICU, SCU)
peripherals can be independently enabled or disabled
by setting or clearing the appropriate OPSEL bit.
Figure 12.
7
The contents of the OPHA register are:
OPHA
7
o
A8
OPSEL Register Format
The formats for the individual internal peripheral registers appear below. Since address checking is not
performed, do not overlap two peripheral I/O address
spaces.
DULA
7
o
4
I - I - I ~ I - I 55 I T5 I IS I DS I OPSEL
~J
rrPeripheral
Selected
~
DMAU
~
ICU
TCU
7
IULA
o
7
TULA
o
7
SULA
o
Operation
0==
1
Disabled
Enabled
SCU
83-001813A
Figure 13.
JlPD7020B Peripheral Relocation
64 K byte 1/0 space
FFFFH
FFOOH
Reserved
System 1/0 Area
256 byte area
r--------;
/
/
OPHA'256~/
0100HD '\\.\~_____. .
"\
-'-'-...-ou LA
.....
_ ..............L.J...'"-'-"--'-'-............
OOOOH
83-0027278
37
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pPD70208 (V40)
The RCU will then perform back-to-back refresh cycles
until three requests remain in the queue. This guarantees the integrity of the DRAM system while maximizing performance.
Timer Clock Selection Register
The timer clock selection (TCKS) register selects the
clock source for each of the timer/counters as well as
the divisor for the internal clock prescaler. Figure 14
shows the format of the TCKS register. The clock
source for each timer/counter is independently selected from either the prescaled internal CPU clock orfrom
an external clock source (TCLK). The internal clock is
derived from the CLKOUT signal and can be divided by
2,4,8, or 16 before being presented to the clock select
logic.
The refresh count interval can be calculated as follows:
Refresh interval
= 8 x N x tCYK
where N is the timer factor selected by the RTM
field.
When the pPD70208 is reset, the RE field in the RFC
register is unaffected and the RTM field is set to 01000
(N = 9). No refresh bus cycles occur while RESET is
asserted.
Refresh Control Unit
The refresh control unit (RCU) refreshes external
dynamic RAM devices by outputting a 9-bit row address
on address lines As-Ao and performing a memory read
bus cycle. External logic can distinguish a refresh bus
cycle by monitoring the refresh request (REFRQ) pin.
Following each refresh bus cycle, the refresh row
counter is incremented.
Figure 15.
Refresh Control Register
5
IRE
4
1-I -1
I RFC
RTM
L
The refresh control (RFC) register in the system I/O
area contains two fields. The refresh enable field
enables or disables the refreshing fu nction. The refresh
timer (RTM) field selects a refresh interval to match the
dynamic memory refresh requirements. Figure 15
shows the format for the RFC register.
R.I.... Ti_
N (Timer Factor)
00000
00001
00010
00011
17
18
19
20
-- -- - - - 5
00100
To minimize the impact of refresh on the system bus
bandwidth, the pPD70208 utilizes a refresh request
queue to store refresh requests and perform refresh
bus cycles in otherwise idle bus cycles.
.
00101
6
11110
11111
31
32
Refresh Enable
Function
0
1
Disables Refresh
The RCU normally requests the bus as the lowestpriority bus requester (normal mode). However, if
seven refresh requests are allowed to accumulate in
the RCU refresh request queue, the RCU will change to
the highest-priority bus requester (demand mode).
Figure 14.
Enables Refresh
83-001814A
Timer Clock Selection Register
4
I - I - I - I CS2 I CS1 I cso I
PS
~
I
TCKS
Prescale Select
Internal Clock
Prescaled by:
00
2
01
4
10
8
16
11
Clock Selection
for TCTn
Clock
Input
0
Internal Clock
TCLK Pin
1
83-001819B
38
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pPD70208 (V40)
Wait Control Unit
The wait control unit (WCU) inserts from zero to three
wait states into a bus cycle in order to compensate for
the varying access times of memory and 1/0 devices.
The number of wait states for CPU, DMAU, and RCU
bus cycles is separately programmable. In addition,
the memory address space is divided into three independent partitions to accommodate a wide range of
system designs. RESET initializes the WCU to insert
three wait states in all bus cycles. This allows operation
with slow memory and peripheral devices before the
initialization of the WCU registers.
The three system I/O area registers that control the
WCU are wait cycle 1 (WCY1), wait cycle 2 (WCY2),
. and wait state memory boundary (WMB). The WCU
always inserts wait states corresponding to the wait
count programmed in WCY1 or WCY2 registers into a
bus cycle, regardless of the state of the external
READY input. After the programmed number of wait
states occurs, the WCU will insert Tw states as long as
Figure 16.
the READY pin remains inactive. When READY is again
asserted, the bus cycle continues with T4 as the next
cycle. TheJlPD70208 internal peripherals neverrequire
wait states; four clock cycles will terminate an internal
peripheral bus cycle.
CPU Wait States
The WMB register divides the 1M-byte memory address
space into three independent partitions: lower, middle,
and upper. Figure 16 shows the WMB register format.
Initialization software can then set the number of wait
states for each memory partition and the 1/0 partition
via the WCY1 register (figure 17).
DMA and Refresh Wait States
The WCY2 register (figure 18) specifies the number of
wait states to be automatically inserted in DMA and
refresh bus cycles. DMA wait states must be set to the
maximum of the DMA memory and I/O partitions.
Refresh wait states should be set to the maximum value
of all DRAM memory partitions.
Wait State Memory Boundary Register
7
I-I
6
LMB
I-I
UMB
I
~
WMB
Lower Memory Block Size [1)
Upper Memory Block Size
Memory Block Size (KB)
32
64
96
000
001
010
011
128
100
192
101
256
384
110
111
512
FFFFFH .....-------........,}
Upper Memory Block
Specified by the UMB Field
Middle Memory Block
~_Lo_w_e_rM_e_m_O_ry_B_lo_Ck_..... } Specified by the
OOOOOH _
LM B Field
Note:
[1) By default, the address space remaining between the UBM and LBM is the
middle memory block.
83-0018208
39
NEe
pPD70208 (V49)
Figure 17.
Wait Cycle 1 Register
Figure 18.
Wait Cycle 2 Register
76543210
4
I lOW UMWIMMWILMW IWCY1
G. . ,
,--I
-.J
I -
I -
I -
I -
I DMAW I
RFW IWCY2
~""'h
M.m,,,! Block W.' .,,",
~
Middle Memory Block Wait States Number of
Upper Memory Block Wait States Wait States
1/0 Wait States
0
00
01
1
10
2
11
3
W.;I
'101"
DMA Wait States
Number of
Wait States
00
0
01
1
10
11
3
2
83-001815A
83-001818A
Timer/Counter Unit
The timer/counter unit (TCU) provides a set of three
independent 16-bit timer/counters. The output signal
of ti mer/cou nter 0 is hardwi red internally as an i nterru pt
source. The output of timer/counter 1 is available
internally as an interrupt source, used as a baud rate
generator, or used as an external output. The timer/
counter 2 output is available as an external output. Due
to mode restrictions, the TCU is a subset of the
Figure 19.
pPD71054 Programmable Timer/Counter.' Figure 19
shows the internal block diagram of the TCU.
The TCU has the following features:
•
•
•
•
•
Three 16-bit timer/counters
Six programmable count modes
Binary/BCD counting
Multiple latch command
Choice of two clock sources
TCU Block Diagram
TCLK (EXT)
CLOCK
TCTLO=High
TOUTO (to ICU)
TCTL1 =Hlgh
TOUT1 (EXT)
TCTL2 (EXT)
TOUT2 (EXT)
Read/Write Control
Circuit
TMD
(Mode
Register)
I
I
I
I
L
83-001834B
40
NEe
pPD70208 (V40)
Because RESET leaves the TCU in an uninitialized
state, each timer/counter must be initialized by
specifying an operating mode and a count. Once
programmed, a timer/counter will continue to operate
in that mode until another mode is selected. When the
count has been written to the counter and transferred
to the down counter, a new count operation starts.
Both the current count and the counter status can be
read while count operations are in progress.
TCU Commands
The TCU is programmed by issuing I/O instructions to
the I/O port addresses programmed in the OPHA and
TULA registers. The individual TCU registers are
selected by address bits A1 and Ao as follows.
At
AD
Register
Operation
0
0
TCTO
TSTO
TCT1
TST1
TCT2
TST2
TMD
Read/Write
Read
0
0
The timer
mode for
command
shows the
Read/Write
Read
Read/Write
Read
Write
mode (TMO) register selects the operating
each timer/counter and issues the latch
for one or more timer/counters. Figure 20
format for the TMD register.
Writes to the timer/counter 2-0 (TCT2-TCTO) registers
stores the new count in the appropriate timer/counter.
The count latch command is used before reading
count data in order to latch the current count and
prevent inaccuracies.
The timer status 2-0 (TST2-TSTO) registers contain
status information for the specified cou nter (figu re 21).
The latch command is used to latch the appropriate
counter status before reading status information. If
both status and counter data are latched for a counter,
the first read operation returns the status data and
subsequent read operations obtain the count data.
Count Modes
There are six programmable timer/counter modes. The
timing waveforms for these modes are in figure 22.
Mode 0 [Interrupt on End of Count]. In this mode,
TOUT changes from the low to high level when the
specified count is reached. This mode is available on
all timer/counters.
Mode 1 [ Retriggerable One-Shot]. In mode 1, a lowlevel one-shot pulse, triggered by TCTL2 is output
from the TOUT2 pin. This mode is available only on
timer/counter 2.
'
Mode 2 [Rate Generator]. In mode 2, TOUT cyclically
goes low for one clock period when the counter
reaches the 0001 H count. A counter in this mode
operates as a frequency divider. All timer/counters can
operate using mode 2.
Mode 3 [Square-Wave Generator]. Mode 3 is a frequency
divider similar to mode 2, but the output has a symmetrical duty cycle. This mode is available on all three
timer/counters.
Mode 4 [Software-Triggered Strobe]. I n mode 4, when
the specified count is reached, TOUT goes low for the
duration of one clock pulse. Mode 4 is available on all
timer/counters.
ModeS [Hardware-Triggered Strobe]. Mode5 is similar
to mQde 4 except that operation is triggered by the
TCTL2 input and can be retriggered. This mode is
available only on timer/counter 2.
Serial Control Unit
The serial control unit (SCU) is a single asynchronous
serial channel that performs serial communication
between the pPD70208 and an external serial device.
TheSCU issimiiartothepPD71051 Serial Control Unit
except for the lack of synchronous communication
protocols. Figure 23 is the block diagram of the
SCU.
The SCU has the following features.
•
•
•
•
•
•
•
•
•
•
Full-duplex asynchronous serial controller
Clock rate divisor (x16, x64)
Baud rates to 250 kb/ssupported
7-, 8-bit character lengths
1-, 2-bit stop bit lengths
Break transmission and detection
Full-duplex, double-buffered transmitter/receiver
Even, odd, or no parity
Parity, overrun, and framing error detection
Receiver-full/transmitter-empty interrupt
The SCU contains fou r separately addressable registers
for reading/writing data, reading status, and controlling operation of the SCU. The serial receive buffer
(SRB) and the serial transmit buffer (STB) store the
incoming and outgoing character data. The serial
status (SST) register allows software to determine the
current state of both the transmitter and receiver. The
serial command (SCM) and serial mode (SMD) registers
determine the operating mode of the SCU while the
serial interrupt mask (SIMK) register allows software
control of the SCU receive and transmit interrupts.
41
~
a:iI
NEe
pPD70208 (V40)
Figure 20.
TMD
L
Timer Mode ,Register
sc
I
4
RWM
I
~
I
CMODE
BD
I
TMD
4
r
oT
sc
0
I o I
0
I
0
I o I
I
~
0
1
I
L-_
Binary
BCD
I
Count Mode
Mode
000
001
x10
0
x11
3
100
101
4
Counter to be Latched
TCTO
01
TCT1
10
TCT2
5
Operation
00
01
Counter Latch Command
Lower Byte Only
10
Higher Byte Only
11
Lower Byte Followed by
Higher Byte
Operation
Select Counter
00
01
TCTO
TCT1
10
TCT2
Multiple Latch Command
11
SC
00
1
2
Read/Write
Mode
~
L-....,
Count
Binary or BCD
Note: x = Don't care
83-0018178
Figure 21.
TCU Status Register
4
TSTn
I
oL'1 NC 1
RWM
2
1
CMODE
I
BD
I
1.1'"""'" ,•• '""'"'
mo. . . .«h'g.
The meaning of each field is the same
as that of the TMD register.
r
Null Count
1
Count Data
0
1
Valid
1
1
Invalid
I
r Output Levell
Level
1
Low
r
I
0
1
I
High
I
1
J
1
I
1
1
83-0018218
42
NEe
Figure 22.
pPD70208 (V40)
TCU Waveforms (Sheet 1 of 3)
Mode 0
ClK
IOWR
TOUT
Count Value
IOWR
L.:.J
TOUT
Count Value
IOWR
~
LJ
TCTL2
TOUT2
OOOOH
Count Value
IFFFFH IFFFEH IFFF DH I FFFCH
Mode 1
TCTL2 - - - - - - - - - \
t1---------------\ t1--------------\ t1----- -I 11------- ---
TOUT2
Count Value
TCTL2
n
I
n-1
I n-2
L:J
_--_-__
_ --__--__ t1----------------1t1---------------------~\
TOUT2
Count Value
n
I
n-1
I n-2
83-001851 B
43
NEe
pPD70208 (V40)
Figure 22.
TCU Waveforms (Sheet 2 of 3)
Mode 2
ClK
LJ
TCTL
TOUT
Count
Value
n
TOUT
Count
Value
n
n-1
I0006H I 0005H I 0004H I0003H I 0002H
Mode 3
ClK
IOWR
l
LB=4
LJ
TCTL
U
TOUT
Count
Value
IOWR
n
1
n-1
0004H
n-1
0004H
0002H
0004H
I
0002H
0004H
I
0002H
I
0004H
0004H
0004H
LB=5
L
TOUT
Count
Value
I
n
I
Q002H
I
OOOOH
0004H
I
0002H
0004H
0002H
I
0004H
OOOOH
I
83-0018536
44
NEe
Figure 22.
pPD70208 (V40)
TCU Waveforms (Sheet 3 of 3)
Mode 4
TOUT
Count Value
n
n-1
I
n
n-1
I 0004H I 0004H I 0004H I 0003H I 0002H I 0001 H
n-1
I
0004H
I
0003H
I
0002H
I
0001H
OOOOH
FFFFH
I
I
I
FFFEH FFFDH FFFCH
TCTl
TOUT
Count Value
IOWR
--, lB=5/
L-..J
TOUT
I
0005H
I
0004H
I
0003H
I
I
0002H
0003H
I
0002H
I
Q001H
OOOOH
FFFFH
Mode 5
TCTL2
-- - - - - - - - - - - -
TOUT2
Count Value
n-1
TCTL2 -- - - - - - -',
TOUT2
Count Value
I
I
-\n- --------- -- ----\ n------
n-2
I
n-3
I
0002H
I
l:
n ------
0001H'
n--------------------------: n----------
n-1
I
0004H
I
0003H
I
0002H
I
0001H
LJI
I
OOOOH
FFFFH tFFFEH
I
0003H I0002H
83-0018558
45
NEe
pPD70208 (V40)
Figure 23.
SCU Block Diagram
RESET
r--.
K"
~
J
SST
(Status Register)
J
I
CLOCK
I
I"
f~
I
I
Read/Write
Control
III
Ao
ec
SUS
0
RTCLK (from TCU)
II)
~
'" I
I
III
~K
1\1
SCM
(Command Register)
~
';
SRB
1 (Receive Data Buffer)
I
L
....
I
"
I
0
Receiver (Including
Receive Buffer)
f
(8)
(8)
I
A
iii
E
STB
(Transmit Data Buffer)
!
~
SMD
(Mode Register)
[
I
.4
~
~
.. 1
~
SIMK (Interrupt
Mask Register)
I
I
...
....
~
lieD
Transmitter
(Including Transmit
Buffer)
"~
"
:::)
0
II)
-
Receiver Operation
While the RxD pin is high, the receiver is in an idle state.
A transition on RxD from high to low indicates the start
of new serial data. When a complete, character has
been received, it is transferred to the SRB; the receive
buffer ready (RBRDY) bit in the SST register is set and
(if unmasked) an interrupt is generated. The SST also
latches any parity, overrun, or framing errors at this
time.
The receiver detects a break condition when a null
character with zerd parity is received. The BRK bit is
set for as long as the subsequent receive data is low
and resets when RxD returns to a high level. The MRDY
bit (SCM) and RBRDY (SST) are gated to form the
output SRDY. SRDY prevents overruns from occurring
when the program is unable to process the input data.
Software can control MRDY to prevent data from being
sent from the remote transmitter while RBRDY can
prevent the immediate overrun of a received character.
Transmitter Operation
TxD is kept high while the STB register is empty. When
the transmitter is enabled and a character is written to
the STB register, the data is converted to serial format
and output on the TxD pin. The start bit indicates the
start of the transmission and is followed by the character
46
/
'"
I
I
S
RxD
c
~
A
::I
Interrupt
Generation logic
SINT (To ICU)
83-001838B
stream (LSB to MSB) and an optional parity bit. One or
two stop bits are then appended, depending on the
programmed mode. When the character has been
transferred from the STB, the TRBDY bit in the SST is
set and if unmasked, a transmit buffer empty interrupt
is generated.
Serial data can be transmitted and received by polling
the SST register and checking the TBRDY or RBRDY
flags. Data can also be transmitted and received by
SCU-generated interrupts to the interrupt control unit.
The SCU generates an interrupt in either of these
conditions:
(1) The receiver is enabled, the SRB is full, and receive
interrupts are unmasked.
(2) The transmitter is enabled, the STB is empty, and
transmit interrupts are unmasked.
NEe
pPD70208 (V40)
SCU Registers and Commands
I/O instructions to the I/O addresses selected by the
OPHA and SULA registers are used to read/write the
SCU registers. Address bits A1 and Ao and the read/
write lines select one of the six internal registers as
follows:
AI
0
Ao
0
0
0
Register
Operation
SRB
STB
Read
Write
SST
SCM
Read
Write
SMD
Write
SiMK
Read/Write
Figure 25 shows the SCM and SMD registers. The SCM
register stores the command word that controls
transmission, reception, error flag reset, break transmission, and the state of the SRDY pin. The SMD
register stores the mode word that determines serial
characteristics such as baud rate divisor, parity, character length, and stop bit length.
Initialization software should first program the SMD
register followed by the SCM register. Unlike the
JlPD71051, the SMD register can be modified at any
time without resetting the SCU.
The SIMK register (figure 26) controls the occurrence
of RBRDY and TBRDY interrupts. When an interrupt is
masked, it is prevented from propagating to the inter- ~
rupt control unit.
U
The SRB and STB are a-bit registers. When the
character length is 7 bits, the lower 7 bits of the SRB
register are valid and bit 7 is cleared to O. If programmed
for 7-bit characters, bit 7 of the STB is ignored.
Baud Rate Generator
Timer/counter 1 is used as the baud rate generator
when the SCU is enabled. The input baud rate clock is
scaled by 16 or 64, as selected in the SMD register, to
determine the receive/transmit data clock. There are
no restrictions on the SCU input baud rate clock other
than operating the TCU in mode 3 with a square-wave
output.
The SST register (figure 24) contains the status of the
transmit and receive data buffers and the error flags.
Error flags are persistent. Once an error flag is set, it
remains set until a clearerrorflags command is issued.
Figure 24.
SST Register
4
SST \
1
\ BKD \ FE \ OVE \ PE \
1
\RBRDV\TBRDV\
I
J
Transmit Buffer Ready
0
l
1
l
.1 Receive Buffer Ready
0
L
I
1
J
Parity Error
1
L
J
0
1
Overrun Error
L
L
0
I
Framing Error
L
0
L
J
I
L
1
1
Break
0
1
1 Operation
I STB Full
I STB Empty
I
I
I
Operation
SRB Empty
SRB Full
I
1
1
1
I
1
Error Occurred
1
\
I
I Operation
I No Error
1 Error Occurred
1
I
1
1 Operation
1No Error
1
1
1 Operation
I No Error
I
\ Error Occurred
\
Operation
1
I Normal Reception I
1 Break Detected 1
I
83-0018328
47
NEe
pPD70208 (V40)
Figure 25.
SCM and SMD Registers
SCM Register
4
SCM
I -
I
-
IMRDVI·ECL ISBRKI RE
1 - I
o
TE
I
Transmitter Enabled
I
Operation
0
Transmitter Disabled
1
Transmitter Enabled
Receiver Enabled
0
1
Send Break
I
Operation
Receiver Disabled
Receiver Enabled
0
Operation
Normal Operation
1
TxD
= 0 (Break)
Error Clear
I
Operation
0
No Operation
1
Error Flag Clear
MRDY
Mask Ready
= 1 (Mask)
0
SRDY
1
Normal Operation .of
SFi'ilY Output
SMD Register
SMD
I
STL
I
PS
I
CL
J
BF
L
Baud Rate Factor
010
11
Operation
Illegal
RTCLK Frequency + 16
RTCLK Frequency + 64
Character Length
0-
Operation
Illegal
10
7 Bit Characters
11
8 Bit Characters
Parity Select
Operation
-0
No Parity
01
Odd Parity
Even Parity
11
Stop Bit Length
Operation
Illegal
-0
01
1 Stop Bit
11
2 Stop Bits
83-0018368
48
NEe
Figure 26.
pPD70208 (V40)
The ICU has the fellewing features.
SIMK Register
4
3
2
• Eight interrupt request inputs
• Cascadable with JlPD71059 Interrupt Centrollers
• Pregrammable edge- er level-triggered interrupts
(TCU, edge-triggered interrupts enly)
• Individually maskable interrupt reql,lests
• Pregrammable interrupt request prierity
• Pelling mede
0
eperation
o
Unmask
1
Mask
o
Unmask
1
Mask
leu Registers
Use I/O instructiens to. the I/O addresses selected by
the OPHA and IULA registers to read from and write to
the ICU registers. Address bit Ao and the cemmand
word selects an ICU internal register.
83-002736A
Interrupt Control Unit
The interrupt centrel unit (ICU) is a pregrammable
interrupt centreller equivalent to. the JlPD71059. The
ICU arbitrates up to. eight interrupt inputs, generates a
CPU interrupt request, and eutputs the interrupt vecter
number en the internal data bus during an interrupt
acknowledge cycle. Cascading up to. seven external
slave JlPD71059s permits the JlPD70208 to. suppert up
to. 56 interrupt seurces. Figure 27 is the bleck diagram
fer the ICU.
Read
AO
Other Condition
Operation
0
0
0
IMD selects IRQ
IMD selects liS
Polling phase
CPU - IRQ data
CPU -liS data
CPU - Polling data
D4= 1
D4 = 0 and D3 = 0
D4 = 0 and D3 = 1
CPU
CPU
CPU
-+
During initialization
CPU
CPU
CPU
CPU
-+
1
Write
0
0
0
CPU -IMKW
After initialization
IIW1
IPFW
-+ IMDW
-+
IIW2
IIW3
-+ IIW4
-+ IMKW
-+
Note:
(1)
Figure 27.
I:R
______-------'---~ a:I
In polling phase. polling data has priority. over the contents of
the IRQ or liS register when read.
leu Block Diagram
SAO}
{_A8
SAl To BIU" - A g
SA2
Read/Write
Control
--..oA10
t----INTAK (from CPU)
1 - - - - INT (to CPU)
J1
'..
Priority
Determination
Logic
INTo
INT 1
InInterrupt
service
Request
Register 1 4 - - - - - 1 - - - - + 1 Register
(liS)
(IRQ)
Interrupt
Mask
Register
(IMK)
INT 2•
.
TeUTO (from TCU)
SINT (from SCU)
TeUT1 (from TCU)
Mux
INTPl
Mux
INTP2
INT3
olNTP3
INT4
INTs
olNTP4
olNTPs
INTs
olNTPs
INT7
olNTP7
External Pins
83-0018378
49
NEe
pPD70208 (V40)
Initializing the ICU
The ICU is always used to service maskable interrupts
in a J.lPD70208 system. Prior to accepting maskable
interrupts, the ICU must first be initialized (figure 28).
Following initialization, command words from the CPU
can change the interrupt request priorities, mask/unmask interrupt requests, and select the polling mode.
Figures 29 and 30 list the ICU initialization and command words.
Interrupt initialization words 1-4 (IIW1-IIW4) initialize
the ICU, indicate whether external J.lPD71059s are
connected as slaves, select the base interrupt vector,
and select edge- or level-triggered inputs for INT1INT7. Interrupt sources from the TCU are fixed as
edge-triggering. INTO is internally connected to
TOUTO, and INT2 may be connected to TOUT1 by the
IRSW field in the OPCN.
slave J.lPD71059 INT output is routed to one of the
J.lPD70208 INTP inputs. During the second interrupt
acknowledge bus cycle, the ICU places the slave
address on address lines A10-Aa. Each slave compares this address with the slave address programmed
using interrupt initialization word 3 (1IW3).lf the same,
the slave will place the interrupt vector on pins ADr
ADo during the second interrupt acknowledge bus
cycle.
Figure 29.
Interrupt Initialization Words 1-4
07
IIW1
I -
06
I
-
05
I -
04
03
1
I
lr
I
1
~I Single Mode
~
IIW4 Not Required
I
Mode
0
I Extended Mode (Slave Controllers)
1
1Single Mode (No Slave Controllers) I
Level-Triggered
Mode
Mode
Edge Trigger (RiSing Edge)
Level Trigger (Active High)
0
Higher 5 bits of interrupt
vector number
IIW3
To increase the number of maskable interrupts, up to
seven slave J.lPD71059 Interrupt Controllers can be
cascaded. During cascade operation (figure 31), each
I
S7
I
S6
I
S5 I S4 I S3 I S2
lE'"
Initialization Sequence
I
I
SNGL=O, 114=1
I
I
IIW2
Ao=1
SNGL=O, 114=0
I
I
IIW4
SNGL=I, 114=1
SNGL=I, 114=0
I
I l
I L
IIW3
Ao-1
IIW4
I
I o
I
o
I
o
IEXTNI
I
I
I
I
I
llnltlalization
Completed
IIW4
Ao-1
I
.I
-
I
I
83-003821 A
-
0
INTn is not a slave
input
1
INTn is a slave input
I -
~
L
I
I
I
Ao=1
I
o
Status
C"oKIi"
Status
IIWI
I Bits SNGL and 114 are set.
lAo = 0,04 = 11 The default Initialization
I
Is performed.
I
I
SI I
~
I
IIW3
I
I
IIW4 Required
1
I1PD71059 Cascade Connection
Ao-1
I
Operation
I
0
00
I I
Writes IIW4 I
The initialization words' are written in consecutive
order starting with IIW1. IIW2 sets the interrupt vector.
IIW3 specifies which interrupts are connected to slaves.
IIW3 is only required in extended systems. The ICU will
only expect to receive IIW3 if SNGL = 0 (bit 01 of IIW1).
IIW4 is only written if 114 = 1 (bit Do of IIW1).
I
I
01
ISNGL.i 114
I
The interrupt mask word (IMKW) 'contains programmable mask bits for each of the eight interrupt inputs.
The interrupt priority and finish word (IPFW) is used by
the interrupt handler to terminate processing of an
interrupt or change interrupt priorities. The interrupt
mode word (IMDW) selects the polling register, interrupt request (IRQ) or interrupt in service (liS) register,
and the nesting mode.
Figure 28.
02
LEV I -
I SFI I
1
I
I
Self Finish
Interrupt
Operation
0
FI Command Mode
1
Self Finish Mode
External
Nesting Mode
0
1
Mode
Normal Nesting
Extended Nesting
83-0027268
50
NEe
Figure 30.
pPD70208 (V40)
Command Words
Interrupt Request Mask
Operation
INTn not Masked
INTn Masked
IPFW
I RP
Sil
oI
FI
0
Il2
1L1 IlO
I
+ + +
Interrupt
level
Rotate Priority
Specify Interrupt level,
Finish Interrupt
Commands
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
0
0
1
D6
IMDW
I-
I SNM IEXCNI
0
0
0
0
0
INTO
0
0
1
INT1
0
1
0
INT2
0
1
1
1
INT3
0
0
INT4
1
0
1
INT5
1
1
1
0
INT6
1
1
INT7
No Rotation
No level
Specification Rotation
FI
Command
No Rotation
FI Command
for Specification
Rotation
Specified Bit
level
Rotation FI Command
Specification
No Rotation No Operation
Non·FI
Command
No level
Specification
0
Normal FI Command
Normal Rotation
FI Command
0
Rotation
Specified Bit
Rotation Command
No Rotation
Sell FI Mode
Rotation Reset
Rotation
Sell FI Mode
Rotation Set
DO
0
I
1
I POL I SR IISJlR
I
Select Register
to Read
0
-
1
0
1
1
Polling Mode
I
No Operation
IRQ Selection
liS Selection
Polling
0
No Operation
1
Polling Command
Set Nesting
Mode
Read Register Selection
In-Service/Request Register
Select
Exceptional
Nesting Mode
I
Nesting Mode 2
0
-
1
0
Exceptional Nesting Mode Release
1
1
Exceptional Nesting Mode Set
No Operation
83-001835C
51
NEe
pPD70208 (V40)
Figure 31.
pPD71059 Cascade Connection
~D702081
I
ASTB
Address
A19/PS3·A1S/PSo I - - Latches/ LA1
A1S-AS I - - Buffers
~S
AD7·ADo
r
",PD71059
D7-DO
'--
lORD
10WR
Ao
RD
WR
INT
INTAK
INTPn
INTAK
INTPo
INTP1
INTP2
INTP 3
INTP4
INTPs
INTPs
INTP7
-
' - - - SA2·SAo
LA - Latched Address
BA - Buffered Address
83-002739A
DMA Control Unit
Terminal Count
The DMA Control Unit (DMAU) is a high-speed DMA
controller compatible with the pPD71071 DMA Controller. The DMAU has four independent DMAchannels
and performs high-speed data transfers between
memory and external peripheral devices at speeds as
high as 2 megabytes/second in an 8-MHz system.
Figure 32 is the block diagram for the DMAU.
The DMAU ends DMA service when the terminal count
condition is generated or when the END input is
asserted. A terminal count (TC) is produced when the
contents of the current count register becomes zero. If
autoinitialization is not enabled when DMA service
terminates, the mask bit of the channel is set and the
DMARQ input of that channel is masked. Otherwise,
the current count and address registers are reloaded
from the base registers and new DMA transfers are
again enabled.
The DMAU has the following features.
•
•
•
•
•
•
•
•
•
•
•
Four independent DMA channels
Cascade mode for slave pPD71071 DMA controllers
20-bit address registers
16-bit transfer count registers
Single, demand, and block transfer modes
Bus release and bus hold modes
Autoinitialization
Address increment/decrement
Fixed/rotating channel priorities
TC output at transfer end
Forced termination of service by END input
DMAU Basic Operation
The DMAU operates in either a slave or master mode.
In the slave mode, the DMAU samples the four DMARQ
input pins every clock. If one or more inputs are active,
the corresponding DMA request bits are set and the
DMAU sends a bus request to the BAU while continuing
to sample the DMA request inputs. After the BAU
returns the DMA bus acknowledge signal, the DMAU
stops DMA request sampling, selects the DMA channel
with the highest priority, and enters the bus master
mode to perform the DMA transfer. While in the bus
master mode, the DMAU controls the external bus and
performs DMA transfers based on the preprogrammed
channel information.
52
DMA Transfer Type
The type of transfer the DMAU performs depends on
the following conditions.
• Direction of the transfer (each channel)
• Transfer mode (each channel)
• Bus mode
Transfer Direction
All DMA transfers use memory as a reference point.
Therefore, a DMA read operation transfers data from
memory to an I/O port. A DMA write operation reads an
I/O port and writes the data into memory. During
memory-to-I/O transfer, the DMA mode (DMD) register
is used to select the transfer directions for each
channel and activate the appropriate control signals.
Operation
Transfer Direction
Activated Signals
DMA read
Memory -I/O
10WR, MRD
DMA write
I/O -
DMA verify
Memory
lORD, MWR
Addresses only; no transfer
performed
NEe
Figure 32.
pPD70208 (V40)
DMAU Block Diagram
DMAU Address Bus (20)
Internal Address Bus
Internal Bus
Interface
Address
Register
Internal Data Bus
I Current Address (20x4) I
Control Register Group
Base Address (20x4)
Internal Control Bus
Channel (4)
Device Control (10)
BUSRQ
BAU { BUSAK
Status (8)
DMAU Data Bus
Mode Control (7x4)
Count
Register
DMARQ3-0
I
Base Count (16x4)
Mask (4)
Current Count (16x4)
Priority Control
DMAAK3-0
Terminal Count
END/TC
Bus Mode
83-001830B
Figure 33.
The DMA device control (DDC) register selects operation in either the bus release or bus hold mode. The
selected bus mode determines the DMAU conditions
for return of the bus to the BAU. Figure 33 shows that in
bus release mode, only a single channel is serviced
after the DMAU obtains the bus. When DMA service
ends (termination conditions depend on the transfer
mode), the DMAU returns the bus to the BAU regardless
of the state of other DMA requests, and the DMAU
reenters the slave mode. When the DMAU regains use
of the bus, a new DMA operation can begin.
In bus hold mode, several channels can receive contiguous service without releasing the bus. If there is
another valid DMA request when a channel's DMA
service is finished, the new DMA service can begin
immediately after the previous service without returning the bus to the BAU.
Bus Modes
Bus Release Mode
Right to Use
Bus
Service
Channel
CPU
DMAU
L.JLJULJ
CHO CH1
CH2 CH3
Bus Hold Mode
Right to Use
Bus
Service
Channel
CPU
DMAU
~
CHO:CH1 !cH21cH3
I
,
I
83-001864A
Transfer Modes
The DMD register also selects either single, demand,
or block transfer mode for each channel. The conditions
for the termination of each transfer characterize each
transfer mode. The following table shows the various
transfer modes and termination conditions.
Transfer Mode
Termination Conditions
Single
After each byte/word transfer
Demand
END input
Terminal count
Inactive DMARQ
DMARQ of a higher priority channel
becomes active (bus hold mode)
Block
END input
Terminal count
53
NEe
pPD70208 (V40)
The operation of single, demand, and block mode
transfers depends on whether the DMAU is in bus
release or bus hold mode. Figure 34 shows the operation flow for the six possible transfer and bus mode
operations in DMA transfer.
Single-Mode Transfer. I n bus release mode, when a
channel completes transfer of a single byte, the DMAU
enters the slave mode regardless of the state of DMA
request inputs. I n this manner, other lower-priority bus
masters will be able to access the bus.
In bus hold mode, when a channel completes transfer
of a single byte, the DMAU terminates the channel's
service even if the DMARQ request signal is asserted.
The DMAU will then service any other requesting
channel. If there are no requests from any other DMA
channels, the DMAU releases the bus and enters the
slave state.
Demand-Mode Transfer. In bus release mode, the
currently active channel continues to transfer data as
long as the DMA request of that channel is active, even
though other DMA channels are issuing higher-priority
requests. When the DMA request of the serviced
channel becomes inactive, the DMAU releases the bus
and enters the slave state.
I n bus hold mode, when the active channel completes a
single transfer, the DMAU checks the other DMA
request lines without ending the current service. If
there is a higher-priority DMA request, the DMAU
stops the service of the current channel and starts
servicing the highest-priority channel requesting service. If there is no higher request than the current one,
the DMAU continues to service the currently active
channel. Lower-priority DMA requests are honored
without releasing the bus after the current channel
service is complete.
Block-Mode Transfer. In bus release mode, the current
channel continues DMA transfers until a terminal
count or the external END input becomes active.
During this time, the DMAU ignores all other DMA
requests. After completion of the block transfer, the
DMAU releases the bus and enters the slave state, even
if DMA requests from other channels are active.
In bus hold mode, the current channel transfers data
until an internal or external END Signal becomes
active. When the service is complete, the DMAU
checks all DMA requests without releasing the bus. If
there is an active request, the DMAU immediately
begins servicing the request. The DMAU releases the
bus after it honors all DMA requests or a higher-priority
bus master requests the bus.
54
Byte Transfer
The DMD register can specify only byte DMA transfers
for each channel. Depending on the mode selected, the
address register can either increment or decrement,
whereas the count register is always decremented.
Autoinitialize
When the DMD register selects autoinitialize for a
channel, the DMAU automatically reinitializes the address and count registers when END is asserted or the
terminal count condition is reached. The contents of
the base address and base count registers are transferred to the current address and current count registers,
and the applicable bit of the mask register remains
cleared.
Channel Priority
Each of the four DMAU channels is aSSigned a priority.
When multiple DMA requests from several channels
occur simultaneously, the channel with the highest
priority will be serviced first. The DDC register selects
one of two priority schemes: fixed or rotating (figure
35). In fixed priority, channel 0 is assigned the highest
priority and channel 3, the lowest. In rotating priority,
priority order is rotated after each service so that the
channel last serviced receives the lowest priority. This
method prevents the exclusive servicing of higherpriority channels and the lockout of lower-priority
DMA channels.
NEe
Figure 34.
pPD70208 (V40)
Transfer Modes
Bus Mode
Bus Release
Bus Hold
Transfer Mode
Single
Demand
Block
83-001856C
55
~EC
pPD70208 (V40)
Cascade Connection
Slave pPD71071 DMA Controllers can be cascaded to
easily expand the system DMA channel capacity to 16
DMA channels. Figure 36 shows an example of cascade
connection. During cascade operation, the DMAU acts
as a mediator between the BAU and the slave
pPD71071 s. During DMA cascade mode operation, it
is the responsibility of external logic to isolate the
cascade bus master from the pPD70208 control
outputs. These outputs are listed in a table at the front
of this data sheet.
Figure 35.
The DMAU always operates in the bus hold mode while
a cascade channel is in service, even when the bus
release mode is programmed. Other DMA requests are
held pending while a slave pPD71071 channel is in'
service. When the cascaded pPD71071 ends service
and moves into the slave state, the DMAU also moves
to the slave state and releases the bus. At this time, all
bits of the DMAU request register are cleared. The
DMAU cont'inues to operate normally with the other
noncascaded channels.
Priority Order
Highest
Fixed Priority
Highest
Rotating Priority
Highest
CH1 Service
Lowest
83-003819B
Figure 36.
pPD71071 Cascade Example
DMA1
..
DMA2
DMA3
I
DMAAK
C......
Channel
DMARQ
~
--
HLDAK
..
HLDRQ
DMA4
~
DMA5
DMAU
(Master)
..
..
-""
DMA6
--'"
DMA7
fLPD71 071
(Slave)
83-001857B
56
NEe
pPD70208 (V40)
Bus Waiting Operation
DMAU Registers
The DMAU will automatically perform a bus waiting
operation (figure 37) whenever the RCU refresh request
queue fills. When the DMA bus acknowledge goes
inactive, the DMAU enters the bus waiting mode and
inactivates the DMA bus request signal. Control of the
bus is then transferred to the higher-priority RCU by
the BAU.
Initialize. The DMA initialize command (DICM) register
(figure 38) is used to perform a software reset of the
DMAU. The DICM is accessed using the byte OUT
instruction.
Two clocks later, the DMAU reasserts its internal DMA
bus request. The bus waiting mode is continued until
the DMA bus acknowledge signal again becomes
active and the interrupted DMA service is immediately
restarted.
Programming the DMAU
To prepare a channel for DMA transfer, the following
characteristics must be programmed.
•
•
•
•
Starting address for the transfer
Transfer count
DMA operating mode
Transfer size (byte/word)
The contents of the OPHA and DULA registers determine the base I/O port address of the DMAU. Addresses
A3-AO are used to select a particular register as follow:
Register
Operation
0
0
1
1
Ao
0
1
0
1
DICM
DCH
DBC/DCC (low)
DBC/DCC (high)
Write
Read/Write
Read/Write
Read/Write
1
1
1
1
0
0
1
1
0
1
0
1
DBA/DCA (low)
DBA/DCA (high)
DBA/DCA (upper)
Reserved
Read/Write
Read/Write
Read/Write
0
0
0
0
0
0
1
1
0
1
0
1
DDC (low)
DDC (high)
DMD
DST
Read/Write
Read/Write
Read/Write
Read
0
0
1
1
0
1
0
1
Reserved
Reserved
Reserved
DMK
Read/Write
A3
A2
Al
0
0
0
0
0
0
0
0
0
0
0
0
Channel Register. Writes to the DMA channel (DCH)
register (figure 39) select one of the four DMA
channels for programming and also the base/current
registers. Reads of the DCH register return the currently-selected channel and the register access mode.
Count Registers. When. bit 2 of the DCH register is
cleared, a write to the DMA count register updates both
the DMA base count (DBC) and the DMA current count
(DCC) registers with a new count. If bit 2 of the DCH
register is set, a write to the DMA count register affects
only the DBC register. The DBC register holds the
initial count value until a new count is specified. If
autoinitialization is enabled, this value is transferred to
the DCC register when a terminal count or END
condition occurs. For each DMA transfer, the current
count register is decremented by one. The format of
the DMA count register is shown below. The count
value loaded into the DBC/DCC registers is one less
than the desired transfer count.
2H, IN/OUT
7
o
Co
7
DBC/DCC
DBA/DCA (higher/lower only)
DDC
o
Cg
Ca
Address Register. Use either byte or word I/O instructions with the lower two bytes (4H and 5H) of the
DMA address register. However, byte I/O instructions
must be used to access the high-order byte (6H) of this
register. When bit 2 of the channel register is cleared, a
write to the DMA address register updates both the
DMA base address (DBA) and the DMA current address
(DCA) registers with the new address. If bit 2 of the
DCH register is set, a writeto the DMA address register
affects only the DBA register.
7
Word I/O instructions can be used to read/write the
register pairs listed below. All other registers are
accessed via byte I/O instructions.
3H, IN/OUT
4H, IN/OUT
o
Ao
7
5H, IN/OUT
o
7
6H, IN/OUT (Byte only)
0
F.7
~
1:.:1
NEe
pPD70208 (V40)
The DBA register holds the starting address value until
a new address is specified. This value is transferred to
the DCA register automatically if auto'initialization is
selected. For each DMA transfer, the current address
register is increment~d/decremented by one.
Status Register. The DMA status (DST) register (figure
41) contains information about the current state of
each DMA channel. Software can determine if a termination condition has been reached (TC3-TCo) or if a
DMA service request is present (RQ3-RQO). The byte
IN instruction must be used to read this register.
Device Control Register. The DMA device control
(DOC) register (figure 40) is used to to p'rogram the
DMA transfer characteristics common to. all DMA
channels. It controls the bus mode, write timing,
priority logic, and enable/disable of the DMAU.
Figure 37.
Bus Waiting Operation
Other
Bus Master
DMARO
DMA BUSAK
RCU
DMAU
DMAU
-.l
-.l
I
\
Approx 2 Clocks
I~
Other
Bus Master
'----'----
-I
DMA BUSRO
83-0018588
Figure 38.
DMA Initialize Command Register
Initialize
7
OH
I
3
I
0
Note:
[1] The DMAU initializes as follows:
Register
Initialization Operation
Initialize
Address
Count
Channel
Mode Control
Device Control
Status
Mask
Clears all bits
No change
No change
SeleCts channel 0
Clears all bits
Clears all bits
Clears all bits
Sets all bits [masks all channels]
83-0018598
NEe
Figure 39.
pPD70208 (V40)
DMA Channel Register
Channel Register Read
6
7
o
3
4
I - I - I - I BASE I SEL3 I SEL2 I SEL1 I SELo
1H
IN
(Byte only)
J
0001
I
Selected
Channel
Channel 0
0010
Channel 1
0100
Channel 2
1000
Channel 3
0
Current (read), Base
and Current (write)
1
Base (read/write)
Base Only
Channel Register Write
6
7
1H
4
3
1-1-1 - I - 1 - 1BASE 1
OUT (Byte only)
SELCH
L
Select
Channel
Channel 0
00
01
Channel 1
10
Channel 2
11
Channel 3
0
Select Current (read),
select both Base and
Current (write)
1
Select Base (read/write)
Base Only
83-0038208
Figure 40.
DMA Device Control Register
7
5
4
2
.
Disable DMA
Operation(1)
I
Priority
I
Extended
Writing(2)
0
Enable
1
Disable
Fixed
0
1
0
Rotational
Normal
1
Extended
o
9H
1 - 1 - 1 -1-1 - 1 - I WEV 1BHLD
IN/OUT
L
Bus Mode
Wait Enable
During Verify(3
0
Bus Release
1
Bus Hold
0
Disable
1
Enable
Note:
[1 J Disables BUSRQ to the BAU to prevent incorrect DMA
operation while the DMAU registers are being initialized
or modified.
[2] When EXW is 0, the write signal becomes active [normal
writeJ during T3 and TW [see timing waveformsJ. When 1,
the write Signal becomes active during T2, T3, and TW [like
the read signalJ.
[3J Wait states are generated by the READY signal during a
verify transfer.
83-0018638
pPD70208 (V40)
Mode Control Register. The DMA mode (DMD) register
(figure 42) selects the operating mode for each DMA
channel. The DCH register selects which DMD register
will be accessed. A byte IN/OUT instruction must be
used to access this register.
Figure 41.
Mask Register Read/Write. The DMA mask (DMK)
register (figure 43) allows software to individually
enable and disable DMA channels. The DMK register
can only be accessed via byte I/O instructions.
DMA Status Register
7
4
6
I R03 I R02
OBH
R01·1 ROo
o
2
I
TC3
I TC2 I
TC1
I TCo
IN
I
(Byte only)
Terminal
Count
DMA
Request
0
Not ended (for each read)
1
0
END or terminal
count
No DMA request active
1
DMA request active
83-0018608
Figure 42.
DMA Mode Register
7
OAH
I
4
TMODE
1ADIR 1AUTI 1
o
2
3
1 -I -
TDIR
L~
Transfer
Direction
00
01
10
Verify
I/O-to-memory
Memory-to-I/O
11
Not allowed
0
Disable
Address
Direction
1
0
1
00
Enable
Increment
Decrement
Demand
Transfer
Mode
01
10
11
Block
Cascade
Autoinitialize
Single
83-002734B
Figure 43.
DMA Mask Register
76543210
OFH
I - I - I - I. - I
M3
l
I
M2
I
M1
I
MO
I INIOUT
(Byte only)
J
IL....-__- fl
I
OMARa
Mask
I 0 I Not masked I
I 1 I Masked
I
83-0038298
NEe
pPD70208 (V40)
Reset
Output Pin Status
The falling edge of the RESET signal resets the
The following table lists output pin status during reset.
pPD70208. The signal must be held low for at least four
clock cycles to be recognized as valid.
Signal
Status
High level
CPU Reset State
Register
Reset Value
PFP
PC
PS
OOOOH
OOOOH
FFFFH
INT AK.JllifEJillU.£.R/JL _
MRD, MWR, END/TC, 10WR, lORD,
REFRQ, BS~BSo, :USLOCK,
RESOUT, D AAK -DMAAKO
QS1-QSO, ASTB, HLDAK
Low level
SS
DSO
DS1
OOOOH
OOOOH
OOOOH
A15-Aa
High or low level
AD7-ADO
High impedance
PSW
AW, BW, CW, DW,
IX, IV, BP, SP
F002H
Undefined
_CL_K_O_UT_____________________
Co_n_ti_nu_e_s_to_s_u_pp_ly_c_lo_C_k__
Instruction queue
Cleared
When RESET returns to the high level, the CPU will
start fetching instructions from physical address
FFFFOH.
Internal Peripheral Registers
Internal peripheral devices initialized on reset are
listed in the following table. 1/0 devices not listed are
not initialized on reset and must be initialized by
software.
System
I/O area
SCU
DMAU
Symbols: x
Register
Reset Value
OPCN
OPSEL
WCV1
----0000
----0000
11111111
WCV2
WMB
TCKS
RFC
- - - -1111
-111-111
---00000
x--01000
SMD
SCM
SIMK
01001011
--0000-0
- - - - - -11
SST
DCH
DMD
10000100
---00001
000000-0
DDC (low)
DDC (high)
DST
--00-0-------00
xxxxOOOO
DMK
----1111
= unaffected; 0 = cleared; 1 = set; (-) = unused.
~
NEe
J.lPD70208 (V40)
Instruction Set
Symbols
Symbols
Symbol
Meaning
mem8
8-bit memory location
Preceding the instruction set, several tables explain
symbols, abbreviations, and codes.
Clocks
In the Clocks column ofthe instruction set, the numbers
cover these operations: instruction decoding, effective
address calculation, operand fetch, and instruction
execution.
Clock timings assume the instruction has been prefetched and is present in the four-byte instruction
queue. Otherwise, add four clocks for each byte not
present.
For instructions that reference memory operands, the
number on the left side of the slash (I) is for byte
operands and the number on the right side is for word
operands.
For conditional control transfer or branch instructions,
the number on the left side of the slash is applicable if
the transfer or branch takes place. The number on the
right side is applicable if it does not take place.
mem16
16-bit memory location
mem32
32-bit memory location
memptr16
Word containing the destination address
within the current segment
memptr32
Double word containing a destination
address in another segment
mod
Mode field (00 to 10)
near..Jabel
Label within the current segment
near--proc
Procedure within the current segment
offset
Immediate offset data (16 bits)
Number of bytes to discard from the stack
reg
Register field (000 to 111);
8- or 16-bit general-purpose register
reg8
8-bit general-purpose register
reg16
16-bit general-purpose register
regptr
16-bit register containing a destination
address within the current segment
regptr16
Register containing a destination address
within the current segment
If a range of numbers is given, the execution time
depends on the operands involved.
seg
Immediate segment data (16 bits)
shorLiabel
Label between -128 and +127 bytes from
the end of the current instruction
Symbols
sr
Segment register
Symbol
Meaning
src
Source operand or address
acc
Accumulator (AW or AL)
temp
Temporary register (8/16/32 bits)
disp
Displacement (8 or 16 bits)
AC
Auxiliary carry flag
dmem
Direct memory address
AH
Accumulator (high byte)
dst
Destination operand or address
AL
Accumulator (low byte)
ext-disp8
16-bit displacement (sign-extension byte
+ 8-bit displacement)
AW
Accumulator (16 bits)
BW register (high byte)
Label within a different program
segment
BH
BL
BW register (low byte)
Procedure within a different program
segment
BP
BP register
BRK
Break flag
Floating point instruction operation
BW
BW register (16 bits)
imm
8- or 16-bit immediate operand
CH
CW register (high byte)
imm3/4
3- or 4-bit immediate bit offset
CL
CW register (low byte)
imm8
8-bit immediate operand
CW
CW register (16 bits)
imm16
16-bit immediate operand
Carry flag
mem
Memory field (000 to 111);
8- or 16-bit memory location
CY
DH
DlR
Direction flag
DL
OW register (low byte)
far_label
far-proc
OW register (high byte)
NEe
pPD70208(V40)
Symbols (cont)
Flag Operations
Symbol
Meaning
Symbol
Meaning
DSO
Data segment 0 register (16 bits)
(blank)
No change
DS1
Data segment 1 register (16 bits)
o
Cleared to 0
DW
DW register (16 bits)
IE
Interrupt enable flag
x
Set or cleared according to result
IX
Index register (source) (16 bits)
IV
Index register (destination) (16 bits)
MD
Mode flag
Set to 1
Undefined
R
Restored to previous state
Memory Addressing Modes
P
Parity flag
PC
Program counter (16 bits)
mem
mod = 00
mod = 01
PS
Program segment register (16 bits)
000
BW+IX
BW + IX + disp8
BW + IX + disp16
PSW
Program status word (16 bits)
001
BW+IV
BW + IV + disp8
BW + IV + disp16
R
Register set
010
BP + IX
BP + IX + disp8
BP + IX + disp16
S
Sign extend operand field
S = 0 No sign extension
S = 1 Sign extend immediate byte
operand
011
BP+ IV
BP + IV + disp8
BP + IV + disp16
100
IX
IX + disp8
IX + disp16
101
IV
IV + disp8
IV + disp16
S
Sign flag
110
Direct
BP + disp8
BP + disp16
SP
Stack pointer (16 bits)
111
BW
BW + disp8
BW + disp16
SS
Stack segment register (16 bits)
v
Overflow flag
Register Selection (mod
=
mod = 10
11)
W
Word/byte field (0 to 1)
reg
W=O
W=1
X,XXX, VVV, ZZZ
Data to identify the instruction code of the
external floating point arithmetic chip
000
AL
AW
001
CL
CW
XOR
Exclusive logical sum
010
DL
DW
XXH
Two-digit hexadecimal value
011
BL
BW
100
AH
SP
101
CH
BP
110
DH
IX
111
BH
IV
XXXXH
Four-digit hexadecimal value
Z
Zero flag
Segment Register Selection
sr
Segment Register
00
DS1
01
PS
10
SS
11
DSO
1m
NEe
pPD70208 (V40)
Instruction Set
Mnemonic
Operand
6 5 4 3 2
0
Opcode
7 6 5 4 3 2 1 0
Clocks
Bytes
Flags
AC CY V P S Z
Data Transfer Instructions
MOV
reg, reg
0
0
0 1 W
mem, reg
0 0 0
0 0 W
reg
reg
mod
reg
mem
reg, mem
0 0 0 1 0
mem, imm
1 0 0 0
W
mod
reg
W
mod
reg
reg, imm
1 0
1 W
acc, dmem
1 0
0 0 0 0 W
dmem, acc
0
sr, reg16
0 0 0
sr, mem16
0 0 0
reg16, sr
0 0 0
mem16, sr
0 0 0 1
OSO, reg16, mem32
2
2-4
mem
10/14
2-4
mem
9/13
3-6
reg
0 0 0
W
3
mem
14
2-4
reg
2
2
mem
12
2-4
reg
mem
25
2-4
reg
mem
25
2-4
1
mod 0
sr
0 0
1 1 0
sr
0 0
mod 0
sr
0 0 0
0
mod
0 0
0
mod
2
1
PSW, AH
0 0
1 0
LOEA
reg16, mem16
0 0 0
0
TRANS
srctable
XCH
reg, reg
0 0 0 0
W
1 1
mem, reg
0 0 0 0
W
mod
0
x x
3
mod
reg
mem
4
reg
reg
3
2
reg
mem
13/21
2-4
0
0
3
2
reg
0 0
2-3
10/14
9/13
sr
OS1, reg16, mem32
1
4
2
1 1 0
AH, PSW
AW, reg16
2
7/11
x x x
2-4
9
0
reg
3
Repeat Prefixes
REPC
0
0 0
0
2
REPNC
0
0 0
0 0
2
REP
REPE
REPZ
2
0 0
REPNE
REPNZ
1 1 1 1 0 0 1 0
2
Block Transfer Instructions
o
oW
MOVBK
dst, src
1 0 1
CMPBK
dst, src
1 0 1 0 0 1 1 W
1
x x x x x x
7 (13) + 14n (W = 0)
7 (21) + 22n (W = 1)
CMPM
dst
1 0 1 0 1 1 1W
1
x x x x x x
7 (7) + 10n (W = 0) .
7(11)+14n(W=1)
LOM
src
1 0 1 0 1 1
STM
dst
1 0 1 0 1 0 1 W
0 1
oW
1
9 (9) + Bn (W = 0)
9 (17) + 16n (W = 1)
1
7 (7) + 9n (W = 0)
7 (11) + 13n (W = 1)
1
5 (5) + 4n (W = 0)
5 (9) + Bn (W = 1)
n = number of transfers
String instruction execution clocks for a single instruction execution are in parentheses.
CA
NEe
pPD70208 (V40)
Instruction Set (cont)
Mnemonic
Operand
6
Opcode
7 6 5 4 3 2 1 0
4 3
o
Clocks
Bytes
0 W
9/13
2
W
8/12
W
8/12
1 W
8/12
Flags
AC CY V P S Z
110 Instructions
IN
OUT
acc, imm8
0 0
acc, DW
0
imm8, acc
o
o
o
------------------------------------------------------------------------------DW, acc
INM
OUTM
dst, DW
o
DW, src
0
2
1
0 W
9 (10)
9 (18)
+ 8n (W = 0)
+ 16n (W = 1)
9 (10)
9 (18)
+ 8n
1 1 0 1 1 1 W
1
(W = 0)
1)
+ 16n (W =
n = number of transfers
String instruction execution clocks for a single instruction execution are in parentheses.
BCD Instructions
o
ADJBA
o
ADJ4A
xxuuuu
0
x x u x x x
3
ADJBS
xxuuuu
o
ADJ4S
ADD4S
SUB4S
dst, src
CMP4S
dst, src
ROL4
reg8
ROR4
x x u x x x
0
o
dst, src
o
o
o
o
o
o
o
0
1 1 1
mem
0 0 0
0 0 0
0 0 0 1
1 1 0 0 0
o
0 0 0 0
7 + 19n
2
uxuuux
uxuuux
000
7+ 19n
0 1 1 0
7 + 19n
2
0
o
o
000
13
3
o
0
o
000
25
3-5
0
uxuuux
reg
mem8
o
reg8
o
0 0 0 1 1 1 1
1 1 0 0 0
reg
o
0
o
o
o
17
3
mem8
o
o
0
o
o
o
29
3-5
15
2
u u u x x x
7
2
uuuxxx
2
x
x x x x x x
0 0 0
mod 0 0
0 0 0 1 1 1 1
mod 0 0 0 mem
n = number of BCD digits divided by 2
Data Type Conversion Instructions
CVTBD
1
CVTDB
1 1 0
0
CVTBW
0
CVTWL
o
o
0
0
0 0 0 0
o
0 0 0
o
o
o
o
000
2
o
4/5
0
Arithmetic Instructions
ADD
reg, reg
o
reg, mem
o
0 0 0 0 0 1 W
1 1
reg
reg
0 0 0 0 0 1 W
mod
reg
mem
o
o
o
0 0 0 0 S W
1 1 0 0 0
reg
0 0 0 0 S W
mod 0 0 0
mem
2
x
x
x
x x
------------------------------------------------------------------------------mem, reg
13/21
2-4
x x x x x x
o 0 0 0 0 0 0 W mod reg
mem
reg, imm
mem, imm
acc, imm
0 0 0
0 W
10/14
2-4
4
3-4
x x x x x x
15/23
3-6
x x x x x x
4
2-3
x x x x x x
65
NEe
pPD70208 (V40)
Instruction Set (cont)
Mnemonic
Operand
Opcode
7 6 5 4 3 2 1 0
o
6 5 432
Clocks
Bytes
2
2
Flags
AC CV V P S Z
Arithmetic Instructions (cont)
ADDC
reg, reg
0 0 0
0 0 1 W
reg
reg
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x
x x x x
x
x x x x
x
x x x x
x
x x x x
x
x x x x
x
x x x x
uxxuuu
uxxuuu
uxxuuu
uxxuuu
uxxuuu
uxxuuu
uxxuuu
uxxuuu
uuuuuu
uuuuuu
uuuuuu
uuuuuu
--------------------------------------------------------------------------~~
mem, reg
0 0 0
reg, mem
o
mem
0 0 1 0 0 1 W
mod
reg
mem
mem, imm
000
reg, reg
o
o
o
reg, mem
reg, imm
0 0 0 0 S WOO
0 0 0
3-6
2-3
2
2
0 0 W
mod
reg
mem
13/21
2-4
0
0 1 0 1 W
mod
reg
mem
10/14
2-4
o
0 0 0 0 S W
reg
mem
ace, imm
mem, reg
o
o
o
reg, mem
0
0
0 W
0 0
0 1 W
1 1
reg
reg
0 0
0 0 W
mod
reg
mem
0001
01W
mod
reg
mem
o
0 0 0 0 S W
1 1 0 1
reg
mem, imm
100000SW
mod 0 1
mem
ace, imm
000
regS
0 W
1
1 1
o
15/23
4
0
1 0 1
reg, reg
2-4
3-4
0
1 0 1
0
1 1 0 0 0
reg
W
mod 0 0 0
mem
reg
000
4
3-4
15/23
3-6
4
2-3
2
2
13/21
2-4
10/14
2-4
4
3-4
15/23
3-6
4
2-3
2
2
13/21
2-4
2
regS
1 1
1 1 0
1 1 0 0
reg
2
2
mem
1 1
1 1 W
mod 0 0
mem
13/21
2-4
reg
21-30
2
mem
26-39
2-4
2
o
o
o
o
o
o
reg
reg16,mem16,immS
reg16,reg16,imm16
reg16,mem16,imm16
reg
mem
reg
mem
o
o
o
o
reg
0 1
reg
reg16,reg16,immS
66
reg
10/14
4
0
mem
DIV
W
reg
2-4
0
mem
DIVU
mem
mod
reg16
MUL
0 1 0
13/21
0
mem
MULU
mod
010W
1 0 0 0 0 0 S W
reg16
DEC
S W
reg
mem, imm
reg, imm
INC
reg
ace, imm
mem, reg
SUBC
mod
o
o
reg, imm
SUB
0 0 0 W
o
o
2
1 W
1 1
0 0
1 1 W
mod
1 1 W
1 1
o
o
reg
33-47
1
mod
0
mem
3S-56
2-4
1 1
reg
reg
2S-34
3
W
0
0
mod
reg
mem
37-43
3-5
000
1 1
reg
reg
36-42
4
000
mod
reg
mem
45-51
4-6
reg
19-25
2
mem
24-34
2-4
reg
29-43
2
mem
34-52
2-4
0
o
o
o
o
W
1 1
0
W
mod
1 1 0
W
1 1
W
mod 1 1
NEe
pPD70208 (V40)
Instruction Set (cont)
Mnemonic
Operand
432
6
Opcode
7 6 5 4 3 2 1 0
o
Clocks
Bytes
Flags
AC CY V P S Z
2
2
x x x x x x
Comparison Instructions
CMP
reg, reg
0 0
0 1 W
reg, mem
0 0 1 1
0 1 W
reg
reg
---------------------------------------------------------------------------mem, reg
0 0
0 0 W mod
reg
mem
10/14
2-4
x x x x x x
mem, imm
ace, imm
mod
0 0 0 0 0 S W
reg, imm
o
0 0 0 0
S W mod
0
oW
reg
mem
10/14
2-4
x x x x x x
1 1 1
reg
4
3-4
x x x x x x
1 1 1
mem
12/16
3-6
x x x x x x
4
2-3
x x x x x x
2
2
Logica/lnstructions
NOT
reg
0
WOO
reg
~
=m=e=m========================o======w===m=od===O====0===m=e=m====13=/2=1===2=-4=================~
________
NEG
reg
0
W
reg, reg
o 0 0 0
0 W
mem, reg
o
0 W
reg
2
2
x x x x x x
---------------------------------------------------------------------------mem
1 1
0
1 W mod 0
mem
13/21
2-4
x x x x x x
TEST
0
o
reg, imm
mem, imm
AND
OR
XOR
~g
~g
2
2
u 0 0 x x x
reg
mem
9/13
2-4
u 0 0 x x x
o 0 0
reg
4
3-4
0 0 x x x
o 0 0
mem
10/14
3-6
0 0 x x x
4
2-3
0 0 x x x
mod
W
1
0 1 1 W
ace, imm
10
0100W
reg, reg
o
0001W
reg
reg
2
2
mem, reg
o
0 0 0 0 W
mod
reg
mem
13/21
2-4
u 0 0 x x x
reg, mem
0010001W
mod
reg
mem
10/14
2-4
u 0 0 x x x
reg
4
3-4
OOxxx
mod
1 0 0
mem
15/23
3-6
0 0 x x x
4
2-3
0 0 x x x
reg, imm
o
0 0 0 W
mem, imm
o
0 0 0 W
ace, imm
0010010W
reg, reg
0000
mem, reg
000
reg, mem
o
mod
o
01W
0
reg
reg
2
2
u 0 0 x x x
u 0 0 x x x
0 W
mod
reg
mem
13/21
2-4
u 0 0 x x x
0 1 0 1 W
mod
reg
mem
10/14
2-4
u 0 0 x x x
0 1
reg
4
3-4
uOOxxx
0 1
mem
15/23
3-6
0 0 x x x
4
2-3
reg, imm
OOOOOOW
mem, imm
OOOOOOW
mod
o
o
ace, imm
o
reg, reg
00
001W
mem, reg
o 0
0 0 0 W
mod
reg
mem
13/21
2-4
u 0 0 x x x
reg, mem
o 0 1 1 0 0 1 W
mod
reg
mem
10/14
2-4
u 0 0 x x x
reg
4
3-4
OOxxx
mod
1 1 0
mem
15/23
3-6
0 0 x x x
4
~3
0 0 x x x
reg, imm
0
1 1 0 W
reg
OOOOOOW
mem, imm
1 0
ace, imm
o 0
0 0 0 0 W
0
0 W
1 0
reg
2
0 0 x x x
u 0 0 x x x
67
twEC
pPD70208 (V40)
Instruction Set (cont)
Mnemonic
Operand
Opcode
0765432
65432
o
Flags
AC CV V P SZ
Clocks
Bytes
0 0
35-133
3
o
35-133
4
0
34-59
3
o
34-59
4
3
3
uOOuux
0 W
7/11
3-5
uOOuux
Bit Manipulation Instructions
INS
reg8, reg8
reg8, imm8
EXT
TEST1
SET1
reg
0000111100
. 1 1 0 0 0
reg
NOT1
68
o
0
reg8, reg8
0000111100
1 1
reg
reg
reg8, imm8
0000111100
1 1 0 0 0
reg
reg, CL
00001111000
1 1 0 0 0
reg
o
mem, CL
00001111000
mod 0 0 0 mem
o
reg, imm3/4
000011'11000
1 1 0 0 0
reg
o
0 W
4
4
uOOuux
mem, imm3/4
00001111000
mod 0 0 0
mem
o
0 W
8/12
4-6
uOOuux
reg, CL
00001111000
1 1 0 0 0
reg
oW
4
3
mem, CL
00001111000
mod 0 0 0 mem
0 W
10/18
3-5
reg, imm3/4
00001111000
1 1 0 0 0
reg
5
4
mem, imm3/4
0000111100
mod 0 0 0 mem
11/19
4-6
o
CY
CLR1
o
d 0
000 0
1 1
reg
0
o
W
W
oW
0
DIR
1 1 1 1 1 1 0 1
reg, CL
00001111
1 1 0 0 0
reg
mem, CL
2
2
o
0
0
W
5
3
00001111000
mod 0 0 0 mem
o
W
11/19
3-5
reg, imm3/4
00001111000
1 1 0 0 0
reg
o
W
6
4
mem, imm3/4
00001111000
mod 0 0 0
mem
o
W
12/20
4-6
o
CY
1
0 0 0
2
DlR
1 1 1 1
1 0 0
2
1
reg, CL
o
0 0 0 1 1 1 1
1 1 0 0 0
reg
000
o
W
4
3
mem, CL
00001111
mod 0 0 0 mem
o
0
o
W
10/18
3-5
reg, imm3/4
00001111
1 1 0 0 0
reg
o
0
W
mem, imm3/4
00001111
mod 0 0 0
mem
0
W
CY
1 1
o
1 0 1
o
4
11/19
2
4-6
x
NEe
pPD70208 (V40)
Instruction Set (cont)
Mnemonic
Operands
Opcode
7 6 5 4 3 2 1 0
o
7 6 543 2
Clocks
Bytes
Flags
AC CY V P S Z
Shift/Rotate Instructions
SHL
reg, 1
0
0 0 0 WOO
reg
2
2
u x x x x x
----------------------------~-------------------------------------------------
SHR
mem, 1
0
0 0 0 W
mod
0 0
mem
13/21
2-4
u x x x x x
reg, CL
0
0 0
W
1 1
mem, CL
0 1 0 0 1 W
mod
0 0
reg
7+ n
2
u x u x x x
0 0
mem
16/24 + n
2-4
reg, immB
0 0 0 0 0 W
1 1
0
reg
u x u x x x
7+ n
3
u x u x x x
mem, immB
0 0
0 0 W
mod
0
mem
reg, 1
0
0 0 0 W
1 1
mem, 1
0
0 0 0 W
mod
0
mem
reg, CL
0
0 0 1 W
1 1
0
reg
reg, 1
0
reg
16/24 + n
3-5
u x u x x x
2
2
u x x x x x
13/21
2-4
u x x x x x
7+ n
2
u x u x x
u x 0 x x x
II
X
- - - - - - - , - - - u x u x x x
mem, CL
0 1 0 0 1 W
mod
mem
16/24 + n
2-4
reg, immB
0 0 0 0 0 W
1 1
0
reg
7+ n
3
u x u x x x
mem, immB
0 0 0
0 W
mod
0
mem
16/24 + n
3-5
u x u x x x
SHRA
mem, 1
ROL
ROR
ROLC
0 0 0 W
1 1
reg
2
2
0 0 0 W
mod
mem
13/21
2-4
u x 0 x x x
1 1
reg
7+ n
2
u x u x x x
reg, CL
0
0
W
mem, CL
0
0 0
W
reg, immB
0 0 0 0 0 W
mem, immB
reg, 1
mem, 1
mod
mem
1 1 1
1
reg
0 0 0 0 0 W
mod
1
mem
0
0 0 0 W
1 1 0 0 0
0
0
mod 0 0
reg, CL
0
0 0
W
1 1 0 0 0
reg
mem, CL
0 1 0 0 1 W
mod 0 0 0
mem
reg, imm
0 0 0 0 0 W
1 1 0 0 0
reg
mem, imm
0 0 0
0 W
mod 0 0 0
mem
reg, 1
0
0 W
1 1 0
reg
0
0 W
1
mem, 1
0
0 0 0 W
mod
reg, CL
0
0
1 1 0 0
mem, CL
0 1 0 0 1 W
mod
W
reg
mem
0
0 0
2-4
u x u x x x
3
u x u x x x
u x u x x x
16/24 + n
3-5
2
2
13/21
2-4
7+ n
x x
x x
x u
16/24 + n
2-4
x u
7+ n
3
x u
16/24 + n
3-5
x u
2
2
x u
mem
13/21
2-4
x x
reg
7+n
16/24 + n
2-4
x u
mem
x u
7+ n
3
x u
16/24 + n
3-5
x u
2
2.
mem
13/21
2-4
x x
x x
0
reg
7+ n
2
x u
0
mem
16/24 + n
2-4
x u
1 1 0
0
reg
7+ n
3
x u
mod 0
0
mem
16/24 + n
3-5
x u
reg, immB
0 0 0 0 0 W
1 1 0 0
reg
mem, immB
0 0 0
mod 0 0
mern
reg, 1
0
0 0 0
iN
1 1 0
0
reg
mem, 1
0
0 0 0 W
mod 0
0
reg, CL
0
0 0
W
1 1 0
mem, CL
0 1 0 0
W
mod 0
reg, immB
0 0 0 0 0 W
mem, immB
0 0 0 0 0 W
0 W
16/24 + n
7+ n
n = number of shifts
69
NEe
pPD7020'8 (V40)
Instruction Set (cont)
Mnemonic
Opcode
7 6 5 4 3 2 1 0
o
6 543 2
Operands
Flags
AC CV V PS Z
Clocks
Bytes
reg
2
2
x x
0
reg
7+ n
2
0 l'
mem
16/24 + n
2-4
x u
x u
7+ n
3
x u
16/24 + n
3-5
x u
23
2-4
Shift Rotate Instructions (cont)
RORC
reg, 1
0
0 0 0 W
0
-------------------------------------------------------------------------mem, 1
0
0 0 0 W mod 0
mem
13/21
2-4
x x
reg, CL
0
mem, CL
o
W
0 0
1 0 0 1 W
mod
reg, immB
OOOOOW
0
reg
mem, immB
o
0
mem
0 0 0 0 W mod
n = number of shifts
Stack Manipulation Instructions
PUSH
mem16
1
sr
0 0 0
o
PSW
POP
sr
mod
1 1 0
mem
1 0
0
10
01100000
imm
o
mem16
1 0 0 0
reg16
o
o
65
1 1 0 1 0 S 0
mod 0 0 0
1 0
0 0
PSW
1 0
R
o
sr
mem
2-4
1 1
12
R R R R R R
12
75
0 0 0
*immB =0: 16
immB> 1 : 21 + 16 (immB - 1)
DISPOSE
2-3
25
12
1 1 0
0
9-10
reg
100001
o
imm16, immB
10
0
R
sr
PREPARE
1 1 1 1 1 1
-------------------------------------------------------------------------reg16
0 1 0 1 0
reg
10
o
0 1
0
0 0 0
*
4
10
Control Transfer Instructions
CALL
near_proe
20
3
--------------------------------~----------------------------------------
regptr
l '1 1 0
memptr16
1 1
1
far_proe
0 0
0
memptr32
mod 0
1 1 1 1
o
o
o
o
RET
shorLiabel
70
31
mod 0
mem
2-4
29
5
47
2-4
19
24
o
o
o
1
29
1 0
32
3
0
13
3
0
0
o
1 1
1
o
o
mem
1
o
near-.label
0
0
memptr16
BV
BNV
1B
0 0 0
reg
memptr32
reg
0 0 0
o
o
BR
1
0
o
o
1 1
1
o
0 0 0
000
mod
mod
o
o
o
3
12
2
0
reg
11
2
0
mem
23
2-4
mem
15
5
34
2-4
14/4
2
14/4
2
NEe
pPD70208(V40)
Instruction Set (cont)
Mnemonic
Operands
Opcode
7 654321
0
5 4 3 2
0
Clocks
Bytes
Flags
AC CY V P
S Z
Control Transfer Instructions (cont)
BC, BL
near-1abel
0
0 0
14/4
2
BNC, BNL
near-1abel
0
0 0 1
14/4
2
BE, BZ
near-1abel
0
0
0 0
14/4
2
BNE, BNZ
near-1abel
0
0
0 1
14/4
2
BNH
near-1abel
0
0
0
14/4
2
BH
near-1abel
0
0 1
14/4
2
BN
near-1abel
0
0 0 0
14/4
2
BP
neaUabel
0
0 0
14/4
2
BPE
near-1abel
0
0
0
14/4
2
BPO
near-1abel
0
0
1
14/4
2
BLT
near-1abel
0
0 0
14/4
2
BGE
near-1abel
0
0 1
14/4
2
BLE
near-1abel
0
0
14/4
2
BGT
near-1abel
0
1
14/4
2
OBNZNE
near-1abel
0 0 0 0 0
14/5
2
OBNZE
near-1abel
0 0 0 0
14/5
2
OBNZ
near-1abel
0 0 0
0
13/5
2
BCWZ
near-1abel
0 0 0
1
13/5
2
0
1 1
Interrupt Instructions
BRK
BRKV
3
0 0
0 0
50
1
imm8
0 0
0 1
50
2
imm8
0 0 1
RETI
0
1
0 0 1 1
0 0 0
CHKINO
reg16, mem32
0
BRKEM
imm8
0 0 0 0
52/3
39
0
mod
reg
mem
R R R R R R
25/72-75 2-4
1 1 1 1 1 1 1 1
3
50
CPU Control Instructions
HALT
0
BUS LOCK
FP01
FP02
0 0
1
0 0 0 0
fp_op
0
X X X
fp_op, mem
0
1 X X X
2
2
1 1 Y Y y Z Z Z
2
mod y y y
14
2-4
2
2
14
2-4
mem
fp_op
0
0 0
X
1 1 Y Y Y Z Z Z
fp_op, mem
0 1 1 0 0
X
mod y y y
mem
POLL
0 0
0
n = number of times POLL pin is sampled.
NOP
0 0
0 0 0 0
01
1
EI
0
1
OSO:, OS1:, PS:, and SS:
(segment override prefixes)
0 0
0
seg
2
2+5n
3
2
0
1
2
0
2
8080 Instruction Set Enhancements
RETEM
CALLN
imm8
1
0
0
1
0
39
2
1
0
0
0
0
58
3
R R R R R R
pPD70208 (V40)
72
NEe
NEe
NEe Electronics Inc.
Description
The pPD70216 (V50™) is a high-performance, lowpower 16-bit microprocessor integrating a number of
commonly-used peripherals to dramatically reduce the
size of microprocessor systems. The CMOS construction makes the pPD70216 ideal for the design of
portable computers, instrum~ntation, and process
control equipment.
The pPD70216 contains a powerful instruction set that
is compatible with the pPD70108/pPD70116 (V20®/
V30®) and pPD8086/pPD8088 instruction sets. Instruction set support i.ncludes a wide range of arithmetic, logical, and control operations as well as bit
manipulation, BCD arithmetic, and high-speed block
transfer instructions. The pPD70216 can also execute
the entire pPD8080AF instruction set using the 8080
emulation mode. Also available is thepPD70208 (V40TM),
identical to the pPD70216 but with an 8-bit external
data bus.
pPD702i6 (V50)
i6-Bit Microprocessor:
High-Integration, CMOS
Ordering Information
Part Number
Max Frequency IMHzl
pPD70216R8
8
R10
V20 and V30 are registered trademarks of NEC Corporation.
V40 and V50 are trademarks of NEC Corporation.
10
GF8
8
GF10
10
68-pin PLCC
80-pin plastic QFP
Bottom View
/
000000000
00000000000
00
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pPD70216R
00
00
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00
00000000000
L 10
000000000
A2
8 MHz; 200 ns at 10 MHz
o
o
o
o
8
L10
68-Pln Ceramic PGA
Features
- Clock generator
- Bus interface
- Bus arbitration
- Programmable wait state generator
- DRAM refresh controller
- Three 16-bit timer/counters
- Asynchronous serial I/O controller
- Eight-input interrupt controller
- Four-channel DMA controller
Hardware effective address calculation logic
Maskable and nonmaskable interrupt inputs
IEEE 796 compatible bus interface
Low-power standby mode
10
L8
Pin Configuration
o Low-power CMOS technology
o V20/V30 instruction set compatible
o Minimum instruction execution time: 250 ns at
o Direct addressing of 1M bytes of memory
o Powerful set of addressing modes
o Fourteen 16-bit CPU registers
o On-chip peripherals including
Package
68-pin ceramic PGA
10
11
A
H
G
0
C
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
A2
INTP7
B9
DMARQl
FlO
AD7
K4
NMI
RESET
A3
INTP5
B10
DMARQO
Fll
GND
K5
A4
INTP3
Bll
ADO
Gl
Xl
K6
RESOUT
AS
INTPl
Cl
TCTL2
G2
CLKOUT
K7
HLDRQ
C2
POLL
K8
A19/PS3
A7
DMAAK2
Cl0
ADl
Gll
AD9
K9
A17/PSl
A8
DMAAKl
Cll
AD2
Hl
BUFEN
Kl0
AD14
A9
DMAAKO
Dl
QSl
H2
BUFR/W
Kll
AD1S
Al0
END/TC
D2
QSo
Hl0
AD10
L2
lORD
Bl
TCLK
010
AD3
Hll
AD11
L3
BSo
B2
TOUT2
Dll
AD4
Jl
BUSLOCK
L4
BS2
B3
INTP6
El
ASTB
J2
iOWA
L5
READY
B4
INTP4
E2
UBE
J10
AD12
L6
B5
INTP2
El0
ADs
Jll
L7
Voo
HLDAK
Ell
AD6
Kl
AD13
MWR
L8
REFRQ
Fl
GND
K2
MRD
L9
A1a1PS2
F2
X2
K3
BS1
Ll0
A16/PSo
A6
B6
B7
B8
DMAAK3/TxD
INTAK/TOUT11
SRDY
DMARQ3/RxD
DMARQ2
Gl0
ADa
83-0027196
50008-1 (NECEL-419)
NEe
pPD70216 (V50)
Pin Configurations (cont)
68-Pin Plastic Leaded Chip Carrier (PLCC)
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INTP7
lORD
43
MRD
42
INTP6
BSo
41
INTP5
BS1
40
INTP4
BS2
39
INTP3
NMI
38
IflITP2
READY
37
INTP1
RESET
36
INTAK/TOUT1/SRDY
35
DMAAK3/TxD
RESOUT
34
DMARQ3/RxD
HLDAK
33
DMAAK2
HLDRQ
32
DMARQ2
REFRQ
31
DMAAK1
A19/PS3
30
DMARQ1
A1S/PS2
29
DMAAKO
A17/PS1
28
DMARQO
A16/PSO
27
END/TC
Voo
0
83-0041266
2
pPD70216 (V50)
64
lORD
63
NC
62
MWR
61
IOWR
60
BUSLOCK
59
BUFR/W
58
BUFEN
57
CLKOUT
56
X1
55
X2
54
GND
53
NC
52
GND
51
UBE
50
ASTB
49
aSO
48
aS1
47
POLL
46
TCTL2
45
TOUT2
44
TCLK
43
NC
42
INTP7
41
INTP6
1m
83-0041278
3
NEe
pPD70216 (V50)
Pin Identification
Symbol
ASTB
Symbol
Function
Function
TOUT2
Timer/counter 2 output
Multiplexed address/ processor status outputs
UBE
Upper byte enable output
Multiplexed address/data bus
VDn
+5 V power supply input
Address strobe output
Xl, X2
Crystal/external clock inputs
Bus status outputs
BUFEN
Data bus transceiver enable output
BUFR/W
Data bus transceiver direction output
BUS LOCK
Buslock output
CLKOUT
System clock output
DMAAKO
DMA channel 0 acknowledge output
DMAAK1
DMA channel 1 acknowledge output
DMAAK2
DMA channel 2 acknowledge output
DMAAK3/TxD
DMA channel 3 acknowledge output/Serial
transmit data output
DMARQO
DMA channel 0 request input
DMARQ1
DMA channel 1 request input
DMARQ2
DMA channel 2 request input
DMARQ3/RxD
DMA channel 3 request input/Serial receive
data input
END/TC
End input/Terminal count output
GND
Ground
HLDAK
Hold acknowledge output
HLDRQ
Hold request input
IC
Internal connection; leave unconnected
INTAKITOUT1/SRDY
Interrupt acknowledge output/Timer/counter 1
output/Serial ready output
INTP1-INTP7
Interrupt request inputs
lORD
I/O read strobe output
10WR
I/O write strobe output
MRD
Memory read strobe output
MWR
Memory write strobe output
NC
No connection
NMI
Nonmaskable interrupt input
POLL
Poll input
CPU queue status outputs
READY
Ready input
REFRQ
Refresh request output
RESET
Reset input
RESOUT
Synchronized reset output
TCLK
Timer/counter external clock input
TCTL2
Timer/counter 2 control input
4
Pin Functions
A19-A16/PS3-PSO [Address/Status Bus]
These three-state output pins contain the upper 4 bits
of the 20-bit address during T1 and processor status
information during the T2, T3, TW, and T4 states of a
bus cycle. During T1 of a memory read or write cycle,
these pins contain the upper 4 bits of the 20-bit
address. These pins are forced low during T1 of an I/O
bus cycle.
Processor status is output during T2, T3, TW, and T4 of
both memory and I/O bus cycles. PS 3 is zero during
any CPU native mode bus cycle. During any DMA,
refresh, or 8080 emulation mode bus cycle, PS3 outputs
a high level. PS2 outputs the contents of the interrupt
enable (IE) flag in the CPU PSW register. PS1 and PS o
indicate the segment register used to form the physical
address of a CPU bus cycle as follows:
PSI
PSo
Segment
0
0
0
Data segment 1 (DS1)
Stack segment (SS)
1
0
1
Program segment (PS)
Data segment 0 (DSO)
These pins are in the high-impedance state during hold
acknowledge.
AD15-ADo [Address/Data Bus]
These three-st~te pins form the middle byte of the
active-high, time-multiplexed address/data bus. During
T1 of a bus cycle, AD1S-ADo output the lower 16 bits of
the 20-bit memory or I/O address. During the T2, T3,
TW, and T4 states, AD1S-ADo form the 16-bit bidirectional data bus.
The memory and I/O address spaces are organized
into a pair of byte-wide banks. The even bank is
accessed whenever ADo = 0 during T1 of a bus cycle.
Access to the odd bank is controlled by the USE pin.
The AD1S-ADo pins enter the high-impedance state
during hold acknowledge or internal interrupt acknowledge bus cycles or while RESET is asserted. Pins
AD10-ADs contain the slave address of an external
interrupt controller during the second interrupt acknowledge bus cycle.
NEe
pPD70216 (V50)
ASTB [Address Strobe]
BUSLOCK
This active-high output is used to latch the address
from the multiplexed address bus in an external address
latch during T1 of a bus cycle. ASTB is held at a low
level during hold acknowledge.
This active-low output provides a means forthe CPU to
indicate to an external bus arbiter that the bus cycles of
the next instruction are to be kept contiguous.
BUSLOCK is asserted forthe duration of the instruction
following the BUS LOCK prefix. BUSLOCK is also
asserted during interrupt acknowledge cycles and
enters the high-impedance state during hold acknowledge. While BUSLOCK is asserted, DMAU, RCU, and
external bus requests are ignored.
BS2-BSO [Bus Status]
Outputs BS2-BSO indicate the type of bus cycle being
performed as shown below. BS2-BSO become active
during the state preceding T1 and return to the passive
state during the bus state preceding T4.
Bus Cycle
CLKOUT
CLKOUT is a buffered clock output used as a reference
for all timing. CLKOUT has a 50-percent duty cycle at
ha:/f the frequency of the input clock source.
BS2
BS)
BSo
0
0
0
0
0
1
Interrupt acknowledge
I/O read
0
0
1
1
0
1
I/O write
Halt
DMAAKO-DMAAK2 [DMA Acknowledge]
0
0
0
1
Instruction fetch
Memory read (1)
0
1
Memory write (2)
Passive state
This set of outputs contains the DMA acknowledge
signals for channels 0-2 from the internal DMA control.Ier and indicate that the peripheral can perform the
requested transfer.
Note:
(1) Memory read bus cycles include CPU, DMA read, DMA verify,
and refresh bus cycles.
(2) Memory write bus cycles include CPU and DMA write bus cycles.
BS2-BSO are three-state outputs and are high impedance during hold acknowledge.
BUFEN [Buffer Enable]
BUFEN is an active-low output for enabling an external
data bus transceiver during a bus cycle. BUFEN is
asserted during T2 through T3 of a read cycle, T2
through T3 of a slave interrupt acknowledge cycle, and
T1 through T4 of a write cycle. BUFEN is not asserted
when the bus cycle corresponds to an internal peripheral, DMA, refresh, or internal interrupt acknowledge cycle. BUFEN enters the high-impedance state
during hold acknowledge.
BUFR/W [Buffer Read/Write]
BUFR/W is a three-state, active-low output used to
control the direction of an external data bus transceiver during CPU bus cycles. A high level indicates the
pPD70216 will perform a write. cycle and a low level
indicates a read cycle. BUFR/W enters the highimpedance state during hold acknowledge.
nI
DMAAK3/TxD [DMA Acknowledge 3]/[Serial
Transmit Data]
Two output signals multiplexed on this pin are selected
by the PF field of the on-chip peripheral connection
register.
• DMAAK3 is an active-low output and enables an
external DMA peripheral to perform the requested
DMA transfer for channel 3.
• TxD is the serial data output from the serial control
unit.
DMARQO-DMARQ2 [DMA Request]
These synchronized inputs are used by external peripherals to request DMA service for channels 0-2 from
the internal DMA controller.
DMARQ3/RxD [DMA Request 3]/[Serial Receive
Data]
Two input signals multiplexed on this pin are selected
by the PF field of the on-chip peripheral connection
register.
• DMARQ3 is used by an external peripheral to request
a DMA transfer cycle for channel 3.
• RxD is the serial data input to the serial control unit.
5
~
NEe
pPD70216 (V50)
END/TC [End/Terminal Count]
• TOUT1 is the output of timerlcounter 1.
This active-low bidirectional pin controls the termination of a DMA service. Assertion of END by external
hardware during DMA service causes the service to
terminate. When a DMA channel reaches its terminal
count, the DMAU asserts TC, indicating the programmed operation has completed.
• SRDY is an active-low output and indicates that the
serial control unit is ready to receive the next
character.
END/TC is an open-drain 1/0 pin, and requires an
external 2.2-kO pull-up resistor.
HLDAK [Hold Acknowledge]
When an external bus requester has become the
highest priority requester, the internal bus arbiter will
assert the HLDAK output indicating the address, data,
and control buses have entered a high-impedance state
and are ayailable for use by the external bus master.
Should the internal DMAU or RCU (demand mode)
request the bus, the bus arbiter will drive HLDAK low.
When this occurs, the external bus master should
complete the current bus cycle and negate the HLDRQ
signal. This allows the bus arbiter to reassign the bus to
the higher priority requester.
If a higher priority internal bus master subsequently
requests the bus, the high-level width of HLDAK is
guaranteed to be a minimum of one CLKOUT period.
HLDRQ [Hold Request]
This active-high signal is asserted by an external bus
master requesting to use the local address, data, and
control buses. The HLDRQ input is used by the internal
bus arbiter, which gives control of the buses to the
highest priority bus requester in the following order.
Bus Master
RCU
DMAU
HLDRQ
CPU
RCU
Priority
Highest (demand mode)
•
•
•
Lowest (normal operation)
INTAK/TOUT1/SRDY [Interrupt Acknowledge]1
[Timer 1 Output]l[Serial Ready]
Three output signals multiplexed on this pin are
selected by the PF field of the on-chip peripheral
connection register.
• INTAK is an interrupt acknowledge signal used to
cascade external siavepPD71059 Interrupt Controllers. INTAK is asserted during T2, T3, and TW states
of an interrupt acknowledge cycle.
6
INTP1-INTP7 [Peripheral Interrupts]
INTP1-INTP7 accept either rising-edge or high-level
triggered asynchronous interrupt requests from external
peripherals. These INTP1-INTP7 inputs are internally
synchronized and prioritized by the interrupt control
unit, which requests the CPU to perform an interrupt
acknowledge bus cycle. External interrupt controllers
such as the pPD71059 can be cascaded to increase the
number of vectored interrupts.
These interrupt inputs cause the CPU to exit both the
standby and 8080 emulation modes.
The INTP1-INTP7 inputs contain internal pull-up resistors and may be left unconnected.
lORD [1/0 Read]
This three-state pin outputs an active-low 110 read
strobe during T2, T3, and Tw of an I/O read bus cycle.
Both CPU I/O read and DMA write bus cycles assert
lORD. lORD is not asserted when the bus cycle
corresponds to an internal peripheral or register. It
enters the high-impedance state during hold acknowledge.
10WR [1/0 Write]
This three-state pin outputs an active-low 110 write
strobe during T2, T3, and TW of a CPU I/O write or an
extended DMA read cycle and during T3 and TW of a
DMA read bus cycle. 10WR is not asserted when the
bus cycle corresponds to an internal peripheral or
register. It enters the high-impedance state during
hold acknowledge.
MRD [Memory Read Strobe]
This three-state pin outputs an active-low memory
read strobe during T2, T3, and TW of a memory read
bus cycle. CPU memory read, DMA read, and refresh
bus cycles all assert MRD. MRD enters the highimpedance state during hold acknowledge.
MWR [Memory Write Strobe]
This three-state pin outputs an active-low memory
write strobe during T2, T3, and TW of a CPU memory
write or DMA extended write bus cycle and during T3
and TW of a DMA normal write bus cycle. MWR enters
the high-impedance state during hold acknowledge.
NEe
pPD70216 {V50}
NMI [Nonmaskable Interrupt]
REFRQ [Refresh Request]
The NMI pin is a rising-edge-triggered interrupt input
that cannot be masked by software. NMI is sampled by
CPU logic each clock cycle and when found valid for
one or more CLKOUT cycles, the NMI interrupt is
accepted. The CPU will process the NMI interrupt
immediately after the current instruction finishes
execution by fetching the segment and offset of the
NMI handler from interrupt vector 2. The NMI interrupt
causes the CPU to exit both the standby and 8080
emulation modes. The NMI input takes precedence
over the maskable interrupt inputs.
REFRQ is an active-low output indicating the current
bus cycle is a memory refresh operation. REFRQ is
used to disable memory address decode logic and
refresh dynamic memories. The 8-bit refresh row
address is placed on As-A1 during a refresh bus cycle.
POLL [Poll]
The active-low POLL input is used to synchronize the
operation of external devices with the CPU. During
execution of the POLL instruction, the CPU checks the
POLL input state every five clocks until POLL is once
again asserted.
QS1-QSO [Queue Status]
The QS1 and QSo outputs maintain instruction synchronization between the pPD70216 CPU and external
devices.These outputs are interpreted as follows.
QSo
o
Instruction Queue Status
No operation
RESET [Reset]
RESET is a Schmitt trigger input used to force the
pPD70216 to a known state by resetting the CPU and
on-chip peripherals. RESET must be asserted for a
minimum of four clocks to guarantee recognition. After
RESET has been released, the CPU will start program
execution from address FFFFOH in the native mode.
RESET will release the CPU from the low-power
standby mode and force it to the native mode.
~
RESOUT [Reset Output]
~
This active-high output is available to perform a systemwide reset function. RESET is internally synchronized
with CLKOUT and output on the RESOUT pin.
TCLK
TCLK is an external clock source for the timer control
unit. The three timer/counters can be programmed to
operate with either the TCLK input or a prescaled
CLKOUT input.
First byte of instruction fetched
Flush queue contents
TCTL2
Subsequent byte of instruction fetched
TCTL2 is the control input for timer/counter 2.
Queue status is valid for one clock cycle after the CPU
has accessed the instruction queue.
TOUT2
READY [Ready]
UBE [Upper Byte Enable]
This active-high input synchronizes external memory
and peripheral devices with the pPD70216. Slow
memory and I/O devices can lengthen a bus cycle by
negating the READY input and forcing the SIU to insert
TW states. READY must be negated prior to the rising
edge of CLKOUT during the T2 or by the last internallygenerated TW state to guarantee recognition. When
READY is once again asserted and recognized by the
SIU, the SIU will proceed to the T4 state.
USE is an active-low output, asserted when the upper
byte of the 16-bit data bus contains valid data. USE is
used along with Ao by the memory decoding logic to
select the even/odd banks as follows.
The READY input operates in parallel with the internal
pPD70216 wait control unit and can be used to insert
more than three wait states into a bus cycle.
TOUT2 is the output of timer/counter 2.
Operation
UBE
Ao
Bus
Cycles
Word, even address
0
0
1
Word, odd address
0
2
1
1 (1st bus cycle)
o(2nd bus cycle)
Byte, even address
1
0
Byte, odd address
0
USE is a three-state output and enters the highimpedance state during hold acknowledge.
7
NEe
pPD70216.(V50)
X1, X2 [Clock Inputs]
Pin States
These pins accept either a parallel resonant, fundamental mode crystal or an external oscillator input with
a frequency twice the desired operating frequency.
Table 1.lists the output pin states during the Hold, Halt,
Reset and DMA Cascade conditions.
In the case of an external clock generator, the X2 pin
can either be left unconnected or be driven by the
complement of the X1 pin clock source.
Table 1.
Output PIn States
DMA
Output
Hold
Halt
A19- A16 1PS3-PSO
3-state Out
Hi-Z
H/L
H/L
Hi-Z
AD15- AD o
3-state I/O
Hi-Z
H/L
Hi-Z
Hi-Z
Out
L
L
L
L
BS2-BSO
3-state Out
Hi-Z
H
H
H
Symbol
ASTB
Reset Cascade
BUFEN
3-state Out
Hi-Z
H
H
Hi-Z
BUFR/W
3-state Out
Hi-Z
H/L
H
Hi-Z
BUS LOCK
3-state Out
Hi~Z
H/L
H
Hi-Z
CLKOUT
Out
H/L
H/L
H/L
H/L
DMAAKO-DMAAK2
Out
H
H/L
H
H/L
DMAAK31
Out
H
H/L
TxD
H/L
END/TC
I/O
H
H/L
HLDAK
Out
H
H/L
INTAK
Out
H
H
TOUT1
H/L
H/L
SRDY
H/L
H/L
Hi-Z
H
lORD
3-state Out
H
H/L
H/L
H/L
H
H
H
H
L
H/L
H/L
H
Hi-Z
10WR
3-state Out
Hi-Z
H
H
Hi-Z
MRD
3-state Out
Hi-Z
H
H
Hi-Z
MWR
3-state Out
Hi-Z
H
H
Hi-Z
QS1-QSO
Out
H/L
L
L
H/L
REFRQ
Out
H
H/L
H.
H
RESOUT
Out
L
L
H
L
TOUT2
Out
H/L
H/L
H/L
H/L
3-state Out
Hi-Z
H
H
Hi-Z
UBE
H: high level; L: low level; H/L.: high or low level; Hi-Z: high
impedance.
8
NEe
pPD70216 (V50)
Block Diagram
INTP1
INTP2
INTP3
INTP4
INTPS
Interrupt
Control
Unit
[ICU]
Wait
Control
Unit
[WCU]
A19-A16/PS3-PSO
AD1S-ADo
INTP6
BS2-BSo
INTP7
QS1
QSo
TOUT2
TOUT1
TCTL2
TCLK
Timer/
Counter
Unit
[TCU]
POLL
Bus
Interface
Unit
[BIU]
ASTB
USE
BUFEN
BUFR/W
B
BUSLOCK
DMARQO
DMAAKO
DMARQ1
i5MAAi<1
DMARQ2
DMA
Control
Unit
DMAAK2
[DMAUl
Central
Processing
Unit
[CPU]
lORD
IOWR
MRD
MWR
READY
RESET
DMARQ3
RESOUT
DMAAK3
END/TC
Bus
Arbitration
Unit
INTAK
NMI
X1
X2
CLKOUT
HLDAK
HLDRQ
[BAUl
Clock
Generator
[eG]
Refresh
Control
Unit
[RCUl
Serial
Control
Unit
[SCUl
TxD
SRDY
RxD
REFRQ
83-004138C
9
NEe
IlPD70216 (V50)
Absolute Maximum Ratings
DC Characteristics
TA = +25°C
TA = -10 to +70°C, Voo = +5 V ±10% (8 MHz),
Voo = 5 V ±5% (10 MHz)
Power supply voltage, Voo
-0.5 to +7.0 V
Input voltage, VI
ClK input voltage, VK
-0.5 to Voo + 1.0 V
Output voltage, Vo
-0.5 to Voo + 0.3 V
-10 to +70°C
Operating temperature, TOPT
Storage temperature, TSTG
-65 to +150 °C
Comment: Exposure to Absolute Maximum Ratings for extended
periods may affect device reliability; exceeding the ratings could
cause permanent damage. The device should be operated within the
limits specified under DC and AC Characteristics.
Capacitance
TA=+25°C, Voo=OV
Limits
Parameter
Symbol
Min
Max
Input capacitance
CI
15
Output capacitance
Co
15
10
Limits
-0.5 to Voo + 0.3 V
Unit
Test
Conditions
Symbol
Min
Max
Unit
rnput voltage, high
VIH
2.2
Voo+
0.3
V
Input voltage, low
Parameter
VIL
-0.5
0.8
V
X1, X2 input
voltage, high
VKH
3.9
Voo +
1.0
V
X1, X2 input
voltage, low
VKL
-0.5
0.6
V
Output voltage, high VOH
0.7 Voo
Test
Conditions
V
10H = -400J1.A
V
10L= 2.5 rnA
Output voltage, low
VOL
0.4
Input leakage
current, high
ILiH
10
J1.A
VI = Voo
Input leakage
current, low
ILlPL
-300
J1.A
VI =0 V, INTP
input pins
ILiL
-10
J1.A
VI = 0 V, other
input pins
Output leakage
current, high
ILOH
10
J1.A
Vo = Voo
Output leakage
current, low
ILOL
-10
J1.A
Vo=OV
Supply current
8 MHz
100
90
20
rnA
rnA
Normal mode
Standby mode
10 MHz
100
120
25
rnA
rnA
Normal mode
Standby mode
pF fc = 1 MHz;
unmeasured pins
pF
are returned to 0 V.
NEe
pPD70216 (V50)
AC Characteristics
TA
= -10 to +70°C; Voo = 5 V ±10% (8 MHz), Voo = 5 V ±5% (10 MHz), CL = 100 pF
8 MHz Limits
Parameter
10 MHz Limits
Symbol
Min
Max
Min
Max
External clock input cycle time
tCYX
62
250
50
250
External clock pulse width, high
tXXH
20
19
ns
VKH
External clock pulse width, low
tXXL
20
19
ns
VKL = 1.5 V
External clock rise time
tXR
10
5
ns
1.5 - 3.0V
External clock fall time
tXF
10
5
ns
3.0 -.1.5 V
CLKOUT cycle time
tCYK
124
500
ns
CLKOUT pulse width, high
tKKH
0.5 tCYK-7
0.5 tCYK - 5
ns
VKH
CLKOUT pulse width, low
tKKL
0.5 tCYK-7
0.5 tCYK - 5
ns
VKL = 1.5 V
500
100
Unit
Test Conditions
ns
= 3.0 V
= 3.0 V
CLKOUT rise time
tKR
7
5
ns
1.5 - 3.0 V
CLKOUT fall time
tKF
7
5
ns
3.0 -1.5 V
CLKOUT delay time from external clock
tDXK
55
40
ns
Input rise time (except external clock)
tlR
20
15
ns
0.8- 2.2 V
Input fall time (except external clock)
tlF
12
10
ns
2.2 -
Output rise time (except CLKOUT)
tOR
20
15
ns
0.8- 2.2V
tOF
12
10
ns
2.2 - 0.8 V
Output fall time (except CLKOUT)
RESET setup time to CLKOUT 1
tSRESK
25
RESET hold time after CLKOUT 1
tHKRES
35
RESOUT delay time from CLKOUT 1
60
20
ns
25
ns
tDKRES
5
READY inactive setup time to CLKOUTt
tSRYLK
15
15
READY inactive hold time after CLKOUTt
tHKRYL
25
20
ns
READY active setup time to CLKOUTt
tSRYHK
15
15
ns
5
50
ns
ns
READY active hold time after CLKOUTt
tHKRYH
25
20
ns
NMI, POLL setup time to CLKOUTt
tSIK
15
15
ns
Data setup time to CLKOUT 1
tSDK
15
15
ns
Data hold time after CLKOUT 1
tHKD
10
10
ns
Address delay time from CLKOUT 1
tDKA
10
Address hold time after CLKOUT 1
tHKA
10
1/0 recovery time
tAl
PS delay time from CLKOUT 1
tDKP
60
60
tFKP
10
tSAST
tKKL - 20
Address float delay time from CLKOUT 1
tFKA
tHKA
50
ns
10
50
ns
10
50
ns
tHKA
A19-AO UBE
(Note 1)
ns
tKKL - 30
60
ns
ns
2tCYK - 40
10
PS float delay time from CLKOUTt
10
10
2tCYK - 50
Address setup time to ASTBl
ASTB t delay time from CLKOUT 1
55
1m
0.8 V
50
ns
40
ns
45
ns
tDKSTH
45
ASTBl delay time from CLKOUTt
tDKSTL
50
ASTB pulse width, high
tSTST
tKKL -10
tKKL -10
ns
Address hold time after ASTBl
tHSTA
tKKH - 20
tKKH - 20
ns
Control delay time from CLKOUT
tDKCT1
10
70
10
60
ns
(Note 2)
tDKCT2
10
60
10
55
ns
(Note 3)
11
NEe
tlPD70216 (V50)
AC Characteristics (cont)
10 MHz limits
8 MHz Limits
Parameter
Symbol
Min
Max
RO! delay time from address float
tOAFRL
0
RO! delay time from CLKOUT!
tOKRL
10
75
10
70
Min
Max
0
Unit
Test Conditions
ns
(Note 4)
10
65
ns
10
60
ns
ROt delay time from CLKOUT!
tOKRH
REFRQt delay from MROt
tORQHRH
tKKL - 30
tKKL - 30
ns
Address delay time from ROt
tORHA
tCYK - 40
tCYK - 40
ns
RO pulse width, low
tRR
2tCYK - 50
2tCYK - 40
ns
tOBECT
tKKL - 20
tKKL - 20
ns
Read cycle
tOWCT
tKKL - 20
tKKL - 20
ns
Write cycle
BUFR/W delay from BUFENt
tDKD
10
60
10
55
ns
Data float delay time from CLKOUT!
tFKO
10
60
10
55
ns
WR pulse width, low
Data output delay time from CLKOUT!
ns
tww
2tCYK - 40
2tCYK - 40
BS! delay time from CLKOUTt
tOKBL
10
60
10
55
BS t delay time from CLKOUT!
tOKBH
10
60
10
55
HLDRQ setup time to CLKOUTt
tSHQK
20
15
(Note 5)
(Note 4)
ns
ns
ns
HLOAK delay time from CLKOUT!
tOKHA
10
70
10
60
ns
DMAAK! delay time from CLKOUTt
tOKHOA
10
60
10
55
ns
DMAAK! delay time from CLKOUT!
tOKLOA
10
90
10
80
ns
Cascade mode
WR pulse width, low (DMA cycle)
tWW1
2tCYK - 40
2tCYK - 40
ns
DMA extended
write cycle
WR pulse width, low (DMA cycle)
tWW2
tCYK - 40
tCYK - 40
ns
DMA normal
write cycle
RD!, WR! delay from DMAAK!
tOOARW
tKKH - 30
tKKH - 30
ns
DMAAKt delay from RDt
tORHOAH
tKKL- 30
tKKL - 30
os
RDt delay from WRt
towHRH
5
5
ns
TC output delay time from CLKOUTt
tOKTCL
60
55
ns
TC off delay time from CLKOUTt
tOKTCF
60
55
ns
TC pulse width, low
tTCTCL
TC pullup delay time from CLKOUTt
tOKTCH
END setup time to CLKOUTt
tSEOK
35
30
ns
END pulse width, low
tEOEOL
100
80
ns
DMARQ setup time to CLKOUTt
tSOQK
35
30
ns
INTPn pulse width, low
tlPlPL
100
80
ns
RxD setup time to SCU internal clock!
tSRX
0.5
J,Js
RxD hold time·after SCU internal clock!
tHRX
SRDY delay time from CLKOUT!
tOKSR
ns
tCYK -15
tCYK -15
tKKH
tKKH
+ tCYK -10
+ tCYK -10
0.5
150
ns
J,Js
100
ns
Notes:
(1) This is specified to guarantee a read/write recovery time for I/O
devices.
(2) Delay from CLKOUT to DMA cycle MWR/IOWR outputs.
(3) Delay from CLKOUT to BUFR/W, BUFEN, INTAK, REFRQ outputs and CPU cycle MWR/IOWR outputs.
12
(4) RD represents lORD and MRD. WR represents 10WR and MWR.
(5) This is specified to guarantee that REFRQ t is delayed from
MRD t at all times.
NEe
pPD70216 (V50)
AC Characteristics (cont)
8 MHz Limits
Parameter
Symbol
TxD delay time from TOUT1!
tOTX
Min
Max
10 MHz Limits
Min
500
Max
Unit
200
ns
TCTL2 setup time from CLKOUT!
tSGK
50
40
ns
TCTL2 setup time to TCLKt
tSGTK
50
40
ns
TCTL2 hold time after CLKOUT!
tHKG
100
80
ns
TCTL2 hold time after TCLKt
tHTKG
50
40
ns
TCTL2 pulse width, high
tGGH
50
40
ns
tGGL
50
40
TCTL2 pulse width, low
TOUT output delay time from CLKOUT!
TOUT output delay time from TOUT!
ns
tOKTO
200
150
ns
100
ns
tOTKTO
150
TOUT output delay time from TCTL2!
tOGTO
120
90
ns
TCLK rise time
tTKR
25
25
ns
TCLK fall time
tTKF
25
ns
TCLK pulse width, high
tTKTKH
TCLK pulse width, low
tTKTKL
50
TCLK cycle time
tCYTK
124
RESET pulse width low
tRESET1
50
50
tRESET2
4 tCYK
4 tCYK
25
50
45
100
1m
ns
45
DC
Test Conditions
ns
DC
ns
pS
After power on
During operation
13
NEe
pPD70218 (V50)
Timing Measurement Points
pPD70216 Clock Input Configurations
Crystal-Controlled Internal Clock
{
Input 2.4 V
[except Clock]
1
'II-_-'-_~ X1
1~~F
II
0.4
T
---v-
2.2 V
2.2 V \ ; - -
v~_0_.8_V_ _ _ _ _ _.;.;0.;;.,8..;...V~
J:::l
15pF
1 - -.......-~X2
q::
Output
V
2.2 V
2.2 V \ ; - -
~~0~.8_V_ _ _ _ _ _. .;.;0.8~V~
External Clock 1
CLK~
83·00181SA
I
External Clock 2
X1
CLK-1
X2
I
Buffers are high-speed
CMOS inverters.
83·004019A
Timing Waveforms
Clock Timing
External
Clock
[X1]
CLKOUT
83-001844B
14
NEe
pPD70216 (V50)
Timing Waveforms (coni)
Reset and Ready Timing
Reset Timing
CLKOUT
___
~,"6)
t",'6~~
-flt' (1
RESOUT
_ __
Ready Timing,No Wait States
T1
T2
T3
T4
T1
T1
T2
T3
TW
T4
CLKOUT
READY
Ready Timing, Wait States
CLKOUT
READY
83-0027258
15
NEe
pPD70216 (V50)
Timing Waveforms (cont)
Poll, NMI, and Buslock Timing
CLKOUT
POLL, NMI Input Timing
_f_t
S'K
POLL, NMI
_
CLKOUT
BUSLOCK Output Timing
83-001831 B
Read/Write Recovery Time
1+----
tAI---~
83-004266B
16
NEe
pPD70216 (V50)
Timing Waveforms (coni)
Read Timing
T4
T1
T2
T4
T3fTW
CLKOUT
A19/PS3·
A1s1 PSo
-----
Processor Status
II
tSOK~1
Data Input
ASTB .......- - - -
[Note 1)
I
tOCKT2
tOKeT2
[Note 1)
~-----------rtRR----------~
tOKBL
Note:
(1) Except internal If 0 accesses.
83-0018458
17
NEe
pPD7021'6{V50)
Timing Waveforms (cont)
Write Timing
T4
T1
T2
T3/TW
T4
CLKOUT
A19/ PS3 .
-A16/PS O
AD15"ADO
Processor Status
-+-----(J
Data Output
AsrB
tOKCT2
[Note 1]
BUFRiW
tOKCT2
tOKCT2
[Note 1]
~----------+-tww--------~
tOKBL
tOKBH
Note:
[1] Except internal 1/0 accesses.
83-0018438
18
NEe
pPD70216 (V50)
Timing Waveforms (cont)
Status Timing
T4
T1
T2
T3/TW
T4
CLKOUT
A19/ PS 3
-A16/ PS o
Processor Status
II
UBE
tsoK~1
tFKA~
AD1S-AD o
Address
Em
Data Input
ASTB
tOKBH
Bus Status
tOKRH
~---------tRR----------~.1
OS1,OSO
_____X'-------IX__--.JX'---_)C
83-0027218
19
NEe
pPD70218 (V50)
Timing Waveforms (cont)
Interrupt Acknowledge Timing
CLKOUT
ItHKD
---.....---f'' ' --~
Vector number
[Note2J
~~_ _~_ _ _ _ _ _ _ _ _ _ _ _ _~~~______J~~_______________________________
ASTB
tOKCT2
1
\ ' - - _ _- - . 1
tOKCT2
BUFR/W ________
~--------------------------~~--------~~------~----------~------------------------
-(-~..
BUSLOCK
_
2
-----...,1
(1-(
Notes:
[1 J If the Interrupt Is accepted following a control transfer, the three TI states
can be replaced .wIth an unused instruction fetch bus cycle.
[2J Slave address when the Interrupt Is' from external pPD70159. Undefined
when internallCU Interrupt.
.'
.
[3J Solid line when Interrupt·from externalpPD70159.Dash Une when internal
ICU Interrupt.
83-0018416
20
NEe
pPD70216 (V50)
Timing Waveforms (coni)
HLDRQ/HLDAK Timing, Normal Operation
TI
CLKOUT~<",---+----+QK~~
HLDRQ
~
~
______________
T1
T4
TI
~
+-____~_____________
______
HLDAK
tOKA
Internal Bus Master
[N;(~e 1]
~
Internal
Bus Master
tFKA
tOKA
Inte-r-n-a-I-B-us--M-a-st-e-r-[N..(~ote 2] .-------------'~-----------------------o(]
(
Internal Bus Master
~--------
NOTES: (1) A19/PS3-A1S/PSo, AD1S-ADo, BUFEN,BUFR/W,MRD,IORD,MWR,IOWR,UBE
(2) BS2-BSO
83-0018288
HLDRQ/HLDAK Timing, Bus Wait
CLKOUT
HLDRQ
HLDAK
Bus
___
_Master
_ _[Note
_ _1]_
_ _ _ External
~(r:t'.~~-------------------J).-----_~(~_I_nt_eM_ran!.atl!B!:..u_S
:
~
_po
_
__
Note:
[1] A19/PS3-A1S/PSo, AD1S-ADO, UBE, BUFEN, BUFR/W, MRD, tORD, MWR, IOWR, B52-B50_
83-0018298
21
NEe
pPD70216 (V50)
Timing Waveforms (cont)
Refresh Timing
T1
T4
T4
T3/TW
T2
CLKOUT
ADS·ADO
------0«1
ASTB
tOAFRL
tORQHRH
tOKRL
tOKeT2
itOKBL
'l
rtOKBH
BS2
= 1, BS1 = 0, BSo
~1
!
83-003517C
22
NEe
pPD70216 (V50)
Timing Waveforms (cont)
DMAU. DMA Transfer Timing
T4
T1
T2
T3/TW
T4
CLKOUT
ASTB
83-0018478
23
NEe
pPD70216 '(V50)
Timing Waveforms (cont)
DMA Timing
EN CITe Timing
T2
T1
T3
T4
CLKOUT
TC
tSEDK
1tEDl~
-------0..----------------------CMA Request Timing
CLKOUT
OMARan
(n=0-3)
Cascade Mode, Normal Operation
Cascade Mode, Refresh Cycle Insertion
CLKOUT
OMARa
OMAAK -----------------~
83-001S26C
24
NEe
pPD70216 (V50)
Timing Waveforms (coni)
SCU Timing
+--t_ _ _
R X D \_ _ _
I~ tSRX
.1.
L
tHRx--.I
\J
TounJ
14----+-16 or 64 Toun pulses---+I
1 + - - - - 1 6 or 64 TOUT1 pulses---+i
TxD
CLKOUT
________
I""d:~-------~
SRDY
83-0018496
ICU Timing
INTPn
(n=1-7)
(I",,,)
25
NEe
pPD70216 (V50)
Timing Waveforms (coni)
TCU Timing, Internal Clock Source
CLKOUT
TCTL2
_ _ _ _f'O.WITOUT2)
TOUTn
[n = 1, 2]
-------------------83-0027228
TCU Timing, TCLK Source
trKR
tTKF
TCL.K
TCTL2
____~_;~~_)_:x=t-~:x=~'M'ro
TOUTn [n = 1, 2]
83-0018238
26
NEe
pPD70216 (V50)
Functional Description
Central Processing Unit
Refer to the JlPD70216 block diagram for an overview
of the ten major functional blocks listed below.
The JlPD70216 CPU functions similarly to the CPU of
the JlPD70116 CMOS microprocessor. However, because the pPD70216 has internal peripheral devices,
its bus architecture has been modified to permit
sharing the bus with internal peripherals. ThepPD70216
CPU is object code compatible with both thepPD70108/
JlPD70116 and theJlPD8086/JlPD8088 microprocessors.
•
•
•
•
•
•
•
•
•
•
Central processing unit (CPU)
Clock generator (CG)
Bus interface unit (BIU)
Bus arbitration unit (BAU)
Refresh control unit (RCU)
Wait control unit (WCU)
Timer/counter unit (TCU)
Serial control unit (SCU)
Interrupt control unit (ICU)
DMA control unit (DMAU)
Figure 1.
Figure 1 is the pPD70216 CPU block diagram. A listing
of the JlPD70216 instruction set is in the final sections
of th is data sheet.
JlPD70216 CPU Block Diagram
Internal address/data bus (20)
To BIU
•
NMI
INT
(from ICU)
TEMP
Qo
Q1
Q2
Q3
Q4
Qs
CLOCK
(from CG)
•
BCU
----
EXU
LC
PC
Effective Address
Generator
AW
BW
CW
•
OW
IX
•
IV
BP
SP
•
•
•
Subdata bus(16)
Main data bus(16)
83-0018396
')7
NEe
pPD70216 (V50)
Register Configuration
Program Counter [PC]. The program counter is a 16bit binary counter that contains the program segment
offset of the next instruction to be executed. The PC is
incremented each time the microprogram fetches an
instruction from the instruction queue. The contents of
the PC are replaced whenever a branch, call, return, or
break instruction is executed and during interrupt
processing. At this time, the contents of the PC are the
same as the prefetch pointer (PFP).
Prefetch Pointer [PFP]. The prefetch pointer is a
16-bit binary counter that contains the program segment offset of the next instruction to be fetched for the
instruction queue. Because instruction queue prefetch
is independent of instruction execution, the contents
of the PFP and PC are not always identical. The PFP is
updated each time the bus interface unit (BIU) fetches
an instruction for the instruction queue. The contents
of the PFP are replaced whenever a branch, call, return
or break instruction is executed and during interrupt
processing. At this time, the contents of the PFP and
PC are the same.
Segment Registers [PS, SS, OSo, OS1]. ThepPD70216
memory address space is divided into 64K-byte logical
segments. A memory address is determined by the sum
of a 20-bit base address (obtained from a segment
reg ister) and a 16-bit offset known as the effective
address (EA). I/O address space is not segmented and
no segment reg ister is used. The four segment reg isters
are program segment (PS), stack segment (SS), data
segment 0 (DSo), and data segment 1 (DS1)' The
following table lists their offsets and overrides.
Default
Segment Register
Offset
AW
Word multiplication/division, word I/O,
data conversion
Al
Byte multiplication/division, byte I/O, BCD
rotation, data conversion, translation
AH
Byte multiplication/division
BW
Translation
CW
loop control, repeat prefix
Cl
Shift/rotate bit counts, BCD operations
DW
Word multiplication/division, indirect
I/O addressing
Pointer [SP, BP] and Index Registers [IX, IV]. These
registers serve as base pointers or index registers
when accessing memory using one of the base,
indexed, or base indexed addressing modes. Pointer
and index registers can also be used as operands for
word data transfer, arithmetic, and logical instructions.
These registers are impliCitly selected by certain
instructions as follows.
Override
SP
Stack operations, interrupts
IX
Source block transfer, BCD string
operations, bit field extraction
IY
Destination block transfer, BCD string
operations, bit field insertion
PS
PFP register
None
Program Status Word [PSW]
SS
SP register
None
SS
Effective address (BP-based)
PS, OSo, OS1
The program status word consists of six status flags
and four control flags.
DSo
Effective address (non BP-based)
PS, SS, OS1
Status Flags
DSo
IX register (1)
PS, SS, OS1
DS1
IY register (2)
None
Note:
(1) Includes source block transfer, output, BCD string, and bit field
extraction.
(2) Includes destination block transfer, input, BCD string, and bit
field insertion.
28
General-Purpose Registers. The pPD70216 CPU contains four 16-bit general-purpose registers (AW, BW,
CW, DW), each of which can be used as a pair of 8-bit
registers by dividing into upper and lower bytes (AH,
Al, BH, Bl, CH, Cl, DH, Dl). General, purpose
registers may also be specified implicitly in an instruction. The implicit assignments are:
•
•
•
•
•
•
V (Overflow)
S (Sign)
Z (Zero)
AC (Auxiliary Carry)
P (Parity)
CY (Carry)
Control Flags
•
•
•
•
MD (Mode)
DIR (Direction)
IE (Interrupt Enable)
BRK (Break)
NEe
pPD70216 (V50)
When pushed onto the stack, the word image of the
PSW is as follows:
15
Dual Data Buses
8
v
MD
DIR
IE I BRK
I
o
7
S
Figure 2.
z
o
AC
o
P
CY
The status flags are set and cleared automatically
depending upon the result of the previous instruction
execution. Instructions are provided to set, clear, and
complement certain status and control flags. Other
flags can be manipulated by using the POP PSW
instruction.
Between execution of the BRKEM and RETEM instructions, the native mode RETI and POP PSW
instructions can modify the MD bit. Care must be
exercised by emulation mode programs to prevent
inadvertent alteration of this bit.
CPU Architectural Features
The major arch itectu ral featu res of the pPD70216 CPU
are:
•
•
•
•
Main data bus
Sub data bus
83-0038288
Figure 3.
Effective Address Generator
Dual data buses
Effective address generator
Loop counter
PC and PFP
Dual Data Buses. To increase performance, dual data
buses (figure 2) have been employed in the CPU to
fetch operands in parallel and avoid the bottleneck of a
single bus. For two-operand instructions and effective
address calculations, the dual data bus approach is 30
percent faster than single-bus systems.
Effective Address Generator. Effective address (EA)
calculation requires only two clocks regardless of the
addressing mode complexity due to the hardware
effective address generator (figure 3). When compared
with microprogrammed methods, the hardware approach saves between 3 and 10 clock cycles during
effective address calculation.
Effective Address
83-002737A
Program Counter and Prefetch Pointer. The functions
of instruction execution and queue prefetch are decoupled in thepPD70216. By avoiding a single instruction pointer and providing separate PC and PFP
registers, the execution time of control transfers and
the interrupt response latency can be minimized.
Several clocks are saved by avoiding the need to
readjust an instruction pointer to account for prefetct;Jing before computing the new destination address.
Loop Counter and Shifters. A dedicated loop counter is
used to count the iterations of block transfer and
multiple shift instructions. This logic offers a significant
performance advantage over arch itectu res that control
block transfers and multiple shifts using microprogramming. Dedicated shift registers also speed up the
execution of the multiply and divide instructions.
Compared with microprogrammed methods, multiply
and divide instructions execute approximately four
times faster.
29
t\fEC
pPD70216 (V50)
Enhanced Instruction Set
In addition to the pPDSOS6/SS instruction set, the
pPD70216 has added the following enhanced instructions.
Instruction
Function
PUSH imm
PUSH R
POP R
Push immediate data onto stack
Push all general registers onto stack
Pop all general registers from stack
MUL imm
Multiply register/memory by immediate data
SHL immB
SHR immB
SHRA immB
ROL immB
ROR immB
ROLC immB
RORC immB
Shift/rotate by immediate count
CHKIND
INM
OUTM
Check array index
Input multiple
Output multiple
PREPARE
DISPOSE
Prepare new stack frame
Dispose current stack frame
Unique Instruction Set
In addition to the pPD70216 enhanced instruction set,
the following unique instructions are supported.
Instruction
Function
INS
EXT
Insert bit field
Extract bit field
ADD4S
SUB4S
CMP4S
ROL4
ROR4
BCD string addition
BCD string subtraction
BCD string comparison
Rotate BCD digit left
Rotate BCD digit right
TEST1
SET1
CLR1
NOT1
Test bit
Set bit
Clear bit
Complement bit
REPC
REPNC
Repeat while carry set
Repeat while carry cleared
FP02
Floating point operation 2
Bit Fields. Bit fields are data structures that range in
length from 1 to 16 bits. Two separate operations on bit
fields, insertion and extraction, with no restrictions on
the position of the bit field in memory are supported.
Separate segment, byte offset, and bit offset registers
are used for bit field insertion and extraction. Because
of their power and flexibility, these instructions are
highly effective for graphics, high-level languages, and
data packing/unpacking applications.
30
Insert bit field (INS) copies the bit field of specified
length (0 = 1 bit, 15 = 16 bits) from the AW register to
the bit field addressed by DS1 :IY:regS (figure 4). The
bit field length can be located in any byte register or
supplied as an immediate value. The value in regS is a
bit field offset. A content of 0 selects bit 0 and 15 selects
bit 15 of the word that DSO:IX points to. Following
execution, the IY and bit offset register are updated to
point to the start of the next bit field.
Bit field extraction (EXT) copies the bit field of specified
length (0 = 1 bit, 15 = 16 bits) from the bit field
addressed by DSO:IX:regS to the AW register (figure 5).
If the bit field is less than 16 bits, it is right justified with
a zero fi II. The bit field length can be located in any byte
register or supplied as immediate data. The value in
regS is a bit field offset. A content of 0 selects bit 0 and
15 selects bit 15 of the word that DSO:IX points to.
Following execution, the IX and bit offset register are
updated to point to the start of the next bit field.
Packed BCD Strings. These instructions are provided
to efficiently manipulate packed BCD data as strings
(length from 1 to 254 digits) or as a byte data type with a
single instruction.
BCD string arithmetic is supported by the ADD4S,
SUB4S, and CMP4S instructions. These instructions
allow the source string (addressed by DSO:IX) and the
destination string (addressed by DS1 :IY) to be manipulated with a single instruction. When the number of
BCD digits is even, the Z and CY flags are set according
to the result of the operation. If the number of digits is
odd, the Z flag will not be correctly set unless the upper
4 bits of the result are zero. The CY flag will not be
correctly set unless there is a carry out of the upper 4
bits of the result.
The two BCD rotate instructions (ROR4, ROL4) perform
rotation of a single BCD digit in the lower half of the AL
register through the register or memory operand.
Bit Manipulation. Four bit manipulation instructions
have been added to the pPD70216 instruction set. The
ability to test, set, clear, or complement a single bit in a
register or memory operand increases code readability
as well as performance over the logical operations
traditionally used to manipulate bit data.
Repeat Prefixes. Two repeat prefixes (REPC, REPNC)
allow conditional block transfer instructions to use the
state of the CY flag as a terminating condition. The use
of these prefixes allows inequalities to be used when
working on ordered data, increasing the performance
of searching and sorting algorithms.
NEe
Figure 4.
pPD70216 (V50)
Bit Field Insertion
Bit length
o
15
!
AW
I
~~----+-!t _----"v---- 1: 17 + 8(imm8 -1)
o
DISPOSE
6/10
0
Control Transfer Instructions
CALL
near _proc
0 0 0
regptr
1
1
1
1 1 0 1 0
memptr16
1
1
1
mod
0 0
0
0
far-proc
memptr32
RET
0
16/20
3
reg
14/18
1
mem
23/31
2-4
----------------------------------------------------------------------------
1 1 1 1
o
o
o
o
mod
0
0
1 0
mem
21/29
5
31/47
2-4
0 0 0
1
15/19
1
0 0 0
0
20/24
3
0
0
0
o
21/29
o
24/32
69
~
NEe
pPD70216 (V50)
Instruction Set (cont)
Mnemonic
Operands
Opcode
7 6 5 4 3 2 1 0
0
5 4 3 2
Clocks
Bytes
3
Flags
AC CY V P
S Z
Control Transfer Instructions (cont)
BR
near_label
0
0 0
13
0
0
12
memptr16
1
1
far_label
0
0
1
shorLiabel
reg
1 1
0 0
reg
11
mod
0 0
mem
19/23
2-4
15
5
26/34
2-4
0
memptr32
1 1 1
BV
near_label
0 0 0 0
14/4
BNV
near_label
0 0 0 1
BC, Bl
neaLiabel
BNC,BNl
near.Jabel
0
BE, BZ
near_label
0
BNE, BNZ
near_label
BNH
near_label
BH
near_label
0
0 1
14/4
2
BN
near_label
0
0
14/4
2
14/4
2
mod
0
mem
14/4
2
0
0
14/4
2
0 0
1
14/4
0
0 0
14/4
0
0 1
14/4
2
0
14/4
2
BP
near_label
0 0
BPE
near_label
0
0
14/4
BPO
near_label
1 1
14/4
2
BlT
near_label
0 0
14/4
2
BGE
near_label
0 1
14/4
2
BlE
near-label
0
14/4
2
BGT
near_label
1
14/4
2
DBNZNE
near_label
0 0 0
14/5
0
1
0
DBNZE
near_label
0 0 0 0 1
14/5
2
DBNZ
near_label
0 0 0
13/5
2
BCWZ
near_label
0
13/5
2
0
0
Interrupt Instructions
BRK
imm8
BRKV
imm8
RETI
0
38/50
1
0
0 1
38/50
2
0
0
0 0
3
1
0 0 1 1
0 0 0
CHKIND
reg16; mem32
0
BRKEM
imm8
0 0 0 0
40/3
27/39
mod
reg
mem
1 1 1 1 1 1 1 1
R R R R R R
17-251
52-55
2-4
38/50
3
CPU Control Instructions
HALT
0 1 0 0
BUSlOCK
FP01
FP02
70
fp_op
1
0 0 0
0
X X X
2
2
1 1 Y Y Y Z Z Z
2
mod Y Y Y
10/14
2
2-4
fp_op, mem
1
fp_op
0
0 0
X
1 1 Y Y Y Z Z Z
2
2
fp_op, mem
0
0
X
mod Y Y Y
10/14
2-4
0 1 1 X X X
mem
mem
NEe
pPD70216 (V50)
Instruction Set (cont)
Opcode
Mnemonic
Operand
2
5 4
0
7 654321 0
Clocks
Bytes
Flags
AC CV V P
R R R R R R
S Z
CPU Control Instructions (cont)
POLL
0
2 + 5n
0
n = number of times POLL pin is sampled.
NOP
0 0
0
3
01
1
1 1
0
0
2
EI
1
1
0
1
2
OSO:, OS1:, PS:, SS:
(segment override prefixes)
0
0
2
0 0
seg
8080 Instruction Set Enhancements
RETEM
CALLN
1
imm8
1 0
1
0
27/39
2
0
0
0
38/58
3
1m
71
pPD70216 (V50)
72
NEe
NEe
pPD70136 (V33)
16·Bit Microprocessor:
High·Speed, CMOS
NEC Electronics Inc.
Description
The I-'PD70136 (V33™) is a 16-bit, high-speed CMOS
microprocessor that is object and source code compatible with the I-'PD70116 (V30~). Performance is four times
that of the 10-MHz V30 due to a number of architectural
features, such as hard-wired data path control and
dedicated high-speed logic. The address space is expanded to 16M bytes using an internal address translation table.
The powerful instruction set includes bit processing,
bit-field insertion and extraction, and BCD string arithmetic. Using a modified Booth's algorithm, the 16-MHz
device can execute a 16-bit multiply in 750 ns.
The I-'PD70136 has separate 16-bit data and 24-bit address buses. Bus control is synchronous. The nominal
bus cycle is two clock periods. Dynamic bus sizing is
supported for devices that require an 8-bit data path.
This allows the I-'PD70136 to be used in either 16- or 8-bit
systems.
An undefined instruction trap allows instructions that
are not part of the V-Series instruction set (such as
commands for proprietary MMUs) to be emulated. The
I-'PD72291, a high-speed CMOS floating-point coproces~
sor capable of 530K floating-point operations per second at 16 MHz, is offered.
Features
o 125-ns minimum instruction execution time at
16 MHz
o Expanded add ress space
- 24-bit addressing to 16M bytes
- LIM 4.0 compatible
o No microcode; better performance with hard-wired
data path control
o Dynamic bus sizing for both memory and I/O
o Fully I-'PD70116 software compatible
o Undefined instruction trap
V30 is a registered trademark of NEC Corporation
V20, V33, V40, and V50 are trademarks of NEC Corporation
50049
o High-speed multiplication: 16-bit multiply in
12 clocks (0.75 I-'s at 16 MHz)
o High-speed division: 16-bit divide in 19 clocks
(1.19 I-'S at 16 MHz)
o I-'PD72291 floating-point coprocessor executes 530K
floating-point operations per second
o BCD string arithmetic instructions
o CMOS with low-power standby mode
o 12.5-MHz or 16-MHz clock
o Single power supply
Ordering Information
Part Number
Clock (MHz)
p.PD70136R-12
12.5
R-16
16
L-12
12.5
L-16
16
GJ-12
12.5
GJ-16
16
Package
68-pin ceramic PGA
68-pin PLCC
74-pin plastic QFP
NEe
pPD70136 (V33)
Pin Configurations
BB-Pin Ceramic PGA
Bottom View
000000000
00000000000
00
00
00
00
00
00
ILPD70136R
00
00
00
00
00
00
00
00
00000000000
o 0 0 0 0 0 0 0 0 L10
A2
4
10
11
ABC
D
G
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
A2
AEX
B9
CLK
F10
Voo
K4
A12
A3
HLOAK
B10
014
F11
GNO
KS
A14
A4
READY
B11
012
G1
AO
KS
GNO
AS
CPREQ
C1
UBE
G2
A1
K7
A1S
AS
VOO
C2
Bussn
G10
Os
KS
01S
A7
CPBUSY
C10
011
G11
04
K9
A20
AS
INT
C11
010
H1
A2
K10
A23
A9
01S
01
BUSSTO
H2
A3
K11
A22
A10
013
02
RNI
H10
03
L2
A7
B1
BUSLOCK
010
09
H11
02
L3
A9
B2
BCYST
011
Os
J1
A4
L4
A11
B3
BSSIBS1S
E1
MilO
J2
AS
LS
A13
B4
HLORQ
E2
OSTB
J10
01
LS
VOO
BS
RESET
E10
07
J11
DO
L7
A1S
BS
GNO
E11
Os
K1
AS
LS
A17
B7
CPERR
F1
GNO
K2
AS
L9
A19
BS
NMI
F2
VOO
K3
A10
L10
A21
H
49NR-339B
BB-PinPLCC
AEX
8S8/8S16
41
40
39
HlDAK
HlDRQ
READY
RESET
CPREQ
GND
VDD
CPERR
CP8USY
NMI
INT
ClK
D15
D14
D13
49NR-340B
2
NEe
pPD70136 (V33)
74-Pin Plastic QFP
A21
A20
A19
015
3
A18
CLK
A17
INT
A16
A15
CPBUSY
7
NC
GNO
VDO
I-lPD70136GJ
GND
A14
CPREQ
A13
NC
A12
NC
RESET
READY
HLDRQ
HLDAK
BSSIBS16
AEX
A11
41
A10
A9
As
A7
49NR-346B
Pin Identification
Symbol
1/0
Ao-A23
3-state
0 0-015
3-state
USE
3-state
Function
Symbol
1/0
HLDAK
Out
Bus hold acknowledge
Data bus
INT
In
Maskable interrupt
Upper byte enable
NM1
In
Nonmaskable interrupt
Function
_Address bus
R!W
3-state
Read/write
CPBUSY
In
Coprocessor busy
M/iO
3-state
Memory I/O
CPERR
in
Coprocessor error
BUSSTO,
BUSST1
3-state
Bus status
BCYST
3-state
Bus cycle start strobe
lrn'i'B
3-state
Data strobe
BUSLOCK
Out
Bus lock
READY
In
Ready
BS'8/BS16
In
Dynamic bus sizing control
AEX
Out
Address expansion flag
HLDRQ
In
Bus hold request
CPREQ
In
Coprocessor request
RESET
In
Reset
CLK
In
Clock
Voo
+5-volt power supply
GND
Ground
IC
Internal connection; connect to
ground
NC
No connection
3
NEe
,.,PD70136 (V33)
Table 1. Output Pin States
State.
Symbol
Hold
Standby
Re.et
Ao-A23 (Note 1)
015-00 (Note 1)
O'BE (Note 1)
R/W (Note 1)
M/K) (Note 1)
BUSSTO, BUSST1 (Note 1)
BOYSi (Note 1)
I5'SiB (Note 1)
eOSLOOR
AEX
HLDAK
HI-z
HI-z
HI-z
HI-z
HI-z
HI-z
HI-z
HI-z
(Note 4)
(Note 5)
H
L
(Note 2)
H
L
L
H
(Note 3)
H
(Note 4)
(Note 5)
L
HI-z
HI-z
HI-z
HI-z
HI-z
HI-z
HI-z
HI-z
H
L
L
Note.:
(1) Latched Internally.
(2) Undefined during first two clock periods of the halt acknowledge
cycle; three-state thereafter.
(3) Low during first clock period of the halt acknowledge cycle; high
thereafter.
(4) Low If =BU"""S=L-=O-=C":":K prefix Is used for halt Instruction; high otherwise.
(5) Low If In extended addressing mode; high otherwise.
PIN FUNCTIONS
elK (Clock)
sizing can be selected so that only the lower 8 bits,
00-07, are used. During CPU read cycles, the value on
the data bus is latched by the CPU on the trailing edge of
T2 orthe last TW state. During CPU write cycles. 00-015
become valid after the rising edge of T1 and remain valid
until after the rising edge of the clock cycle following T2
or the last TW state. During HLOAK and when RESET is
asserted. 00-015 are not driven.
UBE (Upper Byte Enable)
USE indicates thatthe upper 8 bits of the data bus will be
used in the current CPU bus cycle. This signal is used in
conjunction with Ao as shown in table 2.
Table 2. Bus Operation l'S USE and Ao
USE
Ao
Word at odd address
0
1
0
Byte at even address
Byte at odd address
o (Note 1)
1 (Note 3)
1 (Note 1)
o (Note 2)
0
0
Bu. Operation
Word at even address,
~8/BS16 = 0
Number of
Bu. Cycle.
2
2
Note.:
(1) First bus cycle
(2) Second bus cycle
(3) Second cycle for bus sizing
CLK is the main clock. All timing is relative to this input.
Each bus state is one CLK period wide. Instruction clock
counts refer to this CLK input.
USE has the same timing as Ao-A23 and is not driven
during HLOAK or while RESET is asserted.
Ao-A23 (Address Bus)
RiW indicates whether the current bus cycle will be a
read or a write. If RiW is high. then the cycle will be a
read; if low, a write cycle. RiW has the same timing as
Ao-A23 and is not driven during HLOAK or while RESET is
asserted.
Ao-A23 form the 24-bit physical address bus. It is used to
access both the 16M-byte expanded and 1M-byte normal memory spaces and the 64K-byte 1/0 space. These
three-state outputs become valid during T1 of all bus
cycles and remain valid until after the bus cycle is
completed. During HLOAK and when RESET is active.
these outputs are not driven.
Do-D15 (Data Bus)
00-015 form the 16-bit data bus. which is used to transfer
16- and 8-bit data between the "P070136 and the external system. To accommodate 8-bit devices. dynamic bus
4
R/W (Read/Write)
M/iO (Memory/IO)
MIlO indicates whether the current bus cycle will be. an
access to the memory or 1/0 space. If MIlO is high,
access will be to memory; if low. to the I/O space. MIlO is
used with SUSSTO and SUSST1 to identify the cycle type.
MIlO has the same timing as Ao-A23 and is not driven
during HLOAK or while RESET is asserted.
NEe
pPD70136 (V33)
BUSSTO-BUSST1 (Bus Cycle Status)
BUSLOCK (Bus Lock)
BU.SSTO and BUSST1, in conjunction with M/IO and R~
identify the current cycle type as shown in table 3.
BUS LOCK should be used by external logic to exclude
any other bus master (e.g., a DMAcontroller) from using
a shared resource that the I'PD70136 currently is using.
When BUSLOCK is asserted high, HLDRQ will beignored.
Table 3. Bus Cycle Types
Status
M/iQ
RNi
0
0
BUSST1
BUSSTO
0
0
0
0
1
0
0
0
0
I/O write
0
0
Coprocessor read
0
Coprocessor write
0
Instruction fetch
HALT acknowledge
1
0
1
0
0
0
0
Interrupt acknowledge
I/O read
0
0
Type of Bus Cycle
Memory. read
Memory write
0
CP data read
0
CP data write
Note: All bus status signals change after the start of the T1 state.
The 11 cycle types are described in detail in the bu.s
cycles section. The remaining five combinations of these
inputs are reserved for future use.
BUSSTO-BUSST1 have the same timing as the address
bus, Ao-A23' and are not driven during HLDAK or while
RESET is asserted.
BUS LOCK is asserted when the BUSLOCK prefix is
executed or when the I'PD70136 is performing a bus
operation that must not be interfered with, such as an
interrupt acknowledge cycle. BUS LOCK has the same
timing as the address bus AO-A23· and is driven high
during HLDAK and RESET.
READY (System Ready)
READY is asserted low when the external system is
ready for the current bus cycle to terminate. While
READY is not asserted, the I'PD70136 will·add TW (wait)
states to the current bus cycle. The bus state in which
READY is sampled low wi II be the last state of the cycle.
READY is used during CPU read cycles to give slow
devices time to drive the Do-D7 inputs, and during write
cycles to give slow devices enough time to finish the
write operation.
READY is sampled on the rising (middle) edge Of T2 and
all TW states. READY is ignored during the HLDAK state.
This input is not internally synchronized. To ensure
proper device operation, minimum setup and hold times
must be met.
BCYST (Bus Cycle Start).
BCYST indicates the start of a bus cycle. It is asserted
low during T10t every bus cycle, and only for the first
clock period of each bus cycle. BCYST is not driven
during HLDAK or while RESET is asserted.
DSTB (Data Strobe)
DSTB indicates the status of the data on Do-D15. When
asserted low during a write cycle, the I'PD70136 drives
the write data on Do-D15. When the CPU asserts this
output during a read cycle, external logic should drive
the read data onto Do-D15'
DSTB is asserted following the rising edge (middle) of
T1, and stays asserted through T2 and any TW (wait)
state that may be inserted. During write cycles, DSTB
will be deasserted after the rising edge of either T2 or the
last wait state. During read cycles, DSTB is deasserted
after the trailing edge of T2 or the last wait state. DSTB
is not driven during HLDAK, HALT acknowledge cycles,
or while RESET is asserted.
BS8/BS16 (8-Bit Bus Size/16-Bit Bus Size)
BS8/BS16 is driven low by external logic when the
I'PD70136 addresses a device with an 8-bit data path. If
the I'PD70136 operand is 16 bits wide and BS8/BS16 is
low, then thel'PD70136 will perform two 8-bit bus
cycles. The current bus cyCle will handle the low byte on
Do-D7, and the next bus cycle wi II handle the upper byte
also on Do-D7' This input is ignored during HLDAK,
interrupt acknowledge, and coprocessor cycles.
BS8/BS16 is sampled on the rising (middle) edge of T2 or
the last TW state, coincident with READY. This input is
not internally synchronized. To ensure proper device
operation, minimum setup and hold times must be met.
AEX (Address Expansion)
AEX is asserted when the expanded addressing mode is
enabled. When AEX is high, the memory address space
is 16M bytes (24-bit address), and when low, 1M bytes
(20-bit address).
5
NEe
IIPD70136 (V33)
H LORQ (Hold Request)
HLDRQ is asserted high by external logic when an
external bus master (e.g., a DMA controller) wants to
take over the #,PD70136 bus. When HLDRQ is detected
high, the #,PD70136 will release the bus after the current
bus operation is completed. Note that this is not necessarily the current bus cycle. The #,PD70136 releases its
bus by floating the address, data, and control buses. See
table 1.
.
HLDRQ is sampled on the rising edge of each clock. It
will be ignored while BUSLOCK is asserted. This input is
not internally synchronized. To ensure proper device
operation, minimum setup and hold times must be met.
HLOAK (Hold Acknowledge)
NMI is sampled on the rising edge of. each clock. This
input is not internally synchronized. To ensure proper
device operation, minimum setup and hold times must
be met.
Once NMI is samped low, an internal flag is set, so that a
one-clock pulse meeting setup and hold times will be
recognized. The flag is cleared when the NMI is accepted
and can be set again immediately.
CPBUSY (Coprocessor Busy)
CPBUSY is asserted low by a coprocessor (such as
#,PD72291) when it is busy with an internal operation.
The #,PD70136 uses this pin to check the status of the
coprocessor.
HLDAK is asserted when the #,PD70136 enters the hold
acknowledge state in response to HLDRQ. Data, address, and control buses are not driven. See table 1.
CPBUSY is sampled on the falling edge of each clock.
This- input is not internally synchronized. To ensure
proper device operation, minimum setup and hold times
must be met.
INT (Interrupt Request)
CPERR (Coprocessor Error)
INT is asserted high by external logic to notify the CPU
that an external event has occurred that requires the
CPU's attention. After INT has been sampled high, and if
the IE (enable interrupts) bit in the PSW is high, interrupt
processing will begin after the current instruction is
completed.
'
CPERR is asserted low by a coprocessor to notify the
#,PD70136 of an error.
INT is sampled on the rising edge of each clock. After
being asserted high, INT must be kept high until the first
INTAK cycle begins. This input is not internally synchronized. To ensure proper device operation, minimum
setup and hold times must be met.
NMI (Nonmaskable Interrupt Request)
NMI is asserted by external logic to notify the CPU that
an external event has occurred which requires the CPU's
immediate attention. When NMI is sampled low, ,interrupt
processing will begin immediately after the current instruction is completed: A trap will be taken through
vector 2. The state of the IE bit in the PSW has no effect
on NM I acceptance.
6
CPERR is sampled on the falling edge of each clock. This
input is not internally synchronized. To ensure proper
device operation, minimum setup and hold times must
be met.
CPREQ (Coprocessor Request)
CPREQ is asserted high by a coprocessor to request the
#,PD70136 to run a memory operation for the coprocessor.
CPREQ is sampled on the falling edge of each clock. This
input is not internally synchronized. To ensure proper
device operation, minimum setup and hold times must
be met.
NEe
"PD70136 (V33)
RESET (Reset)
RESET is asserted high when external logic needs to
initialize the #,PD70136; for instance, after power-up.
When RESET is asserted for at least 6 clock periods, the
#,PD70136 wi II abort any current bus cycles and initialize
the registers as shown in table 4.
Table 4. Regi.ter Initl.,iZlltion by Reset
Regl8ter
OffaetValue
PFP
OOOOH
PC
OOOOH
PS
FFFFH
SS
OOOOH
eso
OOOOH
eS1
OOOOH
1514 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSW
11 11 11 11 10 10 10 10 10 10 10 10 10 10 11 10
Prefetch Queue
I
Cleared
Address Mode
Normal Address Mode
Other
Registers
Undefined Qf power has just been turned on)
Unchanged Qf power on, but RESET Is asserted)
Refer to table 1 for the state of the #,PD70136 outputs
during reset. When RESET is de asserted low, the
#,PD70136 will begin fetching from address OFFFFOH.
This input is not internally synchronized. To ensure
proper device operation, minimum setup and hold times
must be met.
7
NEe
pPDl0136. (V33)
"PD70136 Block Diagram
20
Address
Expansion
Control
24
AO-A23
DO-D15
LC
PC
AW
CLK. RESET. HLDRQ.
READY. BSSIBS1"6
HLDAK. BUSLOCK.
UBE.
Registerl
ALU
Control
RiW. M/iO.
BUSST1. BUSSTO.
Main Decoder
AEX. BCYST. DSTB
CPBUSY
CPERR
Execution
Control
Sub
Data Bus
Interrupt
Control
INT
NMI
Main
Data Bus
49NR-333B
8
NEe
pPD70136 (V33)
ELECTRICAL SPECIFICATIONS
Typ;CIII Supply Current VB Clock Frequency
Absolute Maximum Ratings
=- +25°C
200
TA
-0.5 to +7.0 V
Power supply voltage. Voo
150
Input voltage. VI
-0.5 V to Voo + 0.3 V
ClK Input voltage. VK
-0.5 Vto Voo + 1.0 V
Output voltage. Vo
-0.5 V to Voo + 0.3 V
---
[100)
Operating ' "
-~
Operating temperature. TOPT
Storage temperature. TSTG
50
~
[5)
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
~
~
~
I
Sta~dbY",
r-
4
8
10
Frequency [MHz]
6
16m
[25)
12
14
Capacitance
49NR-326A
TA- +25°C. Voo = 0 V
Parameter
Symbol
Max
Unit
Conditions
Input capacitance
CI
15
pF
fc = 1 MHz;
1/0 capacitance
CIO
15
pF
unmeasured pins
returned to 0 V.
DC Characteristics
TA .. -10 to +70°C. Voo =- +5 V :10%
Parameter
Symbol
Input voltage high
Min
Typ
2.2
Input voltage low
Max
Unit
Voo + 0.3
V
-0.5
0.8
V
ClK Input voltage high
0.8 Voo
Voo + 0.5
V
ClK Input voltage low
-0.5
0.6
Output voltage high
V
V
0.7Voo
Conditions
IOH-400 rnA
= 2.5 rnA
Output voltage low
0.45
V
Input leakage current high
-10
p.A
VI = Voo
Input leakage current low
10
p.A
VI =OV
Output leakage current high
10
p.A
Vo - Voo
Output leakage current low
-10
p.A
Vo
150
rnA
Normal operation
Standby mode
Supply current
100
= OV
16 MHz
100
25
35
rnA
12.5 MHz
75
110
rnA
Normal operation
20
30
rnA
Standby mode
200
p.A
Stop mode
(see graph)
*Stop mode current is not a function of CPU
clock frequency
10L
*
9
NEe
IIPD70136 .(V33)
AC Characteristics
TA
= -10 to
= 5 V ±10%; CL = 100 pF
+70·C; VOO
12.5-MHz Limits
Parameter
Symbol
Clock period
18 MHz-Limits
Min
Max
Min
Max
tcYK
80
500
62.5
500
Clock high-level width
tKKH
35
Clock low-level width
If INT > BRK flag> others at same level
Interrupts are not accepted during certain times. NMI,
INT and BRK flags are not accepted in these cases:
(1) Between execution of MOV or POP that uses a
segment register as an operand and the next instruction.
(2) Between a segment override prefix and the next
instruction
(3) Between a repeat or BUS LOCK prefix and the next
instruction
28
INT is not accepted when the PSW IE flag isO, or
between an RETI or POP PSW and the next instruction.
Figure 12 is a flow.diagram for processing interrupt
requests.·
.
Interrupt Vectors
Once an interrupt has been accepted, an interrupt service routine will be entered. The address of this routine is
specified by an interrupt vector, which is stored in the
interrupt vector table. For most interrupts, the vector
used depends on what interrupt is being processed (e.g.,
NMI always uses vector 2). For INT and BRK imm8
Interrupts, any vector may be used; the vector number is
supplied by an external device in the case of INT (e.g., a
p.PD71059), or by immediate data in the case of BRK.
Figure 13 is the interrupt vector table. The table uses 1K
bytes of memory-addresses OOOH to 3FFH-and stores
up to 256 vectors (4 bytes per vector).
NEe
IIPD70136 (V33)
Figure 12. Interrupt Prioritization Flow Diagram
Complete
current
instruction
*
If current instruction causes internal interrupt, SOFT flag
At the end of current instruction:
• If BRK flag in PSW = 1, BRK =1
• If INT from ICU is sampled, INT = 1
• If NMI input is sampled, NMI = 1
=1
Execute
next instruction
83YL·6327B
29
NEe
,.,PD70136 (V33)
Each interrupt vector consists of 4 bytes. The 2 bytes in
the low addresses of memory are loaded into PC as the
offset, and the 2 high bytes are loaded into PS as the
base address. Interrupt vector 0 in figure 14 is an example. The bytes are combined in reverse order. The lowerorder bytes in the vector become the most significant
bytes in the PC and PS, and the higher-order bytes
become the least significant.
Figure 14. Interrupt ",ctor 0
Based on this format, the contents of each vector should
be initialized at the beginning of the program. The basic
mechanism for servicing an interrupt is:
During interrupt servicing, the third item pushed on the
stack is the return PC value. For some types of traps
(divide error, CHKIND, illegal opcode, AFPP error, coprocesor not present, or other CP error), this value pOints
to the instruction that generated the trap. For the other
interrupts (single-step, BRK3, BRKV, NMI, or INT), this
value points to the next instruction. Trap handlers for
error traps can thus easily find the offending opcode,
and other handlers can simply return after processing
the interrupt.
(SP (SP (SP SP IE PS PC -
1, SP - 2) - PSW
3, SP - 4) - PS
5, SP - 6) - PC
SP-6
0, BRK-O
vector high bytes
vector low bytes
004H
008H
OOCH
010H
014H
018H
Vector 0
Divide Error
Vector 1
Break Flag
Vector 2
NMllnput
Vector 3
BRK 3 Instruction
Vector 4
BRKV Instruction
VectorS
CHKIND Instruction
::~
07CH
l::
j
1E8
H
... }
1_ _ _V_ec_t_or_1_22_~
204H
208H
...
'f
~
"-
""
200H
Vector 128
In the HALT standby mode, the internal clock is supplied
only to those circuits related to functions required to exit
this mode and bus hold control functions. As a result,
power consumption is reduced to one-fifth the level of
normal operation.
General Use
• BRK Imm8 Instruction
The HALT standby mode is exited when RESET or an
external interrupt (NMI, INT) is received. If INT is used
and interrupts were enabled before the HALT state was
entered, an INTAK cycle will be performed to fetch a
vector number. The interrupt service routine will be
executed. After RETI, execution will resume with the
instruction following the HALT. If interrupts were disabled, the interrupt service routine will not be entered,
but execution will resume with the instruction following
the HALT.
INT Input [External]
Undefined Instruction Trap
General Use
• BRK Imm8 Instruction
• INT Input [External]
I1PD72291 AFPP Error
Vector 129
Other Coprocessor Error
Vector 130
Coprocessor Does Not Exist
...
1
General Use
'f .BRK Imm8 Instruction
3FCH r~===v=ec=t=or=2=55===:!1
49NR·345A
HALT Standby Mode
I------i .
Vector 32
...
PC +- [001 H, OOOH]
PS +- [003H, 002H]
Dedicated
Vector 31
080H
002H
The ItPD70136 offers two standby modes to reduce
power consumption: HALT and STOP. Both are entered
after executing a HALT instruction.
tRe~NOO
Vector 6
OOOH
003H
STANDBY FUNCTION
Figure 13. Interrupt ",ctor Table
OOOH
Vector 0
001H
• INT Input [External]
49NR·332A
If NMI is used to exit the HALT standby mode, the NMI
service routine will always be entered.
The bus hold (HLDRQ/HLDAK) function still operates
during HALT standby mode. The CPU returns to HALT
standby mode when the bus hold request is removed.
During HALT standby mode, when all control outputs go
low, the address and data buses will be either high or
low. Refer to table 1 for information about the states of
other outputs in the standby mode.
30
NEe
pPD70136 (V33)
STOP Standby Mode
Enhanced Stack Operation Instructions
In the STOP standby mode, the ~PD70136 clock is
stopped for maximum power reduction. To enter this
mode, special steps must be taken .to prepare the
~PD70136 for having its clock stopped.
PUSH imm. This instruction allows immediate data to
be pushed onto the stack.
INT, NMI and HLDRQ must not be asserted while the
is in STOP mode, or for at least 10 clock
periods before STOP is entered, or for at least 10 clock
periods after STOP mode is exited. External hardware
must ensure that these intputs are not asserted during
this time.
~PD70136
STOP mode is entered by disabling NMI, INT, and
HLDRQ, entering the HALT standby mode, and stopping
the clock input 10 clock periods after the HALT acknowledge but cycle is issued. The eLK input must be stopped
during the low phase of the clock. STOP mode is exited
when external logic starts the clock, waits 10 clock
periods, and enable NMI, INT, and HLDRQ; the
~PD70136 will return to the HALT standby mode.
PUSH R; POP R. These instructions allow the contents
of the eight general registers to be pushed onto or
popped from the stack with a single instruction.
Enhanced Multiplication Instructions
MUL reg16, Imm16; MUL mem16, Imm16. These instructions allow the contents of a register or memory
location to be multiplied by immediate data.
Enhanced Shift and Rotate Instructions
SHL reg, imm8; SHR reg, imm8; SHRA reg, Imm8.
These instructions allow the contents of a register to be
shifted by the number of bits defined by the immediate
data.
All output pins in STOP mode are in the same state as in
HALT standby mode. Refer to table 1.
ROL reg, imm8; ROR reg imm8; ROLC reg, Imm8;
RORC reg, imm8. These instructions allow the contents
of a register to be rotated by the number of bits defined
by the immediate data.
INSTRUCTION SET HIGHLIGHTS
Check Array Boundary Instruction
Enhanced Instructions
In addition to the ~PD8088/86 instructions, the
has enhanced instructions listed in table 8.
~PD70136
Table 8. Enhanced Instruction
Instruction
Function
PUSH Imm
Pushes Immediate data onto stack
PUSHR
Pushes 8 general registers onto stack
POPR
Pops 8 general registers onto stack
MULLlmm
Executes 16·bit multiply of register or memory
contents by Immediate data
SHLlmm8
SHRlmm8
SHRAlmm8
ROLlmm8
RORlmm8
ROLClmm8
RORClmm8
Shifts/rotates register or memory by Immediate
value
CHKlND
Checks array Index against designated
boundaries
INM
Moves a string from an I/O port to memory
OUTM
Moves a string from memory to an I/O port
PREPARE
Allocates an area for a stack frame and copies
previous frame pointers
DISPOSE
Frees the current stack frame on a procedure exit
CHKINO reg16, mem32. This instruction is used to
verify that index values pointing to the elements of an
array data structure are within the defined range. See
figure 15. The lower limit of the array should be in
memory location mem32, the upper limit in mem32 + 2. If
the index value in reg16 is not between these limits when
CHKIND is executed, a BRK 5 will occur. This causes a
jump to the location in interrupt vector 5.
Figure 15. Check Array Boundary
Memory
UP"""mlt~
~
.
Array
.............. 15
~
~
0
mem32 + 2 (Upper limit)
........
LowerLimitk:-~"""""''''''''''''<'"'''''<''"''''''''''''''''''''''''....-.d'--or
mem32 (Lower Limit)
49NR-336A
Block I/O Instruction
OUTM ow, src-block; INM dlst-block, ow. These instructions are used to output or input a string to Qrfrom
memory, when preceded by a repeat prefix.
31
NEe
pPD70136 (V33)
Stack Frame Instruction
PREPARE Imm16,lmm8. This instruction is used to
generate the stack frames required by block-structured
languages. such as PASCAL and Ada. The stack frame
consh~ts of two areas. One area has a pointer that points
to another frame which has variables that the current
frame can access. The other is a local variable area for
the current procedure.
DISPOSE. This instruction releases that last stack frame
generated by the PREPARE instruction. It returl1s the
stack and base pOinters to the values they had before
the PREPARE instruction was used to call a procedure.
Unique Instructions
In addition to the "POSOSS/S6 instructions and the ,enhanced instructions. the "P070136 has the unique instructions listed in table 9.
INS reg8, reg8; INS reg8, Imm4. This instruction transfers low bits from the 16-bit AW register (the number of
bits is specified by the second operand) to the memory
location specified by the segment base (OS1 register)
plus the byte offset (IY register). The starting bit position
within this byte is specified as an offset by the lower 4
bits of the first operand. See figure 16.
After each complete data transfer. the IY register and the
register specified by the first operand are automatically
updated to pOint to the next bit field. .
Either immediate data or a register may specify the
number of bits transferred (second operand). Because
the maximum transferable bit length is 16 bits. only the
lower 4 bits of the specified register (OOH to OFH) will be
valid.
Bit field data may overlap the byte boundary of memory.
Figure 16. Bit Field Insertion
Table 9. Unique Instructions
Instruction
Function
INS
Insert bit field
EXT
Extract bit field
ADD4S
Adds packed decimal strings
S UB4S
Subtracts one packed decimal string from
another
CMP4S
Compares two packed decimal strings
ROL4
Rotates one BCD digit left through AL lower 4 bits
ROR4
Rotates one BCD digit right through AL lower 4 bits
BRKXA
Break and enable expanded addressing
RETXA
Return from break and disable expanded
addressing
TEsn
Non
Tests a specified bit and sets/resets Z flag
Inverts a specified bit
CLR1
Clears a specified bit
SET1
Sets a specified bit
REPC
Repeats next Instruction until CY flag Is cleared
REPNC
Repeats next Instruction until CY flag Is set
FP02
Additional floating-point processor call
variable Length Bit Field Operation Instructions
This category has two instructions: INS (Insert Bit Field)
and EXT (Extract Bit Field). These instructions are
highly effective for computer graphics and high-level
languages. They can, for example. be used for data
structures such as packed arrays and record type data
used in PASCAL.
32
Bit
Awl"
0
g
JJ.·rnme'1
Bit
By"
~~:--.--~--r-lt~~--+-t----lJtt.Me=~
:
OftootjlY]
1
Byte
Boundary
Segment Base .
[DS1]
49NR-341A
EXT reg8, reg8; EXT reg8, Imm4. This instruction
loads to the AW registers the bit field data whose bit
length is specified by the second operand of the instruction from the memory location that is specified by the
OSO segment register (segment base). the.lX Index
register (byte offset). and the lower 4 bits of the first
operand (bit offset). See figure 17.
After the transfer is complete. the IX register and the
lower 4 bits of the first operand are automatically updated to point to the next bit field.
Either immediate data or a register may be specified for
the second operand. Because the maximum transferable bit length is 16 bits. however. only the lower 4 bits of
the specified register (OOH to OFH) will be valid.
Bit field data may overlap the byte boundary of memory.
NEe
IIPD70136 (V33)
Figure 17. Bit Field Extrtlction
Bit
Byte
Bit
: • O~t.~.
~
Offseat[lXl
--jl
#~:-----rJ--+-_~--+-_
j
f
15
~
0
AW ,;.;:,;""-0-.....f%;.,..~.;--7I
BCD data and uses the lower 4 bits of the Al register
(ALL,) to rotate that data one BCD digit to the left. See
figure 18.
Byte
Boundary
;---r
I
Memory
Figure 18. BCD Rotate Left
Segment Base
[DS01
49NR-342A
Packed BCD Operation Instructions
The instructions described here process packed BCD
data either as strings (ADD4S. SUB4S. CMP4S) or byteformat operands (ROR4. ROl4). Packed BCD strings
may be from 1 to 254 digits in length.
When the number of digits is even. the zero (Z) and carry
(CY) flags will be set according to the result of the
operation. When the number of digits is odd. the Z and
CY flags may not be set correctly. In this case (Cl =
odd). the Z flag will not be set unless the upper 4 bits of
the highest byte are all Os. The CY flag will not be set
unless there· is a carry out of the upper 4 bits of the
highest byte. When Cl is odd. the contents of the upper
4 bits of the highest byte of the result are undefined.
ADD4S. This instruction adds the packed BCD string
addressed by the IX index register to the packed BCD
string addressed by the IY index register. and stores the
result in the string addressed by the IY register. The
length of the string (number of BCD digits) is specified
by the Cl register. and the result of the operation will
affect the V (overflow). CY, and Z flags.
BCD string (IY, Cl) - BCD string (IY, Cl)
(IX. Cl)
+ BCD string
SUB4S. This instruction subtracts the packed BCD
string addressed by the IX index register from the
packed BCD string addressed by the IV register. and
stores the result in the string addressed by the IV
register. The length of the string (number of BCD digits)
is specified by the Cl register. and the result of the
operation will affect the V.CY, and Z flags.
BCD string (IY, Cl) - BCD string (IY, Cl) -- BCD string
(IX. Cl)
CMP4S. This instruction performs the same operation
as SUB4S except that the result is not stored and only
the V. CY, and Z flags are affected.
BCD string (IY, Cl) -- BCD string (IX. Cl)
ROL4. This instruction treats the byte data of the register or memory operand specified by the instruction as
ROR4. This instruction treats the byte data of the register or memory specified by the instruction as BCD data
and uses the lower 4 bits of the Al register (ALL,) to rotate ~_
that data one BCD digit to the right. See figure 19.
~
Figure 19. BCD Rotate Right
Bit Manipulation Instructions
TEST1. This instruction tests a specific bit in a register
or memory location. If the bit is 1. the Z flag is reset to O.
If the bit is O. the Z flag is set to 1.
NOT1. This instruction inverts a specific bit in a register
or memory location.
CLR1. This instruction clears a specific bit in a register
or memory location.
SET1. This instruction sets a specific bit in a register or
memory location.
Repeat Prefix Instructions
REPC. This instruction causes the #,PD70136 to repeat
the following primitive block transfer instruction until
the CY flag becomes cleared or the CW register becomes zero.
REPNC. This instruction causes the p,PD70136 to repeat
the following primitive block transfer instruction until
the CY flag becomes set or the CW register becomes
zero.
Address Expansion Control Instructions
BRKXA ImmS. This instruction is used to turn on expanded addressing. The 8-bit immediate data specifies
an interrupt vector. The PC field of this vector is loaded
into the PC (and PFP). The XA flag in the XAM register is
set to 1. thereby enabling the expanded addressing
33
ttlEC
pPD70136 (V33)
mode. The p.PD70136 will begin fetching from the new
PFP through the address translation table. That is, the
new PC is treated as a logical address and is translated
to the new, larger physical address space.
(5) When processing a divide error, the p.PD70116 saves
the address of the next instruction. The p.PD70136
saves the address of the current instruction (the
divide instruction).
This instruction does not save any return address information, such as PC, PS, or PSW to the stack.
(6) The p.PD70116 allows up to 3 prefix instructions in
any combination. The p.PD70136 also allows 3 prefixes, but only one of each type can be used. The
p.PD70136 could operate incorrectly if there are two
prefixes of the same type. For example, consider:
RETXA ImmB. This instruction is' used to turn off expanded addressing. It is identical in operation to BRKXA,
except that the expanded addressing mode is turned off
before fetching from the new address. That is, the XA flag
in the XAM register is set to 0, and the PC is loaded with
the value of the PC field in the interrupt vector selected
by the immediate data.
This instruction does not save any return address information such as PC, PS, or PSW to the stack.
Porting I'PD70116n0108 Code to I'PD70136
The p.PD70136 is completely software compatible with
the p.PD70116/70108. However, the p.PD70136 offers
some improvements that may affect the porting of
p.PD70116 code to the p.PD70136. These improvements
are:
(1) The p.PD70116 does not trap on undefined opcodes.
The p.PD70136 will trap, and also will trap when a
register addressing mode is used for any of these
instructions:
CHKIND
MOV DSO/DS1
CALL 1,id
LDEA
BR 1,id
(2) During signed division (DIV), if the quotient is 80H
(byte operation) or 8000H (word), the p.PD70116 will
take a Divide By 0 trap. The p.PD70136 will perform
the calculation.
(3) When the p.PD70116 executes the POLL instruction,
it will wait for the POLL input signal to be asserted.
The p.PD70136 has no POLL input; instead, when this
instruction is executed, if a coproce$sor is not
connected, then a Coprocessor Not Present trap will
be taken. If a coprocessor is attached, then no
, operation takes place.
The p.PD70116 accepts FP01 and FP02 as opcodes
for the iAPX8087 coprocessor. The p.PD70136 accepts these as opcodes for the p.PD72291 coprocessor, which is not compatible with the iAPX8087.
(4) D!.ning the POP R instruction, the p.PD70116 does
. not restore the SP register. The p.PD70136 does
restore the gP.
34
REP
REPC
CMPBK SS: src-block, dst-block
If the compare operation is interrupted, then when it
resumes following the interrupt service, execution
will begin at the REPC instruction, not the REP
instruction, because two repeat prefixes were used.
(7) The p.PD70116 accepts NMI requests even while
processin~NMI. The p.PD70136 does not allow
nes!!n9..of NMls; the NMI input will be ignored until
the NMI interrupt handler is exited.
INSTRUCTION SET
Symbols
Preceding the instruction· set, several tables explain
symbols, abbreviations, and codes.
Clocks
In the Clocks column of the instruction set, the numbers
cover these operations: instruction decoding, effective
address calculation, operand fetch, and instruction execution.
Clock timings assume the instruction has been
prefetched and is present in the 8-byte instruction
queue. Otherwise, add two clocks for each pair of bytes
not present.
Word operands require two additional clocks for each
transfer to an unaligned (odd address) memory operand.
These times are shown on the right side of the slash (/).
For conditional control transfer or branch instructions,
the number on the left side of the slash is applicable if the
transfer or branch takes place. The number on the right
side is applicable if it does not take place.
If a range of numbers is given, the execution time
depends on the operands involved.
N'EC
pPD70136 (V33)
Symbols
Symbol
Meaning
Symbol
Meaning
acc
Accumulator(AW or AL)
AW
Accumulator (16 bits)
duso
Displacement (8 or 16 bits)
BH
BW register (high byte)
dmem
Direct memory address
BL
BW register (low byte)
dst
Destination operand or address
ext-disp8
16-blt displacement (sign-extension byte
bit displacement)
far_label
Label within a different program segment
far_proc
Procedure within a different program segment
fp_op
Floating-point Instruction operation·
imm
8- or 16-blt Immediate operand
imm3/4
3- or 4-bit Immediate bit offset
imm8
8-bit immediate operand
+ 8-
imm16
16-bit Immediate operand
mem
Memory field (000 to 111): 8- or 16-bit memory
location
mem8
8-blt memory location
mem16
16-bit memory location
mem32
32-bit memory location
memptr16
memptr32
Word containing the destination address within
the current segment
Double word containing a destination address in
another segment
mod
Mode field (00 to 10)
neaclabel
Label within the current segment
neacproc
Procedure within the current segment
offset
Immediate offset data (16 bits)
BP
BP register
BRK
Break flag
BW
BW register (16 bits)
CH
CW register (high byte)
CL
CW register (low byte)
CW
CW register (16 bits)
CY
Carry flag
DH
DW register (hIgh byte)
DIR
Direction flag
DL
DW register Oow byte)
DSO
Data segment 0 register (16 bits)
DS1
Data segment 1 register (16 bits)
DW
DW register (16 bits)
IE
Interrupt enable flag
IX
Index register (source) (16 bits)
IY
Index register (destination) (16 bits)
MD
Mode flag
P
Parity flag
PC
Program counter (16 bits)
PS
Program segment register (16 bits)
PSW
Program status word (16 bits)
R
Register set
S
Sign extend operand field
S No sign extension
S = Sign extend immediate byte operand
pop_value
Number of bytes to discard from the stack
reg
Register field (000 to 111): 8- or 16-bit generalpurpose register
reg8
8-bit general-purpose register
S
Sign flag
reg16
16-bit general-purpose register
SP
Stack pointer (16 bits)
regptr
16-bit register containing a destination address
within the current segment
SS
Stack segment register (16 bits)
=
V
Overflow flag
regptr16
Register containing a destination address within
the current segment
W
Word/byte field (0 to 1)
seg
Immediate segment data (16 bits)
X,XXX,
YYY, ZZZ
Data to identify the Instruction code of the
external floating-point arithmetic chip
shorLJabel
Label between -128 and + 127 bytes from the
end of the current Instruction
XXH
Two-digit hexadecimal value
sr
Segment register
src
Source operand or address
temp
Temporary register (8116/32 bits)
AC
Auxiliary carry flag
AH
Accumulator (hIgh byte)
AL
Accumulator (low byte)
II
XXXXH
Four-digit hexadecimal value
Z
Zero flag
35
NEe
pPD70136 (V33)
Register Selection (mod = 11)
Flag Operations
Symbol
MeanIng
reg
w =0
W =1
(blank)
No change
000
AL
AW
o
Cleared to 0
001
CL
CW
Set to 1
010
OL
ow
x
Set or cleared according to result
011
BL
BW
u
Undefined
100
AH
SP
R
Restored to previous state
101
CH
BP
110
OH
BH
IX
Memory Addressing Modes
mem
mod
= 00
mod
= 01
mod
111
= 10
IV
Segment Register Selection
BW + IX
BW + IX + dlsp8
BW + IX + dlsp16
000
--------------------------------------~
BW + IV + disp16
001
BW + IV
BW + IV + dlsp8
_sr_ _ _ _ _ _S_e..;:g~m_e_nt_R_e...;;g~ls_te_r_ _ _ _ _ _ _ __
BP + IX + dlsp16
_00_____________
0_S1_________________________
010
BP + IX
BP + IX + dlsp8
011
BP + IV
BP
100
IX
IX + dlsp8
IX + disp16
+ IV +
~+N+~p~
dlspS
101
IV
IV + disp8
IV + disp16
110
Oirect
BP + disp8
BP + dlsp16
111
BW
BW + dlsp8
BW + dlsp16
~
~
11
OSO
----------------------------------------_10_____________
SS
___________________________
----------------------------
Instruction Set
Flags
Opcode
Mnemonic
Operand
7
6
5
4
3
2
1
0
7
6 5
4
3
2
1 0
Clocks
Bytes
AC
CY V
P S
Z
Dsts Trsnsfer Instructions
MOV
reg, reg
W
reg
reg
2
2
o
000
--~~------~--------------------------~----~----------------------------mod
reg
mem
3/5
2-4
mem, reg
000100W
reg, mem
o
0
0
1
mem,lmm
1 0
0
0
reg, imm
o
o
o
o
o
o
o
acc, dmem
dmem, acc
sr, reg16
sr, mem16
reg16, sr
0
1 0
0
0
0
0
0 0
mem
5/7
2-4
000
mem
3/5
3-6
0
2
2-3
W
5/7
3
W
3/5
3
0
1 1 0
sr
reg
1
0
mod
0
sr
mem
0
0
1 1 0
sr
reg
sr
2
5/7
2
2
2-4
2
0
()
1
00
modO
mem
3/5
2-4
0
0
mod
reg
mem
10/14
2-4
OS1, reg16, mem32
1 0
0
0
o
o
mod
reg
mem
10/14
2-4
AH, PSW
0
0
. 0
0
1 0
0
reg16, mem16
TRANS
reg, reg
mem, reg
36
0
0
reg
mod
reg
0
0
mod
W
o
PSw, AH
XCH
1 W
W
OSO, reg16, mem32
mem16, sr
LOEA
0
o
1 0
0
.1
2
o
0
1
1 0
mod
reg
mem
o
0
0 0
0
W
1
1
reg
reg
0
0
W
mod
reg
mem
0
x
2
0
2
2-4
5
3
8/12
2
2-4
x
x x x
NEe
IIPD70136 (V33)
Instruction Set (cont)
Opcode
Mnemonic
Operand
7
6
2
1
0
7
Flags
5
4
3
6
5
4
3
2
1 0
0
1
0
reg
o
o
0
o
1
2
0
o
0
2
Bytes AC
Clocks
CY V
P S Z
Dsts Trsnsfer Instructions (cont)
XCH (cont)
AW, reg16
1 0
3
Repest Prefixes
REPC
o
REPNC
o
REP
REPE
REPZ
REPNE
REPNZ
1
1
1
1
o
0
0
0
2
1
0
2
Block Trsnsfer Instructions
MOVBK
CMPBK
CMPM
dst, src
dst, src
dst
1010010W
1
3
3
3
3
+
+
+
+
4n
4n
8n
6n
fY'/
fY'/
fY'/
fY'/
=
=
=
=
0)
1, even addresses)
1, odd addresses)
1, odd/even addresses)
3
3
3
3
+
+
+
+
7n fY'/ = 0)
7n fY'/ = 1, even addresses)
11n fY'/ = 1, odd addresses)
9n fY'/ = 1, odd/even addresses)
1
1010011W
1010111W
1
x
x
xxxxx
xxxxx
3 + 5n fY'/ = 0)
3 + 5n fY'/ = 1, even addresses)
3 + 7n fY'/ = 1, odd addresses)
LOM;
src
1010110W
1
5 +2nfY'/= 0)
5 + 2n fY'/ = 1, even addresses)
5 + 4n fY'/ = 1, odd addresses)
STM
dst
1010101W
1
3 +2nfY'/= 0)
3 + 2n fY'/ = 1, even addresses)
3 + 4n fY'/ = 1, odd addresses)
n = number of returns
String Instruction execution clocks for a single-Instruction execution are In parentheses.
I/O Instructions
IN
OUT
ace,Imm8
0
acc, OW
0
Imm8, ace
0
Ow, ace
0
0
0
0
W
5/7
0
W
3/5
W
3/5
2
W
3/5
1
2
37
NEe
IIPD70136 (V33)
Instruction Set (cont)
Opcode
MnemonIc
Operand
7
6
5
4
3
2
1
0
7
Flags
6
5
4
3
2
1
0
Clocks
Bytes AC
CY V
P
S Z
I/O Instructions (cont)
INM
OUTM
dst, OW
Ow. src
1
0110110W
3
3
3
3
+ 11n ~ = 0)
+ 8n ~ = 1, even addresses)
+ 22n ~ = 1, odd addresses)
+ 20n ~ = 1, odd/even addresses;
3
+
3
3
3
3
+ 11n ~ = 0)
+ 8n ~ = 1, even addresses)
+ 22n ~ = 1, odd addresses)
+ 20n ~ = 1, odd addresses;
3
+
odd for I/O)
13n ~ = 1, odd/even addresses;
odd for memory)
0110111W
1
odd for I/O)
13n ~ = 1, odd addresses;
odd for memory)
n = number of transfers
String instruction execution clocks for a single-Instruction execution are In parentheses.
Use the right side of the slash (J) for OMA I/O accesses.
BCD Instructions
ADJBA
0
0
1
0
4
x
x
u
u
u
u
ADJ4A
0
0
0
0
2
x
x
u
x
x
x
ADJBS
0
0
1
4
u
u
u
0
0
0
2
x
x
u
ADJ4S
u
x x x
u u x
u u x
u u x
18n
2
u
18n
2
u
14n
2
u
x
x
x
x
x
2
u
u
u
2
u
u
u
1
+
+
+
ADD4S
dst, src
0
0
0
0
0
0
0
0
0
0
2
SUB4S
dst, src
0
0
0
0
0
0
0
0
0
0
2
CMP4S
dst, src
0
0
0
0
0
0
0
0
1
1 0
7
ROL4
reg8
0
0
0
0
1
0
0
0
0
0
0
9
0
0
0
reg
mem8
0
0
0
0
0
0
0
0
0
0
15
3-5
mod
0
0
0
mem
0
0
0
0
0
0
0
0
0
13
3
1
1 0
0
0
reg
0
0
0
0
1
0
0
0
0
0
19
3-5
mod
0
0
0
0
0
0
0
0
0
12
0
0
0
0
0
0 8
ROR4
reg8
mem8
0
u
u
u
3
mem
n = number of BCD digits divided by 2
Dsts Type Conversion Instructions
CVTBD
1
1 0
0
0
0
0
0
CVTDB
CVTBW
0
0
0
0
CVTWL
0 0
0
0
38
0
0
2
2
x x x
x x x
t\fEC
pPD70136 (V33)
Instruction Set (cont)
Flags
Opcode
Mnemonic
Operand
7
6
5
4
3
2
1
0
7
6
W
11
5
4
3
2
1 0
Bytes
AC
2
x
xxxxx
6/8
2-4
2
3-4
7/11
3-6
2
2-3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Clocks
CV V
p
S Z
Arithmetic Instructions
ADD
ADDC
SUB
reg, reg
000000
reg, mem
0000001W
reg, imm
OOOOOSW
mem, inim
100000SW
aoc, imm
00000
reg, reg
00000
mem, reg
000
reg, mem
2
0
reg
mod
0
0
0
mem
OW
1
reg
reg
OOOW
mod
reg
mem
7/11
2-4
mod
reg
mem
6/8
2-4
x
x
x
0001001W
x
x
W
1
1
1
0
1 0
reg
mod
0
1 0
mem
2
2
3-4
x
7/11
3-6
x
2
2-3
2
2
x
x
x
x
x
x
x
reg
0 W
mod
reg
mem
7/11
2-4
W
mod
reg
mem
6/8
2-4
x
x
x
x
2
3-4
x
x
x x x x
7/11
3-6
x
x x x x
2
2-3
x
x
x
x x x x
2
2
x
x
x x x x
o 0
o a
a a
0
W
a
0
0
a
1
x
x
x
x
reg, imm
OOOOOSW
1
1
a
reg
mem,imm
OOOOOSW
mod
0
mem
1
reg
reg
mod
reg
mem
7/11
2-4
x
x
x x x x
mod
reg
mem
6/8
2-4
x
x
x x x x
1
reg
2
3-4
x
x
x x x x
7/11
3-6
x x x x
2
2-3
x
x x x x
2
2
x
x
x
x
x
x
x
x
reg, reg
o a
a
o a a
a
mem, reg
000
OOW
0
W
W
000110
W
OOOOOSW
mem,imm
100000SW
acc, imm
a a a
a
reg8
mem
reg16
o
o
1
1
0
a
1
reg16
o
1
a a
a
reg16
a
o
1
reg8
reg16
mem8
mem16
1
1
reg16, reg16, imm8
a
o
0
mod
0
1
a
1
1
0
0
0
reg
W
mod
0
0
0
mem
mem
W
a
7/11
2-4
2
o
1
W
mod
1 0
0
0
reg
0
mem
2
7/11
2
2-4
x x x x
x x x x
x x x x
x x x x
x
2
x x x x
reg
8
2
u
x
x
o
0
reg
12
2
u
x
x u u u
mod
0
0
mem
12
2-4
u
x
x
u
u u
mod
a a
a
a
mem
16/18
2-4
u
x
x
u
u u
o
o
x x x x
o 0
0
o
a
a
a
a
mem16
1
reg
reg8
mem8
1
~g
regS
mem
1
mod
1
mod
0
1
1
u
u
u
reg
8
2
u
x
x
u
u u
reg
12
2
u
x
x
u
u u
o
a
mem
12
2-4
u
x
x
u
u u
mem
16/18
2-4
u
x
x
u
u u
reg
reg
3
u
x
x
u
u u
12
1:9!11
x~
reg
000010W
reg, reg
0
2
1
acc, imm
reg,imm
MUL
0
OOOOOSW
reg, mem
MULU
mem
0
OOOOOSW
acc, imm
DEC
reg
1
reg,imm
reg, mem
INC
mod
1
mem, imm
mem, reg
SUBC
reg
reg
----------------------------------------------------------------------------------2-4
mem, reg
mem
7/11
x x x x x x
OOOOOOOW
mod
reg
39
NEe
pPD70136 (V33)
Instruction Set (cont)
Flags
Opcode
Mnemonic
Operand
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1 0
Clocks
Bytes
AC
3-5
u
CY V
P
S
Z
u
u
u
Arithmetic Instructions (cont)
MUL
(cont)
reg16, mem16,
Imm8
o
0
o
mod
reg
mem
16/18
x
x
-------------------------------------------------------------------------------reg16, reg16,
1 1
reg
reg
12
4
u
xxuuu
o
o 0
o
Imm16
reg16, mem16,
Imm16
DIVU
DIV
o
o
o
0
mod
o
o
o
reg16
mem8
o
mem16
o
o
o
o
o
reg8
reg8
reg16
mem8
mem16
reg
mem
16/8
4-6
u
x
x
u
u
u
1
1
11
2
u
u
u
u
u
u
1
o
o
reg
1
reg
19
2
u
u
u
u
u
u
o
mod
o
mem
15
2-4
u
u
u
u
u
u
1
mod
o
mem
23/25
2-4
U
U
U
U
U
U
o
1
2
U
UUUUU
1
o
reg
16
1 1
reg
24
2
U
UUUUU
mod
mem
20
2-4
U
U
U
U
U
U
mod
mem
28/30
2-4
U
U
U
U
U
U
2
x
x
x
x
x
x
1
Compsrlson Instructions
CMP
reg, reg
0 0
reg, mem
0 0
0
1 W
W
1
1
reg
reg
mod
reg
mem
2
-------------------------------------------------------------------------------mem, reg
0 0
0 0 W
mod
reg
mem
6/8
2-4
x
x x x x x
1
1
0
0 0 0
0
0 S W
1
mem, Imm
1 0 0 0
0
0 S W
mod
ace, Imm
0 0
reg, Imm
1
reg
mem
0 W
6/8
2-4
x
x
x
x
x
x
2
3-4
x
x
x
x
x
x
6/8
3-6
x
x
x
x
x
x
2
2-3
x
x
x
x
x
x
Logicsllnstructlons
NOT
NEG
reg
0
W
1 1 0
0
reg
2
2
--~------------------------------------------~----------------------------mem
0
W
mod 0
0
mem
7/11
2-4
reg
mem
TEST
mod
1 0
reg
0
mem
o
0 0
0
0 W
1
1
reg
reg
o
0 0
0
0 W
mod
reg
mem
o
o
W
1
1 W
1
1 0 0 0
modOOO
reg
mem
2
7/11
2
x
x
x
x
x
x
2-4
x
x
x
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x x x
0
2
U
6/8
2-4
U
2
3-4
U
6/8
3-6
U
2
2-3
U
o
o
o
o
o
x
x
x
2
2
U
0
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
2
ace,lmm
100100W
reg, reg
o
0001W
11
reg
reg
mem, reg
OOOOOOW
mod
reg
mem
7/11
2-4
U
reg, mem
000001W
mod
reg
mem
6/8
2-4
U
2
3-4
U
7/11
3-6
U
o
o
o
o
2
2-3
U
0
2
U
OOxxx
2-4
U
0
reg,lmm
40
1
reg, reg
mem,lmm
OR
W
W
mem, reg
reg,lmm
AND
o
o
0
OOOOOOW
mem,lmm
1000000W
acc,lmm
0000
reg, reg
00000
mem, reg
0000
1
1
mod
o
o
0
reg
0
mem
10W
W
11
reg
reg
OOW
mod
reg
mem
2
7/11
0
x
x
x
NEe
pPD70136 (V33)
Instruction Set (cont)
Opcode
Mnemonic
Operand
7
6
5
4
3
2
0
0
0
0
1
0
1
Flags
0
7
6
W
mod
mod
5
4
3
2
1 0
Clocks
Bytes
AC
CY V
P
S
Z
Logical Instructions (cont)
OR (cont)
reg, mem
0
0 0
0
0
0
W
ace, Imm
0
0
0
1
1 0
W
reg, reg
0
0
0
0
reg, mem
001a01W
mem,lmm
XOR
reg
mem
6/8
2-4
u
0
0
x
x
x
0
mem
7/11
3-6
u
0
0
x
x
x
2
2-3
u
0
0
x
x
x
2
2
u
0
0
x
x x
o
x x x
o x x x I:JI!II
o x x x~
o
x
x x
-------------------------------------------------------------------------------reg, Imm
0 a 0 0 0 0 W
1 1 0 0
reg
2
3-4
u
0
0 x x x
a
1 W
1
0
1
reg
mod
reg
reg
-------------------------------------------------------------------------------mem, reg
o 0
a a 0 W
mod
reg
mem
7/11
2-4
u
0 0 x x x
reg,lmm
oaoaoow
mem, imm
100aOOOw
acc,lmm
o
a
0
a
mem
1
o
mod
1 0
1
reg
mem
W
6/8
2-4
u
2
3-4
u
7/11
3-6
u
2
2-3
u
o
o
o
o
3
u
0
0
u
u
x
3-5
u
0
0
u
u
x
3-5
u
0
0
u
u
x
4
u
OOuux
13
4-6
u
0
a
u
u
B/10
4-6
u
0
0
u
u x
Bit Manipulation Instructions
INS
reg8, regS
0
0
0
0
001
reg
regS,lmm4
EXT
reg8, reg8
reg8, imm4
000
0
1
a
1 0
000
a
1
reg
o
0
1
TEST1
reg, CL
o
0
1
memB, CL
mem16, CL
reg, imm3/4
memB,lmm3
mem16,lmm4
SET1
reg, CL
mem,CL
o
0
0
1
0
0
0
0
0
1
0
0
0
0
a
1
0
0
0
0
0
mod
0
a
0
0
0
1
mod
0
0
0
0
0
0
mod
0
0
o
0
0
1
1 1 0 0
a
mem8,lmm3
0
1
1 0
a a
o
a
a
a
mod
a
0
0
o
0
29-61/
4
33-63
000
o
0
0
000
a
0
008
000
000
000
o
0
W 4
000
o
0
0
000
o a
W 4
B/10
x
1
mem
o a
0
o
a
W 4
3
000
o
o
W 9
3-5
o
W 4
4
reg
0
o
3
mem
1
0
modaaO
reg,lmm3/4
1
reg
o
a
29-61/
mem
0
0
0
0
o 0
reg
mem
1 0
4
33-63
o
1
1
o
37-69/
reg
0
000
3
39-77
o a
0
0
o a
0
reg
reg
0
o
37-61/
39-77
o
0
mod
o
1 000
reg
mem
o a 0
1
a
reg
a
mem
o a
0
1
1
009
4-6
41
NEe
pPD70136 (V33)
Instruction Set (cont)
Opcode
Mnemonic
Operand
7
6
5
4
3
2
0
0
1
0
1
1
0
Flags
7
6
5
4
3
2
1 0
o
0
0
1
1
1 0
Clocks
Bytes
AC
CY V
P S
Z
Bit Manipulation Instructions (cont)
SET1
(cont)
mem16, Imm4
0 0
mod
0
0
DIR
1
1
1
reg, CL
o
0 0
0
1
1
1 0
0
0
reg
o
0
0
0
mod
0
0
0
mem
o
CY
CLR1
memS, CL
mem16, CL
reg,lmm3/4
memS,imm3
mem16,lmm4
CY
reg,CL
memS, CL
mem16, CL
0
memS,lmm3
mem16,lmm4
0
o
0
0
0
1
1
1 0
0
0
o
0
0
0
1
1
mod
0
0
0
mem
0
mod
0
1
0
0
o
0 0
0
1
1 0
0
0
o
0
0
0
1
mod
0
0
0
1
0
3-5
9/13
3-5
000
o
W 4
4
O' 0
0
o
o 9
4-6
000
o
4-6
9/13
000
o
W4
000
o
o
000
o
o
3
9
3-5
9/13
3-5
mem
1
0
reg
0
mem
0000111
1
o
9
mem
0
1
000
3
reg
0
0
o
2
0
0
0
2
1 0
0
o
0
0
0
000
0
1
0
W4
0
o
mod
0
o
0000111
000
o
mem
1
1
000
reg
1
o
4-6
mem
0
1
1
mod
CY
2
1
modOOO
reg, imm3/4
2
0
mod
000
1 9/13
0
0000111
DIR
NOT1
1
mem
0
000
W 4
4
000
W 9
4-6
000
4-6
9/13
mem
0
1 0
1
0
0
0 W
1
1
0
0
x
2
Shift/Rotste Instructions
SHL
42
reg, 1
0
reg
2
2
u
x
x
x
x
x
-------------------------------------------------------------------------------mem, 1
0
0 0 0 W
mod
0 0
mem
7/11
2-4
u
x x x x x
reg, CL
0
0
0
W
1
1
0
0
reg
mem, CL
0
1
0
0
W
mod
0
0
mem
reg, ImmS
0
0
0
0
0 W
1
0
0
reg
1
2
+n
+
+n
n
= number of shifts
2
6/10
n
2
u
x
u
x
x
x
2-4
u
x
u
x
x
x
3
u
x
u
x
x
x
NEe
pPD70136 (V33)
Instruction Set (cont)
Opcode
Mnemonic
Operand
7
6
5
4
o
o
0
3
2
1
o
7
Flags
6
5
4
3
0
2
1 0
Clocks
Bytes AC
CV
V
P
S Z
x
x
x
x
u
x
x
u
u
u
u
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Shift/Rotste Instructions (cont)
SHL (cont)
mem.lmm8
SHR
reg. 1
SHRA
ROL
W
mod
o
W
1
1
o
reg
0
mem
o
0
0
W
mod
0
mem
0
0
W
1 1
0
reg
mem.CL
o
o
0
0
1 W
mod
0
mem
reg.lmm8
o
0
0
0
0
W
1
1
0
reg
mem.lmmS
o
o
0
0
0
0
W
mod
0
mem
reg. 1
0
0
0
W
1
mem.1
o
0
0
0
W
mod
reg. CL
o
0
W
1
mem.CL
o
o
0
0
1 W
mod
reg. imm8
o
0
0
0
0
W
1
mem.immS
0
0
0
0
W
mod
1
0
0
0
W
1
0
0
0
0
W
modOOO
reg. CL
o
o
o
o
0
0
W
1
1
0
0
0
reg
mem.CL
o
0
0
W
mod
0
0
0
mem
reg.lmm
o
0
0
0
0
W
1
0
0
0
reg
mem.imm
o
0
0
0
0
W
modOOO
reg. 1
0
0
0
W
1
1
0
0
reg
mem.1
o
o
0
0
0
W
mod
0
0
mem
reg. 1
reg
1
mem
reg
1
mem
reg
1
1
1
mem
0
0
reg
mem
mem
reg. CL
000
W
1
1
0
0
reg
mem.CL
000
W
mod
0
0
mem
reg.imm8
1 0
0
reg
0
mem
reg. 1
o
o
o
mem.1
o
reg. CL
mem.immS
o
o
o
o
reg. 1
0
0
0
0
W
1
0
0
0
0
W
mod
0
o
0
0
W
1
1
0
0
reg
o
0
0
W
mod
0
0
mem
o
0
W
1
0
0
W
mod
0
0
0
0
W
1
0
0
0
0
W
mod
0
o
0
0
0
W
1
0
mem.1
o
OOOW
reg. CL
000
W
110
reg
mem.CL
0100
W
modO
mem
reg. imm8
o
W
110
reg
mem.CL
reg.lmm8
RORC
0
0
reg. CL
mem. immS
ROLC
0
0
mem.1
mem.1
ROR
0
0
1
0
0
0
0
1 0
0
reg
0
0
mem
1 0
0
reg
0
mem
1
modO
reg
mem
6/10 + n
2
3-5
u
2
u
2-4
u
+n
2
u
6/10 + n
2-4
u
x
3
u
3-5
u
2
u
2-4
u
2
u
7/11
2
+n
2
x
x
x
x
x
x
x
x
x
x
x
6/10 + n
2-4
x
u
3
u
x
3
x
x
x
x
x
x
x
3-5
x
u
2
x
2-4
x
x
2+n
6/10 + n
2
7/11
2+n
2-4
u
+n
3
u
6/10 + n
3-5
u
6/10 + n
2
2
2
7/11
2
2+n
2-4
6/10 + n
3-5
+n
2
2
7/11
2-4
+n
2
6/10 + n
2-4
7
2+n
6/10 + n
2
o
o
u
u
u
u
x
u
u
u
u
u
2
x
u
+n
3
3-5
2-4
x
x
x
x
u
6/10 + n
2
2
2
7/11
2 + n
6/10 + n
2 + n
n
x~
x
x
x
x
u
2-4
2+n
6/10 + n
x~
x
x
x
7/11
x
x
x
x
x
x
x
u
u
x
x
2
x
u
2-4
x
u
3
X
LI
= number of shifts
43
N'EC
"PD70136 (V33)
Instruction Set (cont)
Ope ode
Mnemonic
Operand
76 5 4
Flags
3
2
1
0
7
6
5
4
3
0
0
0
W
mod
0
1
1
mem
mod
1
1 0
mem
2
1
0
Clocks
Bytes AC
CY V
P
S Z
Shift/Rotste Instructions (cont)
RORC
mem,lmm8
1
1 0
0
6/10
+n
3-5
x
u
R
R R R R
(cont)
Stack Manlpulstlon Instructions
PUSH
mem16
1
reg16
0
sr
0
PSW
POP
PREPARE
R
0
Imm
0
mem16
1
1
0
0
0
0
0
0
0
reg
1
0
3/5
1
0
0
3/5
sr
1
0
0
0
0
3/5
0
0
0
20/36
0
S
0
3/5
2-3
5/9
2-4
mod
reg16
0
1 0
sr
0
0
0
PSW
1 0
0
1
1
R
0
1
0
0
0
0
0
0
Imm16,lmm8
2-4
5/9
0
0
0
0
mem
reg
5/7
1
5/7
1
0
5/7
0
0
22/38
sr
0
R
4
*
*imm8 = 0:15
imm8:=!: 1: 17 + 12 (imm8 - 1) odd, 15
DISPOSE
1 0
0
1
0
0
1
0
0
0
+ 8 (imm8-1)
6/10
1
7/9
3
Control Trsnsfer Instructions
CALL
near_proc
0
regptr16
memptr16
1
1
faLproc
0
0
0
0
0
reg
mod
0
0
mem
mod
0
0
memptr32
RET
pop_value
pop_value
BR
1
1
1
mem
11/15
9/13
5
15/23
2-4
0
0
0
1
10/12
0
0
0
0
0
10/12
0
0
0
1
12/16
1
0
0
0
1
0
12/16
3
0
0
0
shorLJabel
0
0
regptr16
1
1
0
0
reg
memptr16
mod
0
0
mem
1
mem
0
0
1
BV
shorLJabel
0
0
0
0
BNV
shorLJabel
0
0
0
0
BC,BL
shorLJabel
0
0
0
mod
0
0
1
0
3
7
3
7
·2
7
2
11/13
7
0
memptr32
2-4
5
13/17
2-4
3(6
2
3/6
2
3/6
n
44
2-4
0
near_label
faLlabel
2
7/9
2
= number of shifts
even
NEe
IIPD70136 (V33)
Instruction Set (cont)
Flags
Opcode
Mnemonic
Operand
7
6
5
4
3
2
0
0
1
0
7
6 5
4
3
2
1 0
Clocks
Bytes
AC
CYV
P
S Z
Control Transfer Instructions (cont)
1
1
BNC, BNl
shorUabel
0
BE,BZ
shorUabel
0
0
0
BNE, BNZ
shorUabel
0
0
1 0
BNH
shorUabel
0
0
BH
shorUabel
0
0
BN
shorUabel
0
BP
shorLlabel
BPE
shorLlabel
BPO
shOrLlabel
1
0
0
0
0
0
0
0
0
0
3/6
2
3/6
2
3/6
2
0
3/6
2
1
3/6
2
0
3/6
2
1
3/6
2
0
3/6
2
3/6
2
0
ED
Interrupt Instructions
BlT
shorLlabel
0
0
0
3/6
2
BGE
shOrLlabel
0
0
1
3/6
2
BlE
shorLlabel
0
3/6
2
BGT
shOrLlabel
0
3/6
2
OBNZNE
shorLlabel
0
0
0
0
OBNZE
shorLlabel
0
0
0
0
OBNZ
shorLlabel
0
0
0
BCWZ
shorLlabel
0
0
0
BRK
3
0
imm8
0
imm8
0
0
0
0
1
0
0
BRKV
RETI
CHKlNO
0
1
1
reg16, mem32
0
0
3/6
2
3/6
2
0
3/6
2
1
1
3/6
2
0
0
0
0
0
18/24
18/24
0
1
0
0
2
20/26
R
13/19
mod
reg
mem
24-26/
30-32
R
R R R R
2-4
CPU Control Instructions
HALT
FP01
FP02
0
1 0
0
0
0
0
0
0
X X
X
1
0
X X
X
mod
1
BUSLOCK
fp_op
2
2
1 Y Y Y Z
Z
Y Y Y
mem
fp_op, mem
1
fp_op
0
0
0
X
1
fp_op, mem
0
0
0
X
mod
POLL
0
0
1 Y Y Y Z
Z
Y Y Y
mem
Z
Z
*
*
*
*
2
0
2
2-4
2
2-4
+ 5n
n = number of times POLL pin is sampled.
NOP
0
0
0
01
0
0
EI
1
1
OSO:, OS1:, PS:, SS:
(segment override prefixes)
0
0
0
0
0
2
2
0
seg
3
0
2
45
NEe
IIPD70136 (V33)
Instruction Set (cont)
Opcode
Mnemonic
Operand
7
6
5
4
3
2
Flags
1
0
7
6 5
4
3
2
1 0
Clocks
1
1
1
1
1
1
Bytes
1
1 0
0
0
0 0
12
3
1
1
1 0
0
0 0
12
3
Address Expansion Contro/lnstructions
BRKXA
immS
0
0 0
0
1
immS
RETXA
immS
o
0
0
0
immS
46
1
1
AC
CV V
P S Z
NEe
NEG Electronics Inc.
Description
The V53™ is a high-speed, high-integration 16-bit
CMOS microprocessor with a CPU that is object and
source code compatible with the V2CJiJN3CJiJ. Integrated
on the same die is a 4-channel DMA controller, a UART,
three timer/counters, an interrupt controller, a refresh
controller, a clock generator, and a bus controller.
(1)
The DMA unit has four channels of highbandwidth DMA (up to 8M bytes/sec). It has two
sets of control registers, one compatible with the
JlPD71087/8237 and another with the JlPD71071.
(2)
The UART offers asynchronous serial I/O and is
functionally compatible with the JlPD71051 (8251).
(3)
The three 16-bit general-purpose timer/counters
are compatible with the JlPD71054 (8254).
(4)
The interrupt controller is identical to the
JlPD71059 (8259) and offers eight interrupt channels. External JlPD71059s may be cascaded.
(5)
The refresh controller generates a 16-bit refresh
cycle for use with dynamic or pseudostatic RAMs.
(6)
The clock generator uses a crystal at two times
the desired frequency to produce the internal
clock for the CPU and peripherals. A peripheral
clock is also output.
(7)
The bus controller generates JlPD71088-style control signals for easy interface to external devices.
The full V33 bus is also provided. Bus cycles are
nominally two clock cycles long and can be extended using the internal wait state generator.
Dynamic bus sizing can be used to set the datapath width for every bus cycle. Both 8- and 16-bit
cycles are supported, allowing the V53 to be used
on both 8- and 16-bit systems.
The V53 CPU is identical to the JlPD70136 (V33™).
Hardwired data-path control and a high-bandwidth bus
give a performance level four times that of the 10-MHz
V30. The 1M-byte addressing range of the V30 is
mapped into a 16M-byte LIM specification using onchip page registers.
pPD70236 (V53)
16-Bit Microprocessor:
High-Speed, High-Integration, CMOS
The V53 instruction set is upward compatible with the
native modes of the V20, V30, V40™, and V50™. It
includes bit processing, bit field insertion and extraction, and BCD string arithmetic. Using a modified
Booth's algorithm, the 16-MHz V53 executes 16-bit
multiplies in 750 ns. The CPU performance is the highest currently available in a high-integration microprocessor.
The V53 has an undefined instruction trap that allows
instructions not part of the V-series instruction set
(such as commands for proprietary MMUs) to be emulated. High-speed numerics support is provided by the
JlPD72291 CMOS floating-point unit (530K FLOPs at
16 MHz).
The V53's combination of high-speed CPU and DMA
makes it ideal for high-bandwidth data control applications such as disk or LAN controllers. The high integration and software compatibility of the CPU and peripherals with the V33 and V30 makes the V53 ideal for very
compact personal computer applications such as diskless work stations and lap top computers, or embedded MS-DOS® compatible PCs for POS terminals or
control applications.
Features
o High-speed, V30-compatible CPU
-125-ns minimum instruction execution time at
16MHz
-750-ns 16-bit multiply at 16 MHz
-1.19 Jls 16-bit divide (16 MHz)
- Fastest high-integration MPU available
o Dual bus architecture
o 8-byte instruction queue
o Expanded LIM 4.0-compatible 24-bit addressing
o Four DMA channels (to 8M bytes/sec)
o On-chip serial I/O controller
o Three JlPD71054-compatible 16-bit counter/timers
o Eight-channel JlPD71059-compatible interrupt
controller
o Refresh controller
V20 and V30 are registered trademarks of NEC Corporation.
V33, V40, V50, and V53 are trademarks of NEC Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
o Bus controller with wait-state generator
o Clock generator with STOP mode control for low
power
o 16-MHz (or 12.5-MHz) operation with 32-MHz (or
25-MHz) crystal
50159-1
ED
NEe
pPD70236 (V53).
Ordering Information
Clock (MHz)
Part Number
IlPD70236GD-10
10
GD-12
12
GD-16
16
R-10
10
R-12
12
R-16
16
Package
120-pin plastic QFP
132-pin ceramic PGA
Pin Configurations
120-Pin Plastic QFP
C')
C\I
~
0
00
NNNNCZ
en co 1'-.
<0 II)
...-...-..-..-..-
..,.
.....
0
C')
C\I
~
00
o..-..-..-..-z
0
0
(7)cor---COLnvCZ
('1')(\,1..-0
««>~«««>««~«««>~««
ENOITC
90
0 15
DMARQO
89
014
OMAAKO
88
013
DMARQ1
87
012
VOD
GNO
DMAAK1
DMARQ2
DMAAK2
°11
°10
OMARQ3
5MAAi<3
REFRQ
81
HLORQ
HLOAK
GNO
08
OO
INTPO
°5
°4
INTP1
INTP2
03
INTP3
02
GNO
voo
INTP4
INTP5
°9
°7
°6V
71
°1
00
INTP6
IC
INTP7
CPBUSY
INTAK
CPERR #
TCTLO
CPREQ#
TOUTO
TCTL1
VOO
GNO
TOUT 1
UBE
TCTL2
BUFEN
TOUT2
TCLK
OSTB
BCYST
# CPERR (error Indication) and CPREQ (data request)
are Inputs from a coprocessor.
83YL·6469B
2
NEe
IIPD70236 (V53)
132-Pin Ceramic PGA
Bottom View
Top View
00000000000000
00000000000000
00000000000000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
0000
00000000000000
00000000000000
00000000000000
P N M L
K
J
H G
FED C
14
13
12
11
10
9
S
7
S
S
4
Index mark
3
2
o
B A
/
ABC 0
E
F
G H
J
KL M N
III
P
Pin
Symbol
Pin
Symbol
Pin
Symbol
OMAROO
H1
INTP2
L13
GNO
N7
BUS LOCK
0 14
H2
INTP3
L14
CPERRII
NS
RESOUT
013
IC
H3
M1
TOUTO
N9
X2
014
H12
M2
TCTL2
N10
BUSSTO
E1
0 11
HLORO
VOO
GNO
H13
02
M3
TCLK
N11
RiW
E2
i5MAAK3
H14
M4
OTR
N12
lORD
E3
OMAR02
J1
03
INTP4
.MS
RxROY
N13
BCYST
OMAAKO
E12
INTPS
Me
AEX
N14
UBE
E13
VOO
0 10
J2
IC
J3
INTP7
M7
GNO
P1
OSR
E14
08
J12
IC
M8
VOO
P2
CTS
CS
A23
IC
F1
NC
J13
01
M9
BUSST1
P3
SINT
C6
A 18
F2
HLOAK
J14
NC
M10
IC
P4
TxO
A3
C7
REFRO
K1
INTPS
M11
MRO
PS
READY
C8
VOO
GNO
F3
Ao
F12
09
K2
INTAK
M12
IC
P6
BS8IBS1S
B1
OMAR01
C9
A7
F13
TCTL1
M13
BUFEN
P7
PCLKOUT
ENOITC
C10
VOO
F14
K12
CPREOII
PS
CLKOUT
A21
C11
A1
G1
VOO
CPBUSY
M14
B3
07
Os
INTP1
K3
B2
N1
TOUT 1
P9
X1
B4
VOO
C12
G2
INTPO
K14
IC
P10
RESET
A17
C13
G3
GNO
L1
DO
TCTLO
N2
BS
°1S
0 13
N3
RTS
P11
BUSST2
B6
A1S
C14
GNO
G12
VOO
l2
IC
N4
IC
P12
MliO
B7
A13
01
OMARQ3
G13
L3
TOUT2
NS
RxO
P13
IOWR
B8
A10
02
OMAAK1
G14
Os
04
L12
OSTB
NS
NMI
P14
MWR
Symbol
Pin
Symbol
B9
A9
03
B10
AS
012
B11
GNO
A 19
B12
A1S
B13
A2
IC
Pin
Symbol
Pin
A1
A22
A2
A20
GNO
A4
AS
AS
A14
B14
A7
A12
C1
AS
A11
C2
A9
NC
C3
A10
AS
C4
A11
AS
A12
A4
A13
A14
A3
0 12
OMAAK2
K13
# CPERR (error indication) and CPREO (data request)
are inputs from a coprocessor.
83YL-6470B
3
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,.,PD70236· (V53)
Pin Identification
Symbol
AEX
I/O
Function
Symbol
I/O
Function
Out
Address bus
TxD
Out
Serial transmit data
Out
Address expansion mode flag
UBE
Out
Data bus higher byte enable
Out
Bus cycle start
X1,X2
In
Crystal/external clock
In
In
Data bus width specification
Voo
Out
Buffer enable
GND
Ground
BUSLOCK
Out
Bus lock flag
IC
Internal connection
B USSTO-B USST2
Out
Bus status
NC
No connection
CLKOUT
Out
System clock
In
Coprocessor busy
Out
Clear to send
BS8/BS16
DMARQO-DMARQ3
I/O
Data bus
Out
DMA acknowledge
In
DMA request
In
Data set ready
Out
Data strobe
Out
Data terminal ready
I/O
DMA service forced-end input;
DMA service complete output
HLDAK
Out
Bus hold acknowledge
HLDRQ
In
Bus hold request
INTAK
Out
Interrupt acknowledge
INTPO-INTP7
In
Maskable interrupt request
lORD
Out
I/O read
10WR
Out
I/O write
M/IO
Out
Memory I/O select
MRD
Out
Memory read
MWR
NMI
Out
In
PCLKOUT
Out
External I/O clock
READY
In
Bus cycle end
REFRQ
RESET
Out
In
Refresh request
Reset.
RESOUT
Out
System reset
RTS
Out
Request to send
R/W
Out
Read/write
RxD
In
Serial receive data
RxRDY
Out
Serial receive ready
SINT
Out
Serial interrupt request
TCLK
In
Timer clock
TCTLO-TCTL2
In
Timer control
TOUTO-TOUT2
Out
Timer output
4
Table 1. Output Pin States
DMA
Symbol
Hold
Halt
Reset
Cascade
Hi-Z
L
Hi-Z
Hi-Z
Note 6
Note 6
H/L
Note 6
BCYST
Hi-Z
Note 4
Hi-Z
Hi-Z
BUFEN
Hi-Z
H
Hi-Z
Hi-Z
Note 5
Note 5
H
H
Hi-Z
H
Hi-Z
H
AEX
BUSLOCK
BUSSTO-BUSST2
CLKOUT
o
o
o
O'
Hi-Z
Note 3
Hi-Z
Hi-Z
H
o
H
o
Hi-Z
H
Hi-Z
Hi-Z
o
o
o
H
Hi-Z
Hi-Z
o
o
H
H/L
L
L
H
H
H
H
Hi-Z
H
Hi-Z
Hi-Z
Hi-Z
H
Hi-Z
Hi-Z
MiiO
Hi-Z
L
Hi-Z
H
MRD
Hi-Z
H
Hi-Z
Hi-Z
DMAAKO-DMAAK3
HLDAK
Memory write
Nonmaskable interrupt request
+ 5-volt power source
Hi-Z
H
Hi-Z
Hi-Z
PCLKOUT
o
o
o
REFRQ
H
o
o
H
H
RESOUT
L
L
H
L
RTS
o
o
H
o
L
Hi-Z
H
o
o
o
H
o
L
o
o
R/W
RxRDY
SINT
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pPD70236 (V53)
Table 1. Output Pin States (conI)
BCYST (Bus Cycle Start Strobe)
DMA
Symbol
Cascade
Hold
Halt
Reset
TOUTO-TOUT2
0
0
0
0
TxD
0
0
H
0
iJBi:
HI-Z
H
HI-Z
HI-Z
Notes:
(1). The pin states are Interpreted as follows: H Is high level; L Is low
level; H/L Is high or low level; Hi-Z is high impedance; 0 is
indeterminate.
(2) Halt includes both the HALT and STOP modes.
(3) Undefined for the first two clocks of the halt acknowledge cycle
and the Hi-Z.
(4) L for the first clock of the halt acknowledge cycle and then H.
(5) L under either of the following conditions: an instruction is
executed during hold with a BUSLOCK prefix, or the HALT
instruction is executed with a BUSLOCK prefix. Otherwise, the
value is H.
This signal indicates the start of a bus cycle by going low
for one clock immediately after the bus cycle is started.
When the bus is placed in the hold state, the BeYST pin
enters the high-impedance state.
BS8/BS16 (8-Blt Bus Slze/16-Blt Bus Size)
BS8/B516 is driven low by external logic when the
p.PD70236 addresses a device with an 8-bit data path. If
the p.PD70236 operand is 16 bits wide and B58/BS16 is
low, then the p.PD70236 will perform two 8-bit bus
cycles. The current bus cycle will handle the low byte on
Do-D7, and the next bus cycle will handle the upper byte
als6 on Do-D7' This input is ignored during HLDAK,
interrupt acknowledge, and coprocessor cycles.
(6) H in address expansion mode; L in nonexpansion mode.
BS8/B516. is samP.led on the rising (middle) edge of T2 or
the last TW state~ coincident with READY. This input is
not internally. synchronized. To ensure proper device
operation, minimum setup and hold times must be met.
PIN FUNCTIONS
BUFEN (Buffer Enable)
Ao-A,,3 (Address Bus)
This signal is output to enable an external buffer, and
becomes active during the read cycle, interrupt acknowledge cycle, and write cycle. It does not become active
while the internal I/O is being accessed.
These pins constitute an address bus that outputs real
addresses when memory or an I/O device is accessed.
Up to 64K bytes of I/O space and up to 16M bytes of
memory space (including reserved areas) 'can be accessedthrough the address bus.
The address bus enters the high-impedance state if one
of the following occurs.
• RESET signal is applied
• Microprocessor is in HOLD mode
• DMA requests are cascade connected
The status of the address bus is undefined during an
interrupt acknowledge cycle. When interrupt requests
are cascade connected, the slavelCU address is output
on pins Ao-A2'
When I/O is accessed, pins A16-A23 go low. The address
can be expanded even when the interrupt vector table is
accessed.
AEX (Address Extension)
AEX is asserted when the expanded addressing mode is
enabled. When AEX is high, the memory address space
is 16M bytes (24-bit address), and when [ow, 1M byte
(20-bit address).
BUSLOCK (Bus Lock)
BU5LOCK should be used by external logic to exclude
any other bus master (e.g., a DMA controller) from using
a shared resource.that the p.PD70236 currently is using.
When BU5LOCK is asserted high, HLDRQ will be ignored.
BU5LOCK is asserted when the BU5LOCK prefix is
executed or when the p.PD70236is performing· a bus
operation that must not be interfered with, such as an
interrupt acknowledge cycle. BUS LOCK has the same
timing as the address bus Ao-A23 and is driven high
during HLDAK and RESET.
BUSSTO-BUSST2 (Bus Status)
These three pins encode and output information identifying the type of bus cycle currently being executed.
They enter the high-impedance state in the bus hold
mode. These pins are used with the M/IO and R/W
signals, as shown in table 2.
5
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"PD70236 (V53)
Tsble2. BusCycle8
~ R~ BUSST2 BUSST1 BUSSTO
0
0
0
0
0
0
0
BUI
Cycle
0
0
Interrupt acknowledge
cycle (from SLAVE)
0
0
Interrupt acknowledge
cycle (from ICU)
0
External I/O read cycle
0
Internal I/O read cycle
0
External I/O write cycle
0
Internal I/O write cycle
0
0
0
0
0
1
0
o .
Coprocessor read cycle
0
0
0
0
Coprocessor write cycle
0
0
0
0
0
InstruCtion fetch Cycle
1
0
0
Refresh cycle
0
0
CPU memory read
0
DMA read transfer cycle
0
1
<,
Halt acknowledge cycle
~cle
0
0
0
CPU memory write cycle
0
1
0
DMA write transfer cycle
0
0
0
Coprocessor memory
read cycle
0
0
Coprocessor memory
write cycle
DMAcascade
Interrupt, Acknowledg. Cycle (from SLAVE). This cycle is the second interrupt acknowledge cycle during
which an interrupt request from a slave interrupt control
unit '(ICU) is acknowledged. During this cycle, the data
output by an external interrupt controller is processed
as a vector. The bus sizing function cannot be effected in
this cycle. The programmable wait function and READY
signals are both valid,' however.
Interrupt Acknowledge Cycle (f~om ICU). This cycle is
output during the first interrupt acknowledge cycle, during which an interrupt request for a non-slave ICU is
acknowledged. During this acknowledge cycle, the data
output by the internallCU is processed as a vector, and
the bus sizing function cannot be effected. The programmable wait function and READY signal are both valid,
however.
External 1/0 Read Cycle. This cycle is output when an
external 1/0 area is read by executing the IN instruction.
During this cycle, the bus sizing function can be effected. Also, the programmable wait function and
READY signal are both valid.
Internal 1/0 Read Cycle. This cycle is output when the
internal 1/0 area is read by executing the IN instruction.
6
The bus sizing function cannot be effected. Both the
programmable wait function and READY signal are invalid. However, two wait state clocks are automatically
inserted into all internal 1/0 area cycles except those for
the address expansion table and address expansion flag.
External 1/0 Write Cycle. This cycle is output when an
external 1/0 area, is written by executing the OUT instruction. The bus sizing function can be effected. Also,
the programmable wait function and READY signal are
both valid.
Internal 1/0 Write Cycle. This is output when the internalllO area is. written by executing the OUT instruction.
The bus sizing function cannot be effected. Both the
programmable wait function and READY signal are invalid. However, two wait state clocks are automatically
inserted into all internal ,I/O area cycles except those for
the address expansion table and address expansion flag.
Coprocessor Read Cycle. This cycle indicates that an
external coprocessor Is accessed for data read when a
coprocessor instruction is executed. The bus timing and
ac characteristics of this cycle are the same as those of
the ordinary I/O read cycle.
Although the bus sizing function cannot be effected,
coprocessor operations are not guaranteed if the bus
sizing function is used. The programmable wait function
is invalid, but the READY Signal is valid.
Coprocessor Write Cycle. This cycle indicates that an
external coprocessor instruction is executed. The bus
timing and ac characteristics of this cycle are the same
as those of the ordinary 1/0 write cycle.
Although the bus sizing function can be effected; coprocessor operations are not guaranteed if the bus sizing
function is used. The programmable wait function is
invalid, but the READY signal is valid.
flalt Acknowledge Cycle. This cycle is output when the
HALT instruction is executed. During this bus cycle, the
OSTB pin does not output a low level. The bus sizing
function cannot be effected. Both the programmable
wait function and READY signal are invalid.
Instruction Fetch Cycle. This cycle indicates that an
instruction is being fetched. The bus sizing function can
be effected. Also, the programmable wait function and
READY signal are both valid ..
Refresh Cycle. This cycle indicates that DRAM refreshingis in progress. The bus sizing function cannot be
effected. (Note that BS8/BSt6must be 16 bits.) The
programmable wait function and READY signal are both
valid.
CPU Memory Read Cycle. This cycle is output when the
CPU reads data from memory. The bus sizing function
NEe
can be effected. Also, the programmable wait function
and READY signal are both valid.
DMA Read Transfer Cycle. This cycle is output when
DMA transfer (that is, data transfer from memory to 1/0)
takes place. The bus sizing function cannot be effected~
The programmable wait function and READY signal are
both valid.
CPU Memory Write Cycle. This cycle is output when the
CPU writes data to memory. The bus sizing function .can
be effected. Also, the programmable wait function and
READY signal are both valid.
DMA Write Transfer Cycle. This cycle is output when
write DMA transfer (that is, data transfer from 110 to
memory) takes place. The bus sizing function cannot be
effected. The programmable wait function and READY
signal are both valid.
Coprocessor Memory Read Cycle. This cycle is output
when data read from memory is sent to the coprocessor.
Although the bus sizing function cannot be effected,
coprocessor operations are not guaranteed if bus sizing
is used. The programmable wait function and READY
signal are both valid.
Coprocessor Memory Write Cycle. This cycle is output
when data for a coprocessor is written to memory. The
CPU does not drive the data bus. Instead, the cop'rocessor drives the data bus to write data to memory.
Although the bus sizing function cannot be effected,
coprocessor operations are not guaranteed if the bus
sizing function is used. The programmable wait function
and READY signal are both yalid.
DMA Cascade. This cycle indicates that the DMA is
cascade connected to an external slave DMA controller.
During this cycle, the buses are relinquished.
CLKOUT (Clock Output)
This pin outputs a square-wave clock pulse. The frequencyof the output clock pulse is obtained by dividing
the frequency of the 'clock signal input to the X1 and X2
pins by a specific value. The duty factor of the output
clock pulse is 50%. The outputfrequency is the same':as
the operating frequency of the CPU (programmable to
one-half, one-fourth, one-eighth, or one-sixteenth of the
oscillation frequency).
CPBUSY (Coprocessor Busy)
CPBUSY is asserted low by a coprocessor (such as
p.PD72291) when it is busy with an internal operation;
The p.PD70236 uses this pin to check the. ~tatus of the
coprocessor.
pPD70236 (V53)
CPBUSY is sampled on the falling edge of each clock.
This input is not internally synchronized. To ensure
proper device operation, minimum setup and hold times
must be met.
If a 'coprocessor is not connected to the p.PD70236,
CPBUSY should be grounded.
CTS (Clear to Send)
This is a serial transmission control input pin. T~e SCU is
ready for data transmission when bit 0 of the SCM
register is set to 1 and this pin is at low level. When this
pin is made high while data transmission is in progress,
transmission is stopped atter the current data has been
completely transmitted, and 'the TxD pin goes high.
00-0 15 (Data Bus)
These pins constitute a data b~s that inputs or outputs
write data and read data when the external main memory or 1/0 device is accessed. The data bus is in the input
mode during any bus cycle ,other than a write cycle.
During the write bus cycle, the bus outputs data starting
from the rising edge of the T1 clock until the cycle
following the write bus end cycle.
OMAAKO -OMAAK3 (OMA Acknowledge)
These pins output active-low DMA acknowledge signals
fr'Om channels 0 to 3 of the internal DMAU.
OMARQO ..OMARQ3 (OMA Request)
These pins input active-high DMA request signals from
channels 0 to 3 of the internal DMA control unit (DMAU).
OSR (Oata Set Ready)
This is a general-purpose input pin. The status of this pin
can be determined by reading bit 7 of the serial status
(SSn register.
OSTB (Oata Strobe)
This is a strobe signal for read and write operations. The
signal does not go low during the halt acknowledge cycle
that indicates that the' HALT instruction has been executed. When the buses are placed in the hold state, the
DSTB pin enters the high-impedance state. The signal
output timing of this pin differs depending on whether a
read or write operation is performed. The DSTB signal
does not go low when the internal 1/0 area is accessed.
OTR (Oata Terminal Ready)
This is a general-purpose output pin. The status of this
pin can be set by bit 1 olthe SCM register.
7
III
NEe
pPD70236 (V53)
END/TC (End/Terminal Count)
This pin inputs the END signal to or outputs the TC
signal from the internal DMAU.
is not internally synchronized. To ensure proper device
operation, minimum setup and hold times must be met.
INTAK (Interrupt Acknowledge)
END Input. When a low-level pulse is input to this pin
during DMA transfer, the DMA .service under execution
is terminated after the current bus cycle is over.
This is an active-low acknowledge signal for a maskable
interrupt.
TC Output. When the count register of the DMAU
channel currently performing DMA transfer becomes
0, and when the DMA transfer has been performed the
specified number of times, the TC pin outputs a lowlevel pulse.
INTPO-INTP7 (Interrupt from Peripherals)
H LOAK (Hold Acknowledge)
This is an acknowledge signal that indicates that the
V53 has accepted the HLDRQ signal, placed the address, data, and control buses in the high-impedance
state, and relinquished the buses to an external device.
The external devices that can acquire the buses are
assigned the following priority.
REFU (highest priority)
DMAU
HLDRQ
CPU
REFU
If a bus hold request takes place while the buses are idle
(TI state), during the CPU bus cycle, or during lowestpriority refresh cycle, the HLDRQ signal is accepted
immediately after the bus cycle is over and the buses
are relinquished .. '
If a DMA request or top-priority refresh request is
generated while the buses are in the hold state, the
HLDAK signal is forcibly made inactive. In this case, the
external device must return control of the bus to the
V53 (making the HLDRQ signal inactive). Therefore, the
high-level width of the HLDAK signal when it is made
inactive forcibly is 1 clock minimum.
H LDRQ (Hold Request)
HLDRQ is asserted. high by external logic when an
external bus master (e.g., a DMA controller) wants to
take over the pPD70236 bus. When HLDRQ is detected
high, the pPD70236 wi II release the bus after the current
bus operation is completed. Note that this is. not
necessarily the. current bus cycle. The pPD70236 re~
leases its bus by floating the address, data, and control
buses.
HLDRQ is sampled on the rising edge of each clock. It
will be ignored while BUSLOCK is asserted. This input
8
These are asynchronous interrupt request input pins
for the internal interrupt control unit (lCU). The input
signals can be triggered either at the rising edge or at
high level. The priority of these signals can be fixed or
rotated. These interrupt request inputs are also used to
release the HALT and STOP modes.
lORD (I/O Read)
This active-low read signal goes low during the I/O read
cycle. This signal is also output when write DMA transfer is performed. However, it is not output during the
CPU's internal I/O read cycle.
10WR (I/O Write)
This is an active-low write signal that goes low during
the I/O write cycle. This signal is also output when read
DMA transfer is performed in two output timing modes:
the expansion write mode and the ordinary write mode.
It is not output during the CPU's internal I/O write cycle.
M/IO (Memory I/O)
This pin indicates whether a memory or other device
(such as an I/O device or' coprocessor) is currently
accessed. The device to be accessed is determined ~
this pin and the BUSSTO and BU.sST1 signals. The M/IO
pin enters the high-impedance state in the bus hold
mode. Its status changes at the falling edge of the T1
clock.
MRD (Memory Read)
This is an active-low read signal that goes low during a
read cycle in which data is read from memory. This
signal is output not only during the CPU's memory
read, but alsoquring the refresh cycle and when read
DMAtransfer is 'performed.
MWR (Memory Write)
This active-low write signal goes low when the memory
write cycle is in progress. This signal is output not only
during the CPU's memory write cycle, but also during
the write DMA transfer and when write DMA transfer is
performed in two output timing modes: the expansion
write mode and the ordinary write mode.
NEe
pPD70236 (V53)
NMI (Nonmaskable Interrupt Request)
RESOUT (Reset Output)
NMI is asserted by external logic to notify the CPU that
an external event requires the CPU's immediate attention. When NMI is sampled low, interrupt processing
will begin immediately after the current instruction is
completed. A trap will be taken through vector 2. The
state of the IE bit in the PSW has no effect on NMI
acceptance.
This pin outputs an active-high signal which is an
asynchronous RESET signal synchronized with the
internal clock. This signal can be used to reset the
system.
NMI is sampled on the falling edge of each CPU clock.
This input is not internally synchronized. To ensure
proper device operation, minimum setup and hold
times must be met.
Interrupt processing begins immediately after the end
of the current instruction. Once NMI processing commences, no further NMI requests will be accepted until
termination of the current NMI routine, which is indicated by the RETI instruction.
PClKOUT (Peripheral Clock Output)
This pi n outputs a square-wave clock pulse with a
frequency one-fourth the frequency of the clock signal
input to the X1 and X2 pins. The duty factor of the
output clock pulse is 50%.
READY (System Ready)
The READY signal is asserted low when the external
system is ready for the current bus cycle to terminate.
While READY is not asserted, the Jl PD 70236 wi II add TW
(wait) states to the current bus cycle. The bus state in
which READY is sampled low will be the last state of the
cycle.
During CPU read cycles, READY gives slow devices
time to drive the Do-D7 inputs, and during write cycles
gives slow devices enough time to finish the write
operation.
The READY input is sampled on the rising (middle)
edge of T2 and all TW states. It is ignored during the
HLDAK state. This input is not internally synchronized.
To ensure proper device operation, minimum setup and
hold times must be met.
RE F RQ (Refresh Request)
This signal is asserted during refresh cycles.
RESET (Reset)
This signal initializes the processor. The processor is
reset when this signal is held low for six clocks or longer
and then returned to the high level.
RTS (Request to Send)
This is a general-purpose output pin. The status of this
pin can be set by bit 5 of the serial command (SCM)
register.
R/W (Read/Write)
This pi n indicates whether the current bus cycle is a
read cycle or a write cycle. This pin is valid only while a
bus cycle is being executed, and goes high if the
current bus cycle is a read cycle or during an interrupt
acknowledge cycle; it J!oes low if the current bus cycle
is a write cycle. The RIW pin enters the high-impedance
state in the bus hold mode. The level of this pin
changes at the falling edge of the T1 clock.
RxD (Receive Data)
When the serial control unit does not receive data, this
pin is at high level (mark state). When the pin detects a
start bit, the SCU starts receiving serial data from an
external device.
RxRDY (Receive Ready)
When the serial control unit has received one character
of data, and when that data is transferred to the receive
data buffer (that is, when the receive data is ready to be
read), this pin goes high.
SINT (Serial Interrupt)
This signal becomes active to output an interrupt
request signal from the SCU when the transmit data
buffer of the SCU is empty and when the interrupt of, the
transmitting side is not masked, or when it contains the
SCU's receive buffer data to be read and the receive
interrupt is not masked.
TClK (Timer Clock)
This pi n inputs a clock pulse from an external source to
the internal timer/counter unit (TCU). When the system
is initialized, either the external clock or the internal
clock is selected to be supplied to the TCU.
TCTlO -TCTl2 (Timer Control)
These pins input control signals to the three TCU
counters. The functions of the control signals input
9
III
NEe
IIPD70236 (V53)
through these pins differ depending on the mode· (six
modes are available) set by the TCU.
TOUTO·TOUT2 (TImer Output)
These are output pins for the internal timer/counter unit.
The TCU outputs signals through these pins in six
different modes.
TxD (Transmit Data)
When the serial control unit (SCU) has no data to be
transmitted to an external device, this pin is at high level
(mark state). When transmit data is set in theSCU, the
TxD pin automatically outputs a start bit, serial data that
has been set in the SCU, a parity bit, and 1 or 2 stop bits.
UBE (Upper Byte Enable)
When the microprocessor accesses external main memory or an I/O device that requires the upper 8 bits
(08-D15) of the data bus, this pin goes low at the falling
edge ofthe T1 clock, enabling the upper byte on the bus.
The lower 8 bits (Do-D7) of the data bus are controlled by
the Ao pin as shown in the following table.
UBE
0-
o
1
1
&
0
1
0
1
Operation
16 bits accessed
Upper 8 bits accessed
Lower 8 bits accessed
Second cycle (for use with bus sizing
function)
When dynamic bus sizing is used to make a 16-bit
access into an a-bit, Ao must be used as an address bit;
UBE can be ignored.
X1, X2 (Crystal)
To use the internal clock generator, connect a crystal
with a frequency twice the operating frequency across
these pins. When using an external clock generator,
input square waves with a frequency twice the operating
frequency to the X1 pin. To the X2 pin, make the input
signal 180° out of phase (an Inverter output) with the
signal input to the X1 pin.
UNIT OPERATION
Central Processing Unit (CPU)
The ILPD70236 CPU is a high-performance engine whose
performance surpasses most other 16-bit CPUs. To
achieve this performance level, hardwired data path
control was used (no microcode) so that instruction
execution times are greatly reduced.
10
The #,PD70236 CPU has functions equivalent to those of
the ILPD70136 (V33) and is therefore completely software
compatible with the V33. The ",PD70236 instruction set
is upward compatible with the native modes of the V20,
V30, V40, and V50.
Clock Generator (CG)
The clock generator divides the oscillation frequency of
the crystal or external oscillator connected across pins
X1 and X2 by 2, 4, 8, or 16 to generate a clock that is
supplied' to the CPU as an operation clock and to an
external device through the CLKOUT pin. A clock having
a frequency one-fourth the oscillation frequency is also
output to the PCLKOUT pin.
Bus Interface Unit (BIU)
The bus interface unit controls the pins of the address
bus, data bus, and control bus, which are used by the
CPU, DMA unit (DMAU), and refresh control unit (RE FU).
Bus Arbitration Unit (BAU)
The bus arbitration unit arbitrates the internal bus mastership. The priority of the bus mastership is:
CPU with BUSLOCK (highest priority)
RE FU of top priority
DMAU
HLDRQ
Ordinary CPU
RE FU of lowest priority
Walt Control Unit (WCU)
The function of the wait control unit is to insert wait
states equivalenrtoO to 7 clocks automatically into the
memory, I/O, DMA, and refresh cycles. The 16M-byte
memory space can be divided into three blocks. In
addition, any 1M-byte memory space can also be divided
into three blocks.
Refresh Control Unit (REFU)
The RE FU supports the DRAM refresh operation by
generating 16-bit refresh addresses and a refresh signal
(REFRQ) indicating that the refresh cycle is currently
taking place.
Timer/Counter Unit (TCU)
The timer/counter unit of the #,PD70236 performs the
same. functions as the #,PD71054. It provides a set of
three independent 16-bit timer/counters.
NEe
Serial Control Unit (SCU)
The p.PD70236 SCU has the same functions as the
p.PD71051 except the synchronous mode for supporting
RS-232C protocol. This SCU is equipped with a dedicated baud rate generator.
The SCU provides serial communications functions· of
the start-stop synchronization type. Commands for the
SCU in the V53 are similar to those of the p.PD71051
except that the V53 uses two registers-SCM (serial
command) register and SMD (serial mode) register-to
implement the functions of the control word register of
the p.PD71051.
Interrupt Control Unit (ICU)
The ICU in the V53 has the same functions as those on
the p.PD71059 except the V53 does not have the CALL
mode (8085 mode) or the slave mode of cascade connection. The p.PD70236 ICU has eight external interrupt
input pins and can arbitrate up to eight interrupt requests. The number of external interrupt inputs can be
increased by cascade connecting the ICU to an external
interrupt controller.
IIPD70236 (V53)
Unlike the p.PD71059, p.PD70208, and p.PD70216, the
INTPO to INTP7 pins in the V53 do not have internal
pullup resistors to reduce current dissipation.
DMA Control Unit (DMAU)
The DMAU on the p.PD70236 functions the same as the
DMAUs on the p.PD71071 and p.PD71037 and, therefore, it
can operate in two modes (p.PD71071 mode and
p.PD71037 mode). You can set the operation modes using
a register in the system 1/0 area.
In p.PD71071 mode, source and destination addresses
are 24 bits. In p.PD71037 mode, source and destination
addresses are 16 bits. To extend these addresses to 20 or
24 bits, four 8-bit bank registers are provided. These
registers supply the upper address bits.
The DMA unit provides. four channels of p.PD71071compatible or p.PD71037-compatible DMA. External
hardware requests DMA cycles via the DMA request
inputs. DMA is always between an I/O device and memory (fly-by style DMA). External DMA controllers may be
cascaded using the V53 DMAU.
11
.:91
.:II
NEe
pPD70236 (V53)
"PD70236 Block Diagram
~I~I~I
ClKO~ ~
PCLKOUT~
TCLK
DMAROO
TxO
DMAAKO
RxO
DMAR01
RxROY
CPU
DMAAK1
SINT
DMAU
DMAR02
SCU
DMAAK2
CTS
DMARQ3
RTS
DMAAK3
OTR
ENDfTC
OSR
REFRO
-1
WCU
REFU
BAU
»
m
x
~I~ ~1~'~I~I~I~I~I~I~I~lil~li'
A
BAU
Bus Arbitration Unit
ICU
BIU
Bus Interface Unit
REFU
Refresh Control Unit
CG
Clock Generator
SCU
Serial Control Unit
CPU
Central Processing Unit
TCU
Timer/Counter Unit
DMAU
DMA Control Unit
WCU
Wait Control Unit
a>
Interrupt Control Unit
83YL-5728B
12
NEe
pPD70236 (V53)
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
TA = +25°C
Power supply voltage, Voo
-0.5 to + 7.0 V
Input voltage, VI
-0.5 to Voo + 0.3 V
Clock input voltage, VK
-0.5 to Voo + 1.0 V
Output voltage, Vo
-0.5 to Voo + 0.3 V
Output short circuit current, 10
50 mA
t Operating temperature, TOPT
-65 to + 150°C
Storage temperature, TSTG
t Devices with a rating of -40 to + 85°C are available. Contact NEC
for dc and ac characteristics.
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage.
III
DC Characteristics
TA = -10 to + 70°C; Voo = +5 V ±10%
Parameter
Symbol
Min
Input voltage, high
VIH
2.2
Max
Unit
VOO + 0.3
V
V
RESET
Input voltage, low
Vil
-0.5
0.8
V
Except RESET
0.2 Voo
V
RESET
Clock input voltage, high
VKH
0.8 Voo
VOO + 0.5
V
Clock input voltage, low
VKl
-0.5
0.6
V
Output voltage,high
VOH
0.7 Voo
Output voltage, low
VOL
0.8 VOO
0.45
Conditions
Except RESET
= -400 pA
V
10H
V
10l = 2.5 mA
Input leakage current, high
ILiH
10
Input leakage current, low
ILil
-10
pA
VI = 0 V
Output leakage current, high
ILOH
10
pA
Vo = VOO
Output leakage current, low
IlOl
-10
pA
Vo = 0 V
Supply current
100
13 f + 40
mA
Operating; f
40
mA
HALT mode
TBD
pA
STOP mode
= 2 to 16 MHz
Voltage Thresholds for Timing Measurements
AC (except ClK)
Signal Inputs 2.4 V = X 2 . 2 V
2
. 2V;C
(except ClK) 0.4 V
..;;0,;.;;.8...,;v_ _ _ _.....,;0;.;,;.8;,..v;;...
AC test input measuring point
ClK Input
---Y·2.2V
2.2VV--
~..;;0.;.;;.8...;V~_ _ _.....,;0~.8~V;;.."_____
83VL·6484A
13
NEe
JlPD70236(V~53)
AC Characteristics
TA = -10 to + 70°C; VOO = 5 V ±10%; CL of output terminals =
100 pF max
Parameter
Symbol
Min
Max
Unit
Param'
'I
Clocks (figure 1)
CLKOUT period
tCYK
CLKOUT high-level
width
t",(H
62.5
CLKOUT rise time
CLKOUTfall time
X1 input perio'
Unit
"
50
ns
40
ns
0.5 tr
X1 input high-level
width
X1 input low-level
width
X1 input rise time
Max
50 r
P070236 t\lS3)
dUm"
to
the
~
, d \n thiS
d bV Adden
\S \nc\Ude
Supersede
addendum
Sheet. "the . section 7.
oata
\( 10\\0'11\09
data bOO
CLKOUT low-level
width
Min
... KOUTto MWR
delay
t)
5
ns
X1 input fall time
tXKF
5
ns
X1 to CLKOUT delay
tOXK
20
ns
PCLKOUT period
tCYPK
1000
ns
PCLKOUT high-level
width
tpKH
PCLKOUT low-level
width
tpKL
PCLKOUT rise time
tpKR
7
ns
PCLKOUT fall time
tpKF
7
125
ns
40
ns
0
40
ns
'OKMR
0
40
ns
tOKMW
0
40
ns
40
tOKOSH
5
tOAOSL
tKKL + tKR - 15
ns
Address/status hold
time from DSTB t
tHOSHA
tKKL + tKR - 15
ns
Data output delay
from DSTB t
tooSHO
tKKL + tKR - 15
ns
Data output delay
from address/status
output
tOAD
tKKL + tKR - 15
ns
ns
Data output delay
from CLKOUT t
tOKo
5
ns
4 tCYK-7
t
ns
')
Address/status output
delay to DSTB ~
ns
4 tCYK-7
CLKOUT t to DSTB
10
Reset (figure 2)
40
ns
ns
RESET setup time vs
CLKOUT ~
tSRSTK
30
ns
Data setup time to
CLKOUT ~
tSOK
7
ns
RESET hold time vs
CLKOUT ~
tHKRST
15
ns
Data hold time from
CLKOUT ~
tHKO
10
ns
RESET low-level width
twRSTL
6
tcyC
Data hold time from
DSTB t
tHOSO
0
ns
RESOUT delay from
CLKOUT ~
tOKRO
0
Data hold time from
change point of
address or status
tHASO
0
ns
' tHRWO
0
ns
40
ns
Write, Read (figures 3-12, 16-19, 23-24, 28, 31) Note 2
BCYST delay from
CLKOUT ~
tOKBC
BCYST low-level width
tBCBCL
tBCBCH
BCYST high-level
width
Address delay from
CLKOUT ~
ns
Dat hold time from
R/W t
tCYK-10
ns
7
ns
ns
READY setup time to
CLKOUT t
tSRYK
tCYK (n+ 1) - 10
READY hold time from
CLKOUT t
tHKRY
15
ns
5
40
toKA
5
40
ns
Control 2 delay from
CLKOUT
to KCT2
0
40
ns
(1) tCYC = CPU clock period
n = number of wait states
Status delay from
CLKOUT ~
toKST
5
40
ns
(2) The clock-to-signal delays in the -10 (10 MHz) and -12 (12.5 MHz)
parts are 45 ns compared to 40,ns in the -16 (16 MHz) part. For
full electrical characteristics of the -10 and -12 parts, contact
NEC.
14
Notes:
1ttIEC
pPD70236 (V53)
AC Characteristics (cont)
Parameter
Min
Symbol
Max
Unit
Bus Sizing (figures 13, 14)
888/8816 setup time
to CLKOUT f
tSBSK
888/8816 hold time
from CLKOUT f
tWVD"
Bus Hold (figure
HLDRQ setup tilT'
CLKOUT t
HLDRQ hold til).
form CLKOUT t
NMI, INTPO-INTP7,
CP8U8Y hold time
from CLKOUT ~
CLI\~_
.,.
tOFh •.
ns
."
tSIK
10
ns
tHKT
10
ns
.)
IORD~, IOWR ~ delay
from DMMKODMAAK3 ~
DMMKO-DMMK3
delay from lORD t
t
ns
50
TCTLO-TCTL2 hold
time from CLKOUT ~
tHKG
100
tGGL
50
ns
tGGH
50
ns
TOUTO-TOUT2 output
delay from CLKOUT ~
tOKTO
TCLK period
tCYTK
100
100
TCLK rise time
trKR
15
TCLK fall time
tTKF
15
TCLK low-level width
trKTKL
45
500
ns
v
40
ns
0
40
ns
tOKHOA
0
40
ns
tOOARW
tKKH - 30
ns
tORHOAH
tKKH -30
ns
~)
ns
0
40
tOWHRH
5
40
TC output delay from
CLKOUT t
·tOKTCL
0
40
ns
TC off output delay
from CLKOUT t
tOKTCF
0
40
ns
TC pullup delay from
CLKOUT t
tOKTCH
0
40
ns
lORD
tsGK
ns
tOKCT1
t delay to
IOWR
t
TCTLO-TCTL2 setup
time to CLKOUT ~
TCTLO-TCTL2 highlevel width
Unit
DMMKO-uMMK3
delay
CLKOUT to control 1
delay
Timer/Counter Unit TCU (figures 20-21)
TCTLO-TCTL2 low-level
width
Max
70236 {\}53)
'\ to the ~p~ \0 thiS
~ddeodum .s \Oc\ude
ded bV
odUm \
SUperse \ 1he add~ ct\OO 7.
oa\a She~ 10\\0'1l\Og e
data bOo
Input Setup and Hold (figure 15,
NMI,INTPO-INTP7,
CP8U8Y setup time
to CLKOUT ~
Min
ns
CLKOUT t to H LDA~
delay
.Output floating to
HLDAK delay
~" ... I-
Parameter
-.C::P.,.;-'
TC low-level width
trCTCL
tCYC -15
ns
ns
END setup time to
CLKOUT t
tSEOK
35
ns
ns
END low-level width
tEOEOL
100
ns
ns
lORD, MRD low-level
width
tRR
2tCYC - 40
IOWR, MWR low-level
width (Expanded
write)
tWWI
2tCYC - 40
ns
ns
TCLK high-level width
trKTKH
30
ns
TCTLO-TCTL2 setup
time to TCLK t
tsGTK
50
ns
IOWR, MWR low-level
width (Normal write)
tv-IW2
tCYC -40
TCTLO-TCTL2 hold
time from TCLK t
tHTKG
100
ns
DMARQO-DMARQ3
setup time to
CLKOUT t
tSOQK
15
TOUTO-TOUT2 output
delay from TCLK ~
tOTKTO
100
tOKLOA
0
TOUTO-TOUT2 output
delay from TCTL ~
tOGTO
100
CLKOUT ~ to
DMAAKO-DMMK3
delay
ns
ns
ns
45
ns
Interrupt Control Unit, ICU (figure 27)
INTPO-INTP7 low-level
width
tlPIPL
100
ns
15
ED
NEe
pPD70236 (V53)
Figure 1. Clock Timing
(X1)
CLKOUT
PCLKOUT
~-----tpKH ----~ ~-----tpKL----~
~-----------tCYPK-----------~
83YL·6482B
Figure 2. Reset Timing
CLKOUT
~-I------ tWRSTL------+-I
RESET
RESOUT
'DKRO \ ' -_ _ _ __
83YL·6483B
16
ttiEC
pPD70236 (V53)
Figure 3. B••,c Write (0 Waif
T2
T1
J
CLKOUT
r-
tOKBC-
tOKBC
(TI, T1)
J
_I
J
.tBCBCH-
\
\
I
I -r--tBCBCL
-I
I
)
r-
tOKA-
-
tOKMW
III
~tOKMW
\
)
*
'r-
t OKST -.../
OSTB
r-
J
BUFEN
tHOSHA
tOAOSL
. - tOKos
\
r--
tOKOSH
I
~tosoSL-
r- tOKCT2
~.
- r-
tOKCT2
!
\
tOOSHO
-
tOAD
r- t OKO
\
I
-
I--
tFK
* AMi, M/iQ, BUSSTO, BUSST1, BUSST2, UBE, AEX
83YL-83428
17
NEe
"PD70236 (V53)
Flllur.... B••/e Wrll. (1 "'0
T1
T2
I
CLKOUT
-
tOKBC_
\
-.-
TW
I
--
tOKBC
(TI, T1)
J
tBCBCH
I
\
1
- r-
f-tBCBCL-1
*-
tOKMW
\
MWR
K
)
II
~
tOKA1
)
*
tOKST-I
tOKMW
II
-
r-
-
J
tOAOSL
r+-
I
I--
tOKOS
\
K
~ tHOSHA
tOKOSH
i
J
tOSOSL
-F
~ tOKcT2
-
-
OKCT2
\
- - tDDSHD
-
tOAD
-tDKO
~
>-
p
--.ltS.T..~.
tSRv~~1
j EtHK~
* RIW,
~
C
MliD, BUSSTO, BUSST1, BUSST2, UBE, AEX
83YL-6343B
18
NEe
pPD70236 (V53)
Figure 5. S••'c Rad (0
Hlri~
T2
T1
(TI, T1)
~
J
CLKOUT
t DKBC
I-
tDKBC_
,
}
~
tBCBCH
\
H
\
1
-
I---I-tBCBCL-I
MRD
-
tDKMR
H
tDKMR
\
l-
tDKA1
)
*
tDKST-1
III
~
)
II
I
-
-..
I+-
"K
r-- tDKDSH
tDKDS
\
DSTB
I
J
1\
-- -
tDADSL
tDsDSH
I+-
tDKCT2
~tHDSD
-..
BUFEN
-
I - tDKcT2
\
~tHASD
I - t HRWD
/
tSDK
HI-Z
Hi-Z
tSRYK
:.----..
\
* RMi, M/iQ, BUSSTO, BUSST1, BUSST2, UBE, AEX
-
I
tHKD
t HKRy
83YL-6344B
19
NEe
I'PD70236 (V53)
Figure a. S••/e Read (1 l1li/(,1
T2
T1
CLKOUT
-
tDKBC_
TW
(TI, T1)
I
~
j
t DKBC
~
J
tBCBCH
\
l
\
I
k-- I-tBcBCL-1
-
H
~ tDKMR
\
)
tDKA~
l-
II
II
II
I
)
*
tDKST-l
-
-
~
tDKDSH
~ tDKDS
\~
------
tDADSL
--
~ tDKCT2
j.
tHDSD
~tDSD SH
j.
tHASD
~
~t
DKCT2
~
t HRWD -
\
L
/
~
k:
tSDK
Hi-Z
Hi-Z
-
r
tSRYK
tSRYKI-
~
tHKRY -
* - -
-
I-
\
~
tHKD
f--
-
tHKRY
RIW, MIlO, BUSSTO, BUSST1, BUSST2, UBE, AEX
83YL·6345B
20
NEe
pPD70236 (V53)
Figure 7. External I/O Read (0 l1li/(1
T2
Tl
I)
j
CLKOUT
\
\
~ f-tBCBCL-1
-
-
j
"
r-
t DKBC
I-
tDKBC_
(TI, Tl)
tDKIR
H
tDKIR
\
tDKA~
l-
)
*
tDKST-1
II
I
--
BUFEN
III
X
)
,
I-
II
tDKDSH -
tDKDS
I
X
I
f-
~I\
)
-
t HDSD
I-- tDKCT2
tDSDSH
:.-
f..---.j
tDKCT2
!
\
tSDK
Hi-Z
Hi-Z
tSRYK I - -
READY
\
* RIW, M/iO, BUSSTO, BUSST1, BUSST2, UBE, AEX
-
II
tHKD
tHKRY
83YL-6346B
21
NEe
"PD70236 (V53)
Figure &
External I/O Read (1 . , '
T1
TW
T2
(TI, T1)
/
/
CLKOUT
I-
tDKBC""'"
t_
tDKBC
\
\
~ r-tBCBCL-1
.,...,.
I-
tDKIR
H
tDKIR
\
X
)
II
l-
tDKA-I
)
*
tDKST-i
II
II
..-
.,...,.
+-
-
tDKDSH
t DKDS
\
.,...,.
X
/
L
..
-
-
~ tDKCT2
\
I
~
tSDK
tHDSD
I-
~
CT2
Hi-Z
~
* R1W, M/iO, BUSSTO, BUSST1, BUSST2, UBE, AEX
Hi-Z
\
I
I
tHKD
tSRYK
t SRYK \ -
tHKRY -
t DsD SH
I-
-
t HKRy
83YL-6347B
22
NEe
IIPD70236 (V53)
Figure 9. Externall/O Write (0 WaIO
T2
T1
,j
j
CLKOUT
j
r-
t oKBC
I-
tOKBC_
(TI, T1)
\
\
I+-- I-tBCBCL-
-\
IOWR
I-
tOKIW
-j
tOKIW
X
)
l-
tOKA1
)
*
tOKST
-...J
II
I
f-
-
OSTB
-
I--
tOKOS
X
H
I
tOKOSH
\
k------tososL -
k- tOKCT2
=l
-
\
k-
-
t oKo
~
~
(
r-
tO KcT2
!
I+-
tFK
~
'HKRV
* R/W, M/iO, BUSSTO, BUSST1, BUSST2, UBE, AEX
83YL-6348B
23
NEe
pPD70236 (V53)
Figure 10. External 110 Write (1 l1li/(1
T1
\
CLKOUT
J
I-
tOKBC-
r
tOKBC
\
BCYST
TW
T2
(TI, T1)
Ij
"
J
.\
~ f-tBCBCL-1
-
tOKA
-I
I-
tOKIW
Ht
OK,W
\
)
X
~
II
I
II
X
)
*
tOKST
-.J
-
~
DSTB
BUFEN
-
-1
f+- tOKOS
\
I
tOKOSH
~
-
I- tOKCT2
\k
-
~ tOKO
\;
F'
OKCT2
l~
I
tSRYKH
tSRYKI-I
~
REAOY
tHKRy -
* RJW,- MIlO,- BUSSTO, BUSST1, BUSST2, UBE,
- AEX
~
\
-
tH KRY
83YL-8349B
24
NEe
pPD70236 (V53)
Figure 11. Internal
ua Read
T2
T1
*
TW
T1rr1
-
=x--!...-----~X
~1~tIDKD
Do-D15
TW
--------~
r
* RJW,
tDKCT2
M/iQ, BUSSTO, BUSST1, BUSST2, UBE, AEX
83YL·6359B
25
NEe
,.,PD70236 (V53)
Figure 12. Internal I/O Write
T1
T2
TW
TW
T1fT!
*==r~--------------~x~
---!..-1~t
'OKO
°0·D 15
--------~
I
BUFEN
r
E
t DKCT2
_-----J
* RiW,
MliO, BUSSTO, BUSST1, BUSST2, UBE, AEX
83YL-6360B
26
ttiEC
Figure 13.
pPD70236 (V53)
Bus Sizing (0
./0
T1
T2
(T1.TI)
CLKOUT
BS8/BS16
* RIW. M/iO.
BUSSTO. BUSST1. BUSST2. UBE. AEX
83YL-6361B
27
NEe
pPD70236 (V53)
Figure 14. Bus Sizing (1
./0
T1
T2
TW
(T1,TI)
CLKOUT.
BS8/BS16
* - -
-
RIW, MIlO, BUSSTO, BUSST1, BUSST2, UBE, AEX
83YL-6362B
28
NEe
pPD70236 (V53)
Figure 15. Input S.tup/Hold
CLKOUT
~
SIK
NMI, CPBUSY,
INTPa - INTP7
-------
Figure 16.
~
-t-HK-T---------------83YL-6369B
a. Lock
CLKOUT
III
BUSLOCK
83YL-6370B
29
~EC
pPD70236 (V53)
Figure 17.
Bus Hold
CLKOUT
HLDRQ
HLDAK
*
Hi-Z
CLKOUT
HLDRQ
HLDAK
* ____________________~H~I-~Z~_________________~t~
*
30
AO -A 23 • Do -D15. MliO. BUSSTO. BUSST1. BUSST2. UBE. BCYST. DSTB
83VL-6371B
NEe
Figure 18.
pPD70236 (V53)
Interrupt Acknowledge (Single Mode)
T1
T2
TW
T1
TW
T1
T2
TW
TW
AO-A23
II
tOKCT2
-j
~
tOKCT2
tO KCT2
III
II
INTAK
II
*
II
-iLt
BUFEN
DKcT,
C
tSRYK ~
tSRYK
\
\[
t HKRy
I--
H
t HKRy
~
Hi-Z
_o_srn
BUS LOCK
11 tD~
-
~~______________________________
* RIW.
\r-t_tOK_A_ _ _ _ __
J"
M/iO. BUSSTO. BUSST1. BUSST2. UBE. AEX
83YL·6372B
31
NEe
pPD70236 (V53)
Figure 19.
Interrupt Acknowledge (Cascade Mode)
T1
T2
TW
TW
T1
T1
TW
TW
I II I
I I
II I
~
T2
!: 1-I {'DKCT'
cT2
!
1
~~'DKCT'
II
II
11
tDKCT2
tSDK
* R/W,
32
MliO, BUSSTO, BUSST1, BUSST2, UBE, AEX
83YL·6373B
NEe
Figure 20.
pPD70236 (V53)
Timer/Counter Unit (TCU)
CLKOUT
TCTLO TCTL2
~
_______________________________
tD_K_TO
__-___
.
TOUTOTOUT2
----------------------------~
III
TCLK
TCTLO TCTL2
__________________________tD_G_T_O____
~t:
~---------------~.-
TOUTO)(
TOUT2 _______________________________________---J L -________
DTKTO
t
~
83YL-6374B
33
NEe
pPD70236 (V53)
Figure 21. Serial Control Unit (SCU)
RxD
TOUT 1
I-
1.....1 - - - - 1 6 or 64 TOUT 1 pulses -
Tx D
1--16 or 64 TOUT1 pulses -
--------'1--.
tDTX
83YL-6375B
Figure 22. Refresh Timing
T1
T4
T2
T3
T4
CLKOUT
ID~ ~
Ao-A23 ____________
ttt
ocOCL
~)(~--~----------~----------------------~~------')(~_____________
tl
I
*--------------~)(~~------~~----------------~--J)(---------------------tD_K_C_T_2_~
____________
REFRQ
___{
tDKCT2
1~
-i~
-.J
)+-
~-------"
ISRYK
* R!W,
ylSRYK
M/iO, BUSSTO, BUSST1, BUSST2, UBE, AEX
83YL-6376B
34
NEe
Figure 23.
pPD70236 (V53)
DMA Timing 1
T4
T1
T2
T3
T4
CLKOUT
ED
tOOARW
MRO,IORO
tOKCT1
tOOARW
_
tOWHRH
83YL·6377B
35
NEe
pPD70236 (V53)
Figure 24. DIIA Timing 2
T1
T2
T4
T3
CLKOUT
tDKTCF
tDKTCH
SEDK
tEDED'}.~________________________________________________
_____________{
t
END
__
CLKOUT
DMARQn
(n =0 -3)
*
Pull-up resistance at TC pin = 2200 ohms
83YL·6378B
Figure 25. DIIA Timing 3; Ca.~dellode (Norma' Operation)
CLKOUT
/\.
r
T4
T1
ttSS_DD_QQ~K-Jr~~~------~\~--~
-________
--J
DMARQn
_
(n =0 -3)
~------------------~----------------
tD_K~L~~
_________________
DMAAKn
(n
= 0 - 3)
)7------------------------------'
83YL·6379B
36
NEe
pPD70236 (VS3)
Figure 26. DIIA Timing 4; Refresh Cyclell To Be Inserted
~
CLKOUT
DMARQn
(n=O-3)
r---'5
---.l
______________
~/~tDKLD:r~ ,~------tD-KL-DA----~~~
DMAAKn
(n
= 0 - 3)
_ _ _ __ _
83YL-6380B
Figure 27.
ICU Timing
III
INTPn __ttIPlPLJ__
(n=O-7)
__
83YL-6381A
37
NEe
IIPD70236 (V53)
Figure 28. "elllOry Write tor Coprocessor (0
\
CLKOUT
T1
TC
/
/
r-
tOKBC_
-
t OKBC
\
).
w./~
T2
~
/
tBCBCH
I
\
I
r-tBCBCL-1
I
(
-
t OKA -
(TI,T1)
H t oKMW
MWR
j..--I
-
)
*
-I
-
-
tOKMW
1-
tOKCT2
tOKsT
K
-I
-
tHosHA
t OKOS
~
\
OSTB
tSRYK
\
38
MliO, BUSSTO, BUSST1, UBE, AEX
t OKOS
I
-
_tOSOSL-
* RIVii,
tOK CT2
-
-I
tHKRY
83YL-6382B
NEe
pPD70236 (V53)
Figure 29. Memory Write tor Coprocessor (1
./0
T1
TC
T2
TW
(TI,T1)
I
I
I
1,/
I
r-
ClKOUT
-n
t DKBC
t DKBC
BCYST
I-
f-
.1
tBCBCH
I
\
I
1 -I-tBCBCl-i
=~
-
tDKA
K
f-
H tDKMW
~
-I
-
III
-
tDKCT2
I--
*
I
tDKMW
\
-
t DKCT2
K
-
tDKST
-I
-
tHDSHA
t DKDS
~ tDKDS
\
DSTB
I
tDSDSl
tSRYK~
READY
* R/W, wiD, BUSSTO, BUSST1, UBE, AEX
-
tSRYK
\
-
\
I
-
tHKRY
I
-
tHKRY
83YL·6383B
39
NEe
pPD70236 (V53)
Figure 3D. lIemory Read for Coproctlllllor (0 ./0
..-
tOKBC-
\
)
-
)
t OKST
OSTB
-I
_I
..-
..
J
tBCBCH
I
\
-tBCBCL-1
I
-I 11",r
--I
..- t OKCT2
tOKOS
..- t OKOS
-.!
tOSOSH-
tSRYK
\
* RIW, M/iO, BUSSTO, BUSST1, UBE, AEX
..-
r-
L
\
J
tOKMR
t OKCT2 -
tOKMR
tOAOSL
40
/
~
I
-\
-
BUFEN
*
t OKBC
..-
tOKA-
(TI, T1)
~
J
CLKOUT
T2
TC
T1
-
-
1..-
t HKRy
83YL-6384B
ttiEC
pPD70236 (V53)
Figure 31. Memory RfNld tor Coprocessor (1./0
T1
CLKOUT
-
BCYST
TC
T2
TW
(TI. T1)
\
~
I
---
~ tOKBC
~tOKBC
I
tBCBCH
n
I
\
t
1 - '-tBCBCL-1
~
-
tOKA ~
~
-ltOKST
ED
\
-\
*
1-
tOKMR_
-
-
-~
tDK~2)-
tOKMR
tOKCT2
tOKDS
_ t OKOS
\
~
I
IOAOSL
ISRYK!-
tHKRy -
\
-
r'-
ISRYK
1\
REAOY
* Rlw. M/iO. BUSSTO. BUSST1. UBE. AEX
-..J
IOSOSH-
-
IHKRY -
83VL·6385B
41
pPD70236·· (V53)
FUNCTIONAL OPERATION
•
•
•
•
•
•
•
The I'PD70236 is described under these major headings.
•
•
•
•
Central Processing Unit
Clock Generator
Bus Operation
System ControlI/O
Wait Control -Unit
Refresh Control Unit
Timer/Counter Unit
Serial Control Unit
Interrupt Control Unit
DMA Control Unit
Power Conservation
Figure 32.' CPU BIDCk DllIIJI'sm
)I
II
PS
DSO
DS1
c:::>
SS
PFP
f'
~""
II
Address
Translation
Table
?"
Internal
Address Bus
Address
Expansion
Control
)
ToBIU
)
ToBIU
/'.
p
Internal Data
Bus
LC
~
PC
AW
<=
OW
P
EAG
BW
CW
ODR
(I
PO
P
U
IX
L---
IV
'---
~
Pre-Decoder
BP
SP
Registerl
ALU
Control
U
TC
p
TA
P
Main Decoder
TB
M
U
I
PSW
Sub Data Bus
(16)
Execution
Control
lc
Co-Processor
Control
Interrupt
Control
I-
INT (from ICU)
I-
NMI
Main Data Bus
(16)
83YL-6216B
42
NEe
pPD70236 (V53)
CENTRAL PROCESSING UNIT (CPU)
are general-purpose registers (AW, BW. Cw. DW, IX. IV, BP.
and SP). These contain either operand data or point-to.operand data in memory.
Architecture
A unique hardware architecture feature of the CPU is that
it contains no microcode. Instruction decode and data
path control are implemented using logic and small
independent state machines. This greatly enhances instruction execution speed. The V53 is four times faster
than the V30.
The CPU comprises the execution unit and the address
generator. Figure 32 is the CPU block diagram.
CPU Execution Unit
The execution unit consists of a register file. an ALU. and
instruction decode and execution control logic.
In addition to the hardware control logic. the most
significant feature of the execution unit is a dual-bus
internal data path (figure 33). The AW and many registers are dual ported with a data bus on each port. This
allows two operands to be transferred in one clock cycle
instead of two. Performance is improved as much as
30% by the dual data bus concept.
Figure 33. DuII'O.'. Buses
Subdata
Bus
Main Data
Bus
The temporary registers speed up instruction execution
by serving as scratch pad registers during complex
operations.
The loop counter (LC) is used during primitive block
transfer operations. It contains the count value. It is also
a shift counter for multiple-bit shift and rotate instructions.
Temporary registers TA. TB. and TC are inputs to the
AW. They are used as temporary registers/shifters during multiply. divide. shift/rotate. and BCD rotate operations.
AW. The ALU consists of a complete adder ar1d logical
operation unit. It executes arithmetic (ADD. SUB. MUL.
DIV. INC. DEC. NEG. etc.) and logical (TEST. AND. OR.
XOR. NOT, SET1. CLR1. etc.) instructions.
Data Path Control Logic. This logic comprises the
main instruction decoder and the execution control
blocks. Its purpose is to determine which operations
must be done and to schedule them. It transfers operands. as required. and controls the ALU. State machines
implement long. complex instructions.
.
Instruction Prefetchlng. The V53 is a pipelined machine. To keep the pipeline running efficiently. it should
be kept full of instructions in various stages of execution. Instructions are fetched before they are needed and
placed in the instruction processing queue (lPQ).
Data in the IPQ is broken out by the decoder logic to
determine what addressing modes will be used and what
CPU resources are required to execute the prefetched
instruction. To keep the a-byte IPQ full, the bus control
logic schedules an instruction prefetch cycle whenever
there are at least 2 unused bytes in the IPQ.
The IPO is cleared whenever a control transfer instruction (any branch. call, return. or break is executed). This
is done because a different instruction stream will be
used following a control transfer, and the IPO will then
contain instruction data that will never be used. When
this happens. the V53's pipeline is emptied and performance is reduced. To maximize performance. the number of control transfers should be minimized.
49NR-247A
Register File. There are 12 registers in the internal RAM.
Four are temporary registers used in the execution of
certain instructions (LC. TA. TB. and TC). The other eight
Effective Address Generator. The effective address
generator (EAG) logic computes a 16-bit effective address for each operand. This address is an offset into one
of the four segments. Refer to figure 34. This effective
address is passed on to the address modifier adder. The
EAG decodes the first byte(s) of each instruction to
43
ED
NEe
JlPD70236 (V53)
determine the addressing mode and initiates any bus
cycles required to fetch pointers/offsets from memory.
Effective addresses are calculated in a maximum of 1
clock period as compared with 5 to 12 clocks for a
microprogrammed machine.
Figure U. Effective Address Generator
Effective Address
49NR-248A
. Address Generator
The address generator comprises the address register
file, the address modifier (ADM), the address translation
table, and the needed control logic.
The registers in the address register file are PS. SS, DSO,
DS1, PC, and PFP. The ADM is a dedicated adder that
adds one of the segment registers to the effective address to produce the 20-bit normal address. The ADM
also increments the prefetch pointer. If extended addressing is enabled, the address translation table is
accessed to map the 20-bit address into a 24-bit extended address.
For instruction stream data, addresses are generated
differently. The prefetch pointer contains a 16-bit offset
into the PS segment that points to the next instruction
word to be prefetched. The program counter contains an
offset into the PS segment that points to the instruction
that is currently being executed. As part of all control
transfers, the PFP is set to the same value as the PC.
CPU Addressing Mechanism
The V53 is completely compatible with the p.PD70108/116
in its addressing modes and in the way that addresses
are computed. It offers a method of expanding the
memory address space to 16M bytes.
The I/O space is 64K bytes (16-bit address). The normal
memory address space is 1M byte (20-bit address), and
the expanded address space is 16M bytes (24-bit address). See figure 35. Expanded addreSSing is enabled or
disabled using the BRKXA and RETXA instructions.
The memory space is accessed when an instruction uses
a memory addressing mode. Memory addresses are
44
calculated as described below. The I/O space can only
be accessed through the IN, OUT, INM, and OUTM
instructions.
Certain areas of the V53 address spaces (physical for
normal mode and logical for expanded addressing
mode) are reserved .. Memory addresses 0-3FCH are
used for the interrupt vector ta.ble (figure 35) located in
the interrupt operation section. Memory addresses
FFFFOH-FFFFFH must contain a branch to boot code;
PC, PFP, and PS are initialized at RESET to point to this
area.
I/O addresses FFOOH-FFFFH are reserved for the address translation registers and system control registers.
The DMAU, TCU, ICU, and SCU sections each contain a
block of registers with programmable base addresses.
They may be located inside any 256-byte block in the I/O
space. See figure 36.
Figure 35. lIIemory Address Space
16M B
FFFFFFH r - - __ _ .:.,.yte_s---,
1M Bytes
FFFFFH
FFFFCH
FFFFBH
Reserved
Reset Vector
1 Page = 16K Bytes
FFFFOH
1 Page = 16K Bytes
1024 Pages
64 Pages
3FCH
Interrupt
Vector Table
Normal Memory
Address Space
~
01
~
1
Expanded Address Mode
Address Space
49NR-334A
I/O Addresses
I/O devices can be referenced by 8-bit immediate addresses or by 16-bit addresses via the OW register. If I/O
operations require other more complex addressing
modes, the I/O devices must be placed in the memory
address space (using memory-mapped I/O techniques).
For· memory-mapped I/O devices, there are no restrictions on instruction or addressing mode usage. However,
the V53 will not automatically insert 6 clock cycles after
NEe
pPD70236 (V53)
memory-mapped 1/0 operations; external logic must
provide the necessary I/O device recovery time.
Figure 36.
Figure 37. 2O-8il AddrellS
15
va Address Space
15
FFFFH
System Control
and Address
Translation
Registers
FFOOH
Normal Mode Physical Address
or
Expanded Mode Logical Address
DMAU
Within
256 Bytes
in the
Internal 110 Area
ICU
49NR-349A
TCU
If normal addressing mode is enabled, this 20-bit result is
presented on the address bus during the bus cycle. If
expanded addressing mode is enabled, this address is
used as a logical address.
SCU
Expanded Addresses
OOOOH
83YL-6549A
Normal Memory Addresses
The V53 is a 16-bit device with 16-bit registers. To allow a
memory address space larger than 64K bytes, memory
segmentation is used. The 1M-byte memory address
space is divided into 64K-byte'segments. Up to four
segments can be in use at any given time. The base
addresses of the four active segments (program segment, stack segment, data segment 0, and data segment
1) are contained in four 16-bit segment registers (PS, SS,
OSO, and OS1, respectively). The 16-bit value in each
register is the upper 16 bits of the 20-bit memory address. Thus, segments must start on 16-byte boundaries.
As described above, the V53 hardware generates a 16-bit
effective address for each memory operation. This effective address is an offset into one of the four active
segments. The actual 20-bit memory address is computed by adding the EA to the segment register value
expanded with zeros to 20· bits. Figure 37 shows this
process.
In the expanded addressing mode, the memory space is
divided into 1024 pages (figure 35). Each page is 16K
bytes. Each page of the normal 20;.bit address space is
mapped to a page in the expanded address space using
a 64-entry address translation table. The table is made
up of 64 page registers that reside in the 1/0 space.
The programming model of this mode is the same as for
the normal mode. Address expansion. is a layer added to
the normal mode that is transparent to executing code.
The program still sees a 20-bit contiguous logical memory address space, but the hardware sees 64 pages
mapped into a set of 1024 physical pages.
The 1/0 space is not affected by the expanded addressing mode.
The address translation mechanism is shown in figure
38. The upper 6 bits of the logical 20-bit address select
one of the entries in the address translation table, which
supplies a 10-bit value. This value is substituted for the
original 6 bits in the normal address to create a 24-bit
expanded address.
45
mil
E.JI
NEe
"PD70236 (V53)
Figure 38. Address Translation Mechanism
Figure 39. Addr.s Expansion Registers
Page Registers
20-Bit Logical Address
Page Offset
o
14
PGR Selected
PGR I/O Addr•••
PGR1
FFOO
PGR2
FF02
2
PGR3
FF04
3
PGR4
FF06
63
PGR64
FF7E
Translation Table
XAM Regllt.r
15
14 13
o
Operand Addressing Modes
24-Bit Expanded Address
49NR-335A
Address Expansion Registers
These are the page and XAM registers, accessed by the
word IN and OUT instructions. Figure 39 shows page
register usage and 1/0 addresses. The page registers
contain the 10-bit physical page base address. The XAM
register is a read-only status flag that indicates whether
expanded addressing is enabled.
Unused data bits in the XAM register are read as O.
Expanded addressing must be disabled before accessing any of the page registers. That is, if expanded mode
is enabled, the page registers cannot be accessed. This
prevents an expanded mode task from accidentally modifying its memory map.
For operand addressing, the V53 offers nine modes.
•
•
•
•
•
•
•
•
•
Register
Immediate
Direct
Register indirect
Indexed
Based
Based indexed
Bit
Autoincrement/autodecrement
Register. The operand is in a V53 register pointed to by
the instruction.
Immediate. The operand is in the instruction stream
following the opcode of the instruction. This data will
have been prefetched. Immediate. data uses the V53
pipeline efficiently.
Direct. Immediate data in the instruction stream points
directly to the operand. This data can be a 16-bit effective address or a bit field length of 4 bits.
Register Indirect. A 16-bit register (IX, IV, or BW)
contains a 16-bit effective address.
Indexed. One or two bytes of immediate data are
treated asa signed displacement that is added to the
contents of a 16-bit index register (IX or IV) to obtain a
16-bit effective address.
Based. One or two bytes of immediate data are treated
as a signed displacement that is added to the contents of
a 16-bit base register (BP or BW) to form a 16-bit
effective address.
Based Indexed. One or two bytes of immediate data
are treated as a signed displacement that is added to two
46
1\'EC
16-bit registers (BP or BW and IX or IV) to form the
effective address. This mode is useful for array addressing.
Bit. Used with NOT1, ClR1, or TEST1. A 4-bit immediate
data value SET1 selects a bit in a 16-bit operand. For
8-bitoperands,· only 3 bits are used.
Autolncrement/Autodecrement. Some iterative operations (such as MOVBK or IN S) will automatically increment or decrement index registers after each iteration.
Specifically, IX is used in addressing a source pointer,
and/or IY is used in addressing a destination pointer.
After the operation, both will be incremented or decremented (according to the PSN DIR control flag) to point
to the next operand in the array.
Instruction Addressing Modes
Instruction address modes are basically the same as the
operand addressing modes, but the PC is always used in
the register. These modes are used in control transfer
instructions.
• Direct
• Relative
• Register
• Register indirect
• Indexed
• Based
• Based indexed
Direct. Four bytes of immediate data are taken as an
absolute address and loaded directly into the PS and PC
(and PFP).
Relative. One or two bytes of immediate data are a
signed displacement that is added to the contents of the
PC, and then placed in the PC (and PFP). This mode is
useful to create position-independent code.
Register. The register selected by the instruction (AW,
BW, etc.) contains an effective address, which is loaded
into the PC (and PFP).
Register Indirect. An index register (IX, IV. or BW)
points to a memory location that contains an effective
address (short pointer) or a segment register value and
the effective address (far pointer). This effective address
is read from memory and loaded into the PS and/or PC
(and PFP).
Indexed. One or two bytes of immediate data are a
signed displacement added to the contents of a 16-bit
index register (IX or IV) to form an effective address. This
address is used to fetch another effective address from
memory, which is then loaded into the PC (and PFP).
,.,PD70236 (V53)
Based. One or two bytes of immediate date are a signed
displacement added to the contents of a 16-bit base
register (BP or BW) to form an effective address. This
address is used to fetch another effective address from
memory, which is then loaded into the PC (and PFP).
Based Indexed. One or two bytes of immediate data are
a signed displacement added to the contents of two
16-bit registers (BP or BW and IX or IV) to form an
effective address. This address is used to fetch another
effective address from memory, which is then loaded into
the PC (and PFP).
CPU Register Configuration
Program Counter (PC). The ,PC is a 16-bit register
containing the effective address of the instruction currently being executed. The PC is incremented each time
the instruction decoder accepts a new instruction from
the prefetch queue. The PC is then loaded with a new
value during execution of a branch, call, return, or break
instruction, and during interrupt processing.
Segment Registers (PS, SS, DSO, DS1). There are four
segment registers, each containing the upper 16 bits of
the base address of a 64K logical segment. Since logical
segments reside on 16-byte boundaries, the lower 4 bits
of the base address are always zero. Normal 20-bit
memory addresses are formed by adding the 16-bit
effective address to the base address of one of the
segments. During this operation, certain types of effective addresses will be paired with specific segment
registers.
Segment Register
PS (program segment)
SS (stack segment)
DSO (data segment 0)
DS1 (data segment 1)
Default Offset
PFP
SP, effective address
IX, effective address
IY
Program instructions will always be· fetched from the
program segment. Whenever the IY index register addresses an operand, the DS1 segment register will be
used. DSO is usually used with IX. Stack operations with
the SP will always use the stack segment. For other
effective addresses, the table above shows the default
segment, but another segment may be selected by a
segment override prefix instruction.
General-Purpose Registers (AW, BW, Cw, DW). The
four 16-bit general-purpose registers can be accessed as
16-bit or 8-bit quantities. When the AW, BW, Cw, or rJN
destination is used, the register will be 16 bits. When Al,
AH, Bl, BH, Cl, CH, Dl, or DH is used, the register will
be 8 bits. Al will be the low byte of PW and AH will be the
high byte, etc.
47
mil
.:II
NEe
,.,PD70236 (V53)
Some operations require the use of specific registers.
Operation
Word multiplication/division, word I/O,
data conversion
Byte multiplication/division, byte I/O, BCD
rotation, data conversion, translation
Byte multiplication/division
Translation
Shift instructions, rotation instructions,
BCD operations
Word multiplication/division, indirect
addressing I/O
AL
AH
BW
CW
Pointer (SP, BP) and Index Registers (IX, IV). These
registers are used as base pOinters and index registers
when based, indexed, or based indexed addressing
modes are used.
They may also be used as general-purpose registers for
data transfer, arithmetic, and logical instructions. They
can only be accessed as 16..bit registers.
Some operations use these registers in specific ways.
Register
SP
IX
IV
Operation
Stack operations
Source pointer for block transfer, bit field,
and BCD string operations
Destination pointer for block transfer, bit
field, and BCD string operations
Program Status Word (PSW). The program status word
reflects the status of the CPU by six status flags and
affects the operation of the CPU by three control flags.
PSW
15
I
1
I
1
I
1
I
z
I
0
I
8
V
DIR
I
IE
I BRK I
P
I
1
CY
0
7
S
Status
V
S
Z
AC
P
CV
48
AC
Flags
Overflow
Sign
Zero
Auxiliary carry
Parity
Carry
0
I
Control
DIR
IE
BRK
Flags
Direction
Interrupt enable
. Break
The DIR control flag determines whether address pointers are incremented (1) or decremented (0) for block
(string) operations. IE enables interrupts (1) or disables
interrupts (0). BRK enables (1) or disables (0) the single
stepping trap (vector 1).
The P&N cannot be accessed directly as a 16-bit register.
Specific instructions set/reset the control flags. When
the PSW is pushed on the stack (as during interrupt
processing), the PSW is set as shown in the diagram
above.
Interrupt Operation
The interrupts supported by the V53 can be divided into
two types: those generated by external interrupt requests and traps generated by software processing.
Interrupts of each type are listed below.
•. External Interrupts
- NMI input (nonmaskable)
- INTPO-INTP7 (maskable)
• Software Traps
- Divide error during DIV or DIVU instruction
- Array bound error during CHKIND
- Single-step (PSW BRK flag = 1)
- Undefined instruction
- Coprocessor error
- Coprocessor not connected
- Break instructions (BRKV, BRK3, BRK imm8,
BRKXA)
The eight INTP interrupts are handled by the interrupt
control unit (ICU). The leu prioritizes the INTPs and
produces a single INT output, an internal signal that
goes to the CPU interrupt logic.. There the interrupt
prioritization· flow diagram (figure 40) is implemented.
Interrupts are prioritized by the CPU as follows.
NMI (highest priority
INT
BRKflag
Other software interrupts and exceptions
NEe
Figure 411.
pPD70236 (V53)
Interrupt Pl'loritizstlon Row Dlllllram
Complete
current
Instruction
*
If current Instruction causes Internal Interrupt, SOFT flag = 1
At the end of current Instruction:
• If BRK flag In PSW= 1, BRK = 1
• If INT from leu Is sampled, INT = 1
• If NMllnput Is sampled, NMI = 1
III
Execute
next instruction
83YL-6327B
49
NEe
pPD70236 (V53)
Interrupts are not accepted by the CPU at certain times.
NMI, INT, and BRK flags are not accepted under the
following conditions.
(1)
(2)
(3)
Between execution of a MOV or POP that uses a
segment register as an operand and the next
instruction.
Between a segment override prefix and the next
instruction...
Between a repeat or BUSLOCK prefix and the next
instruction.
INT is not accepted when the PSW IE flag is 0, or
between an RETI or POP PSW and the next instruction.
Once an interrupt has been accepted by the CPU, an
interrupt service routine will be entered. The address of
this routine is specified by an interrupt vector stored in
the interrupt vector table (figure 41). For most interrupts, the vector used depends on what interrupt is
being processed (e.g., NMI always uses vector 2). For
INT and BRK imm8 interrupts, any vector may be used;
the vector number is supplied by the ICU or an external
device (such as a j.lPD71059) in the case of INT, or by
immediate data in the case of BRK.
The interrupt vector table uses 1K bytes of memory at
addresses OOOH to 3F FH and stores up to 256 vectors.
Figure 41. Interrupt Vector Table
OOOH
004H
008H
OOCH
010H
014 H
018 H
Vector 0
Divide Error
Vector 1
Break Flag
Vector 2
NMllnput
Vector 3
BRK 3 Instruction
Vector 4
BRKV Instruction
VectorS
CHKIND Instruction
~~
Dedicated
~
Vector 31
------i1.
f
~
080H
Vector 32
~
1E8H
INT Input [External]
t-_--Vec-t-or-1-22----I
Vector 128
Undefined Instruction Trap
General Use
• BRK Imm8 Instruction
• INT Input [External)
ILPD72291 AFPP Error
Vector 129
Other Coprocessor Error
,
i"
200H
204H
208H
~"
'f
3FCH
50
~
1
002H
PC ~ [001 H, OOOH]
PS ~ [003H, 002H]
49NR-345A
Based on this format, the contents of each vector
should be initialized at the beginning of the program.
The basic mechanism for servicing an interrupt follows.
(SP - 1, SP - 2) - PSW
(SP - 3, SP - 4) - PS
(SP - 5, SP - 6) - PC
SP - SP - 6
IE - 0, BRK - a
PS - vector high bytes
PC - vector low bytes
When an interrupt is accepted, two possible PC values
could be saved. For some interrupts, the offset of the
current instruction is saved. These interrupts are divide
error, CHKIND, illegal opcode, j.lPD72291 FPP error,
other coprocessor error, and CP not present. For the
other interrupts (NMI, BRKflag, BRK instruction, or ICU
interrupt), the offset of the next instruction is saved.
CLOCK GENERATOR (CG)
The source frequency is divided to supply various
clocks to internal units (CPU, DMAU, etc.) and to external devices at pins CLKOUT and PCLKOUT.
General Use
'f . BRK Imm8 Instruction
r~====vec==tor=2=55===~1
OOOH
003H
For operation with an external clock, the maximum
delay through the inverter connected to pin X2 should
not exceed 20 ns.
Coprocessor Does Not Exist
Vector 130
Vector 0
001H
For crystal operation, the crystal should be AT-cut,
fundamental mode, and parallel resonant. Connect a
5-pF capacitor from pin X1 to ground and a 15-pF
capacitor from pin X2 to ground.
General Use
• BRK Imm8 Instruction
~
Figure 42. Interrupt Vector 0
The clock generator (figure 43) is driven by a crystal
connected to pins X1 and X2 or' an external clock
connected directly to pin X1 and through an inverter to
pi n X2. The frequency of the crystal or external clock is
twice the frequency of the CPU clock.
tR.reN~
Vector 6
07CH
j
Each interrupt vector consists of four bytes. The two
low bytes are loaded into the PC as the offset, and the
two high bytes are loaded into the PS as the base
address. See figure 42.
• INT Input [External)
49NR-332A
NEe
pPD70236 (V53)
Bus Arbitration Unit (BAU)
Figure 43. Clock Gener.tor Dillflr.m
The BAU accepts and grants five different requests for
bus mastership in the following priority order.
X1
X2
Programmable
Frequency
Divide-by
1,2,4,orS
CPU Clock
CPU, DMAU,
REFU,SCU
CLKOUT
PCLKOUT
1-----
REFU demand (highest)
DMAU request
HLDRQ
CPU request
REFU request
The refresh unit is assigned both the highest and the
lowest priorities. Normally, REFU requests are made,
and if the bus is not granted, they are placed in a queue.
Once the queue depth reaches seven requests, a refresh
demand is made, and the BAU gives this the highest
priority.
TCU
Bus Wait Function
BRC
83VL-6217A
BUS OPERATION
The V53 uses a synchronous bus interface. The X1 and
X2 inputs provide a reference oscillator frequency for the
internal clock generator, which supplies the main system
clock to the ,other .internal devices and to external
devices via the CLKOUT pin. All V53 bus timings and
instruction execution clock counts are specified relative
to the CLKOUT signal. Bus cycles start on the falling
edge of CLKOUT.
The V53's internal bus is a multimaster, shared bus. The
CPU, DMAU, or REFU can all be bus masters. Each
requests bus mastership from the bus arbitration unit
(BAU). External devices can also request mastership of
the bus using the HLDRQ input.
Bus Interface Unit (BIU)
The BIU contains the interface logic that allows the three
internal bus masters (CPU, DMAU, and RE FU) to control
the external address, data, and control buses. The BIU
also synchronizes the BS8/BS16, RESET, and READY
inputs to the system clock. When a reset signal is
acceptec!, the BIU asserts the RES OUT output.
When the bus is active and the BAU receives a higher
priority request, the BAU will take away its grant to the
current bus master. But the current master may not
release the bus immediately. The BAU will wait until the
current master takes away its request before granting
the bus to the higher priority requester. This is called bus
waiting.
For example, if an external device has been granted the
bus via the HLDAK output, and the DMAU requests the
bus (DMA is higher priority than HLDRQ), the V53 will
deassert HLDAK but will not take the bus back until the
external master deasserts HLDRQ. Note that the external master is not required to immediately release the bus
back to the V53; the BAU will wait until HLDRQ is
removed.
Usually a higher priority request will be granted quickly;
for example, if a DMA request is accepted during T2 of a
CPU bus cycle, the next bus cycle will usually be a DMA
cycle. However, each internal bus master will hold onto
the bus under certain circumstances.
The CPU will not let go of the bus as long as the
BUSLOCK prefix is used, or until the current bus operation is completely finished (an unaligned or bus-sizing
operation may take more than one bus cycle). Likewise,
when it is in bus hold mode, the DMAU will not release
the bus until all active DMA requests have been processed.
This mode should be used with care as it can result in
DRAM refresh errors if the DMA takes a long time to
complete. Note that bus hold mode is only available
when DMAU is in ",PD71071 compatibility mode;
",PD71037 mode is always in bus release mode.
51
III
NEe
"PD70236 (V53)
External Bus Masters
Figure 44. CPU Bus State Diagram
At times, external bus masters will need to use the V53
bus. There are two methods provided for that purpose:
hold request and DMA cascade. Up to five external bus
masters can be connected to the V53.
Hold Request. The external bus master can request the
bus using a hold request. Hold request is implemented
using the HLDRQ and HLDAK signals. The V53 grants
the bus by floating many of its outputs and asserting
HLDAK to notify the external device that the bus is now
free.
BUSRO= 1
CPUGT= 1
READY = 1
BUSRO= 1
CPUGT= 1
DMA Cascade. DMA cascade is very similar to hold
request; the difference is that a DMARQ/DMAAK signal
pair requests and grants the bus. While DMA cas.cade is
meant to be used to connect additional DMA controllers,
it can be used by any type of external bus master. Since
there are four DMA channels, each of which can be in
cascade mode, up to four external masters can be
connected by DMA cascade.
BUSRO=O
CPUGT= 1
Bus Cycle Descriptions
Each of the internal bus masters uses the V53 bus
interface 'in a different way: DMA bus cycles have a
different structure than CPU bus cycles or REFU cycles.
There are 18 different V53 bus cycles summarized previously in table 1.
CPU Bus Cycles
The bus state diagram for CPU cycles is shown in figure
44. CPU bus cycles are nominally two clock periods long,
and may be extended by adding wait states using either
the internal wait state generator or the external READY
input.
TI
T1
T2
TW
TH
CPUGT= 0
READY = 1
BUSRO=O
CPUGT= 1
READY = 1
Idle state
Start bus cycle
Sample READY, DATA
Wait for READY = 1
Bus hold state; release bus to external BAU
BUSRO = 1 when a read or write bus cycle is requested.
CPUGT = 1 when BAU grants internal bus to CPU.
83YL-6548A
The first state of every bus cycle is T1, and it is followed
immediately by T2. READY is sampled on the rising
(middle) edge of T2. If READY is not asserted, the next
bus state will be the TW wait state. TWs will be inserted
until READY is sampled low, after which the bus cycle
will finish. TWs also will be inserted by the wait state
generator, and the READY input is ignored until all TWs
programmed in the wait state have been inserted. The
dynamic bus sizing input, BS8/BS16, is sampled at the
same time as READY.
Note that dynamic bus sizing is only implemented for
CPU cycles; DMAU or REFU cycles do not use this input.
Address and bus status are output after the leading edge
of T1, and maintained until after the cycle is completed.
A strobe, BCYST, is asserted during T1 to indicate the
beginning of a bus cycle. BCYST is output following the
leading edge of T1 and deasserted after the leading edge
ofT2.
Write data is driven on Do-D15 following the rising (middle) edge of T1, and maintained until after the rising edge
of T2 or the last TW. Read data is sampled on the trailing
52
NEe
pPD70236 (V53)
edge of T2 or the last TW state. A strobe, OSTB, gives
the status of the V53 data bus. OSTB is asserted after
the risi ng (m iddle) edge of T1. OSTB is oeasserted after
the rising edge of T2 or the last TWfor a write cycle, and
after the trailing edge of T2 or the last TW for a read
cycle.
I/O cycles are identical to memory cycles except for the
encoding of the bus status lines. However, six idle
states are inserted after every I/O bus cycle to provide
a recovery time for the I/O devices.
Dynamic Bus Sizing for CPU Cycles
The V53 supports dynamic bus sizing for CPU cycles.
On a cycle-by-cycle basis, the width of the data bus can
be changed from 16 t08 bits. This simplifies connection
with 8-bit I/O devices that may have internal registers
at consecutive byte addresses. Other 16-bit CPUs require two ROMs for startup code, but the V53 dynamic
bus sizing makes it possible to use a single 8-bit wide
ROM.
Table 3.
Write Cycle Bus Sizing
Type
Address
Byte
Even
External logic requests an 8-bitdata path by driving
BS8/BS16 low in time for the V53 to sample it on the
rising edge of T2 (or TW). The. V53 will perform an
additional cycle if needed to finish the operation in
byte-wide pieces.
If the bus operation is already 8 bits wide, no further
bus cycles will occur (refer to tables 3 and 4). For a read
cycle, the data will be sampled on 07-00. For a write
cycle to an even address, data wi II be driven on OrOo.
On all byte writes to an odd address, the V53 will put the
byte data on both the upper and lower data .buses so
that the write data will be on OrOo as well as 015-08'
If the bus operation is 16-bit, two bus cycles will be
required. The first one, in which BS8/BS16 is sampled
low, will handle the low byte. The second cycle will take
the form of a byte read or write using 07- 0 0'
16-Bit Bus (BS8/BS16
UBE
Ao
0
Odd
Word
Even
0
0
0
Odd
0
0
Note: Lower
=
Table 4.
Read Cycle Bus Sizing
Type
Address
Ao
Byte
Even
0
low-order byte; Upper
=
Word
Even
0
Odd
= 0)
07- 0 0
015- 0 8
01" 0 0
1st
Invalid
Lower
Invalid
Lower
1st
Lower
Lower
Lower
Lower
1st
Upper
Lower
Upper
Lower
2nd
Not needed for 16-bit bus
Upper
Upper
1st
Lower
Lower
Lower
Lower
2nd
Lower
Upper
Lower
Upper
high-order byte
UBE
= 1)
8-Bit Bus (BS8/BS16
= 0)
Cycle
015- 0 8
01" 0 0
015- 0 8
01" 0 0
1st
Not used
Lower
Not used
Lower
0
1st
Lower
Not used
Not used
Lower
0
1st
Upper
Lower
Not used
Lower
2nd
Not needed for 16-bit bus
Not used
Upper
0
0
8-Bit Bus (BS8/BS16
015- 0 8
16-Bit Bus (BS8/BS16
Odd
= 1)
Cycle
1st
Lower
Not used
Not used
Lower
2nd
Not used
Upper
Not used
Upper
Note: Lower = low-order byte; Upper = high-order byte
CPU Bus Cycle Types. There are many types of CPU
bus cycles (shown previously in table 2). They comprise
read, write, and acknowledge cycles.
CPU Read Cycles. There are six CPU read cycles:
memory, external I/O, internal I/O coprocessor, copro-
cessor data reads, and instruction fetch. All have the
general timing described previously. Coprocessor
reads access the internal registers of an external coprocessor. Coprocessor data reads transfer data from
memory to an internal coprocessor register. Instruction fetches fill the V53's 8-byte instruction queue from
53
III
NEe
JlPD70236. (V53)
internal or external I/O device or a memory location.
During internal I/O reads, the lORD and BUFEN outputs
are not asserted.
Dynamic bus sizing is ignored during the interrupt acknowledge cycles. Wait states can be inserted by the
internal wait state generator or by the READY input.
Dynamic bus sizing is ignored during internal I/O read
cycles, and is not recommended for coprocessor data
read cycles. The wait state generator does not affect
internal I/O reads ()r coprocessor reads. READY is used
for all CPU read cycles.
Halt Acknowledge Cycle. When the CPU executes a
HALT instruction, a halt acknowledge bus cycle is issued
to notify external logic that the V53 is entering a standby
mode. This cycle is always two clocks long; READY is
ignored and DSTB is not asserted. The V53 has several
standby modes.
CPU Write Cycles. There are five types of CPU writes.
Memory writes transfer data from the V53 to a memory
location. External and internal I/O writes transfer data
from the V53 to external or internal I/O devices. During
internal 1/0 writes, the 10WR and BUFEN outputs are not
asserted. Coprocessor data writes transfer data from an
external coprocessor to a memory location. Coprocessor writes transfer data from the V53 directly to a
coprocessor internal register:
Dynamic bus sizing is ignored during internal I/O read/
writes, and is not recommended for coprocessor data
write cycles. The wait state generator does not affect
internal I/O writes or coprocessor writes. READY is used
for all CPU write cycles.
Interrupt Acknowledge Cycles. The CPU interrupt acknowledge operation takes two consecutive bus cycles.
The first cycle freezes the state of the internal interrupt
control unit (ICU) and any external slave p,PD71059
interrupt controllers. The second bus cycle reads an
8-bit vector number on 07-00, supplied by either the ICU
or an· external slave. This vector number is then used by
the CPU as an index into the interrupt vector table to
select an interrupt handler: The BUSLOCK output is
asserted for the first cycle, and remains asserted until
after the second to guarantee that no other bus master
will take control of the bus until the interrupt has been
accepted.
There are two types of interrupt acknowledge cycles
produced by the V53: a master and a slave. The INTAK
output is asserted for both types, and should be connected to the interrupt acknowledge inputs of all slave
devices. The master cycle is used for the first INTAK to
both internal and external ICUs, and the second INTAK
to the internal ICU. The slave cycle is used only for the
second INTAK to an external slave device.
During the slave cycle, the address of the slave device to
be used is presented on A2-Ao. These address lines
should be buffered and then connected to the slave
address inputs of the external ICUs. Buffering is necessary because the slave address pins of external devices
might be in an output state on power-up, producing a
bus conflict on A2-Ao if they are connected directly.
54
DMA Unit Bus Cycles
Figure 45 shows the bus state diagram for DMA bus
cycles. There are eight different states. When the DMAU
is idle, it is in state SI. In this state, it is continually
sampling the four DMARQ inputs. When a request is
detected, the DMAU requests use of the V53 bus from
the BAU, and enters state SO. It remains in SO until the
BAU grants the bus to the DMAU, at which point the
actual DMA bus cycle starts with state S1. Addresses
and control status are output along with BCYST and
DMAAK.
DMA bus cycles are nominally four clocks long, but they
can be stretched by the internal wait state generator or
READY. S1 always changes to S2 and then to S3.
Memory and I/O strobes are asserted during S2, S3, and
Sw. READY is sampled during S2 for use during S3. If
waits are inserted, the SW state is entered. Control stays
in that state until no more waits are desired. If no waits
are inserted, S3 moves to S4 and the current cycle is
over:
Depending on the DMA mode, another DMA cycle might
be ready to start immediately (e.g., in burst mode), or
another DMA request input may now be asserted. During
S4, a decision is made whether to begin another DMA
cycle at S1, to return to SI, or to enter the bus wait state
S4W. The latter transition will be made if another DMA
cycle is ready to start but the BAU has taken the bus
away from the DMAU. In S4W, the DMAU releases the
bus, but is ready to begin as soon as the bus is granted
again and the DMA request is still pending.
NEe
pPD70236 (V53)
Figure 45. DMAU Bus Sta'e Diagram
DMAGT=O
READY =0
DMA incomplete; bus hold mode
(block or demand modes only)
DMA complete; or single mode
DMA incomplete; bus release mode
DMAGT=O
DMAGT= 1
DMARQ= 1
ED
DMAGT=O
DMARQ=O
81
80
81
82
83
84
S4W
8W
Idle state; sample DMA requests.
Wait for BAU to grant bus to DMAU.
Output DMA memory address.
Assert strobes; sample READY, END.
Check READY.
End of DMA cycle; check DMA completion.
Bus wait state; release bus to BAU.
Walt for READY = 1.
83YL·6330B
DMA Read Cycle. The DMAU performs "fly-by" DMA.
During one DMA read bus cycle, .data moves from the
source address in memory to the destination 1/0 device.
The V53 puts the memory address on A23-Ao, and asserts
MRD. At the same time, 10WR is asserted. Memory will
drive the DMA data onto the bus, and the 10WR signal
will latch the data into the 1/0 device. DMAAK should be
used to control chip select at the 1/0 device. Since the
V53 does not use the data, BUFEN is not asserted during
DMA bus cycles.
DMA Write Cycle.The DMAU performs "fly-by" DMA.
During one DMA write bus cycle, data moves from the
source 1/0 device to the destination address in memory.
The V53 puts the memory address on A23-Ao, and asserts
MWR. At the same time, lORD is asserted. The 1/0 device
will drive the DMA data onto the bus; and the MWR
signal will latch the data into memory. DMAAK should be
used to control chip select at the 1/0 device. Since the
V53 does not use the data, BUFEN is not asserted during
DMA bus cycles
Note that when DMA writes are made to DRAM, it may be
necessary to generate a delayed CAS strobe because
the data is being supplied by an 1/0 device that may have
long access time. The write data may not be valid when
the normal CAS signal is asserted.
Dynamic bus sizing cannot be used for DMA operations.
The internal wait state generator and READY can be
used to stretch the cycle.
DMA Cascade. During DMA cascade, the DMA state
machine releases the V53 bus to an external bus master
such as a p.PD71071 or p.PD71037 DMA controller.
DMAAK is connected to the HLDAK input of the external
device. DMAAK will stay asserted until the external
master deasserts DMARQ. If the V53 BAU needs to give
the bus to a higher priority bus master, DMAAK will be
deasserted. The external bus master is expected to then
deassert the DMARQ input, at which point the bus will be
given to the higher priority bus master.
Refresh Unit Bus Cycles
The refresh unit performs memory read cycles from
consecutive memory addresses. These bus cycles are
the same as CPU memory read cycles, except that the
RE FRQ output is asserted. External logic should use the
RE FRQ logic to enable RAS for all memory banks,
regardless of the address decoding scheme, so that all
banks are refreshed.
55
NEe
pPD70236 (V53)
Dynamic bus sizing cannot be used during refresh
operations. The internal wait state generator and
READY can be used to stretch the cycle.
SYSTEM INTERFACE
System Memory Access Time
Table 5 shows the system memory access time required for 12.5-MHz and 16-MHz V53 systems to run
with zero, one, two, and three wait states. This is the
time from when the address bus is valid to when the
external system must present the read data on the data
bus. These numbers are based on the preliminary ac
timing given in this document and are sUbject to
change.
Table 5.
Performance VS. Wait States
12.5 MHz
Memory
Number Cycle
of Wait Time
States (ns)
0
160
2
3
400
System
Access
Time
(ns)
16 MHz
Relative Memory System Relative
Perfor- Cycle
Access Performance
Time
Time
mance
(%)
(%)
(ns)
(ns)
113
78
125
78
100
240
193
64
187.5
140.5
82
320
273
52
250
203
67
353
43
312.5
265.5
56
Note: Performance is relative to the 0 wait state, 16 MHz.
Wait States
Table 5 also illustrates the effect of wait states on
performance. The V53 CPU overlaps bus interface
operations in time with instruction execution. This
greatly reduces the effect of wait states on performance. Each bus cycle is nominally two clocks long,
while the minimum instruction is two clocks with many
instructions taking longer.
There is some idle bus time when the CPU is processing
a long instruction and the prefetch queue is full. Wait
states can often fill these idle states. However, adding
wait states to bus cycles reduces the bus bandwidth
available for other bus masters, such as DMA controllers. This is because some of the idle time that would
have been available to them is used for CPU cycles.
Note that in all cases, a 16-MHz V53 with N+ 1 wait
states is faster than a 12.S-MHz device with N wait
states but slower memory.
Note also that the numbers are. for comparison only.
Different results will be obtained for other program
mixes.
56
Interfacing the #,PD72291 AFPP
The AFPP is a very-high-performance floating-point
coprocessor able to process more than 530K floatingpoint operations per second at 16 MHz.
The AFPP is programmed as an extension of the V53
instruction set. The AFPP executes floating-point operations, computes transcendental functions, and performs vector multiplications.
AFPP instructions use the FP01 and FP02 formats.
When one of these opcodes is encountered and an
AFPP is connected, a coprocessor protocol routine is
entered. The V53 computes any effective addresses
required, reads or writes the operands for the AFPP,
and tells the AFPP which operation should be performed.
The AFPP responds by asserting its BUSY output when
it starts the operation. The V53 will not start another
AFPP operation until BUSY is deasserted, but may
execute CPU instructions. When BUSY is deasserted r
the V53 will transfer the AFPP status to the AW register:
Figure 46 shows how to connect a V53 CPU to a
pPD72291 AFPP. The CPU reads and writes status and
commands to the AFPP using coprocessor read and
write cycles, which always take two clocks. AFPP operands are written using coprocessor memory write/read
cycles, which always require one wait state. The V53
automatically inserts one wait state into these cycles
so no external wait generation logic is required.
On reset, CPBUSY is sampled. If it is high, the V53
assumes that a coprocessor is connected. CPERR is
also sampled to determine what kind of coprocessor is
connected as follows.
CPBUSY
o
1
1
CPERR
x
0
1
Coprocessor Connected
None
pPD72291
Another kind
Note: If no coprocessor will ever be used in the system,
ground pins CPBUSY, CPERR, and CPREQ.
AFPP memory operands must always begin on an even
address and may not reside in 8-bit wide memory.
Dynamic bus sizing may not be used for AFPP operands.
NEe
Figure 46.
pPD70236 (V53)
Connections Between the V53
and pPD72291
Figure 47.
Peripheral Relocation
64K-bytel/0 space
IlPD70236
V53
X1
CPU
332MHZ
X2
16MHZ
ClKOUT
MIlO
IlPD72291
Advanced
Floating·Point
Processor
FFFFH r - - - - - - - - - ,
Reserved
System 1/0 Area
FFOOH
ClK
MIlO
-
-
RIW
RIW
BUSST1
BUSSTO
BUSST1
BUSSTO
DSTB
BCYST
DSTB
BCYST
83YL·6682A
V DD
-CPBUSY
~O--GND
i
--
Table 6. System I/O Area
BUSY
_____________________________
F_ig~u_r_e
Register Name
I/O Address
*
Do-D15
"-
RESET
RESET
*
256-byte area
*
Do -D15
RESET
1
When only the ~PD72291 socket is provided and
the ~PD72291 is not connected, switch CPBUSY to GND.
FFFFH
Reserved
FFFEH
SCTL
48
FFFDH
OPSEL
49
FFFCH
OPHA
50
FFFBH
DULA
50
FFFAH
IULA
50
FFF9H
TULA
50
FFF8H
SULA
50
FFF7H
Reserved
FFF6H
WCY4
FFF5H
WCY3
60
FFF4H
WCY2
59
FFF3H
WMB1
55
FFF2H
RFC
62
FFF1H
SBCR
110
FFFOH
TCKS
51
83YL·6550A
SYSTEM CONTROL I/O
On-Chip Control Registers
The V53 provides many on-chip control registers. Some
of these reside in the 256-byte system I/O area (I/O
space addresses FFOO to FFFF). These are shown in
table 6. Other registers reside in small blocks associated with an on-chip peripheral (addresses are programmable). There are register blocks for DMAU, TCU,
ICU, and SCU. The base addresses for these register
blocks are programmable using the OPHA, DULA,
TULA, and SULA registers in the system I/O area. See
figure 47.
61
F FEFH-F FE EF
Reserved
FFEDH
WAC
56
FFECH
WCYO
57
FFEBH
WCY1
58
FFEAH
WMBO
54
FFE9H
BRC
52
FFE8H
Reserved
FFE7H-FFE2H
Reserved
57
III
NEe
pPD70236 (V53)
TableS. System I/O Area (conI)
Register Name
FFE1H
BADR
FFEOH
BSEL
FFDFH-FF81H
Reserved
XAM (Read Only)
FFBOH
FF7FH-FFOOH
PGR64-PGR1
Note: All registers are Read/Write except XAM.
110 Address
Figure 411. On-Chlp Peripheral Selection
Regl.ter (OPSEL)
IS
ss
TS
7
Figure
102
I
103
SS
0
1
39
39
TS
System Control Register (SCTL)
The SCTL register (figure 48) selects the 8-bit or 16-bit
boundary of an internal peripheral relocation address. It
also sets the internal DMAU in the #,PD71071 or
#,PD71037 modes. In #,PD71037 mode, SCTL controls
propagation of carry from A15 to A16 or from A19 to A20.
SCTL selects the baud rate generator or TOUT as the
SCU clock.
I
I
1 - I sc I CE1
I CEO
IDMAM Ii00G I
0
Address FFFEH
SC
0
1
CE1
0
1
CEO
0
1
DMAM
0
1
10AG
0
1
SCU Input Clock
TOUT1
From baud rate generator
Carry to A20 In "PD71037
Does not propagate
Propagates
Carry to A16 In "PD71037
Does not propagate
Propagates
DMAU Mode
"PD71071
"PD71037
Internal 1/0 Address
Even or odd (16-bit boundary)
Contiguous (a-bit boundary)
On-Chip Peripheral Selection Register (OPSEL)
The OPSEL registers (figure 49) controls the V53 internal
peripherals. Any of the four peripherals (DMAU, TCU,
leU, or SCU) can be independently enabled or disabled
by setting the appropriate OPSEL bit.
58
I
I
I
OS
I
0
SCU Operation
Disabled
Enabled
TCU Operation
Disabled
Enabled
ICU Operation
Disabled
Enabled
DMAU Operation
Disabled
Enabled
Internal Peripheral Relocation Registers
Figure 48. System Control Regl.ter (SCTLJ
7
0
1
IS
0
1
DS
0
1
I
The five internal peripheral registers fix the I/O addresses of the DMAU, leU, TCU, and SCU. Register
OPHA fixes the high-order byte of the 16-bit I/O addresses. Registers DULA, IULA, TULA, and SULA select
the .Iow-order byte of the I/O addresses for the DMAU,
leU, TCU, and SCU peripherals, respectively.
The formats ofthe individual internal peripheral registers
are shown in figure 50. Since address checking is not
performed, two peripheral I/O address spaces should
not be overlapped.
NEe
pPD70236 (V53)
Figure 50. Internal Peripheral Relocation
Registers
OPHA Register
I A15 I A14 I A13 I A12 I A11 I A10 I Ag
7
A8
I/O Address FFFCH
0
DULA Register
10AG = x*
10AG = 0 #
A7
Ae
A5
I A7
Ae
A5
I~ I
I
Timer Clock Selection Register (TCKS)
Ao
o
7
I/O Address FFFBH
* J.IPD71071 mode
# J.IPD71037 mode
IULA Register
10AG = 0
A7
7
The IOAG bit of the SCTL register changes how the
DULA, IULA, TULA, and SULA registers are used. When
IOAG = 1, the DAMU, ICU, TCU, and SCU registers are
on contiguous bytes. When IOAG = 0, each of these
byte-wide registers is put on a word boundary. Bit Ao
selects the low or high byte of the word. This allows code
written for a 16-bit system to be ported to a V53 design
with no modifications. Because the DMAU registers in
JlPD71071 mode are 16-bit, the IOAG bit in figure 50 is
noted as "x" (don't care).
Ae
A5
~
A3
Ao
o
I/O Address F F FAH
The TCKS register (figure 51) selects the clock source for
the timer/counters as well as the divisor for the internal
clock prescaler. The clock source for each timer/counter
is independently selected from an internal clock (figure
43) or an external clock source (TCLK).
The frequency of the internal clock selected by bits 2, 3,
and 4 is programmable. The PS bits allow the clock to be
set to the external osci Ilator frequency divided by 4, 8,
16, or 32.
TULA Register
Figure 51.
10AG = 1
I- I
7
o
I/O Address FFF9H
CS2
0
S ULA Register
10AG ='1
CS1
10AG = 0
0
1
Ao
7
I/O Address FFF8H
o
I - I CS2 I CS1 I CSO I
PS
I/O Address FFFOH
7
Ao
10AG = 0
Timer Clock Selection Register (TCKS)
CSO
0
1
PS
00
01
10
11
I
0
Clock Input to TCT2
Internal clock
TCLK pin
Clock Input to TCT1
Internal clock
TCLK pin
Clock Input to TCTO
Internal
TCLK pin
Prescale Divisor of External Oscillator
4
8
16
32
59
III
NEe
IIPD70236 (V53)
Baud Rate Counter (BRC)
Figure 53•. Memory Spsce Division
The BRC. (figure 52) is an a-bit, frequency-division
counter for the dedicated baud rate generator. It sets the
value by which an internal frequency is to be divided to
provide the SCU with its baud rate clock.
16M
Bytes
Figure 52. Bsud Rsl. Counler(BRC)
Do
7
I
o
I/O Address FFE9H
Table 7 illustrates the relationship between the .baud
rate and the value set in the BRC.
rsbl.7. Bsud Rsle Setting by BRC
Oscillation frequency
24.576 MHz
29.4912 MHz
Oscillation frequency + 2
12.288 MHz
14.7456 MHz
Baud rate factor (+)
16
64
16
64
Internal frequency
0.768
0.192
0.9216
0.2304
Baud Rate
Number of Counts Set In BRC
1200
160
192
2400
80
96
4800
160
40
192
48
9600
80
20
96
24
,
Low
83YL·6547A
The WCU can insert waits into memory or external I/O
cycles, but not into coprocessor, internal I/O, or halt
acknowledge cycles.
Eight system I/O registers (figures 54-61) control the
WCU. They are the wait state memory boundary registers (WMBO and WMB1), the WCU address control register (WAC), and the wait state cycle count registers
(WCYO-WCY4).
Memory Boundary Registers (WMBO, WMB1)
WAIT CONTROL UNIT
The WMBO register divides the entire .16M-byte address
space into three sections. The EL MB and EUMB fields
specify the size of the upper and lower memory blocks.
The middle block is the area left in between. The WCYO
and WCY1 registers specify the wait states of each
expanded memory block.
The wait control unit (WCU) inserts from 0 to 7 wait
states (TW) into a bus cycle to· compensate for the
varying access times of different memory and I/O devices. Each wait state is equivalent to one CPU clock
cycle. rhe number· of wait states can be individually
programmed for CPU, DMAU, RE FU, INTAK, and externall/O cycles. The INTAK cycles can be programmed for
2-7 wait states.
In addition to dividing expanded memory, a specific
1M-byte memory area can also be partitioned into three
blocks for wait state generation. rhe WAC register determines which 1M-byte area is referenced. The WMB1
register divides this area into three blocks in the same
manner as described above for WMBO. Registers WCY2
and WCY3 specify the wait states for each block and
also I/O.
19,200
40
10
48
12
38,400
20
5
24
6
For memory accesses, the address space is divided into
a total of six sections (labeled High, Middle, and Low in
figure 53). A different number of wait states can be
programmed for each section, allowing much flexibility
in the system design. The WCU works with the external
READY input. After the proper number of rws have been
inserted into the bus cycle, READY will be sampled, and
wait states will be inserted until it is asserted.
60
NEe
,.,PD70236 (V53)
Figure 54. Memory Boundary Register 0 (WMBO)
I- I
I- I
ELMS
7
EUMS
I/O Address FFEAH
I
0
After RESET, the WCY registers are set to all 1s, thereby
inserting seven waits into all cycles. This allows the use
of slow ROMs. Initialization code must set the WCY
registers to their values.
Memory Block Size (Bytes)
ELMB/EUMB
000
001
010
011
1M
2M
3M
4M
100
101
110
111
5M
6M
Figure 57.
WCYO Register
I- I
I- I- I- I
7
I- I
I- I
LMS
7
UMS
I/O Address FFF3H
0
100
101
110
111
64K
Figure 58.
96K
128K
192K
256K
7
512K
WCU Address Control Register (MC)
I
I
I
WCY1 Register
I
I/O Address FFEDH
UWA
I
0
UWA '" Upper 4 bits of expanded address specifying a 1M-byte
memory space
Wait State Cycle Count Registers eyiCYO-WCY4)
Each WCY register has one or two 3-bit fields that set the
number of waits for a particular kind of cycle or the
number of waits to be inserted into cycles during which
certain memory blocks are accessed.
(1) WCYO and WCY1 (figures 57 and 58) pertain to the
16M-byte memory space set by the WMBO register.
(2) WCY2 and WCY3 (figures 59 and 60) pertain to the
1M-byte memory space set by the WMB1 register.
(3) Also, the lOW field of WCY3 sets the numberof waits
for external I/O cycles and interrupt acknowledge
cycles.
I- I
EMMW
ELMW
o
I/O Address FFEBH
EMMW/ELMW
384K
I
6
7
I- I
Figure 56.
7
4
5
* Upper section of 16M-byte memory space
32K
000
001
010
011
3
100
101
110
111
I
Memory Block Size (Bytes)
LMB/UMB
0
1
2
000
001
010
011
Figure 55. Memory Boundary Register 1 (WMB1)
o
·Walt States
EUMW
7M
8M
EUMW
I/O Address FFECH
·Walt States
000
001
010
011
0
1
2
3
100
101
110
111
4
5
* Middle and
Figure 59.
I- I
6
7
lower sections of 16M-byte memory space
WCY2 Register
I- I
MMW
LMW
I/O Address FFF 4H
7
MMW/LMW
000
001
010
011
100
101
110
111
* Middle and
o
·Walt States
0
1
2
3
4
5
6
7
lower sections of 1M-byte memory space
(4) The waits set by WCY3 cannot be inserted into the
internal I/O area read/write cycle.
(5) WCY4 (figure 61) sets the number of waits for DMA
cycles and refresh cycles.
61
t\'EC
,.,PD70236 (V53)
Figure flO. WCY3 Register
I
I
I- I
lOW
7
UMW
o
I/O Address FFF5H
Walt State.
lOW
000
001
010
011
100
101
110
111
UMW
000
001
010
011
100
101
110
111
Ext 1/0 Cycle.
Int Ack Cycle.
0
1
2
3
2
3
2
3
4
5
4
5
6
6
7
7
I- I
7
Refresh interval = 16 x N x tcyc
*Walt State.
With a 16-MHz CPU clock, this allows a range of intervals
from 1 to 32 p,s. After RESET, N will be 9, which gives an
interval of 9 p,s.
0
1
2
3
Since the V53 may operate with either 8- or 16-bit
memory devices, the refresh address can be incremented by 1 (for 8-bit memory) or by 2 (for 16-bit
memory). The ROB8 bit in the RFC makes the selection.
In the word mode, UBE is always low (active) for refresh
cycles. In the byte mode, UBE is asserted only for
refreshes to an odd address.
4
5
6
7
WCY4 Register
I - I
DMAW
I/O Address FFF6H
DMAW/RFW
000
001
010
011
100
101
110
111
Refresh Control Register (RFC)
The RFC (figure 62) controls the refresh control unit. The
RE bit enables or disables the REFU. The refresh interval
is set by the RTM field by choosing refresh interval factor
N, which determines how many CPU clock cycles elapse
between refreshes.
* Upper section of 1M-byte memory space
Figure 61.
REFU is given the highest bus priority. .The REFU gets
control of the bus, performs a burst of four refreshes,
and then falls back to the lowest priority. This refresh
queue ensures that refresh cycles are not lost even when
the V53 is busy for long periods of time.
RFW
o
*Walt State.
0
1
2
3
Figure 62. Refresh Control Register (RFC)
I RE IROBS I
I
7
I/O Address FFF2H
RE
o
1
4
5
ROBS
6
7
1
o
* DMA cycle or refresh cycle.
RTM
RE FRESH CONTROL UNIT
RTM
I
0
Refre.h
Disable
Enable
lCU Clock for Channel 2
Increment by 2 ((J'i3E = low leveO
Increment by 1 ((J'i3E = high level for even addresses
and low level for odd-addresses)
Refre.h Interval Factor N
00000
00001
00010
00011
00100
1
3
11110
11111
31
32
2
The refresh control unit (REFU) refreshes external dynamic devices by periodically performing a memory
read cycle from consecutive, incrementing addresses. A
16-bit counter provides the refresh address. The upper
bits (A23-A16) are low during refreshes. Each refresh bus
cycle has two wait states inser:ted, so that it will be a
minimum of 4 clocks long. Refresh cycles can be distinguished from other memory reads by the assertion of the
REFRQ output or by the bus status code.
TIMER/COUNTER UNIT
If the V53 is busy when it is time to perform a refresh, the
refresh request is placed in a refresh queue until the bus
is no longer busy. Normally, the RE FU has the lowest bus
priority. However, after seven refreshes are queued, the
The timer/counter unit (TCU) provides a set of three
independent 16-bit timer/counters. Each timer has an
individual output and gate control input. The clock
source for each channel is set individually to either the
62
4
5
NEe
JlPD70236 (V53)
prescaled CPu clock or the external TCLK. TOUn is
also internally connected to supply the baud rate clock
to the SCU. Figure 63 is the TCU block diagram.
The TCU has the following features.
• Three 16-bit timer/counters
• Six programmable count modes
•
•
•
•
•
•
Binary/BCD counting
Multiple latch command
Count latch command
Choice of two clock sources
16-MHz operation
Functionally compatible with "PD71054 {8254}
Figure 63.
Because RESET leaves the TCU in an uninitialized state,
each timer/counter must be initialized by specifying an
operating mode and a count. Once programmed, a
timer/counter will continue to operate in that mode until
another mode is selected. When the count has been
written to the counter and transferred to the down
counter, a new count operation starts. Both the current
count and the counter status can be read while count
operations are in progress. Figure 64 is a flow diagram
for TCU operations.
1CU Block Dillgrsm
TCLK
(External)
Clock
TCTLO
(External)
TCTL1
(External)
TOUT1
(External)
TOUTO
(External)
Internal Signal
III
TCTL2
(External)
TOUT2
(External)
r-------~~------,
__
lORD IOWR
AD
(A 1)
A1
(A2)
TUS
j j j j j
TCTO
r--- - ------------- ------- --------
ReadlWrite Control
Status
Register
TCT1
TMD
(Mode Register)
Status
Latch
TCT2
Count
Latch
'---______-+__---j (8) 1--------1 (8) f--------j (8) f-----------~-;
Internal Data Bus
83YL-6218B
63
NEe
IIPD70236 (V53)
Figure 64. TCU Operating Procedure
more timer/counters. Figures 65, 66, and 67 show three
configurations of the TMD register.
Figure 65. TMD Regl.ter; "ode IIbnt
_
OUT
I
Instruction
7
SC
_
Instruction
I
o
Oounter latch command
Lower byte only
Upper byte only
Lower byte followed by upper byte
11
OUT
BD
Read/Wrlte Mode
00
01
10
_
OMODE
TOTO
TCT1
TCT2
Multiple latch command
11
RWM
I
RNM
Counter
00
01
10
OUT
I
so
CMODE Count Mode
Instruction
_IN
Instruction
000
001
x10
Mode 0
Mode 1
Mode 2
x11
100
101
Mode 3
Mode 4
Mode 5
BD
Count
o
Binary count
BOD count
1
x
= Don't care.
Figure 66. TMD Regl.ter; Count Latch Command
83YL-SS12A
I
I
SO
0
I
0
I
0
I
0
I
0
I
0
7
TCU Commands
SC
The TeU is programmed by issuing I/O instructions to
the I/O port addresses programmed in the OPHA and
TULA registers. The individual TeU registers are selected by address bits A2 and A1 or (Ad and (Ao) as
follows.
A2 (A1)
A1 (Ao)
0
0
0
0
Register
TCTO
TSTO
Operation
TCT1
TST1
Read/write
Read
Read/write
Read
Write
TCT2
TST2
TMD
Read/write
Read
Timer Mode Register (TMD)
The TMD register selects the operating mode for each
timer/counter and issues the latch command for one or
64
I
0
00
01
10
Oounter To Be Latched
TOTO
TOT1
TOT2
Figure 67. TMD Regi.terj "ultiple Latch
Command
I
I eL I
SL
7
OL
o
1
SL
o
1
eTn
o
1
Latches Count Data
Yes
No
Latches Status
Yes
No
Selects Counter TCTn
No
Yes
CT2
CT1
CTO
o
o
NEe
pPD70236 (V53)
Timer/Counter Registers (TCT)
Count· Modes
Writes to the timer/counter registers (TCTO-TCT2) stores
the new count in the appropriate timer/counter. The
count latch command is used before reading count data
to latch the current count and prevent inaccuracies.
There are six programmable timer/counter modes. The
timing waveforms for these modes are shown in figure
69.
Timer Status Registers (TST)
The timer status registers (T5TO-T5T2) contain status
information for the specified counter. See figure 68. The
latch command is used to latch the appropriate counter
status before reading status information. If both status
and counter data are latched for a counter, the first read
operation returns the status data and subsequent read
operations obtain the count data.
Figure 68.
Timer St.tus Registers (TS Tn)
I OL I NC I
RNM
I
7
CMODE
I SD I
0
OL
0
1
NC
0
1
RWM
TOUTn Level
Low
High
Null Count
Valid
Invalid
Mode 0 (Interrupt on End of Count). In mode 0, TOUT
changes from low to high level when the specified count
is reached. This mode is available on all timer/counters.
Mode 1 (Retrlggerable One-Shot). In mode 1, a lowlevel, one-shot pulse triggered by TCTl is output from the
TOUT pin.
Mode 2 (Rate Generator). In mode 2, TOUT cyclically
goes low for one clock period when the counter reaches
the 0001 H count. A counter in this mode operates as a
frequency divider.
Mode 3 (Square-Wave Generator). Mode 3 is a f r e - I I I
quency divider similar to mode 2, but the output has a
symmetrical duty cycle.
Mode 4 (Software-Triggered Strobe). In mode 4, when
the specified count is reached, TOUT goes low for the
duration of one clock pulse.
Mode 5 (Hardware-Triggered Strobe). Mode 5 is similar to mode 4 except that operation is triggered by the
TCTl input and can be retriggered.
Read/Wrlte Mode
Same as TMD register.
CMOOE Count Mode
Same as TMD register.
BO
Count
Same as TMD register.
65
NEe
"P070236 .(V53)
Figure 69.
Timer Counter Unit (1CU) Waveforms (Sheet 1 of 3)
ModeO
ClK
IOWR
TOUT
Count Value
IOWR
~
TOUT
Count Value
IOWR
~
LJ
TCTL2
TOUT2
Count Value
OOOOH
IFFFFH IFFFEH IFFFDH IFFFCH
Mode1
TCTl2
---------1 t1---------------\ t1--------------\ t1------\ t1----------
TOUT2
Count Value
n
I
n-1
LJ
IOWR~
TCTl2
I n-2
- - - - - - - - \
Il----------------\ Il---------------------
TOUT2
Count Value
n
I
n-1
I n-2
83-001851 B
66
NEe
Figure 69.
pPD70236 (V53)
Timer Counter Unit (IClJ)
_reforms (Sheet 2 of 3)
Mode 2
ClK
LJ
TCTL
TOUT
Count
Value
--\::j
IOWR
TOUT
Count
Value
n-1
I 0006H I 0005H I 0004H I 0003H I 0002H
III
Mode 3
ClK
IOWR
l
lB=4
LJ
TCTL
U
TOUT
Count
Value
IOWR
n
1
n-1
0004H
0002H
0004H
I
0002H
0004H
I
0002H
I
0004H
0004H
0004H
lB=5
L
TOUT
Count
Value
I
n-1
0004H
I
0002H
I
OOOOH
0004H
I
0002H
0004H
0002H
I
0004H
OOOOH
I
83-0018536
67
NEe
pPD70236 (V53)
Figure till.
Timer Counter Unit (TCU) IItIvelorms(Sheet 3013)
Mode 4
TOUT
Count Value
n-1
I
0004H
I
0003H
I
0002H
I
0001H
I
n-1
I
0004H
I
0004H
I
0004H
I
0003H
I
0002H
I
0001H
n-1
I
0005H
I
0004H
I
0003H
I
0002H
I
0003H
I
0002H
OOOOH
I
I
FFFFH FFFEH FFFDH FFFCH
TCTl
TOUT
Count Value
IOWR
n
--, LB=5,
L....J
TOUT
n
I
I
0001H
OOOOH
FFFFH
ModeS
TCTL2 -- - - - - - - - - - - - -;
TOUT2
Count Value
n
I
n-1
TCTl2 - - - - - - - - -;
TOUT2
Count Value
n
I
I
n-2
n----------------1 n------l n -----I
n-3
I
0002H
I
0001 H'
n---------------- --------l n----------
n-1
~
I
0004H
I
0003H
I
0002H
I
0001 H
L.JI
I
OOOOH
I
FFFFH FFFEH
I
0003H
I
0002H
83-001855B
68
NEe
"PD70236 (V53)
SERIAL CONTROL UNIT
The serial control unit (SCU) is a single asynchronous
channel that performs serial communication between
the V53 and an external device. The SCU is similar to the
~PD71051 Serial Control Unit except for the lack of
synchronous communication protocols. Figure 70 is a
block diagram of the SCU.
Figure 70. SCU Block DllIIJram
Reset
Clock
ReadlWrite
Control
SST
(Status Register)
...----
:~:~}
/ + - - - - A1(A2)
Internal Signals
. . . - - - - AO(A1)
SUS
SCM
(Command Register)
SRB
(Receive Data Buffer)
III
RTCLK (From TOUT1)
Receiver
(Including
RxRDY (External)
I./'--....,."...-----i Receiver Buffer) "'--+---0 RxD (External)
STB
(Transmit Data Buffer)
TxD (External)
SMD
(Mode Register)
SIMK
(Interrupt Mask Register)
SINT (External)
CTS (External)
Transmissionl
Reception
Control
RTS (External)
t---_oO DTR (External)
DST (External)
83YL-6219B
The SCU has the following features.
• Full-duplex, asynchronous serial controller
• Clock rate divisor: 16 or 64
• Baud rates to 640 kb/s (external clock), 500 kb/s
(internal clock)
• Dedicated baud-rate generator or can use timer 1
• Full modem signaling support (ATS, CTS, DSR, DTR)
• Character length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Break transmission and detection
• Full-duplex, double-buffered transmitter/receiver
• Even, odd, or no parity
• Parity, overrun, and framing error detection
• Receiver-full/transmitter-empty interrupt
The SCU contains four separately addressable registers
for reading/writing data, reading status, and controlling
operation Qfthe SCU. The serial receive buffer (SRB) and
the serial transmit buffer (STB) store the incoming and
outgoing character data. The serial status register (SST)
allows software to. determine the current state of both
the transmitter and the receiver:
The serial command (SCM) and serial mode registers
(SMD) determine the operating mode of the SCU while
the serial interrupt mask register (SIMI<) allows software
control of the SCU receive and transmit interrupts.
Serial Data Format
Figure 71 shows the format of the serial data processed
by the SCU. In this serial data, the character bits are
69
NEe
pPD70236 (V53)
transferred between the cpu· and SCU. The start bit,
parity bit, and stop bit(s) sandwiching the character bits
are control information necessary for serial data communications. They are automatically appended when
data is transmitted or deleted when data is received by
the SCU.
No Parity
On-1
c+{~te~ bitS:
On
>
__ _
Is~rr=
SCU Registers and Commands
A2 (A1)
Parity
0
0
0
0
A1 (Ao)
-0-0
1
1
0
n = 6or7
Stop bit = 1 or 2 bits
83YL-6514A
Receiver Operation
While the RxD pin is high, the receiver is in an idle state.
A transition on RxD from high to low indicates the start
of new serial data. When a complete character has been
received, it is transferred to the SRB register. The receive
buffer ready (RBRDY) bit in the SST register is set and (if
unmasked) an interrupt is generated. The SST also
latches any parity, overrun, or framing errors at this time.
The receiver detects a break condition when a null
character with zero parity is received. The BRK bit is set
for as long as the subsequent receive data is low and
resets when RxD returns to a high level.
Transmitter Operation
TxD is kept high while the STB register is empty. When
the transmitter is enabled and a character is written to
the STS register, the data is converted to serial format
and output on the TxD pin. The start bit indicates the
start oft he transmission and is followed by the character
stream (LSB to MSB) and an optional parity bit. One or
two stop bits are then appended, depending on the
programmed mode. When the character has been transferred from the STB, the TBRDY bit in the SST is set and
if unmasked, a transmit buffer empty interrupt is generated.
Serial data can be transmitted and received by polling
the SST register and checking the TBRDY or RBRDY
fl~gs. Data can· also be transmitted and received by
SCU-:generated interrupts. The SCU generates an interrupt in either of these conditions:
70
interrupts are unmasked.
(2) The transmitter is enabled, the STB is empty, and
transmit interrupts are unmasked.
I/O instructions to the I/O addresses selected by the
OPHA and SULA registers are used to read/write the
SCU registers. Address bits A2 and A1 (or A1 and Ao) and
the read/write lines select one of the six internal registers
as shown below.
Figure 71. Serial Data Format
01
(1) The receiver is enabled, the SRB is full, and receive
1
Register
srurSTB
SST
SCM
SMD
SIMK
Operation
Read
Write
Read
Write
Write
Read/write
The baud rate counter (BRC) register is fixed at address
FFE9H in the system I/O area.
The SRB and STB are a-bit registers. When the character
length is 7 bits, the lower 7 bits of the SRB register are
valid and bit 7 is cleared to o. If programmed for 7-bit
characters, bit 7 of the STB is ignored.
The SST register (figure 72) contains the status of the
transmit and receive data buffers and the error flags.
Error flags are persistent. Once an error flag is set, it
remains set until a clear error flags command is issued.
SCU Initialization
After a hardware reset, the SCU is set to the following
condition.
Baud rate factor
Character length
Stop bit
Transmit/receive
Break detection
Errors
RTS, DTR pins
x64
7 bits
1 bit
Disabled
No
No
High level
NEe
pPD70236 (V53)
Figure 73. Serial Comlllllnd Regisler (SCII)
Figure 72. Serial Stalus Reglsler (SS T)
I
DSR
I
BKD
I
FE
lOVE
I
7
PE
I
I RBRDVI TBROVI
I
0
7
-
I)S1Ilnput Pin
RTS
0
1
High level
Low level
0
1
0
1
FE
0
1
OVE
0
1
PE
0
1
Break Detection
Framing Error
Overrun Error
TBRD'f
0
1
I
High level
Low level
Clears Error Flags
No operation
Clears error flags
SBRK
Break Transml .. lon
TxD pin operates normally
TxD pin outputs low level
0
1
RE
No error
Error
0
1
Parity Error
DTR
No error
Error
0
1
TE
SRB empty
SRB full
TE
Controls RTS Output Pin
0
1
No error
Error
RBRD'f Receive Data Buffer
0
1
ECL
Normal reception
Break status detected
I
0
DSR
BKD
I - I RTS I ECL ISBRK I RE I DTR
Enables/DI ..bles Reception
Disables
Enables
Controls D'i"R Pin
High level
Low level
enables/Disables Transmission
Disables
Enables
0
1
Transmit Data Buffer
STBfull
STB empty
The SCM register (figure 73) stores the command word
that controls transmission, reception, error flag reset
and break transmission.
The SMD register (figure 74) stores the mode word that
determines serial characteristics such as baud rate divisor, parity, character length, and stop bit length.
Initialization software should first program the SMD
register followed by the SCM register. Unlike the
~PD71051, the SMD register can be modified anytime
without resetting the SCU.
Figure 74. Seriaillode Reglsler (SliD)
I
STL
I
PS
7
I
CL
I
BF
I
0
STL
xO
01
11
PS
xO
01
11
CL
xO
10
11
BF
Ox
10
11
Number of Stop Bits
Illegal
1 stop bit
2 stop bits
Parity Selection
Parity disabled
Odd parity
Even parity
Character Length
Illegal
7 bits
8 bits
Baud Rate
Illegal
RTCLK frequency/16
RTCLK frequency 64
The SIMK register (figure 75) controls the occurrence of
RBRDY and TBRDY interrupts. When an interrupt is
masked, it is prevented from propagating to the interrupt
control unit.
71
NEe
pPD70236 (V53)
Figure 75. Serial Interrupt lIasle Register (SIIIK)
I- I- I- I- I
I
7
I TM I RMI
0
TM
TBRDY Interrupt Mask
INTERRUPT CONTROL UNIT
Unmasked
Masked
0
1
RM
internal baud rate generator is discussed in the System
I/O section, and timer 1 is described in the TCU section.
The SCTL system I/O register controls the selection of
the baud rate clock.
RBRDY Interrupt Mask
Unmasked
Masked
0
1
Baud Rate Clock
The baud rate clock may come from either of two
sources: the internal baud rate generator or timer 1. The
The interrupt control unit (ICU) is a programmable interrupt controller equivalent to the p.PD71059. The ICU
arbitrates up to eight interrupt inputs, generates a CPU
interrupt request, and outputs the interrupt vector number on the internal data bus during an interrupt acknowledge cycle. Cascading up to seven external slave
p.PD71059 interrupt controllers permits the V53 to support up to 56 interrupt sources. Figure 76 is the block
diagram for the ICU.
Figure 76. ICU Block Diagram
~~~
lORD
IOWR
A1{A2)
In.ternal
Signals
(
}
To BIU -+-
SA2
{= ~~
-..0
A2
(External Signals)
ReadlWrite
Control
AO{A1)
IUS
INTLO
INTL1
INTL2
INTL3
INTL4
INTL5
INTL6
INTL7
INTPO
INTP1
INTP2
INTP3
INTP4
External
Pins
INTP5
INTP6
INTP7
83YL·6220B
To reduce current drain in the standby modes, the V53
does not have internal pullup resistors on the INTPOINTP7 pins. This is different from the p.PD71059 and
V40N50.
The ICU has the following features.
• Eight external interrupt request inputs
• Cascadable with p.PD71059 interrupt controllers
• Programmable edge- or level-triggered interrupts
(TeU, edge-triggered only)
• Individually maskable interrupt requests
• Programmable interrupt request priority
• Polling mode
72
ICU Registers
Use I/O instructions to the I/O addresses selected by the
OPHA and IULA registers to read from a,nd write to the
ICU registers. Address bit A1 and the command word
select an ICU internal register. See table 7.
1ttlEC
pPD70236 (V53)
Table 7. ICU Register Selection
Figure 77. InitialiZlltion Sequence
A1 (Ao)
Other Condition
Operation
Read
0
0
0
IMO selects IRQ
IMO selects liS
*Polllng phase
CPU - IRQ data
CPU -liS data
CPU - Polling data
Write
0
0
0
04 = 1
04 =0 and 03 = 0
04 = and 03 = 1
CPU -IIW1
CPU -IPFW
CPU-IMOW
During Initialization
CPU-IIW2
CPU -IIW3
CPU -IIW4
After initialization
CPU-IMKW
Bits SNGL and 114 are set.
The default initialization
is performed.
CPU -IMKW
o
114= 1
114= 0
* In the poliing phase, polling data has priority over the contents of
the IRQ or liS register when read.
Initializing the
leu
The ICU is always used to service maskable interrupts in
a V53 system. Prior to accepting maskable interrupts,
the ICU must first be initialized. See figure 77. Note that
RESET does not initialize the ICU.
Interrupt Initialization Words 1-4. W:>rds IIW1-IIW4
(figures 78-81) indicate whether external p.P071059s are
connected as slaves, select the base interrupt vector,
and select edge- or level-triggered inputs for INT1-INT7.
Interrupt sources from the TCU are fixed as edgetriggering. INTO is internally connected to TOUTO, and
INT2 may be connected to TOUT1 by the IRSW field in
the OPCN.
The initialization words are written in consecutive order
starting with IIW1. IIW2 sets the interrupt vector. IIW3
specifies which interrupts are connected to slaves. IIW3
is only required in extended systems. The ICU will only
expect to receive IIW3 if SNGL = 0 (bit 01 of IIW1). IIW4
is only written if 114 = 1 (bit Do of IIW1).
Figure 78. ICU Initialize, IIbnl1 (IIW1)
I- I- I- I
I LEV I
ISNGL I
07
LEV
Input Trigger Mode
Rising-edge trigger
High-level trigger
1
Mode
o
Expanded mode (slave controllers)
Single mode (no slave controllers)
1
114
I
DO
o
SNGL
114
Write to W4
o
IiW4 not required
IiW4 required
1
Figure 79. ICU Initialize, IIbnl2 (l1W2)
I~ I
07
V7-V3
~
I
~
I
~
I
~
I- I
= Higher 5 bits of Interrupt vector number
DO
73
NEe
IIPD70236 (V53)
Figure 80.
Figure 83. Command Word IPFW
ICU Initialize, Word 3 (IIW3)
I
o
07
DO
Slave Connection
o
RP
SIL
Figure 81.
I
0
I
0
ICU Initialize, Word 4 (IIW4)
I
0
I
EXTN
I
I
I
o
SFI
o
1
FI
FI command mode
Self-finish mode
Command Words. The interrupt mask word (MKW)
contains programmable mask bits for each of the eight
interrupt inputs. The interrupt priority and finish word
(IPFW) is used by the interrupt handler to terminate
processing of an interrupt or change interrupt priorities.
The interrupt mode word (IMDW) selects the polling
register, interrupt request (IRQ) or interrupt in-service
(liS) register, and the nesting mode. See figures 82-84.
Command Word IMKW
o
1
Interrupt Request Mask
INTn not masked
INTn masked
IL1
ILO
Interrupt Level
INTO
INT1
INT2
011
100
101
INT3
INT4
INT5
110
111
INT6
INT7
Figure 84.
Command Word IMOW
I - I SNM IEXCN I
0
I
I POL
SR
EXCN
0
Mo
Nesting Mode 2
No operation
Release exceptional nesting mode
Set exceptional nesting mode.
Polling Mode
0
SR
IS/IR
DO
07
POL
Mn
IL2
Non-FI command
FI command
DO
D7
I
Not specified
Specified
0
M1
0
Level
000
001
010
SNM
Figure 82.
I
Finish Interrupt
I L2-1 LO
Self-Finish Interrupt
0
No rotation
Rotation'
1
Normal
Expanded
I
Rotate Priority
o
External Nesting Mode
FI
DO
SFI
DO
I
SIL
o
07
EXTN
I
o
INTn is not a slave input
INTn is a slave input
1
RP
07
No operation
Polling command
IStlR
0
0
1
Register to Be Read
No operation
Interrupt request register (IRQ)
Interrupt in-service register (liS)
I'PD71059 Cascade Connection
To increase the number of maskable interrupts, up to
seven slave JlPD71059 interrupt controllers can be
cascaded. During cascade operation, each slave
JlPD71059 INT output is routed to one of the V53 INTP
inputs.
During the second interrupt acknowledge bus cycle,
the leu places the slave address on the address lines
Ao-A2' Each slave compares this address with the slave
address programmed using interrupt initialization
word 3 (IIW3). If the same, the slave will place the
interrupt vector on pins 00-07 during the second interrupt acknowledge bus cycle.
74
1ttfEC
"PD70236 (V53)
DMA CONTROL UNIT
The DMA control unit (DMAU) is a high-speed DMA
controller compatible with the "PD71071 and "PD71037
DMA controllers. The DMAU has four independent DMA
channels and performs high-speed data transfers between memory and external peripheral devices at
speeds as high as 4M words/second in a 16-MHz system.
Figure 85 is the block diagram for the DMAU.
The DMAU has the following features.
• Four independent DMA channels
•
•
•
•
•
•
•
•
•
•
"PD71037 or "PD71071 compatibility modes
Cascade mode for slave DMA controllers
24-bit address registers
16-bit transfer count registers
Single, demand, and block transfer modes
Autoinitialization
Address increment/decrement
Fixed/rotating channel priorities
TC output at transfer end
Forced termination of service by END input
Figure 85. DMAU Block DlllIIram
DMAU Address Bus
Internal Address Bus
Internal Control Bus
Address
Incrementerl
Decrementer
(24)
Control Registers
Internal Bus
Interface
Address
Register
Base Address (24 x 4)
BUSRQ
BAU
{
Channel (4)
Device Control (10)
BUSAK
Status (8)
Mode Control (7 x 4)
Base Count(16 x 4)
Count
Register
Mask (4)
Current Count (16 x 4)
DMARQ3-DMARQO
External
DMAAK3-DMAAKO
Priority
Control
PinS
{
Terminal Count
ENDtTc
83YL·6221B
"PD71071·and "PD71037 Mode Comparison
The DMAU has two operating modes selected by the
SCTL system control register. Respectively, the
"PD71071 and "PD71037 modes offer hardware and
software compatibility. with existing systems based on
the "PD71071 DMA controller (also the V40N50 microprocessor) and the "PD8237 DMA controller.
In applications where DMA software compatibility is not
an issue, programming flexibility is greater in the
"PD71071 mode. However, the software DMA request
capability of the "PD71037 mode is often useful.
The following compares the major functional differences
between the two modes.
75
NEe
"PD70236 (V53)
Function
DMA channel
selection
Base and
current register
access
Base registers
DMA
termination
Software DMA
requests
DMA transfers
"PD71037
Mode
Mode control
register by
write data
(operand);
other registers
have a unique
address
Consecutive
8-bit quantities
"PD71071 Mode
Write only
Bus release
mode
Read and write
Bus release and
bus hold modes
Yes
No
Byte
Byte or word
Referenced by
channel register
(DCH)
DMA Transfer Type
The type of transfer the DMAU performs depends on the
following conditions.
16-bit quantities
The DMAU is intended for high-speed data transfers
between memory and peripherals with minimum latency.
Neither mode provides memory-to-memory DMA transfers because the powerful string moves of the CPU can
accomplish block memory transfers as fast as dedicated
DMA hardware could. The DMAU does not provide compressed timing as do the "PD71071 and "PD71037.
Master/Slave Mode
The DMAU operates in either master or slave mode. In
slave mode, the DMAU samples the four DMARQ input
pins every clock. If one or more inputs are active, the
corresponding DMA request bits are set and the DMAU
sends a bus request to the BAU while continuing to
sample the DMA request inputs.
After the BAU returns the DMA bus acknowledge signal,
the DMAU stops DMA request sampling, selects the DMA
channel with the highest priority, and enters the bus
master mode to perform the DMA transfer: While in the
bus master mode, the DMAU controls the external bus
and performs DMA transfers based on the preprogrammed channel information.
See figure 45 and the associated text for a detailed
description of DMA bus cycles.
Terminal Count
The DMAU ends DMA service when the terminal count
condition is generated or when the END input is asserted. A terminal count (TC) is produced when the
contents of the current count register underflows from
zero. If autoinitialization is not enabled when DMA service terminates, the mask bit of the channel is set and
76
the DMARQ input of that channel is masked. Otherwise,
the current count and address registers are reloaded
from the base registers, and new DMA transfers are again
enabled.
• Transfer direction (each channel)
• Bus mode
• Transfer mode (each channel)
Transfer Direction
All DMA transfers use memory as a reference point.
Therefore, a DMA read operation (figure 86) transfers
data from memory to 1/0 port and writes the data into
memory. During memory-to-I/O transfer, the DMA mode
register (DMD) is used to select the transfer directions
for each channel and activate the appropriate control
signals.
Operation
Transfer
Signals Activated
DMA read
DMAwrite
DMA verify
Memory to 1/0
1/0 to memory
No transfer
10WR, MRD
lORD, MWR
Addresses only
Bus Mode
The two available modes for determining how the DMAU
releases the CPU bus are bus release and bus hold. In
"PD71037 mode, the DMAU always functions in bus
release mode. In "PD71071 mode, the DMAU is programmable for bus release or bus hold mode via the DMA
device control (DOC) register:
In bus release mode, bus control is always relinquished
each time the service has completed. Therefore, if multiple DMA requests are generl;itedsimultaneously, a bus
cycle other than that for the DMAU is inserted between
consecutive DMA services (see figure 87). Consequently,
in certain applications DMA response may be delayed.
However, bus release mode gives better assurance that
the CPU will continue to execute programs in DMA
intensive environments.
In bus hold mode, if another DMA request is generated
before the end of one service, that request can be
serviced without the DMAU relinquishing the bus. However, the same channel cannot be serviced consecutively. This mode provides better DMA response but may
prevent CPU bus activity for extended periods of time.
NEe
Figure 86.
pPD70236 (V53)
TypiCIII Memory-to-l/O DMA Cycle
I
-
S1
I
S2
I
S3
I
S4
I
Figure 87.
~
Bus Modes
-
Bus Release Mode
Right to Use
Bus
MRD
\
'--
RIW
The operation of single, demand, and block transfers
depends on whether the DMAU is in bus release or bus
hold mode. Figure 88 shows the operations flow for the
six possible transfer and bus mode operations in DMA
transfer.
-- ~ -
Service
Channel
I
n n n r-
CPU - - ,
DMAU
LJ
CHO
L...I LJ LJ
CH1
CH2 CH3
Bus Hold Mode
-
1/
~
Right to Use
Bus
-
1/
~
Service
Channel
CPU ----,
DMAU
I
''''~'n
CHO,
CH1 , CH2 ,CH3
83SL-6687A
~------------------------------------~
READY
H rJ
II
DMAAK
ENDfTC
BUFEN
\0.-
-
1/
"H"
* Dotted line shows effect of selecting "Early Write"
timing in DDC register or command register.
83YL·6515A
Transfer Modes
The DMAU has three transfer modes as listed below. In
14PD71071 mode, bits 6 and 7 (TMODE) of the mode
control register (DMD) select the transfer mode. In
14PD71037 mode, bits 6 and 7 of the channel mode
register specify the mode. Transfer mode operation is
the same in both 14PD71071 and 14PD71037 modes.
Transfer Mode
Single
Termination Conditions
After each byte/word transfer
END input
Terminal count
Demand
END input
Terminal count
Service channel DMARQ dropped
Generation of a higher priority
DMARQ (bus hold mode)
Block
END input
Terminal count
77
EI
NEe
pPD70236 .(V53)
Figure 88. Transfer Modes
Single Transfer Mode
Bus Release Mode
Bus Hold Mode
No
No
Bus Release Mode
Bus Release Mode
(
78
Idle State
Demand Transfer Mode
Block Transfer Mode
Bus Hold Mode
Bus Hold Mode
NEe
Sing Ie Transfer Mode. In bus release mode, when a
channel completes transfer of a single byte or word, the
DMAU enters the slave mode regardless of the state of
DMA request inputs. In this manner, other lower priority
bus masters can access the bus.
In bus hold mode (p.PD71071 mode only), when a channel completes transfer of a single byte or word, the
DMAU terminates the channel's service even if the
DMARQ request signal is asserted. The DMAU will then
service any other requesting channel. If there are no
requests from any other DMA channels, the DMAU releases the bus and enters the idle state.
Demand Transfer Mode. In bus release mode, the
currently active channel continues to transfer data as
long as the DMA request of that channel is active, even
though other DMA channels are issuing higher priority
requests. When the DMA request of the serviced channel
becomes inactive, the DMAU releases the bus and
enters the idle state.
In bus hold mode (not available in p.PD71037 mode),
when the active channel completes a single transfer, the
DMAU cheeks the other DMA request lines without
ending the current service. If there is a higher priority
DMA request, the DMAU stops the service of the current
channel and starts servicing the highest priority channel
requesting service. If there is no higher request than the
current one, the DMAU continues to service the currently
active channel. Lower priority DMA requests are honored
without releasing the bus after the current channel
service is complete.
pPD70236 (V53)
When a mode register enables autoinitialize for a channel, the DMAU automatically reinitializes the address
and count registers when END is asserted or the terminal count condition is reached. The contents of the base
address and base count registers are transferred to the
current address and current count registers, and the
applicable bit of the mask register remains cleared.
Channel Priority
Each of the four DMAU channels is assigned a priority.
When multiple DMA requests from several channels
occur simultaneously, the channel with the highest priority will be serviced first.
The device control register selects one of two priority
schemes: fixed or rotating (figure 89). In fixed priority,
channel 0 is assigned the highest priority, and channel 3,
the lowest. In. rotating priority, priority order is rotated
after each service so that the channel last serviced
receives the lowest priority. This method prevents the
exclusive servicing of higher priority channels and the
lockout of lower priority DMA channels.
The rotating priority feature is selected by programming
the DMA device control (DDC) register in p.PD71071
. mode or by a write to the command register in p.PD71037
mode.
Figure 89. Priority Order
Fixed Priority
Highest
Block Transfer Mode. In bus release mode, the current
channel continues DMA transfers until a terminal count
or the external END input becomes active. During this
time, the DMAU ignores all other DMA requests. After
completion of the block transfer, the DMAU releases the
bus and enters the idle state, even if DMA requests from
other channels are active.
In bus hold mode (p.PD71071 mode only), the current
channel transfers data until an internal or external END
signal becomes active. When the service is complete,
the DMAU checks all DMA requests without releasing
the bus. If there is an active request, the DMAU immediately begins servicing the request. The DMAU releases
the bus after it honors all DMA requests or a higher
priority bus master requests the bus.
Lowest
Rotation Priority
Highest
Highest
Autoinitiali ze
This function is enabled by programming the mode
register (p.PD71071 and p.PD71037 modes).
83SL·6688A
79
.:!II
E.II
NEe
pPD70236 (V53)
Cascade Connection
Figure 91. Bus Waiting Operation
Slave DMA controllers can be cascaded to easily expand
the system DMA chanrlel capacity to 16 DMA channels.
Figure 90 shows an example of cascade connection.
During cascade operation, the DMAU acts as a mediator
between the BAU and the slave DMA controller. During
DMA cascade mode operation, it is the responsibility of
external logic to isolate the cascade bus master from the
V53 control outputs. These outputs are listed near the
beginning of this document.
The DMAU always operates in the bus release mode
while a cascade channel is in service, even when the bus
hold mode is programmed. Other DMA requests are held
pending while a slave DMA controller channel is in
service. When the cascaded device ends service and
moves into the idle state, the DMAU also moves to the
idle state and releases the bus. The DMAU continues to
operate normally with the other noncascaded channels.
Figure 90. pPD71071 Cascade EXllmple
~DMA1
V53
DMAU
(Master)
~DMA2
~DMA3
Cascade {DMAAK
HLDAK
Channels DMARQ 1.....1 - - - _ . 1 HLDRQ
DMA4
Other
Bus Master
I
DMARQ
_ _..oJ
DMABUSAK
_ _..oJ
DMAU
I
~
DMA BUSRQ
RCU
I
DMAU
I
Other
Bus Master
~ Approx 2 clocks
_ _..oJ
~
~ Bus waiting state
83YL-6684A
Address and Count Registers
Each DMA channel has a 24-bit base address register
and a 24-bit current address register. In addition, each
channel also has its own 16-bit current count register
and base count register: The base registers hold a value
determined by the CPU and transfer this value to the
current registers during autoinitialization. These registers are available in both p.PD71071 mode and p.PD71037
mode, but the method of accessing these registers
changes with compatibility mode.
The BN KR registers extend the p.PD71037 mode addresses from 16 to 24 bits. In p.PD71071 mode, the count
register and lower word of the address registers can be
accessed in 16-bit quantities. In p.PD71037 mode, these
registers must be accessed in 8-bit quantities.
.
DMAS
~PD71071
Programming the DMAU
(Slave)
DMA6
DMA7
83SL-6686A
Bus Waiting Operation
The DMAU automatically performs a bus waiting operation (figure 91) whenever the RE FU refresh request
queue fills. When the DMA bus acknowledge goes inactive, the DMAU enters the bus waiting mode and inactivates the DMA bus request signal. Control of the bus is
then transferred to the higher priority RE FU by the BAU.
Two clocks later, the DMAU reasserts its internal DMA
bus request. The bus waiting mode is continued until the
DMA bus acknowledge signal again becomes active and
the interrupted DMA service is immediately restarted.
80
To prepare a channel for DMA transfer, the following
characteristics must be programmed.
•
•
•
•
Starting address for the transfer
Transfer count
DMA operating mode
Transfer size (byte/word in p.PD71071 mode)
The contents of the OPHA and DULA registers determine
the base I/O port address of DMAU. Addresses A3-Ao are
used to select a particular register. There are two register
sets, one for p.PD71071 mode and the other for p.PD71037
mode.
I'PD71071 Mode
The p.PD71071 mode is selected by programming the
DMAU bit of the SCTLregister to zero. The register set
for this mode (table 7) is mapped into ~-Ao regardless of
the IOAG value in the SCTL register.
NEe
pPD70236 (V53)
Table 7. Regl.teT Selection (pPD71071I1ode)
Note.
FlguTe 92. DIIA Initialize Command Regl.teT
(DICM); pPD71071 Mode
Read/Write
1
7
DBC/DCC Oow)
Read/Wrlte
2
DBC/DCC (hIgh)
Read/Wrlte
2
4H
DBNQCA Oow)
Read/Write
2
0101
5H
DBNQCA (hIgh)
Read/Write
2
0110
6H
DBNQCA (upper)
Read/Write
1,2
A3-Ao
Addres.
Register
Operation
0000
OH
DICM
Write
0001
1H
DCH
0010
2H
0011
3H
0100
0111
7H
Reserved
1000
8H
DOC Oow)
Read/Write
1001
9H
DOC (hIgh)
Read/Write
1010
AH
DMD
Read/Write
1011
BH
DST
Read
1100
CH
Reserved
1101
DH
Reserved
1110
EH
Reserved
1111
FH
DMK
I
I
I- I
~
I- I
R~
Address OH
Byte OUT Instruction
RES
o
1
0
Reset
No operation
Reset DMAU
Channel Register. Writes to the DMA channel register
(DCH) select one of the four DMA channels for programming and also the base/current registers. Reads of the
DCH register return the currently selected channel and
the register access mode. See figure 93.
1,2
FlguTe 93. DIIA Channel Regl.teT (DCH);
pPD71071110de
-~---
Channel Register Read
I
Read/Write
Notes:
BASE
o
(1) Register can be accessed only with byte In/Out instructions. All
others can be accessed with 16-bit In/Out Instructions.
(2) There are four such registers, one for each DMA channel. The
particular register accessed Is determined by the DCH register.
0001
0010
0100
1000
Initialize. The DMA initialize command register (DICM)
performs a software reset of the DMAU. The DICM is
accessed using the byte OUT instruction. See figure 92.
Operation
Clear
Select channel 0
No change
DBA, DCA
DDC
DMD
DST
DMK
Address
Device control
Mode control
Status
Mask
No change
Clear
Clear
Clear
Set (mask all channels)
SEL3
I
SEL2
I
SEL 1
I
SELO
I
0
Access Conditions
Read: current only
Write: base and current
Selected Channel
o
1
2
3
Channel Register Write
- I- I- I
The DMAU initializes the registers as follows.
Name
Initialize
Channel
Count
I
Read/Wrlte: base only
SEL3-SELO
DMAU Registers In "PD71071 Mode
Register
DICM
DCH
DBC, DCC
BASE
Address 1H
Byte IN Instruction
7
BASE
Address 1H
Byte OUT Instruction
7
BASE
o
I
SELCH
0
Access Conditions
Read: current only
Write: base and current
Read/write: base only
SELCH
00
01
10
11
Selected Channel
Channel
Channel
Channel
Channel
0
1
2
3
Count Registers. When bit 2 of the DCH register is
cleared, a write to the DMA count register (figure 94)
updates both the DMA base count (DBC) and the DMA
current count (DCC) registers with a new count. If bit 2 of
the DCH register is set, a write to the DMA count register
affects only the DBC·register.
81
ED
NEe
pPD70236 (V53)
The DBC register holds the initial count value until a new
count is specified. If autoinitialization is enabled, this
value is transferred to the DCC register when a terminal
count or END condition occurs. For each DMA transfer,
the current count register is decremented by 1. The
count value loaded into the DBC/DCC register is 1 less
than the desired transfer count.
Figure S4. DMA Count Regl.ter. (DBC, DCC);
pPD71071 lIode
controls the bus mode, write timing, priority logic, and
enable/disable of the DMAU See figure 97.
Figure IJ6. DMA Device Control Regl.ter (DDC);
pPD71071 lIode
I EXW I ROT I
EXW
0
eol
o
Address 2H
IN/OUT Instruction
7
o
Address 3H
IN/OUT Instruction
7
1
ROT
0
I
Ca
1
DDMA
0
1
Address Register. Use either byte or word I/O instructions with the lower 2 bytes (4H and 5H) of the DMA
address register (figure 95). However, byte I/O instructions must be used to access the high-order byte (6H) of
this register. When bit 2 of the channel register is cleared,
a write to the DMA address register updates both the
DMA base address (DBA) and the DMA current address
(DCA) registers with the new address. If bit 2 of the DCH
register is set, a write to the DMA address register affects
only the DBA register.
The DBA register holds the starting address value until a
new address is specified. This value is transferred to the
DCA register automatically if autoinitialization is selected. For each DMA transfer, the current address
register is updated by 2 during word transfers and by 1
during byte transfers.
Figure 95. DMA Address Regl.'er. (DBA, DCA);
pPD71071 Mode
I7 A15
A14
A13
I A12 I A11 I A10
Address 5H
A9
I As 0I
A17
A16
IN/OUT Instruction
I A23
7
A22
A21
I A20 I A19 I A18
Address 6H
0
I
IN/OUT Instruction
Device Control Register. The DMA device control register· (DDG) (figure ~) is used to program the DMA
transfer characteristics common .to all DMA channels. It
82
Priority
Fixed
Rotational
DMA Operation (Note 2)
Enable
Disable
-
I
Disable
Enable
BHLD
Bus Mode
0
1
I
WEV
I
BHLD
I
0
Walt During Verify (Note 3)
1
0
o
Normal
Extended
Address 9H
IN/OUT Instruction
WEV
I - I
Writing (Note 1)
I
I7
I
Bus release
Bus hold
Notes:
(1) Disables BUSRQ to the BAU to prevent Incorrect DMA operation
whUe the DMAU registers are being Initialized or modified.
(2) When EXW = 0, the write signal becomes active (normal write)
during S3 and Sw. When EXW = 1, the write signal becomes
active during S2, S3, and SW (like the read slgnaQ.
(3) Walt states are generated by the READY signal during a verify
transfer.
o
Address 4H
IN/OUT Instruction
7
I
~ DDMA
Address 8H
IN/OUT Instruction
7
NEe
IIPD70236 (V53)
Figure 97. EBrly Write Cycle Timing
Ouring word transfers, two bytes starting at an even
address are handled as a single word. If the starting
address is odd, a OMA transfer is started after first
decrementing the address by 1. For this reason, always
select even addresses. The Ao and UBE outputs control
byte and word OMA transfers. The following shows the
relationship between the data bus width, Ao, and UBE
signals, and data bus status.
.
I S1 I S2 I S3 I S4 I S1 I S2 I S3 I SW I S4 I
Read
Normal Write
Ao
0-
Early Write
1
READY
n
------------~
o
~----
83YL·6685A
Mode Control Register. The DMA mode control register
(OMO) selects the operating mode for each OMA channel. The OCH register selects which OMO register will be
accessed. A byte IN/OUT instruction must be used to
access this register. See figure 98.
Figure9B. OIlA Mode Control Register (OliO);
pP071071 Mode
TMODE
1
7
TMODE
TDIR
Address OAH
1
Increment
Decrement
AUTI
Autoinitialize
o
TDIR
1
RQn
DMA Request, Channel n
o
No DMA request active
DMA request active
1
TCO
0
Terminal Count, Channel n
TCn
o
Not ended (for each read)
'E"ND or terminal count
1
Mask Register. The OMA mask register (OMK) allows
software to individually enable and disable OMA channels. The OMK register can only be accessed via byte 1/0
instructions. See figure 100.
Figure 100. DIM lIask Register (OIlK);
pPD71071 Mode
Verify
I/O-to-memory
Memory-to-I/O
Not allowed
11
Address OBH
Byte IN Instruction
o
Transfer Direction
00
01
10
W/B
7
Disable
Enable
1
0 8-015 valid
00-015 valid
Figure 99. OIlA Status Register (OS 1};
pPD71071 Mode
Address Direction
o
0
0
1 RCS 1 RQ2 I RC1 1 ROO I TCS I TC2 1 TC1
Demand
Single
Block
Cascade
11
Oata Bus Status
DO-07 valid
Status Register. The OMA status register (OST) contains information about the current state of each OMA
channel. Software can determine if a termination condition has been reached (TCO-TC3) or if a OMA service
request is present (ROb-R03). The byte IN instruction
must be used to read this register. See figure 99.
Transfer Mode
00
01
10
ADIR
wiS
1 ADIR I· AUTI 1
UBE
-,--
1
7
1
-
1 M3 I M2
Address OFH
Byte IN/OUT Instruction
1
M1
MO
a
Word/Byte Transfer
o
1
Mn
Byte
Word
o
1
DMARQ Mask, Channel n
Not masked
Masked
Addresses and count registers are updated as follows
during byte/word transfers.
Register
Address register
Count register
Byte Transfer
'M>rd Transfer
±1
±2
-1
-1
83
ED
NEe
pPD70236 (V53)
"PD71037 Mode
The p.PD71037 mode is selected by programming the
DMAM bit of the SCTl register to 1. See figure 48. Note
that on RESET, the DMAU is put into p.PD71071 mode.
The register set for the p.PD11037 mode (table 8) is
mapped into A3-Ao(lOAG = 0) or ~-A1 (IOAG = 1). For
the case where 10AG = 1, the DUlA system I/O register
determines whether the DMAU responds to Ao = 0 or 1.
TableS.
Register Set for pPD71037 Mode
Channel
Register
Read/Wrlte
Address
0
DCA
DCA, DCB
R
W
0000
DCC
DCC, DBC
R
W
0001
DCA
DCA, DCB
R
W
0010
DCC
DCC, DBC
R
W
0011
DCA
DCA, DCB
R
W
0100
DCC
DCC, DBC
R
W
0101
DCA
DCA, DCB
R
W
0110
DCC
DCC, DBC
R
W
0111
DST
DDC
R
W
1000
1001
1010
1011
1111
2
3
DSRQ
W
DSCM
W
DMD
W
DMK
W
The commands and their corresponding, addresses
Ao) are shown here.
Command
Clear byte select flag
Initialize
Clear mask register
10AG=O
x1100
x1101
x1110
(~
IOAG=1
1100x
1101x
1110x
DMAU Registers In "PD71037 Mode
Most of the DMAU registers ill this mode are the same as
those in the p.PD71071 mode, but with a different I/O
address or method of access.
Count and Address Registers. The DCA, DBA, DCC,
and DBC registers are 16 bits wide, but can only be'
accessed in byte-wide chunks. The byte select flag (BSF)
determines which byte is accessed. When the BSF is low,
the low byte is used; when the BSF is higti, the high byte
is used. The BSF cannot be read; to set it to a known
state, a byte select flag clear command must be issued
by performing an 8-bit I/O write to address x1100b. To
read or write one of these registers, first clear the BSF,
and then perform two consecutive 8-bit I/O operations.
The low byte will be accessed first and the high byte
second.
Bank Registers. The DMA memory addresses in the
p.PD71037 mode are 16 bits, compared with 24-bit addresses in the p.PD71071 mode. To expand the 16-bit
addresses into the full 24-bit address space of the V53, a
set of bank registers is provided, BN KRO-BN KR3, one per
DMA channel.
"PD71037 Commands
Each 8-bit register contains the upper address bits,
A23-A16, to be used when a DMA channel is active. DMA
addresses are modified after each transfer to point to the
next address in the DMA buffer. The SCTl system I/O
register, CE1-CEO bits, control whether a carry is propagated into the upper address bits when the DMA address is incremented or decremented. CEO controls the
carry propagation to A16 and CE1 controls the carry to
A20·
The BNKR registers are read 'or written using byte I/O
operations. See figure 101. As with other V53 internal
registers, the I/O address to which the BNKR registers
respond is programmable. The BADR system I/O register
(address FFE1H) sets the base address of the BNKR
registers in the 256-byte block of I/O space selected by
the OPHA register. See figure 102.
In addition to the registers explained above, three I/O
addresses cause commands to be executed when they
are written to. The val ue of the data written is not
important; it is the action of performing an I/O write to
one of these addresses that initiates the desired action.
Also, to allow maximum flexibility, the low two address
bits of each BN KR register are programmable. The BSEl
system I/O register (address FFEOH) sets the low two
address bits for each BN KR register. See figure 103. As
with other programmable addresses, the 10AG bit of the
The registers in table 8 can be accessed only by byte I/O
operations. The 10AG bit of the SCTl register determines
whether these registers reside in contiguous bytes, or
whether they each occupy one-half word (i.e., whether
the registers are byte or word aligned). If word aligned
(IOAG =1), the low bit of the DUlA register determines
whether the DMAU will use the upper or lower byte ofthe
word. In p.PD71071 mode, the setting of the 10AG bit
makes no difference; the register addresses do not
change.
84
NEe
pPD70236 (V53)
SCTL register has the effect of shifting the settable
address one bit position to the left.
The bank registers are only enabled in p.PD71037 mode.
In p.PD71071 mode, they cannot be read or written.
Figure 101. DMA Sank Registers (BNKR);
pPD71037 Mode
I A23
A22
7
I A19
I A21 I A20BNKRO
A18
A17
I
A16
a
IN/OUT
I A23
A22
I A23
A22
~
A18
I
A16
A17
I
A16
a
I
A21
DMA Device Control Reglsler (ODC);
pPD71037 Mode
I - I - I EXW I ROT I - IOOMA I
Byte OUT Instruction
EXW
a
1
A20
A19
BNKR2
IN/OUT
A18
A20
A19
BNKR3
IN/OUT
7
A17
a
I
A21
7
I A23
A18
A20
A19
BNKR1
IN/OUT
7
Figure 104.
7
I
A21
Device Control Register. In p.PD71037 mode, there are
fewer device options. The wait during verify and bus hold
control bits are not offered. The DMA device control
register (DOC) has only one byte to control early write
cycles, channel priority, and global DMA enable. See
figure 104.
A17
I
A16
a
ROT
I- I
a
Write Timing (Note 1)
Normal
Early
Channel Priority
a
Fixed
a
Enable
Disable
1
Rotational
- - oOMA
DMA Operation
1
Notes:
Figure 102. Sank Address Register (SADR);
pPD71037 Mode
I
As
A7
I
I
As
~
I
I
A3
Address FFE1H
IOAG = a
7
7
A2
*A1
(1) When EXW = a, the write signal becomes active during S3 and
Sw. When EXW 1, the write strobe is asserted earlier during S2,
S3. and SW (same as read strobe).
=
*~
a
o
Address FFE1H
IOAG = 1
*Address bits are set by the BSEL register.
Figure 103.
Sank Select Register (BSEL);
pPD71037 Mode
I
I
~~
~~
7
I
~~
Address FFEOH
BN Kn
00
01
10
11
Channel Mode Registers. Each channel has a mode
register allocated to it. All four registers are accessed
using the same I/O address. The low two bits of the data
written to the DMD register select the channel. Note that
byte transfers are supported but 16-bit transfers are not.
Figure 105 shows the format of the channel mode register.
~~
0
*Address Bits InBADR Register
00
01
10
11
* Address bits are A1, ~ if 100G
a bit in the SCTL register.)
= a or A2, A1 if IOAG = 1. (iOAG is
85
III
NEe
"PD70236 (V53)
Figure 105.
TMODE
7
OMA Channel Mode Registers (0110);
pP071D37Mode
I
ADIR
I
AUTI
I
TDIR
TMODE
00
01
10
11
ADIR
o
1
11
SELCH
00
01
10
11
Disable
Enable
RQn
o
1
TCn
o
1
Byte OUT Instruction
1
SELCH
00
01
10
11
Channel Selection for Mode Change
0
1
2
3
OMA Status Registers (DS7);
pP071D3711ode
Address x1000b
Byte IN Instruction
TCO
o
DMA Request, Channel n
I
SELCH
I
0
Mask Setting
Clear mask bit
Set mask bit
DMARQ Mask Channel Selection
Channel
Channel
Channel
Channel
0
1
2
3
Figure 109. Software 01fA Request Register
(OSRQ); pP071D37Mode
I- I
I - I - I -. I - I
SRO
Byte OUT Instruction
7
SRQ
Terminal Count, Channel n
1
Not ended (for each read)
END or terminal count
SMO
Software DMA Request Register. The DSRQ register is
used by software to trigger a DMA operation. One
application is to simulate the assertion of a hardware
DMA request for diagnostic purposes. This register is
written with the number of the targeted channel and a bit
that sets or clears an internal request flag associated
with that channel. Figure 109 shows the format of this
register.
No DMA request active
DMA request active
Mask Register and Single-Channel Mask Control
Register. The format and 1/0 address of this DMK
register (figure 107) is the same as in #,PD71071 mode
except that it cannot be read; it is a write-only register.
The DMK register can be put into a known state by
writing to it directly, by using the clear mask register
command, or by using the single-channel mask control
register (DSCM) at 1/0 address x1010b to set or clear the
enable bit for an individual channel (figure 108).
86
I- I- I- I- I
o
Verify
I/O-to-memory
Memory-to-1/0
Not allowed
Channel
Channel
Channel
Channel
Not masked
Masked
7
SMQ
I R03 I RQ2 I R01 I ROO I TC3 I TC2 I TC1
7
I
o
DMARQ Mask, Channel n
I
Transfer Direction
Status Register. This DST register (figure 74) is identical to the #,PD71071 mode DST register, but is at 1/0
address x1000b.
Figure 106.
MO
M1
Figure 108. OMA Single-Channel Masle Control
Register (OSCM); pP071D3711ode
Addres. Direction
Autoinitialize
00
01
10
I
M3
M2
Address OFH
Byte OUT Instruction
o
1
TDIR
I- I- I
7
Mn
Demand
Single
Block
Cascade
AUTI
1
0
Transfer Mode
Increment
Decrement
o
I I
SELCH
Byte OUT Instruction
Figure 107. OMA Masle Register (OMK);
pP071D37 Mode
o
SELCH
00
01
10
11
I
SELCH
0
I
Request
Clear request bit
Set request bit
Software DMARQ Channel Selection
Channel
Channel
Channel
Channel
0
1
2
3
Initialization. In #,PD71037 mode, there is no DICM
initialize register. Instead, the DMAU is initialized by
performing an 1/0 write to address x1100b.
NEe
I'PD70236 (V53)
entered by setting the STOP bit in the SBCR to 0 and
executing a HALT instruction. (See table 1 for output
pin states.)
POWER CONSERVATION
The V53 has three power conservation features.
• Scalable system clock
• Low-power HALT standby mode
• Very-low-power STOP mode
These features give three levels of power reduction,
making the V53 ideal for use in portable or other
low-power applications. The standby control register
(SBCR) at address OF F F1H in the system I/O area
controls all three functions. See figure 110.
Scalable System Clock
The V53 is a CMOS device and power consumption is
directly proportional to clock frequency. By reducing
the frequency, power use can be significantly decreased. The system clock is used by the CPU and
internal peripherals. The CLKC field in the SBCR selects a scale factor that divides the oscillation frequency by 2, 4, 8, or 16 to produce the system clock.
This value can be changed dynamically to adjust the
clock rate to the most efficient performance level for
the task at hand.
Caution: The system clock must not be set to less than the
minimum frequency specified in the AC Characteristics table.
Figure 110. Standby Control Register (SBCR)
I
I
I
I
fClK = Osc freq
fClK = Osc freq
fClK = Osc freq
fClK = Osc freq
2 19
2 18
217
2 16
-+-+-+-+-
fClK
fClK
felK
fClK
Sets HALT mode
Sets STOP mode
if WT
=
11 and fClK
=
16 MHz, time
The bus hold (HLDRQ/HLDAK) function still operates
during standby mode. External bus masters can take
the bus from V53. Also, refresh and DMA cycles can still
occur. The SCU and TCU can both be active, and can
supply the wakeup interrupt if desired.
STOP Mode
This mode provides the maximum power reduction. The
clock generator is disabled; the oscillator circuit is
turned off. Power usage is minimal. STOP mode is
entered by setting the STOP bit in the SBCR to 1 and
exec uti ng a HALT instruction. Since the system clock is
not active, none of the on-Chip peripherals can be used.
If the timer units TCLK input is used and driven by an
external oscillator, the timer will continue to function
and consume power.
The output pins in STOP mode are in the same state as
in HALT mode. Refer to table 1. The V53 will wake up
from STOP mode in response to a RESET, NMI, or
INTPn. The CPU may be in EI or 01 state. The INTP line
should be held active through oscillator stabilization
time until it is acknowledged.
Oscillator Stabilization Time
When HALT Instruction Is Executed
0
* For example,
-+- 2
-+- 4
-+- 8
-+- 16
* Oscillation Stabilization Time
00
01
10
11
STOP
0
System Clock Frequency felK
00
01
10
11
WT
I STOP I
WT
Address F F F1 H
7
CLKC
I
CLKC
The V53 will come out of HALT standby mode in
response to RESET, NMI, or an interrupt from the
internal interrupt control unit. If interrupts were enabled (IE= 1) before HALT mode was entered, an ICU
interrupt wakeup will result in the interrupt handler
being entered; if interrupts were not enabled (IE= 0),
then execution will resume at the instruction following
the HALT that put the CPU in the standby mode. If NMI
wakes up the CPU, the NMI handler is always entered.
=
4.096 ms
When the V53 is reset or when it wakes up from STOP
mode, the oscillator circuit is started up. This circuit
can take a relatively long time to come up to speed and
to stabilize. The oscillator stabilization time field (WT)
in the SBCR does not affect the physical startup time; it
determines how long the V53 will wait for the clock
generator oscillator circuit to stabilize. The user should
determine the worst case stabilization time and select
a longer value of WT.
HALT Standby Mode
RESET FUNCTION
Power can be further reduced by putting the CPU in
HALT standby mode. In this mode, the CPU is not
operating, but all the internal peripherals are still
enabled and may be drawing power. HALT mode is
The V53 is reset when a falling edge is input to the
RESET pin and is subsequently held low for six clocks
or longer than the oscillator stabilization time and then
made high.
87
III
NEe
pPD70236 (V53)
CPU Operations
Figure 112. Register Reset Status (conI)
When the V53 is reset, the CPU is initialized as shown in
figure 111 and starts prefetching instructions from address FFFFOH.
Register
Prefetch Pointer
PFP
Program Counter ,
PC
OOOOH
Program Segment Register
PS
FFFFH
Stack Segm$nt Register
SS
OOOOH
OOOOH
DSO
Data Segment 1 Register
OOOOH
DS1
OOOOH
Queue
Cleared
Program Status Word
PSW
V
0
I
OIR
0
IE
0
15
I
S
0
z
AC
0
0
0
0
I B~K0 I
I ~Y I
P
0
0
7
5
4
3
o
o
o
o
o
o
o
o
0,
o
o
o
o
o
o
o
o
o
2
Serlsl Control Unit
SMD
Figure 111. CPU Reset Status
Data Segment 0 Register
Initial Value, Bits 7-0
6
7
0
SCM
o
o
o
o
o
o
SIMK
SST
DMA Control Unit
DCH
DMD
0
DDC
(8H)
o
o
o
DDC
(9H)
DST
o
o
o
o
o
o
o
o
o
o
o
o
DMK
INSTRUCTION SET HIGHLIGHTS
Enhanced Instructions
Internal Register Operations
Some internal registers are also initialized by the RESET
input signal. See figure 112. The rest of the registers
retain the status they had immediately before the RESET
signal was applied, but their contents are undefined at
power up.
In addition to the "P08088/86 instructions, the
"P070236 has enhanced instructions listed in table 8.
Table B. Enhanced Instruction
Instruction
Function
PUSH Imm
Pushes Immediate data onto stack
PUSHR
Pushes 8 general registers onto stack
PO P R
Pops 8 general registers onto stack
MULlmm
Executes 16-bit multiply of register or memory
contents by Immediate data
SHLimm8
SHR imm8
SHRA ImmS
ROLlmmS
ROR ImmS
ROLClmm8
RORC ImmS
Shifts/rotates register or memory by immediate
value
CHKlND
Checks array index against designated
boundaries
WCY4
INM
Moves a string from an I/O port to memory
WMBO
OUTM
Moves a string from memory to an I/O port
PREPARE
Allocates an area for a stack frame and copies
previous frame pointers
DISPOSE
Frees the current stack frame on a procedure exit
Figure 112. Register Reset Status
Initial Value, Bits 7-0
Register
7
6
5
0
4
3
2
0
0
0
0
0
0
0
0
0
System 110 Ares
SCTL
OPSEL
1
WCYO
WCY1
WCY2
WCY3
WMB1
1
WAC
TCKS
RFC
SBCR
88
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
NEe
IIPD70236 (V53)
Enhanced Stack Operation Instructions
Stack Frame Instruction
PUSH Imm. This instruction allows immediate data to
be pushed onto the stack.
PREPARE Imm16,lmmS. This instruction is used to
generate the stack frames required by block-structured
languages, such as PASCAL and Ada. The stack frame
consists of two areas. One area has a pointer that points
to another frame which has variables that the current
frame can access. The other is a local variable area for
the current procedure.
PUSH R; POP R. These instructions allow the contents
of the eight general registers to be pushed onto or
popped from the stack with a single instruction.
Enhanced Multiplication Instructions
MUL reg16, Imm16; MUL mem16, Imm16. These instructions allow the contents of a register or memory
location to be multiplied by immediate data.
Enhanced Shift and Rotate Instructions
DISPOSE. This instruction releases that last stack frame
generated by the PREPARE instruction. It returns the
stack and base pointers to the values they had before
the PREPARE instruction was used to call a procedure.
Unique Instructions
SHL reg, ImmS; SHRreg, ImmS; SHRA reg, ImmS.
These instructions allow the contents of a register to be
shifted by the number of bits defined by the immediate
data.
In addition to the p.PD8088/86 instructions and the enhanced instructions, the p.PD70236 has the unique instructions listed in table 9.
~
ROL reg, immSj ROR reg immSj ROLC reg, ImmS;
RORC reg, ImmS. These instructions allow the contents
of a register to be rotated by the number of bits defined
by the immediate data.
Instruction
Function
INS
Insert bit field
EXT
Extract bit field
Check Array Boundary Instruction
ADD4S
Adds packed decimal strings
CHKIND reg16, mem32. This instruction is used to
verify that index values pointing to the elements of an
array data structure are within the defined range. See
figure 113. The lower limit of the array should be in
memory location mem32, the upper limit in mem32 + 2. If
the index value in reg16 is not between these limits when
CHKIND is executed, a BRK 5 will occur. This causes a
jump to the location in interrupt vector 5.
SUB4S
Subtracts one packed decimal string from
another
Figure 113. Check Array Boundary
Memory
Table 9. Unique Instructions
CMP4S
Compares two packed decimal strings
ROL4
Rotates one BCD digit left through AL lower 4 bits
ROR4
Rotates one BCD digit right through AL lower 4 bits
BRKXA
Break and enable expanded addressing
RETXA
Return from break and disable expanded
addressing
TEST1
Tests a specified bit and sets/resets Z flag
NOT1
Inverts a specified bit
CLR1
Clears a specified bit
SET1
Sets a specified bit
REPC
Repeats next Instruction until CY flag Is cleared
15
Upper Limit
~
.:!t
Array
~
Low"umlt~
mem32 + 2 (Upper Limit)
mem32 (Lower Limit)
REPNC
Repeats next instruction until CY flag Is set
FP02
Additional floating-point processor call
49NR-336A
variable Length Bit Field Operation Instructions
Block I/O Instruction
OUTM DW, src-block; INM dist-block, ow, These instructions are used to output or input a string to or from
memory, when preceded by a repeat prefix.
This category has two instructions: IN S (Insert Bit Field)
and EXT (Extract Bit Field). These instructions are
highly effective for computer graphics and high-level
languages. They can, for example, be used for data
structures such as packed arrays and record type data
used in PASCAL.
89
NEe
pPD70236 (V53)
IN S reg8, regs; IN S regS, Imm4. This instruction transfers low bits from the 16-bit AW register (the number of
bits is specified by the second operand) to the memory
location specified by the segment base (DS1 register)
plus the byte offset (IV register). The starting bit position
within this byte is specified as an offset by the lower 4
bits of the first operand. See figure 114.
After each complete data transfer, the IV register and the
register specified by the first operand are automatically
updated to point to the next bit field.
Either immediate data or a register may specify the
number of bits transferred (second operand). Because
the maximum transferable bit length is 16 bits, only the
lower 4 bits of the specified register (OOH to OFH) will be
valid.
Bit field data may overlap the byte boundary of memory.
Figure 114. Bit Field Insertion
Bit
~
dJ'
O~~_!I: O""'t[1Y]
~F---:----r-~~f:'-"-l--~~1--/-iqM.mo.
Awi' 0
Bit
Byte
Boundary
.yre
Segment Base
[OS1]
49NR-341A
EXT regS, regs; EXT regS, Imm4. This instruction
loads to. the AW registers the bit field data whose bit
length is specified by the second operand of the instruction from the memory location that is specified by the
DSO segment register (segment base), the IX index
register (byte offset), and the lower 4 bits of the first
operand (bit offset). See figure 115.
After the transfer is complete, the IX register and the
lower 4 bits of the first operand are automatically updated to point to the next bit field.
Either immediate data or a register may be specified for
the second operand. Because the maximum transferable bit length is 16 bits, however, only the lower 4 bits of
the specified register (OOH to OFH) will be valid.
Bit field data may overlap the byte boundary of memory.
Figure 115. Bit Field Extraction
Bit
Bit
Byte
; ~. OOjr~t~M'=.
15
1
0
Awl·oV//I
Byte
Boundary
Segment Base
[OSO]
49NR-342A
Packed BCD Operation Instructions
The instructions described here process packed BCD
data either as strings (ADD4S, SUB4S, CMP4S) or byteformat operands (ROR4, ROl4). Packed BCD strings
may be from 1 to 254 digits in length.
When the number of digits is even, the zero (Z) and carry
(CY) flags will be set according to the result of the
operation. When the number of digits is odd, the Z and
CV flags may not be set correctly. In this case (Cl =
odd), the Z flag will not be set unless the upper 4 bits of
the highest byte are all Os. The CV flag will not be set
unless there is a carry out of the upper 4 bits of the
highest byte. When Cl is odd, the contents of the upper
4 bits of the highest byte of the result are undefined.
ADD4S. This instruction adds the packed BCD string
addressed by the IX index register to the packed BCD
string addressed by the IV index register, and stores the
result in the string addressed by the IV register. The
length of the string (number of BCD digits) is specified
by the Cl register, and the result of the operation will
affect the V (overflow), Cv, and Z flags.
BCD string (Iv, Cl) - BCD string (IV, Cl)
(IX, CL)
+ BCD string
SUB4S. This instruction subtracts the packed BCD
string addressed by the IX index register from the
packed BCD string addressed by the IV register, and
stores the result in the string addressed by the IV
register. The length of the string (number of BCD digits)
is specified by the Cl register, and the result of the
operation will affect the V, Cv, and Z flags.
BCD string (Iv, el) - BCD string (Iv, el) - BCD string
(IX, Cl)
CMP4S. This instruction performs the same operation
as SUB4S except that the result is not stored and only
the V, CY, and Z flags are affected.
BCD string (Iv, el) - BCD string (IX, Cl)
ROL4. This instruction treats the byte data of the register or memory operand specified by the instruction as
90
t-IEC
BCD data and uses the lower 4 bits of the AL register
(ALL) to rotate that data one BCD digit to the left. See
figure 116.
Figure 116. BCD Rotste Left
ROR4. This instruction treats the byte data of the register or memory specified by the instruction as BCD data
and uses the lower 4 bits of the AL register (ALL) to rotate
that data one BCD digit to the right. See figure 117.
pPD70236 (V53)
mode. The IkPD70236 will begin fetching from the new
PFP through the address translation table. That is, the
new PC is treated as a logical address and is translated
to the new, larger physical address space.
This instruction does not save any return address information, such as PC, PS, or PSW to the stack.
RETXA ImmS. This instruction is used to turn off expanded addressing. It is identical in operation to BRKXA,
except that the expanded addressing mode is turned off
before fetching from the new address. That is, the XA flag
in the XAM register is set to 0, and the PC is loaded with
the value of the PC field in the interrupt vector selected
by the immediate data.
This instruction does not save any return address information such as PC, PS, or PSW to the stack.
Figure 117. BCD Rotste Right
Porting I'PD70116/70108 Code to I'PD70236
Bit Manipulation Instructions
TEST1. This instruction tests a specific bit in a register
or memory location. If the bit is 1, the Z flag is reset to O.
If the bit is 0, the Z flag is set to 1.
NOT1. This instruction inverts a specific bit in a register
or memory location.
CLR1. This instruction clears a specific bit in a register
or memory location.
SET1. This instruction sets a specific bit in a register or
memory location.
Repeat Prefix Instructions
REPC. This instruction causes the IkPD70236 to repeat
the following primitive block transfer instruction until
the CY flag becomes cleared or the CW register becomes zero.
REPNC. This instruction causes the IkPD70236 to repeat
the following primitive block transfer instruction until
the CY flag becomes set or the CW register becomes
zero.
Address Expansion Control Instructions
BRKXA immS. This instruction is used to turn on expanded addressing. The 8-bit immediate data specifies
an interrupt vector. The PC field of this vector is loaded
into the PC (and PFP). The XA flag in the XAM register is
set to 1, thereby enabling the expanded addressing
The IkPD70236 is completely software compatible with
the IkPD70116/70108. However, thelkPD70236 offers
some improvements that may affect .the porting of
IkPD70116 code to the IkPD70236. These improvements
are:
(1) The IkPD70116 does not trap on undefined opcodes.
The IkPD70236 will trap, and also will trap when a
register addressing mode is used for any of these
instructions:
CHKIND
MOV DSO/DS1
CALL 1,id
LDEA
BR 1,id
(2) During signed division (DIV), if the quotient is OOH
(byte operation) or 8000H (word), the IkPD70116 will
take a Divide By 0 trap. The IkPD70236 will perform
the calculation.
(3) When the IkPD70116 executes the POLL instruction,
it will wait for the POLL input signal to be asserted.
The IkPD70236 has no POLL input; instead, when this
instruction is executed, if a coprocessor is not
connected, then a Coprocessor Not Present trap will
be taken. If a coprocessor is attached, then no
operation takes place.
The IkPD70116 accepts FP01 and FP02 as opcodes
for the iAPX8087 coprocessor. The IkPD70236 accepts these as opcodes for the IkPD72291 coprocessor, which is not compatible with the iAPXOO87.
(4) During the POP R instruction, the IkPD70116 does
not restore the SP register. The IkPD70236 does
restore the SP.
91
III
NEe
pPD70236 (V53)
(5) When processing a divide error, the 14PD70116 saves
the address of the next instruction. The 14PD70236
saves the address of the current instruction (the
divide instruction).
(6) The p.PD70116 allows up to three prefix instructions
in any combination. The 14PD70236 also allows three
prefixes, but only one of each type can be used. The
14PD70236 could operate incorrectly if there are two
prefixes of the same type. For example, consider:
REP
REPC
CMPBK SS: src-block, dst-block
If the compare operation is interrupted, then when it
resumes following the interrupt service, execution
will begin at the REPC instruction, not the REP
instruction, because two repeat prefixes were used.
(7) The 14PD70116 accepts NMI requests even while
processin9..!!!..NMI. The 14PD70236 does not allow
nes!l!:!9..of NMls; the NMI input will be ignored until
the NMI interrupt handler is exited.
INSTRUCTION SET
Symbols
Preceding the instruction set, several tables explain
symbols, abbreviations, and codes.
Clocks
In the Clocks column of the instruction set, the numbers
cover these operations: instruction decoding, effective
address calculation, operand fetch, and instruction execution.
Clock timings assume the instruction has been
prefetched and is present in the 8-byte instruction
queue. Otherwise, add two clocks for each pair of bytes
not present.
VVord operands require two additional clocks for each
transfer to an unaligned (odd address) memory operand.
These times are shown on the right side of the slash (j).
For conditional control transfer or branch instructions,
the number on the left side of the slash is applicable if the
transfer or branch takes place. The number on the right
side is applicable if it does not take place.
If a range of numbers is given, the execution time
depends on the operands involved.
92
NEe
pPD70236 (V53)
Symbols
Symbol
Meaning
Symbol
Meaning
acc
Accumulator(AW or AL)
AL
Accumulator ~ow byte)
duso
Displacement (8 or 16 bits)
AW
Accumulator (16 bits)
dmem
Direct memory address
BH
BW register (hIgh byte)
dst
Destination operand or address
BL
BW register Oow byte)
ext-dlspS
16-bit displacement (sign-extension byte
bit displacement)
+ 8-
far-'abel
Label within a different program segment
far_proc
Procedure within a different program segment
fp_op
Floating-point Instruction operation
Imm
8- or 16-blt immediate operand
Imm3/4
3- or 4-bit Immediate bit offset
Imm8
8-bit Immediate operand
Imm16
16-bit Immediate operand
mem
Memory field (000 to 111); 8- or 16-bit memory
location
mem8
8-blt memory location
mem16
16-bit memory location
mem32
32-bit memory location
memptr16
Word containing the destination address within
the current segment
memptr32
Double word containing a destination address in
another segment
mod
Mode field (00 to 10)
neaclabel
Label within the current segment
near_proc
Procedure within the current segment
offset
Immediate offset data (16 bits)
pop_value
Number of bytes to discard from the stack
reg
Register field (000 to 111); 8- or 16-bit generalpurpose register
regS
S-bit general-purpose register
BP
BP register
BRK
Break flag
BW
BW register (16 bits)
CH
CW register (hIgh byte)
CL
CW register Oow byte)
CW
CW register (16 bits)
CV
Carry flag
DH
OW register (hIgh byte)
DIR
Direction flag
DL
OW register Oow byte)
DSO
Data segment 0 register (16 bits)
DS1
Data segment 1 register (16 bits)
OW
OW register (16 bits)
IE
Interrupt enable flag
IX
Index register (source) (16 bits)
IV
Index register (destination) (16 bits)
MD
Mode flag
P
Parity flag
PC
Program counter (16 bits)
PS
Program segment register (16 bits)
PSW
Program status word (16 bits)
R
Register set
S
Sign extend operand field
S = No sign extension
S = Sign extend Immediate byte operand
reg16
16-bit general-purpose register
S
Sign flag
regptr
16-bit register containing a destination address
within the current segment
SP
Stack pointer (16 bits)
SS
Stack segment register (16 bits)
regptr16
Register containing a destination address within
the current segment
seg
Immediate segment data (16 bits)
shorUabel
Label between-128 and + 127 bytes from the
end of the current instruction
sr
Segment register
src
Source operand or address
temp
Temporary register (8/16/32 bits)
AC
Auxiliary carry flag
AH
Accumulator (high byte)
ED
V
Overflow flag
W
Word/byte field (0 to 1)
X, XXX, YYY, ZZZ
Data to identify the Instruction code of the
external floating-point arithmetic chip
XXH
Two-digit hexadecimal value
XXXXH
Four-digit hexadecimal value
Z
Zero flag
93
NEe
pPD70236 (V53)
Flag Operations
Register Selection (mod
= 11)
Symbol
Meaning
reg
w=o
(blank)
No change
000
AL
AW
W
=1
Cleared to 0
001
CL
CW
Set to 1
010
OL
OW
x
Set or cleared according to result
011
BL
BW
u
Undefined
100
AH
SP
R
Restored to previous state
101
CH
BP
110
OH
.IX
111
BH
IY
0
Memory Addressing Modes
= 00
= 01
= 10
mem
mod
000
BW+ IX
BW + IX + dlspS
BW + IX + dlsp16
Segment Register Selection
001
BW+IY
BW + IY + dlspS
BW + IY + dlsp16
sr
010
BP + IX
BP + IX + dlspS
BP + IX + dlsp16
00
OS1
011
BP + IY
BP + IY + dlspS
BP + IY + dlsp16
01
PS
100
IX
IX + dlspS
IX + dlsp16
10
SS
101
IV
IY + dlspS
IY + dlsp16
11
OSO
110
Direct
BP + dlsp8
BP + dlsp16
111
BW
BW + dlspS
BW + dlsp16
mod
mod
Segment Register
Instruction Set
Opcode
Mnemonic
Operand
7
6
5
4
Flags
0
7
6
0
1 W
1
1
reg
reg
0
0
mod
reg
mem
3/5
3
2
1
0
1-
5
4
3
2
1
0
Clocks
Bytes
AC
CY
x
x
V
P S Z
Dsts Trsnsfer Instructions
MOV
reg, reg
0
0
0
mem, reg
0
.0
0
reg, mem
1
0
mem,lmm
0
0
1
.0
0
0
reg,imm
0
1 W
acc, dmem
0
0
0
0
dmem, acc
0
1 0
0
0
sr, reg16
0
.0
0
mod
reg
mem
5/7
2·4
mod
000
mem
3/5
3·6
-2
5/7
3
W
3/5
3
2
2
0
1
1
0
sr
reg
0
sr
mem
1 0
sr
reg
sr
mem
0
.0
0
1
0
reg16, sr
0
.0
0
0
0
1
mem16, sr
0
0
0
0
0
mod
1
0
0
0
0
1
mod
reg
0
0
0
1 0
0
mod
reg
0
0
1
OS1, reg16, mem32
1
AH, PSW
.0
.0
1
LOEA
PSw, AH
reg16, mem16
1
0
0
.0
TRANS
src_table
1
1 .0
2·3
W
mod
1
2
2·4
W
reg
0
2
W
sr, mem16
OSO, reg16, mem32
94
W
0
.0
0
.0
1
1
1
2·4
2
2·4
mem
1.0/14
2·4
mem
10/14
2·4
2
2
0
1
2
3/5
1
1
5/7
mod
reg
mem
2
5
2·4
x x x
NEe
pPD70236 (V53)
Instruction Set (cont)
Opcode
Mnemonic
Operand
7
8
5
4
3
2
1
o
7
Flags
8
5
4
3
2
1
0
Clocks
BytnACCYVPSZ
Dsts Trsnsfer Instructions (cont)
XCH
0
0
0
0
w
mem, reg
0
0
0
0
W
AW, reg16
o 0
reg, reg
1
o
reg
mod
reg
reg
reg
mem
3
8112
2
2-4
3
Repest Prefixes
REPC
REPNC
REP
REPE
REPZ
REPNE
REPNZ
0
0
0
0
1
O· 1
2
0
0
1
0
0
2
0
0
1
0
0
1
0
0
0
1
0
W
2
2
Block Trsnsfer Instructions
MOVBK
dst, src
1
0
1
1
3+4n(W=0)
3 + 4n (W = 1, even addresses)
3 + 8n (W = 1, odd addresses)
3 + 6n (W = 1, odd/even addresses)
CMPBK
dst, arc
1
0
1
o
0
1
1
1
W
x
x
xxxx
3+7n(W=O)
3 + 7n (W = 1, even addresses)
3 + 11 n (W = 1, odd addresses)
3 + 9n (W = 1, odd/even addresses)
CMPM
dst
1
0
1
o
1
1
1
W
x
x
xxxx
3 + 5r'1(W = 0)
3 + 5n (W = 1, even addresses)
3 + 7n (W = 1, odd addresses)
LDM
src
1
0
1
o
1
0
1
W
5+2n(W=0)
5 + 2n (W = 1, even addresses)
5 + 4n (W = 1, odd addresses)
STM
dst
1
0
1
o
1
0
1
W
1
3+2n(W=0)
3 + 2n (W = 1, even addresses)
3 + 4n (W = 1, odd addresses)
n = number of returns
String Instruction execution clocks for a single-Instruction execution are in parentheses.
95
NEe
IIPD70236 (V53)
Instruction Set (cont)
Opcode
Mnemonic
Operand
7
6
5
4
3
2
1
0
7
Flags
6
5
4
3
2
1
0
Clocks
Bytes
AC
CY
V
P
S
Z
I/O Instructions (cont)
IN
OUT
INM
acc.lmm8
0
0
0
W
5fT
acc. OW
0
1
0
W
3/5
Imm8. acc
0
0
1
W
3/5
ow, acc
0
1
W
3/5
0
0
W
dst. OW
0
2
2
1
+ 11n rN = 0)
+ 8n rN = 1. even addresses)
+ 22n rN = 1. odd addresses)
+20n rN = 1. odd/even addresses;
odd for I/O)
3 + 13n rN = 1. odd/even addresses;
odd for memory)
3
3
3
3
OUTM
Ow, src
o
1
1
0
1
1
1
W
11n rN = 0)
8n rN = 1. even addresses)
22n rN = 1. odd addresses)
20n rN
1. odd addresses;
odd for I/O)
3 + 13n rN = 1. odd addresses;
odd for memory)
3
3
3
3
+
+
+
+
=
n = number of transfers
String Instruction execution clocks for a single-Instruction execution are In parentheses.
Use the right side of the slash (f) for OMA I/O accesses.
BCD Instructions
AOJBA
0
0
AOJ4A
0
0
AOJBS
0
0
1
AOJ4S
0
0
1
0
0
o
o
AOO4S
dst. src
0
0
0
0
0
0
0
0
0
SUB4S
dst. src
0
0
0
0
0
0
0
0
0
CMP4S
dst. src
0
0
0
0
0
ROL4
reg8
0
0
0
0
1
1
1
0
0
0
mem8
0
0
0
0
1
mod
0
0
0
0
0
0
0
1
1
1
0
0
0
reg
0
0
0
0
mod
0
0
0
mem
ROR4
reg8
mem8
n
96
0
4
x
x
u
u
u
u
2
x
x
u
x
x
x
4
x
u
u
u
x
x
x
x
x
x
u
2
u
x
x
x
u
u
u
x
u
u
u
u
u
u
x
x
0
2 + 18n
2
u
0
2 + 18n
2
u
2
u
+
0
0
0
0
7
0
0
0
0
0
0
9
0
0
0
0
0
0
15
3·5
0
0
0
a
0
13
3
0
0
0
a
0
19
3·5
14n
3
reg
mem
1
= number of BCD digits divided by 2
NEe
IIPD70236 (V53)
Instruction Set (cont)
Opcode
Mnemonic
Operand
7
6
5
4
3
2
Flags
1
o
765
4
321
o
Clocks
0
o
o
o
o
o
o
o
Bytes
AC
CY
V
P
S
Z
12
2
u
u
u
x
x
x
8
2
u
u
u
x
x
x
x
x
x
Dsts Type Conversion Instructions
CVTBD
1
0
1
o
CVTDB
CVTBW
o
0
CVTWL
o
0
0
o
1
0
o
o
0
0
0
0
0
0
0
o
2
0
2
Arithmetic Instructions
ADD
reg, reg
0
0
0
0
0
0
1
W
mem, reg
0
0
0
0
0
0
0
W
mod
reg, mem
0
0
0
0
0
0
W
mod
0
0
0
0
0
S
0
0
0
0
0
S W
reg, Imm
mem, imm
1
W
mod
reg
reg
2
x
x
x
reg
mem
7/11
2-4
x
x
6/8
2-4
x
x
2
3-4
x
x
x x x x
x x x x
x x x x
7/11
3-6
x
x
x
reg
mem
000
reg
000
mem
2
x
x
x
mil
_________a_~
__
,_lm_m
____0___
0__0___0__0_._____
0 __W
______________~_________2_________2_-3___,_x____x___x___x___
x___
x ~
ADDC
reg, reg
0
0
0
0
0
1
W
reg
reg
2
x
mem, reg
0
0
0
0
0
0
W
mod
reg
mem
7/11
2-4
x
x
x
reg, mem
0
0
0
W
mod
reg
mem
6/8
2-4
x
x
0
0
S WOO
2
3-4
x
x
0
0
S
W
7/11
3-6
x
x
0
1
0
W
2
2-3
x
reg, Imm
mem,lmm
a~i
SUB
Imm
0
0
0
0
0
0
0
reg
reg
2
x
mod
reg
mem
7/11
2-4
x
mod
reg
mem
6/8
2-4
x
x
1
0
1
W
o
0
0
0
0
S
W
mem,lmm
1
0
0
0
0
0
S
W
aee,lmm
o
0
1
0
1
0
W
reg, reg
000
01W
mem, reg
0
0
0
0
reg, mem
0
0
0
0
0
0
0
0
S
W
0
0
0
S
W
0
W
0
ace, imm
o
0
0
0
0
mod
W
mod
o
mem
W
000
1
o
001
mem8
mem16
o
mod
o
mod
mod
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
reg
2
x
x
x
x
mem
7/11
2-4
x
x
x
x
x
x
reg
mem
6/8
2-4
x
x
x
x
x
x
2
3-4
x
x
x
x
x
x
7/11
3-6
x
x
x
x
x
x
2
2-3
x
x
x
x
x
x
2
2
x
x
x
x
x
2-4
x
x
x
x
x
x
x
x
x
x
2
x
x
x
x
x
2-4
x
x
x
x
x
x
x
x
x
u
x
x
u
u
u
mem
o
reg
0
mem
000
reg
000
mem
2
3-4
x
x
7/11
3-6
x
x
2
2-3
x
x
2
7/11
o
0
reg
0
0
mem
2
7/11
x
2
0
x
reg
reg
0
reg
1
x
reg
0
2
W
1
o
o
o
reg16
mod
o
mem
reg16
mod
2
x
x x x
x x x
x x x
x x x
x
x
x
x
x
x
reg
regS
regS
mod
W
regS
o
mem
W
0
0
0
0
1
1
0
0
0
mem, imm
mod
reg
x
x
x
o
o
reg16
MULU
0
00001W
reg, Imm
DEC
0
reg, reg
reg,lmm
INC
0
0
mem, reg
reg, mem
SUBC
0
0
2
o
o
o
o
x x
0
reg
8
2
0
reg
12
2
u
x
x
u
u
u
0
mem
12
2-4
u
x
x
u
u
u
0
mem
16/18
2-4
u
x
x
u
u
u
97
NEe
"PD70236 (V53)
Instruction Set (cont)
Opcode
Mnemonic
Operand
7
6
543
2
1
0
7
Flag6
5
4
3
2
1 0
Clock_
Byte_ AC
CY V
P S Z
Arithmetic Instructions (cont)
MUL
regS
memS
mem16
DIVU
0
0
0
1 0
0
reg
S
2
u
x
x
u
u u
mod
0
mem
12
2·4
u
x
x
u
u u
mod
0
mem
16/18
2·4
u
x
x
u
u u
1
reg
reg
3
u
x
x
u u u
3-5
u
x
x
u u u
4
u
x
x
u
u u
4·6
u
x
x
u
u u
reg16, reg16, Imm8
0
0
0
reg16, mem16, ImmS
0
0
0
mod
reg
mem
reg16, reg16, Imm16
0
0
0
0
1
1
reg
reg
reg16, mem16, Imm16
0
0
0
0
mod
reg
mem
1
12
16/1S
12
16/8
regS
0
0
0
reg
11
2
u
u
u
u
u u
reg16
o
o
o
o
o
o
o
1
0
reg
19
2
u
u
u
u
u u
mem8
mem16
DIV
0
----------------------------------------------------------------------------------reg16
0
0
reg
12
2
u
x xu' u u
regS,
reg16
memS
mem16
0
mod
0
mem
15
2·4
u
u
u
u
u u
1
mod
0
mem
23/25
2·4
u
u
u
u
u u
reg
16
2
u
u
u
u
u u
reg
24
2
u
u
u
u
u u
mod
mem
20
2·4
u
u
u
u
u u
mod
mem
28/30
2·4
u
u
u
u u u
x:
X
X
X
0
.1
0
Comparison Instructions
CMP
reg, reg
0 0
0
1 W
1
1
reg
reg
2
2
X
X
----------------------------------------------------------------------------------~
mem, reg
o
reg, mem
001110
reg,lmm
0
0
0
W
W
OOOOOSW
mem,lmm
100000SW
acc,lmm
o
0
0
2·4
x
x
x
x
x
x
6/S
2·4
x
x
x
x
x
x
2
3·4
x
x
x
x
x
x
6/S
3·6
x
x
x
x
x
x
2
2·3
x
x
x
x
x
x
2
2
mod
reg
mem
6/8
mod
reg
mem
1
1
reg
mod
mem
W
Logics/Instructions
NOT
NEG
reg
0
W
1 W
mod
reg, reg.
0000
OW
1
mem, reg
0000
OW
reg,lmm
o
W
reg
1
0
1
1 W
1 0
reg
0
mem
1
reg
mod
reg
1
1 0
mod
reg
mem
0
0
reg
0 0
0
mem
2
x
x
x
x
x
2·4
x
x
x
x
x
x
2
u
0
6/8
2·4
u
2
3·4
u
6/8
3·6
u
2
2·3
u
2
2
u
o
o
o
o
o
o
o
o
o
o
o
x
0 x
0 x
0 x
0 x
0 x
0 x
0 x
0 x
0 x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x x x
2
7/11
2
ace, imm
100100W
reg, reg
00
0001
W
1
1
reg
reg
memo reg
o
0
W
mod
reg
mem
7/11
2·4
u
reg, mem
001000
W
mod
reg
mem
6/8
2·4
u
OOOOOOW
11
o
2
3·4
u
mod
o 0
7/11
3·6
u
2
2·3
u
reg, imm
98
1
o
1
mem, imm
AND'
1 1 0
1 0
reg
mem
TEST
W
----------------------------------------------------------------------------------mem
o
W
mod 0
0
mem
7/11
2·4
0
mem, imm
1 0
0
0
ace, imm
0000
0
0
0
0
0
0
W
OW
0
reg
mem
x
NEe
pPD70236 (V53)
Instruction Set (cont)
Flag.
Opcode
Mnemonic
Operand
7
6
5
4
3
2
1
0
7
6
o
o
5
4
3
2
1
0
Clock.
1
W
1
1
reg
reg
0
W
mod
reg
mem
7/11
Byte. AC
CY
V
P
S
Z
o
o
0
x
x x
0
x
x
x x
x x
x x
Logicsllnstructlons (cont)
OR
XOR
reg, reg
0
0
0
0
mem, reg
0
0
0
0
reg, mem
o
0
0
0
W
mod
reg
mem
reg,imm
1
000
0
0
0
W
1
1
0
0
reg
mem,imm
1
000
0
0
0
W
mod
0
0
mem
ace, imm
00001
reg, reg
mem, reg
o
o
reg, mem
001100
reg,imm
0
2
OW
2
u
2·4
u
6/8
2·4
u
o
0
2
3·4
u
0
x
7/11
3·6
u
0
2
2·3
u
0
x· x x
x x x
2
2
u
2
3·4
u
7/11
3·6
u
2
2·3
u
o
o
o
o
o
o
o
o
o
0
0
0
1
W
1
1
reg
reg
0
0
0
0
W
mod
reg
mem
7/11
2·4
u
W
mod
reg
mem
6/8
2·4
u
OOOOOOW
mem, imm
1000000W
ace, imm
o
0
0
0
1
o
o
1
mod
reg
mem
W
0
x
x
o
x
x
x
x
o
x
x
x
oxx:
o x x
o x x x
Bit Msnlpulstlon Instructions
INS
reg8, reg8
rega, imm4
EXT
rega, reg8
rega, imm4
TEST1
reg, CL
0
0
1
1
0
o
0
0
0
1
1
1
0
0
0
o
0
0
1
1
o
0
0
0
1
1
0
0
o
0
001
mem16, CL
reg, imm3/4
mem8, imm3
mem16, imm4
o
reg, CL
0
0
000
o
0
001
1
1
0
0
0
0
0
0
mod
0
0
0
o
0
mod
reg, imm3/4
o
0
0
0
mem
0
1
o
0
0
29·61/
3
33·63
o
0
29·61/
4
33·63
000
o
0
0
W
4
3
u
0
0
u
u
x
000
o
0
0
0
a
3·5
u
0
0
u
u
x
000
000
8/10
3·5
u
0
0
u
u
x
000
o
0
W
4
4
u
0
0
u
u
x
000
o
0
0
13
4·6
u
0
0
u
u
x
000
o
0
8/10
4·6
u
0
0
u
u
x
000
o
o
W
4
3
000
o
o
W
9
3·5
o
W
4
4
reg
mem
0 0
000
0
4
39·77
mem
0 0
000
0
37·69/
mem
0 0
o
0
mem
reg
000
3
reg
0
000
mem,CL
o
0
reg
000
mod
o
o
o
0
000
0
37·61/
39·77
o
mod
0
0
reg
001
o
100
reg
0
0
mod
SET1
001
reg
reg
o
mema, CL
0
reg
1
reg
99
1II
NEe
pPD70236 (V53)
Instruction Set (cont)
Opcode
Mnemonic
Operand
7
8
5
4
3
2
1
Flags
1
0
7
8
5
1
1
0
0
0
1
0
0
0
4
3
2
1
0
Clocks
0
0
9
4-6
9/13
4·6
Bytes
AC
CV
Bit Manipulation Instructions (cont)
SET1 (cont)
mem8,lmm3
mem16,Imm4
0
0
0
0
1
mod
0
0
0
0
0
0
0
1
mod
0
0
0
1
1
1
1
0
0
0
1
0
0
0
cv
reg, CL
mem8, CL
mem16, CL
reg,lmm3/4
mem8,lmm3
mem16,lmm4
NOT1
0
0
0
1
0
0
0
0
0
0
1
mod
0
0
0
mem
0
reg
0
0
0
1
0
0
0
0
0
1
1
0
0
mem
0
0
0
0
1
mod
0
0
0
1
1
0
mem16, imm4
Cy
100
1
0
1
0
0
0
1
1
0
0
0
mem
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
1
mod
0
0
0
0
0
0
0
1
mod
0
0
0
1
1
1
0
1
0
0
0
0
0
9
3·5
1
0
0
0
0
0
9/13
3·5
0
0
0
0
W
4
4
0
0
0
0
0
9
4·6
1
0
0
0
9/13
4·6
1
1
0
1
0
0
0
0
0
W
4
3
0
0
0
0
0
9
3·5
0
0
0
0
9/13
3·5
0
0
0
W
4
4
0
0
0
W
9
4·6
0
0
0
1
9/13
4-6
reg
0
0
0
1
mod
0
3
2
1
0
4
2
0
0
W
0
0
0
0
0
0
mod
0
0
0
0
0
0
0
0
0
mem
0
1
mem8,imm3
1
0
reg,CL
reg, imm3/4
1
0
1
2
0
mem
mod
1
2
reg
0
1
0
1
0
0
0
1
0
0
CIR
mem16, CL
1
mem
mod
CV
mem8, CL
1
0
CIR
CLR1
mem
1
1
mem
reg
mem
1
1
1
1
1
mem
1
0
1
2
x
V
P S Z
NEe
pPD70236 (V53)
Instruction Set (cont)
Flags
Opcode
MnemonIc
Operand
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
o
0
reg
0
0
mem
0
Clocks
Bytes
AC
CY
V
P
S
2
2-4
Z
u
x
x
x
x
x
u
x
x
x
u
x
x
u
x
x
x
x
x
u
x
Shift/Rotste Instructions
SHL
SHR
o
o
0
0
W
mem.1
0
0
0
0
W
reg. 1
1
mod
reg. CL
0
0
0
memo CL
0
0
0
1
W
reg. immS
0
0
0
0
0
WOO
memo ImmS
0
0
0
0
0
W
reg. 1
0
0
0
0
W
memo 1
0
0
0
reg. CL
0
0
0
WOO
0
W
0
mod
mod
mod
W
0
reg
mem
reg
0
0
mem
0
1
reg
0
mem
0
reg
2
7/11
2 + n
6/10 + n
2 + n
6/10 + n
2
7/11
2 + n
2
u
2-4
u
3
u
x
x
x
x
x
x
3-5
u
x
u
x
x
2
u
x
x
x
2-4
u
2
u
x
x
x
x
x
x
x
x
x
u
x
x
x
w____m_o_d_____o~______m_e_m
__~6_11_0_+
__n____2:.4____U____X___u___
x __x____
xx ~
reg
2 + nux
u x x
EM
_m_e_m_._C_L_________0___
1 __0___
0 _____
_ reg. immS
0 0 0 0 0 W
SHRA
ROL
ROR
memo immS
0
0
0
0
W
reg. 1
0
0
0
0
W
memo 1
0
0
0
0
W
reg. CL
0
0
0
memo CL
0
1
0
0
1
W
mod
0
mem· 6/10 + n
reg
mod
mem
W
reg
mod
mem
reg. ImmS
0
0
0
0
0
W
memo ImmS
0
0
0
0
0
W
reg. 1
0
0
0
0
WOO
0
reg
mem.1
0
0
0
0
W
0
mem
mod
mod
1
0
1
0
2
7/11
2 + n
6/10 + n
reg
2 + n
mem
6/10 +
2
reg. CL
0
0
0
WOO
0
reg
2 + n
0
1
0
0
W
0
0
mem
6/10 +
reg. imm
0
0
0
0
0
WOO
0
reg
2 + n
memo imm
0
0
0
0
0
W
0
mem
reg. 1
0
0
0
0
WOO
memo 1
0
0
0
0
W
reg. CL
0
0
0
0
1
W
reg. imm8
o
o
o
0
0
0
0
WOO
memo immS
o
0
0
0
0
W
reg. 1
o
0
0
0
WOO
mem.1
0
0
0
0
0
mem.CL
o
o
o
reg, imm8
o
0
0
0
0
W
mem.immS
o
0
0
0
0
W
reg. CL
mod
mod
mod
0
0
0
0
reg
0
mem
WOO
W
mod
mod
mod
0
0
0
reg
0
0
mem
reg
1
0
WOO
o 0
W
mod
mod
mem
reg
mem
reg
0
0
mem
o
o
reg
0
o
mem
n
7/11
memo CL
mem.CL
ROLC
0
n
6/10 + n
2 + n
u
x
u
x
x
2
u
x
x
2-4
u
x
o x x
o x x
2
u
x
u
x
x
x
2-4
u
x
u
x
x
3
u
x
u
x
x
3-5
u
u
x
x
x
x
x
2
x
x
2-4
x
2
2-4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3
x
u
3-5
x
u
2-4
3
3-5
2
2-4
7/11
7 + n
+n
+n
6/10 + n
6/10
2
2
2
2-4
3
3-5
2
2-4
7/11
2
3-5
+n
6/10
+n
2+n
6/10
+n
2
x
x
x
x
u
u
u
u
u
x
u
u
u
u
x
x
u
u
n = number of shifts
101
NEe
pPD70236 (V53)
Instruction Set (cont)
Flags
Opcode
Mnemonic
Operand
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Clocks
Bytes
AC
CY
V
x
x
x
x
x
x
x
x
R
R
P
S
Z
R
R
R
Shift/Rotate Instructions (cont)
RORC
reg, 1
0
0
0
0
W
1
1
0
reg
mem, 1
0
0
0
0
W
mod
0
mem
reg, CL
0
0
0
W
1
1
0
reg
mem,CL
0
0
0
1
W
mod
0
mem
reg,lmmS
0
0
0
0
0
W
1
0
reg
mem,lmmS
0
0
0
0
0
W
mod
0
mem
.1
2
2
7/11
2+n
6/10 + n
2+n
6/10 + n
n
2-4
2
2-4
3
3-5
u
u
u
u
= number of shifts
Stack Manipulation Instructions
PUSH
mem16
1
1
1
reg16
sr
0
1
0
0
0
0
0
0
PSW
POP
R
0
Imm
0
mem16
1
reg16
0
sr
0
PSW
R
PREPARE
1
1
0
0
0
0
0
0
0
0
5/9
1
0
0
3/5
0
0
0
0
0
20/36
0
S
0
mod
0
0
0
0
mem
reg
sr
0
3/5
2-3
5/9
2-4
5/7
1
5/7
1
1
0
5/7
0
0
0
22/38
0
0
0
1
0
0
0
0
2-4
3/5
1
0
*
immS~
1
mem
3/5
*immS
DiSPOSE
0
1
0
Imm16,lmmS
1
1. 0
0
0
1
reg
sr
0
0
mod
R
4
= 0:15
1: 17 + 12 QmmS -1) odd, 15 + S QmmS-1) even
6/10
1
7/9
3
Control Transfer Instructions
CALL
near_proc
0
0
0
0
reg
mod
0
0
mem
mod
0
regptr16
memptr16
faLproc
memptr32
RET
pop_value
pop_value
BR
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
shorLiabel
0
0
1
0
memptr16
memptr32
102
9/13
5
15/23
2-4
10/12
0
regptr16
mod
0
2
2-4
3
12/16
0
0
11/15
10/12
1
near_label
faLlabei
mem
7/9
0
0
reg
0
0
mem
12/16
3
7
3
7
2
7
2
11/13
7
0
mod
0
mem
13/17
2-4
5
2-4
NEe
pPD70236 (V53)
Instruction Set (cont)
Flag.
Opcode
Mnemonic
Operand
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Clock.
Byte. AC
CY
V
P
S
Z
Control Transfer Instructions (cont)
BV
shorLJabel
0
0
0
0
0
3/6
2
BNV
shorLJabel
0
0
0
0
1
3/6
2
BC,BL
shorLJabel
0
0
0
BNC, BNL
shorLJabel
0
0
0
BE,BZ
shorLJabel
0
BNE, BNZ
shorLJabel
0
BNH
shorLJabel
0
0
BH
shorLJabel
0
BN
shorLJabel
0
0
3/6
2
1
1
3/6
2
0
0
0
3/6
2
0
0
3/6
2
3/6
2
3/6
2
0
0
1
0
BP
shorLJabel
0
0
BPE
shorLJabel
0
0
BPO
shorLJabel
0
0
0
0
3/6
2
1
3/6
2
0
3/6
2
3/6
2
0
ED
Interrupt Instructions
BlT
shorLJabel
0
0
0
3/6
2
BGE
shorLJabel
0
0
1
3/6
2
BlE
shorLJabel
0
0
3/6
2
BGT
shorLJabel
0
OBNZNE
1
1
1
shorLJabel
0
0
0
0
OBNZE
shorLJabel
0
0
0
0
OBNZ
shorLJabel
0
0
0
BCWZ
shorLJabel
1
0
BRK
3
0
0
0
Imm8
0
0
0
BRKV
1
Imm8
RETI
CHKlNO
reg16, mem32
0
1
1
0
0
0
0
1
0
0
0
0
0
3/6
2
3/6
2
3/6
2
3/6
2
3/6
2
18/24
0
18/24
0
2
20/26
R
13/19
0
0
1
0
reg
mod
mem
24-26/
30-32
R
R
R
R
R
2-4
CPU Control Instructions
HALT
0
1
0
0
BUSlOCK
0
0
0
0
1
X
X
X
1
1
X
X
X
mod
Y
y
y
X
1
Y Y
Y
X
mod
Y
Y
FP01
FP02
fp_op
1
fp_op, mem
1
fp_op
0
fp_op, mem
0
1
0
1
0
POll
0
0
NOP
0
0
0
0
0
0
2
2
1
1
Y Y Y
n
0
01
0
EI
0
Z
Z
mem
Z
Z
mem
Z
*
*
*
*
2
0
0
Y
Z
0
2
2-4
2
2-4
+ 5n
= number of times POll pin Is sampled.
0
3
0
2
1
2
103
!\fEe
pPD70236 (V53)
Instruction Set (cont)
Flag.
Opcode
Mnemonic
Operand
7
6
5
4
3
7
6
5
4
3
2
1
0
Clocks
Bytes
2
1
0
1
1
0
1
1
1
1
1
1
0
0
0
0
0
12
3
1
1
1
1
1
1
1
0
0
0
0
12
3
CPU Control Instructions (cont)
050:,051:, P5:, 55:
(segment override prefixes)
0
0
1
seg
2
Address Expansion Control Instructions
BRKXA
ImmS
0
0
0
0
1
ImmS.
RETXA
ImmS
o
0
0
0
ImmS
104
1
AC
CY
V
P
S
Z
NEe
i6-Bit Microcomputers
4-1
NEe
16·Bit Microcomputers
Section 4
16-Bit Microcomputers
"PD70320/70322 (V25)
16-Bit Microcomputers:
Single-Chip, CMOS
4a
"PD70330/70332 (V35)
16-Bit Microcomputers:
Advanced, Single-Chip, CMOS
4b
"PD70P322
16-Bit Microcomputer:
Single-Chip, CMOS,
With EPROM for V25N35 Modes
4C
"PD70325 (V25 Plus)
16-Bit Microcomputer:
High-Speed DMA, Single~Chip, CMOS
4d
"PD70335 (V35 Plus)
16-Bit Microcomputer:
Advanced, High-Speed DMA,
Single-Chip, CMOS
4e
"PD70327 (V25 Software Guard)
16-Bit Microcomputer:
Software-Secure, Single-Chip, CMOS
4f
"PD70337 (V35 Software Guard)
16-Bit Microcomputer:
Software-Secure, Single-Chip, CMOS
4g
"PD79011
16-Bit Microcomputer:
Single-Chip, CMOS, With Bui It-In RTOS
4h
"PD79021
16-Bit Microcomputer:
Single-Chip, CMOS, With Bui It-In RTOS
4i
4-2
NEe
NEe Electronics Inc.
Description
The tJPD70320 and tJPD70322 (V25™) are high-performance, 16-bit, single-chip microcomputers with an
8-bit external data bus. They combine the instruction
set of the tJPD70108 (V20®) with many of the on-chip
peripherals in NEC's 78000 series.
The tJPD70320/322 processor has software compatibility with the V20 (and subsequently the 8086/8088),
faster memory accessing, superior interrupt processing
ability, and enhanced control of internal peripherals.
A variety of on-chip components, including 16K bytes
of mask programmable ROM (tJPD70322 only), 256
bytes of RAM, serial and parallel I/O, comparator port
lines, timers, and a DMA controller make thetJPD70320/
322 a sophisticated microsystem.
Eight banks of registers are mapped into internal RAM
below an additional 256-byte special function register
(SFR) area that is used to control on-chip peripherals.
I nternal RAM and the SFR area are together relocatable
to anywhere in the 1M-byte address space. This
maintains compatibility with existing system memory
maps.
ThetJPD70322 is the mask ROM version, thetJPD70320
is the ROM-less version, and the tJPD70P322 is the
EPROM version.
pPD70320/70322 (V25)
is-Bit Microcomputers:
Single-Chip, CMOS
o DRAM refresh pulse output
o Two standby modes
o
o
o
o
-HALT
-STOP
Internal clock generator
- 5-MHz maximum CPU clock frequency (O.4-tJs
instruction cycle time)
- 8-MHz maximum CPU clock frequency (0.25-tJs
instruction cycle time)
Programmable wait state generation
Separate address/data bus interface
CMOS technology
Ordering Information
Part Number
Clock IMHz)
Package Type
ROM
pPD70320L
5
84-pin PLCC
ROM-less
8
PLCC
-16-bit ALU
- 16K bytes of ROM (tJPD70322)
- 256 bytes of RAM
6-byte instruction prefetch queue
24 parallel 110 lines
Eight analog comparator inputs with programmable
threshold level
Two independent DMA channels
Two 16-bit timers
Programmable time base counter
Two full-duplex UARTs
Programmable interrupt controller
- Eight priority levels
- Five external, 12 internal sources
- Register bank (eight) context switching
- Eight macro service function channels
V20 is a registered trademark and V25 is a trademark of NEC Corporation.
5
L-8-xxx
8
GJ-xxx
5
GJ-8-xxx
o Complete single-chip microcomputer
50002-2INECEL-583l
GJ-8
pPD70P322KE-8
Features
o
o
o
o
o
8
5
pPD70322L-xxx
LCC
o
o
o
L-8
GJ
1m
94-pin plastic QFP
84-pin PLCC
Mask ROM
94-pin plastic QFP
8
8
84-pin LCC
= plastic leaded chip carrier
= ceramic leadless chip carrier (with window)
EPROM
(UV erasable)
NEe
pPD70320/322 (V25)
Pin Configurations
84-Pln PLCC and LCe
P07/CLKOUT
74
PT7
DO
73
PT6
01
72
PT5
02
71
PT4
03
70
PT3
04
69
PT2
05
68
PT1
Os
67
PTO
07
66
P17/REAOY
Ao
65
P16/SCKO
A1
64
P15/TOUT
A2
63
P14/1NT/POLL
A3
62
P13/1NTP2/1NTAK
A4
61
P12/1NTP1
A5
60
P11/1NTPO
As
59
P10/NMI
A7
58
P27/HLORO
A8
57
P2s/HLOAK
Ag
56
P25/TC1
A10
55
P24/0MAAK1
A11
54
P23/0MAR01
~
M
~
~
~
~
~
~
0
.;.;.;.;.;.;.;.;~
o
e
01z t) 0 '-1'-
a: Cl
0
0
I/)
I/)
>C
I-
>c
I-
a: 0
>c
I-
100
"0
T
Q,
Q,
0
0
a:
0""
~
N
S! c
~
> ::
~
S!
t:
I:t
~~
N
'Pin functions for normal operation of the pP070P322
are changed as follows for programming.
Pin No.
3
Symbol
Vpp
45
OE
46
CE
Function
Write power supply input
Output enable signal
input
Chip enable signal input
83-0039608
2
~
I
!~
'b
ii'
fI)
::!:
(')
"C
"C
~ ~I>
~>
N;!:;
~
I~
;!:;
< <
~ 0
~ ~ 0
~ ~
~
~
01~Z~CC_~O~OO~ZO~~~~~~~Z~
0 c e o 0 ......1. . 0 01 0
0
C
CD
Q)
....
en
U1
....
...
0
'"
DDDDDDDDDDDDDDDDD[
N N N N
W
N
~
0
~
~
~
~
~
~
~
m
~
~
~
~
~
W
~
N
~
~
~
0
IC
24
P23/0MAR01
25
P24/0MAAK1
26
NC
P2s/TC1
27
A10
A11
91
P26/HLOAK
28
P27/HLORO
29
AS
P10/NMI
30
A7
P11/1NTPO
31
A6
P12/1NTP1
32
AS
P13/1NTP2/1NTAK
33
A4
P14/1NT/POLL
34
A3
P1s/TOUT
35
A2
P16/SCKO
36
A1
P17/REAOY
37
PTO
38
PT1
39
06
PT2
40
Os
PT3
41
D4
PT4
42
D3
PT5
43
D2
NC
44
D1
PT6
45
DO
PT7
46
P07/CLKOUT
IC
47
A9
AD
81
07
P06
....
m
....
W
U1
0
U1
~
U1
N
U1
W
U1
~
U1
~
U1
m
U1
~
=
U1
U1
W
< Z Z ~ ~ x x < < ~I ~I ~
:i
0
0
Z Z ... N
c c
g g rn
~
~ ~
=el
m m m m m m m m m m .... ....
0
~
(J)
m
~
ill
ml"C"C"C"C"C
;!:;151;!:;1
~
m
N
m ~ 0
~
~
~
> 8 !: ~ 8 ~
W
0
~
n 0Z"C&
't:
"a--a
0
W
~
0
'W
~
~
........
<
~
u.:>
l'"
------
- -
m
(II
......,.
NEe
pPD70320/322 (V25)
Pin Identification
Pin Functions
Symbol
Function
Address bus outputs
CLKOUT
System clock output
Ao-A19 [Address Bus]
Ao-A19 is the 20-bit address bus used to access all
external devices.
CTSO
Clear to send channel 0 input
CTS1
Clear to send channel 1 input
CLKOUT [System Clock]
Bidirectional data bus
This is the internal system clock. It can be used to
synchronize external devices to the CPU.
EA
External access
10STB
I/O strobe output
MREQ
Memory request output
MSTB
Memory strobe output
I/O port 0
P10/NMI
P13/INTP2/INTAK
Port 1 input line/Nonmaskable
interrupt input
P16/SCKO
P20/DMARQO
Do- D7 [Data Bus]
Port 1 input line/External
interrupt input line/Interrupt
acknowledge output
0 0-0 7 is the 8-bit external data bus.
I/O port 1/Timer out
These are the control signals to and from the on-chip
OMA controller.
I/O port 1/Serial clock out
EA [External Access]
I/O port 2/DMA request 0
If this pin is low on reset, the pP070322 will execute
program code from external memory instead of from
internal ROM.
I/O port 2/DMA terminal count 0
I/O port 2/DMA request 1
I/O port 2/DMA acknowledge 1
P26/HLDAK
DMARQn, DMAAKn, TCn [DMA Request, DMA
Acknowledge, Terminal Count]
I/O port 1/Ready input
I/O port 2/DMA acknowledge 0
P25ITC1
Receive Data, Transmit Data, Serial Clock Out]
The two serial ports (channels 0 and 1) use these lines
for transmitting and receiving data, handshaking, and
serial clock output.
Port 1 input lines/External
interrupt input lines
I/O port 1/Interrupt request input/
I/O poll input
P15/TOUT
------CTSn, RxDn, TxDn, SCKO [Clear to Send,
I/O port 2/DMA terminal count 1
HLDAK [Hold Acknowledge]
The HLOAK output (active low) informs external
devices that the CPU has released the system bus.
I/O port 2/Hold acknowledge output
I/O port 2/Hold request input
HLDRQ [Hold Request]
PTO-PT7
Comparator port input lines
REFRQ
Refresh pulse output
The HLORO input (active high) is used by external
devices to request the CPU to release the system bus to
an external bus master. The following lines go into a
high-impedance state with internal 4.7-kO pullup
resistors: Ao-A19, 00-07, MREO, R/W, MSTS, REFRO,
and IOSTS.
RESET
Reset input
RxDO
Serial receive data, channel 0 input
RxD1
Serial receive data, channel 1 input
R/W
Read/Write output
TxDO
Serial transmit data, channel 0 output
TxD1
Serial transmit data, channel 1 output
X1,X2
Crystal connection terminals
VDD
Positive power supply voltage
Threshold voltage input
GND
Ground
IC
Internal connection
4
NEe
pPD70320/322 (V25)
INT [Interrupt Request]
POLL [Poll]
INT is a maskable, active-high, vectored interrupt
request input. After assertion, external hardware must
provide the interrupt vector number.
Upon execution of the POLL intruction, the CPU
checks the status of this pin and, if low, program
execution continues. If high, the CPU will check the
level of the line every five clock cycles until it is low.
POLL can be used to synchronize program execution
to external conditions.
INTAK [Interrupt Acknowledge]
After INT is asserted, the CPU will respond with INTAK
(active low) to inform external devices that the interrupt
request has been granted.
PTO-PT7 [Comparator Port]
PTO-PT7 are inputs to the analog comparator port.
INTPO-INTP2 [External Interrupt]
INTPO-INTP2 allow external devices to generate interrupts. Each can be programmed to be rising or falling
edge triggered.
10STB [I/O Strobe]
10STB is asserted during read and write operations to
external 1/0.
MREQ [Memory Request]
MREQ (active low) informs external memory that the
current bus cycle is a memory access bus cycle.
MSTB [Memory Strobe]
MSTB (active low) is asserted during read and write
operations to external memory.
NMI [Nonmaskable Interrupt]
NMI cannot be masked through software and is typically used for emergency processing. Upon execution,
the interrupt starting address is obtained from interrupt
vector number 2. NMI can release the standby modes
and can be programmed to be either rising or falling
edge triggered.
POO-P07 [Port 0]
POO-P07 are the lines of port 0, an 8-bit bidirectional
parallel I/O port.
P1o-P17 [Port 1]
The status of P1 O-P13 can be read but these lines are
always control functions. P14-P17 are the remaining
lines of parallel port 1, each line individually programmable as either an input, an output, or a control
function.
P2o-P27 [Port 2]
P2o-P27 are the lines of port 2, an 8-bit bidirectional 1/0
port. The lines can also be used as control signals for
the on-chip DMA controller.
READY [Ready]
After READY is de-asserted low, the CPU will synchronize and insert at least two wait states into a read or
write cycle to memory or 1/0. This allows the processor
to accommodate devices whose access times are
longer than normal execution allows.
REFRQ [Refresh]
This active-low output pulse can refresh nonstatic
RAM. It can be programmed to meet system specifications and is internally synchronized so that refresh
cycles do not interfere with normal CPU operation.
RESET [Reset]
A low on RESET resets the CPU and all on-chip
peripherals. RESET can also release the standby
modes. After RESET returns high, program execution
begins from address FFFFOH.
R/W [Read/Write]
An R/W output allows external hardware to determine
if the current operation is a read or write cycle. It can
also control the direction of bidirectional buffers.
TOUT [Timer Out]
TOUT is the square-wave output signal from the
internal timer.
X1, X2 [Crystal Connections]
The internal clock generator requires an external
crystal across these terminals as shown in figure 36.
By programming the PRC register, the system clock
frequency can be selected as the oscillator frequency
(fosd divided by 2, 4, or 8.
Voo [Power Supply]
Two positive power supply pins (VDD) reduce internal
noise.
5
NEe
pPD70320/322 (V25)
VTH [Threshold Voltage]
GND
The comparator port uses this pin to determine the
analog reference point. The actual threshold to each
comparator line is programmable to VTH x n/16, where
n 1 to 16.
Two ground connections reduce internal noise.
=
IC [Internal Connection]
Allie pins should be together and pulled up to VDD with
a 10K-20K resistor.
Block Diagram
Staging
Latch
P20/DMARQO
P21/DMAAKO
P22/TCO
P23/DMARQ1
P24/DMAAK1
P25/TC1
Staging
Latch
A19-AO
TxDO
RxDO
P16/SCKOCTSO
TxD1
RxD1
RESET
HLDAK/P26
HLDRQ/P27
READY/P17
MSTB
P10/NMI
P11/1NTPO
P1211NTP1
P13I1NTP2IINTAK
P1411NT/POLL
• Macro
Service
Channel
Instruction Decoder
Micro Sequencer
Micro ROM
X1-
Clock
Generator
POLLIINT/P14
X2-
TOUT/P15
REFRQ
CLKOUT/P07
83-001993C
6
NEe
pPD70320/322 (V25)
Functional Description
Architectural Enhancements
The following features enable the pPD70320/322 to
perform high-speed execution of instructions:
• Dual data bus
• 16-/32-bit temporary registers/shifters (TA, TB,
TA+TB)
• 16-bit loop counter (LC)
• Program counter (PC) and prefetch pointer (PFP)
• Internal ROM pass bus (pPD70322 only)
Dual Data Bus. The pPD70320/322 has two internal
16-bit data buses: the main data bus and a subdata bus.
This reduces the processing time required for addition/
subtraction and logical comparison instructions by
one-third over single-bus systems. The dual data bus
method allows two operands to be fetched simultaneously from the general-purpose registers and
transferred to the ALU.
16-/32-Bit Temporary Registers/Shifters. The 16-bit
temporary registers/shifters (TA, TB) allow high-speed
execution of multiplication/ division and shift/rotation
instructions. By using the temporary registers/shifters,
the pPD70320/322 can execute multiplication/division
instructions about four times faster than with the
microprogramming method.
Figure 1.
Loop Counter [LC1. The dedicated hardware loop counter
counts the number of loops for string operations and
the number of shifts performed for multiple bit shift/
rotation instructions. The loop counter works with
internal dedicated shifters to speed the processing of
multiplication/division instructions.
Program Counter and Prefetch Pointer [PC and PFP1.
The hardware PC addresses the memory location of
the instruction to be executed next. The hardware PFP
addresses the program memory location to be accessed
next. Several clocks are saved for branch, call, return,
and break instructions compared with processors
having only one instruction pointer.
Internal ROM Pass Bus. The pPD70322 features a
dedicated data bus between the internal ROM and the
instruction pre-fetch queue. This allows internal ROM
opcode fetches to be performed in a single clock cycle
(200 ns at 5 MHz); it also makes it possible for opcode
fetches to be performed while the external data bus is
busy. This feature gives the V25 a 10-20% performance
increase when executing from the internal ROM.
Register Set
Figure 1 shows the pPD70320/322 has eight banks of
registers functionally mapped into internal RAM. Each
bank contains general-purpose registers, pointer and
index registers, segment registers, and save areas.
Register Banks in Internal RAM
AW
XXFOOH
XXEFEH
Bank 7
CW
CH
Data Register
DW
32 bytes
AH
XXEEOH
BW
XXEF8H
Bank 6
SP
6H
BP
XXECOH
4H
Index Register
IX
2H
IV
XXEFOH
~
DS1
EH
PS
Segment Register
CH
SS
XXE40H
AH
DSO
Bank1
XXEE8H
Save PC
6H
XXE20H
SavePSW
4H
BankO
XXEOOH
Vector PC
2H
XXEEOH
Reserved
Internal RAM
49-001342B
7
III
NEe
pPD70320/322 (V25)
General-Purpose Registers [AW, BW, CW, OW]. There
are four 16-bit g~neral-purpose registers that can each.
serve as individual 16-bit registers or two independent
a-bit registers (AH, AL, BH, BL, CH, CL, DH, DL). The
following instructions use the general-pu rpose registers
for default:
AW
AL
Word multiplication/division, word I/O, data
conversion
Byte multiplication/division, byte I/O, BCD
rotation, data conversion, translation
AH
Byte multiplication/division
Program Counter [PC]. The PC is a 16-bit binary
counter that contains the offset ad.dress from the
program segment of the next instruction to be executed.
It is incremented every time an instruction is received
from the queue. It is loaded with a new location
whenever a branch, call, return, break, or interrupt is
executed.
Program Status Word [PSW]. The PSW contains the
following status and control flags.
RB2
I RB1
BW
Translation
7
CW
Loop control branch, repeat prefix
I
CL
Shift instructions, rotation instructions, BCD
operations
Status Flags
DW
Word multiplication/division, indirect addressing I/O
V
Overflow bit
S
Sign
. Pointers [SP,BP] and Index Registers [IX, IV]. These
registers are used as 16-bit base pointers or index
registers in based addressing, indexed addressing,
and based indexed addressing. The registers are used
as default registers under the following conditions:
Z
Zero
SP
Stack operations
IX
Block transfer (source), BCD string operations
IY
Block transfer (destination), BCD string
operations
Segment Registers. The segment registers divide the
1M-byte address space into 64K-byte blocks. Each
segment register functions as a base address to a
block; the effective address is an offset from that base.
Physical addresses are generated by shifting the associated segment register left four binary digits and then
adding the effective address. The segment registers
are:
Segment Register
PS (Program segment)
SS (Stack segment)
DSO (Data segment-O)
DS1 (Data segment-1)
Default Offset
PC
SP, Effective address
IX, Effective address
. IY, Effective address
Save Registers. Save PC and Save PSW are used as
save areas during register bank context switching. The
Vector PC save location contains the effective address
of the interrupt service routine when register bank
switching is used to service interrupts.
a
a
PSW
15
RBO
I
V
I
DIR
IE
BRK
p
I BRKI I
CY
I
o
s I z I
F1
AC Auxiliary carry
P
Parity
CY
Carry
FO
AC
I
Control Flags
DIR
Direction of string
processing
IE
Interrupt enable
BRK
Break (after every
instruction)
RBn
Current register
bank flags
BRKI
I/O trap enable (see
software interrupts)
FO, F1 General-pu rpose
user flags (accessed
through the Flag
special function
register)
The eight low-order bits of the PSW can be stored in
the AH register and restored by a MOV instruction
execution. The only way to alter the RBn bits via
software is to execute an RETRBI or RETI instruction.
NEe
pPD70320/322 (V25)
Memory Map
The jlPD70320/322 has a 20-bit address bus that can
directly access 1M bytes of memory. Figure 2 shows that
the 16K bytes of internal ROM (JIPD70322 only)
are located at the top of the address space from FCOOOH
to FFFFFH.
Figure 2 shows the internal data area (IDA) is a 256byte internal RAM area followed consecutively by a
256-byte special function register (SFR) area. All the
data and control registers for on-chip peripherals and
1/0 are mapped into the SFR area and accessed as
RAM. For a description of these functions, see table 6.
The IDA is dynamically relocatable in 4K-byte increments by changing the value in the internal data base
(IDB) register. Whatever value is in this register will be
assigned as the uppermost eight bits of the IDA
address. The IDB register can be accessed from two
different memory locations, FFFFFH and XXFFFH,
where XX is the value in the IDB register.
On reset, the internal data base register is set to FFH
which maps the IDA into the internal ROM space.
However, since the jlPD70322 has a separate bus to
internal ROM, this does not present a problem. When
these address spaces overlap, program code cannot be
executed from the IDA and internal ROM locations
cannot be accessed as data. You can select any of the
eight possible register banks, which occupy the entire
internal RAM space. Multiple register bank selection
allows faster interrupt processing and facilitates multitasking.
Figure 2.
Memory Map
Instruction Set
The jlPD70320/322 instruction set is fully compatible
with the V20 native mode instruction set. The V20
instruction set is a superset of the jlPDBOB61BOBB
instruction set with different execution times and
mnemonics.
The jlPD70320/322 does not support the V20 BOBO
emulation mode. All of the instructions pertaining to
this have been deleted from the jlPD70320/322 in- ~
struction set.
~
Enhanced Instructions
In addition to the jlPDBOB6/88 instructions, the
jlPD70320/322 has the following enhanced instructions.
I nstruction
FCOOOH
/
XXFFFH
XXFOOH
External
Area
XXEFFH
XXEOOH
t---------/
Special Function
Registers
1-[256 Bytes]
1/"
Internal RAM
[256 Bytes]
Pushes immediate data onto stack
PUSH R
Pushes eight general registers onto
stack
POP R
Pops eight general registers from stack
MUL imm
Executes 16-bit multiply of register or
memory contents by immediate data
Shifts/rotates register or memory by
SHL immB
immediate value
SHR immB
SHRA immB
ROL immB
ROR immB
ROLC immB
RORC immB
CHKIND
Checks array index against designated
boundaries
INM
Moves a string from an 1/0 port to
memory
OUTM
Moves a string from memory to an 1/0
port
PREPARE
Allocates an area for a stack frame and
copies previous trame pOinters
DISPOSE
Frees the current stack frame on a
procedure exit
,-
OOOOOH
1 Mbyte Memory Space
Function
PUSH imm
FFFFFH
Internal
ROM
......-----1
In larger-scale systems where internal RAM is not
required for data memory, the internal RAM can be
removed completely from the address space and
dedicated entirely to registers and control functions
such as macro service and DMA channels. Clearing the
RAMEN bit in the processor control register achieves
this. When the RAMEN bit is cleared, internal RAM can
only be accessed by register addressing or internal
control processes. Many instructions are executed
faster when the internal RAM is disabled.
49-001343A
9
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pPD70320/322 (V25)
Unique Instructions
effective forgraphics, high-level languages, and packingl
unpacking applications.
The pPD70320/322 has the following unique
instructions.
Bit field insertion copies the bit field of specified length
from the AW register to the bit field addressed by
DS1 :IV:reg8 (8-bit general-purpose register). The bit
field length can be located in any byte register or
supplied as immediate data. Following execution, both
the IV and reg8 are updated to point to the start of the
next bit field.
Instruction Function
INS
Inserts bit field
EXT
Extracts bit field
ADD4S
Performs packed BCD string addition
SUB4S
Performs packed BCD string subtraction
CMP4S
Performs packed BCD string
comparison
ROL4
Rotates BCD digit left
ROR4
Rotates BCD digit right
TEST1
Tests bit
SET1
Sets bit
CLR1
Clears bit
Bit field extraction copies the bit field of specified
length from the bit field addressed by DSO:IX:reg8 to
the AW register. If the length of the bit field is less than
16 bits, the bit field is right justified with a zero fill. The
bit field length can be located in any byte register or
supplied as immediate data. Following execution, both
IX and reg8 are updated to point to the start of the next
bit field.
Figures 3 and 4 show bit field insertion and bit field
extraction.
NOT1
Complements bit
BTCLR
Tests bit; if true, clear and branch
REPC
Repeat while carry set
REPNC
Repeat while carry cleared
Packed Be 0 Instructions
Packed BCD instructions process packed BCD data
either as strings (ADD4S, SUB4S, CMP4S) or byte
format operands (ROR4, ROL4). Packed BCD strings
may be 1 to 254 digits in length. The two BCD rotation
instructions perform rotation of a single BCD digit in
the lower half of the AL register through the register or
the memory operand.
Variable Length Bit Field Operation Instructions
Bit fields are a variable length data structure that can
range in length from 1 to 16 bits. The pPD70320/322
supports two separate operations on bit fields: insertion
(INS) and extraction (EXT). There are no restrictions
on the position of the bit field in memory. Separate
segment, byte offset, and bit offset registers are used
for insertion and extraction. Following the execution of
these instructions, both the byte offset and bit offset
are left pointing to the start of the next bit field, ready
for the next operation. Bit field operation instructions
are powerful and flexible and are therefore highly
Figure 3.
Bit Manipulation Instructions
The pPD70320/322 has five unique bit manipulation
instructions. The ability to test, set, clear, or complement a single bit in a register or memory operand
increases code readability as well as performance over
the logical operations traditionally used to manipulate
bit data. This feature further enhances control ove,r
on-chip peripherals.
Bit Field Insertion
Bit length
15
o
AW
Bit offset
Memory
Byte boundary
Segment base (OS1)
83-0001068
10
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Figure 4.
pPD70320/322 (V25)
Bit Field Extraction
Bit length
Bit offset
Byte boundary
Segment base (OSO)
83-000107B
Additional Instructions
Table 2.
Besides the V20 instruction set, the pPD70320/322
has the four additional instructions described in
table 1.
Instruction
Function
BRKCS reg 16
Performs a high-speed software interrupt with
context switch to the register bank indicated by the
lower 3-bits of reg 16. This operation is identical to
the interrupt operation shown in figure 9.
Table 1.
Additionallnstructions
Instruction
Function
BTCLR var,immB,
short label
Bit test and if true, clear and branch;
otherwise, no operation
STOP (no operand)
Power down instruction, stops oscillator
RETRBI (no operand)
FINT (no operand)
Bank Switch Instructions
TSKSW reg 16
Return from register bank context switch
interrupt
Performs a high-speed task switch to the register
bank indicated by the lower 3-bits of reg 16. The PC
and PSW are saved in the old banks. PC and PSW
save registers and the new PC and PSW values are
retrieved from the new register bank's save areas.
See figure 10.
MOVSPA
Finished interrupt. After completion of a
hardware interrupt request, this instruction
must be used to reset the current priority
bit in the in-service priority register (ISPR). *
Transfers both the SS and SP of the old register
bank to the new register bank after the bank has
been switched by an interrupt or BRKCS instruction.
MOVSPB
Transfers the SS and the SP of the current register
bank before the switch to the SS and SP of the new
register bank indicated by the lower 3-bits of reg 16.
*00 not use with NMI or INTR interrupt service routines.
Repeat Prefixes
Two new repeat prefixes (REPC, REPNC) allow conditional block transfer instructions to use the state of
the CY flag as the termination condition. This allows
inequalities to be used when working on ordered data,
thus increasing performance when searching and
sorting algorithms.
Table 3.
Software Interrupts
Interrupt
Description
Divide error
The CPU will trap if a divide error occurs as the
result of a DIV or DIVU instruction.
Single step
The interrupt is generated after every instruction if
the BRK bit in the PSW is set.
Overflow
By using the BRKV instruction, an interrupt can be
generated as the result of an overflow.
Interrupt
instructions
The BRK 3 and BRK immB instructions can generate interrupts.
Array bounds
The CHKIND instruction will generate an interrupt if
specified array bounds have been exceeded.
Escape trap
The CPU will trap on an FP01,2 instruction to allow
software to emulate the floating point processor.
I/O trap
If the I/O trap bit in the PSW is cleared, a trap
will be generated on every IN or OUT instruction.
Software can then provide an updated peripheral
address. This feature allows software interchangeability between different systems.
Bank Switch Instructions
The V25 has four new instructions that allow the
effective use of the reg ister ban ks for software i nterru pts
and multitasking. These instructions are shown in
table 2. Also, see figures 8 and 10.
Interrupt Structure
The pPD70320/322 can service interrupts generated
both by hardware and by software. Software interrupts
are serviced through vectored interrupt processing.
See table 3 for the various types of software interrupts.
11
II
~.
NEe
pPD70320/322 (V25)
When executing software written for another system, it
is better to implement I/O with on-chip peripherals to
reduce external hardware requirements. However,
since pPD70320/322 internal peripherals are memory
mapped, software conversion could be difficult. The
1/0 trap feature allows easy conversion from external
peripherals to on-chip peripherals.
Table 4.
Address
Interrupt Vectors
Vector No.
Assigned Use
0
Divide error
08
2
NMI
BRK3 instruction
00
04
Break flag
OC
3
Interrupt Vectors
10
4
BRKV instruction
The starting address of the interrupt processing
routines may be obtained from table 3. The table
begins at physical address OOH, which is outside the
internal ROM space. Therefore, external memory is
required to service these routines. By servicing interrupts via the macro service function or context
switching, this requirement can be eliminated.
14
5
CHKIND instruction
General purpose
18
6
1C
7
FPO instructions
20-2C
8-11
General purpose
30
12
INTSERO (Interrupt serial error, channel 0)
34
13
INTSRO (Interrupt serial receive, channel 0)
Each interrupt vector is four bytes wide. To service a
vectored interrupt, the lower addressed word is transferred to the PC and the upper word to the PS.
See figure 5.
38
14
INTSTO (Interrupt serial transmit, channel 0)
3C
15
General purpose
40
16
INTSER1 (Interrupt serial error, channel 1)
44
17
INTSR1 (Interrupt serial receive, channel 1)
Figure 5.
48
18
INTST1 (Interrupt serial transmit, channel 1)
4C
19
1/0 trap
50
20
INTDO (Interrupt from DMA, channel 0)
54
21
INTD1 (Interrupt from DMA, channel 1)
Interrupt Vector 0
Vector 0
OOOH
002H
:
I
00lH
003H
PS <- (OO3H, 002H)
PC <- (OO1H, OOOH)
83-000112A
Execution of a vectored interrupt occurs as follows:
(SP-1, SP-2) - PSW
(SP-3, SP-4) - PS
(SP-5, SP-6) - PC
. SP +- SP-6
IE-O,BRK-O
PS +- vector high bytes
PC - vector low bytes
Hardware Interrupt Configuration
The V25 features a high-performance on-chip controller capable of controlling multiple processing for
interrupts from up to 17 different sources (5 external,
12 internal). The interrupt configuration includes
system interrupts that are functionally compatible with
those of the V20IV30 and unique high-performance
microcontroller interrupts.
12
58
22
General purpose
5C
23
General purpose
60
24
INTPO (Interrupt from peripheral 0)
64
68
25
INTP1 (Interrupt from peripheral 1)
26
INTP2 (Interrupt from peripheral 2)
6C
27
General purpose
70
28
INTTUO (Interrupt from timer unit 0)
74
29
INTTU1 (Interrupt from timer unit 1)
78
30
INTTU2 (Interrupt from timer unit 2)
7C
31
INTTB (Interrupt from time base counter)
080-3FF
32-255
General purpose
NEe
pPD70320/322 (V25)
Interrupt Sources
The 17 interrupt sources (table 5) are divided into
groups for management by the interrupt controller.
Using software, each of the groups can be assigned a
priority from 0 (highest) to 7 (lowest). The priority of
individual interrupts within a group is fixed in hardware.
If interrupts from different groups occursimultaneously
and the groups have the same assigned priority level,
the priority followed will be as shown in the Default
Priority column of table 5.
The ISPR is an .8-bit special function register; bits
PRo-PR7 correspond to the eight possible interrupt
request priorities. The ISPR keeps track of the priority
of the interrupt currently being serviced by setting the
appropriate bit. The address of the ISPR is X;XFFCH.
The ISPR format is shown below.
NMI and INTR are system-type external vectored
interrupts. NMI is not maskable via software. INTR is
maskable (IE bit in PSW) and requires that an external
device provide the interrupt vector number. It allows
expansion by the addition of an external interrupt
controller (j.tPD71059).
Figure 6.
Table 5.
Interrupt Sources
Interrupt Source
(Priority Within Group)
Group
1
2
3
Default
Priority
Non-maskabie interrupt
NMi
Timer unit
iNTTUO INTTU1
0
DMA controller
INTDO
INTD1
External peripheral
interrupt
iNTPO
iNTP1
Serial channel 0
INTSERO INTSRO INTSTO
4
Seriai channel 1
iNTSER1 INTSR1
Time base counter
INTTB
interrupt request
INTR
5
6
7
INTTU2
1
2
INTP2
INTST1
3
II
Interrupt Mode Register (INTM)
I
0
5
6
7
INTM
NMI, INTPO, and INTP1 are edge-sensitive interrupt
inputs. By selecting the appropriate bits in the interrupt
mode register, these inputs can be programmed to be
either rising or falling edge triggered. ESO-ES2 correspond to INTPO-INTP2, respectively. See figure 6.
I
ES2
I
0
4
I
ES,
I
0
o
2
3
I
ESo
I
0
I
ES
NMI
Trigger Mode
0
Falling Edge
1
Rising Edge
0
Falling Edge
1
Rising Edge
0
Falling Edge
1
Rising Edge
0
Falling Edge
1
Rising Edge
49-0013826
13
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pPD70320/322 (V25)
Interrupt Processing Modes
Register Bank Switching
Interrupts, with the exception of NMI, INT, and INTTB,
have high-performance capability and can be processed in any of three modes: standard vector interrupt, register bank context switching, or macro service
function. The processing mode for a given interrupt
can be chosen by enabling the appropriate bits in the
corresponding interrupt request control register. As
shown in table' 6, each individual interrupt, with the
exception oflNTR and NMI, has its own associated IRC
register. The format for all IRC registers is shown in
figure 7.
Register bank context switching allows interrupts to be
processed rapidly by switching register banks. After an
interrupt, the new register bank selected is that which
has the same register bank number (0-7) as the priority
of the interrupt to be serviced. The PC and PSWare
automatically stored in the save areas of the new
register bank and the address of the interrupt routine is
loaded from the vector PC storage location in the new
register bank. As in the vectored mode, the IE and BRK
bits in the PSW are cleared to zero. After interrupt
processing, execution of the RETRBI(return from
register bank interrupt) returns control to the former
register bank and restores the former PC and PSW.
Figures 8 and 9 show register bank context switching
and register bank return.
All interrupt processing routines other than those for
NMI and INT must end with the execution of an FINT
instruction. Otherwise, subsequently, only interrupts
of a higher priority will be accepted.
In the vectored interrupt mode, the CPU traps to the
vector location shown in table 4.
Figure 7.
Interrupt Request Control Registers (lRC)
7
IRC
I
FLAG
I
MASK
I
MSI
INT
I
ENCS
I
0
I
PR2
I
I I
PR1
PRo
I
PR
2 1 0
Priority
000
Highest
1 1 1
Lowest
ENCS
Context Switch
..
0
Vectored Interrupt Mode
1
Bank Switching
MS/INT
0
Macro Service or Interrupt
Interrupt
1
Macro Service
xxMKn
Interrupt Mask
0
1
xxFn
Mask Open: Interrupts Enabled
Mask Closed: Interrupts Disabled
Interrupt Request Flag
0
No Request
1
Interrupt Requested
49-0013838
14
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Figure 8.
pPD70320/322 (V25)
Register Bank Context Switching
RBi
Macro Service Function
The macro service function (MSF) is a special microprogram that acts as an internal DMA controller between on-chip peripherals (special function registers,
SFR) and memory. The MSF greatly reduces the
software overhead and CPU time that other processors
would require for register save processing, register
returns, and other handling associated with interrupt
processing.
RBj
AW
AW
CW
CW
DW
DW
BW
BW
SP
SP
c)
BP
IX
BP
IX
IV
IV
DS1
DS1
PS
PS
SS
SS
DSO
DSO
~
Save PC
r-- ~
SavePSW
If the MSF is selected for a particular interrupt, each
time the request is received, a byte or word of data will
be transferred between the SFR and memory without
interrupting the CPU. Each time a request occurs, the
macro service counter is decremented. When the
counter reaches zero, an interrupt to the CPU is
generated. The MSF also has. a character search
option. When selected, every byte transferred will be
compared to an a-bit search character and an interrupt
will be generated if a match occurs or if the macro
service counter counts out.
Save PC
SavePSW
Vector PC
Vector PC
Reserved
Reserved
t--
r--
y
Y
Like the NMI, INT and INTTB, the two DMA controller
interrupts (INTDO, INTD1) do not have MSF capability.
PC
PSW
49-001344A
Figure 9.
Register Bank Return
RBi
RBj
AW
AW
CW
CW
DW
DW
BW
BW
SP
SP
BP
BP
0
IX
IV
There are eight a-byte macro service channels mapped
into internal RAM from XXEOOH to XXE3FH. Each
macro service channel contains all of the necessary
information to execute the macro service process.
Figure 11 shows the components of each channel.
Figure 10.
Task Switching
CURRENT
IX
NEW
AW
AW
cw
CW
DW
DW
BW
BW
SP
IV
SP
[)
BP
BP
DS1
DS1
PS
PS
IX
IX
SS
SS
IV
IV
DSO
DSO
DS1
DS1
Save PC
r---
SavePSW
r--
-
Save PC
SavePSW
Vector PC
Vector PC
Reserved
Reserved
~
PS
SS
SS
DSO
~
.-1-
Lr
PS
PC
r--
PC Save
PSWSave
-
PSWSave
VPC
VPC
Reserve
Reserve
y
PSW
49-001346A
DSO
PC Save
L-{
PC
PSW
RBL
j.-
IReg 16
VPC: Vector PC
RB: Register ba nk field
83-MBOOS273A
15
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pPD70320/322 (V25)
Figure 11.
On-Chip Peripherals
Macro Service Channels
Timer Unit
t
The tlPD70320/322 (figure 13) has two programmable
16-bit interval timers (TMO, TM1) on-chip, each with
variable input clock frequencies. Each of the two 16-bit
timer registers has an associated 16-bit modulus
register (MDO, MD1). Timer 0 operates in the interval
timer mode or one-shot mode; timer 1 has only the
interval timer mode.
Upt03FH
XXE08H
MSS
M.S. Channel 0
MSP
Resl'lvcci
SFRP
I
SCHR
MSC
1
Interval Timer Mode. In this mode, TMO/TM1 are
decremented by the selected input clock and, after
counting out, the registers are automatically reloaded
from the modulus registers and counting continues.
Each time TM1 counts out, interrupts are generated
through TF1 and TF2 (Timer Flags 1, 2). When TMO
counts out, an interrupt is generated through TFO.
The timer-out signal can be used as a square-wave
output whose half-cycle is equal to the count time.
There are two selectable input clocks (SCLK: system
clock = fosc/2; fosc = 10 MHz).
XXEOOH [Internal RAM]
~16Bits-l
MSS
= Macro service segment
MSP
= Macro service pointer
SCHR = Search character
SFRP = Special function register pOinter
MSC = Macro service counter
49-001345A
Clock
Setting the macro service mode for a given interrupt
requires programming the corresponding macro service control register. Each individual interrupt, excluding INTR, NMI and TBC, has its own associated MSC
register. See table 6. Format for all MSC registers is
shown in figure 12.
Figure 12.
Full Count
1.2 tiS
25.6 tiS
78.643 ms
1.678 s
SCLK/6
SCLK/128
Macro Service Control Registers (MSC)
6
7
xxMSn
Timer Resolution
I
MSM2
I
MSM1
o
4
I
MSMo
I
DIR
I
0
I
CH2
I
I
CH1
I
CHo
I
2 1
0
Macro Service Channel
0 0
0
Channel 0
1 1
1
Channel 7
···
..
Transfer Direction
0
From Memory to SFR
1
From SFR to Memory
Transfer Mode-
* All other combinations are reserved
*
0 ()
0 0
1 0
0
1
0
8-bit Transfer
16-bit Transfer
8-bit Transfer with Character Search
49-001384B
16
NEe
Figure 13.
pPD70320/322 (V25)
Timer Unit Block Diagram
,-------
"I
I
I
I
I
fose /S
fose/ 128
I
I
I
fose/ 12
fosC/ 128
I
I
fose /S
fose/ 12
foSc/128
L
___ _
I
Output
Control
--11-----------Internal Bus
1---~nTO
--~
~
49-0013478
17
NEe
pPD70320/322 (V25)
One-Shot Mode. In the one-shot mode, TMO and MOO
operate as independent one-shot timers. Starting with
a preset value, each is decremented to zero. At zero,
counting ceases and an interrupt is generated by TFO
(from TMO) or TF1 (from MOO). One-shot mode allows
two selectable input clocks (fosc = 10 MHz).
Figure 14.
Timer Resolution
Full Count
2.4 p.s
25.6 P.S
157.283 ms
1.678 s
SCLK/12
SCLK/128
Setting the desired timer mode requires programming
the timer control register. See figures 14 and 15 for
format.
Timer Control Register 0
7
I
Clock
o
6
I
TSO
TCLKO
I
MSO
I
MCLK
I
ENTO
I
ALV
I
MOD1
MODO
I
I
MOD1
MODO
0
0
Timer Mode
Interval Timer Mode
0
1
One-shot Timer Mode
1
X
Reserved
Active Level of TOUT
0
TOUT initial level = 0
1
TOUT initial level = 1
0
Disable Timer Out
1
Enable Timer Out
0
SCLK/12
1
SCLK/128
0
Stop Modulus Register Count
1
Start Modulus Register Count
Enable Timer-Out Signal
One-shot Mode Modulus Register Clock
Modulus Start (One-shot Mode)
TM Register Clock Select
MODO
TCLK
0
0
0
0
0
1
SCLK/128
0
1
0
SCLK/12 One-shot Mode
0
1
1
MOD1
SCLK/6 Interval Timer Mode
SCLK/128
Timer Start Bit
0
Stop Timer"
1
Start Timer"
"Starts and stops TMO in one-shot mode
~,H)01387B
Figure 15.
Timer Control Reg/ster 1
7
I
TS1
TCLK1
I
I
0
I
0
I
0
o
2
3
4
I
I
0
I
0
I
0
TM1 Clock Select
oI
SCLK/6
1
SCLK/128
I
Timer Start Bit
oI
Stop TM1 counting
I
Start TM1 counting
1
49-0013898
18
NEe
pPD70320/322 (V25)
Time Base Counter/Processor Control Register
The TBC (figure 18) uses the system clock as the input
frequency. The system clock can be changed by
programming the PCKO and PCK1 bits in the processor
control register (PRC). Reset initializes the system
clock to fasc/8 (fasc = external oscillator frequency).
The 20-bit free-running time base counter controls
internal timing sequences and is available to the user
as the source of periodic interrupts at lengthy intervals.
One of four interrupt periods can be selected by programming the TBO and TB1 bits in the processor
control register (PRC). The TBC interrupt is unlike the
others in that it is fixed as a level 7 vectored interrupt.
Macro service and register bank switching cannot be
used to service this interrupt. See figures 16 and 17.
Figure 18.
Time Base Counter (TBC) Block Diagram
SCLK
The RAMEN bit in the PRC register allows the internal
RAM to be removed from the memory address space to
implement faster instruction execution.
49-001348A
Figure 16.
Time Base Interrupt Request Control Register
6
7
I
TBF
I
TBMK
4
I
0
I
0
2
I
0
I
1
I
1
I
1
I
Time Base Interrupt Mask Bit
oI
1
I
Unmasked
Masked
Time Base Interrupt Flag
oI
1
I
No Interrupt Generated
Interrupt Generated
49-0013936
Figure 17.
Processor Control Register (PRC)
o
7
PRC
I
0
I
RAMEN
I
0
I
0
I
TB1
TBO
I
I
I
PCK1
I
I
PCKO
I
System Clock Select
PCK1
PCKO
0
0
fosc/2
0
1
fOSC/4
1
0
fOSC/8
1
1
Reserved
Time Base Interrupt Period
TB1
TBO
0
0
0
1
1
0
1
1
21O/fCLK
213/fCLK
216/fCLK
22O /fCLK
Internal RAM Enable
0
Disabled
1
Enabled
49-0013958
19
NEe
pPD70320/322 (V25)
Refresh Controller
The pP070320/322 has an on-chip refresh controller
for dynamic and pseudostatic RAM mass storage
memories. The refresh controller generates refresh
addresses and refresh pulses. It inserts refresh cycles
between the normal CPU bus cycles ~ccording to
refresh specifications.
The refresh controller outputs a 9-bit refresh address
on address bits Ao-As during the refresh bus cycle.
Address bits Ag-A19 are all 1'so The 9-bit refresh
address is automatically incremented at every refresh
timing for 512 row addresses. The a-bit refresh mode
(RFM) register (figure 19) specifies the refresh operation and allows refresh during both CPU HALT and
HOLD modes. Refresh cycles are automatically timed
to REFRQ following read/write cycles to minimize the
effect on system though put.
The following shows the REFRQ pin level in relation to
bits 4 (RFEN) and 7 (RFLV) of the refresh mode
register.
--
RFEN
--
RFLV
REFRQ Level
0
0
1
1
0
1
0
1
0
1
0
Refresh pulse output
Serial Interface
ThepP070320/322 hastwo full-duplex UARTs, channel
o and channel 1. Each serial port channel has a
transmit line (TxOn), a receive line (RxOn), and a clear
to send (CTSn) input line for handshaking. Communication is synchronized by a start bit, and you can
program the ports for even, odd, or no parity, character
lengths of 7 or a bits, and 1 or 2 stop bits.
ThepP070320/322 has dedicated baud rate generators
for each serial channel. This eliminates the need to
obligate the on-chip timers. The baud rate generator
allows a wide range of data transfer rates (up to 1.25
Mb/s). This includes all of the standard baud rates
without being restricted by the value of the particular
external crystal.
20
Each baud rate generator has. an 8-bit baud rate
generator (BRGn) data register, which functions as a
prescaler to a programmable input clock selected by
the serial communication control (SCCn) register.
Together these must be set to generate a frequency
equivalent to the desired baud rate.
The baud rate generator can be set to obtain the
desired transmission rate according to the following
formula:
B
X
where
G = SCLK X 106
2n + 1
B = baud rate
G = baud rate generator register (BRGn)
value
n = input clock specifications (n between
o and 8) This is the value that is loaded
into the SCCn register (see figure 23).
SCLK = system clock frequency (MHz)
Based on the above expression, the following table
shows the baud rate generator values used to obtain
standard transmission rates when SCLK = 5 MHz.
BRGn Value
Error 1%)
110
7
178
0.25
150
7
130
0.16
300
6
130
0.16
600
5
130
0.16
1200
4
130
0.16
2400
3
130
0.16
4800
2
130
0.16
9600
1
130
0.16
19,200
0
130
0.16
38,400
0
65
0.16
1.25M
0
2
Baud Rate
0
NEe
Figure 19.
pPD70320/322 (V25)
Refresh Mode Register (RFM)
7
RFM
I
RFLV
5
I
HLDRF
I
HLTRF
4
I
RFEN
2
I
RFW1
RFWO
I
I
I
RFT1
RFTO
Refresh Cycle Speed
Refresh Period
RFT1
RFTO
0
0
16JSCLK
0
1
32JSCLK
1
0
64JSCLK
1
1
128JSCLK
Refresh Cycle Wait States
RFW1
RFWO
0
0
Number of Wait States
0
0
1
1
1
0
2
1
1
2
Refresh Enable
RFLV
0
Refresh Pin
1
Refresh Enabled
0
Refresh During Halt Disabled
1
Refresh During CPU HALT
0
Hold Refresh Disabled
1
Refresh During Hold
Halt Refresh Enable
Hold Refresh Enable
Refresh level output
to RFSH pin when RFEN = 0
49-001392B
21
NEe
pPD70320/322 (V25)
In addition to the asynchronous mode, channel 0 has a
synchronous 1/0 interface mode. In this mode, each bit
of data tranferred is synchronized to a serial clock
(SCKO). This is the same as the NEC pCOM75 and
pCOM87 series, and allows easy interfacing to these
devices. Figure 20 is the serial interface block diagram;
figures21, 22, and 23 show the three serial communication registers.
Figure 20.
Serial Interlace Block Diagram
TxDO
RxDO
CTSO
Baud Rate
Generator
SCKO
TxD1
RxD1
CTS1
TxC1
Baud Rate
Generator
49-0013498
22
NEe
Figure 21.
SCM
I
pPD70320/322 (V25)
Serial Communication Mode Register (SCM)
TxROY
I
o
I
RxE
PRTY1
PRTYO
I
I
I
CLITSK
I
SLlRSCK
I
MD1
MOO
I
I
M01 MOO
0
Mode
0
I/O Interface [Note 1)
0
1
Asynchronous
1
X
Reserved
Stop Bit Length/Rcv Clk [Note 3)
0
1 Stop Bit/Ext Clk [input on CTSO)
1
2 Stop Bits/lnt Clk [output on CTSO)
Char Length/Trans Shift Clk [Note 3)
0
7 Bits/No Effect
1
8 Bits/Trigger Transmit
PRTY
Parity Control
t--r--
1
0
0
0
0
1
o Parity [Note 2)
1
0
Odd Parity
1
1
No Parity
Even Parity
Receiver Control
0
Disable
1
Enable
0
Disable
1
Enable
Transmitter Control
Notes.
(1) Only Channel 0 has I/O interface mode.
(2) When 0 parity is selected, the parity is 0
during transmit and is ignored during receive.
(3) Applies only to I/O interface mode.
49·0013858
Figure 22.
Serial Communication Error Registers (SCE)
3
SCEn
I
RxO
I
0
I
0
I
0
I
0
2
I
ERP
I
ERF
J
ERO
L
Overrun Error Flag
I
oI
1
Overrun has occurred
Overrun has not occurred
Framing Error
I
oI
1
Stop bit not detected
Framing error has not occurred
Parity Error
1
I
oj
Parity error has occurred
No parity error has occurred
RxD Line Status
I
oI
1
RxDLine
RxDLine
=1
=0
49·001386A
23
NEe
pPD70320/322 (V25)
Figure 23.
Serial Communication Control Register (SCC)
7
scc
I
I
I
0
0
I
0
2
3
4
0
I
PRS3
1
PRS2
PRS1
1
PRSo
Input clock for baud
rate generator
PRS
321 0
0000
*AII oth er combinations after 1000 are illegal
SCLK/2
0001
SCLK/4
001 0
SCLK/8
00 1 1
SCLK/16
01 00
SCLK/32
o1
o1
o1
0 1
SCLK/64
1 0
SCLK/128
1 1
SCLK/256
1 000
SCLK/512*
49-0013888
DMA Controller
The pPD70320/322 has a two-channel, on-chip DMA
controller. This allows rapid data transfer between
memory and auxiliary storage devices. The DMA controller supports four modes of operation, two for
memory-to-memory transfers and two for transfers
between 1/0 and memory. See figures 24, 25, and 26 for
a graphic representation of the DMA registers.
Memory-to-Memory Transfers. In the single-step mode,
when one DMA request is made, execution of one
instruction and one DMA transfer are repeated alternately until the prescribed number of DMA transfers
has occurred. Interrupts can be accepted while in this
mode. In burst mode, one DMA request causes DMA
transfer cycles to continue until the DMA terminal
counter decrements to zero. Software can also initiate
memory-to-memory transfers.
Figure 24.
DMA Channels
TC1
SARH1
DARHt
DAR1
The bottom of internal RAM contains all the necessary
address information for the designated DMA channels.
The DMA channel mnemonics are as follows:
TC
SAR
SARH
DAR
DARH
Terminal counter
Source address register
Source address register high
Destination address register
Destination address register high
SAR1
Channel 1
TCO
Channel 0
When the EDMA bit is set, the internal DMARa flag is
cleared. Therefore, DMARas are only recognized after
the EDMA bit has been set.
XXEOOH
See Execution Clock Counts for Operation and Bus
Controller Latency tables for DMA latency and transfer
rate information.
SARHOI
DARHO
DARO
SARO
1-16Bits-J
49-001350A
24
In all modes, the TC (terminal count) output pin will
pulse low and a DMA completion interrupt request will be
generated after the predetermined number of DMA
cycles has been completed.
The DMA controller generates physical source
addresses by offsetting SARH 12 bits to the left and
then adding the SAR. The same procedure is also used
to generate physical destination addresses. You can
program the controller to increment or decrement
source andlor destination addresses independently
during DMA transfers.
XXEOEH
I
Transfers Between 1/0 and Memory. In single-transfer
mode, one DMA transfer occurs after each rising edge
of DMARa. After the transfer, the bus is returned to the
CPU. In demand release mode, the rising edge of
DMARa enables DMA cycles, which continue as long
as DMARa is high.
NEe
Figure 25.
pPD70320/322 (V25)
DMA Mode Registers (DMAM)
o
4
I
MD2
I
I
MD1
I
MDo
I
I
I
W
EDMA
I
TDMA
I
I
0
DMAMO
0
DMAM1
Trigger DMA [Note 1]
o
1
I No Effect
I TriggerDMA
Enable DMA [Note 2]
o
1
I
I
Disable DMA
Enable DMA
Word/byte
oI
1
Byte Transfers
I Word Transfers
DMAMode
Notes:
[1] Valid only during single-step and burst
modes.
[2] Cleared when TC = 0; cleared when DMA
transfer is aborted by NMI.
MD2
MD1
MDo
0
0
0
Single Step (Mem to Mem)
0
0
1
Demand Release (110 to Mem)
0
1
0
Demand Release (Mem to 110)
0
1
1
Reserved
1
0
0
Burst Mode (Mem to Mem)
1
0
1
Single Transfer (110 to Mem)
1
1
0
Single Transfer (Mem to 110)
1
1
1
Reserved
49·0013908
Figure 26.
DMA Address Control Registers (DMAC)
7
I
0
I
0
I
PD1
PD~
I
I
I
0
I
0
I
PS1
I
I
I
PSO
I
DMACO
DMAC1
Source Address Increment/Decrement Control
PS1
PSO
0
0
Source Address not
Incremented/Decremented
0
1
Increment Source Address
1
0
Decrement Source Address
1
1
Source Address not
Incremented/Decremented
Destination Address Increment/Decrement Control
PD1
PD~
0
0
Destination Address not
Incremented/Decremented
0
1
Increment Destination
Address
1
0
Decrement Destination
Address
1
1
Destination Address not
Incremented/Decremented
49-0013918
25
NEe
pPD70320/322 (V25)
Parallel Ports
Use the associated port mode and port mode control
registers to select the mode for a given I/O line.
The pPD70320/322 has three a-bit parallel I/O ports:
PO, P1, and P2. Refer to figures 27 through 31. Special
function register (SFR) locations can access these
ports. The port lines are individually programmable as
inputs or outputs. Many of the port lines have dual
functions as port or control lines.
Figure 27.
Port Mode Registers 0 and 2 (PMO, PM2)
6 -
7
o
2
PMO
PM2
Output Port Mode
Input Port Mode
49-001377B
Figure 28.
Port Mode Register 1 (PM 1)
7
PM1
I
PM17
I
I
2
4
6
PM16
PM1s
I
I
I
PM14
I
I
1
I
1
PMC1 n
n
1
1
1
1
1
PM1 n
Port P1 n
0
0
Output
0
1
Input
= 7, 6, 5, or 4
83-004537B
Figure 29.
Port Mode Control Register 0 (PMCO)
7
4
49-001378B
26
NEe
pPD70320/322 (V25)
Port Mode Control Register 1 (PMC1)
Figure 30.
5
7
I
PMC 17
I
PMC 1S
I
o
4
PMC 1S
I
PMC 14
I
PMC13
I
PMC12
I
PMC 11
I
PMC 10
-
I
Port/Control Bit Selection
X
NMIIP10 Input
X
INTPO/P11 Input
X
INTP1/P12 Input
0
INTP2/P13 Input
1
INTAK Output
0
P14 1/0 or POLL Input
1
INT Input
0
P1S"0
1
TOUT Output
0
P1S"0
1
SCKO Output
0
P17110
1
READY Input
49-0013796
Figure 31.
Port Mode Control Register 2 (PMC2)
7
PMC2
I
PMC27
4
6
I
PMC 26
I
PMC2s
I
PMC24
PMC23
o
2
3
I
I
PMC 22
I
PMC 21
I
PMC 20
Port/Control Bit Selection
0
110 Port
1
DMARQO Input
0
110 Port
1
DMAAKO Output
0
110 Port
1
TCOOutput
0
110 Port
1
DMARQ1 Input
0
110 Port
1
DMAAK1 Output
0
110 Port
1
TC10utput
0
110 Port
1
HLDAK Input
0
110 Port
1
HLDRQ Output
49-0013806
27
NEe
pPD70320/322 (V25)
Figure 33.
The analog comparator port (PT) compares each input
line to a reference voltage. The reference voltage is
programmable to be the VTH input x n/16, where n = 1
to 16. See figure 32.
Programmable' Walt State Generation
FFFFFH
256K
Programmable Wait State Generation
COOOOH
You can generate wait states internally to further
reduce the necessity for external hardware. Insertion
of these wait states allows direct interface to devices
whose access times cannot meet the CPU read/write
timing requirements.
.,
L.o
L"
~
40000H
128K
20000H
When using this function, the entire 1M-byte memory
address space is divided into 128K-blocks. Each block
can be programmed for zero, one, ortwo wait states, or
two plus those added by the extenal READY signal.
The top two blocks are programmed together as one
unit.
128K
OH
49-001351A
The appropriate bits in the wait control word (WTC)
control wait state generation. Programming the upper
two bits in the wait control word will set the wait state
conditions for the entire I/O address space. Figure 33
shows the memory map for programmable wait state
generation; see figure 34 for a graphic representation
of the wait control word.
Figure 32.
Port Mode Register T (PMT)
7
I
0
o
3
I
0
I
0
I
0
I
PMT3
I
I
PMT2
I
PMT1
I
PMTo
PMT
J
Comparator Port Threshold Selection
x 16/16
x 1/16
VTH x 2/16
0
0
0
0
VTH
0
0
0
1
VTH
0
0
1
0
0
0
1
1
VTH
0
1
0
0
VTH
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
x 3/16
x 4/16
VTH x 5/16
VTH x 6/16
VTH x 7/16
VTH x 8/16
VTH x 9/16
VTH x 10/16
VTH x 11/16
VTH x 12/16
VTH x 13/16
VTH x 14/16
VTH x 15/16
49-001381 B
28
NEe
pPD70320/322 (V25)
Standby Modes
STOP Mode.
The two low-power standby modes are HALT and
STOP. Software causes the processor to enter either
mode.
The STOP mode allows the largest power reduction
while maintaining RAM. The oscillator is stopped,
halting all internal peripherals. Internal status is maintained. Only a reset or NMI can release this mode.
HALT Mode.
A standby flag in the SFR area is reset by rises in the
supply voltage. Its status is maintained during normal
operation and standby. The STBC register (figure 35)
is not initialized by RESET. Use the standby flag to
determine whether program execution is returning
from standby or from a cold start by setting this flag
before entering the STOP mode.
In the HALT mode, the processor is inactive and the
chip consumes much less power than when operational. The external oscillator remains functional and
all peripherals are active. Internal status and output
port line conditions are maintained. Any unmasked
interrupt can release this mode. In the EI state, interrupts subsequently will be processed in vector mode.
In the 01 state, program execution is restarted with the
instruction following the HALT instruction.
Figure 34.
Walt Control Word
Wait Control High
o
7
Wait Control Low
7
I
4
BLK31
I
BLK30
I
BLK21
I
BLK20
I
BLK11
I
BLK10
I
BLK01
I
o
BLKOO
l
BLKn1
BLKnO
0
0
Mode
No Waits
0
1
1 Wait
1
0
2 Wait
1
1
2 Waits
+ Ext. Ready
49-0013948
Figure 35.
7
Standby Register
5
4
o
o
o
o
o
SBF
I
L
STBC
Standby Flag
I
oI
1
No changes in supply voltage (standby)
Rising edge on supply voltage (cold start)
49-0013968
29
NEe
pPD70320/322 (V25)
Special Function Registers
Table 6 shows the special function register mnemonic,
type, address, reset value, and function. The 8 highorder bits of each address (xx) are specified by the I DB
register.
Reset
Value
(Note 2)
Name
By tel
Word Address
RXBO
B
xxF60H
R
Receive buffer 0
TXBO
B
xxF62H
W
Transfer buffer 0
R/W
(Note 1)
Function
SFR area addresses not listed in table 6 are reserved. If
read, the contents of these addresses are undefined,
and any write operation will be meaningless.
SRMSO
B
xxF65H
R/W
Serial receive
macro service 0
STMS1
B
xxF66H
R/W
Serial transmit
macro service 1
Table 6.
SCMO
B
xxF68H
OOH
R/W
Serial communication
mode 0
SCCO
B
xxF69H
OOH
R/W
Serial communication
control 0
Port 0
BRGO
B
xxF6AH
OOH
R/W
Baud rate generator 0
SCEO
B
xxF6BH
OOH
R
Serial communication
error 0
SEICO
B
xxF6CH
47H
R/W
Serial error interrupt
control 0
SRICO
B
xxF6DH
47H
R/W
Serial receive interrupt
control 0
STICO
B
xxF6EH
47H
R/W
Serial transmit interrupt
control 0
Special Function Registers
Name
Bytel
Word
Address
PO
B
xxFOOH
Reset
Value
(Note 2)
R/W
(Note 1)
R/W
Function
PMO
B
xxF01H
FFH
W
Port mode 0
PMCO
B
xxF02H
OOH
W
Port mode control 0
P1
B
xxF08H
R/W
Port 1
PM1
B
xxF09H
FFH
W
Port mode 1
PMC1
B
xxFOAH
OOH
W
Port mode control 1
P2
B
xxF10H
R/W
Port 2
PM2
PMC2
PT
B
B
PMT
xxF11H
FFH
W
Port mode 2
xxF12H
OOH
W
Port mode control 2
xxF38H
R
PortT
xxF3BH
OOH
R/W
Port mode T
xxF40H
OOH
RXB1
B
xxF70H
R
Receive buffer 1
TXB1
B
xxF72H
W
Transmit buffer 1
SRMS1
B
xxF75H
R/W
Serial receive macro
service 1
R/W
Serial transmit macro
service 1
B
B
R/W
Interrupt mode
STMS1
B
xxF76H
EMSO
xxF44H
R/W
External interrupt
macro service 0
SCM1
B
xxF78H
OOH
R/W
EMS1
B
xxF45H
R/W
External interrupt
macro service 1
Serial communication
mode 1
SCC1
B
xxF79H
OOH
R/W
EMS2
xxF46H
R/W
External interrupt
macro service 2
Serial communication
control 1
BRG1
B
xxF7AH
OOH
R/W
EXICO
xxF4CH
47H
R/W
External interrupt
control 0
Baud rate generator
register 1
SCE1
B
xxF7BH
OOH
R
EXIC1
xxF4DH
47H
R/W
External interrupt
control 1
Serial communication
error 1
SEIC1
B
xxF7CH
47H
R/W
EXIC2
xxF4EH
47H
R/W
External interrupt
control 2
Serial error interrupt
control 1
SRIC1
B
xxF7DH
47H
R/W
Serial receive interrupt
control 1
STIC1
B
xxF7EH
47H
R/W
Serial transmit interrupt
control 1
Timer register 0
INTM
Notes:
(1) Indicates if register is available for read/write operations.
(2) Reset values not specified are undefined.
30
TMO
W
xxF80H
R/W
TMOL
B
xxF80H
R/W
Timer register 0 low
TMOH
B
xxF81H
R/W
Timer register 0 high
MDO
W
xxF82H
R/W
Modulo register 0
NEe
Table 6.
pPD70320/322 (V25)
Special Function Registers (cant)
Reset
Value
(Note 2)
Absolute Maximum Ratings
TA = 25°C
Name
Bytel
Word Address
MDOL
B
xxF82H
R/W
Modulo register 0 low
MDOH
B
xxF83H
R/W
Modulo register 0 high
TM1
W
xxF88H
R/W Timer register 1
R/W
(Note 1)
TM1L
B
xxF88H
R/W Timer register 1 low
TM1H
B
xxF89H
R/W Timer register 1 high
MD1
W
xxF8AH
R/W Modulo register 1
MD1L
B
xxF8AH
R/W Modulo register 1 low
MD1H
B
xxF8BH
TMCO
B
xxF90H
OOH
R/W Modulo register 1 high
R/W Timer control 0
TMC1
B
xxF91H
OOH
R/W Timer control 1
TMMSO
B
xxF94H
R/W Timer macro service 0
TMMS1
B
xxF95H
R/W Timer macro service 1
TMMS2
B
xxF96H
TMICO
B
xxF9CH
47H
R/W Timer interrupt control 0
TMIC1
B
xxF9DH
47H
R/W Timer interrupt control 1
R/W Timer macro service 2
Input voltage, VI
-0.5 to VDD + 0.5 V (::::: +7.0 V)
Output voltage, Vo
-0.5 to VDD + 0.5 V (::::: +7.0 V)
Threshold voltage, VTH
-0.5 to VDD + 0.5 V (::::: +7.0 V)
Output current, low; IOL
Each output pin
Total
4.0 rnA
50 rnA
Output current, high; IOH
Each output pin
Total
Comment: Exposure to Absolute Maximum Ratings for extended
periods may affect device reliability; exceeding the ratings could
cause permanent damage.
limits
Parameter
Symbol
Typ
Max
Unit
Test
Conditions
Supply current,
operating
IDD1
43
58
100
120
rnA
rnA
fCLK = 5 MHz
fCLK = 8 MHz
Supply current,
HALT mode
IDD2
17
21
40
50
rnA
rnA
fCLK = 5 MHz
fCLK = 8 MHz
Supply current,
STOP mode
IDD3
10
30
J1A
xxF9EH
B
xxFAOH
DMAMO
B
xxFA1H
DMAC1
B
xxFA2H
DMAM1
B
xxFA3H
OOH
R/W DMA mode 1
DICO
B
xxFACH
47H
R/W DMA interrupt control 0
DICI
B
xxFADH
47H
R/W DMA interrupt control 1
Threshold current ITH
R/W Standby control
Input voltage,
low
VIL
Input voltage,
high
VIH1
OOH
R/W DMA mode 0
R/W DMA control 1
STBC
B
xxFEOH
RFM
B
xxFE1H
OFCH
R/W Refresh mode
WTC
W
xxFE8H
FFH
R/W Wait control
WTCL
B
xxFE8H
FFH
R/W Wait control low
WTCH
B
xxFE9H
FFH
R/W Wait control high
FLAG
B
xxFEAH
OOH
R/W Flag register
PRC
B
xxFEBH
4EH
R/W Processor control
TBIC
B
xxFECH
47H
ISPR
B
xxFFCH
R
IDB
B
xxFFFH
FFFFFH
R/W Internal data area base
R/W Time base IRC register
In service priority register
ED
DC Characteristics
VDD = +5 V ±10%; TA = -10 to +70°C (Note 1)
B
R/W Timer interrupt control 2
-40 to +85°C
-65 to +150 °C
Storage temperature range, TSTG
DMACO
R/W DMA control 0
-2.0 rnA
-20 rnA
Operating temperature range, TOPT
TMIC2
47H
-0.5 to +7.0 V
Supply voltage, VDD
Function
Min
0.5
1.0
rnA
0
0.8
V
2.2
VOD
V
VTH = 0 to VDD
~utsexcept
RESET, P10INMI,
X1, X2
VIH2
0.8 x
VDD
VOD
V
RESET, P10INMI,
X1, X2
0.45
V
IOL = 1.6 rnA
V
IOH = -0.4 rnA
Output voltage,
low
VOL
Output voltage,
high
VOH
Input current
liN
±20
J1A
EA, P10/NMI;
VI = 0 to VDD
Input leakage
current
III
±10
J1A
All except EA,
P10/NMI;
VI = 0 to VDD
Output leakage
current
ILO
±10
J1A
Vo = 0 to VDD
Data retention
voltage
VDDDR
5.5
V
VDD
-1.0
2.5
Notes:
(1) The standard operating temperature range is -10 to +70°C.
However, extended temperature range parts (-40 to +85 0c) are
available.
31
NEe
pPD70320/322 (V25)
Supply Current vs Clock Frequency
AC Characteristics
Voo = +5 V ±10%; TA = -10 to +70°C; CL = 100 pF (max)
150
limits
TA = 25°C
Voo = 5 v
140 r - -
Typ. Sample
130
splc.Point
120
110
Spec.
Point
100
90
C( 80
E.
Q
.E
./
/"'"
50
40
/"'"
30
/"'"
~
V
Voo rise,
fall time
tRVO, tFVO
200
Input rise,
fall time
tlR, tlF
20
ns ~xcept X1, X2,
ESET, NMI
Input rise,
fall time
tIRS, tlFS
30
ns RESET, NMI
(Schmitt)
Output rise,
fall time
tOR, tOF
20
ns Except CLKOUT
X1 cycle time
tCYX
98
250
ns Note 3
62
250
o
o
X1 width, high
5
6
9
felK [MHz]
83-004331 A
Comparator Characteristics
= +5 V ±10%; TA = -10 to +70°C
limits
Symbol
Accuracy
VACOMP
Min
Threshold voltage VTH
0
Max
Unit
±100
mV
VOO
+0.1
V
Comparison time
tCOMP
64
65
tCYK
PT input voltage
VIPT
0
VOO
V
PTn leakage
current
ILC
±10
pA
Test
Conditions
Max
Unit
Input capacitance
Symbol
CI
Min
10
pF
Output capacitance
Co
20
pF
1/0 capacitance
CIO
20
pF
tXR, tXF
CLKOUT cycle
time
tCYK
/lS STOP mode
Test
Conditions
fc = 1 MHz;
Unmeasured pins
returned to 0 V
20
ns Note 4
35
ns Note 3
ns Note 4
20
ns
200
2000
ns Note 3
125
2000
ns Note 4
0.5T -15
ns Note 1
CLKOUT width, tWKH
high
0.5T -15
ns
CLKOUT rise,
fall time
tKR, tKF
Address delay
time
tOKA
15
Address hold
time
tHMA
0.5T - 30
MREQ to data
delay
tOMRO
MSTB to data
delay
tOMSO
MREQ width,
low
tWMRL
Input data hold tHMOR
time
Next control
setup time
tscc
15
ns
90
ns
ns
T(n + 1.5) ns Note 2
-90
T(n+ 1)
-75
0.5T
-35
0.5T
+35
ns
T(n + 1)
-30
ns
0
ns
T -25
ns
Notes:
(3) For 5 MHz parts (J.IPD70320/322).
(4)
ns
T(n +0.5) ns
-75
(1) T = CPU clock period (tCYK)'
(2) n = number of wait states inserted.
32
ns Note 4
ns Note 3
CLKOUT width, tWKL
low
MREQ to MSTB. tOMRMS
delay
= 0 v; TA = 25°C
Limits
X1 rise,
fall time
Unit
35
Address valid to tOAOR
input data valid
CapaCitance Characteristics
Parameter
tWXH
Max
20
4
Parameter
tWXL
.,/"
10
Voo
Min
X1 width, low
20
Voo
. Symbol
70
60
Test
Conditions
Parameter
For 8 MHz parts (J.IPD70320/322-8).
NEe
pPD70320/322 (V25)
AC Characteristics (cont)
AC Characteristics (cont)
Limits
Limits
Parameter
Symbol
MREQ to TC
delay time
tOMRTC
0.5T + 50 ns
Address data
output
tOAOW
0.5T + 50 ns
MREQ delay time
tOAMR
0.5T - 30 0.5T + 30 ns
Min
Max
Unit
MSTB delay time
tOAMS
T -30
MSTB width,
low
tWMSL
T(n + 0.5)
- 30
ns
Data output
setup time
tSOM
T(n + 1)
- 50
Data output
hold time
tHMOW
0.5T - 30
10STB delay time
tOAIS
10STB to data
input
tDiSO
10STB width,
low
tWISL
Address hold
time
Input data
hold time
tHISA
tHISOR
Output data
setup time
tSOIS
Output data
hold time
tHISOW
T +30
Test
Conditions
ns
30
ms STaPf
paR
(Poweron reset)
tWRSL2
5
/15
HLDRQ setup time
tSHQK
30
ns
HLDAK output delay
tOKHA
Bus control float to
HLDAK~
tCFHA
T -50
ns
HLDAK t to control output
time
tOHAC
T -50
ns
HLDRQ to HLDAK delay
tOHQHA
ns
ns
T(n + 1)
-50
ns
0.5T - 30
ns
tSOAOQ
DMARQ hold
time
tHOAOQ
DMAAK read
width, low
tWOMRL T(n + 1.5)
- 30
DMAAK write
width, low
tWOMWL
DMAAK to TC
delay time
tOOATC
TC width, low
tWTCL
2T - 30
ns
REFRQ delay
time
tOARF
0.5T - 30
ns
ns Demand mode
ns Demand mode
ns
ns
0.5T + 50 ns
Address hold
time
tHRFA
T(n + 1)
- 30
ns
0.5T - 30
ns
ns
3T + 160
tOHQC
3T +30
HLDRQ width, low
tWHQL
1.5T
ns
ns
ns
T
ns
HLDAK width, low
tWHAL
tSIQK
30
ns
INTP, DMARQ width, high
tWIQH
8T
ns
INTp, DMARQ width, low
tWIQL
8T
ns
POLL setup time
tSPLK
30
ns
NMI width, high
tWNIH
5
/15
NMI width, low
tWNIL
5
/15
CTS width, low
tWCTL
2T
ns
INTR setup time
tSIRK
30
INTAK delay time
tOKIA
INTR hold time
tHIAIQ
0
ns
INTAK width, low
tWIAL
2T -30
ns
tWIAH
T -30
INTAK width, high
INTAK to data hold
SCKO (TSCK) cycle time
ns
80
tDiAO
Em
ns
INTp, DMARQ setup
INTAK to data delay
tWRFL
ns n2::2
80
HLDRQ ~ to control float
System
reset
ns n2::2
T(n -1)
Next DMARQ
setup time
REFRQ width,
low
T(n -1)
-100
tHCRY
ns
T(n + 1)
- 30
tWRSL1
MREQ, 10STB to READY
hold time
0.5T - 30
0
RESET width low
ns
ns
T
Min
tSCRY
T(n + 1)
-30
0
Symbol
MREQ, 10STB to READY
setup time
0.5T - 30 0.5T + 30 ns
T(n + 1)
- 90
Max
Test
Unit Conditions
Parameter
ns
ns
2T -130
ns
0.5T
ns
tHIAO
0
ns
tCYTK
1000
SCKO (TSCK) width, high
tWSTH
450
ns
SCKO (TSCK) width, low
tWSTL
450
ns
210
ns
TxD delay time
tOTKO
TxD hold time
tHTKO
20
ns
CTSO (RSCK) cycle time
tCYRK
1000
ns
CTSO (RSCK) width, high
tWSRH
420
ns
CTSO (RSCK) width, low
tWSRL
420
ns
RxD setup time
tSROK
80
ns
RxD hold time
tHKRO
80
ns
33
NEe
pPD70320/322 (V25)
Figure 36.
External System Clock Control Source
r
External Oscillator Configuration
Recommended Crystal Configuration
10 pF
~ ~F pt.
-=-
Osc
X1
X1
74HC10
~7
-X2
...X_2_ _ _ _---'
resonant
crystal
Note:
When using a quartz crystal, it is recommended that 15 pF capacity be used.
83-0045748
Recommended Ceramic Resonator and Capacitance Requirements
Manufacturer
Product Number
Recommended
Cl(pF)
Constants
C2(pF)
33
Product Number
Recommended
Cl(pF)
Constants
C2(pF)
Kyocera
KBR-10.0M
33
Murata Manufacturing
CSA.10.0MT
47
47
CSA 16.0MX040
30
30
TDK
FCR10.0M2S
30
30
FCR16.0M2S
15
6
Timing Waveforms
AC Input Waveform 2 (RESET, NMI)
Stop Mode Data Retention Timing
- tlRS
~
VOO
0.8 V
tRVO
83-o04333A
AC Input Waveform 1 (Except X1, X2,
2.4V
0.4V
4
iiESEf, NMI)
It-tiFS
83-00430SA
AC Output Test Point (Except CLKOUT)
~
2.2 V
0.8 V
0.8 V
tlR
83-004305A
li=-tOF
tOR
83-004307A
Clock In and Clock Out
CLKIN1
[X1]
j4------ tC Y X - - - - . 1
CLKOUT
\
-
I--
-
tKR
-tKF
\ 2.2V
0.8 V
/
tWKH
tWKL
tCYK
.
83-004308A
34
NEe
pPD70320/322 (V25)
Timing Waveforms (coni)
Memory Read
~I--------B1--------rl--------B2------~
CLKOUT~~~~~~:K~~~~~~~~~~~~
tOKA-
)
r
-
.
tOAOR
tHMOR ..
I+--tOMRO-
R/W
K
/
tOAMR
J
tWMRL
I
"
tscc-
~
r\
tOMSO
I+---
-tOMRMS-
i
'\
t O A M S - I----tWMSL----...J
~
1\
-tOMRTC
\1+---.-
------+l(
--tWT-CL-
83-004309C
35
NEe
pPD10320/322 (V25)
Timing Waveforms (coni)·
Memory Write
1----81-----+1---- 82 - - - - I
C~OUT ~t----\~YK)__\~I
\------/
tOKA-
)k
r
I+-tOAOW ....
tHMA
....
'.
07- 0 0
l-.
R/W
K
I
tSOM
~IH.oWy
tWMRL
~tscc-
\
c+-toAMRl
"
1I
\
-tOMRMS-
tOAMS~
1\
V
l=-tWMSL_
i\
i\
I-- tOMRTC
TC1-TCO
\1+--.----~tW-TCL_-____+l(
83-004310C
36
NEe
pPD70320/322 (V25)
Timing Waveforms (cont)
110 Read
I
I
B1
CLKOUT
I
B2
J
ICYK
/
~
K
)
I--IOAOR_
rIHISA-
IDiSO
R/W
I.IHISOR.
/
l\I-- IOA,s-:-1
\
IWISL
ISCC-
It
l\-
I\.
83-004311C
37
NEe
pPD70320/322 (V25)
Timing Waveforms {cont}
110 Write
CLKOUT
81
I
tCYK
I
I
82
I
J
~
l(
).
tDADW
rtHISA--
tSDIS
R/W
.
\
tHISDW
V
r\
I-tDAIS--1
"
tWISL
.
~
I+---tscc_
\
r\
83-004312C
38
NEe
pPD70320/322 (V25)
Timing Waveforms (coni)
DMA, 110 to Memory
1r-----B1----+I----B2------i
t=1+----tCYK---J~
CLKOUT
~~~\'-------J ----"\\'-------J!~\'--------J!~~\
tOKA_
J
'K
\
V
07-00
Riw
tWMRL
I--tOAMR-+
I--tHMA--
i\
~
I
tscc-
-tOMRMS-
V
1\
t O A M S - / . - tWMSL-+
1\
_tSOAOQ_
DMARQODMARQ1
~
I--tHOAOQ ......
if
\
tWOMRL
1\
-tODATC- I
tWTCL
II
83-004313C
39
NEe
pPD70320/322 (V25)
Timing Waveforms (coni)
DMA, Memory to 110
~-------B1------~--------B2--------
1 + - - - - - - - teYK - - - - + I
CLKOUT
I+--tOKA_
~
R/W
K
/
"
I--tHMA_
tWMRL
I-tOAMR-
II
\
'\
tOAMS
,
1\
tsee
l"
"
!--tWMSL---=:.j
I--tSOAOO __
DMAROO
DMAR01-
~
I+-tHOAOO~
"
tWOMWL--=1
N:
I+- tOOATC-.
I
tWTCL
J
83-004314C
40
NEe
pPD70320/322 (V25)
Timing Waveforms (coni)
Refresh
1---'----81----+-----82------1
1+----teYK-----'--~
CLKOUT
I--tOKA ....
A19-AO
)~
K
R/W
)'1
1\
ED
~
"
1"----I-tOARF1
tWRFL
\
-tHRFA_
~
tsee
)
~
83-00431SC
CLKOUT------------------------------------~~--J
RESET
~
tWRSL1
Y
R
83-0043168
41
NEe
pPD70320/322 (V25)
Timing Waveforms (cont)
RESET 2
CLKOUT
__
RESET·
~tWRSU~r-----_
~
~
83-0043176
READY 1
~----B1-----+-----BAW-----+-----BAW-----r-----B2_____1
/
~CRY~
\ - tHCRY----j
READY ____________________
I
~~
~~_________________________________________
83-0043186
READY 2
~----B1----_+-----BAW----+-----BAW----~-----BW----~-----B2_____1
-
n=2
n=3
:---tHCRY'
L
tSCRY'
n=2
READY
\
In=3
,V I
• tSCRY [READY setup time) and tHCRY [READY hold time) are a function of
T and n. Timings shown are examples for n = 2 and n = 3.
83-0043196
42
NEe
pPD70320/322 (V25)
Timing Waveforms (cont)
HLDRQ/HLDAK 1
Bus control'
~----tDHQHA-----~
'A19-AO, 07"00, MREO, MSTB, IOSTB, R/W
J..--------twHAL-------+J
~
L-_____________________________________________________~83~-0~04=32~08 ~
HLDRQ/HLDAK 2
CLKOUT
HLORO
~-----tWHQL----~
Bus control' --~----------."I----+----------------_lC
IDKH~----~U}---:~~~~~~~~----~-----tD-H-Q-C----------_-~_-_-_-_-_-_~_ _ _ _ _ ___
83-0043218
INTp, DMARQ Input
CLKOUT
INTp,
OMARO'
J..------------tWIQH---------~ ~ -~- - - - - - - - - - - - -~t~W~IQ-L- - - - - - - - - - - - - ~
'INTP2-INTPO, OMARQ1-0MARQO
83-0043228
pPD70320/322 (V25)
NEe
Timing Waveforms (cont)
POLL Input
CLKOUT
_
l.--tSPLK _ _
POLL~
_ _ _--JI
83-0043236
NMllnput
CLKOUT
NM, --1t+-:---tWN'H--~ht+--.======-tWN-IL====--=--:r
83-0043246
CTS Input
CLKOUT
1~-.~tW-CTL-==r
83-0043256
44
NEe
pPD70320/322 (V25)
Timing Waveforms (coni)
INTRIINTAK
eLKOUT
r~---+--~
INTR
IOKIA
IHIAIQ
D7-DO------------~i~------------~~------------------------{1
83-004326B
Serial Transmit
CLKOUT
ICYTK
\
j
IWSTL
~
TxD
_I
I
\
IWSTH
IHTKO
C
IOTKO
83-004441B
45
ttiEC
pPD70320/322 (V25)
Timing Waveforms (cont)
Serial Receive
CLKOUT
tCYRK
\
tWSRL
RxD
\
,j
tWSRH
~
K
I--tSRDK-
tHKRD
83-0043329
46
NEe
pPD70320/322 (V25)
Instruction Set
Identifier
Instructions, grouped according to function, are
described in a table near the end of this data sheet.
Descriptions include source code, operation, opcode,
number of bytes, and flag status. Supplementary
information applicable to the instruction set is contained in the following tables.
dst-block
Name of block addressed by the IV register
near-proc
Procedure within the current program segment
far-proc
Procedure located in another program segment
• Symbols and Abbreviations
• Flag Symbols
• 8- and 16-Bit Registers. When mod = 11, the register
is specified in the operation code by the byte/word
operand (W = 0/1) and reg (000 to 111).
• Segment Registers. The segment register is specified in the operation code by sreg (00, 01, 10, or 11).
• Memory Addressing. The memory addressing mode
is specified in the operation code by mod (00, 01, or
10) and mem (000 through 111).
• Instruction Clock Count. This table gives formulas
for calculating the number of clock cycles occupied
by each type of instruction. The formulas, which
depend on byte/word operand and RAM enable/disable, have variables such as EA (effective address),
W (wait states), and n (iterations or stringinstructions).
Symbols and Abbreviations
Identifier
Description
reg
8- or 16-bit general-purpose register
reg8
8-bit general-purpose register
reg16
16-bit general-purpose register
dmem
8- or 16-bit direct memory location
mem
8- or 16-bit memory location
mem8
8-bit memory location
mem16
16-bit memory location
mem32
sfr
32-bit memory location
8-bit special function register location
imm
Constant (0 to FFFFH)
imm16
Constant (0 to FFFFH)
imm8
Constant (0 to FFH)
imm4
Constant (0 to FH)
imm3
Constant (0 to 7)
acc
AW or AL register
sreg
Segment register
src-table
Name of 256-byte translation table
src-block
Name of block addressed by the IX register
Description
near-label
Label in the current program segment
short-label
Label between -128 and +127 bytes from the end
of instruction
far-label
Label in another program segment
memptr16
Word containing the offset of the memory location
within the current program segment to which control
is to be transferred
memptr32
Double word containing the offset and segment base
address of the memory location to which control is to
be transferred
regptr16
16-bit register containing the offset of the memory
location within the program segment to which control
is to be transferred
pop-value
Number of bytes of the stack to be discarded (0 to
64K bytes, usually even addresses)
fp-op
Immediate data to identify the instruction code of the
external floating point operation
R
Register set
W
Word/byte field (0 to 1)
reg
Register field (000 to 111)
mem
Memory field (000 to 111)
mod
Mode field (00 to 10)
S:W
When S:W = 01 or 11, data = 16 bits. At all
other times, data = 8 bits.
X, XXX, VVV, ZZZData to identify the instruction code of the
external floating pOint arithmetic chip
AW
Accumulator (16 bits)
AH
Accumulator (high byte)
AL
Accumulator (low byte)
BP
Base pointer register (16 bits)
BW
BW register (16 bits)
BH
BW register (high byte)
BL
BW register (low byte)
CW
CW register (16 bits)
CH
CW register (high byte)
CL
CW register (low byte)
OW
OW register (16 bits)
DH
OW register (high byte)
~
DL
OW register (low byte)
SP
Stack pointer (16 bits)
PC
Program counter (16 bits)
PSW
Program status word (16 bits)
47
NEe
pPD70320/322 (V25)
Symbols and Abbreviations (cont)
Flag Symbols
Identifier
Description
Identifier
Description
IX
Index register (source) (16 bits)
(blank)
No change
IV
Index register (destination) (16 bits)
o
PS
Program segment register (16 bits)
SS
Stack segment register (16 bits)
DSo
Data segment 0 register (16 bits)
DS1
Data segment 1 register (16 bits)
AC
Auxiliary carry flag
CV
Carry flag
P
Parity flag
S
Sign flag
Z
Zero flag
DIR
Direction flag
IE
Interrupt enable flag
V
Overflow flag
BRK
Break flag
MD
Mode flag
(... )
Values in parentheses are memory contents
Cleared to 0
Set to 1
X
Set or cleared according to the result
U
Undefined
R
Value saved earlier is restored
8- and 16-81t Registers (mod = 11)
reg
w=o
W=1
000
AL
AW
001
CL
CW
010
DL
OW
011
BL
BW
100
AH
SP
101
CH
BP
110
DH
IX
111
BH
IV
disp
Displacement (8 or 16 bits)
ext-disp8
16-bit displacement (sign-extension byte
+ 8-bit displacement)
Segment Registers
temp
Temporary register (8/16/32 bits)
sreg
tmpcy
Temporary carry flag (1-bit)
00
Immediate segment data (16 bits)
01
PS
Immediate offset data (16 bits)
10
SS
Transfer direction
11
DSo
seg
offset
+
Register
DS1
Addition
Subtraction
Memory Addressing
Multiplication
mem
mod = 00
mod = 01
mod = 10
Division'
000
BW+IX
BW + IX + disp8
BW + IX + disp16
%
Modulo
001
BW+IV
BW + IV + disp8
BW + IV + disp16
AND
Logical product
010
BP+ IX
BP + IX + disp8
BP + IX + disp16
OR
Logical sum
011
BP+ IV
BP + IV + disp8
BP + IV + disp16
XOR
Exclusive logical sum
100
IX
IX + disp8
IX + disp16
XXH
Two-digit hexadecimal value
101
IV
IV + disp8
IV + disp16
XXXXH
Four-digit hexadecimal value
110
Direct
BP + disp8
BP + disp16
111
BW
BW + disp8
BW + disp16
x
48
NEe
pPD70320/322 (V25)
Instruction Clock Count
Mnemonic
Operand
Clocks
Mnemonic
Operand
Clocks
ADD
regS, regS
reg16, reg16
2
2
BRK
3
immS
55+10W [43+10W]
56+10W [44+10W]
regS, memS
reg16, mem16
EA+6+W
EA+S+2W
memS, regS
mem16, reg16
EA+S+2W [EA+6+W]
EA+12+4W [EA+S+2W]
regS, immS
reg16, immS
reg16, imm16
5
5
6
memS, immS
mem16, immS
mem16, imm16
EA+9+2W [EA+7+2W]
EA+9+2W [EA+7+2W]
EA+14+4W [EA+ 10+4W]
AL, immS
AW, imm16
5
6
ADD4S
ADDC
BTCLR
29
BUSLOCK
2
CALL
ADJ4S
9
ADJBA
17
near-proc
regptr16
22+2W [1S+2W]
22+2W [1S+2W]
memptr16
far-proc
memptr32
EA+26+4W [EA+24+4W]
36+4W [34+4W]
EA+36+8W [EA+24+SW]
CY
DIR
2
2
regS, CL
reg16, CL
S
S
memS, CL
mem16, CL
EA+14+2W [EA+12+W]
EA+1S+4W [EA+14+2W]
7
7
CHKIND
CLR1
Same as ADD
9
EA+26+4W
17
regS, imm3
reg16, imm4
regS, regS
reg16, reg16
2
2
memS, imm3
mem16, imm4
EA+11+2W [EA+9+W]
EA+15+4W [EA+10+2W]
regS, memS
reg16, mem16
EA+6+W
EA+S+2W
regS, regS
reg16, reg16
2
2
memS, regS
mem16, reg16
EA+S+2W [EA+6+W]
EA+12+4W [EA+S+2W]
regS, memS
reg16, mem16
EA+6+W
EA+S+2W
regS, immS
reg16, imm16
5
6
memB, regB
mem16, reg16
EA+6+W
EA+B+2W
memS, immS
mem16, imm16
EA+9+2W [EA+7+2W]
EA+14+4W [EA+10+4W]
regS, immS
reg16, immS
reg16, imm16
5
5
6
memS, immS
mem16, immB
mem16, imm16
EA+7+W
EA+10+2W
EA+10+2W
AL, immS
AW, imm16
5
6
ADJBS
Bcond (conditional branch)
S or 15
BCWZ
Sor 15
BR
15
55+10W [43+10W]
22+(27+3W)n [22+(25+3W)n]
ADJ4A
AND
BRKCS
BRKV
near-label
short-label
12
12
regptr16
memptr16
13
EA+17+2W
far-label
memptr32
15
EA+25+4W
CMP
CMP4S
CMPBK
II
22+(23+2W)n
memS, memS
mem16, mem16
23+2W [19+2W]
27+4W [21+2W]
Notes:
(1 ) If the number of clocks is not the same for RAM enabled and
RAM disabled conditions, the RAM enabled value is listed first,
followed by the RAM disabled value in brackets; for example,
EA+8+2W [EA+6+W).
(2) Symbols in the Clocks column are defined as follows.
EA= additional clock cycles required for calculation of the
effective address
= 3 (mod 00 or 01) or 4 (mod 10)
W = number of wait states selected by the WTC register
n = number of iterations or string instructions
49
NEe
pPD70320/322 {V25}
Instruction Clock Count (cant)
Mnemonic
Operand
CMPBKB
CMPBKW
CMPM
Clocks
Mnemonic
Operand
Clocks
16+(21+2W)n
INM
memS, DW
mem16, DW
19+2W [17+2W]
21+4W [17+4W]
memS, DW
mem16, DW
1S+(13+2W)n [1S+(11+2W)n]
1S+(15+4W)n [1S+(11 +4W)n]
regS, regS
regS, imm4
63-155
64-156
memS
12+W
16+(25+4W)n
memS
mem16
17+W
19+2W
CMPMB
16+(15+W)n
CMPMW
164-(17+2W)n
CVTBD
19
CVTBW
3
CVTDB
20
CVTWL
8
DBNZ
S or 17
DBNZE
S or 17
DBNZNE
DEC
5
2
memS
mem16
EA+11+2W [EA+9+2W]
EA+15+4W [EA+11+4W]
4
DISPOSE
12+2W
DIVU
AW, regS
AW,memS
46-56
EA+4S+W to EA+5S+W
DW:AW, reg16
DW:AW, mem16
54-64
EA+5S+2W to EA+6S+2W
AW, regS
AW,memS
31
EA+33+W
DW:AW, reg16
DW:AW, mem16
39
EA+43+2W
DSO:
2
DS1:
2
EI
EXT
41-121
42-122
2
FP01
60+10W [4S+10W]
FP02
60+10W [4S+10W]
HALT
0
INC
50
LDM
AL, immS
AW, immS
14+W
16+2W
AL, DW
AW,DW
13+W
15+2W
regS
reg16
5
2
memS
mem16
EA+11+2W [EA+9+2W]
EA+15+4W [EA+11+4W]
EA+2
mem16
16+(12+2W)n
LDMB
mem16
14+2W
LDMW
mem8
16+(10+W)n
MOV
regS, regS
reg16, reg16
2
2
regS, memS
reg16, mem16
EA+6+W
EA+S+2W
mem8, reg8
mem16, reg16
EA+4+W [EA+2]
EA+6+2W [EA+2]
regS, immS
reg16, imm16
5
6
memS, immS
mem16, imm16
EA+5+W
EA+5+2W
AL, dmemS
AW, dmem16
9+W
11+2W
dmemS, AL
dmem16, AW
7+W [5]
9+2W [5]
sreg, reg16
sreg, mem16
4
EA+10+2W
reg16, sreg
mem16, sreg
3
EA+7+2W [EA+3]
AH, PSW
PSW, AH
2
3
DSO, reg16, memptr32
DS1, reg16, memptr32
EA+19+4W
EA+19+4W
memS, memS
mem16, mem16
20+2W [16+W]
16+(20+4W)n [16+(12+2W)n]
12
regS, regS
regS, imm4
FINT
IN
LDEA
S or 17
regS
reg16
DI
DlV
INS
MOVBK
MOVBKB
memS, memS
16+(16+2W)n [16+(12+W)n]
MOVBKW
mem16, mem16
24+4W [20+2W]
MOVSPA
16
MOVSPB
MUL
11
AW, AL, regS
AW, AL, memS
31-40
EA+33+W to EA+42+W
DW:AW, AW, reg16
DW:AW, AW, mem16
39-4S
EA+43+2W to EA+52+2W
reg16, reg16, immS
reg16, mem16, immS
39-49
EA+43+2W to EA+53+2W
reg16, reg16, imm16
reg16, mem16, imm16
40-50
EA+44+2W to EA+54+2W
NEe
pPD70320/322 (V25)
Instruction Clock Count (cont)
Mnemonic
MULU
NEG
Operand
regB
memB
24
EA+26+W
reg16
mem16
32
EA+34+2W
NOT1
OR
OUT
OUTM
Operand
Clocks
PREPARE
imm16, immB
immB = 0: 27+2W
immB= 1: 39+4W
immB= n > 1: 46+19 (n-1)+4W
PS:
2
10+2W [6]
EA+18+4W [EA+14+4W]
DS1
PS
11+2W [7]
11+2W [7]
4
SS
DSO
11+2W [7]
11+2W [7]
regB
reg16
5
5
PSW
R
10+2W [6]
B2+16W [50]
memB
mem16
EA+11+2W [EA+9+W]
EA+15+4W [EA+11+2W]
immB
imm16
13+2W [9]
14+2W [10]
regB
reg16
5
5
memB
mem16
EA+11+2W [EA+9+W]
EA+15+4W [EA+11+2W]
PUSH
CY
2
REP
2
regB, CL
reg16, CL
7
7
REPE
2
REPZ
2
REPC
2
memB, CL
mem16, CL
EA+13+2W [EA+11+W]
EA+17+4W [EA+13+2W]
regB, imm3
reg16, imm4
6
6
REPNC
2
REPNE
2
memB, imm3
mem16, imm4
EA+10+2W [EA+B+W]
EA+14+4W [EA+10+2W]
REPNZ
regB, regB
reg16, reg16
2
2
regB, memB
reg16, mem16
EA+6+W
EA+B+2W
memB, regB
mem16, reg16
EA+B+2W [EA+6+W]
EA+12+4W [EA+B+2W]
regB, immB
reg16, imm16
5
6
memB, immB
mem16, imm16
RET
ED
2
null
pop-value
20+2W
20+2W
null
pop-value
29+4W
30+4W
RETI
43+6W [35+2W]
RETRBI
12
regB,1
reg16, 1
B
B
EA+9+2W [EA+7+2W]
EA+14+4W [EA+10+4W]
memB,1
mem16,1
EA+14+2W [EA+12+W]
EA+1B+4W [EA+14+2W]
AL, immS
AW, imm16
5
6
regB, CL
reg16, CL
11+2n
11+2n
immB, AL
immB, AW
10+W
10+2W
memB, CL
mem16, CL
EA+17+2W+2n [EA+15+W+2n]
EA+21+4W+2n [EA+ 17+2W+2n]
DW,AL
DW,AW
9+W
9+2W
regB, immB
reg16, immB
9+2n
9+2n
DW,memB
DW, mem16
19+2W [17+2W]
21+4W [17+4W]
memB, immB
mem16, immB
EA+13+2W+2n [EA+11+W+2n]
EA+17+4W+2n [EA+ 13+2W+2n]
DW,memB
DW, mem16
1B+(13+2W)n [1B+(11+2W)n]
1B+(15+4W)n [1B+11+4W)n]
regB
memB
17
EA+1B+2W [EA+16+2W]
ROL
ROL4
0
ROLC
reg16
mem16
12+2W
EA+16+4W [EA+12+2W]
ROR
DS1
SS
13+2W
13+2W
DSO
PSW
13+2W
14+2W
R
B2+16W [5B]
POLL
POP
Mnemonic
reg16
mem16
NOP
NOT
Clocks
ROR4
Same as ROL
Same as ROL
regB
memB
RORe
SET1
21
EA+24+2W [EA+22+2W]
Same as ROL
CY
DIR
2
2
51
NEe
pPD70320/322 (V25)
Instruction Clock Count (cant)
Mnemonic
Operand
SET1 (cont) reg8, CL
reg16, CL
Clocks
Mnemonic
Operand
Clocks
7
7
XCH
reg8, reg8
reg16, reg16
3
3
mem8, CL
mem16, CL
EA+13+2W [EA+11+W]
EA+17+4W [EA+13+2W]
reg8, mem8
reg16, mem16
EA+10+2W [EA+8+2W]
EA+14+4W [EA+10+4W]
reg8, imm3
reg16, imm4
6
6
mem8, reg8
mem16, reg16
EA+10+2W [EA+8+2W]
EA+14+4W [EA+10+4W]
mem8, imm3
mem16, imm4
EA+10+2W [EA+8+W]
EA+14+4W [EA+10+2W]
AW,reg16
reg16, AW
4
4
SHL
Same as ROL
SHR
Same as ROL
SHRA
Same as ROL
2
SS:
STM
mem8
mem16
12+2 [10]
16+(10+2Wln [16+(6+2Wln]
STMB
mem8
16+(8+Wln [16+(6+W)n]
STMW
mem16
Same as ADD
SUB
SUB4S
22+(27+3Wln [22+(25+3Wln]
SUBC
TEST
TEST1
14+2W [10]
0
STOP
Same as ADD
reg8, reg8
reg16, reg16
4
4
reg8, mem8
reg16, mem16
EA+8+W
EA+10+2W
mem8, reg8
mem16, reg16
EA+8+W
EA+10+2W
reg8, imm8
reg16, imm16
7
mem8, imm8
mem16, imm16
EA+11+W
EA+11+2W
AL, imm8
AW, imm16
5
6
reg8, CL
reg16, CL
7
7
mem8, CL
mem16, CL
EA+11+W
EA+13+2W
reg8, imm3
reg16, imm4
6
6
mem8, imm3
mem16, imm4
EA+8+W
EA+10+2W
8
TRANS
10+W
TRANSB
10+W
TSKSW
11
52
XOR
Same as AND
NEe
pPD70320/322 (V25)
Execution Clock Counts for Operations
Byte
RAM Enable
Word
RAM Disable
Context switch interrupt (Note 1)
DMA (Single-step mode) (Note 2)
20+2W
DMA (Demand release mode)
20+2W
RAM Enable
RAM Disable
27
27
24+4W
24+4W
15+W
15+W
17+2W
17+2W
DMA (Burst mode)
(12 + 2W)n
(12 + 2W)n
(12 + 4W)n
(12 + 4W)n
DMA (Single-transfer mode)
33+W+N
33+W+N
35 + 2W + N
35 + 2W + N
62+6W
62+6W
Interrupt (lNT pin)
Macro service, sfr - mem (Note 2)
24+W
19+W
26+2W
21 +2W
Macro service, mem - sfr
22+W
20+W
22+2W
22+2W
58 + 10W
58 + 10W
Macro service (Search char mode), sfr - mem
27+W
27+W
Macro service (Search char mode), mem - sfr
37+W
34+W
Priority vectored interrupt, including NMI (Note 1)
N = number of clocks to complete the instruction currently executing.
Notes:
(1) Every interrupt (except NMI) has an additional associated
latency time of 27 + N clocks. During the 27 clocks, the interrupt
controller performs some overhead tasks such as arbitrating
priority. This time should be added to the above listed interrupt
and macro service execution times. NMllatency time is 18 + N
clocks.
(2) The DMA and macro service clock counts listed are the required
number of CPU clocks for each transfer.
(3) When an external interrupt is asserted, a maximum of 6 clocks is
required for internal synchronization before the interrupt request
flag is set. For an internal interrupt, a maximum of 2 clocks
is required.
Bus Controller Latency
Mode
HLDRQ latency
DMA request latency (Note 1)
Clocks
7+2W
Burst
29+ N
Single step
29+ N
Demand release
29+ N
Single transfer
31 + N
Notes:
(1) The listed DMA latency times are the maximum number of clocks
when a DMA request is asserted until DMAAK or MREQ goes low
in the corresponding DMA cycles. The test conditions are no
wait states, no interrupts, no macro service requests, and no hold
requests.
53
~
IiiiI
0'1
.J:>.
Instruction Set
1::
Operation Code
Mnemonic
Operand
7 6 5 4 3 2
Operation
6 5 4 3 2 1 0
0
No. of
Bytes AC
Flags
CY V P S
z
Data Transfer
MOV
reg, reg
reg -
mem, reg
(mem) -
o1
o0
000
reg
000
reg
reg, mem
reg -
mem, imm
(mem)-imm
reg, imm
reg -
acc, dmem
When W = 0 AL When W = 1 AH -
000 1 0
(mem)
000
imm
(dmem)
(dmem + 1), AL -
0
1 W
0
o
0
000
W
reg
reg
2
W mod
reg
mem
2-4
W mod
reg
mem
2-4
mem
3-6
W mod 000
N
0
"W
N
N
0 0 0 W
.......
3
<
N
(dmem)
dmem, acc
When W = 0 (dmem) - AL
When W = 1 (dmem + 1) - AH, (dmem) -
sreg, reg16
sreg -
reg16 sreg : SS, OSO, OS1
sreg, mem16
sreg -
(mem16) sreg : SS, OSO, OS1
reg16, sreg
reg16 -
mem16, sreg
(mem16) -
OSO, reg16,
mem32
OS1, reg16,
mem32
W
3
(II
......
AL
0 1 1 0
000
sreg
reg
000
1 0 mod
0
sreg
mem
2-4
000
0 1 1 0
sreg
reg
2
000 1
o
o
0 mod 0
sreg
mem
2-4
reg16 - (mem32)
OSO - (mem32 + 2)
000
0
mod
reg
mem
2-4
reg16 - (mem32)
OS1 - (mem32 + 2)
000
o
0 mod
reg
mem
2-4
reg
mem
2-4
sreg
sreg
o
o
0 1
1
0 1
1 0
AH, PSW
AH -
PSW, AH
S, Z, x, AC, x, P, x, CY -
LOEA
reg16, mem16
reg16
TRANS
src-table
AL-(BW+AL)
XCH
reg, reg
reg-reg
000 0
W1
1
reg
reg
mem, reg
or reg, mem
(mem)-reg
000 0
W mod
reg
mem
AW, reg16
or reg16, AW
AW-reg16
o
S, Z, x, AC, x, P, x, CY
-+-
0
W
2-3
reg
AH
000 1
mem16
0
0
x
x x x
1
0
0
x
mod
0
"D.....
2
2-4
reg
Repeat Prefixes
REPC
While CW op 0, the next byte of the primitive block
transfer instruction is executed and CW is
decremented (- 1). If there is a waiting interrupt,
it is processed. When CY op 1, exit the loop.
o
1 1
o
0 1
o
1
REPNC
While CW op 0, the next byte of the primitive block
transfer instruction is executed and CW is
decremented (- 1). If there is a waiting interrupt,
it is processed. When CY op 0, exit the loop.
o
1 1
o
0 1
o
0
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
7 6 5 4 3 2
Operation
07654321 0
No. of
Bytes AC
Flags
CY V P S Z
Repeat Prefixes (cont)
REP
REPE
REPZ
While CW =F 0, the next byte of the primitive block
transfer instruction is executed and CW is
decremented (- 1). If there is a waiting interrupt, it is
processed. If the primitive block transfer instruction
is CMPBK or CMPM and Z =F 1, exit the loop.
o
0
REPNE
REPNZ
While CW =F 0, the next byte of the primitive block
1 1 1 1
transfer instruction is executed and CW is
decremented (- 1). If there is a waiting interrupt, it is
processed. If the primitive block transfer instruction
is CMPBK or CMPM and Z =F 0, exit the loop.
o
0 1 0
~
~
Primitive Block Transfer
MOVBK
dst-block,
src-block
When W = 0 (IV) - (IX)
DIR = 0: IX - IX + 1, IV - IV + 1
DIR = 1: IX -IX -1, IV -IV-1
When W = 1 (IV + 1, IV) - (IX + 1, IX)
DIR = 0: IX - IX + 2, IV - IV + 2
DIR = 1: IX -IX - 2, IV - IV - 2
1
1
o
0 1 0 W
CMPBK
src-block,
dst-block
When W = 0 (IX) - (IV)
DIR = 0: IX -IX + 1, IV -IV + 1
DIR = 1: IX - IX - 1, IV - IV - 1
When W = 1 (IX + 1, IX) - (IV + 1, IV)
DIR = 0: IX - IX + 2, IV - IV + 2
DIR = 1: IX - IX - 2, IV - IV - 2
1 0 1
o
0 1 1 W
x
x
x x x x
CMPM
dst-block
When W = 0 AL - (IV)
DIR = 0: IV - IV + 1; DlR = 1: IV When W = 1 AW - (IV + 1, IV)
DIR = 0: IV - IV + 2; DIR = 1: IV -
o
o
1 1 1 W
x
x
x x x x
1
o
1
IV -1
IV - 2
LDM
src-block
W~en
W = 0 AL - (IX)
DIR = 0: IX -IX + 1; DlR = 1: IX -IX-1
WhenW=1 AW-(IX+1,IX)
DIR = 0: IX - IX + 2; DlR = 1: IX - IX - 2
1 0 1 0 1 1 0 W
STM
dst-block
When W = 0 (IV) - AL
DIR = 0: IV - IV + 1; DIR = 1: IV -
1
When W
=
1 (IY
+ 1, IY)
-
o
1 0 1
o
1:::
"D......
0
1 W
W
IV -1
~
AW
0
DIR = 0: IV -IV + 2; DlR = 1: IV -IV - 2
"W
Bit Field Transfer
INS
reg8, reg8
16-Bit field -
AW
o
0 0 0 1 1 1 1
reg
reg
1 1
o
0
reg8, imm4
16-Bit field -
AW
o
o
0
0 0 0 1 1 1 1
reg
1 1 000
o
0
3
0
4
~
~
........
<
~
CIt
........
OJ
OJ
II
01
0')
'l:::
Instruction Set (cont)
Operation Code
Mnemonic
Operation
7 654 3 2
regS, regS
AW -16-Bit field
o
regS, imm4
AW -
o
acc, immS
When W = 0 AL When W = 1 AH -
(immS)
(immS + 1), AL -
acc, OW
When W = 0 AL When W = 1 AH -
(OW)
(OW +1), AL -
Operand
0
0
65432
No. of
Bytes AC
11
Flags
CY V P S Z
Bit Field Transfer (cont)
EXT
0 0 0
reg
1 1
0
W
3
0
reg
~.
0 0 0 1 1 1 1
1 1 000
reg
16-Bit field
o
0
o
0
1
,W
0
4
I/O
IN
OUT
-
immS, acc
OW, acc
o
o
W
o
W
N
N
2
(immS)
-""""'"
0
<
N
(OW)
When W= 0 (immS) - AL
When W = 1 (immS + 1) - AH, (immS) When W = 0 (OW) - AL
When W = 1 (OW + 1) - AH, (OW) -
0
a
.-..
o
ell
2
W
0
"-'"
AL
W
0
AL
Primitive Block I/O Transfer
INM
dst-block, OW
When W = 0 (lY) - (OW)
OIR = 0: IY .(.-IY + 1; OIR = 1: IY -IY-1
When W = 1 (IY + 1, IY) - (OW + 1, OW)
OIR;= 0: IY -IY + 2; OIR = 1: IY -IY - 2
o
1 1 0 1 1 0 W
OUTM
OW, src-block
When W = 0 (OW) - (IX)
OIR = 0: IX -IX + 1; OIR = 1: IX -IX-1
When W = 1 (OW + 1.. OW) - (IX + 1, IX)
OIR = 0: IX - IX + 2; DIR = 1: IX - IX - 2
o
1 1 0 1 1 1 W
reg, reg
reg -
0
mem, reg
(mem) -
reg, mem
reg -
reg + (mem)
o
o
o
reg + imm
Addition/Subtraction
AOO
reg + reg
(mem) + reg
reg, imm
reg -
mem, imm
(mem)-(mem)+imm
acc, imm
When W = 0 AL - AL + imm
When W = 1 AW -:- AW + imm
W 1 1
reg
reg
0 0 0 0 0 0 W mod
reg
mem
2-4
reg
mem
2-4
0
000
o
0 0 1 W mod
OOOOOSW1
o
o
1 000
0 0 0 0 S W mod 0 0 0
0 0 0 0
o
W
2
reg
3-4
mem
3-6
2-3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
7 654 3 2
Operation
5 4 3 2 1 0
0
No. of
Bytes AC
Flags
CV V P S Z
Addition/Subtraction (cont)
ADDC
reg, reg
mem, reg
reg, mem
reg, imm
mem, imm
ace, imm
SUB
SUBC
+ reg + CY
(mem) - (mem) + reg + CY
reg - reg + (mem) + CY
reg - reg + imm + CY
(mem) - (mem) + imm + CY
When W = 0 AL - AL + imm + CY
When W = 1 AW - AW + imm + CY
000
o
o
o
reg -
reg
reg, reg
reg -
mem, reg
(mem) -
reg, mem
reg -
reg - (mem)
reg, imm
reg -
reg - imm
reg - reg
(mem) - reg
000
o
0 0 1
o
000
3-4
3-6
2-3
W
reg
2
reg
mem
2-4
0
0
1 W mod
reg
mem
2-4
reg
3-4
mem
3-6
000
(mem) -
(mem) -- (mem) - imm - CY
reg
mem
reg
reg -
When W = 0 AL - AL - imm - CY
When W = 1 AW - AW - imm - CY
1 0
W 1 1
reg, reg
ace, imm
0
o
0 W mod
mem, reg
mem, imm
o
0
OOOOOSW1
o
0
0 0 1
o
o
o
o
1
2-3
1 W 1 1
reg
reg
0 W mod
reg
mem
reg
1 W mod
1
0 0 0 0 S W mod
000
1
W
OOOOOSW1
o
1 1 0
0 0 0 0 S W mod
000
o
1 0
0
o
reg - (mem) - CY
2-4
2-4
o
o
0
reg - imm - CY
mem
mem
0
1
reg -
reg
reg
0
o
reg -
0 0 W mod
0 1 W mod
0
(mem)-(mem)-imm
reg, imm
reg
0
When W = 0 AL - AL - imm
When W = 1 AW - AW - imm
reg, mem
reg
W
0 0 0 0 S W mod
mem, imm
(mem) - reg - CY
0
OOOOOSW1
1
ace, imm
reg - reg - CY
o
o
o
1 0 W
o
o
2-4
mem
2-4
1 1
reg
3-4
1 1
mem
3-6
2-3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
~
~
x
x
x
1:::
"a
~
0
w
~
0
"W
~
~
.......
<
~
en
...,
(Jl
--..J
I
(]1
ex>
l:::
Instruction Set (cont)
Operation Code
Mnemonic
Operand
No. of
Operation
7 654 3 2
ADD4S
dst BCD string - dst BCD string
+ src BCD string
o
0 0 0
o
0
000
SUB4S
dst BCD string - dst BCD string
- src BCD string
o
0 0 0
o
0
CMP4S
dst BCD string - src BCD string
o
o
0 0 0
o
o
5 4 3 2 1 0
Flags
ROL4
reg8
AL
ALL
H
reg
Upper 4 bits
I
Lower 4 bits
~
0 0 0 1
1 1 000
"a.....
Bytes AC
CV
V P S Z
0
2
x
u u u x
W
000
0
2
x
u u u x
0
0
o
0 1
0
2
x
u u u x
0
0
0
0
3
0
BCD Operation
0
~
'-W
~
~
.........
reg
<
~
UI
......,
mem8
AL
0
ALL
ROR4
H
mem
Upper4bits
I
Lower 4 bits
I·
ALL
t
H
mem8
AL
ALL
t
H
reg
Upper 4 bits
I
Lower 4
b~
mem
Upper 4 bits
I
Lower 4 bits
I
0 0 0 1 1 1 1
mod 000
mem
o
0 1 0 1 000
o
0 0 0 1 1 1 1
1 1 000
reg
o
0 1
o
1
o
o
0 1
o
1 0 1 0
3-5
I
reg8
AL
o
o
1 0
3
I
0 0 0
mod o 0
1 1 1
mem
3-5
I
BCD Adjust
ADJBA
ADJ4A
When (AL AND OFH) >9 or AC = 1,
AL - AL + 6, AH - AH + 1, AC GY - AG, AL - AL AND OFH
When
AL When
AL -
(AL AND OFH) >9 or AC = 1,
AL + 6, CY - CY OR AC, AC AL > 9FH, or CY = 1
AL + 60H, CY - 1
ADJBS
When (AL AND OFH) >9 or AC = 1,
CY -- AC, AL - AL AND OFH
ADJ4S
When
AL When
AL -
o
0 1 1
o
0 1
o
0
o
0
o
1 1 1
x
x
u u u u
0 1 1 1
x
x
u x x x
x
x
u u u u
x
x
u x x x
1,
o
1,
(AL AND OFH) >9 or AG = 1,
AL - 6, CY - CY OR AC, AC -- 1,
AL > 9FH, or CY = 1
AL + 60H, CY - 1
0
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
7 6 543 2 1 0
Operation
65432 1 0
No. of
Bytes AC
Flags
CY V P S Z
x
x x x x
Increment/Decrement
INC
OEC
reg8
reg8 -
reg8 + 1
+1
+1
mem
(mem) -
reg16
reg16 -
reg16
reg8 - 1
reg8
regB -
mem
(mem) -
reg16
reg16 -
0 1 1 000
1 1 1
(mem)
0
o
0 0
W mod
1
0
reg16 - 1
o
1 W mod
0
0 0
mem
2-4
reg
1 1 0 1 1
(mem) - 1
o
reg
o
o
0
reg
0
mem
2-4
reg
x
x x x x
x
x x x x
x
x x x x
x
x x x x
x
x x x x
~
~
Multiplication
MULU
reg8
memB
MUL
1 1 1 1 0 1 1 0 1 1 1 0 0
AW - AL x reg8
AH = 0: CY - 0, V AH ¥ 0: CY - 1, V -
0
1
AW - AL x (memB)
AH = 0: CY - 0, V AH ¥ 0: CY - 1, V -
0
1
1 1 1 1 0 1 1 0 mod
1 0 0
reg
2
x
x u u u
mem
2-4
x
x u u u
x
x u u u
reg16
OW, AW - AW x reg16
OW = 0: CY - 0, V - 0
OW ¥ 0: CY - 1, V - 1
1 1 1 1 0 1 1 1 1 1 1 0 0
reg
mem16
OW, AW - AW x (mem16)
OW = 0: CY - 0, V - 0
OW ¥ 0: CY -- 1, V - 1
1 1 1 1 0 1 1 1 mod
mem
2-4
x
x u u u
reg8
AW - AL x reg8
AH = AL sign expansion: CY AH ¥ AL sign expansion: CY -
reg
2
x
x u u u
0, V 1, V -
0
1
AW - AL x (mem8)
AH = AL sign expansion: CY AH ¥ AL sign expansion: CY -
mem
2-4
x
x u u u
0, V 1, V -
0
1
mem8
1 0 0
1 1 1 1 0 1 1 0 1 1 1 0 1
1 1 1 1 0 1 1 0 mod
1 0 1
"t::
reg16
OW, AW - AW x reg16
OW = AW sign expansion: CY - 0, V - 0
OW ¥ AW sign expansion: CY -1, V-1
1 1 1 1 0 1 1 1 1 1 1 0 1
mem16
OW, AW - AW x (mem16)
OW = AW sign expansion: CY - 0, V - 0
OW ¥ AW sign expansion: CY -1, V-1
1 1 1 1 0 1 1 1 mod
reg16,
reg16,
immB
reg16 - reg16 x imm8
Product::; 16 bits: CY Product> 16 bits: CY -
0 1 1 0 1 0 1 1 1 1
reg16,
mem16,
immB
reg16 - (mem16) x imm8
Product::; 16 bits: CY - 0, V -- 0
Product> 16 bits: CY - 1, V - 1
0, V 1, V -
reg
2
x
x u u u
2-4
x
x u u u
"a
0
1 0 1
mem
---
(.)
N
0
reg
reg
3
x
x u u u
0
1
0 1 1 0 1 0 1 1 mod
reg
mem
3-5
x
x u u u
"(.)
N
N
.......
<
N
ell
01
c.o
"-'"
B
0>
o
Operation Code
Mnemonic
o
No. of
Operation
7 6 5 4 3 2
reg16,
reg16,
imm16
reg16 +- reg16 x imm16
Product::; 16 bits: CY +- 0, V+-~
Product> 16 bits: CY +- 1, V+-1
o
reg16,
mem16,
imm16
reg16 +- (mem16) x imm16
Product::; 16 bits:CY +- 0, V+-O
Product> 16 bits: CY .:- 1, V+-1
o
temp +- AW
When temp -:- regS> FFH
(SP-1, SP - 2) +- PSW, (SP - 3, SP - 4) +- PS
(SP - 5, SP - 6) +- PC, SP +- SP - 6
IE +- 0, BRK +- 0, PS +- (3, 2), PC +- (1, 0)
All other times
AH +- temp % regS, AL +- temp -:- regS
1 1 1 1 0 1 1 0 1 1 1 1 0
memS
temp +- AW
When temp -:- (memS) > FFH
(SP -1, SP - 2) +- PSW, (SP - 3, SP - 4) +- PS
(SP - 5, SP - 6) +- PC, SP +- SP - 6
IE +- 0, BRK +- 0, PS +- (3, 2), PC +- (1, 0)
All other times
AH .;..- temp % (memS), AL +- temp -:- (memS)
1 1 1 1 0 1 1 0 mod
reg16
temp +- AW
When temp -:- reg16> FFFFH
(SP -1, SP - 2) +- PSW, (SP - 3, SP - 4) +- PS
(SP - 5, SP - 6) .;..- PC, SP +- SP - 6
IE +- 0, BRK +- 0, PS +- (3, 2), PC +- (1, 0)
All other times
AH +- temp % reg16, AL +- temp -:- reg16
mem16
temp +- AW
When temp -:- (mem16) > FFFFH
(SP -1, SP- 2) +- PSW, (SP - 3, SP - 4) +- PS
(SP - 5, SP - 6) +- PC, SP +- SP - 6
IE +- 0, BRK +- 0, PS +- (3, 2), PC +- (1, 0)
All other times
AH +- temp % (mem16), AL +- temp -:- (mem16)
Operand
6543210
Flags
o
o
0
reg
reg
reg
mem
CY
V P S Z
4
x
x u u u
W
N
4-6
x
xuuu
"W
regS
o
o
1 1 0 1 0 0 1 mod
N
N
Unsigned Division
DIVU
....
Bytes AC
Multiplication· (cont)
MUL (cant)
,.a
1:::
Instruction Set (cont)
reg
u u u u
<
N
"""'"""
ell
......,
mem
2-4
u u u u
1 1 1 1 0 1 1 1 1 1 1 1 0
reg
2
u u u u
1 1 1 1 0 1 1 1 mod
mem
2-4
1 1 0
1 1 0
u
u u u u
~
~
Instruction Set (cont)
Mnemonic
Operand
Operation
Operation Code
765432
0
654321
0
No. of
Bytes AC
Flags
CY V P S Z
Signed Division
DIV
reg8
temp-AW
When temp -;- reg8 > 0 and temp -;- reg8 > 7FH or
temp +- reg8 < 0 and temp -;- reg8 < 0 - 7FH - 1
(SP -1, SP - 2) - PSW, (SP - 3, SP - 4) - PS
(SP - 5, SP - 6) - PC, SP -+- SP - 6
IE -+- 0, BRK - 0, PS - (3, 2), PC - (1, 0)
All other times
AH - temp % reg8, AL - temp -;- reg8
mem8
temp - AW
When temp -;- (mem8) > 0 and (mem8) > 7FH or
temp -;- (mem8) < 0 and
temp -;- (mem8) < 0 - 7FH - 1
(SP ~ 1, SP - 2) -+- PSW, (SP - 3, SP - 4) -+- PS
(SP - 5, SP - 6) - PC, SP -+- SP - 6
IE - 0, BRK +- 0, PS - (3, 2), PC - (1, 0)
All other times
AH - temp % (mem8), AL - temp -;- (mem8)
1 1 1 1 0 1 1 0 mod
reg 16
temp - DW,AW
When temp +- reg 16> 0 and reg 16> 7FFFH or
temp -;- reg 16 < 0 - 7FFFH - 1
(SP -1, SP - 2) - PSW, (SP - 3, SP - 4) - PS
(SP - 5, SP - 6) - PC, SP - SP - 6
IE - 0, BRK - 0, PS - (3, 2), PC - (1, 0)
All other times
AH - temp % reg. 16, AL - temp -;- reg 16
1 1 1 1 0 1 1 1 1 1 1 11
mem 16
temp - DW, AW
When temp -;- (mem 16) > 0 and (mem 16) > 7FFFH
or temp -;- (mem 16) < 0 and temp -;- [mem 16]
<0 - 7FFFH-l
(SP - 1, SP - 2)) - PSW, (SP -3, SP - 4) -+- PS
(SP - 5, SP - 6) -+- PC, SP -+- SP - 6
IE -+- 0, BRK -+- 0, PS -+- (3, 2), PC -+- (1, 0)
All other times
AH - temp % (mem 16), AL -+- temp -;- (mem 16)
1 1 1 1 0 1 1 1 mod
0
reg
0
1 11
1 11
mem
2
2-4
~
~
u u u u
u u u u
reg
mem
u u u u u
2-4
u u u u
,.
1:::
a
....
o
w
~
o
"W
N
N
.......
<
N
UI
-.....
~
II
0>
I\)
Instruction Set (cont)
Mnemonic
Operand
Operation
o
076 5 4 3 2
7 654 3 2
No. of
Bytes AC
Flags
CY V P S Z
Data Conversion
o
01000000
o
o
2
u
u x x x
o
01010000
o
o
2
u
u x x x
CVTBD
AH -
AL + OAH, AL -
CVTDB
AH -
0, AL -
CVTBW
When AL < 8OH, AH - 0,
all other times AH - FFH
o
CVTWL
When AL < 8OOOH, OW - 0,
all other times OW - FFFFH
001100
AL %OAH
AH x OAH
+ AL
0
000
--a
o
W
N
o
"
W
N
~
---.
Comparison
CMP
,.a
l:::
Operation Code
2
x
x
mem
2-4
x
x
x x x x
mem
2-4
x
x
x x x x
1 0 0 0 0 0 S W 1 1 1 1 1
reg
3-4
x
x
x x x x
1 0 0 0 0 0 S W mod 1 1 1
mem
3-6
x
x
x x x x
2-3
x
x
x x x x
reg, reg
reg - reg
0 0
0 1 W 1 1
reg
reg
mem, reg
(mem) - reg
0 0
reg, mem
reg - (mem)
0 0 W mod
reg
0 0 1 1 1 0 1 W mod
reg
reg, imm
reg - imm
mem, imm
(mem) - imm
ace, imm
When W = 0, AL - imm
When W = 1, AW - imm
0 0 1 1 1 1 0 W
x x x x
<
N
en
~
Complement
NOT
NEG
reg
reg -
mem
(mem) -
reg
reg
reg -
mem
(mem) -
0
W 1 1 0
0
reg
0
W mod 0
0
mem
2-4
1 1 1 1 0 1 1 W 1 1 0 1 1
reg
2
x
xxxxx
1 1 1 1 0 1 1 W mod 0 1 1
mem
2-4
x
x
x x x x
(mem)
reg + 1
(mem) + 1
2
Logical Operation
TEST
AND
reg, reg
reg AND reg
0 0 0 0
0 W 1 1
reg
reg
2
0
0 x x x
mem, reg
or reg, mem
(mem) AND reg
0 0 0 0
0 W mod
reg
mem
2-4
0
0 x x x
1 1 W 1 1 0 0 0
reg
3-4
o
0 x x x
1 1 W mod 0 0 0
mem
3-6
o
0 x x x
2-3
o
0 x x x
o
o
0 x x x
0 x x x
0 x x x
reg, imm
reg AND imm
mem, imm
(mem) AND imm
ace, imm
When W= 0, AL AND imm8
When W = 1, AW AND imm8
reg, reg
reg -
mem, reg
(mem) -
reg, mem
reg AND reg
(mem) AND reg
o
o
o
o
1 0 0 W
0010001W11
reg
reg
2
u
o
0 1 0 0 0 0 W mod
reg
mem
2-4
u
0 1 0 0 0 1 W mod
reg
mem
2-4
u
000000W11
o
reg
3-4
u
mem
3-6
o
o
o
2-3
o
o
reg -
reg AND (mem)
reg, imm
reg -
reg AND imm
mem, imm
(mem)-(mem)ANDimm
1 0 0 0 0 0 0 W mod 1 0 0
ace, imm
When W = 0, AL - AL AND imm8
When W = 1, AW - AW AND imm16
0010010W
0
0
x x x
0 x x x
0 x x x
;(
~
Instruction Set (cant)
Operation Code
Mnemonic
Operand
7 654 3 2
Operation
076543210
No. of
Bytes AC
Flags
CY V P S Z
Logical Operation (cant)
OR
XOR
reg OR reg
0 0
o
o
0
W
reg, reg
reg -
mem, reg
(mem) -
0 0 0 0 1 0 0 W mod
reg
mem
2-4
0
reg, mem
reg -
reg OR (mem)
0 0 0 0 1 0 1 W mod
reg
mem
2-4
0
0 x x x
reg, imm
reg -
reg OR imm
1 0 0 0 0 0 0 W 1 1 0 0 1
reg
3-4
0
0 x x x
1 0 0 0 0 0 0 W mod 0 0 1
mem
3-6
0
0 x x x
2-3
0
0 x x x
0 x x x
(mem) OR reg
(mem) OR imm
mem, imm
(mem) -
ace, imm
When W = 0, AL - AL OR imm8
When W = 1, AW - AW OR imm16
0 0 0 0 1 1 0 W
o
o
o
reg, reg
reg -
mem, reg
(mem) -
reg, mem
reg -
reg XOR (mem)
reg, imm
reg -
reg XOR imm
mem, imm
(mem) -
ace, imm
When W = 0, AL - AL XOR imm8
When W= 1, AW - AW XOR imm16
reg XOR reg
(mem) XOR reg
0 1 1 0 0 1 W 1 1
reg
reg
2
0 1 1 0 0 0 W mod
reg
mem
2-4
0 1 1 0 0 1 W mod
reg
mem
2-4
o
o
o
reg
3-4
o
0 x x x
mem
3-6
o
0 x x x
2-3
o
0 x x x
3
o
0 u u x
3-5
o
0 u u x
o
0 u u x
000000W11110
1 0 0 0 0 0 0 W mod 1 1 0
(mem) XOR imm
0 x x x
0011010W
~~
0 x x x
0 x x x
Bit Operation
3rd byte*
2nd byte*
TEST1
reg8, CL
regS bit no. CL = 0: Z regS bit no. CL = 1: Z -
memS, CL
(memS) bit no. CL = 0: Z (mem8) bit no. CL = 1: Z -
reg16, CL
reg16 bit no. CL = 0: Z reg16 bit no. CL = 1: Z -
mem16, CL
(mem16) bit no. CL = 0: Z (mem16) bit no. CL = 1: Z -
regS, imm3
reg8 bit no. imm3 = 0: Z reg8 bit no. imm3 = 1:Z -
mem8, imm3
(mem8) bit no. imm3 = 0: Z (mem8) bit no. imm3 = 1: Z -
1
0
1
0
1
0
1
0
1
0
1
000
o
0 0 0 1 1 0 0 0
reg
000
o
0 0 0 mod 0 0 0
mem
000
000
1 1 0 0 0
reg
3
000
000
mod 0 0 0
mem
3-5
u
o
0 u u x
u
o
0 u u x
000
00011000
reg
4
000
o
0 0 mod 0 0 0
mem
4-6
o
0 u u x
000
o
0
1 1 0 0 0
reg
4
o
0 u u x
000
o 0
mod 0 0 0
mem
4-6
o
0 u u x
0
reg16, imm4
reg16 bit no. imm4 = 0: Z reg16 bit no. imm4 = 1: Z -
mem16, imm4
(mem16) bit no. imm4 = 0: Z (mem16) bit no. imm4 = 1: Z -
1
0
1
0
2nd byte*
*Note: First byte = OFH
en
c.J
3rd byte·
m
,.
1:::
D
o--w
~
o
"w
~
~
.........
<
~
en
.......
C>
.;..
Mnemonic
Operand
Operation Code
Operation
Flags
No. of
7654321
07654321
0
Bytes AC
CY
Bit Operation (cant)
2nd byte*
NOT1
reg8, CL
reg8 bit no. CL -
mem8, CL
(mem8) bit no. CL -
reg8 bit no. CL
(mem8) bit no. CL
reg16, CL
reg16 bit no. CL -
mem16, CL
(mem16) bit no. CL -
reg16 bit no. CL
(mem16) bit no. CL
reg8, imm3
reg8 bit no. imm3 -
mem8, imm3
(memS) bit no. imm3 -
reg16, imm4
reg16 bit no. imm4 -
mem16, imm4
reg8 bit no. imm3
(mem8) bit no. imm3
(reg16) bit no. imm4
(mem16) bit no. imm4 -
(mem16) bit no. imm4
o
o
CY-Cy
reg8, CL
reg8 bit no. CL -
(memS) bit no. CL -
000
0
1 1 000
reg
3
0
mod 000
mem
3-5
1 1 000
reg
4
mod 0 0 0
mem
o
o
000
1 1 000
reg
4
mod 0 0 0
mem
4-6
o
000
0
000
reg16, CL
reg16 bit no. CL -
inem16, CL
(mem16) bit no. CL -
reg8, imm3
reg8 bit no. imm3 -
mem8, imm3
(mem8) bit no. imm3 -
reg16, im'm4
reg16 bit no. imm4 -
mem16, imm4
(mem16) bit no. imm4 -
0
0
0
0
0
<
......
'"
N
3rd byte*
x
1
3rd byte*
0
o
0
0 mod 000
1 1 000
0
1 1 000
0
1 mod 0 0 0
000
0
o
000
0
0 mod 000
000
0
000
0
000
0
o
o
o
o
N
N
...-..-
4-6
000
1
0
"W
3-5
000
o
--a
W
N
3
000
000
0
mem
0
1 1 1 1
mem8, CL
reg
mod 0 0 0
0
000
2nd byte*
CLR1
1 1 000
000
000
V P S Z
0
3rd byte*
2nd byte*
*Note: First byte = OFH
CY
,.a
"t::
Instruction Set (cant)
2nd byte*
*Note: First byte = OFH
CY
CY-O
1 1 1 1 1 0 0 0
DlR
DIR-O
1 1 1 1 1 1
o
1 1 000
reg
3
mem
3-5
reg
3
mem
3-5
reg
4
mem
4-6
1 1 000
reg
4
mod 0 0 0
mem
4-6
3rd byte*
0
0
~
~
Instruction Set (cont)
Mnemonic
Operand
Operation Code
7 6 5 4 3
Operation
0
5 4 3 2 1 0
0
000
No. of
Bytes AC
Flags
CY V P S Z
Bit Operation (cont)
SET1
000
0
(mem8) bit no. CL-1
000
0
o
o
reg16 bit no. CL -
000
0
0
000
0
0 1 1 000
000
o
o
o
000
0
1 1 000
000
0
mod
reg8, CL
reg8 bit no. CL -
mem8, CL
reg16, CL
mem16, CL
(mem16) bit no. CL -
reg8, imm3
reg8 bit no. imm3 -
mem8, imm3
(mem8) bit no. imm3 -
reg16, imm4
reg16 bit no. imm4 -
mem16, imm4
(mem16) bit no. imm4 -
1
1
1
000
1
1
1
1
2nd byte*
*Note: First byte
CY
CY-1
1 1 1 1 1
DIR
DIR-1
1
reg, 1
CY - MSB of reg, reg - reg x 2
When MSB of reg # CY, V-1
When MSB of reg = CY, V - 0
mem,1
CY - MSB of (mem), (mem) When MSB of (mem) # CY, V When MSB of (mem) = CY, V -
reg, CL
1
0 mod 000
1 1 000
1 mod
0 mod
000
000
000
reg
mem
reg
mem
reg
mem
reg
mem
3
3-5
3
~
~
3-5
4
4-6
4
4-6
3rd byte*
= OFH
o
0 1
0
Shift
SHL
o
0 0 W 1 1 1
o
0
reg
1
o
0
mem
1 1
o
0
reg
1
o
0
mem
1 1
o
0
reg
1 1
o
1
o
0 0 W mod
temp - CL, while temp # 0,
repeat this operation, CY - MSB of reg,
reg - reg x 2, temp - temp - 1
1 1
o
1
o
0 1 W1
mem, CL
temp - CL, while temp # 0,
repeat this operation, CY - MSB of (mem),
(mem) - (mem) x 2, temp - temp - 1
1 1
o
1
o
0 1 W mod
reg, imm8
temp - imm8, while temp # 0,
repeat this operation, CY - MSB of reg,
reg - reg x 2, temp + - temp - 1
1 1 OOOOOW1
temp + - imm8, while temp ¥- 0,
repeat this operation, CY + - MSB of (mem),
(mem) - (mem) x 2, temp - temp - 1
1
CY - LSB of reg, reg - reg -:- 2
When MSB of reg # bit following MSB
of reg: V-1
When MSB of reg = bit following MSB
of reg: V - 0
1 1
mem, imm8
SHR
0
reg, 1
(mem) x 2
1
0
2-4
2-4
x
x x x x
x
x x x x
x
u x x x
x
u x x x
x
u x x x
1:::
"a--a
0
W
~
1
o
0 0 0 0 W mod
o
1
o
1
o
0
0 0 W 1 1 1 0 1
mem
3-5
x
u x x x
0
"W
reg
2
x
x x x x
~
~
~
<
~
en
0>
~
CJ1
II
0>
0>
,.a
'l:::
Instruction Set (cont)
Mnemonic
Operand
Operation
Operation Code
Flags
No. of
1 6 5 4 3 2 1 0 1 6 543 2 1 0
Bytes AC
CY
V P S Z
-.a
Shift (cont)
SHR(cont)
SHRA
mem, 1
o
CY - LSB of (mem), (mem) - (mem) -;- 2
When MSB of (mem) oF bit following MSB
of (mem): V - 1
When MSB of (mem) == bit following MSB
of (mem): V - 0
1 1 0 1
reg, CL
temp - CL, while temp oF 0,
repeat this operation, CY - LSB of reg,
reg - reg -;- 2, temp - temp - 1
1 1 0 1
o
0 1 W1
mem, CL
temp - CL, while temp oF 0,
repeat this operation, CY - LSB of (mem),
(mem) - (mem) -;- 2, temp - temp - 1
1 1 0 1
o
0 1 W mod
reg, immB
temp - immB, while temp oF 0,
repeat this operation, CY - LSB of reg,
reg - reg -;- 2, temp - temp - 1
1 1
o
0
o
0 0 W 1 1 1 0 1
mem, immB
temp - immB, while temp oF 0,
repeat this operation, CY - LSB of (mem),
(mem) +- (mem) -;- 2, temp +- temp - 1
1 1
o
0
o
0 0 W mod
reg, 1
CY +- LSB of reg, reg +- reg -;- 2, V+-O
MSB of operand does not change
0
o
0 0 W 1 1
reg
mem,1
CY - LSB of (rriem), (mem) +- (mem) -;- 2,
V +- 0, MSB of operand does not change
0
o
0 0 W mod
mem
reg, CL
temp +- CL, while temp oF 0,
repeat this operation, CY +- LSB of reg,
reg +- reg -;- 2, temp +- temp - 1
MSB of operand does not change
0
o
0
mem,CL
temp +- CL, while temp oF 0,
repeat this operation, CY +- LSB of (mem),
(mem) +- (mem) -;- 2, temp +- temp - 1
MSB of operand does not change
1 1 0 1
o
0 1 W mod
reg, immB
temp +- immB, while temp oF 0,
repeat this operation, CY +- LSB of reg,
reg +- reg -;- 2, temp +- temp - 1
MSB of operand does not change
1 1 00000W1
mem, immB
temp +- immB, while temp oF 0,
repeat this operation, CY +- LSB of (mem),
(mem) +- (mem) -;- 2, temp +- temp - 1
MSB of operand does not change
1 1
0 0 W mod
1 0 1
mem
2-4
0
CiI)
~
x x x x x
0
"W
1 1 0 1
1 0 1
reg
2
x u x x x
mem
2-4
x u x x x
~
~
"'"""-
<
N
c.n
~
o
0
o
W1
1 0 1
1
mem
reg
1 1 1
1 1 1 1
0 0 W mod
reg
1 1 1
mem
reg
mem
3
x u x x x
3-5
x u x x x
2
x
ox x x
2-4
x
ox x x
2
x u x x x
2-4
x u x x x
3
x u x x x
3-5
x u x x x
I
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
Operation
reg, 1
CY +- MSB of reg, reg +- reg x 2 + CY
MSB of reg -=F- CY: V+-1
MSB of reg = CY: V+-O
mem, 1
CY +- MSB of (mem),
(mem) +- (mem) x 2 + CY
MSB of (mem) -=F- CY: V+-1
MSB of (mem) = CY: V+-O
1 1
o
reg, CL
temp +- CL, while temp -=F- 0,
repeat this operation, CY +- MSB of reg,
reg +- reg x 2 + CY
temp +- temp - 1
1 1
mem, CL
temp +- CL, while temp -=F- 0,
repeat this operation, CY +- MSB of (mem),
(mem) +- (mem) x 2 + CY
temp +- temp - 1
1 1
reg, immB
temp +- immB, while temp -=F- 0,
repeat this operation, CY +- MSB of reg,
reg +- reg x 2 + CY
temp +- temp - 1
1 1 00000W1
mem, immB
temp +- immB, while temp -=F- 0,
repeat this operation, CY +- MSB of (mem),
(mem) +- (mem) x 2 + CY
temp +- temp - 1
1 1
o
0 0 0 0 W mod
reg, 1
CY +- LSB of reg, reg +- reg -;- 2
MSB of reg +- CY
MSB of reg -=F- bit following MSB of reg: V+-1
MSB of reg = bit following MSB of reg: V+-O
1 1
o
1
o
mem, 1
CY +- LSB of (mem), (mem) - (mem) -;- 2
MSB of (mem) +- CY
MSB of (mem) -=F- bit following MSB
of (mem): V+-1
MSB of (mem) = bit following MSB
of (mem): V+-O
1 1
o
1
o
temp +- CL, while temp -=F- 0,
repeat this operation, CY +- LSB of reg.
reg +- reg -;- 2, MSB of reg +- CY
temp +- temp - 1
1 1
temp +- CL, while temp -=F- 0,
repeat this operation, CY +- LSB of (mem),
(mem) +- (mem) -;- 2, MSB of (mem) +- CY
temp +- temp - 1
1 1
765432
0
654321 0
No. of
Bytes AC
Flags
CY V P S Z
Rotation
ROL
ROR
reg. CL
mem, CL
o
0
W
o
1
o
0 0 W mod
000
o
1
o
o
1
o
0
0
reg
x
x
mem
2-4
x
x
0 1 W 1 1 000
reg
2
x
u
0 1 W mod
000
reg
2-4
x
u
1 000
reg
3
x
u
000
mem
3-5
x
u
0 0 W 1 1
o
0 1
reg
2
x
x
0 0 W mod
o
0 1
mem
2-4
x
x
~~
,.
1::::
D
-III
0
W
~
o
1
o
1
o
0 1 W 1 1
o
0 1 W mod
o
0 1
o
0 1
reg
mem
2-4
x
U
x
u
0
"W
~
~
~
<
~
en
()')
~
~
II
0)
0)
1::::
Instruction Set (cont)
Mnemonic
Operand
Operation
Bytes AC
CV
V P S Z
"....a
3
x
u
W
No. of
Operation Code
7 654 3 2
0
654321
0
Flags
Rotation (cont)
ROR (cont)
reg, immB
mem, immB
o
OOOOOW
temp - immB, while temp #- 0,
repeat this operation, CY - LSB of reg,
reg - reg -;- 2, MSB of reg - CY
temp - temp - 1
0
reg
0
~
0
o
0 0 0 0 W mod
o
0 1
mem
temp - immB, while temp #- 0,
repeat this operation, CY - LSB of (mem),
(mem) - (mem) -;- 2
temp - temp - 1
1 1
reg, 1
tmpcy - CY, CY - MSB of reg
reg - reg x 2 + tmpcy
MSB of reg = CY: V ~ 0
MSB of reg #- CY: V - 1
1 1
o
1
o
0 0 W 1 1
o
1 0
reg
mem,1
tmpcy - CY, CY - MSB of (mem)
(mem) - (mem) x 2 + tmpcy
MSB of (mem) = CY: V - 0
MSB of (mem) #- CY: V - 1
1 1
o
1
o
0 0 W mod
o
1 0
mem
reg, CL
temp - CL, while temp #- 0,
repeat this operation, tmpcy - CY,
CY - MSB of reg, reg - reg x 2 + tmpcy
temp - temp - 1
1 1
o
1
o
0 1 W 1 1
o
1 0
reg
mem, CL
temp - CL, while temp #- 0,
repeat this operation, tmpcy +- CY,
CY - MSB of (mem),
(mem) - (mem) x 2 + tmpcy
temp - temp - 1
1 1
o
1
o
0 1 W mod
o
1 0
reg, immB
temp - immB, while temp #- 0,
repeat this operation, tmpcy - CY,
CY +- MSB of reg, reg - reg x 2 + tmpcy
temp - temp - 1
1 1 00000W1
1
o
mem, immB
temp - immB, while temp ~ 0,
repeat this operation, tmpcy +- CY,
CY - MSB of (mem)
(mem) - (mem) x 2 + tmpcy
temp - temp -;- 1
1 1
0 0 0 0 W mod
o
3-5
x
u
~
N
......"
Rotate
ROLC
"W
o
x
x
2-4
x
x
2
x
u
mem
2-4
x
u
1 0
reg
3
x
u
1 0
mem
3-5
x
u
<
~
'"
........
;(
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
7 654 3 2
Operation
65432 1 0
0
No. of
Bytes AC
Flags
CY V P S Z
2
x x
2-4
x x
2
x u
Rotate (cont)
RORC
reg, 1
mem, 1
tmpcy - CY, CY - LSB of reg
reg - reg -:-- 2, MSB of reg - tmpcy
MSB of reg ~ bit following MSB of reg: V MSB of reg = bit following MSB of reg: V tmpcy - CY, CY - LSB of (mem)
(mem) - (mem) -:-- 2, MSB of (mem) MSB of (mem) ~ bit following MSB
of (mem): V - 1
MSBof (mem) = bit following MSB
of (mem): V - 0
0
o
0 0 W
0
reg
1
0
1 1
o
1
o
0 0 W mod
o
1 1
mem
tmpcy
reg, CL
temp - CL, while temp ~ 0,
repeat this operation; tmpcy - CY,
CY - LSB of reg, reg - reg -:-- 2,
MSB of reg- tmpcy, temp - temp-1
1 1
o
1
o
0 1 W1
1
o
1 1
reg
mem, CL
temp - CL, while temp ~ 0,
repeat this operation, tmpcy - CY,
CY - LSB of (mem), (mem) - (mem) -:-- 2
MSB of (mem) - tmpcy, temp - temp - 1
1 1
o
1
o
0 1 W mod
o
1 1
mem
2-4
x u
reg, immB
temp - immB, while temp ~ 0
repeat this operation, tmpcy - CY,
CY - LSB of reg, reg - reg -:-- 2
MSB of reg - tmpcy, temp - temp - 1
1 1 000OOW1 1
o
1 1
reg
3
x u
mem, immB
temp - immB, while temp ~ 0,
repeat this operation, tmpcy - CY,
CY - LSB of (mem), (mem) - (mem) -:-- 2
MSB of (mem) - tmpcy, temp - temp - 1
1 1
o
1 1
mem
3-5
x u
o
0 0 0 0 W mod
Subroutine Control Transfer
CALL
~
~
"t::
near-proc
(SP - 1, SP - 2) PC - PC + disp
PC, SP -
SP - 2
0
regptr16
(SP - 1, SP - 2) PC - regptr16
PC, SP -
SP - 2
1 1 0
SP - 2
mod 0
memptr16
(SP - 1, SP - 2) - PC, SP PC - (memptr16)
far-proc
(SP - 1, SP - 2) - PS, (SP - 3, SP - 4) SP - SP - 4, PS - seg, PC - offset
PC
memptr32
(SP - 1, SP - 2) - PS, (SP - 3, SP - 4) SP - SP - 4, PS - (memptr32 + 2),
PC +- (fnemptr32)
PC
o
0
3
000
0
0
0
reg
2
mem
2-4
0
5
mod
o
1 1
mem
2-4
"a--a
0
W
N
0
"W
N
N
......
<
N
VI
C>
co
II
---
.......
0
,.a
1:::-
Instruction Set (cont)
Mnemonic
Operllnd
Operation
Flags
No. of
Operation Code
7654321
07654321
0
Bytes AC
CY
V P S Z
.....
Subroutine Control Transfer (cont)
RET
pop-value
PC -
(SP + 1, SP), SP -
PC SP -
(SP + 1, SP)
SP + 2, SP -
PC SP -
0 0 0
1
0 0 0
0
W
N
3
0
SP + pop-value
(SP + 3, SP + 2)
o
0
0
(SP + 1, SP), PS - (SP + 3, SP + 2)
SP + 4, SP - SP + pop-value
o
0
0
PC - (SP + 1, SP ), PS SP-SP+4
pop-value
o
o
SP + 2
0
"W
0
N
N
3
--..
<
N
Stack Manipulation
PUSH
POP
PREPARE
1 1 1 mod
mem16
(SP -1, SP - 2) -
(mem16), SP -
reg16
(SP - 1, SP - 2) -
reg16, SP -
sreg
(SP-1, SP- 2) -
PSW
(SP - 1, SP - 2) -
R
Push registers on the stack
0
00000
imm
(SP -l;SP - 2) - imm
SP - SP - 2, When S == 1, sign extension
0
0
mem16
(mem16) -
reg16
reg16 -
sreg
sreg - (SP + 1, SP) sreg : SS, DSO, DS1
SP - SP+2
sreg, SP -
(SP + 1, SP), SP -
PSW
PSW -
R
Pop registers from the stack
imm16, immS
Prepare new stack frame
DISPOSE
(SP + 1, SP), SP -
SP - 2
SP - 2
PSW, SP -
(SP + 1, SP), SP -
SP - 2
SP - 2
SP + 2
SP + 2
o
o
0 0 sreg
1
o
1 0
0
o
o
0
2-3
S 0
mod 0 0 0
mem
2-4
reg
0 0 sreg
1 1
0 1 1 1 0
R
R R R R R
1 0 0 0 0 1
o
o
0
000
4
0
o
0
1
PC+ disp
0
o
0
3
0
0
Dispose of stack frame
en
-......
2-4
0
0 1 1 1
1 0
o
SP + 2
mem
reg
0
1 000
o
o
1 1 0
Branch
BR
near-label
PC -
short-label
PC -
PC + ext-dispS
regptr16
PC -
regptr16
memptr16
PC -
(memptr16)
far-label
PS -
seg, PC -
memptr32
PS -
(memptr32 + 2), PC -
1 1
1
0
offset
(memptr32)
1 mod
0
o
o
0
reg
0
mem
2-4
mem
2-4
5
0
mod
0
I
~
~
Instruction Set (cont)
Mnemonic
Operand
Operation Code
7 6 5 4 3 2
Operation
07654321
0
No. of
Bytes AC
Conditional Branch
BV
short-label
if V = 1, PC -
PC + ext-disp8
0
o
BNV
short-label
if V = 0, PC -
PC + ext-disp8
0
000
BC, Bl
short-label
if CY = 1, PC -
0
BNC,BNl
short-label
if CY = 0, PC -
0
o
o
BE,BZ
short-label
0
0
BNE, BNZ
short-label
0
0
BNH
short-label
0
BH
short-label
o
o
BN
short-label
BP
short-label
BPE
short-label
BPO
short-label
BLl
short-label
BGE
short-label
BlE
short-label
BGT
short-label
DBNZNE
short-label
DBNZE
DBNZ
short-label
short-label
PC + ext-disp8
+ ext-disp8
if Z = 1, PC - PC + ext-disp8
if Z = 0, PC - PC + ext-disp8
if CY OR Z = 1, PC - PC + ext-disp8
if CY OR Z = 0, PC - PC + ext-disp8
if S = 1, PC - PC + ext-disp8
if S = 0, PC - PC + ext-disp8
if P = 1, PC - PC + ext-disp8
if ,P = 0, PC - PC + ext-disp8
if S XOR V = 1, PC - PC + ext-disp8
if S XOR V = 0, PC - PC + ext-disp8
if (S XOR V) OR Z = 1, PC - PC + ext-disp8
if (S XOR V) OR Z = 0, PC - PC + ext-disp8
PC
CW-CW-1
if Z = 0 and CW =P 0, PC -
PC + ext-disp8
CW-CW-1
if Z = 1 and CW =P 0, PC -
PC + ext-disp8
CW-CW-1
if CW =P 0, PC -
PC + ext-disp8
PC + ext-disp8
0 0 0
0
short-label
if CW= 0, PC -
BTClR
sfr. imm3,
short-label
if bit no. imm3 of (sfr) = 1,
PC - PC + ext - disp8,
bitno. imm3 of (sfr) - 0
2
0
o
o
1
0
1
0
2
1 1 1
2
0
000
2
0
o
2
0
0
0
2
0
o
1 1
2
o
o
2
0
0
0
0
0
1 1
o
0
1
2
0
2
1
0
2
00000
2
000 0
2
2
0
000
2
1 0 0 1 1 1
0 0 0
o
0
5
3
imm8
(=p3)
:1
1:::
"a....
,
0
W
N
0
Interrupt
BRK
~
0
2
000
BCWZ
2
0
Flags
CY V P S Z
($P-1, SP - 2) - PSW, (SP - 3, SP - 4) (SP - 5, SP - 6) - PC, SP - SP - 6
IE-O,BRK-O
PS -(15, 14), PC - (13, 12)
PS,
(SP -1, SP- 2) - PSW, (SP -3, SP -4) (SP - 5, SP - 6) - PC; SP - SP - 6
IE-O, BRK-O
PC - (n x 4, + 1, n x 4)
PS - (n x 4 + 3, n x 4 + 2) n = imm8
PS.
1 1
o0
1 1
o
0
W
~
N
1 1
o
0 1 1
o
1
2
,.-..
<
N
en
.......
II
.......
I\)
,.a,
Instruction Set (cont)
Mnamonle
Operand
Interrupt (cont)
BRKV
RETI
1:::
Operation Code
7 654 3 2
Operation
When V =.1
(SP --, 1, SP - 2) - PSW, (SP - 3, SP - 4) (SP - 5, SP - 6) - PC, SP - SP - 6
IE:-O, BRK-O
PS - (19, 18), PC- {17, 16)
PC -
(SP+ 1, SP), PS -
RETRBI
PC -
Save PC, PSW -
~'NT
Indicates that interrupt service routine to the
interrupt controller built in the CPU has been
completed
CHKINO
o0
7 6 5 4 3 2 1 0
.....
0
w.
1 0
~
PS,
Q,
Save PSW
When (mem32) > reg16 or (mem32 + 2) < reg16
(SP -1, SP - 2) - PSW, (SP - 3;SP - 4) - PS,
(SP -5,SP - 6) - PC, SP - SP - 6
IE - 0, BRK - 0,
PS - (23, 22), PC - (21, 20)
"W
o0
(SP + 3, SP + 2),
SP + 6
psw- (SP + 5, SP + 4), SP -
reg16,
mem32
o
Flags
No. of
Bylas AC CYVPSZ
o0
o0
o
o0
o0
0 0
0 0
1 1 0 0 0 1 0 mod
o0
o0
0 1
2
0
2
R
RR R R R
R
R R R R R
N
N
.......
<
N,
en
-..,.,
reg
mem
1 1
1 1
2-4
CPU Control
HALT
CPU Halt
1
STOP
CPU Halt
o
BUS LOCK
Bus Lock Prefix
FP01 (Note 1) fp-op
fp-op,mem
FP02 (Note 1) fp-op
fp-op,mem
No Operation
0
o
No Operation
Poll and wait
o
0
NOP
No Operation
o
0
01
IE-O
EI
IE-1
OSO; OS1;
PS;SS
Segment override prefix
Notes:
(1) Does not execute on the V25, but does generate an interrupt.
X X X
0
011001
POLL
o
o
o0
YYYZZZ
Q
sreg
mem
2
2-4
X 1 1 Y Y Y ZZ Z
2
X mod Y Y Y
2-4
mem
1 1
0 0 0
0
1
1 0
0 0 0
1 1 X X X mod Y Y Y
o
0
(mem)
0
0
o
1
data bus""':' (mem)
data bus -
o
1 0
0 0 0
0
1
0
I
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
Operation
7 6 5 4 3 2
o 7 6 5 4 3 2
0
No. of
Bytes AC
Flags
CY V P S Z
Register Bank Switching
MOVSPA
BRKCS
MOVSPB
TSKSW
reg16
reg16
reg16
o
o
o
0 0 0
1 1 1 1
o
o
o
0 0 0
000
000
1 1 1 1
reg
1 1
reg
0 1 0 0
0
2
0 1 0 1
0
3
o
0
0
0
3
o
0
0
o
0
3
x
~
~
x x x x x
l:::
'11
a
o---
w
~
o
"w
~
~
........
,:
N
CII
-....I
"-'"
Ci.)
II
pPD70320/322 (V28)
74
NEe
NEe
NEe Electronics Inc.
Description
The pPD70330170332 (V35™) is a high-performance,
16-bit single-chip microcomputer with a 16-bit external
data bus. The pPD70330170332 is fully software compatible with pPD8086/8088 and pPD70108170116
(V20®/30®) instruction set.
The pPD70330 is a ROMless part. The pPD70332 has
16K ROM, while the pPD70P322 has 16K EPROM and
can be used as a pPD70330 (V35) or a pPD70320
(V25™).
Features
o Functionally compatible with pPD70320/322 (V25)
o Internal 16-bit architecture and external 16-bit
o
o
o
o
o
o
o
o
data bus
Software compatible with pPD8086/8088,
pPD70108170116 (V20/30) in the native mode
New and enhanced instructions
Six-byte prefetch queue
Minimum instruction cycle: 500 ns at 8 MHz
Internal memory
- ROM: 16K bytes (pPD70332 only)
- RAM: 256 bytes
Memory space: 1M bytes
Input port with comparator (port T): eight bits
Bus interface optimized for use with dynamic
RAMs
- Multiplexed address
- On-board refresh controller
V20 and V30 are registered trademarks of NEC Corporation.
V25 and V35 are trademarks of NEC Corporation.
50006-2 (NECEL-870)
pPD70330/70332 (V35)
is-Bit Microcomputers:
Advanced, Single-Chip, CMOS
o 24 parallel 1/0 lines
o Serial interface: two channels
- Dedicated baud rate generator
- Asynchronous mode, 1/0 interface mode
o Interrupt controller
- Programmable priority (eight levels)
- Three interrupt service functions
- Vectored interrupt, register bank switching,
macro service
o DRAM, pseudo SRAM refresh function
o Two DMA channels
o Two 16-bit timers
DOne 20-bit time base counter
o Clock generator
o Programmable wait function
o Low power modes
-HALT
-STOP
o 1.2-micron CMOS
Ordering Information
Package
Part Number
Clock (MHz)
pPD70330L-8
8
84-pin PLCC
8
94-pin plastic QFP
8
84-pin PLCC
8
94-pin plastic QFP
8
84-pin LCC
GJ-8
pPD70332L-8-xxx
GJ-8-xxx
pPD70P322KE-8
Internal ROM
ROMless
16K mask ROM
16K EPROM
(UVerasable)
Em
NEe
pPD70330/332 (V35)
Pin Configuration
84-Pln PLCC and 84-Pln LCC
P07/CLKOUT
74
PT7
Do
73
72
71
70
69
68
67
PT6
PT5
PT4
PT3
PT2
PT1
PTO
Ao
66
65
64
63
62
61
60
59
58
57
P17/REAOY
P16/SCKO
P15ITOUT
P14/1NT/POLL
P13/INTP2IINTAK
P12/1NTP1
P11/1NTPO
P10/NMI
P27/HLORO
P26/HLOAK
A9 /A 1
A10/A2
A11 /A 3
56
55
54
P25ITC1
P24/DMAAK1
P23/0MAR01
01
02
03
04
Os
06
07
08
09
0 10
011
0 12
013
014
015
* Connect pin 9 to GNO through a 5-kn to 10-kn resistor.
83YL-6633B
2
NEe
pPD70330/332 (V35)
Pin Configuration (cont)
94-Pin
Pla~tic
QFP
A12/A4
NC
A13 /A S
A14 /A S
A1S/A7
A1S /A S
A17 /A 1S
A19
A1S /UBE
RxDO
GND
CTSO
TxDO
RxD1
PO S
NC
*
P0 4
P03
P0 2
P0 1
POO
EX
MREQ
IOSTB
MSTB
RtW
REFRQ
RESET
CTS1
TxD1
P2Q/DMARQO
IC
VOO
VOO
VDD
VDD
P21/DMAAKO
GNO
GNO
NC
P22ITCO
X2
X1
NC
NC
VIN
*Connect pin 69 to GND through a 5-kn to 10-kn resistor.
83YL-66348
3
NEe
pPD70330/332 (V35)
Pin Identification
Symbol
Function
Symbol
Function
A19- AO
CLKOUT
Address bus outputs
RxD1
Receive data input, serial channel 1
System clock output
SCKO
Serial clock output
CTSO
Clear-to-send input, serial channel 0
TCO
CTS1
Clear-to-send input, serial channel 1
Terminal count output; DMA completion,
channel 0
D15- DO
DMAAKO
Bidirectional data bus
TC1
Terminal count output; DMA completion,
channel 1
TOUT
Timer output
TxDO
Transmit data output, serial channel 0
TxD1
Transmit data output, serial channel 1
UBE
Upper byte enable
X1, X2
Connections to external frequency control
source (crystal, ceramic resonator, or clock)
DMAAK1
DMAROO
DMA acknowledge output, DMA controller
channel 0
DMA acknowledge output, DMA
controller channel 1
DMA request input, DMA controller
channel 0
DMAR01
DMA request input, DMA controller
channel 1
Voo
+5-volt power source input (two pins)
EA
External access; clamped low or high
according to program access requirements
VTH
Threshold voltage input to comparator
circuits
HLDAK
Hold acknowledge output
GND
Ground reference (two pins)
HLDRO
Hold request input
IC
INT
Interrupt request input
Internal connection; must be tied to Voo
externally through a pullup resistor
INTAK
Interrupt acknowledge output
INTPO
Interrupt request 0 input
INTP1
Interrupt request 1 input
INTP2
Interrupt request 2 input
10STB
110 read or write strobe output
MREQ
Memory request output
MSTB
Memory strobe output
NMI
Nonmaskable interrupt request
POLL
Input on POLL synchronizes the CPU and
external devices
P07-POO
110 port 0
P1rP10
110 port 1
P27-P20
110 port 2
PTO-PT?
Comparator port input lines
READY
Ready signal input controls insertion of
wait states
REFRO
DRAM refresh request output
RESET
Reset signal input
R/W
Readlwrite strobe output
RxDO
Receive data input, serial channel 0
4
NEe
pPD70330/332 (V35)
Pin Functions
EA; External Access
A19-AO; Addres$ Bus
For the ROM-less pPD70330, connect this pin to
ground. For the pPD70332, connect EAto ground if
program code is in external memory; connect EA to +5
volts if program code isin the internal ROM.
To support dynamic RAMs, the 20-bit address is multiplexed on 11 lines. When MREQ is asserted, A17-A9 are
valid. When MSTB or 10STB are asserted, A8-A1 and A18
are valid. A18 is also multiplexed with UBE and is valid
when MREQ is asserted. ThereforeA18 is active throughout
the bus cycle. A 19 and Ao are not multiplexed but have
dedicated pins and are valid throughout the bus cycle.
CLKOUT; Clock Out
The system clock (ClK) is distributed from the internal
clock generator to the CPU and output to peripheral
hardware at the ClKOUT pin.
CTSO; Clear-to-Send 0
This is the CTS pin of the channel 0 serial interface. In
asynchronous mode, a low-level input on CTSO
enables transmit operation. In 1/0 interface mode,
CTSO is the receive clock pin.
CTS1; Clear-to-Send 1
This is the CTS pin of the channel 1 serial interface. In
asynchronous mode, a low-level input on CTS1
enables transmit operation.
015-00; Data Bus
D15-Do is the 16-bit data bus.
DMAAKO and DMAAK1; DMA Acknowledge
These are the DMA acknowledge outputs of the DMA
controller, channels 0 and 1. Signals are not output
during DMA memory-to-memory transfer operations
(burst mode, single-step mode).
OMARQO and DMARQ1; DMA Request
HLDAK; Hold Acknowledge
The HlDAK output signal indicates that the hold
request (HlDRQ) has been accepted. When HlDAK is
active (low), the following lines go to the high-impedance state with internal 4700-0~lIup resistors:
A 1fLAO, DrDo, IOSTB, MREQ, MSTB, REFRQ, and
R/W.
HLDRQ; Hold Request
The HlDRQ input from an external device requests
that the pPD70330/332 relinquish the address, data,
and control buses to an external bus master.
INT; Interrupt
The INT input is a vectored interrupt request from an
external device that can be masked by software. The
active high level is detected in the last clock cycle of an
instruction. The external device confirms that the INT
interrupt request has been accepted by the INTAK
signal output from the Cpu.
The INT signal must be held high until the first INTAK
signal is output. Together with INTAK, INT is used for
operation with an interrupt controller such as
pPD71059.
INTAK; Interrupt Acknowledge
The I NTAK output is the acknowledge signal for the
software-maskable interrupt request INT. The INTAK
signal goes low when the CPU accepts INT. The
external device inputs the interrupt vector to the CPU
via data bus D7-DO in synchronization with INTAK.
These are the DMA request inputs of the DMA controller, channels 0 and 1.
5
NEe
pPD70330/332 (V35)
INTPO, INTP1, INTP2; Interrupt from
Peripheral 0, 1, 2
The I'NTPn inputs (n = 0, 1, 2) are external interrupt
requests that can be masked by software. The INTPn
input is detected at the effective edge specified by
external interrupt mode register INTM.
The INTPn input is also used to release the HALT
mode.
10STS; 1/0 Strobe
A low-level output on 10STB indicates that the I/O bus
cycle has been initiated and that the I/O add ress output
on A15-AO is valid.
MREQ; Memory Request
A low-level output on MREQ indicates that the memory
or I/O bus cycle has started and that address bits Ao,
A1rA 9, A19and A 18 are valid:
MSTB; Memory Strobe
P17-P10; Port 1
Lines P1rP14 are individually programmable as an
input, output, or control function. The status of P13P10 can be read but these lines are always control
functions.
P27-P20; Port 2
P27-P20 are the lines of port 2, an 8-bit bidirectional
I/O port. These lines can also be used as control
signals for the on-chip DMA controllers. See table 2-3.
POLL; Poll
The POLL input is checked by the POLL instruction. If
the level is low, execution. of the next instruction is
initiated. If the level is high, the POLL input is checked
every five clock cycles until the level becomes low..
The POLL functions are used to synchronize the CPU
program and the operation of external devices.
Note: POLL is effective when P1 ~ecified for the
input port mode; otherwise, POLL is assumed to
be at low level when the POLL instruction is
executed.
Togetherwith MREQ and R/W, MSTB controls memory
accessing operations. MSTB should be used either to
enable datahuffers or as a qata strobe. During memory
write, a low-level output on MSTB indicates that data
on the data bus is valid. A low-level output on MSTB
indicates that multiplexed address bits As-A1' A1S,
and USE are valid.
The PT input is compared witha threshold voltage that
is programmable to one of 16 voltage steps individually
for each of the eight lines.
NMI; Nonmaskable Interrupt
READY
The NMI input is an interrupt request that cannot be
masked by software. The NMI is always accepted by
the CPU; therefore, it has priority over any other
interrupt.
After READY is de-asserted low, the CPU will synchro~
nize and insert at least two wait states into a read or
write cycle to memory or I/O. This allows the processor
to accommodate devices whose access times are
longer than normal execution allows.
The NMI input is detected at the effective edge specified by external interrupt mode register INTM. Sampled
in each clock cycle, NMI is accepted when the active
level lasts for some clock cycles. When the NMI is
accepted, a number 2 vector interrupt is generated
after completion of the instruction currently being
executed.
PTO-PT7; Port with Comparator
REFRQ; Refresh Request
This output pulse can refresh nonstatic RAM. It can be
programmed to meet system specifications and is
internally synchronized so that refresh cycles do not
interfere with normal CPU operation.
The NMI input is also used to release the CPU standby
mode.
P07-POO; Port 0
Port 0 is an 8-bit bidirectional I/O port.
This input signal is asynchronous. A low on RESET for
a certain duration resets the CPU and all on-chip
peripherals regardless of clock operation. The reset
operation has priority over all other operations.
The reset signal is used for normal initialization/startup
and also for releasing the STOP or HALT mode. After
the reset signal returns high, program execution
begins from address FFFFOH.
6.
NEe
pPD70330/332 (V35)
R/W; Read/Write Strobe
X1, X2; Clock Control
When the memory bus cycle is initiated, the R/W signal
output to external hardware indicates a read (high
level) or write (low level) cycle. It can also control the
direction of bidirectional buffers.
The frequency of the internal clock generator is controlled by an external crystal or ceramic resonator
connected across pins X1 and X2. The crystal frequency is the same as the clock generator frequency
fx. Sy programming the PRC register, the system clock
frequency fCLK is selected as fx divided by 2, 4, or B.
RxDO, RxD1; Receive Data 0,1
These pins input data from serial channels 0 and 1.
In the asynchronous mode, when receive operation is
enabled, a low level on the RxDO or RxD1 input pin is
recognized as the start bit and receive operation is
initiated.
In the I/O interface mode (channel 0 only), receive data
is input to the serial register at the rising edge of the
receive clock.
SCKO; Serial Clock
The SCKO output is the transmit clock of serial
channelO.
TCO, TC1; Terminal Count 0, 1
The TCO and TC1 outputs go low when the terminal
count of DMA service channels 0 and 1, respectively,
reach zero, indicating DMA completion.
TOUT; Timer Output
The TOUT signal is a square-wave output from the
internal timer.
TxDO, TxD1; Transmit Data 0,1
These pins output data from serial channels 0 and 1.
In the asynchronous mode, the transmit signal is in a
frame format that consists of a start bit, 7 or 8 data bits
(least significant bit first), parity bit, and stop bit. The
TxDO and TxD1 pins become mark state (high level)
when transmit operation is disabled or when the serial
register has no transmit data.
In the I/O interface mode (channel 0 only), the frame
has B data bits and the most significant bit is transmitted first.
As an alternative to the crystal or ceramic resonator,
the positive and negative phases of an external clock
(with frequency fx) can be connected to pins X1
and X2.
Voo
+S-volt power source (two pins).
VTH
Comparator port PTO-PT7 uses threshold voltage VTH
to determine the analog reference points. The actual
thresholq to each comparator line is programmable to
VTH x n/16 where n = 1 to 16.
GND
Ground reference (two pins).
IC
Internal connection; must be tied to
through a 10-kO to 20-kO resistor.
VDD
externally
UBE, Upper Byte Enable
USE is a high-order memory bank selection signal
output. USE and Ao are used to decide which bytes of
the data bus will be used. USE is used along with Ao to
select the even/odd banks as follows.
Operand
UBE
Even address word
0
Odd address word
0
Even address byte
1
Odd address byte
0
AU
0
Number of bus cycles
1
2
7
NEe
pPD70330/332 (V35)
Block Diagram
AO
P20/DMAROO
P2 t /DMAAKO
Ae l At-Ai6 1As
A17 / Ata
P23/DMARQt
P24 I DMAAKt
Ata/UBE
RESET
HLDAK/P22
HLDRQ/P27
READY IPt7
MREQ
MSTB
~/TCO
At9
P%~:g.; =;:::===~
RxDO
P16 ISCKO . . . CTSO ...TxDt _....1,-----, 1''rY' I 1-"-_ _--'\.1
R/W
RxDt - CTSt --a==,,",",,~==;;!J
PtO I NMI
Ptt/lNTPO
Pt2/1NTPt
Pt3/1NTP2
IINTAK
I05TB
POLL liNT I P14
EA
Pt~
I POLL
X1
X2
TOUTlPts
REFRQ
CLKOUT/P07
PO
PI
P2
PTO-PT7
VTH
83-0049658
Functional Description
Architectural Enhancements
The following features enable the JlPD70330/332 to
perform high-speed execution of instructions:
• Dual data bus
• 16-/32-bit temporary registers/shifters (TA, TB,
TA +TB)
• 16-bit loop counter (LC)
• Program counter (PC) and prefetch pointer (PFP)
• Internal ROM pass bus (J1PD70332 only)
Dual Data Bus. The JlPD70330/332 has two internal
16-bit data buses: the main data bus and a subdata bus_
This reduces the processing time required for addition/
subtraction and logical comparison instructions by
one-third over single-bus systems. The dual data bus
method allows two operands to be fetched simultaneously from the general-purpose registers and
transferred to the ALU.
16-/32-Bit Temporary Registers/Shifters. The 16-bit
temporary registers/shifters (TA, TB) allow high-speed
execution of multiplication/division and shift/rotation
instructions. By using the temporary registers/shifters,
8
the JlPD70330/332 can execute multiplication/division
instructions about four times faster than with the
microprogramming method.
Loop Counter [LC]. The dedicated hardware loop counter
counts the number of loops for string operations and
the number of shifts performed for multiple bit shift/
rotation instructions. The loop counter works with
internal dedicated shifters to speed the processing of
mu Iti pi ication/d ivision instructions.
Program Counter and Prefetch Pointer [PC and PFP].
The hardware PC addresses the memory location of
the instruction to be executed next. The hardware PFP
addresses the program memory location to be accessed
next. Several clocks are saved for branch, call, return,
and break instructions compared with processors
having only one instruction pointer.
Internal ROM Pass Bus. The JlPD70332 features a
dedicated data bus between the internal ROM and the
instruction pre-fetch queue. This allows internal ROM
opcode fetches to be performed in a single clock cycle
(200 ns at 5 MHz); it also makes it possible for opcode
fetches to be performed while the external data bus is
busy. This feature gives the V35 a 10-20% performance
increase when executing from the internal ROM.
NEe
Register Set
The J.lPD70330/70332 CPUs have general purpose
register sets compatible with the J.lPD701 08/70116 and
the J.lPD70320/70322 microprocessors. Like the
J.lPD70320/70322, they also have a set of special function
registers for controlling the onboard peripherals. All
registers reside in the CPU's memory space. They are
grouped in a 4K byte block called the internal data area
(IDA). The 256 byte internal RAM is also in the IDA. The
addresses of the register are given as offsets into the
IDA. The start address of the IDA is set by the Internal
Data Area Base register (lOB), and may be programmed
to any 4K boundary in the memory address space.
Register Banks. Because the general purpose register
set is in internal RAM, it is possible to have multiple
banks of registers. TheJ.lPD70330/70332 CPU supports
up to 8 register banks. A bit field in the PSW selects
which bank is currently being used. Each bank contains the entire CPU register set plus additional
information needed for context switching. Register
banks may be switched using special instructions
(TSKSW, BRKCS, MOVSPA, MOVSPB), or may switch
in response to an interrupt. This provides fast context
switching and fast interrupt handling. During and after
RESET, register bank 7 is selected.
Figure 1 shows the configuration of a register bank and
how the banks are mapped to internal RAM. The Vector
PC treld contains the value that will be loaded into the
PC when a register bank switch occurs. The PC Save
and PSW Save fields contain the values of the PC and
the PSW just before the banks are switched. The PSW
is left unmodified after a bank switch; the PSW Save
field is used to restore the PSW to its previous state is
required.
General-Purpose Registers [AW, BW, CW, OW]. These
four 16-bit general-purpose registers can also serve as
independent 8-bit registers (AH, AL, BH, BL, CH, CL,
DH, DL). The instructions below use general-purpose
registers for default:
AW
Word multiplication/division, word 110, data
conversion
AL
Byte multiplication/division, byte 110, BCD
rotation, data conversion, translation
AH
BW
Byte multiplication/division
Translation
CW
Loop control branch, repeat prefix
CL
Shift instructions, rotation instructions, BCD
operations
OW
Word multiplication/division, indirect addressing I/O
pPD70330/332 (V35)
Figure 1.
Register Bank Configuration
Eight ~2-Byte
Register Banks
15
xxEFFH
0
Register Bank
7
xxEEOH
xxECOH
6
xxEAOH
5
xxE80H
4
xxE60H
3
xxE40H
2
xxE20H
1
xxEOOH
0
Banks 0-7
L- Start address; xx =value
specified by lOB register
32-Byte
Register Bank
0
15
AW
+lEH
AH
+lCH
GH
+lAH
DH
+18H
BH
I
AL
I
GL.
I
DL.
CW
ow
BW
+16H
+14H
+12H
+10H
+OEH
+OCH
+OAH
+08H
+06H
+04H
+02H
+OOH
I
BL
SP
BP
IX
IV
OS1
PS
SS
OSO
PC .torage
PSW Storage
Vector PC
Re.erved
L..= Offset
from register bank
start address
83M-004643
9
NEe
pPD70330/332 (V35)
Pointers [SP, BPl and Index Registers [IX, IV]. These
registers are used as 16-bit base pointers or index
registers in based addressing, indexed addressing,
and based indexed addressing. The registers are used
as default registers under the following conditions:
15
I
PSW
1
RB2
I,
RB1
RBO
F1
AC
I
8
V
I BRK I
DIR
IE
p
I BRKI I
SP
Stack operations
IX
Block transfer (source), BCD string operations
I
IY
Block transfer (destination), BCD string
operations
Status Flags
Control Flags
V
Overflow bit
DIR
S
Sign
Direction of string
processing
Z
Zero
IE
Interrupt enable
7
Segment Registers. The segment registers divide the
1M-byte address space into 64K-byte blocks. Each
segment register functions as a base address to a
block; the effective address is an offset from that base.
Physical addresses are generated by shifting the associated segment register left four binary digits and then
adding the effective address. The segment registers
are:
Segment Register
Default Offset
PS (Program segment)
SS (Stack segment)
DSO (Data segment-O)
DS1 (Data segment-1)
PC
SP, Effective address
IX, Effective address
IY, Effective address
During RESET, PS is set to FFFFH; DSO, DS1 and SS
are set to OOOOH. .
Program Counter [PC]. The PC is a 16-bit binary
counter that contains the offset address from the
program segment of the next instruction to be executed.
It is incremented every time an instruction is received
from the queue .. It is loaded with a new location
whenever a branch, call, return, break, or interrupt is
executed. During RESET, PC is serto OOOOH.
10
Program Status Word [PSW]. The PSW contains the'
following status and control flags.
's
I
o
z
AC Auxiliary carry
P
Parity
CY
Carry
FO
I
Cy
I
BRK Break (after every
instruction)
RBn
Current register
bank flags
BRKI I/O trap enable (see
software interrupts)
FO, F1 General-purpose
user flags
The eight low-order bits of the PSW can be stored in the
AH register and restored by a MOV instruction execution. The only way to alter the RBn bits via software is to
execute an RETRBI orRETI instruction. During RESET,
PSW is set to F002H. The FO and F1 flags may be accessed as bits in the FLAG special functioning register.
Memory Map
The pPD70330/332 has a 20-bit address bus that can
directly access 1M bytes of memory. Figure 2 shows that
the 16K bytes of internal ROM (pPD70332 only)
are located at the top of the address space from FCOOOH
to FFFFFH ..
NEe
Figure 2.
pPD70330/332 (V35)
Memory Map
Eight 128K-Byte
Memory Banks
[1 M-ByteMemoryj
15
0
Lr
FFFH lOB Registeri
FFFFFH
Memory Bank
7
EOOOOH
DFFFFH
16K"Byte
Internal ROM [JlPD70322j
15
87
0
FFFFBH
12 Byles
FFFEFH
Use ProhibitEid
FFEFFH
COOOOH
BFFFFH
6
AOOOOH
9FFFFH
5
80000H
7FFFFH
4
16,128 Bytes
FCOOOH
15
60000H
5FFFFH
3
40000H
3FFFFH
2
20000H
lFFFFH
1
OOOOOH
0
0
Special Function
Registers, 256 Bytes
{ "FFFH
xxFOOH
xxEFFH
_
512-Byte
Internal Data Area
256-Byte
Internal RAM
xxEOOH
,
1 K-Byte
Vector Area
{ 003FFH
~
OOOOOH
15
0
General-Purpose Vectors
Special-Purpose Vectors
32-Byte
Register Bank
15
+lFH
0
AW
CW
OW
BW
SP
BP
IX
IV
r--'
DSl
PS
SS
DSO
PC Storage
8-Byte
Macro Service Channel
15
0
8 7
PSW Storage
Vector PC
Eight 32-Byte
Register Banks
15
xxEFFH
+OOH
~{
Reserved
0
xxEEOH
Register Bank
7
xxECOH
6
xxEAOH
5
xxE80H
4
xxE60H
3
xxE40H
2
xxE20H
1
xxEOOH
0
Eight 8-Byte
Macro Service Channels
15
0
xxE3FH
Macro Service Channel
7
xxE38H
-
~
xxE30H
6
xxE28H
5
xxE20H
4
xxE18H
3
xxEl0H
2
+7H
MSS
MSP
Reserved
+OH
SFRP
1
xxEOOH
0
SCHR
MSC
Two 8-Byte
DMA Service Channels
0
15
8 7
xxEOFH
xxE08H
I
I
-
]-I
Chan 1
TCl
SARH1
xxEOOH
OARHl
SARl
xxE08H
xxE07H
ChanO
I
DARl
TCO
SARHO
I
DARHO
DARO
SARO
83-004644C
11
NEe
pPD70330/332 (V35)
Figure 2 shows the internal data area (IDA) is a 256byte internal RAM area followed consecutively by a
256-byte special function register (SFR) area. All the
data and control registers for on-chip peripherals and
I/O are mapped into the SFR area and accessed as
RAM. For a description of these functions, see table 6.
The IDA is dynamically relocatable in 4K-byte increments by changing the value in the internal data base
(lOB) register. Whatever value is in this register will be
assigned as the uppermost eight bits of the IDA
address. The lOB register can be accessed from two
different memory locations, FFFFFH and XXFFFH,
where XX is the value in the lOB register.
On reset, the internal data base register is set to FFH
which maps the IDA into the internal ROM space.
However, since the pPD70332 has a separate bus to
internal ROM, this does not present a problem. When
these address spaces overlap, program code cannot be
executed from the IDA and internal ROM locations
cannot be accessed as data.
Figure 2 shows that the internal data area is divided into
2 parts: the 256 byte internal RAM and the special
function register area.
The internal RAM area serves various purposes. When
the RAMEN bit in the Processor Control Register is set,
this area may be accessed as RAM and code may be
executed from it. Note that the processor may ru n
slower when the RAMEN bit is set. See the Instruction
Clock Count table. I n addition, whether the RAMEN bit
is on or off, each of the B macroservice channels has an
B byte control block that is assigned to a fixed location
in the low 64 bytes of the internal RAM. Similarly, the
two B byte DMA control blocks are assigned to the low
16 bytes of the RAM. The B CPU register banks use 32
bytes each. Since the RAM can't be used for more than
one purpose, there are restrictions on how V35 features
can be combined. For example, if register bank 0 is
used, then macroservice channels 0-3 and both DMA
channels cannot be used. If DMA channel 1 is used,
then macroservice channel 1 cannot be used.
The special function register area contains the registers
used to control the onboard peripheral functions.
Table 6 shows the SFRs. The address shown in the
table is an offset from the lOB register. MostSFRs can
be both read and written, but some are read-only;
others are write-only. Some SFRs may be accessed
one bit at a time; others only B bits at a time, and some
SFRs are 16 bits wide.
12
Instructions
The pPD70330/332 instruction set is fully compatible
with the V20 native mode instruction set. The V20
instruction set is a superset of the pPDBOB6/BOBB
instruction set with different execution times and
mnemonics.
The pPD70330/332 does not support the V20 BOBO
emulation mode. All of the instructions pertaining to
this have been deleted from the pPD70330/332 instruction set.
Enhanced Instructions
In addition to the pPDBOB6/BB instructions, the
pPD70330/332 has the following enhanced instructions.
Instruction
Function
PUSH imm
Pushes immediate data onto stack
PUSH R
Pushes eight general registers onto
stack
POPR
Pops eight general registers from stack
MUL imm
Executes 16-bit multiply of register or
memory contents by immediate data
SHL immB
Shifts/rotates register or memory by
SHR immB
immediate value
SHRA immB
ROL immB
ROR immB
ROLC immB
RORC immB
CHKIND
Checks array index against designated
boundaries
INM
Moves a string from an 110 port to
memory
OUTM
Moves a string from memory to an I/O
port
PREPARE
Allocates an area for a stack frame and
copies previous frame pointers
DISPOSE
Frees the current stack frame on a
procedure exit
NEe
pPD70330/332 (V35)
Unique Instructions
The pPD70330/332 has the following unique
instructions.
Instruction Fu nction
INS
Inserts bit field
EXT
Extracts bit field
ADD4S
Performs packed BCD string addition
SUB4S
Performs packed BCD string subtraction
CMP4S
Performs packed BCD string
comparison
ROl4
Rotates BCD digit left
ROR4
Rotates BCD digit right
TEST1
Tests bit
SET1
Sets bit
ClR1
Clears bit
Bit field insertion copies the bit field of specified length
from the AW register to the bit field addressed by
DS1:IY:reg8 (8-bit general-purpose register). The bit
field length can be located in any byte register or
supplied as immediate data. Following execution, both
the IY and reg8 are updated to point to the start of the
next bit field.
Bit field extraction copies the bit field of specified
length from the bit field addressed by DSO:IX:reg8 to
the AW register. If the length of the bit field is less than
16 bits, the bit field is right justified with a zero fill. The
bit field length can be located in any byte register or
supplied as immediate data. Following execution, both
IX and reg8 are updated to point to the start of the next
bit field.
NOT1
Complements bit
BTClR
Tests bit; if true, clear and branch
REPC
Repeat while carry set
REPNC
Repeat while carry cleared
Figures 3 and 4 show bit field insertion and bit field
extraction.
Packed BCD Instructions
Variable Length Bit Field Operation Instructions
Packed BCD instructions process packed BCD data
either as strings (ADD4S, SUB4S, CMP4S) or byte
format operands (ROR4, ROl4). Packed BCD strings
may be 1 to 254 digits in length. The two BCD rotation
instructions perform rotation of a single BCD digit in
the lower half of the Al register through the register or
the memory operand.
Bit fields are a variable length data structure that can
range in length from 1 to 16 bits. The pPD70330/332
supports two separate operations on bit fields: insertion
(INS) and extraction (EXT). There are no restrictions
on the position of the bit field in memory. Separate
segment, byte offset, and bit offset registers are used
for insertion and extraction. Following the execution of
these instructions, both the byte offset and bit offset
Figure 3.
are left pointing to the start of the next bit field, ready
for the next operation. Bit field operation instructions
are powerful and flexible and are therefore highly
effective for graphics, high-level languages, and packingl
unpacking applications.
Bit Field Insertion
Bit length
15
o
AW
Bit offset
Memory
Byte boundary
Segment base (OS1)
83-0001068
13
NEe
pPD70330/332 (V35)
Figure 4.
Sit Field Extraction
Bit length
Bit offset
Byte boundary
Segment base (050)
83-0001076
Bit Manipulation Instructions
Bank Switch Instructions
The jlPD70330/332 has five unique bit manipulation
instructions. The ability to test, set, clear, or complement a single bit in a register or memory operand
increases code readability as well as performance over
the logical operations traditionally used to manipulate
bit data. This feature further enhances control over
on-chip peripherals.
The V35 has four new instructions that allow the
effective use of the reg ister ban ks for software i nterru pts
and multitasking. These instructions are shown in
table 2. Also, see figures 8 and 10.
Instruction
Function
Additional Instructions
BRKCS reg 16
Performs a high-speed software interrupt with
context switch to the register bank indicated
by the lower 3-bits of reg 16. This operation is
identical to the interrupt operation shown in
figure9.
TSKSW reg 16
Performs a high-speed task switch to the
register bank indicated by the lower 3-bits of
reg 16. The PC and PSW are saved in the old
banks. PC and PSW save registers and the new
PC and PSW values are retrieved from the new
register bank's save areas. See figure 10.
MOVSPA
Transfers both the SS and SP of the old
register bank to the new register bank after
the bank has been switched by an interrupt or
BRKCS instruction.
MOVSPB
Transfers the SS and the SP of the current
register bank before the switch to the SS and
SP of the new register bank indicated by the
lower 3-bits of reg 16.
Besides the V20 instruction set, the JlPD7033010332
has the eight additional instructions described in
table 1.
Table 1.
Additionallnstructions
Instruction
Function
BTCLR var,imm8,
short label
Bit test and if true, clear and branch;
otherwise, no operation
STOP (no operand)
Power down instruction, stops oscillator
RETRBI (no operand)
Return from register bank context switch
interrupt
FINT (no operand)
Finished interrupt. After completion of a
hardware interrupt request, this instruction
must be used to reset the current priority
bit in the in-service priority register (ISPR).*
Table 2.
Sank Switch Instructions
*00 not use with NMI or INTR interrupt service routines.
Interrupt Structure
Repeat Prefixes
Two new repeat prefixes (REPC; REPNC) allow conditional block transfer instructions to use the state of
the CY flag as the termination condition. This allows
inequalities to be used when working on ordered data,
thus increas'ing performance when searching and
sorting algorithms.
14
The JlPD70330/332 can service interrupts generated
both by hardware and by software. Software interrupts
are serviced through vectored interrupt processing.
See table 3 forthe various types of software interrupts.
NEe
Table 3.
Software Interrupts
Interrupt
Divide error
pPD70330/332 (V35)
Figure 5.
Interrupt Vector 0
. Description
Vector 0
The CPU will trap if a divide error occurs as the
result of a DIV or DIVU instruction.
OOOH
Single step
The interrupt is generated after every instruction
if the BRK bit in the PSW is set.
002H
Overflow
By using the BRKV instruction, an interrupt can be
generated as the result of an overflow.
Interrupt
instructions
The BRK 3 and BRK imm8 instructions can
generate interrupts.
Array bounds
The CHKIND instruction will generate an interrupt
if specified array bounds have been exceeded.
Table 4.
Escape trap
The CPU will trap on an FP01,2 instruction to
allow software to emulate the floating point
processor.
00
1/0 trap
If the 1/0 trap bit in the PSW is cleared, a trap will
be generated on every IN or OUT instruction.
Software can then provide an updated peripheral
address. This feature allows software
interchangeability between different systems.
:I
001H
003H
PS +- (OO3H, 002H)
pc <- (OO1H, OOOH)
83-000112A
Address
Interrupt Vectors
Vector No.
0
Assigned Use
Divide error
Break flag
04
08
2
NMI
OC
3
BRK3 instruction
10
4
BRKV instruction
14
5
CHKIND instruction
18
6
General purpose
1C
7
FPO instructions
20-2C
8-11
General purpose
30
12
INTSERO (Interrupt serial error, channel 0)
INTSRO (Interrupt serial receive, channel 0)
When executing software written for another system, it
is better to implement liD with on-chip peripherals to
reduce external hardware requirements. However,
since J.lPD70330/332 internal peripherals are memory
mapped, software conversion could be difficult. The
I/O trap feature allows easy conversion from external
peripherals to on-chip peripherals.
34
13
38
14
INTSTO (Interrupt serial transmit, channel 0)
Interrupt Vectors
3C
15
General purpose
The starting address of the interrupt processing
routines may be obtained from table 4. The table
begins at physical address OOH, which is outside the
internal ROM space. Therefore, external memory is
required to .service these routines. By servicing interrupts via the macro service function or context
switching, this requirement can be eliminated.
40
16
INTSER1 (Interrupt serial error, channel 1)
44
17
INTSR1 (Interrupt serial receive, channel 1)
48
18
INTST1 (Interrupt serial transmit, channel 1)
4C
19
I/O trap
50
20
INTDO (Interrupt from DMA, channel 0)
54
21
INTD1 (Interrupt from DMA, channel 1)
Each interrupt vector is four bytes wide. To service
a vectored interrupt, the lower addressed word is
transferred to the PC and the upper word to the PS.
See figure 5.
58
22
General purpose
5C
23
General purpose
60
24
INTPO (Interrupt from peripheral 0)
64
25
INTP1 (Interrupt from peripheral 1)
68
26
INTP2 (Interrupt from peripheral 2)
6C
27
General purpose
70
28
INTTUO (Interrupt from timer unit 0)
74
29
INTTU1 (Interrupt from timer unit 1)
78
30
INTTU2 (Interrupt from timer unit 2)
7C
31
INTTB (Interrupt from time base counter)
080-3FF
32-255
General purpose
m
15
NEe
pPD70330/332 (V35)
Execution of a vectored interrupt occurs as follows:
(SP-1, SP-2) - PSW
(SP-3, SP-4) - PS
(SP-5, SP-6) - PC
SP +- SP-6
IE-O,BRK-O
PS +- vector high bytes
PC +- vector low bytes
If interrupts from different groups occur simultaneously
and the groups have the same assigned priority level,
the priority followed will be as shown in the Default
Priority column of table 5.
The ISPR is an 8-bit SFR; bits PRo-PR7 correspond to
the eight possible interrupt request priorities. The
ISPR keeps track of the priority of the interrupt currently being serviced by setting the appropriate bit.
The address of the ISPR is XXFFCH. The ISPR format
is shown below.
Hardware Interrupt Configuration
The V35 features a high-performance on-chip controller capable of controlling multiple processing for
interrupts from up to 17 different sources (5 external,
12 internal). The interrupt configuration includes
system interrupts that are functionally compatible with
those of the V20IV30 and unique high-performance
microcontroller interrupts.
I
PR 7
I
PRs
I
PRs
I
PR4
I
PR3
I
PR2
I
PR1
I
PRo
I
Interrupt Sources
NMI and INT are system-type external vectored
interrupts. NMI is not maskable via software. INTR is
maskable (IE bit in PSW) and requires that an external
device provide the interrupt vector number. It allows
expansion by the addition of an external interrupt
controller (pPD71059).
The 17 interrupt sources (table 5) are divided into
groups for management by the interrupt controller.
Using software, each of the groups can be assigned a
priority from 0 (highest) to 7 (lowest). The priority of
individual interrupts within a group is fixed in hardware.
NMI, INTPO, and INTP1 are edge-sensitive interrupt
inputs. By selecting the appropriate bits in the interrupt
mode register, these inputs can be programmed to be
either rising or falling edge triggered. ESo-ES2 correspond to INTPO-INTP2, respectively. See figure 6.
Figure 6.
Interrupt Mode Register (INTM)
7
INTM
o
6
I I I I I I I I I
0
ES2
0
ES1
0
ESo
0
ES
NMI
Trigger Mode
0
Falling Edge
1
Rising Edge
0
Falling Edge
1
Rising Edge
0
Falling Edge
1
Rising Edge
0
Falling Edge
1
Rising Edge
49-0013828
16
NEe
Table 5.
pPD70330/332 (V35)
Interrupt Sources
Interrupt Source
NMI
Nonmaskable interrupt
INTTUO
Interrupt from timer
unit 0
INTTU1
Interrupt from timer
unit 1
INTTU2
Interrupt from timer
unit 2
INTDO
Interrupt from DMA
channel 0
INTD1
Interrupt from DMA
channel 1
INTPO
Interrupt from
peripheral 0
INTP1
Interrupt from
peripheral 1
INTP2
Interrupt from
peripheral 2
INTSERO
Interrupt from serial
error on channel 0
INTSRO
Interrupt from serial
receiver of channel 0
INTSTO
Interrupt from serial
transmitter of channel 0
INTSER1
Interrupt from serial
error on channel 1
INTSR1
Interrupt from serial
receiver of channel 1
INTSn
Interrupt from serial
transmitter of channel 1
INTTB
Interrupt from time
base counter
INT
Interrupt
External/
Internal
External
Priority Order
Between
Groups
Multiple
Processing
Control
Not
accepted
Accepted
Vector
2
Macro
Service
No
Bank
Switching
No
Setting
Possible
No
Internal
28
Yes
Yes
Yes
Internal
29
Yes
Yes
Yes
2
Internal
30
Yes
Yes
Yes
3
Internal
20
No
Yes
Yes
2
Internal
21
No
Yes
Yes
2
External
24
Yes
Yes
Yes
3
External
25
Yes
Yes
Yes
3
2
External
26
Yes
Yes
Yes
3
3
Internal
12
No
Yes
Yes
4
Internal
13
Yes
Yes
Yes
4
2
Internal
14
Yes
Yes
Yes
4
3
Internal
16
No
Yes
Yes
5
Internal
17
Yes
Yes
Yes
5
2
Internal
18
Yes
Yes
Yes
5
3
Internal
31
No
No
No
(Preset to 7)
6
Accepted
External
Ext.
input
No
No
No
7
Not
accepted
Within
Groups
0
Accepted
2
Accepted
1m
Accepted
Accepted
17
NEe
pPD70330/332 (V35)
Interrupt Processing Modes
Register Bank Switching
Interrupts, with the exception of NMI, INT, and INTTB,
have high-performance capability and can be processed in any of three modes: standard vectored interrupt, register bank context switching, or macro service
function; The processing mode for a given interrupt
can be chosen by enabling the appropriate bits in the
corresponding interrupt request control register. As
shown in table 6, each individual interrupt, with the
exception of INTR and NMI, has its own associated IRC
register. The format for all IRC registers is shown in
figure 7. There is an IRC for every interrupt source
except NHI and INT.
Register bank context switching allows interrupts to be
processed rapidly by switching register banks. After an
interrupt, the new register bank selected is that which
has the same register bank number (0-7) as the priority
of the interrupt to be serviced. The PC and PSWare
automatically stored in the save areas of the new
register bank and the address of the interrupt routine is
loaded from the vector PC storage location in the new
register bank. As in the vectored mode, the IEand BRK
bits in the PSW are cleared to zero. After interrupt
processing, execution of the RETRBI (return from
register bank interrupt) returns control to the former
register bank and restores the former PC and PSW.
Figures 8 and 9 show register bank context switching
and register bank return.
All interrupt processing routines other than those for
NMI and INT must end with the execution of an FINT
instruction. Otherwise, subsequently, only interrupts
of a higher priority will be accepted. FINT allows the
internal interrupt controller to begin looking for new
interrupts.
In the vectored interrupt mode, the CPU traps to the
vector location in the interrupt vector table.
Figure 7.
Symbol
IRC Register
DICO, DIC1
EXICO-EXIC2
SEICO, SEIC1
SRICO, SRIC1
STICO, STIC1
TMICO-TMIC2
DMA
External
Serial error
Serial receive
Serial transmit
Timer
Interrupt Request Control Registers (lRC)
7
IRC
Specific IRC registers include the following.
f
FLAG
4
6
2
1 J I I I I I
MASK
MSI
INT
ENCS
0
PR2
L
PR1
o
PRo
J
PR
2 1 0
Priority
000
Highest
1 1 1
Lowest
ENCS
Context Switch
···
0
Vectored Interrupt Mode
1
Bank Switching
MS/INT
0
Macro Service or Interrupt
Interrupt
1
Macro Service
xxMKn
Interrupt Mask
0
1
xxFn
Mask Open: Interrupts Enabled
Mask Closed: Interrupts Disabled
Interrupt Request Flag
0
No Request
1
Interrupt Requested
49-0013838
18
NEe
pPD70330/332 (V35)
Macro Service Function
Figure 8.· Register Bank Context Switching
RBi
The macro service function (MSF) is a special microprogram that acts as an internal DMA controller between on-chip peripherals (special function registers,
SFR) and memory. The MSF greatly reduces the
software overhead and CPU time that other processors
would require for register save processing, register
returns, and other handling associated with interrupt
processing.
RBj
AW
AW
CW
CW
OW
OW
BW
BW
SP
SP
Q
BP
IX
BP
IX
IV
IV
OS1
OS1
PS
PS
SS
SS
OSO
Save PC
,.
Save PC
f---+
SavePSW
-
SavePSW
If the MSF is selected for a particular interrupt, each
time the request is received, a byte or word of data will
be transferred between the SFR and memory without
interrupting the CPU. Each time a request occurs, the
macro service counter is decremented. When the
counter reaches zero, an interrupt to the CPU is
generated. The MSF also has a character search
option. When selected, every byte transferred will be
compared to an a-bit search character and an interrupt
will be generated if a match occurs or if the macro
service counter counts out.
OSO
Vector PC
Vector PC
Reserved
Reserved
f--
.----
y
L-f
Like the NMI, INT and INTTB, the two DMA controller
interrupts (INTDO, INTD1) do not have MSF capability.
I
PC
PSW
49-001344A
Figure 10.
Task Switching
Figure 9. .Register Bank Return
CURRENT
NEW
AW
AW
cw
RBi
RBj
CW
AW
AW
OW
OW
CW
CW
BW
BW
SP
OW
OW
BW
BW
SP
SP
IX
BP
BP
IV
IV
OS1
OS1
PS
PS
¢J
IX
IV
IX
IV
OS1
OS1
PS
PS
SS
SS
OSO
OSO
Save PC
SavePSW
r---
.---
~avePC
+--
SavePSW
Vector PC
Vector PC
Reserved
Reserved
lr
L-J
SP
(>
BP
r-
IX
SS
SS
oso
oso
,-----
PC Save
,-j-.; PSWSave
~
~
PC
BP
.------'--
PC Save
PSWSave
VPC
VPC
Reserve
Reserve
PC
PSW
~
~
VPC: Vector PC
RB: Register b ank field
RBL
Reg 16
PSW
83-MB005273A
49-001346A
19
NEe
pPD70330/332 (V35)
There are eight 8-byte macro service channels mapped
into internal RAM from XXEOOH to XXE3FH. Figure 11
shows the components of each channel.
Setting the macro service mode for a given interrupt
requires programming the corresponding macro service control register. Each individual interrupt, excluding INTR, NMI and TBC, has its own associated MSC
register. See table 6. Format for all MSC registers is
shown in figure 12.
Figure 11.
Macro Service Channels
8
15
+7H
Clock
o
7
SCLK/6
SCLK/128
MSS
MSP
r
+OH
Reserved
SCHR
SFRP
MSC
Interval Timer Mode. In this mode, TMO/TMl are
decremented by the selected input clock and, after
counting out, the registers are automatically reloaded
from the modulus registers and counting continues.
Each time TMl counts out, interrupts are generated
through TFl and TF2 (Timer Flags 1, 2). When TMO
counts out, an interrupt is generated through TFO.
The timer-out signal can be used as a square-wave
output whose half-cycle is equal to the count time.
There are two selectable input clocks (SCLK: system
clock = fose/2; fose = 10 MHz).
Offset from macro service channel start address.
+6H
Segment value of memory address used
for data transfer. Memory address
will be MSS x 16 + MSP.
MSP
+4H
Offset value of memory address used
for data transfer.
SCHR
+2H
B·bit data compared In character search.
SFRP
+1H
Offset value of special function register
address, which is xxFOOH + SFRP. (xx is
specified by 108 register).
MSC
+OH
Number of transfers performed in
macro service
83M·OO5285A
On-Chip Peripherals
Timer Unit
The JlP070330/332 (figure 13) has two programmable
16-bit interval timers (TMO, TM1) on-chip, each with
variable input clock frequencies. Each of the two 16-bit
timer registers has an associated 16-bit modulus
register (MOO, MOl). Timer 0 operates in the interval
timer mode or one-shot mode; timer 1 has only the
interval timer mode.
Full Count
1.2J1s
25.6J1s
78.643 ms
1.678 s
One-Shot Mode. In the one-shot mode, TMO and MOO
operate as independent one-shot timers. Starting with
a preset value, each is decremented to zero. At zero,
counting ceases and an interrupt is generated by TFO
(from TMO) or TFl (from MDO). One-shot mode allows
two selectable input clocks (fose = 10 MHz).
Clock
MSS
Timer Resolution
SCLK/12
SCLK/128
Timer Resolution
Full Count
2.4 JlS
25.6 JlS
157.283 ms
1.678 s
Setting the desired timer mode requires programming
the timer control register. See figures 14 and 15 for
format.
Time Base Counter/Processor Control Register
The 20-bit free-running time base counter controls
internal timing sequences and is available to the user
as the source of periodic interrupts at lengthy intervals.
One of four interrupt periods can be selected by programming the TBO and TBl bits in the processor
control register (PRC). The TBC interrupt is unlike the
others in that it is fixed as a level 7 vectored interrupt.
Macro service and register bank switching cannot be
used to service this interrupt. See figures 16 and 17.
The RAMEN bit in the PRC register allows the internal
RAM to be removed from the memory address space to
implement faster instruction execution.
The TBC (figure 18) uses the system clock as the input
frequency. The system clock can be changed by
programming the PCKO and PCKl bits in the processor
control register (PRC). Reset initializes the system
clock to fose/8 (fose = external oscillator frequency).
20
NEe
Figure 12.
pPD70330/332 (V35)
Macro Service Control Registers (MSC)
I
MSM2
o
4
7
xxMSn
I
MSM1
I
MSMo
I
DIR
I
0
I
CH2
L
I
CH1
I
CHo
J
2
1
0
Macro Service Channel
0
0
0
Channel 0
1
1
Channel 7
1
··
·
.
Transfer Direction
0
From Memory to SFR
1
From SFR to Memory
Transfer Mode
*
* All other combinations are reserved
0
0
1
0
0
0
0
1
0
8-bit Transfer
16-bit Transfer
8-bit Transfer with Character Search
49-001384B
Figure 13.
I
Timer Unit Block Diagram
fSCLK
Idivided bY~
12:~L..-"':""":""'-I
12~
128
r----L~~r-~
1-----oTO
- - - - - - - - - L(";,.- - - - -. - - - - - - - - - - - - -
r
V
Internal Bus
83SL--s746A
21
NEe
pPD70330/332 (V35)
Figure 14.
Timer Control Register 0
5
6
I
I
TSO
TCLKO
I
MSO
4
I
MCLK
o
2
I
ENTO
I
ALV
I
MOD1
MODO
I
I
MOD1
MODO
0
0
Timer Mode
Interval Timer Mode
0
1
One-shot Timer Mode
1
X
Reserved
Active Level ofTOUT
0
TOUT initial level = 0
1
TOUT initial level = 1
0
Disable Timer Out
1
Enable Timer Out
0
SCLK/12
1
SCLK/128
0
Stop Modulus Register Count
1
Start Modulus Register Count
Enable Timer-Out Signal
One-shot Mode Modulus Register Clock
Modulus Start (One-shot Mode)
TM Register Clock Select
MOD1
MODO
TCLK
0
0
0
SCLK/6 Interval Timer Mode
0
0
1
SCLK/128
0
1
0
SCLK/12 One-shot Mode
0
1
1
SCLK/128
Timer Start Bit
0
Stop Timer"
1
Start Timer"
"Starts and stops TMO in one-shot mode
49-0013878
Figure 15.
Timer Control Register 1
7
I
TS1
6
I
TCLK1
I
4
5
I
0
I
0
3
I
0
o
2
I
0
I
0
I
0
TM1 Clock Select
o
1
I SCLK/6
I SCLK/128
Timer Start Bit
o
1
I Stop TM1 counting
I Start TM1 counting
49-0013898
22
NEe
Figure 16.
Time Base Interrupt Request Control Reg/ster
I
I
TBMK
3
4
6
7
TBF
pPD70330/332 (V35)
I
0
I
0
I
0
o
2
I
1
J
1
l
1
I
Time Base Interrupt Mask Bit
oI
Unmasked
1
I
Masked
o
I No Interrupt Generated
Time Base Interrupt Flag
1
I
Interrupt Generated
49-0013936
Figure 17.
Processor Control Register (PRC)
I
0
5
6
7
PRC
I
RAMEN
I
0
4
I
0
o
3
I
TB1
TBO
I
I
I
PCK1
I
I
PCKO
I
I
System Clock,Select
PCK1
PCKO
0
0
fosc/ 2
0
1
fosc/ 4
1
0
fosc/8
1
1
Reserved
Time Base Interrupt Period
TB1
TBO
0
0
0
1
1
0
1
1
21O /fCLK
213/fCLK
216/fCLK
22O/fCLK
Internal RAM Enable
0
Disabled
1
Enabled
49-0013956
Figure 18.
Time Base Counter (TBC) Block Diagram
SCLK
+210
+ 213
+216
+220
49-001348A
23
NEe
pPD70330/332 (V35)
Refresh Controller
The pPD70330/332 has an on-chip refresh controller
for dynamic and pseudostatic RAM mass storage
memories. The refresh controller generates refresh
addresses and refresh pulses. It inserts refresh cycles
between the normal CPU bus cycles according to
refresh specifications.
HOLD modes. Refresh. cycles- are automatically timed
to REFRQ following read/writecycles to minimize the
effect on system though put.
The following shows the REFRQ pin level in relation to
bits 4 (RFEN) and 7 (RFLV) of the refresh mode
register.
RFEN
The refresh controller outputs a9-:bitrefresh address
on address bits Ao-As during the refresh bus cycle.
Address bits Ag-A19 are all 1'So The 9-bit refresh
address is automatically incremented at every refresh
timing for 512 row addresses. The 8-bit refresh mode
(RFM) register (figure 19) specifies the refresh operation and allows refresh during both CPU HALT and
Figure 19.
I
REFRQ Level
0
1
0
1
0
1
0
Refresh pulse output
Refresh Mode Register (RFM)
7
RFM
RFLV
--
0
0
1
1
RFLV
I
6
HLDRF
4
I
HLTRF
I
RFEN
o
2
I
RFW1
RFWO
I
I
I
RFT1
RFTO
Refresh Cycle Speed
Refresh Period
RFT1
RFTO
0
0
16/SCLK
0
1
32/SCLK
1
0
64/SCLK
1
1
128/SCLK
RFW1
RFWO
0
0
0
0
1
1
1
0
2
1
1
Refresh Cycle Wait States
Number of Wait States
2
Refresh Enable
= RFLV
0
Refresh Pin
1
Refresh Enabled
0
Refresh Duringtialt Disabled
1
Refresh During CPU HALT
0
Hold Refresh Disabled
1
Refresh During Hold
Halt Refresh Enable
Hold Refresh Enable
Refresh level output
to RFSH pin when RFEN
=0
49-001392B
24
NEe
pPD70330/332 (V35)
Serial Interface
Baud Rate
ThepPD70330/332 has two full-duplex UARTs, channel
and channel 1. Each serial port channel has a
transmit line (TxDn), a receive line (RxDn), and a clear
to send (CTSn) input line for handshaking. Communication is synchronized by a start bit, and you can
program the ports for even, odd, or no parity, character
lengths of 7 or 8 bits, and 1 or 2 stop bits.
o
ThepPD70330/332 has dedicated baud rate generators
for each serial channel. This eliminates the need to
obligate the on-chip timers. The baud rate generator
allows a wide range of data transfer rates (up to 1.25
Mb/s). This includes all of the standard baud rates
without being restricted by the value of the particular
external crystal.
Each baud rate generator has an 8-bit baud rate
generator (BRGn) data register, which functions as a
prescaler to a programmable input clock selected by
the serial communication control (SCCn) register.
Together these must be set to generate a frequency
equivalent to the desired baud rate.
The baud rate generator can be set to obtain the
desired transmission rate according to the following
formula:
B
X
G = SCLK X 10
2n + 1
6
where B = baud rate
G = baud rate generator register (BRGn)
value
n = input clock specifications (n between
o and 8). This is the value that is loaded
into the SCCn register. See figure 23.
SCLK = system clock frequency (MHz)
BRGn Value
Error (%)
110
7
178
0.25
150
7
130
0.16
300
6
130
0.16
600
5
130
0.16
0.16
1200
4
130
2400
3
130
0.16
4800
2
130
0.16
9600
1
130
0.16
19,200
0
130
0.16
38,400
0
65
0.16
1.25M
0
2
0
In addition to the asynchronous mode, channel 0 has a
synchronous I/O interface mode. I n this mode, each bit
of data tranferred is synchronized to a serial clock
(SCKO). This is the same as the NEC pCOM75 and
pCOM87 series, and allows easy interfacing to these
devices. Figure 20 is the serial interface block diagram;
figures 21,22, and 23 show the three serial communication registers.
DMA Controller
The pPD70330/332 has a two-channel, on-chip DMA
controller. This allows rapid data transfer between
memory and auxiliary storage devices. The DMA controller supports four modes of operation, two for
memory-to-memory transfers and two for transfers
between I/O and memory. See figu res 24, 25, and 26 for
a graphic representation of the DMA registers.
Based on the above expression, the following table
shows the baud rate generator values used to obtain
standard transmission rates when SCLK = 5 MHz.
25
NEe
pPD70330/332 (V35)
Figure 20.
Serial Interface· Block Diagram
TxDO
RxDO
CTSO
Baud Rate
Generator
SCKO
TxD1
RxD1
CTS1
Baud Rate
Generator
49-001349B
26
NEe
Figure 21.
pPD70330/332 (V35)
Serial Communication Mode Register (SCM)
4
7
SCM
I
TxRDY
I
RxE
I
PRTY1
PRTYO
I
I
3
I
CL/TSK
I
SL/RSCK
I
MD1
MDO
I
I
MD1 MDO
0
0
Mode
I/O Interface [Note 1]
0
1
Asynchronous
1
X
Reserved
Stop Bit Length/Rcv Clk [Note 3]
0
1 Stop Bit/Ext Clk [input on CTSO]
1
2 Stop Bits/lnt Clk [output on CTSO]
Char Length/Trans Shift Clk [Note 3]
0
7 Bits/No Effect
1
8 Bits/Trigger Transmit
PRTY
Parity Control
1
0
0
0
No Parity
0
1
o Parity [Note 2]
1
0
Odd Parity
1
1
Even Parity
Receiver Control
0
Disable
1
Enable
0
Disable
1
Enable
Transmitter Control
Notes.
[1] Only Channel 0 has I/O interface mode.
[2] When 0 parity is selected, the parity is 0
during transmit and is ignored during receive.
[3] Applies only to I/O interface mode.
49-0013858
27
NEe
pPD70330/332 (V35)
Figure 22.
Serial Communication Error Registers (SCE)
7
SCEn
I
5
6
I
RxD
I
0
I
o
3
4
0
0
I
0
I
ERP
I
ERF
I
ERO
L
Overrun Error Flag
1
o
I Overrun has occurred
I Overrun has not occurred
Framing Error
1
o
I Stop bit not detected
I Framing error has not occurred
Parity Error
o
I
I
1
1 RxD Line = 1
1
Parity error has occurred
No parity error has occurred
RxD Line Status
o
I
RxD Line = 0
49-001386A
Figure 23.
Serial Communication Control Register (SCC)
7
sec
l
0
6
I
0
I
I
0
2
3
4
0
I
PRS3
I
I
PRS2
PRS1
I
o
PRSo
I
PRS
321 0
0000
*AII oth er combinations after 1000 are illegal
Input clock for baud
rate generator
SCLK/2
0001
SCLK/4
00 1 0
SCLK/8
o0 1 1
SCLK/16
01 00
SCLK/32
01 01-
SCLK/64
o 1 1 0
SCLK/128
o 1 1 1
SCLK/256
1 000
SCLK/512*
49-0013888
28
NEe
Figure 24.
pPD70330/332 (V35)
DMA Channels
TC1
SARH1
XXEOEH
I
OARH1
OAR1
SARHO
SAR1
Channel 1
TCO
Channel 0
I
OARHO
OARO
SARO
XXEOOH
1-16 B i t s - J
49-001350A
Figure 25.
DMA Mode Registers (DMAM)
o
4
1
M02
I
·1
MOl
I
MOo
I
1
W
1
EOMA
1
TDMA
1
0
1
0
OMAMO
OMAM1
Trigger OMA [Note 1 J
oJ
1
I
No Effect
Trigger DMA
Enable DMA [Note 2J
o
1
I Disable DMA
I Enable DMA
Word/byte
oI
1
I
Byte Transfers
Word Transfers
DMAMode
MD2
Notes:
[1 J Valid only during single-step and burst
modes.
[2J Cleared when TC = 0; cleared when DMA
transfer is aborted by NMI.
MOl
MOo
0
0
0
Single Step (Mem to Mem)
0
0
1
Demand Release (110 to Mem)
0
1
0
Demand Release (Mem to 1/0)
0
1
1
Reserved
1
0
0
Burst Mode (Mem to Mem)
1
0
1
Single Transfer (110 to Mem)
1
1
0
Single Transfer (Mem to 110)
1
1
1
Reserved
49·001390B
29
!VEe
pPD70330/332 (V35)
Figure 26.
DMA Control Registers (DMAC)
4
I
0
I
0
I
PD1
PD~
I
I
o
2
I
0
I
0
I
PS1
I
I
I
PSO
I
DMACO
DMAC1
Source Address Increment/Decrement Control
PS1
PSO
0
0
Source Address not
Incremented/Decremented
0
1
Increment Source Address
1
0
Decrement Source Address
1
1
Source Address not
Incremented/Decremented
Destination Address IncrementlDecrement Control
PD1
PD~
0
0
Destination Address not
Incremented/Decremented
0
1
Increment Destination
Address
1
0
Decrement Destination
Address
1
1
Des.tination Address not
Incremented/Decremented
49-001391 B
Memory-Io-Memory Transfers. In the single-step
mode, when one DMA request is made, execution of
one instruction and one DMA transfer are repeated
alternately until the prescribed number of DMA transfers has occurred. Interrupts can be accepted while in
this mode. In burst mode, a DMA request causes DMA
transfer cycles to continue until the DMA terminal
counter decrements to zero. Software can also initiate
memory-to-memory tranSfers.
Transfers Between 1/0 and Memory. In single-transfer
mode, one DMA transfer occurs after each rising edge
of DMARa. After the transfer, the bus is returned to the
CPU. In demand release mode, the rising edge of
DMARa enables DMA cycles, which continue as long
as DMARa is high.
In all modes, the TC (terminal count) output pin will
pulse low and a DMA completion 1/0 request will be
generated after the predetermined number of DMA
cycles has been completed.
The bottom of internal RAM contains all the necessary
address information forthe designated DMA channels.
The DMA channel mnemonics are as follows:
TC
SAR
SARH
DAR
DARH
30
Terminal counter
Source address register
Source address register high
Destination address register
Destination address register high
The DMA controller generates physical source
addresses by offsetting SARH 12 bits to the left and
then adding the SAR. The same procedure is also used
to generate physical destination addresses. You can
program the controller to increment or decrement
source andlor destination addresses independently
during DMA transfers.
When the EDMA bit is set, the internal DMARa flag is
cleared. Therefore, DMARQs are only recognized after
the EDMA bit has been set.
Parallel Ports
The pPD70330/332 has three 8-bit parallel 1/0 ports:
PO, P1, and P2. Refer to figures 27 through 31. Special
function register (SFR) locations can access these
ports. The port lines are individually programmable as
inputs or outputs. Many of the port lines have dual
functions as port or control lines.
Use the associated port mode and port mode control
registers to select the mode for a given I/O line.
The analog comparator port (PT) compares each input
line to a reference voltage. The reference voltage is
programmable to be the VTH input x n/16, where n = 1
to 16. See figure 32.
NEe
Figure 27.
pPD70330/332 (V35)
Port Mode Registers 0 and 2 (PMO, PM2)
7
0
PMO
PM2
Output Port Mode
Input Port Mode
49-0013776
Figure 28.
Port Mode Register 1 (PM 1)
5
PM1
I
PM 17
l
I
PM16
PM15
J
I
4
I
PM14
I
1
I
1
1
1
I
1
I
j
n
PMC1 n
PM1 n
0
0
Port P1 n
Output
0
1
Input
= 7, 6, 5, or 4
83-0045376
Figure 29.
Port Mode Control Register 0 (PMCO)
7
6
4
o
49-0013786
31
NEe
pPD70330/332 (V35)
Figure 30.
Port Mode Control Register 1 (PMC1)
7
I
o
4
PMC 17
I
PMC 1S
I
PMC1S
I
PMC14
I
PMC13
I
PMC12
I
PMC 11
I
PMC10
-
I
Port/Control Bit Selection
X
NMI/P10 Input
X
INTPO/P11 Input
X
INTP1/P12 Input
0
INTP2/P13 Input
1
INTAK Output
0
P14 1/0 or POLL Input
1
INT Input
0
P1sI/0
1
TOUT Output
0
P1sI/0
1
SCKO Output
0
P171/0
1
READY Input
49-001379B
Figure 31.
Port Mode Control Register 2 (PMC2)
7
PMC2
I
PMC 27
6
I
PMC2s
2
I
PMC2s
I
PMC24
I
PMC 23
I
PMC22
I
PMC 21
I
o
PMC20
Port/Control Bit Selection
0
110 Port
1
DMAROO Input
0
1/0 Port
1
DMAAKO Output
0
1/0 Port
1
TCOOutput
0
1/0 Port
1
DMAR01 Input
0
1/0 Port
1
DMAAK1 Output
0
1/0 Port
1
TC10utput
0
1/0 Port
1
HLDAK Input
0
1/0 Port
1
HLDRO Output
49-001380B
32
NEe
Figure 32.
Port Mode Register T (PMT)
7
I
0
pPD70330/332 (V35)
4
6
I
0
I
0
I
0
I
PMT3
I
PMT2
I
PMT1
I
PMTo
PMT
J
I
Comparator Port Threshold Selection
0
0
1
0
x 16/16
x 1/16
VTH x 2/16
0
0
1
1
VTH
0
1
0
0
VTH
0
1
0
1
x 3/16
x 4/16
VTH x 5/16
0
1
1
0
VTH
0
1
1
1
VTH
0
0
0
0
VTH
0
0
0
1
VTH
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
x 6/16
x 7116
VTH x 8/16
VTH x 9/16
VTH x 10/16
VTH x 11/16
VTH x 12/16
1
1
0
1
VTH
x 13/16
1
1
1
0
VTH
1
1
1
1
VTH
x 14/16
x 15/16
49-001381 B
Programmable Wait State Generation
You can generate wait states internally to further
reduce the necessity for external hardware. Insertion
of these wait states allows direct interface to devices
whose access times cannot meet the CPU read/write
timing requirements.
When using this function, the entire 1M-byte memory
address space is divided into 128K-blocks. Each block
can be programmed for zero, one, or two wait states, or
two plus those added by the extenal READY signal.
The top two blocks are programmed together as one
unit.
The appropriate bits in the wait control word (WTC)
control wait state generation. Programming the upper
two bits in the wait control word will set the wait state
conditions for the entire I/O address space. Figure 33
shows the memory map for programmable wait state
generation; see figure 34 for a graphic representation
of the wait control word.
Figure
33~
Programmable Wait State Generation
FFFFFH
256K
COOOOH
40000H
20000H
OH
128K
128K
49-001351A
33
NEe
pPD70330J:3'32 (V35)
Standby Modes
halting all internal peripherals. Internal status is maintained. Only a reset or NMI can release this mode.
The two low-power standby modes are HALT and
STOP. Software causes the processor to enter either
mode.
A standby flag in the SFR area is reset by rises in the
supply voltage. Its status is maintained during normal
operation and standby. The STBC register (figure 35)
is not initialized by RESET. Use the standby flag to
determine whether program execution is returning
from standby or from a cold start by setting this flag
before entering the STOP mode.
HALT Mode.
In the HALTrriode, the processor is inactive and the
chip consumes much less power than when operational. The external Qscillator remains functional and
all peripherals are active. Internal status and output
port line conditions are maintained. Any unmasked
interrupt-can release this mode. In the EI state, interrupts subsequently will be processed in vector mode.
In the DI state, program execution is restarted with the
instruction following the HALT instruction.
Special Function Registers
Table 6 shows the special function register mnemonic,
type, address, reset value, and function. The 8 highorder bits of each add ress (xx) are specified by the I DB
register.
STOP Mode.
SFR area addresses not listed in table 6 are reserved. If
read, the contents of these addresses are undefined,
and any write operation will be meaningless.
The STOP mode allows the largest power reduction
while maintaining RAM. The oscillator is stopped,
Figure 34.
Wait Control Word
Walt Contr.ol High
Wait Control Low
7
I
BLK31
I
6
BLK30
5
I
BLK21
BLK20
2
3
.4
I
I
BLK11
I
BLK10
I
BLK01
I
o
BLt<____--JX'-__________________---'X'-_______
tHCRY
II ..
~tSCRY-----'
\
..
tSRYK ~
l~ tHKRY
READY
83SL-5392B
~8
NEe
pPD70330/332 (V35)
Timing Waveforms (cont)
READY Timing 2
B1
BAW
B2IBAW
BAW/BW
BW/B2
B3
(RIW)
CLKOUT
ADDRESS
~~______J)(~
__________________________________________________J)(~________
tHCRY
~tSCRY
III
II ...
..
\
tSRYK
\
READY
I·~SRYK,.
~
1I
t HKRY, - * + -
1\
t HK RY,~
I+83SL·5393B
HLDRQ/HLDAK 1
CLKOUT
HLORQ
~K~_-+--~l-------I.
J------~
Bus control *
14----tDHQHA---~
*A19-AO, 07-00, MREQ, MSTB, IOSTB, R/W
14---------tWHAL--------~
83·0043208
49
m
NEe
pPD70330/332;{V35)
Timing Waveforms (cont)
HLDRQ/HLDAK 2
CLKOUT
HLORQ
~-----tWHQL
Bus control *
____
~
---I---------ll----+-----------....;..----(
tDKH:;:-____~l~l---~-----------~---------~----t-D-H-Q-c~~~~~~~~~~_-_~________
* A19-AO, 07-00, MREQ, MSTB, IOSTB, R/W
83-0043216
INTp, DMARQ Input
CLKOUT
r
INTp,
OMARQ*
_ _- 1
14---------tW.lQH _________--1 :~~~~~~~~~_-_-_~-_-twl~I-Q-L========~~~~:.
* INTP2-INTPO, OMARQ1-0MARQO
83-0043226
POLL Input
CLKOUT
_PO_L_L~-t-S-PL-K--------------
---~!
83-0043236
50
NEe
pPD70330/332.(V35)
Timing Waveforms (coni)
NMllnput
CLKOUT
NMI ----1I4.------twNH-----+lnl4'-.~~~~~~~~~~~-=-tw-N-IL-----------------------+If
83-004324B
CTS Input
CLKOUT
IN TRIINTAK
eLKOUT
INTR
r'I--------I---'
tOKIA tHIAIQ
~---------------------
D7-DO------------~~--------------~----------------------__{1
83-004326B
51
NEe
pPD70330/332 (V35)
Timing Waveforms (cont)
Serial Transmit
CLKOUT
tCYTK
\
-~
I
II
tWSTL
"
tWSTH
)k
TXO
I-tOTKO-+
tHT KD
K=
83MB-005283B
Serial Receive
CLKOUT
•
tCYRK
\
~tWSRL_
"
i\
tWSRH
RXD
!.:=tSROK __
52
tHKRD
•
K
83MB-005284B
NEe
pPD70330/332 (V35)
Instruction Set
Identifier
Instructions, grouped according to function, are
described in a table near the end of this data sheet.
Descriptions include source code, operation, opcode,
number of bytes, and flag status. Supplementary
information applicable to the instruction set is contained in the following tables.
dst-block
Name of block addressed by the IV register
near-proc
Procedure within the current program segment
far-proc
Procedure located in another program segment
near-label
Label in the current program segment
short-label
Label between -128 and +127 bytes from the end
of instruction
• Symbols and Abbreviations
far-label
Label in another program segment
• Flag Symbols
memptr16
Word containing the offset of the memory location
within the current program segment to which control
is to be transferred
memptr32
• Segment Registers. The segment register is specified in the operation code by sreg (OO, 01,10, or 11).
Double word containing the offset and segment base
address of the memory location to which control is to
be transferred
regptr16
• Memory Addressing. The memory addressing mode
is specified in the operation code by mod (OO, 01, or
10) and mem (OOO through 111).
16-bit register containing the offset of the memory
location within the program segment to which control
is to be transferred
pop-value
Number of bytes of the stack to be discarded (0 to
64K bytes, usually even addresses)
fp-op
Immediate data to identify the instruction code of the
external floating pOint operation
• 8- and 16-Bit Registers. When mod = 11, the register
is specified in the operation code by the byte/word
operand (W = 0/1) and reg (OOO to 111).
• Instruction Clock Count. This table gives formulas
for calculating the number of clock cycles occupied
by each type of instruction. The formulas, which
depend on byte/word operand and RAM enable/disable, have variables such as EA (effective address),
W (wait states), and n (iterations or string instructions).
Symbols and Abbreviations
Identifier
Description
reg
8- or 16-bit general-purpose register
reg8
8-bit general-purpose register
reg16
16-bit general-purpose register
dmem
8- or 16-bit direct memory location
mem
8- or 16-bit memory location
mem8
8-bit memory location
mem16
16-bit memory location
mem32
32-bit memory location
sfr
8-bit special function register location
imm
Constant (0 to FFFFH)
imm16
Constant (0 to FFFFH)
imm8
Constant (0 to FFH)
imm4
Constant (0 to FH)
imm3
Constant (0 to 7)
acc
AW or AL register
sreg
Segment register
src-table
Name of 256-byte translation table
src-block
Name of block addressed by the IX register
Description
R
Register set
W
Word/byte field (0 to 1)
reg
Register field (000 to 111)
mem
Memory field (000 to 111)
mod
Mode field (00 to 10)
S:W
When S:W = 01 or 11, data = 16 bits. At all
other times, data = 8 bits.
x, XXX, VVV, ZZZData to identify the instruction code of the
external floating point arithmetic chip
AW
Accumulator (16 bits)
AH
Accumulator (high byte)
AL
Accumulator (low byte)
BP
Base pointer register (16 bits)
BW
BW register (16 bits)
BH
BW register (high byte)
BL
BW register (low byte)
CW
CW register (16 bits)
CH
CW register (high byte)
CL
CW register (low byte)
OW
OW register (16 bits)
DH
OW register (high byte)
DL
OW register (low byte)
SP
Stack pOinter (16 bits)
PC
Program counter (16 bits)
PSW
Program status word (16 bits)
53
NEe
pPD70330/332 (V35)
Symbols and Abbreviations (cont)
Flag Symbols
Identifier
Description
Identifier
Description
IX
Index register (source) (16 bits)
(blank)
No change
IV
Index register (destination) (16 bits)
o
PS
Program segment register (16 bits)
SS
Stack segment register (16 bits)
DSo
Data segment 0 register (16 bits)
DS1
Data segment 1 register (16 bits)
AC
Auxiliary carry flag
CV
Carry flag
P
Parity flag
S
Sign flag
Z
Zero flag
DIR
Direction flag
IE
Interrupt enable flag
V
Overflow flag
BRK
Break flag
MD
Mode flag
(... )
Values in parentheses are memory contents
, disp
Displacement (8 or 16 bits)
Cleared to 0
Set to 1
X
Set or cleared according to the result
U
Undefined
R
Value saved earlier is restored
8- and 16-81t Registers (mod
11)
w=o
W=l
000
AL
AW
001
CL
CW
010
DL
OW
011
BL
BW
100
AH
SP
101
CH
BP
110
DH
IX
111
BH
IV
ext-disp8
16-bit displacement (sign-extension byte
+ 8-bit displacement)
temp
Temporary register (8/16/32 bits)
sreg
tmpcy
Temporary carry flag (1-bit)
00
seg
Immediate segment data (16 bits)
01
PS
offset
Immediate offset data (16 bits)
10
SS
Transfer direction
11
DSo
+
=
reg
Segment Registers
Register
DS1
Addition
Subtraction
Memory Addressing
mod = 10
Multiplication
mem
mod = 00
mod = 01
Division
000
BW+IX
BW + IX + disp8
BW + IX + disp16
%
Modulo
001
BW+IV
BW + IV + disp8
BW + IV + disp16
AND
Logical product
010
BP+ IX
BP + IX +~isp8
BP + IX + disp16
OR
Logical sum
011
BP+IV
BP + IV + disp8
BP + IV + disp16
XOR
Exclusive logical sum
100
IX
IX + disp8
IX + disp16
Two-digit hexadecimal value
101
IV
IV + disp8
IV + disp16
Four-digit hexadecimal value
110
Direct
BP + disp8
BP + disp16
111
BW
BW + disp8
BW + disp16
x
XXH
XXXXH
54
NEe
pPD70330/332 (V35)
Instruction Clock Count
Mnemonic
Operand
Clocks
Mnemonic
Operand
Clocks
ADD
regS, regS
reg16, reg16
2
2
BRK
3
immS
50+5W [3S+5W]
51+5W [39+5W]
regS;memS
reg16, mem16
EA+7+W
EA+7+W
memS, regS
mem16, reg16
EA+10+2W [EA+7+W]
EA+10+2W [EA+7+W]
regS, immS
reg16, immS
reg16, imm16
5
5
6
memS, immS
mem16, immS
mem16, imm16
EA+ 11+2W [EA+9+2W]
EA+9+2W [EA+7+2W]
EA+12+2W [EA+S+2W]
AL, immS
AW, imm16
5
6
ADD4S
BRKCS
15
BRKV
50+5W [3S+5W]
BTCLR
29
BUSLOCK
2
CALL
21+W [17+W]
21+W [17+W]
memptr16
far-proc
memptr32
EA+24+2W [EA+22+2W]
36+2W [32+2W]
EA+32+4W [EA+20+4W]
CY
DIR
2
2
regS, CL
reg16, CL
S
S
memS, CL
mem16, CL
EA+16+2W [EA+13+W]
EA+16+2W [EA+13+W]
CHKIND
CLR1
22+(30+3W)n [22+(2S+3W)n]
ADDC
near-proc
regptr16
Same as ADD
EA+24+2W
ADJ4A
9
ADJ4S
9
ADJBA
17
ADJBS
17
regS, imm3
reg16, imm4
7
7
regS, regS
reg16, reg16
2
2
memS, imm3
mem16, imm4
EA+13+2W [EA+10+W]
EA+13+2W [EA+9+W]
regB, memB
reg16, mem16
EA+7+W
EA+7+W
regS, regB
reg16, reg16
2
memB, regB
mem16, reg16
EA+10+2W [EA+7+W]
EA+10+2W [EA+7+W]
regB, memB
reg16, mem16
EA+7+W
EA+7+W
regB, immB
reg16, imm16
5
6
memB, regB
mem16, reg16
EA+7+W
EA+7+W
memB, immB
mem16, imm16
EA+ 11 +2W [EA+9+2W]
EA+ 12+2W [EA+B+2W]
regB, immB
reg16, immB
reg16, imm16
5
5
6
memB, immB
mem16, immB
mem16, imm16
EA+B+W
EA+9+W
EA+9+W
AL, immB
AW, imm16
5
6
AND
Bcond (conditional branch)
Bor 15
BCWZ
Bor15
BR
near-label
short-label
12
12
regptr16
memptr16
13
EA+16+W
far-label
memptr32
15
EA+23+2W
CMP
CMP4S
CMPBK
1m
2
22+(25+2W)n
memB, memB
mem16, mem16
2S+2W [21+2W]
25+2W [19+2W]
Notes:
(1)
If the number of clocks is not the same for RAM enabled and
RAM disabled conditions, the RAM enabled value is listed first,
followed by the RAM disabled value in brackets; for example,
EA+8+2W [EA+6+W].
(2) Symbols in the Clocks column are defined as follows.
EA = additional clock cycles required 'for calculation of the
effective address
= 3 (mod 00 or 01) or 4 (mod 10)
W = number of wait states selected by the WTC register
n = number of iterations or string instructions
55
NEe
pPD70330/332 (V35)
Instruction Clock Count (cont)
Mnemonic
Clocks
Mnemonic
Operand
Clocks
CMPBKB
16+(23+2W)n
INM
CMPBKW
16+(23+2W)n
mem8, OW
mem16, OW
21+2W [19+2W]
19+2W [15+2W]
mem8, OW
mem16, OW
18+(15+2W)n [1B+(13+2W)n]
1B+(13+2W)n [1B+(9+2W)n]
regB, reg8
regB, imm4
63-155
64-156
CMPM
Operand
mem8
mem16
18+W
19+2W
CMPMB
16+(16+W)n
CMPMW
16+(16+2W)n
CVTBO
19
CVTBW
3
CVTOB
20
CVTWL
B
OBNZ
8 or 17
OBNZE
8 or 17
OBNZNE
DEC
5
2
mema
mem16
EA+13+2W [EA+11+2W]
EA+13+2W [EA+9+2W]
4
DISPOSE
11+W
OIVU
AW, regB
AW,memB
46-56
EA+49+W to EA+59+W
OW:AW, reg16
OW:AW, mem16
54-64
EA+57+W to EA+67+W
AW, regB
AW,mem8
31
EA+34+W
OW:AW, reg16
OW:AW, mem16
39
EA+43+2W
OSO:
2
OS1:
2
EI
EXT
41-121
42-122
2
FP01
55+5W [43+5W]
FP02
55+5W [43+5W]
HALT
INC
56
LOM
N/A
AL, immB
AW, immB
15+W
15+W
AL, OW
AW,OW
14+W
14+W
reg8
reg16
5
2
mem8
mem16
EA+13+2W [EA+11+2W]
EA+13+2W [EA+9+2W]
EA+2
memB
13+W
mem16
13+W
LOMB
mem16
16+ (11+W)n
LOMW
mem8
16+(10+W)n
MOV
regB, reg8
reg16, reg16
2
2
reg8, memB
reg16, mem16
EA+7+W
EA+7+W
memB, reg8
mem16, reg16
EA+5+W [EA+2]
EA+5+W [EA+2]
regB, immB
reg16, imm16
5
6
mem8, imm8
mem16, imm16
EA+6+W
EA+6+W
AL, dmem8
AW, dmem16
10+W
10+W
dmem8, AL
dmem16, AW
B+W [5]
B+W [5]
sreg, reg16
sreg, mem16
4
EA+9+W
reg16, sreg
mem16,sreg
3
EA+6+W [EA+3]
AH, PSW
PSW, AH
2
3
OSO, reg16, memptr32
OS1, reg16, memptr32
EA+17+2W
EA+17+2W
memB, memB
mem16, mem16
22+2W [17+W]
22+2W [17+W]
MOVBKB
memB, memB
16+(1B+2W)n [16+(13+W)n]
MOVBKW
mem16, mem16
16+(1B+2W)n [16+(10+W)n]
12
regB, reg8
reg8, imm4
FINT
IN
LOEA
B or 17
reg8
reg16
01
OIV
INS
MOVBK
MOVSPA
16
MOVSPB
MUL
11
AW, AL, regB
AW, AL, memB
31-40
EA+34+W to EA+43+W
OW:AW, AW, reg16
OW:AW, AW, mem16
39-4B
EA+42+W to EA+51+W
reg16, reg16, immB
reg16, mem16, immB
39-49
EA+42+W to EA+52+W
reg16, reg16, imm16
reg16, mem16, imm16
40-50
EA+43+W to EA+53+W
NEe
pPD70330/332 (V35)
Instruction Clock Count (cont)
Mnemonic
Operand
Clocks
Mnemonic
Operand
Clocks
MULU
regS
memS
24
EA+27+W
PREPARE
imm16, immS
reg16
mem16
32
EA+33+W
immS = 0: 26+W
immS = 1: 37+2W
immS = n > 1: 44+19 (n-1)+2nW
regS
reg16
S
S
memS
mem16
regS
reg16
S
S
memS
mem16
EA+13+2W [EA+10+W]
EA+13+2W [EA+10+W]
CY
2
regS, CL
reg16, CL
7
7
memS, CL
mem16, CL
EA+1S+2W [EA+12+W]
EA+1S+2W [EA+12+W]
regS, imm3
reg16, imm4
6
6
NEG
NOP
NOT
NOT1
OR
OUT
OUTM
PUSH
2
reg16
mem16
13+W [9+W]
EA+ 16+2W [EA+12+2W]
EA+13+2W [EA+10+W]
EA+13+2W [EA+10+W]
OS1
PS
10+W [7]
10+W [7]
4
SS
OSO
10+W [7]
10+W [7]
PSW
R
9+W [6]
74+SW [SO]
immS
imm16
12+W [9]
13+W [10]
memS, imm3
mem16, imm4
EA+12+2W [EA+9+W]
EA+12+2W [EA+9+W]
regS, regS
reg16, reg16
2
2
regS, memS
reg16, mem16
EA+7+W
EA+7+W
memS, regS
mem16, reg16
EA+10+2W [EA+7+W]
EA+10+2W [EA+7+W]
regS, immS
reg16, imm16
S
6
memS, immS
mem16, imm16
REP
2
REPE
2
REPZ
2
REPC
2
REPNC
2
REPNE
2
REPNZ
RET
19+W
19+W
null
pop-value
27+2W
2S+W
RETI
40+3W [34+W]
RETRSI
12
S
S
EA+11+2W [EA+9+2W]
EA+12+2W [EA+S+2W]
memS, 1
mem16,1
EA+16+2W [EA+13+W]
EA+16+2W [EA+13+W]
AL, immS
AW, imm16
S
6
regS, CL
reg16, CL
11+2n
11+2n
immS, AL
immS, AW
11+W
9+W
memS, CL
mem16, CL
EA+19+2W+2n [EA+16+W+2n]
EA+ 19+2W+2n [EA+16+W+2n]
OW,AL
OW,AW
10+W
S+W
regS, immS
reg16, immS
9+2n
9+2n
OW,memS
OW, mem16
21+2W [19+2W]
19+2W [1S+2W]
memS, immS
mem16, immS
EA+1S+2W+2n [EA+ 12+W+2n]
EA+ 1S+2W+2n [EA+12+W+2n]
OW,memS
OW, mem16
1S+(1S+2W)n [1S+(13+2W)n]
1S+(13+2W)n [1S+(9+2W)n]
regS
memS
17
EA+20+2W [EA+1S+2W]
reg16
mem16
11+W
EA+14+2W [EA+11+W]
OS1
SS
12+W
12+W
OSO
PSW
12+W
13+W
R
74+SW [SS]
N/A
ROL
Em
2
null
pop-value
regS, 1
reg16,1
POLL
POP
PS:
ROL4
ROLC
Same as ROL
ROR
Same as ROL
ROR4
regS
memS
RORC
SET1
21
EA+26+2W [EA+24+2W]
Same as ROL
CY
OIR
2
2
57
NEe
pPD70330/332 (V35)
Instruction Clock Count (cont)
Mnemonic
Operand
SET1 (cont) reg8, CL
reg16, CL
Clocks
7
EA+15+2W [EA+ 12+W]
EA+15+2W [EA+12+W]
reg8, imm3
reg16, imm4
6
6
mem8, imm3
mem16, imm4
EA+12+2W [EA+9+W]
EA+12+2W [EA+9+W]
SHL
Same as ROL
SHR
Same as ROL
SHRA
Same as ROL
2
STM
mem8
mem16
13+W [10]
13+W [10]
STMB
mem8
16+(9+W)n [16+(7+W)n]
STMW
mem16
STOP
Same as ADD
SUB4S
22+(30+3W)n [22+(28+3W)n]
SUBC
TEST
TEST1
TRANS
16+(9+W)n [16+(5+W)n]
N/A
SUB
Same as ADD
reg8, reg8
reg16, reg16
4
4
reg8, mem8
reg16, mem16
EA+12+W
EA+11+2W
mem8, reg8
mem16, reg16
EA+12+W
EA+11+2W
reg8, imm8
reg16, imm16
7
8
mem8, imm8
mem16, imm16
EA+9+W
EA+10+W
AL, imm8
AW, imm16
6
5
reg8, CL
reg16, CL
7
mem8, CL
mem16, CL
EA+12+W
EA+12+W
reg8, imm3
reg16, imm4
6
mem8, imm3
mem16, imm4
EA+9+W
EA+9+W
7
6
11+W
TRANSB
11+W
TSKSW
20
58
Operand
Clocks
reg8, reg8
reg16, reg16
3
3
reg8, mem8
reg16, mem16
EA+12+2W [EA+9+W]
EA+12+2W [EA+9+W]
mem8, reg8
mem16, reg16
EA+12+2W [EA+9+W]
EA+12+2W [EA+9+W]
AW, reg16
reg16, AW
4
7
mem8, CL
mem16, CL
55:
Mnemonic
XCH
XOR
4
Same as AND
N'EC
pPD70330/332 (V35)
Instruction Clock Count for Operations
Byte
RAM Enable
Word
RAM Disable
Context switch interrupt
DMA (Single-step mode)
RAM Enable
RAM Disable
27
27
20+2W
20+2W
20+2W
20+2W
DMA (Demand release mode)
17.5+ W+
(13+W).(n-1 )
17.5+ W+
(13+W).(n-1)
17.5 + W+
(13+W).(n-1)
17.5+ W+
(13+W).(n-1)
DMA (Burst mode)
20.5 +2W+
(16+2W).(n-1 )
20.5 + 2W+
(16+2W).(n-1)
20.5 + 2W+
(16+2W).(n-1)
20.5 +2W+
(16+2W).(n-)
19.5 + W
19.5+W
DMA (Single-transfer mode)
Interrupt (lNT pin)
17+W
17+W
57+3W
57+3W
Macro service, sfr - mem
25+W
20+W
25+W
20+W
Macro service, mem - sfr
22+W
21 +W
22+W
21 + W
Macro service (Search char mode), sfr - mem
28+W
28+W
Macro service (Search char mode), mem - sfr
38+W
35+W
Priority interrupt (Vectored mode)
55+5W
55+5W
NMI (Vectored mode)
53+5W
53+5W
W = number of wait states inserted into external bus cycle
n = number of iterations
N = number of clocks to complete the instruction currently executing
Notes:
(1) Every interrupt (except NMI) has an additional associated
latency time of 27 + N clocks. During the 2'7 clocks, the interrupt
controller performs some overhead tasks such as arbitrating
priority. This time should be added to the above listed interrupt
and macro service execution times. NMllatency time is 18 + N
clocks.
(2) The DMA and macro service clock counts listed are the required
number of CPU clocks for each transfer.
(3) When an external interrupt is asserted, a maximum of 6 clocks is
required for internal synchronization before the interrupt request
flag is set. For an internal interrupt, a maximum of 2 clocks
is required.
Pin Request Latency
Clocks
Source
Typ
Max
NMI pin
12 + N
18+ N
INT pin
8+N
8+N
All other interrupts
15+ N
27+ N
DMARa pin
14+N
HLDRa pin
7+2W
59
0>
0
Instruction Set
"t::
Operation Code
Mnemonic
Operand
7 6 5 4 3 2
Operation
07654321 0
No. of
Bytes AC
W
Flags
CY V P S Z
Data Transfer
MOV
o1
reg, reg
reg -
mem, reg
(mem) -
reg, mem
reg -
mem, imm
(mem)-imm
1
reg, imm
reg -
0
1W
acc, dmem
When W = 0 AL When W = 1 AH -
0
o
dmem, acc
When W = 0 (dmem) - AL
When W = 1 (dmem + 1) - AH, (dmem) -
0
000
sreg, reg16
sreg -
reg16 sreg : SS, OSO, OS1
sreg, mem16
sreg -
(mem16) sreg : SS, OSO, OS1
reg16, sreg
reg16 -
000
reg
reg
reg
2
0 0 1 0 0 W mod
reg
mem
2-4
000101 W mod
reg
mem
2-4
mem
3-6
o
reg
(mem)
imm
(dmem)
(dmem + 1), AL -
o
0 0 1 1 W mod 0 0 0
reg
3
W
3
000
o
o
1 1 0
sreg
reg
000
1
mod 0
sreg
mem
2-4
000
o
o
0 1 1 0
sreg
reg
2
000
000
0
mod
reg
mem
2-4
OS1, reg16,
mem32
reg16 - (mem32)
OS1 - (mem32 + 2)
000
o
0 mod
reg
mem
2-4
AH, PSW
AH -
sreg
LOEA
reg16, mem16
reg16 -
mem16
o
o
o
TRANS
src-table
AL-(BW+AL)
1
XCH
reg, reg
reg - - reg
(mem)--reg
AW-- reg16
o
S, Z, x, AC, x, P, x, CY
AH
0 mod 0
sreg
(mem16) -
reg16 - (mem32)
OSO - (mem32 + 2)
AW, reg16
or reg16, AW
N
........
<
W
ell
-.....
2
mem16, sreg
mem, reg
or reg, mem
(,)
AL
sreg
S, Z, x, AC, x, P, x, CY -
"W
(dmem)
OSO, reg16,
mem32
PSW, AH
0
W
W
0
2-3
0 0 0 W
0
1
0
1 0
o
reg
000 0
W 1 1
000 0
W mod
0
0
1 0
0
2-4
1
mod
0 0 1
mem
".....a
mem
2-4
reg
reg
2
reg
mem
2-4
x
x
x x x
1
reg
Repeat Prefixes
REPC
While CW 0# 0, the next byte of the primitive block
transfer instruction is executed and CW is
decremented (- 1). If there is a waiting interrupt,
it is processed. When CY #- 1, exit the loop.
o
11 0 0 1
o
1
REPNC
While CW #- 0, the next byte of the primitive block
transfer instruction is executed and CW is
decremented (- 1). If there is a waiting interrupt,
it is processed. When .CY #- 0, exit the loop.
o
1 1 0 0 1
o
0
~
0
Instruction Set (cont)
Mnemonic
Operand
Operation
Operation Code
7 654 3 2
076543210
No. of
Bytes AC
Flags
CY V P S Z
Repeat Prefixes (cont)
REP
REPE
REPZ
While CW =;t. 0, the next byte of the primitive block
1 1 1 1 0 0
transfer instruction is executed and CW is
decremented (- 1). If there is a waiting interrupt, it is
processed. If the primitive block transfer instruction
is CMPBK or CMPM and Z =;t. 1, exit the loop.
REPNE
REPNZ
While CW =;t. 0, the next byte of the primitive block
1 1 1 1 0 0 1 0
transfer instruction is executed and CW is
decremented (- 1). If there is a waiting interrupt, it is
processed. If the primitive block transfer instruction
is CMPBK or CMPM and Z =;t. 0, exit the loop.
~
~
Primitive Block Transfer
MOVBK
dst-block,
src-block
When W = 0 (IV) - (IX)
DIR = 0: IX - IX + 1, IV - IV + 1
DIR = 1: IX -IX -1, IV -IV-1
When W = 1 (IV + 1, IV) - (IX + 1, IX)
DIR = 0: IX - IX + 2, IV - IV + 2
DIR = 1: IX - IX - 2, IV - IV - 2
1010010W
CMPBK
src-block,
dst-block
When W = 0 (IX) - (IV)
DIR = 0: IX - IX + 1, IV -IV + 1
DIR=1: IX-IX-l, IV -IV-1
When W = 1 (IX + 1, IX) - (IV + 1, IV)
DIR = 0: IX - IX + 2, IV - IV + 2
DIR = 1: IX - IX - 2, IV - IV - 2
1010011W
x
x
x x x x
CMPM
dst-block
When W = 0 AL - (IV)
DIR = 0: IV -IV + 1; DIR = 1: IV When W = 1 AW - (IV + 1, IV)
DIR = 0: IV - IV + 2; DIR = 1: IV -
1 0 1 0 1 1 1 W
x
x
x x x x
IV -1
IV - 2
LDM
src-block
When W = 0 AL - (IX)
DIR = 0: IX -IX + 1; DIR = 1: IX -IX-1
When W = 1 AW - (IX + 1, IX)
DIR = 0: IX - IX + 2; DIR = 1: IX - IX - 2
1010110W
STM
dst-block
When W = 0 (IV) - AL
DIR = 0: IV -IV + 1; DIR = 1: IV -IV-1
WhenW=1 (IV+1,IV)-AW
DIR = 0: IV - IV + 2; DIR = 1: IV - IV - 2
1010101W
16-Bit field -
0000111100
1 1
reg
reg
1:::
"oa
--w
w
o
'w
Bit Field Transfer
INS
regS, regS
regS, imm4
~
16-Bit field -
AW
AW
0000111100
reg
1 1 0 0 0
m
000
o
0
3
4
w
~
..-"
<
W
en
"'-'"
0>
f\)
Instruction Set (cont)
"t:::
Operation Code
Mnemonic
Operand
Operation
7 654 3 2
AW -
o
65432
0
0
No. of
Bytes AC
Flags
CV V P S
z
Bit Field Transfer (cont)
EXT
reg8, reg8
0 0 0
1 1
reg
16-Bit field
o
reg
o
reg8, imm4
AW -
acc, imm8
When W = 0 AL When W = 1 AH -
(imm8)
(imm8 + 1), AL -
When W = 0 AL When W = 1 AH -
(OW)
(OW + 1), AL -
0 0 0 1 1 1 1
1 1 000
reg
16-Bit field
o
0
0
0
3
0
4
0
W
W
0
"W
110
IN
acc, OW
OUT
imm8, acc
OW, acc
o
W
o
W
o
W
~
2
.--.
(imm8)
0
<
W
(OW)
When W = 0 (imm8) - AL
When W = 1 (imm8 + 1) - AH, (imm8) When W = 0 (OW) - AL
When W = 1 (OW + 1) - AH, (OW) -
0
o
0
"D....
W
ell
.......
2
AL
W
0
AL
Primitive Block 110 Transfer
INM
dst-block, OW
When W = 0 (IV) *- (OW)
OIR = 0: IV -IV +' 1; OIR = 1: IV - IV -1
When W = 1 (IV + 1, IV) - (OW + 1, OW)
OIR = 0: IV +- IV + 2; OIR = 1: IV - IV - 2
o
1 1 0 1 1 0 W
OUTM
OW, src-block
When W = 0 (OW) - (IX)
OIR = 0: IX -IX + 1; OIR = 1: IX -IX-1
When W = 1 (OW + 1, OW) - (IX + 1, IX)
OIR = 0: IX -IX + 2; OIR = 1: IX - IX - 2
o
1 1 0 1 1 1 W
reg, reg
reg -
mem, reg
(mem) -
o
o
reg, mem
reg -
reg +(mem)
reg, imm
reg -
reg + imm
n: number of transfers
Addition/Subtraction
ADD
reg + reg
(mem) + reg
0 0 0 0 0
3-6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2-3
x
x
x x x x
W 1 1
reg
reg
2
0 0 0 0 0 0 W mod
reg
mem
2-4
0000001 W mod
reg
mem
2-4
reg
3-4
mem
0
000SW1 1 000
mem, imm
(mem)-(mem)+imm
1 0 0 0 0 0 S W mod 0 0 0
acc, imm
When W' = 0 AL - AL + imm
When W = 1 AW - AW + imm
00OOO10W
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
~
0
Instruction Set (cont)
Mnemonic
Operand
Operation
Operation Code
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
No. of
Bytes AC
Flags
CY V P S Z
Addition/Subtraction (cont)
ADDC
reg, reg
mem, reg
reg, mem
reg, imm
mem, imm
ace, imm
SUB
SUBC
+ reg + CY
(mem) +- (mem) + reg + CY
reg +- reg + (mem) + CY
reg +- reg + i~m + CY
(mem) +- (mem) + imm + CY
Wl'ten W = 0 AL +- AL + imm + CY
When W = 1 AW +- AW + imm + CY
reg +- reg
o
o
o
0 0
0 0
1
o
o
0
0
reg, reg
reg +- reg - reg
mem, reg
(mem) +- (mem) - reg
reg, mem
reg +- reg - (mem)
o
o
reg, imm
reg +- reg - imm
1 0
mem, imm
(mem)+-(mem)-imm
1 0 0
ace, imm
When W = 0 AL +- AL - imm
When W = 1 AW +- AW - imm
o
0
0
o
0
0
o
reg, mem
reg
0 0 0
reg, imm
reg +- reg - imm - CY .
mem, imm
(mem) +- (mem) - imm - CY
1 0
ace, imm
When W = 0 AL +- AL - imm - CY
When W = 1 AW +- AW - imm - CY
o
+-
reg - (mem) - CY
0
0 0 W mod
reg
mem
0
reg
mem
2-4
0
reg
3-4
0
mem
3-6
W mod
S W mod
0
o
o
0
W1
1
reg
reg
W mod
reg
mem
W mod
0
0
2
2-4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x x
x x
x x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2-4
mem
2-4
reg
3-4
0 S W mod
0
mem
3-6
2-3
1
reg
reg
W mod
reg
mem
1 W mod
reg
mem
2-4
reg
3-4
mem
3-6
1
o
0 S W 1 1 0 1 1
0 S W mod
0 W
0 1 1
x
x
x
x
x
x
2
0
o
o
x x x x
x x x x
x x x x
x x x
x x x
x x x x
x
reg
0 W
x
x
x
x
2-3
1
0 S W1
W1
0 0
0
o0
o1
0
o
o
1 0
0 W
0
reg +- reg - reg - CY
reg
reg
0 0
0
o
reg
S W1
0
0
0 1 W 1 1
0 0
0
(mem) +- (mem) - reg - CY
reg, reg
o
o
o
0 0
2
2-4
2-3
~
~
x
x
x
1::
"a
--I
0
W
W
0
"
W
W
N
,.......
<
W
0')
UJ
m
(II
"-'"
(J')
~
Instruction Set (cont)
l:::
Operation Code
Mnemonic
Operand
7 654 3 2
Operation
0765432
0
No. of
Bytes AC
Flags
CV V P S Z
BCD Operation
ADD4S
SUB4S
CMP4S
ROL4
o
0 0 0
o
0
o
dst BCD string - dst BCD string
- src BCD string
o
0 0 0
o
0
000
0
dst BCD string - src BCD string
o
o
0 0 0
o
o
0
o
0 1
0
0
0
reg8
AL
ALL
I
H
ALL
ROR4
Upper 4 bits
I
Lower 4 bits
~
H
mem
Upper 4 bits
I
Lower 4 bits
I
I
reg8
AL
ALL
mem8
AL
ALL
f
2
x
u u u x
2
x
u u u x
0
2
x
u u u x
0
3
0 0 0 0
W
W
0
"W
W
N
reg
~
<
W
en
mem8
AL
reg
0 0 0 1
1 1 000
~
0
dst BCD string
dst BCD string -
+ src BCD string
"a
H
H
reg
Upper 4 bits
I
Lower 4 bits
mem
Upper 4 bits
I
Lower 4 bits
I I
I I
"'-'"
o
0 0 0 1 1 1 1
mod 0 0 0 mem
o
0 1 0 1 000
o
0 0 0 1 1 1 1
reg
1 1 000
o
0 1 0 1
o
1 0
3
o
o
0 1 0 1
o
1 0
3-5
0 0 0 1 1 1 1
mod 0 0 0 mem
3-5
BCD AdJust
ADJBA
ADJ4A
ADJBS
ADJ4S
When (AL AND OFH) >9 or AC= 1,
A~ - AL + 6, AH - AH + 1, AC CY - AC, AL - AL AND OFH
When (AL AND OFH) >9 or AC = 1,
AL - AL + 6, CY - CY OR AC, AC When AL> 9FH, or CY - =
AL - AL + 60H, CY - 1
When (AL AND OFH) >9 or AC = 1,
CY - AC, AL - AL AND OFH
When
AL When
AL -
(AL AND OFH) >9 or AC = 1,
AL - 6, CY - CY OR AC, AC AL > 9FH, or CY - =
AL + 60H, CY - 1
o
o
0 1 1
1 1 1
x
x
u u u u
o
0 1 0 0 1 1 1
x
x
u x x x
o
0
x
x
u u u u
o
0
x
x
u x x x
1,
1,
1,
0
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
7 6 543 2
Operation
0
6 543 2 1 0
No. of
Bytes AC
Flags
CY V P S Z
Increment/Decrement
INC
OEC
reg8
reg8 -
mem
(mem) -
reg16
reg16 -
reg8
regS -
mem
(mem) -
reg16
reg16 -
reg8 + 1
1 0
(mem) + 1
reg16 + 1
1
1
0
000
reg8 - 1
1
(mem) - 1
0
reg16 - 1
o
000
1 W mod 000
reg
2
x
x x x x
mem
2-4
x
x x x x
x
x x x x
reg
1
1 1 0 1 1
1
1 1 W mod
o
o
0
reg
2
x
x x x x
0
mem
2-4
x
x x x x
x
x x x x
reg
0
~
~
Multiplication
MULU
regS
memS
MUL
01
0
1
AW - AL x (memS)
AH = 0: CY - 0, V AH ¥ 0: CY - 1, V -
0
1
o
1 1
o
1 1 1
o
0
reg
2
x
x u u u
1 1 1 1
o
1 1 0 mod 1
o
0
mem
2-4
x
x u u u
reg16
OW, AW - AW x reg16
OW = 0: CY - 0, V - 0
OW ¥ 0: CY - 1, V - 1
1 1 1 1
o
1 1 1 1 1 1
o
0
reg
2
x
x u u u
mem16
OW, AW - AW x (mem16)
OW = 0: CY - 0, V - 0
OW ¥ 0: CY - 1, V - 1
1 1 1 1
o
1 1 1 mod 1
o
0
mem
2-4
x
x u u u
regS
AW - ALx reg8
AH = AL sign expansion: CY AH ¥ AL sign expansion: CY -
1 1 1 1
o
1 1 0 1 1 1
o
1
reg
2
x
x u u u
0, V 1, V -
0
1
AW - AL x (memS)
AH = AL sign expansion: CY AH ¥ AL sign expansion: CY -
1 1 1 1
o
1 1 0 mod 1
o
1
mem
2-4
x
x u u u
0, V 1, V -
0
1
memS
0>
AW - ALx reg8
AH = 0: CY - 0, V AH ¥ 0: CY - 1, V -
1:::
reg16
OW, AW - AW x reg16
OW = AW sign expansion: CY - 0, V - 0
OW ¥ AW sign expansion: CY -1, V-1
1 1 1 1
o
1 1 1 1 1 1
o
1
reg
2
mem16
OW, AW - AW x (mem16)
OW = AW sign expansion: CY - 0, V - 0
OW ¥ AW sign expansion: CY -1, V-1
1 1 1 1
o
1 1 1 mod 1
o
1
mem
2-4
reg16,
reg16,
imm8
reg16 - reg16 x immS
Product:5 16 bits: CY Product> 16 bits: CY -
o
1 1
1
o
1 1 1 1
reg
reg
3
reg16,
mem16,
immS
reg16 - (mem16) x immB
Product:5 16 bits: CY - 0, V - 0
Product> 16 bits: CY - 1, V - 1
o
1 1 0 1
o
1 1 mod
reg
mem
3-5
0, V 1, V -
x
x u u u
u
x
x u u u
u
x
x u u u
x
x u u u
"--..
D
0
W
W
0
o
0
1
"
W
W
~
.......
<
en
W
m
~
~
Instruction Set (cont)
Mnemonic
Operand
1:::
Operation Code
7 6 543 2
Operation
0
654321 0
No. of
Bytes AC
Flags
CYVPSZ
Multiplication (cont)
MUL (cont)
reg16,
reg16,
imm16
reg16 - reg16 x imm16
Product::; 16 bits: CY Product> 16 bits: CY -
0, V 1, V -
0
1
reg16,
mem16,
imm16
reg16 - (mem16) x imm16
Product::; 16 bits: CY - 0, V Product> 16 bits: CY - 1, V -
0
1
0
o
o
0
0
1 10 1 0 0 1 mod
reg
reg
4
x
x u u u
reg
mem
4-6
x
x u u u
reg8
0
--W
W
0
"W
W
I\)
Unsigned Division
DIVU
"a
o
1 1
o
~
1 1 1 1 0 reg
temp-AW
When temp + reg8 > FFH
(SP-1, SP - 2) - PSW, (SP - 3, SP-4) - PS
(SP - 5, SP - 6) - PC, SP - SP - 6
IE -0, BRK - 0, PS - (3,2), PC - (1, 0)
All other times
AH - temp % reg8, AL - temp + reg8
1 1 1 1
mem8
temp-AW
When temp + (mem8) > FFH
(SP-1, SP- 2) - PSW, (SP - 3, SP-4) - PS
(SP - 5, SP - 6) - PC, SP - SP - 6
IE -0, BRK -0, PS - (3, 2), PC - (1, 0)
All other times
AH - temp % (mem8), AL - temp + (mem8)
1 1 1 1
o
1 1 0 mod 1 1 0 mem
2-4
u
u u u u
reg16
temp -AW
When temp + reg16 > FFFFH
(SP -1, SP- 2) - PSW, (SP -3, SP- 4) - PS
(SP - 5, SP - 6) - PC, SP - SP - 6
IE - 0, BRK - 0, PS - (3, 2), PC - (1, 0)
All other times
AH - temp % reg16, AL - temp + reg16
1 1 1 1
o
1 1 1 1 1 1 1 0 reg
2
u
u u u u
mem16
temp-AW
When temp + (mem16) > FFFFH
(SP - 1, SP - 2) - PSW, (SP - 3, SP - 4) - PS
(SP - 5, SP - 6) - PC, SP - SP - 6
IE -0, BRK-O, PS - (3, 2), PC - (1, 0)
All other times
AH - temp % (mem16), AL - temp + (mem16)
1 1 1 1
o
1 1 1 mod 1 1 0 mem
2-4
u
uu u u
2
u
u
u u u u
<
c.»
UI
---
~
~
Instruction Set (cont)
Mnemonic
Operand
Operation
Operation Code
7 6 543 2
0
6543210
No. of
Bytes AC
Flags
CY V P S Z
Signed Division .
DIV
u
temp-- AW
When temp -;- regS> 0 and temp -;- regS> 7FH or
temp -;- regS <0 and temp -;- regS < 0 - 7FH - 1
(SP -1, SP - 2) -- PSW, (SP - 3, SP - 4) -- PS
(SP - 5, SP - 6) -- PC, SP -- SP - 6
IE -- 0, BRK -- 0, PS -- (3, 2), PC -- .(1, 0)
All other times
AH -- temp % regS, AL -- temp -;- reg8
memS
temp W -When temp -;- (mem8) > 0 and (memS) > 7FH or
temp -;- (memS) < 0 and
temp -;- (mem8) < 0 - 7FH - 1
(SP - 1, SP - 2) -- PSW, (SP - 3, SP - 4) -- PS
(SP - 5, SP - 6) -- PC, SP -- SP - 6
IE -- 0, BRK -- 0, PS -- (3, 2), PC -- (1, 0)
All other times
AH -- temp % (mem8), AL -- temp -;- (mem8)
1 1 1 1 0 1 1· 0 mod 1 1 1
mem
2-4
u u u u
reg 16
temp -- AW
When temp -;- reg 16> 0 and reg 16> 7FFFH or
temp -;- reg 16 < 0 - 7FFFH - 1
(SP - 1, SP - 2) -- PSW, (SP - 3, SP - 4) -- PS
(SP - 5, SP - 6) -- PC, SP -- SP - 6
IE -- 0, BRK -- 0, PS -- (3,2), PC -- (1,0)
All other times
AH -- temp % reg. 16, AL -- temp -;- reg 16
1 1 1 1 0 1 1 1 1 1 1 11
reg
2
u u u u
temp -- AW
When temp -;- (mem 16) > 0 and (mem 16) > 7FFFH
or temp -;- (mem 16) < 0 and temp -;- [mem 16]
<0-7FFFH -1
(SP -1, SP - 2)) -- PSW, (SP -3, SP - 4) -- PS
(SP - 5, SP - 6) -- PC, SP -- SP - 6
IE -- 0, BRK -- 0, PS -- (3, 2), PC -- (1, 0)
All other times
AH -- temp % (mem 16), AL -- temp -;- (mem 16)
1 1 1 1 0 1 1 1 mod 1 1 1
mem
2-4
u u u u
mem
16
0
reg
regS
0
u
u u u u
~
~
1::
"
D
o
--w
w
o
"w
w
~
.......
<
W
C>
.....,
m
VI
.......
0)
(X)
Instruction Set (cont)
Mnemonic
Operand
1:::
Operation Code
7 6 5 4 3 2
Operation
o
o
65432
No. of
Bytes AC
Flags
CY V P S Z
o
01000000
o
o
2
u x x x
1 0
01010000
o
o
2
u x x x
CVTBD
AH -
AL +- OAH, AL -
CVTDB
AH -
0, AL -
CVTBW
When AL < 80H, AH - 0,
all other times AH - FFH
o 0
CVTWL
When AL < 8000H, OW - 0,
all other times OW - FFFFH
o
AL %OAH
AH x OAH + AL
000
0 1 1 0 0
reg, reg
o
w
w
o
"'w
W
N
........
Comparison
CMP
"a
~
Data Conversion
reg - reg
0 0
0
W 1 1
reg
reg
2
x
x
x x x x
mem, reg
(mem) - reg
0 0
0 0 W mod
reg
mem
2-4
x
x
x x x x
reg, mem
reg - (mem)
0 0 1 1 1 0 1 W mod
reg
mem
2-4
x
x
x x x x
reg, imm
reg - imm
1 0 0 0 0 0 S W 1 1 1 1 1
reg
3-4
x
x
x x x x
mem, imm
(mem) - imm
1 0 0 0 0 0 S W mod 1 1 1
mem
3-6
x
x
x x x x
ace, imm
When W = 0, AL - imm
When W = 1, AW - imm
0 0 1 1 1 1 0 W
2-3
x
x
x x x x
<
W
(II
........
Complement
NOT
NEG
reg
reg -
0
W 1 1 0
0
reg
mem
(mem) -
reg
(mem)
0
W mod 0
0
mem
2-4
reg
reg -
+1
0
W 1 1 0
reg
2
x
x
x x x x
mem
(mem) -
(mem) + 1
0
W mod 0
mem
2-4
x
x
x x x x
u
0
0 x x x
0
0 x x x
0 x x x
reg
2
Logical Operation
TEST
AND
reg, reg
reg AND reg
0 0 0 0
0 W 1 1
reg
reg
2
mem, reg
or reg, mem
(mem) AND reg
0 0 0 0
0 W mod
reg
mem
2-4
reg, imm
reg AND imm
mem, imm
(mem) AND imm
ace, imm
When W = 0, AL AND imm8
When W = 1, AW AND imm8
o
o
1 1 W 1 1 0 0 0
reg
3-4
o
1 1 W mod 0 0 0
mem
3-6
o
0 x x x
2-3
o
0 x x x
o
o
o
o
0 x x x
o
o
0 x x x
o
o
o
0
000
W 1 1
reg
reg
2
o
o
0 1 0 0 0 0 W mod
reg
mem
2-4
0 1 0 0 0 1 W mod
reg
mem
2-4
reg
3-4
mem
3-6
u
2-3
u
1 0 0 W
reg, reg
reg -
mem, reg
(mem) -
reg, mem
reg -
reg AND (mem)
reg, imm
reg -
reg AND imm
mem, imm
(mem)-(mem)ANDimm
1 0 0 0 0 0 0 W mod 1 0 0
ace, imm
When W = 0, AL - AL AND imm8
When W = 1, AW - AW AND imm16
0010010W
reg AND reg
(mem) AND reg
OOOOOOW11100
u
0 x x x
0 x x x
0 x x x
0 x x x
~
~
Instruction Set (cont)
Mnemonic
Operand
Operation
Operation Code
7 6 5 4 3 2
reg -
0 0 0 0
0 1 W 1 1
reg
0 0 0 0
No. of
Flags
Bytes AC
CY V P S Z
reg
2
0
0 x x x
076543210
Logical Operation (cont)
OR
XOR
reg, reg
reg OR reg
mem, reg
(mem) -
0 0 W mod
reg
mem
2-4
0
0 x x x
reg, mem
reg -
reg OR (mem)
(mem) OR reg
0 0 0 0 1 0 1 W mod
reg
mem
2-4
u
0
0 x x x
reg, imm
reg -
reg OR imm
1 0 0 0 0 0 0 W 1 1 0 0 1
reg
3-4
u
0
0 x x x
mem, imm
(mem) -
1 0 0 0 0 0 0 W mod 0 0 1
mem
3-6
0
0 x x x
ace, imm
When W = 0, AL - AL OR imm8
When W = 1, AW - AW OR imm16
0 0 0 0 1 lOW
2-3
0
0 x x x
o
(mem) OR imm
o
o
reg, reg
reg -
mem, reg
(mem) -
reg, mem
reg -
reg XOR (mem)
reg, imm
reg -
reg XOR imm
mem, imm
(mem)-(mem)XORimm
1 0 0 0 0 0 0 W mod 1 1 0
ace, imm
When W = 0, AL - AL XOR imm8
When W = 1, AW - AW XOR imm16
0011010W
reg XOR reg
0
o0
o0
o
(mem) XOR reg
0 1 W 1 1
reg
reg
2
0 0 W mod
reg
mem
2-4
0
0 x x x
1 1 0 0 1 W mod
reg
mem
2-4
o
0 x x x
reg
3-4
3-6
o
o
0 x x x
mem
2-3
o
0 x x x
0 x x x
0 u u x
0 0 0 0 0 W 1 1 1 1 0
u
~
~
OOxxx
Bit Operation
2nd byte*
TEST1
reg8, CL
reg8 bit no. CL = 0: Z reg8 bit no. CL = 1: Z -
mem8, CL
(mem8) bit no. CL = 0: Z (mem8) bit no. CL = 1: Z -
reg16, CL
reg16 bit no. CL = 0: Z reg16 bit no. CL = 1: Z -
mem16, CL
(mem16) bit no. CL = 0: Z (mem16) bit no. CL = 1: Z -
reg8, imm3
reg8 bit no. imm3 = 0: Z reg8 bit no. imm3 = 1: Z -
mema, imm3
(mema) bit no. imm3 = 0: Z (mem8) bit no. imm3 = 1: Z -
reg16, imm4
reg16 bit no. imm4 = 0: Z-l
reg16 bit no. imm4 = 1: Z - 0
mem16, imm4
(mem16) bit no. imm4 = 0: Z (mem16) bit no. imm4 = 1: Z -
1
0
1
0
1
0
1
0
1
0
1
0
1
0
3rd byte*
000
o
0 0 0 1 1 0 0 0
reg
3
o
000
o
0 0 0 mod 0 0 0
mem
3-5
o 0
000
000
1 1 0 0 0
reg
3
000
000
mod 0 0 0
mem
u u x
o
0 u u x
3-5
o
0 u u x
o
0 u u x
o
0 u u x
u
000
00011000
reg
4
000
o
mem
4-6
000
o 0
1 1 0 0 0
reg
4
o
0 u u x
000
o 0
mod 0·0 0
mem
4-6
o
0 u u x
0 0 mod 0 0 0
2nd byte*
*Note: First byte = OFH
3rd byte*
u
1:::
"a
o--w
w
o
"w
W
N
.--..
<
W
en
.......
0">
<0
II
-...,J
0
1::
Instruction Set (cant)
Mnemonic
Operand
Operation Code
7 65 4 3 2 1 0 76 543 2 1 0
Operation
Flags
No. of
Bytes AC CYVPSZ
Bit Operation (cant)
2nd byte*
NOT1
reg8, CL
reg8 bit no. CL -
mem8, CL
(mem8) bit no. CL -
reg16, CL
reg16 b:~ no. CL -
mem16, CL
(mem16) bit no. CL -
reg8 bit no. CL
(mem8) bit no. CL
reg16 bit no. CL
(mem16) bit no. CL
reg8, imm3
reg8 bit no. imm3 -
mem8, imm3
(mern8) bit no. imm3 -
reg16, imm4
reg16 bit no. imm4 -
mem16, imm4
(mem16) bit no. imm4 -
reg8 bit no. imm3
(mem8) bit no. imm3
(reg16) bit no. imm4
(mem16) bit no. imm4
reg
3
mod 0 0 0
mem
3-5
11 0 0 0
reg
3
1 mod 0 0 0
mem
3-5
011000
reg
4
mod 0 0 0
mem
4-6
000
1 1 0 0 0
reg
4
000
mod 0 0 0
mem
4-6
000
0
011000
0
o
000
0
000
0
000
1
o
000
2nd byte*
*Note: First byte = OFH
CV
reg8, CL
reg8 bit no. CL -
mem8, CL
(mem8) bit no. CL -
reg16, CL
reg16 bit no. CL -
000
0
000
0
000
0
mem16, CL
(mem16) bit nO.CL -
reg8, imm3
reg8 bit no. imm3 -
mem8, imm3
(mem8) bit no. imm3 -
reg16, imm4
reg16 bit no. imm4 -
mem16, imm4
(mem16) bit no. imm4 -
0
0
0
"
W
W
~
......
<
W
CD
"-"
x
0 -1 O· 1 1 0 0 0
0
0
3rd byte*
o
0
reg
mod 0 0 0
mem
1 1 0 0 0
reg
3
3-5
3
0
1 mod 0 0 0
mem
3-5
000
0
011000
reg
4
000
0
o
mod 0 0 0
mem
000
0
1 1 0 0 0
reg
4
000
0
mod 0 0 0
mem
4-6
000
0
0
o
o
o
o
W
W
3rd byte*
1 1 110101
CV-CV
2nd byte*
CLR1
0
3rd byte*
000
"....a
2nd byte*
*Note: First byte = OFH
CV
CV-O
1 1 1 1 1 0 0 0
DIR
DIR-O
11111100
4-6
3rd byte*
0
~
~
~
Instruction Set (cont)
Operalion Code
Mnemonic
Operand
7 6 5 4 3 2
Operation
076543210
Flags
No. of
Bytes AC CY V P S Z
Bit Operation (cont)
SET1
reg8. CL
reg8 bit no. CL -
mem8. CL
(mem8) bit no. CL -
reg16. CL
reg16 bit no. CL -
000
0
o
o
000
0
0
1 1 0 0 0
000
0
000
o
o
o
0 mod 0 0 0
000
0
000
0
000
1
1
1
mem16. CL
(mem16) bit no. CL -
reg8. imm3
reg8 bit no. imm3 -
memS. imm3
(mem8) bit no. imm3 -
reg16. imm4
reg16 bit no. imm4 -
mem16, imm4
(mem16) bit no. imm4 -
1
1
0
000
1
1
1
0
000
0 mod 0 0 0
3-5
reg
3
1 mod 0 0 0
mem
3-5
0 1 1 000
reg
4
mem
4-6
1 1 000
reg
4
mod 0 0 0
mem
4-6
2
u
x
x x x x
~
~
3rd byte*
CY
CY-1
1 1 1 1 1 0 0 1
DlR
DIR-1
1 1
reg. 1
CY - MSB of reg. reg - reg x 2
When MSB of reg -F CY, V-1
When MSB of reg = CY, V - 0
mem.1
CY - MSB of (mem). (mem) When MSB of (mem) -F CY. V When MSB of (mem) = CY. V -
reg, CL
temp - CL. while temp -F O.
repeat this operation. CY - MSB of reg.
reg - reg x 2. temp - temp - 1
1 101001W1 1 1 0 0
mem.CL
temp - CL. while temp -F O.
repeat this operation. CY - MSB of (mem).
(mem) - (mem) x 2. temp - temp - 1
1 1
reg. imm8
temp - imm8. while temp -F O.
repeat this operation. CY - MSB of reg.
reg·+-- reg x 2. temp - temp-1
1 100000W1 1 1 0 0
memo imm8
temp - imm8. while temp -F 0,
repeat this operation. CY - MSB of (mem).
(mem) - (mem) x 2. temp - temp - 1
1 1
CY - LSB of reg. reg - reg -:- 2
When MSB of reg -F bit following MSB
of reg: V-1
When MSB of reg = bit following MSB
of reg: V - 0
1 1
o
3
mem
2nd byte*
*Note: First byte = OFH
1 1
reg
1
Shiff
SHL
SHR
::1
reg. 1
(mem) x 2
1
0
0
1 1 0 1
o
1
o
0 0 W 1 1 1 0 0
reg
o
0 0 W mod 1 0 0
mem
2-4
u
x
x x x x
reg
2
u
x
u x x x
mem
2-4
u
x
u x x x
't::
reg
3
x
u x x x
0
mem
3-5
x
u x x x
o
0 1 W mod 1
o
0
o
0 0 0 0 W mod 1 0 0
o
1
u
n: number of shifts
o
0 0 W 1 1 1
o
1
reg
2
u
x
x x x x
,.a
--..
e.»
e.»
0
'e.»
e.»
t-)
...-.
<
e.»
m
CII
~
~
I\)
,.a
Instruction Set (cont)
Mnemonic
't::
Operation Code
7 654 3 2 1 0765432 1 0
Operand
Operation
mem,1
CV - LSB of (mem), (mem) - (mem) + 2
When MSB of (mem) "" bit following MSB
of (mem): V - 1
When MSB of (mem) =bit following MSB
of (mem): V - 0
No. of
Bytes AC
Flags
CYVPSZ
2-4
x
Shift (cont)
SHR (cont)
SHRA
o
0
0 0 W mod
mem
0
u
0
--W
W
x x x x
0
reg, CL
temp - CL, while temp"" 0,
repeat this operation, CV - LSB of reg,
reg - reg + 2, temp - temp - 1
1 1
o
1
o
0 1 W 1 1 1
o
1
reg
2
mem, CL
temp- CL, while temp"" 0,
repeat this operation, CV - LSB of (mem),
(mem) - (mem) + 2, temp - temp - 1
1 1
o
1
o
0 1 W mod 1
o
1
mem
2-4
reg, immB
temp -immB, while temp #- 0,
repeat this operation, CV - LSB of reg,
reg - reg + 2, temp - temp - 1
1 1 OOOOOW1 1 1
o
1
reg
mem, immB
temp- immB, while temp"" 0,
repeat this operation, CV - LSB of (mem),
(mem) - (mem) +2, temp - temp - 1
1 1
o
1
mem
reg, 1
CV '+- LSB of reg, reg"'::' reg + 2, V MSB of operand does not change
0
0
o
0 0 W 1 1
reg
mem,1
CV - LSB of (mem), (mem) - (mem) + 2,
V - 0, MSB of operand does not change
0
o
0 0 W mod
mem
reg, CL
temp - CL, while temp"" 0,
repeat this operation, CV - LSB of reg,
reg - reg + 2, temp - temp - 1
MSB of operand does not change
0
o
0
mem, CL
temp - CL, while temp"" 0,
repeat this operation, CV - LSB of (mem),
(mem) - (mem) + 2, temp - temp - 1
MSB of operand does not change
1 1
o
0 1 W mod 1 1 1
reg, immB
temp - immB, while temp"" 0,
repeat this operation, CV - LSB of reg,
reg - reg + 2, temp - temp - 1
MSB of operand does not change
1 1 OOOOOW1 1 1 1 1
melTl; immB
temp - immB, while temp"" 0,
repeat this operation, CV - LSB of (mem),
(mem) - (mem) + 2, temp - temp - 1
MSB of operand does not change
1 1
x
u x x x
x
u x x x
x
u x x x
"
W
W
N
....."
o
0 0 0 0 W mod 1
u
<
W
UI
"-'"
3
3-5
u
x
u x x x
2
u
x
o
x x x
2-4
x
o
x x x
reg
2
x
u x x x
mem
2-4
u
x
u x x x
reg
3
u
x
u x x x
mem
3-5
x
u x x x
n: number of shifts
o
o
1
W 1 1
0 0 0 0 W mod 1 1 1
n: number of shifts
I
~
~
~
Instruction Set (cont)
Mnemonic
Operation Code
7 6 5 4 3 2
Operand
Operation
reg, 1
CY - MSB of reg, reg - reg x 2 + CY
MSB of reg ¥- CY: V - 1
MSB of reg = CY: V - 0
mem, 1
CY - MSB of (mem),
(mem) - (mem) x 2 + CY
MSB of (mem) ¥- CY: V - 1
MSB of (mem) = CY: V - 0
1 1
o
reg, CL
temp - CL, while temp ¥- 0,
repeat this operation, CY - MSB of reg,
reg - reg x 2 + CY
temp - temp - 1
1 1
mem,CL
temp - CL, while temp ¥- 0,
repeat this operation, CY - MSB of (mem),
(mem) - (mem) x 2 + CY
temp - temp - 1
1 1
reg, immB
No. of
Bytes AC
Flags
CY V P S Z
reg
2
x
x
07654321 0
Rotation
ROL
ROR
o
0 0 W
1
o
0 0 W mod 0 0 0
mem
2-4
x
x
o
1
o
0 1 W 1 1 000
reg
2
x
u
o
1
o
0 1 W mod 0 0 0
reg
2-4
x
u
temp - immB, while temp ¥- 0,
repeat this operation, CY - MSB of reg,
reg - reg x 2 + CY
temp - temp - 1
1 1 00000W1 1 000
reg
3
x
u
mem, immB
temp - immB, while temp ¥- 0,
repeat this operation, CY - MSB of (mem),
(mem) - (mem) x 2 + CY
temp - temp - 1
1 1
o
0 0 0 0 W mod 0 0 0
mem
3-5
x
u
reg, 1
CY - LSB of reg, reg - reg -;- 2
MSB of reg - CY
MSB of reg ¥- bit following MSB of reg: V - 1
MSB of reg = bit following MSB of reg: V - 0
1 1
o
1
o
0 0 W 1 1
reg
2
x
x
mem, 1
CY - LSB of (mem), (mem) - (mem) -;- 2
MSB of (mem) - CY
MSB of (mem) ¥- bit following MSB
of (mem): V - 1
MSB of (mem) = bit following MSB
of (mem): V - 0
1 1
o
1
o
0 0 W mod 0 0 1
mem
2-4
x
x
temp - CL, while temp ¥- 0,
repeat this operation, CY - LSB of reg,
reg - reg -;- 2, MSB of reg - CY
temp - temp - 1
1 1
temp - CL, while temp ¥- 0,
repeat this operation, CY - LSB of (mem),
(mem) - (mem) -;- 2, MSB of (mem) - CY
temp - temp - 1
1 1
reg, CL
mem, CL
......,
(..)
0
000
~
~
n: number of shifts
o
0 1
'l::::
"
--,
D
0
o
o
1
1
o
o
0 1 W 1 1
o
W
W
0 1
reg
2
x
u
0
W
W
0 1 W mod 0 0 1
n:number of shifts
m
mem
2-4
x
u
t-)
.--..
<
W
(II
.......
;;!
Instruction Set (cont)
Mnemonic
Operand
1::
Operation Code
7 6 5 4 3 2
Operation
0
654321 0
No. of
Bytes AC
Flags
CYVPSZ
ROR (cont)
reg, immB
mem, immB
temp - immB, while temp # 0,
repeat this operation, CY - LSB of reg,
reg - reg +- 2, MSB of reg - CY
temp - temp-1
o
0
o
0 0 W
o
0
reg
3
x
u
0
W
W
,0
temp - immB, while temp # 0,
repeat this operation, CY - LSB of (mem),
(mem) ' - (mem) +- 2
temp -temp - 1
1 1
reg, 1
tmpcy - CY, CY - MSB of reg
reg - reg x 2 + tmpcy
MSB of reg = CY: V - 0
MSB of reg # CY: V - 1
1 1
o
1
o
0 0 W 1 1
mem, 1
tmpcy - CY; CY - MS6 of (mem)
(mem) - (mem) x 2 + tmpcy
MSB of (mem) = CY: V - 0
MSB of (mem) # CY: V - 1
1 1
o
1
o
0 0 W mod 0 1 0
reg, CL
temp - CL, while temp # 0,
repeat this operation, tmpcy - CY,
CY - MSB of reg, reg - reg x 2 + tmpcy
temp - temp - 1
1 1
o
1
o
0 1 W 1 1
mem, CL
temp - CL, while temp #0,
repeat this operation, tmpcy CY - MSB of (mem),
(mem) - (mem)'x 2 + tmpcy
temp - temp - 1
1 1
o
1
o
0 1 W mod 0 1 0
0 0 0 0 W mod 0 0 1
mem
3-5
x
u
o
o
W
W
N
..-.
n: number of shifts
Rotate
ROLC
"a
~
Rotation (cont)
1 0
1 0
reg
2
x
x
mem
2-4
x
x
reg
2
x
u
mem
2-4
x
u
reg
3
x
u
mem
3-5
x
u
<
en
"'-"
W
CY,
reg, immB
temp - immB, while temp # 0,
repeat this operation, tmpcy - CY,
CY - MSB of reg, reg - reg x 2 + tmpcy
temp - temp - 1
1 1 00000W1 1
mem, immB
temp - immB, while temp # 0,
repeat this operation, tmpcy - CY,
CY - MSB of (mem)
(mem)-- (mem) x 2 + tmpcy
temp - temp - 1
1 1
o
o
1 0
0 0 0 0 W mod 0 1 0
n: number of shifts
~
~
t)
Instruction Set (cont)
Mnemonic
Operand
Operation Code
7 6 5 4 3 2
Operation
0
No. of
Bytes AC
Flags
CY V P S Z
reg
2
x x
mem
2-4
x x
reg
2
x u
mem
2-4
x u
reg
3
x u
mem
3-5
x u
6543210
Rotate (cont)
RORC
reg, 1
mem, 1
tmpcy - CY, CY - LSB of reg
reg - reg -;- 2, MSB of reg - tmpcy
MSB of reg # bit following MSB of reg: V MSB of reg = bit following MSB of reg: V tmpcy - CY, CY - LSB of (mem)
(mem) - (mem) -;- 2, MSB of (mem) MSB of (mel]1) # bit following MSB
of (mem): V - 1
MSB of (mem) = bit following MSB
of (mem): V - 0
0
o
0 0 W
0
1
0
1 1
o
1
o
0 0 W mod 0 1 1
tmpcy
o
reg, CL
temp - CL, while temp # 0,
repeat this operation, tmpcy - CY,
CY - LSB of reg, reg - reg -;- 2,
MSB of reg - tmpcy, temp - temp - 1
1 1
o
1
o
0 1 W1 1
mem, CL
temp - CL, while temp # 0,
repeat this operation, tmpcy - CY,
CY - LSB of (mem), (mem) - (mem) -;- 2
MSB of (mem) - tmpcy, temp - temp - 1
1 1
o
1
o
0 1 W mod 0 1 1
reg, immB
temp - immB, while temp # 0
repeat this operation, tmpcy - CY,
CY - LSB of reg, reg - reg -;- 2
MSBof reg - tmpcy, temp - temp-1
1 1 00000W1 1
mem, immB
temp - immB, while temp # 0,
repeat this operation, tmpcy - CY,
CY - LSB of (mem), (mem) - (mem) -;- 2
MSB of (mem) - tmpcy, temp - temp - 1
1 1
o
o
1 1
1 1
0 0 0 0 W mod 0 1 1
Subroutine Control Transfer
CALL
""-.I
CJ'1
~
~
near-proc
(SP - 1, SP - 2) PC - PC +disp
PC, SP -
SP - 2
regptr16
(SP - 1, SP - 2) PC - regptr16
PC, SP -
SP - 2
1 1 0
0
reg
2
memptr16
(SP - 1, SP - 2) - PC, SP PC - (memptr16)
SP - 2
mod 0
0
mem
2-4
far-proc
(SP - 1, SP - 2) - PS, (SP - 3, SP - 4) SP - SP - 4, PS - seg, PC - offset
PC
memptr32
(SP -1, SP -2) - PS, (SP -3, SP-4) SP - SP - 4, PS - (memptr32 + 2),
PC - (memptr32)
PC
0
o
0
000
0
3
5
0
mod 0 1 1
mem
2-4
,.
1::
D
.....
0
W
W
0
"W
W
N
~
<
W
m
CIt
.......
--...I
0)
Instruction Set (cont)
Mnemonic
Operand
"t::
Operation Code
7 654 3 2
Operation
076543210
No. of
Bytes AC
Flags
CYVPSZ
Subroutine Control Transfer (cont)
RET
pop-value
o
o
0 0 0
(SP + 3, SP + 2)
o
0
0
(SP + 1, SP), PS - (SP + 3, SP + 2)
SP + 4, SP - SP + pop-value
o
0
0
PC -
(SP + 1, SP), SP -
PC SP -
(SP + 1, SP)
SP + 2, SP -
SP + 2
PC SP -
0
SP + pop-value
PC - (SP + 1, SP ), PS SP-SP+4
pop-value
Q
3
0
"W
W
~
3
0
.--.
<
W
Stack Manipulation
PUSH
POP
PREPARE
mem16
(SP -1, SP - 2) -
reg16
(SP -1, SP - 2) -reg16, SP -
sreg
(SP-1, SP- 2) -
PSW
(SP -1, SP -2) -
(mem16), SP -
sreg, SP -
SP - 2
PSW, SP -
1 1 1 mod 1 1 0
SP - 2
SP - 2
SP - 2
0
o
0
0 0 sreg
Push registers on the stack
0
00000
0
0
mem16
(mem16) reg16 -
(SP + 1, SP), SP -
SP + 2
o
S 0
000
SP + 2
sreg - (SP + 1, SP) sreg : SS, DSO, DS1
SP-SP+2
o
o
2-3
mod 0 0 0
PSW -
Pop registers from the stack
0
imm16, immS
Prepare new stack frame
11001000
*: immS = 0: 16
immS> 1: 25 + 16 (immS -1)
DISPOSE
Dispose of stack frame
2-4
1 1
0 0 sreg
PSW
SP + 2
mem
reg
1 0
R
(SP + 1, SP), SP -
---
1 0
(SP ~ 1, SP - 2) - imm
SP - SP - 2, When S = 1, sign extension
sreg
en
2-4
1 0 0 1 1 1 0 0
imm
(SP + 1, SP), SP -
mem
reg
0
R
reg16
a--I
0
W
1
0 0 0
-a
1001110
o
R
R R R R R
0 0 0 1
4
1001001
Branch
BR
near-label
PC -
PC+ disp
0
o
short-label
PC -
PC + ext-dispS
0
0
regptr16
PC -
regptr16
1
1 1 1
memptr16
PC -
(memptr16)
1
1 mod
far-label
PS -
seg, PC -
memptr32
PS -
(memptr32 + 2), PC -
0
offset
(memptr32)
0
0
3
2
o
o
0
reg
0
mem
0
2
2-4
5
mod
0
mem
2-:4
~
t'l
Instruction Set (cont)
Mnemonic
Operand
Operation Code
7 6 543 2
Operation
076543210
No. of
Bytes AC
Conditional Branch
PC + ext-dispS
0
PC + ext-dispS
0
o
o
o
o
0 1 1
2
0
0
o
0
2
0
0
0
0
2
BV
short-label
if V = 1, PC -
PC + ext-dispS
0
BNV
short-label
if V = 0, PC -
PC + ext-dispS
0
BC,Bl
short-label
if CY = 1, PC -
BNC,BNl
short-label
if CY = 0, PC -
BE,BZ
short-label
if Z = 1, PC -
PC + ext-dispS
BNE, BNZ
short-label
if Z = 0, PC -
PC + ext-dispS
BNH
short-label
if CY OR Z = 1, PC -
PC + ext-dispS
0
0
BH
short-label
if CY OR Z = 0, PC -
PC + ext-dispS
0
o
BN
short-label
if S = 1, PC -
PC + ext-dispS
0 0 0
2
0 0 1
2
0
1
1
2
0
000
2
0 1
2
1 0
2
BP
short-label
if S = 0, PC -
PC + ext-dispS
0
BPE
short-label
if P= 1, PC -
PC + ext-dispS
0
o
o
PC + ext-dispS
0
0
BPO
short-label
if P= 0, PC -
BLT
short-label
if S XOR V = 1, PC -
PC + ext-dispS
0
BGE
short-label
if S XOR V = 0, PC -
PC + ext-dispS
0
BlE
short-label
if (S XOR V) OR Z = 1, PC -
PC + ext-dispS
0
BGT
short-label
if (S XOR V) OR Z = 0, PC -
PC + ext-dispS
0
DBNZNE
short-label
CW-CW-1
if Z = 0 and CW ¥- 0, PC -
PC + ext-dispS
DBNZE
short-label
CW-CW-1
if Z = 1 and CW ¥- 0, PC -
PC + ext-dispS
DBNZ
short-label
CW-CW-1
if CW ¥- 0, PC -
PC + ext-dispS
PC + ext-dispS
BCWZ
short-label
if CW = 0, PC -
BTClR
sfr. imm3,
short-label
if bit no. imm3 of (sfr) = 1,
PC - PC + ext - dispS,
bit no. imm3 of (sfr) - 0
0
3
immS
(¥- 3)
'-I
'-I
~
~
2
o
o
0
2
1
2
0
1
2
00000
o
0 0 0
000
2
0
,.a
1:::
1 1 1 0 0 0
o
0 0 0
2
1 0 1 1 1 1 0 0
5
.....
0
W
W
Interrupt
BRK
Flags
CV V P S Z
(SP -1, SP- 2) - PSW, (SP - 3, SP - 4) (SP - 5, SP - 6) - PC, SP - SP - 6
IE-O, BRK-O
PS - (15, 14), PC - (13,12)
PS,
(SP -1, SP- 2) - PSW, (SP - 3, SP - 4) (SP - 5, SP - 6) - PC, SP - SP - 6
IE-O, BRK-O
PC - (n x 4, + 1, n x 4)
PS - (n x 4 + 3, n x 4 + 2) n = immS
PS,
0
1 1 0 0 1 1 0 0
"W
W
I\)
1 1 0 0 1 1 0 1
2
---.
<
W
en
.......
IfJ
.......
(Xl
,.a
"t::
Instruction Set (cont)
Operation Code
Mnemonic
Operand
7 654 3 2
Operation
No. of
Flags
Bytes AC CYVPSZ
076543210
R R R R R
-.a
0
c.»
c.»
0
"c.»
c.»
R R R R R
...-..
Interrupt (cont)
BRKV
When V = 1
(SP-1, SP -2) - PSW, (SP-3, SP-4) (SP - 5, SP - 6) - PC, SP - SP - 6
IE-O, BRK"';"'O
PS - (19,18), PC - (17, 16)
RETI
o0
o0
PC - (SP+ 1, SP), PS - (SP+3, SP+2),
PSW -- (SP + 5, SP + 4), SP - SP + 6
RETRBI
PC ....,. Save PC, PSW -
FINT
Indicates that interrupt service routine to the
interrupt controller built in the CPU has been
completed
CHKINO
reg16,
mem32
0
PS,
Save PSW
When (mem32) > reg16 or (mem32 + 2) < reg16
(SP -1, SP-2) - PSW, (SP-3, SP-4) - PS,
(SP - 5, SP - 6) - PC, SP - SP - 6
IE-O, BRK-O,
PS - (23, 22), PC - (21, 20)
o0
o0
R
o0
o0
0 0
0 0
000
o0
2
R
~
<
c.»
(II
2
0
"-'"
o
1 1 0 0 0 1 0 mod
reg
mem
1 1
1 1
2-4
CPU Control
CPU Halt
STOP
CPU Halt
BUS LOCK
Bus Lock Prefix
FP01 (Note 1) fp-op
fp-op, mem
FP02 (Note 1) fp-op
fp-op, mem
00001111
1
No Operation
data bus -
(mem)
No Operation
data bus -
o0
1 1 1 0
HALT
o
0
X X X
X X X mod Y Y Y
1
o0
o0
o0
o0
1
POLL
Poll and wait
NOP
No Operation
01
IE-O
1 1
EI
IE-1
1 1
0
OSO; OS1;
PS;SS
Segment override prefix
o0
Notes:
(1)
Does not execute on the V25, but does generate an interrupt.
0
YYYZZZ
mem
2
2-4
X11YYYZZZ
2
X mod Y Y Y
2-4
1 0
1
o0
0 0
0
0
sreg
1 0
0 0
0
0
(mem)
o0
mem
1
0
I
~
~
NEe
pPD70330/332 (V35)
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
"-01
"-01
~
~
0
0
0..-
0..-
0
0
0..-
0..-
0
0
0..-
0..-
0
0
0..-
0..-
~
~
(0
~
~
~
:c:
01
as
01
1m
C,
/XI
...
.! «c..
~
2»
a:
ED
c..
en
en en
> u
:::.::: >
0
0
3:
en
ED
I-
::!!:
a:
::!!:
:::.:::
en
79
pPD70330/332 (V35)
80
NEe
NEe
pPD70P322
16-Bit Microcomputer:
Single-Chip, CMOS,
With EPROM for V25N35 Modes
NEG Electronics Inc.
Description
Features
The jiPD70P322 is a 16-bit, single-chip CMOS microcomputer operable as a jiPD70322 (V25™) or a
jiPD70332 (V35™). The mask ROM of the V25N35 is
replaced in the jiPD70P322 by an EPROM.
o Reprogrammable EPROM appropriate for system
evaluation of V25 or V35
o V25 mode (,uPD70322 equivalent)
-Internal 16-bit architecture
- External 8-bit data bus
Ordering Information
Part Number
Ext Input
Frequency
Int System
Clock
JiPD70P322K-8
16 MHz
8 MHz
o V35 mode (,uPD70332 equivalent)
-Internal 16-bit architecture
- External 16-bit data bus
Package
84-pin ceram ic LCC
with quartz window
V25 and V35 are trademarks of NEC Corporation
"PD70P322 Block Diagram
~
DMARQO
Ao
DMAAKO
Ag-A 16 /A 1 -A 8
TCO
DMARQ1
DMAAK1
A17 /A 18
A18 /UBE
Controller
A19
TC1
RESET
TxDO
HLDAK
RxDO
HLDRQ
SCKO
Internal EPROM
16K Bytes
CTSO
TxD1
READY
MREQ
MSTB
RxD1
RlW
CTS1
IOSTB
POLL
NMI
INTPO
Instruction Decoder
INTP1
Micro Sequencer
INTP2I
Micro ROM
V25N35
PROG
CE
INTAK
OE
INT
Vpp
DO-D7 (V25 Mode)
Do-D15 (V35 Mode)
X1
X2
- - - VDD
TOUT
CLKOUT
PO
P1
P2
PTO-PT7
V TH
- - - GND
83YL-68178
50283-1
N'EC
pPD70P322
Pin Configurations
84-Pin LCe, V25 Mode
P07/CLKOUT
74
00
73
PT6
01
72
PT5
02
71
PT4
03
70
PT3
04
69
PT2
05
68
PT1
06
67
PTO
07
66
P17/REAOY
Ao
65
P16/SCKO
A1
64
P15fTOUT
A2
63
P14/INT/POLL
A3
62
P13/INTP2fINTAK
A4
61
P12/INTP1
A5
60
P11/INTPO
A6
59
NMI
A7
58
P27/HLORQ
A8
57
P26/HLOAK
PT7
A9
56
P25~
A10
55
P24/0MAAK1
An
P23/0MARQ1
81C.!'l CI~18Q
a:~$l:$t:::
~a.
Pin
Symbol
Connect to
3
V
9
V25N35
VOO
High level (H)
~gj
e
e
~
~
49
PROG
High level (H)
53,75
IC
High level through pullup resistor
a.
83YL-6794B
2
1t¥EC
pPD70P322
84-Pin LCC, V35 Mode
P07/ClKOUT
74
00
73
PT7
PT6
01
72
PT5
02
71
PT4
03
70
PT3
04
69
PT2
05
68
PT1
06
67
07
08
66
65
P16/SCKO
09
64
P15ITOUT
0 10
0 11
0 12
0 13
PTO
,P17/REAOY
63
P14/1NT/POll
62
P13/INTP2IINTAK
61
P12/1NTPl
----
60
Pl1 IINTPO
0 14
59
NMI
0 15
58
P27/HlORQ
Ao
A9 /A l
57
P26/HLDAK
56
P25ITCl
A1O /A 2
55
P24/0MAAKl
A11 /A 3
54
P23/0MARQl
Pin
Symbol
Connect to
3
V
9
V25N35
VOO
low level (l)
49
PROG
High level (H)
53,75
IC
High level through pullup resistor
83YL-6796B
3
NEe
pPD70P322
84-Pin Lee, EPROM Programming Mode
74
73
72
71
70
69
68
67
D7
66
Ao
65
A1
64
A2
~
~
~
A4
~
~
00
~
~
~
~
~
~
Open
56
A10
55
A11
54
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
c:
~
a
Pin
Symbol
Connect to
9
V
49
PROG
VDD
Low level through pullup resistor
Low level through pullup resistor
High level through pullup resistor
Do not connect to these pins.
L
H
Open
83YL~795B
4
NEe
pPD70P322
Pin Identification, V25N35 Mode
Symbol
I/O
Function
Also Used For
Port Pins
POo-P06
I/O
PO]
(P1o) NMI
P11
In
In
Input or output mode can be
specified per bit
CLKOUT
Non-maskable interrupt;
cannot be used as a generalpurpose port pin.
Port 1 input lines
Symbol
I/O
Function
Also Used For
INTAK
Out
Interrupt acknowledge
P13iINTP2
INTPO
In
External interrupt request
P1 1
INTP1
P1 2
INTP2
P13iINTAK
IOST8
Out
I/O access strobe
MREQ
Out
Indicates memory bus cycle
start
INTPO
P12
INTP1
MST8
Out
Memory access strobe
P13
INTP2
POLL
In
Wait insertion
P14J'INT
POLL/INT
READY
In
External ready
P17
TOUT
REFRQ
Out
DRAM refresh pulse
P14
I/O
P1s
Input or output mode can be
specified per bit.
P16
SCi<'--______________
A_dd_re_s_s_ln_pu_t_ _ _ _ _ _ _ _ _ _ _ _ _
---<,-__ _...IH
D_a_ta_l_np_u_t
Data output
~~,-_ _ _D_a_ta_in_p_ut_ _- , ) ' - - - - -
+12.5V ~
VDD
RESET
~L
-
PROG
_________________
~'~
~'-_________________________~I~
.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
)5
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
55
83YL-6793B
8
NEe
pPD70P322
System Clock
Figure 3. EPROM Read Timing
A
A13- O
=x____
X'-____
TA = -10 to + 70°C; Voo = + 5.0 V ±10% at 5 MHz, ±5% at 8 MHz
Vss = OV;VTH = OtoV oo + 1
A_dd_r_es_s_in_p_u_t _ _- J
p.PD70P322
p.PD70P322-8
Min
Max
Min
Max
Unit
4
10
4
16
MHz
Frequency, fx
4
10
4
16
MHz
Rise/fall time, tRltF
0
10
0
10
ns
Xl input, high/low
35
250
20
250
ns
Parameter
Internal Oscillator
Frequency, fxx
External Clock
OE
\'--------J/
level width, tOH/tOL
0TOO - - - - - - - - ( ' -__
o_at_a_ou_t_pu_t_..I))----
System Clock Control Circuit
83YL-S79OA
Internal Oscillator
INSTALLATION
Di rect solderi ng to pi ns of the J-lPD70P322 is not allowed.
The device must be installed in a socket.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
TA = 25°C
Notes:
Supply voltage, Voo
-0.5 to + 7.0 V
Input voltage, VI
-0.5 to VOO+ 0.5 :5 + 7.0 V
Output voltage, Vo
-0.5 to VOO+ 0.5 :5 + 7.0 V
Threshold voltage, VT H
-0.5 to V 00+ 0.5 :5 + 7.0 V
Output current low, IOL
Each output pin 4.0 rnA (total 50 rnA)
Output current high, IOH
(1)
Mount the capacitors and crystal or ceramic
resonator as close to pins X1 and X2 as possible.
(2)
00 not route other signal lines through the shaded
area.
External Clock
Each output pin -2.0 rnA (total-20 rnA)
Operating temperature range, TOPT
-40 to + 85°C
Storage temperature range, TSTG
-65 to + 150°C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
Clock
74HC04
t
'-------I
X1
X2
83SL·7000A
Capacitance
TA = 25°C; Voo = 0 V
Parameter
Symbol
Input capacitance
CI
Output capacitance
I/O capacitance
Max
Unit
10
pF
Co
20
pF
CIO
20
pF
Conditions
fc = 1 MHz;
unmeasured pins
returned to ground
9
NEe
pPD70P322
Recommended Oscillator Components
Ceramic Resonator (Note 1)
Manufacturer
Crystal (Note 2)
Capacitors
Product No.
C1 (pF)
Capacitors
Manufacturer
C2 (pF)
Product No.
Kinseki
C1 (pF)
C2 (pF)
HC-49/U
15
15
HC-43/U
15
15
Kyocera
KBR-10.0M
Murata Mfg.
CSA.10.0MT
47
47
CSA16.0MX040
30
30
Notes:
FCR10.M2S
30
30
FCR16.0M2S
15
6
(1) Ceramic resonator product no. includes the frequency: 10.0 or
16.0 MHz.
TDK
33
33
(2) Crystal frequencies: 10, 16 MHz.
DC Characteristics 1; V25N35 Mode
TA = -10 to +70°C; voo = +5.0 V ±10 %
Parameter
Symbol
Input voltage, low
VIL
Input voltage, high
Conditions
Max
Unit
0
0.8
V
VIH1
2.2
Voo
V
VIH2
0.8 Voo
Voo
V
RESET, P101NMI, X1, X2
0.45
V
IOL = 1.6 mA
V
IOH = -0.4 mA
p.A
EA,.P101NMI; VIN = 0 to Voo
p.A
All except EA, P101NMI; VIN = 0 to Voo
Output voltage, low
VOL
Output voltage, high
VOH
Min
Typ
Voo -1.0
All except RESET, P101NMI, X1, X2
liN
±20
Input leakage current
III
±10
Output leakage current
ILO
±10
p.A
Vo = 0 to Voo
VTH = Oto Voo
Operation mode
Input current
VTH supply current
ITH
0.5
1.0
mA
Voo supply current, p.PD70P322
1001
50
100
mA
1002
20
40
mA
HALT mode
1003
10
30
p.A
STOP mode
1001
65
120
mA
Operation mode
1002
25
50
mA
HALT mode
1003
10
30
p.A
STOP mode
Voo supply current, p.PD70P322-8
DC Characteristics 2; EPROM Program Operation
TA = 25 ±5°C; Voo = 6.0 ±0.25 V; Vpp = 12.5 ±0.3 V
Parameter
Symbol
Min
Max
Unit
Input voltage, high
VIH
2.2
Voo + 0.3
V
Input voltage, low
VIL
-0.3
0.8
V
Input leakage current
III
10
p.A
VIH = 0 to Voo
Output voltage, high
VOH
V
IOH = -400 p.A
Output voltage, low
VOL
V
IOL = 1.6 mA
Voo supply current
Vpp supply current
10
Typ
Voo-1
0.45
100
40
mA
Ipp
30
mA
Conditions
NEe
pPD70P322
DC Characteristics 3; EPROM Read Operation
TA =25 ±5°C
Parameter
Symbol
Min
Typ
Max
Unit
Power supply voltage
VOO
4.5
5.0
5.5
V
V
Write power supply voltage
Vpp
Input voltage, high
VIH
2.2
Input voltage, low
VIL
-0.3
Input leakage current
III
Output voltage, high
VOH
Output voltage, low
VOL
Output leakage current
Conditions
+ 0.3
VOO
Vpp = VOO
V
0.8
V
10
p.A
Voo-1
0.45
VIN = 0 to VOO
V
IOH = -400 p.A
V
IOL =1.6 mA
ILO
10
p.A
VOO supply current
100
40
mA
Vpp supply current
Ipp
100
p.A
Vpp = Voo
AC Characteristics 1; V25N35 Mode
TA = -10 to + 70°C; fCLK = 0.5 to 5 MHz with Voo = 5 V ± 10%; fCLK = 5 to 8 MHz with Voo = 5 V ±5%
70P322
70P322-8
~
Parameter
Symbol
Max
Unit
Input rise, fall times
tlR, tlF
20
20
ns
Except X1, X2, RESET, NMI
Input rise, fall times (Schmitt)
tIRS, tlFS
30
30
ns
RESET, NMI
Output rise, fall times
tOR, tOF
20
20
ns
Except CLKOUT
X1 cycle time
tcyx
98
250
ns
X1 width, low
tWXL
35
20
X1 width, high
tWXH
35
20
X1 rise, fall times
tXR, tXF
Min
Min
Max
250
62
Conditions
ns
ns
20
ns
2000
20
CLKOUT cycle time
tCYK
200
ns
CLKOUT = fx/2
CLKOUT width, low
tWKL
0.5T - 15
0.5T - 15
ns
T
CLKOUT width, high
tWKH
0.5T-15
0.5T -15
ns
CLKOUT rise, fall times
tKR, tKF
2000
125
15
15
= tcYK
ns
AC Characteristics 2; V25 Mode
TA = -10 to +70°C; CL = 100 pF (max); T == tcYK; n = number of wait states inserted
fCLK = 0.5 to 5 MHz with Voo = 5 V ±10%; fCLK = 5 to 8 MHz with Voo = 5 V ±5%
Parameter
Symbol
Address delay time
tOKA
Address valid to input data valid
MREQ to data delay time
Max
Unit
90
ns
tOAOR
(n+1.5)T - 90
ns
tOMRO
(n +1)T -75
ns
MSTB to data delay time
tOMS O
(n +0.5)T - 75
ns
0.5T + 50
ns
MREQ to TC delay time
tOMRTC
MREQ to ~ delay time
tOMRMS
MREQ width, low
tWMRL
Address hold time
Input data hold time
Next control setup time
TC width, low
Min
0.5T - 35
0.5T + 35
Conditions
ns
(n+1)T - 30
ns
tHMA
0.5T - 30
ns
tHMoR
0
ns
tscc
T -25
ns
tWTCL
2T -30
ns
11
Iii:I
NEe
JlPD70P322
AC Characteristics 2; V25 Mode (cont)
Parameter
Symbol
Address data output
tOAOW
MREQ delay time
tOAMR
0.5T -30
MSTB delay time
tOAMS
T -30
ns
MSTB width, low
tWMSL
(n+0.5)T 30
ns
Data output setup time
tSOM
(n+1)T - 50
ns
Data output hold time
tHMoW
0.5T - 30
ns
IOSTB delay time
tOAIS
0.5T - 30
iOSfB to data input
iOSfB width, low
tOISO
tWISL
(n+1)T - 30
ns
Address hold time
tHISA
0.5T - 30
ns
tHISOR
0
ns
Data input hold time
Output data setup time
tSDlS
Output data hold time
tHISOW
Next OMARa setup time
tSOAOQ
Unit
ns
Conditions
ns
ns
(n+1)T - 90
ns
(n+1)T - 50
ns
0.5T -30
ns
ns
Demand mode
tHOAOQ
ns
Demand mode
tWOMRL
(n+1.5)T 30
ns
DMMK read width, low
fC
tOOATC
delay time
Max
0.5T + 50
0
OMARa hold time
DMMK to
Min
T
0.5T + 50
ns
(n+1)T - 30
ns
tOARF
0.5T -30
ns
tWRFL
(n+1)T - 30
ns
Address hold time
tHRFA
0.5T - 30
ns
RESET width, low
tWRSL1
30
ms
STOP mode release/Power-on reset
RESET width, low
tWRSL2
5
~s
System reset
MREQ, IOSTB to READY setup time
tSCRY
MREQ, IOSTB to READY hold time
tHCRY
H LDAK output delay time
tOKHA
BUS control float to HLDAK.j.
tCFHA
T -50
ns
HLDAK ito control output time
tOHAC
T-50
ns
HLDRa .j. to control output time
tOHQC
3T + 30
ns
H LDAK width, low
tWHAL
T
ns
H LDRa setup time
tSHQK
30
DMMK write width, low
tWOMWL
REFRQ delay time
RE F RQ width, low
HLDRa to HLDAK delay time
H LORa width, low
INTP, OMARa setup time
(n -1)T -100
(n-1)T
n
~
2
ns
n
~
2
ns
80
ns
3T
tOHQHA
ns
+
160
ns
tWHQL
1.5T
ns
tSIQK
30
ns
INTP, DMARa width, high
tWIQH
8T
ns
INTP, DMARa width, low
tWIQL
8T
ns
POLL setup time
tSPLK
30
ns
NMI width, high
tWNIH
5
~s
NMI width, low
tWNIL
5
~s
Q'S width, low
tWCTL
2T
ns
12
NEe
pPD70P322
AC Characteristics 2; V25 Mode (cont)
Parameter
Symbol
Min
I NT setup time
tSIRK
30
ns
ns
INT hold time
tHIAIQ
0
INTAK width, low
tWIAL
2T -30
INTAK delay time
tOKIA
INTAK width, high
tWIAH
Max
Unit
ns
80
T -30
ns
ns
INTAK to data delay time
tOIAO
INTAK to data hold time
tHIAO
0
SCKO cycle time
tCYTK
1000
ns
SCKO (TSCI<) width, high
tWSTH
450
ns
SCKO (TSCI<) width, low
tWSTL
450
2T -130
ns
0.5T
ns
ns
TxD delay time
tOTKD
TxD hold time
tHTKD
20
ns
ns
CTSO (RSCI<) cycle time
Conditions
210
ns
tCYRK
1000
CTSO (RSCI<) width, high
tWSRH
420
ns
CTSO (RSCI<) width, low
tWSRL
420
ns
RxD setup time
tSROK
80
ns
RxD hold time
tHKRO
80
ns
II
AC Characteristics 3; V35 Mode
TA = -10 to +70°C; CL = 100 pF (max); T = tcYK; n = number of wait states inserted
fCLK = 0.5 to 5 MHz with Voo = 5 V ±10%; fCLK = 5 to 8 MHz with Voo = 5 V ±5%
Parameter
Symbol
Address delay time
tOKA
Address valid to input data
valid
MREQ to data delay time
Min
Max
Unit
90
ns
tOAOR
(n+1.5)T - 90
ns
tOMRO
(n+2)T -75
ns
MSTB to data delay time
tOMSO
(n+1)T -75
ns
MREQ to TC delay time
tOMRTC
0.5T + 50
ns
MREQ to MSTB delay time
Conditions
tOMRMS1
T-35
T + 35
ns
Read operation
tOMRMS2
(n + 1)T - 35
(n + 1)T + 35
ns
Write operation
tOMRMS
0.5 T - 30
ns
MREQ width, low
tWMRL
(n+2)T -30
ns
Address hold time
tHMA
0.5T - 30
ns
Input data hold time
tHMOR
0
ns
ns
Next control setup time
tscc
T-25
Te width, low
tWTCL
2T-30
Address data output
tOAOW
MREQ delay time
tOAMR
0.5T -30
R/W to MSTB delay time
tORMS
0.5T - 30
ns
tOWMS
(n + 0.5)T - 30
ns
tWMSL1
(n + 1)T - 30
ns
Read operation
tWMSL2
T-30
ns
Write operation
MSTB width, low
ns
0.5T + 50
ns
ns
13
NEe
pPD70P322
AC Characteristics 3; V35 Mode (cant)
Parameter
Symbol
Data output setup time
tsoM
Data output hold time
Min
Max
(n+2)T - 50
Unit
tHMOW
0.5T - 50
ns
IOSTB delay time
tOMRIS
T -35
ns
iOS'i'B to data input
iOS'i'B width, low
tOISO
tWISL
(n+1)T - 30
ns
Address hold time
tHISA
0.5T - 30
ns
Data input hold time
tHISOR
0
ns
Output data setup time
tSOIS
(n+2)T -50
ns
Output data hold time
tHISOR
Next DMARQ setup time
tSOAOQ
DMARQ hold time
tHoAOQ
0
DMAAK read width, low
tWOMRL
(n+1.5)T - 30
DMAAK to
fC delay time
(n + 1) T -90
ns
ns
0
T
ns
Demand mode
ns
Demand mode
ns
0.5T + 50
tOOATC
Conditions
ns
ns
DMAAK write width, low
tWOMWL
(n+2)T -30
ns
RE F RQ delay time
tOARF
0.5T - 30
ns
REFRQ width, low
tWRFL
(n+1)T -30
ns
Address hold time
tHRFA
0.5T - 30
ns
RESET width, low
tWRSL1
30
ms
STOP mode release/Power-on reset
RESET width, low
tWRSL2
5
/Ls
System reset
ns
n
~
2
ns
n
~
2
MREQ, IOSTS to READY setup
time
tSCRY
MREQ, IOSTS to READY hold
time
tHCRY
HLDAK output delay time
tOKHA
BUS control float to H LDAK ~
HLDAK ito control output time
nT -100
nT
80
ns
tCFHA
T -50
ns
ns
tOHAC
T -50
HLDRQ J. to control output time
tOHQC
3T + 30
ns
H LDAK width, low
tWHAL
T
ns
H LDRQ setup time
tSHQK
30
HLDRQ to HLDAK delay time
tOHQHA
H LDRa width, low
tWHQL
1.5T
ns
INTP, DMARa setup time
tSTQK
30
ns
INTP, DMARa width, high
tWIQH
8T
ns
INTP, DMARQ width, low
tWIQL
8T
ns
POLL setup time
tSPLK
30
ns
NMI width, high
tWNIH
5
/Ls
NMI width, low
tWNIL
5
/Ls
C'fS width,
tWCTL
2T
ns
INT setup time
tSIRK
30
ns
INT hold time
tHAIQ
0
ns
tWIAL
2T- 30
low
INTAK width, low
INTAK delay time
14
tOKlA
ns
3T + 160
ns
ns
80
ns
NEe
pPD70P322
AC Characteristics 3; V35 Mode (cont)
Parameter
Symbol
INTAK width, high
tWIAH
INTAK to data delay time
tOIAO
INTAK to data hold time
tHIAO
0
SCKO cycle time
tCYTX
1000
ns
SCKO (TSCI<) width, high
tWSTH
450
ns
SCKO (TSCI<) width, low
tWSTL
450
TxD delay time
tOTKD
TxD hold time
tHTKD
20
CTSO (RSCI<) cycle time
tCYRK
1000
ns
CTSO (RSCI<) width, high
tWSRH
420
ns
CTSO (RSCI<) width, low
tWSRL
420
ns
tSROK
SO
ns
tHKRO
SO
ns
RxD setup time
RxD hold time
Min
Max
T -30
Unit
Conditions
ns
2T - 130
ns
0.5T
ns
ns
210
ns
ns
AC Characteristics 4; EPROM Program Operation
= 25 ±5°C, VOO = 6.0 ±0.25 V; Vpp = 12.5 ±0.3 V
1m
TA
Parameter
Symbol
Min
Typ
Max
Unit
Address setup time to CE .J.
tAS
2
OE setup time
tOES
2
P.s
Data input setup time to CE .J.
tos
2
P.s
Address retention time
tAH
2
p.s
Data input retention time
tOH
2
p.s
OE to data output float delay
tOF
0
p.s
Vpp setup time to CE .J.
tvps
2
p.s
VOO setup time to CE .J.
tvos
2
Initial program pulse width
tpw
0.95
Additional program pulse width
topw
2.S5
OE to data output delay time
tOE
Condition
P.s
p.s
1.0
1.05
ms
7S.75
ms
2
p.s
Max
Unit
IJs
CE = OE "" V1L
IJs
OE "" VIL
IJs
= V1L
= V1L
CE = "DE = V1L
AC Characteristics 5; EPROM Read Operation
= 25 ±5°C, VOO = 5.0 ±0.5 V; Vpp"" VOO
TA
Parameter
Symbol
Min
Typ
Address to data output delay time
tACC
2
CE to data output delay time
icE
2
OE to data output delay time
tOE
OE to data output float delay
tOF
0
IJs
Address to output retention
tOH
0
IJs
Condition
CE
CE
15
NEe
pPD70P322
Figure 4.
EPROM Program Operation Timing
+ 12.SV
Vpp
VDD
+6V
VOD
VDD
CE
V1H
VIL
tOES
r.-
V1H
-------------,1
OE
83VL·6791 B
Figure 5.
Comparator Characteristics
EPROM Read Operation Timing
TA = -10 to 70°C; fCLK = 0.5 to 5 MHz with V DD
fCLK = 5 to 8 MHz with Voo = 5 V ±5%
Address input
Parameter
=5V
±10%;
Max
Unit
±100
mV
VDD +0.1
V
tCOMP
64
65
tCYK
VIPT
0
VDD
V
Symbol
Min
Accuracy
VACOMP
Threshold voltage
VTH
0
Comparison time
PT input voltage
Data Memory STOP Mode; Low Supply Voltage
Data Retention
*OE
TA = -10 to +70°C
o-,-DO
---.:!!-~--
Data output
Hi-Z
* To read within the range of tACC. set the delay
of OE from
CE fall to tACC -
tOE(Max).
83VL·6792A
16
Parameter
Symbol
Min
Max
Data retention supply voltage
VDDDR
2.5
5.5
V DD rise, fall time
tR\fD' tFVD
200
Unit
V
p.s
NEe
NEG Electronics Inc.
pPD70325 (V25 Plus)
16-Bit Microcomputer:
High-Speed DMA, Single-Chip, CMOS
Description
o Internal 256-byte RAM memory
The jiPD70325 0125 Plus) is a high-performance, 16-bit,
single-chip microcomputer with an 8-bit external data
bus. The jiPD70325 is fully software compatible with
the pPD70108/116 ry2Q®/30®) as well as the jiPD70320/
330 ry25™ /35™). The V25 Plus microcomputer demonstrates numerous enhancements over the standard
V25; however, it maintains strict pin compatibility with
its predecessor, the V25.
o 1-megabyte memory address space
o Two independent full-duplex serial channels
The V25 Plus offers improved DMA transfer rates to 5
megabytes/second, additional serial channel status
flags, improved memory access timing, and enhanced
software control of register bank context switching.
o Priority interrupt controller
- Standard vectored service
- Register bank switching
- Macroservice
The jiPD70325 has the same complement of internal
peripherals as the V25 and maintains compatibility
with existing drivers; however, some modification Of
DMA device drivers may be necessary. The jiPD70325
does not offer on-chip ROM or EPROM.
Features
o 16-bit CPU and internal data paths
o Functional and pin compatibility with V25
o Eight internal memory-mapped register banks
o Four multifunction I/O ports
- 8-bit analog comparator port
- 20 bidirectional port lines
- Four input-only port lines
o Pseudo SRAM and DRAM refresh controller
o Two 16-bit timers
o On-chip time base counter
o Programmable wait state generator
o Two standby modes: STOP and HALT
Ordering Information
Part Number
Clock (MHz)
Package
JlPD70325L-S
S
S4-pin PLCC
o Software compatible with jiPD8086
L-10
10
o New and enhanced V-Series instructions
GJ-S
S
o 6-byte prefetch queue
GJ-10
10
o Two-channel high-speed DMA controller
o Minimum instruction cycle
-250 ns at 8 MHz
- 200 ns at 10 MHz
V20 and V30 are registered trademarks of NEC Corporation.
V25 and V35 are trademarks of NEC Corporation.
50134-2
94-pin plastic QFP
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IIPD703'26 (V25 Pills)
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•
i"
Pin Configurations
84-PlnPLCC
P07/CLKOUT
74
PT7
DO
73
PT6
01
72
PTS
02
71
PT4
03
70
PT3
04
69
PT2
05
68
PTt
06
67
PTO
07
66
P17/REAOY
Ao
65
P16/SCKO
At
64
P1SITOU~
A2
63
P14/INT/PO~
A3
62
P13/INTP2IINTAK
A4
61
P12/1NTP1
A5
60
P11/1NTPO
A6
59
P10/NMI
A7
58
P27/HLORQ
A8
57
P26/HLDAK
A9
56
P25~
A10
55
P24/0MAAK1
54
P23/0MARQ1
A11
I"'-
v
~~~~~~~~8
c(c(c(c(c(c(c(c(tt.
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Z
(!l
()
0
~ Eilen
x f-
f-
a: ()
co
v
~ 8
a:
f-
~
e
Cl
v
o
~
N
C')
on on on on
TIc
Q o
Q
~ ()
> ~ ~
e~
0
N
a.
N
a.
Notes:
(1) Pin functions are identical to IlP070320.
(2) All IC pins should be tied together and pulled up to V DO with a
10- to 20-k.Cl resistor.
(3)
EA must be tied low because IlP070325 does not support Internal
ROM or EPROM.
83SL-G689B
2
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,.,PD70325 (V25 Plus)
94-Pln PI••tlc QFP
A12
NC
A13
A14
A15
A16
A17
A18
A19
RxDO
GND
CTSO
TxDO
RxD1
CTS1
TxD1
P20/DMARQO
IC
VDD
VDD
P21/DMAAKO
NC
P22ITCO
71
POs
70
NC
69
IC
68
P04
67
P03
66
P02
65
P01
64
POo
63
EA
62
MREQ
61
IOSTB
60
MSTB
59
RIW
58
REFRQ
57
RESET
56
55
VDD
VDD
54
X2
53
X1
52
GND
51
GND
50
NC
49
~ ~ ~ ~
re
~ g
M~
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~48
NC
VrH
Notes:
(1) Pin functions are Identical to J.l.PD70320.
(2) All IC pins should be tied together and pulled up to V DD with a
10- to 20-kn resistor.
(3) EA must be tied low because J.l.PD70325 does not support internal
ROM or EPROM.
83SL-e690B
3
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pPD70325 (V25 Plus)
Pin 'Identification
Symbol
Function
Address bus outputs
CLKOUT
System clock output
PIN FUNCTIONS
Ao-A19 (Address Bus)
Ao-A19 is the nonmultiplexed 20-bit address bus used to
access all external devices.
Clear to send channel 0 input
CTS1
Clear to send channel 1 input
CLKOUT (System Clock)
Bidirectional data bus
This is the internal system clock. It can be used to
synchronize external devices to the CPU.
External access
I/O strobe output
MREQ
Memory request output
MSTB
Memory strobe output
I/O portO
P101NMI
Port 1 input line; nonmaskable interrupt
P11-P12/INTPOINTP1
Port 1 input lines; external interrupt input lines
P131'INTP2/
INTAK
Port 1 input line; external interrupt input line;
interrupt acknowledge output
P141'1 N17POLL
I/O port 1; interrupt request input; I/O poll input
P1:/TOUT
I/O port 1; timer out
P1e1SCKO
I/O port 1; serial clock output
I/O port 2; DMA request 0
I/O port 2; DMA acknowledge 0
I/O port 2; DMA terminal count 0
P231'DMARQ1
I/O port 2; DMA request 1
I/O port 2; DMA acknowledge 1
I/O port 2; DMA terminal count 1
P2e1HLDAK
The two serial ports (channels 0 and 1) use these lines
for transmitting and receiving data, handshaking, and
serial clock output.
00-07 (Data Bus)
I/O port 1; ready input
P20/DMARQO
CTSn, RxDn, TxDn, SCKO (Clear to Send,
Receive Data, Transmit Data, Serial Clock Out)
I/O port 2; hold acknowledge output
Do-D7 is the 8-bit external data bus.
DMARQn, DMAAKn, TCn (DMA Request, DMA
Acknowledge, Terminal Count)
These are the control signals to and from the on-chip
DMA controller.
EA(External Access)
If this pin is low on reset, the J.1PD70322 0/25) will
execute program code from external memory instead
of internal ROM.
Because the V25 Plus does not support internal ROM,
the EA pin must be fixed low in hardware.
I/O port 2; hold request input
PTO-PT7
Comparator port input lines
Refresh pulse output
RESET
Reset input
RxDO
Serial receive data channel 0 input
RxD1
Serial receive data channel 1 input
R/W
Read/Write output
TxDO
Serial transmit data, channel 0 input
TxD1
Serial transmit data, channel 1 input
X1,X2
Crystal connection terminals
VDD
Positive power supply voltage
Threshold voltage input
GND
Ground reference
IC
Internal connection
H LDAK (Hold Acknowledge)
The HLDAK output (active low) informs external devices that the CPU has released the system bus.
H LDRQ (Hold Request)
The HLDRQ input (active high) is used by external
devices to request the CPU to release the system bus to
an external bus master. The following lines go into a
high-impedance status: Ao-A19, Do-D7, MREQ, RiW,
MSTB, REFRQ, and IOSTB.
INT (Interrupt Request)
INT is a maskable, active-high, vectored interrupt request. After assertion, external hardware must provide
the interrupt vector number.
The INT pin allows direct connection of slave J.1PD71059
interrupt controllers.
4
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INTAK (Interrupt Acknowledge)
After INT is asserted, the CPU will respond with INTAK
(active low) to inform external devices that the interrupt
request has been granted.
pPD70325 (V25 Plus)
every five clock cycles until it is low. POLL can be used
to synchronize program execution to external conditions.
PTO ·PT7 (Comparator Port)
INTPO ·INTP2 (External Interrupt)
PTO-PT7 are inputs to the analog comparator port.
INTPO-INTP2 allow external devices to generate interrupts. Each can be programmed to be rising or falling
edge triggered.
READY (Ready)
10STB (I/O Strobe)
10STB is asserted during read and write operations to
external I/O.
MREQ (Memory Request)
MREQ (active low) informs external memory that the
current bus cycle is a memory access bus cycle.
MSTB (Memory Strobe)
MSTB (active low) is asserted during read and write
operations to external memory.
NMI (Nonmaskable Interrupt)
NM I cannot be masked through software and is typically
used for emergency processing. Upon execution, the
interrupt starting address is obtained from interrupt
vector number 2. NMI can release the standby modes
and can be programmed to be either rising or falling
edge triggered.
After READY is de-asserted low, the CPU synchronizes
and inserts at least two wait states into a read or write
cycle to memory or I/O. This allows the processor to
accommodate devices whose access times are longer
than nominal p.PD70325 bus cycles.
REFRQ (RefreSh)
This active-low output pulsecan refresh nonstatic RAM.
It can be programmed to meet system specifications an
is internally synchronized so that refresh cycles do not
interfere with normal CPU operation.
RESET (Reset)
A low on RESET resets the CPU and all on-chip periPh-1!!I
erals. RESET can also release the standby modes. After
RESET returns high, program execution begins from
address FFFFOH.
R/W (Read/Write)
Rm output allows external hardware to determine if the
current operation is a read or a write cycle. It can also
control the direction of bidirectional buffers.
POO·P07 (Port 0)
POo-P07 are the lines of port 0, an 8-bit bidirectional
parallel I/O port.
P10·P17 (Port 1)
The status of P1o-P13 can be read but these lines are
always control functions. P14-P17 are the remaining lines
of parallel port 1; each line is individually programmable
as either an input, an output, or a control function.
P20·P27 (Port 2)
P2o-P27 are the lines of port 2, an 8-bit bidirectional
parallel I/O port. The lines can also be used as control
signals for the on-chip DMA controller.
TOUT (Timer Out)
TOUT is the square-wave output signal from the internal
timer.
X1, X2 (Crystal Connections)
The internal clock generator requires an external crystal
across these terminals. By programming the PRC register, the system clock frequency can be selected as the
oscillator frequency (fosd divided by 2, 4, or 8.
Voo (Power Supply)
Two positive power supply pins (VDD) reduce internal
noise.
POLL (Poll)
Upon execution of the POLL instruction, the CPU checks
the status of this pin and, if low, program execution
continues. If high, the CPU checks the level of the line
5
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pPD70325 (V25 Plus)
VTH (Threshold Voltage)
GND (Ground)
The comparator port uses this pin to determine the
analog reference point. The actual threshold to each
comparator line is programmable to VTH x n/16 where n
=1 to 16.
.
Two ground connections reduce internal noise.
IC (Internal Connection)
Allie pins should be tied together and pulled up to Voo
with a 10- to 20-kO resistor.
"PD70325 Block Diagram
...............
It>
-+-::
1
P2 I~;:~~~ =lprOg~::ableil
'"
Ao-A19
P20/DMARQO
P2 3 IDMARQ1 -j~
P2 4 /DMAAK1 - : :
LRESIT
Controller
-1.. . . . . . . . . . . . . . . . . . . .
:;.- HLDAK/P2 6
P2 s rrC1 ..
}-~. HLDROIP2 7
~.~
~:~~ : :..··············::·;::;·················11
P1 /SCKO ~~
6
:. b' .:~
:: [ ; -
Interface
CTSO~:
TxD1
~:
- General
Registers
-Macro
Service
Channel
r------,
~;~~ =:1. . . . . . . . . . . . . ..
P1 0 /NMI
P13/INTP2I
M~B
Ili~ :TB
~ POLUINT/P14
(Reserved)
Instruction Decoder
P11/1NTPO
P12/1NTP1
Internal ROM
8K Bytes
READY/P1 7
MREQ
Micro Sequencer
Programmable
Interrupt
Controller
i;"'" EA
Micro ROM
INTAK
;=.............}
P1 4 /1NTI
POLL
X1
X2
TOUT/P15
REFRQ
P07/CLKOUT
PO
P1
P2
PTO-PT7
V TH
VDD
GND
Notes:
(1) The I1PD70325 (V25 Plus) is not a masked ROM product.
Internal ROM Is reserved and not accessible.
(2) Shaded blocks are functionally different on V25 Plus and V25.
83YL·5731B
6
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pPD70325 (V25 Plus)
FUNCTIONAL DESCRIPTION
Register Set
The following features enable the p.PD70325 to perform
high-speed execution of instructions.
Figure 1 shows the eight banks of internal registers,
which the p.PD70325 has functionally mapped into internal RAM. Each bank contains general-purpose registers,
pointer and index registers, segment registers, and save
areas for context switching.
•
•
•
•
Dual internal data bus
16- and 32-bit temporary registers/shifters
16-bit loop counter
Program counter and prefetch pointer
Dual Data Bus
The p.PD70325 has two internal 16-bit data buses: the
main data bus and the secondary data bus. This reduces
the processing time required for addition/subtraction
and logical comparison instructions by one third over
single-bus systems. The dual data bus method allows
two operands to be fetched simultaneously from the
general-purpose registers and transferred to the AlU.
16- and 32-Bit Temporary Registers/Shifters
The 16-bit temporary registers/shifters (TA and TB) allow
high-speed execution of multiplication/division and
shift/rotate instructions. Using the temporary registers,
the p.PD70325 can execute multiplication/division instructions about four times faster than with the microprogrammed method.
Loop Counter (LC)
The dedicated hardware loop counter (lC) counts the '
number of iterations for string operations and the number of shifts performed for multiple-bit shift/rotate instructions. The loop counter works with internal dedicated shifters to speed the processing of multiplication/
division instructions.
Program Counter and Prefetch Pointer
(PC and PFP) ,
The hardware PC addresses the memory location of the
instruction to be executed next. The hardware PFP
addresses the program memory location to be accessed
by the instruction queued next. Several clock cycles are
saved for branch, call, return, and break instructions.
Although these memory locations may be accessed as
normal RAM with the full set of memory addressing
modes provided by the V25 family, the capability of
context switching provides superior speed in register
access. When used in the internal memory disabled
state, many instructions execute considerably faster.
Eight macroservice channel control blocks are also
mapped into register banks 0 and 1. The V25 Plus does
not map the DMA channel control blocks into the internal RAM like the V25; instead, these control blocks are
mapped into the special function register area.
General-Purpose Registers (AW, BW, Cw, OW). Four
16-bit general-purpose registers (AW, BW, Cw, and DW)
can serve as 16-bit registers or as four sets of dual a-bit
registers (AH, Al, BH, Bl, CH, Cl, DH, and Dl). The
instruction classes default to the following generalpurpose registers.
AW Word multiplication/division, word I/O, data
conversion.
Al
Byte multiplication/division, byte I/O, BCD
rotation, data conversion, translation.
AH
Byte multiplication/division.
BW Translation
CW loop control, branch, and repeat prefixes.
Cl
Shift 'instructions, rotate instructions, BCD
operations.
DW Word multiplication/division, indirect
addressing.
I/O
Pointers (SP, BP) and Index Registers (IX, IY). These
registers are 16-bit base pOinters (SP, BP) or index
registers (IX, IY) in based addressing, indexed addressing, and based indexed addressing. They are used as
default registers under the following conditions.
SP
Stack operations
IX
Block transfer (source), BCD string operations
IY
Block transfer (destination), BCD string
operations
7
II'1I'I
Iii:I
NEe
JlPD70325 (V25 Plus)
Figure 1. Internal RAM Mapping
32-Byte
Register Bank
15
+1FH
AW
CW
ow
BW
SP
Eight 32-Byte
Register Banks
BP
IX
15
IV
xxEFFH
xxEEOH
Register Bank
7
xxECOH
6
xxEAOH
5
OS1
PS
SS
OSO
PC Storage
xxE80H
4
xxE60H
3
xxE40H
2
xxE20H
1
xxEOOH
0
PSW Storage
Vector PC
+OOH
]
Reserved
Eight a-Byte
Macroservice Channels
Macroservlce t;nannel
xxE3FH
0
7
xxE38H 15
xxE30H
6
xxE28H
5
s.{
a-Byte
Macroservice Channel
15
+7H
4
xxE18H
3
xxE10H
2
xxE08H
1
xxEOOH
0
0
MSP
Reservedi SCHR
+OH
xxE20H
87
MSS
SFRP
I
MSC
83SL-6691B
Segment Registers. The segment registers divide the
1M-byte address space into 64K-byte blocks. Each segment register functions as a base address to a block; the
effective address is an offset from that base. Physical
addresses are generated by shifting the associated segment register left by four binary digits and then adding
the offset address. The segment registers and default
offsets are listed below.
8
Segment Register
PS (Program Segment)
Default Offset
PC (Program Counter)
SS (Stack Segment)
SP and Effective Address
DSO (Data Segment 0)
IX and Effective Address
DS1 (Data Segment 1)
IV and Effective Address
Save Registers (Save PC and Save PSW). Save PC and
save PSW are used as the storage areas during register
bank context-switching operations. The Vector PC save
location contains the effective address of the interrupt
service routine when register bank switching is used to
service interrupts.
Program Counter (PC). The PC is a 16-bit binary
counter that contains the offset address from the program segment of the next instruction to be executed. It
is incremented every time an instruction is received from
the queue. It is loaded with a new location whenever the
branch, call, return, break, or interrupt is executed.
NEe
pPD70325 (V25 Plus)
Program Status Word (PSW). The PSW contains status
and control flags used by the CPU and two generalpurpose user flags. The configuration of this 16-bit register is shown below.
15
8
RB2
RB1
RBO
V
F1
AC
FO
I
DIR
IE
BRK
P
I BRKI I
CY
0
7
S
z
I
Status Flags
V
Overflow bit
S
Sign
Z
Zero
AC Auxiliary carry
P
Parity
CY Carry
In large-scale systems where internal RAM is not required for data memory, internal RAM can be removed
completely from the address space and dedicated entirely to register banks· and control functions such as
macroservice.You do this by clearing the RAMEN bit in
the processor control register. When the RAMEN bit is
cleared, internal RAM can only be accessed by register
addressing or internal control processes. Many instructions execute faster when internal RAM is disabled.
Figure 2. Memory Map
Control Flags
DIR
Direction of string
processing
Interrupt enable
IE
BRK
Break (after every
instruction)
Current register
RBn
bank flags
BRKI
I/O trap enable
FO, F 1 General-purpose
user flags
The eight low-order bits of the PSW can be stored in
register AH and restored using a MOV instruction. The
only way to alter the RBn bits with software is to execute
an RETRBI or RETI instruction.
Memory Map
The p.PD70325 has a 20-bit address bus that can directly
access 1 megabyte of memory. Figure 2 shows the
memory map. The internal data area (IDA) is a 256-byte
internal RAM area followed consecutively by a 256-byte
special function register (SFR) area.
All the data and control registers for on-Chip peripherals
and I/O are mapped into the SFR area and accessed as
RAM.
The IDA is dynamically relocatable in 4K-byte increments
by changing the value in the internal data base (lOB)
register. The value in this register is assigned as the
uppermost eight bits of the IDA address. The lOB register
is accessed from two memory locations, FFFFFH and
XXFFFH, where XX is the value in the lOB register.
FFFFFH
,,/--------/
XXFFFH
External
Area
XXFOOH
XXEFFH
XXEOOH
Vector
Table
(1K Bytes)
Special Function
Registers
[256 Bytes)
~?
Internal RAM
[256 Bytes)
.,?
OOOOOH
1M Bytes Memory Space
83YL-6771A
INSTRUCTIONS
The p.PD70325 instruction set is fully compatible with the
V20 native mode instruction set. The V25 Plus is a
superset of the p.P08086/8088 instruction set with different execution times and mnemonics.
The p.P070325 does not support the V20 8080 emulation
mode.
On reset, the internal data base register is set to FFH,
which maps the IDA into the internal ROM space. However, since internal ROM is not present on the p.PD70325,
this does not present a problem. You can select any of
the eight possible register banks, which occupy the
entire internal RAM space. Multiple register bank selection allows faster interrupt processing and facilitates
multitasking.
9
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"PD70325 (V25 Plus)
Enhanced Instructions
variable-Length Bit Field Operation Instructions
In addition' to thep.PDB086/B088 instructions, the
p.PD70325 provides the following enhanced instructions.
Bit fields are a variable-length data structure that can
range from 1 to 16 bits. The p.PD70325 supports two
separate operations on bit fields: insertion (INS) and
extraction (EXT). There are no restrictions on the position' of the bit field in memory.
Instruction
PUSH imm
PUSH R
POPR
MULimm
SHL immB
SHR immB
SHRAimmB
ROLimmB
ROR immB
ROLCimm8
RORC imm8
CHKIND
INM
OUTM
PREPARE
DISPOSE
Description .
Pushes immediate data onto stack
Pushes 8 general registers onto stack
Pops 8 g'eneral registers from stack
Executes 16-bit multiply of register or
memory contents by immediate data
Shifts/rotates register or memory by
immediate data
Checks array index against designated
boundaries
Moves a string from an I/O port to
memory
Moves a string from memory to an I/O
port
Allocates an area for a stack frame and
copies previous frame pointers
Frees the current stack frame on a
procedure exit
Unique Instructions
The p.PD70325 provides the following unique instructions.
Instruction
INS
EXT
ADD4S
SUB4S
CMP4S
ROL4
Description
Inserts bit field
Extracts bit field
Performs packed BCD string addition
Performs packed BCD string subtraction
Performs packed BCD string comparison
Rotates BCD digit left
ROR4
TEST1
SET1
CLR1
NOT1
BTCLR
REPC
REPNC
Rotates BCD digit right
Tests bit
Sets bit
Clears bit
Complements bit
Tests bit; if true, clear and branch
Repeat whi Ie carry set
Repeat while carry cleared
10
Separate segment, byte offset, and bit offset registers
are used for insertion and extraction. Following the
execution of these instructions, both the byte offset and
bit offset are left pointing to the start of the next bit field,
ready for the next operation. Bit field operation instructions are powerful and flexible and are therefore highly
effective for graphics, high-level languages, and
packing/unpacking applications.
Bit field insertion copies the bit field of specified length
from the AW register to the bit field addressed by
DS1 :IY:reg8 (8-bit general-purpose register). The bit field
length can be located in any byte register or supplied as
immediate data. Following execution, both IYand regB
are updated to point to the start of the next bit field.
Bit field extraction copies the bit field of specified length
from the bit field addressed by DSO:IX:regB to the AW
register. If the length of the bit field is less than 16 bits,
the bit field is right justified with a zero fill. The bit field
length can be located in any byte register or supplied as
immediate data. Following execution, both IX and regB
are updated to point to the start of the next bit field.
Figures 3 and 4 further illustrate bit field insertion and
bit field extraction, respectively.
Packed BCD Instructions
Packed BCD instructions process packed BCD data
either as strings (ADD4S, SUB4S, and CMP4S) or byte
format operations (ROR4 and ROL4). Packed BCD
strings may be 1 to 254 digits in length. The two BCD
rotation instructions rotate a Single BCD digit in the
lower half of the AL register using the register or
thememoryoperand.
Bit Manipulation Instructions
The p.PD70325 provides five unique bit manipulation
instructions that allow you to test, set, clear, or complement a single bit in a register or memory operand. This
increases code r~adability as well as performance over
the logical operations traditionally used to manipulate
bit data. These instructions also give you additional
control over on ..chip peripherals. .
NEe
pPD70325(V25 Plus)
Figure 3. Bit Field Insertion
Bit length
0
15
Awl
~
I
I
I
t
111/
~ ~.
VtJ
Bit offset
Byte offset (IV)
f
L~
Byte boundary
[tMem~
1
Segment base (051)
83-0001069
Figure 4. Bit Field Extraction
Bit length
Bit offset
Byte boundary
Segment base (OSO)
83-0001079
Additional Instructions
Besides the V20 instruction set, the ItPD70325 provides
the following additional instructions.
Instruction
Description
BTClR
Sfr.imm3,
short-label
STOP
(no operand)
RETRBI
(no operand)
Bit test and if true, clear and
branch; otherwise, no operation
Power-down instruction; stops
oscillator
Return from register bank context
switch interrupt
FINT
(no operand)
Finished interrupt; after completion
of a hardware interrupt request, this
instruction must be used to reset
the current priority bit in the inservice priority register, ISPR. Not
for use with NMI or INT interrupt
service routines.
Repeat Prefixes
Two repeat prefixes (REPC and REPNC) allow conditional block transfer instructions to use the state of the
CY flag as the termination condition. This allows inequalities to be used when working on ordered data, thus
increasing performance when searching and sorting
algorithms.
11
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pPD70325 (V25 Plus)
Bank Switch Instructions
Escape trap
The CPU traps in an FP01,2 instruction
to allow software to emulate the
floating-point processor since the
",PD70325 does not support an
external hardware coprocessor:
1/0 trap
If the 1/0 trap bit in the PSW is cleared,
a trap is generated on every IN or OUT
instruction. Software can then provide
an updated peripheral address. This
feature provides software portability
between different systems.
The following instructions allow the effective use of the
register banks for software interrupts and multitasking.
Instruction
BRKCS reg 16
Description
Performs a high-speed software
interrupt with context switch to
register bank indicated by lower 3
bits of register 16.
TSKSW reg 16
Performs a high-speed task switch
to register bank indicated by lower 3
bits of register 16. The PC and PSW
are saved in the old banks. PS and
PSW save registers and the new PC
and PSW values are retrieved from
the new register bank's save areas.
MOVSPA
Transfers both SS and SP of old
register bank to new register bank
after bank has been switched by an
interrupt or BRKCS instruction.
MOVSPB reg16
Transfers SS and SP of current
register bank before switching to SS
and SP of new register bank indicated by lower 3 bits of register 16.
INTERRUPT STRUCTURE
The ",PD70325 can service interrupts generated by both
hardware and software. Software interrupts are serviced
through vectored interrupt processing. The following
interrupts are provided.
Interrupt
Divide error
Single step
Description
The CPU traps if a divide error occurs
as the result of a DIV or DIVU
instruction.
The interrupt is generated after every
instruction if the aRK bit in the PSW is
set.
When executing software written for another system, it
is better to implement 1/0 with on-chip peripherals to
reduce external hardware requirements. However, since
",PD70325 internal peripherals are memory mapped,
software conversion may be difficult. The 1/0 trap feature allows for easy conversion from external peripherals
to on-chip peripherals.
Interrupt Vectors
Table 1 lists the interrupt vectors beginning at physical
address OOH. External memory is required to service
these routines. By servicing interrupts via the macroservice function or context switching, this requirement can
be eliminated.
Each interrupt vector is 4 bytes wide. To service a vectored interrupt, the lower addressed word is transferred to
the PC and the upper word to the PS. See figure 5.
Figure 5. Interrupt fMc tor 0
Vector 0
OOOH
002H
.T
I
I
I
001H
003H
PS +- (OO3H, 002H)
PC +- (OO1H, OOOH)
83-000112A
Overflow
Using the BRKV instruction, an
interrupt can be generated as the
result of an overflow.
Interrupt
instructions
The BRK 3 and BRK imm8 instructions
can generate interrupts.
Arraybounds
The CHKIND instruction generates an
interrupt if the specified array bounds
are exceeded.
12
Execution of a vectored interrupt occurs as follows:
(SP-1, SP-2) - PSW
(SP-3, SP-4) - PS
(SP-5, SP-6) - PC
SP - SP-6
IE -0, BRK-O
PS - vector high bytes
PC - vector low bytes
NEe
pPD70325 (V25 Plus)
Table 1. Interrupt
*to,.
Addres8
Vector
Anlgned Use
00
04
08
OC
0
1
2
3
Divide error
Break flag
NMI
BRK3 Instruction
10
14
18
1C
4
5
6
7
BRKV Instruction
CHKlND Instruction
General purpose
FPO Instructions
2O·2C
30
34
38
8·11
12
13
14
General purpose
INTSERO Onterrupt serial error, channel 0)
INTSRO Onterrupt serial receive, channel 0)
INTSTO Onterrupt serial transmit, channel 0)
3C
40
44
48
15
16
17
18
General purpose
INTSER1 Onterrupt serial error, channel 1)
INTSR1 Onterrupt serial receive, channel 1)
INTST1 Onterrupt serial transmit, channel 1)
4C
50
54
58
19
22
1/0 trap
INTDO Onterrupt from DMA.. channel 0)
INTDl Onterrupt from DMA, channel 1)
General purpose
5C
60
64
68
23
24
25
26
General purpose
INTPO Onterrupt from peripheral 0)
INTP1 Onterrupt from peripheral 1)
INTP2 Onterrupt from peripheral 2)
6C
70
74
78
27
30
General purpose
INTTUO Onterrupt from timer unit 0)
INTTU1 Onterruptfrom timer unit 1)
INTTU2 (Interrupt from timer unit 2)
7C
080·3FF
31
32·255
INTTB Onterrupt from time base counter)
General purpose
20
21
28
29
Be careful when assigning the priority of a given interrupt group; the assignment is done by the three priority
bits inonly one interrupt control register in each group.
If interrupts from different groups occur simultaneously
and the groups have the same priority level, the priority
is as shown in table 2.
Table 2. Interrupt Sources
Interrupt Source
(Priority Within Group)
Group
2
1
3
Default
Priority
Nonmaskable interrupt
NMI
Timer unit
INTTUO
INTTU1 INTTU2
1
DMA controller
INTDO
INTD1
2
External peripheral interrupt INTPO
INTP1
0
INTP2
3
Serial channel 0
INTSERO INTSRO INTSTO
4
Serial channel 1
INTSER1 INTSR1 INTST1
5
Time base counter
INTTB
6
Interrupt request
INT
7
The priority of the currently active interrupt is stored in
the ISPR special function register. Bits PR7-PRO corresp~nd to the eight possible interrupt request priorities.
The ISPR keeps track of the priority of active interrupts
by setting the appropriate bit of this register. The address
of this a-bit register is xxFFCH, and the format is shown
below.
I
PR7
I PRs
PRs
PR4
PR3
PR2
PR1
PRo
Hardware Interrupt Configuration
The V25 Plus features a high-performance on-chip controller capable of controlling multiple processing for
interrupts from up to 17 different sources (5 external, 12
internal). The interrupt configuration includes system
interrupts that are functionally compatible with those of
the V20N30 and unique high-performance microcontroller interrupts.
Interrupt Sources
The 17 interrupt sources are divided into groups for
management by the interrupt controller. Using software,
each of the groups can be assigned a priority from 0
(highest) to 7 (lowest). The priority of individual interrupts within a group is fixed in hardware.
NMI and INT are system type external vectored interrupts. NMI is not maskable via software, and is also
recognized by the I'PD70325 during DMA demandrelease transfer. INT is maskable by the IE bit in the PSW
and requires that an external device provide the interrupt
vector number. It is designed to allow the interrupt
controller to be expanded by the addition of an external
interrupt controller such as the I'PD71059.
NMI, INTPO-INTP1 are edge-sensitive inputs. By selecting the appropriate bits in the interrupt mode register,
these inputs can be programmed to be either rising- or
falling-edge triggered. Bits ESO-ES2 correspond to
INTPO-INTP2, respectively, as shown in figure 6.
13
1m
~.
NEe
pPD70325 (V25 Plus)
Figure 6. External Interrupt Mode Register (I NTIf)
a
ES2
a
7
I ES1
laESa
a
Address xxF 40H
ES2
The twelve internal interrupts are:
IESNMI I
INTTUO
INTTU1
INTTU2
INTDO
INTD1
INTSERO
INTSRO
INTSTO
INTSER1
INTSR1
INTST1
INTTB
a
INTP2 Input Effective Edge
Falling edge
Rising edge
a
1
ES1
INTP1 Input Effective Edge
Falling edge
Rising edge
a
1
ESO
INTPO Input Effective Edge
Falling edge
Rising edge
a
Table 3 shows the various interrupt request control
registers, the options for service, their relative priorities,
and the options for multiple control.
NMI Input Effective Edge
ESNMI
Falling edge
Rising edge
a
1
Timer unit 0 interrupt
Timer unit 1 interrupt
Timer unit 2 interrupt
DMA channel 0 interrupt
DMA channel 1 interrupt
Serial channel 0 error interrupt
Serial channel 0 receive interrupt
Serial channel 0 transmit interrupt
Serial channel 1 error interrupt
Serial channel 1 receive interrupt
Serial channel 1 transmit interrupt
Time base counter interrupt
The five external interrupts are:
NMI
INT
INTPO
INTP1
INTP2
Nonmaskable interrupt
Cascaded PIC interrupt
Interrupt from peripheral 0
Interrupt from peripheral 1
Interrupt from peripheral 2
Table 3. Interrupt Processing
Interrupt
Source
Interrupt
Vector
Macro
Service
Bank
Switching
Priority
Setting
Priority
Between Groups
NMI
2
No
No
Not available
a
INT
External
No
No
Not available
7
INTTUO
28
Yes
Yes
Available
Priority
Within Group
Not accepted
Not accepted
Accepted
INTTU1
29
2
INTTU2
30
3
INTDO
20
INTD1
21
INTPO
24
INTP1
25
2
INTP2
26
3
No
Yes
Available
2
Yes
Yes
Available
3
2
INTSERO
12
No
INTSRO
13
Yes
2
INTSTO
14
Yes
3
INTSER1
16
No
INTSR1
17
Yes
INTST1
18
Yes
INTTS
31
No
14
Yes
Yes
Available
Available
4
5
2
3
No
Not available
Multiple
Process Control
6
NEe
IIPD70325 (V25 Plus)
Interrupt Processing Modes
Interrupts, with the exception of NMI, INT, and INTTB
have high-performance capability and can be processed
in any ofthree modes: standard vector method (compatible with V20N30), register bank context switching (supported in hardware), and macroservice (SFR transfers).
The processing mode for a given interrupt can be chosen
by enabling the appropriate bits in the corresponding
interrupt request control register. Each interrupt, except
INTand NMI, has its own associated IRC register. The
general format for each of these registers is shown in
figure 7.
All interrupt processing routines other than those for
NMI and INT must end with the execution of the FINT
instruction. This instruction informs the interrupt controller that the current interrupt service routine is complete; if FINT is not executed within the service routine,
subsequently only interrupts of higher priority will be
accepted.
In the vectored service mode, the CPU traps to a vector
location.
Figure 7. Interrupt Request Control Registers
(IRC)
IF
\ IMK \MSIINT\ ENCS \
0
o
7
Interrupt Flag
IF
o
1
IMK
o
1
MS/INT
o
1
ENCS
o
1
No interrupt request generated
Interrupt request generated
Interrupt Mask
Open (interrupts enabled)
Closed (interrupts disabled)
Interrupt Response Method
Vector interrupt or register bank switching
Macroservice function
Not used
Used
This method of interrupt service offers a dramatic performance advantage over normal vectored service because there is no need to store and retrieve datal
registers on the stack. This also allows hardware-based
real-time task switching in high-speed environments.
In addition to context switching, the I4PD70325 has a
task switch opcode (TSKSW) that allows multiple independent processes to be internally resident. Figure 10
shows the task switching function.
Figure B. Register Bank Context Switching
RB)
RBi
AW
AW
CW
CW
ow
OW
BW
BW
SP
SP
BP
BP
IX
IX
IV
IV
r:::>
OS1
OS1
PS
PS
SS
SS
OSO
OSO
Save PC
Highest (0)
J,
1 1 1
As in the vectored mode, the IE and BRK bits in the PSW
are cleared to zero. After processing, execution of the
RETRBI instruction must be executed to return control
to the original register bank and restore the former PC
and PSW Figures 8 and 9 show register bank context
switching and register bank return.
Register Bank Switching Function
Interrupt Group Priority (0-7)
000
associated IRC register. The PC and PSW are automatically sorted in the save areas of the new register bank,
and the address of the interrupt routine is loaded from
the vector PC storage register in the new register bank.
Save
Save PC
psw
Save
y
Lowest (7)
Register Bank Switching.
Register bank context switching allows interrupts to be
processed rapidly by switching register banks. After an
interrupt, the new register bank selected has the same
bank number (0-7) as the priority programmed in the
Vector PC
Reserved
y
PC
PSW
~
I
psw
Vector PC
Reserved
83SL~21A
15
NEe
"PD70325 (V25 Plus)
Figure 10.
Figure 9. Register Bank Return
Task Switching
RBi
RBI
AW
AW
AW
AW
CW
CW
CW
CW
OW
OW
OW
OW
BW
BW
BW
BW
New
Current
SP
SP
SP
SP
BP
BP
BP
BP
IX
IX
IX
IX
IV
¢:::J
OS1
PS
IV
IV
OS1
OS1
PS
PS
q
IV
OS1
PS
SS
SS
SS
SS
OSO
OSO
oso
OSO
Save PC
Save PC
Save PC
Save PSW
+1
Vector PC
Reserved
4
PC
psw
1
I
H
psw
Save PSW
Save
Vector PC
Vector PC
Reserved
Reserved
il-f
RB
PC
r----
psw
l~
L
Save PC
Save
Reg 16
psw
Vector PC
Reserved
RB Register bank
field
83SL-6822A
83SL-6823A
Interrupt Factor Register
The IkPD70325 provides an additional register that stores
the interrupt vector number of the last-serviced interrupt
request. The register is located in special-function memory and is read only in 8-bit operations. This register
facilitates the use of one register bank to service multiple
interrupt sources, particularly those within the same
group (interrupts within the same group will all context
switch to the same register bank).
The interrupt vector is stored in the IROS register as
shown in figure 11, and is retained unti I the next interrupt
request is accepted. The value of the IROS register is not
altered by NMI, INT, or macroservice transfers. It is
generally recommended that the IROS register be read
before the EI bit is set within the interrupt service routine
to assure that its contents wi II not be altered by multiple
processing routines.
16
Figure 11. Interrupt Factor Register (IRQS)
o
I
0
I
7
Interrupt Factor
Interrupt Vector
0
5
4
Address xxFE FH
Interrupt Vector
INTTUO
1CH
INTTU1
IDH
INTTU2
IEH
INTDO
14H
INTD1
15H
INTPO
18H
INTP1
19H
INTP2
1AH
INTSERO
OCH
INTSRO
ODH
INTSTO
OEH
INTSER1
10H
INTSR1
11H
INTST1
12H
INTTB
1FH
0
NEe
IIPD70325 (V25 Plus)
Macroservice Function
The macroservice function (MSF) is a special microprogram that acts as an internal DMA controller between
on-chip peripheral special-function registers and memory. The MSF greatly reduces the software overhead and
CPU time that other processors would require for register save processing, register returns, and other handling
associated with interrupt processing.
If the MSFis selected for a particular interrupt, each time
the requestis received, a byte or word of data is transferred between an SFR and memory without interrupting
the CPU. Each time a request occurs, the macroservice
counter is decremented. When the counter reaches zero,
an interrupt to the CPU is generated. The MSF also has
a character search option. When selected, every byte
transferred is compared to an 8-bit search character and
an interrupt is generated if a match occurs or if the
macroservice counter reaches zero.
Like the NMI, INT, and INTTB, the two DMA controller
interrupts (lNTDO and INTD1) do not have MSF capability.
Eight 8-byte macroservice channels are mapped into
internal RAM from XXEOOH to XXE3FH. Each macroservice channel contains all necessary information to
execute the macroservice process. Figure 12 shows the
components of each channel.
Figure 12. Macroservice Channels
Upto3FH
Setting the macroservice mode requires programming
the corresponding macroservice control register. Each
individual interrupt, excluding INT, NMI, serial error,
DMA, and TBC, has its own associated register. Figure 13
shows the generic format for all MSC registers.
Figure 13. Macroservice Control Registers
(IISC)
I MSM21 MSM1 I MSMo I
DIR
o
o
7
Macroservlce Mode
Normal (a-bit transfer)
Normal (16-bit transfer)
Character search (a-bit transfer
Other combinations are not allowed.
000
o0 1
100
Data Transfer Direction
DIR
o
Memory to SF R
SF R to memory
Macroservlce Channel
000
Channel 0
1 1 1
Channel
7
J..
------------------TIMER UNIT
The #kPD70325 (figure 14) has two programmable 16-bit
interval timers (TMO and TM1) on chip, each with variable input clock frequencies. Each of the two 16-bit timer
registers has an associated 16-bit modulus register
(MDO and MD1). Timer 0 operates in the interval timer
mode or one-shot mode; timer 1 has only the interval
timer mode.
XXE08H
Interval Timer Mode
MSS
M.S. Channel 0
In this mode, TMO/TM1 are decremented by the selected
input clock, and, after counting out, the registers are
automatically reloaded from the modul us registers and
counting continues. Each time TM1 counts out, interrupts are generated through TF1 and TF2 (timer flags 1
and 2). When TMO counts out, an interrupt is generated
through TFO. The timer-out signal can be used as a
square-wave output whose half-cycle is equal to the
count time.
MSP
Reserved
SCHR
SFRP
MSC
XXEOOH [Internal RAM]
1----16 Bits---l
MSS
MSP
= Macro service segment
= Macro service pOinter
Two input clocks derived from the system clock are
SCLK/6 and SCLK/128. Typical timer values shown below are based on fosc = 10 MHz and fSCLK = fosc/2.
SCHR = Search character
SFRP = Special function register pOinter
MSC = Macro service counter
49·001345A
Clock
SCLK/6
SCLK/128
Timer Resolution
1.2 #kS
25.6 #kS
Full Count
78.643 #kS
1.678 s
17
1m.
~
NEe
pPD70325 (V25 Plus)
Figure 14.
Timer Unit Block Diagram
Figure 15.
Timer Control Register 0 (TMCO)
TSO 'TClKa' MSO 'MClKa' ENTO' AlV 'MOD1' MODo'
Address xxF90H
0
7
I
fSCLK
TSO
Idivided bY~
12:
a
1
~L-':""':'---1
MOD1
0
0
0
0
12~
128
~L~--1--~
MSO
0
1
TMO In Either Mode
Stop countdown
Start countdown
MOOD
TClKO
0
0
1
1
0
1
a
TMO Register Clock Frequency
fscu
.
IOAOR
~
_IOMRO_
R/W
I
,
tOAMR~1
-I
I~
-
tWMRL
IHMOR
1+
tscc-
II
1\
IOMSO
I----
!--IOMRMS-
1\
IOAMS-
j
~tWMSL-1
1\
REFRQ
~
83-004309C
39
NEe
,.,PD70325 (V25 Plus)
Memory Write
1 - - - - - B 1 - - - - + I - - - - B2 -------"
CLKOUT
~I+---\,-------,YK)_\~I
IOKA-
K
)
!+-IOAOW'"
l..-t HMA -
07- 0 0
tSOM
R/Iii
\
,
tWMRL
+-toAMRl
MREQ
I
. I-IHMowr;
-tscc-
1I
1\
I+-tOMRMS-
\
tOAMS-
V
~tWMSL _ _
IOSTB
~
REFRQ
~
-tOMRTC
\1+----."""----~tW-TCL-----+l(
83-004310C
40
NEe
,.,PD70325 (V25 Plus)
//ORad
tOKA
K
~
I+------,- tOAOR _ _ _
rtHISA-
l
1
tHIS OR
tOISO
R/W
I----
/
I\MSTB
I-tOAIS-1
IOSTB
\
tWISL
.
II
m
tscc--
"\.
DMAAK1
DMAAKO
83-004311C
41
NEe
,.PD70325 (V25 Plus)
I/O Write
I
81
CLKOUT
I
82
"I
ICYK
~I
J
~
A19-AO
~K
)
tDADW
rIHISA .....
k.
ISOIS
R/W
F
.
IHISDW
V
\
~
I
I-IDAIS .....
REFRQ
"
IWISL
.
I+-'------- t s e e -
ill
f\
1\
83"004312C
42
NEe
pPD70325 (V25 Plus)
DMA, I/O 10 Memory
~I--------B1--------41---------B2------~
}=1.--------t
eLKOUT
CYK
-------;
----1'L-----..\~---J ~\~----J!~\~---Jlr--------.\
tOKA-
'K
>~
'.
R/Vi
V
\
tWMRL
I-tOAMR-
I--tHMA--
~
/
\
tscc
j..-tOMRMS-
)
f\
tOAMS~ ~tWMSL_
f\
_tSOAOO __
DMARQO
DMARQ1
~
j.-tHOAOO ....
V
~
tWOMRL
1\
-tOOATC-
r
tWTCL
II
83-004313C
43
NEe
JlPD70325 (V25 Plus)
DIM, IIemory to I/O
1------B1-----+-----B2---~
1+----tCYK----+t
CLKOUT
I--tOKA_
R/W
)(
K
J
1\
I--tOAMR_
\+-tHMA_
tWMRL
Ij
"
~
,
1\
tscc
\
~twMSL--l
tOAMS
1\
I---tSOAOQ---.
DMARQO
DMARQ1-
'"
I+-tHOAOQ ....
I
'\
tWOMWL---l
N:
TC1-TCO
~tOOATC_
I
tWTCL
I
83-004314C
44
!\fEe
pPD70325 (V25 Plus)
Refresh
~
__-B1 ___-)----B2-__-J
I+----ICYK----.l
~ ~\'--" ·-----"\\~r
IOKA ___
A19-AO
)
~K
J
1\
D7-DO
R/W
~
11\
f--IOARF1
_IHRFA_
IWRFL
\
-
~
ISCC
"""---83-00431SC
CLKOUT----------------------------------~l~-J
RESET
~
IWRSL1
~
II
83-0043168
45
NEe
"PD70325 (V25 Plus)
CLKOUT
__
RESET -
~~RSU~
_ _
----.Y
~~
83-0043178
READY 1
I
f - - - - B1
BAW ---'---+--- B A W - - - + - - - B 2 - - 1
\--------/
IseRY FrIHCRY
READY ____________________
-J~
I
'\~__________~_____________________________ _
83-0043188
READY 2
1 - - - - B 1 - - - + - - - - BAW - - - + - - - - BAW - - - - + - - - BW - - - + - - - - B 2 - - 1
-
\
n=2
n=3
I+-tHCRY'
tSCRY'
n=2
READY
\
L
In = 3
1/
• tSCRY [READY setup time] and tHCRY [READY hold time] are a function of
T and n. Timings shown are examples for n = 2 and n = 3.
83-0043196
46
1'fEC
pPD70325 (V25 Plus)
HLORQ/ HLlJAK 1
Bus control *
1+-----tDHQHA---~
*A19-AO, 07-00, MREQ, MSTB, IOSTB, R/W
~--------tWHAL-----------~
83-0043208
HLORQ/HLIJAK 2
CLKOUT
HLORQ
~----tWHQL---~
Bus control * --I---------;~l_--+---------------_{
IDKH~----~Il~-----:======~~~~~~----tD-H-Q-C------------~_-_-_-_-_-_~_____________
* A19-AO, 07-00, MREQ, MSTB, IOSTB, R/W
83-0043218
IN7P, OMARQ Input
CLKOUT
INTp,
OMARQ*
~-------tWIQH-------~
* INTP2-INTPO, OMARQ1-0MARQO
:= = = = = = = - t~W~'Q-L- - - - - - - - - - - - - ~
83-0043228
47
IIPD70325 (V25 Plus)
POLL Input
CLKOUT
_ .. 1.
..----tSPLK_ _
POLL~
_ _ _---J!
83-0043236
Nllllnput
CLKOUT
NMI
--11+-:---twNIH-----.jnl4--.~~~~~=-twN-,L====--=--:f
83-0043246
CTSlnput
CLKOUT
1~~.~tW-CTL-==f
83-0043256
48
t\'EC
pPD70325 (V25 Plus)
INTR/IN71UC
CLOOUT
r~---+--~
INTR
tOKIA
tHIAIQ
D7-DO--------------~~----------------+_--------------------------~
83-004326B
Serial Transmit
.-------------------------------------------------------------------------~
CLKOUT
tCYTK
\
I
I
tWSTL
TxD
r\
tHTKO
tWSTH
I
C
)(
tOTKO
83-004441 B
Serial Receive
CLKOUT
tCYRK
\
I
tWSRL
RxD
\
tWSRH
)
K
~tSROK_
tHKRD
83-004332B
49
m
~.
NEe
,.,PD70325 (V25'Plus),
INSTRUCTION SET
Instructions, grouped according to function, are described in a table, near th~ end of this data ,sheet.
Descriptions'include source code, operation, opcode,
number of bytes, and flag status. Supplementary information applicable to the instruction set is contained, in
the following tables.
• Symbols and Abbreviations
• Flag Symbols
• 8- and 16-Bit Registers. When mod = 11, the register
is specified in the operation code by the byte/Word
operand rN =, 0/1) and reg (000 to 111).
• Segment Registers. The segment register is specified
in the operation code by sreg (00,01, la, or 11).
• Memory Addressing. The memory addressing mode is
specified in the operation code by mod (00, 01, or 10)
and mem (000 through 111).
• Instruction Clock Count. This table gives formulas for
calculating the number of clock cycles occupied by
each type of instruction. The formulas, which depend
on byte/word operand and RAM enable/disable, have
variables such as EA(effective address), W (wait
states), and n (iterations or string instructions).
Identifier
Description
far-proc
Procedure located In another program segment
near-label
Label In the current program segment
shortlabel
Label between -128 and
of Instruction
+127 bytes from the end
far-label
Label In another program segment
memptr16
Word containing the offset of the memory location
within the current program segment to which
control Is to be transferred
memptr32
Double word containing the offset and segment
base address of the memory location to which
control Is to be transferred
regptr16
16-blt register containing the offset of the memory
• location within the program segment to which
control Is to be transferred
pop-value
Number of bytes of the stack to be discarded (0 to
64K bytes, usually even addresses)
fp-op
Immediate data to Identify the Instruction code of
the external floating-point operation
R
Register set
W
Word/byte field (0 to 1)
reg
Register field (000 to 111)
mem
Memory field (000 to',111)
Symbols sndAbbrevistions
mod
Mode field (00 to 10)
Identifier
Description
S:W
When S:W - 01 or 11, data - 16 bits. At all other
times, data - 8 bits.
reg
8- or 16-blt general-purpose register
reg8
8-blt general-purpose register
X,XXX,
YYY,
zzz
Data to Identify the Instruction code of the external
floating-point arithmetic chip
reg16
16-bit general-purpose register
AW
Accumulator (16 bits)
dmem
8- or 16-bit direct memory location
AH
Accumulator (high byte)
mem
8- or 16-blt memory location
AL
Accumulator (low byte)
mem8
8-blt memory location
BP
Base pointer register (16 bits)
mem16
16-bit memory location
BW
BW register (16 bits)
mem32
32-bit memory location
BH
BW register (high byte)
sfr
8-bit special function register location
BL
BW regl ster (low byte)
Imm
Constant (0 to FFFFH)
CW
CW register (16 bits)
Imm16
Constant (0 to FFFFH)
CH
CW register (hIgh byte)
Imm8
Constant (0 to FFH)
CL
CW register (low byte)
imm4
Constant (0 to FH)
OW
OW register (16 bits)
OW register (hIgh byte)
Imm3
Constant (0 to 7)
DH
acc
AW or AL register
DL
OW register (low byte)
. Segment register
SP
Stack pointer (16 bits)
sreg
src-table
Name of 256-byte translation table
PC
Program counter (16 bits)
src-block
Name of block addressed by the IX register
PSW
Program status word (16 bits)
dst-block
Name of block addressed by the IV register
near-proc
Procedure within the current program segment
50
NEe
IIPD70325 (V25 Plus)
Symbols and Abbreviations (conI)
Rag Symbols
Identifier
Description
Identifier
Description
IX
Index register (source) (16 bits)
(blank)
No change
Index register (destination) (16 bits)
o
IY
PS
Cleared to 0
. Program segment register (16 bits)
Set to 1
SS
Stack segment register (16 bits)
x
DSo
Data segment 0 register (16 bits)
u
Set or cleared according to the result
Undefined
Data segment 1 register (16 bits)
AC
Auxiliary carry flag
CY
Carry flag
P
S
Parity flag
Sign flag
Z
Zero flag
DIR
Direction flag
IE
v
BRK
MD
Interrupt enable flag
Overflow flag
Break flag
Mode flag
(...)
Values In parentheses are memory contents
disp
Displacement (8 or 16 bits)
ext-disp8
16-bit displacement (sign-extension byte + 8-bit
displacement)
temp
Temporary register (8116/32 bits)
tmpcy
Temporary carry flag (1-blt)
seg
Immediate segment data (16 bits)
offset
Immediate offset data (16 bits)
Transfer direction
+
Addition
Subtraction
x
Multiplication
+
Division
%
Modulo
AND
Logical product
OR
Logical sum
XOR
Exclusive logical sum
XXH
Two-digit hexadecimal value
XXXXH
Four-digit hexadecimal value
Value saved earlier Is restored
8- and 16-Bit Registers (mod
= 11)
reg
w-o
000
AL
AW
001
CL
CW
010
DL
OW
011
BL
BW
100
AH
SP
101
CH
BP
110
DH
IX
111
BH
IY
W-1
ED
Segment Registers
sreg
Register
00
DS1
01
PS
10
SS
11
DSo
lIemory Addressing
= 00
= 01
= 10
mem
mod
000
BW+ IX
BW + IX + disp8
BW + IX + disp16
001
BW+ IV
010
011
+ IX
BP + IV
100
IX
101
IV
110
Direct
111
BW
+ disp8
+ IX + disp8
BP + IV + disp8
IX + dlspS
IV + disp8
BP + dlsp8
BW + dlsp8
+ IV + disp16
+ IX + disp16
BP + IV + disp16
IX + disp16
IV + disp16
BP + disp16
BW + disp16
BP
mod
BW + IV
BP
mod
BW
BP
51
NEe
pPD70325 (V25 PIUs)
Instruction Clock Count.
Mnemonic
Operand
Clocks
Mnemonic
Operand
Clocks
ADD
reg8, reg8
reg16, reg16
2
2
CALL
near-proc
regptr16
22+2w [18+2W)
22+2W [18+2W)
reg8, mem8
reg16, mem16
EA+6+W
EA+8+2W
mem8, reg8
reg16, mem16
EA+8+2W [EA+6+W]
EA+12+4W [EA+8+2W]
memptr16
far-proc
memptr32
EA+26+4W [EA+24+4W]
36+4W [34+4WJ
EA+36+8W [EA+24+8W]
reg8,Imm8
reg16,Imm8
mem16, Imm16
5
5
6
CY
DIR
2
2
mem8,Imm8
mem16,Imm8
mem16, Imm16
EA+9+2W [EA+7+2W]
EA+9+2W [EA+7+2W]
EA+14+4W [EA+10+4W]
reg8, CL
reg16, CL
8
8
mem8, CL
mem16, CL
EA+14+2W [EA+12+W]
EA+18+4W [EA+14+2W]
AL,Imm8
AW,lmm16
5
6
reg8,Imm3
reg16,Imm4
7
7
mem8,Imm3
mem16,Imm4
EA+11 +2W [EA+9+W]
EA+15+4W [EA+10+2WJ
reg8, reg8
reg16, reg16
2
2
reg8, mem8
reg16, mem16
EA+6+W
EA+8+2W
mem8, reg8
mem16, reg16
EA+6+W
EA+8+2W
reg8,ImmS
reg16,ImmS
reg16, Imm16
5
5
6
memS,Imm8
mem16,ImmS
mem16, Imm16
EA+7+W
EA+10+2W
EA+10+2W
AL,Imm8
AW, imm16
5
6
memB, mem8
mem16, mem16
23+2W [19+2W]
27+4W[21 +2W]
ADD4S
ADDC
CLR1
22+(27-i:3W)n [22+(25+3W)n]
Same as ADD
ADJ4A
9
ADJ4S
9
ADJBA
17
ADJBS
AND
CHKlND
CMP
17
reg8, reg8
reg16, reg16
2
2
reg8, memS
reg16, mem16
EA+6+W
EA+8+2W
memS, regS
mem16, reg16
EA+S+2W [EA+6+W]
EA+12+4W [EA+S+2W]
reg8,ImmS
reg16, Imm16
5
6
memS, imm8
mem16, Imm16
EA+9+2W [EA+7+2W]
EA+14+4W [EA+10+4W]
CMP4S
Bcond (conditional branch)
S or 15
CMPBK
BCWZ
S or 15
BR
BRK
22+ (23+2W)n
CMPBKB
16+ (21+2W)n
near-label
short-label
12
12
regptr16
memptr16
13
EA+17+2W
CMPM
far-label
memptr32
15
EA+25+4W
CMPMB
16+(15+W)n
CMPMW
16+(17+2W)n
3
immS
55+ 10W [43+ 10W]
56+10W [44+10W]
BRKCS
15
BRKV
55+ 10W [43+ 10W]
BTCLR
29
BUSLOCK
2
52
EA+26+4W
CMPBKW
16+ (25+4W)n
memB
mem16
17+W
19+2W
CVTBD
19
CVTBW
3
CVTDB
20
CVTWL
S
NEe
pPD70325 (V25 Plus)
Instruct/on Clock Count. (conI)
Clocks
Mnemonic
Operand
Clocks
OBNZ
Mnemonic
8 or 17
MOV
OBNZE
8 or 17
reg8. reg8
reg16. reg16
2
2
OBNZNE
8 or 17
reg8. mem8
reg16. mem16
EA+6+W
EA+S+2W
mem8. regS
mem16. reg16
EA+4+W [EA+2]
EA+6+2W [EA+2]
regS.lmmS
reg16. Imm16
5
6
memSjlmmS
mem16. Imm16
EA+5+W
EA+5+2W
OEC
Operand
regS
reg16
5
2
memS
mem16
EA+11+2W [EA+9+2W]
EA+15+4W [EA+11+4W]
01
4
OISPOSE
12+2W
OIV
OIVU
AW, regS
AW, mem8
46-56
EA+48+W to EA+58+W
AL. dmemS
AW, dmem16
9+W
11+2W
OW,AW, reg16
OW; AW,
mem16
54·64
EA+58+2W to EAt6S+2W
dmemS.AL
dmem16. AW
7+W [5]
9+2W [5]
AW, regS
AW, mem8
31
EA+33+W
sreg. reg16
sreg. mem16
4
EA+10t2W
39
EA+43+2W
reg16. sreg
mem16. sreg
3
OW,AW, reg16
Ow, AW, mem16
AH. PSW
PSw, AH
2
OSO:
2
OS1:
2
EI
12
EXT
regS. regS
regS.lmm4
41·121
42·122
MOVBK
EA+7+2W [EA+3]
3
Em
OSO. reg16.
memptr32
OS1. reg16.
memptr32
EA+19+4W
memS. memS
mem16. mem16
2O+2W [16+W]
16+ (20+ 4W) n [16+ (12+ 2W)n]
EA+19+4W
FINT
2
FP01
60+ 10W [48+ 10W]
MOVBKB
memS. memS
16+(16+2W)n [16+(12+W)n]
FP02
60+ 10W [48+ 10W]
MOVBKW
mem16. mem16
24+4W [20+2W]
HALT
IN
INC
INM
INS
0
MOVSPA
AL.lmm8
AW,lmm8
14+W
16+2W
MOVSPB
AL.OW
AW,OW
13+W
15+2W
regS
reg16
5
2
mem8
mem16
EA+11+2W [EA+9+2W]
EA+15+4W [EA+11+4W]
memS. OW
mem16. OW
19+2W [17+2W]
21 +4W [17+4W]
mem8. OW
mem16. OW
1S+(13+2W)n [18+(11+2W)n]
18+ (15+4W)n [18+ (11 +4W)n]
reg8. reg8
reg8.lmm4
63·155
64·156
LOEA
EA+2
LOM
mem8
mem16
12+W
16+ (12+2W)n
LOMB
mem16
14+2W
LOMW
mem8
16+(10+W)n
MUL
MULU
16
11
AW, AL. reg8
AW, AL. mem8
31·40
EA+33+W to EA+42+W
OW,AW, AW,
reg16
OW,AW, AW,
mem16
39·4S
reg16. reg16.
Imm8
reg16. mem16.
Imm8
39·49
reg16. reg16.
imm16
reg16.
mem16. Imm16
40·50
reg8
mem8
24
EA+26+W
reg16
mem16
32
EA+34+2W
EA+43+2W to EA+52+2W
EA+43+2Wto EA+53+2W
EA+44+2Wto EA+54+2W
53
NEe
pPD70325 (V25 Plus)
Instruction Clock Counts (cont)
Mnemonic
Operand
Clocks
Mnemonic
Operand
Clocks
NEG
regS
reg16
5
5
PREPARE
imm16, immS
memS
mem16
EA+11+2W [EA+9+W]
EA+15+4W [EA+11+2W]
immS = O:27+2W
immS = 1:39+4W
immS = n > 1:46+19
(n-1)+4W
Nap
NOT
NOn
OR
OUT
OUTM
3
regS
reg16
5
5
memS
mem16
EA+11+2W [EA+9+W]
EA+15+4W [EA+11+2W]
CY
2
regS. CL
reg16, CL
7
7
memS, CL
mem16, C.L
EA+13+2W [EA+11+W]
EA+17+4W [EA+13+2W]
regS. imm3
reg16, imm4
6
6
memS, imm3
mem16, imm4
EA+1O+2W [EA+S+W]
EA+14+4W [EA+10+2W]
regS, regS
reg16, reg16
2
2
regS, memS
reg16, mem16
EA+6+W
EA+S+2W
memS, regS
mem16, reg16
EA+S+2W [EA+6+W]
EA+12+4W [EA+S+2W]
regS, immS
reg16, imrn16
5
6
memS, immS
mem16, imm16
EA+9+W [EA+7+W]
EA+14+4W [EA+10+4W]
AL, immS
AW, imm16
5
6
immS, AL
immS,AW
10+W
10+2W
Ow, AL
Ow, AW
9+W
9+2W
Ow, memS
OW,mem16
19+2W [17+2W]
21 +4W [17+4W]
Ow, memS
1S+(13+2W)n
[1S+(11 +2W)n]
1S+(15+4W)n
[1S+(11+4W)n]
Ow, mem16
POLL
POP
54
12+2W
EA+16+4W [EA+12+2W]
OS1
SS
13+2W
13+2W
OSO
PSW
13+2W
14+2W
R
S2+16W [58]
reg16
mem16
10+2W [6]
EA+1S+4W [EA+14+4W]
OS1
PS
11+2W [7]
11+2W [7]
SS
OSO
11 +2W [7]
11 +2W [7]
PSW
R
10+2W[6]
S2+16W [50]
immS
imm16
13+2W[9]
14+2W [10]
REP
2
REPE
2
REPZ
2
REPC
2
REPNC
2
REPNE
2
REPNZ
RET
2
null
pop-value
20+2W
20+2W
null
pop-value
29+4W
30+4W
43+6W [35+2W]
RETI
RETRBI
ROL
12
regS, 1
reg16, 1
S
S
memS,1
mem16,1
EA+14+2W [EA+12+W]
EA+1S+4W [EA+14+2W]
regS, CL
reg16, CL
11+2n
11+2n
memS, CL
EA+17+2W+2n
[EA+15+W+2n]
EA+21 +4W+2n
[EA+17+2W+2n]
mem16, CL
0
reg16
mem16
2
PS:
PUSH
regS,immS
reg16, imm8
9+2n
9+2n
memS, immS
EA+13+2W+2n
[EA+11 +W+2n]
EA+17+4W+2n
[EA+13+2W+2n]
mem16,ImmS
ROL4
regS
memS
17
EA+1S+2W [EA+16+2W]
NEe
pPD70325 (V25Plus)
InstructiDn Clock Count. (conI)
Mnemonic
ROLC
ROR
ROR4
RORC
SET1
Operand
2
2
reg8, CL
reg16, CL
7
7
mem8, CL
mem16, CL
EA+13+2W [EA+11 +W]
EA+17+4W [EA+13+2W]
reg8,lmm3
reg16,lmm4
6
6
mem8,lmm3
mem16,lmm4
EA+10+2W [EA+8+W]
EA+14+4W [EA+10+2W]
Same as ROL
SHRA
Same as ROL
SS:
2
memS
mem16
12+2 [10]
16+ (10+2W)n [16+(6+2W)n]
STMB
memS
16+ (S+W)n [16+(6+W)n]
STMW
mem16
14+2W [10]
STOP
0
Same as ADD
SUB4S
SUBC
Clocks
reg8, CL
reg16, CL
7
7
mem8, CL
mem16, CL
EA+11+W
EA+13+2W
reg8,lmm3
reg16,lmm4
6
6
mem8,lmm3
mem16,lmm4
EA+8+W
EA+10+2W
21
EA+24+2W [EA+22+2W]
CV
DIR
Same as ROL
TEST
Operand
Same as ROL
SHR
SUB
Mnemonic
TEST1
Same as ROL
reg8
mem8
SHL
STM
Clocks
Same as ROL
22+ (27+3W)n
[22+ (25+3W)n]
Same as ADD
regS, regs
reg16, reg16
4
4
regS, memS
reg16, mem16
EA+S+W
EA+10+2W
memS, regS
mem16, reg16
EA+S+W
EA+10+W
regS, immS
reg16, imm16
7
S
memS, immS
mem16, imm16
EA+11 +W
EA+11 +2W
AL, immS
AW, imm16
5
6
TRANS
10+W
TRANSB
10+W
TSKSW
XCH
XOR
11
reg8, reg8
reg16, reg16
3
3
reg8, mem8
reg16, mem16
EA+10+2W [EA+8+2W]
EA+14+4W [EA+10+4W]
mem8, regS
mem16, reg16
EA+10+2W [EA+S+2W]
EA+14+4W [EA+10+4W]
AW, reg16
reg16, AW
4
4
1m
Same as AND
Notes:
(1) If the number of clocks Is not the same for RAM enabled and RAM
disabled conditions, the RAM enabled value is listed first, followed by the RAM disabled value In brackets; for example,
EA+S+2W [EA+6+W]
(2) Symbols In the Clocks column are defined as follows.
EA = additional clock cycles required for calculation of the
effective address
= 3 (mod 00 or 01) or 4 (mod 10)
W = number of wait states selected by the wrc register
n = number of iterations or string instructions
55
NEe
pPD70325 (V25Plus)
Execution Clock Counts for Operations
Byte
RAM Enable
Word
RAM Disable
Context switch interrupt (Note 1)
DMA (Single-step mode) (Note 2)
8+2W
DMA (Demand release mode)
DMA (Burst mode)
8+2W
RAM Enable
RAM Disable
27
27
14+4W
14+4W
(2+W)n
(2+W)n
(4+2W)n
(4+2W)n
3.5 + (4+ 2W) (n-1)
3.5 + (4+2W)(n-1)
9.5 +2W+ (4+ 2W) (n-1)
9.5 +2W+ (4+2W)(n-1)
2+W
2+W
DMA (Single-transfer mode)
Interrupt (INT pin) (Note 3)
4+2W
4+2W
62+6W
62+6W
Macroservice, sfr .... mem (Note 2)
24+W
19+W
26+2W
21+2W
Macroservice, mem .... sfr
22+W
20+W
22+2W
22+2W
mem
27+W
27+W
~
37+W
34+W
58+10W
58+10W
Macroservice (Search char mode), sfr
~
Macroservice (Search char mode), mem
sfr
Vectored priority interrupts (including NMI)
(Note 1)
N = number of clocks to complete the instruction currently executing.
n = number of transfers
Notes:
(1) Every interrupt has an additional associated latency time of 27 +
N clocks. During the 27 clocks, the interrupt controller performs
some overhead tasks such as arbitrating priority. This time
should be added to the above listed interrupt and macroservice
execution times.
(2) The DMA and macroservice clock counts listed are the required
number of CPU clocks for each transfer.
(3) When an external interrupt is asserted, a maximum of 6 clocks is
required for internal synchronization before the interrupt request
flag is set. For an internal interrupt, a maximum of 2 clocks is
required.
Bus Controller Latency
Clocks
Latency
Mode
Hold request
Refresh active
9+3W
Intack active
10+2W
Typ
No refresh or intack
DMA request
(Notes 1, 2)
Max
7+2W
Burst
3
14+2W
Single-step
3
14+2W
Demand release
3
14+2W
Single-transfer
4
14+2W
Notes:
(1) The listed DMA latency times are the maximum number of clocks
when a DMA request is asserted until DMAAK or MREQ goes low
in the corresponding DMA cycle.
(2) The test conditions are: no wait states, no interrupts, no macroservice requests, and no hold requests.
56
NEe
pPD70325 (V25 Plus)
Instruction Set
Mnemonic Operand
Operation
7
6
Operation Code
3 2
5 4
0
0
Flags
0
Bytes
W
2
W
2-4
W
2-4
W
3-6
AC
CY
V
P
S
z
Data Transfer
MOV
reg, reg
reg +- reg
0
0
reg
mem, reg
(mem) +- reg
0
0
mod
reg,mem
reg +- (mem)
0
(mem) +- imm
mod
0
0
reg
0
mod
mem,imm
reg
0
0
reg
mem
0
0
0
0
0
0
mem
reg,imm
reg +- imm
0
acc,dmem
When W = 0: AL +- (dmem)
WhenW= 1:AH +- (dmem + 1),
AL +- (dmem)
0
0
0
0
dmem,acc
When W = 0: (dmem) +- AL
WhenW= 1 : (dmem + 1) +- AH,
(dmem) +- AL
0
0
0
0
sreg, reg16
sreg +- reg16 sreg: SS, OSO, OS1
0
sreg,mem16
sreg +- (mem16) sreg : SS, OSO, OS1
0
W
0
mod
reg16,sreg
reg16 +- sreg
0
0
(mem16) +- sreg
0
mod
0
reg16 +- (mem32),
OSO +- (mem32 + 2)
OS1,reg16,
mem32
reg16 +- (mem32),
OS1 +- (mem32 + 2)
AH,PSW
AH +- S, Z, x, AC, x, P, x, CY
0
0
PSW,AH
S, Z, x, AC, x, P, x, CY +- AH
0
0
LOEA
reg16, mem16
reg16 +- mem16
0
0
TRANS
src-table
AL +- (8W + AL)
XCH
reg, reg
reg
0
mod
reg
mem
sreg
reg
sreg
mem
0
0
0
0
mod
0
0
~reg
(mem)
AW,reg16
orreg16, AW
AW~reg16
0
0
mod
0
3
0
2
0
2-4
0
2
0
2-4
1m
2-4
0
0
0
2-4
x
x
x
x
x
2-4
0
mem
0
0
0
0
W
2
W
2-4
reg
0
reg
0
W
0
0
reg
mem, reg
orreg,mem
3
mem
reg
0
W
mem
reg
0
0
0
reg
mod
~
sreg
0
0
OSO,reg16,
mem32
reg
0
0
mem16,sreg
sreg
0
0
2-3
reg
0
0
0
0
0
mem
mem
0
reg
57
NEe
pPD70325 (V25 Plus)
Instruction Set (cont)
Operation Code
Flags
4
3
0
0
0
0
0
0
0
0
6
5
Operation
7
REPC
While CW ;II!: 0, the next byte of the
primitive block transfer instruction is
executed and CW is decremented (-1).
If there is a waiting interrupt, it is
processed. When CV ;II!: 1, exit the loop.
REPNC
While CW ;II!: 0, the next byte ofthe
primitive block transfer instruction is
executed and CW is decremented (-1).
If there is a waiting interrupt, it is
processed. When CV ;II!: 0, exitthe loop.
REP
REPE
REPZ
While CW ;II!: 0, the next byte of the
primitive block transfer instruction is
executed and CW is decremented (-1 ).
If there is a waiting interrupt, it is
processed. Ifthe primitive block transfer
instruction is CMPBK or CMPM and
Z;II!: 1, exit the loop.
0
0
REPNE
REPNZ
While CW ;II!: 0, the next byte of the
primitive block transfer instruction is
executed and CW is decremented (-1).
If there is a waiting interrupt, it is
processed. If the primitive block transfer
instruction is CMPBK or CMPM and
Z ;II!: 0, exit the loop.
0
0
Mflemonic Operand
2
AC
CV
V
P
S
Z
W
x
x
x
x
x
x
W
x
x
x
x
x
x
0
Bytes
Repeat Prefixes
0
0
Primitive Block Transfer
MOVBK
dst-block,
src-block
When W = 0: (IV) ~ (IX)
DIR = 0: IX ~ IX + 1, IV ~ IY + 1
DIR = 1:IX ~ IX-1,IY ~ IY-1
When W = 1: (IY + 1, IY) ~ (IX + 1,IX)
DIR = 0: IX ~ IX + 2, IY ~ IY + 2
DIR = 1: IX ~ IX-2,IY ~ IY-2
0
0
0
CMPBK
src-block,
dst-block
When W = 0: (IX) -(IY)
DIR = 0: IX ~ IX + 1, IY ~ IY + 1
DIR= 1:IX ~ IX-1,IY ~ IY-1
WhenW = 1:(IX+ 1,IX)-(IY + 1,IY)
DIR = 0: IX ~ IX + 2, IY ~ IY + 2
DIR = 1:IX ~ IX-2,IY ~ IY-2
0
0
0
CMPM
dst-block
When W = 0: AL- (IY)
DIR=O:IY ~ IY+ 1;DIR=1:IY ~ IV-1
WhenW= 1:AW-(lY + 1,IY)
DIR=O:JY ~ IY +2;DIR= 1:IY ~ IY-2
0
0
LDM
src-block
When W = 0: AL ~ (IX)
DIR=O:IX~ IX+ 1;DIR= 1:IX~ IX-1
WhenW= 1:AW ~ (IX+ 1,IX)
DIR=O:IX ~ IX+2;DIR= 1 :IX ~ IX-2
0
0
STM
dst-block
When W = 0: (IV) ~ AL
DIR=O:IY ~ IY+ 1;DIR= 1:IY ~ IY-1
WhenW=1:(IY+1,IY) ~AW
DIR=O:IY ~ IY+2;DIR= 1:IY ~ IY-2
0
0
58
0
0
0
W
W
W
t\fEC
pPD70325 (V25 Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
16-bitfield ... AW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Flags
0
Bytes
AC
CV
V
P
S
Z
Bit Field Transfer
INS
regS, regS
3
0
0
0
reg
reg
reg8,imm4
EXT
reg8, reg8
16-bitfield ... AW
AW ... 16-bitfield
0
4
0
0
0
0
0
0
AW ... 16-bitfield
3
0
0
0
reg
0
0
reg
reg8,imm4
0
reg
4
0
0
0
0
0
reg
0
0
W
0
W
I/O
IN
OUT
ace,imm8
When W = 0: AL ... (immS)
WhenW= 1:AH ... (immS + 1),
AL ... (immS)
0
ace, DW
When W = 0: AL ... (DW)
WhenW= 1:AH ... (DW+ 1),
AL ... (DW)
0
immS,acc
When W = 0: (immS) ... AL
WhenW= 1:(immS+ 1) ... AH,
(immS) ... AL
0
DW,acc
When W = 0: (DW) ... AL
WhenW= 1:(DW + 1) ... AH,
(DW) ... AL
0
W
0
2
1m
2
W
Primitive Block I/O Transfer
INM
dst-block, DW
When W = 0: (IV) ... (DW)
DIR = 0: IV ... IV + 1
DIR = 1:IV ... IV-1
When W = 1: (IV + 1, IV) ...
(DW+1,DW)
DIR = 0: IV ... IV + 2
DIR= 1:IV ... IV-2
0
0
OUTM
DW,src-block
When W = 0: (DW) ... (IX)
DIR = 0: IX ... IX + 1
DIR = 1:IX ... IX-1
When W = 1: (DW + 1, DW) ...
(IX+1,IX)
DIR = 0: IX ... IX + 2
DIR=1:IX ... IX-2
0
0
0
W
W
59
NEe
"PD70325 (V25 Plus)
Instruction Set (cont)
Operation Code
Mnemonic Operand
Operation
7
6
5
4
3
2
o
0
0
0
o
0
Flags
V P
o
Bytes
AC
CY
W
2
x
x
x
W
2-4
x
x
W
2-4
x
W
3-4
W
o W
S
Z
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3-6
x
x
x
x
x
x
2-3
x
x
x
x
x
x
x
x
x
x
x
Addition I Subtraction
ADD
reg, reg
reg +- reg
+ reg
reg
mem, reg
(mem) +- (mem)
+ reg
o
0
0
mod
reg,mem
reg +- reg + (mem)
o
0
reg +- reg
+ imm
0
AD DC
(mem) +- (mem)
0
000
+ imm
ace, imm
When W = 0: AL +- AL + imm
When W = 1: AW +- AW + imm
reg, reg
reg +- reg
+ reg + CY
0
000
mod
0
0
o
0
0
0
0
000
o
0
mem
o
o
o
o
o
0
o
0
(mem) +- (mem)
+ reg + CY
o
0
0
reg,mem
reg +- reg
+ (mem) + CY
mod
reg,imm
reg +- reg
+ imm + CY
o
o
mem,imm
(mem) +- (mem) + imm + CY
acc,imm
WhenW = O:AL +- AL + imm + CY
When W = 1: AW +- AW + imm + CY
000
reg, reg
reg +- reg - reg
o
mod
SUB
0
0
0
reg,mem
(mem) +- (mem) - reg
reg +- reg - (mem)
o
o
o
o
o
o
reg
o
o
0
mod
reg,imm
reg +- reg - imm
0
0
(mem) +- (mem) - imm
000
SUBC
= O:AL +- AL - imm
= 1: AW +- AW - imm
acc,imm
WhenW
When W
reg,reg
reg +- reg - reg - CY
o
0
o
0
o
(mem) +- (mem)-reg-CY
o
0
reg,mem
reg +- reg-(mem)-CY
o
0
mod
60
x
W
2-4
x
x
x
x
x
x
W
3-4
x
x
x
x
x
W
3-6
x
x
x
x
x
x
o W
2-3
x
x
x
x
x
x
W
2
x
x
x
x· x
x
W
2-4
x
x
x
x
x
x
W
2-4
x
x
x
x
x
W
3-4
x
x
x
x
x
x
W
3-6
x
x
x
x
x
x
o W
2-3
x
x
x
x
x
x
W
2
x
x
x
x
x
x
W
2-4
x
x
x
x
x
x
W
2-4
x
x
x
x
x
S
S
0
o
mem
o
0
S
reg
o
0
S
mem
o
0
reg
o
0
mod
x
mem
reg
mem, reg
x
reg
o
o
mod
x
mem
o
mem,imm
x
reg
reg
000
x
o
o
0
mod
2-4
0
reg
mem, reg
W
0
mem
o
0
W
mem
reg
000
o
0
reg
000
S
mem
reg
o
0
mod
S
reg
reg
mem, reg
0
mem
reg
o
mem,imm
o
reg
mod
reg,imm
0
reg
reg
0
mem
o
0
reg
mem
NEe
IIPD70325 (V25 Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
Flags
0
Bytes
AC
CY
V
P
S
Z
W
3-4
x
x
x
x
x
x
W
3-6
x
x
x
x
x
x
2-3
x
x
x
x
x
x
2
u
x
u
u
u
x
2
u
x
u
u
u
x
x
u
u
u
x
Addition/Subtraction (cont)
SUBC
reg +- reg-imm-CY
reg,imm
0
0
0
0
0
0
mem,imm
acc,imm
(mem) +- (mem)-imm-CY
S
reg
0
0
mod
0
mem
WhenW = O:AL +- AL-imm-CY
WhenW= 1:AW +- AW-imm-CY
0
0
0
0
W
dst BCD string +- dst BCD string
+ src BCD string
0
0
0
0
0
0
0
dst BCD string +- dst BCD string
- src BCD string
0
0
0
0
dst BCD string - src BCD string
0
0
0
0
0
0
0
S
BCD Operation
ADD4S
SUB4S
CMP4S
ROL4
reg 8
7
mem8 7
ROR4
reg 8
7
mem8 7
AL
AL
AL
AL
7
7
mem8
0
7
7
mem8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
mod
2
3
0
0
0
0
0
1m
3-5
0
0
0
mem
0
3
0
0
reg
0
3-5
0
0
0
reg
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
mod
0
0
0
0
0
0
0
0
0
0
0
0
0
mem
BCD Adjust
ADJBA
When (AL AND OFH) > 9 or AC = 1 :
AL +- AL + 6, AH +- AH + 1, AC ... 1,
CY ... AC, AL ... AL AND OFH
0
0
ADJ4A
When (AL AND OFH) > 9 or AC = 1:
AL ... AL+ 6,CY ... CYORAC,AC ... 1,
WhenAL>9FH,orCY= 1:
AL ... AL + 60H, CY ... 1
0
0
ADJBS
When (AL AND OFH) > 9 or AC = 1 :
CY +- AC,AL ... ALANDOFH
0
0
ADJ4S
When (AL AND OFH) > 9 or AC = 1:
AL ... AL - 6, CY ... CY OR AC, AC ... 1,
WhenAL>9FH,orCY = 1:
AL ... AL + 60H, CY ... 1
0
0
0
0
0
x
x
u
u
u
u
0
x
x
u
x
x
x
x
x
u
u
u
u
x
x
u
x
x
x
61
NEe
"PD70325 (V25 Plus)
Instruction Set (cont)
Mnemonic Operand
7
Operation
6
Operation Code
3 2
5 4
Flags
V
P
S
z
x
x
x
x
x
x
x
x
x
x
0
Bytes
AC
CY
0
2
W
2-4
x
x
x
x
x
0
2
x
x
x
x
x
W
2-4
x
x
x
x
x
x
x
x
x
x
x
x
u
u
u
x
x
u
u
u
x
x
u
u
u
x
x
u
u
u
Incrementl Decrement
INC
regS
regS +- regS
+1
0
mem
DEC
(mem) +- (mem)
0
reg
mem
reg
+1
+1
reg16
reg16 +- reg16
regS
regS +- regS - 1
mem
(mem) +- (mem) - 1
reg16
0
reg16 +- reg16 - 1
mod
0
0
0
0
0
0
0
0
0
reg
mod
0
0
mem
0
0
0
reg
Multiplication
MULU
regS
memS
reg16
mem16
MUL
regS
memS
reg16
mem16
62
AW +- ALxregS
AH = O:CY +- 0, V+-O
AH ;II!: 0: CY +- 1, V +- 1
AW +- ALx(memS)
AH = O:CY +- 0, V+-~
AH ;II!: 0: CY +- 1, V +- 1
0
0
0
mod
OW,AW +- AWxreg16
OW = 0: CY +- 0, V+-~
OW ;II!: 0: CY +- 1, V +- 1
OW, AW +- AW x (mem16)
OW = 0: CY +- 0, V+-~
OW ;II!: 0: CY +- 1, V +- 1
2
0
2·4
0
2
0
2·4
0
mem
0
0
OW,AW +- AWxreg16
OW = AW sign expansion: CY +- 0, V+-~
OW ;II!: AW sign expansion: CY +- 1, V +- 1
0
0
reg16 +- reg16ximmS
Product::5 16 bits: CY +- 0, V+-O
Product> 16 bits: CY +- 1, V +- 1
0
reg16,
mem16,
immS
reg16 +- (mem16) x immS
Product::5 16 bits: CY +- 0, V+-O
Product> 16 bits: CY +- 1, V +- 1
0
0
mod
reg
reg16,
reg16,
imm16
reg16 +- reg16 x imm16
Product::5 16 bits: CY +- 0, V+-~
Product> 16 bits: CY +- 1, V +- 1
0
0
reg16,
mem16,
imm16
reg16 +- (mem16)ximm16
Product::5 16 bits: CY +- 0, V+-~
Product> 16 bits: CY +- 1, V +- 1
0
0
mod
reg
0
u
x
x
u
u
u
0
2·4
u
x
x
u
u
u
2
x
x
u
u
u
2·4
x
x
u
u
x
x
u
u
u
3·5
x
x
u
u
u
4
x
x
u
u
u
4-6
x
x
u
u
u
reg
mem
0
reg16,
reg16,
immS
2
mem
0
0
OW,AW +- AWx(mem16)
OW = AW sign expansion: CY +- 0, V+-~
mod
OW;II!: AW sign expansion: CY +- 1, V +- 1
0
reg
0
mod
u
reg
0
0
mod
u
mem
0
0
AW +- AL x regS
AH = ALsign expansion: CY +- 0, V+-~
AH ;II!: AL sign expansion: CY +- 1, V +- 1
AW +- ALx(memS)
AH = AL sign expansion: CY +- 0, V+-~
AH ;II!: AL sign expansion: CY +- 1, V +- 1
0
0
reg
0
3
0
u
reg
reg
0
mem
0
reg
0
reg
0
0
mem
1tt{EC
"PD70325 (V25· Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
Flags
S
z
u
u
u
u
0
Bytes
AC
CY
V
0
2
u
u
u
0
2-4
u
u
u
u
2
u
u
u
u
2-4
u
u
u
u
u
u
0
2
u
u
u
u
u
u
0
2-4
u
u
u
u
u
u
P
Unsigned Division
DIVU
reg8
mem8
reg16
mem16
temp +- AW
When temp 7 reg8 > FFH:
(SP-1,SP-2) +- PSW,
(SP-3, SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AH +- temp % reg8, AL +- temp 7 reg8
0
temp +- AW
When temp 7 (mem8) > FFH:
mod
(SP-1,SP-2) +- PSW,
(SP-3, SP-4) +- PS,
(SP-5,SP-6) +- PC,SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AH +- temp % (mem8), AL +- temp 7 (mem8)
0
temp +- AW
When temp 7 reg16 > FFFFH:
(SP-1,SP-2) +- PSW,
(SP-3, SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AH +- temp% reg16, AL +- temp 7 reg16
0
temp +- AW
When temp 7 (mem16) > FFFFH:
mod
(SP-1,SP-2) +- PSW,
(SP-3, SP-4) +- PS,
(SP-5, SP-6) +- PC,SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AH +-temp%(mem16),AL +-temp7(mem16)
0
temp +- AW
When temp 7 reg8 > 0 and temp 7 reg8
> 7FH or temp 7 reg8 < 0 and
temp 7 reg8 < 0-7FH-1:
(SP-1,SP-2) +-PSW,
(SP-3, SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AH +- temp % reg8, AL +- temp 7 reg8
0
temp +- AW
When temp 7 (mem8) > 0 and (mem8) >
mod
7 FH ortemp 7 (mem8) < 0 and
temp 7 (mem8) < 0-7FH -1:
(SP-1, SP-2) +- PSW,
(SP-3, SP-4) +- PS,
(SP-5,SP-6) +- PC,SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AH +- temp % (mem8), AL +- temp 7 (mem8)
0
0
0
0
reg
mem
u
reg
III
0
mem
Signed Division
DIV
reg8
mem8
reg
mem
63
NEe
IIPD70325 (V25 Plus)
Instruction Set (cant)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
Flags
0
Bytes
AC
CY
V
P
S
z
2
u
u
u
u
u
u
2-4
u
u
u
u
Signed Division (cont)
OIV
reg16
mem16
temp +- OW, AW
When temp -7 reg16 > 0 and reg16
> 7FFFH or temp -7 reg16 <
0-7FFFH-1:
(SP-1,SP-2) +- PSW,
(SP-3,SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AH +- temp%reg16,AL +- temp -7 reg16
0
temp +- OW, AW
When temp -7 (mem16) > 0 and (mem16)
mod
> 7FFFHortemp -7 (mem16) reg16 or
(mem32 + 2) < reg16
(SP-1,SP-2) ... PSW,
(SP-3, SP-4) ... PS,
(SP-5, SP-6) ... PC, SP ... SP-6,
IE ... 0, BRK ... 0,
PS ... (23,22), PC ... (21, 2a)
0
0
mod
reg
2
a
a
0
0
0
0
a
Rim
2
a
0
a
2-4
mem
CPU Control
HALT
CPU Halt
STOP
CPU Halt
BUSLOCK
Bus Lock Prefix
a
0
0
0
0
0
FP01
(Note 1)
fp-op
a
Y
fp-op,mem
data bus ... (mem)
fp-op
No Operation
y
0
y
fp-op,mem
data bus ... (mem)
y
Y
y
y
0
a
y
y
0
a
y
y
a
mod
FPa2
(Note 1)
a
0
No Operation
a
mod
0
a
y
0
0
a
x x
X
Z
Z
Z
x x
X
2-4
x
2
2
mem
Z
Z
Z
x
2-4
mem
Notes:
(1) Does not execute but does generate an interrupt.
75
NEe
"PD70325 (V25Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2 1
0
Bytes
AC
CY
x
x
Flags
V P
S
Z
x
x
CPU Control (cont)
0
POLL
Poll and Wait
0
0
NOP
No Operation
0
0
01
IE~O
0
EI
IE~
0
OSO;OS1;
PS;SS
Segment Override Prefix
0
1
0
0
0
0
0
0
0
0
0
0
sreg
0
Register Bank Switching
MOVSPA
BRKes
MOVSPB
reg16
reg16
0
0
0
0
0
0
0
0
0
2
0
0
3
0
0
0
0
0
0
0
0
1
0
0
0
0
0
3
0
0
reg
TSKSW
reg16
0
3
0
0
reg
76
0
x
x
NEe
pPD70335 (V35 Plus)
16-Bit Microcomputer:
Advanced, High-Speed DMA
Single-Chip, CMOS
NEC Electronics Inc.
Description
The )1PD70335 (V35 Plus) is a high-performance, 16-bit
single-chip microcomputer with a 16-bit external data
bus. The )1PD70335 is fully software compatible with
the )1PD70108/116 (V2~N30®) as well as the )1PD70320/
330 (V25™ N35™). The V35 Plus demonstrates numerous enhancements over its predecessor, the standard
V35; however, it maintains pin compatibility and DRAMdirect bus interface with its predecessor, the V35.
The V35 Plus offers improved DMA transfer rates (over
5M bytes per second), additional serial channel status
flags, improved memory access timing, and enhanced
software control of register bank context switching.
The )1PD70335 has the same complement of internal
peripherals as the V35 and maintains compatibility
with existing drivers; however, some modification of
the DMA drivers may be necessary. The)1PD70335 does
not offer on-chip ROM or EPROM.
Features
o Four multifunction I/O ports
..,- 8-bit analog comparator port
- 20 bidirectional port lines
- 4 input-only port lines
o Two independent full-duplex serial channels
o Priority interrupt controller
- Standard vectored service
- Register bank switching
- Macroservice
o Pseudo-SRAM and DRAM refresh controller
o Two 16-bit timers
o On-chip time base counter
o Programmable wait state generator
o Two standby modes: STOP and HALT
Ordering Information
~
- = - -Clock
---1
Iii:I
iI
(MHz)
Package
Part Number
JiPD70335L-8
L-10
8
o 16-bit CPU and internal data paths
GJ-8
8
o 16-bit non-multiplexed external data path
GJ-10
10
o Direct RAS/CAS DRAM interface
o Functional and pin compatibility with the V35
o Software compatible with )1PD8086
o New and enhanced V-Series instructions
o Minimum instruction cycle 200 ns (at 10 MHz)
o 6-byte prefetch queue
o Two-channel high-speed DMA controller
o Internal 256 bytes RAM memory
DOne 1M-byte memory address space
o Eight internal memory-mapped register banks
V20 and V30 are registered trademarks of NEC Corporation.
V25 and V35 are trademarks of NEC Corporation.
50155-2
84-pin PLCC
10
94-pin plastic QFP
NEe
pPD70335 (V35 'Ius)Pin Configurations
84-PinPLCC
PT7
PO 7 ICLKOUT
PT6
DO
01
72
PT5
02
71
PT4
03
70
PT3
04
69
PT2
05
68
06
67
07
66
08
65
PT1
PTO
P17/REAOY
P16/SCKO
09
64
P15/TOU!..-
010
63
P14/INT/P~
011
62
P1 3/INTP2IINTAK
012
61
P12/1NTP1
013
60
P11/1NTPO
014
59
P10/NMI
015
Ao
A9 /A 1
58
P27 /Hl ORO
57
P26/HlOAK
56
P25~
55
P24/0MAAK1
54
P23/DMAR01
A10/A2
A11 /A 3
co
q-
Cl
q-
Ci 8
Cil >< a:
Q
CD
q-
q-
II)
CD
I'-
co co
I
Cl W
0
~~~~~<.("~~
C\lC')q-II)CDa:
.-
....................
f'o-
««<.("
co
°1&1
a t>
.(
0
~
~
I'q-
~
~
e
0
C\I
Notes:
Q.
oII) II)
....
C\I
II)
C')
II)
i51i! 18 Q
>~~
e~
N
Q.
(1) Pin functions are identical to ~P070330.
(2) IC pins should be tied together and pulled up to V DO with a
10- to 20-k.Q resistor.
(3)
EA must be tied low because IlP070335 does not support Internal
ROM or EPROM.
(4) Pin 9 should be tied to GNO through a pull-down resistor.
83SL-6827B
2
NEe
pPD70335 (V35 Plus)
94-Pin Plastic QFP
POs
A12/A4
NC
NC
A13 /A S
IC
P04
A14 /A 6
P03
A1S/A7
P02
A16 /A a
A17 /A 18
P01
POo
A19
EA
A1a/UBE
MREQ
RxDO
10STB
GND
MSTB
CTSO
AlW
TxDO
REFRQ
RxD1
RESET
CTS1
VOD
TxD1
Voo
P20lDMARQO
X2
IC
X1
VDD
GND
~
GND
P21/DMAAKO
NC
NC
NC
P22ITCO
VrH
Q
C'l ..r- III
~ l- I- I- 0
0
>0 . ~
O:
P20/DMAROO
:;
.....................::
---f:.
P2 1IDMAAKO ~:
::
",Programmable"
P2 2/TCO ~,
DMA
.
P23 /DMAR01 -----.;'
P24/DMAAK1 - (
Controller
:i-j.---
P2S/TC1 - - {......
:~ HLDRO/P2 7
ff'~ READY/P1 7
TxDO ~---{...
RxDO
--t
P1 6 /SCKO - : :
Serial
Interface
Internal ROM
8K Bytes
CTSO.....;:.
?.----.....,
TxD1 - .....
RXD1~:
CTS1
(Reserved)
P13"NTP2I
b' ::-.......
MREO
o· ,:----
IOSTB
}:c: ~B
:i.-
POLUINT/P14
~, '----:-'.:.:.:.:./
P1 0 /NMI
P11"NTPO
P12"NTP1
RESET
HLDAKlP2 6
Instruction Decoder
Micro Sequencer
Programmable
Interrupt
Controller
Micro ROM
.:- EA (Fixed Low
INTAK
Externally)
:::.:.:.,.:.,.,.i
P1 4 /INT'
POLL
X1
X2
P1S /TOUT
REFRO
P07/CLKOUT
PO
P1
P2
PTO·PT7
VTH
VDD
GND
Notes:
(1) The IlPD7033S (V3S Plus) is not a masKed ROM product.
Internal ROM is reserved and not accessible.
(2) Shaded blOCKS are modified from the standard V3S.
83YL-6989B
7
NEe
,.,PD7033S{V3S- Plus)
FUNCTIONAL DESCRIPTION
Architectural Enhancements
The following features enable the J,lPD70335 to perform
high-speed execution of instructions.
• Dual data bus
• 16-/32-bit temporary registers/shifters (TA, TB, TA
TB)
• 16-bit loop counter (lC)
• Program counter (PC) and prefetch pointer (PFP)
• Internal ROM pass bus
+
Dual Data Bus. The J,lPD70335 has two internal 16-bit
data buses: the main data bus and a subdata bus. This
reduces the processing time required for addition/
subtraction and logical comparison instructions by
one-third over single-bus systems. The dual data bus
method allows two operands to be fetched simultaneously from general-purpose registers and transferred to the AlU.
memory space. They are grouped in a 512-byte block
called the internal data area (IDA). The 256-byte internal RAM is also in the IDA. The addresses of the register
are given as offsets into the IDA. The start address of
the IDA is set by the Internal Data Area Base register
(IDB), and may be programmed to any 4K boundary in
the memory address space.
Register Banks. Because the general-purpose register
set is in internal RAM, it is possible to have multiple
ba~ks of registers. The J,lPD70335 CPU supports up to a
register banks. A bit field in the PSW selects which bank
is currently being used. Each bank contains the entire
CPU register set plus additional information needed
for context switching. Register banks may be switched
using special instructions (TSKSW, BRKCS, MOVSPA,
M
OS1
OS1
PS
PS
PS
PS
SS
SS
S8
SS
OS1
OSO
080
OSO
Save PC
Save PC
Save PC
Save PSW
Save PSW
Save
Vector PC
Vector PC
Reserved
Reserved
Vector PC
Reserved
~I
~
PC
PSW
I
I
psw
'.
OS1
OSO
f--l
PC
.J+-
Save PC
rY
l~
SavePSW
psw
RB
L
Reg 16
Vector PC
Reserved
RB Register bank
field
-e822A
83SL-e823A
MACROSERVICE FUNCTION
The macroservice function (MSF) is a special microprogram that acts as an internal DMA controller between
bn-chip peripherals (special-function registers, SFR)
and memory. The MSF greatly reduces the software
overhead and CPU time that other' processors would
require for register save processing, register returns,
and other handling assoCiated with interrupt processing.
If the MSF is selected for a particular interrupt, each
time the request is received, a byte or word of data will
be transferred between the SFR and memory without
interrupting the CPU. Each time a request occurs, the
macroservice - counter is' decremented. .When the
counter reaches zero, an interrupt to the CPU is generated. The MSF also has a character search option.
When selected, every byte transferred will be compared to an 8-bit search character and an interrupt will
be generated if a match occurs or if the macroservice
counter counts out.
18
NEe
pPD7033S (V3S Plus)
Like the NMI, INT, and INTTB,the two DMA controller
interrupts (INTOO, INTD1) and the serial error interrupts
(INTSERO, INTSER1) do not have MSF capability.
There are eight, 8-byte macroservice channels mapped
into internal RAM from XXEOOH to XXE3FH. Figure 11
shows the components of each channel.
Setting the macroservice mode for a given interrupt
requires programming the corresponding macroservice control register. Each individual interrupt serviceable with the MSF has its own associated MSC specialfunction register. The general format for all MSC
registers is shown in figure 12.
Figure 11.
/IIacroservice Channels
a
15
+7H
IMSM21 MSM1 I MSMo I
DIR
0
CH2
CH1
I CHo I
0
7
MSM2- MSM o
Macroservice Mode
000
001
1 00
Normal (8-bit transfer)
Normal (16-bit transfer)
Character search (8-bit transfer
Other combinations are not allowed.
Data Transfer Direction
DIR
Memory to SFR
SFR to memory
0
1
Macroservice Channel
CH2-CHO
o
7
Figure 12. /IIacroservice Control Registers
(/liSe)
000
Channel 0
111
Channel 7
~
MSS
MSP
Reserved
SCHR
SFRP
MSC
TIMER UNIT
MSS
+6H
Segment value of memory address used
for data transfer. Memory address
will be MSS x 16 + MSP.
The ~P070335 (figure 13) has two programmable 16-bit
interval timers (TMO, TM1) on-chip, each with variable
input clock frequencies. Each of the two 16-bit timer
registers has an associated 16-bit modulus register
(MOO, MD1). Timer
operates in either the interval
timer mode or one-shot mode; timer 1 has only the
interval timer mode.
MSP
+4H
Offset value of memory address used
for data transfer.
Interval Timer Mode
SCHR
+2H
a·blt data compared In character search.
SFRP
+1H
Offset value of special function register
address, which Is xxFOOH + SFRP. (xx Is
specified by lOB register).
MSC
+OH
Number of transfers performed In
macro service
r
+OH
Offset from macro service channel start address.
°
83M·005285A
In this mode, TMOfTM1 are decremented by the selected input clock and, after counting out, the registers
are automatically reloaded from the modulus registers
and counting continues. Each time TM1 counts out,
interrupts are generated through TF1 and TF2 (Timer
Flags 1, 2). When TMO counts out, an interrupt is
generated through TFO. The timer-out signal can be
used as a square-wave output whose half-cycle is equal
to the count time.
Two input clocks derived from the system clock ~re
SCLK/6 and SCLK/128. Typical timer values shown
below are based on fosc = 10 MHz and fSCLK = foscl2.
Clock
SCLK/6
SCLK/128
Timer Resolution
1.2J1s
25.6~s
Full Count
78.643 ms
1.678 s
19
..
Ii.i.i
NEC
pPD7033S (V3S Plus)
One-Shot Mode
Figure 14. Timer Control RegisterO. (TIfCO)
In the one-shot mode, TMO and MDO operate as independent one-shot timers. Starting with a preset value,
each is decremented to zero. At zero, counting ceases
and an interrupt is generated by TFO (from TMO) or TF1
(from MDO).
I TSO ITClKO I MSO I MClKO I ENTO·I AlV I MOD1 MODo I
When TMO is programmed to one-shot mode, TM1 may
still operate in interval mode.
Two input clocks derived from the system clock are
SCLK/12 and SCLK/128. Typical timer values shown
below are based on fosc = 10 MHz and fSClK = fosc/2.
Clock
SCLK/12
SCLK/128
Timer Resolution
2.4 Jis
25.6Jis
Full Count
157.283 ms
1.678 s
I
7
0
TSO
Timer 0 in Either Mode
0
1
Stop countdown
Start countdown
MOD 1
MODo
0
0
0
0
0
0
1
TClKO
TMO Register Clock Frequency
0
1
0
1
fSCLKl6 (Interval)
fSCLKl128 (Interval)
fSCLKl12 (One-shot)
fSCLKl128 (One-shot)
MSO
MOO Register Countdown
(One-Shot Mode)
0
1
Stop
Start
MClKO
Timer Control Registers
Setting the desired timer mode requires programming
the timer control register. See figures 14 and 15 for
format.
MOO Register Clock Frequency
0
1
fSCLKl1;2
fSCLKl128
ENTO
TOUT Square-Wave Output
0
1
Figure 13. Timer Unit Block Diagram
Disable
Enable
AlV
TOUT Initial level
(Counter Stopped)
low
High
0
I
fSCLK
:divlded bY~
12:~
MOD 1
MODo
Timer Unit Mode
0
0
0
1
X
Interval timer
One-shot
Reserved
.......;....:.---,
Figure 15.
12
128
I1S1 ITClK1 I
L---I"""'"......T-i---'"
o
TClK1
o
I
t-----oTO
I
---------~-----------------
r
Internal Bus
}
83SL-6746A
20
o
0
o
7
TS1
V
Timer Control Register 1 (TIfCI)
o
o
o
o
I
Timer 1 Countdown
Stop
Start
Timer 1 Clock Frequency
fSCLKl6
fscLKl128
TIME BASE COUNTER
The 20-bit free-running time base counter (TBC) controls internal timing sequences and is available as the
source of periodic interrupts at lengthy intervals. One
of four interrupt periods can be selected by programming the TBo and TB1 bits in the processor control
register (PRC). The TBC interrupt is unlike the others
NEe
IIPD70335 (V35 Plus)
because it is fixed as a level 7 vectored interrupt.
Macroservice and register bank switching cannot be
used to service this interrupt. See figures 16 and 17.
Figure 16.
Figure 18.
~-E
Time Base Interrupt Request
Control Register (TBIC)
I TBF I TBMK I
0
0
0
1
I
o
Address xxFECH
7
Time Base Counter (TBC) Block
Diagram
I I I I
+210
+ 2 13
+216
+220
83NR-7450A
Time Base Interrupt Flag
TBF
o
REFRESH CONTROLLER
1
No interrupt generated
Interrupt generated
TBMK
Time Base Interrupt Mask
o
The JlPD70335 has an on-Chip refresh controller for
dynamic and pseudostatic RAM mass storage memories. The refresh controller generates refresh addresses
and refresh pulses. It inserts refresh cycles between the
normal CPU bus cycles accordi ng to refresh specifications.
Unmasked
Masked
Figure 17. Processor Control Register (PRC)
I
0
IRAMENI
0
7
o
I TB1
I
TBo
I PCK1
I
pCKo
Address xxFEBH
RAMEN
I
o
Built-In RAM
0
Disable
Enable
1
TB1
TBo
0
0
0
1
0
1
1
PCK1
PCKo
0
0
0
1
0
1
Time Base Interrupt Period
21 O/fscLK
2 13/fSCLK
2 16/fSCLK
22O/fSCLK
System Clock Frequency
(fsCLId
foscl2
foscl4
foscl8
Reserved
The RAMEN bit in the PRC register allows the internal
RAM to be removed from the memory address space to
implement faster instruction execution.
The TBC (figure 18) uses the system clock as the input
frequency. The system clock can be changed by programming the PCKo and PCK1 bits in the processor
control register (PRC). Reset initializes the system
clock to foscl8 (fosc = external oscillator frequency).
The refresh controller outputs a 9-bit refresh address on _
address bits Ao-As during the refresh bus cycle. Address ~
bits A9-A19 are all zeros. The 9-bit refresh address is
automatically incremented at every refresh timing for
512 row addresses. The 8-bit refresh mode (RFM) register (figure 19) specifies the refresh operation and
allows refresh duri ng both CPU HALT and HOLD
modes. Refresh oycles are automatically timed to minimize the effect on system throughput.
The following shows the REFRQ pin level in relation to
bits 4 (RFEN) and 7 (RFLV) of the refresh mode register.
RFEN
-0--
o
1
1
RFLV
-0-1
REFRQ Level
o
1
o
o
1
Refresh pulse output
It should be noted that since the V35 Plus directly
supports dynamic RAM memory, the refresh controller
output should be gated into the RAS input of the
memory chips. When combined with the chip select
logic and the MREQ Signals, a direct DRAM interface is
supported.
SERIAL CONTROL UNIT
The JlPD70335 has two full-duplex UARTs, channel 0
and channel 1. Each serial port channel (figure 20) has
a transmit line TxDn, a receive line RxDn, and a clearto-send input line CTSn for handshaking. Communication is synchronized by a start bit, and the ports can be
programmed for even, odd, or no parity, character
lengths of 7 or 8 bits, and 1 or 2 stop bits.
21
NEe
pPD70335 (V3S Plus)
Figure 19. Refresh Mode Register (RFM)
IRFLV IHLDRF IHLTRF I RFEN I RFW1 I RFWo I RFT1
7
Bx G =
RFTo
Address xxFE1 H
RFLV
RFEN
0
1
0
1
0
0
1
I
0
REFRQ Output Signal Level
0
1
0
Refresh pulse
Automatic Refresh Cycle in HOLD Mode
HLDRF
Disabled
Enabled
0
1
Automatic Refresh Cycle In HALT Mode
HLTRF
0
Disabled
Enabled
Automatic Refresh Cycle
RFEN
0
1
Refresh pin = RFLV
Refresh enabled
RFW1
RFWo
0
0
1
1
0
1
0
1
RFT1
RFTo
0
0
1
1
0
1
0
1
No. of Wait States Inserted In Refresh Cycle
0
1
2
2
Refresh Period
16/SCLK
32/SCLK
64/SCLK
128/SCLK
The JlPD70335 has dedicated baud rate generators for
each serial channel. This eliminates the need to obligate the on-chip timers. The baud rate generator allows
a wide range of data transfer rates up to 1.25 Mb/s. This
includes all of the standard baud rates without being
restricted by the value of the particular external crystal.
Each baud rate generator has an 8-bit baud rate generator register BRGM, which functions as a prescalerto
a programmable input clock selected by the serial
communication control register SCCn. Together these
must be set to generate a frequency equivalent to the
desired baud rate.
The baud rate generator can be set to obtain the
desired transmission rate according to the following
formula.
22
SCLK x 106
2n +1
where B = baud rate
G = Baud rate genrator register BRGn value
(table 4)
n = input clock specification (n between 0
and 8). This is the value that is loaded into
the SCCn register. See figure 21.
SCLK = system clock frequency (MHz).
Based on the above expression, table 4 shows the baud
rate generator values used to obtain standard transmission rates when SCLK = 8 MHz.
Tab/e4.
Baud Rate Generator Register (BRGn)
Baud Rate
n
G
Error (%)
110
7
142
0.03
300
6
208
0.16
1200
4
208
0.16
2400
3
208
0.16
4800
2
208
0.16
208
0.16
0.16
9600
19,200
0
208
38,400
0
104
0.16
1.00M
0
4
0.00
NEe
pPD7033S (V3S Plus)
Figure 20. Serial Interface Block Diagram
Channel 0
TXDO~
Serial
Register
~
TxBO
o----t>-1
Serial
Register
~
RxBO
RxDO
~
F=>
CTSO
Channel 1
RxD1
o----t>-1
Serial
Register
Serial
Register
Please refer to the V25N35 User's Manual for additional
information on the serial channels.
Figure 21. Serial Communication Control
Register (SCCn)
7
6
5
4
0
0
0
0
PRS 3-PRS o
SCKO~--------------'---~
TXD1~
software to poll for the completion of a message (the
last bit of the last byte is shifted out when the ALL SENT
bit is set). All error flags are available in this register
(refer to figure 24).
~
TxB1
~
RxB1
~
F=>
n
I PRS3
0 0
000 1
00 1 0
0
1
2
SCLK/2
SCLK/4
SCLK/8
o0 1 1
o1 0 0
o1 o1
o1 10
o1 1 1
3
4
5
SCLK/16
SCLK/32
SCLK/64
6
7
8
SCLK/128
SCLK/256
SCLK/512
Combinations after
PRS
PRS2
0
PRS1
PRSol
Input Clock for Baud Generator
o0
1 000
2
3
II
= 1000 are not valid.
CTS1
In addition to the asynchronous mode, channel 0 has a
synchronous I/O interface mode. In this mode, each bit
of data transferred is synchronized to a serial clock
SCKO. This is the same as the NEC /lCOM75 and
/lCOM87 series, and allows easy interfacing to these
devices.
Figures 22 and 23 show the serial communication
mode register SCMn and error register SCEn.
The serial control unit of the /lPD70335 is functionally
identical to that of the standard V35, with the exception
of several enhanced features.
All serial status information is moved to the serial
status register (SSTn) on the V35 Plus. Included in this
register is an additional flag which signals that the
transmit shift register is clear of data. This flag allows
23
NEe
pPD70335 (V35 Plus)
Figure 23. Serial Communication Error
Registers (SCEn)
Figure 22. Serial Communication Mode
Registers (SCMn)
7
6
5
4
3
o
2
7
I RxD
RxD
TxRDY
o
Transmitter Control
0
1
Disable
Enable
1
RxE
o
ERP
Receiver Control
0
Disable
Enable
1
ERF
Parity Control
00
o1
1 0
1 1
CL/TSK
o
No parity
o parity (0 during transmit; ignored during
receive)
SlJRSCK
Odd parity
Even parity
Character Length/Transmit Shift Clock (I/O
interface mode only)
o
Stop Bit Length/Receive Clock
mode only)
2 stop bits/Internal clock (output on CTSO)
Mode
00
o1
1
24
(110 interface
1 stop bit/External clock (input on CTSO)
1
x
I/O interface (Channel 0 only)
Asynchronous
Reserved
ERO
0
7 bits/No effect
8 bits/Trigger transmit
1
0
1
6
5
4
3
2
0
0
0
0
ERP
RxD Line Status
RxD line
RxD line
=
=
0
1
Parity Error
No parity error
Parity error has occurred
Framing Error
No framing error
Stop bit not detected
Overrun Error Flag
No overrun
Overrun has occurred
0
ERF
I ERO I
1ttIEC
pPD70335 (V3S Plus)
Figure 24. Serial Status Register (SSTn)
IRxDN I ASn ITxBEn IRxBFn I
0
ERPn
ERFn
I EROn I
Parity Error Flag
o
7
ERPn
Indicates that transmit parity was not consistent
with receive parity (Note 5)
Framing Error Flag
Receive Terminal Pin State
RxON
ERFn
Indicates that stop bit was not detected (Note 5)
Input state of RxDn pin is checked by RxDN bit
Overrun Error Flag
All Sent Flag
ASn
Reset when transmit data has been written to
transm it shifter
o
EROn
Indicates that succeec!ing receive has completed
before the previous receive data is taken over from
the receive buffer (Note 5)
Set when all the data in the transmit buffer and
transmit shift register has been sent (Note 1)
Notes:
Transmit Buffer Empty Flag
TxBEn
Reset when transmit data has been written to
transmit buffer (Note 1)
o
Set when transmit data in transmit buffer has
been sent to shift register
(1) Transmitterflags are reset to 1 when the value of either the baud
rate generator or serial control register is written.
(2) Receive buffer full flag is also reset when either the baud rate
generator or serial control register is written.
(3) Receive buffer full flag is not related to the receive error state.
Receive Buffer Full Flag
Reset when receive data has been read from
receive buffer (Note 2)
RxBFn
(4) Error flags are cleared when the next data byte is received.
~_
o
(5) In the table, n = 0 or 1.
~
Set when receive data has been sent from shift
register to receive buffer (Note 3)
Table 5. DMA Controller Operation
Single-Step Mode
Burst'Mode
Single-Transfer Mode
Demand Release Mode
Transm ission
coverage
Memory - memory
Memory - memory
Memory -I/O
Memory -I/O
Function
Under one time of DMA
request instruction,
one bus cycle and one DMA
transmission are alternately
executed the specified
number of times.
Under one DMA
request, specified number
of DMA transmissions
are executed.
One DMA transfer is
executed every time DMA
request occurs.
DMA transmission is executed
while DMARa terminal is kept
high-level.
DMA start
Rise of DMARa
Rise of DMARa
Rise of DMARa
High level of DMARa
Setting TDMA bit of DMA
control register
Setting TDMA bit of DMA
control register
Depends on software
None
Depends on software
Halted at low level of DMARa
during DMA transmission
Terminal count
decremented from zero
Terminal count
decremented from zero
Terminal count
decremented from zero
Terminal count
decremented from zero
Interrupt
All accepted
Not accepted
during DMA transmission
All accepted
All accepted except
during DMA transmission
During halt
Specified times of DMA
transmission are executed
consecutively
Specified number of DMA
transfers are executed
consecutively
Active
Active
DMA request
during DMA
transmission
DMA at channel 1 is retained
while DMA at channel 0 is
executed
Other DMA is retained until
DMA transmission
is terminated.
DMA transmission under
request is executed after one
DMA transmission is over
DMA at channel 1 is retained
while DMA at channel 0 is
executed.
Halt method
25
NEe
pPD70335 (V35 Plus)
DMA CONTROLLER
Two memory-to-memory transfer modes (single-step
and burst) are supported as well as two I/O-to-memory
modes (single-transfer and demand release). Refer to
table 5.
Figure 26. DIIIA Channellllode Registers
(DIIIAllln)
1
MD2
1
MD1
1
MDo
W
1
1
EDMA
1
The most significant V35 Plus enhancement boosts the
transfer rates of the dual internal DMA channels to full
bus bandwidth. All operational modes remain the same
as the V35, but since the V35 Plus DMA controller is
implemented in hard-wired logic, the control delays of
a microprogrammed method are not present. As a
result, the demand release mode transfer rate boasts a
theoretical transfer rate of over 6M bytes per second.
MD2-MD o
The ,uPD70335 DMA control registers are moved from
the internal RAM to the SFR area; thus the V35 Plus may
effectively have a larger internal RAM memory area
than comparable designs on the standard V35.
W
Transfer Method
0
Byte transfer
Word transfer
Additionally, the ,uPD70335 DMA controller uses linear
registers for both source and destination address
pointers. Thus, three a-bit registers completely specify
the DMA address pointers as shown in figure 25. These
pointers may be updated by byte (±1) or word (±2)
quantities as programmed in the DMA channel mode
register shown in figure 26. This register also specifies
the operational mode of the channel. The EDMA bit is
c;lutomatically cleared when terminal count is reached,
and DMA requests are ignored when this bit is cleared.
0
1
20 19
f--
16 15
1
0
o
o
1
Transfer Mode
000
001
010
011
Single-step (memory to memory)
Demand release (I/O to memory)
Demand release (memory to I/O)
Disabled
100
101
110
111
Burst (memory to memory)
Single-transfer (I/O to memory)
Single-transfer (memory to I/O)
Disabled
TDMA
EDMA
Transfer Condition
o
o
Disabled
DMA channel enabled
Software initiate DMA (memory to
memory modes)
The TDMA bit is only valid for single-step and burst
modes. This bit allows software iriitiation of the DMA
transfer (provided the EDMA bit is set); the bit always
reads as zero and .has no meaning in the demandrelease or single-transfer modes.
The DMA address pointers may be incremented or
decremented per transfer as specified in the DMA
address update register shown in figure 27. The address pointer can also be programmed to remain the
same, allowing repeated transfers to or from a location.
Figure 25. DIIIA Address Registers
23
TDMA
7
8 7
Applied addresses (20 bits)
Figure 27.
-l
n =0,1
83YL-6715A
o
.1
0
DIIIA Address Control Registers
(DIIIAC)
1
PD 1
1
PDo
0
0
pS 1
pSo
I
o
7
Destination Address Offset
00
01
10
11
No modification
Increment
Decrement
No modification
Source Address Offset
00
01
10
11
No modification
Increment
Decrement
No modification
The DMAAKn Signals are not output for memory-tomemory transfer modes, but are driven low for each
transfer I/O to/from memory. Nominal DMA bus cycles
26
NEe
pPD70335 (V35 Plus)
are three clock states; however, programmable wait
states may be added. Wait states for memory-tomemory transfers are added to both source and destination addresses as programmed for each specific
address.
During memory-to-I/O transfers, the number of wait
states inserted is determined by the slower of the
source and destination. IIO-to-memory transfers add
the number of wait states required by the memory write
address.
PARALLEL I/O PORTS
Figure 30.
Port Mode Control Register 0 (PMCO)
I
I
PMC0
71
Use the associated port mode and port mode control
registers to select the mode for a given I/O line.
PMC1 7
0
1
PMC16
0
1
PMC15
0
1
Figure 28. Por,t Mode Registers 0 and 2 (pM01
PM2)
PMC13
0
1
0
1
PMC12
o
7
x
0
Input or Output Bit Selection
PMC1 1
Output port mode
Input port mode
x
PMC10
n = 7 through 0
x
Figure 29. Port Mode Register 1 (PMI)
PM17
I
PM16
I
PM15
I
PM14
I
I
o
o
I I
o
Port mode
CLKOUT
0
Port/Control Bit Selection
P171/0
READY input
Port/Control Bit Selection
P161/O
SCKO output
a
Port/Control Bit Selection
P1 5 1/0
TOUT output
Port/Control Bit Selection
P14 I/O or POLL input
INT input
Port/Control Bit Selection
INTP2/P13 input
INTAK output
Port/Control Bit Selection
INTP1/P12 input
INTP2/P13 input
Port/Control Bit Selection
INTPO/P11 input
Port/Control Bit Selection
NMI/P1 o input
I
o
7
PMC1 n
I
Figure 31. Port Mode Control Register 1 (PMCI)
PMC14
I
I
Port or Control Bit Selection
o
The analog comparator port (PT) compares each input
line to a reference voltage. The reference voltage is
programmable to be the (VTH input pin) x n/16, where n
= 1 to 16. See figure 33.
1
I
7
The J1PD70335 has three 8-bit parallel I/O ports: PO, P1,
and P2. Refer to figures 28 through 32. Special function
register (SFR) locations can access these ports. The.
port lines are individually programmable as inputs or
outputs. Many of the port lines have dual functions as
port or control lines.
o
I
7
PM1 n
o
1
Port Mode Input/Output (Port P1 n)
Output port mode
Input port mode
n = 7, 6, 5, or 4.
27
NEe
pPD70335 (V35 Plus)
Figure 32. Port Mode Control Register 2 (PMC2)
7
0
Port/Control Bit Selection
o
I/O port
1
HLDRQ output
o
I/O port
1
HLDAK input
Port/Control Bit Selection
PMC2s
o
I/O port
TC1 output
1
The appropriate bits in the wait control word (WTe)
control wait state generation. Programming the upper
two bits in the wait control word will set the wait state
conditions for the entire I/O address space. Figure 34
shows the memory map for programmable wait state
generation; see figure 35 for a graphic representation
of the wait control word.
Port/Control Bit Selection
o
I/O port
1
DMAAKI output
Port/Control Bit Selection
o
I/O port
DMARQ1 .input
1
Port/Control Bit Selection
x
Figure 34. Programmable Wait State Generation
I/O port
TCO output
o
You can generate wait states internally to further reduce the necessity for external hardware. ·Insertion of
these wait states allows direct interface to devices
whose access times cannot meet the CPU read/write
timing requirements.
When using this function, the entire 1M-byte memory
address space is divided into 128K-blocks. Each block
can be programmed for zero, one, or two wait states, or
two plus those added by the external READY signal.
The top two blocks are programmed together as one
unit.
Port/Control Bit Selection
PMC26
PROGRAMMABLE WAIT STATE GENERATION
FFFFFH
Port/Control Bit Selection
256K
x
I/O port
1
DMAAKO outp~t
COOOOH
Port/Control Bit Selection
PMC20
I/O port
1
DMARQO input
. 40000H
128K
Figure 33. Port T Mode Register (PMT)
I
0
I
0
I
0
I
0
I PMT3 I PMT2 I PMT1
7
0100
0101
0110
0111
1000
1001
1010
1 01 1
1100
1 101
1110
1111
28
20000H
PMTol
128K
OH
0
PMT3-PMTO
0000
0001
0010
0011
VTH
VTH
VTH
VTH
~~
~~
o
x 16/16
x 1/16
x 2/16
x 3/16
VTH x 4/16
VTH x 5/16
VTH x 6/16
VTH x 7/16
VTH x 8/16
VTH x 9/16
VTH x 10/16
VTH x 11/16
VTH x 12/16
VTH x 13/16
VTH x 14/16
VTH x 15/16
83NR-7451A
STANDBY MODES
The two low-power standby modes are HALT and STOP.
Software can cause the processor to enter either mode.
HALT Mode
In the HALT mode, the CPU is inactive and the chip
consumes much less power than when operational.
The external oscillator remains functional and all peripherals are active. Internal status and output port line
conditions are maintained. Any unmasked interrupt
can release this mode. In the EI state, interrupts subsequently wi II be serviced and the HALT state released.
In the 01 state, program execution is restarted with the
instruction following the HALT instruction and the
interrupt causing the release from HALT will be latched.
NEe
STOP Mode
pPD7033S (V3S Plus)
Figure 35.
The STOP mode allows the largest power reduction
while maintaining RAM. The oscillator is stopped, halting the CPU and all internal peripherals. Internal status
and port pin outputs are maintained. Only a RESET or
NMI can release this mode.
A standby flag in the STBC register is reset by rises in
the supply voltage. Its status is maintained during
normal operation and standby. The STBC register (figure 36) is not initialized by RESET. Use the standby flag
to determine whether program execution is returning
from standby or from a cold start by setting this flag
before entering the STOP mode.
SPECIAL-FUNCTION REGISTERS
Table 6 shows the special-function register mnemonic,
type, address, reset value, and function. The eight
high-order bits of each address (xx) are specified by
the lOB register.
SFR area addresses not listed in table 6 are reserved. If
read, the contents of these addresses are undefi ned,
and any write operation will be meaningless.
Wait Control Word (WTC)
7
Wait Control, High
o
7
Wait ContrOl, Low
o
Wait States
o
Block n1
Block nO
o
o
o
o
2
2 or more (control from
READY pin)
n = 0 thru 6
Figure 36. Standby Register (STBC)
I~_~~I_o~l_o~l__o_l~o~l_o~l__o~l_s_:F~I~
Standby Flag
SBF
o
No changes in Voo (standby)
Rising edge on VOO (cold start)
1
Table 6. Special-Function Registers
Address
Register Function
Symbol
R/W
Manipulation (Note 6)
xxFOOH
Port 0
PO
R/W
8/1
Undefined
xxF01H
Port mode 0
PMO
w
8
OFFH
When Reset
xxF02H
Port mode control 0
PMCO
w
8
OOH
xxF08H
Port 1
P1
R/W
8/1
Undefined
xxF09H
Port mode 1
PM1
OFFH
Port mode control 1
PMC1
w
w
8
xxFOAH
8
OOH
xxF10H
Port 2
P2
R/W
8/1
Undefined
xxF11H
Port mode 2
PM2
8
OFFH
8
OOH
xxF12H
Port mode control 2
PMC2
w
w
xxF38H
Threshold port
PT
R
8
Undefined
xxF3BH
Threshold port mode
PMT
R/W
8/1
OOH
xxF40H
External interrupt mode
INTM
R/W
8/1
OOH
xxF44H
External interrupt macro service control 0 (Note 1)
EMSO
R/W
8/1
Unde'fined
xxF45H
External interrupt macro service control 1,(Note 1)
EMS1
R/W
8/1
xxF46H
External interrupt macro service control 2 (Note 1)
EMS2
R/W
8/1
xxF4CH
External interrupt request control 0 (Note 1)
EXICO
R/W
8/1
xxF4DH
External interrupt request control 1 (Note 1)
EXIC1
R/W
8/1
xxF4EH
External interrupt request control 2 (Note 1)
EXIC2
R/W
8/1
47H
29
NEe
pPD70335 (V3S Plus)
Table 6.
Special-Function Registers (cont)
Address
Register Function
Symbol
R/W
Mani pulation (Note 6)
When Reset
xxF60H
Receive buffer 0
RxBO
R
8
Undefined
xxF62H
Transmit buffer 0
TxBO
W
8
xxF65H
Serial receive macro service control 0 (Note 1)
SRMSO
R/W
8/1
xxF66H
Serial transmit macro service control 0 (Note 1)
STMSO
R/W
8/1
xxF68H
Serial mode register 0
SCMO
RIW
8/1
xxF69H
Serial control register 0
SCCO
R/W
8/1
OOH
xxF6AH
Baud rate generator 0
BRGO
R/W
8/1
xxF6BH
Serial status register 0
SSTO
R
8
60H
xxF6CH
Serial error interrupt request register 0 (Note 1)
SEICO
R/W
8/1
47H
xxF6DH
Serial receive interrupt request register 0 (Note 1)
SRICO
R/W
8/1
xxF6EH
Serial transmit interrupt request register 0 (Note 1)
STICO
R/W
8/1
xxF70H
Serial receive buffer 1
RxB1
R
8
xxF72H
Serial transmit buffer 1
TxB1
W
8
xxF75H
Serial receive m'acro service register 1 (Note 1)
SRMS1
R/W
8/1
xxF76H
Serial transmit macro service register 1 (Note 1)
STMS1
R/W
8/1
xxF78H
Serial communication register 1
SCM1
R/W
8/1
xxF79H
Serial control register 1
SCCt
R/W
8/1
Undefined
OOH
xxF7AH
Baud rate generator 1
BRG1
RIW
8/1
xxF7BH
Serial status register 1
SCS1
R
8
60H
xxF7CH
Serial error interrupt request register I (Note 1)
SEIC1
R/W
8/1
47H
xxF7DH
Serial receive interrupt request register 1 (Note 1)
SRIC1
R/W
8/1
xxF7EH
Serial transmit interrupt request register 1 (Note 1)
STIC1
RIW
8/1
xxF80H
Timer register 0 (Note 2)
TMO
R/W
16
xxF82H
Timer 0 modulo register (Note 2)
MOO
R/W
16
xxF88H
Timer register 1 (Note 2)
TM1
R/W
16
Undefined
xxF8AH
Timer 1 modulo register (Note 2)
M01
R/W
16
xxF90H
Timer 0 control register (Note 2)
TMCO
R/W
8/1
xxF91H
Timer 1 control register (Note 2)
TMC1
R/W
8/1
xxF94H
Timer unit 0 macro service register (Note 1)
TMMSO
RIW
8/1
xxF95H
Timer unit 1 macro service register (Note 1)
TMMS1
R/W
8/1
xxF96H
Timer unit 2 macro service register (Note 1)
TMMS2
R/W
8/1
xxF9CH
Timer unit 0 interrupt request register (Note 1)
TMICO
R/W
8/1
xxF9DH
Timer unit 1 interrupt request register (Note 1)
TMIC1
R/W
8/1
xxF9EH
Timer unit 2 interrupt request register (Note 1)
TMIC2
RIW
8/1
xxFAOH
DMA address update control register 0
DMACO
R/W
8/1
Undefined
xxFA1H
DMA mode register 0
DMAMO
RIW
8/1
47H
xxFA2H
DMA address update control register 1
DMAC1
R/W
8/1
Undefined
xxFA3H
DMA mode register 1
DMAM1
R/W
8/1
OOH
47H
xxFACH
DMA interrupt request control register 0 (Note 1)
DICO
R/W
8/1
xxFAOH
DMA interrupt request control register 1 (Note 1)
DIC1
R/W
8/1
30
OOH
Undefined
47H
NEe
pPD7033S (V3S Plus)
Table 6. Special-Function Registers (cont)
Address
Register Function
Symbol
R/W
Manipulation (Note 6)
When Reset
xxFCOH
DMA channel 0 source address pointer low
SAEOL
R/W
16/8
Undefined
xxFC1H
DMA channel 0 source address pointer mid
SAEOM
R/W
16/8
xxFCOH
DMA Channel 0 source address pointer low
SAEOL
R/W
16/8
xxFC1H
DMA channel 0 source address pointer mid
SAEOM
R/W
16/8
xxFC2H
DMA channel 0 source address pointer high
SAROH
R/W
8
xxFC4H
DMA channel 0 destination address pointer low
DAROL
R/W
16/8
xxFC5H
DMA channel 0 destination address pointer mid
DAROM
R/W
16/8
xxFC6H
DMA channel 0 destination address pointer high
DAROH
R/W
8
xxFC8H
DMA channel 0 count register
DMATCO
R/W
16/8
xxFDOH
DMA channel 1 source address pointer low
SAR1L
R/W
16/8
xxFD1H
DMA channel 1 source address pointer mid
SAR1M
R/W
16/8
xxFD2H
DMA channel 1 source address pointer high
SAR1H
R/W
8
16/8
xxFD4H
DMA channel 1· destination address pointer low
DAR1L
R/W
xxFD5H
DMA channel 1 destination address pointer mid
DAR1M
R/W
16/8
xxFD6H
DMA channel 1 destination address pointer high
DAR1H
R/W
8
xxFD8H
DMA channel 1 terminal count register
DMATC1
R/W
16/8
xxFEOH
Standby control register
STBC
R/W
(Note 3)
8/1
Undefined
(Note 4)
xxFE1H
Refresh mode register
RFM
R/W
8/1
OFCH
xxFE8H
Wait state control
WTC
R/W
16/8
OFFFFH
xxFEAH
User flag (Note 5)
FLAG
R/W
8/1
OOH
xxFEBH
Processor control register
PRC
R/W
8/1
4EH
xxFECH
Time base interrupt request control register
(Note 1)
TBIC
R/W
8/1
47H
xxFEFH
Interrupt factor register (Note 1)
IROS
R
8
Undefined
xxFFCH
Interrupt priority control register (Note 1)
ISPR
R
8
OOH
xxFFFH
Internal data area base
IDB
R/W
8/1
OFFH
Notes:
= OOH;
= no change.
(1) One wait state is inserted into accesses to these registers.
(4) Upon power-on reset
(2) A maximum of 6 wait states are added into accesses to these
registers.
(5) For the user flag register (FLAG), manipulating bits other than
bits 3 and 5 is meaningless. The contents of user flags 0 and 1 (FO
and F1) of the FLAG register are affected by manipulating FO and
F1 of the PSW
(3) Each bit of the standby control register can be set to 1 by an
instruction; however, once set, bits cannot be reset to 0 by an
instruction (only 1 can be written to this register).
other
(6) The manipulation column indicates which memory operations
can read or modify the register according to the following key.
16
8
Word operations
Byte operations
Bit operations
31
m
NEe
pPD70335 (V35 Plus)
Comparator Characteristics
= + 5 V ±10%; TA = -10 to + 70°C
ELECTRICAL SPECIFICATIONS
Voo
Note: The de and ac characteristics specified in this data
sheet are for 8-MHz parts (lJPD70335-8). The specifications for 10-MHz parts (J./PD70335-10) are in a separate
publication.
Parameter
Symbol
Accuracy
VACOMP
Threshold voltage
Min
Max
Unit
±100
mV
VTH
0
VOO + 0.1
V
Absolute Maximum Ratings
Comparison time
tCOMP
64
65
tCYK
TA
PT input voltage
VIPT
0
VOO
V
= 25°C
-0.5 to +7.0 V
Supply voltage, Voo
Input voltage, VI
-0.5 to Voo + 0.5 V (::; + 7.0 V)
Output voltage, Vo
-0.5 to Voo + 0.5 V (::; + 7.0 V)
Threshold voltage, VT H
-0.5 to Voo + 0.5 V (::; + 7.0 V)
Output current, low; IOL
Each output pin
Total
4.0 rnA
SOmA
Output current, high; IOH
-2.0 rnA
-20 rnA
Operating temperature range, TOPT
-10 to +70°C
Storage temperature range, TSTG
-65 to +150°C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage.
Supply Current VB Clock Frequency
120
-
~
I- TA = 25°C
Voo =5V
I-Typical Sample
i~fs~
100
1c 80
c
60
40
.--
--
.-- ~
-- --
..- .......
3
= OV; TA = 25°C
Parameter
Min
Symbol
Max Unit Conditions
Input capacitance
CI
10
pF
Output capacitance
Co
20
pF
I/O capacitance
CIO
20
pF
4
voo
fc = 1 MHz;
unmeasured pins
returned to 0 V
= +5V ±10%; TA = -10to +70°C (Note.1)
Parameter
5
6
fSCLK(MHz)
7
8
9
10
83NR·7427A
Symbol
Min
Typ Max Unit Conditions
Supply current,
operating
1001
65
120
rnA
Supply current,
HALT mode
1002
25
50
rnA
Supply current,
STOP mode
1003
10
30
JiA
VTH supply
current
ITH
0.5
1.0
rnA VT H = 0 to VOO
Input voltage,
low
VIL
o
0.8
V
Input voltage,
high
VIH1
2.2
VOD
V
All inputs
except RESET,
P1o/NMI, X1, X2
VIH2
0.8 x
Voo
VOO
V
RESET, P101
NMI, X1, X2
0.45
V
IOL = 1.6mA
V
IOH = -0.4 rnA
~
20
2
Capacitance
Voo
DC Characteristics; J£PD70335-8
Each output pin
Total
140
Conditions
Output voltage,
low
VOL
Output voltage,
high
VOH
Input current
Voo
-1.0
±20
JiA
EA, P101NMI;
VI = 0 toVOO
Input leakage
current
III
±10
JiA
All except EA,
P1o/NMI; VI = 0
to VOO
Output leakage
current
ILO
±10
JiA
Vo = Oto VOO
Notes:
(1) The standard operating temperature range is -10 to +70°C.
However, extended temperature range parts (-40 to +85°C) are
available with certain restrictions.
32
NEe
pPD70335 (V35 Plus)
AC Characteristics; "PD70335-8
VOO = +5 V ±10%; TA -10 to + 70°C; CL = 100 pF (max)
n = total number of wait states; T = CPU clock period (tcyKl
Symbol
Max
Unit
tlR, tlF
20
ns
Input rise, fall time
tlRS' tlFS
30
ns
RESET, NMI (Schmitt)
Output rise, fall time
tOR, tOF
20
ns
Except CLKOUT
X1 cycle time
tCYX
62
250
ns
tWXH/tWXL
20
X1 width, high/low
X1 rise, fall time
Min
Conditions
Parameter
Input rise, fall time
tXR, tXF
125
ns
20
ns
2000
ns
CLKOUT cycle time
tCYK
CLKOUT width, high/low
tWKH/t,WXL
CLKOUT rise, fall time
tKR, tKF
Address delay time
tOKA
Address valid to input data valid
tOAOR
MREQ to address hold time
tHMRA
MREQ to data delay
tOMRO
(n+ 2)T- 60
ns
MSTB to data delay
tOMSO
(n + 1)T - 60
ns
MREQ to MSTB delay
tOMRMSR
T + 35
ns
MREQ width, low
twMRL
MREQ, MSTB to address hold time
tHMA
Input data hold time
Next control setup time
MREQ to TC delay time
tOMRTC
0.5T -15
15
ns
15
ns
90
ns
(n + 1 .5)T - 70
ns
0.5T - 30
T-35
ns
(n + 2)T -30
ns
0.5T - 30
ns
tHMO
0
ns
tscc
T-25
MREQ delay time
tOAMR
MSTB read delay time
0.5T - 30
ns
ns
tOAMSR
0.5T- 30
ns
twMSLR
(n+1)T-30
ns
Address data output
tOAOW
tSOM
MSTB write delay time
tOAMSW
0.5T -35
0.5T
+
50
ns
(n +0.5)T - 30
ns
MREQ to MSTB write delay time
tOMRMSW
MSTB write width low
twMSLW
T-30
ns
Data output hold time
tHMOW
0.5T - 30
ns
10STB delay time
tOAIS
0.5T -30
10STB to data input
tOISO
10STB width, low
Address hold time from 10STB
Data hold time from 10STB
t
t
(n + 1)T + 35
ns
Write cycle
ns
tWISL
(n + 1)T-30
ns
tHISA
0.5T - 30
ns
tHISOR
0
ns
T-35
MREQ to 10STB delay time
tOMRIS
Next DMARQ setup time
tSOAOQ
DMARQ hold time
tHOARQ
DMAAK read width, low
twDMRL
(n
+ 2.5)T -30
ns
twOMWL
(n + 2)T:... 30
ns
DMAAK write width, low
Write cycle
ns
(n + 1)T-60
I/O cycle
ns
(n -1)T - 50
0
Read cycle
ns
(n + 2)T - 50
(n + 1)T-35
1m
ns
0.5T + 50
MSTB width, read low
Data output setup time
Except X1, X2, RESET, NMI
ns
Demand mode
ns
33
NEe
pPD70335 (V35 Plus)
AC Characteristics; "PD70335-8 (cent)
Parameter
Symbol
DMAAK to TC delay time
tOOATC
TC width, low
twrCL
REFRQ delay time
tOARF
REFRQ width, low
twRFL
Min
Max
OoST
(n
(n
+
+ SO
Unit
Conditions
ns
ns
3)T - 30
OoST- 30
ns
+ 2)T-30
ns
Address hold time
tHRFA
OoST - 30
ns
RESET width low
twRSL 1
30
ms
Crystal oscillator; STOP/
Power on reset
twRSL2
S
/1s
System warm reset
READY setup time from MREQ ~
tSCRYO
2T -100
ns
First sample n ;:: 2
READY setup time from MREQ
tSCRY
nT -100
ns
n;:: 3
READY hold time from MREQ ~
tHCRYO
2T
ns
First sample n = 2
ns
n;:: 3
READY hold time from MREQ ~
tHCRY
nT
READY hold time from MREQ ~
tHCRY1
(n -1)T
ns
READY setup time from CLKOUT ~
tSRYK
20
ns
READY hold time from CLKOUT ~
tHKRY
40
ns
All samples
READY setup time from laSTS ~
tSSRYO
T-100
ns
READY setup time from laSTS ~
tSSRY
(n -1)T-100
ns
n;:: 3
READY hold time from laSTS ~
tHSRYO
T
ns
First sample n = 2
n;:: 3
READY hold time from laSTS ~
tHSRY
(n -1)T
ns
READY hold time from laSTS ~
tHSRY1
(n -2)T
ns
HLDRQ setup time
tSHQK
30
HLDAK output delay time
tOKHA
1S
Sus control float to HLDAK ~
tCFHA
T-SO
HLDAK t to control output time
tOHAC
T-SO
HLDRQ to HLDAK delay
tOHQHA
HLDRQ ~ to control float time
tOHQC
HLDRQ width, low
ns
80
n$
3T
3T
ns
ns
+ 160
+ 30
ns
ns
tWHQL
10ST
ns
HLDAK width, low
twHAL
T
ns
INTP, DMARQ setup
tSIQK
30
ns
INTP, DMARQ width, high/low
twIQH/tWIQL
8T
ns
POLL setup time
tSPLK
30
n$
NMI width, high/low
tWNIH/tWNIL
S
/1s
n$
CTS width, low
twCTL
2T
INT setup time
tSIRK
30
INTAK delay time
tOKIA
1S
INT hold time
tHlAlQ
0
ns
INTAK width, low
twlAL
2T-30
ns
INTAK width, high
tWIAH
T- 30
INTAK to data delay time
to lAO
INTAK to data hold time
tHIAO
0
SCKO (TSCK) cycle time
tCYTK
1000
34
n$
80
ns
ns
2T -130
n$
OoST
ns
ns
First sample n ;:: 2
NEe
pPD7033S (V3S Plus)
AC Characteristics; p.PD70335-8 (cont)
Parameter
Symbol
Min
SCKO (TSCK) width, high/low
twSTH/ tWSTL
450
TxD delay time
tOTKO
Max
Unit
210
TxD hold time
ns
20
ns
ns
CTSO (RSCI<) cycle time
tCYRK
1000
CTSO (RSCK) width, high/low
tWSRH/ tWSRL
420
ns
80
ns
RxD setup/hold time
Conditions
ns
Recommended Oscillator Components
External System Clock Control Source
Ceramic Resonator
Capacitors
Manufacturer
Product No.
C1 (pF)
C2 (pF)
Kyocera
KBR-10.0M
33
33
30
Internal Oscillator
!
Murata Mfg.
I::
1
TDK
CSA16.00MX040
30
CSA20.00MX040
10
10
FCR10.M2S
30
30
15
6
FCR16.0M2S
Manufacturer
Case
--1m
C1 (pF)
C2 (pF)
Kinseki (KSS)
HC-49/U (KR·100)
22
22
*Crystal
External Clock
Clock
X1
Capacitors
HC-49/U (KR·160)
22
22
HC-49/U (KR-200)
22
22
*AT cut, fundamental mode; 10-, 16-, or 20-MHz crystal
recommended.
X2
83SL~718A
STOP Mode Data Retention Characteristics
TA = -10 to + 70°C
Timing Waveforms
AC Input 1 (Except X11 X21 RESET I NMI)
4V
2.
0.4 V
Parameter
Symbol
Min
Max
Unit
Data retention voltage
VOOOR
2.4
5.5
v
4
ps
200
VOO rise/fall time
Stop Mode Data Retention Timing
2.2 V
0.8 V
VOO
IIR
!-IIF
VDDDR
83-004305A
IRVO
AC Input 2 (RESET I NMI)
~
83-004333A
AC Output (Except CLKOUT)
rt=
0.8 V
IIRS
It-IIFS
.2V
~
0.8 V
83-004306A
lOR
-
-I-O-F- - . - 83-004307A
35
NEe
pPD70335 (V35Plus)
Clock In and Clock Out
CLKIN1
[X1j
0.8 V
1-----tCYX----+1
CLKOUT
.
-
I+-
-
tKR
1\ 2.2 V
V
tWKH
tWKL
-tKF
ICYK
..
0.8 V
Memory Read
r-----B1---~---B2----_r----B3~
CLKOUT
ADDRESS
015· DO
--------+----+--+----<1
REFRQ
t:1't~.~---------tWTCL-------~:('
DMRTC
36
831JB-0052768
NEe
pPD70335 (V35 Plus)
Memory Write
r-----B1-----+-----B2----~---B3~
CLKOUT
ADDRESS
t DADW
-·~---------I--t SDM ------~
tscc---
t DMRMSW-k------.I
tDMRTC
~---------tWTCL-----------.1
83MB-005277B
37
NEe
pPD70335 (V3S Plus)
I/O Read
~B1----~-----B2----4----B3~
CLKOUT
ADDRESS
0
15
-0
0
+-.....~...............--~I
........................................~...............
R/W
.--tDMRD--+---~
t DAMR
~----~
I+-----/----+--t WMRL
MSTB
tDAIS
IOSTB ............................................................+-...............~I
83NR-7429B
38
NEe
IIPD70335 (V35 Plus)
I/O Write
~B1----~----B2----~---B3~
CLKOUT
ADDRESS
~---+----tWMRL------~
MSTB
-----------------------+----+-------~------~~-------------+------------
10STB
REFRQ
83NR-7430B
39
NEe
pPD70335 (V3S Plus)
DMA, I/O to Memory
~B1-----r----B2----4----B3~
eLKOUT
ADDRESS
0..5 -Do
RtW
tDAMR~--~~1
~~-----+--
tsee ----./
DMARQODMARQ1
: = ~ -=- - - :. - -t-WT-e-L~ -=- =- =- =- =- - - :"~{
40
83MS-005280S
NEe
DMA~
pPD70335 (V35 Plus)
Memory to I/O
~Bl----~----B2----4----B3~
CLKOUT
ADDRESS
RtW
t DAMR -I4--~
'-"-------1--
tscc---~
DMARQODMARQl
TC1-TCO
---t-{
:===-=--=--=----------twr-C-L-:.-=--=--=----:..-----
83MB'()()5281B
41
JlPD70335 (V3S'Plus)
Refresh
~B1--~~~--B2----4----B3~
CLKOUT
1~--~tDKA
ADDRESS
RtW
tscc----
t DARF
~--+I
1+------ tWRFL--------.I
83MB-005282B
CLKOUT--------------------------------------~~-J
RESET-------~~·~-_-_-_-_-_-_-_tW_R_S_L1_-
~j;--------~U----------------------------------
_____-____
83-0043168
CLKOUT
_ _ ~~".12~ _ _ _ _ __
RESET-~
~
83-0043178
42
NEe
pPD70335 (V35 Plus)
READY 1
B1
B2IBAW
BAW
BAW/B2
B3
(RIW)
CLKOUT
READY
83SL-74328
READY 2
B1
B2JBAW
BAW
BAWIB2
B3
(RIW)
CLKOUT
J:1m5
iOsi'B
_~~_----Jr
I.......-~--+-_+-+--+---..J/
READY
83SL-7431B
HLDRQ/ HLDAK 1
Bus control"
1-----tDHQHA ---~
HLOAK
"A19 -AO, 015-00, MREQ, MSTB, IOSTB, R/W
~---------tWHAL-------~
43
ttlEC
JlPD70335 (V35 PIUs)
H LDRQ/HLDAK 2
CLKOUT
HLDRQ
f4-~--
tWHOL -.,.---.1
Bus control· --1--------of~--_+____::---_:_---------_l(
t_D_KH~A t=____~U~--~I~.===========~-t-D-H-OC--------------_-_-_-_-_~________
___
HLoAK _
r
* A19-AO, 015-00, MREQ, MSTB,IOSTB, RNi
83-0043216
INffl DMARQ Input
CLKOUT
44
NEe
I'PD70335 (V35 Plus)
CTSlnput
-twcn-===cJ
1t---------.
INTR/INTAK
tOKIA
tHIAIQ
tHIAO
tsc
D7-DO------------~~--------------~----------------------~1
83-0043268
Serial Transmit (I/O Interface Mode)
tCYTK
\
II
I
i\
II
tWSTL
tHTKD
tWSTH
C
)
TxD
j+tDTKD-+
83MB-005283B
Serial Receive (I/O Interface Mode)
tCYRK
\
II
i)
I+--tWSRL-
..
tWSRH
"
K
RxD
l-tSRDK-
tHKRD
II
83MB-005284B
45
NEe
pPD7033S (V3S Plus)
INSTRUCTION SET
Symbols and Abbreviations (cont)
Instructions, grouped according to function, are described in a table near the end of this data sheet.
Descriptions include source code, operation, opcode,
number of bytes, and flag status. Supplementary information applicable to the instruction set is contained in
the following tables.
Identifier
Description
near-proc
Procedure within the current program segment
far-proc
Procedure located in another program segment
near-label
Label in the current program segment
shortlabel
Label between -128 and +127 bytes from the end
of instruction
• Symbols and Abbreviations
• Flag Symbols
• 8- and 16-Bit Registers. When mod = 11, the register
is specified in the operation code by the byte/word
operand (W = 0/1) and reg (000 to 111).
• Segment Registers. The segment register is specified in the operation code by sreg (00,01, 10, or 11).
• Memory Addressing. The memory addressing mode
is specified in the operation code by mod (00, 01, or
10) and mem (000 through 111).
• Instruction Clock Count. This table gives formulas
for calculating the number of clock cycles occupied
by each type of instruction. The formulas, which
depend on byte/word operand and RAM enable/
disable, have variables such as EA (effective address), W (wait states), and n (iterations or string
instructions).
far-label
Label in another program segment
memptr16
Word containing the offset of the memory location
within the current program segment to which
control is to be transferred
memptr32
Double word containing the offset and segment
base address of the memory location to which
control is to be transferred
regptr16
16-bit register containing the offse~ of the memory
location within the program segment to which
control is to be transferred
pop-value
Number of bytes of the stack to be discarded (0 to
64K bytes, usually even addresses)
fp-op
Immediate data to identify the instruction code of
the external floating-point operation
R
Register set
W
Word/byte field (0 to 1)
reg
Register field (000 to 111)
mem
Memory field (000 to 111)
Symbols and Abbreviations
mod
Mode field (00 to 10)
Identifier
Description
S:W
reg
8- or 16-bit general-purpose register
When S:W = 01 or 11, data = 16 bits. At all other
times, data 8 bits.
X, XXX,
Data to identify the instruction code of the
external floating point arithmetic chip
reg8
8-bit general-purpose register
reg16
16-bit general-purpose register
dmem
8- or 16-bit direct memory location
mem
8- or 16-bit memory location
mem8
8-bit memory location
mem16
16-bit memory location
mem32·
32-bit memory location
sfr
8-bit special function register location
imm
Constant (0 to FFFFH)
imm16
Constant (0 to F FF FH)
imm8
Constant (0 to F FH)
imm4
Constant (0 to FH)
imm3
Constant (0 to 7)
acc
AW or AL register
sreg
Segment register
src-table
Name of 256-byte translation table
src-block
Name of block addressed by the IX register
dst-block
Name of block addressed by the IV register
46
YVY, ZZZ
=
AW
Accumulator (16 bits)
AH
Accumulator (high byte)
AL
Accumulator (low byte)
BP
Base pointer register (16 bits)
BW
BW register (16 bits)
BH
BW register (high byte)
BL
BW register (low byte)
CW
CW register (16 bits)
CH
CW register (high byte)
CL
CW register (low byte)
DW
DW register (16 bits)
DH
DW register (high byte)
DL
DW register (low byte)
SP
Stack pointer (16 bits)
PC
Program counter (16 bits)
PSW
Program status word (16 bits)
IX
Index register (source) (16 bits)
NEe
pPD70335 (V35 Plus)
Symbols and Abbreviations (cont)
Flag Symbols
Identifier
Description
Identifier
Description
IV
Index register (destination) (16 bits)
(blank)
No change
PS
Program segment register (16 bits)
a
SS
Stack segment register (16 bits)
Cleared to
a
Set to 1
a register (16 bits)
x
Data segment 1 register (16 bits)
U
Undefined
AC
Auxiliary carry flag
R
Value saved earlier is restored
CV.
Carry flag
P
Parity flag
DSo
S
Z
Data segment
Zero flag
DIR
Direction flag
Interrupt enable flag
v
BRK
8- and 16-Bit Registers (mod = 11)
Sign flag
IE
Overflow flag
Break flag
MD
Mode flag
(...)
Values in parentheses are memory contents
disp
Displacement (8 or 16 bits)
ext-disp8
16-bit displacement (sign-extension byte
displacement)
temp
Temporary register (8/16/32 bits)
tmpcy
Temporary carry flag (1-bit)
seg
Immediate segment data (16 bits)
offset
Immediate offset data (16 bits)
Transfer direction
+
Addition
Subtraction
x
Multiplication
%
Modulo
AND
Logical product
OR
Logical sum
XOR
Exclusive logical sum
XXH
Two-digit hexadecimal value
XXXXH
Four-digit hexadecimal value
Division
Set or cleared according to the result
+ 8-bit
reg
W=O
000
AL
AW
001
CL
CW
010
DL
DW
011
BL
BW
100
AH
SP
101
CH
BP
110
DH
IX
111
BH
IV
W = 1
II
Segment Registers
sreg
Register
00
DS 1
01
PS
10
SS
11
DSo
Memory Addressing
mem
mod
000
BW
= 00
011
+ IX
BW + IV
BP + IX
BP + IV
100
IX
001
010
101
IV
110
Direct
111
BW
mod
= 01
+ IX + disp8
BW + IV + disp8
BP + IX + disp8
BP + IV + disp8
IX + dispB
IV + disp8
BP + disp8
BW + disp8
BW
mod
= 10
+ IX + disp16
BW + IV + disp16
BP + IX + disp16
BP + IV + disp16
IX + disp16
IV + disp16
BP + disp16
BW + disp16
BW
47
NEe
,.,PD70335 (V35Plus)
Instruction Clock Count
Mnemonic
Operand
Clocks
Mnemonic
Operand
Clocks
ADD
reg8, reg8
reg16, reg16
2
2
CALL
near-proc
regptr16
21+W [17+W]
21+W [17+W]
reg8, mem8
reg16, mem16
EA+7+W
EA+7+W
mem8, reg8
reg16, mem16
EA+10+2W [EA+7+W]
EA+ 10+ 2W [EA+ 7 + W]
memptr16
far-proc
memptr32
EA+24+2W [EA+22+2W]
36+2W [32+2WI
EA+32+4W [EA+20+4W]
reg8, imm8
mem16, imm16
5
6
mem8,imm8
mem16, imm16
AL, imm8
AW, imm16
CHKIND
reg16, mem32
EA+24+2W
CLA1
CY
DIA
2
2
EA+ 11+2W [EA+9+2W]
EA+12+2W [EA+8+2W]
reg8, CL
reg16, CL
8
8
5
6
mem8, CL
mem16, CL
EA+16+2W [EA+13+W]
EA+16+2W [EA+13+W]
ADD4S
22+ (30+3W)n [22+ (28+3W)n]
Same as ADD
reg8, imm3
reg16, imm4
7
ADDC
mem8, imm3
mem16, imm4
EA+13+2W [EA+10+W]
reg8, reg8
reg16, reg16
2
2
reg8, mem8
reg16, mem16
EA+7+W
EA+7+W
mem8, reg8
mem16, reg16
EA+7+W
EA+7+W
reg8, imm8
reg16, imm8
reg16, imm16
5
5
6
memS, imm8
mem16, immS
mem16, imm16
EA+8+W
EA+9+W
EA+9+W
AL, immS
AW, imm16
5
6
ADJ4A
9
ADJ4S
9
ADJBA
17
ADJBS
AND
17
reg8, reg8
reg16, reg16
2
2
reg8, mem8
reg16, mem16
EA+7+W
EA+7+W
mem8, reg8
mem16, reg16
EA+10+2W [EA+7+W]
EA+10+2W [EA+7+W]
reg8, imm8
reg16, imm16
5
6
memS,lmmS
mem16, imm16
EA+11+2W [EA+9+2W]
EA+12+2W [EA+S+2W]
AL, imm8
AW, imm16
5
6
Bcond (conditional branch)
S or 15
BCWZ
8 or 15
BA
BAK
near-label
short-label
12
12
regptr16
memptr16
13
EA+16+W
far-label
memptr32
15
EA+23+2W
3
immS
50+5W [3S+5W]
51 +5W [39+5W]
BAKCS
15
BAKV
50+5W [3S+5W]
BTCLR
29
BUSLOCK
2
48
CMP
CMP4S
CMPBK
7
EA+13+2W[EA+9+~
22+ (25+2W)n
memS,memS
mem16, mem16
CMPBKB
25+2W [21 +2W]
25+2W [19+2W]
16+ (23+2W)n
CMPBKW
16+ (23+2W)n
CMPM
mem8
mem16
1S+W
19+2W
CMPMB
n> 1
16+(16+W)n
CMPMW
n> 1
16+ (16+2W)n
CVTBD
19
CVTBW
3
CVTDB
20
CVTWL
8
DBNZ
S or 17
DBNZE
S or 17
DBNZNE
S or 17
NEe
pPD7033S (V3S Plus)
Instruction Clock Count (cant)
Mnemonic
Operand
Clocks
Mnemonic
Operand
Clocks
DEC
reg8
reg16
5
2
MOV
reg8, reg8
reg16, reg16
2
2
mem8
mem16
EA+13+2W [EA+11+2W]
EA+13+2W[EA+9+2W]
reg8, mem8
reg16, mem16
EA+7+W
EA+7+W
DI
4
DISPOSE
11+W
mem8, reg8
mem16, reg16
EA+5+W [EA+2]
EA+5+W [EA+2]
reg8, imm8
reg16, imm16
5
6
mem8, imm8
mem16, imm16
EA+6+W
EA+6+W
AL, dmem8
AW, dmem16
10+W
10+W
dmem8, AL
dmem16, AW
8+W [5]
8+W [5]
sreg, reg16
sreg, mem16
4
EA+9+W
DIV
DIVU
AW, reg8
AW, mem8
46-56
EA+49+W to EA+59+W
DW:AW, reg16
DW: AW, mem16
54-64
EA+57+W to EA+67tW
AW, reg8
AW, mem8
31
EA+34+W
DW:AW, reg16
DW: AW, mem16
39
EA+43+2W
DSO:
2
DS1:
2
EI
12
reg16, sreg
mem16, sreg
3
EA+6+W [EA+3]
41-121
42-122
AH, PSW
PSw, AH
2
3
FINT
2
55+5W [43+5W]
FP02
55+5W [43+5W]
DSO, reg16,
memptr32
.DS1, reg16,
memptr32
EA+17t2W
FP01
EXT
reg8, reg8
reg8, imm4
INC
INM
INS
EA+17+2W
N/A
MOVBK
AL, imm8
AW, imm8
15+W
15+W
mem8,mem8
mem16, mem16
22+2W [17+W]
22+2W [19+W]
MOVBKB
n>
16+ (18+2W)n [16+ (13+W)n]
AL, DW
AW, DW
14+W
14+W
MOVBKW
n> 1
reg8
reg16
5
2
HALT
IN
1m
mem8
mem16
EA+13+2W [EA+11+2W]
EA+13+2W [EA+9+2W]
mem8, DW
mem16, DW
21 +2W [19+2W]
19+2W [15+2W]
mem8, DW
mem16, DW
18+ (15+2W)n [18+ (13+2W)n]
18+(13+2W)n [18+ (9+2W)n]
reg8, reg8
reg8, imm4
63-155
64-156
LDEA
MOVSPA
MOVSPB
reg16
11
MUL
AW, AL, reg8
AW, AL, mem8
31-40
EA+34+Wto EA+43+W
DW:AW, AW,
reg16
DW:AW, AW,
mem16
39-48
reg16, reg16,
imm8
reg16, mem16,
imm8
39-49
reg16, reg16,
imm16
reg16, mem16,
imm16
40-50
reg8
mem8
24
EA+27+W
reg16
mem16
32
EA+33+W
EA+2
LDM
mem8
mem16
13+W
13+W
LDMB
n>
16+(11+W)n
LDMW
n>
16+(11+W)n
16+(18+2W)n [16+ (10+W)n]
16
MULU
EA+42+Wto EA+51+W
EA+ 42+ W to EA+ 52+ W
EA+ 43+ W to EA+ 53+ W
49
NEe
pPD7033S (V3S Plus)
Instruction Clock Count (cont)
Mnemonic
Operand
Clocks
Mnemonic
Operand
Clocks
NEG
regS
reg16
5
5
PREPARE
imm16, immS
mem8
mem16
EA+13+2W [EA+10+W]
EA+13+2W [EA+10+W]
imm8 = 0:26+ W
immS = 1:37+2W
imm8 = n, n > 1 :44+ 19
(n-1)+2Wn
NOP
NOT
NOT1
OR
OUT
OUTM
4
reg8
reg16
5
5
mem8
mem16
EA+13+2W [EA+10+W]
EA+13+2W [EA+10+W]
CY
2
regS, CL
reg16, CL
7
7
memS, CL
mem16, CL
EA+15+W [EA+12+W]
EA+15+2W [EA+12+W]
reg8, imm3
reg16, imm4
6
6
memS, imm3
mem16, imm4
EA+12+2W [EA+9+W]
EA+12+2W [EA+9+W]
regS, regS
reg16, reg16
2
2
regS, mem8
reg16, mem16
EA+7+W
EA+7+W
memS, reg8
mem16, reg16
EA+10+2W [EA+7+W]
EA+10+2W [EA+7+W]
regS,immS
reg16, imm16
5
6
memS, immS
mem16, imm16
EA+11 +2W [EA+9+2W]
EA+12+2W [EA+8+2W]
AL, immS
AW, imm16
5
6
immS, AL
immS, AW
11+W
9+W
Ow, AL
Ow, AW
10+W
S+W
Ow, memS
Ow, mem16
21+2W [19+2W]
19+2W [15+2W]
Ow, mem8
18+ (15+2W)n
[1S+ (13+2W)n]
18+ (13+2W)n
[18+ (9+2W)n]
Ow, mem16
POLL
POP
50
PS:
PUSH
11+W
EA+14+2W [EA+11+W]
OSO,1
SS
12+W
12+W
OSO
PSW
12+W
13+W
R
74+8W [5S]
reg16
mem16
13+W [9+W]
EA+16+2W [EA+12+2W]
OS1
PS
10+W [7]
10+W [7]
SS
OSO
10+W [7]
10+W [7]
PSW
R
9+W [6]
74+SW [50]
immS
imm16
12+W [9]
13+W[10]
REP
2
REPE
2
REPZ
2
REPC
2
REPNC
2
REPNE
2
REPNZ
RET
2
null
pop-value
19+W
19+W
null
pop-value
27+2W
2S+2W
RETI
40+ 3W [34+ W]
RETRSI
12
ROL
regS 1
reg16,1
8
8
mem8,1
mem16,1
EA+16+2W [EA+13+W]
EA+16+2W [EA+13+W]
regS, CL
reg16, CL
11+2n
11+2n
memS, CL
EA+ 19+ 2W+ 2n
[EA+16tW+2n]
EA+ 19+ 2W+ 2n
[EA+16+W+2n]
mem16, CL
N/A
reg16
mem16
2
regS, immS
reg16, immS
9+2n
9+2n
mem8, immS
EA+ 15+2W+2n
[EA+12+W+2n]
EA+ 15+2W+2n
[EA+ 12+ W+ 2n]
mem16, immS
ROL4
regS
mem8
17
EA+20+2W [EA+1S+2W]
ROLC
Same as ROL
ROR
Same as ROL
NEe
pPD70335 (V35 Plus)
Instruction Clock Count (cont)
Mnemonic
Operand
Clocks
Mnemonic
Operand
Clocks
ROR4
reg8
mem8
21
EA+26+2W [EA+24+2W]
TEST1
reg8, CL
reg16, CL
7
7
mem8, CL
mem16, CL
EA+12+W
EA+12+W
reg8, imm3
reg16, imm4
6
6
mem8, imm3
mem16, imm4
EA+9+W
EA+9+W
Same as ROL
RORe
SET1
CY
DIR
2
2
reg8, CL
reg16, CL
7
7
mem8, CL
mem16, CL
EA+15+2W [EA+12+W]
EA+ 15+ 2W [EA+ 12+ W]
reg8, imm3
reg16, imm4
6
6
mem8, imm3
mem16, imm4
EA+12+2W [EA+9+W]
EA+ 12+2W [EA+9+ W]
SHL
Same as ROL
SHR
Same as ROL
SHRA
Same as ROL
SS:
2
STM
mem8
mem16
13+W[10]
13+W (10]
STMB
n> 1
16+ (9+ W)n [16+ (7+ W)n]
STMW
n> 1
TRANS
11+W
TRANSB
11+W
TSKSW
20
XCH
XOR
reg8, reg8
reg16, reg16
3
3
mem8, reg8/
reg8, mem8
EA+12+2W [EA+9+W]
mem16, reg16/
reg16, mem16
EA+ 12+2W [EA+9+2W]
AW, reg16
reg16, AW
4
4
m
Same as AND
16+ (9+ W)n [16+ (5+ W)n]
Notes:
STOP
N/A
SUB
Same as ADD
SUB4S
22+ (30+3W)n
[22+ (28+3W)n]
(1) If the number of clocks is not the same for RAM enabled and RAM
disabled conditions, the RAM enabled value ,is listed first,
followed by the RAM disabled value in brackets; for example,
EA+8+2W [EA+6+W]
SUBC
Same as ADD
TEST
reg8, reg8
reg16, reg16
4
4
reg8, mem8
reg16, mem16
EA+12+W
EA+11+2W
mem8, reg8
mem16, reg16
EA+12+W
EA+11+2W
reg8, imm8
reg16, imm16
7
8
mem8, imm8
mem16, imm16
EA+9+W
EA+10+W
AL, imm8
AW, imm16
5
(2) Symbols in the Clocks column are defined as follows.
EA
additional clock cycles required for calculation of the
effective address
3 (mod 00 or 01) or 4 (mod 10)
W
number of wait states selected by the WTC register
n
number of iterations or string instructions
6
51
NEe
,.,PD70335 (V35 Plus)
Instruction Clock Count for Operations
Word
Byte
RAM Enable
RAM Disable
RAM Enable
RAM Disable
Context switch interrupt
27
27
DMA (Single-step mode)
9.5+2W
15.5+4W
15.5+4W
DMA (Demand release mode)
(3+W)n
(3+W)n
(3+W),n
(3+W)n
3.5+ (6+2W)n
3.5+ (6+ 2W)n
9.5+2W+ (6+2W)n
9.5+2W+ (6+2W)n
3+W
3+W
DMA (Burst mode)
DMA (Single-transfer mode)
9.5+2W
Interrupt (INT pin)
3+W
3+W
57+3W
57+3W
Macro service, sfr .... mem
25+W
20+W
25+W
20+W
Macro service, mem .... sfr
22+W
21+W
22+W
21+W
Macro service (Search char mode), sfr ..... mem
28+W
28+W
Macro service (Search char mode), mem
38+W
35+W
Priority interrupt (Vectored mode)
55+5W
55+5W
NMI (Vectored mode)
53+5W
53+5W
+-
sfr
W = number of wait states inserted into external bus cycle
n = number of iterations
Interrupt Latency
Bus Controller Latency
Clocks
Clocks
Latnecy
Mode
Max
Source
Typ
Max
Hold request
Refresh active
9+3W
NMI pin
18+N
18+N
Intack active
10+2W
INT pin
8+N
8+N
No refresh or intack
7+2W
All others (Note 3)
11+N
27+N
DMA request
(Notes 1, 2)
Typ
Burst
4
9.5+2W
Single-step
4
15.5+2W
Demand release
4
10+2W
Single-transfer
4
10+2W
Notes:
(1) The listed DMA latency times are the maximum number of clocks
when a DMA request is asserted until DMAAK or MREQ goes low
in the corresponding DMA cycle.
(2) The test conditions are: no wait states, no interrupts, no macroservice requests, and no hold requests.
(3) An additional 6 clocks is required to latch an external INTPn
interrupt input.
52
N = number of clocks to complete the instruction
currently executing
NEe
pPD7033S (V3S Plus)
Instruction Set
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
0
0
0
Bytes
W
2
W
2-4
W
2-4
W
3-6
AC
CY
Flags
V P
S
Z
Data Transfer
MOV
reg, reg
reg +- reg
0
0
reg
mem,reg
(mem) +- reg
0
0
mod
reg,mem
reg +- (mem)
mem,imm
(mem) +- imm
0
0
0
0
0
0
0
0
0
0
0
0
mem
reg
mem
reg,imm
reg +- imm
0
acc,dmem
When W = 0: AL +- (dmem)
WhenW = 1 :AH +- (dmem + 1),
AL +- (dmem)
0
0
0
W
0
dmem,acc
WhenW = O:(dmem) +- AL
WhenW = 1 : (dmem + 1) +- AH,
(dmem) +- AL
0
0
0
0
sreg, reg16
sreg +- reg16 sreg: SS, OSO, OS1
0
sreg,mem16
sreg +- (mem16) sreg : SS, OSO, OS1
0
0
mod
0
0
0
0
reg16 +- sreg
mem16,sreg
(mem16) +- sreg
0
0
mod
0
OSO, reg16,
mem32
reg16 +- (mem32),
OSO +- (mem32 + 2)
OS1,reg16,
mem32
reg16 +- (mem32),
OS1 +- (mem32 + 2)
AH,PSW
AH +- S, Z, x, AC, x, P, x, CY
0
0
mod
0
mod
sreg
mem
0
0
sreg
reg
sreg
mem
0
0
0
0
S,.z, x, AC, x, P, x, CY +- AH
0
0
reg16 +- mem16
0
0
TRANS
src-table
AL +- (8W + AL)
XCH
reg, reg
reg
mod
0
~reg
(mem)
AW,reg16
or reg16,AW
AW~reg16
0
2
0
2-4
0
2
0
2-4
1m
2-4
0
0
0
2-4
0
0
x
x
x
mem
0
0
0
0
W
2
W
2-4
reg
0
mem
reg
0
x
2-4
0
reg
mod
0
3
0
0
0
0
W
mem
reg
mem,reg
orreg,mem
3
mem
reg
PSW,AH
0
0
W
0
reg16, mem16
reg
reg
reg
LOEA
~
sreg
0
0
2-3
reg
0
0
0
reg16,sreg
0
mem
reg
mod
mod
reg
0
reg
53
NEe
pPD70335 (V3S Plus)
Instruction Set (cont)
Mnemonic Operand
6
Operation Code
5 4
3 2
Flags
Operation
7
REPC
While CW ;00 0, the next byte of the
primitive block transfer instruction is
executed and CW is decremented (-1).
If there is a waiting interrupt, it is
processed, When CV ;00 1, exit the loop.
0
0
0
0
REPNC
While CW ;00 0, the next byte of the
primitive block transfer instruction is
executed and CW is decremented (-1).
If there is a waiting interrupt, it is
processed. When CY ;00 0, exit the loop.
0
0
0
0
REP
REPE
REPZ
While CW ;00 0, the next byte ofthe
primitive block transfer instruction is
executed and CW is decremented (-1 ).
Ifthere is a waiting interrupt, it is
processed. Ifthe primitive block transfer
instruction is CMPBK or CMPM and
Z;oo 1, exitthe loop.
0
0
REPNE
REPNZ
While CW ;00 0, the next byte of the
primitive block transfer instruction is
executed and CW is decremented (-1).
Ifthere is a waiting interrupt, it is
processed.lfthe primitive block transfer
instruction is CMPBK or CMPM and
Z;oo 0, exit the loop.
0
0
AC
CV
V
P
S
"z
W
x
x
x
x
x
x
W
x
'x
x
x
x
x
0
Bytes
Repeat Prefixes
0
0
Primitive Block Transfer
MOVBK
dst-block,
src-block
When W = 0: (IY) +- (IX)
DIR = 0: IX +- IX + 1, IY +- IV + 1
DIR = 1: IX +- IX:-1, IY +- IY-1
When W = 1: (IY + 1, IY) +- (IX + 1, IX)
DIR = 0: IX +- IX + 2, IY +- IY + 2
DIR = 1: IX +- IX-2, IY +- IY-2
0
0
0
CMPBK
src-block,
dst-block
Wt"\enW = O:(IX)-(IY)
DIR = 0: IX +- IX + 1, IY +- IY + 1
DI R = 1: IX +- IX -1 , IY +- IY-1
WhenW= 1:(IX+ 1, IX)-(IV+ 1, IY)
DIR = 0: IX +- IX + 2, IY +- IY + 2
DIR = 1: IX +- IX-2, IV +- IY-2
0
0
0
CMPM
dst-block
WhenW= O:AL-(IY)
DIR = 0: IY +- IY + 1 ; DIR = 1: IY +- IY-1
WhenW= 1:AW-(IY + 1, IY)
DIR =0: IY +-IY + 2;DIR= 1: IY +-IY-2
0
0
LDM
src-block
When W = 0: AL +- (IX)
DIR=O:IX +-IX+ 1 ;DIR= 1:IX +-IX-1
WhenW = 1:AW +- (IX + 1, IX)
DIR =O:IX +-IX + 2;DIR= 1:IX +-IX-2
0
0
STM
dst-block
When W = 0: (IY) +- AL
DIR =0: IY +- IY + 1 ;DIR= 1: IY +-IY-1
WhenW= 1:(IY+ 1, IY) +- AW
DIR =0: IY +-IY + 2;DIR = 1 :IY +-IY-2
0
0
54
0
0
0
W
W
W
NEe
pPD70335 (V35 Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Flags
0
Bytes
AC
CY
V
P
S
Z
Bit Field Transfer
INS
reg8, reg8
16-bitfield
~
AW
3
0
0
0
reg
reg8,imm4
EXT
reg8, reg8
16-bitfield
AW
~
~
AW
16-bitfield
0
reg
4
0
0
0
0
0
0
0
AW
~
16-bitfield
3
0
0
0
reg
0
reg
reg8,imm4
0
reg
4
0
0
0
0
0
reg
0
0
W
0
W
1m
I/O
IN
OUT
acc, imm8
When W = 0: AL ~ (imm8)
WhenW= 1:AH ~ (imm8 + 1),
AL ~ (imm8)
0
acc,OW
When W = 0: AL ~ (OW)
WhenW = 1 :AH ~ (OW + 1),
AL ~ (OW)
0
imm8,acc
When W = 0: (imm8) ~ AL
WhenW = 1: (imm8 + 1) ~ AH,
(imm8) ~ AL
0
OW,acc
When W = 0: (OW) ~ AL
WhenW = 1:(OW+ 1) ~ AH,
(OW) ~ AL
0
W
0
2
2
W
Primitive Block I/O Transfer
INM
dst-block, OW
When W = 0: (IY) ~ (OW)
OIR = 0: IY f- IY + 1
OIR = 1: IY ~ IY-1
When W = 1: (IY + 1, IY) ~
(OW+ 1,OW)
OIR = 0: IY ~ IY + 2
OIR = 1:IY ~ IY-2
0
0
OUTM
OW, src-block
When W = 0: (OW) ~ (IX)
OIR = 0: IX ~ IX + 1
OIR = 1: IX ~ IX-1
When W = 1: (OW + 1, OW)
(IX+ 1,IX)
OIR = 0: IX ~ IX + 2
OIR = 1: IX ~ IX - 2
0
0
0
W
W
~
55
NEe
pPD70335 (V35 Plus)
Instruction Set (cont)
Operation Code
Mnemonic Operand
Operation
7
6
5
4
3
2
reg +- reg + reg
o
0
0
0
o
0
o
Bytes
W
2
W
2-4
W
AC
CY
Flags
V P
S
Z
Addition I Subtraction
ADD
reg, reg
reg
mem, reg
(mem) +- (mem)
+ reg
o
0
0
mod
reg,mem
reg +- reg + (mem) .
o
0
reg +- reg + irrim
0
AD DC
0
000
(mem) +- (mem) + imm
0
000
mod
0
0
0
0
ace, imm
WhenW = O:AL +- AL + imm
When W = 1: AW +- AW + imm
o
reg, reg
reg +- reg + reg + CY
000
0
0
o
(mem) +- (mem)
+ reg + CY
mod
reg, mem
reg +- reg + (mem) + CY
o
o
o
o
o
0
mod
reg,imm
reg +- reg + imm + CY
o
0
0
mem,imm
(mem) +- (mem)
+ imm + CY
000
mod
SUB
0
aec,imm
When W = 0: AL +- AL + imm + CY
When W = 1: AW +- AW + imm + CY
000
reg, reg
reg +- reg - reg
o
reg,mem
(mem) +- (mem) - reg
reg +- reg - (mem)
o
reg
o
o
0
mod
reg,imm
0
o
o
o
o
o
0
o
(mem) +- (mem) - imm
0
0
SUBC
= O:AL +- AL - imm
= 1: AW +- 9 or AC = 1 :
AL ~ AL + 6, AH ~ AH + 1 ,AC ~ 1,
CY ~ AC,AL ~ ALANDOFH
0
0
ADJ4A
When (AL AND OFH) > 9 or AC = 1 :
AL ~ AL + 6, CY ~ CY OR AC, AC ~ 1,
WhenAL>9FH,orCY= 1:
AL ~ AL + 60H, CY ~ 1
0
0
ADJBS
When (AL AND OFH) > 9 or AC = 1 :
CY ~ AC, AL ~ AL AND OFH
0
0
ADJ4S
When (AL AND OFH) > 9 or AC = 1 :
AL ~ AL - 6, CY ~ CY OR AC, AC
. WhenAI,.>9FH,orCY= 1:
AL ~ AL + 60H, CY ~ 1
0
0
~
0
0
0
x
x
0
x
u
u
u
u
x
x
x
x
x
x
u
u
u
x
x
u
x
x
1,
57
NEe
pPD70335 (V3S Plus)
Instruction Set (cant)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
Flags
V
P
S
Z
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
u
u
0
Bytes
AC
0
2
W
2-4
x
0
2
x
W
2-4
x
CY
Increment I Decrement
INC
reg8
mem
OEC
reg8 +- reg8
+1
(mem) +- (mem)
reg16 +- reg16
reg8 +- reg8 - 1
0
0
reg
mod
0
0
0
mem
0
0
0
0
reg
+1
+1
reg16
reg8
0
0
mem
reg16
reg
0
(mem) +- (mem) - 1
reg16 +- reg16 - 1
mod
0
0
mem
0
0
0
reg
x
x
x
Multiplication
MULU
reg8
mem8
reg16
mem16
MUL
reg8
mem8
reg16
mem16
58
AW +- AL x reg8
AH = 0: CY +- 0, V+-~
AH ~ 0: CY +- 1, V+-1
AW +- ALx (mem8)
AH = O:CY +- 0, V+-~
AH ~ 0: CY +- 1, V+-1
0
0
0
0
x
x
0
2-4
x
x
2
x
x
0
2-4
x
x
0
0
0
0
reg16,
mem16,
imm8
reg16 +- (mem16)ximm8
Product,;; 16 bits: CY +- 0, V+-~
Product> 16 bits: CY +- 1, V+-1
0
reg16,
reg16,
imm16
reg16 +- reg16 x imm16
Product,;; 16bits:CY +- 0, V+-~
Product> 16 bits: CY +- 1, V+-1
0
reg16,
mem16,
imm16
reg16 +- (mem16) x imm16
Product,;; 16 bits: CY +- 0, V+-~
Product> 16 bits: CY +- 1, V+-1
0
0
mod
reg
0
0
u
x
x
u
u
u
0
2-4
u
x
x
u
u
u
2
u
x
x
u
2-4
u
x
x
u
u
u
3
u
x
x
u
u
u
3-5
u
x
x
u
u
u
4
u
x
u
4-6
u
x
u
u
reg
0
reg
0
2
mem
reg
mod
0
reg
0
reg16 +- reg16ximm8
Product,;; 16 bits: CY +- 0, V+-~
Product> 16 bits: CY +- 1, V+-1
u
mem
0
reg16,
reg16,
imm8
u
reg
0
0
u
mem
0
0
mod
u
reg
0
mod
u
mem
0
mod
OW,AW +- AWxreg16
OW = AW sign expansion: CY +- 0, V+-~
OW ~ AW sign expansion: CY +- 1, V+-1
OW, AW +- AW x (mem16)
OW = AW sign expansion: CY +- 0, V+-~
OW ~ AW sign expansion: CY +- 1, V+-1
0
2
0
AW +- AL x reg8
AH = AL sign expansion: CY +- 0, V+-O
AH ~ AL sign expansion: CY +- 1, V+-1
AW +- AL x (mem8)
AH = AL sign expansion: CY +- 0, V+-O
AH ~ AL sign expansion: CY +- 1, V+-1
0
0
reg
0
mod
OW,AW +- AWxreg16
OW = 0: CY +- 0, V+-O
OW~O:CY +-1,V +-1
OW, AW +- AW x (mem16)
OW = 0: CY +- 0, V+-O
OW~O:CY +-1,V +-1
0
mem
0
reg
0
u
reg
0
0
mem
x
u
u
NEe
pPD70335 (V35 Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
Flags
0
Bytes
AC
CY
V
P
S
Z
Unsigned Division
DIVU
regS
memS
reg16
mem16
temp +- AW
When temp -0- regS> FFH:
(SP-1, SP-2) +- PSW,
(SP-3, SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AH +- temp % regS, AL +- temp -0- reg8
°
°
°
2
u
u
reg
temp +- AW
When temp -0- (memS) > FFH:
mod
(SP-1, SP-2) +- PSW,
(SP-3, SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AH +- temp% (memS), AL +- temp -0- (memS)
°
°
°
2-4
u
u
u
mem
temp +- AW
When temp -0- reg16 > FFFFH:
(SP-1,SP-2) +- PSW,
(SP-3, SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AH +- temp % reg16, AL +- temp -0- reg16
°
°
u
u
reg
temp +- AW
When temp -7 (mem16) > FFFFH:
mod
(SP-1, SP-2) +- PSW,
(SP-3,SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All othertimes:
AH +- temp%(mem16),AL +- temp -7 (mem16)
°
°
mem
temp +- AW
When temp -0- regS> and temp -0- regS
> 7FH ortemp -7 regS < and
temp -7 regS < 0- 7FH -1 :
(SP-1,SP-2) +- PSW,
(SP-3, SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AH +- temp % regS, AL +- temp -0- regS
°°
°
°
2
u
reg
temp +- AW
When temp -7 (memS) > and (memS) >
mod
7 FH or temp -7 (memS) < and
temp -7 (memS) < 0-7FH -1:
(SP-1,SP-2) +- PSW,
(SP-3, SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0, PS +- (3,2), PC +- (1,0)
All other times:
AI-! +- temp % (memS), AL +- temp -7 (mem8)
°
°
2-4
u
mem
u
2
u
u
1m
2-4
u
u
u
Signed Division
DIV
regS
memS
°°
u
u
59
NEe
pPD70335 (V35 Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
0
Bytes
AC
2
u
2-4
u
CY
Flags
V P
S
Z
u
u
u
u
x
x
x
u
x
x
x
x
x
x
Signed Division (cont)
OIV
reg16
mem16
temp ~ OW,AW
When temp -;- reg16 > 0 and reg16
> 7FFFH ortemp -;- reg16 <
0-7FFFH-1:
(SP-1,SP-2) ~ PSW,
(SP-3,SP-4) ~ PS,
(SP-5, SP-6) ~ PC, SP ~ SP-6,
IE ~ 0, BRK ~ 0, PS ~ (3,2), PC ~ (1,0)
All other times:
AH ~ temp % reg16, AL ~ temp -;- reg16
0
temp ~ OW,AW
When temp -;- (mem16) > 0 and (mem16)
mod
> 7 FFFH ortemp -;- (mem16) < 0 and
temp -;- (mem16) < 0-7FFFH-1:
(SP-1,SP-2) ~ PSW,
(SP-3, SP-4) ~ PS,
(SP-5, SP-6) ~ PC, SP ~ SP-6,
IE ~ 0, BRK ~ 0, PS ~ (3,2), PC ~ (1,0)
All other times:
AH ~ temp%(mem16),AL ~ temp -;- (mem16)
0
u
u
reg
u
mem
Data Conversion
AH
CVTBO
CVTOB
AH
~
~
AL -;- OAH, AL
0, AL
~
~
AL % OAH
AH x OAH
0
0
0
0
0
0
0
+ AL
0
0
0
0
0
0
0
0
0
u
2
0
0
2
0
CVTBW
When AL < 80H: AH ~ 0
All other times: AH ~ FFH
0
0
0
0
CVTWL
When AL < 8000H: OW ~ 0
All other times: OW ~ FFFFH
0
0
0
0
0
Comparison
CMP
reg, reg
reg-reg
0
0
0
reg
mem,reg
(mem)-reg
0
0
0
mod
reg,mem
reg-(mem)
0
reg,imm
reg-imm
0
0
0
0
reg
0
0
2
W
2-4
x
x
x
x
W
2-4
x
x
x
x
W
3-4
x
x
x
x
x
x
W
3-6
x
x
x
x
x
x
W
2-3
x
x
x
x
x
x
x
x
mem
reg
mod
W
reg
x
mem
0
0
S
reg
mem,imm
(mem)-imm
0
mod
acc,imm
60
WhenW = O:AL-imm
WhenW= 1:AW-imm
0
0
0
0
0
0
S
mem
0
NEe
pPD70335 (V35 Plus)
Instruction Set (cant)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
Flags
V
P
5
Z
x
x
x
x
x
x
x
x
0
0
x
x
0
0
x
0
0
x
u
0
0
x
x
2-3
u
0
0
x
x
W
2
u
0
0
x
x
W
2-4
0
0
x
x
W
2-4
0
0
x
x
W
3-4
0
0
W
3-6
u
0
0
W
2-3
u
0
0
0
Bytes
W
2
W
2-4
W
2
W
2-4
W
2
W
2-4
W
3-4
W
3-6
W
AC
CY
Complement
NOT
reg
mem
reg +- reg
0
reg
0
0
0
(mem) +- (mem)
reg
0
mod
NEG
0
reg +- reg + 1
0
mem
1.
0
mem
reg
(mem) +- (mem) + 1
0
mod
0
0
0
mem
Logical Operation
TEST
reg, reg
reg AND reg
0
0
0
reg
mem,reg
or reg, mem
(mem) AND reg
reg,imm
regANDimm
mem,imm
0
0
0
0
0
0
(mem) AND imm
ace, imm
When W = 0: AL AND imm8
When W = 1: AW AND imm8
reg, reg
reg +- reg AND reg
0
0
reg
0
reg
0
0
0
0
0
0
(mem) +- (mem) AND reg
0
0
0
mod
reg,mem
reg +- reg AND (mem)
0
0
0
reg,imm
mem,imm
reg +- reg AND imm
0
(mem) +- (mem) AND imm
0
mod
ace, imm
When W = 0: AL +- AL AND imm8
When W = 1: AW +- AW AND imm16
0
a
0
0
0
0
mem
0
0
reg
0
xII
reg
reg
mod
0
0
reg
mem,reg
x
mem
0
0
0
u
mem
0
mod
AND
0
mod
x
reg
u
mem
0
0
0
0
0
0
0
0
0
0
mem
0
0
0
x
reg
0
0
x
x
x
61
NEe
pPD70335 (V35 Plus)
Instruction Set (cont)
Operation Code
Mnemonic Operand
Operation
7
6
5
4
reg +- reg OR reg
o
0
0
0
3
2
Flags
V P
S
Z
0
x
x
x
o
0
x
x
x
2-4
o
0
x
x
x
W
3-4
o
0
x
x
W
3-6
o
0
x
2-3
o
0
x
W
2
o
0
x
x
W
2-4
o
0
x
x
W
2-4
o
0
x
W
3-4
o
0
x
W
3-6
o
0
x
x
2-3
o
0
x
x
x
3
o
0
u
u
x
o
Bytes
AC
CY
W
2
u
o
W
2-4
W
Logical Operation (cont)
OR
reg, reg
o
reg
mem,reg
(mem) +- (mem) OR reg
o
0
0
mod
reg,mem
reg +- reg OR (mem)
o
0
0
o
mem,imm
XOR
o
(mem) +- (mem) OR imm
0
0
0
0
0
When W = 0: AL +- AL OR imm8
When W = 1: AW +- AW OR imm16
o
0
reg, reg
reg +- reg XOR reg
o
0
mem
o
0
o
0
(mem) +- (mem) XOR reg
o
o W
o
reg,mem
reg +- reg XOR (mem)
o
0
reg,imm
0
000
mem,imm
(mem) +- (mem) XOR imm
ace, imm
When W = 0: AL +- AL XOR imm8
When W = 1: AW +- AW XOR imm16
o
0
reg 8 bit no. CL = 0: Z +- 1
reg8 bit no. CL = 1 : Z +- 0
o
0
(mem8) bit no. CL = 0: Z +- 1
(mem8) bit no. CL = 1: Z +- 0
o
o
reg16 bit no. CL = 0: Z +- 1
reg16bitno.CL = 1:Z +- 0
0
mod
u
mem
reg
0
0
mem
o
0
o
reg +- reg XOR imm
0
reg
mod
x
reg
o
0
mod
0
mem
reg
mem, reg
0
reg
0
0
acc,imm
o
0
mod
0
mem
reg
000
reg +- reg OR imm
o
0
reg
mod
reg,imm
reg
o
o
o
o
o
0
o
o
0
o
o
0
0
x
reg
0
0
mem
o W
Bit Operation
TEST1
reg8, CL
mem8,CL
reg16,CL
mem16,CL
reg8, imm3
(l11em16) bit no. CL = 0: Z +- 1
(mem16) bit no. CL = 1: Z +- 0
reg8 bit no. imm3 = 0: Z +- 1
reg8 bit no. imm3 = 1 : Z +- 0
0
o
0
0
0
0
0
0
mod
0
0
o
0
0
0
000
o
o
0
0
0
0
0
reg
0
3-5
u
o
0
u
u
3
u
o
0
u
u
o
0
o
0
0
mem
x
o
reg
3-5
x
000
0
0
mod
0
0
o
0
0
0
0
000
o
o
mem
4
o
000
o
62
0
000
0
o
0
reg
0
u
u
x
NEe
pPD7Q335 (V3S Plus)
Instruction Set (cant)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
(mem8) bit no. imm3 = 0: Z +- 1
(mem8) bit no. imm3 = 1: Z +- 0
0
0
0
0
0
0
mod
0
0
reg16 bit no. imm4 = 0: Z +- 1
reg16 bit no. imm4 = 1: Z +- 0
0
0
0
0
0
0
0
0
Bytes
AC
CY
Flags
V
P
5
Z
Bit Operation (cont)
TEST1
mem8,imm3
reg16,imm4
mem16,imm4
NOT1
reg8, CL
mem8,CL
reg16, CL
mem16,CL
reg8, imm3
mem8,imm3
reg16, imm4
mem16,imm4
(mem16) bit no. imm4 = 0: Z +- 1
(mem16) bit no. imm4 = 1: Z +- 0
reg8 bit no. CL +- reg8 bit no. CL
(mem8) bit no. CL +- (mem8) bit no. CL
reg16 bit no. CL +- reg16 bit no. CL
(mem16) bit no. CL +- (mem16) bit no. CL
0
0
0
0
0
0
0
0
mod
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
mod
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
u
u
x
4
0
0
u
u
x
4-6
0
0
x
0
mem
3
,
0
1
0
reg
0
III
3-5
0
0
mem
3
0
reg
3-5
0
0
0
0
0
0
0
0
0
0
(mem8) bit no. imm3 +- (mem8) bit no. imm3 0
0
0
0
0
0
0
0
mem
4
0
0
reg
4-6
0
mod
0
0
0
0
0
0
0
0
0
0
0
(mem16)bitno.imm4 +- (mem16)bitno.imm4 0
0
0
0
0
0
0
0
0
0
0
CY +- CY
0
0
0
mod
reg16 bit no. imm4 +- reg16 bit no. imm4
4-6
0
reg
0
0
reg8 bit no. imm3 +- reg8 bit no. imm3
0
0
0
mem
0
0
0
mod
CY
0
0
0
mem
4
0
reg
4-6
0
mem
0
0
x
63
NEe
pPD7033S (V3S Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
mod
0
0
0
0
Bytes
AC
CY
Bit Operation (cont)
CLR1
reg8,CL
mem8,CL
reg16,CL
mem16,CL
reg8,imm3
mem8,imm3
reg16,imm4
mem16,imm4
SET1
reg16bitno. CL
~
~
reg8 bit no. imm3
0
0
~
~
~
~
reg16 bit no. imm4
0
0
(mem8) bit no. imm3
DIR
reg8,CL
reg8 bit no. CL
0
0
~
(mem16) bit no. imm4
DIR
mem16,CL
0
(mem16) bit no. CL
CY~O
reg16,CL
~
(mem8) bit no. CL
CY
mem8,CL
64
reg8 bit no. CL
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3-5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
mem
3
0
0
reg
3-5
0
mod
0
mem
0
4
0
reg
4-6
0
mod
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
mod
0
0
(mem8) bit no. CL
reg16 bit no. CL
~
~
(mem16) bit no. CL
1
1
~
1
0
mem
4
0
reg
0
4-6
0
0
0
mem
0
0
0
0
0
0
0
0
reg
0
0
0
mem
0
0
0
reg
0
0
0
mem
~O
1
0
0
0
~
0
0
0
0
0
reg
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
mod
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
mod
0
0
0
3
3-5
0
3
3-5
Flags
V P
S
Z
NEe
pPD70335 (V35 Plus)
Instruction Set (cont)
Mnemonic Operand
6
Operation Code
5 4
3 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Operation
7
regS bit no. imm3 +- 1
Flags
0
Bytes
AC
CY
V
P
S
Z
Bit Operation (cont)
SET1
regS,imm3
memS,imm3
(memS) bit no. imm3 +- 1
0
reg16, imm4
mem16,imm4
reg16 bit no. imm4 +- 1
(mem16) bit no. imm4 +- 1
0
0
0
0
0
0
0
0
O· 0
0
0
0
0
0
0
0
mod
0
CY
CY +-1
DIR
DIR +- 1
reg, 1
CY +- MSB of reg, reg +- reg x 2
When MSB of reg ~ CY, V+-1
When MSB of reg = CY, V+-O
0
CY +- MSB of (mem), (mem) +- (mem) x 2
When MSB of (mem) ~ CY, V+-1
When MSB of (mem) = CY, V+- 0
0
0
reg
4-6
0
0
mem
0
0
0
0
0
mod
0
4
.1
0
reg
4-6
0
0
0
mem
0
1m
0
0
Shift
SHL
mem, 1
reg,CL
mem,CL
reg, immS
mem,immS
mod
temp +- CL, whiletemp~ 0,
repeat this operation, CY +- MSB of reg,
reg +- reg x 2, temp +- temp-1
temp +- CL, while temp ~ 0,
repeat this operation, CY +- MSBof(mem),
(mem) +- (mem)x2, temp +- temp-1
0
0
1.
0
0
0
0
0
0
0
0
mod
temp +- immS, while temp ~ 0,
repeat this operation, CY +- MSB of reg,
reg +- reg x 2, temp +- temp-1
0
temp +- immS, while temp ~ 0,
repeatthis operation, CY +- MSB of (mem),
mod
(mem) +- (mem)x2, temp +- temp-1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
x
x
x
x
x
reg
0
0
W
2-4
x
x
mem
0
u
W
x
reg
0
W
2-4
u
W
3
u
x
W
3·5
u
x
x
x
x
mem
0
0
reg
{)
0
x
mem
65
NEe
IIPD70335 (V35 Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
Flags
V
P
S
z
x
x
x
x
x
x
x
x
x
x
x
0
Bytes
AC
CY
W
2
u
x
W
2-4
u
W
2
u
W
2-4
u
W
3
u
W
3-5
u
W
2
u
x
0
W
2-4
u
x
0
W
2
u
x
x
x
x
W
2-4
u
x
x
x
x
W
3
u
u
x
x
x
W
3-5
u
x
u
x
x
x
W
2
x
x
W
2-4
Shift (cont)
SHR
reg, 1
mem, 1
reg,CL
mem,CL
reg,imm8
mem,imm8
SHRA
reg, 1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
CY ... LSB of reg, reg ... reg -:- 2
When MSB of reg ;c bit following MSB
ofreg:V ... 1
When MSB of reg = bit following MSB
of reg: V ... 0
CY ... LSBof(mem), (mem) ... (mem) -:- 2
When MSB of (mem) ;c bit following MSB
of(mem):V ... 1
When MSB of (mem) = bit following MSB
of(mem):V ... 0
0
0
0
0
mem
0
0
0
0
0
x
u
x
x
x
u
x
x
x
x
x
reg
0
0
0
mem
0
mod
u
reg
0
0
0
0
reg
0
0
0
0
0
0
0
reg, 1
mem,1
0
0
0
mod
mem
0
0
0
0
0
reg
0
0
0
0
mod
66
CY ... MSBofreg, reg ... regx2 + CY
MSBofreg;c CY:V ... 1
MSB of reg = CY:V ... 0
CY ... MSB of (mem),
(mem) ... (mem) x 2 + CY
MSBof(mem);c CY:V ... 1
MSBof(mem) = CY:V ... 0
x
reg
0
mem
Rotation
ROL
x
mem
mod
temp ... imm8, while temp ;c 0,
repeat this operation, CY ... LSB of reg,
reg ... reg -:- 2, temp ... temp-1
MSB of operand does not change
temp ... imm8, whiletemp;c 0,
repeatthisoperation,CY ... LSBof(mem),
(mem) ... (mem) -:- 2, temp ... temp-1
MSB of operand does not change
0
0
0
temp ... CL, while temp ;c 0,
repeatthis operation, CY ... LSB of reg,
reg ... reg -:- 2, temp ... temp-1
MSB of operand does not change
temp ... CL, while temp ;c 0,
repeatthisoperation,CY ... LSBof(mem),
(mem) ... (mem) -:- 2, temp ... temp-1
MSB of operand does not change
0
0
mod
0
mem
0
CY ... LSB of reg, reg ... reg -:- 2, V ... 0
MSB of operand does not change
CY ... LSB of (mem), (mem) ... (mem) -:- 2,
V ... 0, MSB of operand does not change
0
0
0
0
reg
0
0
mod
temp ... imm8, while temp ;c 0,
repeat this operation, CY ... LSB of reg,
reg ... reg -:- 2, temp ... temp-1
temp ... imm8, while temp ;c 0,
repeat this operation, CY ... LSB of (mem),
(mem) ... (mem) -:- 2, temp ... temp-1
0
0
temp ... CL, while temp ;c 0,
repeatthis operation, CY ... LSB of reg,
reg ... reg -:- 2, temp ... temp-1
temp ... CL, whiletemp;c 0,
repeatthisoperation, CY ... LSBof(mem),
(mem) ... (mem) -:- 2, temp ... temp-1
0
0
0
0
0
0
0
mod
0
0
0
0
0
0
reg
0
0
0
mem
x
NEe
pPD7033S (V3S Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
AC
Flags
V
P
0
Bytes
W
2
W
2-4
u
W
3
u
W
3-5
CY
S
Z
Rotation (cont)
ROL
reg,CL
mem,CL
reg,imm8
mem,imm8
ROR
reg, 1
mem, 1
reg,CL
mem,CL
reg,imm8
mem,imm8
temp +- CL, whiletemp;lO 0,
repeat this operation, CY +- MSB of reg,
reg +- reg x 2 + CY,
temp +- temp-1
0
0
temp +- CL, while temp ;10 0,
repeat this operation, CY +- MSB of (mem),
mod
(mem) +- (mem) x 2 + CY,
temp +- temp-1
temp +- imm8, while temp ;10 0,
repeatthis operation, CY +- MSB of reg,
reg +- regx2 + CY,
temp +- temp-1
temp +- imm8, while temp ;10 0,
repeatthis operation, CY +- MSB of (mem),
(mem) +- (mem) x 2 + CY,
temp +- temp-1
mod
CY +- LSB of reg, reg +- reg -;.. 2,
MSB of reg +- CY
MSB of reg ;10 bitfollowing
MSBofreg:V +-1
MSB of reg = bit following
MSBofreg:V +- 0
CY +- LSB of (mem), (mem) +- (mem) -;.. 2,
MSBof(mem) +- CY,
MSB of (mem) ;10 bitfollowing
MSBof(mem):V +- 1
MSB of (mem) = bit following
MSBof(mem):V +- 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
mod
0
mem
0
0
0
0
0
0
0
0
x
u
W
1m
x
0
W
2-4
x
x
W
2
x
u
W
2-4
x
W
3
u
W
3-5
u
reg
0
0
0
0
0
mem
0
0
0
mem
mem
0
0
0
reg
0
0
u
reg
0
0
mod
0
0
0
x
reg
0
0
mod
temp +- imm8, while temp ;10 0,
repeat this operation, CY +- LSB of reg,
reg +- reg -;.. 2, MSB of reg +- CY,
temp +- temp-1
temp +- imm8, while temp ;10 0,
repeatthis operation, CY +- LSB of (mem),
(mem) +- (mem) -;.. 2,
temp +- temp-1
0
0
0
0
0
temp +- CL, while temp ;10 0,
repeat this operation, CY +- LSB of reg,
reg +- reg -;.. 2, MSB of reg +- CY,
temp +- temp-1
temp +- CL, while temp ;10 0,
repeat this operation, CY +- LSB of (mem),
(mem) +- (mem) -;.. 2, MSB of (mem) +- CY,
temp +- temp-1
0
0
0
0
0
reg
0
0
0
mem
67
NE€
.
pPD7033S (V3S Plus)
...• . . ! . ":(;;' ..
Instruction Set (cont)
Operation Code
Mnemonic Operand
Operation
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Flags
V P
0
Bytes
W
2
W
2-4
W
2
W
2-4
W
3
u
W
3-5
u
W
2
x
W
2-4
W
2
W
2 c4
W
3
W
3-5
AC
CY
Rotate
ROLC
reg, 1
mem, 1
reg,CL
mem,CL
reg,imm8
mem,imm8
RORC
reg, 1
mem, 1
reg,CL
mem,CL
reg,imm8
mem,imm8
68
tmpcy +-CY,CY +- MSBofreg,
reg +- reg x 2 + tmpcy
MSB of reg = CY:V +- 0
MSB of reg ;.:: CY: V+-1
tmpcy +- CY, CY +- MSB of (mem),
(mem) +- (mem) x 2 + tmpcy
MSBof(mem) = CY:V +- 0
MSBof(mem);.:: CY:V +- 1
mod
temp +- CL, while temp ;.:: 0,
repeat this operation, tmpcy +- .CY,
CY +- MSB of reg, reg +- reg x 2 + tmpcy,
temp +- temp-1
temp +- CL, while temp;.:: 0,
repeat this operation, tmpcy +- CY,
CY +- MSB of (mem),
(mem) +- (mem) x 2 + tmpcy,
temp +- temp-1
mod
temp +- imm8, while temp;.:: 0,
repeat this operation, tmpcy +- CY,
CY +- MSB of reg, reg +- reg x 2 + tmpcy,
temp +- temp-1
temp +- imm8, while temp;.:: 0,
repeatthis operation, tmpcy +- CY,
CY +- MSBof(mem),
(mem) +- (mem) x 2 + tmpcy
temp +- temp - 1
0
0
. mod
tmpcy +- CY, CY +- LSBofreg,
reg +- reg -7 2, MSB of reg +- tmpcy,
MSB of reg;.:: bit following
MSBofreg:V +-1
MSB of reg = bit following
MSBofreg:V +- 0
tmpcy +- CY,CY +-LSBof(mem),
(mem) +- (mem) -7 2,
MSB of (mem) +- tmpcy,
MSB of (memj ;.:: bit following MSB
of (mem): V+-1
MSB of (mem) = bit following MSB
of(mem):V +- 0
0
0
0
0
0
0
0
0
0
0
0
0
0
mem
0
0
0
0
0
0
x
x
u
reg
0
0
x
mem
0
0
0
0
0
reg
0
0
0
mem
0
0
u
reg
0
mod
x
. mem
0
0
u
reg
reg
0
mod
0
mem
0
0
mod
temp +- imm8, while temp ;.:: 0,
repeat this operation, tmpcy +- CY,
CY +- LSBofreg, reg +- reg -7 2,
MSBofreg +- tmpcy, temp +- temp-1
temp +- imm8, while temp ;.:: 0,
repeat this operation, tmpcy +- CY,
CY +- LSBof(mem), (mem) +- (mem) -7 2,
MSBof(mem) +- tmpcy, temp +- temp-1
0
reg
0
temp +- CL, while temp ;.:: 0,
repeatthisoperation, tmpcy +- CY,
CY +- LSB of reg, reg +- reg -7 2,
MSB of reg +- tmpcy, temp +- temp-1
temp +- CL, whiletemp;.:: 0,
repeatthisoperation, tmpcy +- CY,
CY +- LSB of (mem), (mem) +- (mem) -72,
MSB of (mem) +- tmpcy, temp +- temp-1
0
0
0
0
0
0
0
mem
u
S
z
NEe
IIPD70335 (V35 Plus)
Instruction Set (cont)
Mnemonic Operand
7
Operation
6
Operation Code
5 4
3 2
0
Bytes
0
3
AC
CY
Flags
V P
5
Z
Subroutine Control Transfer
CALL
near-proc
(SP-1,SP-2) +- PC,SP +- SP-2,
PC +- PC + disp
regptr16
(SP-1, SP-2) +- PC, SP +- SP-2,
PC +- regptr16
memptr16
(SP-1, SP-2) +- PC, SP +- SP-2,
PC +- (memptr16)
far-proc
(SP-1,SP-2) +- PS,
(SP-3, SP-4) +- PC,
SP +- SP-4, PS +- seg, PC +- offset
memptr32
(SP-1,SP-2) +- PS,
(SP-3, SP-4) +- PC,
SP +- SP-4, PS +- (memptr32 + 2),
PC +- (memptr32)
pop-value
pop-value
0
2
0
reg
mod
0
0
mem
0
0
2-4
0
0
5
2-4
mod
+ 1, SP), SP +- SP + 2
mem
0
0
0
0
0
0
0
0
PC +- (SP + 1, SP), PS +- (SP + 3, SP + 2),
SP +- SP + 4
0
0
0
PC +- (SP + 1, SP), PS +- (SP + 3, SP + 2),
SP +- SP + 4, SP +- SP + pop-value
0
0
0
PC +- (SP + 1, SP),
SP +- SP + 2, SP +- SP
0
0
0
PC +- (SP
RET
0
1,
0
3
0
3
1m
+ pop-value
Stack Manipulation
PUSH
POP
mem16
(SP-1, SP-2) +- (mem16),
SP +- SP-2
2-4
mod
reg16
(SP-1, SP-2) +- reg16, SP +- SP-2
0
sreg
(SP-1, SP-2) +- sreg, SP +- SP-2
0
PSW
(SP-1,SP-2) +- PSW,SP +- SP-2
0
0
0
0
0
R
Push registers on the stack
0
0
(SP-1,SP-2) +- imm,
SP +- SP - 2, When S = 1, sign extension
0
0
mem16
(mem16) +- (SP + 1, SP), SP +- SP
+ 1, SP), SP +- SP + 2
reg16
reg16 +- (SP
sreg
sreg +- (SP + 1, SP), sreg : SS, DSO, DS1
SP +- SP + 2
PSW
PSW +- (SP
R
Pop registers from the stack
0
0
0
mod
0
0
0
0
+ 1, SP), SP +- SP + 2
mem
0
reg
sreg
imm
+2
0
0
0
0
0
0
0
0
0
S
0
2-4
mem
0
reg
0
0
0
0
0
0
2-3
sreg
R
0
0
0
0
0
PREPARE imm16, immS
Prepare new stack frame
0
0
0
0
DISPOSE
Dispose of stack frame
0
0
0
0
0
R
R
R
R
R
4
69
pPD7033~
NEe
(V3S Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
3 2
5 4
Flags
0
Bytes
Branch
BR
near-label
PC +- PC
+ disp
0
0
short-label
PC +- PC
+ ext-disp8
0
0
regptr16
PC +- regptr16
memptr16
3
0
2
2
0
0
reg
0
0
mem
2-4
PC +- (memptr16)
mod
far-label
P8 +- seg, PC +- offset
memptr32
P8 +- (memptr32 + 2),
PC +- (memptr32)
o.
0
0
5
2-4
mod
mem
0
Conditional Branch
BV
short-label
if V
= 1, PC
+- PC
+ ext-disp8
0
0
0
0
BNV
short-label
if V
= 0, PC
+- PC
+ ext-disp8
0
0
0
0
BC,Bl
short-label
ifCY
= 1, PC
+- PC
+ ext-disp8
0
0
0
BNC,BNl short-label
if CY
= 0, PC
+- PC
+ ext-disp8
0
0
0
BE,BZ
if Z
= 1, PC
+- PC
+ ext-disp8
0
0
0
if Z
= 0, PC
+- PC
+ ext-disp8
0
0
0
BNH
short-label
if CY OR Z
= 1 , PC+-
BH
short-label
if CY OR Z
= 0, PC
BN
short-label
if 8
= 1 , PC
0
0
+- PC
+ ext-disp8
0
0
+ ext-disp8
+- PC
0
0
0
BP
short-label
if 8
= 0, PC
+- PC
+ ext-disp8
0
0
short-label
if P
= 1 , PC
+- PC
+ ext-disp8
0
0
= 0, PC +-
+ ext-disp8
0
0
short-label
if P
short-label
if 8 XOR V
= 1, PC
+- PC
+ ext-disp8
0
0
BGE
short-label
if 8 XOR V
= 0, PC
+- PC
+ ext-disp8
0
0
BlE
short-label
if (8 XOR V) OR Z
= 1, PC
+- PC
+ ext-disp8
0
BGT
short-label
if (8 XOR V) OR Z
= 0, PC
+- PC
+ ext-disp8
0
DBNZNE
short-label
CW +- CW-1
if Z = 0 and CW
DBNZE
DBNZ
short-label
short-label
+-
PC
+ ext-disp8
CW +- CW-1
if Z = 1 and CW;o: 0, PC +- PC
+ ext-disp8
CW +- CW-1
if CW ;0: 0, PC +- PC
+ ext-disp8
+ ext-disp8
BCWZ
short-label
if CW = 0, PC +- PC
BTClR
sfr,imm3,
short-label
if bit no. imm3 of (sfr) = 1,
PC +- PC + ext-disp8,
bit no. imm3 or (sfr) +- 0
70
0
2
0
2
0
2
0
2
0
2
0
2
2
2
2
1
0, PC
2
2
BPO
BlT
;0:
0
2
0
BPE
PC
2
2
short-label
+ ext-disp8
2
2
0
BNE,BNZ short-label
PC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
0
2
2
5
0
0
0
AC
CY
V
P
S
Z
NEe
pPD70335 (V35 Plus)
Instruction Set (cont)
Mnemonic Operand
7
Operation
6
Operation Code
5 4
3 2
Flags
0
Bytes
AC
CY
V
P
S
Z
R
R
R
R
R
Rm
R
R
R
R
R
R
Interrupt
BRK
3
(SP-1, SP-2) +(SP-3, SP-4) +(SP-5, SP-6) +IE +- 0, BRK +- 0,
PS +- (15,14), PC
imm8
(~3)
BRKV
PSW,
PS,
PC, SP +- SP-6,
0
0
0
(SP-1, SP-2) +- PSW,
(SP-3,SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0,
PC +- (nx4 + 1, nx4),
PS +- (n x 4 + 3, n x 4 + 2) n = imm8
0
0
0
WhenV= 1
(SP-1,SP-2) +(SP-3, SP-4) +(SP-5, SP-6) +IE +- 0, BRK +- 0,
PS +- (19, 18), PC
0
0
0
0
0
+- (13, 12)
RETRBI
PC +- Save PC, PSW +- Save PSW
reg16,
mem32
0
+- (17, 16)
PC +- (SP + 1, SP),
PS +- (SP + 3, SP + 2),
PSW +- (SP + 5, SP + 4),
SP +- SP + 6
CHKIND
2
PSW,
PS,
PC, SP +- SP-6,
RETI
FINT
0
0
Indicates that interrupt service routine
to the interrupt controller built in the
CPU has been completed
0
When (mem32) > reg16 or
(mem32 + 2) < reg16
(SP-1,SP-2) +- PSW,
(SP-3, SP-4) +- PS,
(SP-5, SP-6) +- PC, SP +- SP-6,
IE +- 0, BRK +- 0,
PS +- (23,22), PC +- (21,20)
0
0
0
0
0
0
0
0
0
2
0
0
0
0
0
0
2
0
0
reg
mod
0
0
0
2-4
mem
CPU Control
HALT
CPU Halt
STOP
CPU Halt
BUSLOCK
Bus Lock Prefix
0
0
0
0
0
0
0
FP01
(Note 1)
fp-op
0
No Operation
0
Y
fp-op,mem
data bus +- (mem)
FP02
(Note 1)
fp-op
No Operation
y
0
y
fp-op,mem
data bus +- (mem)
Y
Y
y
y
0
0
y
y
0
mod
y
0
0
y
y
0
0
0
X
X
X
Z
Z
Z
X
X
2-4
X
2
X
0
mod
0
0
2
mem
Z
Z
Z
X
2-4
mem
Notes:
(1) Does not execute but does generate an interrupt.
71
t\'EC
pPD70335 (V35 Plus)
Instruction Set (cont)
Mnemonic Operand
Operation
7
6
Operation Code
5 4
3 2
Flags
0
Bytes
AC
CY
V
P
x
x
x
x
S
z
CPU Control (cont)
'0
POLL
Poll and Wait
0
0
NOP
No Operation
0
0
01
IE +- 0
0
EI
IE +- 1
0
OSO;OS1;
PS;SS
Segment Override Prefix
0
0
0
0
0
0
0
sreg
0
Register Bank Switching
MOVSPA
BRKes
MOVSPB
reg16
reg16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
0
0
0
3
0
0
0
3
0
0
reg
TSKSW
reg16
0
3
0
0
0
reg
72
0
x
NEe
NEC Electronics Inc.
JlPD70327 (V25 Software Guard)
16-Bit Microcomputer:
Software-Secure, Single-Chip, CMOS
Description
o Internal 256-byte RAM memory
The p.PD70327 (V25 Software Guard) is a highperformance, 16-bit, single-chip microcomputer with an
a-bit external data bus. The p.PD70327 is fully software
compatible with the p.PD70108/116 (V20®/30®) as well as
the p.PD70320/330 (V25 ™/35 TM).
o 1-megabyte memory address space; 64K-byte I/O
space
The p.PD70327 allows external executable code to be
encrypted by a user-defined translation table. The
p.PD70327 will automatically decode the encrypted opcodes internally before the instructions are moved into
the instruction execution register. As a result, the
p.PD70327 offers identical performance to the standard
V25 even during security mode operation. The security
feature may be selected by hardware and/or software,
and may be switched from one state to the other under
software control.
The p.PD70327 has the same complement of internal
peripherals as the standard V25 and maintains compatibility with existing drivers. Other than the additional
mode select pin, the p.PD70327 also maintains pin compatibi lity with other members of the standard V25 family.
Note:The electrical specifications of the V25 Software
Guard and the standard V25 are the same. The instruction sets are also the same except for (BRKS and BRKN
added to control the Security and Normal operational
modes. For electrical specifications and standard instructions, refer to the ~PD70320/322 (V25) Data Sheet.
Features
o Security and normal operational modes
o System clock speeds to a MHz (16-MHz crystal)
o 16-bit CPU and internal data paths
o Functional compatibility with V25
o Software upward compatible with p.PDa086
o New and enhanced V-Series instructions
o 6-byte prefetch queue
o Two-channel on-chip DMA controller
o Minimum instruction cycle: 250 ns at a MHz
V20 and V30 are registered trademarks of NEC Corporation.
V25 and V35 are trademarks of NEC Corporation.
50185-1
o Eight internal RAM-mapped register banks
o Four multifunction I/O ports
- 8-bit analog comparator port
- 20 bidirectional port lines
- Four input-only port lines
o Two independent full-duplex serial channels
o Priority interrupt controller
- Standard vectored service
- Register bank switching
- Macroservice
o Pseudo SRAM and DRAM refresh controller
o Two 16-bit timers
o On-chip time base counter
o Programmable wait state generator
III
o Two standby modes: STOP and HALT
Ordering Information
Part Number
,uPC 70327L-8-xxx
GJ-8-xxx
Clock (MHz)
Package
8
84-pin PLCC
8
94-pin plastic QFP
·
t-{EC
.
"
pPD70327 ·(V25 Software Guard)
Pin Configurations
84-PinPLCC
PT7
P07/CLKOUT
DO
73
PT6
01
72
PT5
02
71
PT4
03
70
PT3
04
69
PT2
05
68
PT1
06
67
PTO
07
66
P17/REAOY
Ao
65
P16fSCKO
A1
64
P15 fTOU:!....-
A2
6.3
P14I1NTfPO~
A3
62
P13I1NTP2IINTAK
A4
61
P1211NTP1
A5
60
P1111NTPO
A6
59
P10/NMI
A7
58
P27/HLORO
A8
57
P26/HLOAK
A9
56
A10
55
P25~
P24/0MAAK1
54
P23/0MAR01
A11
I'~
co 01 0 .... t\I C'l
~
~
LO LO LO LO
Notes:
(1) Pin functions are Identical to jJ.P070320.
(2) All IC pins should be tied together and pulled up to V DO with a
10- to 20-k.Q resistor.
83SL-7039B
2
NEe
pPD70327 (V25 Software Guard)
94-Pin Plastic QFP
§
~
Q
O~~=~~~~MN~O~~~~MN~O~~
-1
o---t>--i
Serial
Register
l<=i
TxBO
Buffer
~
Serial
Register
~I
RxBO
Buffer
~
Transmit
Control
I
RxCO
SCKO
Channel 1
TxD1
RxD1
~
o-----t>-1
Serial
Register
l<=i
Serial
Register
~I
TxB1
Buffer
~
RxB1
Buffer
~
CTS1
RxC1
83SL·7028A
NEe
pPD70327 (V25 Software Guard)
Figure 17. Serial Communication Mode Registers
(SCM)
I
TxRDY
I
RxB
I
I
I
PRTY1 PRTYO CLTSK §LRsc3 MD1
7
I
MDO
Figure 18. Serial Communication Control
Register (SCC)
I
o
0
Transmitter Control
TxRDY
o
o
Disabled
Enabled
1
PRTY1-PRTYO
o
o
0
1
0
1
1
1
CLTSK
o
Parity Control
No parity
o parity (Note
1)
Odd parity
Even parity
Character Length (Async Mode)
Tx Shift Clock (I/O Interface Mode)
7 bits (Async)
No effect (I/O intfc)
8 bits (Async)
Trigger transmit (I/O intfc)
SLRSCK
o
Stop Bits (Async Mode)
Receiver Clock (I/O Interface Mode)
1 stop bit (Async)
Ext clock input on CTSO (I/O intfc)
2 stop bits (Async)
Int clock output on CTS1 (I/O intfc)
MD1-MDO
o
o
0
1
1
x
Mode
I/O interface (Note 2)
Asynchronous
Reserved
Notes:
(1) Parity is 0 during transmit and ignored during receive.
(2) I/O interface mode only.
(3) Channel 0 only.
o
I PRS3 I PRS2 I PRS1 I PRSo
Baud Rate Generator Input Clock Frequency
0000
0001
0010
0011
0100
0101
0110
01 11
1000
Receiver Control
RxB
o
o
PRS3-PRSO
Disabled
Enabled
1
o
7
fSCLKl2 (n = 0)
fscuq'4
fscLKl8
fscLKl16
fSCUQ32
fscLKl64
fSCUQ128
fSCUQ256
fscLKl512 (n = 8)
Figure 19. Serial Communications Error Register
(SCE)
RxDn
I
0
o
o
o
ERP
R xDn
ERF
ERO
o
7
Receive Terminal State
0, 1
Status of RxD pin
o
No error
Transmit and receive parity are different
- - - ERP
Parity Error Flag
1
ERF
o
1
ERO
o
1
Framing Error Flag
No error
Stop bit not detected
Overrun Error Flag
No error
Data is received before receive buffer outputs previous
data
DMA CONTROLLER
The #-,PD70327 has a two-channel, on-chip Direct Memory Access (DMA) controller. This allows rapid data
transfer between memory and auxiliary devices. The
DMA controller supports four modes of operation, two
for memory-to-memory transfers and two for I/O to
memory; in all cases, transfer direction is programmable.
Memory-to-Memory Transfers
In the single-step mode, a Single DMA request will
commence the alternation of one DMA cycle with one
CPU cycle until the prescribed number of transfers
(terminal count) is reached. Interrupts are accepted
while in this mode.
19
III
~
pPD70327 '. (V25.Software' .Guard)
Alternatively, ttl. the bursLmode, one' DMA req~est
causes DMA transfer cycles'to continue consecutively
until the DMA terminal count decrements to zero. Software can initiate memory-to-memory transfers.
Figure 21. ' DMA,Address Contrt)' Registers
(DMAC)
o
o
I PD1
o
PDo
o
PSo
o
7
I/O:-Jo-Memory Transfers
The single tr:ansfer· mode 'will. yield~exactly one DMA
transfer per DMA request. After the transfer, the bus is
returned to the CPU. Alternatively, in demand release
mode, the rising edge of DMARQ enable DMA cycles
which continue while the DMA 're.qI,Jest remains active.
DMA Registers
Figures 20 and 21 show the DMA mode registers (DMAM)
and the DMA address control registers (DMAC).
In i:lll modes: the TC (Terminl:!1 Count)' output pin' will
pulse low and a DMA end-of-service int~rrupt request
will be internally generated after the programmed number of transfers have been completed. The bottom of
internal RAM contains all the necessary address information for the deSignated DMA channels~ .J:he DMA
channel mnemonics are as follows. '
.
Terminal count
Source address register
Source address. register high
Destination (;!,ddressregister
Destination address'regis.ter high
TC
SAR
SARH
DAR
DARH
MD1 I MOo I .' w
'
I
lEOMA TDMAI,
0
No modification.
Increment
Decrement
No modification
11
Source Address Offset
00
01
10
No modification
Increment
Decrement
No modification
11
These control regis.ters (figure 22) are mappec;l into .the
same area of regis,ter bank 0 as the macroservice control
block registers. Thesemacroservice channels should
not be used when the DMA controller is active.
The DMA controller generates .the physical source and
destination addresses by offsetting Address High register 12 bi.ts to .the left, and .then, adding .the Addre~s
register: The source and des.tinationaddress registers
can be programmed to incre,men.t or decrement independently for DMAoperation. ,
Figure 22. DMA Channels
o
o
7
TC1
Transfer Mode,
Single-step (memory to memory)
Oemand release (I/O to memory)."
Demanc:t rel~ase (memory to I/O)
Reserved'
000
001
010
011
SARH1
I
w
Transfer Method
DARO
Byte transfer .'
Word transfer
SARO
1
TDMA
o
o
1
20
Transfer Condition
DiSabled
Maintain condition
' Start DMA transfer
Channel 1
SAR1
Burst (l1)emory to memory)
Single-transfer (110 to memory) .
, Single-transfer (memory to liD)
Reserved
o
xxEOEH
DARH1
DAR1
100
101
110
,1 1 1
EDMA
",
When the EOMA bit is set, the in.ternal DMARQ flag is
cleared. Therefore, subsequent requests are recognized
only after the EDMA bit has been set.
Figure 20. DMA Mode Regis.tersiQlfAAf) ,'
MD2
Destination Address Offset
00
01
10
TCO
SARHO
I
Channel 0
DARHO
xxEOOH
If§ I~
~ 1I::::
I\Q
Ol
' ° a:
Q
<0
'-
>~~
U
Q ~
N
c..
All IC pins should be tied together and pulled up to V DO with a
10- to 20-kO resistor.
83SL~7'9B
2
NEe
pPD79011
94-Pin Plastic QFP
~~~c;;~~~I0~~~~~;o~~:e::::!elert~~
A12
NC
A13
A14
A15
A16
A17
A18
A19
RxDO
GND
CTSO
TxDO
RxD1
P05
NC
69
IC
68
P04
67
P03
66
P02
65
P01
64
POo
63
IC
62
MREQ
61
IOSTB
60
MSTB
59
RIW
58
~
RESET
57
CTS1
56
TxD1
P20/0MARQO
IC
VDD
~
P21/DMAAKO
NC
P22ITCO
71
70
55
VOD
VOD
54
X2
53
X1
52
GND
51
GND
50
NC
49
~ ~ ~ ~ ~ ~ g M ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~48
Note:
NC
~H
AIlIC pins should be tied together and pulled up to VDD with a
10- to 20-kQ resistor.
83SL~7~B
3
NEe
pPD7,9011.
Pin Identification
Symbol
Function
Address bus outputs
CLKOUT
System clock output
PIN FUNCTIONS
Ao-A19 (Address Bus)
Ao-A'9 is the 20-bit address bus used to access all
external devices.
Clear to send channel 0 input
Clear to send channel 1 input
CLKOUT, (System Clock)
Bidirectional data bus
This is the internal system clock. It can be used to
synchronize external devices to the CPU.
I/O strobe output
Memory request output
Memory strobe output
POa-PO;
I/O portO'
P101NMI
Port 1 input line; nonmaskable interrupt
CTSn, RxDn, TxDn, SCKO (Clear to Send,
Receive Data, Transmit Data, Serial Clock Out)
Port 1 input lines; Interrupt requests from
peripherals 0 and 1
The two serial ports (channels 0 and 1) use these lines
for transmitting and receiving data, handshaking, and
serial clock output.
P131'INTP2/INTAK
Port 1 input I,ine; Interrupt requests from
peripheral 2; Interrupt acknowledge output
00-07 (Data Bus)
P1,JINT/POLL
I/O port 1; Interrupt request input; I/O poll input
00-07 is the a-bit external data bus.
P151'TOUT
I/O port 1; Timer out
P1s1SCKO
I/O port 1; Serial clock output
DMARQn, oMAAKn , TCn (DMA' Request, DMA
Acknowledge, Terminal Count)
I/O port 1; Ready input
P201DMARQO
I/O port 2; DMA request 0
I/O port 2; DMA acknowledge 0
I/O port 2j DMA terminal count 0
These are the control signals to and from the on-chip
OMA controller.
.
H LDAK (Hold Acknowledge)
P231'DMARQl
I/O port 2; DMA request 1
P2,JDMAAK1
I/O port 2; DMA acknowledge 1
P251'TCl
I/O port 2; DMA terminal count 1
P2s1HLDAK
I/O port 2; Hold acknowledge output
H LORQ (Hold Request)
I/O port 2; Hold request input
The HLORQ input. (active high) is used by external
devices to request the CPU to release the system bus to
an external bus master. The following lines go into a
high-impedance state with internal 4.7-kO pullup resistors: Ao-A19' 00- 0 7, MREQ, RiW, MSTB, REFRQ, and
IOSTB.
PTO-PT7
Comparator port input lines
Refresh pulse output
The HLOAK output (active low) informs external devices
that the CPU has released the system bus.
RESET
Reset input
RxDO
Serial receive data channel 0 input
RxD1
Serial receive data channel 1 input
R/W
Read/write output
INT (Interrupt Request)
TxDO
Serial transmit data, channel 0 input
TxDl
Serial transmit data, channel 1 input
INT is a maskable, active-high, vectored request interrupt. After assertion, external hardware must provide the
interrupt vector number.
Xl, X2
Crystal connection terminals
Voo
Positive power supply voltage
INTAK (Interrupt Acknowledge)
Threshold voltage input for comparator
GND
Ground reference
IC
Internal connection
4
After INT is asserted, the CPU will respond with INTAK
(active low) to inform external devices that the interrupt
request has been granted.
NEe
pPD79011
INTPO·INTP2 (External Interrupt)
PTO ·PT7 (Comparator Port)
INTPO-INTP2 allow external devices to generate interrupts. Each can be programmed to be rising or falling
edge triggered.
PTO-PT7 are inputs to the analog comparator port.
10STS (I/O Strobe)
10STS is asserted during read and write operations to
external I/O.
MREQ (Memory Request)
MREQ (active low) informs external memory that the
current bus cycle is a memory access bus cycle.
MSTS(Memory Strobe)
MSTS (active low) is asserted during read and write
operations to external memory.
NMI (Nonmaskable Interrupt)
NMI cannot be masked through software and is typically
used for emergency processing. Upon execution, the
interrupt starting address is obtained from interrupt
vector number 2. NM I can release the standby modes
and can be programmed to be either rising or falling
edge triggered.
POo·P07 (Port 0)
POO-PO? are the lines of port 0, an 8-bit bidirectional
parallel I/O port.
READY (Ready)
After READY is de-asserted low, the CPU synchronizes
and inserts at least two wait states into a read or write
cycle to memory or I/O. This allows the processor to
accommodate devices whose access times are longer
than normal execution.
REFRQ (Refresh)
This active-low output pulse can refresh nonstatic RAM.
It can be programmed to meet system specifications
and is internally synchronized so that refresh cycles do
not interfere with normal CPU operation.
RESET (Reset)
A low on RESET resets the CPU and all on-chip peripherals. RESET can also release the standby modes. After
RESET returns high, program execution begins from
address FFFFOH.
R/W (Read/Write)
RiW output allows external hardware to determine if the
current operation is a read or a write cycle. It can also
control the direction of bidirectional buffers.
TOUT (Timer Out)
TOUT is the square-wave output signal from the internal
timer.
P10·P17 (Port 1)
The status of P1o-P13 can be read but these lines are
always control functions. P1 4-P1? are the remaining lines
of parallel port 1; each line is individually programmable
as either an input, an output, or a control function.
X1, X2 (Crystal Connections)
The internal clock generator requires an external crystal
across these terminals. By programming the PRC register, the system clock frequency can be selected as the
oscillator frequency (fosd divided by 2,4, or 8.
P20·P27 (Port 2)
Vee (Power Supply)
P20-P2? are the lines of port 2, an 8-bit bidirectional
parallel I/O port. The lines can also be used as control
signals for the on-chip DMA controller.
Two positive power supply pins (VDD) reduce internal
noise.
POLL (Poll)
VTH (Threshold Voltage)
Upon execution of the POLL instruction, the CPU checks
the status of this pin and, if low, program execution
continues. If high, the CPU checks the level of the line
every five clock cycles until it is low. POLL can be used
to synchronize program execution to external conditions.
The comparator port uses this pin to determine the
analog reference point. The actual threshold to each
comparator line is programmable to VTH x n/16 where n
= 1 to 16.
5
IDI
NEe
pPD.79011
GND (Ground)
IC (Internal Connection)
Two ground connections reduce internal noise.
All Ie pins should be tied together and pulled up to Voo
with a 10- to 20-kO resistor.
p.PD79011 Block Diagram
P20/DMAROO
P21/DMAAKO
P22 rrco
P23/DMARQ1
RESET
P2 4 /DMAAK1
HLDAKlP26
P2srrC1
HLDROip27
READY/P17
TxDO
MREO
RxDO
MSTB
P16/SCKO
Internal ROM
(OS)
CTSO
TxD1
RiW
10STB
POLUINT/P14
RxD1
CTS1
P10/NMI
Instruction Decoder
P11/1NTPO
Micro Sequencer
P12/1NTP1
Micro ROM
P13/1NTP2
IINTAK
P14/1NT
IPOLL
X1
X2
TOUT/P1S
6
REFRO CLKOUT/P0 7
PO
P1
P2
PTO-PT7
VTH
VDD
GND
83YL·5792B
NEe
pPD79011
Comparator Characteristics
ELECTRICAL SPECIFICATIONS
TA
Absolute Maximum Ratings
TA = 25°C
Supply voltage, Voo
-0.5 to 7.0 V
Input voltage, VI
-0.5 to Voo+0.5 (::;; +7.0 V)
Output voltage, Vo
-0.5 to Voo + 0.5 (::;; +7.0 V)
Threshold voltage, VT H
-0.5 to Voo +0.5 (::;; +7.0 V)
Output current low, IOl
Output current high, IOH
Each output pin 4.0 mA (Total 50 mA)
Each output pin -2.0 mA (Total -20 mA)
Operating temperature range, TOPT
-40 to +85°C
Storage temperature range, TSTG
-65 to + 1500C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
= -10 to
+70°C; voo
=
+5.0 V ±10%
Parameter
Symbol
Accuracy
VACOMP
Min
Max
Unit
±100
mV
Threshold voltage
VTH
0
Voo+0.1
V
Comparison time
tCOMP
64
65
tCYK
PT input voltage
VIPT
0
Voo
V
Capacitance
TA
=
25°C; Voo
=
0V
Parameter
Input capacitance
Output capacitance
110 capacitance
Symbol
Max
Unit
Conditions
CI
10
pF
Co
20
pF
CIO
20
pF
f = 1 MHz;
unmeasured
pins returned
to ground
Min
DC Characteristics
TA = -10 to +70°C; voo = +5.0 V ±10%
Parameter
Symbol
Supply current, operating mode
1001
Supply current, HALT mode
Min
1002
Typ
Max
Unit
Conditions
43
100
mA
fCLK
58
120
mA
fCLK
17
40
mA
fCLK
21
50
mA
fCLK
10
=
=
=
=
5 MHz
8 MHz
1m
5 MHz
8 MHz
Supply current, STOP mode
1003
30
p,A
Input voltage, low
Vil
0
0.8
V
Input voltage, high
VIH1
2.2
Voo
V
VIH2
0.8 x Voo
Voo
V
RESET, P101NMI, X1, X2
0045
V
IOL = 1.6mA
V
= -OAmA
= 0 to Voo
All except P101NMI; VI = 0 to Voo
Vo = 0 to Voo
VTH = 0 to Voo
Output voltage, low
VOL
Output voltage, high
VOH
Input current
liN
Voo - 1.0
±20
p,A
Input leakage current
III
±10
p,A
Output leakage current
ILO
±10
p,A
VTH supply current
ITH
Data retention voltage
VOOR
0.5
2.5
1.0
mA
5.5
V
All except RESET, P101NMI, X1, X2
IOH
P101NMI; VI
7
NEe
pPD79011
Supply Current vs Clock Frequency
External System Clock Control Source
150
Internal Oscillator
TA = 25°C
Voo = 5 V
140 I - -
Typ. Sample
130
splc. Point
120
110
Spec.
Point
100
90
<"
Note: For a parallel resonant quartz crystal,
C 1, C2 = 15 pF (recommended)
80
§.
c
E 70
60
50
40
/
V V
30
V
V
~
External Clock
~
Clock
X1
X2
20
83SL~718A
10
o
o
Recommended Oscillator Components
4
Ceramic Resonator
fCLK [MHz]
B3-004331A
Capacitors
Manufacturer
Product No.
C1 (pF)
C2 (pF)
Kyocera
KBR-10.0M
33
33
Murata Mfg.
CSA.10.0MT
47
47
CSA16.0MX040
30
30
FCR10.M2S
30
30
FCR16.0M2S
15
6
TDK
AC Characteristics
TA
= -10 to
+70°C; VD D
=
+5.0V ±10%
Parameter
Symbol
Min
VDD rise, fall time
tRv'D, tFVD
200
Input rise, fall time
tlR, tlF
20
ns
Except X1, X2, RESET, NMI
Input rise, fall time (Schmitt)
tlRS, tlFS
30
ns
RESET, NMI
Output rise, fall time
tOR, tOF
20
ns
Except C LKOUT
X1 cycle time
tcyx
98
250
ns
5-MHz CPU clock
62
250
ns
8-MHz CPU clock
tWXL
35
ns
5-MHz CPU clock
20
ns
8-MHz CPU clock
20
ns
5-MHz CPU clock
20
ns
8-MHz CPU clock
X1 width, low
X1 width, high
twxH
X1 rise, fall time
tXR, tXF
CLKOUT cycle time
tCYK
8
125
Max
Unit
Conditions
p.s
STOP mode
20
ns
8-MHz CPU clock
2000
ns
fx/2, T = tCYK
NEe
pPD79011
AC Characteristics (cont)
Parameter
Symbol
Min
CLKOUT width, low
tWKL
O,5T -15
CLKOUT width, high
tWKH
O,5T -15
CLKOUT rise, fall time
tKR' tKF
Address delay time
tOKA
Address valid to input data valid
15
Max
Unit
Conditions
ns
Note 1
ns
15
ns
90
ns
ns
tOAOR
T(n+1,5) - 90
MREQ to data delay time
tOMRO
T(n+1) -75
ns
MSTB to data delay time
tOMSO
T(n+O,5) -75
ns
tOMRTC
O,5T+50
ns
0,5+35
ns
MREQ to TC delay time
tOMRMS
O,5T -35
MREQ width, low
tWMRL
T(n+1) -30
Address hold time
tHMA
O,5T -30
ns
Input data hold time
tHMoR
0
ns
MREQ to MSTB delay time
ns
Next control setup time
tscc
T -25
ns
TC width, low
tWTCL
2T-30
ns
Address data output
tOAOW
O,5T +50
ns
MREQ delay time
tOAMR
O,5T -30
ns
MSTB delay time
tOAMS
T -30
ns
MSTB width, low
tWMSL
T(n+O,5) - 30
ns
Data output setup time
tSOM
T(n+1) -50
ns
Data output hold time
tHMOW
O,5T -30
ns
IOSTB delay time
tOAIS
O,5T -30
ns
10STB to data input
tDlSO
10STB width, low
tWISL
T(n+1) - 30
ns
Address hold time
tHISA
O,5T -30
ns
Data input hold time
tHISOR
0
ns
tSOIS
T(n+1) -50
ns
tHISOW
O,5T -30
Output data setup time
Output data hold time
Next DMARQ setup time
T(n+1) -90
1m
ns
ns
T
tSDAOQ
Note 2
ns
Demand mode
ns
Demand mode
DMARQ hold time
tHOAOQ
0
DMMK read width, low
tWOMRL
T(n+1,5) -30
DMMK to TC delay time
tOOATC
DMMK write width, low
twoMWL
T(n+1) - 30
ns
RE F RQ delay time
tOARF
O,5T -30
ns
RE F RQ width, low
tWRFL
(n+1)T - 30
ns
Address hold time
tHRFA
D,5T -30
ns
RESET width, low
tWRSL 1
30
ms
STOP mode release; poweron reset
RESET width, low
tWRSL2
5
p.s
System warm reset
MREQ, IOSTB to READY setup time
tSCRY
ns
n ;;:: 2
MR'EO, iOSTB to READY hold time
tHCRY
ns
n ;;:: 2
ns
O,5T+50
T(n -1) -100
T(n -1)
ns
9
NEe
pPD79011
AC Characteristics (cont)
Parameter
Symbol
H LDAK output delay time
tOKHA
Bus control float to H LDAK J.
tCFHA
T-SO
ns
HLDAK Ho control output time
tOHAC
T -so
ns
H LDRQ J. to cont rol output time
tOHQC
3T +30
H LDAK width, low
tWHAL
HLDRQ setup time
tSHQK
HLDRQ to HLDAK delay time
tOHQHA
H LDRQ width, low
tWHQL
1.ST
INTP, DMARQ setup time
tSIQK
30
ns
INTP, DMARQ width, high
tWIQH
8T
ns
INTP, DMARQ width, low
tWIQL
8T
ns
tSPLK
30
ns
p's
POLL setup time
NMI width, high
Min
Max
Unit
80
ns
ns
T
ns
ns
30
3T+160
ns
ns
tWNIH
S
NMI width, low
tWNIL
S
p.s
CTS width, low
tWCTL
2T
ns
INTR setup time
tSIRK
30
ns
INTR hold time
tHIAIQ
0
ns
INTAK width, low
tWIAL
2T-30
ns
INTAK delay time
tOKIA
INTAK width, high
tWIAH
INTAK to data delay time
tOIAO
INTAK to data hold time
tHIAO
0
SCKO cycle time
tCYTK
1000
SCKO (TSCK) width, high
tWSTH
4S0
ns
SCKO (TSCK) width, low
tWSTL
4S0
ns
80
T-30
ns
ns
2T -130
ns
O.ST
ns
ns
TxD delay time
tOTKO
TxD hold time
tHTKO
20
ns
eTSO (RSCI<) cycle time
tCVRK
1000
ns
eTSO (RSCI<) width, high
tWSRH
420
ns
eTSO (RSCI<) width, low
tWSRL
420
ns
RxD setup time
tSRoK
80
ns
RxD hold time
tHKRO
80
ns
Notes: (1) T = CPU clock period
(tcvKl
210
(2) n = number of wait states inserted
STOP Mode Data Retention Characteristics
TA = -10 to +70°C
Parameter
Symbol
Min
Max
Data retention voltage
VO OOE
2.5
5.5
Voo rise time
tLFVO
200
p.s
VOO fall time
tFVO°C
200
p's
10
Unit
V
ns
Conditions
NEe
pPD79011
Timing Waveforms
Stop Mode Dlltll Retention Timing
AC InDUt Kttveform 2 {RESET JI NUl}
~
VOO
VOOOR
0.8 V
IRVO
83-004333A
AC Input Waveform 1 (Except XI, X2, RESET, NUl)
4V
2.
0.4 V
4
l-"FS
IIRS
83-004306A
AC Output Test Point (Except CLKOUT)
4
2.2 V
0.8 V
0.8 V
IIR
83-00430SA
!=-IOF
lOR
83-004307A
Clock In Ilnd Clock Out
0.8 VOO
0.8 V
CLKIN1
[X1]
~----ICYX----..I
-
I--
IKR
-1\
..
I-IKF
2.2 V
CLKOUT
IIJ
IWKH
IWKL
ICYK
0.8 V
83-0043088
11
NEe
pPD79011
Memory Read
I~--------B1------~~1--------B2------~
CLKOUT
_{t------=:\'--------I:K-)~\'__________'I
tOKA_
)~
r
-
.
tOAOR
It
It
tHMOR ..
I-tOMRO-
R/Vi
K
I
tOAMR
I
tWMRL
I
\k:
tscc-
I{
1\
l.tOMSO.
-tOMRMS-
i
\
tOAMS- I-tWMSL-!
~
i\
I+-tOMRTC
TC1-TCO
\1+---1-
-~(
--tWT-CL-
83-004309C
12
NEe
I'P.D79011
Memory Write
1 - - - - B 1 - - - - + . - I - - - - B2 - - - - - - - - 1
eLKOUT
~I+-------\-----.,,'K).......---..--\~!
_
. ___
IOKA-
A19- A O
K
)
I+-tOAOW-
I_IHMA-+
~
07-00
~
ISOM
R/W
.
I
~tHMDWy
\
IWMRL
\-IOAMj
"
-
1/
Isee--,-----..
1\
!--IOMRMS-
r\
MSTB
IOAMS---,---+
1/ "
~ IWMSL-
1\
\
i-IoMRTe
TC1-TCO
\I----~.~IW-TeL---------+l(
83-00431OC
13
NEe
pPD79011
I/DRead
II
B1
tCYK
I
B2
"I
CLKOUT
..J
~
K
)L
I---tOAOR_
r-tHISA1
~
tOISO
R/iii
J
f\
I+-tOA1S-1
'I
tWISL
tscc-
I
l\-
i\.
DMAAK1
DMAAKo
83-004311C
14
NEe
pPD79011
I/O Writ.
CLKOUT
B1
I
ICYK
I
I
B2
I
J
~
A19-AO
K
)
10AOW
rIHISA .....
07-00
If
ISOIS
R/W
.
IHISOW
V
\
1\
,
!--IOAIS .....
IWISL
. I----tsccII
1\
i\
83-004312C
15
NEe
pPD79011
OMit, I/O to Memory
I~--------B1--------~I---------B2~----~
}=~-------tCYK-------l+t
eLKOUT
.---IL---\~---'!"""-----""\~---'!-\,",-----JI
\
tOKA-
R/W
}
X
\
V
tWMRL
I+-tOAMR-
I-o-tHMA-
II
1\
tscc
I+-tOMRMS-
..
1\
lJ
1\
tOAMS-
~tWMSL_
1\
[+--tSOAOO_
DMARQODMARQ1
~
I+-tHOAOO .....
II
''I
tWOMRL
rx
I+- tOOATC-
I
tWTCL
J
I
83-004313C
16
1tIEC
DM~
pPD79011
Memory to I/O
~-------B1--------+-----~-B2-------
I+-------ICYK - - - - - - - + l
CLKOUT
_IOKA_
A19- A O
R/W
)
K
J
1\
-tOAMR_
_IHMA _ _
IWMRL
~
1\
1/
ISCC
rx
IOAMS
1\
-'
!--IWMSL-I
r\
_ISOAOO __
DMARQO
DMARQ1
1\
I+-tHOAOO-+
1
"
IWOMWL---l
If\b
j+-1OOATC_
I
IWTCL
_I
83-004314C
17
NEe
pPD79011
Refresh
~-------B1--------~--------B2--------~
'---------tCYK - - - - - - I
CLKOUT
~tDKA-
R/W
)
K
J
~
l\..-
I\.._tDARFj
\
tWRFL
I--tHRFA-
II
tscc
83-004315C
CLKOUT----------------------------------------~,~-J
_---.~I+--.-tWRsL1----.!.~-~lll!--------
RESET
18
----------------
83-0043168
NEe
pPD79011
RESET 2
CLKOUT
__ I~RS"-=, _ _
J
RESET-~
83-0043178
READY 1
~-----B1----~~----BAW----~------BAW-----+------B2-----1
/
READY ______________________
~;'
~~____________________________________________
83-0043188
~
READY 2
r-------------1iiII
~ B1-------1r----- BAW -----+------ BAW -----+----- BW -----+----- B2-----1
MREQ
n=2
n=3
-tHCRY*
tSCRY*
n=2
READY
\
L
In = 3
VI
* tSCRY [READY setup time] and tHCRY [READY hold time] are a function of
T and n. Timings shown are examples for n = 2 and n = 3.
83-0043198
19
NEe
pPD79011
H LORQ/H LlJAK 1
CLKOUT
~KI------+--------l~
HLORQJ
-
,
Bus control'
~-------tDHQHA------~
'A19-AO, 07-00, MREQ, MSTB, IOSTB,
Riw
~--------------tWHAL--------------~
83-0043206
HLORQJHLIJAK 2
CLKOUT
HLORQ
~------tWHQL----~~
Bus control' --r---------it----i----------------~
IOKH:;:-_ _ _ _
--tU~--~~--------------~--------~-t-DH-Q-C--_-_-_-_-~--~~~~~~:-----------
83-0043218
I NTP, OMARQ Input
CLKOUT
INTP,
OMARQ'
~--------------tWIQH------------~
:===============-tW~~IQ-L~------------------------~~
'INTP2-INTPO, OMARQ1-0MARQO
83-0043226
20
NEe
pPD79011
POLL Input
CLKOUT
_~IS'"
I
POLL
83-0043238
Nllllnput
CLKOUT
NMI-1.
tWNIH
h
tWNIL
r
83-004324B
CTSlnput
Em
CLKOUT
CTS1-CTSO~
)
tWCTL
r
83-0043258
21
NEe
pPD79011
INTR/INTAK
CLOOUT
r'~--4---'
INTR
tOKIA
tHIAIQ
07-DO--------------~r----------------+_--------------------------~
83-0043268
Serial Transmit
CLKOUT
tCVTK
\
~
I
tWSTL
)
TxD
J
I
tWSTH
tHTKO
C
tOTKO
83-004441B
22
NEe
pPD79011
Serial Receive
CLKOUT
tCYRK
\
,j
tWSRL
RxD
1\
tWSRH
K
}.
tHKRD
f+---tSRDK -
83-0043326
ARCHITECTURAL DESCRIPTION
The IkPD79011 is an upgraded version of IkPD70322
(V25) , NEC's original single-chip microcomputer. It has a
real-time operating system built into internal ROM.
Figure 1. Memory Map
FFFFF
FFFFO
P[3lliffu3llillilililli3lliillili3lliIq
RESET
Ii
The IkPD79011 is the same as the V25 in both hardware
and software specifications except for the built-in ROM
contents. For more information on the V25, refer to the
IkPD70320/70322 V25 Data Sheet
Memory Map
The IkPD79011 can access a maximum of 1M bytes of
memory via the 20-bit address bus. A 16K-byte segment
of memory (FCOOOH to FFFFFH) is allocated to the
on-chip ROM. The IkPD79011 operating system is stored
in this ROM area.
FDOOO
FCOOO
An external memory area of 2K bytes (FB 800H to
FBFFFH) contains a configuration table. When reset, the
IkPD79011 starts program execution at address
FFFFOH, and performs the necessary initialization according to the information in this table. Then, program
control is passed to each user-defined task.
User's Initial Task
[System Setup. etc.) ~--lf-----'
User's Area
A 1K-byte area (OOOOOH to 003FFH) contains the vector
tables. Thus, the total area for user tasks is from 00400H
to FB7FFH.
Address determined at
configuration time.
Figure 1 is the IkPD79011 memory map.
00400
t - - - - -........- - - - i
Vector Table
00000'--_ _ _ _ _ _ _ _--'
49TB-516A
23
NEe
pPD79011
Reset Operation
Table 1.
When reset, the p,PD79011 begins program execution at
address FFFFOH and jumps to the reset routine, which
performs the following processing.
Vector
Number
Start
Address
72 to 79
00120H
External p.PD71059
(Slave 1. Available for use)
•
•
•
•
•
80 to 87
00140H
External p.PD71059
(Slave 2. Available for use)
88 to 95
00160H
External p.PD71059
(Slave 3. Available for use)
96 to
103
00180H
External p.PD71059
(Slave 4. Available for use)
After completing the required reset processing, the
p,PD79011 jumps to the operating system dispatch routine, and then passes the program control to each
user-defined task.
104 to
111
001AOH
External p.PD71059
(Slave 5. Available for use)
112 to
119
001COH
External p.PD71059
(Slave 6. Available for use)
Figure 2 is a flowchart of system operation at reset time.
120 to
127
001EOH
External p.PD71059
(Slave 7. Available for use)
Figure 2. Reset Operation Flowchart
128 to
255
00200H
Available for use
Initializes special registers
Initializes the interrupt vector table
Generates the system table
Specifies both semaphore and mail box areas
Generates and starts tasks
~ctor
Table Area Assignments (cont)
Use
Note: Vectors 56 to 127 are aSSigned to the master and slave interrupt
controllers when added to the p.PD79011. Otherwise, the area is free
to be used.
RESET
Configuration Table
The configuration table resides in memory from FB 800H
to FBFFFH. The reset routine obtains initialization information from the configuration table. Any items not initialized by the reset routine must be initialized by the
user initial task.
Table 2 is an example of a configuration table. It shows
the assembler sources (described by RA70116). The
input values in the table are only examples.
Table 2. Configuration Table, Filing Example
49TB-517A
Data Type
Example Value
INTERNAL RAM_ BASE
PTR1
OW
OW
TASK...CNT
PTR2
OW
SMA-CNT
PTR3
OW
MBOK-CNT
INTERNAL
RAM_BASE
DB
FFH
46H
Interrupt Vectors
PTRO
Up to 256 interrupt vectors (4 bytes/vector) can be
stored in the vector table area. See table 1.
Table 1.
~ctor
Table Area Assignments
Vector
Number
Start
Address
Use
DB
o to 31
OOOOOH
Reserved for hardware as on p.PD70322 (V25)
OW
1000H
32 to 47
00080H
Avai lable for use
OW
OW
2000H
48
OOOCOH
Operating system data table
49 to 55
OOOC4H
Available for use
56 to 63
OOOEOH
External p.PD71059 (Master. Available for use)
64 to 71
00100H
External p.PD71059 (Slave O. Available for
use)
24
BLK...SIZE
2FCOH
Notes
2
3
tyEe
Table 2.
pPD79011
conf~uration Table~
(co.nt
"
CONF_TBL
Data Type
Filing Example
Example Value
Notes
4
PORTO
DW
1000H
PORT1
DW
2000H
PORT2
DW
OFFFFH
PORT3
DW
CiF'FFFH
PORT4
DW
OFFFFH
PORT5
DW
OFFFFH
PORT6
DW
OFFFFH
PORT?
DW
OFFFFH
PORT8
DW
OFFFFH
TASK..CNT
DB
2BH
MIN_TASK..NO
DB
0
INIT_TASK
DB
0
IDL~SP
DW
1000H
IDL~SS
DW
OFOOOH
INILPCO
DW
OOOOH
INILPSO
DW
4000H
INILSPO
DW
2000H
INILSSO
DW
OFOOOH
I NILD SO
DW
2000H
INILPC1
DW
1000H
INILPS1
DW
4000H
INILSP1
DW
3000H
INILSS1
DW
OFOOOH
INILDS1
DW
2000H
SMA-CNT
DW
2
INILRSCO
DW
DW
10H
MBOx...CNT'
DW
10H
RESEFNE
DW
OOH
CONF_TBL
ENDS
END
Notes:
(1) Pointers
(2) Systeminformati,on
(3) RAM information
(4) Interrupt controller information
Pointers
A pointer is an offset value obtained using a segment
value of OFB08H. The following pointers are provided.
The organization of the configuration table changes
according to user system status.
Pointer
PTRO
PTR1
PTR2
PTR3
Size
1 word
1 word
1 word
1 word
Points to
INTERNALRAM:...BASE
TASK-CNT
SM~CNT
MBOx..CNT
System Information
5
6
?
User
Task
0
INTERNALRAM_BASE: This byte is required to se~ the
internal RAM base segment of the JLPD79011. It is specified in the internal data area base register (lOB address
OFFFFFH).
If XXH is specified as the IDB value (where' X is a
hexadecimal number), the internal RAM base segment is
assumed to be XXOOH. Therefore, each register bank and
the special function register (including lOB) are assigned ~
to the 512-byte area starting at address XXEOOH.
II.i&I
PRC_INFO. This byte sets the processor control register
(PRC), wh,ich has the following functions.
7
User
Task
1
• System clock divider of oscillator frequency
• Interval of time base interrupt
• Enable/disable of internal RAM
RAM Information
8
9
The configuration table provides the following RAM information.
LOW_DS/HIGH_OS: These two words specify the user
free RAM area. Because it is a continuous memory area,
both the upper and lower limit segment addresses (offset
0) must be used to specify this area.
The initialize routine sets the system table and each
control block in this RAM area .. Any remaining, control
blocks are queued in the system table as memory blocks
(the section System Calls provides more information).
The user free RAM area must be large enough to hold all
control blocks.
(5) User task information
(6) Idle task stack information
(7) User task register information
(8) Semaphore/mail box information
(9) Reserved area
25
NEe
pPD79011
Bues IZE: This word of information specifies the memory block size in units of 16 bytes. If BLK....S IZE of zero is
specified, no memory blocks are generated.
Interrupt Controller
INIT_DSO: This word of information specifies the initial
value of the data segment (DS) for the first user task.
The above set of register initial values is repeated for
each user task.
PORTO th rough PORT8 (9 words) provide the information
required when one or more external interrupt controllers
(J,.t.PD71059) are connected to J,.t.PD79011.
Semaphore/Mail box
PORTO specifies the port address for the master interrupt controller. PORT1 through PORT8 specify the port
addresses corresponding to the slave interrupt controllers (0 to 7).
INIT_RSCO: This word of information supplies the initial
number of resources for semaphore O. After specification
of semaphore 0, the initial number of resources of all
other semaphores should be specified sequentially.
If fewer than nine interrupt controllers are used, OFFFFH
indicates the addresses of the unused interrupt controllers.
MBO)LC NT: This word of information specifies the number of mail boxes (up to 256) to be used.
SMA...CNT: This word of information specifies up to 256
semaphores to be used.
Reserved Area
User Task Information
RESERVE is a one-word area. You must specify a value of
TASK....CNT: This byte of information specifies the total
number of user tasks (except for idle tasks). Up to 63
tasks can be specified.
o for RESERVE.
MIN_TASICNO: User task numbers are assigned sequentially starting from this number, the mimimum task
number. Only tasks with numbers greater than the minimum task number are generated.
Table 3 shows the various task statuses. Figure 3 shows
all task status changes.
INIT_TASK: This byte of information indicates the number of the first task that the operating system must
execute when the system is initialized. All other tasks are
dormant when the system is initialized.
Task Status and Status Change
Table 3. Task Status
Status
Meaning
RUN
One task, given priority to use the CPU, is
currently being executed.
READY
A task is ready to execute. A READY task has a
priority lower than the task currently under
execution and is hence blocked by the priority
handler.
WAIT
A task is waiting for an event to occur so it can
go into the READY status. This status is caused
by the following conditions:
WAIT - a system call caused the status change
and the task is either waiting for a resource with
a semaphore, waiting for a message (through
mail box or direct connection), or waiting for an
interrupt.
SUSPEND
The system call SUS_TSK suspended execution
forcibly when the task was in the RUN status.
The task must wait for a system call to restart
execution
WAIT SUSPEND
A task was forcibly moved Into the WAIT status
and has a double wait status. If the system call
RSM_TSK is issued to a task in the WAIT
SUSPEND status, the task is released from the
SUSPEND status and goes into the WAIT
status. If released from the WAIT status, the task
goes into SUSPEND status.
DORMANT
When the system is initialized, only one task
goes into the READY state. All other tasks go
into the DORMANT status. If the system call
EXLTSK is issued to a task that is executing,
this task becomes DORMANT.
Id Ie Task Stack
IDLE_SP: This word of information specifies the idle task
stack pointer (SP) value.
IDLE-SS: This word of information specifies the idle tas~
stack segment (SS) value. When a stack is set, any value
can be used for the address. The stack area must be a
minimum of 32 bytes.
User Task Register Initialization
INIT_PCO: This word of information specifies t~e initial
value of the program counter (PC) in relation to the
mini mum user task number specified for MIN_TASK-NO.
INIT_PSO: This word of information specifies the initial
value of the program segment (PS) for the first user task.
INIT_SPO: This word of information specifies the initial
value of the stack pointer (SP) for the first user task.
INIT_SSO: This word of information specifies the initial
value of the stack segment (SS) for the first user task.
26
NEe
Figure 3.
pPD79011
Task Status Change
End
Start
The remaining tasks, numbered 6 to 63, are all assigned
to bank 6. These tasks, unlike tasks resident in banks,
require processing time to swap the task state to register
bank 6.
Table 4 shows the register banks and tasks.
Table 4. Register Banks and Corresponding
Tasks
Register Bank
Task
*Priorlty
Type
o
0
o
Resident
2
2
2
3
3
3
4
4
4
5
5
5
6
6 to 63
6 to 63
7
Non-resident
Occupied by I'PD79011 OS
No priority can be set for DMA or macroservice transfer.
Task Management
Idle Task
The p.PD79011 operates an idle task when no user-set
task needs to be executed. The user-specified maximum
number plus 1 is used as the idle task number.
If the idle task begins execution, it executes the HALT
instruction in the Interrupt Enable status, then waits for
an interrupt to be issued.
FUNCTIONAL DESCRIPTION
The p.PD79011 can handle up to 64 tasks numbered and
assigned priorities from 0 to 63. Task numbers and
priority levels correspond to each other. (For example,
task 3 has a task priority of 3.) Level 0 is the highest
priority; level 63 is the lowest priority.
Tasks are scheduled according to their priority levels.
The p.PD79011 selects and executes the READY task
with the highest priority (RUN status).
Like the V25, the p.PD79011 has 8 register banks (numbered 0 to 7). Task switching can be done at a high speed
using these register banks. The operating system occupies bank 7. The remaining banks (0 to 6) are all assigned
to tasks.
Of the 7 register banks, tasks numbered 0 to 5 are
assigned to banks 0 to 5 and are resident in the banks.
Because the bank-resident tasks do not require any
processing to save/return the task status, task switching
can be handled quickly.
The task management function is used to terminate,
start, suspend, restart tasks, and set the restart address.
If system call STA.TSK is issued to a task, the task exits
the DORMANT status and goes into the READY status.
If system call SUS_TSK is issued to a task, the specified
task goes into the SUSPEND status. The task exits the
SUSPEND status when system call RSM_TASK is issued,
and its status becomes READY
The restart address is set by issuing system call
SET....ADA. The SET....ADR is always used with system call
RES_INT to end the interrupt handler. (Refer to the
section Interrupt Management for additional information.)
Synchronization/Communication Management
Tasks are synchronized by queuing or mutual exclusion.
If tasks are queued, they are processed and executed
one at a time.
Mutual exclusion is used in task processing to prohibit
simultaneous access by more than one task to a shared
resource (such as memory, an I/O device, etc.).
The p.PD79011 uses semaphores for task synchronization and mail boxes for intertask communication.
Semaphores
The p.PD79011 implements semaphores to manage resources and for queuing or mutually excluding tasks.
27
~
IiiII
NEe
pPD79011
Both the. Pinstruction .(Obtain Resource) a.nd the V
instruction (Release Resource) manage only one resource at a time.
The P instruction can use the following system calls. "
REQ_RSC: If the request to obtain resource is not accepted, the task goes into;the WA,IT status.
POLRSC: If the request to obtain resource is not accepted, the system is notified that the request has been
rejected.
The V instruction (system call RELRSC) releases the
occupied resource.
Figure 4 shows how to use system calls to avoid simultaneous read and write to shared memory. In figure 4,
both tasks A and B share the same resource (memory).
An interrupt is issued when task A is executed and
control is passed between the two tasks. If the
REQ_RSC request is not accepted because the resource
is used by another task (task A), task B goes into the
WAIT status.
POLMSG: Issued if a message was sent to a mailbox;
notifies the system that no message can be received.
POLDIR: Issued if a message was sent directly; notifies
the system that no message can be received.
Memory Management
You can issue system callsto secure and return memory
blocks dynamically on the p.PD79011. The memory block
size is specified at configuration time.
Task status remains the same and an the error code is
returned when the GET_MEM system call is unable to
secure.a block of memory.
If a memory block is specified as the message area, the
system uses the first two bytes of memory (figure 5).
Consequently, ava:ilable memory (specified in the configuration table) is reduced by 2 bytes.
Figure 5. Memory Block
Figure 4. Mutual Exclusion
User Area
Allocated Memory Block
Addresses
2 Bytes
[Used by OS]
49TB-52OA
Interrupt Management
49TB-519A
Intertask Communication
Tasks communicate with each other in one of two ways,
directly and nondirectly . Each task has a mailbox with a
task queue for receiving·messages and a message queue
for sending messages. No mailbox is required-for direct
communication. Messages c~m be. sent directly from one
task to another.
If a task cannot receive a message for any reason (either
directly or in a mailbox), onecf the following syst~m
calls is issued.
RCV_MSG: Issued if a message was sent to a mailbox;
..
the task goes into WAIT status.
RCV_DIR:lssued if a message was sent directly; the task
goes into the WAIT status.
"28
Fo( internally and externally generated· ii'lterrupt requests, RTOS has the following functions to support the
associated interrupt service routines~
•
•
•
•
Interrupt handler assignment
Interrupt handler return
Interrupt enable/disable.
interrupt wait status
When DE F_I NT is issued; a correspondence is set between the request level(br vector type) of an external
p.PD71059 interrupt controller and the starting address
of its service routine.
The ENA.:JNT and DIS_JNT calls allow interrupts to be
enabled or disabled.
NEe
pPD79011
The SIG_INT and RES_INT system calls terminate the
interrupt handler and pass control to the top-queued
task (queued by the WAUNT call).
Figure 6 shows how SIG_INT passes control to a task.
The following events occur in the figure.
• Due to WAUNT, task B waits for an interrupt.
• An interrupt is issued while task A is running.
• SIG_INT is issued to task B at the end of interrupt
handling.
If the priority of task A is higher than that of task B,
control is passed to task A when SIG_INT is executed
(the interrupted task). If the priority of task B is higher,
control is passed to task B.
Figure 6. SIa.lNT Examples
TaskS
I
,/ Interrupt Handler"
Task A
Interrupt ___
k'/
,/
,/,/,/
""
"
""
WAUNT
The RES_INT system call is always used with the SET_
ADR system call to set the restart address. If SET-ADR
has already been issued in an interrupted task handler
that issues RES_INT, RES_INT passes control to the
restart address specified by SET-ADR, not to the address where the interrupt was issued.
Figure 7 shows how to use the RES_INT system call to
pass control to a task.
Figure 7. RES_INT Example
SET_ADR (Restart_Address) Interrupt _
Re'tart_Add,,,,
L----
Interrupt Handler
-
-
-
-
-
-
-
-l
Ir------------
The JLPD79011 provides the following types of system
calls.
•
•
•
•
•
Task management
Synchronization/communication management
Memory management
Time management
Interrupt management
The system calls all have ID numbers assigned to them.
Descriptions of system calls include their syntax and
any error codes that may be returned to the task when
the call is issued.
You can use the C language or assembly language to
develop programs for the I-I-PD79011. If using the C
language, an error code is returned as a function value of
the system call. If using assembly language, an error
code is returned to the AW register of the JLPD79011 as a
return parameter.
C Language Interface
"
83YL-6775A
Task
SYSTEM CALLS
The JLPD79011 supports the C language, a high-level
language for developing large or small programs. To
issue system calls in the C language, an assembler
routine is required as an interface between the I-I-PD79011
operating system and the C language. Refer to the
Assembly Language Interface section for details on writing the interface.
Following is the syntax use for issuing calls in the C
language.
err = < name> ([ < parameter>));
Argument
err
< parameter>
Description
Function value returned by RTOS
7-letter System Call Name
Input parameter
Assembly Language Interface
The JLPD79011 has a C language-oriented architecture.
Therefore, when issuing system calls using assembly
language, the I-I-PD79011 always sends and receives
parameters via a stack. (If the system call requires no
parameters, no stacking is needed.)
RES_INT
49TB-S22A
The syntax for issuing system calls using assembler and
loading the stack for operation are shown below. If the
parameter is a pointer, the offset value is stacked in the
lower address area of the stack, and the segment val ue is
stacked in the upper address area.
29
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pPD79011
(1) Parameter.
err = (arg1, arg2, arg3);
Argument
arg1
arg2
arg3
Description
7-letter System Call Name
unsigned int
int
unsigned int
I/O
In
An intersegment system call is needed even when the
RTOS_ENTRY address is within the same segment.
Figure 8. Stacking Conditions
SS : SP Always necessary to
I
arg3
indicate this position
immediately before
RTOS _ ENTRY
(FOOO:COOO) is called
between segments
Segment Value of arg2
Description
Task number (0 to 62)
(2) Return val ue.
The system call is issued in the following sequence.
• Parameter 3 (arg3) is stacked.
• Parameter 2 (arg2) is stacked.
• Parameter 1 (arg1) is stacked.
• A pOinter to the parameter area is stacked.
• The system call number is set in the AW register.
• RTOS_ENTRY (FCOOOH) is called between segments.
_
Parameter Area Pointer
t-----------I
arg1
Offset Value of arg2
Name
int taslLno;
Error Code
E_OK
E_DMT
Number
o
1
Description
Normal end
Task is not DORMANT
(3) C format.
short taslLno;
ercode = STA-TSK(taslLno);
STA-TSK can only be issued to a task that is in the
DORMANT status.
The started task processing is done in one of the following ways .
• Executed for the first time.
• After it is terminated once, it is restarted.
If a task is executed for the first time, the task processing
starts from the initial address. Initial values from the
configuration table are also used for the stack pointer,
stack segment, and data segment values. Other register
values are not defined.
High
The procedures for issuing the SIG_INT and RES_INT
system calls are different. They are explained later in this
data sheet.
If the task processing is ended once and then restarted,
the task also resumes at the initial address. In this case,
the stack pointer, stack segment, data segment values,
and other register values assume the values they had
just before the EXT_TSK system call was issued.
TASK MANAGEMENT SYSTEM CALLS
Exit Task (EXT_T5K)
The following system calls are used for task management.
System Call 1. EXT_TSK terminates task processing
and moves the task into the DORMANT status from the
RUN status. It has the following syntax.
49TB-523A
System Call
STA-TSK
EXT_TSK
SUS_TSK
RSM_TSK
SET-ADR
Description
Starts task processing
Terminates task processing
Suspends task processing
Restarts task processing
Sets restart address
int EXT_TSK ()
(1) Return value.
Error Code
E_OK
Number
o
Description
Normal end
(2) C format.
Start Task
(ST~TSK)
System Call O. STA-TSK starts task processing during
which the task goes into the READY status from the
DORMANT status. It has the following syntax.
int STA-TSK (taslLno)
30
ercode = EXT_TSK();
If STA-TSK restarts a task in the DORMANT status (due
to EXT_TSK) , the start address returns to the initial
value. Other register values retain the values they had
when EXT_TSK was issued. Thus, the stack pointer,
stack segment, data segment values may not match the
values assumed at configuration time.
fttIEC
pPD79011
Suspend Task (SUS_TSK)
Set Restart Address (SET~DR)
System Call 2. SUS_TSK suspends a task and puts it
into the SUSPEND status. It has the following syntax.
System Call 4. SET-ADR sets the restart address of a
task. It has the following syntax.
int SUS_TSK (taslLno)
int SET-ADR (restarLadr)
(1) Parameter.
I/O
In
(1) Parameter.
Name
int taslLno;
Description
Task number (0 to 62)
(2) Return val ue.
Error Code
E_OK
E_DMT
E_SUS
In
Name
int (restarLadr);
Description
Task restart address
(2) Return val ue
Number
0
1
2
Description
Normal end
Task is DORMANT
Task is in SUSPEND status
Error Code
E_OK
Number
o
Description
Normal end
(3) C format.
ercode = STA-TSK(restarLadr);
pointer restarLadr;
(3) C format.
short taslLno;
ercode = SUS_TSK(taslLno);
SUS_TSK cannot be issued to tasks that are in the
DORMANT status or in the SUSPEND status.
If SUS_TSK is issued to a task in the WAIT status, the task
goes into the WAIT SUSPEND status.
Resume Task (RSM_TSK)
System Call 3. RSM_TSK restarts a task that is in the
SUSPEND status. It has the following syntax.
int RSM_TSK (taslLno)
SELADR is always used in conjunction with the RES_INT system call. If RES_INT is issued on return from the
interrupt handler, control is passed to the restart address
set previously by SET-ADR.
SELADR can be issued more than once, but the system
only validates the last restart address that was issued.
Setting the restart address to 0 clears current restart
address.
SYNCHRONIZATION/COMMUNICATION
MANAGEMENT SYSTEM CALLS
The following system calls are used for synchronization/
communication management:
(1) Parameter.
I/O Name
Description
In int taslLno; Task number (0 to 62)
(2) Return val ue.
Error Code
E_OK
E_DMT
E_SUS
I/O
System Call
REQ_RSC
POLRSC
Number
o
1
2
Description
Normal end
Task is DORMANT
Task is not in SUSPEND
status
(3) C format.
short taslLno;
ercode = RSM_TSK(taslLno);
RSM_TSK cannot be issued to tasks that are in the
DORMANT status or in the SUSPEND status.
If it is issued to a task in the WAIT SUSPEND status, the
task is released from the SUSPEND status and goes into
the WAIT status.
RELRSC
RCV_MSG
POLMSG
SND_MSG
RCV_DIR
POLDIR
SND_DIR
Description
Requests resource from a
semaphore
Requests resource from a
semaphore (no wait)
Releases resource for a semaphore
Receives messages from a mailbox
Receives messages from a mailbox
(no wait)
Sends messages to a mailbox
Receives messages sent to this task
Receives messages sent to this task
(no wait)
Sends messages to the specified
task
Request Resource (REQ_RSC)
System Call 5. REQ_RSC requests a resource from the
specified semaphore. It has the following syntax.
int REQ_RSC (semaphore_no)
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(1) Parameter.
(1) Parameter.
1/0 Name
Description
In int semaphore_no; Semaphore number (0 to
specified number)
(2) Return value.
Error Code
E_OK
1/0 Name
Description
In int semaphore_no; Semaphore number (0 to
specified number)
(2) Return value.
Number
o
Description
Normal end
Error Code
E_OK
Number
o
Description
Normal end
(3) C format.
(3) C format.
ercode = REQ_RSC(semaphore_no);
short semaphore_no;
ercode = RELRSC(semaphore_no);
short semaphore_no;
If REQ_RSC is issued when the resource count is 0, the
task goes into the WAIT status. If the resource count is
more than 1, the resource countis decremented by one.
When RELRSC is issued, the semaphore resource
count is increased by 1. If WAIT tasks exist, the earliestwait task is selected and released from the WAIT status.
Each semaphore has a task queue. But, if REQ_RSC
causes a task to go into the WAIT status, the task is
placed in the last position in the queue regardless of its
priority.
The initial value of the semaphore resource count is set
when the system is started. No error occurs even when
the resource count exceeds the initial value asa result of
issuing RELRSC. If the resource count exceeds 65,535,
the resource count is cleared to 0 automatically and no
error is generated.
Poll Resource (POLRSC)
System Call 6. POLRSC is used to request resources
from the specified semaphore. It has the following syntax.
int POLRSC (semaphore_no)
Receive Message (RCV_MSG)
System Call 8. RCV_MSG receives messages from
mailboxes. It has the following syntax.
int RCV_MSG (mailbo>Lno)
(1) Parameter.
1/0 Name
Description
In int semaphore_no; Semaphore number (0 to'
specified number)·
(1) Parameter.
1/0
In
Name
int mailbo>Lno;
(2) Return value.
Error Code
E_OK
E_RSC
Number
o
6
Description
Normal end
Resource count is 0
(3) C format.
ercode = POLRSC(semaphore_no);
short semaphore_no;
POLRSC is used to determine whether any resources
are left in the specified semaphore. Unlike the REQ_RSC, POLRSC never causes a task to go into the
WAIT status. Instead, it returns the E_RSC error code
when the resource count is O. If the resource count is
more than 1, the count is decremented by 1.
Release Resource (RELRSC)
System Call 7. RELRSC releases resource for the
specified semaphore. It has the following syntax.
int RELRSC (semaphore_no)
32
Description
Mailbox number (0 to
specified number)
(2) C format.
seg = RCV_MSG(mailbo>Lno);
short mailbox....no;
If RCV_MSG is issued when messages are present in
mailboxes, the earliest message is selected and the
segment value of the message area is returned as the
function value.
If there is no message, the task goes into the WAIT status
and it is placed in the last position in the mail box queue.
Poll Message (POLMSG)
System Call 9. POLMSG receives messages from
mailboxes. It has the following syntax.
int POLMSG (mailbo>Lno)
NEe
pPD79011
Receive Direct Message (RCV_DIR)
(1) Parameter.
I/O
In
Name
int mail bO)Lno;
Description
Mail box number (0 to
specified number)
(2) Return value. If there are any messages in the specified mailbox, the message area segment value is
returned. If there is no message, the following error
code is returned.
Error Code
E_MSG
Number
7
Description
No message found
(3) C format.
int RCV_DIR ()
(1) C format.
ercode = RCV_DIR();
If RCV_DIR is issued when there is no message, the task
goes into the WAIT status. If a message is present, the
message area segment value is returned.
Poll Direct Message (POLDIR)
seg = POLMSG(mailbo)Lno);
short mailbo)Lno;
If POLMSG is issued when messages are present in
mail boxes, the earliest message is selected and the
segment value of the message area is returned as the
function value.
If no message is found, unlike the RCV_MSGsystem call,
the task never goes into the WAIT status. Instead, the
E_MSG error code is returned.
Send Message (SND_MSG)
System Call 10. SND_MSG sends messages to mailboxes. It has the following syntax.
int SND_MSG (mailbo)Lno, msg_seg)
(1) Parameter.
I/O Name
Description
In int mailbo)Lno; Mailbox number (0 to
specified number)
In int msg_seg;
Send message area segment
(2) Return value.
Error Code
E_OK
System Call 11. RCV_DIR receives messages sent directly to a task. It has the following syntax.
Number
o
Description
Normal end
(3) C format.
ercode = SND_MSG(mailbo)Lno, msg_seg);
short mailbo)Lno;
short msg_seg;
If SND_MSGis issued when a task is waiting to be
processed, the task is released from the WAIT status, and
the send message area segment value is returned.
If no tasks are in the WAIT status, the message is queued
in the mail box. Like tasks, messages are queued using
the first-in, first-out (FIFO) method.
System Call 12. POLOIR receives messages sent by a
task to itself. It has the following syntax.
int POLDIR ( )
(1) Return value. If POLDIR is issued when a message is
present, .the message area segment value is returned. If no message is present, the following error
code is returned and the task does not enter WAIT
status.
Error Code
E_MSG
Number
7
Description
No message is present
(2) C format.
ercode
=
POLDIR(n);
Send Direct Message (SND_DIR)
System Call 13. SND_DIR specifies a task and sends a
message· to the specified task. It has the following
syntax;
int SND_DIR (task_no, msg_seg)
(1) Parameter.
I/O
In
In
Name
int taslLno;
int msg_seg;
Description
Task number (0 to 62)
Send message area segment
(2) Return val ue.
Number
o
Description
Normal end
(3) C format.
ercode = SND_DIR(task_no, msg_seg);
short taslLno;
short msg_seg;
If SND_DIR is issued when the specified task is waiting
for a message directly, the task is released from the WAIT
status. The message area segment value is returned to
the task.
33
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If the specified task is not waiting for any message
directly, the message is placed in the task message
queue using the FIFO method.
RELMEM cannot release memory blocks containing
messages in a mail box or task queue. The memory block
can only be released after a message is received.
MEMORY MANAGEMENT SYSTEM CALLS
TIME MANAGEMENT SYSTEM CALLS
The following system calls are used for memory management.
The following system calls are used for time management.
System
GET_MEM
RELMEM
Call Description
Gets a memory block
Releases the memory block
System Call
GET_TIM
SET_TIM
Description
Reads the system time
Sets the system time
Get Memory (GET_MEM)
Get Time (GET_TIM)
System Call 14. GET_MEM allocates a memory block. It
has the following syntax.
System Call 16. GET_TIM reads the system time. It has
the following syntax.
int GET_MEM ( )
int GET TIM (time_ptr)
(1) Return value. If a memory block is available when
GET_MEM is issued, the memory block segment
value is returned. If no memory block is present, the
following error code is returned.
Error Code
E_BLK
Number
3
Description
No memory block found
(2) C format.
ercode = GET_MEM();
(1) Parameter:
1/0
In
Name
struct Ltime
struct Ltime{
int Uime;
int m_time;
int h_time;};
(3) Return value.
If the error code is returned, the task never goes into the
WAIT status.
(4) C format.
System Call 15. RELMEM releases the specified memory block. It has the following syntax.
int RELMEM (mem_blk)
(1) Parameter:
1/0 Name
Description
In int mem_blk; Segment value of the released
memory block
(2) Return val ue.
Error Code
E_OK
Number
o
Description
Normal end
(3) C format.
ercode = RELMEM(mem_blk);
short mem_blk;
34
Description
Pointer to location
of system time
(2) Time structure.
GET_MEM can use the memory block as a message area
for intertask communications: The memory block size is
specified when the system is started, and the value is
fixed.
Release Memory (RELMEM)
* time_ptr;
Error Code
E_OK
Number
o
Description
Normal end
ercode = GET_TIM(time_ptr);
pointer time_ptr;
The system time is 3-word data. The lower order word is
stored in the lowest order address; the intermediate data
is in the intermediate address; and the upper order data
is in the highest address.
The minimum resolution of the system time is determined by the value set in the time base counter in the
14PD79011. However, since interrupts to the 14PD79011
are inhibited during system call processing, choose the
minimum resolution of the system time with system call
overhead time in mind.
Set Time (SET_TIM)
System Call 17. SET_TIM sets the system time. It has
the following syntax.
t-IEC
pPD79011
Define Interrupt Handler (DE F_INT)
int SET_TIM (time_ptr)
(1) Parameter.
I/O
In
Name
struct Ltime
* time_ptr;
Description
Time pointer
System Call 18. DEF_INT sets the start address of the
interrupt handler. It has the following syntax.
int DE F_INT (device_no, starLadr)
(1) Parameter.
(2) Time structure.
struct Ltime{
int Uime;
int m_time;
int h_time;};
I/O
In
Name
int device_no;
In
int (starLadr) ();
(3) Return val ue.
Error Code·
E_OK
Number
0
Description
Normal end
(4) C format.
pointer time_ptr;
ercode = SET_TIM (time_ptr);
The p.PD79011 uses the on-chip timer base counter
output as the system real-time clock source .. The onchip timer therefore starts its counting operation when
the system is started.The interval from the SET_TIM call
to the next real-time clock interrupt is an error term
associated with the initial call to SET_TIM, and all
subsequent calls produce additional pseudorandom error times. The real-time clock interval is set at configuration time.
INTERRUPT MANAGEMENT SYSTEM CALLS
The following system calls are used for interrupt management:
System Call
DEF_INT
WAUNT
CAN_INT
DIS_INT
Description
Sets the start address of the
interrupt handler
Starts a task waiting for an
interrupt and terminates the
interrupt handler operation
Waits for an interrupt
Releases a task waiting for an
interrupt from WAIT status
Disables interrupts by device
number
Enables interrupts by device
number
Terminates interrupt handler
operation and calls the restart
address
Description
Device number (interrupt
level or vector type)
Pointer to interrupt
handler start address
(2) Return value.
Error Code
E_OK
E_DVN
E_SYS
Number
o
4
5
Description
Normal end
Device number error
System error
(3) C format.
ercode = DEF_INT(device_no, starLadr);
shCirt device_no;
pointer starLadr;
If DE F_INT is issued, correspondence between interrupt
request level of external p.PD71059 interrupt controller
(or interrupt request vector type) and start address ofthe
interrupt handler is established. When an interrupt, request vector type is specified, the interrupt request
control register can also be set at the same time.
If 0 is specified for the interrupt handler start address,
the existing start address is cleared. If the start address
of the interrupt handler is cleared after an interrupt
request level of the interrupt controller is specified, the
mask bit (IMK) equivalent to the specified interrupt
request level is set and the interrupt is masked. Then the
existing start address is cleared.
If the start address of the interrupt handler is cleared
after an interrupt request vector type is specified, the
existing start address is cleared and the interrupt request control register is set. At this time, the interrupt
mask can be set at the same time by explicitly setting bit
6 of the interrupt request control register.
If the start address of the interrupt handler is not 0, the
address is set with no other changes. The IMK (mask bit)
is never altered.
If the start address of the interrupt handler is set after the
vector type of interrupt request is specified, the interrupt
request control register is also set. Therefore, interrupt
mask operation can be specified using bit 6 of the
interrupt request control register.
35
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IIPD79011
External Interrupt Controller Definition
The interrupt request level of the external interrupt
controller can be specified by setting 0 in bit 7. It is
specified as follows.
Bit(s)
0-2
3
Description
Slave level interrupt request level
If 0, master/slave configuration;
if 1, master only
Master interrupt request level
Fixed to 0
Upper-order byte is fixed to 0
4-6
7
8-15
The low-order byte is used to specify the interrupt level.
Bits 0 to 2 specify the slave interrupt request level when
in master-slave configuration; bit 3, whether to use any
slave device; bits 4 to 6, the master interrupt request
level.
The interrupt request level of the interrupt controller and
each interrupt request vector type are in one-to-onE~
corrrespondence The interrupt request is divided into 72
levels, and they correspond to interrupt request vector
types 56 to 127.
For example, if; the device consists of only the master, 0
is specified for the master interrupt request level; this
interrupt request vector type becomes 56. Slave interrupt request level 7 must be connected to master interrupt request level 7 when in master-slave configuration
and becomes vector type 127.
The interrupt request vector type can be specified by
setting 1 in bit 7. It is specified as follows.
Bit(s)
0-6
7
8-15
Description
Vector type
Fixed to 1
Interrupt request control register value
The J.(.PD79011 operating system uses the on-chip time
base counter as the system timer. As a result, other tasks
cannot specify vector type 31 (equivalent to the time
base counter) when the system timer function is used.
Signal Interrupt (SIG_INT)
System Call 19. SIG_INT activates a task waiting fo~ an
interrupt and terminates the currently executing .interrupt handler. It has the following syntax.
void SIG_INT (taslLno)
(1) Parameter.
I/O
In
36
Name
int task_no;
Description
Target task number (0 to 62)
(2) C format.
ercode = SIG_INT(taslLno);
short taslLno;
SIG_INT can be issued only from inside an interrupt
handler.
If S IG_I NT is issued, the interrupt handler operation ends
and control is passed to the target task. Therefore, when
SIG_INT is used, control is never passed to the address
following S IG_INT.
If an error occurs, no error code is returned and the
specified task is not started. In this cas'e, control is
returned immediately to the point where the interrupt
was issued.
SIG_INT is not used to control multiprocessing of external or internal interrupt requests. Nesting management
related to the interrupt handler and execution of the EOI
(End Of Interrupt) and FINT (Finish Interrupt) instructions must be done in each interrupt handler.
The procedures used to issue SIG_INT (and system call
RES_INT) differ from those to issue other system calls.
When using assembly language, SIG_INT is issued as
follows.
Procedure
PUSH task_no
Description
The target task number is set in
stack
Far jump to absolute address
OFCOOEH
BR SIG_INT_
ENTRY
Wait for Interrupt (WALINT)
System Call 20. WAUNT moves a task into the WAIT
status. It has the following syntax.
int WAUNT ()
(1) Return value.
Error Code
E_OK
E_INT
Number
o
8
Description
Normal end
Release from interrupt
wait status
(2) C format.
ercode = WAUNT;
When issuing this system call, the" current task goes into
the interrupt wait status. If the SIG_INT system call is
issued to a waiting task (which was invoked by WAUNT),
the specified task is released from the WAIT status.
pPD79011
A task can release another task's WAIT (for interrupt)
status by means of the CAN_I NT system call. Otherwise
an interrupt handler will release the WAIT status after an
interrupt is presented.
If SIG_INT is used to release a task from the WAIT status,
the error code E_OK is returned. If CAN_INT is used to
release the WAIT status, the error code E_INT is returned.
Cancel Interrupt (CAN_INT)
System Call 21. CAN_INT releases the specified task
from the WAIT status. It has the following syntax.
int CAN_INT (taslLno)
Name
int taslLno;
To specify the interrupt request level of the interrupt
controller, set the corresponding IMR (mask bit) of the
external n059. To specify the interrupt request vector
type, set bit 6 of the interrupt request control register.
Enable Interrupt (ENAJNT)
System Call 23. ENAJNT enables interrupts in units of
device number (interrupt request level or interrupt request vector type). It has the following syntax.
int ENAJNT (device_no)
(1) Parameter:
(1) Parameter:
I/O
In
DIS_INT can be issued from either a task or an interrupt
handler:
Description
Task number (0 to 62)
(2) Return val ue.
Error Code Number Description
~OK
0
Normal end
E_INT
8
Task is not waiting for interrupt
(3) C format.
ercode = CAN_INT(taslLno);
short taslLno;
I/O
In
Name
int device_no;
Description
Device number
(2) Return value.
Error Code
E_OK
E_DVN
Number
o
4
Description
Normal end
Device number error
(3) C format.
ercode = ENAJNT(device_no);
short device_no;
ENA..JNT can be issued from either a task or an interrupt
handler.
If CAN_INT is issued to a task that is waiting for an
interrupt (due to system call WAUNT) , the specified task
exits the WAIT status. If CAN_INT is issued when the
specified task is not waiting for any interrupt, the E_INT
error code is returned.
To specify the interrupt request level of the interrupt
controller, reset the corresponding IMR (mask bit) of
external 71059. To specify the interrupt request vector
type, reset bit 6 of the interrupt request register.
Disable Interrupt (DIS_INT)
Reset Interrupt (RES_INT)
System Call 22. DIS_INT disables interrupts in units of
device number (interrupt request level or interrupt request vector type). It has the following syntax.
System Call 24. RES_INT terminates interrupt handler
void RES_INT ( )
int DIS_INT (device_no)
(1) C format.
(1) Parameter:
I/O
In
Name
int device_no;
Description
Device number
(2) Return val ue.
Error Code
E_OK
E_DVN
operation and passes control to the restart address. It
has the following syntax.
Number
o
4
Description
Normal end
Device number error
(3) C format.
ercode = DIS_INT(device_no);
short device_no;
ercode = RES_INTO;
RES_INT is always used in conjunction with system call
SELADR.
If SELADR has been already issued in a task that was
interrupted by a handler that issues RES_INT, control is
passed to the specified restart address. If SET....ADR has
not been issued to that task, control is returned to the
pOint where the interrupt was issued.
RES_INT cannot be used to control multiple interrupt
processing, neither for internal nor for external 71059
37
"PD79011
sources. Management of interrupt handler nesting and
the execution of EOI (End Of Interrupt) and FINT (Finish
Interrupt) instructions must be done in each interrupt
handler.
The procedure .for issuing RES_INT (and system call
SIG_INT) differs from the procedure for issuing other
system calls. Use the following syntax to issue RES_INT
using assembly language.
BR RES_INT_ ENTRY; Far jump to absolute
address FC020H
38
t-{EC
NEe
,.,PD79021
16·Bit Microcomputer:
Single-Chip, CMOS,
With Built-In RlOS
NEC Electronics Inc.
Description
The ILPD79021 is an upgraded ILPD70332 (V35™) singlechip microcomputer with a built-in real-time operating
system (RTOS).
The ILPD79021 provides high-speed multitask processing particularly suited for real-time event processing and
as a kernel of an embedded control system for process
control and data processing applications.
The RTOS kernel provides extensive system calls for
task synchronization, control, and communication as
well as interrupt and time management.
The ILPD79021 instruction set is the same as the V35
instruction set. The ILPD79021 hardware is also identical
to the standard V35, but uses 6K of the internal ROM for
RTOS system code. Refer to the V35 Data Sheet for
hardware-related details and the ILPD79011 Data Sheet
for RTOS system call descriptions.
Features
oReal-time multitask processing
o Supports five types of system calls
- Task management
- Communication management
- Memory management
- Time management
-Interrupt management
o High-speed response to events
- System call processing shortens time to 41 ILS
(minimum) when operated at 8 MHz
- High-speed task switching using V35 register
banks
V35 is a trademark of NEC Corporation.
CP/M is a registered trademark of Digital Research, Inc.
MS-DOS is a registered trademark of Microsoft Corporation.
VMS is a trademark of Digital Equipment Corporation.
UNIX is a trademark of AT&T Bell Laboratories.
50184
o Flexibility to perform status changes by event
driven task scheduling function
o System clock: 8 MHz maximum
o V35 hardware compatibility
o CMOS technology
o Development tools
- V35 software can be used without modification
- Relocatable assembler (RA70320)
- C compiler (CC70116)
- Concurrent CP/M@, MS-DOS@, VMSTM, and
UNIXTM base
Ordering Information
Part Number
Clock
Package
,u.PD79021L-S
SMHz
S4-pin PLCC
8 MHz
94-pln plastic QFP
GJ-S
•.
~
NEe
IJPD79021
"PD79021 Block Diagram
AO
Ag/A1-A 16 /A S
A17 /A 1S
P20/DMARQO
A19
P21/DMAAKO
A1S /UBE
P22fTCO
RESET
P23/DMARQ1
HLDAKlP2 6
P2 4 /DMAAK1
HLDRQ/P27
P2SfTC1
READY/P17
MREQ
MSTB
TxDO
RiW
RxDO
10STB
P16/SCKO
Internal ROM
16K Byte
(RTOS)
CTSO
TxD1
POLUINT/P14
RxD1
crst
P10/NMI
Instruction Decoder
P1 1 "NTPO
Micro Sequencer
P12/1NTP1
Micro ROM
P13"NTP2I
INTAK
P14"NTI
POLL
X1
X2
TOUT/P1S
2
REFRQ CLKOUT/P0 7
PO
P1
P2
PTO-PT7
VDD
GND
83YL-5793B
NEe
Peripherals for CPUs
5-1
NEe
Peripherals for CPUs
Section 5
Peripherals for CPUS
"PD71011
5a
Clock Pulse Generator/Driver
"PD71 037
5b
Direct Memory Access (DMA) Controller
"PD71 051
5c
Serial Control Unit
"PD71 054
5d
Programmable Timer/Counter
"PD71 055
5e
Parallel Interface Unit
"PD71 059
5f
Interrupt Control Unit
"PD71 071
59
DMA Controller
"PD71 082, 71083
5h
8-Bit Latches
"PD71 084
5i
Clock Pulse Generator/Driver
"PD71 086, 71087
5j
8-Bit Bus Buffer/Drivers
"PD71 088
5k
System Bus Controller
"PD71641
Cache Memory Controller
5-2
51
NEe
pPD71011
Clock Pulse
Generator/Driver
NEe Electronics Inc.
Description
Pin Configurations
The p.PD71011 is a clock pulse generator/driver for the
V20@N30@ microprocessors and their peripherals using
NEC's high-speed CMOS technology.
IS-Pin Pla.tic DIP
Features
CJ
CJ
CJ
CJ
CJ
CJ
CMOS technology
Clock pulse generator/driver for p.PD70108/70116 or
other CMOS or NMOS CPUs and their peripherals
SO% duty cycle
Frequency source can be crystal or external clock
input
Reset signal with Schmitt-trigger circuit for CPU or
peripherals
Bus ready signal with two-bus system
synchronization
CJ
Clock synchronization with other p.PD71011 s
CJ
Si,ngle +S-volt ±10% power supply
Industrial temperature range: -40 to +8SoC
CJ
Ordering Information
Part Number
~PD71011 C-8
Maximum Clockout
Frequency
8 MHz
C-10
10 MHz
G-8
8 MHz
1
6
VOO
X1
X2
ROYSYN
EXFS
Fix
OSC
RESIN
RESET
83-000196A
2O-Pin Pla.tic SOP
CKYSN
PRClK
NC
RENl
RDYl
READY
RDY2
REN2
ClK
VSS
VDD
Xl
NC
X2
RDYSYN
EXFS
FiX
OSC
RESIN
RESET
m
83ML-6187A
Package
18-pin plastic DIP
20-pin plastic SOP
V20 and V30 are registered trademarks of NEC Corporation
50153
CKSYN
PRClK
REN1
RDY1
READY
RDY2
REN2
ClK
NEe
I'PD71011
Pin Identification
Symbol
Function
CKSYN
Clock synchronization Input
ClK (Processor Clock)
The ClK output supplies the CPU· and its local bus
peripherals' clocks. ClK is a 50-percent duty cycle clock
of one-half the frequency of the external frequency
source. The ClK output is +0.4 V higher than the other
outputs.
PRClK
Peripheral clock output
J=fEN1
Bus ready enable Input 1
RDY1
Bus ready Input 1
READY
Ready output
PRClK (Peripheral Clock)
RDY2
Bus ready Input 2
The PRClK output supplies a 50-percent duty cycle
clock at one-half the frequency of ClK to drive peripheral
devices.
J=fEN2
Bus ready enable Input 2
ClK
Processor clock output
Vss
Ground potential
RESET
Reset output
~
Reset Input
esc
Oscillator output
FIX
External frequency source/crystal select Input
EXFS
External frequency source input
RDYSYiil
Ready $ynchronization select input
X2
Crystal input
X1
Crystal input
Voo
+5-volt power supply
NC
No connection
PIN FUNCTIONS
X1, X2 (Crystal)
OSC (Oscillator)
OSC outputs a Signal at the same frequency as the
crystal input. When EXFS is selected, the OSC output is
powered down, and its output will be a high.
CKSYN (Clock Synchronization)
CKSYN synchronizes one ~PD71011 to other ~PD71011 s.
A high level at CKSYN resets the internal counter, and a
low level enables it to count.
RESIN (Reset)
This Schmitt-trigger input generates the RESET output.
It is used as a power-on reset.
RESET (Reset)
When FiX is low, a crystal connected to X1 and X2 will be
the frequency source for a CPU and its peripherals. The
crystal frequency should be two times the frequency of
ClK.
This output is a reset signal for the CPU. Reset timing is
provided by the RESIN input to a Schmitt-trigger input
gate and a flip-flop which will synchronize the reset
timing to the falling edge of ClK. Power-on reset can be
provided by a simple RC circuit on the RESIN input.
EXFS (External Frequency Source)
RDY1, RDY2 (Bus Ready)
EXFS input is the external frequency input in the external TTL-frequency source mode (FiX high). A square
TTL-level clock signal two times the frequency of ClK's
output should be used for the source.
A peripheral device sends RDY1 or RDY2 to signal that
the data on the system bus has been received or is ready
to be sent. REN1 and REN2 enable the RDY1 or RDY2
signals.
FIX (Frequency/Crystal Select)
REN1, REN2 (Bus Ready Enable)
FIX input selects whether an external TTL-type input or
an external crystal input is the frequency source of the
ClK output. When FIX is low, ClK is generated from the
crystal connected to X1 and X2. When FIX is high, ClK
is generated from an external TTL-level frequency input
on the EXFS pin. At the same time, the internal oscillator
circuit will go into stop mode and the OSC output will be
high.
REN1 and REN2 qualify their respective ROY inputs.
2
1\fEC
pPD71011
RDYSYN (Ready Sychronization Select)
RDYSYN selects the mode of READY signal synchronization. A low-level signal makes the synchronization a
two-step process. This is used when RDY1 and RDY2
inputs are not synchronized to ClK. A high-level signal
makes synchronization a one-step process. This is used
when RDY1 and RDY2 are synchronized to ClK. See
block diagram.
READY (Ready)
The READY signal to the processor is synchronized by
the ROY inputs to the processor ClK. READY is cleared
after the ROY signal goes low and the guaranteed hold
time of the processor has been met.
Figure 1 shows the recommended circuit configuration.
Capacitors C1 and C2 are required for frequency stability. The values of C1 and C2 (C1 = C2) can be calculated
from the load capacitance (CL,) specified by the crystal
manufacturer.
C L-
C1 x C2
C1 + C2
Where CS is any stray capacitance in parallel with the
crystal, such as the p.PD71011 input capacitance CIN.
Figure 1. Crysl., Conligur.,lon CirculI
pPD71011
Crystal
The oscillator circuit of the p.PD71011 works with a
parallel-resonant, fundamental mode, '~T cut" crystal
connected to pins X1 and X2.
83-001577A
I'PD71011 Block Diagram
X1
X2
i----.------------ - - - - - - - 0 osc
PRClK
FIX
EXFS
0--------1
CKSYNo-------------------------~~--+_----r_~
REN1
0-----,
RDY1
0-----'
REN2
0------,
ClK
RDYSYN
RESIN
READY
o----------------------------~
o--------------------~~--------------,
RESET
83-0001978
3
NEe
pPD71011
Absolute Maximum Ratings
DC Characteristics
= -40 to +85°C; voo .. 5 V :t10%
TA = 25°C; VS8 .. 0 v
TA
Power supply voltage, Voo
- 0.5 to
+ 7.0 V
Input voltage, VI
- 1.0 V to Voo + 1.0 V
Output voltage, Vo
- 0.5 V to Voo + 0.5 V
Parameter
Symbol
Input voltage, high
VIH
Input voltage, low
VIL
Storage temperature, T8TG
Output voltage, high VOH
500mW
Power dissipation, Po (SO package)
200mW
Max Unit Conditions
2.6
Operating temperature, TOPT
Power dissipation, Po (DIP)
Min
__2_.2_ _ _ _V
_ _ _ _ __
V
0.8
Voo -0.4
Voo-0.8
Output voltage, low
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage. The device should be operated within the limits specified
under DC and AC Characteristics.
VOL
Input leakage current liN
RESIN input
-1.0
1.0
1.0
V
ClK output,
10H = -4mA
V
10H" -4 rnA
VIOL" 4 rnA
0.45
-400
RESI N input
V
p.A RDYSYN input
V
0.20
hysteresis
Capacitance
TA .. 25°C; Voo = +5 V
Parameter
Symbol
Input capacitance
CIN
Min
Max
Unit
Conditions
12
pF
tc'" 1 MHz
Power supply
current (static)
100
Power supply
current (dynamic)
loodyn
200
30
p.A
rnA fin" 20 MHz
AC Characteristics
=
f08C
10 MHz; TA -40 to +85°C; Voo ... +5 V ± 10%
fOSC = 16 MHz; TA -10 to +70°C; Voo - +5 V :t5%
f08C = 20 MHz; TA -10 to +70°C; VOO ... +5 V ±5%
"PD71011-10
"PD71011
Parameter
Symbol
Min
Max
Min
Max
Unit
Conditions
Clock Timing
EXFS input cycle time
EXFS pulse width, high
EXFS pulse width, low
tCYFS
50
50
ns
tPWF8H
20
20
ns
20
ns
tPWFSL
20
OSC cycle time
fosc
8
CKSYN pulse width
tpwCT
CKSYN setup time
tHF8CTK
20
8
20
MHz
2tCYF8
2tCYF8
ns
20
20
ns
ns
2.2 V measurement point
0.8 V measurement pOint
from EXFS
CKSYN hold time
t8CTF8
20
20
ClK cycle time
tC't'CK
125
100
ns
ClK pulse width, high
tpwCKH
80
41
ns
3.0 V, f08C == 10 MHz, f08C == 20 MHz
ns
3.0 V, f08C == 16 MHz
ns
= 20 MHz
= 16 MHz
1.5 ... 3.0 V, f08C = 10 MHz, f08C = 20 MHz
1.5'" 3.0 V, fosc = 16MHz
3.0 ... 1.5 V, f08C = 10 MHz, f08C = 20 MHz
3.0 ... 1.5 V, f08C = 16 MHz
50
ClK pulse width, low
tPWCKl
90
49
ns
60
ClK rise time
10
iLHCK
5
ClKfall time
10
tHLCK
ns
ns
8
5
ns
ns
7
1.5 V, f08C = 10 MHz, f08C
1.5 V, f08C
OSC to ClK i delay
tOCK
2
30
2
30
ns
ClKi
OSC to ClK J, delay
tOCK
-6
28
-6
28
ns
ClKJ,
PRClK cycle time
tCYPRK
250
4
200
ns
NEe
IIPD7 1011
AC Characteristics (cont)
"PD71011
Parameter
Max
"PD71011-10
Symbol
Min
Min
Max
PRClK pulse width, high
tpWPRKH
tCYCK
-20
tCYCK
-20
ns
PRClK pulse width, low
tpWPRKL
tCYCK
-20
tCYCK
-20
ns
PRClK i delay from ClK,J.
tOPRKH
22
22
ns
PRClK,J. delay from ClK,J.
tOPRKL
22
22
ns
Unit
Conditions
Clock Timing (cont)
Reset Timing
RESIN setup to ClK,J.
tSRICK
65
65
ns
RESIN hold from ClK,J.
tHCKRI
20
20
ns
RESET delay from ClK ,J.
tOCKRS
40
20
ns
Ready Timing (RDYSYN = 'H7
REN1, 2 setup to RDY1, 2
REN1, 2 hold from ClK,J.
RDY1, 2 setup to ClK ,J.
tSRERY
15
15
tHCKRE
0
0
ns
ns
35
ns
tSRYCK
35
RDY1, 2 hold from ClK ,J.
tHCKRY
0
0
ns
RDYSYN setup to ClK ,J.
tSRYSCK
50
50
ns
RDYSYN hold from
tHCKRYS
0
0
ns
READY output delay from ClK ,J.
tOCKROY
RDYSYN high
8
8
ns
READYi
8
8
ns
READY,J.
III
Ready Timing (RDYSYN = 'L 7
REN1, 2 setup to RDY1, 2
tSRERY
15
15
ns
REN1,2 hold from ClK,J.
tHCKRE
0
0
ns
RDY1, 2 setup to ClK
tSRYCK
35
35
ns
RDY1, 2 hold from ClK ,J.
tHCKRY
0
0
ns
RDY8YN setup to ClK ,J.
tSRYSCK
50
50
ns
tHCKRYS
0
0
RDYSYN hold from ClK ,J.
READY output delay from ClK,J.
tOCKROY
RDYSYN low
ns
8
ns
READYi
8
8
ns
READY,J.
8
Output Pin Timing
Rise time
tLH
20
20
ns
0.8
-+
2.0V
Fall time
tHL
12
12
ns
2.0
-+
0.8 V
5
NEe
IIPD71011
Timing Waveforms
AC Test Input (except RESIN)
AC Test Output (CLK)
2.6V =>{2.2V
2. 2V X =
Test Points
0.8 V
0.8 V
0.45 V
..;;.;.;;~------------RESIN: Input high level
Input low level
3.00 V
0.45 V
Measurement point
Measurement point
tPWCKH
2.6 V
0.8 V
83-004046A
AC Test Output (except CLK)
=>{
2.2V
0.8 V
Test Points
-
tpWCKL
tHLCK......
...
....
... tLHCK
83-004048A
2.2VX=
0.8 V.
~------------------------
83-004047A
Clock Output
FIX
~~____________________________________________________________________
EXFS/OSC
CKSYN
ClK
PRCLK ----------------------~
83-004049B
6
NEe
IIPD71011
Timing Waveforms (cant)
RESET Pin
ClK
RESIN
IDCKRS/_
RESET
IOCKRS-
{
83-0040508
READY Pin (RDYSYN
= 6H,
RENI.,:)
ISRERY
.-
IHCKRE --
ROY1,2
cm
ClK
IHCKRYS -RDYSYN
IDCKRDV_j
IDCKRDV_
L
READY
83-0040518
7
NEe
pPD71011
Timing Waveforms (cant)
READY Pin (RDYSYN
= 6L,
83-0040528
8
NEe
IIPD71011
Test Circuit for CLK to READY
(in EXFS Oscillation Mode)
Test Circuit for CLK High Dr Low Time
(in Crystal Oscillation Mode)
VDD ,....._ _ _ _......
FiX
.-----.---1
Xl
ClK
16 MHz [:::::J
.-_._---1
71011
X2
ClK
RENl
EXFS
READY
I
Cl
FiX
c2
71011
CKSYN
1
83ML-6145A
1-----1 RDY2
REN2
Test Circuit for CLK High Dr Low Time
(in EXFS Oscillation Mode)
CKSYN
83ML-6148A
Loading Circuits
Voo r - - - - - - - - ,
FiX
Load 1
Vl= 2.SV
ClK
Rl=525n
71011
0ad2
S=1
Vl=2.3V
Rl=47Sn
71011
EXFS
Cl=100pF
CKSYN
forCLK
'I
Cl=30 pF
'I
for Other Output
ExceptCLK
83ML-6149A
83ML-6146A
Test Circuit for CLK to READY
(in Cryst.IOscillation Mode)
Voo ,....._ _ _ _.......
RENl
ClK
. - - - - - - - -......--1 Xl
16 MHz I::]
. - - - - - -......--1 X2
READY
71011
RDY2
Cl
I I
C2
FiX
REN2
asc
CKSYN
83ML-6147A
9
pPD71011
10
NEe
NEe
pPD71037
Direct Memory Access
(DMA) Controller
NEe Electronics Inc.
Description
The p.PD71037 is a direct memory access (OMA) controller that provides high-speed data transfers between
peripheral devices and memory for microprocessor systems. It is faster and draws less power than its predecessors. The unit has four DMA channels, each with a
64K-byte address area and a transfer byte count function. The channels enable I/O-to-memory and memoryto-memory data transfer.
The p.PD71037 is a versatile DMA controller that can be
used for the following applications.
• Office automation equipment (personal computers,
small business computers, EWS, etc.)
• Communications
• Instrumentation
• Control
Features
o Processing speed of 10 MHz (twice that of the
p.PD8237A-5)
o Four independent DMA channels
o Self-initialization for each channel
o Memory-to-memory data transfer
o Block-level memory initialization
o High-speed data transfer
- 3.2 Mb/s, 10-MHz normal transfer
- 5.0 Mb/s, 10-MHz compression transfer
o DMA channel count directly expandable in
expansion mode
o END input for the end of transfer
o Software DMA request
o CMOS
o Low power consumption
50169
Ordering Information
Part Number
Clock (MHz)
Package
"PD71037CZ-10
10
40-pln plastic DIP (600 mlQ
GB-10
10
44-pln plastic QFP
LM-10
10
44-pln PLCC
Pin Configurations
4D-Pln PI••tlc DIP
lORD
IOWR
MWR
4
READY
HlDAK
ASTB
8
HlDRQ
Cs
ClK
RESET
DMAAK2
DMAAK3
DMARQ3
DMARQ2
DMARQ1
DMARQO
GND
A7
A6
AS
A4
ENDfTC
A3
A2
A1
Ao
VDD
ADo
AD1
AD2
AD3
AD4
DMAAKO
DMAAK1
ADs
AD6
AD7
* Undefined; same non-function as ~PD8237A
S3YL·5812A
NEe
pPD71037
Pin Identification
U-Pin PI••fic QFP
READY
33
A3
HLDAK
32
A2
ASTB
31
A1
AEN
30
AO
HLDRQ
29
NC
28
VDD
NC
CS
27
AOO
CLK
26
AD1
RESET
25
24
· AD 2
AD3
23
AD4
DMAAK2
DMAAK3
~ ~ ~ ~ ~ ~ ~ ~ ~
~~~~~
c( c( c( c(
~
~
~
~
o 0 0 0
()
Z
'"
<0
N
N
N
I/O
Function
Aq-A3
3-state I/O
Four low-order bits of address bus
~-A7
3-state out
Middle four bits of the output state
address bus
ADrrAD7
3-state I/O
Eight high-order bits of the address and
funct,lons as an 8-blt data bus
AEN
Out
Permits output from an external latch
connectec;t to t~e "PD71037
ASTB
Out
Makes an external latch to the high-order
address
ClK
In
Clock Input for Internal operations and
data transfer speeds
es
In
Selects the "PD71037 as an I/O device
and enables read/Wrlte operation
Out
Permits peripheral device to perform
DMA transfer
T"'"
0
DMAAKODMAAK3
0
~0
DMARQO- In
DMARQ3
Requests the "PD71037 to perform DMA
transfer
tNDtfC
I/O
Input that forces the "PD71037 to
terminate DMA transfer; output that posts
the end of DMA transfer
HlDAK
In
Permits the "PD71037 to hold the bus
HlDRQ
Out
Requests the host CPU to hold the bus
fORD
3-state I/O
Input that enables the host CPU to read
the "PD71037 status; output that enables
the "PD71037 to read data from a
peripheral device during DMA transfer
IOWA
3-state I/O
Input that enables the host CPU to write
data to the "PD71037; outputlhat
enables the "PD71037 to write data to a
peripheral device during DMA transfer
000::':: ::.::
c( c( c(.~
Lt)
Symbol
83vB-6516A
U-Pln PLCC
NC
39
NC
38
A2
HLDAK
37
A1
ASTB
36
AO
AEN
35
VDD
HLDRQ
34
ADO
A3
Cs
33
AD1
MAD
3-state out
Memory read during DMA transfer
CLK
32
AD2
~
3-state out
Memory write during DMA transfer
RESET
31
AD3
READY
In
DMAAK2
30
AD4
Requests extension of a read/Wrlte cycle
during DMA transfer
29
NC
RESET
In
Initializes the "PD71037
NC
~ ~ ~ N ~ ~ ~ ~ ~ ~ co
N
~8~o8or--
DI
"-r--
~
HLDAK
f~
Ao-A7
STB
~
-
UBE, Ao-A19
DO
Aa- A 15
DE
L
~
i
)
-
HLDRQ
Ao-A7
ADo -AD 7
h
IlPD71 037
ASTB
B
Ao-A7
lJ L~A
> Address Bus
j>
HLDRQ
ASTB I - HLDAK
DO
~7
..
Data Bus
(High-order Byte)
T I - - f--
A OE ~
~PD710a6
)
y
Data Bus
(Low-order Byte)
~PD710a2
-
AEN ' - - -
I
DO ' - - ' - -
DI
y
STB
j
OE
t
83YL·5815B
V20 and V30 are registered trademarks of NEC Corporation
6
NEe
pPD71037
"PD71037 Block Diagram
Bus Control Unit
<
<
I Add~~ I "
<
II
Buffer
Data Bus
Buffer
I
I
CS
Address
Registers
ClK
I
RESET
READY
Bus
Control logic
ASTB
AEN
MRD,MWR
IORD,IOWR
"
I
,
DMAROODMARQ3
DMAAKODMAAK3
4
Count
Registers
~
Priority
Control logic
I
HlDRQ
I
Address Set
(16 x 4)
I
I11m'... Coo,,"' I
logic
ENDITC
l
I
Count Set
(16x 4)
Effective Count
(16 x 4)
Control Registers
I
I
Device Control (8)
Status Read (8)
..
Internal Data Bus (8)
2,
DMA Control Unit
11
Effective Address
(16 x 4)
D
D
A
K
2
4,
HlDAK
Address
IncremenV
Decrement
(16)
Internal Address Bus (16)
>
Mode Control (4 x 6)
Temporary Data (8)
Request Control (4)
I
Mask.Control (4)
J
D
Count
Decrement
(16)
83YL·6264B
INTERNAL BLOCK FUNCTIONS
The #,PD71037 has the following functional units as
shown in the block diagram.
•
•
•
•
•
•
•
Bus control unit
DMA control unit
Address registers
Address incrementer/decrementer
Count registers
Count decrementer
Control registers
Bus Control Unit
The bus control unit consists of the address and data
buffers and bus control logic. The bus control unit
generates and receives signals that control addresses
and data on the Internal address and data buses.
DMA Control Unit
The DMA control unit contains the priority and timing
control logic. The priority control logic determines the
priority level of DMA requests and arbitrates the use of
the bus in accordance with this priority level. The DMA
control unit also provides internal timing and controls
DMA operations.
Address Registers
Each of the four DMA channels has one address set
register and one effective address register. Each register
stores a DMA 16-bit address. The effective address
register is updated for each single-byte DMA transfer
and constantly holds the address to be transferred next.
The contents of the address set register remain unchanged until the host CPU writes a new value to it. At
self-initialization, the initial DMA address for the next
DMA service is transferred from the address set register
to the effective address register.
Address Incrementer/Decrementer
The address incrementer/decrementer updates the contents of the current address register whenever a DMA
transfer completes.
7
m
NEe
pPD71037
Count Registers
Each of the four DMA channels has one 16-bit count set
register and one 16-bit effective count register that store
a DMA transfer byte count. The count set register holds
a value written by the CPU. At self-initialization the value
is transferrred to the effective address register where it
is set as the number of DMA transfers in the next DMA
service.
A channel's effective count register is decremented by 1
for each single-byte transfer and constantly holds the
remaining number of DMA transfers. If a ~orrow occurs
when this register is decremented, the terminal count is
set to mark the end of the specified number of DMA
transfers.
Figure 1.
DIM Operation Flow
No
Inactive Cycle
No
Count Decrementer
The count decrementer decrements the contents of the
effective count register by 1 when each DMA transfer
takes place.
DMACycle
No
Control Registers
The #,PD71037 contains six registers that control the bus
mode, pin active levels (DMARQ and DMAAK), and the
DMA transfer mode.
Inactive Cycle
83YL-5816A
DMA OPERATION
Inactive Cycle
The #,PD71037 operates in an inactive cycle and a DMA
cycle. Figure 1 illustrates basic DMA operation flow.
During the inactive cycle, the host CPU has authority
and the #,PD71037 is in one of the following states.
• The #,PD71037 has not yet received an effective DMA
service request from a peripheral device.
• The #,PD71037 has received an effective DMA service
request, but has not yet received bus authority from
the host CPU.
• The #,PD71037 performs the following operations during the inactive cycle.
- Detecting a DMA service request
- Requesting bus authority
- Selecting a DMA channel
- Programming
In the inactive cycle, there are no active DMA cycles but
there may be one or more active DMA requests. However,
the CPU has not yet released the bus.
Detecting a DMA Service Request. The #,PD71037 wiIJ
sample the four DMARQ input pins for each clock Signal.
8
NEe
Requesting Bus Authority. When an effective (unmasked) DMA request is received, a bus hold request
signal (HLDRQ) is output to the host CPU. The "PD71037
continues to sample DMA requests until it obtains the
bus by HLDAK input.
Selecting a DMA Channel. After the CPU returns an
HLDAK signal and the "PD71037 obtains the bus, the
"PD71037 stops DMA sampling and selects the DMA
channel with the highest priority from the valid DMA
request signals.
pPD71037
Figure 2. Generalion of Terminal Count (TC)
No
Programming. Before DMA transfer, the transfer addresses, the number of DMA transfers, the DMA transfer
mode, and the active levels of the DMARQ and DMAAK
pins must be determined.
While the host CPU holds bus authority, "PD71037
programming can be done by inputting a low signal to
the CS pin. The four low-order address bits (Ao-As)
specify a register for a read/write operation. Inputting an
10RD/IOWR signal performs the operation on the specified register.
DMACycle
In a DMA cycle, the "PD71037 controls the bus and
performs DMA transfer operations based on· programmed information.
Terminal Count. External input of an END signal or
internal generation of a terminal count terminates DMA
transfer. The terminal count is generated when a borrow
occurs as a result of decrementing the effective count
register, which counts the number of DMA transfers in
bytes. When this occurs, the "PD71037 outputs the low
level pulse TC.
Figure 2 shows that the effective count register is tested
after each DMA operation. A borrow is detected after
each DMA transfer is completed. As a result, the actual
number of DMA transfers is one greater than the value
set in the effective count register.
If self-initialization is not set when DMA service ends, the
mask control register bits applicable to the channel
where service is ended are set, and the DMARQ input of
that channel is masked.
83YL·6265A
DMA Transfer Type
The type of transfer the "PD71037 performs depends on
the following conditions.
• Memory-to-memory transfer enable
• Direction of I/O-to-memory transfer for each channel
• Transfer mode of each channel
Memory-to-Memory Transfer Enable. The "PD71037
performs each DMA transfer (1 byte of data) between an
I/O device and memory in a one-bus cycle and between ~
memories in a two-bus cycle.
_
Memory-to-memory transfer can occur only when bit 0 of
the device control register is set to 1. The DMA channels
used in memory-to-memory transfers are fixed, with
channel 0 as the source channel and channel 1 as the
destination channel. Channels 2 and 3 cannot be used in
memory-to-memory transfers. The contents of the count
registers of each channel should be the same when
performing this type of DMA transfer.
The "PD71037 performs the following operations until a
channel 0 terminal count or until END input is present.
Only the block mode is valid for this type of transfer.
(1) The memory data pointed to by the effective address
register of channel 0 is read into the temporary data
register of the "PD71037 and the effective address
register and effective count register of channel 0 are
updated.
(2) The temporary register data is written to the rnemory
location shown by the effective address register of
channel 1; the effective address register and effective count register are updated.
9
NEe
pPD71031
During memory-to-memory transfers, the address of the
transfer source can be fixed using the device control
register. In this manner, a range of memory can be
padded with the same value (0 or 1) since the contents of
the source address never change. During memory-tomemory transfer, the DMAAK signal and channel a's
terminal count (TC) are not output.
Note: If DMARQ1 (channel '1) becomes active, the
#,PD71037 will perform memory-to-I/O transfer even
though memory-to-memory transfer is selected. Since
this may cause erroneous memory-to-memory transfers, mask out channel 1 (DMARQ1) by setting bit 1 of
the mask register to 1 before starting memoryto-memory transfers.
Direction of I/O-to-Memory Transfers. All DMA transfers use memory as a reference point. Therefore, a DMA
read reads a memory location and writes to an 1/0 port.
A DMA write reads an I/O port and writes the data to a
memory location. In memory-to-I/O transfer, use the
mode control register to set one of the transfer directions in table 1 for each channel and activate the appropriate control signals.
mode of DMA transfer for each channel. Table 2 shows
the various transfer modes and termination conditions.
Table 2. Transfer Termination
Transfer Mode
End of Transfer Condition
Single
After 1 byteof 0CD 0"I~
~ III:
== ICI)
0
Read strobe input
Receiver ready output
TxRDY
Transmitter ready output
SYNC/BRK
Synchronization/Break input/output
CTS
Clear to send input
TxEMP
Transmitter empty output
NC
Not connected
RxROY
RESET [Reset]
;:
o~
RD
RxRDY
0 7 -00 [Data Bus]
TxROY
pPD71051 15
14
CD ,...
Chip select input
Control or data input
DrDo are an 8-bit, 3-state, bidirectional data bus. The
bus transfers data by connecting to the CPU data bus.
SYNC/BRK
03
on
CS
C/D
Pin Functions
en
...
Voo
02
>C
I83-004212A
2
Function
TxDATA
A high level to the RESET input resets the pPD71051
and puts it in an idle state. It performs no operations in
the idle state. The pPD71051 enters standby mode
when this signal falls from a high level toa low level.
Standby mode is released when the CPU writes a mode
byte to thepPD71 051. The reset pulse width must be at
least 6 tCYK cycles and the clock must be enabled.
NEe
pPD71051
ClK [Clock]
6'S'R [Data Set Ready]
This clock input produces internal timing for the
pPD71 051. The clock freq uency shou Id be at least 30
times the transmitter or receiver clock input frequency
(TxCLK, RxCLK) in sync or async mode with the X1
clock. This assures stable operation. The clock
frequency must be more than 4.5 times the TxCLK or
RxCLK in async mode using x16 or x64 clock mode.
DSR is a general-purpose input pin that can be used for
modem control. The status of this pin can be determined
by reading bit 7 of the status byte.
CS [Chip Select]
The CS input selects the pPD71051. The pPD71051 is
selected by setting CS = O. When CS = 1, thepPD71051
is not selected, the data bus (DrDo) is in the high
impedance state, and the RD and WR signals are
ignored.
RD [Read Strobe]
The RD input is low when reading data or status
information from the pPD71051.
WR [Write Strobe]
The WR input is low when writing data or a control byte
to the pPD71051.
DTR [Data Terminal Ready]
DTR is a general-purpose output pin that can be used
for modem control. The state of this pin can be
controlled by writing bit 1 of the command byte. If bit 1
= 0, then DTR = 1. If bit 1 = 1, then DTR = O.
RTS [Request to Send]
RTS is a general-purpose output pin that can be used
for modem control. The status of this pin can be
controlled by writing bit 5 of the command byte. If bit 5
= 1, then RTS = O. If bit 5 = 0, then RTS = 1.
CTS [Clear to Send]
The CTS input controls data transmission. The
pPD71051 is able to transmit serial data when CTS = 0
and the command byte sets TxEN = 1.lf CTS is set
equal to 1 during transmission, the sending operation
stops after sending all currently written data and the
TxDATA pin goes high.
C/O [Control or Data]
The C/O input determines the data type when accessing
the pPD71051. When C/O = 1, the data is a control
byte (table 1) or status. When C/O = 0, the data is
character data. This pin is normally connected to the
least significant bit (Ao) of the CPU address bus.
Table 1.
cs
Control Signals and Operations
iiD WR ciii
tJ PD71051
CPU Operation
Receive data buffer
<7
Read receive data
Data bus
Status register
~
Read status
Data bus
Data bus
<>
Write transmit data
Transmit data buffer
Data bus
0
Write control byte
Control byte regIster
Data bus
High impedance
Data bus:
High impedance
TxDATA [Transmit Data]
The pPD71051 sends serial data over the TxDATA
output.
TxRDY [Transmitter Ready]
The TxRDY output tells the CPU that the transmit data
buffer in the pPD71051 is empty; that is, that new
transmit data can be written. This signal is masked by
the TxEN bit of the command byte and by the CTS
input. It can be used as an interrupt signal to request
data from the CPU.
The status of TxRDY can be determined by reading bit
status byte. This allows the pPD71051 to be
polled. Note that TxRDY of the status byte is not
masked by CTS or TxEN.
o of the
TxRDY is cleared to 0 by the falling edge of WR when
the CPU writes transmit data to the pPD71 051. DCita in
the transmit data buffer that has not been sent is
destroyed if transmit data is written while TxRDY = O.
None
None
3
pPD71051
TxEMP [Transmitter Empty]
The pPD71051 reduces CPU overhead by using a
double buffer; the transmit data buffer (second buffer)
and the transmit buffer (first buffer) in the transmitter.
When the CPU writes transmit data to the transmit data
buffer (second buffer), the pPD71051 sends data by
transferring the contents of the second buffer to the
first buffer, after transmitting the contents of the first
buffer.
This empties the second buffer and TxRDY is set to 1.
The TxEMP output becomes 1 when the contents of the
first buffer are sent and the second buffer is empty.
Thus, TxEMP = 1 shows that both buffers are empty. In
half-duplex operation, you can determine when to
change from sending to receiving by testing TxEMP= 1.
When TxEMP = 1 occurs in async mode, the TxDATA
pin goes high. When the CPU writes transmit data,
TxEMP is set to 0 and data transmission resumes.
When TxEMP = 1 occurs in sync mode, thepPD71051
loads SYNC characters from the SYNC character
register and sends them through the TxDATA pin.
TxEMP is set to 0 and resumes sending data after
sending (one or two) SYNC characters and the CPU
writes new transmit data to the pPD71051.
TxCLK [Transmitter Clock]
The TxCLK input is the reference clock input that
determines the transmission rate. Data is transmitted
at the same rate as TxCLK in sync mode. In async
mode, set TxCLK to 1, 16, or 64 times the transmission
rate. Serial data from TxDATA is sent at the falling edge
of TxCLK.
For example, a rate of 19200 baud in sync mode means
that TxCLK is 19.2 kHz. A rate of 2400 baud in async
mode can represent a TxCLK of:
x1 clock = 2.4 kHz
x16 clock = 38.4 kHz
x64 clock = 153.6 kHz
RxDATA [Receive Data]
ThepPD71051 receives serial data through the RxDATA
input.
RxRDY [Receiver Ready]
The RxRDY output becomes 1 when the pPD71051
receives one character of data and transfers that data
to the receive data buffer; that is, when the receive data
can be read. This signal can be used as an interrupt
signal for a data read request to the CPU. You can
4
NEe
determine the status of RxRDY by reading bit 1 of the
status byte and use the pPD71 051 in a polling application. RxRDY becomes 0 when the CPU reads the
receive data.
Unless the CPU reads the receive data (after RxRDY =
1 is set) before the next Single character is received and
transferred to the receive buffer, an overrun error
occurs, and the aVE status bit is set. The unread data
in the receive data buffer is overwritten by newly
transferred data and lost.
RxRDY is set to 0 in the receive disable state. This state
is set by changing the RxEN bit to 0 through the
command byte. After RxEN issetto 1 (making receiving
possible), RxRDY becomes 1 whenever new characters
are received and transferred to the receive data buffer.
SYNC/BRK [Synchronization/Break]
The SYNC pin detects synchronization characters in
sync mode. The SYNC mode byte selects internal or
external SYNC detection. The SYNC pin becomes an
output when internal synchronization is set, and an
input when externa.1 synchronization is set.
The SYNC output goes high when the pPD71051
detects a SYNC character in internal synchronization.
When two SYNC characters are used, SYNC goes·high
when the last bit of the two consecutive SYNC
characters is detected. You can read the status of the
SYNC signal in bit 6 of the status byte. Both the SYNC
pin and status are set to 0 by a read status operation.
In external synchronization, in order for the external
circuit to detect synchronization, a high level of at least
one period of RxCLK must be input to the SYNC pin.
When the pPD71 051 detects the high level, it begins to
receive data, starting at the rising edge of the next
RxCLK. The high level input may be removed when
synchronization is released.
The BRK output is used only in async mode and shows
the detection of a break state. BRK goes high when a
low level signal is input to the RxDATA pin for two
character bit lengths (including the start, stop, and
parity bits). As with SYNC, you can read the status of
BRK in bit 6 of the status byte. BRK is not cleared by the
read operation.
The set BRK signal is cleared when the RxDAT A pin
returns to high level, or when the pPD71051 is reset by
hardware or software. The SYNC/BRK pin goes low on
reset, regardless of previous mode. Figure 1 shows the
break state and BRK signal.
NEe
pPD71051
Block Diagram
RxCLK [Receiver Clock]
RxCLK is a reference clock input that controls the
receive data rate. In sync mode, the receiving rate is the
same as RxCLK.ln async mode, RxCLK can be 1, 16, or
64 times the receive rate. Serial data from RxDATA is
input by the rising edge of RxCLK.
07- Do
TxOATA
TxROY
TxEMP
TxClK
Voo [Power]
+5 V power supply.
GND [Ground]
RESET
ClK
C/O
Ground.
Figure 1.
AD
WR
Break Status and Break Signal
IIr
B-blt Character, No Parity
Charac~er Bits
r
RxOATA - ,
)
'Do
07
~~
Stop Bit [2J
Charac!er Bits
Do
r
0;
i----First Data
., •
Second Oata---i
Block
Block [1 J
BRK __________________________
~~
lIT
6-blt Character with Parity
RCharac~er
~Charact!er ,II
m
Parity Bit
Stop Bit [2J
Start Bit
Start Bit
Bits
Bits
i i i
RxOATA - - ,
Do
05
Parity Bit
Stop Bit
Start Bit
Do
I
05
i--Flrst Oata---!-- Second Oata-..l
Block
Block [1 J
BRK --------------------~
Note:
[1J When RxOATA goes high In the stop bit position ofthe second data block,
the BRK signal level may [but does not alwaysJ become high for a
maximum of one bit time.
[2J Only one bit of the stop bit is checked.
83-000783A
IlPD71051 Functions
The pPD71051 is a CMOS serial control (USART) unit
that provides serial communications in microcomputer
systems. The CPU handles thepPD71 051 as an ordinary
1/0 device.
ThepPD71 051 can operate in synchronous or asynchronous systems. In sync mode, the character bit length,
number of sync characters, and sync detection mode
must be designated. In async mode, the communication
rate, character bit length, stop bit length, etc., must be
designated. The parity bit may be designated in either
mode.
CTS
RTS
OSR
OTR
83-000782A
Stop Bit
StartBit
)
cs
RxOATA
RxROY
SYNC/BRK
RxClK
The CPU can read the current status of the pPD71 051
and can process data after checking the status, after
checking fortransfererrors, andpPD71051 data buffer
status.
ThepPD71051 can be reset under hardware or software
control to a standby mode that consumes less power
and removes the device from system operation. In this
mode, the pPD71 051 's previous operating mode is
released and it waits for a mode byte to set the mode.
The pPD71051 leaves standby mode and shifts to a
designated operating mode when the CPU writes a
mode byte to it.
Status Register
The status register allows the CPU to read the status of
the pPD71051 except in standby mode. This register
indicates status and allows the CPU to manage data
reading, writing, and error handling during operations.
Receive Data Buffer
When the receiver has converted the serial data input
from the RxDATA pin into parallel,data, the converted
data is stored in the receive data buffer. The CPU can
then read it. Data for one character entering the receive
buffer is transferred to the receive data buffer and
RxRDY becomes 1, requesting that the CPU read the
data.
ThepPD71051 converts parallel data received from the
CPU into serial transmitted data (from the TxDATA
pin), and converts serial input data (from the RxDATA
pin) into parallel data so that the CPU can read it
(receiving operation).
5
Ell
NEe
pPD71051
Transmit Data Buffer
The transmit data buffer holds the parallel data from
the CPU that the transmitter will convert to serial data
and output from the TxDATA pin. When the CPU writes
transmit data to the pPD71051, the pPD71051 stores
data in the transmit data buffer. The transmit data
buffer transfers the data to the transmitter, which
sends the data from the TxDATApin.
Absolute Maximum Ratings
TA = +25°C
Power supply voltage, Voo
-0.5 to +7.0 V
Input voltage, VI
-0.5 to Voo + 0.3 V
Output voltage, Vo
-0.5 to Voo + .0.3 V
Operating temperature, TOPT
Storage temperature, TSTG
1.0 W
Power dissipation, PDMAX
Control Register
This register stores the mode and the command bytes.
Control Logic
The control logic sends control signals to the internal
blocks and controls the operation of the pPD71051
based on internal and external signals.
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Capacitance
TA = +25°C, Voo = 0 v
Limits
Synchronous Character Register
This register stores one or two SYNC characters used
in sync mode. During transmission, the SYNC
characters stored in this register are output from the
TxDATA pin when the CPU does not send a new
character and TxEMP status is set. During receiving,
synchronization is established when the characters
received and the SYNC characters stored in this
regist~r are the same.
Transmitter
The contents of the transmit data buffer are transferred
to the transmitter, converted from parallel to serial, and
output from the TxDATA pin. The transmitter adds
start, stop, and parity bits.
Receiver
The receiver converts serial data input from the RxDATA
pin into parallel data and transfers the· parallel data to
the receive data buffer, allowing the CPU to read it.
The receiver detects SYNC characters and checks
parity bits in sync mode. It detects the start and stop
bits, and checks parity in the async mode.
In async mode, receiving does not begin (thestart bit is
not detected) until one effective stop bit (high level) is
input to the RxDATA pin and Receive Enable (RxEN =;=
1) is set after setting up the mode.
Modem Control
This block controls the CTS, RTS, DSR, and DTR
modem interface pins. The RTS, DSR, and DTR pins
can also be used as general-purpose I/O pins.
6
Test
Symbol Min Max Unit
Parameter
Input capacitance
CI
10
pF
1/0 capacitance
CIO
20
pF
Conditions
fc = 1MHz
Unmeasured pins
returned to 0 V
DC Characteristics
TA=-AO°Cto+85°C,Voo=+5V±10%
Limits
Typ
Parameter
Symbol
Min
Max
Unit
Input voltage
high
VIH
2.2
Voo+0.3
V
Input voltage
low
VIL
-0.5
0.8
V
Output voltage VOH
high
0.7 x Voo
Test Conditions
V
IOH = -AOO I1A
IOL = 2.5 rnA
Output voltage VOL
low
0.4
V
Input leakage
current high
IUH
10
I1A
VI = Voo
Input leakage
current low
IUL
-10
I1A
VI =OV
Output leakage ILOH
current high
10
I1A
Vo = Voo
Output leakage ILOL
current low
-10
I1A
Vo=OV
Supply current
ti PD71051
1001
1002
I1PD71051-10
50
1001
la02
2
10
rnA
Normal mode
100
I1A
Stand-by mode
10
rnA
Normal mode
50
I1A
Stand-by mode
NEe
pPD71051
AC Characteristics
TA = -40°C to +85°C, VDD = 5 V ±10%
8 MHz Limits
Parameter
Symbol
Min
Max
10 MHz Limits
Min
Max
Unit
Test Conditions
Read Cycle
Address setup to RD ~
Address hold from RD
t
tSAR
0
0
ns
CS,C/D
tHRA
0
0
ns
CS,C/D
150
RD low level width
tRRL
Data delay from RD ~
tORO
t
tFRO
10
tSPR
20
20
Data float from RD
Port (DSR, CTS) set-up to RD ~
95
120
80
10
ns
85
ns
65
ns
CL = 150 pF
tCYK
Write Cycle
Address setup to WR ~
tSAW
0
0
ns
CS, C/O
tHWA
0
0
ns
CS,C/D
WR low level width
twwL
150
95
ns
t
tsow
80
80
ns
Address hold from WR
Data setup to WR
Data hold from WR
t
t
Port (DTR, RTS), delay from WR
Write recovery time
tHWO
t
tCYK
8
towp
tRV
tCYK
6
6
tCYK
Mode initialize
8
8
tCYK
Async mode
16
16
tCYK
Sync mode
Serial Transfer Timing
ClK cycle time
tCYK
125
ClK high level width
tKKH
50
35
ClK low level width
tKKL
35
25
ClK rise time
tKR
5
20
5
20
ClK fall time
tKF
5
20
5
20
ns
TxDATA delay from TxClK
tOTKTD
0.5
/lS
Transmitter input clock pulse
width low level
tTKTKL
Transmitter input clock pulse
width high level
Transmitter input clock
frequency
Receiver input clock pulse
width low level
Receiver input clock pulse
width high level
DC
100
0.5
DC
ns
ns
ns
ns
12
12
tCYK
1
1
tCYK
16x, 64xBR
tTKTKH
15
15
tCYK
1xBR
tCYK
16x, 64xBR
fTK
(Note 2)
DC
240
DC
300
kHZ
1xBR
DC
1536
DC
1920
kHz
16xBR
DC
1536
DC
1920
kHz
64xBR
tCYK
1xBR
3
3
1xBR (Note 1)
tRKRKL
12
12
tCYK
16x, 64xBR
tRKRKH
15
15
tCYK
1xBR
3
3
tCYK
16x, 64xBR
7
NEe
pPD71051
AC Characteristics (cont)
8 MHz limits
Parameter
Symbol
Min
fRK
(Note 2)
10 MHz Limits
Max
Unit
Test Conditions
DC
300
kHz
1xBR
DC
1920
kHz
16xBR
DC
1920
kHz
64xBR
Max
Min
DC
240
DC
1536
DC
1536
Serial Transfer Timing (cont)
Receiver input clock frequency
RxDATA set-up to Sampling pulse
tSROSP
fJS
RxDATA hold from sampling
pulse
tHSPRO
fJS
TxEMP delay time (TxDATA)
tOTXEP
20
20
tCYK
TxRDY delay time (TxRDYt)
tOTxR
8
8
TxRDY delay time (TxRDY l)
tOWTXR
200
100
tCYK
ns
RxRDY delay time (RxRDYt)
tORXR
26
26
RxRDY delay time (RxRDY l)
tORRXR
200
100
tCYK
ns
SYNC output delay time
(for internal sync)
tORKSY
26
26
tCYK
SYNC input set-up time
(for external sync)
tSSYRK
RESET pulse width
18
18
tCYK
6
6
tCYK
Notes:
(1) BR = Baud rate
(2) 1xBR: fTK or fRK::; 1/30tCLK, 16x, 64xBR: fTK orfRK::; 1/4.5tCLK
(3) System elK is needed during reset operation
(4) Status update can have a maximum delay of 28 tCYK from the
event effecting the status.
Timing Waveforms
Write Data Cycle
Read Data Cycle
k==
X
c/o - - -.....
cs----M
_ _ _I----,1II+-IWWL--!
WR
~
r+r-I
~
I
i
J(I~
!--IDWTXR
~
x:
----!
\\
I
07-
0
0
OSR,CTS
0=
I
I
VJ'~
rftft'
-H1C
I
~--------+l-------------I
~L
I---IRRL--!
__+-____;....r:!_DR""D
!-IDWP-j
I
TxRDY
r--IS~R---!
_1_ _
nc=
\n
cs---........
I....----ll
-' IHWD
_ _ _ _--.. 1I SDW~
07-00
ic:
---JX
c/o _ _
I
RxROY _ _ _ _ _oJ
~
______
~
83-01913A
83-000767A
8
NEe
pPD71051
Timing Waveforms (coni)
Transmitter Clock and TxDA TA
TxClK [1 x BR]
TxDATA
---..1-'·~'T'm"~1--'_---..1,.---~tDTKTD1
ltDTKTD1
I
I
------..,X
X. . .- - - - - - - -
1+----------
16~
Cycle
-----------+1
TxClK [16 x BR]
TxDATA
:':
83-0007698
Receiver Clock and RxDATA Timing
RxClK [1 x BR]
Internal
Sampling
Pulse
_
_1J:t"~
~'
__
RxDATA
tSRDSP'----1-.1.1
~~-------S-ta-rt-B-it------~J(~-------1s-t-D-at-a-B-It--______--J)(~______
r-I r~~
__
SRxClK
RxClK [16 x BR]
tnternal
Sampling
Pulse
RxDATA
11\____
tH-s-p-RD-l-----------J
....
SRxClK
~~
,',
16 RxClK
"~~
tRKRKL tRKRKH
'1' .\ LJ
H
~~'m,..~~/'LYL
I~'
~,'-----
~ll·~ __________ts_R_DS~p~----------~~t~H-SP-R-Dl--~
~ :::::::::(~::::::::::~~':.=::x-----"
Start Bit
"
....
1st Data Bit
83-0007688
AC Test Input
4V
2.
0.4SV
Write Recovery Time
2,2 V
=::X_
_
O.S V
-x==
2.2 V
Test Points
-------=
0.8 V
Main Clock
83-OOO766A
ClK
83-000770A
9
NEe
pPD71051
Fi9We 3.
Connecting the pPD71051 to the System
pPD71051 Opera,t("gProcedure
The CPU uses the pPD71051 as an I/O device by
allocating two I/O addresses, set by the value of C/O.
One I/O address is allocated when the level of C/O is
low and becomes a port to the transmit and receive
data register. The other I/O address is allocated when
C/O is high and becomes aport to the mode, command,
and status registers. Generally, the least significant bit
(Ao) of the CPU address bus is connected to C/O to get
a continuous I/O address. This is shown in figure 2.
Pins TxRDY and RxRDY are connected to the CPU or,
when interrupts are used, to the interrupt pin of the
interrupt controller.
Operating the pPD71051
Start with a hardware reset (set the RESET pin nigh)
after powering on the pPD71051. This puts the
pPD71051 into standby mode and it waits for a mode
byte. In async mode, the pPD71051 is ready for a
command byte after the mode byte; the mode byte sets
the communication protocol to the async mode. In
sync mode, the pPD71 051 waits for one or two SYNC
characters to be sent after the mode byte; set C/O = 1.
A command byte may be sent after the SYNC characters
are written. Figure 3 shows this operation sequence.
I n both modes, it is possible to write transmit data, read
receive data, read status, and write more command
bytes after the first command byte is written. The
pPD71051 performs a reset, enters standby mode, and
returns to a state where it waits for a mode byte when
the command byte performs a software reset.
Figure 2.
System Connection
Note:
[lJ This is done with C/O
CPU
= 0, Others are operated with C/O = 1.
83-0007858
MEM/IO
JlPD71051
RD~------------~--~
WR~----------------~
83-000784A
10
NEe
Mode Register .
When the JlPD71051 IS In standby mode, writing a
mode byte to it will release standby mode. Figure 4
shows the mode byte format for designating async
mode. Figure 5 shows the mode byte format for
designating sync mode. Bits 0 and 1 must be 00 to
designate sync mode. Async mode is designated by all
other combinations of bits 0 and 1.
pPD71051
Figure 4.
Mode Byte for Setting Asynchronous Mode
C/D=1
7654321
PO I L1
IST1ISTOI P1
L,J
LO I B1 I BO
L,J
L~
J
~B1
BO
0
1
x 1 Clock
1
0
x 16 Clock
1
1
x 64 Clock
L1
LO
Character Length
0
0
5·bit
0
1
6-bit
1
0
7-bit
1
1
8-bit
P1
PO
Parity Generate/Check
x
0
No Parity
0
1
Odd Parity
1
1
Even Parity
TheP1, PO and L 1, LO bits are common to both modes.
Bits P1 and PO (parity) control the generation and
checking (sending and receiving) functions. These
parity bit functions do not operate when PO = O. When
P1, PO = 01, the JlPD71051 generates and checks odd
parity. When P1, PO = 11 , it generates and checks even
parity.
Bits L 1 and LO set the number of bits per character (n).
Additional bits such as parity bits are not included in
this number. Given n bits, the JlPD71051 receives the
lower n bits of the 8-bit data written by the CPU. The
upper bits (8 -n) of data that the CPU reads from the
JlPD71051 are set to zero.
ST1 STO
The ST1, STO and B1, BO bits are used in async mode.
The ST1 and STO :bits determine the number of stop
bits added by the JlPD71 051 during transmission.
The B1 and BO bits determine the relationship between
the baud rates for sending and receiving, and the
clocks TxCLK and RxCLK. B1 and BO select a multiplication rate of 1, 16, or 64 for the frequency of the
sending and receiving clock relative to the baud rate.
Multiplication by 1 is not normally used in async mode.
Note that the data and clock must be synchronized on
the sending and receiving sides when multiplication by
1 is used.
The SSC and EXSYNC bits are used in sync mode. The
SSC bit determines the number of SYNC characters.
SSC = 1 designates one SYNC character. SSC = 0
designates two SYNC characters. The number of
SYNC characters determined by the SSC bit are
written to the JlPD71 051 immediately after writing the
mode byte.
The EXSYNC bit·determines whether sync detection
during receiving operations is internal or external.
EXSYNC = 1 selects external sync detection and
EXSYNC = 0 selects internal sync detection.
Baud Rate
Transmit Stop Bits
Use Illegal
0
0
0
1
1-bit
1
0
1-1/2 bit
1
1
2-bit
x: don't care
Figure 5.
83-000786A
Mode byte for Setting Synchronous Mode
C/D=1
5
4
L
PO
LSscLEXSYNC P1
L..J
3
2
1
I Ld LO I 0 10
T
L1
LO
0
0
Character Length
5-bit
0
1
6-bit
1
0
7-bit
1
1
8-bit
P1
PO Parity Generate/Check
x
0
No Parity
0
1
Odd Parity
1
1
Even Parity
EXSYNCI
Sync Detect
0
Internally IOutput]
1
Externally [Input]
SSC
Sync Characters
0
2 [BSC]
1
1
x: don't care
83-000787A
m
NEe
pPD71051
Command Register
Commands are issued to the JlPD71051 by the CPU by
command bytes that control the sending and receiving
operations of the JlPD71051. A command byte is sent
after the mode byte (in sync mode, a command byte
may only be sent after writing SYNC characters) and
the CPU must set C/O = 1. Figure 6 shows the
command byte format.
Bit EH is set to 1 when entering hunt phase to
synchronize in sync mode. Bit RxEN should also be set
to 1 at that time. Data reception begins when SYNC
characters are detected and synchronization is
achieved, thus releasing hunt phase.
The TxEMP and RxRDY bits have the same meaning as
the pins of the same name. The SYNC/BRK bit generally
has the same meaning as the SYNC/BRK pin. In
external synchronization mode, the status of this bit
does not always coincide with the pin. In this case, the
SYNC pin becomes an input and the status bit goes to 1
when a rising edge is detected at the input. The status
bit remains at 1 until it is read, even when the input level
at the SYNC pin goes low. The status bit becomes 1
when a SYNC character is input with the RxDATA
input, even when the pin is at a low level.
The DSR bit shows'the status of the DSR input pin. The
status bit is 1 when the DSR pin is low.
When bit SRES is set to 1, a software reset is executed,
and the JlPD71051 goes into standby mode and waits
for a mode byte.
The FE bit (framing error) becomes 1 when less than
one stop bit is detected at the end of each data block
during asynchronous receiving. Figure 8 shows how a
framing error can happen.
Bit RTS controls the RTS output pin. RTS is low when
the RTS bit = 1 , and goes high when RTS = O.
Figure 6.
Setting bit ECl to 1 clears the error flags (PE, aVE, and
FE) in the status register. Set ECl to 1 when entering
the hunt phase or enabling the receiver.
Command Byte Format
C/D=l
5
4
LEH1SRES IRTsJeCll SBRK1RxEN IDTR\ TxEN \
L..r
Bit SBRK sends a break. When SBRK = 1, the data
currently being sent is destroyed and the TxDATA pin
goes low. Set SBRK = 0 to release a break. Break also
.
works when TxEN = 0 (send disable).
TxEN
1Transmit Enable
o
I
Disable
1
I
Enable
I DTR Pin Control
DTR
Bit RxEN enables and disables the receiver. RxEN = 1
enables the receiver and RxEN = 0 disables the
receiver. Synchronization is lost if RxEN = 0 during
sync mode.
I
o
1
DTR=l
1
I
DTR=O
J
I RxEN J Receive Enable
o
I
The TxEN bit enables and disables the transmitter.
TxEN = 1 enables the transmitter and TxEN = 0
disables the transmitter. When TxEN = 0, sending
stops and the TxDATA pin goes high (mark status)
after all the currently written data is sent.
I
SBRK
Send Break
0
TxDATA Pin
Normal Operation
1
TxDATA = 0
ECl
Error Clear
0
No Operation
1
Error Flag Clear
..J RTS
Status Register
The CPU can read the status of the JlPD71051 at any
time except when the JlPD71 051 iSJn standby mode.
Status can be read after setting C/D = 1 and RD = O.
Status is not updated while being read. Status updating
is delayed at least 28 clock periods after an event that
affects the status. Figure 7 shows the format of the
status register.
I
0
I
1
'SRES
I
Disable
Enable
1
Bit DTR controls the DTR output pin. DTR goes low
when the DTR bit = 1 and goes high when the DTR
bit = O.
RfS Pin Control
FiTS=l
I
RfS=o
Soltware Reset
0
No Operation
1
Reset Operation
EH [1] Enter Hunt Phase
0
No Operation
1
Enter Hunt Phase
Note:
[1] The EH bit is eflective only in SYNC mode.
83-000788B
1':>
NEe
pPD71051
The aVE bit (overrun error) becomes 1 when the CPU
delays reading the received data and two new data
bytes have been received. In this case, the first data
byte received is overwritten and lost in the receive data
buffer. Figure 9 shows how an overrun can happen.
The PE bit (parity error) becomes 1 when a parity error
occurs in a receive state.
Figure 7.
Status Register Format
C/D=l
I
DSR
5
4
Framing, overrun, and parity errors do not disable the
pPD71 051 's operations. All three error flags are cleared
to 0 by a command byte that sets the ECl bit to 1.
The TxRDY bit becomes 1 when the transmit data
buffer is empty. The TxRDY output pin becomes 1
when the transmit data buffer is empty, the CTS pin is
low, and TxEN = 1. That is, bitTxRDY = Transmit Data
Buffer Empty, pin TxRDY = (Transmit Data Buffer
Empty)-(CTS = O)-(TxEN = 1).
Figure 8.
3
l~~~c/'FEjoVE'PE ITXEM~ RxR DY' TxR DY
L
I
I
1 Character = 5-bit, No Parity, 1 Stop Bit
Same as the Output Pin
Function with the Same Na
TxRDY
Full
1
Empty
PE
Parity Error
0
- No Error
1
- Error
Overrun Error
0
- No Error
FE
Framing Error
I
0
- No Error
DSR
Enter the Break State
I -r . I I It\~
mlI I I~
""'1....
1 -,.1.....1...'-.'
1"",
I
I
Stop Start
Bit
Bit
I
FE = 1
Set because a stop bit
should be here.
[2J A large frequency difference between RxCLK and TxCLK:
RxDATA - - - ,
I 1II! , t:- Sto~
bit
: \ \ \ \ \ \ +/FE - 1
~ ~ , \ \ \ \
This pulse samples the stop bit. Because of
the frequency of RxCLK is lower than that of
_ _ _ _ _ _ _
TxCLK the start bit is sampled too late
in time.
IIIIIII
Sampling
Pulse
I
- Error
-I
1
RxDATA
Start
Bit
OVE
1
[1 J In the break state:
Trasmit Data
Buffer State
0
Framing Error
[3J When data is changed during transmission: [Using less
reliable transmission circuit, etc.J
I
- Error
TxDATA ---,
Start
Bit
~Input
Pin State
0
DSR = 1
1
DSR =0
n nn n
nn
~ I u U+~ I 4J+~
RxDATA - ,
Stop Start
Bit
Bit
\I
n n
Lt-
Stop Start
Bit
Bit
UII~U4.JI~
Bit Change
Bit
Change
FE= 1
Bit Change
83-000796A
83-000797A
Figure 9.
Overrun Error
OVE
RxRDY
Receive Data Buffer
[Second BufferJ
CPU
Receive Buffer
[First BufferJ
R x Data
f/!'W/01l:!¥,6~
~Char1
I I I I I I I I
I I I I I I I I
~Char1
Readcharo--I
~ch~ri~Char1
W~q~¥r)~
I I I I I I I ~ Char2
I I I I I I ~ Char2
~Ch;r1~
f0V44ch~r1~
~Chrr2~A--
WW4c+,2/0Y~
I I I I I I I t0J-- Char 3
~)cj,:r;~
~Char2
Char2
Char 1 is not read by the CPU and is discarded on receipt 01 Char 2
83-0007988
NEe
pPD71051
Sending in Asynchronous Mode
The TxDATA pin is typically in the high state (marking)
when data is not being sent. When the CPU writes
transmit data to the pPD71 051, the pPD71 051 transfers
the transmit data from the transmit data buffer to the
send buffer and sends the data from the TxDAT A pin
after adding one start bit (low level) and a programmed
stop bit. If parity is used, a parity bit is inserted between
the character and the stop bit. Figure 10 shows the data
format for async mode characters. Serial data is sent
by the falling edge of the signal that divided TxCLK
(1/1,1/16, or 1/64).
When bit SBRK is set to 1, the TxDATA pin goes low
(break status), regardless of whether data is being
sent. Figure 11 is a fragment of a typical program to
send data in the async mode. Figure 12 shows the
output from pin TxDAT A.
Asynchronous Mode Data Format
Figure 10.
No Parity
- - - , Start
Mark I Bit
Do
0,
I
On.'
On
::::
With Parity
-:-:-:-1
Mark
I
DO
Start
Bit
0,
I
On.l
Is:;:C
Bit[s]
Data Bits
On
::::
Data Bits
n=4,5,6,7
I
Is:;:C
Parity Bit[s]
Bit
Stop Bit = 1 bit, 1.5 bit, 2 bit
83·000789A
Figure 11.
Asynchronous Transmitter Example
ASYNTX:
TXSTART:
TXDADR
ASYNMOD:
Figure 12.
CALL
MOV
OUT
MOV
IN
TEST1
BNE
MOV
OUT
INC
CMP
BNE
RET
DB
DB
MOV
OUT
OUT
OUT
MOV
OUT
MOV
OUT
RET
ASYNMOD
AL, 00010001 B
PCTRL,AL
BW, OFFSET TXDADR
AL, PCTRL
AL,O
TXSTART
AL, [BW]
PDATA,AL
BW
AL,OOH
TXSTART
;Set async mode
;Command: clear error flag, transmit enable
'NEC'
;Transmit data 4EH, 45H, 43H, 00
;Transmit data area
;Read status
;Wait until TxRDY = 1
;Write transmit data
;Set next data address
;End if data
=0
o
AL,O
PCTRL, AL
PCTRL, AL
PCTRL, AL
AL, 01000000B
. PCTRL, AL
AL,11111010B
.PCTRL, AL
;Writes control bytes three times
;with OOH to unconditionally
;accept the new command byte
;Software reset
;Write mode byte
;Stop bit = 2 bits, even parity
;7 bits/character, x16 clock
TxDATA Pin Output
83-0007908
1-11
NEe
J.lPD71051
Receiving in Asynchronous Mode
The RxDATA pin is normally in the high state when
data is not being received, as shown in figure 13. The
,uPD71051 detects the falling edge of a low level signal
when a low level signal enters it.
The ,uPD71051 samples the level of the RxDATA input
(only when x16 or x64 clock is selected) in a position
1/2 bit ti me after the fall i ng edge of the RxDA T A input
to check whether this low level is a valid start bit. It is
considered a valid start bit if a low level is detected at
that time. If a low level is not detected, it is not regarded
as a start bit and the ,uPD71 051 continues testing for a
valid start bit.
When a start bit is detected, the sampling points of the
data bits, parity bit (when used), and stop bit are
decided by a bit counter. The sampling is performed by
the rising edge of the RxCLK when an X1 clock is used.
When a x16 or x64 clock is used, it is sampled at the
nominal middle of RxCLK.
Figure 13.
RxDATA [2J
Bit Boundary
When a valid stop bit is detected, the ,uPD71 051 waits
for the start bit of the next data. If a low level is detected
in the stop bit, a framing error flag is set; however, the
receiving operation continues as if the correct high
level had been detected. A parity. .error flag is set if a
parity error is detected. An overru'n error flag is set
when the CPU does not read the data in time, and the
next receiving data is transferred to the receive data
buffer, overwriting the unread elata. The jJPD71 051's
sending and receiving operations are not affected by
these errors.
If a low le~el is input to the RxDATA pin for more than
two data blocks during a receive operation, the
,uPD71051 considers it a break state and the SYNC/BRK
pin status becomes 1.
In async mode, the start bit is not detected until a high
level of more than one bit is input to the RxDATA pin
and the receiver is enabled. Figure 14 is a fragment of a
typical program to receive the data sent in the previous
async transmit example.
Start Bit Detection
RxDATA [1J
Data for one character entering the receive buffer is
transferred to the receive data buffer and causes
RxRDY = 1, requesting that the CPU read the data.
When the CPU reads the data, RxRDY becomes O.
~
~
Sampling
_ _---"'_.........
1_
.........._ _ _ _
Note:
[1 J Start bit is not recognized because R x Data is high at the sampling time.
[2J Start Is recognized because R x Data is low at the sampling time.
83-000791 A
Figure 14.
Asynchronous Receiver Example
ASYNRX:
RXSTART:
RXDADR
CALL
MOV
ASYNMOD
AL, 000101 OOB
OUT
MOV
IN
TEST1
BNE
IN
MOV
INC
CMP
BNE
RET
DB
PCTRL,AL
BW, OFFSET RXDADR
AL, PCTRL
AL,1
RXSTART
AL, PDATA
[BWJ, AL
BW
AL,OOH
RXSTART
256DUP
;Set ASYNC mode
;Command: clear error flag, receive
;enable
;Data store area
;Read status
;Wait until RxRDY = 1
;Read and store the receive data
;Set next store address
; End if data = 0
;Reserve receive data area
15
NEe
pPD71051
Figure 15.
Sending in Synchronous Mode
Following the establishment of sync mode and the
enabling of the transmitter,the TxDATA pin stays high
until the CPU writes the first character (normally,
SYNC characters). When data is written, the TxDATA
pin sends one bit for each falling edge of TxCLK if the
CTS pin is low. Unlike async mode, start and stop bits
are not used. However, a parity bit may be set. Figure
15 shows these data formats.
Synchronous Mode Data Format
Character Data without Parity
Do
0,
~:
Dn-,
On
I
I...- - - - - O n e C h a r a c t e r - - - - -...I
I
Character Data with Parity
I
Do
0,
::
On·'
On
n
I
= 4, 5, 6, 7
Once sending begins, the CPU must write data to the
JlPD71051 at the same rate as that of TxCLK. If TxEMP
goes to 1 because of. a delay in writing by the CPU, the
JlPD71051 sends SYNC characters until the CPU writes
data. TxEMP goes to 0 when data is written, and the
data is sent as soon as transmission of SYNC characters
stops.
Figure 16.
Parity
I...- - - - - - O n e Character with Parity -------.1
83-000792A
Synchronous Mode Transmit Timing
No. of Sync characters = 2 [BSC]
!,PD71051 Transmits
Automatically
CTS=O
TxDATA
Mark
TxRDY
[Pin]
TxEMP - - - ,
.----,
I~_--------------------------~I
Data 0
Data 2
Data 3
I~
______________
~
Data 4
r----------,
r-----,
83-000793B
Figure 17. Issuing a Command During SYNC Character
Transmission
No. of Sync Characters = 1
Data
TxRDY
By the 71051
Bythe71051
By the CPU
Sync
Character
Sync
Character
J
L-J
TxEMP _ _ _ _---'
[1]
AD
I[2]
U
U
[4]
[3]
~
U--
Note:
[1] Confirm the automatic trasmlsslon of the SYNC
character by the TxEMP status.
[2] Write SYNC character data.
[3] Confirm the beginning of SYNC character trasmlsslon
by the CPU by reading the status.
[4] Write command word.
B3-000794A
16
NEe
pPD71051
Automatic transmission of SYNC characters begins
after the CPU sends new data. SYNC characters are
not automatically sent by enabling the transmitter.
Figure 16 shows these timing sequences.
If a command is sent to the JiPD71051 while SYNC
characters are automatically being sent and TxEMP =
1, the JiPD71 051 may interpret the command as a data
Figure 18.
SYNTX:
TXlEN:
TXDATA:
SYNC1
SYNC2
lDlEN
TXDADR
SYNMOD:
byte and transmit it as data. If a command must be sent
under these conditions, the CPU should send a SYNC
character to the JiPD71051 and send the command
while the SYNC character is being transmitted. This is
shown in figure 17.
Figure 18 is a fragment of a typical program for sending
in sync mode.
Synchronous Transmitter Example
CAll
MOV
OUT
MOV
MOV
MOV
IN
TEST1
BZ
MOV
OUT
IN
TEST1
BZ
MOV
OUT
INC
DBNZ
MOV
OUT
RET
DB
DB
DB
DB
MOV
OUT
OUT
OUT
SYNMOD
Al, 00010001 B
PCTRl, Al
8W, OFFSET TXDADR
Cl, lDlEN
CH,OOH
Al, PCTRl
Al,O
TXlEN
Al, lDlEN
PDATA,Al
Al, PCTRl
Al,O
TXDATA
Al, (BW)
PDATA,Al
BW
TXDATA
Al, 00010000B
PCTRl, Al
?
?
?
255 DUP (?)
Al,OOH
PCTRl, Al
PCTRl, Al
PCTRl, Al
MOV
OUT
MOV
OUT
Al, 01000000B
PCTRl, Al
Al,001111008
PCTRl, Al
MOV
OUT
MOV
OUT
RET
Al, SYNC1
PCTRl, Al
Al, SYNC2
PCTRl, Al
;Set sync mode
;Command; clear error
;flags, transmit enable
;Start location of data area TxDADR
;Set number of bytes (lDlEN) to be transmitted
;Transmit the length byte
;Transmit the number of
;bytes specified by lDlEN
;Command; clear error
;flags, transmit disable
;SYNC character 1
;SYNC character 2
;transmit data count
;transm it data
;Write control bytes
;three times with OOH to
;unconditionally accept the new
;command byte
;Software reset
;Write mode byte: 2 SYNC
;characters, internal sync detect,
;even parity, 8 bits/character
;Write SYNC characters
17
NEe
Receiving in Synchronous Mode
bit becomes 1, and goes to 0 when the status is read.
The SYNC status bit is set to 1 when the SYNC input
has a rising edge followed by a high level of more than
one period of RxClK, even after synchronization is
achieved.
In order to receive in sync mode, synchronization must
be established with the sending side. The first command
after setting sync mode and writing the SYNC character
must be EH = 1, ECl = 1, and RxEN = 1. When hunt
phase is entered all the bits in the receive buffer are set
to 1. In internal synchronization, data on the RxDATA
pin is input to the receive buffer for each rising edge of
RxClK and is compared with the SYNC character at
the same time. Figure 19 shows this internal sync
detection.
ThepPD71051 can rE3gain lost synchronization anytime
by issuing an enter hunt phase command.
After synchronization, the SYNC character is compared
with each character regardless of whether internal or
external synchronization is used. When the characters
coincide, SYNC becomes 1, indicating that a SYNC
character has been received. SYNC (SYNC status bit
only in external detection) becomes 0 when the status
is read.
When the receive buffer and the SYNC character
coincide, and parity is not used, the pPD71051 ends
hunt phase and SYNC is set to 1in the center of the last
SYNC bit. When parity is'used, SYNC becomes 1 in the
center of the parity bit. Receiving starts with the bit
which follows the bit when SYNC is set to 1.
Overrun and parity errors are checked the same way as
in async mode, affecting only the status flag. Parity
checking is not performed in the hunt phase. Figure 20
is a fragment of a typical program that receives the data
sent by the previous sync transmit program example.
Note that the frequencies of TxClK on the transmitter
and RxCLK on the receiver must be the same.
In external sync detection, synchronization is achieved
by setting the SYNC pin high from an external circuit
for at least one period of RxClK. Hunt phase ends, and
data reception can start. At this time, the SYNC status
Figure 19. Internal Sync Detection Example
5-bit Character, No Parity, 2 Sync Characters
Sync Character 1 = 01100B, Sync Character 2 = 11001B
Sync Character 2
Sync Character 1
LSB
MSB
LSB
~
cb
CPU Operation
SYNC
MSB
11!oi O ! < 1 ! x ! X ! x l
10!o!111!0ixix!xl
®
Receive Buffer
~
cb
®
RxEN=1
1 , 1 , 1
ECL=1
I
1 , 1
I
1
I
1
I
1
I
1
1
I
1 , 1
I
1
I
1
I
1
I
1
I
1 , 1
!1
i
1
' } Mark
1
i 1! 1 i 1 i 1: 1 i 1! 111: 1 i 1: 1 i 1: 1 i 1 i 1.: 1 1 - - 1
: 1 i 1 i 1 i 1 : 1 ; 1 ! 1 I 1 i 1 i 1 ! 1 i 0 i 1 ! 1 i 1 :1 I-- 0
1 : 1 : 1 i .1 i 1 i 1 : 1 ! 1 ! 1 I 1 : 1 ; 1 ; 0 ! 0 ! 1 i 1 ! 1 ! ·1 I-- 0
1 i 1.! 1 : 1 i 1 i 1 ! 1 i 1 i 1 I 1 i 1 ; 0 ! 0 ; 1 ! 1 : 1 i 1: 1 I-- 1
Sync Character 1
1 i 1 i 1 ! 1 i 1. ! 1 ! 1 i 1 i 1 I 1 ! 0 ! 0 ! 1
1 ! 1 i 1 ! 1 ; 1 I-- 1
1 i 1 ! 1 : 1 i 1 ! 1J 1 i 1 : 1 I 0 i 0 ! 1 i 1 : 0 : 1 i 1 ! 1 : 1 I-- 0
1 : 1 i 1 i 1 i 0 i 1 ! 1 i 1 i 1 l o ! 1 i 1 i O! 1 i 1! 1 ! 1 i 1 1 - - 1
1! 1 i 1! O! 0 i 1! 1 i 1: 111 i 1 i 0 i 1 i o! 1! 1! 1! 1 1 - - 0
, ! ' !, ! ' ! ' ! ' ! ' !, : ' I ' : ' i ' : ' i ' ! ' : ' : , ! , 1---, .,,, C.""",,,
1 ! 0 i o! 1 ! 1 ! 1 ! 1 i 1 i 1 I 0 : 1 i o! o! 1 i 1! 1: 1 i 1 1 - - 1
o i 0 i 1 i 1 i 0 ! 1.1 1 ! 1 1 1 I 1 1 0 i 0 ! 1 ! 1 ! 1 ! 1 ; 1 ! 1 I-- 1
o i 1 ! .~ ! 0 1 1 i1 1 1 :1 i 1 I 0 1 0 i 1 ;1 i 0 ! 1 ! 1 1, 1 ; 1 I--- 0 Data
11: 1
I1
Read Status
I
I
RxOATA Input
I ' i ' i' i ' i ' i ' i ' i ' : ' I ' i ' ! ' i ' i ' i ' i ' ! ' i ' I
Command EH=1
All bits are set to 1 by
EH = 1.
Cleared by Status Read
00
00
1
X: don't care
Note:
Since the character is 5 bits, part1 of the sync character register [lower
five bits] is valid and part 2 doesn't mailer. Similarly, in the receive
buffer, part3 is valid and part 4 is not used. SYNC = 1 when part 1 3.
With parity, the LSB of part4 is the parity bit, but it is not compared with
the SYNC character.
=
83-000795B
18
NEe
Figure 20.
pPD71051
Synchronous Receiver Example
SYNRX:
RXlEN:
RXDATA:
STlEN
RXDADR
CAll
MOV
OUT
MOV
IN
TEST1
BZ
IN
MOV
MOV
SYNMOD
Al, 100101 OOB
PCTRl, Al
BW, OFFSET RXDADR
Al, PCTRl
Al,1
RXlEN
Al,DATA
STlEN,Al
Cl, Al
MOV
IN
TEST1
BZ
IN
MOV
INC
DBNZ
MOV
OUT
RET
DB
DB
CH,OOH
Al, PCTRl
Al,1
RXDATA
Al, PDATA
[BW],Al
BW
RXDATA
Al,OOOOOOOOB
PCTRl, Al
?
256 DUP (0)
Standby Mode
The pPD71 051 is a low-power CMOS device. In standby
mode, it disables the external input clocks to the inside
circuitry (ClK, TxClK, and RxClK), thereby consuming less power.
;Set sync mode
;Command: enter hunt
;phase, clear error flags, receive enable
;Set receive data store address
;Receive the number of
;receive data
;Set the number of
;receive data to both variable and
;counter
;Receive and store the
;number of data bytes
;stated by the counter
;Command: receive disable
;Set number of receiver data
;Reserve receive data area
Figure 21.
Standby Mode Timing
Hardware Reset
A hardware reset is one way to enter standby mode.
The input of a high level to the RESET pin causes the
pPD71051 to enter standby mode at the falling edge of
the high level. A software reset command is the other
way to enter standby mode. The only way to take the
pPD71051 out of standby mode is to write a mode byte.
In standby mode, the TxRDY, TxEMP, RxRDY, and
SYNC/BRK pins are at low level and the TxDATA, DTS,
and RTS pins are at high level.
Figure 21 shows the timing for standby mode. While
the internal standby signal is high, the external clocks
to thepPD71 051 are ignored. If data (C/D = 0) is written
to the pPD71 051 in standby mode, the operations are
undefined and unpredictable operation may result.
Mode Word
Software Reset
83-000799A
19
JlPD71 051
20
NEe
NEe
NEe Electronics Inc.
Description
pPD71054
Programmable Timer/Counter
Pin Configurations
The J1PD71 054 is a high-performance, programmable
counter for microcomputer system timing control.
Three 16-bit counters, each with its own clock input,
gate input, and OUT pin, can be clocked from dc to
10 MHz. Under software control, theJ1PD71054 can generate accurate time delays. Initialize the counter, and
the J1PD71054 counts the delay, and interrupts the
CPU when the task is complete. This eliminates the
need for software timing loops.
The J1PD71054 contains three counters capable of
binary or BCD operation. There are six programmable
count modes. The counters operate independently and
each can be set to a different mode. Use address lines
A 1 , Ao to select a counter and perform a read/write
operation.
24-Pin Plastic DIP
Voo
06
05
03
02
01
Do
ClKO
83-000800A
44-Pln Plastic QFP
Features
o Three independent 16-bit counters
o Six programmable counter modes
o Binary or BCD count
o Multiple latch command
o Clock rate: dc (standby mode) to 10 MHz
o Low-power standby mode
o CMOS technology
o Single power supply, 5 V ±10%
o Industrial temperature range -40 to +85°C
o 8 MHz and 10 MHz
Ordering Information
Part Number
Package Type
pPD71054C-8
24-pin plastic DIP
.... ()
z c... c'" c'" c z
()
~ I~
()
()
()
z z z
NC
NC
NC
RD
NC
cs
03
Al
02
Ao
NC
NC
01
ClK2
DO
OUT2
ClKO
GATE2
OUTO
ClKl
NC
NC
C-10
G-8
44-pin plastic QFP (P44G-80-22)
G8-8
44-pin plastic QFP (P44G8-80-384)
()
z
e(
l'
G8-10
L-8
L-10
50009-2 (NECEL-139)
0
()
w c
z z IZ
()
28-pin PLCC
l'
::.
I-
-
0
()
::J
Ui
l-
()
()
()
Z
Z
Z
e(
l'
Note:
[1 J 00 not connect any signal with pin 17.
83-001787A
1m
NEe
pPD71054
Pin Configurations (cont)
Pin Functions
28-Pln PLCC (Plastic Leaded Chip Carrier)
D7-DO [Data Bus]
These pins are an 8-bit three-state bidirectional data
b,us. This t?us is used to program counter modes and to
read status and count values. The data bus is active
when CS = 0, and is high impedance when CS = 1.
N
NNW
~
I- I-
~
0
~ I~ ~ ~ <3
L()
N
IIII:J'
N
'('I')
N
N
N
N
5~
N
0)
,....
AD
26
18
WR
27
17
GATE1
VOO
28
16
oun
0
15
NC
D7
14
GND
Ds
13
GATEO
12
OUTO
NC
Os
1
jlP071054
CLK1
4
Ln
CD
,....
ClKn [Counter Clock, n
,OUTn [Counter Output, n = 0-2]
co en ~ ~
88Bc8~~
0'
83-004204A
Pin Identification
Symbol
Function
D7- DO
Three-state, bidirectional data bus
= 0-2]
These pins are the clock input that determine the count
rate for counter rio The clock rate may be DC (standby
mode) to 8 MHz.
These are the output pins for counter n. A variety of '
outputs is available depending on the count mode.
When the pPD71054 is used as an interrupt source,
these pins can output an interrupt request signal.
GATEn [Counter Gate, n
= 0-2]
These output pins inhibit or trigger counter n according
to the mode selected.
CLKn
Counter n clock output (n = 0-2)
OUTn
Counter n output (n = 0-2)
A1, Ao [Address]
GATEn
Output to inhibit or trigger counter n (n = 0-2)
GND
Ground
These input pins select the counter. A1, Ao equal to 00,
01, or 10 selects counter 0, 1, or 2,respectively. The
control register is selected when A1, Ao equals 11.
These pins are normally connected to the address bus.
IC
Internally connected
Ao-A1
Select counter input 0, 1, or 2
CS
Chip select
CS [Chip Select]
RD
Read strobe
WR
Write strobe
Voo
+5V
When the CS input = 1, all the bits of the data bus
become high impedance. CS must be low to access the
pPD71054.
NC
Not connected
RD [Read Strobe]
The RD input must be low to read data from the
pPD71054.
WR [Write Strobe]
The WR input must be low to write data to the
pPD71 054. The contents of the data bus are written to
the pPD71 054 at the risi ng edge of WR.
Voo [Power]
+5V.
GND [Ground]
Ground.
2
NEe
pPD71 054
Block Diagram
n
07- DO
~
...,.-"
Data Bus
Buffer
[8J
A.
Counter #0
1----------------,
[8J
.J..
~
[8J
::
[8J
~
:
A
[8J
'of
-
r-
Hi9h
[8J
O~'Low
[8J
i
c
i
Hi9h
~
[8J
g~f--
o ....
'Low
[8J
i
,
,
,
,
L
~
I---e-
Down
Counter
[16J
~
Status
Latch [8J
[8J
,
Control
Logic
~
~,
A
0
~
~
~
A.
I~
.
I
\
[8J
~
--y
I
I
UI
GATEO
OUTO
,
L ________________
1-
CLKO
,
8
Status
[ J Register [8J
!
+
II
i
g'6.f--
A
'4
Control
Register
c $~
:, t
_ _c
Read/Write
Controller
+
I
A
1\
I.
,
,
,
,
,
,
,
,
~
CLK1
Counter #1
GATE1
OUT1
.
r
A
[8J
)
.
~
Counter #2
)
CLK2
GATE2
OUT2
--y
"Note:
The internal architecture of counters #1 and #2 is the same as counter #0.
L-__________________________________________________________________________________
Block Functions
Data Bus Buffer
This is an a-bit three-state bidirectional buffer that acts
as an interface between the JlPD71054 and the system
data bus. The data bus buffer handles control commands, the count to be written to the count register,
count data read from the count latch, and status data
read from the status latch.
Read/Write Control
This circuit decodes signals from the system bus and
sends control signals to other blocks of the JlPD71 054.
A1 and Ao select one of the counters or the control
register. A low signal on RD or WR selects a read or
write operation. CS must be low to enable these
operations.
Control Register
This is an a-bit register into which is written the control
command that determines the operating mode of the
counter. Data is written to this register when the CPU
~83~-O~OO~80~lB
executes an OUT command when A1, Ao = 11. The
contents of this register cannot be read if the CPU
executes an I N command when A1, Ao = 11. However,
the multiple latch command allows you to read the
mode and status of each counter.
Counter n [n
= 0-2]
A 16-bit synchronous down counter performs the
actual count operation within the counter. You can
preset this counter and select binary or BCD operation.
The count register is a 16-bit register that stores the
count when it is first written to the counter. The count is
transferred to the down counter and a count operation
for a specified number of counts begins.
The a-bit width of the internal data bus permits the
transfer of only eight bits at a time when the count is
written to the count register. However, when data is
written from the count register to the down counter, all
16 bits can be written at once. When the count is written
to the count register while the counter is in read/write
one byte mode, a OOH is written to the remaining byte of
the register.
3
m
•
NEe
j.lPD71 054
The count latch normally holds the current value of the
down counter. If the contents of the down counter
change, the contents of the count latch also change so
that the two values are the same. When the j.lPD71 054
receives a count latch command, the count latch
latches the value of the down counter and holds it until
the CPU can read it. When the data is read, the count
latch returns to tracking the value of the down counter.
When the mode specified is written to the counter, the
lower six bits of the control register are copied to the
lower six bits of the a-bit status register. The remaining
two bits show the status of the OUT pin and the null
count flag. When the multiple latch command is sent to
the counter, the current value of the status register is
latched into the status latch. This data is held in the
latch until the CPU can read it.
The control logic controls each internal block according
to the mode and the state of the ClK and GATE pins.
The result is output to and sets the state of the OUT pin.
Absolute Maximum Ratings
-0.5 to Voo + 0.3 V
Output voltage, Va
-0.5 to Voo + 0.3 V
Operating temperature, TOPT
-40°C to 85°C
Storage temperature, TSTG
-65°C to +150 °C
Power dissipation, PDMAX
lOW
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Capacitance
TA = +25°C, VDD = a v
Limits
Symbol
Min
Max Unit
Input capacitance
10
pF
1/0 capacitance
20
pF
4
Test Conditions
fc = 1 MHz
Unmeasured pins
returned to 0 V
Symbol Min
Input voltage
high
VIH
2.2
Input voltage
low
VIL
-0.5
Output voltage
high
VOH
0.7
xVoo
Output voltage
low
VOL
Input leakage
current high
Typ
Max
Unit Test Conditions
Voo + 0.3 V
0.8
V
V
IOH = -40011A
0.4
V
IOL = 2.5 rnA
ILiH
10
I1A
VI = Voo
Input leakage
current low
ILiL
-10
I1A
VI =OV
Output leakage
current high
ILOH
10
I1A
Va = Voo
Output leakage
current low
ILOL
-10
I1A
Vo= OV
30
rnA Normal
-0.5 to +7.0 V
Input voltage, VI
Parameter
limits
Parameter
Supply current
I1PD71054
TA = +25°C
Power supply voltage, Voo
DC Characteristics
TA = -40°C to +85°C, VDD = +5 V ±10%
I1PD71054-10
1001
1002
2
50
I1A
1001
10
20
rnA Normal
Stand-by mode
1002
2
50
I1A
Stand-by mode
NEe
pPD71 054
AC Characteristics
TA = -40°C to +85°C, VDD = 5 V ±10%
8 MHz Limits
Parameter
Max
10 MHz Limits
Min
Max
Unit Test Conditions
Symbol
Min
tSAR
30
20
ns
tHRA
10
0
ns
tSCR
0
0
ns
tRRL
150
95
Read Cycle
Address set-up to RD !
Address hold from RD
t
CS set-up to RD !
RD low level width
Data delay from RD !
Data float from RD
120
tORO
t
tFRO
Data delay from address
tOAO
Read recovery time
tRV
10
85
10
220
200
ns
85
ns
CL = 150 pF
65
ns
CL = 20 pF; RL = 2 kn
185
ns
CL = 150 pF
165
ns
Write Cycle
Address set-up to WR !
ns
tSAW
0
tHWA
0
0
ns
CS set-up to WR !
tscw
0
0
ns
WR low level width
tWWL
160
95
ns
t
Data hold from WR t
tsow
120
95
ns
tHWO
0
0
ns
Write recovery time
tRV
200
165
ns
ClK cycle time
tCYK
125
ClK high level width
tKKH
60
60
Address hold from WR
t
Data set-up to WR
ClK and Gate Timing
ClK low level width
tKKL
ClK rise time
tKR
DC
100
DC
ns
30
45
25
ns
25
ns
ClK fall time
tKF
tGGH
50
50
ns
GATE low level width
tGGL
50
50
ns
GATE set-up to ClK
t
t
Clock delay from WR t
tSGK
50
40
ns
GATE hold from ClK
tHKG
50
50
ns
tOWK
Clock set-up to WR
t (latch)
t
tSKW
1m
ns
25
GATE high level width
(count transfer)
25
ns
100
40
ns
tKKH 2: 125 ns
225 - tKKH
40
ns
tKKH:::; 125 ns
85
60
ns
0
ns
GATE delay from WR
tOWG
OUT delay from GATE!
tOGO
120
100
ns
tOKO
150
100
ns
CL = 150 pF
towo
295
240
ns
CL = 150 pF
OUT delay from ClK !
OUT delay from WR
t (initial out)
CL = 150 pF
Notes:
(1) AC timing test pOints for output VOH = 2.2 V, VOL = 0.8 V
5
NEe
pPD71 054
Timing Waveforms
AC Test Input
2.4 V
O.4V
Read Cycle
~2~
.
_
==::C:
2.2 V
Test Points
0.8 V
0.8 V
83-000766A
AD
CLK and GA TE Timing
l--tDAD~~
~--tOAD---
83-001788A
ClK
GATE
Write Cycle
----'---4~
Ir----+----+-------. latch
[2J
OUT
83-001789A
---towo--Note:
Read/Write Recovery
[1 J The last 1 byte of count number writing.
[2J Count latch command or multiple latch command.
83-000773A
83-000772A
6
NEe
pPD71 054
Functional Description
Bits RMW1 and RMW2 specify the read/write operation
to the counter or select the count latch command.
IlPD71 054 System Configuration Example
Bits CM2, CM1, and CMO set the counter mode (0 to 5).
The CPU views the three counters and the control
register as four I/O ports. A1 and Ao are connected to
the A1 and Ao pins of the system address bus. CS is
generated by decoding the address and 10/MEM
signals so that CS goes low when the address bus is set
to the target I/O address and I/O is selected. These
connections are shown in figure 1.
You can use the JlPD71 054 in memory-mapped I/O
configurations. However, the decoding should be such
that CS goes low when memory is selected.
Programming and Reading the Counter
The counter must be programmed and the operating
mode specified before you can use the JlPD71 054.
Once a mode has been selected for a counter, it
operates in that mode until another mode is set. The
count is written to the count register and when that
data is transferred to the down counter, a new count
operation begins. The current count and status can be
read while the counter is in operation. Figure 2 outlines
the steps of operation.
Bit BCD selects binary or BCD operation. The count
may be 0 to FFFFH in binary mode or 0 to 9999 in BCD.
If a control command written to the counter specifies a
mode, the lower six bits of the control command are
copied to the lower six bits of the status register of the
counter selected by SC1 and SCO. The mode selected
remains in effect until a new mode is set. This is not true
if the control command specifies the count latch or
multiple latch command.
Writing the Count
The count is written to the counter after the mode is set.
Set A1, Ao to specify the target counter as shown in
table 1. A new count can be written to a counter at any
time, but the read/write mode selected (when the mode
was written) must be used when writing the count.
Programming the Counter
I n high 1-byte and low 1-byte modes only, the higher or
lower byte of the count register is written by the first
write. The write operation ends and OOH is automatically
written to the remaining byte ,by the JlPD71 054. In the
2-byte modes, the lower byte is written by the fi rst write
and the higher byte by the second.
TheJlPD71 054 is controlled by a microcomputer program.
The program must write a control command to set the
counter mode and write the count data that determines
the length of the count operation. Table 1 shows the
values for A1 and Ao that determine the target counter
for write operations.
For example, if the 2-byte count 8801 H is written to a
counter set in lower 1-byte mode, the lower byte (01 H) ~
is written first, followed by the higher byte (88H). ~
Therefore, the data written to the count register is
0001 H for the first write and 0088H for the second. This
is shown in Table 2.
Table 1.
o
o
Write Operations (CS
= 0, RD = 1, WR = 0)
AO
Write Target
o
Counter 0
Counter 1
o
Counter 2
Control word register
Control and Mode Setting
The control command must be written to set the
counter mode before operating the counter. If a write
operation is performed when A1, Ao = 11, a control
command is written to the control register. Figure 3
shows the format of the 8-bit control command.
Bits SC1 and SCO specify a counter or the multiple
latch command. When a counter is chosen, the specifications described below apply to the counter.
Table 2.
Read/Write Mode and Count Write
No. of
Read/Write Mode
Writes
Count Register
Higher Byte
Lower Byte
Low 1-byte
OOH
High 1-byte
nnH
OOH
nnH
(2nd write)
nnH
(1st write)
Low/High 2-byte
nnH
nnH = Two-digit hexadecimal value
Reading the Counter
The following three methods allow you to read the
contents of the down counter during operation. In
particular, the multiple latch command reads the
current count data and the counter mode orthe state of
the OUT pin. Table 3 shows the values of A1, Ao used to
select the counter to be read.
7
NEe
pPD71 054
Figure 1.
Typical System Configuration
CPU
A1
A1
.J\
iO/MEM
1
l
I
Decoder
L
-
- - - - -
OUT Instruction
CS
- - - - - - OUT Instruction
RD
RD
WR
07" Do
Basic Operating Procedure
IJPD71054
Ao
Ao
A7-A2
Figure 2.
ViR
[8]
07- Do
-
- - - - -
OUT Instruction
83-000802A
- - - - - - IN Instruction
Yes
83-000803A
Figure 3.
Control Register Format
06
\ SC1
05
01
Do
SCO \RWM1 RWMO\ CM2 \ CM1 \ CMO \ BCD \
L~
L,J
I
I
Lr
BCD \ Binary or BCD
\ o \
\ 1 \
Binary Count [16 Bits]
BCD Count [4 Digits]
Count Mode[1]
CM2
CM1
CMO
0
0
0
Mode 0
0
0
1
Mode 1
X
1
0
Mode 2
X
1
1
Mode 3
1
0
0
Mode 4
1
0
1
Mode 5
RWM1 RWMO Read/Write Mode
Note:
Count Latch Command[2]
0
0
0
1
Lower Byte Only
1
0
Higher Byte Only
1
1
Lower Byte then Higher
Select Counter or Multiple
Latch Command
SC1
SCO
0
0
0
1
Counter # 1
1
0
Counter # 2
1
1
Multiple Latch Command[2]
Counter#O
X: Don't Care
[1] CS = 0, AD = 0, ViR = 1
[2] See: Reading the Counter
83-0008048
8
NEe
Table 3.
pPD71054
Read Operations
(CS = 0, iiD = 0, WR = 1)
AD
o
o
o
Read Target
Counter 0
Counter 1
o
Counter 2
Directly Reading the Counter
You can read the current value of the counter by
reading the counter selected 'by A1, Ao as shown in
table 3. This involves reading the count latch; since the
value of the down counter may change while the the
count latch is read, this method may not provide an
accurate reading. You must control the ClK or GATE
input to stop the counter and read it for a correct
reading.
Using the Count Latch Command
When the count latch command is executed, the
current counter value is latched into the counter latch.
This value is held by the latch until it is read or until a
new mode is set. This provides an accurate reading of
the counter value when the command is executed
without affecting counter operation. Figure 4 shows
the format for the count latch command.
If the counter value that was latched into the count
latch is not read before a second count latch command
is executed, the second command is ignored. This is
because the counter value latched by the first command
is held until it is read or until a new mode is set. When
the data in the count latch is read, the latch is released
and continues tracking the value of the down counter.
When the status bit is 0, the status of the selected
counters is latched into the status latches. Bits Os-Do
of the status register show the mode status of the
counter. The output bit (D7) shows the state of the OUT
pin of that counter. These bits are shown in figure 6.
The null count bit (06) indicates whether the count
data is valid. When the count is transferred from the
count register to the down counter, this bit changes to
o to show that the data is valid. Table 4 shows how the
null count flag operates.
Table 4.
Null Count Flag Operation
Null Count Flag
Operation
Write control word for mode set
Write count to count register(1)
1
Transfer count from count register to down counter
0
Note:
(1) When 2-byte mode is selected, the flag becomes 1 when the
second byte is written.
Figure 4.
07
06
Control Register Format for Count Latch
Command
05
o
I
I
SC1
0
I
I
0
I SCO
0
Latch Target
0
0
Counter#O
0
1
Counter # 1
1
0
Counter # 2
1
1
Multiple Latch Command
Note:
When bits SC1 and SCO are 11, the command Is not the count
latch command; it is the mUltiple latch command.
83-00080SA
Using the Multiple Latch Command
When the multiple latch command is received, the
counter value and status register for any counter may
be selectively latched into the count latch and status
latch. Bits 0 1 -05 of the multiple latch command specify
the counter latching. The CPU can then read the status
and counter value for the selected counter. FigureS
shows the format for this command.
Bits CNT2, CNT1 , and CNTO correspond to counters 2,
1, and O. The command is executed for all counters
whose corresponding bit is 1. This allows the data for
more than one counter to be latched by a single count
latch command.
When the count bit is 0, the counter value of the
selected counters is latched into the count latches.
Figure 5.
07
Control Register Format for Multiple Latch
Command
06
I 1 I 1 ICOUNTISTATUSICNT2ICNT1ICNTOI 0 I
Il
0 I Counter # 0 Not Selected
l 1 J Counter # 0 Selected
l
l
J
I
0 I Counter # 1 Not Selected
J
J Counter # 1 Selected
J
1
I 0 I Counter # 2 Not Selected I
I 1 I Counter # 2 Selected
I 0 I Latch Status
l
I
I
1 I Do Not Latch Status
J
I 0 I Latch Count
I
I 1 I Do Not Latch Count
I
83-000B06A
9
NEe
pPD71 054
If the data that was latched is not read before a second
mu Itiple latch command is executed, the second command
is ignored for those latches whose contents have not
been read. This is because the data latched by the first
command is held until it is read or until a new mode is
set. When the data in the latch is read, the latch is
released. See figure 7.
It is possible to latch both the count and status using
two multiple latch commands. However, regardless of
which data is latched first, the status is always read
first. The count data is read by the next read operation
(1- or 2..,step read as determined by read/write mode). If
additional read commands are received, the count data
that has not been latched (the contents of the down
counter as reflected by the current counter value) is
read.
Read operations must be performed in accordance
with read/write mode. In 2-byte mode, two bytes of
data must always be read. This does not imply that the
second byte must be read immediately after the first;
other counter operations may be. performed between
the two reads. For example, you coulcl read the lower
byte, write a new lower byte, read the higher byte, and
write a new higher byte.
Definitions
Initial OUT refers, to the state,of the OUT pin immediately
after the mode is set.
Count transfer refers to the transfer from the count
register to the down counter. The down counter is
decremented at the falling edge of the ClK pulse.
Count zero is the state of the down counter when the
counter is decremented,to zero.
PCNTO, PCNT1, and PCNT2 are the I/O ports for
counters 0,1, and 2, respectively. PCTRl is the I/O port
for the control comm.and.
CW is the control command~
HB is the higher byte of the count.
lB is the lower byte of the count.
In the timing charts for each counter mode, counter 0 is
in the read/write 1-byte and binary count mode. When
no GATE signal appears in the charts, assume a high
level signal. The valu'e shown below the OUT signal is
the counter value. The maximum value that can be set
for the count iheach mode IS O. When this value is set, a
maximum value of 10000H (hexadecimal count) or
10000 (BCD count) is obtained.
Figure 7.
Multiple Latch Command Execution
Example
ClK pulse refers to the time from the rising to the
falling edge of the CLKn input.
Latch Condition
Trigger refers to the rising edge of the GATEn input.
The GATEn input is sampled at each rising edge of the
ClKn input. The GATE input can be level or rising edge
sensitive. In the latter case, counter n's internal flip-flop
is set at the rising eclge of the GATE signal, sensed at
the rising edge of the next ClK pulse, and reset
immediately. This allows edge-triggering to be sensed
whenever it occu rs.
Figure 6.
Start
Latched Count
of Counter 0
Ignored
Status Data
,
*
*
*
EI3 EJ3 .Er:::!J
*
*
EI3
*
*
EJ:!] EJ:!]
Command to
Latch Status
of Counter
1 Ignored. ,
All Latches
Ignored
o Latch Released
• Latched
* Command Ignored
83-00080BA
10
NEe
pPD71054
Counter Modes
Mode 0: Interrupt on End of Count. In this mode, the
OUT output changes from low to high level when the
end of the specified count is reached. See table 5 and
figure 8.
Table 5.
SUBRO:
Mode 0 Operation
Function
Result
Initial OUT
low level
GATE High
Count enable
GATE low
Count disable
Count Write
The OUT pin goes low independent of the ClK pulse.
In 2-byte mode, the count is disabled when the first
byte is written. The OUT pin goes low. OUT goes low
when a new mode or new count is written.
Count
Transfer
and
Operation
Count Zero
Mode 0 Program Example. This subroutine causes a
delay of 10004 (decimal, or 2710H) elK pulses. In this
program, counter 2 is set to 2-byte mode and binary
count. See figure 9.
When the count is written with GATE high:
Transfer is performed at the first ClK pulse after the
count value is written. The down counter is decremented beginning at the first ClK pulse after data
transfer. If a count of n is set, the OUT pin goes high
after n + 1 ClK pulses.
When the count is written with GATE low:
Transfer is performed at the first ClK pulse after the
count is written. The down counter is decremented
beginning at the first ClK pulse after the GATE
signal goes high. If a count of n is set, OUT is low for
a period of n ClK pulses after GATE goes high.
The signal at the OUT pin goes high. The count
operation does not stop and counts down to FFFFH
(hexadecimal) or 9999 (BCD) and continues to count
down.
.
MOV
Al, 1011 OOOOB
OUT
MOV
OUT
MOV
OUT
RET
PCTRl,Al
Al,10H
PCNT2,Al
Al,27H
PCNT2,Al
;set mode: counter 2,
;2-byte mode,
;count mode 0, binary
;write count 10000 (decimal)
Mode 1: GATE Retriggerable One-Shot. I n mode 1, the
pPD71054 functions as a retriggerable one-shot. A
low-level pulse triggered by the GATE input is output
from the OUT pin. See table 6 and figure 10.
Table 6.
Mode 1 Operation
Function
Initial OUT
Result
High level
GATE Trigger(1) Count data is transferred at the ClK pulse after the
trigger.
Count Write
The count is written without affecting the current
operation.
Count
Transfer and
Operation
Transfer is performed at the first ClK pulse after the
trigger. At the same time, the signal at the OUT pin goes
low to start the one-shot pulse operation. The count is
decremented beginning at the next ClK pulse. If a count
of n is set, the one-shot output from the OUT pin
continues for n ClK pulses.
Minimum Count
Count Zero
The signal at the OUT pin becomes high. Count operation does not stop and wraps to FFFFH (hexadecimal)
or 9999 (BCD) and continues to count.
Minimum Count 1
Note:
(1) The trigger is ignored when the count has not been written after
the mode is set, or when only one byte of the count has been
written in 2-byte count mode.
11
1m
•
NEe
pPD71 054
Figure 8.
Mode 0 Timing Chart
OUTO
Count Value
--~--~--~----~--~--~----T----r--~
LJ
GATEO
OUTO
Count Value
83-0008098
Figure 9.
Mode 0 Program Example T.imlng Chart
CLK2
GATE2
OUT2
---.,
Count Value
83-0008108
Figure 10.
Mode 1 Timing Chart
GATEO
---------1 tl---------------\ tl--------------\
OUTO
Count Value
\VA
n-1
--e.:.J
I
tl------~!
tl------- ----
n-2
L..:.J
GATED ________
1n----------------1 n---------------------
OUTD
Count Value
I
n-1
I
n-2
83-000811B
12
NEe
pPD71 054
Mode 1 Program Example. This subroutine waits until
no trigger is generated for an interval of 200 or more
ClK pulses after the first gate trigger and returns to the
main program. Counter 1 is set to low-byte read/write
mode and binary count. See figure 11.
SUBR1:
FSTTRG:
WAIT:
Table 7.
Mode 2 Operation
Function
Result
Initial OUT
High level
GATE High
Count enable
GATE low
Count disabled. If GATE goes low when OUT is low, OUT
will go high (independent of the ClK pulse).
MOV
OUT
MOV
OUT
Al,01010010B
PCTRl,Al
Al,200
PCNT1,Al
;set mode: counter 1,low-byte
;read/write mode, count mode 1,
;binary
;write low byte of count
GATE
Trigger(1)
Transfer is performed at the first ClK pulse after the
trigger.
Count Write
Count is written without affecting the current
operation.
MOV
Al,11100100B
OUT
IN
TEST1
BNZ
PCNT1,Al
Al,PCNT1
AL,7
FSTTRG
;multiple latch command:
;counter 1,
;status
Count
Transfer and
Operation
MOV
Al,11100100B
Transfer is performed at the ClK pulse after the count
is ·Nritten following the mode setting. The counter is
then decremented. Transfer is again performed at the
first ClK pulse after the count becomes 1. When the
trigger is used, transfer is performed at the next ClK
pu Ise. When the contents of the down counter becomes
1, OUT goes low for one ClK pulse and returns to high. If
a count of n is set, OUT repeats this sequence every n
ClK pulses.
;wait for first trigger
OUT
PCTRl,Al
IN
Al,PCNT1
TEST1 Al,7
BZ
WAIT
RET
;multiple latch command:
;counter 1,
;status
;wait until output goes high
Count Zero
Never occurs in this mode.
Minimum
Count
2
Note:
Mode 2: Rate Generator. In mode 2, the signal from the
OUT pin cyclically goes low for one clock period when
the counter reaches 0001 H. The counter operates as a
frequency divider. See table 7 and figure 12.
Figure 11.
(1) The trigger is ignored when the count has not been written or
when only one byte of the count has been written in 2-byte mode.
Mode 1 Program Example Timing Chart
Number of ClK Pulses . 1 - 80 - 1 - 60-100-'- - - 2 0 0 - - - - ' 1
GATE1
r
Return to Main Program
Subroutine Start
83-0008128
Figure 12.
Mode 2 Operation Timing Chart
ClKO
LJ
GATEO
aUTO
Count Value
I
n
I
0003H
I0002H I 0002H I 0003H I 0002H
-~
WR
aUTO
Count Value
I
n
I n-1
I 0006H I 0005H I 0004H I 0003H I 0002H
0001H
0004HI 0003H 10002H
83-0008138
13
NEe
pPD71054
Mode 2 Program Example. This subroutine generates
an interrupt to the CPU each time 10000 (decimal)
clock pulses elapse. Counter 0 is in 2-byte mode and
binary counting. See figure 13.
SUBR3:
MOV
OUT
MOV
OUT
MOV
OUT
RET
Al,00110100B
PCTRl,Al
Al.10H
PCNTO,Al
Al,27H
PCNTO,Al
;mode setting: counter 0, 2-byte
;mode, count mode 2, binary
;write count 10000 (decimal)
Mode 3: Square Wave Generator. Mode 3 is a freq uency
divider similar to mode 2, but with a different duty
cycle. See table 8 and figure 14.
Figure 13.
Table 8.
Mode 3 Operation
Function
Initial OUT
High level
GATE High
Count enable
GATE low
Count disable. If GATE goes low when OUT is low,
OUT will go high (independent of the ClK pulse).
GATE Trigger(1)
Transfer is performed at the first ClK pulse after the
trigger.
Count Write
Current operation is not. affected. The count is
transferred at the end of the half-period of the
current square wave and the OUT pin goes high.
Count
Transfer
and Operation
Count data is transferred at the first ClK pulse after
the count write following the mode setting. Transfer
is performed at the end of the current half-cycle and
the OUT pin is inverted. Transfer is also performed
at the ClK pulse after the trigger. The operation
performed depends on whether count n is even or
odd. When n is even, the count is decremented by
two on each following clock pulse. At the end of the
count of two, the count is again transferred and the
OUT pin is inverted. This is taKen as a half-cycle and
repeated. When n is odd, n - 1 is transferred and
the count is decremented by two on each following clock pulse. The half-cycle when the OUT pin
is high continues until the end of count 0 and
n ,.- 1 is transferred again at the next ClK pulse.
The half-cycle while OUT is low continues until
the end of count 2. Thus, the half-cycle while
OUT is high is one ClK longer than the halfcycle while OUT is low.
Count Zero
Occurs only when the count is odd.
Miniinum Count
3
Mode 2 Configuration
Voo
CPU
INT
1----0<: t - - - - - i
J.
Result
OUTO
83-000814A
Note:
(1) The trigger is ignored when the count has not been written after
the mode is set or when only one byte of count has been written in
2-byte mode.
Figure 14.
Mode 3 Timing Chart.
CLKO
LJ
GATEO
u
OUTO
CounlValue
n-1
I
0004H
I
0002H
n-1
I
0004H
I
0002H
0004HI
0002H
OOOOH
0004H
0004H
I
0002H
I
0004H
I
0004H
0004H
I
0002H
I
OOOOH
I
0004H
OUTO
CounlValue
I
I
0002H
0004H
83·0008158
14
NEe
pPD71 054
Mode 4: Software-Triggered Strobe. In mode 4, when
the specified count is reached, OUT goes low for one
ClK pulse. See table 9 and figure 16.
Mode 3 Program Example. This subroutine divides the
input ClK frequency (5.0688 MHz) by 264 to get a
19,200 Hz clock. Counter 2 is in 2-byte binary mode.
See figure 15.
Table 9.
SUBR4:
MOV
OUT
MOV
OUT
MOV
OUT
RET
Figure 15.
Al,10110110B
PCTRl,Al
Al,08H
PCNT2,Al
A,01H
PCNT2,Al
;mode setting: counter 2, 2-byte
;mode, count mode 3, binary
;264 frequency division
Frequency Division
Voo
IlPD710S4
GATE2
Result
Initial OUT
High level
GATE High
Count enable
GATE low
Count disable
Count Write
Count is transferred at the next ClK pulse when the
count is written. In 2-byte mode, data is transferred
after the second byte is written.
Count
Transfer
and
Operation
Count is transferred at the first ClK following the
count write. If GATE is high, the down counter begins
to decrement from the next ClK. If GATE is low,
decrement begins at the first ClK after GATE goes
high.
Count Zero
OUT is low for one ClK pulse and returns to high. The
down counter Wraps to FFFFH (hexadecimal) or 9999
(BCD) without stopping counter operation.
Minimum Count
1
¢' [19200 Hz]
OUT2
¢ [5.0688 MHz] -
Mode 4. Operation
Function
CLK2
83-000816A
Figure 16.
Mode 4 Timing Chart
OUTO
Count Value
GATEO
OUTO
Count Value
I
n
I
n-1
I
0004H
I
0003H
I
0002H
I
0001H
OOOOH
I
I
I
FFFFH FFFEH FFFDH FFFCH
--------------------~
I
n
I
n-1
I
0004H
I
0004H
I
0004H
I
0003H
I
0002H
I
I
n
I
n-1
I
OOOSH
I
0004H
I
0003H
I
0002H
I
0003H
I
0001H
OOOOH
FFFFH
I
FFFEH
OUTO
Count Value
0002H
I
0001H
83-0008178
15
NEe
pPD71054
Figure 17.
Mode 5 Timing Chart
-
--
- -
-
- -
-
- -
--,
-
GATEO
I
OUTO
I
Count Value
ViR
n
I
n-1
~
GATEO - - - - - - - - -;
OUTO
Count Value
I
n
I
I
n-2
I
n-3
I
0002H
I
0001 H
E::J
n------------------ ------\ n ---- ------
n-1
I
0004H 10003H
I
0002H
I
~
0001H
I OOOOH IFFFFH IFFFEH I0003H 10002H
83-0008188
Mode 5: Hardware-Triggeretl Strobe [Retriggerable].
Mode 5 is similar to mode 4 except that operation is
triggered by the GATE input and can be retriggered.
See table 10 and figure 17.
Table 10.
Mode 5 Operation
Function
Result
Initial OUT
High level
GATE Trigger(1)
The count is transferred at the ClK pulse after the
trigger. The GATE has no effect on the OUT signal.
Count Write
The count is written without affecting the current
operation.
Count
Transfer
and
Operation
Count is transferred at the first ClK pulse after a
trigger, providing that the mode and count have
been written. Decrement begins from the first ClK
pulse after a data transfer. If a count of n is set, OUT
goes low for n + 1 ClK pulses after the trigger.
Count Zero
OUT is low for one ClK and goes high again. The
down counter counts to FFFFH (hexadecimal) or
9999 (BCD) without stopping the counter operation.
Mode 5 Program Example. Use mode 5 to add a
fail-safe function to an interface. For example, the
receiving equipment requests data by issuing a REO
signal to the sending equipment. The sending equipment responds by outputting data to the data bus and
returning a SEND signal to the receiving equipment. In
this type of system, if a malfunction exists in the
sending equipment and no SEND signal is sent, the
receiving equipment waits indefinitely for the SEND
signal and system operation stops. The following
subroutine remedies this situation. If no SEND signal is
output within a given period (50 elK cycles in this
example) after the REO signal is output, the system
assumes the sending equipment is malfunctioning and
a FAil Signal is sent to the receiving equipment.
SUBR5:
MOV Al,00011010B
OUT PCTRl,Al
MOV Al,50
OUT PCNTO,Al
RET
Minimum Count
;mode setting: counter 0, low
;1-byte
;mode, count mode 5, binary
;set interval: 50 ClK pulses
Note:
(1) The trigger is ignored when the count has not been written after
the mode is set or when only one byte has been written in 2-byte
mode.
Figure 18.
Interface Fail-safe Example
Data Bus
Receiving
Equipment
P - - - _ _ . - - - - - - - - - - I S E N D Sending
i-----+-------..-clREQ
Equipment
IlPD71054
83-000819A
16
NEe
NEe Electronics Inc.
pPD71055
Parallel Interface Unit
Description
44-Pln Plastic QFP
The JlPD71055 is a low-power CMOS programmable
parallel interface unitforuse in microcomputer systems.
Typically, the unit's three I/O ports interface peripheral
devices to the system bus.
Features
D Three 8-bit liD ports
D Three programmable operation modes
D Bit manipulation command
D
D
D
D
D
Microcomputer compatible
CMOS technology
Single +5 V ±10% power supply
Industrial temperature range: -40 to +85°C
8 MHz and 10 MHz
NC
NC
Cs
RESET
GNO
Do
Al
01
Ao
02
P27
03
P26
04
P2s
05
P24
06
P 20
07
P2 1
Voo
Ordering Information
Part Number
pPD71055C-8
Clock (MHz)
8
Package
40-pin plastic DIP
C-10
10
G-8
8
44-pin plastic QFP
(P44G-80-22)
G8-8
8
G8-10
10
44-pin plastic QFP
(P44G8-80-384)
L-8
8
L-10
10
83-001218A
44-Pln Plastic Leaded Chip Carrier (PLCC)
r----------,
I-
~
W
44-pin PLCC
~
WR
40-Pln Plastic DIP
NM(J
Q
Q
Z
..
Q
.,,"',..Q
>
C Q Q Q
40
41
28
27
P17
42
26
P15
POs
43
25
P04
P03
2
24
23
22
P14
P13
NC
44
1
P07
P06
Pin Configurations
.....
Q Q
0
pPD7105S
P16
NC
P12
P02
POl
21
20
POo
RD
19
Plo
P23
18
P22
Pll
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
I~~~~~~~~~£&
~
~
~ ~ ~ ~ ~
83-004205A
49-000610A
50010-1 (NECEL-153)
I!'-II
aiiI
NEe
pPD71055
Pin Identification
WR [Write Strobe]
Symbol
Function
CS
Chip select input
GND
Ground
Address inputs 1 and 0
110 port 0, bits 7-0
A1, Ao [Address]
110 port 1, bits 7-0
The A1 and Ao inputs are used in combination with
the RD and WR signals to select one of the three
ports or the command register. A1 and Ao are usually
connected to the lower two bits of the system
address bus (table 1).
110 port 2, bits 7-0
IC
Internally connected
VDD
+5V
°rDo
110 data bus
RESET
Reset input
WR
Write strobe input
RD
Read strobe input
NC
No connection
Pin Functions
07-00 [Data Bus]
DrDo make up an 8-bit, three-state, bidirectional
data bus. The bus is connected to the system data
bus. It is used to send commands to the JLPD71055
and to send data to and from the pPD71 055.
CS [Chip Select]
The es input is used to select the pPD71055. When
es = 0, the pPD71055 is selected and the states of the
DrDo pins are determined by the RD and WR inputs.
When es = 1; the pPD71 055 is not selected and its data
bus is high-impedance.
RD [Read Strobe]
The RD input is set low when data is being read from
the pPD71 055 data bus.
WR [Write Strobe]
The WR input should be set low when data is to be
written to the pPD7.1055 data bus. The contents of
the data bus are written to the pPD71055 at the rising
edge (low to high) of the WR signal.
A1, Ao [Address]
The A1 and Ao inputs are used in combination with
the RD and WR signals to select one of the three
ports or the command register. A1 and Ao are usually
connected to the lower two bits of the system
address bus (table 1).
2
The WR input should be set low when data is to be
written to the pPD71055 data bus. The contents of
the data bus are written to the pPD71055 at the rising
edge (low to high) of the WR signal.
Table 1.
Control Signals and Opera,tion
pPD71 055
Operation
o
o
0
o
o
o
Input
Port 1 to data bus
Input
o
Port 2 to data bus
Input
o
o
Use prohibited'
1
0
0
x
o
o
o
o
o
o
o
Operation
Port 0 to data bus
0
x
x
x
o
x
x
x
x
Data bus to port 0
Output
Data bus to port 1
Output
Data bus to port 2
Output
Data bus to command
register
Output
Data bus high impedance
RESET [Reset]
When the RESET input is high, the JLPD71055 is reset.
The group 0 and the group 1 ports are set to mode 0
(basic I/O port mode). All port bits are cleared to zero
and all ports are set for input.
P07-POO, P17-P10, P27-P20 [Ports 0, 1, 2]
Pins POrPOo, P1rP10, and P2rP20 are the port 0,1,
and 2 I/O pins, bits 7-0, respectively.
IC [Internally Connected]
Pins marked Ie are used internally and must be left
unconnected.
NEe
pPD71 055
Block Diagram
Data
bus
buffer
R[jo--_od
WRo--_od
Read!
A,
o------l~
RESET
o------l~
write
control
cs 0 - - - - - - - '
49·0006118
Functional Description
Ports 0, 1, 2
Group 0 Control and Group 1 Control
The pPD71 055 has three a-bit I/O ports, referred to as
port 0, port 1, and port 2. These ports are divided into
two groups, group 0 and group 1. The groups can be in
one of three modes, mode 0, mode 1, and mode 2.
Modes can be set independently for each group.
These blocks control the operation of group 0 and
group 1.
When port 0 is in mode 0, port 0 and the four upper
bits of port 2 belong to group 0, and port 1 and the four
lower bits of port 2 belong to group 1. When port 0 is
in mode 1 or 2, port 0 and the 5 upper bits of port 2
belong to group 0 and port 1 and the three lower bits of
port 2 belong to group 1.
Command Register
The host writes command words to the pPD71055 in
this register. These commands control group 0 and
group 1. Note that the contents of this register cannot
be read.
Read/Write Control
The read/write control controls the read/write operations for the ports and the data bus in response to the
RD, WR, CS, and address signals. It also handles
RESET signals and the Ao, A1 address inputs.
Data Bus Buffer
The data bus buffer latches information going to or
from the system data bus.
NEe
pPD71 055
DC Characteristics
Absolute Maximum Ratings
(TA = -40 to +85°C, Voo = 5 v ±10%)
(TA = 25°C)
Limits
-0.5 to +7.0 V
Power supply voltage, Voo
Input voltage, VI
-0.5 to Voo + 0.3 V
Parameter
Output voltage, Vo
-0.5 to Voo + 0.3 V
Input voltage
high
VIH
2.2
Voo + 0.3
V
Input voltage
low
VIL
-0.5
0.8
V
Output voltage
high
VOH
0.7 Voo
Output voltage
low
VOL
Darlington
drive current
10AR
Input leakage
current high
IUH
10
Input leakage
current low
IUL
-10
Power dissipation, PD MAX
500mW
Operating temperature, Topt
-40 to +85°C
Storage temperature, Tstg
-65 to +150°C
Comment: These devices are not meant to be operated outside the
limits specified above. Exposure to stresses beyond those listed in
Absolute Maximum Ratings could cause damage. Exposure to an
absolute maximum rating for extended periods may affect reliability.
Capacitance
(TA = 25°C, Voo = GND = 0 V)
Limits
Parameter
Symbol
Input
capacitance
CI
1/0 capacitance CIO
MI.~
Typ
Max Units
10
pF
20
pF
Test
Conditions
fc = 1 MHz
Unmeasured
pins returned
to 0 V
Symbol
Min
Typ
Max
0.4
-1.0
-4.0
Units Test Conditions
V
10H = -400 JJA
V
10L = 2.5 rnA
rnA See test
setup diagram
JJA
VI = VOO
JJA VI =OV
Output leakage ILOH
current high
10
Output leakage ILOL
current low
-10
JJA Vo=OV
10
rnA Normal
operation
JJA
Vo = Voo
Supply current
(dynamic)
JJPD71055
1001
JJPD71055-10
1001
5
10
rnA Normal
operation
Supply current 1002
(standby)
2
50
JJA
Inputs: RESET
= 0.1 V,
others =
Voo - 0.1 V
Outputs: Open
Test Setup for IDAR Measurement
For up to 8 lines chosen arbitrarily
from ports 1 and 2
83VL-6619A
4
NEe
JlPD71 055
AC Characteristics
(TA = -40 to +85°C. Voo = 5 v ±10%)
8 MHz Limits
Parameter
Symbol
Min
Max
10 MHz Limits
Min
Max
Unit Test Conditions
Read Timing
A1. Ao. CS set-up to RD ~
t
A1. Ao. CS hold from RD
tSAR
0
0
ns
tHRA
0
0
ns
160
RD pulse width
tRRL
Data delay from RD ~
tORO
t
tFRO
10
tRV
200
150
ns
tSAW
0
0
ns
tHWA
0
0
ns
100
ns
Data float from RD
Read recovery time
150
120
85
10
ns
100
ns
CL=150pF
60
ns
CL = 20 pF; RL = 2 kn
Write Timing
A1. Ao. CS set-up to WR ~
t
A1. Ao. CS hold from WR
WR pulse width
tWWL
120
t
Data hold from WR t
tsow
100
100
ns
tHWO
0
0
ns
Write recovery time
tRV
200
150
ns
ns
Data set-up to WR
Other Timing
Port set-up time to RD ~
tSPR
0
0
t
tHRP
0
0
ns
Port set-up time to STB ~
tsps
0
0
ns
tHSP
150
Port hold time from RD
Port hold time from STB
Port delay time from WR
t
t
150
350
towp
STB pulse width
tSSL
350
100
DAK pulse width
tOAOAL
300
100
Port delay time from DAK ~(mode 2)
tOOAP
Port float time from DAK t(mode 2)
tFOAP
OBF set delay from WR
t
20
tOWOB
ns
ns
ns
ns
250
ns
CL = 20 pF; RL = 2 kn
300
150
ns
CL=150pF
ns
250
20
OBF clear delay from DAK ~
tooAOB
350
150
IBF set delay from STB ~
tOSIB
300
150
ns
tORIB
300
150
ns
tOOAI
350
150
ns
tOWI
450
200
ns
tOSI
300
150
ns
tORI
400
200
t
INT set delay from DAK t
IBF clear delay from RD
INT clear delay from WR ~
INT set delay from STB
t
INT clear delay from RD ~
RESET pulse width
tRESEn
50
tRESET2
500
CL = 150 pF
150
300
ED
ns
200
CL = 150 pF
ns
50
ps
During right after
power-on
500
ns
During operation
5
NEe
JlPD71 055
Timing Waveforms
AC Test Waveform
.Recovery Time
24
2~.2~______________~2~.2
0:4.===x>
Test Points
0.8
::::::::x===
0.8
49·000166A
AD
\VA
-----:L
Timing Mode 0: Input
49-00027SA
Mode 1: Input
Port
07-00
IBF
------------<
_ _---,--J
49·001140A
Mode 0: Output
INT _ _ _ _ _ _J
Cs, A1,AO
~~--:----:-:-------,;jC
WR ______ts'-A'-W"'
49-001142A
J.-__t _HW_A_ _ __
Mode 1: Output
07-00
Port
49-001141A
INT
07-00
Port
_ _ _ _ _ _ _ _ _.J
49-000276A
6
NEe
IIPD71 055
Timing Waveforms (coni)
Mode 2
INT
07-00
IBF
portO------------~----------~
Perlpheral- fLP071055
fLP071055 -Peripheral
49-000277A
7
NEe
pPD71 055
pPD71055 Commands
Two commands control pPD71055 operation. The
mode select command determines the operation of
group 0 and group 1 ports. The bit manipulation
command sets or resets the bits of port 2. These
commands are executed by writing an 8-bit command
word to the command register (A1AO = 11).
The RD and WR signals that appear in the descriptions
of each mode refer to the port in question as addressed
by A1 and Ao. These signals only affect the port
addressed by A1 and Ao.
Where the port addressed may not be clear, 0 or 1 is
appended to the signal name to indicate the port.
Mode 0
Mode Select
ThepPD71055 port groups have three modes. Modes 0
and 1 can be specified for groups 0 and 1, but mode 2
can only be specified for group O. The bits of all ports
are cleared when a mode is selected or when the
pPD71055 is reset.
Mode o. Basic input/output port operation.
Mode 1. Strobed input/output operation controlled by
three or four bits of port 2 used as control/status
signals.
Mode 2. (Only available for group 0). Port 0 is the
bidirectional 1/0 port and the higher 5 bits of port 2 are
used for status and control signals.
To specify the mode, set the command word as shown
in figure 1 and write it to the command register.
Bit Manipulation Command
This command (figure 2) affects only port 2.lt is mainly
used in mode 1 and mode 2 to control the port 2 bits
which are used as control/status signals. It is also used
to enable and disable pPD71 055-generated interrupts
and to set and reset port 2 general input/output pins.
For example, to set bit 2 of port 2 to 1 (P22 = 1), set the
command word as shown in figure 3 (05H) in the
command register.
Operation in Each Mode
The operation mode for each group in the pPD71055
can be set according to the application. Group 0 can be
in modes 0, 1, or 2, while group 1 is in mode 0 or 1.
Group 1 cannot be used in mode 2.
8
In this mode the ports of the pPD71055 are used to
perform basic 1/0 operations. Each port operates with
a buffered input and a buffered latched output. See
figure 4.
Depending on the control word sent to the pPD71055
from the system bus, ports 0, 1, and 2 can be independently specified for input or output.
Input Port Operation
While the RD signal is low, data from the port selected
by the A1 Ao signals is put on the data bus. See figure 5.
Output Port Operation
When the pPD71 055 is written to (WR = 0), the data on
the data bus will be latched in the port selected by the
A1AO signals at the rising edge of WR and output to the
port pins (figure 6). Following the programming of
mode 0, all outputs are at a low level.
By reading a port which is set for output, the output
value of the port can be obtained.
Note: When group 0 is in mode 1 or mode 2, only bits
P22-P20 of port 2 can be used by group 1. Bit P23
belongs to group o.
Mode 0 Example
This is an example of a CPU connected to an AID
converter via apPD71055 (figure 7). Here both group 0
and group 1 are set to mode 0 and port 2 is used to start
conversion and detect the end of the conversion
process.
Figure 8 is a subroutine that reads the converted data
from an AID converter.
NEe
Figure 1.
pPD71 055
Mode Select Command Word
I
I
1
I
L,J
I
I
J
1
I
Group 1
~
0
OutpUI
1
Inpu1
0
Output
Port 2 (Lower)
Port 1
Mode
1
Inpu1
0
ModeD
1
Model
GroupO
Port 2 (Upper)
PortO
0
Output
1
InpU1
0
OutpU1
1
Mode
InpU1
00
ModeD
01
Model
lX
Mode 2
0
Bit manlpulalion
1
Mode select
Command
select
49-0006138
Figure 2.
Bit Manipulation Command Word
I
o
I
x
I
x
I
x
I
I
I
I
I
I
I
Y
l
I
Bilsellresel
Port 2
bil
select
Command
select
0
1
J
I
Resel
Sel
0
o
0
0 1
Bill
0
1 0
Bil2
0
1 1
Bil3
1
0
Bit 4
1
o
o
1
Bit 5
1
1 0
Bit 6
1
1
Bit 7
BilO
0
1
I
0
I
1
IBit manipulation
I
Mode select
49-0006148
Figure 3.
Bit Manipulation Command Example
I
0
I
x
I
x
I
x
I
0
I
1
I
0
I
1
I =05H
f
Bil
manipulation
Command
Don't care
Specifies bit 2
Bit set
49-000615A
Q
NEe
pPD71055
Figure 4.
Mode 0
Group 1 Mode 0
flPD71055
GroupO
I
I
I
3·
I
1
I
0
I
0
L~
2
0
C
1
I
1: Input
0: Output
t
[1: Input
0
0: OUtput
1: Input
mode
0
0
Mode 0
0
1
Mode 1
1
X
Mode 2
(
.A
A.
4
"
r
.L
~
Port 2
P23-P20
,
<.
4
r
A.
,
<.
J.
8
r
Port 2
P2 7 -P2.
PortO
P07 -POO
Group 0 Mode 0
Command
0
Bit manipulation
select
1
Mode select
I
"Y
T
Port 1
P1 7 -P1 0
flPD71 055
0: Output
1: Input
GroupO
<.
~
8
I
G~UP1
~
A-
O:OutPut
I
I
49·000620A
Figure 5.
Mode 0 Input Timing
Ro~
Port input
0 -0
7
0
-------~--------------------Internal delay
(RD-D 7 -Do)
Internal delay Internal delay
(RD-D7 -Do) (Port-D7 -D o)
49-000618A
Figure 6.
Mode 0 Output Timing
WR-----......\
7
0
0 -0
Port output
_____
~
~X'____ . . J~_x-~=~~=--~=-_:=-_:~-_==+_.... ......
-----------l~....J ,~
In~aldelay
(WR-Port)
49·000619A
10
NEe
Figure 7.
pPD71055
AID Converter Connection Example
CPU
B
.
AID
Converter
fJ. Po71 055
P07
0 7 -0 0
r
I
B
0 7 -00
A'N
POD '
P27
P20
--
Analog signal
EOC
-
-i>u-
__ START
49-000621 A
Figure 8.
AID Converter Example
READ---A/D:
WAIT_EOC:
MOV
OUT
AL,1 0011 OOOB
CTRLPORT,AL
MOV
OUT
IN
TEST1
BNZ
IN
RET
AL,00000001 B
CTRLPORT,AL
AL,PORT2
AL,?
WAIT_EOC
AL,PORTO
;pPD?1055 Mode Setting:
;Group 0, group 1 in mode 0
;Port 0 & port 2 (upper) are inputs
;Port 1 & port 2 (lower) are outputs
;Conversion starts by setting P20 high
;End of conversion wait loop
;Conversion ends when P27 = 0
;Read A/D converted values
~--------------~m
Mode 1
Mode 1 Input Operation
In this mode, the control and status signals control the
I/O data. In group 0, port 0 functions as the data port
and the upper five bits of port 2 function as control/
status. In group 1, port 1 functions as the data port and
the lower three bits of port 2 function as control/status.
I n mode 1 ,portO is the data port for grou pO, and port 1
for group 1. The control/status bits (port 2) are used as
listed below. Figure 10 shows the signal timing.
In mode 1, the bit manipulation command is used to
write the bits of port 2.
Group 0 Mode 1
When group 0 is used in mode 1, the upper five bits of
port 2 become part of group O. Of these five bits, three
are used for control/status and the remaining two can
be used for I/O (using the bit manipulation command).
See figure 9.
Group 1 Mode 1
When group 1 is used in mode 1, the lower three or four
bits of port 2 become part of group 1. Of these four bits,
three are used for control/status. The remaining bit,
P23, can be used for I/O only if group 0 is in mode o.
Otherwise, P23 belongs to group 0 as a control/status
bit. See figure 9 and table 4.
ffi [Strobe]. The data input at port 0 is latched in port
Owhen the STBO input is brought low. The data input at
port 1 is latched in port 1 by STB1.
IBF [Input Buffer Full F/F]. The ISF output goes high to
indicate thatthe input buffer has become full.IBF goes
high when the STB signal goes low. ISF goes low at the
rising edge of the RD signal when STB = 1.
The IBF F/F is cleared when mode 1 is programmed.
INT [Interrupt Request]. INT goes high when the data
is latched in the input port, when RIE is 1 and STB, IBF
and RD are all high. INT goes low at the falling edge of
the RD signal. It can function as a data read request
interrupt signal to a CPU.
INT is cleared when mode 1 is programmed.
11
NEe
pPD71055
Figure 9.
Mode 1 Input
Command word
,
,
Group 1
GroupO
7
L
1
J
0
1
L.----J
I
1
J
i
I
1
I
1
I
0: Output
1: Input
IBFO
~
5Teo
O:Outp ut/
ltlTO
1: Input
5TB1
-
00
GroupO
mode
Mode 0
IBF1
01
Mode 1
INTI
1 X
Mode 2
Group 1
0
Mode 0
mode
1
Model
Command
select
0
Bit manipulation
1
Mode select
fJ,PD71055
P27-P2.
Port 1
input
8
PortO
input
8
-"
1
y
I RI~O I
P25
P2.
P2,·
P22
P2,
P20
•
_____ -1
~
... _____ J
P1 7 -P1 0
P07-PO O
RIEO and RIEl
are controlled by bit
manipulation command
I
I
"Note: Bit P23 Is available In Group 1 only when Group 0 Is Mode O. For all other conditions
P23 Is part 01 Group O. This diagram shows how bit P23 would be used II Group 1
waaln Mode 1.
49-0006'68
Figure 10.
Mode 1 Input Timing
RIE =1
IBF _ _ _ _- J
Port input ----.J"\--->,Pt---+-~''---~-------+_-Portlntemal - . . . , - - - -____,t~H-----M,:_------+_-latch
I~
__________- J
Note: II STB goes low here belore IBF goes low, original contents 01 port latch will change.
STB must be kept high untlllBF goes low to prevent loss 01 date.
49'OOO624A
1?
NEe
JlPD71 055
RIE [Read Interrupt Enable Flag]. RIE controls the
interrupt output. Interrupts can be enabled by using
the bit manipulation command to set this bit to 1, and
disabled by resetting it to o. This signal is internal to the
pPD71055 and is not an output. The state of RI E does
not affect the function of STSO or STS1, which are
inputs to the same bits (P2 4 and P22) of port 2.
Mode 1 Output Operation
I n mode 1 output operation (figu re 11), the status/
control bits (port 2) are used as listed below. Figure 12
shows the signal timing.
OBF [Output Buffer Full F/F]. OBF goes low when data
is received by the pP071 055 and is latched in output
ports 1 or O. OBF functions as a data receive flag. OBF
goes low at the risi ng edge of WR when OAK = 1 (write
complete). It goes high when the OAK signal goes low.
When input is specified in mode 1, the status of I SF,
INT and RIE can be read by reading the contents of
port 2.
Figure 11.
Mode 1 Output
Command word
I
1
I
0
1
L~
GroupO
Group 1
!
!
I
I
0
I
1
I
0
I
f.li>D71055
OBFO
- - - - - - 1 P27
DAKO
r
P2.
0: Output
1: Input
P25-P24
0:0utPutjlNTO
l:lnput
DAKl
00
~
Mode 0
01
Model
INn
OX
Mode 2
Port 1
output
Group 1
mode
0
Mode 0
1
Model
Command
select
0
Bit manipulation
1
Mode select
GroupO
mode
I
WI,:E 0
I
P23* .- ____ J
P22
~,1
P2,
~
- - - - - - 1 P20 _ - - _..J
PortO
output
WIEO and WIEl
are controlled by
manipulation command
I
I
'Note: Bit P23 is available in Group 1 only when Group 0 is Mode o. For all other conditions
P23 is part of Group O. This diagram shows how bit P23 would be used II Group 1
was in Mode 1.
49·0006168
Figure 12.
Mode 1 Output Timing
WIE =1
INT
¥~
YL!.iA
[Note]
j?--
~
I\:
\ X
Port output
l\\),J
"
X
\'
"2J~
Note: If data is written to the IIPD71055 betore OBF goes high the original contents of the
port latch will change. Data must not be written while OBF is low to prevent loss of data
49·000623A
NEe
pPD71055
Table 2.
OAK [Data Acknowledge]. When this input is low, it
signals the pP071055 that output port data has been
taken from the 71055.
Functions of Port 2 Bits In Mode 1
Group Bit
P20
Data Input
Data Output
INT1 (Interrupt request)
INT1 (Interrupt request)
'P2'~"""i'BF1'('i~p~t'b~ff~~"f~ii'fif)""OB'F1''(O~tP'~'t'b'~'ff~~'f~'ii'f'if')"'"
INT [Interrupt Request]. INT goes high when the
output data is taken when WIE is set to 1 and WR, OBF
and OAK areall high. It goes low at the falling edge of
the WR signal. INT therefore functions as a write
request signal, indicating that new data should be
sent to the.pP071055. ;
·p2;......si=s-1..(St~~·b~·i~p·~·t)........·.... ·DAK1-(·D~t~·~~k·~·~;;i~dg·~..........
RIE1 (Read interrupt
enable flag)
input)
WIE1 (Write interrupt
enable flag)
110 (Note)
110 (Note)
............ -....... __ ............................ -....... __ ..... --_ .. _---_ .... --_ .............. __ ........ -..... ---.
P23
WIE [Write Interrupt Enable Flag]. WIE controls the
interrupt output. Interrupts can be enabled by using
the bit manipulation command to set this bit to 1 and
disabled by resetting it to O. This signal is internal to the
pP071 055 and is not an output. The state of WI E does
not affect the function of OAK addressed to the same
bits of port 2.
0
.~?~...... !.~!.~..~!.~.~~!.~.~~~.~.e.~~.~.~.t1.....I.~.~~.~.I.~~.~.~.~~.~.~.!.~~.~.~~~! ......... .
P24
STBO (Strobe input)
RIEO (Read interrupt
enable flag)
110
IBFO (Input buffer
full flf)
110
........ __ ............... ___ ... _..... ___ .... _.. __ ._ ... ··-_0.···· ... ··· ... ···· .. ···· .. ---- ... ···· .. ·_--.····· ....... .
P25
·P-2~
..····I·i·o·· .. ·· .. ············ .. ··· ....·.. ·..
········DAKO·(·D~t~·~·~·k~~·:;;i~d·g·~·······
input)
WIEO (Write interrupt enable
flag)
When output is specified in mode 1, the status of OBF,
INT and WIE can be obtained by reading the contents
of port 2.
OBFO (Output buffer full f If)
Table 2 shows a summary of these signals.
Note: Can be used with group 1 only when group 0 is set to mode O.
In other modes, P23 belongs to group O.
Mode 1 Example
This example (figure 13) demonstrates connecting
a printer to the pP071055. Group 0 is used in mode 1
output. Group f can operate in mode 0 or 1; in this
example it is set to mode 0:
FIgure 13.
Connection to PrInter
CPU
!,-P071055
Printer
0 7 -00
8
.
r
P0 7 -POO
0.,-0 0
8
One-shot delay
OBFO(P27l
OAKO(P2sl
P2s
--9
1>
r
-- STROBE
ACK
BUSY
19-000625A
14
NEe
Figure 14.
pPD71055
Printer Example Subroutine
;This subroutine sends character strings to the printer
INIT:
MOV
AL,10101000B
;pPD71055 Mode Setting:
;Group 0: mode 1 output
;Group 1: mode 0
OUT
CTRLPORT,AL
RET
MOV
SENDPRN:
BW,DATA
;Output data address
PRNLOOP:
MOV
AL,[BW]
AL,OFFH
CMP
;End if data = OFFH
BNZ
WAIT
RET
WAIT:
IN
AL,PORT2
TEST1
AL,7
;Wait until output buffer is empty
, BZ
WAIT
TEST1
AL,5
;Wait until printer can accept data
BNZ
WAIT
MOV
AL,[BW]
;Send data to printer
OUT
PORTO,AL
INC
BW
BR
PRNLOOP
Mode 2
Mode 2 can only be used by group o. In thismode, port
o functions as a bidirectional 8-bit data port operating
a!the rising edge of the WRO signal (end of data write).
It goes high when DAKO is low (output data from port 0
received).
under the control of the upper five bits of port 2 as
control/status signals. In this mode, port 0 combines
the input and output operations of mode 1. See figures
15 and 16.
DAKo [Data Acknowledge]. DAKO is sent to the
pPD71055 in response to the OBFO signal. It should be
set low when data is received from port 0 of the
pPD71055.
In mode 2, the status of the following signals can be
determined by reading port2: OBFO, IBFO, INTO, WIEO,
and RIEO.
WI EO [Write Interrupt Enable Flag]. WIEO controls the
write interrupt request output. Interrupts are enabled
by using the bit manipulation command tosetthis bitto
1 and disabled by setting it to O. The state of WIE does
not affect the DAK function of this pin.
The DAKO and STBO signals are used to select input or
output for port O. By using these signals, bidirectional
operation between the pPD71 055 and peripheral can
be realized.
In mode 2, the bit manipulation command is used to
write to port 2.
Control/Status Port Operation
The following control/status signals are used for output:
6ii'Fo [Output Buffer Full]. OBFO goes low when data
is received from the Do-D7 data bus and is latched in
the port 0 output buffer. It therefore functions as a
receive request signal to the peripheral. OBFO goes low
The following control/status signals are used for input:
STBO [Strobe Input]. When STBO goes low, the data
being sent to the pPD71055 is ratched in port O.
IBFO [Input Buffer Full F/F]. When IBFO goes high, it
indicates that the input buffer is full. It functions as a
signal which can be used to prohibit further data
transfer. IBFO goes high when STBO goes low. It goes
low at the rising edge of RDO when STBO = 1 (read
complete).
15
Ell
NEe
pPD71055
Figure 150
Mode 2
Command word
4
3
iJ.P071055
GroupO
mode
OBFO
P27
o 0
Mode 0
OAKO
P2.
o
1
Model
IBFO
P2 5
1 X
Mode 2
STBO
P2.
INTO
P23
iB
~~
P07-POO
WIEO and RIEO
are controlled by bit
manipulation command
49-Q00627A
Figure 160
Mode 2 Timing
WIEO = 1
RIEO = 1
INTO
• {WINTO
~
J
CU
I
~J
\
/
RINTO
\
~~
X
X Valid
D<
Valid
71055~CPU
CPU~71055
\:
I
I
IBFO
X
Y
1
i
"
PO~POO--~--------~:=~~~---------------------Peripheral~7l055
71055~perlpheral
Note:
WINTO and RINTO are Internal signals and are write and read Interrupt request
signals to the CPU, respectively.
WINTO = 0iiF0 (0) WiEo (0) OAKO (0) WFiO
RINTO = IBFO (0) RIEO (0) STBO (0) ROO
Also note that
INTO = WINTO (+) RINTO
49·00062813
16
NEe
pPD71055
RIEO [Read Interrupt Enable Flag]. RIEO controls the
read interrupt request output. Interrupts are enabled
by using the bit manipulation command to set this bit to
1 and disabled by setting it to O. The state of RI EO does
not affect the STBO function of this pin.
This control/status signal is used for both input and
output:
INTO [Interrupt Request]. During input operations,
INTO functions as a read request interrupt signal.
During output, it functions as a write request interrupt
signal. Thissignal is the logical OR of the INTsignal for
data read (RINTO) and the INTsignal for write (WINTO)
in mode 1 (RINTO OR WINTO).
Table 3.
Functions of Port 21n Mode 2
Bit
Function
P23
INTO (Interrupt request)
P24
STBO (Strobe input)
RIEO (Read interrupt enable flag)
P25
IBFO (Input buffer full f If)
P26
DAKO (Data acknowledge input)
WIEO (Write interrupt enable flag)
P27
OBFO (Output buffer full f If)
Mode 2 Example
Figures 17, 18, and 19 show data transfer between two
CPUs.
In mode 2, the status of OBFO, IBFO, INTO, WIEO, and
RIEO can be determined by reading port 2.
Table 3 is a summary of these signals.
Figure 17.
Connecting Two CPUs
Main CPU
f-lP071055
,.
8
0 7 '°0
'I
INT
°7·°0
Sub CPU
P0 7 -PO O
y
8
°7'°0
'I
INTO
(P2,)
OBFO(P27 )
NMI
OAKO(P26 )
AD
IBFO(P2.)
INT
STBO(P2.)
ViA
49-Q00626A
17
NEe
pPD71055
Figure 18.
Main CPU Flowchart
Main routine
49-006298
18
NEe
Figure 19.
pPD71055
Sub CPU Flowchart
Main routine
Nonmaskable
interrupt
routine
9-000630B
19
NEe
pPD71055
Mode Combinations
Table 4 is a complete list of all the combinations of
modes and groups, and the function of the port 2 bits in
each mode.
Table 4.
Mode Combinations and Port 2 Bit Functions
Group 0
Mode
Group 1
P07-POO
P27
P2&
P25
P24
P23
Mode
P1 7-P1 0
P23
P22
P2 1
0
In
D
D
D
D
NA
0
In
D
D
D
0
In
D
D
D
D
NA
0
Out
D
D
D
0
In
D
D
D
D
NA
In
B
ST81
(RIE1)
IBF1
INn
0
In
D
D
D
D
NA
Out
B
DAK1
(WIE1)
OBF1
INT1
0
Out
D
D
D
D
NA
0
In
D
D
D
D
0
Out
D
D
D
D
NA
0
Out
D
D
D
D
0
Out
0
D
0
D
NA
In
8
STB1
(RIE1)
IBF1
INT1
0
Out
D
D
D
D
NA
Out
B
DAK1
(WIE1)
OBF1
INT1
In
B
B
IBFO
STBO
(RIEO)
INTO
In
NA
D
D
D
In
B
B
IBFO
STBO
(RIEO)
INTO
Out
NA
0
0
D
In
B
B
IBFO
STBO
(RIEO)
INTO
In
NA
STB1
(RIE1)
IBF1
INT1
In
B
B
IBFO
STBO
(RIEO)
INTO
Out
NA
DAK1
(WIE1)
OBF1
INT1
Out
OBFO
DAKO
(WIEO)
B
B
INTO
In
NA
D
D
D
Out
OBFO
DAKO
(WI EO)
B
B
INTO
Out
NA
D
D
D
Out
OBFO
DAKO
(WI EO)
B
B
INTO
In
NA
STB1
(RIE1)
IBF1
INT1
Out
OBFO
DAKO
(WIEO)
B
B
INTO
Out
NA
DAK1
(WIE1)
OBF1
INT1
2
I/O
OBFO
DAKO
(WIEO)
IBFO
STBO
(RIEO)
INTO
0
In
NA
D
D
D
2
I/O
OBFO
DAKO
(WIEO)
IBFO
STBO
(RIEO)
INTO
0
Out
NA
D
D
D
2
I/O
OBFO
DAKO
(WI EO)
IBFO
STBO
(RIEO)
INTO
In
NA
STB1
(RIE1)
IBF1
INT1
2
I/O
OBFO
DAKO
(WIEO)
IBFO
ST80
(RIEO)
INTO
Out
NA
DAK1
(WIE1)
OBF1
INT1
0
0
Note:
(1) In this chart, "NA" indicates that the bit cannot be used by this group.
(2) The symbol "8" indicates bits that can only be rewritten by the bit manipulation command.
(3) In this chart, "D" indicates that is used by the user.
(4) Symbols in parentheses are internal flags. They are not output to port 2 pins and they cannot be read by the host.
(5) In indicates Input, Out indicates Output, and 1/0 indicates Input/Output.
20
P20
D
D
NEe
NEe Electronics Inc.
pPD71059
Interrupt Control Unit
Pin Configurations
Description
The tJPD71059 is a low-power CMOS programmable
interrupt control unit for microcomputer systems. It
can process eight interrupt request inputs, allocating a
priority level to each one. It transfers the interrupt with
the highest priority to the CPU, along with interrupt
address information. By cascading up to eight slave
tJPD71059s to a master tJPD71 059, a system can
process up to 64 interrupt requests. System scale,
interrupt routine address, interrupt request priority,
and masking are all under complete program control.
28-Pin Plastic DIP
Voo
AD
INTAK
INTP 7
INTP.
INTPs
INTP.
Features
(extended mode)
Ordering Information
Part Number
pPD71059C-8
Package
28-pin plastic DIP (600 mil)
C-10
INTP 3
Oz
0,
INTP z
INTP,
DO
INTP o
INT
SAD
o tJPD8085A compatible (CALL mode)
o tJPD70108/70116 compatible (vector mode)
o Eight interrupt request inputs per chip
o Up to 64 interrupt request inputs per system
o Edge- or level-triggered interrupt request inputs
o Each interrupt maskable
o Programmable priority level
o Polling operation
o Single +5 V ±10% power supply
o Industrial temperature range: -40 to +85 DC
o CMOS technology
o 8 MHz and 10 MHz
03
SV[BUFR/Wl
SA z
83-001220A
44-Pin Plastic QFP
CJ
Z
CJ
Z
CJ
Z
10 Ie
~
~
II/)
0
g
>
C0
I~
_
CJ
Z
CJ
Z
NC
NC
07
INTP 7
06
1NTP6
Os
1NTPs
04
1NTP4
03
1NTP3
02
INTP2
0,
INTP,
Do
1NTPo
G-8
44-pin plastic QFP (P44G-80-22)
NC
NC
GB-8
44-pin plastic QFP (P44GB-80-3B4)
NC
NC
GB-10
L-8
L-10
28-pin PLCC
CJ
Z
CJ
Z
0
C
I/)
~
I/)
0
Z
CI
!:! CJz :;
rn
CJ
~ 1!: z
I-
I~
"-
::J
!!I.
lin
50013-1 (NECEL-160)
83-001579A
III
NEe
pPD71059
Pin Configurations (cont)
Pin Functions
28-Pin Plastic Leaded Chip Carrier (PLCC)
07-00 [Data Bus]
The 8-bit 3-state bidirectional bus transfers data to and
from the CPU through the system bus. The data bus
becomes active when data is sent to the CPU in the
I NTAK sequence. Otherwise, the data bus is high
impedance.
lNTAK
26
18
lNTPo
Ao
27
17
INT
voo
28
16
SV[BUFR/Wj
15
14
SA2
13
12
SA1
cs
J.lPD
0
71059
WR
RD
07
DO
CD
I.t)
-.:t
M
0)
(\I
The CPU uses the pPD71059's CS input to select a
pPD71059 to read from (IN instructions) or write to
(OUT instructions). The RD and WR signals to the
IlPD71 059 are enabled when CS is low. CS is not used
for the INTAK sequence.
GND
SAo
o ...
,..
,....
Q
T""
C C C C C C C
63-004217A
Pin Identification
Function
Symbol
Cs [Chip Select]
Data bus 1/0
RO [Read Strobe]
The CPU sets the RD input to 0 when reading the
internal registers IMR, IRR and ISR, and during polling
operations to read polling data.
WR [Write Strobe]
Slave address 1/0, bits 2,1,0
GND
Ground potential
The CPU sets the WR input to 0 when writing initializing
words IW1-IW4 and command words IMW, PFCW and
MCW.
IC
Internally connected
SV (BUFR/W)
Slave (Buffer read write) 1/0
INT
Interrupt output
Ao [Address]
INTPO-INTP7
Interrupt inputs
INTAK
Interrupt acknowledge input
AO
Address input
VDD
Power supply
The Ao input is used with CS, RD, and WR to read or
writeto thepPD71059. Normally, Ao is connected to Ao
of the address bus. Table 1 shows the relationship
between read/write operations and the control signals
(CS, WR, RD, and Ao)~
CS
Chip select input
WR
Write strobe input
INTP7-INTPo [Interrupt Request from Peripheral]
RD
Read strobe input
NC
Not connected
INTPrlNTPoare eight asynchronous interrupt request
inputs. They can be set to be either edge-or leveltriggered. These pins are pulled up by an internal
resistance. Their power consumption is lower at highlevel input than at low-level input.
INT [Interrupt]
INT is the interrupt request output from a
pPD71059 to the CPU or master pPD71 059. When an
interrupt from a peripheral is input to an INTP pin and
acknowledged, the pPD71059 asserts INT high to
generate an interrupt request at the CPU or master
pPD71059.
2
NEe
pPD71059
INTAK [Interrupt Acknowledge]
SA2-SAO [Slave Address]
The I NT AK input from the CPU acknowledges an
interrupt from the pPD71 059. After acknowledging the
interrupt request, the CPU returns three low-level
pulses (pPD8085) or two low-level pulses (pPD70108/
70116). Synchronizing to these pulses, thepPD71059
sends a CALL instruction in three bytes, or an interrupt
vector number in one byte through the data bus.
These pins are only used in systems with cascaded
pPD71 059s. The master pPD71 059 uses these pins to
address up to eight slave pPD71 059s. These pins are
output pins for masters, and input pins for slaves.
Voo [Power Supply]
SV [BUFR/W] [Slave, Buffer Read/Write]
This pin has two functions. When no external buffer is
used in the data bus, it is the SV input. When SV is low,
the pPD71059 acts as a slave. It operates as a master
when SV is high. SV has no master/slave meaning
when the pPD71059 is set to single mode.
As the BUFR/W output, this pin can allow a bus
transceiver to be controlled by the pPD71 059, if one is
required. When the pPD71059 changes its data bus to
output, it sets BUFR/W low. It sets BUFR/W high when
the data bus changes to input.
Table 1.
CS
iii
WR
IC [Internally Connected]
This pin must be left unconnected.
Other Conditions
pPD71 059 Operation
IRR set by MCW
IRR to Data bus
IRR read
ISR to Data bus
ISR read
---.----------------------
--- .. -----._--------------------------------------------
----------------------._.------._----.-------------------
1
1
0
0
D4 = 1
0
Polling data to Data bus
Polling
IMR read
---------"._--------._--- --.-----------------
Data bus to PFCW register
----------.---------.----- -----_ ... _- .. -----------_ .............
---------._-------------------- ---------------------.-----
MCW write
Data bus to IW2 register
IW2 write
... _ ....... __ ...... _--_ ...
-----_ .. _---_ .... _._-- .... _-- ....
x
x
0
.................. __ ._-_._ ... _----_ ... -_.-
(Note 2)
_--.---
x
x
x
Note:
(1) In the polling phase, polling data is read instead of IRR and ISR.
(2) Refer to Control Words section forlW2-IW4 writing procedure.
... _ ........ _ ....... -.....
IW3write
--_ .. __ ._- ........ _--- ..... _--_._ ... _--_ ...
Data bus to IW4 register
IW4write
Data bus to IMR
IMWwrite
-----_._._----._ .. _---. __ ..... _- .. _ ... _---._ .... _----- .. _-----_ ..
After initializing
0
PFCW write
Data bus to MCW register
Data bus to IW3 register
0
IW1 write
------_.--. __ .__ .----.-._._---------
D4 = 0, D3 = 1
--_ ... _--._ ..... _-._ ..... _---_ .. _._- ... -... _--
0
1
CPU Operation
IMR to Data bus
Data bus to IW1 register
"---------._-------._-----
D4, D3 = 0
0
This is the ground potential.
0
Polling phase (Note 1)
0
GND [Ground]
AD
ISR set by MCW
0
This is the positive power supply.
Read/Write Operations
0
0
Note: In the single mode, SA2-SAO are output pins, but the output
data has no meaning.
Data bus high impedance
Illegal
m
NEe
JlPD71059
Block Diagram
SAD
Initialization and
Command Word
Register Group
Data Bus
Buffer
SA,
SA 2
L-...._ _ _
SVI(BUFRIW)
b o 4 - - - - INTAK
RO---..a
WR---+<1
Control Logic
I - - - -. . INT
Readl
Write
Control
cs --------'
In
Service
Register
(ISR)
Priority
Decision
Logic
INTP o
INTP,
INTP 2
INTP 3
INTP.
INTP s
INTP.
INTP 7
49OO0146B
Block Diagram Functions
Interrupt Request Register [IRR]
Data Bus Buffer
The interrupt request register shows which interrupt
levels are currently being requested. If bit n of the IRR
is 1, INTPn is requesting an interrupt. The CPU can
read this register.
The data bus buffer is a buffer between Dr Do and the
pPD71059's internal bus.
Read/Write Control
The read/write control controls the CPU's reading and
writing to and from the pPD71 059 registers.
Initialization and Command Word Registers
These registers store initializing words IW1-IW4 and
command words PFCW (priority and finish control
word) and MCW (mode control word). The CPU
cannot read these registers.
Interrupt Mask Register [IMR]
The interrupt mask register stores the interrupt mask
word (IMW) command word. Each bit masks an interrupt. If bit n of this register is 1, the interrupt request
INTP n is masked and cannot be accepted by the
pPD71 059. The CPU can read this register by performing an IN instruction with Ao = 1.
4
In-Service Register [ISR]
The in-service register shows all interrupt levels currently in service. If bit n of this register is 1, the interrupt
routine corresponding to INTP n is currently being
executed. The CPU can read this register.
Slave Control
Slave control is used in systems with cascaded
pPD71 059s. A master pPD71 059 uses it to control slave
pPD71059s, and a slave uses it to interface with the
master pPD71059.
Control Logic
The control logic receives and generates the signals
that control the sequence of events in an interrupt.
NEe
J.lPD71 059
Priority Decision Logic
DC Characteristics
The priority decision logic determines which interrupt
request from the IRR will be serviced next. The
decision is made based upon the current interrupt
mask, interrupt service status, mode status, and current
priority.
Absolute Maximum Ratings
TA = 25°C
Power supply voltage, Voo
-0.5 to +7.0 V
Input voltage, VI
-0.5 to Voo + 0.3 V
Output voltage, Vo
-0.5 to Voo + 0.3 V
Power dissipation, PDMAX
500mW
Operating temperature, Topt
-40 to +85°C
Storage temperature, Tstg
-65 to +150°C
Comment: Exposing the device to stresses above those listed in the
absolute maximum ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational section of this specification.
Exposure to absolute maximum ratings for extended periods may
affect device reliability.
Capacitance
TA = 25°C; Voo = GND = 0 V
Limits
Parameter
Symbol
Input
capacitance
1/0
capacitance
Min
Typ
Test
Max
Unit
Conditions
CI
10
pF
fc = 1 MHz
CIO
20
pF
Unmeasured pins
returned to 0 V
TA = -40 to +85°C; Voo = 5 V ±10%
Limits
Parameter
Typ
Max Unit Test Conditions
Symbol
Min
Input voltage,
high
VIH
2.2
Voo +
0.3
V
Input voltage,
low
VIL
-0.5
0.8
V
Output voltage,
high
VOH
0.7 x Voo
Output voltage,
low
VOL
0.4
Input leakage
current, high
IUH
10
pA VI = Voo
Input leakage
current, low
IUL
-10
pA VI =OV
Output leakage
current, high
ILOH
10
pA Vo = Voo
Output leakage
current, low
ILOL
-10
pA Vo =0 V
INTP input
leakage
current, high
IUPH
10
pA VI = Voo
INTP input
leakage
current, low
IUPL
V
IOH = -400pA
V
IOL = 2.5 mA
-300 pA VI =OV
Supply current
(dynamic)
pPD71059
1001
3.5
9
mA
pPD71059-10
1001
4
9
mA
Supply current
(power down
mode)
1002
2
50
pA Input pins:
VIH = Voo- 0.1 V
VIL=0.1V
Output pins: open
(Note 1)
Notes:
(1) In power down mode, INTPo-INTP7, INTAK, and CS must be at
high level (VIH = Voo - 0.1 V).
III
NEe
pPD71059
AC Characteristics
TA
= -40 to +85°C; Voo ± 5 v + 10%
10 MHz limits
8 MHz Limits
Symbol
Parameter
Min
Max
Min
Max
Unit Test Conditions
Read Timing
Ao, CS setup to RD
t
tSAR
t
0
0
ns
tHRA
0
0
ns
RD pulse width low
tRRL
160
120
ns
RD pulse width high
tRRH
120
90
Ao, CS hold from RD
t
tORO
t
tFRO
Data delay from RD
Data float from RD
Data delay from Ao, CS
120
10
85
tOAD
200
10
ns
95
ns
CL = 150 pF
60
ns
CL
120
ns
CL
BUFR/W delay from RD
t
tORBL
100
80
ns
BUFR/W delay from RD
t
tORBH
150
100
ns
= 100 pF
= 150 pF
Write Timing
t
Ao, CS setup to WR
t
Ao, CS hold from WR
WR pulse width low.
WR pulse width high
Data setup from WR
Data hold from WR
t
t
tSAW
0
0
ns
tHWA
0
0
ns
tWWL
120
100
ns
tWWH
120
90
ns
tsow
120
100
ns
tHWO
0
0
ns
tlPIPL
100
80
ns
(Note 1)
Slave
Interrupt Timing
INTP pulse width
t
tSSIA
40
40
ns
INTAK pulse width low
tlAIAL
160
120
ns
INTAK pulse width high
tlAIAH
120
SA setup to second, third INTAK
INT delay from INTP
t
SA delay from first INTAK
Data delay from INTAK
Data float from INTAK
t
t
t
ns
INTAK Sequence
tDiPI
300
200
ns
CL = 150 pF
tOIAS
360
250
ns
Master, CL = 150 pF
tDiAO
120
95
ns
CL = 150 pF
60
ns
toso
200
150
tFIAO
10
90
85
10
ns
Slave, CL = 150 pF
BUFR/W delay from INTAK
t
tOIABL
100
80
ns
CL = 150 pF
BUFR/W delay from INTAK
t
tDiABH
150
100
ns
D.ata delay from SA
Other Timing
Command recovery time
INTAK recovery time
INTAK/command recovery time
tRV1
120
90
ns
(Note 2)
tRv2
250
90
ns
(Note 3)
tRv3
250
90
ns
(Note 4)
Notes:
(1) The time to clear the input latch in edge-trigger mode.
(2) The time to move from read to write operation.
(3) The time to move to the next INTAK operation.
(4) The time to move INTAK to/from command (read/write).
6
NEe
JlPD71059
Timing Waveforms
INTAK Sequence (Vector Mode)
A C Test Input/Output Waveform
____
2~.2~____=-~~
0:4-==X>
Test Points
0.8
24
11-
~I
~2~.2
=<::x===
0.8
49·000166A
r-tOIPI
,." ~ I~__\__------
1
INT
Read Cycle
\'------------
tlAIAL
AO,CS ----'1'-------------------------'1'---
0 7 -0 0 --------------1--------1-<1
tRRL---~
1,1.------AD ---+---, I
"f-----------fl
SA 2 -SA o -----------~
INTP Input Should be Maintained..mJ:!!gh Level
until the Leading Edge of the 1stlNTAK Pulse.
49-00016AA
Write Cycle
Other Timing
0 7 -0 0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'1'--_____+--"1'\.______
~ tOIABL
_
INTAK~
=1
~k-----------------
49-00016SA
INTAK Sequence (CALL Mode)
~
1=-
"" --f.=}INT
0 7 -0 0
WR-----------. 1
r-tolPI
~
1....- - \ - - - - - - -____
L
"IWR.".TAK~'~_I
-----------+"'
INTAK or RO/WR
.
il'---......J/
49-000169A
SA -SA _________________......J
2
o
83-001629A
7
NEe
pPD71059
Interrupt Operation
Software Features
Almost all microcomputer systems use interrupts to
reduce software overhead when controlling peripherals. However, the number of interrupt pins on a CPU
is limited. When the number of interrupt lines increases
bey·ond that limit, external circuits like the pPD71 059
become necessary.
The pPD71 059 has the following software features:
The pPD71059 can process eight interrupt request
according to an allocated priority order and transmit
the signal with the highest priority to the CPU. It also
supplies the CPU with information to ascertain the
interrupt routine start address. Cascading pPD71059s
by connecting up to eight "slave" pPD71059s to a
single "master" pPD71 059 permits expansion to up to a
maximum of64 interrupt request signals.
Interrupt system scale (master/slave), interrupt routine
addresses, interrupt request priority, and interrupt
request masking are all programmable, and can be set
by the CPU.
Normal interrupt operation for a single pPD71059 is as
follows. First, the initialization registers are set with a
sequence of initialization words. When the pPD71 059
detects an interrupt request from a peripheral to an
INTP pin it sets the corresponding bit of the interrupt
request register (IRR). The interrupt is checked against
the interrupt mask register (IMR) and the interrupt
service register (ISR). If the interrupt is not masked
and there is no other interrupt with a higher priority in
service or requesting service, it generates an INT
signal to the CPU.
The CPU acknowledges the interrupt by bringing the
INTAK line low. The pPD71059 then outputs interrupt
CALL or vector data onto the data bus in response to
INTAK pulses. During the last INTAK pulse, the
pPD71059 sets the corresponding bit in its ISR to
indicate that this interrupt is in service and to disable
interrupts with lower priority. It resets the bit in the IRR
at this point. When the CPU has finished processing
the interrupt, it will inform the pPD71 059 by sending a
finish interrupt (FI) command. This resets the bit in the
ISR and allows the pPD71 059 to accept interrupts with
lower priorities. If the pPD71 059 is in the self-FI mode,
the ISR bit is reset automatically and this step is not
necessary.
• Interrupt types:
• Interrupt masking:
• End of interrupt:
• Priority rotation:
CALL/vector
Normal/extended nesting
Self-FI/normal FI/
specific FI
Normal nested/extended
nested/exceptional nested
Automatic priority rotation
Rotate to specific priority
• Polled mode
• CPU-readable registers
Hardware Configurations
The pPD71059 has the following hardware configurations:
• Interrupt input:
• Cascading pPD71059s:
• Output driver control:
Edge/level sensitive
Single/extended
(master/slave)
Buffered/non-buffered
Mode Control
These features and configurations are selected and
controlled by the four initialization words (lW1-IW4)
and the three command words (IMW, PFCW, and
MCW). The format of these words are shown in figures
2 and 3, respectively.
Control Words
There are two types of pPD71059 control words:
initialization words and command words.
There are four initialization words: IW1-IW4. These
words must be written to the pPD71 059 at least once to
initialize it. They must be written in sequence.
There are three types of command words: interrupt
mask word (IMW), priority and finish control word
(PFCW), and the mode control word (MCW). These
words can be written freely after initialization.
N'EC
Initialization Words
Initialization sequence. When data is written to a
JlP071059 after setting Ao = 0 and 04 = 1, data is
always accepted as IW1. This results in a default
initialization as shown below. See figure 1.
(1) The edge-trigger circuit of the INTP input is
reset. IRR is cleared in the edge-trigger mode.
(2) ISR and IMR are cleared.
(3) INTP7 receives the lowest priority; INTPo
receives the highest.
(4) The exceptional nesting mode is released. IRR
is set as the register to be read.
(5) Register IW4 is cleared. The normal nesting
mode, non-buffer mode, FI command mode,
and CALL mode are set.
Initialization Words. The initialization words are written
consecutively, and in order. The first two, IW1 and IW2,
set the interrupt address or vector. IW3 specifies which
interrupts are slaves for master systems, and defines
the slave number of a slave system. Therefore, IW3 is
only required in extended systems. TheJlP071059 will
only expect it if bit D1 of IW1, SNGL = O. IW4 is only
written if bit Do of IW1 , 14 = 1. See figu re 2 for the format
of the initialization words.
pPD71059
SIL (specify interrupt level) is set to 1 to change the
priority order or designate an interrupt level. It is used
with.the RP and FI bits (bits 07 and 05). When SIL = 1
and RP or FI = 1, the level identified by I L2-1 Lo is
designated as the lowest priority level. The other
priorities will be set correspondingly. When used with
FI = 1, it resets the ISR bit corresponding to the
interrupt leveIIL2-ILo.
MCW [Mode Control Word]. This word is used to set
the exceptional nesting mode, to poll the JlP071059,
and to read the ISR and IRR registers.
Figure 1.
Initialization Sequence
START
CPU Sends
IW1
[AO=O,04=1]
Command Words
The command words give various commands to a
JlP071059 during its operation to change interrupt
masks and priorities, to end interrupt processing, etc.
See figure 3.
IMW [Interrupt Mask Word]. This word masks the IRR
and disables the corresponding INTP interrupt requests. It also masks the ISR in the exceptional nesting
mode. Bits MrMo correspond to the interrupt levels of
INTPrINTPo, respectively.
In the exceptional nesting mode, interrupts corresponding to the bits of IRR and ISR are masked if the
Mn bit is set to 1.
PFCW [Priority and Finish Control Word]. This word
sets the FI (finish interrupt) command that defines the
way that interrupts are ended, and the commands that
change interrupt request priorities.
When RP (rotate priority) is set to 1, the priorities of the
interrupt requests change (rotate). The priority order
of the 8 I NTP pins is as shown in figure 4. Setting a level
as the lowest priority sets all the other levels correspondingly. For example, if INTP3 is the lowest
priority, INTP4 will be the highest. (INTP7 has the
lowest priority after initialization).
83-0016308
9
NEe
pPD71059
Bits SR and IS/IR are used to read the contents of the
IRR and ISR registers. When SR = 0, no operation is
performed. To read IRR or ISR, set Ao = 0 and select
the IRR or ISR register by writing to MeW. To select
the IRR register, write MeW with SR = 1 and IS/iR = O.
To select the ISR, write MeW with SR = 1 and IS/iR = 1.
The selection is retained, and MeW does not have to
be rewritten to read the same register again. IRR and
ISR are not masked by the IMR.
Figure 2.
Initialization Word Formats (Sheet 1 of 2)
IW1 [Initializalion Word 1]
L
A.
D3
Ds
D.
D7
A7
1
I
As
1
1 LEV
D2
1 AG4
D,
1 SNGL 1
14
1
.1
IIW4
Selection
The Higher 3 Bits of
the Lower Byte of
the Interrupt Routine
Address in CALL Mode
~
Interrupt
Scale
I
l
INTP Input
1
1
IW4Write
IW4 Not Written
Single Mode
1
J
1
Extended Mode
J
1
1
4 Bytes
1
J
o
8 Bytes
1
I
1
I
Level-Trigger Mode
I
1
o
1
Edge-Trigger Mode
1
_I CALL Mode 1
-I Trigger
1
1 o 1
-I Address Gap I
.1
1
1 o 1
IW2 [Inilialization Word 2]
AO
V7 -V 3 :
Higher Byte of Interrupt Routine
Address in CALL Mode
The Higher 5 Bits of Interrupt
Vector Number in Vector Mode
IW3 [Initialization Word 3] Master Mode
INTP Input is a Slave
INTP Input is Not a Slave
49-000160C
10
NEe
Figure 2.
J.lPD71 059
Initialization Word Formats (Sheet 2 of 2)
IW3 [Initialization Word 3) Slave Mode
D.
I
0
I
0
I
0
I
0
I
03
O2
0,
0
SN 2
SN,
SNo
0
0
0
0
0
1
1
0
1
0
2
0
Slave Number
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
IW4 [Initialization Word 4)
I
0
I
0
I
0
I EXTN I
03
O2
BUF
BSV
LJ
0,
I
SFI
VIC
I
Interrupt
Mode
Select
~
FI
Mode
1
Vector Mode
0
CALL Mode
1
Self-FI Mode
0
FI Command Mode
BUF
Buffer
Mode
Select
Extended
Nest
I
I
BSV
0
X
Non-Buffer Mode
1
1
Buffer Mode Master
1
0
Buffer Mode Slave
1
Extended Nest Mode
0
Normal Nest Mode
I
49-000161C
11
NEe
J.lPD71059
Figure 3.
Command Word Format
IMW [Interrupt Mask Word]
I
O2
0,
M2
M,
I
I
I
Mo
I
J
I
Interrupt
Mask
1 1
Set Interrupt Mask
I
Reset Interrupt Mask
0
PFCW [Priority Finish and Control Word]
Ao
07
D.
~
RP
1 SIL
Os
1
FI
03
D.
0
1
1
O2
0,
IL2
IL,
Do
1
ILo
In~:~:~II----I_-+_-+-_-l
No Level
Designation
FI
Command
Priority
Rotation and
FI Command
With Level
Designation
NonFI
Command
No Level
Designation
Without Rotation
Normal FI Command
With Rotation
Normal Rotation FI Command
Without Rotation
Specific FI Command
With Rotation
Specific Rotation FI Command
Without Rotation
No Operation
With Rotation
Specific Rotation Command
Without Rotation
Self-FI Mode Rotation Reset
With Rotation
Self-FI Mode Rotation Set
-~:.
MCW [Mode Control Word]
Ao
07
~
X
D.
Os
1 SNM 1 EXCN 1
03
D.
0
1
O2
0,
Do
POL
1 SR
1 ISIIR
I
Read
Exceptional
LI
/l
X
1
1
1 Polling Command
1
0
1No Operation
Polling
1
1
No Operation
Register
ISRSelect
Select
IRRSelect
No Operation
Nesting
Exceptional Nesting Mode Set
Mode
Exceptional Nesting Mode Release
49~000162C
12
NEe
Figure 4.
pPD71059
Vector Mode [pPD7010S170116 CPUs]
INTP Priority Order
Highest
Priority
Lowest
Priority
After Initialization
In the vector mode, the pPD71059 outputs a one-byte
interrupt vector number to the data bus in the INTAK
sequence. The CPU uses that vector number to generate an interrupt routine address. See figure 7.
The higher five bits of the vector number, Vr V3, are set
by IW2 during initialization. The pPD71059 sets the
remaining three bits to the number of the interrupt
input (0 for INTPo, 1 for INTP1, etc). See figure B.
After Rotation
83-001631A
CALL or Vector Modes
ThepPD71 059 passes interrupt routine address data to
the CPU in two modes, depending on the CPU type.
This mode is set by bit VIC in initialization word IW4.
VIe is set to one to to select the vector mode for
pPD701 OB170116 CPUs, and reset to zero to select the
CALL mode for pPDBOB5A CPUs.
CALL Mode [J.IPDSOS5A CPUs]
In this mode, when an interrupt is acknowledged by
the CPU, thepPD71 059 outputs three bytes of interrupt
data to the data bus in its INTAK sequence. During the
fi rst I NT AK pu Ise from the CPU, the pPD71 059 outputs
the CALL opcode OCDH. During the next INTAK pulse,
it outputs the lower byte of a two-byte interrupt routine
address. During the third INTAK pulse, it outputs the
upper byte of the address. The CPU interprets these
three bytes as a CALL instruction and executes the
CALL interrupt routine. See figure 5 and the INTAK
sequence (CALL mode) pPDBOB5 diagram in the AC
Timing Waveforms.
Interrupt routine addresses are set using words IW1
and IW2 during initialization. However, only the higher
ten or eleven bits of the interrupt addresses are set,
A1S-A6 or A1S-AS. The pPD71059 sets the remaining
low bits (Os-Do or 04-00) to get the address of INTPn's
interrupt routine. The addresses for INTP 1-INTP 7 are
set in order of interrupt level. The space between
interrupt addresses is determined by setting the AG4
bit (address gap 4 bytes) of IW1. When AG4 = 1, the
interrupt routine starting addresses are 4 bytes apart.
Therefore, the starting address for I NTP n is the starting
address for INTPo plus four times n. When AG4 = 0,
starting addresses are eight bytes apart, so the starting
address for INTP n is the starting address for INTPo
plus eight times n. See figure 6.
The CPU generates an interrupt vector by multiplying
the vector number by four, and using the result as the
address of a location in an interrupt vector table
located at addresses 000H-3FFH. See figure 9.
System Scale Modes
The pPD71059 can operate in either single mode, with
up to eight interrupt lines orextended mode, with more
than one pPD71059 and more than eight interrupt
lines. In extended mode apPD71 059 is in either master
or slave mode.
Bit 01, SNGL (single mode), of the first initialization
word IW1 designates the scale of the interrupt system.
SNGL = 1 designates that only onepPD71059 is being
used (single mode system). SNGL = 0 designates an
extended mode system with a master and slave
pPD71059s. In the single mode (SNGL = 1), the SV
input and IW4 buffer mode bits 03 and 02 do not
indicate a master/slave relation for the pPD71059.
Single Mode
This mode is the normal mode of pPD71059 operation.
It has been described in the Interrupt Operation
description. See figure 10 for a system example.
Extended Mode
In this mode, up to 64 interrupt requests can be
processed using a master (pPD71 059 in master mode)
connected to a maximum of eight slaves (pPD71059s
in slave mode). See figure 11 for a system example.
13
nil
all
NEe
pPD71059
Figure 5.
CALL Mode Interrupt Sequence
Peripheral Circuit
[Connected to INTPnJ
CPU (fl.PD8085A)
(Interrupt Enable)
I
I
I
I
Generated Interrupt
Request INTPn
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Hold INTP n High until First
INTAK Pulse Is Generated
I
Reset Interrupt
Request at INTPn
INTAK
Sequence
Output Address
Higher Byte (ADH )
to Data Bus
I
I
I
I
I
Set Bit n of ISR;
Reset Bit n of IRR
I
I
I
I
I
I
49 0OOl~7C
14
NEe
Figure 6.
JlPD71 059
CALL Mode Interrupt Address Sequence
• Address Lower Byte [AOLJ During Second INTAK
AG4
= 1 (4-By1e Spacing Address)
Interrupt
Level
07
03
O2
INTP o
A7
As
As
0
0
0
0
0
INTP,
A7
As
As
0
0
1
0
. 0
INTP 2
A7
As
As
0
1
0
0
0
INTP 3
A7
As
As
0
1
1
0
0
INTP.
A7
As
As
1
0
0
0
0
INTP s
A7
As
As
1
0
1
0
0
INTPs
A7
As
As
1
1
0
0
0
INTP 7
A7
As
As
1
1
1
0
0
0,
AG4
0,
= 0 (8-By1e Spacing Address)
Interrupt
Level
07
03
O2
INTP o
A7
As
0
0
0
0
0
0
INTP,
A7
As
0
0
1
0
0
0
INTP 2
A7
As
0
1
0
0
0
0
INTP 3
A7
As
0
1
1
0
0
0
INTP.
A7
As
1
0
0
0
0
0
INTP s
A7
As
1
0
1
0
0
0
INTP s
A7
As
1
1
0
0
0
0
INTP 7
A7
As
1
1
1
0
0
0
03
O2
0,
A"
AlO
Note: When AG4
= 0, bit As is ignored .
• Address Higher Byte [AOHI During Third INTAK
A,s
A'4
A'3
A'2
83-001632A
~----------------------------------------------------------------------------------------------~
15
m
NEe
pPD71059
Figure 7.
Vector Mode Interrupt Sequence
Peripheral Circuit
Connected to INTPn
.,.PD71 059
CPU (.,.PD70108!70116)
(Interrupt Enable)
I
I
I
I
I
Hold INTPn High until
FirstlNTAK Pulse
is Generated
FirstlNTAK Pulse is
Generated when INT is
INTAK
Sequence
Sel Bit n 01 ISR;
Reset Bit n ollRR
49000148C
16
NEe
Figure B.
pPD71059
Vector Numbers Output in Vector Mode
Output During the Second INTAK
Interrupt
Levels
03
O2
INTP o
V7
V.
Vs
V.
V3
0
0
INTP,
V7
V.
Vs
V.
V3
0
0
1
INTP 2
V7
V.
Vs
V.
V3
0
1
0
0,
0
INTP 3
V7
V.
Vs
V.
V3
0
1
1
INTP.
V7
V.
Vs
V.
V3
1
0
0
INTP s
V7
V.
Vs
V.
V3
1
0
1
INTP.
V7
V.
Vs
V.
V3
1
1
0
INTP 7
V7
V.
Vs
V.
V3
1
1
1
83-00'6338
Figure 9.
Interrupt Vectors for the JiPD7010BI70116
Vector Table
Address
Interrupt Vector Table
OOOH
Vector 0
Program Counter Word
Program Segment Word
004H
Vector 1
008H
Vector 2
Vector Number x 4
(Interrupt vector
table address is
obtained by
multiplying vector
number times four.)
;::---.
3F8H
Vector 254
3FCH
Vector 255
~
____________________________________________________________________________________________________4_9-_OOO_'_52-"A
Figure 10.
Single Mode System
",P071 059
f----------+j INTAK
f-------------I INT
f----------+j Ao
49000'49A
17
~
NEe
J1PD,71059
Figure 11.
Extended System Example with Three Slaves
A
j
Address Bus
II
II
(
II
Control Bus
'\
t
(
~
cs
..
Ao
Master
0,-0 0 INTAK
SA 2 -SA o
INTP o - - - - - - INTP 7
..
.
Data Bus
..
T T T
i"-
-~
rI
Slave Address Local Bus
~
cs
Ao
Slave [SN
~
t
cs
0,-0 0 INTAK
If-
5J
INT INTP o
r
...
'INTP 7
I
6
7
Slave [SN
~
13
SA 2 -SA o
6J
INT INTP o
1
cs
0,-0 0 INTAK
Ao
I
...
1 2 3 4 5
\\ I
\\
\\
...
INTP 7
Slave [SN
0,-0 0 INTAK
Ao
~
7J
INT INTP o
I
...
14 15
I'r-
21
SA 2 -SA o
...
Ifr'r-
INTP 7
...
22 23
29
49-0001508
Master Mode
When a pPD71059 is a master in an extended mode
system, SrSo of IW3 (master mode) define which of
I NTPrl NTPo are inputs from slave pPD71059s or
, peripheral interrupts.
Consider an interrupt request from INTP n. If Sn = 0, the
interrupt is from a peripheral (for example, INTPo of
the master pPD71 059 in Figure 11), and the pPD71 059
treats it the same way it would if it were in the single
mode. SA2-SAO outputs are low level and the master
provides the interrupt address or vector number.
If Sn = 1, the interrupt is from a slave (for example,
INTP 7 of the master). The master sends an interrupt to
the CPU if the slave requesting the interrupt has
priority. The master then outputs slave address n to
pins SA2-SAO on the first INTAK pulse by the CPU. It
lets slave n perform the restof the INTAK sequence.
18
Slave Mode
When a slave receives an interrupt request from a
peripheral, and the slave has no interrupts with higher
priority in service, it sends an interrupt request to the
master through its INT output. When the interrupt is
accepted by the CPU through the master, the master
outputs the slave's address on pins SA2-SAO' Each
slave compares the address on SA 2-SAo to its own
address. The slave that sent the interrupt will find a
match. It completes the INTAK sequence the same
way as a single pPD71059 would.
The master outputs slave address 0 when it is processing a non-slave interrupt. Therefore, do not use 0 as a
slave address if there are less than eight slaves connected to the master.
Figures 12 and 13 show the interrupt operating sequences for slaves in the extended mode.
NEe
Figure 12.
pPD71059
Interrupt from Slave (CALL Mode)
Peripheral Circuit
[Connected to INTP m
In Slave)
Slave JlPD71059
ISm =0)
Master JlPD71 059
[Sn = 1)
I
CPU [JlPD8085A)
[Interrupts Enabled)
I
I
Hold INTPm High Until
First INTAK Pulse is
Generated
Generate First INTAK
Pulse After
Accepting INT
SA2 - SAD
Opcode OCDH
Output to Data Bus
Output SA2 - SAD
Generate Second
INTAK Pulse
INTAK
Sequence
Output Address
Higher Byte (ADHl
to Data Bus
Set Bit m of ISR;
Reset Bit m of IRR
Set Bit n Of ISR;
Reset Bit n of IRR
~ R_e_s_et_B_it~m_o_f_IS_R ~~I·~------------__
__
Reset Bit n of ISR
19
NEe
pPD71059
Figure 13.
Interrupt from Slave (Vector Mode)
Peripheral Circuit
[Connected to INTP m
in SI.aveJ
Slave liP 071 059
[Sm=OJ
Master IIPD71059
[S" = 1J
IIPD70108/70116 [V201V30J
[
I
I
I
I
Generate Interrupt
Request to INTPm
I
II
Hold INTP m High Until
First INTAK Pulse is
Generated
Set Bit n of IRR
I
I
Generate First
Reset Interrupt Request
at INTP m
INTAK
Sequence
iNTAK
Output Vector
to Data Bus
Set Bit m of ISR;
Reset Bit m of IRR
Set Bit n 01 ISR;
Reset Bit n of IRR
Reset Bit m of ISR
Reset Bit n ot ISR
49-000154C
20
NEe
Buffer and Non-Buffer Modes
In a large system, a buffer may be needed by the
pP071059 to drive the data bus. A buffer mode is
supplied, with a signal to specify the buffer direction.
In the buffer mode, SV (BUFR/W) is used to select the
buffer direction and SV cannot be used to specify the
master/slave mode. The master/slave selection must
be set by IW4. IW4 bit 03, BUF (buffer) and D2 , BSV
(buffered slave) are used together to set the buffer
mode and master/slave relation. When BUF = 0, the
non-buffer mode is set and BSV has no meaning. When
BUF = 1, the buffer mode is set. In buffer mode, the
pP071059 is a master when BSV = 1, a slave when BSV
= O. See figure 14.
pPD71059
Figure 14.
Buffer Mode
............ ~
fJ.PD71 059
Buffer
A
~
,.
"
-A
~
A
B
.
D7- DO
I'
D
en
"
In
~
Voo
4B
High Level: A--B
Note 2: The /lPD71059 is set to input SV in its Initial
state and is pulled up by R to set D to the low level
during initialization.
49-000155A
Normal Nesting Mode
This mode is set when IW4 is not written or when IW4
has EXTN = O. It is the most common nesting mode.
See figure 15.
Figure 15.
Lowest
Priority
When an interrupt is being executed in this mode (corresponding bit of ISR = 1), only interrupt requests with
higher priority can be accepted.
7
ISR
The extended nesting mode is set by setting bit 04 of
IW4 in both the master and the slave. Interrupt requests
of a higher level than the one currently being serviced
can be accepted in the master from the same slave in
the extended nesting mode.
Care should be exercised when issuing an FI (finish
interrupt) command in the extended nesting mode. In
an interrupt by a slave, the CPU first issues an FI
command to the slave. Then, the CPU reads the slave's
in-service register (ISR) to see if that slave still has
interrupts in service. If there are no interrupts in
service, (ISR = OOH) an FI command is issued to the
master, as in the single mode when an interrupt is
made by a peripheral.
Highest
Priority
6
I
Extended Nesting Mode
This mode is only applicable to a master in the
extended mode. A slave's eight interrupt priority levels
become only one priority level when viewed by the
master. Therefore, a request made by a slave with a
higher priority than a previous request from the same
slave will not be accepted. This cannot be called
complete nesting since priority ranking within slaves
loses its significance.
Normal Nesting Mode
P;0~1~
I
0
I
I
0
I
I
0
I
I
0
0
0
0
0
Interrupts that can be accepted are INTP 5 through
INTP 0 during execution of interrupt Level 6.
0
Request Generated in Level 2
I
ISRl/offi1/1/0?EO$0?J«a 0
0
Interrupt Level 2 has been accepted and is being executed.
If a
Request Generated in Level 4
IRR
k> $ /% b?f
ISR
1% 0 $ 1 a;; 0
0
:x:
1
0
0
%0
;£ 0 % <1
0
I
0
0
0
10
10
I
Level 4 requests cannot be accepted.
Level 2 FI Command Issued
ISRI20$//t0/£1?1 0
10
Level 4 request can be accepted after processing of
Level 2 has been. ended, when high level is maintained
at INTP4 until INTP4 is accepted.
49-000144A
21
NEe
JlPD71059
Exceptional Nesting Mode
A pP071 059 in the normal or extended nesting mode
cannot accept interrupts of a lower priority than the
interrupts in service. Sometimes, however, it is desirable that requests with lower priority be accepted
while higher-priority interrupts are being serviced.
Setti ng the exceptional nesti ng mode allows th is. After
releasing the exceptional mode, the previous mode is
resumed.
The exceptional nesting mode is controlled by the
SNM (set nesting mode) and EXCN (exceptional nesting mode) bits (06 and Os) of MCW. They set and
release the exceptional nesting mode. The mode
doesn't change when SNM = O. Exceptional nesting is
set if SNM and EXCN = 1 and released when SNM =1
and EXCN = O.
Setting a bit in the IMW in the exceptional nesting
mode, inhibits interrupts of that level and allows
unmasked interrupts to all other levels, higher or lower
priority.
Figure 16. Exceptional Nesting Mode
[a]
Priority
Levels
ISR
Acceptable
Levels
[White blocks]
IMR
Highest
Lowest
Requests from INTPS and INTP7 cannot be accepted when only
bit 2 of the IMR is set to 1.
[b]
Priority
Levels
ISR
Acceptable
Levels
[White blocks]
IMR
Highest
1
_
Setting of exceptional
nesting mode
The procedure for setting the exceptional nesting (EN)
mode is as follows:
(1) Read the ISR.
(2) Write the ISR data to the IMR.
(3) Set the exceptional nesting mode.
Lowest
All requests other than those being executed can be accepted when the IMR is set the
same as the ISR, in exceptional nesting mode.
83·001634A
In this way, all interrupt requests not currently in
service will be enabled.
Figure 16 (a) shows what happens if IMR is not set to
ISR. When the exceptional nesting is set, bit 2 of ISR
will be ignored, and bit 5 will be serviced. Servicing bit
5 will mask the lower priority interrupts 6 and 7. When
the ISR is set equal to the IMR as in (b), all interrupts
except 2 and 5 can be serviced when the exceptional
nesti ng mode is set.
Issuing an FI command to a level masked by the
exceptional nesting mode requires caution. Since the
ISR bit is masked, the normal FI command will not
work. Forthis reason, a specific FI command specifying
the ISR bit must be issued. After the exceptional mode
is released, the normal FI command may be used.
Finishing Interrupts (FI) and Changing
the Priority Levels
The priority and finish control word (PFCW) issues FI
commands and changes interrupt priorities.
Normal FI Command
07
PFCW =
06
Ia I I
0
Os
04
0
03
02
01
Do
I a I x I x Ix I
When a normal FI command is issued, the pP071 059
resets the ISR bit corresponding to the highest priority
level selected from the interrupts in service. This
operation assumes that the interrupt accepted last has
ended.
When an interrupt routine changes the priority level or
the exceptional nesting mode is set, this command will
not operate correctly because the highest priority
interrupt is not necessarily the last interrupt in service.
22
NEe
pPD71059
Specific FI Command
07
PFCW =
06
Os
04
03
02
01
00
I 0 I 1 I 1 I 0 I 0 IIL211L1 IILo
I
When the normal rotation FI command is issued, the
pP071059 resets the ISR bit corresponding to the
highest priority level selected from the interrupts in
service, then rotates the priority levels so that the
interrupt just completed has the lowest priority.
Specific Rotation FI Command
When the specific FI command is issued, thepP071 059
resets the ISR bit designated by bits IL2-ILo of the
PFCW. This command is used when the normal nesting
mode isn't being used.
07
PFCW =
06
Os
I 1 I 1 11
04
I 0
03
I0
02
01
00
IIL211L1 IILo
I
Self-FI Mode
When SFI of IW4 = 1, the pP071 059 is set to the self-FI
mode. In this mode, the ISR bit corresponding to the
interrupt is set and reset during the third INTAK pulse.
Therefore, the CPU does not have to issue an FI
command when the interrupt routine ends. In this
mode, however, the ISR does not store the routine in
service. Unless interrupts are disabled by the interrupt
routine, newly generated interrupt requests are generated without priority limitation by the ISR. This can
cause a stack overflow when frequent interrupt requests
occur, or when the interrupt is level triggered.
Self-FI Rotation
When the specific rotation FI command is issued, the
pP071059 resets the ISR bit designated by bits IL2-ILo
of the PFCW and rotates the interrupt priorities so that
the interrupt just reset becomes the lowest priority.
This change in priority levels is different from the normal
nesting mode, therefore, it is the user's responsibility
to manage nesting.
Specific Rotation Command
07
PFCW =
Rotation of interrupt priorities can be added to the
self-FI mode. In this case, the corresponding interrupt
is set to the lowest priority level when a bit is reset in
the ISR at the end of the INTAK sequence.
Self-FI Rotation Set:
06
Os
04
03
02
01
00
I 1 I 1 I 0 I 0 I 0 IIL211L1 IILo I
When the specific rotation command is issued, the
pP071 059 sets the interrupt priority specified by I L2-1Lo
to the lowest priority. In this case also, the user must
manage nesting.
Triggering Mode
07
PFCW =
06
Os
04
03
02
01
00
I 1 I 0 I 0
0
0
X
X
X
Bit 03 of the first initialization word, IW1, is LEV (Ieveltrigger mode bit). LEV sets the trigger mode of the
INTP inputs. The level-trigger mode is set when LEV =
1. The risi ng-edge-triggered mode is set when LEV = O.
Self-FI Rotation Reset:
Edge-Trigger Mode
06
07
PFCW=
I
o
I
o
Os
I
o
I
04
03
02
01
00
o
I 0
X
X
X
04
03
O2
01
00
0
0
X
X
X
Normal Rotation FI Command
07
PFCW=
06
0
Os
In the edge-trigger mode, an interrupt is detected by
the rising edge of the signal on an INTP input.
Although an IRR bit goes high when INTP is high, the
IRR bit is not latched until the CPU returns an INTAK
pulse. Therefore, the INTP input should be maintained
high until INTAK is received. This filters out noise
spikes on the INT lines. To send the next interrupt
request, temporarily lower the INTP input, then raise it.
23
nil
a.
NEe
pPD71059
Level-Trigger Mode
In the. level-trigger mode, an I RR bit is set by the I NTP
input being at a high level. As in the edge-trigger mode,
the INTP must be maintained high until the INTAK is
received. Interrupts are requested as long as the INTP
input remains high. Care should be taken so as not to
cause a stack overflow in the CPU. See figure 17.
Note: The JlPD71059 operates as if the INTP7 interrupt had
occurred if the INTAK pulse is sent to theJlPD71 059 by the
CPU when the JlPD71 059 INT output level is low. Bit 7 of
ISA is not set. Accordingly, if it is expected that this will
occur, the INTP7 interrupt should be reserved for servicing
incomplete interrupts. The FI should not be issued for
incomplete interrupts. See figure 18.
Figure 17.
When the CPU performs a read operation with Ao = 0 in
the polling mode, polling data as shown in figure 19 is
read instead of ISR or IRR. The pPD71059 then ends
the polling mode.
Figure 19.
Polling Data
03
D.
0,
MCW=LI_1_NT~__o__~1__o~l__o__~I__o~__PL~.~_P_L,~_PL~o~
83-00163SA
The INT bit has the same meaning as the INT pin.
When it is set to 1, it means that the pPD71059 has
accepted an INTP input.
The PL2-PLO (permitted level) bits show which INTP
input requested an interrupt when INT = 1.
INTP Input
If INT in the polling data is 1, thepPD71059 sets the ISR
bit corresponding to the interrupt level shown by bits
PL2-PLO of the polling data and considers that interrupt
as being executed. The CPU then processes the
interrupt accordingly, based on the polling data read.
An FI command should be issued when this processing
ends.
RESTG
49-000156A
Figure 18.
Incomplete Interrupt Request
INTP-.-/
INT--1
\I-_____~
:i :I\....._----First INTAK Pulse
'N~K-------~I~I~~~--INT Ssmpllng by CPU _
I I
_
49-000157A
Polling Operation
When polling, the CPU should disable its INT input.
Next, it issues a polling command to the pPD71059
using MCW with POL = 1. This command sets the
pPD71059 in polling mode until the CPU reads one of
the pPD71059's registers.
24
Note: When a read is performed with AO = 1 after the polling
command is sent to the JlPD71 059, the IMA will be read
instead of polling data. However, when the polling command
is sent, the JlPD71 059 operates in the same manner when
Ao = 0 as it does when Ao = 1. This means that although Ao
was set to 1, the JlPD71 059 will send the contents of the
IMA, but it will also set an ISA bit just as it would if AO had
been set to zero. This may disturb the nesting. Therefore,
performing a read operation with Ao = 1 immediately after
sending the polling command should be avoided.
NEe
NEe Electronics Inc.
Description
The pPD71071 is a high-speed, high-performance
direct memory access (DMA) controller that provides
high-speed data transfers between peripheral devices
and memory. A programmable bus width allows
bidirectional data transfer in both 8- and 16-bit systems.
In addition, the pPD71071 uses CMOS technology to
reduce power consumption.
The pPD71 071 can perform a variety of transfer functions including byte/word, memory-to-memory, and
transfers between memory and I/O. The pPD71071
also utilizes single, demand, and block mode transfers;
release and bus hold modes; and normal and compressed timing.
Features
o Four independent DMA channels
o 16M-byte addressing
o 64K-byte/word transfer count
o 8- or 16-bit programmable data bus width
o Enable/disable of individual DMA requests
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Software DMA requests
Enable/disable of autoinitialize
Address increment/decrement
Fixed/rotational DMA channel priority
Terminal count output signal
Forced transfer termination input
Cascade capability
Programmable DMA request and acknowledge
signal polarities
High-performance data transfer bandwidth
- 5.33 Mbyte/s at 8 MHz
- 6.67 Mbyte/s at 10MHz
pPD70108/70116-compatible
CMOS technology
Low-power standby mode
Single power supply, 5 V ±10%
Industrial temperature range, -40 to +85°C
10-MHz operation
50012-2 (NECEL-302)
pPD71071
DMA Controller
Ordering Information
Part Number
Package
pPD71071C-10
48-pin plastic DIP
L-10
52-pin PLCC
Pin Configurations
48-Pin Plastic DIP
elK
HlDRQ
RESET
HlDAK
END/TC
READY
DMAAK3
cs
DMAAK2
MWR
DMAAKl
MRD
DMAAKO
IOWR
DMARQ3
lORD
DMARQl
AEN
UBE
DMARQO
GND
ASTB
Ao
D1S/ A 2J
Voo
D14/A22
Al
D13/A21
A2
D12/A20
AJ
A4
010/A1S
As
Dg/A17
As
Ds/A1S
A7
D7/A1S
Do/As
Os/A14
Dl/Ag
Ds/A1J
D2/Al0
D4/A12 _o__ _ _---r- DJ/All
83-001876A
NEe
pPD71071
Pin Configurations (cont)
Pin Identification
52-Pin Plastic Leaded Chip Carrier (PLCC)
Symbol
Function
A23- AS/
D15- DO
Bidirectional address/data bus
IC
. Internally connected; leave open
Ar A4
Not connected
Bidirectional address bus
DMAAKO
46
IOWR
A3- AO
DMAR03
45
lORD
44
UBE
Vnn
Power supply
DMAR02
DMAR01
43
AEN
ASTB
Address strobe output
DMAROO
42
ASTB
AEN
Address enable output
GND
41
Ao
UBE
Upper byte enable input/ output
D15/A23
40
Voo
D14/A22
39
A1
lORD
I/O read input/ output
D13/A21
38
A2
10WR
I/O write input/output
D12/A20
37
A3
D11/A19
36
A4
MRD
Memory read output
D10/A18
35
NC
34
A5
NC
~
N
N
N
~
N
~
N
~
N
~
N
~
N
m
N
~
N
Q
~
~
~
N
~
M
~
~~~;!~~~::~..r:.(~
~~~~~~
g~lj~8cr
~~~"O
BSQQ
83-004260A
Pin Functions
ClK [Clock]
ClK controls the internal operation and data transfer
speed of the JlPD71 071.
RESET [Reset]
RESET initializes the controller's internal registers and
leaves the controller in the idle cycle (CPU controls the
bus). Active high.
END/TC [End/Terminal Count]
This is a bidirectional pin. The END input is used to
terminate the current DMA transfer. TC indicates the
designates!....£ycles of the DMA count transfer have
finished. END/TC is open drain and requires an external pull-up resistor. Active low.
DMAAK3-DMAAKO [DMA Acknowledge]
DMAAK3-DMAAKO indicates to peripheral devices
that DMA service has been granted. DMAAK3-DMAAKO
respond respectively to DMA channels 3-0 and the
polarities are user programmable.
2
Address bus output
NC
MWR
Memory write output
CS
Chip select input
READY
Ready input
HlDAK
Hold acknowledge input
HlDRO
Hold request output
ClK
Clock input
RESET
Reset input
ENDITC
End DMAtransfer input/terminal count output
DMAAK3DMAAKO
DMA acknowledge output
DMAR03DMAROO
DMA request input
GND
Ground
DMARQ3-DMARQO [DMA Request]
DMARQ3-DMARQO accept DMA service requests from
peripheral devices. DMARQ3-:DMARQO respond respectively to DMA channels 3-0 and the polarities are
user programmable. DMARQ must remain asserted until
DMAAK is asserted.
GND [Ground]
GND connects to the power supply ground terminal.
A23-AS/D1S-Do [Address/Data Bus]
A23-AS/D1S-DO function as a 16-bit, multiplexed address/
data bus when the JlPD71 071 is in the 16-bit data mode.
In the 8-bit data mode, A23-A16 (pins 13-20) become
address bits only and A1s-As/DrDo (pins 21-28) remain
an 8-bit multiplexed address/data bus. A23-AS/D1S-Do
are three-state.
NEe
pPD71071
A7-A4, A3-AO [Address Bus]
CS [Chip Select]
ArA4, A3-AO function as the lower eight bits of the address
bus. ArA4 output memory addresses during the DMA
cycle and become high impedance in the idle cycle.
A3-AO function as the lowerfour bits of the address bus.
In the idle cycle, A3-AO become address inputs to select
internal registers for the CPU to read or write. In the
DMA cycle, A3-AO output memory addresses.
During the idle cycle, CS selects the j1PD71071 as an
I/O device. Active low.
READY [Ready]
VDD connects to the +S-V power supply.
During a DMA operation, READY indicates that a data
transfer for one cycle has been completed and may be
terminated. To meet the requirements of low-speed I/O
devices or memory, READY may be negated to insert
wait states to extend the bus cycle until READY is again
asserted.
ASTB [Address Strobe]
HLDAK [Hold Acknowledge]
ASTS latches address A23-A8 (16-bit mode)/ A15-A8 (8bit mode) from the address/data bus into an external
address latch at the falling edge of ASTS during a DMA
cycle. Active high.
When active, HLDAK indicates that the CPU has
granted the j1PD71 071 the use of the system bus. Active
high.
Voo [Power Supply]
HLDRQ [Hold Request]
AEN [Address Enable]
AEN enables the output of an external latch that holds
DMA addresses. AEN becomes high during the DMA
cycle.
UBE [Upper Byte Enable]
HLDRQ outputs a bus hold request to the CPU. Active
high.
Block Diagram Description
The j1PD71 071 has the following functional units.
USE indicates the upper byte of the data bus is valid
during 16-bit mode. In the idle cycle during data
transfer, the j1PD71 071 acknowledges data on 015-08
when USE is asserted. During a DMA cycle, USE goes
low to signify the presence of valid data on 015-08.
USE has no meaning in 8-bit mode and becomes high
impedance in the idle cycle and high level in the DMA
cycle. Three-state, active low.
•
•
•
•
•
•
•
lORD [1/0 Read]
The bus control unit consists of the address and data
buffers, and bus control logic. The bus control unit
generates and receives signals that control addresses
and data on the internal address and data buses.
In the idle cycle, lORD inputs a read signal from the
CPU. In the DMA cycle, lORD outputs a read signal to
an I/O device. Three-state, active low.
10WR [1/0 Write]
In the idle cycle, 10WR inputs a write signal from the
CPU. In the DMA cycle, 10WR outputs a write signal to
an I/O device. Three-state, active low.
MRD [Memory Read]
Sus control unit
DMA control unit
Address registers
Address incrementer/decrementer
Count registers
Count decrementer
Control registers
Bus Control Unit
DMA Control Unit
The DMA control unit contains the priority and timing
control logic. The priority control logic determines the
priority level of DMA requests and arbitrates the use of
the bus in accordance with this priority level. The DMA
control unit also provides internal timing and controls
DMA operations.
During the DMA cycle, MRD outputs a read signal to
memory. MRD is high impedance during the idle cycle.
Three-state, active low.
MWR [Memory Write]
During the DMA cycle, MWR outputs a write signal to
memory. MWR is high impedance during the idle cycle.
Three-state, active low.
3
NEe
pPD71071
Block Diagram
~
<
~
··
Bus Control Unit
II
Address Bus
Buffer
·
Data Bus
Buffer
cs
~
Internal Address
Bus (24)
I
Address
Registers
ClK
RESET
READY
Bus Control
logic
ASTB
Address
Incrementerl
Decrementer
(24)
I
I
D
(24x4)
Base
(24x4)
MRD,MWR
A
II
1\
~
DMARQ3
DMARQO
A
<
Internal Data Bus (16)
~y
\j
DMA Control Unit
l
Count
Registers
Priority
Control
logic
DMAAK3
(
DMAAKO 't
I
I
Base
(16x4)
Current
(16x4)
HlDAK
Timing
Control
logic
I
I
I
I
I
"\ I
vi I
I
I
Channel
Device Control
Status
Mode Control
Temporary
(5)
(10)
(8)
(7x4)
(16)
Request
(4)
Mask
(4)
I
I
I
I
I
I
I
~J
"
HlDRQ
I
I
-~}
AEN
UBE
Control Registers
Current
Count
Decrementer
(16)
Terminal Count
END/TC
49·0005188
Address Registers
Each of the four DMA channels has one 24-bit base
address register and one 24-bit current address register.
The base address register holds a value determined by
the CPU and transfers this value to the current address
register during autoinitialization (address and count
are automatically initialized). The channel's current
address register is incremented/decremented foreach
transfer and alwQyscontains the address of the data to
be transferred next.
generates a terminal count when the count register is
decremented to FFFFH.
Note: The number of DMA transfer cycles is actually the value
of the current count register + 1. Therefore, when programming the count register, specify the number of DMA
transfers minus one,
Count Decrementer
The count decrementer decrements the contents of the
current count register by one when each DMA transfer
cycle ends.
Address Incrementer/Decrementer
The address incrementer/decrementer updates the
contents of the current address register whenever a
DMA transfer completes.
Count Registers
Each of the four DMA channels has one i6-bit base
count register and one i6-bit current count register.
The base count register holds a value written by the
CPU and transfers the value to' the current count
register during autoinitialization. A channel's current
count register is decremented for each transfer and
4
Control Registers
The pPD7i 071 contains the following control registers.
•
•
•
•
•
•
•
Channel
Device
Status
Mode
Temporary
Request
Mask
These registers control bus mode, pin active levels,
DMA operation mode, mask bits, and other pPD71 071
operating functions.
NEe
pPD71071
Absolute Maximum Ratings
DC Characteristics
-0.5 to +7.0 V
Power supply voltage, Voo
Input voltage, VI
-0.5 to Voo + 0.3 V
Output voltage, Vo
-0.5 to Voo + 0.3 V
-40 to +85°C
Operating temperature, TOPT
Storage temperature, TSTG
limits
Parameter
Symbol
Min
Input high
voltage
VIH
-65 to +150°C
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Capacitance
TA = 25°C
Limits
Parameter
TA = -40 to +85°C, Voo = 5 V ±10%
Symbol
Typ
Max
Unit
Output
capacitance
Co
4
8
pF
Input
capacitance
CI
8
15
pF
I/O capacitance
CIO
10
18
pF
Test
Conditions
fc =1.0 MHz
unmeasured
pins returned
to 0 V
Typ
Test
Conditions
Max
Unit
3.3
Voo+
0.3
V
ClK input pin
2.2
Voo+
0.3
V
Other inputs
0.8
V
Input low
voltage
VIL
-0.5
Output high
voltage
VOH
0.7 Voo
Output low
voltage
VOL
Input leakage
current
V
IOH = -400 IJA
0.4
V
IOL = 2.5 mA;
4.5 mA (TC)
III
±10
IJA
oV~ VI ~ Voo
Output leakage
current
ILO
±10
IJA
oV~Vo ~ Voo
Supply current
(dynamic)
1001
15
30
mA
Supply current
(stable)
1002
10
IJA
Supply current
(static)
1002
10
IJA
Inputs stable
outputs open
DJ
5
NEe
pPD71071
AC Characteristics
TA = -40 to +85°C, Voo = 5 V ±10%
Parameter
Symbol
Min
Max
Unit
tCYK
100
ns
tKKH
39
ns
tKKL
49
Test Conditions
DMA Mode
Clock cycle
Clock pulse width high
Clock pulse width low
ns
tKR
10
ns
1.5 V -3.0V
Clock fall time
tKF
10
ns
3.0V -1.5V
Input rise time
tlR
20
ns
Input fall time
tlF
12
ns
Output rise time
tOR
20
ns
Output fall time
tOF
12
DMARQ setup time to ClK high
tSOQ
20
HlDRQ high delay from ClK low
tOHQH
5
HlDRQ low delay from ClK low
tOHQL
5
HlDRQ low level period
tHQHQL
2tCYK - 50
Clock rise time
ns
ns
S1, SO, S3, SW, S4w
70
ns
S1. S4w
70
ns
S1. SO, S4w
ns
S4w
HlDAK high setup time to ClK low
tSHA
20
ns
SO,S4,S4w
AEN high delay from ClK low
tOAEH
5
70
ns
S1, S2
AEN low delay time from ClK low
tOAEL
5
70
ns
S1, S4w
ASTB high delay time from ClK low
tOSTH
5
70
ns
S1
ASTB low delay time from ClK high
tOSTL
70
ns
S1
ASTB high level period
tSTSTH
ADR/UBE/RD/WR active delay from
ClK low (Note 1)
tOA
ADR/UBE/RD/WR float time
from ClK low
tFA
ADR setup time to ASTB low
tSAST
tKKL - 40
ns
ADR hold time to ASTB low
tHSTA
tKKH - 20
ns
6
ns
tKKL -15
5
80
ns
S1, S2
70
ns
S1, S4w
NEe
pPD71071
AC Characteristics (cont)
Parameter
Symbol
Min
Max
Unit
Test Conditions
ns
S1, S2
DMA Mode (cont)
ADR/UBE off delay time from ClK low
70
tOAF
RD low delay time from ADR float
tOAR
Input data delay time from MRD low
tOMRIO
-10
ns
2tCYK - 80
Input data hold time from MRD high
tHMRID
Output data delay time from ClK low
toaD
10
Output data hold time from ClK high
tHaD
10
80
ns
S12
ns
S14
ns
S22
ns
S24
Output data hold time from MWR high
tHMWOO
RD low delay time from ClK high
tOKHR
RD low level period
tRRL 1
2tCYK - 30
ns
Normal timing
tRRL2
tCYK + tKKH - 30
ns
Compressed timing
ns
S4
ns
tKKL - 35
ns
RD high delay time from ClK low
tORH
10
ADR delay time from RD high
tORA
tCYK - 30
70
S2 compressed timing
ns
WR low delay time from ClK low
tOWL1
5
50
ns
S3 normal write
WR low delay time from ClK low
tOWL2
5
50
ns
S2 extended write, normal timing
WR low delay time from ClK high
tOWL3
5
50
ns
S2 extended write, compressed timing
tWWL1
tCYK - 30
ns
Normal write
tWWL2
2tCYK - 30
ns
Extended write, normal timing
ns
Extended write, compressed timing
WR low level period
tWWL3
tCYK + tKKH - 30
WR high delay from ClK low
tOWH
5
50
ns
S4
RD low delay time from ClK low
tOKLR
5
50
ns
S2 normal timing
RD, WR low delay from DMAAK active
tOOARW
0
ns
S1, S2
RD high delay time from WR high
tOWHRH
5
ns
DMAAK delay time from ClK high
tOKHOA
5
70
ns
DMAAK delay time from ClK low
tOKLOA
10
90
ns
S1 cascade mode
DMAAK inactive delay time from
ClK high
tOOAl1
5
ns
S4
BI
S11/0 memory timing
7
NEe
pPD71071
AC Characteristics (cont)
Parameter
Symbol
Min
tOOAI2
5
Max
Unit
Test Conditions
tKKl + 70
ns
S4 cascade mode, HlDAK low HlDAK low in S4
4tKKl + 70
ns
S4 cascade mode, HlDAK low except in S4
DMA Mode (cont)
DMAAK inactive delay time from
tOOAI3
DMAAK active level period
tOAOA
TC low delay time from ClK high
tnTcl
TC off delay time from ClK high
tOTCF
TC high delay time from ClK high
tOTCH
TC low level period
tTCTCl
tCYK -15
ns
END low setup time to ClK high
tSED
20
ns
END low level period
tEoEOL
50
ns
READY setup time to ClK high
tSRY
20
ns
S3, SW
READY hold time from ClK high
tHRY
10
ns
S3, SW
5
tKKH
ns
Cascade mode
70
ns
S3
30
ns
S4
ns
oto 2.2 V (Note 2)
+ tCYK -10
S2
Programming Mode and RESET
tlWIWL
80
ns
CS low setup time to IOWR high
IOWR low level period
tSCSIW
80
ns
CS hold time from IOWR high
tHIWCS
0
ns
ADR/UBE setup time to IOWR high
tSAIW
80
ns
ADR/UBE hold time from IOWR high
tHIWA
0
ns
Input data setup time to IOWR high
tSlDlW
80
ns
Input data hold time from IOWR high
tHIWID
0
ns
lORD low level period
tlRIRl
120
ns
ADR/CS setup time to lORD low
tSAIR
20
ns
ADR/CS hold time from lORD high
tHIRA
0
Output data delay time from lORD low
tDiROO
10
Output data float time from lORD high
tFIROO
RESET high level period
tRESET
2tCYK
ns
VOO setup time to RESET low
tsvoo
500
ns
IOWRIIORD wait time from RESET low
tSYIWR
2tCYK
ns
tRVIWR
160
ns
IOWRIIORD recovery time
Notes:
(1) RD/WR refers to i'O'R5 or MRD and IOWR or MWR, respectively.
(2) For END/TC, output load capacitance = 75 pF maximum. To
meet the tDTCH parameter use a 2.2-kO pull-up resistor with a
load capacitance of 75 pF. For other than END/TC, output load
capacitance = 100 pF maximum.
8
ns
100
ns
80
ns
RESET low to first read/write
NEe
pPD71071
Input/Output Edge Timing
Ti m i ng Waveforms
Timing Measurement Points
2.4 V J 2 . 2
v___
T~st
1ttiF
_____ 2.2
tnput
vC
0.8 V- - Pomts - - 0.8 V
0.4 V
83-003764A
Output
OF
1[t
r
r
49·000786A
Clock Timing
elK
49·000784A
9
:::::
-.L
o
ClK
OMARQ
(Active High)
Ji.J~~jif\00~J\00~JN f\~r\~
I"OQ~L
d. -
1-'''0'
-
CD
til
...
CD'
~
S'
CQ
tOAEH-
ASTB
1=
C
:;t
HlOAK
AEN
CD
QI
~
--------
I--tSHA
3
~
0
{",o,
HlORQ
I - tOSTL
I-- tOAEL
-
++---+----+--+--+--+--+---+-+-ol
,,1-..;..1
I
~---
__________________~V I
~--~--~~~~~--~~~--------
_ _ _ _ _ _--rV
'::l-A
...
3'
3: ;'
0
...
CD
..3
0
'1:::
."
D
....
--0
....
---
-..
en
n
0
:::I
tSASTf--:.....
tOAI- ~ tHSTA
Ir,.-A23-As --------------------------------~
I~----+-----~~---+--+-~~----~-+--+--------------I'- r--(A1S-AS107-00 if 8·bit data base)
I-!OA
A7-AO
(A23-A 16. A7-Ao if 8·bit data base)
-
I-- tFA
~-~~--~--~-+--~
c-t~AF
V+--~----+_----+__+--~
iJiiE
OMAAK
(Active Low)
' ' 'r \-
""'y ':1\ -r"QA
- H''''
+
____________+-'1-----<-- ""'--u
\ -".U-~----Ir-----_
tOOARWI-"ItOAR-+\
READ
-
WRiTE
-
I-tOKLR
tOWL1-!
-
I - tORH
tOOARW-
I-
-tORH
f-.
tOKHR
f-.
tOW~3
1
I--tOWHRH
-tORA-:-
I--
t
H I-tOWH
OWH'RH
\l-tOWL~~-+jr1"----
tOWL:~
-
~
tWWL1
I-tWWL2
Normal Timing
tOWH
1["________
....
tWWL1
-twWL3
Compressed Timing
83-0037S1C
~
~
NEe
pPD71071
Timing Waveforms (conI)
Memory-to-Memory Transfer Timing
elK
AEN
ASTB
ADRJDB - - - - . . . . . ( ]
IFA
~~~----.....(] __
~
~+-
_______
~+-_-J
MRi5-------'"
1 eW~L1
IOWH
MWR-----J/~-------------------~\~-_-_-_~_~~ 'H.WO:__________
IOWL2
fi
IWWL2
83-003752C
Ready Timing
READY
83-0037538
11
NEe
pPD71071
Timing Waveforms (cont)
Programming Mode and RESET Timing
VDD
tSCSIW
I
---'
tSVDD
tlWIWl
RESET
I
tRESET
tSYIWR
tSAIW
1--""'::':'';:'';':'''--11-+1 tHIWA
\
iOWA
or iORi5
ADR/UBE
tRVIWR
tSIDW
DB
CS
IOWR
ADR
lORD
DB----------------~
83-0037546
ENDITC Timing
ClK
TC --------------------------~----------~
SED
-lt
~----~·\~'Sih~7~·~-------------------------83-0037558
1?
NEe
pPD71071
Timing Waveforms (cont)
Bus Wait Timing
ClK
HlDAK
t-----tHQHOL---+j
HlDRQ
tOAEL
AEN
DB/ADR - - - - - - - - - - - - - - - - - - " " ' "
RD/WR - - - - - - - - - - - - - - - - - - - "
83-003756B
Cascade Timing
so
S1
S2
S3
S4
S4
S4
SI
ClK
DMARQ------~----------------------~----~~
(Active
High)
tDHOL
HlDRQ
HlDAK
tODAI2
tDKLDA
1_------tDDAI3------+!
DMAAK
(Active
High) _ _ _ _ _.1
~-----------tDADA----------~
83-003757B
NEe
J,iPD71 071
Functional Description
DMA Operation
The pPD71071 functions in three cycles: idle, DMA,
and standby. In an idle or standby cycle, the CPU uses
the bus, while in a DMA cycle, the pPD71071 uses it.
Idle Cycle. In an idle cycle, there are no DMA cycles
active, but there may be one or more active DMA
requests; however, the CPU has not released the bus.
The pPD71 071 will sample the four DMARQ input pins
at every clock. If one or more inputs are active, the
corresponding DMA request bits (RQ) are set in the
status register and the pPD71071 sends a bus hold
request to the CPU. The pPD71071 continues to
sample DMA requests until it obtains the bus.
Table 1 shows the relationship of the data bus width,
Ao, UBE, and the internal registers.
Table 1.
Data Bus Width
Bus Width
AO
8 bits
x
16 bits
UBE Internal Read/Write Registers
X D7-DO - - 8-bit internal register
1
D7-DO - - 8-bit internal register
--------.-------------
o --_._.--------------------------------------_
D1S-Ds - - 8-bit internal register
.. -_ .. _-------._------._.
D1S-Do +---'>- 16-bit internal register
Figure 1.
DMA Operation Flow
After the CPU returns a HLDAK signal and the
pPD71071 obtains the bus, the pPD71 071 stops DMA
sampling and selects the DMA channel with the highest
priority from the valid DMA request signals. Programming of the pPD71 071 is done when the pPD71 071 is in
the idle cycle or the standby mode.
Idle Cycle
DMA Cycle. In a DMA cycle, thepPD71071 controls the
bus and performs DMA transfer operations based on
programmed information. Figure 1 outlines the sequentialflow of a DMA operation.
• •••• (3)
Standby Mode. The pPD71071 can also be used in
standby mode. It is in standby mode and consumes the
static supply current (IDD2) when the clock is turned off
and no I/O read or write operations are being performed. All internal registers will retain their contents.
• •••• (4)
ThepPD71071 can be programmed (using IOWR) and
read (using lORD) with the clock off. The pPD71071
only uses the clock for the DMA data transfer cycles.
The clock may be turned off without altering the
internal registers when the pPD71071 is in the idle
cycle. If the clock is turned off during a DMA transfer,
the pPD71071 will not operate correctly. When the
clock is off, the DMARQ inputs will not be recognized.
The DMARQ inputs could be externally logically ORed
and cause an interrupt to the CPU. The CPU could then
turn on the clock, thus activating the pPD71 071. If the
previously programmed mode of operation is still valid,
the pPD71 071 does not have to be reprogrammed.
Data Bus Width
I n order to allow an easy interface with an 8- or 16-bit
CPU, the data bus width of the pPD71071 is user
programmable for 8 or 16 bits. A 16-bit data bus allows
16-bit memory-to-memory DMA transfers and also
provides a one-I/O bus cycle access to the 16-bit
internal registers.
••••• (5)
DMA Cycle
• •••• (6)
••••• (7) }
Idle Cycle
~----r---"'"
49-0005208
NEe
pPD71071
Terminal Count
The JlPD71 071 ends DMA service when it generates a
terminal count (TC) or when the END input becomes
active. A terminal count is produced when a borrow is
generated by the current count register and a low-level
pulse is output to the TC pin. Figure 2 shows that the
current count register is tested after each DMA
operation.
If autoinitialize is not set when DMA service ends, the
mask register bit applicable to the channel where
service ended is set, and the DMARQ input of that
channel is masked.
DMA Transfer Type
The type of transfer the JlPD71 071 performs depends
on the following conditions.
•
•
•
•
Memory-to-memory transfer enable
Direction of memory-to-I/O transfer (each channel)
Transfer mode (each channel)
Bus mode
Memory-to-Memory Transfer Enable. The JlPD71071
can perform memory-to-I/O transfers (one transfer
cycle in one bus cycle) and memory-to-memory transfers (one transfer in two bus cycles). To select
memory-to-memory transfer, set bit 0 of the device
control register to 1. The DMA channels used in
memory-to-memory transfers are fixed, with chan nel 0
as the source channel and channel 1 as the destination
channel. Channels 2 and 3 cannot be used in memoryto-memory transfers. The contents of the count
registers and word/byte transfer modes of channels 0
and 1 should be the same when performing memoryto-memory transfer.
Figure 2.
Generation of Terminal Count (TC)
For memory-to-memory byte transfer in 16-bit data
bus mode, a read data from upper data bus is to be
written to upper data bus, while a read data from lower
data bus is to be written to lower data bus. Therefore,
start addresses for source and destination must be the
even-even or odd-odd. For word transfer, only eveneven addresses are to be set forsource and destination.
(See Byte/Word Transfer paragraphs below.) When
DMARQO (channel 0) becomes active, the transfer is
initiated.
During memory-to-memory bus cycles in the 16-bit
mode, data read from the DMAC's upper (lower) data
bus is written to the upper (lower) data bus of the
destination device. Thus, for word transfers, only even
source and destination addresses should be used.
The DMA request input pin or a software DMA request
to channel 0 may initiate memory-to-memory transfers.
The JlPD71 071 performs the following operations until
a channel 1 terminal count or END input is present:
• During the first bus cycle, the memory data pointed
to by the current address register of channel 0 is
read into the temporary register of the JlPD71071
and the address and count of channel 0 are updated.
• During the second bus cycle, the temporary register
data is written to the memory location shown by the
current address register of channel 1, and the
address and count of channel 1 are updated.
Note: If DMARQ1 (channel 1) becomes active, the t.tPD71 071
will perform memory-to-I/O transfer even though memory-tomemory transfer is selected. Since this may cause erroneous
memory-to-memory transfers; mask out channel 1 (DMARQ1)
by setting bit 1 of the mask register to 1 before starting
memory-to-memory transfers.
During memory-to-memory transfers, the addresses
on the source side (channel 0) can be fixed by setting
bit 1 of the device control register to 1. I n this manner, a
Figure 3.
Memory-to-Memory Transfer in 16-Bit Data
Bus Mode
83-003758A
15
NEe
pPD71071
range of memory can be initialized with the same value
since the contents of the source address never change.
During memory-to-memory transfer, the DMAAK signal
and channel O's terminal count (TC) pulse are not
output. (See figure 3.)
Direction of Memory-to-I/O Transfers. All DMA transfers use memory as a reference pOint. Therefore, a
DMA read reads a memory location and writes to an 1/0
port. A DMA write reads an 1/0 port and writes the data
to a memory location. In memory-to-I/O transfer, use
the mode control register to set one of the transfer
directions in table 2 for each channel and activate the
appropriate control signals.
Table 2.
Bus Modes
Bus Release Mode
Right to Use
Bus
Service
Channel
n n n r--
CPU - - - ,
fLPD71071
W
CHO
W
W W
CH1
CH2 CH3
Bus Hold Mode
Activated Signals
lID (DMA read)
10WR, MRD
memory (DMA write)
lORD, MWR
Memory -
Figure 4.
Transfer Direction
Transfer Direction
110 -
Figure 4 shows that in bus release mode, only one
channel can receive service after obtaining the bus.
When DMA service ends (end of transfer conditions
depend on thetransfer mode), the channel returns the
bus to the CPU (regardless of the state of other DMA
requests) and the pPD71071 enters the idle cycle.
When thepPD71071 regains use of the bus, a new DMA
operation begins.
Right to Use
Bus
~
Service
Channel
CHO: CH I :CH2; CH3
49·000522A
Verify
(Outputs addresses only. Does not
perform a transfer.)
Transfer Modes. In memory-to-I/O transfer, the mode
control register selects the single, demand, or block
mode of DMA transfer for each channel. The conditions
for the termination of each transfer characterize each
transfer mode. Memory-to-memory transfers have no
relationship to single, demand, or block mode. Memory-tomemory transfers are a separate and distinct type of
transfer'mode. Table 3 shows the various transfer
modes and termination conditions.
Table 3.
Transfer Termination
Transfer Mode
End of Transfer Conditions
Single
After each bytelword
Demand
END input
Generation of terminal count
When DMA request of the channel in service
becomes inactive
When DMA request of a channel in higher priority
becomes active (bus hold mode)
Block
END input
Generation of terminal count
Memory-tomemory
END input
Generation of terminal count
In bus hold mode, several channels can receive service
without releasing the bus after obtaining it. If there is
another valid DMA request when a channel's DMA
service is finished, the new DMA service can begin
after the previous service without returning the bus to
the CPU. End of transfer conditions depend on the
transfer mode. A channel cannot terminate (end count)
atransfer mode and immediately start on its next set of
transfers. There must be anotherDMA channel service
interleaved or the pPD71 071 will put in an idle cycle.
The following shows an example of the possible sequences for Channel 2.
CHAN2 or,
CHAN2 -
CHANn (n
idle -
= 0,1,3) -
CHAN2
CHAN2
The operation of single, demand, and block mode
transfers depends on whether the pPD71 071 is in bus
release or bus hold mode. In bus release mode, only
one type of bus mode (single, demand, or block) is
used each time the pPD71071 has the bus. In bus hold
mode, multiple types of transfers are possible. Channel
o might operate in the demand mode, and channel 1,
which could get the bus immediately after channel 0,
could operate in block mode.
Single Mode Transfer
Bus Modes. The device control register selects either
the bus release or bus hold mode. The bus mode
determines when thepPD71 071 returns the system bus
to the CPU. The pPD71071 can be in either the release
or hold modes for the single, demand, or block mode
transfers. Therefore, there are six possible mode
combinations.
16
In bus release mode, when a channel completes the
transfer of a single byte or word, the pPD71 071 enters
the idle cycle regardless of the state of the DMA
request inputs. In this manner, other devices will be
able to access the bus on alternate bus cycles.
NEe
In bus hold mode, when a channel completes the
transfer of a single byte or word, the jJPD71071
terminates the channel's service even if it is still
asserting a DMA request signal. The jJPD71071 will
then service the highest priority channel requesting
the bus. If there are no requests from any other
channel, thejJPD71 071 releases the bus and enters the
idle cycle.
Demand Mode Transfer
In bus release mode, the currently active channel
continues its data transfer as long as the DMA request
of that channel is active, even though other DMA
channels are issuing higher priority requests. When
the DMA request of the serviced channel becomes
inactive, the jJPD71 071 releases the bus and enters the
idle state, even if the DMA request lines of other
channels are active.
In bus hold mode, when the active channel completes
a single transfer, the jJPD71071 checks DMA request
lines (other request lines when END or TC, all request
lines including the last serviced channel when there is
no END or TC). If there are active requests, the
jJPD71071 starts servicing the highest priority channel
requesting service. Ifthere is no request, the jJPD71 071
releases the bus and enters the idle state.
pPD71071
Table 4.
Address and Count Registers .
Register
Byte Transfer
Word Transfer
Address
±1
±2
Count
-1
-1
During word transfers, two bytes starting at an even
address are handled as one word. If word transfer is
selected and the initial value of the set address is odd,
thejJPD71071 will always decrement that address by 1,
thus making the address even for the data transfer. For
this reason, it is best to select even addresses when
transferring words, to avoid destroying data. Ao and
USE control byte and word transfers.
Table 5 shows the relationship between the data bus
width, Ao and USE signals, and data bus status.
Table 5.
Data Bus Status
Data Bus Width
Ao
UBE
Data Bus Status
8 bits
X
1 (1)
D7-DO valid byte
16 bits
0
1
---- -
0
D7-DO valid byte
------ -------------
D15-Da valid byte
D15-DO valid word
Note:
(1) Always 1 for an 8-bit bus.
Block Mode Transfer
Compressed Timing
In bus release mode, the current channel continues
data transfer until a terminal count or the external END
signal becomes active. During this time, the jJPD71 071
ignores all other DMA requests. After completion of
the block transfer, the jJPD71 071 releases the bus and
enters the idle cycle even if DMA requests from other
channels are active.
In transfers between I/O and memory, a DMA transfer
cycle is normally executed in four clocks. However,
when the device control register selects compressed
timing, one DMA cycle can be executed in a three-clock
bus cycle. Compressed timing may be used in the
release or hold modes when doing block transfers
between I/O and memory. In the demand mode, only
use compressed timing in the bus release mode.
Compressed timing mode increases data transfer rates
by 33%.
In bus hold mode, the current channel transfers data
until a terminal count or the external END signal
becomes active. When the service is complete, the
jJPD71071 checks all DMA requests without releasing
the bus. If there is an active request, the jJPD71 071
immediately begins servicing the request. The
jJPD71071 releases the bus after it honors all DMA
requests or a higher priority bus master requests the
bus.
Figure 5 shows the operation flow for the six possible
transfer and bus mode operations in DMA transfer.
Byte/Word Transfer
If the initialize command selects a 16-bit data bus
width, the mode control register can specify DMA
transfer in byte or word units for each channel. Table
4 shows the update of the address and count registers
during byte/word transfer.
The jJPD71071 is able to omit one clock period during
compressed timing by not updating the upper 16 bits
of the latched address. In block mode and demand bus
release mode, addresses are output sequentially and
the upper 16 bits of addresses latched in external
latches need not be updated except after a carry or
borrow from A7 to A8. For this reason, during compressed timing, the 81 state (output of upper 16 bits of an
address for external latching) is omitted in the bus
cycles except during the first bus cycle when the upper
16 bits of an address are changed. Figure 6 shows one
word waveforms for normal and compressed timing.
17
NEe
J,lPD71,071
Figure 5.
Transf~r and
Bus Modes Operations
Bus Mode
Bus Release
Transfer Mode
Single
Demand
Block
18
Bus Hold
NEe
Figure 6.
pPD71071
Normal and Compressed Timing Waveforms
h
When the mode control register is set to autoinitialize a
channel, the IlPD71071 automatically initializes the
address and count registers when END is input or a
terminal count is generated. The contents of the base
address and base count registers are transferred to the
current address and current count registers, respectively. The applicable bit of the mask register is
unaffected. The applicable bit of the mask register is
set for channels not programmed for autoinitialize.
- 1'-11
The autoinitialize function is useful for the following
types of transfers.
51 52 5354 51 52 53 54 51 52 53 54 51 52
Normal TIming
A5TB
DB
(Upper 16 bits
of Address)
A7- A O
-
DB
(Upper 16 bits
of Address)
A7- A O
h
..... - r-
h
It-
h
I-- rr- f~ I-Ir- '"'"""
~
rrfr)-"'I'- ~
I'- ~
~I--
~
~
Ir-
-
~
51 52 5354 5253 54 52 53 54 5253 54 52
Compressed TIming
A5TB
Autoinitialize
-
Ir-I\
49·000524A
Software DMA Requests
The IlPD71071 can accept software DMA requests in
addition to DMA requests from the four DMARQ pins.
Setting the appropriate bit in the request register
generates a software DMA request. The mask register
does not mask software DMA requests. Software DMA
requests operate differently depending on which bus
or transfer mode is used.
Bus Mode. When bus release mode is set, the highest
priority channel among software DMA requests and
OMARQ pins is serviced, and all bits of the request
register are cleared when the service is over. Therefore,
there is a chance that other software DMA requests will
be cancelled.
When bus hold mode is set, only the corresponding bit
of the request register is cleared after a DMA service is
over. Therefore, all software DMA requests will be
serviced in the sequence of their priority level.
Software OMA requests for cascade channels (see
Cascade Connection) must be performed in bus hold
mode. When a cascade channel is serviced, the master
IlPD71071 operational mode is changed to bus release
mode temporarily and all bits of the request register
are cleared when the cascade channel service is over.
To avoid this, it is necessary to mask any cascade
channels before issuing a software DMA request. After
confirming that all DMA software services are complete
and all bits of the request register are cleared, the
cascade channel masks can be cleared.
Transfer Mode. When single or demand mode is set,
the applicable request bits are cleared and software
OMA service ends with the transfer of one byte/word.
When block mode or memory-to-memory modes are
set, service continues until END is input or a terminal
count is generated. Applicable request bits are cleared
when service ends.
Repetitive Input/Output· of Memory Area. Figure 7
shows an example of DMA transfer between a CRT
controller and memory. After setting the value in the
base and current registers, autoinitialize allows repetitive DMA transfer between the CRT controller and
the video memory area without CPU involvement.
Continuous Transfer of Several Memory Areas. The
CPU can indirectly write to the address or count
registers by writing to the base registers. New values
can be written to the base registers. In the autoinitialize
mode, the value in the base register will be transferred
to the address/count registers when termination is
reached in the address/count registers. Because of ~
this, the autoinitialize function can perform continuous ~
transfer of several contiguous or noncontiguous memory areas during single or demand bus release modes
in the following manner.
During the transfer of data in area 1 (the first area being
transferred), the CPU can write address and count
information about area 2 (the second area to be
transferred). Generation of a terminal count for area 1
results in the transfer of information of area 2 to the
address and count registers. This will cause area 2 to
be transferred. Figure 8 illustrates this procedure.
Channel Priority
Each of the IlPD71 071 's four channels has its own
priority. When there are DMA requests from several
channels simultaneously, the channel with the highest
priority will be serviced. The device control register
selects one of two channel priority methods: fixed and
rotational priority. In fixed priority, the priority (starting
with the highest) is channel 0, 1,2, and 3, respectively.
I n rotational priority, priority order is rotated so that
the channel that has just been given service receives
the lowest priority and the next highest channel
number is given the highest priority. This method
prevents exclusive servicing of some channel(s).
Figure 9 shows the two priority order methods.
1Q
NEe
JlPD71071
Figure 7.
Autoinitialize Application 1
Memory
CRT
:~~~::SS_{~"~~77TrTr.r.n~77~IIL--------------------~\
CRTC
flP071 071
Base Count
Set Values
OMA
Controller
r-----~ OMAAK
.----1
OMARQ
flP071 071
49-0005258
Figure 8.
Autoinitialize Application 2
1/0
Memory
CPU
I
Write Area 1
Information
Base Current
Registers
I
Areal
Transfer
Auto- initialize
Generated
Write Area 2
Information in
Base Register
•
Area 2
Transfer
I
49-0005268
Figure 9.
Priority Order
Fixed Priority
Highest
Rotational Priority
Highest
Highest
CHl Service
£
u
Lowest _
49-0005278
NEe
pPD71071
Cascade Connection
Bus Wait Operation
The pPD71 071 can be cascaded to expand the system
DMA channel capacity. To connect a pPD71071 for
cascading (figure 10), perform the following operations.
In systems using a pPD70208/70216 (V40/V50) as the
CPU, the refresh control unit in the CPU changes the
HLDAK signal to inactive (even during a DMA cycle)
and uses the bus. Here, the pPD71 071 automatically
performs a bus wait operation. This system has a bus
master (V40/V50) whose priority level is higher than
that of the pPD71071.
(1) Connect pins HLDRQ and HLDAK of the secondstage (slave) pPD71071 to pins OMARQ and DMAAK
of any chan nel of the fi rst-stage (master)
pPD71071.
(2) To select the cascade mode of a particular channel
of a master pPD71 071, set bits 7 and 6 of that
channel's mode control register to 11.
When a channel is set to the cascade mode in a master
pPD71071, DMARQ, DMAAK, HLDRQ, HLDAK, and
RESET are the only valid signals in the master
pPD71 071. The other signals are disabled. The master
cascade channel only intermediates hold request/hold
acknowledge between the slave and CPU.
The master pPD71071 always operates in the bus
release mode when a cascade channel is in service
(even when the bus hold mode is set). Other DMA
requests are ignored while a cascade channel is in
service. When the slave pPD71071 ends DMA service
and moves into an idle cycle, the master also moves to
an idle cycle and releases the bus. At this time, all bits
of the master's request register are cleared. The master
operates its non-cascaded channels normally.
Figure 10.
The pPD71 071 executes the bus wait operation when
the HLDAK signal becomes inactive in an operating
mode where transfer is executed continuously in block
mode, during demand bus release mode, or during
memory-to-memory transfer.
When HLDAK becomes inactive during service in other
operating modes, the operation returns to the idle
cycle and transfers control of the bus to the higher bus
master.
Figure 11 shows that when the HLDAK signal becomes
inactive during a continuous transfer, the pPD71 071 is
set up in an S4w state (bus wait). Operation moves to
the idle cycle if DMARQ is inactive in the demand
mode. The HLDRQ signal is made inactive for a period
of about two clocks and the bus is released. The S4w
state is repeated until the HLDAK signal again becomes
active and the interrupted service is immediately _ _
restarted.
~
Cascade Connection Example
HLDAK
HLDAK
HLDRQ
HLDRQ
_DMA1
-
DMA2
_DMA3
Cascaded
Channel
CPU
(,"AAX
DMARQ
HLDAK
~
HLDRQ
-
-
--
fJ.PD71071
(Master)
DMA4
DMA5
DMA6
DMA7
fJ.PD71 071
(Slave)
49·0005288
21
NEe
pPD71071
Figure 11.
Bus Wait Operation
Bus Master
CPU
OMARQ
HLOAK
flP071 071
.I
Higher Priority
Bus Master
",P071071
CPU
--1
--1
\""'__-11
HLORQ
49·QO0529A
Programming the pPD71071
Initialize
To prepare a channel for DMA transfer, you must select
the following characteristics.
Use the initialize command as a software initialize to
the pPD71 071 or to set the width of the data bus. When
usi ng a 16-bit CPU, set the data bus width to 16 bits
first. Figure 12 shows the initialize command format.
•
•
•
•
•
Starting address for the transfer
Number of byte/word transfers
DMA operating modes
Data bus widths
Active levels of the DMARQ and DMAAK signals
When reading from or writing to a pPD71 071 internal
register, address lines A3-AO select the register: lORD
or IOWR select the data transfer direction, and CS
enables the transfer. Table 6 shows the register and
command configurations.
Table 6.
Register Configuration
Bit O. When the RES bit is set, the internal state of the
pPD71071 is initialized and will be the same as when a
hardware reset is used (except for data bus width
selection). A software reset leaves bit 168 intact
whereas a hardware reset selects the 8-bit data bus.
After initialization, the registers are as in table 8 and the
RES bit is cleared automatically.
Table 8.
Register Initialization
Register
Initialization Operation
Initialize
Clears bit 0 only
No change
Register
Bit size
Channel
5
Address
Base address
24 (4)
Count
No change
Current address
24 (4)
Channel
Selects channel 0, current and base
Base count
16 (4)
Mode control
Clears all bits
16 (4)
Device control
Clears all bits
7 (4)
Status
Clears bits 3-0 only
Device control
10
Request
Clears all bits
Status
8
Mask
Sets all bits (masks all channels)
Request
4
Temporary
Clears all bits
Mask
4
Temporary
16
Current count
Mode control
Note:
When using a 16-bit CPU and selecting a 16-bit data bus, the word
IN/OUT instruction can be used to read/write information two bytes
at a time. However, commands in table 7 suffixed with 8 must be
issued with the byte IN/OUT instruction.
22
Bit 1. The 168 bit determines the data bus width. When
using the pPD71071 in a 16-bit system, set this bit
immediately after a hardware reset since a hardware
reset always initializes it to the 8-bit data bus mode.
NEe
Table 7.
pPD71071
Command Configuration
Address
OH
R/W
Command Name
Format
MSB
W(B)
Initialize
-
I
-
-
R(B)
Channel Register
Read
-
I -
-
W(B)
Channel Register
Write
-
-
-
LSB
I - I
-
BASE SEL3
-
I 16B I RES I
SEL2
SEL11 SELO
I
SE~CH
I
1H
2H
R/W
3H
R/W
Count Register
Read/Write
-
C7
C6
C5
C15
C14
C13
I A7
I A15
I
-
BAS
C4
C3
C2
C1
I CO I
C12
C11
C10
C9
I
I
I
C8
I
AO
I
4H
R/W
5H
R/W
6H
R/W(B)
8H
R/W
9H
R/W
OAH
R/W(B)
Mode Control
Reg. Read/Write
I
OBH
R(B)
Status Register
Read
I RQ3
OCH
R
Temporary Reg.
(lower) Read
I
R
Temporary Reg.
(higher) Read
I T15
T14
OEH
R/W(B)
Request Reg.
Read/Write
I
-
-
-
I
-
I SRQ31 SRQ21 SRQ1 I SRQO
OFH
R/W(B)
Mask Reg.
Read/Write
I
-
-
-
I
-
I
ODH
Address Register
Read/Write
Device Control
Reg. Read/Write
A6
A5
A4
A3
A2
A14
A13
A12
A11
A10
I
A1
A18
I A171
A9
A8
I
I
I A23
I AKL
A22
A21
A20
A19
RQL
EXW
ROT
CMP I DDMAI AHLD I MTM I
-
-
-
I
TMODE
T7
-
-
RQ1
T6
T5
I RQO I
I
T13 I
T4
I
ml
-
TDIR
ADIR I AUTI I
RQ2
I
Te3
A16
I WEV IBHLD I
I
-
I WID I
I TC2 I TC1 I TCO I
I
T1
I
TO
I
T11 I T10 I
T9
I
T8
I
T3 I
M3 I
T2
M2 I
M1
I
MO
I
I
49-tlOO603B
Figure 12.
Initialize Command Format
OH
I - I -I - 1 - 1 - 1 - 1 16B LRES
L
OUT (Byte only)
Software
Reset
'--------- 16-bil
data bus
0
1
No operation
Reset
0
8-bit data bus
1
16-bit data bus
49-000604B
Channel Register
This command reads and writes the channel register
that selects one offour DMA channels for programming
the address, count, and mode control registers.
Figure 13 shows the channel reg ister read/write format.
Channel Register Read
SEL3-SELO. These mutually exclusive bits show which
of the four channels is currently selected for
programming.
Base = 1. Only the base registers may be read or
written to.
Channel Register Write
SELCH. This bit selects the channel to be programmed.
BASE. Base = O. The current register may be read.
During a write, the base and current registers will be
written to simultaneously.
Base = 1. Only the base registers may be read or
written to.
BASE. Base = O. The current register may be read.
During a write, the base and current registers will be
written to simultaneously.
23
NEe
pPD71071
Figure 13.
Channel Register Format
Channel Register Read
1H
I - J-
I
-
I BASE I SEL3 I SEL.2 I SEL1 I SELO
f IN [Byte only]
I
Selected
Channel
0001
Channel 0
0010
Channel 1
0100
Channel 2
1000
Channel 3
0
Select Current (read),
select both Base and
Current (write)
1
Select Base (read/write)
Base Only
Channel Register Write
1H
I -1 -
I
-
I
-
1 -
IBASEI
OUT (Byte only)
SELCH
'L.
Selected
Channel'
Base Only
00
Channel 0
01
Channel 1
10
Channel 2
11
Channel 3
0
Select Current (read),
select both Base and
Current (write)
1
Select Base (read/write)
49·0006058
Count Register Read/Write
When the 16-bit bus mode is selected, the IN/OUT
instruction can directly transfer 16-bit data. The
channel register selects one of the count registers.
When bit 2 of the channel register write is cleared, a
write to the count register updates both the base and
current count registers with the new data. If bit 2 of the
channel register write is set, a write to the count
register only affects the base count register.
The base count registers hold the initial count value
until a new count is specified. If autoinitialize is
enabled, this value is transferred to the current count
register when an END or TCis generated. For each
DMA transfer, the current count register Is decremented by one. Figure 14 shows the count register
read/write format.
Address Register Read/Write
When a 16-bit data bus width is selected, the IN/OUT
instruction can directly transfer the lower two bytes
(4H and 5H) of the register. You m;ust use the byte
IN/OUT instruction with the upper byte (6H) of the
register. The channel register selects one of the address
registers. When bit2 of·thechannel register is cleared,
a write to the address register updates both the base
and current add ress reg isters with the new data. If bit 2
of the channel register is set, a write to the address
register only affects the base address register.
24
The base register holds the starting address value until
a new setting is made and this value is transferred to
the current address register during autoinitialization.
For each DMAtransfer, the durrent address register is
updated ±2 during word transfer and ±1 during byte
transfer. Figure 15 shows the address register read/
write format.
Device Control Register Read/Write
The device control command reads from and writes to
the device control register. When using a 16-bit data
bus, use the word IN/OUT instruction to read and write
16-bit data. Figure 16 shows the device control register
read/write format.
NEe
Figure 14.
pPD71071
Count Register Read/Write Format
Figure 15.
Address Register Read/Write Format
2H I C7
C6
Cs
C4
C3
C2
Cl
Co
Iiniout
4H I A7
A6
As
A4
A3
A2
Al
Ao
Iiniout
3H I CIS
C14
C13
C12
Cll
Cl0
Cg
Cs
Iiniout
5H I AIS
A14
A13
A12
All
Al0
Ag
As
Iiniout
I
A22
A21
A20
A19
AIS
A17
A16
83-001951A
6H
A23
I
;~y~eU~nIYJ
83-001952A
Figure 16.
Device Control Register Read/Write Format
BH I AKL I RQL I EXW I ROT I CMP IDDMAI AHLD I MTM
L
IN/OUT
Memory-toMemory
O
1
Disable
Fixed
0
1
Disable for CHO
Enable for CHO
Disable DMA
Operation [2J
0
1
Enable
Compressed
Timing [3J
0
1
Rotational
Priority
0
1
Extended
Writing [4J
DMARQ
Active Level
0
1
0
1
DMAAK
Active Level
0
Active Low
1
Active High
0
1
Bus Release
'------ Address [IJ
9H
Enable
(
Disable
Normal
Compressed
Fixed
Rotational
Normal
Extended
Active High
Active Low
1-1-1-1-1-1 - I WEVlBHLDJ IN/OUT
L
Bus Mode
' - - - - - Wait Enable
During
Verify [5]
0
Bus Hold
Disable
1
Enable
Note:
[IJ This bit Is only used when MTM = I, [memory-to-memory translersJ_
[2J Disables HLDRQ to thl! CPU to prevent Incorrect DMA operation while the
pPD71071's registers are being Initialized or modified.
[3] When I, causes the pPD71071 to use compressed timing In the demand bus
release mode or In the block mode.
[4] When EXW Is O,the write signal becomes active [normal wrlteJ during S3 and SW.
When l,the write signal becomes active during S2, S3, and SW.
See figures 27-29.
[5J This bit enables or disables the walt state generated by the READY Signal
during a verify transler.
49-000606C
NEe
pPD71071
Mode Control Register Read/Write
Mask Register Read/Write
This command reads from and writes to the mode
control register to specify the operating mode for each
channel. The channel register selects the mode control
register to be programmed. This command must be
issued by the byte IN/OUT instruction. Figure 17
shows the mode control register read/write format.
This command reads from and writes to the mask
register to mask or unmask external DMA requests for
the corresponding four DMA channels (DMARQ3DMARQO). This command may be issued by the byte
IN/OUT instruction. Figure 21 shows the mask register
read/write format.
Status Register Read
DMA Transfer Modes
This command reads the status register for the individual DMA channels. The register has DMA request
states and terminal count or END information. This
command must be issued by the byte IN instruction.
Figure 18 shows the status register read format.
Figures 22-27 show state transition diagrams for the
different modes of DMA transfer.
Temporary Register Read
Transfer Timing
When a 16-bit data bus is selected, the IN instruction
will read 16-bit data with this command. The last data
transferred in memory-to-memory transfer is stored in
the temporary register. Figure 19 shows the temporary
register read format.
Request Register Read/Write
This command reads from and writes to the request
register to generate DMA requests by software for the
four corresponding DMA channels. This command
may be issued by the byte IN/OUT instruction.
Figure 20 shows the reguest register read/write format.
Figure 17.
Figure 23 shows the state of a master pPD71071 when
an input from a slave pPD71071 (cascaded pPD71 071)
is using the system bus.
Figures 28-30 show pPD71071 timing waveforms.
Examples of System Configuration
Figures 31-32 show system configuration examples
using the 8- bitpPD701 08 CPU and the 16-bitpPD70116
CPU. ThepPD71082 externally latches addresses and
data.
Mode Control Register Read/Write Format
OAH
I
TMODE
I ADIA I AUTI I
TDIA
L~
I - I
W/B
L
Word/byte
Transfer [1]
Transfer
Direction [2]
AutoInitialize [3]
Address
Direction [4]
Transfer
Mode [5]
0
1
00
01
10
11
0
Byte
Word
Verify
I/O-to·memory
Memory.to-I/O
Not allowed
1
0
1
00
Disable
Enable
Increment
Decrement
Demand
01
10
11
Single
Block
Cascade
Note:
[1] This bit selects byte or word transfer for DMA transfers. This bit Is used only
In 16·blt data bus mode.
[2] These bits select the DMA transfer direction between memory and I/O. These bits
are meaningless during memory-to-memory transfer.
[3] Channel 0 and 1 must have the same AUT I bit value when performing
memory-to-memory transfer.
[4] This bit decides the update direction of the Current Address Register. When ADIA Is 0,
the register Increments by 1 for a byte transfer and by 2 for a word transfer. When ADIR Is 1,
the register decrements by 1 for a byte transfer and by 2 for a word transfer.
[5] These bits select the transfer mode during DMA transfer between memory and I/O and are
meaningless during memory-to-memory transfer.
49-0006088
26
NEe
Figure 18.
pPD71071
Status Register Read Format
OBH
I R03 I R02
ROl
I ROo I
TC3
I TC2 I
I
TCl
TCO
I
(Byte only)
IN
Terminal
Count
OMA
Request
[1]
0
Not ended (for each read)
1
END or terminal
count
No OMA request active
0
1
External OMA
request present
Note:
[1) Bits R03-ROO will be set if an external hardware OMA request is pending even if
its request bit is masked. Software·generated OMA requests, hardware reset, and
software reset will not affect these bits.
49·000607B
Figure 19.
Temporary Register Read Format
OCH
I
T7
T6
Ts
T4
T3
T2
Tl
To
lin
OOH
I
T1S
T14
T13
T12
Tl1
Tl0
Tg
Ta
lin
83-001953A
Figure 20.
Request Register Read/Write Format
Note:
[1] In memory-to-memory applications, only bit SROO will be cleared
at terminal count or when an EN 0 input is present.
83-0018878
Figure 21.
Mask Register Read/Write Format
6
OFH
I - I - I - I - I
3
M3
2
I
M2
I
1
0
Ml
L MO I
IN/OUT
11.--__-11 OMARO
I
Mask [1]
(Byte only)
I 0 1 Not masked J
I 1 I Masked
J
Note:
[1] In memory-to-memory applications, only bits MO and Ml will be set
at lerminal count or when an EN 0 input is present.
49-0006098
')7
NEe
pPD71071
Figure 22.
Idle Cycle
SI:
DMA request idle c.ycle
SO:
HLDAK walt state
Sl:
Address latch state
S2:
Read signal output state
S3:
Write signal output state
S4:
Read/Write signal recovery
state
SW:
READY walt state
S4w:
Bus walt state
1 :
Memory-I/O Transfer
2:
Memory-ta-Memory Transfer
3 :
OMARa and HLDAK Inputs present
N
49·0005318
28
NEe
Figure 23.
pPD71071
DMA Cycle, Cascade Mode
Figure 24.
DMA Cycle, Single Mode
49-000532A
49-000533C
')0
pPD71071
Figure 25.
NEe
DMA Cycle,Demand Mode
SI
Note:
[1J Carry or borrow to upper two bytes of address?
49-000534C
NEe
Figure 26.
pPD71071
DMA Cycle, Block Mode
N
N
N
Nole:
[1J Carry or borrow 10 upper Iwo byles of address?
49-000535C
ttlEC
pPD71071
Figure 27.
DMA Cycle, Memory-fo-Memory Transfer
511-514: Channel 0 Operation
521-524: Channel 1 Operation
y
~
o
o
83-001674C
NEe
Figure 28.
,pPD71071
Memory-IIO Transfer, Normal Timing
51
elK
51
50
50
51
52
54
53
51
52
53
51
54
51
J1lJl JlJl Jl Jl ~ Jl JlLn ~ JlL1l IrF
\
OMARQ
HlORQ
HlOAK
L I---
- W
I
'\
AEN
A5TB
n
1\
r-\
r-~
L-J
IL.....-J
A7-AO
OC
OC
OMAAK
LW
I
r-\
,
[2J
'---
L
\
II
\
LV
\
--l..
'Hmlnput
1,--'
[2J
'---
~ V--'
L f-..j
'T<::output
Note:
[IJ When an B-bit data bus is selected, OW08 are not used. Therefore, A23-A16 are
not multiplexed address/data signals and will have the same liming as A7-AO'
[2J The broken lines of the write signal are lor extended write liming;
49-000537C
NEe
pPD71071
Figure 29.
Memory-IIO Transfer, Compressed Timing
51
elK
51
50
so
52
51
53
52
54
HLOAK
54
51
u-
\
-
U
L I--I
II
1\
AEN
A5TB
51
Jl IJl W' ~ W' ~ lJl W"' J' UlW' ~
OMARQ
HLORQ
53
III
Ir--I'\
1\...--1-'
OC
IX
OMAAK
I
\.. W
II
Ir-t\
\
[2[
'---
L
V
~L~
n.
\
1,11\
\.~J .L1,11\
~ENl)lnput
to-
L
H
l''fCOutput
Note:
(1) When an 8-bit data bus is selected, 0 15 -08 are not used_ Therefore, A23-A16 are
not multiplexed address/data signals and will have the same liming as A7-AO_
12) The broken lines of the write signal are for extended write tlmlng_
49-000538C
34
NEe
Figure 30.
pPD71071
Memory-to-Memory Transfer
5tate
SO
511
512
513
514
521
522
523
524
51
Note:
[1) When an 8-blt data bus is selected, 015-08 are not used. Therefore, A23-A16
are not multiplexed address/data signals and will have the same timing as A7-Ao.
[2) The broken lines of the MWR signal are for extended write timing.
49·0005396
Figure 31.
END/TC Input/Output
5tate
51
52
53
54
elK
TC (Output)
END (Input)
83-003760A
35
NEe
pPD71071
Figure 32.
System Configuration with I1PD70108
!,P071082 x 3
A19- A16
~
A19- A 16
)
01
DO
")
01
DO
U
v
A1S-As
A1S-AS
!,P070l0S
A
A07-AOO
ASTB
HLOAK
Kr-
"
~
I---
A7-AO
01.
DO
STB
OE
,
/,>.
L~
Address Bus
A19-AO
A19-AS
07- 0 0
HLORQ
:)
~
HLORQ
HLOAK
"-
n
V·
I
"-
0~
Data Bus
07- 0 0
A7-AO
A7-AO
07- 0 0
A
A1S-AS/07- 0 0
I~
!,P071071
A19-A16
""
A23- A 16
-V
!,P0710S2
>
L
"v
AEN ASTB
I
36
....
v
A1S-AS
01
DO
STB
OE
J
83-001673C
NEe
Figure 33.
pPD71071
System Configuration with pPD70116
pP071082
>
x3
UBE, A19-A16
~
UBE, A19-A16
v
J'..
A
pP070116
A07-AOO
"
<;
-
A1S-AS
~Ol
A01S-AOsl<
DO
~
~Ol
-
HLOAK
-
HLORQ
A7-AO
DO
STB
ASTB f - -
J
DO
01
./>.
OE
t...
A
11
~
01S- 0 0
01S-00 J'..
/";:.V
HLOAK
HLORQ
A7-AO
01S- DO
~
07- 0 0
I~
,,~
01S-0S
pP071071
pP071082
x2
A1S-AS
=>01
A23- A 1s10 1S- DS
UBE
AEN ASTB
I
Data Bus
01S- 0 0
A7-AS
V'
A
A1S-Asl 0 7-00
Address Bus
UBE, A19-AO
A19-AS, UBE
~Ly7
v>
~
1<"
V'
A19-AO, UBE
v
A19-A16
01
DO
STB
OE
t
......
t...
)
DO
I
83-001672C
37
pPD71071
38
NEe
NEe
pPD71082, 71083
8-Bit Latches
NEG Electronics Inc.
Description
Pin Configurations
p.PD71082 and p.PD71083 are CMOS 8-bit transparent
latches with three-state output buffers. They are used as
bus buffers or bus multiplexers in microprocessor systems. Their high-drive capability makes them suitable for
data latch, buffer, or I/O port applications.
20-Pin Plastic DIP
010
Voo
011
000/000
012
001/001
Features
013
002/002
014
o CMOS technology
015
003/003
004/004
o 8-bit parallel data register
017
016
OE
o Three-state output buffer
Vss
005/005
006/006
007/007
STB
o High drive capability output buffer (IOL = 12 rnA)
o p.PD8085A, 8048, 8086, 8088, p.PD70108/116, and
p.PD70208/216 system compatible
83-000225A
2O-Pin Plastic SOP
o p.PD71082 - non-inverted output;
p.PD71083 - inverted output
010
Voo
o Single +5 V ± 10% power supply
011
000/000
o Transparent operation
012
001/001
013
o Industrial temperature range: -40 to +85°C
014
015
002/002
003/003
004/004
Ordering Information
016
005/005
017
006/006
Part Number
Package
Output
,uPD71082C
20-pin plastic DIP
Non-inverted
,uPD71082G
20-pin plastic SOP
,uPD71083C
20-pin plastic DIP
,uPD71083G
20-pin plastic SOP
OE
007/007
STB
Vss
83-004227A
Inverted
Pin Identification
Symbol
Function
Data input, bits 0-7
Data output, bits 0-7; non-inverted (,uPD71082)
or inverted (,uPD71083)
STS
Strobe input
Output enable input
Voo
Vss
50150
+5 V power supply
Ground
NEe
pPP71082, 71083
latch. Data is latched on the falling edge of STS. When
STS is low, the 000-007/000-007 outputs do not
change.
PIN FUNCTIONS
DIQ-DI7 (Data Input)
010-017 are data input lines to the 8-bit data latch. 'Data
on 01 lines passes through the latch while STS is high.
The data is latched to 00/00 with the falling edge of
STS.
DOo-D07/i5oo-D~ (Data Output)
000-007/000-007 are the three-state data output lines
from the a-bit data latch. When OE is high, these lines go
into the high-impedance state. When OE is low, data
from the latch is output, either non-inverted (p.P0710a2)
or inverted (p.P071083).
STB (Strobe)
OE (Output Enable)
OE input is the output enable signal for the three-state
00/00 lines. When OE is high, 00/00 lines are high
impedanc$. When OE is low, data from the a-bit latch is
output to 000-007/000-007. See table 1.
Tabl. 1. I..IItch Operation
STB
OE
000-00.,1000-00.,
8-Blt Oata Latch
Low
Low
Latched data from 8·blt
data latch Is enabled
01 line data has been
latched with failing edge
of STB (hIgh to low)
High
STS is the input strobe signal for the 8-bit latch. When
STS is high, data on the 01 lines passes through the 8-bit
High
High Impedance
Low
Data on 010-017
01 passed through to
High
High Impedance
oollm
Block Diagram
pP071083
pP071082
OE O - - - - - Q '>-----,
STB
STB
,---------I
1
010 0--+~
I
>----'---0 000
1
1
1
010 0--+---1
1
Oh~
4001
f------------- J
012~
~002
012
0 13 ()------i
1----0
01 3
003
0---4
~
,-----------,
0 15 ()-----1
L ____________
01 6
0---4r -
017
0-------1
L
004
~
't----O
003
1",,-
014 ~
,---v 004
,-------------1
~ 005
015 G-------j
~ 006
01
r----o 007
____________ J
002
L-------------"l
I
1---0
1------------ 1 I
-j
- - - - - - ',- - - - ,
i--o
o---i
I-- - - - - - - - - - - -'-l
L-------------1
01 4
L-o 001
011 G-------j
1-------------.J
,------------,
1
1
1- - - - - - - - -----..j
L ____ - - - - - - - - - - 1
60-:_ 0 17 ()------i
L
-
-
-
-
-
-
-
-
-
r
l--o
_____________ J
005
006
007
83-0002266
2
NEe
pPD71082, 71083
Capacitance
FUNCTIONAL DESCRIPTION
The #,PD71082 and #,PD71083 are 8-bit data latches
strobed by the STS signal. They have high-drive capability output buffers controlled by the OE signal. Data on
the 01 lines is latched by the trailing edge of STS (high to
low). When STS is high, data passes through the latch.
When OE is high, DO lines are high impedance. When OE
is low, the contents of the latches are output on 000007. The DO lines are isolated from OE switching noise.
ELECTRICAL SPECI FICATIONS
Absolute Maximum Ratings
TA - 25°C; Vss - OV
-0.5 to +7.0 V
Power supply voltage, Voo
Input voltage, VI
-1.0 to Voo + 1 V
Output voltage, Vo
-0.5 to Voo + 0.5 V
Power diSSipation, POMAX, DIP
SOOmW
Power diSSipation, POMAX, SO
200mW
Operating temperature, Topt
-40 to +85°C
Storage temperature, Tstg
Exposing the device to stresses above those listed In the absolute
maximum ratings could cause permanent damage. Exposure to
absolute maximum ratings for extended periods may affect device
reliability.
DC Characteristics
TA .. -40 to +85°C; Voo - 5V :1:10%
Parameter
Symbol
Min
Input voltage,
high
VIH
2.2
Input voltage,
low
VIL
Output voltage,
high
VOH
Output voltage,
low
VOL
Max Units Conditions
V
VOL = 0.45 V
VOH
Voo
-0.8V
=
0.8
V
VOL = 0.45 V
VOH = Voo
-0.8V
V
10H = -4mA
TA - 25°C; Voo - +5 V
Parameter
Cln
V
1.0
p.A
VI = Voo, VSS
-10
10
p.A
DE =
100
80
p.A
VI
loodyn
20
rnA
fin = 10MHz
C
200pF
10FF
Power supply
current (static)
Power supply
current
(dynamic)
f - 1 MHz
Max
Units
tOIO
5
40
ns
STe to output
delay
toSTBO
10
60
ns
Data float
time from 'OE
high
tFCTO
5
30
ns
Data output
delay from 'OE
low
toCTO
10
40
ns
Input to STe
setup time
tSISTB
0
ns
Input to STe
hold time
tHSTBI
25
ns
STe high
pulse width
tPWSTB
20
ns
Signal rise
time
lLH
20
ns
0.8 to 2.0V
Signal fall
time
tHL
12
ns
2.0 to 0.8V
Symbol
Conditions
Loading circuit (a)
Loading circuit (b)
Loading circuit (a)
II
Loading Circuits for AC Testing
[a] VOL, VOH Outputs
[b] Three-State Output
2.87V
~'''O
10L = 12mA
-1.0
Leakage
current, high
impedance
Conditions
pF
Min
Parameter
Input to
output delay
Loading Conditions: IOl
Input current
Units
12
AC CharacteristiCS
r200PF
0.45
Max
TA - -40 to +85°C; Voo - 5 V :1:10%
Out
Voo -0.8
Min
Symbol
Input capacitance
2.87V
Out
fJ
6750
r200 pF
= 12 mA, IOH = -4 mA, Cl = 200 pF
83-000228A
Voo
= Voo, VSS
=
3
NEe
pPD71082, 71083
Timing waveforms
01
tSISTB
tHSTBI
STB
tPWSTB
tOIO
tOSTBO
00/00
--------(1
83-0042166
Timing IIeasurement Point.
Input
2.4 V
0.4 V
2.2 V
0.8 V
Measurement Points
Output
2.2 V
2.2 V
0.8 V
0.8 V
Measurement Points
2.2 V
0.8 V
83-0042116
4
NEe
II PD71 084
Clock Pulse
Generator/Driver
NEC Electronics Inc.
Description
Pin Configurations
The p,PD71084 is a clock pulse generator/driver for microprocessors including the V20® and V30® and their
peripherals using NEe's high-speed CMOS technology.
18-Pin Plastic DIP
Features
o CMOS technology
CKSYN
PRCLK
REN1
RDY1
READY
o Clock pulse generator/driver for p,PD70108/70116 or
other CMOS or NMOS CPUs and their peripherals
o Frequency source can be crystal or external clock
input
VDD
X1
X2
RDYSYN
EXFS
FIX
asc
CLK
Vss
RESIN
RESET
83-001580A
o Reset signal with Schmitt-trigger circuit for CPU or
peripherals
2O-Pin Plastic SOP
o Bus ready signal with two-bus system
synchronization
o Clock synchronization with other p,PD71084s
o Single +5 V ±10% power supply
o Industrial temperature range: -40 to + 85°C
Ordering Information
Part Number
elK Out, Max
Package
~PD710S4C-S
SMHZ
1S-pin plastic DIP
C-10
10 MHz
G-S
SMHz
Vss
VDO
X1
NC
X2
RDYSYN
EXFS
FIX
asc
RESIN
RESET
83-0041S3A
20-pin plastic SOP
V20 and V30 are registered trademarks of NEC Corporation.
50190
CKSYN
PRCLK
NC
REN1
RDY1
READY
RDY2
REN2
CLK
NEe
pPD71084
Pin Identification
ClK (Processor Clock)
Symbol
Function
CKSYN
Clock synchronization input
PRClK
Peripheral clock output
REN1
Bus ready enable input 1
RDY1
Bus ready input 1
READY
Ready output
RDY2
Bus ready input 2
REN2
Bus ready enable input 2
ClK
Processor clock output
Vss
Ground potential
RESET
Reset output
RESIN
Reset input
asc
Oscillator output
FIX
External frequency source/crystal select
EXFS
External frequency source input
Ready synchronization select input
X2
X1
VDD
NC
Crystal input
Crystal input
. +5 V power supply
No connection
ClK output supplies the CPU and its local bus peripherals. ClK is a 33% duty cycle clock, one-third the frequency of the frequency source. The ClK output is
+0.4 V higher than the other outputs.
PRClK (Peripheral Clock)
PRClK output supplies a 50% duty cycle clock at onehalf the ClK frequency to drive peripheral devices.
OSC (Oscillator)
OSC outputs a Signal at the same frequency as the
crystal input. When EXFS is selected, the OSC output is
powered down, and its output will be high.
CKSYN (Clock Synchronization)
CKSYN input synchronizes one p.PD71084 to other
p.PD71084s. A high level at CKSYN resets the internal
counter, and a low level enables it to count.
RESIN (Reset)
This Schmitt-trigger input generates the RESET output.
It is used as a power-on reset.
PIN FUNCTIONS
RESET (Reset)
X1, X2 (Crystal)
This output is a reset signal for the CPU. Reset timing is
provided by the RESIN input to a Schmitt-trigger input
gate and a flip-flop which will synchronize the reset
timing to the falling edge of ClK. Power-on reset can be
provided by a simple RC circuit on the RESIN input.
When the FIX input is low, a crystal connected to X1 and
X2 will be the frequency source to generate clocks for a
CPU and its peripherals. The crystal frequency should
be three times the frequency of ClK.
EXFS (External Frequency)
EXFS is the external frequency input in the external TTL
frequency source mode (FiX high). A TTL-level clock
signal three times the frequency of the ClK output
should be used for the source.
FiX (Frequency/Crystal Select)
FIX input selects whether an external TTL-level input or
an external crystal input is the frequency source of the
ClK output. When FIX is low, ClK is gene~ated from the
crystal connected to X1 and X2. When FIX is high, ClK
is generated from an external TTL-level frequency input
on the EXFS pin. At the same time, the internal oscillator
circuit will stop and the OSC output will be high.
2
RDY1, RDY2 (Bus Ready)
A peripheral device drives the RDY1 or RDY2 inputs to
signal that the data on the system bus has been received
or is ready to be sent. REN1 and REN2 enable the RDY1
and RDY2 signals.
REN1, REN2 (Address Enable)
REN1 and REN2 inputs qualify their respective RDY
inputs.
RDYSYN (Ready Synchronization Select)
RDYSYN input selects the mode of READY signal synchronization. A low-level signal makes the synchronization a two-step process. Two-step synchronization is
used when RDY1 or RDY2 are not synchronized to the
microprocessor clock and therefore cannot be guaranteed to meet the READY setup time. A high-level signal
makes synchronization a one-step process. One-step
NEe
synchronization is used when RDY1 and RDY2 are syn~
chronized to the processor clock. See Block Diagram.
pPD71084
ity. The values of C1 and C2 (C1 = C2) can be calculated from the load capacitance (C0 specified by the
crystal manufacturer.
READY (Ready)
The READY output signal to the processor is synchronized by the ROY inputs to the processor ClK. READY is
cleared after RDY goes low and the guaranteed hold time
of the processor has been met.
CL =
C1 xC2
+
C
S
C1 + C2
Cs is any stray capacitance in parallel with the crystal,
such as the p.PD71084 input capacitance 01
Figure 1. Crystal Configuration Circuit
CRYSTAL
The oscillator circuit of the p.PD71084 works with a
parallel-resonant, fundamental mode, "AT-cut" crystal
connected to pins X1 and X2.
Figure 1 shows the recommended circuit configuration.
Capacitors C1 and C2 are required for frequency stabil-
.1 C1
~
~C2 T
X1
~PD71084
X2
83VL·7023A
",PD71084 Block Diagram
X1
X2
FIX
OSC
PRClK
EXFS
CKSYN
REN1
ClK
RDY1
REN2
READY
RDY2
RDYSYN
RESIN
RESET
83-0015838
3
NEe
IIPD71084
DC Characteristics
= 5 V :t 10%
ELECTRICAL SPECIFICATIONS
TA = -40 to +85°C; V OD
Absolute Maximum Ratings
Parameter
TA = 25°C; Vss = OV
Power supply voltage, Voo
Min
VIH
2.2
Input voltage, low
VIL
Output voltage,
high
VOH
-0.5 to + 7.0 V
Input voltage, VI
-1.0 V to VDD
Output voltage, Vo
-0.5 V toVDD
+
+
1.0 V
0.5 V
Operating temperature, TOPT
Storage temperature, TSTG
Symbol
Input voltage, high
-65 to
V
V
2.6
+ 150°C
0.8
500mW
Output voltage, low
VOL
Power dissipation, Po (SOP)
200mW
Input leakage
current
liN
RESIN hysteresis
RESIN input
V
V
Voo - 0.4
ClK output,
IOH = -4mA
V
IOH = -4mA
0.45
V
IOL =4mA
-1.0
1.0
p.A
-400
1.0
p.A RDYSYN input
Voo -0.8
Power dissipation, Po (DIP)
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
Max Unit Conditions
V
0.25
Power supply
current (static)
100
200
p.A
Power supply
current (dynamic)
IDDdyn
30
mA fin = 24 MHz
Capacitance
TA = 25°C; Voo = +5V
4
Parameter
Symbol
Input capacitance
Cln
Min
Max Unit Conditions
12
pF
f = 1 MHz
NEe
pPD71084
AC Characteristics
= -40 to +85°C; VDD 5 V ± 10%
TA
Parameter
Symbol
EXFS high
tEHEL
Min
Max Unit Conditions
16
ns At2.2V
Parameter
Symbol
Max
Unit
ClKto RESET
delay
tCLlL
40
ns
ClK to PRClK
t delay
tCLPH
22
ns
22
ns
Min
Conditions
EXFS low
tELEH
16
ns At 0.8V
EXFS period
tELEL
40
ns
35
ns
ClKto PRClK
.!.delay
tCLPL
tRWCL,
tRWCH
-5
22
ns
0
ns
OSC ClKt
delay
tOLCH
RDY1, 2 hold to tCLR1X
ClK.!.
2
35
ns
tRSYVCL
50
ns
OSC ClK.!.
delay
tOLCL
RDYSYN setup
to ClK.!.
20
ns
0.8 to 2.0V
0
ns
Signal rise time
(except ClK)
~H
RDYSYN hold to tCLRSYX
ClK
12
ns
2.0 to 0.8 V
tA1RW
15
ns
Signal fall time
(except ClK)
tHL
REN1, 2 setup
to RDY1, 2
REN1,2 hold to tCLA1X
ClK.!.
0
ns
CKSYN setup to tYHEH
EXFS
20,
ns
XTAl frequency
RDY1, 2 setup
to ClK.!.
12
CKSYN hold to tEHYL
EXFS
CKSYN width
25 MHz
(1) Test points are specified in accordance with V-Series CMOS
peripherals.
(2) Test points are specified in accordance with the
20
ns
Timing Waveforms
2tELEL
ns
65
ns
RESI N hold to
ClK
tCLl1H
20
ns
ClK cycle
period
tCLCL
125
ns
ClK high
tCHCL
41
ns 3V, fosc
24 MHz
(Note 1)
ns 1.5V, fosc
s 24 MHz
(Note 2)
2/3 (tCLCU -15
ClK rise and
fall time
tCLH, tCHL
PRClKhigh
tPHPL
tCLCL - 20
ns (Note 3)
PRClKlow
tpLPH
tCLCL - 20
ns (Note 3)
10
Test Points
0.8 V
RESIN: Input high level
Input low level
3.00 V
0.45 V
2V
2.
0.8 V
Measurement point
Measurement point
X=
2.6 V
0.8 V
83-004046A
AC Test Output (Except CLK)
==>{2.2V
0.8 V
Test Points
2V
2.
0.8 V
X=
83-004047A
CLKOutput
ns 1.5 to 3.5 V,
3.5 to 1.5V
READY inactive tRYLCL
to ClK!
8
ns
READY active
to ClK t
8
ns
tRYHCH
=
ns 1.5V, fosc
= 24 MHz
(Note 1)
68
v ==>{ 2.2 v
0.45 V
ns 1.5V, fosc
s 24 MHz
(Note 2)
1/3 (tCLCU +2
tCLCH
D
AC Test Input (Except RESIN)
2.6
ClKlow
~PD8284.
(3) tpHPL + tpLPH total must meet a minimum of 250 ns.
RESIN setup to tl 1HCL
ClK
tYHYL
Notes:
83YL-7024A
5
NEe
pPD71084
eLK, RESET Signals
ClK
PRClK
---I-.I-o----tPHPL----+--+l
CKSYN
~~-----~--------~
~r---t
RESET
Note:
(1 J VtN to 0.8 V or 2.2 V to VIN
(2J 1.5 V to 3.0 V or 3.0 V to 1.5 V
83-000'988
6
NEe
pPD71084
READY Pin (RDSYN = High)
ClK
RDY1, RDY2 _ _ _ _ _ _ _ _ _- . 1
REN1,REN2 ------~
RDYSYN _ _ _ _ _ _ _ _ _.1
--------~l'~-----------READY---------------83-0001999
READY Pin (RDSYN = Low)
ClK
RDY1, RDY2 - - - - - - - - - - REN1, REN2 - - - - - - - " " " "
RDYSYN -------------~
READY
_______________,""c,
I~I- - - - - - - - - - 93·70259
7
NEe
pPD71084
Test Circuit for CLK to READY
(EXFS Oscillation Mode)
Test Circuit for CLK High or Low Time
(Crystal Oscillation Mode)
Vee
.----_-~
X1
ClK
ClK
FIX
REN1
'---+----1 X2
71084
. -........--,---1 EXFS
FIX
READY
CKSYN
71084
83-004173A
1 - - - - - - 1 R DY2
Test Circuit for CLK to READY
REN2
(Crystal Oscillation Mode)
CKSYN
83-004176A
Vee
ClK
REN1
Loading Circuits
,....---+---1 X1
Load 2
Load 1
' - - -.......---1 X2
I
READY
71084
~---tRDY2
F/i(
OSC
REN2
83-004174A
Test Circuit for CLK High or Low Time
(EXFS Oscillation Mode)
Vee
ClK
71084
r - - - - t EXFS
CKSYN
83-004175A
8
FLPFl
CL = 100
71084
Output except ClK
1C'~30PF
83-004177A
CKSYN
FIX
71084
NEe
pPD71086, 71087
8·Bit Bus Buffer/Drivers
NEG Electronics Inc.
Description
Pin Configurations
p.PD71086 and p.PD71087 are 8-bit, bidirectional bus
buffer/drivers with three-state outputs. The system bus
outputs are noninverted (p.PD71086) or inverted
(p.PD71087). These devices are used to expand CPU bus
drive capability. The input/output lines are isolated from
OE and BUFR/W switching noise.
20-Pin Plastic DIP and SOP
voo
SBo/SBo
SB1/SB 1
SB2/SB 2
Features
SB3/SB 3
o CMOS technology
SB4/SB4
SBs/SBs
SBs/SBs
o Bidirectional 8-bit parallel bus buffer
SB7/SB7
BUFRtW
o Three-state output
o High system bus-drive capability (IOL = 12 mA)
o Compatible with p.PD70108/116, p.PD70208/216, and
other CMOS or NMOS designs
83SL·6912A
Pin Identification
Symbol
o p.PD71086: noninverted system bus output
Function
CPU local I/O data bus, bits 7-0
p.PD71087: inverted system bus output
System I/O data bus, bits 7-0; noninverted
(,uPD71086) or inverted (,uPD71087)
o Single +5 V ±10% power supply
o Industrial temperature range: -40 to +85°C
Output enable input
BUFR/W
Ordering Information
Buffer read/write input
Part Number
Package
Output
Voo
+5 V power supply
,uPD71086C
20-pin plastic DIP (300 mil)
Noninverted
Vss
Ground
G
,uPD71087C
G
50152
20-pin plastic SOP
20-pin plastic DIP (300 mil)
20-pin plastic SOP
Inverted
NEe
pPD71086, 71087
PIN FUNCTIONS
OE (Output Enable)
LB7-LBo (Local Data Bus)
OE input controls the output buffers. When OE is high, all
output buffers go to the high-impedance state. When OE
is low, data is output from the buffers specified by the
BUFR/W signal.
LBrLBo are three-state inputs/outputs that connect to
the CPU local data bus. They move data between the
CPU and memory, I/O, or other peripherals. Data read/
write mode is controlled by the BUFR/W signal input.
SB7-SBO/SB7-SBo (System Data Bus)
SB 7 -SBoISB 7 -SB o are three-state inputs/outputs that
connect to the system bus, along with the memory, I/O,
or other peripherals. The p,PD71086 causes no signal
inversion, the p,PD71087 inverts the signal. Input/output
condition is determined by BUFR/W status. See table 1.
BUFR/W (Buffer Read/Write)
The data read/write mode is controlled by the BUFR/W
signal input. When BUFR/Wis, high, LB lines are inputs
and SB lines are outputs. When BUFR/W is low, SB lines
are inputs and LB lines are outputs. See table 1.
Table 1. Data Read/Write Mode
OE
BUFR/W
LB Pins
5B/SB Pins
Mode
Low
Low
Output
Input
System bus to local
bus
Low
High
Input
Output
Local bus to system
bus
High
Don't care
High-Z
High-Z
p.PD71086, 71087 Block Diagram
"PD71086
"PD71087
6E 0--....-------,
6E
0--....------,
BUFR/W o--_--~+-~
r-------'
LBO o-----+-~
I
~---+---o
SBo
LBO
I
~-----------...j
LB1
o-------J
~
L ___________ J
I
LB2 ~
SB,
LB,
~SB2
~
o-------l
~
LB6
LB7
~
SB4
~SBs
1---------------1
o----J
~ SB7
L __________ -1
~
SB,
I
LB3
o--------j
LB4
~-------------l
o-------l
LB s
1------------1
I
I
Q--------j
r-----<>
SBs
I-----------...j
SB3
L-----------~
~ SB6
o-----i
0-------1
LB2
t-----------~
LBs
I
t- - - - - - - - - - - - I
~
1-------0 SB2
~-----------...j
L B4
I
I
I
o-----l
....----+---0 SBo
I
I
1------------,
~-------------1
LB3
o----J.---.
t--------o
t--------o
S B3
SB4
~------------I
LB6~
~SB6
,-----------1
LB7
0----1
~ SB7
L __________ -.J
83-0011418
2
NEe
pPD71086, 71087
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
TA = 25°C; Vss
AC Characteristics
= -40 to 85°C; Voo = 5 V ±10%
= OV
TA
Power supply voltage, Voo
-0.5 to +7.0 V
Input voltage, VI
-1.0 to Voo
+
Output voltage, Vo
-0.5 to Voo
+ 0.5 V
Power dissipation, Po
DIP
SOP
1.0 V
500mW
200mW
Operating temperature, TOPT
Storage temperature, TSTG
-65 to
+150°C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
Capacitance
Parameter
Symbol
Min
Max
Units
Conditions
Input to output
delay
tOIO
5
40
ns
Load (1), (1')
and (2), (2')
BUFR/W hold
time from OE
tHCTRW
5
ns
BUFR/W setup
time to OE
tSRWCT
10
ns
Data float time
from DE
tFCTO
5
30
ns
Load (3) and
(3')
--------------~------------------
Data output
delay from OE
tOCTO
10
40
ns
Signal rise time
tR
20
ns
0.8 to 2.0V
Signal fall time
tF
12
ns
2.0 to 0.8V
TA = 25°C; Voo = +5 V
Parameter
Symbol
Min
Max
Units
24
pF
Input capacitance
Conditions
fc
= 1 MHz
Loading Circuit for AC Test
LB to SB/SB
2.87 V
DC Characteristics
TA
[2J
[1J
[3J
= -45 to +85°C; voo = 5 V ±10%
Parameter
Symbol Min Max Units Conditions
Input voltage high
VIH
Input voltage low
VIL
Output voltage
high
VOH
Output voltage low
VOL
Output voltage low
VOL
2.2
V
0.8
Voo
-0.8
V
V
10H
V
= -4mA
0.45
V
IlL
-1.0
1.0
p.A
= 4mA
SB, 10L = 12mA
VI = Voo, Vss
Leakage current,
high impedance
10FF
-10
10
p.A
OE
Power supply
current (static)
100
80
p.A
VI
= Voo, VSS
loodyn
40
mA
fin
= 2 MHz
Input leakage
current
Power supply
current (dynamic)
0.45
0"'
LB, 10L
1"'"
206 n
Out
Out
306
n
0------.----,
675
n
SB/SB to LB
= Voo
2.05 V
[1'J
[2'J
[3'J
4130
Out
Out
1'"'"
1008
n
Out
roo"'
876
n
1100PF
-=83-001137A
3
NEe
pPD71086, 71087
AC Test Voltages
X
2AV ---"""90,...O,..,..Yo.....
OAV
10%
Test Point 1.5 V
*
't;;;....._ _ _ _ _ _ _ _ _---J
=r.VO_H-_O.1
'-_ _ _ _..:=:J
v_ _ _ ~ VOZ +0.1 V
VOL +0.1 V
VOZ -O.1 V
83YL·7002B
Timing Waveforms
BUFRIw
tHCTRW
Input
Output
----------....(1
83ML·615OB
4
NEe
pPD71088
System Bus Controller
NEG Electronics Inc.
Description
20-Pin Plastic SOP
The p.PD710SS is a CMOS system bus controller for a
p.PD7010S (V20@) or p.PD70116 (V30@) microprocessor
system. It controls the memory or I/O system bus.
lOB
BSO
BS1
BS2
BUFR/W
Features
o CMOS technology
DBEN
AEN
CEN
iiii'fAi(
AMWR
MWR
o Command outputs for system bus control
Vss
o Control outputs for I/O peripheral bus control
ICE/PBEN
ASTB
MRD
o Bus controller for microcomputer system expansion
Voo
ClK
lORD
AIOWR
10WR
83-004058A
o High drive capability for command and control
outputs (IOl = 12 mA)
Pin Identification
o Three-state outputs for command outputs
o Advanced I/O and memory write command outputs
o p.PD7010S, p.PD70116 compatible
Symbol
Function
lOB
Input/output bus mode input
ClK
Clock input
o +5-volt ± 10% single power supply
BS1
Bus status input 1
o 20-pin plastic DIP (300 mil) or SOP package
BUFR/W
Buffer read/write output
o Industrial temperature range: -40 to +S5°C
ASTB
Address strobe output
Address enable input
Ordering Information
Memory read output
Part Number
Clock (MHz)
Package Type
,uPD710aac-a
a
20-pin plastic DIP
C-10
10
G-a
a
20-pin plastic SOP
Advanced memory write output
Memory write command output
Vss
Advanced I/O write command output
Pin Configurations
I/O read command output
Interrupt acknowledge output
20-Pin Plastic DIP
CE N
Command enable input
DBEN
Data buffer enable output
ICE/PBEN
Interrupt cascade enable/Peripheral data bus
enable output
OBEN
BS2
Bus status input 2
CEN
BSO
Bus status input 0
Voo
Power supply
Voo
BSO
BS2
ICE/PBEN
iNTAK
lORD
AIOWR
10WR
83-004181 A
V20 and V30 are registered trademarks of NEC Corporation.
50151
Ground
I/O write command output
NEe
II PD71088
PIN FUNCTIONS
10WR (I/O Write Command)
BSO-BS2 (BuS Status Inputs '0, 1, 2)
The 10WR output is the signal to write data to an I/O
device. 10WR is three-state, active low.
The BSO-BS2 inputs are connected to the encoded .cPU
status outputs. The I'PD71088 decodes these status
outputs into command and 'control outputs for timing
control. See table 1 f~r an explanation of. these inputs.
ClK (Clock)
AEN (Address Enable)
The AEN input controls the command output buffers.
When lOB is low, a low-level AEN causes the command
buffers to output command output signals. A high-level
AEN makes'all command lines go to high impedance.
When lOB is high, the I'PD71088 is in I/O bus mode, and
the command lines are not affected by AEN .
CEN (Command Enable)
The CEN input controls DBEN, PBEN and all command
outputs. When CEN is high, all these outputs are active.
When CEN is low, they are inactive.
lOB (I/O Bus Mode)
When the lOB· input is high, the bus control mode is I/O
bus mode. When lOB is low, the bus control mode is
system bus mode.
Rea~
The INTAK output acknowledges interrupt requests. Requesting devices output an interrupt vector address in
response to INTAK. INTAK is three-state, activ~ low.
ASTB (Address Strobe)
The ASTB output control signal. latches the address
outputs from the CPU into an external address latch,
such as a I'PD71082 or I'PD71083. Address data should
be strobed with the trailing edge (high to low) of ASTB.
DBEN (Data Buffer Enable)
The DBEN output activates a data bus buffer/driver such
as a I'PD71086 or I'PD71087 to input or output data
between the CPU local bus and the memory or I/O
system bus.
.
BUFR/W (Buffer Read/Write)
The BUFR/W output controls the direction in which data
moves' through a transceiver between the CpU and the
memory or I/O peripherals. When BUFR/W is high, data
is transferred from the CPU local bus to the memory or
I/O system bus. When BUFR/W is low, data is transferred
from the memory or I/O system bus to the CP.U local bus.
Command)
The MRD output is the signa:! to read data from a memory
device. MRD is three-state, active low.
MWR (Memory Write Command)
The MWR output is the Signal to write data to a memory
device. MWR is three-state, active low.
AMWR (AdvanCed Memory Write Command)
This command output is the same as MWR, except that
it is generated one state (clock cycle) earlier than MWR.
lORD (I/O Read Command)
The lORD output is the signal to read data from an I/O
device. lORD is three-state, active low.
2
This,command output is the same as 10WR~ exceptthat
it is generated one state (clock cycle) earlier than 10WR.
INTAK (Interrupt Acknowledge)
The ClK input is connected to the same Clock output
that drives the CPU ciock, usually the ClK output of a
I'PD71084 or a I'PD71011. It is the internal system clock
of the I'PD71088.
MRD (Memory
AIOWR (Advanced I/O Write Command)
ICE/PBEN (Interrupt Cascade Enable/Peripheral
Data Bus Enable)
The meaning of this output signal depends on lOB. If lOB
is low (system bus" mode), it is the ICE output. ICE
controls the cascade address transfer from a master
priority interrupt controller to slave priority interrupt
controllers. The slave reads the add ress from the master
when ICE goes high. ,
When lOB is high, it becomes PBEN. PBEN controls the
I/O bus the same way that DBEN controls the system
bus. In this case, however, the output is active low.
NEe
pPD71088
Block Diagram
MRD
~{
Input
MWR
BS2
AMWR
Command
Process
Status
Decoder
BS1
Command
Output
lORD
IOWR
BSO
AIOWR
INTAK
~-{
Signal
Input
ClK
}e,_,
BUFR/W
AEN
DBEN
Control
Process
CEN
Output
ICE/PBEN
ASTB
lOB
49-0003668
Absolute Maximum Ratings
Capacitance
TA = 25°C; Vss = OV
TA = 25°C; Voo = +5 V
Power supply voltage, VOO
-0.5 to +7.0 V
Input voltage, VI
-1.0 to Voo + 1.0 V
Output voltage, Vo
-0.5 to Voo + 0.5 V
Operating temperature, TOPT
Parameter
Symbol
Min
Input capacitance
Max
Units
12
pF
Conditions
f
= 1 MHz
-40 to +85°C
Storage temperature, TSTG
-65 to +150°C
Power dissipation, Po (DIP)
500mW
Power dissipation, PD (SO)
200mW
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
DC Characteristics
TA -40°C to +85°C; Voo = 5 V ±10%
Parameter
Symbol
Min
Input voltage, high
VIH
2.2
Input voltage, low
VIL
Output voltage, high
VOH
Output voltage, low
VOL
Input current leakage
Max
Unit
0.8.-
VOD -0.8
0.45
V
V
Controls:
IOH
-8 mA @ 10 MHz, -4 mA @ 8 MHz
V
Commands:
IOL = 24 mA @ 10 MHz, 12 mA @ 8 MHz
Controls:
IOL = 8 mA@ 10 MHz, 4 mA@8 MHz
IlL
-1.0
1.0
p.A
Leakage current at high impedance
IOFF
-10
10
p.A
Power supply current (static)
100
80
p.A
loodyn
20
mA
Power supply current (dynamic)
Conditions
V
=
fin
= 10 MHz
3
NEe
pPD71088
AC Characteristics
TA
=-40 to +85°C; voo = 5 V ±10%
I'PD71 088
Max
I'PD71088C-10
Parameter
Symbol
Min
ClK cycle period
tcVCK
125
ClK pulse width, high
tpWCKH
40
41
ns
ClK pulse width, low
tPWCKL
60
49
ns
Setup time for bus status active to CLK l'
tSBSV
40
35
ns
Hold time for bus status inactive from CLK ~
tHBSV
10
10
ns
Setup time for bus status inactive to CLK .j.
tSBSIV
35
35
ns
Hold time for bus status inactive from ClK i
tHBSIV
10
10
ns
Command active delay from ClK ~
toCML
10
40
10
35
Command inactive delay from ClK ~
toCMH
10
·40
10
35
ns
Command output on delay from AE N .j.
toAECM
40
ns
Command active output delay from AE N .j.
toAECML
200
ns
20
ns
tOCML
ns
20
ns
40
100
295
tFAECM
50
Command active delay from CE N l'
toCECM
tOCML
ASTB active delay from CLK ~
toCKSTH
30
ASTB active delay from BS2, 1, 0
toBSST
DBEN, PBEN active delay from ClK ~
DBEN, PBEN inactive delay from ClK i
Max
100
Command disable delay from AE N i
ASTB inactive delay from ClK i
Min
115
Units
ns
20
ns
toCKSTL
7
25
7
25
ns
toCTV
10
50
10
35
ns
toCT
10
50
10
35
ns
25
DBEN, PBEN active delay from AEN ~
to AECT
30
30
ns
DBEN, PBEN active delay
toCECT
30
30
ns
BUFR/W i delay from CLK i
tOCKWR
40
40
ns
BUFRIW ~ delay from ClK i
toCKRo
60
40
ns
ICE active delay from ClK ~
toCKIC
30
30
ns
ICE active delay from BS2, 1,0
toBSIC
25
20
ns
ICE inactive delay from CLK ~
tolCL
Input rise time
tRI
Output rise time
40
ns
20
20
ns
tRO
20
20
ns
Input fall time
tFI
12
12
ns
Output fall time
tFO
12
12
ns
4
10
50
10
Conditions
ns
IOL = 4 mA
IOH = -4 mA
CL = 100 pF
0.8Vto 2.0V
2.0 Vto 0.8 V
NEe
#,PD71088
Timing Waveforms
General
ClK
BSO, BS1, BS2
tOCML_
tOCML-
ASTB
BUFIi/W
+------Write Mode--------t----<~I
DBEN
tOCTV
tOCK1)C.
tOBSIC
------.
ICE
Note: The rising edges of ASTB and ICE are determined by the last event: ClKI or bus status
going active.
83-0040568
5
NEe
pPD71088
Timing Waveforms (cent)
DBEN, PBEN, and Command Output
lOB
/
_---J
}~
\t}r-
CEN
~.
tOAECT
DBEN
tOCECT-
-
I~
;'-
.
-tOCECM_
_I
tOAECML
_I
tOCECM
- - tFAECM - - -
-T
\
~
83-0040576
AC Test Input
2.4 V
0.45 V
}"-
~,
+-
Command Outputs
--
-'r-
tOCECT-
Output Test Loads
=x
Voo
2.2 V
Test Points
2.2 V ) C
...
0;,;;.8..;V_ _ _ _ _ _ _ _ _ _ _...
O.;,;;8.....
V.
4700
83-004055A
AC Test Output
=x
2.2 V
_0~.8~V~
-::- 820 0
2.2V)C
_ _ _ _Test
_ _Points
_ _ _ _ _ _ _...
I
200 pF
Voo
0;,;;.8~V
1.2 kO
83-004D47A
-::- 1 kO
r100 pF
Notes:
[1] For co~d outputs MRD. lORD.
MWR, IOWR, INTAK, AMWR, and
AIOWR.
[2] For other outputs.
83-004182A
6
NEe
pPD71088
FUNCTIONAL DESCRIPTION
Table 1. Command Logic
~PD71088
Command Logic
The PD71088 decodes the CPU bus status outputs into
command outputs. The bus status outputs (BSO-BS2)
and their decoded commands are shown in table 1.
Bus Control Mode
The CEN, lOB, and AEN signals control the bus controller mode as shown in table 2.
BS2
BS1
BSO
CPU Status
Command Output
Low
Low
Low
Interrupt
acknowled ge
INTAK
Low
Low
High
I/O read mode
lORD
Low
High
Low
I/O write mode
IOWR,AIOWR
Low
High
High
Halt mode
None
High
Low
Low
Instruction
fetch mode
MRD
High
Low
High
Memory read
mode
MRD
High
High
Low
Memory write
mode
MWR,AMWR
High
High
High
No bus cycle
mode
None
Table 2. Bus Control Mode
Control Input
Control Output
Command Output
Memory
I/O
CEN
lOB
AEN
MRD, MWR, AMWR
IOWR, AIOWR, lORD, INTAK
ICE/PBEN
ASTB, BUFRrw, DBEN
H
H
H
High impedance
Outputs enabled (NC)
PBEN (NC)
Outputs enabled (NC)
ICE (NC)
Outputs enabled (NC)
(110 bus mode)
H
L
(Command
disable mode)
L
Outputs enabled
L
(System bus
mode)
H
High impedance
High impedance
L
Outpus enabled
Outputs enabled
x
x
H
H
Note:
x = Don't care, NC
= No change,
H
PBEN
=H
Outputs enabled
(DBE N = L:ASTB,
BUFR/W are NC)
= High, L = Low
7
II
fJPD71088
NEe
NEe
pPD71641
Cache Memory Controller
NEG Electronics Inc.
Description
Features
The pPD71641 is an LSI cache controller chip offering
advanced features, unequaled flexibility, and built-in
reliability to system designers. The pPD71641 makes it
practical and economical to use sophisticated caches
in microprocessor-based systems.
o General-purpose interface supports highperformance microprocessors
The implementation of pPD71641 is transparent to the
application program. The pPD71641 is configurable
from direct-mapped to 4-way set-associative mapping.
The pPD71641 allows up to 128K bytes of cache memory. Cache updating is made efficient with sub-block
partition and burst mode features.
The pPD71641 can be easily used with many generalpurpose, high-performance 32-bit or 16-bit microprocessors. Its architecture is suitable for multiprocessors
and multi master environments. Cache data consistency is ensured by bus monitoring and dual comparator techniques. The pPD71641 uses a write-through
strategy to update main memory, which guarantees
the best cache consistency in a multiprocessor and
multimaster system. External data storage is flexible in
size and organization. The pPD71641 will work with any
word width.
The pPD71641 is unique in offering features to implement a highly reliable cache memory subsystem. The
pPD71641 provides built-in reliability checks, such as
address tag parity check, multiple hit detection, and
self-diagnosis for directory faults. Upon detection of an
erroneous condition, the pPD71641 can either be disabled, or continue to operate in a functionally degraded mode.
o Transparent to application programs
o Flexible placement algorithm: direct 2-, 4-way setassociative
o Large tag memory configuration:
- 1024 sets x 1 way x 2 sub-blocks
-512 sets x 2 ways x 2 sub-blocks
- 256 sets x 4 ways x 2 sub-blocks
o Programmable sub-block size up to 64 bytes
o Bus replacement cycle variable from 1 to 16 words
o Supports large cache memory up to 128K bytes
o Supports up to 4G bytes of main memory
o LRU replacement algorithm
o Write-through strategy
o Data consistency check by bus monitoring
o External PURGE input to flush tag store
o Increased reliability through internal error
detection
- Parity check on tag store
-Incorrect match check
- Multiple hit check
- LRU output check
o Unique level degradation feature to maximize
cache system up time
o 16- and 20-MHz operation
o 132-pin PGA package
Ordering Information
Part Number
pPD71641R
50135-1
Max Clockout
Frequency
Package
25 MHz
132-pin Ceramic PGA
NEe
JlPD71641
Pin Configuration
132-Pln Ceramic PGA
PNML KJ HGFE DCBA
o 0 0,0 0 0 '0 0 0 0 0 0 0 0 14
00000000000000 13
00000000000000 12
o 00 11
0 0 0,
000
o 00 10
o 00 9.
9 000
o 00 8
8 000
pPD71641
o 00 7
7 000
o 00 6
6 000
o 00 5
5 000
e 0 00 4
4 000
3 o 0 0 000 0 00 0 0 0 0 0 3
200000Qoooooooo 2
10000000000000.1
14
13
12
11
10
P N M L K J H G FED C BA
Pin
Symbol
MAg
K14
MAs
l1
MA25
03
MAa
l2
MA28
012
GNO
l3
MAa1
013
As
l12
Aao
014
Ag
l13
A27
E1
MA12
l14
A24
E2
MA10
M1
MA26
E3
MA7
M2
MAao
E12
A7
M3
GNO
E13
A 10
M4
BOY
E14
A12
M5
OPAR
MA14
M6
GNO
e Orientation Pin
F2
MA13
M7
VOO
Index Mark
F3
MA11
M8
GNO
F12
A11
M9
msg
F13
A13
M10
10
F14
GNO
M11
VDO
G1
MA16
M12
GND
G2
MA15
M13
'Az3
G3
GNO
M14
A25
G12
A14
N1
MA29
G13
A15
N2
VDO
G14
A16
N3
~
H1
MA17
N4
BYPf
H2
MA18 "
N5
PURGE
H3
MA19
N6
FAULT
H12
A18
N7
OlK
H13
Voo
N8
CR3
83-004660A
Pin Identification
Pin Identification
Pin
Symbol
Pin
Symbol
A1
lffim
B9
10
A2
01
A3
mR
lV\S
Pin
B10
Symbol
RBOY
A5
R02
B11
'OW2O
A6
RAO
B12
CR21
A7
RA2
B13
A8
RA3
B14
A10
A11
A12
A13
VOO
k
10
01
MAs
l3Ef!fR
02
M~
AT/BY
03
Voo
m:IDY
04
GNO
CR20
05
02
Aa
06
B1
Mk
07
VOO
B2
GNO
08
GNO
B3
Do
09
B4
03
010
B5
R01
011
B6
R03
012
B7
RA1
013
~
B8
10
014
As
A14
2
~1
01
F1
•
A9
. Symbol
02
Bottom Vie';';
A4
Pin
ROO
BRO
~
CW21
GNO
H14
A17
N9
~
J1
MA20
N10
"CW3
J2
MA21
N11
10
J3
MA23
N12
AHIT
J12
A22
N13
GND
J13
~o
N14
A28
J14
A19
P1
RJW
K1
MA22
P2
OM)
K2
MA24
P3
RESET
K3
MA27
P4
FATAL
K12
A26
P5
OlAMP
K13
A23
P6
'CRO
NEe
pPD71641
Pin Identification
(coot)
Pin
Symbol
Pin
Symbol
P7
CR1
00
'CWO
"CW2
P11
SYPO
P12
Ie
P13
tROY
Aa1
P8
P9
P10
P14
PIN FUNCTIONS
CPU Interface
A3-A31 (Address Bus). CPU address outputs are connected to these inputs. Depending on cache organization, from. 8 to 10 of the low address bits are used to
select a set of tags. These inputs are latched internally
once a p.PD71641 cycle begins.
is asserted, the p.PD71641 will treat the cycle as noncacheable, and assert BYPO. The cache memory is not
accessed.
DPAR (Data Parity). This active-high input signals that
an error has occurred in the cache data store. When
these errors are received, the p.PD71641 will disable the
current level and enter a functionally degraded mode.
That is, if a parity error occurs in bank 3 of a 4-way
set-associative cache memory, level 3 will be disabled.
AHIT (Asynchronous Cache Hit). This active-high
asynchonous output is. asserted when the current address inputs (Aa-A31)' produce a tag match, indicating
that the data being accessed is mapped into the cache
data store.
BCY (Bus Cycle Start). This active-low input is sampled
on the rising edge of ClK It indicates that a CPU cycle is
ready to be submitted to the p.PD71641. When BCY is
detected, the p.PD71641 will begin its cycle.
CRDY (CPU Ready). This active-low output can be used
to sign~1 the CPU that the bus cycle can be ended. CRDY
is asserted when the. cycle is a cache hit, when the
requested data is available at the end of a cache update
cycle, when a CMD access is completed, or when a
bypass cycle has completed (actually controlled by
external logic via the SRDY input).
CS (Chip Select). This active-low input is sampled on
the rising edge of ClKlf this pin is not asserted, then the
cache will not operate. This input is used to separate
cacheable (e.g., memory access) and non-cacheable
(e.g., I/O) CPU bus cycles. If this input is not asserted,
BCY is ignored, but CMD operations can still take place
and the bus monitor function continues to operate.
MISS (Cache Miss). This active-low output is asserted
when the p.PD71641 has detected a cache miss on a CPU
read cycle. It remains asserted throughout the cache
update operation. MISS is distinct from AHIT because it
is synchronous to the ClK, while AHIT is not. MISS is
also asserted when an internal error. forces a cache
update, or if a cache bypass cycle is aborted by BERR. ~
R/W (Read/Wrlte). This input is used to separate CPU
read cycles from CPU write cycles, since the p.PD71641
handles each type of cycle differently. If this input is low
when BCY is sampled, a cache write operation will
begin. If RiW is high, read operation will begin. This input
is also used during CMD accesses.
BYPO (Bypass Out). This active-low output indicates to
external hardware that the current CPU bus cycle will
bypass the cache memory. Either the address is not
cacheable, or the cycle is a memory write. In the case of
a memory write, the data will be written in parallel to the
cache memory. External logic must complete the bus
cycle. This output is asserted whenever the BYPI input is
~sserted at the start of a cycle, during all cache writethrough cycles, and whenever the p.PD71641 is unable to
complete a cycle due to an internal error condition.
CMD (Command Mode). This active-low input is sampled on the rising edge of ClK It should be asserted
when the CPU needs to access one of the p.PD71641's
internal registers. Inputs RAO-RA3 select which internal
register will be used. CMD overrides the BCY and CS
inputs.
CLAMP (Clamp Address Input). This active-high input
prevents any problems due to a floating level on any
p.PD71641 inputs. In the event it becomes necessary to
float the inputs to the p.PD71641 (e.g., during,DMA), this
input should be asserted. If this input is used, external
pullup resistors will not be required.
BYPI (Bypass In). This active-low input is sampled on
the rising edge of ClK If this input is asserted when BCY
FAULT (Fault). This active-high output indicates that the
p.PD71641 is operating in a functionally degraded mode,
that is, some portion of the tag store has been disabied
due to an internal or external error.
FATAL (Fatal Fault). This active-high output in conjuction with FAULT indicates the status of the p.PD71641. If
an unrecoverable internal error occurs, and the
p.PD71641 removes itself from the system, this output will
remain asserted.
RAO-RA3 (Replacement Address). These inputs select
the internal register for a CMD access. They also supply
the starting offset for a fetch bypass operation. During
3
11:61
NEe
IIPD71641
normal replacement operations, the replace cycle begins
at an offset of O. If fetch bypass is enabled, the first bus
cycle of the replacement will be to the address determined by these inputs, so that the data requested by the
CPU will be available as soon as possible.
00-03 (Data Bus). These bidirectional pins form the
4-bit data bus used to access the p.PD71641 internal
registers. This bus is also used to output tag store
contents during a cache directory dump operation.
CRO-CR3 (4-Way Cache Read Strobes). When a 4-way
set-associative cache organization is selected, these
four active-low outputs select which of the four banks of
cache data storage will supply the data on a CPU read
cycle. They are also asserted during a cache memory
dump operation.
CR20-CR21 (2-Way Cache Read' Strobes).When a 2way set-associative cache organization is selected,
these two active-low outputs select which of the two
banks of cache data storage will supply the data on a
CPU read cycle.
'
They are also asserted during a cache memory dump
operation. These outputs are also used for directmapped caches. CR20 and CR21 must be logically
ORed with external logiC to produce a single read strobe
for the one bank of RAM.
CWO-CW3 (4-Way Cache Write Strobes). When a 4way set-associative cache organization is sele,cted,
these four active-low outputs select which bank of the
cache data store will be written during a CPU write cycle.
CW20-CW21 (2-Way Cache Write Strobes). When a
2-way .set-associative cache organization is selected,
these two active-low outputs select which bank of the
cache data store will be written during a CPU write cycle.
These outputs are also used for direct-mapped caches.
CW20 and CW21 must be logically ORed with external
logic to produce a single write strobe for the one bank of
RAM.
Bus Monitor Interface
MAS (Bus Monitor Address Strobe). This active-low
input is sampled on the riSing edge of ClK. When it is
sampled low, the p.PD71641 will begin a cache invalidate
cycle on the address presented on inputs MAs-MAs1.
Each' check-and-invalidate operation takes two clocks.
MA3-MA31 (Bus Monitor Address). These inputs. are
sampled when MAS is sampled low. The system bus
address lines should be logically connected to these
inputs.
4
A write cycle to global memory could change a memory
location that has been cached. If this happens, the data
in the local cache is no .longer consistent with global
memory. To ensure cache data consistency, the
p.PD71641 provides bus monitoring. When an address is
presented on these MA inputs, the p.PD71641 will perform a tag search on that address. If a high is detected,
the indicated sub-block will be invalidated. This tag
search operation is completely independent from the
CPU address tag search, since the p.PD71641 tag store is
fully dual-ported with two sets of comparators.
MAa-MAa1 become outputs during cache' dump operations, supplying the upper address bits for the dump.
System Bus Interface
RREQ (Replacement Request). This active-low output
is asserted when the p.PD71641 wants to use the global
bus for· a cache data replacement cycle or for a cache
directory or data dump operation.
RACK (Replacement Acknowledge). This active-low
input is asserted by the system bus interface when
access to the shared memory for a replacement or a
dump cycle has been granted. Once begun, replacement
or dump cycles can be suspended by desserting this
input. The p.PD71641 will interrupt the miss cycle,
thereby releasing the global bus to a higher priority bus
master, and will resume the interrupted operation when
RACK is asserted again. Bus monitoring is disabled while
the replacement or dump cycle is suspended.
RAE (Replacement Address Enable). This active-low
output indicates that the p.PD71641 has begun a cache
data replacement cycle to service a cache read miss.
This output should be used to control the multiplexing
between the RC outputs and CPU address. Also, any
other logic that changes during a replacement cycle
should use the RAE signal.
RCO-RC3 (Replacement Count). Sub-blocks can be
up to 16 words in length. During a replacement cycle, the
RC outputs provide the offset address in the sub-block.
Depending on the size of the sub-block, not all these pins
will be used.
RBCY (Replacement Bus Cycle Start).This active-low
output signals the start of a replacement bus cycle or a
dump cycle.
SRDY (System Ready). This active-low input is asserted
by the system bus interface or shared memory control
logic when the bus operation that the p.PD71641 requested has been completed. The p.PD71641 will pass
this signal through to the CPU via its CRDY output.
NEe
BRC (Burst Replacement Cycle). This active-high input determines on a cycle-by-cycle basis if the replacement cycle is to use a burst data transfer.
BERR (Bus Error). This active-low input signals a system bus error. If the current cycle is a replacement
operation, RT/BY can be used to either abort the cycle or
try it again. If the current cycle is a cache bypass (such
as a CPU data write cycle), the ~PD71641 will assert its
MISS output to let the CPU know that the operation did
not complete.
RT/BY (Retry/Bypass). When BERR has been detected,
the p.PD71641 uses the state of this input pin to decide
whether to abort the cycle (RT/BY = 0) or to retry the
cycle (RT/BY = 1).
This input is also used to implement external write
buffering, or a "posted write" system write performance. Normally, during a CPU data write cycle, boththe
CPU and the p.PD71641 are suspended waiting for the
write cycle to end. However, if the RT/BY input is high, the
p.PD71641 will not wait for SRDY. It will immediately end
its internal cycle and go into the Ti state, allowing the
p.PD71641 to begin processing the next CPU bus cycle if
one is available. External logic can finish the write cycle.
pPD71641
Other Signals
RESET (Reset). This active-high input will reset the
All tag stores will be invalidated, all preset
commands will be cleared, and all status bits will be
cleared. The cache will be disabled until enabled by the
software command. RESET must be asserted for at least
10 clock pulses.
~PD71641.
PURGE (Purge). This active-high input will purge all the
tag stores when it is asserted. An identical softwaregenerated PU RG E operation is also available.
PU RGE may be used to invalidate the cache tag store in
the event the bus monitoring function is unable to keep
up with external bus activity.
The PURGE input must be asserted until the purge
operation is complete. This takes a maximum of 5 clocks,
so PURGE must be asserted for at least 5 clocks.
CLK (Clock). This is the p.PD71641 clock and should be
sychronized to the CPU clock.
IC. Internally connected; leave disconnected.
VDD.
Supply pins for +5 V power supply.
GND. Supply pins for power ground.
Block Diagram
elK
RESET
A 31-A3
DPAR
FAULT
FATAL
L---------o
L-_ _ _ _ _ _ _ _ _ _ _ _ _
~
PURGE
~S
BCY
AHIT
CADY
5
NEe
JlPD71641
Figure 1. lIemery Size Expansion '
Cache Access Address A
83YL·6162B
Figure 2. TypICllI System Configuration
Main
Memory
83YL·6163B
6
fttIEC
INTERNAL BLOCK FUNCTIONS
Dual-Port Address Tag Memory
Dual-port address tag memory is dual-port memory that
decodes the index field input Independently from the
CPU side and monitor side and outputs the contents of
the memory (block entry) as address tag. When a mis-hit
occurs during CPU access, a new block address is
registered.
IIPD71641
CPU Interface Controller
The CPU interface controller generates a normal/notnormal response (data acknowledge, bus error, fatal
error, etc.).
Replace Sequencer
The replace sequencer regenerates the replace timing
and replace count value when a mis-hit occurs.
Valid Bit Memory
Bus Interface Control Block
Valid bit memory is a group of flags that indicate whether
each block entry Is valid or Invalid. These flags are set
each time the replacement of a sub-block Is completed,
and reset upon a monitor hit.
The bus Interface control block generates the read/write
strobe signal to the external cache data memory.
Comparators
Two comparators are provided. One is for the CPU side
and the other Is for the monitor side. The comparator on"
the CPU side is used to check if the address tag registered In the directory coincides with the address used to
access the system bus.
Table 1 describes each of the bus states. Figure 3 Is a
state diagram for the bus interface.
Ts6/. 1. Sua Int.rlse. SIs'.
Bu. State
o..crlptlon
TI
Idle state. waiting for BeY and ~ to be asserted.
T2
First state of any cacheable CPU cycle or 10 cycle to
"PD71641 registers. T2 Is the dispatch state that
decides what the "PD71641 will do. If there Is a cache hit
or a 2-clock cycle request, T21s also the last active state.
If there Is a miss, Tm Is entered. If this Is a cache write
cycle, Tb Is entered. Tc Is entered If It Is a "PD71641
command cycle.
Tc
Command Mode state. If this Is a I'PD71641 command
cycle, the Tc Is entered following T2, then repeated
before returning to the Idle state.
Tm
Miss state. Entered If there Is cache read miss. The . .
system bus Is requested, and the RTistate Is entered. If
RACK Is already asserted, the AT state sequence Is
entered.
RTI
Replacement Transfer Idle state. walts for the system
bus to be granted via RACK, then transitions to AT1.
Rn
First Replacement Transfer state. While RACK Is on,
proceeds directly to RT2.
RT2
Second replacement transfer state. walts for SRl5Y to be
asserted, Indicating the system bus memory Is ready to
begin the transfer, the goes to RT3.
RT3
Third RT state. The read data Is written to the cache data
store, and If the sub-block transfer Is complete or the
transfer Is aborted, the RTw state Is entered. If not
complete, and burst transfers are not requested, a
return Is made to RT1 to begin another single-word
transfer. If In burst mode, RT41s enered to get the rest of
the sub-block. If a retry Is requested, RTr Is entered.
RT4
Fourth RT state. Used only for burst transfers, which
take two clocks each. Until replacement Is complete, the
state machine ping-pongs between RT4 and RT5. The
data Is written at RT5.
RT5
Last RT state. Accepts data from burst transfers. If the
transfer Is over, RTw Is entered. On a retry request, RTr
Is entered.
Parity Generator
The parity generator generates the parity for the address
tag associated with CPU accessing, and compares it
with the address parity registered in the directory. This
compare operation Is performed simultaneously with the
CPU address comparison. When a mis-hit occurs, the
generated parity is registered together with the new
address.
Status Register
The status register indicates reduction data related to
parity errors or mUlti-hit errors. In addition, it also indicates whether or not the "PD71641 is in the fatal state.
LRU and LRU Memory
LRU and LRU memory manage the CPU block accessing
order and perform LRU calculations based on valid bit,
error status, number of associative units, etc.
Main Sequencer
The m~ sequencer decodes the bus cycle signals (BCY,
CS, R/W, BYPI, CMD, etc.) generated by the CPU, and
generates the timing for the basic cache memory operation cycle. The main sequencer determines whether the
accessing is a cache memory access, a cache memory
bypass access, or a cache command access. The main
sequencer enters the standby state when the replace
sequencer is in operation.
7
~
NEe
JlPD71641
Tabl. 1. Bus In'erface
St.,..
Diagnosis Sequencer·
(conI)
Bus State
Description
RTr
m retry state. nansltlons directly to Rn, which begins
the cycle again.
RTw
RT recovery state. During this state, If the replacement
was successful, the "PD71641 tag store Is updated. and
the data thatthe CPU requested Is made avallable.lfthe
cycle was aborted, the bypass state Is entered.
Tb
Bypass state. The bypass cycle was started by T2 soTb
walts for the system memory to respond with SRDY, then
returns to TI.
Tf
Fatal error state. If during Tm an unrecoverable error
occurs. Tf Is entered to record the error. then a bypass
cycle Is entered by going to Tb.
The dlagnosis sequencer consists of the direetory trace
sequencer and the internal diagnosis sequencer. The
directory trace sequencer performs cache selfdiagnostics and dump processing. The internal diagno.sis sequencer sequentially generates the memory diagnostics data for the issuance of internal diagnostics
commands. and the collects the data.
Flgur.3. SIM Sta'. DIagram
Always
Not Burst Mode' Replacement Not Completed
SRDY#
Asserted
Fatal Internal Error
Replacement Completed
+ (BERR# Asserted, RT/BY# = 0)
SRDY#
Asserted
Replacement
Bus Error Abort
Replacement Completed
(BERR# Asserted; RT/BY# = 0)
Replacement
Completed
Repeat Once
83YL-6288B
8
NEe
pPD71641
ELECTRICAL SPECI FICATIONS
AC Characteristics (cont)
Parameter
Symbol
Absolute Maximum Ratings
ClK low-level width
~KL
ClK rise time
tRK
ClKfall time
tFK
TA
= 25°C
-0.5 to + 7.0 V
Supply voltage,Voo
Input voltage
Min
Max
Unit
3
ns
1.7 to 3.0 V
3
ns
3.0 to 1.7V
Other than ClK, VI1
-0.5 to Voo +0.3 V
ClKVI2
-0.5 to Voo +1.0 V
Number of reset
clock
tCYKRS
10
RESET setup time
(vs. ClK.!.)
tSRSK
7
ns
RESET retention
time (vs. ClK .!.)
tHKRS
8
ns
Number of purge
clock
tCYKPG
3
tCYK
PURGE setup time
(vs. ClK.!.)
tSPGK
7
ns
PURGE retention
time (vs. ClK .!.)
tHKPG
8
ns
Address setup time
(vs. ClK 1)
tSAK
5
ns
Address retention
time (vs. ClK 1)
tHKA
15
ns
~setuptime
(VS. ClK 1)
tSBCK
7
ns
~ retention time
tHKBC
8
ns
tSCSK
7
ns
tHKCS
8
ns
tSCMK
7
ns
CMD retention
time (vs. ClK 1)
tHKCM
8
ns
lWPi setup time
tSBIK
7
ns
tHKBI
8
ns
tSRWK
7
ns
tHKRW
8
ns
CLAMP setup time
(vs. ClK 1)
tSCPK
25
ns
CLAMP retention
time (vs. ClK 1)
tHKCP
0
ns
RT/BY setup time
(vs. ClK.!.)
tSRTK
7
ns
Output voltage, Vo
-0.5 to Voo +0.3 V
-10to +70°C
-SO to + 15O"C
Storage temperature range, TSTG
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent
damage.
Capacitance
TA
= +25°C; Voo
= GND = 0 V
Parameter
Symbol
Min
Max
Unit
Condition
f = 1 MHz;
unmeasured
pins returned
to OV
Input capacitance
CI
15
pF
Output capacitance
Co
15
pF
Input/output
capacitance
CIO
15
pF
DC Characteristics
TA
= -10 to
+70°C; Voo
Parameter
= +5.0V::I:10%
Max
Symbol Min
Input voltage,
high
VIH1
2.2
V1H2
4.0
Unit Condition
Voo + 0.3
Voo + 0.3
V
ClK
Other than ClK
CS' retention time
(vs. ClK 1)
VIL1
-0.5
0.8
VIL2
-0.5
0.6
V
ClK
Output voltage,
high
VOH
2.4
V
10H
Output voltage,
low
VOL
0.45
V
Input leakage
current
III
::1:10
p.A
Output leakage
current
ILO
Operating
current
100
CS' setup time
= -10 to
CL = 100 pF
(vs. ClK 1)
= -400 p.A
'CMi5 setup time
(vs. ClK 1)
10L
= 3.2mA
(vs. ClK 1)
::1:10
1WPi retention time
p.A
(vs. ClK 1)
250
mA fiN = 20 MHz
RJW setup time
(VS. ClK 1)
RJW retention time
AC Characteristics
TA
= 100 pF
(vs. ClK1)
Other than ClK
V
tCYK CL
CPU Input
V
Input voltage,
low
= 1.7V
VIL 2
Reset, Purge
Operating temperature range, TOPT
Condition
ns
20
(vs. ClK 1)
+70°C; Voo = +5 V ::1:5%
Parameter
Symbol
Min
Max
Unit
Condition
Clock
Clock frequency
tCYK
50
ClK high-level
width
~KH
20
125
ns
ns
VIH2 = 3.0V
9
NEe
pPD71641
Replace/Bypass Timing Specifications
AC Characteristics (cont)
Parameter
Symbol
Min
Max Unit Condition
tHKRT
8
ns
OPAR setup time
(vs. ClKJ.)
tSOPK
7
OPAR retention
time (vs. ClK .1.)
tHKDP
8
RT/BY retention
time (vs. ClK J.)
= 100 pF
BRC setup time
(ClKJ.)
ns
ns
CL
CPU-Side Output Timing Specifications
Parameter
Symbol Max Unit
Add valid - AHIT delay
tOAAH
50
ns
ClK .1. - 'OFIDV valid delay
tOKCRY
25
ns
ClK J. - ~ valid delay
tOKMS
25
ns
tOKBO
25
ns
tOKCRL
25
ns
tOKCRH
25
ns
tOKCW
25
ns
ClK t - ~ - CR21 J. delay
tOKCR2L
25
ClK J. - ~ - 'Ci121 t delay
tOKCR2H
25
ClK t ClK t ClK J. ClK J. -
BYJ50 valid delay
CRO - 'OR3 J. delay
CRO - 'OR3 t delay
'CWO - mv3 valid delay
'CW2O- 'OW21 delay
Condition
= 25pF
CL = 100pF
CL
8
ns
ClKt-lmEO
valid delay
tOKRRQ
mR setup time
(ClK.1.)
tSRKK
7
ns
mRholdtlme
(ClKJ.)
tHKRK
8
ns
AAE valid
25
tOKRC
25
ns
ClK t - RC float
delay
tFKRC
ns
SRD'Y setup time
tSSRYK
7
ns
ns
(ClKJ.)
SRI5Y hold time
tHKSRY
8
ns
tSBEK
7
ns
tHKBE
8
ns
tOKFL
25
ns
§Ei1R setup time
ns CL
RAO-RA3 hold time (ClK 1)
tHKRA
10
ns
00-03 setup time (ClK 1)
tSOK
15
ns
8
ns
ns
ns
00-03 float delay
tFKD
MA hold time (ClK J.)
tHKMA
8
ns
MA setup time (ClK J.)
tSMAK
15
ns
MAS' hold time (ClK.1.)
tHKMS
10
ns
MAS' setup time (ClK J.)
tSMSK
10
ns
ns
(ClKJ.)
~holdtlme
(ClKJ.)
Symbol Min Max Unit Conditions
10
= 100 pF
(ClKJ.)
Command Access/Bus Monitor Timing
Specifications
RAO-RA3 set·up time (ClK 1) tSRAK
ClK J. delay
Conditions
CL
ns
ClK t - RC valid
delay
ClK t - FAULT valid delay
10
tHKBR
ns
ns
25
BRC hold time
(ClKJ.)
25
ns
tOKD
tSBRK
ns
tOKRB
25
tHKD
Unit
ClK t - 'FfBOY
valid delay
25
00-03 hold time (ClK 1)
Max
7
ns
tOKFT
00-03 valid delay
Min
25
tOKCW2
Parameter
Symbol
tOKRAE
ClK t - FATAL valid delay
ClK J. -
Parameter
= 100 pF
DUMP Timing Specifications
Parameter
Symbol
ClK J. - M~·MAa1
delay
tOKMA
ClK J. - MAa·~A31
floating
tFKMA
Min
Max
Unit
25
ns
ns
Conditions
CL
= 100 pF
NEe
pPD71641
Timing Waveforms
Resel/PU'1Ie Timing
AC Test IlIIOutput (except CLK)
2.4 V
0.45V
--y. 2.2 V
2.2 V
V-
~...;0.;.;..8....;.V_ _ _ _ _ _..;.;0.~8~VA-
elK
83YL-6151A
AC Test IlIIOutput (CLK)
4.0 V
--y. 3.0 V
3.0 V
V-
RESET
0.6 V ~_1_.7_V_ _ _ _ _ _....;.1.....;.7__
V A83YL-6152A
Clock Timing
elK
elK
PURGE
83YL-6154A
83YL-6153A
11
pPD71641
CPUlnpuf
T1
T2
DPAR
:C
~_ _ _ _ _ _ _
83YL-6155B
12
ttiEC
IIPD71 641
CPU Output
T1
T2
ClK
A31-A3
~
tDAAH
I
I
~~~
__~_______
AHIT
~--------~~--------
'-----
_t:DKCRYh~1
CRDY
MISS
=x
_lbK+?-~1'----=x
I I
tDKCRl
___b_
FATAL
=x
y
tDKFT
__
_]tDKFL
FAULT
-----------
83VL-6156A
13
NEe
pPD71641
Command Access Timing
TC
T2
TC
TI
ClK
RA3- RAO
D3-DO
83YL·6159B
Bus Monitor Timing
ClK
'MA31 - MA3
83YL-616OA
14
NEe
pPD71641
ReplBee Timing
Tm
RT1
RT1
ClK
BRC
tOKRRC \4----+1
tOKRAE t+---~
tOKRB 14-------.1
tOKRC
RC3-RCO
--------------------------------------------------~
83YL-6157B
Dump Timing
Bypsss Timing
RT2
RT3
RT1
RT2
RT1
Tc
Ti
1\1
IDKMAF~:..
ClK \
MA31-MA3~
15
pPD71641
16
1tIEC
NEe
Development Tools
6-1
NEe
Development Tools
Section 6
Development Tools
CC7011S
V-Series C Compiler
Sa
DDK-70320
Evaluation Board for V25 Microcomputer
Sb
DDK-70330
Evaluation Board for V35 Microcomputer
Sc
IE-70136
In-Circuit Emulator for p.PD70136 (V33)
Microprocessor
Sd
IE-70136-PC
In-Circuit Emulator for p.PD70136 (V33)
Microprocessor
Se
IE-70208, IE-70216
In-Circuit Emulators for p.PD70208 (V40) and
p.PD70216 (V50) Microprocessors
Sf
IE-70320
In-Circuit Emulator for p.PD70320/70322 (V25)
Microcomputers
S9
IE-70330
In-Circuit Emulator for p.PD70330/70332 (V35)
Microcomputers
6h
RA70116
Relocatable Assembler Package for V20-V50
Microprocessors
6i
RA70136
Relocatable Assembler Package for V33
Microprocessor
6j
RA70320,
Relocatable Assembler Package for V25N35
Microcomputers
Sk
V25N35 MINI-IE Plus
In-Circuit Emulator
V40N50 MINI-IE
In-Circuit Emulator
6-2
61
6m
NEe
CC70116
V-Series C Compi ler
NEC Electronics Inc.
Description
The CC70116 C Compiler package converts standard C
source code into relocatable object modules for the NEC
V20® (~PD70108), V30® ~PD70116), V40™ ~PD70208),
and V50™ ~PD70216) microprocessors and the V25™
~PD70320) and V35 ™ ~PD70330) single-chip microcomputers. These modules are compatible with those
produced by the RA70116 V20-V50 Relocatable Assembler package and the RA70320 V25N35 Relocatable Assembler package and may be linked with other modules
using the appropriate linker provided with the assembler
package.
o Runs under a variety of operating systems
-MS .. DOS
-VAXNMS®
- VAX/UNIXTM 4.2 BSD or Ultrix®
Ordering Information
Part Number
Description
CC70116-D52
MS-DOS, 5" double-density floppy diskette
CC70116-WT1
VAX/VMS, 9-track 1600BPI magnetic tape
CC70116-VXT1
VAX/UNIX 4.2 BSD or Ultrix, 9-track 1600BPI
magnetic tape
Features
Extensions to Standard C
o Standard Kernighan and Ritchie C
- Defined in UNIX System III
Enumeration data type: Similarto the enumerated type in
Pascal, this allows the definition of a limited set of
[mnemonic] values for a variable, thus preventing assignment of invalid values to the variable.
o Supports small and large memory models
o NEC enhancements
- Enumeration data type support
- Assignment of all members by a structure name
- Ability to use identical names in identifiers of
different types in different structures
- Addition of a void type to declare functions with
no return val ue
- Addition of char as a data type for which
unsigned can be specified
- Ability to initialize structures with bit fields
o CC70116 library conforms to UNIX System III
specifications
- MS-DOS® and CP/M-86® dependent functions
included
o C macros for sorting and converting ASCII code
characters
o User-selectable object code optimizer
Assignment of all members by a structure name: Allows
assignment of all the members of a structure from
another structure of the same type simply by using the
names of the structures.
Ability to use identical names for identifiers of different
types in different structures: Allows the same member
name in two different structures to have a different name
in each.
Addition of a void type: Prevents the use of functions ~
which return no value in expressions where a return ~
value is required.
Addition of char as a data type for which unsigned can
be specified: Allows the full 8 bits of the char data type to
be used as a value, rather than only the low-order 7 bits.
Ability to initialize structures with bit fields: Allows
structure with bit-field members to be initialized via the
C construct.
Compiler Options
V20 and V30 are registered trademarks of NEC Corporation.
V25, V35, V40 and V50 are trademarks of NEC Corporation.
UNIX is a trademark of AT&T.
CP/M-86 is a registered trademark of Digital Research Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
VAX, VMS, and Ultrix are registered trademarks of Digital Equipment
Corporation.
50222
The CC70116 C Compiler supports the following options
during compilation.
A
B
Generates assembly language listing
C
Specifies drive for compiler phases
Leaves comments in C source image file (used
with P)
D
Defines a name
NEe
CC70116
E
H
NS
o
P
T
U
X
Outputs C source image to a standard output
device after only compiler control line
processing
Generates an object module for the interrupt
handling section of RX116 (realtime operating
system)
Specifies drive for include files
Suppresses symbol table information in object
module
Selects optimization
Outputs C source image to a file after only
compiler control line processing
Limits· compiler phases to be input from drive
selected by B option
Nullifies the initial definition of the name
defined by 0 option
Generates object code for the large model
Memory Models
The CC70116 supports the small and .large memory
models. With the small model, a total of 128K bytes of
memory can be accessed: 64K bytes for data and 64K
bytes for code.· With the large model, up to 1M byte of
memory can be accessed for code and data. In addition,
data constants can be permanently encoded into the
ROM space. Programs using the small memory model
are more efficient in terms of space utilization and
execution speed and are recommended when your program can fit into one data and one code segment.
CC70116 Library Functions
The CC70116 C Compiler library conforms to the UNIX
System III library specifications. Some library routines
are operating system dependent and may only be used
to create programs that run under MS-DOS or CP/M-86;
other functions do not call the operating system, and
may be used in any program.
In the list below, the asterisk (*) means user system,
MS-DOS, or CP/M-86 dependent.
abort*
abs
access*
atoi
atol
close*
creat*
exit*
fclose
2
fread
freopen
fscanf
fseek
ftell
fwrite
getchar
gets
getw
MSDOS1*
MSDOS2*
MSDOS3*
open*
perror
.printf
putchar
puts
putw
srand
sscanf
strcat
strchr
strcmp
strcpy
strlen
strncat
strncmp
fdopen
fflush
fgetc
fgets
fopen
fprintf
fputc
fputs
lseek*
mktemp
mpm1*
mpm2*
mpm3*
mpm4*
mpm5*
mpm6*
qsort
rand
read*
rewind
sbrk*
scanf
setbuf
sprintf
strncpy
swab
ungetc
unlink*
write*
C Macros
Included with the C compiler are C macros for sorting
and converting ASC II code characters. These macros
are listed below.
_to lower
_toupper
feof
ferror
fileno
getc
getchar
salnum
isalpha
isascii
iscntrl
isdigit
isgraph
islower
isprint
ispunct
isspace
isupper
isxdigit
putc
putchar
toascii
Start-Up Modules
Six small and large start-up modules are included in the
CC70116 C Compiler package to initialize programs
generated by the compiler: modules for embedded systems; modules for executing programs under the MSDOS operating system; modules for executing programs
under the CP/M-86 operating system.
Operating Environment
The CC70116 package can be supplied to run under a
variety of operating systems. One version is available for
an MS-DOS system with one or more disk drives and at
least 128K bytes of system memory. Other versions are
available to run on a Digital Equipment Corporation VAX
computer with UNIX 4.2 BSD or Ultrix or VMS (Version
4.1 or later) operating systems.
To produce executable programs, a linker (LK70116 or
LK70320) and a hexadecimal object code converter
(OC70116 or OC70320) program are required and the
librarian (LB70116 or LB70320) program is useful. These
programs are available separately from NEC Electronics
Inc. as part of the RA70116 V20-V50Relocatable Assembler package or the RA70320 V25N35 Relocatable Assembler package.
The linker produces an absolute load module containing
both symbol and source code line number information
and the absolute object code. This module may be
loaded directly into the appropriate NEC in-circuit emulator for execution with full symbolic debug capabilities.
NEe
CC70116
The hexadecimal object code converter produces an
extended hexadecimal format object code file that may
be loaded into a PROM programmer.
Documentation
For further information on source program format, compiler operation, and actual program examples, the following documentation is furnished with the CC70116
compiler package. Additional copies may be obtained
from NEC Electronics Inc.
• CC70116, V-Series C Compiler Operation Manual
(MS-DOS)
• CC70116, V-Series C Compiler Operation Manual
(VMS)
• CC70116, V-Series C Compiler Operation Manual
(UNIX)
License Agreement
CC70116 is sold under terms of a license agreement that
must be completed and returned to NEC Electronics
before the C compiler is shipped. A copy of this license
agreement may be obtained from any NEC Electronics
Sales Office. Software updates are provided to registered users.
3
CC70116
4
NEe
NEe
DDK·70320
Evaluation Board
for V25 Microcomputer
NEG Electronics Inc.
Ordering Information
Description
The DDK-70320 is an evaluation board for NEC's
~PD70320 (V25 TM) 16-bit, single-chip microcomputer.
The DDK-70320 gives you maximum flexibility when
evaluating and designing with the ~PD70320. It features
a ~PD70320 with 32K bytes of EPROM, 32K bytes of
RAM, two RS-232C communication ports, and a powerful monitor program. The DDK-70320 is on an IBM PC
compatible card and includes a prototyping area for
building your application-specific hardware.
Part Number
Description
DDK-70320
~PD70320
Evaluation Board
V25 and V35 are trademarks of NEC Corporation.
PCJ)(T and PC AT are registered trademarks of International Business
Machines Corporation.
DDK-70320 Evaluation Board
A copy of RA70320, the V25N35™ Family Relocatable
Assembler package for use on an IBM PC, PCf)(T®, PC
AT®, or compatible host computer, is shipped with each
DDK-70320 to allow you to develop code for evaluation
purposes. Also included with the DDK-70320 is an emulator controller program for the IBM PC, a variety of
V-Series software utilities, a small demonstration program, and a complete set of documentation. This total
package provides you with a fast, efficient means for
evaluating the capabilities of the ~PD70320 for your
application.
Features
o
~PD70320
(V25) Evaluation Board with power supply
o On-board memory
- 32K-byte EPROM (user expandable to 64K bytes)
- 32K-byte RAM (user expandable to 64K bytes)
o Powerful on-board debug monitor
- Real-time and single-step operation
- Display/change memory and internal registers
- Display/change special-function registers
- Line assembler and disassembler
- Multiple software breakpoints
-Input/output from I/O ports
- User program downioad capability
o Two RS-232C serial interfaces
- One for a terminal or host computer
- One for auser application
o Prototyping area for user circuitry
o IBM PC card form factor
o RA 70320 V25N35 Relocatable Assembler package
o Host control software for IBM PC, PC/XT, PC AT, or
compatibles
o V-Series software uti lities and demonstration
programs
50228
Hardware
The DDK-70320 (figure 1) features 64K bytes of on-board
memory: 32K bytes of EPROM and 32K bytes of RAM.
The EPROM area, which is dedicated to a powerful
monitor program, can be expanded up 64K bytes. The
RAM area can also be expanded to 64K bytes and ~
contains the interrupt vector space, the monitor work
area, and a user area for program downloading.
1:6:1
A ~PD71051 serial communications controller is connected through an RS-232C driver/receiver to a DB25 pin
connector. The monitor uses this serial interface to
communicate with an external terminal or host computer. A second RS-232C channel is connected to serial
port 0 of the V25 for user applications.
A RESET switch returns the DDK-70320 to the power-up
state with or without losing the contents of the external
RAM. An NMI switch returns control to the monitor from
a user program while saving the user's state.
An ac/dc converter supplies power to the DDK-70320 in
the stand-alone mode. The DDK-70320 can also receive
its power directly from the IBM PC bus.
ODK-70320
Software
The DDK-70320 has 10 address breakpoints, which are
set in the GO command line. The monitor sets a breakpoint by substituting a BRK 3 instruction (opcode CCH)
for an instruction in the user's program.
The DDK-70320 comes with a powerful interactive monitor to facilitate software design using the p.PD70320. A
user program can be downloaded into user' RAM and
executed, in real-time with or without breakpoints, or it
can be executed one instruction at a time. During
single-stepping{ the registers, program counter, and the
next instruction to be executed are displayed.
Figure 1.
DDK-703~O
Additional commands are available to display, fill~
change,or move memory; display or change the generalpurpose' and special-funbtion registers; input from or
output to an 1/0 port; disassemble memory; assemble a
line of source code; and display the command list. Table
1 lists all of the DDK-70320 monitor commands.
Block Diagram
!
r--Address/Control Bus
EPROM
I
) Buffers
"I
-----
V25
System Bus
r--;,
Data Bus
'
"
"
Buffers
"
1
V25
l'
...
"I
-1
SRAM
UART
I
I
.A
...
") Expansion
Connector
'---83YL·6696B
Table 1. DDK-70320 Command Us,
RA70320 Relocatable Assembler
Command
Description
Package'
A
A(ssemble) a line of source ,code
D
D(ump) memory
The RA70320 Relocatable Assembler package converts
symbolic source code for NEC's V25N35 family of microcomputers into executable absolute address object
code. A copy of RA70320 is included with the DDK-70320
for use on an IBM PC; PC/XT, PC AT, or compatibles. With
this software, you can easily write evaluation programs
for the p.PD70320.,
E
E(nter) memory
F
F(ill) memory
G
G(o) with optional breakpoints
H
H,(elp) menu
I(nput) a byte from an I/O port
L
L(oad) a HEX file onto the DDK-70320
M
M(ove) a block of memory
o
O(utput) a byte to an I/O port
R
R(egister) display/alter R[reg]
S
S(pecial) function register display/alter
T
T(race) execution
U(nassemble) a block of rr\emory
?
H(elp) menu
Emulator Controller Program
Absolute address object files produced by the RA70320
Relocatable Assembler package can be downloaded to
the DDK-70320 using the NEC Emulator Con,troller program supplied with the ODK-70320. This controller program allows you to download files from your IBM PC or
compatible to the DDK-70320board.'The program provides the following additional capabilities.
• Complete DDK-70320 control from host 'console
• On-line help facilities
• Host system directory and file display
• Storage of debug session on disk'
2
~EC
DDK·70320
Documentation
For further information, refer to the DDK-70320 User's
Manual supplied with the evaluation board. Additional
copies may be obtained from NEC Electronics Inc.
License Agreement
RA 70320 is provided under the terms of a license agreement included with the DDK-70320 board. The accompanying card must be completed and returned to NEC
Electronics Inc. to register the license. Software updates
are provided to registered users.
3
DDK·70320
4
NEe
NEe
DDK·70330
Evaluation Board
for V3S Microcomputer
NEG Electronics Inc.
Description
The DDK-70330 is an evaluation board for NEC's
~PD70330 (V35™) 16-bit, single-chip microcomputer.
The DDK-70330 gives you the maximum flexibility when
evaluating and designing with the ~PD70330. It features
a ~PD70330 with 128K bytes of EPROM, 128K bytes of
RAM, two RS-232C communication ports, and a powerful monitor prog'ram. The DDK-70330 board includes a
prototyping area for building your application specific
hardware.
A copy of RA70320, the V25 ™N35 ™ Family Relocatable
Assembler package for use on an IBM PC, PCIXT@, PC
AT@, or compatible host C?omputer, is shipped with each
DDK-70330 to allow you to develop code for evaluation
purposes. Also included with the DDK-70330 is an emulator controller program for the IBM PC, a variety of
V-Series software utilities, a small demonstration program, and a complete set of documentation. This total
package provides you with a fast, efficient means for
eval uating the capabilities of the ~PD70330 for your
application.
Features
o ~PD70330 (V35) Evaluation Board with power supply
o On-board memory
- 128K-byte EPROM
-128K-byte RAM (user expandable to 512K bytes)
o Powerful on-board debug monitor
- Real-time and single-step operation
- Display/change memory and internal registers
- Display/change special-function registers
- Line assembler and disassembler
- Multiple software breakpoints
- Input/output from I/O ports
- User program download capability
o Two RS-232C serial interfaces
- One for a terminal or host computer
- One for a user application
o Prototyping area for user circuitry
o RA 70320 V25N35 Relocatable Assembler package
V25 and V35 are trademarks of NEC Corporation.
PC/XT and PC AT are registered trademarks of International Business
Machines CorporatIon.
50221
o Host control software for IBM PC, PCIXT, PC AT, or
compatibles
o V-Series software utilities and demonstration
programs
Ordering Information
Part Number
Description
DDK·70330
~PD70330
Evaluation Board
Hardware
The DDK-70330 (figure 1) features 256K bytes of onboard memory: 128K bytes of EPROM and 128K bytes of
RAM. The EPROM area includes a powerful monitor
program and a user area. The RAM area can be expanded to 512K bytes by replacing the 64K x 4 dynamic
RAMS with 256K x 4 dynamic RAMS. This RAM space
contains the interrupt vectors, the monitor work area,
and a user area for program downloading.
A ~PD72001 multiprotocal serial communications controller is connected through an RS-232C driver/receiver
to a DB25 pin connector. The monitor uses this serial
interface to communicate with an external terminal or
host computer. A second RS-232C channel is available
for connection to the second channel oft he ~PD72001 or
one of the serial ports of the ~PD70330 for user applications. DMA interface circuitry between the ~PD72001
and the V35 is provided to allow the you to evaluate the ~
DMA capabilities of both devices.
I:i:I
A RESET switch returns the DDK-70330 to the power-up
state with or without lOSing the contents of the external
RAM. An NMI switch returns control to the monitor from
a user program while saving the user's state. An ac/dc
converter supplies power to the DDK-70330.
NEe
DDK·70330
Figure 1. DDK-70330 Block Diagram
I
Expansion
PO-P2
I
Serial Ports
I
I
I
RS-232C
I
Serial VO
Options
I
I
I
Controls
V35
CPU
I
I
Control
Logic
DMALoglc
Options
I
I
High-Byte Data
1
DMAByte
Data Xaver
~
Serial
VO
I
Low-Byte Data
Address
Address
Demux
I
I
.t=;
~
" " - - 64K or 256K
DRAM
.t::::::j
~
.-
J-,..--
r---
-
I
Expansion
I
128K
EPROM
--83SL-6683B
2
NEe
DDK·70330
Software
RA70320 Relocatable Assembler Package
The DDK-70330 comes with a powerful interactive monitor to facilitate software design using the p.PD70330. A
user program can be downloaded into user RAM and
executed in real-time with or without breakpoints, or it
can be executed one instruction at a time. During
single-stepping, the registers, program counter, and the
next instruction to be executed are displayed.
The RA 70320 Relocatable Assembler package converts
symbolic source code for NEC's V25N35 family of microcomputers into executable absolute address object
code. A copy of RA70320 is included with the DDK-70330
for use on an IBM PC, PC/XT, PC AT, or compatibles. With
this software, you can easily write evaluation programs
for the p.PD70330.
The DDK-70330 has 10 address breakpoints, which are
set in the GO command line. The monitor sets a breakpoint by substituting a BRK 3 instruction (opcode CCH)
for an instruction in the user's program.
Additional commands are available to display, fill,
change, or move memory; display or change the generalpurpose and special-function registers; input from or
output to an I/O port; disassemble memory; assemble a
line of source code; and display the command list. Table
1 lists all of the DDK-70330 monitor commands.
Table 1. DDK-70330 Command Us,
Command
Description
A
A(ssemble) a line of source code
D
D(ump) memory
E
E(nter) memory
F
F(ill) memory
G
G(o) with optional breakpoints
H
H(elp) menu
I (nput) a byte from an I/O port
L
L(oad) a HEX file onto the DDK-70330
M
M (ove) a block of memory
0
O(utput) a byte to an I/O port
R
R(egister) display/alter R[reg]
S
S(pecial) function register display/alter
T
T(race) execution
U
U(nassemble) a block of memory
?
H(elp) menu
Emulator Controller Program
Absolute address object files produced by the RA70320
Relocatable Assembler package can be downloaded to
the DDK-70330 using the NEC Emulator Controller program supplied with the DDK-70330. This controller program allows you to download files from your IBM PC or
compatible to the DDK-70330 board. The program provides the following additional capabilities.
•
•
•
•
Complete DDK-70330 control from host console
On-line help facilities
Host system directory and file display
Storage of debug session on disk
Documentation
For further information, refer to the DDK-70330 User's
Manual supplied with the evaluation board. Additional
copies may be obtained from NEC Electronics Inc.
License Agreement
RA 70320 is provided under the terms of a license agreement included with the DDK-70330 board. The accompanying card must be completed and returned to NEC
Electronics Inc. to register the license. Software updates
are provided to registered users.
3
II
•
DDK·70330
4
~EC
NEe
NEC Electronics Inc.
Description
The IE-70136 is a portable, stand-alone, in-circuit emulator that provides hardware emulation and softwa:re
debug capabilities for the ItP070136 (V33 TM) 16-bit microprocessor.
Real-time and single-step emulation-coupled with software performance analysis, sophisticated memory mapping, symbolic debugging, macrofile command facilities, user-programmable breakpoints and trace
qualifiers-create a powerful development environment.
Command entry is simplified by eight dynamically reprogrammed function keys, called softkeys, that visually
prompt a user with the next level of commands. User
programs can be uploaded/downloaded from a variety of
host systems by a serial link or they can be loaded
directly from an MS-OOS® disk.
Features
o Portable, stand-alone, in-circuit emulator
- 9.5-inch amber CRT display
- Two 5-inch, 640K-byte floppy-disk drives
- ASCII keyboard with eight function keys
- EPROM programmer: 2732, 2764, 27128, 27256,
27512
- Supports NEC's V20®, V30®, V25 TM, V35 TM, V40 ™,
V50 TM, V53 ™ , and V60 ™ microprocessors
o Precise real-time and single-step emulation
- Selectable internal clock: 8 MHz or 16 MHz
- Up to 16-MHz external TTL clock
o Emulation memory bus size selection
o 256K bytes of memory for prototype memory
emulation; mappable into 16M-byte address space in
4K-byte units
o Automatic break with disconnected target I/O
access
o Six user-programmable hardware breakpoints
- Real-time break on address, data, CPU status, or
external input
- Selectable as execution or nonexecution
o 256 user-programmable software breakpoints
V20 and V30 are registered trademarks of NEC Corporation.
V25, V33, V35, V40, V50, V53, and V60 are trademarks
of NEC Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
50224
IE-70136
In-Ci rcuit Emulator
for pPD70136 (V33) Microprocessor
o Trace buffer: disassemble, frame, and code trace
display
- 8192 frames by 64 bits
- Programmable enable/disable points
o Performance modes avai lable for software
performance evaluation: time interval, module
activity, and count modes
o Full symbolic debug capabilities
o Symbolic line assembler and disassembler
o Macrofile command capability
o Dual window display in emulation mode
o Softkey and menu-driven user input
o System commands are available while in emulation
mode
Ordering Information
Part Number
Description
IE-70136-A016
In-circuit emulator for p.PD70136 (V33)
EP-70136L-A
68-pin PLCC/PGA emulation probe/socket
EP-70136GJ-A
74-pin plastic QFP emulation probe
HARDWARE DESCRIPTION
The IE-70136 (figure 1) consists of a system chassis with
a detachable ASCII keyboard and an emulation pod unit.
The chassis houses a 9.5-inch amber CRT, two 5-1/4
inch, 640K-byte floppy-disk drives, an EPROM programmer, a card cage, a power supply, and three control
boards. T, he boards are main CPU, expansion system . . ,
memory, and emulation pod interface.
~
The main CPU board contains a supervising CPU, 512K
bytes of system memory, and the peripheral interfaces.
The expansion system memory board provides an additional 512K bytes of system memory.
The em41ation pod interface contains the clock selection
logic, emulation bus sizing switch, and enabling of the
ROY and 8S8/8S16 signals from the target to emulator
memory. The emulation pod contains the V33 EVACHIP,
external event input, trigger out, and target interface.
This' unit connects to the target system by the EP70136L-A emulation probe forthe 68-pin PLCC/PGA For
the 74-pin plastic QFP, an EP-70136GJ-A probe adapter
is also needed.
NEC
IE-70136
The IE-70136 supports the following external interfaces:
two RS-232C serial ports, one Centronics parallel printer
port, and one RG B video output.
The emulator can be converted to support NEC's V20,
V25, V30, V35, V40, V50, V53, and V60 CMOS microprocessors by exchanging the appropriate control boards
and the emulation pod unit.
Figure 1. IE-70136 System Configuration
The target NMI and INT signals may be enabled or
disabled by the Configure command.
Emulation
The IE-70136 executes #,PD70136 user programs in real
time in three different modes: break, trace, and performance. In break emulation mode, 'the program is run in
real time or in single-step mode until a breakpoint is
encountered. In trace emulation mode, the program is
executed in real time while filling the trace buffer with
bus information.
In performance emulation mode, the emulator. can:
Memory and I/O Mapping Capabilities
The IE-70136 contains 256K bytes of zero wait-state
emulation memory; 252K bytes are available for emulating target RAM (read/write) or ROM (read only) and the
remaining 4K bytes are reserved for use by the system
monitor.
The complete 16M-byte memory space of the #,PD70136
must be mapped into one of the following categories.
Target
ROM
RAM
Locked
Memory resident in target system (read/
write)
External ROM emulation memory (read
only)
External RAM emulation memory (read/
write)
Access inhibited memory (remaining
unmapped addresses)
All memory mapping is executed in 4K-byte blocks using
the Configure and Mapping softkey commands. If an
address mapped as "Iocked" is accessed or a write i.s
attempted to ROM, a break in the emulation will occur.
The I/O space of the #,PD70136 is always mapped to the
target. If the probe is not connected to a target system, a
break will occur in emulation when any target I/O is
accessed.
2
(1)
Measure the execution time between enable and
disable points
(2)
Measure the accumulated execution time in three
areas of memory and then display the ratio of time
spent within each area in both absolute and relative terms
(3)
Count the number of times a particular trigger
point is satisfied between enable and disable
points.
Once emulation is stopped in either break or trace mode,
the trace automatically displays one screen of data,
ending on the laslinstruction executed. In performance
mode, time is shown in a table and in a bar graph. At this
point, it is possible to display the contents of memory,
the general-purpose and special registers, the symbol
tables, directories, and other information. All can be
displayed individually or in split screen with the trace
display. The windows may be scrolled independently.
Break Capabilities
The IE-70136 has six hardware breakpoints. Five can be
set to occur in· response to a real-ti me event with the
BCond command. The remaining one is reserved for
setting a real-time address (execution only) breakpoint
with the GO command.
You can use the BCond command to set breakpoints to
occur on an address, a data value, or a CPU state.
Hardware breakpoints can be either an execution or
nonexecution type. An execution break occurs when an
instruction is clocked into the execution unit of the V33.
A nonexecution break occurs when the bus condition is
satisfied regardless of the status of the instruction
queue.
An enable and disable point can also be specified to
indicate when detection of hardware break and trace is
to start and stop. If not specified, trace and break
detection is enabled when the GO command is exe-
t-IEC
cuted. The external channel can also be used to create
a breakpoint. Either the rising or falling edge can be
selected.
'
Up to 256 software breakpoints can be set plus an
additional one in the GO command. To set a software
breakpoint, the emulator replaces an instruction in the
user's program with a BRK 0 instruction. A break will
occur when this instruction is executed, and the user's
program will be restored. This capability is not available
for program code executing out of ROM. A Check command is provided to verify that the breakpoint can
actually be set.
Trace Capabilities
The trace buffer is 8192 frames by 64 bits wide and
sampling is done on every machine cycle. The buffer is
filled in round-robin fashion. The emulator traces the
external address and data buses, the CPU and queue
status, and control signals.
The IE-70136 has five trace trigger pOints. When the
trigger condition is true, a positive logic pulse is output
on the TRIGGER OUT pin of the emulator pod. Separate
ENABLE and DISABLE points can be set to restrict
tracing pr trigger detection to a particular section of
program code. If not used, tracing and trigger detection
will be enabled when the GO command is issued. An
address point can be set with the GO command to
record the trace after, about, or before the condition is
true. The external input can also be used as a trigger
point. Either a positive or negative edge can be specified.
The trace data may be displayed in one of three modes:
disassembly, frame, or code. In disassembly mode, fetch
and execution cycles are displayed separately, and bus
cycles are rearranged so that a fetch cycle and its
associated execution cycle are displayed next to each
other. In frame mode, the CPU bus cycle conditions are
displayed as traced. In code mode, only the executed
fetch cycles are displayed. In disassembly and code
modes, the fetch cycle is displayed bright, the execution
cycle is dim, and a trigger point is indicated by reverse
video.
IE·70136
Run-Time Interval Mode. Execution time from the enable point to the disable point is repeatedly measured,
and the mean value, the maximum value, the minimum
value, and the distributed values are stored. The measured distribution values, from a maximum of six time
intervals, can be displayed graphically.
Module Activity. The accumulated execution time for
three areas of code (from enable to disable points) can
be measured. The ratio of time spent in each one
compared to the total measured time (ABS) and the ratio
of time spent in each one compared to the time spent in
all three areas (REL) can be displayed. If the overall
processing speed does not satisfy the desired speed,
the portion of the code taking more time can be determined and improved. This mode can be very effective for
increasing total throughput.
Count Mode. The number of times a trigger point is
satisfied within an area of code (from enable to disable
points) can be counted. Up to four trigger points can be
set and the ratio of the number of times each trigger
point is satisfied to the total number of all triggers is
displayed.
Address Specification
An address can be specified as either a 24-bit absolute
address (beginning with a ;) or as a segment:offset
address. Segment:offset addresses can be either physical, addressing only the base 1M byte, or logical. Logical
addresses are converted to 24-bit physical addresses by
the emulator according to the address extension table
(EXPAND TABLE) specified by the SEText command.
There are two types of expand tables. One uses the MMU
(Memory Management Unit) in the CPU. However, conversion is done only during a break if the XA flag is set. . . ,
Otherwise, no conversion is performed. A user-defined
expand table is independent of the MMU. This table is
defined by loading the extended linker locator output file
(EL70136), by definition in the program stage, or by
copying the contents of the MMU. With the user-defined
table,:conversion is performed regardless of the status of
the XA flag.
1:6:.1
SOFTWARE DESCRIPTION
If the user-defined expand table is selected, conversion
back to logical address is performed according to this
table when displaying trace results in disassembly mode.
Software Performance Analysis
System Software
Using the IE-70136, software performance can be evaluated in real-time in anyone of three different modes:
run-time interval mode, module activity mode, and count
mode. Improvements in software performance can be
statistically measured.
The IE-70136 is controlled by the MIOS/U proprietary
operating system. Command input is simplified by eight
function keys, providing a choice of up to 24 softkeys
within any menu level. The dynamically reprogrammed
softkeys visually prompt with the next valid set of com-
3
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IE·70136
mands. The softkeys are at the bottom of the display
screen and correspond to the eight function keys on the
keyboard. To select a command, press a softkey. The
softkeys are automatically relabeled with the next set of
commands.
All system functions can be used in emulator mode. The
IE-70136 system software uses an overlay method so
that a necessary program is loaded when a command is
input and then executed. File handling, communications, and PROM writing can be performed during emulation, reducing development time.
Table 1 shows some of the utility programs provided with
the emulator.
that runs in the emulator itself and is supplied as part of
the IE-70136 package. The Multiple File Handler allows
the emulator to read MS-DOS disks, among others.
Symbolic Debug and Line Assembly!
Disassembly
The IE-70136 supports complete symbolic debugging of
programs produced by NEC's RA70136 Relocatable Assembler Package and various third-party software packages, including those from Intel and Microsoft. The
symbols can be used as address and data constants in
break, trace, and emulation control commands and are
displayed during disassembly. A symbolic line assembler
is also available to make modifications to existing programs or to enter code from the keyboard.
Table 1. IE-70136 Utility Programs
Utility
Function
SPECIFICATIONS
EMUV35
IE-70136 emulator software
KERMIT
Communication program for file transfer
Table 2 gives the electrical, environmental, and physical
specifications of the equipment.
FI LESEFW
File management for system disks
EDITOR
Full screen editor
FORMAT
PROM
Floppy-disk formatter
Built-in EPROM programmer control program
TERMINAL Terminal utility program for file transfer between
emulator and another intelligent device
SYMBOL
Symbol table converter; converts non-SROC symbol
formats to SROC format
o BJCONV
Object fi Ie converter: converts object files to and from
the Motorola SROC format
TIMESET
Internal battery backed-up clock and calendar setting
DE FINE
Soft key definition
MDEVICE
Disk format specification
Connecting to Host Systems
Host systems may be connected to the IE-70136 using
the RS-232C connectors at the rear of the machine.
Parameters such as baud rates, character length, parity,
and number of stop bits are software programmable to
suit the system being attached. The KERMIT communications program is supplied with the emulator and can
be used for uploading and downloading files. NEC currently provides KERMIT for the VAX® under VMS® and
UNIXTM 4.2BSD or Ultrix™, the IBM PC, IBM PC/XT®, IBM
PC/AT®, or compatibles under PC-DOS® or MS-DOS.
Files may also be transferred to the emulator via the
RS-232C ports using the TERMINAL utility. The emulator
acts as a terminal for data transfer.
Another means of loading files into the IE-70136 is
available with the Multiple File Handler utility, a program
4
Table 2.
IE-70136 Specifications
AC power
Temperature
90 to 132 V, 50/60 Hz, 400 W maximum
Operating: +5 to +40°C
Storage: -20 to +50°C
Relative humidity
(noncondensing)
Weight
Operating: 20 to 80%
Storage: 10 to 90%
Main chassis: 40 pounds
Pod and cables: 4-3/4 pounds
Dimensions (L x W x H)
19.7 x 16.7 x 8.7 inches
DOCUMENTATION
The following manuals are supplied with the in-circuit
emulator. Additional copies may be obtained from NEC
Electronics Inc.
• IE-70136 In-Circuit Emulator User's Manual
• IE-70XXX-A Hardware User's Manual
• IE-70XXX-A Software Utilities User's Manual
VAX and VMS are registered trademarks of Digital Equipment
Corporation.
Ultrix is a trademark of Digital Equipment Corporation.
UNIX is a trademark of AT&T.
PC/XT, PC AT, and PC-DOS are registered trademarks of International
Business Machines Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
t\'EC
IE-70136-PC
In-Ci rcuit Emulator
for pPD70136 (V33) Microprocessor
Description
o User-programmable software breakpoints
- 100 logical/physical address breakpoints
maximum
- Forced break possible
NEG Electronics Inc.
The IE-70136-PC is a low-cost in-circuit emulator that
provides hardware emulation and software debug capabilities for the NEC ILPD70136 (V33™) 16-bit microprocessor. It is designed to be used with an IBM PC, PC/XT®,
PC AT®, or compatible machine under PC-DOS® or
MS-DOS®.
o Memory display/fill/move capability in byte or word
format
- Access to normal or extended memory
- Disassembler
Features
o Macro/batch processing capabilities
o Interfaces to host PC via a parallel interface
- PC interface card and cable included
o Direct access to PC-DOS and MS-DOS system
commands
o Real-time and single-step emulation
-16-MHz internal clock
- 2- to 16-MHz external clock
- 65,535 instructions can be stepped in single
command
o LED displays for CPU status: RUN, NOREADY,
HOLD, HALT
o Load/Save programs using Extended CO F F, NEC
LN K, Intel Extended HEX, and Motorola SROC
formats
DOne 64K-byte block of emulation memory
o Four user-programmable breakpoints
- Real-time break on address during instruction
fetch, data memory read/write, or I/O read/write
V33 is a trademark of NEC Corporation.
IBM PC, PC/XT, PC AT, and PC-DOS are registered'trademarks of
International Business Machines Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
Figure 1. IE-70136-PC System Configuration
50225
Ordering Information
Part Number
Description
IE-70136-PC
In-circuit emulator for
EP-70136L-PC
68-pin PLCC/PGA emulation probe/socket
~PD70136/70332
IE· 70i36·PC
2
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NEC Electronics Inc.
IE·70208, IE-70216
In-Circuit Emulators
for pPD70208 (V40) and pPD70216 (V50)
Microprocessors
Description
The IE-70208 and.IE-70216 are portable, stand-alone,
in-circuit emulators providing both hardware emulation
and software debug capabilities for the NEC p.PD70208
(V40TM) and p.PD70216 (V50™) 16-bit microprocessors.
Real-time and single-step emulation in both native and
8080 emulation modes-coupled with sophisticated
memory mapping, user-programmable breakpoints and
trace qualifiers, symbolic debug, and macrofile command facilities-create a powerful development environment.
Command entry is simplified by eight dynamically reprogrammed function keys, called softkeys, that visually
prompt the user with the next level of commands. User
programs can be uploaded/downloaded from a variety of
host systems by a serial link or loaded directly from an
MS-DOS® disk.
Features
o Portable, stand-alone, in-circuit emulator
- 9.5-inch amber CRT display
- Two 5-inch, 640K-byte floppy-disk drives
- ASCII keyboard with eight function keys
- EPROM programmer: 2732, 2764, 27128, 27256,
27512
- Supports NEC's V20®, V25 TM, V30®, V33 ™, V35 ™,
V53 ™, and V60 ™ microprocessors
o Precise real-time and single-step emulation
- Programmable internal clock: 2 to 10 MHz in
1-kHz steps
- External clock: 2 to 10 MHz
o Memory and I/O space mappable in 1K-byte blocks
o 256K bytes of memory for prototype memory
emulation; expandable to 768K bytes
o Eight user-programmable hardware breakpoints
- Real-time break on address, data, CPU status, or
external probes
- Break on pass count and register, memory, or I/O
values
- Selectable as execution or code fetch break
o 16 user-programmable software breakpoints
V20 and V30 are registered trademarks of NEC Corporation
V25. V33. V40. V50, V53. and V60 are trademarks of NEC Corporation
50227
o Trace buffer: machine cycle, mnemonic, and jump
trace display
-1024 frames by 64 bits
- Programmable trigger point and trace qualifiers
o Eight optional probes for tracing target system
signals
o Full symbolic debug capabilities
o Symbolic line assembler and disassembler
o Macrofile command capability
o Dual window display in emulation mode
o Softkey and menu driven user input
Ordering Information
Part Number
Package
IE-70208-A010
In-circuit emulator for ~PD70208 (with V40 pod)
IE-70216-A010
In-circuit emulator for #,PD70216 (with V50 pod)
IE-70000-2958
68-pin PLCC package emulation probe
IE-70000 -2959
68-pin PGA package emulation probe
IE-70208-2010
Optional pod unit for ~PD70208 emulation
IE-70216-2010
Optional pod unit for ",PD70216 emulation
IE-70000-2954
Optional external logic probe.
IE-70000-2957
Optional 512K-byte expansion emulation
memory
HARDWARE DESCRIPTION
The IE-70208/216 (figure 1) consists of a system chassis
with a detachable ASCII keyboard and an emulation pod
unit. The chassis houses a 9.5-inch amber CRT, two 5-1/4
inch 640K-byte floppy disk drives, an EPROM programmer, card cage, power supply, and three control boards.
The boards are main CPU, emulation control, and traceemulation memory.
The main CPU board contains the supervising CPU,
512K bytes of system memory, and the peripheral interfaces. The emulation control board controls the memory
mapping, event detection, and the break and emulation
CPU status circuitry. The trace-emulation board contains a trace buffer and 256K bytes of external emulation
memory. The optional IE-70000-2957, a 512K-byte expanSion emulation memory board, may be installed to
increase the external emulation memory to 768K bytes.
ftI
a:.I
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IE-70208, ·1 E"70216
The external emulation pod unit houses the emulation
CPU, high-speed buffers, and clock selection logic. The
emulation pod unit can be connected to the target
system with one oftwo emulation probes: IE-70000-29S8
supports the 68-pin PLCC package and the IE-7000029S9 supports the 68-pin PGA package. These probes
are ordered separately.
Memory and I/O Mapping Capabilities
The IE-70208/216 contains 256K bytes (expandable to
768K bytes) of emulation RAM (0 wait states) for emulating external RAM or ROM. The complete 1M-byte
memory space of the #tPD70208/70216 must be mapped
into one of the following categorie~ of memory:
The IE-70208/216 supports the following external interfaces: two RS-232C serial ports, one Centronics parallel
printer port, an RG B video output, and eight optional
external logic probes. These probes (IE-70000-29S4) can
be used for tracing and/or breaking on signals from the
target system.
Target
Ease of migration within the V-Series family 91. emulators
is provided in the system design. To alternate between
V40 and VSO emulation simply requires changing the
emulation pod unit. The emulator can also be converted
to support the V20, V2S, V30, V33, V3S, VS3, and· V60
CMOS microprocessors by exchanging the appropriate
control boards and the emulation pod unit.
Locked
Figure 1. IE-70208/216 System Configuration
ROM
RAM
Memory resident in target system
(read/write)
External ROM emulation memory
(read only)
External RAM emulation memory
(read/write)
Access inhibited memory
(remaining unmapped addresses)
All memory mapping is done in 1K-byte blocks using the
Configure and Memory softkey commands. If an address
mapped as "Iocked" is accessed, a break in the emulation
will occur.
The complete 64K-byte I/O space ofthe #tPD70208/70216
must be mapped in 1K-byte blocks to the emulation
memory, the target system, or as "Iocked" memory.
Emulation
The IE-70208/216 executes #tPD70208 and #tPD70216
user programs in real~time in four different modes: break,
trace, count, and time.
2
(1)
In break emulation mode, the user's program is
executed in real-time or in single-step until a breakpoint is encountered.
(2)
In trace emulation mode, the user's program is
executed until the trace buffer is filled.
(3)
During the count emulation mode, the emulator
counts the number of times a particular trigger
point is reached within a given set of conditions.
(4)
In time emulation mode, the emulator measures
execution time between the specified enable and
disable points. The measurable time range is from 0
to 72 minutes (in microseconds).
NEe
Once emulation is stopped in either break ortrace mode,
the trace automatically displays one screen of data,
ending on the last instruction executed. In count or time
mode, the current count or elapsed time is displayed. At
this point, it is possible to display the contents of
memory, the general-purpose and· special registers, the
symbol tables, directories, and other information. All can
be displayed individually or by split screen with the trace
display. The windows may be scrolled independently.
Prior to the start of emulation, the user can specify
whether an external or internal clock will be used for
~mulation, whether the internal or external ready sigDal
IS used, and whether the NMI signal from the target
system should be enabled or disabled. If the internal
clock is used, it can be set from 2 to 10 MHz in 1-kHz
steps.
Break Capabilities
The IE-70208/216 has eight hardware breakpoints. Seven
can be set to occur on a real-time event or a nonreal-time condition. The remaining one is reserved for
setting a real-time address breakpoint in the GO
command.
A real-time breakpoint can be set to occur on an address,
a data value, a CPU state, or the external probe status.
A non-real-time breakpoint can be set to occur after
satisfying an address/condition setting a certain number
of times (maximum 4096).
Conditions pertaining to the general-purpose registers,
memory locations, I/O locations or the external probes
can be defined. For non-real-time breakpoints, the user
program is executed in real time until it reaches the
address, then emulation pauses while the conditions are
checked. If the conditions are not satisfied, emulation
will continue in this manner until they are met.
To distinguish between the condition occurring at an
op-code fetch or at the execution of an instruction, each
breakpoint can be tagged with either a nonexecution or
execution flag.
IE· 70208, IE· 70216
Trace Capabilities
The trace buffer is 1024 frames by 64 bits wide and
sampling is done on every machine cycle. The buffer is
filled in a round-robin fashion. The emulator traces the
external address and data buses, the CPU and queue
status, and the eight external logic probes.
The IE-70208/216 has eight trace specification points.
One of these is reserved for setting a trigger point in the
GO command. The other seven can be specified as trace
trigger,enable, disable, qualify, or check points. Check
points are used to display register, memory, or I/O
contents each time a certain event or address occurs.
The trace buffer can be split into a maximum of 64
partitions to allow tracing of particular segments of the
user program (Le., subroutines).
The trace data may be displayed in one of three modes:
machine, disassembly, or jump. In machine display
mode, all bus activity is displayed in machine code. In
disassembly mode, all instructions are disassembled. In
jump mode, only instructions that alter program flow are
displayed.
SOFTWARE DESCRIPTION
System Software
The IE-70208/216 is controlled by the MIOS/U proprietary operating system. Command input is simplified by
eight function keys (providing a choice of up to 24
softkeys within any menu level). The dynamically reprogrammed soft keys visually prompt with the next valid set
of commands. The softkeys are at the bottom of the
display screen and correspond to one of the eight
function keys on the keyboard. To select a command,
press a softkey. The softkeys are automatically relabeled
with the next set of commands.
Table 1 lists the utility programs provided with the
emulator.
Up to 16 software breakpoints can be set plus an
additional one in the GO command. To set a software
breakpoint, the emulator replaces an instruction in the
user's program with a BRK 0 instruction. A break will
occur when this instruction is executed, and the user's
program will be restored. This capability is not available
for program code executing out of ROM.
3
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IE-70208,IE·70216
Table 1. IE-7020B/216 Utility Programs
Utilities
Function
EMUV4050
IE-70208/216 emulator software
KERMIT
Communication program for file transfer
FILESEFN
File management for system disks
EDITOR
Full screen editor
FORMAT
Floppy-disk formatter
PROM
Built-In EPROM programmer control program
TERMINAL
Terminal utility program for file transfer between
emulator and another intelligent device
SYMBOL
Symbol table converter; converts non-SROC
symbol formats to SROC format.
OBJCONV
Object file converter; converts object files to
and from the Motorola SROC format.
TIMESET
Internal battery backed-up clock and calendar
setting
Symbolic Debug and Line Assembly/
Disassembly
The IE-70208/216 supports complete symbolic debugging of programs produced by NEC's RA70116 Relocatable Assembler Package and various other third-party
software packages, including those from Intel and Microsoft. The symbols can be used as address and data
constants in break, trace, and emulation control commands and are displayed during disassembly. A symbolic line assembler is also available to make modifications to existing programs or to enter code from the
keyboard.
SPEC IFICATIONS
Table 2 gives the electrical, environmental, and physical
specifications of the equipment.
DEFINE
Softkey definition
Table 2. IE-7020B/216 Specifications
MDEVICE
Disk format specification
AC power
90 to 132 V, 50/60 Hz, 400 W maximum
Temperature
Operating: +5 to +40°C
Connecting to Host Systems
Host systems may be connected to the IE-70208/216 via
the RS-232C connectors at the rear of the machine.
Parameters such as baud rates, character length, parity,
and number of stop bits are software programmable to
suit the system being attached. The KERMIT communications program supplied with the emulator can be used
for uploading and downloading files. Currently, NEC
provides KERMIT for the VAX® under VMS® and UNIXTM
4.2 BSD or Ultrix™, and the IBM PC, PC/XT®, PC AT®, or
compatibles under PC-DOSTM or MS-DOS®.
Files may also be transferred to the emulator via the
RS-232C ports by using the TERMINAL utility. The emulator acts as a terminal for data transfer:
Another means of loading files into the IE-70208/216 is
available with the Multiple File Handler utility, a program
that runs in the emulator itself and is supplied as part of
the IE-70208/216 package. The Multiple File Handler
allows the emulator to read MS-DOS disks, among
others.
VAX and VMS are registered trademarks of Digital Equipment
Corporation.
Ultrix is a trademark of Digital Equipment Corporation.
UNIX is a trademark of AT&T.
PCIXT, PC AT, and PC-DOS are registered trademarks of International
Business Machines Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
4
Storage: -20 to +50°C
Relative humidity
(noncondensing)
Weight
Operating: 20 to 80%
Storage: 10 to 90%
Main chassis: 40 pounds
Pod and cables: 4-3/4 pounds,
Dimensions (L x W x H)
19.7 x 16.7 x 8.7 inches
DOCUMENTATION
The following manuals are supplied with the in-circuit
emulator. Additional copies may be obtained from NEC
Electronics Inc.
• IE-70208/216 In-Circuit Emulator User's Manual
• IE-70XXX-A Hardware User's Manual
• IE-70XXX-A Software Utilities User's Manual
~EC
NEC Electronics Inc.
IE-70320
In-Ci rcuit Emulator
for pPD70320/70322 (V2S) Microcomputers
Description
o 16 user-programmable software breakpoints
The IE-70320 is a portable, stand-alone, in-circuit emulator that provides hardware emulation and software
debug capabilities for the NEC jtPD70320/70322 0125 TM)
16-bit, single-chip microcomputers.
o Trace buffer: machine cycle, mnemonic, and jump
trace display
- 2047 frames by 108 bits
- Programmable trigger point and trace qualifiers
Real-time and single-step emulation, coupled with sophisticated memory mapping, symbolic debugging,
macrofile command facilities, and user-programmable
breakpoints and trace qualifiers create a powerful development environment.
o Eight optional probes for tracing of target systems
signals
Command entry is simplified by eight dynamically reprogrammed function keys, called softkeys, that visually
prompt a user with the next level of commands. User
programs can be uploaded/downloaded from a variety of
host systems by a serial link or they can be loaded
directly from an MS-DOS® disk.
Features
o Portable stand-alone in-circuit emulator:
- 9.5-inch amber CRT display
- Two 5-inch, 640K-byte floppy-disk drives
- ASCII keyboard with eight function keys
- EPROM programmer: 2732, 2764, 27128, 27256,
27512
- Can be converted to support NEC's V20®, V30®,
V33 TM, V35 TM, V40 TM, V50 TM, V53 ™ , and V60 ™
microprocessors
o Precise real-time and single-step emulation
- Programmable internal clock: 1 to 16 MHz in
1- kHz steps
- Up'to 16 MHz external TTL clock
o Memory and I/O space mappable in 4K-byte blocks
o 32K bytes of memory for-internal ROM emulation
o 124K bytes of memory for prototype memory
emulation; expandable to 636K bytes
o Eight user-programmable hardware breakpOints
- Real~time break on address, data, CPU status, or
external probes
- Break on pass count and register, memory, or I/O
values
- Selectable as execution or nonexecution
V20 and V30 are registered trademarks of NEC Corporation.
V25, V33, V35, V40, V50, V53, and V60 are trademarks of
NEC Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
50229
o Full symbolic debug capabilities
o Symbolic line assembler and disassembler
o Macrofile command capability
o Dual window display in emulation mode
o Soft key and menu-driven user input
Ordering Information
Part Number
Package
IE-70320 -AOOS
In-circuit emulator for MPD70320/70322
IE-7032'b-RTOS
MPD79011 RTOS System Software for IE-70320
EP-70320L
MPD70320/70322 84-pln PLCC emulation probe
IE-70000 -2957
Optional 512K-byte expansion emulation
memory
IE-70000 -2954
Optional external logic probes
EP-70320GJ
Optional 94-pln plastic QFP package probe
adapter for use with EP-70320L
Hardware
The IE-70320 (figure 1) consists of a system chassis with
a detachable ASCII keyboard and an emulation pod unit.
The chassis houses a 9.5-inch amber CRT, two 5-1/4 inch
640K-byte floppy-disk drives, an· EPROM programmer,
card cage, power supply, and five control boards. The
boards are main CPU, expansion system memory, emulation control I and II, and trace emulation memory.
The main CPU board contains a supervising CPU, 512K
bytes of system memory, and the peripheral interfaces.
The expansion system memory board provides an additional 512K bytes of system memory.
The two emulation control boards control memory mapping, event detection, and the break and emulation CPU
status circuitry. The trace emulation board contains a
trace buffer and 124K bytes of external emulation memory. The optionaIIE-70000-2957, a 512K-byte expansion
emulation memory board, may be installed to increase
the external emulation memory to 636K bytes.
~
~
NEe
IE·70320
The emulation pod unit houses the I!-PD70329 EVACHIP
used to emulate the I!-PD70320 or I!-PD70322, the internal
ROM emulation memory, the high-speed buffers, and the
clock selection logic. This unit can be connected to the
target system by the EP-70320L, an emulation probe for
the 84-pin PLCC. For the 94-pin plastic QFP package, an
EP-70320GJ probe adapter is also needed.
INTROM
ROM
RAM
Target
Internal I!-PD70322 ROM emulation memory
(0, 8, 16, or 32K bytes selectable)
External ROM emulation memory
(read only)
External RAM emulation memory
(read/write)
Memory resident in target system
(read/write)
Access inhibited memory
(remaining unmapped addresses)
The IE-70320 supports the following external interfaces:
two RS-232C serial ports, one Centronics parallel printer
port, and one RG B video output.
Locked
An optional external logic probe unit (lE-70000-2954) is
also available . The eight probes contained in the unit
allow signals on the target system to be used in the
break and trace functions.
All memory mapping except INtrom is executed in 4K..
byte blocks using the CONFIGure and MEMory softkey
commands. If an address that has been mapped as
"locked" is accessed, a break in emulation will occur.
The emulator can be converted to support NEC's V20,
V30, V33, V35, V40, V50, V53, or V60 CMOS microprocessors by exchanging the appropriate control boards and
the emulation pod unit. .
The complete 64K-byte input/output space of the
I!-PD70320 or I!-PD70322 must be mapped in 4K-byte
blocks eitherto the RAM emulation memory, to the target
system, or as "locked" memory.
Figure 1. IE-70320 System Configuration
Emulation
The IE-70320 executes I!-PD70320 and I!-PD70322 user
programs in real time in four different modes: break,
trace, count, and time.
(1)
In break emulation mode, the program is runin real
or in single step until a breakpoint is encountered.
ti~e
Memory and I/O Mapping Capabilities
The IE-70320 contains two kinds of emulation memory:
32K bytes of high-speed RAM that can be accessed in
one clock cycle per byte for emulating the internal ROM
of the I-l-PD70322, and 124K bytes (expandable to 636K
bytes) of two-cycle RAM (0 wait states) for emulating
external RAM or ROM.
The complete 1M-byte memory space of the I!-PD70320/
I!-PD70322 must be mapped into one of the following
categories:
2
(2)
In trace emulation mode, the program is executed
until the trace buffer is filled.
(3)
In count emulation mode, the emulator counts the
number of times a particular trigger pOint is
reached within a given set of conditions.
(4)
In time emulation mode, the emulator times execution between the specified enable and disable
points. The measurable time range is from 0 to 72
minutes (in microseconds).
Once emulation is stopped in either break or trace mode,
the trace automatically displays one screen of data,
ending on the last instruction executed. In count or time
mode, the current count or elapsed time is displayed. At
this point, it is possible to display the. contents of
memory, the general-purpose and special registers, the
symbol tables, directories, and other infqrmation. All can
be displayed individually or by split screen with the trace
display. The windows may be scrolled independently.
NEe
Prior to the start of emulation, the user can specify the
internal ROM size (if any), whether an external or internal clock will be used for emulation, and whether the
NMI, READY, and HOLD signals from the target system
should be enabled or disabled. If the internal clock is
used, it can be set from 1 to 16 MHz in 1-kHz steps.
Break Capabilities
The IE-70320 has eight hardware breakpoints. Seven can
be set to occur on a real-time event or a non-real-time
condition. The remaining one is reserved for setting a
real-time address breakpoint in the GO command.
A real-time breakpoint can be set to occur on an address,
a data value, a CPU state and an external probe status.
A non-real-time breakpoint can be set to occur after an
address/condition setting has been satisfied for a certain number of times (maximum 4096).
Conditions pertaining to the general-purpose registers,
memory locations, input/output locations, or external
probes can be defined. For non-real-time breakpoints,
the user program is executed in real time until it reaches
the break address. Emulation stops while the conditions
are checked. If the conditions are not satisfied, emulation will continue in this manner until they are met.
IE·70320
dress occurs. The trace buffer can be split into a maximum of 128 partitions to allow tracing of particular
segments of the user program (i.e., subroutines).
The trace data may be displayed in one of three modes:
machine, disassembly, or jump. In machine display
mode, all bus activity is displayed in machine code. In
disassembly mode, all instructions are disassembled. In
jump mode, only instructions that alter program flow are
displayed.
IE-70320 -RTOS System Software
The optionaIIE-70320-RTOS system software allows the
IE-70320 to be used for hardware emulation and software debugging for the ~PD79011, a V25 16-bit, singlechip microcomputer with an on-board real-time operating system (RTOS). When using the IE-70320-RTOS
system software, the RTOS object code is loaded into
the 16K bytes of internal ROM emulation memory wheneverthe IE-70320 is powered uporthe CAncel command
is executed.
In addition, the IE-70320-RTOS system software adds
the following commands to the IE-70320.
Mem/reg SYstime
Sets system time of the RTOS.
Display TStat
Displays system time, task
status, number of unused
memory blocks, segment val ue
of all messages queued in the
TC B, start address of the
initialization routine, and
interrupt return address in the
TC B for a specified task.
Displays status of specified
mailbox.
To distinguish b~tween an address condition occurring
at any memory read/write access or the execution of an
instruction, each breakpoint can be tagged with either a
nonexecution or execution flag.
Up to 16 software breakpoints can be set plus an
additional one in the GO command. To set a software
breakpoint, the emulator replaces an instruction in the
user's program with a BRK 0 instruction. A break will
occur when this instruction is executed, and the user's
program will be restored. This capability is not available
for program code executing out of ROM.
Display MAil box
Display SEmaph 4
Trace Capabilities
The trace buffer is 2047 frames by 108 bits wide and
sampling is done on every machine cycle. The buffer is
filled in a round-robin fashion. The emulator traces the
external address and data buses, the internal ROM
address and data buses, the CPU and queue status, the
DMMKO/DMMK1 pins, and the eight external logic
probes.
Display TMap
Displays number of tasks
waiting for specified
semaphore and remaining
number of free resources.
Displays a list of all tasks
currently being managed by
RTOS and their state.
The IE-70320 has eight trace specification points. One of
these is reserved for setting a trigger point in the GO
command. The other seven can be specified as trace
trigger, enable, disable, qualify, or check points. Check
points are used to display the register, memory, or
input/output contents each time a certain event or ad-
3
NEe
IE·70320
System Software
The IE-70320 is controlled by the MIOS/U proprietary
operating system. Command input is simplified by eight
function keys (providing a choice of up to 24 softkeys
within any menu level). The dynamically reprogrammed
softkeys visually prompt the user with the next valid set
of commands. The softkeys are at the bottom of the
display and correspond to the eight function keys. To
select a command, the desired softkey is entered, and
the softkeys are automatically relabeled with the next set
of commands.
Table 1 shows some of the utility programs provided with
the emulator.
Table 1. IE-70320 Utility Programs
Utility
Function
EMUV25
IE-70320 emulator software
KERMIT
Communication program for file transfer
FILESEFW
File management for system di sks
EDITOR
Full !lcreen editor
FORMAT
Floppy-disk formatter
PROM
Built-In EPROM programmer control program
TERMINAL
Terminal utility program for file transfer between
emulator and another intelligent device
SYMBOL
Symbol Table Converter: converts non-SROC
symbol formats to SROC format.
OBJCONV
Object File Converter: converts object files to
and from the Motorola SROC format.
TIMESET
Internal battery backed-up clock and calendar
setting
DEFINE
Softkey definition
MDEVICE
Disk format specification
Connecting to Host Systems
Host systems may be connected to the IE-70320 by the
RS-232C connectors at the rear of the machine. Parameters such as baud rates, character length, parity, and
number of stop bits are software programmable to suit
the system being attached. The KERMIT communications program is supplied with the emulator and can be
used for uploading and downloading files. NEC currently
provides KERMIT for the VAX.® under VMS® and UNIXTM
4.2 BSD or Ultrix®, the IBM PC, PC/XT®, IBM PC AT®, or
compatibles under PC-DOS® or MS-DOS.
VAX, VMS, and Ultrix are registered trademarks of Digital Equipment
Corporation.
UNIX is a trademark of AT&T Bell Laboratories
PCJ)(T, PC AT, and PC-DOS are registered trademarks of International
Business Machines Corporation.
4
Files may also be transferred to the emulator via the
RS-232C ports by using the TERMINAL utility. The emulator acts as a terminal for data transfer.
Another means of loading files into the IE-70320 is
available with the Multiple File Handler utility, a program
that runs in the emulator itself and which is also supplied
as part of the IE-70320 package. The Multiple File Handier allows the emulator to read MS-DOS disks, among
others.
Symbolic Debug and Line Assembly/
Disassembly
The IE-70320 supports complete symbolic debugging of
programs produced by NEC's RA70320 Relocatable Assembler package and various other third-party software
packages, including those of Intel and Microsoft. The
symbols can be used as address and data constants in
break, trace, and emulation control commands and are
displayed during disassembly. A symbolic line assembler
is also available to make modifications to existing progr~ms or to enter code from the keyboard.
Specifications
Table 2 gives the electrical, environmental, and physical
specifications of the equipment.
Table 2. IE-70320 Specifications
Ac power
Temperature
90 to 132 V, 50/60 Hz, 400 W maximum
Operating: +5 to +40°C
Storage: -20 to +50°C
Relative humidity
(noncondensing) ..
Operating: 20 to 80%
Weight
Main chassis: 40 pounds
Storage: 10 to 90%
Pod and cables: 4-3/4 pounds
Dimensions (L x W x H)
19.7 x 16.7 x 8.7 inches
Documentation
The following manuals are supplied with the in-circuit
emulator.. Additional copies may be obtained from NEC
Electronics Inc.
•
•
•
•
IE-70320 In-Circuit Emulator User's Manual
IE-70XXX-A Hardware User's Manual
IE-70XXX-A Software Utilities User's Manual
IE-70320-RTOS I-t-PD79011 RTOS System Software
User's Manual
NEe
NEe Electronics Inc.
IE-70330
In-Ci rcuit Emulator
for pPD70330/70332 (V3S) Microcomputers
Description
o 16 user-programmable software breakpoints
The IE-70330 is a portable, stand-alone, in-circuit emulator that provides hardware emulation and software
debug capabilities for the /tPD70330/70332 (V35 TM) 16bit, single-chip microcomputers.
o Trace buffer: machine cycle, mnemonic, and jump
trace display
- 2047 frames by 108 bits
- Programmable trigger point and trace qualifiers
Real-time and single-step emulation, coupled with sophisticated memory mapping, symbolic debugging,
macrofile command facilities, and user-programmable
breakpoints and trace qualifiers, create a powerful development environment.
Command entry is simplified by eight dynamically reprogrammed function keys, called softkeys, that visually
prompt a user with the next level of commands. User
programs can be uploaded/downloaded from a variety of
host systems by a serial link, or they can be loaded
directly from an MS-DOS® disk.
Features
o Portable, stand-alone, in-circuit emulator
- 9.5-inch amber CRT display
- Two 5-inch, 640K-byte floppy-disk drives
- ASCII keyboard with eight function keys
- EPROM programmer: 2732, 2764, 27128, 27256,
27512
- Supports NEC's V20®, V30®, V33 ™ , V25 ™ , V40 ™ ,
V50 TM, V53 ™, and V60 ™ microprocessors
o Precise real-time and single-step emulation
- Programmable internal clock: 1 to 16 MHz in
1-kHz steps
- Up to 16-MHz external TTL clock
o Memory and I/O space mappable in 4K-byte blocks
o 32K bytes of memory for internal ROM emulation
o 124K bytes of memory for prototype memory
emulation; expandable to 636K bytes
o Eight user-programmable hardware breakpoints
- Real-time break on address, data, CPU status, or
external probes
- Break on pass count and register, memory, or I/O
values
- Selectable as execution or nonexecution
V20 and V30 are registered trademarks of NEC Corporation.
V25, V33, V3S, V40, V50, V53, and V60 are trademarks
of NEC Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
!I022O
o Eight optional probes for tracing target system
signals
o Full symbolic debug capabilities
o Symbolic line assembler and disassembler
o Macrofile command capability
o Dual window display in emulation mode
o Soft key and menu-driven user input
Ordering Information
Part Number
Description
IE-70330 -AQ08
In-circuit emulator for ~PD70330/70332 (V35)
IE-70330-RTOS
~PD79021
RTOS system software for
IE-70330-A008
EP-70320L
~PD70320/70322
IE-70000 -2957
Optional 512K-byte expansion emulation
memory
IE-70000 -2954
Optional external logic probes
EP-70320GJ
Optional 94-pin plastic QFP package probe
adapter for use with EP-70320L
84-pln PLCC emulation probe
Hardware
The IE-70330 (figure 1) consists of a system chassis with
a detachable ASCII keyboard and an emulation pod unit. ~
The chassis houses a 9.5-inch amber CRT, two 5-1/4 inch
640K-byte floppy-disk drives, an EPROM programmer,
card cage, power supply, and five control boards. The
boards are main CPU, expansion system memory, emulation controll.and II, and trace emulation memory.
I:11III
The main CPU board contains a supervising CPU, 512K
bytes of system memory, and the peripheral interfaces.
The expansion system memory board provides an additional 512K bytes of system memory.
NEe
IE·70330
The two emulation control boards control memory mapping, event detection, and the break and emulation CPU
status circuitry. The trace emulation board contains a
trace buffer and 124K bytes of external emulation memory. The optionaIIE-70000-2957, a 512K-byte expansion
emulator memory board, may be installed to increase
the external emulator memory to 636K bytes.
The emulation pod unit houses the p.PD70339 EVACHIP
used to emulate the p.PD70330 or p.PD70332, the internal
ROM emulation memory, the high-speed buffers, and the
clock selection logic. This unit can be connected to the
target system by the EP-70320L, an emulation probe for
the 84-pin PLCC. For the 94-pin plastic QFP, an EP70320GJ probe adapter is also needed.
The IE-70330 supports the following external interfaces:
two RS-232C serial ports, one Centronics parallel printer
port, and one RG B video output.
An optional external logic probe unit (IE-70000-2954) is
also available. The eight probes contained in the unit
allow signals on the target system to be used in the
break and trace functions.
The emulator can be converted to support NEC's V20,
V25, V30, V33, V40, V50, V53, and V60 CMOS microprocessors by exchanging the appropriate control boards
and the emulation pod unit.
Figure 1. IE-70330 System Configuration
Memory and I/O Mapping Capabilities
The IE-70330 contains two kinds of emulation memory:
32K bytes of high-speed RAM that can be accessed in
one clock cycle per byte for emulating the internal ROM
of the p.PD70332, and 124K bytes (expandable to 636K
bytes) of two-cycle RAM (0 wait states) for emulating
external RAM or ROM.
2
The complete 1M-byte memory space of the p.PD70330/
70332 must be mapped into one of the following categories:
INTROM
Internal p.PD70332 ROM emulation memory
(0, 8, 16, 32K bytes selectable)
ROM
External ROM emulation memory
(read only)
External RAM emulation memory
(read/write)
Memory resident in target system
(read/write)
RAM
Target
Locked
Access inhibited memory
(remaining unmapped addresses)
All memory mapping except INTROM is executed in
4K-byte blocks using the Configure and Memory softkey
commands. If an address that has been mapped as
"Iocked" is accessed, a break in emulation will occur.
The complete 64K-byte input/output space of the
p.PD70330 or p.PD70332 must be mapped in 4K-byte
blocks either to the RAM emulation memory, to the target
system, or as "locked" memory.
Emulation
The IE-70330 executes p.PD70330 and p.PD70332 user
programs in real time in four different modes: break,
trace, count, and time.
(1)
In break emulation mode, the program is run in real
time or in single step until a breakpoint is encountered.
(2)
In trace emulation mode, the program is executed
until the trace buffer is filled.
(3)
In count emulation mode, the emulator counts the
number of times a particular trigger point is
reached within a given set of conditions.
(4)
In time emulation mode, the emulator times execution between the specified enable and disable
points. The measurable time range is from 0 to 72
minutes (in microseconds).
Once emulation is stopped in either break or trace mode,
the trace automatically displays one screen of data,
ending on the last instruction executed. In count or time
mode, the current count or elapsed time is displayed. At
this pOint, it is possible to display the contents of
memory, the general-purpose and special registers, the
symbol tables, directories, and other information. All can
be displayed individually or by split screen with the trace
display. The windows may be scrolled independently.
NEe
Prior to the start of emulation, the user can specify the
internal ROM size (if any), whether an external or internal clock will be used for emulation, and whether the
NMI, READY, and HOLD signals from the target system
should be enabled or disabled. If the internal clock is
used, it can be set from 1 to 16 MHz in 1-KHz steps.
Break Capabilities
The IE-70330 has eight hardware breakpoints. Seven can
be set to occur on a real-time event or a non-real-time
condition. The remaining one is reserved for setting a
real-time address breakpoint in the GO command.
A real-time breakpoint can be set to occur on an address,
a data val ue, a CPU state, or an external probe status. A
non-real-time breakpoint can be set to occur after an
address/condition setting has been satisfied for a certain number of times (maximum 4096).
Conditions pertaining to the general-purpose registers,
memory locations, input/output locations, or external
probes can be defined. For non-real-time breakpoints,
the user program is executed in real time until it reaches
the break address. Emulation stops while the conditions
are checked. If the conditions are not satisfied, emulation will continue in this manner until they are met.
To distinguish between an address condition occurring
at any memory read/write access or the execution of an
instruction, each breakpoint can be tagged with either a
nonexecution or execution flag.
Up to 16. software breakpoints can be set plus an
additional one in the GO command. To set a software
breakpoint, the emulator replaces an instruction in the
user's program with a BRK 0 instruction. A break will
occur when this instruction is executed, and the user's
program will be restored. This capability is not available
for program code executing out of ROM.
Trace Capabilities
The trace buffer is 2047 frames by 108 bits wide and
sampling is done on every machine cycle. The buffer is
filled in a round-robin fashion. The emulator traces the
external address and data buses, the internal ROM
address and data buses, the CPU and queue status, the
DMAAKO/1 pins, and the eight external logic probes.
IE·70330
The IE-70330 has eight trace specification points. One of
these is reserved for setting a trigger point in the GO
command. The other seven can be specified as trace
trigger, enable, disable, qualify, or check points. Check
points are used to display the register, memory, or
input/output contents each time a certain event or address occurs. The trace buffer can be split into a maximum of 128 partitions to allow tracing of particular
segments of the user program (i.e., subroutines).
The trace data may be displayed in one of three modes:
machine, disassembly, or jump. In machine display
mode, all bus activity is displayed in machine code. In
disassembly mode, all instructions are disassembled. In
jump mode, only instructions that alter program flow are
displayed.
System Software
The IE-70330 is controlled by the MIOS/U proprietary
operating system. Command input is simplified by eight
function keys (providing a choice of up to 24 softkeys
within any menu level). The dynamically reprogrammed
softkeys visually prompt the user with the next valid set
of commands. The softkeys are at the bottom of the
display screen and correspond to the eight function keys
on the keyboard. To select a command, the desired
softkey is entered, and the. softkeys are automatically
relabeled with the next set of commands.
Table 1 lists some of the utility programs provided with
the emulator.
IE-70330-RTOS System Software
The optionaIIE-70330-RTOS system software allows the
IE-70330 to be used for hardware emulation and software debugging for the p.PD79021, a V35 16-bit single- ~
chip microcomputer with an on-board real-time operating system (RTOS). The RTOS object code is loaded into
the 16K bytes of internal ROM emulation memory whenever the IE-70330 is powered uporthe CAncel command
is executed.
l:.1li
In addition, the IE-70330-RTOS system software adds
the commands in table 2 to the IE-70330.
3
NEe
IE-70330
Files may also be transferred to the emulator via the
RS-232C ports by using the TERMINAL utility. The emulator acts as a terminal for data transfer.
Table 1. IE-70330 Utility Programs
Utility
Function
EMUV35
IE-70330 emulator software
KERMIT
Communication program for file transfer
FILESE~
File management for system disks
EDITOR
Full screen editor
FORMAT
Floppy-disk formatter
PROM
Built-in EPROM programmer control program
TERMINAL Terminal utility program for file transfer between
emulator and another intelligent device
SYMBOL
Symbol table converter; converts non-SROC symbol
formats to SROC format
OBJCONV Object file converter; converts object files to and from
the Motorola SROC format
TIMESET
Internal battery backed-up clock and calendar setting
DEFINE
Softkey definition
MDEVICE
Disk format specification
Table 2. IE-70330-RTOS Commands
Another means of loading files into the IE-70330 is
available with the Multiple File Handler utility, a program
that runs in the emulator itself and is supplied as part of
the IE-70330 package. The Multiple ,File Handler allows
the emulator to read MS-DOS disks, among others.
Symbolic Debug and Line Assembly!
Disassembly
The IE-70330 supports complete symbolic debugging of
programs produced by NEC's RA70320 RelocatableAssembler package and various other third-party software
packages, incl uding those of Intel and Microsoft. The
symbols can be used as address and data constants in
break, trace, and emulation control commands and are
displayed during disassembly. A symbolic line assembler
is also available to make modifications to existing programs or to enter ~ode from the keyboard.
Command
Description
Specifications
Mem/reg SYstime
Sets RTOS system time.
Display TStat
Displays system time, task status, number of
unused memory blocks, segment value of all
messages queued in the TCB, start address of
initialization routine, and interrupt return
address in the TCB for a specified task.
Table 3 gives the electrical,environmental, and physical
specifications of the equipment.
mailbo~.
Display MAilbox
Displays status of specified
Display SEmaph
Displays number of tasks waiting for specified
semaphore and remaining number of free
resources.
Display TMap
Displays a list of all tasks currently being
managed by RTOS and their current state.
Table 3.
IE-70330 Specifications
Ac power
Temperature
90 tQ 132 V, 50/60 Hz, 400 W maximum
Operating: +5 to +40°C
Storage:-20 to +50°C
Relative humidity
(noncondensing)
Operating: 20 to 80%
Storage: 10 to 90%
Weight
Main chassis: 40 pounds
Dimensions (L x W x H)
19.7 x 16.7 x 8.7 inches
Pod and cables: 4-3/4 pounds .
Connecting to Host Systems
Host systems may be connected to the IE-70330 through
RS-232C connectors at the rear of the machine. Parameters such as baud rates, character length, parity, and
number of stop bits are software programmable to suit
the system being attached. The KERMIT communications program is supplied with the emulator and can be
used for uploading and downloading files. NEC currently
provides KERMIT for the VAX® under VMS® and UNIXTM
4.2BSD or Ultrix®, the IBM PC, PC/XT®, IBM PC AT®, or
compatibles under PC-DOS® or MS-DOS.
VAX, VMS, and Ultrix are registered trademarks of Digital Equipment
Corporation.
UNIX is a trademark of AT&T Bell Laboratories.
PC/XT, PC AT, and PC-DOS are registered trademarks of International
Business Machines Corporation.
4
Documentation
The following manuals are supplied with the in-circuit
emulator. Additional copies may be obtained from NEC
Electronics Inc.
•
•
•
•
IE-70330 In-Circuit Emulator User's Manual
IE-70XXX-A Hardware User's Manual
IE-70XXX-A Software Utilities User's Manual
IE-70330-RTOS, Il-PD79021 RTOS System Software
User's Manual
NEe
NEG Electronics Inc.
RA70116
Relocatable Assembler Package
for V20 -V50 Microprocessors
Description
Ordering Information
The RA70116 Relocatable Assembler package converts
symbolic source code for the ~PD70108 (V20®) ,
jA-PD70116 (V30®) , ~PD70208 (V40™), and jA-PD70216
(V50™) microprocessors into executable absolute address object code. The package consists offour separate
programs: an assembler (RA70116), a linker (LK70116), a
hexadecimal format object code converter (OC70116),
and a librarian (LB70116).
Part Number
Package
RA70116-D52
MS-DOS, 5-1/4" double-density floppy-diskette
RA70116-WT1
VAX/VMS, 9-track 1600-BPI magnetic tape
RA70116-VXT1
VAX/UNIX 4.2BSD or Ultrix, 9-track 1600-BPI
magnetic tape
RA70116 translates a symbolic source module into a
relocatable object module. This symbolic source module
can contain both V20-V50 microprocessor instructions
and Intel 8087 Floating-Point Arithmetic Coprocessor
instructions. The assembler verifies that each instruction assembled is valid and produces a listing file and a
relocatable object module.
LK70116 combines relocatable object modules and absolute load modules and converts them into an absolute
load module. OC70116 converts an absolute object module or an absolute load module to an expanded hexadecimal (7-bit ASCII) object file.
LB 70116 allows commonly used relocatable object modules to be stored in one
and linked into multiple
programs, greatly increasing programming efficiency.
When the input of the linker contains a library file, the
linker first extracts only those modules required to resolve external references from the file and relocates and
links them.
file
Features
o Absolute address object code output
SOFTWARE DESCRIPTION
Program Syntax
An RA70116 source module consists of a series of code,
data, or stack segments. Each segment consists of
statements composed of up to four fields: symbol, mnemonic, operand, and comment.
The symbol field may contain a label whose value is the
instruction or data address, or a name that represents an
instruction address, data address, or constant. The mnemonic field may contain an instruction or assembler
directive. The operand field contains the data or expression for the specified instruction or directive. Explanations of statements may be inserted in the comment
field.
Character constants are translated into 7-bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal. Arithmetic expressions
may include the operators +, -, *, I, MOD, OR, AND,
NOT, XOR, EO, NE, LT, LE, GT, GE, SHR, SHL, LOW,
HIGH, PTR, SHORT, THIS, SEG, OFFSET, SMSIZE,
GRSIZE, SMOFFSET, GROFFSET, TYPE, LENGTH,
SIZE, MASK, WIDTH, (), [ ], period (.), colon (:), < >.
o Macro and code macro capability
Macro and Code Macro Capability
o User-selectable and directable output files
RA70116 allows the definition of macrocode sequences
with parameters, LOCAL symbols, and special repeated
code sequences. The macrocode sequence is different
from a subroutine call. That is, the invocation of a macro
in the source code results in the direct replacement of a
macro call with the defined code sequence.
o Extensive error reporting
o Powerful Librarian
o Runs under the following operating systems:
- MS-DOS®
- VAXNMS® and VAX/UNIX® 4.2BSD or Ultrix®
V20 and V30 are registered trademarks of NEC Corporation.
V40 and V50 are trademarks of NEC Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
VAX., VMS, and Ultrix are registered trademarks of Digital Equipment
Corporation.
UNIX is a trademark of AT&T Bell Laboratories.
50223
RA70116 also allows the definition of code macros to
give the user the capability of defining a new instruction
(mnemonic). Although an instruction definition could
also be defined using the ordinary macro facility, code
macros specify the allowable operand types for the new
instructions whereasordinary macros cannot.
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RA70116
Assembler Directives
Assembler directives give instructions to the assembler
but are not translated into machine code during assembly. Basic assembler directives include those for storage
definition and allocation (DB, Ow, DO, DBS, DWS, DDS,
STRUC/ENDS, RECORD); symbol control (EQU, LABEL,
PURGE); and location counter control (ORG, EVEN,
ALIGN).
Figure 1. Relocatable Assembler Functional
Diagram
Program control directives include those for segment
definition and control (SEGMENT/ENDS, PROC/END P,
ASSUME, GROUP, END); linkage (NAME, PUBLIC, EXTRN); and PARITY.
The relocation types for SEGMENT/ENDS directives are
specified in the operand column and include BYTE,
WORD, PARA, PAGE, and INPAGE. The combination
types of PUBLIC, COMMON, AT, STACK, and MEMORY,
which are also specified in the operand column, define
the means of linking segments and groups of the same
name.
Assembler Controls
Two types of assembler controls are available for the
RA70116.
• Basic controls (specified in the assembler command
line)
- File specification
- Output file selection
'- Output file destination
- Listing format controls
- Debug information output selection
- Symbol case selection
- Macro processing selection
• General controls (speCified in the source program)
- Inclusion of other source files
- Page eject
- Generation/suppression of listing
- Generation/suppression of macro listings
- Listing titles
A list file may contain the complete assembly listing, or
it may contain only lines with errors and a symbol or
cross-reference table. The symbol table lists all defined
symbols in alphabetical order and also shows their
types, attributes, and the values initially assigned to
them. The cross-reference table contains all defined
symbols as well as the numbers of all statements referring to them.
The object file contains the relocatable object module.
The format of this module is an NEC proprietary relocatable object module format. Figure 1 is a functional
diagram of the assembler.
2
83YL-6471A
Linker
The LK70116 linker combines relocatable object modules
and absolute load modules and produces one absolute
load module. See figure 2. The controls for LK70116 may
be specified in either the command line or in a parameter
file. In addition to being able to specify the module name
and the starting address and order for code/data/stack
segments, you can also protect areas of memory from
being .assigned. Furthermore, you can instruct the program to create a list file containing a link map, a local
symbol table, or a pUQlic symbol table. The absolute load
module contains symbol information for the symbolic
debugger and absolute object code.
NEe
Figure 2.
RA70116
Unker Functional Diagram
Figure 3. Hexadecimal Object Code Converter
Functional Diagram
Library
Module
File
System
, Console
System
Console
-
Temporary
Work
Files
* Absolute addresses with no external references.
83YL·6473A
Librarian
83YL·6472A
Hexadecimal Object Code Converter
The OC70116 object code converter translates an absolute load module file into an expanded hexadecimal
format (7-bit ASCII) file that may be downloaded to a
PROM programmer. Addresses may be specified as
being output in the order in which they were input or in
ascending order. Figure 3 is a functional diagram of the
hexadecimal object code converter.
The LB70116 librarian creates and maintains files containing relocatable object modules. The program reduces the number of files that need to be linked together
by allowing several modules to be kept in a single file. It
also provides an easy way to link frequently used. modules into programs. Modules may be added to, deleted
from, or replaced within a library file.
Operating Environment
The RA70116 package can be supplied to run under
several different operating systems. One version is for an
MS-DOS system with one or more disk drives and at
least 512K bytes of system memory. Other versions run
on a Digital Equipment Corporation VAX computer with
UNIX 4.2 BSD or Ultrix, or VMS (Version 4.1 or later)
operating systems.
3
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RA70116
Downloading Files Into the Emulator
DOCUMENTATION
Absolute load modules produced by the RA70116 package for the V40 and V50 can be debugged using the NEC
IE-70208 (V40) or IE-70216 (V50) stand-alone in-circuit
emulator. Communication between these emulators and
the host system is through an RS-232C serial line using
the KERMIT communication protocol developed at Columbia University. With the appropriate version of the
KERMIT Communication Program running on both the
emulator and host system, absol ute load modules or
hexadecimal object code files may be transferred between machines.
For further information on source program formats,
assembler operation, and actual program examples,
refer to the following manuals supplied with the
RA70116. Additional copies may be obtained from NEC
Electronics Inc.
A version of the KERMIT Communication Program is
supplied with the IE-70208 and IE-70216. Versions of
KERMIT run on the IBM PC, PC/XT®, PC AT®, or compatibles under MS-DOS, and the DEC VAX under VMS,
UNIX 4.2BSD or Ultrix. An appropriate version is provided with each relocatable assembler package at no
extra charge. Versions of KERMIT for other host systems
are available directly from Columbia University.
A second means of loading files into the emulator is also
available in the Multiple File Handler, a utility program
that runs in the emulator and is supplied with the
IE-70208 and IE-70216. The Multiple File Handler allows
the emulator to read MS-DOS formatted disks, among
others.
.
PC/XT, PC AT, and PC-DOS are registered trademarks of International
Business Machines Corporation.
4
• RA70116 V20-V50 Relocatable
Language Manual
• .RA70116 V20-V50 Relocatable
Operation Manual (MS-DOS)
• RA70116 V20-V50 Relocatable
Operation Manual (UNIX)
• RA 70116 V20-V50 Relocatable
Operation Manual (VMS)
Assembler Package
Assembler Package
Assembler Package
Assembler Package
LICENSE AGREEMENT
RA70116 is sold under terms of a license agreement
included with purchased copies of the assembler. The
accompanying card must be completed and returned to
NEC Electronics Inc. to register the license. Software
updates are provided to registered users.
NEe
RA7.013~
Relocatable Assembler Package
for V33 Microprocessor
NEe Electronics Inc.
Description
The RA70136 Relocatable Assembler package converts
symbolic source code for the #-,PD70136 (V33 TN) microprocessor into executable absolute address object
code. The package. consists of five separate programs:
an assembler (RA 70136), a linker (LK70136), an extended
mode locater (EL70136), a hexadecimal format object
code converter (OC70136), and a librarian (LB70136).
RA70136 translates a symbolic source module into a
relocatable object module. This symbolic source module
can contain both V33 microprocessor instructions and
NEC #-,PD71291 Advanced Floating-Point Processor
(AFPP) instructions. The assembler verifies that each
instruction assembled is valid and produces a listing file
and a relocatable object module.
LK70136 combines relocatable object modules and absolute load modules and converts them into an absolute
load module. If V33 normal addressing mode is being
used, OC70136 is used to convert an absolute object
module or an absolute load module to an expanded
hexadecimal (7-bit ASCII) object file. If V33 extended
addressing mode is being used, the EL70136 converts
load modules produced by LK70136 to an extended load
module file in extended COFF format.
LB70136 allows commonly used relocatable object modules to be· stored in. one file and linked into multiple
programs, greatly increasing programming efficiency.
When the input of the linker contains a library file, the
linker first extracts only those modules required to resolve external references from the file and relocates and
links them.
Features
Cl
Cl
Cl
Cl
Absolute address object code output
- In extended hexadecimal format for normal
addressing mode
-In extended COFF format for extended
add ressing mode
Macro and code macro capability
User-selectable and directable output files
Extensive error reporting
V33 Is a trademark of NEC Corporation.
MS·DOS Is a registered trademark of Microsoft Corporation.
VAX, VMS, and Ultrlx are registered trademarks of Digital Equipment
Corporation.
UNIX Is a trademark of AT&T.
Cl
Cl
Powerful Librarian
Runs under the following operating systems
-MS-DOS®
- VAXNMS® and VAX/UNIXTM 4.2BSD or Ultrix™
Ordering Information
Part Number
Description
RA70136·D52
MS·DOS, 5-1/4" double-density floppy diskette
RA70136·WT1
VAX/VMS, 9·track 1600·BPI magnetic tape
RA70136·VXT1
VA:XIUNIX 4.2 BSC or Ultrlx, 9·track 1600·BPI
magnetic tape
SOFTWARE DESCRIPTION
Program Syntax
An RA70136 source module consists of a series of code,
data, or stack segments. Each segment consists of
statements composed of up to four fields: symbol, mnemonic, operand, ~nd comment.
The symbol field may contain a label, whose val ue Is the
instruction or data address, or a name that r~presents an
instruction address, data address, or constant. The mnemonic field may contain an instruction or assembler
directive. The operand field contains the data or expression for the specified instruction or directive. explanations for statements maybe inserted in the comment
field.
Character constants are translated into 7-bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal.. Arithmetic expressions
may include the operators +, -, ., I, MOD, OR, AND,
NOT, XOR, EO, NE, LT, LE, GT, GE, SHR, SHL, LOW,
HIGH, PTR, SHORT, THIS, SEG, OFFSET, SMSIZE,
GRSIZE, SMOFFSET, GROFFSET, TYPE, LENGTH,
SIZE, MASK, WIDTH, (), []i period (.), colon (:), < >.
Macro and Code Macro Capability
RA70136 allows the definition of macrocode sequences
with parameters, LOCAL symbols, and special repeated
code sequences. The macrocode sequence is different
from a subroutine call. That is, the invocation of a macro
in the source code results in the direct replacement of a
macro call with the defined code sequence.
RA70136 also allows the definition of code macros to
give the user the capability of defining anew instruction
(mnemonic). Although an instruction definition could
m
•
NEe
RA70136
also be defined using the ordinary macro facility, code
macros specify the allowable operand types for the new
instructions whereas ordinary macros cannot.
Assembler Directives
Assembler directives give instructions to the assembler
but are not translated into machine code during assembly. Basic assembler directives include those for storage
definition and allocation (DB,
DO, DO, OS, Dl, DBS,
r:J.NS, DDS, DOS, DSS, DlS, STRUC/ENDS, RECORD);
symbol control (EaU, LABEL, PURGE); and location
counter control (ORG, EVEN, ALIGN).
The object file contains the relocatable object module.
The format of this module is an NEC proprietary relocatable object module format. Figure 1 is a functional
diagram of the assembler.
Figure 1. Relocstable Assembler Functional
Dillgram
r:m.
Program control directives Include those for. segment
definition and control (SEGMENT/ENDS, PROC/ENDP,
ASSUME, GROUP, END); linkage (NAME, PUBLIC, EXTRN); and PARITY.
The relocation types for SEGMENT/ENDS directives are
specified in the operand column and include BYTE,
WORD, PARA, PAGE, and INPAGE. The combination
types of PUBLIC, COMMON, AT, STACK, and MEMORY,
whIch are also specified in the operand column, define
the means of linking segments and groups of the same
name.
Assembler Controls
Two types of assembler controls are available for the
RA70136.
• Basic controls (specified in the assembler .command
line)
- File specification
- Output file selection
- Output file destination
- Listing format controls
- Debug information output selection
- Symbol case selection
'- Macroprocessing selection
• General controls (specified in the source program)
-Inclusion of other source files
- Page eject
- Generation/siJppressionof listing
- Generation/suppression of macro listings
- Listing titles
A list file may contain the complete assembly listing, or
it may contain only lines with errors and a symbol or
cross-reference table. The symbol table lists all defined
symbols in alphabetical order and also shows their
type~, attributes, and the values initially ass,igned to
them. The cross-reference table contains all defined
symbols as well as the numbers of all statements referring to them.
'
2
Source
Module
File
Include
File
System
Console
83VL-6474A
Linker
The lK70136 linker combines relocatable object modules and absolute load modules and produces one absolute load module. See figure 2. The controls for
lK70136 may be specified in eitherthe.command line or
In a parameter file. In addition to being ,able to specify the
module name and the starting address and order for
code/data/stack segments, you can also protect areas of
memory. from being assigned. Furthermore, you can
instruct the program to create a list file containing a 1i1J~
map, a local symbol table, or a public symbol table.' The
absolute load module contains symbol information for
the symbolic debugger and absolute object code.
NEe
RA70136
Figure 3. HeXJIdecimalObject Code Converter
FunctlolllllDi.,am
Figure 2. Unker FunctlonalDlllIJram
Object
Module
File
*
System
Console
-
Absolute
Load
Module
File
Temporary
Work
Files
* Absolute addresses with no external references.
83YL·6476A
Extended Mode Locater
83YL·6475A
Hexadecimal Object Code Converter
The OC70136 object code converter translates an absolute load module file into an expanded hexadecimal
format (7-bit ASC II) file that may be downloaded to a
PROM programmer. This program is used with the V33 in
normal addressing mode (1 M-byte address space). Addresses may be specified as being output in the order in
which they were input or in ascending order. Figure 3 is a
functional diagram of the hexadecimal object code converter.
The EL70136 extended mode locater converts multiple
load modules produced by LK70136 Into one extended
load module file in extended COFF format (figure 4).
This program is used with the V33 in extended address
mode (16M-byte address space). Starting addresses for
each load module are specified in the Locate Information
file. The name of this file along with the name of the
extended load module file and any locater options are
included in the command line when EL70136 is invoked.
EL70136 can be instructed to create a locate map file
and to include debugging information in the extended
load module file. To support debugging with the IE70136, EL70136 also sets initial values for the IE-70136 . . .
PGR tables in the extended load module file.
~
To simplify the task of using the extended addressing
mode of the V33, NEC Electronics provides three subroutines with the RA70136 package.
(1) V33_MAP. Maps the #,PD70136 Page Registers
(PGRs)
(2) V33-BRK. Branches from the normal address mode
to the interrupt routine starting address in the extended address mode.
(3) V33_RET. Branches from the extended address
mode to the interrupt routine starting address in the
normal address mode.
3
ttiEC
RA70136
Figure 4. Extended Locater Functional Dlllllram
Load
Module
File 1
Ultrix. An appropriate version is provided with each
relocatable assembler package at no extra charge. Versions of KERMIT for other host systems are available
directly from Columbia University.
A second means of loading files into the emulator is also
available in the Multiple File Handler, a utility program
that runs in the emulator and is supplied with the
IE-70136. The Multiple File Handler allows the emulator
to read MS-DOS formatted disks, among others.
EL70136
Extended Mode
Locater
DOCUMENTATION
83VL-64nA
Librarian
The LB70136 librarian creates and maintains files containing relocatable object modules. The program reduces the number of files that need to be linked together
by allowing several modules to be kept in a single file. It
also provides an easy way to link frequently used modules into programs. Modules may be added to, deleted
from, or replaced witl1in a library file.
Operating Environment
The RA70136 package can be supplied to run .under
many different operating systems. One version is for an
MS-DOS system with one or more disk drives and at
least 512K bytes of system memory. Other versions run
on a DEC VAX computer with UNIX 4.28S0 or Ultrix, or
VMS (Version 4.1 or later) operating systems.
Downloading Files Into the Emulator
Absolute load modules and extended load modules
produced by the RA70136 package for the V33 can be
debugged by using the NEC IE-70136 stand-alone incircuit emulator. Communication between the IE-70136
and the host system is through an RS-232C serial line
using the KERMIT communication protocol developed at
Columbia University. With the appropriate version of the
KERMIT Communication Program running on both the
emulator and host system, absolute load modules, extended load modules, or hexadecimal object code files
may be transferred between machines.
A version of the KERMIT Communication Program is
supplied with the IE-70136.. Versions of KERMIT run on
the IBM PC, PC/XT®, PC AT®, or compatibles under
MS-DOS, and the DEC VAX under VMS, UNIX 4.28SD or
4
For further information on source program formats,
assembler operation, and actual program examples,
refer to the following manuals supplied with the
RA70136. Additional copies may be obtained from NEC
Electronics Inc.
RA70136 V33 Relocatable Assembler Package Language Manual
RA70136 V33 Relocatable Assembler Package Operation Manual.
LICENSE AGREEMENT
RA70136 is sold under terms of a license agreement
included with. purchased copies of the assembler. The
accompanying card must be completed and returned to
NEC Electronics Inc. to register the license. Software
updates are provided to registered users.
PC/XT and PC AT are registered trademarks of International Business
Machines Corporation.
.
NEe
NEC Electronics Inc.
Description
The RA 70320 Relocatable Assembler package converts
symbolic source code for the V25 ™N35 ™ family of
microprocessors into executable absolute address object code. The package consists of four programs:
RA70320 assembler, LK70320 linker, OC70320 hexadecimal object code converter, and LB70320 librarian.
The RA70320 assembler translates a symbolic source
module into a relocatable object module. The LK70320
linker combines relocatable object modules and absolute load modules and converts them into one absolute
load module. The OC70320 converts an absolute object
module or absolute load module to an expanded hexadecimal (7-bit ASCII) object file.
The LB70320 librarian allows commonly used relocatable object modules to be stored in one file and linked
into multiple programs, greatly increasing programming
efficiency. When the input of the linker contains a library
file, the linker first extracts only those modules required
to resolve external references from the file and then
relocates and links these modules.
RA70320
Relocatable Assembler Package
for V25N35 Microcomputers
Ordering Information
Part Number
Description
RA70320-D52
MS-DOS; 5-1/4" double-density floppy diskette
WT1
VAX/VMS; 9-track 1600 BPI magnetic tape
VXT1
VAX/UNIX 4.2B5D or Ultrix; 9-track 1600 BPI
magnetic tape
Assembler
The RA70320 assembler program translates a symbolic
source module into a relocatable object module by first
verifying that each instruction assembled is valid for the'
target microprocessor and then producing a list file and
a relocatable object module (figure 1).
Figure 1. Relocatable Assembler Functional
Diagram
Source
Module
File
I
Features
o Absolute address object code output
o Macro and code macro capability
o User-selectable and directable' output files
o Extensive error reporting
o Powerful librarian
o Multisystem compatibility
-MS-DOS®
-VAX®NMS®
- VAX/UNIXTM 4.2BSDor Ultrix®
Include
File
System
Console
1
RA70320
Relocatable
Assembler
~
I--'-
j
J
Object
Module
File
Assembler
List
File
Temporary
Work
Files
83-004615A
V25 and V35 are trademarks of NECCorporation.
MS-DOS is a registered trademark of Microsoft Corporation.
VAX., VMS, and Ultrix are registered trademarks of Digital
Equipment Corp.
UNIX is a trademark of AT&T.
50230
NEe
RA70320
Program Syntax
An RA70320 source module consists of a series of code,
data, or stack segments. Each segment contains lines
composed of up to four fields: symbol, mnemonic, operand, and comment.
The symbol field may contain either a label-whose
value is an instruction or data address-or a name that
represents an instruction address, data address, or constant. The mnemonic field may contain an instruction or
assembler directive. The operand field contains the data
or expression for the specified instruction or directive.
Explanations forthe statements may be inserted into the
comment field.
Character constants are translated into 7-bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal. Arithmetic expressions
may include the operators +, -, *, /, MOD, OR, AND,
NOT, XOR, EO, NE, LT, LE, .GT, GE, SHR, SHL, LOW,
HIGH, PTR, SHORT, THIS, SEG, OFFSET, SMSIZE,
GRSIZE, SMOFFSET, GROFFSET, TYPE, LENGTH,
SIZE, MASK, WIDTH, (), [], period (.), colon (:), and
< >.
Macro and Code Macro Capability
RA70320 allows the definition of macro code sequences
with parameters, LOCAL symbols, and special repeated
code sequences. The macro code sequence is different
from a subroutine call in that the invocatiqn of a macro in
the source code results in the direct replacement of a
macro call with the defined code sequence.
RA70320 also allows the definition of code macros to
give the user the capability of defining a new instruction
(mnemonic). Although an instruction definition could
also be defined using the ordinary macro facility, code
macros specify the allowable operand types for the new
instructions whereas ordinary macros cannot.
Directives
Assembler directives give instructions to the program
but are not translated into machine code during assembly. Basic directives include those for storage definition
and allocation (DB, Ow, DO, DO, DT, DBS, DWS, DDS,
DOS, DTS, STRUC/ENDS, RECORD); symbol control
(EOU, LABEL, PURGE); and program counter control
(ORG, EVEN, ALIGN). Program control directives include those for segment definition and control
(SEGMENT/ENDS, PROC/ENDP, ASSUME, GROUP,
END); special function registers and internal RAM
(SETIDB, ASGNSFR); linkage (NAME, PUBLIC, EXTRN);
and PARITY.
2
The relocation types for SEGMENT/ENDS directives are
specified in the operand column and include BYTE,
WORD, PARA, PAGE, and INPAGE. The combination
types of PUBLIC, COMMON, AT, STACK, and MEMORY,
which are also specified in the operand column, define
the means of linking segments and groups of the same
name.
Controls
There are two types of assembler controls for the
RA70320:
• Basic (specified in the assembler command line)
- File specification
- Output file selection
- Output file destination
- Listing format controls
- Debug information output selection
- Symbol case selection
- Macro processing selection
• General (specified in the source program)
-Inclusion of other source files
- Page eject
- Generation/suppression of listing
- Listing titles
A list file may contain the complete assembly listing or it
may contain only lines with errors and a symbol or
cross-reference table. The symbol table lists all defined
symbols in alphabetical order and also shows their
types, attributes, and the values initially assigned to
them. The cross-reference table contains all defined
symbols, as well as the numbers of all statements referring to them.
The object file contains the relocatable object module.
The format of this module conforms to NEC's proprietary
relocatable object module format.
Linker
The LK70320 linker combines relocatable object modules and absolute load modules and produces one absolute load module (figure 2). The controls for the linker
may be specified in either the command line or ina
parameter file. In addition to being able to specify the
date, the module name, the starting address and the
order for code/data/stack segments, it is also possible to
protect areas of memory from being assigned. Furthermore, it is possible to instruct the program to create a
list file containing a link map, a local symbol table, or a
public symbol table. The absolute load module contains
symbol information for the symbolic debugger and the
absolute object code.
NEe
Hexadecimal Object Code Converter
The OC70320 object code converter (figure 3) translates
an absolute load module file into an expanded hexadecimal (7-bit ASC II) file that may be downloaded to a PROM
programmer. Addresses may be specified as being output in the order in which they were input or in ascending
order.
RA70320
IE-70320 and IE-70330 packages. The Multiple File Handier allows the emulator to read MS-DOS formatted
disks, among others.
Figure 2. Unker Functlona'DI.am
Library
Module
File
Librarian
The LB70320 librarian creates and maintains files containing relocatable object modules. The program reduces the number of files that need to be linked together
by allowing several modules to be kept in a single file,
and also provides an easy way to link frequently used
modules into programs. Modules may be added, deleted,
or replaced within a library file.
Absolute
Load
Module
File 1
....
l
Object
Module
File 1
J
Operating Environment
The RA70320 package has been designed to run under a
variety of operating systems. One version is available to
run on an MS-DOS system with one or more disk drives
and at least 512K of system memory. Other versions are
available to run on a Digital Equipment Corporation VAX
computer under the UNIX 4.2BSD, Ultrix, and the VMS
(Version 4.1 or later) operating systems.
Absolute
Load
Module
File n
....
Object
Module
File n
I
1
System
Console
Temporary
Work
File.
LK70320
Linker
j
j
Absolute
Load
Module
File
Linker
List
File
Downloading Files Into the Emulator
Absolute load modules produced by the RA70320 Relocatable Assembler package can be debugged by using
the NEC IE-70320 (V25) or IE-70330 (V35) stand-alone
in-circuit emulator. Communication between these emulators and the host system is handled through an RS232C serial line that uses the KERMIT communications
protocol developed at Columbia University. With the
appropriate version of KERMIT running on both the
emulator and host system, absolute load modules or
hexadecimal object code files may be transferred between machines.
A version of the KERMIT Communication Program is
supplied with each NEC emulator. NEC supplies versions
of KERMIT to run on the IBM PC, PC/XPM, PC ApM, or
compatibles under MS-DOS operating systems, and the
Digital Equipment VAX under VMS, UNIX 4.2BSD, or
Ultrix. An appropriate version is provided with each
relocatable assembler package at no extra charge. Versions of KERMIT for other host systems are available
directly from Columbia University
A second means of loading files into the emulator is also
available in the Multiple File Handler, a utility program
that runs in the emulator and is supplied as part of the
83-004616A
Figure 3. HeXlldeclmalObject Code
Converter Functionsl Diagram
Absolute
Load
Module
File
Object
Module
File
I
System
Console
~
OR
~
J
OC70320
Hexadecimal Format
Object Converter
J
Hexadecimal
Object
Code
File
* Absolute addresses with no external references
83-004617A
PC/XT and PC AT are trademarks of International Business Machines
Corp.
3
RA70320
Documentation.
For further information on source program formats,
assembler operation, and actual program examples,
refer to the following manuals $upplied with the
RA70320. Additional copies may be obtained from NEC
Electronics Inc.
• RA70320 V25N35 Relocatable Assembler Package
Language Manual
• RA 70320 V25N35 Relocatable Assembler Package
Operation Manual.
License Agreement
RA 70320 is sold under terms of a license agreement
included with purchased copies of the assembler. The
accompanying card'musfbe completed and returned to
NEC Electronics Inc. to register the license. Software
updates are provided to registered users.
4
NEe
NEe
V25!V35 MINI-IE Plus
In-Ci rcuit Emulator
NEG Electronics Inc.
Description
The V25 MINI-IE Plus and V35 MINI-IE Plus are low-cost
In-Circuit Emulators for'· the JlPD70320 (V25™),
JlPD70325 (V25 Plus), JlPD70330 (V35™), and JlPD70335
(V35 Plus) microcomputers from NEC Electronics. Low
cost is achieved by using an IBM PCJ)(T®, PC AT®, IBM
PS/2™, or compatible machine.
The control software for the MINI-IE Plus is AdVICE
(Advance V-Series In~Circuit Emulator), which acts as
both a monitor and debugger. Debugging with breakpoint and non-real-time tr,acing of executing programs
are accomplished in software using a V25N35 microcomputer located on the MINI-IE Plus board. An optional real-time trace (RTT) board is avai lable for those
who need this additional tool.
o Optional real-time trace (RTl) board
- 8K frames by 48-bit trace buffer··
- Two hardware breakpoints with don't care
features
- Eight external data inputs
- Hardware trigger output
- Qualifier controlled recording
-32-bit timer with 250~ns resolution
o Executes NEC .LNK absolute files and Microsoft
.COM and .EXE files
- Files can be downloaded to and uploaded from
the MINI-IE Plus
- Supports real-time and single-step emulation
- User programmable public symbol buffer size
o Emulates JlPD70325/70335 at up to 10 MHz
o Controlled by powerful AdVICE monitor and .
debugging program
-Symbolic full screen debugger
- Displays six window areas with second-level
break setup window
- Updates display information as program singlesteps
- On-line assembler
- Programmable trace and symbol buffer sizes
-On-line help menus
- Keyboard macros speed up repetitive operations
- User definable commands
- Resident operation with hot key activation
- Message exchange capabilities between PC and
emulator
o Jumper selectable internal or external (target)
clock.
o Sample batch file contains demonstration
program
o Parallel interface with host PC; interface card and
cable included
Ordering Information
The AdVICE software is designed to provide a very
user~friendly operating-debugging interface using a
custom multiwindow display. User code developed
with standard PC software development tools can be
directly loaded (.EXE and .MAP files) into the MINI-IEPluS. The AdVICE control program can even be left in
PC memory as a background TSR while code modification is performed..
Features
o Emulates JlPD70320/70330 at up to 8 MHz.
o Connects to target system via flexible PLCC socket
adapter
- Emulation memory may be mapped to MINI-IE
Plus or target system
- Supports two 64K-byte mappable user
emulation RAM areas
o Software break and trace capabilities
- Up to eight conditional breakpoints plus 'one in
command line
-Additional breakpoints can be given in the
command line
- Various actions can be programmed to take
place on a break
- Error checking of break entry conditions
150231-1
Part Number
Description
EB-V25MI NI-IE-P
pPD70320/70325 MINI-IE Plus package
EB-V35MINI-IE-P
pPD70330/70335 MINI-IE Plus package
EB-V25/35-RTT
V25/V35 MINI-IE Plus real-time trace option
IBM PC/XT, IBM PC AT, and IBM PS/2 are registered trademarks of
International Business Machines Corporation.
V25 and V35 are trademarks of NEC Corporation.
NEe
V25N35 MINI·IE Plus
HARDWARE
The V25N35 MINI-IE Plus package consists of five
components.
e
e
e
e
e
V25N35 MINI-IE Plus box with target adapter
Modified printer adapter card
Interface cable
Dc power plug
AdVICE software and user's manual
The MINI-IE Plus contains two 64K-byte blocks of static
RAM that is allocated by software to any 64K-byte
boundary within the 1M-byte address range of the
V25/35. ROM simulation is performed by write protecting this memory. An additional64K bytes of RAM and a
12S-byte I/O block are used by the internal monitor and
can be relocated by command to ~void conflicts with
external addressing needs.
Typical memory mapping allocates one block at the
beginning of the addressspace (OOOOOH) and the other
at address OFOOOOH. This may represent the final hardware configuration. The upper block would contain
program code and be write protected. Any writes to
this area would stop the program execution and allow
the user to analyze the program. This feature allows
debug when the program tries to write to ROM. Execution of the reset procedure is done by activating the
target's RESET pin. Emulator hardware/software will
not be reset by this action.
An optional real-time trace (RTl) board can be plugged
on top of the emulator card to provide a 4S-bit by SK
deep trace buffer. Eight external logic pins can be
monitored along with the V25N35 bus sigl1als.
Command control of the EA pin of the V25N35 allows
use of ROM-bas;ed devices~ After initialization, EA is
forced low to access external memory, but can be
forced high by command or may be controlled by the
target hardware.
The NMI signal is normally used by the MINI-IE Plus to
stop program execution using interrupt vector 02. Use
of the target NMI signal in an application is possible by
assigning an unused interrupt vector in place of the
normal vector. Any high-to-Iow transitions of the target
NMI signal will cause the emulator to execute this new
vector.
The interface card is a modified printer adapter card
that allows fast bidirectional communications between
the host PC and the MINI-IE Plus. This card is not
needed with an IBM PS/2. The interface cable connects
the MINI-IE Plus to the interface card onPC/XT/AT or
compatible or to the printer port of an IBM PS/2. Power
for the MINI-IE Plus is supplied via the interface card.
With PS/2, the dc power" plug and a user-supplied
external + 5-volt power supply power the MINI-IE Plus.
The flexible target adapter allows direct connection to
a PLCC socket of the target hardware. The cable is
approximately 16 cm long and protrudes from the front
of the MINI-IE Plus box. See figure 1.
Figure 1. MINI-IE Plus Front Panel
Power
•
Connector for
External Probes
Connector for
Target PLCC Adapter
Clock Selection
83-6759A
2
NEe
V251'l35 MINI-IE Plus
SOFTWARE
Emulation
The control software (AV35N .EXE or AVRTT35N .EXE)
uses the PC screen to display program and memory
data. All information is updated after every command,
and it keeps the user informed of the current state of
the emulation. The screen is divided into seven areas.
These areas display the current contents of the registers and bottom of stack, the command line, two
memory dump areas with an additional ASCII dump
display, the disassembler, and function key assignments. See figure 2.
User programs loaded into emulator RAM can be executed in real-time or in single-step mode. Single-step
mode executes only one instruction, and procedure
step executes an entire subroutine or software interrupt routine. Real-time execution is command activated and terminates when a breakpoint is encountered or the user terminates execution from the
keyboard. Program execution is also stopped when an
exception interrupt or an interrupt with an unitialized
vector occurs.
Help and other setup screens, such as breakpoint
menus, overlay some of the windows described above.
Executing a new command will restore the display to
the original screen. Figure 3 .shows the AdVICE screen
with a help window and the command line prompts.
Message exchange between the PC and an executing
application program is provided. See figure 4. An interrupt function similar to the DOS INT21 allows communication to the application program without a keyboard
or display attached to the target system.
AdVICE controls all the monitor and debug functions of
the V25N35 MINI-IE Plus including upload and download of programs, breaking, tracing, program execution, disassembly, line assembly, and register/memory
display and manipulation. The cursor can be moved
anywhere within the window displays for immediate
change of the memory areas, registers, flags, and
breakpoi nts.
Figure 2. AdVICE Main Screen
AW
noo
0000
CW 3BA8
OW 0000
Bioi
0m
IX
IY
BP
SP
0000
0000
0000
OOFE
PC OOOF
Stack +0
+2
HS 0040
+4
FS 0040 Resident +6
PS F800
DS
noo
ES 0000
SS 0040
1
)
1
RESET:
0000 B8FFFF
0003 8E08
0005 C6060FOOF7
OOOA B800F7
0000 8E08
OOOF C606020FFF
0014 C606E10FB2
0019 C706E80F5555
2
FS:OOOO
FS:0010
FS 0020
FS 0030
FS 0040
1
Step
FfFF
423E
23C3
A352
0
CC
47
FF
FF
22
1
OF
40
FF
FF
44
2
42
FE
FF
FF
CE
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
3
6C
FB
FF
FF
AE
5
2F
2A
FF
FF
A2 C7
4
04
5E
FF
FF
OS 0000
OS 0008
OS 0010
OS 0018
OS 0020
OS 0028
OS 0030
OS 0038
OS 0040
OS:0048
AW,FFFF
OS,AW
[OOOFj,F7
AW,F700
OS,AW
PMCO,FF
RFM,B2
WTC,5555
6
7
EE A2
AC
FF
FF
67
53
FO
FF
FO
8
1F
OC
FF
FF
B2
2ProcStep 3Retrieve 4Help ON
9
00
99
FF
FF
09
A
76
FO
3F
FF
EF
B
FE
E7
FF
FF
F7
C
98
6F
FO
FF
0
o
a
a
0
0
a
1
FF
FF
FF
FF
00
00
00
00
FF
FF
2
FF
FF
FF
FF
00
00
00
00
FF
FF
3
FF
FF
FF
FF
00
00
00
00
FF
FF
4
FF
FF
FF
FF
00
00
00
00
FF
FF
FF
FF
FF
FF
02
00
00
00
FF
FF
E
84 7F
6B 81
FF FF
7F FF
11 05 7F
5BRK Menu 6 DOS
PSW F002 IntM:l
V25
RB 7
V OIR IE S Z AC
P CY
F
FO
FB
FF
FF
73
7 up
~. B1
\0/ £6
GM.r"'~S
1
"Of«6f-g3
8 dn
a
0
a
5 6 7
FF FF FF
FF FF FF
FF FF FF
FE' FF FF
00 00 00
81 00 00
00 00 00
00 00 00
FF FF FF
FF FF Ff
.. v·Y=
.0 1 "coki.ll
7 1
I·n::::.s
9 Ie 10 ri
83-6760A
3
NEe
Figure 3. AdVICE Screen With He*, Menu.andCommand Une Prompts
AW
BW
CW
DW
F700
0000
3UA8
0000
D
IC~D
IX
IY
BP
SP
or
0000
PS F800
0000
DS F7'OO
0000
ES 0000
OOFE
SS 0040
DEF or DIR
>D
FFB8-
00E7 8BOF
.00E9 2EFFl5
OOEe EBC6
VECTOR_TABLE:
OOEE 56
OOEF 029802FO
OOF3 0450
00F5 03B40328
00F9 024805
o
~
1
Stack +0
+2
+4
liS 0040
FS 0040 Resident +6
PC OOOF
MOV
CALL
BR
PUSH
ADD
ADD
ADD·
ADD
BW,IY
.PS: [IY]
V40--,CLI
IX
BL, [F002+BW+IX]
AL,50
IX, [2803+IX]
eL, [B\HIX+05]
FFFF
423E
23C3
A352
1
OS:OOOO
OS:0008
08:0010
OS:0018
D8:0020
OS:0028
~'S: 0030
;OS: 0038
OS:0040
OS:0048
PSW F002
IntM:l V25
RB 7
V DIR IE S Z AC P CY
0 O. a a a a 0 0
0
FF
FF
FF
FF
02
00
00
00
FF
FF
1
FF
FF
FF
FF
00
00
00
00
FF
FF
2
FF
FF
FF
FF
00
00
00
00
FF
FF
3
FF
FF
FF
FF
00
00
00
00
FF
FF
4
FF
FF
FF
FF
00
00
00
00
FF
FF
5
FF
FF
FF
FF
00
81
00
00
FF
FF
6
"7
FF
FF
FF
Ff
00
00
00
00
FF
FF
FF
FF
FF
FF
00
00
00
00
FF
FF
(/~
ON I OFF) addr
Display - code at the specified address. With '0 1<' or 'Ctrl-Enter' the
address of the current instruction will b~ used~ If a memoiy location is
accessed by the actual instruction its value is shown on the screen. Use
to optional /M parameter to control the display of this memory data.
Standard segment PS:
________________________________
W'ith PgUp/PgDn text can be paged ______________
Step
2ProcStep 3Retrieve 4l1elp OFF SBRK Menu 6 DOS
7 up
8 dn
~
9 Ie 10 ri
8U761 A
Figure 4.
Executing Program ""ith MeSSllge Exchange
AW F700
Bioi 0000
CW 00B2
DW 0000
2
,>
1<1<1<
IX
IY
BP
SP
or
0000
0000
0000
OlFE
GC
PS 0065
OS F700
ES 0000
S8 0040
E X E C U T I N G
stack +0
+2
+4
liS 0060
FS 0040 Resident +6
PC 0000
I< 1< 1<
Analyze
Emulator Messages
< from emulator
=123 OS:[IX]= /W ES:32B4 CY=l
For more details refer to the user's manual.
BR# Break AOR
1 HAIN20
2 MAIN60
3
4 -
5 6 7 8 Address
EV1 TIMER
EV2 0
QUA 0
Condition
........................................................................
.............. ........................................................ ..
SWTIH >= 0100 ........................ " ..................
........................................................................
........................................................................
........................................................................
........................................................................
........................................................................
Type Oir
Oat OaM
AddrH
ExO ExM
0
FFFFF
00
H
R
0
0
0
R
FFFFF
H
0
00
0
X
0
000
X
0
IView Trace 3Read Setup 4 Help OFF
5 CMO line
Count Occur
1
1
1
1
1
1
0
0
0
0
0
'Action
trace ON
TR OFF A ON
br
0
0
0
0
0
P2 P2M
Action
0 00
RT ON TI ON
0 00
RTT Mode: C
7Save Setup 9Clear BRIOClear" OCC
8H763A
Figure 6. Soft Trace Buffer Oi$play
T R A C E
B U F F E R
0 I S P LAY
Buffer Offset
0
1<1<1< Begin of TRACE buffer 1<1<
HAIN20:
AW=FFOO IX=0004
0027 CALL
INIT_TIMER
BW=OOOO IY=0074
>8tarted by BRI
V OIR IE 8 Z AC P CY CW=00B2 BP=OOOO
0 0 0 0 1 0 1 0 OW=1388 SP=OIFE
INIT_TIMER:
AW=FFOO IX=0004
003E MOV
ES:TMCO,CO
BW=OOOO IY=OO74
V OIR IE S Z AC P CY CW=00B2 BP=OOOO
0 0 0 0 1 0 1 0 OW=1388 8P=01FC
AW=FFOO IX=0004
0044 MOV
ES:MOO,0140
BW=OOOO IY=0074
V OIR IE S
Z AC
P CY CW=00B2 BP=OOOO
0
0 0 0 1 0 1 0 OW=1388 SP=OlFC
004B HOV
AW=FFOO IX=0004
ES:TMICO,07
BW=OOOO IY=0074
V OIR IE S
P CY CW=00B2 BP=OOOO
Z AC
0
0 0 0 1 0 1 0 DW=1388 SP=01FC
0051 RET
AW=FFOO IX=0004
BW=OOOO IY=0074
VOIR IE S Z AC P CY CW=00B2 BP=OOOO
0
0 0 0 1 0 1 0 DW=1388 8P=01FC
Use cursor keys to scroll data up and down
PS=0065 8tack+0 E80]
OS=0060
+2 340C
ES=FFOO
+4 0012
+6 5400
S8=0040
PS=0065 Stack+O 002A
+2 E80]
OS=0060
+4 140C
ES=FFOO
+6 5400
8S=0040
PS=0065 Stack+O 002A
OS=0060
' +2 E803
+4 340C
ES=FFOO
+6 5400
SS=0040
PS=0065 Stack+O 002A
+2 E803
OS=0060
+4 340C
ES=FFOO
+5 5400
SS=0040
PS=0065 'Stack+O 002A
+2 E803
OS=0060
+4 340C
ES=FFOO
+6 5400
SS=0040
F1 or '---1'
to return
83-6764A
6
NEe
V25N35 MINI·IE Plus
Figure 7. Real-Time Trace Buffer Display
Addr
00B02
Ctl
M R
R e a 1 - T i m e
Data External
P2
fA ff=l1111111 ff
T r a c e
D a t a
Record :
1 of 2271
astart:
FA
B82103
vdgroupqJ:
DI
AW,0321
B8 FF-=l1111111 FF
MOV
00B03 M R
21 FF=11111111 FF
00B04 M R
03 fF=11111111 ff
00B05 M R
MOV
nW,0321
00B06 M R
BB ff= 11111111 fF BB2103
FF=11111111 fF
00B07 M R
21
03 fF=11111111 fF
00B08 M R
CW,03BO
MOV
00B09 M R
89 Ff=l1l11111 FF B98003
BO Ff=11111111 FF
OOBOA M R
OOBOB M R
03 FF=11111111 FF
MOV
CW,0212
OOBOC M R
B9 FF=11111111 FF 891202
12 fF=1111l111 fF
OOBOD M R
OOBOE M R
02 FF=l1l1l111 FF
FC FF= 11111111 FF FC
CLR1
DIR
OOBOF M R
MOV
DS,BW
8E FF=11111111 FF 8EDB
00B10 M R
DB FF=1l111111 FF
OOB11 M R
MOV
DW,FFFF
BA FF=l111l111 FF BAFFFF
00B12 M R
OOB13 M R
FF FF=lll11111 FF
FF FF=11111111 FF
OOB14 M R
MOV
ES,DW
8E FF=l1l11l11 FF 8EC2
00B15 M R
C2 FF=11111111 FF
00B16 M R
lShow MK1 2Show MK2 3Set MKl 4Set MK2 Ctl-PgDn/Up:+/- 100 Ctl-End/Home:+/-10OO
8J.e7e&A
V25 PLUS AND V35 PLUS EMULATION
The V25 MINI-IE Plus oan emulate both the standard
V25 and the V25 Plus. This is accomplished by simply
switching the V25 in the emulator with the V25 Plus
chip. The emulator can be upgraded to support the V25
Plus at 10 MHz, either by changing the 16-MHz crystal
in the emulator with a 20-MHz crystal or by· using an
external 20-MHz frequency source. (Do not use an
external crystal as a frequency source because the
crystal may not oscillate due to probe cable effects.) In
addition to changing the emulator CPU, 10-MHz operation requires replacement of memory devices in the
emulator. The V25 MINI-IE Plus requires 70-ns access
time (or faster) and 32K-byte by a-bit static memory
chips when run at zero wait states and 10 MHz.
The V35 MINI-IE Plus can emulate the V35 in the same
manner as described above. Note that 10-MHz operation also requires the faster SRAMS. The V25 MINI-IE
Plus cannot be used to emulate either the V35 or V35
Plus devices; the V35 MINI-IE Plus cannot be used to
emulate either the V25 or V25 Plus devices.
The control program of the V25 MINI-IE Plus and V35
MINI-IE Plus will automatically sense the CPU in the
emulator upon power-up and adjust the internal Special Function Registers to support the installed CPU.
7
EI
V25N35 MINI·IE Plus
8
NEe
NEe
V40N50 MINI-IE
In-Circuit Emulator
NEC Electronics Inc.
Description
o Emulates JJPD70208/70216 at 8 MHz
o Controlled by powerful AFD-Sym monitor and
debugging program
- Symbolic full-screen debugger
- Uses function keys as well as direct command
entry
- Displays six window areas with second-level
break setup window
- Updates disp1ay information as program single
steps
- On-line assembler
-Evaluates and displays arithmetic expressions
- Displays color on color systems
- Programmable trace and symbol buffer sizes
-On-line help menus
- Macro command capability
o Parallel interface with host PC; interface card and
cable included
o Sample batch file contains demonstration
program
The V40 MINI-IE and VSO MINI-IE are low-cost in-circuit
emulators for the JJPD70208 (V40TM) and JJPD70216
(VSOTM) microcomputers. The MINI-IE is designed to be
used with an IBM PCIXT®, PC AT®, IBM PS/2., or compatible machine. The control software for the MINI-IE is
AFD-Sym (Advanced Full-Screen Debug with Symbols),
which acts as both a monitor and debugger. Debugging
with breakpoints and non-real-time tracing of executing programs are accomplished in software using a
V40NSO microprocessor located on theMINI-IE board.
Features
o Connects to target system via PGA or PLCC probe
o MINI-IE hardware
- 64K bytes of static RAM starting at address
0000:0
- MINI-IE reserved PROM at address F800:0
through FFFF:F
- MINI-IE memory may be disabled to use target
memories
- 32 bytes of MINI-IE I/O starting at address
8000:0
Ordering Information
Part Number
Description
EB-V40MINI-IE
pPD70208 (V40) PC-based MINI-IE with
adapter
EB-V50MINI-IE
pPD70216 (V50) PC-based. MINI-IE with
adapter
ADAPT68PGA68PLCC
Adapter for 68-pin PLCC socket
(shipped with MINI-IE)
HARDWARE
o Software break and trace capabilities
- Up to eight conditional breakpoints in break
definition mode
- Additional breakpoints can be given in the
command line
- Various actions can be programmed to take
place on a break
- Error checking of break entry conditions
The MINI-IE (figure 1) consists of a parallel interface
board providing bidirectional data communication and
a JJPD70208 or JJPD70216 emulation board (or MINI-IE
board). The parallel board fits into a free slot in the PC
and is hardwired for address 0278H within the PC I/O
space.
o Executes NEC .LNK absolute files and Microsoft
.COM and .EXE files
- Files can be downloaded to and uploaded from
the MINI-IE
- Supports real-time and single-step emulation
- User-programmable public symbol buffer size
The MINI-IE board consists of aJJPD70208 or JJPD70216,
32K bytes of EPROM, 64K bytes of static RAM, decoding logic, and a parallel interface. It can receive power
from the PC, the target system, or an external supply.
The MINI-IE board connects to the parallel board in the
PC by a 2S-line cable.
IBM PC/XT, IBM PC AT, and IBM PS/2 are registered trademarks of
International Business Machines Corporation.
Hercules is a registered trademark of Hercules Computer
Technology Inc.
V40 and V50 are trademarks of NEC Corporation.
60232-1
The MINI-IE can be connected directly into a 68-pin
PGA socket on the target system or into a 68-pin PLCC
socket on the target system through· adapter
ADAPT68P~68- PLCC. In this. configuration, the
MINI-IE RAM and EPROM can be disabled via jumpers
so that target memory is accessed, or a combination of
MINI-IE and target memories can be used.
~
~
NEe
V40/y50 MINI·IE
Figure 1.
V40/V50 MINI-IE Board (Component Side)
INI
..
T
nnnn,
III
a
=-
.17 .14.13 .15
s
s
.......
o
..•
a
~
V4~
II
HIG~At1
LOVRAM
YOO
I/OPAL
6b~OD
JD~~
tJul:JtJ~~
1
IlNE!
:.
o
'"
:.
"II
•
~
i7ilt
71155
HEHPAL
.8;!-6766A
Figure 2. AFD-Sym Main Screen
A'i'l 0207
SW 0000
CW 0089
DW FFFD
!'r---G
Gm
IX
IY
BP
SP
or
OCOO
018.4
0000
OlFE
GC
PS
DS
ES
SS
0221
0220
0000
0200
PC 0000
Stack +0
+2
+4
+6
HS 0220
FS 01BB
>G
>
2
E X E C U T I N G ***
:
A\oj',0220
682002
MOV
8ED3
MOV
DS, A~~
90
NOP
FA
DI
33CO
AW,AW
XOR
8Eeo
MOV
·ES,AW
90
NOP
Analyze
1<*1<
~lAIN
0000
0003
0005
0006
0007
0009
OOOB
8 9' A
00 00 00
CO 8E CO
O~ 00 33
BA FA FF
01 EE BA
2
HS
HS
HS
HS
HS
0013
0023
0033
0043
3
00
8E
AB
FC
EE
1
Step
2ProcStep 3Retrieve 4Help ON
0003
4
00
D8
8C
FF
BA
5
00
90
C8
BO
FO
.6
00
FA
AB
00
FF
7
00
33
E8
EE
BO
B
00
90
CO
BO
FD
C
00
FC
FB
60
FF
D
00
BF
40
EE
B8
E
00
80
90
BA
02
FFFF
340C
0012
0000
PSW F002
0
OC
00
B8
CO
B8
08
FC
BA
FF
01
F
00
01
EB
F9
00
2
02
00
BA
50
13
5BRK Menu 6
1
20
65
CC
BO
BO
V40
V DIR IE S Z AC
0 0 0 o· 0 0
1
DS:OOOO
DS:0008
DS:0010
DS:0018
DS:0020
DS:0028
DS:0030
DS:0038
DS :.0040
Ds:0048
0
B8
B8
FC
FF
EE
IntM:1
1
34
00
20
8E
65
00
CC
FA
BO
EE
7 up
2
12
00
02
,CO
00
33
BA
FF
50
BA
3
00
00
8E
90
AB
CO
FC
BO
EE
FD
4
00
00
D8
FC
8C
FB
FF
60
BA
FF
P CY
0 0
5
00
00
90
BF
C8
40
BO
EE
FO
B8
.
6 7
00.00
00 00
FA: 33
~O 01
AB E'8
90 EB
00 EE
BA F9
FF BO
02 00
........
,
;tti03LAL
£l1~<;:"e.
Y.a
~,,3
~ I W0i~i'; I
8 dn
, " "
,
!~~ i~'\~!
E
'2' , , , E tll,
9 Ie 10
r1
83-6767A
2
NEe
SOFTWARE
The control software, AFD-Sym, provides six windows
on the main screen display (figure 2).
• p.PD70208/70216 registers and flags and the top four
words of the stack
• Command entry line
• Offset addresses, opcodes, and disassembly of eight
lines of the program load area
• 80-byte memory dump area
• Second 80-byte memory dump area
• ASCII equivalent of the second 80M-byte memory
area
AFD-Sym controls all the monitor and debug functions of
the MINI-IE including uploading and downloading programs, program execution with or without breakpoints,
recording of trace history, dlsassembly, in-line code
assembly, and register/memory display and manipulation. The cursor may be moved anywhere within the
window displays for immediate change of the memory
areas, registers, flags, and breakpoints.
AFD-Sym software running on a PC requires 75K to 147K
bytes of system memory depending on the options
required. It may be copied to a hard disk or run directly
from the floppy diskette.
Emulation RAM area starting at address 0000:0 is partly
used by the AFD-Sym monitor and the interrupt vectors.
The lowest available user memory is indicated by the
segment registers after reset and depends on the trace
buffer size allocated. The AFD-Sym code in EPROM is
located at F800:0 and the following 32K bytes are reserved for this purpose.
Emulation
User programs loaded into emulator RAM or EPROM can
be executed in real-time or in single-step mode. Singlestep mode executes only one instruction; procedure
step executes an entire subroutine or software interrupt
routine. It is possible to Single-step a hardware interrupt
handler when the associated interrupt mode is selected.
Real-time execution is command activated and terminates when a breakpoint is encountered or the user
terminates execution from the keyboard. Program execution is also stopped when an exception interrupt or an
interrupt with an uninitialized vector occurs.
V40N50 MINI·IE
Programs generated using NEC's RA 70320 Relocatable
Assembler package allow symbols to be loaded directly
with the program code. Programs produced with development tools that generate .EXE or .COM files can be
loaded into the MINI-IE, but symbols must be loaded
separately. Several symbol files can be loaded into the
internal symbol table. The buffer used for symbol storage is allocated in the PC and can be varied in size from
1K to 64K bytes. Symbols can be added, deleted, and
renamed interactively.
Break Capabilities
Two types of breakpoints are available. Immediate breakpoints are entered directly with the execution command
and stop execution when the instruction at the specified
location is to be executed. The second type of breakpoint is specified in a separate breakpoint menu.
The breakpoint entry menu (figure 3) is a. second-level
menu and can be entered by F 5 key of the PC keyboard.
The menu contains six fields: breakpoint number, breakpoint conditions, a count, number of occurrences, and
action to be taken.
Up to eight address breakpoints can be defined in the
menu. They can be tagged with conditions and a count
value (up to 65,535) for the number of times the breakpoint is satisfied. Up to eight conditions may be entered
for each breakpoint, including satisfying other breakpoints and comparisons of register and memory contents (direct or indirect addressing modes) with those of
other registers, memory locations, and immediate
values.
JI!!!III!!II!I
The action field defines an operation or operations to be ~
done when a breakpoint occurs. Such actions include
trace on/off, analyze on/off, restart the breakpoint,
browse through a file, turn on/off the snap feature, and
jump to a different section of code.
To set up the analyze mode, an address field in the
breakpoint menu is left empty but conditions are placed
in the condition field. Then, on enabling the analyze
mode, the program is run in single-step mode while the
conditions are checked. In the snap mode, the instruction and the register values are put in the trace buffer
when conditions for a breakpoint are met.
Actions are performed when the occurrence counter is
equal to a specified count. This occurrence counter is
incremented only when all specified conditions are true.
When emulation is to resume after a breakpoint, an
option can be used in the GO command that will not
reset the occur field and the trace mode.
3
NEe
V40N50 "MINI·IE
Trace' Capabil ities
CONNECTION TO IBM PC
The MINI-IE trace is handled in software by the' AFDSym. When, trace is active, the current register pontents
and the top four words of the stack are saved to the traoe
buffer, along with the instruction that is to be executed
in single-step mode.' Program execution is .not in real
time when trace or analyze modes are enabled. Interrupt
routines are, however, executed in real time and 'are' not
recorded in the trace buffer (unless the user selects
interrupt step mode of the MINI-IE).
The V40 or V50 MINI-IE. can be ,used with IBM PC/XT/AT
or full compatibles, and on IBM PS/2. A monochrome,
CGA, Hercules@ color graphics or EGA adapter and
corresponding monitor is·'required. With IBM PC/XT/AT,
at least one expansion slot must be available for use with
the parallel interface adapter included with the MINI-IE.
The trace buffer resides in the emulation mel110ry and its
size can be set from 1K to 64K bytes by the user. The
default size of 4Kbytes allows 100 records to be stored:
Trace data, which can be displayed from the main SQreen
or from the menu screen, can be shown with register
contents or instructions only. See figure 4. Records can
be print~d or saved to a file. If symbols are lOaded, they
will be shown in the trace records.
,
At least one printer port address should' also be, available. IBM PS/2 models will use the system printer port
and will require a user-provided +5-volt dc power supply
to power the MINI-IE. A minimum of 75K bytes of free
memory is, needed to run AFD-Sym. A hard disk is not
required but is recommended.
The parallel board of the MINI-IE is hardwired for address
0278H of the PC I/O space. A provision on the parallel
board allows you to change the I/O address to a different
value, and a command line switch tells AFD-Sym where
the parallel board is located.
With the MINI-IE board conne~ted to the parallel board
via the 25-line cable,. running the AFD-Sym program
initiates communications with the MINI-IE and/or the
target system.
'
Figure 3. BreakpointEntry,Menu
AW
BW
CW
OW
02AO
0000
0089
FFFO
IX
IY
BP
SP
0000
0184
0000
01FE
PS
OS
ES
SS
0221
0220
0000
0200
PC OOIE
Stack +0
+2
+4
+6
HS 0~20
FS 01BB
FFFF
340C
0012
0001
PSW,F216
IntH:I
V OIR IE S
o 0 1 0
Z AC
P CY
0
1
1
V40
0
Defines the address of a breakpoint. With as the first character
the breakpoint is inactive. A breakpoint with an empty address field
will be checked on ~very break if count>O and an action is specified
for this breakpoint. With 'Alt'+n (n=1..8) the address of the actual
instruction will be stored to the corresponding breakpoint.
~tandard,segment PS:
,
Condition
Count Occur
3
SWTIM >= 0100 ............... ~ . ; ... .
1
1
1
4 -
. . ,. . . . . . . . . . . . . . . . . ,. . . . . . . . ." . .- .'. . .
BR# Break ADR
. 1 MAIN20
2 MAIN60
.5 -
6 -
-:
~
7 -
8 -
.
••••••••••••••••••••••••••••••••
IView TraCe 3Read Setup 4 Help OFF
.
5 CHD line
!II
.
•••
o
o
o
o
o
1
1
1
o
Action
trace ON
TR OFF A,ON
br
o
o '
o
o
7-Save Setup 9Clea'r BRIOClear OCC
83-6768A
4
NEe
Figure 4.
V40N50 MINI·IE
Trace Buffer Display
T R A C E
B U F F E R
0 I S P LAY
Buffer Offset
0
1< 1< -A
Begin of TRACE buffer I< 1<
MAIN20:
.~W=0221
IX=OOOO
0017 CALL
INITV40
BW=OOOO IY=0184
>Started by BR1
V OIR IE S
Z AC
P CY CW=0089 BP=OOOO
0 0 0 0 1 0 1 0 DW=FFFD SP=OlFE
INITV40:
AW=0221
IX=OOOO
0022 MOV
DW,FFFC
BW=OOOO IY=0184
V OIR IE S Z AC P CY CW=0089 l3P=OOOO
0 0 0 0 1 0 1 0 DW=FFFD SP=OlFC
0025 MOV
AL,OO
IX=OOOO
AW=0221
BW=OOOO IY=0184
V OIR IE S Z AC P CY CW=0089 BP=OOOO
0 0 0 0 1 0 1 0 DW=FFFC SP=OlFC
0027 OUT
DW,AL
AW=0200 IX=OOOO
BW=OOOO
IY=0184
V DIR IE S
Z AC
P CY CW=0089 BP=OOOO
0 0 0 0 1 0 1 0 DW=FFFC SP=OlFC
DW,FFFA
AW=0200
IX=OOOO
0028 MOV
BW=OOOO IY=0184
V OIR IE S Z AC P CY CW=0089 BP=OOOO
0 0 0 0 1 0 1 0 DW=FFFC SP=OlFC
Use cursor keys to scroll data up and down
F1 or
PS=0221
OS=0220
ES=OOOO
SS=0200
PS=0221
OS=0220
ES=OOOO
SS=0200
PS=0221
OS=0220
ES=OOOO
SS=0200
PS=0221
DS=0220
ES=OOOO
SS=0200
PS=0221
DS=0220
ES=OOOO
SS=0200
'~'
Stack+O
... 2
... 4
+6
Stack+O
+2
+4
+6
Stack+O
+2
+4
... 6
Stack+O
+2
+4
+6
Stack+O
+2
fFFf
340C
0012
0000
001.\
fFFF
340C
0000
001.~
FFFF
340C
0000
00lA
FFFF
340C
0000
001A
ffFF
+4 J40C
... 6 0000
to return
US1aOA
5
V40N50· MINI·IE
6
NEe
NEe
Package Drawings
7-1
II
NEe
Package Drawings
Section 7
Package Drawings
Package/Device Cross-Reference
7-3
18-Pin Plastic DIP
7-5
20-Pin Plastic DIP (300 mil)
7-5
20-Pin Plastic SOP (300 mil)
7-6
24-Pin Plastic DIP (600 mil)
7-6
28-Pin Plastic DIP (600 mil)
7-7
28-Pin PLCC
7-8
40-Pin Plastic DIP (600 mil)
7-8
44-Pin Plastic QFP (P44G-80-22)
7-9
44-Pin Plastic QFP (P44G 6-80-364)
7-9
44-Pin PLCC
7-10
48-Pin Plastic DIP
7-11
52-Pin Plastic QFP
7-12
52-Pin PLCC
7-13
68-Pin PLCC
7-14
68-Pin Ceramic PGA
7-15
74-Pin Plastic QFP
7-16
80-Pin Plastic QFP
7-17
84-Pin PLCC
7-18
84-Pin Ceramic LCC
7-19
94-Pin Plastic QFP
7-20
120-Pin Plastic QFP
7-21
132-Pin Ceramic PGA
7-22
7-2
NEe
P~ckage
Drawings
Package/Device Cross-Reference
Package
Device, "PO
Package
Device, "PO
lS-Pin Plastic DIP
7l0llC-S
7l011C-l0
44-Pin Plastic QFP
(P44G B-SO-3B4);
2.70 mm thick
71037GB-l0
7l0S4C-S
710S4C-10
20-Pin Plastic DIP (300 mil)
71054GB-S
71054GB-10
710S2C
710S3C
71055GB-S
71055GB-10
710S6C
710S7C
710SSC-S
710SSC-10
20-Pin Plastic SOP (300 mil)
71059GB-S
71059GB-10
44-Pin PLCC
71011G-S
7010SL-S
7010SL-10
710S2G
710S3G
70116L-S
70116L-10
710S4G-S
710S6G
71037LM-10
710S7G
710SSG-S
24-Pin Plastic DIP (600 mil)
71054C-S
71054C-10
2S-Pin Plastic DIP (600 mil)
71051C-S
71051 C-10
71059C-S
71059C-10
2S-Pin PLCC
71051 L-S
71051 L-10
71055L-S
71055L-10
4S-Pin Pla$tic DIP
71071 C-10
52-Pin Plastic QFP
7010SGC-S
7010SGC-10
70116GC-S
70116GC-10
52-Pin PLCC
71071 L-10
6S-Pin PLCC
70136L-12
70136L-16
7020SL-S
7020SL-10
71054L-S
71054L-10
70216L-S
70216L-10
71059L-S
71059L-10
40-Pin Plastic DIP (600 mil)
7010SC-S
7010SC-10
6S-Pin Ceramic PGA
70136Fl-12
70136R-16
70216R-S
70216R-10
71037CZ-10
71055C-S
71055C-10
74-Pin Plastic ·QFP
70136GJ-12
70136GJ-16
71054G-S
71055G-S
SO-Pin Plastic QFP
7020SGF-8
7020SGF-10
71059G-S
IB
7020SR-S
7020SR-10
70116C-S
70116C-10
44-Pin Plastic QFP
(P44G-80-22); 1.45 mm thick
7l051GB-S
71051 GB-l0
70216GF-S
70216GF-10
7-3
NEe
Package Drawings
Package/Device Cross-Reference (cont)
Package
Device, "PD
84-Pin PLCC
70320L
70320L-8
70322L-xxx
70322L-8-xxx
70325L-8
70325L-10
70327L-8-xxx
70330L-8
70332L-8-xxx
70335L-8
70335L-10
70337L-8-xxx
79011L-8
79021L-8
84-Pin Ceramic LCC
70P322KE-8
94-Pin Plastic QFP
70320GJ
70320GJ-8
70322GJ-xxx
7022GJ-8-xxx
70325GJ-8
70325GJ-10
70327GJ-8-xxx
70330GJ-8
70332GJ-8 -xxx
70335GJ-8
70335GJ-10
70337GJ-8-xxx
79011GJ-8
79021GJ-8
120-Pin Plastic QFP
70236GD-10
70236GD-12
70236GD-16
132-Pin Ceramic PGA
70236R-10
70236R-12
70236R-16
71641R
7-4
NEe
Package Drawings
18-Pin Plastic DIP
Inches
Item
Millimeters
A
B
C
22.86 max
1.27 max
.900 max
2.54 (TP)
.100 (TP)
D
0.50 ±0.10
.020
F
1.2 min
.047 min
G
3.5 ±0.3
.138 ±.012
H
0.51 min
.020 min
4.31 max
.170 max
K*
.050 max
~:gg~
5.08 max
.200 max
7.62 (TP)
.300 (TP)
~ : : : ~ : : : ;.1
A
.252
6.4
~g:6g
~ :gg~
M
0.25
N
0.25
.010
P
1.0 min
.039 min
.010
* Item K to center of leads
when formed parallel.
49NR·506B
P18C·l OO·300A. C
(4/89)
20-Pin Plastic DIP (300 mil)
Item
Millimeters
Inches
A
25.40 max
1.000 max
B
1.27 max
.050 max
C
2.54 (TP)
.100 (TP)
D
0.50 ±0.10
.020
F
1.1 min
.043 min
G
3.5 ±0.3
.138±.012
H
0.51 min
.020 min
4.31 max
.170 max
K*
~ :gg~
5.08 max
.200 max
7.62 (TP)
.300 (TP)
L
6.4
M
0.25
N
0.25
.010
P
0.9 min
.035 min
20
11
F::: 0-: : : : ;.1
A
.252
~g:6g
.010
~:gg~
* Item K to center of leads
when formed parallel.
P20C·l 00-300A. C
49NR·624B (11/89)
7-5
NEe
Package Drawings
20-Pin Plastic SOP (300 mil)
Item
Millimeters
A
B
C
13.00 max
0.78 max
.512 max
1.27 (TP)
.050 (TP)
Inches
.031 max
~&6~
~:gg~
0
0.40
E
F
0.1 ±0.1
.004 ±.004
1.8 max
.071 max
G
1.55
.061
H
I
7.7 ±0.3
.303 ± .012
K
5.6
.220
1.1
.043
~g:6~
11
R
A
.008
~:gg~
0.6 ±0.2
.024
~:gg~
0.12
.005
0.20
M
.016
20
6~!i~
[TI I$l
M
@i
P20GM·SO·300B. c
49NR·S94B (9189)
24-Pin Plastic DIP (600 mil)
hem
Millimeters
Inches
A
B
C
33.02 max
2.54 max
1.300 max
.100 max
2.54 (TP)
.100 (TP)
0
0.50 ±0.10
.020
F
1.2 min
.047 min
G
3.5 ±0.3
.138 ±.012
H
I
0.51 min
.020 min
4.31 max
.170 max
K*
~:gg:
5.72 max
.226 max
15.24 (TP)
.600 (TP)
L
13.2
M
0.2S
N
0.25
13
24
.520
~g:6~
.010
~:gg~
12
.010
J
A
* Item K to center of leads
when formed parallel.
IT]
L
[TI I$l
P24C-1oo·600
7-6
N
@i
49NR·S92B (9/89)
ttiEC
Package Drawings
2B-Pin Plastic DIP (600 mil)
Item
Millimeters
Inches
A
38.10 max
2.54 max
1.500 max
.100 max
2.54 (TP)
.100 (TP)
D
0.50 ±0.10
.020
F
1.2 min
.047 min
G
3.6 ±0.3
.142 ± .012
H
0.51 min
.020 min
4.31 max
.170 max
B
C
K*
:::gg~
5.72 max
.226 max
15.24 (TP)
.600 (TP)
L
13.2
M
0.25
N
0.25
.520
::g:6~
.010
:::gg~
1
.010
~
14
.1
A
* Item K to center of leads
when formed parallel.
0
L
M
0-15°
[£J f$l
P2SC-100·600A1
N
@I
49NR·514B
(5/89)
II
7-7
t\'EC
Package Drawings
28-PinPLCC
Item
A
B
C
MlIIlmeters
12.45 ±0.2
11.50
Inches
.490 ±.008
.453
0
11.50
12.45 ±0.2
.453
E
1.94 ±0.15
.076
F
0.6
.024
G
4.4 ±0.2
.
.490 ±.008
~:gg~
173 + .00ll
-.008
~:gg~
H
2.8 ±0.2
.110
.035 min
.134
.050 (TP)
K
0.9 min
3.4
1.27 (TP)
M
0.40 ±0.10
.016
N
0.12
.005
P
10.42 ±0.20
.410
Q
0.15
.006
T
0.8 rad
U
0.20
~:gg:
~:gg~
.031 rad
~g:~~
28
.008
~ :gg~
G
~~-~~~~~~~u
,
r
I
lf~T
1.0~ @I.I
N
P
P28L·50Al
49NR·52SB
(5/89)
4O-Pin Plllstlc DIP (600 mil) .
Item
Millimeters
Inches
A
B
C
53.34 max
2.100 max
2.54 max
2.54 (TP)
.100 max
.100 (TP)
0
0.50 ±0.10
.020
F
1.2mln
.047 min
G
3.6 ±D.3
.142 ±.012
H
0.51 min
.020 min
4.31 max
.170 max
J
5.72 max
.226 max
K*
15.24 (!P)
.600 (TP)
L
13.2
.520
M
0.25
N
0.25
~:6~
.010
~:gg:
~:gg~
.010
• Item K to center of leads when
formed parallel
P4OC·I00-600A
7-8
83.o·6140B (1/90)
NEe
Package Drawings
44-Pin Plastic QFP (p44G-80-22); 1.45 mm thick
Item
Millimeters
A
13.6 ±0.4
.535
~:g~~
B
10.0 ±0.2
.394
~ :ggg
c
10.0 ±0.2
.394
~ :gg~
D
13.6 ±0.4
.535
~:g~~
F
G
1.0
1.0
.039
.039
H
0.35
~g:~g
.014
.006
.031 (TP)
K
1.8 ±0.2
.071
~ :ggg
.039
~ :gg~
.006
~:gg~
L
1.0 ±0.2
0.15
N
0.15
~g:6~
C D
I$l
I
@I OJ
Enlarged detail of lead end
.006
~:gg~
P
1.45 ±0.1
.057
Q
0.0 ±0.1
1.65 max
.000 ±.004
.065 max
S
B
~:gg~
0.15
0.8 (TP)
M
A
Inches
Q
P44G-SO·22
49NR·636B (11/89)
44-Pin Plastic QFP (P44GB-BO-3B4); 2.70 mm thick
Item
Millimeters
A
13.6 ±0.4
.535
~:g~~
B
10.0 ±0.2
.394
~ :gg~
C
10.0 ±0.2
.394
~ :ggg
D
13.6 ±0.4
.535
~:g~~
F
G
1.0
1.0
.039
.039
H
0.35 ±0.10
.014
0.15
0.8 (TP)
.006
.031 (TP)
1.8 ±0.2
.071
~:ggg
0.8 ±0.2
.031
~:gg~
.006
~:gg~
K
P44GB--60·3B4·1
~g:6~
Inches
C
D
II
~:gg~
M
0.15
N
P
0.15
.006
Q
2.7
0.1 ±0.1
R
S
0.1 ±0.1
3.0 max
.106
.004 ±.004
.004 ±.004
.119 max
I$l
I
@I OJ
Enlarged detail of lead end
K
AUlliDwlDJlD[D~ ---.l
~~~l
M
~
a
R
49NR·556B (1/90)
7-9
NEe
Package Drawings
44-PinPLCC
Item
A
B
C
0
Millimeters
17.5 ±C.2
.689 ±.008
16.58
.653
16.58
.653
17.5 ±C.2
.689 ±.008
E
1.94 ±C.15
.076 ±.006
F
0.6
.024
4.4 ±C.2
.173 ±.008
2.8 ±C.2
.110 ±.008
G
H
0.9 min
.035 min
3.4
.134
K
M
1.27 (!P}
.050 (TP)
0.40 ±C.10
.016 ±.004
N
0.12
.005
P
15.50 ±O.20
.610 ±.008
a
0.15
.006
T
0.8 radius
.031 radius
U
0.20
~:6~
F:
Inches
.008
44
1
0
C
Jll
F
~:gg:
G
T
....-----P------.I
P44L·50A1·1
7-10
3190 83VL·58048
NEe
Package Drawings
48-Pin Plastic DIP
Item
Millimeters
Inches
A
63.50 max
15.24 [TP)
2.500 max
K
13.8
5.72 max
4.31 max
3.6±O.3
2.54 max
2.54 [TP)
1.1 min
0.51 min
0.50±O.10
.543
.225 max
.170 max
.142 ±.012
.100 max
.100 [TP)
.043 min
.020 min
.02O±.004
L
0.25
M
0.25
B
C
0
E
F
G
H
J
j
~:6~
.600 [TP)
.010
~:gg~
25
A
.010
[[J
c
---t~
0-15'
P4SC·l00-600A
~138B(6/89)
II
7-11
Package' Drawings:
52-Pin Plastic QFP
Item
MIllimeters
Inches
A
17.6 ±0.4
.693 ±.016
B
14.0 ±0.2
.551
c
14.0 ±0.2
:gg:
.551 ~ :gg:
D
G
17.6 ±0.4
1.0
1.0
.693 ±.016
.039
.039
H
0.40 ±0.10
.016
0.20
1.0 (TP)
.OOS
1.S ±0.2
.071
~:ggg
O.S ±0.2
.031
~
.006
~:gg~
F
K
M
0.15
N
P
0.15
Q
R
S
~g:J~
2.7
0.1' ±0.1
0.1 ±0.1
3.0 max
~
C 0
~:gg~
.039· (TP)
:gg:
.006
.106
.004 ±.004
.004 ±.004
.119 max
'K
.
Enlarged detail of lead end
~c+ ~
Q
P52GC·100-386
7-12
R
49NR-493B (5189)
NEe
Package Drawings
52-PinPLCC
Item
A
B
C
0
E
F
G
H
M""meters
20.1iO.2
.791 ±.008
19.12
19.12
20.1 iO.2
.753
.753
.791 ±.008
1.94 iO.15
0.6
.076 ±.006
.024
4.4 iO.2
.173 ±.008
2.8 iO.2
.110 ±.008
0.9 min
3.4
.035 min
.134
M
1.27 (IPl
0.40 iO.10
.050 (TPl
.016 ±.004
N
P
0.12
18.04 iO.20
.005
Q
T
0.15
0.8 radius
U
0.20
J
K
~~1~
F:
Inches
52
0
C
.710 ±.008
.006
.031 radius
.008
~.~~~
F
G
H
T
I+-------P-------+j
P52L·50A1
83YL·5805B
II
7-13
NEe
Package Drawings
68-PinPLCC
A
B
Item
MillImeters
A
D
25.2±O2
24.20
24.20
25.2±O.2
.992±.00S
.953
.953
.992±.00S
E
1.94±O.15
.076 ~:gg~
B
C
F
0.6
.024
G
4.4±O.2
.173~:gg~
H
2.S±O.2
.110~:gg~
K
Ii-
Inches
0.9 min
.035 min
3.4
.134
1.27 (IPI
.050 (IPI
M
0.40 ±O.10
.016~:gg~
N
0.12
.005
P
23.12±O.20
.910 ~:gg~
Q
T
0.15
O.S radius
.006
.031 radius
U
0.2O~:~~
.00s~:gg:
DDDDDDDD
68
D
C
F
T
....---....:.:..:...----P--------_
P68L-5OAH
(2/90)
83YL·5561B
N'EC
Package Drawings
68-Pin Ceramic PGA
Item
Millimeters
Inches
A
27.94 ± 0.4
D
27.94 ±0.4
E
F
1.27
.050
2.54 (TP)
.100 (TP)
G
2.8 ±0.3
H
0.5 min
.019 min
2.70
.106
4.57 max
.180 max
K
1.2 ±0.2 dia
L
0.46 ± 0.05 dia
M
0.5
[£J f$l
.020
@I
M
Top View
IE
A
~
I
Bottom View
0
0
0
0
0
0
0
@
0
0
0
0
0
0
@
0
10
0
0
0
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
11
0
8
0
7
0
0
6
0
0
5
0
0
4
0
0
3
@
0
0
0
0
0
0
0
@
0
2
0
0
0
0
0
0
0
0
0
H
G
F
E
D
C
B
K
A
49NR·528B
($/89)
7-15
II
ttlEC
Package Drawings
74-Pin Plastic QFP
Item
Millimeters
A
23.2 ±0.4
.913
B
20.0 ±0.2
.787 :: :gg~
c
20.0 ±0.2
.787
:::gg~
D
23.2 ±0.4
.913
:::g~~
2.0
1.0
2.0
1.0
.079
.039
.079
.039
H
0.40 ±0.10
.016
I
0.20
.008
J
K
1.0 (TP)
1.6 ±0.2
.039 (TP)
.063 ± .002
L
0.8 ±0.2
.031 :: :gg~
M
0.15
N
P
0.15
3.7
0.1 ±0.1
0.1 ±0.1
4.0 max
F1
F2
G1
G2
Q
R
S
::g:6~
A
Inches
B
:::g~~
F2
C D
:::gg~
F1
.006 :: :gg~
.006
.146
.004 ± .004
.004 ± .004
.158 max
Enlarged detail of lead end
~
Q
S74G.J·100-5BJ-1
7-16
R
49NR-347B (2190)
NEC
Package Drawings
SO-Pin Plastic QFP
Item
A
B
3>.0:102
Inche.
.929±016
+.00:1
.7fIl -.QC8
C
14.0:102
.551
0
F
17.6:10.4
10
G
OB
.6OO±016
.039
.031
+004
.014 -00)
H
MIllimeters
23.6:10.4
0.35:10.10
Q15
+.00:1
-roJ
K
1B:I02
.006
.031 erp)
+.00:1
.071 -.000
L
0.8:102
.Q31
M
Q15
N
P
Q15
OB(TP)
Q
R
S
+0.10
-0.05
2.7
0.1:10.1
0.1:10.1
3.0 max
c
0
+.00:1
-.000
006+004
.
-002
.006
.1
4
•
4
4
./
I"
c
0
)
)
)
)
)
)
4
)
)
~
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..,..
~
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X84KW-5OA
4
4
>
j
y
---~ ,-"-'
U
B
•
- r
•
~
838 L·5401 B (3/90)
7-19
NE~
Package ,Drawings
94-Pin Plastic QFP
A
Item
MIllimeters
Inches
A
23.2 ±O.4
.913 +.017
-.016
B
20.0 ±O.2
.787 +.009
-.008
C
20.0 ±O.2
.787 +.009
-.008
0
23.2 ±O.4
.913 +.017
-.016
F,
F2
G,
G2
1.6
0.8
.063
.031
.063
.031
'.6
0.8
H
0.35 ±O.10
.014 +.004
-.005
K
0.15
0.8 (TP)
1.6 ±O.2
.006
.031 (TP)
.063 ±.008
0.8 ±O.2
.031 +.009
-.008
0.15~:ci~
.006 +.004
-.003
0.15
3.7
0.1 ±O.l
0.1 ±O.l
4.0 max
.006
.146
.004 ±.004
.004 ±.004
.158 max
M
N
a
R
S
C 0
Detail of lead end
P
R
S94GJ·80·5BG·l
7-20
Q
S
(2190)
83YL·5810B
NEe
Package Drawings
120-Pin Plastic OFP
Item
Millimeters
Inches
A
32.0 ±0.4
1.260 ±.016
1.102
~ :gg~
B
28.0 ±0.2
c
28.0 ±0.2
1.102~:gg~
0
32.0 ±0.4
2.4
2.4
1.260 ± .016
.094
.094
F
G
~:gg~
H
0.35 ±0.10
.014
J
0.15
0.8 (TP)
.006
.031 (TP)
K
2.0 ±0.2
.079
~ :gg~
L
0.8 ±0.2
.031
~:gg~
~g:6~
M
0.15
N
P
0.15
3.7
0.1 ±0.1
0.1 ±0.1
4.0 max
Q
R
S
+ .004
.006 -.003
.006
.146
.004 ± .004
.004 ±.004
.157 max
Enlarged detail of lead end
fEDt
t
Q
P120GD·BO·5BB
tR
K
o
N
~+
49NR·653B (12/89)
•
7-21
Package Drawings
132-Pin Ceramic PGA
P N M L K J H G FED C B A
©
0
0
0
0
0
0
0
0
0
0
0
0
©
o
0
0
0
0
0
0
0
0
0
0
0
0
0
13
o
0
0
0
0
0
0
0
0
0
0
0
0
0
12
000
o
0
0
11
000
o
0
0
10
000
0
0
9
0
0
8
0
0
7
000
o
o
o
o
0
0
6
000
o 0
0
:
000
000
\.
j
000
°N°~~~
o 0 0 0
0
000 0
o
0
0
0
0
000 0
o
0
0
0
©
0
0
0
0
0
o 0
0
©
0
0
0
14
S
2
1
~torpin
J
!J
i
G
X132R-l00A
7-22
I
~ Ii
u u u u u uu u u u 0
-H-LK
W ~- _ .•
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RIB M@I
E
Item
Millimeters
Inches
A
3S.S6 ±O.4
1.400~:g~~
D
3S.S6 ±O.4
1.400~:g~~
E
1.27
.OSO
F
2.S4 (TP)
.100 (TP)
G
2.8±O.3
.110~:g~~
H
O.Smln
.019 min
.114
I
2.9
J
4.57 max
.180 max
K
s1.2±O.2
S.047~:gg~
L
s0.46 ±O.OS
S.018~:gg~
M
O.S
.020
6189
83YL·5817B
NEe
pPD70236 (V53)
16-Bit Microprocessor:
High-Speed, High-Integration, CMOS
NEC Electronics Inc.
Addendu m 1 (April 1991)
Scope
Changes
This addendum to the J,lPD70236 (V53) data sheet,
document no. 50159-1, revises the AC Characteristics
table to include data for operation with CPU clock
frequencies of 10, 12.5, and 16 MHz.
Pages 14 and 15. Replace with the AC Characteristics
table in this addendum.
AC Characteristics
= -10 to + 70°C; Voo = 5 V
TA
±10%; CL of output terminals
=
100 pF max; tCYK
=
CPU clock period; n
=
number of wait states·
Maximum CPU Clock Frequency
10 MHz
Parameter
Symbol
12.5 MHz
16 MHz
Min
Max
Min
Max
80
500
Min
Max
Unit
tCYK
100
500
tKKH
0.5tCYK - 12
0.5tCYK-10
0.5tCYK-7
62.5
500
ns
tKKL
0.5tCYK -12
0.5tCYK-10
0.5tCYK-7
Clocks (figure 1)
CLKOUT period
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time (1.0-3.5 V)
tKR
CLKOUT fall time (3.5-1.0 V)
tKF
12
10
12
250
10
40
250
31.25
ns
ns
7
ns
7
ns
250
ns
X1 input period
tcyx
50
X1 input high-level width
txKH
20
15
13
ns
X1 input low-level width
txKL
20
15
13
ns
X1 input rise time
txKR
7
5
5
ns
X1 input fall time
txKF
7
5
5
ns
X1 to CLKOUT delay
tOXK
10
35
10
35
10
35
ns
PCLKOUT period
tCYPK
4tcyx
1000
4tcyx
1000
4tcyx
1000
ns
PCLKOUT high-level width
tpKH
2tcyx - 12
2tcyx -10
2tcyx -7·
PCLKOUT low-level width
tpKL
2tCYX -12
2tCYX -10
2tCyx-7
PCLKOUT rise time (1.0-3.5 V)
tpKR
12
10
7
ns
PCLKOUTfall time (3.5-1.0 V)
tpKF
12
10
7
ns
ns
ns
ns
Input signal rise time
tlR
t
15
15
12
Input signal fall time
tlF
t
10
10
10
ns
Output signal rise time
tOR
t
15
15
12
ns
Output signal fall time
tOF
t
10
10
10
ns
Reset (figure 2)
RESET setup to CLKOUT !
tSRSTK
30
30
30
RESET hold from CLKOUT !
tHKRST
15
15
15
ns
RESET low-level width
tWRSTL
6
6
6
tCYK
RESOUT delay from CLKOUT!
tOKRO
0
t This parameter is not shown on the timing waveforms.
50159-1Al
40
0
40
0
. ns
40
ns
NEe
pPD79236
(V53),
Acjdendum 1 (April 1991)
.
..
AC Characteristics (cont)
Maximum CPU Clock Frequency
12.5 MHz
10 MHz
Parameter
Min
Symbol
Max
Min
16 MHz
Max
Min
Max
Unit
Read, Write (figures 3-12,16,18-19, 22,28-31)
Address/status setup time
before assertion of MRD,
lORD ~
tOARL t
Data hold time from MRD,
lORD t
tHRO
Address/status setup time
before assertion of MWR,
tOAWL t
t
0.5tCYK -15
0.5tCYK- 15
0.5tCYK-15
ns
0
0
0
ns
0.5tCYK -15
0.5tCYK- 15
0.5tCYK-15
ns
IOWR~
MWR, IOWR low-level width
twWL
t
(n+1)tCYK,...10
(n+1)tCYK-10
(n+ 1)tCYK -10
ns
0.5tCYK -15
0.5tcYK -15
0.5tCYK -15
ns
Address/status hold time from
MWRt
tHMWHA
BCYST delay from CLKOUT ~
tOKBC
5
BCYST low-level width
tBCBCL
tCYK-10
BCYST high-level width
tBCBCH
Address delay from CLKOUT ~
tOKA
Control 2 delay from CLKOUT
(Control 2 = MWR, IOWR in
DMA cycles)
t
45
(n+ 1)tCYK - 10
5
45
5
tCYK-10
tCYK-10
(n+ 1)tCYK - 10
(n+ 1)tCYK -10
40
ns
ns
ns
5
45
tOKCT2
5
45
tOKST
5
45
5
45
tFK
0
40
0
35
DSTB ~ delay from CLKOUT ~
tOKOS
5
45
5
45
5
DSTB low-level width
tOSOSL
(n+ 1)tCYK - 10
(n+ 1)tCYK - 10
(n+ 1)tCYK -10
DSTB high-level width
tOSOSH
0.5tCYK-10
0.5tCYK- 10
0.5tCYK- 10
CLKOUT to IOWR delay
tOKIW
0
45
0
45
0
40
ns
CLKOUT to lORD delay
tOKIR
0
45
0
45
0
40
ns
CLKOUT to MRD delay
tOKMR
0
45
0
45
0
40
ns
CLKOUT to MWR delay
tOKMW
0
45
0
45
0
40
ns
45
5
45
5
40
ns
Status delay from CLKOUT
~
Data float delay from CLKOUT
CLKOUT t to DSTB
t
t
5
45
5
40
ns
5
45
5
40
ns
5
40
ns
0
30
ns
40
ns
ns
ns
tOKOSH
5
Address/status output delay to
DSTB ~
tOAOSL
0.5tCYK-15
0.5tCYK-15
0.5tCYK-15
ns
Address/status hold time from
DSTB t
tHOSHA
0.5tCYK - 15
0.5tCYK-15
0.5tCYK - 15
ns
tOOSHO
0.5tCYK-15
0.5tCYK- 15
0.5tCYK-15
ns
Data output delay from address/
status output
tOAO
0.5tCYK -15
0.5tCYK- 15
0.5tCYK - 15
ns
Data output delay from
CLKOUT t
tOKO
5
Data output delay from DSTB
t
~
45
5
45
5
40
ns
tSOK
10
10
10
ns
tHKO
7
7
7
ns
Data hold time from DSTB high
tHOSO
0
0
0
ns
Data hold time from change
point of address or status
tHASO
0
0
0
ns
Data setup time to CLKOUT
Data hold time from CLKOUT
2
~
NEe
IIPD70236 (V53), Addendum 1 (April 1991)
AC Characteristics (cont)
Maximum CPU Clock Frequency
12.5 MHz
10 MHz
Parameter
Min
tHRWO
0
0
0
ns
tSRYK
10
10
7
ns
tHKRY
20
20
15
ns
8S8/8S16 setup time to
CLKOUT t
tSBSK
10
10
7
ns
8S8/BS16 hold time
from CLKOUT t
tHKBS
15
15
10
ns
HLDRQ setup time to
CLKOUT t
tSHQK
10
10
7
ns
HLDRQ hold time from
CLKOUT t
tHKHQ
20
20
15
ns
t to
tOKHA
5
tOFHA
0.5tCYK-15
0.5tCYK - 15
0.5tCYK-15
ns
Data hold time from
RIW t
READY setup time to CLKOUT
t
READY hold time from
CLKOUT t
Max
Min
16 MHz
Symbol
Max
Min
Max
Unit
Bus Sizing (figures 13, 14)
Bus Hold (figure 17)
CLKOUT
HLDAK delay
Output tristate to HLDAK delay
45
5
45
5
40
ns
Input Setup and Hold (figure 15)
NMI, INTPO-INTP7, CPBUSY
setup time to CLKOUT ~
tSIK
15
15
10
ns
NMI, INTPO-INTP7, CPBUSY
hold·time from CLKOUT ~
tHKT
15
15
10
ns
ns
Timer/Counter Unit, TCU (figure 20)
TCTLO-TCTL2 setup time to
CLKOUT +
tSGK
50
50
50
TCTLO-TCTL2 hold time from
CLKOUT +
tHKG
100
100
100
TCTLO-TCTL2Iow-level width
tGGl
50
50
50
taGH
50
50
50
TCTLO-TCTL2 high-level width
100
, ns
ns
ns
100
TOUTO-TOUT2 output delay
from CLKOUT ~
tOKTO
TCLK period
tCYTK
TCLK rise time
tTKR
15
15
15
TCLK fall time
tTKF
15
15
15
TCLK low-level width
tTKTKl
45
100
100
100
100
ns
ns
ns
ns
45
45
ns
TCLK high-level width
tTKTKH
30
30
30
ns
TCTLO-TCTL2 setup time to
TCLK t
tSGTK
50
50
50
ns
TCTLO-TCTL2 hold time from
TCLK t
tHKTG
100
100
100
ns
TOUTO-TOUT2 output delay
from TCLK ~
tOTKTO
100
100
100
ns
TOUTO-TOUT2 output delay
from TCTLO-TCTL2 ~
tOGTO
100
100
100
ns
3
&lEe
pPD70236 (V53),I'AddendUm 1 (A.,rU 199:1)
AC Characteristics (cont)
Maximum CPU Clock Frequency
10 MHz
Parameter
Symbol
Min
12.5 MHz
'Max
Min
16 MHz
Max
Min
Max
Unit
Serial Contro/Unit, SCU (figure 21)
RxD setup time to SCU internal
clock +
tSRX
ns
RxD hold time to SCU internal
clock f
tHRX
ns
TOUn
t to TxD
delay
500
tOTX
500
500
ns
Direct Memory Access, DMA (figures 23-26)
CLKOUT +to MRD, lORD
delay
t
tOKRH
0
45
0
45
0
40
ns
CLKOUT +to MRD, lORD
delay
+
tOKRL
0
45
0
45
0
40
ns
CLKOUT t to DMAAKO-DMAAK3
d.elay
tOKHOA
0
45
0
45
0
40
ns
lORD, IOWR +delay from
DMAAKO -DMAAK3 +
tOOARW
0.5tCYK -15
0.5tCYK -15
0.5tCYK - 15
ns
tORHOAH
0.5tCYK -,5
0.5tCYK ~ 15
.o.5tCYK - 15
ns
tOKCT1
0
45
0
45
0
40:
ns
tOWHRH
5
45
5
45
5
40
ns
tOKTCL
0
45
0
45
0
40
ns
tOKTCF
0
45
0
45
0
'40,
" , ns
45
0
45
0
40
ns
DfVlAAKO-DMAAK3
IORD.f
t delay from
CLKOUT to control 1, delay, .
(Control 1 = BUFEN, INTAK,
REFRQ)
lORD
t delay to IOWR t
TC OIJ~put delay from GLKOUT
t
TC off output delay from
CLKOUTt
T~ pullup delay from CLKOUT
t
tOKTCH
0
tTCTCL
tCYK - 20
tCYK- 20
tCYK - 15
tSEOK
35
35
35
ns
END low-level width
tEOEOL
100
100
100
ns
IORD,MRD low-level width
TC low-level width
END·setup time to CLKOUT
t
ns
tRR
2tCYK- 45
2tCYK- 45
2tCYK- 40
ns
IOWR, MWR low-level width
(expanded write)
tWW1
2tCYK- 45
2tCYK- 45
2tCYK - 40
ns
IOWR, MWR low-level width
(normal write)
tWW2
2tCYK- 45
2tCYK - 45
2tCYK- 40
ns
DMARQO-DMARQ3 setup time
to CLKOUTt
tSOQK
20
20
15
ns
CLKOUT +to DMAAKO-DMAAK3
delay
tOKLOA
0
45
0
45
0
40
ns
Interrupt Control Unit, ICU (figure 27)
INTPO-INTP7 low-level width
tlPIPL
100
100
100
ns
NEe
Notes:
NEe
NEe
Notes:
FIELD SALES OFFICES
EASTERN REGION
EASTERN REGION [cont]
EASTERN REGION [cont]
CENTRAL REGION [cont]
WESTERN REGION [cont]
901 Lake Destiny Drive
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TEL: 407-875-1145
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2525 Meridian Parkway
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TEL: 614-436-1778
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The Centre at Stirling
and Palm
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TEL: 305-436-8114
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WESTERN REGION
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NORTHERN CALIFORNIA
REGION
401 Ellis Street
PO. Box 7241
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TEL: 415-965-6200
FAX: 415-965-6683
NEe
NEe Electronics Inc.
CORPORATE HEADOUARTERS
401 Ellis Street
P.O. Box 7241
Mountain View. CA 94039
TEL 415-960-6000
TLX 3715792
~~
.
For literature, call toll-free 7 a.m. to 6 p.m. Pacific time:
1-800-632-3531
DOC NO. 50054-1
@1991 NEC Electronics Inc.lPrinted in U.S.A.
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