1991_Brooktree_Product_Databook 1991 Brooktree Product Databook

User Manual: 1991_Brooktree_Product_Databook

Open the PDF directly: View PDF PDF.
Page Count: 1106

Download1991_Brooktree_Product_Databook 1991 Brooktree Product Databook
Open PDF In BrowserView PDF
Quick Reference to Products

Bt101

5 - 5

Bt403

6 - 17

Bt463

4 - 279

Bt102

5 - 19

Bt424

6 - 27

Bt468

4 - 327

Bt103

5 - 33

Bt431

6 - 39

Bt471

4 - 371

Bt106

5 - 47

Bt438

6 - 61

Bt473

4 - 395

Bt107

5 - 61

Bt439

6 - 73

Bt474

4 - 421

Bt109

5 - 75

Bt450

4 - 7

Bt475

4 . - 455

Bt110

6 - 3

Bt451

4 - 23

Bt476

4-371

BU21

5 - 89

Bt453

4 - 57

Bt477

4 - 455

B1208

3 - 3

Bt453/883

4 - 75

Bt478

4-371

B1251

3 - 19

Bt454

4 - 91

Bt479

4 - 481

B1253

3 - 43

Bt455

4 - 91

Bt492

4 - 515

B1261

3 - 67

Bt457

4 - 23

BtS01

6 - 85

B1281

3 - 93

Bt458

4 - 23

BtS02

6 - 85

B1291

3 - 125

Bt458/883

4 - 111

Bt604

6 - 95

B1294

3 - 161

Bt459

4 - 135

Bt605

6 - 109

B1296

3 - 191

Bt460

4 - 187

Bt622

6 - 123

B1297.

3 - 197

Bt461

4 - 241

Bt624

6 - 123

Bt401

6 - 17

Bt462

4 - 241

Bt7l0

3 - 205

PixelVu

3 - 253

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego. CA 92121-2790
(619) 452-7580
(800) VIDEO IC

TLX: 383596
FAX: (619) 452-1249

PRODUCT
DATABOOK
1991

Thank you for your interest in Brooktree products.
Our commitment is to provide a steady stream of innovative products that offer the highest
quality, lowest cost/perfonnance solutions and back them with comprehensive support services.
These include timely and accurate technical information and responsive, experienced applications
assistance.
At Brooktree, listening to our customer's requirements is what we do first. Solving our
customer problems is what we do best.

Copyright © 1990 Brooktree Corporation All rights reserved.
Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability,
or manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable.
However, no responsibility is assumed by Brooktree Corporation for its use; nor for any infringement of patents
or other rights of third parties which may result from its use. No license is granted by its implication or
otherwise under any patent or patent rights of Brooktree Corporation.
VIDEODAC, RAMDAC, WindowVu, VideoNet, Pixel Vu, and True Vu are trademarks of Brooktree Corporation.
Brooktree is a registered trademark of Brooktree Corporation. Personal System/2 and PS/2 are registered
trademarks of IBM. Macintosh is a licensed trademark of Apple Computer, Inc. IMS is a registered trademark of
Inmos Limited.

Contents
Introduction

Quality Assurance

Imaging Products

RAMDACs

VIDEODACs

Peripherals

Packaging Information

r"f_1I,

~ales

"-.p....

uUu.:es

Product Index

..
..
..

Table of Contents
SECTION 1

INTRODUCTION

1- 1

SECTION 2

QUALITY ASSURANCE

2-1

SECTION 3

IMAGING PRODUCTS

3-1

Contents

3-2

SECTION 4

Bt208

18 MSPS 8-Bit Flash Video AID Converter

3-3

BU51

18 MSPS Single Channel8-bit Image Digitizer

3 - 19

Bt253

18 MSPS Triple Channel8-bit Image Digitizer

3 -43

Bt261

30 MHz HSYNC Line Lock Controller

3 - 67

Bt281

36 MHz Programmable Color Space Converter

3 - 93

Bt291

27 MHz RGB-to-YCrCb VideoNet™ Encoder

3 -125

Bt294

27 MHz YCrCb-to-RGB VideoNet™ Decoder

3 - 161

Bt296

27 MHz ll-bit TIL/ECL Translator

3 - 191

Bt297

27 MHz ll-bitECL/ITL Translator

3 -197

Bt710

Scaler/Orthogonal Rotator Element

3 - 205

PixelVu

Object-oriented Software Toolkit for Imaging

3 - 253

RAMDACs

4-1

Contents

4-2

Selection Guide

4-4

Bt450

66, 50, 30 MHz Triple 4-bit RAMDAC with 16 x 12 RAM

4-7

Bt451/457/458

165, 125, 110,80 MHz Triple 4-bit RAMDAC with 256 x
12 RAM/Single 8-bit RAMDAC with 256 x 8 RAM/Triple
8-bit RAMDAC with 256 x 24 RAM, 4:1 or 5:1
Multiplexed Pixel Inputs

4 -23

Bt453

66,40 MHz Triple 8-bit RAMDAC with 256 x 24 RAM

4 - 57

iv

Bnxktree®

SECTION 5

Table of Contents

Bt453/883

40 MHz MIL-STD-883 Version of Bt453

4 -75

Bt454/455

170, 135, 110 MHz Triple 4-bit/Single 4-bit RAMDAC with
16 x 12 or 16 x 4 RAM, 4: 1 Multiplexed Pixel Inputs

4 - 91

Bt458/883

110 MHz MJL-STD-883 Version of Bt458

4 - 111

Bt459

135, 110, 80 MHz Triple 8-bit RAMDAC with 256 x 24
RAM, 1: 1,4: 1, or 5: 1 Multiplexed Pixel Inputs, 64 x 64
Cursor

4 - 135

Bt460

135, 110,80 MHz Triple 8-bit RAMDAC with 512 x 24
RAM, 1:1,4:1, or 5:1 Multiplexed Pixel Inputs, 64 x 64
Cursor

4 - 187

Bt4611462

170, 135, 110, 80 MHz Single 8-bit RAMDAC with 1024 x 8
RAM, 256 x 8 Alternate RAM, 3:1, 4:1, or 5:1 Multiplexed
Pixel Inputs

4 - 241

Bt463

170, 135, 110 Triple 8-bit True Color Window RAMDAC
with (3) 528 x 8 RAM, 1:1,2:1, or 4:1 Multiplexed Pixel
Inputs

4 -279

Bt468

200, 170 MHz Triple 8-bit RAMDAC with 256 x 24 RAM,
8: 1 Multiplexed Pixel Inputs, 64 x 64 Cursor

4 - 327

Bt471/476/478

80, 66, 50, 35 MHz Triple 6-bit/8-bit RAMDAC with 256 x
18 or 256 x 24 RAM

4 - 371

Bt473

80,66, 50, 35 MHz Triple 8-bit True Color RAMDAC with
(3) 256 x 8 RAMs

4 - 395

Bt474

85,66 MHz Triple 8-bit RAMDAC with 256 x 24 RAM

4 - 421

Bt47S/477

80,66,50,35 MHz Triple 6-bit/8-bit Power-Down
RAMDAC with 256 x 18 or 256 x 24 RAM

4 -455

Bt479

80, 66, 50, 35 MHz Triple 8-bit RAMDAC with 1024 x 24
RAM, Window Management

4 - 481

Bt492

360 MHz Single 8-bit RAMDAC with 256 x 8 RAM

4 - 515

VIDEODACs

5-1

Contents

5-2

Selection Guide

5-3

BUOl

50, 30 MHz Triple 8-bit VIDEODAC

V

5-5

Table of Contents

SECTION 6

Btl02

75 MHz Single 8-bit VIDEODAC

5 - 19

Btl03

75, 30 MHz Triple 4-bit VIDEODAC

5 - 33

Btl06

50, 30 MHz Single 8-bit VIDEODAC

5 -47

Btl07

400 MHz Single 8-bit VIDEODAC with 2:1
Multiplexed Pixel Inputs (IOKH/100K ECL)

5 - 61

Btl09

250 MHz Triple 8-bit VIDEODAC, TDC1318 Pin
Compatible (IOKH ECL)

5 -75

Bt121

SO, 50 MHz Triple 8-bit VIDEODAC, On-Chip Voltage
Reference and Analog Output Comparators

5 - 89

PERIPHERALS

6-1

Contents

6-2

Bt110

100 ns Octal8-bit D/A Converter with Standard MPU
Interface

6-3

Bt401/403

250 MHz 256 x 8 Pipelined Static RAM (IOKH ECL)

6 - 17

Bt424

250 MHz 40-bit Multi-Tap Video Shift Register (10KH
ECL/ITL)

6-27

Bt431

64 x 64 Pixel User-Definable Cursor, Cross Hair Cursor

6-39

Bt438

250 MHz Clock Generator Chip for CMOS RAMDACs

6-61

Bt439

200 MHz Clock Generator/Synchronizer Chip for
CMOS RAMDACs

6 -73

Bt501/502

10KH/100K Octal ECL/ITL Bidirectional
Transceiver/Translator

6- 85

Bt604

125 MHz Dynamically Programmed Timing Edge
Vernier

6 -95

Bt60S

125 MHz Programmable Timing Edge Vernier

6-109

Bt6221624

Dual Channel and Quad Channel Delay Lines, Very
High-Speed,10KH ECL-Compatible

6-123

vi

Table of Contents

SECTION 7

PACKAGING INFORMATION

7-1

Contents

7-2

Part Numbering System

7-3

Device Marking

7-4

Thennal Resistance Infonnation

7-5

Packaging Drawings

SECTIONS

SECTION 9

Plastic DIP

7-6

CERDIP

7-8

Ceramic Sizebraze DIP

7 - 11

Ceramic Cavity Down DIP

7 - 14

Plastic J-Lead (PLCC)

7 - 15

Ceramic J-Lead (CERQUAD)

7 - 18

Ceramic Pin Grid Array (PGA)

7 - 19

Ceramic Flatpack with Heatsink

7 - 22

Ceramic Leadless Chip Carrier

7 - 23

Plastic Quad Flat Pack (PQFP)

7 - 24

SALES OFFICES

8- 1

Brooktree Sales Offices

8-2

North American Representatives

8-3

North American Distributors

8-7

E~rop~m} Rcpr~s~ntrlti,,'es/Dis!!"ib~tc:~

R - 11

Japanese Representatives/Distributors

8 - 14

Asia-Pacific Representatives/Distributors

8 - 14

PRODUCT INDEX

9-1

vii

SECTION 1

...--- INTRODUCTION ----.

Company Facts
Brooktree began operations in 1983 following the
development of an advanced architecture for data
conversion. The architecture, invented by company
co-founder and chief scientist Henry Katzenstein,
permits the combination of high-performance analog
and digital circuitry on a single monolithic integrated
circuit which can be manufactured using standard
bipolar or CMOS processes.
Brooktree Corporation is a privately held company
located in San Diego, California. Facilities of
133,000 sq. ft house all design, test, and quality
assurance activities as well as marketing, sales, and
administration.
Brooktree has established a
worldwide network of distributors and factory
representatives, with offices in the United States,
Europe, and the Far East.
The company's products are manufactured under
agreements with several domestic and international
foundry sources. Second-source agreements are in
effect with a number of suppliers.
Since its first volume shipments in 1985, Brooktree
has achieved leadership share in the workstation
graphics market, and a large share of the emerging
markets for PC graphics and electronic imaging.

Products
Our first product, introduced in early 1985, was a 75

MHz 8-bit CMOS video digital-to-analog converter
(VIDEODAC). By mid-1985, Brooktree had introduced

1-2

INTRODUCTION

six CMOS video digital-to-analog converter products
(our VIDEODAC line) to the high-performance
graphics market. Further system level integration led
to our family of RAMDACs, which combine triple
VIDEODACs, color palette RAMs, and pixel input
multiplexers on a single chip. Recently introduced
products include a 360 MHz bipolar RAMDAC and
several next-generation CMOS RAMDACs.
In 1988, Brooktree entered the image acquisition
market with it's first CMOS flash video A/D
converter. Further system level integration led to our
family of Image Digitizers, which combine one or
more AID converters and many additional functions
required to digitize a video signal. Additional
products are under development to enable image
acquisition to be a "drop-in" solution.

Products for the automatic test equipment and
instrumentation markets include programmable
timing verniers, high-speed comparators, and
load/driver/comparator circuits.

Strategy
Brooktree will combine the elements of its
high-performance mixed signal design capabilities
and proprietary test technology to provide a unique
family of application-specific products. We will
continue to develop highly-integrated products for use
in computer graphics and imaging while introducing
enabling technologies aimed at solving problems in
the automatic test equipment and instrumentation
markets.

Data Sheet Designations
Advance Information
This is the first official information released about a potential product. The datasheet contains basic information
about the product and contains the target parametric and functional specifications. It usually precedes sample devices
by approximately six months. This datasheet has the phrase "Advance Information" in the upper left comer on the
front page.

Preliminary Information
This datasheet is released with sample devices. It contains a more extensive discussion of device operation and
provides more complete parametric information. The functional operation is fully defmed and the parametric
information is the result of early testing of the initial devices. Not all of the parametric specifications may be fully
tested or characterized. This datasheet has the phrase "Preliminary Information" in the upper left comer on the front
page.

Final datasheet
This datasheet evolves from the Preliminary Information datasheet. It is a result of test information collected from
fully characterized devices. This datasheet is distinguished by the absence of any designation, except the part
number, at the top of the front page.

Device Designations
Engineering Sample
Devices which have exhibited most of the functionality for which it was designed. Engineering samples are used to
enable selected customers to evaluate the device as early as possible. While some of the AC and DC parameters may
be tested, the accuracy or completeness of the testing is not guaranteed. In addition, the product has not been put
through Brooktree's quality and reliability testing. They have standard markings with an additional "ES" marked on
top of the package. These devices have a Preliminary datasheet under document control.

Pre-Qual
These devices have production silicon, testing, and bum-in. Most characterization is done, but the device must still
pass a QA life-test qual. These devices have standard markings with an additional "PQ" marked on top of the
package. These devices have a Preliminary datasheet under document control.

Full Production
These devices have production silicon, testing, bum-in, and have successfully passed a QA life-test qual. These
devices have standard markings with no additional designators. These devices have a Final datasheet under document
control.

INTRODUCTION

1-3

SECTION 2

.-- QUALITY ASSURANCE -----.

-

Quality Assurance

Introduction
The value of a product is measured by how well it is
designed, manufactured and tested and how well it
continues to perform over time. This value can be
represented in quantitative terms by stating levels of
quality and reliability. Brooktree determines these
quality levels by performing industry recognized
evaluation and monitoring programs for all products
it manufactures.
Quality is a critical aspect of product success, and we
have established an aggressive schedule of measuring,
testing and monitoring the product to assure our
customer that each device will perform to the highest
quality and reliability standards. We have made
substantial investments in experienced personnel and
in state-of-the-art capital equipment for our design,
manufacturing, and quality assurance departments.

procedures assure with a high degree of confidence
that a lot will not be approved for shipment if certain
levels of quality are not met. For sampling plans, the
operating characteristic curve illustrated in Figure 1
shows the relationship of lot quality versus
probability of acceptance. Point A on the curve is
termed AQL; it signifies the lot quality in percent
defective (0.065%) that will give a high probability
(95%) of lot acceptance. Point B on the curve is
termed LTPD and signifies the unsatisfactory level of
quality where the lot will be rejected 90% of the time.
Brooktree performs quality conformance testing using
an acceptance sampling method based on
MIL-STD-I05D and MIL-M-38510H.

Product Quality

Manufacturing process control is accomplished
through the efforts of the Document Control
Department. An effective plan for document sign-off
and distribution ensures that updated documents are
reviewed and are made available immediately to
affected operations.

Quality is a measure of product conformance to the
specifications. This is determined by measuring the
percentage of defects in a given sample size. The
Quality Assurance program includes material
inspections which employ industry-standard Lot
Tolerance Percent Defective (LTPD) and Acceptable
Quality Level (AQL) sampling plans. These sampling

Brooktree's Quality Assurance program imposes strict
requirements on vendors, and monitors their
performance through inspection of incoming
materials and regular audits of the vendor's facilities
and quality methods. Figure 2 is a generalized
standard product manufacturing flow which illustrates
the manufacturing steps and quality assurance

100%

r-~~~.----r---.------------------~

...............=1A-

90% I---+-~~:::........--l"\---------l
80% ~--+---44--~--~------------------~
70%
Probability of
Lot Acceptance

"'\

60%
50% 1----f----1H--f----1f---\-'r--------l
40%

I---+--t+--+--I--~\r____----_l

30%

f---+-I+--+-I-----\-\------I

:~: ~..-...-....-...+..-....-...-...~.. 4.l-...-...-...~..-...-...-...+.-....-...-...-...-....~..~r
..B-.!----------~
0.03 0.06 0.09 . . . . . . . . %
Lot Quality (Percent Defective)

Figure 1.

2 • 2

SECTION 2

Lot Quality vs. Probability of Acceptance.

Bnxkt:ree®

Quality Assurance

I
I
I

I
I

Commercial Plastic
Package

Mold and Cure

Wafer Probe
Wafer Saw and Dice
~

I
I
J

I

High Magnification Visual

I

I

Die Attachment

I

I

Wire Bonding

I

Low Magnification Visual

I

Commercial Hermetic Package

J

I

Seal

I

l
l
I

Stabilization Bake
Method 1008 Condo C
Temperature Cycle 10 cycles
Method 1010 Condo C

I

Fine and Gross Leak
Method 1014

I

External Visual Inspection

I

Preburn-in
Electrical Test

I

Lot Sample Bum-in

i

!lcstbu:7I.-L-;.
Electrical Test

II
I

Wafer Fabrication

I
I

I

Constant Acceleration
Method 2001 Condo E

I
I
I

I
~

I

J
J
I
I
I

I
J

i

I Quality Conformance Inspection J
Figure 20

Standard Product Manufacturing Flow.

QUALITY ASSURANCE

2 - 3

Quality Assurance
monitors used for all our products. The Brooktree
quality assurance program conforms to the program
guidelines as specified in MIL-Q-9858.

Product Reliability
Reliability is quality over time, a measurement of how
long the product continues to perform to original
specifications. This must be guaranteed by using a
worst-case design methodology, precisely controlled
wafer-processing, and manufacturing assembly and
testing to highest quality standards.
Verification of product reliability is accomplished
through accelerated life testing and physical and
environmental stress testing.
The stress tests
performed for product qualification are listed in Tables
1 and 2. These tests are repeated at six-month
intervals to verify continuing process and product
integrity.
Strict engineering change control
procedures are used to assure a controlled process.

Figure 3 is an idealized graph of device failure rate vs
time, often called the Bathtub Curve. Three distinct
Region A is
regions are of importance.
characterized by high failure rates that show up in
early usage and then decrease with time. This area of
early life failures needs to be eliminated prior to
product being shipped to the final consumer. The
early life failure rate is minimized by screening
procedures, the most common of which is bum-in
testing performed at the device and/or system level.
Region B is characterized by a constant failure rate,
and indicates the normal operating region that will
assure maximum useful service and reliability.
Region C indicates the wearout region where device
failure rate increases. The wearout region is seldom
reached in well-designed semiconductor integrated
circuits under normal operating conditions. Results
of accelerated life testing are extrapolated to estimates
of in-service reliability through use of the Arrhenius
model.

Product Development
Screening is performed to eliminate early-failure
devices and to conform to military requirements.
Military grade products are tested in conformance to
MIL-STD-883C. The basic method used to estimate
product life is accelerated environmental testing.
These tests expose the product to stresses greater than
expected in actual use. The number of device failures
that occur can be related to the magnitude of the stress
applied. The common practice is to express the
results in failures in 109 hours, or FITs (one FIT is
equal to one failure per billion device hours of
operation. It can also be expressed in the common
notation of 0.0001 % failures per 1000 hours).

~

REGION A

~

Quality and reliability planning begins with the
product development cycle. It is vital that every
possible effort to increase the reliability is made
during the development cycle. This is achieved by
defining specific design goals, using proven reliable
materials and manufacturing methods, and
implementing controlled production processes with
accurate testing and monitoring.

REGION B

NOIDlal usefill operating "'l!ion

REGION C

Wearout region

It.

I
z

Decreasing failure ra/e

Constant fanure ra/e

haeasing failure ra/e

11MB

Figure 3.

2·4

SECTION 2

Device Failure Rate vs. Time.

Quality Assurance

Design
Brooktree's engineering department has established a
comprehensive design methodology developed to
produce reliable devices. Product definition begins
with experienced system designers who can accurately
specify the electrical interface and functional
boundary requirements. This assures that all new
devices will have specifications and worst case
operating and environmental conditions identified
before design begins.
Design engineers use schematic capture and
simulation software to verify the operation of the
design over temperature, power supply, and
processing varlatlons.
Design reviews require
designers to demonstrate to the Quality Assurance
department that their design will meet or exceed
reliability rules, including allowable amount of
electrostatic discharge (ESD), latch-up protection
(CMOS products), and current density (to prevent
metal migration). Computer simulation of each circuit
design is done using a worst case methodology.
Conformance to strict layout rules gives products
immunity to process variation while maximizing
reliability. An extensive set of checks is provided by
several state-of-the-art CAD tools that assure the
design layout is correct and that wafers can be
consistently processed with confidence in yield and
reliability.

Wafer Probe
Wafer probe is performed at Brooktree to ensure the
tightest quality and reliability controls early in the
life of the product. Wafer probe test conditions and
limits are guard banded to ensure early removal of
defective devices. Correlation between the final test
programs and probe programs is an effective gate to
prevent a nonfunctional device from entering the
assembly operation. Rejected dice are marked with an
ink dot to allow easy identification after the
individual die is scribed from the wafer.

Device Assembly
lite Quaii(y As.surance aepaIi. flle.w. i(H..jJl~LU.lS Ui~
performance of various processing steps by requiring
mandatory sampling of each lot moving through
critical quality operations. We have instituted eight
sampling points or gates in the assembly area: wafer
inspection, material inspection, first QA die visual
(high magnification), die attach control, second QA
die visual (low magnification), QA hermeticity check,

QA final inspection, and QA outgoing audit. Daily
monitoring and audits of equipment and operators
ensure that the final product meets all predefined
quality criteria.

Device Packaging
Brooktree packaging uses standard, semi-custom and
custom packages. Package outlines and foot prints
comply with JEDEC and SEMI standards whenever
possible. Since product performance is affected by
packaging design, custom packages are constructed
when necessary to preserve the reliability and
performance of the enclosed device.

Final Testing
Final electrical testing is performed at Brooktree
using state-of-the-art test equipment and techniques.
Test parameters and test conditions are such that
proper performance is guaranteed to data sheet
requirements. Test limits are guard banded to
compensate for tester inaccuracy, thereby minimizing
measurement correlation errors between the factory
and customer. To comply with quality conformance
requirements, QA verifies proper processing, proper
electrical performance over specified operating
temperatures and voltage ranges, and visual criteria.

Qualification
All products we manufacture are labeled to show the
classification of the products reliability for consumer
use. Each product datasheet contains a designation as
to the product development and specification
parameters status. The product datasheet designations
are Advanced, Preliminary, and Final. When the
device has been fully characterized to all the
specifications and datasheet parameters, and has
completed the environmental tests outlined in Tables
I and 2, it is labeled production-worthy and labeled a
Final Data Sheet.

Failure Analysis
Even under the strictest of standards, failures do occur.
To control this situation and learn from it, the failure
analysis gtuup iJtal.~~flc,:) .tt;HctL:I:~y PJ.c,!:;!'oSl.-t'; ai"...:!
performs corrective action on failures from in-house
stress testing as well as customer field returns.
Brooktree provides customers with specific feedback
so that the customer can be assured that appropriate
action has been taken.

QUALITY ASSURANCE

2 . 5

•

Quality Assurance

Description

Methods and Conditions*

Sample /
Max. Reject

High Temperature
Operating Life
Electrical

2000 hours, T A = 125 0 C ***

280
«400 FIT)

TA=Tmax

****

High Temperature
Storage
Electrical

2000 hours, T A = 2000 C

.55/0

Temperature Cycle

Method 1010, condition C,
-65 0 C / +150 0 C, 500 cycles
TA=Tmax

116/0

Method lOll, condition B,
_55 0 C / +125 0 C, 200 cycles
TA=Tmax

116/0

Pre-conditioning
Temperature Cycle
Temperature Cycle
Electrical

-400 C / +150 0 C, 20 cycles

153/0

Pre-conditioning
Temperature Cycle
Pre-conditioning
Temperature/Humidity
Steady-State
Temperature/Humidity
Electrical

-65 0 C / +1500 C, 10 cycles
85 0 C /85% RH, 24 hours,
unbiased
85 0 C / 85% RH, 1500 hours,
biased
TA=Tmax

Pressure Cooker

125 0 C, 2.3 atm, 288 hours

Electrical
Thermal Shock
Electrical

Electrical

TA=Tmax

Notes

electrical at 16, 48, 168,
500, 1000, 1500, 2000
hours
electrical at 500,
1000, 1500, 2000
hours

electrical every 500
cycles

00 C / + 125 0 C 3000 cycles
TA=Tmax
195/1

plastic package only

electrical at 500, 1000,
1500 hours
77/1

plastic package only

3 sets

1 set from each of 3
wafer lots

TA=Tmax

Destructive Physical
Analysis

SEM - surface and cross
section

*Test methods reference MlL-STD-883C.
**Samples to be selected from 3 wafer lots (each lot shall be processed with a minimum of 1 week
separating it and the other two wafer lots.
***Power supplies shall be set to 0.5 V less than the absolute maximum specified supply voltage;
T A shall be reduced, if necessary, to guarantee TJ to be less than 175 0 C for ceramic packages, or less
than 1500 C for plastic packages.
****FIT shall be calculated using the Ahhrenius acceleration model and the following assumptions:
Ea = 0.5 eV if no failures; if failures, Ea to be determined based upon failure mechanism.
Ts = 55 0 C (derating temperature)
confidence level = 60%

Table 1.

2 - 6

SECTION 2

Wafer Foundry Tests**.

Brod.itree®

Quality Assurance

Methods and Conditions*

Sample /
Max. Reject

External Lead Plating
Thickness
Solderability

Method 2003

4/0

Resistance to Solvents

Method 2015

4/0

Internal Visual
Bond Strength
Die Shear

Method 2010
Method 2011
Method 2019

4/0

External Lead
Integrity
Fine Leak
Gross Leak

Method 2004, condition B

34/2

Description

4 units /
all leads

for CERDIP only
for CERDIP only

Method 1014, condition A or B
Method 1014 , condition C
Method 1010, condition C,
_65 0 C / + 1500 C, 500 cycles
TA=Tmax

116/0

Method lOll, condition B,
_55 0 C / +125 0 C, 200 cycles
TA=Tmax

116/0

Preconditioning
Temperature Cycle
Temperature Cycle
Electrical

-40 0 C / +150 0 C, 20 cycles

153/0

Steady-State Temp.
and Humidity
Visual

85 0 C / 85% RH,
1500 hours, biased

50/0

Method 2002, condition B
Method 2007, condition A
Method 2001, condition E,
YI axis only
Method 1014, condition A or B
Method 1014, condition C
TA=Tmax

34/2

Temperature Cycle
Electrical
Thermal Shock
Electrical

Mechanical Shock
Vibration
Constant Acceleration
Fine Leak
Gross Leak
Electrical

Table 2.

Notes

00 C / +125 0 C, 3000 cycles
TA=Tmax

electrical every 500
cycles
empty (dummy) packages
may be used

Monolithic Hermetic Package Assembly Tests**.

QUALITY ASSURANCE

2 - 7

Quality Assurance

Description

Methods and Conditions*

Sample /
Max. Reject

Salt Atmosphere
Fine Leak
Gross Leak

Method 1009
Method 1014, condition A or B
Method 1014, condition C

34/2

Resistance to
Soldering Heat
Fine Leak
Gross Leak
Electrical

15 sec dip to with 1/8" of body
in solder at 260° C
Method 1014, condition A or B
Method 1014, condition C

22/0

SEM - surface and
cross-section

3 sets

Destructive Physical
Analysis

Notes

1 set from each of 3
assembly lots

*Test methods reference MIL-STD-883C.
**Samples to be selected from 3 assembly lots (each lot shall be processed with a minimum of 1 week
separating it and the other two assembly lots.

Table 2.

2 -8

SECTION 2

Monolithic Hermetic Package Assembly Tests**,
(Continued)

BJl)(j{tree®

Quality Assurance

Methods and Conditions*

Sample I
Max. Reject

External Lead Plating
Thickness
Solderability

Method 2003

4/0

Resistance to Solvents

Method 2015

Description

Notes

4 units /
2 leads

X-Ray

4/0
4/0

Mechanical Shock
Electrical

Method 2002, condition B
TA=Tmax

25/l

Temperature Cycle

Method 1010, condition C,
_65 0 C / +150 0 C, 500 cycles
TA=Tmax

116/0

Method 1011, condition B,
_55 0 C / +125 0 C, 200 cycles
TA=Tmax

116/0

Preconditioning
Temperature Cycle
Temperature Cycle
Electrical

--400 C / +150 0 C, 20 cycles

153/0

Preconditioning
Temperature cycle
Preconditioning
Temperature!Humidity
Steady-State
Temperature!Humidity
Electrical

-65 0 C / +150 0 C 10 cycles

Electrical
Thermal Shock
Electrical

Pressure Cooker
Electrical

0° C / +125 0 C, 3000 cycles
TA=Tmax

electrical every 500
cycles
195/1

85 0 C / 85% RH, 24 hours,
unbiased
85 0 C / 85% RH, 1500 hours,
biased
TA=Tmax

125 0 C, 2.3 atm, 288 hours

electrical at 500, 1000,
and 1500 hours
77/1

TA=Tmax

Table 3.

Monolithic Plastic Package Assembly Tests".

QUALITY ASSURANCE

2 - 9

Quality Assurance

Methods and Conditions*

Sample I
Max. Reject

Salt Atmosphere

Method 1009

34/2

High Temperature
Operating Life
Electrical

TA = 125° C (TJ < 150° C),
1500 hours
TA=Tmax

150
«400 FIT)
***

Preconditioning
Pressure Cooker
Infra-Red Reflow (lR)
Pressure Cooker
Electrical

125° C, 2.3 atm, 72 hours

45/0

PLCC packages only

45/0

PLCC packages only

45/0

PLCC packages only

Description

electrical at 500, 1000,
1500 hours

3 cycles
125° C, 2.3 atm, 200 hours
TA=Tmax

Preconditioning
Pressure Cooker
Infra-Red Reflow (lR)
Temperature Cycle

125° C, 2.3 atm, 72 hours

Electrical

3 cycles
Method 1010, condition C
_65° C I +150° C, 500 cycles
TA=Tmax

Preconditioning
Temperature Cycle

Method 1010, condition C,
_65° C I +150° C, 20 cycles
85° C I 85% RH, 72 hours,
unbiased

Preconditioning
Temperature!Humidity
Vapor Phase Solder
Pressure Cooker
Electrical I Visual
Resistance to
Soldering Heat

Notes

125° C, 2.3 atm, 200 hours
TA=Tmax
15 sec dip to within 1/8" of body
in solder at 260°C

Electrical

22/0

TA=25°C

Destructive Physical
Analysis

SEM - surface and cross-section

3 sets

1 set from each of 3
assembly lots

*Test methods reference MIL-STD-883C.
**Samples to be selected from 3 wafer lots (each lot shall be processed with a minimum of 1 week
separating it and the other two wafer lots.
***FIT shall be calculated using the Ahhrenius acceleration model and the following assumptions:
Ea = 0.5 e V if no failures; if failures, Ea to be determined based upon failure mechanism.
Ts = 55° C (derating temperature)
confidence level = 60%

Table 3.

2 • 10

SECTION 2

Monolithic Plastic Package Assembly Tests*"'.
(Continued)

Quality Assurance
Terms and Definitions
Activation Energy

Biased Humidity

The excess energy over the ground state which must
be acquired by an atomic or molecular system in order
for a specific process to occur.

An environmental test where the subject device is
exposed to high humidity and temperature conditions
(85% relative humidity and 85° C) while having the
device under an electrical bias. This procedure is
designed to measure the device's susceptibility to
electrolysis or electrolytic corrosion.
The
acceleration factor for a humidity change from 50% to
85% has been standardized as approximately 10. In
analyzing bias humidity and temperature results, the
acceleration factors of humidity and temperature are
estimated separately.

Arrhenius Model (Acceleration Factor)
The Arrhenius Model defines a relationship between
the failure rate and time that is commonly used in
correlating accelerated life environmental testing to
useful lifetime. The equation is used to calculate
failure rates based on lower junction temperatures and
normal operating environmental conditions.
The acceleration factor is the reaction rate of a process
at one temperature compared with the reaction rate of
the same process at another temperature. The
acceleration factor equation determines the
multiplication factor of time that the change in
temperature caused on the reaction process.

Burn-In
A thermal and electrical stress test designed to
eliminate early failures. The early device failures
(infant mortality) are detected and removed, thus
enhancing reliability.

Environmental Tests
AF = e [ EafK (lff1 - 1ff2) 1
Where:
AF = Acceleration Factor
e = natural logarithm base of 2.71828
E = the activation energy for semiconductor
material
K =Boltzmann's Constant
(8.626 x 10-5 eV / Kelvin)
T1 =Lower temperature in Degrees Kelvin
T2 = Higher temperature in Degrees Kelvin
Example: The AF for a temperature change from 85°
C to 125° C is 25.9 with an assumed activation energy
(Ea) of 1.0 eV. This factor is the time multiplication
factor: 1 hour at 125° C is equivalent to 25.9 hours
(over 1 day) at 85° C.

Bias
The electrical connection to the device pins that
allows specified signals, loading, and power supply
voltage to be applied. Often referred to as "electrical
l'

U.lal,).

Several tests that determine the long-term stability
and reliability of products. The product is exposed to
various conditions and extremes of temperature,
humidity, pressure or mechanical stress that
stimulates potential faults to appear, and accelerate
detection of device failures.

Failure in Time

(FIT)

A standard reliability unit that measures the device
failure rate as a function of device hours. One FIT is
equal to one device failure per billion device hours of
operation (1 FIT = 0.0001 % failures /1000 hours).

Infant Mortality
Initial failures of devices that occur in early life
operation. This is the region of the device failure rate
curve where the device failure rate decreases with time.
Product reliability is enhanced when environmental
screening eliminates these early failures region.

"

QUALITY ASSURANCE

2 - 11

-

Quality Assurance
Terms and Definitions (continued)
Pressure Cooker

Reliability Growth

A test that subjects the device to an atmosphere of
high temperature moisture under a pressure of
approximately two atmospheres. This test exposes
susceptibility to galvanic corrosion due to chemical
instability of the encapsulating materials.

The continuing efforts to reduce failure rates result in
continued improvements (or growth) in reliability.
This takes place in the design and manufacturing
phases, and when additional product improvements
are needed as determined from field performance data.

Qualification

Sampling

The test procedures as defined by the Quality
Assurance Department that a product must survive
before being considered a reliable manufacturing
product.

Inspection method to determine lot quality by careful
examination of a small number of devices from the
lot. A sampling plan is used to set the sample size,
based on the desired quality level.

Quality·

Screening

The extent to which a product successfully serves the
purpose of the user, during usage, is called "fitness for
use." This concept of fitness for use is popularly
called quality. Several parameters can be used to
characterize product quality. Quality of design is a
technical measure of the level or degree of excellence
of the product to meet it's intended needs of the user.
Three activities that compose the quality of design
are; Quality of market research, Quality of concept,
and Quality of specification. Quality of conformance
is the extent to which the product conforms to the
design, and can be measured by testing to the product
specification. Conformance also is termed Quality of
manufacturing or Quality of production. The quality
of products over time is characterized by the
time-oriented factors such as; availability, reliability,
and maintainability.

The process of subjecting all products to
non-destructive stresses to accelerate and identify
early failures.

Stress
An extreme environmental, electrical or physical
condition applied to a device to evaluate the device
performance or to accelerate reaction rates.

Temperature Cycling
A test that determines the thermal expansion
compatibility of materials used in device packaging.
The test exposes the device to temperature extremes,
typically a low temperature of _65 0 C. to a high
temperature of +150 0 C. The device is under no
electrical bias.

Quality Assurance (QA)
Thermal Shock
The activity of providing, to all concerned, the
evidence needed to establish confidence and assurance
that all the activities which affect product quality are
being performed adequately.

Reliability
Quality of products over time can be stated by the
products ability to perform without failure. The
classic definition is "the probability of a product
performing without failure a specified function under
given conditions for a specified period of time."

2 • 12

SECTION 2

This is a temperature cycling test in which the
temperature transitions are very rapid, less than 10
seconds. The device is immersed in suitable liquid
baths, each having extreme high and low temperatures
to expose failures such as device cracking, and
package leaking.
*QUALITY CONTROL HANDBOOK, Third Edition
McGraw Hill 1974, JURAN, Joseph M., Frank M.
Gryna Jr., and R.S. Bingham Jr.

SECTION 3
r--

IMAGING PRODUCTS ----.

Contents
AID Con'Verters
BU08

18 MSPS 8-Bit Flash Video AID Converter

3-3

Image Digitizers
Bt251

18 MSPS Single Channel 8-Bit Image Digitizer

3 - 19

Bt253

18 MSPS Triple Channel 8-Bit Image Digitizer

3 -43

Genlock I Video Timing
Bt261

30 MHz HSYNC Line Lock Controller

3 -67

Color Space Con'Version
Bt281

36 MHz Programmable Color Space Converter

3 - 93

4:2:2 Digital Video
Bt291

27 MHz RGB to YCrCb VideoNet™ Converter

3 - 125

Bt294

27 MHz YCrCb to RGB VideoNet™ Converter

3 - 161

Bt296

27 MHz ll-bit TIL-to-ECL Translator

3 - 191

Bt297

27 MHz II-bit ECL-to-TIL Translator

3 -197

Bt710

Scaler/Orthogonal Rotator Element

3 -205

PixelVu™

Object-oriented Software Toolkit for Imaging

3 - 253

3 - 2

Preliminary Information
This document contains information on a new product. The parametric infonnation,
although not fully characterized, is the result of testing initial devices.

Distinguishing Features

Applications

• No Video Amplifier Required
• ±1!4 LSB Typical DL Error
• ±1/2 LSB Typical n. Error
• External Zero and Clamp Control
• Overflow Output
• On-Chip Reference
Output Enable Control
• TTL Compatible
• +5 V CMOS Monolithic Construction
• 24-pin 0.3" DIP or 28-pin PLCC Package
Typical Power Dissipation: 500 mW

•
•
•
•

Image Processing
Image Capture
Desktop Publishing
Graphic Art Systems

Related Products
• Bt251, Bt253
• Bt261

--t=::::;=:::;--=:t=:----,

aAMP

--II---IC

LEVEL

-11------1

12V

I---+-- VRBP

..... -11--#'-...,
R
E
G
I

S
T
R/'

-1---<

2551'08

CLOCK

DO-D7

E

R

DB'

OND

VAA

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121
(619) 452-7580. (800) VIDEO IC
rLX: 383596· FAX: (619) 452-1249
L208oo1 Rev. J

18 MSPS
Monolithic CMOS
8-bit Flash
Video AID Converter
Product Description
The Bt208 is an 8-bit flash AID converter
designed specifically for video digitizing
applications. A flash converter topology is
utilized which has 256 high-speed comparators in
parallel to digitize the analog input signal.
Flexible input ranges enable NTSC and CCIR
video signals to be digitized without requiring a
video amplifier.

Functional Block Diagram

YIN

Bt208

3 - 3

The TTL-compatible output data and OVERFLOW
are registered synchronously with the clock
signal.
OE* three-states the DO-D7 outputs
asynchronously to CLOCK.
The ZERO input is used to zero the comparators,
while CLAMP perfonns DC restoration of the
video signal (by forcing the VIN input to the
voltage on the LEVEL pin) if AC-coupled to the
video signal.

Bt208
Circuit Description
As illustrated in the functional block diagram, the
Bt208 contains 256 high-speed comparators, a
255-to-8 encoder, output register, and a resistor
divider network. Two hundred fifty-five of the
comparators are used to digitize the analog signal; the
additional comparator is used to generate the
OVERFLOW bit.

Comparator Zeroing
The ZERO input is used to periodically zero the
comparators. The comparators have an initial
threshold mismatch due to manufacturing tolerances.
Zeroing charges capacitors in the comparators that
offset this threshold mismatch. Due to capacitor
discharging, they must be periodically zeroed.

General Operation
The Bt208 converts an analog signal in the range of
REF- S Vin S REF+, generating a binary number from
$00 to $FF, and an OVERFLOW output (see Table 1).
The values of REF+ and REF- are flexible to enable
various video signals to be digitized without requiring
a video amplifier. Refer to the Recommended
Operating Conditions and Application Information
sections for suggested configurations.
Figure 1 shows the input/output timing of the Bt208.
The sample is taken following the falling edge of
CLOCK. While CLOCK is low, the 255 to 8 encoding
is performed. The binary data and OVERFLOW are
registered and output onto the DO-D7 and OVERFLOW
pins on the next rising edge of CLOCK.

While ZERO is a logical one, the comparators are
zeroed. During ZERO cycles, DO-D7 and OVERFLOW
are not updated. They retain the data loaded before the
ZERO cycle.

Input Signal Clamping
CLAMP and LEVEL are used only in applications
where the video signal is AC-coupled to VIN. While
CLAMP is a logical one, the YIN input is forced to the
voltage level of the LEVEL pin to DC-restore the
video signal.
In applications where the video signal is DC-coupled

to YIN, the LEVEL pin should float, be connected to
VIN, or (only on the 28-pin PLCC package) CLAMP
should always be a logical zero.

VIN

])o·D7.
OVERFLOW

____D_:_:t__~)(~____D_t_TA____~)(~____~_A_It____~)(L____D_NA_I_t__

Figure 1.

3·4

SECTION 3

Input/Output Timing.

Bt208
Pin Descriptions
Pin Name

Description

00-07

Data outputs (TIL compatible). 00 is the least significant data bit. These outputs are latched
and output following the rising edge of CLOCK. Coding is binary. For optimum performance.
00-07 should have minimal loading. If driving a large capacitive load. an external buffer is
recommended.

OE*

Output enable control input (TIL compatible). Negating OE* three-states 00-07
asynchronously to CLOCK. The OVERFLOW output is not affected by the state of OE*.

OVERFLDW

Overflow output (lTL compatible). OVERFWW is latched and output following the rising edge
of CLOCK. OE* does not affect the OVERFLOW output signal. OVERFLOW is not available on
the DIP package.

CLOCK

Clock input (TIL compatible). It is recommended that this pin be driven by a dedicated TIL
buffer to minimize sampling jitter.

REF+

Top of ladder voltage reference (voltage input). REF+ sets the VIN voltage level that generates
$FF on the 00-07 outputs. All REF+ pins must be connected together as close to the device as
possible. A decoupling capacitor is NOT recommended on REF+.

REF-

Bottom of ladder voltage reference (voltage input). Typically. this input is connected to GND.
REF- sets the VIN voltage level that generates $00 on the DO-07 outputs. All REF- pins must
be connected together as close to the device as possible.

R/2

Mid-tap of reference ladder (voltage output). R/2 is not available on the DIP package. If not
used. this pin should remain floating. If used. it should be buffered by a voltage follower. A
decoupling capacitor is NOT recommended on R/2.

YIN

Analog signal inputs (voltage input). All VIN pins must be connected together as close to the
device as possible.

ZERO/CLAMP

Zeroing control input (TIL compatible). While ZERO is a logical one. the comparators are
zeroed. ZERO is latched on the rising edge of CLOCK. Note that on the 24-pin DIP package.
ZERO and CLAMP share the same pin; hence. zeroing and clamping occur simultaneously.
Clamp control input (TIL compatible). While CLAMP is a logical one. the VIN inputs are
forced to the voltage level on the LEVEL pin to perform DC restoration of the video signal.
CLAMP is asynchronous to clock. Note that on the 24-pin DIP package. ZERO and CLAMP
share the same pin; hence. ZERO and CLAMP are asserted simultaneously.

lEVEL

Level control input (voltage input). This input is used to specify what voltage level is to be
used for clamping while CLAMP is, a logical one. It is typically connected to GNO in
applications where the video signal is AC-coupled to VIN. In applications where the video
signal is DC-coupled to YIN. the LEVEL pin should float or be connected to VIN.

VREF

Voltage reference output pin. This pin provides a 1.2 V (typical) output.
capacitor is NOT recommended on VREF.

VM

+5 V power. All VAA pins must be connected together as close to the device as possible. A 0.1
IlF ceramic capacitor should be connected between each group of VAA pins and GND. as close to
the device as possible.

GND

Ground. All GNO pins must be connected together as close to the device as possible.

IMAGING PRODUCTS

A decoupling

3 •5

Bt208
Pin Descriptions (continued)

VIN

8

00

VIN

D1

REF +

02

I

~ ~ ~

~

Q

l'l ~ ~ ~ i'I !il l!l

03

02

VAA

VAA

01

17

OS

VAA

GND

DO

16

1)4

VREP

13

D6

GND

DE'

VIN

15

2'1lRO

GND

CLOCK

REF +

14

CLAMP

N/C

D7

REF +

13

LEVEL

REF·

06

VREF

12

REF·

LEVEL

DS

2'1lRO (CLAMP)

04

'" '" " " '"
~

24-pin 0.3" DIP Package

S~

~

:::

~ ~ ~ ~

28·pin Plastic I·Lead (PLCC)
Package

Note: N/C pins are reserved and must remain floating.

Vin* (v)

Overflow

DO-D7

OE*

> 0.998

1
0
0

$FF
$FF
$FE

0
0
0

0.996
0.992
:

:

:

:

0.500
0.496
0.492

0
0
0

$81
$80
$7F

0
0
0

:

:

:

:

0.004
< 0.002

0
0

$01
$00
3-state

0
0
1

*with REF+ = LOOO V and REF- = 0.000 V. Ideal center values. 1 LSB = 3.9063 mY.

Table 1.

3- 6

SECTION 3

Output Coding.

Bt208
PC Board Layout Considerations
PC Board Considerations

Supply

This product requires special attention to proper
layout techniques to achieve optimum performance.
Before beginning PCB layout, refer to the CMOS
Digitizer layout examples found in the Bt208, Bt251,
or Bt253 Evaluation Module Operation and
Measurements, application notes (AN-13. 14. and 15.
respectively). These application notes can be found
in Brooktree's 1990 Applications Handbook.

The bypass capacitors should be installed using the
shortest leads possible. consistent with reliable
operation. to reduce the lead inductance.

The layout should be optimized for lowest noise on
the B t208 power and ground lines by shielding the
digital inputs and providing good decoupling. The
lead length between groups of VAA and GND pins
should be as short as possible to minimize inductive
ringing.

Signal Interconnect

Ground Planes
The ground plane area should encompass all Bt208
ground pins. voltage reference circuitry. power supply
bypass circuitry for the Bt208. the analog input
traces, any input amplifiers. and all the digital signal
traces leading up to the Bt208.

Decoupling

For the best performance. a 0.1 )IF ceramic capacitor
should be used to decouple each of the two power pin
groups to GND. These capacitors should be placed as
close as possible to the device.

The digital signals of the Bt208 should be isolated as
much as possible from the analog inputs and other
analog circuitry. Also, these digital signals should
not overlay the analog power plane.
Any termination resistors for the digital signals
should be connected to the regular PCB power and
ground planes.

Power Planes
The Bt208 and any associated analog circuitry should
have its own power plane. referred to as the analog
power plane. This power plane should be connected to
the regular PCB power plane (VCC) at a single point
through a ferrite bead, as illustrated in Figure 2. This
bead should be located within 3 inches of the Bt208.
The PCB power plane should provide power to all
digital logic on the PC board, and the analog power
plane should provide power to all Bt208 power pins.
any voltage reference circuitry., and any input
amplifiers.
It is important that portions of the regular PCB power
and ground planes do not overlay portions of the
analog power plane, unless they can be arranged such
that the plane-to-plane noise is common mode. This
will reduce plane-to-plane noise coupling.
Dest

peffonHa.iH';~ ~s uui.a~l1ed

u.sing a deoicated linear

regulator to provide power to the Bt208.

IMAGING PRODUCTS

3 • 7

Bt208
PC Board Layout Considerations (continued)

IF AC-COUPUID TO
VIDEO SIGNAL

/

0.1

50

,....--------,

VIDEO T.....-....\I'---'VIN
75

Bt208

L1

.5V(VCC) _ - , . _ _....1

+

C3

GROUND

VREF

Location

Vendor Part Nwnber

Description

C1, C2
C3

0.1

L1

~

ceramic capacitor
10 ~ capacitor
ferrite bead

Erie RPEl12ZSU104MSOV
Mallory CSR13G106KM
Fair-Rite 2743001111

Note: The vendor numbers above are listed only as a guide.
characteristics will not affect the performance of the Bt208.

Figure 2.

3 - 8

SECTION 3

Substitution of devices with similar

Typical Connection Diagram and Parts List
(Internal Reference).

Bt208
Application Information
Using the Internal Reference

AC-Coupled )'s. DC-Coupled Input

The Bt20S has a 1.2 Von-chip reference available
(VREF). VREF may be divided down and used to drive
the REF+ input as shown in Figure 2. The 200 0
potentiometer serves three purposes: to allow
adjustment for different video signal levels, to allow
for video level tolerances, and to adjust for tolerance
of the internal reference.

The Bt20S may be either AC- or DC-coupled to the
video signal, as shown in Figure 2. The 75 0 resistor
to ground provides the typical 75 0 AC and DC
termination required by video signals. The 50 0
resistor provides isolation from any clock kickback
noise on YIN and prevents it from being coupled onto
the video signal. If DC-coupled to the video signal,
the 0.1 I1F capacitor is not used and CLAMP should be
grounded.

Note that VREF should supply at least 5 rnA of current
to maintain voltage stability over temperature. Thus,
VREF should drive a resistive load between 90 and
2400.

Using An External Reference
Figure 3 illustrates using a 1.2 V LM385 to generate a

o V-1.2 V reference for applications requiring a better
reference tempco than the internal reference can
supply. Supply decoupling of the op-arnp is not
shown. Any standard op-arnp may be used that is
capable of operating from a single +5 V supply.
As REF+ should be driven by a high AC impedance
source, a 100 0 resistor should be placed between
REF+ and the output of the op-arnp, as shown in
Figure 3. REF- may be driven in a similar manner if a
value other than GND is desired.

Zeroing
Unlike many CMOS AID converters requiring the
comparators to be zeroed every clock cycle, the
comparators in the Bt208 are designed to be only
periodically zeroed. It is convenient to assert ZERO
during each horizontal retrace interv al.
Note that, before using the Bt208 after a power-up
condition, ZERO must be a logical one for at least
1000 clock cycles (cumulative) to initialize the
comparators to the rated linearity. In normal video
applications this will be transparent due to the
number of horizontal scan lines that will have
occurred before using the Bt208.
As long as the recommended zeroing interval is
maintained, the Bt208 will meet linearity
specifications. The longer the time between zeroing
intervals, the more the linearity error increases.

FLOATING REP+

LEVEL

Figure 3.

Using an External Reference.

IMAGING PRODUCTS

3 - 9

Bt208
Application Information (continued)
Input Ranges
Table 2 shows some common video signal
amplitudes. For signals possibly exceeding 1.2 v,
the signal should be attenuated (using a resistor
divider network) so as not to exceed the 1.2 V input
range.
When digitizing with a full-scale range less than 0.7
V, the BaOS's integral linearity errors are constant in
terms of voltage regardless of the value of the
reference voltage. Lower reference voltages will
therefore produce larger integral linearity errors in
terms of LSBs.
For example, with a reference difference of 0.6 V, 0.6
V video signals may be digitized; however, the
integral linearity (IL) error will increase to about ±
loS LSB; the SNR will be about 40 dB. With a
reference difference of 0.5 V, 0.5 V video signals may
be digitized with an IL error of about ±2 LSB; the SNR
will be about 39 dB.

SNR and Error Rate

)IS.

The output noise of the BaOS may be reduced by
adjusting the duty cycle of the clock-this is
especially true above 10 MHz clock operation. Note
that uncorrelated noise less than 1% peak-to-peak will
be perceived with the same quality as that of a
consumer 1/2 inch VCR.

PC Board Sockets
If a socket is required, a low-profile socket is
recommended, such as AMP part no. 641746-2 for the
PLCC package.

ESD and Latchup Considerations
Correct ESD-sensitive handling procedures are
required to prevent device damage, which can produce
symptoms of catastrophic failure or erratic device
behavior with somewhat "leaky" inputs.

Clock Timing

Figure 4 illustrates the error rate vs. clock low time,
while Figure 5 illustrates the SNR vs. clock high
time.
An error is defined as being a sample that is more than
S LSBs (out of 255) from the expected value, where
the previous and following samples are less than (or
equal to) S LSBs from the expected value.

Output Noise
Although the BaOS does exhibit some output noise
for a DC input, the output noise remains relatively
constant for any input bandwidth. Competitive NO

All logic inputs should be held low until power to the
device has settled to the specified tolerance. Avoid
ADC power decoupling networks with large time
constants, which could delay V AA power to the
device. Ferrite beads must only be used for analog
power V AA decoupling. Inductors cause a time
constant delay that induces latchup.
Latchup can be prevented by assuring that all VAA
pins are at the same potential and that the VAA supply
voltage is applied before the signal pin voltages. The
correct power-up sequence assures that any signal pin
voltage will never exceed the power supply voltage
by more than +0.5 V.

Nominal
Amplitude

Worst Case
Amplitudes

1.0 V
BLACK -WHITE

0.9-1.1 V

RS-170 w/sync

1.4 V
SYNC-WHITE

1.2-1.6 V

RS-170A w/sync

1.2 V
SYNC-WHITE

1.0-1.4 V

0.7 V
BLACK -WHITE

0.6-0.S5 V

Video Standard

RS-170 w/o sync

RS-343A w/o sync

Table 2.
3 - 10

converters have no noise for a DC input; however, the
output noise increases greatly as the input bandwidth
and clock rate increaSe.

SECTION 3

Video Signal Tolerances.

Bt208
Application Information (continued)

..
Error Rate (ppm)

SNR (dB)

120 -r-'--""'-'''--''---'--''--''--'--'-''''----r--1

100 +-1\H-+-l-+-+-+-f-+-+-+--l--I

\

80

·····I'·""!"··· ..... ·····1····· ....
\1

60

oI

1

:

I

24

!
i

25

I

-r. . . . . ·····1····· .....

:

.

!

i

I . I
26
27

'

~: :~:jj~~m~~tt
39rH~'~iH+~I+I~IH+rH~

III

1
:

I
28

r--t-ti

I

29

I

I

30

II II ! II II

33 I' I I :,
II
II
i I
10 12 14 16 18 20 22 24 26 28 30

Clock Low Time (ns)
At 35 ns Error Rate

Figure 4.

=

Clock High Time (ns)

10- 6

Error Rate vs. Clock Low
Time.

Figure 5.

SNR vs. Clock High Time.

IMAGING PRODUCTS

3 - 11

Bt208
Recommended Operating Conditions
Parameter
Power Supply
Voltage References
Top
Bottom
Difference (Top-Bottom)

Symbol

Min

Typ

Max

Units

VAA

4.5

5.00

5.5

Volts

REF+
REF-

0.7
0
0.7

1
0
1

2.0
1.3
1.2

Volts
Volts
Volts

0.7

1
REFtoREF+

1.2

Volts
Volts

GND-O.5

REF60

REF+
150
+70

Volts

Max

Units

7.0

Volts

Input Amplitude Range
Analog Input Range

LEVEL Input Voltage
Time between Zeroing Intervals
Ambient Operating Temperature

TA

0

Symbol

Min

IJ.S
°C

Absolute Maximum Ratings
Parameter
VAA (measured to GND)

Typ

Voltage on any Signal Pin*

GND-O.5

VAA+0.5

Volts

Analog Input Voltage

GND-O.5

VAA+0.5

Volts

25

IlA

+125
+150
+150

°C
°C
°C

260

°C

220

°C

R!2 Output Current
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
(5 seconds. 1/4" from pin)
Vapor Phase Soldering
(1 minute)

TA
TS

TJ

-55
-65

TSOL

TVSOL

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability .
... This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD
sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can
induce destructive latchup.

3 • 12

SECTION 3

Bt208
DC Characteristics
Parameter
Resolution
Accuracy
Integral Linearity Error (note 1)
Differential Linearity Error
Output Noise (note 2)
Offset Error
Top
Bottom
Tempco
Coding
No Missing Codes
VIN Analog Inputs (note 3)
CLAMP = 0
Input Impedance
Input Current
Input Capacitance
CLAMP = 1
Input Impedance
REP+ Reference Input
Input Current
Input Impedance
Digital Inputs
Input High Voltage
Input Low Voltage
Input High Current (Vin = 2.4 V)
Input Low Current (Vin = 0.4 V)
Inpu t C apaci tance

Symbol

Min

Typ

Max

Units

8

8

8

Bits

±0.5
±0.25
±1

±l
±l

LSB
LSB
LSB

IL
II..

RlN
ill
CAIN

tbd
tbd
tbd

mV
mV
mV/oC

guaranteed

Binary

10

M=ohms
1

J.IA

15

pF

RlN

50

Ohms

IREP+
RREP+

1
1

rnA

VIH

2.0

VIL

0.8
1
-1

IIH
IlL
CIN

kn

10

Volts
Volts

J.IA
J.IA
pF

See test conditions on next page.

IMAGING PRODUCTS

3 - 13

..

Bt208
DC Characteristics (continued)
Parameter

Symbol

Min

Clock Kickback (note 4)
Digital Outputs
Output High Voltage
(IOH = -50 itA)
Output Low Voltage
(IOL = 1.6 rnA)
Three-State Current
Output Capacitance

Typ

Max

160

Va:!

Units
pV - sec

Volts

2.4

VOL

0.4

Volts

Ial

10
10

ItA

tbd

Volts
mV
rnA

cour

Internal Voltage Reference
Regulation (at 6 rnA)
Output Current

VREF

Power Supply Rejection Ratio
(not including reference)

PSRR

tbd

1.2
5

IREF

15
0.004

pF

%/%
!J.VAA

Test conditions (unless otherwise specified): "Recommended Operating Conditions" with REF+ = 1 V and
REF- = GND. REF- s Vin s REF+, LEVEL = float. Typical values are based on nominal temperature, i.e., room,
and nominal voltage, i.e., 5 V.
Note 1: Using best-fit linearity (offset independent). Averaged value evaluated using a closed-loop system.
Note 2: Clock duty cycle adjusted for minimum output noise for a DC input. For a DC input, output noise
may increase if clock duty cycle is not adjusted.
Note 3: LEVEL=GND.
Note 4: Measurement of noise coupled onto VIN due to clocking (Rs = 75 0). Typically occurs over a 5-ns
interval.

3 • 14

SECTION 3

Bt208
AC Characteristics
Parameter

Symbol

Conversion Rate

Fs

Clock Cycle Time
Clock Low Time
Clock High Time
Data Output Delay

1
2
3
4

OE* Asserted 10 DO-D7 Valid
OE* Negated to DO-D7 3-Stated

5
6

ZERO Setup Time
ZERO Hold Time
ZERO, CLAMP High Time (note 1)

7
8

Aperture Delay
Aperture Jitter
Full Power Input Bandwidth

9
BW

Min

Typ

Max

Units

18

MHz

25

ns
ns
ns
ns

25
25

ns
ns

55.5
35*
20**

0
20
1

10
50

ns
ps
MHz

6

Transient Response (note 2)
Overload Recovery (note 3)
Zero Recovery Time (note 4)

1
1
1

RMS Signal to Noise Ratio
Fin = 4.2 MHz, Fs = 10.7 MHz
Fin = 4.2 MHz, Fs = 14.32 MHz
Fin = 2.75 MHz, Fs = 6.75 MHz
Fin = 5.75 MHz, Fs = 13.5 MHz
Fin = 4.2 MHz, Fs = 17.72 MHz

SNR

Differential Gain Error (note 5)
Differential Phase Error (note 5)
Supply Current (note 6)
(Excluding IREF+)

..

ns
ns
Clock

Clock
Clock
Clock

dB

43
42
44
41
41

dB
dB

00
DP

2
1

%
Degree

IAA

100

dB

dB

tbd

rnA

Test conditions (unless otherwise specified): "Recommended Operating Conditions" with REF+ = 1 V and REF= GND. REF- $ Yin $ REF+, LEVEL = float. TTL input values are 0-3 V, with input rise/fall times $ 4 ns,
measured between the 10% and 90% points. Timing reference points at 50% for digital inputs and outputs.
DO-D7 and OVERFLOW output load $ 75 pF. Typical values are based on nominal temperature, i.e., room, and
nominal voltage, i.e., 5 V.
Note 1: Number of clock cycles ZERO is a logical one does not affect linearity. For best performance, ZERO
should be a logical one for an odd number of clock cycles.
Note 2: For full-scale step input, full accuracy attained in specified time.
l"tOU.,:;.:J~ 11rl1c u,) l"t::covei (0 luli accuracy afler a > 1.2 -v~ input signal.
Note 4: Time 10 recover 10 full accuracy following a zero cycle.
Note 5: 4x NTSC subcarrier, unlocked.
Note 6: IAA (typ) at VAA = 5.0 V, Fin =4.2 MHz, Fs = 14.32 MHz.
IAA (max) at VAA = 5.5 V, Fin = 6 MHz, Fs = 18 MHz.
*For 10- 6 typical error rate (see Figure 4).
**For typical SNR of 41 dB (see Figure 5).

IMAGING PRODUCTS

3 - 15

Bt208
Ordering Information

Package

Bt208KP

24-pin 0.3"
Plastic DIP

0° ro +70° C

Bt208KPJ

28-pin Plastic
J-Lead

0° ro +700 C

Bt208KPEVM

Bt208 Evaluation Board
(includes Bt208KP)

Timing Waveforms

CLOCK

VIN

DO·D7.
OVERFLOW

InputlOutput Timing.

3 - 16

Ambient
Temperature
Range

Model Number

SECTION 3

Bt208
Revision History
Revision
H

Change from Previous Revision
Cormection diagrams simplified. R/2 tap on PLCC package brought out.
Actual numbers for AC/OC parameters replace some "tbds."

J

Revised Application Information.

..

IMAGING PRODUCTS

3 - 17

Preliminary Information
This document contains information on a new product. The parametric information,
although not fully characterized, is the result of testing initial devices.

Distinguishing Features

Applications

, Image Processing
4 Software Selectable Analog Inputs
DC- or AC-Coupled Video Inputs
• Image Capture
Desktop Publishing
• Optional MPU Adjustment of Gain and Offset
• Graphic Art Systerns
Composite Sync Detection
8-bit Flash NO Converter
R/2 Reference Ladder Tap
256 x 8 Lookup Table
• Genlock Externally Implemented
• Bt253
StandardMPU Interface
, Bt261
TTL Compatible
+5 V CMOS Monolithic Construction
44-pin PLCC Package
, Typical Power Dissipation: 750 mW

Related Products

Functional Block Diagram

,---,------i-

RSEt'

CSYNC·

1Ouro

Bt2S1
18 MSPS
Monolithic CMOS
Single Channel
8-bit Image Digitizer
Product Description
The Bt251 Image Digitizer is designed to digitize
standard video signals (NTSC or CCIR). The
architecture of the B t251 enables the addition of
external circuitry for filtering, gain, etc., along
the signal path. A standard MPU interface is
provided for accessing various control functions.
Four analog inputs are supported, selectable under
MPU control. The MPU may select from which
input to detect sync information for external
genlocking independently of the video input
being digitized. A TTL-compatible composite
sync signal is output to interface to the genlock
circuitry.

rncr2-+----------~
JOurl

CEXTi _ + - - - - . ,
vroo
VIOl
VI02
VI03

::::j:=====~~~

-/---------'i-f--I

1 - - - - - - - - 4 - vour

-+-----------'-I~

M~_+--------_i
R/2 _ + - - - - - - - - 1
YIN

_+-------.--1

The output of the 8-bit NO converter addresses a
256 x 8 lookup table RAM, enabling real-time
image manipUlation prior to data storage,
including thresholding, contrast enhancement,
reversing video, implementing a nonlinear ND,
etc. The digitized data outputs may be three-stated
asynchronously to clock via the OE* control.

OB'
CLAMP

_+-------L

LEVEL
REF-

_+----------'

Optional MPU-controlled adjustment of gain and
offset is supported by the ability to program the
levels of the REF+ and REF- inputs to the AID.
Zeromg and clampmg Signals are available to
control the NO timing for application-specific
designs. The clamping level is externally set via
the LEVEL pin.

-+----__-1

?,~c_+----------l

00-01

RD-

wa-

NJ

At

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121
(619) 452-7580· (800) VIDEO IC
TLX: 383596, FAX: (619) 452-1249
L251001 Rev. H

3 - 19

..

Bt251
Circuit Description
MPU Interface

Analog Input Selection

As shown in the functional block diagram, the Bt251
supports a standard MPU interface (DO-D7, RD*,
MPU operations are
WR*, AO, and AI).
asynchronous to the clock.

The Bt251 supports four analog input sources,
VlDO-VID3. The MPU specifies which one is to be
digitized via the command register.

An internal 8-bit address register, in conjunction with
AO and AI, is used to specify which control register or
RAM location the MPU is accessing, as shown in
Table 1. All registers and RAM locations may be
written to or read by the MPU at any time; however,
while digitizing a video signal, the MPU should not
access the RAM as this will corrupt the digitized data.

When the MPU accesses the RAM, the address register
increments after each MPU access (read or write
cycle). After writing to RAM location $FF, the
address register resets to $00.
When accessing the address register or control
registers, the address register does not increment after
an MPU read or write cycle. Data written to reserved
locations is ignored; data read from reserved
locations returns invalid data. ADDRO corresponds to
DO and is the least significant bit

The selected video signal is output onto VOUT. VOUT
may be connected directly to VIN if no filtering or
gain of the video signal is required.
If digitizing only the luminance information of a
video signal containing color subcarrier information,
a filter should be used to remove the subcarrier
information to avoid possible artifacts on the display
screen. A low-pass filter, notch filter, or comb filter
may be used to remove the chroma information.

Note that sync information (if present) will still be
present on VOUT.
The multiplexers are not a break-before-make design.
Therefore, during the multiplexer switching time it is
possible for the input video signals to be
momentarily connected together through the
equivalent of 200 Q.
The 75 Q resistors to ground (Figure 1) provide the
typical 75 Q termination required by video signals.

Flash AID Converter
The Bt251 uses an 8-bit flash AID converter to
digitize the video signal. The AID digitizes analog
signals in the range of REF- ~ Yin ~ REF+. The
output will be a binary number from $00 (Vin ~ REF-)
to $FF (Vin 
12 = FIXED REP>

VREF
PC -PI

\----r-------

Sl1
I\,-+_---------IIOUTI

TO
FRAME
BUFFIlR

Bt251
VOUT

REP-

1------,
, ....................

i

0Pl10NAL
LOW-PASS

L._.. ~~~____ _

13 = ADJUSTABLE REF14 = FIXED REF- (GND EXAMPLE)

FILTER
TERMINATION

SO· 300VIN

1-------'

VIDEO
IN

TO VIDEO SIGNAL
15 = DC RESTORE TO GND
16 =COLOR DIFFERENCE DC RESTORE
• NEEDED ONLY IF ACTIVE FILTER IS USED. ADJUST FOR MINIMUM CLOCK KICKBACK.

Figure 1.

3 - 22

SECTION 3

Typical Bt251 External Circuitry.

Bt251
Circuit Description (continued)
Lookup Table RAM
A 256 x 8 lookup table RAM is provided on-chip to
implement simple imaging operations such as gamma
manipulation, simple contrast enhancement,
inverting of data, or a nonlinear transfer function of
the ND converter. Data from the AID is used to
address the RAM; the addressed data is output onto
PO-P7.
The RAM may be effectively bypassed by loading
each location with its corresponding address. As the
lookup table RAM is not dual-ported, MPU accesses
have priority over digitized data passing through the
RAM. During MPU accesses to the RAM, PO-P7 are
undefined.

Sync Detect Circuitry
The Bt251 performs composite sync detection from
the analog input specified by the command register.
Thus, sync information may be recovered from one
analog input while another input is being digitized.
The composite sync signal (CSYNC*) contains any
serration and equalization pulses the video signal may
contain. Note that CSYNC* is output asynchronously
to the clock and there are no pipeline delays (the
output delay from VIN to CSYNC* is approximately
25 ns).

The MPU specifies from which analog input to detect
sync (negative sync polarity). The selected video
signal is output on CEXTl. A 0.1 JlF capacitor between
CEXTl and CEXT2 AC-couples the video signal to the
sync detection circuit. The MPU selects one of four
levels of sync threshold by selecting how many
miIIivolts above the sync tip to use for sync detection.
If the sync tip on CEXT2 is below the selected
threshold, CSYNC* wiII be a logical zero. A low-pass
filter removes subcarrier burst ringing and extraneous
vertical interv al signals from false sync detection.
If it is desired to low-pass filter the sync signal prior to
sync detection, the low-pass filter should be inserted
between CEXTI and the 0.1 JlF capacitor (see Figure
1).

If the sync detection circuit is not used, CEXT2 should
be connected to GND or VAA (CEXTI may float), or an
unused (grounded) video input selected for the sync
detector.

External Sync Detection
CEXTI may be connected to an external sync detector
circuit. In this case, CEXT2 should be connected
directly to GND or VAA and the CSYNC" output left
floating.
The sync analog multiplexer may still be used to select
from which video source to detect sync information. As
the multiplexer switches analog video signals, the
selected video source wiII be output onto CEXTl.

IMAGING PRODUCTS

3 • 23

-

Bt2S1
Internal Registers
Command Register
The command register may be written to or read by the MPU at any time and is not initialized. DO is the least
significant bit.

D7,D6

Digitize select
(00)
(01)
(10)
(11)

D5,04

D3,02

VIDO
VID1
V1D2
VID3

Sync detect select
(00)
(01)
(10)
(11)

These bits specify which analog input is to be digitized.
The selected signal is output onto VOUT.

VIDO
VIOl
V1D2
VID3

Sync detect level select

These bits specify from which analog input sync
information is to be detected. The selected signal is
output onto CEXTl.

These bits specify how much above the sync tip to slice
CEXT2 for sync detection.

(00) 50 mV
(01) 75 mV
(10) 100 mV
(11) 125 mV

Ol,DO

reserved (logical zero)

The MPU must write a logical zero to these bits to
ensure proper operation.

lOUT Data Registers
These two 8-bit registers specify the output current on the IOUTO and IOUT1 outputs, from 0 rnA ($00) to full scale
($FC). The six MSBs of data are used to drive the DACs. DO and D1 (the two LSBs) must be programmed to be a
logical zero.
These registers may be written to or read by the MPU at any time and are not initialized. DO is the least significant
bit.

3·24

SECTION 3

Bt251
Pin Descriptions
Description

Pin Name
General Reference Functions
RSEf

Full-scale adjust control. An external 511 0 resistor must be connected between this pin and
GND. It is used to provide reference information to the internal D/A converters. See Figure 1.

IOUTO, IOUTI

Current outputs. The amount of output current is specified by the lOUT data registers. External
511 0 resistors are typically connected between each pin and GND. See Figure 1. The
relationship between full-scale lOUT and RSET is:
lOUT (rnA) =1,200 / RSET (0)

CEXTl, CEXT2

External capacitor pins. A 0.1 IlF capacitor must be connected between CEXTI and CEXTI to
AC-couple the video signal to the sync detect circuitry. A 1M 0 resistor must also be connected
between CEXTI and GND. See Figure 1.

AID Functions
REF+

Top of resistor ladder (voltage input). REF+ sets the VIN voltage level that generates $FF from
the AID converter. A decoupling capacitor is NOT recommended on REF+.

REF-

Bottom of resistor ladder (voltage input). REF- sets the VIN voltage level that generates $00
from the NO converter.

R/2

Reference ladder midpoint tap. If not used, this pin should remain floating. A decoupling
capacitor is NOT recommended on R/2. External loading should be < 1 IlA to obtain the best
linearity.

ZERO

Zeroing control input (TTL compatible). While ZERO is a logical one, the comparators of the
NO are zeroed. ZERO is latched on the rising edge of CLOCK. During zeroing cycles, PO-P7
are not updated; they retain the data loaded before the zeroing cycle.

CLAMP

Clamp control input (TTL compatible). While CLAMP is a logical one, the YIN input is forced
to the voltage level on the LEVEL pin to perform DC restoration of the video signal. CLAMP is
asynchronous to clock. In applications where VIN is DC-coupled to the video signal, LEVEL
should float or be connected to VIN, or CLAMP should always be a logical zero.

lEVEL

Level control input (voltage input). This input is used to specify what voltage level is to be for
DC restoration while CLAMP is a logical one. In applications where VIN is DC-coupled to the
video signal, LEVEL should float or be connected to YIN, or CLAMP should be a logical zero.

YIN

NO converter input. The analog signal to be digitized should be connected to this analog input
pin. It may be either DC- or AC-coupled to the video signal being digitized.

VlDO-VID3,

Analog inputs and analog output. VlDO-VID3 are connected to the video signals to be digitized.
The signal selected to be digitized is output onto VOUT. Unused inputs should be connected to
G!'lD.

your

Timing

Functions

CLOCK

Clock input (TTL compatible). CLOCK should be driven by a dedicated TTL buffer to minimize
sampling ji tter.

CSYNC*

Recovered composite sync output (TTL compatible). Sync information is detected on the
VlDO-VlD3 input specified by the command register, converted to TTL levels, and output onto
this pin. It is output asynchronously to the clock and there are no pipeline delays.

IMAGING PRODUCTS

3 • 2S

Bt251
Pin Descriptions (continued)
Pin Name

Description

Digital Control

Functions

PO-P7

Digitized video data outputs (TTL compatible). Digitized video data is output onto these pins
following the rising edge of CLOCK. PO is the least significant bit. They are three-stated if
OE* is a logical one.

OE*

Output enable control input (TIL compatible). A logical one three-states the PO-P7 outputs
asynchronously to CLOCK.

RD*

Read control input (TIL compatible). If RD* is a logical zero, data is output onto 00-07. RD*
and WR* should not be asserted simultaneously.

WR*

Write control input (TIL compatible). If WR* is a logical zero, data is written into the device
via DO-D7. Data is latched on the rising edge of WR *. RD* and WR * should not be asserted
simultaneously.

00-07

Bidirectional data bus (TIL compatible). MPU data is transferred into and out of the device over
this 8-bit data bus. DO is the least significant bit.

AO,Al

Address control inputs (TIL compatible). AO and Al are used to specify the operation the MPU
is performing as indicated in Table 1. They are latched on the falling edge of either RD* or
WR*.

Power and Ground
VAA

+5 V power. All VAA pins must be connected together as close to the device as possible. A 0.1
~F ceramic capacitor should be connected between each group of VAA pins and GND, as close to
the device as possible.

GND

Ground. All GND pins must be connected.

+

'"~ ~ ~ ~ ~ ~
1i1 II! f;;

~

0

Q

8

'" 8
Q

~

::l ~ t:l !:! ;;; $l III

VIN

28

DS

RSET

27

D6
D7

VOUT
10UTO

Z5

AO

23

RD'

VIDO

Al

10UTI
VIOl

WR'

CLAMP

P7

VI02

P6

LEVEL

PS
P4

VI03

9 :::

~

3 • 26

SECTION 3

~

~

::: :::

;!; :!! ~

!:<

1ii ~ Ii: 0: Ii! Ii!
El u"' gj d

~ ~

Bt251
PC Board Layout Considerations
PC Board Considerations

Supply Decoupling

This product requires special attention to proper
layout techniques to achieve optimum performance.
Before beginning PCB layout, refer to the CMOS
Digitizer layout examples found in the Bt208, Bt251,
or Bt253 Evaluation Module Operation and
Measurements, application notes (AN-13, 14, and 15,
respectively). These application notes can be found
in Brooktree's 1990 Applications Handbook.

The bypass capacitors should be installed using the
shortest leads possible, consistent with reliable
operation, to reduce the lead inductance.
Each group of VAA pins should have a 0.1 ~F ceramic
bypass capacitor to GND, located as close as possible
to the device.

Digital Signal Interconnect
The layout should be optimized for lowest noise on
the B t251 power and ground lines by shielding the
digital inputs/outputs and providing good decoupling.
The trace length between groups of VAA and GND
pins should be as short as possible to minimize
inductive ringing.

The digital signals of the Bt251 should be isolated as
much as possible from the analog signals and other
analog circuitry. Also, the digital signals should not
overlay the analog power plane.

Ground Planes

Any termination resistors for the digital signals
should be connected to the regular PCB power and
ground planes.

The ground plane area should encompass all Bt251
ground pins, voltage reference circuitry, power supply
bypass circuitry for the Bt251, the analog input
traces, any input amplifiers, and all the digital signal
traces leading up to the B t25!.

Power Planes
The Bt251 and any associated analog circuitry should
have its own power plane, referred to as the analog
power plane. This power plane should be connected to
the regular PCB power plane (VCC) at a single point
through a ferrite bead, as illustrated in Figure 2. This
bead should be located within 3 inches of the B1251.

Analog Signal Interconnect
Long lengths of closely spaced parallel video signals
should be avoided to minimize crosstalk. Ideally,
there should be a ground line between the video signal
traces driving the VIDx inputs.
Also, avoid routing high-speed TTL signals close to
the analog signals to minimize noise coupling.

The PCB power plane should provide power to all
digital logic on the PC board, and the analog power
plane should provide power to all Bt251 power pins,
any voltage reference circuitry, and any input
amplifiers.
It is important that portions of the regular PCB power
and ground planes do not overlay portions of the
analog power plane, unless they can be arranged so
that the plane-to-plane noise is common mode. This
will reduce plane-to-plane noise coupling.
Best periormance is obtained using a dedicaLCd linear
regulator to provide power to the B1251.

IMAGING PRODUCTS

3 • 27

..

Bt251
PC Board Layout Considerations (continued)

Bt251
L1

rvvv.

+5V(VCC)

~

,..------

"~a+-==-

C3

GROUND

Location

Description

Cl, C2
C3
L1

0.1 J.!F ceramic capacitor
10 J.!F tantalum capacitor
ferrite bead

3 - 28

GND

Vendor Part Nwnber
Erie RPE112Z5UI04M50V
Mallory CSR13G106KM
Fair-Rite 2743001111

Note: The vendor numbers above are listed only as a guide.
characteristics will not affect the performance of the Bt251.

Figure 2.

VAA

Substitution of devices with similar

Typical Power Supply Connection Diagram and Parts List.

SECTION 3

Bt251
Application Information
Zeroing

Increasing the Resolution of DACs

Unlike many CMOS AID converters requiring the
comparators to be zeroed every clock cycle, the
comparators in the Bt251 are designed to be only
periodically zeroed. It is convenient to assert ZERO
during each horizontal retrace interv al.

With a 511 Q resistor connected between each DAC
output (IOUTO, IOUTl) and OND, the resolution of the
ladder adjustment is 19 mY. The resolution of the top
of the resistor ladder (REF+) adjustment may be
increased by biasing the DAC outputs and using the
DAC outputs to adjust the voltage over a smaller range
with fmer resolution.

Note that before using the Bt251 after a power-up
condition, ZERO must be a logical one for at least
1000 clock cycles (cumulative) to initialize the
comparators to the rated linearity. In normal video
applications this will be transparent due to the
number of horizontal scan lines that will have
occurred before using the B 1251.
As long as the recommended zeroing interval is
maintained, the Bt251 will meet linearity
specifications. The longer the time between zeroing
intervals, the more the linearity error increases.

Figure 3 shows a circuit that allows adjustment of the
REF+ inputs from 0.714 V to 1 V with 4.5 mV
resolution. With the DAC data = $00, 0.714 V is
output; if the DAC data = $FC, 1 V is output.

As the typical maximum DAC output current is 2.35
rnA (RSET =511 Q), if a 0.286 V adjustable range is
desired, Rl II R2 must equal 121 Q. The minimum
output voltage desired determines the ratio of Rl and
R2:
Vmin = VREF * (R21 (Rl + R2»
The bottom of the resistor ladder (REF-) may be
adjusted from 0 V to 0.286 V with 4.5 mV resolution
by using a 121 Q resistor to ground rather than a 511
Q resistor. As long as the minimum range is 0 V, the
resistor to ground may be used to adjust the total
range. and thus the resolution.

Video Standard

Nominal
Amplitude

Worst Case
Amplitudes

1.0 V
BLACK - WHITE

0.9-1.1 V

RS-170 wlsync

1.4 V
SYNC-WHITE

1.2-1.6 V

RS-170A wlsync

1.2 V
SYNC-WHITE

1.0-1.4 V

0.7 V
BLACK - WHITE

0.6--0.85 V

RS-170 wlo sync

VREP=2.SV

~

RI.421

10lITO

TOVOLTA08
FOlLOWER

Rl=l69

RS-343A wlo sync

Table 2.

Video Signal Tolerances.

Figure 3.

Increasing DAC Output
Resolution.

IMAGING PRODUCTS

3 • 29

Bt2S1
Application Information (continued)
Using an External Reference

digitized with an IL error of about ± 2LSB; the SNR
will be about 39 dB.

Figure 4 illustrates using a 1.2 V LM385 to generate a
to 1.2 V reference for applications requiring a
better reference tempco than the internal reference can
supply. Supply decoupling of the op-amp is not
shown. Any standard op-amp may be used that is
capable of operating from a single +5 V supply.

oV

As REF+ should be driven by a high AC impedance
source, a 100 n resistor should be placed between
REF+ and the output of the op-amp, as shown in
Figure 4. REF- may be driven in a similar manner if a
value other than GND is desired.

SNR and Error Rate vs. Clock Timing
Figure 5 illustrates the NO error rate vs. clock low
time, while Figure 6 illustrates the NO SNR vs. clock
high time.

An NO error is defmed as being a sample that is more
than 8 LSBs (out of 255) from the expected value,
where the previous and following samples are less
than (or equal to) 8 LSBs from the expected value.

Output Noise
Input Ranges
Table 2 shows some common video signal
amplitudes. For signals possibly exceeding 1.2 V,
the signal should be attenuated (using a resistor
divider network) so as not to exceed the 1.2 V input
range.

Although the NO does exhibit some output noise for
a DC input, the output noise remains relatively
constant for any input bandwidth. Competitive NO
converters have no noise for a DC input; however, the
output noise increases greatly as the input bandwidth
and clock rate increase.

When digitizing with a full-scale range less than 0.7
V, the Bt251's integral linearity errors are constant in
terms of voltage regardless of the value of the
reference voltage. Lower reference voltages will
therefore produce larger integral linearity errors in
terms of LSBs.

The output noise of the AID may be reduced by
adjusting the duty cycle of the clock-this is
especially true above 10 MHz clock operation. Note
that uncorrelated noise less than 1% peak-to-peak will
be perceived with the same quality as that of a
consumer 1/2" VCR.

For example, by setting the reference difference to 0.6
V, 0.6 V video signals may be digitized; however the
integral linearity error will increase to about ±1.8
LSB; the SNR will be about 40 dB. With a reference
difference of 0.5 V, 0.5 V video signals may be

PC Board Sockets

VAA

If a socket is required, a low-profile socket is

recommended, such as AMP part no. 641747 - 2.

FWA TING REF+

.---.-----------------~ ffiW+
LM611

LIlVEL

Figure 4.
3 - 30

SECTION 3

Using an External Reference.

Bt251
Application Information (continued)
Bt251 with Minimal External Circuitry

ESD and Latchup Considerations

Figure 7 shows the Bt251 in an application for
digitizing 1 V video signals.

Correct ESD-sensitive handling procedures are
required to prevent device damage, which can produce
symptoms of catastrophic failure or erratic device
behavior with somewhat "leaky" inputs.

In this instance, the IOUTO output is driving the top
of the reference ladder (REF+) directly, without being
buffered by a voltage follower. The 1050 n resistor
between IOUTO and GND, in parallel with the
reference ladder, develops a 0 V-1.2 V reference
voltage for the AID (based on the contents of the
IOUTO data register). IOUTl and REF- are connected
toGND.
Although this implementation is not as temperature
stable as the one shown in Figure 1 (due to some
variation in the reference ladder resistance over
temperature), it will probably suffice for most
applications.

Error Rate (ppm)

All logic inputs should be held low until power to the
device has settled to the specified tolerance. Avoid
ADC power decoupling networks with large time
constants, which could delay V AA power to the
device. Ferrite beads must only be used for analog
power VAA decoupling. Inductors cause a time
constant delay that induces latchup.
Latchup can be prevented by assuring that all VAA
pins are at the same potential, and that the VAA
supply voltage is applied before the signal pin
voltages. The correct power-up sequence assures that
any signal pin voltage will never exceed the power
supply voltage by more than +0.5 V.
SNR(dB)
43

1\
l00-H\H-+-+-+-+-t-if-t-+-+-+-I
1

\

80

41

--,iT -!\I

-+-r -T-

39

60+-~~-+~4-~+-~~-;

;

;

37

35

20

0+-~~~-4-+~~~4-~

24

25

26

27

29

28

30

33

- - tl-- 1t -tlI
I I I I i I I I I I
I I : I
I; I
10 12 14 16 18 20 22 24 26 28 30

Clock High Time (ns)

Clock Low Time (ns)
At 35 ns Error Rate = 10-6

Figure 5.

AID Error Rate
Low Time.

l'S.

Clock

Figure 6.

AID SNR
High Time.

IMAGING PRODUCTS

l'S.

Clock

3 - 31

..

Bt251
Application Information (continued)

Sl1
CLOCK

RSBT
1M

CSYNC'"

TO/FROM
OBNLOCK

ZERO

CIRCUJlRY

CEXT2

1050

--I

CLAMP

CEXTl

LOW PASS FILTER
IOIITO

LBVBL

REP.

.~

R/2

TO
PO·PI I - - - r - - - - - - FRAMB
8UF1'1lR

t-------------iIOurl

Bt2S1
vourl---...,

t-----------------------~REP.

OPI1ONAL
LOWPASS

FILTER

GND

!
i
!

FILTER
TIlRMINATION

SO-300·

VINI---.J

VIDEO
IN

TO VIDEO SIGNAL

IS = OC RESTORE TO GND
16 = COLOR DIFFERIlNCH DC RESTORE
• NEIlDED ONl..Y II' ACTIVE FILTER IS USED. ADJUST POR MINIMUM CLOCK KICKBACK.

Figure 7.

3 • 32

SECTION 3

Typical Bt251 External Circuitry.

Bt251
Recommended Operating Conditions
Parameter
Power Supply
Voltage References
Top
Bottom
Difference (To~Bottom)

Symbol

Min

Typ

Max

Units

VAA

4.75

5.00

5.25

Volts

REF+
REF-

0.7
0
0.7

1
0
1

2.0
1.3
1.2

Volts
Volts
Volts

VAA-O.5
+2.2

Volts
Volts

1.2

Volts
Volts

2.0 Vp-p

Volts

REF60

REF+
150
+70

Volts
J.1S
°C

Typ

Max

Units

7.0

Volts

GND-O.5

VAA + 0.5

Volts

GND-O.5

VAA+0.5

Volts

25

!JA

+125
+150
+150

°C
°C
°C

220

°C

VIDO-VlD3 Amplitude Range
Multiplexer Compliance (DC)

0.5
-0.2

VIN Input Amplitude Range
VIN Input Range

0.7

CEXT AC Amplitude
LEVEL Input Voltage
Zeroing Interv al
Ambient Operating Temperature

1

REFto REF+
0.2 Vp-p
TA

GND-O.5
0

Absolute Maximum Ratings
Parameter

Symbol

Min

VAA (measured to GND)
Voltage on Any Signal Pin·
Analog Input Voltage

YIN, VlDx

R/2 Output Current
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Vapor Phase Soldering
(1 minute)

TA
TS
TJ

-55
-65

TVSOL

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
• This device employs high-impedance CMOS devices on all signal pins. It should be handled as an
ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V
can induce destructive latchup.

IMAGING PRODUCTS

3 • 33

Bt251
DC Characteristics
Parameter
AID. Resolution
AID Accuracy
Integral Linearity Error (note 1)
Differential Linearity Error
AID Offset Error
Top
Bottom
Tempco
AID Coding
No Missing Codes
VIN Analog Input (note 2)
CLAMP = 0
Input Impedance
Input Current
Input Capacitance
CLAMP = 1
Input Impedance

Symbol

Min

Typ

Max

Units

8

8

8

Bits

±1

LSB
LSB

lL
ll...

±l

guaranteed

RlN

m

10
15

RlN

50

n

100
10

n
Mn
pF

See test conditions on next page.

3 - 34

SECTION 3

pF

tbd

Clock Kickback (note 4)

CSYNC* Digital Output
Output High Voltage
(lOH = -400 J.l.A)
Output Low Voltage
(lOL = 1.6 rnA)
Output Capacitance

IJA.

CAIN

REF+ Reference Input
Input Current
Input Impedance

PO-P1 Digital Outputs
Output High Voltage
(lOH = -400 J.l.A)
Output Low Voltage
(lOL = 1.6 rnA)
Three-S tate Current
Output Capacitance

Mn

1

VlDO-VlD3 Analog Inputs (note 3)
Input Impedance to VOUT
Input Selected
Input Deselected
Input Capacitance

Digital Inputs
Input High Voltage
Input Low Voltage
Input High Current (Vin = 2.4 V)
Input Low Current (Vin = 0.4 V)
Input Capacitance

mV
mV
mV/oC
Binary

tbd
tbd
tbd

VlH
VIL

rnA

tbd

pV -sec

0.8
1
-1
10

IOZ
CDUI'

IJA.
IJA.

Volts

0.4

Volts

1

IJA.

10

pF

2.4

Volts

0.4

VOL
roUT

Volts
Volts

pF

2.4

VOL

VOO

kn

2.0

IlH
IlL
ClN

VOO

1
1

10

Volts

Bt2S1
DC Characteristics (continued)
Parameter
DO-D7 Digital Outputs
Output High Voltage
(lOH = -400 ItA)
Output Low Voltage
(lOL = 3.2 rnA)
Three-State Current
Output Capacitance

Symbol

Min

vrn

2.4

Max

Units

Volts

VOL

IOZ

cour

IOUTO and IOUTl Outputs
DAC Output ClDTent
DAC Output Impedance
DAC Output Capacitance
DAC Output Compliance (±100 j.LA)
AID Power Supply Rejection Ratio
(not including reference)

Typ

0.4

Volts

1

IlA

10

0

pF

2.5

rnA

+1.2

kO
pF
Volts

100
20
-0.2
PSRR

tbd

-

%/%
tJ.VAA

Test conditions (unless otherwise specified): "Recommended Operating Conditions" with REF+ = 1 V and REF- =
OND. REF- S Vin S REF+, LEVEL = float. Typical values are based on nominal temperature, i.e., room, and
nominal voltage, i.e., 5 V.
Note 1: Best-fit linearity. Averaged value evaluated using a closed-loop system. Linearity is tested with
RAM transparent (data = address).
Note 2: LEVEL=OND.
Note 3: VOUT connected to OND.
Note 4: Measurement of noise coupled onto VIN due to clocking (Rs = 75 0). Typically occurs over a 5-ns
interval.

Vin* (v)

PO-P7

OE*

> 0.996

$FF
$FE
:
$81
$80
$7F
:
$01
$00
3-state

0
0
:
0
0
0
:

0.992
:

0.500
0.496
0.492
:
0.1)04
< 0.002

I)

0
1

*with REF+ = 1.000 V and REF- = 0.000 V. Ideal center values. 1 LSB = 3.9063 mV. RAM
transparent (data = address).

AID Coding.

IMAGING PRODUCTS

3 - 3S

Bt251
AC Characteristics
Parameter
Conversion Rate

Symbol

Min

Typ

Fs

Multiplexer Switching Time
ON Resistance

Tmux

Clock Cycle Time
Clock Low Time
Clock High Time

1
2
3

PO-P7 Output Delay
OE'" Asserted to PO-P7 Valid
OE'" Negated to PO-P7 3-Stated

4
5
6

ZERO Setup Time
ZERO Hold Time
ZERO, CLAMP High Time (note 1)

7
8

Aperture Delay
Aperture Jitter
Full Power Input Bandwidth (note 7)

9
BW

Units

18

MHz

100
100

ns

n

ns
ns
ns

55.5
35·
20"
40
50
50
0
20
1

ns
ns
ns
ns
ns
Clock
ns
ps
MHz

10
50
6

Transient Response (note 2)
Overload Recovery (note 3)
Zero Recovery Time (note 4)
RMS Signal to Noise Ratio
Fin = 4.2 MHz, Fs = 10.7 MHz
Fin = 4.2 MHz, Fs = 14.32 MHz
Fin = 2.75 MHz, Fs = 6.75 MHz
Fin = 5.75 MHz, Fs = 13.5 MHz
Fin = 4.2 MHz, Fs = 17.72 MHz

Max

1
1
1

Clock
Clock
Clock

SNR

Analog Multiplexer Crosstalk
All Hostile Crosstalk
Single Channel Crosstalk
Adjacent Input Crosstalk
IOUTO, IOUT1 Settling Time
to±1 LSB

43
42
44
41
41

dB
dB
dB
dB
dB

-50
-50
-50

dB
dB
dB

100

ns

Differential Gain Error (note 5)
Differential Phase Error (note 5)

00
DP

2
1

%
Degree

Supply Current (note 6)
(Excluding REF+ )

IAA

150

rnA

See test conditions on next page.

3·36

SECTION 3

Bt251
AC Characteristics (continued)
Parameter

Symbol

Min

AO, Al Setup Time
AO, Al Hold Time

10

10
10

ns
ns

RD·, WR· High Time
RD· Asserted to Data Bus Driven
RD· Asserted to Data Valid
RD· Negated to Data Bus 3-Stated

12
13
14
15

50
5

ns
ns
ns
ns

WR·LowTime
Write Data Setup Time
Write Data Hold Time

16
17
18

50
10
10

11

Pipeline Delay

Typ

Max

40
20

2

Units

ns
ns
ns
2

2

Clocks

Test conditions (unless otherwise specified): "Recommended Operating Conditions" with REF+ =1 V and REF= GND. REF-:S; Yin :s; REF+, LEVEL = float. TIL input values are 0-3 V, with input rise/fall times :s; 4 ns,
measured between the 10% and 90% points. Timing reference points at 50% for digital inputs and outputs.
DO-D7, PO-P7, CSYNC* output 10ad:S; 75 pF. VOUT, lOUTO, lOUTI output 10ad:S; 75 pF. Typical values are
based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.
Note 1: Number of clock cycles ZERO is a logical one does not affect linearity. For best performance, ZERO
should be a logical one for an odd number of clock cycles.
Note 2: For full-scale step input, full accuracy attained in specified time.
Note 3: Time to recover to full accuracy after a > 1.2 V input signal.
Note 4: Time to recover to full accuracy following a zero cycle.
Note 5: 4x NTSC subcarrier, unlocked.
Note 6: lAA (typ) at VAA = 5.0 V, Fin =4.2 MHz, Fs = 1432 MHz.
IAA (max) at VAA = 5.25 V, Fin = 6 MHz, Fs = 18 MHz.
Note 7: Tested.
·For 10-6 typical AID error rate (see Figure 5).
··For typical AID SNR of 41 dB (see Figure 6).

IMAGING PRODUCTS

3 - 37

Bt2S1
Timing Waveforms

11

10

--,.
AD, Al

VALID
16

11

- J-1S

14

DO - D7 (RI!AD)

DO - D7 (WRITE)

~

DATA OIIT(RD'-O)

t

DATAIN(WR'=O)
17

-

MPU Read/Write Timing.

ZERO

CLOCK

VIN

PO-PI

Video Input/Output Timing.

3 - 38

SECTION 3

I--

18

I

Bt251
Test Circuits

IK

,-------jVIDO

37.5

VIDO

IK
VOllT I-V,-,O:;:llT,,---.1\

SI

VIOl

S2

VI02

S3

VOllT

VOllT

VIOl
VI02
VID3

VI03

OV-2.2V
5 MHZ
(75 OHMS)

VIN

OV -2.2V
5 MHZ

(75 OHMS)

1. VIDO SELECTED
2. XTALK =20WG (VOllT/VIN)

1. VIDO SELECTED
2. XTALK = AVERAGE VALUE OF 20 LOG (VOllT /VIN)
SCANNED SEQUENflALLY FROM SI TO S3
3. OPEN VIO INPUTS HA VB 75 OHM TERMINATION

TOGNO

All Hostile Crosstalk
Test Circuit.

Single Channel Crosstalk
Test Circuit.

IK
VIOO

VOllTl----'\I\r--,

VIOl
VI02
VI03

OV-2.2V
5 MHZ
(75 OHMS)

~

IN
1. VID3 SELECTED
2. XTALK=20WG(VOllT/VIN)

Adjacent Input Crosstalk Test Circuit.

IMAGING PRODUCTS

3 - 39

..

Bt251
Ordering Information

Ambient
Temperature
Range

Model Number

Package

Bt251KPI

44-pin Plastic
I-Lead

O· to +70· C

Bt251 Evaluation Board
(includes Bt251KPJ)

Bt251EVM

Analog Multiplexer Circuit

~--..-sm.o

VIDO -{>01I-f--OO-----,

'-+-+-.- sm.o·

Sm.l
VIOl
SBL1"

VOUT/CEXTI

SBL2
VI02
SBL2·

SBL3
VI03
SBL3·

3 - 40

SECTION 3

+

CMOS TRANSMISSION OATH:
ONs!OOHMS
OFP=-=lOMOHM$

Bt251
Revision History
Datasheet
Revision
E
F

Change from Previous Revision
Speed increased to 18 MSPS, production pinout added, AC and DC characteristics have "tbds"
replaced with numbers.
Maximum DAC output current changed to 2.5 rnA; RSET and DAC output resistors changed to 511
DAC output compliance changed to -0.2 V to +1.2 V. Address register operation corrected.

.n.
G

Expanded Applications Section.

H

Revised Figures 1,4, and 7. Updated Table 2. Added parameters.

IMAGING PRODUCTS

..

3 • 41

Preliminary Information
This document contains information on a new product. The parametric information,
although not fully characterized, is the result of testing initial devices.

Distinguishing Features

Applications

Image Processing
• Three 8-bit Video NO Converters
• Two Sets Software-Selectable Analog Inputs • Image Capture
Optional MPU Adjustment of Gain and Offset • Desktop Publishing
Graphic Art Systems
• Composite Sync Detection
• Genlock Externally Implemented
• Standard MPU Interface
Related Products
• TTL Compatible
• +5 V CMOS Monolithic Construction
• Bt251
• 84-pin PLCC Package
Bt261
Typical Power Dissipation: 1.5 W

Functional Block Diagram
,..--,----1COY,.,"

RSIlT

1 0.996

$FF
$FE

0
0

0.992
:

:

:

0.500
0.496
0.492

$81
$80
$7F

0
0
0

:

:

:

0.004
< 0.002

$01
$00
3-state

0
0
1

*with (R,G,B)REF+ = 1.000 V and (R,G,B)REF- = 0.000 V. Ideal center values.
1 LSB = 3.9063 mY.

AID Coding.

3 - 60

SECTION 3

Bt253
A.C. Characteristics
Parameter
Conversion Rate
Multiplexer Switching Time
ON RESISTANCE

Symbol

Min

Typ

Fs
Tmux

Clock Cycle Time
Clock Low Time
Clock High Time

1
2
3

R,G,B(0-7) Output Delay
OE* Asserted to Pixel Data Valid
OE* Negated to Pixel Data 3-Stated

4
5

ZERO Setup Time
ZERO Hold Time
ZERO, CLAMP High Time (note 1)

7
8

Aperture Delay
Aperture Jitter
Full Power Input Bandwidth (note 7)

9

18

MHz
ns

ns
ns
ns

55.5
35*
20**
40
50
50

ns
ns
ns
ns
ns
Clock

0
20
1

ns
ps
MHz

10
50
6

Transient Response (note 2)
Overload Recovery (note 3)
Zero Recovery Time (note 4)
RMS Signal-to-Noise Ratio
Fin = 4.2 MHz, Fs = 10.7 MHz
Fin = 4.2 MHz, Fs = 14.32 MHz
Fin = 2.75 MHz, Fs = 6.75 MHz
Fin = 5.75 MHz, Fs = 13.5 MHz
Fin = 4.2 MHz, Fs = 17.72 MHz

Units

100
100

6

BW

Max

1
1
1

Clock
Clock
Clock

SNR

Analog Multiplexer Crosstalk
All Hostile Crosstalk
Single Channel Crosstalk
Adjacent Input Crosstalk
IOUTO-IOUT5 Settling Time
to± 1 LSB

43
42
44
41
41

dB
dB
dB
dB
dB

-50
-50
-50

dB
dB
dB

100

ns

Degree

Differential Gain Error (note 5)
Differential Phase Error (note 5)

!Xl
DP

2
1

Supply Current (note 6)
(Excluding REF+)

IAA

300

%

tbd

IMAGING PRODUCTS

rnA

3 - 61

Bt253
AC Characteristics (continued)
Parameter

Symbol

Min

AO-A2 Setup Time
AO-A2 Hold Time

10
11

10
10

ns
ns

RD*, WR* High Time
RD* Asserted to Data Bus Driven
RD* Asserted to Data Valid
RD* Negated to Data Bus 3-Stated

12
13
14
15

50
5

ns
ns
ns
ns

WR*LowTime
Write Data Setup Time
Write Data Hold Time

16
17
18

50
10
10

Pipeline Delay

Typ

Max

40
20

1

Units

ns
ns
ns
1

1

Clock

Test conditions (unless otherwise specified): "Recommended Operating Conditions" with (R,O,B)REF+ = 1 V
and (R,O,B)REF- = OND. REF- ~ Yin ~ REF+, (R,O,B) LEVEL =float. TTL input values are 0-3 V, with input
rise/fall times ~ 4 ns, measured between the 10% and 90% points. Timing reference points at 50% for digital
inputs and outputs. 00-D7 output load ~ 75 pF. CSYNC*, RO-R7, 00-07, and BO-B7 output load ~ 75 pF.
ROUT, GOUT, BOUT, IOUTO-IOUT5 output load ~ 75 pF. Typical values are based on nominal temperature, i.e.,
room, and nominal voltage, i.e., 5 V.
Note 1: Number of clock cycles ZERO is a logical one does not affect linearity. For best performance, ZERO
should be a logical one for an odd number of clock cycles.
Note 2: For full-scale step input, full accuracy attained in specified time.
Note 3: Time to recover to full accuracy after a > 1.2 V input signal.
Note 4: Time to recover to full accuracy following a zero cycle.
Note 5: 4x NTSC subcarrier, unlocked.
Note 6: IAA (typ) at VAA = 5.0 V, Fin =4.2 MHz, Fs = 14.32 MHz.
IAA (max) at VAA = 5.25 V, Fin = 7.5 MHz, Fs = 15 MHz.
Note 7: Tested
*For 10-6 typical ND error rate (see Figure 6).

3 ·62

SECTION 3

Bt253
Timing Waveforms

10

AO-A2

~

11

VALID
16

12

14

DO-D7(READ)

DO - D7 (WRITE)

-

~

DATA OIIT (RD. = 0)

t

J-lS

I

..

DATA IN (WR. = 0)
17

-

f--

18

MPU Read/Write Timing.

ZERO

RCLOCK, GruJCK,

BCLOCK

RIN, GIN,
BIN

r

Rll-R7,OO-G7,

BO-B7

00·

Video Input/Output Timing.

IMAGING PRODUCTS

3 - 63

Bt2S3
Test Circuits

IK

IK
RVIDO

vour

ROur

RVlDO
SI

37.5

GVIDO
S2
DVIDO
S3

GOur
S4

GVIDI

GVIDO
DVIDO
RVIDI

GOur

GVIDI
IK

lK
DVIDI

vour

IK

IK
RVIDI

ROur

SS

DOur

DVIDI

DOur

VIN
OV·2V
5 MHZ

(75 OHMS)

1. RVIDO SELECI'ED

1. RVlDO SELECI'ED
2. XTALK = 20 LOG (your, VIN)

2. XTALK=AVERAGE VALUE OP20LOG (your 'VIN)
SCANNED SEQUENTIAlLYPROMSl TOSS
3. OPEN VID INPIITS HAVE 75 OIlMTERMINATION
TOGNO

All Hostile Crosstalk
Test Circuit.

Single Channel Crosstalk
Test Circuit.

IK
RVIDO

ROur

GVIDO
DVIDO
lK
DVIDI

GOur

GVIDI
lK
RVIDI

OV·IV
5 MHZ

(75 OHMS)

DOur

1. RVIDI SELIlCl1lD
2 XTALK = 20 LOG (your, VIN)

Adjacent Input Crosstalk Test Circuit.

3 - 64

SECTION 3

Bt253
Ordering Information

Model Number

Package

Ambient
Temperature
Range

Bt253KPI

84-pin Plastic

0 0 to +700 C

I-Lead
Bt253EVM

Bt253 Evaluation Board
(includes Bt253KPJ)

Analog Multiplexer Circuit

RVDlO/

.-1---_-

SBLO

GVDlO/~~+-~-oo------,

BVDlO

1-\--+--+- SBLO"
ROIIT / OOIIT / BOUT

RVIDI/

rl---_-

SELI

GVIDl/~OO+-~-Do-----~

DVID!

'-/--+---+-- SELl"

+

CMOS TRANSMISSION GAm:
ON =50 OHMS
OFF =10M OHMS

IMAGING PRODUCTS

3 • 65

Bt253
Revision History
Datasheet
Revision

3 - 66

Change from Previous Revision

D

Speed increased to 18 MSPS, production pinout added, AC and DC characteristics have "tbds"
replaced with numbers.

E

Maximum DAC output current changed to 2.5 rnA; RSET and DAC output resistors changed to 511
!l. DAC output compliance changed to -0.2 V to +1.2v.

F

Command bit DO function inverted.

G

Added Multiplexer Considerations to Circuit Description. Revised figures 2, 5, and table 3.
Added Multiplexer Compliance (DC) and CEXT AC Amplitude parameters.

SECTION 3

Preliminary Information
This document contains information on a new product. The parametric information,
although not fully characterized, is the result of testing initial devices.

Distinguishing Features

Applications

Programmable 12-Bit Video Timing
• Bidirectional HSYNC and CLOCK Pins
Horizontal Sync Noise Gating
• External VCO Support
• Standard MPU Interface
• TTL Compatible
• + 5 V Monolithic CMOS
• 28-pin PLCC Package
• Typical Power Dissipation: 300 m W

•
•
•
•

30 MHz Pixel Clock
Monolithic CMOS
HSYNC Line Lock
Controller

Image Processing
Video Digitizing
Desktop Publishing
Graphic Art Systems

Product Description
The Bt261 HSYNC Line Lock Controller is
designed specifically for image capture
applications.
Either composite video or TTL composite sync
information is input via VIDEO. An internal sync
separator separates horizontal and vertical sync
information. Programmable horizontal and
vertical video timing enables recovery of both
standard and non-standard timing information.

Functional Block Diagram

asCI,

asCI-

M

XTAL osc TO

a.C2
0SC2'

U

PIXELCLOCX

x

IlIlNERATOR

}----+-

PCOUT

>---r-----f--

CLOCK

HORIZONTAL
VIlll!O

1--+--

ZERO

VIDEO

a..AMP

TIMING
CON1ROL

HSYNC

CAP1URB

1 - - - - - - - - - - - - - + - VSYNC'

L====}------------+___________+-_

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121
(619) 452-7580· (800) VIDEO IC
TLX: 383596· FAX: (619) 452-1249
L261001 Rev. E

Bt261

3 - 67

AaD
CSYNC.

An external VCO may be used in conjunction with
the on-chip phase comparator for implementation
of clocks locked to the horizontal frequency.

Alternately, a high speed clock (OSC) may be
divided down to generate the pixel clock. The
OSC inputs may be configured to be either TTL or
ECL compatible. Thus, four TTL clocks, two TTL
clocks and one differential ECL clock, or two
differential ECL clocks may be used. The ECL
clock inputs are designed to be driven by 10KH
ECL using a single +5 V supply. The higher the
OSC clock rate, the lower the pixel clock jitter.
The CLAMP and ZERO outputs are programmed by
the MPU for DC restoration of the video signal
and zeroing the Image Digitizer or NO converter
at the appropriate time.

Bt261
Circuit Description
MPU Interface
As seen in the functional block diagram. the Bt261
supports a standard MPU interface (00-07. RD·.
WR*. and AO). MPU operations are asynchronous to
the clocks.
AO is used to select either the internal 5-bit address
register (AO = logical zero) or the control register
specified by the address register (AO = logical one).
ADDR5-ADDR7 are ignored during MPU write cycles.
and are in an unknown state when read by the MPU.
ADDRO corresponds to DO and is the least significant
bit. ADDRO-ADDR4 increment following any MPU

ADDRO - ADDR4

Addressed by MPU

$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$OA
SOB
SOC
$00
$OE
$OP
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$IA
$IB
$IC
$10
$IE
$IP

command register_O
command register_l
command registec2
command register_3
VSYNC sample register
OSC count low register
OSC count high register
status register
HSYNC start low register
HSYNC start high register
HSYNC stop low register
HSYNC stop high register
CLAMP start low register
CLAMP start high register
CLAMP stop low register
CLAMP stop high register
ZERO start low register
ZERO start high register
ZERO stop low register
ZERO stop high register
FIELD gate start low register
FIELD gate start high register
FIELD gate stop low register
FIELD gate stop high register
noise gate start low register
noise gate start high register
noise gate stop low register
noise gate stop high register
HCOUNT start low register
HCOUNT start high register
reserved
reserved

Table 1.

3 • 68

Internal Register Addressing.

SECTION 3

read or write cycle to a control register other than the
address register. MPU write cycles to reserved
addresses are ignored and MPU read cycles from
reserved addresses return invalid data.
Table 1 shows the internal register addressing.

Video Input / Sync Detector
Either an AC-coupled video signal or a DC-coupled
TTL-compatible composite sync signal may be input
via the VIDEO input pin (negative going sync
polarity).
Command register_O specifies the threshold above
the sync tip to use for sync detection. If the sync tip
on VIDEO is below the selected threshold. composite
sync information is detected and output onto CSYNC*
with no pipeline delay and asynchronous to the pixel
clock.
Typically. the VIDEO input will be connected to the
TTL-compatible CSYNC* output of the B1251/253
Image Digitizer. and the highest sync slicing level
will be selected.

Horizontal Counter
The rising edge of pixel clock (CLOCK) increments a
12-bit horizontal counter used to generate horizontal
video timing information. The value of the counter is
compared to various registers to determine when
signals are to be asserted and negated. $000
corresponds to the falling edge of CSYNC* with a
variable pipeline delay.

Horizontal Sync Separation
The Bt261 separates horizontal sync information
from CSYNC* by use of the horizontal noise gate
register. which derives gated composite sync by
removing equalization and serration pulses at
half-line intervals.
Two 12-bit noise gate start and stop registers specify
at what horizontal count (with pixel clock resolution)
to open and close sync transitions on the VIDEO
input to be detected.

Bt261
Circuit Description (continued)
The sync noise gating is provided to filter incorrect
horizontal sync information from noisy video
signals. The noise gating also serves a second
pUIpose: to filter serration and equalization pulses at
half-line intervals from CSYNC* during the vertical
retrace interv al. This enables steady synchronization
of horizontal sync information during vertical retrace
intervals.

HSYNC Input/Output
The HSYNC output may be programmed to be either
active high or active low. The beginning of HSYNC
(in pixel clock cycles) is determined by the HSYNC
start register, and is typically programmed to be
coincident with beginning of the noise-gated
CSYNC*.
The width of the HSYNC output is
determined by the HSYNC stop register and is
specified in pixel clock cycles.
The HSYNC output may be three-stated via the
command register.

FIELD Output
The FIELD output is derived from the vertical sync
information.
By positioning the FIELD gate
start/stop values a half-line interval apart, the
half-line delay in vertical sync during the second
field's vertical interval can provide a signal
distinguishing the fields.
The polarity of the FIELD output may be programmed
to be either active high (field one = I, field two = 0) or
active low (field one = 0, field two = 1).
When digitizing noninterlaced video signals, the
FIELD output will remain a logical one if FIELD is
programmed to be active low. FIELD will remain a
logical zero if the FIELD output is programmed to be
active high.
Figure 1 illustrates the operation of the FIELD gate
and FIELD output

Capture Output
HSYNC may also be configured as an input enabling
external circuitry to generate HSYNC and drive the
phase comparator.

VSYNC·

The Bt261 outputs a CAPTURE signal, which is a
command register bit (CR05) synchronized to the
vertical sync or FIELD signals.

Output

The vertical sync interval is determined by sampling
CSYNC* a specified number of pixel clock cycles
after the beginning of the recovered composite sync.
This interval is specified by the VSYNC sample
register.

To capture a single frame of video in an interlaced
system, the MPU resets the capture bit (CR5) low,
then sets it high before the next rising edge of field.
At the rising edge of field, the capture output will be
set to a logical one until the next rising edge or field
(one frame time).

For each scan line that the sample is a logical zero,
the VSYNC* output is a logical zero. Thus, the
VSYNC sample register should be programmed so that
the sample occurs well after the end of CSYNC*.
VSYNC is output on the rising edge of PCLK.

In a non-interlaced system, the MPU resets the capture
bit (CR5) low, then sets it high before the falling
edge of VSYNC*. When the falling edge of VSYNC*
occurs, the capture output will be set high until the
next falling edge of VSYNC*.

CLAMP and ZERO Outputs
The CLAMP and ZERO outputs are provided to control
the clamping and zero timing of the AID converter or
Image Digitizer. The start and stop timing is
programmable by the MPU (in pixel clock cycles).
ZERO is used to zero the comparators of the AID
converter or Image Digitizer. CLAMP is used to
DC-restore the video signal. Both CLAMP and ZERO
may be programmed to be either active high or active
low.

IMAGING PRODUCTS

3 - 69

..

Bt261
Circuit Description (continued)
If the falling edge of the noise-gated CSYNC. occurs
before the beginning of HSYNC, the phase
comparator "dumps" a charge onto an external
capacitor, increasing the VCO frequency. If the
falling edge of noise-gated CSYNC· occurs after the
beginning of HSYNC, the phase comparator "sinks" a
charge from the external capacitor, decreasing the
VCO frequency.

External VCO Pixel Clock Generation
An external VCO or pixel clock may be used to drive
the Bt261, as shown in Figure 2. The pixel clock
signal (from the VCO if one is used) is connected to
the CLOCK pin and anyone of the OSC input pins
(the one used must be selected by command bits
CROO-CR02). Note that the VCO must have positive
control voltage (positive voltage forces a higher
frequency).

The output of the phase comparator is PCOUT and it is
a TIL-compatible three-statable output. The width of
the output pulse on PCOUT is equal to the phase
difference with a gain of 4'1t I VCC.

An on-chip phase comparator is available to compare
the phase of HSYNC and the falling edge of the
noise-gated CSYNC•.

HSYNC
(ACTlVB LOW)

If

LJ

FIIlLDGATB
(START < STOp)

II

VSYNC·
BVENFIIlLD
(FIIlLD-O)

FIIlLD

ODDFIIlLD
(FIIlLD _I)

II

I

FIIlLDGATB
(START> STOP)

II

VSYNC·

BVENFIIlLD
(FIIlLD-I)

FIIlLD~

Figure 1.

3 - 70

SECTION 3

ODDFIIlLD
(FIBID -0)

II
FIELD Output Operation.

Bt261
Circuit Description (continued)
The "divide-by-N" for the PLL loop is the 12-bit
HCOUNT register. Command register bits CR07 and
CR06 must be set to (1,0) for proper operation. This
configures the horizontal counter to be reset to zero
upon reaching the HCOUNT value.

In the event lock is lost, phase limiting is disabled

until lock is re-established. Command bit CR22 may
be used to override this feature to tell the phase
comparator it is always locked.

Asynchronous (non-line
Clock Generation

Phase/Frequency Detector Operation
The phase comparator compares the phase of the
falling edge of the noise-gated CSYNC* and generated
HSYNC.
The HSYNC can be either internally
generated (and optionally output onto the HSYNC
pin) or an external HSYNC signal can be input via the
HSYNCpin.
In the event of a missing horizontal sync (either
recovered or generated), the phase comparator can be
configured to ignore the missing pulse and to not
adjust the frequency of the VCO. This pbase
limiting avoids adjusting the VCO frequency
erroneously due to the large phase error that would
otherwise occur until the next sync interval.
Command bit CRI0 enables or disables this
capability .
If the falling edge of the noise-gated CSYNC* and
generated HSYNC are within the number of pixel
clock cycles specified by command bits CR24-CR27
(1 to 16 clock cycles), the Bt261 considers itself
locked to the video signal. If the clock cycle
condition (as specified by command bits
CR24-CR27) is not met, status bit SROO is set to low
to indicate locking to the video signal was lost. If
the line count condition (as specified by command
bits CR3~R37) is not met, the phase limiter is
disabled.

locked)

Pixel

Four oscillator clock inputs are provided (OS C),
selectable by the MPU, configurable as either TTL or
differential ECL inputs (designed to be driven by
10KH EeL using a single +5 V supply).
The selected OSC input is divided down to the desired
pixel clock rate and duty cycle. The pixel clock low
and high times are programmable by the MPU (as a
function of OSC clock cycles) via the OSC count low
and high registers. Note that both the rising and
falling edge of the OSC inputs are used when
specifying the OSC count (for example, values of 2
for the OSC count low and high registers will divide
the OSC clock symmetrically by two).
The generated pixel clock is synchronized to the
falling edge of the noise-gated CSYNC* each scan
line. Each time a horizontal sync is detected on the
VIDEO input, the CLOCK output is resynchronized by
the OSC clock so that the beginning of a pixel clock
cycle and the falling edge of the noise-gated
CSYNC*are coincident (see Figure 3) within a period
of the OSC input While there is some sampling jitter
on CLOCK associated with the falling edge of
CSYNC*, the residual jitter in the remaining line
interval is strictly a function of the OSC clock source

---.n=. . =:=. . . . :::::::;::;;:mOANCll)
HSYNCLAGS CSYNC·,

_.u::=. . .

HSYNCLEADSCSYNC.,

OBCREASB PRBQ. (PCOUT =oV)

r - - -.....--V\r----; PCOUT

Bt261

Figure 2.

External VCO Configuration.

IMAGING PRODUCTS

3 - 71

..

Bt261
Circuit Description (continued)
jitter, and amplitude/slew rate jitter, at the OSC input.
Differential OSC signals of fast edges will minimize
the latter contribution.

CR07 and CR06 are (1,1): if a falling edge of the
noise-gated CSYNC· does not occur before the
number of pixel clock cycles specified by HCOUNT,
the horizontal counter is reset to zero upon reaching
HCOUNT, and begins incrementing again, until the
next falling edge of the noise-gated CSYNC. or
HCOUNT value is reached. CLOCK is continuous and
is resynchronized to each falling edge of the
noise-gated CSYNC*.

There are three ways of controlling the horizontal
counter, as determined by command bit CR07 and
CR06.
CR07 and CR06 are (0,1): if a falling edge of the
noise-gated CSYNC* does not occur before the
number of pixel clock cycles specified by HCOUNT,
the horizontal counter stops at the HCOUNT value and
is held there until the next falling edge of the
noise-gated CSYNC., at which time it is reset to zero.
CLOCK stops in the high state at the HCOUNT value,
until the next falling edge of the noise-gated
CSYNC·.

If a falling edge of the noise-gated CSYNC. occurs
before the number of pixel clock cycles specified by
HCOUNT, the horizontal counter is cleared at the
falling edge of the noise-gated CSYNC., and begins
incrementing again, until the next falling edge of the
noise-gated CSYNC· or HCOUNT value is reached.
CLOCK will be continuous and is resynchronized to
the falling edge of the noise-gated CSYNC·. This
mode is used if the number of pixel clock cycles per
scan line is not known or an arbitrary value is to be
used.

If a falling edge of the noise-gated CSYNC· occurs
before the number of pixel clock cycles specified by
HCOUNT, the horizontal counter is reset to zero by
the falling edge of the noise-gated CSYNC·. CLOCK
will be continuous and is resynchronized to each
falling edge of the noise-gated CSYNC·. This mode is
used if the number of pixel clock cycles per scan line
is known and is a fIXed number.

GAmD

CSYNC

aAlCK

rm
~

i

CR07 and CR06 are (1,0):
HCOUNT only.

Resets H counter at

esc
COUNT
LOW

............. i~

I

esc
COUNT
\llGH

L

aAlCK

:

esc

Figure 3.

3·72

CYCLB
RBSTARTIlD

LJUUlSL

Pixel Clock Output Timing (Crystal-Based Clock).

SECTION 3

Bt261
Internal Registers
Horizontal Counter
The 12-bit horizontal cOlmter is incremented on the rising edge of CLOCK. It is not accessible by the MPU.

Command Register_O
This command register may be written to or read by the MPU at any time and is not initialized. CRoo corresponds to
DO and is the least significant bit.

CR07, CR06

A value of (01) or (11) forces the horizontal
counter to be reset to zero at the beginning of
reserved
every recovered horizontal sync. These modes
reset each recovered HSYNC
(typically mode 01) should be selected when
reset to zero upon reaching HCOUNT using crystal-based pixel clock generation.
use both modes (01) and (10)
A value of (10) specifies that the horizontal
counter will be reset to zero upon reaching the
HCOUNT value. This mode should be selected
when using the horizontal counter as a simple
divide-by-N circuit (such as when using an
external VCO).

Horizontal counter control
(00)
(01)
(10)
(II)

CR05

Capture strobe

This bit is synchronized to VSYNC* and FIELD
and output onto the CAPTURE output pin.

CR04, CR03

Sync detect select

These bits specify how much above the sync tip
to slice VIDEO for sync detection. If inputting
TIL sync information, the highest slicing level
should be selected.

(00)
(01)
(10)
(11)

CR02-CROO

25 mV
50 mV
100 mV
125mV

Clock input select
(000)
(001)
(010)
(011)
(100)
(101)
(110)
(111)

TIL compatible OSCI
TIL compatible OSC1*
TIL compatible OSC2
TIL compatible OSC2*
ECL compatible OSCI, OSCI *
ECL compatible OSC2, OSC2*
reserved
reserved

These bits specify which OSC input is to be used
to generate pixel clock information. ECL input
selection is compatible with IOKH differential
ECL driven by a single +5 V supply.

IMAGING PRODUCTS

3 - 73

..

Bt261
Internal Registers (continued)
Command Register_1
This command register may be written to or read by the MPU at any time and is not initialized. CRIO corresponds to
DO and is the least significant bit

CRl7

Interlaced or noninterlaced select
(0) noninterlaced operation
(1) interlaced operation

CR16

CLOCK output disable

(0) drive CLOCK output
(1) three-state CLOCK output

CR15

CSYNC* output disable

(0) drive CSYNC* output
(1) three-state CSYNC* output

CR14

VSYNC* output disable

(0) drive VSYNC* output
(1) three-state VSYNC* output

CR13

HSYNC output disable

(0) drive HSYNC output
(1) three-state HSYNC output

3 - 74

SECTION 3

This bit specifies whether an interlaced or
noninterlaced video signal is being digitized.
The MPU must write a logical zero followed by a
logical one to this bit to reset the status bit
(SROO) to a logical one.

This bit specifies whether the CLOCK pin is
three-stated (logical one) or is actively driven
(logical zero). A logical one enables an external
pixel clock to drive the internal counters,
ignoring the OSC inputs and pixel clock
generator.

This bit specifies whether the CSYNC* output is
three-stated (logical one) or is actively driven
(logical zero).

This bit specifies whether the VSYNC· output is
three-stated (logical one) or is actively driven
(logical zero).

This bit specifies whether the HSYNC output is
three-stated (logical one) or is actively driven
with the internally generated HSYNC signal
(logical zero). If external circuitry is driving the
HSYNC pin, this bit must be set to a logical one.

Bt261
Internal Registers (continued)
Command Register_1 (continued)

CRI2

Reset lock loss status bits
(0) reset status bits
(I) inactive

CRll

Phase comparator input select
(0) HSYNC pin
(1) internally generated HSYNC

CRIO

Phase limit enable
(0) inhibit phase limiting
(1) enable phase limiting

This bit resets the status bits indicating loss of
lock. The MPU must write a logical zero to this
bit to clear the status bits (SR05 and SROO) to a
logical zero.

One input to the phase comparator is recovered
composite sync. The other input to the phase
comparator is specified by this bit to be either
the internally generated HSYNC or the HSYNC
pin. When an external source is driving the
HSYNC pin, this bit should be set to a logical
zero.

If this bit is a logical one, both horizontal sync
signals (recovered and either internally or
externally generated) must be present to adjust
the YCO frequency. If one is missing, the YCO
frequency is not adjusted. If this bit is a logical
zero, a missing horizontal sync signal will
adjust the YCO frequency.

IMAGING PRODUCTS

3 - 7S

..

Bt261
Internal Registers (continued)
Command Register_2
This command register may be written to or read by the MPU at any time and is not initialized. CR20 corresponds to
DO and is the least significant bit.

CR27-CR24

Phase lock pixel count
(0001) 2 clock cycles
(1111) 16 clock cycles

These bits specify the maximum number of pixel
clock cycles between the falling edge of
noise-gated CSYNC* and the HSYNC signal
(either internally or externally generated) to be
considered locked.
If the number of pixel clock cycles between the
falling edge of noise-gated CSYNC* and the
HSYNC signal exceed this value, lock is
considered to be lost for that scan line, and the
lock loss status bit (SROO) is set to a logical
zero.

CR23

Pixel clock mask enable
(0) continuous pixel clock
(1) stop pixel clock at HCOUNT

CR22

Lock override
(1) normal operation
(0) tell phase comparator it's locked

CR21, CR20

Pixel clock select
(00)
(01)
(10)
(11)

OSC inputs
external pixel clock
OSC drives CLOCK direct
reserved

If this bit is a logical one, the CLOCK output is

stopped in the logical one state when the
horizontal counter reaches the HCOUNT value.
This ensures a minimum pulse width when the
noise-gated CSYNC* signal is asynchronously
sampled. If it is a logical zero, the CLOCK
output will continuously clock (if command bit
CR 16 is a logical zero). This bit is ignored if an
external pixel clock is driving the CLOCK pin
(command bit CR16 is a logical one).

If the Bt261 goes out of lock, the phase limiter
is automatically disabled until it is back in lock.
If this bit is a logical zero, this function is
overridden.

These bits specify whether to use the
OSC-generated pixel clock or an external pixel
clock (driving the CLOCK pin) to clock internal
counters.
In mode (00), the selected OSC input(s) is divided
down by the OSC count registers to generate the
pixel clock (CLOCK).
If mode (01) is selected, an external pixel clock
must drive the CLOCK pin and one of the OSC
inputs. Command bit CR16 must be a logical
one.
If mode (10) is selected, the OSC clock is output
directly onto the CLOCK pin. The OSC count low
and high registers are ignored.

3 - 76

SECTION 3

Bt261
Internal Registers (continued)
Command Register_3
This command register may be written to or read by the MPU at any time and is not initialized. CR30 corresponds to
DO and is the least significant bil

CR37-CR30

Phase lock line count
(0000 0000) 1 scan line
(0000 0001) 2 scan lines

These bits specify the number of consecutive scan lines
for which lock must be maintained. If lock is not
maintained for the specified number of scan lines, the
phase limiter is disabled only if command bit CR22 is a
10 gical one.

(1111 1111) 256 scan lines

VSYNC Sample Register
This 8-bit register specifies the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at which
to sample the CSYNC* signal each scan line. This register may be written to or read by the MPU at any time and is
not initialized. Values from $00 (1) to $FF (256) may be specified. A value of [1/4 HCOUNT] is recommended
(greater than the maximum horizontal sync pulse width of about 5 I1S). For a conventional video input with
negative-going syncs, this produces a negative-going VSYNC* at the number of clock cycles specified after the
falling CSYNC* edge with some pipeline delay.

OSC Count Low and High Registers
These two 4-bit registers specify the number of rising and falling edges of an OSC input the pixel clock output
(CLOCK) is to be low and high. Values from $02 (2) to $OB (15) may be specified. These registers may be written to
or read by the MPU at any time and are not initialized. A value of $00 results in no pixel clock generation while the
OSC inputs are used. Note that the counters clock on both the rising and falling edge of the selected OSC input.

Status Register
This status register may be read by the MPU at any time and is not initialized. MPU write cycles to this register are
ignored. SRoo corresponds to DO and is the least significant bit.

SROO

Lock loss status (pixel count related)
(0) lock loss detected
(1) reset or no lock loss

This bit is reset if loss of lock occurred for a period
defined by CR24-CR27. It is reset by writing to
command bit CR12.

IMAGING PRODUCTS

3 • 77

..

Bt261
Internal Registers (continued)
HSYNC Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC· at
which to assert or negate the HSYNC output. The [start value] specifies the number of CLOCK cycles after the falling
edge of noise-gated CSYNC. that the HSYNC output is set high. The [stop value] specifies the number of CLOCK
cycles after the falling edge of noise-gated CSYNC* that the HSYNC output is set low. If [start value] = [stop value].
HSYNC will remain a constant logical zero. Values from $0000 (1) to $OFFF (4096) may be specified. Note that
there is a variable pipeline delay between the CSYNC* and HSYNC outputs.
D4-D7 of HSYNC start high are ignored during MPU write cycles and return a logical zero during MPU read cycles.
The 16-bit HSYNC start register is not updated until the write cycle to the HSYNC start high register. Thus. the
writing sequence should be [HSYNC start low] [HSYNC start high].
D4-D7 of HSYNC stop high are ignored during MPU write cycles and return a logical zero during MPU read cycles.
The 16-bit HSYNC stop register is not updated until the write cycle to the HSYNC stop high register. Thus. the
writing sequence should be [HSYNC stop low] [HSYNC stop high].

HSYNC Start/Stop High

HSYNC Start!Stop Low

Data Bit

D3

D2

D1

DO

D7

D6

OS

D4

D3

D2

D1

DO

Cascaded Value

Hll

HI0

H9

H8

H7

H6

H5

H4

H3

H2

HI

HO

CLAMP Start and Stop Registers
These two 16-bit registers specify the horizontal count (in pixel clocks) at which to assert and negate the CLAMP
output. The [start value] specifies the number of CLOCK cycles after the falling edge of noise-gated CSYNC· that
CLAMP is set high. The [stop value] specifies the number of CLOCK cycles after the falling edge of noise-gated
CSYNC* that CLAMP is set low. If [start value] = [stop value]. CLAMP will remain a cortSlant logical zero. Values
from $0000 (1) to $OFFF (4096) may be specified. Note that there is a variable pipeline delay between the CSYNC·
and CLAMP outputs.
D4-D7 of CLAMP start high are ignored during MPU write cycles and return a logical zero during MPU read cycles.
The 16-bit CLAMP start register is not updated until the write cycle to the CLAMP start high register. Thus. the
writing sequence should be [clamp start low] [clamp start high].
D4-D7 of CLAMP stop high are ignored during MPU write cycles and return a logical zero during MPU read cycles.
The 16-bit CLAMP stop register is not updated until the write cycle to the CLAMP stop high register. Thus. the
writing sequence should be [clamp stop low] [clamp stop high].
CLAMP Start/Stop High

CLAMP Start/Stop Low

Data Bit

D3

D2

D1

DO

D7

D6

OS

D4

D3

D2

Dl

DO

Cascaded Value

Hll

HI0

H9

H8

H7

H6

H5

H4

H3

H2

HI

HO

A value corresponding to 1 ~S after the falling edge of CSYNC. is recommended for the [start] value, and a value of 1
~S before the rising edge of CSYNC* is recommended for the [stop] value if DC restoration is to occur during the
horizontal sync interval. If DC restoration is to occur during the back porch interval. a value corresponding to SOO
ns after the rising edge of CSYNC. is recommended for the [start] value and a value corresponding to 2.S ~ after the
rising edge of CSYNC· is recommended for the [stop] value.

3 - 78

SECTION 3

BnxKtree~

Bt261

Internal Registers (continued)
ZERO Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at
which to assert or negate the ZERO output. The [start value] sets this output high at the specified number of CLOCK
cycles following the falling edge of noise-gated CSYNC*. The [stopvalue] sets this output low at the specified
number of CLOCK cycles following the falling edge of noise-gated CSYNC*. If [start value] = [stop value]. ZERO
will remain a constant logical zero. Values from $0000 (1) to $OFFF (4096) may be specified. Note that there is a
variable pipeline delay between the CSYNC* and ZERO outputs.
D4-07 of ZERO start high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The
16-bit ZERO start register is not updated until the write cycle to the ZERO start high register. Thus. the writing
sequence should be [zero start low] [zero start high].
D4-07 of ZERO stop high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The
16-bit ZERO stop register is not updated until the write cycle to the ZERO stop high register. Thus. the writing
sequence should be [zero stop low] [zero stop high].
ZERO Start/Stop High

ZERO Start/Stop Low

OataBit

D3

D2

D1

DO

D7

D6

05

D4

D3

D2

01

DO

Cascaded Value

Hll

HI0

H9

HS

H7

H6

H5

H4

H3

H2

HI

HO

Since an active high signal is need for the Bt20S. Bt2S1. and Bt253 during non-acquisition intervals. the ZERO
output can be programmed to be within the horizontal retrace interval.

IMAGING PRODUCTS

3 - 79

..

Bt261
Internal Registers (continued)
FIELD Gate Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at
which to start and stop the FIELD gate "window." With the noise gate properly programmed to ignore half-line
vertical interval pulses, the VSYNC* transition will occur half a line later during the vertical sync interval between
fields one and two (assuming a typical 2: 1 interlaced video signal). By programming the FIELD start and stop values
to have an interval exceeding half a line (e.g. starting at 1/4 line time and stopping at 3/4 line time) the FIELD output
is high during field one if [start value] < [stop value] or low during field one if [start value] > [stop value], with
transitions at every falling edge of VSYNC*. If [start value] = [stop value), FIELD will remain a constant logical
zero. Values from $()()()() (I) to $OFFF (4096) may be specified. Field edge coincides with VSYNC* falling edge.
D4-D7 of FIELD gate start high are ignored during MPU write cycles and return a logical zero during MPU read cycles.
The l6-bit FIELD gate start register is not updated until the write cycle to the FIELD gate start high register. Thus, the
writing sequence should be [field gate start low] [field gate start high].
D4-D7 of FIELD gate stop high are ignored during MPU write cycles and return a logical zero during MPU read cycles.
The l6-bit FIELD gate stop register is not updated until the write cycle to the FIELD gate stop high register. Thus, the
writing sequence should be [field gate stop low] [field gate stop high].

FIELD Gate Start/Stop High

FIELD Gate Start/Stop Low

Data Bit

D3

D2

DI

DO

D7

D6

D5

D4

D3

D2

D1

DO

Cascaded Value

H11

HIO

H9

H8

H7

H6

H5

H4

H3

H2

HI

HO

A difference between [start] and [stop] greater than [HCOUNT/2) is recommended, resulting in an active high FIELD
output (field one = I, field two = 0).

3 - 80

SECTION 3

Bt261
Internal Registers (continued)
Noise Gate Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at
which to force the Noise Gate to be closed (start value) or open (stop value). If [start value] = [stop value]. the Noise
Gate will remain open. Values from $0000 (1) to $OFFF (4096) may be specified.
D4-D7 of Noise Gate start high are ignored during MPU write cycles and return a logical zero during MPU read cycles.
The 16-bit Noise Gate start register is not updated until the write cycle to the Noise Gate start high register. Thus. the
writing sequence should be [Noise Gate start low] [Noise Gate start high].
D4-D7 of Noise Gate stop high are ignored during MPU write cycles and return a logical zero during MPU read cycles.
The 16-bit Noise Gate stop register is not updated until the write cycle to the Noise Gate stop high register. Thus. the
writing sequence should be [Noise Gate stop low] [Noise Gate stop high].

Noise Gate Start/Stop Low

Noise Gate Start!Stop High

Data Bit

D3

D2

D1

DO

D7

D6

D5

D4

D3

D2

Dl

DO

Cascaded Value

Hll

HIO

H9

H8

H7

H6

H5

H4

H3

H2

HI

HO

A value corresponding to [HCOUNT/2 - 2.5 IJ.S] is recommended for the [start] value and a value of [> HCOUNT/2] is
recommended for the [stop] value to remove typical equalization and serration pulses. This register should be
initialized early to minimize indeterminate outputs during vertical retrace.

HCOUNT Register
This 16-bit register specifies the maximum number of pixel clocks to generate per horizontal line.
The HCOUNT low and high registers are cascaded to form a 16-bit HCOUNT register. D4-D7 of HCOUNT high are
ignored during MPU write cycles and return a logical zero during MPU read cycles. The 16-bit HCOUNT register is not
updated until the write cycle to the HCOUNT high register. Thus. the writing sequence should be [HCOUNT low]
[HCOUNT high]. Values from $0000 (1) to $OFFF (4096) may be specified. This register should be written first
during initialization to minimize indeterminate output activity.

HCOUNTHigh

HCOUNfLow

Data Bit

D3

D2

Dl

DO

D7

D6

D5

D4

D3

D2

D1

DO

Cascaded Value

Hll

HI0

H9

H8

H7

H6

H5

H4

H3

H2

HI

HO

IMAGING PRODUCTS

3 - 81

..

Bt261
Pin Descriptions
Pin Name

Description

HSYNC

Horizontal sync input/output (TTL compatible). As an output, HSYNC is programmed to be
either a logical zero or logical one during the desired horizontal sync interval. It is output
following the rising edge of CLOCK. As an input, it is input into the phase comparator
asynchronously to the clocks with no pipeline delays.

VSYNC*

Vertical sync output (TTL compatible) with a negative composite sync output. VSYNC* is a
logical zero for scan lines during detected vertical sync intervals on the VIDEO input. It is
output following the rising edge of CLOCK.

CSYNC*

Composite sync output (TTL compatible). CSYNC* is a logical zero during negative composite
sync intervals detected on the VIDEO input. It is output asynchronous to the clocks with no
pipeline delays.

ZERO

Zero output (TTL compatible). This output is used to control the ZERO input of the Image
Digitizer or AID converter. It may be programmed to be either active high or active low and is
output following the rising edge of CLOCK.

CLAMP

Clamp output (TTL compatible). This output is used to control the CLAMP input of the Image
Digitizer or AID converter. It may be programmed to be either active high or active low and is
output following the rising edge of CLOCK.

FIElD

Even/odd field output (TTL compatible). For interlaced operation. this output (with transitions
coincident with the VSYNC* output) indicates whether the current field is even or odd; the
polarity is programmable. For noninterlaced operation. this output is always either a logical
one or a logical zero. depending on whether it is programmed to be active high or low. It is
output on the falling edge of VSYNC*.

PCOUf

Phase comparator output (TTL compatible). This three-state output indicates the phase
difference in time between the generated horizontal sync signal (either the internally generated
HSYNC or the HSYNC pin) and the recovered horizontal sync signal. High = lags. Low = leads.

VIDEO

Video and composite sync input. Either a DC-coupled TTL composite sync information or an
AC-coupled analog video signal (less than 2v peak-to-peak) may be input via this pin for
detection of sync information. Sync information must be of negative polarity.

CLOCK

Pixel clock input/output (TIL compatible). The device may either drive this pin with a
generated clock or an external pixel clock may drive this pin.

OSCI,OSCI*.
OSC2,OSC2*

External clock inputs (TTL or EeL compatible). These inputs are programmed to be either TIL
or ECL compatible (IOKH differential EeL driven by a single +5 V supply).

CAPTIJRE

Active video output (TTL compatible). This output is active high for a frame duration and is
synchronized to the vertical sync interval and FIELD signal. It is output following the rising
edge of FIELD for interlaced, or the falling edge of VSYNC* if non-interlaced.

RD*

Read control input (TTL compatible). If RD· is a logical zero. data is output onto OO-D7. RD·
and WR* should not be asserted simultaneously.

WR*

Write control input (TTL compatible). If WR* is a logical zero. data is written into the device
via OO-D7. Data is latched on the rising edge of WR *. RD* and WR * should not be asserted
simultaneously.

DO-D7

Bidirectional data bus (TTL compatible). MPU data is transferred into and out of the device over
this 8-bit data bus. If RD* is a logical one, OO-D7 are three-stated.

3 - 82

SECTION 3

Bt261
Pin Descriptions (continued)
Pin Name

Description

AO

Address control inputs (1TL compatible). AO specifies whether the MPU is accessing the
address register (AO = 0) or the control register specified by the address register (AO = 1).

vee

Power.

GND

Ground.

..

DO

18

D1

17

0SC1.

D2

16

VSYNCO

D3

15

PII!LD

D4

14

CAP\1JRI!

os

13

CSYNC·

D6

12

VIDOO

OSCI

IMAGING PRODUCTS

3 - 83

Bt261
Application Information
Inter/acing to the 8t208
Figure 4 illustrates interfacing the Bt261 to the Bt20S
Flash AID Converter. The VIDEO input of the Bt261
connects to the YIN input of the Bt20S through a 0.1
IlF ceramic capacitor. The sync slicing level of the
Bt261 should be selected for optimum performance.

The HSYNC, YSYNC*, FIELD, and CAPTURE signals
of the Bt261 interface to the video timing controller
and video DRAM controller.

The Bt261 provides the ZERO and CLAMP signals
required by the Bt208, in addition to the CLOCK.

HSYNC

FIElD

Bt261

1M

CAPTIlRE

TO VIDEOTIMWG
CONTROLLER AND

\r---4J--i VIDEO

VDRAM CONTROLLER

OPTIONAL

SUBCARR!ER

FILTER

VIDEO
(IVp.p)

G
soo

ZERO CLAMP CLOCK

0.1

SO

------~I

VW

"'-

IF AC-COUPLllD TO
VIDEO SIGNAL

Figure 4.

3 ·84

Bt208

SECTION 3

Inter/acing to the 8t208.

Bt261
Application Information (continued)
Inter/acing to the Bt25I
Figure 5 illustrates interfacing the Bt261 to the B1251
Image Digitizer. The VIDEO input of the Bt261
connects directly to the CSYNC* output of the Bt251.
As CSYNC* is a TIL-compatible output, the highest
sync slicing level should be selected on the Bt261.

The HSYNC, VSYNC*, FIELD, and CAPTURE signals
of the Bt261 interface to the video timing controller
and video DRAM controller.

The Bt261 provides the ZERO and CLAMP signals
required by the Bt251, in addition to the CLOCK.

..

HSYNC

VSYNC·

FIELD

Bt261

CAPfVRE

TO VIDEO TIMING
CONTROlLER AND

VDRAM CONTROLLER
VIDEO

ZERO CLAMP CLOCK

CSYNC·

ZERO

a...AMP CLOCK

Bt251

Figure 5.

Inter/acing to the Bt25I.

IMAGING PRODUCTS

3 • 8S

Bt261
Application Information (continued)
Inter/acing to the Bt253

ESD and Latchup Considerations

Figure 6 illustrates interfacing the Bt261 to the Bt253
Image Digitizer. The VIDEO input of the Bt261
connects directly to the CSYNC* output of the Bt253.
As CSYNC* is a TIL-compatible output, the highest
sync slicing level should be selected on the Bt261.

Correct ESD-sensitive handling procedures are
required to prevent device damage, which can produce
symptoms of catastrophic failure or erratic device
behavior with somewhat "leaky" inputs.

The Bt261 provides the ZERO and CLAMP signals
required by the Bt253, in addition to the (R,O,B)
CLOCK inputs of the Bt253.
The HSYNC, VSYNC*, FIELD, and CAPTURE signals
of the Bt261 interface to the video timing controller
and video DRAM controller.

Latchup can be prevented by assuring that all VCC
pins are at the same potential and that the VCC supply
voltage is applied before the signal pin voltages. The
correct power-up sequence assures that any signal pin
voltage will never exceed the power supply voltage
by more than +0.5 V.

HSYNC
VSYNC"

FIELD

Bt26l

TO VIDEO TIMING

CAPruRI!

CONTROILER AND
VDRAM CONTROILER
VIDEO

ZERO CLAMP CLOCK

I

I

1 1 1

1

CSYNC· ZERO CLAMP RCLOCK GCLOCK BCLOCK

Bt253

Figure 6.

3 - 86

SECTION 3

Inter/acing to the Bt253.

Bt261
Recommended Operating Conditions
Parameter
Power Supply
Ambient Operating Temperature

Symbol

Min

Typ

Max

Units

VCC
TA

4.75
0

5.00

5.25
+70

Volts
·C

5
2

Volts
Voltspp

Video Input
DC-coupled
AC-coupled*

0.2

* Video input DC quiesent about (VCC/2) volts.

..

Absolute Maximum Ratings
Parameter

Symbol

Max

Units

7.0

Volts

GND-O.5

VCC+O.5

Volts

-55
-65

+ 125
+ 150
+ 150

·C
·C
·C

220

·C

Min

VCC (measured to GND)
Voltage on any Signal Pin*
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Vapor Phase Soldering
(1 minute)

TA
TS
TJ
TVSOL

Typ

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
* This device employs high impedance CMOS devices on all signal pins. It should be handled as an
ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V
can induce destructive latchup.

IMAGING PRODUCTS

3 • 87

BnxKtree~

Bt261
D.C. Characteristics
Parameter
TTL Digital Inputs
Input High Voltage
Input Low Voltage
Input High Current (Vin = 2.4 V)
Input Low ClUTent (Vin =0.4 V)
Input Capacitance
(f = 1 MHz, Vin =2.4v)
OSC Digital Inputs
TTL Mode
Input High Voltage
Input Low Voltage
Input High ClUTent (Vin =2.4 V)
Input Low ClUTent (Yin =0.4 V)
Input Capacitance
(f =1 MHz, Vin =2.4 V)
ECLMode
Input High Voltage
Input Low Voltage
Input High Current (Vin =4.0 V)
Input Low ClUTent (Vin =0.4 V)
Input Capacitance
(f = 1 MHz, Vin =2.4v)
DO - D7 Digital Outputs
Output High Voltage
(lOH =-400 IJ.A)
Output Low Voltage
(lOL =6.4 rnA)
3-state ClUTent
Output Capacitance
PCOUT Output
Output High Voltage
(lOH =-400 IJ.A)
Output Low Voltage
(lOL =3.2 rnA)
3-state ClUTent
Output Capacitance
Other Digital Outputs
Output High Voltage
(lOH =-400 IJ.A)
Output Low Voltage
(lOL =3.2 rnA)
3-State ClUTent
Output Capacitance

Symbol

Min

VIH
VIL
IIH
IlL

2.0
GND-O.5

Typ

Max

Units

VCC+05
0.8
1
-1

Volts
Volts

CIN

IIA
IIA
pF

7

VIH
VIL
IIH
IlL

2.0
GND-0.5

1

IIA
IIA

7

VCC-l.O
GND-0.5

CIN

VOH

Volts
Volts

-1

CIN

VIH
VIL
IIH
IlL

VCC+0.5
0.8

pF

VCC+0.5
VCC-1.6
1
-1
7

IIA
IIA
pF

2.4

Volts

VeL
ICYZ
roUT

Volts
Volts

0.4

Volts

50

IIA

20

pF

VOH

100

Q

VeL

75

Q

50

IIA

IOZ
roUT

VOH

20

2.4

Volts

VeL
ICYZ

rour

pF

20

0.4

Volts

50

IIA
pF

Test conditions (unless otherwise specified): "Recommended Operating Conditions." Typical values are based
on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.

3 - 88

SECTION 3

Bt261
AC Characteristics
Parameter

Units

Min

OSCmax
Fmax

10
33.33

ns
ns

AO Setup Time
AOHoidTime

1
2

10
10

ns
ns

RD*/WR* Low Time
RD*/WR* High Time
RD* Asserted to Data Bus Driven
RD* Asserted to Data Valid
RD* Negated to Data Bus 3-Stated

3
4
5
6
7

50
50
5

ns
ns
ns
ns
ns

Write Data Setup Time
Write Data Hold Time

8
9

10
10

ns
ns

OSC High Time
OSCLowTime

10
11

3.5
3.5

ns
ns

CLOCK Low Time
CLOCK High Time
OSC to CLOCK Output Delay Pipelines

12
13
14

tbd
tbd

VIDEO to CSYNC* Output Delay
HSYNC, ZERO, CLAMP Output Delay
VSYNC*, FIELD Output Delay Pipelines

15
16
17

PCOUT Output Delay
Minimum Compare Differential

18
19
ICC

OSC Cycle Time
CLOCK Cycle Time*

VCC Supply Current**

Typ

Max

Symbol

40
20

tbd
tbd
tbd

ns
ns
ns

tbd
tbd
tbd

ns
ns
ns

5

tbd
tbd

ns
ns

60

tbd

rnA

Test conditions (unless otherwise specified): "Recommended Operating Conditions". TTL input values are 0-3
V, with input rise/fall times ~ 4 ns, measured between the 10% and 90% points. Timing reference points at 50%
for inputs and outputs. CLOCK, HSYNC, CLAMP, ZERO, VSYNC*, FIELD, CAPTURE, and CSYNC* output load ~
50 pF, DO--D7 output load ~ 130 pF. Typical values are based on nominal temperature, i.e., and nominal voltage,
i.e., 5 V.
*Maximum load of 20 pf.
**At Fmax. ICC (typ) at VCC = 5.0 V. ICC (max) at VCC = 5.25 V. OSC/pcLOCK = 2, CLOCK/HSYNC

IMAGING PRODUCTS

~100.

3 • 89

Bt261
Timing Waveforms

I

----

AO

I

2

~

VALID

---.J

3

RD"'. WR'"

4
6

5

DO • D7 (READ)

=Jst-

DO • D7 (WRrIll)

.1"
.....

DATA OUT (RD'

DATA IN (WR'

- 1=7

=0)

I

./

=0)

-

I--

9

MPU Read/Write Timing.

r----t-

OSC PIlRIOD

~
osc

r"
----.l
I r"
~

HSYNC, CLAMP,
ZilRO

VSYNc', FIELD

CLOCKPIlRIOD -1-2- - - - I "

13

~_ _ _ _ _r l------~_ _ _ _~~

u:

____~rl-------------------------------100 mV ABOVE SPIlCIPIED 11IRJlSHOLD

VIDEO

100 mV BELOW SPIlCIPIED 11IRJlSHOLD

J

CSYNC·

Video Input/Output Timing.

3 • 90

SECTION 3

J

j--IS

Bt261
Timing Waveforms (continued)

1'--____-'

IISYNC

L

~19

..

VIDEO
(llSYNC)

BELOW SPECIFIED TIlRESHOID

~

3-STATE

pcom

Video Input/Output Timing.

Ordering Information

Model Number

Package

Bt261KPI

28-pin Plastic
I-Lead

Ambient
Temperature
Range
O· to +70· C

IMAGING PRODUCTS

3 - 91

Preliminary Information
This document contains information on a new product. The parametric information,
although not fully characterized, is the result of testing initial devices.

Distinguishing Features

Applications

• Real-Time Color Space Conversion
Pseudo-Color Mode
• Progranunable Matrix Coefficients
• Three 256 x 8 Input Lookup Table RAMs
Standard MPU Interface
TTL Compatible
• +5 V Monolithic CMOS
84-pin PLCC Package
• Typical Power Dissipation: 1.1 W

Image Processing
• Image Capture
Color Correction

Bt2S1
36 MHz
Programmable
Color Space Converter
and Color Corrector

Product Description
The Bt281 Color Space Converter is designed
specifically for image capture and processing
applications. It provides real-time conversion of
the color space during the image capture process
or during the CRT display process. Thus, the
color space of the frame buffer may be optimized
for image processing applications regardless of
the type of video signal being digitized or the
requirement that ROB information be generated to
drive the CRT.

Functional Block Diagram

INO,INI

OUTO,OUTI

CFLAG

21
DAO·DA7

QAO·QA7

SHIff
AND

DBO·DB7

QBO·QB7

ROUNDING
DCO-DC7

QCO-QC7

OE'

Twenty-four bits of color information are input
via the DAx, DBx, and DCx inputs, converted to a
new color space by the 3 x 3 matrix multiplier,
and output onto QAx, QBx, and QCx.
Three independent 256 x 8 input lookup tables
enable the addition or removal of gamma
correction or gain control prior to converting to
another color space.
The QAx, QBx, and QCx outputs may be
three-stated asynchronously to CLOCK via the
OE* control input.

CLOCK

Two sets of matching delay lines are included to
maintain synchronization of control signals.
DO - D7

CS·

RD'

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121
(619) 452-7580· (800) VIDEO IC
TLX: 383 596 • FAX: (619) 452-1249
L281001 Rev. F

WR'

AO,Al

RESET"

3 • 93

Bt281
Circuit Description
MPU Interface
As seen in the functional block diagram and in Figure
I. the Bt281 supports a standard MPU interface
(DO-D7. CS*. RD*. WR*. AO. and AI). MPU
operations are asynchronous to clock.
AO and Al are used to select address register. RAM
location. or control register specified by the address
register. as shown in Table 1. The ll-bit address
register specifies which control register or RAM
location the MPU is accessing. as shown in Table 1.
The address register resets to $000 following a read or
write cycle to location $7FF. Write cycles to reserved
addresses are ignored. and read cycles from reserved
addresses return invalid data. ADDRll-ADDR15 are
always a logical zero.
The address register increments after each MPU read or
write cycle and is not initialized. ADDRO and ADDR8
correspond to data bus bit DO. with ADDRO being the
least significant bit. The address register is not
initialized following a reset or power-up condition.
The lookup table RAMs are not dual-ported. so MPU
accesses have priority over pixel accessing. During
MPU access to the color palette RAMs. the QAx.
QBx. and QCx outputs are undefined and invalid. Thus.
lookup table updates should occur only during
blanking intervals.

Matrix Multiplier
DAO-DA7. DBO-DB7. and DCO-DC7 are latched on
the rising edge of CLOCK and address the three color
lookup table RAMs. The outputs of the RAMs are
input to the 3 x 3 matrix multiplier.
The 3 x 3 matrix multiplier performs the fundamental
color space conversion. as follows:

ml-m9 are loaded by the MPU to perform the color
space conversion desired. The values of ml-m9 are
programmable over the range of -4.000 to +3.996
using 2's complement notation.
The 3 x 3 matrix mUltiplier generates three 21-bit
(including sign) values (one for each of the three
channels). As only 8 bits per channel may be output,
command bits CR17-CR15 are used to select which 8
bits (or 7 bits + sign) of these 21 bits are output. as
shown in Table 2.
The fractional data indicated in Table 2 is used to
round to 8 bits as follows: round up if the fractional
data = 0.5 and the rounded result will be an even
number (LSB =0) or if the fractional data is > 0.5. If
the fractional data is < 0.5. the number will be rounded
down. Circuitry is included to avoid wrapping around
on overflow or underflow conditions; rather the data
is saturated at the minimum and maximum allowable
values.
QAO-QA7. QBO-QB7. and QCO-QC7 are output
following the rising edge of CLOCK.
The QAx. QBx. and QCx outputs may be three-stated
asynchronously to the output clock via the OE*
control input and command bit CRlO.

Bypassing
The Bt28l may be entirely bypassed with no change
in the pipeline delay via the command register.
Following a reset condition. the Bt281 is initialized
to be in the bypass mode. (See Figure 8.)

I/O Delay Lines
The INO and INl inputs are latched on the rising edge
of CLOCK. pipe lined to maintain synchronization
with the color data, and output onto OUTO and OUTI.
The delay lines may be used for control signals. such
as sync. blank. etc.. that should have the same
pipeline delay as the pixel data.

3 - 94

SECTION 3

n:;.
~

S
.....
~

~

.,'"
~

.0'
....

~

i

®

O·

=
"""'
....=
S·
=
~

0

""l

DAD· DA7 -,;"t.i'~--l

~.

INTERPOlATION

;::

FILTER

MUX

~

l·MUX

QAO-QA7

(A+B)/2

:--

'-'

MATRIX

MULTIPLY

QBO-QB7

DBD - DB1 --,17<-'--1

0

'"e.

!>CO - DC!

SHIITING

-7L----1

EVEN

~

;:".

....
=::
;r.-

C:l
....

z

C:l
"':i

::0
0
0

e

..,

""0

MUX

ROUNDING

INTFRPOLAnON

DEMUX

t-r-

QCO - QC7

FILTER

b:I

...SO

~

Q.

3X3

EVEN
ROUNDING

(A+B)l2

MULTIPLEXED
EVEN
ROUNDING

INTERPOlATION

crlAG~~----~----~

INTERPOlATE

is'

DYNAMIC
RANGE
SELECT
CPLAG

~

j!

DEClMATION

IIII I I
00-D7

RD·

WR'"

CS·

AD,At

SELECT

RES~

~

CIl

co

~

N
00

r.M
Ie

~

III

II

Bt281
Circuit Description (continued)

Al,AO

ADDRO-ADDRlO

Accessed by MPU

00
01

$xxx
$xxx

address register low (ADDRO-ADDR7)
address register high (ADDR8-ADDRI0)

10
10

$000
$001

DA RAM location $00
DA RAM location $01

:

:

:

10
10
10

$OFF
$100
$101

DA RAM location $FF
DB RAM location $00
DB RAM location $01

:

:

:

10
10
10

$IFF
$200
$201

DB RAM location $FF
DC RAM location $00
DC RAM location $01

:

:

:

10

$2FF

DC RAM location $FF

10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10

$300
$301
$302
$303
$304
$305
$306
$307
$308
$309
$30A
$30B
$30C
$30D
$30E
$30F
$310
$311
$312
$313
$314

ml register low
ml register high
m2 register low
m2 register high
m3 register low
m3 register high
m4 register low
m4 register high
m5 register low
m5 register high
m6 register low
m6 register high
m7 register low
m7 register high
m8 register low
m8 register high
m9 register low
m9 register high
command registecO
command register_l
reserved

:

:

:

10
11

$7FF
$xxx

reserved
reserved

Table 1.

3 • 96

SECTION 3

Control Register Addressing.

Bt281
Circuit Description (continued)
Matrix Multiplication Operation
8-bit pixel input:
ll-bit coefficient:

DA7 DA6 DAS DA4 DA3 DA2 DA1 DAO
C10 C9 C8 . C7 C6 C5 C4 C3 C2 C1 CO

5 T17 T16 T15 T14 T13 T12 Tll T10 T9 T8 . T7 T6 T5 T4 T3 T2 T1 TO

19-bit total:

Three of these 19-bit totals (since there are three coefficients per channel) must be added together, resulting in a 21bit result per channel (5 = sign bit):

-

5 R19 R18 R17 R16 R15 R14 R13 R12 Rll RIO R9 R8 . R7 R6 R5 R4 R3 R2 R1 RO

CR17-CR15

QA7

QA6

QAS

QA4

QA3

QA2

QA1

QAO

Used for Rounding

R19
R18
R17
R16
R15

R18
R17
R16
R15
R14

R17
R16
R15
R14
R13

R16
R15
R14
R13
R12

R15
R14
R13
R12
R11

R14
R13
R12
Rll
RIO

R13
R12
Rll
RIO
R9

R12
R11
RIO
R9
R8

Rll-RO
R10-RO
R9-RO
RS-RO
R7-RO

S

Rl8
Rl7
Rl6
R15
Rl4

R17
Rl6
Rl5
Rl4
Rl3

R16
R15
R14
Rl3
Rl2

R15
Rl4
R13
Rl2
R11

R14

R13
Rl2
R11
RIO
R9

kl.l.
R11
RIO
R9
R8

kll-Rv
RIO-RO
R9-RO
RS-RO
R7-RO

unsigned
magnitude
format
100
011
010
001
000
other two
formats
100
011
010
001
000

Table 2.

5
5
5
5

R13
R12
R11
RIO

Example Dynamic Output Range Selections (QAx Channel).

IMAGING PRODUCTS

3 • 97

Bt2S1
Circuit Description (continued)
Number Representations

2's Complement Representation

The Bt281 accommodates analog sign magnitude,
unsigned magnitude, and 2's complement formats to
ease interfacing to NO and D/A converters, frame
buffers, and processing circuits. (See Table 3.)

Frame buffers and image processors commonly use 2's
complement representation t:l simplify sign bit
handling.
Only the DAx and OCx inputs and the QAx and QCx
outputs can be configured for this representation for
processing of color difference signals (Cr/Cb, IIQ,
UN, R-Y/B-Y, etc.). The DBx inputs and QBx outputs
are always configured for 8-bit unsigned magnitude
representation (O-25S) for luminance processing.

Offset Binary Representation
Only the DAx and OCx inputs and the QAx and QCx
outputs can be configured for this representation for
processing of color difference signals (Cr/Cb, IIQ,
UN, R-Y/B-Y, etc.). The DBx inputs and QBx outputs
are always configured for 8-bit unsigned magnitude
representation (0-2SS) for luminance processing.

2's complement may be used at the input if a frame
buffer is driving the DAx and DCx inputs to ease
interfacing to other image processing circuitry. 2's
complement may be used at the output if the QAx and
QCx outputs are interfaced to a frame buffer to ease
interfacing to image processing circuitry.

Offset binary representation should be used if NO
converters drive the DAx and DCx inputs (with the
NO midscale corresponding to zero).

Unsigned Magnitude Representation

Offset binary representation should be used at the
output if the QAx and QCx outputs drive D/A
converters (with the D/A midscale corresponding to
zero).

This 0 to 2SS range input/output format is used when
the Bt281 is inputting or outputting ROB video
signals.

2's Complement
Representation

Offset Binary
Representation
DAx,DCx,
QAx,QCx

DA7-DAO,
OC7-OCO

Represented

DA7-DAO,
DC7-DCO

$FF
$FE
:
$81
$80
$7F

1111 1111
1111 1110

+127
+126

1111 1111
1111 1110

Number

:

:

:

1000 0001
1000 0000
0111 1111

+1
0
-1

1000 0001
1000 0000
0111 1111

Represented

DA7-DAO,
DC7-DCO

-1
-2
:
-127
-128
+127

1111 1111
1111 1110
:
1000 0001
1000 0000
0111 1111

Number

Number

Represented
2SS
2S4
:

129
128
127

:

:

:

:

:

:

:

$01
$00

0000 0001
0000 0000

-127
-128

0000 0001
0000 0000

+1
0

0000 0001
0000 0000

1
0

Table 3.

3 • 98

Unsigned Magnitude
Representation

SECTION 3

Numbering Representations.

Bt281
Circuit Description (continued)
Input Interpolation Circuitry
The Bt281 may be configured to input 8 bits of
luminance on the DBx inputs and 8 bits of
multiplexed color difference signals on the DCx
inputs. The multiplexed color difference signals are
demultiplexed and the missing values interpolated
using linear interpolation filters. The resulting 24
bits of luminance and color difference data are input to
the 3 x 3 matrix multiplier for processing (see Figure
9). The DAx inputs are ignored. Figure 2 illustrates
the input interpolation circuitry.
Assume YCrCb processing with Y input via the DBx
inputs and multiplexed Cr/Cb input via the DCx
inputs:
The 16-bit input sequence is:
DBx= Y (n)
DCx= Cb (n)

Y (n + 1)

Cr (n)

Y(n+2)
Cb (n + 2)

Y(n+3)
Cr (n + 2)

The 24-bit output after the interpolation filters is:
DBx '= Y (n) Y (n + 1) Y (n + 2)
Y (n + 3)
DCx '= Cb (n) Cb (n + 1) Cb (n + 2) Cb (n + 3)
DAx'= Cr(n) Cr(n+l) Cr(n+2) Cr(n+3)

may be input via the DAx and DCx inputs, with a data
rate of 1/2 the DBx inputs (see Figure 11). The
interpolation filter generates the missing values by
averaging successive data points.
Assume YCrCb processing with Y input via the DBx
inputs, Cr input via the DAx inputs, and Cb input via
the DCx inputs:
The 24-bit input sequence is:
DAx= Cr(n)
DBx= Y(n)
DCx= Cb (n)

Cr(n)
Y(n+l)
Cb (n)

Cr (n + 2)
Y(n+2)
Cb (n + 2)

Cr (n + 2)
Y(n+3)
Cb (n + 2)

The 24-bit output after the interpolation filters is:
DBx'= Y(n)
Y(n+l) Y(n+2)
DCx' = Cb (n) Cb (n + 1) Cb (n + 2)
DAx'= Cr(n) Cr(n+l) Cr(n+2)

Y(n+3)
Cb (n + 3)
Cr(n+3)

In either case, the DBx inputs are configured for an
unsigned magnitude representation, while the DAx
and DCx inputs are configured for either offset binary
or 2's complement numbering representation.

The CFLAG input indicates whether the multiplexed
DCx inputs contain Cb (CFLAG = 1) or Cr (CFLAG =
0) information. The demultiplexer, controlled by
CFLAG, demultiplexes the Cr and Cb information.
Alternately, nonmultiplexed color difference signals

DAO·DA7

-"7'----1

MUX

INTIlRPOLATION
Pll.TER
(A+B)/2

MUX

DAx·

EVEN
ROUNDING

DBO·DB7

TO

DBx'

-"7'----1

3X3

MATRIX
MULTIPLIER

DCO.DC7 -~--I

oc".

DEMUX
MULTIPUlXED
INTIlRPOLATION

INTIlRPOLATION
Pll.TER
(A+B)/2
EVEN
ROUNDING
INTERPOLATE

CFlAG

Figure 2.

Input Interpolation Circuitry.

IMAGING PRODUCTS

3 - 99

Bt2S1
Circuit Description (continued)
The output of the interpolation filters is 9 bits
(including sign). Rounding to 8 bits is done as
follows: round up if the fractional data = 0.5 and the
result will round to an even number (LSB = 0) or if the
fractional data is > 0.5. If the fractional data is < 0.5,
the number will be rounded down.

Output Decimation Circuitry
The Bt281 may be configured to output 8 bits of
luminance on the QBx outputs and 8 bits of
multiplexed color difference signals on the QCx
outputs. The color difference signals from the matrix
mUltiplier are decimated and multiplexed onto the QCx
outputs (see Figure 10).

Decimation is done by the multiplexer, by removing
every other sample of color information.
Figure 3 illustrates the output decimation circuitry.
Assume YCrCb processing with Y output via the QBx
outputs and multiplexed CrCb output via the QCx
outputs:
The 24-bit input to the decimation circuit is:
QAx'= Cr (n) Cr (n+ 1) Cr (n+ 2)
QBx' = Y (n) Y (n + 1) Y (n + 2)
QCx' = Cb (n) Cb (n + 1) Cb (n + 2)

Cr (n+ 3)
Y (n + 3)
Cb (n + 3)

The output sequence is:
The QBx outputs are configured for an unsigned
magnitude representation, while the QAx and QCx
outputs are configured for either offset binary or 2's
complement representation.
The CFLAG input is used to specify whether Cr or Cb
data is to be output onto the QCx bus. If CFLAG is a
logical zero, Cb data is output during the next clock
cycle. If CFLAG is a logical one, Cr data is output
during the next clock cycle. This timing enables the
CFLAG status to match the data present on the QCx
outputs.

QBx= Y(n)
QCx= Cb (n)
QAx= Cr(n)

Y (n+ 1) Y(n+2)
Cr (n)
Cb (n + 2)
Cr(n+l) Cr(n+2)

Note that the QAx outputs contain normal output data.

QAx'

-/
/

PROM
3X3

QJIJt.

,8.,

MATRIX
MULTlPLlI!R

0-

QOt.

,

8.,

M1lX

1

'--.--

mAo

?

r
DBaMATION
SELI!CT

Figure 3.

3 - 100

SECTION 3

Y(n+3)
Cr (n + 2)
Cr(n+3)

Output Decimation Circuitry.

QAO·QA7

QBO-QB7

Bt2S1
Circuit Description (continued)
Typical Applications
Figure 4 shows two common applications of the
Bt281. Figure 4a shows the Bt281 being used when
the color space of the analog video signal to be
digitized may be one of several formats. The Bt281 is
ensures that the video data is converted into the color
space of the frame buffer.

The Bt281 enables these color space transformations
to take place in real time, simplifying the system
design.

In Figure 4b, the Bt281 is used to convert a frame
buffer using a color space other than ROB (i.e., YIQ,
YUV, etc.) into the ROB color space to drive the CRT
display.

Bt28 I

I

AID

1
ANALOG VIDEO
INFORMATION
(ROB. Y1Q. YIN.BTC.)

1

I
1

I

AID

AID

I

8

8
RO·R7

/

1

/

loo-07

,/

1BO-B7

,

OAO-OA7

QAO-QA7

,/

OBO-DB7

QBO-QB7

,/

DOl-DC7

Qal-QC7

,,

8

8

J

I

Figure 46.

8

8

Typical Application.

..............................................

Bt281

DlorrAI.. VIDEO
FROMFRAMB

B\JFI'IlR

8

,

/

,

/

8
DAO-DA7

QAO-QA7

,/

DBO-DB7

QBO-QB7

,/

DCO-DC7

QCl-QC7

,/

8

RO-R7

8

8

1

I
00-071

I

(RGB, YIQ. YIN, ETC.)

,/

DIGITAl.. VIDEO
TO FRAMIl BUPPBR
(ROB. Y1Q. YIN.BTC.)

8
BO-B7

,

1

I

D/A

D/A

D/A

1

~

!
!

I
1
1

ANALOGRGB
TOMONrrOR

1

I

L.............................................."

Figure 4b.

Typical Application.

IMAGING PRODUCTS

3 - 101

Bt281
Internal Registers
Command Register_O
This command register may be written to or read by the MPU at any time and is initialized to $00 following a reset
sequence. CROO is the least significant bit and corresponds to data bus bit DO. Note that the pipeline delay is
constant regardless of the input/output configuration.
CR07-CR05

DAx, DCx input format select
(000)
(001)
(010)
(011)

unsigned magnitude (nonmultiplexed, no interpolation)
offset binary (nonmultiplexed, no interpolation)
offset binary (nonmultiplexed, interpolated)
offset binary (multiplexed, interpolated)

(100)
(101)
(110)
(111)

2's complement (nonmultiplexed, no interpolation)
2's complement (nonmultiplexed, interpolated)
2's complement (multiplexed, interpolated)
pseudo-color mode (unsigned magnitude, nonmultiplexed, no interpolation)

These bits are ignored in bypass mode. They specify the input format and range for the DAx and
DCx inputs. The DBx inputs are always configured for unsigned magnitude operation.
If pseudo-color mode is selected, the DBx inputs address all three lookup table RAMs
simultaneously, generating 24 bits of color information. The DAx and DCx inputs are ignored.

CR04-CR02

QAx, QCx output format select
(000)
(001)
(010)
(011)

unsigned magnitude (nonmultiplexed, no decimation)
offset binary (nonmultiplexed, no decimation)
offset binary (multiplexed, decimated)
reserved

(100)
(101)
(110)
(111)

2's complement (nonmultiplexed, no decimation)
2's complement (multiplexed, decimated)
reserved
reserved

These bits specify the output format and range for the QAx and QCx outputs. The QBx outputs are
always configured for unsigned magnitude operation. These bits are ignored in bypass mode.

CR01

Error flag
(0) reset by MPU
(1) set by device

This bit is set by the device if a negative number is detected on the QAx, QBx, or QCx outputs
while outputting an unsigned magnitude number (which should always be positive). To reset the
bit to a logical zero, the MPU must write a logical zero to this bit. Note that the error flag may be
set if the MPU accesses the lookup table RAMs and while programming the command registers if
the operating mode is changed.

3 • 102

SECTION 3

Bt281
Internal Registers (continued)
Command Register_0 (continued)

CROO

Overflow I underflow error flag
(0) reset by MPU
(1) set by device

This bit is set by the device if an overflow or underflow condition is detected on the 3 x 3 matrix
mUltiplier outputs (prior to the saturation circuitry). To reset the bit to a logical zero, the MPU
must write a logical zero to this bit Note that the overflow/underflow flag may be set if the MPU
accesses the lookup table RAMs and while programming the command registers if the operating
mode is changed.

Command Register_1
This command register may be written to or read by the MPU at any time and is initialized to $E1 following a reset
sequence. CR10 is the least significant bit and corresponds to data bus bit DO. Note that the pipeline delay is

constant regardless of the input/output configuration.

CR17-CR15

Matrix dynamic output range select
(000)
(001)
(010)
(011)
(100)
(101 )
(110)
(111)

R8-RI5 for unsigned magnitude output format; R9-R14 + sign for other formats
R9-R16 for unsigned magnitude output format; R10-R15 + sign for other formats
RIO-R17 for unsigned magnitude output format; Rll-R16 + sign for other formats
Rll-R18 for unsigned magnitude output format; R12-R17 + sign for other formats
R12-R19 for unsigned magnitude output format; R13-R18 + sign for other formats
reserved
reserved
bypass device

Mode (111) specifies to bypass the entire device with no change in pipeline delay. See Table 2.

CR14-CRll

reserved

CRIO

QAx, QBx, QCx output disable
(0) enable QAx, QBx, and QCx outputs
(1) disable QAx, QBx, and QCx outputs

This bit is logically gated with the DE* input pin, and the resulting value is used to control
three-stating the QAx, QBx, and QCx outputs.

IMAGING PRODUCTS

3 • 103

Bt281
Internal Registers (continued)
ml-m9 Low/High Registers
For the ml-m9 values, the 8-bit low and high registers are cascaded to form a 11-bit register. DO-07 comprise the
low register, while 08-010 comprise the high register (08 corresponds to data bus bit DO). 03-07 of ml-m9 high
registers are always a logical zero.
The ml-m9 low/high registers may be written to or read by the MPU at any time and are not initialized following a
reset sequence. DO is the least significant bit.
These registers specify the matrix operators from-4.000 to +3.996 (using 2's complement notation) as follows:

010-00

Value

111 . 1111 1111
111 . 1111 1110

-0.004
-0.008
:
-3.996
-4.000
+3.996
:
+0.004
+0.000

:

100. 0000 0001
100. 0000 0000
011. 1111 1111
:
000. 0000 0001
000. 0000 0000

3 • 104

SECTION 3

Bt281
Pin Descriptions
Pin Name

Description

OAO-OA7,
OBO-OB7,
DCO-DC7

Color inputs (1TL compatible). These inputs are latched on the rising edge of CLOCK. OAO,
OBO, and OCO are the least significant bits.

QAO-QA7,
QBO-QB7,
(12O-QC7

Color outputs (TTL compatible). These signals are output following the rising edge of CLOCK.
QAO, QBO, and (120 are the least significant bits.

INO, INI,
OUTO,OUTI

Input/output delay line (1TL compatible). INO and INI are latched on the rising edge of CLOCK,
pipelined to maintain synchronization with the color data, and output onto OUTO and OUTI
following the rising edge of CLOCK.

CFLAG

Multiplex control input (TTL compatible). If the OAx/DCx inputs are multiplexed, CFLAG
indicates when OCx data is present (CFLAG = 1). If the QAx!QCx outputs are multiplexed,
CFLAG indicates when (12x data is to be output (CFLAG = 1). CFLAG is latched on the rising
edge of CLOCK. This input is ignored when in the bypass mode.
Output enable control input (1TL compatible). This input is logically gated with command bit
CRI0, and the result controls three-stating the QAx, QBx, and QCx outputs. OUTO and OUTI
are not three-statable.
CRIO

OE'"

QAx, QBx, (12x Outputs

0
0
1
1

0
1
0
1

enabled
three-stated
three-stated
three-stated

CLOCK

Clock input (TTL compatible).

00-07

Bidirectional MPU data bus (TTL compatible). MPU data is input to and output from the device
via this 8-bit data bus. DO is the least significant bit.
Chip select control input (TTL compatible). CS'" is latched on the falling edge of either RO'" or
WR.... An internally latched logical zero enables data to be written to or read from the device by
the MPU. CS'" should be connected to GND if not used.

RD'"

Read control input (1TL compatible). A logical zero enables the MPU to read data from the
device. Both RO'" and WR'" should not be asserted simultaneously. (See Figure 7.)

WR'"

Write control input (1TL compatible). DO-07 data is latched on the rising edge of WR .... Both
RO'" and WR'" should not be asserted simultaneously. (See Figure 7.)
LatchedCS*

RD·

WR*

MPU Operation

0
0
0
0
I

0
0
1
I
x

0
1
0
I
x

invalid operation
read data onto DO-07
write DO-07 data
DO-07 three-stated
DO-07 three-stated

IMAGING PRODUCTS

3 • lOS

Bt281
Pin Descriptions (continued)
Pin Name

Description

AO,AI

Register select inputs (ITL compatible). AO and Al are latched on the falling edge of either RD*

orWR*.
RESET*

Reset control input (ITL compatible). RESET* must be a logical zero for a minimum of three
consecutive clock cycles to reset the device. RESET* must be a logical one for normal
operation.

vee

Power. All

GND

Ground. All GND pins must be connected together.

3 • 106

vee pins must be connected together.

0IITl

S3

DBI

QCO

51

DBO

QCl

51

DA7

QC2

SO

DA6

QC3

49

DAS

vee

4B

DM

ON»

47

DAl

QC4

DAl

QCS

46
45

QC6

44

DAO
CLOCK

DAl

QC1

43

ON»

4:a

OND

QBO

41

vee

QBI

40

WR"

QB2

39

RD'"

QB3

38

CS"

OND

37

AO

QB4

36

Al

QBS

35

vee

QB6

34

RBSllT*

QB7

33

vee

SECTION 3

Bt2S1
Application Information
RGB-to-Y,R-Y,B-Y

Conversion

The matrix for converting analog RGB to Y, R-Y, B-Y
is as follows. The RGB inputs are normalized to have
a range of 0 to 1 and are gamma-corrected RGB data.

R~YI

[ 0299

B-Y

0.587

Given the resolution of the Bt281 is limited to
0.0039063 (1/256), and the previously specified
input/output pin assignments, the following matrix is
used (after 2's complement conversion and

0114]
0

0.701

-0.587 -0.114

-0.299

-0.587

0.886
(B- Y)'

Note that the analog (R - Y) and (B - Y) terms have an
output range of t 0.701 and t 0.886, respectively,
while Y has a range of 0 to 1.
The conversion of digital RGB to normalized digital
Y, (R - Y)" (B - Y)' (the' indicates normalized
notation) is slightly different in order to compress the
(R - Y)' and (B - Y)' output range to to.5. The input
and output assignment of the Bt281 video I/O pins is
assumed to be as follows:

$0.80

$7.95

$7.EC

$O.4C

$0.96

$0.10

$7.D5

$7.AC

$0.80
1 :

I ..

The command register should specify unsigned
magnitude representation for the DAx and DCx inputs,
and either offset binary or 2's complement
representation for the QAx and QCx outputs.
Command bits CRI7-CRI5 should be 000.

DAO-DA7 = Ro-R7
DBO-DB7 = Go-G7
DCO-DC7

=Bo-B7

QAO-QA7 = (R - Y)'o-(R - Y>'7
QBO-QB7 = Yo-Y7
QC0-QC7 = (B - Y)'o-(B - Y)'7

The RGB inputs to the matrix can have a range of 0 to
255; the lookup table RAMs on the Bt281 may be
used to gamma-correct the RGB data if necessary. The
Y output of the matrix can have a range of 0 to 255,
while the (R - Y)' and (B - Y)' outputs can have a
range of -128 to +127. The ideal matrix (normalized
to the dynamic range) is as follows:

Y

J

(R - Y)'
1
(B- Y)'

=

0.587
[0.299
0.500
-0.169

0.114]1 G
R
-0.419 -0.081
-0.331

0.500

B

I
IMAGING PRODUCTS

3 - 107

Bt281
Application Information (continued)
RGB to YUV Conversion
The matrix for converting analog RGB to YUV is as
follows. The RGB inputs are normalized to have a
range of 0 to 1 and are gamma-corrected RGB data.

0.299
[ -0.169
0.500

0.615

-0.515 -0.100

B

Note that the analog U and V terms have an output
range of ± 0.436 and ± 0.615, respectively, while Y
has a range of 0 to 1.
Note that U and V may also be dermed as:
U = (B - Y) /2.03

=0.4926(B -

Y)

0.587
-0.331

0.114] [ R [
0.500
G

-0.419 -0.081

B

Given the resolution of the Bt281 is limited to
0.0039063 (1/256), and the previously specified
input/output pin assignments, the following matrix is
used (after 2'5 complement conversion and row
swapping:
$0.80

$7.95

[ $O.4C

$0.96

$7.EC]
$0.10

$7.D5

$7.AC

$0.80

V = (R - y) /1.14 = 0.8772(R - Y)

The conversion of digital RGB to normalized digital
YU'V' (the' indicates normalized notation) is slightly
different in order to compress the V' output range to
±a.5 and to expand the U' output range to ±0.5. The
input and output assignment of the Bt281 video I/O
pins is assumed to be as follows:

DAO-DA7 = Ro-R7
DBO-DB7 = Oo-G7
DCO-DC7 = BO-B7
QAO-QA7 = V'o-V'7
QBO-QB7 = YO-Y7

QC0-QC7 =U'o-U'7
The ROB inputs to the matrix can have a range of 0 to
255; the lookup table RAMs on the Bt281 may be
used to gamma-correct the RGB data if necessary. The
Y output of the matrix can have a range of 0 to 255,
while the U' and V' outputs can have a range of -128
to +127. The ideal matrix (normalized to the dynamic
range) is as follows:

3 - 108

SECTION 3

The command register should specify unsigned
magnitude representation for the DAx and DCx inputs,
and either offset binary or 2's complement
representation for the QAx and QCx outputs.
Command bits CRI7-CRI5 should be 000.

Bt281
Application Information (continued)
RGB to YIQ Conversion
The matrix for converting analog RGB to YIQ is as
follows. The RGB inputs are normalized to have a
range of 0 to 1 and are gamma-corrected RGB data.
0.299
[ 0.596
0.212

0.587
0.114] [ G
R
-0.275 -0.321
-0.523

0.311

I

B

Note that the analog I and Q terms have an output
range of ±O.596 and ±0.525, respectively, while Y
has a range of 0 to 1.

I and Q may also be defined as follows:
1= Vcos 33° - Usin 33°

Q = Vsin 33° + Ucos 33°
or
I = 0.839V - 0.545U

Q = 0.545V + 0.839U

The RGB inputs to the matrix can have a range of 0 to
255; the lookup table RAMs on the Bt281 may be
used to gamma-correct the RGB data if necessary. The
Y output of the matrix can have a range of 0 to 255,
while the l' and Q' outputs can have a range of -128 to
+127. The ideal matrix (normalized to the dynamic
range) is as follows:
0.299

0.587

[ 0.500

-0.231

0.114] [ G
R
-0.269

0.203

-0.500

0.297

B

I ..

Given the resolution of the Bt281 is limited to
0.0039063 (1/256), and the previously specified
input/output pin assignments, the following matrix is
used (after 2's complement conversion and row
swapping):
$0.80

$7.C5

[ $OAC

$0.96

S7.BC][
R
$0.10
G

SO.33

$7.80

$OAC

I

B

or
I = 0.736(R - Y) - 0.268(B - Y)

Q = OA78(R - Y) + OA13(B - Y)
The conversion of digital RGB to normalized digital
YI'Q' (the' indicates normalized notation) is slightly
different in order to compress the r and Q' output
range to ±0.5. The input and output assignment of the
Bt281 video I/O pins is assumed to be as follows:

The command register should specify unsigned
magnitude representation for the DAx and DCx inputs,
and either offset binary or 2's complement
representation for the QAx and QCx outputs.
Command bits CR17-CRI5 should be 000.

DAO-DA7 = RO-R7
DBO-DB7 =Go-G7
DCO-DC7 = BO-B7
QAO-QA7 =1'0-1'7
QBO-QB7 =YO-Y7
QCO--QC7 = Q'0-Q'7

IMAGING PRODUCTS

3 - 109

Bt281
Application Information (continued)
Y/R-Y/B-Y-to-RGB

Conversion

The matrix for converting analog Y/R-Y/B-Y to ROB
is as follows.
The Y,R-Y,B-Y inputs are not
normalized and generate gamma-corrected ROB data.

:] [

-0.509

o

Note that the analog (R - Y) and (B - Y) terms have an
input range of ±0.701 and ±0.886, respectively,
while Y has a range of 0 to 1.
The conversion of normalized digital Y,(R - Y)',(B Y)' (the' indicates normalized notation) to digital
ROB is slightly different as the (R - Y)' and (B - Y)'
input range has probably been compressed to ±0.5.
The input and output assignment of the Bt281 video
I/O pins is assumed to be as follows:
DAO-DA7 = (R - Y)'o-(R - Y>,?
DBO-DB7 =YO-Y7
DCO-DC7 =(B - Y)'o-(B - Y)'7
QAO-QA7 =Ro-R7
QBO-QB7 = Oo-G7
QCO-QC7 =Bo-B7

The Y input to the matrix can have a range of 0 to 255
for Y, while the (R - Y)' and (B - Y)' inputs can have
an input range of -128 to +127. The gamma-corrected
ROB outputs of the matrix can have a range of 0 to
255. The ideal matrix (normalized to the dynamic
range) is as follows:

:[

[]

3 - 110

1.402
-0.714

o

~

_0:44] [(R Y),]
1.772

SECTION 3

(B- Y)'

Oiven the resolution of the Bt281 is limited to
0.0039063 (1/256), and the previously specified
input/output pin assignments, the following matrix is
used (after 2's complement conversion and row
swapping):
$1.66

$1.00

[ $7.4A

$1.00

$0.00 ] [(R - Y)]
$7.A8
Y

$0.00

$1.00

$1.C5

(B - Y)'

The command register should specify unsigned
magnitude representation for the QAx and QCx
outputs, and either offset binary or 2's complement
representation for the DAx and DCx inputs.
Command bits CRI7-CRI5 should be 000.

Bt281
Application Information (continued)
YUV-to-RGB Conversion
The matrix for converting analog YUV to RGB is as
follows. The YUV inputs are not normalized and
generate gamma-corrected RGB data.

:] [

o
-0.39S
2.032

~:4:1] [:]

Note that the analog U and V terms have an input
range of ±O.436 and ±0.6IS, respectively, while Y
has a range of 0 to 1.
The conversion of normalized digital YU'V' (the '
indicates normalized notation) to RGB is slightly
different as the V' input range has probably been
compressed to ±O.S while the U' input range has
probably been expanded to ±O.5. The input and
output assignment of the Bt281 video I/O pins is
assumed to be as follows:

Given the resolution of the Bt281 is limited to
0.0039063 (112S6), and the previously specified

input/output assignment, the following matrix is used
(after 2's complement conversion and row swapping):

[:

$1.66

$1.00

[ $7.4A

$1.00

$0.00] [ V
$7.A8
Y

$0.00

$1.00

$1.CS

I

U'

The command register should specify unsigned
magnitude representation for the QAx and QCx
outputs, and either offset binary or 2's complement
representation for the DAx and DCx inputs.
Command bits CRI- CR1S should be 000.

DAO-DA7 = V'frV'7
DBO-DB7 =YfrY7
OCO-OC7 = U'frU'7
QAO-QA7 = RO-R7
QBO-QB7 = Gfr07
QCO-QC7 = BO-B7

The Y input to the matrix can have a range of 0 to
255, while the U' and V' inputs can have an input
range of -128 to +127. The gamma-corrected RGB
outputs of the matrix can have a range of 0 to 2SS.
The ideal matrix (normalized to the dynamic range) is
as follows:

:I [

o
1.402] [ U'
Y
-0.344 -0.714
1.772

o

I

V

IMAGING PRODUCTS

3 - 111

..

Bt281
Application Information (continued)
YIQ-to-RGB Conversion
The matrix for converting analog YIQ to ROB is as
follows. The YIQ inputs are not normalized and
generate gamma-corrected ROB data.

0.956
-0.272

[ :1 [

-1.108

:~~::7] [:1
1.705

Q

Note that the analog I and Q terms have an input range
of ± 0.596 and ± 0.525, respectively, while Y has a
range of 0 to 1.
The conversion of normalized digital YI'Q' (the '
indicates normalized notation) to ROB is slightly
different as the r and Q' input range has probably been
compressed to ± 0.5. The input and output
assignment of the Bt281 video I/O pins is assumed to
be as follows:
DAO-DA7 = Io-I7
DBO-DB7 = Yo-Y7
DCO-DC7=~

QAO-QA7 = Ro-R7
QBO-QB7 = 00-07
QCO-QC7 = BO-B7

The Y input to the matrix can have a range of 0 to
255, while the r and Q' inputs can have an input range
of -128 to +127. The gamma-corrected ROB outputs
of the matrix can have a range of 0 to 255. The ideal
matrix (normalized to the dynamic range) is as
follows:
1.139

[ :1 [

3 - 112

0.648] [ Y
-0.324 -0.677
I'
-1.321

SECTION 3

1.783

Q'

1

Given the resolution of the Bt281 is limited to
0.0039063 (1/256), and the previously specified
input/output assignment, the following matrix is used
(after 2's complement conversion and row swapping):

[:

$1.23

$1.00

[ $7.AE

$1.00

$0.A5] [ I'
$7.53
Y

B

$6.AE

$1.00

$l.C8

1

Q

The command register should specify unsigned
magnitude representation for the QAx and QCx
outputs, and either offset binary or 2's complement
representation for the DAx and DCx inputs.
Command bits CRI7-CRI5 should be 000.

Bt281
Application Information (continued)
YIQ (D2 Format)-to-RGB Conversion
The D2 format digitizes the entire composite color
video signal, including sync information. Thus, after
digitally separating the Y, I, and Q information, the Y
information has a range of 0-130, I has a range of
0-78 and Q has a range of 0-±68.

Given the resolution of the Bt281 is limited to
0.0039063 (1/256), and the previously specified
input/output assignment, the following matrix is used
(after 2's complement conversion and row swapping):

The
matrix to
forRGB
converting
digital YIQ (derived fr0ym a
D2 format)
is as follows.

[ :R [

:B [

[ :1 :.:9:7:2

~::::: -31~.23·:6:17]

[ QI [

-2.187
The input and output assignment of the Bt281 video
I/O pins is assumed to be as follows:

[$::l.:E:O:

$l.F9
$1.F9

$1.39] [ I [
$6.BC
Y

$1.F9

$3.5C

Q

The command register should specify unsigned
magnitude representation for the QAx and QCx
outputs, and either offset binary or 2's complement
representation for the DAx and DCx inputs.
Command bits CRI7-CRI5 should be 100.

DAO-DA7 = Io-I7
DBO-DB7 =YrrY 7
DCO-DC7 =QO-Q7
QAO-QA7 = RO-R7
QBO-QB7 = Go4J7
QCO-QC7 = BO-B7

The Y input to the matrix can have a range of 0-130,
while the I and Q inputs can have a range of 0-±78 and
Q can have a range of 0-±68. The gamma-corrected
RGB outputs of the matrix have a range of 0-255.

IMAGING PRODUCTS

3 - 113

..

Bt281
Application Information (continued)
Concatenating Matrices
By concatenating matrices, conversions such as YIQ
to YUV may be implemented. The procedure for
concatenating matrices is as follows:

[ .j+~+~

ak+bn+cq

m+oo+a]

dj +em+fp

dk+en+fq

dl+eo+fr

gj +hm +ip

gk+hn+iq

gl+ho+ir

[

a

b

c

d

e

f

g

h

][ :

k

n
q

o

]

Implementing RGB to HSV

Implementing HSV to RGB

ROB to HSV may be performed by configuring the
Bt281 to implement ROB-to-Y/R-Y/B-Y conversion.

HSV to ROB may be performed by configuring the
Bt281 to implement Y/R-Y/B-to-ROB conversion.

The V value is equivalent to the Y (luminance) output
onto QBO-QB7.

The V value is equivalent to the Y (luminance) input
via DBO-DB7.

Saturation (S) = SQRT(R - y2) + (B - Y)

R-Y =S*cos(H)

Hue (H) = tan-I (B - Y) I (R - Y)

B-Y=S*sin(H)

Using the 16 bits (8 bits each) of (R - Y) and (B - Y)
data generated by the Bt281 to address a 64K x 8 ROM
(a 16K x 8 ROM may be used addressed by the six
MSBs of the (R - Y) and (B - Y) data), the ROM is be
programmed to generate 8 bits of saturation data using
the equation above. An output register on the ROM
data outputs may be needed to meet setup and hold
times for any circuitry after the ROM.

Using the 16 bits (8 bits each) of saturation (S) and
hue (H) data to address a 64K x 8 ROM (a 16K x 8
ROM may be used addressed by the six MSBs of the S
and H data), the ROM may be programmed to generate
8 bits of (R - Y) data to input to the Bt281 using the
equation above. An input register on the ROM data
inputs may be needed to meet setup and hold times to
the ROM.

The same 16 bits of (R - Y) and (B - Y) data generated
by the Bt281 to address another 64K x 8 ROM (a 16K
x 8 ROM may be addressed by the six MSBs of the (R
- Y) and (B - Y) data), this ROM is programmed to
generate 8 bits of hue data using the equation above.
An output register on the ROM data outputs may be
needed to meet setup and hold times for any circuitry
after the ROM.

The same 16 bits (8 bits each) of saturation (S) and
hue (H) data to address a 64K x 8 ROM (a 16K x 8
ROM may be used addressed by the six MSBs of the S
and H data), the ROM is programmed to generate 8
bits of (B - Y) data to input to the Bt281 using the
equation above. An input register on the ROM data
inputs may be needed to meet setup and hold times.

A single 64K x 16 ROM may be used instead of two
64Kx8 ROMs.

3 • 114

SECTION 3

A single 64K x 16 ROM may be used instead of two
64Kx 8 ROMs.

Bt281
Application Information (continued)
Matrix Coefficient Considerations

Adjusting Contrast and Saturation

The example matrices are only typical; adjustment of
the matrix coefficients may be required to minimize
rounding errors, especially when multiple devices are
cascaded.

By scaling the matrix or lookup table RAM values,
the contrast and saturation of a video signal may be
adjusted while simultaneously converting to another
color space.

Also, the matrix coefficients may be multiplied (left
shifted) by 2 or 4, and the MI-M8 (2x) or M2-M9
(4x) outputs selected, rather than the MO-M7 outputs.
This may reduce rounding errors, especially when
multiple devices are used.

Typical Applications

Color Correction of Cameras
The color response of a video camera is never exactly
that specified by the standards, which require negative
responses to certain portions of the light spectrum. In
practice, this is achieved by matrixing the three color
signals of the form:
Rcorrect = aRcam + bG cam + cBcam

Figures 5 and 6 show typical applications of the
B t281 in an image caprure and display environment.
Note the Bt281 may also be placed between the frame
buffer memory and MPU. Thus, the MPU may operate
in a single color space, while many color spaces may
reside in the frame buffer. The CLOCK of the Bt281
would typically be connected to the video system
clock.

ESD and Latchup Considerations
Correct ESD-sensitive handling procedures are
required to prevent device damage, which can produce
symptoms of catastrophic failure or erratic device
behavior with somewhat "leaky" inputs.
All logic inputs should be held low until power to the
device has settled to the specified tolerance.

where the constants a, e, and i are positive values near
unity and the other constants are small in comparison
with unity and usually negative.
Since it is usually desired to keep the color balance of
the camera constant:

Latchup can be prevented by assuring that all VCC
pins are at the same potential, and that the VCC
supply voltage is applied before the signal pin
voltages. The correct power-up sequence assures that
any signal pin voltage will never exceed the power
supply voltage by more than +0.5 V.

a+b+c=1
d+e+f= I
g+h+i= I

Rather than implementing the color correction using
differential amplifiers, the Bt281 makes it feasible to
use a digital architecture involving matrix
multiplication.

IMAGING PRODUCTS

3 - 115

..

Bt2S1
Application Information (continued)

)

(

~t;

I
<1'1'

'"

~~~
~~

8

~I
t
......

00

p
j:Q

-I.-

i



J!
.....

00

~
~

-'--

;$t

:.=

-

~

Figure 6.

~~

Typical Application.

IMAGING PRODUCTS

3 • 117

Bt281
Recommended Operating Conditions
Parameter
Power Supply
Ambient Operating Temperature

Symbol

Min

Typ

Max

Units

vee

4.5
0

5.00

TA

5.5
+70

Volts
·C

Symbol

Min

Typ

Max

Units

7.0

Volts

GND-0.5

VCC+0.5

Volts

-55
-65

+125
+150
+150

·C
·C
·C

220

·C

Absolute Maximum Ratings
Parameter
VCC (measured to GND)
Voltage on Any Signal Pin*
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Vapor Phase Soldering
(1 minute)

TA
TS
TJ
TVSOL

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
* This device employs high impedance CMOS devices on all signal pins. It should be handled as an
ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V
can induce destructive latchup.

3 - 118

SECTION 3

Bt281
DC Characteristics
Parameter
Digital Inputs
Input High Voltage
Input Low Voltage
Input High Current (Vin = 2.4 V)
Input Low Current (Vin = 0.4 V)
Input Capacitance
(f= 1 MHz, Vin = 2.4 V)
Digital Outputs (DO-D7)
Output High Voltage
(IOH = -400 ~A)
Output Low Voltage
(IOL = 6.4 rnA)
3-state Current
Output Capacitance
QAx, QBx, QCx Digital Outputs
Output High Voltage
(IOH = -400 ~A)
Output Low Voltage
(IOL = 6.4 rnA)
3-state Current
Output Capacitance
Other Digital Outputs
Output High Voltage
(IOH = -400 ~A)
Output Low Voltage
(IOL = 6.4 rnA)
Output Capacitance

Symbol

Min

vrn
vn..

2.0
GND-0.5

Typ

IIH

ilL
C1N

VOH

Volts
Volts

pF

0.4

Volts

10

J.IA
pF

10

Volts

2.4

VCL
IOZ

cour

J.IA
J.IA

Volts

IOZ

0.4

Volts

10

J.IA
pF

10

Volts

2.4
0.4

VCL

cour

VCC +0.5
0.8
1
-1

2.4

cour

VOH

Units

7

VCL

VOH

Max

10

Volts
pF

Test conditions (unless otherwise specified): "Recommended Operating Conditions." Typical values are based
on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.

IMAGING PRODUCTS

3 • 119

..

Bt281
AC Characteristics
Parameter
Clock Rate

Symbol

Min

Typ

Fmax

Max

Units

36

MHz

AO, AI, CS* Setup Time
AO, AI, CS* Hold Time

1
2

10
10

ns
ns

RD*, WR*LowTime
RD*, WR * High Time
RD* Asserted to Data Bus Driven
RD* Asserted to Data Valid
RD* Negated to Data Bus 3-Stated

3
4
5
6
7

70
15
1

ns
ns
ns
ns
ns

Write Data Setup Time
Write Data Hold Time

8
9

10
10

ns
ns

Pixel and Control Setup Time
DAx, DBx, DCx, INO, IN1, CFLAG
Pixel and Control Hold Time
DAx, DBx, DCx, INO, IN1, CFLAG

10
5

ns

4

ns

Clock Cycle Time
Clock Pulse Width High
Clock Pulse Width Low

12
13
14

27.7
10
10

ns
ns
ns

Pipeline Delay
Output Delay
Three-State Disable Time
Three-State Enable Time

15
16
17

Ibd

VCC Supply Current*

70
20

11

14

ICC

14

14
16
15
15

Clocks
ns
ns
ns

220

tbd

rnA

Test conditions (unless otherwise specified): "Recommended Operating Conditions" TTL input values are 0-3
V, with input rise/fall times:!> 4 ns, measured between the 10% and 90% points. Timing reference points at 50%
for inputs and outputs. QAx, QBx, QCx, aUTO, OUT1 output load:!> 75 pF, DO-D7 output load:!> 75 pF. Typical
values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.
*At Fmax. ICC (typ) at VCC = 5.0 V. ICC (max) at VCC (max).

3 • 120

SECTION 3

Bt2S1
Timing Waveforms

I

AO, AI, CS·

----.,

2

VALID

6

I

*

f---L-L,

DO- D7 (READ)

t

DO - D7 (WRITE)

Figure 7.

4

DATA OlIT (RD' = 0)

......

..

3

J-7

./

DATA IN (WR'=0)
8

-

I--

9

MPU Read/Write Timing.

CLOCK

DAO-DA7, DBO-DB7,
DCO - DC7, INO, INI

QAO-QA7, QBO-QB7,
QCO-QC7

OB'

,LIS
OlITO, OlITI

_ _ _.JXI..._ _ _ _--'XI..._ _ _ _--IX,..-DA-T-A-(N---14-)-"

~ATA(N -13)

Figure 8. Video InputlOutput Timing
(Bypass or Noninterpolated & Nonmultiplexed 24-bit 110).
IMAGING PRODUCTS

3 - 121

Bt281
Timing Waveforms (continued)

CLOCK

O'LAG

DBO-DB7

DB(N)

DB(N+I)

DCO-DC7

DC(N)

DA(N)

10

QAO - QA7, QBO - QB7,
QCO-QC7

11

DATA(N -14)

Figure 9. Video Input/Output Timing
(Multiplexed & Interpolated 16·bit Input, 24·bit Output).

CLOCK

DAO-DA7, DBO-DB7,

DATA(N)

DCO-DC7

10

DATA(N+I)

11

O'LAG

QBO-QB7

QB(N-I4)

QB (N -13)

QCO-QC7

QC(N-I4)

QA(N-I4)

Figure 10.

Video Input/Output Timing

(24. bit Input, Multiplexed & Decimated 16-bit Output).

3 • 122

SECTION 3

Bt281
Timing Waveforms (continued)

Cl'LAO

DB(N)

DBO-DB7

DAO-DA7,

..

DB (N + I)

DA 00, OC (N)

OCO-0C7

10

QAO-QA7, QBO-QB7,
QCO-QC7

11

DATA(N-14)

DATA(N-ll)

IS

Figure 11. Video Input/Output Timing
(Nonmultiplexed & Interpolated 24·bit Input, 24· bit Output).

Ordering Information
Ambient
Temperature
Range

Model Number

Package

Bt281KPl

84-pin Plastic
I-Lead

00 to +70 0 C

IMAGING PRODUCTS

3 • 123

Bt281
Revision History
Datasheet
Revision

Change from Previous Revision

E

Pipeline delay changed to 14 clock cycles, pixel setup time changed to 5 ns. Even rounding added
after interpolation filters. Command bit CRIO modified to optionally three-state outputs. Table
2 added.

F

Replaced analog sign with offset binary notation. Note added to CRO! and CROO command bits
that they may be set while programming the command registers. Note added about 2's
complement conversion and row-swapping between some matrices to clarify matrix
transformations. YIQ to RGB matrices adjusted. Added note to DC/AC sections regarding typical
values.

3 • 124

SECTION 3

Preliminary Information

Bt291

This document contains information on a new product. Parametric information, although
not fully characterized, is the result of testing initial devices.

Distinguishing Features

Applications

NTSC and CCIR Compatible
• Three 256 x 8 RGB Input RAMs
Selectable RGB to YCrCb Conversion
16-Bit Multiplexed YCrCb I/O Bus
• 8-bit Ancillary Data Input Bus
Selectable Cr/Cb Decimation Filters
• Low-Pass Y Filter (Optional)
• Video Timing Insertion
• Dynamic Range Control
• TTL Compatible Inputs and Outputs
• +5 V Monolithic CMOS
• 100-pin PLCC Package
• Typical Power Dissipation: 1.1 W

•
•
•
•
•

CCIR601
SMPTE RPI25
EBU3246-E
Image Processing and Capture
RGB to YCrCb Conversion

Product Description
Related Products
The Bt291 performs real-time RGB-to-YCrCb
conversion. Twenty-four bits of RGB information
(8 bits each) are input and converted to YCrCb
color information (8 bits each).
YCrCb data
(4:4:4 format) may also be input via the RGB
inputs.

• Bt294, Bt296

Functional Block Diagram

SRD*

SWR'

Y(0·7)

27 MHz VideoNet™
RGB-to-YCrCb
8-bit Encoder for
4:2:2 Video Applications

The Y data is optionally low-pass filtered. The Cr
and Cb data are decimated to 1/2 the Y data rate and
multiplexed together. The Y and Cr/Cb data are
further multiplexed, video timing information
inserted, and output onto 00--07.

CRJCB(O·7)

A 16-bit YCrCb I/O bus is available for active
video data I/O. Ancillary data may also be input
via AO--A7 for insertion of digital audio, teletext,
etc.

RO-R7

no·07
GO·G7

Three 256 x 8 lookup RAMs are available on the
RGB inputs, to support gamma correction, etc.

BO·B7

OE'
H,

v,

F

MO.RS!

RD'"

wa'"

RESET'

Brooktree Corporation
9950 Bames Canyon Rd.
San Diego, CA 92121
(619) 452-7580, (800) VIDEO IC
TLX: 383596, FAX: (619) 452-1249
L291001 Rev. E

CD FLAG

CLOCK

CLOCK 12

3 • 125

The output enable (OE*) three-states the 00-07
outputs asynchronously to the clocks.
An internal command register (accessible via
AO-A 7) enables forced blanking levels of Y and
erICh data, and automatic line count
transmission. RD* and WR * are used to control
accessing the command register.

Broddree®

t:::;

IN

a

-

....
N

!.

Cl\

~

Q.

c=

f"t-

N
\0
1-1-

t::=

0'
f")

ill;"

SRD'"

I:Il

t"l

..,...

YO - Y7

CR/CB (0 -7)

AO-A?

t:::;
;.

ANC'

! !

(")

~
IN

SWR*

(JQ

Cl

=

""l

~.

Il::

;;:

....

RO-R?

7

<

RAM

...t:l
S

~

GO-G7

7

<
RAM

~

11

~

•

I:I:l

C5"

...

BO-87

>L.

l'o'"

256 X8

RGB

I .

I

RANGE
SBLBCf

_.1.-_-+--1

1-1

TO

Y/CRICB
ROUNDING
CONfROL

W

MllX I Y/CRICB

MUX

RANGE
SBLBCf

I CR/CB

MllX

DO-D7

RANGB
SBLBCf

t:l

JJ'
i:l

?I

3

H.V.F

7

L.

t f
RD-

WR..

t
RESET"

I

Bt291
Circuit Description
Input Lookup Table RAMs
RO-R7, 00-07, and BO-B7 are latched on the rising
edge of CLOCK while CLOCK/2 is a logical one.
RO-R7 address the red 256 x 8 lookup table RAM,
00-07 address the green 256 x 8 lookup table RAM,
and BO-B7 address the blue 256 x 8 lookup RAM. The
outputs of the lookup table RAMs drive the ROB to
Y/Cr/Cb color conversion circuitry. (See Figure 1.)
Note that gamma-corrected ROB data must be used for
conversion to the YCrCb color space. The three input
lookup table RAMs may be used to provide gamma
correction on the RO-R7, 00-07, and BO-B7 inputs
in the event that they contain linear (rather than
gamma-corrected) ROB data.
The lookup table RAMs are not dual-ported, so MPU
accesses have priority over pixel accessing. During
MPU access to the color palette RAMs, the lookup
table RAM outputs are undefined and invalid.
The lookup table RAMs are not initialized following a
reset condition or power-up sequence.

RGB to YCrCb Matrix
The output of the lookup table RAMs drives the ROB
to YCrCb matrix. The selected ROB to YCrCb
conversion is determined by the command register and
is either:
analog coefficient matrix:
Y = 0.299R + 0.5870 + 0.114B
Cr

= 0.500R -

235 (or 1-254), in addition to providing gamma
correction.
ROM lookup tables are used to perform the
multiplications, and for the analog matrix, 5 bits of
fractional data are maintained. The final result is
rounded to 8 bits as specified by command registec1.
Note the digital matrix maintains full precision (8
bits of fractional data).
The output range of matrix is selected by the CR04
command bit:
(0) Y

= 16 to 235;

-

Cr and Cb = 16 to 240

or

(1) Y = 1 to 254; Cr and Cb = 1 to 254

If the CR04 command bit is a logical one, then if the
Y, Cr, or Cb output value is zero, it is made 1; if the
Y, Cr, or Cb output value is 255, it is made 254.

If the CR04 command bit is a logical zero, then if the
Y output value is 0-15, it is made 16; if the Youtput
value is 236-255, it is made 235. If the Cr or Cb
output value is 0-15, it is made 16; if the Cr or Cb
output value is 241-255, it is made 240.
This YCrCb range limiting also applies when
inputting YCrCb data via the ROB inputs, bypassing
the ROB to YCrCb matrix. Note that the lookup table
RAMs are still used when inputting YCrCb data via
the ROB inputs. The YCrCb range limiting occurs
after the lookup table RAMs.

0.4190 - 0.081B + 128

Cb = -O.169R - 0.3310 + 0.500B + 128

or digital coefficient matrix:

To ease system timing requirements, the ROB,
YCrCb, CbFLAO, H, V, and F inputs have the same
relative input timing.

Y Low-Pass Filter

Cr = (131/256)R - (110/256)0 - (21/256)B + 128

The Y channel has a digital low-pass filter after the
ROB to YCrCb matrix. Command bit CROO specifies
whether or not to bypass the low-pass filter.

Cb = -(44/256)R - (87/256)0 + (13l/256)B + 128

CrlCh Filters and Multiplexer

Y = (77/256)R + (150/256)0 + (29/256)B

The analog coefficient matrix can handle ROB data
ranges of 1-254 or 16-235. The digital coefficient
matrix can only handle ROB data ranges of 16-235.
If the ROB data has a range of 0 to 255 (such as data in
a graphics frame buffer), the lookup table RAMs may
also be used to compress the ROB data range to 16 to

Digital filters low-pass and subs ample the Cr and Cb
data, reducing the sampling rate of the Cr and Cb data
to 1/2 the Y rate, generating 4:2:2 data. The
decimated Cr and Cb data is multiplexed together by
the Cr/Cb multiplexer. The multiplexer is controlled
by the CbFLAO signal.
CbFLAO is latched on the rising edge of CLOCK while
CLOCK/2 is a logical one.

IMAGING PRODUCTS

3 - 127

Bt291
Circuit Description (continued)
YCrCb Multiplexer
The YCrCb multiplexer multiplexes the Y and
multiplexed CrlCb video data into an 8-bit data
stream. The timing of the multiplexer is controlled by
the internal video timing circuitry.

Timing Insertion
The B t291 inputs horizontal blanking (H), vertical
blanking (V), and even/odd frame (F) timing
information. H, V, and F are latched on the rising
edge of CLOCK while CLOCK/2 is a logical one and
pipelined to maintain synchronization with the RGB
data inputs. All changes in state of the V and F inputs
must occur with a change of state in H. (Refer to
Figures 2-7.)

EA V and SA V Sequences
A zero-to-one transition on the H input triggers an
EAV (end of active video) sequence that is output onto
DO-D7, overriding YCrCb color data (refer to Figure
9). A one-to-zero transition on the H input triggers a
SAY (start of active video) sequence that is output
onto DO-07, overriding any Ancillary data (refer to
Figure 10. The pipeline delay of the H input is
internally adjusted relative to the RGB inputs so that
the SA V and EA V sequences start at the proper
location.
The EAV and SAV output sequences are as follows:
$FF $00 $00 $xx

$FF is output with the start of horizontal blanking
during the EAV sequence. $xx is output with the end
of horizontal blanking during the SAV sequence.
$xx is defined as follows:
D7 = logical one
D6 = F input (F = 1 for field 2; F = 0 for field 1)
05 = V input (V = 1 during vertical blanking)
D4=H (H=O atSAV, H = 1 atEAV)
D3-DO = protection bits

The protection bits are derived from V, H, and F as
follows:

F=D6

V=D5

H=D4

D3-DO

0
0
0
0

0
0
1
1

0
1
0
1

0000
1101
1011
0110

1
1
1
1

0
0
1
1

0
1
0
1

0111
1010
1100
0001

DI-D3 are protection bits (Hamming code 6:3) while
DO is an even parity bit for DI-D6.

Line Count Ancillary Sequence
If the line count ANC bit in the command register is

set, the Bt291 will generate an Ancillary (ANC)
sequence indicating the line number of the scan line
about to be sent. This occurs during the six words
preceding the SA V sequence. The Line Count ANC
output sequence is as follows:
$00 $FF $FF IT MM LL
TT is the automatic Line Count ANC identification
code, and is specified by the Line Count register.

ByteTT
D7 = Line Count register bit A7
D6 = Line Count register bit A6
05 = Line Count register bit A5
D4 = Line Count register bit A4
03 = Line Count register bit A3
02 = Line Count register bit A2
Dl = Line Count register bit Al
DO = odd parity bit

The Bt291 generates an odd parity bit for the Line
Count register contents automatically.

3 • 128

SECTION 3

Bt291
Circuit Description (continued)
The MM and LL data words are defmed as:
ByteMM

ByteLL

07=0
D6=Lll
05 =L10
D4=L9
03=L8
D2=L7
D1=L6
DO = odd parity bit

07=0
06=L5
05=1A
D4=L3
D3=L2
D2=L1
D1=LO
00 = odd parity bit

An internal 12-bit vertical counter (LO is the least
significant bit) is used to determine the line number.
The H, V, and F inputs are used to control the vertical
counter. Command bit CR10 specifies whether line
counting is to conform to SMPTE/NTSC or EBU/CClR
standards.

If CR10 is a logical zero (SMPTE/NTSC compatible),
the vertical counter is reset to $001 when the V input
makes a transition from a logical zero to a logical one
while the F input is a logical one. The F input must
change state only at the beginning of the vertical

sync interval, and have the same timing as the H
input. The V input must also have the same timing as
the H input (i.e., all changes in state of the V and F
inputs must occur with a change of state in H). Field 1
will have 262 lines and field 2 will have 263 lines
(assuming a 525-line interlaced system).
If CRI0 is a logical one (EBU/CCIR compatible), the
vertical counter is reset to $001 when the F input
makes a transition from a logical one to a logical
zero. The F input must change state only at the
beginning of the vertical sync interval, and have the
same timing as the H input. The V input must also
have the same timing as the H input (i.e. all changes
in state of the V and F inputs must occur with a change
of state in H). Field 1 will have 312 lines and field 2
will have 313 lines (assuming a 625-line interlaced
system).
The vertical counter increments when the H input
makes a transition from a logical zero to a logical
one.
Note that there are no Ancillary data words associated
with the line count ANC sequence. If the automatic
line count ANC is enabled, the ANC* output will go
high six clock cycles earlier than indicated in Figure
10.

525-Line

Effective sampling frequency·
Luminance (Y)
Color difference (Cr, Cb)
Luminance samples (Y) per total line
Color difference samples per total line (Cr, Cb)

60 Field per Sec.

625-Line
50 Field per Sec.

13.5 MHz
6.75 MHz

13.5 MHz
6.75 MHz

858
429

864
432

720
360

720
360

32 words
244 words
276 words

24 words
264 words
288 words

Number of samples per digital active line
Y

Cr, Cb
Analog to digital horizontal timing relationship
start of digital blanking to start of analog sync
start of analog sync to end of digital blanking
digital blanking interval

·with CLOCK = 27 MHz. Sampling structure is orthogonal, line, field, and picture repetitive Cr
and Cb samples co-sited with odd (1st, 3rd, 5th, etc.) Y samples in each line.

Table 1.

Typical Operational Parameters.

IMAGING PRODUCTS

3 - 129

Bt291
Circuit Description (continued)

WORD 31

LOCATION

SO'iI>SYNC
lEVEL
DIGITAL
BLANKING

DIGITAL ACTIVE LINE

Z/6WORDS

1440 WORDS

(O·Z/S)

(Z/6 -1715)

TOTAL LINE
1716 WORDS
(0-1715)

Figure 2.

525-Line, 60 Field/Sec. Horizontal Sync Relationship.

L

J
START OF DIGITAL LINE

EAVCODE

H CONTROL SIGNAL (DELAYED)

START OF DIGITAL ACTIVE LINE

BLANKING

SAVCODI!

CQ.SITED

NEXT LINE

CO·SITED
DIGITAL
VIDEO
STRI!AM

1716

Figure 3.

3 - 130

525-Line, 60 Field/Sec. Digital Horizontal Blanking.

SECTION 3

BnxKtree~

Bt291

Circuit Description (continued)
The YCrCb output range is selected by the CR04
command bit:

YCrCb I/O Bus
A 16-bit bidirectional multiplexed YCrCb bus is
provided for reading and writing active video data. The
SRO* and SWR* inputs are used to synchronously
read and write YCrCb data. SRO* and SWR* must be
synchronous to CLOCK/2. (See Figure 8.)

(0) Y = 16 to 235; Cr and Cb = 16 to 240
or
(1) Y = 1 to 254; Cr and Cb = 1 to 254

Reading YCrCb Data
While SRO* is a logical zero, YCrCb information
from the ROB to YCrCb matrix is output onto Y (0-7)
and Cr/Cb (0-7) following the rising edge of CLOCK
while CLOCK/2 is a logical one.

H the CR04 command bit is a logical one, then if the
y, Cr, or Cb output value is zero, it is made 1; if the
Y, Cr, or Cb output value is 255, it is made 254.
If the CR04 command bit is a logical zero, then if the

Y output value is 0-15, it is made 16; if the Youtput
value is 236-255, it is made 235. If the Cr or Cb
output value is 0-15, it is made 16; if the Cr or Cb
output value is 241-255, it is made 240.

LINB 1 (V= 1)

LINB4

BLANKING

P1BLD1

LINB
NUMBER

P

1·3
4-9
10-263
2114-265
266-Z1l
Z73-52.5

1
0
0
0
1
1

V

H

H

(BAV)

(SAY)

1
1
1
1
1
1

0
0
0
0
0
0

(F-O)
ODD

LlNB266

1
1
0
1
1
0

LINB3

H.1
BAV

H-O
SAV

Figure 4.

525-Line, 60 Field/Sec. Vertical Timing.

IMAGING PRODUCTS

3 - 131

Bt291
Circuit Description (continued)

WORD 23
LOCATION

SO'I>SYNC
LRVBL

DIGrrAL
BLANKING

DIGrrAL ACI1VIl LINE

288 WORDS

1440 WORDS
(288 -1727)

(0- 287)

TOTAL LINE
1728 WORDS
(0-17Z7)

Figure 5.

625-Line, 50 Field/Sec. Horizontal Sync Relationship.

L

J
STAR1'OPDIGITALLINE

BAVCODB

H CON1ROLSIGNAL (DELAYED)

START OF DIGrrAL ACI1VIl LINE

BLANKING

SAVCODB

CO-SITBD

NBXTLINE

CO-SITIlD
DIGITAL

VIDOO
S'I1U!AM

1728

Figure 6.

3 • 132

625-Line, 50 Field/Sec. Digital Horizontal Blanking.

SECTION 3

Bt291
Circuit Description (continued)

I

525/60 systems

122T

OH
leading edge of line syncs,
half-amplitude reference

I

625/50 systems

132T

nOT

16T

digital
active line
period

Next line

OH
nOT

I

12T

T = one luminance sampling clock (74 ns nominal).

Table 2.

LmEl

Digital-Analog Timing Relationship.

,-,---~-------------------,

LINE I(V=I)

BLANKING

.

FIELD I

(F=O)
ODD

:'~ELDl··

LINE 23 (V=O)

LINE

P

V

NUMBER

.. ACnvtY1Dio::,·,
LINE 311 (V = I)

LmE313
LINE 336 (V = 0)

1-22
23·310
311·312
313 - 335
336 - 623
624 -625

0
0
0
I
I
I

I
0
I
I
0
I

H

H

(EAV)

(SAV)

I

0
0
0
0
0
0

I
I
I
I
I

FIELD 2

(F=I)
EVEN

LINE 625

BLANKING
-L--+__+-__________________
---'

LINE 624 (V = I)
LINE 625 (V = I)

H=I
EAV

H=O
SAY

Figure 7.

625-Line, 50 Field/Sec. Vertical Timing.

IMAGING PRODUCTS

3 - 133

Bt291
Circuit Description (continued)
Ifreading YCrCb data during the blanking intervals, Y
will be either 1 (CR04 = logical one) or 16 (CR04 =
logical zero); CrCb data will be 128.

The CbFLAG input is used to specify whether Cr
(CbFLAG = 0) or Cb (CbFLAG = 1) data is being
latched via the CrCb bus.

Note that Y data will be 16 if command register bit
CR06 is a logical one (regardless of the value of
CR04) and CrCb data will be 128 if command register
bit CR07 is a logical one.

Inputting Ancillary Data-Mode 0

If CbFLAO is a logical zero (and CLOCK/2 = I), Cb
data is output onto the CrCb bus during the next read
cycle; if CbFLAO is a logical one (and CLOCK/2 = I),
Cr data is output during the next read cycle. This
timing enables the CbFLAG status to match the data
present on the CrCb (0-7) outputs. CbFLAO is latched
on the rising edge of CLOCK while CLOCK/2 is a
logical one.

While SRO* is a logical one, the YCrCb bus is
three-stated. Note: SRO* must be synchronized to
CLOCK externally for proper operation.
Writing YCrCb Data
While SWR * is a logical zero, YCrCb information
(and CbFLAO) are latched on the rising edge of
CLOCK while CLOCK/2 is a logical one (the ROB
inputs are ignored). This YCrCb information is used
to generate the 00-07 output data, rather than the
ROB inputs.
The YCrCb input range is selected by the CR04
command bit:
(0) Y = 16 to 235; Cr and Cb = 16 to 240
or
(1) Y= 1 to 254; CrandCb= 1 to 254

If the CR04 command bit is a logical one, then if the
Y, Cr, or Cb input value is zero, it is made 1; if the Y,
Cr, or Cb input value is 255, it is made 254.
If the CR04 command bit is a logical zero, then if the
Y input value is 0-15, it is made 16; if the Y input
value is 236-255, it is made 235. If the Cr or Cb
input value is 0-15, it is made 16; if the Cr or Cb
input value is 241-255, it is made 240.

Note that if command register bit CR06 is a logical
one, the Y data will be made 16. CrCb data will be
made 128 if command register bit CR07 is a logical
one.

3 - 134

SECTION 3

The AI-A7 bus, along with the ANC* output and
SAWR* input, are used to input Ancillary data, such as
digital audio, teletext, etc. The Bt291 ensures that the
ANC and its associated data block will not occupy the
intervals reserved for EAV, SAV, or active video.
ANC* is a logical zero for CLOCK cycles that
Ancillary data may be input into the Bt291 during
horizontal blanking intervals (except when EAV,
SA V, or automatic Line Count ANCs are being
generated) and active video time during vertical
blanking intervals. ANC* is output following the
rising edge of CLOCK and its timing is relative to the
AI-A7 inputs.
If both SAWR* and ANC* are a logical zero during the
rising edge of CLOCK, the AI-A7 input data is
accepted as Ancillary data on the rising edge of
CLOCK. If ANC. or SAWR. are a logical one,
AI-A7 are ignored (except while accessing the
command register).

The Ancillary sequence input via AI-A7 and output
onto 00-07 is:
$00 $FF $FF 1T MM lL xx xx...
where the AI-A7 inputs provide the TT, MM, LL, and
$xx data. TT is the data identification code, MM and
LL specify the Ancillary data word count, and xx are
Ancillary data words.
The Bt291 automatically generates the three word
preamble ($00, $FF, $FF). The preamble is generated
after a high to low transition of SAWR* while ANC·
is a logical zero.
Note that if more than one Ancillary sequence is to be
transmitted during a digital blanking interval, the
SAWR* input must be a logical one for at least three
CLOCK cycles to allow the generation of the three
word preamble ($00, $FF, $FF).
Ancillary data identification codes (TT) are
represented by a 7-bit word, input via AI-A7. The AO
input is ignored, and the Bt291 internally generates
an odd parity bit for the 00 data. This prevents the
data identification codes from generating the $00 and
$FF values reserved for timing reference purposes.

Q
.,
t')

...50
'='

I'D

.,
C"I!I
t')

...

06°
0°

CLOCK/2

~
oQ.

RGBINPIJTS

..

!lO
~

c:.

CBPLAG

YO • Y7 •

~

II>-

~
~

"'CI
~

0
0

c:::
n

CR/CB (0·7)·

0=
0=

OQ

~

...

YO·Y7·1NPIlT

::.
~

~

-.::
~

I

; I

r-

=
...:r=

u

,-..
t')

=

SWR"

~

...3:
z...

N+l

SRD"

~

s:::

I

0

I::

S!:
~
......

N

I

I'D

LJ

l

~I
Y(N)

II

r------~III-------1

I

Y(N)

I

Y(N+l)

I

CB(N)

I
I

Y(N+l)

CR(N)

I

Y(N+2)

I

Y(N+3) I

1lIRJlIl.SfATB

ICB(N+2) ICR(N+2) I

1lIRJlIl.SfATB

Q.
'-'

11--1_ _ _ _ _ _ _ _ _ _ _ _ __

CR!CB (0·7)·1NPIlT
a.GCK

C)

~

c:.
~

I~

DO· 'l7

1

~ 1 ~ I(N~1)1(~2)I(N!2)I(N~2)I(N!3)1

20 CLOCK /2 CYCLIlS

~
C'IJ

t:=

1M

~

I-'

\C

~

~

"""'"

I

Bt291
Circuit Description (continued)

1

1

IIa!=:
~i

eo!

~i

............1.....................

I!
I

;
=:

Figure 9.

3· 136

SECTION 3

Ii
8

EA V Sequence and Writing Ancillary Data.

Bt291
Circuit Description (continued)

>~
ei~
>~

fJ~

g
§

.
8

Ii

a

I
E

t
Ii
§

......

;
iii

B

~

I!o

~

.~
.........................

I..

~

I!o

i§
!i!

~

...... ...... ..............

~

~
"~

~

~

iil

~

~

Q

8

Figure 10.

SA V Sequence.

IMAGING PRODUCTS

3 - 137

Bt291
Circuit Description (continued)
Ancillary sequences can occur multiple times per scan
line if different blocks of data are transmitted.

ByteTI

SAWR* and AI-A7 are latched on the rising edge of
CLOCK.
When not transmitting Ancillary
information (ANC* = logical zero, SAWR* = logical
one), a value of 128 is transmitted.

D7=A7
D6=A6

D5=AS
D4=A4
D3=A3
D2=A2
D1=AI
DO = odd parity bit (AO = x)

Inputting Ancillary Data-Mode I

The Ancillary data word count is specified as a 12-bit
binary value, with a range of I to 1440. Two 6-bit
values (MM) and (LL) are written, the most significant
6 bits (MM) fl1"st.
The Ancillary data word count is represented as two
6-bit words, input via AI-A6. The AO and A7 inputs
are ignored. The Bt291 internally generates an odd
parity bit for the DO data and internally sets the D7 bit
to a logical zero. This prevents the data from
generating the $00 and $FF values reserved for timing
reference purposes. The most significant 6 bits are
transmitted first
ByteMM

ByteLL

D7 =0 (A7 =x)
D6=M5(A6)

D5=M4(AS)
D4=M3 (A4)
D3=M2(A3)
D2=MI (A2)
D1=MO(AI)
DO = odd parity bit (AO = x)

D7=0(A7=x)
D6=L5 (A6)
D5=L4(AS)
D4=L3 (A4)
D3=L2(A3)
D2=L1 (A2)
D1 =LO(AI)
DO = odd parity bit (AO = x)

Ancillary data words are represented as one or more
7-bit words, input via AI-A7. The AO input is
ignored, and the Bt291 internally generates an odd
parity bit for the AO data. This prevents the data from
generating the $00 and $FF values reserved for timing
reference purposes.
Byte(s) xx
D7=A7
D6=A6

D5=AS
D4=A4
D3=A3
D2=A2
D1=AI
DO = odd parity bit (AO = x)

3 - 138

SECTION 3

Unlike Mode 0, in this mode the AO-A7 data are
output onto DO-D7 directly. No three word ANC
preamble is generated, no parity information is
generated, and no checking is done to ensure the
reserved words $00 and $FF are not transmitted. It is
the responsibility of external circuitry to properly
generate the Ancillary sequence. There is no change
in the pipeline delay from the Mode 0 operation.
Ancillary sequences can occur multiple times per scan
line if different blocks of data are transmitted.
SAWR * and AO-A7 are latched on the rising edge of
CLOCK.
When not transmitting Ancillary
information (ANC* = logical zero and SAWR* =
logical one), a value of 128 is transmitted.

Ancillary Data Blocks (NTSC)
During horizontal blanking, small blocks of data, up
to 268 words in total length (including the ANC
preamble(s», can be transmitted within a horizontal
blanking interval. If the Line Count ANC is enabled,
262 words are available (including the ANC preamble
(s».
During vertical blanking, large blocks of data, up to
1440 words in total length (including the ANC
preamble(s», may be transmitted in the interval
starting with the end of the SAV and terminating with
the beginning of EAV.
Note that in Ancillary mode I, three less words are
available per horizontal or vertical blanking interval.

Ancillary Data Blocks (CCIR)
During horizontal blanking, small blocks of data, up
to 280 words in total length (including the ANC
preamble(s», can be transmitted within a horizontal
blanking interval. If the Line Count ANC is enabled,
274 words are available (including the ANC preamble
(s».

Bt291
Circuit Description (continued)
During vertical blanking, large blocks of data, up to
1440 words in total length (including the ANC
preamble(s», may be transmitted in the interval
starting with the end of the SA V and terminating with
the beginning of EA V.
Note that in Ancillary mode I, three less words are
available per horizontal or vertical blanking interval.

DO-D7 Outputs
Video data is output onto DO-D7 following the rising
edge of CLOCK. Command bit CRII is logically
gated with the OE* input, and the resulting value is
used to control three-stating the DO-D7 outputs
asynchronously to the clocks as described in the Pin
Descriptions section.

where the three words Cb, Y, Cr refer to co-sited
samples, the following word [V] being an isolated
luminance sample. Note that Y data will be 16 if
command register bit CR06 is a logical one and CrlCb
data will be 128 if command register bit CR07 is a
logical one.
Note that the Bt291 ensures that color data does not
generate $00 or $FF to avoid timing errors in the
received data.
During horizontal and vertical digital blanking
intervals (except for EAV and SAV sequences), the
Bt291 outputs 128 if no Ancillary information is
being transmitted.

The output sequence of YCrCb color data is:
Cb Y Cr [V] ...

RS1, RSO

CR17, CR16

ADDRO-ADDR7

Accessed by MPU

00

xx

$xx

address register

01
01

00
00

$00
$01

red RAM location $00
red RAM location $01

:

:

:

:

01

00

$FF

red RAM location $FF

01
01

01
01
:
01

$00
$01

blue RAM location $00
blue RAM location $01
:
blue RAM location $FF

$00
$01

01

10
10
:
10

10
10
10
10
:
10
11

xx
xx
xx
xx
:
xx
xx

:

01
01
01
:

:

$FF

Table 3.

:

$FF
$00
$01
$02
$03
:

$FF
$xx

green RAM location $00
green RAM location $01
:
green RAM location $FF
command registecO
command register_l
line count ANC register
reserved
:
reserved
reserved

Internal Register Addressing.

IMAGING PRODUCTS

3 - 139

..

Bt291
Circuit Description (continued)
MPU Interface

The address register increments after each MPU read or
write cycle (except when reading or writing to the
address register), and is not initialized. ADDRO is the
least significant hit and corresponds to bit AO.

The Bt291 supports a standard MPU interface (AO-A7,
RD*, WR*, MPU*, RSO, and RSl).

As the MPU shares the Ancillary bus with Ancillary
information, care must be taken that the MPU does
not attempt to access the internal registers and lookup
table RAMs during the digital blanking intervals. The
MPU* output signal may be used to provide
arbitration; while MPU* is a logical zero, the MPU
may access the Bt291 without contention with any
Ancillary data.

The MPU* output indicates when the MPU may access
the Bt291 via the AO-A7 pins. A logical zero
indicates MPU accesses may be done without
contention with Ancillary data timing.
RSO and RS 1 are used to select address register
(logical zero) or RAM location or control register
specified by the address register (logical one), as
shown in Table 3. The 8-bit address register specifies
which control register or RAM location the MPU is
accessing, also seen in Table 3_ The address register
resets to $00 following a read or write cycle to
location $FF. Write cycles to reserved addresses are
ignored, read cycles from reserved addresses return
invalid data.

The rising edge of WR· latches AO-A7 into the
selected register or lookup table RAM location_ While
RD* is a logical zero, the contents of the selected
register or lookup table RAM location are output onto
AO-A7. Only one of the RD*, WR*, and SAWR*
inputs should be asserted at a time to avoid bus
contention.

CClR601

CSYNC·

OIINLOCK

H, V, P

 0.5. If the fractional data is
< 0.5, the number will be rounded down.
(11) specifies to use Dynamic Rounding™, where the
fractional data is compared to a random number, and
the result (1 bit) added to the 8 bits of color data. If
the fractional data = 0, no rounding is done. R, G, and
B each have their own random number generator.
Typically, this mode should be used.

Dynamic Rounding™ is used under license from
Quantel Limited.

CR12

Ancillary input format
(0) modeO
(1) mode 1

CRl1

DO-D7 output disable
(0) enable DO-D7 outputs
(1) disable 00-D7 outputs

This bit specifies the operation of inputting Ancillary
data. Refer to text for details. Typically. mode (0)
should be used.

This bit is logically gated with the OE* input pin, and
the resulting value is used to control three-stating the
DO-D7 outputs.

IMAGING PRODUCTS

3 - 143

..

Bt291
Internal Registers (continued)
Command Register_l (continued)

CRIO

Vertical counter operation
(0) SMPTE/NTSC compatible
(1) EBU/CC1R compatible

This bit specifies whether the vertical counter scan
line numbering for the Line Count ANC function is to
be SMPTE/NTSC (logical zero) or EBU/CCIR (logical
one) compatible.
During SMPTE/NTSC compatibility, scan line number
one is the first scan line during vertical blanking in
digital field 2.
During EBU/CC1R compatibility, scan line number
one is the first scan line during vertical sync in digital
field 1.

Line Count ANC Register
The 8-bit Line Count register may be written to or read by the MPU at any time and is initialized to $00 following a
reset condition. AO is the least significant bit.
This register specifies the Ancillary data 1D value (TT) of the automatic Line Count ANC.
Bit AO is always a logical zero. MPU data written to bit AO is ignored.

3· 144

SECTION 3

Bt291
Pin Descriptions
Pin Name

Description

YD-Y7

Y data inputsloutputs (TIL compatible). Y information is input or output via these pins
depending on the value of SWR* and SRD*. YO is the least significant bit. If inputting Y data,
it is latched on the rising edge of CLOCK while CLOCK/2 is a logical one. If outputting Y data,
it is output following the rising edge of CLOCK while CLOCK/2 is a logical one.

CRlCh (0-7)

Cr/Cb data inputsloutputs (TIL compatible). Multiplexed Cr and Cb information is input or
output via these pins depending on the value of SWR* and SRD*. CrChO is the least significant
bit. If inputting Cr/Cb data, it is latched on the rising edge of CLOCK while CLOCK/2 is a
logical one. If outputting Cr/Cb data, it is output following the rising edge of CLOCK while
CLOCK/2 is a logical one.

SWR*

Synchronous write control input (TIL compatible). A logical zero enables Y/Cr/Cb data to be
input via the YO-Y7 and Cr/Cb (0-7) pins. Both SRD* and SWR* should not be asserted
simultaneously.

SRD*

Synchronous read control input (TIL compatible). A logical zero enables Y/Cr/Cb data to be
output onto the YO-Y7 and Cr/Cb (0-7) pins. Both SRD* and SWR* should not be asserted
simultaneously.

AD-A7

Ancillary data inputs (TIL compatible). While both ANC* and SAWR* are a logical zero,
AI-A7 are latched on the rising edge of CLOCK and output onto DO-D7. MPU data is also input
and output via this bus. AO is the least significant bit.

SAWR*

Ancillary write control input (TIL compatible). If ANC* is a logical zero, a logical zero on
SAWR* will enable AI-A7 data to be latched. SAWR* is latched on the rising edge of CLOCK,
and pipelined to maintain synchronization with the AI-A7 data. This pin should be a logical
one if the Ancillary data transmission capabilities are not used.

ANC*

Ancillary output (TIL compatible). A logical zero indicates Ancillary data may be input via the
AI-A7 pins. ANC* is output following the rising edge of CLOCK.

ChFLAG

CbFLAG control input (TIL compatible). It is latched on the rising edge of CLOCK while
CLOCK/2 is a logical one.

RO-R7

Red inputs (TIL compatible). Red color information is input via these pins. Data is latched on
the rising edge of CLOCK while CLOCK/2 is a logical one. RO is the least significant bit.

GO-G7

Green inputs (TIL compatible). Green color information is input via these pins. Data is latched
on the rising edge of CLOCK while CLOCK/2 is a logical one. GO is the least significant bit.

BO-B7

Blue inputs (TIL compatible). Blue color information is input via these pins. Data is latched
on the rising edge of CLOCK while CLOCK/2 is a logical one. BO is the least significant bit.

DO-D7

Data outputs (TIL compatible). Transmitted data is output onto I?O-D7 following the rising
edge of CLOCK. DO is the least significant bit.

V,H,F

Video timing control inputs (TIL compatible). They are latched on the rising edge of CLOCK
while CLOCK/2 is a logical one.

IMAGING PRODUCTS

3 • 145

..

Bt291
Pin Descriptions (continued)
Pin Name
OE·

Description
Output enable control input (TTL compatible). This input is logically gated with command bit
CRll, and the result controls three-stating the DO-D7 outputs as follows:
CRll

OE·

DO-D7 Outputs

0
0

0

enabled
three-stated
three-stated
three-stated

1
1

1
0
1

RESET*

Reset control input (TTL compatible). RESET· is sampled on the rising edge of CLOCK, and
must be a logical zero for a minimum of three consecutive CLOCK cycles to reset the device.
RESET· must be a logical one for normal operation.

RD*

MPU read control input (TIL compatible). While a logical zero, the contents of the control
register/RAM location are output onto AO-A7 asynchronously to the clocks. If both RD* and
WR* are asserted simultaneously, all signal pins are three-stated (note the device should be reset
after three-stating the signal pins).

WR·

MPU write control input (TIL compatible). The rising edge of WR* latches the AO-A7 inputs
into the control register/RAM location asynchronously to the clocks. If both RD. and WR. are
a asserted simultaneously, all signal pins are three-stated (note the device should be reset after
three-stating the signal pins).

RSO, RSl

Register select control inputs (TIL compatible). These bits specify whether the MPU is
accessing the address register or the control register/RAM location specified by the address
register. See Table 3.

MPU·

MPU access control output (TIL compatible). A logical zero indicates the MPU may access the
internal registers without contention with Ancillary data. MPU* is output following the rising
edge of CLOCK.

CLOCK

27 MHz clock input (TIL compatible). The clock must be present for the MPU to access the
internal control registers.

CLOCK/2

13.5 MHz clock input (TTL compatible).

vee

Power pins. All vee pins must be connected together.

GND

Ground pins. All GND pins must be connected together.

3 - 146

SECTION 3

Bt291
Pin Descriptions (continued)

GND

R1

aND

A2

vee

vee

R3

AI

R4

AD

R3

U/

aND

D6

R6

OND

R7

D5

00

D4

01

D3

aND

D2

vee

vee

02

GND

G3

DI

(l4

DO

OS

CB.7/CB7

G6

CB.6/CB6

G7

GND

BO

c:R5/CBS

BI

CB.4/CB4

aND

CB.3/CB3

vee

vee

B2

GND

B3

CB.2/CB2

IMAGING PRODUCTS

III

3 - 147

Bt291
Application Information
CrlCb Decimation Filters

Y Low-Pass Filter

The Cr/Cb linear phase decimation filters low-pass
and subs ample the Cr and Cb data to generate 4:2:2
YCrCbdata.

Y may be optionally low-pass filtered using a 19-tap
filter whose transfer function is:

If the CR04 command bit is a logical one, then then if
the result is zero, it is made 1; if the result is 255, it
is made 254. If the CR04 command bit is a logical
zero, if the result is 0-15, it is made 16; if the result
is 241-255, it is made 240.

The transfer function of the 13-tap filters is:
H(Z) = 128/256 * ZO
+ (80/25) * (Z-l + Z+I)
+ (-24/256)*(Z-3 + Z+3)
+ (12/256)*(Z-5 + Z+5)
+ (-6/256)*(Z-7 + Z+7)
+ (3/256)*(Z-9 + Z+9)
+ (-1/256)*(Z-1l +Z+I1)

Eighteen-bit precision (including sign and overflow)
is maintained until the final output stage, then
rounded to 8 bits as specified by command regis tee!.
Figure 13 shows the transfer function of the 13-tap Cr
and Cb decimation filters.
The transfer function of the 3-tap filters is:
H(Z) = 128/256*ZO
+ (64/256)*(Z-1 + Z+I)

Twelve-bit precision (including sign and overflow) is
maintained until the final output stage, then rounded
to 8 bits as specified by command register_I.
During blanking periods, the input color data is
undefined, possibly disturbing the computed color
data at the beginning and end of active color data. To
avoid this, if the 13-tap is filter selected, the 3-tap
filter is automatically used at the beginning and end of
the active line unless the 13-tap filter is available
(i.e., the filter pipe is full). Regardless of the filter
selection, the first active pixel per scan line to be
decimated uses only the multiplexer (bypassing the
digital filters).

3 - 148

SECTION 3

H(Z) = 116/128* ZO
+ (l2/128)*(Z-1 +Z+I)
+ (-ll/128)*(Z-2 + Z+2)
+ (l0/128)*(Z-3 + Z+3)
+ (-8/128)*(Z-4 + Z+4)
+ (6/128)*(Z-5 + Z+5)
+ (-5/128)*(Z-6+ Z+6)
+ (3/128)*(Z-7 + Z+7)
+ (-2/128)*(Z-8+ Z+8)
+ (1/128)*(Z-9 + Z+9)
Seventeen-bit precision (including sign and overflow)
is maintained until the final output stage, then
rounded to 8 bits as specified by command registeel.
If the CR04 command bit is a logical one, then if the
result is zero, it is made 1; if the result is 255, it is
made 254. If the CR04 command bit is a logical zero,
then if the result is 0-15, it is made 16; if the result is
236-255, it is made 235. Figure 14 shows the
transfer functions of the 19-tap Y filter.
During blanking periods, the input color data is
undefined, possibly disturbing the computed color
data at the beginning and end of active color data. To
avoid this, the first and last 19 active pixels per scan
line are not processed by the digital filter (bypassing
the digital filter).
The Y data and control signals are pipelined to
maintain synchronization with the Cr/Cb data. There
is no change in the pipeline delay regardless of which
filter (if any) is used.

Bt291
Application Information (continued)

DB

0.05

DB

.---:----:----:-----~_____,

10.-~-~~~-~~~-_____,

..
-10

0.00

-20

-30

-0.05
-40

-so
-0.10
-60

!i

-70
-0.15

-so
-90

-0.20

+---'---.;--~-~-~___I

2
INPUT FREQUENCY (MHZ)

-100

+-'-ir--r'-'-~-il---,--+-,-"4'......;.'""T"----I
o

INPUT FREQUENCY (MHZ)

Figure 13. CrCb I3-Tap Pass-Band and Stop-Band
Low-Pass I Decimation Filter Characteristics.
IMAGING PRODUCTS

3 - 149

Bt291
Application Information (continued)

DB
DB

4

INPUT FREQUENCY (MHZ)

INPUT FREQUENCY (MHZ)

Figure 14. Y 19-Tap Pass-Band and Stop-Band
Low-Pass Filter Characteristics.

DO

Figure 15.

3 - ISO

SECTION 3

Random Number Generator.

Bt291
Application Information (continued)
Random Number Generator

Typical Applications

Figure IS illustrates the random number generator

Figure 16 shows the Bt291 and Bt294 being used with
a 24-bit RGB frame buffer. The Bt291 and Bt294
provide another video I/O port to the
imaging/graphics system.

used when Dynamic Rounding™(used under license
from Quantel Limited) is selected. Following a reset
condition the random number generator is initialized
to $00000.
As each YCrCb value in the analog matrix has 5
fractional data bits, 5 bits of random numbering is
generated for each Y, Cr, and Cb value (random
number bits DO, 04, and 08 correspond to the LSBs of
Y, Cr, and Cb digital matrix fractional data).
Usage

Fractional Oata Bits
(MSB-LSB)

Y matrix (digital)
Y matrix (analog)

07-00
07-03

Cr matrix (digital)
Cb matrix (digital)

011-04
015-08

Cr matrix (analog)
Cb matrix (analog)

011-07
015-011

Y filter

03-00,019-017

CrCb filter (13-tap)
CrCb filter (3-tap)

019-012
019, Dl8

As a single CrCb filter is used in a multiplexed
fashion, a single CrCb random number generator is
used. The 13-tap CrCb filter has 8 bits of fractional
data. Random number bit 012 corresponds to the LSB
of Cr and Cb fractional data.

Figure 17 shows the Bt291 and Bt294 being used with
a 16-bit YCrCb frame buffer. The Bt291 and Bt294
provide another video I/O port to the
imaging/graphics system.

ESD and Latchup Considerations
Correct ESO sensitive handling procedures are required
to prevent device damage which can produce
symptoms of catastrophic failure or erratic device
behavior with somewhat "leaky" inputs.
All logic inputs should be held low until power to the
device has settled to the specified tolerance.
Latchup can be prevented by assuring that all VCC
pins are at the same potential, and that the VCC
supply voltage is applied before the signal pin
voltages. The correct power-up sequence assures that
any signal pin voltage will never exceed the power
supply voltage by more than +0.5 V.

PLCC Sockets
loo-pin PLCC sockets for the Bt291 are available
from:
McKenzie Technology
44370 Old Warm Springs Blvd.
Fremont, CA 94538
Phone: (415) 651-2700
FAX: (415) 651-1020
TLX: 910-240-6355
Part Number: PLCC-lOO-P-T

Random number bits 019 and 018 are used for the
3-tap CrCb filter, which has 2 bits of fractional data.
The 19-tap Y filter has 7 fractional data bits, with the
random number fractional bits shown above.

or
Yamaichi Electric Mfg.Co., LTO.
3-28-7 Nakamagome, Ohta-Ku,
Tokyo 143 Japan
Phone: 03-778-6161
FAX: 03-778-6181
U.S. Representative: (408) 452-0797

IMAGING PRODUCTS

3 • 151

..

t=
-=-=> '*
N

1M

-=

...u.

-=
n'

w

S'

~

~

~

=
0'

I:Il

'"I

l"'.l

(")

::!
~

I

Bt261
GENLOCK

I

a
=

-=

VIDIlO TIMING
AND DRAM

I

S'

CONTROL

1M

~

:] ~

oQ'
Ii:::

~

~

....

?'

ROB

24

Bt253

RGBVIDIlO

AID

COLORSPACl

/

RGB

FRAMR

COLQRSPACl

BUPFBR

7

~
~

24

""

Bt473

~

RAMDAC
~

---o
:=
i'

-=
f')

~

Co

;:;.

:g
Q

Bt294

Bt291

~

YCRCB

RGB

TO

TO

ROB

YCRCB

l ;"
Q

::.
0
1I

-

DIGITAL VIDIlO
DATA

Bt297

8
8

/

BCL
TO

11L

"

""

Bt296
rn.

_.

DIGITAL VIDEO
DATA

TO
BCL

I

>-

-=_. i~

"0

'E.
;:).
~

0

~.~ I

....
.,0-=

VIDEO TIMING

-=
-=
-=

AND DRAM

I

@J

:I~

CON1ROL

O·
t ')

"'l

0

oq'

..

I::

24

~

VIDEO

....

RGB, YIN

Bt2S3
AID

;"-l

-rRGB

16-BIT

Bt291

FRAME

RGBTO

BI1FPER

YCRCB

:r

YCRCB
COLORSPACB

I'D

C.

'-'

~
~

-

/V16

l;'
Q

....

a:
>

c;':l

....
Z

c;':l

."

:=

0
0

~

-...-,

~

l;'

YCRCB
DIGITAL
VIDEO
DATA

Bt297
ECLTO
TTL

8

/
/

Bt294

8

YCl.CB
TO ROB

Bt296

/

TTL TO
ECL

/

Q

c:o

iZ

24/

RGB

/

R

Bt473

~

(")

RAMDAC

,..;j
I:Il

G

B

J

TO
CRT

c=
f"to

(M

N

....

I,C

~

1--&

I

Bt291
Recommended Operating Conditions
Parameter
Power Supply
Ambient Operating Temperature

Symbol

Min

Typ

Max

Units

vee

4.5
0

5.00

TA

5.5
+70

Volts
°C

Symbol

Min

Typ

Max

Units

7.0

Volts

GND-O.5

VCC+0.5

Volts

-55
-65

TJ

+125
+150
+150

°C
°C
°C

TVSOL

220

°C

Absolute Maximum Ratings
Parameter
VCC (measured to GND)
Voltage on Any Signal Pin*
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Vapor Phase Soldering
(1 minute)

TA
'IS

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
* This device employs high impedance CMOS devices on all signal pins. It should be handled as an
ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V
can induce destructive latchup.

3 - 154

SECTION 3

Brocktree®

Bt291

DC Characteristics
Parameter
Digital Inputs
Input High Voltage
Input Low Voltage
Input High Current (Vin =2.4 V)
Input Low Current (Vin =0.4 V)
Input Capacitance
(f = 1 MHz, Vin =2.4 V)
Digital Outputs
Output High Voltage
(IOH =-400 I1A)
Output Low Voltage
(IOL =6.4 rnA)
3-state Current (If Applicable)
Output Capacitance

Symbol

Min

vrn

2.0
GND-O.5

VIL

Typ

IIH
TIL

Max

Units

VCC+0.5
0.8
1
-1

Volts
Volts

J.IA
J.IA
pF

CIN

7
VOH

Volts

2.4

VeL

IOZ
cnUf

0.4

Volts

50

J.IA

20

pF

Test conditions (unless otherwise specified): "Recommended Operating Conditions." Typical values are based
on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.

IMAGING PRODUCTS

3 - ISS

..

Bt291
AC Characteristics
Parameter
Clock Rate

Symbol

Min

Typ

Fmax

Max

Units

27

MHz

MPU Write Data Setup Time
MPU Write Data Hold Time
RSO, RS1 Setup Time
RSO, RS1 Hold Time

1
2
3
4

10
10
10
10

ns
ns
ns
ns

RD*LowTime
WR* Low Time
WR * Cycle Time
RD*, WR * High Time
RD* Asserted to Data Bus Driven
RD* Asserted to Data Valid
RD* Negated to Data Bus 3-Stated

5
6
7
8
9
10
11

1
100
3
30
5

Clock
ns
Clocks
ns
ns
ns
ns

Clock/2 Setup Time
Clock/2 Hold Time

12
13

12
5

ns
ns

ROB (0-7), H, V, P, CbPLAO,
Y/Cr/Cb (0-7)
Setup Time
Hold Time

14
15

10
4

ns
ns

Y/Cr/Cb Output Delay

16

5

A1-A7 Input Data, SAWR *
Setup Time
Hold Time

17
18

10
4

100
25

23

ns
ns

SRD* Asserted to YCrCb Bus Driven
SRD* Negated to YCrCb Bus 3-Stated
MPU*, ANC* Output Delay
DO-D7 Output Delay

19
20

DO-D7
Three-State Disable Time
Three-State Enable Time

21
22

Clock Cycle Time
Clock Pulse Width High
Clock Pulse Width Low

23
24
25

VCC Supply Current*

ICC

ns

5
5

25
25

ns
ns

23
23

ns
ns

25
25

ns
ns

37.04
15
15

ns
ns
ns
220

tbd

rnA

Test conditions (unless otherwise specified): "Recommended Operating Conditions." TTL input values are 0-3
V, with input rise/fall times ~ 4 ns, measured between the 10% and 90% points. Timing reference points at 50%
for inputs and outputs. ANC*, Yx, Crx/Cbx, Dx, MPU* output load ~ 75 pP. Typical values are based on
nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.
*At Fmax.

3 - 156

lee (typ) at vee =5.0 V. lee (max) at vee (max).

SECTION 3

Bt291
Timing Waveforms

RSO, RSI

b:

>--

:d

VALID

I--

I

7

6

~}

RD"', WR'"
8
10

V

AO - A7 (READ)

DATA OlJf (RD' =0)

"

I

I--

/

I--

f

AO - A7 (WRITE)

}-n

-

9

DATA IN(WR' =0)
0----

I

-

r--

2

MPU Read/Write Timing.

23

a..OCK

a..OCK/2
12

13

CBFLAO

14

IS

Y/CR,CB (0 - 7) - INPlJf,

SRD·, SWR·, H, V, F,

ROB OR Y ICR DATA

ROB OR YICB DATA

ROB(O-7)
16

Y/CRICB (0 -7)· OlITPlIT

Y/CB DATA

Y/CR DATA

RGB, YCrCb Timing,

IMAGING PRODUCTS

3 - 157

Bt291
Timing Waveforms (continued)

CLOCK

AI·A7.SAWR"

DO·D7

AI-A 7, DO-D7 Timing.

DO·D7

DE"

Output Enable Timing.

3 • 158

SECTION 3

Bt291
Ordering Information

Ambient
Temperature
Range

Model Number

Package

Bt29lKPI

100-pin Plastic
I-Lead

00 to +70 0 C

-

IMAGING PRODUCTS

3 - 159

Preliminary Information
This document contains information on a new product. The parametric information,
although not fully characterized, is the result of testing initial devices.

Distinguishing Features

Applications

NTSC and CCIR Compatible
• YCrCb to ROB Conversion
16-bit Multiplexed YCrCb 1/0 Bus
• 8-Bit Ancillary Data Output Bus
Selectable Cr/Cb Interpolation Filters
Optional Data Rate Doubling to 27 MHz
• Three 256 x 8 ROB Output RAMs
• Video Timing Recovery
Programmable Color Key Output
TTL Compatible Inputs and Outputs
+5 V Monolithic CMOS
• loo-pin PLCC Package
• Typical Power Dissipation: 900 mW

•
•
•
•
•

CCIR601
SMPTE RP125
EBU3246-E
Image Processing and Capture
YCrCb-to-ROB Conversion

ANC'

CRICB (0. 7)

27 MHz VideoNet™
YCrCb-to-RGB
8-bit Converter for
4:2:2 Video Applications
Product Description

Related Products
The Bt294 performs real-time YCrCb to ROB
conversion. Eight bits of multiplexed YCrCb
information are input and converted to ROB color
information (8 bits each).

• Bt291, Bt297

The incoming DO-D7 data has video timing
information extracted, generating the horizontal
blanking (H), vertical blanking (V), and field (F)
outputs. Y and CrICb data are demultiplexed, and
available on the 16-bit Y and Cr/Cb I/O bus.

Functional Block Diagram
AO·A7

Bt294

Y (0 - 7)

SRD'

SWR'

RESE1"

8

ERROR

8
Y

8

R

RO-R7

00-07
GO·07

The Cr and Cb data are demultiplexed and
interpolated data is generated using one of two
interpolation filters, selectable by the MPU.
Ancillary data is detected and output onto the
AO-A7 pins. ANC* is a logical zero while
outputting Ancillary data.

CLOCK

BO-B1

Three 256 x 8 lookup table RAMs are provided, to
support gamma correction, etc.

Oll*
COLOR KEY

H.V.P

RO'

WR'

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121
(619) 452-7580 • (800) VIDEO IC
TLX: 383 596 ,FAX: (619) 452-1249
L294001 Rev. E

RSO,RSI

MPU·

CEPIAO

CLOCK/2

3 - 161

The output enable (OE*) control three-states the
RO-R7, 00-07, and BO-B7 outputs
asynchronously to clock. YCrCb data (4:4:4
format) may also be output onto the ROB outputs.

-t:::'

eM

fD

....
="

e.

N

fD
Q.

t=
....
N
\C

.&:;I..

t:=

~

t:::'
;.

til

I:"'.l

n

::3

AO-A7

-

R

+
~

+

ei
+

>-

fl

:::+

g

~

>-

e!

~

g
fl

>-

..

R
~

~~
eii
R
>-~

fli

;
....

~

!:I

>-~

eig
>-g
flg

s

8

Figure 2. Reading/Writing Active Video Data
(13.5 MHz RGB Output Rate).
IMAGING PRODUCTS

3 - 165

Bt294
Circuit Description (continued)

!

I

~
!::
~
~
§

I

!

:

~

~

!

..~
~

a

i
i
!

g

§
!::l

01

§

El ~I

§

5l

~

.~

~
i

~

I

~l
=:

=

~ \.Ii

:;ll

:;l

~

~l

>~

iili

iii

~:i

ejg

~

ii

>g

i

Elg

......

.······t·······

~

I
=
l;i

Figure 3.

3 - 166

SECTION 3

:.:

~

~

6

8

~

Ii:
~

~

EA V Sequence and Reading Ancillary Data
(13.5 MHz RGB Output Rate).

Bt294
Circuit Description (continued)

If

1111

~l

9i

!

i
i

!

.....1

eg .....................................

g
i
i

Ei

!
.,~

a

Figure 4. SA V Sequence
(13.5 MHz RGB Output Rate).

IMAGING PRODUCTS

3 • 167

Bt294
Circuit Description (continued)
Reading YCrCb Data
While SRD'" is a logical zero, YCrCb information
from the RDO-D7 inputs is output onto Y (0-7) and
CrCb (0-7) following the rising edge of CLOCK while
CLOCK/2 is a logical one. Cb data is being output
onto the CrCb bus while CbFLAG is a logical one.
The YCrCb output range is selected by the CR07
command bit:
(0) Y = 16 to 235; Cr and Cb = 16 to 240
or
(1) Y= 1 to 254; CrandCb= 1 to 254

If the CR07 command bit is a logical one, then if the
Y, Cr, or Cb output value is zero, it is made I; if the
Y, Cr, or Cb output value is 255, it is made 254.
If the CR07 command bit is a logical zero, then if the
Y output value is 0-15, it is made 16; if the Y output
value is 236-255, it is made 235. If the Cr or Cb
output value is 0-15, it is made 16; if the Cr or Cb
output value is 241-255, it is made 240.
If CbFLAG is a logical one, Cb data is present on the
CrCb bus; if CbFLAG is a logical zero, Cr data is
present. CbFLAG is output following the rising edge
of CLOCK while CLOCK/2 is a logical one.
While SRD* is a logical one, the YCrCb bus is
three-stated. Note: SRD'" must be synchronized to
CLOCK externally for proper operation.

If the CR07 command bit is a logical one, if the Y, Cr,
or Cb input value is zero, it is made 1; if the Y, Cr, or
Cb input value is 255, it is made 254.
If the CR07 command bit is a logical zero, then if the
Y input value is 0-15, it is made 16; if the Y input
value is 236-255, it is made 235. If the Cr or Cb
input value is 0-15, it is made 16; if the Cr or Cb
input value is 241-255, it is made 240.

While CbFLAG is a logical one, Cb data is latched on
the CrCb bus; if CbFLAG is a logical zero, Cr data is
latched. CbFLAG is output following the rising edge
of CLOCK while CLOCK/2 is a logical one.

CrCb Demultiplexer I Filters
The CrCb demultiplexer, using the CbFLAG signal,
separates the 8 bits of multiplexed Cr and Cb data.
As Cr and Cb data are to be co-sited with the odd (first,
third, fifth, etc.) Y samples, digital interpolation
filters provide the even 8 bilS of Cr and Cb data,
converting the 4:2:2 YCrCb data to 4:4:4 YCrCb
data.

YCrCb·to·RGB Matrix
The matrix converts the 24 bits of YCrCb data (8 bits
each) to 24 bits of RGB data (8 bits each), and outputs
the data onto RO-R7, G0-07, and BO-B7.
The YCrCb to RGB conversion is selected by the
command register and is either:
analog coefficient matrix:

Writing YCrCb Data

R = Y + 1.402(Cr - 128)

While SWR'" is a logical zero, YCrCb information is
latched on the rising edge of CLOCK while CLOCK/2
is a logical one. This YCrCb information is used to
generate the RGB output data, rather than the DO-D7
inputs.

G = Y - 0.714(Cr - 128) - 0.344(Cb - 128)
B = Y + 1.772(Cb - 128)

or digital coefficient matrix:
The YCrCb input range is selected by the CR07
command bit:
(0) Y = 16 to 235; Cr and Cb = 16 to 240

R = Y + 1.370(Cr - 128)
G = Y - 0.698(Cr - 128) - 0.336(Cb - 128)
B =Y + 1.730(Cb - 128)

or
(1) Y= 1 to 254; CrandCb= 1 to 254

3 • 168

SECTION 3

Bt294
Circuit Description (continued)
ROM lookup tables are used to perform the
multiplications and 4 bits of fractional data are
maintained. The fmal result is rounded to 8 bits as
specified by command register_I. If the resulting R,
0, or B value is less than zero, it is set to zero. If the
resulting R, 0, or B value is greater than 255, it is set
to 255.
NO!e the digital coefficient matrix operates properly
only when the YCrCb input range is Y = 16 to 235; Cr
and Cb = 16 to 240 (the ROB output range will
typically be 16 to 235). The analog coefficient
matrix can handle the YCrCb input range of Y = 16 to
235; Cr and Cb = 16 to 240 (the ROB output range
will typically be 16 to 235) or YCrCb = 1 to 254 (the
ROB output range will typically be 1 to 254).
The YCrCb to ROB matrix may also be bypassed via
the command register.

Output Lookup Table RAMs
Note that gamma-corrected ROB data is generated by
the YCrCb to ROB matrix. The three output lookup
table RAMs may be used to remove gamma correction
on the RO-R7, 00-07, and BO-B7 outputs in the
event that they are to contain linear (rather than
gamma-(;orrected) ROB data.
AIl the ROB data range from the YCrCb to ROB matrix
is typically 16 to 235 (or 1 to 254), the lookup table
RAMs may also be used to expand the range to 0 to
255.
The lookup table RAMs are not dual-ported, so MPU

accesses have priority over pixel accessing. During
MPU access to the color palette RAMs, the lookup
table RAM outputs are undefmed and invalid.
The lookup table RAMs are not initialized following a
reset condition or power-up sequence.

RS1, RSO

CR03, CR02

ADDRO-ADDR7

Accessed by MPU

00

xx

$xx

address register

01
01

00
00

$00
$01

red RAM location $00
red RAM location $01

:

:

:

:

01

00

$FF

red RAM location $FF

01
01
:
01

01
01

$00
$01

green RAM location $00
green RAM location $01

:

:

:

01

$FF

green RAM location $FF

01
01

10
10

blue RAM location $00
blue RAM location $01
:
blue RAM location $FF
command register_O
command register_l
red color key register
green color key register
blue color key register
red color mask register
green color mask register
blue color mask register
reserved

:

:

01

10

$00
$01
:
$FF

10
10
10
10
10
10
10
10
10
:
10

xx
xx
xx
xx
xx
xx
xx
xx
xx
:
xx
xx

$00
$01
$02
$03
$04
$05
$06
$07
$08
:
$FF
$xx

11

Table 1.

:

reserved
reserved

Internal Register Addressing.

IMAGING PRODUCTS

3 - 169

-

Bt294
Circuit Description (continued)
The ROB (or YCrCb) output rate may optionally be
doubled to 27 MHz via the command register. In this
mode of operation, the ROB outputs are updated every
CLOCK cycle. The doubling of the data rate occurs
after the lookup table RAMs.
Note that ROB data addressing the RAM is $00 during
digital blanking intervals (including EAY and SAY
sequences). When YCrCb data is selected as the output
(CR06 is set to one), the lookup table is bypassed.

Output Enable Control
Command bit CROI is logically gated with the OE*
input, and the resulting value is used to control
three-stating the RO-R7, 00-07, and BO-B7 outputs
asynchronously to the clocks as described in the Pin
Descriptions section.

Color Key Output
The Bt294 generates a COLOR KEY output,
determined by the color key and color mask registers.
For a programmed color, or range of colors, the
COLOR KEY output will be a logical one coincident
with the specified color being output on the ROB
outputs. COLOR KEY is output following the rising
edge of CLOCK.

MPU Inter/ace
The Bt294 supports a standard MPU interface (AO-A7,
RD*, WR*, RSO, and RSl).

3· 170

SECTION 3

The MPU* output indicates when the MPU may access
the Bt294 via the AO-A7 pins. A logical zero
indicates MPU accesses may be done without
contention with Ancillary data timing.
RSO and RS 1 are used to select address register
(logical zero) or RAM location or control register
specified by the address register (logical one), as
shown in Table 1. The 8-bit address register specifies
which control register or RAM location the MPU is
accessing. The address register resets to $00
following a read or write cycle to location $FF. Write
cycles to reserved addresses are ignored, and read
cycles from reserved addresses return invalid data.
The address register increments after each MPU read or
write cycle (except when reading or writing to the
address register), and is not initialized. ADDRO is the
least significant bit and corresponds to bit AO.
As the MPU shares the Ancillary bus with Ancillary
information, care must be taken that the MPU does
not attempt to access the internal registers and lookup
table RAMs during the digital blanking intervals. The
MPU* output signal may be used to provide
arbitration; while MPU* is a logical zero, the MPU
may access the Bt294 without contention with any
Ancillary data.
The rising edge of WR'" latches AO-A7 into the
selected register or lookup table RAM location. While
RD* is a logical zero, the contents of the selected
register or lookup table RAM location are output onto
AO-A7.

Bi:lXKtree

Bt294

GP

Circuit Description (continued)
Typical Application
Figure 5 illustrates a typical application of the Bt294.
The Bt294 converts the incoming DO-D7 data stream
from the Bt297 ECL to TIL receiver, recovering video
timing information, and reformatting the color data
into 16 bits of multiplexed Y and CrICb color data for
loading into the frame buffer. Data from the frame
buffer may also be clocked into the Bt294.

The Bt294 converts the YCrCb data into the ROB
format for driving a true-color VIDEODAC and
RAMDAC, such as a Bt101 or Bt473.
The ROB outputs may also be used to interface to an
ROB frame buffer, rather than driving a VIDEODAC or
RAMDAC, as shown in Figure 6.

..
CCOUOI
VIDEO TIMING
(DNrROLIJ!R

II. V. p

CLOCK
27 MHZ

CDFLAG

BT294
8

8

,"
TO/PROM PRAMI! BIlPI'IlR
(Y/CR/ CD CXlLORSPACB)

-

BT297
Ba./TI'L RBCIlIVER

RD·R7

,"

CR,CIIO. CR/CB7

CJO·G7

,"

DO·D7

BO·B7

,"

8

,"
PROMBa.
BUS

yo.Y7

I
I

8

8

,"

,........1....................................
i
I

J

I

8

AIJ·A7

ANC'

I

D/A

I

D/A

I

D/A

I

R/R.Y!

I
ANALOG
VIDEO

G/Y

I
B/B.Y.

I
I
I
".............................................I
~

1 1
ANCILLARY DATA
IN11lRPACB

Figure 5.

Typical Application.

IMAGING PRODUCTS

3 - 171

Bt294
Circuit Description (continued)

cx:JR601

VIDBO TlMlNO
CONIROUJlR

II,

v, p

CLOCK
71M11Z

CBFLAO

BT294
8

RO·R7

,"

00·07

,"

BO·B7

,"

8

PROMBa.

BUS

-

8

8

BT297

/

Ea.1 TIL RBCEIVBR

"

JlO. D7

AD·A7

ANC·

1 1
ANaLLARYDATA
INTBRPACB

Figure 6.

3-172

SECTION 3

Typical Application.

TO PRAMB BUPPIlR
(ROB COLOR SPAC!!)

Bt294
Internal Registers
Command Register_O
This command register may be written to or read by the MPU at any time and is initialized to $03 following a reset
condition. CROO is the least significant bit and corresponds to data bit AO.

This bit specifies the range of Y, Cr, and Cb on the
YCrCb I/O bus (when inputting or outputting color
(0) Y = 16 to 235, Cr/Cb = 16 to 240 data), and the DO-D7 color data. Typically, mode (0)
(1) Y, Cr, Cb = 1 to 254
should be used. Regardless of the selection, there is
no change in the pipeline delay.

CR07

YCrCbrange

CR06

ROB or YCrCb output select
(0) ROB
(1) YCrCb

CR05

13.5 MHz or 27 MHz ROB outputs

This bit specifies whether the RGB outputs are
outputting RGB or YCrCb color information. Y
information is output onto the OO--G7 outputs, Cr
information is output onto the RO-R7 outputs, and Cb
information is output onto the BO-B7 outputs.
Regardless of the selection, there is no change in the
pipeline delay.

This bit specifies whether or not to double the data
rate of the RGB data.

(0) 13.5 MHz
(1) 27 MHz

CR04

Cr/Cb interpolation filters select
(0) use 12-tap filters
(1) use 2-tap filters

CR03, CR02

Lookup table RAM select
(00)
(01)
(10)
(11)

CROI

These bits specify which lookup table RAM the MPU
is accessing.

red lookup table RAM
green lookup table RAM
blue lookup table RAM
reserved

ROB output disable
(0) enable ROB outputs
(1) disable ROB outputs

CROO

This bit specifies which interpolation filters to use
for the Cr and Cb data. Typically, the 12-tap filters
should be used. Regardless of the selection, there is
no change in the pipeline delay.

Matrix coefficient select
(0) analog matrix
(1) digital matrix

This bit is logically gated with the OE· input pin, and
the resulting value is used to control three-stating the
RGB outputs.

This bit selects which set of coefficients to use in the
YCrCb-to-ROB matrix, as described in the text.
Typically, the digital matrix should be used.
Regardless of the selection, there is no change in the
pipeline delay.

IMAGING PRODUCTS

3 - 173

-

Bt294
Internal Registers (continued)
Command Register_1
This command register may be written to or read by the MPU at any time and is initialized to llxx xxxx following a
reset condition. CR10 is the least significant bit and corresponds to data bit AO.

CR17. CR16

Rounding select
(00)
(01)
(10)
(11)

normal rounding
even rounding
reserved
Dynamic RoundingTM

This bit specifies the type of rounding used.
Regardless of the selection, there is no change in the
pipeline delay.
(00) specifies round up if the fractional data is ~ 0.5.
If the fractional data is < 0.5. the number will be
rounded down.
(01) specifies round up if the fractional data = 0.5 and
the rounded result will be an even number (LSB =0) or
if the fractional data is > 0.5. If the fractional data is
< 0.5. the number will be rounded down.
(11) specifies to use Dynamic Rounding™. where the
fractional data is compared to a random number. and
the result (1 bit) added to the 8 bits of color data. If
the fractional data = O. no rounding is done. R. G. and
B each have their own random number generator.
Typically. this mode should be used.
Dynamic Rounding™ is used under license from
Quantel Limited.

CRlS-CRI0

reserved (test bits)

These bits should be ignored when the MPU reads this
register. Data written to these bits are ignored.

Color Key Registers
The three 8-bit color key registers may be written to or read by the MPU at any time and are initialized to $00
following a reset condition. Data bit AO is the least significant bit and corresponds to the RO. GO. and BO output
bits.
The red color key register is compared against the RO-R7 outputs. the green color key register is compared against
the GO-G7 outputs. and the blue color key register is compared against the BO-B7 outputs. If all unmasked bits
match, the COLOR KEY output is a logical one.

Color Mask Registers
The three 8-bit color mask registers may be written to or read by the MPU at any time and are initialized to $00
following a reset condition. Data bit AO is the least significant bit and corresponds to the RO. GO. and BO output
bits.
A logical zero specifies that the corresponding RGB output bit is to be compared against the corresponding bit in the
color key registers. A logical one specifies that no comparison for the corresponding bit is to take place. and is not
used in the generation of the COLOR KEY output signal.

3· 174

SECTION 3

Bt294
Pin Descriptions
Pin Name

Description

DO-D7

Data inputs (TIL compatible). DO-D7 are latched on the rising edge of CLOCK. DO is the least
significant bit.

Cr/CbO-Cr/Cb7

CrlCb data inputsloutputs (TIL compatible). Multiplexed Cr and Cb information is input or
output via these pins depending on the value of SWR* and SRD*. CrCbO is the least significant
bit. If inputting CrlCb data, it is latched on the rising edge of CLOCK while CLOCK/2 is a
logical one. If outputting CrICb data, it is updated following the rising edge of CLOCK while
CLOCK/2 is a logical one.

YO-Y7

Y data inputs/outputs (TIL compatible). Y information is input or output via these pins
depending on the value of SWR* and SRD*. YO is the least significant bit. If inputting Y data,
it is latched on the rising edge of CLOCK while CLOCK/2 is a logical one. If outputting Y data,
it is updated following the rising edge of CLOCK while CLOCK/2 is a logical one.

CbFLAG

CbFLAG control output (TIL compatible). A logical one indicates Cb data may be input or
output on the CrlCb (0-7) bus. It is output following the rising edge of CLOCK while CLOCK/2
is a logical one.

SWR*

Synchronous write control input (TIL compatible). A logical zero enables Y/Cr/Cb data to be
input via the YO-Y7 and CrlCb (0-7) pins. Both SRD* and SWR* should not be asserted
simultaneously.

SRD*

Synchronous read control input (TTL compatible). A logical zero enables YICr/Cb data to be
output onto the YO-Y7 and CrlCb (0-7) pins. Both SRD* and SWR* should not be asserted
simultaneously.

AO-A7

Ancillary data outputs (TIL compatible). DO-D7 data is output onto AO-A7 following the
rising edge of CLOCK. MPU data is also input and output via this bus. AO is the least
significant bit.

ANC*

Ancillary output (TIL compatible). A logical zero indicates Ancillary data may be present on
the AD-A7 pins. ANC* is output following the rising edge of CLOCK.

RO-R7

Red outputs (TIL compatible). Red color information is output via these pins. Data is output
following the rising edge of CLOCK. RO is the least significant bit.

GO-G7

Green outputs (TIL compatible). Green color information is output via these pins. Data is
output following the rising edge of CLOCK. GO is the least significant bit.

BO-B7

Blue outputs (TIL compatible). Blue color information is output via these pins. Data is output
following the rising edge of CLOCK. BO is the least significant bit.

H,V,F

Video timing control outputs (TIL compatible). They are output following the rising edge of
CLOCK.

RESET"

Reset control input (TTL compatible). RESET* is sampled on the rising edge of CLOCK, and
must be a logical zero for a minimum of three consecutive CLOCK cycles to reset the device.
RESET* must be a logical one for normal operation.

ERROR

Error indicator output (TIL compatible). This output indicates a parity error in the EAV, SAV,
Ancillary data identification code, Ancillary data word count, or Ancillary data. If an error is
detected, ERROR will be a logical one for five CLOCK cycles, three CLOCK cycles after the error
has occurred.

IMAGING PRODUCTS

3 - 175

..

Bt294
Pin Descriptions (continued)
Pin Name
OE*

Description
Output enable control input (TIL compatible). This input is logically gated with command bit
CROl, and the result controls three-stating the RGB outputs as follows:
CROI

OE*

RGBOutputs

0
0
1
1

0
1
0
1

enabled
three-stated
three-stated
three-stated

CLOCK

27 MHz clock input ('ITL compatible). The clock must be present for the MPU to access the
internal control registers.

CLOCK/2

13.5 MHz clock output ('ITL compatible). The clock output is 1(2 the CLOCK rate.

RD*

MPU read control input (TIL compatible). While a logical zero, the contents of the control
If both RD* and WR* are asserted
register/RAM location are output onto AO-A7.
simultaneously, all signal pins are three-stated (note the device should be reset after
three-stating the signal pins).

WR*

MPU write control input ('ITL compatible). The rising edge of WR* latches AO-A7 into the
control register/RAM location. WR* is internally resynchronized to CLOCK, so ClDCK must
be a continuous clock. If both RD* and WR* are asserted simultaneously, all signal pins are
three-stated (note the device should be reset after three-stating the signal pins).

RSO,RSI

Register select control inputs ('ITL compatible). These bits specify whether the MPU is
accessing the address register or the control register/RAM location specified by the address
register. See Table 3.

MPU*

MPU access control output (TIL compatible). A logical zero indicates the MPU may access the
internal registers without contention with Ancillary data. MPU· is output following the rising
edge of CLOCK.

BLANK*

Composite blanking output ('ITL compatible). BLANK* is the logical NOR of the H and V
outputs, and has the same timing.

COlDRKEY

Color key output ('ITL compatible). This output is a logical one for clock cycles where the RGB
outputs contain color information specified by the color key and color mask registers. It is
output following the rising edge of CLOCK.

vee

Power pins. All VCC pins must be connected together.

GND

Ground pins. All GND pins must be connected together.

3· 176

SECTION 3

Bt294
Pin Descriptions (continued)

:/

:::

~

= so

u

~

~ ~

~

!;! :;( ~ iii

" !2 &l «I i

....

1£

~

!!! !::

~

.... .. . ~

~ ~ ~ ~ ~

~ ~

Ii!

:e

t! I:! f:!;:! 12 $ • r.; is \Il II>

~

~

0

(;

63

G3

A7

III

OZ

GND

61

GND

RD'

IlO

01

WR'

51

00

RSO

58

R7

RSl

57

R6

A6

OE'

56

as

vee

55

R-'

vee

GND

54

CLOCK

S3

GND

RESI!T"

52

R3

R2.

DO

51

Dl

50

Rl

D2

49

RO
C1!.7/C/f/

os

 =:

~

§~ ~

..

~

~

lEI I: ~

~

IMAGING PRODUCTS

3·177

Bt294
Application Information
Cr and Cb Interpolation Filters
The Cr/Cb linear phase interpolation filters
interpolate the missing Cr and Cb data to generate
4:4:4 YCrCb data. Input color data samples are passed
unchanged to the output; computed color data (from
the filters) are inserted into the output flow.
If the CR07 command bit is a logical one, then if the
interpolated result is zero, it is made 1; if the
interpolated result is 255, it is made 254. If the CR07
command bit is a logical zero, then if the interpolated
result is 0-15, it is made 16; if the interpolated result
is 241-255, it is made 240.

The transfer function of the 12-tap filters is:
H(Z) = (160!256)*(Z-1 + Z+I)
+ (-48/256)*(Z-3 + Z+3)
+ (24/256)*(Z-5 + Z+5)
+ (-12/256)*(Z-7 + Z+7)
+ (6/256)*(Z-9 + Z+9)
+ (-2!256)*(Z-1l + Z+ll)

During blanking periods, the input color data is
undefmed, possibly disturbing the computed color
data at the beginning and end of active color data. To
avoid this, if the 12-tap is filter-selected, the 2-tap
filter is automatically used at the beginning and end of
the active line unless the 12-tap filter is available
(i.e., the filter pipe is full). Regardless of the filter
selection, the last active pixel per scan line uses the
previous Cr and Cb data for color information.

Doubling the RGB Data Rate
The data rate of RGB output data may be doubled from
13.5 MHz to 27 MHz via the command register. In
this instance, new RGB data is output following the
rising edge of every CLOCK cycle, rather than every
other CLOCK cycle.
To accomplish this, an additional set of 2-tap linear
interpolation filters are used to double the RGB data
rate from 13.5 MHz to 27 MHz. Input color data
samples are passed unchanged to the output; computed
color data (from the filters) are inserted into the output
flow.
The transfer function of the 2-tap filters is:

Seventeen-bit precision (including sign and overflow)
is maintained until the final output stage, then
rounded to 8 bits as specified by command register_I.
Figure 7 shows the transfer function of the 12-tap Cr
and Cb interpolation filters.
The transfer function of the 2-tap filters is:

H(Z) = (128!256)*(Z-1 +Z+I)

Eleven-bit precision (including sign and overflow) is
maintained until the final output stage, then rounded
to 8 bits using Dynamic RoundingTM (used under
license from Quantel Limited).

H(Z) = (128!256)*(Z-1 + Z+I)

Eleven-bit precision (including sign and overflow) is
maintained until the fmal output stage, then rounded
to 8 bits as specified by command register_I.
The Y data and control signals are pipelined to
maintain synchronization with the Cr and Cb data.
There is no change in the pipeline delay regardless of
which filter is used.

Outputting RGB data at the 27 MHz rate may simplify
the analog filtering if the RGB outputs are driving
external D/A converters. Note that any sin x I x
correction must be done with the analog filters after
the D/A converters.

SA V and EA V Error Co"ection
Table 2 gives corrected values for F, V, and H where
possible. Multiple (uncorrectable) errors are denoted
by an asterisk. 01-D3 are Hamming (6:3) protection
bits, and DO is an even parity bit for 01-06.
In the event of an uncorrectable error, the H, V, and F
outputs assume the state specified by the EAV or SAV
sequence (as if an error did not occur).

3 - 178

SECTION 3

Bt294
Application Information (continued)
Random Number Generators
The Bt294 contains two random number generators,

as shown in Figures 8 and 9, used when Dynamic
RoundingTN (used under license from Quantel Limited)
is selected.
Figure 8 shows the random number generator used for
the YCrCb to ROB matrix and the ROB data rate
doubling (it is initialized to $000 following a reset
condition). As each ROB value in the matrix has 4
fractional data bits, 4 bits of random numbering is
generated for each ROB value. The LSB of each 4-bit
random number (DO, 04, D8) corresponds to the LSB
of fractional ROB data.

DB

The ROB rate doubling filters have 1 bit of fractional
data. Random number bit D12 corresponds to red
fractional data, bit D13 corresponds to green, and bit
D14 corresponds to blue.
Figure 9 shows the random number generator for the
Cr and Cb filters (it is initialized to $00 following a
reset condition). As a single CrCb filter is used in a
multiplexed fashion, a single CrCb random number
generator is used. The 12-tap filter has 7 bits of
fractional data. The LSB of the 7-bit random number
(00) corresponds to the LSB of fractional Cr and Cb
data. The LSB of this random number generator (00)
is used for the 2-tap filters, which have 1 bit of
fractional data.

DB

0.1 ..---:---_--.,.----~

o -!-i-H>--4---'"-:......;.,.···.,i..-..o.....!················
1

~

·10

·15

4
INPIJT FREQUENCY (MHZ)

6

INPIJT FREQUIlNCY (MHZ)

Figure 7. CrCb Pass-Band and Stop-Band
Interpolation Filter Characteristics.
IMAGING PRODUCTS

3 - 179

..

Bt294
Application Information (continued)
Typical Applications
Figure 11 shows the Bt291 and Bt294 being used with
a 16-bit YCrCb frame buffer. The Bt291 and Bt294
provide another video I/O port to the
imaging/graphics system.

Figure 10 shows the Bt291 and Bt294 being used with
a 24-bit ROB frame buffer. The Bt291 and Bt294
provide another video I/O port to the
imaging/graphics system.

BGR

DOUBLER

i

G

R

B

MATRIX

MATRIX

MATRIX

CLOCK!2 - - ;................................................................

Figure 8.

Figure 9.

3 - 180

Random Number Generator.

Random Number Generator for Cr and Cb Filters.

SECTION 3

Bt294
Application Information (continued)
ESD and Latchup Considerations

PLCC Sockets

Correct ESO-sensitive handling procedures are
required to prevent device damage, which can produce
symptoms of catastrophic failure or erratic device
behavior with somewhat "leaky" inputs.

l00-pin PLCC sockets for the Bt294 are available
from:
McKenzie Technology
44370 Old Warm Springs Blvd.
Fremont, CA 94538
Phone: (415) 651-2700
FAX: (415) 651-1020
TLX: 910-240-6355
Part Number: PLCC-100-P-T

All logic inputs should be held low until power to the
device has settled to the specified tolerance.
Latchup can be prevented by assuring that all VCC
pins are at the same potential, and that the VCC
supply voltage is applied before the signal pin
voltages. The correct power-up sequence assures that
any signal pin voltage will never exceed the power
supply voltage by more than +0.5 V.

..

or
Yamaichi Electric Mfg. Co., LTD.
3-28-7 Nakamagome, Ohta-ku,
Tokyo 143 Japan
Phone: 03-778-6161
FAX: 03-778-6181
US Representative: (408) 452-0797

Received F, V, H (Bits 06-04)
D3-DO

000

001

010

011

100

101

110

0000
0001
0010
0011

000
000
000

000

000

,.

000

,.

,.

111
101

111

111
111
111

0100
0101
0110
0111

000

,.

,.

001
011

1000
1001
1010
1011

000

1100
1101
1110
1111

,.

,.

,.
,.

,.

,.
,.

,.

011

,.

,.

,.

,.

011
011

,.
,.

110

100
100
100

,.

111
011

100

100

,.

,.
,.
,.

101

110

,.

,.

111
101

011

001
101

010
010
010

001

001
001

,.

,.
,.

010

,.
,.

,.

,.
,.

010

101
101

110

,.

110

,.

,.

,.

001
011

,.

001
101

001

010

Table 2.

,.

,.

101

,.

,.

,.

,.

,.

,.
,.

,.

,.

100

010

,.
,.

100

111
011

,.
,.

111

,.

100

,.

,.

,.

010
110
110
110

,.

,.
,.

110

,.

,.
,.

SA V and EA V Error Correction Table.

IMAGING PRODUCTS

3 - 181

(M

>

....

"5!.

'I:S

n'

-=

QO

N

~

O·

t=

~

N
\0

.,.

.....

=
.,0-

t:Il

t"1
C":l

...,....

l

0
Z

(M

Bt261
GENLOCK

I
I

3

-=
~

VIDEO TIMING
AND DRAM
CONfROL

o·

~

o'q'

.....,
10:

...
~

RGB
COLOR SPACI!

:u

Bt253

RGBVIDEO

AID

/

/

FRAME
BUFFER

RGB
COLOR SPACI!

:u

Bt473

/

RAMDAC

8
/

Bt296

/

~
~

-

--

-

:]~

--.
f")
o

-==
:i"

tD

Q.

;:;.

III

~

:g

-

Bt294

Bt291

YCRCB

RGB

TO

TO

RGB

YCRCB

~.

::to
~

ill

-

DIGITAL VIDEO
DATA

Bt297

8

EeL

/

TO
TLL

/

/

TIL

VIDEO
f---I 'IGrrAL
DATA

TO

EeL

r~

>

-=o· !

't:I

"2r;.
::I

.,.;

::I

I

Bt261
GENLOCK

I

.,0'
:3

VIDEO TIMING

I

i

®

-=o·

AND DRAM
CONTROL

::I

,-...
r'l

-=

""l

0
::I

~.

....,
lO:

24

VIDEO

Bt253

RGB, YIN

.....
!""

AID

-rRGB

16-BIT

Bt291

FRAME

RGBTO

BUFFER

VCRCB

~

-

/

I:l

....

::
>
C:l
....

Z

C:l
"I:l

:=

0

~

-

~

;.
I:l
::-.
<::>

~

Q.
'-"

~

;.

S·

VCRCB
COLOR SPACE

V16

VCRCB
DIGITAL
VIDEO
DATA

.

Bt297
EQ,TO

TTL

8

/

/

Bt294

8

VCRCB
TORGH

/
/

?I

RGB

Bt296

DIGITAL

TTL TO

VIDEO

ECL

DATA

24
/

/

R

~

Bt473

c::
n

RAMDAC

>-3

r----

G
H

00

J

TO
CRT

c=

....

"'*'
N

...

\C

....

~

QC

I

Bt294
Recommended Operating Conditions
Parameter
Power Supply
Ambient Operating Temperature

Symbol

Min

Typ

Max

Units

vee

4.5
0

5.00

5.5
+70

Volts

TA

Symbol

Min

Typ

Max

Units

7.0

Volts

GND-O.5

vee +0.5

Volts

-55
-65

+125
+150
+150

°e
°e
°e

220

°e

°e

Absolute Maximum Ratings
Parameter

vee (measured to GND)
Voltage on any Signal Pin*
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Vapor Phase Soldering
(1 minute)

TA
15
TJ
TVSOL

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
* This device employs high impedance CMOS devices on all signal pins. It should be handled as an
ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V
can induce destructive latchup.

3 - 184

SECTION 3

Bt294
DC Characteristics
Parameter
Digital Inputs
Input High Voltage
Input Low Voltage
Input High Current (Vin = 2.4 V)
Input Low Current (Vin = 0.4 V)
Input Capacitance
(f = 1 MHz, Vin = 2.4 V)
Digital Outputs
Output High Voltage
(lOH = -400 ~A)
Output Low Voltage
(lOL = 6.4 rnA)
3-state Current (if applicable)
Output Capacitance

Symbol

Min

VIH
VIL

2.0
GND-0.5

Typ

IIH
TIL
CIN

Max

Units

VCC+0.5
0.8
1
-1

Volts
Volts
~
~

pF
7

VOH

2.4

Volts

VeL
IOZ
COUl'

0.4

Volts

50

~

20

pF

Test conditions (unless otherwise specified): "Recommended Operating Conditions." Typical values are based
on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.

IMAGING PRODUCTS

3 • 185

..

Bt294
AC Characteristics
Parameter

Symbol

Clock Rate

Min

Typ

Fmax

MPU Data Setup Time
MPU Data Hold Time
RSO, RSI Setup Time
RSO, RSI Hold Time

1
2
3
4

RD*LowTime
WR* Low Time
WR* Cycle Time
RD*, WR* High Time
RD* Asserted to Data Bus Driven
RD* Asserted to Data Valid
RD* Negated to Data Bus 3-Stated

5
6
7
8
9
10
11

CLOCK/2 Low Time
CLOCK/2 High Time
CLOCK/2, H, V, F, Y/Cr/Cb (0-7),
ROB (0-7), CbFLAO,
BLANK* Output Delay

12
13

Max

Units

27

MHz

10
10
10
10

ns
ns
ns
ns

I

100
25

Clock
ns
Clocks
ns
ns
ns
ns

15
15

tbd
tbd

ns
ns

14

5

23

ns

Y/Cr/Cb Input Data, SRD*, SWR*
Setup Time
Hold Time

15
16

10
4

ns
ns

DO-D7 Input Data
Setup Time
Hold Time

17
18

10
4

ns
ns

MPU*, ANC*, ERROR,
COLOR KEY Output Delay
AO-A7 Output Delay

19
20

5
5

100
3
30
5

SRD* Asserted to YCrCb Bus Driven
SRD* Negated to YCrCb Bus 3-Stated
ROB Three-State Disable Time
ROB Three-State Enable Time

21
22

Clock Cycle Time
Clock Pulse Width High
Clock Pulse Width Low

23
24
25

VCC Supply Current*

ICC

23
23

ns
ns

25
25

ns
ns

25
25

ns
ns

37.04
15
15

ns
ns
ns
180

tbd

rnA

Test conditions (unless otherwise specified): "Recommended Operating Conditions." TTL input values are 0-3
V, with input rise/fall times ~ 4 ns, measured between the 10% and 90% points. Timing reference points at 50%
for inputs and outputs. CbFLAO, CLOCK/2, ANC*, Yx, Crx/Cbx, AO-A7, RO-R7, 00-07, BO-B7, MPU*,
COLOR KEY, and ERROR output load ~ 75 pF. Typical values are based on nominal temperature, i.e., room, and
nominal voltage, i.e., 5 V.
*At Fmax. ICC (typ) at VCC

3 - 186

=5.0 V.

SECTION 3

ICC (max) at VCC (max).

Bt294
Timing Waveforms

'1\---~t--LRSO, RSI

b:

I---

~

VALID

t--

I

7

6

WR'

-

9
AO-A7(READ)

AO - A7 (WRfIll)

~}

8
10

V

DATAOIIT(RD'=O)

t

..

I

}-ll

>---

./

>--DATA IN (WK' = 0)
r--

I

-

-2

MPU Read/Write Timing.

CLOCK

CLOCK/2

CBFLAO

Y/CRICB (0 - 7) - OUTPUT,

H, V, F, ROB(O-7),

RGB OR Y 101. DATA

ROB OR Y/eB DATA

BLANK'"
IS

Y/CRICB (0 - 7) -INPIIT,
SRD·, SWR*

16

Y/OI. DATA

Y/CB DATA

RGB, YCrCb Timing.

IMAGING PRODUCTS

3 - 187

Bt294
Timing Waveforms (continued)

CLOCK

DO-D7

MPU', ERROR,
COLORKBY, ANC·

AO-A7

AO-A7, DO-D7 Timing,

RO-R7, GO-G1,

8O-B7

OE'

==y p_x'--------'x'---Output Enable Timing.

3 - 188

SECTION 3

Bt294
Ordering Information

Ambient
Temperature
Range

Model Number

Package

Bt294KPI

100-pin Plastic
I-Lead

00 to +700 C

..

IMAGING PRODUCTS

3 • 189

Advance Information
This document contains information on a product under development. The parametric
information contains target parameters and is subject to change.

Distinguishing Features

Applications

• Latched TIL-Compatible lnputs
• lOKH ECL-Compatible Parallel Outputs
PLL Operation for Stable Timing
Separate TIL and ECL Supply Pins
• TTL-Compatible Control Inputs
• 68-pin PLCC Package

• CCIR601
• SMPTE RP125
• EBU3246-E

Related Devices

Bt296
27 MHz VideoNet™
TTL-to-IOKH EeL
II-Bit Translator
Product Description

• Bt297
The Bt296 TIL/ECL Translator converts 11 bits of
TIL data to 11 bits of differential 1OKH ECL data.
In many cases involving the transmission of
digital video signals, differential ECL signals
In addition, the phase
levels are used.
relationship between the clock and data signals
(and between data signals) is tightly defined.
Thus, the TIL video data must be converted to ECL
levels, and the phase relationship between clock
and data adjusted to compensate for part-to-part
output delay variations of TIL devices.

Functional Block Diagram

ECLCLK*
TTLCLK
ECLCLK

10

The B t296 incorporates all translators in one
package to eliminate delay skew that results when
using multiple devices. A lO-bit data path is
supported for high-end systems and compatibility
with future products.

ECL (DO> - D9*)
TTL (DO-D9)

10
ECL(DO-D9)
OE*

VCC

GND

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121
(619) 452-7580· (800) VIDEO IC
TLX: 383 596 • FAX: (619) 452-1249
L296001 Rev. B

VEE

3 - 191

The clock-to-data timing on the ECL outputs is
controlled by the on-chip PLL, enabling
CCIR601, EBU 3246-E, and SMPTE RP-125
timing requirements to be met without adjustment.
In addition, the ECL CLK outputs have a 50% duty
cycle regardless of the TIL CLK duty cycle.

..

Bt296
Pin Descriptions
Pin Name

Description

TIL (DO-D9)

TIL data inputs (TIL compatible). They are latched on the rising edge of TIL CLK, converted to
differential ECL levels, and output onto the ECL (00-09) and (DO*-D9*) pins. Unused pins
should be connected to GND. In 8-bit systems, TIL DO and TIL Dl should be connected to
ground, using the TIL D2 (LSB)-TIL 09 inputs for the 8 bits of data.

TILCLK

TIL clock input (TIL compatible). The rising edge of TIL CLK latches the TIL DO--D9 data.

ECL (DO--D9),
ECL (00*-D9*)

Differential ECL data outputs (ECL compatible). These are open emitter-follower outputs.

ECLCLK,
ECLCLK*

Differential ECL clock outputs (ECL compatible). These are open emitter-follower outputs.

OE*

Output enable control (TIL compatible). A logical one forces the ECL outputs low and the ECL*
outputs high (both data and clock) asynchronously to the clocks.

REXT

VCO free-running control. A resistor between this pin and GND sets the free-running frequency
of the VCO. For 27 MHz, a value of 4220 ohms is recommended.

IF

Loop filter pin. The loop filter for the PLL is connected between this pin and GND. See Figure 1
(resistor values are in ohms, capacitor values are in f.lF).

vee

TIL power supply. All VCC pins must be connected together as close to the device as possible.

GND

Ground. All GND pins must be connected together as close to the device as possible.

VFE

ECL power supply. All VEE pins must be connected together as close to the device as possible.

4221)

RElIT

LF

I--J\f\r---,

1--'--...,
0.005
56.2

Bt296

Figure 1.

3 • 192

PLL Loop Filter (27 MHz Clock, 100 KHz Loop Bandwidth).

SECTION 3

Bt296
Recommended Operating Conditions
Parameter
Device Ground
TTL Power Supply
ECL Power Supply
Ambient Operating Temperature

Symbol

Min

Typ

Max

Units

GND

0
+4.75

VFE
TA

-4.9

0
+5.0
-5.2

0
+5.25
-5.5
+70

Volts
Volts
Volts

vee

0

·e

Note: Thermal eqUilibrium is established by applying power for at least 2 minutes while maintaining a
transverse air flow of 400 linear feet per minute over the device, either mounted in the test socket or on the
printed circuit board.

Absolute Maximum Ratings
Parameter

Symbol

Min

VEE (measured to GND)
(measured to GND)

vee

Typ

Max

Units

-8.0
+7.0

Volts
Volts

Voltage on Any ECL Pin

-1.8

GND

Volts

Voltage on Any TTL Pin

GND-O.5

vee +0.5

Volts

-50

rnA

+125
+150
+150

·e
·e
·e

220

·e

ECL Output Current
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Vapor Phase Soldering
(1 minute)

TA
TS
TJ
TVSOL

-55
-65

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

IMAGING PRODUCTS

3 • 193

Bt296
ECL DC Characteristics
Parameter

Symbol

TA(OC)

Min

Output High Vo1tage*

VOH

0
+25
+70

Output Low Voltage*

VOL

0
+25
+70

Typ

Max

Units

-1020
-980
-920

-840
-810
-735

mV
mV
mV

-1950
-1950
-1950

-1630
-1630
-1600

mV
mV
mV

Output hnpedance
Output Capacitance

VEE Supply Current**

7
tbd

IEE

0
+25
+70

55
55
55

Ohms
pF
70
70
70

rnA
rnA
rnA

Test conditions (unless otherwise specified): "Recommended Operating Conditions" with ECL output loading
of 50 n to -2.0 V. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.
*Relative to GND.
**For power calculations, it is necessary to add an additional 330 mW due to emitter-follower devices.
The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium
is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet
per minute over the device, either mounted in the test socket or on the printed circuit board.

TTL DC Characteristics
Parameter

Max

Units

2.0

TILVCC
+0.5

Volts

TILGND
-0.5

0.8

Volts

IIH

70

J.IA

IlL

-0.7

rnA

Symbol

Min

Input High Voltage*

VIH

Input Low Voltage*

VlL

Input High Current
(Vin = 2.4 V)
Input Low Current
(Vin= 0.4 V)
Input Capacitance

Typ

pF

tbd

VCC Supply Current

ICC

80

110

rnA

Test conditions (unless otherwise specified): "Recommended Operating Conditions." Typical values are based
on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.
*Relative to GND.

3 • 194

SECTION 3

Bt296
AC Characteristics
Parameter
TTL DO-D9 Setup Time
TTL DO-D9 Hold Time
TTL CLK High Time
TTL CLK Low Time
TTL CLK Input Rate
ECL DO-D9 Output Delay
ECL DO-D9 Delay Skew*
ECL CLK Output Delay**
ECL CLK Output Duty Cycle

Max

Units

tbd

27

ns
ns
ns
ns
MHz

5

tbd

6

(0.5 / Fin)-3
42

10
3
(0.5 / Fin)+3
58

ns
ns
ns
%

10,000
200

Clocks
Clocks

2

ns

15
15

ns
ns

Symbol

Min

1
2
3
4
Fin

3
3
10

Typ

10

0.5 / Fin
50

PLL Acquire Time***
100 KHz Loop Bandwidth
1 MHz Loop Bandwidth
Output Rise/Fa11 Time
(20%-80%)
Output Disable Time
Output Enable Time

0.5

1

7
8

Test conditions (unless otherwise specified): "Recommended Operating Conditions" with ECL output loading
of 50 n to -2 Y. TTL input values are 0--3 Y, with input rise/fall times $ 4 ns, measured between the 10% and
90% points. Timing reference points at 50% for inputs and outputs. Typical values are based on nominal
temperature, i.e., room, and nominal voltage, i.e., 5 Y.
*Fastestlslowest (unipolar).
**Rising edge of ECL CLK relative to ECL (DO - D9).
*** At 27 MHz. Initial frequency offset of ± 30%, [mal residual frequency error of ±1 %.

Timing Waveforms

TILCLK

TIL (DO. 09)

JlCL (DO· 09)

BCLCLK

OB'

Input/Output Timing.

IMAGING

PRODUCTS

3 • 195

..

Bt296
Ordering Information

3 • 196

Model Number

Package

Bt296KPI

68-pin Plastic
I-lead

SECTION 3

Ambient
Temperature
Range
0° to +700 C

Advance Information
This document contains information on a product under development. The parametric
information contains target parametersis are subject to change.

Distinguishing Features

Applications

•
•
•
•
•
•
•

CCIR601
• SMPTE RP125
• EBU3246-E

lOKH ECL Compatible Inputs
Registered or Transparent Operation
TTL-Compatible Outputs
Separate TTL and ECL Supply Pins
TTL-Compatible Control Inputs
68-pin PLCC Package
Typical Power Dissipation: 550 mW

Related Devices

Bt297
27 MHz VideoNet™
lOKH EeL to TTL
ll-Bit Translator
Product Description

• Bt296
The Bt297 ECL/ITL Translator converts 11 bits of
differential 10KH ECL data to 11 bits of TTL
data.
The Bt297 incorporates all translators in one
package to eliminate delay skew that results when
using mUltiple devices.

Functional Block Diagram

The REG EN input controls whether the input data
is registered or the data register is bypassed
(transparent operation).
The TTL clock and data outputs may be three-stated
asynchronously to the clock by the OE* pin.

ECLCLK'

X-I----

TILCLK

ECLCLK
10
ECL (DO' - D9')

>-~-- TIL (DO - D9)

10
ECL(DO·D9)

OE'

REGEN

VCC

Brooktree Corporation
9950 Barnes Canyon Rd.
San Diego, CA 92121
(619) 452-7580· (800) VIDEO IC
TLX: 383596· FAX: (619) 452-1249
L297001 Rev. D

GND

VEE

3 • 197

Bt297
Pin Descriptions
Pin Name

Description

TIL (DO-09)

TIL data outputs (TIL compatible).

T1LCLK

TIL clock output (TIL compatible).

EeL(DO-09)
EeL (00*-09*)

Differential EeL data inputs (EeL compatible). ECL data is latched by the EeL CLK signals,
converted to TIL levels, and output onto the TIL data pins. Single-ended EeL operation may be
used by connecting the EeL (00*-09*) pins to VBB (-2 V). If a pair of EeL inputs are left
floating or are in the same logical state, the corresponding TIL output will be a logical zero.

EeLCLK,
EeLCLK*

Differential ECL clock inputs (EeL compatible). Single-ended ECL operation may be used by
connecting the ECL CLK pin to VBB (-2 V). If REG EN is a logical one, the EeL CLK is
inverted and output onto the TIL CLK output pin. If REG EN is a logical zero, the EeL CLK is
not inverted before being output onto the TIL CLK output pin.

REGEN

Register enable control input (TIL compatible). A logical one enables the DO-09 input data to
be registered by the data input register. A logical zero bypasses the data input register, enabling
transparent operation.

OE*

Output enable control (TIL compatible). A logical one three-states the TIL (00-09) and TIL
CLK outputs asynchronously to the clock.

vee

TIL power supply. All VCC pins must be connected together as close to the device as possible.

GND

Ground. All GND pins must be connected together as close to the device as possible.

VFE

EeL power supply. All VEE pins must be connected together as close to the device as possible.

3· 198

SECTION 3

Bt297
Recommended Operating Conditions
Parameter
Device Ground
TTL Power Supply
ECL Power Supply
Ambient Operating Temperature

Symbol

Min

Typ

Max

Units

GND

0
+4.75
-4.9
0

0
+5.0
-5.2

0
+5.25
-5.5
+70

Volts
Volts
Volts
°C

VCC
VEE
TA

Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a
transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the
printed circuit board.

Absolute Maximum Ratings
Parameter

Symbol

Min

VEE (measured to GND)
VCC (measured to GND)

Typ

Max

Units

-8.0
+7.0

Volts
Volts

Voltage on Any ECL Pin

-1.8 V

GND

Volts

Voltage on Any TTL Pin

GND-O.5

VCC +0.5

Volts

-55
-65

TJ

+125
+150
+150

°C
°C
°C

TVSOL

220

°C

Ambient Operating Temperature
Storage Temperature
Junction Temperature
Vapor Phase Soldering
(1 minute)

TA
15

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

IMAGING PRODUCTS

3 • 199

Bt297
ECL DC Characteristics
Parameter

Symbol

TA(OC.)

Min

Input High Voltage·

VIH

0
+25
+70

Input Low Voltage·

vn.

0
+25
+70

Input Current
(Vin = VIHmax or VIL min)

UN

0
+25
+70

Common Mode Voltage Range
Differential Input Voltage

Max

Units

-1170
-1130
-1070

-840
-810
-735

mV
mV
mV

-1950
-1950
-1950

-1480
-1480
-1450

mV
mV
mV

10
10
10

jJA
jJA
jJA

-310

mV
mV

tbd

- 2450
185

Input Impedance
Input Capacitance

ECL VEE Supply Current

Typ

lEE

0
+25
+70

Ohms
pF

tbd
tbd

5
5
5

7
7
7

rnA
rnA
rnA

Test conditions (unless otherwise specified): "Recommended Operating Conditions." Typical values are based
on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.
*Relative to GND.
The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium
is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet
per minute over the device, either mounted in the test socket or on the printed circuit board.

3 - 200

SECTION 3

Bt297
TTL DC Characteristics
Parameter

Symbol

Min

Input High Voltage*

V1H

Input Low Voltage*

vn..

Input High Current
(Vin = 2.4 V)
Input Low Current
(Vin = 0.4 V)
Output High Voltage*
(IOH = -2.0 rnA)
Output Low Voltage.
(lOL=20rnA)

VOH

1bree-S tate Output Current
Vout = VOHmin
Vout = VOLmax

IOZ

Max

Units

2.0

TILVCC
+0.5

Volts

TILGND
-0.5

0.8

Volts

illI

70

IlA

m..

-0.7

rnA

Volts

2.5

VOL

Output Capacitance
Input Capacitance
TIL VCC Supply Current

Typ

0.5

Volts

10
-10

IlA
IlA
pF
pF

tbd
tbd
ICC

100

130

rnA

Test conditions (unless otherwise specified): "Recommended Operating Conditions." Typical values are based
on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.
*Relative to GND.

IMAGING PRODUCTS

3 • 201

-

Bt297
AC Characteristics-Registered Operation
Parameter

Symbol

Min

1

3
3
10

ECL DO-D9 Setup Time
EeL DO-D9 Hold Time
EeL CLK High Time

2
3

Clock Rate

Typ

Max

Units
ns
ns
ns

tbd

27

MHz

TIL DO-D9 Output Delay
TIL CLK Output Delay

4
5

tbd
tbd

10
10

ns
ns

Output Disable Time
Output Enable Time

6

7

tbd
tbd

15
15

ns
ns

Test conditions (unless otherwise specified): "Recommended Operating Conditions." EeL input values are
-0.89 to -1.69 V, with input rise/fall times S 4 ns, measured between the 20% and 80% points. Timing
reference points at 50% for inputs and outputs. Typical values are based on nominal temperature, i.e., room, and
nominal voltage, i.e., 5 V.

Timing Waveforms-Registered Operation

BCLCLK

3

~
I

OB·

I

2 I

1

* *
DATA
IN

BCL(DO.D9)

7TIL(DO·D9)

I--

-

1--4

DATA

our

I-- 5

TILCLK

Registered Input/Output Timing.

3· 202

SECTION 3

-

-6

Bt297
AC Characteristics-Transparent Operation
Parameter

Symbol

Min

Output Delay

1

Output Disable Time
Output Enable Time

2
3

Typ

Max

Units

tbd

10

ns

tbd
tbd

15
15

ns
ns

Test conditions (unless otherwise specified): "Recommended Operating Conditions." ECL input values are
-D.89 to -1.69 Y, with input rise/fall times S 4 ns, measured between the 20% and 80% points. Timing
reference points at 50% for inputs and outputs. Typical values are based on nominal temperature, i.e., room, and
nominal voltage, i.e., 5 Y.

Timing Waveforms-Transparent Operation

~

OE'

ECL(DO-D9).
Ila.CLK

DATA

3TIl.. (DO· 09),
TIl..CLK

-

IN
1

-

I

*

1--2

DATA

OIIT

Transparent Input/Output Timing.

IMAGING PRODUCTS

3 - 203

..

Bt297
Ordering Information

3 - 204

Model Number

Package

Bt297KPJ

68-pin Plastic
J-lead

SECTION 3

Ambient
Temperature
Range
00 to +70 0 C

Advance Information
This docwnent contains information on a product under development. Specifications are
subject to change without notice.

Distinguishing Features
•
•
•
•
•
•
•
•

Arbitrary Scaling of Raster Bit Maps from 5% through 750%
Scale Down (Reduce) and Scale Up (Enlarge) Capability
Rotation of +/- 90· and 180·
Output Image Cropping
Output Image Bit-aligned Block Transfers (Bitblt)
Scaler Output of 4-bit Gray Scale
Output Mapping through Internal 8-bit Lookup Table for 1-,4-, or 8-bit Output
132-pin PGA Package

Raster Data Accelerator for Image Viewing and Printing
Docwnent Imaging Systems Requiring Fast Response Times
Laser Printer Controllers

Functional Block Diagram

I.
ADDRESS

ADDRESS

DATA

DATA

MUX

MUX

CONI1
    I/O Port A Address Bus. Pins AA9 (MSB) through AAO (LSB) comprise a triple multiplexed address bus. The frrst phase is termed the extended address cycle. The next two phases are termed the RAS and CAS DRAM cycles. On the falling edge ofAXAL*, AA9-AAO contain the extended address bits. On the falling edge of ARAS*, AA9-AAO contain the row address. On the falling edge of ACAS*, AA9-AAO contain the column address. During programmed I/O operations, AA3-AAO are inputs and select the internal register to be read or written by the MPU. When DMA is not active, this bus is high-7. ARAS* OUT Port A Row Address Strobe. This pin is asserted when the row address has been placed on AA9-AAO. When DMA is not active, this pin is high-7. ACAS* OUT Port A Column Address Strobe. This pin is asserted when the column address has been placed on AA9-AAO. When DMA is not active, this pin is high-7. AXAL* OUT Port A Extended Address Latch Enable. This pin is asserted when an extended address cycle is performed to output the high-order address bits on AA9-AAO. AXAL is activated prior to the first cycle of each DMA transfer and thereafter as necessary (whenever the extended address changes). The number of bits which are output on an extended cycle depends upon the DRAM size specification provided in the CONTROL.2 register. The Bt710 will always output 24 bits of address in a triple multiplexed fashion. This output is never put in high-7 state. AD<15--o> I/O Port A Data Bus. These pins comprise the 16-bit bi-directional data bus. AD15 is the most-significant bit and ADO is the least-significant bit. When DMA is not active, this bus is high-7. ADS* I/O Port A Data Strobe. During DMA operations, this pin is an output and is asserted when output data will be placed on the data bus during DMA writes. It is asserted during DMA reads to indicate to the slave device that input data may be placed on the data bus. During bus slave operations, this pin is an input and should be asserted when write data is valid or when read data should be output on the data bus. ACS* IN Port A Chip Select. This pin, when active-low, enables access to the internal registers. AR/W* I/O Port A Read Not Write Strobe. During DMA operations, this pin is an output. During programmed I/O operations, this pin is an input. During bus cycles, this signal differentiates between read and write cycles. ARDY* I/O Port A Ready. During DMA operations, this pin is an input. During bus slave operations, this pin is an output. This signal is asserted to indicate that the current bus cycle may be completed. If not asserted prior to frrst being sampled by the Bt710, wait states will be added to the current DMAcycle. AGNT* IN Port A Bus Grant. This pin is an input which grants the Bt710 access to the bus. AREQl* OUT Port A Bus Request 1. This pin, in conjunction with AREQO*, requests access to the Port A and remains active until AGNT* is asserted. The encode for AREQI * and AREQO* is shown in Table 2. AREQO* OUT Port A Bus Request O. This pin is the second of two encoded bus requests output when access to Port A is requested. Table 2 lists the encode for these two bus requests. IMAGING PRODUCTS 3·219 .. Bt710 Pin Descriptions (continued) Pin Name I/O Description AOWN OUT Port A Bus Owned. This output goes active-high during DMA cycles to indicate to external devices that the Bt71 0 has control of the Port A bus. When DMA is not active. this pin is high-7. BA<9--O:> OUT Port B Address Bus. Pins BA9 (MSB) through BAO (LSB) comprise a triple multiplexed address bus. The first phase is termed the extended address cycle. The second two phases are termed the RAS and CAS DRAM cycles. On the falling edge of BXAL"'. BA9-BAO contain the extended address bits. On the falling edge of BRAS*. BA9-BAO contain the row address. On the falling edge of BCAS*. BA9-BAO contain the column address. When DMA is not active. this pin is high-7. BRAS* OUT Port B Row Address Strobe. This pin is asserted when the row address has been placed on BA9-BAO. BCAS* OUT Port B Column Address Strobe. This pin is asserted when the column address has been placed on BA9-BAO. When DMA is not active. this pin is high-7. BXAL* OUT Port B Extended Address Latch Enable. This pin is asserted when an extended address cycle is performed to output the high-order address bits on BA9-BAO. BXAL* is activated prior to the first cycle of each DMA transfer and thereafter as necessary (i.e .• whenever an increment of the DMA address counter causes a carry out of the lower bits). The number of bits which are output on an extended cycle depends upon the DRAM size specification provided in the control register. The Bt701 will always output 24 bits of address in a triple multiplexed fashion. This output is never put in a high-7 state. BD<15--D> I/O Port B Data Bus. These pins comprise the 16-bit bi-directional data bus. BD15 is the most-significant bit and BDO is the least-significant bit. When DMA is not active. this bus is high-7. BDS* OUT Port B Data Strobe. During DMA operations. this pin is an output and is asserted when output data will be placed on the data bus during DMA writes. It is asserted during DMA reads to indicate to the slave device that input data may be placed on the data bus. When DMA is not active. this bus is high-7. BRjW* OUT Port B Read Not Write Strobe. This pin differentiates between read and write cycles. When DMA is not active. this pin is high-7. BRDY* IN Port BReady. During DMA operations. this input is asserted to indicate that the current bus cycle may be completed. If not asserted prior to first being sampled by the Bt710. wait states will be added to the the current DMA cycle. BGNT* IN Port B Bus Grant. This pin is an input which grants the Bt710 access to the bus. BREQl* OUT Port B Bus Request 1. This pin. in conjunction with BREQO*. requests access to the Port B and remains active until BGNT* is asserted. The encode for BREQl'" and BREQO'" is shown in Table 2. BREQO* OUT Port B Bus Request o. This pin is the second of two encoded bus requests output when access to port B is requested. Table 2 lists the encode for these two bus requests. 3·220 SECTION 3 Bt710 Pin Descriptions (continued) Pin Name IJO Description BOWN OUT Port B Bus Owned. This output goes active-high during a DMA cycle to indicate to external devices that the Bt710 has control of the Port B bus. When DMA is not active, this pin is high-7. SBF* IN Source Buffer Full. This input is from an external processor such as the Bt701 which, when driven low, indicates that the next available source buffer is full. This input must stay low until the SBA* output is driven low. When strip mode is not enabled, this input is ignored. SBA* OUT Source Buffer Available. This output is driven low when the SBF* has been sampled low and the next available source buffer is available to the external processor. This output remains low until the SBF* input is sampled high. When strip mode is not enabled, this output remains high. OUT Interrupt This active-low output indicates a request by the Bt701 for interrupt servicing by the host processor. The interrupt reason and interrupt enable/disable may be controlled via the register interface on the Bt710. RESET* IN Reset When driven low, the Bt7lO operation is haIted and put into a known state. This pin contains an internal pull-up resistor. CLOCK IN External clock input This input supplies the internal clock signal for timing the B t70 I state machines and bus timing. This clock is 2x the internal clock. TEST* IN Test Pin. This pin is intended for manufacturing tests and should be left disconnected in normal use. This pin contains an internal pull-up resistor causing the input to remain high when unconnected. VDD IN Power supply. All VDD pins must be connected to a common power supply system. This supply is nominally 5V. VSS IN Ground Connections. Ail VSS pins must be connected to the common ground system. IMAGING PRODUCTS 3- 221 ]Jrod{tree~ Bt710 Pin Descriptions (continued) Signal AD9 VSS AOIO ADll ADl2 ADl3 VSS VOO ADl4 ADl5 AAO AAI VSS AA2 AA3 AA4 Signal C3 B2 Al 03 C2 BI CI SBP* RESET* n/c SBA* VSS BREQO* BREQI* BOWN VDO BRJW* F3 F2 PI G3 G2 01 HI AA6 VSS VOO AA7 AA8 AA9 ADS* ARAS* VSS ACAS* AXAL J1 KI K2 L1 K3 MI L2 NI L3 M2 M3 N2 PI n/c n/c n/c n/c ARJW* VOO AROY* AOWN VSS AREQI* AREQO* INT· VSS CLK VOO TEST ACS* AGNT* n/c VOO BROY* BGNT* VSS E3 EI P2 N3 M4 P3 N4 P4 M5 N5 P5 M6 N6 P6 M7 N7 SECTION 3 PIn Signal Pin Number BOlO VSS BOO 014 013 012 Cl4 Cl3 Bl4 Cl2 Bl3 Al4 Al3 Bl2 Cll Al2 Bll All CIO BIO AIO C9 B9 A9 C8 B8 A8 A7 B7 C7 A6 B6 C6 Number D2 01 E2 AA5 3 - 222 Pin Number n/c n/c n/c BXAL BCAS* VSS BRAS* BOS* BA9 BA8 BA7 VOO VSS BA6 BAS BA4 BA3 BA2 VSS BAI BAO VSS BOl5 BD14 VOO B013 BD12 BOll P7 P8 N8 M8 P9 N9 M9 PIO NIO MIO Pll NIl Mll Pl2 Nl2 Pl3 Ml2 Nl3 Pl4 Nl4 Ml3 Ll2 Ml4 L13 Ll4 Kl2 Kl3 Kl4 112 113 114 Hl2 Hl3 Hl4 014 013 012 Pl4 Pl3 Pl2 El4 El3 El2 n/c n/c n/c n/c n/c n/c VDO VDO BDS B07 BD6 VSS B05 BD4 B03 VSS BD2 BOI BOO VSS VDO ADO ADI VSS AD2 AD3 VOO AD4 AS AD5 VSS B5 C5 A4 B4 AD6 A07 VOO AD8 n/c n/c VSS VSS VOO VOO C4 A3 B3 A2 H2 H3 J2 J3 Bt710 Pin Descriptions (continued) 14 FOR EVALUATIVE PURPOSES ONLY. Contact the Factory for Final Pin Out. BDIS BAI VSS BA4 VSS BAB BOS' VSS B0l2 BDI4 BAO BAl BAS VOD BM VSS BD9 BDl1 VOO VSS BAl BA6 RA? BRAS' BCAS' BXAL BR/W' VOD VOD 12 BD? VOO 11 VSS BD6 BD8 10 BD3 BD4 BDS BOl BD2 VSS VOD VSS BOO ADO ADI VSS AD2 AD3 VOD ILK VOO TEST AD4 ADS VSS AREQO 1Nf' VSS AD6 AD? VOD ARDY' VSS AREQI VOD AOWN AD8 Bt710 AA4 VSS VOD ADS' AXAL VSS ADI2 ADI4 AAO AA2 AA5 VSS VOD AA8 VSS ADI3 VSS ADIS VSS AA3 AA6 VSS VOD AA? AA9 A B C D E p G H K L BXAL BeAS· BDS· BA8 VSS BA4 VSS BAI BD15 8D13 BOlO VSS BA9 VDO BAS BA2 BAO BDI4 BDI2 VSS BRAS' BA? BA6 BAl VSS VOD BOl1 BD9 BR/W* AR/W' ARAS' ACAS' M N p VDD VOD BO? 11 BREQO BREQI BOWN BDS BD6 VSS 10 SBA. VSS BDS BD4 B03 VSS VSS B02 BDI BDO VSS VOD BRDY· BGNT* ET' VDD (BOTTOM VIEW) SBP AGNf* ACS· VSS ADI ADO TEST VDD CLK VOD AD3 AD2 VSS 1Nf' AREQO VSS ADS AD4 AREQI VSS ARDY' YDn AD7 AD6 AOWN VDD AR/W' ACAS' ARAS' p N M .. RESET· (TOP VIEW) AAI VOO SOA· VDD VDD 13 12 VSS ADl1 8 14 BOWN BREQI BREQO AD9 2 FOR EVALUATIVE PURPOSES ONLY. Contact the Factory for Final Pin Out. B0l3 13 4 aligrunent marker (on top) BOlO AXAL ADS· VDD VSS AA4 AAl VDD ADll AD9 ADS VSS AA8 VOD VSS AA5 AA2 AAO ADI4 ADI2 VSS AA9 AA? VOD VSS AA6 AA3 VSS ADIS VSS AD13 [ADI~ L K H G p E D C B A IMAGING PRODUCTS 3 - 223 Bt710 Application Information Bt710 Parameters and Data Structures Source DMA Parameters Figure 21 illustrates the parameters used by the Bt710 for source DMA operations. The SRC.PITCH parameter, specified in the register by the same name, defines the pitch of the frame buffer from which the source image is to be read. This parameter is the distance in words to the next line. The SRC.ADR.1 parameter is a 24-bit address pointer to the first word of the source image. This parameter is specified in the register by the same name. Note that the source image must be specified on a word boundary. SRC.LM SRC.ADR.1 • The SRC.LINE.LEN parameter specifies the length of the source image line in 16-bit words. This parameter is specified in the register by the same name. The SRC.LM and SRC.RM parameters specify the left and right margin offsets respectively. These parameters are found in the SRC.MARGINS register. See the description for DST.LM and DST.RM in the next section. The SRC.LINE.COUNT parameter specifies the total number of raster lines in the source image. This parameter is specified in the register by the same name. SRCPITCH ---"I-...."- SRC.LINE.LEN L -.J § 0 u ~ ~ • Y LW IMAGE TO BE PROCESSED BYTHEBt7l0 ~ V) FRAME BUFFER Figure 21. Source X-Y DMA Parameters. 3 - 224 SECTION 3 V- SRC.RM Bt710 Application Information (continued) Destination DMA Parameters The DST.LM parameter specifies the left pixel offset in the word pointed to the DST.ADR.l in which the image is to be placed. This is illustrated in Figure 23. This parameter allows images to be placed on pixel boundaries in the destination frame buffer. The DST.LM parameter is contained in the DST.MARGINS register. IT the output pixels are packed 4-bit or 8-bit pixels, the DST.LM register must be on a 4-bit or 8-bit boundary as appropriate. Other values in this case will cause unpredictable operation. Figure 22 illustrates the parameters used by the Bt7l0 for destination DMA transfers. The destination DMA channel is capable of full bit-aligned block transfer to a destination frame buffer. The DST.PITCH parameter specifies the pitch of the frame buffer that will contain the destination image. The parameter is specified in the register by the same name. DST.PITCH is expressed in words. The DST.LINE.LEN parameter specifies the number of words in one output line. This parameter is specified in the register by the same name. The DST.ADR.l parameter is a 24-bit address pointer to the first word of the destination image. This parameter is specified in the register by the same name. When rotation is performed, DST.ADR.l points to the fmt word of the image. IT a DST.LINE.LEN parameter is specified which is not equal to the line length as a result of scaling and rotation, then unpredictable operation will occur. DST.LM DST.ADR.1 --- • • DSTPITCH ~I DST.UNELEN ~, L W L ~ Y f-I ~ DST.RM IMAGE 0 TO BE WRITTEN I BYTHEBt710 .5 V. Bt710 Recommended Operating Conditions Symbol Min Nom Max Units Supply Voltage VDD 4.75 5 5.25 V Supply Voltage VSS High-level Output Current IOH Parameter V 0 ARAS*, ACAS*, ADS·, AR/W*, ARDY*, AREQ* Low-level Output Current BRAS*, BCAS*, BDS*, BR/W*, BREQ* -400 ILA 1.7 rnA IOL AA<9:O>, BA<9:0:> 3 All other outputs 2 High-level Input Voltage VlH 2 VCC+.3 V Low-level Input Voltage VIL -0.3 0.8 V 30 pF ARDY*, AREQ*<1:0> BREQ*<1:0> SBA*, DBF*, INT*, AXAL*, BXAL* Load Capacitance Operating Free-air Temperature ADS*, AR/W*, AOWN,BDS*, BR/W*, BOWN, 35 CL ARAS*, ACAS*, BRAS*, BCAS* AD<15:0>,BD<15:0> 50 AA<9:O:>, BA<9:0:> 65 TA 0 70 IMAGING PRODUCTS ·C 3- 233 Bt710 Absolute Maximum Ratings Symbol Parameter Min Typ Supply Voltage Max Units 7 V Input Voltage Range* VSS"'{}.3 VCC+.5 V Output Voltage Range -2 7 V 0 70 °C TA Operating Free-air Temperature Range Note: Stresses above those listed IDlder "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. DC Characteristics Symbol Test Conditions High-level output voltage VOH VDD=MIN,IOH=MAX Low-level output voltage VOL VDD=MIN,IOL=MAX 0.4 V Input leakage current, high IIH VDD=MAX, VlH=MIN 1 I1A Input Leakage current, low IIL VDD=MAX, VIL=MAX -1 ItA Off-state output current IOZ VO = 0.4 V to 2.4 V 10 I1A Supply current IDD VDD=MAX, TA=25° 250 rnA CI f=1 MHz, all other inputs atOV. 15 pF Parameter Input capacitance Min Typ Max 2.4 V NOTE Throughout these specifications, the frrst letter (A or B) is removed from the signal name if the identical signal on different B t710 ports has the same behavior. For example, a column address strobe signal (CAS*) is present on both port A and port B of the Bt710. Since these signals behave identically, only the generic signal name CAS* will be used. 3 - 234 SECTION 3 Units Bt710 CLOCK Timing Parameters (See Note 1 and Figure 35) No. Parameter Min Max 21 1 Cycle Time (tc) 19 2 Pulse Width High 6 3 Pulse Width Low 6 4 Rise Time 2 5 Fall Time 2 Units ns .. / Figure 35. CWCK Timing. IMAGING PRODUCTS 3·235 Bt710 Bus Arbitration Timing Parameters (See Note 1 and Figures 36-37) No. Parameter Min Max 6 Delay time, CLOCK to REQI */REQ2* high or low 45 7 Delay time, CLOCK to OWN high 45 8 Delay time, CLOCK to XAL* high 45 9 Delay time, CLOCK to RAS* high 45 10 Delay time, CLOCK to CAS* high 45 11 Delay time, CLOCK to R/W*, DS* high 45 12 Delay time, GNT* low to OWN high 13 Delay time, CLOCK to address no longer hi-z. 14 Delay time, GNT* low to XAL* high, first memory cycle (note 4) 15 Hold time, REQI *, REQO* low after OWN high 0 16 Hold time, GNT* low after OWN high (note 3) 0 17 Delay time, GNT* high to OWN low, bus release (note 5) 18 Delay time, CLOCK to OWN low, bus release 45 19 Delay time, CLOCK to address, data, and control hi-z, bus release 45 20 Delay time, OWN high to address no longer hi-z tc 21 Delay time, OWN high to XAL*, RAS*, CAS*, R/W*, DS* driven high or low tc Units 4te 5 45 ns Notes: 3·236 8te 30tc+3w 1. All timing references are to the 0.8 V and 2 V levels. 2. If the GNT* input is taken high prior to state T1 of any cycle, the bus will be released at the end of that cycle; otherwise the bus release occurs at the end of the next bus cycle unless a refresh operation is pending. If a refresh is pending, the Bt7l0 will hold the bus until refresh is complete. If the Bt7l0 enters wait states after or when GNT* is taken high, OWN will remain high indefinitely as long as the Bt710 is in wait states. 3. Once GNT* is asserted to the Bt7l0, GNT* must remain low until parameter Iii is met. 4. After XAL is driven high, the bus timing is as shown for read, write, or refresh cycles unless this is the first bus request after enabling DRAM refresh for the first time. In this case, the first bus cycles following OWN going high will be eight CAS before RAS refresh cycles for DRAM initialization. 5. w =Number of wait states. SECTION 3 Bt710 Bus Arbitration Timing Parameters (continued) Tx CLOCK REQI·, REQO· GNT" .. OWN AO-A9 ------ ---------- XAL· RAS·, CAS· R/W. os· 00-015 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- Figure 36. BI710 Acquires Bus. IMAGING PRODUCTS 3-237 Bt710 T4 T5 CLOCK REQ1*! REQO* ONT* 18 OWN AO-A9 XAL* RAS·! CAS· R/W* DS* DO-015 Figure 37. B(710 Releases Bus. ReadlWrite Cycle Timing Parameters (See Note 1 and Figures 38-41) No. Parameter Min Max 22 Delay time, CLOCK to XAL*, DS·, R/W·low or high 43 23 Delay time, CLOCK to RAS* low 47 24 Delay time, CLOCK to RAS· high 33 25 Delay time, CLOCK to address valid, DS·, XAL· high or low 34 26 Delay time, CLOCK to CAS· low 31 27 Delay time, CLOCK to CAS* high 31 Units ns 3 ·238 SECTION 3 Bt710 ReadlWrite CycleTiming Parameters (continued) No Parameter Min 28 Delay time, row address valid to RAS* low 29 Delay time, RAS* low to row address no longer valid 3tc-1O 30 Delay time, RAS* low to CAS* low 4tc-16 31 Delay time, RAS* low to DS* low 2tc-1O 32 Delay time, column address valid to CAS* low tc-3 33 Delay time, CAS* low to column address no longer valid 5tc+3 34 Pulse width, RAS* low (note 2, 4) 6tc -10 35 Pulse width, CAS* low (note 2, 3) 4tc 36 Pulse width, RAS* high (note 2, 5) 4tc+2 37 Delay time, extended address valid to XAL* low tc-2 38 Delay time, XAL* low to extended address no longer valid 39 Access time, RAS* low to read data valid (note 2, 3) 40 Pulse width, DS* low (note 2, 3) 41 Delay time, RAS* low to RDY* low to guarantee zero wait states Max Unit tc+2 .. ns tc 6tc-4 -5 42 Delay time, RDY* low to DS* high with zero wait states 8tc-9 43 Pulse width low, RDY* 2tc 44 Setup time, read data valid prior to CAS* no longer low 30 45 Hold time, read data after CAS* high 0 46 Delay time, R/W* high to CAS* low, read cycle 47 Read/Write cycle time (note 2) 48 Access time, CAS* low to read data valid (note 2, 3) 49 Delay time, CAS* high to RAS* no longer high 4tc -12 10tc 2tc +3 IMAGING PRODUCTS 3·239 Bt710 ReadlWrite CycieTiming Parameters (continued) No Parameter Min 50 Delay time, CAS· high to R/W'" no longer high 51 Delay time, colunm address valid to RAS· no longer low 3tc + 1 52 Delay time, OS* low to CAS· low 2tc-12 53 Delay time, RAS· low to 00-015 no longer hi-z 2tc-6 54 Oelay time, CLOCK high to write data valid 55 Delay time, OS * low to write data valid 56 Delay time, write data valid to CAS· low 2tc-ll 57 Oelay time, OS* high to write data no longer valid 2tc+ 1 58 Delay time, R/W* high to 00-015 hi-z 59 Delay time, CAS· high to R/W* no longer low 60 Hold time, ROY'" high after RAS. low to add one or more wait states 2tc 61 Delay time, ROY· low to OS· high, one or more wait states 8tc 62 Setup time, ROY* high prior to RAS· low for one or more wait states Notes: 1. 2. 3. 4. 5. 3- 240 Max Unit 2tc 9 40 5 ns 0 2tc+ 1 tc+ 1 All timing references are to 0.8 V and 2 V. When one or more wait states are inserted, state T4w is automatically inserted. Only one T4w state is inserted irrespective of the number of wait states. When wait states are inserted, 2n+2 additional tc cycles are added to this time where n is equal to the number of wait states. Minimum times are for zero wait states. Times given are for zero wait states. When one or more wait states are inserted, the maximum and minimum times are extended by 2n tc cycles where n is equal to the number of wait states inserted. The minimum time is when state Tl of the next cycle occurs following T5 of the current cycle. If a Tx cycle occurs, this parameter is increased by one tc period. SECTION 3 Bt710 ReadlWrite CycleTiming Parameters (continued) Tx CLOCK Tl 1'2 25 M ~ 23 ji ::t 24 h 34 36 ~ r\ CAS· 28 ) 51 12 29 11 37 !I ( ROW ADDRESS 24. 35 " 49 ~ 10 25 \ 47 I A AO-A9 T1 u If vuvuuuUUlfVVVVV - XAL" Tx T5 T4 1'3 ~ COLUMN ADDRESS .. 18 EXT.ADR !lo". 46 I R/W. / 52 31 DS· - 48 44 45 51 25 40 } I A -.) 39 DO-Dl5 »»»»)») ---------------41 RDY· '\'\'\'\'\'\'\'\'\'\'\'\~ VALID READ DATA ----------- 42 41 1/////////////////////;//////////////////// Figure 38. Read Cycle Timillg-O Wait States. IMAGING PRODUCTS 3·241 Bt710 ReadlWrite CycleTiming Parameters (continued) Tx T1 T3w 1'3 T2 T4w T4 T5 TI ~11 UV\JVlf\]IJ"'-nJ\J\J\J ~ XAL· 23:] RAS· 47 31 24 .1 34 .R I'-- ~ 111 7:1 49 CAS· ... .25J 128 I X X ROW ADDRESS 22- 11 12 .II OOLUMN ADDRESS 3: 50 1 40 ~ J 1 45 i"---- VAlJDRBADDATA ~---. 52 !::::::125 DS· j!.. 46 ~ .J 39 DO-DI5 »»»»».1>. 1 62 RDY· //////$ -------------------------~ ..6l ..Jlll. JI1( 1 43 .1 ·Y////////////////L///////////////////////// Figure 39. Read Cycle Timing with Wait States. 3 • 242 SECTION 3 .1 Bt710 ReadlWrite CycieTiming Parameters (continued) Tx a.OCK leAL· ~ n T1 Tx 1'5 T4 T1 U UUIf'J If'J lJlJ lfVlJ\JlJUL 4 ;r \ 47 24J 23H RAS· 36 ,I 34 :)I ~ 30 49 '--- -E-.. 35 CAS· .,f 251 29 28 32 T X 37 33 X ROW ADDRESS ~ COLUMN ADDRESS EXT.ADR 52 59 I \ 3' os· - 25 40 55 roD15 -l ---------- 57 VALID WRTIB DATA 42 " \..\..\..\..\..\..\..\.\.\.\. ~ I 56 r- ~ 54 53 41 RDY· 38 :11 43 ~ - -:k//////////U////////////////////////////// Figure 40. Write Cycle Timing-O Wait States. IMAGING PRODUCTS 3·243 .. Bt710 ReadlWrite CycleTiming Parameters (continued) Tx CLOCK 1'2 TI T3w 1'3 T.... T4 T5 TI 1{UVVUVUlJ\JVLfl.1I..JVLfUl/U'L XAL· 23=f RAS· 47 36 24 .1 34 .lI i'---- .A.. ,. n 35 CAS· lSI 111 X 3~ ?O I X ~ .., 33 II. ROW ADDRESS 40 COLUMN ADDRESS 52 ;;---- 24 ,j! " I-- 2S os· f.--A-.t 40 I .55. 00-015 53 ------62 ROY· ///////7 f-&- 56 ~ 61 I 43 J J(// / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Figure 41. Write Cycle Timing with Wait States. 3 • 244 SECTION 3 ~~- vALIDWRITB DATA 60 .11 .., Bt710 DRAM Refresh Timing Parameters (See Note 1 and Figures 42-43) No Parameter Min 63 Delay time, CAS· low to RAS· low 2tc + 17 64 Pulse width, RAS*low (note 3) 6tc-lO 65 Pulse width, CAS. low (note 3) Stc 66 Pulse width, RAS· high (note 2) 4tc+2 67 Delay time, CAS· low to ROY· low to guarantee zero wait states 6S Delay time, ROY· low to CAS· high, zero wait states 69 Hold time, ROY· high after CAS· low to guarantee one or more wait states 2tc 70 Delay time, ROY· low to CAS· high, one or more wait states Stc Notes: 1. 2. 3. 4. Max -5 Unit ns .. All timing refererences are to the O.S V and 2 V levels. When one or more wait states are inserted, state T5w is automatically inserted. Only one T5w state is inserted irrespective of the number of wait states. When wait states are inserted, n+1 additional tc cycles are added to this time where n is equal to the number of wait states. Times given are for zero wait states. When one or more wait states are inserted, the maximum and minimum times are extended by n tc cycles where n is equal to the number of wait states inserted. IMAGING PRODUCTS 3 - 245 Bt710 DRAM Refresh Timing Parameters (continued) T1 T2 T3 T4 TS CLOCK XAL" RAS" CAS" AO-A9 DON'T CARE R/W" High OS" High DO-DIS ROY" Figure 42. DRAM Refresh Timing-No WailSlales. 3·246 SECTION 3 T6 T1 Bt710 DRAM Refresh Timing Parameters (continued) Tl 1'2 1'3 1'3w T4 TS TSw T6 Tl CLOCK XAL" RAS" CAS" AO-A9 R/W" OS" OO-D1S RDY" DON'T CARE ~~----~-----61 ------43 Figure 43. DRAM Refresh Timing-Wait States. IMAGING PRODUCTS 3·247 .. Bt710 Programmed I/O Timing Parameters (See Note 1 and Figures 4~5) No. Parameter Min Max 75 Access time, register address valid to read data valid 76 Access time, ACS* low to read data valid (note 2) 12tc 77 Access time, ADS* low to to read data valid (note 2) 12tc 78 Delay time, ACS* low to AOWN low 79 Delay time, ADS* low to ARDY* low 120 80 Hold time, register address valid after ADS* high 2tc 81 Setup time, ARJW* high prior to ADS* low 2tc 82 Hold time, AR/W* after ADS* high 83 Pulse width, ADS* high between consecutive cycles 4tc 84 Delay time, ADS* high to read data no longer valid 4 85 Delay time, ADS* high to OO-D15 hi-z 4 86 Delay time, ADS* high to ARDY* high 2tc 87 Delay time, ADS* low to ARDY* active 100 88 Setup time, register address prior to ADS* low 2tc 89 Setup time, ACS* low prior to ADS* low 2tc 90 Hold time, ACS* low after ADS* high 160 91 Setup time, write data prior to ADS* no longer low 2tc 92 Hold time, ADS* high after AOWN no longer high 93 Pulse width, ADS* low, write cycle 94 Hold time, write data valid after ADS* high Unit 30tc+3w 183 0 ns Notes: 1. 2. 3. 3·248 163 4tc 4 All timing references are to the 0.8 V and 2 V levels. Register access begins when ACS*, ADS*, and AOWN are all low. If AOWN is high when ACS* is taken low, register access is delayed until the Bt70l takes AOWN low. The minimum times given are based upon AOWN being low when the ACS* or ADS* are taken low. The maximum times are the worst case delay times for the Bt710 to remove AOWN after sampling ACS* low. OWN must be driven low by the Bt710 prior to driving the programmed I/O input signals. SECTION 3 Bt710 Programmed I/O Timing Parameters (continued) A4-AO ACS· AOWN .. AR/W. ADS· ADO-IS - - - - - - - ARDY· - - - _ _ _ _ _ _ _ _ _ _ VAUDREADDATA Figure 44. Programmed 110 Read Cycle. A4-AO VAUD ADDRESS ACS· AOWN AR/W* ADS· ADO-IS ARDY* Figure 45. Programmed 110 Write Cycle. IMAGING PRODUCTS 3·249 Bt710 Reset Timing Parameters (See Figure 46) No. 95 Parameter Min 8tc Pulse width, RESET low RESET* Max Unit ns _y 1_9_5 Figure 46. RESET Timing. SBF/SBA DBA/DBF Timing Parameters (See Figure 47) No. Parameter Min 96 Pulse width. SBF* • DBA* low 8tc 97 Delay time. SBA*. DBA* low to SBF*. DBF* low 7tc Max Unit ns 96 SBF*/DBA* 97 SBA*/DBF* Figure 47. SBFISBA DBAIDBF Timing. 3·250 SECTION 3 Bt710 Ordering Information ModelNwnber Package Ambient Temperature Range Bt710KG 132-pinPGA O· to +70·C Bt700EVK Evaluation Kit 00 to +70·C IMAGING PRODUCTS 3 - 251 Advance Information This document contains information on a product under development. The parametric information contains target parameters and is subject to change. PixelVu™ Object-oriented Software Toolkit for Imaging Distinguishing Features Product Description • C-callable library. Concise set of powerful functions. • Multiple platform support: PC-AT, Macintosh and SUN. • Multiple windowing environments: MS-Windows, Color QuickDraw, andX. • Multiple operating systems: MS-DOS with third-party DOS extenders, Macintosh aod UNIX. Object-oriented processing for maximum power and flexibility. • Open Architecture: Support of application-specific image objects. • Scale-to-gray algorithm for enhanced visual quality. Transparent hardware acceleration. PixelVu is a toolkit specifically designed for OEMs and systems integrators of imaging systems. PixelVu consists of a concise set of C-callable functions. Because of the small number of functions, the programmer can easily become familiar with this powerful library. Compressed images can be read, decompressed, scaled, rotated and BitBLTed directly into the frame buffer or print buffer. PixelVu contains all the image manipulation functions required to process bi-level images on a disk or in memory and output the result to memory or a display device. The PixelVu toolkit was designed with portability as a key requirement. The same library is available for 286 and 386-based PCs, 68020- and 68030- based Macintosh computers, and SUN platforms. In addition, PixelVu supports multiple operating MS-DOS, environments, including MS-Windows, Color QuickDraw, and X. PixelVu supports devices and system resources through programming structures called image objects (Figure 1). Brooktree's object-oriented software toolkit permits developers to reference an image object and select an operation to be performed on that image without having to know any details about how to read data from or write data to the object. In this way, software development is simplified because Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 L700001 Rev. A 3 - 253 device-specific data need not be studied by the application developer. OEMs and third party developers can create their own objects and interface them within the PixelVu environment. In this way, custom file formats or third party devices can be added to PixelVu's image management and image manipUlation capabilities. PixelVu provides scale-to-gray capabilities. Scaling a bi-Ievel image to gray-scale display image provides anti-aliasing effects. This provides a much more readable image at resolutions less than that normally needed for readability. PixelVu performance can be increased by adding image manipulation hardware into the system. Hardware acceleration can be transparent to the application. If supported hardware is present in the system it will be used to optimize function execution. If no hardware is present, image manipulation is executed in software. In this way, PixelVu provides a low-cost solution for moderate use environments and a high-performance solution for performance-critical applications. The Brooktree Bt710 scale-to-gray integrated circuit can be used to efficiently provide hardware scale-to-gray capability. PixelVu™ Raster Image Manipulation PixelVu includes the manipulation primitives: following raster image cropped to any pixel boundary, permitting any window area to be selected. • Compression and Decompression. CCfIT Group 3 and Group 4 compression and decompression are provided to support existing standards. • Reflection. To provide correcting capabilities for reverse scanning of microfihn, bitmaps may also be reflected. • Image Scaling. A bitmap may be scaled down in increments of 1% to as small as 6% of its initial size. A bitmap may be scaled up to as much as 750% of its initial size. • Conversion to Gray. A binary bitmap may be converted to gray when scaling to provide improved display quality on gray scale or color monitors. This prevents loss of information inherent in decimation scaling algorithms. • Image Rotation. Rotation of +/- 90 and 180 degrees is supported. Rotation facilitates conversion between landscape and portrait modes. • BilBLT. Bitwise Block Transfers are performed by PixelVu. Data can be copied into a destination area on pixel boundaries. Boolean operations can also be performed on images. • Cropping. The input or output bitmap may be PixelVu Strip Engine Image In Image Out Raster Image Manipulation Functions PixelVu Image Manager Scanner Objects File Objects Memory Objects Printer Objects Display Objects Figure 1: PixeWu is an Object-Oriented Toolkit. 3 - 254 SECTION 3 ApplicationSpecific Objects PixelVu™ PixelVu Functions There are four types of functions in the PixelVu library: Initialization and Termination Functions, Image Object Functions, Image Manipulation Functions and Support Utility Functions. InitialiZlJtion and Termination Functions Image Manipulation Functions All image manipulation functions in PixelVu are selected using a Parameter Block. Fields in a parameter block select different processing functions to take place. Bt_Transfer performs the selected image manipulation functions. BeGetParamBlock Initialization and termination functions provide the means to begin a session of PixelVu, terminate it and obtain error and status information. Belnit Initialize the PixelVu Software Toolkit. Bt_DisposeParamBlock Deallocate all memory previously allocated to a parameter block. Verify the validity of the fields in a parameter block. Terminate PixelVu. BeGetError Obtain the last PixelVu error status. BeVersion Obtain this PixelVu Ve~sion Number. Bt_ErrorStr Return a text error message. Perform image manipulation based upon the fields of the parameter block. BeUpdateTransfer Image Object Functions Image Object Functions are used to open, create or dispose of image objects. The image objects supported include: file objects: TIFF (Tagged Image File Format) and Sun Raster file formats; memory objects; and window objects: Macintosh Color QuickDraw, Microsoft Windows 3.0 and Xl1.3. BeOpenImageTiff Open an existing TIFF file .. BeCreatelmageTiff Create a new TIFF file. Create a new Parameter Block. Perform image manipUlation based upon the fields of the parameter block but only affect a subset of the destination area. Utility Functions Utility functions are provided to facilitate calculation of source and destination rectangles. the Calculate a destination rectangle based upon a given source rectangle and scale factor. Open an existing Sun Raster file. Bt_CalcSourceRect Calculate a source rectangle based upon a given destination rectangle and scale factor. B t_CreatelmageSunR Create a new Sun Raster file. BeCalcSourceClip B t_CreatelmageMem Create a new memory Image Object. BeOpenImageMem Create a new memory Image Object from a user supplied memory pointer. Open a Macintosh Window. BeOpenImageWindow Adjust a source rectangle to conform to a destination clipping area, rotation, reflection and scale factor. A detailed description of PixelVu functions and operations may be found in the PixelVu Programmers Reference Manual. Open a Microsoft Windows 3.0 Window. BCOpenImageXWindow Open an X.l1 Window. Free up all memory resources previously allocated to an Object. IMAGING PRODUCTS 3·255 .. PixelVu™ Ordering Information Platforms: PC-AT SUN-3 SUN-4 SPARCstation Macintosh II* Operating System MS-DOS V3.1* UNIX System 6.0.3* Windowing Environments Microsoft Windows 3.0 X11.3 Open Windows Macintosh Windowing Environment X11.3 Server SUNC THINK's LightSpeedC X11.3 Server Compilers Supported Microsoft C VS.l TurboC V2.0 Watcom COpt. Compiler/386 V7.0** High C-386** Extended Memory Support Eclipse OS/286 DOS Extender** Eclipse OS/386 DOS Extender** Phar Lap 3861ASM/Link and Phar Lap 3861VMM DOS Extenders** Part Number Bt700SDA * ** Under System 7 Bt700SSA Bt700SMA Indicates a level of support and higher. Not running under Microsoft Windows. PixelVu, Bt701, Bt710, B t71 02 and Bt71 03 are registered trademarks of Brooktree Corporation. SUN, SUN-3, SUN-4, SPARCstation and Open Windows are registered trademarks of Sun Microsystems, Inc. Macintosh, Macintosh Plus, QuickDraw and Apple are registered trademarks of Apple Computer, Inc. Microsoft and MS-DOS are registered trademarks of Microsoft Corporation. UNIX is a registered trademark of AT&T. X Window System is a registered trademark of Massachusetts Institute of Technology. Turbo C is a registered trademark of Borland International. High C is a registered trademark of Metaware, Inc. Watcom is a registered trademark of Watcom, Inc. Eclipse is a registered trademark of Eclipse Computer Solutions, Inc. Phar Lap is a registered trademark of Phar Lap Software. Lightspeed is a registered trademark of Lightspeed, Inc. THINK Technologies is a division of Symantec Corporation. Infonnation furnished by Brooktree Cor(x>ration is helieved to be accurate and reliable. However, no responsihility IS assumed for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Brooktree Corporation. 3 - 256 SECTION 3 Copyright © 1990, Brooktree Corporation. Specifications are subject to change without notice. SECTION 4 r------ RAMDACs ------. Contents Bt450 80,66, 50, 35 MHz Triple 4-bit RAMDAC with 16 x 12 RAM 4-7 Bt453 66, 40 MHz Triple 8-bit RAMDAC with 256 x 24 RAM 4 - 57 Bt453/883 40 MHz MlL-STD-883 Version of Bt453 4 -75 Bt454 170, 135, 110 MHz Triple 4-bit RAMDAC with 16 x 12 RAM, 4: 1 Multiplexed Pixel Inputs 4 - 91 Bt455 170, 135, 110 MHz single 4-bit RAMDAC with 16 x 4 RAM, 4: 1 Multiplexed Pixel Inuts 4 - 91 Bt461 170, 135, 110, 80 MHz Single 8-bit RAMDAC with 1024 x 8 RAM, 256 x 8 Alternate RAM, 3:1,4:1, or 5:1 Multiplexed Pixel Inputs 4 - 241 Bt462 170, 135, 110, 80 MHz Single 8-bit RAMDAC with 1024 x 8 RAM, 256 x 8 Alternate RAM, 3:1, 4:1, or 5:1 Multiplexed Pixel Inputs 4 - 241 Bt474 85,66 MHz Triple 8-bit RAMDAC with 256 x 24 RAM, 4:1 Multiplexed Pixel Inputs 4 - 421 Bt492 360 MHz Single 8-bit RAMDAC with 256 x 8 RAM 4 - 515 Bt458 Family Bt451 125,110,80 MHz Triple 4-bit RAMDAC with 256 x 12 RAM, 4:1 or 5:1 Multiplexed Pixel Inputs 4 - 23 Bt457 125,110,80 MHz Single 8-bit RAMDAC with 256 x 8 RAM, 4:1 or 5:1 Multiplexed Pixel Inputs 4 - 23 Bt458 165, 125, 110, 80 MHz Triple 8-bit RAMDAC with 256 x 24 RAM, 4:1 or 5:1 Multiplexed Pixel Inputs 4 - 23 Bt458/883 110 MHz MIL-STD-883 Version of Bt458 4 - 111 Bt459 Family Bt459 135, 110,80 MHz Triple 8-bit RAMDAC with 256 x 24 RAM, 1:1,4:1, or 5:1 Multiplexed Pixel Inputs, 64 x 64 On-Chip Cursor 4 - 135 Bt460 135, 110,80 MHz Triple 8-bit RAMDAC with 512 x 24 RAM, 1:1,4:1, or 5:1 Multiplexed Pixel Inputs, 64 x 64 On-Chip Cursor 4 - 187 Bt468 200, 170 MHz Triple 8-bit RAMDAC with 256 x 24 RAM, 8: 1 Multiplexed Pixel Inputs, 64 x 64 On-Chip Cursor 4 - 327 TrueVu Family Bt463 170, 135, 110 MHz Triple 8-bit True Color Window RAMDAC with (3) 528 x 8 RAM, 1:1,2:1,4:1 Multiplexed Inputs 4 - 2 4 - 279 VGA Family Bt471 80,66,50,35 MHz Triple 6-bit RAMDAC with 256 x 18 RAM 4 - 371 Bt473 80,66,50,35 MHz Triple 8-bit RAMDAC with 256 x 24 RAM, 8:1 Multiplexed Pixel Inputs 4 - 395 B t4 7 5 80, 66, 50, 35 MHz Triple 6-bit Power-Down RAMDAC with 256 x 18 RAM 4 - 455 Bt476 66,50,35 MHz Triple 6-bit RAMDAC with 256 x 18 RAM 4 - 371 B t4 77 80,66, 50, 35 MHz Triple 8-bit Power-Down RAMDAC with 256 x 24 RAM 4 - 455 Bt478 SO, 66, 50, 35 MHz Triple 8-bit RAMDAC with 256 x 24 RAM 4 - 371 Bt479 80,66,50,35 MHz Triple 8-bit WindowVu RAMDAC with 1024 x 24 RAM 4 - 481 4 - 3 RAMDAC Selection Guide D/A Organization Speed (MHz) triple 4-bit 80, 66, 50, 30 triple 4-bit Part Page RAM Size Overlay Size Bt450 4-7 16 x 12 3 x 12 4:1 muxed pixel inputs 125, 110, 80 Bt451 4 - 23 256 x 12 4 x 12 Bt458 pin compatible triple 4-bit 170, 135, 110 Bt454 4 - 91 16 x 12 1 x 12 triple 6-bit 80, 66, 50, 35 Bt471 4-371 256 x 18 15 x 12 Bt478 pin compatible triple 6-bit 80, 66, 50, 35 Bt475 4 - 455 256 x 18 15 x 12 power-down Bt471 triple 6-bit 66,50,35 Bt476 4 - 371 256 x 18 - Bt478 pin compatible single 8-bit 170, 135, 110, 80 Bt461 4 - 241 1024 x 8 256 x 8 muxed pixel inputs single 8-bit 170, 135, 110, 80 Bt462 4 - 241 1024 x 8 256 x 8 underlay capability single 8-bit 125, 110, 80 Bt457 4 - 23 256 x 8 4x8 Bt458 pin compatible single 8-bit 360 Bt492 4 - 515 256 x 8 16 x 8 2: 1 muxed pixel inputs triple 8-bit 66,40 Bt453 4 - 57 256 x 24 3 x24 triple 8-bit 165, 125, 110, 80 Bt458 4 - 23 256 x 24 4 x24 triple 8-bit 135, 110, 80 Bt459 4 - 135 256 x 24 15 x 24 4:1, 5:1 muxed pixel inputs on-chip cursors triple 8-bit 135, 110, 80 Bt460 4 - 187 512 x 24 15 x 24 on-chip cursors triple 8-bit 200, 170 Bt468 4 - 327 256 x 24 15 x 24 8: 1 muxed pixel inputs triple 8-bit 85,66 Bt474 4 -421 256 x 24 15 x 24 4:1 muxed pixel inputs triple 8-bit 80, 66, 50 Bt477 4 -455 256 x 24 15 x 24 power-down feature triple 8-bit 80, 66, 50, 35 Bt478 4 - 371 256 x 24 15 x 24 PS!2RAMDAC triple 8-bit 80, 66, 50, 35 Bt479 4 - 481 1024 x 24 15 x 24 Window RAMDAC true color 170, 135, 11 Bt463 4 - 279 (3) 528 x 8 (3) 15 x 8 true color 80, 66, 50, 35 Bt473 4 - 395 (3) 256 x 8 (3) 15 x 8 Nwnber ° 4-4 Brod-r---t-- COMP PO-Pl -:>---+-_ lOR SYNC' >---+--100 BLANX' >---01-- lOB OLO,OLl DO-04 Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580, (800) VIDEO IC TLX: 383596, FAX: (619) 452-1249 lA50001 Rev. G 4. 7 The Bt450 generates RS-343A compatible video signals into a doubly terminated 75 n load, and RS-170 compatible video signals into a singly terminated 75 n load, without requiring external buffering. Differential and integral linearity errors of the D/A converters are guaranteed to be a maximum of ±1/16 LSB and ±l/8 LSB, respectively, over the full temperature range. Bt450 Circuit Description MPU Interface As illustrated in the functional block diagram, the Bt450 has an internal 16 x 12 color palette RAM, three 12-bit overlay registers, and three 4-bit D/A converters, allowing the display of up to 19 simultaneous colors from a 4096-color palette. The dual-port color palette RAM and dual-port overlay registers allow color updating without contention with the display refresh process. The CO input specifies whether the MPU is accessing the address register (logical zero), or the color palette RAM location or overlay register specified by the address register (logical one). The 5-bit address register is used to address the color palette RAM and overlay registers, eliminating the requirement for external address multiplexers. ADDRO corresponds to DO and is the least significant bit. To write color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be modified. During color write cycles, color data is input from DO-D3, with DO being the least significant bit. D4 is ignored. The MPU performs three successive write cycles (4 bits each of red, green, and blue), using CO to select the color palette RAM and overlay registers. Duting the blue write cycle, the three bytes of color information are concatenated into a 12-bit word and written to the location specified by the address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. To read color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be read. Duting color read cycles, color data is output onto OO-D3, with DO being the least significant bit. D4 is a logical zero. The MPU performs three successive read cycles (4 bits each of red, green, and blue), using CO to select the color palette RAM and overlay registers. Following the blue read cycle, the address register increments to the next location, which the MPU may read by simply reading another sequence of red, green, and blue data. The address register increments to $13 following a blue read or write cycle to location $12. 4·8 SECTION 4 To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADDRa, ADDRb) that count modulo three, as shown in Table 1. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The MPU does not have access to these bits. The other five bits of the address register (ADDR0-4) are accessible to the MPU, and are used to address color palette RAM locations and overlay registers, as shown in Table 1. Figute 1 illustrates the MPU read/write timing. Frame Buffer Interface The PO-P3, OLO, and OL1 inputs are used to address the color palette RAM and overlay registers, as shown in Table 2. The addressed location provides 12 bits of color information to the three 4-bit D/A converters. Refer to Figute 2 for video input/output timing. The SYNC. and BLANK· inputs, also latched on the rising edge of CLOCK to maintain synchronization with the color data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figute 3. Table 3 details how the SYNC· and BLANK· inputs modify the output levels. The analog outputs of the Bt450 are capable of directly driving a 31.5 n load, such as a doubly terminated 15 n coaxial cable. ESD and Latchup Considerations Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failute or erratic device behavior with somewhat "leaky" inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay V AA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by asSuting that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assutes that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. Bt450 Circuit Description (continued) Value co 00 01 10 1 1 1 $xx $OO-$OF $10 $11 $12 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 write to address register write to color palette RAM write to overlay color 1 write to overlay color 2 write to overlay color 3 $xx $OO-$OF $10 $11 $12 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 read address register read color palette RAM read overlay color 1 read overlay color 2 read overlay color 3 $xx $xx x x 0 1 0 x 0 x invalid operation 3-state DO--D4 ADORa, b (counts modulo 3) ADOR0-4 (counts binary) Table 1. CS*, co RD", WR.. cs· RD* WR* Addressed by MPU red value green value blue value, increment AOOR0-4 I Address Register (ADDR) Operation. =x X VALID \ / < DO - D4 (KllAD) DATA oUT (RD. = 0) X DO-D4(WRITIl) Figure 1. DATA IN(WR•• O) > X MPU Read/Write Timing. RAMDACs 4 • 9 Bt450 Circuit Description (continued) OLl OLO PO--P3 Addressed by frame buffer 0 0 : 0 0 1 1 0 0 $0 $1 : $F $x $x $x color palette RAM location $0 color palette RAM location $1 : color palette RAM location $F overlay color 1 overlay color 2 overlay color 3 : 0 1 0 1 Table 2. Pixel and Overlay Control Truth Table. CLOCK PO -P3, OLD, OLl, SYNC·. BLANK· DATA lOR, 100, lOB Figure 2. 4 - 10 SECTION 4 Video Input/Output Timing. Bt450 Circuit Description (continued) RED,BUlB ORBBN MA V MA V 1~.OS 0.714 26.ffl 1.000 . , - - - - - , . . - - - - - - - - - - - - - - - - . ; . . - - - - - WHIT!! LIlVBL 1M 0.054 9.05 0.340 -t---------\-----(--------- BLACK LJ!VBL 7.5 IRE 0.00 0.000 7.62 Cl.286 0.00 0.000 -t--------'-...,.---r-.&--------- BLANK LIlVBL .. 40 IRE -L._ _ _ _ _ _ _............L_ _ _ _ _ _ _ _ _ _ SYNC LIlVBL Note: 75 Q doubly tenninated load, RSET =499 Q. RS-343A levels and tolerances assumed on all levels. Figure 3. Composite Video Output Waveforms. Description lOG (rnA) lOR, lOB (rnA) SYNC· BLANK· DAC Input Data WHrIE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 19.05 data + 1.44 data + 1.44 1.44 1.44 0 0 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $F data data $0 $0 $x $x Note: Typical with full-scale lOG = 26.67 rnA. RSET = 499 Q. Table 3. Video Output Truth Table. RAMDACs 4 - 11 Bt450 Pin Descriptions Pin Name Description BlANK* Composite blank control input (TTL compatible). A logic zero drives the analog outputs to the blanking level, as illustrated in Table 3. It is latched on the rising edge of CLOCK. When BLANK* is a logical zero, the pixel and overlay inputs are ignored. SYNC'" Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source on the lOG output (see Figure 3). SYNC'" does not override any other control or data input, as shown in Table 3; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. If sync information is not to be generated on the lOG output, this pin should be connected to GND. CLOCK Clock input (TTL compatible). The rising edge of CLOCK latches the PO-P3, OLO, OLI, SYNC"', and BLANK* inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedicated TTL buffer to avoid reflection-induced jitter. PO-P3 Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 16 entries in the color p'alette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK. PO is the LSB. Unused inputs should be connected to GND. OLO,OLI Overlay select inputs (TTL compatible). These inputs specify which palette is to be used to provide color information, as illustrated in Table 2. When accessing the overlay palette, the PO-P3 inputs are ignored. They are latched on the rising edge of CLOCK. OLO is the LSB. Unused inputs should be connected to GND. lOR, lOG, lOB Red, green, and blue current outputs. These high-impedance current sources are capable of directly driving a doubly terminated 75-ohm coaxial cable (Figure 4). All outputs, whether used or not, should have the same output load. FSADJUST Full scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal (Figure 4). Note that the IRE relationships in Figure 3 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on lOG is: RSET (0) = 13,308/IOG (rnA) The amount of full-scale output current on lOR and lOB for a given RSET is: lOR, lOB (rnA) = 9,506/ RSET (0) 4· 12 SECTION 4 Bt450 Pin Descriptions (continued) Pin Name Description COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 J.lF ceramic capacitor must be connected between this pin and the adjacent V AA pin (Figure 4). The COMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to PC Board Layout Considerations for critical layout criteria. VM Analog power. All VAA pins must be connected. GND Analog ground. All GND pins must be connected. CS* Chip select control input (ITL compatible). This input must be a logical zero to enable data to be written to or read from the device. Note that the Bt450 will not function correctly while CS*. RD*. and WR* are simultaneously a logical zero. WR* Write control input (ITL compatible). To write data to the device. both CS* and WR* must be a logical zero. Data is latched on the rising edge of WR* or CS*. whichever occurs first. See Figure 1. RD* Read control input (ITL compatible). To read data from the device. both CS* and RD* must be a logical zero. See Figure 1. CO Command control input (TTL compatible). CO specifies whether the MPU is accessing the address register (logical zero) or the color palettes (logical one). DO-D4 Data bus (TTL compatible). Data is transferred into and out of the device over this 5-bit bidirectional data bus. DO is the least significant bit. P3 OLO P2 OLI PI BLANK· FO SYNC· CLOCK PSADlUST VAA COMP GND VAA D4 GND 03 lOR 02 lOG 01 lOB DO GND RD' WR' Figure 4. es' eo 28-pin CERDIP Package. RAMDACs 4 - 13 - Bt450 PC Board Layout Considerations PC Board Considerations Power Planes This product requires special attention to proper layout techniques to achieve optimum performance. Before beginning PCB layout, refer to the CMOS RAMDAC layout example found in Bt4511718 A separate digital and analog power plane is necessary. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt450 power pins, any reference circuitry, and COMP and reference decoupling. There should be at least a 1/8 inch gap between the digital power plane and the analog power plane. Evaluation Module Operation and Measurements, application note (AN-16). This application note can be found in Brooktree's 1990 Applications Handbook. The layout should be optimized for lowest noise on the Bt450 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. A well-designed power distribution network is critical to eliminating digital switching noise. Ground planes must provide a low.impedance return path for the digital circuits. A minimum of a 4-layer PC board is recommended with layers 1 (top) and 4 (bottom) for signals and layers 2 and 3 for power and ground. The optimum layout enables the Bt450 to be located as close to the power supply connector and as close to the video output connector as possible. Ground Planes For optimum performance, a common digital and analog ground plane with tub isolation (at least a 1/8 inch gap) and connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector to preserve digital noise margins during MPU read cycles. Thus, the ground tub isolation technique is constrained by the noise margin degradation during digital readback of the Bt450. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. The analog ground plane should include all Bt450 ground pins, all reference circuitry and decoupling (external reference if used, RSET resistors, etc.), power supply bypass circuitry for the Bt450, analog output traces, and the video output connector. 4 - 14 SECTION 4 The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 4. This bead should be located within 3 inches of the Bt450 and provides resistance to switching currents, acting as a resistance at high frequencies. A low resistance bead should be used, such as Ferroxcube 5659064-3B, Fair-Rite 2743001111, or TKD BF45-4001. Plane-to-plane noise coupling can be reduced by ensuring that portions of the digital power and ground planes do not overlay portions of the analog power and ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. Device Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Power Supply Decoupling Best power supply decoupling performance is obtained with a 0.1 IlF ceramic capacitor decoupling each of the two groups of VAA pins to GND. For operation above 75 MHz, a 0.1 IlF capacitor in parallel with a 0.001 IlF chip capacitor is recommended. The capacitors should be placed as close as possible to the device. The 10 IlF capacitor is for low-frequency power supply ripple; the 0.1 IlF capacitors are for high-frequency power supply noise rejection. Bt450 PC Board Layout Considerations (continued) A linear regulator to filter the analog power supply is recommended if the power supply noise is ~ 200 mV or greater than 10 LSBs. This is especially important when a switching power supply is used and the switching frequency is close to the raster scan frequency. Note that about 10% of power supply hum and ripple noise less than 1 MHz will couple onto the analog outputs. COMP Decoupling The COMP pin must be decoupled to VAA, typically using a 0.1 ~F ceramic chip capacitor. Low-frequency supply noise will require a larger value. Lead lengths should be minimized for best performance, so that the self-resonance frequency is greater than the LD* frequency. Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge speeds (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals. Ensure that the power pins for the clock driver are properly decoupled to minimize transients. Minimize edge speeds and ringing, using damping resistors (10-50 Q) or parallel termination where necessary. If using parallel termination on digital signals, the resistors should be connected to the digital power and ground planes, not the analog power and ground planes. Analog Signal Interconnect If the display has a "ghosting" problem, additional capacitance in parallel with the COMP capacitor may helpto fix the problem. The Bt450 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. Digital Signal Interconnect The digital inputs to the Bt450 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power and ground planes. Most noise on the analog outputs will be caused by excessive edge speeds (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The digital edge speeds should be no faster than necessary, as feedthrough noise is proportional to the digital edge speeds. Lower speed applications will benefit from using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission line mismatch will exist if the line length reflection time is greater than 1/4 the signal edge time, resulting in ringing, overshoot, and undershoot that can generate noise onto the analog outputs. Line termination or reducing the line length is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (10-50 Q). The video output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. For maximum performance, the analog outputs should have a source load resistor equal to the destination termination (via a clean isolated ground return path). The load resistor connection between the current output and GND should be as close as possible to the Bt450 to minimize reflections. Unused analog outputs should be connected to GND. Analog edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce high-frequency energy, benefiting EMI and noise reduction. Analog Output Protection The Bt450 analog outputs should be protected against high energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figure 4 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 parts are low-capacitance, fastswitching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7oo1). RAMDACs 4· 15 .. Bt450 PC Board Layout Considerations (continued) ANALOOPOWERPLANB Ll ..... _...n'Yr~.,. ___ cs + + 5V (VCC) Cl Bt4S0 ~_~_~",~",,,_~,,, Rl R2 _ _ _ _ _" _ _ _ _" _ _ _ _ GROIDID R3 FS ADJUST lOR TO VIDOO lOG CONNBCrOR lOB VAA 0 lN4l4819 DAC OllTPUl' TO MONITOR lN4l48 19 GND Location Description CI-C4 C5 Ll Rl. R2. R3 0.1 IJF ceramic capacitor 10 IlF tantalwn capacitor ferrite bead 75 n 1% metal film resistor 499 n 1% metal film resistor RSEf Vendor Part Nwnber Erie RPEII2Z5U104M50V Mallory CSR13G106KM Fair-Rite 2743001111 Dale CMF-55e Dale eMF-55e Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the Bt450. Figure 4. 4 - 16 SECTION 4 Substitution of devices with similar Typical Connection Diagram and Parts List. Bt450 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load FS ADJUST Resistor Symbol Min Typ Max Units VAA TA RL RSEf 4.75 0 5.00 5.25 +70 Volts ·C Oluns Oluns 37.5 499 .. Absolute Maximum Ratings Parameter Max Units 7.0 Volts VAA + 0.5 Volts +125 +150 ·C ·C +175 +150 ·C ·C TSOL 260 ·C TVSOL 220 ·C Symbol Min Typ VAA (measured to GND) Voltage on Any Signal Pin* Analog Output Short Circuit Duration to Any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature Ceramic Package Plastic Package Soldering Temperature (5 seconds, 1/4" from pin) Vapor Phase Soldering (1 minute) GND-O.5 ISC TA 'IS TJ indefinite -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. RAMDACs 4 - 17 Bt450 DC Characteristics Parameter Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Vin = 2.4 V) Digital Outputs Output High Voltage (IOH = -400 J.lA) Output Low Voltage (IOL = 3.2 rnA) 3-State Current Output Capacitance Analog Outputs Gray Scale Current Range Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Blank Level on lOR, lOB Blank Level on lOG Sync Level on lOG LSB Size DAC to DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT =0 rnA) Power Supply Rejection Ratio (COMP = 0.1 J.lF, f = 1 KHz) Symbol Min Typ Max Units 4 4 4 Bits ±lIS LSB LSB % GrayScale 1L II. ±1/16 ±l0 guaranteed Binary VIH VlL IIH 2.0 GND-O.5 VAA+0.5 O.S 10 -10 IlL CIN Val Volts 2.4 VOL 0.4 PSRR Volts IJA pF 20 16.81 15.86 0.95 -10 6.29 -10 VOC RAOUl' CAOUl' IJA IJA pF 10 IOZ COOUl' Volts Volts 19.05 17.62 1.44 5 7.62 5 1.175 2 -1.0 20 rnA 21.30 19.40 1.90 50 S.96 50 rnA rnA rnA IJA +1.4 rnA % Volts kil pF 0.5 %1%tJ.VAA 10 30 0.2 IJA rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 499 il. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 4 - 18 SECTION 4 Bt450 AC Characteristics Parameter Symbol Minrryp/ Max Fmax max 66 50 30 MHz CS*, CO Setup Time CS*, CO Hold Time I 2 min min 35 35 35 35 35 35 ns ns RD*, WR* High Time RD* Asserted to Data Bus Driven RD* Asserted to Data Valid RD* Negated to Data Bus 3-Stated WR*LowTime 3 4 5 6 7 min min max max min 25 4 100 30 50 25 4 100 30 50 25 4 100 30 50 ns ns ns ns ns Write Data Setup Time Write Data Hold Time 8 9 min min 35 10 35 10 35 10 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 10 11 min min 5 2 5 2 10 5 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time 12 13 14 min min min 15.1 5.8 5.8 20 7 7 33.3 10 10 ns ns ns Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time Clock and Data Feedthrough* Glitch Impulse* DAC-to-DAC Crosstalk Analog Output Skew 15 16 17 typ max max typ typ typ typ max 15 7 20 -30 50 -25 0 2 15 7 20 -30 50 -25 0 2 25 7 25 -30 50 -25 0 2 ns ns ns Pipeline Delay 18 2 2 2 Clocks VAA Supply Current** IAA 175 220 140 175 110 135 rnA rnA Clock Rate typ max Units - dB pV-sec dB ns ns Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 499 Q. TTL input values are 0-3 V, with input rise/fall times ~ 4 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ~ 10 pF, DO-D4 output load ~ 130 pF. See timing notes in Figure 6. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the digital inputs have a 1 ill resistor to GND and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 2x clock rate. **At Fmax. IAA (typ) at VAA = 5.0 V. IAA (max) at VAA = 5.25 V. RAMDACs 4 • 19 Bt450 Timing Waveforms I CS·, co 2_ ~ - VALID 7 RD·, WR* 3 S - 4 L DO· D4 (READ) DATA OUT (RD' = 0) ...... f DO· D4 (WRlTI!) Figure 5. J-6 I /' DATA IN (WR' =0) 8 -- i-- 9 MPU Read/Write Timing Dimensions. 12 18 CLOCK PO • P3, OLD, OLi, SYNC·, BLANK- 11 lOR, lOG, lOB --------------------------------------------~---1l__16 Note 1: Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition, Note 2: Settling time measured from the 50% point of full-scale transition to the output remaining within ±l/S LSB, Note 3: Output rise/fall time measured between the 10% and 90% points of full-scale transition. Figure 6. 4 - 20 ~ SECTION 4 Video Input/Output Timing. Bt450 Ordering Information Model Number Speed Package Ambient Temperature Range Bt450KC66 66 MHz 28-pin 0.6" O· to +70· C CERDIP Bt450KC50 50 MHz O· to +70· C 28-pin 0.6" CERDIP Bt450KC30 30 MHz 28-pin 0.6" O· to +70· C CERDIP .. Device Circuit Data Bt450 -~'---'---4IIt-- VAA GO·G7 lOG SYNC· RL C(stray + load) (IOGONLy) Equivalent Circuit of the Current Output (lOG). RAMDACs 4 • 21 Bt450 Revision History Datasheet Revision Change from Previous Revision E 70 MHz speed grade replaced with 66 MHz. AC parameters: Clock Cycle Time (66 MHz) changed from 14.3 ns to 15.1 ns. F Expanded PCB layout section. G Changed 35 MHz operation to 30 MHz. RD* Asserted to Data Bus Driver changed from 10 ns to 4 ns. Pixel and Control Setup time changed to 5 ns for 66 MHz and 30 MHz operation. 4 • 22 SECTION 4 Bt451 Bt457 Bt458 Distinguishing Features Applications • • • • • • • • • High-Resolution Color Graphics 165, 125, 110, 80 MHz Operation 4:1 or 5:1 Input MUX 256-Word Dual Port Color Palette 4 Dual Port Overlay Registers RS-343A Compatible Outputs Bit Plane Read and Blink Masks Standard MPU Interface 84-pin PLCC or PGA Package +5 V CMOS Monolithic Construction 125 MHz / 165 MHz Monolithic CMOS 256 Color Palette RAMDAC™ • CAE/CAD/CAM Image Processing Video Reconstruction Related Products Product Description • Bt431, Bt438, Bt439 • Bt459, Bt460, Bt462, Bt468 The Bt451, Bt457, and Bt458 are pin-compatible _ and software-compatible RAMDACs designed specifically for high-performance, highresolution color graphics. The architecture enables the display of 1280 x 1024 bit-mapped color graphics (up to 8 bits per pixel plus up to 2 bits of overlay information), minimizing the use of costly ECL interfacing, as most of the high speed (pixel clock) logic is contained on chip. The multiple pixel ports and internal multiplexing enable TTL-compatible interfacing (up to 32 MHz) to the frame buffer, while maintaining the 165 MHz video data rates required for sophisticated color graphics. Functional Block Diagram FS ADJUST VR1!F L_..v'rT-COMP IOR(NJC) 1'0.1'7 (A.E) The Bt451 has a 256 x 12 color lookup table with triple 4-bit video D/A converters. lOO(lOtrr) The Bt458 contains a 256 x 24 color lookup table with triple 8-bit video D/A converters. OLO·OLI (A.E) IOB(PLL) SYNC" The B t457 is a single-channel version of the Bt458 and has a 256 x 8 color lookup table with a single 8-bit video D/A converter. It includes a PLL output to enable sub-pixel synchronization of mUltiple Bt457s. CR· R/W 01 Cl On-chip features include programmable blink rates, bit plane masking and blinking, color overlay capability, and a dual-port color palette DO·D7 RAM. Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121-2790 (619) 452-7580· (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 lA58001 Rev. K 4 - 23 Bt451/457/458 Circuit Description MPU Interface address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. Note that the Bt451 uses only the four most significant bits of color data (04-07) and ignores 00-03. As illustrated in the functional block diagram, the Bt451/457/458 supports a standard MPU bus interface, allowing the MPU direct access to the internal control registers and color/overlay palettes. The dual-port color palette RAM and dual-port overlay registers allow color updating without contention with the display refresh process. To read color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be read. The MPU performs three successive read cycles (red, green, and blue), using CO and Cl to select either the color palette RAM or overlay registers. Following the blue read cycle, the address register increments to the next location, which the MPU may read by simply reading another sequence of red, green, and blue data. Note that the B t451 outputs only 4 bits of color data onto 04-07 and forces DO-03 to a logical zero. As illustrated in Table 1, the CO and Cl control inputs, in conjunction with the internal address register, specify which control register, color palette RAM entry, or overlay register will be accessed by the MPU. The 8-bit address register (AOORO-7) is used to address the internal RAM and registers, eliminating the requirement for external address multiplexers. AOORO corresponds to DO and is the least significant bit. When accessing the color palette RAM, the address register resets to $00 after a blue read or write cycle to location $FF. When accessing the overlay registers, the address register increments to $04 following a blue read or write cycle to overlay register 3. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits that count modulo three. They are reset to zero when the MPU reads or writes to the address register. The MPU does not have access to these bits. The other 8 bits of the address register (AOORO-7) are accessible to the MPU. Bt4511458 Reading/Writing Color Data To write color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be modified. The MPU performs three successive write cycles (red, green, and blue), using CO and Cl to select either the color palette RAM or overlay registers. During the blue write cycle, the 3 bytes of color information are concatenated into a 24-bit word (12-bit word for the B t451) and written to the location specified by the AOOR0-7 Cl CO Addressed by MPU $xx $OO-,$FF $00 $01 $02 $03 $04 $05 $06 $07 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 address register color palette RAM overlay co lor 0 overlay color 1 overlay color 2 overlay color 3 read mask register blink mask register command register control/test register Table 1. 4·24 SECTION 4 Address Register (ADDR) Operation. Bt451/457/458 Circuit Description (continued) BI457 Reading/Writing Color Data (Normal Mode) To write color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be modified. The MPU performs a color write cycle, using CO and CI to select either the color palette RAM or the overlay registers. The address register then increments to the next location, which the MPU may modify by simply writing another color. Reading color data is similar to writing, except the MPU executes read cycles. This mode is useful if a 24-bit data bus is available, as 24 bits of color information (8 bits each of red, green, blue) may be read or written to three Bt457s in a single MPU cycle. In this application, the CE* inputs of all three Bt457s are connected together. If only an 8-bit data bus is available, the CE* inputs must be individually selected during the appropriate color write cycle (red CE* during red write cycle, blue CE* during blue write cycle, etc.). When accessing the color palette RAM, the address register resets to $00 after a read or write cycle to location $FF. When accessing the overlay registers, the address register increments to $04 following a read or write cycle to overlay register 3. Bt457 Reading/Writing Color Data (RGB Mode) To write color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using CO and CI to select either the color palette RAM or the overlay registers. After the blue write cycle, the address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. Reading color data is similar to writing, except the MPU executes read cycles. This mode is useful if only an 8-bit data bus is available. Each Bt457 is programmed to be a red, green, or blue RAMDAC, and will respond only to the assigned color read or write cycle. In this application, the Bt457s share a common 8-bit data bus. The CE * inputs of all three B t457 s must be asserted simultaneously only during color read/write cycles and address register write cycles. When accessing the color palette RAM, the address register resets to $00 after a blue read or write cycle to location $FF. When accessing the overlay registers, the address register increments to $04 following a blue read or write cycle to overlay register 3. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits that count modulo three. They are reset to zero when the MPU reads or writes to the address register. The MPU does not have access to these bits. The other 8t bits of the address register (ADDRO-7) are accessible to the MPU. Additional Information Although the color palette RAM and overlay registers are dual-ported, if the pixel and overlay data is addressing the same palette entry being written to by the MPU during the write cycle, it is possible for one or more of the pixels on the display screen to be disturbed. A maximum of one pixel is disturbed if the write data from the MPU is valid during the entire chip enable time. Accessing the control registers is also done through the address register in conjunction with the CO and CI inputs, as shown in Table 1. All control registers may be written to or read by the MPU at any time. The address register does not increment following read or write cycles to the control registers, facilitating read-modify-write operations. Note that if an invalid address is loaded into the address register, data written to the device will be ignored and invalid data will be read by the MPU. RAMDACs 4· 2S .. Bt451/457/458 Circuit Description (continued) Frame Buffer Interface To enable pixel data to be transferred from the frame buffer at TTL data rates, the Bt451/457/458 incorporate internal latches and multiplexers. As illustrated in Figure I, on the rising edge of LD*, sync and blank information, color (up to 8 bits per pixel), and overlay (up to 2 bits per pixel) information, for either four or five consecutive pixels, are latched into the device. Note that, with this configuration, the sync and blank timing will be recognized only with four- or five-pixel resolution. Typically, the LD* signal is used to clock external circuitry to generate the basic video timing. Each clock cycle, the Bt451!457/458 outputs color information based on the (A) inputs, followed by the (B) inputs, etc., until all four or five pixels have been output, at which point the cycle repeats. The overlay inputs may have pixel tlmmg, facilitating the use of additional bit planes in the frame buffer to control overlay selection on a pixel basis, or they may be controlled by external character or cursor generation logic. To simplify the frame buffer interface timing, LD* may be phase shifted, in any amount, relative to CWCK. This enables the LD* signal to be derived by externally dividing CLOCK by four or five, independent of the propagation delays of the LD* generation logic. As a result, the pixel and overlay data are latched on the rising edge of LD*, independent of the clock phase. Internal logic maintains an internal LOAD signal, synchronous to CLOCK, and is guaranteed to follow the LD* signal by at least one, but not more than four, clock cycles. This LOAD signal transfers the latched pixel and overlay data into a second set of latches, -,vhich are then internally multiplexed at the pixel clock rate. If 4: 1 multiplexing is specified, only one rising edge of LD* should occur every four clock cycles. If 5: 1 multiplexing is specified, only one rising edge of LD* should occur every five clock cycles. Otherwise, the internal LOAD generation circuitry assumes it is not locked onto the LD* signal, and will continuously attempt to resynchronize itself to LD*. !D' po.P7 (A-E), m.o-OLi (A-E). SYNC·, BLANK. lOR, lOG. lOB (lOUT -- BT457) aocK Figure I. 4 - 26 . SECTION 4 Video Input/Output Timing. Bt451/457/458 Circuit Description (continued) Color Selection Video Generation Each clock cycle, 8 bits of color infonnation (PO-P7) and 2 bits of overlay infonnation (OLD, OLl) for each pixel are processed by the read mask, blink mask, and command registers. Through the use of the control registers, individual bit planes may be enabled or disabled for display, and/or blinked at one of four blink rates and duty cycles. Every clock cycle, the selected color information from the color palette RAMs or overlay registers is presented to the D/A converters. The SYNC* and BLANK* inputs, pipelined to maintain synchronization with the pixel data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figure 2. To ensure that a color change due to blinking does not occur during the active display time (i.e., in the middle of the screen), the Bt451/457/458 monitors the BLANK* input to determine vertical retrace intervals. A vertical retrace interval is recognized by determining that BLANK* has been a logical zero for at least 256 LD* cycles. The varying output current from each of the D/A converters produces a corresponding voltage level, which is used to drive the color CRT monitor. Note that only the green output (100) on the Bt451 and Bt458 contains sync information. Table 3 details how the SYNC* and BLANK* inputs modify the output levels. The processed pixel data is then used to select which color palette entry or overlay register is to provide color information. Note that PO is the LSB when addressing the color palette RAM. Table 2 illustrates the truth table used for color selection. The D/A converters on the Bt45I, Bt457, and Bt458 use a segmented architecture in which bit currents are routed to either the current output or OND by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current-steering their outputs. An on-chip operational amplifier stabilizes the D/A converter's full scale output current against temperature and power supply variations. CR6 OLI OLO PO-P7 Addressed by frame buffer I I 0 0 : 0 0 0 I I 0 0 : 0 0 $00 $01 color palette entry $00 color palette entry $01 : color palette entry $FF overlay color 0 overlay color I overlay color 2 overlay color 3 : 1 0 x x x Table 2. I 0 I : $FF $xx $xx $xx $xx Palette and Overlay Select Truth Table. RAMDACs 4 - 27 Bt451/457/458 Circuit Description (continued) lOR. lOB lOG (IOIlT) MA v 19.05 0.714 1f>.~ 1.000 -,---~It"""-----------~::-----WHrmLBVEL 1.44 0.054 9.05 0.340 ~------+-----4~--------BUCKLEVEL 0.00 0.000 7.62 0.286 MA V ______.a.........,._.,........L_________ BLANK LBVEL 7.5 IRE ~ 40 IRE 0.00 0.000 -L-------------~_.a.... Note: 75 n doubly terminated load, RSET assumed on all levels. Figure 2. Description WHITE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC = 523 n, VREF _______________ SYNCLBVa = 1.235 V. Composite Video Output Waveforms. lOG (lOUf) IOR,IOB (rnA) (rnA) 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 19.05 data + 1.44 data + 1.44 1.44 1.44 0 0 SYNC* BLANK.* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: Typical with full-scale lOG = 26.67 rnA. RSET = 523 uses only the upper four DAC input data bits. Table 3. 4 - 28 SECTION 4 RS-343A levels and tolerances n, VREF = 1.235 V. Note that the Bt451 Video Output Truth Table. Bt451/457/458 Internal Registers Command Register The command register may be written to or read by the MPU at any time, and is not initialized. CRO corresponds to data bus bit DO. CR1 MUltiplex select (0) 4: 1 multiplexing (1) 5: 1 multiplexing This bit specifies whether 4: 1 or 5: 1 multiplexing is to be used for the pixel and overlay inputs. If 4: 1 is specified, the (E) pixel and (E) overlay inputs are ignored and should be connected to GND, and the LD* input should be 1/4 the CLOCK rate. If 5:1 is specified, all of the pixel and overlay inputs are used, and the LD* input should be 1/5 the CLOCK rate. Note that it is possible to reset the pipeline delay of the Bt451/458 to a fixed eight clock cycles. In this instance, each time the input multiplexing is changed, the B t451 /458 must again be reset to a fixed pipeline delay. CR6 RAM enable (0) use overlay color 0 (1) use color palette RAM CR5, CR4 Blink rate selection (00) 16 on, 48 (01) 16 on, 16 (10) 32 on, 32 (11) 64 on, 64 CR3 off (25{75) off (50/50) off (50/50) off (50/50) OLl blink enable (0) disable blinking (1) enable blinking CR2 OLO blink enable (0) disable blinking (1) enable blinking When the overlay select bits are 00, this bit specifies whether to use the color palette RAM or overlay color 0 to provide color information. These 2 bits control the blink rate cycle time and duty cycle, and are specified as the number of vertical retrace intervals. The numbers in parentheses specify the duty cycle (% On/off). If a logical one, this bit forces the OLl (A-E) inputs to toggle between a logical zero and the input value at the selected blink rate prior to selecting the palettes. A value of logical zero does not affect the value of the OLl (A-E) inputs. In order for overlay 1 bit plane to blink, bit CRI must be set to a logical one. If a logical one, this bit forces the OLO (A-E) inputs to toggle between a logical zero and the input value at the selected blink rate prior to selecting the palettes. A value of logical zero does not affect the value of the OLO (A-E) inputs. In order for overlay 0 bit plane to blink, bit CRO must be set to a logical one. RAMDACs 4 - 29 - Bt451/457/458 Internal Registers (continued) Command Register (continued) CR1 OLl display enable (0) disable (1) enable CRO OLO display enable (0) disable (1) enable If a logical zero, this bit forces the OL1 (A-E) inputs to a logical zero prior to selecting the palettes. A value of a logical one does not affect the value of the OLl (A-E) inputs. If a logical zero, this bit forces the OLO (A-E) inputs to a logical zero prior to selecting the palettes. A value of a logical one does not affect the value of the OLO (A-E) inputs. Read Mask Register The read mask register is used to enable (logical one) or disable (logical zero) a bit plane from addressing the color palette RAM. DO corresponds to bit plane 0 (PO (A-E) and 07 corresponds to bit plane 7 (P7 (A-E)). Each register bit is logically ANDed with the corresponding bit plane input. This register may be written to or read by the MPU at any time and is not initialized. Blink Mask Register The blink mask register is used to enable (logical one) or disable (logical zero) a bit plane from blinking at the blink rate and duty cycle specified by the command register. 00 corresponds to bit plane 0 (PO (A-E) and 07 corresponds to bit plane 7 (P7 (A-E)). In order for a bit plane to blink, the corresponding bit in the read mask register must be a logical one. This register may be written to or read by the MPU at any time and is not initialized. 4 • 30 SECTION 4 Bt451/457/458 Internal Registers (continued) Bt451/458 Test Register The test register provides diagnostic capability by enabling the MPU to read the inputs to the 0/A converters. It may be written to or read by the MPU at any time. and is not initialized. When writing to the register. the upper 4bits (04-07) are ignored. The contents of the test register are defined as follows: 07-04 color information (4 bits of red. green. or blue) D3 low (logical one) or high (logical zero) nibble blue enable green enable red enable D2 D1 DO To use the test register. the host MPU writes to it. setting one. and only one. of the (red, green, blue) enable bits. These bits specify which 4 bits of color information the MPU wishes to read (RO-R3. GO-G3. BO-B3. R4-R7. G4-G7. or B4-B7). When the MPU reads the test register. the 4 bits of color information from the OAC inputs are contained in the upper 4 bits. and the lower 4 bits contain the (red. green. blue. low or high nibble) enable information previously written. Note that either the CLOCK must be slowed down to the MPU cycle time. or the same pixel and overlay data must be presented to the device during the entire MPU read cycle. For example. to read the upper 4 bits of red color information being presented to the 0/A converters. the MPU writes to the test register. setting only the red enable bit. The MPU then proceeds to read the test register. keeping the pixel data stable. which results in 04-07 containing R4-R7 color bits, and DO-03 containing (red. green. blue. low or high nibble) enable information. as illustrated below: D7 D6 05 04 R7 R6 R5 R4 D3 0 D2 0 D1 DO 0 Note that since the Bt451 has 4-bit O/A converters. bit 03 of the test register will always be a logical zero. RAMDACs 4 - 31 .. Bt451/457/458 Internal Registers (continued) Bt457 Control/Test Register The control/test register provides diagnostic capability by enabling the MPU to read the inputs to the D/A converter. It may be written to or read by the MPU at any time, and is not initialized. When writing to the register, the upper 4 bits (04-D7) are ignored. The contents of the test register are defined as follows: D7-04 color information D3 D2 low (logical one) or high (logical zero) nibble blue channel enable green channel enable red channel enable D1 DO To use the control/test register, the MPU writes to it, specifying the low or high nibble of color information. When the MPU reads the register, the 4 bits of color information from the DAC inputs are contained in the upper 4 bits, and the lower 4 bits contain whatever was previously written to the register. Note that either the CLOCK must be slowed down to the MPU cycle time, or the same pixel and overlay data must be presented to the device during the entire MPU read cycle. The red, green, and blue enable bits are used to specify the mode of writing color data to, and reading color data from, the Bt457. If all three enable bits are a logical zero, each write cycle to the color palette RAM or overlay registers loads 8 bits of color data. During each read cycle of the color palette RAM or overlay registers, 8 bits of color data are output onto the data bus. If a 24-bit data bus is available, this enables three Bt457s to be accessed simultaneously. If any of the red, green, blue enable bits are a logical one, the Bt457 assumes the MPU is reading and writing color information using red, green, blue cycles, such as are used on the Bt451 and Bt458. Setting the appropriate enable bit configures the Bt457 to output or input color data only for the color read/write cycle corresponding to the enabled color. Thus, if the green enable bit is a logical one, and a red, green, blue write cycle occurred, the Bt457 would input data only during the green write cycle. If a red, green, blue read cycle occurred, the Bt457 would output data only during the green read cycle. Note that CE* must be a logical zero during each of the red, green, blue cycles. One, and only one, of the enable bits must be a logical one. This mode of operation is useful where only an 8-bit data bus is available, and the software drivers are written for RGB operation. 4 - 32 SECTION 4 Bf"Od{treeQp Bt451/457/458 Pin Descriptions Pin Name Description BlANK* Composite blank control input (TIL compatible). A logic zero drives the analog outputs to the blanking level, as illustrated in Table 3. It is latched on the rising edge of LD*. When BLANK* is a logical zero, the pixel and overlay inputs are ignored. SYNC* Composite sync control input (TIL compatible). A logical zero on this input switches off a 40 IRE current source on the lOG output (see Figure 2). SYNC* does not override any other control or data input, as shown in Table 3; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of LD*. If sync information is not to be generated on the lOG output, this pin should be connected to GND. Load control input (TIL compatible). The PO-P7 {A-E}, OLO-OLI {A-E}, BLANK*, and SYNC* inputs are latched on the rising edge of LD*. LD*, while it is either 1/4 or 1/5 the CLOCK rate, may be phase independent of the CLOCK and CLOCK* inputs. LD* may have any duty cycle, within the limits specified by the AC Characteristics section. PO-P7 {A-E} Pixel select inputs (TTL compatible). These inputs are used to specify, on a pixel basis, which one of the 256 entries in the color palette RAM is to be used to provide color information. Either four or five consecutive pixels (up to 8 bits per pixel) are input through this port. They are latched on the rising edge of LD*. Unused inputs should be connected to GND. Note that the {A} pixel is output first, followed by the {B} pixel, etc., until all four or five pixels have been output, at which point the cycle repeats. OLO-OLI {A-E} Overlay select inputs (TIL compatible). These control inputs are latched on the rising edge of LD*, and in conjunction with bit 6 of the command register, specify which palette is to be used for color information, as follows: bLl OLO CR6= 1 0 0 1 1 0 1 0 1 color palette RAM overlay color 1 overlay color 2 overlay color 3 CR6=0 overlay overlay overlay overlay color color color color 0 1 2 3 When accessing the overlay palette, the PO-P7 {A-E} inputs are ignored. Overlay information bits (up to 2 bits per pixel) for either four or five consecutive pixels are input through this port. Unused inputs should be connected to GND. lOR, lOG, lOB, lour PlL Red, green, and blue video current outputs. These high -mpedance current sources are capable of directly driving a doubly terminated 75 il coaxial cable (Figure 3). The Bt457 outputs lOUT rather than lOR, lOG, and lOB. Phase lock loop current output-Bt457 only. This high-impedance current source is used to enable multiple Bt457s to be synchronized with sub-pixel resolution when used with an external PLL. A logical one on the BLANK* input results in no current being output onto this pin, while a logical zero results in the following current being output: PLL (mA) = 3,227 * VREF ( V) / RSET (il) If sub-pixel synchronization of mUltiple devices is not required, this output should be connected to GND (either directly or through a resistor up to 150 il). RAMDACs 4·33 Bt451/457/458 Pin Descriptions (continued) Pin Name Description COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 I1F ceramic capacitor must be connected between this pin and VAA (Figure 3). Connecting the capacitor to V AA rather than to GND provides the highest possible power supply noise rejection. The CaMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum and maximize the capacitor's self-resonant frequency to be greater than the LO* frequency. Refer to PC Board Layout Considerations for critical layout criteria. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal (Figure 3). Note that the IRE relationships in Figure 2 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on lOG (or lOur for the Bt457) is: RSET (.0) = 11,294 '" VREF ( V) I lOG (rnA) The full scale output current on lOR and lOB (for the Bt451 and Bt458) for a given RSET is: lOR, lOB (rnA) = 8,067 '" VREF ( V) I RSET (.0) VREF Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 3, must supply this input with a 1.235 V (typical) reference. The use of a resistor network to generate the reference is not recommended, as any low-frequency power supply noise on VREF will be directly coupled onto the analog outputs. A 0.1 I1F ceramic capacitor is used to decouple this input to V AA, as shown in Figure 3. If V AA is excessively noisy, better performance may be obtained by decoupling VREF to GND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. CLOCK, Clock inputs. These differential clock inputs are designed to be driven by ECL logic configured for single supply (+5 V) operation. The clock rate is typically the pixel clock rate of the system. CLOCK'" CE'" Chip enable control input (ITL compatible). This input must be a logical zero to enable data to be written to or read from the device. During write operations, data is internally latched on the rising edge of CE"'. Care should be taken to avoid glitches on this edge-triggered input. R/W Read/write control input (TTL compatible). To write data to the device, both CE'" and R/W must be a logical zero. To read data from the device, CE'" must be a logical zero and R/W must be a logical one. R/W is latched on the falling edge of CE"'. CO,Cl Command control inputs (TTL compatible). CO and Cl specify the type of read or write operation being performed, as illustrated in Table 1. They are latched on the falling edge of CE*. 00-07 Oata bus (TTL compatible). Oata is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. VAA Analog power. All VAA pins must be connected. GND Analog ground. All GNO pins must be connected. 4·34 SECTION 4 Bt451/457/458 Pin Descriptions (continued)-84-Pin J-Lead Package w ~ ~ tI ~~~~~~~~~~~~~~9 ~i~~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 1 ~ ; ; $ ~ ~ ~ ~ ~ ~ 51 P4B PSA PSB PSC 49 P5D "n P2A PlB PlD PIC PlB PIA $1 48 P5B 47 P6A POD ~ PIIB POe POB 4S of4 PIID POA 43 PIIB OUB OLID OLIC OLIB OLlA aLOE 4Z 41 P7A P7B P7C P7D P7B 11 VAA OLOD 36 GND POE 40 39 38 OLOC 311 VAA OLOB 34 GND 33 VRBF OLOA ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 8 Q a8 aE8 S § ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 8 0 ~ ~ ~ 00> ~ ~ I8 S~ e g Ie > ~ ~ ~ .. PIIC ~ Note: Bt457 pin names are in parentheses. RAMDACs 4 - 3S BnxKtree® Bt451/457/458 Pin Descriptions (continued)-84-pin PGA Package Signal Pin Signal Number BLANK* 19 SYNC* LD* MIO M9 CLOCK* L8 CLOCK M8 POA POB POC POD POE 01 02 HI K11 L12 K12 III 112 P6A P6B P6C P6D P6E H11 H12 012 011 F12 P7A P7B P7C P7D P7E FH E12 Ell 012 Dll aUlA OUlB OUlC aUlD OUlE Al C2 Bl Cl 11 J2 Kl LI P2A K3 P2B P2C Ml P2D M2 M3 P2E PSA P5B P5C P5D P5E H2 PIA PIB PIC PlO PIE K2 l2 13 Pin Signal Number D2 VAA VAA VAA VAA VAA VAA C12 C11 GND GND GND GND GND B12 Bll M6 B6 A6 COMP FSADJUST VREF A12 BIO CIO P4A P4B P4C P4D P4E lA M4 L5 M5 L6 MH LIO Lll KIO MI2 OLlA OLIB OLIC OLlD OLlE lOG (IOUI') IOB(PLL) IOR(NfC) Note: Bt457 pin names are in parentheses. 4·36 SECTION 4 01 E2 El Fl F2 AlO All B9 A9 L7 M7 A7 CE* AS R/W B8 Cl CO B7 DO 01 P3A P3B P3C P3D P3E Pin Number D2 D3 AS C3 B2 B3 A2 A3 D4 D5 B4 D6 D7 B5 A4 BnxKtree® Bt451/457/458 Pin Descriptions (continued)-84-pin PGA Package 12 CDMP GND VAA PlD P1B PIIIl RiC 11 lOB GND VAA P7Il PIC PIA PID 10 IJG FSADI VREP VAA lOR C1 PIW VAA co GND GND CI!' - PSB P5C PSB I'I4Il P.D P.If. !OIC !'If. PI> I'IB SYNC· But' L\)' Cut' Cut VAA VAA P'JE GND 01 PJC P.I) Il6 D5 P.If. P.!B D4 D2 DO P2A P1JC Pm D3 DI 0l.III QUE ILlB CL\B EJ OLOC am ILIA ILlC CL\D A B C D B F RiB Bt451/457/458 (TOP VIEW) FOB PID P1It. P1D PlB I'D FOe PIll PlB PIC P2B K L M G H RiC PIIIl PlB PlD VAA GND row PID PIA PIC P7Il VAA GND lOB VREP FSADI IJG alignment marker (on top) - 12 I'IB PSB P5C PSB 11 I'IA !OIC P.If. P.D 10 SYNC· I'IB PI> L\)' But' lOR VAA Cut CLK' PIW CI VAA VAA co VAA GND PJB GND GND P.I) PJC 01 CI!' PJB P.If. D5 Il6 Pm P2C P2A DO D2 D4 I'D PlB P1D P1It. PID P2B PIC PlB PIll FOe M L K 2 RiB (BOTTOM VIEW) H roB G CL\B OLlB QUE OLOII DI D3 CL\D ILlC ILIA am 0l.0C f3 F B D C B A Pin Bt451/458 Bt457 AIO A11 100 lOB lOR lour B9 PI.L N/C RAMDACs 4· 37 Bt451/457/458 PC Board Layout Considerations PC Board Considerations Power Planes This product requires special attention to proper layout techniques to achieve optimum performance. Before beginning PCB layout, refer to the CMOS RAMDAC layout example found in Bt45114571458 Evaluation Module Operation and Measurements, application note (AN -16). This application note can be found in Brooktree's 1990 Applications Handbook. Separate digital and analog power planes are necessary. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt451/457/458 power pins, VREF circuitry, and COMP and VREF decoupling. There should be at least a lI8-inch gap between the digital power plane and the analog power plane. The layout should be optimized for lowest noise on the Bt451/457/458 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 3. This bead should be located within 3 inches of the Bt451/457/458 and provides resistance to switching currents, acting as a resistance at high frequencies. A low resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. A well-designed power distribution network is critical to eliminating digital switching noise. Ground planes must provide a low-impedance return path for the digital circuits. A minimum of a 6-layer PC board is recommended. The ground layer should be used as a shield to isolate noise from the analog traces with layer 1 (top) the analog traces, layer 2 the ground plane (preferable analog ground plane), layer 3 the analog power plane, using the remaining layers for digital traces and digital power supplies. The optimum layout enables the Bt451/457/458 to be located as close to the power supply connector and as close to the video output connector as possible. Ground Planes For optimum performance, a common digital and analog ground plane with tub isolation (at least a 1/8" inch gap) and connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector to preserve digital noise margins during MPU read cycles. Thus, the ground partitioning isolation technique is constrained by the noise margin degradation during digital readback of the Bt451/457/458. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. For maximum performance, a separate isolated ground plane for the analog output termination resistors, RSET resistor, and VREF circuitry should be used, as shown in Figure 3. Another isolated ground plane is used for the GND pins of the Bt451/457/458 and supply decoupling capacitors. 4 - 38 SECTION 4 Plane-to-plane noise coupling can be reduced by ensuring that portions of the digital power and ground planes do not overlay portions of the analog power and ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. Device Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Power Supply DecoupUng Best power supply decoupling performance is obtained with a 0.1 I1F ceramic capacitor in parallel with a 0.01 I1F chip capacitor decoupling each of three groups of VAA pins to GND. The capacitors should be placed as close as possible to the device. The 33 !1F capacitor is for low frequency power supply ripple; the 0.1 I1F and 0.01 I1F capacitors are for high-frequency power supply noise rejection. Bt451/457/458 PC Board Layout Considerations (continued) A linear regulator to filter the analog power supply is recommended if the power supply noise is ~ 200 mY. This is especially important when a switching power supply is used and the switching frequency is close to the raster scan frequency. Note that about 10% of power supply hum and ripple noise less than I MHz will couple onto the analog outputs. COMP Decoupllng The COMP pin must be decoupled to VAA, typically using a 0.1 I1F ceramic capacitor. Low frequency supply noise will require a larger value. Lead lengths should be minimized for best performance so that the self-resonance frequency is greater than the LD* frequency. If the display has a "ghosting" problem, additional capacitance in parallel with the COMP capacitor may helpto fix the problem. Digital Signal Interconnect The digital inputs to the Bt451/457/458 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power and ground planes. Most noise on the analog outputs will be caused by excessive edge speeds (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The digital edge speeds should be no faster than necessary, as feedthrough noise is proportional to the digital edge speeds. Lower speed applications will benefit by using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission line mismatch will exist if the line length reflection time is greater than 1/4 the signal edge time, resulting in ringing, overshoot, and undershoot that can generate noise onto the analog outputs. Line termination or reducing the line length is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (10 to 50 Q). Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge speeds (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals. Ensure that the power pins for the clock driver are properly decoupled to minimize transients. Minimize edge speeds and ringing, using damping resistors (10 to 50 Q) or parallel termination where necessary. If using parallel termination on digital signals, the resistors should be connected to the digital power and ground planes, not the analog power and ground planes. Analog Signal Interconnect The Bt451/457/458 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog outputs should have a source load resistor equal to the destination termination (via a clean isolated ground return path). The load resistor connection between the current output and GND should be as close as possible to the Bt451/457/458 to minimize reflections. Unused analog outputs should be connected to GND. Analog edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce high-frequency energy, reducing EMI and noise. Analog Output Protection The Bt451/457/458 analog outputs should be protected against high-energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figure 3 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 parts are low-capacitance, fastswitching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7001). RAMDACs 4 - 39 .. Bt451/457/458 PC Board Layout Considerations (continued) C9 Ll +5V(VCC) Cl Bt4S1/4S7I4S8 GROUND (I'OWI!R SIlPI'LY CONNBCrOR) Rl R2 R3 PSADJUST (N/C) lOR TO VIDIlO CONNBCrOR (IO\lT)IOO (PIL) lOB NOTE: BT4S7 PIN NAMIlS ARB IN PARENIlIIlSBS. • NOT USIlD wrrn BT4S7. VAA 0 lN4148/9 DAC TO MONITOR 01II'PlIT lN4148/9 OND Location Description CI-C4. C8. C9 C5-C7 CI0 Ll Rl. R2. R3 R4 0.1 IJF ceramic capacitor 0.01 I1F ceramic chip capacitor 33 IJF tantalum capacitor ferrite bead 75 n 1% metal film resistor 1000 n 1% metal film resistor 523 n 1% metal film resistor 1.2 V voltage reference RSET ZI Vendor Part Number Erie RPEl12Z5U104M50V AVX 12102T103QAI018 Mallory CSR13F336K.M Fair-Rite 2743001111 Dale CMF-55C Dale CMF-55C Dale CMF-55C National Semiconductor LM385Z-1.2 Note: The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the Bt4511457/458. R3 not used with Bt457 (see Application Information section). Figure 3. 4·40 SECTION 4 Typical Connection Diagram and Parts List. Bt451/457/458 Application Information Clock Inter/acing Due to the high clock rates at which the Bt451/457/458 may operate, it is designed to accept differential clock signals (CLOCK and CLOCK"). These clock inputs are designed to be generated by ECL logic operating at +5 V. Note that the CLOCK and CLOCK" inputs require termination resistors (typically a 220 Q resistor to VCC and a 330 Q resistor to GND). The termination resistors should be as close as possible to the Bt451/457/458. Typically, LD" is generated by dividing CLOCK by four or five (depending on whether 4:1 or 5:1 mUltiplexing was specified) and translating it to TTL levels. As LD" may be phase-shifted relative to CLOCK, the designer need not worry about propagation delays in deriving the LD" signal. LD" may be used as the shift clock for the video DRAMs and to generate the fundamental video timing of the system (SYNC", BLANK", etc.). 165 MHz applications require robust ECL clock signals with strong pull-down (-20 rnA at VOH) and double termination for clock trace lengths greater than 2 inches. It is recommended that the Bt438 or Bt439 Clock Generator Chips be used to generate the clock and load signals. Both support the 4:1 and 5:1 input mUltiplexing of the Bt451/457/458, and set the pipeline delay of the Bt457 and Bt458 to eight clock cycles. Figures 4 and 5 illustrate using the Bt438 with the Bt451/457/458. The CLOCK and CLOCK" inputs must be differential signals and greater than 0.6 V peak-to-peak due to the noise margins of the CMOS process. The Bt451/457/458 will not function using a single-ended clock with CLOCK" connected to ground. In applications using a single Bt457, the PLL output is ignored and should be connected to GND (either directly or through a resistor up to 150 Q). +5V +5V 220 I. CLOCK CLOCK MONITOR PRODUCTS +5V 330 Bt451f458 9700 220 a..OCK'" CLOCK'" 330 Bt438 LDA LD" VREF VREF lK Figure 4. Generating the Bt4511458 Clock Signals. RAMDACs 4 • 41 .. Bt451/457/458 Application Information (continued) Setting the Pipeline Delay (Bt457, Bt458) The pipeline delay of the Bt457/458, although fixed after a power-up condition, may be anywhere from six to ten clock cycles. The Bt457/458 contains additional circuitry enabling the pipeline delay to be fixed at eight clock cycles. The Bt438 and Bt439 Clock Generator Chips support this mode of operation when used with the Bt457/458. To reset the Bt457/458, it should be powered up, with LD*, CLOCK, and CLOCK* running. Stop the CLOCK and CLOCK* signals with CLOCK high and CLOCK* low for at least three rising edges of LD*. There is no upper limit on how long the device can be held with CLOCK and CLOCK* stopped. Restart CLOCK and CLOCK* so that the first edge of the signals is as close as possible to the rising edge of LD* (the falling edge of CLOCK leads the rising edge of LD* by no more than one clock cycle or follows the rising edge of LD* by no more than 1.5 clock cycles). When restarting the clocks, care must be taken to ensure that the minimum clock pulse width is not violated. The resetting of the B t457/458 to an eight clock cycle pipeline delay does not reset the blink counter circuitry. Therefore, if the multiple Bt457/458s are used in parallel, the on-chip blink counters may not be synchronized. In this instance, the blink mask register should be $00 and the overlay blink enable bits a logical zero. Blinking may be done under software control via the read mask register and overlay display enable bits. In standard operation, the Bt457/458 need be reset only following a power-up or reset condition. Under these circumstances the on-chip blink circuitry may be used. Bt457 Color Display Applications For color display applications where up to four Bt457s are being used, it is recommended that the Bt439 Clock Generator Chip be used to generate the clock and load signals. It supports the 4:1, and 5:1 input mUltiplexing of the Bt457, synchronizes them to sub-pixel resolution, and sets the pipeline delay of the Bt457 to eight clock cycles. The Bt439 may also be used to interface the Bt457 to a TTL clock. Figure 6 illustrates using the Bt439 with the Bt457. +5V f. I. 220 ~ 330 $ CLOCK MONITOR PRODUcrS +5V CLOCK 8t457 9700 220< T CLOCK' 330 Bt438 CLOCK' -j; LDA LD' VAA T .0.1=r VREF v VREF IK Figure 5. 4·42 Generating the Bt457 Clock Signals (Monochrome Application). SECTION 4 Bt451/457/458 Application Information (continued) Sub-pixel synchronization is supported via the PLL output. Essentially. PLL provides a signal to indicate the amount of analog output delay of the Bt457. relative to CLOCK. The Bt439 compares the phase of the PLL signals generated by up to four Bt457s. and adjusts the phase of each of the CLOCK and CLOCK* signals to the Bt457s to minimize the PLL phase difference. There should be minimal layout skew in the CLOCK and PLL trace paths to assure proper clock alignment. If sub-pixel synchronization of multiple Bt457s is not necessary. the Bt438 Clock Generator Chip may be used instead of the Bt439. In this instance. the CLOCK. CLOCK*. and LD* inputs of up to four Bt457s are connected together and driven by a single Bt438 (daisy chain with single balanced termination for <100 MHz or through a 10H116 buffer for >100 MHz). The VREF inputs of the Bt457s must still have a 0.1 I1F bypass capacitor to VAA. The PLL outputs would not be used and should be connected to GND (either directly or through a resistor up to 150 Q) . .. I'lL +sv a.OCK 14 a.OCK' MONITOR PRODUCTS !/7----1-- lOR SYNC'" >----1-- 100 The Bt453 generates RS-343A compatible video signals into a doubly terminated 75 Q load, and RS-170 compatible video signals into a singly terminated 75 Q load, without requiring external buffering_ !SYNC BlANK' >---+--IOB OLD,OLl BUS CONTROL DO-D7 Brooktree Corporation 9950 Barnes Canyon Rd_ San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 IA53001 Rev_ I CS'" RD'" WR* co Cl 4 - 57 Both the differential and linearity errors of the D/A converters are guaranteed to be a maximum of ±1 LSB over the full temperature range. Bt453 Circuit Description MPU Interface As illustrated in the functional block diagram, the Bt453 supports a standard MPU bus interface, allowing the MPU direct access to the color palette RAM and overlay color registers. The MPU interface operates asynchronously to the video data, simplifying the design interface. The CO and CI control inputs specify whether the MPU is accessing the address register, color palette RAM, or the overlay registers, as shown in Table 1. The 8-bit address register is used to address the color palette RAM and overlay registers, eliminating the requirement for external address multiplexers. ADDRO corresponds to DO and is the least significant bit. To write color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using CO and CI to select either the color palette RAM or overlay registers. During the blue write cycle, the three bytes of color information are concatenated into a 24-bit word and written to the location specified by the address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. Note that any time the CS* input is a logical zero, the video outputs are forced to the black level. When accessing the color palette RAM, the address register resets to $00 following a blue read or write cycle to RAM location $FF. While accessing the overlay color registers, the six most significant bits of the address register (ADDR2-7) are ignored. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADDRa, ADDRb) that count modulo three, as shown in Table 2. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The MPU does not have access to these bits. The other 8 bits of the address register (ADDR0-7) are accessible to the MPU, and are used to address color palette RAM locations and overlay registers, as shown in Table 2. Figure I illustrates the MPU read/write timing. To read color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be read. The MPU performs three successive read cycles (8 bits each of red, green, and blue), using CO and CI to select either the color palette RAM or overlay registers. Following the blue read cycle, the address register increments to the next location, which the MPU may read by simply reading another sequence of red, green, and blue data. CI CO Addressed by MPU 0 0 0 I 0 I address register color palette RAM address register overlay registers 1 I Table 1. 4 - 58 SECTION 4 Control Input Truth Table. Bt453 Circuit Description (continued) Value Cl co Addressed by MPU 00 01 10 x x x 1 1 1 red value green value blue value $00 - $FF xxxx xxOO xxxx xxOI xxxx xxl0 xxxx xxll 0 1 1 1 1 1 1 1 1 1 color palette RAM reserved overlay color 1 overlay color 2 overlay color 3 ADDRa, b (counts modulo 3) ADDR0-7 (counts binary) Table 2. cs .., co, Cl RD"', WR'" Address Register (ADDR) Operation. =>< X VALID ! \ < 00· 07 (READ) OATAOUT (RD"= 0) X DO· 07 (WRITIl) Figure 1. DATA IN (WR"',..O) > X MPU Read/Write Timillg. RAMDACs 4 • S9 Bt453 Circuit Description (continued) Frame Buffer Interface ESD and Latchup Considerations While CS* is a logical one, the PO-P7, OLO, and OLI inputs are used to address the color palette RAM and overlay registers, as shown in Table 3. The addressed location provides 24 bits of color information to the three D/A converters. (See Figure 2 for timing information.) Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. The SYNC* and BLANK* inputs, also latched on the rising edge of CLOCK to maintain synchronization with the color data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figure 3. Table 4 details how the SYNC* and BLANK* inputs modify the output levels. The analog outputs of the Bt453 are capable of directly driving a 37.5 Q load, such as a doubly terminated 75 Q coaxial cable. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay V AA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. OLl OUl PO -P7 Addressed by frame buffer 0 0 0 0 $00 $01 color palette RAM location $00 color palette RAM location $01 : : : : 0 0 1 1 0 1 0 1 $FF $xx $xx $xx color palette RAM location $FF overlay color 1 overlay color 2 overlay color 3 Table 3. Pixel and Overlay Control Truth Table. CLOCK PO·PI. OLO. aLI. DATA SYNC". BLANK" lOR. lOG. JOB. !SYNC Figure 2. 4 - 60 SECTION 4 Video Input/Output Timing. Bt453 Circuit Description (continued) RED. BLUE GREEN MA V MA 19.05 0.114 26.({/ 1.000 -r-----.~----------------------~~------WHITEm~ 1M 0.054 9.05 0.340 -t-------------t--------4'------------------ V BLACK mVEL 7.SIRB 0.00 0.000 7.62 0.286 -i-------------......--.--..............------------------ 0.00 0.000 - ' - - - - - - - - - - - - - - - - - ' _........____________________ SYNC lEVEL BLANK lE~ 40IRB Note: 75 Q doubly terminated load, RSET = 280 Q, VREF = 1.235 V. ISYNC connected to lOG. RS-343A levels and tolerances assumed on all levels. Figure 3. Description WHITE DATA DATA-SYNC BLACK. BLACK-SYNC BLANK SYNC Composite Video Output Waveforms. lOG 10R,lOB (rnA) (rnA) 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 19.05 data + 1.44 data + 1.44 1.44 1.44 0 0 SYNC* BLANK* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: Typical with full-scale lOG = 26.67 rnA. RSET = 280 Q, VREF lOG. Table 4. = 1.235 V. ISYNC connected to Video Output Truth Table. RAMDACs 4 • 61 .. Bt453 Pin Descriptions Pin Name Description BLANK* Composite blank control input (TTL compatible). A logic zero drives the lOR, lOG, and lOB outputs to the blanking level, as illustrated in Table 4. It is latched on the rising edge of CLOCK. When BLANK* is a logical zero, the pixel and overlay inputs are ignored. SYNC'" Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source on the ISYNC output (see Figure 3). SYNC* does not override any other control or data input, as shown in Table 4; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. CLOCK Clock input (TTL compatible). The rising edge of CLOCK latches the PO-P7, OLO, aLl, SYNC *, and BLANK* inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedicated TTL buffer to avoid reflection-induced jitter. PO-P7 Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the color palette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK. PO is the LSB. Unused inputs should be connected to GND. OLO,OLl Overlay select inputs (TTL compatible). These inputs specify which palette is to be used to provide color information, as illustrated in Table 3. When accessing the overlay palette, the PO-P7 inputs are ignored. They are latched on the rising edge of CLOCK. OLO is the LSB. Unused inputs should be connected to aND. lOR, lOG, lOB Red, green, and blue current outputs. These high-impedance current sources are capable of directly driving a doubly terminated 75 0 coaxial cable (Figure 4). All outputs, whether used or not, should have the same output load. ISYNC Sync current output. This high-impedance current source is typically connected directly to the lOG output (Figure 4), and is used to encode sync information onto the green channel. ISYNC does not output any current while SYNC* is a logical zero. The amount of current output while SYNC'" is a logical one is: ISYNC (rnA) =1,728 * YREF (Y) / RSET (0) If sync information is not required on the green channel, this output should be connected to aND. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and aND controls the magnitude of the full-scale video signal (Figure 4). Note that the IRE relationships in Figure 3 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on lOG is (assuming ISYNC is connected to lOG): RSET (0) = 6,047 * YREF (Y) /lOG (rnA) The relationship between RSET and the full-scale output current on lOR and lOB is: lOR, IOB (rnA) = 4,319 * YREF (Y) / RSET (0) 4 - 62 SECTION 4 Bt453 Pin Descriptions (continued) Pin Name Description COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 IlF ceramic capacitor must be connected between this pin and VAA (Figure 4). The COMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to PC Board Layout Considerations for critical layout criteria. VREF Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 4, must supply this input with a 1.2 V (typical) reference. The Bt453 has an internal pull-up resistor between VREF and VAA. As the value of this resistor may vary slightly due to process variations, the use of a resistor divider network to generate the reference voltage is not recommended. A 0.1 IlF ceramic capacitor is used to decouple this input to VAA, as shown in Figure 4. If VAA is excessively noisy, better performance may be obtained by decoupling VREF to OND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. VM Analog power. All VAA pins must be connected. OND Analog ground. All OND pins must be connected. CS* Chip select control input (lTL compatible). This input must be a logical zero to enable data to be written to or read from the device. While CS* is a logical zero, the lOR, 100, and lOB outputs are forced to the black level. Note that the Bt453 will not function correctly while CS*, RD*, and WR* are simultaneously a logical zero. WR* Write control input (lTL compatible). To write data to the device, both CS* and WR* must be a logical zero. Data is latched on the rising edge of WR* or CS*, whichever occurs first. See Figure 1. RD* Read control input (lTL compatible). To read data from the device, both CS* and RD* must be a logical zero. See Figure 1. CO, Cl Command control inputs (TTL compatible). CO and Cl specify the type of read or write operation being performed, as illustrated in Table 1. DO-D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8 bit bidirectional data bus. DO is the least significant bit. RAMDACs 4 - 63 .. Bt453 Pin Descriptions (continued) 40-pin DIP Package 44-pin Plastic I-Lead (PLCC) Package u e~ ~ ~ ~ ~ ~ ~ ~ PSADJUST Dl VRFF 02 VAA 03 COMP D4 lOR lOR 28 CS" os lOG COMP '1:1 C1 D6 ISYNC 2Ii OJ 07 lOB VAA VREF 2S a.ocK SYNC· ~ lit !;; ~ III ~ m I:l :n ~ ~ GND GND FSADJUST 2A VAA DO 'l3 BLANK" Dl 22 01.0 P6 VAA VAA VAA 02 21 OLI ps WR' D3 20 PO P7 4·64 ~ ~ DO P4 RD' D4 19 PI P3 CS' os 18 P2 P2 CI PI CO PO CLOCK OLl SYNC· 01.0 BLANK· SECTION 4 ::'! IS 15 ~ !:l ~ ~ ~ ~ ~ :t :0 Ii: if 1£ ~ ~ ;( s: Bt453 PC Board Layout Considerations PC Board Considerations Power Planes This product requires special attention to proper layout techniques to achieve optimum performance. Before beginning PCB layout, refer to the CMOS RAMDAC layout example found in Bt4511718 Separate digital and analog power planes are necessary. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt453 power pins, any reference circuitry, and COMP and reference decoupling. There should be at least a 1/8 inch gap between the digital power plane and the analog power plane. Evaluation Module Operation and Measurements, application note (AN-16). This application note can be found in Brooktree's 1990 Applications Handbook. The layout should be optimized for lowest noise on the B t453 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. A well-designed power distribution network is critical to eliminating digital switching noise. Ground planes must provide a low-impedance return path for the digital circuits. A minimum of a 4-layer PC board is recommended with layers 1 (top) and 4 (bottom) for signals and layers 2 and 3 for power and ground. The optimum layout enables the B t453 to be located as close to the power supply connector and as close to the video output connector as possible. Ground Planes For optimum performance, a common digital and analog ground plane with tub isolation (at least a 1/8 inch gap) and connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector to preserve digital noise margins during MPU read cycles. Thus, the ground tub isolation technique is constrained by the noise margin degradation during digital readback of the Bt453. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. The analog ground plane should include all Bt453 ground pins, all reference circuitry and decoupling (external reference, RSET resistors, etc.), power supply bypass circuitry for the Bt453, analog output traces, and the video output connector. The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 4. This bead should be located within 3 inches of the Bt453 and provides resistance to switching currents, acting as a resistance at high frequencies. A low resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. Plane-to-plane noise coupling can be reduced by ensuring that portions of the digital power and ground planes do not overlay portions of the analog power and ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. Device Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Power Supply Decoupling Best power supply decoupling performance is obtained with a 0.1 IJ.F ceramic capacitor decoupling each of the three groups of V AA pins to GND. The capacitors should be placed as close as possible to the device. The 10 IJ.F capacitor is for low-frequency power supply ripple; the O.l IJ.F capacitors are for high-frequency power supply noise rejection. RAMDACs 4 • 65 Bt453 PC Board Layout Considerations (continued) A linear regulator to filter the analog power supply is recommended if the power supply noise is ~ 200 mV or greater than 10 LSBs. This is especially important when a switching power supply is used and the switching frequency is close to the raster scan frequency. Note that about 10% ofpower supply hum and ripple noise less than 1 MHz will couple onto the analog outputs. COMP DecoupUng The COMP pin must be decoupled to VAA, typically using a 0.11J.F ceramic chip capacitor. Low-frequency supply noise will require a larger value. Lead lengths should be minimized for best performance. Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge speeds (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals. Ensure that the power pins for the clock driver are properly decoupled to minimize transients. Minimize edge speeds and ringing, using damping resistors (10 to 50 ohms) or parallel termination where necessary. If using parallel termination on digital signals, the resistors should be connected to the digital power and ground planes, not the analog power and ground planes. If the display has a "ghosting" problem, additional capacitance in parallel with the COMP capacitor may help fix the problem. Analog Signal Interconnect Digital Signal Interconnect The Bt453 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The digital inputs to the Bt453 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power and ground planes. Most noise on the analog outputs will be caused by excessive edge speeds (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The digital edge speeds should be no faster than necessary, as feedthrough noise is proportional to the digital edge speeds. Lower speed applications will benefit by using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission line mismatch will exist if the line length reflection time is greater than 1/4 the signal edge time, resulting in ringing, overshoot, and undershoot that can generate noise onto the analog outputs. Line termination or reducing the line length is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (10 to 50 ohms). The video output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog outputs should have a source load resistor equal to the destination termination (via a clean isolated ground return path). The load resistor connection between the current output and GND should be as close as possible to the Bt453 to minimize reflections. Unused analog outputs should be connected to GND. Analog edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce high-frequency energy, reducing EMI and noise. Analog Output Protection The Bt453 analog outputs should be protected against high energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figure 4 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 parts are low-capacitance, fast-switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7001). 4 - 66 SECTION 4 Bt453 PC Board Layout Considerations (continued) C6 L1 ~..,. _ _• + SV (VCC) C1 Bt453 ~_~~_~_~~_~~ _ _ _ _ _. ._ _ _ _. . . ._ _ ~OIDID RSBT Rl R2 R3 PSADJUST IDRr-------~~--r--;-------{ - TO 100 r---...... VIDEO ------~~-;-------{ CONNECTOR !SYNC IDB~---------------1~----_{ P VAA 0 lN4148/9 DAC TO MONITOR OU11'lJT lN4148/9 OND Location Description CI-C6 C7 LI RI, R2, R3 0.1 lIP ceramic capacitor 10 I1F tantalum capacitor ferrite bead 75 n I % metal fihn resistor 280 n I % metal fihn resistor 1.2 V voltage reference RSEr ZI Vendor Part Number Erie RPEl12Z5U104M50V Mallory CSRI3G106KM Fair-Rite 2743001111 Dale CMF-55C Dale CMF-55C National Semiconductor LM385BZ-I.2 Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the Bt453. Figure 4. Substitution of devices with similar Typical Connection Diagram and Parts List. RAMDACs 4 - 67 Bt453 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage FS ADJUST Resistor Symbol Min Typ Max Units VAA TA 4.75 0 5.00 5.25 +70 RL VREF RSET 1.14 37.5 1.235 280 1.26 Volts °C Ohms Volts Ohms Symbol Min Typ Max Units 7.0 Volts VAA+0.5 Volts +125 +150 °C °C +175 +150 °C °C TSOL 260 °C TVSOL 220 °C Absolute Maximum Ratings Parameter VAA (measured to GND) Voltage on Any Signal Pin* Analog Output Short Circuit Duration to Any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature Ceramic Package Plastic Package Soldering Temperature (5 seconds, 1/4" from pin) Vapor Phase Soldering (1 minute) GND-O.5 indefinite ISC TA TS TJ -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. 4 - 68 SECTION 4 Bt453 DC Characteristics Parameter Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs Input High Voltage Input Low Voltage Input High Current (Vin =2.4 V) Input Low Current (Vin =0.4 V) Input Capacitance (f = 1 MHz, Vin =2.4 V) Digital Outputs Output High Voltage (lOH =-400 IlA) Output Low Voltage (lOL =3.2 rnA) 3-State Current Output Capacitance Analog Outputs Gray Scale Current Range Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Blank Level on lOR, lOB Blank Level on lOG Sync Level on lOG LSB Size DAC-to-DAC Matching (25-700 C.) Output Compliance Output Impedance Output Capacitance (f =1 MHz, lOUT =0 rnA) Symbol Min Typ Max Units 8 8 8 Bits ±1 ±l ±5 LSB LSB % Gray Scale n.. IL guaranteed Binary VlH vn.. 2.0 GND-O.5 VAA+O.5 0.8 1 -1 IIH TIL CIN VCH 2.4 Volts VOL Volts 10 IIA pF 22 rnA 20.40 18.50 1.90 50 8.96 50 rnA rnA rnA 5 +1.4 10 30 % Volts kn pF IIA 15 VOC RAOUT CAOUT 0.4 20 17.69 16.74 0.95 0 6.29 0 IIA IIA pF 10 IOZ CDOUT Volts Volts 19.05 17.62 1.44 5 7.62 5 69.1 2 -1.0 Voltage Reference Input Current IREF 10 Power Supply Rejection Ratio (COMP =O.IIlF, f =1 kHz) PSRR 0.12 0.5 IIA rnA IIA IIA %/%!:NAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 280 n, VREF = 1.235 V, ISYNC connected to lOG. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. RAMDACs 4·69 Bt453 AC Characteristics 66 MHz Devices Parameter Clock Rate Symbol Min Typ Fmax 40 MHz Devices Max Min Typ 66 Max Units 40 MHz CS*. CO. Cl Setup Time CS*. CO. Cl Hold Time 1 2 35 35 35 35 ns ns RD*. WR* High Time RD* Asserted to Data Bus Driven RD* Asserted to Data Valid RD* Negated to Data Bus 3-Stated 3 4 5 6 25 5 25 5 ns ns ns ns WR*LowTime Write Data Setup Time Write Data Hold Time 7 8 9 50 35 5 50 35 5 ns ns ns Pixel and Control Setup Time Pixel and Control Hold Time 10 11 5 2 7 3 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time 12 13 14 15 5 5 25 7 7 ns ns ns Analog Output Delay Analog Output RiseIFalI Time Analog Output Settling Time* Clock and Data Feedthrough* Glitch Impulse* DAC-to-DAC Crosstalk Analog Output Skew 15 16 17 Pipeline Delay 18 VAA Supply Current" IAA 100 15 2 20 3 25 -48 50 -22 1 30 2 2 220 275 100 15 2 2 20 3 25 -48 50 -22 1 30 2 ns ns ns dB pV-sec dB ns 2 2 Clocks 190 250 rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 280 ohms. VREF = 1.235 V. ISYNC connected to lOG. TTL input values are 0-3 V. with input rise/falI times ~ 4 ns. measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ~ 10 pF. DO-D7 output load ~ 75 pF. See timing notes in Figure 6. As the above parameters are guaranteed over the full temperature range. temperature coefficients are not specified or required. Typical values are based on nominal temperature. i.e .• room. and nominal voltage. i.e .• 5 V. *Clock and data feedthrough is a function of the amount of edge rates. overshoot, and undershoot on the digital inputs. For this test, the digital inputs have a 1 k.Q resistor to ground and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feed through. -3 dB test bandwidth = 2x clock rate. **At Fmax. IAA (typ) at VAA =5.0 V. IAA (max) at VAA =5.25 V. 4 - 70 SECTION 4 Bt453 Timing Waveforms I CS·, co, Cl - 1_ --., VALID ----1 7 3 - 5 ~ DO -07 (READ) OATA 011J' (RD. =0) If DO - D7 (WIUI'Il) Figure 5. }--6 I / DATA IN(WR·.O) 8 - I-- 9 MPU Read/Write Timing Dimensions. 11 18 PO - P1, OLO, OLI, SYNC', BLANK" lOR, lOG, lOB, ISYNC B- ---------------------------------------------~--(l__16 Note 1: Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of fulJ-scale transition. Note 2: Settling tinte measured from the 50% point of full-scale transition to the output remaining within ±l LSB. Note 3: Output rise/fall tinte measured between the 10% and 90% points of full-scale transition. Figure 6, Video Input/Output Timing. RAMDACs 4 - 71 Bt453 Ordering Information Ambient Temperature Range Model Number Speed Package Bt453KP66 66 MHz 40-pin 0.6" Plastic DIP O· to +70· C Bt453KPI66 66 MHz 44-pin Plastic I-Lead O· to +70· C Bt453KC66 66 MHz 40-pin 0.6" O· to +70· C CERDIP Bt453KC 40 MHz 40-pin 0.6" O· to +70· C CERDIP 4 - 72 Bt453KP 40 MHz 40-pin 0.6" Plastic DIP O· to +70· C Bt453KPI 40 MHz 44-pin Plastic I-Lead O· to +70· C SECTION 4 Bt453 Device Circuit Data . - - _ - - - - . _ - - - - - - _ - - - . . - VAA VREP >--#-- TODACS .. PSADJUST IPI!BDBACK Equivalent Circuit of the Reference Amplifier. Bt453 VAA GO-G7 100 ·30pp SYNC· BLANK" (100 ONLy) T RL q ....y + load) Equivalent Circuit of the Current Output (lOG). RAMDACs 4 - 73 Bt453 Revision History Datasheet Revision 4·74 Change from Previous Revision H Expanded PCB layout section. I Added ESD/latchup information. Expanded PCB Layout section. SECTION 4 Bt453/883 Applications Distinguishing Features • • • • • • • • • • 40 MHz Pipelined Operation Triple 8-bit D/A Converters 256 x 24 Color Palette RAM 3 x 24 Overlay Palette RS-343A/RS-170-Compatible Outputs Standard MPU Interface +5 V CMOS Monolithic Construction 40-pin Ceramic Sidebraze DIP Package Typical Power Dissipation: 950 mW High-Resolution Color Graphics CAE/CAD/CAM Image Processing Instrumentation Desktop Publishing Product Description The Bt453/883 RAMDAC is designed specifically for high-resolution color graphics. It has a 256 x 24 color lookup table with triple 8-bit video D/A converters, supporting up to 259 simultaneous colors from a 16.8 million color palette. Three overlay registers provide for overlaying cursors, grids, menus, etc. The MPU bus operates asynchronously to the video data, simplifying the design interface to the system. Functional Block Diagram VAA a.OCK FS ADJUST GND r-----, VRBF L_-=::V>f'==T>----i-- PO-PI caMP lOR !SYNC >----i-- 100 BLANK' >----i-- lOB OLO,OLI DO-D7 Brooktree Corporation 9950 Bames Canyon Rd_ San Diego, CA 92121-2790 (619) 452-7580· (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 L453MOI Rev. F MIL-STD-883C, Class B Monolithic CMOS 256 x 24 Color Palette 40 MHz RAMDAC™ 4 . 7S The Bt453/883 generates RS-343A compatible video signals into a doubly terminated 75 n load, and RS-170 compatible video signals into a singly terminated 75 n load, without requiring external buffering. Both the differential and linearity errors of the D/A converters are guaranteed to be a maximum of ±1 LSB over the full temperature range. .. Bt453/883 Circuit Description MPU Interface As illustrated in the functional block diagram, the Bt453/883 supports a standard MPU bus interface, allowing the MPU direct access to the color palette RAM and overlay color registers. The MPU interface operates asynchronously to the video data, simplifying the design interface. The CO and Cl control inputs specify whether the MPU is accessing the address register, color palette RAM, or the overlay registers, as shown in Table 1. The 8-bit address register is used to address the color palette RAM and overlay registers, eliminating the requirement for external address multiplexers. ADORO corresponds to DO and is the least significant bit. To write color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be modified. The MPU performs three successive write cycles (red, green, and blue), using CO and Cl to select either the color palette RAM or overlay registers. Ouring the blue write cycle, the three bytes of color information are concatenated into a 24-bit word and written to the location specified by the address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. Note that any time the CS· input is a logical zero, the video outputs are forced to the black level. When accessing the color palette RAM, the address register resets to $00 following a blue read or write cycle to RAM location $FF. While accessing the overlay color registers, the six most significant bits of the address register (ADOR2-7) are ignored. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADORa, ADDRb) that count modulo three, as shown in Table 2. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The MPU does not have access to these bits. The other 8 bits of the address register (AOOR0-7) are accessible to the MPU, and are used to address color palette RAM locations and overlay registers, as shown in Table 2. Figure 1 illustrates the MPU read/write timing. To read color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be read. The MPU performs three successive read cycles (red, green, and blue), using CO and Cl to select either the color palette RAM or overlay registers. Following the blue read cycle, the address register increments to the next location which the MPU may read by simply reading another sequence of red, green, and blue data. Cl CO Addressed by MPU 0 0 1 1 0 1 0 1 address register color palette RAM address register overlay registers Table 1. 4·76 SECTION 4 Control Input Truth Table. BnxKtree~ Bt453/883 Circuit Description (continued) Value Cl co Addressed by MPU 00 01 10 x x x 1 1 1 red value green value blue value $00 - $FF xxxx xxOO xxxx xxOI xxxx xxl0 xxxx xxll 0 1 1 1 1 1 1 1 1 1 color palette RAM reserved overlay color 1 overlay color 2 overlay color 3 ADDRa, b (counts modulo 3) ADDR0-7 (counts binary) Table 2_ CS', co, Cl RD"'. WR- - Address Register (ADDR) Operation, =x X VALID \ / < READ (DO - D7) DATA OUT (RD' .0) X WRJI1! (DO - D7) Figure 1. DATA IN (WR'.O) > X MPU Read/Write Timing. RAMDACS 4 - 77 Bt453/883 Circuit Description (continued) Frame Buffer Interface While CS* is a logical one, the PO-P7, 01.0, and OLl inputs are used to address the color palette RAM and overlay registers, as shown in Table 3. The addressed location provides 24 bits of color information to the three D/A converters. (See Figure 2.) The analog outputs of the Bt453/883 are capable of directly driving a 37.5 n load, such as a doubly terminated 75 n coaxial cable. The SYNC* and BLANK* inputs, also latched on the rising edge of CLOCK to maintain synchronization with the color data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figure 3. Table 4 details how the SYNC· and BLANK· inputs modify the output levels. OLI 01.0 PO-P7 Addressed by frame buffer 0 0 0 0 $00 $01 color palette RAM location $00 color palette RAM location $01 : color palette RAM location $FF overlay color 1 overlay color 2 overlay color 3 : : : 0 0 1 1 0 1 0 1 $FF $xx $xx $xx Table 3. Pixel and Overlay Control Truth Table. po. P7. 01.0. OLi. DATA SYNC·. BLANK· lOR. lOG, lOB. ISYNC Figure 2. 4 - 78 SECTION 4 Video Input/Output Timing. Bt453/883 Circuit Description (continued) RED,BLUE GREEN MA V MA V 19.05 0.714 26.rn 1.000 -r----..,...---------------,::---- 1.44 0.054 9.0' 0.340 -1-------1...-----1--------- BLACK UlYEL 0.00 0.000 7.62 0.286 -I------~~~~-~-------- ~KUlYEL WHITE LBVEL 0.00 ~ ~ 401RB - L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SYNCLBVEL 0.000 Note: 75 n doubly terminated load, RSET tolerances assumed on all levels. Figure 3, Description WHrIE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC = 280 n, VREF = 1.235 V. ISYNC connected to 100. RS-343A levels and Composite Video Output Waveforms. 100 lOR, lOB (rnA) (rnA) 26.67 data + 9.05 data + 1.44 9,05 1.44 7.62 0 19.05 data + 1.44 data + 1.44 1.44 1.44 0 0 Note: Typical with full-scale 100 = 26.67 rnA. RSET SYNC· BLANK· DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx =280 n, VREF = 1.235 V ISYNC connected to 100. Table 4. Video Output Truth Table. RAMDACS 4·79 .. Bt453/883 Pin Descriptions Pin Name Description BlANK* Composite blank control input (ITL compatible). A logic zero drives the lOR, 100, and lOB outputs to the blanking level, as illustrated in Table 4. It is latched on the rising edge of CLOCK. When BLANK. is a logical zero, the pixel and overlay inputs are ignored. SYNC* Composite sync control input (ITL compatible). A logical zero on this input switches off a 40 IRE current source on the ISYNC output (see Figure 3). SYNC· does not override any other control or data input, as shown in Table 4; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. CLOCK Clock input (ITL compatible). The rising edge of CLOCK latches the PO-P7, OLO, OLl, SYNC*, and BLANK· inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedicated TTL buffer. PO-P7 Pixel select inputs (ITL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the color palette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK. PO is the LSB. Unused inputs should be connected to GND. OLO,OL1 Overlay select inputs (TTL compatible). These inputs specify which palette is to be used to provide color information, as illustrated in Table 3. When accessing the overlay palette, the PO-P7 inputs are ignored. They are latched on the rising edge of CLOCK. OLO is the LSB. Unused inputs should be connected to GND. lOR, 100, lOB Red, green, and blue current outputs. These high-impedance current sources are capable of directly driving a doubly terminated 75 n coaxial cable (Figure 4). All outputs, whether used or not, should have the same output load. ISYNC Sync current output. This high-impedance current source is typically connected directly to the 100 output (Figure 4), and is used to encode sync information onto the green channel. ISYNC does not output any current while SYNC. is a logical zero. The amount of current output while SYNC· is a logical one is: ISYNC (rnA) = 1,728 ... VREF (V) I RSET (n) If sync information is not required on the green channel, this ou tput should be connected to GND. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal (Figure 4). Note that the IRE relationships in Figure 3 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on lOG is (assuming ISYNC is connected to lOG): RSET (n) = 6,047 • VREF (V) /lOG (rnA) The relationship between RSET and the full-scale output current on lOR and lOB is: lOR, lOB (rnA) = 4,319 • VREF (V) I RSET (n) 4 • 80 SECTION 4 Bt453/883 Pin Descriptions (continued) Pin Name Description COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 I1F ceramic capacitor must be connected between this pin and VAA (Figure 4). The COMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to PC Board Layout Considerations for critical layout criteria. VREF Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 4, must supply this input with a 1.2 V (typical) reference. The Bt453/883 has an internal pull-up resistor between VREF and VAA. As the value of this resistor may vary slightly due to process variations, the use of a resistor divider network to generate the reference voltage is not recommended. A O.II1F ceramic capacitor is used to decouple this input to VAA, as shown in Figure 4. If VAA is excessively noisy, better performance may be obtained by decoupling VREF to GND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. VAA Analog power. All VAA pins must be connected. GND Analog ground. All GND pins must be connected. CS* Chip select control input (TTL compatible). This input must be a logical zero to enable data to be written to or read from the device. While CS* is a logical zero, the lOR, lOG, and lOB outputs are forced to the black level. Note that the Bt453/883 will not function correctly while CS*, RD*, and WR * are simultaneously a logical zero. WR* Write control input (TTL compatible). To write data to the device, both CS* and WR* must be a logical zero. Data is latched on the rising edge of WR* or CS*, whichever occurs first. See Figure 1. RD* Read control input (TTL compatible). To read data from the device, both CS* and RD* must be a logical zero. See Figure 1. CO,Cl Command control inputs (TIL compatible). CO and Cl specify the type of read or write operation being performed, as illustrated in Tables 1 and 2. DO-D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. DO FSADJUST D1 VREP 02 VAA 03 COMP D4 lOR os 100 D6 ISYNC 07 lOB GND GND VAA VAA F'1 VAA )'W; VAA PS WR' N RD' P.! CS' P2 CI PI co PO CLOCK OLl SYNC' 01.0 BLANK' RAMDACS 4,81 .. Bt453/883 PC Board Layout Considerations PC Board Considerations Power Planes This product requires special attention to proper layout techniques to achieve optimum performance. Before beginning PCB layout, refer to the CMOS RAMDAC layout example found in Bt4511718 Evaluation Module Operation and Measurements, application note (AN-16). This application note can be found in Brooktree's 1990 Applications Handbook. Separate digital and analog power planes are necessary. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt453 power pins, any reference circuitry, and COMP and reference decoupling. There should be at least a 1/8 inch gap between the digital power plane and the analog power plane. The layout should be optimized for lowest noise on the Bt453/883 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 4. This bead should be located within 3 inches of the Bt453/883 and provides resistance to switching currents, acting as a resistance at high frequencies. A low resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. A well-designed power distribution network is critical to eliminating digital switching noise. Ground planes must provide a low-impedance return path for the digital circuits. A minimum of a 4-layer PC board is recommended with layers 1 (top) and 4 (bottom) for signals and layers 2 and 3 for power and ground. Plane-to-plane noise coupling can be reduced by ensuring that portions of the digital power and ground planes do not overlay portions of the analog power and ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. The optimum layout enables the Bt453/883 to be located as close to the power supply connector and as close to the video output connector as possible. Ground Planes For optimum performance, a common digital and analog ground plane with tub isolation (at least a 1/8 inch gap) and connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector to preserve digital noise margins during MPU read cycles. Thus, the ground tub isolation technique is constrained by the noise margin degradation during digital readback of the Bt453/883. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. The analog ground plane should include all Bt453/883/883 ground pins, all reference circuitry and decoupling (external reference, RSET resistors, etc.), power supply bypass circuitry for the Bt453, analog output traces, and the video output connector. 4 - 82 SECTION 4 Device Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Power Supply DecoupUng Best power supply decoupling performance is obtained with a 0.1 I1F ceramic capacitor decoupling each of the three groups of VAA pins to GND. The capacitors should be placed as close as possible to the device. The 10 I1F capacitor is for low-frequency power supply ripple; the 0.1 I1F capacitors are for high-frequency power supply noise rejection. A linear regulator to filter the analog power supply is recommended if the power supply noise is ~ 200 mV or greater than 10 LSBs. This is especially important when a switching power supply is used and the switching frequency is close to the raster scan frequency. Note that about 10% of power supply hum and ripple noise less than 1 MHz will couple onto the analog outputs. Bt453/883 PC Board Layout Considerations (continued) COMP Decoupling Analog Signal Interconnect The COMP pin must be decoupled to VAA, typically using a 0.1 JLF ceramic chip capacitor. Low-frequency supply noise will require a larger value. Lead lengths should be minimized for best performance so that the self-resonance frequency is greater than the LO* frequency. The Bt453/883 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. If the display has a "ghosting" problem, additional capacitance in parallel with the COMP capacitor may help to fix the problem. Digital Signal Interconnect The digital inputs to the B t453/883 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power and ground planes. Most noise on the analog outputs will be caused by excessive edge speeds (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The video output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog outputs should have a source load resistor equal to the destination termination (via a clean isolated ground return path). The load resistor connection between the current output and GND should be as close as possible to the Bt453/883 to minimize reflections. Unused analog outputs should be connected to GND. Analog edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce high-frequency energy, reducing EM! and noise. Analog Output Protection The digital edge speeds should be no faster than necessary, as feedthrough noise is proportional to the digital edge speeds. Lower speed applications will benefit by using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. The Bt453/883 analog outputs should be protected against high-energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. Transmission line mismatch will exist if the line length reflection time is greater than 1/4 the signal edge time, resulting in ringing, overshoot, and undershoot that can generate noise onto the analog outputs. Line termination or reducing the line length is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (10 to 50 Q). The diode protection circuit shown in Figure 4 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 parts are low-capacitance, fastswitching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMB07001). Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge speeds (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals. Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. Ensure that the power pins for the clock driver are properly decoupled to minimize transients. Minimize edge speeds and ringing, using damping resistors (10 to 50 Q) or parallel termination where necessary. If using parallel termination on digital signals, the resistors should be connected to the digital power and ground planes, not the analog power and ground planes. ESD and Latchup Considerations All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay VAA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +{l.5 V. RAMDACS 4 - 83 .. Bt453/883 PC Board Layout Considerations (continued) LI +5V(VCC) +C/ Cl Bt453 ~""p-"~"~"~"""""""""""""",,,,,,, Location Description CI-C6 C7 0.1 J.lF ceramic capacitor 10 J.lF tantalum capacitor ferrite bead 75 n 1% metal film resistor 280 n 1% metal film resistor 1.2 V voltage reference L1 Rl, R2, R3 RSEf Zl Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the B t453/883. Figure 4. 4·84 SECTION 4 GROUND Substitution of devices with similar Typical Connection Diagram and Parts List. Bt453/883 Recommended Operating Conditions Parameter Symbol Min Typ Max Units VAA TA 4.5 -55 5.0 5.5 +125 RL VREF RSET 1.14 37.5 1.235 280 1.26 Volts ·C Ohms Volts Ohms Symbol Min Typ Max Units 7.0 Volts VAA+0.5 Volts TJ +125 +150 +175 ·C ·C ·C 'ISOL 260 ·C aJC 18 ·C/W aJA 28 ·C/W Power Supply Ambient Operating Temperature Output Load Reference Voltage FS ADmST Resistor .. Absolute Maximum Ratings Parameter VAA (measured to GND) Voltage on Any Digital Pin Analog Output Short Circuit Duration to Any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds. 1/4" from pin) GND-O.5 ISC TA 'IS indefinite -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RAMDACS 4 • 8S Bt453/883 DC Characteristics Parameter Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs Input High Voltage CLOCK Other Input Low Voltage Input High Current (Vin =VAA) Input Low Current (Vin =0 V) Input Capacitance** Digital Outputs Output High Voltage (IOH =-400 J.lA) Output Low Voltage (IOL =3.2 rnA) 3-State Current Output Capacitance** Analog Outputs Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Blank Level on lOR, lOB Blank Level on lOG Sync Level on lOG LSB Size*** DAC-to-DAC Matching Output Compliance Output Capacitance** Symbol Min Typ Max Units 8 8 8 Bits ±I ±1 ±5 LSB LSB % GrayScale IL IL guaranteed Binary VIH 2.4 2.0 VlL IIH IlL CIN VCH 0.8 1 -1 10 2.4 Volts Volts Volts ~ ~ pF Volts VOL 0.4 Volts lOZ mom 10 30 pF 17.69 16.74 0.95 -10 6.29 -10 65.7 Vex: CAOm -1.0 19.05 17.62 1.44 1 7.62 1 69.1 3.5 20.40 18.50 1.90 50 8.96 50 72.6 7 +1.4 30 ~ rnA rnA rnA ~ rnA ~ ~ % Volts pF Test conditions (unless otherwise specified): 100% tested at VAA = 4.5 V and 5.5 V, TA = _55', +25', and +125' C. RSET = 280 ± 0.1% n, VREF = 1.235 V. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. **Derived from characterization (TA = 25' C, VAA = 5 V ± 10%), not tested. These parameters are controlled via design or process parameters and are not directly tested. They are characterized upon initial design release and upon design changes which would affect them. ***Computed by the formula: (White Level Relative to Black) I 255. 4 - 86 SECTION 4 Bt453/883 AC Characteristics _55° to +125° C. Parameter Clock Rate Symbol Min Fmax Max Units 40 MHz CS*, CO, Cl Setup Time CS*, CO, Cl Hold Time 1 2 35 35 ns ns RD*, WR* High Time RD* Asserted to Data Bus Driven RD* Asserted to Data Valid RD* Negated to Data Bus 3-Stated 3 4 5 25 2 ns ns ns ns WR*LowTime Write Data Setup Time Write Data Hold Time 7 8 9 50 35 5 ns ns ns Pixel and Control Setup Time Pixel and Control Hold Time 10 11 7 3 ns ns Clock Cycle Time Clock Pulse Width High Clock Pulse Width Low 12 13 14 25 7 7 ns ns ns Analog Output Rise/Fall Time** 15 8 ns 1M 300 rnA V AA Supply Current*** 100 15 6 .. Test conditions (unless otherwise specified): 100% testing at VAA = 4.5 V and 5.5 V with TA = _55°, 25°, and 125° C. RSET = 280 n ± 0.1 %, VREF = 1.235 V. Input values are 0.8-2.4 V, with input rise/fall times :s; 4 ns, measured between the 10% and 90% points. Analog output load with doubly terminated 50 n line. 00-D7 output load - 75 pF. See timing notes in Figure 6. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. **Derived from characterization (TA = 25° C. V AA = 5 V ± 10%), not tested. These parameters are controlled via design or process parameters and are not directly tested. They are characterized upon initial design release and upon design changes which would affect them. *** IAA (max) is measured at Fmax, with V AA =5.5 V and is 100% tested at TA =25° C. RAMDACS 4 ·87 Bt453/883 Timing Waveforms I CS·. co, Cl 2_ ~ VALID 7 t RD"', WR" 3 - J-6 5 ~ DO - D7 (READ) DATA OUT (RD' =0) t DO - D7 (WRITE) Figure 5. I /' DATA IN (WR' = 0) 8 - t-- 9 MPU Read/Write Timing Dimensions. 12 CLOCK PO-PI, 01.0, OLI, SYNC·, BLANK'" lOR, lOG, lOB, !SYNC -------Ir Note 1: Settling time measured from the 50% point of full-scale transition to the output remaining within ±1 LSB for data only, Note 2: Output rise/fall time measured between the 10% and 90% points of full-scale transition, Figure 6. 4 - 88 SECTION 4 Video Input/Output Timing. Bt453/883 Ordering Information Model Number MrBF* (hours) Package Bt453SC883 0.54 x 106 40-pin 0.6" Ceramic Sidebraze DIP Ambient Temperature Range _55 0 to +125 0 C. *MrBF is calculated per MIL Handbook 217. .. RAMDACS 4·89 Bt454 Bt455 Distinguishing Features Applications • 170, 135, 110 MHz Operation • 4:1 Multiplexed TIL Pixel Ports Triple 4-bit D/A Converters • 16 Word Dual Port Color Palette • 1 Dual Port Overlay Palette • RS-343A-Compatible Outputs • Standard MPU Interface • +5 V CMOS Monolithic Construction • 44-pin PLCC Package • Typical Power Dissipation: 1 W • • • • • High Resolution Color Graphics CAE/CAD!CAM Image Processing Video Reconstruction Desktop Publishing Product Description Related Products • Bt451, Bt457 , Bt458, Bt459 Bt460, Bt468 Functional Block Diagram CLOCK* LD' a...OCK VAA 170 MHz Monolithic CMOS 16 Color Palette RAMDAC™ GND FS ADJUST The Bt454 and Bt455 are pin-compatible and software-compatible RAMDACs designed specifically for high-performance, high-resolution color graphics_ The architecture enables the display of 1600 x 1200 bit-mapped color graphics (up to 4 bits per pixel plus 1 bit of overlay information), minimizing the use of costly ECL interfacing, as most of the high-speed (pixel clock) logic is contained on chip_ The multiple pixel ports and internal multiplexing enables TTL-compatible interfacing (up to 42.5 MHz) to the frame buffer, while maintaining the l70-MHz video data rates required for sophisticated color graphics. -I--r--I 10R(N/Cl PO-P3 (A-D) 10G(IOUI) OL(A-D) lOB (N/Cl The Bt454 is a triple 4-bit video RAMDAC, and supports up to 17 simultaneous colors from a 4096 color palette. On-chip features include a temperature-compensated precision voltage reference, divide-by-four of the clock for load generation, color overlay capability, and a dual-port color palette RAM. The Bt455 is a single-channel version of the Bt454, well-suited for high-performance monochrome or gray-scale applications. CB* R/W co Cl Brooktree Corporation 9950 Barnes Canyon Rd_ San Diego, CA 92121-2790 (619) 452-7580 • (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 lA54001 Rev_ I The Bt454/455 generates RS-343A-compatible video signals, and is capable of driving doubly terminated 75 n coax directly, without requiring external buffering_ Both the differential and integral linearity errors of the D/A converters are guaranteed to be a maximum of ±1/4 LSB over the full temperature range_ DO-D3 4 • 91 - Bt4S4/4SS Circuit Description MPU Interface As illustrated in the functional block diagram, the Bt454/455 supports a standard MPU bus interface, allowing the MPU direct access to the internal control registers and color/overlay palettes. The dual-port color palette RAM and overlay register allow color Updating without contention with the display refresh process. As shown in Table I, the CO and CI control inputs, in conjunction with the internal address register, specify which color palette RAM entry or overlay register will be accessed by the MPU. The address register is used to address the internal RAM, eliminating the requirement for external address multiplexers. ADDRO corresponds to DO and is the least significant bit. To write color data to the color palette RAM, the MPU loads the address register with the desired RAM location to be modified. The MPU performs three successive write cycles (4 bits each of red, green, and blue), using CO and CI to select the color palette RAM. Following the blue write cycle, the address register increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. To read color data from the color palette RAM, the MPU loads the address register with the desired RAM location to be read. The MPU performs three successive read cycles (4 bits each of red, green, and blue), using CO and CI to select the color palette RAM. Following the blue read cycle, the address register increments to the next location, which the MPU may read by simply reading another sequence of red, green, and blue data. 4 • 92 SECTION 4 When accessing the color palette RAM, the address register resets to $0 following the blue read or write cycle to location $F. To read from or write to the overlay register, the MPU, using CO and CI to select the overlay register, performs three successive read or write cycles (4 bits each of red, green, and blue). ADDR0-3 are not used. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADDRa, ADDRb) that count modulo three, as shown in Table 1. They are reset to zero when the MPU reads or writes to the address register. The MPU does not have access to these bits. The other 4 bits of the address register (ADDRO-3) are accessible to the MPU, and are used to address the color palette RAM locations. Although the Bt455 uses only the green channel, it must still go through the count modulo 3 write sequence. The values loaded into the red and blue color palette should be $0. When reading or writing the color values, the RAM or overlay register is accessed each time a 4-bit color value is read or written. Although the color palette RAM and overlay register are dual-ported, if the pixel and overlay data is addressing the same palette entry being written to by the MPU, it is possible for one or more of the pixels on the display screen to be disturbed. Figure 1 illustrates the MPU read/write timing when accessing the device. Bt454/455 Circuit Description (continued) Value ADDRa, b (counts modulo 3) 00 01 10 0 0 0 0 write to address register write to color palette RAM DO-D3 ignored, 0 --> ADDRa, b write to overlay register $x $x 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 read address register read color palette RAM o--> DO-D3, 0 --> ADDRa, b read overlay register $x x x 1 x 3-state DO-D3 $x Table 1. DO - D3 (WRITE) red value green value blue value 0 0 0 0 SO-SF DO - D3 (READ) Addressed by MPU RJW 0 1 0 1 $x $x CIl' CE* 0 0 1 1 SO-SF ___ co 1 1 1 $x ADDR0-3 (counts binary) ~.rn.cI ====><~ C1 V_AL_ID__ - Address Register (ADDR) Operation. ~)(~_______________________________________________ \'----------'/ ---------------------« DATA OUT (RJW = I) ________________________--'x Figure 1. DATA IN(RJW =0) )>------ x'--____ MPU Read/Write Timing. RAMDACs 4 - 93 Bt454/455 Circuit Description (continued) Frame Buffer Interface To enable pixel data to be transferred from the frame buffer at reasonable data rates (up to 42.5 MHz), the Bt454/455 incorporates internal latches and multiplexers. As illustrated in Figure 2, the SYNC*, BLANK*, PO-P3 {A-OJ. and OL (A-D) inputs are latched on the rising edge of LooUT. Note that with this configuration, the sync and blank timing will be recognized only with four pixel resolution. Typically, the LooUT signal is used to cIock external circuitry to generate the basic video timing and to cIock the video DRAMs of the frame buffer. The overlay inputs may have pixel tlmmg, facilitating the use of an additional bit plane in the frame buffer to control overlay selection on a pixel basis, or they may be controlled by external character or cursor generation logic. The Bt454/455 generates the LDOUT signal internally by dividing the clock by four. LooUT is the setup-and-hold time reference for the pixel, overlay, sync, and blank inputs. It is recommended that LooUT be buffered to clock the shift registers of the video DRAMs. Once the pixel and overlay data are latched by LooUT, they are internally multiplexed at the pixel cIock rate. On each cIock cycle, the Bt454/455 outputs color information based on the {A} inputs, followed by the (B) inputs, etc., until all four pixels have been output, at which point the cycle repeats. LOOUT po.P3 IA·D). OLIA·D). SYNC·, BLANK" lOR. 100. lOB (lOUT·· BT4SS) CLOCK Figure 2. 4·94 SECTION 4 Video Input/Output Timing. Bt454/455 Circuit Description (continued) Video Generation CRT Monitor Interface Each clock cycle, 4bits of color information (PO-P3) and 1 bit of overlay information (OL) for each pixel are used to determine whether a color palette entry in the RAM or whether the overlay register is to provide color information. Note that PO is the LSB when addressing the color palette RAM. Table 2 illustrates the truth table used for color selection. The analog outputs are capable of directly driving a 37.5 n load, such as a doubly terminated 75 n coaxial cable, when soldered directly to a PC board. When the device is socketed, it is recommended that only a singly terminated 75 n load be used (unless air flow or heat sinking are available). Note that when driving a singly terminated 75 n load, the RSET value must be adjusted. Every clock cycle, the selected information is presented to the three 4-bit D/A converters. ESD and Latchup Considerations The SYNC* and BLANK* inputs, pipelined to maintain synchronization with the pixel data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figure 3. Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. The varying output current from each of the D/A converters produces a corresponding voltage level, which is used to drive the color CRT monitor. Note that only the green output (lOG) on the Bt454 contains sync information. Table 3 details how the SYNC* and BLANK* inputs modify the output levels. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay V AA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. The D/A converters on the Bt454/455 use a segmented architecture in which bit currents are routed to either the current output or GND by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current-steering their outputs. An on-chip operational amplifier stabilizes the full-scale output current against temperature and power supply variations. Latchup can be prevented by assuring that all V AA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. a., PO-P3 Addressed by frame buffer 0 0 $0 $1 color palette entry $0 color palette entry $1 : color palette entry $F overlay color Table 2. : : 0 1 $F $x Palette and Overlay Select Truth Table. RAMDACS 4· 9S .. Bt454/455 Circuit Description (continued) IOR,IOB MA IOG,IOUT V MA v 19.05 0.714 26.67 1.000 -r----::..-------------::::----- WHlTIl LEVEL 1.44 0.054 9.05 0.340 +------+-----/'----------- BLACK LEVEL 0.00 0.000 7.62 0.286 +------~~-~~---------BUWKLEVEL 0.00 0.000 7.5 IRE 40 IRE Note: 75 levels. n -f-_ _ _ _ _ _ _- - - ' _ " -_ _ _ _ _ _ _ _ _ _ SYNC doubly tenninated load, RSET = 523 Figure 3. Description WHITE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC n. RS·343A levels and tolerances assumed on all Composite Video Output Waveforms. IOG,IOUT IOR,IOB (rnA) (rnA) 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 19.05 data + 1.44 data + 1.44 1.44 1.44 0 0 SYNC* BLANK* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $F data data $0 $0 $x $x Note: Typical with full-scale lOG =26.67 rnA. RSET = 523 n. Table 3. 4 - 96 SECTION 4 LEVEL Video Output Truth Table. Bt454/455 Pin Descriptions Pin Name Description BLANK" Composite blank control input (lTL compatible). A logic zero drives the analog outputs to the blanking level, as illustrated in Table 3. It is latched on the rising edge of LOOUT. When BLANK· is a logical zero, the pixel and overlay inputs are ignored. SYNC" Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source on the 100 output (see Figure 3). SYNC" does not override any other control or data input, as shown in Table 3; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of LooUT. If sync information is not to be generated on the lOG output, this pin should be connected to GND. lDOUT Load control output (TIL compatible). The PO-P3 {A-DJ, OL {A-DJ, BLANK", and SYNC· inputs are latched on the rising edge of LooUT. LooUT is internally generated by dividing the clock by four. LDOUT should have absolute minimal loading (one TIL load) to avoid display artifacts. PO-P3 {A-DJ Pixel select inputs (TTL compatible). These inputs are used to specify, on a pixel basis, which one of the 16 entries in the color palette RAM is to be used to provide color information. Four consecutive pixels (up to 4 bits per pixel) are input through this port. They are latched on the rising edge of LooUT. PO is the LSB. Unused inputs should be connected to GND. Note that the {AJ pixel is output first, followed by the {BJ pixel, etc., until all four pixels have been output, at which point the cycle repeats. OL{A-DJ Overlay select inputs (lTL compatible). These control inputs are latched on the rising edge of LooUT, and specify which palette is to be used for color information. A logical zero indicates the color palette RAM is to provide color information, while a logical one indicates the overlay register is to provide color information. When accessing the overlay palette, the PO-P3 {A-DJ inputs are ignored. Unused inputs should be connected to GND. lOur lOR, lOG, lOB, Red, green, and blue video current outputs. These high-impedance current sources are capable of directly driving a doubly terminated 75 n coaxial cable (Figure 4). All outputs, whether used or not, should have the same output load. The Bt455 outputs lOUT rather than lOR, 100, and lOB. GND Analog ground. All GND pins must be connected. VM Analog power. All VAA pins must be connected. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full scale video signal (Figure 4). Note that the IRE relationships in Figure 3 are maintained, regardless of the full scale output current The relationship between RSET and the full scale output current on lOG is: RSET (n) =13,948/100 (rnA) The full-scale output current on lOR and lOB for a given RSET is: lOR, lOB (rnA) = 9,963/ RSET (n) RAMDACs 4 - 97 Bt454/455 Pin Descriptions (continued) Pin Name Description COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 I1F ceramic capacitor must be connected between this pin and the adjacent VAA pin (Figure 4). Connecting the capacitor to VAA rather than to GND provides the highest possible low-frequency power supply noise rejection. The COMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to PC Board Layout Considerations for critical layout criteria. CLOCK, CLOCK* Clock inputs. These differential clock inputs are designed to be driven by ECL logic configured for single supply (+5 V) operation. The clock rate is typically the pixel clock rate of the system. CE* Chip enable control input (TTL compatible). This input must be a logical zero to enable data to be written to or read from the device. During write operations, data is internally latched on the rising edge of CE* (Figure 1). Care should be taken to avoid glitches on this edge-triggered input. R!W Read/write control input (TTL compatible). To write data to the device, both CE* and R!W must be a logical zero. To read data from the device, CE* must be a logical zero and R!W must be a logical one. R!W is latched on the falling edge of CE*. See Figure 1. CO,Cl Command control inputs (TTL compatible). CO and CI specify the type of read or write operation being performed, as illustrated in Table 1. They are latched on the falling edge of CE*. DO-D3 Data bus (TTL compatible). Data is transferred into and out of the device over this 4 bit bidirectional data bus. DO is the least significant bit. §~ ~ ~ ~ ~ ~ ~ ~ ~ § III 311 Il; lI! :q 11; ~ R ;;; ~ fII DO 28 DI 'E1 FOB D2 2Ii POe D3 PID CR' BLANK' R/W SYNC- co PIA C1 PIB ~/C)[OR PlC (I01lT)[OO ~/C) PlD lOB ... .. . ~~ ~ 18 ::; ~ ~ ... Q :::I ~ ~ ~ U .. < ~ Il! Il! Il! Il! :!l !:; ~ ~ ~ Q !2 Note: Bt455 pin names are in parentheses. 4·98 POA SECTION 4 PM Bt454/455 PC Board Layout Considerations PC Board Considerations Power Planes This product requires special attention to proper layout techniques to achieve optimum performance. Before beginning PCB layout, refer to the CMOS RAMDAC layout example found in Bt451n/8 Evaluation Module Operation and Measurements, application note (AN-16). This application note can be found in Brooktree's 1990 Applications Handbook. Separate digital and analog power planes are necessary. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt454/455 power pins, any reference circuitry, and COMP and reference decoupling. There should be at least a 1/8 inch gap between the digital power plane and the analog power plane. The layout should be optimized for lowest noise on the Bt454/455 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 4. This bead should be located within 3 inches of the Bt454/455 and provides resistance to switching currents, acting as a resistance at high frequencies. A low resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. ringing. A well-designed power distribution network is critical to eliminating digital switching noise. Ground planes must provide a low-impedance return path for the digital circuits. A minimum of a 6-layer PC board is recommended. The ground layer should be used as a shield to isolate noise from the analog traces with layer 1 (top) the analog traces, layer 2 the ground plane (preferably analog ground plane), layer 3 the analog power plane, using the remaining layers for digital traces and digital power supplies. The optimum layout enables the Bt454/455 to be located as close to the power supply connector and as close to the video output connector as possible. Ground Planes For optimum performance, a common digital and analog ground plane with tub isolation (at least a 1/8 inch gap) and connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector to preserve digital noise margins during MPU read cycles. Thus, the ground tub isolation technique is constrained by the noise margin degradation during digital readback of the Bt454/455. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. Plane-to-plane noise coupling can be reduced by ensuring that portions of the digital power and ground planes do not overlay portions of the analog power and ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. Device Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Power Supply Decoupllng Best power supply decoupling performance is obtained with a 0.1 J!F ceramic capacitor in parallel with a 0.01 J!F chip capacitor decoupling each of the two groups of VAA pins to GND. The capacitors should be placed as close as possible to the device. The 10 J.LF capacitor is for low frequency power supply ripple; the 0.1 J!F and 0.01 J!F capacitors are for high-frequency power supply noise rejection. The analog ground plane should include all Bt454/455 ground pins, reference circuitry (RSET resistors, etc.), power supply bypass circuitry for the Bt454/455, analog output traces, and the video output connector. The Bt455 no-connect (N/C) pins should be tied directly to ground. RAMDACs 4 - 99 .. Bt454/455 PC Board Layout Considerations (continued) A linear regulator to filter the analog power supply is recommended if the power supply noise is ~ 200 mV. This is especially important when a switching power supply is used and the switching frequency is close to the raster scan frequency. Note that about 10% of power supply hum and ripple noise less than 1 MHz will couple onto the analog outputs. COMP DecoupIlng The COMP pin must be decoupled to VAA, typically using a 0.1 ILF ceramic capacitor. Low-frequency supply noise will require a larger value. Lead lengths should be minimized for best performance. If the display has a "ghosting" problem, additional capacitance in parallel with the COMP capacitor may help to fix the problem. Digital Signal Interconnect The digital inputs to the Bt454/455 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power and ground planes. Most noise on the analog outputs will be caused by excessive edge speeds (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The digital edge speeds should be no faster than necessary, as feedthrough noise is proportional to the digital edge speeds. Lower speed applications will benefit using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission line mismatch will exist if the line length reflection time is greater than 1/4 the signal edge time, resulting in ringing, overshoot, and undershoot that can generate noise onto the analog outputs. Line termination or reducing the line length is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (10 to 50 Cl). Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge speeds (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals. Ensure that the power pins for the clock driver are properly decoupled to minimize transients. Minimize edge speeds and ringing, using damping resistors (10 to 50 Cl) or parallel termination where necessary. If using parallel termination on digital signals, the resistors should be connected to the digital power and ground planes, not the analog power and ground planes. Analog Signal Interconnect The Bt454/455 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog outputs should have a source load resistor equal to the destination termination (via a clean isolated ground return path). The load resistor connection between the current output and GND should be as close as possible to the Bt454/455 to minimize reflections. Unused analog outputs should be connected to GND. Analog edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce high-frequency energy, reducing EMI and noise. Analog Output Protection The Bt454/455 analog outputs should be protected against high-energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figure 4 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 parts are low-capacitance, fast-switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7(01). 4 • 100 SECTION 4 Bt454/455 Broddree GP PC Board Layout Considerations (continued) ANALOG POWBR PLAN!! LI . . . . ._...J1rrT'-1..._ _ _ + SV (VCC) + r::t Cl Bt454/455 ~-~"'~P--P-~-~~-----"----""--- GROmm FS ADJUST 1------' (NJC)lOR I-----_-I--+----{ (I01l1)100 I---------+----{ (NJC) lOB I------------{ TO VIDEO CONNECTOR VAA IN4148 (9 DAC OtrrPllT ---4--- TOMONrrOR IN4148f9 GND Location Description C1, C7 C2, C3, C6, C8 C4, C5 10 J.1F tantwum capacitor 0.1 J.1F ceramic capacitor 0.01 J.1F ceramic chip capacitor ferrite bead 75 n 1% metBl film resistor 523 n 1% metBl film resistor L1 Rl, R2, R3 RSET Vendor Part Number Mallory CSR13G106KM Erie RPEll0Z5U104M50V Johanson Dielectrics X7R500S41W103KP Fair-Rite 2743001111 Dale CMF-55C Dale CMF-55C Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the Bt454/455. Figure 4. Substitution of devices with similar Typical Connection Diagram and Parts List. RAMDACs 4 - 101 Bt454/455 Application Information LDOUT Termination ECL Clock Generation To reduce reflections on the LDOUT signal, it should be terminated at the point furthest from the Bt454/455. A 330 n resistor to VCC and a 470 n resistor to GND should work in most cases. Due to the high clock rates at which the Bt454/455 may operate, it is designed to accept differential clock signals (CLOCK and CLOCK"'). These clock inputs are designed to be generated by ECL logic operating at +5 V. Note that the CLOCK and CLOCK'" inputs require termination resistors (typically a 220 n resistor to VCC and a 330 n resistor to GND), located as close as possible to the Bt454/455. LDOUT should have absolute minimal loading (one TTL load) to avoid display artifacts. Using Multiple Bt455s When using multiple Bt455s, each Bt455 should have its own power plane ferrite bead. Each Bt455 must still have its own individual RSET resistor, analog output termination resistors, power supply bypass capacitors, and COMP capacitor. TTL Clock Inter/acing Figure 5 illustrates interfacing the Bt454/455 to a TTL clock. The MC10H116 is operated from a single +5 V supply. The resistor network attenuates the TTL levels to MECL input levels. Although not shown, both the CLOCK and CLOCK'" lines require termination resistors (220 n resistor to VCC and 330 n resistor to GND), located as close as possible to the Bt454/455. 170 MHz applications require robust ECL clock signals with strong pull-down (-20 mA at VOH) and double termination for clock trace lengths greater than 2 inches. The CLOCK and CLOCK'" inputs must be differential signals due to the noise margins of the CMOS process. The Bt454/455 will not function using a single-ended CLOCK with CLOCK'" connected to ground. A 10K or 10KH ECL crystal oscillator that generates differential outputs, operating between +5 V and ground, may be interfaced directly to the B454/455, as shown in Figure 6. If the crystal oscillator generates only a single-ended output, a MC10H116 may be used to generate the differential clock signals, as illustrated in Figure 7. If the MC10H116 is not readily available, a MCIOHlOl, MC10HI05, or MC10H107 may be used. Although ECL works well using a single +5 V supply, care must be taken to isolate the TTL power supply lines from the ECL power supply. Further information on ECL design may be obtained in the MECL Device Data Catalog and the MECL System Design Handbook, by Motorola. +sv +-------f''-o::----a.ocK· q....-(F----~ a.ocK Figure 5. 4 - 102 SECTION 4 Inter/acing the Bt454/455 to a TTL Clock. Bt454/455 Application Information (continued) +5V 14 MONrrOR r-------------------~~auxx PRODucrs 330 +5V 97(11 Figure 6. Interfacing to a Differential ECL Oscillator. +5V +5V 14 r----------.~auxx MONrrOR PRODUcrs 220 Bt4S4/4SS 970B 330 L---_~----___IC1OCK· Figure 7. Interfacing to a Single-Ended ECL Oscillator. RAMDACs 4 - 103 Bt454/455 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load FS ADJUST Resistor Symbol Min Typ Max Units VAA TA RL 4.75 0 5.00 5.25 +70 Volts °C Ohms Ohms Max Units 7.0 Volts VAA+0.5 Volts +125 +150 +150 °C °C °C 220 °C 37.5 523 RSEf Absolute Maximum Ratings Parameter Symbol Min Typ VAA (measured to GND) Voltage on Any Signal Pin* GND-O.5 Analog Output Short Circuit Duration to Any Power Supply or Common ISC Ambient Operating Temperature Storage Temperature Junction Temperature TA 1S TJ Vapor Phase Soldering (1 minute) TVSOL indefinite -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. 4 - 104 SECTION 4 Bt454/455 DC Characteristics Parameter Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs (except CLOCK, CLOCK*) Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = I MHz, Vin = 2.4 V) Clock Inputs (CLOCK, CLOCK*) Differential Input Voltage Input High Current (Vin = 4.2 V) Input Low Current (Vin = 3.2 V) Input Capacitance (f = 1 MHz, Vin = 4.2 V) Digital Outputs Output High Voltage DO-D3 (lOH = -400 J.lA) LDOUT (lOH = -12 rnA) Output Low Voltage DO-D3 (lOL = 3.2 rnA) LDOUT (IOL = 24 rnA) 3-state Current (DO-D3) Output Capacitance Symbol Min Typ Max Units 4 4 4 Bits ±1/4 ±1/4 ±10 LSB LSB % Gray Scale IL IX. guaranteed Binary VIH VIL 1IH IlL CIN LlVIN IKIH lKIL CKIN VAA + 0.5 0.8 1 -1 2.0 GND-O.5 10 .6 Volts Volts IIA IIA pF 6 Volts 1 -1 IIA IIA 10 pF VOH Volts Volts 2.4 2.4 VOL Ial CDOlJf 0.4 0.5 10 10 Volts Volts IIA pF See test conditions on next page. RAMDACs 4 - lOS Bt454/455 DC Characteristics (continued) Parameter Analog Outputs Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Blank Level on lOR, lOB Blank Level on 100 or lOUT Sync Level on 100 or lOUT LSD Size DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 rnA) Symbol Min Typ Max Units 16.81 15.86 0.95 0 6.29 0 19.05 17.62 1.44 5 7.62 5 1.175 21.30 19.40 1.90 50 8.96 50 rnA rnA rnA VOC RAOur CAOur -1.0 Internal Reference Voltage VREF 1.18 Power Supply Rejection Ratio (COMP = 0.1 J.I.F, f = 1 KHz) PSRR 5 +1.4 50 20 1.22 0.5 1.26 ~ rnA ~ rnA % Volts kn pF Volts %/%lJ.VAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 n. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 4 - 106 SECTION 4 BnxKtree~ Bt454/455 AC Characteristics 135 MHz Devices 170 MHz Devices Parameter Clock Rate Symbol Min Typ Fmax Max Min Typ 170 110 MHz Devices Max Min Typ 135 Max Units 110 MHz RIW, CO, Cl Setup Time RIW, CO, Cl Hold Time 1 2 0 15 0 15 0 15 ns ns CE*LowTime CE* High Time CE* Asserted to Data Bus CE* Asserted to Data Valid CE* Negated to Data Bus 3-Stated 3 4 5 6 50 25 10 50 25 10 50 25 10 Write Data Setup Time Write Data Hold Time 8 9 35 10 35 10 35 10 ns ns LDOUT Pulse Width High LDOUT Pulse Width Low Clock to LooUT 10 11 12 9 9 4 11.5 11.5 4 13 13 4 ns ns ns Pixel and Control Setup Time Pixel and Control Hold Time 13 14 0 3 0 5 0 5 ns ns Clock Cycle Time Clock Pulse Width High Clock Pulse Width Low 15 16 17 5.88 2 2 7.4 3 3 9 3.6 3.6 ns ns ns Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time* Clock and Data Feedthrough* Glitch Impulse* Analog Output Skew 18 19 20 7 Pipeline Delay VAA Supply Current*· 75 75 15 15 15 ns 14.3 7.5 14.3 6 70 50 0 2 6 6 200 tbd 7.5 70 50 0 2 ns ns ns pV -sec pV -sec ns 6 6 Clocks 120 200 rnA 9 9 6 14.3 20 2 20 2 20 2 6 IAA 7.5 75 ns ns ns ns 70 50 0 2 6 6 150 tbd 6 Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 n. TTL input values are 0-3 V, with input rise/fall times S 4 ns, measured between the 10% and 90% points. ECL input values are 3.2-4.2 volts, with input rise/fall times S 2 ns, measured between 20% and 80% points. Timing reference points at 50% for inputs and outputs. Analog output load S 10 pF, OO-D3 output load S 75 pF. See timing notes in Figure 9. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the TTL digital inputs have a 1 ill resistor to ground and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 2x clock rate. **AtFmax. lAA(typ)atVAA=5.0V, TA=20·C. IAA (max) at VAA = 5.25 V, TA=O·C. RAMDACs 4· 107 .. Bt454/455 Timing Waveforms I R/W. co, Cl .2..- I VALID 3 ~I 4 fi s I V DO· 03 (READ) DATA OlIT (RIW -I) ....... f DO· D3 (WRITE) DATAIN(R/W-O) ./ J 8 I Figure 8. R t-!- MPU Read/Write Timing Dimensions .. 11 lDOlIT PO·p] (A·D). OL(A·D). SYNC., BLANK. 14 18 20 lOR, 100. lOB (IOlIT - BT4SS) 12 19 D.OCK 11 Note 1: Output delay time measured from 50% point of the rising clock edge to 50% point of full scale transition. Note 2: Output settling time measured from 50% point of full-scale transition to output settling within ±1/4LSB. Note 3: Output rise/fall time measured between 10% and 90% points of full-scale transition. Figure 9. 4 - 108 SECTION 4 Video Input/Output Timing. BfOd.{tree~ Bt454/455 Device Circuit Data ..----------<,..--.....- r -....... VAA >-"*--ro DACS IFI!IlDBACK .. Equivalent Circuit of the Reference Amplifier. Bt454/455 VAA 00·07 IOGarlOur SYNC· (100 ONLy) BLANK" -2OPP T RL C(lIray+lood) Equivalent Circuit of the Current Output (lOG or lOUT). RAMDACs 4 - 109 Bt454/455 Ordering Information Ambient Temperature Range Model Number Speed Package Bt454KPI 110 MHz 44-pin Plastic I-Lead 0·to+70·C Bt454KPJ135 135 MHz 44-pin Plastic I-Lead 0·to+70·C Bt454KPJ170 170 MHz 44-pin Plastic I-Lead O· to +70· C Bt455KPJ110 110 MHz 44-pin Plastic I-Lead O· to +70· C Bt455KPJ135 135 MHz 44-pin Plastic I-Lead 0·to+70·C Bt455KPJ170 170 MHz 44-pin Plastic I-Lead 0·to+70·C Revision History Datasheet Revision 4 - 110 Change from Previous Revision F Note added to pin description and applications section that LDOUT should have absolute minimal loading (one TTL load) to avoid display artifacts. G Expanded PCB layout section. H Added Bt455 part and description. I Expanded ESO and PCB Layout sections. SECTION 4 Bt458/883 Distinguishing Features Applications 110 MHz Pipelined Operation Multiplexed TIL Pixel Ports Triple 8-bit D/A Converters 256 x 24 Dual Port Color Palette 4 x 24 Dual Port Overlay Registers RS-343A Compatible RGB Outputs Bit Plane Read and Blink Masks Standard MPU Interface +5 V CMOS Monolithic Construction 84-pin Ceramic PGA Package • Typical Power Dissipation: 2 W High-Resolution Color Graphics • CAE/CAD/CAM • Image Processing • Video Reconstruction Product Description The Bt458/883 is a triple 8-bit RAMDAC designed specifically for high-performance, highresolution color graphics_ The architecture enables the display of 1280 x 1024 bit-mapped color graphics (up to 8 bits per pixel plus up to 2 bits of overlay information), minimizing the use of costly ECL interfacing, as most of the high speed (pixel clock) logic is contained on chip_ The mUltiple pixel ports and internal multiplexing enables TTL-compatible interfacing (up to 28 MHz) to the frame buffer, while maintaining the 110 MHz video data rates required for sophisticated color graphics_ Functional Block Diagram o.OCK* LD' CLOCK VAA MIL-STD-883C, Class B Monolithic CMOS 256 x 24 Color Palette 110 MHz RAMDAC™ GND FS ADJUST VREP -1-.---1 lOR PO-P1 (A-E) lOG 01.0 - OLI The Bt458/883 has a 256 x 24 color lookup table with triple 8-bit video D/A converters_ On-chip features include programmable blink rates, bit plane masking and blinking, color overlay capability, and a dual-port color palette RAM_ (A-E) lOB SYNC'" BLANK'" ---'r--\_.r-~_----' CE'" R/W co Cl Brooktree Corporation 9950 Barnes Canyon Rd_ San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 L458MOI Rev_ I 00-D7 4 - 111 The Bt458/883 generates RS-343A-compatible red, green, and blue video signals, and is capable of driving doubly terminated 75 n coax directly, without requiring external buffering_ - Bt458/883 Circuit Description MPU Interface As illustrated in the functional block diagram, the Bt458/883 supports a standard MPU bus interface, allowing the MPU direct access to the internal control registers and color/overlay palettes. The dual-port color palette RAM and dual-port overlay registers allow color updating without contention with the display refresh process. As illustrated in Table I, the CO and C 1 control inputs, in conjunction with the internal address register, specify which control register, color palette RAM entry, or overlay register will be accessed by the MPU. The 8-bit address register (ADDR0-7) is used to address the internal RAM and registers, eliminating the requirement for external address multiplexers. ADDRO corresponds to DO and is the least significant bit. To write color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be modified. The MPU performs three successive write cycles (red, green, and blue), using CO and C1 to select either the color palette RAM or overlay registers. During the blue write cycle, the 3 bytes of color information are concatenated into a 24-bit word and written to the location specified by the address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. ADDRa, b (counts modulo 3) ADDR0-7 (counts binary) Cl CO Addressed by MPU 00 01 10 x x x 1 1 1 red value green value blue value $xx 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 address register color palette RAM overlay color 0 overlay color 1 overlay color 2 overlay color 3 read mask register blink mask register command register test register $00 $01 $02 $03 $04 $05 $06 $07 4 - 112 SECTION 4 When accessing the color palette RAM, the address register resets to $00 after a blue read or write cycle to location $FF. When accessing the overlay registers, the address register increments to $04 following a blue read or write cycle to overlay register 3. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADDRa, ADDRb) that count modulo three. They are reset to zero when the MPU reads or writes to the address register. The MPU does not have access to these bits. The other 8 bits of the address register (ADDR0-7) are accessible to the MPU. Value $00 - $FF Table 1. To read color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be read. The MPU performs three successive read cycles (red, green, and blue), using CO and Cl to select either the color palette RAM or overlay registers. Following the blue read cycle, the address register increments to the next location, which the MPU may read by simply reading another sequence of red, green, and blue data. Address Register (ADDR) Operation. Bnxktree® Bt458/883 Circuit Description (continued) Additional Information Although the color palette RAM and overlay registers are dual-ported, if the pixel and overlay data is addressing the same palette entry being written to by the MPU during the blue write cycle, it is possible for one or more of the pixels on the display screen to be disturbed. A maximum of one pixel is disturbed if the write data from the MPU is valid during the entire chip enable time. Note that if an invalid address in loaded into the address register, data written to the device will be ignored and invalid data will be read by the MPU. Figure 1 illustrates the MPU read/write timing when accessing the Bt458/883. Accessing the control registers is also done through the address register in conjunction with the CO and C I inputs. as shown in Table 1. All control registers may be written to or read by the MPU at any time. The address register does not increment following read or write cycles to the control registers. facilitating read-modify-write operations. WW,CO,Cl CEO .. ~____V_AL_ID____J)(~___________________________________________________ \'---_ _ _----1/ DO - D7 (RIlAD) DO - D7 (WRITE) __________________________-J)(~_____ D_A_T_A_m_ovw ___=_O_)____ Figure 1. ~)(~____________________ MPU Read/Write Timing. RAMDACS 4· 113 Bt458/883 Circuit Description (continued) Frame Buffer Interface To enable pixel data to be transferred from the frame buffer at reasonable data rates (up to 28 MHz), the Bt458/883 incorporates internal latches and multiplexers. As illustrated in Figure 2, on the rising edge of LD*, sync and blank information, color (up to 8 bits per pixel), and overlay (up to 2 bits per pixel) information, for either four or five consecutive pixels, are latched into the device. Note that with this configuration, the sync and blank timing will be recognized only with four- or five-pixel resolution. Typically, the LD* signal is used to clock external circuitry to generate the basic video timing. Each clock cycle, the Bt458/883 outputs color information based on the (A) inputs, followed by the (B) inputs, etc., until all four or five pixels have been output, at which point the cycle repeats. The overlay inputs may have pixel tlmmg, facilitating the use of additional bit planes in the frame buffer to control overlay selection on a pixel basis, or they may be controlled by external character or cursor generation logic. To simplify the frame buffer interface timing, LD* may be phase shifted, in any amount, relative to CLOCK. This enables the LD* signal to be derived by externally dividing CLOCK by four or five, independent of the propagation delays of the LD* generation logic. As a result, the pixel and overlay data are latched on the rising edge of LD*, independent of the clock phase. Internal logic maintains an internal LOAD signal, synchronous to CLOCK, and is guaranteed to follow the LD* signal by at least one, but not more than four, clock cycles. This LOAD signal transfers the latched pixel and overlay data into a second set of latches, which are then internally multiplexed at the pixel clock rate (up to 110 MHz). If 4:1 multiplexing is specified, only one rising edge of LD* should occur every four clock cycles. If 5:1 mUltiplexing is specified, only one rising edge of LD* should occur every five clock cycles. Otherwise, the internal LOAD generation circuitry assumes it is not locked onto the LD* signal, and will continuously attempt to resynchronize itself to LD*. FI).p/ {A·E). OLO-OLI {A·E). SYNC·, BLANK· lOR. lOG. lOB CLOCK Figure 2. 4 • 114 SECTION 4 Video Input/Output Timing. Bt458/883 Circuit Description (continued) Color Selection Video Generation Each clock cycle, 8 bits of color information (PO-P7) and 2 bits of overlay information (OLO, aLl) for each pixel are processed by the read mask, blink mask, and command registers. Through the use of the control registers, individual bit planes may be enabled or disabled for display, and/or blinked at one of four blink rates and duty cycles. Every clock cycle, the selected 24 bits of color information (8 bits each of red, green, and blue) are presented to the three 8-bit D/A converters. The SYNC* and BLANK* inputs, pipelined to maintain synchronization with the pixel data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figure 3. To ensure that a color change due to blinking does not occur during the active display time (i.e., in the middle of the screen), the Bt458/883 monitors the BLANK* input to determine vertical retrace intervals. A vertical retrace interval is recognized by determining that BLANK* has been a logical zero for at least 256 LD* cycles. The varying output current from each of the D/A converters produces a corresponding voltage level, which is used to drive the color CRT monitor. Note that only the green output (lOG) contains sync information. Table 3 details how the SYNC* and BLANK* inputs modify the output levels. The processed pixel data is then used to select which color palette entry or overlay register is to provide color information. Note that PO is the LSB when addressing the color palette RAM. Table 2 illustrates the truth table used for color selection. The D/A converters on the Bt458/883 use a segmented architecture in which bit currents are routed to either the current output or GND by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabilizes the D/A converter's full scale output current against temperature and power supply variations. CR6 aLl OLO P7-PO Addressed by frame buffer 1 1 0 0 0 0 : 0 0 1 0 1 $00 $01 color palette entry $00 color palette entry $01 : : 1 0 x x x 0 0 0 1 1 Table 2. : : $FF $xx $xx $xx $xx color palette entry $FF overlay color 0 overlay color 1 overlay color 2 overlay color 3 Palette and Overlay Select Truth Table. RAMDACS 4· 115 - Bt458/883 Circuit Description (continued) RED. BLUE GREEN MA V MA V 19.05 0.714 26.1i1 1.000 -r----~._--------------------~~------willmm~ 1M 0.054 9.0S 0.340 -+------------t--------~--------------- BLACK mYEL 7.5JRE 0.00 0.000 7.62 0.286 0.00 0.000 ~----------~--~~--L-----------------B~Km~ 40lRB -1-_____________-'-...&..__________________ Note: 75 n doubly terminated load, RSET assumed on all levels. Figure 3. DATA DATA-SYNC BlACK BlACK-SYNC BLANK SYNC 100 IOR,IOB (rnA) 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 19.05 data + 1.44 data + 1.44 1.44 1.44 0 0 Note: Typical with full-scale lOG Table 3. 4 • 116 SECTION 4 RS-343A levels and tolerances Composite Video Output Waveforms. (rnA) Description WHITE = 523 n, VREF = 1.235 V. SYNC mVEL =26.67 rnA. SYNC* BLANK* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx RSET =523 n, VREF = 1.235 V. Video Output Truth Table. Bt458/883 Internal Registers Command Register The command register may be written to or read by the MPU at any time, and is not initialized. CRO corresponds to data bus bit DO. CR7 Multiplex select (0) 4: 1 multiplexing (1) 5: 1 multiplexing This bit specifies whether 4: 1 or 5: 1 multiplexing is to be used for the pixel and overlay inputs. If 4:1 is specified, the (E) pixel and (E) overlay inputs are ignored and should be connected to GND, and the LD* input should be 1/4 the CLOCK rate. If 5:1 is specified, all of the pixel and overlay inputs are used, and the LD* input should be 1/5 the CLOCK rate. Note that it is possible to reset the pipeline delay of the Bt458/883 to a fixed eight clock cycles. In this instance, each time the input multiplexing is changed, the Bt458/883 must again be reset to a fixed pipeline delay. CR6 RAM enable (0) use overlay color 0 (1) use color palette RAM CR5, CR4 Blink rate selection (00) (01) (10) (11) CR3 16 16 32 64 on, on, on, on, 48 16 32 64 off (25[75) off (SO/50) off (SO/50) off (SO/50) all blink enable (0) disable blinking (1) enable blinking CR2 OLO blink enable (0) disable blinking (1) enable blinking When the overlay select bits are 00, this bit specifies whether to use the color palette RAM or overlay color 0 to provide color information. These two bits control the blink rate cycle time and duty cycle, and are specified as the number of vertical retrace intervals. The numbers in parentheses specify the duty cycle (% on/off). If a logical one, this bit forces the all (A-E) inputs to toggle between a logical zero and the input value at the selected blink rate prior to selecting the palettes. A value of logical zero does not affect the value of the aLl (A-E) inputs. In order for overlay 1 bit plane to blink, bit CRI must be set to a logical one. If a logical one, this bit forces the OLO (A-E) inputs to toggle between a logical zero and the input value at the selected blink rate prior to selecting the palettes. A value of logical zero does not affect the value of the OLO (A-E) inputs. In order for overlay 0 bit plane to blink, bit CRO must be set to a logical one. RAMDACS 4· 117 .. Bt458/883 Internal Registers (continued) Command Register (continued) CRI OLl display enable (0) disable (I) enable CRO OLO display enable (0) disable (1) enable If a logical zero, this bit forces the OLl {A-E} inputs to a logical zero prior to selecting the palettes. A value of a logical one does not affect the value of the OLl {A-E} inputs. If a logical zero, this bit forces the OLO {A-E} inputs to a logical zero prior to selecting the palettes. A value of a logical one does not affect the value of the OLO {A-E} inputs. Read Mask Register The read mask register is used to enable (logical one) or disable (logical zero) a bit plane from addressing the color palette RAM. DO corresponds to bit plane 0 (PO (A-E}) and D7 corresponds to bit plane 7 (P7 (A-E}). Each register bit is logically ANDed with the corresponding bit plane input. This register may be written to or read by the MPU at any time and is not initialized. Blink Mask Register The blink mask register is used to enable (logical one) or disable (logical zero) a bit plane from blinking at the blink rate and duty cycle specified by the command register. DO corresponds to bit plane 0 (PO (A-E}) and D7 corresponds to bit plane 7 (P7 (A-E}). In order for a bit plane to blink, the corresponding bit in the read mask register must be a logical one. This register may be written to or read by the MPU at any time and is not initialized. 4 - 118 SECTION 4 Bt458/883 Internal Registers (continued) Test Register The test register provides diagnostic capability by enabling the MPU to read the inputs to the O/A converters. It may be written to or read by the MPU at any time, and is not initialized. When writing to the register, the upper 4 bits (04-07) are ignored. The contents of the test register are defmed as follows: 07-04 color information (4 bits of red, green, or blue) D3 low (logical one) or high (logical zero) nibble blue enable green enable red enable D2 01 DO , To use the test register, the host MPU writes to it, setting one, and only one, of the (red, green, blue) enable bits. These bits specify which 4 bits of color information the MPU wishes to read (RO-R3, 00--03, BO-B3, R4-R7, 04-07, or B4-B7). When the MPU reads the test register, the 4 bits of color information from the OAC inputs are contained in the upper 4 bits, and the lower 4 bits contain the (red, green, blue, low or high nibble) enable information previously written. Note that either the CLOCK must be slowed down to the MPU cycle time, or the same pixel and overlay data must be presented to the device during the entire MPU read cycle. For example, to read the upper 4 bits of red color information being presented to the O/A converters, the MPU writes to the test register, setting only the red enable bit. The MPU then proceeds to read the test register, keeping the pixel data stable, which results in 04-07 containing R4-R7 color bits, and DO-03 containing (red, green, blue, low or high nibble) enable information, as illustrated below: D7 D6 OS 04 R7 R6 R5 R4 D3 0 D2 0 Dl DO 0 RAMDACS 4 - 119 .. Bnmtree® Bt458/883 Pin Descriptions Pin Name Description BLANK'" Composite blank control input (ITL compatible). A logic zero drives the analog outputs to the blanking level, as illustrated in Table 3. It is latched on the rising edge of LD"'. When BLANK'" is a logical zero, the pixel and overlay inputs are ignored. SYNC'" Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source on the lOG output (see Figure 3). SYNC'" does not override any other control or data input, as shown in Table 3; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of LD"'. LD* Load control input (ITL compatible). The PO-P7 (A-E), OLO-OLl (A-E), BLANK"', and SYNC'" inputs are latched on the rising edge of LD"'. LD"', while it is either 1/4 or 1/5 tb" CLOCK rate, may be phase independent of the CLOCK and CLOCK'" inputs. LD'" may have any duty cycle, within the limits specified by the AC Characteristics section. PO-P7 (A-E) Pixel select inputs (TTL compatible). These inputs are used to specify, on a pixel basis, which one of the 256 entries in the color palette RAM is to be used to provide color information. Either four or five consecutive pixels (up to 8 bits per pixel) are input through this port. They are latched on the rising edge of LD"'. Unused inputs should be connected to GND. Note that the (A) pixel is output first, followed by the (B) pixel, etc., until all four or five pixels have been output, at which point the cycle repeats. OLD-aLl (A-E) Overlay select inputs (TTL compatible). These control inputs are latched on the rising edge of LD'" and, in conjunction with bit 6 of the command register, specify which palette is to be used for color information, as follows: aLl OLD CR6 = 1 0 0 1 1 0 1 0 1 color palette RAM overlay color 1 overlay color 2 overlay color 3 CR6=0 overlay overlay overlay overlay color color color color 0 1 2 3 When accessing the overlay palette, the PO-P7 (A-E) inputs are ignored. Overlay information bits (up to 2 bits per pixel) for either four or five consecutive pixels are input through this port. Unused inputs should be connected to GND. lOR, lOG, lOB Red, green, and blue video current outputs. These high impedance current sources are capable of directly driving a doubly terminated 75-ohm coaxial cable (Figure 4). VAA Analog power. AIl VAA pins must be connected. GND Analog ground. AIl GND pins must be connected. 4 • 120 SECTION 4 Bt458/883 Pin Descriptions (continued) Pin Name Description CaMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.01 JlF ceramic capacitor must be connected between this pin and VAA (Figure 4). Connecting the capacitor to V AA rather than to GND provides the highest possible power supply noise rejection. The CaMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to PC Board Layout Considerations for critical layout criteria. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal (Figure 4). Note that the IRE relationships in Figure 3 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on lOG is: RSET (0) = 11,294 * VREF (V) / lOG (rnA) The full-scale output current on lOR and lOB for a given RSET is: lOR, lOB (rnA) = 8,067 * VREF (V) / RSET (0) VREF Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 4, must supply this input with a 1.23 5 V (typical) reference. The use of a resistor network to generate the reference is not recommended, as any low-frequency power supply noise on VREF will be directly coupled onto the analog outputs. A 0.01 JlF ceramic capacitor is used to decouple this input to V AA, as shown in Figure 4. If VAA is excessively noisy, better performance may be obtained by decoupling VREF to GND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. CLOCK, CLOCK* Clock inputs. These differential clock inputs are designed to be driven by ECL logic configured for single supply (+5 V) operation. The clock rate is typically the pixel clock rate of the system. CE* Chip enable control input (TTL compatible). This input must be a logical zero to enable data to be written to or read from the device. During write operations, data is internally latched on the rising edge of CE* (Figure 1). Care should be taken to avoid glitches on this edge triggered input. R/W Read/write control input (TTL compatible). To write data to the device, both CE* and R/W must be a logical zero. To read data from the device, CE* must be a logical zero and R/W must be a logical one. R/W is latched on the falling edge of CE*. See Figure 1. CO, Cl Command control inputs (TTL compatible). CO and Cl specify the type of read or write operation being performed, as illustrated in Table 1. They are latched on the falling edge of CE*. DO-D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. RAMDACS 4 - 121 Bnxj{tree® Bt458/883 Pin Descriptions (continued) Signal Pin Signal Number BLANK* SYNC* LD* CLOCK* L9 MlO M9 CLOCK Pin Signal Number VAA VAA VAA VAA VAA VAA C12 Cll GND GND GND GND GND B12 Bll M6 B6 A6 COMP A12 BlO ClO M8 P5A P5B P5C P5D P5E K11 Ll2 K12 III 112 POA POB POC POD POE 01 02 HI H2 11 P6A P6B P6C P6D P6E H11 H12 012 011 F12 PIA PIB PIC PlO PIE 12 Kl Ll P7A P7B P7C P7D P7E Fll E12 Ell 012 011 CE* AS OLOA OLOB OLOC OLOD OLOE Al C2 Bl Cl RJW B8 A8 B7 D2 DO P2A P2B P2C P2D P2E L8 K2 12 K3 Ml 13 M2 M3 FSADJUST VREF Cl CO P3A P3B P3C P3D P3E lA M4 L5 M5 L6 OLlA OLlB OLlC OLlD OLlE 01 E2 El Fl F2 Mll LlO Lll KlO M12 100 AlO All B9 SECTION 4 lOB lOR L7 M7 A7 D2 D3 D4 A2 A3 D5 D6 B4 A4 B5 D7 P4A P4B P4C P4D P4E A9 C3 B2 B3 Dl 4 - 122 Pin Number BrIC 10 JJG FSADI VRBP N> l'IB SYNC· VAA lOR BIJ(" ID* Cl R/W CIJ(" eLK VAA (Xl VAA VAA P3B GND 4 Bt458/883 (TOP VIEW) P4I! - GND GND (]!* TJ1 P.lC PJ) D6 D5 PSA P.lB D4 m. DO P2A P2C pm III Dl 0lJlB OUI! OUB 0LlE FOB FID PIA PlD PlB I'D E1 OLOC am CLlA OUC CUD 1'00\ roc POO PlB PIC P2B A B C 0 B P G H K L M alignment marker (on top) 12 11 10 - PSB PSC PSB Rill P6C FQl P1B PlD VAA GND roM' I>IC PSA P.I) PM. AD P7A P7C P1B VAA GND lOB SYNC· l'IB N> VRBP FSADI JJG ID* BIJ(" lOR VAA eLK CLK" R/W CI VAA VAA co VAA GND P3B GND GND PJ) P.lC TJ1 rn" P.lB PSA ll5 D6 P2B P2C P2A DO D2 D4 I'D PlB PlD PIA FID FOB OLIB OUB OUI! 0lJlB Dl III P2B PIC PlB POO roc 1'00\ CLIO OUC 0LlA am OLOC f3 M L K H G P I! 0 C B A P4I! (BOTTOM VIEW) RAMDACS 4 • 123 Bt458/883 PC Board Layout Considerations PC Board Considerations Power Planes This product requires special attention to proper layout techniques to achieve optimum performance. Before beginning PCB layout, refer to the CMOS RAMDAC layout example found in Bt4511718 Evaluation Module Operation and Measurements. application note (AN-16). This application note can be found in Brooktree's 1990 Applications Handbook. Separate digital and analog power planes are necessary. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt458/883 power pins, VREF circuitry, and COMP and VREF decoupling. There should be at least a 1/8 inch gap between the digital power plane and the analog power plane. The layout should be optimized for lowest noise on the Bt458/883 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 13. This bead should be located within 3 inches of the Bt458/883 and provides resistance to switching currents, acting as a resistance at high frequencies. A low resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. A well-designed power distribution network is critical to eliminating digital switching noise. Ground planes must provide a low-impedance return path for the digital circuits. A minimum of a 6-layer PC board is recommended. The ground layer should be used as a shield to isolate noise from the analog traces with layer 1 (top) the analog traces, layer 2 the ground plane (preferably analog ground plane), layer 3 the analog power plane, using the remaining layers for digital traces and digital power supplies. The optimum layout enables the Bt458/883 to be located as close to the power supply connector and as close to the video output connector as possible. Ground Planes For optimum performance, a common digital and analog ground plane with tub isolation (at least a 1/8 inch gap) and connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector to preserve digital noise margins during MPU read cycles. Thus, the ground partitioning isolation technique is constrained by the noise margin degradation during digital readback of the Bt458/883. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. For maximum performance, a separate isolated ground plane for the analog output termination resistors, RSET resistor, and VREF circuitry should be used, as shown in Figure 13. Another isolated ground plane is used for the GND pins of the Bt458/883 and supply decoupling capacitors. 4 • 124 SECTION 4 Plane-to-plane noise coupling can be reduced by ensuring that portions of the digital power and ground planes do not overlay portions of the analog power and ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. Device Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Power Supply DecoupUng Best power supply decoupling performance is obtained with a 0.1 I1F ceramic capacitor in parallel with a 0.01 I1F chip capacitor decoupling each of four groups of VAA pins to GND. The capacitors should be placed as close as possible to the device. The 33 I1F capacitor is for low-frequency power supply ripple; the 0.1 I1F and 0.01 I1F capacitors are for high-frequency power supply noise rejection. Bt458/883 PC Board Layout Considerations (continued) A linear regulator to filter the analog power supply is recommended if the power supply noise is ~ 200 mV or greater than 10 LSBs. This is especially important when a switching power supply is used and the switching frequency is close to the raster scan frequency. Note that about 10% of power supply hum and ripple noise less than 1 MHz will couple onto the analo g outputs. COMP Decoupling The COMP pin must be decoupled to VAA, typically using a O.IIlF ceramic chip capacitor. Low-frequency supply noise will require a larger value. Lead lengths should be minimized for best performance so that the self-resonance frequency is greater than the LD* frequency. Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge speeds (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals. Ensure that the power pins for the clock driver are properly decoupled to minimize transients. Minimize edge speeds and ringing, using damping resistors (10 to 50 0) or parallel termination where necessary. If using parallel termination on digital signals, the resistors should be connected to the digital power and ground planes, not the analog power and ground planes. Analog Signal Interconnect If the display has a "ghosting" problem, additional capacitance in parallel with the COMP capacitor may help to fix the problem. The Bt458/883 should be located as close as possible to the output connectors to minimize noise pickUp and reflections due to impedance mismatch. Digital Signal Interconnect The digital inputs to the Bt458/883 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power and ground planes. Most noise on the analog outputs will be caused by excessive edge speeds (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The digital edge speeds should be no faster than necessary, as feedthrough noise is proportional to the digital edge speeds. Lower speed applications will benefit by using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission line mismatch will exist if the line length reflection time is greater than 1/4 the signal edge time, resulting in ringing, overshoot, and undershoot that can generate noise onto the analog outputs. Line termination or reducing the line length is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (10 to 50 0). The video output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog outputs should have a source load resistor equal to the destination termination (via a clean isolated ground return path). The load resis tor connection between the current output and GND should be as close as possible to the Bt458/883 to minimize reflections. Unused analog outputs should be connected to GND. Analog edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce high-frequency energy, reducing EMI and noise. Analog Output Protection The Bt458/883 analog outputs should be protected against high-energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figure 4 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 parts are low-capacitance, fastswitching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7001). RAMDACS 4 - 125 .. Bt458/883 PC Board Layout Considerations (continued) C9 Ll +SV(VCC) ClO Cl 8t458/883 GROUND (poWBRSUPPLY CONNECTOR) RSET FS ADJUST (NIC) lOR TO VIDEO (10m) lOG CONNECTOR (PLL) lOB VAA 0 lN414819 DAC TO MONITOR OUTPUT IN4148/9 OND Location Description C1-C4 C5-C7 C8, C9 C10 0.1 I1F ceramic capacitor 0.01 I1F ceramic chip capacitor 0.1 I1F ceramic capacitor 33 I1F tantalum capacitor ferrite bead 75 n 1% metal film resistor 1000 n 1% metal film resistor 523 n 1% metal film resistor 1.2 V voltage reference L1 R1, R2, R3 R4 RSEf Zl Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the Bt458/883. Figure 4. 4 • 126 SECTION 4 Substitution of devices with similar Typical Connection Diagram and Parts List. Bt458/883 Application Information Clock Inter/acing Due to the high clock rates at which the Bt458/883 may operate. it is designed to accept differential clock signals (CLOCK and CLOCK*). These clock inputs are designed to be generated by ECL logic operating at +5 V. Note that the CLOCK and CLOCK* inputs require termination resistors (220 n resistor to VCC and a 330 n resistor to GND). The termination resistors should be as close as possible to the Bt458/883. Typically. LD* is generated by dividing CLOCK by four or five (depending on whether 4:1 or 5:1 mUltiplexing was specified) and translating it to TTL levels. As LD* may be phase shifted relative to CLOCK. the designer need not worry about propagation delays in deriving the LD* signal. LD* may be used as the shift clock for the video DRAMs and to generate the fundamental video timing of the system (SYNC*. BLANK*. etc.). The CLOCK and CLOCK* inputs must be differential signals due to the noise margins of the CMOS process. The Bt458/883 will not function using a single-ended clock with CLOCK* connected to ground. It is recommended that the Bt438 Clock Generator Chip be used to generate the clock and load signals. It supports both the 4:1 and 5:1 input multiplexing of the Bt458/883. and will also optionally set the pipeline delay of the Bt458/883 to eight clock cycles. The Bt438 may also be used to interface the B t458/883 to a TTL clock. Figure 5 illustrates using the Bt438 with the Bt458/883 . +5V +5V 14 a.OCKf--------~...jCI.OCK MONITOR PRODUcrs 970E 330 Bt458/883 220 CLOCK·I-----~---_lcLOCK· Bt438 330 LDA~--------~LD· IK Figure 5. Generating the Bt458/883 Clock Signals. RAMDACS 4 • 127 .. Bt458/883 Application Information (continued) Setting the Pipeline De/ay The pipeline delay of the Bt458/883, although fixed after a power-up condition, may be anywhere from six to ten clock cycles. The Bt458/883 contains additional circuitry enabling the pipeline delay to be fixed at eight clock cycles. The Bt438 Clock Generator Chip supports this mode of operation when used with the Bt458/883. be synchronized. In this instance, the blink mask register should be $00 and the overlay blink enable bits a logical zero. Blinking may be done under software control via the read mask register and overlay display enable bits. To reset the Bt458/883, it should be powered up, with LD*, CLOCK, and CLOCK* running. Stop the CLOCK and CLOCK* signals with CLOCK high and CLOCK* low for at least three rising edges of LD*. There is no upper limit on how long the device can be held with CLOCK and CLOCK* stopped. Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. Restart CLOCK and CLOCK* so that the first edge of the signals is as close as possible to the rising edge of LD* (the falling edge of CLOCK leads the rising edge of LD* by no more than 1 clock cycle or follows the rising edge of LD* by no more than 1.5 clock cycles). When restarting the clocks, care must be taken to ensure that the minimum clock pulse width is not violated. The resetting of the Bt458/883 to an eight clock cycle pipeline delay does not reset the blink counter circuitry. Therefore, if the multiple Bt458/883s are used in parallel, the on-chip blink counters may not 4 • 128 SECTION 4 ESD and Latchup Considerations All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay V AA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. Bt458/883 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage FS ADJUST Resistor Symbol Min Typ Max Units VM TA RL VREF 4.5 -55 5.0 5.5 +125 Volts °C Ohms Volts Ohms 1.20 RSET CLOCK. CLOCK· Inputs Input High Voltage Input Low Voltage Differential Voltage 37.5 1.235 523 1.26 VAA+0.5 VAA-1.6 Volts Volts mV Max Units 7.0 Volts VAA+0.5 Volts TJ +125 +150 +175 °C °C °C TSOL 260 °C aJC 15 °C/W aJA 25 °C/W 3.025 W VAA-1.0 GND-O.5 600 Absolute Maximum Ratings Parameter Symbol Min Typ VAA (measwed to GND) Voltage on Any Digital Pin Analog Output Short Circuit Duration to Any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds. 1/4" from pin) Power Dissipation GND-O.5 indefinite ISC TA TS -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RAMDACS 4 - 129 Bt458/883 DC Characteristics Parameter Analog Outputs Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity** Coding Symbol 8 8 8 Bits ±l ±1 ±5 LSB LSB % Gray Scale Binary IKlH IKn. CKlN SECTION 4 Units guaranteed Clock Inputs (CLOCK, CLOCK·) Input High Current (Yin = VAA) Input Low Current (Yin = 0 V) Input Capacitance**. 4· 130 Max n. IIH IIL CIN See test conditions on next page. Typ IX. Digital Inputs (except CLOCK, CLOCK·) Input High Voltage Input Low Voltage Input High Current (Vin = VAA) Input Low Current (Yin = 0 V) Input Capacitance*·· Digital Outputs (OO-D7) Output High Voltage (IOH =~OO IJA) Output Low Voltage (IOL = 6.4 rnA) 3-state Current Output Capacitance*** Min VlH 2.0 vn. VOO 4 0.8 10 -10 10 4 10 -10 10 Volts Volts IIA IIA pF IIA IIA pF Volts 2.4 VOL 0.4 Volts IOZ 10 10 IIA coour pF Bt458/883 DC Characteristics (continued) Parameter Symbol Analog Outputs Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Blank Level on lOR, lOB Blank Level on lOG Sync Level on lOG DAC-to-DAC Matching**** TA = +25, +125 °C TA=-55°C Output Compliance Output Capacitance*** VOC CAOUT Min Typ Max Units 17.69 16.74 0.95 -10 6.29 -10 19.05 17.62 1.44 5 7.62 5 20.40 18.50 1.90 50 8.96 50 rnA rnA rnA 3 5 7 +1.2 20 % % Volts pF -1.0 j.iA rnA j.iA Voltage Reference Input Leakage Current (VREF = 1.235 V) IREF 10 j.iA Power Supply Rejection Ratio*** (COMP = 0.01 JlF, f = 1 KHz) PSRR 0.5 %/%!:NAA Test conditions (unless otherwise specified): 100% tested at VAA = 4.5 V and 5.5 V, TA = -55°,25°, and 125° C, RSET = 523 n ± 0.1%, VREF = 1.235 V. Typical values are based on nominal temperature, i.e., room and nominal voltage, i.e., 5 V. **Guaranteed by design, not tested. ***Derived from characterization (TA = 25° C, VAA = 5 V ± 10%), not tested. These parameters are controlled via design or process parameters and are not directly tested. They are characterized upon initial design release and upon design changes which could affect them. ****Computed by the formula: (max refwhite - min refwhite / max ref-white) * 100 RAMDACS 4 - 131 .. Bt458/883 AC Characteristics Parameter Clock Rate**** LD* Rate**** Symbol Min Typ Fmax LOmax Max Units 110 27.5 MHz MHz R/W, CO, Cl Setup Time R/W, CO, Cl Hold Time 1 2 0 15 ns ns CE*LowTime CE* High Time CE* Asserted to Data Bus Driven CE* Asserted to Data Valid CE* Negated to Data Bus 3-Stated 3 4 5 6 7 50 25 8 ns ns ns ns ns Write Data Setup Time Write Data Hold Time 8 9 35 3 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 10 11 3 2 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time 12 13 9.09 4 4 ns ns ns 36.36 15 15 ns ns ns LD* Cycle Time**** LD* Pulse Width High Time LD* Pulse Width Low Time Analog Output Rise/Fall Time**** Clock and Data Feedthrough** VAA Supply Current*** 14 15 16 17 75 15 18 4 -23 ns db IAA 550 rnA Test conditions (unless otherwise specified): 100% testing at VAA =4.5 V and 5.5 V with TA =-55°,25°, and 125°C. RSET = 523 n ± 0.1 %, VREF = 1.235 V. TTL input values are 0-3 V, with input rise/fall times ~ 4 ns, measured between the 10% and 90% points. ECL input values are VAA-0.8 to VAA-1.8 V, with input rise/fall times ~ 2 ns, measured between the 20% and 80% points. Analog output with doubly terminated 50 n line. DO-D7 output load - 75 pF. See timing notes in Figure 6. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. **Derived from characterization (TA = 25°C, VAA =5 V ± 10%), not tested. These parameters are controlled via design or process parameters and are not directly tested. They are characterized upon initial design release and upon design changes which could affect them. ***IAA (max) is measured at Fmax, with VAA = 5.5 V, 100% tested at TA = _55° C. ****Fmax 100% tested at TA = 125° C and VAA =4.5 V. 4 - 132 SECTION 4 Bt458/883 Timing Waveforms 17 16 PO-P7 (A-EI. OLO-OLI (A-EI. SYNC·, BLANK'" DATA 10 II lOR. lOG. lOB (IOlIT -- BT457) - - - - - - j [. 12 CLOCK 14 Note 1: Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition for data only_ Note 2: Output rise/fall time measured between 10% and 90% points of full-scale transition. Figure 6. Video Input/Output Timing. RAMDACS 4 - 133 Bt458i883 Timing Waveforms (continued) L RtW. co. Cl f-2-- 1 VALID \ J 3 CE' 4 s I V DO • D7 (READ) DATAOUf(R/W=I) ....... t DO· D7 (WRITE) ::::j DATA IN (R/W=O) 1\ 8 I Figure 7. f-L- MPU Read/Write Timing Dimensions. Ordering Information Model Number MTBF* (hours) Package Bt458SG883 .510 x 106 84-pin CeramicPGA *MTBF is calculated per MIL Handbook 217. 4 - 134 SECTION 4 " I 6 Ambient Temperature Range _55 0 to +125 0 C Preliminary Information This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. Distinguishing Features Applications • 135, 110, 80 MHz Operation • 1: I, 4: I, or 5: 1 Multiplexed Pixel Ports 256 x 24 Color Palette RAM 16 x 24 Overlay Color Palette I x to 16x Integer Zoom Support • I, 2, 4, or 8 Bits per Pixel • Frame Buffer Interleave Support • Pixel Panning Support On-Chip User-Definable 64 x 64 Cursor Programmable Setup (0 or 7.5 IRE) X Windows Support for Overlays/Cursor • 132-pin PGA or PQFP Package • • • • High-Resolution Color Graphics CAE/CAD/CAM Image Processing Video Reconstruction CLOCK VAA GND 135 MHz Monolithic CMOS 256 x 24 Color Palette RAMDAC™ Related Products Product Description • Bt438, Bt439 • Bt460, Bt462, Bt468 The Bt459 triple 8-bit RAMDAC is designed specifically for high-performance, highresolution color graphics. The multiple pixel ports and internal multiplexing enable TTLcompatible interfacing to the frame buffer, while maintaining the 135 MHz video data rates required for sophisticated color graphics. Functional Block Diagram a..OCK* Bt459 FS ADJUST VREF L--l/r-t- CQMP On chip features include a 256 x 24 color palette RAM, 16 x 24 overlay color palette RAM, programmable 1:1,4:1, or 5:1 input mUltiplexing of the pixel and overlay ports, bit plane masking and blinking, programmable setup (0 or 7.5 IRE), pixel panning support, Ix to 16x integer zoom support, and independent cursor generation. lOR PO·p? (A·E) lOG OLO·OL3 (A·E) Pixel data may be input as I, 2, 4, or 8 bits per pixel. Overlay and cursor information may optionally be enabled on a pixel-by-pixel basis for X Windows hardware support. lOB OLE(A·E) P!L SYNC· BLANK" The Bt459 has an on-chip three-color 64 x 64 pixel cursor and a three-color full-screen (or fullwindow) cross hair cursor. The PLL current output enables the synchronization of multiple devices with sub-pixel resolution. Olo R/W CO Cl Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 L459001 Rev. K DO·D7 4 - 13S Bt459 Circuit Description MPU Interface As illustrated in the functional block diagram, the Bt459 supports a standard MPU bus interface, allowing the MPU direct access to the internal control registers and color palettes. The dual-port color palette RAMs and dual-port overlay RAM allow color updating without contention with the display refresh process. As illustrated in Table 1, the CO and Cl control inputs, in conjunction with the internal address register, specify which control register or color palette location will be accessed by the MPU. The 16-bit address register eliminates the requirement for external address multiplexers. ADDRO is the least significant bit. To write color data, the MPU loads the address register with the address of the primary color palette RAM, overlay RAM, or cursor color register location to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using CO and C1 to select either the primary color palette RAM, overlay RAM, or cursor color registers. After the blue write cycle, the address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. Reading color data is similar to writing, except the MPU executes read cycles. When accessing the color palette RAM, overlay RAM, or cursor color registers, the address register increments after each blue read or write cycle. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADDRa, ADDRb) that count modulo three. They are reset to zero when the MPU reads or writes to the address register. The MPU does not have access to these bits. The other 12 bits of the address register (ADDRO-ll) are accessible to the MPU. ADDR12-ADDRI5 are always a logical zero. ADDRO and ADDR8 correspond to DO. The only time the address register resets to $0000 is after accessing location $OFFF (due to wraparound). ADDRO-15 Cl, CO Addressed by MPU $xxxx $xxxx $OOOO-$OOFF $0100 address register (ADDR0-7) address register (ADDR8-15) reserved overlay color 0* $010F 00 01 10 10 10 10 $0181 10 : : $0183 10 cursor color register 1* cursor color register 2* cursor color register 3* $0200 $0201 $0202 $0203 $0204 $0205 $0206 $0207 $0208 $0209 $020A $020B $020C $020D $020E $0220 $0300 $0301 $0302 $0303 $0304 $0305 $0306 $0307 $0308 $0309 $030A $030B $030C $0400-$07FF 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 ID register ($4A) command register_O command register_l command register_2 pixel read mask register reserved ($00) pixel blink mask register reserved ($00) overlay read mask register overlay blink mask register interleave register test register red signature register green signature register blue signature register revision register cursor command register cursor (x) low register cursor (x) high register cursor (y) low register cursor (y) high register window (x) low window (x) high window (y) low window (y) high window width low register window width high register window height low register window height high register cursor RAM $OOOO-$OOFF 11 color palette RAM* : : overlay color 15* *Indicates requires three tead/write cycles-ROB. Table 1. 4 - 136 SECTION 4 Address Register (ADDR) Operation. Bt459 Circuit Description (continued) Although the color palette RAM, overlay RAM, and cursor color registers are dual-ported, if the pixel and overlay data is addressing the same palette entry being written to by the MPU during the write cycle, it is possible for one or more of the pixels on the display screen to be disturbed. A maximum of one pixel is disturbed if the write data from the MPU is valid during the entire chip enable time. Accessing the control registers and cursor RAM is also done through the address register in conjunction with the CO and Cl inputs, as shown in Table 1. All control registers may be written to or read by the MPU at any time. When accessing the control registers and cursor RAM, the address register increments following a read or write cycle. Note that if an invalid address is loaded into the address register, data written to the device will be ignored and invalid data will be read by the MPU. Figure I illustrates the MPU read/write timing of the Bt459. Bt459 Reading/Writing Color Data (RGB Mode) To write color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using CO and Cl to select either the color palette RAM or the overlay registers. After the blue write cycle, the address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. Reading color data is similar to writing, except the MPU executes read cycles. This mode is useful if only an 8-bit data bus is available. Each Bt459 is programmed to be a red, green, or blue RAMDAC, and will respond only to the In this assigned color read or write cycle. application, the Bt459s share a common 8-bit data bus. The CE* inputs of all three Bt459s must be asserted simultaneously only during color read/write cycles and address register write cycles. When accessing the color palette RAM, the address register resets to $00 after a blue read or write cycle to location $FF. When accessing the overlay registers, the address register increments to $04 following a blue read or write cycle to overlay register 3. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits that count modulo three. They are reset to zero when the MPU reads or writes to the address register. The MPU does not have access to these bits. The other 8 bits of the address register (ADDRO-7) are accessible to the MPU. ww.rn.Q CE" DO· D7 (READ) DO· D7 (WRITE) ====><~ __ VMID ____~)(~_________________________________________ \'--_____--J/ --------------------~~ DATAOUT~=I) ___ =:»------------------- ________________________~)(~_____D_A_TA ___ m~ ___._~____~)(~___________________ Figure 1. MPU Read/Write Timing. RAMDACs 4· 137 Bt459 Circuit Description (continued) Frame Buffer Interface To enable pixel data to be transferred from the frame buffer at TIL data rates, the Bt459 incorporates internal latches and multiplexers. As illustrated in Figure 2, on the rising edge of LD*, sync and blank information, color, and overlay information, for either one, four, or five consecutive pixels, are latched into the device. Note that with this configuration, the sync and blank timing will be recognized only with one, four, or five pixel resolution. Typically, the LD* signal is used to clock external circuitry to generate the basic video timing and to clock the video DRAMs. For 4:1 or 5:1 input mUltiplexing, the Bt459 outputs color information each clock cycle based on the {A} inputs, followed by the {B} inputs, etc., until all four or five pixels have been output, at which point the cycle repeats. In the 1: 1 input mUltiplexing mode, the {B}, {C}, {D}, and {E} inputs are ignored. The overlay inputs may have pixel timing, facilitating the use of additional bit planes in the frame buffer to control overlay selection on a pixel basis, or they may be controlled by external circuitry. To simplify the frame buffer interface timing, LD* may be phase shifted, in any amount, relative to CLOCK. This enables the LD* signal to be derived by externally dividing CLOCK by four or five, independent of the propagation delays of the LD* generation logic. As a result, the pixel and overlay data are latched on the rising edge of LD*, independent of the clock phase. Internal logic maintains an internal LOAD signal, synchronous to CLOCK, and is guaranteed to follow the LD* signal by at least one, but not more than three, clock cycles. This LOAD signal transfers the latched pixel and overlay data into a second set of latches, which are then internally multiplexed at the pixel clock rate. If 4:1 mUltiplexing is specified, only one rising edge of LD* should occur every four clock cycles. If 5:1 mUltiplexing is specified, only one rising edge of LD* should occur every five clock cycles. Otherwise, the internal LOAD generation circuitry assumes it is not locked onto the LD* signal, and will continuously attempt to resynchronize itself to LD*. LD* PO-PI (A-E), OLE (A-E) OLO-OL3(A-E), SYNC·, BLANK· lOR, lOG, lOB, PIL a.OCK Figure 2. 4· 138 SECTION 4 Video Input/Output Timing. BllXKtree~ Bt459 Circuit Description (continued) If 1: 1 multiplexing is specified, LO· is also used for clocking the Bt459 (at a maximum of 50 MHz). The rising edge of LO· still latches the PO-P7 (A), OLO-OL3 (A), OLE (A), SYNC·, and BLANK· inputs. However, analog information is output following the rising edge of LO· rather than CLOCK. Note that CLOCK must still run, but is ignored. Pixel Panning To support pixel panning, command register_l specifies by how many clock cycles to pan. Only the pixel inputs and underlays are panned--overlays and cursors are not. Panning is done by delaying SYNC· and BLANK· an additional one, two, three, or four clock cycles. Read and Blink Masking If 0 pixel panning is specified, pixel (A) is output first, followed by pixel (B), etc., until all four or five pixels have been output, at which point the cycle repeats (note that this asswnes the interleave select is pixel (A)). Each clock cycle, 8 bits of color information (PO-P7) and 4 bits of overlay information (OLO-OL3) for each pixel are processed by the read mask, blink mask, and command registers. Through the use of the control registers, individual pixel and overlay inputs may be enabled or disabled for display, and/or blinked at one of four blink rates and duty cycles. If 1 pixel panning is specified, pixel (B) wiII be fust, followed by pixel (C), etc. Pixel (A) will have been processed during the last clock cycle of the blanking interval, and wiII not be seen on the display screen. At the end of the active display line, pixel (A) will be output. Pixels (B), (C), (O), and (E) will be output during the blanking interval, and will not be seen on the display screen. To ensure that a color change due to blinking does not occur during the active display time (i.e., in the middle of the screen), the Bt459 monitors the BLANK· input to determine vertical retrace intervals (any BLANK· pulse longer than 256 LO. cycles). The processed pixel data is then used to select which color palette entry or overlay register is to provide color information. Note that PO is the LSB when addressing the color palette RAMs, and OLO is the LSB when addressing the overlay palette RAM. Table 4 illustrates the truth table used for color selection. The process is similar for panning by two, three, or four pixels. Note that when a panning value other than 0 pixels is specified, valid pixel data must be loaded into the Bt459 during the first LO· cycle that BLANK. is a logical zero. In the 1: 1 multiplex mode, 0 pixel panning should be specified. Note that the cursor position does not change relative to the edge of the display screen during panning. Bits per Pixel Pixels per LD* (1:1 muxing) Pixels per LD· (4:1 muxing) Pixels per LD* (5:1 muxing) Colors Displayed 1 2 4 8 8 N/A N/A N/A 32 16 8 4 40 20 10 5 2 4 16 256 Table 2. Block Mode Operation. RAMDACs 4 • 139 - Bt459 Circuit Description (continued) Pixel Zoom The Bt459 supports Ix to I6x integer zoom through the use of pixel replication. Only the PO-P7 inputs are zoomed. If 2x zooming is specified, the (A} pixel is output for two clock cycles, followed by the (B} pixel for two clock cycles, etc. 3x zooming is similar, except each pixel is output for three clock cycles. For 1: 1 mUltiplexing, only the (A} pixel is output. the appropriate number of LD* cycles until new PO-P7 information is needed. OLO-OL3, OLE, SYNC*, and BLANK* information are still latched every LD'" cycle. Note that in the 1:1 multiplex mode, Ix zoom must be specified. Also, while in the block mode (1, 2, or 4 bits pixel), Ix zoom must be specified. Figure 3 illustrates the zoom timing. Block Mode Operation Note that LD* must always be the pixel clock (1:1 multiplex mode) or 1/4 or 1/5 the CLOCK rate. Regardless of the zoom factor, PO-P7 data is latched every LD* cycle. During 2x zoom, new PO-P7 data must be presented every two LD* cycles. During 3x zoom, new PO-P7 data must be presented every three LD* cycles. The pixel data must be held at the PO-P7 (A-E} inputs for The Bt459 supports loading of pixel data at 1, 2, 4, or 8 bits per pixel. Only the PO-P7 inputs are affected. Note that LD* must always be the pixel clock (1:1 multiplex mode) or 1/4 or 115 the CLOCK rate, regardless of the block mode. Regardless of the block mode, PO-P7 data is latched every LD'" cycle. 1 Bit per Pixel (RAI-RA7 = 0) RAO= 2 B its per Pixel (RA2-RA7 = 0) RAl,RAO= 4 Bits per Pixel (RA4-RA7 = 0) RA3-RAO= 8 Bits per Pixel RA7-RAO= P7A P6A P7A, P6A P5A,P4A P3A,P2A PIA,POA P7B, P6B (4:1) P5B, P4B (4:1) P3B, P2B (4:1) PIB, POB (4:1) P7C, P6C (4:1) P5C, P4C (4:1) P3C, P2C (4:1) PIC, POC (4:1) P7D, P6D (4:1) P5D, P4D (4:1) P3D, P2D (4:1) PlO, POD (4:1) P7E, P6E (5:1) P5E, P4E (5:1) P3E, P2E (5:1) PIE, POE (5:1) P7A, P6A, P5A, P4A P3A, P2A, PIA, POA P7B, P6B, P5B, P4B (4:1) P3B, P2B, PIB, POB (4:1) P7C, P6C, P5C, P4C (4:1) P3C, P2C, PIC, Poe (4:1) P7D, P6D, P5D, P4D (4:1) P3D, P2D, PlO, POD (4:1) P7E, P6E, P5E, P4E (5:1) P3E, P2E, PIE, POE (5:1) P7A,P6A,P5A,P4A,P3A,P2A,PIA,POA P7B, P6B, P5B, P4B, P3B, P2B, PIB, POB (4:1) P7C, P6C, P5C, P4C, P3C, P2C, PIC, POC (4:1) P7D, P6D, P5D, P4D, P3D, P2D, PlO, POD (4:1) P7E, P6E, P5E, P4E, P3E, P2E, PIE, POE (5:1) : POA P7B (4:1) P6B (4:1) : POB (4:1) P7C (4:1) P6C (4:1) : POC (4:1) P7D (4:1) P6D (4:1) : POD (4:1) P7E (5:1) P6E (5:1) : POE (5:1) Note: Each line represents one pixel clock cycle. A column represents one LD* cycle loading new PO-P7 data. All entries with "4: 1" descriptor are also valid for 5: 1 mode. Table 3. 4 - 140 Block Mode Operation (RA = Color Palette RAM Address). SECTION 4 Bt459 Circuit Description (continued) For 8 bits per pixel, new PO--P7 information must be presented every LD* cycle. For 4 bits per pixel, new PO-P7 information must be presented every two LD* cycles. For 2 bits per pixel, new PO--P7 information must be presented every four LD* cycles. For 1 bit per pixel, new PO-P7 information must be presented every eight LD* cycles. Tables 2 and 3 show the block mode operation, and the addressing of the color palette RAM. Figure 4 illustrates the block mode timing (4 bits per pixel). Note that in the 1:1 multiplex mode, 8 bits per pixel must be specified. Also, for block modes other than 8 bits per pixel, a 0 pixel interleave must be selected. The pixel data must be held at the PO--P7 inputs for the appropriate number of LD* cycles until new PO-P7 information is needed. OLO-OL3, OLE, SYNC*, and BLANK* information are still latched every LD* cycle. LD' OLO·OL3 (A. E). SYNC"', BLANK·, OLE(A·E} PO·P7(A.E} __~x~____~x~____~x~____~x~____ __~x~______________~x~_____________ ____I A A B B C COO = OUfPUT SEQUENCE Figure 3. Zoom Input Timing (8 Bits per Pixel, 2x Zoom). LD' OLO·OL3(A·E}. SYNC·, BLANK·, OLE (A·E) PO·P7 (A·E) __~x~____~x~____~x~____~x~____ __~x~____________~x~____________ UA BLANK· -----/ LA UA=P4-P7 UB=P4-P7 UC=P4-P7 UD=P4-P7 UB (A); (B); (C); (O); LB UC LC UD LD = OUTPUT SEQUENCE LA=PO-P3 (A) LB=PO-P3 (B) LC=PO-P3 (C) LD=PO-P3 (O} Figure 4. Block Mode Input Timing (4 Bits per Pixel, Ix Zoom, 4:1 Multiplexing). RAMDACs 4 - 141 .. Bt459 Circuit Description (continued) On-Chip Cursor Operation (0,0) enables the color palette RAM and overlay RAM to be selected as normal. Each "plane" of cursor information may also be independently enabled or disabled for display via the cursor command register (bits CR47 and CR46). The Bt459 has an on-chip, three-color" 64 x 64 pixel user-definable cursor. The cursor operates only with a noninterlaced video system. The cursor pattern and color may be changed by changing the contents of the cursor RAM. The pattern for the cursor is provided by the cursor RAM, which may be accessed by the MPU at any time. Cursor positioning is done via the cursor (x,y) register. Note that the Bt459 expects (x) to increase going right, and (y) to increase going down, as seen on the display screen. The cursor (x) position is relative to the first rising edge of LD* following the falling edge of SYNC*. The cursor (y) position is relative to the second sync pulse during vertical blanking. (See Figure 5.) The cursor is centered about the value specified by the cursor (x,y) register. Thus, the cursor (x) register specifies the location of the 31st column of the 64 x 64 array (assuming the columns start with 0 for the left-most pixel and increment to 63). Similarly, the cursor (y) register specifies the location of the 31st row of the 64 x 64 array (assuming the rows start with o for the top-most pixel and increment to 63). Three-Color 64 x 64 Cursor The 64 x 64 x 2 cursor RAM provides2 bits of cursor information every clock cycle during the 64 x 64 cursor window, selecting the appropriate cursor color register as follows: plane I planeO cursor color 0 0 1 1 0 1 0 1 cursor not displayed cursor color register 1 cursor color register 2 cursor color register 3 sYNC·~ t--x~ CURSOR(X.Y) _---+---t':---/0 Q 03 OS. D4 red select green select blue select 145 mVref. select result CURSOR - - - - - - - ' D7-D4 0000 1010 1001 0110 0101 IfD3= 1 normal operation red DAC compared to blue DAC red DAC compared to 150 mVreference green DAC compared to blue DAC green DAC compared to 150 mV reference IfD3=O - - red> blue red> 150mV green> blue green> 150 mV blue>rcd red < 145mV blue> green green < 145 mV The above table lists the valid comparison combinations. A logical one enables that function to be compared; the result is D3. The comparison result is strobed into D3 on the left edge of the 64 x 64 cursor area. The output levels of the DACs should be constant for 5 ).ls before the left edge of the cursor. For normal operation, D3-D7 must be a logical zero. 4 • 158 SECTION 4 Bt459 Internal Registers (continued) Cursor Command Register This command register is used to control various cursor functions of the Bt459. It is not initialized. and may be written to or read by the MPU at any time. CR40 corresponds to data bus bit DO. CR47 64 x 64 cursor planel display enable Specifies whether plane 1 of the 64 x 64 cursor is to be displayed (logical one) or not (logical zero). (0) disable planel (1) enable planel CR46 64 x 64 cursor planeO display enable Specifies whether planeO of the 64 x 64 cursor is to be displayed (logical one) or not (logical zero). (0) disable planeO (1) enable planeO CR45 Cross hair cursor plane 1 display enable Specifies whether planel of the cross hair cursor is to be displayed (logical one) or not (logical zero). (0) disable planel (1) enable plane 1 CR44 Cross hair cursor planeO display enable (0) disable planeO (1) enable planeO CR43 Cursor format (0) XOR (1) OR CR42. CR41 Cross hair thickness (00) (01) (10) (11) CR40 1 3 5 7 pixel pixels pixels pixels Cursor blink enable (0) blinking disabled (1) blinking enabled Specifies whether planeO of the cross hair cursor is to be displayed (logical one) or not (logical zero). Note that planeO and planel contain the same information. If both the 64 x 64 cursor and the cross hair cursor are enabled for display. this bit specifies whether the contents of the cursor RAM are to be logically exclusive-ORed (logical zero) or ORed (logical one) with the cross hair cursor. This bit specifies whether the vertical and horizontal thickness of the cross hair is one. three. five. or seven pixels. The segments are centered about the value in the cursor (x.y) register. This bit specifies whether the cursor is to blink (logical one) or not (logical zero). If both cursors are displayed. both will blink. The blink rate and duty cycle are as specified by command register_O. RAMDACs 4 - 159 Bt459 Internal Registers (continued) Cursor (x,y) Registers These registers are used to specify the (x,y) coordinate of the center of the 64 x 64 pixel cursor window, or the intersection of the cross hair cursor. The cursor (x) register is made up of the cursor (x) low register (CXLR) and the cursor (x) high register (CXHR); the cursor (y) register is made up of the cursor (y) low register (CYLR) and the cursor (y) high register (CYHR). They are not initialized and may be written to or read by the MPU at any time. The cursor position is not updated until the vertical retrace interval after CYHR has been written to by the MPU. CXLR and CXHR are cascaded to form a 12-bit cursor (x) register. Similarly, CYLR and CYHR are cascaded to form a 12-bit cursor (y) register. Bits D4-07 of CXHR and CYHR are always a logical zero. Cursor (x) High Cursor (x) Low (CXLR) (CXHR) OataBit D3 D2 D1 DO D7 D6 OS D4 D3 D2 Dl DO X Address Xll XIO X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Cursor (y) High (CYHR) Cursor (y) Low (CYLR) OataBit D3 D2 01 DO 07 D6 05 D4 03 D2 D1 DO Y Address Yll YI0 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Yl YO The cursor (x) value to be written is calculated as follows: Cx = desired display screen (x) position + H-P where P = 37 if 1:1 input multiplexing, 52 if 4:1 input multiplexing, 57 if 5:1 input multiplexing H =number of pixels between the fust rising edge of LO* following the falling edge of SYNC· to active video. Values from $0000 to $OFFF may be written into the cursor (x) register. The cursor (y) value to be written is calculated as follows: Cy = desired display screen (y) position + V-32 where v = number of scan lines from the second sync pulse during vertical blanking to active video. Values from $OFCO (-64) to $OFBF (+4031) may be loaded into the cursor (y) register. The negative values ($OFCO to $OFFF) are used in situations where V < 32, and the cursor must be moved off the top of the screen. 4 - 160 SECTION 4 Bt459 Internal Registers (continued) Window (x,y) Registers These registers are used to specify the (x,y) coordinate of the upper left comer of the cross hair cursor window. The window (x) register is made up of the window (x) low register (WXLR) and the window (x) high register (WXHR); the window (y) register is made up of the window (y) low register (WYLR) and the window (y) high register (WYHR). They are not initialized and may be written to or read by the MPU at any time. The window position is not updated until the vertical retrace interval after WYHR has been written to by the MPU. WXLR and WXHR are cascaded to form a 12-bit window (x) register. Similarly, WYLR and WYHR are cascaded to form a 12-bit window (y) register. Bits D4-07 of WXHR and WYHR are always a logical zero. Window (x) Low (WXLR) Window (x) High (WXHR) OataBit D3 D2 D1 DO 07 D6 05 D4 D3 D2 01 DO X Address X11 XI0 X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Window (y) Low (WYLR) Window (y) High (WYHR) OataBit D3 D2 D1 DO D7 D6 05 D4 D3 D2 D1 DO Y Address Y11 YlO Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Yl YO The window (x) value to be written is calculated as follows: Wx = desired display screen (x) position + H-P where P = 5 if 1:1 input mUltiplexing, 20 if 4:1 input mUltiplexing, 25 if 5:1 input multiplexing H =number of pixels between the first rising edge of LO· following the falling edge of HSYNC· to active video. The window (y) value to be written is calculated as follows: Wy = desired display screen (y) position + V where V = number of scan lines from the second sync pulse during vertical blanking to active video. Values from $0000 to $OFFF may be written to the window (x) and window (y) registers. A full-screen cross hair is implemented by loading the window (x,y) registers with $0000 and the window width and height registers with $OFFF. RAMDACs 4 • 161 Bt459 Internal Registers (continued) Window Width and Height Registers These registers are used to specify the width and height (in pixels) of the cross hair cursor window. The window width register is made up of the window width low register (WWLR) and the window width high register (WWHR); the window height register is made up of the window height low register (WHLR) and the window height high register (WHHR). They are not initialized and may be written to or read by the MPU at any time. The window width and height are not updated until the vertical retrace interval after WHHR has been written to by the MPU. WWLR and WWHR are cascaded to form a 12-bit window width register. Similarly, WHLR and WHHR are cascaded to form a 12-bit window height register. Bits D4-D7 of WWHR and WHHR are always a logical zero. Window Width Low (WWLR) Window Width High (WWHR) Data Bit D3 D2 D1 DO D1 D6 OS D4 D3 D2 D1 DO X Address XU XI0 X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Window Height Low (WHLR) Window Height High (WHHR) Data Bit D3 D2 Dl DO D1 D6 OS D4 D3 D2 Dl DO YAddress YU YI0 Y9 Y8 Y1 Y6 Y5 Y4 Y3 Y2 Yl YO The actual window width is 2, 8, or 10 pixels more than the value specified by the window width register, depending on whether 1:1, 4:1, or 5:1 input multiplexing is specified. The actual window height is 2 pixels more than the value specified by the window height register. Therefore, the minimum window width is 2,8, or 10 pixels, for 1:1,4:1, and 5: 1 mUltiplexing, respectively, and the minimum window height is two pixels. Values from $0000 to $OFFF may be written to the window width and height registers. 4 - 162 SECTION 4 Bnxktree Bt459 GP Internal Registers (continued) Cursor RAM This 64 x 64 x 2 RAM is used to define the pixel pattern within the 64 x 64 pixel cursor window, and is not initialized. For Revision A, the cursor RAM should not be written to by the MPU during the horizontal sync time and for the two LO* cycles after the end of the horizontal sync. The cursor RAM may otherwise be written to or read by the MPU at any time without contention. If writing to the cursor RAM asynchronously to horizontal sync, it is recommended that the user position the cursor off-screen in the Y direction (write to the cursor (y) registers and wait for the vertical sync interval to move the cursor off-screen), write to the cursor RAM, then reposition the cursor back to the original position. An alternative is to perform a write then read sequence, and if the correct cursor RAM data was not written, perform another write then read sequence. Since the contention occurs only during horizontal sync at the Y locations coincident with the cursor, the second write/read sequence bypasses the window of time when cursor RAM is in contention. For Revision B, cursor contention has been eliminated. The cursor RAM may be written to or read by the MPU at any time without contention. During MPU accesses to the cursor RAM, the address register is used to address the cursor RAM. Figure 12 illustrates the internal format of the cursor RAM, as it appears on the display screen. Addressing starts at location $400 as shown in Table 1. Note that in the X Windows mode, planel serves as a cursor display enable while planeO selects one of two cursor colors (if enabled). Note: in both modes of operation, planel = 07, 05, 03,01; planeO = 06, 04, 02, DO. UPPIlRLEFr CORNER AS DISPLAYBD ON SCREBN PIXIlLS I BYIl!$400 BYIl!$401 BYIl!S4CI' BYIl!S410 BYIl! $411 BYIl!$41P BYIl!$7FIl BYIl!S7Pl BYTI! $7PF Ii4 POOlLS 1 / ' 4 PIXELS ~ 107,061 os. 041 D3, Dzi 01, DO I Nonna1 Mode: ()() - color polelle or overlay RAM 01 = cwsor color I 10 = cursor color 2 II cunror color 3 & x·Windows Mode: ()() = color polelle or ove:lay RAM 01 = color polelle or ove:lay RAM 10 = cwsor color 2 11 = cursor color 3 Figure 12. Cursor RAM as Displayed on the Screen. RAMDACs 4 • 163 Bt459 Pin Descriptions Pin Name Description BlANK* Composite blank control input (lTL compatible). A logical zero drives the analog output to the blanking level, as illustrated in Tables 6 and 7. It is latched on the rising edge of LD*. When BLANK* is a logical zero, the pixel and overlay inputs are ignored. SYNC* Composite sync control inputs (lTL compatible). A logical zero typically switches off a 40 IRE current source on the lOG output (see Figures 9 and 10). SYNC* does not override any other control or data input, as shown in Tables 6 and 7; therefore, it should be asserted only during the blanking interval. SYNC* is latched on the rising edge of LD*. LD* Load control input (TTL compatible). The PO-P7 {A-E}, OLO-OL3 (A-E). OLE {A-E}, BLANK*, and SYNC* inputs are latched on the rising edge of LD*. LD*, while it is the output clock (1:1 multiplex mode) or is 1/4 or 115 of CLOCK, may be phase independent of the CLOCK and CLOCK* inputs. LD* may have any duty cycle, within the limits specified by the AC Characteristics section. PO-P7 {A-E} Pixel select inputs (TTL compatible). These inputs are used to specify, on a pixel basis, which location of the color palette RAM is to be used to provide color information (see Table 4). Either one, four, or five consecutive pixels (up to 8 bits per pixel) are input through this port. They are latched on the rising edge of LD*. Unused inputs should be connected to GND. Note that typically the {A} pixel is output first, followed by the {B} pixel, etc., until all one, four, or five pixels have been output, at which point the cycle repeats. OLD-OL3 {A-E} Overlay select inputs (TTL compatible). These inputs are latched on the rising edge of LD* and, in conjunction with CR05 in command registecO, specify which palette is to be used for color information, as illustrated in Table 4. When accessing the overlay palette RAM, the PO-P7 {A-E} inputs are ignored. Overlay information (up t04 bits per pixel) for either one, four, or five consecutive pixels are input through this port. Unused inputs should be connected to GND. OLE {A-E} Overlay enable inputs (TTL compatible). In the X Windows mode for overlays, a logical one indicates overlay information is to be displayed. A logical zero indicates to display PO-P7 information. In the normal mode for overlays, these inputs are ignored. They are latched on the rising edge of LD*. Unused inputs should be connected to GND. lOR, lOG, lOB Red, green, and blue current outputs. These high-impedance current sources are capable of directly driving a doubly terminated 75 n coaxial cable (Figure 13). All outputs, whether used or not, should have the same output load. PLL Phase lock loop output current. This high-impedance current source is used to enable mUltiple Bt459s to be synchronized with sub-pixel resolution when used with an external PLL. A logical one for SYNC* or BLANK* (as specified by CR23 in command register_2) results in no current being output onto this pin, while a logical zero results in the following current being output: PLL (rnA) = 3,227 * VREF (V) I RSET (n) If sub-pixel synchronization of multiple devices is not required, this output should be connected to GND (either directly or through a resistor up to 150 n). IZE* Interleave zoom enable input (TTL compatible). This input should be a logical zero for a minimum of 16 LD* cycles after the falling edge of BLANK* during scan lines that require an interleave shift. If zoom while interleaving is not supported, this pin may be connected directly toGND. VM Analog power. All VAA pins must be connected. GND Analog ground. All GND pins must be connected. 4 • 164 SECTION 4 Bt459 Pin Descriptions (continued) Pin Name Description CaMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 JlF ceramic capacitor must be connected between this pin and VAA (Figure 13). Connecting the capacitor to VAA rather than to GND provides the highest possible power supply noise rejection. The CaMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum and maximize the capacitor's self-resonant frequency to be greater than the LD* frequency. Refer to PC Layout Considerations for critical layout criteria. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal (Figure 13). Note that the IRE relationships in Figures 9 and 10 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on lOG is: RSET (n) = Kl * VREF (V) I lOG (rnA) The full-scale output current on lOR and lOB for a given RSET is: lOR, lOB (rnA) = K2 * VREF (V) I RSET (n) where Kl and K2 are defined as: 100 Setup IOR,IOB 7.5 IRE Kl = 11,294 K2 = 8,067 DIRE Kl = 10,684 K2 = 7,457 VREF Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 13, must supply this input with a 1.235 V (typical) reference. The use of a resistor network to generate the reference is not recommended, as any low-frequency power supply noise on VREF will be directly coupled onto the analog outputs. A 0.1 JlF ceramic capacitor is used to decouple this input to VAA, as shown in Figure 13. If VAA is excessively noisy, better performance may be obtained by decoupling VREF to GND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. CLOCK, CLOCK* Clock inputs. These differential clock inputs are designed to be driven by ECL logic configured for single supply (+5 V) operation. The clock rate is typicalIy the pixel clock rate of the system. CE* Chip enable control input (TTL compatible). This input must be a logical zero to enable data to be written to or read from the device. During write operations, data is internally latched on the rising edge of CE*. Care should be taken to avoid glitches on this edge-triggered input. RNI Read/write control input (TTL compatible). To write data to the device, both CE* and R/W must be a logical zero. To read data from the device, CE* must be a logical zero and R/W must be a logical one. R/W is latched on the falling edge of CE*. CO, Cl Command control inputs (TTL compatible). CO and Cl specify the type of read or write operation being performed, as illustrated in Table 1. They are latched on the falling edge of CE*. DO--D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. RAMDACs 4· 165 BnxKtree® Bt459 Pin Descriptions (continued)-132-pin PGA Package Signal BLANK* SYNC* Pin Number Signal Pin Number Signal Pin Number Ll OUlA OUlB OUlC OUlD OUlE El F2 Fl 03 02 (N) HI H2 OLlA OLlB OLlC OLlD OLlE OL2A OL2B OL2C OL2D OL2E M3 N2 PI P2 N3 OL3A OL3B OL3C OL3D OL3E M4 P3 N4 P4 MS K3 AS LD* CLOCK Kl CLOCK* IZE* BS POA POB POC POD POE K2 F3 D2 Dl E2 C7 012 M8 M7 1.2 (N) N7 L3 COMP M2 FSADJUST N9 MIO P9 PIA PIB PIC PlO PIE Al D3 C2 Bl Cl P2A P2B P2C P2D P2E A3 B3 A2 C3 B2 VREF A8 A7 B7 A6 B6 P4A P4B P4C P4D P4E C9 B9 lOB lOR A9 PIL OLFB OLF.C ()IllJ) OLEE 100 C8 B8 PSA PSB PSC PSD PSE Bll All CIO BIO AIO P6A P6B P6C P6D P6E Al4 A13 B12 Cll Al2 P7A P7B P7C P7D P7E E13 El2 Dl4 Dl3 Dl2 SECTION 4 CE* R/W Cl CO VM VM VM VM VM VM VM VM VM NS PS M6 N6 P6 PIO Pll NIO Nll 11 12 13 C6 F12 M9 P7 P8 N8 P13 NI2 P12 Mll D6 D7 L13 M14 L12 Ml3 Nl4 Pl4 N13 Ml2 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 014 013 Fl4 Fl3 El4 J13 J14 Hl2 Hl3 H14 CS A4 B4 C4 C14 Cl3 Bl4 Cl2 Bl3 L14 Kl2 112 Kl4 Kl3 DO Dl D2 D3 D4 DS P3A P3B P3C P3D P3E H3 Nl F3 OlEA 4 • 166 Ml GND GND GND GND GND GND Bt459 Pin Descriptions (continued)-132-pin PGA Package 14 D4 !l5 13 D6 Cli" 12 R/W C! Ol RL lOB AhJ lOR IXl VAA OOMP VREP GND VAA VAA GND GND VAA 0UlC 0UlD aJlI! 0L3I! 0lllA 0lllB <13A 0L3C IL'lD 11 10 PSH I'D PSC FS Bt459 1'3B P3C GND (TOP VIEW) PD 2 14 VAA POI! aID GND VAA SYNC' OLID CL?A 0L2I! OL'IB FID 0l.III OUE GND VAA CLK' OLIB OLIB 0L2B CI..2J) RIC CLOA 0UlC NIC GND VAA ax BLI{' WA OLIC ouc D E p G H K L M N p !'SB P1A PlB PD PlB _ P2C P2Il PIC RIB P1D PIE A B C !l5 D4 DI D6 D3 6 alignment marker (on top) P3B 13 DO 12 C! 11 lOB RL co PID PSA 10 IXl lOR FS ADI PSC I'D PSH _ NB I'$C 2 .. D1 VREP CDMP VAA VAA VAA GND VAA GND GND GND P3C 1'3B 0CEIl 0UlD 0UlC VM P3B PD 0lllB 0lllA 0L3I! 0L3D OL3C CL3A N/C N/C N/C 0L3B 0L2I! ------{ VAA 0 IN4l48/9 DAC OlITPllT TO MONITOR IN4l48/9 GND Location Description CI--C5, CI0, C11 C6--C9 C12 Ll Rl, R2, R3 R4 0.1 jlF ceramic capacitor 0.01 IJ.F ceramic chip capacitor 33 IJ.F tantalwn capacitor ferrite bead 75 Q 1% metal film resistor 1000 Q 1% metal film resistor 523 Q 1% metal film resistor 1.2 V voltage reference RSEr ZI Vendor Part Nwnber Erie RPE110ZSUI04M50V AVX 12102T103QAI018 Mallory CSR13F336KM Fair-Rite 2743001111 Dale CMF-55C Dale CMF-55C Dale CMF-55C National Semiconductor LM385Z-1.2 Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the Bt459. Figure 13. 4 - 172 SECTION 4 Substitution of devices with similar Typical Connection Diagram and Parts List. BnxktreeQP Bt459 Application Information Clock Interfacing Due to the high clock rates at which the Bt459 may operate, it is designed to accept differential cloc~ signals (CLOCK and CLOCK*). These clock inputs are designed to be generated by ECL logic operating at +5 V. Note that the CLOCK and CLOCK* inputs require termination resistors (typically a 220 n resistor to VCC and a 330 n resistor to GND). The termination resistors should be as close as possible to the Bt459. The CLOCK and CLOCK* inputs must be differential signals and greater than 0.6 V peak-to-peak due to the noise margins of the CMOS process. The Bt459 will not function using a single-ended clock with CLOCK* connected to ground. Typically, LD* is generated by dividing CLOCK by four or five (depending on whether 4:1 or 5:1 multiplexing was specified) and translating it to TTL levels. As LD* may be phase shifted relative to CLOCK, the designer need not worry about propagation delays in deriving the LD* signal. LD* may be used as the shift clock for the video DRAMs and to generate the fundamental video timing of the system (SYNC·, BLANK·, etc.). For display applications where a single Bt459 is being used, it is recommended that the Bt438 Clock Generator Chip be used to generate the clock and load signals. It supports the 4:1 and 5: 1 input multiplexing of the Bt459, and will also optionally i set the pipeline delay of the B t459 to eight clock cycles. The Bt438 may also be used to interface the Bt459 to a TTL clock. Figure 14 illustrates using the Bt438 with the Bt459. When using a single Bt459, the PLL output is ignored and should be connected to GND (either directly or through a resistor up to 150 n). Using Multiple Bt459s For display applications where up to four Bt459s are being used, it is recommended that the Bt439 Clock Generator Chip be used 10 generate the clock and load It supports the 4: I and 5: 1 input signals. mUltiplexing of the Bt459, synchronizes them to sub-pixel resolution and sets the pipeline delay of the Bt459 to eight clock cycles. The Bt439 may also be used to interface the Bt459 to a TTL clock. Figure 15 illustrates using the Bt439 with the Bt459. Sub-pixel synchronization is supported via the PLL output. Essentially, PLL provides a signal to indicate the amount of analog output delay of the Bt459, relative to CLOCK. The Bt439 compares the phase of the PLL signals generated by up to four Bt459s, and adjusts the delay of each of the CLOCK and CLOCK· signals 10 the Bt459s to minimize the PLL delay difference. There should be minimal layout skew in the CLOCK and PLL trace paths to assure proper clock alignment. +'v 220..; I. CLOCK 330~ MOIIlTOR PROOUCfS 2201 !JIll! r Bt4S9 oe; CLOCK· CLOCK· 330~ Bt438 CLOCK IDA LD· VAA VREP Figure 14. o.lT VREP Generating the Bt459 Clock Signals. RAMDACs 4 • 173 .. BnxKtree~ Bt459 Application Information (continued) If sub-pixel synchronization of multiple Bt459s is not necessary, the Bt438 Clock Generator Chip may be used instead of the Bt439. In this instance, the CLOCK, CLOCK*, and LD* inputs of up to four Bt459s are connected together and driven by a single Bt438 (daisy chain with single balanced termination for <100 MHz or through a 10H116 buffer for >100 MHz). The VREF inputs of the Bt459s must still have a 0.1 I1F bypass capacitor to VAA, and have individual voltage references. The designer must take care to minimize skew on the CLOCK and CLOCK· lines. The PLL outputs of the Bt459s would not be used and should be connected to GND (either directly or through a resistor up to 150 0). When using multiple Bt459s, each Bt459 should have its own power plane ferrite bead and voltage reference. Each Bt459 must still have its own individual RSET resistor, analog output termination resistors, power supply bypass capacitors, CaMP capacitor, and VREF capacitor. PIJ.. +sv C1.OCK ,. C1.OCK- MONITOR PRODUCI'S !I7(E Bt439 Bt4S9 #1 lK +SV @ Bt459 #2 PROM BT459 ~T VAA so lK VREP LM38SZ·1.l PIJ.. 8T8'I C1.OCK m C1.OCK- LDVAA Bt4S9 #3 lK VRBF Figure 15. 4 - 174 Generating the Clock Signals for Multiple Bt459s. SECTION 4 Bt459 Application Information (continued) Setting the Pipeline Delay The pipeline delay of the Bt459, although fixed after a power-up condition, may be anywhere from six to ten clock cycles. The Bt459 contains additional circuitry enabling the pipeline delay to be fixed at eight clock cycles. The Bt438 and Bt439 Clock Generator Chips support this mode of operation when used with the Bt459. To reset the Bt459, it should be powered up, with LD*, CLOCK, and CLOCK* running. Stop the CLOCK and CLOCK* signals with CLOCK high and CLOCK* low for at least three rising edges of LD*. There is no upper limit on how long the device can be held with CLOCK and CLOCK* stopped. Restart CLOCK and CLOCK'" so that the first edge of the signals is as close as possible to the rising edge of LD* (the falling edge of CLOCK leads the rising edge of LD* by no more than I clock cycle or follows the rising edge of LD* by no more than 1.5 clock cycles). When restarting the clocks, care must be taken to ensure that the minimum clock pulse width is not violated. In order to assure the Bt459 has the proper configuration, all the command registers must be initialized prior to a fixed pipeline reset. Because of this requirement, the power-up which occurs prior to initialization of the command registers cannot be used to assume the fixed pipeline. An additional reset is required after command register writes. The resetting of the B t459 to an eight clock cycle pipeline delay does not reset the blink counter circuitry. Therefore, if the multiple Bt459s are used in parallel, the on-chip blink counters may not be synchronized. In this instance, the blink mask register should be $00 and the overlay blink enable bits a logical zero. Blinking may be done under software control via the read mask register and overlay display enable bits. Resetting the Bt459 to an eight clock cycle pipeline delay is required for proper cursor pixel alignment. Interleave Operation To support interleaved frame buffers, the Bt459 may be configured for various interleave factors, as shown in Table 8. Table 9 shows an example of interleave operation for 4: I multiplexing, an interleave select of 3, and starting with pixel {AJ. Table 10 shows the same operation with pixel {B J selected as the starting pixel (the display has been panned down 3 scan lines). Scan line number 0 corresponds to the top of the display screen and is the first displayed scan line after a vertical blanking interval. The output sequence is shown starting at the left-most displayed pixel. Scan Line Output Sequence Scan Line Output Sequence 0 1 2 3 4 5 6 7 ABCDABCD ... DABCDABC ... CDABCDAB ... BCDABCDA ... ABCDABCDoo, DABCDABC ... CDABCDAB ... BCDABCDA... : 0 BCDABCDA... ABCDABCD ... DABCDABC ... CDABCDAB ... BCDABCDA ... ABCDABCD ... DABCDABC... CDABCDAB ... : : Table 9. Interleave Example. I 2 3 4 5 6 7 : Table 10. Interleave Example. RAMDACs 4 • 175 .. Bt459 Application Information (continued) ESD and Latchup Considerations Correct ESO-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid OAC power decoupling networks with large time constants, which could delay V AA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. Test Features 0/ the Bt459 The Bt459 contains two dedicated test registers and an analog output comparator that assist the user in evaluating the performance and functionality of the part. This section is intended to explain the operating usage of these test features. Signature Register (Signature Mode) The signature register, in the active mode, operates with the 24 bits of data that are output from the color palette RAM. These 24-bit vectors represent a single pixel-color, and are presented as inputs simultaneously to the red, green, and blue signature analysis registers (SARs), as well as the three on-chip OACs. The SARs act as a 24-bit wide Linear Feedback Shift Register on each succeeding pixel that is latched. It is important to note that in either the 4: 1 or 5: 1 multiplexed modes the SARs only latch one pixel per "load group." Thus the SARs are operating on only every fourth or fifth pixel in the multiplexed modes. The user determines which pixel phase (A, B, C, 0, or E) is latched for generating new signatures by setting bits 00-02 in the Test Register. In 1:1 mux mode, the SARs will generate signatures truly on each succeeding pixel in the input stream. In this case, the user should always select pixel "A" (Test Register DO, 01, and 02 = (00) when in the 1:1 mode, since the "A" pixel pins are the only active pixel inputs. 4· 176 SECTION 4 The Bt459 will only generate signatures while in "active-display" (BLANK· negated). The SARs are available for reading and writing via the MPU port when the Bt459 is in a blanking state (BLANK* asserted). Specifically, it is safe to access the SARs after the OAC outputs are in the blanking state (up to 15 pixel clock periods after BLANK* is asserted). Typically, the user will write a specific 24-bit "seed" value into the SARs. Then, a known pixel stream will be input to the chip, say one scan-line or one frame buffer worth of pixels. Then, at the succeeding blank state, the resultant 24-bit signature can be read out by the MPU. The 24-bit signature register data is a result of the same captured data that is fed to the OACs. Thus, overlay and cursor data validity is also tested using the signature registers. Assuming the chip is running 4:1 or 5:1 mux modes, the above process would be repeated with all different pixel phases-A, B, C, etc.-being selected. It is not simple to speicfy the algorithm which descirbes the linear feedback shift operation used in the Bt459. The linear feedback configuration is shown in Figure 16. Note that each register internally uses XORs at each input bit (On) with the output (result) by one least significant bit (Qn-l). Experienced users have developed tables of specific seeds and pixel streams and recorded the signatures that result from those inputs applied to "known-good" parts. Note that a good signature from one given pixel stream can by used as the seed for the succeeding stream to be tested. Any signature is deterministically created from a starting seed and the succeeding pixel stream fed to the SARs. Signature Register (Data Strobe Mode) Setting command bit CR20 to "1" puts the SARs into data strobe mode. In this instance, the linear feedback circuits of the SARs are disabled, which stops the SARs from generating signatures. Instead, the SARs simply capture and hold the respective pixel phase that is selected. Any MPU data written to the SARs is ignored. One use, however. is to directly check each pixel color value that is strobed into the SARs. To read out a captured color in the middle of a pixel stream, the user should first freeze all inputs to the Bt459. The levels of most inputs do not matter EXCEPT that CLOCK should be high, and CLOCK* should be low. Then, the user may read out the pixel color by doing three successive MPU reads from the red, green, and blue SARs. respectively. Bt459 Application Information (continued) In general, the color read out will correspond to a pixel latched on the previous load. However, due to the pipelined data path, the color may come from an earlier load cycle. To read successive pixels, toggle LD*, pulse the CLOCK pins according to the mux state (I, 4, or 5 periods), then hold all pixel-related inputs and perform the three MPU reads as described. This overall process is best done on a sophisticated VLSI semiconductor Tester. Analog Comparator The other dedicated test structure in the Bt459 is the analog output comparator. It allows the user to measure the DACs against each other, as well as against a specific reference voltage. Four combinations of tests are selected via the Test Register. With a given setting, the respective signals (DAC outputs or the 145 mV reference) will be continuously input to the comparator. The result of the comparator is latched into the Test Register on each of the 64 scan lines of the 64 x 64 user-defined cursor block (the 64 x 64 cursor must be enabled for display). On each of these 64 scan lines, the capture occurs over one LD* period that corresponds to the cursor (x) position, set by the 12-bit cursor (x) register. To obtain a meaningful comparison, the cursor should be located on the visible screen. There is no significance to the cursor pattern data in the cursor RAM. For a visual reference, the capture point actually occurs over the left-most edge of the 64 x 64 cursor block. Due to the simple design of the comparator, it is recommended that the DAC outputs be stable for 5 I1S before capture. At a display rate of 100 MHz, 5 ~s corresponds to 500 pixels. In this case, the cursor (x) position should be set to well over 500 pixels to ensure an adequate supply of pixels. Furthermore, either the color palette RAM or the pixel inputs (or both) should be configured to guarantee a single continuous output from the DACs under test, up until capture. Typically, users will create screen-wide test bands of various colors. Various comparison cases are set up by moving the cursor up and down (by changing the 12-bit cursor (y) register) over these bands. For each test, the result is obtained by reading Test Register bit D3. RD·R7 00·07 BO·B7 FROMLOOKIJPTABLE FROMLOOKIJPTABLE FROM LOOK\JPTABLE a • MPU SARREAD BIT Figure 16. Signature Analysis Register Circuit. RAMDACs 4· 177 .. Bt459 Application Information (continued) Initializing the Bt459 Load Cursor RAM Pattern Following a power-on sequence, the Bt459 must be initialized. This sequence will configure the Bt459 as follows: 4:1 multiplexed operation no overlays, no blinking, no interleave 64 x 64 block cursor, no cross hair cursor 8 bits per pixel, no panning, no zoom sync enabled on lOG, 7.5 IRE blanking pedestal Control Register Initialization Cl, CO Write $01 to address register low Write $02 to address register high Write $40 to command register_O Write $00 to command register_l Write $CO to command registec2 Write $FF to pixel read mask register Write $00 to reserved location Write $00 to pixel blink mask register Write $00 to reserved location Write $00 to overlay read mask register Write $00 to overlay blink mask register Write $00 to interleave register Write $00 to test register 00 01 10 10 10 10 10 10 10 10 10 10 10 Write $00 to address register low Write $03 to address register high Write $CO to cursor command register Write $00 to cursor (x) low register Write $00 to cursor (x) high register Write $00 to cursor (y) low register Write $00 to cursor (y) high register Write $00 to window (x) low register Write $00 to window (x) high register Write $00 to window (y) low register Write $00 to window (y) high register Write $00 to window width low register Write $00 to window width high register Write $00 to window height low register Write $00 to window height high register 00 01 10 10 10 10 10 10 10 10 10 10 10 10 10 4· 178 SECTION 4 Write $00 to address register low Write $04 to address register high Write $FF to cursor RAM (location $000) Write $FF to cursor RAM (location $001) 00 01 10 10 Write $FF to cursor RAM (location $3FF) 10 Color Palette RAM Initialization Write $00 to address register low Write $00 to address register high Write red data to RAM (location $00) Write green data to RAM (location $00) Write blue data to RAM (location $00) Write red data to RAM (location $01) Write green data to RAM (location $01) Write blue data to RAM (location $01) 00 01 11 11 11 11 11 11 Write red data to RAM (location $FF) Write green data to RAM (location $FF) Write blue data to RAM (location $FF) 11 11 11 Overlay Color Palette Initialization Write $00 to address register low Write $01 to address register high Write red data to overlay (location $0) Write green data to overlay (location $0) Write blue data to overlay (location $0) Write red data to overlay (location $1) Write green data to overlay (location $1) Write blue data to overlay (location $1) 00 01 10 10 10 10 10 10 Write red data to overlay (location $F) Write green data to overlay (location $F) Write blue data to overlay (location $F) 10 10 10 Cursor Color Palette Initialization Write $81 to address register low Write $01 to address register high Write red data to cursor (location $0) Write green data to cursor (location $0) Write blue data to cursor (location SO) Write red data to cursor (location $1) Write green data to cursor (location $1) Write blue data to cursor (location $1) Write red data to cursor (location $2) Write green data to cursor (location $2) Write blue data to cursor (location $2) 00 01 10 10 10 10 10 10 10 10 10 Bt459 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage FS ADJUST Resistor Symbol Min Typ Max Units VAA TA RL 4.75 0 5.00 5.25 +70 Volts ·C VREF RSET 1.20 1.26 Volts 37.5 1.235 523 n n Absolute Maximum Ratings Parameter Symbol Typ Max Units 6.5 Volts VAA+0.5 Volts +125 +150 ·C ·C TJ +150 +175 ·C ·C ·C TSOL 260 TVSOL 220 Min VAA (measured to GND) Voltage on Any Signal Pin* Analog Output Short Circuit Duration to any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature PQFP PGA Soldering Temperature (5 seconds, 1/4" from pin) GND-O.5 indefinite ISC TA TS TJ TJ -55 -65 ·C Vapor Phase Soldering (1 minute) Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. RAMDACs 4 • 179 .. Bt459 DC Characteristics Parameter Analog Outputs Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs (except CLOCK, CLOCK·) Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Yin = 2.4 V) Clock Inputs (CLOCK, CLOCK·) Differential Input Voltage Input High Current (Vin = 4.0 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Yin = 4.0 V) Digital Outputs (DO-D7) Output High Voltage (lOH = -400 ).LA) Output Low Voltage (lOL =3.2 rnA) 3-state Current Output Capacitance See test conditions on next page. 4 • 180 SECTION 4 Min Typ Max Units 8 8 8 Bits 1L ±l IL ±1 ±S LSB LSB % Gray Scale Symbol guaranteed Binary VIH V1L 2.0 GND-O.S IIH IlL CIN L1VIN 4 .6 IKIH IK1L CKIN VOO 4 Volts Volts 6 Volts 1 -1 10 IlA IlA IlA IlA pF pF Volts 2.4 VOL ICYZ CDOUT VAA+O.S 0.8 1 -1 10 10 0.4 Volts 10 IlA pF Bt459 DC Characteristics (continued) Parameter Analog Outputs Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank SETUP = 7.5 IRE SEfUP=OIRE Blank Level on lOG Blank Level on IOR, lOB Sync Level on lOG LSB Size DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 rnA) Symbol VOC RAOUT CAOUT PLL Analog Output Output Current SYNC*/BLANK* = 0 SYNC*/BLANK* = 1 Output Compliance Output Impedance Output Capacitance (f= 1 MHz, PLL = ornA) PJ.L Voltage Reference Input Current Rev. A Rev. B IREF Power Supply Rejection Ratio (COMP = 0.1 )J.F, f = 1 KHz) PSRR Min Typ Max Units 17.69 16.74 19.05 17.62 20.40 18.50 rnA rnA 0.95 0 6.29 0 0 1.44 5 7.62 5 5 69.1 2 1.90 50 8.96 50 50 rnA 5 +1.2 % Volts kn pF -0.5 50 13 6.00 0 -1.0 7.62 5 50 8 20 9.00 50 +2.5 15 ~ rnA J.lA ~ ~ rnA ~ Volts kn pF 500 10 ~ ~ 0.5 %/%tNAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 n, VREF = 1.235 V. SETUP = 7.5 IRE. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. RAMDACs 4 - 181 .. Bt459 AC Characteristics Parameter Clock Rate ill* Rate 1:1 multiplexing 4:1 multiplexing 5:1 mUltiplexing Symbol Fmax Mintryp/ Max 135 MHz 110 MHz MHz 80 Units max 135 110 80 MHz max max max 50 33.75 27 50 27.5 22 50 20 16 MHz MHz MHz LDmax RIW, CO, Cl Setup Time RIW, CO, Cl Hold Time 1 2 min min 0 10 0 10 0 10 ns ns CE*LowTime CE* High Time CE* Asserted to Data Bus Driven CE* Asserted to Data Valid CE* Negated to Data Bus 3-Stated 3 4 5 6 7 min min min max max 40 20 5 40 12 40 20 5 40 12 40 20 5 40 12 ns ns ns ns ns Write Data Setup Time Write Data Hold Time 8 9 min min 15 2 15 2 15 2 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 10 11 min min 3 2 3 2 3 2 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time 12 13 14 min min min 7.4 3.2 3.2 9.09 4 4 12.5 5 5 ns ns ns LD* Cycle Time 1:1 multiplexing 4: 1 multiplexing 5:1 mUltiplexing LD* Pulse Width High Time 1:1 multiplexing 4:1 or 5:1 multiplexing LD* Pulse Width Low Time 1:1 multiplexing 4:1 or 5:1 multiplexing 15 min min min 15.15 29.63 37.04 20 36.36 45.45 20 50 62.5 ns ns ns min min 6 12 7 15 7 20 ns ns min min 6 12 7 15 7 20 ns ns See test conditions on next page. 4 • 182 SECTION 4 16 17 Bt459 AC Characteristics (continued) Parameter Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time Clock and Data Feedthrough* Glitch Impulse* DAC to DAC Crosstalk Analog Output Skew Symbol Minffyp/ Max 135 MHz 110 MHz 80 MHz Units 18 19 20 typ typ max typ typ typ typ max 12 1.5 8 tbd 50 tbd 0 2 12 1.5 8 tbd 50 tbd 0 2 12 2 12 tbd 50 tbd 0 2 ns ns ns dB pV - sec dB ns ns min max 6 10 6 10 6 10 Clocks Clocks typ max 240 360 220 335 200 300 rnA rnA Pipeline Delay VAA Supply Current** IAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 n, VREF = 1.235 V. TTL input values are 0-3 V, with input rise/fall times :5: 4 ns, measured between the 10% and 90% points. ECL input values are V AA-0.8 to VAA-1.8 volts, with input rise/fall times :5: 2 ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. Analog output load :5: 10 pF, DO-D7 output load :5: 75 pF. See timing notes in Figure 18. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the TTL digital inputs have a 1 ill resistor to GND and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 2x clock rate. ** At Fmax. IAA (typ) at VAA = 5.0 V, TA = 20° C. IAA (max) at VAA = 5.25 V, TA = 0° C. RAMDACs 4 - 183 .. Bt459 Timing Waveforms I RIW, co, P I \ VALID CI 3 ~I \ CE' 4 6 s I V "- DO - D1 (READ) DATAOIIT(RIW=I) ;( DO - D1 (WRITE) DATA IN (RIW= 0) ~ /1\ 8 ~ Figure 17. MPU Read/Write Timing Dimensions. IS 16 17 LD' PO-PI {A-EJ, OLE {A-E}, OLO-OI.3 {A-E}, SYNC', BLANK' DATA 10 11 18 20 lOR, lOG, lOB, I'LL 19 12 CLOCK 14 Note 1: Output delay time measured from 50% point of the rising clock edge scale transition. Note 2: Output settling time measured from 50% point of full-scale transition to output settling within ±l LSB. Note 3: Output rise/fall time measured between 10% and 90% points of full-scale transition. Figure 18. 4 - 184 SECTION 4 Video 1nputlOutput Timing. to 50% point of full- Br----x~ ____ MPU Read/Write Timing. RAMDACs 4 - 189 .. Bt460 Circuit Description (continued) Frame Buffer Interface To enable pixel data to be transferred from the frame buffer at TTL data rates, the Bt460 incorporates internal latches and multiplexers. As illustrated in Figure 2, on the rising edge of LD*, sync and blank information, color, and overlay information, for either one, four, or five consecutive pixels, are latched into the device. Note that with this configuration, the sync and blank timing will be recognized only with one, four, or five pixel resolution. TypicalIy, the LD* signal is used to clock external circuitry to generate the basic video timing and to clock the video DRAMs. For 4:1 or 5:1 input multiplexing, the Bt460 outputs color information each clock cycle based on the {A I inputs, folIowed by the {B I inputs, etc., until all four or five pixels have been output, at which point the cycle repeats. In the 1: 1 input multiplexing mode, the {B I, (C), {DJ, and {EI inputs are ignored. The overlay inputs may have pixel timing, facilitating the use of additional bit planes in the frame buffer to control overlay selection on a pixel basis, or they may be controlIed by external circuitry. To simplify the frame buffer interface timing, LD* may be phase shifted, in any amount, relative to CLOCK. This enables the LD* signal to be derived by externally dividing CLOCK by four or five, independent of the propagation delays of the LD* generation logic. As a result, the pixel and overlay data are latched on the rising edge of LD*, independent of the clock phase. Internal logic maintains an internal LOAD signal, synchronous to CLOCK, and is guaranteed to follow the LD* signal by at least one, but not more than three, clock cycles. This LOAD signal transfers the latched pixel and overlay data into a second set of latches, which are then internally multiplexed at the pixel clock rate. If 4: 1 multiplexing is specified, only one rising edge of LD* should occur every four clock cycles. If 5: 1 multiplexing is specified, only one rising edge of LD* should occur every five clock cycles. Otherwise, the internal LOAD generation circuitry assumes it is not locked onto the LD* signal, and will continuously attempt to resynchronize itself to LD*. LD' po.P8 (A·E). OLE (A· E). OLO-OL3{A-E}. SYNC·. BLANK. lOR. lOG. lOB. P!L CLOCK Figure 2. 4 - 190 SECTION 4 Video Input/Output Timing. Bt460 Circuit Description (continued) color information. Note that PO is the LSB when addressing the color palette RAMs, and OLO is the LSB when addressing the overlay palette RAM. Table 4 illustrates the truth table used for color selection. If 1: 1 multiplexing is specified, LD* is also used for clocking the Bt460 (at a maximum of 50 MHz). The rising edge of LD* still latches the PO-P8 (A), OLO-OL3 (A), OLE (A), SYNC*, and BLANK* inputs. However, analog information is output following the rising edge of LD* rather than CLOCK. Note that CLOCK must still run, but is ignored. Pixel Panning To support pixel panning, command registec1 specifies by how many clock cycles to pan. Only the pixel inputs and underlays are panned~verlays are not. Panning is done by delaying SYNC· and BLANK·, an additional I, 2, 3, or 4 clock cycles. Pixel Addressing 0/ Color Palette RAM Typically, the P8 pixel input port is used to select the lower (P8 = 0) or upper (P8 = 1) 256 entries in the color palette RAM. If 0 pixel panning is specified, pixel (A) is output flTst, followed by pixel (B), etc., until all four or five pixels have been output, at which point the cycle repeats (note that this assumes the interleave select is pixel (Al). Alternately, the Bt460 can also use the cross hair cursor window to select the lower (outside the cursor window) or upper (inside the cursor window) 256 entries in the color palette RAM. In this case, the P8 pixel inputs are logically ORed with the lower/upper selection by the cursor window. Use of the P8 pixel inputs for palette selection can be disabled by the pixel read mask register (high). If 1 pixel panning is specified, pixel .ff1 1.000 1M 0.054 9.os 0.340 -r------;r----~-----------~A~uwa 7.62 0.286 7.S IRE + __________ 0.00 0.000 0.00 0.000 -r---,.or--------------::~--- WHITB UlVEL --IL.-....,....-...._~ ______________ BLANK LEva 40 IRE ~ ______________ ~~ ___________________ SYNCUWa Note: 75 Q doubly tenninated load, RSET = 523 Q, VREF = 1.235 V. Blank pedestal = 7.5 IRE. RS-343A levels and tolerances assumed on all levels. Figure 9. Composite Video Output Waveform (SETUP = 7.5 IRE). Description Sync Iout(mA) No Sync lout (mA) SYNC'" BLANK'" DAC Input Data WHIlE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 19.05 data + 1.44 data + 1.44 1.44 1.44 0 0 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: Typical with RSET = 523 Q, VREF = 1.235 V. Blank pedestal = 7.5 IRE. Table 6. 4·200 Video Output Truth Table (SETUP = 7.5 IRE). SECTION 4 Bt460 Circuit Description (continued) SYNC DISABLi!D SYNC I!NABLi!D MA V V 18.1iO Cl.6!I8 '1f[,E/ 1.000 -.---.......- - - - - - - - - - - = - - - - WHm! LBVEL 0.00 0.000 8.05 0.301 -r-----~~._T_~--------~A~~~VEL 0.00 0.000 MA 43lRB ~ ______ Note: 75 n doubly terminated load, RSET = 495 tolerances assumed on all levels. Figure 10. ~~~ _________ n. VREF = 1.235 V. SYNC~~ Blank pedestal = 0 IRE. RS-343A levels and Composite Video Output Waveform (SETUP = 0 IRE). Description Sync Iout(mA) No Sync Iout(mA) SYNC* BlANK* DAC Input Data WHITE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC 26.67 data of- 8.05 data 8.05 18.60 data data 0 1 1 0 1 0 0 8.05 0 0 0 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: Typical with RSET = 495 Table 7. n. VREF = 1.235 V. Blank pedestal = 0 IRE. Video Output Truth Table (SETUP 0 IRE). RAMDACs 4 • 201 Bt460 Internal Registers Command register_O This register may be written to or read by the MPU at any time and is not initialized. CROO corresponds to data bus bit DO. CR07, CR06 Multiplex select (00) (01) (10) (11) reserved 4:1 multiplexing 1:1 multiplexing 5:1 multiplexing These bits specify whether 1:1, 4:1, or 5:1 multiplexing is to be used for the pixel and overlay inputs. If 4:1 is specified, the {E} pixel and overlay inputs are ignored and should be connected to GND, and the LD* input should be 1/4 the CLOCK rate. If 5:1 is specified, all of the pixel and overlay inputs are used, and the LD* input should be 1/5 the CLOCK rate. If 1: 1 is specified, the {B}, (C), {O}, and {E} inputs are ignored. Note that in the 1:1 multiplex mode, the maximum clock rate is 66 MHz. LO* is used for the pixel clock. Although CLOCK is ignored in the 1:1 mode, it must remain running. Note that it is possible to reset the pipeline delay of the Bt460 to a fixed eight clock cycles. In this instance, each time the input multiplexing is changed, the Bt460 must again be reset to a fixed pipeline delay. CR05 Overlay 0 enable (0) use color palette RAM (1) use overlay color 0 CR04 reserved (logical zero) CR03, CR02 Blink rate selection (00) (01) (10) (11) CR01, CROO on, 48 off (25{75) on, 16 off (SO/50) 8 4 2 1 These 2 bits specify the blink rate cycle time and duty cycle, and are specified as the number of vertical retrace intervals. The numbers in parentheses specify the duty cycle (% on/oro. on, 32 off (SO/50) on, 64 off (SO/50) Block mode (00) (01) (10) (11) 4 - 202 16 16 32 64 When in the normal overlay mode, this bit specifies whether to use the color palette RAM or overlay color 0 to provide color information when the overlay inputs are SO. See Table 4. bits per pixel bits per pixel bits per pixel bit per pixel SECTION 4 These bits specify whether the PO-P7 pixel data is input as 1, 2, 4, or 8 bits per pixel. Note that only the PO-P7 inputs are affected. Br blue red> 150mV green> blue green> 150 mY blue> red red < 150mV blue> green green < 150 mV The above table lists the valid comparison combinations. A logical one enables that function to be compared; the result is D3. The comparison result is strobed into D3 on the left edge of the 64 x 64 cursor area. The output levels of the DACs should be constant for 5 !J.S before the left edge of the cursor. For normal operation, D3-D7 must be a logical zero. RAMDACs 4 - 211 .. Bt460 Internal Registers (continued) Cursor Command Register This command register is used to control various cursor functions of the Bt460. It is not initialized, and may be written to or read by the MPU at any time. CR40 corresponds to data bus bit DO. CR47 64 x 64 cursor plane 1 display enable Specifies whether plane I of the 64 x 64 cursor is to be displayed (logical one) or not (logical zero). (0) disable planel (I) enable plane 1 CR46 64 x 64 cursor planeO display enable Specifies whether planeO of the 64 x 64 cursor is to be displayed (logical one) or not (logical zero). (0) disable planeO (I) enable planeO CR45 Cross hair cursor plane 1 display enable Specifies whether planel of the cross hair cursor is to be displayed (logical one) or not (logical zero). (0) disable planel (I) enable planel CR44 Cross hair cursor planeO display enable (0) disable planeO (I) enable planeO CR43 Cursor format (0) XOR (1) OR CR42, CR41 Cross hair thickness (00) (01) (10) (11) CR40 1 3 5 7 pixel pixels pixels pixels Cursor blink enable (0) blinking disabled (I) blinking enabled 4·212 SECTION 4 Specifies whether planeO of the cross hair cursor is to be displayed (logical one) or not (logical zero). Note that planeO and planel contain the same information. If both the 64 x 64 cursor and the cross hair cursor are enabled for display, this bit specifies whether the contents of the cursor RAM are to be logically exclusive-ORed (logical zero) or ORed (logical one) with the cross hair cursor. This bit specifies whether the vertical and horizontal thickness of the cross hair is one, three, five, or seven pixels. The segments are centered about the value in the cursor (x,y) register. This bit specifies whether the cursor is to blink (logical one) or not (logical zero). If both cursors are displayed, both will blink. The blink rate and duty cycle are as specified by command registecO. Bt460 Internal Registers (continued) Cursor (x,y) Registers These registers are used to specify the (x,y) coordinate of the center of the 64 x 64 pixel cursor window, or the intersection of the cross hair cursor. The cursor (x) register is made up of the cursor (x) low register (CXLR) and the cursor (x) high register (CXHR); the cursor (y) register is made up of the cursor (y) low register (CYLR) and the cursor (y) high register (CYHR). They are not initialized and may be written to or read by the MPU at any time. The cursor position is not updated until the vertical retrace interval after CYHR has been written to by the MPU. CXLR and CXHR are cascaded to form a 12-bit cursor (x) register. Similarly, CYLR and CYHR are cascaded to form a 12-bit cursor (y) register. Bits D4--07 of CXHR and CYHR are always a logical zero. Cursor (x) High Cursor (x) Low (CXLR) (CXHR) OataBit D3 D2 01 DO D7 D6 05 D4 D3 02 D1 DO X Address Xli XIO X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Cursor (y) High (CYHR) Cursor (y) Low (CYLR) OataBit D3 D2 D1 DO D7 D6 OS D4 D3 02 D1 DO Y Address Yll YI0 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Yl YO The cursor (x) value to be written is calculated as follows: Cx = desired display screen (x) position + H-P where P = 37 if 1:1 input multiplexing, 52 if 4:1 input multiplexing, 57 if 5:1 input mUltiplexing H = number of pixels between the first rising edge of LO* following the falling edge of SYNC'" to active video. Values from $0000 to $OFFF may be written into the cursor (x) register. The cursor (y) value to be written is calculated as follows: Cy = desired display screen (y) position + V-32 where v = number of scan lines from the second sync pulse during vertical blanking to active video. Values from $OFCO (-64) to $OFBF (+4031) may be loaded into the cursor (y) register. The negative values ($OFCO to $OFFF) are used in situations where V < 32, and the cursor must be moved off the top of the screen. RAMDACs 4 • 213 .. Bt460 Internal Registers (continued) Window (x,y) Registers These registers are used to specify the (x,y) coordinate of the upper left comer of the cross hair cursor window. The window (x) register is made up of the window (x) low register (WXLR) and the window (x) high register (WXHR); the window (y) register is made up of the window (y) low register (WYLR) and the window (y) high register (WYHR). They are not initialized and may be written to or read by the MPU at any time. The window position is not updated until the vertical retrace interval after WYHR has been written to by the MPU. WXLR and WXHR are cascaded to form a 12-bit window (x) register. Similarly, WYLR and WYHR are cascaded to form a 12-bit window (y) register. Bits D4-D7 of WXHR and WYHR are always a logical zero. Window (x) High (WXHR) Window (x) Low (WXLR) Data Bit D3 D2 D1 DO D7 D6 D5 D4 D3 D2 D1 DO X Address XlI X10 X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Window (y) Low (WYLR) Window (y) High (WYHR) Data Bit D3 D2 D1 DO D7 D6 D5 D4 D3 D2 D1 DO Y Address YlI Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO The window (x) value to be written is calculated as follows: Wx = desired display screen (x) position + H-P where P = 5 if 1:1 input multiplexing, 20 if 4:1 input multiplexing, 25 if 5:1 input multiplexing H =number of pixels between the flTst rising edge of LD* following the falling edge of HSYNC* to active video. The window (y) value to be written is calculated as follows: Wy = desired display screen (y) position + V where V =number of scan lines from the second sync pulse during vertical blanking to active video. Values from $0000 to $OFFF may be written to the window (x) and window (y) registers. A full screen cross hair is implemented by loading the window (x,y) registers with $0000 and the window width and height registers with $OFFF. The cursor window may also be used to specify whether PO-P7 address the lower (outside the cursor window) or upper (inside the cursor window) 256 entries in the color palette RAM. 4 - 214 SECTION 4 Bt460 Internal Registers (continued) Window Width and Height Registers These registers are used to specify the width and height (in pixels) of the cross hair cursor window. The window width register is made up of the window width low register (WWLR) and the window width high register (WWHR); the window height register is made up of the window height low register (WHLR) and the window height high register (WHHR). They are not initialized and may be written to or read by the MPU at any time. The window width and height are not updated until the vertical retrace interval after WHHR has been written to by the MPU. WWLR and WWHR are cascaded to form a 12-bit window width register. Similarly, WHLR and WHHR are cascaded to form a 12-bit window height register. Bits D4-D7 of WWHR and WHHR are always a logical zero. Window Width High Window Width Low (WWLR) (WWHR) Data Bit D3 D2 D1 DO D7 D6 D5 D4 D3 D2 D1 DO X Address Xll X10 X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Window Height High Window Height Low (WHHR) (WHLR) Data Bit D3 D2 D1 DO D7 D6 D5 D4 D3 D2 D1 DO Y Address Yll Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO The actual window width is 2, 8, or 10 pixels more than the value specified by the window width register, depending on whether 1:1, 4:1, or 5:1 input mUltiplexing is specified. The actual window height is 2 pixels more than the value specified by the window height register. Therefore, the minimum window width is 2,8, or 10 pixels, for 1:1,4:1, and 5:1 multiplexing, respectively, and the minimum window height is two pixels. Values from $0000 to $OFFF may be written to the window width and height registers. RAMDACs 4 • 215 .. Bt460 Internal Registers (continued) Cursor RAM This 64 x 64 x 2 RAM is used to define the pixel pattern within the 64 x 64 pixel cursor window, and is not initialized. For Revision A, the cursor RAM should not be written to by the MPU during the horizontal sync time and for the two LO* cycles after the end of the horizontal sync. The cursor RAM may otherwise be written to or read by the MPU at any time without contention. If writing to the cursor RAM asynchronously to horizontal sync, it is recommended that the user position the cursor off-screen in the Y direction (write to the cursor (y) registers and wait for the vertical sync interval to move the cursor off-screen), write to the cursor RAM, then reposition the cursor back to the original position. An alternative is to perform a write then read sequence, and if the correct cursor RAM data was not written, perform another write then read sequence. Since the contention occurs only during horizontal sync at the Y locations coincident with the cursor, the second write/read sequence bypasses the window of time when cursor RAM is in contention. For Revision B, cursor contention has been eliminated. The cursor RAM may be written to or read by the MPU at any time without contention. During MPU accesses to the cursor RAM, the address register is used to address the cursor RAM. Figure 12 illustrates the internal format of the cursor RAM, as it appears on the display screen. Addressing starts at location $400 as shown in Table 1. Note that in the X Windows mode, planel serves as a cursor display enable while planeO selects one of two cursor colors (if enabled). Note: in both modes of operation, planel = 07, 05, 03, Dl; planeO = 06, 04, 02, DO. UPPIlR LEFr CORNER AS . DiSPLA YEn ON SCREEN , 64 PIXELS BYTES400 BYTIl $401 BYTIl $401' BYTES410 BYTIl $411 BYTIl$4IF BYTE $7FO BYTIl S7PI BYTIl $7FF 64 PlXllLS I / 4 PIXELS ~ 107.06105.04103,02101.00 1 Nonnal Mode: 00 =color palette or overlay RAM 01 = cursor color 1 10 = cursor color 2 11 = cursor color 3 X·Windows Mode: ()() = color palette or overlay RAM 01 = color palette or overlay RAM 10 =cursor color 2 11 = cursor color 3 Figure 12. 4·216 SECTION 4 Cursor RAM as Displayed on the Screen. Bt460 Pin Descriptions Pin Name Description BLANK* Composite blank control input (TTL compatible). A logical zero drives the analog output to the blanking level, as illustrated in Tables 6 and 7. It is latched on the rising edge of LD*. When BLANK* is a logical zero, the pixel and overlay inputs are ignored. SYNC* Composite sync control inputs (TIL compatible). A logical zero typically switches off a 40 IRE current source on the lOG output (see Figures 9 and 10). SYNC* does not override any other control or data input, as shown in Tables 6 and 7; therefore, it should be asserted only during the blanking interval. SYNC* is latched on the rising edge of LD*. LD* Load control input (TTL compatible). The PO-P8 {A-E}, OLO-OL3 {A-E}, OLE {A-E}, BLANK*, and SYNC* inputs are latched on the rising edge of LD*. LD*, while it is the output clock (1:1 multiplex mode) or is 1/4 or 1/5 of CLOCK, may be phase independent of the CLOCK and CLOCK* inputs. LD* may have any duty cycle, within the limits specified by the AC Characteristics section. PO-P8 Pixel select inputs (TTL compatible). These inputs are used to specify, on a pixel basis, which location of the color palette RAM is to be used to provide color information (see Table 4). Either one, four, or five consecutive pixels (up to 9 bits per pixel) are input through this port. They are latched on the rising edge of LD*. Unused inputs should be connected to aND. Note that typically the {A} pixel is output first, followed by the {B} pixel, etc., until all one, four, or five pixels have been output, at which point the cycle repeats. P8 {A-E} have internal pull-down devices so, if left floating, they assume a logical zero state. {A-E} OW-OL3 {A-E} Overlay select inputs (TTL compatible). These inputs are latched on the rising edge of LD* and, in conjunction with CR05 in command register_O, specify which palette is to be used for color information, as illustrated in Table 4. When accessing the overlay palette RAM, the PO-P8 {A-E} inputs are ignored. Overlay information (up to 4 bits per pixel) for either one, four, or five consecutive pixels are input through this port. Unused inputs should be connected to aND. OLE {A-E} Overlay enable inputs (TTL compatible). In the X Windows mode for overlays, a logical one indicates overlay information is to be displayed. A logical zero indicates to display PO-P8 information. In the normal mode for overlays, these inputs are ignored. They are latched on the rising edge of LD*. Unused inputs should be connected to aND. lOR, lOG, lOB Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 n coaxial cable (Figure 13). All outputs, whether used or not, should have the same output load. IZE* Interleave zoom enable input (TTL compatible). This input should be a logical zero for a minimum of 16 LD* cycles after the falling edge of BLANK* during scan lines that require an interleave shift. If zoom while interleaving is not supported, this pin should be connected directly to aND. CURAC Cursor active output. This output is a logical one while cursor or cross hair window information is being output. It is output following the rising edge of CLOCK. (See Figure 20.) CURDIS* Cursor disable input. A logical zero three-states the CURAC output asynchronously to the clocks. A logical one enables cursor information to be output onto CURAC. CURDIS* has an internal pull-down device so, if left floating, it assumes a logical zero state. (See Figure 20.) RAMDACs 4·217 .. Bt460 Pin Descriptions (continued) Pin Name Description CaMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 J.lF ceramic capacitor must be connected between this pin and VAA (Figure 13). Connecting the capacitor to V AA rather than to aND provides the highest possible power supply noise rejection. The CaMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum and maximize the capacitor's self-resonant frequency to be greater than the LD* frequency. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and aND controls the magnitude of the full-scale video signal (Figure 13). Note that the IRE relationships in Figures 9 and 10 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on lOG is: RSET (0) = Kl * VREF ( V) /lOG (rnA) The full scale output current on lOR and lOB for a given RSET is: lOR, lOB (rnA) = K2 * VREF ( V) I RSET (0) where Kl and K2 are defined as: 100 Setup VREF 4·218 IOR,IOB 7.5 IRE Kl = 11,294 K2 = 8,067 oIRE Kl = 10,684 K2 = 7,457 Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 13, must supply this input with a 1.235 V (typical) reference. The use of a resistor network to generate the reference is not recommended, as any low-frequency power supply noise on VREF will be directly coupled onto the analog outputs. A 0.1 J.lF ceramic capacitor is used to decouple this input to VAA, as shown in Figure 13. If VAA is excessively noisy, better performance may be obtained by decoupling VREF to aND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. SECTION 4 Bt460 Pin Descriptions (continued) Pin Name I'lL Description Phase lock loop output current. This high-impedance current source is used to enable mUltiple Bt460s to be synchronized with sub-pixel resolution when used with an external PLL. A logical one for SYNC* or BLANK* (as specified by CR23 in command register_2) results in no current being output onto this pin, while a logical zero results in the following current being output: PLL (rnA) =3,227 * VREF (V) I RSET (0) If sub-pixel synchronization of multiple devices is not required, this output should be connected to GND (either directly or through a resistor up to 150 0). CLOCK, CLOCK* Clock inputs. These differential clock inputs are designed to be driven by ECL logic configured for single supply (+5 V) operation. The clock rate is typically the pixel clock rate of the system. CE* Chip enable control input (TTL compatible). This input must be a logical zero to enable data to be written to or read from the device. During write operations, data is internally latched on the rising edge of CE*. Care should be taken to avoid glitches on this edge-triggered input. R/W Read/write control input (TTL compatible). To write data to the device, both CE* and R/W must be a logical zero. To read data from the device, CE* must be a logical zero and R/W must be a logical one. R/W is latched on the falling edge of CE*. CO,Cl Command control inputs (TTL compatible). CO and Cl specify the type of read or write operation being performed, as illustrated in Table 1. They are latched on the falling edge of CE*. DO-D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. VM Analog power. All VAA pins must be connected. GND Analog ground. All GND pins must be connected. RAMDACs 4 • 219 .. Bnxj{tree® Bt460 Pin Descriptions (continued) Signal Pin Signal Number BLANK* SYNC* LD* K3 AS CWCK KI CLOCK* IZE* B5 POA POB POC POD POE PIA PIB PIC PlO PIE P2A P2B P2C P2D P2E 4 - 220 Ll K2 E3 D2 01 E2 Pin PSA P8B P8C PSO PSE 014 013 FI4 FI3 EI4 OUJA OUlB OUlC OUlO OUlE EI F2 FI 03 02 OLlA OLlB OLlC OLlD OLlE MI L2 NI L3 M2 OUA 0L2B OL2C 0L2D OUE M3 N2 PI P2 N3 OL3A OL3B OL3C 0L30 OL3E M4 P3 N4 P4 M5 OlEA OLEB OLEC OlEO N5 P5 M6 N6 P6 F3 Al D3 C2 BI CI A3 B3 A2 C3 B2 P3A P3B P3C P3D P3E A8 A7 B7 A6 B6 P4A P4B P4C P4D P4E C9 B9 P5A P5B P5C P5D P5E Bll All CIO BIO AlO P6A P6B P6C P6D P6E AI4 A13 BI2 Cll Al2 P7A P7B P7C P7D P7E E13 EI2 014 013 012 A9 C8 B8 SECTION 4 Signal Number GND GND GND GND GND GND GND GND COMP FSADmST VREF CE* R/W CI CO lOG lOB lOR PIL PIO Pll NIO Nll CURAC CURDIS* A4 C5 VAA VAA VAA VAA VAA VAA VAA VAA VAA 11 12 J3 C6 FI2 M9 P7 P8 N8 HI H2 H3 C7 GI2 M8 M7 N7 N9 MIO P9 P13 NI2 PI2 Mll 07 Ll3 MI4 LI2 MI3 N14 PI4 NI3 MI2 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 113 114 HI2 H13 HI4 B4 C4 C14 CI3 Bl4 CI2 B13 LI4 KI2 112 K14 K13 DO 01 D2 D3 D4 05 0lEE Pin Number D6 Bt460 Pin Descriptions (continued) 14 NiC Dl D4 D5 13 DO D3 D6 CE' 12 D2 111 11 P5B P5A P5C 10 Bt460 P3B P3C GND CI (]) Ill. FS AD! lOR VAA roM' VREP GND VM VM GND GND VAA 0L3E OlEA OUlB 100 MHz). The VREF inputs of the Bt460s must still be isolated by 100 !l resistors. as shown in Figure 15. and have a 0.1 ~F bypass capacitor to VAA. The designer must take care to minimize skew on the CLOCK and CLOCK* lines. The PLL outputs of the Bt460s would not be used and should be connected to GND (either directly or through a resistor up to 150 !l). Higher performance may be obtained if each Bt460 has its own voltage reference. This may further reduce the amount of color channel crosstalk and color palette interaction. Each Bt460 must still have its own individual RSET resistor. analog output termination resistors. power supply bypass capacitors. COMP capacitor. and VREF capacitor. I'lL +SV CLOCK 14 CLOCK' MONITOR Bt460 PRODUcrS #1 9700 Bt439 +sv I'lLI CLOCK @ CLOCK' FROM BT460 !D' VAA Bt460 #2 TOJ VREI' @T@:r 330 I'lL CLOCK 100 CLOCK' !D' VREI' VAA TOJ VREI' Figure 15. 4 - 226 Generating the Clock Signals for Multiple Bt460s. SECTION 4 Bt460 #3 Bt460 Application Information (continued) Setting the Pipeline Delay The pipeline delay of the Bt460, although fixed after a power-up condition, may be anywhere from six to ten clock cycles. The Bt460 contains additional circuitry enabling the pipeline delay to be fixed at eight clock cycles. The Bt438 and Bt439 Clock Generator Chips support this mode of operation when used with the Bt460. synchronized. In this instance, the blink mask register should be $00 and the overlay blink enable bits a logical zero. Blinking may be done under software control via the read mask register and overlay display enable bits. The resetting of the Bt460 to an eight cycle pipeline delay is required for proper cursor pixel alignment. Interleave Operation To reset the Bt460, it should be powered up, with LD*, CLOCK, and CLOCK* running. Stop the CLOCK and CLOCK* signals with CLOCK high and CLOCK* low for at least three rising edges of LD*. There is no upper limit on how long the device can be held with CLOCK and CLOCK* stopped. Restart CLOCK and CLOCK* so that the first edge of the signals is as close as possible to the rising edge of LD* (the falling edge of CLOCK leads the rising edge of LD* by no more than 1 clock cycle or follows the rising edge of LD* by no more than 1.5 clock cycles). When restarting the clocks, care must be taken to ensure that the minimum clock pulse width is not violated. To support interleaved frame buffers, the Bt460 may be configured for various interleave factors, as shown in Table 8. Table 9 shows an example of interleave operation for 4: 1 multiplexing, an interleave select of 3, and starting with pixel {AJ. Table 10 shows the same operation with pixel {B J selected as the starting pixel (the display has been panned down three scan lines). Scan line number 0 corresponds to the top of the display screen and is the first displayed scan line after a vertical blanking interval. The output sequence is shown starting at the left-most displayed pixel. ESD and Latchup Considerations In order to assure the Bt460 has the proper confiuration, all the command registers must be initialized prior to a fixed pipeline reset. Because of this requirement, the power up which occurs prior to initialization of the command registers cannot be used to assure the fixed pipeline. An additional reset is required after command register writes. The resetting of the B t460 to an eight clock cycle pipeline delay does not reset the blink counter circuitry. Therefore, if the multiple Bt460s are used in parallel, the on-chip blink counters may not be Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. Latchup can be prevented by assuring that all V AA pins are at the same potential, and that the V AA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. Scan Line Output Sequence Scan Line Output Sequence 0 1 2 3 4 5 6 ABCDABCD ... DABCDABC ... CDABCDAB ... BCDABCDA... ABCDABCD ... DABCDABC ... CDABCDAB ... BCDABCDA... 0 1 2 3 4 5 6 7 BCDABCDA... ABCDABCD ... DABCDABC ... CDABCDAB ... BCDABCDA ... ABCDABCD ... DABCDABC ... CDABCDAB ... : : : 7 : Table 9. Interleave Example. Table 10. Interleave Example. RAMDACs 4 • 227 Bt460 Application Information (continued) Test Features of the Bt460 The Bt460 contains three dedicated test registers and an analog output comparator that assist the user in evaluating the performance and functionality of the part. This section is intended to explain the operating usage of these test features. Signature Registers (Signature Mode) The input signature register is 8 bits wide, capturing pixel information prior to the lookup table. Since the pixel path is 9 bits wide, the P7 or P8 pixel input, in conjunction with the PO-P6 pixel inputs, are selected for capture via command bit CR65. The output signature register, in the active mode, operates with the 24 bits of data that are output from the color palette RAM. These 24-bit vectors represent a single pixel color, and are presented as inputs simultaneously to the red, green, and blue output signature analysis registers (output SARs), as well as the three on-chip OACs. The output SARs act as a 24-bit wide Linear Feedback Shift Register on each succeeding pixel that is latched. It is important to note that in either the 4: 1 or 5: 1 multiplexed modes the SARs only latch one pixel per "load group." Thus the SARs are operating on only every fourth or fifth pixel in the mUltiplexed modes. The user determines which pixel phase (A, B, C, 0, or E) is latched for generating new signatures by setting bits 00-02 in the Test Register. In 1: 1 mux mode, the SARs will generate signatures truly on each succeeding pixel in the input stream. In this case, the user should always select pixel "A" (Test Register DO, 01, and 02 =000) when in the 1:1 mode, since the "A" pixel pins are the only active pixel inputs. The Bt460 will only generate signatures while in "active-display" (BLANK* negated). The SARs are available for reading and writing via the MPU port when the Bt460 is in a blanking state (BLANK* asserted). Specifically, it is safe to access the SARs after the OAC outputs are in the blanking state (up to 15 pixel clock periods after BLANK* is asserted). Typically, the user will write a specific 8-bit or 24-bit "seed" value into the SARs. Then, a known pixel stream will be input to the chip, say one scan-line or one frame buffer worth of pixels. Then, at the 4· 228 SECTION 4 succeeding blank state, the resultant 8-bit or 24-bit signature can be read out by the MPU. The 24-bit signature register data is a result of the same captured data that is fed to the OACs. Thus, overlay and cursor data validity is also tested using the signature registers. Assuming the chip is running 4:1 or 5:1 mux modes, the above process would be repeated with all different pixel phases-A, B, C, etc.-being selected. It is not simple to specify the algorithm which specifies the linear feedback shift operations used in the Bt460. The linear feedback configurations are shown in Figures 16 and 17. Note that each register internally uses XORs at each input bit (On) with the output (result) by one least significant bit (On-I). Experienced users have developed tables of specific seeds and pixel streams and recorded the signatures that result from those inputs applied to '·known-good" parts. Note that a good signature from one given pixel stream can be used as the seed for the succeeding stream to be tested. Any signature is deterministically created from a starting seed and the succeeding pixel stream fed to the SARs. Signature Registers (Data Strobe Mode) Setting command bit CR20 to "I" puts the SARs into data strobe mode. In this instance, the linear feedback circuits of the SARs are disabled, which stops the SARs from generating signatures. Instead, the SARs simply capture and hold the respective pixel phase that is selected. Any MPU data written to the SARs is ignored. One use, however, is to directly check each pixel value that is strobed into the SARs. To read out values captured in the middle of a pixel stream, the user should first freeze all inputs to the B t460. The levels of most inputs do not matter EXCEPT that CLOCK should be high, and CLOCK* should be low. Then, the user may read out the pixel color by doing three successive MPU reads from the red, green, and blue output SARs, respectively. Likewise, the input SAR may be read with one MPU read. In general, the color read out will correspond to a pixel latched on the previous load. However, due to the pipelined data path, the color may come from an earlier load cycle. To read successive pixels, toggle LO*, pulse the CLOCK pins according to the mux state (I, 4, or 5 periods), then hold all pixel-related inputs and perform the three MPU reads as described. This overall process is best done on a sophisticated VLSI semiconductor Tester. Bt460 Application Information (continued) RO·R1 PROM LOOKUPTABLH 00·01 PROM LOOKUPTABLH • Figure 16. 8O·B1 PROM LOOKUP TABLH MPU SAR READ BIT Output Signature Analysis Register Circuit. RAMDACs 4 • 229 Bt460 Application Information (continued) Analog Comparator The other dedicated test structure in the Bt460 is the analog output comparator. It allows the user to measure the DACs against each other, as well as against a specific reference voltage. Four combinations of tests are selected via the Test Register. With a given setting, the respective signals (DAC outputs or the 145 mV reference) will be continuously input to the comparator. The result of the comparator is latched into the Test Register on each of the 64 scan lines of the 64 x 64 user-defined cursor block (the 64 x 64 cursor must be enabled for display). On each of these 64 scan lines, the capture occurs over one LD* period that corresponds to the cursor (x) position, set by the 12-bit cursor (x) register. Due to the simple design of the comparator, it is recommended that the DAC outputs be stable for 5 J.Ls before capture. At a display rate of 100 MHz, 5 J.Ls corresponds to 500 pixels. In this case, the cursor (x) position should be set to well over 500 pixels to ensure an adequate supply of pixels. Furthermore, either the color palette RAM or the pixel inputs (or both) should be configured to guarantee a single continuous output from the DACs under test, up until capture. Typically, users will create screen-wide test bands of various colors. Various comparison cases are set up by moving the cursor up and down (by changing the 12-bit cursor (y) register) over these bands. For each test, the result is obtained by reading Test Register bit D3. To obtain a meaningful comparison, the cursor should be located on the visible screen. There is no significance to the cursor pattern data in the cursor RAM. For a visual reference, the capture point actually occurs over the left-most edge of the 64 x 64 cursor block. PO·P(j.P70RPS • Figure 17. 4·230 SECTION 4 MPUSARREADBIT Input Signature Analysis Register Circuit. Bt460 Application Information (continued) Load Cursor RAM Pattern Initializ.ing the Bt460 Following a power-on sequence, the Bt460 must be initialized. This sequence will configure the Bt460 as follows: 4:1 multiplexed operation no overlays, no blinking, no interleave 64 x 64 block cursor, no cross hair cursor 9 bits per pixel, no panning, no zoom sync enabled on 100, 7.S IRE blanking pedestal Control Register Initialization Cl, CO Write $01 to address register low Write $02 to address register high Write $40 to command register_O Write $00 to command register_l Write $CO to command registec2 Write $FF to pixel read mask register low Write $01 to pixel read mask register high Write $00 to pixel blink mask register low Write $00 to pixel blink mask register high Write $00 to overlay read mask register Write $00 to overlay blink mask register Write $00 to interleave register Write $00 to test register Write $OF to address register low Write $14 to command register_3 00 01 10 10 10 10 10 10 10 10 10 10 10 00 10 Write $00 to address register low Write $03 to address register high Write $CO to cursor command register Write $00 to cursor (x) low register Write $00 to cursor (x) high register Write $00 to cursor (y) low register Write $00 to cursor (y) high register Write $00 to window (x) low register Write $00 to window (x) high register Write $00 to window (y) low register Write $00 to window (y) high register Write $00 to window width low register Write $00 to window width high register Write $00 to window height low register Write $00 to window height high register 00 01 10 10 10 10 10 10 10 10 10 10 10 10 10 Write $00 to address register low Write $04 to address register high Write $FF to cursor RAM (location $000) Write $FF to cursor RAM (location $001) 00 01 10 10 Write $FF to cursor RAM (location $3FF) 10 Color Palette RAM Initialization Write $00 to address register low Write $00 to address register high Write red data to RAM (location $000) Write green data to RAM (location $000) Write blue data to RAM (location $000) Write red data to RAM (location $001) Write green data to RAM (location $001) Write blue data to RAM (location $001) 00 01 11 11 11 11 11 11 Write red data to RAM (location $IFF) Write green data to RAM (location $IFF) Write blue data to RAM (location $IFF) 11 11 11 Overlay Color Palette Initialization Write $00 to address register low Write $01 to address register high Write red data to overlay (location $0) Write green data to overlay (location $0) Write blue data to overlay (location $0) Write red data to overlay (location $1) Write green data to overlay (location $1) Write blue data to overlay (location $1) 00 01 10 10 10 10 10 10 Write red data to overlay (location $F) Write green data to overlay (location $F) Write blue data to overlay (location $F) 10 10 10 Cursor Color Palette Initialization Write $81 to address register low Write $01 to address register high Write red data to cursor (location $0) Write green data to cursor (location $0) Write blue data to cursor (location SO) Write red data to cursor (location $1) Write green data to cursor (location $1) Write blue data to cursor (location $1) Write red data to cursor (location $2) Write green data to cursor (location $2) Write blue data to cursor (location $2) RAMDACs 00 01 10 10 10 10 10 10 10 10 10 4 - 231 - Bt460 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage FS ADJUST Resistor Symbol Min Typ Max Units VAA TA 4.75 0 5.00 5.25 +70 Volts ·C Ohms Volts Ohms RL VREF RSEI' 1.20 37.5 1.235 523 1.26 Symbol Min Typ Max Units 6.5 Volts VAA + 0.5 Volts TJ +125 +150 +150 ·C ·C ·C TSOL 260 ·C Absolute Maximum Ratings Parameter VAA (measured to GND) GND-0.5 Voltage on Any Signal Pin· Analog Output Short Circuit Duration to Any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds. 1/4" from pin) indefinite ISC TA TS -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. • This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. 4 - 232 SECTION 4 Bt460 DC Characteristics Parameter Analog Outputs Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs (except CLOCK, CLOCK*) Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) P8 {A-E}, CURDIS* Other Inputs Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Yin = 2.4 V) Clock Inputs (CLOCK, CLOCK*) Differential Input Voltage Input High Current (Vin = 4.0 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Yin = 4.0 V) Digital Outputs (DO-D7, CURAC) Output High Voltage (lOH = -400 !LA) Output Low Voltage (lOL = 3.2 rnA) 3-state Current Output Capacitance Symbol Min Typ Max Units 8 8 8 Bits ±1 ±1 ±5 LSB LSB % Gray Scale IL IL guaranteed Binary V1H VIL 2.0 GND-O.5 VAA+0.5 0.8 Volts Volts 4 60 1 -1 10 j.IA j.IA j.IA pF 4 6 1 -1 10 Volts j.IA j.IA pF IIH IlL CIN L\VJN .6 IK1H IKIL CKIN VOO: Volts 2.4 VOL IOZ CDOUT 0.4 Volts 10 j.IA pF 10 See test conditions on next page. RAMDACs 4 • 233 Bt460 DC Characteristics (continued) Parameter Analog Outputs Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank SETUP = 7.5 IRE SETUP=OIRE Blank Level - Sync Enabled Blank Level - Sync Disabled Sync Level (If Enabled) LSB Size DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 mA) Symbol vee Min Typ Max Units 17.69 16.74 19.05 17.62 20.40 18.50 rnA rnA 0.95 0 6.29 0 0 1.44 5 7.62 5 5 69.1 2 1.90 50 8.96 50 50 rnA 5 +1.2 % Volts kQ pF -0.5 50 13 RAOur CAOur 20 J.l.A rnA J.l.A J.l.A J.l.A PLL Analog Output Output Current SYNC*/BLANK* = 0 SYNC*/BLANK* = 1 Output Compliance Output Impedance Output Capacitance (f= 1 MHz,PLL=OmA) PlL Voltage Reference Input Current IREF 100 J.l.A Power Supply Rejection Ratio (COMP = O.IIJF, f= 1 kHz) PSRR 0.5 %/%t:NAA 6.00 0 -1.0 7.62 5 50 8 9.00 50 +2.5 15 rnA J.l.A Volts kQ pF Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 Q, VREF = 1.235 V. SETUP = 7.5 IRE. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, Le., 5 V. 4· 234 SECTION 4 Bt460 AC Characteristics Parameter Clock Rate Rate 1:1 mUltiplexing 4:1 mUltiplexing 5:1 multiplexing LI)* Symbol Min/Typ/ Max 135 MHz 110 MHz 80 MHz Units Fmax max 135 110 80 MHz max max max 50 33.75 27 50 27.5 22 50 20 16 MHz MHz MHz LOmax RIW, CO, Cl Setup Time RIW, CO, Cl Hold Time 1 2 min min 0 10 0 10 0 10 ns ns CE*LowTime CE* High Time CE* Asserted to Data Bus Driven CE* Asserted to Data Valid CE* Negated to Data Bus 3-Stated 3 4 5 6 7 min min min max max 40 20 5 40 12 40 20 5 40 12 40 20 5 40 12 ns ns ns ns ns Write Data Setup Time Write Data Hold Time 8 9 min min 15 2 15 2 15 2 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 10 11 min min 3 2 3 2 3 2 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time 12 13 14 min min min 7.4 3.2 3.2 9.09 4 4 12.5 5 5 ns ns ns LD* Cycle Time 1: 1 multiplexing 4: 1 multiplexing 5:1 multiplexing LO* Pulse Width High Time 1:1 multiplexing 4: 1 or 5: 1 multiplexing LD* Pulse Width Low Time 1:1 multiplexing 4: 1 or 5: 1 multiplexing 15 min min min 15.15 29.63 37.04 20 36.36 45.45 20 50 62.5 ns ns ns min min 6 12 7 15 7 20 ns ns min min 6 12 7 15 7 20 ns ns typ typ typ 18 tbd tbd 18 tbd tbd 18 tbd tbd ns ns ns CURAC Output Delay CURAC Disable Time CURAC Enable Time 16 17 18 19 20 See test conditions on next page. RAMDACs 4·235 Bt460 AC Characteristics (continued) Parameter Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time Clock and Data Feedthrough. Glitch Impulse· DAC to DAC Crosstalk Analog Output Skew Symbol 21 22 23 Pipeline Delay VAA Supply Current·· IAA Minrryp/ Max Units 135 110 80 MHz MHz MHz ns ns ns dB pV - sec dB ns ns typ typ max typ typ typ typ max 12 12 1.5 1.5 8 tbd 50 tbd 0 2 8 tbd 50 tbd 0 2 12 2 12 tbd 50 tbd 0 2 min max 6 10 6 10 6 10 Clocks Clocks typ max 390 420 360 400 320 370 rnA rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 n, VREF = 1.235 V. TTL input values are 0-3 V, with input rise/fall times s 4 ns, measured between the 10% and 90% points. ECL input values are VAA~.8 to VAA-1.8 V, with input rise/fall times S 2 ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. Analog output load S 10 pF, DO-D7 output load S 75 pF. CURAC output load S 5 pF. See timing notes in Figure 19. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. ·Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the TTL digital inputs have a 1 ill resistor to GND and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 2x clock rate. ··AtFmax. IAA (typ) at VAA = 5.0 V, TA = 20" C. lAA (max) atVAA =5.25 V, TA=O· C. 4·236 SECTION 4 BnxKtree~ Bt460 Timing Waveforms I RIW, CO, Cl ....L. 1 VALID , 3 ~I Cl· 4 6 I 5 V DO· D7 (RIlAD) ....... DO· D7 (WlUfB) DATA our (RIW -I) R ./ DATA IN (RIW - 0) J B .. P Figure 18. MPU Read/Write Timing Dimensions. 16 PO·PI {A· B). OLB IA·B), 0L0·01.3 (A·B), SYNC·, BLANK· 17 DATA 10 11 21 23 lOR, lOG. lOB. I'lL 21 12 CLOCK 14 Note 1: Output delay time measured from 50% point of the rising clock edge to 50% point of fullscale transition. Note 2: Output settling time measured from 50% point of full-scale transition to output settling within ±1 LSB. Note 3: Output rise/fall time measured between 10% and 90% points of full-scale transition. Figure 19. Video Input/Output Timing. RAMDACs 4 - 237 Bt460 Timing Waveforms (continued) IOR,IOB, 100 C\JRAC DATA(N) Figure 20. Cursor Output Timing. Ordering Information Model Number Speed Package Ambient Temperature Range Bt460KG135 135 MHz 132-pin Ceramic 0" to +70· C PGA Bt460KGllO 110 MHz 132-pin Ceramic O· to +70· C PGA Bt460KG80 80 MHz 132-pin Ceramic PGA 4 - 238 SECTION 4 0" to +70· C Bt460 Revision History Change from Previous Revision Datasheet Revision B Full datasheet. C Expanded PCB layout section, added using test features to Application Information section. Clarified MPU contention with cursor RAM in Cursor RAM section of Internal Registers. D Added double reset, modified PLL feedback circuitry. Added revision register section and eliminated write contention for revision B devices. Device Revision B .. Added revision register, eliminated write contention. RAMDACs 4 - 239 Preliminary Information This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. Distinguishing Features Applications 170, 135, no, 80 MHz Operation 3:1,4:1, or 5:1 Pixel Input Muxing Single 8-bit D/A Converter 1024 x 8 Primary Color Palette RAM 256 x 8 Alternate Color Palette RAM 32 x 8 Overlay Color Palette RAM RS-343A-Compatible Output Pixel Panning Support Programmable Setup (0 or 7.5 IRE) Bit Plane Read and Blink Masks Two Load Color Palette Modes • Standard MPU Interface 132-pin PGA or PQFP Package • • • • • • • • High-Resolution Color Graphics True-Color Graphics Systems CAE/CAD/CAM Image Processing Video Reconstruction !D" CLOCK VAA Product Description The Bt461/462 single-channel RAMDACs are designed specifically for high-performance, highresolution color graphics. The multiple pixel ports and internal multiplexing enable TTLcompatible interfacing (up to 45 MHz) to the frame buffer, while maintaining the 170-MHz video data rates required for sophisticated color graphics. • Bt431, Bt438, Bt439 Bt459, Bt460, Bt468 GND FS ADJUST VREF L--~/I-1r COMP - 1 -.....--1 ",.P9 (A·E) ALT (A-E) (OIIT OLO-OlA (A-E) I'LL BLANK" --,~_~..... CE· R/W I co Cl Brooktree Corporation 9950 Bames Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 L461001 Rev. H 170 MHz Monolithic CMOS lK x 8 Color Palette RAMDAC™ Related Products Functional Block Diagram a..OCK· Bt461 Bt462 On chip features include a 1024 x 8 dual-port color palette RAM, a 256 x 8 dual-port alternate color palette RAM, 32 x 8 overlay color palette RAM, programmable 3:1, 4:1, or 5:1 input multiplexing of the pixel and overlay ports, bit plane masking and blinking, programmable setup (0 or 7.5 IRE), and pixel panning support. The B t462 also supports an optional under lay mode; only 15 overlays are available when the underlay is used. Color data may be written to and read from the Bt461/462 by the MPU each cycle or using red, green, blue cycles. The MPU interface operates asynchronously to the pixel data, simplifying system design. The PLL current output enables the synchronization of mUltiple Bt461/462s with sub-pixel resolution. 00-D7 4 - 241 .. Bt461/462 Circuit Description MPU Interface Reading/Writing Color Data (Normal Mode) As illustrated in the functional block diagram, the Bt4611462 supports a standard MPU bus interface, allowing the MPU direct access to the internal control registers and color palettes. The dual-port color palette RAMs and dual-port overlay RAM allow color updating without contention with the display refresh process. As illustrated in Table I, the CO and Cl control inputs, in conjunction with the internal address register, specify which control register or color palette location will be accessed by the MPU. The 10-bit address register eliminates the requirement for external address multiplexers. ADDRO is the least significant bit. There are two ways of reading and writing color data to the device, as controlled by command register_O. The rust mode (normal mode), loads color data into the device each write cycle, and outputs color data from the device each read cycle. The second mode (ROB mode) loads color data into the device using red, green, blue write cycles, and outputs data from the device using red, green, blue read cycles. The device is configured to respond only to the color cycle specified by the command register. This mode is useful if a 24-bit data bus is available, as 24 bits of color information (8 bits each of red, green, blue) may be read or written to three Bt461/462s in a single MPU cycle. In this application, the CE* inputs of all three Bt4611462s are connected together. If only an 8-bit data bus is available, the CE* inputs must be individually selected during the appropriate color write cycle (red CE* during red write cycle, blue CE* during blue write cycle, etc.). When accessing the primary color palette RAM, the address register resets to $0000 after a read or write cycle to location $03FF. When accessing the color palette RAMs or the overlay RAM, the address register increments after each read or write cycle. ADDRO-IS Cl CO Addressed by MPU $xxxx $xxxx $OOOO-$OOFF $0100 0 0 1 1 0 1 0 0 address register low (ADDR0-7) address register high (ADDR8-9) alternate color palette RAM overlay color 0 : : : : $OllF $0200 $0201 $0202 $0203 $0204 $0205 $0206 $0207 $0208 $0209 $020C 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 overlay color 31 ID register command register_O command register_l command register_2 pixel read mask register low pixel read mask register high pixel blink mask register low pixel blink mask register high overlay read mask register overlay blink mask register test register $0000-$03FF 1 1 primary color palette RAM Table 1. 4 - 242 To write color data, the MPU loads the address register with the address of the primary color palette RAM, alternate color palette RAM, or overlay RAM location to be modified. The MPU performs a color write cycle, using CO and C 1 to select either the primary color palette RAM, alternate color palette RAM, or the overlay palette RAM. The address register then increments to the next location, which the MPU may modify by simply writing another color. Reading color data is similar to writing, except the MPU executes read cycles. SECTION 4 Address Register (ADDR) Operation. Bt461/462 Circuit Description (continued) Reading/Writing Color Data (RGB Mode) To write color data, the MPU loads the address register with the address of the primary color palette RAM, alternate color palette RAM, or overlay RAM location to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using CO and Cl to select either the primary color palette RAM, alternate color palette RAM, or overlay RAM. After the blue write cycle, the address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. Reading color data is similar to writing, except the MPU executes read cycles. This mode is useful if only an 8-bit data bus is available. Each Bt461/462 is programmed to be a red, green, or blue RAMDAC, and will respond only to the assigned color read or write cycle. In this application, the Bt461/462s share a common 8-bit data bus. The CE* inputs of all three B t461/462s must be asserted simultaneously only during color read/write cycles and address register write cycles. When accessing the primary color palette RAM, the address register resets to $0000 after a blue read or write cycle to location $03FF. When accessing the color palette RAMs or the overlay RAM, the address register increments after each blue read or write cycle. To keep track of the red, green, and blue read/write cycles, the address register has 2 additional bits (ADDRa, ADDRb) that count modulo three. They are reset to zero when the MPU reads or writes to the address register. The MPU does not have access to these bits. The other 10 bits of the address register (ADDR0-9) are accessible to the MPU. RIW. CO. CI ==x VALID Command registerO is used to specify whether the device loads or outputs data during the red, green, or blue cycle. This mode is useful if only an 8-bit data bus is available, and the software drivers are written for ROB operation. Note that CE* must be a logical zero during each of the red, green, blue read/write cycles. Additional Information Although the color palette RAMs and overlay RAM are dual-ported, if the pixel and overlay data is addressing the same palette entry being written to by the MPU during the write cycle, it is possible for one or more of the pixels on the display screen to be disturbed. A maximum of one pixel is disturbed if the write data from the MPU is valid during the entire chip enable time. Accessing the control registers is also done through the address register in conjunction with the CO and C 1 inputs, as shown in Table 1. All control registers may be written to or read by the MPU at any time. The address register does not increment following read or write cycles to the control registers, facilitating read-modify-write operations. ADDRO and ADDR8 correspond to DO. ADDRIO-ADDR15 are always a logical zero. Note that if an invalid address is loaded into the address register, data written to the device will be ignored and invalid data will be read by the MPU. Figure 1 illustrates the MPU read/write timing of the Bt461/462. X ~-------------------------------------- \ DO - D7 (READ) DO· D7 (WRITE) / -----------< DATA OlIT(R/W _______________X Figure 1. =1) DATA IN (R/W =0) )>----- x'--____ MPU Read/Write Timing. RAMDACs 4 • 243 .. Bt461/462 Circuit Description (continued) Frame Buffer Interface To enable pixel data to be transferred from the frame buffer at TTL data rates, the Bt461/462 incorporates internal latches and multiplexers. As illustrated in Figure 2, on the rising edge of LD*, sync and blank information, color, and overlay information, for either three, four, or five consecutive pixels, are latched into the device. Note that with this configuration, the sync and blank timing will be recognized only with three, four, or five pixel resolution. Typically, the LD* signal is used to clock external circuitry to generate the basic video timing and to clock the video DRAMs. Typically, the (A} pixel is output fust, followed by the (B} pixel, etc, until all three, four, or five pixels have been output, at which point the cycle repeats. The overlay inputs may have pixel timing, facilitating the use of additional bit planes in the frame buffer to control overlay selection on a pixel basis, or they may be controlled by external circuitry. To simplify the frame buffer interface timing, LD* may be phase-shifted, in any amount, relative to CLOCK. This enables the LD* signal to be derived by externally dividing CLOCK by three, four, or five, independent of the propagation delays of the LD* generation logic. As a result, the pixel and overlay data are latched on the rising edge of LD*, independent of the clock phase. Internal logic maintains an internal LOAD signal, synchronous to CLOCK, and is guaranteed to follow the LD* signal by at least one, but not more than three, clock cycles. This LOAD signal transfers the latched pixel and overlay data into a second set of latches, which are then internally multiplexed at the pixel clock rate. If 3:1 multiplexing is specified, only one rising edge of LD* should occur every three clock cycles. If 4:1 multiplexing is specified, only one rising edge of LD* should occur every four clock cycles. If 5: 1 multiplexing is specified, only one rising edge of LD* should occur every five clock cycles. Otherwise, the internal LOAD generation circuitry assumes it is not locked onto the LD* signal, and will continuously attempt to resynchronize itself to LD*. Note that 3:1 multiplexing may not used at the 170 MHz pixel clock rate. PO - P9 (A· BI. ALT (A- BI OLO·OIA(A·BI. SYNC-. BLANK" lOUT. PU.. CLOCK Figure 2. 4 - 244 SECTION 4 Video Input/Output Timing. be Bt461/462 Circuit Description (continued) Read and Blink Masking Alternate Color Palette RAM Each clock cycle, 10 bits of color information (PO-P9, ALT) and 5 bits of overlay information (OLO-OlA) for each pixel are processed by the read mask, blink mask, and command registers. Through the use of the control registers, individual pixel and overlay inputs may be enabled or disabled for display, and/or blinked at one of four blink rates and duty cycles. Note that the pixel read mask and blink mask registers can also be used when the pixel inputs are addressing the alternate color palette RAM. If the ALT enable bit in command register_O is a logical one, the alternate color palette RAM may be accessed on a pixel basis. A logical one on an ALT (A-E) input forces the PO-P7 (A-E) inputs to address the alternate color palette RAM. P8 and P9 (A-E) are ignored in this instance. If the ALT enable bit in command register_O is a logical zero, the ALT (A-E) inputs are ignored, as shown in Tables 2 and 3. To ensure that a color change due to blinking does not occur during the active display time (i.e., in the middle of the screen), the Bt461/462 monitors the BLANK* input to determine vertical retrace intervals. A vertical retrace interval is recognized by determining that BLANK* has been a logical zero for at least 256 LD* cycles. Pixel bypassing of the primary color palette RAM may be implemented by using the ALT inputs. In this instance, the alternate color palette RAM should be loaded so that each byte contains its corresponding address ($OO-$FF), or with a gamma correction factor. The ALT inputs would then specify, on a pixel basis, whether or not to bypass the primary color palette RAM. The processed pixel data is then used to select which color palette entry or overlay register is to provide color information. Note that PO is the LSB when addressing the color palette RAMs, and OLO is the LSB when addressing the overlay palette RAM. Table CR04 ALT CR05 OLO-OlA PO- P9 Addressed by frame buffer x x x $IF $xxx overlay color 31 : : : : : : x x x x x 1 $01 $00 $xxx $xxx overlay color 1 overlay color 0 0 0 x x 0 x $00 $00 $000 $001 primary RAM location $000 primary RAM location $001 : : : : : : 0 x x $00 $3FF primary RAM location $3FF x x 0 0 0 x $00 $00 $000 $001 primary RAM location $000 primary RAM location $001 : : : : : : x 0 x $00 $3FF primary RAM location $3FF 1 1 : : 0 x $00 : $xOO $xOl alternate RAM location $00 alternate RAM location $01 : 1 1 Table 2. : : : x $00 : : $xFF alternate RAM location $FF Bt461-Palette and Overlay Select Truth Table. RAMDACs 4 • 245 .. Bt461/462 Circuit Description (continued) CR22 CR04 ALT CR05 OlA OLO-OL3 PO-P9 Addressed by Frame Buffer x x x x 1 1111 $xxx : : : : : : : : : : : : : : : : 1 0 0000 1111 : : x x x x 1 : : : : 0 0000 $xxx overlay color 31 : overlay color 16 overlay color 15 : overlay color 0 0 x 0 : : 0 x 0 0000 : : $000 $001 : $3FF primary RAM location $3FF x 0 : : $000 $001 primary RAM location $000 primary RAM location $001 : : : x x 0 x : x 1 : 1 1 : 1 1 x : : : : 1 x x : x 0 x : 0 x : x : : : x 0 0000 0 x 0 0000 : : : : : : : x 0 0000 $3FF primary RAM location $3FF x 0 0000 $xOO : : : : x 0 0000 $xFF alternate RAM location $00 : alternate RAM location $FF x x 0 1111 $xxx : : : : : : x 0 0 1 0001 0000 $xxx $000 Table 3. 4 ·246 primary RAM location $000 primary RAM location $001 : : overlay color 15 : overlay color 1 overlay color 0 (underlay) Bt462-Palette and Overlay Select Truth Table. SECTION 4 Bt461/462 Circuit Description (continued) Pixel Panning Video Generation To support pixel panning, command register_l specifies by how many clock cycles to pan. Every clock cycle, the selected 8 bits of color information are presented to the 8-bit D/A converter. If O-pixel panning is specified, pixel (A) is output first, followed by pixel {B}, etc., until all 3, 4, or 5 pixels have been output, at which point the cycle repeats. The SYNC* and BLANK* inputs, pipelined to maintain synchronization with the pixel data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figures 3 and 4. Command register2 specifies whether a 0 IRE or 7.5 IRE blanking pedestal is to be generated, and whether or not sync information is to be encoded on the video output. A 0 IRE pedestal will force the black level and the blank level to be the same. If I-pixel panning is specified, pixel (B) will be flIst, followed by pixel {C}, etc. Pixel {A} will have been processed during the last clock cycle of the blanking interval, and will not be seen on the display screen. At the end of the active display line, pixel {A} will be output. Pixels {B}, {C}, {D}, and {E} will be output during the blanking interval, and will not be seen on the display screen. The process is similar for panning by 2, 3, or 4 pixels. Note that when a panning value other than 0 pixels is specified, valid pixel data must be loaded into the Bt461/462 during the first LD* cycle that BLANK* is a logical zero. The pixel, overlay, and ALT inputs are all panned. Underlay Operation (Bt462 Only) An underlay plane can be obtained by converting overlay plane 4 (OL4) to underlay operation (command register bit CR22). In this mode of operation, only 15 overlays (OLO-OL3) are available, as shown in Table 3. The varying output current from the D/A converter produces a corresponding voltage level, which is used to drive the CRT monitor. Tables 4 and 5 detail how the SYNC* and BLANK* inputs modify the output levels. The D/A converter on the Bt461/462 uses a segmented architecture in which bit currents are routed to either the current output or GND by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabilizes the full-scale output current against temperature and power supply variations. Note that, during underlay operation, the corresponding overlay plane 4 (OL4) overlay read mask register bit must be a logical zero for proper operation. Underlays may be displayed on a pixel basis. Both overlays and the underlay may be used at the same time. The priority of the display information is: overlays (OLO-OL3) pixel data (PO-P9) underlay (OL4) RAMDACs 4 - 247 .. Bt461/462 Circuit Description (continued) CR27=O CR27=1 MA V MA 19.05 0.714 26./f/ 1.000 -r-----,.---------------------~~------WHITELEVa 1A4 0.054 9.05 0340 +-----------;---------f----------------- BLACK LEVEL 0.00 0.000 7.62 0.286 -+-------------'---r---r-""'------------------- 0.00 0.000 -'-----------------'-~-------------------- V 7.5 IRE BLANK LEva 40 IRE Note: 75 n doubly tenninated load. RSET = 523 tolerances assumed on all levels. Figure 3. n. VREF = 1.235 V. WHITE DATA DATA-SYNC BlACK BlACK-SYNC BLANK SYNC Table 4. 7.5 IRE). IOUT(mA) (CR27 = 1) IOUT(mA) (CR27 = 0) SYNC· BLANK* DAC Input Data 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 19.05 data + 1.44 data + 1.44 1.44 1.44 0 0 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: Typical with full-scale IOUT = 26.67 rnA. RSET = 523 7.5 IRE. 4 - 248 Blank pedestal = 7.5 IRE. RS-343A levels and Composite Video Output Waveform (SETUP Description SYNC LEva n. VREF = 1.235 V. Video Output Truth Table (SETUP SECTION 4 Blank pedestal = 7.5 IRE). Bt461/462 Circuit Description (continued) CR27=0 CRZ7=1 MA V MA \8.60 0.698 26.67 1.000 ..---......,..---------------,;;::----WHITI!U!VEL 0.00 0.000 8.0S 0.302 +-------I.-.,.---r-J--------- V BLACK/BLANX LEVEL 43 iRE ~ 0.00 0.000 _______ Note: 75 Q doubly terminated load, RSET tolerances assumed on all levels. Figure 4. ~-L _ _ _ _ _ _ _ _ _ _ SYNCLEVEL = 495 Q, VREF = 1.235 V. Blank pedestal = 0 IRE. RS-343A levels and Composite Video Output Waveform (SETUP o IRE). Description lOUT (rnA) (CR27 = 1) lOUT (rnA) (CR27 = 0) SYNC* BLANK* DAC Input Data WHITE DATA DATA-SYNC BlACK BLACK-SYNC BLANK SYNC 26.67 data + 8.05 data 8.05 0 8.05 0 18.60 data data 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: Typical with full-scale lOUT = 26.67 mAo RSET IRE. Table 5. = 495 Q VREF = 1.235 V. Video Output Truth Table (SETUP Blank pedestal = 0 o IRE). RAMDACs 4 - 249 .. Bt461/462 Internal Registers Command Register_O This register may be written to or read by the MPU at any time and is not initialized. CROO corresponds to data bus bit DO. CR07, CR06 Multiplex select (00) 3: 1 multiplexing (01) 4:1 multiplexing (10) reserved (11) 5: 1 mUltiplexing These bits specify whether 3:1, 4:1, or 5:1 multiplexing is to be used for the pixel and overlay inputs. If 3:1 is specified, the (D) and (E) pixel and overlay inputs are ignored and should be connected to GND, and the LD* input should be 1/3 the CLOCK rate. If 4: 1 is specified, the (E) pixel and overlay inputs are ignored and should be connected to GND, and the LD* input should be 1/4 the CLOCK rate. If 5:1 is specified, all of the pixel and overlay inputs are used, and the LD* input should be 1/5 the CLOCK rate. Note that it is possible to reset the pipeline delay of the Bt461!462 to a fixed eight clock cycles. In this instance, each time the input multiplexing is changed, the Bt461/462 must again be reset to a fixed pipeline delay. Note that 3:1 multiplexing may not be used at the 170 MHz pixel clock rate. CR05 Overlay 0 enable (0) use color palette RAMs (1) use overlay color 0 CR04 ALTenable (0) disable alternate palette (1) enable alternate palette CR03, CR02 Blink rate selection (00) 16 on, 48 (01) 16 on, 16 (10) 32 on, 32 (11) 64 on, 64 off (25m) off (50/50) off (50/50) off (50/50) CROI reserved (logical zero) CROO reserved (logical zero) 4 - 250 SECTION 4 When the overlay bits are $00, this bit specifies whether to use the color palette RAMs or overlay color o to provide color information. This bit specifies whether the alternate color palette RAM is enabled (logical one) or disabled (logical zero) from being addressed by the ALT (A-E) and PO-P7 (A-E) inputs. These 2 bits specify the blink rate cycle time and duty cycle, and are specified as the number of vertical retrace intervals. The numbers in parentheses specify the duty cycle (% on/off). Bt461/462 Internal Registers (continued) Command Register_1 This register may be written to or read by the MPU at any time and is not initialized. CR10 corresponds to data bus bit DO. CR17-CR15 (000) (001) (010) (011) (100) (101) (110) (111) CR14-CR10 (pixel A) (pixel B) (pixel C) These bits specify the number of pixels to be panned. The (pixel A) indicates pixel A will be output first following the blanking interval, (pixel B) indicates pixel B will be output first, etc. These bits are typically modified only during the vertical retrace interval. (pixel D) {pixel E) Note that the pixel, overlay, and ALT inputs are all panned. Pan select o pixels 1 pixel 2 pixels reserved 3 pixels 4 pixels reserved reserved .. reserved (logical zero) RAMDACs 4 - 251 Bt461/462 Internal Registers (continued) Command Register_2 This register may be written to or read by the MPU at any time and is not initialized. CR20 corresponds to data bus bit DO. CR27 Sync enable (0) disable sync (1) enable sync CR26 Pedestal enable (0) 0 IRE pedestal (1) 7.5 IRE pedestal CR25, CR24 Load palette RAM select (00) (01) (10) (11) CR23 normal redRAMDAC green RAMDAC blueRAMDAC PLL select (0) SYNC* (1) BLANK* CR22 This bit specifies whether a 0 or 7.5 IRE blanking pedestal is to be generated on the video waveform. 0 IRE specifies that the black and blank levels are the same. If (00) is specified, color data is loaded into the Bt461/462 each write cycle, and color data is output each read cycle. If (01), (10), or (11) is specified, the Bt461/462 expects color data to be input and output using (red, green, blue) cycles. The exact value indicates during which one of the three color cycles it is to load or output color information. This bit specifies whether the PLL output uses the SYNC* or BLANK* input for generating PLL information. Bt461-reserved (logical zero) This bit is always a logical zero on the Bt461. Bt462-Underlay enable (0) overlay plane 4 (1) underlay plane 0 On the Bt462, this bit specifies whether overlay plane 4 (OL4) should be converted to an underlay plane (logical one) or be used as a normal overlay plane (logical 0). CR21 reserved (logical zero) CR20 Test enable (0) disable test register (1) enable test register 4 • 252 This bit specifies whether sync information is to be output onto the video waveform (logical one) or not (logical zero). SECTION 4 A logical one enables the P9 (A-E) inputs to serve as a trigger for the test register. A logical zero enables normal operation. Bt461/462 Internal Registers (continued) ID Register This 8-bit register may be read by the MPU to determine the type of RAMOAC being used in the system. The value is different for each RAMOAC. For the Bt461/462, the value read by the MPU will be $40 for the Bt461 and $4C for the B t462. Oata written to this register is ignored. Pixel Read Mask Register The 16-bit pixel read mask register is configured as two 8-bit registers (pixel read mask low and pixel read mask high), and is used to enable (logical one) or disable (logical zero) a bit plane from addressing the color palette RAM. pixel read mask register high pixel read mask register low D7 D6 05 D4 D3 02 D1 DO D7 D6 05 D4 D3 02 D1 DO 0 0 0 0 0 0 P9 P8 P7 P6 P5 P4 P3 P2 PI PO Each register bit is logically ANDed with the corresponding bit plane input. This register may be written to or read by the MPU at any time and is not initialized. Pixel Blink Mask Register The 16-bit pixel blink mask register is configured as two 8-bit registers (pixel blink mask low and pixel blink mask high), and is used to enable (logical one) or disable (logical zero) a bit plane from blinking at the blink rate and duty cycle specified by command register_O. pixel blink mask register low pixel blink mask register high 07 D6 05 D4 D3 02 01 DO D7 D6 05 D4 D3 D2 D1 DO 0 0 0 0 0 0 P9 P8 P7 P6 P5 P4 P3 P2 PI PO In order for a bit plane to blink, the corresponding bit in the pixel read mask register must be a logical one. This register may be written to or read by the MPU at any time and is not initialized. RAMDACs 4 • 253 Bt461/462 Internal Registers (continued) Overlay Read Mask Register The 8-bit overlay read mask register is used to enable (logical one) or disable (logical zero) an overlay plane from addressing the overlay palette RAM. DO corresponds to overlay plane (OLO (A-ED and D4 corresponds to overlay plane 4 (OlA (A-ED. Each register bit is logically ANDed with the corresponding overlay plane input Bits D5-D7 are always a logical zero. This register may be written to or read by the MPU at any time and is not initialized. ° On the Bt462, the overlay read mask register for overlay plane 4 (OlA) must be a logical zero when using the underlay mode. Overlay Blink Mask Register The 8-bit overlay blink mask register is used to enable (logical one) or disable (logical zero) an overlay plane from blinking at the blink rate and duty cycle specified by command register_O. DO corresponds to overlay plane (OLO (A-ED and D4 corresponds to overlay plane 4 (OlA (A-ED. In order for an overlay plane to blink, the corresponding bit in the overlay read mask register must be a logical one. Bits D5-07 are always a logical zero. This register may be written to or read by the MPU at any time and is not initialized. ° Test Register The test register enables the MPU to verify that the pixel and overlay ports are addressing the color palette RAM and overlay registers correctly at full speed. P9 (A-E) is the fast port trigger when CR20 is a logical one. PO-P8 (A-E), ALT (A-E), and OLO-OlA (A-E) address the primary color palette RAM, alternate palette RAM, and overlay registers. A logical one on P9A latches the (A) color data into the test register as it is passed from the color palette to the O/A converter. A logical one on P9B latches the (B) color data into the test register as it is passed from the color palette to the D/A converter, etc. To test the entire color palette, bit D 1 in the pixel read mask register high (P9) must be a logical zero to test the lower 512 entries. Next, bit 01 in the pixel read mask register high (P9) must be a logical one to test the higher 512 entries. There should be only a single "one" on the P9 inputs per test read cycle. A recommended test read cycle is four LD'" cycles long. The test register may be written whenever the test mode is disabled or while in the test mode when no "ones" are present on the P9 inputs. The test registers are not initialized. 4 - 254 SECTION 4 Bt461/462 Pin Descriptions Pin Name Description BLANK* Composite blank control input (ITL compatible). A logical zero drives the analog output to the blanking level, as illustrated in Tables 4 and 5. It is latched on the rising edge of LD*. When BLANK* is a logical zero, the pixel and overlay inputs are ignored. SYNC* Composite sync control input (TTL compatible). A logical zero on this input typically switches off a 40 IRE current source on the lOUT output (see Figures 3 and 4). SYNC* does not override any other control or data input, as shown in Tables 4 and 5; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of LD*. LD* Load control input (TTL compatible). The PO-P9 (A-EJ, OLO..-OlA {A-EJ, BLANK*, and SYNC* inputs are latched on the rising edge of LD*. LD*, while it is either 1/3, 1/4, or 1/5 the CLOCK rate, may be phase-independent of the CLOCK and CLOCK* inputs. LD* may have any duty cycle, within the limits specified by the AC Characteristics section. PO-P9 (A-E) Pixel select inputs (TTL compatible). These inputs are used to specify, on a pixel basis, which location of the primary or alternate color palette RAMs is to be used to provide color information (see Table 2). Either three, four, or five consecutive pixels (up to 10 bits per pixel) are input through this port. They are latched on the rising edge of LD*. Unused inputs should be connected to GND. Note that typically the (A) pixel is output first, followed by the (B) pixel, etc., until all three, four, or five pixels have been output, at which point the cycle repeats. OW-OlA (A-E) Overlay select inputs (ITL compatible). These inputs are latched on the rising edge of LD*, and in conjunction with CR05 in command register_O, specify which palette is to be used for color information, as illustrated in Table 2. When accessing the overlay palette RAM, the PO-P9 (A-E) and ALT (A-E) inputs are ignored. Overlay information bits (up to 5 bits per pixel) for either three, four, or five consecutive pixels are input through this port. Unused inputs should be connected to GND. ALT(A-E) Palette select inputs (TTL compatible). These inputs are latched on the rising edge of LD* and specify which color palette RAM is to be used for color information, as illustrated in Table 2. When accessing the alternate color palette RAM, the P8-P9 (A-E) inputs are ignored. Unused inputs should be connected to GND. lOur Analog current output. This high-impedance current source is capable of directly driving a doubly terminated 75 Q coaxial cable (Figure 5). PiL Phase lock loop output current. This high-impedance current source is used to enable multiple Bt461/462s to be synchronized with sub-pixel resolution when used with an external PLL. A logical one on the SYNC* or BLANK* input (as specified by CR23 in command register_2) results io no current being output onto this pin, while a logical zero results in the following current being output: PLL (rnA) = 3,227 * VREF (V) I RSET (Q) If SUb-pixel synchronization of mUltiple devices is not required, this output should be connected to GND (either directly or through a resistor up to 150 Q). RAMDACs 4 - 255 Bt461/462 Pin Descriptions (continued) Pin Name Description VM Analog power. All VAA pins must be connected. GND Analog ground. All GND pins must be connected. CaMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 IlF ceramic capacitor must be connected between this pin and VAA (Figure 5). Connecting the capacitor to VAA rather than to GND provides the highest possible power supply noise rejection. The CaMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum and maximize the capacitor's self-resonant frequency to be greater than the LD* frequency. Refer to PC Board Layout Considerations for critical layout criteria. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal (Figure 5). Note that the IRE relationships in Figures 3 and 4 are maintained, regardless of the full-scale output current The relationship between RSET and the full-scale output current on lOUT for a 7.5 IRE blanking pedestal is: RSET (n) = 11,294 * VREF (V) I lOUT (rnA) The relationship between RSET and the full scale output current on lOUT for a 0 IRE blanking pedestal is: RSET (n) = 10,684 * VREF (V) I lOUT (rnA) VREF Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 5, must supply this input with a 1.235 V (typical) reference. The use of a resistor network to generate the reference is not recommended, as any low-frequency power supply noise on VREF will be directly coupled onto the analog outputs. A 0.1 IlF ceramic capacitor is used to decouple this input to V AA, as shown in Figure 5. If VAA is excessively noisy, better performance may be obtained by decoupling VREF to GND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. CLOCK, Clock inputs. These differential clock inputs are designed to be driven by ECL logic configured for single supply (+5 V) operation. The clock rate is typically the pixel clock rate of the system. CLOCK* CE* Chip enable control input (TIL compatible). This input must be a logical zero to enable data to be written to or read from the device. During write operations, data is internally latched on the rising edge of CE* (Figure 1). Care should be taken to avoid glitches on this edge-triggered input. R/W Read/write control input (TIL compatible). To write data to the device, both CE* and R/W must be a logical zero. To read data from the device, CE* must be a logical zero and R/W must be a logical one. R/W is latched on the falling edge of CE*. See Figure 1. CO, C1 Command control inputs (TIL compatible). CO and C1 specify the type of read or write operation being performed, as illustrated in Table 1. They are latched on the falling edge of CE*. DO--D7 Data bus (TIL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. 4 • 256 SECTION 4 BnxKtree~ Bt461/462 Pin Descriptions (continued)-132-pin PGA Package Signal Pin Signal Number BLANK· SYNC· Ll K3 Pin Signal Number P8A P8B P8C PSD PSE 014 013 FI4 FI3 EI4 II3 II4 HI2 HI3 HI4 VM VM VM VM VM VM lD* AS CLOCK KI CLOCK· K2 POA POB D2 POe DI POD POE E2 F3 P9A P9B P9C P9D P9E PIA PIB PIC PlD PIE Al D3 C2 BI CI ALTA ALlB ALTC ALID AL1E LI4 KI2 K13 KI4 II2 P2A A3 P2B P2C B3 P2D P2E C3 B2 OUlA OUlB Ol1lC OLOD OUlE EI F2 FI G3 G2 P3A P3B P3C P3D P3E AS OLlA OLlB OLlC OLlD OLlE MI 1.3 D4 M2 D5 M3 N2 PI P2 D7 E3 A2 A7 B7 A6 B6 L2 NI C9 B9 C8 B8 OL2A OL2B OL2C OL2D OL2E P5A P5B P5C P5D P5E B11 All CIO BIO AIO OL3A OL3B OL3C OL3D OL3E M4 P3 N4 P4 M5 P6A P6B P6C P6D P6E AI4 AI3 BI2 Cll AI2 OlAA N5 P5 M6 N6 P6 P7A P7B P7C P7D P7E E13 EI2 DI4 DI3 DI2 A9 OlAB oue OlAD OlAE lour reserved PI.L N3 PIO P11 NIO Jl 12 13 C6 FI2 M9 HI H2 GND GND GND GND GND GND C7 012 M8 COMP FSADJUST VREF N9 MIO P9 CE* P13 NI2 PI2 M11 R/W CI CO DO Dl D2 D3 D6 P4A P4B P4C P4D P4E Pin Number H3 L13 MI4 LI2 MI3 NI4 PI4 N13 MI2 reserved reserved reserved reserved reserved reserved reserved 01 N11 M7 reserved reserved reserved reserved reserved B5 C5 A4 B4 C4 reserved reserved reserved reserved reserved CI4 CI3 BI4 CI2 B13 RAMDACs N7 P7 P8 N8 4·257 Bt461/462 Pin Descriptions (continued)-132-pin PGA Package 14 DI 13 D6 12 Pm RiC NIC 11 !'SB PSo\ PID 10 PSE I'll) PSC P7B P7B VM GND P!IC ALTB AL11l 2 14 co N/C NIC FS ADI RL JOUr VM roM' VREP GND NIC NIC NIC NIC NIC GND I'D P3B VM 0lAC 100 MHz). The designer must take care to minimize skew on the CLOCK and CLOCK· lines. The PLL outputs would not be used and should be connected to GND (either directly or through a resistor up to 150 Q). PlL +5V }-----------~r_~a£CK 14 J-----------~I'<-...... a£CK. MONITOR Bt461/462 PRooucrs #1 91C1l Bt439 +5V +5V FROM Bt461/462 BT46I/462 B~39r #2 VAA T o. 50 1 VREP PlL eT@~ '~ a£CK a£CK· 330 LD· VRIlFI---' VAA Bt461/462 #3 TOl VREP Figure 7. 4 - 266 Generating the Bt4611462 Clock Signals (Color Application). SECTION 4 BnxKtreef> Bt461/462 Application Information (continued) Initializing the Bt4611462 (Monochrome) Following a power-on sequence, tlte Bt461/462 must be initialized. This sequence will configure the Bt461/462 as follows: 4:1 multiplexed operation no overlays no pixel masking, no blinking, no panning color data written/read every cycle sync enabled on lOUT, 7.5 IRE blanking pedestal COlltrol Register Illitializatioll Write $01 to address register low Write $02 to address register high Write $40 to command register_O Write $02 to address register low Write $00 to command register_1 Write $03 to address register low Write seo to command register_2 Write $04 to address register low Write $FF to pixel read mask low Write $05 to address register low Write $03 to pixel read mask high Write $06 to address register low Write $00 to pixel blink mask low Write $07 to address register low Write $00 to pixel blink mask high Write $08 to address register low Write $00 to overlay read mask Write $09 to address register low Write $00 to overlay blink mask Cl, CO 00 01 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 Overlay Color Palette Illitializatioll Write $00 to address register low Write $01 to address register high Write data to overlay (location $00) Write data to overlay (location $01) 00 01 10 10 Write data to overlay (location $1P) 10 Alterllate Color Palette Illitializatioll Write $00 to address register low Write $00 to address register high Write data to alternate (location $00) Write data to alternate (location $01) 00 01 10 10 Write data to alternate (location $FF) 10 Color Palette RAM Illitializatioll Write $00 to address register low Write $00 to address register high Write data to RAM (location $000) Write data to RAM (location $001) 00 01 11 11 Write data to RAM (location $3FF) 11 RAMDACs 4 - 267 Bt461/462 Application Information (continued) Initializing the Bt4611462 (Color) 8-bit MPU Data Bus Green Bt461/462 In this example. three Bt461/462s are being used in parallel to generate true color. An 8-bit MPU data bus is available for accessing the Bt461/462s. Note that while accessing the command, read mask. blink mask, control/test. and address register, each Bt461/462 must be accessed individually. While accessing the color palette RAM, alternate RAM. or overlay registers. all three Bt461/462s may be accessed simultaneously. Following a power-on sequence, the Bt461/462s must be initialized. This sequence will configure the Bt461/462s as follows: 4:1 multiplexed operation no overlays no blinking. no panning initialize each one as a red. green, or blue device sync on all outputs. 7.5 IRE blanking pedestal Control Register Initialization C1, CO Red Bt461/462 Write $01 to address register low Write $02 to address register high Write $40 to command register_O Write $02 to address register low Write $00 to command register_l Write $03 to address register low Write $00 to command register_2 Write $04 to address register low Write $FF to pixel read mask low Write $05 to address register low Write $03 to pixel read mask high Write $06 to address register low Write $00 to pixel blink mask low Write $07 to address register low Write $00 to pixel blink mask high Write $08 to address register low Write $00 to overlay read mask Write $09 to address register low Write $00 to overlay blink mask 4 - 268 SECTION 4 00 01 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 Write $01 to address register low Write $02 to address register high Write $40 to command register_O Write $02 to address register low Write $00 to command register_1 Write $03 to address register low Write $EO to command registec2 Write $04 to address register low Write $FF to pixel read mask low Write $05 to address register low Write $03 to pixel read mask high Write $06 to address register low Write $00 to pixel blink mask low Write $07 to address register low Write $00 to pixel blink mask high Write $08 to address register low Write $00 to overlay read mask Write $09 to address register low Write $00 to overlay blink mask 00 01 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 Blue Bt461/462 Write $01 to address register low Write $02 to address register high Write $40 to command register_O Write $02 to address register low Write $00 to command register_1 Write $03 to address register low Write $FO to command register_2 Write $04 to address register low Write $FF to pixel read mask low Write $05 to address register low Write $03 to pixel read mask high Write $06 to address register low Write $00 to pixel blink mask low Write $07 to address register low Write $00 to pixel blink mask high Write $08 to address register low Write $00 to overlay read mask Write $09 to address register low Write $00 to overlay blink mask 00 01 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 BllXKtree~ Bt461/462 Application Information (continued) Color Palette RAM Initialization Ollerlay Color Palette Initialization Write $00 to all three address low registers 00 Write $00 to all three address high registers 01 Write red data to RAM (location $000) 11 Write green data to RAM (location $000) 11 Write blue data to RAM (location $000) 11 Write red data to RAM (location $001) 11 Write green data to RAM (location $001) 11 Write blue data to RAM (location $001) 11 Write $00 to all three address low registers Write $01 to all three address high registers Write red data to overlay (location $00) Write green data to overlay (location $00) Write blue data to overlay (location $00) Write red data to overlay (location $01) Write green data to overlay (location $01) Write blue data to overlay (location $01) 00 00 10 10 10 10 10 10 Write red data to RAM (location $3FF) Write green data to RAM (location $3FF) Write blue data to RAM (location $3FF) Write red data to overlay (location $1P) Write green data to overlay (location $lF) Write blue data to overlay (location $lF) 10 10 10 11 11 11 Alternate Color Palette Initialiution ESD and Latchup Considerations Write $00 to all three address low registers 00 Write $00 to all three address high registers 01 Write red data to alternate (location $00) 10 Write green data to alternate (location $00) 10 Write blue data to alternate (location $00) 10 Write red data to alternate (location $01) 10 Write green data to alternate (location $01) 10 Write blue data to alternate (location $01) 10 Write red data to alternate (location $FF) Write green data to alternate (location $FF) Write blue data to alternate (location $FF) 10 10 10 Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. Latchup can be prevented by assuring that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than -Hl.S V. RAMDACs 4 - 269 .. Bt461/462 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage FS ADJUST Resistor Symbol Min Typ Max Units VAA TA RL VREF 4.75 0 5.00 5.25 +70 Volts °C OJuns Volts OJuns 1.20 37.5 1.235 523 1.26 Min Typ Max Units 6.5 Volts VAA+0.5 Volts +125 +150 °C °C TI +150 +175 °C °C TSCL 260 °C TVSOL 220 °C RSET Absolute Maximum Ratings Parameter Symbol VAA (measured to GND) Voltage on Any Signal Pin. Analog Output Short Circuit Duration to Any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature FGA PQFP Soldering Temperature (5 seconds, 1/4" from pin) Vapor Phase Soldering (1 minute) AirFlow FGA GND-O.5 indefinite ISC TA 'IS TJ -55 -65 TJ 0 50 PQFP 1.f.p.m. 1.f.p.m. Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. • This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. 4 ·270 SECTION 4 Bt461/462 DC Characteristics Parameter lOUT Analog Output Resolution Accuracy Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs (except CLOCK, CLOCK·) Input High Voltage Input Low Voltage Input High Current (Vin = 2.4V) Input Low Current (Vin =0.4V) Input Capacitance (f = 1 MHz, Yin =2.4V) Clock Inputs (CLOCK, CLOCK·) Differential Input Voltage Input High Current (Vin =4.0V) Input Low Current (Vin =0.4V) Input Capacitance (f = 1 MHz, Yin =4.0V) Digital Outputs (00-07) Output High Voltage (lOH =-400 ItA) Output Low Voltage (lOL =3.2 rnA) 3-state Current Output Capacitance Symbol Min Typ Max Units 8 8 8 Bits ±l ±1 ±5 LSB LSB % Gray Scale IL IL guaranteed Binary vrn VIL Volts Volts 4 VAA + 0.5 0.8 1 -1 10 4 6 1 -1 10 Volts ~ ~ pF 2.0 GND-O.5 llH IlL CIN AVlN .6 IKIH lKIL CKIN VOO .. pF Volts 2.4 VOL Ial coour ~ ~ 0.4 Volts 10 ~ pF 10 See test conditions on next page. RAMDACs 4·271 Bt461/462 DC Characteristics (continued) Parameter lOUT Analog Output Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank SETUP = 7.5 IRE SETUP = oIRE Blank Level Sync Level LSBSize Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 mA) Symbol Min Typ Max Units 17.69 16.74 19.05 17.62 20.40 18.50 mA mA 0.95 0 6.29 0 1.44 5 7.62 5 69.1 1.90 50 8.96 50 mA +1.2 Volts kn pF lOur VOC RAOUf CAOUf PLL Analog Output Output Current SYNC*/BLANK* = 0 SYNC*/BLANK* = 1 Output Compliance Output Impedance Output Capacitance (f= 1 MHz, PLL= OmA) PIL Voltage Reference Input Current Power Supply Rejection Ratio (COMP = 0.1 JJF, f = 1 KHz) -1.0 50 13 6.00 0 -1.0 7.62 5 20 9.00 50 +2.5 IIA mA IIA IIA mA IIA 50 15 Volts kn pF IREF 10 IIA PSRR 0.5 %/%AVAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 n, VREF = 1.235 V. SETUP = 7.5 IRE. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 4-272 SECTION 4 Bt461/462 AC Characteristics 135 MHz Devices 170 MHz Devices Parameter Clock Rate ill* Rate Symbol Min Typ Max Min Typ 170 42.5 Fmax LDmax Max Units 135 45 MHz MHz RIW. CO. C1 Setup Time R/W. CO. C1 Hold Time 1 2 0 15 0 15 ns ns CE*LowTime CE* High Time CE* Asserted to Data Bus Driven CE* Asserted to Data Valid CE* Negated to Data Bus 3-Stated 3 4 5 6 7 60 25 7 60 25 7 ns ns ns ns ns Write Data Setup Time Write Data Hold Time 8 9 35 0 35 0 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 10 11 3 2 3 2 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time 12 13 14 5.88 2.6 2.6 7.4 3.2 3.2 ns ns ns LD* Cycle Time LD* Pulse Width High Time LD* Pulse Width Low Time 15 16 23.5 8 8 22.2 8 8 ns ns ns Analog Output Delay Bt461 Bt462 Analog Output Rise!Fall Time Analog Output Settling Time Clock and Data Feedthrough* Glitch Impulse* 18 17 11 5 2 11 5 2 19 20 8 6 tbd 50 Pipeline Delay Bt461 Bt462 VAA Supply Current** Bt461 Bt462 75 15 75 15 6 8 tbd 50 10 12 6 8 ns ns ns ns dB pV - sec 10 12 Clocks Clocks 445 355 rnA rnA IAA 350 295 470 380 330 270 See test conditions on next page. RAMDACs 4 ·273 .. Bt461/462 AC Characteristics (continued) 110 MHz Devices Symbol Parameter Clock Rate LD* Rate Min Typ Fmax LOmax 80 MHz Devices Max Min Typ 110 36.7 Max Units 80 26.7 MHz MHz RIW, CO, Cl Setup Time RIW, CO, Cl Hold Time 1 2 0 15 0 15 ns ns CE*LowTime CE* High Time CE'" Asserted to Data Bus Driven CE* Asserted to Data Valid CE* Negated to Data Bus 3-Stated 3 4 5 6 7 60 25 7 60 25 7 ns ns ns ns ns Write Data Setup Time Write Data Hold T'tme 8 9 35 0 50 0 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 10 11 3 2 4 2 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time 12 13 14 9.09 4 4 12.5 5 5 ns ns ns LD'" Cycle Time LD* Pulse Width High Time LD* Pulse Width Low Time 15 16 17 27.27 10 10 37.5 12 12 ns ns ns Analog Output Delay Bt461 Bt462 Analog Output Rise/Fall Time Analog Output Settling Time Clock and Data Feedthrough'" Glitch Impulse'" 18 100 15 11 5 2 19 20 11 5 3 12 8 tbd 50 Pipeline Delay Bt461 Bt462 tbd 50 10 12 6 8 6 8 ns ns ns ns dB pV - sec 10 12 Clocks Clocks 410 320 rnA rnA 1M VAA Supply Current** Bt461 Bt462 320 255 See test conditions on next page. 4·274 75 15 SECTION 4 430 340 300 235 Bt461/462 AC Characteristics (continued) Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 n, VREF = 1.235 V. TTL input values are 0-3 V, with input rise/fall times :5 4 ns, measured between the 10% and 90% points. ECL input values are VAA-O.S to VAA-1.S V, with input rise/fall times :5 2 ns, measured between the 20% and SO% points. Timing reference points at 50% for inputs and outputs. Analog output load :5 10 pF, DO-D7 output load :5 75 pF. See timing notes in Figure S. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the TTL digital inputs have a 1 ill resistor to GND and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 2x clock rate. ** At Fmax. IAA (typ) at V AA = 5.0 V, TA = 20° C. IAA (max) at VAA = 5.25 V, TA = 0° C. .. Timing Waveforms 15 16 17 LD' po.P7 (A·E), ALT (A·E) OLO·OlA (A· E), DATA SYNC*, BLANK- 10 18 11 20 101IT. PIL 19 12 a.OCK 14 Note 1: Output delay time measured from 50% point of the rising clock edge to 50% point of fullscale transition. Note 2: Output settling time measured from 50% point of full-scale transition to output settling within ±I LSB. Note 3: Output rise/fall time measured between 10% and 90% points of full-scale transition. Figure 8. Video Input/Output Timing. RAMDACs 4 • 275 Bt461/462 Timing Waveforms (continued) L RIW. co. 1 -2.-. VALID CI 3 (]!. 4 I 6 s I V DO - D7 (READ) } ...... DATA OIIT (R/W = I) R DATA IN (RJW = 0) DO - D7 (WRITI!) 8 r-!Figure 9. MPU Read/Write Timing Dimensions. Revision History Datasheet Revision 4 • 276 Change from Previous Revision F Added Bt462 functionality, corrected Tables 1 and 2. G Added 132-pin PQFP package, expanded PCB layout section. Adjusted 170 MHz clock low and clock high times, power supply current on all speed grades, and AC parameters 3, 5, and 18. H Revised Application Information. Removed Input High and Low Voltage parameters and added Differential Input Voltage to DC Characteristics_ SECTION 4 Bt461/462 Ordering Information Ambient Temperature Range Model Number Speed Package Bt461KG170 170 MHz 132-pin Ceramic PGA D· to +70· C Bt461KG135 135 MHz 132-pin Ceramic PGA O· to +70· C Bt461KGllO 110 MHz 132-pin Ceramic PGA D· to +70· C Bt461KG80 80 MHz 132-pin Ceramic PGA D· to +70· C Bt462KG170 170 MHz 132-pin Ceramic PGA O· to +70· C Bt462KG135 135 MHz 132-pin Ceramic PGA O· to +70· C Bt462KG110 110 MHz 132-pin Ceramic PGA O· to +70· C Bt462KG80 80 MHz 132-pin Ceramic PGA O· to +70· C Bt462KPF170 170 MHz 13 2-pin P]as tic Quad Flatpack O· to +70· C Bt462KPF135 135 MHz 132-pin Plastic Quad Flatpack O· to +70· C Bt462KPFllO 110 MHz 132-pin Plastic Quad Flatpack D· to +70· C Bt462KPF80 80 MHz 132-pin Plas tic Quad Flatpack D· to +70· C RAMDACs - 4 • 277 Advance Information This document contains information on a product under development. The parametric and functional information are target parameters and are subject to change without notice. Please consult Brooktree regarding the most updated datasheet before design. Distinguishing Features Applications • • • • • • • • • • • • • • High Resolution Color Graphics • Medical Imaging • Visualization • CAE/CAD/CAM • Image Processing • Video Reconstruction 170, 135, 110 MHz Operation Multiple Display Modes on a Pixel Basis Multiple Color Maps Variable Palette Sizes Up to 8 Overlay Planes Reconfigurable Pixel Port 1:1,2:1 or 4:1 Multiplexed Pixel Ports Three 528 x 8 Color Palette RAMs Programmable Setup (0 or 7.5 IRE) X Windows Support Input and Output Signature Registers ITAG Support 169-pin PGA Package Related Products CLOCK VAA 170 MHz Monolithic CMOS TrueVu™ RAMDAC'M Product Description The Bt463 is a high performance RAMDAC . . designed specifically for true color and pseudo color graphics addressing multiple lookup tables for different windows. It has three 528 x 8 look-up tables with triple 8-bit D/A converters to support 24-bit true color and 9-bit pseudo color operation. • Bt431, Bt438 Functional Block Diagram CLOCK' 8t463 TM GND PS ADJUST VRI!P COMP ill' JOR JOG JOB WTO-WT3 (A-D) SYNC· The TrueVu RAMDAC allows different display modes of operation for each pixel. Utilizing a proprietary windo,w type scheme, each set of pixel and overlay data has four type bits which map the accompanying pixel data to a user-defined display mode. The type bits address a window type table which ultimately determines the description of the pixel data. With this scheme, arbitrary plane depth and unique visual display type can be achieved on a pixel basis. For example, separate windows displaying 24-plane true color, 8-plane pseudo color, and 12-plane double-buffer true color, each with a separate color map, can exist within a single frame. The size of each individual lookup table is user-configurable and can vary from 16 to 512 addresses. BLANK' rna R/W CO Cl TMS TCK IDJ TDO (ITAG) Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580 • (800) VIDEO IC TLX: 383596. FAX: (619) 452-1249 lA6300l Rev. B 4- 279 On-chip features include programmable 1:1, 2:1, or 4: 1 input mUltiplexing of the pixels, bit plane masking, and a programmable setup (0 or 7.5 IRE). The Bt463 has significant testability features, including input and output signature analysis registers, and fully supports the ITAG specification. Bt463 Architecture Introduction Overview With X Windows becoming the de facto standard, the need for each window to have its unique color map and display type becomes apparent. Each window should be able to use its own private color map and define its own interpretation of pixel values in the frame buffer using a variety of possible visual types. In addition, since each window is completely independent of other windows, the hardware must be able to accommodate mUltiple visual types within a single frame of graphics display. Thus, the ability to switch to different color maps and visual types on a pixel-by-pixel basis is essential. The Bt463 has been designed specifically to address multiple windows and display types. The Bt463 is extremely flexible, permitting multiple visual types to be displayed simultaneously and efficiently supporting mUltiple virtual color maps within the physical color map. Window type data is sent to the TrueVu RAMDAC along with each pixel. The window type addresses a 16 x 24 window type table, which converts pixels from a virtual color map index to a physical color map index prior to sending them to the lookup table. In addition to specifying the physical color map location and display type, the window type table can determine the number of planes, location of the frame buffer data, location of overlay data, and select specific overlay planes for each window. TM Even though the Bt463 has 24-plane true color capability, the assignment of red, green, and blue pins is not fixed to preassigned locations. The B t463 is flexible, allowing pixel or overlay data to be in practically any location of the 28-bit pixeVoverlay word and be shifted into position to address the lookup table. With this flexibility, the Bt463 can be configured in a variety of ways. A number of possible configurations are listed in Table 1. Pixel Pin Location Mapped Function PO-P7 P8-P15 Pl6-P23 P24-P27 RO-R7 GO-G7 BO-B7 OLO-OI.3 24-bit true color 4-plane overlay PO-P8 P24-P27 PO-P8 OLO-OI.3 9-bit pseudo color 4-plane overlay P8-P15 Pl6-P19 PO-P7 OLO-OI.3 8-bit pseudo color 4-plane overlay PO-P7 P8-P15 PI6-P23 P24-P27, WTO-WTI RO-R7 GO-G7 BO-B7 OLO-OL7 24-bit true color 8-plane overlay P4-P7 P12-P15 P20-P23 P24-P27 RO-R3 GO-G3 BO-B3 OLO-OI.3 12-bit true color 4-plane overlay PI-P7 P9-P15 Pl8--P23 P16, P8, PO, P17 RI-R7 Gl-G7 B2-B7 OLO, OLl, OL2, OL3 24-bit true color 4-plane overlay Display Mode Table 1. Example Pixel/Overlay Configurations and Display Modes. 4- 280 SECTION 4 Bt463 Circuit Description MPU Interface Writing/Reading Window Type Table As illustrated in the functional block diagram, the Bt463 supports a standard MPU bus interface, allowing the MPU direct access to the internal control registers, window type table, and color palettes. The dual-port color palette RAMs allow color updating without contention with the display refresh process. To write the window type table, the MPU writes the address register with the table location to be modified. The MPU performs three successive write cycles (BO-B7, B8-B15, then BI6-B23) with BO being the least significant bit, using CO and Cl to select the window type table. BO, B8, and B16 correspond to data bus bit DO. After the third write cycle, the three bytes of the table entry are concatenated into a 24-bit word and written to the window type table address specified by the address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of three bytes to the window type table. To avoid irregular window displays on the screen, MPU accesses to the window type table are restricted to horizontal and vertical retrace periods. As illustrated in Table 2, the CO and Cl control inputs, in conjunction with the internal address register, specify which control register or color palette location will be accessed by the MPU. The 12-bit address register eliminates the requirement for external address multiplexers. ADDRO is the least significant bit. ADDRO and ADDR8 correspond to data bus bit DO. ADDRI2-ADDRI5 are ignored during MPU write cycles and return a logical zero when read by the MPU. The control registers and window type table are also accessed through the address register in conjunction with the CO and Cl inputs, as shown in Table 2. All control registers may be written to or read by the MPU at any time. When accessing the control registers, window type table and the color palette RAM, the address register increments following a read or write cycle. Writing/Reading Color Palette RAM To write color data, the MPU loads the address register with the address of the color palette RAM or cursor color register to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using CO and Cl to select the color palette RAM or cursor color register. After the blue write cycle, the address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. To read the color palette RAM or cursor color register, the MPU loads the address register with the address of the color palette RAM location or cursor color register to be read. Reading color data is similar to writing, except the MPU executes read cycles. When accessing the cursor color registers, the address register increments to $0102 following a blue read or write cycle. The color palette RAM does not have a wraparound feature after the last valid address. However, any attempt to write past $020F does not affect previous data load cycles. The address register will reset to $0000 after incrementing past $OFFF. ADDRO-16 Cl,CO Addressed by MPU $xxxx $xxxx 00 01 address register (ADDR0-7) address register (ADDR8-11) $0100 $0101 10 10 cursor color 0* cursor color 1* $0200 $0201 $0202 $0203 $0205 $0206 $0207 $0208 $0209 $020A $020B $02OC $020D $020E $020F 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 ID register ($2A) command register_O command register_l command register_2 PO-P7 read mask register P8-PI5 read mask register PI6-P23 read mask register P24-P27 read mask register PO-P7 blink mask register P8-P15 blink mask register PI6-P23 blink mask register P24-P27 blink mask register test register input signature register** output signature register* $0220 10 revision register ($A) $0300-$030F 10 window type table* $0000-$020F 11 color palette RAM* *Indicates requires three read/write cycles ** Indicates 2 out of 3 valid read/write cycles Table 2. Address Register (ADDR) Operation. RAMDACs 4·281 .. Bt463 Circuit Description (continued) To read the window type table data, the MPU loads the address register with the address of the type table to be read. Contents of the type table are copied into a 24-bit register and the address register is incremented to the next window type table entry. The MPU performs three successive read cycles (BO-B7, B8-BI5, then BI6-B23) with BO being the least significant bit, using CO and Cl to select the window type table. BO, B8, and B16 correspond to data bus bit DO. the address register has two additional bits (ADDRa, ADDRb) that count modulo three. They are reset to zero when the MPU reads or writes to the address register. The MPU does not have access to these bits. The other 12 bits of the address register (ADDRO-ll) are accessible to the MPU. Note that if an invalid address is loaded into the address register, data written to the device will be ignored and invalid data will be read by the MPU. Additional In/ormation When accessing the color palette RAM, window type table, signature analysis registers, or cursor color registers, the address register increments after every third read/write cycle for each addressable location. To keep track of the red, green. and blue read/write cycles, =:x RtW.m.e! VMID For 8-bit registers, the address increments after every read/write cycle. Figure 1 illustrates the MPU read/write timing of the Bt463. )(~________________________________ / \ DO· JY/ (READ) DO· JY/ (W1Ul1I) ----------« ____________,J)( DATAOIIT(RfW=l) DATAIN(RfW.O) Figure I. MPU ReadiWrite Timing. 4-282 SECTION 4 )>------ x'--____ Bt463 Circuit Description (continued) FralTUl Buffer Interface To enable pixel data to be transferred from the frame buffer at TTL data rates, the Bt463 incorporates internal latches and mUltiplexers. As illustrated in Figure 2, on the rising edge of LD*, sync and blank information, color, window type, and overlay information, for either one, two, or four consecutive pixels, are latched into the device. Note that with this configuration. the sync and blank timing will be recognized only with one, two, Of four pixel resolution. Typically, the LD* signal is used to clock external circuitry to generate the basic video timing and to clock the video DRAMs. For 1:1, 2:1, or 4:1 input mUltiplexing, the Bt463 outputs color information each clock cycle based on the {Al inputs, followed by the {Bl inputs, etc., until one, two, or four pixels have been output, at which point the cycle repeats. To simplify the frame buffer interface timing, LD* may be phase-shifted, in any amount, relative to CLOCK. This enables the LD* signal to be derived by externally dividing CLOCK by two or four, independent of the propagation delays of the LD* generation logic. As a result, the pixel and overlay data are latched on the rising edge of LD*, independent of the clock phase. Internal logic maintains an internal LOAD signal, synchronous to CLOCK, and is guaranteed to follow the LD* signal by at least one, but not more than three, clock cycles. This LOAD signal transfers the latched pixel and overlay data into a second set of latches, which are then internally multiplexed at the pixel clock rate. If 1: 1 multiplexing is specified, the CLOCK and CLOCK* signals are ignored and pixel data is latched on the rising edge of LD*. If 2: 1 multiplexing is specified, only one rising edge of LD* should occur every two clock cycles. If 4:1 multiplexing is specified, only one rising edge of LD* should occur every four clock cycles. Otherwise, the internal LOAD generation circuitry assumes it is not locked onto the LD* signal, and will continuously attempt to resynchronize itself to LD*. Color Palette RAM The color lookup table consists of three independent RAMs with variable size color maps. Multiple color maps can be assigned within each of the three 528 x 8 lookup tables with the minimum color map size being 16 colors. The color map can be as large as 512 colors. Color generated by pixel or overlay data is independent of the absolute physical address of the lookup table. Pixel, overlay, and underlay data is referenced relative to its own color map. The start address indicating the beginning of each physical color map is added to the W' PO-PZ7 {A-D} wro-WTI {A-D}. SYNC·. BLANK'" (OlIT CLOCK Figure 2. Video Input/Output Timing. RAMDACs 4·283 .. Bt463 Circuit Description (continued) pixel data to generate the address for the final color. The start address is specified through the window type table. number of planes, window display type, start address of the physical color map, shift constant, overlay location, and bypass operation. Multiple windows utilizing the same configuration mode can address the same entry of the window type table, as illustrated in Figure 3. It is recommended that the window type table be loaded by the MPU during vertical retrace to miuimize disruptions during the display process. Window Type Table Window type data is sent to the RAMDAC along with each pixel. The window type addresses a 16 x 24 window type table selecting one of sixteen 24-bit The window type word window type words. reconfigures the mapping of the input pixels to the RAMDAC, pixel by pixel. Each color map requires a pointing index to convert pixels from a virtual color map index to a physical color map index. In addition to specifying the physical color map location and display type, the window type table can determine the number of planes, location of the frame buffer data, and location of overlay data, and can select specific overlay planes for each window. The window type table provides the capability to switch back and forth between different display modes and individual color maps on a pixel-by-pixel basis. For example, the Bt463 can switch from 24-plane true color to 12-plane true color to 8-plane pseudo color, all within a single frame of graphic data. This allows users to personalize color maps specific to individual windows. Users have the option of designating the 15th and 16th codes of the window type table to be used as a cursor. These two window type codes directly address the cursor palette, bypassing all pixel manipUlation operations. This feature eliminates the need to use the overlay ports as an interface to a hardware cursor. Window type $E is defmed as cursor color 0 and $F is cursor color 1. Even though the Bt463 has 24-plane true color capability, the assignment of red, green, and blue pins is not fixed to preassigned locations. The Bt463 is flexible, providing capabilities to have pixel or overlay data in practically any location of the 28-bit pixel/overlay word. The pixels are sbifted into position where they address the lookup table. With this flexibility, the Bt463 can be configured in a variety of ways, such as those listed in Table 1. The window type table words consist of 7 different fields which map the function of the accompanying pixel data. The 7 fields, shown in Figure 4 are: shift, number of planes, display mode, overlay location, overlay mask, start address and lookup table bypass. These fields are described in detail in the following sections. Associated with each set of pixel data is a 4-bit window type word (WTO-WT3). The window type addresses one of 16 possible entries of the window type table. Each 24-bit window type entry is associated with a particular configuration mode which specifies the I Window Type Entry #1 ColonnapA I ~ Wrndow Type Entry #4 ColonnapB Window Type Entry #4 ColonnapB Wmdow Type Entry #9 ColonnapB I I Wrndow Type Entry #7 ColonnapC I Window Type Entry #1 ColonnapA Figure 3. Multiple Windows Utilizing Different Color Maps. 4-284 SECTION 4 Bt463 Circuit Description (continued) Window Type Table Fields Overlay Mask <816:B13> Shift <84:80> This field specifies the plane position where active planes begin. If the active planes are in higher order bits, the shift field can shift these bits into the least significant position which will address the RAM. For instance, a value of 8 specifies active planes to begin at position P8. This field is particularly useful for double buffer applications. The shift value applies to the entire 28-bit pixeVoveriay input. Legal values are 0 through 27. However, the number of planes plus the shift value should not exceed 28 within one window type table entry. The overlay mask field is used to enable (logical one) or disable Oogical zero) an overlay plane from addressing the overlay palette. B 13 corresponds to OLO. B 13-B 16 are logically ANDed with the corresponding overlay plane input. The selected overlay planes are then compacted into the LSB positions with the higher significant bits filled with zeroes. This feature allows the user to assign specific overlay planes to individual windows. Two or more separate overlay images can be generated independently and switched on a pixel-by-pixel basis using the same or different overlay palette. Number of Planes <88:85> Start Address <822:817> This field determines the number of active planes used for pixel data. Zeros will be inserted in bit planes above the specified MSB. For true color modes, the appropriate value in this field corresponds to the number of planes per channel. For instance, a 24-plane true color window should specify 8 as the number of planes. Legal values for this field are 0 through 8 for true color and 0 through 9 for pseudo color windows. Zero planes correspond to the color at the start address location regardless of pixel data, dependent on overlay and cursor data. This is useful for generating background color or flood color while the window is being changed or moved. The number of planes plus the shift value should not exceed 28 for the pseudo color mode. The number of planes times 3 plus the shift value shound not exceed 28 for the true color mode. The start address specifies the beginning of the physical address of each individual color map. Pixel data addresses the lookup table independently of the absolute physical location of the color map. The start address constitutes the 6 MSBs of the start rows of the color maps. Color address is generated by adding the pixel data with the start address in the physical color map. The maximum valid physical address resulting from this addition is $020F. Color maps start on 16 row boundaries and are allocated in blocks of 16. Thus a binary value of 000001 corresponds to the physical address location of $0010. It is not necessary to fill the entire block with color map colors. The resultant value from pixel data plus the start address should not exceed the 528 address space of the lookup table. Various color maps can be disjoint, overlapping or subsets of other color maps. Minimum color map size is 16 while the maximum contiguous color map size is 512 colors. Legal values are 000000 through 100000. Display Mode <811:89> This field determines the display mode of the pixel data. Valid display options are true color, pseudo color, bank select, 12-plane double buffer true color and pseudo color with load interleave. Refer to Table 3 for full display mode descriptions. Overlay Location <812> The overlay location field specifies the source location of the overlay planes. A logic zero specifies overlay data to come from P<27:24>. The overlay location is fixed to these four pixel locations, unaffected by any shift in the shift fields. A logic one in this field specifies overlay data to come from the least significant bits of the pixel data (true color mode) or the four planes above the pixel planes (pseudo color mode). The overlay locations for the true color mode are P<17, 0, 8, 16>, with P16 being the LSB of the overlay word. The overlay location is affected by the shift value and only utilizes these variable locations after the shift operation has been completed. Lookup Table Bypass Up to 24 bits of pixel information are input via PO-P27 inputs. Even in the bypass mode, pixel manipUlation still occurs with the 8 lowest significant bits used for each DAC. After shifting, pixels which are positioned in the LSB positions, PO-P7, are mapped as RO-R7, bypass the red color palette, and drive the red DAC directly. Similarly, P8-P15 pixels are mapped as GO-G7 and drive the green DAC directly. Pl6-P23 are mapped as BO-B7 and drive the blue DAC directly. The bypass mode can only be used in the 8-plane mode. With the display mode set to pseudo color, the bypass bit will generate 256 shades of gray scale. Eight bits of color information are applied equally to each of the three DACs. In the bypass mode, overlays are still effective in either the 4- or 8-plane mode and address the overlay palette. RAMDACs 4 - 285 Bt463 Circuit Description (continued) Start Address Figure 4. Window Type Table Fields. Display Mode Field Description True Color 000 An equal number of red, green, and blue pixel planes are input via the pixel porl The number of bits of true color is dependent on the "number of planes" field in the window type table. Eventually, pixel data must be shifted so that the least significant bit of the red pixel word is PO, green is P8, and blue is P16. Number of planes per channel is 0 to 8 for this mode. Correspondingly, the number of planes for the pixel data is three times the value in this field for true color. For example, a value of 8 in the plane field yields 24-plane true color. A value of 4 in the plane field yields a 12-plane true-color configuration. Pseudo Color 001 All three color palette RAMs are addressed by the same planes of pixel data. Pixel data for the pseudo color must come from a contiguous set of planes. Maximum number of active planes is nine for the pseudo color mode. Number of available planes range from 0 to 9. Bank Select 01 0 Overlay bits are concatenated as the MSBs to the pixel data to address a different portion of the lookup table without changing pixel data. Bank select is especially useful for highlighting or color contrasting by changing overlay inputs instead of regenerating the frame buffer image. Number of planes per channel is 0 to 8. Planes used for bank select are also dependent on the overlay mask. Refer to Figure 5 for more details on the bank select mode. 011 Reserved Twelve Plane True Color (Load Interleave) See Figure 6. 100 Twelve plane true color is generated by utilizing the lower or upper nibble (4 bits) from 8 bits each of red, green, and blue. Either the upper or lower nibbles are latched on each load clock across a scan line depending on the value of the shift field immediately after blank has been substantiated. The load cycle will begin with the lower nibble for a shift value of $00. If the shift value is $04 immediately after blank, the load cycle will begin with the upper nibble. The output sequence continues to alternate between lower nibble and upper nibble for each load sequence throughout the entire scan line. This display mode preassigns the mapped function for the pixel inputs. PO-P7 is red, P8-PI5 is green, and PI6-P23 is blue. Refer to Table 4 for more details. Pseudo Color (Load Interleave) See Figure 6. 101 Eight plane pseudo color data is generated from either the lower nibble bits or upper nibble bits of red and green pixel data. The green nibble bits are concatenated with the red nibble bits to generate the 8 bit pseudo color pixel word. The red nibble comprise the least significant bits. Either the upper or lower nibbles are latched on each load clock across a scan line depending on the value of the shift field immediately after blank has been substantiated. The load cycle will begin with the lower nibble for a shift value of $00. If the shift value is $04 immediately after blank, the load cycle will begin with the upper nibble. The output sequence continues to alternate between lower nibble and upper nibble for each load sequence throughout the entire scan line. Refer to Table 5 for more details. 11 0 Reserved 111 Reserved Table 3. Display Mode Options. 4 - 286 SECTION 4 Bt463 Circuit Description (continued) $0000 , . . - - - - - - - - , $0000 Start Address (Bank Select = 00(0) ----t-------cOl'Oio-------- Start Address (Bank Select = 00(0) ----+---------;;~;~-~-------- Color! Color I Color 2 Color 14 Bank Select = 0001 Color IS ----t-------C,;r;;;.-ii-------Color 1 Color 253 Color 254 Color 255 Color 14 _______£QlQt1.L_____ _ Bank Select = OOO! ---.j.-----------------------Co!orO Color I Co!or2 Bank Select =0011 ---+-------'2&.;;0-------Color! _______Color!4_______ _ Cslku:.l~ $020F $020F L..-_ _ _ _ _--' Number of Planes =4 Color 253 Color 254 Color 255 L -_ _ _ _ _- ' Number of Planes =8 Figure 5. Color Map Allocation using Bank Select. Pixel Location Mapped Function Pixel Word 12-bit True Color Lower Nibble PO-P7 P8-P15 Pl6--P23 RO-R7 GO-G7 BO-B7 RO-R3 GO-G3 BO-B3 Lower Nibble Output Sequence ALBLCLDL Pixel Word 12-bit True Color Upper Nibble R4-R7 G4-G7 B4--B7 Upper Nibble Output Sequence AHBHCHDH Table 4. 12-Bit True Color (Load Interleave) Mapping and Output Sequence. Pixel Location Mapped Function PO-P7 P8-P15 Pl6--P23 RO-R7 GO-G7 BO-B7 Pixel Word 8-bit Pseudo Color Lower Nibble Lower Nibble Output Sequence Pixel Word 8-bit Pseudo Color Upper Nibble Upper Nibble Output Sequence GO-G3, RO-R3 ALBLCLDL G4-G7, R4--R7 AHBHCHDH Table 5. 8-Bit Pseudo Color (Load Interleave) Mapping and Output Sequence. RAMDACs 4 - 287 Bt463 Circuit Description (continued) BLAN K"--.J I- load cycle -t-.... load - I - cycle -+- -+load cycle odd load cycle ..-J-.. - I- load - J cycle - I odd ALBLCLDr. AHBHCH~ ALBLCLDr. AHBH ALBLCLDr. AHBHCH~ ALBLCLDr. AHBH ALBLCLDr. AHBHCH~ ALBLCLDr. AHBH ~LDr. AHBHCH~ ALBLCL : : (Shift = $00) : AHBHCH~ ALBLCLDr. AHBHCH~ ALBLCLDr.AHBHCHDH ALBLCL : (Shift = $04) : IBLCLDr. AHBHCHDH ALBLCLDL IBLcLDr. AHBHCHDH ALBLCLDL : : (Shift = $00) Figure 6. Load Interleave Output Sequence. Video Generation Every clock cycle, the color infonnation (up to 24 bits) is presented to the three 8-bit 0/A converters. The SYNC· and BLANK* inputs, pipelined to maintain synchronization with the pixel data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figures 7 and 8. Command Register_2 specifies whether a 0 IRE or 7.5 IRE blanking pedestal is to be generated, and whether or not sync infonnation is to be encoded on the video output. A 0 IRE pedestal will force the black level and the blank level to be the same. 4 ·288 SECTION 4 The varying output current from the O/A converters produces a corresponding voltage level, which is used to drive the CRT monitor. Tables 6 and 7 detail how the SYNC· and BLANK* inputs modify the output levels. The O/A converters on the Bt463 use a segmented architecture in which bit currents are routed to either the current output or GND by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabilizes the full scale output current against temperature and power supply variations. Bt463 Circuit Description (continued) SYNC DISABUlD SYNC ENABLED MA V MA 19.05 0.714 26.tn 1.000 1M 0.1)54 9.05 0340 ~----------~~------~----------------~Aa~va 7.62 0.286 7.51RB -+__________ -J'--...,.........,.__...I..-________________ 0.00 0.000 0.00 0.000 V -.----~r_--------------------~~------wmrn~~ ~ANK ~a 401RB ~ ______________ Note: 75 n doubly terminated load, RSET tolerances are assumed on all levels. ~~ ____________________ = 523 n, VREF = 1.235 V. SYNC~ Blank pedestal = 7.5 IRE. RS-343A levels and Figure 7. Composite Video Output Waveform (SETUP =7.5 IRE). Description Sync Iout(mA) No Sync lout (mA) SYNC· BLANK* DAC Input Data WHITE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 19.05 data + 1.44 data + 1.44 1.44 1.44 0 0 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: Typical with RSET = 523 n. VREF = 1.235 V. Blank pedestal = 7.5 IRE. Table 6. Video Output Truth Table (SETUP = 7.5 IRE). RAMDACs 4·289 Bt463 Circuit Description (continued) SYNC DISABU!D SYNC BNABIJID )fA V )fA V 11.60 Il.fi9Il 'JIj.61 1.000 0.00 0.000 1.05 0.302 0.00 0.000 -r----~~--------------------~------wmmuw~ 4-__________-'----,..---.--1._______________ BLACK/lILANK LB~ 43lRB ~ ____________ Note: 75 n doubly terminated load, RSET tolerances are assumed on all levels. ~~~ _________________ =495 n, VREF = 1.235 V. Blank pedestal SYNCLB~ =0 IRE. RS·343A levels and Figure 8. Composite Video Output Walle!orm (SETUP = 0 IRE). Description Sync Iout(mA) No Sync lout (mA) SYNC· BLANK· WlllTE DATA DATA· SYNC BLACK BLACK·SYNC BLANK SYNC 26.67 data + 8.05 data 8.05 0 8.05 0 18.60 data data 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 1 0 0 Note: $FF data data $00 $00 $xx $xx Typical with RSET =495 n, VREF =1.235 V. Blank pedestal =0 IRE. Table 7. Video Output Truth Table (SETUP = 0 IRE). 4·290 DAC Input Data SECTION 4 Bt463 Circuit Description (continued) Overlay and Underlay Operation of the start address of the window type table. The common overlay palette is located at addresses $0201 to $020F. The Bt463 has capabilities for multiple plane overlay and underlay operation. Instead of a dedicated overlay color palette, the overlay palette may be indexed to each of the independent color maps as specified by the user. Overlay color is determined by subtracting $10 from the start address referenced in the window type table and adding the overlay value. Overlay data can originate from a number of sources. The source location of the overlays is determined by the window type word and command register. All display modes have the capability of utilizing pixel ports 24 to 27 for the overlay address. In addition, for pseudo color applications, the overlay information can originate from the four planes above the pixel planes. For instance, if pixel information is being addressed from PO to P7, then overlay planes may come from P8 through Pll, with P8 being the LSB of the overlay word. For true color applications, overlay information can also be addressed from the least significant bits of the red, green, and blue pixel data. Two LSBs are used from the blue pixel port. The overlay word <0L3:0LO> consists of P17, PO, P8, and P16 (after shift operation), with P16 being the LSB of the overlay word. The overlay enable mask bits designate whether some or all of the LSB pixel data is to be used as overlay planes. Instead of multiple overlay palettes, the user can choose a fixed overlay location for all window type entries. The location of the common overlay palette is fixed, independent Underlay operations with various planes can be achieved by changing command register bit CR 12 to underlay operation. Once this bit is set for underlay operation, OL3 determines whether the remaining overlay planes should be interpreted as overlay or underlay. If underlays are unavailable as specified in the command register, then the overlay ports are restricted to cursor and overlay operation only. To obtain overlay and underlay operation, the overlay mask must be set to $F. All other values of the overlay mask would result in a compacted overlay word, yielding only underlay operation. In the standard mode, the Bt463 utilizes 4 overlay/underlay planes providing a palette of 16 colors. However, the Bt463 has a special mode where the window type bits serve as the upper nibble to the overlay port. By setting a command register bit, 8 overlay planes become available. However, no window operation is available as these window type ports are used strictly for overlay ports. Hardware cursor is still available through OLO and OLI. Both true color and pseudo color operation are available in the 8 overlay plane mode. The physical location of the overlay palette is fixed to a preassigned location. If a color map start address is specified to be $0000, then overlay colors are located at physical address $0201 to $020F. For other start addresses, refer to Figure 9 for a diagram showing the overlay and pixel palette color map scheme. Tables 8 and 9 provide details of overlay operation for different modes of operation. $0000 -----------------------Overlay palette Start Address Color Map 1 Pixel palette ------_ ....----------- .... Overlay palette Start Address Color Map 2 Pixel palette ------------------------ Overlay palette Start Address Color Map 3 Pixel palette $020F T Color Map I + Color Map 2 ~ t Color Map 3 t Figure 9. Overlay and Pixel Palette Color Map Scheme. RAMDACs 4·291 Bt463 Circuit Description (continued) Display Mode Window Type Field Overlay Location Overlay Location True Color 000 000 0 1 P<27:24> P <17,0,8, 16> Pseudo Color 001 001 0 1 P <27:24> P Bank Select 010 010 0 1 P<27:24> P <17, 0, 8,16> 12 Plane True Color (Load Interleave) 100 100 0 1 P<27:24> P <17, 0, 8,16> Pseudo Color (Load Interleave) 101 101 0 1 P<27:24> not available Table 8. Overlay Location Truth Table. Underlay Enable (CRI2) Mapped Function ()()()() Pixel Port Physical Ram location Addressed by frame buffer Operating Mode $000 $001 : $IFF S tart Address + $000 S tart Address + $00 1 : Start Address + $IFF pixel data overlay only x x ()()()() : : x ()()()() 0 : 0 0 1111 : 0010 0001 $xxx : $xxx $xxx Start Address--$lO+ $F : Start Address-$1 0 + $2 Start Address-$1O + $1 1 1 1 1 1 1 1 1 1111 1110 1101 1100 1011 1010 1001 1000 $xxx $xxx $xxx $xxx $xxx $xxx $xxx $xxx Start Address-$10 + $F Start Address-$10 + $E Start Address-$10 + $D Start Address-$10 + $C Start Address-$1O + $B Start Address-$1O + $A Start Address-$1O + $9 Start Address-$10 + $8 1 1 1 1 1 1 1 0111 0110 0101 0100 0011 0010 0001 $000 $000 $000 $000 $000 $000 $000 Start Address- $10 + $7 Start Address-$10 + $6 Start Address-$1O + $5 Start Address-$1O + $4 Start Address-$1O + $3 Start Address-$1O + $2 Start Address-$1O + $1 overlay underlay Table 9. Palette and Overlay Select Truth Table (No Hardware Cursor Interfacing the Overlay Port) CR =00, B<16:13> =$F. 4 ·292 SECTION 4 Bt463 Circuit Description (continued) Hardware Cursor Inter/ace overlay port. Adding cursor planes through the overlay port reduces the available colors for overlays and underlays. The Bt463 has numerous configurations for interfacing with a hardware cursor. Utilizing two enny codes of the window type table for a two-color cursor provides the best method of maximizing overlay plane availability without sacrificing a large number of window type entries. In the one-cursor plane mode, OLO directly addresses the cursor color palette and overrides all other inputs. Otherwise, the overlay ports can be used directly as cursor ports but require setting command register bits CR10 and CRll to configure the RAMDAC for either a single plane cursor or dual-plane cursor through the By setting a command register, mapped function OLJ determines whether OL1 and OL2 serve as overlay or underlays. Only seven combinations of overlaysl underlays are available. Refer to Table 10 for more details. Underlay Enable (CR12) Mapped Function x x : x 0000 0000 One Plane Cursor (Overlay Port) Physical Ram Location Addressed by Frame Buffer Operating Mode Start Address + $000 Start Address + $00 1 : Start Address + $lFF pixel data 0000 $000 $001 : $lFF x xxxI $xxx Cursor Color 0 cursor 0 0 0 0 0 0 0 1110 1100 1010 1000 0110 0100 0010 $xxx $xxx $xxx $xxx $xxx $xxx $xxx Start Address-$10 + $E Start Address-$10 + $C Start Address-$10 + $A Start Address-$10 + $8 Start Address-$10 + $6 Start Address-$10 + $4 Start Address-$10 + $2 x xxxI $xxx Cursor Color 0 1 1 1 1110 1100 1010 1000 $xxx $xxx $xxx $xxx Start Address-$10 + $E Start Address-$10 + $C Start Address-$10 + $A Start Address-$10 + $8 1 1 1 0110 0100 0010 $000 $000 $000 Start Address-$10 + $6 Start Address-$10 + $4 Start Address-$10 + $2 1 : Pixel Port overlay only cursor overlay underlay Table 10. Palette and Overlay Select Truth Table (One Plane Hardware Cursor Inter/acing the Overlay Port) CR<11 :10> = 01, B<16:13> = $F. RAMDACs 4·293 Bt463 Circuit Description (continued) Two Plane Cursor (Overlay Port) In the two-cursor plane mode, both mapped functions 01.0 and OLI become cursor planes with 01.0 being the least significant bit. With the lDlderlay enabled, 01..3 detennines whether OLZ serves as an overlay or an underlay. Refer to Table 11 for more details. Underlay Enable (CRI2) Mapped FlDIction <01..3: 01.0> Pixel Port Physical Ram location Addressed by frame buffer Operating Mode $000 $001 Start Address + $000 Start Address + $001 pixel : : data x 0000 0000 : 0000 $IFF Start Address + $IFF x x xxOI xxIx $xxx $xxx Cursor Color 0 Cursor Color 1 cursor 0 0 0 1100 1000 0100 $xxx $xxx $xxx Start Address-$10 + $C Start Address-$IO + $8 Start Address-$10 + $4 overlay only x x xxOl xxIx $xxx $xxx Cursor Color 0 Cursor Color 1 cursor 1 I 1100 1000 $xxx $xxx Start Address-$10 + $C Start Address-$IO + $8 overlay I 0100 $000 Start Address-$IO + $4 lDlderlay x x : Table 11. Palette and Overlay Select Truth Table (Two Plane Hardware Cursor Inter/acing the Overlay Port) CR<11:10> =10, B<16:13> = $F. 4·294 SECTION 4 Bt463 Circuit Description (continued) Boundary Scan Testability Structures All the complexity of RAMDACs increases, the need to easily access the RAMDAC for functional verification is becoming vital. The Bt463 has incorporated special circuitry that allows it to be accessed in full compliance with standards set by the Joint Test Action Group (ITAG). Conforming to the IEEE P1149.1 "Standard Test Access Port and Boundary Scan Architecture," B t463 has dedicated pins which are used for testability purposes only. ITAG's approach to testability utilizes boundary scan cells placed at each digital pin, both inputs and outputs. All scan cells are interconnected into a boundary-scan register (BSR) which applies or captures test data used for functional verification of the RAMDAC. ITAG is particularly useful for board testers using functional testing methods. ITAG consists of four dedicated pins comprising the Test Access Port (TAP). These pins are TMS (Test Mode Select), TCK (Test Clock), TDI (Test Data Input), and TOO (Test Data Out). Complete verification of the RAMDAC can be achieved through these four TAP pins. With boundary-scan cells at each digital pin, the Bt463 has the capability to apply and capture the logic level. Since all of the digital pins are interconnected as a long shift register, the TAP logic has access and control of all the necessary pins to verify functionality. The TAP controller can shift in any number of test vectors through the TDI input and apply them to the internal circuitry. The output result is scanned out on the TOO pin and externally checked. While isolating the Bt463 from the other components on the board, the user has easy access to all Bt463 digital pins through the TAP and can perform complete functionality tests without using expensive bed-of-nails testers. The bidirectional MPU port is given special attention with respect to ITAG. Because ITAG requires control over each digital pin, an additional output enable (OE) function is included in the BSR for the MPU pins. In conjunction with the ITAG instruction, the output enable will configure the MPU port as an input or output. With the ITAG bus, users also have access to a vital portion of the Bt463, the Output Signature Analysis Register (See Figure 10). With access to this register, users can easily verify expected video data serially through the ITAG port. The OSAR is located between the lookup table and the inputs to the DACs. The power-on reset (POR) circuitry ensures that the Bt463 initializes each pin to operate in a RAMDAC mode instead of a ITAG test mode during power-up sequence. A variety of verification procedures can be performed through the TAP Controller. Through a set of eight instructions, the Bt463 can verify board connectivity at all digital pins, generate artificial pixel vectors on-chip, check signatures on system pixel streams, and scan vectors in and out of the pixel shifter and signature analysis register. The instructions are accessible through the use of a simple state machine. For full explanation and details of the Bt463 ITAG instruction set, please consult the Application Note Bt463 ITAG Implementation, available in 1991. RAMDACs 4·295 - Bt463 Circuit Description (continued) Figure 10. }TAG Block Diagram. 4-296 SECTION 4 Bt463 Internal Registers Command Register_O This register may be written to or read by the MPU at any time and is not initialized. CROO corresponds to data bus bit DO. CR07,CR06 Multiplex select (00) reserved (01) 4:1 multiplexing (10) 1: 1 multiplexing (11) 2:1 multiplexing These bits specify whether 1:1, 2:1, or 4: 1 mUltiplexing is to be used for the pixel and overlay inputs. If 2: 1 is specified, the (C) and {D} pixel and overlay inputs are ignored and should be connected to GND, and the LD* input should be 1/2 the CLOCK rate. If 4: 1 is specified, all of the pixel and overlay inputs are used, and the LD* input should be 1/4 the CLOCK rate. If 1: 1 is specified, the {B}, {C}, and {D} inputs are ignored. Note that in the 1:1 multiplex mode, the maximum clock rate is 66 MHz. LD* is used for the pixel clock. Although CLOCK is ignored in the 1:1 mode, it must remain running. Note that it is possible to reset the pipeline delay of the Bt463 to a fixed 13 clock cycles. In this instance, each time the input multiplexing is changed, the Bt463 must again be reset to a fixed pipeline delay. CR05,CR04 reserved (logical zero) CR03,CR02 Blink rate selection (00) 16 on, 48 off (25n5) (01) 16 on, 16 off (SO/50) (10) 32 on, 32 off (SO/50) (11) 64 on, 64 off (SO/50) CROl,CROO These two bits specify the blink rate cycle time and duty cycle, and are specified as the number of vertical retrace intervals. The numbers in parentheses specify the duty cycle (% on/off). The counters that determine the blink rate are reset when command register_O is written to. reserved (logical zero) RAMDACs 4- 297 Bt463 Internal Registers (continued) Command Register_1 This register may be written to or read by the MPU at any time and is not initialized. CR 10 corresponds to data bus bit DO. CR17 reserved (logical zero) CR16 Overlay mapping (0) Mapped to start address (1) Mapped to common palette CR15 Contiguous Plane Configuration (0) (1) CR14 24/28 planes contiguous 12/16 planes contiguous Overlay planes select (0) 4 overlay planes (1) 8 overlay planes 4·298 SECTION 4 Determines the physical address location of the overlay. In the standard mode, overlays are addressed with respect to the start address specified in the start address field of the window type table. The alternate mapping option addresses the same portion of the color map for overlays regardless of the start address location. For this mode, the overlays must be located at physical address locations $0201 - $020F. Allows the B t463 to be used with 12- or 16-plane systems with an easy field upgrade to 24/28 planes. In the 12/16 plane configuration, up to 12 planes of true color are available. Red must be entered at P<3:O>, blue at P<4:7>, and green at P. No shift is of use with 12-plane true color and the shift value in the window type word should be set to zero. The standard pseudo color mode is available, up to nine planes. In this mode, the shift value should be between 0 and either 11 (12-plane systems) or 15 (16 plane systems). In 16-plane systems, the 4 planes of overlay should be entered at P<15:12>. If the alternate location overlay is selected, then overlays are input at P<5,O,8,4> for the true color mode or at P for the pseudo color mode. Unused pixel pins must be grounded. special mode which configures the Bt463 for 8 overlay planes. This mode can be used for either the standard true color or pseudo color display modes. For true color applications, the red pixel port corresponds to PO-P7, green corresponds P8-P15, and blue corresponds to PI6-P23. The four least significant overlay bits, OLO-OL3 are assigned pixel port P24-P27. The window type port is converted into the four most significant bits of the overlay port where WTO-Wf3 correspond to OlA--OL7, respectively. All 16 window type entries must be loaded and must be set to the same value. The recommended configuration is true color, no shift, 8 planes, all overlay inputs enabled, and the standard overlay location. Although different window display modes are no longer available, pixel operation is still user-defined based on the window type word placed in all 16 type entries. The only field with a restriction is the start address, which should have a value of 010000 ($0100). Thus, the physical location of the pixel lookup table and the overlay palette are preassigned, with the pixel color palette starting from $0100 and ending at $OIFF while the overlay palette RAM is located at $0000 to $OOFF. Bt463 Internal Registers (continued) Command Register_1 (continued) This regista- may be written to or read by the MPU at any time and is not initialized. CRI0 corresponds to data bus bit DO. CRI3 Window type entries (0) (1) CRI2 Underlay enable (0) (1) CR11-CRIO 16 entries 14 entries underlays disabled underlays enabled Overlay conftguration (00) no cursor (01) one cursor plane (10) two cursor planes (11) reserved Determines the number of entries available in the window type table. If 14 entries are selected, then the two window type codes, SE and SF, correspond to cursor color 0 and cursor color 1 respectively. Determines the underlay availability. Once this bit is set to a logic one, underlays operation is achieved when the 01.3 plane is a logic zero. Conftgures the overlay port so that overlay pins may be used as a hardware cursor port. By configuring this regista-, these overlay ports will directly address the cursor palette. If the overlay ports are used for cursors, they must be used on OLO and OLI. OLO is the least signiftcant cursor bit OLO must be used for the single cursor mode. This overlay conftguration register applies to the standard 4-p1ane mode or the eight-plane overlay option. RAMDACs 4- 299 Bt463 Internal Registers (continued) This register may be written to or read by the MPU at any time and is not initialized. CR20 corresponds to data bus bit DO. CR27 Sync enable This bit specifies whether sync information is to be output onto lOG (logical one) or not (logical zero). (0) (1) CR26 disable sync enable sync Pedestal enable (0) (1) 0 IRE pedestal 75 IRE pedestal CR25-CR23 reserved (logical zero) CR22 Input SAR capture selection (0) (1) CR21 Analysis register clock control (0) (1) CR20 every LD* cycle every CLOCK cycle Test mode select (0) (1) 4-300 lower 16 bits upper 16 bits SECTION 4 signature analysis test data strobe test This bit specifies whether a 0 or 7.S IRE blanking pedestal is to be generated on the video outputs. 0 IRE specifies that the black and blank levels are the same. This bit specifies whether the 16-bit input signature analysis register (SAR) should capture the lower or upper 16 bits of the pixel path. This bit controls the rate of operation of all signature analysis register (SAR) clocking. Logical zero is the normal mode, with pixel position (A, B, C, or D) determined by the test register. Logical one is a special mode for chip testing (in this instance, SAR operation is not guaranteed for clock rates above 30 MHz). This bit determines the method of high-speed test used. TIle signature analysis registers are used to hold the test result for both test methods. Bt463 Internal Registers (continued) IDRegister This 8-bit register may be read by the MPU to delezmine the type of RAMDAC being used in the system. The value is different for each RAMDAC. For the Bt463, the value read by the MPU will be $2A. Data written to this register is ignored. Pixel Read Mask Register The 28-bit pixel read mask register is used to enable (logical one) or disable (logical zero) a bit plane from addressing the color palette RAM. Each register bit is logically ANDed with the corresponding bit plane input. The masking flDlCtion is independent of all the operations specified by the window type entries, masking the pixel ports prior to pixel manipulation. This register may be written to or read by the MPU at any time and is not initialized. DO corresponds to PO, P8, P16, and P24. Pixel Blink Mask Register The 28-bit pixel blink mask register is used to enable (logical one) or disable (logical zero) a bit plane from blinking at the blink rate and duty cycle specified by command register_O. The blinking function is independent of all the operations specified by the window type entries, blinking the pixel ports prior to pixel manipulation. This register may be written to or read by the MPU at any time and is not initialized. DO corresponds to PO, P8, P16, and P24. Revision Register This 8-bit register is a read-only register, specifying the revision of the Bt463. The four most significant bits signify the revision letter in hexadecirnaJ form. The four least significant bits do not represent any value and should be ignored. RAMDACs 4-301 .. Bt463 Internal Registers (continued) Red, Green, and Blue Output Signature Registers (OSAR) SiglUllru'e Operation These three 8-bit signature registers may be read by the MPU while BLANK· is a logical zero. While BLANK· is a logical one, the signatures are being acquired. The MPU may write to the output signature registers while BLANK· is a logical zero to load the seed value. The output signature registers use data being loaded into the output DACs to calculate the signatures. ITAG logic can access the output signature analysis register independently of the MPU operation. MPU accesses to the output signature analysis registers require one address register load to address S020F followed by 3 reads or writes to the red, green, and blue signature registers, respectively. DO corresponds to RO, GO, and BO. When a test display is loaded into the frame buffer, a given value for the red, green, and blue signature registers will be returned if all circuitry is working properly. J)Q/a Strobe Operation If command bit CR20 selects "data strobe testing," the operation of the signature registers changes slightly. Rather than determining the signature, they capture red, green, and blue data being presented to the three DACs. Each LD. cycle, the three signature registers capture the color values being presented to the DACs. As only one of the (A-D) pixels can be captured each LD· cycle, DO-D2 of the test register are used to specify which pixel (A-D) is to be captured. Input Signature Registers (ISAR) SiglUllllre Operation This 16-bit signature register may be read by the MPU while BLANK· is a logical zero. While BLANK· is a logical one, the signatures are being acquired. The MPU may write to the input signature register while BLANK· is a logical zero to load the seed value. The input signature register uses PO-P15 or PI6-P27 and WTO-Wf3 (selected by command bit CR22) to calculate the signatures. The 16 bits of data latched in the input signature register may be masked (forced low) by the read mask registers. MPU accesses to the input signature analysis register require one Address register load to S020E followed by 3 reads or writes to, respectively, lower byte, upper byte, and dummy access. DO corresponds to PO and P8 or to P16 and P24. When a test display is loaded into the frame buffer, a given value for the input signature register will be returned if all circuitry is working properly. J)Q/a Strobe Operation If command bit CR20 selects "data strobe testing," the operation of the input signature register changes slightly. Rather than determining the signature, it just captures and holds the 16 bits of pixel data addressing the color palette RAM. Each LD* cycle, the input signature register captures the 16 bits of pixel data addressing the color palette RAM. As only one of the (A-D) pixels can be captured each LD. cycle, DO-D2 of the test register are used to specify which pixel (A-D) is to be captured. 4·302 SECTION 4 Bnxktree~ Bt463 Internal Registers (continued) Test Register This 8-bit register is used for testing the Bt463. H 1:1 pixel multiplexing is specified, signature analysis is done on every pixel; if 2:1 pixel multiplexing is specified, signature analysis is done on every second pixel; if 4:1 pixel multiplexing is specified, signature analysis is done on every fourth pixel. OO-D2 are used for 2: 1 and 4: 1 mUltiplexing to specify whether to use the A, B, C, or D pixel inputs, as follows: D2-DO Selection 000 001 010 011 100 101 110 111 pixel A pixel B pixelC pixel D reserved reserved reserved reserved In 1: 1 mUltiplexing mode, DO-D2 should select pixel A. D3-D7 are used to compare the analog ROB outputs to each other and to a 145 mV reference. This enables the MPU to determine whether the CRT monitor is connected to the analog ROB outputs or not, and whether the DACs are functional. D7 D6 D5 04 D3 red select green select blue select 145 mV ref. select result D7-04 0000 1010 1001 0110 0101 normal operation red DAC compared to blue DAC red DAC compared to 145 mV reference green DAC compared to blue DAC green DAC compared to 145 mVreference HD3=1 IfD3=0 red > blue red> 145mV green> blue green> 145 mV blue > red red < 145 mV blue > green green < 145 mV - The table above lists the valid comparison combinations. A logical one enables that function to be compared; the result is D3. The output levels of the DACs should be constant for 5 I1s to allow enough time for detection. The capture occurs over one LD* period set by a logic one at any of the pixel pins P16A, P16B, PI6C, or PI6D. For normal operation, D4-D7 must be a logical zero. RAMDACs 4-303 - Bt463 Pin Descriptions Pin Name Description BLANK* Composite blank control input (lTL-compatible). A logical zero drives the analog output to the blanking level, as illustrated in Tables 6 and 7. It is latched on the rising edge of LD*. When BLANK* is a logical zero, the pixel and overlay inputs are ignored. SYNC* Composite sync control inputs (ITL-compatible). A logical zero typically switches off a 40 IRE current source on the lOG output (see Figures 9 and 10). SYNC· does not override any other control or data input, as shown in Tables 6 and 7; therefore, it should be asserted only during the blanking interval. SYNC. is latched on the rising edge of LD*. LD* Load control input (ITL-compatible). The PO-P27 {A-D}, WTO-Wf3 {A-D}, BLANK·, and SYNC· inputs are latched on the rising edgeofLD*. LD*, while it is the output clock (1:1 multiplex mode) or is 1tl or 1/4 of CLOCK, may be phase-independent of the CLOCK and CLOCK* inputs. LD* may have any duty cycle, within the limits specified by the A.C. Characteristics section. PO--P27 {A-D} Pixel select inputs (ITL-compatible). These inputs are used to specify, on a pixel basis, which location of the color palette RAM is to be used to provide color information. The function of each of these pixel ports is configurable depending on the entry of the window type table. In fact, overlay data may exist from various locations of this pixel port. If data exists in the assigned overlay input port, then pixel data inputs are ignored. Overlay information (up to four bits per pixel) for either one, two, or four consecutive pixels are input through this port. Either one, two, or four consecutive pixels (up to 24 bits per pixel) are input through this porL All 4 pixels (112 bits) are latched on the rising edge of LD*. Unused inputs should be connected to GND. Note that typically the {A} pixel is output first, followed by the {B} pixel, etc., until all one, two, or four pixels have been output, at which point the cycle repeats. WTO-Wf3 {A-D} Window type inputs (lTL-compatible). These inputs are latched on the rising edge of LD*. The window type references a location within the window type table which configures the corresponding pixel data or overlay data into user-defined display modes. Unused inputs should be connected to GND. lOR, lOG, lOB Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 n coaxial cable (Figure 13). All outputs, whether used or not, should have the same output load. TCK Test Clock (ITL-compatible). Used to synchronize all ITAG test structures. Maximum clock rate for this pin is 50 MHz. When not performing ITAG operations, this pin should be driven to a logic high. TMS Test Mode Select (ITL-compatible). ITAG input pin whose transitions drive the ITAG state machine through its sequences. When not performing ITAG operations, this pin should be driven to a logic high. TDI Test Data Input (ITL-compatible). ITAG input pin used for loading instructions to the TAP controller or for loading test vector data for boundary scan operation. When not performing ITAG operations, this pin should be driven to a logic high. TOO Test Data Output (TTL-compatible). ITAG output used for verifying test results of all ITAG sampling operations. This output pin is active for certain ITAG sequences, and will be 3-stated at all other times. When not performing ITAG operations, this pin should be left floating. VAA Analog power. All VAA pins must be connected. GND Analog ground. All GND pins must be connected. 4·304 SECTION 4 Bt463 Pin Descriptions (continued) Pin Name Description COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 IiF ceramic capacitor must be connected between this pin and VAA (Figure 11). Connecting the capacitor to V AA rather than to GND provides the highest possible power supply noise rejection. The COMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to PC Board Layout Considerations for critical layout criteria. FS ADJUST Full scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full scale video signal (Figure 11). Note that the IRE relationships in Figures 9 and 10 are maintained, regardless of the full scale output current. The relationship between RSET and the full scale output current on lOG is: RSET (ohms) = Kl * VREF (V) I lOG (mA) The full scale output current on lOR and lOB for a given RSET is: .. lOR, lOB (mA) = K2 * VREF (V) I RSET (ohms) where Kl and K2 are defined as: Setup lOG IOR,IOB 7.5 IRE Kl = 11,294 K2= 8,067 oIRE Kl = 10,684 K2 = 7,457 VREF Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 11, must supply this input with a 1.235 V (typical) reference. The use of a resistor network to generate the reference is not recommended, as any low frequency power supply noise on VREF will be directly coupled onto the analog outputs. A 0.1 IiF ceramic capacitor is used to decouple this input to VAA, as shown in Figure 11. If VAA is excessively noisy, better performance may be obtained by decoupling VREF to GND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. CLOCK, CLOCK* Clock inputs. These differential clock inputs are designed to be driven by ECL logic configured for single supply (+5 V) operation. The clock rate is typically the pixel clock rate of the system. CE* Chip enable control input (IlL-compatible). This input must be a logical zero to enable data to be written to or read from the device. During write operations, data is internally latched on the rising edge of CE*. Care should be taken to avoid glitches on this edge-triggered input. R/W Read/write control input (ilL-compatible). To write data to the device, both CE* and R/W must be a logical zero. To read data from the device, CE* must be a logical zero and R/W must be a logical one. R/W is latched on the falling edge of CE*. CO,CI Command control inputs (IlL-compatible). CO and CI specify the type ofread or write operation being performed, as illustrated in Table 1. They are latched on the falling edge of CE*. DO-D7 Data bus (ilL-compatible). Data is transferred into and out of the device over this eight-bit bidirectional data bus. DO is the least significant bit. RAMDACs 4· 305 BnxKtree® Bt463 Pin Descriptions (continued)-169-pin PGA Package Signal BLANK* SYNC* LD* CLOCK* CLOCK POA POB Signal Pin Number Signal Pin Number Jl P9A P9B P9C P9D AIO BIO B9 CIO PI9A PI9B PI9C PI9D Tl3 Ul3 RI3 UI4 PIOA PIOB PIOC PlOD AI2 Cll All Bll P20A P20B P20C P20D RI2 Ull TI2 UI2 PllA PllB PllC PllD AI4 BI2 Al3 CI2 P2IA P2IB P2IC P210 Tll U9 Rll UIO PI2A PI2B PI2C PI2D AI6 Cl3 AI5 Bl3 P22A P22B P22C P22D RIO U8 TIO Pl3A Pl3B Pl3C PI3D CI4 BI5 AI7 BI4 P23A P23B P23C P23D T7 PI4A PI4B PI4C PI4D DI5 BI6 EI5 CI5 P24A P24B P24C P24D R6 U4 R7 U5 PI5A PI5B PI5C PI5D DI6 CI7 CI6 Bl7 P25A P25B P25C P25D T5 U2 T6 U3 PI6A PI6B PI6C PI6D TI6 TI7 RI6 RI7 P26A P26B P26C P26D T4 R4 R5 UI PI7A PI7B PI7C PI7D RI5 RI4 PI5 UI7 P27A P27B P27C P27D R3 N3 PI8A PI8B PI8C PI8D TI4 Ul5 TI5 UI6 TMS TCK TDI TOO Dl7 EI6 El7 PI7 HI H3 J3 J2 F2 POC G3 PI POD Gl PIA PIB PIC PlO F3 DI E2 EI P2A P2B P2C P2D C2 BI D2 CI P3A P3B P3C P3D C3 P4A P4B P4C P4D P5A P5B P5C P5D 4-306 Pin Number D3 E3 B2 Al B3 C4 T9 U6 T8 U7 D4 A3 C5 A2 B4 P6A P6B P6C P6D B6 A4 B5 P7A P7B P7C P7D A7 C7 A6 C6 P8A P8B P8C P8D A9 B8 A8 B7 AS SECTION 4 T3 TI BlU(j{tree® Bt463 Pin Descriptions (continued)-169-pin PGA Package Signal WTOA WTOB WTOC WTOD Pin Signal PI lOR P3 100 Rl Number Ml WT2A Ll N2 WT3A WT3B WT3C WT3D DO D1 D2 D3 D4 D5 D6 D7 Signal lOB F16 HIS F15 COMP FS ADJUST VREF K15 H16 GI6 VAA VAA VAA VAA VAA VAA VAA R8 M16 CE* R/W Cl CO N15 N16 P17 P16 GND GND GND GND GND GND GND C9 G2 GIS H2 LIS MIS R9 1'2 WTIA WTIB WTIC WTlD WT2B WT2C WT2D Pin Number P2 Nl R2 L3 M3 Pin Number C8 GI7 H17 115 K2 .. Kl L2 K3 M2 N17 LI6 M17 K16 LI7 116 K17 117 RAMDACs 4 - 307 Bt463 Pin Descriptions (continued)-169-pin PGA Package 17 P13C PlSD PlSB TMS rol roo VAA VAA D7 D6 D4 D2 DO CI PI6D Pl6B Pl7D 16 Pl2A PI4B PlSC PlSA TCK lOR VRBP PSADJ DS D3 Dl VAA R/W co PIOC PlfiA PI8D IS PI2C PI3B PI4D PI4A PI4C lOB GND lOG VAA COMP GND GND (]l" Pl7C PI7A PlSC PI8B 14 PlIA Pl3D PI3A PI7B PI8A PI9D 13 PlIC PlZO Pl2B PI9C PI9A PI98 12 PlOA PlIB PllD P20A P20C P20D II PIOC PI(J) PlOB PZIC PZIA P20B 10 P9A P9B P9D P22A P22C P2!D GND P22D P2!B 4 2 (TOP VIEW) P8A P9C GND PSC PSB VAA VAA P23C P22B P7A P8D P7B P24C P23A P23D P7C P6B P7D P24A P2SC P23B P6A P6D PSB P26C PZSA P24D P6C PSD P4C P4D P26B P26A P24B PSA P4B P3A P3B P3C PIA POB LD" o.K" Wf3C WT2C WT2D PZ7B WfOB PZ7A P27C PZSD PSC P3D P2A P2C PIC POA GND GND CLK VAA Wf3B Wf3D Wf2B WfIB WfID WfOD PZSB P2B P2D PIB PIO POC p(J) SYNC· BLK* Wf3A Wf2A WfIA WfIC WfOA wroc PZ7D P26D B C D Il F G H K L M N P R T U S A alignment marker (on top) 4 ·308 Bt463 SECTION 4 Bt463 Pin Descriptions (continued)-169-pin PGA Package 17 PI7D Pl6B Pl6D C1 DO D2 D4 D6 D7 VAA VAA 100 TO[ TMS PISB PISD Pl3C 16 P[BD PIM PI6C (Xl R/W VAA DI D3 DS PSAD! VREP lOR TCK PISA PI3C PI4B PI2A IS Pl8B PI8C Pl7A PI7C CE· GND GND COMP VAA [(Xl GND lOB PI4C PI4A Pl4D PI3B Pl2C 14 PI9D PlSA PI7B Pl3A PI3D P11A 13 Pl9B Pl9A PI9C PI2B PI2D PlIC 12 P2IlD P20C P20A PllD PlIB PlOA 11 P20B P2IA P2IC PIOB PlOD PlOC 10 P21D P22C P22A P9D P9B P9A P21B P22D GND GND P9C PSA P22B P23C VAA VAA PSB P8C P23D P23A P24C P7D P8D P7A P23B P2SC P24A P7D P6B P7C P24D P2SA P26C PSB P6D P6A P24B P2M P26B NO P4C PSD P6C P2SD P27C P27A WfOB P27B Wf2D Wf2C Wf3C CLK· LD· POD PIA P3C P3D P3A P4D PSA P2SD wroo WfID WfIB Wf2B Wf3D Wf3B VAA CLK GND GND POA PIC P2C P2A P3D P3C P26D P27D wroc WfOA WfIC WfIA Wf2A Wf3A BLK· SYNC· POD POC PID PIB P2D P2B ~ U T R P N M L K H G P B D C B A 4 2 (BOTTOM VIEW) RAMDACs 4- 309 Bt463 PC Board Layout Considerations PC Board Considerations Power Planes This product requires special attention to proper layout techniques to achieve optimum perfonnance. Before beginning PCB layout, refer to the CMOS RAMDAC layout example found in Bt4511718 Evaluation Module Operation and Measurements, application note (AN-16). This application note can be found in Brooktree's 1990 Applications Handbook. Separate digital and analog power planes are necessary. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt463 power pins, VREF circuitry, and COMP and VREF decoupJing. There should be at least a 1/8 inch gap between the digital power plane and the analog power plane. The layout should be optimized for lowest noise on the Bt463 power and ground lines by shielding the digital inputs and providing good decoupling. Trace lengths between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 11, located within three inches of the Bt463. This bead provides resistance to switching currents, acting as a resistance at high frequencies. A low resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. A well-designed power distribution network is critical to eliminating digital switching noise. Ground planes must provide a low-impedance return path for the digital circuits. A minimum of a six-layer PC board is recommended. The ground layer should be used as a shield to isolate noise from the analog traces with layer 1 (top) the analog traces, layer 2 the ground plane (preferably analog ground plane), layer 3 the analog power plane, with the remaining layers used for digital traces and digital power supplies. The optimum layout enables the Bt463 to be located as close to the power supply connector and as close to the video output connector as possible. Ground Planes For optimum perfonnance, a common digital and analog ground plane with tub isolation (at least a 1/8 inch gap) connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inch from the power supply connector to preserve digital noise margins during MPU read cycles. Thus, the ground partitioning isolation technique is constrained by the noise margin constraint during digital readback of the Bt463. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. For maximum perfonnance, a separate isolated ground plane for the analog output termination resistors, RSET resistor, and VREF circuitry should be used, as shown in Figure 11. Another isolated ground plane should be used for the GND pins of the Bt463 and supply decoupling capacitors. 4-310 SECTION 4 Plane-to-plane noise coupling can be reduced by ensuring that portions of the digital power and ground planes do not overlay portions of the analog power and ground planes, unless they can be arranged such that the plane-to-plane noise is common mode. Device Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Power Supply Decoupling Best power supply decoupling perfonnance is obtained with a 0.1 ~F ceramic capacitor in parallel with a 0.01 ~F chip capacitor decoupling each of four groups of VAA pins to GND. The capacitors should be placed as close as possible to the device. The 33 ~F capacitor is for low-frequency power supply ripple; the 0.1 ~F and om ~F capacitors are for high-frequency power supply noise rejection. Bt463 PC Board Layout Considerations (continued) A linear regulator to filter the analog power supply is recommended if the power supply noise is ~ 200 mV or greater than 10 LSBs. This is especially important when a switching power supply is used and the switching frequency is close to the raster scan frequency. Note that about 100/0 of the power supply hum and ripple noise less than 1 MHz will couple onto the analog outputs. digital edge speeds (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals. Ensure that the power pins for the clock driver are properly decoupled to minimize transients. Minimize edge speeds and ringing, using damping resistors (10 to 50 il) or parallel termination where necessary. COMP DecoupUng The COMP pin must be decoupled to VAA, typically using a 0.1 ~ ceramic capacitor. Low frequency supply noise will require a larger value. Lead lengths should be minimized for best performance so that the self-resonance frequency is greater than the LD* frequency. If the display has a "ghosting" problem, additional capacitance in parallel with the COMP capacitor may help fix the problem. Digital Signal Interconnect The digital inputs to the Bt463 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power and ground planes. Most noise on the analog outputs will be caused by excessive edge speeds (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The digital edge speeds should be no faster than necessary, as feedthrough noise is proportional to the digital edge speeds. Lower speed applications will benefit using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission line mismatch will exist if the line length reflection time is greater than 1/4 the signal edge time, resulting in ringing, overshoot, and undershoot, which can generate noise onto the analog outputs. Line termination or reducing the line length is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (10 to 50 0), Radiation of digital signals can also be picked up by the analog circuitry. Prevention is done by reducing the If using parallel termination on digital signals, the resistors should be connected to the digital power and ground planes, not the analog power and ground planes. Analog Signal Interconnect The B t463 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog outputs should have a load resistor and a termination resistor equal to the transmission line impedance. The load resistor connection between the current output and GND should be as close as possible to the Bt463 to minimize reflections. Unused analog outputs should be connected toGND. Analog edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce high-frequency energy, helping to alleviate EM! and noise problems. Analog Output Protection The Bt463 analog outputs should be protected against high energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figure 11 can prevent latch-up under severe discharge conditions without adversely degrading analog transition times. This protection circuit should be located as close to the driver as possible. The IN4148J9 are low-capacitance, fast-switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7001). RAMDACs 4 - 311 .. Bt463 PC Board Layout Considerations (continued) ANALOG POWER PLANE CII Ll +sv(VcC) Bt463 GROUND (poWER SUPPLY CONNEcroR) RSET R3 FSADJUST lOR TO lOG VIDEO CONNECTOR lOB VAA 0 IN4148/9 DAC TO MONITOR OUTPUT IN4148/9 GND Location Description CI-C5, ClO, Cl1 C6-C9 C12 Ll Rl,R2, R3 R4 RSET ZI O.IIJ.F ceramic capacitor 0.01 IJ.F ceramic chip capacitor 33 IJ.F tantalum capacitor ferrite bead 75 n 1% metal fihn resistor 1000 n 1% metal fihn resistor 523 n 1% metal fihn resistor 1.2 V voltage reference Note: Vendor Part Number Erie RPEllOZ5UI04M50V AVX 12102T103QAI018 Mallory CSR13F336KM Fair-Rite 2743001111 Dale CMF-5SC Dale CMF-55C Dale CMF-55C National Semiconductor LM385Z-1.2 The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the Bt463. Figure 11. Typical Connection Diagram and Parts List. 4·312 SECTION 4 Bt463 Application Information Clock Inter/acing Due to the high clock rates at which the Bt463 may operate, it is designed to accept differential clock signals (CLOCK and CLOCK·). These clock inputs are designed to be generated by ECL logic operating at +5 V. Note that the CLOCK and CLOCK· inputs require termination resistors (typically a 220-ohm resistor to VCC and a 330-ohm resistor to GND). The termination resistors should be as close as possible to the Bt463. The CLOCK and CLOCK* inputs must be differential signals and greater than 0.6 V peak-to-peak due to the noise margins of the CMOS process. The Bt463 will not function using a single-ended clock with CLOCK* connected to ground. may be phase-shifted relative to CLOCK, the designer need not worry about propagation delays in deriving the LD* signal. LD* may be used as the shift clock for the video DRAMs and to generate the fundamental video timing of the system (SYNC*, BLANK*, etc.). For display applications where a single Bt463 is being used, it is recommended that the Bt438 Clock Generator Chip be used to generate the clock and load signals. It supports the 4:1 input multiplexing of the Bt463, and will also optionally set the pipeline delay of the Bt463 to 13 clock cycles. The Bt438 may also be used to interface the Bt463 to a TTL clock. Figure 12 illustrates using the Bt438 with the Bt463. Typically, LD* is generated by dividing CLOCK by two or four (depending on whether 2:1 or 4:1 multiplexing was specified) and translating it to TTL levels. As LD* .. +5V +sv 220 a.OCK CLOCK MONffOR PRODUCTS +sv 330 Bt463 970E 220 CLOCK' CLOCK' 330 Bt438 WA W' lK Figure 12. Generating the Bt463 Clock Signals. RAMDACs 4·313 Bt463 Application Information (continued) Setting the Pipeline Delay The pipeline delay of the Bt463, although fixed after a power-up condition, may be anywhere from 11 to 15 clock cycles. The Bt463 contains additional circuitry enabling the pipeline delay to be fixed at 13 clock cycles. The Bt438 Clock Generator Chip supports this mode of operation when used with the Bt463. To reset the Bt463, it should be powered up, with LD*, CLOCK, and CLOCK* running. Stop the CLOCK and CLOCK* signals with CLOCK high and CLOCK* low for at least three rising edges of LD*. There is no upper limit on how long the device can be held with CLOCK and CLOCK* stopped. Restart CLOCK and CLOCK* so that the first edge of the signals is as close as possible to the rising edge of LD* (the falling edge of CLOCK leads the rising edge of LD* by no more than 1 clock cycle or follows the rising edge of LD* by no more than 1.5 clock cycles). When restarting the clocks, care must be taken to ensure that the minimum clock pulse width is not violated. Resetting the Bt463 to a 13 clock cycle pipeline delay does not reset the blink counter circuitry. Therefore, if mUltiple Bt463s are used in parallel, the on-chip blink counters may not be synchronized. In this instance, the blink mask register should be $00 and the overlay blink enable bits a logical zero. Blinking may be done under software control via the read mask register and overlay display enable bits. ESD and Latchup Considerations ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay VAA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than + sync enabled on lOG, 75 IRE blanking pedestal no cursor interface 24-plane true color start address at $0001 16 window entries Control Register Initialization Write $00 to address register low Write $00 to address register high Write red data to RAM (location $000) Write green data to RAM (location $000) Write blue data to RAM (location $000) Write red data to RAM (location $001) Write green data to RAM (location $001) Write blue data to RAM (location $001) 00 01 Write red data to RAM (location $20F) Write green data to RAM (location $20F) Write blue data to RAM (location $20F) 11 11 11 11 11 11 11 11 11 CunorCoi6rPakUeInitializotion Cl,CO Write $01 to address register low Write $02 to address register high Write $40 to command register 0 Write $00 to command register 1 Write $CO to command register 2 Write $00 to reserved location Write $FF to pixel read mask register PO- P7 Write $FF to pixel read mask register PS- P15 Write $FF to pixel read mask register P16- P23 Write $FF to pixel read mask register P24- P27 Write $00 to pixel blink mask register PO- P7 Write $00 to pixel blink mask register PS-PI5 Write $00 to pixel blink mask register P16- P23 Write $00 to pixel blink mask register P24- P27 Write $00 to test register 00 01 10 10 10 10 10 10 10 10 10 10 10 10 10 Write $00 to address register low Write $03 to address register high Write $00 to BO-B7 register (location $0) Write $El to B8-B 15 register (location $0) Write $03 to BI6-B23 register (location $0) Write $00 to BO-B7 register (location $1) Write $El to B8-B15 register (location $1) Write $03 to BI6-B23 register (location $1) 00 01 10 10 10 10 10 10 Write $00 to BO-B7 register (location $F) Write $El to B8-B15 register (location $F) Write $03 to BI6-B23 register (location $F) 10 10 10 Write $00 to address register low Write $01 to address register high Write red data to cursor (location $0) Write green data to cursor (location $0) Write blue data to cursor (location $0) Write red data to cursor (location $1) Write green data to cursor (location $1) Write blue data to cursor (location $1) Write red data to cursor (location $2)· Write green data to cursor (location $2)· Write blue data to cursor (location $2)· Write red data to cursor (location $3)· Write green data to cursor (location $3)· Write blue data to cursor (location $3)· • Even though cursor locations $2 and $3 are not accessible, they must still be initialized in order for the cursor palette to operate correctly. 4-318 SECTION 4 00 01 10 10 10 10 10 10 10 10 10 10 10 10 Bt463 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage FS ADJUST Resistor Symbol Min Typ Max Units VAA TA RL VREF RSET 4.75 0 5.00 5.25 +70 Volts °C Ohms Volts Ohms 1.20 37.5 1.235 523 1.26 .. Absolute Maximum Ratings Parameter Symbol Min Typ V AA (measured to GND) Voltage on Any Signal Pin* GND-O.5 Analog Output Short Circuit Duration to Any Power Supply or Common ISC Ambient Operating Temperature Storage Temperature Junction Temperature PGA TA TS TJ TJ Soldering Temperature (5 seconds, 1/4" from pin) TSOL Max Units 6.5 Volts VAA+O.5 Volts +125 +150 +150 +170 °C °C °C °C 260 °C indefinite -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. RAMDACs 4 - 319 Bt463 DC Characteristics Parameter Analog Outputs Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs (except CLOCK, CLOCK*) Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Vin = 2.4 V) Clock Inputs (CLOCK, CLOCK*) Differential Input Voltage Input High Current (Vin = 4.0V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Vin = 4.0V) Digital Outputs (OO-D7) Output High Voltage (lOH = 400 JlA) Output Low Voltage (lOL = 3.2 rnA) 3-state Current Output Capacitance See test conditions on next page. 4- 320 SECTION 4 Symbol Min Typ Max Units 8 8 8 Bits ±1 ±l LSB LSB % Gray Scale IL DL ±5 guaranteed Binary VIH VIL I1H IlL CIN 2.0 GND--O.5 "'VIN IKIH IKIL CKIN .6 VOH 2.4 VAA+O.5 0.8 60 -60 4 6 1 -1 4 10 Volts JlA JlA pF Volts VOL IOZ CDOUT 10 Volts Volts JlA JlA pF 10 0.4 Volts 10 JlA pF Bt463 DC Characteristics (continued) Parameter Analog Outputs Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank SETUP = 7.5 IRE SETUP = oIRE Blank Level on lOG Blank Level on lOR, lOB Sync Level on lOG LSB Size DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 rnA) Symbol VOC RAOUT CAOUT Min Typ Max Units 17.69 16.74 19.05 17.62 20.40 18.50 rnA rnA 0.95 0 6.29 0 0 1.44 5 7.62 5 5 69.1 2 1.90 50 8.96 50 50 rnA J.1A rnA J.1A J.1A J.1A % Volts ill pF -0.5 5 +1.2 50 13 20 Voltage Reference Input Current IREF 90 J.1A Power Supply Rejection Ratio (COMP = 0.1 J.1F, f = 1 kHz) PSRR 0.5 %/%!!.VAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 n, VREF = 1.235 V. SETUP = 7.5 IRE. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. RAMDACs 4 - 321 Bt463 A C Characteristics Parameter Clock Rate LD" Rate 1:1 multiplexing 2:1 multiplexing 4:1 multiplexing Symbol Min/fyp/ Max 170 MHz 135 MHz 110 MHz Units Fmax LOmax max 170 135 110 MHz max max max 67.5 67.5 42.5 67.5 67.5 33.75 55 55 27.5 MHz MHz MHz RtW, CO, Cl Setup Time R/W, CO, Cl Hold Time 1 2 min min 0 15 0 15 0 15 ns ns CE"LowTime CE" High Time CE" Asserted to Data Bus Driven CE" Asserted to Data Valid CE" Negated to Data Bus 3-Stated 3 4 5 6 7 min min min max max 50 25 7 75 15 50 25 7 75 15 50 25 7 75 15 ns ns ns ns ns Write Data Setup Time Write Data Hold Time 8 9 min min 35 3 35 3 35 3 ns ns TMS, TDI Setup Time TMS, TDI Hold Time 10 11 min min 8 6 8 6 8 6 ns ns TCK Low Time TCK High Time TCK Asserted to TOO Driven TCK Asserted to TOO Valid TCK Negated to TOO 3-Stated 12 13 14 15 16 min min min max max 10 10 10 10 10 5 12 12 5 12 12 ns ns ns ns ns Pixel and Control Setup Time Pixel and Control Hold Time 17 18 min min 3 2 3 2 3 2 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time 19 20 21 min min min 5.88 2.5 2.5 7.4 3.2 3.2 9.09 4 4 ns ns ns LD" Cycle Time 1: 1 multiplexing 2: 1 mUltiplexing 4:1 mUltiplexing LD* Pulse Width High Time 1: 1 multiplexing 2: 1 multiplexing 4:1 multiplexing LD* Pulse Width Low Time 1: 1 mUltiplexing 2: 1 multiplexing 4:1 multiplexing 22 min min min 14.81 14.81 23.53 14.81 14.81 29.63 18.18 18.18 36.36 ns ns ns min min min 6 5 9 6 6 12 7 8 15 ns ns ns min min min 6 5 9 6 6 12 7 8 15 ns ns ns .. See test condllions on next page. 4·322 SECTION 4 10 5 12 12 23 24 Bt463 AC Characteristics (continued) Parameter Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time Clock and Data Feedthrough· Glitch Impulse· DAC to DAC Crosstalk Analog Output Skew Symbol Min/fyp/ Max 170 MHz 135 MHz 110 MHz Units 25 26 27 typ typ max typ typ typ typ max 12 1.5 S t!xl 50 t!xl 0 2 12 1.5 S t!xl 50 0 2 12 1.5 S t!xl 50 t!xl 0 2 ns ns ns dB pV - sec dB ns ns min max 11 15 11 15 11 15 Clocks Clocks typ max 550 t!xl 500 t!xl 450 rnA rnA Pipeline Delay VAA Supply Current.· IAA tbd tbd Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 n, VREF = 1.235 V. TTL input values are 0-3 V, with input rise/fall times S 4 ns, measured between the 10% and 90% points. ECLinput values are VAA-{).S to VAA-l.S V, with input rise/fall times S 2 ns, measured between the 20% and SO% points. Timing reference points at 50% for inputs and outputs. Analog output load S 10 pF, DO-D7 output load S 75 pF. See timing notes in Figure IS. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. ·Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the TTL digital inputs have a 1 ill resistor to GND and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough. -3 dB test bandwidth = 2x clock rate. ··AtFmax. lAA(typ) at VAA=5.0V, TA= 20" C. IAA(max) atVAA =5.25 V, TA=O·C. RAMDACs 4- 323 Bt463 Timing Waveforms L ...L. I RtW. co, CI \ VALID J 3 ~ 4 I 6 s J L-- DO - D7 (READ) DATA OUT (RJW z I) "'- V 1\ DO - D7 (WRITI!) R /' DATA IN (RJW-O) 8 f-L Figure 15. MPU Read/Write Timing Dimensions. I IDI.TMS ~ 10 * VALID 11 ~ TCK 13 14 IS L-- TOO 16 I ........ VALID AND DRIVING Note 1: TMS and TOI are sampled on the rising edge of TCK Note 2: TOO changes after the falling edge ofTCK Figure 16. JTAG Timing. 4·324 SECTION 4 I ",I /' Bt463 23 PO-P27 (A-D). wro - WI'3 (A - D). DATA SYNC*, BLANIt· 17 2S 18 lOR, JOG. JOB 19 CLOCK 21 Note 1: Output delay time measured from 50% point of the rising clock edge to 50% point of full-scale transition. Note 2: Output settling time measured from 50% point of full-scale transition to output settling within - ±ILSB_ Note 3: Output rise/fall time measured between 10% and 90% points of full-scale transition. Figure 17. Video Input/Output Timing. Ordering Information Model Number Speed Package Ambient Temperature Range Bt463KG170 170 MHz 169-pin Ceramic o· to +70· C PGA Bt463KG135 135 MHz 169-pin Ceramic O· to +70· C PGA Bt463KG110 110 MHz 169-pin Ceramic O· to +70· C PGA RAMDACs 4-325 Bt463 Revision History Datasheet Revision B 4 - 326 Change from Previous Revision Additional information on start address and true-color operation. SECTION 4 Preliminary Information This document contains information on a product under development. The parametric information contains target parameters and is subject to change. Distinguishing Features Applications 200, 170 MHz Operation 8:1 Multiplexed Pixel Ports 256 x 24 Color Palette RAM • 16 x 24 Overlay Color Palette Pixel Panning Support On-Chip User-Defmable Cursor • RS-343A Compatible Outputs Programmable Setup (0 or 7.5 IRE) X Windows Support for Cursor Standard MPU Interface 145-pin PGA Package +5 V CMOS Monolithic Construction • • • • High-Resolution Color Graphics CAE!CAD!CAM Image Processing Video Reconstruction CLOCK VAA The Bt468 triple 8-bit RAMDAC is designed specifically for high-performance, high-resolution color graphics. The multiple pixel ports and internal mUltiplexing enables TTL-compatible interfacing to the frame buffer, while maintaining the 200 MHz video data rates required for sophisticated color graphics. • Bt438, Bt439 GND 200 MHz Monolithic CMOS 256 x 24 Color Palette RAMDAC™ Product Description Related Products Functional Block Diagram CLOCK"- Bt468 On-chip features include a 256 x 24 color palette RAM, 16 x 24 overlay color palette RAM, bit plane masking and blinking, programmable setup (0 or 7.5 IRE), and pixel panning support. FS ADJUST VREF L_--L->J-T- COMP lOR The Bt468 has an on-chip three-color 64 x 64 pixel cursor and a three-color full screen (or full window) cross hair cursor. PO·p? (A·H) lOG The PLL current output enables the synchronization of mUltiple devices with sub-pixel resolution. OLO·OL3 (A·H) lOB PLL SYNC· BLANK· CE' R/W co Cl Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 IA68001 Rev. D 00·07 4 - 327 The Bt468 generates RS-343A compatible red, green, and blue video signals, and is capable of driving doubly terminated 50 Q or 75 Q coax directly, without requiring external buffering. The differential and integral linearity errors of the D/A converters are guaranteed to be a maximum of ±1 LSB over the full temperature range. Bt468 Circuit Description MPU Interface As illustrated in the functional block diagram, the Bt468 supports a standard MPU bus interface, allowing the MPU direct access to the internal control registers and color palettes. The dual-port color palette RAMs and dual-port overlay RAM allow color updating without contention with the display refresh process. As illustrated in Table I, the CO and C1 control inputs, in conjunction with the internal address register, specify which control register or color palette location will be accessed by the MPU. The 16-bit address register eliminates the requirement for external address multiplexers. ADDRO is the least significant bit. To write color data, the MPU loads the address register with the address of the primary color palette RAM, overlay RAM, or cursor color register location to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using CO and C1 to select either the primary color palette RAM, overlay RAM, or cursor color registers. After the blue write cycle, the address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. Reading color data is similar to writing, except the MPU executes read cycles. When accessing the color palette RAM, overlay RAM, or cursor color registers, the address register increments after each blue read or write cycle. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADDRa, ADDRb) that count modulo three. They are reset to zero when the MPU reads or writes to the address register. The MPU does not have access to these bits. The other 12 bits of the address register (ADDRO-ll) are accessible to the MPU. ADDRI2-ADDRI5 are always a logical zero. ADDRO and ADDR8 correspond to DO. ADDRO-15 Cl, CO Addressed by MPU $xxxx $xxxx $OOOO-$OOFF $0100 : $010F 00 01 10 10 10 10 address register (ADDR0-7) address register (ADDR8-15) reserved overlay color 0* $0181 : $0183 10 : 10 cursor color register 1* cursor color register 2* cursor color register 3* $0200 $0201 $0202 $0203 $0204 $0205 $0206 $0207 $0208 $0209 $020A $020B $020C $020D $020E $0220 $0300 $0301 $0302 $0303 $0304 $0305 $0306 $0307 $0308 $0309 $030A $030B $030C $0400-$07FF 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 ID register ($4F) command register_O command register_l command registec2 pixel read mask register reserved ($00) pixel blink mask register reserved ($00) overlay read mask register overlay blink mask register reserved ($00) test register red output signature register green output signature register blue output signature register revision register cursor command register cursor (x) low register cursor (x) high register cursor (y) low register cursor (y) high register window (x) low window (x) high window (y) low window (y) high window width low register window width high register window height low register window height high register cursor RAM $OOOO-$OOFF 11 color palette RAM* : overlay color 15* *Indicates requires three read/write cycles-ROB. Table 1. 4.- 328 SECTION 4 Address Register (ADDR) Operation. Bt468 Circuit Description (continued) Additional Information Although the color palette RAM, overlay RAM, and cursor color registers are dual-ported, if the pixel and overlay data is addressing the same palette entry being written to by the MPU during the write cycle, it is possible for one or more of the pixels on the display screen to be disturbed. A maximum of one pixel is disturbed if the write data from the MPU is valid during the entire chip enable time. Accessing the control registers and cursor RAM is also done through the address register in conjunction with the CO and C 1 inputs, as shown in Table 1. All control registers may be written to or read by the MPU at any time. When accessing the control registers and cursor RAM, the address register increments following a read or write cycle. Note that if an invalid address is loaded into the address register, data written to the device will be ignored and invalid data will be read by the MPU. Figure I illustrates the MPU read/write timing of the Bt468. Each Bt468 must be configured to be either a red, green, or blue RAMDAC via command register_2. Only the green channel (lOG) of each RAMDAC is used; the lOR and lOB outputs should be connected to GND, either directly or through a resistor up to 75 n. To load the color palettes, the MPU performs the normal (red, green, blue) write cycles to all three RAMDACs simultaneously. The red Bt468 loads color data only during the the red write cycle, the green B t468 loads color data only during the green write cycle, and the blue Bt468 loads color data only during the blue write cycle. To read the color palettes, the MPU performs the normal (red, green, blue) read cycles from all three RAMDACs simultaneously. The red Bt468 outputs color data only during the the red read cycle, the green Bt468 outputs color data only during the green read cycle, and the blue Bt468 outputs color data only during the blue read cycle. External circuitry must decode when the MPU is reading or writing to the color palettes and assert CE* to all three Bt468s simultaneously. Single-Channel RAMDAC Operation The Bt468 may be configured (via command register_2) to be a single-channel RAMDAC, enabling three Bt468s to be used in parallel for a 24-bit true-color system. The Bt468s share a common 8-bit data bus (DO-D7). WW.rn.o CE' DO • D7 (READ) DO· D7 (WRTI1l) ~~__v_AUD ____--,)(~_________________________________________________ \'-------~/ ------------« DATAOUf(RJW = 1) _____________.....iX Figure 1. DATA 1N (RJW= 0) )>----- x'--____ MPU Read/Write Timing. RAMDACs 4 • 329 Bt468 Circuit Description (continued) Frame Buffer Interface To enable pixel data to be transferred from the frame buffer at TTL data rates, the Bt468 incorporates internal latches and multiplexers. As illustrated in Figure 2, on the rising edge of LD*, sync and blank information, color, and overlay information, for eight consecutive pixels are latched into the device. Note that with this configuration, the sync and blank timing will be recognized only with eight pixel resolution. Typically, the LD* signal is used to clock external circuitry to generate the basic video timing and to clock the video DRAMs. Typically, the Bt468 outputs color information each clock cycle based on the (A} inputs, followed by the (B} inputs, etc., until all eight pixels have been output, at which point the cycle repeats. The overlay inputs may have pixel timing, facilitating the use of additional bit planes in the frame buffer to control overlay selection on a pixel basis, or they may be controlled by external circuitry. To simplify the frame buffer interface timing, LD'" may be phase-shifted, in any amount, relative to CLOCK. This enables the LD* signal to be derived by externally dividing CLOCK by eight, independent of the propagation delays of the LD'" generation logic. As a result, the pixel and overlay data are latched on the rising edge of LD"', independent of the clock phase. Internal logic maintains an internal LOAD signal, synchronous to CLOCK, and is guaranteed to follow the LD* signal by at least one, but not more than six, clock cycles. This LOAD signal transfers the latched pixel and overlay data into a second set of latches, which are then internally multiplexed at the pixel clock rate. Only one rising edge of LD* should occur every eight clock cycles. Otherwise, the internal LOAD generation circuitry assumes it is not locked onto the LD* signal, and will continuously attempt to resynchronize itself to LD*. po.P7 (A·HI. 0L0·OL3 (A·HI. SYNC". BLANK" lOR. 100, lOB, I'LL CLOCK Figure 2. 4 - 330 SECTION 4 Video Input/Output Timing. Bt468 Circuit Description (continued) Read and Blink Masking Pixel Panning Each clock cycle, 8 bits of color information (PO-P7) and 4 bits of overlay information (OLO-OL3) for each pixel are processed by the read mask, blink mask, and command registers. Through the use of the control registers, individual pixel and overlay inputs may be enabled or disabled for display, and/or blinked at one of four blink rates and duty cycles. To support pixel panning, command register_I specifies by how many clock cycles to pan. To ensure that a color change due to blinking does not occur during the active display time (Le., in the middle of the screen), the Bt468 monitors the SYNC* and BLANK* input to determine vertical retrace intervals (any BLANK* pulse longer than 256 LD* cycles). If I-pixel panning is specified, pixel (B) will be first, followed by pixel {C), etc. Pixel {A) will have been processed during the last clock cycle of the blanking interval, and will not be seen on the display screen. At the end of the active display line, pixel {A) will be output. Pixels (B) through (H) will be output during the blanking interval, and will not be seen on the display screen. The processed pixel data is then used to select which color palette entry or overlay register is to provide color information. Note that PO is the LSB when addressing the color palette RAMs, and OLO is the LSB when addressing the overlay palette RAM. Table 2 illustrates the truth table used for color selection. If O-pixel panning is specified, pixel (A) is output first, followed by pixel (B), etc., until all eight pixels have been output, at which point the cycle repeats. The process is similar for panning by two to seven pixels. Note that when a panning value other than 0 pixels is specified, valid pixel data must be loaded into the Bt468 during the first LD* cycle that BLANK* is a logical zero. The PO-P7 and OLO-OL3 inputs are all panned. Cursor position is also panned. If the user desires to keep the cursor position the same relative to the edge of the display, the X register of the cursor position should be updated at the same time the pixel panning register is updated. Panning is done by delaying the SYNC* and BLANK* signals an additional one to seven clock cycles. RAMDACs 4 • 331 - Bt468 Circuit Description (continued) (0,0) enables the color palette RAM and overlay RAM to be selected as normal. Each "plane" of cursor information may also be independently enabled or disabled for display via the cursor command register (bits CR41 and CR46). On-Chip Cursor Operation The Bt468 has an on-chip, three-color, 64 x 64 pixel, user-defInable cursor. The cursor operates only with a noninterlaced video system. The cursor pattern and color may be changed by changing the contents of the cursor RAM. Either the cursor color registers, color palette RAM, or overlay RAM provides 24 bits of color information during the appropriate clock cycle, depending on the cursor pattern values. The pattern for the cursor is provided by the cursor RAM, which may be accessed by the MPU at any time. Cursor positioning is done via the cursor (x,y) register. Note that the Bt468 expects (x) to increase going right, and (y) to increase going down, as seen on the display screen. The cursor (x) position is relative to the fIrst rising edge of LD* following the falling edge of SYNC*. The cursor (y) position is relative to the first falling edge of SYNC* that is after a vertical sync has been detected. Vertical sync is detected as the second falling edge during blank. The cursor is centered about the value specifIed by the cursor (x,y) register. Thus, the cursor (x) register specifIes the location of the 31st column of the 64 x 64 array (assuming the columns start with 0 for the left-most pixel and increment to 63). Similarly, the cursor (y) register specifies the location of the 31st row of the 64 x 64 array (assuming the rows start with o for the top-most pixel and increment to 63). (See Figure 3.) The resetting of the Bt468 to an eight-cycle pipeline delay is required for proper cursor pixel alignment. Three Color 64 x 64 Cursor The 64 x 64 x 2 cursor RAM provides 2 bits of cursor information every clock cycle during the 64 x 64 cursor window, selecting the appropriate cursor color register as follows: planel planeO cursor color 0 0 1 1 0 1 0 1 cursor not displayed cursor color register 1 cursor color register 2 cursor color register 3 HSYNC· aJRSOR(X.y) _ _--f---t~-------p RBOISTIlR 64.64 aJRSOR DISPLAY SCREEN AREA Figure 3. 4 - 332 SECTION 4 Cursor Positioning. Bt468 Circuit Description (continued) Cross Hair Cursor Cursor positioning for the three-color cross hair cursor is also done through the cursor (x,y) register. The intersection of the cross hair cursor is specified by the cursor (x,y) register. If the thickness of the cross hair cursor is greater than one pixel, the center of the intersection is the reference position. During times that cross hair cursor information is to be displayed, the cursor command register (bits CR45 and CR44) is used to specify the color of the cross hair cursor. CR45 CR44 cross hair color 0 0 1 1 0 1 0 1 cross hair not displayed cursor color register 1 cursor color register 2 cursor color register 3 If a full-screen cross hair cursor is desired, the window (x,y) registers should contain $0000 and the window width and height registers should contain $OFFF. (See Figure 4.) .. HSYNC" ~ J---X The cross hair cursor is limited to being displayed within the cross hair window, which is specified by the window (x,y), window width, and window height registers. Since the cursor (x,y) register must specify a point within the window boundaries, It is the responsibility of the software to ensure that the cursor (x,y) register does not specify a point outside of the cross hair cursor window. CROSS HAIR CURSOR--,- I r----+--~~------~ Y ~w--,-.....i.._.. _................... .J CURSOR (X.V) REGISTER DISPLAY SCREEN CROSS HAIR WINDOW Figure 4. Cross Hair Cursor Positioning. RAMDACs 4 - 333 Bt468 Circuit Description (continued) Dual Cursor Positioning The resetting of the Bt468 to an eight cycle pipeline delay is required for proper cursor pixel alignment. Both the user-definable cursor and the cross hair cursor may be enabled for display simultaneously, enabling the generation of custom cross hair cursors. Both cursor planes utilize the same cursor (x,y) registers. As previously mentioned, the cursor (x,y) register specifies the location of bit (31, 31) of the cursor RAM. As the user-defmable cursor contains an even number of pixels in the horizontal and vertical direction, it will be one pixel off from being truly centered about the cross hair cursor. X Windows Cursor Mode In the X Windows mode, plane! of the cursor RAM is a cursor display enable and planeO of the cursor RAM selects either cursor color 2 or 3. The operation is as follows: plane 1 planeO Selection 0 0 1 0 1 0 1 no cursor no cursor cursor color 2 cursor color 3 1 Figure 5 illustrates displaying the dual cursors. In the 64 x 64 pixel area in which the user-definable cursor would be displayed, each plane of the 64 x 64 cursor may be individually logically ORed or excIusive-ORed with the cross hair cursor information. Thus, the color of the displayed cursor will be dependent on the cursor pattern, whether they are logically ORed or XORed, and the individual cursor display enable and blink enable bits. Refer to Figure 9 as to the organization of the cursor RAM while in the X Windows mode. Note that if the cursor is configured for X Windows mode, the cross hair cursor will not be displayed. Figure 6 shows the equivalent cursor generation circuitry. CROSSIIAIR CURSOR (X.Y) REGISTER 64.64 DISPLAY SCREEN CURSOR AREA CROSS HAIR WINDOW Figure 5. 4 - 334 SECTION 4 Dual Cursor Positioning. Bt468 Circuit Description (continued) Video Generation The varying output current from the D/A converters produces a corresponding voltage level. which is used to drive the CRT monitor. Tables 3 and 4 detail how the SYNC* and BLANK* inputs modify the output levels. Every clock cycle. the selected 24 bits of color information are presented to the three 8-bit D/A converters. The SYNC* and BLANK* inputs. pipelined to maintain synchronization with the pixel data. add appropriately weighted currents to the analog outputs. producing the specific output levels required for video applications. as illustrated in Figures 7 and 8. Command registec2 specifies whether a 0 IRE or 7.5 IRE blanking pedestal is to be generated. and whether or not sync information is to be encoded on the video output. A 0 IRE pedestal will force the black level and the blank level to be the same. The D/A converters on the Bt468 use a segmented architecture in which bit currents are routed to either the current output or GND by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabilizes the full-scale output current against temperature and power supply variations. The Bt468 can drive either doubly terminated 50 n or 75 n coax directly. If a 50 n double termination is used. then a typical RSET value is 348 n for a 7.5 IRE blanking pedestal or 332 n for a 0 IRE blanking pedestal. For a 75 n double termination. a typical RSET is 523 n for a 7.5 IRE blanking pedestal and 495 n for a 0 IRE blanking pedestal. Cursor 1. CursorO CR05 OLO-OL3 PO-P7 Addressed by frame buffer 11 10 01 x x x $x $x $x $xx $xx $xx cursor color 3 cursor color 2 cursor co lor 1 00 x $F $xx overlay color 15 : : : : : 00 00 x 1 $1 $0 $xx $xx overlay color 1 overlay color 0 00 00 0 0 $0 $0 $00 $01 RAM location $00 RAM location $01 : : : : : 00 0 $0 $FF RAM location $FF Note: Refer to Figure 6 for generation of Cursor 1 and CursorO control bits. Table 2. Palette and Overlay Select Truth Table. RAMDACs 4 - 335 .. Bt468 Circuit Description (continued) 64X64X2 aJRSORRAM PLANE! CURSOR! CR47 CR4S CURSOR 0 CROSS HAIR CR44 CR43 BLINK --------------------------~ ---:::::j}>--________________________-j__---l CR40 CR2! --------------------------------------~ Figure 6. 4 - 336 SECTION 4 Cursor Control Circuitry. Bt468 Circuit Description (continued) RED. BLUE GREEN MA V MA V 28.S6 0.714 40.00 1.000 -r-----,.r--------------,:---- 2.16 0.054 13.6 0.340 + - - - - - - \ - - - - - / - - - - - - - - - BLACK LEVEL 0.00 0.000 11.44 0.286 7.5JRE + _____ --I_-.---.-_.L..________ 0.00 0.000 WHITE LEVEL BLANK LEVEL 40JRE -1-_ _ _ _ _ _ _....1...--1.._ _ _ _ _ _ _ _ _ _ SYNC LEVEL Note: 50 n doubly terminated load, RSET = 348 levels. Figure 7. n, VREF = 1.235 V. RS-343A levels and tolerances assumed on all Composite Video Output Waveform (SETUP Description WHITE DATA DATA-SYNC BlACK BLACK-SYNC BLANK SYNC 100 IOR,IOB (rnA) (rnA) 40 data + 13.6 data + 2.16 13.6 2.16 11.44 0 28.56 data + 2.16 data + 2.16 2.16 2.16 0 0 7.5 IRE). CSYNC* BLANK* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1. 0 0 $FF data data $00 $00 $xx $xx Note: Typical with full-scale lOG = 40 rnA. RSET = 348 n, VREF = 1.235 V. Table 3. Video Output Truth Table (SETUP 7.5 IRE). RAMDACs 4 ·337 .. Bt468 Circuit Description (continued) RED.BWE GREEN MA V MA V 27.90 0.698 40.00 1.000 ~----~~--------------------~~------wmmill~ 0.00 0.000 12.08 0.302 -t-------------1--...,---r-.L----------------- BLACK/BLANK ill~ 0.00 0.000 431RB --L-______________ ...L..~ ___________________ SYNC illVEL Note: 50 n doubly terminated load, RSET = 332 n, VREF = 1.235 V. RS-343A levels and tolerances assumed on all levels. Figure 8. Composite Video Output Waveform (SETUP 100 IOR,IOB (rnA) (rnA) 40 data + 12.1 data 12.1 0 12.1 0 27.9 data data 0 0 0 0 Description WHITE DATA DATA-SYNC BLACK BLACK - SYNC BlANK SYNC o IRE). CSYNC* BLANK* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: Typical with full-scale lOG = 40 rnA. RSET = 332 n, VREF = 1.235 V. Table 4. 4 - 338 SECTION 4 Video Output Truth Table (SETUP o IRE). BnxKtree~ Bt468 Internal Registers Command Register_O This register may be written to or read by the MPU at any time and is not initialized. CROO corresponds to data bus bit DO. CR07 reserved (logical one) CR06 reserved (logical zero) CR05 Overlay 0 enable (0) use color palette RAM (1) use overlay color 0 CR04 reserved (logical zero) CR03, CR02 Blink rate selection (00) (01) (10) (11) CROI, CROO 16 16 32 64 on, on, on, on, 48 16 32 64 off (25(15) off (SO/50) off (SO/50) off (SO/50) When in the normal overlay mode, this bit specifies whether to use the color palette RAM or overlay color 0 to provide color information when the overlay inputs are $0. See Table 2. These 2 bits specify the blink rate cycle time and duty cycle, and are specified as the number of vertical retrace intervals. The numbers in parentheses specify the duty cycle (% on/off). reserved (logical zero) RAMDACs 4 ·339 .. Bt468 Internal Registers (continued) Command Register_1 This register may be written to or read by the MPU at any time and is not initialized. CRIO corresponds to data bus bit DO. CR17-CR15 Pan select (000) (001) (010) (011) (100) (101) (110) (111) CR14-CR10 4 - 340 o pixels 1 pixel 2 pixels 3 pixels 4 pixels 5 pixels 6 pixels 7 pixels {pixel A} {pixeIB} {pixel C} {pixeID} {pixel E} {pixel P} {pixel G} {pixeIH} reserved (logical zero) SECTION 4 These bits specify the number of pixels to be panned. These bits are typically modified only during the vertical retrace interval. The {pixel A} indicates pixel A will be output first following the blanking interval, {pixel B} indicates pixel B will be output firSt, etc. Bt468 Internal Registers (continued) Command Register_2 This register may be written to or read by the MPU at any time and is not initialized. CR20 corresponds to data bus bit DO. CR27 Sync Enable (0) disable sync (1) enable sync This bit specifies whether sync information is to be output onto the lOG (logical one) or not (logical zero). Pedestal enable This bit specifies whether a 0 or 7.5 IRE blanking pedestal is to be generated on the video outputs. 0 IRE specifies that the black and blank levels are the same. CR26 (0) 0 IRE pedestal (1) 7.5 IRE pedestal CR25, CR24 Load palette RAM select (00) (01) (10) (11) CR23 normal redRAMDAC green RAMDAC blueRAMDAC PLLselect If (00) is specified, color data is loaded into the Bt468 using three write cycles (red, green, and blue), and color data is output using three read cycles (red, green, and blue). Modes (01), (10), and (11) enable the Bt468 to emulate a single-channel RAMDAC using only the green channel (lOG). This bit specifies whether the PLL output uses SYNC" or BLANK* for generating PLL information. (0) SYNC" (1) BLANK" CR22 reserved (logical zero) CR21 X Windows cursor select (0) normal cursor (1) X Windows cursor CR20 Test mode select (0) signature analysis test (1) data strobe test This bit specifies whether the cursor is to operate normally (logical zero) or in an X Windows compatible mode (logical one). This bit determines the method of high-speed test used. The signature analysis registers are used to hold the test result for both test methods. RAMDACs 4 - 341 .. Bt468 Internal Registers (continued) ID Register This 8-bit register may be read by the MPU to determine the type of RAMDAC being used in the system. The value is different for each RAMDAC. For the Bt468, the value read by the MPU will be $4F. Data written to this register is ignored. Pixel Read Mask Register The 8-bit pixel read mask register is used to enable (logical one) or disable (logical zero) a bit plane from addressing the color palette RAM. Each register bit is logically ANDed with the corresponding bit plane input. This register may be written to or read by the MPU at any time and is not initialized. DO corresponds to PO. Pixel Blink Mask Register The 8-bit pixel blink mask register is used to enable (logical one) or disable (logical zero) a bit plane from blinking at the blink rate and duty cycle specified by command register_O. This register may be written to or read by the MPU at any time and is not initialized. DO corresponds to PO. Overlay Read Mask Register The 8-bit overlay read mask register is used to enable (logical one) or disable (logical zero) an overlay plane from addressing the overlay palette RAM. DO corresponds to overlay plane 0 (OLO (A-H)) and D3 corresponds to overlay plane 3 (OL3 (A-H}). Bits DO-D3 are logically ANDed with the corresponding overlay plane input. D4-D7 are always a logical zero. This register may be written to or read by the MPU at any time and is not initialized. Overlay Blink Mask Register The 8-bit overlay blink mask register is used to enable (logical one) or disable (logical zero) an overlay plane from blinking at the blink rate and duty cycle specified by command registecO. DO corresponds to overlay plane 0 (OLO (A-H)) and D3 corresponds to overlay plane 3 (OL3 (A-H)). In order for an overlay plane to blink, the corresponding bit in the overlay read mask register must be a logical one. D4-D7 are always a logical zero. This register may be written to or read by the MPU at any time and is not initialized. Revision Register (Revision B only) This 8-bit is a read-only register, specifying the revision of the Bt468. The four most significant bits signify the revision letter B, in hexidecimal form. The four least significant bits do not represent any value and should be ignored. Data written to this register is ignored. Since Revision A device does not have a revision register, address $0220 will contain the last data read to or written from the internal bus. 4 - 342 SECTION 4 Bt468 Internal Registers (continued) Red, Green, and Blue Output Signature Registers Signature Operation These three 8-bit signature registers (one each for red, green, and blue) may be read by the MPU while BLANK* is a logical zero. While BLANK* is a logical one, Ihe signatures are being acquired. The MPU may read from or write to the signature registers while BLANK* is a logical zero to load the seed value. By loading a test display into the frame buffer, a deterministic value for the red, green, and blue signature registers will be read from these registers if all circuitry is working properly. Refer to the Application Information test register section for more information. Data Strobe Operation If command bit CR20 selects "data strobe testing," the operation of the signature registers changes slightly. Rather than determining the signature, they capture red, green, and blue data being presented to the three DACs. Each LD* cycle, the three signature registers capture the color values being presented to the DACs. As only one of the (A-E) pixels can be captured each LD* cycle, DO-D2 of the test register are used to specify which pixel (A-E) is to be captured. RAMDACs 4 - 343 - Bt468 Internal Registers (continued) Test Register This 8-bit register is used for testing the Bt468. DO-D2 are used to specify which pixel input to use, as follows: D2-DO Selection 000 001 010 011 100 101 110 111 pixel pixel pixel pixel pixel pixel pixel pixel A B C D E F G H D3-D7 are used to compare the analog RGB outputs to each other and to a 145 mV reference. This enables the MPU to determine whether the CRT monitor is connected to the analog RGB outputs or not, and whether the DACs are functional. D7 D6 D5 D4 D3 D7.D6 ~------. 0 Q 03 OS. D4 red select green select blue select 145 mV ref. select result CURSOR _ _ _ _ _..J D7-D4 0000 1010 1001 0110 0101 IfD3= 1 normal operation red DAC compared to blue DAC red DAC compared to 145 mV reference green DAC compared to blue DAC green DAC compared to 145 mVreference IfD3=O - - red> blue red> 145mV green> blue green> 145 mV blue > red red < 145mV blue> green green < 145 mV The table above lists the valid comparison combinations. A logical one enables that function to be compared; the result is D3. The comparison result is strobed into D3 on the left edge of the 64 x 64 cursor area. The output levels of the DACs should be constant for 5 IJ.S before the left edge of the cursor. For normal operation, D3-D7 must be a logical zero. 4·344 SECTION 4 Bt468 Internal Registers (continued) Cursor Command Register This command register is used to control various cursor functions of the Bt468. It is not initialized, and may be written to or read by the MPU at any time. CR40 corresponds to data bus bit DO. CR47 64 x 64 cursor planel display enable Specifies whether planel of the 64 x 64 cursor is to be displayed (logical one) or not (logical zero). (0) disable plane I (I) enable plane I CR46 64 x 64 cursor planeO display enable Specifies whether planeO of the 64 x 64 cursor is to be displayed (logical one) or not (logical zero). (0) disable planeO (I) enable planeO CR45 Cross hair cursor plane I display enable Specifies whether planel of the cross hair cursor is to be displayed (logical one) or not (logical zero) . (0) disable plane I (1) enable plane I CR44 Cross hair cursor planeO display enable (0) disable planeO Specifies whether planeO of the cross hair cursor is to be displayed (logical one) or not (logical zero). Note that planeO and planel contain the same information. (1) enable planeO CR43 Cursor format (0) XOR (1) OR CR42, CR41 Cross hair thickness (00) (01) (10) (11) CR40 I 3 5 7 pixel pixels pixels pixels Cursor blink enable (0) blinking disabled (I) blinking enabled If both the 64 x 64 cursor and the cross hair cursor are enabled for display, this bit specifies whether the contents of the cursor RAM are to be logically exclusive-ORed (logical zero) or ORed (logical one) with the cross hair cursor. This bit specifies whether the vertical and horizontal thickness of the cross hair is one, three, five, or seven pixels. The segments are centered about the value in the cursor (x,y) register. This bit specifies whether the cursor is to blink (logical one) or not (logical zero). If both cursors are displayed, both will blink. The blink rate and duty cycle are as specified by command register_O. RAMDACs 4 - 345 .. Bt468 Internal Registers (continued) Cursor (x,y) Registers These registers are used to specify the (x,y) coordinate of the center of the 64 x 64 pixel cursor window, or the intersection of the cross hair cursor. The cursor (x) register is made up of the cursor (x) low register (CXLR) and the cursor (x) high register (CXHR); the cursor (y) register is made up of the cursor (y) low register (CYLR) and the cursor (y) high register (CYHR). They are not initialized and may be written to or read by the MPU at any time. The cursor position is not updated until the vertical retrace interval after CYHR has been written to by the MPU. CXLR and CXHR are cascaded to form a 12-bit cursor (x) register. Similarly, CYLR and CYHR are cascaded to form a 12-bit cursor (y) register. Bits D4-D7 of CXHR and CYHR are always a logical zero. Cursor (x) Low (CXLR) Cursor (x) High (CXHR) Data Bit D3 D2 D1 DO D7 D6 D5 D4 D3 D2 D1 DO X Address Xl1 XIO X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Cursor (y) High (CYHR) Cursor (y) Low (CYLR) Data Bit D3 D2 D1 DO D7 D6 D5 D4 D3 D2 D1 DO Y Address Yl1 YlO Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 YI YO The cursor (x) value to be written is calculated as follows: Cx =desired display screen (x) position + H-72 where H = number of pixels between the first rising edge of CLOCK following the falling edge of SYNC· to active video. Values from $0000 to $OFFF may be written into the cursor (x) register. The cursor (y) value to be written is calculated as follows: Cy = desired display screen (y) position + V-32 where V = number of scan lines from the first falling edge of SYNC· that is two or more clock cycles after vertical sync to active video. Values from $OFCO (-64) to $OFBF (+4031) may be loaded into the cursor (y) register. The negative values ($OFCO to $OFFF) are used in situations where V < 32, and the cursor must be moved off the top of the screen. 4·346 SECTION 4 Bt468 Internal Registers (continued) Window (x,y) Registers These registers are used to specify the (x,y) coordinate of the upper left comer of the cross hair cursor window. The window (x) register is made up of the window (x) low register (WXLR) and the window (x) high register (WXHR); the window (y) register is made up of the window (y) low register (WYLR) and the window (y) high register (WYHR). They are not initialized and may be written to or read by the MPU at any time. The window position is not updated until the vertical retrace interval after WYHR has been written to by the MPU. WXLR and WXHR are cascaded to form a l2-bit window (x) register. Similarly, WYLR and WYHR are cascaded to form a l2-bit window (y) register. Bits D4-D7 of WXHR and WYHR are always a logical zero. Window (x) High (WXHR) Window (x) Low (WXLR) Data Bit D3 D2 D1 DO D7 D6 D5 D4 D3 D2 Dl DO X Address Xll XlO X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Window (y) High (WYHR) Window (y) Low (WYLR) Data Bit D3 D2 Dl DO D7 D6 D5 D4 D3 D2 Dl DO Y Address Yll YIO Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Yl YO The window (x) value to be written is calculated as follows: Wx = desired display screen (x) position + H-40 where H = number of pixels between the first rising edge of CWCK following the falling edge of SYNC· to active video. The window (y) value to be written is calculated as follows: Wy = desired display screen (y) position + V where V = number of scan lines from the first falling edge of SYNC* that is two or more clock cycles after vertical sync to active video. Values from $0000 to $OFFF may be written to the window (x) and window (y) registers. A full-screen cross hair is implemented by loading the window (x,y) registers with $0000 and the window width and height registers with $OFFF. RAMDACs 4 - 347 .. Bnxj{tree® Bt468 Internal Registers (continued) Window Width and Height Registers These registers are used to specifY the width and height (in pixels) of the cross hair cursor window. The window width register is made up of the window width low register (WWLR) and the window width high register (WWHR); the window height register is made up of the window height low register (WHLR) and the window height high register (WHHR). They are not initialized and may be written to or read by the MPU at any time. The window width and height are not updated until the vertical retrace interval after WHHR has been written to by the MPU. WWLR and WWHR are cascaded to fonn a 12-bit window width register. Similarly, WHLR and WHHR are cascaded to fonn a 12-bit window height register. Bits D4-07 of WWHR and WHHR are always a logical zero. Window Width High (WWHR) Window Width Low (WWLR) OataBit 03 02 01 DO D7 D6 05 D4 03 D2 01 DO X Address Xll XI0 X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Window Height High (WHHR) Window Height Low (WHLR) OataBit 03 02 D1 DO D7 D6 05 D4 D3 02 01 DO Y Address Yll YI0 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Yl YO The actual window width is 16 pixels more than the value specified by the window width register. The actual window height is 16 pixels more than the value specified by the window height register. Therefore, the minimum window width is 16 pixels, and the minimum window height is 16 pixels. Values from $0000 to $OFFF may be written to the window width and height registers. 4· 348 SECTION 4 Bt468 Internal Registers (continued) Cursor RAM This 64 x 64 x 2 RAM is used to define the pixel pattern within the 64 x 64 pixel cursor window. and is not initialized. The cursor RAM should not be written to by the MPU during the horizontal sync time and for the two LO* cycles after the end of the horizontal sync. The cursor RAM may otherwise be written to or read by the MPU at any time without contention. If writing to the cursor RAM asynchronously to horizontal sync. it is recommended that the cursor be positioned off-screen in the Y direction (write to the cursor (y) registers and wait for the vertical sync interval to move the cursor off-screen). write to the cursor RAM. then reposition the cursor back to the original position. An alternative is to perform a write then read sequence. and if the correct cursor RAM data was not written. perform another write then read sequence. Since the contention occurs only during horizontal sync at the Y locations coincident with the cursor. the second write/read sequence bypasses the window of time when cursor RAM is in contention. ~uring MPU accesses to the cursor RAM. the address register is used to address the cursor RAM. Figure 9 illustrates the internal format of the cursor RAM. as it appears on the display screen. Addressing starts at location $400 as shown in Table 1. Note that in the X Windows mode. plane! serves as a cursor display enable while planeD selects one of two cursor colors (if enabled). Note: in both modes of operation. planel = 07. 05. 03. 01; planeD = 06. 04. 02. DO. UPPIlRLEFr CORNER AS OISPLAYEO ON SCREEN . I 64 PIXELS BYfE$400 BYfES401 BYfES40F BYfES410 BYfES411 BYfES41F BYfES7PO BYfES7Fl BYfES7FF 64 PIXELS 1 / 4 PIXELS ~ 107,06105,04103,02101,00 1 Normal Mode: 00 =color palette or overlay RAM 01 = cursor color 1 10 = cursor color 2 11 = cursor color 3 X·Windows Mode: 00 = color palette or overlay RAM 01 = color palette or overlay RAM 10 = cursor color 2 11 = cursor color 3 Figure 9. Cursor RAM as Displayed on the Screen. RAMDACs 4·349 Bt468 Pin Descriptions Pin Name Description BLANK* Composite blank control input (fTL compatible). A logical zero drives the analog output to the blanking level, as illustrated in Tables 3 and 4. It is latched on the rising edge of LD*. When BLANK* is a logical zero, the pixel and overlay inputs are ignored. SYNC* Composite sync control inputs (fTL compatible). A logical zero typically switches off a 40 IRE current source on the lOG output (see Figures 7 and 8). SYNC* does not override any other control or data input, as shown in Tables 3 and 4; therefore, it should be asserted only during the blanking interval. SYNC* is latched on the rising edge of LD*. LD* Load control input (TTL compatible). The PO-P7 {A-H}, OLO-OL3 {A-H}, BLANK*, and SYNC* inputs are latched on the rising edge of LD*. LD*, while it is 1/8 of CLOCK, may be phase-independent of the CLOCK and CLOCK* inputs. LD* may have any duty cycle, within the limits specified by the AC Characteristics section. PO-P7 {A-H} Pixel select inputs (TTL compatible). These inputs are used to specify, on a pixel basis, which location of the color palette RAM is to be used to provide color information (see Table 2). Eight consecutive pixels (8 bits per pixel) are input through this port. They are latched on the rising edge of LD*. Unused inputs should be connected to GND. Note that typically the {A} pixel is output first, followed by the {B} pixel, etc., until all eight pixels have been output, at which point the cycle repeats. OLD-OL3 {A-H} Overlay select inputs (TTL compatible). These inputs are latched on the rising edge of LD* and, in conjunction with CR05 in command register_O, specify which palette is to be used for color information, as illustrated in Table 2. When accessing the overlay palette RAM, the PO-P7 {A-H} inputs are ignored. Overlay information (up to four bits per pixel) for eight consecutive pixels are input through this port. Unused inputs should be connected to GND. lOR, lOG, lOB Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a doubly-terminated 50 n coaxial cable (Figure 10). All outputs, whether used or not, should have the same output load. PLL Phase lock loop output current. This high-impedance current source is used to enable multiple Bt468s to be synchronized with sub-pixel resolution when used with an external PLL. A logical one for SYNC* or BLANK* (as specified by CR23 in command register_2) results in no current being output onto this pin, while a logical zero results in the following current being output: PLL (rnA) = 3,227 * VREF (V) I RSET (n) If sub-pixel synchronization of multiple devices is not required, this output should be connected to GND (either directly or through a resistor up to 150 n). CaMP 4· 350 Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 jlF ceramic capacitor must be connected between this pin and VAA (Figure 10). Connecting the capacitor to VAA rather than to GND provides the highest possible power supply noise rejection. The CaMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum and maximize the capacitor's self-resonant frequency to be greater than the LD* frequency. Refer to PC Board Layout Considerations for critical layout criteria. SECTION 4 Bt468 Pin Descriptions (continued) Pin Name Description VM Analog power. All VAA pins must be connected. GND Analog ground. All GND pins must be connected. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal (Figure 10). Note that the IRE relationships in Figures 7 and 8 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on lOG is: RSET (0) = Kl * VREF (V) I 100 (rnA) The full scale output current on lOR and lOB for a given RSET is: lOR, lOB (rnA) = K2 * VREF (V) I RSET (0) where Kl and K2 are defined as: Setup 100 IOR,lOB 7.5 IRE Kl = 11,294 K2 = 8,067 oIRE Kl = 10,684 K2 = 7,457 VREF Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 10, must supply this input with a 1.235 V (typical) reference. The use of a resistor network to generate the reference is not recommended, as any low-frequency power supply noise on VREF will be directly coupled onto the analog outputs. A 0.1 ~F ceramic capacitor is used to decouple this input to VAA, as shown in Figure 10. IF VAA is excessively noisy, better performance may be obtained by decoupling VREF to GND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. ClOCK, ClOCK* Clock inputs. These differential clock inputs are designed to be driven by ECL logic configured for single supply (+5 V) operation. The clock rate is typically the pixel clock rate of the system. CE* Chip enable control input (TTL compatible). This input must be a logical zero to enable data to be written to or read from the device. During write operations, data is internally latched on the rising edge of CE* (Figure 1). Care should be taken to avoid glitches on this edge-triggered input. R/W Read/write control input (TTL compatible). To write data to the device, both CE* and R/W must be a logical zero. To read data from the device, CE* must be a logical zero and R/W must be a logical one. R/W is latched on the falling edge of CE*. See Figure 1. CO,Cl Command control inputs (TTL compatible). CO and Cl specify the type of read or write operation being performed, as illustrated in Table 1. They are latched on the falling edge of CE*. DO-D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. RAMDACs 4 - 351 Bnxj{tree® Bt468 Pin Descriptions (continued) Signal Pin Number Signal Pin Number Signal Pin Number BLANK* SYNC* LD* KI P5A P5B P5C P5D P5E P5F P5G P5H D15 EI5 FI5 FI4 GI4 GI5 II4 HI5 Ol2A OL2B OL2C OL2D Ol2E OL2F O12G OL2H PI P2 N2 NI MI l.3 12 M2 P6A P6B P6C P6D P6E P6F P6G P6H BI5 BI4 CI4 CI5 EI4 E13 F13 D14 Ol.3A Ol.3B Ol.3C Ol.3D Ol.3E Ol.3F Ol.3G Ol.3H R4 N5 N4 P4 R2 R3 P3 RI P7A P7B P7C P7D P7E P7F P7G P7H AI2 Cll CI2 BI2 AI4 A13 Bl3 Al5 DO B9 B8 AIO A9 CIO BIO Bll All OUJA OLOB OLOe OUlD OLOE OLOF OLOG OLOH D1 D3 D2 BI CI C2 Al OLlA OLlB OLlC OLID OLlE OLlF OLlG OLlH G2 HI FI GI F3 F2 E2 EI lOR lOG lOB A8 B7 A6 PLL A4 CE* R/W CO CI B2 B3 B5 C5 12 K3 CLOCK II CLOCK* K2 POA POB POC POD POE POF POO POH P7 R7 R6 PIA PIB PIC PID PIE PIF PIG PIH RIO PIO P9 N9 R8 R9 N8 P8 P2A P2B P2C P2D P2E P2F P2G P2H P13 R13 RI2 PI2 Pll Nll NIO Rll N7 N6 P6 P5 R5 P3A P3B P3C P3D P3E P3F P3G P3H Ml3 Ml4 Pl5 Nl5 NI4 RI5 RI4 Pl4 P4A P4B P4C P4D P4E P4F P4G P4H KI5 115 K13 Kl4 LI4 Ll5 MI5 Ll3 COMP FSADJUST VREF C6 4· 352 A3 B6 SECTION 4 E3 D1 D2 D3 D4 D5 D6 D7 VM VM VM VM VM VM VM VM VM VM VM GND GND GND GND GND GND GND GND GND GND GND reserved reserved reserved C3 C7 C8 CI3 D4 GI3 H3 H13 13 N3 NI3 AS A7 C4 C9 DI3 G3 H2 HI4 113 M3 NI2 A2 B4 Ll Bt468 Pin Descriptions (continued) / LS Pm RilL RD !'SA PSB PSC P5F PSH I'IB PIA NF NG P.lD P3C P3F 14 P7E Rill P6C P6H P6Il P!D PSE GND PSG I'ID !'IE P3B P3E P3H P3G 13 P7F PIG VM GND l'Q' F6G VM VM GND l'IC P4H P3A VM PlA P2B 12 YlA PlD YlC GND I'D P2C 11 DI D6 YlB P1F P2E Pm 10 III D6 ])I PlG PlB PIA 1l! m GND PID PIC PIP lOR D1 VM PIG pm - PIE !'(F roc Bt468 (TOP VIEW) GND IlG VM FID lOB VREF CXJMP POE GND OJ C1 OL3B FOG POH HL NJC GND VM 0L3C 100 MHz). The designer must take care to minimize skew on the CLOCK and CLOCK* lines. The PLL outputs would not be used and should be connected to GND (either directly or through a resistor up to 150 Q). When using mUltiple Bt468s, each Bt468 should have its own power plane ferrite bead. In addition, a single voltage reference may drive multiple devices; however, isolation resistors are recommended to reduce color channel crosstalk. Each Bt468 must still have its own individual RSET resistor, analog output termination resistors, power supply bypass capacitors, CaMP capacitor, and VREF capacitor. In order to assure that the B t468 has the proper configuration, all of the command registers must be initialized prior to a fixed pipeline reset. Because of this requirement, the power up which occurs prior to initialization of the command registers cannot be used to assure the fixed pipeline. An additional reset is required after command register writes. The resetting of the Bt468 to an eight clock cycle pipeline delay does not reset the blink counter circuitry. Therefore, if the multiple Bt468s are used in paraIIel, the on-chip blink counters may not be synchronized. In this instance, the blink mask register should be $00 and the overlay blink enable bits a logical zero. Blinking may be done under software control via the read mask register and overlay display enable bits. Resetting the Bt468 to an eight clock cycle pipeline delay is required for proper cursor pixel alignment. ESD and Latchup Considerations Setting the Pipeline Delay The pipeline delay of the Bt468, although fixed after a power-up condition, may be anywhere from six to ten clock cycles. The Bt468 contains additional circuitry enabling the pipeline delay to be fixed at eight clock cycles. The Bt438 and Bt439 Clock Generator Chips support this mode of operation when used with the Bt468. To reset the Bt468, it should be powered up, with LD*, CLOCK, and CLOCK* running. Stop the CLOCK and CLOCK* signals with CLOCK high and CLOCK* low for at least three rising edges of LD*. There is no upper limit on how long the device can be held with CLOCK and CLOCK* stopped. Restart CLOCK and CLOCK* so that the first edge of the signals is as close as possible to the rising edge of LD* (the falling edge of CLOCK leads the rising edge of LD* by no more than 1 clock cycle or follows the rising edge of LD* by no more than 1.5 clock cycles). When restarting the clocks, care must be taken to ensure that the minimum clock pulse width is not violated. Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay V AA power to the device. Ferrite beads must only be used for analog power V AA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all V AA pins are at the same potential, and that the V AA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. RAMDACs 4 - 359 Bt468 Application Information (continued) +5V .4 MON\1OR Bt468 PRODI1CI'S 97111 #1 Bt439 +sv FROM BT41i8 Bt468 #2 VAA T O•1 VR1lP I'lL a.OCK a.OCK" !D" VREP 1------. VAA TOol VREP Figure 12. 4 - 360 Generating the Clock Signals for Multiple Bt468s. SECTION 4 Bt468 #3 BnxKtree~ Bt468 Application Information (continued) Test Features 0/ the Bt468 The Bt468 contains two dedicated test registers and an analog output comparator that assist the user in evaluating the performance and functionality of the part. This section is intended to explain the operating usage of these test features. Signature Register (Signature Mode) The signature register, in the active mode, operates with the 24 bits of data that are output from the color palette RAM. These 24-bit vectors represent a single pixel color, and are presented as inputs simultaneously to the red, green, and blue signature analysis registers (SARs), as well as the three on-chip DACs. The SARs act as a 24-bit wide Linear Feedback Shift Register on each succeeding pixel that is latched. It is important to note that the SARs only latch one pixel per "load group." Thus the SARs are operating on only every eighth pixel in the multiplexed modes. The user determines which pixel phase (A, B, C, D, E, F, G, or H) is latched for generating new signatures by setting bits DO-D2 in the Test Register. The Bt468 will only generate signatures while in "active-display" (BLANK* negated). The SARs are available for reading and writing via the MPU port when the Bt468 is in a blanking state (BLANK* asserted). Specifically, it is safe to access the SARs after the DAC outputs are in the blanking state (up to 15 pixel clock periods after BLANK* is asserted). Typically, the user will write a specific 24-bit "seed" value into the SARs. Then, a known pixel stream will be input to the chip, say one scan-line or one frame buffer worth of pixels. Then, at the succeeding blank state, the resultant 24-bit signature can be read out by the MPU. The 24-bit signature register data is a result of the same captured data that is fed to the DACs. Thus, overlay and cursor data validity is also tested using the signature registers. The above process would be repeated with all different pixel phases-A, B, C, etc.,-being selected. It is not simple to specify the algorithm which desceibes the linear feedback shift operation used in the Bt468. The linear feedback configuration is shown in Figure 13. Note that each register internally uses XORs at each input bit (Dn) with the output (result) by one least significant bit (On-I). Experienced users have developed tables of specific seeds and pixel streams and recorded the signatures that result from those inputs applied to "known-good" parts. Note that a good signature from one given pixel stream can be used as the seed for the succeeding stream to be tested. Any signature is deterministically created from a starting seed and the succeeding pixel stream fed to the SARs. Signature Register (Data Strobe Mode) Setting command bit CR20 to "I" puts the SARs into data strobe mode. In this instance, the linear feedback circuits of the SARs are disabled, which stops the SARs from generating signatures. Instead, the SARs simply capture and hold the respective pixel phase that is selected. Any MPU data written to the SARs is ignored. One use, however, is to directly check each pixel color value that is strobed into the SARs. To read out a captured color in the middle of a pixel stream, the user should first freeze all inputs to the Bt468. The levels of most inputs do not matter EXCEPT that CLOCK should be high, and CLOCK* should be low. Then, the user may read out the pixel color by doing three successive MPU reads from the red, green, and blue SARs, respectively. In general, the color read out will correspond to a pixel latched on the previous load. However, due to the pipelined data path, the color may come from an earlier load cycle. To read successive pixels, toggle LD*, pulse the CLOCK pins according to the mux state (eight periods), then hold all pixel-related inputs and perform the three MPU reads as described. This overall process is best done on a sophisticated VLSI semiconductor Tester. RAMDACs 4 - 361 Bt468 Application Information (continued) Analog Comparator The other dedicated test structure in the Bt468 is the analog output comparator. It allows the user to measure the DACs against each other, as well as against a specific reference voltage. Four combinations of tests are selected via the Test Register. With a given setting, the respective signals (DAC outputs or the 145 mY reference) will be continuously input to the comparator. The result of the comparator is latched into the Test Register on each of the 64 scan lines of the 64 x 64 user-defined cursor block (the 64 x 64 cursor must be enabled for display). On each of these 64 scan lines, the capture occurs over one LD* period that corresponds to the cursor (x) position, set by the 12-bit cursor (x) register. Due to the simple design of the comparator, it is recommended that the DAC outputs be stable for 5 ~ before capture. At a display rate of 100 MHz. 5 I1s corresponds to 500 pixels. In this case, the cursor (x) position should be set to well over 500 pixels to ensure an adequate supply of pixels. Furthermore, either the color palette RAM or the pixel inputs (or both) should be configured to guarantee a single continuous output from the DACs under test, up until capture. Typically, users will create screen-wide test bands of various colors. Yarious comparison cases are set up by moving the cursor up and down (by changing the 12-bit cursor (y) register) over these bands. For each test, the result is obtained by reading Test Register bit D3. To obtain a meaningful comparison, the cursor should be located on the visible screen. There is no significance to the cursor pattern data in the cursor RAM. For a visual reference, the capture point actually occurs over the left-most edge of the 64 x 64 cursor block. 00·07 PROMLOOKUPTABLII RO·R7 PROM LOOKIJP TABLII • MPUSARREADBIT Figure 13. 4 - 362 SECTION 4 Signature Analysis Register Circuit. BO·B7 PROMLOOKlJPTABLII Bt468 Application Information (continued) Initializing the Bt468 Load Cursor RAM Pattern Following a power-on sequence, the Bt468 must be initialized. This sequence will configure the Bt468 as follows: 8:1 multiplexed operation no overlays, no blinking, no panning 64 x 64 block cursor, no cross hair cursor sync enabled on lOG, 7.5 IRE blanking pedestal Control Register Initialization CI, CO Write $01 to address register low Write $02 to address register high Write $40 to command register_O Write $00 to command regis tee 1 Write $CO to command registee2 Write $FF to pixel read mask register Write $00 to reserved location Write $00 to pixel blink mask register Write $00 to reserved location Write $00 to overlay read mask register Write $00 to overlay blink mask register Write $00 to reserved location Write $00 to test register 00 01 10 10 10 10 10 10 10 10 10 10 10 Write $00 to address register low Write $03 to address register high Write $CO to cursor command register Write $00 to cursor (x) low register Write $00 to cursor (x) high register Write $00 to cursor (y) low register Write $00 to cursor (y) high register Write $00 to window (x) low register Write $00 to window (x) high register Write $00 to window (y) low register Write $00 to window (y) high register Write $00 to window width low register Write $00 to window width high register Write $00 to window height low register Write $00 to window height high register 00 01 10 10 10 10 10 10 10 10 10 10 10 10 10 Write $00 to address register low Write $04 to address register high Write $FF to cursor RAM (location $000) Write $FF to cursor RAM (location $001) 00 01 10 10 Write $FF to cursor RAM (location $3FF) 10 Color Palette RAM Initialization Write $00 to address register low Write $00 to address register high Write red data to RAM (location $00) Write green data to RAM (location $00) Write blue data to RAM (location $00) Write red data to RAM (location $01) Write green data to RAM (location $01) Write blue data to RAM (location $01) 00 01 11 11 11 11 11 11 Write red data to RAM (location $FF) Write green data to RAM (location $FF) Write blue data to RAM (location $FF) 11 11 11 Overlay Color Palette Initialization Write $00 to address register low Write $01 to address register high Write red data to overlay (location $0) Write green data to overlay (location $0) Write blue data to overlay (location $0) Write red data to overlay (location $1) Write green data to overlay (location $1) Write blue data to overlay (location $1) 00 01 10 10 10 10 10 10 Write red data to overlay (location $F) Write green data to overlay (location $F) Write blue data to overlay (location $F) 10 10 10 Cursor Color Palette Initialization Write $81 to address register low Write $01 to address register high Write red data to cursor (location $0) Write green data to cursor (location $0) Write blue data to cursor (location $0) Write red data to cursor (location $1) Write green data to cursor (location $1) Write blue data to cursor (location $1) Write red data to cursor (location $2) Write green data to cursor (location $2) Write blue data to cursor (location $2) RAMDACs 00 01 10 10 10 10 10 10 10 10 10 4 • 363 Bt468 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage FS ADJUST Resistor Symbol Min Typ Max Units VAA TA RL 4.75 0 5.00 5.25 +70 VREF 1.20 25 1.235 348 1.26 Volts °C Ohms Volts Ohms Min Typ Max Units 6.5 Volts VAA+0.5 Volts +125 +150 +175 °C °C °C 260 °C RSEf Absolute Maximum Ratings Parameter Symbol VAA (measured to GND) Voltage on any Signal Pin· GND-O.5 Analog Output Short Circuit Duration to any Power Supply or Common ISC Ambient Operating Temperature Storage Temperature Junction Temperature TA 'IS TJ Soldering Temperature (5 seconds, 1/4" from pin) TSOL indefinite -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. • This device employs high impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. 4 - 364 SECTION 4 Bt468 DC Characteristics Parameter Analog Outputs Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs (except CLOCK, CLOCK·) Input High Voltage Input Low Voltage Input High Current (Vin =2.4 V) Input Low Cmrent (Vin =0.4 V) Input Capacitance (f = 1 MHz, Vin =2.4 V) Clock Inputs (CLOCK, CLOCK·) Input Diffemtial Voltage Input High Current (Vin =4.0 V) Input Low Cmrent (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Vin = 4.0 V) Digital Outputs (OO-D7) Output High Voltage (lOH = -400 IIA) Output Low Voltage (lOL = 3.2 rnA) 3-state Current Output Capacitance Symbol Min Typ Max Units 8 8 8 Bits ±l ±1 ±S LSB LSB % Gray Scale n. II.. guaranteed Binary VIR vn. 2.0 GND-O.S IIH IlL CIN AVIN IKllI lKll. 4 .6 4 CKlN VCH Volts Volts 6 Volts 1 -1 10 JJA JJA JJA JJA pF pF Volts 2.4 VOL Ial coour VAA+O.S 0.8 1 -1 10 0.4 Volts 10 JJA pF 10 See test conditions on next page. RAMDACs 4 - 365 .. Bt468 DC Characteristics (continued) Parameter Analog Outputs Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank SETUP = 7.5 IRE SETUP = oIRE Blank Level on lOG Blank Level on lOR, lOB Sync Level on lOG LSBSize DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 rnA) Symbol vex: Min Typ Max Units 26.56 25.08 28.56 26.40 30.56 27.72 rnA rnA 1.48 0 9.44 0 0 2.16 5 11.44 5 5 103.5 2.84 50 13.44 50 50 rnA 5 +1.2 % Volts kn pF -0.5 50 13 RAOUf CAOUf PLL Analog Output Output Cmrent SYNC*/BLANK* = 0 SYNC*/BLANK* = 1 Output Compliance Output Impedance Output Capacitance (f= 1 MHz,PlL=OrnA) PlL Voltage Reference Input Cmrent Power Supply Rejection Ratio (COMP = 0.111F, f = 1 kHz) 9 0 -1.0 11.44 5 20 14 50 +2.5 JIA rnA JIA JIA JIA rnA JIA 50 10 Volts kn pF IREF 10 JIA PSRR 0.5 %/%tNAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 348 n, VREF = 1.235 V. SETUP = 7.5 IRE with 50 n double termination. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 4·366 SECTION 4 Bt468 AC Characteristics 200 MHz Devices Parameter Clock Rate lD*Rate Symbol Min Typ Fmax lDmax 170 MHz Devices Max Min Typ 200 25 Max Units 170 21.25 MHz MHz RtW, CO, Cl Setup Time RtW, CO, Cl Hold Time 1 2 0 10 0 10 ns ns CE*LowTime CE* High Time CE* Asserted to Data Bus Driven CE* Asserted to Data Valid CE* Negated to Data Bus 3-Stated 3 4 5 6 7 45 25 7 45 25 7 ns ns ns ns ns Write Data Setup Time Write Data Hold Time 8 9 20 0 20 0 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 10 11 3 2 3 2 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time 12 13 14 5 2.2 2.2 5.88 2.5 2.5 ns ns ns LD* Cycle Time LD* Pulse Width High Time LD* Pulse Width Low Time 15 16 17 40 15 15 47 20 20 ns ns ns Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time Clock and Data Feedthrough* Glitch Impulse* DAC to DAC Crosstalk Analog Output Skew 18 19 20 12 1 tbd 450 tbd 1 ns ns ns dB pV - sec dB ns 13 Clocks tbd rnA tbd tbd 50 tbd 0 1 13 6 IAA 45 15 12 1 tbd 50 tbd 0 Pipeline Delay VAA Supply Current** 45 15 6 430 Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 348 n, VREF = 1.235 V. TTL input values are 0-3 V, with input rise/fall times S 4 ns, measured between the 10% and 90% points. ECL input values are VAA-O.8 to VAA-1.8 V, with input rise/fall times:S 2 ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. Analog output 10ad:S 10 pF, DO-D7 output 10ad:S 75 pF. See timing notes in Figure 15. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the TTL digital inputs have a 1 ill resistor to GND and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 2x clock rate. **atFmax. IAA (typ) at VAA = 5.0 V, TA= 25° C. IAA (max) at VAA=5.25 V, TA= 0° C. RAMDACS 4·367 Bt468 Timing Waveforms I R(W, co, CI ~ I VALID 3 " s J l....- DO - D7 (RI!AD) DATA OUT (RIW-I) ......... f DO - D7 (WRITB) DATAIN(RIW=D) 16 ~ I 8 I Figure 14. ~I 4 6 ~ MPU Read/Write Timing Dimensions. 17 LDO PO-PI (A-HI, OLO-0L3 (A-HI, SYNC", BLANK· 18 11 lOR, 100, lOB, PU. 19 12 14 Note 1: Output delay time measured from 50% point of the rising clock edge to 50% point of full-scale transition. Note 2: Output settling time measured from 50% point of full scale transition to output settling within ±1 LSB. Note 3: Output rise/fall time measured between 10% and 90% points of full-scale transition. Figure 15. 4 - 368 SECTION 4 Video Input/Output Timing. Bt468 Ordering Information Ambient Temperature Range Model Number Speed Package Bt468KG200 200 MHz 145-pin Ceramic RJA 00 to +70 0 C Bt468KG170 170 MHz 145-pin Ceramic RJA 00 to +70 0 C .. Revision History Datasheet Revision Change from Previous Revision B Full datasheet. C Cursor position panning, RSET value changed to match 50 Q termination. Analog output DC parametrics. D Added double reset, modified PLL feedback circuitry. RAMDACs 4·369 Bt471 Bt476 Bt478 Distinguishing Features Applications • Personal System/2® Compatible • 80, 66, 50, 35 MHz Operation Triple 6-bit or 8-bit D/A Converters • 256-word Color Palette RAM RS-343A/RS-170-Compatible Outputs • 15 Overlay Registers (Bt471/478) Sync on All Three Channels (Bt471/478) Programmable Pedestal (Bt471/478) • External Voltage or Current Reference Standard MPU Interface +5 V CMOS Monolithic Construction • 44-pin PLCC or 28-pin DIP Package • • • • High-Resolution Color Graphics CAE/CAD/CAM Image Processing Instrumentation Desktop Publishing Product Description Related Products The Bt471/476/478 are pin-compatible and software-compatible RAMDACs designed specifically for Personal System/2® compatible color graphics. The Bt476 is also available in a 28-pin DIP package that is pin compatible with the IMS® 0176. Bt473, Bt477, Bt479 • Bt474, Bt475 Functional Block Diagram VAA GND !REP CLOCK r- 80 MHz 256 Color Palette Personal System/2® RAMDAC™ VREP _______l,~;:~~~~===t===OPA COMP The Bt471 has a 256 x 18 color lookup table with triple 6-bit video D/A converters. The Bt478 has a 256 x 24 color lookup table with triple 8-bit video D/A converters. It may be configured for either 6-bit or 8-bit D/A converter operation. The Bt476 is similar to the Bt471, but has no overlays, no programmable setup, or sync information on the analog outputs. >----t-IOR PO-P7 SYNC- :>----+--100 BLANK· OLO-01.3 :>----+--IOB SETUP 00-D7 Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 L478001 Rev. 0 RD· wa· RSO RSI RS2 Additional features on the B t471 and B t478 include 15 overlay registers to provide for overlaying cursors, grids, menus, EGA emulation, etc. Also supported is sync generation on all three channels, a programmable pedestal (0 or 7.5 IRE), and use of either an external voltage or current reference. The Bt471/476/478 generates RS-343A compatible video signals into a doubly terminated 75 Q load, and RS-170 compatible video signals into a singly terminated 75 Q load, without requiring external buffering. ® Personal System/2 and PS/2 are registered trademarks of ffiM. IMS is a registered trademark of Inmos Limited. 4 - 371 III Bt471/476/478 Circuit Description MPU Interface Reading Color Palette RAM Data As illustrated in the functional block diagram, the Bt471/476/478 supports a standard MPU bus interface, allowing the MPU direct access to the color palette RAM and overlay color registers. To read color palette RAM data, the MPU loads the address register (RAM read mode) with the address of the color palette RAM location to be read. The contents of the color palette RAM at the specified address are copied into the ROB registers and the address register is incremented to the next RAM location. The MPU performs three successive read cycles (6 or 8 bits each of red, green, and blue), using RSO-RS2 to select the color palette RAM. Following the blue read cycle, the contents of the color palette RAM at the address specified by the address register are copied into the ROB registers and the address register again increments. A block of color values in consecutive locations may be read by writing the start address and performing continuous R,O,B read cycles until the entire block has been read. The RSO-RS2 select inputs specify whether the MPU is accessing the address register, color palette RAM, overlay registers, or read mask register, as shown in Table 1. The 8-bit address register is used to address the color palette RAM and overlay registers, eliminating the requirement for external address multiplexers. ADDRO corresponds to DO and is the least significant bit. Writing Color Palette RAM Data To write color data, the MPU loads the address register (RAM write mode) with the address of the color palette RAM location to be modified. The MPU performs three successive write cycles (6 or 8 bits each of red, green, and blue), using RSO-RS2 to select the color palette RAM. After the blue write cycle, the three bytes of color information are concatenated into a 24-bit word (I8-bit word for the Bt471/476) and written to the location specified by the address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. A block of color values in consecutive locations may be written to by writing the start address and performing continuous R, 0, B write cycles until the entire block has been written. (See Figure 7.) To write overlay color data, the MPU loads the address register (overlay write mode) with the address of the overlay location to be modified. The MPU performs three successive write cycles (6 or 8 bits each of red, green, and blue), using RSO-RS2 to select the overlay registers. After the blue write cycle, the three bytes of color information are concatenated into a 24-bit word (I8-bit word for the Bt471/476) and written to the overlay location specified by the address register. The address register then increments to the next location which the MPU may modify by simply writing another sequence of red, green, and blue data. A block of color values in consecutive locations may be written to by writing the start address and performing continuous R, 0, B write cycles until the entire block has been written. RS2 RSI RSO Addressed by MPU 0 0 0 0 0 0 I 0 1 1 1 0 address register (RAM write mode) address register (RAM read mode) color palette RAM pixel read mask register I I I I 0 0 1 0 I 1 1 0 Table 1. 4 - 372 Writing Overlay Color Data SECTION 4 address register (overlay write mode) address register (overlay read mode) overlay registers reserved Control Input Truth Table. Bt471/476/478 Circuit Description (continued) Reading Overlay Color Data The MPU interface operates asynchronously to the pixel clock. Data transfers between the color palette RAM/overlay registers and the color registers (R, 0, and B in the block diagram) are synchronized by internal logic, and occur in the period between MPU accesses. Occasional accesses to the color palette RAM can be made without noticeable disturbance on the display screen; however, operations requiring frequent access to the color palette (i.e., block fills of the color palette) should be done during the blanking interval. To read overlay color data, the MPU loads the address register (overlay read mode) with the address of the overlay location to be read. The contents of the overlay register at the specified address are copied into the ROB registers and the address register is incremented to the next overlay location. The MPU performs three successive read cycles (6 or 8 bits each of red, green, and blue), using RSO-RS2 to select the overlay registers. Following the blue read cycle, the contents of the overlay location at the address specified by the address register are copied into the ROB registers and the address register again increments. A block of color values in consecutive locations may be read by writing the start address and performing continuous R, 0, B read cycles until the entire block has been read. To keep track of the red, green, and blue read/write cycles, the address register has 2 additional bits (ADDRa, ADDRb) that count modulo three, as shown in Table 2. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The MPU does not have access to these bits. The other 8 bits of the address register, incremented following a blue read or write cycle, (ADDR0-7) are accessible to the MPU, and are used to address color palette RAM locations and overlay registers, as shown in Table 2. The MPU may read the address register at any time without modifying its contents or the existing read/write mode. Additional In/ormation When accessing the color palette RAM, the address register resets to $00 following a blue read or write cycle to RAM location $FF. While accessing the overlay color registers, the 4 most significant bits of the address register (ADDR4-7) are ignored. Value ADDRa, b (counts modulo 3) ADDRO - 7 (counts binary) RS2 RSI RSO Addressed by MPU red value green value blue value 00 01 10 $00 - $FF xxxx 0000 xxxx 0001 : xxxx Ull Table 2. 0 1 1 : 1 0 0 0 : 0 1 1 1 : 1 color palette RAM reserved overlay color 1 : overlay color 15 Address Register (ADDR) Operation. RAMDACs 4·373 Bt471/476/478 Circuit Description (continued) Bt4711476 Data Bus Interface Frame Buffer Interface Color data is contained on the lower 6 bits of the data bus, with DO being the LSB and D5 the MSB of color data. When writing color data, D6 and D7 are ignored. During color read cycles, D6 and D7 will be a logical zero. The PO-P7 and OLO-OL3 inputs are used to address the color palette RAM and overlay registers, as shown in Table 3. The contents of the pixel read mask register, which may be accessed by the MPU at any time, are bit-wise logically ANDed with the PO-P7 inputs. Bit DO of the pixel read mask register corresponds to pixel input PO. The addressed location provides 24 bits (18 bits for the Bt471/476) of color information to the three D/A converters. Bt478 Data Bus Interface On the Bt478, the 8/6* control input is used to specify whether the MPU is reading and writing 8 bits (8/6* = logical one) or 6 bits (8/6* = logical zero) of color information each cycle. For 8-bit operation, DO is the LSB and D7 is the MSB of color data. For 6-bit operation (and also when using the Bt471/476), color data is contained on the lower 6 bits of the data bus, with DO being the LSB and D5 the MSB of color data. When writing color data, D6 and D7 are ignored. During color read cycles, D6 and D7 will be a logical zero. Note that in the 6-bit mode, the Bt478's full-scale output current will be about 1.5% lower than when in the 8-bit mode. This is due to the 2 LSBs of each 8-bit DAC always being a logical zero in the 6-bit mode. The SYNC* and BLANK* inputs, also latched on the rising edge of CLOCK to maintain synchronization with the color data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figures I, 2, and 3. Tables 4, 5, and 6 detail how the SYNC* and BLANK* inputs modify the output levels. The SETUP input is used to specify whether a 0 IRE (SETUP =GND) or 7.5 IRE (SETUP =VAA) blanking pedestal is to be used. Note that the Bt476 generates only a 0 IRE blanking pedestal (Figures 2 and 3). The analog outputs of the Bt471/476/478 are capable of directly driving a 37.5 n load, such as a doubly terminated 75 n coaxial cable. OLO-OL3 PO-P7 Addressed by frame buffer $0 $0 : $0 $1 $00 $01 color palette RAM location $00 color palette RAM location $01 : color palette RAM location $FF overlay color 1 : $F : $FF $xx $xx $xx : overlay color 15 Table 3. Pixel and Overlay Control Truth Table (Pixel Read Mask Register = $FF). 4·374 SECTION 4 Bt471/476/478 Circuit Description (continued) BT411/418 BT411/418 W/OSYNC WTIH SYNC MA V v MA 19.05 0.114 "]J;.~ 1.000 -r----~r_--------------------~~------WHITBLEVa 1.44 0.054 9.05 0.340 +-----------1---------1----------------- BLACK LEva 0.00 0.000 1.62 0.286 +----------~~~~--~----------------B~LEVa 1.5 IRE 0.00 0.000 Note: 75 Q doubly terminated load. SETUP tolerances assumed on all levels. Figure 1. = 7.5 ~ ~ ~ 40 IRE ______________ ____________________ SYNCLEVa IRE. VREF = 1.235 = 147 Q. V. RSET RS-343A levels and RS-343A Composite Video Output Waveforms (SETUP = 7.5 IRE). Bt471/478 Description lout SYNC* BLANK* DAC Input Data 1 1 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx (rnA) WHIIE DATA DATA-SYNC BLACK BLACK-SYNC BlANK SYNC 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 0 1 0 1 0 Note: 75 Q doubly terminated load, SETUP =7.5 IRE. VREF = 1.235 V. RSET = 147 Q. Table 4. RS-343A Video Output Truth Table (SETUP 7.5 IRE). RAMDACs 4 - 375 .. Bt471/476/478 Circuit Description (continued) BT476OR BT471/478 W,oSYNC MA BT471/478 WI1H SYNC v V MA 17.62 0.660 25.24 0.950 - , - - - - - : : . . . - - - - - - - - - - - - - : : - - - - - WHITE LEVEL 0.00 0.000 7.62 0.286 -+-------L_...---r_.L-________ 0.00 0.000 0.00 0.000 ~-------~-L-----------SYNCLEVEL BLACK/BLANK LEVEL 43 IRE Note: 75 n doubly terminated load. SETUP = 0 IRE. VREF = 1.235 V. RSET tolerances assumed on all levels. Figure 2. Description WHITE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC 4· 376 Bt471/478 lout lout (rnA) (rnA) 17.62 data data 0 0 0 0 25.24 data + 7.62 data 7.62 0 7.62 0 SYNC* BLANK* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx n doubly terminated load. SETUP = 0 IRE. Table 5. RS-343A levels and RS-343A Composite Video Output Waveforms. (SETUP = 0 IRE) Bt476 Note: 75 = 147 n. VREF = 1.235 V. RSET = 147 n. RS·343A Video Output Truth Table (SETUP = 0 IRE). SECTION 4 Bt471/476/478 Circuit Description (continued) NO SYNC MA SYNC V MA V 14.2S 0.713 20.36 \.0\8 -r-----,~--------------------~~------WHITBrnVa 0.00 0.000 6.11 0305 -+------------'-...--.--.1----------- 0.00 0.000 0.00 0.000 ~----------~-L----------sYNCrnva BLACK/BLANK LEva 43 IRE Note: 50 levels. n load, SETUP = 0 IRE. VREF = 1.235 V, RSET = 182 Figure 3. DATA DATA-SYNC BlACK BlACK-SYNC BLANK SYNC PS/2 levels and tolerances assumed on all PS/2 Composite Video Output Waveforms (SETUP = 0 IRE), Sync Disabled Sync Enabled Iout(mA) Iout(mA) 14.25 data data 0 0 0 0 20.36 data + 6.11 data 6.11 0 6.11 0 Description WHITE n. SYNC* BLANK* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: 50 n load, SETUP =0 IRE. VREF = 1.235 V, RSET = 182 n. Table 6. PS/2 Video Output Truth Table (SETUP =0 IRE), RAMDACs 4 • 377 .. Bt471/476/478 Pin Descriptions Pin Name Description BLANK* Composite blank control input (TIL compatible). A logic zero drives the analog outputs to the blanking level, as illustrated in Tables 4, 5 and 6. It is latched on the rising edge of CLOCK. When BLANK* is a logical zero, the pixel and overlay inputs are ignored. SETUP Setup control input (TIL compatible). Used to specify either a 0 IRE (logical zero) or 7.5 IRE (logical one) blanking pedestal. This pin should not be left floating. SYNC* Composite sync control input (TIL compatible). A logical zero on this input switches off a 40 IRE current source on the analog outputs (see Figures I, 2, and 3). SYNC* does not override any other control or data input, as shown in Tables 4, 5, and 6; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. If sync information is not required on the video outputs, SYNC* should be connected to GND. CLOCK Clock input (TIL compatible). The rising edge of CLOCK latches the PO-P7, OLO-OL3, SYNC*, and BLANK* inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedicated TIL buffer to avoid reflection-induced jitter. PO-P7 Pixel select inputs (TIL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the color palette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK. PO is the LSB. Unused inputs should be connected to GND. OW--OL3 Overlay select inputs (TIL compatible). These inputs specify which palette is to be used to provide color information, as illustrated in Table 3. When accessing the overlay palette, the PO-P7 inputs are ignored. They are latched on the rising edge of CLOCK. OLO is the LSB. Unused inputs should be connected to GND. CaMP Compensation pin. If an external voltage reference is used (Figure 4), this pin should be connected to OPA. If an external current reference is used (Figure 5), this pin should be connected to IREF. A 0.1 ~F ceramic capacitor must always be used to bypass this pin to VAA. The CaMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to PC Board Layout Considerations for critical layout criteria. VREF Voltage reference input. If an external voltage reference is used (Figure 4), it must supply this input with a 1.2 V (typical) reference. If an external current reference is used (Figure 5), this pin should be left floating, except for the bypass capacitor. A 0.1 ~F ceramic capacitor is used to decouple this input to GND, as shown in Figures 4. If the VAA supply is very clean, better performance may be obtained by decoupling VREF to VAA. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. OPA Reference amplifier output. If an external voltage reference is used (Figure 4), this pin must be connected to CaMP. When using an external current reference (Figure 5), this pin should be left floating. lOR, lOG, lOB Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 n coaxial cable (Figures 4, 5, and 6). VAA Analog power. All VAA pins must be connected. GND Analog ground. All GND pins must be connected. 4 - 378 SECTION 4 Bt471/476/478 Pin Descriptions (continued) Pin Name IREF Description Full-scale adjust control. Note that the IRE relationships in Figures I, 2, and 3 are maintained, regardless of the full-scale output current. When using an external voltage reference (Figure 4), a resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. The relationship between RSET and the full-scale output current on each output is: RSET (0) =K '" 1,000 * VREF (V) / lout (rnA) K is defmed in the table below. It is recommended that a 147 0 RSET resistor be used for doubly-terminated 75 0 loads (i.e., RS-343A applications). For PS/2 applications (i.e., 0.7 V into 500 with no sync), a 182 0 RSET resistor is recommended. When using an external current reference (Figures 5 and 6), the relationship between IREF and the full-scale output current on each output is: .. IREF (rnA) = lout (rnA) / K Part Mode Pedestal K (with sync) K (no sync) Bt478 6-bit 8-bit 6-bit 8-bit 7.5 IRE 7.5 IRE oIRE oIRE 3.170 3.195 3.000 3.025 2.26 2.28 2.10 2.12 Bt471 (6-bit) 7.5 IRE oIRE 3.170 3.000 2.26 2.10 Bt476 (6-bit) oIRE 3.000 2.10 WR* Write control input (TTL compatible). DO-D7 data is latched on the rising edge of WR*, and RSO-RS2 are latched on the falling edge of WR * during MPU write operations. RD* and WR '" should not be asserted simultaneously. RD* Read control input (TTL compatible). To read data from the device, RD* must be a logical zero. RSO-RS2 are latched on the falling edge of RD* during MPU read operations. RD* and WR * should not be asserted simultaneously. RSO, RS1, RS2 Register select inputs (TTL compatible). RSO-RS2 specify the type of read or write operation being performed, as illustrated in Tables 1 and 2. DO-D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. 8/6* 8-bitl6-bit select input (TTL compatible). This bit specifies whether the MPU is reading and writing 8 bits (logical one) or 6 bits (logical zero) of color information each cycle. For 8-bit operation, D7 is the most significant data bit during color read/write cycles. For 6-bit operation, D5 is the most significant data bit during color read/write cycles (D6 and D7 are ignored during color write cycles and a logical zero during color read cycles). Note: this pin should be connected to GND when using the Bt476. RAMDACs 4 ·379 Bt471/476/478 Pin Descriptions (continued)-44-Pin Plastic J-Lead (PLCC) Ii: II: IC ~ s: ~ Ii: Ii: ~ ~ ~ ~ ~ ~ ~ R ~ S~ Ii: II: IC ~ lit M ~ :II ~ ~ ~ s: ~ Ii: ~ .~ Ii: t:l R ~~~ ~ ~ '" a.OCK 28 IREF OLO Zl lOB GND lOB 0Ll 211 [00 GND [00 0L2 0L3 Bt471/478 NIC a.ocK 25 [OR GND )II GND GND 2! SIl'IlJP (NIC) 8/6* GND VAA VAA VAA OND VAA :10 SYNC· 19 RS2 GND RD' 18 RS! ROO ! 8 S 9 :: ~ !:l " !!l a s 2S a ! s :a OND GND VAA VAA 0\ OND VAA ~[ .. [OR Bt476 NIC OND ,.. IREF VAA !:i ~ lit ~ ~ ~ 8 RS! =~ ~ :!i ~ ~ Q S S 2S a! s ~ ~ .. ~ Names in parentheses are pin names for the Bt471. N/C pins may be left unconnected without affecting the performance of the Bt471/476/478. Pin Descriptions-28-Pin DIP [OR vee 100 RS! lOB RSO IREF D7 PI D6 P2 D5 P3 D4 P4 D3 P5 D2 I'll D! PI DO CLOCK GND 4 - 380 SECTION 4 WR' PO BLANK' RD' !::; Bt471/476/478 PC Board Layout Considerations PC Board Considerations Power Planes This product requires special attention to proper layout techniques to achieve optimum performance. Before beginning PCB layout, refer to the CMOS RAMDAC layout example found in Bt4511718 Evaluation Module Operation and Measurements, application note (AN-16). This application note can be found in Brooktree's 1990 Applications Handbook. Separate digital and analog power planes are necessary. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt471/476/478 power pins, any reference circuitry, and COMP and reference decoupling. There should be at least a 1/8-inch gap between the digital power plane and the analog power plane. The layout should be optimized for lowest noise on the Bt471/476/478 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of V AA and GND pins should be as short as possible to minimize inductive ringing. The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figures 4, 5, and 6. This bead should be located within 3 inches of the Bt471/476/478 and provides resistance to switching currents, acting as a resistance at high frequencies. A low resistance bead should be used, such as Fcrroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. A well-designed power distribution network is critical to eliminating digital switching noise. Ground planes must provide a low-impedance return path for the digital circuits. A minimum of a four-layer PC board is recommended with layers I (top) and 4 (bottom) for signals and layers 2 and 3 for power and ground. The optimum layout enables the Bt471/476/478 to be located as close to the power supply connector and as close to the video output connector as possible. Ground Planes For optimum performance, a common digital and analog ground plane with tub isolation (at least a 1/8-inch gap) and connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector to preserve digital noise margins during MPU read cycles. Thus, the ground tub isolation technique is constrained by the noise margin degradation during digital readback of the Bt471/476/478. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. The analog ground plane should include all Bt471/476/478 ground pins, all reference circuitry and decoupling (external reference if used, RSET resistors, etc.), power supply bypass circuitry for the Bt471/476/478, analog output traces, and the video output connector. Plane-to-plane noise coupling can be reduced by ensuring that portions of the digital power and ground planes do not overlay portions of the analog power and ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. Device Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Power Supply Decoupling Best power supply decoupling performance is obtained with a 0.1 I!F ceramic capacitor decoupling each of the two groups of V AA pins to GND. For operation above 75 MHz, a 0.1 I!F capacitor in parallel with a 0.001 I!F chip capacitor is recommended. The capacitors should be placed as close as possible to the device. The 10 I!F capacitor is for low-frequency power supply ripple; the 0.1 I!F capacitors are for high-frequency power supply noise rejection. RAMDACs 4 • 381 Bt471/476/478 PC Board Layout Considerations (continued) A linear regulator to filter the analog power supply is recommended if the power supply noise is 2: 200 mV or greater than !O LSBs. This is especially important when a switching power supply is used and the switching frequency is close to the raster scan frequency. Note that about 10% of the power supply hum and ripple noise less than 1 MHz will couple onto the analog outputs. COMP Decoupllng The COMP pin must be decoupled to VAA, typically using a 0.1 ~F ceramic chip capacitor. Low-frequency supply noise will require a larger value. Lead lengths should be minimized for best performance. Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge speeds (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals. Ensure that the power pins for the clock driver are properly decoupled to minimize transients. Minimize edge speeds and ringing, using damping resistors (10 to 50 Q) or parallel termination where necessary. If using parallel termination on digital signals, the resistors should be connected to the digital power and ground planes, not the analog power and ground planes. If the display has a "ghosting" problem, additional capacitance in parallel with the COMP capacitor may help to fix the problem. Analog Signal Interconnect Digital Signal Interconnect The Bt471/476/478 should be located as close as possible to the output connectors to minimize noise pickUp and reflections due to impedance mismatch. The digital inputs to the Bt471/476/478 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power and ground planes. The video output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. Most noise on the analog outputs will be caused by excessive edge speeds (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The digital edge speeds should be no faster than necessary, as feedthrough noise is proportional to the digi tal edge speeds. Lower speed applications will benefit from using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission line mismatch will exist if the line length reflection time is greater than 1/4 the signal edge time, resulting in ringing, overshoot, and undershoot that can generate noise onto the analog outputs. Line termination or reducing the line length is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (10 to 50 Q). 4 • 382 SECTION 4 For maximum performance, the analog outputs should have a source load resistor equal to the destination termination (via a clean isolated ground return path). The load resistor connection between the current output and GND should be as close as possible to the Bt471/476/478 to minimize reflections. Unused analog outputs should be connected to GND. Analog edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce high-frequency energy, reducing EMI and noise. Analog Output Protection The Bt471/476/478 analog outputs should be protected against high-energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figures 4, 5, and 6 can prevent latchup under severe discharge conditions without adversely degrading analog transitIOn times. The IN4148/9 parts are low-capacitance, fast-switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BA V99 or MMBD7001). Bt471/476/478 PC Board Layout Considerations (continued) - 44·Pin Plastic J·Lead (PLCC) ANALOG POWER PLANE Ll ' - . . , . - - - + 5V (VCe) Cl Bt471/476/478 . ._~_~_~_~_~_ _ _ _ _ _ _~_ _ _ _. ._ _• ~ GROUND .. R3 IREF IOR\-----_--+--+_--_( TO VIDEO IOG\-------~-+_--_( CONNECTOR IDBr---------_---{ o DAC OlITPUT VAA IN4148/9 ---t---- TOMONITOR IN4148/9 GND Location CI-C5 C6 L1 Rl, R2, R3 R4 RSET ZI Description 0.1 ~ ceramic capacitor 10 ~F capacitor ferrite bead 75 n 1% metal film resistor 1 ill S% resistor 1% metal film resistor 1.2 V voltage reference Vendor Part Nwnber Erie RPEl12Z5UI04M50V Mallory CSR13G106KM Fair-Rite 2743001111 Dale CMF-55C Dale CMF-5SC National Semiconductor LM385BZ-1.2 Note: The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the Bt471/476/478. Figure 4. Typical Connection Diagram and Parts List (External Voltage Reference). RAMDACs 4 - 383 Bt471/476/478 PC Board Layout Considerations (continued) - 44-Pin Plastic J-Lead (PLCC) 8t471/476/478 Ll 1-,...._ _ _ + C6 +SV (VCC) Cl ~. . . . . . . . . . . .~. . . .~~. . . . . . . . . . . . . .~............... GROUND TO lOG VIDEO I - - - - - - - - -.....-+-----{ CONNECTOR 10Br---------+---~ o VAA IN4148 19 DAC TO MONITOR OUTPUT IN4148 19 GND Location Cl - C5 C6 C7, C8 L1 RI, R2, R3 ZI RSEr Description 0.1 ~ ceramic capacitor 10 JlF capacitor I JlF capacitor ferrite bead 75 n 1% metal film resistor adjustable regulator I % metal film resistor Vendor Part Number Erie RPE112Z5UI04M50V Mallory CSRI3G106KM Mallory CSR13G105KM Fair-Rite 2743001111 Dale CMF-55C National Semiconductor LM337LZ Dale CMF-55C Note: The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the Bt471/476/478. Figure 5. 4 - 384 SECTION 4 Typical Connection Diagram and Parts List (External Current Reference), Bt471/476/478 PC Board Layout Considerations (continued) - VAA~~ 28-Pin DIP ______________~__________. . ANALOG POWER PLANE C6 Bt476 L1 (28-pln DIP) +SV{VCC) RSET= 1.22/1RBP Cl GND~""""""~"""~""""""""""""",,,,, GROUND TO 10RI-----.....-+--+----{ .. VIDEO CONNECfOR IOGI-------+--+----{ lOB I - - - - - - - - -.....---{ o VAA IN4148/9 DAC TO MONITOR OIITPUT IN4148/9 GND Location C1-C4 C5 C6.C7 L1 RI. R2. R3 Zl RSEr Vendor Part Number Description 0.1 J.lF ceramic capacitor 10 J.lF capacitor 1 J.lF capacitor ferrite bead 75 n 1% metal film resistor adjustable regulator 1% metal film resistor Erie RPE112Z5U104M50V Mallory CSR13G106KM Mallory CSR13GI05KM Fair-Rite 2743001111 Dale CMF-55C National Semiconductor LM337LZ Dale CMF-55C Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the Bt476. Figure 6. Substitution of devices with similar Typical Connection Diagram and Parts List (External Current Reference). RAMDACs 4 - 385 Bt471/476/478 Application Information Using Multiple Devices Reference Selection When using multiple RAMDACs, each RAMDAC should have its own power plane ferrite bead. In addition, a single reference may drive multiple devices; however, isolation resistors are recommended to reduce color channel crosstalk. An external voltage reference provides about lOx better power supply rejection on the analog outputs than an external current reference. Higher performance is obtained if each RAMDAC has its own reference. This may further reduce the amount of color channel crosstalk and color palette interaction. Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. Each RAMDAC must still have its own individual RSET resistor, analog output termination resistors, power supply bypass capacitors, COMP capacitor, and reference capacitors. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay VAA power to the device. Ferrite beads must only be used for analog power V AA decoupling. Inductors cause a time constant delay that induces latchup. ESD and Latchup Considerations Latchup can be prevented by assuring that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +D.S V. 4 - 386 SECTION 4 BnxktreeQP Bt471/476/478 Recommended Operating Conditions Parameter Symbol Power Supply 80, 66 MHz Parts 50, 35 MHz Parts Ambient Operating Temperature Output Load Voltage Reference Configuration Reference Voltage Current Reference Configuration lREF Current Standard RS-343A PSn. Compatible VM TA RL Min Typ Max Units 4.75 4.5 0 5.00 5.00 5.25 5.5 +70 Volts Volts ·C Ohms 37.5 1.14 1.235 1.26 Volts -3 -3 -8.39 -8.88 -10 -10 rnA rnA Min Typ Max Units 7.0 Volts VAA+O.5 Volts TJ +125 +150 +150 °C °C °C TSOL 260 °C TVSOL 220 °C VREF !REF Absolute Maximum Ratings Parameter Symbol VAA (measured to GND) Voltage on any Signal Pin· Analog Output Short Circuit Duration to any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, 1/4" from pin) Vapor Phase Soldering (1 minute) GND-O.5 indefinite ISC TA TS -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. • This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. RAMDACs 4·387 Bt471/476/478 DC Characteristics Parameter Resolution (each DAC) Bt478 Bt471/476 Accuracy (each DAC) Integral Linearity Error Bt478 Bt476 Bt471 Differential Linearity Error Bt478 Bt476 Bt471 Gray Scale Error Monotonicity Coding Digital Inputs Input High Voltage Input Low Voltage Input High Current (Vin =2.4 V) Input Low Current (Vin =0.4 V) Input Capacitance (f =1 MHz, Vin =2.4 V) Digital Outputs Output High Voltage (IOH =-400 J.IA) Output Low Voltage (IOL =3.2 rnA) 3-State Current Output Capacitance See test conditions on next page. 4·388 SECTION 4 Symbol Min Typ Max Units 8 6 8 6 8 6 Bits Bits ±1 ±l/2 ±1/4 LSB LSB LSB ±1 ±1/2 ±l/4 ±5 LSB LSB LSB % GrayScale n.. II. guaranteed Binary vrn VlL Illi IlL CIN VOO 2.0 GND-O.S VAA+O.S 0.8 1 -1 7 2.4 Volts Volts J.IA J.IA pF Volts VOL 0.4 Volts IOl SO 7 J.IA CDOUf pF BnxKtree~ Bt471/476/478 DC Characteristics (continued) Parameter Symbol Analog Outputs Gray Scale Current Range Output Cmrent (Standard RS-343A) White Level Relative to Black· Black Level Relative to Blank Bt471/478 SEfUP = 7.5 IRE SEIUP=OIRE Bt476 Blank Level Bt471/478 Bt476 Sync Level (Bt471/478 only) LSB Size Bt478 (8/6· = logical one) Bt471/476 DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 rnA) Min Typ Voltage Reference Input Current IVREF Power Supply Rejection Ratio·· (COMP = 0.1 jLF, f = 1 kHz) PSRR Units 20 rnA 16.74 17.62 18.50 rnA 0.95 0 0 1.44 5 0 1.90 50 0 rnA 6.29 0 0 7.62 5 5 8.96 50 50 rnA 69.1 279.68 2 VOC RAOur CAOUf Max -1.0 5 +1.5 10 30 IIA IIA IIA IIA IIA IIA .. % Volts kO pF IIA 10 0.5 %/%/!;,VAA Test conditions to generate RS-343A standard video signals (unless otherwise specified): "Recommended Operating Conditions" using external voltage reference with RSET = 1470, VREF = 1.235 V, SETUP = 7.5 IRE, 8/6· = logical one. For 28-pin DIP version of the Bt476, IREF = -8.39 mAo As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room and nominal voltage, i.e., 5 V. ·Since the Bt471 and Bt476 have 6-bit DACs (and the Bt478 in the 6-bit mode), the output levels are approximately 1.5% lower than these values. **Guaranteed by characterization, not tested. Analog Output Levels - PS/2 Compatibility Parameter Analog Outputs Output Cmrent White Level Relative to Black Black Level Relative to Blank Bt471/478 SEfUP= 7.5 IRE SEIUP=OIRE Bt476 Blank Level Bt471/478 Bt476 Sync Level (Bt4711478 only) Symbol Min Typ Max Units 18.00 18.65 20.00 rnA 1.01 0 0 1.51 5 5 2.0 50 50 rnA 6.6 0 0 8 5 5 9.4 50 50 rnA IIA IIA IIA IIA Test conditions to generate psn compatible video signals (unless otherwise specified): "Recommended Operating Conditions" using external voltage reference with RSET = 140 n. VREF = 1.235 V, SETUP = 7.5 IRE, 8/6· = logical one. For 28-pin DIP version of the Bt476, IREF = -8.88 rnA. RAMDACs 4 ·389 Bt471/476/478 AC Characteristics 80 MHz Devices Symbol Parameter Clock Rate Min Typ 66 MHz Devices Max Min Typ 80 Fmax Max Units 66 MHz RSO-RS2 Setup Time RSO-RS2 Hold Time 1 2 10 10 RD* Asserted to Data Bus Driven RD* Asserted to Data Valid RD* Negated to Data Bus 3-Stated Read Data Hold Tune 3 4 5 6 5 5 5 ns ns ns ns Write Data Setup Time Write Data Hold Time 7 8 10 10 10 10 ns ns RD*. WR* Pulse Width Low RD*. WR * Pulse Width HiBh 9 10 50 6*p13 50 6*p13 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 11 12 3 3 3 3 ns ns Clock Cycle Time (P13) Clock Pulse Width HiBh Time Clock Pulse Width Low Time 13 14 15 12.5 4 4 15.15 5 ns ns ns Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time* Clock and Data Feedthrough* Glitch Impulse· DAC-to-DAC Crosstalk Analog Output Skew 16 17 18 4·390 1M SECTION 4 5 40 20 40 20 5 30 30 3 13 -30 75 -3 4 See test conditions on next page. ns ns 3 13 -30 75 -23 4 4 180 220 4 ns ns ns dB pV -sec dB 2 ns 4 4 Clocks 180 220 rnA 2 Pipeline Delay VAA Supply Current*· 10 10 Bt471/476/478 AC Characteristics (continued) 35 MHz Devices 50 MHz Devices Parameter Clock Rate Symbol Min Typ Max Typ Min 50 Fmax Max Units 35 MHz RSO-RS2 Setup Time RSO-RS2 Hold Time 1 2 10 10 RD* Asserted to Data Bus Driven RD* Asserted to Data Valid RD* Negated to Data Bus 3-Stated Read Data Hold Time 3 4 5 6 5 5 5 ns ns ns ns Write Data Setup Time Write Data Hold Time 7 8 10 10 10 10 ns ns RD*, WR* Pulse Width Low RD*, WR * Pulse Width High 9 10 50 6*p13 50 6*p13 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 11 12 3 3 3 3 ns ns Clock Cycle Time (P13) Clock Pulse Width High Time Clock Pulse Width Low Time 13 14 15 20 6 6 28 7 9 ns ns ns Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time* Clock and Data Feedthrough* Glitch Impulse* DAC-to-DAC Crosstalk Analog Output Skew 16 17 18 ns ns 5 40 20 40 20 2 ns ns ns dB pV - sec dB ns 4 4 Clocks 180 220 rnA 30 30 3 28 -30 75 -23 3 20 -30 75 -23 2 Pipeline Delay Average VAA Supply Current** 10 10 4 IAA 4 4 180 220 4 Test conditions (unless otherwise specified): "Recommended Operating Conditions" using external voltage reference with RSET = 147 n, VREF = 1.235 V, SETUP = 7.5 IRE, 8/6* = logical one. For 28-pin DIP version of the Bt476, IREF = -8.39 mAo TTL input values are 0-3 V, with input rise/fall times ~ 4 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ~ 10 pF, DO-D7 output load ~ 75 pF. See timing notes in Figure 8. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. ·Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the digital inputs have a 1 kn resistor to ground and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth =2x clock rate. **at Fmax. IAA (typ) at V AA = 5.0 V. IAA (max) at V AA (max). RAMDACs 4·391 Bnxktree Bt471/476/478 fJ Timing Waveforms RSO, RSl, RS2 DO - D7 (READ) DO - D7 (WIUl1!) Figure 7. MPU ReadlWrite Timing Dimensions. CLOCK PO - PI, 01.0 - 01.3, SYNC', BLANK" lOR, 100, lOB Note 1: Output delay meBSured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Note 2: Settling time meBSured from the 50% point of full-scale transition to the output remaining within ±1 LSB (Bt478), ±1/4 LSB (Bt471), or ±1/2 LSB (Bt476)_ Note 3: Output rise/fall time meBSured between the 10% and 90% points of full-scale transition. Figure 8. 4·392 SECTION 4 Video Input/Output Timing. Bt471/476/478 Ordering Information Model Number Color Palette RAM Overlay Palette Sync Generation Speed Package Bt471KPJ80 256 x 18 15 x 18 yes 80 MHz 44-pin Plastic J-Lead 00 to +70 0 C Bt471KPJ66 256 x 18 15 x 18 yes 66 MHz 44-pin Plastic J-Lead 00 to +70 0 C Bt471KPJ50 256 x 18 15 x 18 yes 50 MHz 44-pin Plastic J-Lead 00 to +70 0 C Bt471KPJ35 256 x 18 15 x 18 yes 35 MHz 44-pin Plastic J-Lead 00 to +70 0 C Bt476KPJ66 256 x 18 - no 66 MHz 44-pin Plastic J-Lead 00 to +70 0 C Bt476KPJ50 256 x 18 - no 50 MHz 44-pin Plastic J-Lead 00 to +70 0 C Bt476KPJ35 256 x 18 - no 35 MHz 44-pin Plastic J-Lead 0 0 to +700 C Bt476KP66 256 x 18 - no 66 MHz 28-pin 0.6" Plastic DIP 00 to +70 0 C Bt476KP50 256 x 18 - no 50 MHz 28-pin 0.6" Plastic DIP 00 to +700 C Bt476KP35 256 x 18 - no 35 MHz 28-pin 0.6" Plastic DIP 00 to +70 0 C Bt478KPJ80 256 x 24 15 x 24 yes 80 MHz 44-pin Plastic J-Lead 00 to +700 C Bt478KPJ66 256 x 24 15 x 24 yes 66 MHz 44-pin Plastic J-Lead 0° to +70 0 C Bt478KPJ50 256 x 24 15 x 24 yes 50 MHz 44-pin Plastic J-Lead 00 to +70 0 C Bt478KPJ35 256 x 24 15 x 24 yes 35 MHz 44-pin Plastic J-Lead 00 to +700 C I RAMDACs Ambient Temperature Range 4·393 Bt471/476/478 Revision History Datasheet Revision 4 - 394 Change from Previous Revision N Expanded PC Board Layout section. o Changed VREF decoupling from VAA to GND for external voltage reference PCB layout. Added ESD/latchup information. SECTION 4 Preliminary Information This document contains information on a new product. The parametric infonnation, although not fully characterized, is the result of testing initial devices. Distinguishing Features Applications • • • • • • • • • • • • • • • • • • Bt471/478 Software Compatible 80, 66, 50, 35 MHz Operation Triple 8-bit D/A Converters Three 256 x 8 Color Palette RAMs Three 15 x 8 Overlay Registers RS-343A/RS-170 Compatible Outputs Sync on All Three Channels Programmable Pedestal (0 or 7.5 IRE) On-Chip Voltage Reference Standard MPU Interface +5 V CMOS Monolithic Construction 68-pin PLCC Package Typical Power Dissipation: 900 m W High-Resolution Color Graphics CAE/CAD/CAM Image Processing Instrumentation Desktop Publishing GND VREP OUT 80 MHz Monolithic CMOS Triple 8-bit True-Color RAMDAC™ Product Description The Bt473 true-color RAMDAC is designed specifically for true-color computer graphics. It has three 256 x 8 color lookup tables with triple 8-bit video 0/A converters to support 24-bit true-color operation. In addition, 8-bit pseudo-color, 8-bit true-color, and 15-bit true-color operations are supported. Functional Block Diagram VAA Bt473 lRBP VRBF CLOCK OPA RO·R7 COMP GO·Q7 lOR BO·B7 100 SO.SI Features include a programmable pedestal (0 or 75 IRE) and optional on-chip voltage reference. The 15 overlay registers provide for overlaying cursors, grids, menus, EGA emulation, etc. Also supported are a pixel read mask register and sync generation on all three channels. Either an external current reference, an external voltage reference, or the internal voltage reference may be used. SYNC" IDB OIJ)·OU BlANK" CRO·CR3 DO·D7 Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580. (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 1A73001 Rev. H JII)O WK. RSO RBI RB2 4 • 395 The Bt473 generates RS-343A compatible video signals into a doubly terminated 75 n load, and RS-170 compatible video signals into a singly terminated 75 n load, without requiring external buffering. Differential and integral linearity errors are guaranteed to be a maximum of ±1 LSB over the full temperature range. Bt473 Circuit Description MPU Interface As illustrated in the functional block diagram, the Bt473 supports a standard MPU bus interface, allowing the MPU direct access to the color palette RAM and overlay color registers. The RSO-RS2 select inputs specify whether the MPU is accessing the address register, color palette RAM, overlay registers, or read mask register, as shown in Table 1. The 8-bit address register is used to address the color palette RAM and overlay registers, eliminating the requirement for external address multiplexers. ADDRO corresponds to DO and is the least significant bit. Writing Color Palette RAM Data To write color data, the MPU writes the address register (RAM write mode) with the address of the color palette RAM location to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using RSO-RS2 to select the color palette RAM. After the blue write cycle, the three bytes of color information are concatenated into a 24-bit word and written to the location specified by the address register. The address register then increments to the next location which the MPU may modify by simply writing another sequence of red, green, and blue data. A block of color values in consecutive locations may be written to by writing the start address and performing continuous R, G, B write cycles until the entire block has been written. Reading Color Palette RAM Data To read color palette RAM data, the MPU loads the address register (RAM read mode) with the address of the color palette RAM location to be read. The contents of the color palette RAM at the specified Writing Overlay Color Data To write overlay color data, the MPU writes the address register (overlay write mode) with the address of the overlay location to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using RSO-RS2 to select the overlay registers. After the blue write cycle, the three bytes of color information are concatenated into a 24-bit word and written to the overlay location specified by the address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. A block of color values in consecutive locations may be written to by writing the start address and performing continuous R, G, B write cycles until the entire block has been written. Reading Overlay Color Data To read overlay color data, the MPU loads the address register (overlay read mode) with the address of the overlay location to be read. The contents of the overlay register at the specified address are copied into the RGB registers and the address register is incremented to the next overlay location. The MPU performs three successive read cycles (8 bits each of RS2 RSI RSO Addressed by MPU 0 0 0 0 0 0 1 0 1 1 1 0 address register (RAM write mode) address register (RAM read mode) color palette RAMs pixel read mask register 1 1 1 1 0 0 1 0 1 1 1 0 Table 1. 4 - 396 address are copied into the RGB registers and the address register is incremented to the next RAM location. The MPU performs three successive read cycles (8 bits each of red, green, and blue), using RSO-RS2 to select the color palette RAM. Following the blue read cycle, the contents of the color palette RAM at the address specified by the address register are copied into the RGB registers and the address register again increments. A block of color values in consecutive locations may be read by writing the start address and performing continuous R, G, B read cycles until the entire block has been read. SECTION 4 address register (overlay write mode) address register (overlay read mode) overlay registers command register Control Input Truth Table. Bt473 Circuit Description (continued) red, green, and blue), using RSO-RS2 to select the overlay registers. Following the blue read cycle, the contents of the overlay location at the address specified by the address register are copied into the RGB registers and the address register again increments. A block of color values in consecutive locations may be read by writing the start address and performing continuous R, G, B read cycles until the entire block has been read. the address register, incremented following a blue read or write cycle (ADDR0-7), are accessible to the MPU, and are used to address color palette RAM locations and overlay registers, as shown in Table 2. The MPU may read the address register at any time without modifying its contents or the existing read/write mode. 8-Bit / 6-Bit Operation Additional Information The command register specifies whether the MPU is reading and writing 8 bits or 6 bits of color irtformation each cycle. When accessing the color palette RAM, the address register resets to $00 following a blue read or write cycle to RAM location $FF. While accessing the overlay color registers, the 4 most significant bits of the address register (ADDR4-7) are ignored. For 8-bit operation, DO is the LSB and D7 is the MSB of color data. For 6-bit operation, color data is contained on the lower 6 bits of the data bus, with DO being the LSB and D5 the MSB of color data. When writing color data, D6 and D7 are ignored. During color read cycles, D6 and D7 will be a logical zero. Note that in the 6-bit mode, the Bt473's full-scale output current will be about 1.5% lower than when in the 8-bit mode. This is due to the 2 LSBs of each 8-bit DAC always being a logical zero in the 6-bit mode. The MPU interface operates asynchronously to the pixel clock. Data transfers between the color palette RAM/overlay registers and the color registers (R, G, and B in the block diagram) are synchronized by internal logic, and occur in the period between MPU accesses. Occasional accesses to the color palette RAM can be made without noticeable disturbance on the display screen; however, operations requiring frequent access to the color palette (i.e., block fills of the color palette) should be done during the blanking interval. Color Modes Four color modes are supported by the Bt473: 24-bit true color, 15-bit true color, 8-bit true color, and 8-bit pseudo color. The mode of operation is determined by the SO and SI inputs, in conjunction with CR7 and CR6 of the command register. SO and SI are pipelined to maintain synchronization with the RO-R7, GO-G7, BO-B7, and OLO-OL3 pixel and overlay data inputs. To keep track of the red, green, and blue read/write cycles, the address register has 2 additional bits (ADDRa, ADDRb) that count modulo three, as shown in Table 2. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The MPU does not have access to these bits. The other 8 bits of Table 3 lists the modes of operation. Value RS2 RSI RSO Addressed by MPU 00 01 10 x x x 0 0 0 1 1 1 red value green value blue value $00 - $FF xxxx 0000 xxxx 0001 : xxxx 1111 0 1 1 0 0 0 1 1 1 color palette RAMs reserved overlay color 1 ADDRa, b (counts modulo 3) ADDRO - 7 (counts binary) Table 2. : : : : 1 0 1 overlay color 15 Address Register (ADDR) Operation. RAMDACs 4 - 397 .. Bnxktree~ Bt473 Circuit Description (continued) OL3-OLO so Sl, CR7, CR6 Mode R7-RO G7-G0 B7-BO $xx 1111 xx xx overlay color 15 $xx $xx : : : : : : : 0001 xx xx overlay color 1 $xx $xx $xx 0000 0000 0000 0000 00 00 00 00 00 01 10 11 24-bit true color 24-bit true color 24-bit true color reserved R7-RO R7-RO R7-RO reserved G7-G0 G7-G0 G7-G0 reserved B7-BO B7-BO B7-BO reserved 0000 0000 0000 0000 01 01 01 01 00 01 10 11 24-bit true color bypass 24-bit true color bypass 24-bit true color bypass reserved R7-RO R7-RO R7-RO reserved G7-G0 G7-G0 G7-G0 reserved B7-BO B7-BO B7-BO reserved 0000 0000 0000 0000 10 00 01 11 8-bit pseudo color (red) 8-bit pseudo color (green) 8-bit pseudo color (blue) reserved P7-PO ignored ignored reserved ignored P7-PO ignored reserved ignored ignored P7-PO reserved 0000 0000 0000 0000 11 11 11 11 00 01 10 11 8-bit true-color bypass (red) 8-bit true-color bypass (green) 8-bit true-color bypass (blue) 15-bit true-color bypass rrrgggbb ignored ignored Orrrrrgg ignored rrrgggbb ignored gggbbbbb ignored ignored rrrgggbb ignored 10 10 10 10 Table 3. RSO, RSl, RS2 RD·, WR* DO· D7 (READ) DO· D7 (WRITE) ==:x V~ID )(~______________________________________________ \ / ------------------« DATA Ollf (RD' =0) ________________________-J)( Figure 1. 4 - 398 Color Operation Modes. SECTION 4 DATA IN (WR' = 0) MPU Read/Write Timing. )>------ x'--____ Bt473 Circuit Description (continued) 24-Bit True-Color Mode Twenty-four bits of RGB color information may be input into the Bt473 every clock cycle. The 24 bits of pixel information are input via the RO-R7, GO-G7, and BO-B7 inputs. RO-R7 address the red color palette RAM, GO-G7 address the green color palette RAM, and BO-B7 address the blue color palette RAM. Each RAM provides 8 bits of color information to the corresponding D/A converter. The pixel read mask register is used in this mode. 24-Bit True-Color Bypass Mode Twenty-four bits of pixel information may be input into the Bt473 every clock cycle. The 24 bits of pixel information are input via the RO-R7, GO-G7, and BO-B7 inputs. RO-R7 drive the red DAC directly, GO-G7 drive the green DAC directly, and BO-B7 drive the blue DAC directly. The color palette RAMs and pixel read mask register are bypassed. As seen in the table, 3 bits of red, 3 bits of green, and 2 bits of blue data are input. The 3 MSBs of the red and green DACs are driven directly by the inputs, while the 2 MSBs of the blue DAC are driven directly. The 5 LSBs for the red and green DACs, and the 6 LSBs for the blue DAC, are a logical zero. The color palette RAMs and pixel read mask register are bypassed. IS-Bit True-Color Bypass Mode Fifteen bits of pixel information may be input into the Bt473 every clock cycle. The 15 bits of pixel information (5 bits of red, 5 bits of green, and 5 bits of blue) are input via the RO-R7 and GO-G7 inputs: 8-Bit Pseudo-Color Mode Eight bits of pixel information may be input into the Bt473 every clock cycle. The 8 bits of pixel information (p0-P7) are input via the RO-R7, GO-G7 or BO-B7 inputs, as specified by CR7 and CR6. All three color palette RAMs are addressed by the same 8 bits of pixel data (PO-P7). Each RAM provides 8 bits of color information to the corresponding D/A converter. The pixel read mask register is used in this mode. Pixel Inputs Input Format R7 R6 R5 R4 R3 R2 Rl RO 0 R7 R6 R5 R4 R3 G5 G4 G1 Eight bits of pixel information may be input into the Bt473 every clock cycle. The 8 bits of pixel information are input via the RO-R7, GO-G7 or BO-B7 inputs, as specified by CR7 and CR6: RO-R7 Inputs Selected R7 R6 R5 R4 R3 R2 Rl RO GO-G7 Inputs Selected BO-B7 Inputs Selected Input Format G7 B7 B6 B5 B4 B3 B2 Bl BO R7 R6 R5 G6 G5 G4 G3 G2 G1 GO G6 G7 G3 G2 8-Bit True-Color Bypass Mode G7 G6 G5 G4 GO .. G3 B7 B6 B5 B4 B3 The 5 MSBs of the red, green, and blue DACs are driven directly by the inputs. The 3 LSBs are a logical zero. The color palette RAMs and pixel read mask register are bypassed. Overlays The overlay inputs, OLO-OL3, have priority regardless of the color mode, as shown in Table 3. G7 G6 G5 B7 B6 RAMDACs 4 - 399 Bt473 Circuit Description (continued) Pixel Read Mask Register Programmable Setup The 8-bit pixel read mask register is implemented as three 8-bit pixel read mask registers, one each for the RO-R7, 00-07, and BO-B7 inputs. When writing to the pixel read mask register, the same data is written to all three registers. The read mask registers are located just before the color palette RAMs. Thus, they are used only in the 24-bit true-color and 8-bit pseudo-color modes since these are the only modes that use the color palette RAMs. The command register specifies whether a 0 IRE or 7.5 IRE blanking pedestal is to be used. The contents of the pixel read mask register, which may be accessed by the MPU at any time, are bit-wise logically ANDed with the 8-bit inputs prior to addressing the color palette RAMs. Bit DO of the pixel read mask register corresponds to pixel input PO (RO, 00, or BO depending on the mode). Bit DO also corresponds to data bus bit DO. Video Generation The SYNC* and BLANK* inputs, also latched on the rising edge of CLOCK to maintain synchronization with the color data (see figure 2), add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figures 3 and 4. Tables 4 and 5 detail how the SYNC· and BLANK* inputs modify the output levels. The analog outputs of the Bt473 are capable of directly driving a 37.5 n load, such as a doubly terminated 75 n coaxial cable. CLOCK RO·R7. 00·07. BO·87. OLO·01.3, SO, 51, DATA lOR, lOG. lOB Figure 2. 4 - 400 SECTION 4 Video Input/Output Timing. Bt473 Circuit Description (continued) MA V 26.67 1.000 -r-----,.-------------:;~--- WHITE LEVFL 9.05 0.340 -+------t----+--------- BLACK LEVFL 7.5 IRE 7.62 0.286 +-------'--.---"T-~-------- BLANK LEVEL 0.00 0000 -L-------~-L 40 IRE _ _ _ _ _ _ _ _ _ _ _ _ SYNCLEVFL Note: 75 Q doubly terminated load, SETUP = 7.5 IRE, VREF = 1.235 V, RSET = 140 Q. RS-343A levels and tolerances assumed on all levels. Figure 3. Composite Video Output Waveforms (SETUP Description lout SYNC* BLANK* DAC Input Data 1 1 0 1 0 1 1 1 1 1 G $FF data data $00 $00 (rnA) WHnE DATA DATA-SYNC BLACK BLACK-SYNC -I bLAl~1\. SYNC ,~-~ 26.67 data + 9.05 data + 1.44 9.05 1.44 - -~ I.U~ o Note: Typical with full-scale lOR, lOG, lOB 140 Q. Table 4. 7.5 IRE). o o -. $xx $xx = 26.67 rnA, SETUP = 7.5 IRE, VREF = 1.235 V, RSET = Video Output Truth Table (SETUP = 7.5 IRE). RAMDACs 4 • 401 .. Bt473 Circuit Description (continued) MA V 25.24 0.950 -y----,...--------------:;;:;:---- WHITE LEVEL 1.62 0.286 -+--------1-....---,.-.1--------- BLACK/BLANK LEVEL 0.00 0.000 43 IRE - L_ _ _ _ _ _ _- L......._ _ _ _ _ _ _ _ _ _ SYNC LEVEL Note: 75 n doubly terminated load, SETUP = 0 IRE, YREF = 1.235 tolerances assumed on all levels. Figure 4. y, RSET = 140 Composite Video Output Waveforms (SETUP Description lout 25.24 data + 7.62 data 7.62 0 7.62 0 =0 RS·343A levels and IRE). SYNC· BlANK* DAC Input Data 1 I 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx (rnA) WHITE DATA DATA· SYNC BLACK BLACK· SYNC BlANK SYNC n. Note: Typical with full·scale lOR, lOG, lOB = 25.24 rnA, SETUP = 0 IRE, YREF = 1.235 Y, RSET = 140 n. Table 5. 4 • 402 SECTION 4 Video Output Truth Table (SETUP =0 IRE). Bt473 Internal Registers Command Register The command register may be written to or read by the MPU at any time. and is not initialized. CRO is the least significant bit and corresponds to DO. CR7. CR6 Color mode select These bits are used to control the various color modes. as shown in Table 3. CR5 Setup select Used to specify either a 0 IRE (logical zero) or 7.5 IRE (logical one) blanking pedestal. (0) OIRE (1) 7.5 IRE CR4 8-bit I 6-bit color select (0) 6-bit (1) 8-bit CR3-CRO CR3-CRO outputs This bit specifies whether the MPU is reading and writing 8 bits (logical one) or 6 bits (logical zero) of color information each cycle. For 8-bit operation. D7 is the most significant data bit during color read/write cycles. For 6-bit operation. D5 is the most significant data bit during color read/write cycles (D6 and D7 are ignored during color write cycles and a logical zero during color read cycles). These bits are output onto the CR3-CRO pins. RAMDACs 4 • 403 .. Bt473 Pin Descriptions Pin Name Description BLANK'" Composite blank control input (TIL compatible). A logic zero drives the analog outputs to the blanking level, as illustrated in Tables 4 and 5. It is latched on the rising edge of CLOCK. When BLANK'" is a logical zero, the pixel and overlay inputs are ignored. SYNC'" Composite sync control input (TIL compatible). A logical zero on this input switches off a 40 IRE current source on the analog outputs (see Figures 3 and 4). SYNC* does not override any other control or data input, as shown in Tables 4 and 5; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. If sync information is not to be generated on the analog outputs, this pin should be connected to OND. CLOCK Clock input (TIL compatible). The rising edge of CLOCK latches the RO-R7, 00-07, BO-B7, SO, SI, Oill-OL3, SYNC"', and BLANK· inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedicated TIL buffer to avoid reflection-induced jitter. RO-R7, 00-07, BO-B7 Red, green, and blue pixel select inputs (TIL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the red, green, and blue color palette RAMs is to be used to provide color information. They are latched on the rising edge of CLOCK. RO, 00, and BO are the LSBs. Unused inputs should be connected to OND. SO, SI Color mode select inputs (TIL compatible). These inputs specify the mode of operation as shown in Table 3. They are latched on the rising edge of CLOCK. Oill-OL3 Overlay select inputs (TIL compatible). These inputs specify which palette is to be used to provide color information, as illustrated in Table 3. When accessing the overlay palette, the RO-R7, 00-07, BO-B7, SO, and SI inputs are ignored. They are latched on the rising edge of CLOCK. OLO is the LSB. Unused inputs should be connected to OND. IOR,IOG,IOB Red, green, and blue current outputs. These high-impedance current sources are capable of directly driving a doubly terminated 75 Q coaxial cable (Figures 5, 6, and 7). IREF When using a voltage reference (Figures 5 and 6), a resistor (RSET) connected between this pin and OND controls the magnitude of the full-scale video signal. The relationship between RSET and the full-scale output current on each output is: for SETUP =7.5 IRE: RSET (Q) =3,195 * VREF (V) / lout (mA) for SETUP = 0 IRE: RSET (Q) = 3,025 • VREF (V) / lout (mA) When using an external current reference (Figure 7), the relationship between IREF and the full-scale output current on each output is: for SETUP =7.5 IRE: IREF (mA) =lout (mA) /3.195 for SETUP = 0 IRE: IREF (rnA) = lout (mA) /3.025 4 - 404 SECTION 4 Bt473 Pin Descriptions (continued) Pin Name Description COMP Compensation pin. If an external voltage reference is used (Figures 5 and 6), this pin should be connected to OPA. If an external current reference is used (Figure 7), this pin should be connected to IREF. A 0.1 J.1F ceramic capacitor must always be used to bypass this pin to VAA. The CaMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to PC Board Layout Considerations for critical layout criteria. VREF Voltage reference input. If a voltage reference is used (Figures 5 and 6), it must supply this input with a 1.2 V (typical) reference. If an external current reference is used (Figure 7), this pin should be left floating, except for the bypass capacitor. A 0.1 J.1F ceramic capacitor is used to decouple this input to GND, as shown in Figures 5 and 6. If the VAA supply is very clean, better performance may be obtained by decoupling VREF to VAA. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. OPA Reference amplifier output. If a voltage reference is used (Figures 5 and 6), this pin must be connected to CaMP. When using an external current reference (Figure 7), this pin should be left floating. VREFOur Voltage reference output. This output provides a 1.2 V (typical) reference, and may be connected directly to the VREF pin. If the on-chip reference is not used, this pin may be left floating. See Figures 5 and 6. Up to four Bt473s may be driven by this output. VM Analog power. All VAA pins must be connected. GND Analog ground. All GND pins must be connected. WR'" Write control input (TIL compatible). DO-D7 data is latched on the rising edge of WR"', and RSO-RS2 are latched on the falling edge of WR'" during MPU write operations. RD* and WR* should not be asserted simultaneously. See Figures 1 and 8. RD'" Read control input (TIL compatible). To read data from the device, RD'" must be a logical zero. RSO-RS2 are latched on the falling edge of RD'" during MPU read operations. RD'" and WR '" should not be asserted simultaneously. See Figures 1 and 8. RSO, RSl, RS2 Register select inputs (TIL compatible). RSO-RS2 specify the type of read or write operation being performed, as illustrated in Tables 1 and 2. DO-D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. CRO-CR3 Control outputs (TTL compatible). These outputs are used to control application-specific features. The output values are determined by the command register. See Figure 8. RAMDACs 4 ·405 - Bt473 Pin Descriptions (continued) 8 S l iii /I: ~ ;; Iii ~ t ~ ~ ~ ~ :: BO 43 VRBP BI 42 OPA B2 oil roMP B3 40 lRBP B4 BS 39 38 100 B6 37 lOR B7 36 VAAl VAA 3S VAA. VAA VAA • GND 34 33 GND 32 GND • 50 31 GND • 51 30 CR3 BLANK' 29 CR2 SYNC" 28 CRI 27 CRO ··· • CLOCK S ::: ~ ~ :!; !l :!! t:: ~ ~ ~ ~ ::I ~ <'iii ~ ~ ~ ~ 8 S S 8 i3 is is S ~ ~ 4 - 406 SECTION 4 0 ~ lQ :II ~ '"~ lOB VAA • Bt473 PC Board Layout Considerations PC Board Considerations Power Planes This product requires special attention to proper layout techniques to achieve optimum performance. Before beginning PCB layout, refer to the CMOS RAMDAC layout example found in Bt45117/8 Evaluation Module Operation and Measurements, application note (AN-16). This application note can be found in Brooktree's 1990 Applications Handbook. Separate digital and analog power planes are necessary. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt473 power pins, any reference circuitry, and COMP and reference decoupling. There should be at least a liS-inch gap between the digital power plane and the analog power plane. The layout should be optimized for lowest noise on the Bt473 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figures 5, 6, and 7. This bead should be located within 3 inches of the Bt473 and provides resistance to switching currents, acting as a resistance at high frequencies. A low-resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. A well-designed power distribution network is critical to eliminating digital switching noise. Ground planes must provide a low-impedance return path for the digital circuits. A minimum of a four-layer PC board is recommended with layers 1 (top) and 4 (bottom) for signals and layers 2 and 3 for power and ground. The optimum layout enables the Bt473 to be located as close to the power supply connector and as close to the video output connector as possible. Ground Planes For optimum performance, a common digital and analog ground plane with tub isolation (at least a 1I8-inch gap) and connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2-inches from the power supply connector to preserve digital noise margins during MPU read cycles. Thus, the ground tub isolation technique is constrained by the noise margin degradation during digital readback of the Bt473. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. For maximum performance, a separate isolated ground plane for the analog output termination resistors, RSET resistor, and reference circuitry (if used) should be used, as shown in Figures 5, 6, and 7. Another isolated ground plane is used for the GND pins of the Bt473 and supply decoupling capacitors. Plane-to-plane noise coupling can be reduced by ensuring that portions of the digital power and ground planes do not overlay portions of the analog power and ground planes, unless they can be arranged such that the plane-to-plane noise is common mode. Device Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Power Supply DecoupUng Best power supply decoupling performance is obtained with a 0.1 I!F ceramic capacitor decoupling each of the two groups of VAA pins to GND. For operation above 75 MHz. a 0.1 I!F capacitor in parallel with a 0.001 j.lF chip capacitor is recommended. The capacitors should be placed as close as possible to the device. The 10 I!F capacitor is for low-frequency power supply ripple; the 0.1 I!F capacitors are for high-frequency power supply noise rejection. RAMDACs 4 - 407 .. Bt473 PC Board Layout Considerations (continued) A linear regulator to filter the analog power supply is recommended if the power supply noise is ~ 200 m V or greater than 10 LSBs. This is especially important when a switching power supply is used and the switching frequency is close to the raster scan frequency. Note that about 10% of the power supply hum and ripple noise less than I MHz will couple onto the analog outputs. COMP DecoupUng The COMP pin must be decoupled to VAA, typically using a O.II!F ceramic chip capacitor. Low-frequency supply noise will require a larger value. Lead lengths should be minimized for best performance. Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge speeds (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals. Ensure that the power pins for the clock driver are properly decoupled to minimize transients. Minimize edge speeds and ringing, using damping resistors (10 to 50 Q) or parallel termination where necessary. If using parallel termination on digital signals, the resistors should be connected to the digital power and ground planes, not the analog power and ground planes. If the display has a "ghosting" problem, additional capacitance in parallel with the COMP capacitor may help to fix the problem. Digital Signal Interconnect The digital inputs to the Bt473 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power and ground planes. Most noise on the analog outputs will be caused by excessive edge speeds (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The digital edge speeds should be no faster than necessary, as feedthrough noise is proportional to the digital edge speeds. Lower speed applications will benefit from using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission line mismatch will exist if the line length reflection time is greater than 1/4 the signal edge time, resulting in ringing, overshoot, and undershoot that can generate noise onto the analog outputs. Line termination or reducing the line length is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (10 to 50 Q). Analog Signal Interconnect The Bt473 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog outputs should have a source load resistor equal to the destination termination (via a clean isolated ground return path). The load resistor connection between the current output and GND should be as close as possible to the Bt473 to minimize reflections. Unused analog outputs should be connected to GND. Analog edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent Simple pulse filters can reduce ghosts. high-frequency energy, reducing EMI and noise. Analog Output Protection The Bt473 analog outputs should be protected against high-energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figures 5, 6, and 7 can prevent latchup under severe discharge conditions without adversely degrading analog tranSItion times. The IN4148/9 parts are low-capacitance, fast-switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7001). 4· 408 SECTION 4 Bt473 PC Board Layout Considerations (continued) Bt473 Ll +sv (Vcq C2-C3 + C6 Cl ~--""""""""""""""""--"""""""~.GROUND (poWER SUPPLY CONNECTOR) R1 R2 R3 !REP lOR .. TO VIDEO CONNECTOR lOG lOB VAA G IN4148/9 DAC OIlTPllT TO MONITOR IN4148/9 GND Location Description C1-C5 C6 L1 RI. R2. R3 0_1 IlF ceramic capacitor 10 IlF tantalwn capacitor ferrite bead 75 n 1% metal film resistor I % metal film resistor RSET Vendor Part Nwnber Erie RPE 112Z5U1 04M50V Mallory CSRI3G106KM Fair-Rite 2743001111 Dale CMF-55C Dale CMF-55C Note: The vendor numbers above are listed only as a guide_ characteristics will not affect the performance of the Bt473_ Figure 5. Substitution of devices with similar Typical Connection Diagram and Parts List (Internal Voltage Reference). RAMDACs 4 • 409 Bt473 PC Board Layout Considerations (continued) ANALOG POWER PLANE Bt473 +SV(VCC) ~. . . . . . . . . . . . . . . . . . . . . . . .~. . . . . . . . . . . . . . . . . . . . . . . .~~ GROUND (POWER SUPPLY CONNEcroR) RSET R1 R2 R3 !REF lOR P TO VIDEO CONNEcroR lOG lOB VAA 0 IN4148/9 DAC OUTPUT TO MONITOR IN4148/9 GND Location Description CI-C5 C6 L1 Rl. R2. R3 R4 RSEr ZI 0.1 !1F ceramic capacitor 10 ~F tantalum capacitor ferrite bead 75 Q 1% metal film resistor lk Q 5% resistor 1% metal film resistor 1.2 V voltage reference Vendor Part Nwnber Erie RPEl12Z5UI04M50V Mallory CSR13G106KM Fair-Rite 2743001111 Dale CMF-55C Dale CMF-5SC National Semiconductor LM385BZ-1.2 Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the Bt473. Figure 6. 4 • 410 SECTION 4 Substitution of devices with similar Typical Connection Diagram and Parts List (External Voltage Reference). Bt473 PC Board Layout Considerations (continued) ANALOG POWER PLAN!! Bt473 LI +SV (VCC) RSBT= 1.22/1REF C6 GND~""""""""~""""""""""""""__"~. GRmrnD (POWER SUPI'LY CONNECTOR) 10Rr---------+---~--+_----__{ 100 .. TO VIDEO r----------------+_----__{ CONNECTOR 10Br-----------------~----__{ o VAA IN4148/9 DAC TO MONITOR 01ITPlIT IN4148/9 GND Location Description CI-C5 C6 C7. C8 L1 Rl. R2. R3 ZI 0.1 JlF ceramic capacitor 10 JlF tantalum capacitor 1 JlF capacitor ferrite bead 75 n 1% metal film resistor adjustable regulator 1% metal film resistor RSEf Vendor Part Number Erie RPEl12Z5UI04M50V Mallory CSR13G106KM Mallory CSR13G105KM Fair-Rite 2743001111 Dale CMF-55C National Semiconductor LM337LZ Dale CMF-SSC Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the Bt473. Figure 7. Substitution of devices with similar Typical Connection Diagram and Parts List (External Current Reference). RAMDACs 4·411 Bt473 Application Information Using Multiple Devices Reference Selection When using multiple Bt473s, each Bt473 should have its own power plane ferrite bead. An external voltage reference provides about lOx better power supply rejection on the analog outputs than an external current reference. Although the VREF OUT of a Bt473 may drive up to four Bt473s, higher performance may be obtained if each RAMDAC uses its own reference. This will reduce the amount of color channel crosstalk: and color palette interaction. Each Bt473 must still have its own individual RSET resistor, analog output termination resistors, power supply bypass capacitors, COMP capacitor, and reference capacitors. ESD and Latchup Considerations Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. Ail logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay VAA power to the device. Ferrite beads must only be used for analog power V AA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. 4·412 SECTION 4 Bt473 Recommended Operating Conditions Parameter Symbol Power Supply 80, 66 MHz Parts 50, 35 MHz Parts Ambient Operating Temperature Output Load Voltage Reference Configuration Reference Voltage Current Reference Configuration IREF Current Standard RS-343A PS/2 Compatible VAA TA RL VREF Min Typ Max Units 4.75 4.5 0 5.00 5.00 5.25 5.5 +70 Volts Volts °C Ohms 37.5 1.14 1.235 1.26 Volts -3 -3 -8.39 -8.88 -10 -10 rnA rnA Min Typ Max Units 7.0 Volts VAA+0.5 Volts +125 +150 +150 °C °C °C 220 °C !REF Absolute Maximum Ratings Parameter Symbol VAA (measured to GND) Voltage on Any Signal Pin* GND--O.5 Analog Output Short Circuit Duration to Any Power Supply or Common ISC Ambient Operating Temperature Storage Temperature Junction Temperature TA 1S TJ Vapor Phase Soldering (1 minute) TVSOL indefinite -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. RAMDACs 4-413 Bt473 DC Characteristics Parameter Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Using External Reference Using Internal Reference Monotonicity Coding Digital Inputs Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Vin = 2.4 V) Digital Outputs Output High Voltage (IOH = -400 jlA) Output Low Voltage (IOL = 3.2 rnA) 3-State Current (OO-D7) Output Capacitance See test conditions on next page. 4 • 414 SECTION 4 Symbol Min Typ Max Units 8 8 8 Bits ±1 ±1 LSB LSB ±S ±10 % Gray Scale % GrayScale IL II.. guaranteed Binary VIH VlL 2.0 GND--O.S IIH IlL C1N VOH VAA+O.S 0.8 1 -1 7 2.4 Volts Volts IIA IIA pF Volts VOL 0.4 Volts ICYZ SO 7 IIA CDOUT pF Bt473 DC Characteristics (continued) Parameter Symbol Analog Outputs Gray Scale Current Range Output Current (Standard RS-343A) White Level Relative to Black Black Level Relative to Blank SETUP = 7.5 IRE SETUP = oIRE Blank Level Sync Level LSB Size DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 rnA) VOC RAOUT CAOUT Min VREFOUT IREFOUT Power Supply Rejection Ratio* (COMP = 0.1 IiF, f = 1 KHz) Max Units 20 rnA 16.74 17.62 18.50 rnA 0.95 0 6.29 0 1.44 5 7.62 5 69.1 2 1.90 50 8.96 50 rnA 5 +1.5 30 % Volts kn pF 1.32 Volts -1.0 10 IVREF Voltage Reference Input Current Reference Output Voltage Reference Output Current Typ 1.08 10 1.2 100 ~ ~ ~ ~ 0.5 PSRR ~ rnA %/%tNAA Test conditions to generate RS-343A standard video signals (unless otherwise specified): "Recommended Operating Conditions" using external voltage reference with RSET = 140 n, VREF = 1.235 V. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. Note: When using the internal voltage reference, RSET may need to be adjusted to meet these limits. Also, the "gray-scale" output current (white level relative to black) will have a typical tolerance of ±10% rather than the ±5% specified above. *Guaranteed but not tested. Analog Output Levels - PS/2 Compatibility Parameter Analog Outputs Output Current White Level Relative to Black Black Level Relative to Blank SETUP = 7.5 IRE SETUP =oIRE Blank Level Sync Level Symbol Min Typ Max Units 18.00 18.65 20.00 rnA 1.01 0 6.6 0 1.51 5 8 5 2.0 50 9.4 50 rnA ~ rnA ~ Test conditions to generate PS/2 compatible video signals (unless otherwise specified): "Recommended Operating Conditions" using external voltage reference with RSET = 140 n, VREF = 1.235 V or external current reference with IREF = -8.88 rnA. RAMDACs 4 • 415 .. Bt473 AC Characteristics 80 MHz Devices Parameter Symbol Clock Rate Min Typ Fmax 66 MHz Devices Max Min Typ 80 RSO-RS2 Setup Time RSO-RS2 Hold Time 1 2 10 10 RD* Asserted to Data Bus Driven RD* Asserted to Data Valid RD* Negated to Data Bus 3-Stated Read Data Hold Time 3 4 5 6 3 Write Data Setup Time Write Data Hold Time CRO-CR3 Output Delay Max Units 66 MHz 10 10 ns ns 3 40 20 40 20 ns ns ns ns 5 5 7 8 9 10 10 10 10 RD*, WR* Pulse Width Low RD*, WR * Pulse Width High 10 11 50 4*p14 50 4*p14 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 12 13 3 3 3 3 ns ns Clock Cycle Time (pI4) Clock Pulse Width High Time Clock Pulse Width Low Time 14 15 16 12.5 4 4 15.15 5 5 ns ns ns Analog Output Delay Analog Output Rise!Fall Time Analog Output Settling Time* Clock and Data Feedthrough* Glitch Impulse* DAC-to-DAC Crosstalk Analog Output Skew 17 18 19 Pipeline Delay IAA See test conditions on next page. 4 - 416 30 4 VAA Supply Current** SECTION 4 100 100 3 13 -30 150 -23 0 2 4 4 180 250 30 4 ns ns ns 3 13 -30 150 -23 0 2 ns ns ns dB pV - sec dB ns 4 4 Clocks 180 250 rnA Bt473 AC Characteristics (continued) 35 MHz Devices 50 MHz Devices Parameter Clock Rate Symbol Min Typ Max Typ Min 50 Fmax Max Units 35 MHz RSO-RS2 Setup Time RSO-RS2 Hold Time 1 2 10 10 RD* Asserted to Data Bus Driven RD* Asserted to Data Valid RD* Negated to Data Bus 3-Stated Read Data Hold Time 3 4 5 6 3 5 5 Write Data Setup Time Write Data Hold Time CRO-CR3 Output Delay 7 8 9 10 10 10 10 RD*, WR* Pulse Width Low RD*, WR* Pulse Width High 10 11 50 4*p14 50 4*p14 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 12 13 3 3 3 3 ns ns Clock Cycle Time (pI4) Clock Pulse Width High Time Clock Pulse Width Low Time 14 15 16 20 6 6 28 7 9 ns ns ns Analog Output Delay Analog Output RiseIFall Time Analog Output Settling Time* Clock and Data Feedthrough* Glitch Impulse* DAC-to-DAC Crosstalk Analog Output Skew 17 18 19 Pipeline Delay VAA Supply Current** 3 40 20 40 20 100 100 2 4 4 180 220 4 ns ns ns 2 ns ns ns dB pV - sec dB ns 4 4 Clocks 180 220 rnA 30 13 -30 150 -23 0 ns ns ns ns 3 13 -30 150 -23 0 30 3 4 IAA ns ns 10 10 Test conditions (unless otherwise specified): "Recommended Operating Conditions" using external voltage reference with RSET = 140 n, VREF = 1.235 V. TTL input values are 0-3 V, with input rise/fall times ~ 4 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ~ 10 pF, DO-D7 output load ~ 75 pF. See timing notes in Figure 9. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the digital inputs have a 1 kn resistor to ground and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 2x clock rate. **At Fmax. IAA (typ) at VAA = 5.0 V. IAA (max) at VAA (max). RAMDACs 4 • 417 Bt473 Timing Waveforms I I I 2 VALID RSO, RSI, RS2 RD"', WR'" 4 * ~ DO • D7 (READ) 11 - J-S DATAOIIT(RD'=O) '" -1 DO • D7 (WRITE) 10 - /' 1--6 DATA IN (WR'=0) 7 -8 CRO·CR3 Figure 8. I t-9 MPU Read/Write Timing. (LOCK RO·R7, GO· en, 80·87, OLO· 01.3, SO, SI, SYNC*, BLANK'" lOR, lOG, lOB Note 1: Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition, Note 2: Settling time measured from the 50% point of full-scale transition to the output remaining within ±1 LSB. Note 3: Output rise/fall time measured between the 10% and 90% points of full-scale transition. Figure 9. 4 • 418 SECTION 4 Video Input/Output Timing. BnxKtreeQP Bt473 Ordering Information Ambient Temperature Range Model Number Speed Package Bt473KPI80 so MHz 68-pin Plastic I-Lead O· to +70· C Bt473KPI66 66 MHz 68-pin Plastic I-Lead O· to +70· C Bt473KPI50 so MHz 68-pin Plastic I-Lead O· to +70· C Bt473KPI35 35 MHz 68-pin Plastic I-Lead O· to +70· C RAMDACs 4 - 419 Bt473 Revision History Datasheet Revision 4 - 420 Change from Previous Revision F AC parameters: RD* asserted to data bus driven time changed from 5 ns to 3 ns; maximum VAA supply current changed from 220 rnA to 250 rnA for 80 and 66 MHz devices. G Expanded PC Board Layout section. H Modified PC Board Layout recommendations. Modified Sync. SECTION 4 Advance Information This document contains information on a product under development. The parametric information contains target parameters and is subject to change. Distinguishing Features Applications • • • • • • • • • • • • • • • • • • 85, 66 MHz Pipelined Operation 4:1 Multiplexed Pixel Ports VGA Pass-through Option via Overlays Triple 8-bit D/A Converters 256 x 24 Color Palette RAM 15 x 24 Overlay Color Palette Optional Sync on All Three Channels 0 or 7.5 IRE Blanking Pedestal Voltage or Current Reference Analog Output Comparators Anti -S parlde Circuitry Power-Down Mode 84-pin PLCC Package High-Resolution Color Graphics CAE/CAD/CAM Image Processing Instrumentation Desktop Publishing 85 MHz Monolithic CMOS 256 x 24 Color Palette RAMDAC™ Product Description The Bt474 RAMDAC is designed specifically for high-performance color graphics. Included are four byte-wide pixel input ports (multiplexed 4:1), a 256 x 24 color lookup table with triple 8-bit video D/A converters (configurable for either 6-bit or 8-bit D/A converter operation), and four overlay input ports (multiplexed 4:1) for supporting overlay/cursor information. The 4: 1 multiplexed pixel ports ease interfacing to a high-resolution graphics frame buffer. Functional Block Diagram VRBP SCLIt Bt474 IRBP Cl..ClCI(...O a.ocIC,J OPA COMP lOR PO-P7IA-D} The Bt474 may alternately be configured for a lower performance VGA mode, where 8 bits of VGA pixel data (from a VGA controller) are input via two of the overlay input ports and displayed. IIlO OI.D-OLI IA-D} lOB OU.-OUIA-D} OR VGADATA ODD/BVIlN" BLANK* CSYNC" VSYNC 00-D7 Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 lA74001 Rev. B ROO WR· RSO-RS3 4 - 421 The Bt474 generates RS-343A compatible video signals into a doubly terminated 75 n load, and RS-170 compatible video signals into a singly terminated 75 n load, without requiring external buffering. .. Bt474 Circuit Description MPU Inter/ace Writing Overlay Color Data As illustrated in the functional block diagram. the Bt474 supports a standard MPU bus interface. allowing the MPU direct access to the color palette RAM. MPU data is transferred into and out of the Bt474 via the DO-07 data pins. The read/write timing is controlled by the RO* and WR* inputs. To write overlay color data, the MPU writes the address register (overlay write mode) with the address of the overlay location to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using RSO-RS3 to select the overlay registers. After the blue write cycle, the 3 bytes of color information are concatenated into a 24-bit word and written to the overlay location specified by the address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. A block of color values in consecutive locations may be written to by writing the start address and performing continuous R, 0, B write cycles until the entire block has been written. The RSO-RS3 select inputs specify which control register the MPU is accessing. as shown in Tables 1 and 2. The 8-bit address register is used to address the color palette RAM, eliminating the requirement for external address multiplexers. ADORO corresponds to 00 and is the least significant bit Writing Color Palette RAM Data To write color data, the MPU writes the address register (RAM write mode) with the address of the color palette RAM location to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using RSO-RS3 to select the color palette RAM. After the blue write cycle, the 3 bytes of color information are concatenated into a 24-bit word and written to the location specified by the address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green. and blue data. A block of color values in consecutive locations may be written to by writing the start address and performing continuous R, 0, B write cycles until the entire block has been written. Refer to Figure 15 for MPU read write timing. Reading Color Palette RAM Data To read color palette RAM data, the MPU loads the address register (RAM read mode) with the address of the color palette RAM location to be read. The contents of the color palette RAM at the specified address are copied into the ROB registers and the address register is incremented to the next RAM location. The MPU performs three successive read cycles (8 bits each of red, green, and blue). using RSO-RS3 to select the color palette RAM. Following the blue read cycle, the contents of the color palette RAM at the address specified by the address register are copied into the ROB registers and the address register again increments. A block of color values in consecutive locations may be read by writing the start address and performing continuous R, 0, B read cycles until the entire block has been read. Reading Overlay Color Data To read overlay color data. the MPU loads the address register (overlay read mode) with the address of the overlay location to be read. The contents of the overlay register at the specified address are copied into the ROB registers and the address register is incremented to the next overlay location. The MPU performs three successive read cycles (8 bits each of red. green, and blue), using RSO-RS3 to select the overlay registers. Following the blue read cycle, the contents of the overlay location at the address specified by the address register are copied into the RSO -RS3 Access Addressed by MPU $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $0 $E $F R/W R/W R/W R/W R/W R/W address register (RAM write mode) color palette RAM pixel read mask register address register (RAM read mode) address register (overlay write mode) overlay registers reserved address register (overlay read mode) command register_O command registecl ID register ($ll) status register reserved reserved reserved reserved - R/W R/W R/W read only read only Table I. 4 ·422 SECTION 4 - Control Input Truth Table. BllXKtree~ Bt474 Circuit Description (continued) ROB registers and the address register again increments. A block of color values in consecutive locations may be read by writing the start address and performing continuous R, 0, B read cycles until the entire block has been read. 6-Bit I B-Bit Operation Additional In/ormation For 8-bit operation, DO is the LSB and 07 is the MSB of color data. The command bit CROI is used to specify whether the MPU is reading and writing 8 bits or 6 bits of color information each cycle. When accessing the color palette RAM, the address register resets to $()() following a blue read or write cycle to RAM location $FF. For 6-bit operation, color data is contained on the lower 6 bits of the data bus, with DO being the LSB and 05 the MSB of color data. When writing color data, 06 and 07 are ignored. During color read cycles, D6 and 07 are a logical zero. The MPU interface operates asynchronously to the pixel clock. Data transfers between the color palette RAM and the color registers (R, 0, and B in the block diagram) are synchronized by internal logic, and occur in the period between MPU accesses. To reduce noticeable sparkling on the CRT screen during MPU access to the color palette RAMs, internal logic maintains the previous output color data on the analog outputs while the transfer between lookup table RAMs and the ROB registers occurs. Note that in the 6-bit mode, the Bt474's full-scale output current will be about 1.5% lower than when in the 8-bit mode. This is due to the two LSBs of each 8-bit DAC always being a logical zero in the 6-bit mode. Power-Down Mode To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADORa, ADDRb) that count modulo three. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The MPU does not have access to these bits. The MPU may read the address register at any time without modifying its contents or the existing read/write mode. Value ADORa, b (counts modulo 3) ADDR0-7 (counts binary) Table 2. The Bt474 incorporates a power-down capability, controlled by command bit CR03. While command bit CR03 is a logical zero, the Bt474 functions normally. While command bit CR03 is a logical one, the DACs and power to the RAM are turned off. Note that the RAM still retains the data. Also, the RAM may be read or written to by the MPU as long as the pixel clock is running. The RAM automatically powers up during MPU read/write cycles, and shuts down when the MPU access is completed. SCLK is forced into the three-state mode, bidirectional buses are forced to be inputs, the DACs output no current, and the two command registers may still be written to or read by the MPU. Note that the output DACs require about one second to tum off (sleep mode) or tum on (normal). RS2 RSI RSO red value green value blue value 00 01 10 $OO-$FF xxxx 0000 xxxx 0001 : xxxx 1111 Addressed by MPU 0 1 1 : 1 0 0 0 : 0 1 1 1 : 1 color palette RAM reserved overlay color 1 : overlay color 15 Address Register (ADDR) Operation (RS3 = 0). RAMDACs 4 - 423 Bt474 Circuit Description (continued) The DACs will be turned off during sleep mode only if a voltage reference (internal or external) is used. If using an external current reference, external circuitry should turn the current reference off (IREF = 0 rnA) during sleep mode. When using an external voltage reference, external circuitry should turn off the voltage reference (VREF = o V) to further reduce power consumption due to biasing of portions of the internal voltage reference. Frame BUffer Clocking The Video DRAM shift clock (SCLK) is generated by the Bt474. SCLK is 1/4 the pixel clock rate in overlay modes 2 and 3. In overlay modes 0 and I, SCLK is equal to the pixel clock rate. PO-P7 (A-D) are pixel data (8 bits per pixel) for four horizontally consecutive pixels. PO-P7 (A-D) are always latched on the rising edge of SCLK. The pixel clock is specified to be either CLOCK_O or CLOCK_l by command bit CR12. Frame Buffer Pixel Port Inter/ace There are four 8-bit pixel ports, PO-P7 (A-D), used to interface to the frame buffer memory. Video input data ports A through D are designated in this manner to represent the order of pixel data presentation. Port A always corresponds to the first pixel of the rust line of the display. This would be the rust pixel fed to the analog outputs, followed by B, then C, and rmally D, repeating the pattern ABCD, ABCD, ABCD, etc. until the first scan line is completely displayed. At this point, the output sequence is dependent on the CROS command bit and the ODD/EVEN* input, i.e... whether interlaced or noninterlaced operation is selected, the current field being displayed, and whether or not an interleaved frame buffer memory is being used. 4 - 424 SECTION 4 Scan line 0 is always displayed first in the interlaced mode and is considered the rust line of the EVEN field. In the noninterlaced mode, scan line 1 immediately follows scan line O. In the interlaced mode, scan line 1 is considered to be the rust line of the ODD field and is displayed only after the entire EVEN field has been displayed. Tables 3 and 4 demonstrate the display sequence. Table 3 shows the display sequence for interleaved frame buffer memory, while Table 4 shows the display sequence for noninterleaved frame buffer memory. The CROO control bit determines whether or not the Bt474 uses an interleaved frame buffer memory configuration. Figures 1 through 9 and Tables 3 and 4 show the interlaced and noninterlaced display timing including the interleave operation. Pixel Read Mask Each pixel clock cycle, PO-P7 pixel data is bit-wise logically ANDed with the contents of the pixel read mask register. The result is used to address the 256 x 24 color palette RAM. The addressed location provides 24 bits of color information to the three D/A converters. Bt474 Circuit Description (continued) PIXEL TIMES PIXELCLK PIXEL PORT # SCLK BLANK' J J ODD/EVEN' Figure 1. DONT CARE Timing, Interleaved (CROO 1), Noninterlaced (CROS 0), Scan Line O. PIXEL TIMES PIXELCLK PIXEL PORT # SCLK BLANK" ODD/EVEN* Figure 2. J J L....----JI DONTCARE Timing, Interleaved (CROO = 1), Noninterlaced (CROS 0), Scan Line 1. RAMDACs 4 • 425 - Bt474 Circuit Description (continued) PIXEL TIMES PIXELCLK PIXEL PORT # SCLK BLANK* IclnlAIBlclnlAIBlcl J J onn/EVEN* Figure 3. ~l DON'T CARE Timing, Interieaved (CROO 1), Noninterlaced (CROS 0), Scan Line 2. PIXEL TIMES PIXELCLK PIXEL PORT # SCLK BLANK" InlAIB IclnlAIB Ic In I J J Onn/EVEN" Figure 4. 4·426 Timing, Interleaved (CROO SECTION 4 ~---ll DON'T CARE 1), Noninterlaced (CROS = 0), Scan Line 3. Bt474 Circuit Description (continued) PIXEL TIMES PlXELCLK PlXELPOKr' SCLK BLANK· J J ,-----,I ODD/EVEN· Figure S. Timing, Interlealled (CROO = 1), Interlaced (CROS = 1), Even Field, Scan Line O. PIXEL TIMES PlXELCLK PIXEL PORT II SCLK BLANK· J J ODD/EVEN· Figure 6. Timing, Interlealled (CROO = 1), Interlaced (CROS = 1) Ellen Field, Scan Line 2. RAMDACs 4 ·427 Bt474 Circuit Description (continued) P1XELTIMHS PIXELCLK PIXEL PORT II SCLK BLANK· J J ODD/EVEN· Figure 7. Timing, Interleaved (CROO = 1), Interlaced (CROS = 1), Odd Field, Scan Line 1. PlXELTIMHS PlXELCLK PIXEL PORT II SCLK BLANK· J "-----,I J ODD/EVEN· Figure 8. 4 • 428 Timing, Interleaved (CROO = 1), Interlaced (CROS = 1), Odd Field, Scan Line 3. SECTION 4 Bt474 Circuit Description (continued) .. CR05 ODD/EVEN* Scan Line # 0 0 0 0 x x x x 0 0 0 0 0 x x x x Pixel Port Access Sequence Noninterlaced 2 3 ABCD BCDA CDAB DABC ABCD BCDA CDAB DABC ABCD ... BCDA... CDAB ... DABC ... 4 5 6 7 ABCD BCDA CDAB DABC ABCD BCDA CDAB DABC ABCD ... BCDA... CDAB ... DABC ... 0 0 0 0 0 2 4 6 ABCD CDAB ABCD CDAB ABCD CDAB ABCD CDAB ABCD ... CDAB ... ABCD ... CDAB ... 1 1 1 1 1 3 5 7 BCDA DABC BCDA DABC BCDA DABC BCDA DABC BCDA ... DABC ... BCDA ... DABC ... 1 Interlaced, Even Field 1 1 1 1 Interlaced, Odd Field 1 1 1 1 Table 3. Interleaved Operation (CROO = I). RAMDACs 4 - 429 Bt474 Circuit Description (continued) N oninterlaced LINE 0 LINEl LINEN Interlaced Figure 9. CROS even odd even odd LINE 0 LINEl LINE 2 LINE 3 odd UNEN Interlaced I Noninterlaced Display Operation. ODDIEYEN* Scan Line # 0 0 0 0 x x x x 0 1 0 0 0 0 x x x x Pixel Port Access Sequence Noninterlaced 2 3 ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD 4 5 ABCD 6 ABCD ABCD ABCD 7 ABCD ABCD ABCD ABCD 0 ABeD 2 4 ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD Interlaced, Even Field 1 1 1 1 0 0 0 0 6 ABCD ABCD ABCD ABCD Interlaced, Odd Field 1 1 1 1 1 1 1 1 Table 4. 4·430 SECTION 4 1 3 S 7 ABCD Noninterleaved Operation (CROO = 0). ABCD ABCD Bt474 Circuit Description (continued) Overlay Operation Mode 0 Operation The four 4-bit overlay inputs, OLO-OL3 (A-D), are used to input overlay and other information. OLO, OLl, OL2, and OL3 inputs each have a read mask bit (CRI4, CRI5, CRI6, and CRl7, respectively). The mask bits are logically ANDed with the respective overlay bit after the overlay mode circuitry. In mode 0, the OL2 and OL3 inputs are used to input VGA pixel data from a VGA controller, while the OLO and OLI inputs are used to provide overlay (or a three-color cursor) information. (See Table 6.) As shown in Table 5, the overlay inputs may be configured to operate in four different modes, as determined by the CRI0 and CRll command bits. In this mode, the PO-P7 pixel inputs are ignored-pixel data is input using both OL2 and OL3 (as OL2 and OL3 provide a total of eight inputs, 8 bits per pixel of VGA pixel data may be input). The selected clock input (CLOCK_O or CLOCK_I) is output directly onto SCLK (without dividing by four) since the VGA pixel inputs will be input using a 1:1 multiplex mode. CLOCK_O should be selected as the pixel clock while in this mode . Note the overlay inputs are never interleaved. .. Mode CRll CRIO OL3 (A-D) OL2 (A-D) OLl (A-D) OLO (A-D) 0 0 0 VGA data (4 bits) VGA data (4 bits) cursor data cursor data I 0 1 VGA data (4 bits) VGA data (4 bits) cursor enable cursor data 2 1 0 cursor data cursor data cursor data cursor data 3 1 I cursor enable cursor data cursor enable cursor data Table 5. Overlay Configurations. VGAData No Overlay 3-Color Overlay Overlay Data OL3D,OL3C,OL3B,OL3A OL2D,OL2C,OL2B,OL2A OLI OLO Color Palette Addressed 0000 0000 : 1111 0000 0001 : 1111 0 0 0 0 : : 0 0 color palette RAM location $00 color palette RAM location $01 : color palette RAM location $FF xxxx xxxx xxxx xxxx xxxx xxxx 0 1 1 1 0 1 overlay color 1 overlay color 2 overlay color 3 Table 6. Mode 0 (VGA Mode, 3-Color Overlay) Overlay Configuration. RAMDACs 4 - 431 Bt474 Circuit Description (continued) VGAData Overlay Data OL3D,OL3C,OL3B,OL3A OL2D,OL2C,OL2B,OL2A OLl OW Color Palette Addressed 0000 0000 : 1111 0000 0001 : 1111 0 0 : 0 x x x color palette RAM location $00 color palette RAM location $01 : color palette RAM location $FF xxxx xxxx xxxx xxxx 1 1 0 1 overlay color 2 overlay color 3 No Overlay 2-Color Overlay Table 7. : Mode 1 (VGA Mode, 2-Color Overlay) Overlay Configuration. Overlay Data Video OL3-OLO P7-PO Color Palette Addressed 0000 0000 0000 0000 00000001 No Overlay 15 Color Overlay Table 8. : : 0000 1111 1111 color palette RAM location $00 color palette RAM location $01 : color palette RAM location $FF 0001 0010 : 1111 xxxx xxxx xxxx xxxx overlay color 1 overlay color 2 : : xxxx xxxx overlay color 15 Mode 2 (1S-Color Overlay) Overlay Configuration. Enable Data Enable Data 0L3 0L2 OLl OW Color Palette Addressed No Overlay 0 x 0 x color palette RAM location specified by PO--P7 Dual 2-Color Overlays 0 0 1 1 x x 1 1 0 0 0 1 overlay color 2 overlay color 3 overlay color 8 overlay color 12 1 1 1 1 1 1 1 1 0 Overlay Collisions Table 9. 4 - 432 0 1 0 0 1 1 x x 1 0 1 overlay overlay overlay overlay color color color color 10 11 14 15 Mode 3 (Dual 2-Color Overlays) Overlay Configuration. SECTION 4 Bt474 Circuit Description (continued) Mode 1 Operation Video Generation In mode 1, the OL2 and OL3 inputs are used to input VGA pixel data from a VGA controller, while the OLO and OLI inputs are used to provide overlay (or a two-color cursor) information. (See Table 7.) The CSYNC* and BLANK* inputs, also latched on the rising edge of SCLK to maintain synchronization with the color data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figures 10 and 11. Tables 10 and 11 detail how the CSYNC* and BLANK* inputs modify the output levels. In this mode, the PO-P7 pixel inputs are ignored -pixel data is input using both OL2 and OL3 (as OL2 and OL3 provide a total of eight inputs, 8 bits per pixel of VGA pixel data may be input). The selected clock input (CLOCK_O or CLOCK_I) is output directly onto SCLK (without dividing by four) since the VGA pixel inputs will be input using a 1:1 multiplex mode. CLOCK_O should be selected as the pixel clock while in this mode. Mode 2 Operation In the normal overlay mode (mode 2), 4 bits of overlay (or cursor) information are used to enable 15 overlay colors to be displayed. If OLO-OL3 = 0000, PO-P7 pixel data is displayed; otherwise overlay data is displayed. Table 8 shows the pixel and overlay color palette selection for this mode. In this mode, OLO-OL3 (A-D) are latched on the rising edge of SCLK and have the same timing as the PO-P7 (A-D) pixel data. SCLK is 1/4 the selected pixel clock (CLOCK_O or CLOCK_I). Mode 3 Operation In mode 3, two two-color cursors may be displayed. Table 9 shows the operation of the pixel and overlay inputs in this mode. Note that OL3 and OL2 are logically ANDed together, while OLl and OLO are logically ANDed together. Thus, OLl and OL3 become configured as enable bits for OLO and OL2, respectively. The CR04 command bit is used to specify whether a 0 or 7.5 IRE blanking pedestal is to be used. Command bit CR06 specifies whether or not the RGB outputs contain sync information. The analog outputs of the Bt474 are capable of directly driving a 37.5 n load, such as a doubly terminated 75 n coaxial cable. ESD and Latchup Considerations Correct ESD-sensitive handling procedures are required to prevent device damage, wltich can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay V AA power to the device. Ferrite beads must only be used for analog power V AA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all V AA pins are at the same potential, and that the V AA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. In this mode, OLO-OL3 (A-D) are latched on the .a:~sik1g edge of seLK ~,d ha;"e the :;aile tir:li:1g as the PO-P7 (A-D) pixel data. SCLK is 1/4 the selected pixel clock (CLOCK_O or CLOCK_I). RAMDACs 4 - 433 .. Bt474 Circuit Description (continued) NO SYNC MA SYNC V V MA 19.OS 0.714 26.67 1.000 -.----~._--------------------~~------wmrnu~ 1.44 0.054 9.05 0.340 +-----------;--------+--------------- BLACK U~ 0.00 0.000 7.62 0.286 +----------'-....-,--"'------------ 7.5 IRE BLANK LEVEL 40 IRE ~ 0.00 Note: 75 levels. 0.000 ______________ n doubly terminated load, VREF = Figure 10. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SYNCUVEL 1.235 V, RSET = 147 n. RS-343A levels and tolerances assumed on all Composite Video Output Waveforms (SETUP Sync Disabled Sync Enabled lout (mA) Iout(mA) 19.05 data + 1.44 data + 1.44 1.44 1.44 0 0 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 Description WHITE DATA DATA-SYNC BLACK BLACK-SYNC BlANK SYNC Note: 75 Table 10. 4·434 ~-L = 7.5 CSYNC* BlANK* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx n doubly terminated load. VREF = 1.235 V, RSET = 147 n. Video Output Truth Table (SETUP = 7.5 IRE). SECTION 4 IRE). Bt474 Circuit Description (continued) NO SYNC MA SYNC V MA V 17.62 0.660 25.24 0.950 - , - - - - - , . . . - - - - - - - - - - - - - - . : ; ; : : : - - - - WHITE LEVEL 0.00 0.000 7.62 0.286 -r-----~--~~--~--------BUCKffl~llVEL 0.00 0.000 0.00 0.000 ~-------~-L----------SYNCLEVEL 43 IRE Note: 75 levels. n doubly terminated load, VREF = 1.235 V, RSET = 147 n. Figure 11. RS-343A levels and tolerances assumed on all Composite Video Output Waveforms (SETUP = 0 IRE). Sync Disabled Sync Enabled lout (mA) lout (mA) 17.62 25.24 data + 7.62 data 7.62 0 7.62 0 Description WHITE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC Note: 75 Table 11. data data 0 0 0 0 n doubly terminated load, CSYNC* BLANK* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx VREF = 1.235 V, RSET = 147 n. Video Output Truth Table (SETUP o IRE). RAMDACs 4 • 435 .. Bt474 Internal Registers Command Register_O This register may be written to or read by the MPU at any time and is not initialized. CROO corresponds to data bus bit DO, the least significant data bit. CR07 reserved (logical one) A logical one must be written to this bit when writing to the command register. CR06 Sync enable This bit specifies whether the RGB outputs are to contain sync information or not. (0) no sync (1) sync CROS Display mode select (0) noninteriace (1) interlace CR04 Setup select This bit specifies whether the display is interlaced or noninterlaced and selects the appropriate interleave patterns. This bit specifies whether the lOR, lOG, and lOB outputs contain a 0 or 7.S IRE blanking pedestal. (0) OIRE (1) 7.S IRE CR03 Power down enable (0) normal operation (1) reduce power CR02 Nibble swap (0) normal input (I) swap MSN and LSN CROI Color value select While this bit is a logical zero, the Bt474 functions normally. If this bit is a logical one, the DACs and power to the RAM are turned off. The RAM still retains the data and CPU reads and writes can occur with no loss of data. When set, this bit swaps the two nibbles of color data addressing the color palette RAM. This bit affects only pixel ports PO--P7 {A-D}. When set, 8-bit color data is used in the color palette RAM. When reset, 6-bit color data is used. (0) 6-bit (I) 8-bit CROO Interleave enable (0) no interleave (1) interleave 4· 436 SECTION 4 A logical zero inhibits the internal logic from interleaving the PO-P7 {A-D} inputs. A logical one enables the PO--P7 {A-D} inputs to be interleaved. Bt474 Internal Registers (continued) Command Register_1 This register may be written to or read by the MPU at any time and is not initialized. CRI0 corresponds to data bus bit DO, the least significant data bit. CR17 OL3 enable This bit is logically ANDed with OL3 data immediately after the overlay mode circuitry. (0) force OL3 to logical zero (1) pass OL3 data CR16 OL2 enable This bit is logically ANDed with OL2 data immediately after the overlay mode circuitry. (0) force OL2 to logical zero (1) pass OL2 data CR15 OLl enable This bit is logically ANDed with OLl data immediately after the overlay mode circuitry. (0) force OLl to logical zero (1) pass OLl data CR14 OLO enable This bit is logically ANDed with OLO data immediately after the overlay mode circuitry. (0) force OLO to logical zero (1) pass OLO data CR13 Test path enable (0) normal mode (1) test mode CR12 Clock selection A logical one enables certain test paths to be internally set up. This involves any input mode and any inputs which affect access to the color palette RAMs. This bit selects which pixel clock input to use. (0) CLOCK_O (1) CLOCK_l CRll, CRI0 Overlay operation select (00) (01) (10) (11) mode 0 mode 1 mode 2 mode3 These bits select the mode of operation for the OLO-OL3 {A-D) inputs as shown in Tables 5-9. When selecting modes 0 or I, the CLOCK_O input should be selected to be the pixel clock. RAMDACs 4 • 437 Bt474 Internal Registers (continued) Pixel Read Mask Register The 8-bit pixel read mask register may be written to or read by the MPU at any time, and is not initialized. DO is the least significant bit. The contents of this register are bit-wise ANDed with the PO-P7 pixel data prior to addressing the color palette RAM. ID Register This 8-bit register may be read by the MPU at any time and contains the ID number $11. MPU write cycles to this register are ignored. Status Register The 8-bit status register may be read by the MPU at any time; MPU write cycles to this register are ignored. 00 is the least significant bit. 01-07 are always a logical zero. DO is the SENSE* bit. If it is a logical zero, one or more of the lOR, lOG, and lOB outputs have exceeded the internal voltage reference level (335 mY). This bit is used to determine the presence of a CRT monitor and, via diagnostic code, the difference between a loaded or unloaded RGB line can be discerned. The 335 mV reference has a ±5% minimum tolerance when using an external voltage reference or a ±IO% tolerance when using an external current reference or the internal voltage reference. 4·438 SECTION 4 Bt474 Pin Descriptions Pin Name Description BlANK* Composite blank control input (TIL compatible). A logic zero drives the analog outputs to the blanking level, as illustrated in Tables 10 and 11. It is latched on the rising edge of SCLK. When BLANK* is a logical zero, the pixel and overlay inputs are ignored. CSYNC* Composite sync control input (TIL compatible). A logical zero on this input switches off a 40 IRE current source on the analog outputs (see Figures 10 and 11). CSYNC* does not override any other control or data input, as shown in Tables 10 and 11; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of SCLK. If sync information is not to be generated on the analog outputs, this pin should be connected to GND. VSYNC Vertical sync control input (TIL compatible). VSYNC is sampled on the falling edge of BLANK* in the first field/frame to determine the polarity of VSYNC. If a logical one is latched, VSYNC is assumed to be an active low signal; if a logical zero is latched, VSYNC is assumed to be an active high signal. ODD/EVEN* Odd/even field input (TTL compatible). This input is latched on the rising edge of SCLK. This input is ignored if noninterlaced operation (command bit CR05) is selected. Pixel clock inputs (TTL compatible). It is recommended that each clock input be driven by a dedicated buffer to avoid reflection-induced jitter. SCLK Shift clock output (TTL compatible). SCLK is 1/4 the pixel clock rate, except when the overlays are in the VGA mode (overlay modes 0 and 1). PO-P7 (A-D) Pixel select inputs (TIL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the color palette RAM is to be used to provide color information. They are latched on the rising edge of SCLK. PO is the LSB. Unused inputs should be connected to GND. OLO-OL3 (A-D) Overlay select inputs (TIL compatible). These inputs specify which palette is to be used to provide color information. When accessing the overlay palette, the PO-P7 (A-E) inputs are ignored. They are latched on the rising edge of SCLK. OLO is the LSB. Unused inputs should be connected to GND. COMP Compensation pin. If an external or the internal voltage reference is used (Figures 12 and 13), this pin should be connected to OPA. If an external current reference is used (Figure 14), this pin should be connected to IREF. A 0.1 ~F ceramic capacitor must always be used to bypass this pin to VAA. The COMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to PC Board Layout Considerations for critical layout criteria. VREF Voltage reference input. If an external voltage reference is used (Figure 13), it must supply this input with a 1.2 V (typical) reference. If an external current reference is used (Figure 14), this pin should be left floating, except for the bypass capacitor. A 0.1 ~F ceramic capacitor is used to decouple this input to GND, as shown in Figures 12 and 13. If the VAA supply is very clean, better performance may be obtained by decoupling VREF to VAA. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. When using the internal reference, this pin should not drive any external circuitry, except for the decoupling capacitor (Figure 12). OPA Reference amplifier output. If an external or the internal voltage reference is used (Figures 12 and 13), this pin must be connected to COMPo When using an external current reference (Figure 14), this pin should be left floating. VM Analog power. All VAA pins must be connected. GND Analog ground. All GND pins must be connected. RAMDACs 4 - 439 .. Bt474 Pin Descriptions (continued) Pin Name IREF Description Full-scale adjust control. Note that the IRE relationships in Figures 10 and 11 are maintained, regardless of the full-scale output current. When using an external or the internal voltage reference (Figures 12 and 13), a resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. The relationship between RS ET and the full-scale output current on each output is: RSET (0) =K * 1,000 * VREF (v) I lout (rnA) K is defmed in the table below. It is recommended that a 147 0 RSET resistor be used for doubly terminated 75 0 loads (i.e., RS-343A applications). When using an external current reference (Figure 14), the relationship between IREF and the full-scale output current on each output is: IREF (rnA) =lout (rnA) I K Sync Enabled Sync Disabled Setup oIRE 7.5 IRE oIRE 7.5 IRE K= 3.025 3.195 3.000 3.170 lOR, lOG, lOB Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 0 coaxial cable (Figures 12, 13, and 14). WR* Write control input (TTL compatible). DO-D7 data is latched on the rising edge of WR*, and RSO-RS3 are latched on the falling edge of WR* during MPU write operations. RD* and WR* should not be asserted simultaneously. RD* Read control input (TTL compatible). To read data from the device, RD* must be a logical zero. RSO-RS3 are latched on the falling edge of RD* during MPU read operations. RD* and WR * should not be asserted simultaneously. RSO-RS3 Register select inputs (TTL compatible). RSO-RS3 specify the type of read or write operation being performed, as illustrated in Tables 1 and 2. DO-D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. 4· 440 SECTION 4 Bt474 Pin Descriptions (continued) . ~ . . . ~ .. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ " Ii! 0:: i'! ~ ~ Ii: ~ ;:! ~ III ill Ie ~ 18 :i S Ii! 10 (j! 1Il ~ In :R ~ Q 0:: ;j\ POB 53 P2D f'/A 51 P3D P6A $1 P4D P5A 50 PSD P4A 49 P6D P3A 43 f'7D P2A 47 OLOA PIA 4~ OLOB POA 45 OLOC VSYNC 44 OLOD CSYNC· 43 OLiA BLANK' 42 OLiB SQK 41 OLIC QOCK_I 40 OLIO QOCK_O 39 OUA WR' 38 OL2B RD' 37 OL2C ODD/EVEN' 36 OL2J) RS3 35 OLlA RS2 34 OLlB RSI 33 oue l:l ~ ;!; ~ ~ ~ ~ l:l !::; !!: ~ ~ E IS is 21 8 .... Q S 8 ~ ~ "" ~ ~ ~ ~ ~ ~ ~ ~ I< .. 1$ !!l :;: ;;; l:! s~ u ~ ~ ~ 0~ RAMDACs 4 ·441 Bt474 PC Board Layout Considerations PC Board Considerations Power Planes This product requires special attention to proper layout techniques to achieve optimum performance. Before beginning PCB layout, refer to the CMOS RAMDAC layout example found in Bt451n/8 Evaluation Module Operation and Measurements, application note (AN -16). This application note can be found in Brooktree's 1990 Applications Handbook. Separate digital and analog power planes are necessary. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt474 power pins, any reference circuitry, and COMP and reference decoupling. There should be at least a 1I8-inch gap between the digital power plane and the analog power plane. The layout should be optimized for lowest noise on the Bt474 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figures 12, 13, and 14. This bead should be located within 3 inches of the Bt474 and provides resistance to switching currents, acting as a resistance at high frequencies. A low-resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. A well-designed power distribution network is critical to eliminating digital switching noise. Ground planes must provide a low-impedance return path for the digital circuits. A minimum of a four-layer PC board is recommended with layers 1 (top) and 4 (bottom) for signals and layers 2 and 3 for power and ground. The optimum layout enables the Bt474 to be located as close to the power supply connector and as close to the video oulput connector as possible. Ground Planes For optimum performance. a common digital and analog ground plane with tub isolation (at least a 1I8-inch gap) and connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector to preserve digital noise margins during MPU read cycles. Thus, the ground tub isolation technique is constrained by the noise margin degradation during digital readback of the Bt474. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. For maximum performance, a separate isolated ground plane for the analog output termination resistors. RSET resistor, and reference circuitry (if used) should be used, as shown in Figures 12, 13, and 14. Another isolated ground plane is used for the GND pins of the Bt474 and supply decoupling capacitors. 4 - 442 SECTION 4 Plane-to-plane noise coupling can be reduced by ensuring that portions of the digital power and ground planes do not overlay portions of the analog power and ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. Device Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Power Supply DecoupUng Best power supply decoupling performance is obtained with a 0.1 J.lF ceramic capacitor decoupling each of the two groups of VAA pins to GND. For operation above 75 MHz, a 0.1 J.lF capacitor in parallel with a 0.001 J.lF chip capacitor is recommended. The capacitors should be placed as close as possible to the device. The 10 J.lF capacitor is for low-frequency power supply ripple; the 0.1 J.lF capacitors are for high-frequency power supply noise rejection. Bt474 PC Board Layout Considerations (continued) A linear regulator to filter the analog power supply is recommended if the power supply noise is ~ 200 mV or greater than 10 LSBs. This is especially important when a switching power supply is used and the switching frequency is close to the raster scan frequency. Note that about 10% of the power supply hum and ripple noise less than 1 MHz will couple onto the analog outputs. COMP Decoupllng The COMP pin must be decoupled to VAA, typically using a 0.1 IJ.F ceramic chip capacitor. Low frequency supply noise will require a larger value. Lead lengths should be minimized for best performance. Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge speeds (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals. Ensure that the power pins for the clock driver are properly decoupled to minimize transients. Minimize edge speeds and ringing, using damping resistors (10 to 50 n) or parallel termination where necessary. If using parallel termination on digital signals, the resistors should be connected to the digital power and ground planes, not the analog power and ground planes. If the display has a "ghosting" problem, additional capacitance in parallel with the COMP capacitor may help to fix the problem. Analog Signal Interconnect Digital Signal Interconnect The Bt474 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The digital inputs to the Bt474 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power and ground planes. Most noise on the analog outputs will be caused by excessive edge speeds (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The digital edge speeds should be no faster than necessary, as feedthrough noise is proportional to the digital edge speeds. Lower speed applications will benefit from using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission line mismatch will exist if the line length reflection time is greater than 1/4 the signal edge time, resulting in ringing, overshoot, and undershoot that can generate noise onto the analog outputs. Line termination or reducing the line length is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (10 to 50 n). The video output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog outputs should have a source load resistor equal to the destination termination (via a clean isolated ground return path). The load resistor connection between the current output and GND should be as close as possible to the Bt474 to minimize reflections. Unused analog outputs should be connected to GND. Analog edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent Simple pulse filters can reduce ghosts. high-frequency energy, reducing EMI and noise. Analog Output Protection The Bt474 analog outputs should be protected against high energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figures 12, 13, and 14 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 parts are low-capacitance, fast-switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7001). RAMDACs 4 - 443 .. Bt474 PC Board Layout Considerations (continued) ANALOGPOWBRPLANE Bt474 Ll +SV(VCC) C2-C3 + Cl C6 ~. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .~~ GROUND (poWER SUPPLY CONNECTOR) Rl R2 R3 IRBP lOR TO VIDEO CONNEcrOR lOG lOB VAA 0 IN4148/9 DAC 01lTP\JT TO MONITOR IN4148/9 GND Location CI-C5 C6 L1 RI. R2. R3 RSEf Vendor Part Number Description OJ ~ ceramic capacitor 10 ~F capacitor ferrite bead 75 n I % metal film resistor I % metal film resistor Erie RPEII2Z5UI04M50V Mallory CSRl3G106KM Fair-Rite 2743001111 Dale CMF-55C Dale CMF-55C Note: The vendor numbers above are listed only as a guide_ characteristics will not affect the performance of the Bt474_ Figure 12. 4· 444 SECTION 4 Substitution of devices with similar Typical Connection Diagram and Parts List (Internal Voltage Reference). Bt474 PC Board Layout Considerations (continued) Bt474 LI CZ-C3 + ZI CI C6 ~. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .~. GROUND (poWER SUPPLY CONNECfOR) RI R2 R3 !REF 10R~--------+---4---+-------{ TO VIDEO roo~----------~~-+------~ CONNECTOR 10Br-----------------+-------{ VAA IN4148/9 DAC OUTPUT ---------..--+- lOR SYNC" >--rl-t---<~ lOG BLANK' SETUP OLO-013 >-:r:±:t:-t-~ lOB SENSE'" 475/471· (477/471·) DO-D7 Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 L477001 Rev. E Product Description The Bt475 has a 256 x 18 lookup table RAM, 15 x 18 overlay registers, and triple 6-bit D/A converters. VREP PO-P7 80 MHz 256 Word Color Palette Personal System/2® Power-Down RAMDAC™ The Bt475 and Bt477 RAMDACs are designed specifically for Personal System/2® compatible color graphics. Functional Block Diagram VAA Bt475 Bt477 RD'" WR" RSO RSl RS2 On-chip analog output comparators are included to simplify diagnostics and debugging, with the result output onto the SENSE* pin. Also included is an on-chip voltage reference to simplify using the device. A power-down mode is available to reduce power requirements when the analog outputs are not used. This is useful in laptop computer systems that need the option of driving an external RGB monitor. When the 475/471* input pin (477/471* on the Bt477) is floating or a logical zero, the Bt475 and Bt477 behave exactly as a Bt471 with anti-sparkle capabilities, on-chip reference, and analog comparators. When the pin is a logical one, the additional capabilities of the command register are available. ® Personal System/2 and PS/2 are registered trademarks of IBM. 4 . 455 Bt475/477 Circuit Description MPU Interface Reading Color Palette RAM Data As illustrated in the functional block diagram, the Bt475/477 supports a standard MPU bus interface, allowing the MPU direct access to the color palette RAM and overlay color registers. To read color palette RAM data, the MPU loads the address register (RAM read mode) with the address of the color palette RAM location to be read. The contents of the color palette RAM at the specified address are copied into the RGB registers and the address register is incremented to the next RAM location. The MPU performs three successive read cycles (6 or 8 bits each of red, green, and blue), using RSO-RS2 to select the color palette RAM. Following the blue read cycle, the contents of the color palette RAM at the address specified by the address register are copied into the RGB registers and the address register again increments. A block of color values in consecutive locations may be read by writing the start address and performing continuous R,G,B read cycles until the entire block has been read. The RSO-RS2 select inputs specify whether the MPU is accessing the address register, color palette RAM, overlay registers, or read mask register, as shown in Table 1. The 8-bit address register is used to address the color palette RAM and overlay registers, eliminating the requirement for external address multiplexers. ADDRO corresponds to DO and is the least significant bit. Writing Color Palette RAM Data To write color data, the MPU writes the address register (RAM write mode) with the address of the color palette RAM location to be modified. The MPU performs three successive write cycles (6 or 8 bits each of red, green, and blue), using RSO-RS2 to select the color palette RAM. After the blue write cycle, the three bytes of color information are concatenated into a 18-bit or 24-bit word and written to the location specified by the address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. A block of color values in consecutive locations may be written to by writing the start address and performing continuous R,G,B write cycles until the entire block has been written. Writing Overlay Color Data To write overlay color data, the MPU writes the address register (overlay write mode) with the address of the overlay location to be modified. The MPU performs three successive write cycles (6 or 8 bits each of red, green, and blue), using RSO-RS2 to select the overlay registers. After the blue write cycle, the three bytes of color information are concatenated into a IS-bit or 24-bit word and written to the overlay location specified by the address register. The address register then increments to the next location which the MPU may modify by simply writing another sequence of red, green, and blue data. A block of color values in consecutive locations may be written to by writing the start address and performing continuous R,G,B write cycles until the entire block has been written. RS2 RSI RSO Addressed by MPU 0 0 0 0 0 1 0 1 0 1 1 0 address register (RAM write mode) address register (RAM read mode) color palette RAM pixel read mask register 1 1 1 1 0 1 0 1 0 1 1 0 address register (overlay write mode) address register (overlay read mode) overlay registers command register* *Available only when the 475/471* (477/471*) pin is a logical one. Table I. 4· 456 SECTION 4 Control Input Truth Table. Bt475/477 Circuit Description (continued) Reading Overlay Color Data To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADDRa, ADDRb) that count modulo three, as shown in Table 2. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The MPU does not have access to these bits. The other S bits of the address register, incremented following a blue read or write cycle, (ADDR0-7) are accessible to the MPU, and are used to address color palette RAM locations and overlay registers, as shown in Table 2. The MPU may read the address register at any time without modifying its contents or the existing read/write mode. To read overlay color data, the MPU loads the address register (overlay read mode) with the address of the overlay location to be read. The contents of the overlay register at the specified address are copied into the RGB registers and the address register is incremented to the next overlay location. The MPU performs three successive read cycles (6 or 8 bits each of red, green, and blue), using RSO-RS2 to select the overlay registers. Following the blue read cycle, the contents of the overlay location at the address specified by the address register are copied into the RGB registers and the address register again increments. A block of color values in consecutive locations may be read by writing the start address and performing continuous R,G,B read cycles until the entire block has been read. Note the pixel clock must be active for MPU accesses to the color palette RAM. Bt471 Compatible Operation Additional Information If the 475/471* (477/471*) pin is a logical zero, the Bt475/477 operates as a Bt471 RAMDAC; the command register is disabled and 6-bit operation is selected. Color data is contained on the lower 6 bits of the data bus, with DO being the LSB and D5 the MSB of color data. When writing color data, D6 and D7 are ignored. During color read cycles, D6 and D7 will be a logical zero. Note that in the 6-bit mode, the Bt477's full scale output current will be about 1.5% lower than when in the 8-bit mode. This is due to the 2 LSBs of each S-bit DAC always being a logical zero in the 6-bit mode. When accessing the color palette RAM, the address register resets to $00 following a blue read or write cycle to RAM location $FF. While accessing the overlay color registers, the four most significant bits of the address register (ADDR4-7) are ignored. The MPU interface operates asynchronously to the pixel clock. Data transfers between the color palette RAM/overlay registers and the color registers (R, G, and B in the block diagram) are synchronized by internal logic, and occur in the period between MPU accesses. To reduce noticeable sparkling on the CRT screen during MPU access to the color palette RAMs, internal logic maintains the previous output color data on the analog outputs while the transfer between lookup table RAMs and the RGB registers occurs. Value ADDRa, b (counts modulo 3) ADDR0-7 (counts binary) If the 475/471* (477/471*) input is a logical one, the command register is available. On the Bt477, the 6-bitlS-bit select bit in the command register may be used to specify whether 6-bit or S-bit color data values are being used. RS2 RSI RSO Addressed by MPU red value green value blue value 00 01 10 $00 - $FF xxxx 0000 xxx x 0001 0 1 1 0 0 0 1 1 1 color palette RAM reserved overlay color 1 : : : : : xxx x 1111 1 0 1 overlay color 15 Table 2. Address Register (ADDR) Operation. RAMDACs 4 - 457 Bt47S/477 Circuit Description (continued) 8-bit / 6-bit Color Selection SENSE'" Output For 8-bil operation, DO is the LSB and D7 is the MSB of color data. SENSE* is a logical zero if one or more of the lOR, 100, and lOB outputs have exceeded the internal voltal:e reference level (335 mV). This output is used to determine the presence of a CRT monilor and, via diagnostic code, the difference between a loaded or unloaded ROB line can be discerned. The 335 mV reference has a ± 5% tolerance (when using an external 1.235 V voltage reference). The tolerance is ± 10% when using the internal voltage reference or an external current reference. Note that SYNC* should be a logical zero for SENSE* to be stable. For 6-bil operation, color data is contained on the lower 6 bits of the data bus, with DO being the LSB and D5 the MSB of color data. When writing color data, D6 and D7 are ignored. During color read cycles, D6 and D7 will be a logical zero. Note that in the 6-bit mode, the Bt477's full-scale output current will be about 1.5% lower than when in the 8-bit mode. This is due to the 2 LSBs of each 8-bit DAC always being a logical zero in the 6-bit mode. Power-Down Mode The Bt475/477 incorporates a power-down capability, controlled by the SLEEP command bit. While the SLEEP bit is a logical zero, the B1475/477 functions normally. While the SLEEP bit is a logical one, the DACs and power to the RAM are turned off. Note that the RAM still retains the data. Also, the RAM may still be read or written to while sleeping as long as the pixel clock is running. The RAM automatically powers up during MPU read/write cycles, and shuts down when the MPU access is completed. The DACs will be turned off during sleep mode only if a voltage reference (internal or external) is used. If using an external current reference, external circuitry should tum the current reference off (IREF = 0 rnA) during sleep mode. When using an external voltage reference, external circuitry should tum off the voltage reference (VREF = Ov) to further reduce power consumption due to biasing of portions of the internal voltage reference. Frame Buffer Interface The PO-P7 and OLO-OL3 inputs are used to address the color palette RAM and overlay registers, as shown in Table 3. The contents of the pixel read mask register, which may be accessed by the MPU at any time, are bit-wise logically ANDed with the PO-P7 inputs. Bit DO of the pixel read mask register corresponds to pixel input PO. The addressed location provides 18 bits (Bt475) or 24 bits (Bt477) of color information to the three D/A converters. The SYNC* and BLANK* inputs, also latched on the rising edge of CLOCK to maintain synchronization with the color data, add appropriately weighted currents to the analog outputs. This produces the specific output levels required for video applications, as illustrated in Figures 1-3. Tables 4-6 detail how the SYNC· and BLANK* inputs modify the output levels. The SETUP input pin is logically ANDed with the SETUP command bit and is used to specify whether a o or 7.5 IRE blanking pedestal is to be used. The analog outputs of the Bt475/477 are capable of directly driving a 37.5 Q load, such as a doubly terminated 75 Q coaxial cable. OLO-OL3 PO-P7 Addressed by frame buffer $0 $0 : $0 $1 : $F $00 $01 color palette RAM location $00 color palette RAM location $01 : : $FF $xx $xx $xx color palette RAM location $FF overlay color 1 : overlay color 15 Table 3. Pixel and Overlay Control Truth Table. (Pixel Read Mask Register = $FF) 4 - 458 SECTION 4 Bt475/477 Circuit Description (continued) NO SYNC SYNC MA V MA V 19.05 0.714 26.67 1.000 -.----~._--------------------~__------wmrnWVEL 1.44 0.054 9.05 0.340 -r----------~--------+_----------------BLA~wva 0.00 0.000 7.62 0.286 -r-------------1---r--r--~---------------- 0.00 0.000 7.5 IRE BLANK LEva 40 IRE ~ ______________ ~~ ____________________ SYNCWva Note: 75 n doubly terminated load, SETUP = 7.5 IRE. VREF = 1.235 V, RSET = 147 tolerances are assumed on all levels. Figure 1. RS-343A levels and RS-343A Composite Video Output Waveforms (SETUP = 7.5 IRE). Sync Disabled Sync Enabled Iout(mA) Iout(mA) 19.05 data + 1.44 data + 1.44 1.44 1.44 0 0 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 Description WHIlE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC n. SYNC* BLANK* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: 75 n doubly terminated load, SETUP = 7.5 IRE. VREF = 1.235 V, RSET = 147 n. Table 4. RS·343A Video Output Truth Table (SETUP 7.5 IRE). RAMDACs 4 • 459 Bt47S/477 Circuit Description (continued) NO SYNC MA SYNC MA V V 17.62 0.660 25.24 0.950 -r-----,~--------------------~~------WHITELEVa 0.00 0.000 7.62 0.286 +------------'-...,--,.-..1----------------- 0.00 0.000 0.00 0.000 OLACK/BLANK LEva 43 IRE -l-______________-L.......L____________________ SYNC LEva Note: 75 Q doubly terminated load, SETUP = 0 IRE. VREF = 1.235V, RSET = 147 Q. RS-343A levels and tolerances are assumed on all levels. Figure 2. RS-343A Composite Video Output Waveforms (SETUP = 0 IRE). Sync Disabled Sync Enabled lout (mA) lout (rnA) 17.62 data data 0 0 0 0 25.24 data + 7.62 data 7.62 0 7.62 0 Description WHITE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC SYNC* BLANK* DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: 75 Q doubly terminated load, SETUP = 0 IRE. VREF = 1.235 V, RSET = 147 Q. Table 5. 4 - 460 RS-343A Video Output Truth Table (SETUP = 0 IRE). SECTION 4 Bt47S/477 Circuit Description (continued) NO SYNC MA SYNC V MA V 14.25 0.713 20.36 1.018 -.-----,.---------------------~~------wmmrn~ 0.00 0.000 6.11 0.30:5 -r----------~--,_~--~---------------- BLA~~LE~ 43 IRE 0.00 0.000 0.00 0.000 ~--------------~-L--------------------SYNC~ Note: 50 n load, SETUP = 0 IRE. VREF = 1.235 V, RSET levels. Figure 3. PS{l.levels and tolerances are assumed on all PS/2 Composite Video Output Waveforms (SETUP = 0 IRE). Sync Disabled Sync Enabled lout (rnA) lout (mA) 14.25 data 20.36 data + 6.11 data 6.11 0 6.11 0 Description WHITE DATA DATA-SYNC BLACK. BLACK-SYNC BlANK SYNC = 182 n. data 0 0 0 0 SYNC· BlANK· DAC Input Data 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx Note: 50 n load, SETUP =0 IRE. VREF = 1.235 V, RSET = 182 n. Table 6. PS/2 Video Output Truth Table (SETUP =0 IRE). RAMDACs 4 ·461 .. Bt47S/477 Internal Registers Command Register This register is operational only while the 475/471 * (477/471*) pin is a logical one. It may be written to or read by the MPU at any time and is not initialized. D7 reserved (logical zero) A logical zero must be written to this bit when writing to the command register to ensure proper operation. D6 reserved (logical one) A logical one must be written to this bit when writing to the command register to ensure proper operation. D5 SETUP select This bit specifies the blanking pedestal to be either 0 or 7.5 IRE. This bit is logically ANDed with the 475/471 * (477/471 *) input pin. Bit D5 controls the blanking pedestal only when in 475 (477) mode. The SETUP pin is disabled when operating inside this register. (0) OIRE (1) 7.5 IRE D4 Blue sync enable This bit specifies whether the lOB output is to contain sync information or not. (0) no sync on blue (1) sync on blue D3 Green sync enable This bit specifies whether the lOG output is to contain sync information or not. (0) no sync on green (1) sync on green D2 Red sync enable (0) no sync on red (1) sync on red 4·462 SECTION 4 This bit specifies whether the lOR output is to contain sync information or not. Bt475/477 Internal Registers (continued) Command Register (continued) 01 6-bit / 8-bit select (0) 6-bit 8-bit (1) DO SLEEP enable (0) normal operation (1 ) sleep mode On the Bt477, this bit specifies whether the MPU is reading and writing 8 bits (logical one) or 6 bits (logical zero) of color information each cycle. On the Bt475, this bit must be a logical zero to ensure proper 6-bit operation. While this bit is a logical zero, the Bt475/477 functions normally. If this bit is a logical one, the OACs and power to the RAM are turned off. Note that the RAM still retains the data. Also, the RAM may be read or written to as long as the pixel clock is running. The RAM automatically powers-up during MPU read/write cycles, and shuts down when the MPU access is completed. It requires about 1 second for the Bt475/477 to output valid video data after enabling normal operation (coming out of sleep mode). This time will vary depending on the size of the CaMP capacitor. The OACs will be turned off during sleep mode only if a voltage reference (internal or external) is used. If using an external current reference, external circuitry should turn the current reference off during sleep mode. RAMDACs 4·463 .. Bt47S/477 Pin Descriptions Pin Name Description BLANK* Composite blank control input (lTL compatible). A logic zero drives the analog outputs to the blanking level. as illustrated in Tables 4. 5. and 6. It is latched on the rising edge of CLOCK. When BLANK* is a logical zero. the pixel and overlay inputs are ignored. SEIUP Setup control input (lTL compatible). Used to specify either a 0 IRE (logical zero) or 7.5 IRE (logical one) blanking pedestal. This pin should not be left floating. SYNC* Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source on the analog outputs (see Figures 1. 2. and 3). SYNC* does not override any other control or data input. as shown in Tables 4. 5. and 6; therefore. it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. If sync information is not required on the video outputs. SYNC* should be connected to GND. CLOCK Clock input (TTL compatible). The rising edge of CLOCK latches the PO-P7. OLO-OL3. SYNC*. and BLANK* inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedicated TTL buffer to avoid reflection-induced jitter. PO - P7 Pixel select inputs (lTL compatible). These inputs specify. on a pixel basis. which one of the 256 entries in the color palette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK. PO is the LSB. Unused inputs should be connected to GND. OLO-OL3 Overlay select inputs (lTL compatible). These inputs specify which palette is to be used to provide color information. as illustrated in Table 3. When accessing the overlay palette. the PO-P7 inputs are ignored. They are latched on the rising edge of CLOCK. OLO is the LSB. Unused inputs should be connected to GND. COMP Compensation pin. If an external or the internal voltage reference is used (Figures 4 and 5). this pin should be connected to OPA. If an external current reference is used (Figure 6). this pin should be connected to IREF. A 0.1 IlF ceramic capacitor must always be used to bypass this pin to V AA. The COMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to PC Board Layout Considerations for critical layout criteria. VREF Voltage reference input. If an external voltage reference is used (Figure 5). it must supply this input with a 1.2 V (typical) reference. If an external current reference is used (Figure 6). this pin should be left floating. except for the bypass capacitor. A 0.1 IlF ceramic capacitor is used to decouple this input to GND. as shown in Figures 4 and 5. If the VAA supply is very clean, better performance may be obtained by decoupling VREF to V AA. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. When using the internal reference. this pin should not drive any external circuitry. except for the decoupling capacitor (Figure 4). OPA Reference amplifier output. If an external or the internal voltage reference is used (Figures 4 and 5). this pin must be connected to CaMP. When using an external current reference (Figure 6). this pin should be left floating. lOR. lOG. lOB Red. green. and blue current outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 n coaxial cable (Figures 4. 5. and 6). VAA Analog power. All VAA pins must be connected. GND Analog ground. All GND pins must be connected. 4·464 SECTION 4 Bt475/477 Pin Descriptions (continued) Pin Name IREF Description Full scale adjust control. Note that the IRE relationships in Figures I, 2, and 3 are maintained, regardless of the full scale output current. When using an external or the internal voltage reference (Figures 4 and 5), a resistor (RSET) connected between this pin and GND controls the magnitude of the full scale video signal. The relationship between RSET and the full scale output current on each output is: RSEf (0) = K * 1,000 * VREF (V) lIout (rnA) K is defined in the table below. It is recommended that a 147 0 RSET resistor be used for doubly terminated 75 0 loads (i.e., RS-343A applications). For PS/2 applications (i.e., 0.7 V into 50 0 with no sync), a 1820 RSET resistor is recommended. When using an external current reference (Figure 6), the relationship between IREF and the full scale output current on each output is: .. IREF (rnA) = lout (rnA) 1K Part Mode Pedestal K (with sync) K (no sync) Bt477 6-bit 8-bit 6-bit 8-bit 7.5 IRE 7.5 IRE oIRE oIRE 3.170 3.195 3.000 3.025 2.26 2.28 2.10 2.12 Bt475 (6-bit) 7.5 IRE oIRE 3.170 3.000 2.26 2.10 WR* Write control input (TIL compatible). DO-D7 data is latched on the rising edge of WR*, and RSO-RS2 are latched on the falling edge of WR* during MPU write operations. RD* and WR* should not be asserted simultaneously. RD* Read control input (TIL compatible). To read data from the device, RD* must be a logical zero. RSO-RS2 are latched on the falling edge of RD* during MPU read operations. RD* and WR* should not be asserted simultaneously. RSO, RS1, RS2 Register select inputs (TIL compatible). RSO-RS2 specify the type of read or write operation being performed, as illustrated in Tables 1 and 2. DO-D7 Data bus (TIL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. 475/47P (477/471*) Bt475 (Bt477) or B471 select input (TTL compatible). v,'hen the 475/471 * (477/471*) input pin is floating or a logical zero, the Bt475/477 behaves exactly as a Bt471 with anti-sparkle capabilities. When the 475/471* (477/471*) input pin is a logical one, the extra capabilities of the Bt475/477 command register are available. SENSE* Sense output (CMOS compatible). SENSE* is a logical zero if one or more of the lOR, lOG, and lOB outputs have exceeded the internal voltage reference level (335 mY). Note that SENSE* may not be stable while SYNC* is toggling. RAMDACs 4 • 465 Bt475/477 Pin Descriptions (continued) ~ Ii: II: I!: 1£ !C s: Ii! Ii: ~ lit IR G; :Ii III ~ III R ;;; 5t III ~ I< Pulse Width Low RD*. WR * Pulse Width High 9 10 50 6*p13 50 6*p13 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 11 12 3 3 3 3 ns ns Clock Cycle Time (p13) Clock Pulse Width High Time Clock Pulse Width Low Time 13 14 15 12.5 4 4 15.15 5 5 ns ns ns Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time* Clock and Data Feedthrough* Glitch Impulse* DAC-to-DAC Crosstalk Analog Output Skew 16 17 18 SENSE* Output Delay 19 5 40 20 40 20 30 30 3 13 -30 75 -23 3 13 -30 75 -23 4 dB dB 1 1 ns ns ns pV - sec 2 2 Pipeline Delay ns J.!.S 4 4 Clocks 220 180 220 rnA 10 5 10 rnA 4 4 180 5 4 IAA VAA Supply Current** normal operation sleep enabled*** See test conditions on page 4 - 478. See also Figure 8. 4· 476 10 10 SECTION 4 Bt475/477 AC Characteristics (continued) 50 MHz Devices Parameter Clock Rate Symbol Min Typ Fmax 35 MHz Devices Max Min Typ 50 Max Units 35 MHz RSO-RS2 Setup Time RSO-RS2 Hold Time 1 2 10 10 RD* Asserted to Data Bus Driven RD* Asserted to Data Valid RD* Negated to Data Bus 3-Stated Read Data Hold Time 3 4 5 6 5 5 5 ns ns ns ns Write Data Setup Time Write Data Hold Time 7 8 10 10 10 10 ns ns RD*. WR* Pulse Width Low RD*. WR * Pulse Width High 9 10 50 6*p13 50 6*p13 ns ns Pixel and Control Setup Time Pixel and Control Hold Time 11 12 3 3 3 3 ns ns Clock Cycle Time (p13) Clock Pulse Width High Time Clock Pulse Width Low Time 13 14 15 20 6 6 28 7 9 ns ns ns Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time* Clock and Data Feedthrough* Glitch Impulse* DAC-to-DAC Crosstalk Analog Output Skew 16 17 18 SENSE* Output Delay 19 sleep enabled*** ns ns 5 40 20 40 20 30 30 3 28 -30 75 -23 3 20 -30 75 -23 2 Pipeline Delay VAA Supply Current** normal operation 10 10 2 1 4 ns ns ns dB pV - sec dB ns ~ 1 4 4 Clocks 220 180 220 rnA 10 5 10 rnA 4 4 180 5 4 1M See test conditions on next page. See also Figure 8. RAMDACs 4·477 Bt47S/477 AC Characteristics (continued) Test conditions (unless otherwise specified): "Recommended Operating Conditions" using external voltage reference with RSET = 147 Q, VREF = 1.235 V, SETUP = 7.5 IRE, 475/471* (477/471*) pin = logical one. TIL input values are 0 to 3 V, with input rise/fall times ~ 4 ns, measured between the 10% and 90% points. Timing reference points are at 50% for inputs and outputs. Analog output load ~ 10 pF. SENSE*, DO-D7 output load ~ 75 pF. See timing notes in Figure 7. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the digital inputs have a lk Q resistor to ground and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 2x clock rate. **At Fmax. IAA (typ) at VAA= 5.0 V. IAA (max) at VAA(max). ***External current or voltage reference disabled during sleep mode. Test Conditions: +25 0 to +700 C, pixel and data ports at 0.4 V. 13 CLOCK PO·P7.0LO·OL3. SYNC"'. BLANK'" lOR. lOG. lOB ~ 33SMV- lOR. lOG. lOB --, ,-- 17 t- SENSE'" Note I: Output delay measured from the 50% point of the rising edge of CLOCK full scale transition. Note 2: Settling time measured from the 50% point of full scale transition to the output remaining within ±1 LSB (Bt477) or ±1/4 LSB (Bt475). Note 3: Output rise/fall time measured between the 10% and 90% points of full scale transition. Figure 7. 4· 478 SECTION 4 Video Input/Output Timing. to the 50% point of Bt47S/477 Timing Waveforms I 1 I 2 .1 RSO, RSI, RS2 VALID RD·, WR'" 4 * 9 10 - 3 DO - D7 (READ) DO - 07 (W1Uffi) L,- " OAT A OIIT (RD' = 0) 1 - J-5 ./ I--- 6 OATAIN(WR'=O) 7 -8 .. Figure 8. MPU Read/Write Timing. RAMDACs 4 - 479 Bt47S/477 Ordering Information Ambient Temperature Range Model Number Color Palette RAM Overlay Palette Speed Package Bt475KPJ80 256 x 18 15 x 18 80 MHz 44-pin Plastic J-Lead 00 to +70 0 C Bt475KPJ66 256 x 18 15 x 18 66 MHz 44-pin Plastic J-Lead 00 to +700 C Bt475KPJ50 256 x 18 15 x 18 50 MHz 44-pin Plastic J-Lead 0 0 to +700 C Bt475KPJ35 256 x 18 15 x 18 35 MHz 44-pin Plastic J-Lead 0 0 to +700 C Bt477KPJ80 256 x 24 15 x 24 80 MHz 44-pin Plastic J-Lead 0 0 to +700 C Bt477KPJ66 256 x 24 15 x 24 66 MHz 44-pin Plastic J-Lead 0 0 to +700 C Bt477KPJ50 256 x 24 15 x 24 50 MHz 44-pin Plastic J-Lead 0 0 to +70 0 C Bt477KPJ35 256 x 24 15 x 24 35 MHz 44-pin Plastic J-Lead 0 0 to +70 0 C Revision History Datasheet Revision 4·480 Change from Previous Revision B Bt475 added to specification. C Bit D5 controls the Blanking Pedestal only when the Command Register is operational. Maximum, minimum, and typical Internal VREF output voltages are added. D VAA supply currents with sleep enabled are corrected to 5 rnA typical. Temperatures under which tests are conducted are +25 0 to +70 0 C while pixel and data ports are at 0.4 V. RD*/WR* pulse width high times are changed to 6* Clock Cycle Time for all accesses. The command register bit D6 is reserved and must be a logical one to ensure proper operation. E In PCB layout section, figures 4 and 5 now have VREF decoupled to GND. Characteristics. SECTION 4 Revised DC Preliminary Information This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. Distinguishing Features • • • • • • • • • • • • Bt471/476/478 Pin Compatible 80, 66, 50, 35 MHz Operation Triple 8-bit D/A Converters 1024 x 24 Color Palette RAM 16-Window Priority Encoder 15 Overlay Registers Sync Enable/Disable for Each Channel Programmable Pedestal On-Chip Analog Output Comparators Anti-Sparkle Circuitry Automatic Sync Polarity Detection 44-pin PLCC Package Applications • • • • • High-Resolution Color Graphics CAE/CAD/CAM Image Processing Instrumentation Desktop Publishing 80 MHz 1024 X 24 Color Palette Personal System/2® WindowVu™ RAMDAC™ Product Description The Bt479 RAMDAC is designed specifically for Personal System/2® compatible color graphics. It supports up to 1,024 simultaneous colors out of a 16.8 million color palette through the lK x 24 color palette RAM and triple 8-bit D/A converters. Functional Block Diagram VAA Bt479 The Bt479 may also be configured to display up to 16 windows (plus background), with flexible color palette control. An on-chip 16 window priority encoder provides window display priority, color palette selection, and window placement (with pixel resolution). GND The 479/471* pin enables the Bt479 to emulate the Bt471 RAMDAC, and it is fully software-compatible and pin-compatible with the Bt471. CLOCK po.P7 SYNC >--..-+--4-100 BLANK· SBTUP 0L0·0L3 >-....-I+.......j-1OB SI!NSIl· DO·D7 Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121-2790 (619) 452-7580 • (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 L479001 Rev. E ~ Additional features include up to 15 overlay registers to provide for overlaying cursors, grids, menus, EGA emulation, etc. Also supported is sync generation on all three channels (with each channel independently enabled or disabled), and a programmable pedestal (0 or 7.5 IRE). Wlt.. RSO RS! RSa ®Personal System/2 and PS/2 are registered trademarks of mM. 4 - 481 Brodrtree® Bt479 Circuit Description MPU Interface As illustrated in the functional block diagram, the Bt479 supports a standard MPU bus interface, allowing the MPU direct access to the color palette RAM and overlay color registers. The RSO-RS2 select inputs specify whether the MPU is accessing the address register, color palette RAM, overlay registers, or read mask register, as shown in Tables I and 2. The 8-bit address register is used to address the color palette RAM, overlay registers, and control registers, eliminating the requirement for external address multiplexers. ADDRO corresponds to DO and is the least significant bit. contents of the color palette RAM at the specified address are copied into the RGB registers and the address register (ADDRO-ADDR7) is incremented to the next RAM location. The MPU performs three successive read cycles (8 bits each of red, green, and blue), using RSO-RS2 to select the color palette RAM. Following the blue read cycle, the contents of the color palette RAM at the address specified by the address register and command registecO are copied into the RGB registers and the address register again increments. A block of color values in consecutive locations may be read by writing the start address and performing continuous R, G, B read cycles until the entire block has been read. Writing Overlay Color Data Four additional bits in the command register are used to specify which one of four segments of the color palette RAM is being accessed by the MPU as shown in Table 2. Note that when accessing a block of more than 256 colors, the command register must be updated to select the appropriate one of four 256-color segments. Writing Color Palette RAM Data To write color data, the MPU loads the address register (RAM write mode) and optionally command register_O (see Table 2) with the address of the color palette RAM location to be modified. The MPU performs three successive write cycles (6 or 8 bits each of red, green, and blue), using RSO-RS2 to select the color palette RAM. After the blue write cycle, the three bytes of color information are concatenated into a 24-bit word and written to the location specified by the address register and command register_O. The address register (ADDRO-ADDR7) then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. A block of color values in consecutive locations may be written to by writing the start address and performing continuous R, G, B write cycles until the entire block has been written. Reading Color Palette RAM Data To read color palette RAM data, the MPU loads the address register (RAM read mode) and optionally command register_O (see Table 2) with the address of the color palette RAM location to be read. The 4 - 482 SECTION 4 To write overlay color data, the MPU loads the address register (overlay write mode) with the address of the overlay location to be modified. The MPU performs three successive write cycles (6 or 8 bits each of red, green, and blue), using RSO-RS2 to select the overlay registers. After the blue write cycle, the three bytes of color information are concatenated into a 24-bit word and written to the overlay location specified by the address register. The address register (ADDRO-ADDR7) then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. A block of color values in consecutive locations may be written to by writing the start address and performing continuous R, G, B write cycles until the entire block has been written. Reading Overlay Color Data To read overlay color data, the MPU loads the address register (over lay read mode) with the address of the overlay location to be read. The contents of the overlay register at the specified address are copied into the RGB registers and the address register (ADDRO-ADDR7) is incremented to the next overlay location. The MPU performs three successive read cycles (8 bits each of red, green, and blue), using RSO-RS2 to select the overlay registers. Following the blue read cycle, the contents of the overlay location at the address specified by the address register are copied into the RGB registers and the address register again increments. A block of color values in consecutive locations may be read by writing the start address and performing continuous R, G, B read cycles until the entire block has been read. Bt479 Circuit Description (continued) Writing Control Register Data To write control register data, the MPU loads the address register (RAM write mode) with the address of the control register to be modified. The MPU performs a write cycle, using RSO-RS2 to select the control registers. After the write cycle, the address register (ADDRO-ADDR7) then increments to the next location, which the MPU may modify by simply writing another byte of data. A block of data in consecutive control registers may be written to by writing the start address and performing continuous write cycles until the entire block has been written. Reading Control Register Data To read control register data (except the pixel or overlay read mask register), the MPU loads the address register with the address of the control register to be read. The MPU performs a read cycle, using RSO-RS2 to select the control registers. After the read cycle, the address register (ADDRO-ADDR7) then increments to the next location, which the MPU may read by simply reading another byte of data. A block of data in consecutive control registers may be read by writing the start address and performing continuous read cycles until the entire block has been read. Additional In/ormation When accessing the color palette RAM, the address register resets to $00 following a blue read or write cycle to RAM location $FF. While accessing the overlay color registers, the four most significant bits of the address register (ADDR4-7) are ignored. When accessing the control registers, the address register resets to $00 following a read or write cycle to address $FF. Data written to reserved locations are ignored; data read from reserved locations returns invalid data. data on the analog outputs while the transfer between lookup table RAMs and the RGB registers occurs. Accessing of the control registers causes no disturbance on the display screen. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADDRa, ADDRb) that count modulo three, as shown in Table 2. The MPU does not have access to these bits. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The other 8 bits of the address register (ADDR0-7), incremented following a blue read or write cycle, are accessible to the MPU and are used to address color palette RAM locations and overlay registers, as shown in Table 2. The MPU may read the address register at any time without modifying its contents or the existing read/write mode. Bt47I Compatible Operation If the 479/471* pin is a logical zero, the Bt479 operates as a Bt471 RAMDAC; the command register is disabled and 6-bit operation is selected. Color data is contained on the lower 6 bits of the data bus, with DO being the LSB and D5 the MSB of color data. When writing color data, D6 and D7 are ignored. During color read cycles, D6 and D7 will be a logical zero. Note that in the 6-bit mode, the Bt479's full-scale output current will be about 1.5% lower than when in the 8-bit mode. This is due to the 2 LSBs of each 8·bit DAC always being a logical zero in the 6-bit mode. (See Table 3.) If the 479/471* input is a logical zero, the additional control registers are available, however, the contents of the control register will not effect the operation of the device. The MPU interface operates asynchronously to the pixel clock. Data transfers between the color palette RAM/overlay registers and the color registers (R, G, and B in the block diagram) are synchronized by internal logic, and occur in the period between MPU accesses. To reduce noticeable sparkling on the CRT screen during MPU access to the color palette RAMs, internal logic maintains the previous output color RAMDACs 4·483 Bt479 Circuit Description (continued) B-bit / 6-bit Color Selection Window Priority Encoder For 8-bit operation, DO is the LSB and 07 is the MSB of color data. Each window is controlled by four window control registers. The location of each window is specified by its top/left and bottom/right (x,y) coordinates, as shown in Figure 1 and Table 6. To arbitrate overlapping windows, the priority of the window is the window number, with window_O having the highest priority, and window_15 the lowest priority. For 6-bit operation, color data is contained on the lower 6 bits of the data bus, with DO being the LSB and 05 the MSB of color data. When writing color data, 06 and 07 are ignored. Doring color read cycles, 06 and 07 are a logical zero. Note that in the 6-bit mode, the Bt479's full-scale output current will be about 1.5% lower than when in the 8-bit mode. This is due to the 2 LSBs of each 8-bit OAC always being a logical zero in the 6-bit mode. The 6-bit / 8-bit mode selection (available only while the 479/471* pin is a logical one) enables mixing 6-bit and 8-bit color data in the color palette RAM. SENSE· Output SENSE'" is a logical zero if one or more of the lOR, lOG, and lOB outputs have exceeded 335 mY. This output is used to determine the presence of a CRT monitor and via diagnostic code, the difference between a loaded or unloaded ROB line can be discerned. The 335 m V reference has a ±S% tolerance (when using an external 1.235 V voltage reference). The tolerance is ±10% when using an external current reference. Note that SYNC· should be a logical zero for SENSE· to be stable. Pixel Read Mask Register The contents of the pixel read mask register, which may be accessed by the MPU at any time, are bit-wise logically ANDed with the PO-P7 inputs. Bit 00 of the pixel read mask register corresponds to pixel input PO. The contents of the overlay read mask bits in the command register are bit-wise logically ANDed with the OL~L3 inputs. The addressed RAM/overlay location provides 24 bits of color information to the three O/A converters. The pixel read mask register is written to by setting RS2-RSO to 010, as in Table 1. Note that the PO-P7 pixel read mask bits are accessed directly, not through the address register. 4 - 484 SECTION 4 The Bt479 monitors the BLANK'" input to determine the current display position (with pixel resolution). The window positions and sizes are compared to the current display position to determine which windows are being displayed. The window being displayed with the highest priority, in conjunction with PO-P7, addresses the color palette RAM. If no window is being displayed for the current pixel, color palette addresses $OOO-$OFF (palette 0) are used, addressed by PO-P7. Command bits CRIO, CR16, and CR17 control the window and color palette RAM functions, as shown in Tables 4 and 5. Br-.---+-- COMP ' - - - ' - - lOUT The MPU interface signals (00-D7, CS*, RDA*, RDB*, and WR*) are TTL compatible. During MPU accesses to the RAM, the address is input through the pixel ports (PAO-PA7, PBO-PB7). .;'~-I-o~ lOUT' SB'IUP VBB DMIN_ Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580 • (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 L492oo1 Rev. E DO-M 4 . SIS An on-chip voltage reference is available or an external reference may be used. A single external resistor controls the full-scale output current. The Bt492 generates an RS-343A compatible video signal, and is capable of driving either doubly terminated 75 n or 50 n coax directly, without requiring external buffering. Both the differential and integral linearity errors of the D/A converters are guaranteed to be a maximum of ±1/2 LSB over the full temperature range. Bt492 Circuit Description MPU Inter/ace As illustrated in the functional block diagram, the Bt492 has two 256 x 8 RAMs, a 2:1 multiplexer, a single 8-bit DAC, and MPU interface. MPU data is input and output via the DO-D7 data lines. During MPU accesses to the color palette RAMs, the RAMs are addressed via the PAx, PBx, and OLx inputs and the internal pipeline registers are transparenL During MPU write cycles (WR* = 0), data is written to both RAMs. The MPU may read either RAM via the RDA* and RDB* control inputs. (See Figure 1.) BLANK should be asserted during MPU accesses to prevent the data values associated with the MPU address from appearing at the analog outputs. Following an MPU cycle, BLANK should be asserted for at least one valid pixel cycle before the PAx and PBx inputs can be properly routed to the analog outputs. Frame Buffer Inter/ace Pixel data on the PAO-PA7 and OLA inputs (even data) and PBO-PB7 and OLB inputs (odd data) are latched on the fa11ing edge of DIV20UT*, as illustrated in Figure 2. The OLx inputs determine whether the PxO-Px7 inputs address the 256 x 8 color palette RAM (OLx = 0) or the 16 x 8 overlay palette RAM (OLx = 1). When addressing the overlay RAM, Px4-Px7 are ignored. The outputs of the RAMs are then multiplexed at the pixel clock rate and drive the 8-bit video D/A converter. DIV2IN is defined to be 1/2 the CLOCK rate. To simplify system design, the Bt492 outputs a DIV20UT* signal which, when connected to the DIV2IN pin, generates a clock equal to 1/2 the CLOCK rate. For a color system requiring three Bt492s, the DIV20UT signals may be synchronized by connecting the DIV20UT* signal on one of the devices to the DIV2IN pins of all three devices. Care should be taken to keep signal paths short and equal for each connection. The unused DIV20UT signals from the remaining Bt492s can be used to clock the shift registers driving the Bt492 pixel inputs. 4·516 SECTION 4 The BLANK input is also latched on the falling edge of DIV20UT* and overrides the PAO-PA7, OLA, PBO-PB7, and OLB inputs. Blanking information is output synchronously with the even pixel data. Full-scale output current is set by an external resistor (RSET) between the FS ADJUST pin and ECL VCC. RSET has a typical value of 1092 n for generation of RS-343A video into a 37.5 n load, or 729 n for generation of RS-343A video into a 25 n load. The on-chip voltage reference (VREF OUT) may be used to provide the reference for the VREF IN pins of up to three Bt492s, or an external reference may be used. Both sides of the differential current outputs should have the same output load. A single-ended video signal may be generated by connecting the lOUT output through a 25 n resistor to ECL VCC(assuming a doubly terminated 50 n load). The IOUT* output is used to generate the positive video signal. The D/A converter on the Bt492 uses a segmented architecture in which bit currents are routed to either lOUT or IOUT* by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabilizes the full-scale output current against temperature and power supply variations. The analog outputs of the Bt492 are capable of directly driving either a 37.5 n or 25 n load, such as a doubly terminated 75 n or 50 n coaxial cable. BllXKtree~ Bt492 Circuit Description (continued) CS",PAD-PA7, PRO - PB7, OLA, OLB RDA", ROB-, WR- READ (DO - D7) WIUlI! (DO - D7) ==X~ ________ V_MID __________~X~ _________ \'-_____--J/ ---------« DATAOUT(RDA" OR RDB" =0) _________-'X Figure 1. - )>-------- XI..._______ DATA IN(WR" =0) MPU Read/Write Timing. PAD- PA7, PDO- PB7, OLA, OLB, BLANK CLOCK .{'v'---l. ~:!'!IJ, ('v'- lOUT" - - - - - - - - - - - - - - - - - - - ' , Pfu,W' Figure 2. \fr-1 Video Input/Output Timing. RAMDACs 4 - 517 Bt492 Circuit Description (continued) MA MA RSBT= RSBT= 1(192 00.00 00.00 .26.40 ·17.60 ·O.6CiO .28..56 ·19.o5 ·0.714 729 V WHml LBVBL 0.000 BLACK LBVBL 7.5IRB BLANK LI!VEL Note: RSET = 729 n (50 n doubly terminated load) or 1092 n (75 n doubly terminated load), VREF IN = -1.2 V. RS-343A levels and tolerances assumed on all levels. Figure 3. Composite Video Output Waveforms (lOUT·). Description WHITE DATA BLACK BlANK SETUP = ECL vee SETUP = float RSET= 729n RSET= 1092 n IOUT* IOUI'* (rnA) (rnA) 0 data -26.40 0 data -17.62 -26.40 -28.56 -17.62 -19.05 BLANK DAC Input Data 0 0 0 1 $FF data $00 $xx Note: Typical with VREF IN = -1.2 V. Table 1. 4·518 SECTION 4 Video Output Truth Table. Bt492 Pin Descriptions Pin Name Description BLANK Composite blank control input (ECL compatible). A logic one drives the analog output to the blanking level, as illustrated in Table 1. It is latched on the falling edge of DIV20UT*. When BLANK is a logical one, the PAO--PA7, PBO--PB7, OLA, and OLB inputs are ignored. Blanking information is output synchronously with the even pixel data. PAO-PA7, PBO--PB7 Even and odd pixel data inputs (ECL compatible). DO is the least significant data bit. They are latched on the falling edge of DIV20UT* while CS* is a logical one. PAx represent the even pixel data, and PBx represent the odd pixel data. Even data represents the first (leftmost) pixel on the display screen. Coding is binary. PAO and PBO are the LSBs. OLA,OLB Even and odd overlay data inputs (ECL compatible). When OLA or OLB are a logical one, the 4 MSBs of the corresponding pixel inputs (Px4-Px7) are ignored and the 4 LSBs are used to select one of 16 available data words in the overlay palette. They are latched on the falling edge of DIV20UT* while CS* is a logical one. If left floating, they will pull themselves to DVEE. CLOCK, CLOCK* Differential clock inputs (ECL compatible). They are typically the pixel clock rate of the video system. DIV2IN, DIV2IN* Differential CLOCK/2 inputs (EeL compatible). These clocks must be 1/2 the CLOCK rate. They may be configured for single-ended operation by connecting DIV2IN* to VBB. DIV20UT*, DIV20UT CLOCK/2 differential outputs (ECL compatible). When DIV20UT* is connected to the DIV2IN pin, these outputs are 1/2 the CLOCK rate. When not connected to DIV2IN, they generate a signal that is DIV2IN synchronized to CLOCK and inverted. lOUT, IOUT* Differential video current outputs. These high-impedance current sources are capable of directly driving either a doubly terminated 50 Q or 75 Q coaxial cable (Figures 4 and 5). Both outputs, whether used or not, should have the same output load for best settling time. COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.01 IlF ceramic chip capacitor and a 0.001 IlF ceramic chip capacitor must be connected between this pin and AVEE (Figures 4 and 5). The COMP capacitors must be as close to the device as possible to keep lead inductance to an absolute minimum. Refer to PC Board Layout Considerations for critical layout criteria. SETUP Pedestal control input. If connected to ECL VCC, the blanking pedestal on the output is disabled, making the black and blanking levels the same (0 IRE). If left floating, the 7.5 IRE blanking pedestal is enabled. See Figure 3. FSADmST Full-scale adjust control. A resistor (RSET) connected between this pin and ECL VCC controls the magnitude of the full-scale video signal (Figures 4 and 5). Note that the IRE relationships in Figure 3 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current is: RSET (Q) = K * VREF IN (V) I lOUT (rnA) where K = 17,205 if SETUP = float or 15,915 if SETUP = ECL VCC. Note: The RSET value may need to be adjusted to generate the specified video levels due to variations in processing and depending on whether the internal or an external reference is used. RAMDACs 4·519 Bt492 Pin Descriptions (continued) Pin Name Description VREFour Voltage reference output. This output provides a -1.2 V (typical) reference, and may be connected to the VREF IN inputs of up to three Bt492s. When driving multiple Bt492s, use 100 n interconnect resistance to minimize noise pick-Up. If it is not used to provide a voltage reference, it should remain floating. VREFIN Voltage reference input. An external voltage reference, such as the one shown in Figure 6, or the VREF OUT pin must supply this input with a -1.2 V (typical) reference. A 0.01 ~F ceramic chip capacitor in parallel with a 0.001 ~F ceramic chip capacitor must be connected between this pin and ECL VCC, as shown in Figures 4 and 5. The decoupling capacitors must be as close to the device as possible to keep lead inductance to an absolute minimum. CS* Chip select control input (1TL compatible). This input must be a logical zero to enable MPU data to be written to or read from the device. When it is a logical one, DO-D7 are three-stated. While CS* is a logical zero, the PAO--PA7, PBO--PB7, OLA, and OLB inputs are used to address the color palette RAM and overlay RAM, and the internal pipeline registers are configured to, be transparent. RDA*,RDB* Read control input (1TL compatible). To read data from RAM A, both CS* and RDA* must be a logical zero. To read data from RAM B, both CS* and RDB* must be a logical zero. MPU addressing on PAx, PBx, and OLx must be valid while RDA* or RDB* is a logical zero. CS*, RDA*, and RDB* must not be a logical zero simultaneously. (See Figure 8.) WR* Write control input (1TL compatible). To write data to the device, both CS* and WR* must be a logical zero. MPU addresses on PAx and PBx are accepted on the falling edge of WR* or CS*, whichever occurs first. Data is accepted on the rising edge of WR* or CS*, whichever occurs first. MPU addressing on PAx, PBx, and OLx must be valid while WR* is a logical zero. RDx* and WR* must not be a logical zero simultaneously. (See Figure 9.) 00-D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. 00 is the least significant bit. VBB -1.3 V output. A 0.01 TILVCC TTL power. All TTL VCC pins must be connected together. TILGND TTL ground. All TIL GND pins must be connected together. ECLVCC ECL ground. All ECL VCC pins must be connected together. See Figures 4 and 5. DVFE ECL digital power. AU DVEE pins must be connected together. See Figures 4 and 5. AVFE ECL analog power. All AVEE pins must be connected together. See Figures 4 and 5. ~F decoupling capacitor to ECL VCC reduces threshold jitter. Warning: It Is Important that a ferrite bead be used to connect the AVEE power pins to the analog power plane as Illustrated in Figures 4 and 5. Alignment Pin 4· 520 The alignment pin is connected to the metallic cavity lid which is electrically isolated. SECTION 4 Brod REGISTERS SHIFT .. REGISTERS L-.-,_...J S f ~-~ / . . . ."7/L:8 _ _ _ _ _---f PBO -PB7 , -T{ r----I D~IDm D~IDm' .- Bt492 +--D~2IN so '$ lOR .L"'i---- lOR' D~2IN' [ ~> YBB "-r---r--"l -2Y ~ s t--"7,&.-/-+--/-.-S-----+-1 PAO - PA7 t-+-----+--I PBO-PB7 DIV20UT* SO:;;> Bt492 D~2IN' f-- _ > ~---IOG ;--1---1 D~IDUT [D1Y2IN '" YBB 100' -2Y : 1 '---,r-.--t--/-::S,----t----f Cl.OCK/2 PAO - PA7 '-,-r----+----I PBO - PB7 ~---IOB '---=~~--------4---~D~IDm ' - - - - - - - - - - - - - - - t - - - l D1YIDm' Cl.OCK'/2 t----1 D~2IN' [ SO:?- Bt492 D1Y2IN YBB .A:>f----- lOB' '----------' -2Y Figure 7. Using Multiple Bt492s. RAMDACs 4 - 527 Bt492 Recommended Operating Conditions Parameter ECL Power Supply ECLGround TTL Power Supply TTL Ground Ambient Operating Temperature Output Load Reference Voltage FS ADJUST Resistor Symbol Min Typ Max Units DVEE,AVEE ECLVCC TTLVCC TTLGND TA -4.2 -4.5 0 5 0 -5.5 +70 Volts Volts Volts Volts °C -1.29 Volts RL VREFIN 4.75 0 -1.17 RSEf 25 -1.23 729 5.25 Q Q Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. Absolute Maximum Ratings Parameter ECLSupply (measured to ECL VCC) TTL Supply (measured to GND) Max Units DVEE,AVEE -6.5 Volts TTLVCC +7.0 Volts Symbol Min Typ Voltage on Any ECL Input Pin ECLVCC DVEE Volts Voltage on Any TTL Pin TTLGND -0.5 TTLVCC +0.5 Volts °C °C °C Analog Output Short Circuit Duration to Any Common indefinite Ambient Operating Temperature Storage Temperature Junction Temperature TA TJ +125 +150 +175 Soldering Temperature (5 seconds, 1/4 inch from pin) TSOL 260 °C Still Air 28 °C/W 400LFM 13 °C/W 1S -55 -65 Junction-to-Ambient Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4 - 528 SECTION 4 Bt492 DC Characteristics Parameter Symbol Resolution Accuracy Integral Linearity Error Differential Linearity Error Gray Scale Error Internal Reference External Reference Monotonicity Coding Min Typ Max Units 8 8 8 Bits ±l/2 ±1/2 LSB LSB ±10 ±5 % Gray Scale % GrayScale n.. IX. guaranteed Binary TTL Digital Inputs Input High Voltage VlH 2.0 Input Low Voltage VlL TILGND -0.5 Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Vin = 2.4 V) IlH TTL Digital Outputs Output High Voltage (IOH=-2mA) Output Low Voltage (IOL=20mA) 3-State Current Output Capacitance ECL Digital Inputs Input High Voltage Input Low Voltage Input High Current Input Low Current Input Capacitance (f = 1 MHz, Vin = VIHmax) In.. CIN V 1/(20 fcn»*, it is recommended that an output buffer be used to drive a doubly terminated 75 0 load. COMP Resistor To optimize the settling time of the BU01, a resistor may be added in series between the CaMP capacitor and CaMP pin. The series resistor damps inductive ringing on CaMP, thus improving settling time. The value of the resistor is typically 15 0; however, the exact value is dependent on the PC board layout, clock rate, etc., and should be optimized for minimal settling time. An incorrect resistor value will result in degraded output performance, such as excessive ringing of the analog outputs or increased settling time. Non- Video Applications The Btl0l may be used in non-video applications by disabling the video-specific control inputs. SYNC* and REF WJflTE should be a logical zero and BLANK* should be a logical one. ISYNC should be connected to AGND. An three outputs will have the same fun-scale output current. The relationship between RSET and the full-scale output current (lout) in this configuration is as fonows: RSET (0) =7,958 * VREF (V) 1lout (rnA) With the data inputs at $00, there is a DC offset current (Imin) dermed as fonows: Imin (rnA) =650 * VREF (V) 1RSET (0) Therefore, the total full-scale output current will be lout + Imin. The REF WHITE input may optionally be used as a "force to full-scale" control. *(fc = clock frequency) 5 - 12 SECTION 5 The diode protection circuit shown in Figure 3 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 are low-capacitance, fast-switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7001). ESD and Latchup Considerations Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay V AA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. BtlOl Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Btl01KC30, Btl01KPJ Btl01BC Output Load Reference Voltage FS ADJUST Resistor Symbol Min Typ Max Units VAA TA 4.75 5.00 5.25 Volts +70 +85 ·C ·C Ohms Volts Ohms 0 -25 RL VREF 1.14 37.5 1.20 542 1.26 Min Typ Max Units 7.0 Volts VAA+0.5 Volts +125 +150 ·C ·C +175 +150 ·C ·C 'ISOL 260 ·C TVSOL 220 ·C RSEf Absolute Maximum Ratings Parameter Symbol VAA (measured to AGNO) Voltage on any Signal Pin· Analog Output Short Circuit Duration to any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature Ceramic Package Plastic Package Soldering Temperature (5 seconds, 1/4" from pin) Vapor Phase Soldering (1 minute) AGNO-0.5 ISC TA 'IS TJ indefinite -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. • This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. VIDEODACs 5 - 13 BtlOI DC Characteristics Parameter Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin =0.4 V) Input Capacitance (f = 1 MHz, Vin =2.4 V) Analog Outputs Gray Scale Current Range Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Blank Level on lOR, lOB Blank Level on lOG Sync Level on lOG LSB Size DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT =0 rnA) Symbol Min Typ Max Units 8 8 8 Bits ±0.3 ±0.3 ±1 guaranteed ±1 ±1 LSB LSB % Gray Sca1e IL IL ±5 Binary vrn V1L IIH ill.. 2.0 AGND-0.5 CIN VAA + 0.5 0.8 1 -1 17.69 16.74 0.95 0 6.29 0 VOC ROUf oour Voltage Reference Input Current IREF Power Supply Rejection Ratio (COMP =0.01 J,LF, f = 1 kHz) PSRR 19.05 17.62 1.44 5 7.62 5 69.1 2 -1.0 20 rnA 20.40 18.50 1.90 50 8.96 50 rnA rnA rnA +1.4 10 30 0.2 IIA IIA pF 10 15 Volts Volts IIA rnA IIA IIA % Volts kC pF 10 IIA 0.5 %/%I:J.VAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 542 C, VREF = 1.200 V, ISYNC connected to lOG. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 5· 14 SECTION 5 Br--H--- TO DACS FSADIUST IFEEDBACK L---40---<~-+-- AGND Equivalent Circuit of the Reference Amplifier. Bt101 00-07 100 SYNC· BLANK.· RL q.",y + load) (100 ONLY) Equivalent Circuit of the Current Output (lOG). VIDEODACs 5 • 17 Btl02 Distinguishing Features Applications • • • • • • • • • • • • • 75 MHz Pipelined Operation ±1/4 LSB Differential Linearity Error ±1/2 LSB Integral Linearity Error RS-343A/RS-170 Compatible Output 0,7, or 10 IRE Programmable Setup +5 V CMOS Monolithic Construction 24-pin 0.3" DIP Package Typical Power Dissipation: 550 mW High-Resolution Color Graphics CAE/CAD!CAM. hnage Processing Instrumentation Conventional D/A Product Description The Btl02 is an 8-bit multifunction VIDEODAC, designed specifically for color graphics and conventional D/A converter applications. Available control inputs include sync, blank, reference white, and 10% overbright. Additional features include a threshold set input to configure the digital inputs to be either TTL or CMOS compatible, and a setup input to specify one of three available setups in the analog output. Functional Block Diagram VREF 75 MHz Monolithic CMOS Single 8-bit VIDEODAC™ F5 ADJUST THRESHOlD SET CLOCK >--r---+- COMP An external 1.2 V voltage reference and a single resistor control the full-scale output current. The sync, blank, reference white, and 10% overbright inputs are pipelined to maintain synchronization with the input data. 8 DO-D7 )---+...... IOIIT 10'1. OVERBRIGIfl'O SYNC· IRET BLANK· 1..-----+-5ETUP REFWIIITE· VAA Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 Ll02001 Rev. E AGND 5 - 19 The Btl02 generates RS-343A compatible video signals into a doubly terminated 75 n load, and RS-170 compatible video signals into a singly terminated 75 n load, without requiring external buffering. The differential and integral linearity errors of the D/A converter are guaranteed to be a maximum of ±l/4 LSB and ±1/2 LSB, respectively, over the full temperature range. Btl02 Circuit Description As illustrated in the functional block diagram, the Btl02 contains a single 8-bit D/A converter, input registers, and a reference amplifier. The THRESHOLD SET input controls the logic thresholds of the digital inputs. If it is left floating, the logic thresholds are TTL compatible; if connected to VAA, the thresholds are CMOS compatible. On the rising edge of each clock cycle, as shown below in Figure 1, 8 bits of data (OO-D7) are latched into the device and presented to the 8-bit D/A converter. The REF WIDTE* input, latched on the rising edge of CLOCK, forces the inputs of the D/A converter to $FF, regardless of the value of the OO-D7 inputs. Latched on the rising edge of CLOCK to maintain synchronization with the data, the SYNC·, BLANK·, and 10% OVERBRIGHT· inputs add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figure 2. Table 1 details how the SYNC*, BLANK*, REF WHITE*, and 10% OVERBRIGHT* inputs modify the output level. Full-scale output current is set by an external resistor (RSET) between the FS ADJUST pin and AGND. The VREF input requires an external 1.2 V (typical) reference. For maximum performance, the voltage reference should be temperature comperJSated and provide a low-impedance output. The D/A converter on the Btl02 uses a segmented architecture in which bit currents are routed to either the output or IRET by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabilizes the full-scale output current against temperature and power supply variations. The analog output of the Btl02 is capable of directly driving a 375 n load, such as a doubly terminated 75 n coaxial cable. The SETUP input is used to control the difference between the black and blanking level. Available setups include 10 IRE (SETUP = VAA), 7 IRE (SETUP =float), and 0 IRE (SETUP =AGND). A setup of 0 IRE specifies that the blanking level is the same as the black level. CLOCK DO·D7,IG-.OVERBRIGIIT", SYNC·. BLANK·, REF WHrm* lOUT Figure 1. 5 - 20 SECTION 5 Input/Output Timing. Btl02 Circuit Description (continued) RSBT= 1130 RSBT= 1110 RSET= 1050 SETUP = SETIJP= FLOAT SETUP = AGND VAA 1RB 9.5 MA 28.90 1RB 10 Z7.o1 90 MA 28.74 10.7S 7.1 7.65 40.5 Note: 75 10'11> OVERBRlGHf LEVEL 26.97 WHITE LEVEL 8.23 BLACK LEVEL 8.23 BLANK LEVEL 0.00 SYNC LEVEL 0 7.72 0.00 29.00 100 9.09 9.59 39.5 MA 26.81 92.9 10 IRE 44 0.00 n doubly terminated load, VREF = 1.235 V. Figure 2. Description WlllTE+lo% WHIlE WHIlE DATA + 10% DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC RS-343A levels and tolerances assumed on all levels. Composite Video Output Waveform. lOur 10% REF (rnA) OVERBRIGHT'" WHITE· 28.74 26.81 26.81 data + 11.0 data + 9.09 data + 1.37 9.09 1.37 7.72 0 0 1 1 0 1 1 1 1 x x 1 0 1 1 1 1 1 1 x x Note: Typical with white level current =26.81 rnA. RSET Table 1. SYNC· BLANK· DAC Input Data 1 1 1 1 1 0 1 0 1 0 1 1 $FF $xx $FF data data data $00 $00 $xx $xx I 1 1 1 1 1 0 0 = 1110 n, VREF = 1.235 V, SETUP = float. Video Output Truth Table. VIDEODACs 5 • 21 Btl02 Pin Descriptions Pin Name Description BLANK* Composite blank control input ('ITL/CMOS compatible). A logical zero drives the output to the blanking level, as illustrated in Table 1. It is latched on the rising edge of CLOCK. When BLANK· is a logical zero, the OO-D7, REF WHITE·, and 10% OVERBRIGHT· inputs are ignored. SYNC* Composite sync control input (TTlJCMOS compatible). A logical zero on this input switches off a current source on the output equal to approximately 30% of the full-scale current (see Figure 2). SYNC· does not override any other control or data input, as shown in Table 1; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. REFWHITE* Reference white control input ('ITUCMOS compatible). A logical zero on this input forces the output to the white level, regardless of the OO-D7 inputs. It is latched on the rising edge of CLOCK. See Table 1. 10% OVERBRIGH'I'* Overbright control input ('ITL/CMOS compatible). A logical zero on this input causes the output current to increase by approximately 10 IRE units as shown in Table 1 and Figure 2. It is latched on the rising edge of CLOCK. OO-D7 Data inputs (TTUCMOS compatible). DO is the least significant data bit. They are latched on the rising edge of CLOCK. Coding is binary. CLOCK Clock input ('ITUCMOS compatible). The rising edge of CLOCK latches the DO-D7, SYNC·, BLANK·, REF WHITE*, and 10% OVERBRIGHT· inputs. It is typically the pixel clock rate of the video system. It is recommended that the CLOCK input be driven by a dedicated TTL or CMOS buffer to avoid reflection-induced jitter. SETUP Setup control input. This pin controls the difference between the black level and the blanking level. Available setups include 10 IRE units (SETUP = VAA), 7 IRE units (SETUP = float), and 0 IRE units (SEfUP = AGND). THRESHOLD SEf Threshold control input. This pin controls the logic thresholds of the digital inputs. If connected to VAA through a 0.1 IlF ceramic capacitor, the logic thresholds are TTL compatible. If connected directly to VAA, the thresholds are CMOS compatible. lour Current output. This high-impedance current source is capable of directly driving a doubly terminated 75 n coaxial cable (Figure 3). IRET Current return. This pin must be connected to AGND through a ferrite bead, as illustrated in Figure 3. AGND Analog ground. All AGND pins must be connected. VAA. Analog power. All VAA pins must be connected. VREF Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 3, must supply this input with a 1.2 V (typical) reference. The use of a resistor network to generate the reference is not recommended, as any low-frequency power supply noise on VREF will be directly coupled onto the analog outputs. A 0.1 IlF ceramic capacitor must be used to decouple this input to VAA, as shown in Figure 3. The decoupJing capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. 5·22 SECTION 5 Btl02 Pin Descriptions (continued) Pin Name Description COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.01 IJ.F ceramic capacitor in series with a resistor must be connected between this pin and the adjacent VAA pin (Figure 3). Connecting the capacitor to VAA rather than to AGND provides the highest possible power supply noise rejection. The COMP resistor and capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and AGND controls the magnitude of the full-scale video signal (Figure 3). Note that the IRE relationships in Figure 3 are maintained regardless of the full-scale output current. The relationship between RSET and the white level output current is: RSET (0) = K1 * VREF (V) I lOur (rnA) The amount of additional current generated to achieve the overbright level is: lOUT (rnA) = K2 * VREF (V) I RSET (0) K1 and K2 are defmed as follows: .. SETIJP float VAA AGND K1 24,096 24,713 22,930 K2 1,735 1,729 1,726 RBI'WHrrB" BLANK" TTl VAA 10. OVERBRIGHT' SYNC" D6 SIl1llP os IRBT D4 lour a.DCK AGND D3 D2 VAA COMP D1 I'SADlUST DO VRBI' THRESHOlD SET AGND VIDEODACs 5 - 23 Btl02 PC Board Layout Considerations PC Board Considerations Supply Decoupling The layout should be optimized for lowest noise on the Btl02 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and AGND pins should be as short as possible so as to minimize inductive ringing. The bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Ground Planes For the best performance, a 0.1 j.LF ceramic capacitor should be used to decouple each VAA pin to AGND. These capacitors should be placed as close as possible to the device. For optimum performance, a common digital and analog ground plane with tub isolation (at least a 1I8-inch gap) connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector. It is important to note that, while the Btl02 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. The analog ground plane should include all BtlOl ground pins, all reference circuitry and decoupling, power supply bypass circuitry for the BtlOl, analog output traces, and the video output connector. Digital Signal Interconnect Power Planes Due to the high clock rates involved, long clock lines to the Btl02 should be avoided to reduce noise pickup. The Btl02 and any associated analog circuitry should have its own power plane, referred to as the analog power plane. This power plane should be connected to the regular PCB power plane at a single point through a ferrite bead, as illustrated in Figure 3. This bead should be located within 3 inches of the Btl02. The digital inputs to the Btl02 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog ground and power planes. Any termination resistors for the digital inputs should be connected to the regular PCB power and ground planes. Analog Signal Interconnect The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Btl02 power pins, voltage reference circuitry, and any output amplifiers. It is important that portions of the regular PCB power and ground planes do not overlay portions of the analog power or ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. This will reduce plane-to-plane noise coupling. 5 - 24 SECTION 5 The Btl02 should be located as close as possible to the output connector to minimize noise pickup and reflections due to impedance mismatch. The video output signal should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog output should have a 75 n load resistor connected to AGND. The connection between the current output and AGND should be as close as possible to the Btl02 to minimize reflections. Btl02 PC Board Layout Considerations (continued) R3 C4 cs L1 L....___ +5V Cl C6 Btl02 FSADJUST TO IRIlT VIDEO L2 CONNECTOR IOIITI------_~----__{ p VAA o DAC 01ITPlIT IN4148/9 - - - - - - . - - - TOMONITOR IN4148/9 AGND Location Description C1, C2, C3, C5 C4 C6 L1, L2 R1 R2 R3 RSEl' Zl 0.1 J.IF ceramic capacitor 0.01 I1F ceramic capacitor 10 I1F tantalum capacitor ferrite bead 75 n 1% metal film resistor 1000 n 1% metal ftlm resistor 27 n 1% metal film resistor I % metal film resistor 1.2 V voltage reference Vendor Part Number Erie RPEl12Z5U104M50V Erie RPE110Z5U103M50V Mallory CSR13G106KM Fair-Rite 2743001111 Dale CMF-55C Dale CMF-55C Dale CMF-55C Dale CMF-SSC National Semiconductor LM385BZ-1.2 Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the Bt102. Figure 3. Substitution of devices with similar Typical Connection Diagram and Parts List. VIDEODACs 5·25 Btl02 Application Information RS·170 Video Generation For generation of RS-170 compatible video, it is recommended that a singly terminated 75 0 load be used with the SBTUP pin floating and an RSBT value of about 1594 O. If the Btl02 is not driving a large capacitive load, there will be negligible difference in video quality between doubly terminated 75 0 and singly terminated 75 0 loads. The relationship between RSBT and the full-scale output current in this configuration is as follows: RSET (0) = 15,933 • VRBF (V) I lOUT (rnA) The BLANK* input may optionally be used as a "force to zero" control, and the RBF WHITB· input may optionally be used as a "force to full-scale" control. COMP Resistor If driving a large capacitive load (load RC > 11(20 fc7t»*, it is recommended that an output buffer be used to drive a doubly terminated 75 0 load. Color Applications Note that in color applications, sync information is typically required only on the green channel. Therefore, the SYNC* inputs to the red and blue VIDBODACs may always be a logical zero. If SYNC'" is always a logical zero, the relationship between RSBT and the full-scale output current is: lOUT (rnA) = K * VRBF (V) I RSET (0) where K is equal to 17,714; 17,158; or 15,933 for SBTUP =VAA, float, and AGND, respectively. Using Multiple Devices If located close together on the same PC board, multiple Btl02 devices may be connected to a single analog power and ground plane. In addition, a single voltage reference may be used to drive multiple devices. Bach Btl02 must still have its individual RSBT resistor, lOUT termination resistor (Rl in Figure 3), IRBT ferrite bead (L3 in Figure 3), power supply bypass capacitors (C2 and C3 in Figure 3), and CaMP resistor and capacitor (C4 and R3 in Figure 3). At high clock rates, individual ground beads (L2 in Figure 3) may be required to maintain TTL thresholds due to the high current return. Non· Video Applications The Btl02 may be used in non-video applications by disabling the video-specific control inputs. SYNC'" should be a logical zero, while RBF WHITB*, 10% OVBRBRIGHT., and BLANK'" should be a logical one. SBTUP should be connected to AGND. The output current will be determined solely by the DO-D7 inputs. ·(fc = clock frequency) 5 • 26 SECTION 5 To optimize the settling time of the Btl02, a resistor may be added in series between the CaMP capacitor and CaMP pin. The series resistor damps inductive ringing on CaMP, thus improving settling time. The value of the resistor is typically 27 n. however, the exact value is dependent on the PC board layout, clock rate, etc., and should be optimized for minimal settling time. An incorrect resistor value will result in degraded output performance, such as excessive ringing of the analog outputs or increased settling time. Analog Output Protection The Btl02 analog output should be protected against high-energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figure 3 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 are low-capacitance, fast-switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD700l). ESD and Latchup Considerations Correct BSD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay VAA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. Btl02 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage Symbol Min Typ Max Units VAA TA 4.75 -25 5.00 5.25 +85 RL VREF 1.14 37.5 1.235 1.26 Volts ·C Ohms Volts Symbol Min Typ Max Units 7.0 Volts VAA+O.5 Volts TJ +125 +150 +175 ·C ·C ·C TSOL 260 ·C Absolute Maximum Ratings Parameter VAA (measured to AGND) Voltage on Any Signal Pin* Analog Output Short Circuit Duration to Any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, 1/4" from pin) AGND-0.5 ISC TA TS .. indefinite -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. VIDEODACs 5 • 27 Btl02 DC Characteristics Parameter Resolution Accuracy Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs TIL-Compatible Mode Input High Voltage Symbol Typ Max Units 8 8 8 Bits ±1/2 ±1/4 ±5 LSB LSB % GrayScale IL IL guaranteed Binary V1H CLOCK Other Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance CMOS-Compatible Mode Input High Voltage Input Low Voltage Input High Current (Vin = 3.5 V) Input Low Cmrent (Vin = 1.5 V) Input Capacitance Min VIL TIH IlL 3.0 2.0 AGND-0.5 -200 -200 10 CIN V1H VIL TIH IlL 3.5 AGND-0.5 ROur cour Voltage Reference Input Current mEF Power Supply Rejection Ratio (COMP = 0.01 JlF, f = 1 kHz) PSRR AGND+0.5 0.8 2 2 15 vex: Volts Volts Volts J.lA. J.lA. pF 10 CIN Analog Output Gray Scale Current Range Output Current Overbright Relative to White White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank SETUP = float SETUP=AGND SETUP = VAA Blanking Level Sync Level LSB Size Output Compliance Output Impedance Output Capacitance VAA+0.5 VAA + 0.5 0.8 -1200 -1200 Volts Volts J.lA. J.lA. pF 20.5 rnA 1.60 17.90 16.80 1.93 19.09 17.72 2.40 20.31 18.61 rnA rnA rnA 1.10 0 1.6 7.2 0 1.37 5 1.93 7.72 5 69.5 1.70 50 2.4 8.3 50 rnA +1.4 Volts -1.0 J.lA. J.lA. Kn 33 20 0.2 J.lA. rnA rnA pF 10 J.lA. 0.5 %1%tNAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with SETUP = float, RSET = 1110 n, VREF = 1.235 V. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 5 ·28 SECTION 5 Btl02 AC Characteristics Parameter Symbol Clock Rate Fmax Data and Control Setup Time Data and Control Hold Time 1SU Clock Cycle Time Clock Pulse Width Low Clock Pulse Width High Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time* to± If}. LSB to± 1 LSB Clock and Data Feedthrough* Glitch Impulse· Differential Gain Error Differential Phase Error 1M TCYC TClKH TCLKL Typ Max Units 75 MHz 4 I ns ns 13.33 5 6 ns ns ns IDLY TVRF TS 00 DP Pipeline Delay VAA Supply Current·· Min 3 IAA 20 6 ns ns 15 12 -20 100 ns ns dB pV - sec 1 1 % Gray Sca1e Degree 3 3 Clocks 110 175 rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 1110 n, VREF = 1.235 V. THRESHOLD SET = TTL mode, SETUP = float. TTL input values are 0-3 V, with input rise/fall times S 4 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. COMP resistor = 27 n. Analog output load S 10 pF. See timing notes in Figure 4. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the digital inputs have a 1 ill resistor to the regular PCB ground plane and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 150 MHz . • *At Fmax. IAA (typ) at VAA = 5.0 V. lAA (max) at VAA = 5.25 V. VIDEODACs 5 - 29 .. Btl02 Ordering Information Model Number Speed Package Ambient Temperature Range BtlO2BC 75 MHz 24-pin 0.3" _25° to +85° C CERDIP Btl02EVM Evaluation Board for the Btl02 Timing Waveforms a..OCK DO - D7. 10. OVERBRIGHf•• SYNC·. BLANK·. REP WIIITB· lOUT Note 1: Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Note 2: Settling time measured from the 50% point of full-scale transition to the output remaining within ±1/2 LSB or ±1 LSB. Note 3: Output rise/fall time measured between the 20% and 80% points of full-scale transition. Figure 4. 5 - 30 SECTION 5 Input/Output Timing. Btl02 Device Circuit Data High-speed operation is accomplished through pipelining and a unique (patent pending) TIL input buffer. This input buffer features a resistive level shifter that uses a temperature and process-compensated current source. The 0.5 rnA bias current is disabled when THRESHOLD SET is connected to V AA. resulting in a standard high-impedance CMOS input. Equivalent Circuit of the Digital Inputs . .---__ --------~i--TODAC FSADJUST IFIlIlDBACK L-_~_~ +-_ __ AOND Equivalent Circuit of the Reference Amplifier. Btl02 --~--~~-~~--~- VAA DO-D7 lOur 10'lI0 OVERBRIOHfO RL C("'ay + lcod) Equivalent Circuit of the Current Output. VIDEODACs 5 • 31 Btl03 Distinguishing Features Applications " High-Resolution Color Graphics " CAE/CAD/CAM Image Processing Video Reconstruction 75,30 MHz Operation Triple 4-bit D/A Converters ±1/l6 LSB Differential Linearity Error ±1/8 LSB Differential Linearity Error RS-343AIRS-170 Compatible Outputs TTL-Compatible Inputs +5 V CMOS Monolithic Construction 28-pin DIP Package Typical Power Dissipation: 800 mW Product Description The Bt103 is a triple 4-bit VIDEODAC, designed specifically for high-performance, high-resolution color graphics. Available control inputs include sync and blank, both pipelined to maintain synchronization with . . the color data. An on-chip voltage reference simplifies design, and a single external resistor controls the full-scale output current. Functional Block Diagram FS ADJUST CLOCK COMPI RO-R3 lOR GO· 03 lOG BO-B3 lOB SYNC· COMP2 BLANK" VAA Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580" (800) VlDEO IC TLX: 383 596 "FAX: (619) 452-1249 Ll03001 Rev. E 75 MHz Monolithic CMOS Triple 4-bit VIDEODAC™ AOND 5 - 33 The Bt103 generates RS-343A compatible video signals into a doubly terminated 75 n load, and RS-170 compatible video signals into a singly terminated 75 n load, without requiring external buffering. The differential and integral linearity errors of the DIA converters are guaranteed to be a maximum of ±1/16 LSB and ±1/8 LSB, respectively, over the full temperature range. Bt103 Circuit Description As illustrated in the functional block diagram, the Btl03 contains three 4-bit D/A converters, input registers, voltage reference, and a reference amplifier. As shown below in Figure I, on the rising edge of each clock cycle, 12 bits of color information (RO-R3, GO-03, and BO-B3) are latched into the device and presented to the three 4-bit D/A converters. The SYNC* and BLANK* inputs, also latched on the rising edge of CLOCK and pipelined to maintain synchronization with the color data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figure 2. Table 1 details how the SYNC* and BLANK* inputs modify the output levels. The full-scale output current is set by an external resistor (RSET) between the FS ADJUST pin and AGND. RSET has a typical value of 499 n for generation of RS-343A video into a 37.5 n load. The D/A converters on the Btl03 use a segmented architecture in which bit currents are routed to either the output or AGND by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabilizes the full-scale output current against temperature and power supply variations. The analog outputs of the Btl03 are capable of directly driving a 37.5 n load, such as a doubly terminated 75 n coaxial cable. Q.OCK RO·R3, GO·G3, BO·B3, SYNC·, BLANK· DATA lOR, lOG, lOB Figure 1. 5·34 SECTION 5 Input/Output Timing. Btl03 Circuit Description (continued) RED. BLUE GREEN MA V MA 19.05 0.714 11i.67 1.000 -r-----.~----------------------~~------wmm~~ 1.19 0.045 8.81 0.330 +------------+--------I~---------------- BLACK LE~ 0.00 0.000 7.62 0.286 +------------J.-..,.--r-~------------------ BLANK LEVEL 0.00 0.000 V 40lRE Note: 75 levels. n -L--____________ doubly terminated load, RSET = 499 Figure 2. ~ __L -____________________ n. SYNCLE~ RS-343A levels and tolerances assumed on all • Composite Video Output Waveforms. Description IOG(mA) IOR(mA) lOB (mA) SYNC* BLANK* DAC Input Data WHITE DATA DATA-SYNC BLACK BLACK-SYNC 26.67 data + 8.81 data+ 1.19 8.81 1.19 7.62 0 19.05 data + 1.19 data + 1.19 1.19 1.19 0 0 19.05 data + 1.19 data + 1.19 1.19 1.19 0 0 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $F data data $0 $0 $x $x BlANK SYNC Note: Typical with full-scale lOG = 26.67 rnA. RSET = 499 n. Table 1. Video Output Truth Table. VIDEODACs 5 • 35 Btl03 Pin Descriptions Pin Name Description BLANK* Composite blank control input (TTL compatible). A logical zero drives the analog outputs to the blanking level, as illustrated in Table 1. It is latched on the rising edge of CLOCK. When BLANK* is a logical zero, the RO-R3, GO-G3, and BO-B3 inputs are ignored. SYNC* Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source on the lOG output (see Figure 2). SYNC* does not override any other control or data input, as shown in Table 1; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. RO-R3, GO-G3, BO-B3 Red, green, and blue data inputs (TTL compatible). RO, GO, and BO are the least significant data bits. They are latched on the rising edge of CLOCK. Coding is binary. CLOCK Clock input (TTL compatible). The rising edge of CLOCK latches the RO-R3, GO-G3, BO-B3, SYNC*, and B LANK* inputs. It is typically the pixel clock rate of the video system. It is recommended that the CLOCK input be driven by a dedicated TTL buffer to avoid reflection-induced jitter. lOR, lOG, lOB Red, green, and blue current outputs. These high-impedance current sources are capable of directly driving a doubly terminated 75 n coaxial cable (Figure 3). All outputs, whether used or not, should have the same output load. AGND Analog ground. All AGND pins must be connected. VM Analog power. All VAA pins must be connected. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and AGND controls the magnitude of the full-scale video signal (Figure 2). Note that the IRE relationships in Figure 2 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on lOG is: RSET (n) = 13,308/ lOG (rnA) The full-scale output current on lOR and lOB for a given RSET is defined as: IOR, IOB (rnA) =9,506/ RSET (0) 5 • 36 SECTION 5 Btl03 Pin Descriptions (continued) Pin Name COMP1, COMP2 Description Compensation pins. These pins provide compensation for the internal reference amplifier. A 0.1 !iF ceramic capacitor must be connected between these two pins (Figure 3). The COMP resistor and capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. .. R3 N/C HZ SYNC'" RI lOR RO lOG 03 lOB 02 VAA G1 COMPZ GO FS ADJUST B3 COMPI B2 AGND BI AOND DO BLANK'" N/C AGND VAA CLOCK Note: N/C pins may be left floating without affecting the performance of the Bt103. VIDEODACs 5 ·37 Btl03 PC Board Layout Considerations PC Board Considerations Supply Decoupling The layout should be optimized for lowest noise on the Bt103 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and AGND pins should be as short as possible to minimize inductive ringing. The bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Ground Planes For the best performance, a 0.1 IJ.F ceramic capacitor should be used to decouple each VAA pin to AGND. These capacitors should be placed as close as possible to the device. For optimum performance, a common digital and analog ground plane with tub isolation (at least a liS-inch gap) connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector. It is important to note that, while the Bt103 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. The analog ground plane should include all Bt10l ground pins, all reference circuitry and decoupling, power supply bypass circuitry for the Btl01, analog output traces, and the video output connector. Digital Signal Interconnect Power Planes The Bt103 and any associated analog circuitry should have its own power plane, referred to as the analog power plane. This power plane should be connected to the regular PCB power plane at a single point through a ferrite bead, as illustrated in Figure 3. This bead should be located within 3 inches of the Bt103. The digital inputs to the Btl 03 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog ground and power planes. Due to the high clock rates involved, long clock lines to the B t1 03 should be avoided to reduce noise pickup. Any termination resistors for the digital inputs should be connected to the regular PCB power and ground planes. Analog Signal Interconnect The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Btl 03 power pins and any output amplifiers. It is important that portions of the regular PCB power and ground planes do not overlay portions of the analog power or ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. This will reduce plane-to-plane noise coupling. 5 • 38 SECTION 5 The Bt103 should be located as close as possible to the output connectors to minimize noise pickup, and reflections due to impedance mismatch. The video output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog outputs should each have a 75 Q load resistor connected to AGND. The connection between the current output and AGND should be as close as possible to the Btl03 to minimize reflections. Btl03 PC Board Layout Considerations (continued) COMP2 R4 C4 ANALOG POWER PLANE Ll n..._I""'"_ _ +SV Cl Btl03 RSET Rl R2 R3 FSADJUST IOR~--------+---~--+-------~ TO VIDEO lOG I-------------.....--+-------__{ CONNECTOR IOBI-----------------~------__{ VAA IN4148/9 DAC -------- 1/(20 fc1t»*. it is recommended that an output buffer be used to drive a doubly terminated 75 Q load. COMP Resistor To optimize the settling time of the Bt103. a resistor may be added in series between the CaMP capacitor and CaMP pin. The series resistor damps inductive ringing on CaMP. thus improving settling time. The value of the resistor is typically 22 Q. however. the exact value is dependent on the PC board layout. clock rate. etc .• and should be optimized for minimal settling time. An incorrect resistor value will result in degraded output performance. such as excessive ringing of the analog outputs or increased settling time. Non- Video Applications The Bt103 may be used in non-video applications by disabling the video-specific control inputs. SYNC* should be a logical zero and BLANK* should be a logical one. All three outputs will have the same full-scale output current. The relationship between RSET and the full-scale output current (lout) in this configuration is as follows: RSET (Q) = 8.912/ lout (rnA) With the data inputs at $00. there is a DC offset current (Imin) defined as follows: Imin (rnA) = 594/ RSET (Q) Therefore. the total full-scale output current will be lout + Imin. *(fc =clock frequency) 5 - 40 SECTION 5 The diode protection circuit shown in Figure 3 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 are low-capacitance. fast-switching diodes. which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7(01). ESD and Latchup Considerations Correct ESD-sensitive handling procedures are required to prevent device damage. which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants. which could delay V AA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all VAA pins are at the same potential. and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. Btl03 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Btl03KC30 Btl03BC Output Load FS ADJUST Resistor Symbol Min Typ Max Units VAA TA 4.75 5.00 5.25 Volts +70 +85 ·C ·C Ohms Ohms Max Units 7.0 Volts VAA+05 Volts TJ +125 +150 +175 ·C ·C ·C TSOL 260 ·C 0 -25 RL 37.5 499 RSET Absolute Maximum Ratings Parameter Symbol Min Typ VAA (measured to AGND) Voltage on any Signal Pin* Analog Output Short Circuit Duration to any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds. 1/4" from pin) AGND-05 ISC TA TS - indefinite -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. VIDEODACs 5 - 41 Btl03 DC Characteristics Parameter Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Vin = 2.4 V) Analog Outputs Gray Scale Current Range Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Blank Level on lOR, lOB Blank Level on lOG Sync Level on lOG LSB Size DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 rnA) Symbol Min Typ Max Units 4 4 4 Bits ±l/8 ±1/l6 ±10 LSB LSB % GrayScale IL IL guaranteed Binary VlH VIL IIH IlL VAA+0.5 0.8 -1200 -1200 2.0 AGNO-O.5 -200 -200 10 CIN 15 16.88 15.86 1.02 0 6.29 0 VOC ROUT COUT 19.05 17.62 1.19 5 7.62 5 1.175 2 Volts Volts IIA IIA pF 20 rnA 20.69 19.38 1.31 50 8.96 50 rnA rnA rnA IIA rnA IIA rnA 5 +1.4 10 20 % Volts kQ pF Volts -1.0 Internal Voltage Reference VREF 1.2 Power Supply Rejection Ratio (COMP = 0.1 JlF, f = 1 kHz) PSRR 0.2 0.5 %1%ilVAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 499 Q. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 5 - 42 SECTION 5 Btl03 AC Characteristics 30 MHz Devices 75 MHz Devices Parameter Clock Rate Symbol Min Typ Fmax Max Min Typ Max Units 30 MHz 75 Data and Control Setup Time Data and Control Hold Time TSU 1H 4 1 10 2 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time TCYC TClKH 13.3 5 5 33.3 10 10 ns ns ns Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time* Clock and Data Feedthrough* Glitch Irnpulse* DAC-to-DAC Crosstalk Analog Output Skew TCLKL IDLY VAA Supply Current** 4 TS Pipeline Delay 2 IAA 12 12 TVRF 12 -30 50 -25 0 2 2 2 175 9 2 ns ns ns 15 -30 50 -25 0 2 ns 2 2 Clocks 110 rnA dB pV - sec dB Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 499 O. TTL input values are 0-3 V, with input rise/fall times ~ 4 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. COMP resistor = 22 O. Output load ~ 10 pF. See timing notes in Figure 4. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the digital inputs have a 1 ill resistor to the regular PCB ground plane and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth =2x clock rate. **At Fmax. IAA (max) at VAA = 5.25 V. VIDEODACs 5 • 43 Btl03 Ordering Information Model Number Speed Package Ambient Temperature Range Btl03BC 75 MHz 28-pin 0.6" _25° to +85° C CERDIP Btl03KC30 30 MHz 28-pin 0.6" 0° to +70° C CERDIP Btl03EVM Evaluation Board for the Btl03 Timing Waveforms CLOCK RO·R3. 00·03. BO·B3. SYNC'. BLANK' KlR. 100. lOB Note 1: Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Note 2: Settling time measured from the 50% point of full-scale transition to the output remaining within ±1/8 LSB. Note 3: Output rise/fall time measured between the 10% and 90% points of full-scale transition. Figure 4. 5·44 SECTION 5 Input/Output Timing. Btl03 Device Circuit Data High-speed operation is accomplished through pipelining and a unique (patent pending) TIL input buffer. This input buffer features a resistive level shifter that uses a temperature and process-compensated current source. Equivalent Circuit of the Digital Inputs. r-~r-------------~--~r----VAA >--++---TODACS lFIlIlIlBACK Equivalent Circuit of the Reference Amplifier. BtlO3 VAA 00·07 lOG SYNC· (lOG ONLy) BLANK" T- 2Al P' RL C("'y+lood) Equivalent Circuit of the Current Output (lOG). VIDEODACs 5 - 45 \ Btl06 Distinguishing Features Applications • • • • • • • • • • • • • 50, 30 MHz Operation ±1 LSB Differential Linearity Error ±1 LSB Integral Linearity Error RS-343NRS-170 Compatible Output TTL-Compatible Inputs +5 V CMOS Monolithic Construction 20-pin DIP Package Typical Power Dissipation: 400 mW High-Resolution Color Graphics CAE/CAD/CAM Image Processing Video Reconstruction Instrumentation Product Description The Btl06 is an 8-bit VIDEODAC, designed specifically for high-performance, high-resolution color graphics. Available control inputs include sync, blank, and reference white. The reference white input forces the analog output to the reference white level, regardless of the data inputs. Functional Block Diagram VREF 50 MHz Monolithic CMOS Single 8-bit VIDEODAC ni An external 1.2 V voltage reference and a single resistor control the full-scale output current. The sync, blank, and reference white inputs are pipelined to maintain synchronization with the digital input data. FS ADJUST CLOCK COMP 8 00-01 lOur REFWHITE SYNC· BLANK· VAA Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 Ll06001 Rev. G AGNO 5 - 47 The Btl06 generates RS-343A compatible video signals into a doubly terminated 75 n load, and RS-170 compatible video signals into a singly terminated 75 n load, without requiring external buffering. Both the differential and integral linearity errors of the D/A converter are guaranteed to be a maximum of ±1 LSB over the full temperature range. - Btl06 Circuit Description As illustrated in the functional block diagram, the Btl06 contains an 8-bit D/A converter, input registers, and a reference amplifier. On the rising edge of each clock cycle, as shown below in Figure 1, 8 bits of data are latched into the device and presented to the 8-bit D/A converter. The REF WHITE input, latched on the rising edge of CLOCK, forces the inputs of the D/A converter to $FF. Latched on the rising edge of CLOCK to maintain synchronization with the data, the SYNC· and BLANK· inputs add appropriately weighted currents to the analog output, producing the specific output levels required for video applications, as illustrated in Figure 2. Table 1 details how the SYNC·, BLANK·, and REF WHITE inputs modify the output level. The D/A converter on the Bt106 uses a segmented architecture in which bit currents are routed to either the output or AGND by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabilizes the full-scale output current against temperature and power supply variations. The analog output of the Btl06 is capable of directly driving a 37.5 n load, such as a doubly terminated 75 n coaxial cable. Full-scale output current is set by an external resistor (RSET) between the FS ADJUST pin and AGND. RSET has a typical value of 542 n for generation of RS-343A video into a 37.5 n load. The VREF input requires an external 1.2 V (typical) reference. For maximum performance, the voltage reference should be temperature compensated and provide a low-impedance output. CLOCK 00·07. SYNC". BLANK". REP WHl11l DATA IOIIT Figure 1. 5 • 48 SECTION 5 Input/Output Timing. Btl06 Circuit Description (continued) MA V 2f>.ffI 1.000 -,------...----------------::=---- WHrrl! LBVllL 9.05 0.340 -r-----~r_---~--------mAaLBVllL 7.62 0.286 -+--------I---...,....---r-~-------- BLANK LBVllL 401RB ~ 0.00 Note: 75 levels. n _______ doubly tenninated load, RSET = 542 Figure 2. Description WHIlE WHIlE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC ~-L _ _ _ _ _ _ _ _ _ _ SYNCLBVBL 0.000 n, VREF = 1.2 V. RS-343A levels and tolerances assumed on all Composite Video Output Waveform. lOur REF (rnA) WHIlE 26.67 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 1 0 0 0 0 0 x x SYNC· BLANK· DAC Input Data 1 1 1 1 $xx $FF data data $00 $00 $xx $xx 1 1 0 1 0 1 0 1 1 1 0 0 Note: Typical with full-scale lOUT = 26.67 rnA. RSET = 542 n, VREF = 1.2 V. Table 1. Video Output Truth Table. VIDEODACs 5·49 Btl06 Pin Descriptions Pin Name Description BLANK'" Composite blank control input (ITL compatible). A logical zero drives the lOUT output to the blanking level, as illustrated in Table 1. It is latched on the rising edge of CLOCK. When BLANK'" is a logical zero, the OO-D7 and REF WHITE inputs are ignored. SYNC'" Composite sync control input (ITL compatible). A logical zero on this input switches off a 40 IRE current source on the output (see Figure 2). SYNC'" does not override any other control or data input, as shown in Table 1; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. REF WHITE Reference white control input (TTL compatible). A logical one on this input forces the output to the white level, regardless of the OO-D7 inputs. It is latched on the rising edge of CLOCK. See Table 1. DO-D7 Data inputs (ITL compatible). DO is the least significant data bit. They are latched on the rising edge of CLOCK. Coding is binary. CLOCK Clock input (TTL compatible). The rising edge of CLOCK latches the OO-D7, SYNC"', BLANK"', and REF WHITE inputs. It is typically the pixel clock rate of the video system. It is recommended that the CLOCK input be driven by a dedicated TTL buffer to avoid reflection-induced jitter. lOur Current output. This high-impedance current source is capable of directly driving a doubly terminated 75 Q coaxial cable (Figure 3). AGND Analog ground. All AGND pins must be connected. VAA Analog power. All VAA pins must be connected. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and AGND controls the magnitude of the full-scale video signal (Figure 2). Note that the IRE relationships in Figure 2 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current is: RSET (Q) = 12,046 ,.. VREF (V) I lOUT (rnA) 5 - 50 SECTION 5 Btl06 Pin Descriptions (continued) Pin Name Description COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.01 fJ.F ceramic capacitor in series with a resistor must be connected between this pin and the adjacent VAA pin (Figure 3). Connecting the capacitor to VAA rather than to AGND provides the highest possible power supply noise rejection. The COMP resistor and capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. VREF Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 3, must supply this input with a 1.2 V (typical) reference. The Bt106 has an internal pull-up resistor between VAA and VREF. As the value of this resistor may vary slightly due to process variations, the use of a resistor network to generate the reference is not recommended. A 0.1 fJ.F ceramic capacitor must be used to decouple this input to VAA, as shown in Figure 3. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. a.oac: SYNC" IJ7 VAA D6 AOND DS AOND D4 lOUT D3 VAA D2 roMP D1 FS AJ)JIJST DO VRBF REFWHITB BLANK" VIDEODACs 5·51 Btl06 PC Board Layout Considerations PC Board Considerations Supply Decoupling The layout should be optimized for lowest noise on the Bt106 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and AGND pins should be as short as possible to minimize inductive ringing. The bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Ground Planes For the best performance, a 0.1 I1F ceramic capacitor shOUld be used to decouple each VAA pin to AGND. These capacitors should be placed as close as possible to the device. For optimum performance, a common digital and analog ground plane with tub isolation (at least a l/8-inch gap) connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector. It is important to note that while the Btl06 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. The analog ground plane should include all Bt106 ground pins, all reference circuitry and decoupling, power supply bypass circuitry for the Bt106, analog output traces, and the video output connector. Digital Signal Interconnect Power Planes Due to the high cIock rates involved, long clock lines to the Bt106 should be avoided to reduce noise pickup. The Bt106 and any associated analog circuitry should have its own power plane, referred to as the analog power plane. This power plane should be connected to the regular PCB power plane at a single point through a ferrite bead, as illustrated in Figure 3. This bead should be located within 3 inches of the Btl 06. The digital inputs to the Bt106 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog ground and power planes. Any termination resistors for the digital inputs should be connected to the regular PCB power and ground planes. Analog Signal Interconnect The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Btl06 power pins, voltage reference circuitry, and any output amplifiers. It is important that portions of the regular PCB power and ground planes do not overlay portions of the analog power or ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. This will reduce plane-to-plane noise coupling. 5 - 52 SECTION 5 The Bt106 should be located as close as possible to the output connector to minimize noise pickup and reflections due to impedance mismatch. The video output signal should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog output should have a 75 n load resistor connected to AGND. The connection between the current output and AGND should be as close as possible to the Bt106 to minimize reflections. Btl06 PC Board Layout Considerations (continued) ANALOG POWER PLANE C5 Ll '--<1..,.___ +!lV Cl Btl06 ~_ _~_~_ _ _ _. .~. ._ _ _ _ _. ._ _ _ _ _. ._ _• GROUND TO VIDEO ~--------4-----------------{P CONNEcroR VAA lN4148/9 DAC TO MONITOR OlITPUT lN4148/9 - AGND Location Description Cl, C2, C3, C5 C4 C6 L1 Rl R2 0.1 ~ ceramic capacitor 0.01 ~F ceramic capacitor 10 ~F tantalwn capacitor ferrite bead 75 n 1% metal film resistor 12 n 1% metal film resistor 542 n 1% metal film resistor 1.2 V voltage reference RSET ZI Vendor Part Nwnber Erie RPE112Z5UI04M50V Erie RPE 11 OZSUI 03M50V Mallory CSR13GI06KM Fair-Rite 2743001111 Dale CMF-55C Dale CMF-55C Dale CMF-55C National Semiconductor LM385BZ-1.2 Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the B1106. Figure 3. Substitution of devices with similar Typical Connection Diagram and Parts List. VIDEODACs 5 ·53 Btl06 Application Information RS-170 Video Generation For generation of RS-170 compatible video, it is recommended that a singly terminated 75 n load be used with an RSET value of about 774 n. If the Btl06 is not driving a large capacitive load, there will be negligible difference in video quality between doubly terminated 75 n and singly terminated 75 n loads. If driving a large capacitive load (load RC > 1/ (20Fc»,'" it is recommended that an output buffer be used to drive a doubly terminated 75 n load. Color Applications Note that in color applications, sync information is typically required only on the green channel. Therefore, the SYNC'" inputs to the red and blue VIDEODACs may be a logical zero. If SYNC'" is always a logical zero, the relationship between RSET and the full scale output current is: lOUT (rnA) = 8,604 '" VREF (V) I RSET (n) Using Multiple Devices If located close together on the same PC board, multiple Bt106 devices may be connected to a single analog power and ground plane. In addition, a single voltage reference may be used to drive multiple devices. Each Btl06 must still have its individual RSET resistor, lOUT termination resistor (Rl in Figure 3), power supply bypass capacitors (C2 and C3 in Figure 3), and CaMP resistor and capacitor (C4 and R2 in Figure 3). At high clock rates, individual ground beads (L2 in Figure 3) may be required to maintain TIL thresholds due to high current return. Non-Video Applications The Btl06 may be used in non-video applications by disabling the video-specific control inputs. SYNC'" and REF WHITE should be a logical zero and BLANK'" should be a logical one. The relationship between RSET and the full-scale output current (lout) in this configuration is as follows: RSET (n) = 7,958 '" VREF (V) I lOUT (rnA) With the data inputs at $00, there is a DC offset current (Imin) defined as follows: *(fc = Clock Frequency) 5 - 54 SECTION 5 Imin (rnA) =650 ... VREF (V) I RSET (n) Therefore, the total full-scale output current will be lout + Imin. The REF WIDTE input may optionally be used as a "force to full scale" control. COMP Resistor To optimize the settling time of the Btl06, a resistor may be added in series between the CaMP capacitor and CaMP pin. The series resistor damps inductive ringing on CaMP, thus improving settling time. The value of the resistor is typically 12 n; however, the exact value is dependent on the PC board layout, clock rate, etc., and should be optimized for minimal settling time. An incorrect resistor value will result in degraded output performance, such as excessive ringing of the analog outputs or increased settling time. Analog Output Protection The Btl06 analog output should be protected against high-energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figure 3 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 are low capacitance, fast switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7001). ESD and Latchup Considerations Correct ESD sensitive handling procedures are required to prevent device damage which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay V AA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. Btl06 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Btl06KC30 Btl06BC OulpUtLoad Reference Voltage FS ADJUST Resistor Symbol Min Typ Max Units VAA TA 4.75 5.00 5.25 Volts +70 +85 ·C ·C Ohms Volts Ohms 0 -25 RL VREF 1.14 37.5 1.20 542 1.26 Min Typ Max Units 7.0 Volts VAA+0.5 Volts TJ +125 +150 +175 ·C ·C ·C TSOL 260 ·C RSEf Absolute Maximum Ratings Parameter Symbol VAA (measured to AGND) AG~.5 Voltage on Any Signal Pin* Analog Output Short Circuit Duration to Any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, 1/4" from pin) ISC TA 'IS .. indefinite -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. VIDEODACs 5·55 Btl06 DC Characteristics Parameter Resolution Accuracy Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Digital Inputs Input High Voltage Input Low Voltage Input High Current (Vin =2.4 V) Input Low Current (Vin =0.4 V) Input Capacitance (f =1 MHz, Yin =2.4 V) Analog Output Gray Scale Current Range Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Blank Level Sync Level LSB Size Output Compliance Output Impedance Output Capacitance (f =1 MHz, lOUT =0 rnA) Power Supply Rejection Ratio (COMP =0,01 J.IF, f =1 KHz) Symbol Min Typ Max Units 8 8 8 Bits ±1 ±1 LSB LSB % Gray Sca1e IL II. ±5 guaranteed Binary VlH VIL IIH IlL 2.0 AGND-O.5 CIN VAA+0.5 0.8 1 -1 17.69 16.74 0.95 6.29 0 Vex:: ROUf 19.05 17.62 1.44 7.62 5 69.1 -1.0 cour 10 30 PSRR 0.2 JlA JlA pF 10 15 Volts Volts 20 rnA 20.40 18.50 1.90 8.96 50 rnA rnA rnA rnA +1.4 Volts kn pF 0.5 %/%l:NAA JlA JlA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 542 n, VREF = 1.200 V. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 5 - 56 SECTION 5 Btl06 AC Characteristics 30 MHz Devices 50 MHz Devices Parameter Symbol Min Typ Max Min Typ Max Units 30 MHz Clock Rate Fmax Data and Control Setup Time Data and Control Hold Time 1'5U 18 8 2 8 2 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time TCYC TClKH TClKL 20 8 8 33.3 10 10 ns ns ns Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time* Clock and Data Feedthrough* Glitch Impulse* Differential Gain Error Differential Phase Error IDLY 25 -33 50 1.8 1.2 1.8 1.2 % Gray Scale Degrees 25 9 8 ro DP 1 1M 20 -33 50 ns ns ns dB pV - sec 25 TVRF 1'5 Pipeline Delay VAA Supply Current** 50 1 1 80 100 1 1 1 Clock 60 75 rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 542 n, VREF = 1.200 V. TTL input values are 0-3 V, with input rise/fall times s 4 ns, measured between the 10% and 90% points. COMP resistor = 12 n. Timing reference points at 50% for inputs and outputs. Analog output load S 10 pF. See timing notes in Figure 4. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Clock and data feedthrough is a function of the amount of edge rates, overshoot. and undershoot on the digital inputs. For this test, the digital inputs have a 1 ill resistor to the regular PCB ground plane and are driven by 74HC logic. Settling time does not include clock and data feed through. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 2x clock rate. **AtFmax. IAA (typ) at VAA= 5.0 V. IAA (max) at VAA =5.25 V. VIDEODACs 5 - 57 .. Btl06 Ordering Information Model Number Speed Package Ambient Temperature Range Btl06BC 50 MHz 20-pin 0.3" _25° to +85° C CERDIP Bt106KC30 30 MHz 20-pin 0.3" 0° to +70° C CERDIP Bt106EVM Evaluation Board for the Bt106 Timing Waveforms CLOCK DO-D7. SYNC". BLANK·. REP WHrfB lOUT Note 1: Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Note 2: Settling time measured from the 50% point of full-scale transition to the output remaining within ±1 LSB. Note 3: Output rise/fall time measured between the 10% and 90% points of full-scale transition. Figure 4. 5 - 58 SECTION 5 Input/Output Timing. Btl06 Device Circuit Data Equivalent Circuit of the Digital Inputs. r -_ _. . - - - - - -.....--~- VAA .. ">--#-_TODAC FS ADJUST IFEl!DBACIt L....--e----4o---+-- AGND Equivalent Circuit of the Reference Amplifier. BtlO6 VAA DO-D7 lOUT SYNC" BLANK" T- 30 P' RL C(11ray + lood) Equivalent Circuit of the Current Output. VIDEODACs S • S9 Preliminary Information This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. Distinguishing Features • • • • • Applications 400 MHz Pipelined Operation ± 1/2 LSB Differential Linearity Error ±1/2 LSB Integral Linearity Error 500 ps Typical Rise/Fall Time RS-343A-Compatible Output 0 or 7.5 IRE Blanking Pedestal Handles 25-0hm Output Loads 10KH and lOOK ECL-Compatible I/O 2:1 Multiplexed Pixel Inputs 32-pin Flatpack Package Typical Power Dissipation: 1 W • • • • High-Resolution Color Graphics CAE/CAD/CAM Applications Radar Processing Instrumentation D1V2IN 400 MHz 10KH/IOOK ECL 8-bit Multiplexed Input VIDEODAC™ Related Products Product Description • Bt424 The Bt107 is an 8-bit VIDEODAC, designed specifically for high-performance, highresolution color graphics. Multiplexed pixel inputs enable pixel data to be latched into the Btl07 at a 200 MHz data rate, while maintaining the 400 MHz output rate necessary for high-resolution graphics. On-chip circuitry divides the pixel clock by two, generating the 200 MHz clock signal. Functional Block Diagram FSADJUST Btl07 VREFIN VREFOlTf An on-chip voltage reference is available or an external reference may be used. A single external resistor controls the full-scale output current. -+--/ D FUP FLOP D1V20UT" The Btl07 generates an RS-343A compatible video signal, and is capable of driving either doubly terminated 75 Q or 50 Q coax directly, without requiring external buffering. Both the differential and integral linearity errors of the D/A converter are guaranteed to be a maximum of ±I/2 LSB over the full temperature range. --+--..-1 Q" CLOCK CLOCK" B DAO • DA7 -+--7'-'------1 lOur REG 8 AND DBO - DB7 -+--7'-'--_~ MUX BLANK DAC r--+-- -+---_--1 VAA AGND Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 Ll07001 Rev. D SBTUP 5 • 61 IOUI"' 5 Btl07 Circuit Description Both sides of the differential corrent outputs should have the same output load. A single-ended video signal may be generated by connecting the lOUT output through a 25 n resistor to AGND (assuming a doubly terminated 50 n load). The IOUT* output is used to generate the video signal. As illustrated in the functional block diagram, the Btl07 contains a single 8-bit D/A converter, 2:1 multiplexed input register, a voltage reference, and a reference amplifier. Pixel data on the DAO-DA7 (even data) and DBO- DB7 (odd data) are latched on the falling edge of DIV20UT*, as illustrated in Figure 1. The D/A converter on the Bt107 uses a segmented architecture in which bit corrents are routed to either lOUT or IOUT* by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and corrent steering their outputs. An on-chip operational amplifier stabilizes the full-scale output current against temperature and power supply variations. DIV2IN is defmed to be 1/2 the CLOCK rate. To simplify system design, the Btl07 outputs a DIV20UT* signal which, when connected to the DIV2IN pin, generates a clock equal to 1/2 the CLOCK rate. For a color system requiring three Bt107s, the DIV20UT* signals may be synchronized by connecting the DIV20UT* signal on one of the devices to the DIV21N pins of all three devices. Care should be taken to keep signal paths short and equal for each connection. The unused DIV20UT* signals from the remaining BtI07s can be used to clock external lookup table RAMs. The analog outputs of the Bt107 are capable of directly driving either a 37.5 n or 25 n load, such as a doubly terminated 75 n or 50 n coaxial cable. The BLANK input is also latched on the falling edge of DIV20UT*, and overrides the DAO-DA7 and DBO-DB7 data. Blanking information is output synchronously with the even pixel data. Full scale output current is set by an external resistor (RSEr) between the FS ADJUST pin and AGND. RSET has a typical value of 1092 n for generation of RS-343A video into a 37.5 n load, or 729 n for generation of RS-343A video into a 25 n load. The on-chip voltage reference (VREF OUT) may be used to provide the reference for the VREF IN pins of up to three Bt107s, or an external reference may be used. DAO.DA7. DBO.DB7. BLANK ==x'--____ ..JXI...__D_Ii._T_A_--'X'--_ _ _ _..JXI..._ __ ~ D!!l:!>.!7. {'v'- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'/D~~7. ~ Figure 1. 5 - 62 Input/Output Timing (DIV2IN connected to DIV20UT*). SECTION 5 Btl07 Circuit Description (continued) v MA MA RSBT= 7:19 RSET= 1002 00.00 00.00 0.000 • 26.40 - 17.60 - 0.660 WIIlI1! LEVEL BLACK LEVEL 7.S IRE - 28.56 • 19.05 ·0.714 BLANK LEVEL Note: RSET = 729 0 (50 0 doubly tenninated load) or 1092 0 (75 0 doubly terminated load), VREF IN = -1.21 V. RS-343A levels and tolerances assumed on all levels. Figure 2. .. Composite Video Output Waveform (lOUT"') . Description WHITE DATA BLACK BLANK SETUP = AGND SETUP = float RSET= 7290 RSET= 10920 lOur· IOUf* (rnA) (rnA) 0 data -26.40 data -17.62 -26.40 -28.56 -17.62 -19.05 0 BLANK DAC Input Data 0 0 0 1 $FF data $00 $xx Note: Typical with VREF IN = -1.21 V. Table I. Video Output Truth Table. VIDEODACs 5 - 63 Btl07 Pin Descriptions Pin Name Description BlANK Composite blank control input (ECL compatible). A logic one drives the analog output to the blanking level, as iIIustrated in Table 1. It is latched on the falling edge of DIV20UT*. When BLANK is a logical one, the DAO-DA7 and DBO-DB7 inputs are ignored. Blanking information is output synchronously with the even pixel data. DAO-DA7, DBO-DB7 Even and odd pixel data inputs (ECL compatible). DO is the least significant data bit. They are latched on the faIling edge of DIV20UT*. Even data represents the first (leftmost) pixel on the display screen. DAx represent the even pixel data, and DBx represent the odd pixel data. Coding is binary. CLOCK, CLOCK'" Differential clock inputs (ECL compatible). It is typicaIly the pixel clock rate of the video system. The BtI07 may be operated with a single-ended clock by connecting CLOCK* to a -1.3 V YBB; however, common mode noise immunity at high clock rates may degrade. DIV21N CLOCK/2 input (ECL compatible). This clock must be 1/2 the CLOCK rate. It is used to latch the BLANK, DAx, and DBx inputs. See Figure 1. DIV20UI'* CLOCK/2 output (ECL compatible). When connected to the DIV2IN pin, this output is 1/2 the CLOCK rate. When not connected to DIV2IN, it generates a signal that is DIV2IN synchronized to CLOCK and inverted. DIV20UT* must be terminated to -2 V. lOUT, lOUT'" Differential video current outputs. These high impedance current sources are capable of directly driving either a doubly terminated 50 n or 75 n coaxial cable (Figure 3). Both outputs, whether used or not, should have the same output load. AGND Analog ground. AIl AGND pins must be connected. VM Analog power. AIl VAA pins must be connected. Warning: It is important that a ferrite bead be used to connect the VAA(l) power pin to the analog power plane as lIIustrated in Figure 3. Connecting the decoupling capacitors directly to the V AA(l) pin wlII result in unstable operation. COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.01 IlF ceramic chip capacitor and a 0.001 ceramic chip capacitor must be connected between this pin and VAA(O) (Figure 3). Connecting the capacitors to VAA rather than to AGND provides the highest possible power supply noise rejection. The COMP capacitors must be as close to the device as possible to keep lead lengths to an absolute minimum. SEIUP Pedestal control input. If connected to AGND, the blanking pedestal on the output is disabled, making the black and blanking levels the same (0 IRE). If left floating, the 7.5 IRE blanking pedestal is enabled. See Figure 2. S • 64 SECTION S Btl07 Pin Descriptions (continued) Pin Name Description FSADJUST Full-scale adjust control. A resistor (RSET) cOImected between this pin and AGND controls the magnitude of the full-scale video signal (Figure 3). Note that the IRE relationships in Figure 2 are maintained. regardless of the full-scale output current. The relationship between RSET and the full-scale output current is: RSET (0) = K .. VREF IN (V) I lOUT (rnA) where K = 17.205 if SETUP = float or 15.915 if SETUP = AGND. Note: The RSET value may need to be adjusted to generate the specified video levels due to variations in processing and depending on whether the internal or an external reference is used. VREFOUT Voltage reference output. This output provides a -1.2 V (typical) reference. and may be connected to the VREF IN inputs of up to three Bt107s. When driving multiple Bt107s. use lOO o interconnect resistance to minimize noise pick-up. If it is not used to provide a voltage reference. it should remain floating. VREFIN Voltage reference input. An external voltage reference. such as the one shown in Figure 4. or the VREF OUT pin must supply this input with a -1.2 V (typical) reference. A 0.01 I1F ceramic chip capacitor in parallel with a 0.001 I1F ceramic chip capacitor must be connected between this pin and VAA(O). as shown in Figure 3. The decoupling capacitors must be as close to the device as possible to keep lead lengths to an absolute minimum. l!! Q ~ Q ~ ~ ~ § § ~< &l ~ Q Q > - - ~ ~ lQ ~ !:j " DAS 29 211 COMP DBS 30 19 FSADJUST DA4 31 18 VREFIN DB4 3Z 11 VREFOUT DA3 16 SBTIJP DB3 15 VAA(I) DA2 14 DlV20llT' 13 AGND DB2 ~ <.0- t"'- 00 : - '0 '0 ;:). ..... ~ o· ....= ODD PIXELS MPU ADDRESS BUS (TIL) CLOCK I ~ I-'-'-~'~ ">l ciii' $:: :I::~: I :: I • ... :-~ = 0., 9 ~ a.OCK' lOR lOR· I DIV2IN = ~ Q. DIV2IN ()q E:: DAO-DA7 ::;:- DBO-DB7 $:: - ~. 100 Btl 07 100' DIV2OUT' ~ =r= so b:l ::. ...................-..........-.....................-................................1 / I DIV2IN lOB - + - - - - - 1 DAO-DA7 i--: DBO-DB7 DIV20UT' trl 0 Btl07 10B* ! t:::l > ~ '" = ..... = :i' 0 '-' <:::: -< .... t:::l O· ,-.. rl Bt107 -w '"ii' ~ <8 ..... so ~ !i .••.••••••••••••••••••••••••••••••••••••••••••••• n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPUDATA BUS (TIL) .1 CLOCK'/2 ,/ c= ..... = ~ !II 0'1 ....:J ~ I Btl07 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage FS ADJUST Resistor Symbol Min Typ Max Units VAA TA RL VREFIN RSET -4.2 -25 -5.2 -5.5 +85 Volts °C Ohms Volts Ohms -1.13 25 -1.2 -1.3 729 Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. Absolute Maximum Ratings Parameter VAA (measured to AGND) Symbol Min VAA Voltage on Any Digital Pin AGND+05 Analog Output Short Circuit Duration to Any Common Ambient Operating Temperature Storage Temperature Junction Temperature Vapor Phase Soldering (1 minute) Typ Max Units -6.5 Volts VAA-O.5 Volts +125 +150 +175 °C °C °C 220 °C indefinite TA TS TJ TVSOL -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5·70 SECTION 5 Btl07 DC Characteristics Parameter Resolution Accuracy Integral Linearity Error Differential Linearity Error Gray Scale Error Using Internal Reference Using External Reference Monotonicity Coding Digital Inputs Input High Voltage Input Low Voltage Input High Current (Vin = VIHmax) Data All Other Inputs Input Low Current (Vin = VILmin) Blank All Other Inputs Input Capacitance (f = 1 MHz, Yin = VIHmax) Digital Output Output High Voltage Output Low Voltage Analog Output Gray Scale Current Range Output Current White Level Black Level Relative to White Blank Level Relative to Black SETUP=AGND SETUP = float LSB Size Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 rnA) Reference Input Current Reference Output Voltage Reference Output Current Power Supply Rejection Ratio (COMP = 0.001 JlF II 0.01 JlF, f= 1 kHz) Symbol Min Typ Max Units 8 8 8 Bits ±1/2 ±l/2 LSB LSB ±10 ±5 % GrayScale % Gray Scale 1L II... guaranteed Binary V1H VIL I1H -1160 -1870 -710 -1480 mV mV 30 150 ~ ~ 150 5 10 ~ ~ pF -880 -1620 mV mV -40 rnA IlL ClN VOH VOL VOC ROUT COUT IREFIN VREFOUT IREFOUT PSRR -1060 -1810 -955 -1705 ~ 0 -25.08 -5 -26.40 -50 -27.72 rnA 0 -2.05 0 -2.16 -103.5 0 -2.28 rnA rnA +1.5 Volts Kohms pF -1.2 ~ 10 9 -1.14 -200 -1.22 10 -1.3 ~ Volts ~ 0.03 0.5 %/%tJ.VAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET adjusted for -28.56 rnA full-scale output current, VREF IN = -1.21 V, SETUP = float. All digital inputs have 50 n to -2.0 V. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. VIDEODACs 5 - 71 Btl07 AC Characteristics Parameter Clock Rate Symbol Min Typ Fmax Data and Control Setup Time Data and Control Hold Time Clock Cycle Time Clock Pulse Width High Clock Pulse Width Low Units 400 MHz TSU TIl 1 0 ns ns TCYC 2.5 1 1 ns ns ns TCLKH TClKL DIV20UT Delay*** DIV2IN Setup Time DIV2IN Hold Time DDLY DSU Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time Clock and Data Feedthrough* Glitch Impulse* Non-Harmonic Spurious IDLY TVRF TS m 1.5 0 1 350 2.2 ns ns ns 2 700 2 ns ps ns dB LSB -ns dBc 2 Clocks 225 rnA tbd 10 -45 Pipeline Delay 2 VAA Supply Current** Max IAA 2 Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET adjusted for -28.56 mA full scale output current, VREF IN = -.21 V SETUP = float. ECL input values are -0.95 to -1.69 V, with input rise/fall times $ 1 ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. All digital inputs have 50 Q to -2.0 V, unless otherwise specified. Analog output load $ 10 pF. See timing notes in Figure 6. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 800 MHz. **At Fmax. IAA (typ) at VAA = -4.5 V. IAA (max) at VAA = -5.5 V. ***Tested with one ECL load. 5 • 72 SECTION 5 Btl07 Ordering Information Model Number Speed Package Btl07BF400 400 MHz 32-pin Ceramic Flatpack w/heatsink Ambient Temperature Range _25 0 to +85 0 C Timing Waveforms - DlV2IN. DlV20ur' DAO • DA7. DBO· DB7. BLANK CLOCK lOur" IDLY Note 1: Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Note 2: Settling time measured from the 50% point of full-scale transition to the output remaining within ±1f2 LSB. Note 3: Output rise/fall time measured between the 10% and 90% points of full-scale transition. Figure 6. Input/Output Timing (DIV2IN connected to DIV20UT*). VIDEODACs 5 • 73 Btl07 Device Circuit Data Btl07 BLANK DO-D7 -2-SnH IOUT,IOUT' RL C(stray + load) VAA The output network of the Btl07 may be modeled as a three-pole low-pass filter. Settling time is tested on a sample basis with C(stray + load) tuned for optimum performance. Equivalent Output Circuit of the Btl 07. VREPIN >--H---TODAC FSADJUST IFEIlDBACK Equivalent Circuit of the Reference Amplifier. 5 - 74 SECTION 5 Btl09 Applications Distinguishing Features • • • • • • • • • • • High-Resolution Color Graphics 250 MHz Pipelined Operation Triple 8-bit D/A Converters ±1/2 LSB Differential Linearity Error ±1/2 LSB Integral Linearity Error 350 ps Typical Rise/Fall Time RS-343A-Compatible Outputs 10KH ECL-Compatible Inputs 40-pin DIP Package Pin Compatible with TDC1318 Typical Power Dissipation: 2 W • CAE/CADICAM • Image Processing • Video Reconstruction • Instrumentation Product Description Related Products The Btl09 is a triple 8-bit VIDEODAC, designed specifically for high-performance, resolution color graphics. • Bt424 An internal 1.2 V voltage reference and a single external resistor control the full-scale output current. FSADJUST VOLTAGB RBFBRBNCB 8 """,=:---+_~IOR RO-R7 ~---+-_~IOR· R 8 8 BO·B7 SYNC E ~--+-_"IOG G 00-G7 ~~--+~_IOG· I S ~--+_~IOB T E ~----+-"""IOB· R BLANK OVERlAY VAA Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580 • (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 Ll09001 Rev. G high- Available control inputs include sync, blank, and overlay, all registered to maintain synchronization with the pixel data. Functional Block Diagram CLOCK 250 MHz 10KH ECL Triple 8-bit VIDEODAC™ AGND S - 7S The Btl09 generates RS-343A compatible red, green, and blue video signals, and is capable of driving doubly terminated 75 n coax directly, without requiring external buffering. Both the differential and integral linearity errors of the 0/A converters are guaranteed to be a maximum of ±l/2 LSB over the full temperature range. Btl09 Circuit Description As illustrated in the functional block diagram, the Btl09 contains three 8-bit D/A converters, input registers, a voltage reference, and a reference amplifier . On the rising edge of each clock cycle, as shown below in Figure 1, 24 bits of color information (RO-R7, 00--07, and BO-B7) are latched into the device and presented to the three 8-bit D/A converters. The OVERLAY input, also latched on the rising edge of CLOCK, forces the analog outputs to the overlay level, regardless of the data inputs. This also permits blanking of the lOUT" outputs for analog summing. Latched on the rising edge of CLOCK to maintain synchronization with the color data, the SYNC and BLANK inputs add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figure 2. Table 1 details how the SYNC, BLANK, and OVERLAY inputs modify the output levels. Both sides of the differential current outputs should have the same output load. A single-ended video signal may be generated by connecting the lOR, 100, and lOB outputs through 37.5 n resistors to AOND (assuming lOR·, 100*, and 10B* are driving a doubly terminated 75 n load). The 10R*, 100", and lOB'" outputs are then used to generate the video signals. The D/A converters on the Btl09 use a segmented architecture in which bit currents are routed to either lOUT or IOUT* by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabilizes the full-scale output current against temperature and power supply variations. The analog outputs of the Btl09 are capable of directly driving a doubly terminated 75 n coaxial cable or a singly terminated 50 n coaxial cable. The full-scale output current is set by an external resistor (RSET) between the FS ADJUST pin and AOND. RSET has a typical value of 1100 n for generation of RS-343A video into a 37.5 n load. RO·R7. 00·07. BO·B7. DATA SYNC. BLANK, OVERLAY lOR". 100". lOB' Figure 1. 5 - 76 SECTION 5 Input/Output Timing. Btl09 Circuit Description (continued) V MA -r:-:==-....--------------:;;::---- OVBRLAY LIlVEL 0.000 0.00 -1.90 -0.D71 -t---::f-~----------~~~~-wmmLllVEL -19.5 -0.731 -t-------t----+--------- -20.9 -0.714 -t-----~-~_T-~-------- n~~ -28.6 -1.071 _..1..-_ _ _ _ _ _............6_ _ _ _ _ _ _ _ _ _ BLACK LIlVEL 401RB Note: 75 levels. n doubly terminated load, RSET = 1100 Figure 2. Description OVERlAY WHITE DATA BlACK BLANK SYNC n. SYNC LIlVEL (GREllNONLy) RS-343A levels and tolerances assumed on all Composite Video Output Waveforms. 100* (rnA) lOR"', lOB'" (rnA) OVERlAY SYNC BlANK DAC Input Data 0 -1.90 data-1.90 -19.50 -20.90 -28.60 0 -1.90 data-1.90 -19.50 -20.90 -20.90 1 0 0 0 x x 0 0 0 0 0 1 0 0 0 0 1 1 $xx $FF data $00 $xx $xx Note: Typical with full-scale 100'" =-8.60 rnA. RSET = 1100 n. Note that SYNC does not override data, as with the TDC1318. Table 1. Video Output Truth Table. VIDEODACs 5 - 77 Btl09 Pin Descriptions Pin Name Description BLANK Composite blank control input (EeL compatible). A logical one on this input drives the analog outputs to the blanking level, as illustrated in Table 1. It is latched on the rising edge of CLOCK. When BLANK is a logical one, the data and OVERLAY inputs are ignored. SYNC Composite sync control input (EeL compatible). A logical one on this input switches on a 40 IRE current source on the green output (see Figure 2). SYNC does not override any other control or data input, as shown in Table 1; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. OVERLAY Overlay control input (ECL compatible). A logical one on this input overrides the data inputs and forces the analog outputs to the overlay level. It is latched on the rising edge of CLOCK. RO-R7, Red, green, and blue data inputs (EeL compatible). RO, GO, and BO are the least significant data bits. They are latched on the rising edge of CLOCK. Coding is binary. 00-07, BO-B7 CLOCK Clock input (ECL compatible). The rising edge of CLOCK latches the RO-R7, 00-07, BO-B7, SYNC, BLANK, and OVERLAY inputs. It is typically the pixel clock rate of the video system. lOR, lOG, lOB, IOR*, 100*, IOB* Red, green, and blue differential video current outputs. These high-impedance current sources are coaxial cable (Figure 3). All outputs, capable of directly driving a doubly terminated 75 whether used or not, should have the same output load. AGND Analog ground. All AOND pins must be connected. VM Analog power. All V AA pins must be connected. n Warning: It is Important that a ferrite bead be used to connect the VAA(l) power pin to the analog power plane as HIustrated In Figure 3. Connecting the decoupUng capacitors directly to the V AA(l) pin will result in unstable operation. COMP 5 - 78 Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.01 ~F ceramic chip capacitor and a 0.001 ceramic chip capacitor must be connected between this pin and V AA(O) (Figure 3). Connecting the capacitors to V AA rather than to AOND provides the highest possible power supply noise rejection. The CaMP capacitors must be as close to the device as possible to keep lead lengths to an absolute minimum. SECTION 5 Btl09 Pin Descriptions (continued) Pin Name Description FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and AGND controls the magnitude of the full-scale video signal (Figure 3). Note that the IRE relationships in Figure 2 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on lOG· is: RSET (n) = 31,460 flOG (rnA) The full-scale output current on lOR* and lOB· for a given RSET is dermed as: lOR, lOB (rnA) = 22,990 f RSET (n) Note: The RSET value may need to be adjusted to generate the specified video levels due to variations in processing. VAA(rJ) VAA(I) PSADJUST BO COMP BI BLANK B2 OVBRLAY B3 lOB B4 lOB· BS lOR B6 lOR- B7 lOG RO lOGO RI SYNC R2 CLOCK R3 07 R4 G6 RS os R6 G4 R7 G3 GO 02 Gl AOND AGND VIDEODACs 5 - 79 Btl09 PC Board Layout Considerations PC Board Considerations Supply Decoupling The layout should be optimized for lowest noise on the Btl09 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and AGND pins should be as short as possible to minimize inductive ringing. In addition to the ferrite beads between the analog and regular PCB power and ground planes. an additional ferrite bead must be installed between the VAA(l) power pin and the analog power plane. as illustrated in Figure 3. The ferrite bead must be located as close as possible to the VAA( 1) pin. Ground Planes For the best performance. three chip capacitors in parallel (0.1 I1F. 0.01 I1F. and 0.001 I1F) should be placed as close as possible to each power pin for power supply bypassing. These capacitors should be connected on the analog power plane side of the ferrite bead for the VAA(l) pin as illustrated in Figure 3. Connecting the bypass capacitors directly to the VAA(1) pin will result in unstable operation due to high-frequency oscillations. The Btl09 and any associated analog circuitry should have its own ground plane, referred to as the analog ground plane. This ground plane should connect to the regular PCB ground plane at a single point through a ferrite bead. as illustrated in Figure 3. This bead should be located within 3 inches of the Btl09. The analog ground plane area should encompass all Bt109 ground pins. power supply bypass circuitry for the Bt109. the analog output traces. and any output amplifiers. The regular PCB ground plane area should encompass all the digital signal traces. excluding the ground pins. leading up to the Btl 09. Power Planes The Bt109 and any associated analog circuitry should have its own power plane. referred to as the analog power plane. This power plane should be connected to the regular PCB power plane at a single point through a ferrite bead. as illustrated in Figure 3. This bead should be located within 3 inches of the Bt109. The PCB power plane should provide power to all digital logic on the PC board. and the analog power plane should provide power to all Bt109 power pins and any output amplifiers. It is important that portions of the regular PCB power and ground planes do not overlay portions of the analog power or ground planes. unless they can be arranged so that the plane-to-plane noise is common mode. This will reduce plane-to-plane noise coupling. If a switching power supply is used. the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane. Digital Signal Interconnect The digital inputs to the Bt109 should be isolated as much as possible from the analog outputs and other analog circuitry. Also. these input signals should not overlay the analog ground and power planes. Stripline or microstrip techniques should be used for the ECL interfacing. In addition, all ECL inputs should be terminated as closely as possible to the device to reduce ringing. crosstalk, and reflections. Any termination resistors for the digital inputs should be connected to the regular PCB power and ground planes. Analog Signal Interconnect The video output signals should overlay the analog ground plane. and not the analog power plane. to maximize the high-frequency power supply rejection. It is important that the analog transmission lines have matched impedance throughout. including connectors and transitions between printed circuitry wiring and coaxial cable. 5 - 80 SECTION 5 Btl09 PC Board Layout Considerations (continued) ANALOG POWER PLANB L1 BtlO9 ·S.lV + CIO C1 1.2 GROUND RII·R6 FSADJUST lOR, 100. lOB TO VIDEO IOR·.]()GA'.IOB· CONNBCTOR Location Description Cl C2,C3 C4-C6 C7-C9 CI0 Ll, L2, L3 Rl, R2, R3 R4, RS, R6 RSEr 0.1 I1F ceramic capacitor 0.1 I1F ceramic chip capacitor 0.01 I1F ceramic chip capacitor 0.001 I1F ceramic chip capacitor 10 I1F tantalum capacitor ferrite bead 37.4 n 1% metal film resistor 7S n 1% metal film resistor 1100 n 1% metal fIlm resistor Vendor Part Number Erie RPEl12Z5U104M50V Johanson Dielectrics X7R-SOOS41WI04KP Johanson Dielectrics X7R-SOOS41WI03KP Johanson Dielectrics NPO-SOOS41NI02JP Mallory CSR13G106KM Fair-Rite 2743001111 Dale CMF-SSC Dale CMF-SSC Dale CMF-SSC Note: The vendor numbers above are listed only as a guide. characteristics will not affect the performance of the Btl 09. Figure 3. Substitution of devices with similar Typical Connection Diagram and Parts List. VIDEODACs 5 - 81 Btl09 Application Information Terminated Inputs Non-Video Applications All digital inputs of the Btl09 should be terminated using nonnal EeL termination practices. In addition, all of the digital inputs have internal pull-down junctions. Thus, if a digital input is left floating, it assumes the logical zero state. The Btl09 may be used in non-video applications by disabling the video-specific control inputs. The SYNC, BLANK, and OVERLAY inputs should be a logical zero. All three outputs will have the same fullscale output current The relationship between RSET and the full-scale output current (lout) in this configuration is as follows: RSET (n) =19,360 I lout (rnA) With the data inputs at $00, there is a DC offset current (Imin) defmed as follows: Imin (rnA) = 2,090 I RSET (n) Therefore, the total full-scale output current will be lout + Imin. 5 - 82 SECTION 5 Btl09 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Output Load FS ADJUST Resistor* Symbol Min Typ Max Units VM TA -4.9 -5.2 -5.5 +70 Volts ·C 0 RL 37.5 1100 RSET n n *FS ADJUST set to 1.125 rnA Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. Absolute Maximum Ratings Parameter VM (measured to AGND) Symbol Min VM Voltage on Any Digital Pin AGND+0.5 Analog Output Short Circuit Duration to Any Common Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds. 1/4" from pin) Typ Max Units -6.5 Volts VAA-O.5 Volts +125 +150 +175 ·C ·C ·C 260 ·C. indefinite TA TS TJ -55 -65 TSOL Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VIDEODACs 5 • 83 Btl09 DC Characteristics Parameter Symbol TA("C) Min Input High Voltage VIH 0 +25 +70 Input Low Voltage VlL 0 +25 +70 Input High Current (Data, Sync) (Yin = VIHmax) IIH Input High Current (Overlay) (Vin = VIHmax, VILmin) Input High/Low Current (Blank) Max Units -1170 -1130 -1070 -840 -810 -735 mV mV mV -1950 -1950 -1950 -1480 -1480 -1450 mV mV mV 0 +25 +70 25 25 25 ~ ~ ~ IIH 0 +25 +70 210 210 210 ~ ~ ~ IIH/TIL 0 +25 +70 160 160 160 ~ ~ ~ llL 0 25 +70 5 5 5 ~ ~ ~ 20 7 pF pF (Vin = VIHmax, VILmin) Input Low Current (Data, Sync, Overlay) (Vin = VILmin) Input Capacitance (f = 1 MHz, Yin = VIHmax) BLANK All Others CIN Internal Voltage Reference VREF See test conditions on next page. 5 • 84 SECTION 5 Typ -1.2 Volts Btl09 DC Characteristics (continued) Parameter Resolution (each DAC) ACCID'acy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error Monotonicity Coding Analog Outputs Gray Scale Current Range: Black Level Relative to White Blank Level Relative to White Output Current Overlay Level White Level Black Level Relative to White Blank Level Relative to Black Blank Level Relative to White Sync Level Relative to Blank LSB Size DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 rnA) Power Supply Rejection Ratio (COMP = O.OOlIlF II 0.01 j.LF, f= 1 kHz) Symbol Min Typ Max Units 8 8 8 Bits ±1/2 ±1/2 ±10 LSB LSB % Gray Scale n. IL guaranteed Binary 0 -1.70 -15.86 -0.95 -16.81 -6.29 VOC ROur cour -5 -1.90 -17.62 -1.44 -19.05 -7.62 -69.1 2 -1.2 -20 -30 rnA rnA -50 -2.10 -19.38 -1.90 -21.28 -8.96 rnA rnA rnA rnA rnA J.IA 5 +1.5 % Volts ill pF 0.5 %/%t:NAA 10 9 PSRR J.IA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET adjusted for -17.62 rnA full-scale output current (no sync information). Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. Note: The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. VIDEODACs 5 ·85 Btl09 AC Characteristics Parameter Symbol Min Typ Clock Rate Max Units 250 MHz Data and Control Setup Time Data and Control Hold Time 2 1.5 0 ns ns Clock Cycle Time Clock Pulse Width High Clock Pulse Width Low 3 4 5 4 1.6 1.6 ns ns ns Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time Glitch Impulse 6 7 8 VAA Supply Current I IAA 0.5 4 50 3 1 ns ns ns pV - sec 400 rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET adjusted for -17.62 mA full-scale output current (no sync information). ECL input values are -0.89 to -1.69 V. with input rise/fall times S 2 ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. Analog output load S 10 pF. See timing notes in Figure 4. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 5 - 86 SECTION 5 Btl09 Ordering Information Ambient Temperature Range Model Number Speed Package Btl09KC 250 MHz 40-pin 0.6" Ceramic Cavity Down DIP O· to +70· C Timing Waveforms .. RO·R7. 00·07.80·87. SYNC. BLANK. OVERLAY lOR·, 100·, 10B* Note 1: Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Note 2: Settling time measured from the 50% point of full-scale transition to the output remaining within ±1/2 LSB. Note 3: Output rise/fall time measured between the 10% and 90% points of full-scale transition. Figure 4. Input/Output Timing. VIDEODACs 5·87 Advance Information This docwnent contains infonnation on a product under development. The parametric infonnation contains target parameters and is subject to change. Distinguishing Features Applications • 80, 50 MHz Operation • Triple 8-bit D/A Converters • Optional Internal Voltage Reference • On-Chip Analog Output Comparators • RS-343A Compatible Outputs • TIL-Compatible Inputs • +5 V CMOS Monolithic Construction • 44-pin PLCC Package • Typical Power Dissipation: 600 mW • • • • • High-Resolution Color Graphics CAE/CAD/CAM Image Processing Video Reconstruction Instrumentation Product Description The Bt121 is a triple 8-bit VIDEODAC, designed specifically for high-performance, high-resolution color graphics. Bt473 This device offers a higher level of integration than previous VIDEODAC designs. On-chip analog output comparators are included to simplify diagnostics and debugging, with the resultant output on the SENSE'" pin. Also included is an on-chip voltage reference to simplify using the device. Functional Block Diagram CLOCK -+-----.., FSADnJST >==r==--t-- COMP >-,-+_~IOR 8 -t-+-..-I 8 DO -B7 SYNC· BLANK· The Bt121 generates RS-343A compatible video load, and signals into a doubly terminated 75 RS-170 compatible video signals into a singly tenninated 75 load, without requiring external buffering. Both the differential and integral linearity errors of the D/A converters are guaranteed to be a maximwn of ±l LSB over the full temperature range. n n 8 RO·R7 -+-+-~ GO-G7 80 MHz Monolithic CMOS Triple 8-bit VIDEODAC™ Related Products • VREF Bt121 -+-+--.t -t----I -+----1 >r++-I-_~ lOB COMPARATOR VAA Brooktree Corporation 9950 Barnes Canyon Rd San Diego, CA 92121-2790 (619) 452-7580. (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 L121001 Rev. D SENSE AGND 5 -89 Bt121 Circuit Description As illustrated in the functional block diagram, the Bt121 contains three 8-bit D/A converters, input registers, and a reference amplifier. On the rising edge of CLOCK, 24 bits of color information (RO-R7, GO-G7, and BO-B7) are latched into the device and presented to the three 8-bit D/A converters. Latched on the rising edge of CLOCK to maintain synchronization with the color data, the SYNC* and BLANK* inputs add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications as illustrated in Figure 1. Table 1 details how the SYNC* and BLANK* inputs modify the output levels. The D/A converters on the Bt121 use a segmented architecture in which bit currents are routed to either the output or GND by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabilizes the full-scale output current against temperature and power supply variations. The analog outputs of the Bt121 are capable of directly driving a 37.5 n load, such as a doubly terminated 75 n coaxial cable. S -90 SECTIONS SENSE· Output SENSE* is a logical zero if one or more of the lOR, lOG, and lOB outputs have exceeded the internal voltage reference level (335 m V). This output is used to determine the presence of a CRT monitor and, via diagnostic code, the difference between a loaded or unloaded RGB line can be discerned. The 335 mV reference has a ±5% tolerance (when using an external 1.235 V voltage reference). The tolerance is ±10% when using the internal voltage reference. Note that SYNC* should be a logical zero for SENSE* to be stable. ESD and lAtchup Considerations Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupJing networks with large time constants, which could delay VAA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. Bt121 Circuit Description (continued) NO SYNC MA SYNC V MA V __ 19.05 0.714 26.ti1 1.000 -r-----.~---------------------- 1.44 0.054 9.05 0.340 ~------------+-------~~----------------BUCKLE~ 0.00 0.000 7.62 0.286 -+------------.....-,--T""~------------------ ~------wrum~~ 7.S1RE BUNK ~VEL 40 IRE ~ 0.00 Note: 75 levels. 0.000 ______________ n doubly terminated load, RSET - ~ __ ~ ____________________ SYNCLE~ 143 n. VREF = 1.23 V. RS-343A levels and tolerances are assumed on all .. Figure 1. Composite Video Output Waveforms. Description lout (rnA) SYNC* BLANK* DAC Input Data WlllTE DATA DATA-SYNC BLACK BLACK-SYNC 26.67 data + 9.05 data + 1.44 9.05 1.44 7.62 0 1 1 0 1 0 1 0 1 1 1 1 1 0 0 $FF data data $00 $00 $xx $xx BLANK SYNC Note: 75 n doubly terminated load, SETUP = 7.5 IRE. VREF = 1.23 V, RSET - 143 n. Table 1. Video Output Truth Table. VIDEODACs 5·91 Bt121 Pin Descriptions Pin Name Description BLANK'" Composite blank control input (ITL compatible). A logical zero drives the lOR, lOG, and lOB outputs to the blanking level, as illustrated in Table 1. It is latched on the rising edge of CLOCK. When BLANK* is a logical zero, the RO-R7, G0-07, and BO-B7 inputs are ignored. SYNC· Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source on the lOR, lOG, lOB outputs (see Figure I). SYNC* does not override any other control or data input, as shown in Table I; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. RO-R7, G0-07, BO-B7 Red, green, and blue data inputs (TTL compatible). RO, GO, and BO are the least-significant data bits. They are latched on the rising edge of CLOCK. Coding is binary. CLOCK Clock input (ITL compatible). The rising edge of CLOCK latches the RO-R7, G0-07, BO-B7, SYNC"', and BLANK'" inputs. It is typically the pixel clock rate of the video system. It is recommended that the CLOCK input be driven by a dedicated TTL buffer to avoid reflection-induced jitter. lOR, lOG, lOB Red, green, and blue current outputs. These high-impedance current sources are capable of directly driving a doubly terminated 75 Q coaxial cable (Figures 2 and 3). An outputs, whether used or not, should have the same output load. SENSE· Sense output (CMOS compatible). SENSE· is a logical zero if one or more of the lOR, lOG, and lOB outputs have exceeded the internal voltage reference level (335 mY). Note that SENSE'" may not be stable while SYNC* is toggling. FSADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal (Figure 1). Note that the IRE relationships in Figure 1 are maintained, regardless of the fun-scale output current. The relationship between RSET and the fun-scale output current on lOR, lOG and lOB is: RSET (Q) = K '" VREF (V) 110 (rnA) Where; S ·92 SECTIONS K = 2,295 with SYNC"'=O K = 3,195 with SYNC*=1 BnxKtree® Btl21 Pin Descriptions (continued) Pin Name Description COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.01 I1F ceramic capacitor in series with a resistor should be connected between this pin and the nearest VAA pin (Figures 2 and 3) for optimum settling time. Connecting the capacitor to V AA rather than to GND provides the highest possible power supply noise rejection. The COMP resistor and capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. VREF Voltage reference input. IT an external voltage reference is used (Figure 3). it must supply this input with a 1.2 V (typical) reference. A 0.1 I1F ceramic capacitor must always be used to decouple this input to GND. as shown in Figures 2 and 3. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. When using the internal reference. this pin should not drive any external circuitry. except for the decoupling capacitor (Figure 2). GND Analog ground. All GND pins must be connected. VAA Analog power. All VAA pins must be connected. .. t; ..e e ..e ~ ~ ~ ~ ~ ~ ~ ~., ~ 0 ~ ~ :;; :!l ~ ~ i:l f;l ;:: lit ~ R7 28 GND R6 rI GND as 2fi BO R4 2S B1 R3 24 B2 R2 23 B3 R1 22 B4 RO 21 BS GND zo B6 GND 19 B7 SYNC· 18 CLOCK ... . '" §. S S ::: (Ij <:l C!i !::i !:l 8 ;!; :l" ~ !:i a6 8 ~ ~ VIDEODACs 5·93 Btl21 PC Board Layout Considerations PC Board Considerations Power Planes The layout should be optimized for lowest noise on the Bt121 power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of V AA and GND pins should be as short as possible to minimize inductive ringing. Separate digital and analog power planes are necessary. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt121 power pins, any reference circuitry, and COMP and reference decoupling. There should be at least a 1/8 inch gap between the digital power plane and the analog power plane. A well-designed power distribution network is critical to eliminating digital switching noise. Ground planes must provide a low-impedance return path for the digital circuits. A minimum of a four-layer PC board is recommended with layers 1 (top) and 4 (bottom) for signals and layers 2 and 3 for power and ground. The optimum layout enables the Bt121 to be located as close to the power supply connector and the video output connector as possible. The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figures 2 and 3. This bead should be located within 3 inches of the Bt121. The bead provides resistance to switching currents, acting as a resistance at high frequencies. A low-resistance bead should be used, such as Fair-Rite 2743001111, Ferroxcube 5659065-3B, or TDK BF454001. Ground Planes For optimum performance, a common digital and analog ground plane with tub isolation (at least a 1/8 inch gap) connected together only at the power supply connector (or the lowest impedance source) is recommended. Ground plane partitioning should extend the analog ground plane no more than 2 inches from the power supply connector. The digital ground plane should be under all digital signal traces to minimize radiated noise and crosstalk. The analog ground plane should include all Bt121 ground pins, all reference circuitry and decoupling (external reference if used, RSET resistors, etc.), power supply bypass circuitry for the Bt121, analog output traces, and the video output connector. Plane-to-plane noise coupling can be reduced by ensuring that portions of the digital power and ground planes do not overlay portions of the analog power and ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. Device Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Power Supply Decoupling Best power supply decoupling performance is obtained with a 0.1 IJ,F ceramic capacitor decoupJing each of the VAA pins to GND. For operation above 75 MHz, a 0.1 IJ,F capacitor in parallel with a O.OOlIJ,F chip capacitor is recommended. The capacitors should be placed as close as possible to the device. The 10 IJ,F capacitor is for low-frequency power supply ripple; the 0.1 IJ,F capacitors are for high-frequency power supply noise rejection. 5 ·94 SECTION 5 Btl21 PC Board Layout Considerations (continued) A linear regulator to filter the analog power supply is recommended if the power supply noise is ~ 50 mY. This is especially important when a switching power supply is used and the switching frequency is close to the raster scan frequency. Note that about 10% of the power supply hum and ripple noise less than 1 MHz will couple onto the analog outputs. COMP DecoupIing The COMP pin must be decoupled to V AA, typically using a 0.1 JlF ceramic capacitor. Low-frequency supply noise will require a larger value. Lead lengths should be minimized for best performance. Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge speeds (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals. Ensure that the power pins for the clock driver are properly decoupled to minimize transients. Minimize edge speeds and ringing, using damping resistors (10 to 50 Q) or parallel termination where necessary. If using parallel termination on digital signals, the resistors should be connected to the digital power and ground planes, not the analog power and ground planes. If the display has a "ghosting" problem, additional capacitance in parallel with the COMP capacitor may help to fix the problem. Analog Signal Interconnect Digital Signal Interconnect The Bt121 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The digital inputs to the Bt121 should be isolated from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power and ground planes. Most noise on the analog outputs will be caused by excessive edge speeds (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. The digital edge speeds should be no faster than necessary, as feedthrough noise is proportional to the digital edge speeds. Lower speed applications will benefit from using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission line mismatch will exist if the line length reflection time is greater than 1/4 the signal edge time, resulting in ringing, overshoot, and undershoot that can generate noise onto the analog outputs. Line termination or reducing the line length is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (10 to 50 Q). The video output signals should overlay the analog ground plane, not the analog power plane, to maximize the high-frequency power supply rejection. For maximum performance, the analog outputs should have a source load resistor equal to the destination termination (via a clean isolated ground return path). The load resistor connection between the current output and GND should be as close as possible to the Bt121 to minimize reflections. Unused analog outputs should be connected to GND. Analog edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce high-frequency energy, reducing EM! and noise reduction. Analog Output Protection The Bt121 analog outputs should be protected against high-energy discharges, such as those from monitor arc-over or from "hot-switching" AC-coupled monitors. The diode protection circuit shown in Figures 2 and 3 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The 1N4148/9 parts are low-capacitance, fast-switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7001). VIDEODACs 5 ·95 .. Btl21 PC Board Layout Considerations (continued) COMP ANALOG POWBRPLANB LI n...._,...__ +5V CI C6 Btl21 ~_~~_""_",,~,,,,~ RI R2 _ _ _ _ _ _" _ " " " "_____ ~OIDID R3 FSADJUST lOR I - - - -.......I---I--t----{ TO lOG 1--------1I---t----{ 1 0 B I - - -_ _ _ _ _ _- - - - { VIDEO CONNECTOR P VAA 0 IN4148/9 DAC TO MONITOR OIITPUT IN4148/9 AGNO Location Description Cl C2.C3.C5 C4 C6 Ll RI. R2. R3 R4 RSET 33 ~F tantalum capacitor 0.1 ~F ceramic capacitor 0.01 ~ ceramic capacitor 10 ~F capacitor ferrite bead 75 n 1% metal filID resistor 15 n 1% metal filID resistor 143 n 1% metal filID resistor Vendor Part Nwnber Mallory CSR13F336KM Erie RPEII2Z5UI04M50V Erie RPEll OZSUI 03M50V Mallory CSR13GI06KM Fair-Rite 2743001111 Dale CMF-55C Dale CMF-55C Dale CMF-55C Note: The vendor nwnbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the Bt121. Figure 2. Typical Connection Diagram and Parts List (Internal Reference). 5 -96 SECTION 5 Bt121 PC Board Layout Considerations (continued) COMP ANALOG POWER PLANE Ll ~_~ __ ~_~~_"~ _ _ _ _ _" + SV Cl C6 Zl BU21 L..oo..,.___ _ _ _ _" _ _ _ GROIDID R3 FSADJUST lOR I-------<~-I--+--__{ TO lOG 1---------<~--4--_{ VIDEO CONNECfOR I O B I - - - - - - - -......- - _ { p .. VAA lN4148/9 DAC OUIl'llT ---+--- TOMONITQR lN4148/9 AGND Location Description Cl C2,C3,C5 C4 C6 L1 Rl, R2, R3 R4 R5 RSET Zl 33 IlF tantalum capacitor O.lIlF ceramic capacitor O.OllJ.F ceramic capacitor 10 IlF capacitor ferrite bead 75 Q 1% metal mm resistor 1000 Q 5% metal film resistor 15 Q 1% metal film resistor 143 Q 1% metal ftlm resistor 1.2 V voltage reference Vendor Part Number Mallory CSR13F336KM Erie RPEll2Z5UI04M50V Erie RPEll0ZSUI03M50V Mallory CSRI3G106KM Fair-Rite 2743001111 Dale CMF-55C Dale CMF-55C Dale CMF-55C National Semiconductor LM385BZ-1.2 Note: The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the Bt121. Figure 3. Typical Connection Diagram and Parts List (External Reference), VIDEODACs 5· 97 Bt121 Recommended Operating Conditions Parameter Power Supply 80, 66 MHz Parts 50, 35 MHz Parts Ambient Operating Temperature Output Load External Reference Voltage FS ADmST Resistor Symbol Min Typ Max Units 4.75 4.5 0 5.00 5.00 5.25 5.5 +70 Volts Volts ·C Ohms Volts Ohms VAA TA RL VREF RSET 1.14 37.5 1.235 143 1.26 Min Typ Max Units 7.0 Volts VAA+O.5 Volts TJ +125 +150 +150 ·C ·C ·C TVSOL 220 ·C Absolute Maximum Ratings Parameter Symbol VAA (measured to GND) Voltage on Any Signal Pin* Analog Output Short Circuit Duration to Any Power Supply or Common Ambient Operating Temperature Sturage Temperature Junction Temperature Vapor Phase Soldering (1 minute) GND-0.5 indefinite ISC TA TS -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. >I< This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the absolute maximum ratings (especially relative to VAA or between V AA pins) can induce destructive latchup. S·98 SECTIONS Btl21 DC Characteristics Parameter Symbol Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray Scale Error External Reference Internal Reference Monotonicity Coding Analog Outputs Gray Scale Current Range Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Sync Level on lOR, lOG, lOB LSB Size DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (f = 1 MHz, lOUT = 0 rnA) Typ Max Units 8 8 8 Bits ±1 ±1 LSB LSB ±5 % Gray Scale % Gray Scale IL DL ±10 guaranteed Binary Digital Inputs Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Yin = 2.4 V) Digital Output (SENSE*) Output High Voltage (lOH = -400 J.1A) Output Low Voltage (lOL = 400 J.1A) Output Capacitance Min VIH VIL IIH TIL CIN 2.0 GND-O.5 VOH 2.4 Volts Volts J.1A J.1A pF VAA+O.5 0.8 1 -1 7 Volts VOL 0.4 Volts CDOUT 7 pF 20 rnA 20.40 18.50 1.90 7.94 rnA 17.69 16.74 0.95 6.29 VOC ROUT COUT Voltage Reference Input Current IVREF Power Supply Rejection Ratio* (COMP = om J.1F, f = 1 kHz) PSRR 19.05 17.62 1.44 7.62 69.72 2 0 rnA rnA rnA J.1A % Volts ill pF 5 +1.4 10 30 0.2 III 10 J.1A 0.5 %/%t:NAA Test conditions (unless otherwise specified): "Recommended Operating Conditions" using external voltage reference with RSET = 143 n, VREF = 1.235 V. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. Note: When using the internal voltage reference, RSET may need to be adjusted to meet these limits. *Guaranteed by characterization, not tested. VIDEODACs 5·99 Btl21 AC Characteristics 80 MHz Devices Parameter Clock Rate Symbol Min Typ Fmax 50 MHz Devices Max Min Typ 80 Max Units 50 MHz Data and Control Setup Time Data and Control Hold Time 1 2 3 3 3 3 ns ns Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time 3 4 5 12.5 4 4 20 7 7 ns ns ns Analog Output Delay Analog Output RiselFall Time Analog Output Settling Time Clock and Data Feedthrough* Glitch Impulse* DAC-to-DAC Crosstalk Analog Output Skew 6 7 8 Pipeline Delay 3 15.5 -30 75 -23 0 3 ns ns ns dB pV - sec dB ns 2 2 Clock 30 30 3 12.5 -30 75 -23 2 0 3 2 2 2 SENSE* Output Delay 9 1 1 ~ VAA Supply Current"" IAA tbd tbd rnA See test conditions on next page. Test conditions (unless otherwise specified): "Recommended Operating Conditions" using external voltage reference with RSET = 143 VREF = 1.235 V. TTL input values are 0-3 V, with input rise/fall times S 4 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load S 10 pF, SENSE· output load S 50 pF. See timing notes in Figure 4. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e.,5V. n. *Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the digital inputs have a 1 ill resistor to the regular PCB ground plane and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 2x clock rate. "*AtFmax. IAA(typ)atVAA=5.0V. IAA(max)atVAA=5.25V. S -100 SECTIONS Btl21 Ordering Information Ambient Temperature Range Model Number Speed Package Bt121KPJ80 80 MHz 44-pin Plastic J-Lead O· to +70· C Bt121KPJ50 50 MHz 44-pin Plastic J-Lead O· to +70· C Timing Waveforms .. RO-R7,OO·G7,BO-B7, SYNC·, BLANK· lOR, lOG, lOB ~ lOR, lOG, lOB 7 33SMV---: t- Note 1: Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Note 2: Settling time measured from the 50% point of full-scale transition to the output remaining within ±1 LSB. Note 3: Output rise/fall time measured between the 10% and 90% points of full-scale transition. Figure 4, Input/Output Timing, VIDEODACs 5 ·101 SECTION 6 ,--- PERIPHERALS ----, Contents Data Conversion Bt110 100 ns Monolithic CMOS Octal 8-bit D/A Converter 6-3 High Speed Lookup Tables Bt401 250 MHz lOKH ECL 256 x 8 Pipelined Static RAM 6 - 17 Bt403 250 Mhz lOKH ECL 256 x 8 Pipelined Static RAM 6 -17 High Speed Shift Registers Bt424 250 MHz 40-bit Multi-Tap Video Shift Register (10KH ECL/TTL) 6 -27 Cursor Generators Bt431 64 x 64 Pixel User-Definable Cursor, Cross Hair Cursor 6 - 39 Clock Generator Chips/or 80+ MHz CMOS RAMDACs Bt438 250 MHz Clock Generator Chip with Voltage Reference, + 3, 4, 5, or 8 for Load Generation (TTL compatible) 6 - 61 Bt439 200 MHz Clock Generator/Synchronizer Chip with Voltage Reference, + 3, 4, 5, or 8 for Load Generation (TTL compatible) 6 -73 Octal ECUTTL Transceivers/Translators Bt501 lOKH ECL/TTL Compatible 6 - 85 Bt502 lOOK ECLmL Compatible 6 - 85 Timing Verniers Bt604 Dynamically Programmed Timing Edge Vernier, 15 ps Resolution 6 -95 Bt605 Programmable Timing Edge Vernier, 15 ps Resolution 6 -109 ECL Compatible Adjustable Delay Lines Bt622 Very High Speed, lOKH ECL Compatible, Dual Channel Delay Line 6 - 123 Bt624 Very High Speed, lOKH ECL Compatible, Quad Channel Delay Line 6 - 123 6-2 Bt110 Distinguishing Features Applications Eight 8-bit DfA Converters • 100 ns Settling Time to ±l LSB • ±l LSB Differential Linearity Error ±1 LSB Integral Linearity Error Guaranteed Monotonic • Standard MPU Interface • +5 V CMOS Monolithic Construction • 44-pin PLCC Package • Typical Power Dissipation: 150 mW Instrumentation • Test Equipment • Waveform Synthesis • Data Acquisition Systems Product Description The BtllO is an octal 8-bit DfA converter. It provides eight independent DfA converters and has a standard MPU interface. The DfA converters are arranged in pairs, with each pair sharing a common reference amplifier. This provides excellent matching and stability of the paired DfA converters. Functional Block Diagram VREPIN VREPCOMP VREPOUT VAA An on-chip voltage reference is provided or an external reference may be used. Differential and integral linearity errors of the DfA converters are guaranteed to be a maximum of ±1 LSB over the full temperature range. AGND lOUTS lOUT! PSADruSTI FSADIUST4 COMP4 COMP! IOUr7 10= JQUf6 1OUf3 PSADJUST2 PSADJUST3 COMP3 COMP2 lOUTS IOUT4 DO-D7 Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 LlI0001 Rev. G 100 ns Monolithic CMOS Octal 8-bit D/A Converter cs· ~ WR*AO-A2 6 - 3 .. Btll0 Circuit Description As illustrated in the functional block diagram. the BtIlO contains eight 8-bit D/A converters. eight nontransparent (D-type) octal data registers. and MPU bus interface logic_ Also included on chip are four reference amplifiers and a voltage reference_ The on-chip voltage reference (VREF OUT) may be used to provide the reference voltage for the VREF IN pin or an external reference circuit may be used_ The on-chip reference should offer adequate performance for most applications_ The BtllO supports a conventional MPU bus interface through the use of the CS*. RD*. WR*. DO-D7. and AO-A2 pins_ AO-A2 specify which one of the eight internal data latches the MPU is accessing_ These data latches may be written to or read by the MPU at any time_ The input/output timing is illustrated in Figure 1. Better temperature stability may be attainable by using an external voltage reference. such as the LM385BZ-L2_ The use of a resistor network to generate the reference voltage is not recommended. as any low frequency power supply noise on VREF IN will be directly coupled onto the analog outputs_ The data contained in the data latches is presented to the associated D/A converter and used to specify the output current leveL The MPU may read these data latches to determine what data is present at each D/A converter_ The full-scale output current of each pair of D/A converters is set by an external resistor (RSET) between the FS ADJUST pin and AGND_ FS ADJUST! controls the full-scale output current of IOUTI and IOUT2. FS ADJUST2 controls the full-scale output current of IOUT3 and IOUT4. FS ADJUSTI controls the full-scale output current of IOUT5 and IOUT6. and FS ADJUST4 controls the full-scale output current of IOUT7 and IOUT8_ CS*, AO, AI, A2 =x / < DO - D7 (READ) DATA OIIT (RD' = 0) X DO - D7 (WRITE) DATAIN(WR'=O) > X _ _ _ _ _---Jt-Figure 1. 6 - 4 X VALID \ RD-, WR.. IOIIT(I- 8) The D/A converters on the BtllO use a segmented architecture in which bit currents are routed to either lOUT or AGND by a sophisticated decoding scheme_ This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off_ Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs _ The on-chip operational amplifiers stabilize the full-scale output currents against temperature and power supply v~iations_ SECTION 6 Input/Output Timing. Btll0 Pin Descriptions Pin Name Description FSADJUST (1-4) Full-scale adjust controls. A resistor (RSET) between each of these pins and AGND controls the full-scale output currents. FS ADJUSTI controls the full-scale output current for IOUTl and IOUT2, FS ADJUST2 controls the full-scale output current for IOUTI and IOUT4, FS ADJUST3 controls the full-scale output current for lOUTS and IOUT6, and FS ADJUST4 controls the full-scale output current for IOUTI and lOUTS. The relationship between the full-scale output current of each D/A and RSET is defined as follows: RSET (0) = 1000 • VREF IN (V) / lOur (rnA) COMP (1-4) Compensation pins. These pins provide compensation for the internal reference amplifiers. A 0.1 I1F ceramic capacitor should be connected between each compensation pin and V AA, as illustrated in Figure 2. Decoupling the capacitors to VAA rather than to AGND provides the highest possible power supply noise rejection. COMP1 provides compensation for IOUTI and IOUT2, COMP2 provides compensation for IOUTI and IOUT4, COMP3 provides compensation for lOUTS and IOUT6, and COMP4 provides compensation for IOUTI and lOUTS. lOUT (1-8) High-impedance current outputs. These current outputs are designed to drive into a virtual ground, such as an operational amplifier. VREFOUf Voltage reference output. This output provides a 1.2 V (typical) reference, and may be directly connected to the VREF IN pin. When used to provide a reference voltage to VREF IN, an external 1000 0 resistor must be connected between VREF OUT and AGND. VREFIN Voltage reference input. Either an external voltage reference circuit or the VREF OUT pin is used to supply this input with a 1.2 V (typical) reference. A 0.1 I1F ceramic capacitor must be connected between this pin and VREF COMPo VREFCOMP VREF IN compensation pin. A 0.1 I1F ceramic capacitor must be connected between this pin and VREFIN. AGND Analog ground. All AGND pins must be connected. VM Analog power. All VAA pins must be connected. CS· Chip select control input (1TL compatible). To enable data to be written to or read from the device, this input must be a logical zero. While it is a logical one, DO-D7 are three-stated. Note that the BtllO will not function correctly while CS·, RD*, and WR* are simultaneously a logical zero. RD* Read control input (TTL compatible). To enable data to be read from the device, both CS* and RD· must be a logical zero. See Figure 1. PERIPHERALS 6·5 Btll0 Pin Descriptions (continued) Pin Name Description AO,A1,A2 Select control inputs (1TL compatible). These inputs specify which internal D/A latch will be written to or read, as follows: A2, AI, AO D/AOutput 000 001 010 011 100 101 110 111 loon l0UI'2 l0ur3 lour4 lours lour6 IOUI7 lOurs WR* Write control input ('ITL compatible). To enable data to be written to the device, both CS* and WR* must be a logical zero. Data is internally latched on the rising edge of WR* or CS*, whichever occurs first. See Figure 1. DO-D7 Bidirectional data bus (TTL compatible). Data is transferred into and out of the BtllO over this 8-bit data bus. DO is the least significant bit. 44-pin Plastic J-Lead (PLCC) Package 28 ZI COMP3 AGND AGND 211 FSADJUSTI VAA VAA 25 FSADJUSTZ 24 FSADJUSTI VREFCOMP 25 FSADJUST4 VAA VAA :n A2 21 Al AGND 20 AD AGND 19 cs· WR· 18 N/C VREFOIlT COMP4 Note: N/C pins may be left floating without affecting the performance of the Bt110. 6-6 SECTION 6 Dt110 PC Board Layout Considerations PC Board Considerations Supply Decoupling The layout for the BtllO should be optimized for lowest noise on the BtllO power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and AGND pins should be as short as possible to minimize inductive ringing. For the best performance, a 0.1 ~F ceramic capacitor should be used to decouple each VAA pin (or group of VAA pins if they are adjacent) to the adjacent AGND pins. The capacitor should be placed as close as possible to the device. Ground Planes The BtllO and any associated analog circuitry should have its own ground plane, referred to as the analog ground plane. This ground plane should connect to the regular PCB ground plane at a single point through a ferrite bead, as illustrated in Figure 2. This bead should be located within 3 inches of the Bt1lO. The analog ground plane area should encompass all BtllO ground pins, any external voltage reference circuitry, power supply bypass circuitry for the BtllO, the analog output traces, and any output amplifiers. The regular PCB ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the BtllO. Power Planes The BtllO and any associated analog circuitry should have its own power plane, referred to as the analog power plane. This power plane should be connected to the regular PCB power plane at a single point through a ferrite bead, as illustrated in Figure 2. This bead should be located within 3 inches of the BtllO. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all BtllO power pins, any external voltage reference circuitry, and any output amplifiers. It is important that portions of the regular PCB power and ground planes do not overlay portions of the analog power or ground planes, unless they can be arranged so that the plane-to-plane noise is common mode. This will reduce plane-to-plane noise coupling. A 0.1 ~F ceramic capacitor must also be connected between each COMP pin (COMPI-COMP4) and VAA. These capacitors should be placed as close as possible to the device. A 0.1 ~ ceramic capacitor must also be connected between the VREF COMP pin and the VREF IN pin. This capacitor should be placed as close as possible to the device. It is important to note that while the BtllO contains circuitry to reject power supply noise, this rejection decreases with frequency. If a switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane. Digital Signal Interconnect The digital inputs to the Bt1lO should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog ground and power planes. Any active termination resistors for the digital inputs should be connected to the regular PCB power and ground planes. Analog Signal Interconnect The BtllO should be located as close as possible to the output amplifiers. Also, any external voltage reference circuitry should be as close as possible to the BtllO to avoid noise pickup. The analog output signals should overlay the analog ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. PERIPHERALS 6- 7 Btll0 PC Board Layout Considerations (continued) OOMP(I-4) aJRRBNTTOVOLTAOBOONVBImlRS Ll r----------------------------------------------------- +5V Iotm. Cl IOl1l'1I---j----------+-IOllT3 I0IlT41--!----------+_IOIIT5 GROUND IOITI'6 I - - - j - - - - - - - - - - + _ l0UT7 lOUTS I--i----------+-L_..._.....__..._ ..._...._..........._.___ MPUDATABUS-----------~---+--;---+_--~-----------MPUOONnIDLBUS---------------~--~--+_--~------------ MPU~SBUS---1r--~::::::::~----t---~------------ Location Description CI-C8 C9 0_1 I1F ceramic capacitor 22 !1F tantalum capacitor ferrite bead 1000 a 1% metal film resistor 1% metal film resistors Ll,L2 Rl RSET(I-4) Note: The vendor numbers above are listed only as a guide_ characteristics will not affect the performance of the Bt110_ Figure 2. 6·8 Vendor Part Number Erie RPEl12Z5U104MSOV Mallory CSRI3G226KM Fair-Rite 2743001111 Dale CMF-SSC Dale CMF-SSC Substitution of devices with similar Typical Connection Diagram and Parts List (Internal Reference). SECTION 6 Btll0 Application Information External Voltage Reference Programmable Window Comparator For improved temperature stability, an external voltage reference may be used with the BtllO, as shown in Figure 3. In this instance, the VREF OUT pin should remain floating. The temperature stability of the internal reference is equivalent to about 1/4 LSB. The window comparator of Figure 4 is a circuit that may be used to determine whether the input voltage (Vin) lies within predefined limits. Using the BtllO, up to four programmable window comparators may be implemented. One DAC of the matched pair is used to set the low limit and the other DAC is used to set the high limit. Thus, each pair of DACs form a window of programmable size. The output will be high while Vlow S; Yin S; Vhigh. VAA For a RSET value of 1200 n and a VREF IN voltage of 1.2 V, the BtllO outputs a full scale output current of approximately 1 rnA onto lOUT! and IOUT2. The 1 ill resistor generates a 0 V to 1 V output voltage (for DAC codes $00 to $FF), which is amplified to 0 V to 5 V (5x) by the LM358 dual operational amplifier. In this configuration, the LM358 is operating from a single +5 V power supply. 0.1 VREF - - - -... AGND Figure 3. The LM3l9 dual comparator is also operating from a single +5 V power supply and compares the Vlow and Vhigh voltage levels to Yin. The 500 n pull-up resistor is necessary as the LM3l9 has open-collector outputs. External Voltage Reference. .. VIN +sv SOD T11.0UTPUT "I" INWINDOW Figure 4" Programmable Window Comparator. PERIPHERALS 6 - 9 Btll0 Application Information (continued) Programmable Power Supply Driving Active Devices The Bt110, when used with an external operational amplifier and power transistor, provides a way of generating voltages and currents outside of the BtllO's normal capability. Figure 5 illustrates a 0 V to 10 V programmable power supply. If the BtllO is driving an active device whose supply is outside the 0 V to 5 V range, the analog output(s) For a RSET value of 1200 n and a VREF IN voltage of 1.2 V, the BtllO outputs a full-scale output current of approximately I rnA onto IOUT1. The I ill resistor is used to generate a 0 V to I V output voltage from the BtllO (for DAC codes $00 to $FF). One of the operational amplifiers in the LM358 (AI) is used to multiply the voltage at IOUTI by lOx, resulting in a 0 V to 10 V range. In this configuration, the LM358 is operating from a single +15 V power supply. Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. The other operational amplifier in the LM358 (A2) is used as a buffer and driver for the TIP31 transistor. RS is the current limiting resistor to shut down the output in case of an overload. The correct value for RS is determined as follows: RS = 0.7 /IOUTmax should be clamped to VAA (see Figure 5). ESD and Latchup Considerations All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid DAC power decoupling networks with large time constants, which could delay V AA power to the device. Ferrite beads must only be used for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all VAA pins are at the same potential, and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. For output voltages down to or near 0 V, it is necessary to use a CMOS operational amplifier with a very low saturation voltage, or a plus/minus power supply and a bipolar operational amplifier to allow for output saturation, which is typically 2 V to 3 V below the supply voltage. VAA RS ~----~V\~~----------1-------~VOUT Figure 5. 6 • 10 SECTION 6 Programmable Power Supply. Btll0 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Reference Voltage Symbol Min Typ Max Units VAA TA VREFIN 4.75 0 1.0 5.00 1.2 5.25 +70 1.3 Volts ·C Volts Symbol Min Typ Max Units 7.0 Volts VAA + 0.5 Volts +125 +150 ·C ·C +175 +150 ·C ·C 260 ·C 220 ·C Absolute Maximum Ratings Parameter VAA (measured to AGND) Voltage on any Signal Pin* Analog Output Short Circuit Duration to any Power Supply or Common Ambient Operating Temperature Storage Temperature Junction Temperature Ceramic Package Plastic Package AGND--O.5 ISC TA TS TJ - indefinite -55 -65 TSOL Soldering Temperature (5 seconds, 1/4" from pin) TVSOL Vapor Phase Soldering (1 minute) Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ... This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. PERIPHERALS 6 - 11 Btll0 DC Characteristics Parameter Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Full-Scale (Gain) Error Using Internal Reference Using External Reference Zero Error Monotonicity Coding Digital Inputs Input High Voltage Input Low Voltage Input High Current (Vin =2.4 V) Input Low Current (Vin =0.4 V) Input Capacitance (f =1 MHz, Vin =2.4 V) Digital Outputs (DO--07) Output High Voltage (lOH =-800 JlA) Output Low Voltage (lOL =6.4 rnA) 3-state Current Output Capacitance Analog Outputs Output Current DAC-to-DAC Matching Output Compliance Output Impedance Output Capacitance (lOUTI-IOUTS =0 rnA) Reference Output Voltage Reference Output Current Reference Input Current Power Supply Rejection Ratio (COMP =0.1 JlF, f = 1 kHz) Symbol Min Typ Max Units 8 8 8 Bits ±l ±1 LSB ±10 ±5 5 %ofFSR %ofFSR lL I.l.. ID FZ LSB IIA guaranteed Binary VlH VlL IIH 2.0 AGND-t>.5 IlL CIN VOH Volts Volts -1 IIA 10 IOZ CDOur Volts 0.4 Volts 1 IIA 10 2 VOC RAOUr CAOur -1.0 VREFOur IREFour IREFIN 1.05 IIA pF 2.4 VOL PSRR VAA+0.5 0.8 1 pF 1 5 +1.2 125 20 1.17 1.2 0.3 rnA % Volts kn pF 1.29 Volts rnA 10 IIA %/%!1VM Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 1000 n, VREF IN = 1.0 V. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 6 • 12 SECTION 6 BnxKtreeQP Btll0 AC Characteristics Parameter Conversion Rate Symbol Min Typ Tmax Max Units 100 ns CS*, AO, AI, A2 Setup Time CS*, AO, AI, A2 Hold Time 1 2 30 5 ns ns WR·LowTune RD*, WR* High Time RD· Asserted to Data Bus Driven RD· Asserted to Data Valid RD· Negated to Data Bus 3-Stated 3 4 30 20 ns ns 5 6 7 10 Write Data Setup Time Write Data Hold Time 8 9 20 10 Analog Outputs Analog Output Delay Analog Output Rise/Fall Time into 50 n into 1 W Analog Output Settling Time into 50 n into 1 W Data Feedtbrough Glitch Impulse DAC-to-DAC Crosstalk VAA Supply Current· 10 60 40 ns ns ns ns ns ns 15 11 10 ns ns 100 ns ns dB pV-sec dB 38 rnA 350 12 800 -30 75 -25 IAA 30 Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 1000 n, VREF IN = 1.0 V. TTL input values are 0-3 V, with input rise/fall times s 4 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load S 10 pF into a virtual ground, DO-D7 output load S 130 pF. See timing notes in Figure 6. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *IAA (typ) at VAA = 5.0 V. IAA (max) at VAA = 5.25 V. PERIPHERALS 6· 13 .. Btll0 Timing Waveforms 1_ I CSO • AD, AI. A1 ~ t- VALID 3 RD*, WK· 4 6 S DO - D7 (READ) vi DATA OUT(RDo = 0) X DO - D7 (WRll1!) J--7 - I X DATAIN(WRo.O) I I '~9 B I", IOUT(l-B) .r=11 r - - I 1----11 Note 1: Output delay measured from the rising edge of WR* to the 50% point of full-scale transition. Note 2: Settling time measured from the 50% point of full-scale transition to the output remaining within ±1 LSB. Note 3: Output rise/fall time measured between the 10% and 90% points of full-scale transition. Figure 6. Input/Output Timing. Ordering Information 6 - 14 Model Number Package Btll0KPI 44-pin Plastic I-Lead SECTION 6 Ambient Temperature Range 0° to +70° C 'Btll0 Device Circuit Data .......- r-_....---------1~- VAA VRIlPIN >--tt-- TODACS PSADJUST IPBEDBACK L-~....----4~-_+_-AGND Equivalent Circuit of the Reference Amplifier. Bt110 - - - - - - 4 1 1 - - VAA DO-D7 lOOT T- RL 20PP Equivalent Circuit of the Current Outputs. PERIPHERALS 6 - 15 Preliminary Information This document contains information on a new product. The parametric information. although not fully characterized. is the result of testing initial devices. Distinguishing Features • • • • • Applications • • • • 250 MHz Pipelined Operation Optional 3 x 8 Overlay Registers lOKH ECL Compatible Synchronous or Asynchronous Reading Asynchronous Writing 28-pin 0.6" or 24-pin OJ" DIP Package Typical Power Dissipation: 1100 mW High-Resolution Color Graphics CAE/CAD/CAM Image Processing Microcode Storage Related Products • Bt424. BtSOl. BtS02 Functional Block Diagram Bt401 Bt403 250 MHz 10KH EeL 256 x 8 Pipelined Static RAM Product Description The Bt401 is a pipe1ined 256 x 8 RAM designed for high-speed graphics applications. In addition to the 256 colors supported by the RAM. an additional three colors are available via the internal overlay registers. allowing for cursor support. highlighting. etc. Also incorporated is an input/output "pipe" for maintaining synchronization of video control signals. Both the Bt401 and Bt403 are 10KH ECL compatible. CLOCK a..OCK'" WE' VEE vee The Bt403 does not have the three overlay registers and input/output "pipe". --~~~WTIutt-----------------~ Fr' --r...,,==~::.....J ~, J;====~ AO·A7 L A SO.SI 3X8 T C OVERLAY H DX Brooktree Corporation 9950 Barnes Canyon Rd. San Diego. CA 92121-2790 (619) 452-7580· (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 L401001 Rev. D I-.l.-t-_ DO· D7 I---t--QX 6 . 17 The devices may be read either synchronously or asynchronously and written to asynchronously. The asynchronous modes of operation simplify interfacing to an MPU. __ ~ Bt401i403 Circuit Description As illustrated in the functional block diagram, the Bt401 and Bt403 each contain a pipelined 256 x 8 RAM and control logic. The Bt401 has three 8-bit overlay registers, which may be used to overlay menus, cursors, etc. onto the display screen, and a "pipe" consisting of OX and QX to facilitate pipelining of control signals. Regardless of the value of FT*, the OX value is latched on the rising edge of CLOCK and output onto QX two clock cycles later. Table 1 summarizes the various modes of operation. AO-A7 SO SI FT* WE* CS* Operation Mode $00 : $FF 0 : 0 0 : 0 1 : 1 x : x 0 : 0 read RAM location $00 : read RAM location $FF synchronous : synchronous $xx $xx $xx $xx $xx 0 1 1 x x 1 0 1 x x 1 1 1 1 0 x x x x x 0 0 0 I 1 read overlay register 1 read overlay register 2 read overlay register 3 00-07=0 00-07=0 synchronous synchronous synchronous synchronous asynchronous $00 : $FF 0 : 0 0 : 0 0 : 0 I : 1 0 : 0 read RAM location $00 : read RAM location $FF asynchronous : asynchronous $xx $xx $xx 0 1 1 1 0 1 0 0 0 1 1 1 0 0 0 read overlay register 1 read overlay register 2 read overlay register 3 asynchronous asynchronous asynchronous $00 : $FF 0 : 0 0 : 0 0 : 0 0 : 0 0 : 0 write RAM location $00 : write RAM location $FF asynchronous : asynchronous $xx $xx $xx 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 write overlay register 1 write overlay register 2 write overlay register 3 asynchronous asynchronous asynchronous Table 1. 6 - 18 The device operates in either a synchronous read, asynchronous read, or an asynchronous write mode, as determined by the state of the FT. input. The synchronous read mode is typically used only for high-speed (250 MHz) read operations, while the asynchronous read and write modes are used to enable the MPU to read and write to the device at relatively slower data rates. SECTION 6 Control Truth Table. Broddree~ Bt401/403 Circuit Description (continued) Synchronous Read Operation The AO-A7, SO, SI, and CS* inputs are latched on the rising edge of CLOCK. SO and S 1 are used to specify whether the RAM or one of the overlay registers is to provide data, as illustrated in Table 1. When accessing the RAM, the AO-A7 inputs are used to specify which one of the 256 locations are to provide the data. When accessing the overlay registers, the AO-A7 inputs are ignored. During synchronous operation, the WE* input is ignored. Note that CS* must be a logical zero to enable the device to output data during synchronous operation. If CS* is a logical one, the DO-D7 pins are forced to a logical zero, and the AO-A7, SO, SI, and WE* inputs are ignored. During synchronous read operation, the CS* may have the same timing as AO-A7, and is pipelined to maintain synchronization with these signals. Figure 1 illustrates the read timing for synchronous operation. CLOCK CS·. so. AO·A7. 51. DX VALlO .. DATAOUf DO·D7. QX Figure 1. Read Timing (Synchronous Mode). PERIPHERALS () - 19 Bt401/403 Circuit Description (continued) Asynchronous Read/Write Operation During asynchronous operation, the part may be both written to and read. In this instance, the internal input and output latches for the data and address paths are configured to be transparent. The WE· input specifies whether the MPU is reading (WE. = 1) or writing (WE· = 0) to the RAM or overlay registers. Figure 2 illustrates the read timing and Figure 3 illustrates the write timing during asynchronous operation. The 80 and 81 inputs are used to specify whether the MPU is accessing the RAM or one of the overlay registers, as illustrated in Table 1. When accessing the RAM, AO-A7 specify which RAM location is being accessed, otherwise they are ignored. AD· A7. ==x so. SI X ADDRESS \ Fl"" I I \ cs· / DO·D7 Figure 2. Read Timing (Asynchronous Mode, WE· = 1). I cs· \ AD· A7. so. SI \ DATA our ______~x~______ V_MID ______~x~ ____________ \~ ___-J/ \'---~/ WE· DO·D7 _____....Jx Figure 3. 6 - 20 SECTION 6 DATA IN X'--_________ Write Timing (Asynchronous Mode). Bt401/403 Pin Descriptions Pin Name Description CS* Chip select control input (ECL compatible). A logical zero on this input enables data to be written to or read from the device. A logical one forces the DO-D7 pins to a logical zero. It is latched on the rising edge of CLOCK. WE* Write enable control input (ECL compatible). A logical zero on this input enables data to be written into the device. Data is intema1ly latched on the rising edge of WE*. See Figure 1. DO-D7 Bidirectional data bus (ECL compatible). DO is the least significant bit. Data is transferred into and out of the device over this eight bit data bus. Fr* Feedthrough control input (ECL compatible). A logical one configures the device for synchronous operation and a logical zero configures the device for asynchronous operation. Note that the setup and hold times must be met when switching between synchronous and asynchronous operation. While Fr· is a logical one, the rising edge of CLOCK latches the CS*, AO-A7, SO, and SI inputs, and data is output onto DO-D7 following the rising edge of CLOCK. While Fr· is a logical zero, the internal latches for these signals are transparent. CLOCK, CLOCK* Differential clock inputs (ECL compatible). The device may be driven by a single-ended clock by connecting CLOCK* to VBB (-13 V). AO-A7 Address inputs (ECL compatible). AO-A7 are used to specify which location in the RAM is being accessed, if both SO and S1 are a logical zero. If either SO or S1 are a logical one, AO-A7 are ignored. See Table 1. SO, SI Select control inputs (ECL compatible). On the Bt401, the SI and SO inputs specify whether the RAM or one of the overlay registers is being accessed. SO and SI are not incorporated on the Bt403. See Table 1. DX,QX Pipe input and output (ECL compatible). The value of the DX input is latched on the rising edge of CLOCK and output onto QX two clock cycles later, regardless of the state of Fr· . These are typically used to maintain synchronization of data and control signals. DX and QX are not incorporated on the Bt403. VFE Device power. All VEE pins must be connected. vee Device ground. All VCC pins must be connected. cs· WH· FfO SI Fr· WH· fY1 so fY1 cs· D6 A7 D6 A7 05 A6 05 A6 D4 AS D4 AS vee vee A4 VBI! vee vee A4 VBI! 03 A3 03 02 A2 D2 A2 01 AI 01 AI DO AO DO AO QX OX CLOCK· A3 CLOCK CLOCK· CLOCK Bt401 Bt403 PERIPHERALS , • 11 .. Bt401/403 Bt401/403-Recommended Operating Conditions Parameter Device Ground Power Supply Ambient Operating Temperature Min Typ Max Units vee 0 VEE -4.9 0 -5.2 Volts Volts TA 0 0 -5.5 +70 Symbol ·e Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 liner feet per minute over the device either mounted in the test socket or on the printed circuit board. Bt401/403-Absolute Maximum Ratings Parameter VEE (measured to Symbol Min Max Units -8.0 Volts VEE Volts -30 rnA TJ +125 +150 +175 ·e ·e ·e TSOL 260 ·C veC) Voltage on any Pin (except DO - 07, QX) 0 Output Current Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, 1/4" from pin) TA TS -55 -65 Typ Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6·22 SECTION 6 Brocktree~ Bt401/403 Bt401l403-DC Characteristics Max Units -1170 -1130 -1070 -840 -810 -735 mV mV mV 0 +25 +70 -1950 -1950 -1950 -1480 -1480 -1450 mV mV mV VOH 0 +25 +70 -1020 -980 -920 -840 -810 -735 mV mV mV Output Low Voltage VCL 0 +25 +70 -1950 -1950 -1950 -1630 -1630 -1600 mV mV mV Input High Current (Vin = VIHmax) IIH 0 +25 +70 Input Low Current (Vin = VILmin) m.. 0 +25 +70 VEE Supply Current IEE 0 +25 +70 Parameter Symbol TA(OC.) Min Input High Voltage vrn 0 +25 +70 Input Low Voltage VIL Output High Voltage Typ J.IA J.IA J.IA 220 220 220 J.IA J.IA J.IA 0.5 0.5 0.5 280 280 280 rnA rnA rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with output loading of 50 n to -2.0 V. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. PERIPHERALS 6 - 23 Bt401i403 Bt401!403-AC Characteristics Parameter Symbol Min Typ Frnax Clock Rate Max Units 250 MHz 2 ns ns ns ns ns ns Clocks Read (Synchronous Mode) Clock Cycle Time Clock Pulse Width High Clock Pulse Width Low Clock to Output Valid Input Setup Time Input Hold Time Pipeline Delay 1 2 3 4 5 6 7 4 1 1 0 1 3 3 3 Read (Asynchronous Mode) AO-A7 Access Time CS* Access Time CS* Recovery Time FT* Setup Time 10' 5 5 8 9 10 11 5 ns ns ns ns WE* Pulse Width Low AO-A7 Setup Time AO-A7 Hold Time DO-D7 Setup Time DO-D7 Hold Time 12 13 14 15 16 75 5 20 55 5 ns ns ns ns ns CS* Setup Time CS* Hold Time FT* Setup Time FT* Hold Time 17 18 19 20 5 5 5 5 ns ns ns ns Write (Asynchronous Mode) Output Rise/Fall Time 2 ns Test conditions (unless otherwise specified): "Recommended Operating Conditions" with output loading of 50 n to -2.0 V. ECL input values are -0.89 to -1.69 V, with input rise/fall times S 2 ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. Output rise/fall time measured between the 20% and 80% points. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 6 - 24 SECTION 6 Bt401/403 Timing Waveforms CS·, AO-A7, 50,51, OX oo-D7,QX VALID ~~ _ _~X'- ___..JX'-___ --J ' -_ __ Figure 4. AO-A7. so, 51 Read Timing (Synchronous Mode). VALID 11 00-07 OATAOUT Figure 5. Read Timing (Asynchronous Mode, WE· = 1). PERIPHERALS 6 - 2S Bt401/403 Timing Waveforms (continued) es' ~ AD-A7, SO, 51 VALID ~ i--1g lO- r WE' 17 12 13 t DO-D7 DATA IN IS I Figure 6. 18 14 {=16 Write Timing (Asynchronous Mode). Ordering Information 6 • 26 Ambient Temperature Range Model Nwnber Overlays Compatibility Package Bt401KC 3x8 10KHECL 28-pin 0_6" CERDIP 0 0 to +700 C Bt403KC none lOKHECL 24-pin 0.3" CERDIP 0 0 to +70 0 C SECTION 6 Preliminary Information This document contains infonnation on a new product. The parametric infonnation, although not fully characterized, is the result of testing initial devices. Distinguishing Features Configurations • • • • • , • , • • • • , 250 MHz Operation Overlay Support TTL Pixel Inputs TTL MPU Address Interface ECL Shift Register Outputs Shift Enable and Output Enable Controls Optional Single +5 V Operation 68-pin PGA Package with Alignment Pin Typical Power Dissipation: 1.25 W Customer Benefits • , , , • • One 4O-bit Shift Register Two 16-bit or 20-bit Shift Registers Five 8-bit Shift Registers Four lO-bit Shift Registers Bt424 250 MHz 40-bit Multi-Tap TTL/ECL-Compatible Video Shift Register Related Products Product Description , • • • The Bt424 is a 40-bit multi-tap shift register. It is designed specifically for high-resolution graphics systems. Bt40l/403 Btl07 Btl09 Bt492 TTL pixel data from the frame buffer is typically loaded at either 1/8 or 1/10 the clock rate (up to about 32 MHz) using the TTL-compatible LLD'" signal. Data is then transferred from the input latch to the shift register using the ECL-compatible load signal (SLD"'). The double-buffering of incoming pixel data simplifies system timing. Flexible Power Supply Reduced Component Count Simplifies PCB Layout Reduces PCB Interconnect Low Bus Loading Increases System Reliability Functional Block Diagram CLOCK CLOCK" SEN· SO,SI (ECL) (Ba.) (ECL) (TIL) The shift register is clocked by the ECL-compatible CLOCK and CLOCK'" inputs, and features ECL-compatible serial input (SIN) and shift enable (SEN"') controls. TILVCC QO (ECL) TILGND BCLVBB QI (ECL) BCLVCC Q2 (Ea.) DO·D39 (TIL) Q3 (Ea.) Q4 (Ea.) OB' (ECL) Ll.D- SIN SW· AO ~ A4 AEN* (TIL) (ECL) (Ba.) (TIL) (TIL) Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 L424001 Rev. G 6 - 27 The Bt424 performs TTL-to-ECL translation of the MPU address (AO-A4), eliminating external address translators. The MPU address interface enables the MPU address(AO--A4) to be output onto the Q0-Q4 pins, overriding the shift register data. This interface is controlled by the TTL-compatible address enable (AEN*) signal. The Bt424 has separate TTL and ECL supply pins, enabling operation from a single +5 V supply, or a +5 V and -5.2 V supply. a Bt424 Circuit Description As illustrated in the functional block diagram, the Bt424 contains a 40-bit input latch, a 40-bit shift register, and control logic. General Shift Register Operation The 40-bit shift register has multiple taps, as illustrated in the functional block diagram. As illustrated in Figure 3, on the rising edge of LLO*, 00-039 are latched into the input latch. Oata is transferred from the input latch to the shift register synchronously on the rising edge of CLOCK while SLO* is a logical zero. Note that while LLO* is a logical zero, the input latch is transparent, as illustrated in Figure 4. The multiplexers select one of two taps from the 40-bit shift register or a MPU address input. The output of the multiplexers are registered synchronously to CLOCK and output onto the QO-Q4 pins. The SEN* input may be used to synchronously enable (logical zero) or disable (logical one) the shift This is useful for register from clocking. implementing hardware zooming in a graphics application. Figure 5 shows the shift timing and SEN* timing. The OE* input is used to enable (logical zero) or disable (logical one) the outputs asynchronously to CLOCK, as shown in Figure 6. Dual 20-blt Shift Register Operation When used as a dual 20-bit shift register, only the QO and Q2 outputs are used, and the Ql, Q3, and Q4 outputs are ignored. For QO, DO is the fust bit output, followed by 01, etc. For Q2, D20 is the fust bit output, followed by D21, etc. SLD* and LLD* should occur once every 20 clock cycles. SO and SI must configure the Bt424 as four 10-bit shift registers. Dual t6-blt Shift Register Operation When used as a dual 16-bit shift register, only the QO and Q2 outputs are used, and the Ql, Q3, and Q4 outputs are ignored. For QO. DO is the fust bit output. followed by Dl. etc. For Q2, D16 is the first bit output, followed by D17, etc. SLD* and LLD* should occur once every 16 clock cycles. SO and SI must configure the Bt424 as five 8-bit shift registers. Quad to-bit Shift Register Operation When used as a quad lO-bit shift register, all output except Q4 are used (which is ignored). For QO, DO is the fust bit output, followed by Dl, etc. For Ql, DIO is the first bit output, followed by Dll, etc. For Q2, D20 is the first bit output, followed by D21, etc. For Q3, D30 is the first bit output, followed by D31. etc. SLD* and LLD* should occur once every 10 clock cycles. SO and S 1 must configure the Bt424 as four 10-bit shift registers. Quint 8·bit Shift Register Operation Single 40-bit Shift Register Operation When used as a 40-bit shift register, only the QO output is used, and the QI-Q4 outputs are ignored. DO is the fust bit output, followed by 01, etc. SLO* and LLO* should occur once every 40 clock cycles. The state of the SO and S 1 inputs is not important, and they may be connected to TTL GND. Note that single shift registers of any length (up to 40 bits) may be implemented by simply loading the parallel data at the appropriate time. For example, a 32-bit shift register may be implemented by loading parallel data once every 32 clock cycles. 6·28 SECTION 6 When used as a quint 8-bit shift register, all outputs are used. For QO, DO is the first bit output, followed by Dl, etc. For Ql, D8 is the first bit output, followed by D9, etc. For Q2, D16 is the first bit output, followed by D17, etc. For Q3, D24 is the fust bit output, followed by D25. etc. For Q4, D32 is the fust bit output, followed by D33, etc. SLD* and LLD* should occur once every eight clock cycles. SO and S1 must configure the B t424 as five 8-bit shift registers. Bt424 Circuit Description (continued) MPU Address Interface The Bt424 accepts TTL-compatible MPU addresses (AO-A4) and translates them to ECL-compatible levels, eliminating the need for external TTL/ECL translators along the address path. While AEN* is a logical one, pixel data from the shift register is output onto the QO-Q4 pins. While AEN* is a logical zero, AO-A4 are output onto the QO-Q4 pins. Figure 7 illustrates the MPU address timing. Note that QO-Q4 are always output following the rising edge of CLOCK regardless of the value of AEN*. The Bt424 interfaced to the overlay bit planes is configured as a quint 8-bit shifter, and serializes the overlay information. The QO-Q3 outputs are wire-ORed onto the pixel data bus to the RAMDAC. The D32-D39 inputs are serialized to generate the overlay enable (OL) control signal for the RAMDAC. Note that if no overlay information is being displayed, the QO-Q4 outputs are a logical zero, allowing normal pixel data to be displayed. Eight four-input TTL OR gates are required to generate the overlay active signals to the Bt424s. DO, D8, D16, and D24 are ORed together to generate D32, etc. SO, SI Select Inputs Power Supply Operation SO and S 1 specify the configuration of the Bt424 as shown in Table 1. The Bt424 may operate from a +S V and -S.2 V power supply or from a single +S V power supply, as shown in Table 2. Sl SO 0 x 1 0 1 0 Table 1. Function quad 10-bit quint 8-bit quad 8-bit, 8-bit overlay port SO, SI Control Inputs. Figure 1 shows using the Bt424 in a typical graphics system. In this instance, the RAMDAC has separate (nonmultiplexed) pixel and overlay data inputs. Therefore, all three Bt424s are configured for the same mode of operation (either quad lO-bit or quint 8-bit depending on the specific application). Nominal Voltages Applied Supply Pin TTLVCC TILGND ECLVCC ECLVEE Table 2. Figure 2 shows a basic configuration using the B t424 with a RAMDAC that has mUltiplexed pixel and overlay inputs. The OL input of the RAMDAC specifies whether pixel (OL = 0) or overlay (OL = 1) data is present on PO-P7. Single Supply System Dual Supply System +S.OV OV +S.OV OV +S.OV OV OV -S.2 V Power Supply Operation. Inputs and outputs are temperature and voltage compensated. The Bt424s interfaced to bit planes 0-7 are configured to support overlays (S 1 = 1, SO = 0). DO-D7, D8-D1S, D16-D23, and D24-D31 are configured as four 8-bit pixel input ports, while D32-D39 are configured as an 8-bit overlay active input port. If D32-D39 contain a logical one on any bi., the QO-Q3 outputs are disabled and forced to a logical zero, enabling overlay information to be wire-ORed onto the QO-Q3 outputs. PERIPHERALS 6 • 29 III FRAMEBtlPI'BR PLANE PLANE PLANE PLANE OVERLAY OVIlRLAY OVERLAY OVERLAY 0 I 2 3 00-07 OS-DIS 016-023 0:14-031 Bt424 QO QI Q2 Q3 OLO OLI OL2 OL3 SI=X_5O=1 RAMDAC BIT BIT BIT BIT PLANE PLANE PLANE PLANE 0 I 2 3 DO-07 DS-DiS DI6-D23 D:I4-D31 SI=X,SO=I QO QI Q2 Q3 PO PI P2 P3 BIT BIT BIT BIT 1'LANI! 4 DO-07 DS- DIS Dl6-D23 D:I4-D31 QO QI Q2 Q3 P4 Bt424 1'LANI! S 1'LANI! 6 1'LANI! 7 Figure 1. Bt424 SI=X,SO=I 256 COLOR RAM, IS OVERLAYS PS P6 P7 Using the Bt424 with Separate Pixel and Overlay Inputs (256 Colors, IS Overlays). FRAME BUFFER OVllRLAY OVERLAY OVERLAY OVERLAY 1'LANI! 0 PLANE I PLANE 2 PLANE 3 BIT BIT BIT BIT PLANE PLANE PLANE PLANE 0 I 2 3 BIT BIT BIT BIT PLANE PLANE PLANE PLANE 4 I~~ S 4-1NP!IT ORoATES r--- S 6 7 '--- Figure 2. 6 ·30 DO-07 D8-DlS DI6-D23 D:I4-D31 Bt424 QO QI Q2 Q3 - SI=X,SO=I Q4 OL SI=I,5O=0 QO QI Q2 Q3 PO PI P2 P3 QO QI Q2 Q3 P4 Bt424 D32-D39 RAMDAC DO-D7 D8-DlS DI6-D23 D:I4-D31 D32-D39 DO-07 D8-DlS Dl6-D23 D:I4-D31 D32-D39 Bt424 SI=I,5O=0 256 COLOR RAM, IS OVERLAYS PS P6 P7 Using the Bt424 with Multiplexed Pixel/Overlay Inputs (256 Colors, 15 Overlays). SECTION 6 Bt424 Pin Descriptions Pin Name Description DO-D39 Parallel data inputs (TfL compatible). These inputs are latched into the input latch on the rising edge of LLD*, asynchronous to CLOCK. SIN Shift data input (ECL compatible). This input is latched on the rising edge of CLOCK, and may be used to serially load the shift register. If not used, it should be connected to ECL GND. SEN* Shift enable control input (ECL compatible). This input may be used to synchronously start or stop the shift register from clocking. A logical zero enables shifting, and a logical one disables shifting. liD* Input latch load control input (TfL compatible). The rising edge of LLD* is used to latch DO-D39 into the input latch. While LLD* is a logical zero, the input latch is transparent. SLD* Shift register load control input (ECL compatible). SLD* is used to transfer data from the input latch to the shift register synchronously to CLOCK. Data is transferred on the rising edge of CLOCK while SLD* is a logical zero. CLOCK, CLOCK* Differential clock inputs (ECL compatible). The clock rate is typically the pixel clock rate of the video system. The Bt424 may be used with a single-ended clock by connecting CLOCK* to VBB (-1.3 V) QO-Q4 Shift register outputs (ECL compatible). These pins output either DO-D39 data (AEN* = logical one) or AO-A4 data (AEN* = logical zero). Data is output following the rising edge of CLOCK. OE* Output enable control input (ECL compatible). A logical one forces the QO-Q4 outputs to a logical zero, while a logical zero enables data to be output onto QO-Q4. The QO-Q4 outputs are enabled and disabled asynchronously to CLOCK. SO, S1 Select control inputs (TfL compatible). These inputs control the operation of the device as specified in Table 1. AO-A4 Address inputs (TfL compatible). These are typically address inputs from the MPU, used to address the color palette RAM during MPU read/write cycles to the color palette RAM. AEN* Address enable control input (TfL compatible). While AEN* is a logical zero, AO-A4 are output onto Q0-Q4 following the rising edge of CLOCK. If AEN* is a logical one, AO-A4 are ignored. TILVCC Power supply pins for the TTL-compatible circuitry. TILGND Ground pins for the TTL-compatible circuitry. ECLVEE Power supply pins for the ECL-compatible circuitry. ECLVCC Ground pins for the ECL-compatible circuitry. PERIPHERALS 6 • 31 .. lJnxj{tree® Bt424 Pin Descriptions (continued) Signal Pin Signal Number CLOCK CLOCK* Signal Pin Number DO no 01 02 03 H11 H10 G11 GIO 025 026 027 028 029 B2 C1 C2 01 02 030 031 032 033 034 E1 E2 F2 G2 HI UD* A2 SID* SEN* SIN B3 A7 K4 D4 K2 D6 Sl 1.3 D7 AEN* AO Al K3 D9 Fll FlO Ell E10 011 010 011 012 013 014 010 Cll C10 Bll A10 035 036 037 038 039 H2 015 016 017 018 019 B10 B7 A6 B6 TILVCC F1 TILGND G1 AS ECLVEE ECLVEE B9 020 021 022 023 024 B5 ECLVCC ECLVCC ECLVCC ECLVCC A9 K5 so A2 A3 A4 6 • 32 A8 B8 Pin Number 05 os K9 LlO Kll K10 III QO Q1 Q2 Q3 Q4 K7 L7 K6 OE* LA J1 12 K1 L2 L8 L6 SECTION 6 A4 B4 A3 B1 L5 K8 L9 Brcxj{tree® Bt424 Pin Descriptions (continued) 013 D11 D9 f1I os D3 DI Ill. A2 014 DIS DI2 010 IJ8 Il6 D4 D2 DO A3 AI BVCC BYEI! NJ EVCC eLK CLK' BVCC Ql SEN' DI6 Q1 Q2 017 DI8 Q3 Q4 019 Dlll BVCC BYEI! D2l D22 SIN (E' DZl SID" AIlN' SI llD' D2S DZ7 D29 031 D32 D33 D3S D37 so D39 D1>I D26 D1ll D30 1VI H G P E D C B L K AUGNMENTPIN (ONBOTfOM) D A PERIPHERALS 6 • 33 Bt424 Recommended Operating Conditions Parameter TIL Device Ground EeL Device Ground TIL Power Supply ECL Power Supply Ambient Operating Temperature Symbol Min Typ Max Units TILGND EeLVCC TILVCC 0 0 +4.75 -4.2 0 0 0 +5.0 -5.2 0 0 +5.25 -5.5 +70 Volts Volts Volts Volts °C ECLVEE TA Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. Absolute Maximum Ratings Parameter Symbol Min EeL VEE (measured to ECL VCC) TIL VCC (measured to TIL GND) Typ Max Units -8.0 +7.0 Volts Volts Voltage on Any ECL Pin 0 ECLVEE Volts Voltage on Any TIL Pin TILGND -0.5 TILVCC +0.5 Volts -30 rnA TJ +125 +150 +175 °C °C °C TSOL 260 °C Q0-Q4 Output Current Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, 1/4" from pin) TA TS -55 -65 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6 • 34 SECTION 6 Bt424 ECL DC Characteristics Parameter Symbol Min Input High Voltage* Input Low Voltage* VIH VIL Output High Voltage* Output Low Voltage* VOH VOL Input High Current (Vin = VIHmax) Input Low Current (Vin = VILmin) ECL VEE Supply Current Typ Max Units -1165 -1810 -880 -1475 mV mV -1025 -1810 -880 -1620 mV mV llH 500 f.IA TIL 400 f.IA lEE 240 rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with QO-Q4 loading of 50 to -2.0 V. Typical values are based on nominal temperature. i.e .• room, and nominal voltage. i.e .• 5 V. n *Relative to ECL VCC. The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. TTL DC Characteristics Parameter Max Units 2.0 TTLVCC +0.5 Volts TTLGND -0.5 0.8 Volts llH 70 f.IA TIL -0.7 rnA ICC 100 rnA Symbol Min Input High Voltage* VIH Input Low Voltage* VIL Input High Current (Vin =2.4 V) Input Low Current (Vin =0.4 V) TTL VCC Supply Current Typ III Test conditions (unless otherwise specified): "Recommended Operating Conditions" with Q0-Q4 loading of 50 n to -2.0 V. Typical values are based on nominal temperature. i.e.• room. and nominal voltage. i.e .• 5 V. *Relative to TTL GND. PERIPHERALS 6 • 3S Bt424 AC Characteristics Parameter Symbol Clock Rate Min Typ Fmax Max Units 250 MHz Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time 1 2 3 4 1.5 1.5 ns ns ns LLD* Pulse Width Low Time LLD* Setup Time 4 5 7 8 ns ns SLD Setup Time SLD Hold Time 6 7 2 1 ns ns DO-D39 Setup Time to LLD* DO-D39 Setup Time to Clock DO-D39 Hold Time to LLD* DO-D39 Hold Time to Clock 8 9 10 11 10 15 0 0 ns ns ns ns QO-Q4 Output Delay 12 1.5 SEN* Setup Time SEN* Hold Time 13 14 2 1 ns ns SIN Setup Time SIN Hold Time 15 16 2.5 1.5 ns ns OE* Pulse Width Low Time OE* Enable Time OE* Disable Time 17 18 19 4 AO-A4 Setup Time AO-A4 Hold Time AEN* Setup Time AEN* Hold Time 20 21 22 23 12 0 5 0 4 3.5 4 ns ns ns ns ns ns ns ns Test conditions (unless otherwise specified): "Recommended Operating Conditions" with Q0-Q4 loading of 50 Q to -2.0 V. TTL input values are 0-3 V, with input rise/fall times S 4 ns, measured between the 10% and 90% points. ECL input values are -0.89 to -1.69 V, with input rise/fall times S 2 ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. Ordering Information 6 - 36 Model Number Package Bt424KG 68-pin Ceramic PGAwith Alignment Pin SECTION 6 Ambient Temperature Range O· to +70· C Bt424 Timing Waveforms DO·D39 LIJ). SID· a..OCK QO.Q4 Figure 3. Load Latch and Register Timing. .. DO·D39 VALID 11 SID· a..ocK QO.Q4 Figure 4. Transparent Latch Timing (LLD* = Logical Zero). PERIPHERALS 6 • 37 Bt424 Timing Waveforms (continued) SIN VALID 15 16 SBN" CLOCK QO-Q4 Figure 5. Shift Timing (SLD· = Logical OB· QO-Q4 Figure 6. AD - All Output Enable Timing. VALDl 20 21 AEN· QO-Q4 Figure 7. 6 - 38 SECTION 6 Address Enable Timing. One). Bt431 Distinguishing Features Applications • • • • • • • • High-Resolution Color Graphics Image Processing 64 x 64 Pixel User-Defmable Cursor Full-Screen/Window Cross Hair Cursor Pixel Positioning of Cursors Supports Pixel Rates up to 175 MHz 1:1,4:1, and 5:1 Output MUltiplexing TTL-Compatible Inputs/Outputs Standard MPU Interface +5 V CMOS Monolithic Construction 24-pin 0.3" DIP or 28-pin PLeC Package • Typical Power Dissipation: 450 mW Customer Benefits • Reduces Component Count Reduces PCB Area Requirements • Simplifies Cursor Implementation • Allows Fast Cursor Movement • Simplifies Software Interface Functional Block Diagram VSYNCO CLOCK Monolithic CMOS 64 x 64 Pixel Cursor Generator vee GND FORMAT t-.r,.~- CUR(A-E) Product Description The Bt431 cursor generator provides a 64 x 64 pixel user-definable cursor and a cross hair cursor for high-resolution, noninterlaced, monochrome or color graphics systems. The cross hair cursor may be implemented as a full-screen or full-window cross hair cursor. Both cursors may be displayed simultaneously, with logical OR and exclusive-OR operations supported. Either cursor may be moved off the top, bottom, left, or right side of the display without wrap-around. The cursors may be positioned with pixel resolution, and may be individually enabled or disabled from being displayed. A standard MPU bus interface is supported, simplifying system design. LOGIC OE" The Bt431 may be programmed to output cursor information for one, four, or five horizontally consecutive pixels, enabling it to be interfaced to either the multiplexed or nonmultiplexed overlay inputs of Brooktree RAMDACs. The 5: 1 output multiplex mode enables support of pixel rates up to 175 MHz. 00-07 Brooktree Corporation 9950 Barnes Canyon Rd_ San Diego, CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 L431001 Rev. J RjW co CI 6 - 39 Bt431 Circuit Description MPU Interface RAMDAC Interface As illustrated in the functional block diagram, the Bt431 supports a standard MPU bus interface, allowing the MPU direct access to the internal control registers and cursor RAM. The Bt431 is designed to generate cursor information using the overlay input ports of Brooktree RAMDACs. The MPU interface signals consist of DO-D7, CE*, RIW, CO, and Cl. Table 1 illustrates the truth table for the control inputs, and Figure 1 illustrates the MPU read/write timing of the device. Two 8-bit address registers (address registerO and address registed), cascaded to form a 16-bit address pointer register, are used to address the internal control registers and cursor RAM, as illustrated in Table 2. During read/write cycles to the cursor RAM, the 9 least significant bits of the address pointer register (ADDRO-ADDR8) are incremented following each read or write cycle to the cursor RAM. Thus, the MPU may load the address pointer register with the desired starting cursor RAM address, and burst load new cursor RAM data by writing up to 512 bytes of data to the device. Following a read or write cycle to RAM location $OIFF, the address pointer register resets to $0000. During accesses to the control registers, ADDRO-ADDR8 are incremented after any read or write cycle to a register. While accessing the control registers, the address pointer register will reset to $0000 only following a write cycle to location $OIFF. The address register is not incremented when read or written to. RIW. co. CI (]lO DO - D7 (READ) DO - D7 (WRITB) =x v~m To support RAMDACs with nonmultiplexed overlay inputs, the Bt431 may be programmed to output a single pixel of cursor information each CLOCK cycle. In this configuration, the CURA output of the Bt431 would connect directly to one of the overlay inputs of the RAMDAC. This configuration limits the cursor information to an effective 35 MHz rate. The CLOCK input of the Bt431 is typically connected directly to the CLOCK input of the RAMDAC. The Bt431 may be configured for 4:1 or 5:1 output multiplexing, and an external shift register used (with appropriate control logic) to interface to RAMDACs whose input pixel rate is greater than 35 MHz. In this configuration, the CLOCK must be driven at 1/4 or 1/5 the pixel clock rate. Pixel rates up to 175 MHz may be supported using this technique. )(~______________________________________________ \ / ---------------------« DATA OUT(R/W = I) ________________________.-Jx Figure I. 6 - 40 The Bt431 may be interfaced directly to RAMDACs with 4: 1 or 5: 1 multiplexed overlay ports. supporting display resolutions up to 1280 x 1024 pixels. In this instance, the CUR (A-E) outputs of the Bt431 would connect directly to the overlay inputs of the RAMDAC, and the CLOCK input of the Bt431 would typically be connected directly to the LD* or LDOUT pin of the RAMDAC. The Bt431 must be programmed to output either four or five horizontally consecutive pixels of cursor information each CLOCK cycle. This enables the B t431 to output cursor information at an effective 175 MHz rate (using 5:1 mode). SECTION 6 DATAIN(R/W-O) MPU Read/Write Timing. )>------ x'--____ Bt431 Circuit Description (continued) R/W C1 co 0 0 0 0 0 0 1 1 0 1 0 1 write write write write 1 1 1 1 0 0 1 1 0 1 0 1 read address registerO read address register1 read RAM location specified by address pointer register read control register specified by address pointer register Table 1. address registerO address register 1 to RAM location specified by address pointer register to control register specified by address pointer register MPU Control Truth Table. Address Pointer Register (ADDRl5-ADDRO) co Address Register1 (D7-DO) Address RegisterO (D7-oo) 0 0 : 0 0 0 : 0 00000000 00000000 : 00000000 00000001 00000001 : 00000001 00000000 00000001 : 1111 1111 00000001 00000001 : 1111 1111 cursor RAM location $000 cursor RAM location $001 : cursor RAM location $OFF cursor RAM location $100 cursor RAM location $101 : cursor RAM location $lFF 1 1 1 1 1 1 1 1 1 1 1 1 1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx command register cursor (x) low register cursor (x) high register cursor (y) low register cursor (y) high register window (x) low register window (x) high register window (y) low register window (y) high register window width low register window width high register window height low register window height high register xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Table 2. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Register!RAM location addressed Address Pointer Register. PERIPHERALS 6 - 41 Bt431 Circuit Description (continued) 64 x 64 Cursor Positioning When the cursor RAM is being displayed, the contents of the cursor RAM are output onto the CUR (A-E) outputs. A logical one in the cursor RAM results in a logical one being output onto the appropriate CUR (A-E) output during the appropriate clock cycle. The cursor pattern may be changed by changing the contents of the cursor RAM. (See Figure 2.) The 64 x 64 cursor is centered about the value specified by the cursor (x,y) register. Thus, the cursor (x) register specifies the location of the 31st column of the 64 x 64 RAM (assuming the columns start with o for the left-most pixel and increment to 63). Similarly, the cursor (y) register specifies the location of the 31st row of the 64 x 64 RAM (assuming the rows start with 0 for the top-most pixel and increment to 63). Note that the B t431 expects (x) to increase going right, and (y) to increase going down, as seen on the display screen. The cursor (x) position is relative to the first rising edge of CLOCK following the falling edge of HSYNC*. The software must take into account the internal pipeline delays, the amount of skew between the output cursor data and external pixel data, and whether 1:1, 4:1, or 5:1 output multiplexing is being done. The cursor (y) position is relative to the first falling edge of HSYNC* that is at two or more clock cycles after the falling edge of VSYNC*. (See Figure 2.) HSYNC· Y CURSOR(X.y) _ _--t--""J;O.;r......-........-........................ .J REGISTER 64.64 CURSOR AREA Figure 2. 6 - 42 SECTION 6 DISPLAY SCREBN 64 x 64 Cursor Positioning. Bt431 Circuit Description (continued) Cross Hair CIlrsor Positioning Cursor positioning for the cross hair cursor is also done through the cursor (x,y) register. (See Figure 3.) The intersection of the cross hair cursor is specified by the cursor (x,y) register. If the thickness of the cross hair cursor is greater than one pixel, the center of the intersection is the reference position. During times that cross hair cursor information is to be displayed, a logical one is output onto the appropriate CUR (A-E) output during the appropriate clock cycle. The cross hair cursor is limited to being displayed within the cross hair window, which is specified by the window (x,y), window width, and window height registers. Since the cursor (x,y) register must specify a point within the window boundaries, it Is the responslblllty of the software to ensure that the cursor (x,y) register does not spec:ify a point outside of the cross hair cursor window. If a full-screen cross hair cursor is desired, the window (x,y) registers should contain $0000 and the window width and height registers should contain SOFFF. Again, the cursor (x) position is relative to the first rising edge of CLOCK following the falling edge of HSYNC·. The software must take into account the internal pipeline delays, the amount of skew between the output cursor data and the external pixel data, and whether 1:1, 4:1, or 5:1 output multiplexing is being done. The cursor (y) position is relative to the first falling edge of HSYNC· that is two or more clock cycles after the falling edge of VSYNC·. c:; HSYNC' ~ t-- CROSS HAIR aJRSOR--r x ~. I r---~--~~----~ Y aJRSOR(x.Y) RBOJS11!R DISPLAY SCREI!N CROSS HAIR WINDOW Figllre 3. Cross Hair CIlrsor Positioning. PERIPHERALS 6 - 43 Bt431 Circuit Description (continued) Dual Cursor Positioning Both the 64 x 64 cursor and the cross hair cursor may be enabled for display simultaneously, enabling the generation of custom cross hair cursors. During the 64 x 64 pixel area in which the user-definable cursor would be displayed, the contents of the cursor RAM may be logically ORed or exclusive-ORed with the cross hair cursor information. As previously mentioned, the cursor (x,y) register specifies the location of bit (31,31) of the cursor RAM. As the user-defmable cursor contains an even number of pixels in the horizontal and vertical direction, there will be a one-pixel offset from being truly centered about the cross hair cursor. Figure 4 illustrates displaying the dual cursors, and Figure 5 illustrates the video input/output timing of the Bt431. CROSS HAIR CURSOR CURSOR ex.Y) REGISTER 64.64 DISPLAY SCRBIlN aJRSORARBA CROSSHAlR WINDOW Figure 4. Dual Cursor Positioning. ~~ HSYNC". VSYNC. CUR(A·B) ----'x==>-~("___O _ _---II Figure S. 6 - 44 SECTION 6 \1..-_Video Input/Output Timing. Bt431 Internal Registers Cursor (x,y) Register These registers are used to specify the (x,y) coordinate of the center of the 64 x 64 pixel cursor window, or the intersection of the cross hair cursor. The cursor (x) register is made up of the cursor (x) low register (CXLR) and the cursor (x) high register (CXHR); the cursor (y) register is made up of the cursor (y) low register (CYLR) and the cursor (y) high register (CYHR). They are not initialized and may be written to or read by the MPU at any time. CXLR and CXHR are cascaded to form a 12-bit cursor (x) register. Similarly, CYLR and CYHR are cascaded to form a 12-bit cursor (y) register. Bits D4-D7 of CXHR and CYHR are always a logical zero. Cursor (x) High (CXHR) Cursor (x) Low (CXLR) Data Bit D3 D2 D1 DO D7 D6 OS D4 D3 D2 D1 DO X Address XU X10 X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Cursor (y) High (CYHR) Cursor (y) Low (CYLR) Data Bit D3 D2 D1 DO D7 D6 OS D4 D3 D2 D1 DO Y Address Yll YIO Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 YI YO The cursor (x) value to be written is calculated as follows: Cx = desired display screen (x) position + D + H-P where P = 37 if 1:1 output multiplexing, 52 if 4:1 output multiplexing, 57 if 5:1 output multiplexing D = skew (in pixels) between the output cursor data and external pixel data H = number of pixels between the fIrst rising edge of CLOCK following the falling edge of HSYNC· to active video. The P value is 1/2 cursor RAM width + (internal pipeline delay in clock cycles • 1, 4, or 5 depending on multiplex selection) Values from $0000 to SOFFF may be written into the cursor (x) register. PERIPHERALS 6 - 45 Bt431 Internal Registers (continued) The cursor (y) value to be written is calculated as follows: Cy = desired display screen (y) position + V-32 where v= number of scan lines from the fust falling edge of HSYNC. that is two or more clock cycles after the falling edge of VSYNC· to active video. Values from $OFCO (-64) to $OFBF (-+4031) may be loaded into the cursor (y) register. The negative values ($OFCO to $OFFF) are used in situations where V < 32, and the cursor must be moved off the top of the screen. The cursor (x,y) registers should be written to only during the vertical retrace interval. Note that a falling edge of VSYNC. should not occur between the time the MPU writes the first byte of (x,y) and the last (fourth) byte of (x,y) information. Otherwise, temporary "tearing" of the cursor may occur. 6 - 46 SECTION 6 BrodrtreeQ!) Bt431 Internal Registers (continued) Cursor RAM This 64 x 64 RAM is used to derme the pixel pattern within the 64 x 64 pixel cursor window. It is not initialized, and may be written to or read by the MPU at any time. As MPU accesses to the cursor RAM have priority over the cursor display process, the cursor RAM should not be accessed during the horizontal sync intervals to minimize contention of the cursor updating and displaying processes. During MPU accesses to the cursor RAM, the address pointer register is used to address the cursor RAM, as illustrated below. Figure 6 illustrates the internal format of the cursor RAM, as it appears on the display screen. Address Pointer Register Value Address RAM Location $0000 $0001 : $OIFF byte $000 byte $001 : byte $IFF As shown below, bit D7 is the left-most pixel within a segment of eight pixels. This enables the software generation of cursor patterns without bit swapping to obtain the desired pattern. UPPBRLEFr alRNER AS OISPLAYIlD ON SCREIlII 64 PIXELS I I BYTBSOOO BYTBSOOI BYTBS007 BYTB$008 BYTB SOO!I BYTBSOCF BYTBS1F8 BYTBS1P9 BYTBS1P1' 64 PIXELS Figure 6. / ~ 107 D6 05 D4 D3 D2 01 001 Cursor RAM as Displayed on the Screen. PERIPHERALS 6 - 47 Bt431 Internal Registers (continued) Window (x,y) Register These registers are used to specify the (x,y) coordinate of the upper left comer of the cross hair cursor window. The window (x) register is made up of the window (x) low register (WXLR) and the window (x) high register (WXHR); the window (y) register is made up of the window (y) low register (WYLR) and the window (y) high register (wyHR). They sre not initialized and may be written to or read by the MPU at any time. WXLR and WXHR sre cascaded to fann a 12-bit window (x) register. Similarly, WYLR and WYHR sre cascaded to fann a 12-bit window (y) register. Bits D4-D7 of WXHR and WYHR sre slwsys a logicsl zero. Window (x) High (WXHR) Window (x) Low (WXU) Data Bit D3 D2 D1 DO D7 D6 OS D4 D3 D2 D1 DO X Address XlI XIO X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Window (y) Low (WYlR) Window (y) High (WYHR) Data Bit D3 D2 D1 DO D7 D6 OS D4 D3 D2 D1 DO Y Address Yll Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 YI YO The window (x) vslue to be written is cslculated as follows: Wx = desired display screen (x) position + D + H-P where P = 5 if 1:1 output multiplexing, 20 if 4:1 output mUltiplexing, 25 if 5:1 output mUltiplexing D = skew (in pixels) between the output cursor data and externs1 pixel data H = number of pixels between the first rising edge of CLOCK following the fslling edge of HSYNC· to active video. The P vslue is the number of internsl pipeline delays times 1, 4, or 5 depending on the multiplex selection. The window (y) vslue to be written is cslculated as follows: Wy =desired display screen (y) position + V where V = number of scan lines from the first fslling edge of HSYNC. that is two or more clock cycles after the fslling edge of VSYNC. to active video. Vslues from $0000 to $OFFF may be written to the window (x) and window (y) registers. A full-screen cross hair cursor is implemented by loading the window (x,y) registers with $0000 and the window width and height registers with $OFFF. The window (x,y) registers should be written to only during the verticsl retrace intervsl. Note that a fslling edge of VSYNC· should not occur between the time the MPU writes the first byte of (x,y) and the last (fourth) byte of (x,y) information. Otherwise, temporary repositioning of the cross hair cursor may occur. 6 - 48 SECTION 6 Bt431 Internal Registers (continued) Window Width and Height Registers These registers are used to specify the width and height (in pixels) of the cross hair cursor window. The window width register is made up of the window width low register (WWLR) and the window width high register (WWHR); the window height register is made up of the window height low register (WHLR) and the window height high register (WHHR). They are not initialized and may be written to or read by the MPU at any time. WWLR and WWHR are cascaded to form a 12-bit window width register. Similarly, WHLR and WHHR are cascaded to form a 12-bit window height register. Bits D4-07 ofWWHR and WHHR are always a logical zero. Wmdow Width Low Window Width High (WWHR) (WWLR) OataBit D3 D2 Dl DO D1 D6 OS D4 D3 D2 01 DO X Address XU X10 X9 X8 X7 X6 X5 X4 X3 X2 Xl XO Window Height High (WHHR) Window Height Low (WHIR) OataBit D3 D2 Dl DO D1 D6 OS D4 D3 D2 Dl DO Y Address Yll Y10 Y9 Y8 Y1 Y6 Y5 Y4 Y3 Y2 Y1 YO The actual window width is 2, 8, or 10 pixels more than the value specified by the window width register, depending on whether 1:1,4:1, or 5:1 output multiplexing is specified. The actual window height is 2 pixels more than the value specified by the window height register. Therefore, the minimum window width is 2, 8, or 10 pixels, for 1:1, 4:1, and 5:1 multiplexing, respectively, and the minimum window height is 2 pixels. Values from $()()()() to SOFFF may be written to the window width and height registers. The window width and height registers should be written to only during the vertical retrace interval. Note that a falling edge of VSYNC· should not occur between the time the MPU writes the first byte and the last (fourth) byte of information. Otherwise, temporary "resizing" of the cross hair cursor may occur. PERIPHERALS (I - 49 a Bt431 Internal Registers (continued) Command Register The command register is used to control various functions of the Bt431. It is not initialized, and may be written to or read by the MPU at any time. D7 Reserved. This bit should always be a logical zero. D6 64 x 64 cursor enable. A logical one enables the contents of the cursor RAM to be output during times that user-defmable cursor information is to be displayed. A logical zero disables the cursor RAM information from being output. 05 Cross hair cursor enable. A logical one enables cross hair cursor information to be output. A logical zero disables the cross hair cursor information from being output. D4 Cursor format control. If both the 64 x 64 cursor and the cross hair cursor are enabled for display, this bit specifies whether the contents of the cursor RAM are to be logically exciusive-ORed (logical zero) or ORed (logical one) with the cross hair cursor. 03,02 Multiplex control. These 2 bits specify whether I, 4, or 5 bits of cursor information are output every clock cycle, as follows: (00) (01) (10) (11) 01,DO 1:1 mUltiplexing 4: 1 multiplexing 5:1 mUltiplexing reserved Cross hair cursor thickness. These 2 bits specify whether the horizontal and vertical thickness of the ClOSS hair is I, 3, 5, or 7 pixels, as follows: (00) (01) (10) (11) 1 3 5 7 pixel pixels pixels pixels The horizontal and vertical segments are centered about the value in the cursor (x,y) register. 6 - 50 SECTION 6 Bt431 Pin Descriptions Pin Name Description VSYNC* Vertical sync control input (TTL compatible). A logical zero indicates that the display is currently in the vertical sync interval. It is latched on the rising edge of CLOCK. HSYNC* Horizontal sync control input (TTL compatible). A logical zero indicates that the display is currently in the horizontal sync interval. It is latched on the rising edge of CLOCK. CLOCK Clock input (TTL compatible). The rising edge of CLOCK is used to latch the VSYNC· and HSYNC. inputs, and to output cursor information onto the CUR (A-E) outputs. It is recommended that the CLOCK input be driven by a dedicated TIL buffer. If programmed for 1: 1 output multiplexing, CLOCK should be the pixel clock rate. When programmed for 4:1 or 5:1 output multiplexing, CLOCK should be 1/4 or 1/5 the pixel clock rate, respectively. CUR (A-E) Cursor outputs (TTL compatible). During the pixel times that cursor information is to be displayed, either cross hair cursor information or the contents of the cursor RAM are output onto these pins. If programmed for 4:1 output multiplexing, the CURE output will always be a logical zero. If programmed for 1:1 output multiplexing, the CURB, CURC, CURD, and CURE outputs will always be a logical zero. When programmed for 4:1 or 5:1 multiplexing, CURA corresponds to the left-most pixel, followed by CURB, etc., repeating every four or five pixels. OE* Output enable control input (TTL compatible). A logical one asynchronously three-states the CUR (A-E) outputs, and a logical zero asynchronously enables cursor data to be output on the cursor outputs. Readlwrite control input (TTL compatible). A logical zero indicates that the MPU is writing data to the device and a logical one indicates that the MPU is reading data from the device. See Figure 1. CE* Chip enable control input (TTL compatible). This input must be a logical zero to enable data to be written to or read from the device. During write operations, data is internally latched on the rising edge of CE*. See Figure 1. CO, C1 Control inputs (TTL compatible). These inputs specify the operation the MPU is performing. See Tables 1 and 2. DO-D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is the least significant bit. vee Power. GND Ground. PERIPHERALS 6 - 51 Bt431 Pin Descriptions (continued) 24-pin DIP Package CLOCK vee VSYNC· OE' HSYNC· GND DO CURA DI CURB D2 CURC D3 CURD 04 CURE DS CI D6 co D7 R/W GND CE' 28-pin Plastic J-Lead (PLCC) Package ~~~ \'l C\\ ~ ~ ~~ U !:I .. !'i !l GND 18 co OE' 11 R/W vcc 16 CE' CLOCK IS GND VSYNC" 14 D7 HSYNC· 13 12 D6 DO ., '" r- i5 ~ Q N oo 0-. ~ 8 ;:: N/C ;:: aa Note: N/C pins may be left floating without affecting the performance of the Bt431. ESD and Latchup Considerations Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. Avoid power decoupling networks with large time constants, which could delay V AA power to the device. Ferrite beads must only be used for analog power V AA decoupling. Inductors cause a time constant delay that induces latchup. Latchup can be prevented by assuring that all VCC pins are at the same potential, and that the VCC supply voltage is applied before the signal pin voltages. The correct power-up sequence assures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. 6 - S2 SECTION 6 Bt431 Application Information Power-up Initialization Changing the Window Size Following a power-up sequence, the Bt431 must be initialized. The following sequence is recommended: To change the size of the cross hair window, it is recommended that the following sequence be used: 1. 2. 3. 4. Write $0000 to addtess pointer register Do 13 write cycles to control registers Write $0000 to addtess pointer register Do 512 write cycles to the cursor RAM Prior to the above sequence, the MPU may perform diagnostic checks on the device, such as checking that the RAM and control registers may be written to and read back. Loading the Cursor RAM When changing the cursor pattern, it is recommended that the following sequence be used to load the cursor RAM: 1. Write $0000 to addtess pointer register 2. Do 512 write cycles to the cursor RAM Moving the Cursor It is recommended that the following sequence be used to update the cursor (x,y) register: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Write $0001 to addtess pointer register Read cursor (x) low Read cursor (x) high Read cursor (y) low Read cursor (y) high Calculate new (x,y) value Write $000 1 to addtess pointer register Write new cursor (x) low Write new cursor (x) high Write new cursor (y) low Write new cursor (y) high The above sequence also applies to updating the window (x,y) register, except $0005 should be written to the addtess pointer register. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Write $0009 to addtess pointer register Read window width low Read window width high Read window height low Read window height high Calculate new window width/height Write $0009 to addtess pointer register Write new window width low Write new window width high Write new window height low Write new window height high Using Multiple Devices Multiple Bt431s may be used to generate more than one cursor, or to generate a multi-color cursor. If using multiple devices to generate more than one cursor, the cursor outputs may be logically gated together, or each Bt431 may interface to a separate overlay input of the RAMDAC. If separate overlay inputs are used, the cursors will be automatically prioritized depending on which overlay is used for each cursor. To generate a multi-color cursor (for example, using two Bt431s to generate a three-color cursor), each Bt431 must interface to a separate overlay input of the RAMDAC. Either a separate cursor (x,y) calculation for each Bt431 may be performed, or the same cursor (x,y) calculation used with the cursor information approptiately offset in the cursor RAM. Inter/acing to the Bt453 and Bt458 Figure 7 illustrates interfacing a single Bt431 to the Bt453 RAMDAC and Figure 8 illustrates interfacing to the Bt458 RAMDAC. Interfacing to the Bt451, Bt454, Bt457, and Bt461/462 RAMDACs are similar to interfacing to the Bt458, due to the multiplexed overlay inputs of these devices. When interfacing to the Bt454, the CLOCK pin of the Bt431 should be connected to the LDOUT pin of the Bt454, and the Bt431 configured for 4: 1 output mUltiplexing. Interfacing to the Bt450, Bt473, Bt475/477, Bt479, and Bt471/476/478 RAMDACs is similar to interfacing to the Bt453. PERIPHERALS 6 - 53 .. Bt431 Application Information (continued) PIXEL DATA FROM FRAME BUFFHR I I PO-P7 OLO BLANK'" SYNC· VIDEO TIMING Bt453 LOGIC CLOCK ~ VSYN~ OLi I HSYNC· a..ocK CURA I Bt431 I MPU DATA BUS MPU ADDRESS BUS MPU CONTROL BUS Figure 7. Interfacing to the Bt453. PIXEL DATA FROM FRAME BUFFHR I I PO-P7(A-E) OLO(A-E) BLANK' VIDEO SYN~ TIMING LOGIC Bt458 I CLOCK LD' GBNERATION I LOGIC I CLOCK CLOCK' I VSYNC' HSYNC· CLOCK OLi (A-E) CUR (A-E) Bt431 MPUDATABUS I MPU ADDRESS BUS MPU CONTROL BUS Figure S. 6 - S4 SECTION 6 Interfacing to the Bt45S. Bt431 Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Symbol Min Typ Max Units vee 4.75 0 5.00 TA 5.25 +70 Volts ·C Symbol Min Typ Max Units 7.0 Volts GND-O.5 VCC+0.5 Volts -55 -65 +125 +150 ·C ·C +175 +150 ·C ·C '!SOL 260 ·C TVSOL 220 ·C Absolute Maximum Ratings Parameter VCC (measured to GND) Voltage on Any Signal Pin* Ambient Operating Temperature Storage Temperature Junction Temperature Ceramic Package Plastic Package Soldering Temperature (5 seconds, 1/4" from pin) Vapor Phase Soldering (1 minute) TA '!S TJ III Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. PERIPHERALS 6 - 55 Bt431 DC Characteristics Parameter Digital Inputs Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Vin = 2.4 V) Digital Outputs (DO-D7) Output High Voltage (lOH = -400 IlA) Output Low Voltage (lOL = 3.2 rnA) 3-state Current Output Capacitance Digital Outputs (CURA-CURE) Output High Voltage (lOH = -400 IlA) Output Low Voltage (lOL = 1.6 mA) 3-state Current Output Capacitance Symbol Min vrn 2.0 GND-O.5 vn. Typ IllI llL CIN Max Units VCC+0.5 0.8 1 -1 Volts Volts IIA IIA pF 7 VOH Volts 2.4 VeL IOZ roUT VOH Volts 10 IIA pF 20 Volts 2.4 VeL IOZ roUT 0.4 20 0.4 Volts 10 IIA pF Test conditions (unless otherwise specified): "Recommended Operating Conditions." Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. 6 - 56 SECTION 6 Bt431 AC Characteristics Parameter Symbol Min Typ Max Units 35 MHz Clock Rate (per I, 4, or 5 pixels) Fmax CO, CI, R/W Setup Time CO, Cl, R/W Hold Time 1 2 10 15 ns ns CE*LowTime CE* High Time CE* Asserted to Data Bus Driven CE* Asserted to Data Yalid CE* Negated to Data Bus 3-Stated 3 4 5 6 7 50 25 6 ns ns ns ns ns Write Data Setup Time Write Data Hold Time 8 9 35 4 YSYNC*, HSYNC* Setup Time YSYNC*, HSYNC* Hold Time YSYNC*, HSYNC* Low Time YSYNC*, HSYNC* High Time 10 11 10 5 4 4 ns ns Clocks Clocks Clock Cycle Time Clock Pulse Width High Clock Pulse Width Low 12 28.6 10 10 ns ns ns Pipeline Delay Output Delay Three-State Disable Time Three-State Enable Time 15 16 17 18 5 20 15 15 Clocks ns ns ns YCC Supply Current* ICC 100 rnA 13 14 100 15 ns ns 2.5 Test conditions (unless otherwise specified): "Recommended Operating Conditions." TTL input values are 0-3 y, with input rise/fall times ~ 4 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. CURA-CURE output load ~ 10 pF, DO-D7 output load ~ 130 pF. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 Y. *At Fmax. ICC (typ) at YAA = 5.0 Y. ICC (max) at YAA = 5.25 Y. Ordering Information Ambient Temperature Range Model Number Package Bt431KC 24-pin 0.3" CERDIP 0° to +70·C Bt431KPI 28-pin Plastic I-Lead O· to +70· C PERIPHERALS 6 - 57 Bt431 Timing Waveforms L RIW, co, 1 ~ VALID C1 3 CE· J 4 6 s I V DO - D7 (READ) DATA our (WW = 1) ........ 1 DO - D7 (WRITll) ~I R ./ DATA IN(WW= 0) 8 I i-L MPU Read/Write Timing. USYNC". VSYNC· C\JR(A-I!) H~ O =xy c----- 00· Video Input/Output Timing. 6 - 58 SECTION 6 DATA Bt431 Revision History Datasheet Revision Change from Previous Revision G Correct PLCC pinout. H Update Application Infonnation Section to include interfacing to new RAMDACs. I Update three-state currents in DC section to be 10 11A. J Expanded ESD/Latchup infonnation. .. PERIPHERALS 6 - S9 Bt438 Distinguishing Features Customer Benefits • • • • • • • • • • 250 MHz Operation Differential ECL Clock Generation Divide by 3, 4, 5, or 8 of the Clock Divide by 2 and 4 of the Load Resets Pipeline Delay of the RAMDAC 1.2 V Voltage Reference Output Single +5 V Power Supply 20-pin DIP or 28-pin PLCC Package • Typical Power Dissipation: 325 mW Reduces PC Board Area Simplifies RAMDAC Design Cost Reduction over Discretes Increases System Reliability Related Products Product Description • Bt439 The Bt438 is a clock generator for the high-speed Brooktree CMOS RAMDACs. It interfaces a 10KH ECL oscillator operating from a single +5 V supply to the RAMDAC, generating the necessary clock and control signals. The clock output may be divided by three, four, five, or eight to generate the load signal. The load signal is also divided by two and four for clocking video timing logic, etc. Functional Block Diagram VREF VCC GND RESET' CLOCK CLOCK' OSC DSC' 1---lT-;===~:===!.-+- lOA. LDB DMDE i - - - - - t _ LD/2 BY 3.4.5.8 CLOCK L..--.,_--' 1..------1 ~'6IJ:gL DIYO. DIYl Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121 (619) 452-7580 • (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 lA38001 Rev. K 250 MHz Clock Generator Chip for CMOS RAMDACs™ we, lOD A second load signal may be synchronously or asynchronously controlled to enable starting and stopping the clocking of the video DRAMs. The B t438 also optionally configures the pipeline delay of the RAMDAC to a fixed pipeline delay. An on-chip 1.2 V voltage reference is also provided, and may be used to provide the reference voltage for up to four RAMDACs. ENABLE ENABLE (5) (A) 6 - 61 Broddree® III Bt438 Circuit Description The Bt438 is designed to interface to a IOKH ECL crystal oscillator and generate the clock signals required by the RAMDACs. The OSC and OSC* inputs are designed to interface to a IOKH ECL oscillator operating from a single +5 V power supply. The CLOCK and CLOCK* outputs are designed to interface directly to the CLOCK and CLOCK* inputs of the RAMDACs. The output levels are compatible with IOKH ECL logic operating from a single +5 V power supply. DIVO and DIVI are used to specify whether the pixel clock is to be divided by three, four, five, or eight to generate the LDA and LDB signals. LDA is also divided by two and four to generate the LD/2 and LD/4 signals, respectively. ENABLE (S) is internally synchronized to LDA and may be used to synchronously start and stop the LDC and LDD outputs. While ENABLE (S) is a logical zero, LDC and LDD will be a logical zero. While both ENABLE (S) and ENABLE (A) are a logical one, LDC and LDD will be free-running and in phase with LDA and LDB. This architecture allows the shift registers of the video DRAMs to be optionally non-clocked during the retrace intervals. Figure I illustrates the ENABLE implementation within the Bt438, while Figure 2 shows the load output timing. The RESET* input is designed to enable the Bt438 to set the pipeline delay of the RAMDACs to a specified number of clock cycles (the exact number is dependent on the RAMDAC). Following the first rising edge of LD/4 after the rising edge of RESET·, the CLOCK and CLOCK* outputs are stopped in the high and low states, respectively. At the next rising edge of LD/4, the CLOCK and CLOCK* outputs are restarted. Figure 3 shows the operation of the RESET* input. The Bt438 also generates a 1.2 V (typical) voltage reference, which may be used to drive the VREF input of up to four RAMDACs. ENABLE (A) is used to asynchronously start and stop the LDC and LDD outputs. While ENABLE (A) is a logical zero, the LDC and LDD outputs will remain in the state they were when the ENABLE (A) input went to a logical zero. Note that both ENABLE (A) and ENABLE (S) should not be a logical zero simultaneously. If this occurs, synchronous control of LDC and LDD, via ENABLE (S), is not guaranteed. ---------.~----------.-----------__~illA LIl BNABLil (s) - - - - - 1 D BNABLIl(A) Q LOC. illD --------LP-----' Figure 1. 6 - 62 D Q SECTION 6 ENABLE Control Implementation. Bt438 Circuit Description (continued) IDA,IDB L ID/4 ENABlll (S), ENABlll (A) =I ~ IIIIIII! 1111111 IDC, LDD IDC, LDD Figure 2. '=-~=; Load Output Timing. J1MMMflfU1Il ID/4r~JLJL RESEr" a=K a=K" 11111111111111 SLMfU LJ1J1 -UWLn fUU Figure 3. RESET· Timing. PERIPHERALS 6 - 63 Broddree® Bt438 Pin Descriptions Pin Name Description VREF Voltage reference output. This output provides a 1.2 V (typical) reference, and may be used to drive the VREF input of up to four RAMDACs. OSC,OSC* Differential ECL oscillator inputs. These inputs are designed to interface to a lOKH ECL crystal oscillator operating from a single +5 V supply. CLOCK, CLOCK* Differential clock outputs. These outputs connect directly to the CLOCK and CLOCK* inputs of the RAMDAC. The clock rate is equal to the OSC rate, and they are capable of driving up to four RAMDACs directly. The output levels are equivalent to lOKH ECL logic operating from a single +5 V supply. DIVO, DIV! Divide control inputs (TIL compatible). These inputs specify the division factor (3, 4, 5, or 8) for the generation of the LDA and LDB signals, as specified in below: DIVl DIVO Division Factor Clock Cycles Low Clock Cycles High 0 0 1 1 0 1 0 1 +3 1 2 2 4 2 2 +4 +5 +8 3 4 LDA,LDB Load outputs (TIL compatible). LDA and LDB are generated by dividing CLOCK by three, four, five, or eight as determined by the DIVO and DIVl inputs. Each output may drive up to 20 video DRAMs without external buffering. LD/2 Load output (TIL compatible). LD/2 is generated by dividing LDA by two. This output may drive up to 20 video DRAMs without external buffering. LD/4 Load output (TIL compatible). LD/4 is generated by dividing LDA by four. This output may drive up to 20 video DRAMs without external buffering. LDC,LDD Load outputs (TTL compatible). When both ENABLE inputs are a logical one, these outputs have the same timing as the LDA and LDB outputs. Each output may drive up to 20 video DRAMs without external buffering. ENABI..E(S) Synchronous load enable control input (TIL compatible). ENABLE (S) is internally synchronized to LDA and is used to synchronously start and stop the LDC and LDD outputs. While ENABLE (S) is a logical zero, LDC and LDD will be a logical zero. While both ENABLE (A) and ENABLE (S) are a logical one, LDC and LDD are free-running and in phase with the LDA and LDB outputs. ENABI..E(A) Asynchronous load enable control input (TTL compatible). ENABLE (A) is used to asynchronously start and stop the LDC and LDD outputs. While ENABLE (A) is a logical zero, the LDC and LDD outputs will remain in the state they were when the ENABLE (A) input went to a logical zero. While both ENABLE (A) and ENABLE (S) are a logical one, LDC and LDD are free-running and in phase with the LDA and LDB outputs. Care should be taken to avoid glitches on this asynchronous input. 6 • 64 SECTION 6 Bt438 Pin Descriptions (continued) Pin Name Description RESET* Reset control input (TTL compatible). Following the first rising edge of LD/4 after the rising edge of RESET·, CLOCK and CLOCK· are stopped in the high and low states, respectively. At the next rising edge of LD/4, the CLOCK and CLOCK· outputs are set to be free-running. Care must be taken to avoid glitches on this edge-triggered input vee Device power. All VCC pins must be connected. GND Device ground. All GND pins must be connected. 28-pin Plastic J-Lead (PLCC) Package 20-pin DIP Package DIVO BNABLIl(S) < 9 9'" ~ ~ ~ til iii lQ ~ ~ ~ 125 MHZ. TYP 220 OHM FULL DOWN ONLY. 220 +sv a.ocK CLOCK 14 330 +SV OSC MONITOR PRODUCTS RAMDAC 220 510 9706 a.ocK' a.ocK' 330 Bt438 OSC' 510 IDA LD' IK VRHF Figure 4. 6 - 66 SECTION 6 VRHF Interfacing to a Differential Crystal Oscillator. Bt438 Application Information (continued) NOTI!, a.OCK AND CLOCK"lllRMINAll0N AT > 125 MHZ, TYP210 OHM PUlL OOWN ONLY. 220 CLOCK +SV CLOCK 330 +SV +SV +SV OSC MONITOR PRODUCTS 210 RAMDAC 210 1-8_~~_1""'~_-' CLOCK" 9700 330 CLOCK" 330 Bt438 OSC· LDA LD" IK VREF VREF VAA Figure 5. Interfacing to a Single-Ended Crystal Oscillator. NOTI!, a.OCK AND CLOCK" TERMINATION AT > 125 MHZ. TYP 210 OHM PULL OOWN ONLY. +SV 220 CLOCK CLOCK +sv 330 +SV OSC RAMDAC 210 a.OCK" TTL CLOCK CLOCK" 330 Bt438 OSC· LDA LD" IK VREF VREF YAA Figure 6. Interfacing to a TTL Clock. PERIPHERALS 6 - 67 Bt438 Recommended Operating Conditions Parameter Symbol Min Typ Max Units Power Supply VCC 4.75 5.00 5.25 Volts Ambient Operating Temperature TA 0 +70 ·C OSC/OSC* Duty Cycle % 40 Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. Absolute Maximum Ratings Parameter Max Units 7.0 Volts VCC+0.5 Volts 30 rnA +125 +150 ·C ·C +175 +150 ·C ·C TSOL 260 ·C TVSOL 220 ·C Symbol Min VCC (measured to GND) Voltage on any Pin GND-O.5 CLOCK, CLOCK* Output Current Ambient Operating Temperature Storage Temperature Junction Temperature Ceramic Package Plastic Package Soldering Temperature (5 seconds, 1/4" from pin) Vapor Phase Soldering (1 minute) AirFlow TA TS -55 -65 Typ TJ 0 l.f.p.m. Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operatiOIl of the device at these or any other conditions above those listed in the operational sections of this specification is~ot implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6 ·68 SECTION 6 BnxKtree~ Bt438 DC Characteristics Parameter TIL Inputs Input High Voltage (other pins) DIVO,DIVI Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Yin = 2.4 V) ECL Inputs (at 25° C.) Input High Voltage Input Low Voltage Input High Current (Vin = 4.0 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Yin = 4.0 V) Load Outputs Output High Voltage (lOH=-2rnA) Output Low Voltage (lOL =20 rnA) Output Capacitance Clock Outputs (at 25° C) Differential Output Voltage Output Capacitance Voltage Reference Output Voltage (Bt438 Rev. C)* Output Current VCC Supply Current*· Symbol Min VIH 2.0 2.2 GND-O.5 VlL IllI TIL CIN VIH VlL VCC-l.l GND-O.5 rour Units VCC + 0.5 VCC+0.5 0.8 10 -0.7 Volts Volts Volts VCC-O.8 VCC-1.5 15 15 Volts Volts IIA rnA pF IIA IIA pF 4 Volts 2.4 V 4", pulldowns at the B t439 as well as balance lined termination at the palette are recommended. For striplines of Zo characteristic impedance separated by > 2d dielectric spacing, a balanced termination of 2Zo is appropriate. Due to the limited drive capability of the PLL output of the RAMDACs, the buffer circuitry should be located as close as possible to the RAMDAC r~~~~~------------' ! I v~~____~ I I I CLK/l CLK/l" 3VP1' :!..5·4D5 PROPAGATION DELAY +SV CUXXr---------~~--~-i +SV .. 220 PRODucrs RAMDAC of PI] ~CI! CUXX 00 330 I'D CUXX"r---~~--------~-i CUXX" Bt439 '---------IOSC" +SV [J)I-------------------i [J)" IK VREP I'lL 50 OHM TRANSMISSION LINE IF 12 OR MORE INCHES LONG ¢ 510 OHM RESISTOR NEEDED IF THERE ARE NO INTERNAL PUll. DOWNS IN Oscn.LATOR. ¢¢ OPTIONAL BALANCED TERMINATION FOR IDGH IMPEDANCE DIFFERENTIAL LINES> 4 INCHES; OMIT 220 OHM PUlL UP IF USED. ¢¢¢ CLOCK AND CLOCK" TERMINATION AT > 125 MHz. TYP 220 OHM PI) ONLY. Zo - UNBALANCED STRIPLINE IMPEDANCE >1- PD/6. Figure 3. Interfacing to a Differential Crystal Oscillator. PERIPHERALS 6 - 79 Bt439 Application Information (continued) 000220 a.ocK +W a.ocK 330 +W 14 PRODucrs 97011 RAMDAC 000220 MONITOR a.oat. 330 a.oat. 330 Bt439 lDAl----------lID· 111: PlL I'lL 1..-_ _ _---..1 +W so OHM STRIPLINE 300 IF 12 OR MORE INCHES LONG 00 OPTIONAL BALANCED TERMINATION FOR CLOCK UNES >4 INCHES. Zo 000 CLOCK AND CLOCKO TERMINATION AT > 125 MHz.TYP 220 OHMPD ONLY. Figure 4. UNBALANCEDSTRIPUNEIMPEDANCE >/m PD/6 Inter/acing to a Single-Ended Crystal Oscillator. ~1I:1--------+--la.ocK 330 RAMDAC a.oat.I----.....-----I~II:. 330 lDA1 - - - - - - - - - - 1ID· 111: I'LL I'lL moo ~ UNE < 12 • LENGTII PIL 200 00 000 OPTIONAL BALANCED TERMINATION FOR CLOCK UNES >4 INCHES. Zo - UNBALANCEDSTR1PLINEIMPEDANCE >/= POI6 CLOCK AND CLOCK· TERMINATION AT > 125 MHz, TYP 220 OHM PO ONLY. Figure 5. 6 - 80 1 SECTION 6 Inter/acing to a TTL Clock < 80 MHz. Bt439 Recommended Operating Conditions Parameter Symbol Min Typ Max Units Power Supply vee 4.75 5.00 5.25 Volts Ambient Operating Temperature -Still Air TA 0 +70 °C OSC/OSC· Duty Cycle % 40 Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 50 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. Absolute Maximum Ratings Parameter Max Units 7.0 Volts VCC+0.5 Volts 30 rnA TJ +125 +150 +175 °C °C °C TSOL 260 °C Symbol Min VCC (measured to GND) Voltage on any Pin GND-O.5 CLOCK, CLOCK· Output Current Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds. 1/4" from pin) Airflow TA TS -55 -65 Typ .. l.f.p.m. 50 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PERIPHERALS 6·81 Bt439 DC Characteristics Parameter TIL Inputs Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Yin = 2.4 V) ECLInputs Input High Voltage Input Low Voltage Input High Current (Vin = 4.0 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = I MHz, Yin = 4.0 V) Load Outputs Output High Voltage Symbol Min V1H 2.0 GND-O.5 VIL IIH IlL VIL IIH IlL Units VCC+0.5 O.B 10 Volts Volts VCC-l.l VCC-2 -15 4 0 10 IlA rnA pF 10 CIN VOH Max -0.7 CIN V1H Typ VCC-O.B VCC-1.5 15 Volts Volts IlA IlA pF Volts 2.4 (lOH~2mA) Output Low Voltage (lOL=20rnA) Output Capacitance Clock Outputs Differential Output Voltage Output Capacitance Voltage Reference Output Voltage@ IREF = -100 IlA PLLInputs Input High Voltage Input Low Voltage Input High Current (Vin = 1.2 V) Input Low Current (Vin = 0.5 V) Input Capacitance VCC Supply Current* VeL ~VOUT O.B VREF 1.17 V1H 1.5 GND-O.5 VIL IIH IlL ICC 10 pF 10 Volts pF .6 mUT -700 Volts 1.235 0 -IBO 10 275 1.31 Volts VCC+0.5 0.4 10 Volts Volts IlA IlA pF 300 rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions." CLOCK, CLOCK*, and CLK/2 outputs have 50 n to VCC-2 V. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Measured without 50 ohms to VCC-2 volts on CLOCK, CLOCK*, and CLKJ2. At VCC = 5.25 V. The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 50 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. 6 - 82 SECTION 6 Bt439 AC Characteristics Parameter Symbol Min OSC, OSC· Clock Rate (note 1) Fmax LD Output Delay (note 2) LD Pulse Width LD to LD/2 Output Skew (note 3) LD to LD/4 Output Skew (note 3) CLK/2 Output Delay 1 2 3 RESEr. Active Low Time RESEr· Setup Time 4 5 15 10 Alignment Span Residual Alignment Error (note 4) 6 5 6 9 0 0 Typ Max Units 200 MHz 10 12 1.5 1.5 2 3 3 4 ns ns ns ns ns ns ns 1.5 2 ns ns Test conditions (unless otherwise specified): "Recommended Operating Conditions". CLOCK, CLOCK·, and CLK/2 outputs have 50 Q to YCC-2 Y. TTL input values are 0--3 Y, with input rise/fall times S 4 ns, measured between 10% and 90% points. ECL input values are (YCC-O.9) to (YCC-1.6) Y, with input rise/fall times SIns, measured between 20% and 80% points. Timing reference points at 50% for inputs and outputs. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 Y. Note 1: Note 2: Note 3: Note 4: + 3 Mode LD outputs valid only to 100 MHz without significant distortion. Output load = 50 pF. Derate 1 ns for each additional 50 pF loading. Load outputs equally loaded with 50 pF. Unequal loading may result in additional output skew. Maximum deviation of any two dependent PLL inputs after alignment sequence (PLL inputs within span before alignment). Timing Waveforms .. -1-5 osc RESET" BARLIEST PLLX LATEST PLLY CLK/2 ID ID{4 ID/2 __~x~__________~x~________ Figure 6. Input/Output Timing. PERIPHERALS 6·83 Bt439 Ordering Information Model Number Package Bt439KC 28-pin 0.6" CERDIP Ambient Temperature Range 0" to +70· C Revision History Datasheet Revision Change from Previous Revision E Thermal equilibrium notes added to Recommended Operating Conditions and DC Characteristics. F Clarified reset requirements, changed VREF maximum, revised PLL feedback circuitry, reduced ILL maximum, added required airflow. Datasheet Revision B 6·84 Changed pixel alignment sequence for longer period of deskew. SECTION 6 Bt501 Bt502 Distinguishing Features Benefits lOKH or lOOK ECL Compatible Optional Single +5 V Operation • Separate TIL and ECL Supply Pins Three-Statable TTL Pins TIL-Compatible Control Inputs 24-pin 0.3" DIP Package Typical Power Dissipation: 800 mW • • • • • Flexible Power Supply Reduced Component Count Simplifies PCB Layout Reduces PCB Interconnect Low Bus Loading EeL / TTL Octal Transceiver and Translator Product Description The Bt501 and Bt502 are octal ECL/TTL bidirectional transceivers and translators. The BtS01 is 10KH ECL compatible. and the BtS02 is lOOK ECL compatible. The direction and output enable control inputs are TTL compatible to simplify interfacing to a standard MPU. Functional Block Diagram Both devices provide a bidirectional interface between TTL signals and ECL signals. The ECL input/output signals may be generated from normal ECL, single +5 V. or split ECL supplies. 8 TIL(OO - D7) --+......,~-~ 17'......-+-_ ECL(OO - D7) DE" DlR TIL vee TIL GND Brooktree Corporation 9950 Barnes Canyon Rd. San Diego. CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 L501001 Rev. F ECL VEE ECL(DO) TlL(D0) ECL(Dl) TlL(Dl) ECL(D2) TlL(D2) ECL(D3) TlL(D3) DIR ECL vee 6 - 8S OE" ECLVCC '\"IL vee ECLVCC '\"ILGNO ECLVEE '\"ILGNO ECL(D4) TlL(D4) ECL(DS) TlL(DS) ECL(D6) TlL(D6) ECL(D7) TlL(D7) .. BtSOl/S02 Circuit Description Nominal Voltages Applied Supply Pin Single Supply System Dual Supply System Split ECL Supply System +5.0 V OV +5.0 V OV +5.0 V OV OV -5.2 V +5.0 V OV +2.0V -3.2 V TILVCC TILGND EeLVCC ECLVEE BtSOl Supply Operation. Nominal Voltages Applied Supply Pin Single Supply System Dual Supply System Split ECL Supply System +5.0 V OV +5.0 V OV +5.0 V OV OV -4.5 V +5.0 V OV +2.0V -2.5 V TILVCC TILGND EeLVCC ECLVEE BtS02 Supply Operation. Note: The TIL (00-07), DIR, and OE* pins are TIL compatible regardless of the ECL power supply parameters. Changing the ECL power supply parameters affects the threshold levels of only the ECL (00-07) pins. OlR OE* Function 0 1 0 0 1 TIL (00-07) --> EeL (00-07) ECL (00-07) --> TIL (00-07) TIL (00-07) three-stated, ECL (00-07) =0 x Control Truth Table. 6 ·86 SECTION 6 BtSOl/S02 Bt501-Recommended Operating Conditions Parameter TIL Device GrOlmd EeL Device Ground TIL Power Supply ECL Power Supply Ambient Operating Temperature Symbol Min Typ Max Units TILGND EeLVCC TTLVCC 0 0 +4.75 ECLVFE TA -4.9 0 0 0 +5.0 -5.2 0 0 +5.25 -5.5 +70 Volts Volts Volts Volts ·C Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. Bt501-Absolute Maximum Ratings Parameter Symbol Min EeL VEE (measured to ECL VCC) TIL VCC (measured to TIL GND) Typ Max Units -8.0 +7.0 Volts Volts Voltage on Any ECL Pin EeLVCC ECLVEE Volts Voltage on Any TIL Pin TILGND TILVCC +0.5 Volts -50 rnA -0.5 ECL(DO-D7) Output Current TIL(DO-D7) Short Circuit Output Current Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, 1/4" from pin) lOS -50 -150 rnA TA -55 -65 +125 +150 +175 ·C ·C ·C 260 ·C TS TJ TSOL Note: Stresses above those listed under "Absolute Maxintum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not intplied. Exposure to absolute maxintum rating conditions for extended periods may affect device reliability. PERIPHERALS 6 - 87 BtSOl/S02 Bt501-ECL DC Characteristics Parameter Symbol TA(OC) Min Input High Voltage* VIH 0 +25 +70 Input Low Voltage* VIL Output High Voltage* Typ Max Units -1170 -1130 -1070 -840 -810 -735 mV mV mV 0 +25 +70 -1950 -1950 -1950 -1480 -1480 -1450 mV mV mV VOH 0 +25 +70 -1020 -980 -920 -840 -810 -735 mV mV mV Output Low Voltage* VOL 0 +25 +70 -1950 -1950 -1950 -1630 -1630 -1600 mV mV mV Input High Current (Vin =VIHmax) IIH 0 +25 +70 10 10 10 ~ ~ ~ EeL VEE Supply Current lEE 0 +25 +70 75 75 75 rnA rnA rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with ECL (DO-D7) loading of 50 n to -2.0 V. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e.,5 V. *Relative to ECL VCC. The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. 6 - 88 SECTION 6 BtSOl/S02 BtS01-TTL DC Characteristics Parameter Symbol Min Input High Voltage* VlH Input Low Voltage* VIL Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Output High Voltage* (IOH = -2.0 rnA) Output Low Voltage* (IOL=20mA) VOH Three-State Output Current Vout = VOHmin Vout=VOLmax Ial TTL VCC Supply Current ICC Max Units 2.0 TILVa:. +0.5 Volts TILGND -0.5 0.8 Volts IIH 70 ~ In.. -0.7 rnA VOL Typ Volts 2.5 0.5 Volts 10 -10 ~ ~ 85 rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with ECL (00-07) loading of SO n to -2.0 V. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Relative to TTL GND. .. PERIPHERALS 6·89 BtSOliS02 Bt501-AC Characteristics Parameter Symbol Min TTL --> ECL Propagation Delay ECL --> TTL Propagation Delay 1 2 2 5 ECL (00--07) Enable Time ECL (00--07) Disable Time* 3 4 TTL (00-07) Enable Time TTL (00--07) Disable Time* 5 6 Typ Max Units 7 11 ns ns 7 7 13 13 ns ns 4 6 10 12 ns ns Test conditions (unless otherwise specified): "Recommended Operating Conditions" with ECL (00-07) loading of 50 n to -2.0 V. TTL input values are 0--3 V, with input rise/fall times;!; 4 ns, measured between the 10% and 90% points. ECL input values are -0.80 to -2.0 V, with input rise/fall times;!; 2 ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Subject to capacitive loading. DIR I ________ TIL_-_>_ETIL OE" "ITL(DO·D7) ECL(DO-D7) InpullOulpul Timing. 6 • 90 SECTION 6 Bt501/502 Bt502-Recommended Operating Conditions Parameter TTL Device Ground ECL Device Ground TTL Power Supply ECL Power Supply Ambient Operating Temperature Symbol Min Typ Max Units TILGND ECLVCC TILVCC ECLVFE TA 0 0 +4.75 -4.2 0 0 0 +5.0 -4.5 0 0 +5.25 -4.8 +85 Volts Volts Volts Volts °C Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. Bt502-Absolute Maximum Ratings Parameter Symbol Min ECL VEE (measured to ECL VCC) TTL VCC (measlD'ed to TTL GND) Typ Max Units -8.0 +7.0 Volts Volts Voltage on Any ECL Pin ECLVCC ECLVEE Volts Voltage on Any TTL Pin TILGND -0.5 TILVCC +0.5 Volts -50 rnA ECL (00-07) Output Current TTL (00-07) Short Circuit Output Current lOS -50 -150 rnA Ambient Operating Temperature Storage Temperature Junction Temperature TA TS TJ -55 -65 +125 +150 +175 °C °C °C 260 °C Soldering Temperature (5 seconds, 1/4" from pin) TSOL .. Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PERIPHERALS 6 • 91 BtS01/S02 Bt502-ECL DC Characteristics Parameter Symbol Min Input High Voltage" Input Low Voltage* VIH VlL -1165 -1810 Output High Voltage" Output Low Voltage* VOH VOL -1025 -1810 Typ -955 -1705 Max Units -880 -1475 mV mV -880 -1620 mV mV Input High Current (Vin = VlH max) IIH 10 J.IA ECL VEE Supply Current IEE 75 rnA Max Units Bt502-TTL DC Characteristics Parameter Symbol Min Input High Voltage .... VIH 2.0 TILVCC +0.5 Volts Input Low Voltage"* VlL TILGND -0.5 0.8 Volts Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) IIH 70 J.IA IlL -0.7 rnA Output High Voltage"'* (lOH = -2.0 rnA) Output Low Voltage** (lOL=20mA) VOH Three-State Output Current Vout =VOHmin Vout =VOLmax IOZ TTL VCC Supply Current ICC VOL Typ Volts 2.5 0.5 Volts 10 -10 J.IA J.IA 85 rnA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with ECL (00-07) loading of 50 Q to -2.0 V. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. *Relative to ECL VCC. "'''Relative to TTL GND. The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is 'established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. 6 - 92 SECTION 6 BtSOl/S02 Bt502-AC Characteristics Parameter Symbol Min TTL --> ECL Propagation Delay* ECL --> TTL Propagation Delay* 1 2 ECL (00-D7) Enable Time ECL (OO-D7) Disable Time* TTL(OO-D7) Enable Time TTL(DO-D7) Disable Time* Typ Max Units 0.5 2 7 11 ns ns 3 4 2 3 11 11 ns ns 5 6 0.5 0.5 6.5 6.5 ns ns Test conditions (unless otherwise specified): "Recommended Operating Conditions" with ECL(DO-D7) loading of 50 n to -2.0 V. TTL input values are 0-3 V, with input rise/fall times S 4 ns, measured between the 10% and 90% points. ECL input values are -0.80 to -2.0 V, with input rise/fall times S 2 ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. Ordering Information Ambient Temperature Range Model Number Compatibility Package Bt501KC 10KHECL 24-pin 0.3" CERDIP 00 to +700 C Bt502KC lOOKECL 24-pin 0.3" CERDIP 00 to +85 0 C DIR ________ TIL_-_>_ECL __ III -..J~-->TIL OE* TIL(DO-D7) ECL(DO-D7) Input/Ouput Timing. PERIPHERALS 6 • 93 Preliminary Information This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. Distinguishing Features Applications • • • • • • • • • • • • • • 125 MHz Maximum Trigger Rate Less than ±1 LSB Timing Accuracy 15 ps Delay Resolution (4 ns Span) Extendable Delay Span to 40 ns Differential Trigger Inputs 10KH ECL Compatible Monolithic Construction 28-pin Plastic J-Lead (PLCC) Package Typical Power Dissipation: 910 mW Automatic Test Equipment Precision Timing Verniers Arbitrary Waveform Generators Multiple Phase Clock Generators Computer Backplane Timing 125 MHz 10KH EeL Compatible Dynamically Programmed Timing Edge Vernier Product Description Related Products The Bt604 is a Dynamically Programmed Timing Edge Vernier, whose time delay is dynamically loaded upon each trigger of the circuit. In response to a trigger pulse, the Bt604 outputs a pulse of fixed width a programmable delay time later. • Bt605 Functional Block Diagram VBB Bt604 VEE With the delay span set to 4 ns, the Bt604 features 15 ps of resolution (255 steps). The delay span is externally adjusted and is set in the range of 4 ns to 40 ns by IEXT. vee The device is 10KH ECL compatible with ECL inputs and has a differential ECL input trigger and output pulse. 8 DO - D7 -f-:-,'--ooi LATCH 8 .....,..'--~ ')---1 ~---+-- OUT' r-t--I-- TRIG TRIO' CE' OUT COMPI -1r--q COMP2 The Bt604 also meets the need for programmable time delays in numerous electronic instruments that perform signal modulation, processing, and generation. I EXT Brooktree Corporation 9950 Barnes Canyon Rd. San Diego, CA 92121-2790 (619) 452-7580· (800) VIDEO IC TLX: 383 596 • FAX: (619) 452-1249 L60400l Rev. F In applications for Automatic Test Equipment (ATE), the Bt604 forms the critical component in providing precise timing edges having fine resolution and excellent edge placement accuracy, and is suitable for use in testers featuring timing changes "on-the-fly." 6 • 95 III Bt604 Circuit Description As illustrated in the block diagram, the Bt604 contains an 8-bit D/A converter, a linear ramp generator, and a comparator. Functional Operation Referring to Figures 1 and 2, if CE* is a logical zero, the differential input trigger (TRIG, TRIG*) initiates a linear ramp on the rising edge of TRIG and latches the DO-D7 input data which sets the DAC output voltage. The comparator detects when the ramp reaches the DAC's programmed value, whereupon it initiates an output pulse of fixed width and resets the ramp. Upon resetting the ramp, the input data latch is made transparent, enabling 00-D7 to reprogram the DAC and permitting another trigger of the Bt604. Delay Calculations Referring to Figure 2, the output pulse delay consists of a minimum output delay (Tmin) and a programmable output delay (Tprog). For DO-D7 equal to $00 the output delay will be Tmin and for $FF the output delay will be Tmax. The span of the delay range is: Tspan = Tmax - Tmin The output pulse delays are adjustable and are set by IEXT current flow through pin 12. Figure 3 shows the relationships Tspan vs. IEXT and Tspan vs. Tmin. The following equations apply to Figure 3: Tmin (max) = Tspan * 0.217 + 2.7 Tmin (min) = Tspan * 0.187 + 1.6 Tmin (max) - Tmin (min) =Tspan * 0.03 + 1.1 Conditions for Optimum Performance The timing vernier is a mixed signal device and to obtain the maximum accuracy and stability over frequency there are specific conditions required. The following recommendations are for maintaining the lowest linearity errors and minimizing the absolute timing variations over frequency. This product requires special attention to proper layout techniques to achieve correct operations. Before beginning PCB layout, please reference the ECL layout techniques in Bt604160S1606 Evaluation Module Operation and Measurements (AN-I7), found in Brooktree's 1990 Applications Handbook. Do not expect optimum performance when operating the device in a socket. Lead inductance, transmission line discontinuities and restricted air flow attributable to the use of a socket will degrade performance. A transverse air flow of 400 linear feet per minute is very important when considering error sources in the magnitude of tens of picoseconds. The ferrite chip bead selected for use with this device is critical. Use only the bead recommended. It is very important that this bead be mounted as close as possible to the VEE(l) power pins connecting the device to the power plane as illustrated in Figure 4. Connecting the decoupling capacitors directly to the VEE(I) pins will result in unstable operation. Note that all components must be placed as close to the pins as possible, and that all VCC pins must be connected to gether. The data set-up time for trigger of the device should be extended to 5 ns for on-the-fly applications. This will insure the best dynamic performance when making full-scale transitions from code $FF to $00, which is when the worst case settling time conditions occur. Referring to Figure 4: IEXT =(VEXT + 1.25 V) / (REXT + 26 Q) Output Pulse Spacing Consecutive output pulses must be spaced no less than 8 ns apart. A constant trigger pulse width should be maintained to achieve the best absolute time performance over frequency. A trigger pulse width of Tmin - 500 ps is required to keep the falling edge of the trigger pulse width from occurring during the ramp. TRIG DO-D7, CE" our Figure 1. 6 • 96 SECTION 6 Input/Output Timing. Bt604 Circuit Description (continued) VOLTAGE DAC [ output range example max ........................................................................................................ . ~------~--------~-------+---------Tmin __-TIME(m) Tprog Tmax TRIG ~ OUT Figure 2. Linear Ramp and Output Pulse Timing. Tmln Variations vs. Tspan lex! (pA) ~OO".,,,~rT~~~rT,,' 2200H-HH-H-H!+H-HH-H-H +. -. ·++·t·· . ··t·· . ··t·· .+....+- 2000 i i ! :: ::~::: ::ri:f ::f :::I::·l:: J: +. +. i..... ··i··i··t·· ... 1400 .. ··1·· ... ··1·· 1200+++iHj +-i+i-HH-H-HH-H-H 1: :I: ::,~l1: .:.:1: ':':1: t::: T: 2.5 4 2.0 2 1.5 i ~ i· 400 200~-H~~-H~~-H~~~ 4 8 12 16 20 ~ 28 32 36 40 Tspan(ns) Figure 3. 10 15 20 25 30 Topen (nonoOllCondo) 35 40 Typical Output Delays. PERIPHERALS 6 • 97 Bt604 Circuit Description (continued) Bt604 .S.2V C1 GROUND I EXT ---2.- RElIT t-----'V'Ir-- ZO=50 VElIT ZO=50 TRIG· -2V ·2V ZO=50 50 ZO=50 50 TRIG· -2V ·2V 50 50 ALTERNATE 0U11'UT LOADING: 50 SCOPB INPIIT OUT,OUf" -4V Location Description CI-C4 11 0.1 JlF ceramic capacitor ferrite chip bead 1% metal film resistor (selected for proper Tspan) REXT Vendor Part Nwnber Erie RPE1l2Z5UI04M50V TDK HF70ACB322513 or TDK CB301210 Dale CMF-55C Note: The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the Bt604. All devices should be as close as possible to the Bt604. Figure 4. 6 • 98 SECTION 6 Typical Connection Diagram and Parts List. Bt604 Pin Descriptions Pin Name Description DO-D7 Data input pins (ECL compatible). On the rising edge of TRIG, a ramp is initiated whereupon DO-D7 are latched into the device. DO is the LSB. These inputs specify the amount of delay from the rising edge of TRIG to the output pulse. See Figure 1. CE* Chip enable input (ECL compatible). CE* must be a logical zero on the rising edge of the TRIG to enable the device to respond to the trigger. If CE* is floating, the trigger will always be enabled. See Figure 1. TRlG,TRlG* Differential trigger inputs (ECL compatible). The rising edge of TRIG is used to trigger the delay cycle if CE* is a logical zero. If CE* is a logical one, no operation occurs. It is recommended that triggering be performed using differential inputs. OUf,OUf* Differential outputs (ECL compatible). !EXT Current reference pin. The amount of current sourced into this pin determines the span of output delay. The voltage at IEXT is typically -1.25 V. CaMPI, COMP2 Compensation pins. A 0.1 ~F ceramic capacitor must be connected between CaMPI and VEE(O) and also COMP2 and VEE(O). See Figure 4. VEE Device power. All VEE pins must be connected. Warning: It Is important that a ferrite chip bead be used to connect the VEE(l) power pins to the power plane as Illustrated In Figure 4. Connecting the decoupIlng capacitors directly to the VEE(l) pins will result in unstable operation. vee Device ground. All VCC pins must be connected together. VBB -1.36 V (typical) output. III DO 18 N/C 01 17 roMP2 02 16 rn* 03 IS roMPI D4 14 N/C OS 13 VBB D6 12 IEXT Note: N/C pins may be left floating without affecting the performance of the Bt604. PERIPHERALS 6 - 99 Bt604 Application Information Introduction Tspan is set with an external current source (usually a resistor to a voltage VEXT) as shown in Figure 4. The Tspan positive temperature coefficient can be partially compensated with an external network exhibiting a negative temperature coefficient consisting of two resistors and an inexpensive IN4148 diode (see Figure 5). Resistors RI and R2 are selected from Table 1 according to the Tspan desired. R 1 and R2 are metal film resistors. R2 is selected or trimmed to obtain the desired Tspan. The Bt6D4 Timing Edge Vernier uses an external current source to set and calibrate the time delay span, Tspan. This section describes how Tspan may be set using external resistors and how an external diode may be used to improve, by a factor of approximately 3: I, the effects of temperature variations. In applications where the output time delay may be measured, Tspan may be automatically calibrated using an external programmable current source. Also described is how this can be achieved in a cost effective manner using Brooktree's BtllD CMOS Octal 8-bit DAC. The 2 mV/oC decrease in the forward voltage drop across the diode provides the necessary small changes in current. This network is most effective over a temperature range of 40 to 60°C. Also shown in Table 1 are the temperature coefficients that can be expected over this temperature range for a 10° change in temperature. This is not a linear function in all cases. For example, with a 5 ns Tspan, Tmin may decrease from 40 to 50°C, and then increase from 50 to 60 °C. As a result, values shown are absolute values. Tspan Temperature Compensation The Bt604 exhibits small changes in Tspan with changes in temperature caused by temperature coefficient differences between the minimum time delay ([min) and the maximum time delay ([max), where: Tspan = Tmax - Tmin VBB VEE vee otrP 00-07 OlIT TRIG TRIO' COMPI CE' COMP2 I EXT RIORl IN4148 GND Figure 5. 6 • 100 SECTION 6 Typical Temperature Compensation Circuit. Bt604 Application Information (continued) This can be stated more simply as: Tspan Calibration Using the Bt110 The accuracy and stability of the circuit providing the reference current (IEXT) directly affects the timing span accuracy. Computing values for Rl and R2 in Figure 5 results in a Tspan accuracy of better than ±20%. This may require the adjustment or trimming of R2 to set Tspan to the precision required by the application. Using the BtllO CMOS Octal 8-bit DAC can eliminate the need to trim resistors and provides a cost-effective, low-power solution to Tspan calibration. The block diagram of tIle-Btll0 is shown in Figure 6. For example, the Bt604 requires a nominal external current of 1850 IJ.A for a Tspan of 5 ns. When the span is set to 5 ns, the Tspan/IEXT ratio is typically 2.80 ps/lJ.A. Setting Tspan with resistor values as per Table 1 could result in a Tspan error of ±20%, or ±l ns. To correct for this error would require an adjustment of IEXT of ±1 ns divided by 0.0028 ns/IJ.A or ±357 f.LA. If this !EXT adjustment is to be supplied by a DAC, then the full-scale range would need to be 2 x 357 =714 IJ.A. An 8-bit DAC with this range would have a calibration resolution of 714 j.LA divided by 255 or 2.8 f.LA per bit. This represents a calibration resolution of 2.8 f.LA times 2.8 ps/f.LA or 7.84 ps. • Setting Tspan with resistors results in an error of±x% • The Bt604 has 8 bits of resolution • Calibrating with an 8-bit DAC results in a calibration resolution of 2x% of 1 LSB of the Bt604 • For Tspan =5 ns 1 LSB = 5 ns/255 = 19.6 ns Calibration resolution for ±x = ±20% is 0.4 x 19.6 = 7.84 ps The circuit shown in Figure 7 implements this using the Brooktree BtllO CMOS Octal 8-bit DAC. Resistor R5 provides a voltage drop so that the ±l Y compliance range of the Bt110 is not exceeded; variations in R5 have no effect on IEXT. The output range of the Bt1lO is set by R6: Range (f.LA) = l000*YREF (Y) I R6 (0) where YREF into the B tIl 0 may be set by the internal 1.2v reference of the BtllO. Using this internal reference, the full-scale gain error of the BtllO is ±10%. Table 2 shows resistor values for the circuit in Figure 7. As the BtllO has eight 8-bit DACs, it is capable of calibrating up to eight Bt604s. Tspan (ns) Rl R2 (0) TminTempco (psfOC) TmaxTempco (psfOC) Tspan Tempco (0) 5 10 15 20 1000 2000 3300 4700 1154 2411 3569 4590 2.5 2.5 2.5 4.0 2.5 2.5 2.5 4.0 1.0 1.0 2.0 2.0 Table 1. (ps/OC) Component Values for Figure 5. PERIPHERALS 6 • 101 Bt604 Application Information (continued) VREP our VREP IN VREF COMP VAA AONO l0UI'8 lourl PSADJUSTI FSADJUST4 COMP4 COMP! 101m lOUfZ 10tJT6 l0UI'3 FSA= PSADJUST3 COMP> COMP2 lourS lour. DO-D7 Figure 6. CS· RD- WR·AO-A2 Block Diagram of the Bt1l0 Octal 8-Bit DAC. R6 IN4!48 /"1.25V R3 ,.------, GND - .....- ......---'\i'\r--4.....:.IEXT ='-j Bt604 R4 Figure 7. Tspan (ns) R3 R4 R5 R6 (0) (0) (0) (0) Nominal Range of BtllO DAC (IIA) 5 10 15 20 1000 2000 3300 4700 1200 2700 3900 4700 2500 4500 8100 17000 1500 2660 4800 10000 800 450 250 120 Table 2. 6 - 102 Tspan Calibration Using the Bt1lO. SECTION 6 Component Values for Figure 6. Bt604 Recommended Operating Conditions Parameter Device Ground Power Supply Reference Current Ambient Operating Temperature Symbol Min Typ Max Units vee 0 -4.9 150 0 0 -5.2 0 -5.5 2500 +70 Volts Volts VFE IFXf TA IIA ·C Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. Absolute Maximum Ratings Parameter Max Units -8.0 Volts VFE Volts -30 rnA TJ +125 +150 +150 ·C ·C ·C TVSOL 220 ·C Symbol Min VEE (measured to VCC) 0 Voltage on Any Digital Pin Output Current Ambient Operating Temperature Storage Temperature Junction Temperature Vapor Phase Soldering (1 minute) TA 15 -55 -65 Typ Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PERIPHERALS 6· 103 Bt604 DC Characteristics Parameter Symbol TA (OC.) Min Input High Voltage V1H 0 +25 +70 Input Low Voltage VIL Output High Voltage Output Low Voltage Max Units -1170 -1130 -1070 -840 -810 -735 mV mV mV 0 +25 +70 -1950 -1950 -1950 -1480 -1480 -1450 mV mV mV VOO 0 +25 +70 -1020 -980 -920 -840 -810 -735 mV mV mV Va.. 0 +25 +70 -1950 -1950 -1950 -1630 -1630 -1600 mV mV mV Input High Current (Vin = VIH max) TRIG, TRIG* IIH IIH FUlL FUlL 20 30 j.tA j.tA Input Low Current (Vin = VIL min) TRIG, TRIG* IIL IIL FUlL FUlL 20 25 j.tA j.tA Output Delay Spans Differential Linearity Error* * Integral Linearity Error** IL FUlL ±0.9 ±1.0 ±l.25 LSB LSB LSB VBB Output Voltage IEXT for Tspans Tspan = 4ns Tspan= 5 ns Tspan = IOns Tspan = 15 ns Tspan = 20 ns Tspan = 30ns n.. +25°_70° 0° VBB FUlL -1.44 -1.30 Volts IEXT FUlL 2.1 1.6 0.80 0.53 0.39 0.25 2.65 2.1 1.05 0.70 0.52 0.34 rnA rnA rnA rnA rnA rnA FUlL 4.9 6.2 ns Tmin FUlL 2.5 3.5 3.8 4.9 ns ns lEE 70° 0°,25° 200 210 rnA Tspan with IEXT = 1.7 rnA (Tspan = Tmax - Tmin) Minimum Delay Time* Data = 00, Tspan = 5 ns Tspan = IOns VEE Supply Current Typ 180 Test conditions (unless otherwise specified): "Recommended Operating Conditions". OUT and OUT* loading with 50 n to -2.0 V. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. Note: The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. *For other minimum time delay values, refer to delay calculation equations in the Circuit Description section. **Tested at 10 MHz trigger rate with span at 5 ns. 6 • 104 SECTION 6 Bnxktree~ Bt604 AC Characteristics Parameter Max Units 125 MHz ns 4.5 750 ns ps ns ISO 220 ps Ins 4 15.7 40 157 ns ps Symbol Min Trigger Rate (note I) Trigger Width High Fmax TWl 2 Output Pulse Width High Time Output Pulse Rise/Fall Time (20/SO%) Output Pulse Spacing 1WO 2.5 Typ 550 TS Minimum Delay Time vs. Tspan aToo Ins (Tspan = 5 ns to 10 ns) Output Delay Tspan (Tspan = Tmax - Tmin) Resolution (Tspan I 255) Tempco (5 ns Span) aTspan/'C aTmin/'C Power Supply Rejection (Data = O-FF HEX, Tspan = 5 ns) S psI ·C psI ·C 6 4 100 CE* Setup Time CE* Hold Time WRITE Pulse Width High Time DO-D7 Setup Time DO-D7 Hold Time TSU 1H 2.0 1WH lDSU 1m 2 1 ps/V ns ns 1.5 ns ns ns 1.5 Test conditions (unless otherwise specified): "Recommended Operating Conditions". ECL input values are -O.S9 to -1.69 V, with input rise/fall times s 2 ns, measured between the 20% and SO% points. Timing reference points at 50% for inputs and outputs. OUT and OUT* loading with 50 n to -2.0 V. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. Note I: Maximum Tspan and Trigger Rates: Maximum Tspan (ns) Maintaining Linearity of±2LSB of±1 LSB 4.0 5.1 5.S 6.75 S.l 9.9 12.0 15.5 22.0 4.6 5.5 6.3 7.7 8.7 10.5 14.1 20.5 - Maximum Trigger Rate (MHz) Minimum Trigger Period (ns) 125 100 90 SO 70 60 50 40 30 S 10 11.1 12.5 14.3 16.6 20.0 25.0 33.3 The information in this table is guaranteed but not 100% production tested. See Figures S and 9 for a graphic representation. PERIPHERALS 6· 105 - Bt604 AC Characteristics (continued) Max. Tspan vs. Max. Trigger Frequency (30 to 60MHz) ~r----r----~--'---~----r---~--~----r---~---' I" i ~ 10 5~--~--~~--~--~----~--4---~----~--~--~ 20 30 40 50 60 70 Trigger Frequency (MHz) Figure 8. Bt604 Tspan vs. Frequency (30-60 MHz) Max. Tspan vs. Max. Trigger Frequency (70 to 125MHz) 9~--~~--~~'---r--'--~--~~~--~~---r--'-~ Ii' 6 1 ! 5 ! 3+---~~------~----~~-----p------~----~------~ 60 70 60 100 110 130 90 120 T~gger Figure 9. 6 - 106 SECTION 6 Frequency \MHZ) Bt604 Tspan vs. Frequency (70-125 MHz) Bt604 Ordering Information ModelNumbet Package Bt604KPI 28-pin Plastic I-Lead Ambient Temperature Range 0° to +70" C Timing Waveforms TRIG 1'5U 111 msu TDH CEO DO·D7 DATA DBLAY OUT Input/Output Timing. PERIPHERALS 6· 107 Preliminary Information This document contains information on a new product. The parametric information. although not fully characterized. is the result of testing initial devices. Distinguishing Features • 125 MHz Maximum Trigger Rate • Less than ±l LSB Timing Accuracy 15 ps Delay Resolution (4 ns Span) • Extendable Delay Span to 40 ns • Differential Trigger Inputs • 10KH ECL Compatible • Monolithic Construction 28-pin Plastic J-Lead (PLCC) Package • Typical Power Dissipation: 910 mW Applications • • • • Automatic Test Equipment Precision Timing Verniers Arbitrary Waveform Generators Multiple Phase Clock Generators Computer Backplane Timing 125 MHz 10KH ECL Compatible Programmable Timing Edge Vernier Product Description Related Products The Bt605 is a Programmable Timing Edge Vernier. whose time delay is loaded independently of triggering the circuit. In response to a trigger pulse. the B t605 outputs a pulse of fixed width a programmable delay time later. • Bt604 With the delay span set to 4 ns. the Bt605 features 15 ps of resolution (255 steps). The delay span is externally adjusted and is set in the range of 4 ns to 40 ns by IEXT. Functional Block Diagram VBB Bt605 VEE VCC Separate to triggering of the device. a new 8-bit value of delay is written in parallel (OO-D7). ::it; -+----1> DO· D7 -!--:-r--., LATCH ~---;-- OUT" The device is lOKH ECL compatible with ECL inputs and has a differential ECL input trigger. output pulse. and write input. ~-I--+-- OUT TRIO TRIO' CEO COMPl -t--cI COMP2 The Bt605 also meets the need for progranunable time delays in numerous electronic instruments that perform signal modulation, processing. and generation. I EXT Brooktree Corporation 9950 Bames Canyon Rd. San Diego. CA 92121 (619) 452-7580· (800) VIDEO IC TLX: 383596· FAX: (619) 452-1249 L605001 Rev. F In applications for Automatic Test Equipment (ATE). the Bt605 forms the critical component in providing precise timing edges having fine resolution and excellent edge placement accuracy. 6 . 109 Bt605 Circuit Description As illustrated in the block diagram, the Bt605 contains an 8-bit D/A converter, a linear ramp generator, and a comparator. Output Pulse Spacing Consecutive output pulses must be spaced no less than 8 ns aparL Functional Operation Conditions for Optimum Performance Referring to Figures 1 and 2, the linear ramp determines the span of delay and the DAC's output sets the delay value. The programmed value of delay is written into the DAC input register via DO-D7 and WRITE. H CE* is a logical zero, the differential input trigger (TRIG, TRIG*) initiates a linear ramp on the rising edge of TRIG. The comparator detects when the ramp reaches the DAC's programmed value, whereupon it initiates an output pulse of fixed width and resets the ramp. Resetting the ramp permits another trigger of the Bt605. Delay Calculations Referring to Figure 2, the output pulse delay consists of a minimum output delay (Tmin) and a programmable output delay (Tprog). For DO-D7 equal to $00 the output delay will be Tmin and for $FF the output delay will be Tmax. The span of the delay range is: Tspan = Tmax - Tmin The output pulse delays are adjustable and are set by IEXT current flow through pin 12. Figure 3 shows the relationships Tspan vs. IEXT and Tspan vs. Tmin. The following equations apply to Figure 3: Tmin (max) = Tspan * 0.217 + 2.7 Tmin (min) = Tspan * 0.187 + 1.6 Tmin (max) - Tmin (min) = Tspan * 0.03 + 1.1 Referring to Figure 4: IEXT = (VEXT + 1.25 V) / (REXT + 26 0) The timing vernier is a mixed signal device and to obtain the maximum accuracy and stability over frequency there are specific conditions required to achieve maximum performance. This product requires special attention to proper layout techniques to achieve correct operations. Before beginning PCB layout, please reference the ECL layout techniques in Bt60416051606 Evaluation Module Operation and Measurements (AN-17), found in Brooktree's 1990 Applications Handbook. Do not expect optimum performance when operating the device in a socket. Lead inductance, transmission line discontinuities and restricted air flow attributable to the use of a socket will degrade performance. A transverse air flow of 400 linear feet per minute is very important when considering error sources in the magnitude of tens of picoseconds. The ferrite chip bead selected for use with this device is critical. Use only the bead recommended. It is very important that this bead be mounted as close as possible to the VEE(l) power pins connecting the device to the power plane as illustrated in Figure 4. Connecting the decoupling capacitors directly to the VEE( 1) pins will result in unstable operation. Note that all components must be placed as close to the pins as possible, and that all VCC pins must be COIUlected together. A constant trigger pulse width should be maintained to achieve the best absolute time performance over frequency. A trigger pulse width of Tmin - 500 ps is required to keep the falling edge of the trigger pulse width from occurring during the ramp. 11110 DELAY our Figure 1. 6· 110 SECTION 6 Delay Timing. Bt605 Circuit Description (continued) VOLTAGE min DAC [ output example range max ...................................................................................................... .. ~------+--------+--------+----------e Tmin 1]ME(m) Tprog Tmax OUT Figure 2. Linear Ramp and Output Pulse Timing. Tmln Variations va. Tapan Iext(pA) .. 12:-r--;----;--;---;----;:---;---;---, ~"~~i~!~i~~rr~TT~' 2000 !! 1800 .;1600 •• 1400 1200 1000 i\ ! -+H -r- i-' i 1- :t· , .-i.J.. i :: i i! i .+.. ·++"1···· ··t· . -t·· .+...+. i!i + +1+. +.+.+ .+ 8 li- 2.6 4 ... ..,,....... , 2 ....... ~-• 200~~~!~!~~~~~~~~~·~ 481216202428323640 Figure 3. . ........ ...... ~ I • 5 10 ...... ~- .... -~ .. -... ~ ...... -~ .. ..... ~ .... -., I. ;...:-:r.::=~~!=~1...._~.iiiiiiijiii.: ' I I I I 16 20 26 1 t I 30 35 2.0 Ii 1.5 8 1.0 I I 40 Typical Output Delays. PERIPHERALS (I. 111 Bt60S Circuit Description (continued) Bt60S -5.2V CI ZO=SO WRITE -2V GROUND 50 ZO=SO WRITE- IBXT -2V so ----!- ZO=SO -1N TRIG ZO=SO our- 50 ZO=SO VBXT ZO=50 our -2V RBXT -1N lRIG· 50 -2V so AL11lRNATE OUfPUT LOADING: -4V Location Description C1-C4 L1 REXT 0.1 J.lF ceramic capacitor ferrite chip bead 1% metal film resistor (selected for proper Tspan) Vendor Part Number Erie RPE112Z5U104M50V TDK HF70ACB322513 or TDK CB301210 Dale CMF-55C Note: The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the Bt605. All devices should be as close as possible to the Bt605. Figure 4. 6 • 112 SECTION 6 Typical Connection Diagram and Parts List. Bt605 Pin Descriptions Pin Name Description DO-D7 Data input pins (ECL compatible). On the falling edge of WRITE, DO-D7 axe latched into the DAC input register. DO is the LSB. These inputs specify the amount of delay from the rising edge of TRIG to the output pulse. WRITE, WRITE" Differential write inputs (ECL compatible). These inputs control the parallel data input latch. When WRITE is a logical one, the data latch is transparent. Data is latched on the falling edge of WRITE. A single-ended write may be used by connecting WRITE* to VBB. CE" Chip enable input (EeL compatible). CE* must be a logical zero on the rising edge of TRIG to enable the device to respond to the trigger. If CE" is floating, the trigger will always be enabled. TRIG,TRIG" Differential trigger inputs (ECL compatible). The rising edge of TRIG is used to trigger the delay cycle if CE* is a logical zero. If CE" is a logical one, no operation occurs. It is recommended that triggering be performed using differential inputs. OUT,OUT" Differential outputs (ECL compatible). !EXT Current reference pin. The amount of current sourced into this pin determines the span of output delay. The voltage at IEXT is typically -1.25 V. COMPI, COMP2 Compensation pins. A 0.1 J.lF ceramic capacitor must be connected between CaMPI and VEE(O) and also COMP2 and VEE(O). See Figure 4. VEE Device power. All VEE pins must be connected. Warning: It Is important that a ferrite chip bead be used to connect the VEE(l) power pins to the power plane as Illustrated In Figure 4. Connecting the decoupling capacitors directly to the VEE(l) pins will result In unstable operation. vee Device ground. All VCC pins must be connected together. VBB -1.36 V (typical) output. ~ §§ ~ ~ ~ ~ ::l 1li ::l ~ '" l'l !!l DO 18 COMP2 Dl 17 NiC D2 16 NiC OJ IS CE' D4 14 COMPI DS 13 WRITIl' 12 VBB D6 l"- 00 " ~ ~ i!! IF) \C) S ~ .. e ::: 52 s ~ -~ ~ Note: N/C pins may be left floating without affecting the performance of the Bt605. PERIPHERALS 6· 113 Bt60S Application Information Introduction Tspan is set with an external current source (usually a resistor to a voltage VEXT) as shown in Figure 4. The Tspan positive temperature coefficient can be partially compensated with an external network exhibiting a negative temperature coefficient consisting of two resistors and an inexpensive IN4148 diode (see Figure 5). Resistors Rl and R2 are selected from Table 1 according to the Tspan desired. R 1 and R2 are metal film resistors. R2 is selected or trimmed to obtain the desired Tspan. The Bt605 Timing Edge Vernier uses an external current source to set and calibrate the time delay span, Tspan. This section describes how Tspan may be set using external resistors and how an external diode may be used to improve, by a factor of approximately 3:1, the effects of temperature variations. In applications where the output time delay may be measured, Tspan may be automatically calibrated using an external programmable current source. Also described is how this can be achieved in a cost effective manner using Brooktree's BtllO CMOS Octal 8-bit DAC. rc decrease in the forward voltage drop The 2 m V across the diode provides the necessary small changes in current. This network is most effective over a temperature range of 40 to 60 ·C. Also shown in Table I are the temperature coefficients that can be expected over this temperature range for a 10· change in temperature. This is not a linear function in all cases. For example, with a 5 ns Tspan, Tmin may decrease from 40 to 50 ·C, and then increase from 50 to 60 ·C. As a result, values shown are absolute values. Tspan Temperature Compensation The Bt605 exhibits small changes in Tspan with changes in temperature caused by temperature coefficient differences between the minimum time delay (Tmin) and the maximum time delay (Tmax), where: Tspan =Tmax - Tmin VBB VBB vee =-1----1> 'CC---+-- Ol1l'* ~-I--I-- OlIT TRIG TRIG' COMPI Cll" COMPl IBXT RIQIU IN4148 GND Figure 5. 6 • 114 SECTION 6 Typical Temperature Compensation Circuit. Bt605 Application Information (continued) Tspan Calibration Using the Bt110 This can be stated more simply as: The accuracy and stability of the circuit providing the reference current (!EXT) directly affects the timing span accuracy. Computing values for R1 and R2 in Figure 5 results in a Tspan accuracy of better than ±20%. This may require the adjustment or trimming of R2 to set Tspan to the precision required by the application. Using the Bt110 CMOS Octal8-bit DAC can eliminate the need to trim resistors and provides a cost-effective, low-power solution to Tspan calibration. The block diagram of the BtllO is shown in Figure 6. For example, the Bt605 requires a nominal external current of 1850 ~A for a Tspan of 5 ns. When the span is set at 5 ns, the Tspan/IEXT ratio is typically 2.80 ps/~A. Setting Tspan with resistor values as per Table 1 could result in a Tspan error of ±20%, or ±1 ns. To correct for this error would require an adjustment of IEXT of ±1 ns divided by 0.0028 ns/I1A or ±357 ~A. If this !EXT adjustment is to be supplied by a DAC, then the full-scale range would need to be 2 x 357 = 714 ~A. An 8-bit DAC with this range would have a calibration resolution of 714 I1A divided by 255 or 2.8 ~A per bit. This represents a calibration resolution of 2.8 I1A times 2.8 ps/IJ.A or 7.84 ps. • Setting Tspan with resistors results in an error of±x% • The Bt605 has 8 bits of resolution • Calibrating with an 8-bit DAC results in a calibration resolution of 2x% of 1 LSB of the Bt605 • For Tspan = 5 ns 1 LSB = 5 ns!255 = 19.6 ns Calibration resolution for ±x = ±20% is 0.4 x 19.6 = 7.84 ps The circuit shown in Figure 7 implements this using the Brooktree BtllO CMOS Octal 8-bit DAC. Resistor R5 provides a voltage drop so that the ±1 V compliance range of the Bt110 is not exceeded; variations in R5 have no effect on IEXT. The output range of the Bt1lO is set by R6: Range (~A) = l000*VREF (V) / R6 (0) where VREF into the BtllO may be set by the internal 1.2 V reference of the Bt110. Using this internal reference, the full-scale gain error of the BtllO is ±1O%. Table 2 shows resistor values for the circuit in Figure 7. As the Bt110 has eight 8-bit DACs, it is capable of calibrating up to eight Bt605s. III Tspan (ns) Rl R2 (0) (0) TminTempco (psl"C) TmaxTempco (ps/oC) Tspan Tempco (ps/oC) 5 10 15 20 1000 2000 3300 4700 1154 2412 3569 4590 2.5 2.5 2.5 4.0 2.5 2.5 2.5 4.0 1.0 1.0 2.0 2.0 Table 1. Component Values for Figure 5. PERIPHERALS 6· 115 Bt605 Application Information (continued) VREP IN VRBP roMP VRBP our VAA AGND lourl PSADJUSTl 10llrB PSADJUST4 COMP< COMPI lOUl7 10l!r2 1 .. ~ 9 ::1 I~ I GND2 IN'2 IN,. 0UT3* VIlIl3 GND4 GND4 0UT4 0UT4* IN4 .~::!:!:l~~~~ IIQ ~ ~ ~ iii ~ ~ Ii I e PERIPHERALS 6 - 125 Bt622/624 Detailed Block Diagram so 81 0J0ID1 ONDI +-_____-\ 0111'1 INI.IN""I_· 0\11'1· GNDl 0l:Jn 1N2,1N2. 0lIT2· GND3 0J0ID3 0Ij\'J 00,00'" mm o 11113 OND4 0ND4 0IIT4 JN4.1N4· 0111'4· COMP! RBXTI VBB COMPl RBXT1 Bt624 Detailed Block Diagram 6 - 126 SECTION 6 Bt622/624 Application Information Power Supply Decoupling ALL VEE supply pins should be separately decoupled to GND with a 0.1 VF ceramic chip capacitor. The bypass capacitors should be as close as possible to the device. A ground plane is recommended to provide a low-inductance ground return path. The individual channels have separate GND and VEE pins to maintain superior crosstalk performance. The bypass capacitor for each channel should be placed between GNDI and VEEI, GND2 to VEE2, etc. Internal Fanout The DRVMODE control input is used to internally distribute the signal present at Channel 2 of the Bt624 (Channel 1 of the Bt622) to Channels 1, 3, and 4 (Channel 2 of the Bt622). This allows the user to terminate a high-quality signal at only one input, avoiding the larger lumped capacitances involved if mUltiple package inputs were daisy-chained. Refer to the detailed block diagram for the Bt624. DRVMODE enables the AND gate at Channel 2 to drive the OR gate at the other channels, thereby buffering the signal and maintaining signal integrity. The unused channel inputs are still active. They have internal pulI-ups and pulI-downs to create a logical 0 at the inputs. This alIows the user to float these inputs by leaving them unconnected. They may be driven with signals of their own, however. The application may be for a gated signal, such as a clock. The clock signal applied to Channel 2 and fanned out through Channel 1 may be controlIed and gated ON or OFF at Channell's output by asserting a logical 0 or 1 respectively at Channell's input. Once the signal is internally buffered and distributed to the other channel inputs, the signal may be delayed independently through each channel according to the mode selected and the signals present at the VDELAY and VWIDTH control inputs. Ranges of Delay The SO, S 1 control inputs select the range of delay for the signals through the Bt624. There are two types of delay available, one where the input signal is simply delayed and the output signal is identical to the input signal, and the other where independent delay of the leading and trailing edges is available. Refer to Table 1 for the descriptions of modes versus control inputs. Modes 0, 1, 4, and 5 are delays of type I-group delays are imposed upon the input signal with NO independent leading and trailing edge adjustment. The criteria dictating which of these modes the application deserves are range of delay needed and the minimum pulse widths expected. Roughly, Mode 0 is a IO-ns delay range, Modes 1 and 4 are 20-ns delay ranges, and Mode 5 is an extended 30-ns delay range. Modes 0 and 1 delays are adjusted via the channel VDELA Y inputs only. The VWIDTH control inputs are nonfunctional and unused. Modes 4 and 5 delays utilize both the VDELAY and VWIDTH inputs for control. When implementing Modes 4 or 5, the VDELAY and VWIDTH inputs should be shorted together and a common control voltage applied. The minimum pulse widths through the channels of delay are related to the chosen range of delay. The longer the range of delay, the longer a very small pulse width may be delayed before incurring inaccurate tracking and subsequent pulse swallowing. Minimum Pulse Widths The delay elements have bandwidth constraints for different range configurations and group delay control voltages. These bandwidth differences exhibit themselves as limitations to the acceptable minimum pulse widths (TPW(min) ) for a delay channel. Figure I illustrates the minimum pulse widths which may be passed through the delay channels. These are nominal graphs of TPW(min) for the ranges achievable from the SO and SI input pins for modes 0 through 5. The result of violating these minimum curves is a missing output pulse, as the pulse is swallowed. The mode selection of a particular range of delay and trailing edge adjustment offers the user great flexibility in optimizing the needs of the applications at hand. Different range modes utilize more or less of the Bt622/624 circuitry. Unused on-chip circuitry is powered down to alIow cooler operation. Independent Edge Delays Modes 2 and 3 offer the capability to adjust the delays of the leading (rising) and trailing (falling) edges. Mode 2 is a 10 ns delay range and Mode 3 is a 20 ns range. The selection of range depends on the desired range of overall delay (group delay) of the signal and how much trailing edge adjustment will be required. PERIPHERALS 6· 127 .. Bt622/624 Application Information (continued) ~~----------------------------------------~ - MODESO,2 MODES 1.3.4 MODES 30 O+---,---_r--~--~~~~--T_--,---_r--~--_4 o Minimum Pulse Width (nl) Figure 1. Minimum Pulse Width vs. Group Delay. both the leading and trailing edges. For this reason, delay calibration should be performed first with VDELAY, then wilh VWIDTH. This will be covered more fully in Calibrating a System Channel. Figure 2 is a clear representation of the circuit topology of Modes 2 and 3. Notice that the number of delay cells for the trailing edge adjustment remains constant. The VWIDTH delay range of adjustment is fixed and is the same for both Modes 2 and 3 at 10 delay elements. The number of delay cells for the leading edge adjustments changes from 15 to 25 for Modes 2 and 3 respectively. The positive-going edge triggers Ihe set input to the S-R flip-flop. The signal is inverted after it is delayed for the negative-going edge and triggers the reset input to the flip-flop. The trailing edge adjustment (via VWIDTH) controls the trailing edge delay only; it has no effect on the leading edge. The VDELAY control has an effect on (Numbers in blocks are numbers ofdelay cells.) VDEl.A Y ----r--.......... --· ........ --..... -...... -: (15) IN .£>-t>. 5 Lcadins Bdge .£>.£>.1----, 10 o = Mode 3 OIIT .£>-£>.110--..... Figure 3 is a useful tool to determine whether Mode 2 or 3 should be implemented in a particular application. When VDELAY is at minimum delay, the range of adjustment of Ihe trailing edge is 0 to +8 ns at Ihe VWIDTH input. When VDELAY is at maximum delay, the trailing edge has -8 to 0 ns of adjustability. These points set the ranges of adjustment that are available at the VWIDTH pin. The shaded area indicates the operating zone. The user should first determine the required range of adjustability of the trailing edge versus the leading edge position. This will dictate what range of overall group delay is available for the partiCUlar mode. As an example, if ±2 ns of trailing edge adjustment is required, the intercepts for the operating range are at 25% and 75% of the VDELAY range. This relates to the center 50% range of overall VDELAY. For Mode 2, this would allow 5 ns of "group delay," and for Mode 3 it would be 10 ns, each calculated as 50% of the available range. Similarly, if ±1 ns of trailing edge adjustment is required, 12.5% and 87.5% are the intercepts. These would allow 7.5 ns and 15 ns of adjustment range for Modes 2 and 3 respectively. 10 VWIDTII -------------- .... ; Figure 2. 6 • 128 Modes 2, 3 Detailed Channel Block Diagram. SECTION 6 Bt622/624 Application Information (continued) ...... .8.0 1'...... +6.0 +4.0 . e .!' i'... • 2.0 "', ... ... ... ......, 0.0 ~S ""'~ ~... ~. ... ..... ......... ~!ii -2.0 ... . OJ _ ... ... ......... ... c-;;- J1 =i ~ Io ... ... "'t-•..... 'tI.r 1'<' '. ~"'''' ...... 1-....... -4.0 -~ 0, ...... .... 0 10 . 20 40 30 '0 ...... ... ........ -6.0 -lI.o ........ 60 ... ... ........, . 10 _Delay "'....... 100 80 MuDeIay VDELA Y Range ('11» Figure 3. VWIDTH Delay Range Figure 4 depicts the Bt622 in a variety of applications_ The Sl input pin is connected to GND. This programs a logical one, which enables the VWIDTH pins for adjustment of negative transitions through all channels. The DRVMODE input is set to a logical low (tied to -5_2 V) which allows Channell and Channel 2 inputs to both be valid_ If the pin had been a logical one, the input to Channell would also be ORed into Channel 2. Channel I is being driven with a differential ECL input as a high-performance application. The SO input is set low (tied to -5_2 V) to enable the lower delay span, 8 to 18 ns. for both channels_ The VDELAY and VWIDTH control inputs are being driven from a current output DAC (e_g_. a BtllO Octal DAC) with 1 mA full-scales_ This offers complete digital programmability of both the group delay (VDELAY) and the fine adjustment of the negative transitions only (VWIDTH). R1 and R2 are 1 ill. The 1 mA current sources at these pins are summed with the DAC output currents to enable voltages from 0 V to -1.0 V. the entire adjustment range. I'S. VDELAY. Channel 2. in contrast. is a lower-performance application_ The input is driven single-endedly. The inverting input (lN2*) is connected to the VBB output of the Bt622 to allow proper ECL switching at the -1.3 V point The delay control inputs are adjusted by the trimming resistor (R4) to ground. The VDELAY and VWlDTH control inputs are shorted together and tied to this same controlling resistor_ Since two control inputs are tied together, 2 rnA of node current results (1 rnA for each input)_ Therefore. the 500 a trimming resistor will allow a range of 0 to -1 V. This type of connection is used for less demanding applications where the relevant timing is only to a single edge and the need for independent adjustment of leading and trailing edges does not exist. With the two inputs commoned to the same voltage node. the delays of the leading and trailing edge will track and be approximately equal. The Bt622/624 have open-emitter outputs; thus. they must be terminated through 50-a resistors to -2 V at the end of the transmission paths or the equivalent Microstrip layout techniques are recommended_ The input signals should also abide by proper high-frequency layout rules_ Minimize any possible reflection sources and maintain a constant low-impedance transmission line up to the device. PERIPHERALS 6· 129 .. Bt622/624 Application Information (continued) Figure 4 has both channels' differential outputs terminated. Single-ended terminations of the outputs are not recommended for maximum performance. All differential stages should be equally loaded. Figure 4 also shows each termination resistor having its own bypass capacitor to ground for the -2 V termination voltage. The use or nonuse of individual capacitors for each termination resistor is a function of the actual layout and the resultant ground and -2 V path impedances. Adjacent termination resistors (chip resistors are always recommended for maximum performance) may get by with a single bypass capacitor. Under no conditions are common resistor networks recommended for optimum operation. ease of use. It is up to the user to follow these recommendations in the applications and evaluations of the devices. Delay Channel Linearity Figure 5 is a graph of the delay versus VDELAY control voltage. The transfer curve is not an ideal straight line--there is a characteristic nonlinearity to the curve. The Bt622/624 was not designed to be ultra-linear. It is guaranteed monotonic: any decrease in control voltage will increase the programmed delay. Although the Bt622/624 is designed to operate with constant power dissipation, the airflow requirement of 400 LFPM is recommended to minimize any thermal variations which may result in tens of picoseconds of delay variations. A further aid in visualizing the flexibility of ranges available is shown in Table 1. Given the two input pins, S 1 and SO, six different range configurations are possible. Since these ranges are all unique in group delay and trailing edge adjustment capability, they are enumerated as mode numbers-Modes 0 through S. Maximum performance from the Bt622/624 can only be obtained by careful layout and evaluation. Timing measurements in the sub-1OO picosecond range are valid only if great care in the total environment of the device is observed. Great care was taken to design and specify these devices for maximum performance and The AC Characteristics section of this document specifies the sensitivities at the endpoints of the transfer function for given voltages at the VDELAY control inputs. A further aid for determination of the required DAC resolution necessary for adjustment resolution is offered in Figure 6. The figure shows Differential ECLInput Signal Current Adjustments From BtllO Octal DAC or equivalent Single-ended 10KHlnput Signal + Qo.Oljd 9= Qo.lpf Figure 4. 6 - 130 SECTION 6 BI622 Typical Applications. Bt622/624 Application Information (continued) VDELAYor VWIDTH. The resistor value for Rl should be chosen so that the required full-scale control voltage, Vcntrl, is generated by the referenced current I. This full-scale voltage will be generated with the DAC outputting zero current. As the DAC sources more current into the node, less current flows through the resistor R 1 and therefore the voltage generated across the resistor decreases and generates the minimum control voltage. So, simply put, the equation is: Control Voltage Circuits The user has several options in which to interface to the output delay control pins VDELAY and VWIDTH. The interface options include a current output DAC (as in the BtllO), a voltage output DAC, or simply a resistor connection to ground. The VDELAY and VWlDTH nodes, as described in the pin description section, are inputs to internal current sinks. This is indicated in Figure 8. Vcntrl = (ldac-I)*Rl. Figure 8a shows the connection to a current output DAC. For the sake of this discussion, let Vcntrl equal DAC Resolution (# of bits) Figure 6. Picosecondsl DACLSB Modes 0,2 Modes 1,3,4 156.0 78.0 39.0 19.0 9.7 4.9 2.4 6 7 8 7 8 9 10 11 12 9 10 11 12 Bt6221624 Delay vs. DAC Resolution. I \ IN \\\\\ L OUT ~ a. nIl III I--l I--l to to 11 11 Servo the Group Delay via VDELAY Pin. \ IN I \~~~ OUT --I I-- I 13 b. Servo the Negative Transition via VWIDTH Pin. Figure 7. 6 - 132 SECTION 6 B16221624 Channel Calibration. Bt622/624 Application Information Figure 8b indicates the connection for a positive voltage output DAC controlling Vcntrl. As shown, the combination of current source I and resistor R 1 generates the proper offset voltage, and resistor R2 generates the required attenuation. The method with which to calculate the resistor values Rl and R2, given the DAC output voltages and Vcntrl endpoints, is as follows: Vcntrl = Vdac*(R2/(RI + R2) - *Rl*R2/(RI + R2) Let A =R2/(Rl + R2) and B =Rl *R2!(RI + R2) so Vcntrl = Vdac* A-I*B and assume, oV S Vdac S Vdac(max) and, Vcntrl(min) S Vcntrl S Vcntrl(max), then, isolating A and B and substituting yields, B = -Vcntrl(min)II, A = [Vcntrl(max) + B*I]IVdac(max), and R2 = B*(1 + 1/(1 - A» Rl =R2*(1- A)/A. Example: OV S Vdac s7 V, -1.0 V S Vcntrl S -0.1 V, and, I = LOrnA. Substituting into the above equation B = 1.0 V/1.0 rnA =1000 0, A = (--0.1 V + 1000 0*1.0 rnA)!7 V = 0.128 V, R2 = 1000*[1 + 0.128/(1 - 0.128)] = 1148 0 and, Rl = 1148*(1 - 0.128)/0.128 =7776 0 I I =1.2vJREXTl , =1 rnA (nominal) Figure 8a. a Control Voltage from lOUT DAC. I I =l.2vJREXTl , =1 rnA (nominal) VOLTAGE OlITPUT DAC Figure 8b. Control Voltage from VOUT DAC. PERIPHERALS I) - 133 Bt622/624 Recommended Operating Conditions Parameter Device Ground Negative Power Supply Ambient Operating Temperature Symbol Min Typ Max Units GND VEE TA 0 -4.9 0 -5.2 0 -5.5 +70 Volts Volts 0 °C Note: Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. Absolute Maximum Ratings Parameter Symbol Max Units -6.0 Volts Voltage on any Digital Pin VEE Volts Output Current -50 rnA +70 +150 +175 °C °C °C 260 °C VEE (relative to GND) Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, 1/4" from pin) Min 0 TA 'IS TJ TSOL -55 -65 Typ Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6 • 134 SECTION 6 Bt622/624 DC Characteristics Parameter Symbol TA(OC) Min Digital Input High Voltage'" IN,IN· Vlli 0 +25 +70 Digital Input High Voltage'" DRVMODE, SO, SI Vlli Digital Input Low Voltage'" IN,IN'" Digital Input Low Voltage· DRVMODE, SO, SI Max Units -1170 -1130 -1070 -840 -810 -735 mV mV mV 0 +25 +70 -1170 -1130 -1070 0 0 0 mV mV mV VIL 0 +25 +70 -1950 -1950 -1950 -1480 -1480 -1450 mV mV mV VIL 0 +25 +70 VFE VFE VFE -1480 -1480 -1450 mV mV mV FUlL VFE -3.2 V SI Third State (Extended Delay) Typ Digital Output High Voltage· VOH 0 +25 +70 -1020 -980 -920 -840 -810 -735 mV mV mV Digital Output Low Voltage'" VOL 0 +25 +70 -1950 -1950 -1950 -1630 -1630 -1600 mV mV mV Input High Current (Vin =VIHmax) IN, DRVMODE, SO, SI IN* IIH IIH FUlL FUlL 250 -20 IIA IIA Input Low Current (Vin =VILmin) IN, DRVMODE, SO, SI IN'" llL llL FUlL FUlL 100 -40 IIA IIA Test conditions (unless otherwise specified): "Recommended Operating Conditions" with all OUT and OUT'" outputs terminated through 50 n to -2.0 V, REXTI = 1.21 ill, REXT2 = 2.43 ill. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. "'Relative to GND. The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. PERIPHERALS 6 - 135 .. Bt622/624 DC Characteristics (continued) Parameter Symbol TA("C) PSRR FUlL 0.5 % Tpdlvolt VEE Supply Current Quad Channel (Bt624) Mode 0 Modes 1,2 Modes 3,4,5 IFE FUlL FUlL FUlL 235 300 360 rnA rnA rnA Dual Channel (Bt622) Mode 0 Modes 1,2 Modes 3, 4, 5 IFE FUlL FUlL FUlL 130 160 200 rnA rnA rnA Power Supply Rejection Ratio Min Typ Max Units Test conditions (unless otherwise specified): "Recommended Operating Conditions" with all OUT and OUT* outputs terminated through 50 n to -2.0 V, REXTI = 1.3 ill, REXT2 = 2.94 ill. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. 6 - 136 SECTION 6 Bt622/624 AC Characteristics Max Units 5.5 17.8 8.3 29.0 6.5 18.3 9.5 30.0 8.3 29.0 12.5 41.0 6.5 19.3 9.3 30.5 7.5 19.8 10.5 31.5 9.3 30.5 13.5 43.0 ns ns ns ns ns ns ns ns ns ns ns ns -10 +10 ps/3ns Delay vs. Frequency (note 2) SO=low SO=high -20 -40 +20 +40 ps ps VWIDTH Range of Adjustment (VDELAY = -0.5 volts, Mode 2 or 3) VWIDTH = 0 volts VWIDTH = -1.0 volts -4.3 +3.7 -3.7 +4.3 ns ns Rising to Falling Edge Delay Matching Modes 0, 1, 4, 5 -100 +100 ps Parameter Propagation Delays (note I) MODE S1 VDElAY SO 0 0 -0.1 V 0 0 0 0 -1.1 V 1 0 -0.1 V 1 0 -1.1 V 1 1 2 1 0 -0.1 V -1.1 V 2 1 0 -0.1 V 3 1 1 -1.1 V 3 1 1 4 VEE 0 -0.1 V VEE -1.1 V 4 0 5 VEE 1 -0.1 V -1.1 V 5 VEE 1 Symbol Min TPDmin TPDmax TPDmin TPDmax TPDmin TPDmax TPDmin TPDmax TPDmin TPDmax TPDmin TPDmax Rising Edge Delay vs. VWIDTH Delay Change (Modes 2, 3) Propagation Delay Tempco (note 3) Output Rise/Fall Times (20% to 80%) Tr,Tf Delay vs. Input Rise/Fall Time (@ 700 ps TrTf Input) Typ 0.05 %TPDI"C 850 ps 5 ps/100ps Test conditions (unless otherwise specified): "Recommended Operating Conditions" with T A = 25 ·C and all outputs terminated with 50 Q to -2.0 V. Timing reference points at the differential crossing points for input and output signals, REXT1 = 1.3 ill, REXT2 = 2.94 ill. Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V. Note 1: Propagation delay minimums and maximums measured with VWIDTH = VDELAY for both leading and trailing edges. Note 2: Delay versus frequency characteristics are measured by setting VDELAY = VWIDTH = -0.5 V. The delay is measured for both rising and falling edges of a pulse at a 10 MHz repetition rate (100 ns period). The rising and falling edge delays are again measured at a 100 MHz repetition rate (10 ns period). The variation in delays is the delay versus frequency. Measurements are performed using a pulse width of 5 ns. Note 3: For example, 5 ps/·C when programmed for a 10 ns delay. The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board. PERIPHERALS 6 - 137 .. Bt622/624 Timing Waveforms TPD (falling) IN* \ II I1\ - IN OUT* / 1\ TPw - 80% .............. _........... -- 20% OUT - - -Tf --_ ... _-- -- - --- -- -- -- ----- -_ ... -_ ... _.. _- 1\11 / -------------------1 D----------------------- I~l\.-TPD (rising) - Ordering Information 6 - 138 Ambient Temperature Range Model Number Package Bt622KCJ 28-pin Ceramic Leaded Chip Carrier O· to +70· C Bt624KCJ 44-pin Ceramic Leaded Chip Carrier O· to +70· C SECTION 6 -Tr - - -- SECTION 7 .---- PACKAGING ------. INFORMATION .. Packaging Contents Part Numbering System 7-3 Device Marking 7-4 Thermal Resistance Information 7-5 Package Drawings 7 • 2 Plastic DIP 7-6 CERDIP 7-8 Ceramic Sidebraze DIP 7 - 11 Ceramic Cavity Down DIP 7 - 14 Plastic J-Lead (PLCC) 7 - 15 Ceramic J-Lead (CERQUAD) 7 - 19 Ceramic Pin Grid Array (PGA) 7 - 20 Plastic Quad Flatpack (PQFP) 7 - 23 Ceramic Flatpack with Heatsink 7 - 24 SECTION 7 Packaging Part Numbering System optional MIL-STD 883C, Class B processing for the S temperature range. optional speed gradeout information. RAMDACs, specifies MHz. For VIDEODACs and package type: C CI D F IN G L P PI PF S SW HI CERDIP ceramic I-lead (CERQUAD) ceramic sidebraze DIP ceramic flatpack (with heatsink) ceramic flatpack (no heatsink) ceramic PGA ceramic leadless chip carrier plastic DIP plastic I-lead (PLCC) plastic Quad flatpack 150 ntil SOlC 300 mil SOlC plastic I-lead (PLCC with heatsink) performance gradeout: B -25 to +85 °C K 0 to +70 °C (0 to +85 °C for lOOK ECL) L 0 to +70 °C, Low power S -55 to +125 °C For other than standard grades, refer to the individual datasheet for letter designation . basic model number 100-149 200-249 250-299 300-399 400-449 450-499 500-599 600-699 700-799 800-899 900-999 D/A converters AID converters imaging components reserved graphics peripherals RAMDACs general components ATE components reserved reserved reserved PACKAGING INFORMATION 7 - 3 • Packaging Device Marking (Top) Bt Bt458KG 125 - ZZZ YYWW L 7 • 4 SECTION 7 part number date code (YY =year, WW =work week) lot number (last three digits) Packaging Thermal Resistance Information Power Dissipation Calculations The maximum power dissipation that an IC can tolerate is determined by the thermal impedance characteristics of the package. The equation to find the allowable power dissipation at a given ambient operating temperature is: PD= (TJ-TA)/9 JA where: PD = power dissipation at ambient operating temperature TJ = maximum junction operating temperature (typically 150 ·C is used) TA = maximum ambient operating temperature (free air) 8 JA = typical thermal resistance of junction to ambient (OC / W) Packaging Notes 1. Unless otherwise indicated. all thermal impedances listed are typical range values or values in static free air for the package only. These impedances will vary when additional heat-sinking capability is provided through PCB solder attachment or air flow. • PACKAGING INFORMATION 7 •5 Packaging Plastic DIP Packages 16-Pin 0.3" Plastic DIP aJA=75°C/W 0,810 [20,57J 1'16 PIN 1 0,290-0,330 [7.37-8.38] 0.009-0.015 1 INDEX AREA [ ~ 8 0,060 [1.524J Om5 [0,381] 0.140 MAX [3,56] r 1-~0'I25 _I 0,350 [8,89] NOM 9-1 INDEx:;i:: :::: :I]::::::~~~ r;:;1 [0,228-0,381] 1 MAX 0,014-0,028 [0,36-0,58] JL J L--l [31751 0,063MI~,60] 0,100 TYP (2,54] 24-Pin 0.3" Plastic DIP aJA= 60 °C/W 0,06 [1.524] R 0,290-0,330 [7,37-8,38] ~ -.A 0,009-0,015 [0,228-0,381]"'L-j 0,350 [8,89] NOM [ ,~ 0,014-0,028 [0,36-0,58J JL J L--l NOTES - Unless otherwise specified: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: XXX ± 0.005 [0.127] 3. Pins are intended for insertion in hole rows on 0.300 [7.62] centers. 7 - 6 SECTION 7 ~ Om5 [0,381] MIN 0,200 MAX [5,08] 0125 [3."5] 0,07~I~1.905] 0,100 TYP (2,54] Packaging Plastic DIP Packages (continued) 28-Pin 0.6" Plastic DIP aJA= 50 °C/W 1.465 [37.21] OPTIONAL EJECTOR PIN ---$ 0.06 [1.524J R 0.600-0.620 UI5.240-15.74SU -/J7 0.009-0.015 [0.228-0.381J = ) 90-100 DEG I \ I f-- 0.610-0.650 --I 0.530-0.560 [13.46-14.22J ~ [0.015 [0.381J MIN I~~ [15.49-16.51J J L---l II ~0.~0~14~-~O~.0~28~~~ 0.200 MAX [5.08J "m ",>75' 0.07:I~1.905J _D_.1_00_ TyP [2.54J [0.36-0.58J TYP 40-Pin 0.6" Plastic DIP aJA=45°C/W r-------- 2.070 [525781 0.06 [[.524J R ~t:::::::':~:::::::::I,,~~·~:::" rFr 0.600-0.620 ~15 24~5.748D 0.009-0~ -~90-100 [0.228-0.381J DEG \ I I I--- -0.610-0.650 - - - - - --I [15.49-16.511 ~ 0.125-0 l35 [3.175 3.429] 20 [0.508] MIN I. ~~WW9~~mI",,~"'"'' ---IL.- J L-I L 86-94 DEG TYP 0.015.::0~t.. [0 381-0.533J 0.075 [[ 905] - Ql.9.Q. [254] TYP NOTES - Unless otherwise specified: 1. Dimensions are in inches [millimeters). 2. Tolerances are: XXX ± 0.005 [0.127) 3. Pins are intended for insertion in hole rows on 0.600 [15.24) centers. PACKAGING INFORMATION 7 -7 Packaging CERDIP Packages 16-Pin 0.3" CERDIP eJA = 90---95 ·C/W I" 0.025 C0635] R 0.750-0.785 [19,05-19,939] "I 1::::::~15~~;~ 0,051-0,061 [1,295-1.549] 0,290-0,320 [7,366-8,128] ~ II ~ [~~~~:~~~ 0,200 [5,080J MAX 0,125 [3.175] MIN 0,008-0,012 90-100 I [0,203-0,305] - DEG 86-94 DEG JLJ LJ 0,013-0,023 [0,330-0,584] [9.40-10,67J ~ [1.524] MAX 0,100 TYP [2.54] 20-Pin 0.3" CERDIP e JA = 85-90 ·C /W 0.025 [0.635] Q 0.290-0320 0053-0059 [[ 346-1_4_99_J_H-_ _0_'2_0_0_[_5'_08---,OJ MAX [7.366-8,128] ~_[~~:::::~~~:~:::;~ 19'37~~~ 42~ 1 [940-10,67J 86-~~p DEG 0,013-0,019 0.125 [3.175J JLJ LJ [0330-0 482J TYP NOTES - Unless otherwise specified: 1, Dimensions are in inches [millimeters]. 2. Tolerances are: .xxx ± 0.005 [0.127] 3. Pins are intended for insertion in hole rows on 0.300 [7.62] centers. 7 -8 SECTION 7 MIN --t--+ [~.'~~~J 0,090-0,110 [2,29-2,79J TYP MAX Packaging CERDIP Packages (continued) 24-Pin 0.3" CERDIP e JA = 75-80 °C /W 0,025 [0,635J Q 0,290-0320 [7,366-8.128) ~o 90-100 DEG 0,053-0,059 [1.346-1.499J 0020-0070 0,200 [5,080J MAX ---------+~----------_,---~_r 0.125 [3.175J [0'508-1.77~Jt~~ 008 - 0 012 86-94 DEG MIN Ft'==--'---f-- IIJ [o'203-0,305J -+-______L 0,060 MAX [1.524J 0,013-0,019 --H[0,330-0.482) [9.40-10,67J NOTES - Unless otherwise specified: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: XXX ± 0.005 [0.127] 3. Pins are intended for insertion in hole rows on 0.300 [7.62] centers. 24-Pin 0.6" CERDIP MAX~ e JA = 55-60°C /W Inl13li 0,515-0,530 [13,081-13.462) 0,025 [0,635J R 0,055-0,065 [1.397-1.6511 0,020-0,070 - 0,200 [5,080] MAX [0'508-1.77~] I, 0,008-0,012 [0,203-0,305) 86-94 DEG 0,125 [3.175] t 0,016-0,020 MIN j~J 0,060-0.100 [1.524-12,54] [0.406-0,508] [2,54] TYP NOTES - Unless otherwise specified: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: XXX ± 0.005 [0.127] 3. Pins are intended for insertion in hole rows on 0.600 [15.24] centers. PACKAGING INFORMATION 7 - 9 Packaging CERDIP Packages (continued) 28-Pin 0.6" CERDIP e JA = 55-60 °C/W 1.490 [37.846] MAX 0.515-0.530 [13.081-13.462] 0.025 [0.635] R 0.200 [5.080] MAX 0.020-0.070 [0'508-1.77~8 0.008-0.012 ! 0.125 [3.175] [0.203-0.305] 86-94 DEG MIN 0.060-0.100 [1.524-12.54] [0.406-0.508] [2.54] TYP 40-Pin 0.6" CERDIP e JA = 50-55 °C/W f - - - - - - - - - 2.060 [52.324J - - - - 0.515-0.550 [13.081-13.97) 0.025 [0.635J R 0.008-0.012 [0.203-0.305J l2.54J TYP NOTES - Unless otherwise specified: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: XXX ± 0.005 [0.127] 3. Pins are intended for insertion in hole rows on 0.600 [15.24] centers. 7 • 10 SECTION 7 Packaging Ceramic Sidebraze DIP Packages 16·Pin 0.3" Ceramic Sidebraze DIP 9JA=95 ·C/W PIN NO.1 0,054 [1.371] TYP 0.008-0.015 1[12.3i9]1 0,485 fIi ~L 0.165 • [4.1:~1]25 ~ [0,203-0,381lr MIN [3.175] 0,020-0060 [0,508-1.524] [7,62] REF [2.29-2.79] [0,381-0,584] 20·Pin 0.3" Ceramic Sidebraze DIP 9 JA = 85-90 ·C/W ~ 1.010 [25.654] ~ PIN NO, 1 JOENTi:J::::r:: 1~7569J 0,050 [1.27] TYP 0,008-0,015 [0,203-0,381] P9 11-- I .0,300 • [7.62] I 0,090-0,110 I-- [2,29-2,79] II 0,015-0,023 --j 1--[0,381-0,584] REF NOTES - Unless otherwise specified: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: .xXX ± 0.005 [0.127] 3. Pins are intended for insertion in hole rows on 0.300 [7.62] centers. PACKAGING INFORMATION 7· 11 Packaging Ceramic Sidebraze DIP Packages (continued) 24-Pin 0.3" Ceramic Sidebraze DIP 9 JA = 60-65 ·C /W ~ 1.220 [30.988J ~ PIN NO.1 IDENTi~I~:::I:: 13,·569J r 0.020-0.060 [0.508-1.524J 0.125 ~3M1I~5J FITi r D.008-D.0I5 [0.203-0.381J~.300 --I [7.62J I I-- --I ~ 0.090-0.110 [2.29-2.79J --I~ 0.D15-0.023 [0.381-0.584J REF NOTES - Unless otherwise specified: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: .xXX ± 0.005 [0.127] 3. Pins are intended for insertion in hole rows on 0.300 [7.62] centers. 24 PIN 0.3" CERAMIC SIDEBRAZE DIP 24-Pin 0.6" Ceramic Side braze DIP 9 JA =55-60 ·C/W 1.230 (31.242) 0.605 (15.367) PIN NO. 1 IDENT 0.125 J 0.008-0.015 <0.203-0.381) I 0.050 II 0.590-0.620 <14.99-15.75) REF --I II- 0.090-0.110 (2.29-2.79) NOTES - Unless otherwise specified: 1 . Dimensions are in inches [millimeters]. 2. Tolerances are: .xXX ± 0.005 [0.127] 3. Pins are intended for insertion in hole rows on 0.600 [15.24] centers. 7· 12 SECTION 7 --II 0.015-0.023 1-<0.381-0.584) Packaging Ceramic Sidebraze DIP Packages (continued) 28-Pin 0.6" Ceramic Side braze DIP aJA = 50-55 ·C/W 1.430 (36.322) 0.598 (15.189) PIN NO. 1 !DENT 0.050 0.008-0.015 [ LEADS VERTICAL TO 15 DEG. MAX DurwARD TYP -l I-- 0.090-0.110 (2.29-2.79) II --11-- -tt(~I~i5) 0.016-0.020 (0 406-0508) . . MIN . NOTES - Unless otherwise specified: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: .xXX ± 0.005 [0.127] 3. Pins are intended for insertion in hole rows on 0.600 [15.24] centers. PACKAGING INFORMATION 7 - 13 Packaging Ceramic Cavity Down DIP Packages 40·Pin 0.6" Ceramic Cavity Down DIP 9 JA = 30-40 ·C/W I 2.050 [52.07) =l == 0.075 [1.905] L ~r I O'048[1'218)TYP ~0.140 [3.556] LF .- 0.100 ~ [2.54) 0.525 [13.33) j L 0.100 TYP [2.54) 0.015-0.020 [0.381-0.508) JL I DAOO 0.015 LID [0.381] r9 ~:---lC~~~ 0.200 [5.08] ~ I- 10· -1- 0.600-0.660 [15.24-16.76) NOTES - Unless otherwise specified: 1 . Dimensions are in inches [millimeters]. 2. Tolerances are: .xXX ± 0.005 [0.127] 3. Pins are intended for insertion in hole rows on 0.600 [15.24] centers. 7·14 SECTION 7 0.070 [1.778) 0.008-0.012 [0.203-0.305) Packaging Plastic J-Lead (PLCC) Packages 28-Pin Plastic J-Lead 9 JA = 65-70 °C/W PIN NO 1 IDENT 0.165-0.1BO [419-4.57] 0.100-0.110 [254-2.79] 44-Pin Plastic J-Lead 9 JA = 50-55 °C/W PIN NO. 0,045 x 45 DEG PJN NO, 1 !DENT PIN NO, 1 !DENT 0.172 [1.143J - [J 7,526J SQ [2,565J NOTES - Unless otherwise specified: 1, Dimensions are in inches [millimeters], 2, Tolerances are: ,XXX ± 0,005 [0,127] 3, PLCe packages are intended for surface mounting on solder lands on 0,050 [1.27] centers, PACKAGING INFORMATION 7 - 15 Packaging Plastic J.Lead (PLCC) Packages (continued) 68·Pin Plastic J·Lead aJA =45-50 °C/W 0.048 [1.219] --.I L -11- 111 0.045 0029 [0736] [1.143] rr !--=- 0016 [0.406] 0.175 [ 4.445] ~ --I 0.020 - I [0.508fi MIN DETAIL ~0.113 L[2.87] I NOTES - Unless otherwise specified: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: .XXX ± 0.005 [0.127] 3. PLeC packages are intended for surface mounting on solder lands on 0.050 [1.27] centers. 7 • 16 SECTION 7 A 0.030 [0.762] Packaging Plastic J-Lead (PLCC) Packages (continued) 84-Pin Plastic J-Lead 9 JA = 35-40 ·C/W 1.190 [30,226] sa PIN 1 IDENT 1,154 [29,311 ] J 1,000 [ 25.4] sa REF ----L-----tI--l3l'- --=i1 ~ 0,099 [ 2, 514] 0.170 [4.318] ,035 R ,065 ~,02~9---l==~r=~~r-~t t ,016 t ,030 t ,020 MIN DETAIL A NOTES - Unless otherwise specified: 1 . Dimensions are in inches [millimeters]. 2. Tolerances are: XXX ± 0.005 [0.127] 3. PLCC packages are intended for surface mounting on solder lands on 0.050 [1.27] centers. PACKAGING INFORMATION 7 - 17 Packaging Plastic J-Lead (PLCC) Packages (continued) lOO-Pin Plastic J-Lead 9 JA =To be detennined. « PIN #1 IDENTIFIER (OPTION AL) 0.042-0. 056 [1.066-1.422] .-. ,--, l"LO <0 t<) l r \rP1N #1 (RE '¢ I"- ci ci F) '--' co en N 0 0 ci t t I... 1.345 [34.163]SQ o LO o ci ..I 0.200 [5.08] MAX 1.395 [35.433] SQ 0.109-0.130 [2.768-3.302] N en ~ (f) 0 N . 0 «'--' WLO -I ~ 0::0 W • ZO 0::0 Oz U o -I
    Source Exif Data:
    File Type                       : PDF
    File Type Extension             : pdf
    MIME Type                       : application/pdf
    PDF Version                     : 1.6
    Linearized                      : No
    Create Date                     : 2013:08:15 13:31:26-08:00
    Modify Date                     : 2013:08:15 19:32:46-07:00
    XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
    Metadata Date                   : 2013:08:15 19:32:46-07:00
    Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
    Format                          : application/pdf
    Document ID                     : uuid:e7f6e43c-b929-f546-ab3e-44ad26af4efc
    Instance ID                     : uuid:a8928baf-82d6-48bc-a92d-562782c60fe8
    Page Layout                     : SinglePage
    Page Mode                       : UseNone
    Page Count                      : 1106
    
    EXIF Metadata provided by EXIF.tools

Navigation menu