1991_DRAM_Data_Book 1991 DRAM Data Book
User Manual: 1991_DRAM_Data_Book
Open the PDF directly: View PDF .
Page Count: 1274
Download | |
Open PDF In Browser | View PDF |
SUMER 13555 Bishop's Court Brookfield, WI 53005 (414) 784-6641 DRAM DATA BOOK #M11T011 $HITACHI® When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. March 1991 @Copyright 1991, Hitachi America, Ltd. Printed in U.S.A. - - - - -- .HITACHI® DRAM DATA BOOK INDEX Section Introduction MOS Dynamic RAM High Speed BiCMOS Dynamic RAM MOS Dynamic RAM Modules Video RAM HITACHI SALES OFFICES SECTION 5, PAGE 1257 • HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 DRAM Data Book TABLE OF CONTENTS Section 1 Introduction Page PACKAGE INFORMATION............................................................... ... ................. 3 RELIABILITY OF HITACHI I.C. MEMORIES................................................................... 9 QUALITY ASSURANCE OF I.C. MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 OUTLINE OF TESTING METHOD............................................................................ 29 APPLICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Section 2 MOS Dynamic RAM • HM514256A1AL Series HM514256AP-6/7/8/10/12 HM514256AJP-6/7/8/10/12 HM514256AZP-6/7/8/10/12 HM514256ALP-6/718/10/12 HM514256ALJP-6/7/8/10/12 HM514256ALZP-6/7/8/10/12 256k x 4-bit CMOS DRAM. Fast Page Mode ........................ . 45 • HM514258A Series HM514258AP-6/7/8/10/12 HM514258AJP-6/7/8/10/12 HM514258AZP-6/718/10/12 256k x 4-bit CMOS Static Column DRAM ........................... . 59 • HM514266 Series HM514266AP-6/7/8/10/12 HM514266AJP-6/7/8/10/12 HM514266AZP-6/7/8/10/12 256k • HM511 OOOAl AL Series HM511 000AP-6/718/10/12 HM511 000AJP-6/718/10/12 HM511000AZP-6/718/10/12 HM511000ALP-6/7/8/10/12 HM511 000ALJP-6/7 18/10/12 HM511 000ALZP-6/718/10/12 1 Meg x 4-bit DRAM. Write per Bit .................................. . 72 x 1-bit CMOS DRAM ....................................... . 86 • HM511001A Series HM511001AP-6/718/10/12 HM511001AJP-6/7/8/10/12 HM511001AZP-6/7/8/10/12 1 Meg x 1-bit CMOS DRAM with Nibble Mode .....•.................. 98 • HM511 002A Series HM511002AP-6/7/8110/12 HM511 002AJP-6/7/8/1 0112 HM511002AZP-6/7/8/10/12 1 Meg x 1-bit CMOS DRAM with Static Column Mode ................ . 110 • HM511664 Series HM511664JP-8/10 HM511664ZP-8/10 64k x 16-bit DRAM. Write per Byte ..................•.....•......... 125 • HM511664/L Series HM511664JP-8/10 HM511664LJ-8/10 HM511664ZP-8/10 HM511664LZ-8/10 64k x 16-bit Low Power ........................................... . 155 • HM511665 Series HM511665JP-8/10 HM511665ZP-8/10 64k x 16-bit DRAM. Write per Bit ..................•................ 186 • HM511665/L Series HM511665JP-8/10 HM511665LJ-8/10 HM511665ZP-8/10 HM511665LZ-8/10 64k x 16-bit Low Power .......................•.•.................. 204 .HITACHI Hitachi America. Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1619 • (415) 589-8300 TABLE OF CONTENTS --------------------------------------------------___ • HM511666 Series HM511666JP-8/10 HM511666ZP-8/10 64k x 16-bit ........•........... . .. .. . . . . . . . ... . .. .. . . . . . . . . . . . . . . 223 • HM514100A Series 4 Meg x I-bit DRAM, Low Power & Super Low Power Version......... HM514100AJ/ALJ/ASLJ-S/7/8/10 HM5141 OOASIALSI ASLS-6/7 18/10 HM5141 00AZ/ALZ/ASLZ-6/7/8/1 0 HM5141 OOATI ALTI ASLT-6/718/10 HM5141 OOARIALRI ASLR-6/718/10 HM5141 OOATT I ALTTl ASLTT-6/7 18/10 HM5141 OOARRIALRRI ASLRR-6/7 18/10 247 • HM514400A Series 1 Meg x 4-bit DRAM, Low Power & Super Low Power Version......... HM514400AJI ALJI ASLJ-6/718/10 HM514400ASIALSI ASLS-6/718/10 HM514400AZI ALZI ASLZ-6/718/10 HM514400AT/ALT/ASLT-6/718/10 HM514400ARI ALRI ASLR-6/718/10 HM514400ATTI ALTTl ASLTT-6/7 18/10 HM514400ARRI ALRRI ASLRR-6/718/10 268 • HM514100 Series HM5141 00JP-8/1 0/12 HM5141 00ZP-8/1 0/12 4 Meg x I-bit DRAM, Fast Page Mode.............................. 289 • HM514100JP/ZP-7 HM514100JP-7 HM514100ZP-7 4 Meg x I-bit DRAM, Fast Page Mode.............................. 302 • HM514100L Series HM5141 00LJP-8/1 0/12 HM514100LZP-8/10/12 4 Meg x I-bit DRAM, Low Power VersionlFast Page Mode............ 315 • HM514101 Series HM514101JP-8/10/12 HM5141 01 ZP-8/1 0/12 4 Meg x I-bit DRAM with Nibble Mode.............................. 329 • HM514101A Series HM514101AJ-7/8/10 HM514101AS-718/10 HM514101AZ-718/10 4 Meg x I-bit DRAM with Nibble Mode.............................. 343 • HM514400 Series HM514400JP-8/10/12 HM514400ZP-8/10/12 1 Meg x 4-bit DRAM, Fast Page Mode.............................. 361 • HM514400L Series HM514400LJP-8/10/12 HM514400LZP-8/10/12 1 Meg x 4-bit DRAM, Low Power VersionlFast Page Mode............ 374 • HM514410 Series HM514410JP-8/10/12 HM51441 OZP-8/1 0/12 1 Meg x 4-bit DRAM, Write per Bit.................................. 390 • HM514410A Series HM514410AJ-8/718/10 HM51441 OAS-6/7 18/10 HM51441 OAZ-6/718/10 HM514410AT-6/7 18/10 HM514410AR-6/7/8/10 HM514410ATT-6/718/10 HM51441 OARR-6/7 18/10 1 Meg x 4-bit DRAM, Write per Bit.................................. 406 • HM514800 Series HM514800JP-7/8/10 HM514800ZP-7/8/10 512k x 8-bit DRAM................................................ 427 • HM514800L Series HM514800LJP-718/10 HM514800LZP-7/8/10 512k x 8-bit DRAM, Low Power Version............................. 444 ~HITACHI ii Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 TABLE OF CONTENTS • HM514900 Series HM514900JP-7/8/10 HM514900ZP-7/8/10 512k x 9-bit DRAM ............................................... . 461 • HM514260 Series HM514260JP-7/8/10 HM514260ZP-7/8/10 256k x 16-bit DRAM (2 CAS) ...................................... . 478 • HM514170 Series HM514170JP-7/8/10 HM514170ZP-7/8/10 256k x 16-bit DRAM (2 WE) ....................................... . 495 • HM514280 Series HM514280JP-7/8/10 HM514280ZP-7/8/10 256k x 18-bit DRAM (2 CAS) ...................................... . 512 • HM514190 Series HM514190JP-7/8/10 HM514190ZP-7/8/10 256k x 18-bit DRAM (2 WE) ....................................... . 529 • HM5116100 Series HM5116100J-61718/10 HM5116100Z-61718/10 16 Meg x 1-bit DRAM, Fast Page Mode ............................ . 546 • HM5116100L Series HM5116100LJ-61718/10 HM5116100LZ-6/7/8/10 16 Meg x 1-bit DRAM, Low Power Version/Fast Page Mode .......... . 566 • HM5116400 Series HM5116400J-61718/10 HM5116400Z-6/7/8/10 4 Meg x 4-bit DRAM, Fast Page Mode ............................. . 587 • HM5116400L Series HM5116400LJ-6/7/8/10 HM5116400LZ-61718/10 4 Meg x 4-bit DRAM, Low Power Version/Fast Page Mode ........... . 609 • HM571000 Senes HM571000JP-35R/40/45 1 Meg x 1-bit DRAM .............................................. . 633 • HM574256 Series HM574256JP-35R/40/45 256k x 4-bit DRAM ............................................... . 651 • HM574100 Series HM574100JP-35/40/45 4 Meg x 1-bit DRAM .............................................. . 667 • HM574400 Series HM574400JP-35/40/45 1 Meg x 4-bit DRAM .............................................. . 683 • HB56A18 Series HB56A18A-6HI7H/8A110A/12A HB56A18AT-6HI7H/8A110Al12A HB56A18B-6H/7H/8A110A/12A 1 Meg x 8-bit DRAM .............................................. . 701 • HB56C18 Series HB56C18A-8A110A/12A HB56C18AT-8A/10Al12A HB56C18B-8A110Al12A 1 Meg x 8-bit DRAM .............................................. . 706 • HB56G18 Series HB56G18B-7A18A110A HB56G18GB-7A18A110A 1 Meg x 8-bit DRAM .............................................. . 711 • HB56A48 Series HB56A48B/GB-8/10 HB56A48BR/GBR-6AI7 A18A11 OA HB56A48A-8/10 HB56A48AR-6AI7A18A110A HB56A48AT-8/10 HB56A48ATR-6A17 A18A/1 OA 4 Meg x 8-bit DRAM .............................................. . 722 Section 3 High Speed BiCMOS Dynamic RAM Section 4 MOS Dynamic RAM Modules ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 iii TABLE OF CONTENTS ------------------------------------------------------• HB56A19 Series HB56A 19A-6H/7H/SAll OAl12A HB56A19AT-6H/7H/8A110A/12A HB56A19B-6H/7H/8A110Al12A 1 Meg x 9-bit DRAM............................................... 73S • HB56A19L Series HB56A 19A-6L/7L18L11 OLl12L HB56A19AT-6L17L18L110Ll12L HB56A 19B-6L17L/SLll OL/12L HB56A 19GB-6L17L18L11 OL/12L 1 Meg x 9-bit DRAM............................................... 744 • HB56C19 Series HB56C19A-8A110Al12A HB56C19AT-8A110Al12A HB56C19B-8A110Al12A 1 Meg x 9-bit DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 • HB56G19 Series HB56G19A-6A17A1SA/10A HB56G19B/GB-6A17A/8A110A 1 Meg x 9-bit DRAM............................................... 760 • HB56A49 Series HB56A49B/GB-8/10 HB56A49BR/GBR-6A17Al8A11 OA HB56A49A-S/l0 HB56A49AR-6A17A18A110A HB56A49AT-8/10 HB56A49ATR-6A17Al8A11 OA 4 Meg x 9-bit DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 • HB56D25632 Series HB56D25632B-6A17 Al8A11 OAl12A 256k x 32-bit DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 • HB56D51232 Series HB56D51232SB-6A17A18A110Al12A 512k x 32-bit DRAM............................................... 799 • HB56D132 Series HB56D132BR-6A17A18A110A HB56D132BR-8/10 HB56D132SBR-6A17Al8A11 OA HB56D132SBR-8/10 1 Meg x 32-bit DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 • HB56D232B Series HB56D232B-S/l0/12 2 Meg x 32-bit DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 • HB56D232BS/SBS Series HB56D232BS-6A17AlSAll OA HB56D232SBS-6A17Al8A11 OA 2 Meg x 32-bit DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 • HB56D25636 Series HB56D25636B-85/10/12 256k x 36-bit DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 • HB56D51236 Series HB56D51236B-85/10/12 512k x 36-bit DRAM............................................... 854 • HB56D136B Series HB56D136B-8/10/12 1 Meg x 36-bit DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 • HB56D136B/S Series 1 Meg x 36-bit DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HB56D136B/BR/BS-6A17Al8A11 OA HB56D136B/BR-8/10 HB56D136SB/SBR/SBS-6A17 Al8A11 OA HB56D136SB/SBR-S/10 875 • HB56D236B Series HB56D236B-8/10/12 2 Meg x 36-bit DRAM ............................................. . 888 • HB56D236B/SB Series HB56D236B/BS-6A17 A/8A11 OA HB56D236B-S/l0 HB56D236SB/SBS-6A17Al8A11 OA HB56D236SB-8/10 2 Meg x 36-bit DRAM ............................................. . S97 • HB56A 140 Series HB56A 140B-6A17A/8A11 OA HB56A 140SB-6A17Al8A11 OA 1 Meg x 40-bit DRAM ............................................. . 909 ~HITACHI iv Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 TABLE OF CONTENTS 2 Meg x 40·bit DRAM ............................................ . 927 • HM63021 Series HM63021 P·28/35/45 2k x 8·bit Line Memory ........................................... . 947 • HM53051 Series HM53051p·45/60 256k x 4·bit Frame Memory ....................................... . 961 • HM53461 Series HM53461 P·10/12/15 HM53461 ZP·1 0/12/15 64k x 4·bit Multiport CMOS Video RAM ............................ . 971 • HM53462 Series HM53462p·10/12/15 HM53462Zp·10/12/15 64k x 4·bit Multiport CMOS Video RAM with Logic Functions ......... . 984 • HM534251 Series HM534251JP·10/11/12/15 HM534251Zp·1 0/11 112/15 256k x 4·bit Multiport CMOS Video RAM ........................... . 1004 • HM534251A Series HM534251 AJ·81 10 HM534251AZ·8/10 256k x 4·bit Multiport CMOS Video RAM ........................... . 1026 • HM534252 Series HM534252JP·10/11 112/15 HM534252ZP·1 01 11/12/15 256k x 4·bit Multiport CMOS Video RAM with Logic Functions ........ . 1046 • HM534253 Series HM534253JP·10/12/15 HM534253ZP·1 01 121 15 256k x 4·bit Multiport CMOS Video RAM with Extended Functions ..... 1070 • HM534253A Series HM534253AJ·8/10 HM534253AZ·8/10 256k x 4·bit Multiport CMOS Video RAM with Extended Functions ..... 1094 • HM538121 Series HM538121 JP·1 0/11 112/15 128k x 8·bit Multiport CMOS Video RAM ............................ . 1130 • HM538121 A Series HM538121AJ·8/10 HM538121AZ·8/10 128k x 8·bit Multi;>ort CMOS Video RAM ............................ . 1152 • HM538122 Series HM538122JP·10/11/12/15 128k x 8·bit Multiport CMOS Video RAM with Logic Functions ......... . 1170 • HM538123 Series HM538123JP·10/12/15 128k x 8·bit Multiport CMOS Video RAM with Extended Functions ..... . 1197 • HM538123A Series HM538123AJ·8/10 HM538123AZ·8/10 128k x 8·bit Multiport CMOS Video RAM with Extended Functions ..... . 1221 HITACHI SALES OFFICE LISTING........................................................................... 1257 • HB56A240 Series HB56A240B·6A17 Al8A11 OA HB56A240SB·6A17 Al8A11 OA Section 5 Video RAM ~HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589·8300 v • vi HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 Section 1 Introduction • Package Information • Reliability of Hitachi I.C. Memories • Quality Assurance of I.C. Memory • Outline of Testing Method • Application .HITACHI 2 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 • PACKAGE INFORMATION • Dual·in·line Plastic Unit: mm (inch) Scale 3/2 • Dp·188 • Dp·168 19.2 0.756 20.32 max(0.800max) 16 22.0 (0.866) 22.86mox(0.900max) 9 o C . -N-~~ ~ c ~ /I /I 2.54tO.25 (0.100t0.Q10) c • Dp·18C c 'E C 62(0'3001 Ft ~ ~ ~ -;-~~ 0.48tO.l0 0.019tO.004) c -" c:i N~ C) II' o.os~ne 0°-15 "? ~ 0°-15 )( (0.010~g:gg~) \ O.25~g:6~ I I I. _ ~ 'E 2.S4tO.25 (0.100tO.Ol0) (0.010~g:gg~) • 2.54tO.25 (0.1 ootO.D1 0) 10 (0.051) 29.88 (1.176) JO.48mox(1.200mox) I' 1 c:::::::: ::~ll I • •• ~ 11 (0.045) 0.48tO.l0 0.019tO.004) 1 0.48tO.l 0 0.019tO.004) , ~:::::::: :I~! 1 ~~~ ,P.r\ 'E~ /1 ~-~ ~ n 0.2s:,:g:6~,II: ~ W (0.010:':8:88~) " • Dp·20NC 24.8 (0.976) 25.40 max(1.000mox) C 62<0.300 x E ." r------------------,-~-E E , .. , • Dp·20NA (0.045) 10 • c ~-~ ~J.11J 2.54tO.2S (0.100tO.Ol0) ~~ (0.035) (0.051) 1 \(=----'--+--t~ I . _. #1 24.5 (0.965) 25.4 mox(1.000mox) 9 .11,1.3 (0.051) 11 1 • Dp·20N 22.26 (0.876) 22.86max(0.900max) ~ ~ ci ~ (0.010~g:gg~) 0°-15 ~ r ~-! I J.1#0.25~0.11 • \ 0 • 11 II E O. 25 + -O.05~ 0.48tO.l0 0.019tO.004) 62 (0'3001 )( x I I. _ ~ (0.051) 2.54tO.25 (0.100tO.Ol0) , 12 O.4S±O.10 0.019±0.004) ~HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 3 PACKAGE INFORMATION • Dual·in·line Plastic Unit: mm (inch) Scale 3/2 ·Dp·22N ·Dp·22NB 27.08 (1.066) 27.90max(I.098mox) 27.08 (1.066) 27. 90max(I.098 max) 22 2.s4tO.2s (0.100tO.Ol0) 0.48tO.l0 0.019tO.004) 2.54%0.25 (0.100to.ol0) • DP·24 0.l8tO.l0 0.019tO.004) ·Dp·24A 29.62(1.166) 30.48max(1.200max) ~ (0.035) 15.24 0.600 2.S4±O.2S Q.4S±Q., 0 D.D19±D.DDA) (0.100±0.o10) • Dp·24N O.25:!:g:6~ (0.010!8:88i) \ 2.s4±O.2s (0.100tO.Ol0) 0.48tO. ,0 0.0'9tO.004) • Dp·28 2.S4tO.2S (O.,ootO.O'O) 0.48±0.10 0.0'9±0.004) @HITACHI 4 Hitachi America, Ltd.• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 PACKAGE INFORMATION • Dual-ln-Iine Plastic Unit: mm (inch) Scale 3/2 • DP-28C ~ • DP-28N ~3~4~.7~0~1~.3~6~6~=- ~ ______.3S.S6max(1.ADOm.x) . ____ U 2.54:!:0.25 (0.100'0010) " 36.0 1.417 37.32max(1.470max) ~ O.AUO.1 O.019:tO OOA) • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300 5 PACKAGE INFORMATION • Zigzag-in-line Plastic Unit: mm (inch) Scale 3/2 • ZP-20 ·ZP-24 25.61 1.008 26.11 me" 1.028ma,,) • ZP-28 ·ZP-40 • 6 HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 PACKAGE INFORMATION Unit: mm (inch) Scale 3/2 • Flat Package (J-bend Leads) • CP-20D • CP-20DA 1](0.669) 17.27max(0.680max) 16.9(0.665) 17.27max(0.680max) 20 20 II II 'jg ~ rl3 ... ,"":g,,,,:~ o · 0 CI ~ ~g;;~ ~ '"'! aO '"'! o S. ~ '~H~~ .~~. I ,11,0.74(0.029) +1 ~ +1 +1 g;~~::l cOg"'d 1 10 JG (\')11'/1(\')0 o d dd ~n~ 0.74(0.029) 10 ~ .5 ·CP-28D 1817(0715) 18.54mox(0.730max) 28 15 l ~O ~~ ~ ~.s ~ 14 I J10.74(0.029) I ~ d~ d +I,r. +1 D :: S ~ r;:;::;;:;,;;:;;:;;;;;:;;;:;;:;d 1.270.050 QO.l0 0.004 QO.l0 0.004 • CP-40D 25.80(1.016) 26.16max(1.030max) 21 40 ~\g ~11 dct d +1° +1 ) ~~ ~f ~S:: 1 II 0.74{0.029) 20 ~ O. :1:0.10 (0.017±0.004 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 7 PACKAGE INFORMATION Unit: mm (inch) Scale 3/2 - TSOP (Thin Small Outline Package) -TFp-20DA -TFP-20DAR 80(0315) 82 max I 20 (0323 maxi 11 o 1 I 0.20±0 10 (0 008±0 004) ~l:~ ~~ "'-e. 10 1050 (0 020) $ I o 20±0 10 (0 008±0 004) 0.08 (0 003) M eo (0 004) I ~ o+1 .... 0 ~l:~and access time (tRAcl in high temperature pulse test. • Table 12. Reliability Data on MOS Memories Test Item Test Conditions HMSllOOOP (DIP) HMSllOOOJP (SOl) HM622S6FP (SOP) HM62128FP (SOP) EPROM (Cerdip) Sampies Failures Sam· pies Failures Sampies Failures Sampies Fail- ures Sampies Failures Temperature Cycling - SS·C to ISO"C 10 Cycle 3755 0 2786 0 3328 0 710 0 2790 0 Temperature Cycling - SS·C to ISO"C 500 Cycle ISO 0 200 0 482 0 105 0 450 0 Thermal Shock - 6S·C to ISO"C :S Cycle 77 0 100 0 76 0 77 0 80 0 Soldering Heat 260·C, 10 Seconds 22 0 22 0 22 0 22 0 22 0 Mechanical Shock I,SOOG, 0.5 ms 38 0 Variable Frequency 100 to 2,000 Hz 200 38 0 38 0 Constant-Acceleration 6000G • 14 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 Remarks ·6,000G Reliability of Hitachi IC Memories 2.4 Change of Electrical Characteristics on IC Memory The degradation of leBO and hFE are the main factors of degradation in inner cell transistor of bipolar memory. In acExample designed to operate in happen. Therefore no access time are obtime for HM10470 are Example of Time Change in Access Time for Bipolar Memory Device Name HMl0480-15 Test Conditions TA = 125°C, VEE = -5.2V Failure Criteria tAA = 15ns Failure Mechanism tual element designing, however, it is the range at which no degradation change of characteristics including served. Time dependence in access shown in Figure 1. Test Condition 20 Surface Degradation 2 V.. =-5.2V Ta=2S't MaxImum Average MarchIng Patlern Results: Access time is stabilized. Minimum 15 M -. c ."! 10 ,.. ~ 5 I 0 I I 500 1,000 l' 2.000 T,me 'hrl 0137-2 .. Figure 1. Time Change in Access Time for Bipolar Memory Example Example of Time Change in Access Time for Hi-BiCMOS Memory Device Name HMl00490 Test Conditions TA = 125°C, VEE = -4.5V All Bit Scanning Failure Criteria tAA = 15ns Failure Mechanism Surface Degradation 20 . Results: Access time is stabilized. T.Cooiooiao V.. =-4.5V Ta=25't MIrC~I'" 2. ,.,. ~ \\erll' \lInlnlum P.lltrn 15 .5 c c 10 ~ 5 L I 0 I 500 I 1,000 I 2,000 T,me 'hrl 0137-3 Figure 2. Ttme Change m Access Time for HI-BICMOS Memory • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 15 Reliability of Hitachi Ie Memories - - - - - - - - - - - - - - - - - - - - - - - - - Example Examples of Time Change in Vee Min and tAA for Hi-BiCMOS Memory Device Name HM6788P-2S Test Conditions TA = 12S·C, VEE AU Bit Scanning Failure Criteria Failure Mechanism = S.OV 5 ~ 4 Vee = 4.SV, tAA = 2S os Surface Degradation > -;; 3 E ~ II 2 Test Condition > V -5V Maximum Average 1 CCra=25'C Minimum 0 Marching Pattern 2 Results: Both of Vee (min) and tAA arestabi1ized. 0 '30 SOO 1.000 Tlma (hr) 2.000 Test Condition Same as above 25 .5 = - 20 ~ 15 ~ 0 500 1.000 2.000 T1me (hr) 0137-4 Figure 3. Time Change VCC Min and tAA for Hi-BICMOS Memory In Example of Time Change in VDD Min and tRAe for MOS Memory Example Device Name HMSllOOOP Test Conditions TA = 12S·C, Vee AU Bit Scanning = 7V 5 = 4.SV, AVDD = 1.0V Fru1ure Criteria VDD Failure Mechanism Surface Degradation Results: Access time (tAA> is stabilized and is within the failure criteria. • e• I oJ 2 ~ Test Condition Mar.bins pattern ~:.~c. 1 ~ Q i ~ Maximum Average Minimum 0 0 J,OOO 500 2.000 Time (br) 110 Test Condition Same as above 100 1 90 jlO Note: Test Accuracy is O.2V, 2 ns. 10 t I I I 10 0 SOD 1.000 1,000 Time (br) 0137-5 Figure 4. Time Change in VDD Min and tRAC for MOS Memory • 16 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 Reliability of Hitachi IC Memories 2.5 Failure Mode Rate Figures 5 and 6 show examples of failure more happened in users' application. Since IC memories require the finest pattern process technology, the percentage of failures, such as pinholes, defects on photoresist and foreign materials, tends to increase. To eliminate the defects in the manufacturing process, Hitachi has improved the process and performed 100% burn-in screening under high temperature. Hitachi has been collecting and checking customers' process-data and marketing data for higher reliability of our products. To analyze them is very helpful for the improvement of designing and manufacturing. 0137-7 0197-6 Figure 5. Failure Mode Rate of Bipolar Memory 3. RELIABILITY OF SEMICONDUCTOR DEVICES 3.1 Reliability Characteristics for Semiconductor Devices Hitachi semiconductor devices are designed, manufactured and inspected so as to achieve a high level of reliability. Accordingly, system reliability can be improved by combining highly reliable components along proper environmental conditions. This section describes reliability characteristics, failure types and their mechanisms in terms of devices. First, semiconductor device characteristics are examined in light of their reliability. (1) Semiconductor devices are essentially structure sensitive as seen in surface phenomenon. Fabricating the device requires precise control of a large number of process steps. Figure 6. Failure Mode Rate of MOS Memory (5) Semiconductor devices are characterized by volume production. Therefore, variations should be an important consideration. (6) Initial and accidental failures are only considered to be semiconductor device failures based on the fact that semiconductor devices are essentially operable semipermanently. However, wear failures caused by worn materials and migration should also be reviewed when electrode and package materials are not suited for particular environmental conditions. (7) Component reliability may depend on device mounting, conditions for use, and environment. Device reliability is affected by such factors as voltage, electric field strength, current density, temperature, humidity, gas, dust, mechanical stress, vibration, mechanical shock, and radiation magnetic field strength. (2) Device reliability is partly governed by electrode materials and package materials, as well as by the coordination of these materials with the device materials. (3) Devices employ thin-film and fine-processing techniques for metallization and bonding. Fine materials and thin film surfaces sometimes exhibit physically different character1stcs from the bulks. (4) Semiconductor device technology advances drastically: Many new devices have been developed using new processes over a short period of time. Thus, conventional device reliability data cannot be used in some cases. I I Rudom fadure NIlan : Constant future rate. (m =1) 1m. Welbull dlstnbuboD 1 form parameter I I i Tunl! (t) 0137-8 Figure 7. Typical Failure Rate Curve eHITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 17 Reliability of Hitachi Ie Memories Device reliability is generally represented by the failure rate. "Failure" means that a device loses its function, including intermittent degradation as well as complete destruction. Generally, the failure rate of electric components and equipment is represented by the bathtub curve shown in Figure 7. For semiconductor devices, the configuration parameter of the Wei bull distribution is smaller than 1, which means an initial failure type. Such devices ensure a long lifetime unless extreme environmental stress is applied. Therefore, initial and accidental failures can become a problem for semiconductor devices. Semiconductor device reliability can be physically represented as well as statistically. Both aspects of failures have been thoroughly analyzed to establish a high level of reliability. 3.2 Failure Types and Their Mechanisms 3.2.1 voltage near the minimum breakdown voltage BVos by raising internal voltage and when a strong electric field is established near the MaS device's drain resulting from reduced device geometry from 2 ",m to 0.8 ",m. Generated hot carriers may affect surface boundary characteristics on a part of the gate oxide film, resulting in degradation of threshold voltage (VTH) and counter conductance (gm). Hitachi devices have employed improved design and process techniques to prevent these problems. However, as process becomes finer, surface deterioration may possibly become a serious problem. (2) Electrode-Related Failures Electrode-related failures have become increasingly important as multi-layer wiring has become more complicated. Noticeable failures include electro-migration and AI wiring corrosion in plastiC sealed packages. 11' II II 2.5 ~= ~ I 3.0 3.5 T........... I/T (IO'/"K) 0137-12 Figure II. Relationship between Temperature and Time to 1% Failure (RH = 85%) Latch up is a problem unique to CMOS devices. This problem is a thyristor phenomenon caused by a parasitic PNP or NPN transistor formed in the CMOS configuration. Latch up occurs when an accidental surge voltage exceeding a maximum rating, a power supply ripple, an unregulated power supply and noise is applied, or when a device is operated from two sources having different set-up voltages. These cases can cause input or output current to flow in the opposite direction from usual flow, which triggers parasitic thyristors. This results in excessive current flowing between a power supply and ground. This phenomenon continues until the power is off or the flowing current is forced to be reduced to a certain level. Once latch up occurs in an operating device, the device will be destroyed. ~HITACHI 20 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 Reliability of Hitachi IC Memories Much effort should be made in designing circuits to prevent latch up. Latch up triggering input or output currents start to flow under the following conditions. Vin a < Vee or Vin < GND for input level < GND for input level Voul > Vee or VOUI Therefore, circuits should be designed so that no forward current flows through the input protection diodes or output parasitic diodes. @) Soft Errors When a particles are generated from uranium or thorium in a package the silicon surface of an LSI chip, electron-hole pairs are formed which act as noise to data lines and other floating nodes, causing temporary soft errors. This phenomenon is shown in Figure 14. Only electrons from among the electron-hole pairs are only collected to a memory cell. As a result, the cell changes from a state of 1 to 0, which is a soft error. Hitachi devices have been subjected to simulation and irradiation tests to prevent soft errors. In some cases, organic material, PIQ, is applied to the surface of the device. 0137-15 Figure 14. Soft Error Caused by a Particles in Dynamic Memory • Table 13. Failure Causes and Mechanism Failure Related Causes Failure Mechanisms Failure Modes Passivation Surface Oxide Film, Insulating Film between Wires Pin Hole, Crack, Uneven Thickness, Contamination, Surface Inversion, Hot Carrier Injected Withstanding Voltage Reduced, Short, Leak Current Increased, hFE Degraded, Threshold Voltage Variation, Noise Metallization Interconnection, Contact, Through Hole Flaw, Void, Mechanical Damage, Break Due to Uneven Surface, Non-ohmic Contact, Insufficient Adhesion Strength, Improper Thickness, Electromigration, Corrosion Open, Short, Resistance Increased Connection Wire Bonding, Ball Bonding Bonding Runout, Compounds between Metals, Bonding Position Mismatch, Bonding Damaged Open, Short Resistance Increased Wire Lead Internal Connection Disconnection, Sagging, Short Open, Short Diffusion, Junction Junction Diffusion, Isolation Crystal Defect, Crystallized Impurity, Photo Resist Mismatching Withstanding Voltage Reduced, Short Die Bonding Connection between Die and Package Peeling Chip, Crack Open, Short, Unstable Operation, Thermal Resistance Increased Package Sealing Packaging, Hermetic Seal, Lead Plating, Hermetic Package and Plastic Package, Filler Gas Integrity, Moisture Ingress, Impurity Gas, High Temperature, Surface Contamination, Lead Rust, Lead Bend, Break Short, Leak Current Increased, Open, Corrosion Disconnection, Soldering Failure Foreign Matter Foreign Matter in Package Dirt, Conducting Foreign Matter, Organic Carbide Short, Leak Current Increased Input/Output Pin Electrostatistics, Excessive Voltage, Surge Electron Destroyed Short, Open, Fusing Disturbance a Particle Electron Hole Generated Soft Error High Electric Field Surface Inversion Leak Current Increased @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 21 Reliability of Hitachi Ie Memories (6) Fine Geometry Related Problems In response to higher integration requirements for memories and microcomputers, LSI geometry has been reduced in the way of 3 ,..,m ~ 2 ,..,m ~ 1.3 ,..,m ~ 0.8 ,..,m. However power supply has not been scaled down used for 5V, only line dimensions have been fined increasingly. Prob· lems associated with finer geometry are shown in Table 14. • Table 14. Finer Geometry Related Problems Item Problems 5V Single Supply Voltage • Breakdown Voltage of Gate Oxide Films • Si02 Defects Horizontal Dimension Reduction • • • • • Vertical and Horizontal Dimension Reduction • Higher Breakdown Voltage Not Permitted • Electrostatic Discharge Resistance Reduced Soft Errors by a Particles Al Reliability Reduced CMOS Latch Up Mask Alignment Margin Reduced Hot Carriers Countermeasure Oxide Film Formation Process Improved • Cleaning • Gettering • Screening Surface Passivation Film Improved • Metallization Improved • Design/Layout Improved • Process Improved Use of Low Voltage Examined • Configuration Improved • Protection Circuits Enhanced ~HITACHI 22 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 • QUALITY ASSURANCE OF IC MEMORY 1. Purposes of Test Site are as follows: 1. VIEWS ON QUALITY AND RELIABILITY Hitachi basic views on quality are to meet individual users' purpose and their required quality level and also to maintain the satisfied level for general application. Hitachi has made efforts to assure the standardized reliability of our IC memories in actual usage. To meet users' requests and to cover expanding application, Hitachi performs the following: (1) Establish the reliability in design at the stage of new product development. (2) Establish the quality at all steps in manufacturing process. (3) Intensify the inspection and the assurance of reliability of products. (4) Improve the product quality based on marketing data. Furthermore, to get higher quality and reliability, we cooperate with our research laboratories. With the views and methods mentioned above, Hitachi makes the best efforts to meet the users' requirements. 2. RELIABILITY DESIGN OF SEMICONDUCTOR DEVICES 2.1 Reliability Target Establishment of reliability target is important in manufacturing and marketing as well as function and price. It is not practical to determine the reliability target based on the failure rate under single common test condition. So, the reliability target is determined based on many factors such as each characteristics of equipment, reliability target of system, derating applied in deSign, operating condition and maintenance. 2.2 Reliability Design Timely study and execution are essential to achieve the reliability based on reliability targets. The main items are the design standardization, device design including process and structural design, design review and reliability test. (1) DeSign Standardization Design standardization needs establishing design rules and standardizing parts, material, and process. When design rules are established on circuit, cell, and layout design, critical items about quality and reliability should be examined. Therefore, in using standardized process or material, even newly developed products would have high reliability, with the exception of special requirement on function. (2) Device Design It is important for device design to consider total balance of process deSign, structure design, circuit and layout design. Especially in case of applying new process or new material, we study the technology prior to development of the device in detail. • Making clear about fundamental failure mode. • Analysis of relation between failure mode and manufacturing process condition. • Analysis of failure mechanism. • Establishment of QC point in manufacturing. 2. Effects of evaluation by Test Site are as follows: • Common fundamental failure mode and failure mechanism in devices can be evaluated. • Factors dominating failure mode can be picked up, and compared with the process having been experienced in field. • Able to analyze relation between failure causes and manufacturing factors. • Easy to run tests. 2.3 Design Review DeSign review is a method to confirm systematically whether or not design satisfies the performance required including by users, follows the specified ways, and whether or not the technical items accumulated in test data and application data are effectively applied. In addition, from the standpoint of competition with other products, the major purpose of design review is to insure quality and reliability of the product. In Hitachi, design review is performed in designing new products and also in changing products. The followings are the itmes to consider at design review. (1) Describe the products based on specified design documents. (2) Considering the documents from the standpOint of each participant, plan and execute the sub-program such as calculation, experiments and investigation if unclear matter is found. (3) Determine the contents and methods of reliability test based on deSign document and drawing. (4) Check process ability of manufacturing line to achieve design goal. (5) Arrange the preparation for production. (6) Plan and execute the sub-programs of design changes proposed by individual speCialists, for tests, experiments and calculation to confirm the design change. (7) Refer to the past failure experiences with similar devices, confirm the prevention against them, and plan and execute the test program for confirmation of them. In Hitachi, these study and decision at deSign review are made using the individual check lists according to its objects. (3) Reliability Test by Test Site Test site is sometimes called Test Pattern. It is useful method for evaluating reliability of designing and processing ICs with complicated functions. ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 23 Quality Assurance of IC Memory 3.2 Qualification 3. QUALITY ASSURANCE SYSTEM OF SEMICONDUCTOR DEVICES 3.1 Activity of Quality Assurance To assure the quality and reliability, the qualification tests are done at each stage of trial production and mass produc· tion based on the reliability design described in Section 2. The following items are the general views of overall quality assurance in Hitachi; The following are the views on qualification in Hitachi: (1) Problems are solved in each process so that even the potential failure factors will be removed at final stage of production. (2) Feedback of information is made to insure satisfied level of process ability. (1) From the standpoint of customers, qualify the products objectively by a third party. (2) Consider the failure experiences and data from custom· ers. (3) Qualify every change in design and work. (4) Qualify intensively on parts and materials and process. As the result, we assure the reliability. (5) Considering the process ability and factor of manufactur· ing fluctuation, establish the control points in mass pro· duction. Considering the views mentioned above, qualification shown in Figure 1 is done. Step Contents lTUJlt't DesIgn RevIew ~Pf'('lflc.tlUn t Ill'' Kn II Trl,,1 I'roductmn MatHlal,. ParI!. ",pproval Jr- Characterlstl<..s of Material and ParIs Appearance DimensIOn Heat R~slstance II Purpose Characteristics Approval Ir- ME-chanlcal Elect rlcal O'hers E1E"ct ncal Character!st ICS Function VIJ!tagt-' Current Temperature ConfirmatIOn of CharacterIstics and Reltabiltty of Matertals and Parts Confirmation of Target Spec. Mainly about Electrtcal Characteristics Otht"r~ Appearance. DimenSion Ii Quality Approval (I) Ii Qualtty Approval (2) I Mass IrIr- Reltabiltty Test Life Test Thermal Stress MOIsture Resistance MechanIcal Stress Othe rs Reliabiltty Test Conltrmation of QualIty and Reliabiltty In Design Confirmation of Quality Process Check same as and Reliability in Mass Qua I ity Approva I (1) Production ,I Product Ion 0138-1 Figure 1. Flow Chart of Qualification ~HITACHI 24 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819' (415) 589·8300 Quality Assurance of 3.3 Quality and Reliability Control in Mass Production Ie Memory 3.3.1 Quality Control on Parts and Materials To assure quality in mass production, quality is controlled functionally by each department, mainly by manufacturing department and quality assurance department The total function flow is shown in Figure 2. With the tendency toward higher performance and higher reliability of devices, quality control of parts and materials becomes more important The terms such as crystal, lead frame, fine wire for wire bonding, package and materials required in manufacturing process like mask pattern and chemicals, are all subject to inspection and control. Quality Control Process Method Inspection on Mater .. 1 and - Parts for Semiconductor - - Lot Sampling. Confirmation of Quality Level DevIces Manufacturing Eq"ipment. _ _ _ EnvIronment. Sub-mater .. l. Confirmation of Quality Level Worker Control Lot Samp hng. Inne r Process Quality Control Conhrmation of Quality Level 100% InspectIon on Testing, Appearance and Electncal InspectIOn CharacteristIcs Sampling Inspection on Lot Sampling Appea ranc e and E lec tnca I Cha racte ns t ic s ConfirmatIOn of ReliabilIty Test Quality Level. Lot Sampling r-----------, I I I I Quality Information, ClaIm FIeld Expenence General Quality InformatIOn I I Feedback of Information I I I' - _ _ _ _ _ _ _ _ _ _ .JI 0138-2 Figure 2. Flow Chart of Quality Control in Manufacturing Process @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 25 Quality Assurance of IC Memory Besides qualification of parts and materials stated in 3.2, quality control of parts and materials is defined in incoming inspection. Incoming inspection is performed based on its purchase specification, drawing and mainly sampling test based on MIL-STD-105D. The other activities for quality assurance are as follows: (1) Technology Meeting with Vendors (2) Approval and Guidance of Vendors (3) Analysis and tests of physical chemistry The typical check points of parts and materials are shown in Table 1. • Table 1. Quality Control Check Points of Parts and Material (example) Material Parts Important Control Items Appearance Wafer Mask Fine Wire for Wire Bonding Frame Ceramic Package Plastic Dimension Sheet Resistance Defect Density Crystal Axis Point for Check Damage and Contamination on Surface Flatness Resistance Defect Numbers Appearance Dimension Resistoration Gradation Defect Numbers, Scratch Dimension Level Appearance Contamination, Scratch, Bend, Twist Dimension Purity Elongation Ratio Uniformity of Gradation Purity Level Mechanical Strength 3.3.2 Inner Process Quality Control To control inner process quality is very significant for quality assurance of devices. The quality control of products in every stage of production is explained below. Figure 3 shows inner process quality control. (1) Quality Control of Products in Every Stage of Production Potential failure factors of devices should be removed in manufacturing process. Therefore, check points are set up in each process so as not to move the products with failure factors to the next process. Especially, for high reliability devices, manufacturing lines are rigidly selected in order to control the quality in process. Additionally we perform rigid check per process or per lot, 100% inspection in proper processes so as to remove failure factors caused by manufacturing fluctuation, and screenings depending on high temperature aging or temperature cycling. Contents of controlling quality under processing are as follows: • Control of conditions of equipment and workers and sampling test of uncompleted products. • Proposal and execution of working improvement. • Education of workers • Maintenance and improvement of yield • Picking up of quality problems and execution of countermeasures toward them. • Communication of quality information. (2) Quality Control of Manufacturing Facilities and Measuring Equipment Contamination, Scratch Dimension Level Manufacturing facilities have been developed with the need of higher devices in performance and the automated production. It is also important to determine quality and reliability. Bondability, Solderability Heat Resistance In Hitachi, automated manufacturing is promoted to avoid manufacturing fluctuation, and the operation of high performance equipment is controlled to function properly. Appearance Dimension Leak Resistance Plating Mounting Characteristics Electrical Characteristics Mechanical Strength Contamination, Scratch Dimension Level Airtightness Bondability, Solderability Heat Resistance As for maintenance inspection for quality control, daily and periodically inspections are performed based on specification on every check point. Composition Characteristics of Plastic Material Appearance Dimension Processing Accuracy Plating Mounting Characteristics Electrical Characteristics Thermal Characteristics Molding Performance Mounting Characteristics As for adjustment and maintenance of measuring equipment, the past data and specifications are clearly checked to keep and improve quality. (3) Quality Control of Manufacturing Circumstances and Submaterial. Mechanical Strength Quality and reliability of devices are affected especially by manufacturing process. Therefore, we thoroughly control the manufacturing circumstances such as temperature, humidity, dust, and the sub-materials like gas or pure water used in manufacturing process. Molding Performance Mounting Characteristics Dust control is essential to realize higher integration and higher reliability of devices. To maintain and improve the clearness of manufacturing site, we take care of bUildings, facilities, air-conditioning system, materials, clothes and works. Moreover, we periodically check on floating dust in the air, fallen dust or dirtiness on floor. ~HITACHI 26 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 Quality Assurance of Pr_. Control Point Ie Memory Purpo.. of Control Purchase of Material Wafer Characte r istics. Appea rance Wafer Surface Oxidahon Oxidation Appearance. ThIckness of OXIde Film Inspection on Surface OxidatIon Photo ResIst Scratch. Removal of Crystal Defect Wafer Assurance of ResIstance Pinhole. Scratch Photo Resist Inspecllon on Photo ResIst o PQC Level Check D,ffusIOn Dimension, Appearance DiffusIOn Diffusion Depth. Sheet Dimension Level Check of Photo Res ist Diffusion Status Resistance InspectIOn on DiffusIon o PQC Leve I Check EvaporatIon Gate WIdth Characteristics of Oxide Film Breakdown Voltage ration Thickness of Vapor Film. Scratch. Contamination Wafer Thickness. VTH Character is- Evapo- Inspection on Evaporahon o PQC Leve I Check Wa fe r Inspec lion tics Inspechon on ChIp Electrical CharacteristIcs ChIp ScrIbe Inspection on Chip Appearance o PQC Lot Judgement Chip Assembltng Assembltng Control of BasIc Parameters (VTH. etc) Cleaness of surf ace. Prior Check of VIH Breakdown Voltage Check Assurance of Standard ThIckness Prevention of Crack. Quality Assurance of Scribe Electrical Characteristics Appearance of ChIp Frame Appearance after ChIp Bo~dlng Appearance after W,re Bonding Pull Strength. Compresion Width. Shear Strength Appearance after Assembling o PQC Leve I Check InspectIon after Assembling o PQC Lot Judgement Package Sealing Sealing oPQC Level Check MarkIng Final Electrical Inspection OFailure Analysis Quality Check of Chip Bonding Quality Check of W tre Bonding PreventIon of Open and Short Appearance after Sealing Outline. Dimension Marking Strength Guarantee of Appearance and Dimens ion AnalysIs of Failures. Failure Mode. Mechanism Feedback of AnalysIs Information Appearance Inspection Sampling Inspection on Products Receiving Shipment 0138-3 Figure 3. Example of Inner Process Quality Control @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 27 Quality Assurance of Ie Memory - - - - - - - - - - - - - - - - - - - - - - - - - - - The inspection is executed not only to confirm that the products meet users' requirement, but to consider potential factors. Our lot inspection is based on MIL-STD105D. 3.3.3 Final Tests and Reliability Assurance (1) Final Tests Lot inspection is done by quality assurance department for the product passed in 100% test in final manufacturing process. Though 100% of passed products is expected, sampling inspection is subjected to prevent mixture of failed products by mistake. r-----------I I I (2) Reliability Assurance Tests To assure reliability, the reliability tests are performed periodically, and performed on each manufacturing lot if user requires. - - - - - - - - - - - - - - - - - ----1 r-----~------~ Failure Analysis I I I I I I Countermeasure Execution of Countermeasure I I I I I I I I I I I I I I I I Report I I Quality Assurance I I I IL ___________ _ II Follow-up and Confirmation of Countermeasure Execution I I Report I --------------------~ Dept. Sa les Eng inee r 109 Dept. Reply Customer 0138-4 Figure 4. Process Flow Chart of Coping with Failure to a Customer ~HITACHI 28 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 • OUTLINE OF TESTING METHOD 1. INSPECTION METHOD 2. MARCHING PATTERN Compared to conventional core memories, IC memories contain all peripheral circuits, such as the decoder circuit, write circuit and read circuit. As a result, assembly and electrical inspection of ICs are all performed by IC manufacturers. Consequently, as the electrical inspection of IC memories are becoming more systematic, conventional IC inspection facilities are becoming useless. This has led to the development and introduction of a memory tester with pattern generator to generate the inspection pattern of the memory IC at high speed. A function test for such as TTL gates can be performed even by a simple DC parameter faCility. However, when the address input becomes multiplexed as in 16k, 64k and 256k memory, even the generation of the function test pattern becomes a serious problem. The marching pattern, as its name indicates, is a pattern in which "1 "s march into all bits of "O"s. For example, a simple addressing of 1S-bit memory is described below. In the memory IC inspection, its quality cannot be judged by DC test on external pins only, because the number of the element such as transistor which can be judged in the DC test is only 1/1000 of all elements. The following are the address patterns proposed to inspect whether the internal circuits are functioning correctly. (1) (2) (3) (4) (5) (6) (7) All "Low", All "High" Checker Flag Stripe Pattern Marching Pattern Galloping Waling Ping-Pong (1) Clear all bits ........................... See Fig. 1 (a) (2) Read "0" from Oth address and check that the read data is "0". Hereafter, "Read" means "checking and judging data" (3) Write "1" on Oth address ................ See Fig. 1 (b) (4) Read "0" from 1st address. (5) Write "1" on 1st address. (S) Read "0" from nth address. (7) Write "1" on nth address ................ See Fig. 1 (c) (8) Repeat (6) to (7) to the last address. Finally, all data will be "1". (9) After all data become "1", repeat from (2) to (8) replacing "0" and "1". In this method, 5N address patterns are necessary for the N-bit memory. a Those are not all, but only representative ones. There are the pattern to check the mutual interference of bits and the pattern for the maximum power dissipation. Among the above mentioned patterns, those of (1) to (4) are called N pattern, which can check one sequence of N bit IC memory with the several times of N patterns at most. Those of (5) to (7) are called N2 pattern, which need several times of N2 patterns to check one sequence of N bit IC memory. Serious problem arises in using N2 pattern in a large-capacity memory. For example, inspection of 1Sk memory with galloping pattern takes a lot of time = about 30 minutes. (1), (2) and (3) are rather simple and good methods, however, they are not perfect to find any failure in decoder circuits. Marching is the most simple and necessary pattern to check the function of IC memories. $ b c 0139-1 Figure I. Addressing method for 16-bit memory in the Marching pattern HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 29 • APPLICATION 1. VIDEO RAM 1.1 Multiport Video RAM Effective graphic display memory is realized by using the random port of the RAM part for graphic processor drawing and the serial port of the SAM part for CRT display. Figure 1·1 shows general idea of video RAM. Multiport video RAM provides an internal data register (SAM) with the memory (RAM). Both of them can be accessed asynchronously. RAM SAM I DRAM ~j'_:_·"_- M-",~..,-,... ~i["'J -~CRT Random port Drawing _rt_--.-JI 0140-18 Figure 1-1. General Idea of Multi-Port Video RAM Figure 1-2 shows the block diagram of the 256-kbit multiport video RAM HM53461, and Table 1-1 shows the operation modes of the HM53461. DT/OE Dynamlr RAM 110 memory cells WE~--~------~ L_1---~ SC SOE 0140-19 Figure 1-2. Block Diagram of HM53461 The operation modes shown in Table 1-1 are described as follows. • Table 1-1. Operation Modes of HM53461 At the Falling Edge of RAS CAS DT/OE WE SOE H H H X H H L H L H L RAM Modes SAM Modes SIlO Direction Notes ReadIWrite SinlSout 1,2,3 X Temporary Write Mask Data Program SinlSout 1,2,3 H X Read Transfer Sout L L Write Transfer Sin H L L H Pseudo Transfer Sin L X X X CBRRefresh SinlSout 2 1,2 H: High L: Low X: Don't Care Notes: I. Transfer cycle executed previously defines SIlO direction. 2. SIlO is in high impedance state with SOE high, even if the direction is Souto 3. The HM53461 starts write operation if WE is low at the falling edge of CAS or become low between the falling edge of CAS and the rising edge of RAS. ~HITACHI 30 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 Application Read/Write Operation: Read/write is performed on the random port in the same sequence as for a dynamic RAM (Figure 1-3). The HM53461 starts the read operation with WE high and the write operation at the falling edge of WE. AO-A? Read Transfer Operation: In this cycle, the HM53461 transfers the data of one row in RAM (1024 bits), which address is specified at the falling edge of RAS, to SAM (Figure 1-5). The start address in SAM can be programmed at the falling edge of CAS in this cycle. After data transfer, the serial port turns to serial read mode at the rising edge of DT/OE. AO-A? DRAM memory cen DRAM SilO 1 - SI/O< memory ",II 0140-22 1101-1/04 Figure 1-5. Read Transfer Operation 0140-20 Figure 1-3. ReadIWrite Operation Temporary Write Mask Set and Temporary Masked Write Operation: The HM53461 provides temporary masked write operation which inhibits to write data bit-by-bit (write mask) during one RAS cycle. Temporary write mask set function defines the bits to be inhibited (Figure 1-4). This operation puts the data on 1/°1-1/°4 into the internal temporary write mask register. When 0 is programmed to the register, writing to the corresponding bit is inhibited. Write Transfer Operation: In this cycle, the HM53461 transfers the data in the SAM data register (1024-bits) to one row in RAM, which address is specified at the falling edge of RAS (Figure 1-6). The start address in SAM can be programmed in this cycle. After data transfer, serial port turns to serial write mode. AO-A? The temporary write mask register is reset at the rising edge of RAS. AO-A? DRAM memory ",II 51/01- 51/04 0140-23 DRAM ........ Figure 1-6. Write Transfer Operation cell 1/01-1/04 0140-21 Figure 1-4. Temporary Masked Write Operation @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 31 Application Pseudo Transfer Operation: This operation switches the serial port to serial write mode (Figure 1-7). It does not perform data transfer between RAM and SAM. Sam start address can be programmed in this cycle. Serial Read/Write Operation: The HM53461 reads/writes the contents of the SAM data register in serial at the rising edge of SC (serial clock input) (Figure 1-9). The address for serial access is generated by the internal address pointer, independently of random port operation. It should be considered that serial access is restricted in transfer cycles. The SAM, employing static-type data registers, requires no refresh. AO-A7 I Column latch / I~ ~ Row decode, llit" \ DRAM .~ j memory ",II ~ Q 0140-24 Figure 1-7. Pseudo Transfer Operation 51/01-51/04 JI 0140-26 CAS Before RAS Refresh Operation: The HM53461 performs refresh by using the internal address counter in this operation (Figure 1-8). I CoI.mn Figure 1-9. Serial ReadIWrite Operation The HM53462 is a multiport video RAM, adding logic operation capability to ttie advantages of HM53461. I ra.;;t Figure 1-10 shows the block diagram. Table 1-2 describes the operation modes. latch~ DRAM '"""0,>" ",II 0140-25 Figure 1-8. CAS Before RAS Refresh ,----------------RAM I -----I SAM I I DRAM memory cells 1/0 51/0 - Random Soria! POrt I __ WE-+--------~---~---------------J ______ _ _ _ _ _ _ _L +-______~ _......lI ____ sc SOE 0140-27 Figure 1-10. Block Diagram of HM53462 ~HITACHI 32 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 Application • Table 1-2. Operation Modes of HM53462 At the Falling Edge of RAS RAM Modes SAM Modes CAS DTIOE WE SOE H H H X ReadIWrite SinlSout 1,2,3 H H L X Temporary Masked Write ~n/Sout 1,2,3 H L H X Read Transfer Sout H L L L Write Transfer Sin H L L H Pseudo Transfer Sm L X X X CAS Before RAS Refresh SmlSout 1,2 X Logic Operation Program (CBR Refresh) SinlSout 1,2 X L L SIlO Direction Notes 2 H: High L: Low X: Don't Care Notes: I. Transfer cycle previously executed defines SIlO direction. 2. SIlO is in high impedance with SOE high, even if SIlO direction is Souto 3. HM53462 writes if WE is low at the falling edge of CAS or becomes low between the falling edge of CAS and the rising edge ofRAS. Logic Operation Programming: This function programs a logic operation (Figure 1-11). The logic operation is available uintil re-programmed or reset. In logic operation mode, HM53462 performs read-modify-write internally when data is written into random port. The result of the logic operation between memory data and written data is put into the address from which the memory data is transferred. In the logiC operation programming cycle, the mask register, which differs from the temporary mask register, is also programmed. It is available until reprogrammed. t I ', :: I I :i illill I L.J" L_ V . i 0-- i: ::::::r::: "0 ~ .i d <3 • Initialization of logiC operation mode (HM53462). The logic operation programming cycle should be executed before access to the random port to initialize logiC operation mode after power on. At this point, the operation codes (0101) and all 1 write mask data are recommended. ~ ~~ Row , -~±'----------'t' : DRAM 1 memory I cell , , 1.2 Line Memory Hitachi has produced a line memory for line buffers with simple circuits, providing specific functions as described below. The line buffer can improve picture quality by storing 1 horizontal line data. It has following features. I ~I I--------~ .... _ _ _ _ _ _ ,I , I ~ • Capacity to store 1 horizontal line data L.J • High-speed operation matching the sampling speed of PAL TV signal (4 fsc/8 fsc) or NTSC TV signal (4 fsc/8 fsc). I I I I I • Bypass Capacitor. One bypass capacitor should be inserted between Vee and Vss to each device. The Vee pin should be connected to the capacitor by the shortest path. A capacitor of several ftF is suitable. • Negative Voltage Input. Negative polarity input level to input pin or I/O pin should be under -W. In this range, it has no effect on deVice characteristics or RAM/SAM data retention. AO-A7 :' ::, ' Notes: Notes on using HM53461 /HM53462 are as follows: • Dummy RAS Cycle. Devices should be initialized by 8 dummy RAS cycles (minimum) before access to random port. Refresh cycle can be inserted for initialization. It is recommended that the system be initialized by dummy RAS cycle in the automatic reset time of the processor. I , I , I • Separate data inputs/outputs and capability of serial data inputs and outputs. 1/01-1/04 (dotted lanes mdlcate wnte In JOllie operation mode) 0140-28 Figure 1-11. Logic Operation Programming The conventional line buffer composed of high speed static RAMs requires separate input! output for double buffer organization. It also requires interleaving for high speed operation, matching 4 fsc/8 fsc, where fsc is the subcarrier frequency. In addition, external circuits are needed for serial address scan. @HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 33 Application The line memory provides all of these functions. Figure 1-12 shows the standard ogranization of a conventional memory buffer and Figure 1-13 shows the block diagram of line memory. The Hitachi HM63021 is a 2048-word x 8-bit line memory storing 2 horizontal lines of data. It has five different modes for various video graphic system applications. It realizes high speed operations for PAL and NTSC TV signals, and dissipates little power employing 1.3 ).Lm CMOS technology and static-type memory cells. The features of the HM63021 are described as follows: • Five modes for various video graphic system applications -Delay line mode -Alternate 1H/2H delay mode - TBC (Time-Base Corrector) mode -Double speed conversion mode -Time-base compression/expansion mode AdM.ss------t • High speed cycle time -HM63021-34: 34 ns min (corresponds to 8 fsc of NTSC TV signal) -HM63021-28: 28 ns min (corresponds to 8 fsc of PAL TV signal). Address Concrol 0140-29 Figure 1-12. Standard Organization of Conventional Line Buffer I----+---~k Line memory in the system using digital signal processing technologies offers following applications: 1. 2. 3. 4. 5. 6. comb filter double-speed conversion (non-interface) compression/expansion of graphics (picture-in-picture) dropout canceller time-base corrector noise reducer 0140-30 Figurer 1-13. Block Diagram of Line Memory ~HITACHI 34 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 Application normal read/write cycle or a refresh cycle. When using an internal refresh counter, eight or more CAS before RAS refresh cycles are required as dummy cycles. 2. DYNAMIC RAM 2.1 Dynamic RAM Memory Call The dynamic RAM memory cell conSists of 1 MOS transistor and 1 capacitor, as shown in Figure 2-1. It detects the data in the cell (lor 0) by the charge stored in capacitor. Dynamic RAM offers higher density than that of static RAM because of fewer components per Chip. However, Dynamic RAM must rewrite data, called refresh, in a defined cycle because the charge stored in the capacitor leaks. 0140-31 Figure 2-1. Memory Cell of Dynamic RAM 2.2 Power On Procedure After turning on power, to set the internal memory circuitry, hold for more than 100 I-'s, then apply eight or more dummy cycles before operation. The dummy cycle may be either a Ao- A9 CAS 2.3 Address Multiplexing Dynamic RAMs are used to increase capacity because of their smaller cell area. In using dynamic RAMs in systems, however, it is desirable to increase the memory density by using smaller packages. To reduce the number of pins and the package size, address multiplexing is used. Using a l-Mbit dynamic RAM, 20-address signals are necessary to select one of 1,048,576 memory cells. Address multiplexing allows address signals to be applied to each address pin. Thus only 10-address input pins are required to select one of 1,048,576 addresses. Multiplexed address inputs are latched as follows: RAS (Row Address Strobe) selects one of word lines according to the row address signal, and one of column decoders is selected by CAS (column address strobe) following column address signal. Although two extra signals, RAS and CAS, are required, the number of address pins is reduced to half. Figure 2-2 shows the pin arrangement, address latch waveform, and the block diagram of address-multiplexed l-Mbit dynamic RAM. Systems need an address multiplexer in order to latch the multiplexed address signals into the device. Address Inputs Column Address Strobe Data In Din Dout Data Out RAS Row Address Strobe WE ReadIWrite Input Vee Power (+ 5V) Vgg Ground Ao-As Refresh Address Inputs 0140-32 (a) Pin Arrangement 0140-33 Figure 2-2. Address Multiplexing of Dynamic RAMs $ HITACHI Hitachi America, Ltd. • Hitacoli Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 35 Application 2.4 Dynamic RAM Function tRC: Random Read or Write Cycle Time tRCO: RAS to CAS Delay Time tRAC: Access Time from RAS tCAC: Access Time from CAS R: Row Address C: Column Address Dou. 0140-34 (a) Read Cycle m CAS Addre.. WE Don :J:iilmnll~ HAS CAS ~ Dou. Address WE DOl lIliIIi :Lknaol: =m~ 0140-36 (Early Write) 0140-37 (Delayed Write) (b) Write Cycle '''' Add.... D.. Dout :LJim2 tRWC: Read-Write Cycle Time !ftJJJ/Ii~ Hioh Z ( )- (c) Read·Modify·Write Cycle 0140-36 Figure 2-3. Normal Function of Dynamic RAM Read Cycle: In the read cycle, a row address is latched at the falling edge of RAS, and a column address is latched at the falling edge of CAS after the RAS falling edge. If WE is high, the data is read out from Dout with the access time of tCAC (Access time from CAS) or tRAC (Access time from RAS). The tRCD maximum (RAS to CAS delay time) is specified only to guarantee the specified minimum values of other timings such as the cycle time, RAS/CAS pulse width. Therefore, when using these timings with more than the specified minimum value, there is no need to limit the tRCD to the specified maximum value. $ 36 Write Cycle: Dynamic RAM provides two write cycle modes: early write cycle and delayed write cycle. In the early write cycle, when WE is low, data is written into Din at the falling edge of CAS. In delayed write cycle, when WE is high, data is written into Din at the falling edge of WE after CAS falling. Read-Modlfy-Wrlte Cycle: The read-modify-write cycle is initiated by taking WE high. Data is read out from Dout at the falling edge of CAS with WE high. Then, when WE goes low, data is written into the same address from Din in the same cycle. The cycle time in the read-modify-write mode (tRWC> is longer than the cycle time in read/write mode (tRC>' HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 Application 2.5 High Speed Access Mode Dynamic RAM access time is typically longer than that of static RAMs. To realize higher speed operation, they have high speed access modes. The read operation in dynamic RAM is performed as follows: When a word line is selected by row address, all data in the memory cells connected to the selected word line is transferred to sense amplifiers. One of these sense amplifiers is selected by the column address, and its contents are output. Nibble Mode: In a nibble mode dynamic RAM, data from 4 sequential addresses is stored in the 4-bit output latch circuits. Output is provided by the CAS signal, which controls the latch circuits. When 4 addresses are accessed sequentially, the row addresses on and after second bit need not be selected. Therefore, it facilitates the timing design. In nibble mode, the operation is limited to 4 addresses, however, it enables faster access (tNAcl than that in page mode. The output of data from other sense amplifiers is controlled only by the column address. Static Column Mode: In static column mode, the column address is switched without the synchronized signal by highspeed static RAM technology in the peripheral circuits. Access controlled only by column address with the row address fixed is called high speed access mode. Table 2-1 compares each mode. High Speed Page Mode: This mode is the advanced mode of statiC column mode, with CAS providing the address latch function. Page Mode: This is the most typical access mode in dynamic RAM. The column address is switched synchronized with CAS falling. • Table 2-1. Comparison of Dynamic RAM High Speed Access Modes Normal Mode R: Row Address C: Column Address 0140-38 RAS CAS Page Mode Address Dout 0140-39 Nibble Mode 0140-40 Static Column Mode 0140-41 DOO.= RAS' High-Speed Page Mode I~ A:~:'~ 0140-42 .HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 37 Application 2.6 Refresh Refresh operation is performed by accessing every word line within the specified time (refresh cycle). Table 2-2 compares the following refresh modes in dynamic RAM. RAS Only Refresh: In RAS only refresh mode, refresh can be completed by selecting only row addresses synchronized with RAS . CAS Before RAS Refresh: This mode refreshes by CAS falling edge before RAS in the period defined by the the internal refresh address generator. This mode simplifies the external address multiplexer. Hidden Refresh: In hidden refresh, CAS before is performed while output data is valid. RAS refresh • Table 2-2. Comparison of Dynamic RAM Refresh Modes A~:'~Z ---c::::::>- Read DDU' 0140-43 RAS Only Refresh 0140-44 CAS Before RAS Refresh Dout - - - - - - - 0140-45 Hidden Refresh 0140 46 ~: Don't care 0140-47 • 38 HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 Application 3. INSTRUCTIONS FOR USING MEMORY DEVICES 3.1 Prevention of Electrostatic Discharge As semiconductor memory designs are based on a very fine pattern, they can be subject to malfunction or defects caused by static electricity. Though the built-in protection circuits assure unaffected reliability in normal use, devices should be handled according to the following instructions. 1. In transporting and storing memory devices, put them in conductive magazine or put all pins of each device into a conductive mat so that they are kept at the same potential. Manufacturers should give enough consideration to packing when shipping their products. and NMOS transistors. Figure 3-2 shows the relationship between the input voltage and current in this inverter. The top and bottom transistors turn ON and make current flown when the input voltage becomes intermediate level. Therefore, it is necessary to keep the input voltage below 0.2V or above Vee - 0.2V in order to minimize power consumption. The data sheet specifies the stand-by current for both the cases of input level with minimum VIH and maximum VII_, and that with 0.2V or Vee - 0.2V, and the difference in value is remarkably great. Some memory devices are designed to cut off such current flow in standby mode by the control of input signals, but it depends on device type. This should be confirmed in data sheets for each device type. 2. When devices touch a human body in mounting or inspection, the handler must be grounded. Do not forget to insert a resistor (1 Mfi approx. is desirable) in series to protect the handles from electrical shock. .!_ 511"~5.0V 3. Keep the relative ambient humidity at about 50% in process. }1 ~ 4 3 .., 2 0123456 4. For working clothes, cotton is preferrable to synthetic fabrics. Input Voltqe 0140-72 5. Use a soldering iron operating at low voltage (12V or 24V, if possible) with its tip grounded. 6. In transporting the board with memory devices mounted on it, cover it with conductive sheets. 7. Use conductive sheets of high resistance to protect devices from electrostatic discharge. For, if dropped onto conductive materials like a metal sheet, devices may deteriorate or even breakdown owing to sudden discharge of the charge stored on the surface. 8. Never set the system to which memory devices are applied near anything that generates high voltage (e.g., CRT Anode electrode, etc.). 3.2 Using CMOS Memories As shown in Figure 3-1, the input of a CMOS memory is connected to the gate of an inverter consisting of PMOS Figure 3-2. Relationship between Input Voltage and Current in CMOS Inverter Another problem particular to CMOS devices is latCh-Up. Figure 3-3 shows the cross section of a CMOS inverter and the structure of a parasitic bipolar transistor. The equivalent circuit of the parasitic thyristor is shown in Figure 3-4. When positive DC current or pulse noise is applied (Figure 3-4 (a», TR3 is turned on owing to the bias voltage generated between base and emitter. And trigger current flows into GND through Rp, the base resistance of TR2. As a result, TR2 becomes conductive and current flows from power supply (Vee) through the base resistance of TR1 (RN), which puts TR1 into conduction, too. Then, as the base of TR2 is rebiased by collector current from TR1, the closed loop consisting of TR1 and TR2 reacts. Thus current flows constantly between power supply (Vee> and GND even without trigger current caused by outside noise. Latch-up can be caused by a negative pulse, too (Figure 3-4 (bb». Most of semiconductor memory manufacturers are trying to improve latch-up immunity of their products. Hitachi provides enough guard band by applying diffusion layer around inputs and outputs, taking care not to connect input to p+ diffusion layer. Input voltage for 64K-bit static RAM HM6264A, for example, is specified as follows: 0140-71 VIH max 6.0V (not depending on Vee) VIL min 3.0V (pulse width = 50 ns) - 0.3V (DC level) Figure 3-1. CMOS Inverter Thus almost no consideration for latch-up is required in system design . • HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 39 Application P,. <>-..,.-----7--, Inlemallnput (b) (I) 0140-73 Figure 3-3. Cross Section Structure of CMOS Inverter Pm r--V Clo.... Loop cc---"] P,. I I Rn: I I I '---;4-1.1.,: I I I 'I : I Ta, ON L ______ ..J (.) Th....... Elf... b, POllbveVoitaIIe (b) Thynstor Effect by N....... V.,.... 0140-74 Figure 3-4. Equivalent Circuit of Parasitic Thyristor 3.3 Noise Prevention Noise in semiconductor memories is roughly classified into input signal noise and power supply noise. 3.3.1 Input Signal Noise Input signal noise is caused by overshoot and undershoot. If either of them is out of recommended DC operating conditions, normal operation is hindered, and voltage over absolute maximum rating will break the device. In operating high speed systems, special care is required to prevent input signal noise. The noise can be prevented by inserting a serial resistance of less than son into each input or a terminating resistance into the input line. Actually, however, input signal noise can be simply reduced by a stable power supply line, because it is often caused by unstable reference voltage (GND level). 3.3.2 Power Supply Noise The power source noise can be classed as low-frequency noise and high-frequency noise as shown in Figure 3-5. To assure stable memory operation, the peak-to-peak power supply voltage in the presence of low-or high-frequency noise should be held below 10 percent of its standard level. Devices like dynamic RAMs, which operate from clock signals, or high speed CMOS static RAMs, through which current flows during transition of signals, consume high peak • 40 0140-75 Figure 3-5. Power Source Noise current. When a power supply does not have enough capacity for the peak current, voltage drops. And if the recovery rate of the power supply synchronizes with its time constant, it may start oscillating. To reduce the influence of the peak current, a bypass capaCitor of 0.1 - 0.01 ",F should be inserted near the device. The following points must be considered in designing pattern of the board: • For bypass capacitors, use titanium, ceramic, or tantalum capacitors which have better high-frequency characteristics. • Bypass capaCitors must be applied as near to the power supply pin of memory devices as pOSSible, and inductance in the path from Vee pin to Vss pin through the bypass capaCitor must be as little as possible. HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1619. (415) 569-6300 Application • The line connected to the power supply on the board should be as wide as possible. • It is preferable for the power supply line to be at right angles to devices selected at the same time, lest too much peak current should flow through one power supply line at a time. Preferr.. d Non-pre(err..d F"=:::::~:::::~~~ -Faults1 Bypath Lines are too Long. 2 Devices Selected at f":=:s.=~~-+ Sa~:M~7h:rn l~~:e Vee V~S Vcr Vss Vee VS~ ,---~.--~ Vee Vss "--------------.....----~ D... I/O Data I/O 0140-76 Figure 3-6. Examples of Power Supply Board Pattern 3.4 Address Input Waveform of Hi-BiCMOS Memory Data stored in memory might be destructed in case that Ad· dress Input of the HM6716, HM6719, HM6787, HM6788 and HM6789 series becomes floating and sticks at and around threshold voltage. (e.g., CPU does Address Bus to off state in Figure 1.) Consequently, the following three methods are recommended so as to preserve malfunction of memory device. .-------------------------------~ CPU Memory Address Bu. Input cs· Control I L__________________ ..J A: Insert latch as shown in Figure 3-7 lest Address Input should become floating. 0140-77 B: Put CS into High while Address Input becomes floating. (Dotted line in Figure 3·8) Figure 3·7 C: Insert Pull-up Resistor (R) to hold time constant of Rising Edge waveform of Address Input pin (t, = R x C) below 150 ns. Stable operation can be assured if you have already adopted the above three methods (A, B, C), while if you have any problem, please contact our sales offices. Address input _~4 \ '--------- r------, / I ' Write , \ ( Floating Read 0140-78 Figure 3-8 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589·8300 41 o 42 HITACHI Hitachi America, Ltd.• Hitachi Plaza .2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 Section 2 MOS Dynamic RAM $HITACHI® ~HITACHI 44 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM514256AI AL Series 262,144·Word x 4·Bit CMOS Dynamic RAM • DESCRIPTION HM514256A/ALP Series The Hitachi HM514256A1AL is a CMOS dynamic RAM organized 262,144-word x 4-bit. HM514256A/AL has realized higher density, higher performance and various functions by employing 1.3 ,...m CMOS technology and some new CMOS circuit design technologies. The HM514256A1AL offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514256A1 AL to be packaged in standard 20-pin plastic DIP, 20-pin plastic SOJ and 20-pin plastic ZIP. SDDP20NA • FEATURES (DP-20NA) • Single 5V (± 10%) • High Speed Access Time ..................... 60 ns/70 ns/80 ns/100 ns/120 ns (max) • Low Power Standby .......................... 11 mW (max), 1.7 mW (max) (L Version) Active ............. .495 mW/440 mW/363 mW/302.5 mW/258.5 mW (max) • Fast Page Mode Capability .512 Refresh Cycles ................................ (8 ms), (64 ms) (L Version) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • PIN OUT HM514256A1ALP Series HM514256A1AUP Series 3DCP20D (CP-20D) HM514256A1ALZP Series HM514256A1ALZP Series HM514256A/AUP Series rJEDEC Pin NO.1 Hitachi Pin N0 1/01 v" 1/02 1/04 WE 1/03 RAS CAS NC OE AO AS Al A7 A2 A6 A3 AS Voe A4 I I/OI I 1 1/02 2 2 WE 3 3 HAS 4 4 NC 5 5 AO 6 9 Al 7 10 11 12 VcclO 13 A2 8 A3 9 1 I "=F 26 20 V" 19 1/04 181/03 17 CAS 16 OE 25 24 23 22 P P P 18 15 14 16 13 15 12 14 b11 J7p A8 A7 AS AS CAS 2 I/04 4 I/O! 6 WE8 HC 10 AIl2 A314 AIl6 MI8 A820 A4 (ZP-20) • PIN DESCRIPTION Function Pin Name Ao-Ag Address Input Ao-Ag Refresh Address Input I/OI-I/04 Data Input/Data Output RAS Row Address Strobe CAS Column Address Strobe WE Write Enable OE Output Enable 0136-3 0136-2 (Top View) 0136-1 (Top View) 3DZP20 lOE 31/03 5 V" 71/02 9W HAO 13A2 15V" 17A5 19A7 (Top View) Vee Power Supply ( + 5V) VSS Ground @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 45 HM514256A1AL Series • ORDERING INFORMATION • Part No. Access Time Package Part No. Access Time Package HM5l4256AP-6 HM5l4256AP-7 HM5l4256AP-8 HM5l4256AP-1O HM5l4256AP-12 60ns 70ns 80ns lOOns l20ns 300-mil 20-pin Plastic DIP (DP-20NA) HM5l4256ALP-6 HM5l4256ALP-7 HM5l4256ALP-8 HM5l4256ALP-1O HM5l4256ALP-12 60ns 70ns 80ns lOOns l20ns 300-mil 20-pin Plastic DIP (DP-20NA) HM5l4256AJP-6 HM5l4256AIP-7 HM5l4256AJP-8 HM5l4256AJP-1O HM5l4256AJP-12 60ns 70ns 80ns lOOns l20ns 300-mil20-pin Plastic SOJ (CP-20D) HM5l4256AUP-6 HM5l4256AUP-7 HM5l4256AUP-8 HM5l4256AUP-1O HM5l4256AUP-12 60ns 70ns 80ns lOOns l20ns 300-mil20-pin Plastic SOl (CP-20D) HM5l4256AZP-6 HM5l4256AZP-7 HM5l4256AZP-8 HM5l4256AZP-1O HM5l4256AZP-12 60ns 70ns 80ns lOOns l20ns 400-mil 20-pm Plastic ZIP (ZP-20) HM5l4256ALZP-6 HM5l4256ALZP-7 HM5l4256ALZP-8 HM5l4256ALZP-1O HM5l4256ALZP-12 60ns 70ns 80ns lOOns 120ns 400-miI20-pin Plastic ZIP (ZP-20) BLOCK DIAGRAM 1/01 1 1/02 1/03 1/04 1 1 1 I I/O Buffer I I/O BUfferJ L.---l ,..--- ~ ~ CD 0 "- U; 0 ::! .:s Ii 256k Memory E Cell ~ Array 0 ::! !:. <[ ~ '" U; . ~ > .§ .. .. all ~ "0 0 u Ii a E c c <[ ~ '" ~ ~ ~ --1 "- '" 0 ::! Memory Cell Ii Array E <[ ~ " u 256k !:. E 00 "'''' ::! ::! z z ~~ 256k Memory ci ci E <[E Cell ~ Array <[ ~ ~ ~ c c ~ Ii E . !/l . a "0 0 u c E <5 u " !/l Word Driver Row Decoder Row Address Buffer F 0 ::! 5:c ~ .§ Word O"ver Row Decoder I I AD-A8 CD 0 ~ '" ""~ Iii'" <[ ~ ~ > U; !:. "'''' ~ I ~ ~ 0 ~ U; , ~ CD 0 (; !/l ---'\ Word Driver -,I Row Decoder ~ ~ CD U; 256k 0 ::! Memory !:. Cell Ii Array 0 ::! .:s Ii E <[ E =:c ~ <[ !/l 5:c . !/l I Word Driver Row Oecoder I I Column Address Buffer I " I 0136-4 ~HITACHI 46 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM514256A/AL Series • ABSOLUTE MAXIMUM RATINGS Value Unit Voltage on Any Pin Relative to Vss Item Symbol VT -1.0to +7.0 V Supply Voltage Relative to Vss VCC -1.0to +7.0 V Short Circuit Output Current lout 50 rnA Power Dissipation PT 1.0 W Operating Temerature Topr Oto + 70 ·C Storage Temperature Tstg - 55· to + 125 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (T A = 0 to Item Min Typ Max Unit Vss 0 0 0 V VCC 4.5 5.0 5.5 V 1 VIH 2.4 - 6.5 V 1 I10Pin VIL -1.0 - O.S V 1 Others VIL -2.0 - O.S V 1 Supply Voltage Input High Voltage Input Low Voltage Note: I J + 70·C) Symbol Note 1. All voltage reference to Vss. • DC Characteristics (TA = 0 to +70·C, Vee = 5V ±10%, Vss = OV) HM514256 Item Operating Current Standby Current Symbol ICCI AlAL-6 AlAL-7 AlAL-S AlAL-1O AlAL-12 Min Max Min Max Min Max Min Max Min Max - 90 - SO - 66 - 55 - 47 - 2 - 2 - 2 - 2 - 2 Unit Test Conditions Note rnA RAS, CAS Cycling, tRC = Min 1,2 rnA ICC2 RAS, CAS = VIH Dout = High-Z TTL Interface RAS, CAS ~ VCC - 0.2V CMOS Interface - 1 - 1 - 1 - 1 - 1 - 300 - 300 - 300 - 300 - 300 f'-A Dout = High-Z CMOS Interface L-Version tRC = Min RASOnly Refresh Current ICC3 - 90 - SO - 66 - 55 - 47 rnA Battery Backup Current (Only for L-Version) ICC4 - 300 - 300 - 300 - 300 - 300 f'-A CAS Before RASCycling Standby Current Iccs - 5 - 5 - 5 - 5 - 5 rnA RAS = VIH CAS = VIL Dout = Enable CAS Before RAS Refresh Current ICC6 - SO - 70 - 66 - 55 - 47 rnA tRC = Min Fast Page Mode Current ICC? - SO - 70 - 55 - 55 - 47 rnA tpc = Min Input Leakage Current ILl 10 f'-A OV f'-A OV :$ Vout :$ 7V Dout = Disable Output Leakage Current 2 !ru;;... = 125 f'-s ILO -10 -10 10 10 -10 -10 10 10 -10 -10 • 10 10 -10 -10 10 10 -10 -10 10 :$ Yin :$ 4 1 1,3 7V HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 47 HM514256A1AL Series • DC Characteristics (TA = 0 to + 70·C, Vee = 5V ± 10%, Vss = OV) (continued) HM514256 Item Symbol AlAL·6 AlAL·7 AlAL·8 AlAL·12 AlAL·1O Min Max Min Max Min Max Min Max Min Max Test Conditions Unit Note Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V High lout =- Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 mA Notes: I. 2. 3. 4. 5 mA Icc depends on output loading condition when the device is selected. Icc (max) is specified at the output open condition. Address can be changed less than three times while RAS = VIL' Address can be changed once or less while CAS = V/H. tRAS = tRAS (min) to I p.s. Input Voltage: I/O Pins: VIR ~ Vcc - 0.2V, VIL S 0.2V or High·Z The Other Pins: VIH ~ VCC - 0.2V, or VIL S 0.2V • Capacitance (TA = 25·C, Vee ±10%) Item Symbol Input Capacitance Input/Output Capacitance Notes: Address Cll Clock CI2 Data Input/Data Output Typ Max Unit Note 5 pF I 7 pF I 10 pF 1,2 - CliO I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = V/H to disable D out . • AC Characteristics (TA = 0 to + 70·C, Vee = ± 10%, 5V Vss = OV)14 Test Conditions Input Rise and Fall Times 5 ns Input Timing Reference Levels O.BV, 2.4V Output Load 2 TIL Gate + CL (100 pF) (Including Scope and Jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) HM514256 Item Symbol AlAL·6 AlAL·7 Min Max Min 120 - 130 - 50 Max AlAL·8 Min Max AlAL·1O Min Max AlAL·12 Min Unit Random Read or Write Cycle Time tRC RAS Precharge Time tRP 50 RAS Pulse Width tRAS 60 10000 70 10000 80 10000 100 10000 120 10000 ns CAS Pulse Width tCAS 20 10000 20 10000 25 10000 25 10000 30 10000 ns Row Address Setup Time tASR 0 Row Address Hold Time tRAH 10 Column Address Setup Time tASC 0 Column Address Hold Time tCAH 15 - RAS to CAS Delay Time tRcD 20 RAS to Column Delay Time RAS Hold Time - 160 - 70 - 190 80 - 220 90 0 - 0 12 - 15 - 15 0 - 0 0 20 - 20 - 50 22 55 25 15 35 17 40 20 - 25 70 80 - 10 - 10 - 15 - 40 20 tRAD 15 30 tRSH 20 CAS Hold Time tCSH 60 - CAS to RAS Precharge Time tCRP 10 - 0 10 0 • 48 - 0 Note Max - ns - ns ns 25 - 75 25 90 ns g 20 55 20 65 ns 9 25 - 30 120 - ns 100 10 - 10 - ns HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005· 1819· (415) 589·8300 ns ns ns ns HM514256A/AL Series Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) (continued) HM514256 Item Symbol A/AL-6 Min A/AL-8 A/AL-7 Max A/AL-to Max Min Max Min 20 - 25 - 30 0 - 0 - 0 0 - 0 - Unit 0 50 3 50 ns - 8 - 8 ms - 64 - 64 ms - 20 tDZO 0 - 0 CAS Delay Time from Dm tDZC 0 - 0 - Transition Time (Rise and Fall) tT 3 50 3 50 3 50 3 Refresh Period tREF - 8 - 8 - 8 Refresh Period (Only for L-Version) tREF - 64 - 64 - 64 Note Max ns 20 OE Delay Time from Dm Min - tODD OE to Dill Delay Time Max A/AL-12 Min ns ns 1,7 Read Cycle HM514256 Item Symbol A/AL-6 Min A/AL-7 Max Min Max A/AL-8 Min A/AL-to 120 ns 2,3 30 ns 3,4 55 ns 3,5 30 ns Max Min Max - tRAC - 60 - 70 - 80 tCAC - 20 20 - 25 Access Time from Address tAA 30 35 - 45 tOAC - 40 Access Time from OE - - - 100 Access Time from CAS 25 - 25 Read Command Setnp Time 20 Note Min Access Time from RAS 20 Unit A/AL-12 Max 25 tRCS 0 - 0 - 0 - 0 - 0 - ns Read Command Hold Time to CAS tRCR 0 - 0 - 0 - 0 - 0 - ns Read Command Hold Time to RAS tRRR to - to - to - to - to - ns Column Address to RAS Lead Time tRAL 30 - 35 - 40 - 45 - 55 - ns Output Buffer Tum-off Time tOFFl - 20 - 20 - 20 - 25 - 30 ns 6 Output Buffer Tum-off to OE tOFF2 - 20 - 20 - 20 - 25 - 30 ns 6 CAS to Din Delay Time tCDD 20 - 20 - 20 - 25 - 30 - ns Write Cycle HM514256 Item Symbol A/AL-6 A/AL-7 A/AL-8 Min Max Min Max Min 0 15 - 20 to - 15 15 - 20 25 - 25 - 30 - ns 25 - 25 - 30 - ns - 0 - 0 11 25 - ns 20 ns II - 20 tCWL 20 - 20 - - 0 - 0 15 - 15 0 15 to - 20 tDS ns 0 tRWL tDR Note 25 Write Command to CAS Lead Time Data-in Hold time Unit - - Data-in Setup Time Max - to Write Command Pulse Width A/AL-12 Min 0 twp 0 15 Max 20 Write Command to RAS Lead Time twcs tWCR A/AL-to Min - - Write Command Setup Time Write Command Hold Time Max 0 ns ns ~HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 49 HM514256A1AL Series Read-Modify-Write Cycle HM514256 Symbol Item AJAL-6 AJAL-S AJAL-7 AJAL-IO Max AJAL-12 Min Unit Note Max Min Max Min Max Min Max Min ISO 220 - 295 - ns 135 - 160 - ns 10 55 - 255 45 - 60 - 70 - ns 10 10 Read-Write Cycle Time tRWC 170 RAS to WE Delay Time tRWD S5 CAS to WE Delay Time tCWD 45 - Column Address to WE Delay Time tAWD 55 - 60 - 70 - SO - 95 - ns OE Hold Time from WE tOEH 20 - 20 - 25 - 25 - 30 - ns AJAL-12 Unit 95 110 Refresh Cycle HM514256 Item Symbol AJAL-6 AJAL-S AJAL-7 Min Max Min Max AJAL-IO Min Max Min Max Min Note Max CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 15 - 15 - 20 - 20 - 25 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - 10 - ns Fast Page Mode Cycle HM514256 Item Symbol Fast Page Mode Cycle Time tpc Fast Page Mode CAS Precharge Time tcp AJAL-6 AJAL-7 AJAL-S Max AJAL-12 AJAL-IO Min Max Min Unit Note Max Min Max Min Max Min 45 - 50 - 55 - 55 - 65 - ns 10 - 10 - 10 - 10 - 15 - ns Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 - 100000 - 1000000 - 100000 ns 12 Access Time from CAS Precharge tACP - 40 - 45 - 50 - 50 - 60 ns 13 RAS Hold Time from CAS Precharge tRHCP 40 - 45 - 50 - 50 - 60 - ns Fast Page Mode Read-Write Cycle Tim,e tpCM 95 - 100 - 110 - 115 - 135 - ns Notes: I. AC measurements assume tT = 5 ns. 2. Assumes that tRCD S tRCD (max) and tRAD S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TIL loads and 100 pF. 4. Assumes that tRCD ~ tRCD (max) and tRAD S tRAD (max). 5. Assumes that tRCD S tRCD (max) and tRAD ~ tRAD (max). 6. tOFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. Transition times are measured between VIH and VIL. S. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' ~HITACHI 50 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM514256A/AL Series 10. twcs, tRWD, tCWD and tAWD are not restrictive operating parameters. They are inclnded in the data sheet as electrical characteristics only: if twcs ~ twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; iftRWD ~ tRWD (min), tCWD ~ tCWD (min) and tAwD ~ tAWD (min), the cycle is a read-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. II. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or readmodify-write cycles. 12. tRASC is determined by RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of tAA, tCAC or tACp. 14. An initial pause of 100 p.s is required after power-up followed by eight or more initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). If the internal refresh counter is used, eight or more CAS before RAS refresh cycles are required . • TIMING WAVEFORMS • Read Cycle Address WE tCAe 101'1'1 Dout Hlgh-Z Valid Output 101'1'1 tOAC Din OE ~: Don't care 0136-5 ~HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 51 HM514256A1AL Series • Early Write Cycle t.e RAS 'ItAS tM' tT tCAS lRCD tcs. CAS Address WE t •• Om Dout ";"h-Z OE: Don't care twa ~ twa (min) ~ : Don't care 0136-6 • Delayed Write Cycle Address Dm Dout DE IZZZ1 : Doo't care 0136-7 ~HITACHI 52 Hitachi America, Ltd. • Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM514256A/AL Series • Read-Modify-Write Cycle CAS Address WE DiD D~ -+__H_~~-Z__~ ________ t ... ~ : Don't care 0136-8 • RAS Only Refresh Cycle Dout H~-Z OE, WE: Don" care ~ : Don't eire 0136-9 eHITACHI Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819. (415) 589-8300 53 HM514256A1AL Series • CAS Before RAS Refresh Cycle CAS -------,OL Address,Din, WE : Don't care DODt : Hiah-Z ~ : Don't care 0136-10 • Fast Page Mode Read Cycle Address Din Dout ~ : Don't care 0136-11 ~HITACHI 54 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM514256A/AL Series • Fast Page Mode Early Write Cycle Address Don Hlgh-Z Dout OE : Don't care tZz.iI : Don't care 0136-12 • Fast Page Delayed Write Cycle ~ '[)on'teare DE 0136-13 • HITACHI Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 55 HM514256A/AL Series • Fast Page Mode Read-Modlfy-Write Cycle CAS---i-+--..... Address Don ~ : Doa't care 0136-14 • 56 HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589·8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514256A1AL Series Supply Current (Active) vs. Supply Voltage 1.3 l' 1 ~ ] 1.2 ./ 1.1 1.0 ~ V /" ~ 07 llr---+----r----r---~ ] 1 I O.S Jl 4.50 4.75 5.00 or....."t---+=~::::::::::_i 0.9r-----l----t--+---l O.S 0.7!:oO---=20:.---+.40,----=6'::-0-----fSO 5.50 525 "I------+---t----t-------i ~ J ./' 0.9 1: / I-' t Supply Current (Active) vs. Ambient Temperature 1.3,..-----,---.---'--.....- - - - , Ambient Temperature Ta ("C) Supply Voltage Vee (V) Supply Current (Active) vs. Frequency I !] 10.0 ~ b I 5.0 1.0 0.5 V O. 10.1 t ~ ] Supply Current (Standby) vs. Supply Voltage 1.6 V v i 0.6 ...... 1.1 J ] l CMO~ interfaJ 1.0 / 0.9 O.S / / / V rn 0.5 0.74.50 5.0 10.0 1.0 4.75 5.00 5.25 Frequency f (MHz) Supply Voltage Vee (V) Supply Current (Standby) vs. Supply Voltage Supply Current (Standby) vs. Ambient Temperature 5.50 1.3 1TLin~ace l' := / • V 1.0 ~ 1.2 i 1.2 ~ 'iii ~ 1.4 O.S ] 1.3 ,/ !] / ~ i ,.-/ rn 1.2 1.1 1.0 ~ .............. 0.9 f'..... O.S ~ rn 0.4 4. 50 4.75 5.00 5.25 5.50 20 40 60 so Ambient Temperature Ta (0C) Supply Voltage Vee (V) 0136-15 @HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 57 HM514256A1AL Series - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ __ RAS Access Time vs. Supply Voltage RAS Access Time vs. Ambient Temperature ]' 1. 3 "iI 1. 2 IS r--- r--- .. .§ r <~ ~ .... -r-- 0.9 0.8 ~ 1. 1 ~ 1. .. .5 !-o ., I(J :c" - I---~ Or-- o.9 o. 8 II) < 0.7 4.50 4.75 5.00 5.25 5.50 ~ o. 7 20 40 60 80 Supply Voltage Vee (V) Ambient Temperature Ta (0C) CAS Access Time vs. Supply Voltage CAS Access Time vs. Ambient Temperature 1.3 2 1.2 1.1 ~ ........ 1.0 -- ~ 0.9 r--- 0.8 0.7 4. 50 4.75 5.00 5.25 5.50 .. gV ~ o. ~ o. 7 0 1 C 1.3 2 ~ 1.2 1. .. ~., ft < ~ ~ .............. 1. 0 ~ O. 9 -- ~ 4.75 5.00 60 80 / / 1. 1 / I--- O. 8 O. 7-4.50 40 20 Address Access Time vs. Ambient Temperature ]' 1. 1 ./ Ambient Tempetature Ta (OC) 1. 3 j ./ <~ o.8 Address Access Time vs. Supply Voltage ] V 1. 0 Supply Voltage Vee (V) ...... V" 1 5.25 5.50 j., j o. 9 , / L o. 8 o. 7 20 40 60 80 Ambient Temperature Ta (0C) Supply Voltage Vee(V) 0136-16 @HITACHI 58 Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 HM514258A Series 262,144·Word X 4·Bit CMOS Dynamic RAM • DESCRIPTION HM514258AP Series The Hitachi HM514258A is a CMOS dynamic RAM organized 262144-word x 4-bit. HM514258A has realized higher density, higher performance and various functions by employing 1.3 Mm CMOS technology and some new CMOS circuit design technologies. The HM514258A offers Static Column Mode as a high speed access mode. Multiplexed address input permits the HM514258A to be packaged in standard 20-pin plastic DIP, 20-pin plastic SOJ and 20~pin plastic ZIP. 3DDP20NA • FEATURES (DP-20NA) • Single 5V (±10%) • High Speed Access Time ..................... 60 ns/70 ns/80 ns/100 ns/120 ns (max) • Low Power Standby .................................................. 11 mW (max) Active ................. 495 mW/440 mW/413 mW/358 mW/303 mW (max) • Static Column Mode Capability • 512 Refresh Cycles .................................................. (8 ms) • 2 Variations of Refresh RAS Only Refresh CS Before RAS Refresh HM514258AJP Series 3DCP20D (CP-20D) HM514258AZP Series • ORDERING INFORMATION Part No. Access Time Package HM514258AP-6 HM514258AP-7 HM514258AP-8 HM514258AP-1O HM514258AP-12 60 ns 70 ns 80 ns 100 ns 120ns 300 mil20-pin Plastic DIP (DP-20NA) HM514258A1P-6 HM514258A1P-7 HM514258A1P-8 HM514258A1P-1O HM514258A1P-12 60 ns 70 ns 80 ns 100 ns 120 ns HM514258AZP-6 HM514258AZP-7 HM514258AZP-8 HM514258AZP-1O HM514258AZP-12 3DZP2Q (ZP-20) 300 mil20-pin Plastic SOJ (CP-20D) 60ns 70ns 80ns lOOns 120ns • PIN DESCRIPTION Pin Name 400 mil20-pin Plastic ZIP (ZP-20) • PIN OUT HM514258AP Series v. 1/01 1102 1/04 WE 1/03 HM514258AJP Series I HitachI Pm NO. JEDEC Pin No. 1/01 1 fiAs ~ 1/022 NC ill: WE3 RAS. AO A8 AI A1 A. A, . A3 AS v~ NC S .. I 3 S I '=' "25 " 1 es I OE 3 1/03 5 VM 2 1/04 .. '" v. 191/04 181/03 23 17es 22 160E 1/01 6 WE 8 7 1/02 9 iiAs Address Input Ao-Ag Refresh Address Input I/Oo-1I04 Data Input/Data Output RAS Row Address Strobe CS Chip Select WE Write Enable OE Output Enable Vce Vss Power Supply ( + 5V) Ground NC 10 11 AO At 12 13 A2 A3 14 AO. , 18 AI 1 10 11 14 A7 ", " v"" 16 13 A6 IS 12 AS 11M "8 12 10 0114-1 I HM514258AZP Series Function Ao-Ag 13 . (Top View) 15 Vt:c 15 AS A4 16 17 AS AS 18 19 A7 AS 20 0114-3 0114-2 (Top View) (Bottom View) @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300 59 HM514258A Series • BLOCK DIAGRAM 1/01 1/02 1/03 1/04 ~ I/O Buffer r- U; 0 256k ~ Memory U; E Cell Array ! . " < 0 ~ , 8: " V /' ....-V ~ 8: " >, O.S 07 4.50 5.00 5.25 Supply Voltage Vee (V) Ambient Temperature Ta (DC) Supply Current (Active) vs Frequency Supply Current (Standby) vs Supply Voltage 1. 3 1/ g 0 6 ;:: § u >, 8: " til 0 'V O. 1 01 / CM6s interC'::e ]' 5. 0 ] 1 --r-'-1I'==*==-1 0.7 ~O---::20;;-----::40;----;6!;;-0---;;SO 5.50 10 0 ] 1.° O.S t - - - t - - - t - - - t - - - - - j til 4.75 1----1---+--+---1 0.9 r - - - i - - - t - - - t - - - - ; a til 1.1 1. 2 ~ ! 1. 1 [) ~ 1. 0 ! o. 9 >, o. S 8: " 0.5 10 O. 7.~.50 5.0 100 Sf-/ / V 2 ~ 500 V :0Il 12 1 O 1. ] 1. 6 :~ ;:: § >, 6 } 4.75 500 550 Supply Current (Standby) vs Ambient Temperature O. 9 ............... J'-.... i'-- U 4 5.25 1. 3 tiL interCa~e 4 4.75 Supply Voltage Vee (V) Supply Current (Standby) vs Supply Voltage 0 L V til Frequency C(MHz) 1.6 ./ L .L 525 5.50 O. S O. 7 Supply Voltage Vee (V) 20 40 60 80 Ambient Temperature Ta (DC) 0114-15 ~HITACHI 70 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HM514258A Series RAS Access Time vs Supply Voltage ]' :.; E 3 ] 2 5 ~ 1. 1 ~ .$ :--0 .5" . !- RAS Access Time vs Ambient Temperature 9 ~ 1.2 _ 1.1 j, - - r--- ~ 1.3 1.0 - ~ 0.9 -- ~ C) ~ .0 8 I~ o.1 08 450 415 5.00 5.50 5.25 20 Supply Voltage Vee (V) CS Access Time vs Supply Voltage CS Access Time vs Ambient Temperature 3 13 1. 2 1~ 1. 0 """ "-- 9 o. 8 ----- ./ / .5" !- <~ 09 / /' V 0.8 I~ 0 14.50 415 5.00 5.25 5.50 Address Access Time vs Ambient Temperature 1.3 1. 3 12 1. 2 / / 1. 1 1.0 I--.. ---I--- 09 / 1. 0 o.9 / o. 8 0.8 0.1 4.50 80 Ambient Temperature T. (0C) Address Access Time vs Supply Voltage ............... 60 40 20 Supply Voltage Vee (V) 1 80 60 40 Ambient Temperature Ta (0C) 4.15 5.00 5.25 5.50 o.1 0 20 40 60 80 Ambient Temperature Ta ("C) Supply Voltage Vcc(V) 0114-16 @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 71 HM514266 Series 262,144-Word x 4-Bit Dynamic Random Access Memory • DESCRIPTION HM514266AP Series The Hitachi HM514266A is a CMOS dynamic RAM organized 262,144-word x 4-bit. HM514266A has realized higher denSity, higher performance and various functions by employing 1.3 p.m CMOS process technology and some new CMOS circuit design technologies. The HM514266A offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514266A to be packaged in standard 20-pin plastiC DIP, 20-pin plastic SOJ and 20-pin plastic ZIP. 3DDP20NA • FEATURES (DP-20NA) • Single 5V (± 10%) • High Speed Access Time ..................... 60 ns/70 ns/80 ns/l00 ns/120 ns (max) • Low Power Dissipation Active Mode ........... 495 mW/440 mW/363 mW/303 mW/259 mW (max) Standby Mode ............................................. 11 mW (max) • Fast Page Mode Capability • 512 Refresh Cycles .................................................. (8 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • Write per Bit Capability HM514266AJP Series 3DCP20D (CP-20D) HM514266AZP Series • ORDERING INFORMATION Part No. Access Time Package HMS14266AP-6 HMS14266AP-7 HMS14266AP-8 HMS14266AP-1O HMS14266AP-12 60ns 70ns 80ns lOOns 120ns 300 mil20-pin Plastic DIP (DP-20NA) HMS14266AJP-6 HMS14266AJP-7 HMS14266AJP-8 HMS14266AJP-1O HMS14266A]P-12 60ns 70ns 80ns lOOns 120ns 300 mil 20-pin Plastic SO] (CP-20D) HMS14266AZP-6 HMSI4266AZP-7 HMS14266AZP-8 HMS14266AZP-1O HMS14266AZP-12 60ns 70ns 80ns lOOns l20ns 400 mil20-pin Plastic ZIP (ZP-20) 3DZP20 (ZP-20) • PIN DESCRIPTION Function Pin Name Ao-As Address Input Ao-As W]1I0]Wl/I04 Refresh Address Input Write Select! Data-in/Data-out RAS Row Address Strobe CAS Column Address Strobe WB/WE Write Per Bit/Write Enable OE Output Enable Vee Power Supply ( + S.OV) Vss Ground ~HITACHI 72 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM514266 Series • PIN OUT HM514266AP Series Vss Wl/101 W2I102 WBIWE VOl V02 2 3 RAS 4 NC 5 W41104 W31103 CAS OE A8 A7 A6 RAS NC AO Al A2 A3 WE CAS A4 0118-1 15 14 13 12 11 OE 3 1103 CAS 1/04 1101 WE 18 1/03 17 16 OE AO 6 Al 7 A2 8 A3 9 Vcc 10 AS Vee HM514266AZP Series HM514266AJP Series 5 Vss 7 1102 9 RAS 11 Ao 13 A2 15 Vcc 17 As 19A7 AS A7 A6 AS A4 0118-3 0118-2 (Top View) (Top View) (Bottom View) • BLOCK DIAGRAM ~ WlIlOI W2II02 W3II03 W4II04 I I/O Buffer I I I/O Buffer L....--I ~ I 1 - II> II> ., III III III :;) :;) .~ ~ 256k ~ c 0 ::< Memory o!S o!S Ui ~ 0 iii Cell ci. ::< '" Array E !!:.. 8 Ui .. « . II> c: en 0 256k Array til () 00 256k .. .. Array «« II> ..., ..., 0 lUi Ui III .~ 0 ~ .,c: . 256k c: E Array ~ Ui 0 « til c: c: til c: en II> c: Word Driver Word Driver Word Driver RaNDeooder RaNDeoode RaNDeooder Row Address Buffer E .. « .. .. ;3 ~.. . en. en c: en en II> .. eo "8c eo ~ E ., en -1 ~ :;) iii o!S o!S ::< Memory ::<::< Memory .~ en Cii Memory ~ 0 iii 0 Cell I~~ Cen Cell ::< ::< 19i~l~ ci. ci. E c: E « 2E « en --r RaNDeoode Ui .. !!:..::< c c: ...---J.. Word Driver o!S II> :;) IColumn Address Bufferl - 0118-4 ~HITACHI Hitachi America, Ltd. • Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589·8300 73 HM514266 Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Voltage on Any Pin Relative to Vss VT -1.0to Supply Voltage Relative to Vss vcc - 1.0 to Short Circuit Output Current lout Power Dissipation PT Operating Temperature Topr Storage Temperature Tstg Unit + 7.0 + 7.0 V V 50 rnA 1.0 W + 70 55 to + 125 ·C Oto - ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70°C) Parameter Min Typ Max Unit Vss Symbol 0 0 0 V Vcc 4.5 5.0 5.5 V I VIH 2.4 6.5 V I (I/O Pin) VIL -1.0 0.8 V I (Others) VIL -2.0 - O.S V I Supply Voltage Input High Voltage Input Low Voltage Note: I I Note I. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to + 70°C, Vee = 5V ± 10%, Vss = OV) Parameter Symbol Operating Current ICCI Standby Current 514266A-6 514266A-7 514266A-S 514266A-1O 514266A-12 Min Max Min Max Min Min Min - 90 - SO Max 66 - Max 55 - - Max Unit Test Conditions 47 rnA tRC = Min 1,2 - 2 - 2 - 2 - 2 - 2 TTL Interface rnA RAS, CAS = VIH Dout = High-Z - I - I - I - I - I CMOS Interface rnA RAS, CAS 2: VCC - 0.2V, Dout = High-Z ICC2 Note RASOnly Refresh Current ICC3 - 90 - SO - 66 - 55 - 47 rnA tRC 2 Standby Current ICC5 - 5 - 5 - 5 - 5 - 5 rnA I CAS Before RAS Refresh Current ICC6 - SO - 70 - 66 - 55 - 47 rnA tRC = Min Fast Page Mode Current ICC7 - SO - 70 - 55 - 55 - 47 rnA tpc = Min Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 -10 10 /LA OV Output Leakage Current ILO -10 10 -10 10 -10 10 -10 10 -10 10 /LA Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V High lout =- Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 rnA Notes: = Min RAS = VIH, CAS = VIL Dout = Enable :s Yin :s 7V OV :s Vout :s 7V Dout = Disable 5 rnA I. Icc depends on output load condition when the device is selected, Icc max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIV 3. Address can be changed once or less while CAS = VIH' ~HITACHI 74 1,3 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM514266 Series • Capacitance (TA = 25°C, Vee = 5V ± 10%) Parameter Symbol Input Capacitance (Address) Cn Input Capacitance (Clocks) CI2 Output Capacitance (Data-in, Data-out) CliO Notes: Typ Max Unit Note - 5 pF 1 7 pF 1 10 pF 1,2 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out . • AC Characteristics (TA = Oto + 70°C, Vee = 5V ±10%, Vss = OV)1, 14 Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Symbol 514266A-6 Min 514266A-1O 514266A-12 Min Max Min 514266A-8 Max Min Max Min Max 130 - 160 - 190 - 220 - ns 90 - ns 514266A-7 Max - Unit Note Random Read or Write Cycle Time tRC 120 RAS Precharge Time tRP 50 RAS Pulse Width tRAS 60 10000 70 10000 80 10000 100 10000 120 10000 ns CAS Pulse Width tCAS 20 10000 20 10000 25 10000 25 10000 30 10000 ns Row Address Setup Time tASR 0 Row Address Hold Time tRAH 10 Column Address Setup Time tASC 0 Column Address Hold Time tCAH 15 - RAS to CAS Delay Time tRCD 20 RAS to Column Address Delay Time tRAD RAS Hold Time tRSH CAS Hold Time tCSH 60 50 70 80 0 - 0 12 - 15 0 - 0 0 15 - 20 - 40 20 50 22 15 30 15 35 20 - 20 70 0 10 20 - ns 25 - 55 25 75 25 90 17 40 ns 8 20 55 20 65 ns 9 25 80 - 100 25 30 0 - ns 0 - 10 - 10 20 25 0 - 0 15 0 ns ns ns tCRP 10 OE to Din Delay Time toDD 20 - 20 OE Delay Time from Din tDZO 0 0 CAS Delay Time from Din tDZC 0 - 0 - Transition Time (Rise and Fall) tT 3 50 3 50 3 50 3 50 3 50 ns Refresh Period tREF 8 - 8 - 8 - 8 - 8 ms CAS to RAS Precharge Time - 10 0 0 120 10 30 0 ns ns ns ns ns 7 Read Cycle Parameter Symbol 514266A-6 Min 514266A-1O 514266A-12 Max Min Max Min Max - 80 - 100 ns 25 - 25 30 ns 3,4 40 - 45 55 ns 3,5 25 - 25 - 120 - 0 - 514266A-7 Max Min Max 60 70 20 35 514266A-8 Min Access Time from RAS tRAC Access Time from CAS tCAC Access Time from Address tAA - Access Time from OE tOAC - 20 - 20 - - 0 - 0 - 0 - 0 40 - 20 - 20 20 - 20 - - 20 - 25 Read Command Setup Time tRCS 0 Read Command Hold Time to CAS tRCH 0 Read Command Hold Time to RAS tRRH 10 Column Address to RAS Lead Time tRAL Output Buffer Turn-off Time toFFI 20 Output Buffer Turn-off to OE toFF2 - CAS to Din Delay Time tCDD 20 20 30 10 35 20 20 - - 20 10 0 10 45 Unit Note 2,3 30 ns 0 - ns 0 ns 10 - 55 - ns 25 - 30 ns 6 25 - 30 ns 6 - 30 - ns ns ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 75 HM514266 Series Write Cycle Parameter Symbol 514266A-6 Min 514266A-7 Max Min Max 514266A-8 Min Max 514266A-1O 514266A-12 Min Max Min Max 0 0 - 20 - - Write Command Setup Time twcs 0 - 0 - 0 - 0 Write Command Hold Time tWCH 15 15 - 20 - 20 Write Command Pulse Width twp Write Command to RAS Lead Time tRWL Write Command to CAS Lead Time tCWL 10 - 10 - 15 - 15 20 - 20 - 25 - 25 20 - 20 - 25 - 25 Data-in Setup Time tDS 0 Data-in Hold Time tDH 15 0 15 0 20 25 20 30 30 0 25 Unit Note ns 10 ns ns ns ns ns 11 ns 11 Read-Modify-Write Cycle Parameter Read-Write Cycle Time Symbol 514266A-6 514266A-7 514266A-1O 514266A-12 Max Min Max Min Max Min Max 180 - 220 - 295 - ns - 110 135 - 160 - ns 10 45 55 60 - 70 - ns 10 70 - 255 95 80 95 - ns 10 25 - 25 - 30 - ns Min Max Min tRWC 170 RAS to WE Delay Time tRWD 85 CAS to WE Delay TIme tCWD 45 - Column Address to WE Delay Time tAWD OE Hold Time from WE tOEH 55 - 60 - 20 - 20 - 514266A-8 Unit Note Refresh Cycle Parameter Symbol 514266A-6 Min 514266A-7 Max 514266A-1O 514266A-12 Min Max Min 514266A-8 Max Min Max Min Max Unit Note CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 15 - 15 - 20 - 20 - 25 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - 10 - ns Fast Page Mode Cycle Parameter Fast Page Mode Cycle Time Symbol 514266A-6 514266A-7 514266A-8 Max 514266A-1O 514266A-12 Min Min Max Min Max Min - 50 - 55 - 55 - 65 - ns 10 - 10 - 15 - ns tpc 45 Fast Page Mode CAS Precharge Time tcp 10 Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 - 100000 Access Time from CAS Precharge tACP - 40 - 45 - 50 - 40 - 45 - 50 - 95 - 100 - 110 - RAS Hold Time from CAS Precharge tRHCP Fast Page Mode Read-Write tpCM Cycle Time 10 Max Max Unit Note Min 100000 ns 12 50 - 60 ns 13 50 - 60 - ns 115 - 135 - ns 100000 Write Per Bit(15, 16) Parameter Symbol 514266A-6 Min Max 514266A-7 514266A-8 Min Max Min Write per Bit Setup Time tWBS 0 - 0 Write per Bit Hold Time tWBH 10 - 10 - 12 Write per Bit Selection Setup time tWDS 0 - 0 - Write per Bit Selection Hold Time tWDH 10 - 10 - Max 514266A-1O 5l4266A-12 Min Min Max Max 0 - 0 - ns 15 - 15 - ns 0 - 0 - 0 - ns 12 - 15 - 15 - ns 0 ~HITACHI 76 Unit Note Hitachi America, Ltd_. Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM514266 Series Notes: I. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :S tRCD (max) and tRAD :S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD 2: tRCD (max) and tRAD :S tRAD (max). 5. Assumes that tRCD :S tRCD (max) and tRAD 2: tRAD (max). 6. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIR (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIR and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. twcs, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs 2: twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; iftRWD 2: tRWD (min), tCWD 2: tCWD (min), and tAWD 2: tAWD (min), the cycle is a read-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to CAS leading edge in early write cycles and to WB/WE leading edge in delayed write or read-modify-write cycles. 12. tRASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of tAA or tCAC or tACP' 14. An initial pause of 100 ,...S is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles are required. 15. When using the write-per-bit capability, WB/wE must be low as RAS falls. 16. The data bits to which the write operation is applied can be specified by keeping Wi/IOi high with setup and hold time referenced to the RAS negative transition. ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 77 HM514266 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read Cycle Address WB,WE W1~'01 [Dout Hi-Z toze W4/104 Din ~"""""""r""7"7~'1"""'7'~ Hi-Z ~~------~~----~------r_----~ r'-.4-I.'-"'-~"-'-"'" . fI0/~ :Don't care 0118-5 ~HITACHI 78 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 HM514266 Series • Early Write Cycle tCSH tCRP Address WB/WE W1/101 W4~04 [Din Dout OE : Don't care • 1"'7~-r~"";;~;":;' : Don't care 0116-6 @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 79 HM514266 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Delayed Write Cycle Address WB.WE W'\IO' [Din W4/104 Dout '1 Invalid output . WM :Don't care 0118-7 @HITACHI 80 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy., Brisbane, CA 94005-1819' (415) 589-8300 HM514266 Series • Read-Modify-Write Cycle Address WB,WE W1/101 W4~04 [Din Valid Input Dout tOEH OE WM : Don't care 0118-8 _HITACHI Hitachi America, Ltd,. Hitachi Plaza. 2000 Sierra Point Pkwy,. Brisbane, CA 94005-1819. (415) 589-8300 B1 HM514266 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle RAS Address Dout 1 OE, WE 2 ~ :Don't eare : Don'teare 0118-9 • CAS Before RAS Refresh Cycle tCSR tCHR Address, Din, WE : Don't care Dout: Hlgh·Z 0118-10 • 82 HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819' (415) 589·8300 - - - - - - - - - - - - - - - - - - - - - - - - - - HM514266 Series • Fast Page Mode Read Cycle ~ ~ ) ICSH IT.... IRHCP Ipc I+- Icp IRCO ICAS ~ ~ IRAti f+t" IASR 14-'" Address ~ Row lCAH ~ lRAO .. - W1/101 Din lco~ /'///// 1000.... ! ~ o/j ~ . 'C 0 u Ii 0 - '" U; 0 ::IE ~ Ii en0 Memory ~ Cell Array ::IE "E . < ~ c .l! ~ c c .l! II) Word Driver Row Deeoder Word Driver Row Decoder Word Driver Row Decoder 256k .". 8 . E c I I Column Address Buffer I I I .... E < ":;JE < ~.l! Row Address Buffer 0 AO A9 I " 0115-4 .HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy., Brisbane, CA 94005-1819' (415) 589-8300 87 HM511000A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS Parameter Symbol VoItage on Any Pin Relative to V88 Supply Voltage Relative to V88 Value Unit VT -1.0to +7.0 V V mA Vcc -1.0to +7.0 Short Circuit Output Current lout 50 Power Dissipation PT Operating Temperature Storage Temperature 1.0 W Toor Oto + 70 ·C Tstg - 55 to + 125 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70"C) Parameter Min Typ Max Unit Supply Voltage Vcc 4.5 5.0 5.5 V Input High Voltage VIH 2.4 - 6.5 V Input Low Voltage VIL -2.0 - O.S V Note: Symbol All voltages referenced to Vss. • DC ElectrIcal Characteristics (Vee Parameter Symbol = 5V = OV, TA = 0 to + 70·C) ± 10%, VSS HM511000A IAL-6 HM511000A IAL-7 Min Max Min - 90 - HM511000 IA-S Max Min Max - SO - 2 - 2 - 1 - - 300 Refresh Current ICC3 - Battery Back Up Current (Only ICC4 for L-Version) Standby Current HM511000 IA-1O HM511000 IA-12 Unit Test Conditions Min Max Min Max 70 - 60 - 50 - 2 - 2 - 2 1 - 1 - 1 - 1 - 300 - 300 - 300 - 300 CMOS Interface /LA L-Version 90 - SO - 60 - 50 - 45 rnA - 300 - 300 - 300 - 300 - 300 tRC = 125~ p.A CAS Before RAS Cycling Iccs - 5 - 5 - 5 - 5 - 5 rnA CAS Refresh Current ICC6 - SO - 70 - 60 - 50 - 40 CAS Before RAS mA Refresh tRC = Min Fast Page Mode Current ICC7 - 80 - 70 - 50 - 50 - 40 rnA CAS Cycling, 88 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 Operating Current Standby Current Icc! ICC2 Note RAS, CAS Cycling, 1,2 tRC = Min TTL Interface rnA RAS, CAS = VIH, Dout = High-Z rnA mA CMOS Interface RAS,CAS ~ VCC - 0.2V Dout = High-Z RAS Only Refresh, tRC = Min = VIH, = VIL, Dout = Enable 2 4 RAS RAS tpc • 1 = VIL, = Min HITACHI 1,3 HM511000A Series • DC Electrical Characteristics (Vee = 5V ± 10%, Vss = OV, TA = 0 to + 700C) (continued) Parameter Symbol HM511000A /AL-6 HM511000A /AL-7 Min Max Min Max Min Max Min Max Min Max HM511000 IA-8 HM511000 IA-IO HM511000 IA-12 Test Conditions Unit Input Leakage ILl -10 10 -10 10 -10 10 -10 10 -10 10 p.A Vin Output Leakage ILO -10 10 -10 10 -10 10 -10 10 -10 10 p.A VOH 2.4 Vee 0.4 2.4 Vee 0.4 2.4 Vee 0.4 2.4 0 Vee 0.4 2.4 VOL Vee 0.4 Output Levels Notes: I. 2. 3. 4. 0 0 0 0 Note = Oto +7V = Oro +7V, = Disable V lout = -5mA V lout = 4.2mA Vout Dout lee depends on output loading condition when the device is selected. lee max is specified at the output open condition. Address can be changed less than three times while RAS = VIL. Address can be changed once while CAS = VIH' tRAS = tRAS (min) to I p.s Input voltage: All pins: VIH ~ Vee - 0.2V or VIL S 0.2V. • Capacitance (Vee = 5V ±10%, TA = 25'C) Parameter Input Capacitance Output Capacitance Notes: Symbol Max Unit 5 pF I CI2 - 7 pF I Co - 7 pF 1,2 Address, Data Input Cn Clocks Data Output Typ Note I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out. • AC Characteristics (TA = 0 to +70'C, Vss = OV, Vee = 5V ±10%) Test Conditions Input rise and fall times: 5 ns Input timing reference levels: 0.8V, 2.4V (Including scope and jig) Output load: 2 TTL Gate + CL (100 pF) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Symbol HM511000A IAL-6 HM511000A IAL-7 HM511000A IAL-8 HM511000A IAL-IO HM511000A IAL-12 Min Max Min Max Min Min Min - 130 - 160 Random Read or Write Cycle Time tRe 120 - - Max - 190 - Max - 220 Unit Note Max - ns - ns RAS Precharge Time tRP 50 RAS Pulse Width tRAS 60 10000 70 10000 80 10000 100 10000 120 10000 ns CAS Pulse Width teAS 20 10000 20 10000 25 10000 25 10000 30 10000 ns 0 - ns 50 70 Row Address Setup Time tASR 0 - 0 Row Address Hold Time tRAH 10 - 10 - 12 Column Address Setup Time tAse 0 0 - 0 Column Address Hold Time teAH 15 - 15 - RAS to CAS Delay Time tRCD 20 40 20 RAS to Column Address Delay Time tRAD 15 30 15 20 70 10 20 - 50 22 35 80 90 15 - 15 0 - 0 20 - 55 25 17 40 - 25 - 80 - 100 - 10 - 0 0 ns 25 - ns 75 25 90 ns 8 20 55 20 65 ns 9 25 30 10 - ns 120 10 - ns RAS Hold Time tRSH 20 CAS Hold Time tCSH 60 CAS to RAS Precharge Time teRP 10 - Transition Time (Rise and Fall) tT Refresh Period lREF 3 50 3 50 3 50 3 50 3 50 ns - 8 - 8 - 8 - 8 - 8 ms Refresh Period (Only for L-Version) - 64 - 64 - 64 - 64 - 64 ms tREF • ns ns 7 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 89 HM511000A Series Read Cycle Parameter HM511000A /AL-6 HM511000A /AL-7 HM511000A /AL-8 HM511000A /AL-IO HM511000A /AL-12 Min Max Min Max Min Max Min Max Min Max 70 80 - 100 120 os 2,3 20 25 - 25 30 ns 3,4 40 3,5 Symbol Access Time from CAS tCAc - Access Time from Address tAA - Read Command Setup Time tRCS Read Command Hold Time to CAS Unit Note 20 30 - 35 - - 45 - 55 os 0 - 0 - 0 - 0 - 0 - ns tRCH 0 - 0 - 0 - 0 - 0 - ns Read Command Hold Time to RAS tRRH 10 - 10 - 10 - 10 - 10 - ns Column Address to RASLeadTime tRAL 30 - 35 - 40 - 45 - 55 - os - 20 - 20 - 20 - 25 - 30 os Access Time from RAS tRAC Output Buffer Turn-off Time tOFF 60 10 6 Write Cycle Parameter Symbol HM511000A /AL-6 HM511000A /AL-7 HM511000A /AL-8 HM511000A /AL-IO HM511000A /AL-12 Min Min Min Min Min Max os Max Max Max Max Unit Note Write Command Setup Time twcs 0 - 0 - 0 - 0 - 0 Write Command Hold Time twCH 15 - 15 20 - 20 - 25 Write Command Pulse Width twp 10 - 10 - 15 - 15 - 20 - Write Command to RAS Lead Time tRWL 20 - 20 - 25 - 25 - 30 - ns Write Command to CAS Lead Time tCWL 20 - 20 - 25 - 25 - 30 - ns Data-in Setup Time tos 0 - 0 - ns 11 15 20 - 20 - 0 15 - 0 tOH - 0 Data-in Hold Time 25 - ns 11 ns 10 os Read-Modify-Write Cycle Parameter Symbol Read-Write Cycle Time tRWC RAS to WE Delay Time tRWO CAS to WE Delay Time tcwo Column Address to WE Delay Time tAWD HM511000A /AL-12 HM511000A /AL-6 HM511000A /AL-7 HM511000A /AL-8 HM511000A /AL-IO Min Min Min Max Min Max Min Max 190 - 220 - os 120 10 - 25 30 - os 25 - 255 80 ns 10 40 - 45 - 55 - ns 10 Max Max 155 20 - 20 - 30 - 35 - 145 60 70 100 Unit Note Refresh Cycle Parameter Symbol HM511000A /AL-6 Min Max HM511000A /AL-7 Min Max HM511000A /AL-8 HM511000A /AL-IO HM511000A /AL-12 Min Min Min Max Max Unit Note Max CAS Setup Time (CAS Before RAS Refresh) tCSR 10 - 10 - 10 - 10 - 10 - os CAS Hold Time (CAS Before RAS Refresh) tCHR 15 - 15 - 20 - 20 - 25 - os RAS Precharge to CAS Hold Time 10 - 10 - 10 - 0 - 0 - os tRPC .HITACHI 90 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HM511000A Series Fast Page Mode Cycle Parameter Symbol HM511000A /AL-6 HM511000A /AL-7 HM511000A /AL-8 HM511000A /AL-IO HM511000A /AL-12 Min Max Min Min Min Min - 50 Max - Max - - 45 tcp 10 Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 - 100000 - 100000 - 100000 ns 13 Access Time from CAS Precharge tACP - 40 - 45 - 50 - 50 - 60 us 14 RAS Hold Time from CAS Precharge tRHCP 40 - 45 - 50 - 50 - 60 - ns 10 65 - Fast Page Mode Cycle Time tpc 10 55 Unit Note Max CAS Precharge Time 10 55 Max 15 ns ns Fast Page Mode Read-Modify-Wrlte Cycle Parameter Symbol Fast Page Mode ReadModify-Write Cycle Time tpCM Notes: HM511000A /AL-6 HM511000A /AL-7 HM511000A /AL-8 HM511000A /AL-IO HM511000A /AL-12 Min Max Min Min Min Max Min 70 - 75 85 - 100 Max - 85 Max - Unit Note Max - ns I. AC measurements assume tT = 5 ns. 2. Assumes that tRCO :S tRCO (max) and tRAo :S tRAD (max). If tRCO or tRAO is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCO ~ tRco (max), tRAO :S tRAO (max). 5. Assumes that tRco :S tRCD (max), and tRAO ~ tRAD (max). 6. tOFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. Transition times are measured between VIH and VIL. 8. Operation with the tRCO (max) limit insures that tRAC (max) can be met, tRCO (max) is specified as a reference point only, if tRCO is greater than the specified tRCO (max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAO (max) limit insures that tRAC (max) can be met, tRAO (max) is specified as a reference point only, if tRAo is greater than the specified tRAO (max) limit, then access time is controlled exclusively by tAA. 10. twC8, tRWO, tcwo and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs ~ twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ~ tRWD (min), tcWD ~ tCWD (min) and tAWO ~ tAWO (min), the cycle is a read/write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. II. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or readmodify-write cycles. 12. An initial pause of 100 I£s is required after power-up followed by eight or more initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). If internal refresh counter is used, eight or more CAS before RAS refresh cycles are required. 13. tRASC is determined by RAS pulse width in fast page mode cycle. 14. Access time is determined by the longer of tAA, tCAC or tACP . • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 91 HM511000A Series • TIMING WAVEFORMS • Read Cycle - I"" I- r.., / I. II- I .... "-- ICIII' I"" \ '~ - / '~ :.!.5!!.. !!!.orr- I .... I .... 7lJ ---~ @ Row rllllill VJ /////11111/ Column ~r-' ~r-- ...!~ '////1 ;//// -r!!!!- V//////It - ,",< I .. I'... · Valid DOlI' Output I.." ~:DOII""", 0115-5 • Early Write Cycle DHt ____________________ ______________________ H~~~-Z Notes> .1.!:'Z2:Don·t ..... • 2.1_~I_(.ia> 0115-6 • 92 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM511000A Series • Delayed Write Cycle I s. I ... Ilten CAS I,.WL ---++----.~I Ie" ter" ~----~~--------I/ IASIt tUH IASC Address ~ : Don't care. 0115-7 • Read-Modify-Write Cycle ~: D...·lcore 0115-8 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 93 HM511000A Series • RAS Only Refresh Cycle I O~, ______________ • ~mp~·~-z~ ____________________________ ~ : Dontt care 0115-9 • CAS Before RAS Refresh Cycle tCHR CAS Address ljj)!Ji1I/1111///////Ji!II(/!/J//fl/flffll Dout ______________________ ___________________________ ~H~i~~-_Z 17lZI : Don't care 0115-10 • Fast Page Mode Read Cycle Addreu WE Oout 122l: 0 ..·' .... 0115-11 $ 94 HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM511000A Series • Fast Page Mode Write Cycle Addreo. Din lli&b-Z" DOIII N.... ) *l.@:D••'leare *2. ' ..csii:twcs(mlnl 0115-12 • Fast Page Mode Read Modify Write Cycle \~~~----------~----------------~~~~lu~~I'~ tllCD 'PCIt ICIII' ~ \l'-------f I"". I .... I ..e I"". Address Din I Doul I I." IZZI: 0 •• 1 ..... 0115-13 • HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 95 HM511000A Series Supply Current (Active) vs Supply Voltage Supply Current (Active) vs Ambient Temperature 1.3 1.3.----..---.,.---,----, ~ 1.2 1.21----f----+---t----i § 1.1 ~ 1.0 J 0.9 -;; /'r' z I L. V L 1.11----f----+---t----i 1.0r=--+--1-==*=~ V 0.91----+---+--+--.., O.B 1----0.7 4.50 O.BI----f----+---t----i 4.75 5.00 5.25 0.7 =-0---;t20-:----:4~0---6:::0:----:BO 5.50 Ambient Temperature Ta (·C) Supply Voltage Vee (V) Supply Current (Active) vs Frequency 1.3 10.0 CMOS inlerface 5.0 ~ 1 3 1.0 / .:; J 0.5 j - 4.75 5.25 ] o. 6 0. 44.50 V Supply Current (Standby) vs Ambient Temperature >- l ./ 1. 3 inte~face 1. 4 1 3 / Supply Voltage Vee (V) Frequency f (MHz) 1. 6 I 1.2 5.00 5.25 5.50 O. 7 o 20 40 60 BO Ambient Temperature Ta fe) Supply Voltage Vee (V) 0115-14 .HITACHI 96 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589·8300 HM511000A Series RAS Access Time vs Supply Voltage RAS Access Time vs Ambient Temperature 1.3 1. 3 ] 1.2 1. 2 1 z 1.1 -~ 1.0 j 0.9 I~ 0.8 ---- ~ 1. 1 - 1.0 r-- 0.9 0.8 0.7 4. 50 4.75 5.00 5.25 5.50 CAS Access Time vs Supply Voltage 1 z 1.3 1.2 1.2 ~ ......... ~ l; 1.0 ~ ~ 0.9 jj 0.8 ] 0.7 4.50 "---- 4.75 ------ 5.00 5.25 1.0 1.2 1 3 1.1 -§ ... ~ '" j /"'" V 0.9 / V 0.8 5.50 60 40 20 Supply Voltage Vee (V) AmbIent Temperature To (Oe) Address Access Time vs Supply Voltage Address Access Time vs Ambient Temperature 80 1.3 1.3 ] ./ 1. 1 ;:: 80 CS Access Time vs Ambient Temperature 1.3 1.1 60 40 20 Ambient Temperature Ta (Oe) Supply Voltage Vee (V) ] --- -- ~ ............... 1.0 I--. 0.9 0.8 07 4. 50 4.75 5.00 ----5.25 ] 1.2 1 1. 1 z 5.50 / / 1.0 0.9 /' V / 0.8 0.7 o 20 40 60 80 Ambient Temperature Ta (Oe) Supply Voltage Vee (V) 0115-15 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 97 HM511001A Series - - - - - - - - - - 1,048,576·Word x 1·Bit CMOS Dynamic RAM • DESCRIPTION HM511001AP Series The Hitachi HM511001A series is a CMOS dynamic RAM organized 1,048,576word x l-bi!. HM511001A has realized higher density, higher performance and various functions by employing 1.3 p,m CMOS process technology and some new CMOS circuit design technologies. The HM511 001 A offers Nibble Mode as a high speed access mode. Multiplexed address input permits the HM511 001 A to be packaged in standard, 18-pin plastic DIP, 20-pin plastic ZIP and 20-pin plastic SOJ. 3DDP16C (DP-18C) • FEATURES HM51100 lAJP Series • High Speed Access Time ..................... 60 ns/70 ns/80 ns/l00 ns/120 ns (max) • Low Power Active ....................... 495 mW/440 mW/385 mW/330 mW/275 mW Standby ........................................................ 11 mW • Single 5V Supply (±10%) • Nibble Mode Capability • 512 Refresh Cycles .................................................. (8 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh 3DCP20D (CP-20D) HM511001AZP Series • PIN OUT HM511001AP Series HM511001AJP Series Dm TF*' Don V" WE Dou( 3DZP20 RAS CAS TF· ' NC ~C A9 • PIN DESCRIPTION Al A3 Vee A9 Nibble Address Input A2 A6 Din Data Input A3 AS A4 DOUI RAS Data Output Vee HM511001AZP Series NC 8 Refresh Address Input A7 (Top View) WE 6 Ao-As A8 (Top View) 4 Address Input Al 0116-2 V" Ao-A9 AO 0116-1 CAS 2 Function Pin Name AO A2 (ZP-20) I A9 Row Address Strobe CAS Row Address Input WE TF*l Read/Write Input Test Function Vee Power ( + SV) Vss Ground Note: *1. TF pin can be connected with any line or unconnected provided the voltage level of TF pin must be kept lower than 3 Dout 5 Om 7 RAS Vee 9 TF-I + O.SV. NC 10 Al 12 A3 14 A4 16 A6 18 A8 20 11 AO 13 A2 15 Vee 17 A5 19 A7 0116-3 (Bottom View) ~HITACHI 98 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300 HM511001A Series • ORDERING INFORMATION Part No. Access Time Package Part No. Access Time Package HM511001AP-6 HM51IOOIAP-7 HM5I1ooIAP-8 HM51IOOIAP-1O HM5I1ooIAP-12 60ns 70ns 80ns lOOns 120 ns 300 mil 18-pin Plastic DIP (DP-18C) HM51IOOIAZP-6 HM511001AZP-7 HM51IooIAZP-8 HM511ooIAZP-10 HM51IOOIAZP-12 60ns 70ns 80ns lOOns 120ns 400 mil 20-pin Plastic DIP (ZP-20) HM5I1ooIAJP-6 HM5I1ooIAJP-7 HM5I1ooIAJP-8 HM5I1ooIAJP-1O HM511oo1AJP-12 60 ns 70 ns 80 ns lOOns 120ns 300 mil 20-pin Plastic SOJ (CP-20D) • BLOCK DIAGRAM Vi£" ~ ~ ., U; 0 ~ ~ Ii ~ ~ Z56k Memory Cell .. . 1 ~ Array ~ E U; 0 ~ 0 c ~ tilcn 00 Z56k ~ Word Driver Row Decoder ~ ~ ~~ Memory .. ~ Cell ~ E E '" '" H Array E Z56k Memory Cell Array If Word Driver 11 Z56k 0 Memory ~ ~ Cell 0 ~ ~ E l;; ~ U; 0 :> . '" 0 E ~ 1 ~ ~ U; ~ ~ E '" Array j E ~ ,ji Word Driver Row Decoder I Column Address Buffer I I AD I .. . Word Driver Row Decoder Row Decoder Row Address Buffer GO <:.- ~ <:. ,:; U; '" ,ji ,ji r>' ~ , GO § '~" 8 '~" ,ji r-" ., ~ GO ~ <:. - ,:; <:.U; 0 :> Dou! - r-- GO D,n I/O Buffer A9 I 1 0116-4 • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Voltage on Any Pin Relative to VSS VT -1.0to Supply Voltage Relative to Vss Vee -1.0to Short Circuit Output Current lout Power Dissipation PT Operating Temperature Topr Storage Temperature T stg + 7.0 + 7.0 50 1.0 - a to + 70 55 to + 125 Unit V V rnA W ·C ·C @HITACHI Hitachi America, Ltd.' Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 99 HM511001A Series • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70"C) Parameter Supply Input High Voltage Input Low Voltage Symbol Min 4.5 2.4 -2.0 Vcc VIR VIL Typ 5.0 Max 5.5 6.5 0.8 - - Unit V V V I. All voltages referenced to Vss. Note: • DC Characteristics (Vee = 5V ±10%, VSS = OV, TA = 0 to +70"C) HM51100IA Parameter Symbol -6 Min Operating Current - ICCI Standby Current -7 -10 -8 -12 Min Max Min Max Min Max Min Max 90 - 80 - 70 - 60 - 50 2 - - 2 2 - 2 - Test Condition Unit Max RAS, CAS Cycling, tRC = Min mA RASCAS = Dout = High-Z RAS,CAS ~ VCC - 0.2V Dout = High-Z mA ICC2 I - I - I - I - I 1,2 VIR TTL 2 - Note Interface CMOS Interface Refresh Current ICC3 - 90 - 80 - 70 - 60 - 50 mA RAS Only Refresh, tRC = Min 2 Standby Current Iccs - 5 - 5 - 5 - 5 - 5 mA RAS = VIR, CAS = VIV Dout = Enable I Refresh Current ICC6 - 80 - 70 - 60 - 50 - 40 mA CAS Before RAS Refresh, tRC = Min Nibble Mode Current Iccs - 70 - 70 - 50 - 50 - 40 mA RAS = VIL, CAS Cycling, tNc = Min Input Leakage ILl -10 10 -10 10 -10 10 -10 10 -10 10 ,.A Output Leakage ILO -10 10 -10 10 -10 10 -10 10 -10 10 p.A Vin = Oto +7V Dout = Disabled Output Levels VOR 2.4 Vcc 2.4 Vcc V lout = -5mA 0 VCC 0.4 2.4 0.4 VCC 0.4 2.4 0 VCC 0.4 2.4 VOL 0 0.4 V lout = 4.2mA Notes: 0 0 1. Icc depends on output loading condition when the device is selected. ICC max 2. Address can be changed less than three times while RAS = VIL' 3. Address can be changed once or less while CAS = VIR. IS 1,3 VIN = Oto +7V specified at the output open condition. • Capacitance (Vee = 5V ±10%, TA = 25'C) Parameter Input Capacitance Symbol Address, Data Input Clocks Output Capacitance Notes: Data Output CII CI2 Co Typ - Max Unit Note 5 pF I 7 pF I 7 pF 1,2 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIR to disable D out' .HITACHI 100 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM511001A Series = • AC Characteristics (TA 0 to +70"C, Vee = = 5V ±10%, Vss Test Conditions Input Rise and Fall Times ......................... 5 ns Input Timing Reference Levels ............... o.av, 2.4V OV)l, 10 Output Load .........•...... 2 TTL Gate + CL (100 pF) (Including Scope and Jig) Read, Write, Read-Modify-Wrlte and Refresh Cycles (Common Parameter) HM51100IA Parameter Symbol -6 -7 Min Random Read or Write Cycle Time tRC RAS Precharge Time tRP RAS Pulse Width tRAS CAS Pulse Width Row Address Setup Time Max Min - 130 50 - 60 10000 teAS 20 tASR Row Address Hold Time -8 -10 Min Max Min Max - Unit Min Max 220 - ns - ns - 160 50 - 70 - 80 70 10000 80 10000 100 10000 120 10000 ns 10000 20 10000 25 10000 25 10000 30 10000 ns 0 - 0 - 0 ns tRAM 10 - 10 - Column Address Setup Time tASC 0 - 0 Column Address Hold Time teAH 15 - RAS to CAS Delay Time tRCD 20 RAS to Column Address Delay Time tRAD 120 - -12 Max 190 - 90 Note 0 - 0 12 - 15 15 - 0 - 0 - 0 - 15 - 20 - 20 - 25 - ns 40 20 50 22 55 25 75 25 90 ns 7 15 30 15 35 17 40 20 55 20 65 ns II 20 ns ns RAS Hold Time tRSH 20 25 - ns 70 80 - 100 - 30 60 - - tCSH - 25 CAS Hold Time 120 - ns CAS to RAS Precharge Time tcRP 10 - 10 - 10 - 10 - 10 - ns Transition Time (Rise and Fall) tT 3 50 3 50 3 50 3 50 3 50 ns Refresh Period tREF - 8 8 - 8 8 - 8 ms - - 6 Read Cycle HM51100IA -6 Symbol Parameter Min -7 Max Min -8 -10 -12 Max Min Max Min Max Min Max Unit Note Access Time fromRAS tRAC - 60 - 70 - 80 - 100 - 120 ns 2,3 Access Time from CAS tCAC - 20 - 20 - 25 - 25 - 30 ns 3,4 Access Time from Address tAA - 30 - 35 - 40 - 45 - 55 ns 3,4 Read Command Setup Time tRcS 0 - 0 - 0 - 0 - 0 - ns Read Command Hold Time Referenced to CAS tRCH 0 - 0 - 0 - 0 - 0 - ns Read Command Hold Time Referenced to RAS tRRH 10 - 10 - 10 - 10 - 10 - ns Column Address toRAS Lead Time tRAL 30 - 35 - 40 - 45 - 55 - ns Output Buffer Turn-off Delay laFF - 20 - 20 - 20 - 25 - 30 ns 5 eHITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 101 HM511001A Series Write Cycle HM51l00IA Parameter Symbol -6 -7 -8 -12 -10 Min Max Min Max Min Max Min Max Min Max Unit Note 8 Write Command Setup Time twcs 0 - 0 - 0 - 0 - 0 - ns Write Command Hold Time tWCH 15 - 15 - 20 - 20 - 25 - ns Write Command Pulse Width twp 10 - 10 - 15 - 15 - 20 - ns Write Command to RAS Lead Time tRwL 20 - 20 - 25 - 25 - 30 - ns Write Command to CAS Lead Time tCWL 20 - 20 - 25 - 25 - 30 - ns tos 0 - 0 - ns 9 20 - 20 - 0 tOH - 0 15 - 0 25 - ns 9 Unit Note Max Min Max Data-in Setup Time Data-in Hold Time 15 Read-Modify-Write Cycle HM51l00IA Parameter Symbol -6 -7 -8 -10 -12 Min Max Min Max Min Max Min 155 - 190 - 210 - ns - 80 90 110 8 - 25 25 - 30 - ns 20 - - 245 70 ns 8 35 - 40 - 45 - 55 - ns 8 Unit Note Read-Write Cycle Time tRWC 145 RAS to WE Delay Time tRwO 60 CAS to WE Delay Time tcwo 20 - Column Address to WE Delay Time tAWD 30 - Refresh Cycle HM51100IA Parameter Symbol -6 -7 -8 -10 -12 Min Max Min Max Min Max Min Max Min Max CAS Setup Time (CAS Before RAS Refresh) tcsR 10 - 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh) tcHR 15 - 15 - 20 - 20 - 25 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - 10 - ns Max Min Nibble Mode Cycle HM51l00IA Parameter Symbol -6 Min -7 Max Min -8 Max Min -10 Max Min -12 Unit Max Nibble Mode Access Time tNAC - 20 - 20 - 25 - 25 - 30 ns Nibble Mode Cycle Time tNC 40 - 40 - 45 - 45 - 50 - ns Nibble Mode CAS Precharge Time tNCP 10 - 10 - 10 - 10 - 10 - ns Pulse Width tNCA 20 - 20 - 25 - 25 - 30 - ns Nibble Mode RAS Hold Time tNRSH 20 - 20 - 25 - 25 - 30 - ns Nibble Mode CAS • 102 HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 Note HM511001A Series Nibble Mode Read-Modify-Wrile Cycle HM51loo1A Parameter Symbol -6 -7 Min Max Min -8 Max -12 -10 Unit Min Max Min Max Min Max Nibble Mode Read-ModifyWrite Cycle Time tNRWC 65 - 65 - 65 - 65 - 75 - ns Nibble Mode Write Command CAS Lead Time tNcwL 20 - 20 - 20 - 20 - 25 - ns Nibble Mode CAS to WE Delay Time tNCWD 20 - 20 - 20 - 20 - 25 - ns Notes: Note 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :S tRCD (max) and tRAD :S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD AO-A8(AXO-AX8) 0116-9 • CAS Before RAS Refresh Cycle CAS Address --------..1 //I///////////IIIIIIIT////IJI/ Dout ____________________________________________________________ __ Hlgh-Z ~ . Don'l care 0116-10 • Nibble Mode Read Cycle tzZZl : Don't care 0116-11 @HITACHI 106 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM511001A Series • Nibble Mode Write Cycle RAS CAS Address WE D," Dout Notes: 1. ~ . Don't care 2 tlt'cs~twcs(mln) 0116-12 • Nibble Mode Read-Modify-Write Cycle Y," Y," ___++-_"" Y," Address Din Dou! tZ2l : Don't care 0116-13 ~HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300 107 HM511001A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Supply Current (Active) vs. Supply Voltage 'i-; 1.3 1.3.----.,---...,..--...,..----, 1.2 1.21----+----+----+---04 ~ 1.1 ~ 1.0 ~ ~ d ... 1V> Supply Current (Active) vs. Ambient Temperature 0.9 V V L ./ 1.11----+----+----+---04 1.0F""--t--+==i===--i ./ V 0.91----+----+----+---04 o.sr----t---t---r----j O.s 0.7 4.50 4.75 5.00 Supply Voltage Vee 5.25 0.7!:-0----::20=-----:4~0---::6~0--"""t.SO 5.50 Ambient Temperature Ta (V) Supply Current (Active) vs. Frequency Supply Current (Standby) vs. Supply Voltage 10.0 1.3 CMOS inlerface 5.0 1.0 0.5 / / 1.0 0.8 1.4 1 1.2 1.0 O.s 1 0.6 5.50 (V) 1.3 TTL inteJace ] 5.25 5.00 Supply Current (Standby) vs. Ambient Temperature 1.6 ~ ~ 4.75 V V Supply Voltage Vee Supply Current (Standby) vs. Supply Voltage 0 C V / 0.74.50 5.0 10.0 1.0 Frequency f (MHz) , / 1.1 / 0.5 I 1.2 0.9 o. 10.1 (Oe) ~ 0.4 4.50 V /' V / 1.2 1", 1. 1.0 ............ 0.9 ~ 0.8 4.75 5.00 Supply Voltage Vee 5.25 5.50 20 40 ~ 60 so Ambient Temperature Ta (·C) (V) 0116-14 • 108 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM511001A Series RAS Access Time Supply Voltage VS. 1.3 1.3 ~ 1 .:: . 1.2 .!:! Oi E 0 ~ ~ 1.1 1.0 ~ ~ r-- 0.9 u u -- --- § ~ r-- 1-'- « I~ ~ .5" '"" J I~ 0.8 0.74.50 4.75 5.00 5.25 1.2 1.1 1.0 5.50 20 VS. 1.2 ~ 1.0 ~ i:l 0.9 I~ 0.8 « 80 CAS Access Time Ambient Temperature 1.3 ~ ~ ~ 60 40 Ambient Temperature Ta (·e) 1.3 1.1 ~ 0.8 CAS Access Time Supply Voltage Ii ~ 0.9 VS. ~ - ~ Supply Voltage Vee (V) 1 g RAS Access Time Ambient Temperature VS. 0.74•50 1 -; 1.2 ~ 1.1 § ......... ~ 4.75 u -.......... 5.00 E r--- 5.25 ~ 1.0 j 0.9 I~ 0.8 5.50 V ..".. ~ V 20 V 40 60 80 Ambient Temperature Ta ("C) Supply Voltage Vee (V) 0116-15 • HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589·8300 109 HM511002A Series 1,048,576-word x l-bit CMOS Dynamic RAM • DESCRIPTION HM511002AP Series The Hitachi HM511002A Series is a CMOS dynamic RAM organized 1,048,576word x 1-bit. HM511 002A has realized higher density, higher performance and various functions by employing 1.3 J.tm CMOS process technology and some new CMOS circuit design technologies. The HM511 002A offers Static Column Mode as a high speed access mode. Multiplexed address input permits the HM511002A to be packaged in standard 18-pin plastic DIP, 20-pin plastic SOJ and 20-pin plastic ZIP. 3DDP18C (DP-18C) • FEATURES HM511002AJP Series • High Speed Access Time ..................... 60 ns170 ns/80 ns/100 ns/120 ns (max) • Low Power Standby ........................................................ 11 mW Active ....................... 495 mW/440 mW/385 mW/330 mW/275 mW • Single 5V Supply (±10%) • Static Column Mode Capability • 512 Refresh Cycles .................................................. (8 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh 3DCP20D (CP-20D) HM511002AZP Series • PIN OUT HM511002AP Series HM511002AJP Sereis Dm v" WE DoUI RAS Cs" TF·\ NC NC A9 3DZP20 (ZP-20) • PIN DESCRIPTION Pin Name Ao-A9 Ao-As Refresh Address Input AO A8 AI A7 Din Data Input A2 A6 Data Output A3 AS Dou! RAS v" A. CS Chip Select 0117-1 HM51l002AZP Series 2 V... 4 WE 6 NC 8 I A9 WE Write Enable Power Supply ( + 5V) VSS TF'1 Test Function Note: 3 Dout S Dm 7 RAS 9 TF- 1 Row Address Strobe Vee 0117-2 (Top View) (Top View) cs Function Address Input Ground '1. TF pin can be connected with any line or unconnected provided the voltage level of TF pin must be kept lower than Vee + 0.5V. NC 10 Al 12 A3 14 A4 16 A6 18 AS 20 11 AO 13 A2 15 Vee 17 AS 19 A7 0117-3 (Bottom View) ~HITACHI 110 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HM511002A Series • ORDERING INFORMATION Part No. Access Time Package Part No. Access Time Package HM511002AP-6 HM511002AP-7 HM511oo2AP-8 HM51Ioo2AP-1O HM511OO2AP-12 60ns 70ns 80ns lOOns 120 ns 300 mill8-pin Plastic DIP (DP-18C) HM511oo2AZP-6 HM511oo2AZP-7 HM511002AZP-8 HM511oo2AZP-1O HM511oo2AZP-12 60ns 70ns 80ns lOOns 120ns 400 mil 20-pin Plastic ZIP (ZP-20) HM511oo2AJP-6 HM511oo2AJP-7 HM511002AJP-8 HM511002AJP-1O HM511002AJP-12 60 ns 70ns 80ns lOOns l20ns 300 mil 20-pin Plastic SOJ (CP-20D) • BLOCK DIAGRAM rr lr. ~ III 0 "- - U; 0 ::; 256k ~ Memory z I~E < .." Cell 011 U; 0 ::; ~ Array ci E < I: ell .,... .~ C5 . ~ ~ III 0 0 "- - oil 011 ~ U; ::; ~ Cell c E ci Array c ::J 0 E E E < I: III III r-'\ Word Driver -v Row Decoder 00 ::; ::; ~~ ci ci < < .." ." I: ".. 8 ". I: - "- (i)(i) 256k Memory .,8 ", " ------1 . III 256k Memory Cell Array I: Row Address Buffer l' C5 oil - "011 256k ! ., c ::; ~ Cell E c E ci Array ci 0 0 ::J 0 E Memory E I: III III , < ." I: < I: U; 0 ::; ~ ci ell 8 ". " " I AO ...... A9 ~ 0 U; ", Word Driver Row Decoder I I .~ .. III ~ ." " I U; < ell ell Word Driver Row Decoder 011 .,... Din Dout Word Driver Row Decoder Column Address Buffer I I 0117-4 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 111 HM511002A Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Voltage on Any Pin Relative to Vss VT -1.0to +7.0 Unit V Supply Voltage Relative to Vss Vee -1.0to +7.0 V Short Circuit Output Current lout 50 rnA Power Dissipation PT 1.0 W Operating Temperature Topr Oto + 70 °C Storage Temperature T stg - 55 to + 125 °C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70·C) Symbol Min Typ Max Unit Supply Voltage Parameter Vee 4.5 5.0 5.5 V Input High Voltage VIH 2.4 - 6.5 V Input Low Voltage VIL -2.0 - 0.8 V Note I. All voltages referenced to Vss. Note: • DC Electrical Characteristics (Vee = 5V ±10%, VSS = OV, TA = 0 to +70·C) Parameter Operating Current Standby Current Symbol Ieel HM5IIOO2A -6 HM511002A -7 HM5IIOO2A -8 HM511002A Min Min Min Min Max Max Max HM511002A -12 -10 Max Min Unit Test Conditions Note Max - 90 - 80 - 70 - 60 - 50 - 2 - 2 - 2 - 2 - 2 - I - I - I - I - I rnA rnA IeC2 RAS, CS Cycling tRe = Min 1,2 TTL Interface RAS,CS = VIH D out = High-Z CMOS Interface RAS, CS ~ Vee - 0.2V D out = High-Z Refresh Current Iec3 - 90 - 80 - 60 - 50 - 45 rnA RAS Only Refresh tRC = Min 2 Standby Current ICCS - 5 - 5 - 5 - 5 - 5 rnA RAS = VIH, CS = VIL, Dout = Enable I Refresh Current ICC6 - 80 - 70 - 60 - 50 - 40 rnA CS Before RAS Refresh, tRC = Min Static Column Mode Current ICC9 - 80 - 70 - 60 - 50 - 40 rnA tsc = Min Input Leakage ILl -10 10 -10 10 -10 10 -10 10 -10 10 p.A VIN=Oto+7V Output Leakage ILO -10 10 -10 10 -10 10 -10 10 -10 10 p.A Vout = Oto +7V, D out = Disable Output Levels VOH 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V lout = -5mA VOL 0 0.4 0 0.4 0 0.4 0 0.4 0 0.4 V lout = 4.2 rnA Notes: 3 I. Ice depends on output loading condition when the device is selected. Iec max is specified at the output open condition. 2. Address can be changed less than three times while RAS = V IL' 3. Address can be changed once or less while CS = VIH. • Capacitance (Vee = 5V ±100/0 TA = 25·C) Parameter Input Capacitance Output Capacitance Notes: Symbol Typ Max Unit Note Address, Data Input Cn 5 pF I Clocks CI2 7 pF I Data Output Co - 7 pF 1,2 I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CS = VIH to disable D out. ~HITACHI 112 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HM511002A Series • AC Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss = 0V)1, 17 Test Conditions Input Rise and Fall Times 5 ns Input Timing Reference Levels O.BV, 2.4V Output Load 2 TTL Gates + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycle (Common Parameters) Parameter Symbol HM51l002A-6 HM511002A-7 HM511002A-8 Min Max Min Min Max Min Max HM511002A-1O Max HM511002A-12 Min Max Unit Random Read or Write Cycle Time tRC 120 - 130 - 160 - 190 - 220 - ns RAS Precharge Time tRP 50 - 50 - 70 - 80 - 90 - ns Note RAS Pulse Width tRAS 60 10000 70 10000 80 10000 100 10000 120 10000 ns CS Pulse Width tsp 20 10000 20 10000 25 10000 30 10000 30 10000 ns Row Address Setup Time tASR 0 - 0 - 0 - 0 - 0 - ns Row Address Hold Time tRAH 10 - 10 - 12 - 15 - 15 - ns Column Address Setup Time tASW 0 - 0 - 0 - 0 - 0 - os Column Address Hold Tune tAHW 15 - 15 - 20 - 25 - 25 - os RAS to CS Delay Time tRCD 20 40 20 50 22 55 25 70 25 90 ns 8 RAS to Column Address Delay Time tRAD 15 30 15 35 17 40 20 50 20 65 ns 9 20 RAS Hold Time tRSL 20 30 80 100 - 120 - ns 70 - - 60 - 30 tCSH - 25 CS Hold Time CStoRAS Pre-charge Time tSRS 10 - 10 - 10 - 10 - 10 - ns Transition Time (Rise to Fall) tr 3 50 3 50 3 50 3 50 3 50 ns Refresh Period tREF - 8 8 - 8 8 - 8 ms - - ns 7 Read Cycle Parameter Symbol HM511002A-6 Min Max HM51l002A-7 Min Max HM51l002A-8 Min Max HM511002A-1O Min Max HM511002A-12 Min Max Unit Note Access Time from RAS tRAC - 70 120 ns 2,3 - 20 25 - - 20 - 100 tACS - 60 Access Time from CS 30 - 30 ns 3,4 Access Time from Address tAA - 30 - 35 - 40 - 50 - 55 ns 3,5,14 Read Command Setup Time tRCS 0 - 0 - 0 - 0 - 0 - os Read Command Hold Time to CS tRcH 0 - 0 - 0 - 0 - 0 - ns Read Command Hold Time to RAS tRRH 10 - 10 - 10 - 10 - 10 - ns Column Address to RAS Lead Time tRAL 30 - 35 - 40 - 50 - 55 - ns 80 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 113 HM511002A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Read Cycle (continued) Parameter HM511oo2A-6 Symbol HM511oo2A-8 HM511002A-7 Min Max Min Max HM511002A-1O HM511oo2A-12 Min Max Min Max Min Max Unit Note 16 RAS to Column Address Hold Time tAHR 15 - 15 - 15 - 15 - 15 - ns Output Hold Time from Address tAOH 5 - 5 - 5 - 5 - 5 - ns Output Buffer Tum-olTTime tOFF - 20 - 20 - 20 - 25 - 30 ns 60 - 70 - 80 - 100 - 120 - ns Column Address Hold Time tAR to RAS on Read 6 Write Cycle Parameter Symbol HM511002A-1O HM511oo2A-6 HM511oo2A-7 HM511002A-8 Min Max Min Max Min Max Min Max HM511002A-12 Min Max Unit Note 10 Write Command Setup Time twcs 0 - 0 - 0 - 0 - 0 - ns Write Command Hold Time tWCH 15 - 15 - 20 - 25 - 25 - ns Write Command Hold Time to RS tWCR 55 - 65 - 75 - 95 - 115 - ns Write Command Pulse Width twp 10 - 10 - 15 - 15 - 20 - ns Write Command to RAS Lead Time tRWL 20 - 20 - 25 - 25 - 30 - ns Write Command to CSLeadTime tCWL 20 - 20 - 25 - 25 - 30 - ns Data-in Setup Time tDS 0 - 0 - 0 - 0 - 0 - ns 11 Data-in Hold Time tDH 15 - 15 - 20 - 25 - 25 - ns 11 Data-in Hold TimetoRAS tDHR 55 - 65 - 75 - 95 - 115 - ns Column Address Hold Time to RAS or Write tAWR 55 - 65 - 75 - 95 - 115 - ns Read-Modify-Wrlte Cycle Parameter Symbol HM511oo2A-6 HM511oo2A-7 Min Max Min Max HM511oo2A-1O HM511002A-12 Min Max Min Max Min Max HM511oo2A-8 Unit Note Read-Write Cycle Time tRwC 145 - 155 - 190 - 220 - 255 - ns RAS to WE Delay Time tRWD 60 - 70 - 80 - 100 - 120 - ns 10 CStoWE Delay Time tCWD 20 - 20 - 25 - 30 - 30 - ns 10 Column Address to WE Delay Time tAWD 30 - 35 - 40 - 50 - 55 - ns 10 Output Hold Time from WE tWOH 0 - 0 - 0 - 0 - 0 - ns @HITACHI 114 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HM511002A Series Refresh Cycle Parameter HM511002A-7 HM511002A-6 Symbol Min Max Min HM511002A-8 Max Max Min HM511002A-1O Min Max HM511002A-12 Min Max Unit CS Setup Time (CS Before RAS Refresh) tCSR 10 - 10 - 10 - 10 - 10 - ns CSHoldTime (CS Before RAS Refresh) tCHR 15 - 15 - 20 - 20 - 25 - ns RAS Precharge to CS Hold Time tZRH 10 - 10 - 10 - 10 - 10 - ns Note SC Mode Cycle Parameter Symbol HM511002A-6 HM511002A-7 HM511002A-8 Min Max Min Max Min Max HM511002A-1O Min - 40 - 45 - 55 Max HM511002A-12 Min Max Unit SCMode Cycle Time tsc 35 SC Mode RAS Pulse Width tRASC - RAS to Second WE Delay Time tRSWD 70 - 80 - 90 - 110 - 135 - ns SCModeCS Precharge Time tSI 10 - 10 - 10 - 10 - 15 - ns Write Invalid Time tWI 10 - 10 - 10 - 10 - 15 - ns 100000 - 100000 - 100000 - - 60 100000 - - Note ns 100000 ns SC Mode Read-Modify-Write and Mixed Cycle Parameter Symbol HM511002A-6 HM511002A-7 HM511 002A-8 Min Max Min Max Min Max HM511002A-1O Min Max HM511002A-12 Min Max Unit Note SC Mode Cycle Time on Read-Write tSRW 70 - 80 - 90 - 105 - 120 - ns 12 Access Time from Previous WE tALW - 65 - 75 - 85 - 100 - 115 ns 3, 13 Previous WE to Column Address Delay Time tLWAD 20 35 20 40 25 45 25 50 30 60 ns 15 Column Address Hold Time to Previous WE tAHLW 65 - 75 - 85 - 100 - 115 - ns Output Enable Time from WE tow - 25 - 25 - 30 - 30 - 35 ns @HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1S19· (415) 5S9-S300 115 HM511002A Series Notes: 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :S tRCD (max) and tRAD :S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD O!: tRCD (max), tRAD :S tRAD (max). 5. Assumes that tRCD :S tRCD (max), tRAD O!: tRAD (max). 6. tOFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. Transition times are measured between VIH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tACS. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. twcs, tRWD, tcwD and tAwD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs O!: twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; iftRWD O!: tRWD (min), tCWD O!: tcwD (min) and tAWD O!: tAWD (min), the cycle is a read-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to CS leading edge in early write cycles and to WE leading edge in delayed write or readmodify-write cycles. 12. tSRw (min) = tAWD (min) + tLwAD (max) + tT' 13. Assumes that tLWAD :S tLWAD (max). If tLWAD is greater than the maximum recommended value shown in this table, tALW exceeds the value shown. 14. Assumes that tLWAD O!: tLWAD (max). 15. Operation with the tLwAD (max) limit insures that tALW (max) can be met, tLWAD (max) is specified as a reference point only; iftLWAD is greater than the specified tLwAD (max) limit, then access time is controlled exclusively by tAA' 16. tAHR is defined as the time at which the column address hold. 17. An initial pause of 100 I1-s is required after power-up followed by eight or more initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). If internal refresh counter is used, eight or more CAS before RAS refresh cycles are required . • TIMING WAVEFORMS • Read Cycle " iRAS / 1\ tNI' 1M' ".. I.,. tACO lCSH / 1\ ~ - ,--IRAH Address 7lJ Row tRAI t!fAD @ l\-- ~ Kllillil Column J /////111/ -~ i _L1(!.1 I I I I lACS IAA ~ Valid Output Oout 1> I fRA( r!IlJlJ: Don't Care 0117-5 ~HITACHI 116 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM511002A Series • Early Write Cycle IRe tus I. L l~CD Address 'weB twes tD' D,n Dout Valid Input High·Z*2 Notes) * 1.1ZZZZ2I : Dolo" .2. Iwcs ~ t.'cs Care (min) 0117-6 ~HITACHI Hitachi America, Ltd,. Hitachi Plaza· 2000 Sierra Point Pkwy,· Brisbane, CA 94005·1819· (415) 589-8300 117 HM511002A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Read-Modify-Write Cycle Add.... D,o 0.., 1 [17Zlj u"" c... 0117-7 • RAS Only Refresh Cycle 'Be Address HIch-z Notes) el.l?lZl2l: Doo', Care .2. Refresh address AO·AS (AXO·AXS) 0117-8 eHITACHI 118 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589·8300 HM511002A Series • CAS Before RAS Refresh Cycle IIC ',AI ICH' Address I!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! IIiab-Z Dout IZZZ23 : Don't cue • Static Column Mode Read Cycle Addres. I •• Dout I .. fZZ!ZZI : Don't Care 0117-10 eHITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 119 HM511002A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Static Column Mode Write Cycle (1) 'RAse RAS tRCD CS Address Din Dout Notes) *1 ~ : Don', Care *2 t ..csOl:torcs(min) 0117-11 ~HITACHI 120 Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM511002A Series • Static Column Mode Write Cycle (2) Addre•• Din Dout Notes) "I. ~ : Don'\ c.... *2. twel ~ twcs(min) 0117-12 @HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 121 HM511002A Series • Static Column Mode Read-Modify-Write Cycle Address Din Dout E2ZI : Don't care. 0117-13 • Static Column Mode Mixed Cycle t ule Address Din Dout I· .,. Early Write Read .1 Read-Modify-Write t'L2l : Don't care. 0117-14 • 122 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM511002A Series SUPPLY CURRENT (ACTIVE) VS. SUPPLY VOLTAGE SUPPLY CURRENT (ACTIVE) VS. AMBIENT TEMPERATURE 1.3 1.3 r---r----,..------r----, 1.2 1.21---1---1r-----+---i 1.1 V~ 1.0 ./ l.l1---I---1r-----+---i 1.0F""--t-.....f-=~;;:::::::-1 '/ ./ 0.9 0.9/----t---1---t---l V 0.8 0.7 0.81---1----1-----+--...; 4.50 4.75 5.00 Supply Voltage Vee. 0.7':-0---:2~0--...,4.,.0---:!-.60,....---:'80· 5.50 5.25 Amblent Temperature To rel (V} SUPPLY CURRENT (ACTIVE) VS. FREQUENCY SUPPLY CURRENT (STANDBY) VS. SUPPLY VOLTAGE 10.0 1.3 CMOS 5.0 ] ~ 0 3 ~ J 1.0 0.5 iJi 0.1 / V 1.0 0.8 0.5 f 1.2 ~ 1.0 !... 0.8 Ji 0.6 u 8: ~ 0.4 4.50 V 5.25 5.50 SUPPLY CURRENT (STANDBY) VS. AMBIENT TEMPERATURE / 1.2 ] 1 ~ ~ J 1 1.1 / 3 1.0 0.9 0.8 4.75 5.00 Supply Voltage Vee (V) /V 3 /' V / 1.3 onte~.ce 1.4 1 4.75 (MHz) SUPPLY CURRENT (STANDBY) VS. SUPPLY VOLTAGE ] / 0.7 4.50 5.0 10.0 10 Frequency TTL /' 0.9 0.1 I 1.1 / 1.6 I~terf.ce 1.2 5.00 5.25 5.50 20 ............. '" 40 ~ 60 Ambient Temperature To (-C) Supply Voltage Vee (V) 8Q 0117-15 .HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 123 HM511002A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RAS ACCESS TIME RAS ACCESS TIME vs. SUPPL Y VOLTAGE vs. AMBIENT TEMPERATURE 1. 3 1. 3 1. 2 1. 1 1.0 ~ --- r-- r-- 0.9 0.8 0.7 4 .50 4.75 5.00 525 Vic Supppiy Voltage ~ 1 z 1. 1 - 1. 01--- ~ g o. 9 0( 1~ 5.50 o. 8 o. 7 ,::; CS ACCESS TIME ........... '--....... --.. ,0( 0.8 4.75 5.25 5.00 Supppiy Voltage --- V(( 5.50 / 9 ,/ V 8 o. 7 0 20 40 ADDRESS ACCESS TIME vs. AMBIENT TEMPERATURE 1. 3 1.3 ] 1. 2 1.2 1 z 1. 1 ~ 1. 0 ~ o.9 / ./ 1. 1 r-- 0( 80 60 Ambient Temperature Ta ('e) (V) ADDRESS ACCESS TIME vs. SUPPLY VOLTAGE .............. / / 1. 1 0.9 ,::; 80 vs. AMBIENT TEMPERATURE " 4.50 60 CS ACCESS TIME ~ 0.7 40 vs. SUPPLY VOLTAGE 1.2 1.0 20 Ambient Temperature Ta ('C) (VI 1.2 1.1 - L---L--- ,::; 1.30 ~ li:j ~ i 1.3 u ~ 1. 2 ---- r-- / 1.0 0.9 V / ~ ~ ~ o. 8 o. 7 0.8 4.50 4.75 5.00 5.25 5.50 20 40 AmbIent Temperature Ta Suppply Voltage Vee (V) 60 ('C) ~HITACHI 124 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589-8300 80 0117-16 HM511664 Series Preliminary 65,536·Word x 16·Bit Dynamic Random Access Memory • DESCRIPTION HM511664JP Series The Hitachi HM511664 are CMOS dynamic RAM orga· nized as 65,536·word x 16·bit. HM511664 have realized higher density, higher performance and various functions by employing 0.8 ",m CMOS process technology and some new CMOS circuit design technologies. The HM511664 offer Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM511664 to be packaged in standard 400 mil 40·pin plastic SOJ, standard 475 mil 40·pin plastic ZI P. 3DCP4QO (CP.40D) • FEATURES HM511664ZP Series • Single 5V (±10%) • High Speed Access Time ................... 80 ns/100 ns (max) • Low Power Dissipation Active Mode ................................. TBD Standby Mode ........................ 11 mW (max) • Fast Page Mode Capability • Byte Write Capability • 256 Refresh Cycles ............................. (4 ms) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh 3DZP40 (ZP·40) • ORDERING INFORMATION Part No. Access Time Package HM511664JP ·8 HM511664JP·1O 80ns lOOns 400 mil 4O·pin Plastic SOJ (CPAOD) HM511664ZP·8 HM511664Zp·1O 80ns lOOns 475 mil40·pin Plastic ZIP (ZP·40) • PIN DESCRIPTION Pin Name Function I/Ol-I10 16 Data·inlData·out RAS Row Address Strobe CAS Column Address Strobe UW Read/Upper Byte Write Enable LW Read/Lower Byte Write Enable OE Output Enable Power (+ 5V) Ground NC No Connection V"CJl I101CJZ 1/0ZQ3 1I03Q4 1/04Q5 40pV,. 39~II016 38 II01S 17, 1/014 36PIl013 ~~~~ ~~ ~~ltJ ~~~~~ 3Z NC~10 Address Input Refresh Address Input Vss HM511664JP Series 1I08 d9 Ao- A7 Vee • PIN OUT Vss 11 UW lZ Liid13 AAS"d14 AOej15 A1q16 AZQ17 II09 31 NC 30 V" Z9 ill Z8tJOE Z7QNC Z6PNC Z5PNC Z4pA7 A3Q18 Z3§A6 A4q19 ZZ AS vccej",z-,-O_ _-"Z",l V" HM511664ZP Series ~lNC !- 1I09 _3 1/011 ~5 1I0ll 6 7 1/015 8,....:...-=::..~9 "o::s !.ul== ---, 1/010 1/0ll 1/014 1I016 !/?Z !:~b=::r' :-=1~~15 ~~~1 . ',,3 .' 1/04 1/05 16 1/07 18 !!f ZO ~ZZ RAS Z4 17 II06 19 Iloa '21 Vee 23 LW A1 Z6 ----;Z5 AO A3 Z 8 h = Z 7 AZ Z9 A4 '"'[U"" NC 3Z 34 AS ~ 36, OE 38 V,. 40 I 33 V" - 3 5 A6 37 NC :.-.-139 CAS 0074-1 0074-2 (Top View) (Bottom View) ~HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 125 HM511664 Series • TRUTH TABLE Inputs I/O RAS CAS LW UW OE I/OI-I/Os H L L L L L L H H L L L L L H H H L H L L H H H H H L H H H H High-Z High-Z Dout Din Don't Care Din High-Z H L L L Operatiou I/0 9-IIOI6 High-Z High-Z Dout Don't Care Din Din High-Z Standby Refresh Read Lower Byte Write Upper Byte Write Word Write • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Voltage on Any Pin Relative to Vss VT -\.Oto Supply Voltage Relative to Vss Vee -\.Oto Short Circuit Output Current lout 50 Power Dissipation PT Operating Temperature Topr Storage Temperature Tstg Unit + 7.0 + 7.0 V V rnA 0.8 W + 70 55 to + 125 °C Oto - °C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to Parameter Symbol Min Typ Max Unit Vss 0 0 0 V Vee 4.5 5.0 5.5 V Vm 2.4 6.5 V I (I/Oi Pin) VIL -0.5 0.8 V 1,2 (Others) VIL -\.O - 0.8 V 1,2 Supply Voltage Input High Voltage Input Low Voltage Notes: I I + 70"C) Note I \. All voltage referenced to Vss. 2. The device will withstand undershoots to the - 2V level with a maximum pulse width of 20 ns at the - 1.5V level. (See figure \.) -1.0 V -1.5 V i'l-') tCAC> and tAA are determined as follows. / tRAD tRAD max. = tRCD - [tRCD(max) - tRAD(max)] tCAC tRAD min. tRCD min. tRCD max. 0145-5 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIR (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIR and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. twcs, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs 2: twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRwD 2: tRWD (min), tCWD 2: tcwD (min), tAwD 2: tAWD (min) and tcpw 2: tcpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. II. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. tRASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of tAA or tCAe or tACP' 14. An imtial pause of 100 I'-s is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required. IS. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. When both LW and UW go low at the same time, all 16-bits data are written into the device. LW and UW cannot be staggered within the same write cycle. @HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 161 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read Cycle tT tCRP Address I/O 1-1/0 16 Din 0145-6 ~HITACHI 162 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HM511664/L Series • Early Write Cycle tCRP Address Din Din 1/01-1/016 Dout ____________________________~H~ig~h~-Z~_______________________________ 0145-7 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 163 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Upper Byte Early Write Cycle Address Din 1/01-1/08 Din Din 1/09-1/016 Dout __________________________ H~ig~h~.Z~ ________________________________ 0145-8 ~HITACHI 164 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM511664/L Series • Lower Byte Early Write Cycle Address Din I/O 1-1/08 Dout ______________________________H_ig~h_-~z___________________________________ Din 1/09-1/016 Dout __________________________~H~i~g~h~-Z~________________________________ • ~ : VIHorV 1L OE: V 1H or V 1L 0145-9 $ HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 165 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Delayed Write Cycle tr teAs Address Din 1/01·/1016 Dout------------------+-----~ Ot • ~: Vlfi orV iL Invalid Dout comes out, when OE is low level. 0145-10 ~HITACHI 166 Hilachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM511664/L Series • Upper Byte Delayed Write Cycle tr Address Din 1/01-1/08 Dout-----------------------+--/ Din 1/09-1/016 Dout------------------+-----~ * ~ : VIHorV 1L Invalid Dout comes out, when OE is low level. 0145-11 eHITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 167 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Lower Byte Delayed Write Cycle tr tcAH Column Address Din 1/01·1/08 Dout----------------~------~ Din 1/09·1/016 Dout------------------+-----~ • ~ :V1HorVIL Invalid Dout comes out, when OE is low level. 0145-12 ~HITACHI 168 Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819. (415) 589·8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM511664/L Series • Read-Modify-Write Cycle Address Din 1/01-1/016 Dout ............................~r-............~ OE 0145-13 $HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 169 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Read Modify Upper Byte Write Cycle 0145-14 • 170 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM511664/L Series • Read Modify Lower Byte Write Cycle Address Din 1/01-1/08 Dout----------------~------_< Din 1/09-1/016 Dout .~ 0145-15 ~HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 171 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle Address 1101-1/016 High-Z Dout • OE, UW, LW •• ~ : V 1H orVIL : V1H orVIL ••• Refresh address: AO - A7 (AXO - AX7) 0145-16 • CAS Before RAS Refresh Cycle tOFFl 1/01-11016 Dout ** UW,LW,OE 0145-17 ¢!)HITACHI 172 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM511664/L Series • Hidden Refresh Cycle Address 1/01-1/016 OE 0145-18 • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 173 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read Cycle Address Din Dout 0145-19 ~HITACHI 174 Hitachi America, Ltd.• Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HM511664/L Series • Fast Page Mode Early Write Cycle Address 1/01-1i016 High-Z Dout --------------------------~------------------------------------------- 0145-20 @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819. (415) 589-8300 175 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Upper Byte Early Write Cycle Address Dout______________________H_i~g~h.~Z~____________________________ • OE ; V 1H orV1L ~ ;V1HorVIL 0145-21 • 176 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819· (415) 589·8300 HM511664/L Series • Fast Page Mode Lower Byte Early Write Cycle Address LW Dout ____________________~H~i9~h~.Z~____________________________________ Din !/09·1/016 Dout ____________________~H~ig~h~.~Z_____________________________________ • OE : V 1H or V 1L ~ :VIHorV1L 0145-22 @HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589·8300 177 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Delayed Write Cycle High-Z Dout----t----------~----------------+_-----tooo-*"~- 0145-23 ~HITACHI 178 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM511664/L Series • Fast Page Mode Upper Byte Delayed Write Cycle Din 1/01·1/08 Dout-------------------44---------~~--~------------+4-------------- Din 1/09·:/016 High·Z Dout --------~-t--------------------------------------~--------------- 0145-24 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 179 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Lower Byte Delayed Write Cycle 0145-25 $ 180 HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM511664/L Series • Fast Page Mode Read-Modify-Write Cycle 0145-26 • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300 181 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read-Modify-Upper-Byte-Wrlte Cycle 0145-27 o 182 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1619. (415) 569-6300 HM511664/L Series • Fast Page Mode Read-Modify-Lower-Byte-Write Cycle 0145-28 ¢!)HITACHI Hitachi America, Ltd. • Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 183 HM511664/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • CAS Before RAS Refresh Counter Check Cycle (Read) Address toze High-Z Din tCAe 1/01-1/016 Dout ------------------------+---------~I Dout • ~ : V1H orVIL 0145-29 ~HITACHI 184 Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM511664/L Series • CAS Before RAS Refresh Counter Check Cycle (Write) Address I/O 1·1/016 Dout ________________________~H~i2g~h.~Z~________________________________ 0145-30 @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589·8300 185 HM511665 Series Preliminary 65,536·Word x 16·Bit Dynamic Random Access Memory • DESCRIPTION HM511665JP Series The Hitachi HM511665 are CMOS dynamic RAM organized as 65,536-word x 16-bit. HM511665 have realized higher density, higher performance and various functions by employing 0.8 p'm CMOS process technology and some new CMOS circuit design technologies. The HM511665 offer Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM511665 to be packaged in standard 400 mil 40-pin plastic SOJ, standard 475 mil40-pin plastic ZIP. 3DCP40D (CP-40D) • FEATURES HM511665ZP Series • Single 5V (± 10%) • High Speed Access Time ................... 80 ns/100 ns (max) • Low Power Dissipation Active Mode ................................. TBD Standby Mode ........................ 11 mW (max) • Fast Page Mode Capability • Write per Bit Capability • 256 Refresh Cycles ............................. (4 ms) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh SDZP40 (ZP-40) • ORDERING INFORMATION • PIN OUT Part No. Access Time Package HM5Il665JP-S HM511665JP-1O Sans lOOns 400 mil40-pin Plastic SOJ (CP-40D) HM511665ZP-S HM511665ZP-1O Sans lOOns 475 mil40-pin Plastic ZIP (ZP-40) • PIN DESCRIPTION Pin Name Ao-A7 Address Input Refresh Address Input WI/I/01-Wl6/11016 Write SelectiData-in/Data-out RAS Row Address Strobe Column Address Strobe WBIWE Write per BitlRead/Write Enable WBIWE Write per BitiReadlWrite Enable OE Output Enable Power (+ 5V) Ground W3/103 W41l04 W5/105 W6/106 W16II016 3 WI0/IOI0 W151l015 W14/1014 W13/1013 W12l1012 W11/1011 WIO/IOIO W91l09 NC V" CAS 5 7 9 11 19 W81l08 AO Al A2 A3 A4 NC NC NC Al A6 A5 Vee V" 0075-2 0075-1 (Top View) (Bottom View) No Connection ~HITACHI 186 W121l012 W14/J014 W16/1016 WIII01 OE CAS VSS NC HM511665ZP Series v" Vee WIIIOI W8/108 NC Function Vee HM511665JP Series Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM511665 Series • TRUTH TABLE Inputs I/O RAS CAS WBIWE OE H L L L L H H L L L H H H L H H H L H H Operation Wl/I/Oj-W16/1/016 Standby Refresh Read Write High-Z High-Z Dout Din High-Z • ABSOLUTE MAXIMUM RATINGS Parameter Voltage on Any Pin Relative to V88 Supply Voltage Relative to V88 Value Symbol Unit VT -1.0to + 7.0 V Vee -1.0to +7.0 V rnA Short Circuit Output Current lout 50 Power Dissipation PT 0.8 Operating Temperature Topr Storage Temperature Tstg oto W ·C + 70 ·C - 55 to + 125 • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70°C) Parameter Supply Voltage Notes: Typ Max Unit 0 0 0 V I I Note Vee 4.5 5.0 5.5 V - 6.5 V I I VIH 2.4 (Will/Oi Pin) VIL -0.5 - 0.8 V 1,2 (Others) VIL -1.0 - 0.8 V 1,2 Input High Voltage Input Low Voltage Min Symbol VS8 1. All voltage referenced to V88. 2. The device will withstand undershoots to the - 2V level with a maximum pulse width of 20 ns at the - 1.5V level. (See figure 1.) -1.0 V -1.5 V I'i.f-- -2.0 V -? IE- 20 ns (max) 0075-3 Figure 1. Undershoot of input voltage ~HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 187 HM511665 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • DC Electrical Characteristics (TA Parameter Operating Curreut = Symbol 0 to +70'C, Vee Min 5V ±10%, Vss = OV) HMSI166S-1O Max Min Max Unit RAS, CAS Cycling tRC = Min 2 rnA TTL Interface RAS, CAS = VIH, DoU! = High-Z I rnA CMOS Interface RAS, CAS HITACHI 202 Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-t 819' (415) 589-8300 HM511665 Series • CAS Before RAS Refresh Check Cycle (Write) -M-~-tT ~LL", _______________ Di H...:i9:...h_-Z _ _ "_ _ _ _ _ _ _ _ _ _ _ _ _ __ • ~ : VIH orV1L 0075-17 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 203 HM511665/L Series 65,536-Word x 16-Bit Dynamic RAM • DESCRIPTION HM511665JP Series The Hitachi HM511665/HM511665L are CMOS dynamic RAM organized as 65,536-word x 16-bit. HM511665/11665L have realized higher density, higher performance and various functions by employing 0.8 /-tm CMOS process technology and some new CMOS circuit design technologies. The HM511665/HM511665L offer Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM5116651 HM511665L to be packaged in standard 400 mil 40-pin plastic SOJ, standard 475 mil 40-pin plastiC ZIP. 3DCP400 (CP-4OD) HM511665ZP Series • FEATURES • Single 5V (±10%) • High Speed Access Time ................... 80 ns/100 ns (max) • Low Power Dissipation Active Mode ................ 633 mW/495 mW (max) Standby Mode (TTL) .................. 11 mW (max) Standby Mode (CMOS) ............... 5.5 mW (max) ..... 1.1 mW (max) (L-Version) • Fast Page Mode Capability • Write per Bit Capability • 256 Refresh Cycles ............................. (4 ms) ................. (32 ms) (L-Version) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh • Battery Back-up Operation HM511665L Series (L-Version) 3DZP40 (ZP-40) • PIN OUT HM511665JP Series Wl6/1016 WI5/1015 • PIN DESCRIPTION Wl.4/I014 Pin Name Wl/I/Oj-W16/I/Oj6 Write Se1ect/Data-in/Data-out NC RAS Row Address Strobe Vee V" NC CAS CAS Column Address Strobe WB/WE Write per BitiRead/Write Enable OE Output Enable Vee! Power ( + 5V) Ground NC No Connection 2 WIZlIOIZ WII/IOIl WIO/IOIO Address Input Refresh Address Input VSS2 W9/I09 Wll/IOll W13/I013 WI3/1013 Function AQ- A7 Notes: HM511665ZP Series V" W9/109 NC waiiiE DE AO AI NC NC NC AZ A7 A3 A6 A4 A5 Vee -,:::,--_...::..:rV" 0146-2 0146-1 13, 21, 30 pin). All Vee pins must be connected with the same power-supply wiring on the memory board. 2. This device has 3 VSS pins (SOJ: 21, 30, 40 pin/ ZIP: !D, 33, 40 pin). All Vss pins must be connected with the same ground wiring on the memory board. (Bottom View) (Top View) 1. This device has 3 Vee pins (SOJ: I, 11,20 pin/ZIP: • ORDERING INFORMATION Part No. Access Time HM511665JP-8 HM511665JP-10 80ns lOOns HM511665U-8 HM511665U-1O 80ns lOOns HM511665ZP-8 HM511665ZP-1O 80ns lOOns HM511665LZ-8 HM511665LZ-1O SOns lOOns ~HITACHI 204 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 Package 400 mil 4O-pin PlasticSOJ (CP-40D) 475 mil40-pin Plastic ZIP (ZP-40) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM511665/L Series • BLOCK DIAGRAM I WBIWE J. Write Per ~ Bit Control [ J. t.I W811081 Circuit Circuit Circuit Circuit J. IWI4110141 IWI3110131 IWllIIOU! IWIOIIOIO! 1- ! t t t IIOBulTer 110 BulTer I/0BulTer J/OBulTer t.- ~ I W711071 I W61106 I 1I0BulTer ~ ~, Column Decoder Sense Amp& 110 Bus 128k Memory Cen Array 128k Memory Cen Array I W41104! I/0BulTer ~ ~. l? Column Decoder Sense Antp& 110 Bus Row Address t Buffer r--1' I W31103 ! J ! J HI/ODulTer 128k Memory Cell Array 128k Memory Cell Array HIIODulTer I Decoder Sense Aml'& 110 Bus & I Address I W21102! ! HllODulTer I I S. l~ 128k Memory Cell Array 128k Memory Cen Array Column Decoder Sens. AmI' & JIOi3us 128k Memory Cell Array T I Driver I Row I WIIIOI ! ! 1I0nulTer ~ T Decoder t llODulTer t.- ~ l? Colun.., T I Column "t-- I W511051 ! J 11/0DulTer T J IWl2Jl0121 I/0BulTer ~ .J. I W91109 I J. ! S .? 128k Memory Cell Array J. -OE Control - 110 BulTer ! 41110BulTer ~ I OE CAS Control IWI5II0151 ! ~LUOBulTer J I ill Control .J. IW161101~ I CAS -WE Control i-- Circuit I RAS Address I3uffer t I AO-A 7 0146-3 @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 205 HM511665/L Series • TRUTH TABLE Inputs I/O RAS CAS WB/WE OE H L L L L H H L L L H H H L H H H L H H Operation WlII/Ol-WI6/I/0 16 High-Z High-Z Dout Din High-Z Standby Refresh Read Write • ABSOLUTE MAXIMUM RATINGS Value Unit Voltage on Any Pin Relative to Vss Parameter VT -1.0to +7.0 V Supply Voltage Relative to Vss Vee -1.0to +7.0 V Short Circuit Output Current lout 50 mA Symbol Power Dissipation PT 0.8 W Operating Temperature Topr Oto + 70 Storage Temperature Tstg - 55 to + 125 'c 'c • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70'C) Parameter Supply Voltage Notes: Min Typ Max Unit 0 0 0 V I I Vee 4.5 5.0 5.5 V 2.4 6.5 V 1 (Wi/I/Oi Pin) VIL -0.5 0.8 V 1,2 (Others) VIL -1.0 - 0.8 V 1,2 1 I. All voltage referenced to VSS' 2. The device will withstand undershoots to the - 2V level with a maximum pulse width of 20 ns at the - 1.5V level. (See figure I.) VIH -1.0 V I -1.5 V -2.0 V -ll ~ 20 ns(max) 0146-4 Figure 1. Undershoot of input voltage ~HITACHI 206 Note VIH Input High Voltage Input Low Voltage Symbol Vss Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM511665/L Series • DC Electrical Characterlstica (TA Parameter = 0 to Symbol Operating Current ICCI Standby Current +70"C, Vee = 5V HM511665-8 HM511665L-8 ±10%, Vss = OV) HM511665-10 HM511665L-IO Min Max Min Max - 115 - 90 Unit mA 2 mA I mA ICC2 (L-Version) Standby Current ICC2 - 200 - 200 p.A RAS Only Refresh Current Icc3 - 90 mA Icc6 - 115 CAS Before RAS Refresh Current 115 - 90 rnA Test Conditions RAS, CAS Cycling tRC = Min TIL Interface RAS, CAS = VIH, Dout = High-Z CMOS Interface RAS, CAS ~ VCC - 0.2V Dout = High-Z CMOS Interface RAS, CAS = VIH WE, OE, Address and Din = VIHorVIL Dout = High-Z 1,2 4 4 5 = Min tRC = Min tpc = Min tRC = 125 p.s 2 tRC Fast Page Mode Current Icc7 - 100 - 85 mA (L-Version) Battery Back-up Operating Current (Standby with CBR Refresh) ICCIO - 300 - 300 p.A Input Leakage Current ILl -10 10 -10 10 p.A OV S Yin S 6.5V Output Leakage Current IW -10 10 -10 10 p.A OV S Vout S 5.5V, Dout = Disable Output High Voltage VOH 2.4 High lout 0 Vcc 0.4 V VOL VCC 0.4 2.4 Output Low Voltage V Low lout Notes: Note 1,3 !&As S I p.s_ 0 WE = VIH, CAS = VIL OE, Address and Om = VlHorVIL Dout = High-Z 5 = - 2.5 rnA = 2.1 mA 1. ICC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. Clock voltages (RAS and CAS) must be applied simultaneously with or prior to applying supply voltage. 5. VCC - 0.2V S VIH S 6.5Vand OV S VIL S 0.2V. • CapaCitance (TA = 25"C, Vee = 5V ±10%) Parameter Symbol Typ Max Unit Note Input Capacitance (Address) Cu 5 pF I Input Capacitance (Clocks) CI2 7 pF I Output Capacitance (Data-in, Data-out) CliO - 7 pF 1,2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out. • AC Characteristics (TA Test Conditions = 0 to Input Rise and Fall Times: Input Timing Reference Levels: Output Load: +70"C, Vee = 5V ±10%, Vss = 0V)1, 14, 15 5 ns 0.8V,2.4V CL (50 pF) 1 TIL Gate + (Including scope and jig) • HITACHI Hitachi America, Ltd •• Hitachi Plaza .2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 207 HM511665/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Read, Write, Read-Modlfy-Wrlte and Refresh Cycles (Common Parameters) Parameter HM511665-8 HM511665L-8 Symbol HM511665-1O HM511665L-1O Unit Min Max Min Max Note Random Read or Write Cycle Time tRC 135 - 170 - ns RAS Precharge Time RAS Pulse Width CAS Pulse Width tRP tRAS 45 80 - 60 - ns 10000 100 10000 ns teAs 30 10000 40 10000 Row Address Setup Time tASR 0 - 0 Row Address Hold Time tRAH 10 10 Column Address Setup Time Column Address Hold Time tASC tCAH 0 - - 0 15 - ns ns ns ns ns RAS to CAS Delay Time tRco tRAO 50 20 60 ns 8 35 15 45 ns 9 RAS to Column Address Delay Time 15 20 15 RAS Hold Time tRSH 30 - 40 - ns CAS Hold Time CAS to RAS Precharge Time tcSH 80 10 15 - 100 10 - ns ns 15 0 0 - ns ns 0 - - ns 3 50 3 50 4 4 - 32 - ns ms 7 - 32 ms L-Version OE to Din Delay Time OE Delay Time from Din CAS Setup Time from Din Transition Time (Rise and FaIl) Refresh Period tcRP tooo tozo tozc tT lREF 0 Read Cycle Parameter Symbol HM511665-8 HM511665L-8 Min Max - 55 30 40 ns 0 - 0 - 0 45 - 0 0 55 - ns 0 0 20 0 20 0 20 15 0 20 15 ns ns ns - Actess Time from Address tAA - 30 45 Access Time from OE toAC tRes - tRCH tRRH tRAL Output Buffer Turn-off to OE toFFI toFF2 CAS to Din Delay Time RAS Hold Time Referenced to OE tcoo tROH 2,3 3,4,13 ns ns ns tCAC Output Buffer Turn-off Time Note 40 tRAC Access Time from CAS Read Command Hold Time to RAS Column Address to RAS Lead Time Unit - Access Time from RAS Read Command Setup Time Read Command Hold Time to CAS HM511665-1O HM511665L-1O Min Max 100 80 - 10 ns ns ns - 10 3,5,13 6 6 ns Write Cycle Parameter Write Command Setup Time twes Write Command Hold Time Write Command Pulse Width tWCH twp Write Command to RAS Lead Time Write Command to CAS Lead Time lRWL Data-in Setup Time Data-in Hold Time HM511665-8 HM511665L-8 Symbol tcWL tos tOH - ns 10 - ns 20 20 - ns - ns 0 - 15 - ns ns - 0 - 15 15 0 15 15 15 Note Max Max 0 Unit Min Min 20 20 HM511665-1O HM511665L-1O - ns eHITACHI 208 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 11 11 HM511665/L Series Read-Modify-Write Cycle Parameter HM511665-8 HM511665L-8 Symbol Min ---_. - HM511665-1O HM511665L-1O Max Min Unit Note Max Read-Modify-Write Cycle Time tRWC 185 - 220 - ns RAS to WE Delay Time tRwD 105 - 125 - ns 10 CAS to WE Delay Time tCWD 55 - 65 - ns 10 Column Address to WE Delay Time tAWD 70 - 80 - ns 10,13 OE Hold TIme from WE tOEH IS - IS - ns Refresh Cycle Parameter HM511665-8 HM511665L-8 Symbol HM511665-1O HM511665L-1O Max Min Min Unit Note Max CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 10 - 10 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - ns CAS Precharge Time in Normal Mode tCPN 10 - 10 - ns Fast Page Mode Cycle Parameter HM511665-8 HM511665L-8 Symbol Min HM511665-1O HM511665L-1O Max Min Unit Note Max Fast Page Mode Cycle Time tpc 55 - 65 - ns Fast Page Mode CAS Precharge Time tcp 10 - 10 - ns Fast Page Mode RAS Pulse Width tRASC 80 100 100000 ns 12 Access Time from CAS Precharge tACP - 50 - 60 ns 3, 13 RAS Hold Time from CAS Precharge tRHCP 45 - 55 - ns Fast Page Mode Read-ModifyWrite Cycle CAS Precharge to WE Delay Time tcpw 70 - 80 - ns Fast Page Mode Read-ModifyWrite Cycle Time tpCM 100 - 110 - ns 100000 Counter Test Cycle Parameter CAS Precharge Time in Counter Test Cycle HM511665-8 HM511665L-8 Symbol tCPT HM511665-1O HM511665L-1O Min Max Min 40 - 40 Unit Note Max - ns Write Per Bit Cycle16, 17 Parameter HM511665-1O HM511665L-1O HM511665-8 HM511665L-8 Symbol Min Max Min Max - Write per Bit Setup Time tWBS 0 - 0 Write per Bit Hold Time tWBH 10 - 10 Write per Bit Selection Setup Time tWDS 0 - Write per Bit Selection Hold Time tWDH 10 - Unit Note ns ns 0 - ns 10 - ns ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 209 HM511665/L Series Notes: 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :S tRCD (max) and tRAD :S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to I TIL load and 50 pF. 4. Assumes that tRCD ~ tRCD (max) and (tRCD - tRAD) ~ [tRCD (max) - tRAD (max)l. 5. Assumes that tRAD ~ tRAD (max) and (tRCD - tRAD) :S [tRCD (max) - tRAD (max)l. tRAe. tcAC, and tAA are determined as follows: tAA tRAD[ns] tRAD max. tRAD .. = tRCD • [tRCD(max) . tRAD(max)] tCAC tRAC tRAD min. .. , ,, , tRCD min. tRCD max. tRCD[ns] 0146-5 6. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 10. twcs, tRWD, tcWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs ~ twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRwD ~ tRwD (min), tCWD ~ tCWD (min), tAWD ~ tAWD (min) and tcpw ~ tcpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modifY-write cycle. 12. tRASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of tAA or tCAC or tACP. 14. An initial pause of 100 p.s is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a miuimum of eight CAS before RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. When using the write-per-bit capability, WB/WE must be low as RAS falls. 17. The data bits to which the write operation is applied can be specified by keeping WVIOi high with setup and hold time referenced to the RAS negative transition . • 210 HITACHI Hitachi America. Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HM511665/L Series • TIMING WAVEFORMS • Read Cycle tT tCRP wlnOI [Dout D tCDD WI6nOl6 Din tODD 0146-6 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005· 1819· (415) 589·8300 211 HM511665/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Early Write Cycle RAS tT tCRP tCSH CAS tASR • •• ~ :V1HorVll at: V1H or V 1l 0146-7 • 212 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM511665/L Series • Delayed Write Cycle ** * ~ :V1HorVll ** Invalid Dout comes out, when OE is low level. 0146-8 • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 213 HM511665/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Read-Modify-Write Cycle \ Address Wln01 Wl~016 [Din Dout ---------------+----~~uouV+---~------~-------------------- teAC 0146-9 _HITACHI 214 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589·8300 HM511665/L Series • RAS Only Refresh Cycle Address High-Z Wln01 Dout--------------------------~~~----------------------------------- • OE. WE : V1H or VIL H WI6nOl6 ~ :VIHorV 1L ••• Refresh address: AO - A7 (AXO - AX7) 0146-10 • CAS Before RAS Refresh Cycle •• WE WI6nOl6 0146-11 $ HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589-8300 215 HM511665/L Series • Hidden Refresh Cycle 0146-12 ~HITACHI 216 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM511665/L Series • Fast Page Mode Read Cycle WMOI Wl6ll016 0146-13 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 217 HM511665/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Early Write Cycle Wl6nOl& High·Z Dout --------------------------~--------------------------------------- * OE : V 1H or V 1l ** ~ : VIH orVll 0146-14 ~HITACHI 218 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300 HM511665/L Series • Fast Page Mode Delayed Write Cycle w16no~'ou1'------------------------ High-Z ______________________________________ +-________ 0146-15 @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 219 HM511665/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read-Modify-Write Cycle • ~ : v.. or vII. 0146-16 • 220 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 HM511665/L Series • CAS Before RAS Refresh Counter Check Cycle (Read) W1611016 Dout ------------+-----{I Dout * ~ :VIHorVIL 0146-17 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-t 819' (415) 589-8300 221 HM511665/L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • CAS Before RAS Refresh Counter Check Cycle (Write) WlnOI [ Din High-Z Wl6nOl6 Dout-------------------------------~----------------------------------- 0146-16 ~HITACHI 222 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 HM511666 Series Preliminary 65,536-Word x 16-Blt Dynamic RAM • DESCRIPTION HM511666JP Series The Hitachi HM511666 are CMOS dynamic RAM organized as 65,536-word x 16-bit. HM511666 have realized higher density, higher performance and various functions by employing 0.8 ,..m CMOS process technology and some new CMOS circuit design technologies. The HM511666 offers Static Column Mode as a high speed access mode. Multiplexed address input permits the HM511666 to be packaged in standard 400 mil 40-pin plastic SOJ, standard 475 mil40-pin plastic ZIP. 3DCP40D (CP-40D) • FEATURES HM511666ZP Series • Single 5V (±10%) • High Speed Access Time ................... 80 ns/100 ns (max) • Low Power Dissipation Active Mode ................ 633 mW/495 mW (max) Standby Mode ........................ 11 mW (max) • Static Column Mode Capability • Byte Write Capability • 256 Refresh Cycles ............................. (4 ms) • 2 Variations of Refresh RAS Only Refresh CS Before RAS Refresh 3DZP40 (ZP-40) • PIN OUT HM511666JP Series • ORDERING INFORMATION Part No. Access Time Package HM511666JP-8 HM511666JP-1O 80ns lOOns 400 mi140-pin Plastic SOJ (CP-40D) HM511666ZP-8 HM511666ZP-1O 80ns lOOns 475 mi140-pin Plastic ZIP (ZP-40) vee lIOl 1I0Z lI03 lI04 1/05 II06 II07 1108 NC Vee • PIN DESCRIPTION Pin Name Function Ao- A7 Address Input Refresh Address Input Data-in/Data-out RAS Row Address Strobe CS Chip Select UW Read/Upper Byte Write Enable CS DE iiAs LW Read/Lower Byte Write Enable OE Output Enable VCC' 1 Power ( + 5V) VSS'2 Ground NC No Connection Vss 11016 II015 11014 1/013 1/01Z 1/011 II010 109 NC ~ UW LW 110 1-110 16 Notes: 1 NC NC NC A7 A6 AS Vss AO Al AZ A3 A4 Vee 0147-1 (Top View) 1. This device has 3 Vee pins (SOJ: I, II, 20 pin/ZIP: 13, 21, 30 pin). All Vcc pins must be connected with the same power-supply wiring on the memory board. 2. This device has 3 Vss pins (SOJ: 21, 30,40 pin! ZIP: 10, 33, 40 pin). AIl VSS pins must be connected with the same ground wiring on the memory board. $ ~ HM511666ZP Series .-- ~1 Ne 109 2 1=3 1010 1011 4 5 101Z 1013 6 1 = 7 I014 1015 8 9 1016 1 = Vss 10 11101 10Z 12 1 = 13 Vee 10314 15 104 IDS 16 17 106 107 18 19108 NC 20 Zl Vee iiW ZZ Z3Lw RAS Z4 Z5 AD Al Z6 Z7 AZ A328 Z9 A4 Vee 30 31 Ne Ne 32 33 V.S AS 34 35 A6 A736 37 Ne DE 38 39 CS Vss 40 = = == = = = = = = = = = = = = = = --- -- 0147-2 (Bottom View) HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 223 HM511666 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM I Gp I LW l Lower Byte Write Control Circuit 1. Upper Byte Write Control Circuit t 41 110 BulTer I I 11015 t 1I0S t t 41 1/0 BulTer ~ ~ 12Sk Memory Cell Array "'t.- I I 1107 t HIIOBulTer Circuit Circuit 12Sk Memory Cen Array 128k Memory Cen Array I I 1I013 l ~ _t now Address ! 1I0BulTer .... t 1I0BulTer 1109 t I/0SulTer HIIOBulTer 128k Memory Cell Array I I 1102 ! 1/01 ! I Address AO-A 7 I r HIIOBulTerJ ~ Lr-1 12Sk Memory Cell Array Column Decoder Sense Amp& 110 Bus 12Sk Memory C.ll Array T I & Driver I I I/0BulTer ...r I now I "'t.- ~ I I ... I I .J.. t .... Column Decoder Sense Amp& 110 Bus II 1I0lO 1 Decoder Buffer ! 1103 1104 128k Memory Cen Array I I 1I0ll ~ ~, 12Sk Memory Cen Array ..j. 1I0BuITer .... 11/0BulTer Column Decoder Sense Amp& 110 Bus ! 1/0 BulTer I I 1I0S I I 11012 J I Column - ..j. ~. ~ .? Column Decoder Sense Amp& 110 Bus J I/0BulTer T I Circuit ~ I I 1106 J. . -OE Control 110 BulTer I/0BulTer I/0BulTer I I I I I OE CS Control .1. 11014 "'t.- ~ I -l. ;. I RAS Control I II 11016 q=o I RAS ..... I I I Address Buffer T I 0147-3 ~HITACHI 224 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HM511666 Series III TRUTH TABLE Inputs I/O Operation RAS CS LW UW OE 1/0,-1/08 1/°9-1/°,6 H L L L L L L H H L L L L L H H H L H L L H H H H L L L H H L H H H H High-Z High-Z Dout Din Don't eare Din High-Z High-Z High-Z D out Don't Care DID Din High-Z Standby Refresh Read Lower Byte Write Upper Byte Write Word Write III ABSOLUTE MAXIMUM RATINGS Parameter Symbol VT - 1.0 to Supply Voltage Relative to Vss Vee -1.0to lout 50 Short Circuit Output Current Power Dissipation PT Operatmg Temperature Topr Storage Temperature Tstg III ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to Parameter I I V V rnA W + 70 55 to + 125 ·C Oto - ·C + 70°C) Min Typ Max Unit 0 0 0 V Vee 4.5 5.0 5.5 V VIH 2.4 - 6.5 V I (I/Oi Pin) VIL -0.5 0.8 V 1,2 (Others) VIL -1.0 - 0.8 V 1,2 VSS Input High Voltage Input Low Voltage Unit + 7.0 + 7.0 0.8 Symbol Supply Voltage Notes: Value Voltage on Any Pin Relative to Vss Note I 1. All voltage referenced to Vss. 2. The device will withstand undershoots to the - 2V level with a maximum pulse width of 20 ns at the - 1.5V level. (See figure 1.) VIH -1.0 V I -1.5 V IV -2.0 V ...,. ~ 20 ns(max) 0147-4 Figure 1. Undershoot of input voltage ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 225 HM511666 Series • DC Electrical Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss = OV) Parameter Symbol Operating Current ICCI Standby Current HM511666-8 HM511666-1O Min Max Min Max - 115 - 90 Unit rnA RAS, CS Cycling tRC = Min TTL Interface RAS, CS = Vm, Dout = High-Z I rnA CMOS Interface RAS, CS ~ VCC - 0.2V, Dout = High-Z 4 90 rnA tRC = Min 2 tRe = Min - - 115 - 90 rnA - 110 - 100 rnA tsc = Min ICC3 - ICC6 ICC9 ILl -10 10 -10 10 p.A OV S Vin S 6.5V ILO -10 10 -10 10 p.A OV S Vout S 5.5V, Dout = Disable Input Leakage Current Output Leakage Current Output High Voltage VOH 1,2 rnA 115 RAS Only Refresh Current CS Before RAS Refresh Current Note 2 ICC2 Static Column Current Test Conditions 4 1,3 2.4 2.4 V High lout = - 2.5 rnA VCC VCC V 0 0.4 0 0.4 Low lout = 2.1 rnA VOL IcC depends on output load condition when the device is selected, Icc max is specified at the output open condition. Address can be changed once or less while RAS = VIL. Address can be changed once or less while CS = Vm. Clock voltages (RAS and CS) must be applied simultaneously with or prior to applying supply voltage. Output Low Voltage Notes: 1. 2. 3. 4. • Capacitance (TA = 25'C, Vee = 5V ±10%) Symbol Typ Max Unit Note Input Capacitance (Address) CII - 5 pF I Input Capacitance (Clocks) CI2 - 7 pF I Output Capacitance (Data-in, Data-out) CliO - 7 pF 1,2 Parameter Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CS = Vm to disable D out . ~HITACHI 226 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM511666 Series + 70°C, • AC Characteristics (TA = 0 to Test Conditions Input Rise and Fall Times Input Timing Reference Levels Output Load Vee = 5V ± 10%, Vss = OV)1. 14, 15, 16 5 ns O,8V,2.4V 1 TTL Gate + CL (50 pF) (Including scope and jig) Read, Write, and Refresh Cycles (Common Parameters) Parameter Symbol HM511666-1O HM511666-8 Min Max Min Max Unit Random Read or Write Cycle Time tRC 135 - 170 - ns RAS Precharge Time tRP 45 - 60 - ns RAS Pulse Width tRAS 80 10000 100 10000 ns CS Pulse Width tsp 30 10000 40 10000 ns Row Address Setup Time tASR 0 Row Address Hold Time tRAH 10 Column Address Setup Time tASW 0 Column Address Hold Time tAHW IS - RAS to CS Delay Time tRCD 20 50 RAS to Column Address Delay Time tRAD IS 35 RAS Hold Time tRSH 30 CS Hold Time tCSH 80 CS to RAS Precharge Time tcRP 10 OE to Dm Delay Time tODD IS - OE Delay Time from Din tDZO 0 - CS Setup Time from Din tDZC 0 - Transition Time (Rise and Fall) tT 3 Refresh Period tREF - Note ns IS - 20 60 ns 8 IS 45 ns 9 40 - ns 100 ns 0 - 0 - ns 50 3 50 ns 4 - 4 ms 0 10 0 10 IS ns ns ns ns ns ns 7 Read Cycle Parameter Symbol HM511666-8 HM51\666-1O Unit Note Min Max Min Max 80 - 100 ns 2,3 40 ns 3,4, \3 45 - 55 ns 3,5, 13 30 - 40 ns 0 - ns 0 ns 55 - Access Time from RAS tRAC Access Time from CS tACS Access Time from Address tAA - Access Time from OE tOAC - Read Command Setup Time tRCS 0 Read Command Hold Time to CS tRCH 0 Read Command Hold Time to RAS 30 tRRH 0 Column Address to RAS Lead Time tRAL 45 - Output ButTer Tum-otT Time tOFF! 0 20 0 20 ns 6 Output ButTer Tum-otT to OE tOFF2 0 IS 0 IS ns 6 CS to Din Delay Time tCDD 20 - 20 ns 5 - 100 - ns RAS Hold Time Referenced to OE tROH 10 RAS to Column Address Hold Time tAHR IS Output Hold Time from Address tAOH 5 Column Address Hold Time to RAS on Read tAR 80 0 10 IS ns ns ns ns 17 ns ~HITACHI Hitachi America, Ltd,. Hitachi Plaza. 2000 Sierra Point Pkwy,· Brisbane, CA 94005-1819· (415) 589-8300 227 HM511666 Series Write Cycle Parameter HM511666-8 Symbol HM511666-1O Min Max Min Max 0 15 Unit Note ns 10 Write Command Setup Time twcs 0 Write Command Hold Time tWCH 15 - Write Command Pulse Width twp 15 - 15 tRwL 20 20 Write Command to CS Lead Time tCWL 20 Data-in Setup Time tDS 0 - Data-in Hold Time tDH 15 - 15 Data-in Hold time to RAS tDHR 65 - 75 - Column Address Hold Time to RASon Write tAWR 65 - 75 - ns toEH 15 - 15 - ns Write Command to RAS Lead Time OE Hold Time from WE 20 0 ns ns ns ns ns 11 ns II ns Refresh Cycle Parameter HM511666-8 Symbol HM511666-1O Min Max Min Max Unit CS Setup Time (CS Before RAS Refresh Cycle) tCSR 10 - 10 - ns CS Hold Time (CS Before RAS Refresh Cycle) tCHR 10 - 10 - ns RAS Precharge to CS Hold Time tZRH 10 10 10 - ns tSIN - 10 CS Precharge Time in Normal Mode Note ns Static Column Mode Cycle Parameter HM511666-8 Symbol HM511666-1O Min Max Min Static Column Mode Cycle Time tsc 50 - 60 Static Column Mode CS Precharge Time tSI 10 - 10 Static Column Mode RAS Pulse Width tRAsc 80 RAS to Second WE Delay Time tRSWD 80 Write Invalid Time tWI 10 100000 - 100 - Unit Max Note ns ns 100000 ns 100 - ns 10 - ns 12 Counter Test Cycle Parameter CS Precharge Time in Counter Test Cycle Symbol tCPT HM511666-8 Min HM511666-1O Max - 40 Min Max 40 - Unit Note ns Byte Write Mode Parameter Symbol HM511666-8 Min HM511666-1O Max Min Max Unit Masked Write Setup Time tMCS 0 - 0 - ns Masked Write Hold Time Referenced to RAS tMRH 0 - 0 - ns Masked Write Hold Time Referenced to CS tMCH 0 - 0 - ns ~HITACHI 228 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 Note HM511666 Series Notes: 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD S tRCD (max) and tRAD :s tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to I1TL load and 50 pF. 4. Assumes that tRCD O!: tRCD (max) and (tRCD - tRAD) O!: [tRCD (max) - tRAD (max»). 5. Assumes that tRAD O!: tRAD (max) and (tRCD - tRAD) S [tRCD (max) - tRAD (max»). tRAC, tACS, and tAA are determined as follows. tRAD max. tRAC tRCD min. 0147-5 6. toFF (max) defmes the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. Vrn (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between Vrn and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRcD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tACS. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. twcs is not restrictive operating parameter. It is included in the data sheet as electrical characteristics only: if twcs O!: twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. 11. These parameters are referenced to CS leading edge in an early write cycle and to WE leading edge in a delayed write cycle. 12. tRASC defines RAS pulse width in static column mode cycles. 13. Access time is determined by the longer of tAA or tcAC' 14. An iuitial pause of 100 ,",S is required after power up followed by a minimum of eight iuitialization cycles (RAS only refresh cycle or CS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CS before RAS refresh cycles is required. 15. In delayed write cycles, OE must disable output buffer prior to applying data to the device. 16. When both LW and UW go low at the same time, all 16 bits data are written into the device. LW and UW cannot be staggered within the same write cycle. 17. tAHR defmes the time at which the column addresses hold. ~HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300 229 HM511666 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read Cycle RA5 tRP tr tSRS tRCD C5 tASR Address tRAD Column Dout------------~----~----~------------(I I/O 1-1/016 Din 0147-6 ~HITACHI 230 Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM511666 Series • Early Write Cycle Address Din 1/01-11016 Dout ____________________________ ~H~ig~h~-~Z __________________________________ ** OE : V1H or V1L 0147-7 @HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 231 HM511666 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Upper Byte Early Write Cycle Address Din 1/01-1/08 Dout-----------+-----------~----~~~-------------------------------- Din Din 1/09-1/016 Dout ____________________________ ~H~i~g~h~-Z~ ________________________________ * ~ : V1HorV 1L ** OE: V1H or V1L 0147-8 ~HITACHI 232 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM511666 Series • Lower Byte Early Write Cycle Address Din 1/01-1/08 Dout ____________________________~H~i2gh~-~z~_________________________________ Din 1/09-1/016 Dout ____________________________~H~i2g~h~-Z~_________________________________ .. 0147-9 @HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 233 HM511666 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Delayed Write Cycle tSRS tT tsp Address Din 1/01-1/016 OE • ~: V1HorVIL Invalid Dout comes out, when OE is low level. 0147-10 ~HITACHI 234 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM511666 Series • Upper Byte Delayed Write Cycle RAS tT tRCD CS tASR Address Din 1/01-1/08 Dout--------~------------_+--/ Din 1/09-1/016 Dout----------------~------~ * ~ : V1H orVIL Invalid Dout comes out. when OE is low level. 0147-11 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-t 8t 9' (415) 589-8300 235 HM511666 Series • Lower Byte Delayed Write Cycle tT Address Din 1101-1108 Dout----------------~~----~ Din 1109-11016 Dout------------------+-----~ • ~ :V1HorV 1L ** Invalid Dout comes out, when OE is low level. 0147-12 ~HITACHI 236 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM511666 Series • RAS Only Refresh Cycle Row Address 1/01-1/016 High-Z Dout * Ce. UW. LVii : VIH or VIL ** ~ :VIHorVIL *** Refresh address: AO - A7 (AXO - AX7) 0147-13 • CS Before RAS Cycle Dout VIHorVIL 0147-14 eHITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 237 HM511666 Series • Static Column Mode Read Cycle tT Address UW/LW Din tozo Dout Dout tOAe • ~ : VIH orVI~ 0147-15 ~HITACHI 238 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM511666 Series • Static Column Mode Early Write Cycle (1) High·Z** Dout--------------------------------~~~----------------------------- * ~:VIHorVIL ** twcs ii: twcs (min) *** OE : VIH orVIL 0147-16 • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589·8300 239 HM511666 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Static Column Mode Write Cycle (2) Address UW/lW Din 1101-11016 High-Z** Dout----------------------------------~---------------------------------- *~ :VIHorV1L ** twcsi1: twcs(min) *** OE : VIH or V1L 0147-17 _HITACHI 240 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HM511666 Series • Static Column Mode Upper Byte Early Write Cycle (1) tr Address UW Din High·Z*" Dout LW 1101-1/08 High·Z Dout •• twcs il: twcs (min) 0147-18 ~HITACHI Hitachi America, Ltd.· Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 241 HM511666 Series - - - - - - - - - - - - - - - - - - - - - - - - - - -_ _ __ • Static Column Mode Upper Byte Write Cycle (2) 1101-1/08 High-Z Dout * ~ : VIH orVIL ** twcs ~ twcs (min) *** OE : VIH orVIL 0147-19 • 242 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM511666 Series • Static Column Mode Lower Byte Early Write Cycle (1) tT High-Z Dout •• twcsiii: twcs (min) **. OE : VIH orVIL 0147-20 $HITACHI Hitachi America, Ltd. 0 Hitachi Plaza 0 2000 Sierra Poinl Pkwy. 0 Brisbane, CA 94005-1819 0 (415) 589-8300 243 HM511666 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Static Column Mode Lower Byte Write Cycle (2) Address LW UW Din 1109-1/016 High-Z Dout ** twcs<:twcs(min) *"* OE : V,H or V,l 0147-21 ~HITACHI 244 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM511666 Series • CS Before RAS Refresh Counter Check Cycle (Read) Column toze Din 1/01-1/016 Dout -------------------------+--------~I Dout 0147-22 ~HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 245 HM511666 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • CS Before RAS Refresh Counter Check Cycle (Write) Address 1/01·1/016 High·Z Dout--------------------------~------------------------------------ 0147-23 o 246 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HM514100A Series - - - - - - - HM514100AL Series LowPowerVersion HM514100ASL Series Super Low Power Version Preliminary 4,194,304·Word x 1·Bit Dynamic Random Access Memory HM514100AJ Series • DESCRIPTION The Hitachi HM514100A is a CMOS dynamic RAM organized 4,194,304 word x 1-bit HM514100A has realized higher density, higher performance and various functions by employing 0.8 ",m CMOS process technology and some new CMOS circuit design technologies. The HM514100A offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514100A to be packaged in standard 350 mil 20-pin plastic SOJ, standard 300 mil 20-pin plastic SOJ, standard 400 mil 20-pin plastic ZIP, 20-pin plastic TSOP I, 20-pin plastic TSOP I reverse type, 20-pin plastic TSOP II, and 20-pin plastic TSOP II reverse type. 3DCP20DA (CP-20DA) HM514100AS Series • FEATURES • Single 5V (±10%) • High Speed Access Time ............................ 60 ns/70 ns/80 ns/100 ns (max) • Low Power Dissipation Active Mode .................... 605 mW/550 mW/495 mW/440 mW (max) Standby Mode ............................................. 11 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycles ................................ (16 ms, 128 ms, 256 ms) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh • Test Function • Battery Back Up Operation HM514100AL Series (L-Version) • Data Retention Operation HM514100ASL Series (SL-Version) 3OCP20D (CP-20D) HM514100AZ Series 3DZP20 (ZP-20) HM514100AT Series • ORDERING INFORMATION Part No. HM5l4looAJ/AU/ASU-6 HM5l4looAJ/AU/ASU-7 HM5l4looAJ/AU/ASU-8 HM5l4looAJ/AU/ASU-1O Access Time 3DTFP20DA Package 60ns 70ns 80ns lOOns 350 mil20-pin Plastic SOJ (CP-20DA) HM5l4l00AS/ALS/ASLS-6 HM5l4l00AS/ALS/ASLS-7 HM5l4l00AS/ALS/ASLS-8 HM5l4looAS/ALS/ASLS-1O HM5l4l00AZ/ALZ/ASLZ-6 HM5l4l00AZ/ALZ/ASLZ-7 HM5l4l00AZ/ALZ/ASLZ-8 HM5l4l00AZ/ALZ/ASLZ-10 60ns 70ns 80ns lOOns 60ns 70ns 80ns lOOns 300 mil20-pin Plastic SOJ (CP-20D) HM5l4looAT/ALT/ASLT-6 HM5l4l00AT/ALT/ASLT-7 HM5l4looAT/ALT/ASLT-8 HM5l4looAT/ALT/ASLT-1O 60ns 70ns 80ns lOOns 2O-pin Plastic TSOP I (TFP-20DA) HM5l4looAR/ALR/ASLR-6 HM5l4looAR/ALR/ASLR-7 HM5l4looAR/ALR/ASLR-8 HM5l4looAR/ALR/ASLR-IO 60ns 70ns 80ns lOOns 20-pin Plastic TSOP I Reverse Type (TFP-20DAR) HM5l4looATT/ALTT/ASLTT-6 HM5l4looATT/ALTT/ASLTT-7 HM5l4looATT/ALTT/ASLTT-8 HM5l4l00ATT/ALTT/ASLTT-1O HM5l4looARR/ALRR/ASLRR-6 HM5l4looARR/ALRR/ASLRR-7 HM5l4looARR/ALRR/ASLRR-8 HM5l4l00ARR/ALRR/ASLRR-1O 60ns 70ns 80ns lOOns 60ns 70ns 80ns lOOns 2O-pin Plastic TSOP II (TTP-20D) 400 mil 20-pin Plastic ZIP (ZP-20) (TFP-20DA) HM514100AR Series 3DTFP200AR (TFP-20DAR) HM514100ATT Series 3DTTP20D (TTP-20D) HM514100ARR Series 2O-pin Plastic TSOP II Reverse Type (TTP-20DR) aDTIP20DR (TTP-20DR) • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 247 HM514100A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • PIN OUT HM514100AJI AUIASU Series HM514100ASIALSIASLS Series Hitachi Pin No. HM514100AT/ALZlASLT Series HM514100ATT/ALTT I ASLTT Series JEDEC Pin No. ~~t ~~o NC Vss ~~H~ 4 17 AS 16 A4 5 ~~n ~. WE 8, :~~ 1~ ~! !gc 13 A2 '-------------' ~~:~ 0091-3 (Top View) Din 1 WE 20 VSS 2 19 Dout 18 CAS RAS 3 NC 4 A10 5 17 NC 16 A9 AO 6 A1 7 A28 A3 9 VCC10 15 14 13 12 11 A8 A7 A6 AS A4 0091-5 (Top View) 0091-1 (Top View) HM514100AZIALZIASLZ HM514100ARR/ALRR I ASLRR Series HM514100ARIALR/ASLR Series Series 1 Din Vss 20 :!~ 1~ ~ WE ~ ~~:~ 13 A2 8 Din 7 NC 6 VSS NC 5 4 Dout 3 ~!S ~ 14 A3 15 VCC 0 16 A4 17 AS 0 L.__________ --J 18 A6 !~ :~ 2WE Dout19 18 He 17 A9 16 3m CAS A8 A7 A6 AS A4 4 Ne 5 A10 15 14 13 12 11 6 AO 7 A1 8 A2 9 A3 10 Vee 0091-4 (Top View) 0091-6 (Top View) 0091-2 (Bottom View) • PIN DESCRIPTION Pin Name Function Ao-AIO Address Input Ao-Ag Refresh Address Input Din Dout Data-out Data-in RAS Row Address Strobe CAS Column Address Strobe WE ReadlWrite Enable Vee Vss Power(+ SV) NC No Connection Ground $ 248 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819' (415) 589-8300 HM514100A Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on Any Pin Relative to Vss VT -1.0to +7.0 V Supply Voltage Relative to Vss VCC -1.0to +7.0 V Short Circuit Output Current lout 50 rnA 1.0 W Power Dissipation PT Operating Temperature Topr Storage Temperature Tstg oto 'c 'c + 70 - 55 to + 125 • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA (TA Parameter Symbol ~ Typ Max Unit 0 0 0 V 4.5 5.0 5.5 V I 4.0 - 5.5 V 1,2 (SL-Version) 6.5 V 1 O.S V 1 VCC Input High Voltage VIR 2.4 Input Low Voltage VIL -2.0 Notes: 0 to + 70'C) 0 to + 60'C (SL-Version)) Min VSS Supply Voltage ~ Note I. All voltage referenced to Vss. 2. Data retention operation only. • DC Characteristics (TA (TA Parameter Symbol Operating Current ICC! ~ ~ 0 to +70'C, Vee 0 to +60'C, Vee ~ ~ 5V ±10%, Vss 5V ±10%, Vss ~ ~ OV) OV (SL-Version)) HM51 .. 1OOA-6 HM5141OOA-7 Min Max Min Max HM514100A-S Min Max HM5141OOA-1O Min Max - 110 - 100 - 90 - SO rnA - 2 - 2 - 2 - 2 TTL Interface rnA RAS, CAS = VIR Dout = High-Z - 1 - 1 - I - 1 CMOS Interface rnA RAS, CAS> Vcc - 0.2V Dout = High-Z Standby Current [L-Versionl Standby Current ICC2 [SL-Versionl Standby Current - 200 - 200 - 200 - Unit Test Conditions RAS, CAS Cycling tRC = Min Note 1,2 200 CMOS Interface RAS, CAS = VIR /LA WE, Address and Din = VIROrVIL Dout = High-Z 4 4 2 - 100 - 100 - 100 - 100 CMOS Interface RAS, CAS = VIR /LA WE, Address and Din = VIROrVIL Dout = High-Z RASOnly Refresh Current ICC3 - 110 - 100 - 90 - SO rnA tRC = Min Standby Current ICC5 - 5 - 5 - 5 - 5 RAS rnA CAS Dout = VIR = VIL = Enable CAS Before RAS Refresh Current ICC6 - 110 - 100 - 90 - SO rnA tRC = Min Fast Page Mode Current ICC7 - 110 - 100 - 90 - SO rnA tpc = Min I 1,3 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 249 HM514100A Series • DC Characteristics (TA (TA Parameter = = Symbol = = 0 to +70·C, Vee 0 to +60·C, Vee SV ±10%, Vss SV ±10%, Vss HMS14100A-6 HMSI4IooA-7 Min Min [L-Versionl Battery Back Up Operatmg Current (Standby with CBR Refresh) Max - Max - 300 300 = = OV) OV (SL-Version)) (continued) HMSI4IOOA-8 Min Max - HMSI4100A-1O Min - 300 Unit Test Conditions Note p.A tRe = 12S p.s tRAS S I p.s WE = VIR, CAS = VIL Address, Din = VIR or VIL D out = High-Z 4 ISO p.A tRe = 2S0 p.s tRAS S 200ns WE = VIH, CAS = VIL Address, Din = VIR or VIL D out = High-Z 4.0V S Vee S S.SV 4 Max 300 IeelO [SL-Versionl Data Retention Current (EqUIvalent Refresh Time is 2S6 ms) - - ISO ISO - - ISO Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 p.A OV S VIN S 7V Output Leakage Current ILO -10 10 -10 10 -10 10 -10 10 p.A OV S VIN S 7V D out = Disable Output High Voltage VOH 2.4 Vee 2.4 Vee 2.4 Vee 2.4 Vee V High lout Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 mA Notes: I. 2. 3. 4. S mA Icc depends on output load condition when the device is selected, Icc max is specified at the output open condition. Address can be changed once or less while RAS = V IL. Address can be changed once or less while CAS = VIR' Vee - 0.2V S VIR S 6.SV and OV S VIL S 0.2V. • Capacitance (TA = 2S·C, Vee = sv ±10%) Parameter Notes: =- Symbol Input Capacitance (Address, Data-in) Cn Input Capacitance (Clocks) Cl2 Output Capacitance (Data-out) Co Typ Max Unit Note - S pF I 7 pF I 7 pF 1,2 I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIR to disable D ont . • AC Characteristics (TA (TA = = 0 to +70·C, Vee 0 to +60·C, Vee = = SV ±10%, Vss SV ± 10%, Vss = = OV)1, 12, 15 OV (SL-Version)) Test Conditions: Input rise and fall times: S ns Input timing reference levels: 2.4V Output load: 2 TTL Gate + CL (100 pF) (Including scope and jig) o.av, Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Random Read or Write Cycle Time Symbol HMS14100A-6 HMSI4IOOA-7 HMSI4IOOA-8 Min Max Min Min - 130 - 150 SO - 60 Max Max - HMSI4IOOA-1O Min Max 180 - Unit tRe 110 RAS Precharge Time tRP 40 RAS Pulse Width tRAS 60 10000 70 10000 80 10000 100 10000 ns CAS Pulse Width teAS IS 10000 20 10000 20 10000 25 10000 ns Row Address Setup Time tASR 0 Row Address Hold Time tRAH 10 - 0 10 - 0 10 - 70 0 IS - ~HITACHI 250 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 ns ns ns ns Note HM514100A Series Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) (continued) Parameter Symbol HM514100A-6 HM514100A-7 HM514100A-8 Min Max Min Min Max Max HM514100A-1O Min Max Unit Note Column Address Setup Time tASC 0 - 0 - 0 IS - 15 IS - 20 - ns tCAH - 0 Column Address Hold Time RAS to CAS Delay Time tRCO 20 45 20 50 20 60 25 75 ns 8 RAS to Column Address Delay Time tRAO IS 30 15 35 15 40 20 55 ns 9 RAS Hold Time tRSH IS - 20 - 20 25 tCSH 60 70 100 tCRP 10 10 - 80 CAS to RAS Precharge Time - - ns CAS Hold Time 10 - 10 - ns Transition Time (Rise and Fall) tT 3 50 3 50 3 50 3 50 ns Refresh Period tREF - 16 16 Refresh Period (L-Version) tREF 128 128 Refresh Period (SL-Version) tREF - - 16 - 16 - ns ns 16 - 16 ms 128 - 128 ms 16 ms 16 7 Read Cycle Parameter Symbol HM514100A-6 HM514100A-7 Min Min Max Access Time from Address tAA - Read Command Setup Time tRCS 0 Read Command Hold Time to CAS tRCH 0 tRRH Column Address to RAS Lead Time tRAL Output Buffer Tum-off Time tOFF 0 - 30 - 35 0 IS 0 Access Time from RAS tRAC Access Time from CAS tCAC Read Command Hold Time to RAS HM514100A-1O HM514100A-8 Min Unit Max Note Max Min Max - 80 - 100 ns 2,3,16 20 - 25 ns 3,4,14,16 40 - 3,5,14,16 60 - 70 IS - 20 30 - 35 0 0 0 - 0 - 45 ns ns 45 - 0 25 ns 0 0 - 0 - 0 - 40 - 20 0 20 0 ns ns ns 6 Write Cycle Parameter Symbol HM514100A-6 Min Max HM514100A-7 HM514100A-8 Min Max Min Max HM514100A-1O Min twcs 0 - 0 - 0 - 0 Write Command Hold Time tWCH 15 - 15 - IS - 20 Write Command Pulse Width twp 10 - 10 - 10 Write Command to RAS Lead Time tRWL 15 20 tCWL IS Data-in Setup Time tos 0 0 - 20 Write Command to CAS Lead Time 0 - Data-in Hold Time tOH 15 - IS - IS - 20 Write Command Setup Time 20 20 Max Unit Note ns 10 20 - ns 25 - ns 25 - ns 0 ns ns 11 ns 11 @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 251 HM514100A Series Read-Modify-Write Cycle Parameter Symbol HM514100A-6 HM514100A-7 HM514100A-8 Min Min Max Min Max Min Max - 175 - 210 - ns 80 - 100 - ns 10 20 - 25 ns 10 40 - 45 - ns 10 Unit Note Max Read-Modify-Write Cycle Time tRWC 130 tRWD 60 - 155 RAS to WE Delay Time CAS to WE Delay Time tCWD 15 - 20 Column Address to WE Delay Time tAWD 30 - 35 70 HM514100A-1O Unit Note Refresh Cycle Parameter Symbol HM514100A-6 HM514100A-7 HM514100A-8 Min Max Min Min Max Min 10 - 10 - 10 - 10 - ns 10 - 10 - 10 - 10 - ns - 10 - 10 - 10 - 10 - 10 - ns 10 CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR CAS Hold Time (CAS Before RAS Refresh Cycle) tcHR RAS Precharge to CAS Hold Time tRPC 10 CAS Precharge Time in Normal Mode tCPN 10 Max HM514100A-1O Max ns Fast Page Mode Cycle Symbol Parameter Fast Page Mode Cycle Time HM514100A-6 HM514100A-7 HM514100A-8 Min Min Min Max Max - 45 HM514100A-1O Max Min Max 55 - - tpc 40 Fast Page Mode CAS Precharge Time tcp 10 Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 - 100000 Access Time from CAS Precharge tACP - 35 - 40 - 45 - RAS Hold Time from CAS Precharge tRHCP 35 - 40 - 45 - 50 - 10 50 10 10 Unit Note ns ns 100000 ns 13 50 ns 3,14,16 - ns Fast Page Mode Read-Modify-Write Cycle HM514100A-8 HM514100A-1O HM514100A-6 HM514100A-7 Min Max Min Max Min Max Min Fast Page Mode Read-Modify-Write Cycle Time tpCM 60 - 75 - 85 - ns 35 - 70 CAS Precharge to WE Delay Time 45 - 50 - us Parameter Symbol tcpw 40 Max Unit Note 10 Test Mode Cycle Parameter Symbol HM514100A-6 HM514100A-7 HM514100A-8 Min Max Min Min Max - 0 - 0 10 - 10 - Test Mode WE Setup Time tws 0 Test Mode WE Hold Time tWH 10 Max HM514100A-1O Min Max Unit 0 - ns 10 - ns Note Counter Test Cycle Parameter CAS Precharge Time in Counter Test Cycle Symbol tCPT HM514100A-6 HM514100A-7 HM514100A-8 Min Max Min Max Min Max HM514100A-1O Min 40 - 40 - 40 - 40 Max - @HITACHI 252 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 Unit ns Note HM514100A Series Notes: I. AC measurements assume tT = 5 ns. 2. Assumes that tRCD S tRCD (max) and tRAD S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD ~ tRCD (max) and tRAD S tRAD (max). 5. Assumes that tRCD S tRCD (max) and tRAD ~ tRAD (max). 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIR and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. twcs, tRwD, tcwD, tAWD and tcpw are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs ~ twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ~ tRwD (min), tCWD ~ tcwD (min), tAWD ~ tAWD (min) and tcpw ~ tcpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. II. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. An initial pause of 100 /-,S is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required. 13. tRASC defines RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tACP' IS. Test mode operation specified in this data sheet is 8-bit test function controlled by control address bits-RAIO, CAIO and CAD. This test mode operation can be performed by WE and CAS before RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of eight test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. Data output pin is D out and data input pin is Din' In order to end this test mode operation, perform a RAS only refresh cycle or a CAS before RAS refresh cycle. 16. In a test mode read cycle, the value of tRAC, tAA, !cAC and tACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 253 HM514100A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read Cycle - ____________________________ {I (lOll I Uoul r~ : DOlI'l (are 0091-7 $ 254 HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300 HM514100A Series • Early Write Cycle iiAS lr Adchess WE Din Doul High-Z" ~X71 : Dun't • W~ (.III! •• tWI S <: two (min) 0091-6 ~HITACHI Hitachi America, Ltd_. Hitachi Plaza. 2000 Sierra Point Pkwy_. Brisbane, CA 94005-1819. (415) 589-8300 255 HM514100A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Delayed Write Cycle Add,e~1 Dill Duul InVillid Doul • V$,J :Don't (Me 0091-9 ~HITACHI 256 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514100A Series • Read-Modify-Write Cycle tl I\lldreis WE Dill Dout • ~ : DOll't (illl! 0091-10 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 257 HM514100A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle High·Z DOli I .. ~ : 00,,'1 care Relresh address: AO - A9 (AXO - AX9) WE: Don't care 0091-11 • CAS Before RAS Refresh Cycle RAS CAS Address Dout • EZ2I: Don't care .. @HITACHI 258 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819' (415) 589·8300 0091-12 HM514100A Series • Hidden Refresh Cycle Dout DOIII . ~J : Don't care 0091-13 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 259 HM514100A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read Cycle I\ddress Dout • ~ : 0011'\ (are 0091-14 ~HITACHI 260 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM514100A Series • Fast Page Mode Early Write Cycle Alldlc~s Ili9h-Z·· Duut - - - - - - - - - - - - - - - - - - - - " ' - - - - - - - - - - - - - - - - - - • ~ : Don't (are IWCS i': IW(S (min) 0091-15 @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 261 HM514100A Series • Fast Page Mode Delayed Write Cycle AddJ"(!ss wf t>in -~I-H-- Daut -~J-!I"-- tOFF torr Invalid Dout I > - - - - - { • ~ : OOl1't Girl! 0091-16 @HITACHI 262 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005· 1819· (415) 589·8300 HM514100A Series • Fast Page Mode Read-Modlfy-Write Cycle '--" T -4'lin) -4.------" Address liill \IOU' Oou' • ~ : Don't Cille 0091-17 $ HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589·8300 263 HM514100A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Test Mode Cycle • CORorMSolllvre"e,h ~ : DOll't (ar. Address, Din : Du,,'t (al. 0091-18 • Test Mode Set Cycle WE And CAS Before RAS Refresh ~------~ -----~ CAS WE Address Dout • f'ZZI: Don't care • 264 HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 0091-19 HM514100A Series • Test Mode Reset Cycle CAS Before RAS Refresh Cycle k---- 'tic ----.I RAS CAS WE Address Dout • ~: Don't care 0091-20 RAS Only Refresh Cycle k - - - - - ~c - - - - . I RAS CAS Address High-Z Dout • Refresh address AO~A9(AXO~AX9) •• ~: Don't care ••• WE: Don't care 0091-21 @HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 265 HM514100A Series • CAS Before RAS Refresh Counter Check Cycle (Read) RAS CAS Address WE Dout • E'22J: Don't care ~HITACHI 266 Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300 0091-22 HM514100A Series • CAS Before RAS Refresh Counter Check Cycle (Write) Address Din High-Z Dout • ~ : Don't care 0091-23 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 267 HM514400A Series HM514400AL Series Low Power Version HM514400ASL Series Super Low Power Version Preliminary 1,048,576-Word x 4-Bit Dynamic Random Access Memory HM514400AJ/ALJ/ALSJ Series • DESCRIPTION The Hitachi HM514400A is a CMOS dynamic RAM organized 1,048,576 word x 4-bit. HM514400A has realized higher density, higher performance and various functions by employing 0.8 JAm CMOS process technology and some new CMOS circuit design technologies. The HM514400A offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514400A to be packaged in standard 350 mil 20-pin plastic SOJ, standard 300 mil 20-pin plastic SOJ, standard 400 mil 20-pin plastic ZIP, 20-pin plastic TSOP I, 20-pin plastic TSOP I reverse type, 20-pin plastic TSOP II, and 20-pin plastic TSOP II reverse type. 3DCP20DA (CP-20DA) HM514400AS/ALS/ASLS Series • FEATURES • Single 5V (± 10%) • High Speed Access Time ............................ 60 ns/70 ns/80 ns/100 ns (max) • Low Power Dissipation Active Mode .................... 605 mW/550 mW/495 mW/440 mW (max) Standby Mode ............................................. 11 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycles ................................ (16 ms, 128 ms, 256 ms) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh • Test Function • Battery Backup Operation HM514400AL Series (L-Version) • Data Retention Operation HM514400ASL Series (SL-Version) HM514400AZ/ALZ/ASLZ Series 3DZP20 (ZP-20) HM514400AT/ALT/ASLT Series 3DTFP2QDA • ORDERING INFORMATION Part No. HM514400AJI AUIASLI-6 HM514400AJI ALIIASLI-7 HM514400AJI ALIIASLI-8 HM514400AJI ALIIASLI- 10 HM514400ASI ALSIASLS-6 HM5 14400ASIALSIASLS-7 HM514400ASI ALSIASLS-8 HM514400ASI ALSIASLS- 10 HM5 14400AZIALZIASLZ-6 HM514400AZIALZIASLZ-7 HM514400AZIALZIASLZ-8 HM514400AZIALZIASLZ- 10 HM514400AT/ALT/ASLT-6 HM514400AT/ALT/ASLT-7 HM514400AT/ALT/ASLT-8 HM514400ATI ALTIASLT-IO HM514400AR/ALR/ASLR-6 HM5 14400ARIALRIASLR-7 HM5 I 4400AR/ALR/ASLR-8 HM514400ARI ALRIASLR-IO HM514400ATTIALTTI ASLTT-6 HM514400ATT/ALTT/ASLTT-7 HM514400ATT I ALTTlASLTT-8 HM514400ATT/ALTT/ASLTT-IO HM514400ARR/ALRRIASLRR-6 HM514400ARRIALRR/ASLRR-7 HM514400ARRIALRR/ASLRR-8 HM514400ARRIALRR/ASLRR-IO 3DCP20D (CP-20D) (TFP-20DA) Access Time 60ns 70ns 80ns lOOns 60ns 70ns 80 ns lOOns 60ns 70ns 80ns lOOns 60ns 70ns 80ns lOOns 60ns 70 ns 80 ns 100 ns 60ns 70ns 80ns lOOns 60ns 70ns 80ns lOOns Package HM514400AR/ALR/ASLR Series 350 mil 20-pin Plastic SOJ (CP-20DA) 300 mil 20-pin Plastic SOJ (CP-20D) 400 mil 20-pin Plastic ZIP (ZP-20) SDTFP20DAR (TFP-20DAR) HM514400ATT/ ALTT/ ASLTT Series 20-pin Plastic TSOP I (TFP-20DA) 20-pin Plastic TSOPI Reverse Type (TFP-20DAR) 20-pin Plastic TSOP II (TTP-20D) 20-pin Plastic TSOPII Reverse Type (TTP-20DR) 30TIP20D (TTP-20D) HM514400ARR/ALRR/ASLRR Series 3DTTP20DR (TTP-20DR) ~HITACHI 268 Hitachi America, Ltd_ • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM514400A Series • PIN OUT HM514400AJ/AU/ASU Series HM514400CAS/ALS/ASLS Series HM514400AZ/ALZ/ASLZ Series Hitachi Pin No. JEDEC Pin No. OE CAs" IIOJ 1/04 V.. 1/01 1/0.2 WE iiAs At AI AI Al Vee A4 M A6 A7 A, 0090-' 0090-1 (Bottom View) (Top View) HM514400AT/ALT/ASLT Series HM514400ARIALRIASLR Series ~1~~ Wi ~ g:~ 8 13A2 1/02 7 1/01 6 14 .3 15 Vee 0 Vss 5 1/04 4 16 A4 17 AS ~3~O OE 1 L..:._ _ _ _ _ _ _----> ~:~ 20 A8 0090-4 0090-3 (Top View) (Top View) HM514400ATT/ALTT/ASLTT Series HM514400ARR/ALRR/ASLRR Series 1/011 20 Vss !L02 2 WE 3 4 19 1/04 18 ill3 17 CAS 16 Oi m .. AO ., A2 S 6 7 8 Vss 20 1/04 19 ill3 18 DE 15 A8 14 A7 13 66 .3 • . 12 AS " VcclO 1 1/01 2. YOl 3WE 2!S17 4 iii 16 5 •• AS 107 15 14 A6 AS 13 12 • •0 7 Al 8 A2 A4 " • A3 10 Vee 0090-6 0000-5 (Top View) (Top View) • PIN DESCRIPTION Function Pin Name Ao- A9 Ao- A9 Address Input Refresh Address Input I/OI-I/0 4 Data-inlData-out RAS Row Address Strobe CAS Column Address Strobe WE ReadlWrite Enable OE Output Enable Vee Vss Ground Power ( + SV) • HITACHI Hitachi America, Ltd. - Hitachi Plaza- 2000 Sierra Point Pkwy. - Brisbane, CA 94005-1819 - (415) 589-8300 269 HM514400A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Voltage on Any Pin Relative to Vss Parameter VT -1.0to +7.0 V Supply Voltage Relative to Vss Vee -1.0to + 7.0 V Short Circuit Output Current Iont PT 50 mA Power Dissipation Operating Temperature Topr Tstg Storage Temperature 1.0 W Oto+70 ·C - 55 to + 125 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (fA = 0 to + 70·C) (fA = 0 to +60·C (SL-Version) Parameter Symbol Min Typ Max Unit 0 0 0 V 4.5 5.0 5.5 V I 4.0 - 5.5 V 1, 2 (SL-Version) 6.5 V I - O.S V I O.S V I Vss Supply Voltage VCC Input High Voltage Input Low Voltage Notes: I I (1/0 Pin) (Others) VIH 2.4 VIL -1.0 VIL -2.0 Note 1. All voltage referenced to Vss. 2. Data retention operation only. + 70"C, Vee = 5V ± 10%, Vss = OV) = 0 to +60"C, Vee = 5V ±10%, VSS = OV (SL-Version) • DC Electrical Characteristics (TA = 0 to (fA Parameter Symbol Operating Current ICCI HM514400A-6 HM514400A-7 HM514400A-S HM514400A-1O Min Max Min Max Min Max Min Max - 110 - 100 - 90 - 80 - 2 - 2 - 2 - 2 - I - 1 - 1 - I Standby Current [L-Version] Standby Current ICC2 - 200 - - 200 200 - Unit rnA Test Conditions RAS, CAS Cycling tRC = Min 200 CMOS Interface RAS, CAS = VIR, p.A WE, OB, Address and Din = VIR or VII., Dont = High-Z 4 4 2 - 100 - 100 - 100 - 100 CMOS Interface RAS, CAS = VIR, p.A WE, OE, Address and Din = VIR or VII., Dont = High-Z RAS Only Refresh ICC3 Current - 110 - 100 - 90 - SO rnA tRC = Min $ 1,2 TTL Interface mA RAS, CAS = VIR, Dont = High-Z CMOS Interface RAS, rnA RAS, CAS ~ Vee - 0.2V, Dont = High-Z [SL-Veesionl Standby Current 270 Note HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514400A Series • DC Electrical Characteristics (continued) (TA = 0 to + 70"C, Vee = 5V ± 10%, Vss (TA = 0 to + 60"C, Vee = 5V ± 10%, Vss Parameter Symbol HM514400A-6 HM514400A-7 Min Max Min Max HM514400A-8 = = HM514400A-IO Min Max Min Max OV) OV (SL-Version) Unit Test Conditions Standby Current lees - 5 - 5 - 5 - 5 rnA CAS Dout = VIR, = VII.. = Enable CAS Before RAS Refresh Current IcC6 - 110 - 100 - 90 - 80 rnA tRC = Min Fast Page Mode Current ICC7 - 110 - 100 - 90 - 80 rnA tpc IL-Versionl Battery Backup Operating Current (Standby with CBR Refresh) ICCIO - 300 - 300 - 300 - 300 ISL-Versionl Data Retention Current (Equivalent Refresh Time is 256 ms) IccIO - 150 - 150 - 150 - 150 Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 Output Leakage Current IW -10 10 -10 10 -10 10 -10 10 2.4 VCC 0.4 2.4 Vee 0.4 2.4 Vee 0.4 2.4 Vee 0.4 Output High Voltage VOR Output Low Voltage VOL Notes: 1. 2. 3. 4. 0 0 RAS 0 0 Note I 1,3 = Min tRC = 125,..s, !BASS I,..s,_ WE = VIR, CAS = VIL, ,..A OE, Address and Din = VIR or VIL, Dout = High-Z tRC = 250,..s, tRAS S 200~ WE = VIH, CAS = VIL, ,..A OE, Address and Din = VIRorVIL, Dout = High-Z, 4.0V S VCC S 5.5V 4 ,..A OV S Vm S 7V OV:S Vout :S ·IV, ,..A D out = Disable V High Iaut = - 5 rnA V Low lout = 4.2 rnA Icc depends on output load condition when the device is selected, ICC max is specified at the output open condition. Address can be changed once or less while RAS = VIL. Address can be changed once or less while CAS = VIH. Vee - 0.2V S Vrn :S 6.5V and OV S VIL S 0.2V. • Capacitance (TA = 25°C, Vee = 5V ±10%) Symbol Typ Max Unit Note Input Capacitance (Address) Cn - 5 pF I Input Capacitance (Clocks) CI2 - 7 pF I 10 pF 1,2 Parameter CliO 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. Output Capacitance (Data-in, Data-out) Notes: 4 • HITACHI Hitachi AmeriCa, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 271 HM514400A Series • AC Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss = 0V)1, 14, 15. 16 (TA = 0 to 60'C, Vee = 5V ± 10%, Vss = OV (SL-Version» Read, Write, Read-Modify-Wrlte and Refresh Cycles (Common Parameters) Parameter Symbol HM514400A-7 HM514400A-8 HM514400A-1O Min Max Min Max Min Max Min - 130 - 150 - 180 HM514400A-6 Unit Note Max - ns Random Read or Write Cycle Time tRC 110 RAS Precharge Time tRP 40 RAS Pulse Width tRAS 60 10000 70 10000 80 10000 100 10000 ns CAS Pulse Width tCAS 15 10000 20 10000 20 10000 25 10000 ns Row Address Setup Time tASR 0 - 0 Row Address Hold Time tRAH 10 - 10 Column Address Setup Time tASC 0 0 tCAH 15 - 15 - tRCD RAS to Column Address Delay Time tRAD RAS Hold Time tRSH 20 45 20 15 30 15 CAS Hold Time tCSH 60 CAS to RAS Precharge Time tCRP 10 OE to Din Delay Time tODD 15 Column Address Hold Time RAS to CAS Delay Time 50 60 70 ns ns 20 - 60 25 75 ns 8 15 40 20 55 ns 9 - 20 25 - ns 70 - 80 100 - ns 10 - 10 10 20 0 - 0 0 - 0 - 0 - ns 20 - 3 50 3 50 ns 15 - 50 20 15 35 20 0 10 0 0 15 0 ns ns ns tDZO 0 CAS Setup Time from Din tDZC 0 - Transition Time (Rise and Fall) tT 3 50 3 50 Refresh Period tREF - 16 - 16 - 16 - 16 ms Refresh Period (L-Version) tREF - 128 - 128 - 128 - 128 ms Refresh Period (SL-Version) tREF - 16 - 16 - 16 - 16 ms OE Delay Time from Din 0 25 ns ns ns 7 Read Cycle Parameter Symbol HM514400A-6 HM514400A-7 HM514400A-8 Min Max Min Max Min 60 - 70 - 0 Access Time from RAS tRAC Access Time from CAS !cAC Access Time from Address tAA Access Time from OE tOAC - Read Command Setup Time tRCS 0 Read Command Hold Time to CAS tRCH Read Command Hold Time to RAS tRRH 0 Column Address to RAS Lead Time tRAL Output Buffer Tnrn-offTime toFFI Output Buffer Turn-offtu OE toFF2 CAS to Din Delay Time tCDD 15 30 15 20 35 20 HM514400A-1O Unit Note 100 ns 2,3,17 25 ns 3,4,13,17 45 ns 3,5,13,17 25 ns - ns Max Min Max 80 0 0 - 40 - 55 20 40 20 30 35 - 0 15 0 20 0 20 0 25 ns 6 0 15 0 20 0 20 0 25 ns 6 15 - 20 - 20 - 25 - ns 0 0 0 0 0 0 0 .HITACHI 272 3,17 - Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 ns 18 ns 18 ns HM514400A Series Write Cycle Parameter Symbol HM5144ooA-6 HM514400A-7 HM5144ooA-8 HM514400A-1O Min Min Min Min Max Max Max Max Unit Note Write Command Setup Time twcs 0 - 0 - 0 - 0 - ns Write Command Hold Time tWCH 15 - 15 - 15 - 20 ns Write Command Pulse Width twp 25 - 0 - ns 11 20 - ns II 10 - 10 - 10 - 20 Write Command to RAS Lead Time tRWL Write Command to CAS Lead Time tcwL 15 - 20 - 20 25 15 20 tDS 0 Data-in Hold Time tDH 15 - 20 Data-in Setup Time - - 0 15 0 15 10 ns ns ns Read-Modify-Write Cycle Parameter Read-Modify-Write Cycle Time Symbol HM514400A-6 HM514400A-7 HM5144ooA-8 HM514400A-1O Min Max Min Min Max Min 180 200 - 245 - ns 105 135 - ns 45 - 45 - 60 - ns 10 ns 10 Max tRwC 150 RAS to WE Delay Time tRWD 80 CAS to WE Delay Time tCWD 35 - Column Address to WE Delay Time tAWD OE Hold Time from WE tOEH 50 - 60 - 65 - 80 15 - 20 - 20 - 25 95 Max Unit Note 10 ns Refresh Cycle Parameter Symbol HM5144ooA-6 HM5144ooA-7 HM5144ooA-8 HM5144ooA-1O Min Max Min Max Min Max Min Max Unit Note CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 10 - 10 - 10 - 10 - ns RAS Precharge to CAS Hold Time tRPC CAS Precharge Time in Normal Mode tCPN 10 - 10 - 10 - 10 - 10 10 10 - 10 - ns ns Fast Page Mode Cycle Parameter Symbol HM514400A-6 HM514400A-7 HM5144ooA-8 HM514400A-1O Min Min Min Max Min Max Max Max Unit tpc 40 - 45 - 50 - 55 - ns Fast Page Mode CAS Precharge Time tcp 10 - 10 - 10 - 10 - ns Fast Page Mode RAS Pulse Width tRASC Access Time from CAS Precharge tACP - Fast Page Mode Cycle Time RAS Hold Time from CAS Precharge tRHCP Fast Page Mode ReadModify-Write Cycle tcpw CAS Precharge to WE Delay Time Fast Page Mode Read-ModifyWrite Cycle Time tpCM 35 - 40 - 35 - 40 - 45 - 50 - ns 55 - 65 - 70 - 85 - ns 80 - 95 - 100 - 110 - ns 100000 100000 ns Note 100000 - 100000 45 - 50 ns 3,13,17 12 ~HITACHI Hitachi America, Ltd,· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-t 819· (415) 589-8300 273 HM514400A Series Test Mode Cycle HM514400A-6 HM514400A-7 HM514400A-8 HM514400A-1O Min Max Min Min Min tws 0 Test Mode WE Hold Time tWH 10 - 10 Parameter Test Mode WE Setup time Symbol Max - 0 Max - 0 10 Max Unit Note 0 - ns 10 - ns Counter Test Cycle Parameter Symbol CAS Precharge Time in Counter Test Cycle Notes: tCPT HM514400A-6 HM514400A-7 HM514400A-8 HM5l4400A-1O Min Max Min Max Min Min Max 40 - 40 - 40 50 - Max - Note ns 1. AC measurements assume tT = 5 ns. 2. Assnmes that tRCD S tRCD (max) and tRAD S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD @" Row lOA" Column! -,- T 1/ 1\ " fCAH ..... W///b I WI Cmumn2 1 ICWL IAWO tAWO i W// / / ,J,.J,.-,r-r...,...., ~///?( I~CW.2 tAWO lRAO ICRP~ ColumnN ~ IAWO~_ ~ ICWOI--.lf---l..~ Din Dout Dout ! I IACP OoUl2 ])-----<1 OoUlN I'---.J'T '\o~ WM :Don't care 0063-14 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 325 HM514100L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Test Mode Cycle *3 set cycle Reset Cycle *1*3 Test mode cycle *1 *2 Normal mode CBR or RAS only refresh FZ?Z;l : Don' care *3 Address, Din: Don' care 0063-15 • Test Mode Set Cycle (1) Address Dout 2//////////////////////////////1//////////Ih OPEN Note"1 rzzza : Don' care 0063-16 ~HITACHI 326 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514100L Series • Test Mode Reset Cycle (2) Address Wff/l//$l////$ff/////$d//$/////////4 OPEN Dout Note *1 I'ZZZ/I : Don't care 0063-17 • RAS Only Refresh Cycle Address OPEN Dout Note *1 Refresh Address AO-A9 (AXO-AX9) *2 rzzz;I : Don't care 0063-18 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 327 HM514100L Series • CAS Before RAS Refresh Counter Check Cycle (READ) Ai Din Dout Dout Hi-Z *1 ~: Don' care 0063-19 • CAS Before RAS Refresh Counter Check Cycle (WRITE) Ai Din OPEN Dout *1 WM :Don' care 0063-20 .HITACHI 328 Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM514101 Series 4,194,304-Word x 1-Bit Dynamic Random Access Memory • DESCRIPTION HM51410lJP Series The Hitachi HM514101 is a CMOS dynamic RAM organized 4,194,304 word x 1-bit. HM514101 has realized higher denSity, higher performance and various functions by employing 0.8 ,.,.m CMOS process technology and some new CMOS circuit design technologies. The HM514101 offers Nibble Mode as a high speed access mode. Multiplexed address input permits the HM514101 to be packaged in standard 20-pin plastic SOJ and 20-pin plastic ZIP. 3DCP20DA (CP-20DA) • FEATURES HM514101ZP Series • Single 5V (± 10%) • High Speed Access Time ................................. 80 ns/100 ns/120 ns (max) • Low Power Dissipation Active Mode ............................ 495 mW/440 mW/385 mW (max) Standby Mode ............................................. 11 mW (max) • Nibble Mode Capability • 1,024 Refresh Cycles ................................................ (16 ms) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh • Test Function 3DZP20 (ZP-20) • PIN OUT HM514101JP Series • ORDERING INFORMATION Part No. Access Time Package HM5l4l0lJP-8 HM5l4l0lJP-1O HM5l41OlJP-12 80ns lOOns l20ns 350 mil 20-pin PIasticSOJ (CP-20DA) HM5l41OlZP-8 HM5l41OlZP-1O HM5l4l0lZP-12 80ns lOOns l20ns 400 mil20-pin Plastic ZIP (ZP-20) RAS Function 19 Doul 18 CAs 17 NC 16 A9 3 NC 4 A10 5 6 15 AS Al 7 14 A7 Ao • PIN DESCRIPTION Pin Name Din WE A2 8 13 A6 Ao-AIO Address Input A3 9 12 A5 Vee 10 '"IC==:5,tJ 11 A4 Ao-A9 Refresh Address Input Dm Data-in Dout RAS Data-out CAS Column Address Strobe 1M WE ReadIWrite Enable 3 Doul 0066-1 (Top View) HM514101ZP Series Row Address Strobe Vee Power ( + 5V) VSS Ground Vss 4 We 6 A10 8 NC 10 Al 12 A3 14 5 Din 7 RAS 9 NC 11 Ao 13 A2 15VCC 17 A5 19A7 0066-2 (Bottom View) @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 329 HM514101 Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on Any Pin Relative to Vss VT -1.0to +7.0 V Supply Voltage Relative to Vss Vee -1.0to + 7.0 V Short Circuit Output Current lout 50 rnA Power Dissipation PT 1.0 W Operating Temperature Topr Oto + 70 'C Storage Temperature Tstg - 55 to + 125 'C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter = Symbol 0 to + 70'C) Min Typ Max Unit Note Supply Voltage VCC 4.5 5.0 5.5 V I Input High Voltage VIH 2.4 6.5 V I Input Low Voltage VIL -2.0 - O.S V I Note: 1. All voltage referenced to Vss. • DC Electrical Characteristics (TA Parameter Symbol Operating Current Icc! Standby Current = 0 to +70'C, Vee = 5V ±10%, Vss = OV) HM514101-S HM514101-1O HM514101-12 Min Min Max Min Max Max Unit Test Conditions Note 1,2 - 90 - SO - 70 rnA RAS, CAS Cycling tRc = Min - 2 - 2 - 2 rnA TIL Interface RAS, CAS = VIH, Dout = High-Z - I - I - I rnA CMOS Interface RAS, CAS ~ Vee - 0.2V, D out = High-Z - 90 - SO - 70 rnA tRC ICC2 RAS Oniy Refresh Current ICC3 = Min = VIH, = VII" = Enable Standby Current Iccs - 5 - 5 - 5 rnA RAS CAS D out CAS Before RAS Refresh Current ICC6 - 90 - 80 - 70 rnA tRC = Min - SO 2 I = Min Nibble Mode Current Iccs rnA tNC 10 -10 10 -10 70 ILl -10 90 Input Leakage Current 10 /LA OV:s Vin:S 7V Output Leakage Current ILO -10 10 -10 10 -10 10 /LA OV :S Vout :S 7V, D out = Disable Output High Voltage VOH 2.4 Vcc 2.4 Vee 2.4 Vee V High lout Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 rnA Notes: = 25'C, Vee = 5V ±10%) Parameter Symbol Typ Max Unit Note 5 pF I CI2 - 7) pF I Co - 7 pF 1,2 Input Capacitance (Address, Data-in) Cn Input Capacitance (Clocks) Output Capacitance (Data-out) 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out. .HITACHI 330 5 rnA 1. IcC depends on output load condition when the device is selected, lee max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL' 3. Address can be changed once or less while CAS = VIH. • Capacitance (TA Notes: =- 1,3 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HM514101 Series • AC Characteristics (TA = 0 to +70'C, vee = 5V ±10%, vss = OV)1, 12, 13 Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Symbol HM514101-8 HM514101-1O HM514101-12 Unit Min Max Min Max Min - 180 - 210 - ns 80 - ns Max Random Read or Write Cycle Time tRC 150 RAS Precharge Time tRP 60 RAS Pulse Width tRAS 80 10000 100 10000 120 10000 ns CAS Pulse Width tCAS 25 10000 25 10000 30 10000 ns Row Address Setup Time tASR 0 Row Address Hold Time tRAH 12 Column Address Setup Time tASC 0 Column Address Hold Time tCAH RAS to CAS Delay Time 15 - tRCD 22 RAS Hold Time tRsH 25 70 20 - 55 25 - 25 0 15 0 ns 25 - 75 25 90 ns - 30 - ns 0 15 0 ns ns ns RAS to Column Address Delay Time tRAD 17 40 20 55 20 65 ns CAS Hold Time tCSH 80 100 - 120 - ns CAS to RAS Precharge Time tCRP 5 - 10 - 10 - ns tT 3 50 3 50 3 50 ns tREF - 16 16 ms Transition Time (Rise and Fall) Refresh Period - - 16 Note 8 9 7 Read Cycle Parameter Symbol HM514101-8 Min Max 25 tAA - Read Command Setup Time tRCS 0 Read Command Hold Time to CAS tRCH 0 Read Command Hold Time to RAS tRRH 10 Column Address to RAS Lead Time tRAL Output Buffer Turn-off Time tOFF Access Time from RAS tRAC Access Time from CAS !cAC Access Time from Address 80 40 HM514101-1O HM514101-12 Min Max Min - 100 - 25 - 45 0 40 - 45 - 0 20 0 25 0 10 Unit Note 120 ns 2,3,14 30 ns 3,4 - 55 ns 3,5,14 0 - ns 0 10 - ns 55 - ns 0 30 ns Max ns 6 Write Cycle Parameter Symbol HM514101-8 Min Max HM514101-1O HM514101-12 Min Min Max Max Unit Note ns 10 20 - Write Command Setup Time twcs 0 - 0 - 0 Write Command Hold Time tWCH 15 20 twp 15 Write Command to RAS Lead Time tRWL 25 30 - ns Write Command to CAS Lead Time tCWL 25 - 25 - 25 Write Command Pulse Width - 30 ns Data-in Setup Time tDS 0 - 0 - 0 Data-in Hold Time tDH 15 - 20 - 25 - 20 25 ns ns ns 11 ns 11 Unit Note Read-Modify-Write Cycle Parameter Symbol HM514101-8 Min Read-Modify-Write Cycle Time tRWC 180 RAS to WE Delay Time tRWD 80 CAS to WE Delay Time !cWD 25 Column Address to WE Delay Time tAWD 40 Max - HM514101-1O HM514101-12 Min Max Min Max 210 - 245 - ns 120 ns 10 30 - ns 10 55 - ns 10 100 25 45 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 331 HM514101 Series Refresh Cycle Parameter HM514101-1O HM514!01-12 Min Max Min Min Max HM514101-8 Symbol Max Unit CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 20 - 20 - 25 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - ns Note Nibble Mode Cycle Parameter HM514101-1O HM514101-12 Min Max Min HM514101-8 Symbol Min Max Max Unit Nibble Mode Access Time tNAC - 25 - 25 - 30 ns Nibble Mode Cycle Time tNC 45 - 45 55 - ns Nibble Mode CAS Precharge Time tNCP 10 - 10 - 15 - ns Nibble Mode CAS Pulse Width tNCA 25 - 25 - 30 - ns Nibble Mode RAS Hold Time tNRSH 25 - 25 - 30 - ns Note Nibble Mode Read-Modify-Write Cycle HM514101-1O HM514101-12 Min Min Max - 90 - ns 25 - 30 - ns 25 - 30 - ns HM514101-8 Parameter Symbol Nibble Mode Read-Modify-Write Cycle Time tNRWC 75 - 75 Nibble Mode Write Command to CAS Lead Time tNCWL 25 - Nibble Mode CAS to WE Delay Time tNCWD 25 - Min Max Max Unit Note Test Mode Cycle Parameter Test Mode WE Setup Time Test Mode WE Hold Time Symbol HM514101-8 Min Max HM5141Ol-1O HM514101-12 Unit Min Max Min Max - 0 - ns 20 - ns tws 0 - 0 tWH 20 - 20 Note Counter Test Cycle Parameter CAS Precharge Time in Counter Test Cycle Notes: Symbol tCPT HM5141Ol-8 HM514101-1O HM514101-12 Min Max Min Max Min 40 - 50 - 60 Max - Unit ns I. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :S tRCD (max) and tRAD :S tRAD (max). If tRCD or tRAD is greater than the maximum recommended vaIue shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD l!: tRCD (max) and tRAD :S tRAD (max). 5. Assumes that tReD :S tRCD (max) and tRAD l!: tRAD (max). 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and V IL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRCD (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' ~HITACHI 332 Note Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 HM514101 Series 10. twcs, tRWD, tCWD and tAwD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs 2: twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; iftRwD 2: tRWD (min), tCWD 2: tCWD (min) and tAwD 2: tAWD (min), the cycle is a read-modify-write lind the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. II. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. An initial pause of 100 )Jos is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required. 13. Test mode operation specified in this data sheet is 8-bit test function controlled by control address bits-RAIO, CAIO and CAO. This test mode operation can be performed by WE and CAS before RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of eight test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. Data output pin is DOUI and data input pin is Din. In order to end this test mode operation, perform a RAS only refresh cycle or a CAS before RAS refresh cycle. 14. In a test mode read cycle, the value of tRAe. tAA, tCAC and tNAC is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. • TIMING WAVEFORMS • Read Cycle (1) tAC tRAS RSH tACO tCSH teRP Address WE Dout WM :Don't care 0066-3 $ HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 333 HM514101 Series - - - - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ __ • Early Write Cycle (2) Address Din Dout • ~ : Don't care •• twcs;;:twcs (min) 0068-5 • Delayed Write Cycle (3) Address Din • ~ : Don't care • 334 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514101 Series • Read-Modify-Write Cycle (4) RAS Address Din Dout Dout . WM :Don't care 0066-7 • RAS Only Refresh Cycle (5) tAC tRAS tASR Address tRAH Row Dout . WM : Don't ear• •• REFRESH ADDRESS: AO-A9 (AXO-AX9) 0066-6 • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005· 1819 • (415) 589·8300 335 HM514101 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Hidden Refresh Cycle (6) Address Dout YaRd Data "1 WM :Don't care 0066-9 • CAS Before RAS Refresh Cycle (7) tRe Address OPEN Dout . WM:Don,care WE :VIH 0066-10 • 336 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514101 Series • Nibble Mode Read Cycle (8) Address Dout .~: Don't ear. 0066-11 • Nibble Mode Early Write Cycle (9) Address Din Dout Open" ~ : Don'lcare twcs ::r twcs (min) 0066-12 _HITACHI Hitachi America, Ltd,. Hitachi Plaza. 2000 Sierra Point Pkwy,. Brisbane, CA 94005-1819. (415) 589-8300 337 HM514101 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Nibble Mode Delayed Write Cycle (10) Address Din . WM :Don' care 0066-13 _HITACHI 338 Hitachi America, Ltd. 0Hitachi Plaza 02000 Sierra Point Pkwy. 0Brisbane, CA 94005-1819 0(415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514101 Series • Nibble Mode Read-Modify-Wrlte Cycle (11) Address Din · WM :Don't care 0066-14 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 339 HM514101 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Test Mode Cycle *3 set cycle Reset Cycle *1 *3 Test mode cycle Normal mode "1 CBR or RAS only refresh "2 rzzz;I : Don' care "3 Address, Din: Don' care 0066-16 Test Mode Set Cycle (1) Address 1///////////////////////////1////////////////, OPEN Dout Note *1 rzzz;t : Don' care 0066-16 • 340 HITACHI Hitachi America, Ltd. * Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HMS14101 Series • Test Mode Reset Cycle (2) CAS Before RAS Refresh Cycle Address W/ff/ff/ff/ff/////$//ff/ff/////$////# /& OPEN Dout Note01 rzm : Don' care 0066-17 RAS Only Refresh Cycle Address OPEN Dout Note °1 Refresh Address AO .. A9 (AXO"AX9) : Don' care 0066-18 • HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 341 HM514101 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • CAS Before RAS Refresh Counter Check Cycle (READ) Ai Din tOFF Dout Doul HI-Z *1 127M :Don' care 0066-19 • CAS Before RAS Refresh Counter Check Cycle (WRITE) Ai WE Din OPEN Dout ·1 E(/~ : Don't care 0066-20 ~HITACHI 342 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM514101A Series Preliminary 4,194,304·Word x 1·Bit Dynamic Random Access Memory • DESCRIPTION HM514101AJ Series The Hitachi HM514101A is a CMOS dynamic RAM organized as 4,194,304,word x 1·bit. HM514101A has realized higher density, higher performance and various functions by employing 0.8 /Lm CMOS process technology and some new CMOS circuit design technologies. The HM514101A offers Nibble Mode as a high speed access mode. Multiplexed address input permits the HM514101A to be packaged in standard 20·pin plastiC SOJ and 20·pin plastic ZIP. 3DCP20DA (CP·20DA) • FEATURES HM514101AS Series • Single 5V (±10%) • High Speed Access Time .................................. 70 ns/80 ns/100 ns (max) • Low Power Dissipation Active Mode ............................ 550 mW / 495 mW / 440 mW (max) Standby Mode ............................................. 11 mW (max) • Nibble Mode Capability • 1,024 Refresh Cycles ................................................ (16 ms) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh • Test Function 3DCP20D (CP·20D) HM514101AZ Series 3DZP20 (ZP·20) • ORDERING INFORMATION • PIN OUT Part No. Access Time Package HM514101AJ·7 HM514101AJ·S HM5l41OIAJ·1O 70ns SOns lOOns 350 mil 20·pin Plastic SOJ (CP·20DA) HM514101AS·7 HM514101AS·S HM514101AS·1O 70ns SOns lOOns 300 mil 20·pin Plastic SPJ (CP·20D) HM514101AZ·7 HM514101AZ·S HM514101AZ·1O 70ns SOns lOOns 400 mil20·pin Plastic ZIP (ZP·20) HM514101AJ/AS Series HM514101AZ Series A9 CAS Vss WE 5 D;n 7 RAS 9 HC Al0 HC 11 AO A1 13 A2 A3 • PIN DESCRIPTION Pin Name 15 Vee A4 17 A5 AS Function Ao-AIO Address Input AO-A9 Refresh Address Input Dm Data·in DOllt RAS Data·out CAS Column Address Strobe WE ReadIWrite Enable 19 A7 AS 0148-1 (Top View) 0148-2 (Bottom View) Row Address Strobe Vee Power (+ 5V) VSS Ground ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 343 HM514101A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Voltage on Any Pin Relative to Vss VT -1.0to Supply Voltage Relative to Vss Vcc -1.0to Short Circuit Output Current lout 50 Power Dissipation PT Operating Temperature Topr Tstg Storage Temperature Note: V V rnA 1.0 W + 70 55 to + 125 ·C Oto - • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter Unit + 7.0 + 7.0 = 0 to ·C + 70·C) Symbol Min Typ Max Unit Note Supply Voltage VCC 4.5 5.0 5.5 V 1 Input High Voltage VIR 2.4 6.5 V 1 Input Low Voltage VIL -2.0 - O.S V 1 I. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to + 70·C, Vee = 5V ± 10%, Vss = OV) Parameter Operating Current Standby Current Symbol ICC! HM514101A-7 HM514101A-S Min Max Min Max Min Max - 100 - 90 - - 2 - 2 - I - - 100 - HM514101A-1O Unit Test Conditions Note SO mA RAS, CAS Cycling tRC = Min 1,2 - 2 mA TTL Interface RAS, CAS = VIR, Dout = High-Z 1 - 1 mA CMOS Interface, RAS, CAS ~ Vcc - 0.2V, Dout = High-Z 90 - SO mA tRC IeC2 RAS Only Refresh Current ICC3 Standby Current ICC5 - 5 - 5 - 5 mA RAS CAS Dout CAS Before RAS Refresh Current ICC6 - 100 - 90 - SO rnA tRC Nibble Mode Current ICCS - 100 - 90 - = Min = VIR, = VIL, = Enable SO rnA = Min tNC = Min ILl -10 10 -10 10 -10 10 p.A OV ILO -10 10 -10 10 -10 10 p.A OV :$ Vout :$ 7V Dout = Disable Output High Voltage VOH 2.4 VCC 0.4 V High lout 0 VCC 0.4 2.4 VOL VCC 0.4 2.4 Output Low Voltage V Low lout Input Leakage Current Output Leakage Current Notes: 0 0 :$ Vin :$ 1 1,3 7V = - 5 mA = 4.2 mA I. ICC depends on output load condition when the device is selected. Icc max is specified at the output open condition. 2. Address can be changed :$ 1 time while RAS = VIL. 3. Address can be changed :$ 1 time while CAS = VIR' @HITACHI 344 2 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM514101A Series • Capacitance (TA = 25·C, Vee = 5V ±10%) Parameter Notes: Symbol Typ Max Unit Note Input Capacitance (Address, Data-in) Cn - 5 pF I Input Capacitance (Clocks) CI2 7 pF I Output Capacitance (Data-out) Co - 7 pF 1,2 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out ' • AC Characteristics (TA = 0 to + 70·C, Vee = 5V ± 10%, Vss = OV)1, 12, 13 Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Symbol HM514101A-7 HM514101A-8 HM514101A-1O Unit Min Max Min Max Min Max - 180 - ns 70 - ns Random Read or Write Cycle Time tRC 130 tRP 50 - 150 RAS Precharge Time RAS Pulse Width tRAs 70 10000 80 10000 100 10000 CAS Pulse Width tCAS 20 10000 20 10000 25 10000 Row Address Setup Time tASR 0 Row Address Hold Time tRAH 10 Column Address Setup Time tASC 0 Column Address Hold Time tCAH RAS to CAS Delay Time 60 - 10 - 15 ns ns 0 - 0 15 - - 15 20 - ns tRCD 20 50 20 25 75 ns RAS Hold Time tRSH 20 - 20 60 - 25 - ns RAS to Column Address Delay Time 0 0 ns ns ns tRAD 15 35 15 40 20 55 ns CAS Hold Time tCSH 70 - 80 100 tcRP 10 - 10 10 - ns CAS to RAS Precharge Time - Transition Time (Rise and Fall) tT 3 50 3 50 3 50 ns Refresh Period tREF - 16 - 16 16 ms - Note 8 9 ns 7 Read Cycle Parameter Symbol HM514101A-7 Min Max HM514101A-8 Min Max HM514101A-1O Min Max Unit Note 2,3,14 70 - 80 - 100 ns 20 - 20 - 25 ns 3,4 tAA - 40 - 45 ns 3,5,14 Read Command Setup Time IRcs 0 Read Command Hold Time to CAS tRcH 0 Read Command Hold Time to RAS tRRH 0 Column Address to RAS Lead Time tRAL 35 - Output Buffer Tum-off Time toFF 0 20 Access Time from RAS tRAC Access Time from CAS tCAC Access Time from Address 35 $ 40 - 0 20 0 0 0 0 - ns 0 - ns 0 ns 45 - 0 25 ns ns 6 HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 345 HM514101A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Cycle Parameter Symbol HM514101A-7 Min Max twcs 0 Write Command Pulse Width tWCH twp 15 10 Write Command to RAS Lead Time tRWL 20 Write Command to CAS Lead Time tCWL 20 - Data-in Setup Time tDS 0 Data-in Hold Time tDH 15 Write Command Setup Time Write Command Hold Time - HM514101A-8 HM514101A-1O Unit Note - us 10 20 - us ns - 25 - ns 20 - 25 - ns 0 - 0 - ns 11 us 11 Unit Note Min Max Min Max 0 15 - 0 10 - 20 20 15 20 Read-Modify-Write Cycle Parameter Symbol HM514101A-7 HM514101A-8 HM514101A-1O Min Max Min Max Min Max - Read-Modify-Write Cycle Time tRwC 155 - 175 - 210 RAS to WE Delay Time tRWD 70 - 80 - 100 CAS to WE Delay Time tcWD 20 - 20 - 25 Column Address to WE Delay Time tAWD 35 - 40 - 45 us ns 10 ns 10 us 10 Unit Note Refresh Cycle Parameter HM514101A-7 Symbol HM514101A-8 HM514101A-1O Min Max Min Max Min Max CAS Setup Time (CAS Before RAS Refresh Cycle) tcsR 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tcHR 10 - 10 - 10 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 10 10 - 10 - ns tCPN - 10 CAS Precharge Time in Normal Mode us Nibble Mode Cycle Parameter Symbol HM514101A-7 Min HM514101A-8 Max Min HM514101A-1O Max Min Max Unit Nibble Mode Access Time tNAC - 20 - 25 - 25 ns Nibble Mode Cycle Time tNC 40 45 10 10 10 - ns tNCP - 45 NibbleMode CAS Precharge Time Nibble Mode CAS Pulse Width tNCA 20 - 25 - 25 - us Nibble Mode RAS Hold Time tNRSH 20 - 25 - 25 - us Note ns Nibble Mode Read-Modify-Write Cycle Parameter Symbol Nibble Mode Read-Modify-Write Cycle Time HM514101A-7 HM514101A-8 HM514101A-1O Unit Min Max Min Max Min Max tNRWC 55 - 75 - 75 - ns Nibble Mode Write Command to CAS Lead Time tNcWL 20 - 25 - 25 - ns Nibble Mode CAS to WE DeJayTime tNCWD 20 - 25 - 25 - ns • 346 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 Note HM514101A Series Test Mode Cycle Parameter Symbol HM514101A-7 Min Max HM514101A-S Min Test Mode WE Setup Time tws 0 - 0 Test Mode WE Hold Time tws 10 - 10 Max - HM514101A-1O Min Unit Max 0 - ns 10 - ns Note Counter Test Cycle Parameter CAS Precharge Time in Counter Test Cycle Notes: Symbol tCPT HM514101A-7 HM514101A-S HM514101A-1O Min Max Min Max Min 40 - 40 - 50 Max Unit - Note ns 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD S tRCD (max) and tRAD S tRAD (max). If tRcD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TIL loads and 100 pF. 4. Assumes that tRCD C!: tRCD (max) and tRAD S tRAD (max). 5. Assumes that tRCD S tRcD (max) and tRAD C!: tRAD (max). 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIR (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIR and VIL. S. Operation with the tRCD (max) limit insures that tRAc (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. twcs, tRWD, lewD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs C!: twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; iftRWD C!: tRWD (min), lewD C!: tCWD (min) and tAWD C!: tAWD (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. An initial pause of 100 /.I.s is required after power-up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a miuimum of eight CAS before RAS refresh cycles is required. 13. Test mode operation specified in this data sheet is S-bit test function with control address bits-RAIO, CAlO and CAO being don't care. This test mode operation can be performed by WE and CAS before RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of eight test bits match each other, the condition of the output data is high level. When the state of test bits do not match, the condition of the output data is low level. Data output pin is Dou! and data input pin is Om. In order to end this test mode operation, perform a RAS only refresh cycle or a CAS before RAS refresh cycle. 14. In a test mode read cycle, the value of tRAC, tAA, tCAC and tNAC is delayed for 2 ns to 5 us for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. ~HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 347 HM514101A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read Cycle tT-.I--W-- tCSH Address tOFF Dout r;:::;w.J. ~Jj : Don l c - 5 - 5 - 5 mA CAS Before RAS Refresh Current ICC6 - 90 - SO - 70 mA tRC = Min 90 - SO 70 mA tpc = Min 10 -10 10 -10 10 p,A OV:s; Vin:S; 7V OV :s; Vout :s; 7V D out = Disable Fast Page Mode Current ICC? Input Leakage Current ILl -10 Output Leakage Current ILO -10 10 -10 10 -10 10 p,A Output High Voltage VOH 2.4 Vcc 2.4 Vcc 2.4 VCC V High lout Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 V Low lout Notes: 2 I 1,3 = - 5 mA = 4.2 mA 1. Icc depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIR. • Capacitance (TA = 25·C, Vee = 5V ±10%) Max Unit Note Input Capacitance (Address) Parameter CII - 5 pF I Input Capacitance (Clocks) CI2 - 7 pF I CliO - 10 pF 1,2 Output Capacitance (Data-in, Data-out) Notes: Symbol Typ 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIR to disable D out . ~HITACHI 362 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM514400 Series • AC Characteristics (TA = 0 to +70·C, Vee = 5V ±10%, Vss = OV)1, 14, 15, 16 Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Symbol HM5144oo-8 Min HM5144oo-10 Max HM514400-12 Max Min Min Unit Max Random Read or Write Cycle Time tRC ISO - 180 RAS Precharge Time tRP 60 - 70 RAS Pulse Width tRAS 80 10000 100 10000 120 10000 ns CAS Pulse Width tCAS 25 10000 25 10000 30 10000 ns Row Address Setup Time tASR 0 Row Address Hold Time tRAH 12 Column Address Setup Time tASC 0 Column Address Hold Time tCAH RAS to CAS Delay Time IS - tRco 22 RAS to Column Address Delay Time tRAO RAS Hold Time - - 210 80 0 - 0 15 - 0 20 - 55 25 17 40 tRSH 25 CAS Hold Time tCSH CAS to RAS Precharge Time tCRP OE to Din Delay Time Note ns ns ns 15 - 0 - ns 25 - ns 75 25 90 ns 8 20 55 20 65 ns 9 - 25 30 - 100 5 - 10 toDD 20 25 30 OE Delay Time from Dm tozo 0 0 0 - ns CAS Setup Time from Din tozc 0 - - ns 80 - 0 - 0 - ns Transition Time (Rise and Fall) tT 3 50 3 50 3 50 ns Refresh Period tREF 16 - 16 ms - - 16 120 10 ns ns ns ns 7 Read Cycle Parameter Symbol HM514400-1O HM514400-12 Min Max Min Max Min 80 100 - 120 ns 2,3, 17 25 25 - 30 ns 3,4,13 55 ns 3,5,13,16 30 ns HM514400-8 Access Time from RAS tRAC Access Time from CAS tCAC Access Time from Address tAA - 25 - Access Time from OE 40 45 Unit Max Note toAC - Read Command Setup Time tRCS 0 - 0 - ns tRCH 0 - 0 - 0 Read Command Hold Time to CAS 0 ns Read Command Hold Time to RAS tRRH 10 10 - 10 Column Address to RAS Lead Time tRAL 40 - 45 - 55 - Output Buffer Tum-off Time tOFFl 0 20 0 25 0 30 ns 6 Output Buffer Tum-off to OE tOFF2 0 20 0 25 0 30 ns 6 CAS to Din Delay Time tcoo 20 - 25 - 30 - ns 25 ns ns Write Cycle Parameter Symbol HM514400-8 Min Max HM514400-1O HM514400-12 Min Max Min Write Command Setup Time twcs 0 Write Command Hold Time tWCH 15 Write Command Pulse Width twp 15 Write Command to RAS Lead Time tRWL 25 Write Command to CAS Lead Time tCWL 25 - Data-in Setup Time tos 0 - 0 Data-in Hold Time tOH 15 - 20 Max Unit Note 10 0 - 0 - ns 20 - 25 ns 20 - 0 - ns II 25 - ns II 25 25 25 30 30 ns ns ns ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 363 HM514400 Series Read-Modify-Write Cycle Parameter HM514400-8 Symbol HM514400-1O HM514400-12 Min Max Min Min - 245 Read-Modify-Write Cycle Time tRwC 210 RAS to WE Delay Time tRWD 110 CAS to WE Delay Time tCWD 55 Column Address to WE Delay Time tAwD 70 OE Hold Time from WE tOEH 25 Max - 135 60 80 25 Max Unit Note ns ns 10 70 - ns 10 95 - ns 10 30 - ns 285 160 Refresh Cycle HM5144oo-8 Parameter Symbol Min Max HM514400-1O HM5144oo-12 Min Max Min Max Unit CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 20 - 20 - 25 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - ns Note Fast Page Mode Cycle HM514400-8 Symbol Parameter Min HM514400-12 HM514400-1O Min Max - Max Min 55 - 65 10 - 15 Fast Page Mode Cycle Time tpc 55 Fast Page Mode CAS Precharge Time tcp 10 Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 Access Time from CAS Precharge tACP - 50 - 50 - RAS Hold Time from CAS Precharge tRHCP 50 - 50 - Fast Page Mode Read-Modify-Write Cycle Time tpCM 105 - 110 - Max Unit - Note ns ns 100000 ns 12 60 ns 13,17 60 - ns 130 - ns Test Mode Cycle Parameter Symbol HM5144oo-12 HM5144oo-1O HM514400-8 Min Min Max Max Min Max Unit Test Mode WE Setup Time tws 0 - 0 - 0 - ns Test Mode WE Hold Time tWH 20 - 20 - 20 - ns Note Counter Test Cycle Parameter CAS Precharge Time in Counter Test Cycle Notes: Symbol tCPT HM5144oo-8 Min 40 Max - HM514400-1O Min 50 Max - HM514400-12 Min 60 Max - Unit ns I. AC measurements assume tT = 5 ns. 2. Assumes that tRcD S tRCD (max) and tRAD S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAc exceeds the value shown. 3. Measured with a load circuit equivalent to 2TTL loads and 100 pF. 4. Assumes that tRCD ;;: tRCD (max) and tRAD S tRAD (max). 5. Assumes that tRCD S tRCD (max) and tRAD ;;: tRAD (max). 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V1H and VIL' @HITACHI 364 Note Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM514400 Series 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAO (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. twcs, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs tAA, tOAC and tACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. • TIMING WAVEFORMS • Read Cycle Address Dout Din • ~ . Don'leare 0064-3 @HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 365 HM5144DO Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Early Write Cycle RAS CAS Address WE Din Dout OE . Don' care • ~ : Don' care 0064-5 • Delayed Write Cycle Address WE Din Dout • ~ : Dorll care 0064-6 $ 366 HITACHI Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HM514400 Series • Read-Modify-Write Cycle Address '"","","" l'-....,..-o/f Din Dout • ~:Don'I"" 0064-7 • RAS Only Refresh Cycle lAC Address Dout ·oe.WE:DoftI .... ·~·'Don'tGMt •• RelteIh Add,...: /tD-A9 (AXO-A)(9) 0064-8 $ HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 367 HM514400 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Hidden Refresh Cycle Address Dout Din .,~ Don" car. 0064-9 • CAS Before RAS Refresh Cycle Dout OPEN • ~:00n1care .. 'WE :VUo! 0064-10 ~HITACHI 368 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM514400 Series • Fast Page Mode Read Cycle Address Dout ·~Oon'lc:;ue 0064-11 • Fast Page Mode Early Write Cycle Address Din Hogh·Z Dout . OE Don't care .~ Oon'lcare 0064-12 $ HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300 369 HM514400 Series • Fast Page Delayed Cycle Address Din Dout ~'Oon'ICMI 0064-13 • Fast Page Mode Read-Modify-Write Cycle Address Din Dout 0064-14 • 370 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514400 Series • Test Mode Cycle ·3 seteycle Reset Cycle "1"3 Test mode cycle Normal mode WE ., eBR or RAS only refresh ·2 ~ Don'l care ·3 Address, Oln, OE Don't care 0064-15 • Test Mode Set Cycle WE Address Dout OPEN Note" ~ Don'tcare 0064-16 • Test Mode Reset Cycle CAS Before RAS Refresh Cycle WE Dout OPEN Note·' r2'ZZLI Oon't car. 0064-17 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300 371 HM514400 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle Address OPEN Dout No. " Refresh Addr... 1.0-1.9 (AXO-AX9) ~2 ~ Don'r care 0064-18 • CAS Before RAS Refresh Counter Check Cycle (READ) Ai Din Dout 0064-19 @HITACHI 372 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005,1819· (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514400 Series • CAS Before RAS Refresh Counter Check Cycle (WRITE) Ai Din OPEN Dout 0064-20 • 4M DRAM LOW POWER VERSION The specification on the low power version Is the same as the standard 4 megabit DRAM with the exception of the following parameters. Item Conditions 4Mxl Type No. Specifications HM514100UP/LZP IMx4 - Temperature 0-55·C ICC2 (Standby CMOS Interface) RAS. CAS. WE ~ Vcc - O.2V Other Pin ~ Vcc - O.2Vor S O.2V (Address and Din is Stable) Dout: High-Z IcCIO (Standby with CBR Refresh) tRC = 125 ",s. tRAS S 1 ~1 ~ ~C - O.2V. VIL S O.2V WE and OE = VIH. Address and DID is Stable Dout: High-Z 300 ",A max - 128ms 200 ",A max "'S Refresh tREF • HITACHI Hitachi America. Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005·1819. (415) 589-8300 373 HM514400L Series Low Power Version 1,048,576-Word x 4-Bit Dynamic Random Access Memory • DESCRIPTION HM514400UP Series The Hitachi HM514400 is a CMOS dynamic RAM organized 1,048,576 word x 4-bit. HM514400 has realized higher density, higher performance and various functions by employing 0.8 /Lm CMOS process technology and some new CMOS circuit design technologies. The HM514400 offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514400 to be packaged in standard 20-pin plastic SOJ and 20-pin plastic ZIP. 90CP200A (CP-20DA) • FEATURES HM514400LZP Series • Single 5V (±10%) • High Speed Access Time ................................. 80 ns/100 ns/120 ns (max) • Low Power Dissipation Active Mode ............................ 495 mW/440 mW/385 mW (max) Standby Mode .......................................... '... 11 mW (max) • Fast Page Mode Capability , • 1,024 Refresh Cycles ............................................... (128 ms) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh • Test Function • Battery Back Up Operation 3DZP20 (ZP-20) • PIN OUT • ORDERING INFORMATION 1/01 Part No. Access Package HM5l4400UP-8 HM5l4400UP-1O HM5l4400UP-12 80ns lOOns l20ns 350 mi120-pin PlasticSOJ (CP-20DA) HM5l4400LZP-8 HM5l4400LZP-1O HM5l4400LZP-12 80ns lOOns l20ns 400 mil 20-pin Plastic ZIP (ZP-20) 1102 WE RAS • PIN DESCRIPTION Pin Name Function Ao- A9 Ao- A9 Refresh Address Input V Ot-V0 4 Data-iuIData-out Row Address Strobe CAS Column Address Strobe WE ReadlWrite Enable OE Output Enable Vee Power ( + 5Y) VSS Ground 18 1/03 17 CAS 16 Oe Ao 6 A, 7 15 AS 14 A7 A2 8 A3 9 13 AS 12 AS Vcc10UC==~11 A4 Address Input RAS 3 4 AS 5 0065-1 (Top View) HM514400LZP Series CAS 2 1104 4 1101 6 We 8 IS 10 A, 12 A3 10E 3 IJ03 5 Vss 7 1102 9 RAS 11 Ao 13A2 15VCC 17 A5 19A7 0065-2 (Bottom View) o 374 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM514400L Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol VT -1.0to Supply Voltage Relative to Vss vcc - 1.0 to Short Circuit Output Current lout Power Dissipation PT Operating Temperature Topr Storage Temperature T sIg Unit Value Voltage on Any Pin Relative to Vss + 7.0 + 7.0 V V 50 rnA 1.0 W + 70 55 to + 125 ·C Oto - ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70·C) Parameter Symbol Min Typ Max Unit VSS 0 0 0 V Vcc 4.5 5.0 5.5 V I VIH 2.4 6.5 V I (1/0 Pin) VIL -1.0 O.S V I (Others) VIL -2.0 - O.S V I Supply Voltage Input High Voltage Input Low Voltage Note: I 1 I. All voltage referenced to Vss. • DC Electrical Characteristics (TA Parameter Operating Current Standby Current Symbol IcC! = 0 to + 70·C, Vee = 5V ± 10%, Vss = OV) HM514400-S HM514400-1O HM514400-12 Min Min Min Max Max Max Unit ICC3 90 - SO - 70 rnA RAS, CAS Cycling tRC = Min - 2 - 2 - 2 rnA TTL Interface RAS, CAS = VIH, D out = High-Z CMOS Interface RAS, CAS and WE ~ Vcc - 0.2Vor :S 0.2V, Address and Din: Stable, D out = High-Z - 200 - 200 - 200 fLA - 90 - SO - 70 rnA tRC RAS CAS Dout Standby Current ICC5 - 5 - 5 - 5 rnA CAS Before RAS Refresh Current ICC6 - 90 - SO - 70 rnA ICC7 - 90 - SO - 70 rnA Fast Page Mode Current Battery Back Up Operating Current (Standby with CBR Refresh) IcCIO Input Leakage Current ILl Test Conditions - ICC2 RAS Only Refresh Current - -10 300 10 - -10 300 - 10 -10 = Min = VIH, = VIL, = Enable = Min = Min tRC = 125 fLs, Note 1,2 2 I tRC tpc 1,3 tRAS :S I fLs VCC - 0.2V :S VIH:S 6.5V, OV :S VIL :S 0.2V, WEandOE = VIH, Address and Din: Stable, Doul = High-Z 300 fLA 10 fLA OV :S Yin :S 7V OV:SVout :S7V Doul = Disable Output Leakage Current lLO -10 10 -10 10 -10 10 fLA Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High lout Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 V Low lout Notes: Note = - 5 rnA = 4.2 rnA I. ICC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL' 3. Address can be changed once or less while CAS = VIH' @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 375 HM5144DDL Series • Capacitance (TA = 25'C, Vee = 5V ±10%) Parameter Symbol Typ Max Unit Note Input Capacitance (Address) Cll 5 pF I Input Capacitance (Clocks) CI2 - 7 pF I pF 1,2 Output Capacitance (Data-in, Data-out) Notes: 10 CliO I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out . • AC Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss OV)1, 14, 15, 16 = Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter HM514400-8 Symbol HM514400-1O HM514400-12 Min Max Min Max Min Max - 210 - Unit Random Read or Write Cycle Time tRC 150 - 180 RAS Precharge Time tRP 60 - 70 tRAS 80 10000 100 10000 120 10000 ns tCAS 25 10000 25 10000 30 10000 ns RAS Pulse Width CAS Pulse Width 15 - tRCD 22 RAS to Column Address Delay Time RAS Hold Time CAS Hold Time 80 Note ns ns 0 - ns 15 - ns 0 - 0 - ns 20 - 25 - ns 55 25 75 25 90 ns 8 tRAD 17 40 20 55 20 65 ns 9 tRSH 25 - 25 - 30 80 100 tCRP 5 10 - 120 CAS to RAS Precharge Time 10 - ns OE to Din Delay Time tODD 20 25 - 30 - ns OE Delay Time from Din tDZO 0 - - ns tCSH Row Address Setup Time tASR 0 Row Address Hold Time tRAH 12 Column Address Setup Time tASC 0 Column Address Hold Time tCAH RAS to CAS Delay Time CAS Setup Time from Din tDZC Transition Time (Rise and Fall) tT Refresh Period 0 3 - tREF 0 15 ns 0 - 0 - ns 0 - 0 - ns 50 3 50 3 50 ns 128 - 128 - 128 ms 7 Read Cycle Parameter Symbol HM514400-8 Min HM514400-1O HM514400-12 Max Min Max Min Max 80 100 ns 2,3,17 30 ns 3,4,13,17 55 ns 3,5,13, 16, 17 25 - 25 - 120 40 - 30 ns - ns Access Time from RAS tRAC Access Time from CAS tCAC Access Time from Address tAA Access Time from OE tOAC - Read Command Setup Time tRCS 0 - 0 - 0 Read Command Hold Time to CAS tRCH 0 - 0 0 Read Command Hold Time to RAS tRRH 10 - 10 Column Address to RAS Lead Time tRAL 40 - 45 - 55 Output Buffer Turn-off Time 25 25 45 10 Unit Note ns 18 ns 18 ns tOFF! 0 20 0 25 0 30 ns 6 Output Buffer Turn-off to OE toFF2 0 20 0 25 0 30 ns 6 CAS to Din Delay Time tCDD 20 - 25 - 30 - ns ~HITACHI 376 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM514400L Series Write Cycle Parameter HM514400·8 Symbol Min Max twcs 0 Write Command Hold Time tWCH 15 Write Command Pulse Width twp 15 Write Command to RAS Lead Time tRWL 25 Write Command to CAS Lead Time tCWL 25 Data·in Setup Time tDS 0 - Data·in Hold Time tDH 15 - Write Command Setup Time HM514400·1O HM514400·12 Min Max Min 0 0 - 20 - 20 20 25 25 Max - 0 25 25 30 30 0 25 Unit Note ns 10 ns ns ns ns ns 11 ns 11 Unit Note Read-Modify-Write Cycle Parameter HM514400·8 Symbol Min HM5 14400· 10 Max HM514400-12 Max Min Min Max Read·Modify·Write Cycle Time tRWC 210 - 245 - 285 - ns RAS to WE Delay Time tRWD 110 - 135 - 160 - ns CAS to WE Delay Time tCWD 55 - 60 - 70 - ns 10 Column Address to WE Delay Time tAWD 70 80 10 25 - ns toEH - 95 OE Hold Time from WE - 25 30 10 ns Refresh Cycle Parameter HM514400·8 Symbol HM514400·1O HM5 14400-1 2 Min Max Min Max Min Max Unit CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 20 - 20 - 25 - ns tRPC 10 - 10 - 10 - ns RAS Precharge to CAS Hold Time Note Fast Page Mode Cycle Parameter HM514400-8 Symbol Min HM514400·12 HM514400·1O Max Min Max Min Max Unit Fast Page Mode Cycle Time tpc 55 - 55 - 65 - ns Fast Page Mode CAS Precharge Time tcp 10 - 10 - 15 - ns Fast Page Mode RAS Pulse Width tRASC Access Time from CAS Precharge tACP - RAS Hold Time from CAS Precharge tRHCP Fast Page Mode Read·Modify·Write Cycle Time tpCM Note 100000 - 100000 - 100000 ns 12 50 - 50 - 60 ns 13,17 50 - 50 - 60 - ns 105 - 110 - 130 - ns Test Mode Cycle Parameter Test Mode WE Setup Time Test Mode WE Hold Time Symbol HM514400·8 HM514400-1O HM514400-12 Max tws 0 - 0 - 0 - ns tWH 20 - 20 - 20 - ns Min Max Min Max Unit Min Note Counter Test Cycle Parameter CAS Precharge Time in Counter Test Cycle Symbol tCPT HM514400·8 Min HM514400·1O Max Min - 50 40 • Max - HM514400·12 Min Max 60 - Unit Note ns HITACHI Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819' (415) 589·8300 377 HM514400L Series Notes: I. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :s tRCD (max) and tRAD :s tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD O!: tRCD (max) and tRAD :s tRAD (max). 5. Assumes that tRCD :s tRCD (max) and tRAD O!: tRAD (max). 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. twcs, tRWD, leWD and tAwD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs O!: twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) through the entire cycle; if tRWD O!: tRWD (min), tCWD O!: tCWD (min), and tAWD O!: tAWD (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. tRASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of tAA or tCAC or tACP' 14. An initial pause of 100 !,-S is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Test mode operation specified in this data sheet is 8-bit test function controlled by control address bits-CAO. This test mode operation can be performed by WE and CAS before RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of eight test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. Data output pin is 1/03 and data input pin is 1/02. In order to end this test mode operation, perform a RAS only refresh cycle or a CAS before RAS refresh cycle. 17. In a test mode read cycle, the value of tRAC, tAA, tOAC and tACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. ~HITACHI 378 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514400L Series • TIMING WAVEFORMS • Read Cycle (1) tr '~Ho" Address WE Dout Din . WA :Don't care 0065-3 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 379 HM514400L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Early Write Cycle (2) tAC tCSH tCRP tRSH Address WE Din Oout OE : Don' care '1%/ n~~'7~'7~'i : Don't care 0065-5 • 380 HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514400L Series • Delayed Write Cycle (3) Address WE Din Din . WM :Don' care 0065-6 ~HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 381 HM514400L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Read-Modify-Wrlte Cycle (4) Address Din Dout • ~: Don' care 0065-7 • RAS Only Refresh Cycle (5) Address Dout •• DE. WE : Don' care • ~ : Don' care •• REFRESH ADDRESS: AO·A9 (AXO-AX9) 0065-8 $ 382 HITACHI Hitachi America. Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514400L Series • Hidden Refresh Cycle (6) Address WE o Dout t Din : Don' care 0065-9 • CAS Before RAS Refresh Cycle (7) tAC tRPC tCRP Address~ Dout OPEN ~ WE :Don'care :VIH 0065-10 @HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 383 HM514400L Series - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read Cycle (8) ~ ~i'- ) IT+ IRHCP ICSH ... Ipc ICAS ~ ~ IRAH ~ Address ~ Row ~ 0< e WB,WE 1+ IRCfit,. /,////////,;f Ico~ 10lC. Din IASC +-. ~ Col. /'///// 1000... t l tCAC ~ lAA- Hi-Z lASe .~i'" IRCS • IRCH__ .. 10lC Icoo ~1 IoAC ~ ~~///////~ i'" ..-~ IRCH VI ... _ 10lC I+-- \L; lAA ~ ACP 1'---1 I'--' Dout tOFF2V/;& Icoo ICAC ~ tOF~l+ r, Hi-Z 10lO ~ IRRH ~ 07; r~ Dout Dout '" tRAL 4f'H ~///b Col. ICRP -- 5 IACP tOFF 1 lRAC 10lO - ~ ICAH lASe IRCS ~::J Ir---!\ lCAH -IRAO IASR IRSH Icp. IRCO of- ~ Hi-Z + ~OOO tooc !:jj 10FF! Dout IOFF2 IJ/~;Ar~~ lOAC....l- I+- • ~ : Don'l care 0065-11 ~HITACHI 384 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM514400L Series • Fast Page Mode Early Write Cycle (9) RAS Address WE Din Dout Hi-Z • OE : Don' care •~ : Don' care 0065-12 • Fast Page Delayed Write Cycle (10) tRASC Address Din Dout ~ : Don' care 0065-13 @HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 385 HM514400L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read-Modify-Write Cycle (11) CAS Address Din Dout • ~ Don't care 0065-14 • Test Mode Cycle "3 set cycle Reset Tesl mode cycle Cycle "1"3 Normal mode "1 CBR or RAS only refresh "2 Don' care "3 Address, Din, OE : Don' care rzzn : 0065-15 ~HITACHI 386 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - HM514400L Series • Test Mode Set Cycle (1) Address 1///$/$/I/////I/////$/////////$////h OPEN Dout Note *1 tVA :Don' care • Test Mode Reset Cycle (2) Address Dout ~//////////////ff//////////$//$a OPEN Note *1 rzm :Don' care 0065-17 @HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 387 HM514400L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle IRAS Address OPEN Dout Nole·1 Refresh Address AO~A9 (AXO~AX9) ·2 rzzz.J :Don' care 0065-18 • CAS Before RAS Refresh Counter Check Cycle, (READ) IRP Doul IROH Dout 100P "1 ~: Don't care 0065-19 • 388 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM514400L Series • CAS Before RAS Refresh Counter Check Cycle, (WRITE) Ai WE Din OPEN Dout "1 WA :Don't care 0065-20 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 389 HM514410 Series Preliminary 1,048,576-Word x 4-Bit Dynamic Random Access Memory • DESCRIPTION HM514410JP Series The Hitachi HM514410 is a CMOS dynamic RAM organized 1,048,576 word x 4-bit. HM514410 has realized higher density, higher performance and various functions by employing 0.8 ",m CMOS process technology and some new CMOS circuit design technologies. The HM514410 offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514410 to be packaged in standard 20-pin plastic SOJ and 20-pin plastic ZIP. 3DCP20DA (CP-20DA) • FEATURES HM514410ZP Series • Single 5V (±10%) • High Speed Access Time ................................. 80 ns/100 ns/120 ns (max) • Low Power Dissipation Active Mode ............................ 495 mW/440 mW/385 mW (max) Standby Mode ............................................. 11 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycles ................................................ (16 ms) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh • Test Function • Write per Bit Capability 3DZP20 (ZP-20) • PIN OUT HM514410JP Series • ORDERING INFORMATION Part No. Access Time Package W1/101 HM5l44IOJP-8 HM5l44IOJP-1O HM5l44IOJP-12 80ns lOOns l20ns 350 mil 20-pin PlasticSOJ (CP-20DA) WSNVE" HM5l44IOZP-8 HM5l44IOZP-1O HM5l44IOZP-12 80ns lOOns l20ns 400 mil 20-pin Plastic ZIP (ZP-20) • PIN DESCRIPTION Pin Name Function Ao- A9 Ao- A9 Refresh Address Input Wl/IO\-W4I'I04 Write Select/Data-inlData-out Address Input W21102 2 3 4 5 RAS A9 18 W3II03 17 CAS 16 OE Ao 6 A1 7 A2 8 A3 9 Vcc 10 15 14 13 12 11 A8 A7 A6 AS A4 0067-1 RAS Row Address Strobe CAS Column Address Strobe WB/WE Write per Bit/Write Enable OE Output Enable Vee Power ( + 5V) VSS Ground (Top View) HM514410ZP Series 1 OE W411044 WBlWE8 A9 3 W3II03 5 Vss 7 W2I102 9 RiiS 11 Ao A1 13A2 A3 15 Vee 17 As A4 A6 19A7 As 0067-2 (Bottom View) ~HITACHI 390 Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HM514410 Series • ABSOLUTE MAXIMUM RATINGS Parameter Value Uuit Voltage on Any Pin Relative to Vss Symbol VT -1.0to +7.0 V Supply Voltage Relative to Vss Vcc -1.0to + 7.0 V Short Circuit Output Current lout 50 mA Power Dissipation PT 1.0 W Operating Temperature Topr Oto + 70 °C Storage Temperature Tstg - 55 to + 125 °C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter to + 70"C) Min Typ Max Unit VSS 0 0 0 V Vcc 4.5 5.0 5.5 V VJH 2.4 6.5 V I (I/O Pin) VIL -1.0 0.8 V 1 (Others) VIL -2.0 - 0.8 V I Supply Voltage Input High Voltage Input Low Voltage = 0 Symbol I I Note I I. All voltage referenced to VSS' Note: • DC Electrical Characteristics (TA = 0 to +70"C, vee = 5V ±10%, Vss = OV) Symbol Parameter Operating Current ICC! Standby Current HM51441O-8 HM51441O-1O HM51441O-12 Min Min Min Max Max Max Unit Test Conditions Note 1,2 - 90 - 80 - 70 mA RAS, CAS Cycling tRC = Min - 2 - 2 - 2 mA TTL Interface RAS, CAS = VJH, D out = High-Z - I - I - I mA CMOS Interface RAS, CAS ~ Vcc - 0.2V, Dout = High-Z - 90 - 80 - 70 rnA tRC ICC2 RAS Only Refresh Current ICC3 = Standby Current ICCS - 5 - 5 - 5 mA CAS Before RAS Refresh Current ICC6 - 90 - 80 - 70 mA tRC = Min - 90 Fast Page Mode Current ICC7 mA tpc = Min -10 10 10 -10 70 ILl -10 80 Input Leakage Current 10 p.A OV S Yin S 7V Output Leakage Current ILO -10 10 -10 10 -10 10 p.A OV S Vout S 7V, Dout = Disable Output High Voltage VOH 2.4 Vcc 2.4 VCC 2.4 VCC V High lout = - 5 mA VOL 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 mA Output Low Voltage Notes: 2 Min RAS = VJH, CAS = VILD out = Enable 1 1,3 I. Icc depends on output load condition when the device is selected, Icc max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VJH. • Capacitance (TA = 25"C, Vee = 5V ± 10%) Parameter Notes: Symbol Input Capacitance (Address) Cn Input Capacitance (Clocks) CI2 Output Capacitance (Data-in, Data-out) CliO Typ - Max Unit Note 5 pF 1 7 pF 1 10 pF 1,2 I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VJH to disable D out . ~HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 391 HM514410 Series • AC Characteristics (TA = 0 to 70'C, Vee = 5V ±10%, Vss = OV)I, 14, 15, 16 Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Random Read or Write Cycle Time HM51441O·1O HM51441O·8 Symbol Min Max - HM51441O·12 Min Max Min Max 180 - 210 - Unit tRC 150 RAS Precharge Time tRP 60 RAS Pulse Width tRAS 80 10000 100 10000 120 10000 ns CAS Pulse Width tCAS 25 10000 25 10000 30 10000 ns Row Address Setup Time tASR 0 - 0 Row Address Hold Time tRAH 12 - 15 Column Address Setup Time tASC 0 - Column Address Hold Time tCAH 15 RAS to CAS Delay Time 70 80 Note ns ns 0 - ns 15 - ns 0 - 0 - ns - 20 - 25 - ns 55 25 75 25 90 ns 8 20 65 ns 9 30 ns 10 - 30 - ns tRCD 22 RAS to Column Address Delay Time tRAD 17 40 20 55 RAS Hold Time tRSH 25 tCSH 80 - 25 CAS Hold Time 100 CAS to RAS Precharge Time tCRP 5 - 10 OE to Din Delay Time tODD 20 25 OE Delay Time from Din tDZO 0 0 - 0 - ns CAS Setup Time from Din tDZC 0 - - 0 - 0 - ns Transition Time (Rise and Fall) tT 3 50 3 50 3 50 ns Refresh Period tREF - 16 16 ms 120 16 - - ns ns 7 Read Cycle Parameter Symbol HM51441O·8 Min HM51441O·1O HM51441O·12 Max Min Max Min Max Unit Note tRAC - 80 - 120 ns 2,3,17 tCAC - 25 - 100 Access Time from CAS 25 - 30 ns 3,4,13,17 Access Time from Address tAA - 45 ns 3,5,13,16,17 25 - 25 - 55 tOAC - 40 Access Time from OE 30 ns 17 Read Command Setup Time tRCS 0 0 - 0 - ns 0 - 0 - ns 10 - 10 ns Access Time from RAS Read Command Hold Time to CAS tRCH 0 Read Command Hold Time to RAS tRRH 10 - Column Address to RAS Lead Time tRAL 40 - 45 - 55 - Output Buffer Turn·offTime toFFl 0 20 0 25 0 30 ns 6 Output Buffer Turn·off Time to OE tOFF2 0 20 0 25 0 30 ns 6 CAS to Din Delay Time tCDD 20 - 25 - 30 - ns ns Write Cycle Parameter Symbol HM51441O·1O HM51441O·12 Min Max Min Min HM51441O·8 Max Max Unit Note 10 twcs 0 - 0 - ns tWCH 15 - 0 Write Command Hold Time 20 - 25 - ns Write Command Pulse Width twp 15 - 20 - ns tRwL 25 - 25 30 tCWL 25 - 25 Data·in Setup Time tDS 0 - 0 0 - ns Write Command to CAS Lead Time - 25 Write Command to RAS Lead Time Data·in Hold Time tDH 15 - 20 - 25 - ns Write Command Setup Time 30 ns ~HITACHI 392 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819. (415) 589·8300 ns 11 11 HM514410 Series Read-Modify-Write Cycle Parameter HM51441O-8 Symbol Min Max HM51441O-1O HM51441O-12 Min Min Max - Max Read-Modify-Write Cycle Time tRWC 210 - 245 - 285 RAS to WE Delay Time tRWD 110 - 135 - 160 CAS to WE Delay Time tCWD 55 - 60 - 70 Column Address to WE Delay Time tAWD 70 - 80 - 95 OE Hold Time from WE tOEH 25 - 25 - 30 Unit Note ns ns 10 ns 10 ns 10 ns Refresh Cycle Parameter HM51441O-8 Symbol HM51441O-1O HM514410-12 Min Max Min Max Min Max Unit CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 20 - 20 - 25 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - ns tCPN 10 - 10 CAS Precharge Time (Normal Mode) 10 - 15 - ns Note Fast Page Mode Cycle Parameter HM51441O-8 Symbol HM51441O-1O HM51441O-12 Max Unit Min Max Min Max Min - 55 - 65 - ns 15 - ns Note Fast Page Mode Cycle Time tpc 55 Fast Page Mode CAS Precharge Time tcp 10 Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 - 100000 ns 12 Access Time from CAS Precharge tACP - 50 - 50 - 60 ns 13,17 RAS Hold Time from CAS Precharge tRHCP 50 - 50 - 60 - ns Fast Page Mode Read-Modify-Write Cycle Time tpCM 105 - 110 - 130 - ns CAS Precharge to WE Delay Time tcpw 80 - 85 - 100 - ns 10 Test Mode Cycle Parameter HM514410-8 Symbol Test Mode WE Setup Time Test Mode WE Hold Time Min HM51441O-12 HM514410-1O Max Min Max Min Max Unit tws 0 - 0 - 0 - ns tWH 20 - 20 - 20 - ns Note Counter Test Cycle Parameter CAS Precharge Time in Counter Test Cycle HM51441O-8 Symbol Min 40 tCPT HM5144 10-10 Max Min - HM514410-12 Max Min - 50 Max Note ns - 60 Unit Write per Bit 1S ,19 Parameter Symbol HM51441O-8 Min Max - Write per Bit Setup Time tWBS 0 Write per Bit Hold Time tWBH 12 Write per Bit Selection Setup Time tWDS 0 Write per Bit Selection Hold Time tWDH 12 HM51441O-1O HM51441O-12 Min Max Min 0 - 15 0 15 Max Unit ns 0 - 15 - ns 0 15 Note ns ns ~HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 393 HM514410 Series Notes: 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD S tRCD (max) and tRAD S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD 2: tRCD (max) and tRAD S tRAD (max). 5. Assumes that tRCD S tRCD (max) and tRAD 2: tRAD (max). 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA10. twcs, tRWD, leWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs 2: twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; iftRWD 2: tRWD (min), tCWD 2: tCWD (min) and tAWD 2: tAWD (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. II. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. tRASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of tAA or tCAC or tACp. 14. An initial pause of 100 pos is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle of CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Test mode operation specified in this data sheet is 8-bit test function controlled by control address bits-CAO. This test mode operation can be performed by WE and CAS before RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of eight test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. Data output pin is 1/03 and data input pin is 1/02. In order to end this test mode operation, perform a RAS only refresh cycle or a CAS before RAS refresh cycle. 17. In a test mode read cycle, the value of tRAe. tCAe. tAA, tOAC and tACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 18. When using the write-per-bit capability, WBIWE must be low as RAS falls. 19. The data bits to which the write operation is applied can be specified by keeping Wl/IO], W2/I02, W3/I03 and W4/I04 high with setup and hold time referenced to the RAS negative transition. ~HITACHI 394 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589·8300 - - - - - - - - - - - - - - - - - - - - - - - HM514410 Series • TIMING WAVEFORMS • Read Cycle (1) tRC tRAS RAS ~ II tT tRCO CAS tAsR ~ Address tRAl I Row ~ W////~Yj//////////h Column tReS ~ tCAH JQ4 tRRH Hi-Z (Ooul Din tRAe tozc ij'///////h W/////~ tOFFl f-Dout to~ :b tcoo Hi-Z tOFF2 'i"///////g tooo tozo .1 OE tRCH 'l"/ / / / / / / ~.§/ tCAC tAA WlIlO' tCRP tASC tRAH I We,WE r'\.. ~ ~ J tRAO ..... tRP lRSH tCAS tCSH ~///////////////////~ ///////////////// . WM :Don'tcare 0067-3 eHITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 395 HM514410 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Early Write Cycle (2) Address WBlWE W1,I01 [Din W4II04 Dout • OE :Don' care . WA :Don' care 0067-5 .HITACHI 396 HHachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 HM514410 Series • Delayed Write Cycle (3) Address WB,WE W'r'[Din W4II04 Dout ____________ ~------_j RAS ---------~SH---------I I:----\cAS------l -~. f------------+--\cSH--------------~ CAS Address i+--------twcH--------I WE =1=" '"?~ Din~"_ _ _ _ _ _[),_'n_ _ _ _ ~....J _ High-Z • ~ :;:; Don't Care OE = Don't Care 0077-4 @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 433 HM514800 Series • Delayed Write Cycle Itlc ItlAS RAS tT ItlCD ·1 : teSH ItlsH teAS CAS Address WE OE • ~ = Don't Care ··'nvalid Dout comes out, when OE is low level. 0077-5 • 434 HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM514800 Series • Read-Modify-Write Cycle RAS CAS Address WE I1n Dout --------+-----() OE • ~ = Don't Care 0077-6 $ HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 435 HM514800 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle 1+---ItlAS----I~ RAS CAS High-Z Dout ------------------~~~-------------------------------------------• <>E, WE = Don't Core •• I?Z2J = Don't Care ••• Refresh address: AD - AS (AXD - AXS) oon-7 • CAS Before RAS Refresh Cycle RAS CAS Address High-Z •FZJ = Don't Care •• WE = ¥IH 0077-8 • 436 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 HM514800 Series • Hidden Refresh Cycle RAS CAS Address WE Dout -------+- IVCH Din Dout High-Z • ~ : Don't care 0150-14 ~HITACHI 494 Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM514170 Series Preliminary 262,144-Word x 16-81t Dynamic Random Access Memory • DESCRIPTION HM514170JP Series The Hitachi HM514170 are CMOS dynamic RAM organized as 262,144-word x 16-bit. HM514170 have realized higher density, higher performance and various functions by employing 0.8 I'm CMOS process technology and some new CMOS circuit design technologies. The HM514170 offer Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514170 to be packaged in standard 400 mil 40-pin plastic SOJ, standard 475 mil 40-pin plastiC ZIP. 3DCP400 (CP-40D) • FEATURES HM514170ZP Series • Single 5V (±10%) • High Speed Access Time ............. 70 ns/80 ns/l00 ns (max) • Low Power Dissipation Active Mode ....... 770 mW/660 mW/550 mW (max) Standby Mode ........................ 11 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycles .......................... (16 ms) • 2WE Byte Control • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh • PIN OUT • ORDERING INFORMATION Part No. Access Time Package HM5l417OJP-7 HM51417OJP-8 HM5l4l70JP-1O 70ns 80ns lOOns 400 mil40-pin PlasticSOJ (CP-40D) HM5l4l70ZP-7 HM5l4l70ZP-S HM5l4l70ZP-l0 70ns SOns lOOns 475 mil40-pin Plastic ZIP (ZP-40) • PIN DESCRIPTION Pin Name 1/00-1/0 15 RAS HM514170JP Series Vce Address Inpnt -Row Address Ao- A9 -Column Address Ao- A7 -Refresh Address Ao- A9 Data-inlData-out II015 I/Oll 4 1/012 6 1/01Z 1/014 10 1/04 7 8 9 IIOll IIOla 1/09 Vss 1/00 12 .., 1/08 Nt Nt LWE WE RAS A9q15 ReadlWrite Enable OE Output Enable Vee Column Address Strobe 1/014 11013 V" AO~16 Row Address Strobe 2 I/o., 6 UWE,LWE Vee Vss v" HM514170ZP Series Vee Al AZ A3 CAS dl I10aqz 1I01Q3 1I0ZQ4 1I03§S 1105 1106 1101 Function Ao- A9 3DZP40 (ZP-40) 17 18 <6pAS 2SPA7 24PA6 23 AS A4 Vss 8 I/Oz 14 Vee 16 I/O, 18 II~ 20 LWE 22 RAS 24 Ao 26 A2 28 Vee 30 A4 32 A(, 34 As 36 0159-1 Power(+SV) (Top View) Ground CAS 38 NC 40 I I/O, 3 1/0 10 5 Vss 7 I/O" 9 1/0 15 II Vee Il 1/01 15 110, 17 1/04 19 110, 21 NC 23 UWE 25 NC 27 Al 29 A, 31 Vss 33 A, 35 A7 37 OE 39 NC (Bottom View) $ HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 495 HM514170 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TRUTH TABLE Inputs 110 RAS LWE UWE CAS OE H L L L L L L H H H L H L H H H H H L L H H H L L L L L H H L H H H H 1100- 1107 High-Z High-Z Dout Din Don't Care Din High-Z Operation 1108-110 15 High-Z High-Z Dout Don't Care Din Din High-Z Standby Refresh Word Read Lower Byte Write Upper Byte Write Word Write • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Unit V VT -1.0to + 7.0 Supply Voltage Relative to Vss Vee - 1.0 to + 7.0 V Short Circuit Output Current lout PT 50 rnA 1.0 Oto+70 W ·C - 55 to + 125 ·C Power Dissipation Operating Temperature Topr Tstg Storage Temperature • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter I I to + 700C) Min Typ Max Unit VSS 0 0 0 V Vcc 4.5 5.0 5.5 V I VIH 2.4 - 6.5 V I (110 Pin) VIL -1.0 O.S V I (Others) VIL -2.0 - O.S V I Input High Voltage Input Low Voltage = 0 Symbol Supply Voltage Note: Value Voltage on Any Pin Relative to Vss I. All voltage referenced to Vss. • DC Electrical Characteristics (TA Parameter Operating Current Standby Current Symbol ICCI = 0 to + 700C, Vee = 5V ± 10%, Vss = OV) HM514170-7 HM514170-S HM514170-1O Min Max Min Max Min Max - 140 - 120 - 100 rnA - 2 - 2 - 2 rnA - I - I - I rnA - 150 - 130 - 110 rnA tRC Unit ICC2 RAS Only Refresh Current ICC3 Test Conditions RASCycling CAS Cycling tRC = Min TTL Interface RAS, CAS = VIH Dout = High-Z CMOS Interface RAS, CAS ~ Vee - 0.2V, Dont = High-Z = Min = VIR, = VII__ = Enable Standby Current ICC5 - 5 - 5 - 5 rnA RAS CAS Dout CAS Before RAS Refresh Current ICC6 - 150 - 130 - 110 rnA tRC Fast Page Mode Current ICC7 120 -10 110 rnA 10 ",A tpc OV S Yin S 7V Input Leakage Current ILl -10 130 10 -10 • 496 Note 10 = Min = Min HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 Note 1,2 2 I 1,3 HM514170 Series • DC Electrical Characteristics (TA Symbol Parameter = 0 to + 70'C, Vee HM514170-7 = 5V ± 10%, Vss HM514170-8 = OV) (continued) HM514170-1O Min Max Min Max Min Max Unit Test Conditions Note OV S Vout S 7V, D out = Disable Output Leakage Current ILO -10 10 -10 10 -10 10 Output High Voltage VOH 2.4 Vee 2.4 Vee 2.4 Vee V High lout = - 5 rnA Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 rnA Notes: !LA I. Icc depends on output load condition when the device is selected, Icc max is specified at the output open condition. 2. Address can be changed S I time while RAS = VIL' 3. Address can be changed S I time while CAS = VIR. • Capacitance (TA = 25'C, Vee = 5V ±10%) Parameter Symbol Input Capacita~ce (Address) CIl Input Capacitance (Clocks) Output Capacitance (Data-in, Data-out) Notes: Typ CI2 - CliO - Max Unit Note 5 pF I 7 pF I 10 pF 1,2 I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIR to disable D out . • AC Electrical Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss = OV)1, 14, 15 Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Symbol HM514170-7 Min Max HM514170-8 Min Max HM514170-1O Min Max - Unit Random Read or Write Cycle Time tRe 130 - 150 - 180 RAS Precharge Time tRP 50 - 60 - 70 RAS Pulse Width tRAS 70 10000 80 10000 100 10000 ns CAS Pulse Width teAS 20 10000 20 10000 25 10000 ns Row Address Setup Time tASR 0 - 0 Row Address Hold Time tRAH 10 10 Column Address Setup Time tAse 0 - Column Address Hold Time teAH 15 - RAS to CAS Delay Time tReD 20 RAS to Column Address Delay Time tRAD 15 - 50 20 15 35 ns ns ns 0 - 20 - ns 60 25 75 ns 8 15 40 20 55 ns 9 25 ns 10 - ns 25 - ns 0 - ns 0 - ns 0 0 15 ns ns RAS Hold Time tRSH 20 - 20 CAS Hold Time tesH 70 80 CAS to RAS Precharge Time teRP 10 OE to Din Delay Time tODD 20 OE Delay Time from Din tDZO 0 - CAS Setup Time from Din tDze 0 - 0 - Transition Time (Rise and Fall) tT 3 50 3 50 3 50 ns 16 - 16 - 16 ms Refresh Period tREF - Note 10 20 0 100 ns 7 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 497 HM514170 Series Read Cycle Parameter Symbol HM514170-7 Max Min 70 - Access Time from OE tOAC - Read Command Setup Time tRCS 0 Read Command Hold Time to CAS tRCH 0 Read Command Hold Time to R~S tRRH 0 Column Address to RAS Lead Time tRAL 35 - Output Buffer Tum-off Time tOFF! 0 Output Buffer Turn-off to OE tOFF2 tCDD Access Time from RAS tRAC Access Time from CAS tCAC Access Time from Address tAA CAS to Din Delay Time HM514170-8 Min 20 35 20 HM514170-1O Unit Note Max Min Max 80 - 100 ns 2,3 25 ns 3,4,13 45 ns 3,5, 13 25 ns 0 ns 20 40 20 40 - 55 - 15 0 15 0 20 ns 6 0 15 0 15 0 20 ns 6 15 - 15 - 20 - ns 0 0 0 0 0 ns ns ns Write Cycle Parameter Symbol HM514170-7 Max tRWL 20 Write Command to CAS Lead Time tcWL 20 Data-in Setup Time tDS 0 - Data-in Hold Time tDH 15 - Write Command Setup Time twcs 0 Write Command Hold Time tWCH twp 15 10 Write Command Pulse Width Write Command to RAS Lead Time HM514170-8 Min Min Max 0 - 15 10 20 20 0 15 HM514170-1O Unit Note - ns 10 - ns Min Max 0 20 20 25 25 0 20 ns ns ns ns ns 11 11 Read-Modify-Write Cycle Parameter Symbol HM514170-7 HM514170-8 HM514170-1O Min Max Min Max Min Max - 200 - 245 - Read-Modify-Write Cycle Time tRWC 180 RAS to WE Delay Time tRWD 95 CAS to WE Delay Time tCWD 45 Column Address to WE Delay Time tAWD 60 OE to Hold Time from WE tOEH 20 105 45 65 20 135 60 80 25 Unit Note ns ns 10 ns 10 ns 10,13 ns Refresh Cycle Parameter Symbol HM514170-8 HM514170-7 HM514170-1O Min Max Min Max Min Max Unit CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 10 - 10 - 10 - ns RAS Precharge to CAS Hold Time tRPC 10 - ns 10 - 10 tCPN - 10 CAS Precharge Time in Normal Mode 10 10 ~HITACHI 498 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819. (415) 589-8300 ns Note HM514170 Series Fast Page Mode Cycle Parameter Symbol HM514170-7 Min Fast Page Mode Cycle Time tpc 45 Fast Page Mode CAS Precharge Time tcp 10 Fast Page Mode RAS Pulse Width tRASC Access Time from CAS Precharge tACP - RAS Hold Time from CAS Precharge tRHCP Fast Page Mode Read-Modify-Write Cycle CAS Precharge to WE Delay Time Fast Page Mode Read-Modify-Write Cycle Time HM514170-8 Max Min - HM514170-1O Max Min Max - 50 - 55 10 - 10 40 - 40 - tcpw 65 tpCM 95 Unit ns ns 45 - 45 - 50 - ns - 70 - 85 - ns - 100 - 1\0 - ns 100000 100000 Note 100000 ns 12 50 ns 3, 13 Counter Test Cycle Parameter CAS Precharge Time in Counter Test Cycle Notes: Symbol tCPT HM514170-7 HM514170-8 Min Max Min 50 - 50 Max - HM514170-1O Min 50 Max - Unit Note ns 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :s; tRCD (max) and tRAD :s; tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD ., tRCD (max) and tRAD :s; tRAD (max). 5. Assumes that tRCD :s; tRCD (max) and tRAD ., tRAD (max). 6. !oFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. twcs, tRWD, tcwD and tAwD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs ., twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRwD ., tRwD (min), tcwD ., tcwD (min), tAwD ., tAwD (min) and tcpw ., tcpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. II. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. tRASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of tAA or tCAC or tACP. 14. An initial pause of 100 I's is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either tRCH or TRRH must be satisfied for a read cycle. 17. When both LWE and UWE go low at the same time, all 16-bits data are written into the device. LWE and UWE cannot be staggered within the same write cycles. ~HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 499 HM514170 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read Cycle tT tCRP Address UWE LWE tCAe tOFF1 Dout h-Z teDD Din tODD • ~ : Don't care 0159-2 ~HITACHI 500 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005- t 819. (415) 589-8300 HM514170 Series • Early Write Cycle t~c Address tWCH UWE LWE tos Din Din High-Z Dout • ~ : Don't care Oe: Don't care 0159-3 • HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 501 HM514170 Series • Delayed Write Cycle Address twp UWE LWE Din Dout • ~ : Don't care .. Invalid Dout comes out, when OE is low level. 0159-4 @HITACHI 502 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM514170 Series • Read-Modify-Write Cycle Address UWE LWE Din Dout * ~ : Don't care 0159-5 >> ~ : Don't care twcs;;: twcs (min) 0100-12 @HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 559 HM5116100 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Delayed Write Cycle Address Din Dout * ~ : Don't care 0100-13 .HITACHI 560 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 HM5116100 Series • Fast Page Mode Read-Modify-Write Cycle Address Din Dout • ~ : Don't care 0100-14 @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 561 HM5116100 Series • Test Mode Cycle • *** • CBR or RAS only refresh ~ ••• : Don't care Address, Din: Don't care 0100-15 • Test Mode Set Cycle Address Dout OPEN • ~ : Don't care 0100-16 ~HITACHI 562 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM5116100 Series • Test Mode Reset Cycle CAS Before RAS Refresh Cycle Address OPEN Dout * ~ ; Don't care 0100-17 RAS Only Refresh Cycle Address Dout ~~~~~ OPEN * Refresh address AO-A 11 (RAO-RA 11) ~ ; Don't care 0100-18 eHITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 563 HM5116100 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CAS Before RAS Refresh Counter Check Cycle (Read) Address Din Dout • ~ : Don't care 0100-19 ~HITACHI 564 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM5116100 Series CAS Before RAS Refresh Counter Check Cycle (Write) Din Dout • ~ : Don't care 0100-20 ~HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 565 HM5116100L Series Product Preview Low Power Version 16,777,216-Word x 1-Bit Dynamic Random Access Memory • DESCRIPTION HM5116100U Series The Hitachi HM5116100 is a CMOS dynamic RAM organized 16,777,216 words x 1-bit. It employs the most advanced CMOS technology for high performance and low power. The HM51161 00 offers Fast Page Mode as a high speed access mode. • FEATURES • Single 5V (± 10%) • High Speed Access Time ............................ 60 ns/70 ns/80 ns/100 ns (max) • Low Power Dissipation Active Mode .................... 495 mW/440 mW/385 mW/330 mW (max) Standby Mode ............................................. 11 mW (max) • Fast Page Mode Capability • Long Refresh Period 4096 Refresh Cycles ........................................... (256 ms) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh • Battery Back Up Operation 3DCP24D (CP-24D) HM5116100LZ Series 3DZP24 (ZP-24) • ORDERING INFORMATION Part No. Access Time Package HM51l61ooLJ-6 HM5116IooLJ-7 HM5116100LJ-8 HM51161ooLJ-1O 60ns 70ns 80ns lOOns 400 mil 24-pin PlasticSOJ (CP-24D) HM51161ooLZ-6 HM51161ooLZ-7 HM51l61ooLZ-8 HM5116IooLZ-1O 60ns 70ns 80ns lOOns 475 mi124-pin Plastic ZIP (ZP-24) • PIN OUT HM5116100U Series NC NC vss Din • PINQESCRIPTION Pin Name HM5116100LZ Series WE Function All Ao-All Address Input Ao-All Refresh Address Input Din Data Input Dout RAS Data Output Row Address Strobe A4 CAS Column Address Strobe A6 WE Read/Write Enable Vee Power Supply ( + 5V) VSS NC Ground AO A2 vee AB' 0102-1 0102-2 (Top View) No Connection (Bottom View) ~HITACHI 566 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM5116100L Series • BLOCK DIAGRAM 2S6~ 2560( memory cell array memory cell array 256k memory cell atray Sen, am IIObu, 256k memory cellanay 256k memory (ellanay Sen1t' amp, 1I0b.< 256k memory cell ,rr'Y 2561( memory CI!!'II array Sense m &I/Ob\!, 2561( memory cell IIfrllY Row decoder Seneam .&11 b. 256" memory (ell.".y Sense am driver 2561( memory cell .rr.V 2561( memory (ell array SemI!' amp. !fObu\ 256k mt'mOty cellanay 2561( memory cellatray 2561( memory (ell array 2561( memory cell .rray 2561( memory cell array 256k memory cell .rtay 256k m~mory (~II.tlay amp & 110 bu 256k m~mory (ell .n.y $~nU_'rrlP_ & "Obui 256k memory (ell.rray 256k memOry (ell .rr.y 256k memory (ell .rray 256k memOty cell .rr.y I Column decoder & driver 2S6k memOry (ell.tray Column decoder & driver l.n'Hmo I/Obu USk memory (ell.tr.y 1I0bu ~e"se mo 2S61( memory (ella".y 2S6k memOry (ell.ur.y Sens!' mD. 1I0b., 256k m~mory cell.rray Row decoder m 2S6k II b m~mo'y (ell ,".y ~en!te amp 8. 1/0 bus 2S61( memory cell .rr.y 2S6k memory (ell.".y 2S6k memory (ell .".y S'!nse'm tt 110 bu, 256k memory (ell,rray Sen,eam & I/Obu, 2S6k memory (ell .rray . 2S61( memory (ell arr.y I-- t- 2S6k memory (ell .rr.y . ~~ ~1 2S6k memory (ell,rray lS6k memory cell .rr.y U6k memory (ell .rray 2S6k memory cell Sense ama & 1/0 bv 2S6k memory cell .n.y \en,e 'l'"Ip & 110 bu, 2S6it memory cellllrtllY t 11"t- n m II 2S6k memOry (~II ,rray 2S61( memOry c~II'rray L---J Column address buffer I 2561( memory (ellarr.y amp 1/0 bus 256k memory (!'II .rr.y II 110 buffer 2561( memory cell array driver S~nse .m ~I I- Sense.'!!2. & "0 bUi 2S6" memory (ell array 256k memory ccllatr.y n I S.",. m. IIDb., U61( memory cell 'Hay & 256k memory (ell.,r.y n ~y 2S6k memory cell."ay 2S6k memory (ell .rr.y 2S6k memory cell,,,.y I-- ense.m .&1I0bu 256k memory (ellarr.y &lIObU1 ~ens~._m,,-----& 110 bu!t 156k memory cell atr.y I- Sense.m & IIObu, & 1/0 bus ~nse r-f+l &I/Obu\ 2561( memory (ellarr.y Sense .mD. & tlO bus ~nseam I- 5~"1~ /TID. JlQJ:w 2561( memory cell ,nay & 2S6k memory cell.rtay Sen) am I- 256" memory cell array 2561(. memory (ell.t,ay 2561( memOry cell "ray I- Sen1@'.~ & 1/0 bus 2561( memory cell IIr'ay Sen e am;:» "tlO bus 2561( memOly ceUarr.y L-r .rr~y Row address buffer ~ - J Address AO -A 11 0102-3 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 567 HM5116100L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS Value Unit Voltage on Any Pin Relative to Vss Parameter VT Symbol -1.0to + 7.0 V Supply Voltage Relative to Vss VCC -1.0to + 7.0 V Short Circuit Output Current lout 50 rnA Power Disspation PT 1.0 W Operating Temperature Topr Oto + 70 'C Storage Temperature Tstg - 55 to + 125 'C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70'C) Parameter Note: Min Typ Max Uuit Note Supply Voltage Vcc 4.5 5.0 5.5 V I Input High Voltage VIH 2.4 6.5 V I Input Low Voltage VIL -1.0 - O.S V I Symbol I. All voltage referenced to Vss. • DC Electrical Characteristics (TA Parameter Symbol Operating Current ICC! HM5116100-7 HM5116100-S Min Max Min Max Min Max 90 - SO - 70 - Standby Current = 0 to +70'C, Vee = 5V ±10%, Vss = OV) HM5116100-6 2 - 2 - 2 HM5116t00-1O Min - - Max Unit Test Condition 60 rnA tRC = Min 2 TTL Interface rnA RAS, CAS = VIR Dout = High-Z - 300 - 300 - 300 - 300 CMOS Interface RAS, CAS and WE > VCC - 0.2V, or :s 6.5V p.A Address and Din = Stable Dout = High-Z ICC2 Note 1,2 RASOnIy Refresh Current ICC3 - 90 - SO - 70 - 60 rnA tRC = Min Standby Current ICC5 - 5 - 5 - 5 - 5 RAS = VIR rnA CAS = VIL Dout = Enable CAS Before RAS Refresh Current ICC6 - 90 - SO - 70 - 60 rnA tRC = Min 4 Fast Page Mode Current ICC7 - 70 - 60 - 50 - 45 rnA tpc = Min 1,3 500 Standby: CMOS Interface CBR Refresh: tRC = 62.5 p.s p.A tRAS:S I p.s Address and Din = Stable Dout = High-Z Battery Back-up Operating Current (Standby with CBR Refresh) ICCIO Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 p.A OV:s Vin :$ 7V Output Leakage Current ILO -10 10 -10 10 -10 10 -10 10 p.A - 500 - 500 - 500 - OV::$ Vout ::$ 7V Dout = Disable .HITACHI 568 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300 2 1,4 5 HM5116100L Series + 70"C, Vee • DC Electrical Characteristics (TA = 0 to Parameter Symbol Output High Voltage VOH Output Low Voltage VOL Notes: I. 2. 3. 4. 5. HM5116100-6 HM5116100-7 = 5V ± 10%, Vss = OV) (continued) HM5116100·8 HM5116 100-10 Min Max Min Max Min Max Min Max 2.4 Vee 2.4 Vee 2.4 0.4 0 0.4 0 Vee 0.4 2.4 0 Vcc 0.4 0 Unit Test Condition Note V High lout = - 5 rnA V Low lout = 4.2 rnA Icc depends on output load condition when the device is selected, Icc max is specified at the output open condition. Address can be changed once or less while RAS = VIL. Address can be changed once or less while CAS = VIH. Clock voltages (RAS and CAS) must be applied simultaneously with or prior to applying supply voltage. VCC - 0.2V :s VIH :s 6.5V,OV :s VIL S 0.2V. • Capacitance (TA = 25'C, Vee = 5V ±10%) Parameter Notes: Symbol Typ Max Unit Note Input Capacitance (Address, Data·in) Cn - 5 pF 1 Input Capacitance (Clocks) CI2 7 pF 1 Output Capacitance (Data·out) Co - 7 pF 1,2 I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out . • AC Characteristics (TA = 0 to 70"C, Vee = 5V ±10%, Vss = 0V)1, 2, 16 Read, Write, Read-Modlfy-Wrlte and Refresh Cycles (Common Parameters) Parameter Symbol HM5116100·6 HM5116100-7 Min Min Max HM5116100-8 Max Min HM5116100-10 Max Max Max Unit Random Read or Write Cycle Time tRC 110 - 150 50 - 60 70 - ns 40 - 180 tRP - 130 RAS Precharge Time CAS Precharge Time tcp 10 - 10 - 10 - 10 - ns RAS Pulse Width tRAS 60 10000 70 10000 80 10000 100 10000 ns CAS Pulse Width tCAS 15 10000 18 10000 20 10000 25 10000 ns Row Address Setup Time tASR 0 - 0 - 0 - 0 Row Address Hold Time tRAH 10 10 - 10 - 10 0 0 15 - 0 15 - 15 - Note ns ns tASC 0 Column Address Hold Time leAH 15 - RAS to CAS Delay Time tRCD 20 45 20 52 20 60 20 75 ns 3 RAS to Column Address Delay Time tRAD 15 30 15 35 15 40 15 55 ns 4 18 - 20 - 25 70 - 80 100 - 5 5 - ns 5 - 3 30 3 30 3 30 ns Column Address Setup Time RAS Hold Time tRSH 15 CAS Hold Time tcsH 60 CAS to RAS Precharge Time tCRP 5 - tT 3 30 Transition Time (Rise and Fall) ns ns ns ns ns 5 Read Cycle Parameter Symbol HM5116 100-6 HM5116100·7 HM5116100·8 HM5116100·10 Min Max Min Max Max Min Max - 70 Min - 80 20 - 40 0 - 0 0 Access Time from RAS tRAc - 60 Access Time from CAS tCAC - 15 Access Time from Address tAA Read Command Setup Time ~CS 0 Read Command Hold Time to CAS tRCH 0 Read Command Hold Time to RAS tRRH 5 30 - 0 5 18 35 5 Unit Note 100 ns 6,7,17 25 ns 7,8,17 - 45 ns 7,9,17 - 0 ns - 0 - 5 ns 10 ns 10 @HITACHI Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 569 HM5116100L Series Read Cycle (continued) Parameter Symbol HM5lI6100-6 HMSII6100-7 HMSII6100-8 HMSII6100-1O Min Max Min Min Max Min Max 3S - 40 - 4S - 40 - 4S 0 - 0 - 0 3 - 3 - 3 - ns 3S - - 2S ns II Unit Note 12 Column Address to RAS Lead Time tRAL 30 Column Address to CAS Lead Time tCAL 30 CAS to Output in Low-Z tCLZ 0 Output Data Hold Time tOH 3 - Output Buffer Tum -off Time tOFF - IS Max 18 - 20 Unit Note ns ns ns Write Cycle Parameter Symbol HM5116100-6 Min Max HM5116100-7 Min Max HM5116100-8 HM5116100-1O Min Min Max ns Max 0 - 0 - 0 IS - 15 - 15 IS - IS 18 - 20 25 2S - Write Command Pulse Width twp IS Write Command to RAS Lead Time tRWL 15 - Write Command to CAS Lead Time tCWL IS - 18 - 20 - tos 0 0 - 0 - ns 13 tOH - 0 IS - IS - 15 - ns 13 Unit Note Write Command Setup Time twcs 0 Write Command Hold Time tWCH IS Data-in Setup Time Data-in Hold Time IS IS ns ns ns ns Read-Modify-Write Cycle Parameter Symbol HMS1I6100-6 HM5116100-7 HMS116100-8 HM5lI6100-1O Min Min Min Max Min 17S - 210 - ns 80 - 100 - ns 12 20 - 25 - ns 12 40 - 4S - ns 12 Unit Note Max Read-Modify-Write Cycle Time tRWC 130 - IS3 RAS to WE Delay Time tRWO 60 70 CAS to WE Delay Time tcwo 15 tAWO 30 - Column Address to WE Delay Time 18 3S Max - Max Refresh Cycle Parameter Symbol HM51161OO-6 HMS1I6100-7 HMS116100-8 HMSII61oo-1O Min Max Min Min Min Max Max Max CAS Setup Time (CBR Refresh Cycle) tCSR 10 - 10 - 10 - 10 - ns CAS Hold Time (CBR Refresh Cycle) tCHR 20 - 20 - 20 - 20 - ns WE Setup Time (CBR Refresh Cycle) tWRP 10 - 10 - 10 - 10 - ns WE Hold Time (CBR Refresh Cycle) tWRH 10 - 10 - 10 - 10 - ns RAS Precharge to CAS Hold Time tRPC 0 - 0 - 0 - 0 - ns Fast Page Mode Cycle Parameter Fast Page Mode Cycle Time Symbol HMSII6100-6 HMSII6100-7 HMS1I6100-8 HM5116100-1O Min Min Min Min Max - tpc 40 Fast Page Mode RAS Pulse Width tRASP - 100000 Access Time from CAS Precharge tCPA - 35 WE Delay Time from CAS Precharge tcpw 3S - RAS Hold Time from CAS Precharge tCPRH 3S 4S Max - 50 40 - 40 - 40 - - 100000 Max - 55 45 - 4S - SO 4S - 50 100000 Max - Note ns 100000 ns 14 50 ns IS, 17 - ns @HITACHI 570 Unit Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 ns HM5116100L Series Fast Page Mode Read-Modify-Write Cycle Parameter Symbol Fast Page Mode Read-ModifyWrite Cycle Time tPRWC HM5116100-6 HM5116 100-7 Min Max Min Max Min Max Min Max 60 - 68 - 75 - 85 - HM5116100-8 HM5116100-1O Unit Note ns Test Mode Cycle Symbol Parameter HM5116100-6 HM5116100-7 Max Min Min Max HM5116100-8 HM5116100-1O Min Max Min Max - 10 - Test Mode WE Setup Time twTS 10 - 10 - 10 Test Mode WE Hold Time tWTH 10 - 10 - 10 10 Unit Note ns ns Counter Test Cycle Parameter CAS Precharge Time in Counter Test Cycle Symbol tCPT Refresh (TJ = 85·C, Vee Parameter = HM5116100-6 HM5116100-7 Min Max Min TBD - TBD - HM5116100-8 HM5116100-IO Min Min Max TBD - TBD Max - Unit Note ns 5V ±10%) Symbol Refresh Period Notes: Max Max Unit Note 256 ms 4096 Cycles !. AC measurements assume tT = 5 ns. 2. An initial pause of 100 ,,"S is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS only refresh or CAS before RAS refresh). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between Vrn (min) and VIL (max). 6. Assumes that tRcD < tRcD (max) and tRAD < tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2TTL loads and 100 pF. 8. Assumes that tRCD O!: tRCD (max) and tRAD :S tRAD (max). 9. Assumes that tRCD :S tRCD (max) and tRAD O!: tRAD (max). 10. Either tRcH or tRRH must be satisfied for a read cycle. I!. !oFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 12. twcs, tRWD, tCWD, tAWD and !cpw are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if twcs O!: twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD O!: tRWD (min), tCWD ~ tCWD (min) and tAWD O!: tAWD (min), or!cWD ~ tCWD (min), tAwD ~ tAwD (min), and !cPW ~ !cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 13. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or readmodify-write cycles. 14. tRASP defmes RAS pulse width in fast page mode cycles. 15. Access time is determined by the longer of tAA or tCAC or tCPA' 16. Test mode operation specified in this data sheet is 16 bits test function controlled by compression addresses - CAO, CAl, CAlO and CAl!. This test mode operation can be performed by WE and CAS before RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of sixteen test bits accord with each other, the state of the output data is high level. When the state of test bits do not accord with each other, the state of the output data is low level. Data output pin is D out and data input pin is Dm. If any refresh cycle is occurred, the test mode is reset. 17. In a test mode read cycle, the value of tRAC, tAA, !cAC and !cPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. • HITACHI Hitachi America, Ltd. 0 Hitachi Plaza 0 2000 Sierra Point Pkwy. 0 Brisbane, CA 94005-1819 0 (415) 589-8300 571 HM5116100L Series • TIMING WAVEFORMS • Read Cycle Address Dout Dout • ~ : Don't care 0102-4 @HITACHI 572 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005· 1819· (415) 589·8300 HM5116100L Series • Early Write Cycle Address Din OPEN" Dout '~ : Don't care ,. twcs s: twcs (min) 0102-5 • HITACHI Hitachi America, Ltd.• Hitachi Plaza .2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589·8300 573 HM5116100L Series • Delayed Write Cycle Address Din Dout • ~ : Don't care 0102-6 @HITACHI 574 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM5116100L Series • Read-Modify-Write Cycle Address Din Dout • ~ : Don't care 0102-7 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 575 HM5116100L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle Address OPEN Dout • ... •• WE : Don't care ~ : Don't care Refresh address: AO - All (RAO - RA 11) 0102-8 • 576 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM5116100L Series • CAS Before RAS Refresh Cycle Address Dout ~ : Don't care 0102-9 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300 577 HM5116100L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Hidden Refresh Cycle Address Dout * ~ : Don't care 0102-10 ~HITACHI 578 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HM5116100L Series • Fast Page Mode Read Cycle Address Dout • ~ : Don't care 0102-11 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 579 HM5116100L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Early Write Cycle Address Din Dout OPEN" • ~ : Don't care •• twcs;;;; twcs (min) 0102-12 @HITACHI 580 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 HM5116100L Series • Fast Page Mode Delayed Write Cycle Address Din Dout * ~ : Don't care 0102-13 @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 581 HM5116100L Series • Fast Page Mode Read-Modify-Write Cycle Address Din Dout • ~ : Don't care 0102-14 ~HITACHI 582 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM5116100L Series • Test Mode Cycle * , *** • •• CBR or RAS only refresh ~ : Don't care ••• Address, Din: Don't care 0102-15 • Test Mode Set Cycle Address Dout OPEN • ~ : Don't care 0102-16 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 583 HM5116100L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Test Mode Reset Cycle CAS Before RAS Refresh Cycle Address OPEN Dout * ~ : Don't care 0102-17 RAS Only Refresh Cycle Address Dout OPEN • •• Refresh address AO-A 11 (RAO-RA 11) ~ : Don't care 0102-16 @HITACHI 584 Hitachi America, Ltd, • Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 HM5116100L Series CAS Before RAS Refresh Counter Check Cycle (Read) Address Din Dout • ~ : Don't care 0102-19 @HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 585 HM5116100L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CAS Before RAS Refresh Counter Check Cycle (Write) Address Din Dout • ~ : Don't care 0102-20 $ 586 HITACHI Hitachi America, Ltd. 0Hitachi Plaza 02000 Sierra Point Pkwy. 08risbane, CA 94005-1819 0(415) 589-8300 HM5116400 Series Product Preview 4,194,304-Word x 4-Bit Dynamic Random Access Memory • DESCRIPTION HM5116400J Series The Hitachi HM5116400 is a CMOS dynamic RAM organized 4,194,304 words x 4 bits. It employs the most advanced CMOS technology for high performance and low power. The HM5116400 offers Fast Page Mode as a high speed access mode. • FEATURES • Single 5V (± 10%) • High Speed Access Time ............................ 60 ns170 ns/80 ns/100 ns (max) • Low Power Dissipation Active Mode .................... 495 mW/440 mW/385 mW/330 mW (max) Standby Mode ............................................. 11 mW (max) • Fast Page Mode Capability • Long Refresh Period 4096 Refresh Cycles ............................................ (64 ms) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh 3DCP24D (CP-24D) HM5116400Z Series 30ZP24 • ORDERING INFORMATION (ZP-24) Part No. Access Time Package HM51164OOJ·6 HM51164OOJ·7 HM51164OOJ-8 HM51164OOJ-1O 60ns 70ns 80ns lOOns 400 mil 24-pin PlasticSOJ (CP-24D) HM5116400Z-6 HM5I 16400Z-7 HM5116400Z-8 HM5116400Z-1O 60ns 70ns 80ns lOOns 475 mi124-pin PIasticZIP (ZP-24) • PIN OUT HM5116400J Series HM5116400Z Series 1 A9 1/03 1/04 Vss Vee 1101 1/02 • PIN DESCRIPTION WE Pin Name Function Ao-Al1 Address Input Ao-Al1 Refresh Address Input I/OO-I/04 Data Input/Data Output RAS Row Address Strobe CAS Column Address Strobe WE Write Enable OE Output Enable Vee Vss Ground NC No Connection All 11 12 AO 13 Al0 15 Al A2 AO RAS 17 A3 Al 19 V,, A2 A4 20 AS A3 A6 22 vee A7 AS 24 Power(+ 5V) 0101-1 (Top View) $ 0101-2 (Bottom View) HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 587 HM5116400 Series • BLOCK DIAGRAM 256" memory cella"l., 2561c memorycellar,.y Sen~ i mD ,."","",-6110"'" ""0 bus 256k memOly cell .".y 2S6k m~o'y (ell I"." Sense m II/Obu, 256k memory cell."• ., · .. 256t memory cella"a., Sens. amo .. 1/0 bus 256k memo,y cell .,tly Row decoder ·. 5fmll!' Irno .. 110 bus -~ 2S61r. mernoty cell."ay •••"' ...... lIObus 256k tMmOly (ellarr.y 256k memory (ella"• ., 2S6k mel'nOfy cellarra., •• bu ... • 2S6k memoty cell array 2S6it memory cellarr• ., 256k memory c~1 array _5.mu",.~IIObl!. . Senw .•1'JI I 256k memory cetl.".y ZS6k memory ceU .".,. 25611. memoty cellirr., 156k memory cell.rr., .......... 110 .... Z56k memory ceU .rr.., , ••"' .... & 110 bus Z56k memory cell."., I Column decoder & driver Column decoder & driver ·. II 156k mtlftOlyceU .rray 156k memory O\ 256k memory cell.".y 256k memory (ell.tr.y S.n H 256k memory cellatt.y S.n••• mD .,,0 bu. I Row address buffer j Address AO -A 11 I~ l~ If If If I AO-Al1 0103-3 ~HITACHI 610 Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 HM5116400L Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol VT -1.0to Supply Voltage Relative to Vss Vcc -1.0to Short Circuit Output Current lout 50 + 7.0 + 7.0 V V rnA 1.0 Power Dissipation PT Operating Temperature Topr Storage Temperature Tstg - • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter Unit Value Voltage on Any Pin Relative to VSS 0 to = W oto + 70 55 to + 125 °C °C + 70°C) Symbol Min Typ Max Unit Supply Voltage Vcc 4.5 5.0 5.5 V I Input High Voltage VIH 2.4 6.5 V I Input Low Voltage VIL -1.0 - O.S V I Note: Note 1. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to Parameter Operating Current Symbol ICCI = 5V ±10%, Vss = OV) HM5116400-7 Min Max Min Max Min Max 90 - SO - 70 - Standby Current + 70°C, Vee HM5116400-6 2 - 2 HM5116400-S HM5116400-1O - 2 Min - - Max rnA tRC = Min 2 TTL Interface rnA RAS, CAS = VIH Dout = High-Z - 300 - 300 - 300 - 300 CMOS Interface, RAS, CASandWE> VCC - 0.2V or S 6.5V J.'A Address and Din = stable Dout = High-Z - 90 - SO - 70 - 60 rnA tRC = Min 2 Standby Current ICC5 - 5 - 5 - 5 - 5 RAS = VIH rnA CAS = VIL Dout = Enable CAS Before RAS Refresh Current ICC6 - 90 - SO - 70 - 60 rnA tRC = Min Fast Page Mode Current ICC7 - 70 - 60 - 50 - 45 rnA tpc 500 Standby: CMOS Interface CBR Refresh: tRC = 62.5 J.'s J.'A tRAS S I J.'s Address and Din = Stable Dout = High-Z = 1,3 Min ICC 10 Input Leakage Current ILl -to 10 -to 10 -10 10 -10 10 J.'A OV S Yin S 7V Output Leakage Current ILO -to 10 -10 10 -10 to -to 10 OVSVout S7V J.'A D out = Disable Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V High lout = - 5 rnA Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 V Low lout Notes: 1. 2. 3. 4. 5. 500 - 500 - 500 - = 1,4 4 Battery Back Up Operating Current (Standby with CBR Refresh) - Note 1,2 60 ICC2 RAS Only Refresh Current ICC3 Test Conditions Unit 5 4.2 rnA Icc depends on output load condition when the device is selected, Icc max is specified at the output open condition. Address can be changed once or less while RAS = VIL. Address can be changed once or less while CAS = V IH. Clock voltages (RAS and CAS) must be applied simultaneously with or prior to applying supply voltage. VCC - 0.2V S VIH S 6.5V,OV S VIL S 0.2V. ~HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 611 HM5116400L Series • Capacitance (TA = 25'C, Vee = 5V ±10%) Parameter Symbol Input Capacitance (Address) CII Input Capacitance (Clocks) CI2 Output Capacitance (Data-in, Data-out) Co Notes: Typ Max Unit Note - 5 pF I 7 pF I 10 pF 1,2 I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIR to disable D ollt . • AC Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss = OV)1, 2, 3, 19, 20 Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Symbol HM5116400-6 HM5116400-7 HM5116400-8 Min Min Max Min - 150 - 180 - ns 60 - 70 - ns - ns Max Random Read or Write Cycle Time tRC 110 - 130 RAS Precharge Time tRP 40 - 50 CAS Precharge Time tcp 10 - RAS Pulse Width 10 10 tRAS 60 10000 70 CAS Pulse Width tCAS 15 10000 18 Row Address Setup Time tASR a - a - a Row Address Hold Time tRAH 10 - 10 - Column Address Setup Time tASC a - a Column Address Hold Time tCAH 15 - 15 - RAS to CAS Delay Time tRCD 20 45 20 52 RAS to Column Address Delay Time tRAD 15 30 15 35 18 18 - 0 - a 3 tRSH 15 CAS Hold Time tCSH 60 CAS to RAS Precharge Time tCRP 5 OE to Din Delay Time tOED 15 OE Delay Time from Dm tDZO CAS Delay Time from Din tDZC a a - Transition Time (Rise and Fall) tT 3 30 RAS Hold Time HM5116400-1O Max Min 10 - Unit Max 10000 80 10000 100 10000 ns 10000 20 10000 25 10000 ns 70 5 Note a - ns 10 - 10 - ns a - a - ns 15 - 15 - ns 20 60 20 75 ns 4 15 40 15 55 ns 5 20 - 25 ns 80 - 100 5 - 5 20 25 - a a - 0 - 30 3 30 3 30 a ns ns ns 6 ns 7 ns 7 ns 8 Read Cycle Parameter Symbol HM5116400-6 HM5116400-7 HM51164oo-8 Min Max Min Max Min HM51164oo-1O Max Min Max Unit Note Access Time from RAS tRAC - 60 - 70 - 80 - 100 ns 9, 10,21 Access Time from CAS tCAC - 15 - 18 20 - 25 ns 10, 11,21 Access Time from Address tAA - 30 - 35 Access Time from OE tOEA - 15 - 18 - - Read Command Setup Time tRCS Read Command Hold Time to CAS tRCH a a Read Command Hold Time to RAS tRRH 5 Column Address to RAS Lead Time tRAL 30 Column Address to CAS Lead Time tCAL CAS to Output in Low-Z tCLZ Output Data Hold Time Output Data Hold Time from OE 40 - 45 ns 10, 12,21 20 - 25 ns 10,21 - ns ns 13 ns 13 - - a a - a a - 5 - 5 35 - 40 30 - 35 - 40 a - a loH 3 3 tOHO 3 - - 3 - Output Buffer Turn-off Time tOFF 15 a 18 - 20 Output Buffer Turn-off to OE tOEZ - 15 - 18 - CAS to Din Delay Time tCDD 15 - 18 - 20 - a a 45 a - 0 - 3 - 3 - ns 3 - 3 - ns - 25 ns 14 20 - 25 ns 14 - 25 - ns 6 5 45 @HITACHI 612 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 ns ns ns HM5116400L Series Write Cycle Parameter Symbol HM5116400-6 HM5116400-7 HM5116400-S Min Max Min Max Min - 0 IS - IS - 15 - 15 IS - 20 - Write Command Setup Time twcs 0 Write Command Hold Time tWCH IS Write Command Pulse Width twp 15 Write Command to RAS Lead Time tRWL 15 Write Command to CAS Lead Time tcwL 15 Data-in Setup Time tDS 0 tDH 15 Data-in Hold Time IS 0 15 Max HM5116400-1O Min Max Unit Note IS 0 - ns IS - ns - IS - ns - 25 - ns 20 - 25 ns 0 - 0 - 0 IS 15 ns 16 ns 16 Unit Note Read-Modify-Write Cycle Parameter Symbol HM5116400-6 HM5116400-7 HM5116400-S Min Max Min Min - 176 Read-Modify-Write Cycle Time tRWC 150 RAS to WE Delay Time tRWD SO CAS to WE Delay Time tCWD 35 Column Address to WE Delay Time tAWD 50 OE Hold Time from WE tOEH IS Max - 93 41 5S IS Max HM5116400-1O Min Max 200 - 245 - ns 105 - 135 - ns 15 45 - 60 - ns 15 65 - SO ns IS 20 - 25 - ns Refresh Cycle Parameter Symbol HM5116400-6 HM5116400-7 HM5116400-S Min Min Min Max Max Max HM5116400-1O Min Max Unit CAS Setup Time (CBR Refresh Cycle) tCSR 10 - 10 - 10 - 10 - ns CAS Hold Time (CBR Refresh Cycle) tCHR 20 - 20 - 20 - 20 - ns WE Setup Time (CBR Refresh Cycle) tWRP 10 - 10 - 10 - 10 - ns WE Hold Time (CBR Refresh Cycle) tWRH 10 - 10 - 10 - 10 - ns RAS Precharge to CAS Hold Time tRPC 0 - 0 - 0 - 0 - ns Note Fast Page Mode Cycle Parameter Symbol Fast Page Mode Cycle Time HM5116400-6 HM5116400-7 HM5116400-S Min Min Min tpc 40 Fast Page Mode RAS Pulse Width tRASP Access Time from CAS Precharge tCPA - WE Delay Time from CAS Precharge tcpw 55 RAS Hold Time from CAS Precharge tCPRH 35 Max Max - 45 - Max - 50 - 100000 - 100000 35 - 40 - 63 - 70 40 - 45 HM5116400-10 Min 55 Max - Unit Note ns 100000 - 100000 ns 17 45 - 50 ns IS,21 - 85 - ns 50 - ns Fast Page Mode Read-Modify-Write Cycle Parameter Symbol Fast Page Mode Read-ModifyWrite Cycle Time tpRWC HM5116400-6 HM5116400-7 Min Max Min SO - 91 Max - HM5116400-S HM5116400-1O Min Max Min 100 - 110 Max - Unit Note ns ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 613 HM5116400L Series Test Mode Cycle Parameter Symbol HM5Il6400-6 HM5116400-7 HM5116400-S HM5116400-1O Min Max Min Min Min - 10 Test Mode WE Setup Time tWTS 10 Test Mode WE Hold Time tWTH 10 Max - 10 Max - 10 10 10 10 Unit Max - Note ns ns Counter Test Cycle Parameter Symbol CAS Precharge Time in Counter Test Cycle tCPT HM5116400-6 Min TBD Max - HM5116400-1O HM5116400-7 HM5116400-S Min Min Max Min TBD - TBD TBD Max - Unit Max - Note ns Refresh (TJ = 85°C, Vee = 5V ± 10%) Parameter Refresh Period Notes: Symbol Max Unit Note 256 ms 4096 Cycles I. AC measurements assume tT = 5 ns. 2. An initial pause of 100 !,-S is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS only refresh or CAS before RAS refresh). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles are required. 3. Only row address is indispensable ou address A 10 and A I 1. 4. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 5. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 6. Either toDD or TCDD must be satisfied. 7. Either tDZO or TDZC must be satisfied. S. VIR (min) and VIL (max) are reference levels for measuring timing of inpnt signals. Also, transition times are measured between VIR (min) and VIL (max). 9. Assumes that tRCD < tRCD (max) and tRAD < tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 10. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. II. Assumes that tRCD ~ tRCD (max) and tRAD :S tRAD (max). 12. Assumes that tRCD :S tRCD (max) and tRAD ~ tRAD (max). 13. Either tRCH or tRRH must be satisfied for a read cycle. 14. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 15. twcs, tRWD, tCWD, tAWD and tcpw are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if twcs ~ twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRwD ~ tRwD (min), tCWD ~ tCWD (min), tAWD ~ tAWD (min), or tCWD ~ tCWD (min), tA WD ~ tA WD (min) and tcpw ~ tcpw (min) the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 16. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or readmodify-write cycles. 17. tRASP defines RAS pulse width in fast page mode cycles. IS. Access time is determined by the longer of tAA or teAC or tCPA' 19. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 20. Test mode operation specified in this data sheet is 16 bits test function controlled by compression addresses - CAO and CAL This test mode operation can be performed by WE and CAS before RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of four test bits on each I/O accord with each other, the state of the output data on the I/O is high level. When the state of four test bits on the I/O do not accord with each other, the state of the output data on the I/O is low level. Data input and output pins are I/O-I to 1/0-4. If any refresh cycle is occurred, the test mode is reset. 21. In a test mode read cycle, the value of tRAC, tAA, tCAC and tePA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. ~HITACHI 614 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM5116400L Series • TIMING WAVEFORMS • Read Cycle Address Din Dout • ~ : Don't care 0103-4 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 615 HM5116400L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Early Write Cycle Address Din Dout OPEN** OE : Don't care ... ~ : Don't care twcs;;;: twcs (min) 0103-5 .HITACHI 616 Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM5116400L Series • Delayed Write Cycle CAS Address WE Din Dout • ~ : Don't care 0103-6 eHITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 617 HM5116400L Series • Read-Modlfy-Write Cycle Address Din Dout • ~ : Don't care 0103-7 $ 618 HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM5116400L Series • RAS Only Refresh Cycle Address OPEN Dout * OE,WE : Don't care ** ~ : Don't care *** Refresh address: AO - All (RAO - RA 11) 0103-8 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 619 HM5116400L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • CAS Before RAS Refresh Cycle Address Dout ** OE : Don't care ~ : Don't care 0103-9 _HITACHI 620 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM5116400L Series • Hidden Refresh Cycle Address Din Dout • ~ : Don't care 0103-10 @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 621 HM5116400L Series • Fast Page Mode Read Cycle Address Din Dout • ~ : Don't care 0103-11 ~HITACHI 622 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM5116400L Series • Fast Page Mode Early Write Cycle Address Din OPEN** Dout OE : Don't care ** ~: Don't care twcs,,=twcs (min) 0103-12 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 623 HM5116400L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Delayed Write Cycle Address Din Dout Invalod Dout Invalid Dout Invalod Dout * ~ : Don't care 0103-13 • 624 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 HM5116400L Series • Fast Page Mode Read-Modify-Write Cycle Address Din Dout Dout 1 Dout2 DoutN • ~ : Don't care 0103-14 eHITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 625 HM5116400L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Test Mode Cycle * , *** * CBR or m only refresh ** ~ : Don't care *** Address, Din, OE : Don't care 0103-15 • Test Mode Set Cycle Address Dout OPEN * ~ : Don't care 0103-16 • 626 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1 819 • (415) 589-8300 HM5116400L Series • Test Mode Reset Cycle CAS Before RAS Refresh Counter Cycle OPEN Dout * ~ : Don't care 0103-17 • RAS Only Refresh Cycle tCRP Address Dout OPEN * Refresh address AO - A 11 (RAO-RA 11) ~ : Don't care 0103-18 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 627 HM5116400L Series • CAS Before RAS Refresh Counter Check Cycle (Read) Address Din Dout 0103-19 ~HITACHI 628 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM5116400L Series • CAS Before RAS Refresh Counter Check Cycle (Write) Address ~-~~--~ Din Dout • ~ : Don't care 0103-20 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 629 .HITACHI 630 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 Section 3 High Speed BiCM OS Dynamic RAM $HITACHI® $ 632 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM571000 Series 1,048,576-Word x 1-Bit High Speed Dynamic Random Access Memory • DESCRIPTION HM571000JP Series The Hitachi HM571000 is a super high speed dynamic RAM organized 1,048,576-word xl-bit. HM571 000 have realized higher density, higher performance and various functions by employing 1.3 ,...m Bi-CMOS technology and some new BiCMOS circuit design technologies. The HM571000 offers 8 bits static column mode as a high speed access mode. • FEATURES :JDCP28DN (CP-28DN) • Single 5V (± 10%) for HM571000JP/ZP-40/45 5V (±5%) for HM571000JP/ZP-35R • High Speed Access Time ........•.......................... 35 ns/40 ns/45 ns (max) • 512 Refresh Cycles .................................................. (4 ms) HM571000ZP Series • 2 Variations of Refresh CE Refresh Automatic Refresh • 8 Bits Static Column Mode 3DZP28 (ZP-28) • ORDERING INFORMATION Part No. Access Time Package HM571000JP-35R HM571000JP40 HM571000JP-45 35 ns 40ns 45ns 300 mi128-pin Plastic SOJ (CP-28DN) HM571000zP-35'1 HM571000zP40'1 HM571000ZP-45'1 35 ns 40ns 45ns 400 mi128-pin Plastic ZIP (ZP-28) Note: 'I. ZIP type products are preliminary. • PIN DESCRIPTION Pin Name Ao- A9 Function Address Input for CERefresh A9-A16 Address Input A17-AI9 Address Input for Static Column Mode CE Chip Enable OE Output Enable WE Read/Write Enable Din Data-in Dout RF Data-out • PIN OUT HM571000JP Series HM571000ZP Series CE WE Din A10 A9 A18 2 4 6 8 Vss 10 _\1 ::.~ AS A2 Al AO AS A7 A3 A8 RF Ci 14 16 18 20 = =.- A13 24 All 26 A9 28 1 3 RF 5 Dout A19 A17 AO A4 A6 A2 Vee 21 23 2S 27 A16 A14 A12 Al0 = = 0080-2 0080-1 (Top View) Oi 7 --"- 9 l.l 13 lS 17 19 = =-= = A1S 22 OE WE = (Bottom View) Refresh Control Vee Power(+5V) Vss Ground @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 633 HM571000 Series • ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Voltage on Any Pin Relative to VSS VT -1.0to +7.0 V Supply Voltage Relative to Vss Vee -1.0to + 7.0 V Short Circuit Output Current lOS 50 rnA Power Dissipation PT Operating Temperature Storage Temperature Symbol 0.8 W Topr Oto + 70 'C Tstg - 55 to + 125 'C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter Supply Voltage I I = 0 to + 70'C) Symbol -35R Min Vee -40/-45 Max VIR 2.4 Input Low Voltage VIL -1.0 Unit Note V I 6.5 V 1,3 0.8 V 1,2 5.25 5.0 4.50 Input High Voltage Notes: Typ 4.75 5.50 - I. All voltage referenced to Vss. 2. The device will withstand undershoots to the - 2V level with a maximum pulse width of 20 ns at the - 1.5V level. (See Figure I.) VIH -1.0 V -1.5 V r---; ~ -2_0 V 20 ns (max) 0080-3 Figure 1. Undershoot of Input Voltage 3. The VIR level of OE shall be lower than Vee + 0.5V. • DC Electrical Characteristics (TA = 0 to + 70'C, Vss = ov) (Vee = 5V ± 10% for HM571000JP-40/45) (Vee = 5V ±5'10 for HM571000JP-35R) Parameter Normal Operating Current Symbol HM571000-35R HM57 1000-40 Min Min Max Max HM571000-45 Min Max Unit Test Conditions Note leeA See Figure 2 rnA I Refresh Current leeR See Figure 2 rnA I Standby Current Ices Input Leakage Current ILl -10 5 10 -10 5 10 -10 5 rnA 10 p,A OV< Yin < 7V OV < Vout < 7V, Dout = Disable Output Leakage Current lLO -10 10 -10 10 -10 10 p,A Output High Voltage VOH 2.4 Vee 2.4 Vee 2.4 Vee V High lout = - 4 rnA Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 V Low lout = 8 rnA Notes: I. IcC depends on output loading condition when the device is selected, ICC max is specified at the output open condition. 2. The VIN level ofOE that is ILl test condition ofOE must be lower than Vee + 0.5V. ~HITACHI 634 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 2 HM571000 Series 1000 vcc.s.O. Room limp. <" oS a:u .!! 100 tLZ> tWZ) 7.b-. Including seop & jig 0080-6 Figure 4. Output Load Figure 3. Input Pulse $ HITACHI Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 635 HM571000 Series Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter HM571ooo-35R Symbol Min ReadIW rite Cycle Time tcc 75 CE Pulse Width 35 CE Precharge Time teE tcp Address Setup Time tAS 0 Address Hold Time tAH Transition Time (Rise and Fall) tT Refresh Period tREF Min - Max Min - 90 85 5000 40 39 5 - I 10 - 4 34 HM571OOO-45 HM571OOO-40 Max 5000 45 Unit Max - ns 5000 ns 39 - ns 0 - ns 5 - 5 - ns I 10 I 10 ns 4 - 4 ms 0 - Note Read Cycle Parameter Symbol HM571000-35R HM57 1000-40 HM571000-45 Unit Min Max Min Max Min Max 35 - 40 ns 30 ns 25 - 45 25 25 ns 0 - 0 - ns 5 - 5 ns 5 - 5 - Access Time from CE tACS Address Access Time tAA Access Time from OE tOAC - Setup Time on Read tRS 0 Hold Time on Read tRH 5 OE Setup Time tOES 5 - OE Enable to Output in Low-Z tLz 0 - 0 - 0 - OE Disable to Output in High-Z tHZ - 15 - 20 - 20 ns Output Hold Time from Address tAoH 3 - 3 - 3 - ns - 0 - 0 - ns 10 10 - ns Output Hold Time from CE tCOH 0 CE to OE Precharge Time tcop 10 20 30 Note ns ns Write Cycle Parameter Symbol HM571000-35R HM571000-4O HM571000-45 Min Max Min Max Mm Max 30 45 - - 20 Data Setup Time tDW 20 tDH 5 - 25 Data Hold Time Setup Time on Early Write tES 5 - 5 WE Pulse Width twp 25 30 Write Hold Time from CE tWH 35 - 40 - WE Enable to Output in High-Z twz - 15 - 20 5 5 5 35 Unit @HITACHI 636 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 ns ns ns ns ns ns Note HM571000 Series Read-Modify-Write Cycle Parameter Symbol WE Delay Time from CE tCWD HM571000-35R I I Min 35 HM571000-40 Max - Min 40 I I HM571000-45 Max Min - 45 I I Max Unit - Note ns Refresh Cycle Parameter Symbol HM571000-35R Min Max - RF Setup Time tFS 5 RF Hold Time tFH 15 Mode Selection Setup Time tMS 0 Mode Selection Hold Time tMH IS Setup Time on CE Refresh tCRS IS HM57 1000-40 Min Max 5 - IS 0 20 20 HM571000-45 Min Max Unit - ns 15 0 - ns 20 - ns 5 20 Note ns ns Static Column Mode Cycle Parameter Static Column Address Setup Time Symbol HM571000-35R Min Max HM571000-40 HM57 1000-45 Min Max Min Max Unit tASZ 20 - 25 - 25 - ns Address Setup Time to WE tws 0 - 0 - 0 ns Address Hold Time from WE tWR 0 - 0 - 0 - Notes: Note ns 1. If tOES> tOES (min) and OE is held at low level, DOU! will be valid until the next negative transition of CEo 2. 3. 4. 5. 6. 7. S. 9. 10. II. 12. Both tWH and twp must be satisified for a delayed write cycle. If tcop < tcop (min), Dou! cannot be guaranteed to be in high impedance. If the negative transition of OE occurs before that of CE, tLZ is controlled by CEo twp and tDW are specified by the positive transition of CE or WE whichever occurs earlier. When WE goes low, Dou! becomes high impedance and is held in this condition to the next cycle. If the negative transition of WE occurs before that of CE, Dou! is controlled by CEo twz defines the time at which tbe output achieves the open circuit condition. If tES > tES (min), the cycle is early write and DOU! is in high impedance. In static column mode cycles, read operation cannot be performed after write operation. Both tAH and tWR must be satisified for a write cycle. tHZ defines the time at which the output achieves the open circuit condition. An initial pause of 100 ",S is required after power-up, then execute at least eight CE refresh cycles. In static column mode cycle, there must not be any invalid address inputs for static column mode (A17-A19) which are less than tAA' ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 637 HM571000 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read/Read Cycle tCC tCE tCE tCP AO A16 AI7 .A19 tACS tOAC tRH tCOP HilZh-Z Dout * ** Dtn; Don't care ~; Don't care 0080-7 ~HITACHI 638 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HM571000 Series • Read/Early Write Cycle tce tce AO A16 A17 A19 Din Ddut· * ~ Jan't care 0080-8 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 639 HM571000 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Read/Delayed Write Cycle tee tee AO A16 A17 A19 Din Dout * ~ Don't care 0080-9 ~HITACHI 640 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM571000 Series • Read/Read Cycle (OE = Vld tCC teE ~7!/ if AO A16 tAR A17 1 A19 WE tACS tRR tRS OE VIL teOH *1 *4 High-Z Dout * ** Din: Don't care ~: Don't care 0080-10 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 641 HM571000 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Read/Early Write Cycle (OE = VIL> tee tee AO AI6 AI7 A19 Din Cout * ~ Don't care 0080-11 ~HITACHI 642 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM571000 Series • Read/Delayed Write Cycle (OE = VIL> tee tee AO A16 A17 A19 tRS 1oe-_--:;~tWP* 5 Din Dout * ~ Don't care 0080-12 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 643 HM571000 Series • Read-Modify-Write Cycle AO A16 At7 At9 Din Dout * E2Z2l: Don't care 0080-13 @HITACHI 644 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM571000 Series • Automatic Refresh Cycle tee AO At9 P.igh-Z Dout * AO - At9: ** OE, Din *** ~ Don't care Don't care Don't care 0080-14 $ HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 645 HM571000 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • CE Refresh tCC tCE teE tCP AO AS A9A19 Dout High-Z * Din : ** EZZ2l: Don't care Don't care 0080-15 ~HITACHI 646 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM571000 Series • Static Column Mode Read Cycle AO A16 Al7 Al9 WE tRR OE High-Z Dout * Din: ** ITZZI Don't care Don't care 0080-16 • HITACHI Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819· (415) 589-8300 647 HM571000 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Static Column Mode Read Cycle (OE = Vld tFH AO A16 A17 A19 tACS tLZ*4 Dout Hi h-Z *Din: Don't care ** ~ Don't care 0080-17 ~HITACHI 648 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM571000 Series • Static Column Mode Write Cycle '8 (1st Cycle = Early Write Cycle) AO Al6 Al7 Al9 Din Dout *~ Don't care 0060-18 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 649 HM571000 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Static Column Mode Write Cycle *8 (1st Cycle = Delayed Write Cycle) AO A16 A17 A19 Din Dout * ~ Don't care 0080-19 ~HITACHI 650 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM574256 Series 262,144-Word x 4-Bit High Speed Dynamic Random Access Memory • DESCRIPTION HM574256JP Series The Hitachi HM574256 is a super high speed dynamic RAM organized 262,144-word x 4-bit. HM574256 has realized higher density, higher performance and various functions by employing 1.3 I'm Bi-CMOS technology and some new Bi-CMOS circuit design technologies. The HM574256 offers 2-bit static column mode as a high speed access mode. • FEATURES 3DCP28DN (CP-28DN) • Single 5V (± 10%) for HM574256JP/ZP-40/45 5V (±5%) for HM574256JP/ZP-35R • High Speed Access Time ................................... 35 ns/40 ns/45 ns (max) • 512 Refresh Cycles .................................................. (4 ms) • 2 Variations of Refresh CE Refresh Automatic Refresh • 2 Bits Static Column Mode HM574256ZP Series 3DZP28 (ZP-28) • PIN OUT • ORDERING INFORMATION Part No. Access Time Package HM5742561P-35R HM5742561P-40 HM5742561P-45 35 ns 40ns 45 ns 300 mil 28-pin Plastic SOJ (CP-28DN) HM574256ZP-35R HM574256ZP-40 HM574256ZP-45 35 ns 40ns 45 ns 400 mil 28-pin Plastic ZIP (ZP-28) HM574256JP Series Note Cf WE 1 1 1 Note: I. ZIP type products are preliminary. A9 A1 AS A7 Al Ao-Ag Address Input for CE Refresh A9-A16 Address Input if a DE WE A\7 Address Input for Static Column Mode CE Chip Enable OE Output Enable WE ReadlWrite Enable 1/0 0-1/04 Data-in/Data-out RF Refresh Control Vee Vss Ground Q~ Vss 10 A3 AO Function ~ 4 1/02 6 r/04 8 Ala A2 • PIN DESCRIPTION Pin Name HM574256ZP Series 12 14 16 A3 18 AS A15 A13 All 20 22 24 26 A9 28 - 1 3 RF DE 5 7 9 r/01 1/01 A17 AO A4 A6 A2 11 13 15 17 19 21 23 25 27 Vcc A16 A14 A12 A10 0082-2 0062-1 (Top View) (Bottom View) Power (+ 5V) ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 651 HM574256 Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on Any Pin Relative to Vss VT -1.0to +7.0 V Supply Voltage Relative to Vss Vcc -1.0to + 7.0 V Short Circuit Output Current lOS 50 rnA Power Dissipation PT 0.8 W ·C ·C Operating Temperature Topr Oto + 70 Storage Temperature T stg - 55 to + 125 • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70°C) Parameter Supply Voltage I I Symbol Typ 4.75 Vcc -401-45 Input High Voltage Input Low Voltage Notes: Min -35R Max 5.25 5.0 4.50 Unit Note V I 5.50 VIR 2.4 - 6.5 V 1,3 VIL -1.0 - 0.8 V 1,2 I. All voltage referenced to VSS. 2. The device will withstand undershoots to the - 2V level with a maximum pulse width of 20 ns at the - 1.5V level. (See Figure I.) VIH ·1.0 V _ '--- ·1.5 V _ ·2.0 V --; <-- 20 ns (max) 0062-3 Figure 1. Undershoot of Input Voltage 3. The VIR level ofOE shall be lower than VCC + 0.5V. + 70°C, Vss = OV) (Vee = 5V ± 10% for HM5474256JP-40/45) (Vee = 5V ±10% for HM5474256JP-35R) • DC Electrical Characteristics (TA = 0 to Parameter Symbol HM574256-35R HM574256-40 HM574256-45 Min Min Min Max Max Max Unit Test Conditions Note Normal Operating Current ICCA See Figure 2 rnA I Refresh Current ICCR See Figure 2 rnA I Standby Current Iccs Input Leakage Current ILl Output Leakage Current lLO - -10 -10 5 10 10 -10 -10 5 10 10 - -10 -10 5 rnA 10 ".A OV < Yin ".A OV S Vout S 7V, D out = Disable 10 < 7V ~HITACHI 652 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 2 HM574256 Series • DC Electrical Characteristics (TA = 0 to + 70'C, Vss = OV) (Vee = 5V ± 10% for HM5474256JP·40/45) (Vee = 5V ± 10% for HM5474256JP·35R) (continued) Parameter Symbol HM574256·35R HM574256·40 HM574256·45 Min Max Min Max Min Max Vee 0.4 2.4 Vee 0.4 2.4 Vee 0.4 Output High Voltage VOH 2.4 Output Low Voltage VOL 0 Notes: 0 0 Unit Test Conditions V High lout V Low lout Note = - 4 rnA = 8 rnA 1. Icc depends on output loading condition when the device is selected, Icc max is specified at the output open condition. 2. The Vin level of OE that is ILl test condition of OE must be lower than Vee + 0.5V. 1000 Ta_25"C Vcc-5.0Y Ice.tQE.".. 0 II 10 '0 100 1000 TeyCi8 (ns) 0082-4 Figure 2. ICCA, ICCR vs T cycle • Capacitance (TA = 25'C) (Vee = 5V ±5% for HM5474256JP·40/45) (Vee = 5V ±5% for HM5474256JP·35R) Parameter Input Capacitance Symbol Address, Data·in ~nl Clock (CE, OE) ~n2 Clock (WE, RF) ~n3 Output Capacitance (Data·in, Data·out) Notes: CvO Typ Max Unit Note - 5 pF I 5 pF I 7 pF 1 10 pF 1,2 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. OE, CE = VIH to disable D out ' • AC Characteristics (TA = 0 to +70'C, Vss (Vee = 5V ±10% for HM5474256JP·40/45) (Vee = 5V ±10% for HM5474256JP·35R) = OV)1 Test Conditions Input pulse levels: VIH = 3.0V, VIL = OV Transition time: tT = 3 ns Input timing reference levels: High = 2.4V, Low = 0.8V (See Figure 3.) Output timing reference levels: High = 2.4V, Low = O.4V Output load: See Figure 4. tr=3ns tr=3ns VIH=3'O~~ •• __ • __ • VIL=OV _. __ •• 2.4V O.BV 0082-5 Figure 3. Input Pulse ttZ' twZ) -Including scope & jig 0082-6 Figure 4. Output Load ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589·8300 653 HM574256 Series Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Symbol HM574256-35R Mi~ Max HM574256-4O Min Read/Write Cycle Time tee 75 - 85 CE Pulse Width 35 5000 40 CE Precharge Time tCE tcp Address Setup Time tAS 0 Address Hold Time tAR 5 - Transition Time (Rise and Fa))) tT I Refresh Period tREF - 34 Max - HM574256-45 Min 90 Max - Unit ns 45 5000 ns 39 0 - ns 0 - 5 - 5 - ns 10 I 10 I 10 ns 4 - 4 - 4 ms 39 5000 Note ns Read Cycle Parameter Symbol Access Time from CE tACS Address Access Time tAA Access Time from OE Setup Time On Read toAc tRS Hold Time on Read tRH OE Setup Time toES tLZ OE Enable to Output in Low-Z OE Disable to Output in High-Z tHZ Output Hold Time from Address tAOH Output Hold Time from CE tcoH tcop CE to OE Precharge Time HM574256-3SR HM574256-40 HM574256-45 Unit Min Max Min Max Min Max - 35 - 40 ns 0 5 5 0 30 30 25 ns ns - ns - 0 S S 0 45 25 - ns 20 - 20 ns 3 0 - ns 0 - 10 - 10 - 0 5 5 0 3 0 20 15 - - 10 3 25 - Note ns ns ns ns Write Cycle Parameter Symbol HM574256-35R HM574256-40 Min Max Min Max HMS74256-45 Min Max 30 - 5 20 Data Setup Time tDW 20 - 25 Data Hold Time 5 - 5 5 5 25 - - WE Pulse Width tDH tES twp 30 - 35 Write Hold Time from CE tWH 35 40 45 Wh Enabie to Output in High-Z twz - 20 OE to Dm Delay Time 15 OE Hold Time from WE toDD tOEH CE Setup Time from Din tDZC Setup Time on Early Write 15 20 20 - 0 - 20 15 - 0 - • 654 - 5 Unit ns ns ns ns ns ns 20 - ns ns 0 - ns HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 Note HM574256 Series Read-Modify-Write Cycle Parameter Symbol WE Delay Time from CE tewD HM574256-35R Min 35 I I HM574256-45 HM574256-40 Max Min - 40 I I Max I I Min 45 - Max Unit Note ns - Refresh Cycle Parameter Symbol HM574256-35R Min Max - RF Setup Time tFS 5 RFHoldTime tFH 15 Mode Selection Setup Time tMS 0 Mode Selection Hold Time tMH 15 teRs 15 Setup Time on CE Refresh HM574256-40 Min HM574256-45 Max - 5 15 0 20 20 Max Min Umt 5 - ns 15 - ns 0 - ns 20 - ns 20 - ns Note Static Column Mode Cycle Parameter Symbol HM574256-35R HM574256-45 Min Max Min - 25 - 25 - ns 0 - ns 0 - ns tASZ 20 Address Setup Time to WE tws 0 Address Hold Time from WE tWR 0 0 0 Max Umt Max Static Column Address Setup Time Notes: HM574256-40 Min Note I. If tOES> tOES (min) and OE is held at low level, Dou! will be valid until the next negative transition of CE. 2. 3. 4. 5. 6. 7. 8. 9. 10. II. 12. 13. Both tWH and twp must be satisfied for a delayed write cycle. If teop < teop (min), DOU! cannot be guaranteed to be in high impedance. If the negative transition of OE occurs before that of CE, tLZ is controlled by CEo twp and tDW are specified by the positive transition of CE or WE whichever occurs earlier. When WE goes low, Dou! becomes high impedance and is held in this condition to the next cycle. If the negative transition of WE occurs before that of CE, Dou! is controlled by CEo twz defines the time at which the output achieves the open circuit condition. If tES > tES (min), the cycle is early write and DoU! is in high impedance. In static columu mode cycles, read operation cannot be performed after write operation. Both tAH and tWR must be satisfied for a write cycle. tHZ defines the time at which the output achieves the open circuit condition. An initial pause of 100 I1S is required after power-up, then execute at least eight CE refresh cycles. During I/O pins are in the output state, Data-in shall not be applied to I/O pins. So, in all write cycles (early write, delayed write and read-modify-write), OE must go to high level to disable the output buffer prior to applying data to the device. In static column mode cycle, there must not be any invalid address inputs for static column mode (AI7) which are less than tAA' @HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 655 HM574256 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read/Read Cycle tee AO A16 A17 DOolt * ** D1Il: Don't care ~: Don't care 0082-7 .HITACHI 656 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM574256 Series • Read/Early Write Cycle AOA16 A17 Din Dout 0082-8 • HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 657 HM574256 Series • Read/Delayed Write Cycle tee tee AOA16 AI7 Din Dout 0062-9 $ 658 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 HM574256 Series • Read/Read Cycle (OE = VnJ AO A16 A17 D out * ** Din: Don't care ~: Don't care 0082-10 .HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 659 HM574256 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Read-Modlfy-Write Cycle AO A16 A17 WE Din Dout * fZ2I : Don I t care 0082-11 $ 660 HITACHI Hitachi America, Ltd. • HHachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 HM574256 Series • Automatic Refresh Cycle AOA17 Dout High-Z * AO - A17 : Don't care **OE", Ili.n *** E:ZZZl Don't care Don't care 0082-12 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 661 HM574256 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • CE Refresh AOAS A9- Al7 o out * Din ** ~: Don't care Don't care 0062-13 • 662 HITACHI Hitachi America, Ltd. - Hitachi Plaza - 2000 Sierra Point Pkwy. -Brisbane, CA 94005-1819 - (415) 589-8300 HM574256 Series • Static Column Mode Read Cycle -l---AOAI6 AI7 *13 .tACS High-Z tBR ~~~ * Di.~: .* ~ Don't c:are Don't c:are 0082-14 $ HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 663 HM574256 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Static Column Mode Read Cycle (OE = VIL) ADA16 A17 tACS OE V1L -----r------------+--------+-------+-------------------+----------- * Din: ** ~ Don't care Don't care 0082-15 • 664 HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589-8300 HM574256 Series • Static Column Mode Write Cycle 8 (1st Cycle = Early Write Cycle) AO A16 A17 DE tODD*12 Din Dout ~ High-Z " JZZZ]: Don't care OOB2-16 @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819 '(415) 589·8300 665 HM574256 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Static Column Mode Write CycleS (1st Cycle = Delayed Write Cycle) AD All) Al7 Din High-Z Dout * 1ZZZLl: !Jon' t care 0082-17 ~HITACHI 666 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM574100 Series Preliminary 4,194,304-Word x 1-Bit High Speed Dynamic Random Access Memory • DESCRIPTION HM574100JP Series The Hitachi HM574100 is a super high speed dynamic RAM organized 4,194,304-word x 1-bit. HM574100 has realized higher denSity, higher performance and various functions by employing 0.8 ",m Bi-CMOS technology and some new BiCMOS circuit design technologies. The HM574100 offers 8 bit static column mode as a high speed access mode. • FEATURES • Single 5V (±10%) • High Speed Access Time ................................... 35 ns/40 ns/45 ns (max) • 2,048 Refresh Cycles ................................................ (16 ms) • 2 Variations of Refresh CE Refresh Automatic Refresh • 8 Bits Static Column Mode Part No. Access Time Package 35 ns 300 mi132-pin PlasticSOJ (CP·32D) 40ns 45ns • PIN OUT HM574100JP Series VSS A14 All A12 All • ORDERING INFORMATION HM574looJP-35 HM574looJP40 HM574l00JP-45 3OCP32D (CP-32D) AS A4 • PIN DESCRIPTION A3 Ao-AIO Address Input for CE Refresh A2 Al AO AI1-AI8 Address Input RF A19-A21 Address Input for Static Column Mode Pin Name Function CE Chip Enable OE Output Enable WE Read/Write Enable Din Dout Data-in RF Refresh Control Vee Vss Ground CE Oi iii 0079-1 (Top View) Data-out Power ( + 5V) • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 667 HM574100 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VT -1.0to + 7.0 V Supply Voltage Relative to Vss vcc -1.0to +7.0 V Short Circuit Output Current los 50 rnA Voltage on Any Pin Relative to Vss Power Dissipation PT Operatiog Temperature Topr Totg Storage Temperature 0.8 W Oto + 70 ·C - 55 to + 125 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to Parameter + 70'C) Symbol Mio Typ Max Unit Note Supply Voltage Vcc 4.5 5.0 5.5 V I Input High Voltage VIR 2.4 - 6.5 V I Input Low Voltage VIL -1.0 - 0.8 V 1,2 Notes: I. All voltage referenced to Vss. 2. The device will withstand undershoots to the - 2.0V level with a maximum pulse width of 20 ns at the - 1.5V level. (See Figure 1.) r-----1.0 V -' "---- -l.S V _ -2.0 V ....., r- 20 ns (max) 0079-2 Figure 1. Undershoot of Input Voltage • DC Electrical Characteristics (TA Parameter Symbol = 0 to +70"C, Vee = 5V ±10%, Vss = OV) HM574100-35 HM574100-40 HM574100-45 Mio Min Max Min Max Max Unit Test Conditions Note Normal Operatiog Current ICCA TBD TBD TBD TBD TBD TBD rnA I Refresh Current ICCR TBD TBD TBD TBD TBD TBD rnA I Standby Current Ices 5 rnA 10 10 -10 5 ILl -10 5 Input Leakage Current -10 10 ".A Output Leakage Current ILO -10 10 -10 10 -10 10 ".A OV 0079-3 0079-4 ·Including scope & jig Figure 3. Output Load Figure 2. Input Pulse Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Symbol HM574100·35 Min ReadlWrite Cycle Time tcc 70 CE Pulse Width tCE 35 CE Precharge Time tcp 29 Address Setup Time tAS 0 Address Hold Time tAH Transition Time (Rise and Fall) tT Refresh Period tREF Max 5000 HM574100-40 HM5741()().45 Max Unit Max Min 80 - 90 40 5000 45 5000 ns 39 ns 5 - Min - ns 34 5 - 5 - I 10 I 10 I 10 ns - 16 - 16 - 16 ms 0 0 Note ns ns Read Cycle Parameter Symbol HM5741()()'35 Min HM574100·4O Max Min Max 35 - 40 25 20 - HM5741()().45 Unit Min Max 45 ns 30 ns 25 - 25 ns Access Time from OE toAC - Setup Time on Read tRs 0 - 0 - 0 - ns Hold Time on Read tRH 5 5 - 5 toES 5 5 5 OE Enable to Output in Low-Z tLZ 0 - 0 - - ns OE Setup Time - 0 - ns OE Disable to Output in High-Z tHZ - IS - - 20 - 20 ns 3 - 3 ns 0 - 0 - Access Time from CE Address Access Time Output Hold Time from Address tACS tAA tAOH 3 Output Hold Time from CE !coH 0 CE to OE Precharge Time !cop 10 10 30 10 Note ns ns ns eHITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 669 HM574100 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Cycle Parameter Symbol HM574100-35 Min HM574100-40 HM574100-45 Max Min Max Min Max 30 - 5 - 5 Data Setup Time tow 20 - 25 Data Hold Time tOR 5 - 5 Setup Time on Early Write IES 5 - 5 WE Pulse Widtb twp 25 - 30 - Write Hold Time from CE tWR 35 - 40 - 45 - WE Enable to Outupt in High-Z twz - 15 - 20 - 20 35 Unit Note ns ns ns ns ns ns Read-Modify-Write Cycle Parameter Symbol WE Delay Time from CE tcwo HM574100-35 I I Min 35 HM574100-40 Max - Min 40 I I HM574100-45 Max Min - 45 I Max I - Unit Note ns Refresh Cycle Parameter Symbol HM574100-4O HM574100-35 Min RF Setup Time tFS 5 RF Hold Time tFH 15 Mode Selection Setup Time tMS 0 Mode Selection Hold Time tMH IS Setup Time on CE Refresh tCRS 15 Max - Min Max HM574100-45 Min Max 5 - 5 15 IS 0 - 20 - 20 - 20 - 20 - 0 Unit Note ns ns ns ns ns Static Column Mode Cycle Parameter Static Column Address Setup Time Address Setup Time to WE Address Hold Time from WE Notes: Symbol HM574100-35 Min Max HM574100-40 Min Max HM574100-45 Min Max tASZ 20 - 25 - 25 - tws 0 - ns tWR - 0 0 - 0 0 - ns 0 Note ns 1. If toES> toES (min) and OE is held at low level, Doul will be valid until tbe next negative transition of CEo 2. 3. 4. 5. 6. 7. 8. 9. 10. II. 12. Botb tWH and twp must be satisified for a delayed write cycle. If tcop < leop (min), Doul cannot be guaranteed to be in high impedance. If the negative transition of OE occurs before tbat of CE, tLZ is controlled by CEo twp and tow are specified by tbe positive transition of CE or WE whichever occurs earlier. When WE goes low, Doul becomes high impedance and is held in this condition to tbe next cycle. If the negative transition of WE occurs before tbat of CE, DOUI is controlled by CEo twz defines tbe time at which tbe output achieves the open circuit condition. If tES > tES (min), the cycle is early write and Doul is in high impedance. In static column mode cycles, read operation cannot be performed after write operation. Both tAR and tWR must be satisified for a write cycle. tHZ defines the time at which tbe output achieves the open circuit condition. An initial pause of 100 ".S is required after power-up, then execute at least eight CE refresh cycles. In static column mode cycle, tbere must not be any invalid address inputs for static column mode (AI9-A21) are less tban tAA· eHITACHI 670 Unit Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM574100 Series • TIMING WAVEFORMS • Read/Read Cycle t ., L High.Z Oout--~----------~ Din Don't cat. ~ Don't car. 0079-5 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 671 HM574100 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Read/Early Write Cycle Din Dout -...:....-----{ • rLmlI Don't car. 0079-6 ~HITACHI 672 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM574100 Series • Read/Delayed Write Cycle RF AO- AIS A21 Oout--..:;..-----{ ~ Dontear. 0079-7 $ HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 673 HM574100 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Read/Read Cycle (OE = V.u OE __V~ll_ _-r__________~----------_+--------_+-------------tu·· H.gh-Z Oout -....;..---------{ • O,n Don't CIt. Con't car. 0079-8 eHITACHI 674 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM574100 Series • Read/Early Write Cycle (OE = Vld 0e~~--~------~---------4+----P~~~------~~----- Oin Oout--.;;..-----{ • ~ oon't care 0079-9 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 675 HM574100 Series - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ • Read/Delayed Write Cycle (OE = VIL) AO· Al8 Alg. A21 We t.,·Z Oe Din Oout-------t; • ~ Don't car. 0079-10 • 676 HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589.8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM574100 Series • Read-Modlfy-Write Cycle AO· AI. A19· A2! tcwo We t.es 5i OJ.. Dout ~: Don't car. 0079-11 • HITACHI Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy, • Brisbane, CA 94005·1819 • (415) 589-8300 677 HM574100 Series • Automatic Refresh Cycle AO· AZI ~ ______________________ _________________________ H~~~h_'Z • Don', are AQ-Al' Oi. Don't ore Din ~ DOlI'..... 0079-12 • CE Refresh Cycle ' AOAla A19- All Oi _v~,~~~--------+_----~----_+----------------r_-------tu-' Oout _H..;;,i9h_ -_Z_ _ _--{ • : Don't (Ir. ~: DIn Oon't cor. 0079-15 ~HITACHI 680 Hitachi America, Ltd,' Hitachi Plaza' 2000 Sierra Point Pkwy,' Brisbane, CA 94005-1819' (415) 589-8300 HM574100 Series • Static Column Mode Write Cycle"S (1st Cycle Early Write Cycle) • ~: Don't cart 0079-16 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 681 HM574100 Series • Static Column Mode Write Cycle*S (1st Cycle Delayed Write Cycle) J._- ---------11 AO· A18 Alg. All Din Oout Don't car. 0079-17 ~HITACHI 682 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589·8300 HM574400 Series - - - - - - - - - Preliminary 1,048,576-Word x 4-Bit High Speed Dynamic Random Access Memory • DESCRIPTION HM574400JP Series The Hitachi HM574400 is a super high speed dynamic RAM organized 1,048,576-word x 4-bit. HM574400 has realized higher density, higher performance and various functions by employing 0.89 I-'m Bi-CMOS technology and some new Bi-CMOS circuit design technologies. The HM574400 offers 2-bit static column mode as a high speed access mode. • FEATURES • Single 5V (±10%) • High Speed Access Time ................................... 35 ns/40 ns/45 ns (max) • 2048 Refresh Cycles ................................................ (16 ms) • 2 Variations of Refresh CE Refresh Automatic Refresh • 2 Bits Static Column Mode • ORDERING INFORMATION Part No. Access Time Package HM5744001P-35 HM5744001P-40 HM5744001P-45 35 ns 40ns 45 ns 300 mil 32-pin Plastic SOl (CP-32D) • PIN OUT HM574400JP Series Vss A14 A13 A12 All AS A4 A3 A2 • PIN DESCRIPTION Pin Name 3DCP32D (CP-32D) Function Ao-AIO Address Input for CE Refresh Al1-AI8 Address Input Al AD Al9 CE Address Input for Static Column Mode RF Chip Enable CE OE Output Enable OE WE ReadIWrite Enable WE I/OI-I/04 RF Refresh Control Vee Vss Data-in/Data-out 0061-1 (Top View) Power ( + 5V) Ground ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 683 HM574400 Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Voltage on Any Pin Relative to Vss VT -1.0to Supply Voltage Relative to Vss Vee -1.0to Short Circuit Output Current los Unit + 7.0 + 7.0 V V 50 Power Dissipation PT Operating Temperature Topr Storage Temperature T stg rnA W 0.8 + 70 55 to + 125 'C Oto - 'C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to Parameter Notes: + 70·C) Symbol Min Typ Max Unit Note Supply Voltage Vee 4.5 5.0 5.5 V I Input High Voltage VIR 2.4 - 6.5 V I Input Low Voltage VIL -1.0 - 0.8 V 1,2 1. All voltage referenced to Vss. 2. The device will withstand undershoots to the - 2.0V level with a maximum pulse width of 20 ns at the - 1.5V level. (See Figure I.) r----- -1.0 V - _ -loS V _ -2.0 V - ; E-- 20 ns (max) 0081-2 Figure 1. Undershoot of Input Voltage • DC Electrical Characteristics (TA = 0 to Parameter Symbol + 70·C, Vee = HM574400-35 5V ± 10%, Vss = OV) HM574400-40 HM574400-45 Min Max Min Max Min Max Unit Test Conditions Note Normal Operating Current leeA TBD TBD TBD TBD TBD TBD rnA 1 Refresh Current leeR TBD TBD TBD TBD TBD TBD rnA I Standby Current Ices 5 rnA Input Leakage Current ILl -10 10 -10 10 -10 10 /LA OV< Yin < 7V Output Leakage Current ILO -10 10 -10 10 -10 10 /LA OV < Vout < 7V, Dou! = Disable Output High Voltage VOH 2.4 Vee 2.4 Vee 2.4 Vee V High lout Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 V Low lout Note: - 5 - 5 - = - 4 mA = 8 rnA 1. ICC depends on output loading condition when the device is selected, Icc max is specified at the output open condition. ~HITACHI 684 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM574400 Series • Capacitance (TA ~ 25°C, Vee ~ 5V ±10%) Parameter Input Capacitance I I Symbol Max Unit Note Cin! - 5 pF 1 Clock Cin2 - 5 pF I CliO - \0 pF 1,2 Output Capacitance (Data-in, Data-out) Notes: Typ Address, Data-in 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. OE, CE = VIH to disable D out. • AC Characteristics 1 (TA ~ 0 to Test Conditions + 70°C, Vee= 5V ±10%, VSS = OV) Input Pulse Levels: VIH ~ 3.0V, VIL = OV Transition Time: tT ~ 3 ns Input Timing Reference Levels: High = 2.4V, Low ~ O.BV (See Figure 2.) Output Timing Reference Levels: High ~ 2.4V, Low ~ 0.4V Output Load: See Figure 3. SV t-r=3ns DO VIL=OV . - - - - - - ~----'l 0---+---, o.SV 2SSlZ 0061-3 0081-4 -Including scope and jig Figure 3. Output Load Figure 2. Input Pulse Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Parameter Read/Write Cycle Time HM574400-35 Symbol Min tcc 70 CE Pulse Width tCE 35 CE Precharge Time tcp 29 Address Setup Time tAS 0 Address Hold Time tAH Transition Time (Rise and Fall) tT Refresh Period tREF Max - 5000 HM574400-4O Min 80 40 Max - 5000 HM574000-45 Min 90 45 Max 5000 Unit ns ns 34 - 39 - ns 0 - 0 - ns 5 - 5 - 5 - ns 1 10 1 \0 1 10 ns 16 ms - 16 - 16 - Note ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 685 HM574400 Series Read Cycle Parameter HM574400-35 Symbol HM574400-4O Min Max Min Max Access Time from CE tACS 25 - 40 tAA - 35 Address Access Time Access Time from OE tOAe - 20 - 25 Setup Time on Read tRS 0 0 Hold Time on Read tRH 5 - OE Setup Time tOES 5 OE Enable to Output in Low-Z tLZ OE Disable to Output in High-Z HM574400-45 Min - 30 Unit Max 45 ns 30 ns 25 ns ns 0 5 - - 5 - 5 0 - 0 - 0 - tHZ - 15 - 20 - 20 ns Output Hold Time from Address tAOH 3 - 3 tCOH 0 - 0 0 - ns Output Hold Time from CE CE to OE Precharge Time tcop 10 - 10 - 10 - ns 3 5 Note ns ns ns ns Write Cycle Parameter HM574400-35 Symbol Min HM574400-40 Max Min Max HM574400-45 Unit Min Max ns ns Data Setup Time tDW 20 - 25 - 30 Data Hold Time tDH 5 - 5 - 5 Setup Time on Early Write tES 5 5 - 5 WE Pulse Width twp 25 30 - 35 Write Hold Time from CE tWH 35 - 40 - 45 - WE Enable to Output in High-Z twz - 15 - 20 - 20 OE to Dm Delay Time tODD 15 - 20 - 20 - ns OE Hold Time from WE tOEH 15 - 20 - 20 - ns CE Setup Time from Din tDZC 0 - 0 - 0 - ns Note ns ns ns ns Read-Modify-Write Cycle Parameter Symbol WE Delay Time from CE tCWD HM574400-40 HM574400-35 Min 35 I I Max I Min - I 40 HM574400-45 Max Min - 45 I I Max Unit - Note ns Refresh Cycle Parameter Symbol HM574400-35 Min HM574400-40 Max Min HM574400-45 Min Max Max Unit tps 5 - 5 - ns tpH - 15 - 5 15 15 ns Mode Selection Setup Time tMS 0 - 0 - 0 Mode Selection Hold Time tMH 15 20 tCRS 15 - 20 Setup Time on CE Refresh - - 20 - ns RF Setup Time RFHoldTime 20 Note ns ns Static Column Mode Parameter Symbol HM574400-35 Min Max HM574400-4O Min Max HM574400-45 Min Max Unit tASZ 20 - 25 - ns tws 0 - 25 Address Setup Time to WE 0 - 0 ns Address Hold Time from WE tWR 0 - 0 - 0 - Static Column Address Setup Time @HITACHI 686 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 ns Note HM574400 Series Notes: 1. If tOES> tOES (min) and OE is held at low level, D out will be valid until the next negative transition of CEo 2. Both tWH and twp must be satisfied for a delayed write cycle. 3. If teop < teop (min), D out cannot be guaranteed to be in high impedance. 4. If the negative transition of OE occurs before that of CE, tLZ is controlled by CEo 5. twp and tDW are specified by the positive transition of CE or WE whichever occurs earlier. 6. When WE goes low, Dout becomes high impedance and is held in this condition to the next cycle. If the negative transition of WE occurs before that of CE, Doul is controlled by CEo twz defines the time at which the output achieves the open circuit condition. 7. If tES > tEs(min), the cycle is early write and D out is in high impedance. 8. In static column mode cycles, read operation cannot be performed after write operation. 9. Both tAH and tWR must be satisfied for a write cycle. 10. tHZ defines the time at which the output achieves the open circuit condition. 11. An initial pause of 100 J.'s is required after power-up, then execute at least eight CE refresh cycles. 12. During I/O pins are in the output state, Data-in shall not be applied to I/O pins. So, in all write cycles (early write, delayed write and read-modify-write), OE must go to high level to disable the output buffer prior to applying data to the device. 13. In static column mode cycle, there must not be any invalid address inputs for static column mode (A 19) which are less than tAA' • TIMING WAVEFORMS • Read/Read Cycle AO· Ala Al9 ;z·e High.Z Oout--'-------{ Din Don't care ~ Don't car. 0081-5 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 687 HM574400 Series • Read/Early Write Cycle AO· A18 A19 O;n-------+----+---~~--~------------~~I H;gh·Z Oout --.-.:.----4' . ~ Don't care 0061-6 ~HITACHI 688 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 HM574400 Series • Read/Delayed Write Cycle AOAl8 Al9 WE O'n----+-+---I!--+----{ 'u" t High-Z II -, Oout-------{ Don't care 0081-7 @HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 689 HM574400 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Read/Read Cycle COE = Vld Itt" to ,, ~ t,. .-1- --'-~r AO· A19 High.Z Oout------------~--------------------------------------------- AO·A19 Don't care OE. Din Don't care Don't care 0061-10 ~HITACHI 692 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy., Brisbane, CA 94005,1819' (415) 589-8300 HM574400 Series • CE Refresh Cycle AOAl0 AllA19 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Cout : Don't care ~: Din Don't care 0081-11 @HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 693 HM574400 Series • Static Column Mode Read Cycle AO· A18 A19 Oout ~,gh.Z H'gh.Z : Don't c.,. ~: Can't car. Oln 0081-12 $ 694 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 HM574400 Series • Static Column Mode Read Cycle (OE = Vld AOAtB At9 WE Oe _v~"~-J~ +-____-4____ ________ ~ ________________-+________ Dout _H-,ig_h-_z_ _ _-t: • : Don't care ~: Din Don't care 0081-13 @HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 695 HM574400 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Static Column Mode Write Cycle'S (1st Cycle = Early Write Cycle) '---------~ AOAI8 AI9 1000-'2 Oin Dout ~ H;gh-Z ~- t,.,-" • ~: Don't ,art 0061-14 @HITACHI 696 Hitachi America, Ltd,. Hitachi Plaza· 2000 Sierra Point Pkwy,· Brisbane, CA 94005-1819. (415) 589-8300 HM574400 Series • Static Column Mode Write Cycle-a (1st Cycle Delayed Write Cycle) • ~: Don't care 0081-15 @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 697 @HITACHI 698 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819. (415) 589·8300 Section 4 MOS Dynamic RAM Modules fiHITACHI® • 700 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56A 18 Series - - - - - - - - - - - 1,048,576-Word x 8-Bit High Density Dynamic RAM Module • PIN DESCRIPTION • DESCRIPTION The HB56A 18 is a 1M x 8 dynamic RAM module. mounted eight 1-Mbit DRAM (HM511000JP) sealed in SOJ package. An outline of the HB56A 18 is 30-pin single in-line package having Lead types (HB56A 18A. HB56A 18AT). socket type (HB56A 18B). Therefore. the HB56A 18 makes high density mounting possible without surface mount technology. The HB56A 18 provides common data inputs and outputs. Its module board has decoupling capacitors beneath each SOJ. • FEATURES • 30-pin Single In-line Package Lead Pitch ..................................................... 2.54mm • Single 5V (±10%) Supply • High Speed Access Time ..................... 60 ns/70 ns/80 ns/100 ns/120 ns (max) • Low Power Dissipation Active Mode ......... 3.96 mW/3.52 mW/3.08 mW/2.64 mW/2.20 mW (max) Standby Mode ............................................. 88 mW (max) • Fast Page Mode Capability • 512 Refresh Cycle ................................................... (8 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible • ORDERING INFORMATION Pin No. Pin Name Pin No. Pin Name I Vee CAS 16 DQ4 2 17 As 3 DQo 18 4 Ao 19 A9 NC DQs 5 Al 20 6 DQI 21 WE 7 Az 22 Vss DQ6 8 A3 23 9 Vss 24 NC 10 DQz 25 DQ7 11 ~ 26 NC 12 As 27 RAS NC 13 DQ3 28 14 A6 29 NC 15 A7 30 Vee • PIN DESCRIPTION Package Access Time 30-pinSIP Lead Type 30-pin SIP Low Profile Lead Type 30-pinSIMM Socket Type 60ns HB56AI8A-6H HB56AI8AT-6H HB56AI8B-6H 70ns HB56AI8A-7H HB56AI8AT-1H 80ns HB56AI8A-8A lOOns HB56AI8A-IOA 120ns HB56A18A-12A Ao-As RAS Refresh Address Input HB56AI8B-1H HB56AI8AT-8A HB56AI8B-8A CAS Column Address Strobe HB56AI8AT-IOA HB56AI8B-IOA WE ReadIWrite Enable HB56A18B-12A DQo-DQ7 Data-in/Data-out HB56AI8AT-12A OO------------------------w--no 1 pin Function Address Input • PIN OUT I/ Pin Name Ao-A9 Row Address Strobe Vee Power Supply ( + 5V) Vss NC Ground Non-Connection I / 30 pin 0120-1 ~HITACHI Hitachi America. Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819. (415) 589-8300 701 HB56A18 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM AO A1 A2 (4) (5) (7) (8) A3 (11 ) A4 (12) AS A6 A7 A8 A9 (14) (15) I (17) (18) I (27) (2) (21) AO-AS RAS CAS Din Dout Din Dout Dout Din Dout M3 Din ~ ~ 003 ~(10) D02 (6) (3) - ~ (13) D01 Dao - WE - I I - M4 M2 M1 f--- I M8 Din DoutW Din Dout Din Dout Din Dout M7 M6 MS AO-AS RAS CAS I W W (25) ~ (23) D06 (20) (16) I--- D07 DOS D04 r-- -WE r-- Vee (1) vccJiQL] vss!J Vss 22 ~ T .. M1 - 8 Vee C=O.22IJFx 8 .. M1-8Vss 0120-2 @HITACHI 702 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HB56A18 Series • PHYSICAL OUTLINE Unit: mm inch • HB56A18A Series 81.2(3.197) • . c: 0.50(0.0197) .!: .§ E 0 ""'" 1Il 2.54(0.1) 30 I 5.28max. 1-(0.208max.) ~ 225(00098) 0 NB 0120-3 • HB56A18AT Series 90.14 (3.549) ,. "I 8.89max. 1~6~~2~~~~P~i~ii~O~~~~-~TI~-=-=-+---+7'6:--;o!---"f;~0.324 (0.100) (0.0197) (0.300) L (0.350max.lj' "' '~'s ~§ No 0120-4 • HB56A18B Series _~.~IH.~ .82.1413.2.34 ) 5.28max. (0.208max. ) 1:45mln.lo.05?mln. ) 1.27±0.127 (0.05 ± 0.005") lIASIC BOTH SIDES .17 ±O.127( ~.125±0.OO5) 0120-5 Note: I. The plating of the contact finger is solder coat. $HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589·8300 703 HB56A 18 Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Input Yin -1.0to +7.0 V Output Vout -1.0to +7.0 V Supply Voltage Relative to Vss VCC -1.0to +7.0 V Short Circuit Output Current lout 50 rnA Power Dissipation PT 8 W 'c 'c I I Voltage on Any Pin Relative to Vss Operating Temperature Topr Oto +70 Storage Temperature T stg - 55 to + 125 • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to Parameter Symbol VSS Supply Voltage + 70'C) Min Typ Max Unit 0 0 0 V Note Vcc 4.5 5.0 5.5 V I Input High Voltage VIH 2.4 5.5 V 1 Input Low Voltage VIL -1.0 - 0.8 V 1 Note: 1. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss = OV) HB56AI8A/AT/B Parameter Min Operating Current Standby Current IcC! -7H -6H Symbol - -lOA -8A Max Min Max 720 - 640 Min - Max 560 Min - -12A Max 480 Min - Unit Test Conditions 400 mA tRC = Min - 16 - 16 - 16 - 16 - 16 mA TTL Interface RAS, CAS = VIH, Dout = High-Z - 8 - 8 - 8 - 8 - 8 mA CMOS Interface RAS, CAS :!: VCC - 0.2V, D out = High-Z ICC2 RASOnly Refresh Current ICC3 - 720 - 640 - 480 - 400 - 360 mA tRC Standby Current Iccs - 40 - 40 - 40 - 40 - 40 rnA RAS CAS D out CAS Before RAS Refresh Current ICC6 - 720 - 640 - 480 - 400 - 320 rnA tRC = Min Fast Page Mode Current ICC7 - 720 - 640 - 400 - 400 - 320 mA tpc = Min Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 -10 10 /LA OV S Yin S 7V Output Leakage Current lLO -10 10 -10 10 -10 10 -10 10 -10 10 /LA OV S Vout S 7V, Dout = Disable Output High Voltage VOH 2.4 VCC 2.4 Vce 2.4 Vce 2.4 Vee 2.4 Vee V lout = -5mA Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 0 0.4 V lout = 4.2rnA Notes: = = = = Min VIH, VIL Enable 1. Ice depends on output load condition when the device is selected, lee max is specified at the output open condition. 2. Address can be changed less than three times while RAS = V IL. 3. Address can be changed once or less while CAS = VIH. ~HITACHI 704 Note Max Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 1,2 2 I 1,3 HB56A18 Series • Capacitance (TA = 25°C, Vee = 5V ±10%) Parameter Input Capacitance (Address) Input Capacitance (Clock) Input/Output Capacitance (DQo-DQ7) Notes: Symbol Typ Max Unit Note CII - 55 pF I CI2 - 70 pF I CliO - 17 pF 1,2 I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out . • AC Characteristics Please show at HM511000H series or HM511000A series about AC Characteristics. But don't use by Delayed Write Cycle, because the HB56A 18 provides common data inputs and outputs. Please use by Early Write Cycle. (twes :<: twes (min». ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 705 HB56C18 Series 1,048,576·Word x 8·Bit High Density Dynamic RAM Module • PIN DESCRIPTION • DESCRIPTION The HB56C18 is a 1M x 8 static column mode dynamic RAM module, mounted eight 1-Mbit DRAM (HM511002JP) sealed in SOJ package. An outline of the HB56C18 is 30-pin single in-line package having Lead types (HB56C18A, HB56C18AT), socket type (HB56C18B). Therefore, the HB56C18 makes high density mounting possible without surface mount technology. The HB56C18 provides common data inputs and outputs and also provides separate 110 on parity bit for parity check. Its module board has decoupling capacitors beneath each SOJ. Pin No. Pin Name Pin No. Pin Name I Vee CAS 16 DQ4 2 17 As 3 DQo 18 4 19 A9 NC • FEATURES 5 Ao Al 20 DQs • 30-pin Single In-line Package Lead Pitch ..................................................... 2.54mm • Single 5V (± 10%) Supply • High Speed Access Time ................................. 80 nsl100 ns/120 ns (max) • Low Power Dissipation Active Mode ......................... 3080 mW/2640 mW/2200 mW (max) Standby Mode ............................................. 88 mW (max) • Static Column Mode Capability • 512 Refresh Cycle ................................................... (8 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible 6 DQI 21 WE 7 A2 22 Vss 8 A3 23 DQ6 VSS 24 NC DQ2 25 11 A4 26 DQ7 NC 12 As 27 RAS 13 DQ3 28 NC 14 A6 29 NC 15 A7 30 Vee • PIN DESCRIPTION • ORDERING INFORMATION Access Time 9 10 Pin Name Package Function Ao-A9 Address Input Ao-As Refresh Address Input 30-pin SIP Lead Type 30-pin SIP Low Profile Lead Type 30-pin SIP Socket Type 80ns HB56CI8A-8A HB56CI8AT-8A HB56CI8B-8A RAS Row Address Strobe lOOns HB56CI 8A-IOA HB56CI8AT-IOA HB56CI8B-IOA CS Chip Select 120ns HB56C18A-12A HB56CI8AT-12A HB56C18B-12A • PIN OUT WE Read/Write Enable DQo-DQ7 Data-in/Data-out Vee Power Supply ( + 5V) Vss NC Ground Non-Connection I no -·--·------·--·----·------------00 I !- 1 pin ! 30 pin 0121-1 ~HITACHI 706 Hiiachi America, Ltd.' Hiiachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56C18 Series • BLOCK DIAGRAM (4) AO (5) A1 A2. (7) (S) A3 A4 AS A6 A7 AS A9 (11 ) (12) (14) (15) I (17) (1S) I Dout Dout RAS (2) Din Din ~ ~ ~ CAS (21 ) Oin Dout Dout Din M1 M4 M3 M2 f - - - AO-AS (27) I (13) .=.J (10) (6) (3) I-- D03 D02 D01 DOO ~ WE ~ I - I Dout Din Dout W CAS WE Vee (1) ---, Vee~ Vss !J Vss 22 Din Dout Din Dout Din M5 M8 M7 M6 AD-AS RAS I -..--J U - (25) P(23) (20) (16) D07 D06 D05 D04 - ~ M1-8Vee -.L C=O.22IlFx8 T I-__~______~~ . .. M1 - 8 Vss 0121-2 @HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 707 HB56C18 Series • U . PHYSICAL OUTLINE mm nit: (inch) • HB56C18A Series 787413100' • 528mex (O.208n1ai-) oso.!.Q 9191 ~ E :;0; " 0121-3 • HB56C18AT Series 8R9( :l.500} ci .5 .- E ~8 "'NO..... 0121-4 • HB56C18B Series 88.913.500) 82.1413.2:1<) 3.3810..1331 S.28max. (O.2OBma•. ) I 14Smm.(O.057mm ) o DDDDDD~O BASIC BOTH SIDES ., 1.27±o..127 Io..OS ± 0.005 1 3.17± 0..1271 ';0..125 ± 0..005) 1.7810.070.) 7.6210.300\ 73.6612.900)REF . BASIC BOTH SIDES 0121-5 Note: 1. The plating of the contact finger is solder coat. ~HITACHI 708 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56C18 Series • ABSOLUTE MAXIMUM RATINGS Value Unit Voltage on Any Pin Relative to Vss Parameter Symbol VT -1.0to + 7.0 V Supply Voltage Relative to Vss vcc -1.0to +7.0 V Short Circuit Output Current lout 50 rnA Power Dissipation PT 8.0 W Operating Temperature Topr Oto + 70 'C Storage Temperature T stg - 55 to + 125 'C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to Parameter Symbol Supply Voltage Note: + 70'C) Min Typ Max Unit Vss 0 0 0 V Note I Vcc 4.5 5.0 5.5 V Input High Voltage VIR 2.4 5.5 V I Input Low Voltage VIL -1.0 - O.S V 1 I. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to + 70'C, Vee = 5V ± 10%, Vss = OV) HB56CISA/AT/B Parameter -SA Symbol Min Operating Current Standby Current IcC! - -lOA Max 560 Min - -12A Max 4S0 Min - Unit Test Conditions Note Max 400 rnA tRC = Min - 16 - 16 - 16 rnA TTL Interface RAS, CAS = VIH, DOllt = High-Z - S - 8 - S rnA CMOS Interface RAS, CAS 2: VCC - 0.2V, D out = High-Z ICC2 1,2 RASOnly Refresh Current ICC3 - 480 - 400 - 360 rnA tRC = Min 2 Standby Current ICC5 - 40 - 40 - 40 rnA RAS = VIR, CS = VIL D out = Enable 1 CAS Before RAS Refresh Current ICC6 - 480 - 400 - 320 rnA tRC 320 rnA Static Column Mode tpc = Min = Min Static Column Mode Current ICC9 Input Leakage Current ILl -10 10 -10 10 -10 10 p.A OV:S Vin:S 7V Output Leakage Current ILO -10 10 -10 10 -10 10 p.A OV:S Vout:S 7V, DOllt = Disable Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V lout Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 V lout Notes: - 4S0 - 400 - = = 1,3 -5mA 4.2 rnA I. ICC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed less than three times while RAS = V IL. 3. Address can be changed once or less while CS = VIR. ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 709 HB56C18 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Capacitance (TA = 25°C, Vee = 5V ±10%) Parameter Symbol Input Capacitance (Address) Cll Input Capacitance (Clock) CI2 Input/Output Capacitance (DQo-DQ7) Notes: Typ Max Unit - 55 pF I 70 pF 1,2 pF 1,2 17 CliO 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CS = Vm to disable D out . Note • AC Characteristics Please show at HM511002H series about AC Characteristics. But don't use by Delayed Write Cycle, because the HB56C18 provides common data inputs and outputs. Please use by Early Write Cycle. (twes ;:, twes (min)) . • 710 HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56G18 Series 1,048,57S·Word x 8-Bit High Density Dynamic RAM Module • DESCRIPTION The HB56G18 is a 1M x 8 dynamic RAM module, mounted two 4 Mbit DRAM (HM514400AS) sealed in SOJ package. An outline of the HB56G18 is 30-pin single in-line package (socket type). Therefore, the HB56G18 makes high density mounting possible without surface mount technology. The HB56G18 provides common data inputs and outputs. Its module board has decoupling capacitors beside each SOJ. • PIN OUT I! I nnmuumum-uuu--nn ! 30 pin 1 pin 0104-1 • FEATURES • 30-pin Single In-line Package Lead Pitch ................................ 2.54mm • Single 5V (±10%) Supply • High Speed Access Time ............. 70 ns/80 ns/100 ns (max) • Low Power Dissipation Active Mode ...... 1100 mW 1990 mW 1880 mW (max) Standby Mode ........................ 22 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycles .......................... (16 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible • ORDERING INFORMATION Part No. Access Time Package HB56G18B-7A HB56G 18B-8A HB56G18B-IOA 70ns 80ns lOOns 30-pinSIP Socket Type HB56GI8GB-7A HB56GI8GB-8A HB56GI8GB-IOA 70 ns 80ns lOOns 30-pin SIP Socket Type Contact Pad Solder Gold Pin Name Pin No. 16 DQ4 2 Vee CAS 17 As A9 NC Pin No. I 3 DQO 18 4 AD 19 5 Al 20 6 DQI 21 Pin Name DQs WE 7 A2 22 Vss 8 A3 23 DQ6 9 Vss DQ2 24 NC 10 25 DQ7 NC 11 A4 26 12 A5 27 RAS 13 DQ3 28 NC 14 A6 29 NC 15 A7 30 • PIN DESCRIPTION Pin Name Ao- A9 Ao- A9 Function Address Input Refresh Address Input RAS Row Address Strobe CAS Column Address Strobe WE ReadIWrite Enable DQo-DQ7 Data-inIData-out Vee Power Supply ( + 5V) Vss NC Ground No Connection ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 711 HB56G18 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Block Diagram AO A1 A2 A3 A4 AS A6 A7 A8 A9 ~4) (5) (7) (8) (11 ) ( 12) (14) (15) (17) (18) MO ~ (27) (2) (21) AO-A9 1/01 RAS 1/02 CAS 1/03 WE 1/04 Vee Vss (3) DQO (6) (10) (13) DQ1 HM514400AS DQ2 DQ3 OE~ t-i~C1 M1 AO-A9 I/O 1 RAS 1/02 CAS 1/03 WE 1104 OE Vee Vss Hf-Vee Vee Vss Vs 5 (16) (20) (23) (25) DQ4 DQ5 DQ6 HM514400AS DQ7 ~ C2 (1 ) (30) (9) (22) 0104-2 .HITACHI 712 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HB56G18 Series U. • PHYSICAL OUTLINE mm nit: inch • HB56G188/GB Series 3.500 214 . 4 1 3 • 175 if"==::t2fi:-7-8!l!5!;;;;;;;e;;;~--IF-ii!l;lo;;;;;;;;;;;;;~-IDi1ioiffiDOi1ioi1iiooi1ioiffioor/;j:;p.f o "0.125 DO 30 ~8~30r-~~~~~~ o o ~;~~r-~--~~-------.~----------~~~--------------~ 0104-3 Note: Following the specification of the contact pad. Part No. Detail A Contact Pad HB56G18B-XX Solder HB56G18GB-XX Gold 0.25 max. 0.010 1.!!0 min. 0.071 ill 0.070 0104-4 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 713 HB56G18 Series • ABSOLUTE MAXIMUM RATINGS Parameter Value Unit (Input) Yin -1.0to +7.0 V (Output) Vout -1.0to +7.0 V Supply Voltage Relative to Vss Vcc -1.0to +7.0 V Short Circuit Output Current 50 mA Power Dissipation lout PT 2.0 Operating Temperature Topr Oto+70 W DC Storage Temperature Tstg - 55 to + 125 DC I I Voltage on Any Pin Relative to Vss Symbol • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to Parameter Symbol Min Typ Max Unit 0 0 0 V VSS Supply Voltage + 70'C) VCC 4.5 5.0 5.5 V I Input High Voltage VIH 2.4 5.5 V 1 Input Low Voltage VIL -1.0 - O.S V I I. All voltage referenced to Vss. Note: • DC Electrical Characteristics (TA = 0 to Parameter Symbol Operating Current Standby Current ICCI + 70'C, Vee HB56GISB/GB-7A = 5V ± 10%, Vss = OV) HB56GISB/GB-SA HB56G18B/GB-IOA Min Max Min Max Min Max - 200 - 180 - 160 - 4 - 4 - 4 - 2 - 2 - 2 ICC2 Unit Test Conditions mA tRC = Min ICC3 - 200 - 180 - 160 mA Standby Current ICCS - 10 - 10 - 10 mA CAS Before RAS Refresh Current ICC6 - 200 - ISO - 160 mA tRC = Min Fast Page Mode Current ICC7 - 200 - 180 - 160 mA tpc = Min Input Leakage Current ILl -10 10 -10 10 -10 10 /LA OV:S Vin:S 7V Output Leakage Current ILO -10 10 -10 10 -10 10 /LA OV :s Vout:S 7V, Dout = Disable 2.4 VCC 0.4 2.4 Vcc 0.4 2.4 VCC 0.4 V lout V lout Output High Voltage VOH Output Low Voltage VOL Notes: 0 0 0 = Min RAS = VIH, CAS = VIL, Dout = Enable tRC = -SmA = 4.2mA I. IcC depends on output load condition when the device is selected, Icc max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIL. 3. Address can be changed once or less while CAS = Vrn . • Note 1,2 TTL Interface mA RAS, CAS = Vrn, Dout = High-Z CMOS Interface, RAS, mA CAS <: VCC - 0.2V, Dout = High-Z RASOnIy Refresh Current 714 Note HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 2 1 1,3 HB56G18 Series • Capacitance (TA = 25'C, Vee = 5V ±10%) Parameter Symbol Typ Input Capacitance (Address) Cll Input Capacitance (Clock) CI2 - CliO - InputlOutput Capacitance (DQO-7) Notes: Max Unit Note 30 pF I 34 pF I 17 pF 1,2 I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIR to disable D out ' • AC Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss = OV)1, 12 Read, Write, and Refresh Cycles (Common Parameters) Parameter Symbol HB56GI8B/GB-7A Min Max HB56G 18B/GB-8A Min Max HB56G 18B/GB- lOA Unit Min Max 190 - ns - ns Note Random Read or Write Cycle Time tRC 130 RAS Precharge Time tRP 50 RAS Pulse Width tRAS 70 10000 80 10000 100 10000 ns CAS Pulse Width tCAS 20 10000 20 10000 25 10000 ns Row Address Setup Time tASR 0 - 0 - 0 - ns Row Address Hold Time tRAH 10 10 - ns tASC 0 0 - ns Column Address Hold Time tCAH 15 15 - 15 Column Address Setup Time - 20 - ns RAS to CAS Delay Time tRCD 20 50 20 60 25 75 ns 8 RAS to Column Address De1ayTime tRAD 15 35 15 40 20 55 ns 9 - 150 - 60 0 - 70 RAS Hold Time tRSH 20 - 20 - 25 tCSH 70 - 80 - 100 - ns CAS Hold Time CAS to RAS Precharge Time tCRP \0 - 10 - 10 - ns Transition Time (Rise and Fall) tT 3 50 3 50 3 50 ns 7 tREF - 16 16 ms 15 Unit Note Refresh Period - 16 - ns Read Cycle Parameter Symbol HB56GI8B/GB-7A Min HB56G 18B/GB-8A HB56GI8B/GB-IOA Max Min Max Min Max Access Time from RAS tRAC - 70 - 100 ns 2,3 tCAC - 20 - 80 Access Time from CAS 20 - 25 ns 3,4 Access Time from Address tAA - 35 - 40 - 45 ns 3,5 Read Command Setup Time tRCS 0 - 0 - 0 - ns Read Command Hold Time to CAS tRCH 0 - 0 - 0 - ns Read Command Hold TimetoRAS tRRH 0 - 0 - 0 - ns Column Address to RAS Lead Time tRAL 35 - 40 - 55 - ns Output Buffer Tum-off Time tOFF! 0 20 0 20 0 25 ns 6 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 715 HB56G18 Series Write Cycle Parameter Symbol HB56G ISB/GB-7 A HB56G ISB/GB-SA Min Max Min Max HB56G1SB/GB-IOA Min Max Unit Note 10 Write Command Setup Time twcs 0 - 0 15 15 - 20 - ns tWCH - 0 Write Command Hold Time ns Write Command Pulse Width twp 10 - 10 - 20 - ns Data-in Setup Time tDS 0 - 0 - 0 - ns 11 Data-in Hold Time tDH 15 - 15 - 20 - ns 11 Refresh Cycle Parameter Symbol HB56G ISB/GB-7 A Min Max HB56G ISB/GB-SA Min Max HB56GISB/GB-IOA Min Max Unit CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 10 - 10 - 10 - ns tRPC 10 - 10 - 10 - ns RAS Precharge to CAS Hold Time Note Fast Page Mode Cycle Parameter Symbol HB56G1SB/GB-7A Min Max HB56G ISB/GB-8A HB56G1SB/GB-IOA Min Max Min Max Unit Note Fast Page Mode Cycle Time tpc 45 - 50 - 55 - ns Fast Page Mode CAS Precharge Time tcp 10 - 10 - 10 - ns Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 - 100000 ns 13 Access Time from CAS Precharge tACP - 40 - 45 - 50 ns 14 tRHCP 40 - 45 - 50 - ns RAS Hold Time from CAS Precharge Notes: I. AC measurements assume tT = 5 ns. 2. Assumes that tRcD ,;; tRCD (max) and tRAD ,;; tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL load and 100 pF. 4. Assumes that tRCD ~ tRCD (max) and tRAD ,;; tRAD (max). 5. Assumes that tRCD ,;; tRCD (max) and tRAD ~ tRAD (max). 6. !oFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. S. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. Early write cycle only (twcs ~ twcs (min)) II. These parameters are referenced to CAS leading edge in an early write cycle. 12. An initial pause of 100 /Ls is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). 13. tRASC is determined by RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tACP' IS. tREF is determined by 1,024 refresh cycles. @HITACHI 716 Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HB56G18 Series • TIMING WAVEFORMS • Read Cycle Address teAe tOFF Valid Output Dout tRAe High-Z Din ~ : Don't care 0104-5 .HITACHI Hitachi America, Ltd.• Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 717 HB56G18 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Early Write Cycle tRe Address Dout Din High-Z ~ : Don't care 0104-6 ~HITACHI 718 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56G18 Series • RAS Only Refresh Cycle tRC Address High-Z Dout WE : Don't care 2 ~: Don't care 0104-7 • CAS Before RAS Refresh Cycle tRC LRP tCSR tCHR 1 Address, Din: Don't care 2 Dout: High-Z 3 ~: Don't care 4 WE=VIH 0104-8 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 719 HB56G18 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read Cycle Address Dout tRAC High-Z Din ~ : Don't care 0104-9 • 720 HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HB56G18 Series • Fast Page Mode Early Write Cycle tRASC Address Dout High-Z Din ~ : Don't care 0104-10 o HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 721 HB56A48 Series 4,194,304-Word x 8-Bit High Density Dynamic RAM Module • DESCRIPTION • PIN OUT .-------------------------------~ The HB56A48 is a 4M x 8 dynamic RAM module, mounted 8 pieces of 4 Mbit DRAM (HM514100AS, HM514100JP) sealed in SOJ package. An outline of the HB56A48 is 30-pin single in-line package. Therefore, the HB56A48 makes high density mounting possible without surface mount technology. The HB56A48 provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ. Icc- m m _____m ___m _ - ! - mnn I ! 30 1 pin pin 0094-1 • FEATURES • 30-pin Single In-line Package Lead Pitch ................................ 2.54mm • Single 5V (±10%) Supply • High Speed Access Time ....... 60 ns/70 ns/80 ns/100 ns (max) • Low Power Dissipation Active Mode .................. 4840 mW14400 mWI 3960 mW/3520 mW (max) Standby Mode ........................ 88 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycle ........................... (16 ms) • 3 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh Hidden Refresh • TTL Compatible Pin No. Pin Name Pin No. Pin Name I Vee 16 DQ4 2 CAS 17 As 3 DQo IS A9 4 Ao 19 AIO Pin Name Function Address Input Ao-A9 RAS Refresh Address Input CAS Column Address Strobe Row Address Strobe WE Read/Write Enable DQo-DQ7 Data-inlData-out Vee Vss Ground NC No Connection Al 20 DQ5 6 DQ\ 21 WE 7 A2 22 VSS S A3 23 DQ6 9 Vss 24 NC DQ7 11 DOl A4 25 26 NC 12 As 27 RAS NC 10 • PIN DESCRIPTION Ao-AIO 5 13 DQ3 2S 14 ~ 29 NC 15 A7 30 Vee Power Supply ( + 5V) • ORDERING INFORMATION Package 30-pin \ SIP Socket Type 30-pin SIP Lead Type 0.945 Inch Height 0.805 Inch Height HB56A4SBRlGBR-6A 70ns - SOns HB56A4SB/GB-S lOOns HB56A48B/GB-1O Access Time 60ns Note: 30-pin \ SIP Socket Type 30-pin SIP Lead Type 30-pin SIP Low Profile Lead Type 0.9S9 Inch Height O.SIO Inch Height 0.591 Inch Height 0.500 Inch Height HB56A4SAR-6A - HB56A4SATR-6A HB56A4SBRlGBR-7A - HB56A4SAR-7A - HB56A4SATR-7A HB56A4SBRlGBR-SA HB56A4SA-S HB56A4SAR-8A HB56A48AT-8 HB56A48ATR-8A HB56A48BRlGBR-IOA HB56A48A-1O HB56A48AR-IOA HB56A48AT-1O HB56A4SATR-IOA 30-pin SIP Low Profile Lead Type I. Following the specification of the contact pad. HB56A48B-XX, HB56A48BR-XX: HB56A48GB-XX, HB56A48GBR-XX: solder gold eHITACHI 722 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 HB56A48 Series • BLOCK DIAGRAM AO (4) (5) Al A2 A3 A4 AS A6 A7 A8 A9 Al0 (7) ~----(11) M3 -------(12) I (15) (17) I (18) (19) r-RAS CAS WE (13) DQ3 Din (14) (27) Din Dout Ml Din Dout MO AO-Al0 Din RAS (2) Dout W CAS (21) Dout M2 WE W(10) DQ2 --.J (6) DQl ~ (3) - DQO - - I I Dout M6 Din Dout Din Dout M4 Din Dout (25) Din M5 ' - - - AO-Al0 RAS I M7 W DQ7 (23) DQ6 (20) DQ5 l-J (16) r--- l-J l-J DQ4 I- CAS WE I- Vee (1) Vee Vss Vss ~t---l""""'----~' (9) T MO - 7 Vee C=0.22pFx8 ~l---"""'----.~ MO - 7 Vss 0094-2 Note: MO-M7[HB56A4SXX-XXA]: HM514100AS MO-M7[HB56A4SXX-S/I0: HM514100JP ~HITACHI Hitachi America, Ltd.• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300 723 HB56A48 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Unit: mm (inch) • PHYSICAL OUTLINE • HB56A48AR Series 8120 3.197 254 0.100 377 0.148 I.. 5 28 max, 1 0208 • II -- 00.020 so .1. 025 0010 eo "0 - '" NO 0094-3 • HB56A48ATR Series 90.14 3.549 '1- ~I~:; ; : ...::=:;;;;::;;;;:::~]~:;;;;:;;;;::;;;::=::;;;;:::;;;;]'-"I~;;;;::;;;;::=:;;;;::;;;;::;;;:]-:;;;[=::;;;;:=:;;;;::=];;:-onnonnoono---;;;oomoo;;;;;o 00000 1 824 0.324 050 0.020 0100 00000 ~ 8 89 max 0350 ' I 1__ ~ 110 1'-0 N.n _0 025 0.010 , eO "0 '" No I .. 0094-4 • HB56A48BR/GBR Series 528 max 0208 8890 3500 8214 3.234 1 27 II ofso+762 0.300 7366 2.900 Detail A 02,m.. tW'80'!!!!h 0010 0011 Note: Following the specification of the contact pad. Part No. HB56A48BR-XX HB56A48GBR-XX • 724 ~ Contact Pad Solder Gold ill 0070 0094-' HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 HB56A48 Series • PHYSICAL OUTLINE (continued) Unit: mm (inch) • HB56A48A Series 1<_ _ _ _ _ _ _ _ _ _--'88.9 _ _ _ _ _ _ _ _ _ _ ' 3.5 ODOO o OOOOO OOOOU 00000 00000 o 0 0094-6 • HB56A48AT Series 90.14 0094-7 • HB56A48B/GB Series 1<_ _ _ _ _ _ _ _ _ _----"88.9 _ _ _ _ _ _ _ __ -3.5 Hhl~max 1·_~0.208 00000 UOOOO 00000 00000 ~ _i:~82.!~.----- 1<______ ~ 1.27-1 I. 0.05" r' 3.234 _ __7;L66 _ _ _ _ _ _ _ _ _ _>I 2.90 A 025ma. @180m ,n. 0.010 Note: Following the specification of the contact pad. 0011 ~ ill Part No. 0.070 Contact Pad HB56A48B-XX Solder HB56A48GB-XX Gold Detail A 0094-8 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 725 HB56A48 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Voltage on Any Pin Relative to vss VT Symbol -1.0to +7.0 V Supply Voltage Relative to Vss VCC -1.0to +7.0 V Short Circuit Output Current lout 50 rnA Power Dissipation PT S W Operating Temperature Topr Oto + 70 'C Storage Temperature Tst~ - 55 to + 125 'C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter Symbol Supply Voltage 0 to + 70'C) = Min Typ Max Unit VSS 0 0 0 V Note VCC 4.5 5.0 5.5 V I Input High Voltage VIR 2.4 5.5 V I Input Low Voltage VIL -1.0 - O.S V I Note: I. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to +70'C, vee = 5V ±10%, vss = OV) HB56A4SB/GB/BR/GBRIAIAR/ATI ATR Parameter Operating Current Standby Current RASbnly Refresh Current Symbol ICC! -6A -7A -S/-SA -10/-IOA Unit Min Max - SSO - SOO - 720 - 640 rnA tRC = min - 16 - 16 - 16 - 16 rnA TTL Interface RAS, CAS = VIR Dout = High-Z - S - S - S - 8 rnA CMOS Interface RAS, CAS <: VCC - 0.2V Dou! = High-Z - 880 - 800 - 720 - 640 rnA tRC = min 2 I Min Max Min Max Standby Current ICCS - 40 - 40 - 40 - 40 rnA RAS = VIR CAS = VIL Dout = Enable CAS Before RAS Refresh Current ICC6 - 880 - 800 - 720 - 640 rnA tRC = min Page Mode Current ICC7 - 880 - 800 - 720 - 640 rnA tpc = min Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 /LA OV :s VIN :s 7V Output Leakage Current ILO -10 10 -10 10 -10 10 -10 10 /LA OV:s Vout:S 7V Dout = Disable Output High Voltage VOH 2.4 Vce 2.4 Vce 2.4 Vec 2.4 Vec V lout = - 5mA Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 V lout = 4.2 rnA Notes: I. ICC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIL. 3. Address can be changed once or less while CAS = VIR. @HITACHI 726 Note Max ICC2 ICC3 Test Condition Min Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1,2 1,3 HB56A48 Series • Capacitance (TA = 25°C, Vee = 5V ±100/0) HB56A4S Parameter Symbol Input Capacitance (Address) CIl Input Capacitance (Clock) CI2 BR/GBR/AR/ATR AlAT/B/GB Note 65 pF 1 SI pF 1 pF 1,2 Max Typ Max - 55 - 30 6S 17 CliO 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out. Input/Output Capacitance (DQo_ 7) Notes: Unit Typ • AC Characteristics (TA = 0 to +70"C, Vee = 5V ±100/0, Vss Read, WrIte and Refresh Cycle (Common Parameters) = OV)1,12, 15 HB56A4SB/GB/BR/GBR/AIAR/AT/ATR Parameter Random Read or Write Cycle Time Symbol -6A -7A -SA -lOA -S -10 Unit Min Max Min Max Min Max Min Max Min Max Min Max tRC 110 - 130 - 150 - ISO - 150 - 180 - ns RAS Precharge Time tRP 40 - 50 - 60 - 70 - 60 - 70 - ns RAS Pulse Width tRAS 60 10000 70 10000 SO 10000 100 10000 80 10000 100 10000 ns teAS 15 10000 20 10000 20 10000 25 10000 20 10000 25 10000 ns CAS Pulse Width Row Address Setup Time tASR 0 10 10 - 15 - 0 10 - - tRAH - 0 Row Address Hold Time 10 - 15 - ns ns Column Address Setup Time tASC 0 - 0 - 0 - 0 - 0 - 0 - ns Column Address Hold Time 0 0 0 Note leAH 15 - 15 - 15 - 20 - 15 - 20 - ns RAS to CAS Delay Time tRCD 20 50 20 50 20 60 25 75 20 60 25 75 ns S RAS to Column Address Delay Time tRAD 15 35 15 35 15 40 20 55 15 40 20 55 ns 9 20 RAS Hold Time tRSH 15 20 - 25 - ns 70 SO - - 60 - 25 teSH - 20 CAS Hold Time 100 SO - 100 - ns CAS to RAS Precharge Time teRP 10 - 10 - 10 - 10 - 10 - 10 - ns Transition Time (Rise and FaIl) tT 3 50 3 50 3 50 3 50 3 50 3 50 ns 7 Refresh Period tREF - 16 - 16 - 16 - 16 - 16 - 16 ms 17 Read Cycle HB56A4SB/GB/BR/GBR/AIAR/AT/ATR Parameter -6A Symbol -7A -SA -lOA Min Max Min Max Min Max 70 35 - -S Min Max Min - 100 - 20 25 40 - 45 - -10 Unit Max 80 - 100 ns 2,3,16 25 25 ns 3,4,14 40 - 45 ns 3,5,14,16 Access Time from RAS IRAc Access Time from Address !cAc tAA - 60 Access Time from CAS 30 - Read Command Setup Time tRCS 0 - 0 - 0 - 0 - 0 - 0 - ns Read Command Hold Time to CAS tRCH 0 - 0 - 0 - 0 - 0 - 0 - ns Read Command Hold Time to RAS tRRH 0 - 0 - 0 - 0 - 10 - 10 - ns 15 20 SO Note Min Max eHITACHI Hitachi America, Ltd. 0Hitachi Plaza 02000 Sierra Point Pkwy. 0Brisbane, CA 94005-1819 0(415) 589-8300 727 HB56A48 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Read Cycle (continued) HB56A4SB/GB/BR/GBR/AIAR/AT/ATR Parameter Symbol -6A Min -7A Max Min -SA Max Min -S -lOA Min Max Max -10 Max Min Unit Min Max Note Colnmn Address to RAS Lead Time tRAL 30 - 35 - 40 - 45 - 40 - 45 - ns Output Buffer Tum-olTTime toFF 0 15 0 20 0 20 0 25 0 20 0 25 ns 6 Unit Note Max Min 10 Write Cycle HB56A4SB/GB/BR/GBR/AIAR/AT/ATR -6A Symbol Parameter -SA -7A Min Max Min Max -lOA Min Max Min -S Min Max -10 Max Write Command Setup Time twcs 0 - 0 - 0 - 0 - 0 - 0 - ns Write Command Hold Time tWCH 15 - 15 - 15 - 20 - 15 - 20 - ns Write Command Pulse Widtb twp 10 - 10 - 10 - 20 - 15 - 20 - ns Write Command to RAS Lead Time tRWL 15 - 20 - 20 - 25 - 25 - 25 - ns Write Command to CAS Lead Time tcwL 15 - 20 - 20 - 25 - 25 25 0 - 0 0 0 IS - 20 - - ns - - 15 - 20 - Data-in Setup Time tDS 0 - 0 Data-in Hold Time tnH 15 - IS ns ns 11 11 Refresh Cycle HB56A4SB/GB/BR/GBR/AlAR!AT/ATR Parameter Symbol -6A -7A Min Max Min -lOA -SA Max -S Min Max Min Max Min -10 Max Unit Min Max CAS Setup Time (CAS Before RAS Refresb Cycle) tcsR 10 - 10 - 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) !eHR 10 - 10 - 10 - 10 - 20 - 20 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - 10 - 10 - ns Note Fast Page Mode Cycle HB56A4SB/GB/BR/GBR/AlAR!AT/ATR Parameter Symbol -SA -7A -6A -lOA -S -10 Unit Note Min Max Min Max Min Max Min Max Min Max Min Max Fast Page Mode Cycle Time tpc Fast Page Mode !ep CAS Precharge Time 40 - 45 - 50 - 55 - 55 - 55 - ns 10 - 10 - 10 - 10 - 10 - 10 - ns Fast Page Mode RAS Pulse Widtb tRASC - 100000 - 100000 - 100000 - 100000 - 100000 - 100000 ns 13 Access Time from CAS Precharge tACP - 35 - 40 - 45 - 50 - 50 - 50 ns 14,16 tRHCP 35 - 40 - 45 - 50 - 50 - 50 - ns RAS Hold Time from CAS Precharge $ 728 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56A48 Series Test Mode Cycle HB56A48B/GB/BR/GBR/AIAR/AT/ATR Parameter Symbol -6A Min -7A Max -8A Min Max -8 -lOA Min Max Min Max Unit Max Min Max - 0 20 - Test Mode WE Setup Time tws 0 - 0 - 0 - 0 - 0 Test Mode WE Hold Time tWH 10 - 10 - 10 - 10 - 20 Notes: -10 Min Note ns ns I. AC measurements assume tT = 5 ns. 2. Assumes that tRCD S tRCD (max) and tRAD S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD <: tRCD (max), tRAD S tRAD (max). 5. Assumes that tRCD s tRCD (max), tRAD <: tRAD (max). 6. toFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIR (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIR and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAe9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 10. Early write cycle only (twcs <: twcs (min». II. These parameters are referenced to CAS leading edge in an early write cycle. 12. An initial pause of 100 JJ.s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS-only refresh). 13. tRASC is determined by RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or !cAC or tACP. 15. Test mode operation specified in this data sheet is 8-bit test function controlled by control address bits ... RA 10, CA 10 and CAD. This test mode operation can be performed by WE and CAS before RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of eight test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. Data output pin is D out and data input pin is Din. In order to end this test mode operation, perform a RAS only refresh cycle or a CAS before RAS refresh cycle. 16. In a test mode read cycle, the value of tRAC, tAA and tACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 17. tREF is determined by 1,024 refresh cycles. ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 729 HB56A48 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORM • Read Cycle tRC tRP Address teAC tOFF Valid Output Dout tRAC Din High-Z ~ : Don't care 0094-9 eHITACHI 730 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1619 • (415) 569-6300 HB56A48 Series • Early Write Cycle Address Dout High-Z Din ~ : Don't care 0094-10 $ HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 731 HB56A48 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle tRC Address High-Z Dout WE : Don't care 2 ~: Don't care 0094-11 • CAS Before RAS Refresh Cycle tRC lRP tCSR 1 Address, Din: Don't care 2 Dout: High-Z 3 ~: Don't care 4 WE =VIH 0094-12 • 732 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HB56A48 Series • Hidden Refresh Cycle Dout Dout 1 ~ : Don't care 0094-13 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 733 HB56A48 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read Cycle tRASC Address Dout High-Z Din ~ : Don't care 0094-14 $ 734 HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 HB56A48 Series • Fast Page Mode Early Write Cycle tRASC Address Dout High-Z Din ~ ; Don't care 0094-15 @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 735 HB56A48 Series • TEST MODE CYCLE CBR or RAS only refresh 2 ~ : Don't care 3 Address, Din: Don't care 0094-16 • Test Mode Set Cycle Address OPEN Dout ~ : Don't care 0094-17 @HITACHI 736 Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HB56A48 Series • Test Mode Reset Cycle CAS Before RAS Refresh Cycle Address OPEN Dout ~ : Don't care 0094-18 RAS Only Refresh Cycle Address Row OPEN Dout 1 ~ : Don't care 2 Refresh address: AO - A9 (AXO - AX9j 0094-19 • HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 737 HB56A19 Series 1,048,576-Word x 9·Blt High Density Dynamic RAM Module • DESCRIPTION The HB56A19 is a 1M x 9 dynamic RAM module, mounted nine 1-Mbit DRAM (HM511000JP) sealed in SOJ package. An outline of the HB56A19 is 30-pin single in-line package having Lead types (HB56A19A, HB56A19An, Socket type (HB56A19B). Therefore, the HB56A19 makes high density mounting possible without surface mount technology. The HB56A19 provides common data inputs and outputs and also provides separate 1/0 on parity bit for parity check. Its module board has decoupling capacitors beneath each SOJ. • FEATURES • 30-pin Single In-line Package Lead Pitch ..................................................... 2.54mm • Single 5V (±10%) Supply • High Speed Access TIme ..................... 60 ns/70 ns/80 ns/100 ns/120 ns (max) • Low Power Dissipation Active Mode ...... 4455 mW/3960 mW/3465 mW/2970 mW/2475 mW (max) Standby Mode ............................................. 99 mW (max) • Fast Page Mode Capability • 512 Refresh Cycle ................................................... (8 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible • ORDERING INFORMATION Access Time Pin Name Pin No. Pin Name I Vee 16 DQ4 2 CAS 17 AS 3 DQo 18 A9 4 Ao 19 NC 5 Al 20 DQs 6 DQI 21 WE 7 A2 22 VSS 8 A3 23 DQ6 9 Vss 24 NC 10 DQ2 25 D 3175 '1 II 2.03 0.080 I I 762 0.300 Vfo:ji5 II 2.54 0.100 178 • • 0.070 1.27 II o~ 7366 2.900 0153-6 Detail A ~.80mln. o25m"'l 0"0 ~'.71 Note: Following the specification of the contact pad Part No. Contact Pad HB56AI9B-6L/7L/SL/IOL/12L Solder HB56AI9GB-6L/7L/SL/IOL/I2L Gold !1! 0.070 @HITACHI 746 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 0153-7 HB56A19L Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit (Input) Yin -1.0to + 7.0 V (Output) Vout -1.0to +7.0 V Supply Voltage Relative to Vss VCC -1.0to +7.0 V Short Circuit Output Current lout 50 rnA Voltage on Any Pin Relative to Vss I I Power Dissipation PT 9 W Operating Temperature Topr Oto + 70 ·C Storage Temperature Tstg - 55 to + 125 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70·C) Parameter Symbol Min Typ Max Unit Supply Voltage VSS 0 0 0 V VCC 4.5 5.0 5.5 V I Input High Voltage VIR 2.4 - 5.5 V 1 Input Low Voltage VIL -1.0 - 0.8 V I Note: Note I. All voltage referenced to VSS. • DC Electrical Characteristics (TA = 0 to +70·C, Vee = 5V ±10%, Vss = OV) HB56AI9/ATIB/GB Parameter Symbol -6L Min -7L -8L -12L Test Conditions Note Max - 810 - 720 - 630 - 540 - 450 - 18 - 18 - 18 - 18 - 18 TTL Interface rnA RAS, CAS = VIH, D out = High-Z - 2.7 - 2.7 - 2.7 - 2.7 - 2.7 CMOS Interface rnA RAS, CAS ~ Vcc - 0.2V, Dout = High-Z RASOnly Refresh Current ICC3 - 810 - 720 - 540 - 450 - 405 rnA tRc Min 2 Battery Back Up ICC4 Current - 2.7 - 2.7 - 2.7 - 2.7 - 2.7 rnA tRC = 125~ CAS Before RAS Refresh 4 Staodby Current ICC5 - 45 - 45 - 45 - 45 - 45 RAS rnA CAS D out CAS Before RAS Refresh Current ICC6 ICC! Standby Current Max Min Max Min Unit Min Operating Current Min -IOL Max Max ICC2 Fast Page Mode ICC? Current Input Leakage Current rnA tRC = Min = = VIR, = VIL, = - 720 - 630 - 540 - 450 - 360 rnA tRC = Min - 720 - 630 - 450 - 450 - 360 rnA tpc = Min -10 10 -10 10 -10 10 -10 10 -10 10 /loA OVoS Yin oS 7V Output Leakage ILO Current -10 10 -10 10 -10 10 -10 10 -10 10 /loA OV oS Vout:S 7V D out = Disable Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V lout = Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 0 0.4 V lout = 4.2 rnA I. 2. 3. 4. I Enable ILl Notes: 1,2 1,3 -5mA Icc depends on output load condition when the device is selected, Icc max is specified at the output open condition. Address can be changed less than three times while RAS = V IL. Address can be changed :S I time while CAS = VIR. tRAS = tRAS (min) to 1 fLs. Input voltage: All pins: VIR ~ VCC - 0.2V or VIL :S 0.2V. ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 747 HB56A19L Series • Capacitance (TA = 25·C, Vcc = 5V ±10%) Parameter Symbol Typ Max Unit Note Input Capacitance (Address) CII 60 pF I Input Capacitance (Clock) CI2 - 75 pF I Input/Output Capacitance (DQO_7) CliO - 17 pF 1,2 Input Capacitance (PD) CI3 - 10 pF I 12 pF 1,2 Output Capacitance (PQ) Notes: Co 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out . • AC Characteristics (TA = 0 to + 70·C, Vcc = 5V ± 10%, Vss Read, Write, and Refresh Cycle (Common Parameters) OV)1, 12 = HB56AI9/ATIBIGB Parameter -6L Symbol Min -7L Max - -SL Min Max Min 130 - 160 50 -IOL Max - -12L Unit Note Min Max Min Max 190 - 220 - ns SO - 90 - ns Random Read or Write Cycle Time tRC 120 RAS Precharge Time tRP 50 RAS Pulse Width tRAS 60 10000 70 10000 SO 10000 100 10000 120 10000 ns CAS Pulse Width tCAS 20 10000 70 10000 25 10000 25 10000 30 10000 ns Row Address Setup Time tASR 0 - 0 - 0 - 0 - 0 - ns Row Address Hold Time tRAH 10 - 10 - 12 - 15 - 15 - ns Column Address Setup Time tASC 0 - 0 - 0 - 0 - 0 - ns Column Address Hold Time tCAH 15 - 15 - 20 - 20 - 25 - ns RAS to CAS Delay Time tRCD 20 40 20 50 22 55 25 75 25 90 ns S RAS to Column Address Delay Time tRAD RAS Hold Time tRSH 15 30 15 35 17 40 20 55 20 65 ns 9 20 - 20 - 25 - 25 30 - ns CAS Hold Time 120 - ns 10 70 tCSH 60 - 70 - SO - 100 CAS to RAS Precharge Time tCRP 10 - 10 - 10 - 10 - Transition Time (Rise and Fall) tT 3 50 3 50 3 50 3 50 3 50 ns 7 Refresh Period tREF 64 - 64 - 64 - 64 ms 15 Max Min Max - 64 - ns Read Cycle HB56A19A1 AT/B/GB Parameter -6L Symbol -IOL -SL -7L Min -12L Unit Note Min Max Min Max Min Max 70 - SO - 100 - 120 ns 2,3 20 - 25 - 25 30 ns 3,4 40 - 45 - 55 ns 3,5 - 0 - ns tRAC - 60 Access Time from CAS tCAC - 20 Access Time from Address tAA - 30 - Read Command Setup Time tRCS 0 - 0 - 0 - 0 Read Command Hold Time to CAS tRCH Read Command Hold Time to RAS tRRH 0 - 0 - 0 - ns 10 10 - 0 - - 0 10 10 - 10 - ns 30 - 35 - 40 - 45 - 55 - ns - 20 - 20 - 20 - 25 - 30 ns Access Time from RAS Column Address to RAS Lead Time tRAL Output Buffer Turn-off Time tOFF! 35 ~HITACHI 748 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Flrisbane, CA 94005-1819· (415) 589-8300 6 HB56A19L Series Write Cycle HB56AI9A/ATIB/GB Parameter Symbol -6L -7L Min Max Min -SL Max Max - Write Command Setup Time twcs 0 - 0 tWCH 15 - 0 Write Command Hold Time 15 - 20 Write Command Pulse Width twp 10 - 10 - 15 Data-in Setup Time tDS 0 - 0 - 0 tDH 15 - 15 - 20 Data-in Hold Time -IOL Min -12L Max Min Max 0 - - 25 15 - 20 0 - 0 0 20 20 Unit Note Min 25 ns 10 ns ns ns 11 ns 11 Refresh Cycle HB56AI9A/ATIB/GB Parameter Symbol -6L -7L Min Max Min -SL Max -IOL Min Max Min -12L Max Unit Note Min Max CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 15 - 15 - 20 - 20 - 25 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - 10 - ns Max Min Fast Page Mode Cycle HB56AI9A/ATIB/GB Parameter Symbol -6L Min -7L Max Min -SL Max Min -IOL Max Min -12L tpc 45 - 50 - 55 - 55 - 65 Fast Page Mode CAS Precharge Time tcp 10 - 10 - 10 - 10 - 15 Fast Page Mode RAS Pulse Width tRASC Access Time from CAS Precharge tACP 40 Fast Page Mode Cycle Time RAS Hold Time from CAS Precharge tRHCP Notes: 100000 - 100000 - 100000 40 - 45 - 50 - - 45 - 50 - 50 50 - - 60 100000 Unit Note Max - ns ns 100000 ns 60 ns - ns 13 14 I. AC measurements assume tT = 5 ns. 2. Assumes that tRCD S tRCD (max) and tRAD S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD ~ tRCD (max), tRAD S tRAD (max). 5. Assumes that tRCD S tRCD (max), ~ tRAD (max). 6. tOFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. S. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAe (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. Early write cycle only (twcs ~ twcs (min». 11. These parameters are referenced to CAS leading edge in an early write cycle. 12. An initial pause of 100 I-'s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). 13. tRASC is determined by RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tACP. 15. tREF is determined by 512 refresh cycles. @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 749 HB56A19L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read Cycle tRC Address tCAC tOFF Valid Dout Output tRAC High-Z Din ~ : Don't care 0153-8 $ 750 HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brillbane, CA 94005-1819. (415) 589-8300 HB56A19L Series • Early Write Cycle tRC Address Din Dout High-Z ~ : Don't care 0153-9 @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 751 HB56A19L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle tRC Address High-Z Dout 1 WE : Don't care 2 ~: Don't care 0153-10 • CAS Before RAS Refresh Cycle tRC tRP Address, Din: Don't care 2 Dout: High-Z 3 ~: Don't care 0153-11 ~HITACHI 752 Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56A19L Series • Fast Page Mode Read Cycle tRASC ~ tRHCP ----, / i\ tCSH tT tRCD tCAS ,tc~s Address ~ tAsc;, ~ ~ ~ ~ ~ 1"-' tCRP tRAl I~ tASc;, l~ ItASc;, ,~ ~ ~ ~ -column2~ ~ ColumnN I~ ~ ~/- '~ tRCS ~ \.- tRP 1\ / tcp tRAD I~ '1\ / i\ tASR , tRSH tCAS t~~ '~ ~ tRCH ~ tRCS tRClt ~~ ItAA tRCS tCAC ~~ tAA tACP tOFF Dout r Valid ~Output ~ tCAC tAA tACP tOFF rValid ~Output2 ~//.i~ .tRRH ~//.i' I"///.i tCAC ~..o tOFF I~ Valid Output N I}- tRAC High-Z Din ~ : Don't care 0153-12 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 753 HB56A19L Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Early Write Cycle tRASC Address Din Dout High-Z ~ : Don't care 0153-13 .HITACHI 754 Hitachi America, Lid.• Hitachi Plaza. 2000 Sierra Point Pkwy•• Brisbane, CA 94005-1819. (415) 589-8300 HB56C19 Series 1,048,57S-Word x 9-Bit High Density Dynamic RAM Module • PIN DESCRIPTION • DESCRIPTION The HB56C19 is a 1M x 9 static column mode dynamic RAM module, mounted nine 1-Mbit DRAM (HM511002JP) sealed in SOJ package. An outline of the HB56C19 is 30-pin single in-line package having Lead types (HB56C19A, HB56C19AT), socket type (HB56C19B). Therefore, the HB56C19 makes high density mounting possible without surface mount technology. The HB56C19 provides common data inputs and outputs and also provides separate I/O on parity bit for parity check. Its module board has decoupling capacitors beneath each SOJ. Pin No. Pin Name Pin No. Pin Name I Vee CS 16 DQ4 2 17 As 3 DQo 18 A9 4 19 NC • FEATURES 5 Ao Al 20 DQs • 30-pin Single In-line Package Lead Pitch ..................................................... 2.54mm • Single 5V (± 10%) Supply • High Speed Access Time ................................. 80 ns/100 ns/120 ns (max) • Low Power Dissipation Active Mode ......................... 3465 mW/2970 mW/2475 mW (max) Standby Mode ............................................. 99 mW (max) • Static Column Mode Capability ·512 Refresh Cycle ................................................... (8 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible 6 DQI 21 WE 7 A2 22 VSS 8 A3 23 DQ6 9 VSS 24 NC 10 DQ2 25 DQ7 • ORDERING INFORMATION 80ns lOOns 120 ns 30-pin SIP Low Profile Lead Type 30-pinSIMM Socket Type HB56CI9A-8A HB56CI9AT-8A HB56CI9B-8A HB56C19A-12A HB56CI9AT-IOA HB56CI9AT-12A HB56CI9B-IOA HB56C19B-12A • PIN OUT II I I 00--·---·--·---·-·-----·--·---·---00 1 pin 26 PQ 27 RAS PCS 13 DQ3 28 14 A6 29 PD 15 A7 30 Vee Pin Name 30-pin SIP Lead Type HB56CI9A-IOA ~ As • PIN DESCRIPTION Package Access Time II 12 Function Ao-A9 Address Input Ao-As Refresh Address Input RAS Row Address Strobe CS Chip Select PCS Parity Chip Select WE ReadIWrite Enable DQo-DQ7 Data-in/Data-out PD Panty Data-m PQ Parity Data-out Vee Power Supply (+ 5V) VSS NC Ground Non-Connection 30 pin 0123-1 @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 755 HB56C19 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM AO A1 A2 AS A4 AS A6 (4) (5) (7) ill (11 ) (12) (14) A7 11~ (17) I AS A9 (1S) I (2) Din Dout Dout Din Dout ~ (13) D03 ~(10)D02 W - W CAS (21) Din Dout M3 Din M1 RAS M4 M2 I--- AO-A10 (27) I (6) D 01 (3) D 00 (26) PD I-- WE I-(2S) 1·-M9 ICAS I '---- I M8 Din Dout Din Dout Din Dout Din LJ .-J .-J (29) PO (25) D07 DoutW M7 M6 MS AO-A10 RAS I Din Dout (23) (20) I--- (16) ~ D06 DOS D04 - CAS WE - Vee (1) ~30 Vee ..@QU vss!J Vss 22 -.l. T • M1-9Vcc C = 0.2211F x 9 r----....l-----i.~ M1 - 9 Vss 0123-2 ~HITACHI 756 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56C19 Series • mm PHYSICAL OUTLINE Unit: (inch) • HB56C19A Series 81.2(3.197 ) 0.25(0.0098) 0.50(0.0197 ) 2.54(0.1) 0123-3 • HB56C19AT Series 88.9( 3.500) 8.89max. 0123-4 • HB56C19B Series 889(3500) 3.38(0.133) B2.14( 3.234) - F . = '"E. d ...-211 -d I 1.\4min.(2x) (0.045min. ) 0 p 0 p jO 0 0 10 0 ~ _0 0 If 0 0 0 0 _0 ''1nnnnnnnnnnnnnnl _C 0 q lnm..L I 6.35 ( 0.250)/ (RO.067max. ) 1.7max. 2.03( 0.080) 5.28max. (0.208m... ) 30r - '::.. 7.62 (0.300 ) BASIC BOTH SIDES 2.54(0.100) BASIC BOTH SIDES 1.78(0.070) - \ t 1.27±0.127 (0.05 ± 0.005) t2.S4min. (0.1 OOmin. I 3.1 7± 0.127( ~.125± 0.005) (0.07min 73.66(2.900)REF 0123-5 Note: I. The plating of the contact finger is solder coat. $HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589·8300 757 HB56C19 Series • ABSOLUTE MAXIMUM RATINGS Value Unit Voltage on Any Pin Relative to Vss Parameter VT Symbol - 1.0 to + 7.0 V Supply Voltage Relative to Vss vcc -1.0to +7.0 V Short Circuit Output Current lout 50 rnA Power Dissipation PT 9.0 W Operating Temperature Topr Oto + 70 Storage Temperature T stg - 55 to + 125 'c 'c • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70'C) Parameter Min Typ Max Unit VSS 0 0 0 V Symbol Supply Voltage Note VCC 4.5 5.0 5.5 V 1 Input High Voltage Vm 2.4 - 5.5 V 1 Input Low Voltage VIL -1.0 - 0.8 V 1 Note: I. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss = 0V) HB56CI9A/AT/B Parameter -8A Symbol Min Operating Current Standby Current IcC! - -12A -lOA Max Min Max 630 - 540 Min - Unit Test Conditions Note Max 450 rnA tRC = Min - 18 - 18 - 18 rnA TTL Interface RAS, CAS = Vm, Dout = High-Z - 9 - 9 - 9 rnA CMOS Interface RAS, CAS l!: VCC - 0.2V, D out = High-Z tRC ICC2 RASOnly Refresh Current ICC3 - 540 - 450 - 405 rnA Standby Current ICC5 - 45 - 45 - 45 CAS Before RAS Refresh Current ICC6 - 540 - 450 - 360 1,2 = Min 2 rnA = VIR, CS = VIL Dout = Enable 1 rnA tRC 360 rnA Static Column Mode tpc = Min ~S = Min Static Column Mode Current ICC9 Input Leakage Current ILl -10 10 -10 10 -10 10 /LA OV S Yin S 7V Output Leakage Currernt ILO -10 10 -10 10 -10 10 /LA OV S Vout S 7V, D out = Disable Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V lout Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 V lout Notes: - 540 - - = -5mA = 4.2 rnA I. ICC depends on output load condition when the device is selected, Icc max is specified at the output open condition. 2. Address can be changed less than three times while RAS = V IL. 3. Address can be changed once or less while CS = Vm . • 758 450 HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 1,3 HB56C19 Series • Capacitance (TA = 25'C, vee = 5V ±10%) Parameter Symbol Typ Input Capacitance (Address) Cll Input Capacitance (Clock) CI2 Input/Output Capacitance (DQo-DQ7) CliO - Input Capacitance (PD) CI3 - Co - 12 Output Capacitance (PQ) Notes: Max Unit 60 pF Note I 75 pF 1,2 17 pF 1,2 10 pF I pF 1,2 I. Capacitance measured with Boonton Meter or effective capacitance measuriug method. 2. CS = VIR to disable D out . • AC Characteristics Please show at HM511002A series about AC Characteristics. But don't use by Delayed Write Cycle, because the HB56C19 provides common data inputs and outputs. Please use by Early Write Cycle. (twes :<: twes (min)). ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 759 HB56G19 Series 1,048,57S·Word x 9·Bit High Density Dynamic RAM Module • DESCRIPTION • PIN OUT The HB56G19 is a 1M x 9 dynamic RAM module, mounted two 4 Mbit DRAM (HM514400AS) sealed in SOJ package and 1 Mbit DRAM (HM511000AJP) sealed in SOJ package. An outline of the HB56G19 is 30-pin single in-line package having lead types (HB56G19A), socket type (HB56G19BI GB). Therefore, the HB56G19 makes high density mounting possible without surface mount technology. The HB56G19 provides common data inputs and outputs and also provides separate 1/0 on parity bit for parity check. Its module board has decoupling capacitors beneath each SOJ. • FEATURES • 30-pin Single In-line Package Lead Pitch ................................ 2.54mm • Single 5V (± 10%) Supply • High Speed Access Time ....... 60 ns/70 ns/80 ns/100 ns (max) • Low Power Dissipation Active Mode .................. 1705 mW/1540 mWI 1375 mW/1210 mW (max) Standby Mode ........................ 33 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycle ........................... (16 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible • ORDERING INFORMATION Part No. Access Time HB56G19A-6A 60ns HB56G19A-7A 70ns HB56G19A-8A 80ns HB56GI9A-IOA lOOns HB56G 19B/GB-6A Package 3D-pin SIP Low Profile Lead Type r-------------------------------~ I! nn- ------- -------------nn HB56GI9B/GB-7A 70ns 80ns HB56GI9B/GB-IOA lOOns 0154-1 Pin No. Pin Name Pin No. Pin Name I Vee CAS 16 DQ4 2 17 As 3 DQo 18 4 Ao 19 A9 NC DQs 5 AI 20 6 DQI 21 WE 7 A2 22 Vss DQ6 8 A3 23 9 Vss 24 NC 10 DQ2 25 DQ7 11 A4 26 PQ 12 As 27 RAS 13 DQ3 28 PCAS 14 A6 29 PD 15 A7 30 Vee • PIN DESCRIPTION Pin Name 30-pin SIP Socket Type Note: Following the specification of the contact pads. HB56GI9B-XX :solder HB56GI9GB-XX :gold Function Ao-A9 Address Input Ao-A9 Refresh Address Input RAS Row Address Strobe CAS,PCAS Column Address Strobe WE ReadIWrite Enable DQo-DQ7 Data-iniData-out PD Parity Data-in PQ Parity Data-out Vee Power Supply ( + 5V) Vss Ne Ground No Connection ~HITACHI 760 I pin 1 pin 60ns HB56G19B/GB-8A ! 30 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56G19 Series • BLOCK DIAGRAM (4) AO (5) Al (7) A2 (8) A3 (11) A4 (12) AS (14) A6 (15) A7 (17) AS (18) A9 (27) - MO AO-A9 1/ 01 RAS 1102 CAS 1/03 WE 1/04 (6) (10) (2) (21) (3) Vee Vss (13) DOO DOl HMs14400AS D02 D03 Of~ t1~Cl Ml AO-A9 1/01 RAS 1/02 CAS 1/03 WE 1/04 Vee Vss (16) (20) D04 (23) DOS (25) HMs14400AS D06 D07 OE~ t1~C2 - M2 AO-A9 (2S) (26) Dout RAS CAS Din PO (29) HMsl1000AJP PD WE Vee Vss H~ Vc Ve C3 e (1) e~ Vss Vs s (9) (22) 0154-2 ~HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 761 HB56G19 Series • mm PHYSICAL OUTLINE Unit: inch • HB56G19A Series 7874 , 0 2 max , 0 o 00 .... '" ~o 025 0,010 0154-3 • HB56G19B/GB Series 3,500 I~ I 27 0.050 Detail A ~O 025m .. 0.010 Note: Following the specification of the contact pads. Part No. Contact Pad HB56G19B-XX Solder HB56GI9GB-XX Gold 1,80m,n. ~ ~ ill 0010 0154-4 ~HITACHI 762 Hitachi America, Ltd,. Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56G19 Series • ABSOLUTE MAXIMUM RATINGS Parameter Value Unit (Input) Yin -1.0to + 7.0 V (Output) Vout -1.0to +7.0 V Supply Voltage Relative to VSS VCC -1.0to + 7.0 V Short Circuit Output Current lout 50 rnA Voltage on Any Pin Relative to Vss Symbol I I Power Dissipation PT S W Operating Temperature Topr Oto + 70 Storage Temperature T stg - 55 to + 125 'c 'c • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70'C) Parameter Symbol VSS Supply Voltage Input High Voltage Input Low Voltage Note: Min Typ Max Unit 0 0 0 V Note Vcc 4.5 5.0 5.5 V I VIH 2.4 5.5 V I VrL -1.0 - O.S V I I. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss = OV) HB56G 19A/B/GB Parameter Operating Current Standby Current Symbol ICCI -6A -7A Min -lOA -SA Min Max Max - 310 - 2S0 - 6 - - 3 Min Unit Test Conditions Max Min Max - 250 - 220 rnA tRC 6 - 6 - 6 rnA TTL Interface RAS, CAS = VrH, Dout = High-Z - 3 - 3 - 3 rnA CMOS Interface RAS, CAS ::: Vcc - 0.2V, Dout = High-Z ICC2 = Min RASOnly Refresh Current ICC3 - 310 - 280 - 240 - 210 rnA tRC Standby Current ICC5 - 15 - 15 - 15 - 15 rnA RAS CAS Dout CAS Before RAS Refresh Current ICC6 - 300 - 270 - 240 - 210 rnA tRC = Min Fast Page Mode Current ICC7 - 300 - 270 - 230 - 210 rnA tpc = Min Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 !LA OV :$ Yin :$ 7V Output Leakage Current ILO -10 10 -10 10 -10 10 -10 10 !LA OV :$ Vout :$ 7V, Dout = Disable Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V lout = -5mA Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 V lout = 4.2 rnA Notes: = = = = Min VIH, VrL, Enable Note 1,2 2 I 1,3 I. ICC depends on output load condition when the device is selected, Icc max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VrL. 3. Address can be changed :$ I time while CAS = VIH. @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 763 HB56G19 Series • Capacitance (TA = 25'C, Vee = 5V ±10%) Parameter Notes: Typ Max Unit Note Input Capacitance (Address) Symbol Cn - 30 pF I Input Capacitance (Clock) CI2 - 36 pF I Input/Output Capacitance (DQo_ 7) CliO - 17 pF 1,2 Input Capacitance (PD) CI3 - 10 pF I Output Capacitance (PQ) CO - 12 pF 1,2 I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIR to disable D out . • AC Electrical Characteristics (TA = 0 to + 70'C, Vee = 5V ± 10%, VSS = OV) 1, 12 Read, Write, and Refresh Cycles (Common Parameters) HB56GI9A/B/GB Parameter -6A Symbol -7A -SA Min Max Min Max Min - 130 - 160 -lOA Max Unit Min Max 190 - ns - ns Note Random Read or Write Cycle Time tRC 120 RAS Precharge Time tRP 50 RAS Pulse Width tRAS 60 10000 70 10000 SO 10000 100 10000 ns CAS Pulse Width tCAS 20 10000 20 10000 25 10000 25 10000 ns Row Address Setup Time tASR 0 - 0 - 0 - 0 - ns Row Address Hold Time tRAH 10 - 10 - 12 - 15 - ns Column Address Setup Time tASC 0 - 0 - 0 - 0 - ns Column Address Hold Time tCAH 15 - 15 - 20 - 20 - ns RAS to CAS Delay Time tRCD 20 40 20 50 22 55 25 75 ns S RAS to Column Address Delay Time tRAD 15 30 15 35 17 40 20 55 ns 9 - 50 - 70 - SO RAS Hold Time tRSH 20 - 20 - 25 - ns tCSH 60 - 70 - 25 CAS Hold Time SO - 100 - ns CAStoRAS Precharge Time tCRP 10 - 10 - 10 - 10 - ns Transition Time (Rise and Fall) tT 3 50 3 50 3 50 3 50 ns 7 Refresh Period tREF - 16 16 - 16 16 ms 15 - - ~HITACHI 764 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HB56G19 Series Read Cycle HB56G19NB/GB -6A Symbol Parameter Min -7A Max Min -lOA -SA Max Min Max Min Unit Note Max Access Time fromRAS tRAC - 60 - 70 - 80 - 100 ns 2,3 Access Time from CAS tCAC - 20 - 20 - 25 - 25 ns 3,4 Access Time from Address tAA - 30 - 35 - 40 - 45 ns 3,5 Read Command Setup Time tRCS 0 - 0 - 0 - 0 - ns Read Command Hold Time to CAS tRCH 0 - 0 - 0 - 0 - ns Read Command Hold Time toRAS tRRH 10 - 10 - 10 - 10 - ns Column Address to RAS Lead Time tRAL 30 - 35 - 40 - 45 - ns Output Buffer Tum-off Time tOFF 0 20 0 20 0 20 0 25 ns 6 Write Cycle HB56G19AIB/GB Parameter -6A Symbol -7A -SA Min Max Min Max Min -lOA Max Min Unit Note 10 Max Write Command Setup Time twcs 0 - 0 - 0 - 0 - ns Write Command Hold Time tWCH 15 - 15 - 20 - 20 - ns Write Command Pulse Width twp 10 - 10 - 15 - 20 - ns Data-in Setup Time tDS 0 - 0 - 0 - 0 - ns 11 Data-in Hold Time tDH 15 - 15 - 20 - 20 - ns 11 ~HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 765 HB56G19 Series Refresh Cycle HB56G 19AJB/GB Parameter -6A Symbol -8A -7A -lOA Unit Min Max Min Max Min Max Min Max CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 15 - 15 - 20 - 20 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - ns Note Fast Page Mode Cycle HB56GI9AIB/GB Parameter -6A Symbol -7A -8A -lOA Unit Min Max Min Max Miu Max Min Max Fast Page Mode Cycle Time tpc 45 - 50 - 55 - 55 - ns Fast Page Mode CAS Precharge Time tcp 10 - 10 - 10 - 10 - ns Fast Page Mode RAS Pulse Width tRASC 60 100000 Access Time from CAS Precharge tACP - 40 RAS Hold Time from CAS Precharge tRHCP 40 - Notes: 70 100000 80 100000 - 45 - 50 45 - 50 - 100000 ns 13 - 50 ns 14 50 - ns 100 I. AC measurements assume tT = 5 ns. 2. Assumes that tRCD S tRCD (max) and tRAD S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD -0 o'o:tlnan ~ .... 0!d I • oorno 3234 i!", ~~ <1>3175 Vfoi25 >1 lnnnnrmr~:nnnnnnnnnnnnnn·· 203 0080 762 0.300 • 528 max 0208 • 8~.14 254 11178 0.100" 0070 y ,• 1~ ~ 0050 7366 2900 /'0 9~~_l!l!!!. Detail A 0010 Note: Following the specification of the contact pad. Part No. HBS6A49B4-XX Solder HBS6A49GBR-XX Gold t I~I t Contact Pad f.~ 11t 0096-5 • 774 , HITACHI Hitacl)i America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HB56A49 Series Unit: .mm Inch • HB56A49A Series _ _ _ _ _ _ _ _ _ _,88.9 _ __ 3.5 DDDDD DDDDO 0096-6 • HB56A49AT Series 90.14 0096-7 • HB56A49B/GB Series ____________________ ~88.9 ____________________ ~ t·'5.2~max -3.5 w'I"'"' rn 1.27.1/ 0.05" r· 0096-8 Note: Following the specification of the contact pad. Part No. Contact Pad HB56A49B-XX Solder HB56A49GB-XX Gold 0070 Detail A 0096-9 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 775 HB56A49 Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VT -1.0to +7.0 V Supply Voltage Relative to Vss Vcc -1.0to +7.0 V Short Circuit Output Current lout 50 rnA Voltage on Any Pin Relative to vss Power Dissipation PT 9 W Operating Temperature Topr Oto +70 ·C Storage Temperature Tstg - 55 to + 125 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter Supply Voltage + 70'C) = 0 to Symbol Min Typ Max Unit Vss 0 0 0 V Note Vcc 4.5 5.0 5.5 V 1 Input High Voltage VIH 2.4 5.5 V 1 Input Low Voltage VIL -0.5 - 0.8 V 1 Note: 1. All voltage referenced to VSS' • DC Electrical Characteristics (TA = 0 to + 70·C, Vee = 5V ± 10%, Vss = OV) HB56A49B/GB/BR/GBR/A/AR/AT/ATR Parameter Operating Current Standby Current Symbol ICC! -6A -7A -8/-8A -10/-IOA Unit Test Condition Min Max Min Max Min Max Min Max - 990 - 900 - 810 - 720 mA tRC = Min - 18 - 18 - 18 - 18 mA TTL Interface RAS, CAS = VIH D out = High-Z - 9 - 9 - 9 - 9 rnA CMOS Interface RAS, CAS ~ Vcc - 0.2V D out = High-Z ICC2 Note 1,2 RASOnly Refresh Current ICC3 - 990 - 900 - 810 - 720 rnA tRC = Min 2 Standby Current ICC5 - 45 - 45 - 45 - 45 mA RAS = VIH CAS = VIL D out = Enable 1 CAS Before RAS Refresh Current ICC6 - 990 - 900 - 810 - 720 rnA tRC = Min Page Mode Current ICC7 - 990 - 900 - 810 - 720 rnA tpc = Min Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 p.A OV:s VIN:S 7V Output Leakage Current ILO -10 10 -10 10 -10 10 -10 10 p.A OV:S Vout:S 7V D out = Disable Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V lout = -5mA Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 V lout = 4.2 rnA Notes: 1. ICC depends on output load condition when the device is selected, Icc max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIL' 3. Address can be changed once or less while CAS = VIH. ~HITACHI 776 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 1,3 HB56A49 Series • Capacitance (TA = 25'C, Vee = 5V ±10%) HB56A49 Parameter Symbol BR/GBR/AR/ATR Typ Input Capacitance (Address) CII - 60 Input Capacitance (Clock) CI2 - 75 Input Capacitance (PCAS) CD - 12 Input/Output Capacitance (DQO_7) CliO - 17 Input Capacitance (PD) CI4 - 10 Output Capacitance (PQ) Notes: CO AlATIB/GB Max Typ - 12 Unit Note Max 70 pF I 88 pF I 20 pF I 30 pF 1,2 20 pF I 20 pF 1,2 I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIR to disable D out . • AC Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss = OV)1, 12, 15 Read, Write and Refresh Cycle (Common Parameters) HB56A49B/GB/BR/GBR/AiAR/AT/ATR Parameter Symbol -6A Min Ramdon Read or Write Cycle Time tRC -7A Max - 110 Min -8A Max 130 Min - 150 - 60 -lOA Max Min - 180 - -8 Max Min - 150 - 60 -10 Max Min - 180 Unit - ns - ns RAS Precharge Time tRP 40 RAS Pulse Width tRAS 60 10000 70 10000 80 10000 100 10000 80 10000 100 10000 CAS Pulse Width tCAS 15 10000 20 10000 20 10000 25 10000 20 10000 25 10000 Row Address Setup Time tASR 0 Row Address Hold Time tRAH 10 - - 50 70 15 - - 0 - 0 - 0 10 - 10 - 0 - 0 0 - 10 - - 0 0 70 ns ns ns 15 - - 0 - ns 0 Note Max ns Column Address Setup Time tASC 0 - Column Address Hold Time tCAH 15 - 15 - 15 - 20 - 15 - 20 - ns RAS to CAS Delay Time tRCD 20 50 20 50 20 60 25 75 20 60 25 75 ns 8 RAS to Column Address Delay Time tRAD 15 35 15 35 15 40 20 55 15 40 20 55 ns 9 20 - 25 - ns 80 100 - ns 10 - ns RAS Hold Time tRSH 15 - 20 - 20 - 25 CAS Hold Time tCSH 60 - 70 - 80 - 100 - 10 - 3 50 3 50 ns 7 16 - 16 ms 17 CAS to RAS Precharge Time tcRP 10 - 10 - 10 - 10 - Transition Time (Rlse and Fall) tT 3 50 3 50 3 50 3 50 Refresh Period tREF - 16 16 - 16 - - 16 - Read Cycle HB56A49B/GBIBR/GBR/AIAR/AT / ATR Parameter Symbol -6A Min Access Time from RAS Access Time from CAS Access Time from Address Read Command Setup Time -7A Max Min 60 - 70 tCAC - 15 - 20 tAA - 30 - tRCS 0 - 0 tRAC -lOA -8A Max Min Max Min Max -8 Min -10 Max Min Unit Note 2,3,16 Max 80 - 100 - 80 - 100 ns 20 - 25 - 25 ns 3,4,14 40 - 45 - 40 - 25 35 - 45 ns 3, 5, 14, 16 - 0 - 0 - 0 - 0 - ns @HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 777 HB56A49 Series Read Cycle (continued) HB56A49B/GBIBRlGBRlA/ARlAT/ATR Parameter Symbol -6A -7A -8A -lOA Min Max Min Max Min Max Min -8 Max Unit -10 Min Max Min Max Note Read Command Hold Time to CAS tRCH 0 - 0 - 0 - 0 - 0 - 0 - ns Read Command Hold Time to RAS tRRH 0 - 0 - 0 - 0 - 10 - 10 - ns Column Address to RAS Lead Time tRAL 30 - 35 - 40 - 45 - 40 - 45 - ns Output Buffer Turn-off Time tOFF 0 15 0 20 0 20 0 25 0 20 0 25 ns 6 Unit Note Max Min 10 Write Cycle HB56A49B/GBIBRlGBRlAIAR/AT/ATR Parameter Symbol -7A -6A Min Max -8A -lOA Min Max Min Max Min -8 Max Min -10 Max Write Command Setup Time twcs 0 - 0 - 0 - 0 - 0 - 0 - ns Write Command Hold Time twcH 15 - 15 - 15 - 20 - 15 - 20 - ns Write Command Pulse Width twp 10 - 10 - 10 - 20 - 15 - 20 - ns Write Command to RAS Lead Time tRwL 15 - 20 - 20 - 25 - 25 - 25 - ns Write Command to CAS Lead Time tCWL 15 - 20 - 20 - 25 - 25 - 25 - ns - 0 - 0 - 0 - ns 11 20 - 0 15 - 0 15 15 - 20 - ns 11 Data-in Setup Time tos 0 Data-in Hold Time tOH IS Refresh Cycle HB56A49B/GBIBRlGBRlAIARlAT/ATR Parameter -6A Symbol Min -8A -7A Max Min Max Min -lOA Max Min Max -8 Min Unit -10 Max Min Max CAS Setup Time (CAS Before RAS Refresh Cycle) tcsR 10 - 10 - 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 10 - 10 - 10 - 10 - 20 - 20 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - 10 - 10 - ns ~HITACHI 778 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 Note HB56A49 Series Fast Page Mode Cycle HB56A49B/GB/BR/GBRIN AR/ATI ATR Parameter -6A Symbol Min -7A Max Min -SA Max -lOA -10 -S Min Max Min Max Min Max Min Unit Note Max Fast Page Mode Cycle Time tpc 40 - 45 - 50 - 55 - 55 - 55 - ns Fast Page Mode CAS Precharge Time tcp 10 - 10 - 10 - 10 - 10 - 10 - ns Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 - 100000 - 100000 - 100000 - 100000 ns 13 Access Time from CAS Precharge tACP - 35 - 40 - 45 - 50 - 50 - 50 ns 14,16 35 - 40 - 45 - 50 - 50 - 50 - ns RAS Hold Time from CAS Precharge tRHCP Test Mode Cycle HB56A49B/GB/BR/GBRIN ARIATIATR Parameter Symbol -6A Min Test Mode WE Setup Time tws 0 Test Mode WE Hold Time tWH 10 Notes: -7A Max - -lOA -SA Min Max Min Max Min 0 - 0 10 - 10 10 0 -10 -S Max - Min 0 20 Max - Min 0 20 Unit Note Max - ns ns I. AC measurements assume tT = 5 ns. 2. Assumes that tRCO :$ tRCO (max) and tRAo :$ tRAO (max). If tRCO or tRAO is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCO :!: tRCO (max), tRAO :$ tRAO (max). 5. Assumes that tRCO :$ tRCO (max), tRAO :!: tRAO (max). 6. tOFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIR (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. S. Operation with the tRCO (max) limit insures that tRAC (max) can be met, tRCO (max) is specified as a reference point only, if tRCO is greater than the specified tRco (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAO (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. Early write cycle only (twcs :!: twcs (min)). II. These parameters are referenced to CAS leading edge in an early write cycle. 12. An initial pause of 100 I's is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). 13. tRAsc is determined by RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tCAP' 15. Test mode operation specified in this data sheet is 8-bit test function controlled by control address bits ... RAIO, CAIO and CAO. This test mode operation can be performed by WE and CAS before RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of eight test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. Data output pin is Dout and data input pin is Din' In order to end this test mode operation, perform a RAS only refresh cycle or a CAS before RAS refresh cycle. 16. In a test mode read cycle, the value of tRAC, tAA and tACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 17. tREF is determined by 1,024 refresh cycles. @HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 779 HB56A49 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORM • Read Cycle tRC iRP Address tCAC tOFF Valid Output Dout tRAC High-Z Din ~ : Don't care 0096-10 ~HITACHI 780 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HB56A49 Series • Early Write Cycle tRC tT LRP Address Dout High-Z Din ~ : Don't care 0096-11 • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 781 HB56A49 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle tRC Address High-Z Dout WE : Don't care 2 ~: Don't care 0096-12 • CAS Before RAS Refresh Cycle tRC tRP tCSR tCHR 1 Address, Din: Don't care 2 Dout: High-Z 3 ~: Don't care 4 WE =VIH 0098-13 • 782 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56A49 Series • Hidden Refresh Cycle Dout Dout 1 ~ : Don't care 0096-14 _HITACHI Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 783 HB56A49 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read Cycle tRASC tT tASR Address Dout Valid Output N tRAC High-Z Din ~ : Don't care 0096-15 • 784 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56A49 Series • Fast Page Mode Early Write Cycle tRASC Address Dout High-Z Din ~ : Don't care 0096-16 • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 785 HB56A49 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TEST MODE CYCLE 1 CBR or RAS only refresh 2 ~ : Don't care 3 Address, Din: Don't care 0096-17 • Test Mode Set Cycle Address OPEN Dout ~ : Don't care 0096-19 ~HITACHI 786 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56A49 Series • Test Mode Reset Cycle CAS Before RAS Refresh Cycle Address OPEN Dout ~ : Don't care 0096-19 RAS Only Refresh Cycle Address OPEN Dout 1 ~ : Don't care 2 Refresh address: AO - A9 (AXO - AX9) 0096-20 @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589-8300 787 HB56D25632 Series 262,144·Word x 32·Blt High Density Dynamic RAM Module • DESCRIPTION • PIN OUT The HB56D25632B is a 256k x 32 dynamic RAM module, mounted 8 pieces of 1 Mbit DRAM (HM514256JP) sealed in SOJ package. An outline of the HB56D25632B is 72-pin single in-line package. Therefore, the HB56D25632B makes high density mounting possible without surface mount technology. The HB56D25632B provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ. • FEATURES • 72-pin Single In-line Package Lead Pitch ................................ 1.27mm • Single 5V (±5%) Supply • High Speed Access Time ............ 60 ns/70 ns/80 ns/100 nsl 120 ns (max) • Low Power Dissipation Active Mode ............... . 3.78W/3.36W/2.772WI 2.31W/1.974W (max) Standby Mode ........................ 84 mW (max) • Fast Page Mode Capability • 512 Refresh Cycle/8 ms • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible • ORDERING INFORMATION Part No. Access Time HB56D25632B-6A 60ns HB56D25632B-7A 70ns HB56D25632B-8A 80ns Package 72-pinSIP Socket Type HB56D25632B Series 0 0 ~ DD- - _.- - -.- - _.- - -'-00 " 00- -_.- -- - --.- - -'-00 Ji. 3St. 37t. 121m 0095-1 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name I Vss 19 NC 37 NC 55 DQll 2 DQO 20 DQ4 38 NC 56 0027 3 0016 21 DQ20 39 Vss 57 4 DQI 22 DQ5 40 CASO 58 0012 DQ28 5 DQI7 23 0021 41 CAS2 59 Vee 6 DQ2 24 DQ6 42 CAS3 60 DQ29 7 0018 DQ3 25 DQ22 43 CAS I 61 8 26 DQ7 44 RASO 62 0013 DQ30 9 DQI9 27 0023 45 NC 63 DQI4 10 Vee 28 A7 46 NC 64 DQ31 11 NC 29 NC 47 WE 65 12 AO 30 Vee 48 NC 66 0015 NC Vss 13 Al 31 A8 49 DQ8 67 14 A2 32 NC 50 DQ24 68 NC A3 33 NC 51 DQ9 69 T.B.D. T.B.D. H856D25632B- lOA lOOns 15 HB56D25632B-12A 120ns 16 A4 34 RAS2 52 DQ25 70 17 A5 35 NC 53 DQIO 71 NC 18 A6 36 NC 54 0026 72 Vss • PIN DESCRIPTION Pin Name Ao-Ag Function Address Input Ao-Ag Refresh Address Input DQo-DQ31 Data-in/Data-out CASO- CAS3 Column Address Strobe RASO-RAS2 Row Address Strobe WE ReadIWrite Enable Vee VSS Ground NC No Connection Power ( + 5V) _HITACHI 788 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56D25632 Series • BLOCK DIAGRAM tm '1IOlm m DQO DQl DQ2 1102 1/03 001 .£" 00. DO 'et 1I01Eif m 1102 1",3 02 OOS DQI DQ7 ~ lr mt m DQB IlOlm 1m 04 1101 009 0010 0011 ~ 0012 0013 001. OOlS ~ DQII OQ17 ~ 1I01Gr W 1102 06 1103 ~ 0095-2 m 1I01G.f IIOZ 01 1103 0018 DQ19 -#i" 0020 lei m 1/01G.f 1102 1/01 01 OOZl DQ22 0023 .;;!ef ar 1101G.f 1102 OS 1103 ~ DOZ8 DOlO OO2t 'et 1101 m Riil' 1102 07 1103 -#;~ D031 0095-3 AO-AI ••---..~ 00-07 WI" • • 00-D7 : HMS14256 ~ 00-07 Vee • :L Vu • T ~DO-D7 CO - C7 ~ 00-07' 0095-4 • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 789 HB56D25632 Series u' mm • PHYSICAL OUTLINE nit: inch R 1.57 R 0.012 ... '5 I 1. 75 Note: The plating of the contact finger is gold. OetailA 0095-5 • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit (Input) Yin -1.0to +7.0 V (Output) Vout -1.0to +7.0 V Supply Voltage Relative to Vss Vee -1.0to +7.0 V Short Circuit Output Current lout 50 rnA Voltage on Any Pin Relative to Vss I I Power Dissipation PT Operating Temperature Topr Tstg Storage Temperature • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to Parameter Supply Voltage Input High Voltage Symbol W ·C ·C - 55 to + 125 + 70'C) Min Typ Max Unit VSS 0 0 0 V Vee 4.75 5.0 5.25 V I VIH 2.4 - 5.5 V 1 -1.0 - 0.8 V 1 Input Low Voltage VIL Note 1. All voltage referenced to Vss. • 790 8 Oto + 70 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 Note HB56D25632 Series • DC Electrical Characteristics (TA ·6A Symbol Parameter Operating Current = 5V +70"C, Vee ·7A = OV) ±5%, Vss ·8A ·12A ·IOA Test Condition Unit Min Max Min Max Min Max Min Max Min Max - 720 - 640 - 528 - 440 - 376 - 16 - 16 - 16 - 16 - 16 - 8 - 8 - 8 - 8 - 8 mA IcC! Standby Current = 0 to rnA tRC = Min TTL Interface rnA RAS, CAS = VIH Dont = High·Z ICC2 ICC3 - 720 - 640 - 528 - 440 - 376 mA Standby Current ICCS - 40 - 40 - 40 - 40 - 40 rnA CAS Before RAS Refresh Current ICC6 - 720 - 640 - 528 - 440 - 376 rnA tRC = Min Page Mode Current ICC7 - 720 - 640 - 440 - 440 - 376 rnA tpc = Min = Min RAS = VIH CAS = VIL Dont = Enable 2 tRC I 1,3 Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 -10 10 p.A OV::SVin ::S 7V Output Leakage Current IW -10 10 -10 10 -10 10 -10 10 -10 10 p.A OV::S Vont ::s 7V Dont = Disable Output High Voltage VOH 2.4 VCC 2.4 Vee 2.4 Vee 2.4 VCC 2.4 Vee V High lout =- Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 rnA 5 rnA 1. IcC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIL. 3. Address can be changed once or less while CAS = VIH' • Capacitance (TA = 25·C, Vee = 5V ±5%) Symbol Typ Max Unit Note Input Capacitance (Address) Cn - 68 pF I Input Capacitance (WE) CI2 - 76 pF I Input Capacitance (RAS) CI3 - 43 pF I Input Capacitance (CAS) CI4 29 pF I Output Capacitance (DQO-DQ31) CvO - 17 pF 1,2 Parameter Notes: 1,2 CMOS Interface RAS, CAS O!: Vee - 0.2V Dont = High.Z RASOnIy Refresh Current Notes: Note 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out' • AC Characteristics (TA = 0 to +70·C, Vee = 5V ±5%, Vss Read, Write and Refresh Cycle (Common Parameters) Parameter ·6A Symbol Min = 0V)1, 12 ·7A Max - Min 140 - ·12A ·IOA ·8A Max Min Max Min Max Min 160 - 190 80 - 220 70 Unit - ns Random Read or Write Cycle Time tRC 125 RAS Precharge Time tRP 55 RAS Pu1se Width tRAS 60 10000 70 10000 80 10000 100 10000 120 10000 ns CAS Pulse Width teAs 20 10000 20 10000 25 10000 25 10000 30 10000 ns Row Address Setup Time tASR 0 0 0 - ns 10 - 0 tRAH - 0 Row Address Hold Time - 15 - ns 60 10 • 12 - 15 90 Note Max ns HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589·8300 791 HB56D25632 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - Read, Write and Refresh Cycle (Common Parameters) (continued) Parameter -6A Symbol -7A Max Min -SA Min Max -lOA Min Max Min -12A Max Min Unit Note Max Column Address Setup Time tASC 0 - 0 ns 15 - 20 20 - - 15 - 0 leAH - 0 Column Address Hold Time 25 - ns RAS to CAS Delay Time tRCO 20 40 20 50 22 55 25 75 25 90 ns 8 RAS to Column Address Delay Time tRAO 15 30 15 35 17 40 20 55 20 65 ns 9 25 - 25 - 30 100 120 10 - 10 - - ns 80 10 - ns 3 50 3 50 3 50 ns 7 8 - 8 ns 15 Unit Note RAS Hold Time tRSH 20 - 20 CAS Hold Time tcSH 60 70 CAS to RAS Precharge Time tcRP 10 - 10 - Transition Time (Rise and Fall) tT 3 50 3 50 Refresh Period tREF - S - 8 - Min 0 8 - Max Min Max Min - 100 25 25 - ns Read Cycle Parameter -6A Symbol Min -7A Min Max 70 - 60 20 - tAA - 30 - 35 - tRCS 0 0 - 0 0 - 0 - 0 10 - 10 - tRAL 30 - 35 toFF - 20 - Access Time from RAS tRAC Access Time from CAS tCAC Access Time from Address Read Command Setup Time Read Command Hold Time to CAS tRCH Read Command Hold Time to RAS tRRH Column Address to RAS Lead Time Output Buffer Tum-off Time -lOA -8A Max 20 SO -12A Max 120 ns 2,3 30 ns 3,4 3,5 40 - 45 - 55 ns 0 10 - 40 - 45 - 55 - ns 10 - 0 10 - 20 - 20 - 25 - 30 ns 6 Unit Note ns 10 0 0 ns ns ns Write Cycle Parameter -6A Symbol -7A Min Max -SA Min Max Min -lOA Max -12A Min Max Min Write Command Setup Time twcs 0 - 0 - 0 - 0 15 - 15 20 10 - 10 - 15 tos 0 - 0 0 Data-in Hold Time tOH 15 - 15 - - 25 Data-in Setup Time - 20 Write Command Pulse Width tWCH twp - 0 Write Command Hold Time 20 15 0 20 Max - 20 0 25 ns ns ns 11 ns 11 Unit Note Refresh Cycle Parameter -6A Symbol -7A Min Max Min -SA Max Min -lOA Max -12A Min Max Min Max CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tcHR IS - 15 - 20 - 20 - 25 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - 10 - ns ~HITACHI 792 Hitachi America, Ltd_ • Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819' (415) 589-8300 HB56D25632 Series Fast Page Mode Cycle Parameter -6A Symbol Min -SA -7A Max -lOA -12A Unit Min Max Min Max Min Max Min Max Note Fast Page Mode Cycle Time tpc 45 - 50 - 55 - 55 - 65 - ns Fast Page Mode CAS Precharge Time tcp 10 - 10 - 10 - 15 - 20 - ns Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 - 100000 - 100000 - 100000 ns 12 Access Time from CAS Precharge tACP - 40 - 45 - 50 - 50 - 60 ns 13 RAS Hold Time from CAS Precharge tRHCP 40 - 45 - 50 - 50 - 60 - ns Notes: 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :s tRCD (max) and tRAD :s tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TIL loads and 100 pF. 4. Assumes that IRcD :!: tRCD (max), tRAD :s tRAD (max). 5. Assumes that tRCD :s tRCD (max), tRAD :!: tRAD (max). 6. toFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. S. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. Early write cycle only (twcs :!: twcs (min». II. These parameters are referenced to CAS leading edge in an early write cycle. 12. An iuitial pause of 100 ,,"S is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). 13. tRASC is determined by RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tACP' IS. tREF is determined by 512 refresh cycles. eHITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 793 HB56D25632 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORM • Read Cycle Address Valid Dout Output High·Z Din ~ : Don't car. 0095-6 • 794 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 HB56D25632 Series • Early Write Cycle tRC Address Din Dout High·Z ~ : Don't care 0095-7 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 795 HB56D25632 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle tRC Address High·Z Dout WE : Don't car. 2 ~: Don't car. 0095-8 • CAS Before RAS Refresh Cycle tRC tRP tCHR 1 Address, Din, wt : Don't car. 2 Dout: High·Z 3 ~: Don't care 0095-9 ~HITACHI 796 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HB56D25632 Series • Fast Page Mode Read Cycle Address Dout Din High·Z ~ : Don't care 0095-10 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 797 HB56D25632 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Early Write Cycle Address Din High·Z Dout ~ : Don't Clrt 0095-11 ~HITACHI 798 Hitachi America, Ltd. • Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HB56D51232 Series 524,288-Word x 32-Bit High Density Dynamic RAM Module • DESCRIPTION • PIN OUT The HB56D51232SB is a 512k x 32 dynamic RAM module, mounted 16 pieces of 1 Mbit DRAM (HM514256JP) sealed in SOJ package. An outline of the HB56D51232SB is 72-pin single in-line package. Therefore, the HB56D51232SB makes high density mounting possible without surface mount technology. The HB56D51232SB provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ but only on the one side of its module board. ,--------------------------------------, o o D- - - - - _.- - - - - -'-D 1 pin D- _._.- - - - - -,- - --D 36pin 37 pin 72 pin 0097-1 • FEATURES • 72-pin Single In-line Package Lead Pitch ................................ 1.27mm • Single 5V (±5%) Supply • High Speed Access Time ............ 60 nsf70 nsf80 nsf 100 nsf 120 ns (max) • Low Power Dissipation Active Mode ........ . 3.95Wf3.57Wf2.982Wf2.52Wf 2.184W (max) Standby Mode ...................... 168 mW (max) • Fast Page Capability • 512 Refresh Cyclesf8 ms • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible Part No. Access Time 60ns HB56D51232SB-7A 70ns HB56D51232SB-8A 80ns HB56D51232SB-10A HB56D51232SB-12A lOOns 120ns Package 72-pinSIP Socket Type Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VSS 19 NC 37 NC 55 DQl1 2 DQo 20 DQ4 38 NC 56 DQ27 3 DQI6 21 DQ20 39 Vss 57 DQ12 4 DQI 22 DQs 40 CASO 58 DQ2S 5 DQ17 23 DQ21 41 CAS2 59 Vee 6 DQ2 24 DQ6 42 CAS3 60 DQ29 7 DQIS 25 DQ22 43 CAS1 61 DQ13 8 DQ3 26 DQ7 44 RASO 62 DQ30 9 DQI9 27 DQ23 45 RAS1 63 DQI4 10 Vee NC 28 A7 46 NC 64 DQ31 29 NC 47 WE 65 30 Vee 48 NC 66 DQIS NC 13 Ao Al 31 DQs 67 NC A2 32 As NC 49 14 50 DQ24 68 15 A3 33 RAS3 51 DQ9 69 Vss PD1 16 A4 34 RAS2 52 DQ2S 70 PD2 17 As 35 NC 53 DQIO 71 NC 18 A6 36 NC 54 DQ26 72 VSS 11 • ORDERING INFORMATION HB56D51232SB-6A Pin No. 12 • PIN DESCRIPTION Pin Name Function Ao-As Address Input Ao-As Refresh Address Input DQo-DQ3! Data-inlData-out CASO-CAS3 Column Address Strobe RASO-RAS3 Row Address Strobe WE ReadIWrite Enable Vee Power Supply ( + 5V) Vss NC Ground No Connection • PRESENCE DETECT PINOUT HB56D51232SB Pin No. Pin Name 60ns 70ns 80ns lOOns 120ns 69 PD1 NC NC VSS NC 70 PD2 NC VSS NC VSS VSS NC ~HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 799 HB56D51232 Series • BLOCK DIAGRAM mo • ii"ASii 1102 1103 1104 1/03 00 :£"" £OE 01 1104 OE ~ % 004 DOS DOG 007 RAS 1101 CAS 1102 RAS 1/01 CAS 000 001 002 003 1101 CAS RAS 1102 1103 02 1&..4 1101 CAS RAS 1102 1103 03 !&9 ~OE ~OE % 1101 CAS RAS 1102 1103 OS 1101 CAS RAS 1102 04 1103 008 009 DOlO DOll !&9 !&9 ~OE OE % / 1101 CAS RAS 1102 07 1103 1104 0012 0013 0014 0015 ~OE RAS 1101 CAS 1/02 1103 1104 06 £OE % 0097-2 ~ CAS2 11Il! CAS RAS 1102 08 1103 1104 0016 0017 0018 0019 ~OE 110100 RAS 1102 1103 09 1104 ;;-OE % 0020 0021 0022 0023 1101 CAS RAS 1102 1103 010 1101 CAS RAS 1102 1103 011 !&9 !&9 £OE ~OE % CAS3 1101 CAS RAS 1102 1103 012 1104 0024 D02S 0026 0027 1101 CAS RAS 1102 1103 013 1104 ~OE $"OE % 1101 CAS RAS 1102 014 1103 1104 1101 CAS RAS 1102 1103 DIS 1104 0028 0029 0030 0031 di,"0E *OE % 0097-3 AO-A8 ••---~" 00-015 WE • • DO-DIS: HM514256 " 00-07 --:c-r----. 00-015 Vee •• Vss • r CO - C7 .00-015 0097-4 ~HITACHI 800 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56D51232 Series • Unit: mm/inch PACKAGE OUTLINE 107.95 . '"- '" "'''' . '"'" In • ",- ~.19~~!.:~~2 1. 75 0.047 (! ~~ typ\ ' 0.054 0.05 '/ Delail A :t 15'Mjlbn. 0100 ~~ 0010 11m,,. 0042 0097-5 Note: Contact finish 2.2 fLm (86.6 fLinch) Solder over 2.0 fLm (78.7 fLinch) Ni. • ABSOLUTE MAXIMUM RATINGS Value Unit (Input) V -l.Oto +7.0 V (Output) Vifut -l.Oto +7.0 V Supply Voltage Relative to Vss Vee -l.Oto + 7.0 V Short Circuit Output Current lout 50 rnA Parameter Voltage on Auy Pin Relative to Vss Symbol I I Power Dissipation PT 16 W Operating Temperature Topr Oto + 70 ·C Storage Temperature Tstg - 55 to + 125 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to Parameter Supply Voltage Note: + 70·C) Min Typ Max Unit VSS 0 0 0 V Symbol Note Vee 4.75 5.0 5.25 V 1 Input High Voltage VIR 2.4 5.5 V 1 Input Low Voltage VIL -l.0 - 0.8 V 1 l. All voltage referenced to Vss. ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 801 HB56D51232 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • DC Electrical Characteristics (TA Parameter Symbol Operating Current IcC! Standby Current = 0 to -6A +70'C, Vee -7A Min Max - = 5V ±5%, Vss = OV) -lOA -8A -12A Unit Test Condition Note Min Max Min Max Min Max Min Max 760 - 680 - 568 - 480 - 416 - 32 - 32 - 32 - 32 - 32 - 16 - 16 - 16 - 16 - 16 CMOS Interface rnA RAS, CAS ~ VCC - 0.2V Dout = High-Z ICC2 = min TIL Interface rnA RAS, CAS = VIH Dout = High-Z 1,2 rnA tRC RASOnly Refresh Current ICC3 - 760 - 680 - 568 - 480 - 416 rnA tRC Standby Current Iccs - 80 - 80 - 80 - 80 - 80 rnA CAS Before RAS Refresh Current ICC6 - 680 - 568 - 480 - 416 rnA tRc ICC7 - 760 Page Mode Current 680 - 480 - 480 - 416 rnA tpc - min Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 -10 10 /LA OV S VIN S 7V Output Leakage Current Iw -10 10 -10 10 -10 10 -10 10 -10 10 /LA OV S VOUT S 7V Dout = Disable 2.4 Vcc 0.4 2.4 Vcc 0.4 2.4 VCC 0.4 2.4 VCC 0.4 2.4 VCC 0.4 V High lout = - 5 rnA V Low lout = 4.2 rnA Output High Voltage VOH Output Low Voltage VOL Notes: 0 760 0 0 0 2 = min 1,3 1. Icc depends on output load condition when the device is selected, Icc max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. • Capacitance (TA = 25'C, Vee = 5V ±5%) Parameter Symbol Typ Max Umt Input Capacitance (Address) CII 121 pF I Input Capacitance (WE) CI2 - 137 pF I Input Capacitance (RAS) C13 - 48 pF I Input Capacitance (CAS) CI4 - 48 pF I CliO - 17 pF 1,2 Output Capacitance (DQo- DQ3!) Notes: 0 = min RAS = VIH CAS = VIL Dout = Enable Unit 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. = VIH to disable Dout. 2. CAS • AC Characteristics (TA = 0 to +70'C, Vee = 5V ±5%, Vss Read, Write and Refresh Cycle (Common Parameters) Parameter Symbol -6A Min = OV)l, 12 -8A -7A Max - -lOA -12A Unit Min Max Min Max Min Max Min Max 140 - 160 - 190 - 220 - ns 70 - 80 - 90 - ns Random Read or Write Cycle Time tRC 125 RAS Precharge Time tRP 55 RAS Pulse Width tus 60 10000 70 10000 80 10000 100 10000 120 10000 CAS Pulse Width tcAS 20 10000 20 10000 25 10000 25 10000 30 10000 - 0 - - 0 - ns 12 - 0 10 15 15 - 0 0 - ns 0 - 20 - 20 - 25 - Row Address Setup Time tASR 0 Row Address Hold Time tRAH 10 Column Address Setup Time tASC 0 Column Address Hold Time leAH 15 60 - 0 15 $ 802 - 0 HITACHI HHachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 us us us us Note HB56D51232 Series Read, Write and Refresh Cycle (Common Parameters) (continued) Parameter Symbol -6A -7A -SA Min Max Min Max Min -lOA Max -12A Min Max Min Max Unit Note RAS to CAS Delay Time tRCD 20 40 20 50 22 55 25 75 25 90 ns S RAS to Column Address Delay Time tRAD 15 30 15 35 17 40 20 55 20 65 ns 9 RAS Hold Time tRSH 20 - 20 25 - 25 tCSH 60 - 70 SO - 100 !cRP 10 - 10 10 - 10 10 - ns CAS to RAS Precharge Time - 30 CAS Hold Time - Transition Time (Rise and Fall) tT 3 50 3 50 3 50 3 50 3 50 ns 7 Refresh Period tREF - S - S S - S - S ns 15 Unit Note - 120 ns ns • Read Cycle Parameter Symbol -6A Min -7A Max Min -SA -lOA -12A Max Min Max Min Max Min Max - 70 - SO - 100 - 120 ns 2,3 25 30 ns 3,4 55 ns 3,5 0 0 0 - ns 10 Access Time from RAS tRAC - 60 Access Time from CAS !cAC - 20 Access Time from Address tAA - 30 Read Command Setup Time tRCS 0 10 - 20 35 40 Read Command Hold Time to CAS tRCH 0 Read Command Hold Time to RAS tRRH 10 - Column Address to RAS Lead Time tRAL 30 - 35 - 40 - Output Buffer Turn-Off Time toFF - 20 - 20 - 20 0 0 0 25 45 0 - 0 - ns 10 - 10 45 - 55 - ns - 25 - 30 ns 6 Unit Note 10 ns • Write Cycle Parameter Symbol -6A -7A Min Max - Write Command Setup Time twcs 0 Write Command Hold Time tWCH 15 Write Command Pulse Width twp 10 Data-in Setup Time tDS 0 Data-in Hold Time tDH 15 Min -SA Max - 0 15 10 0 15 Min -lOA Max - 0 20 15 0 20 -12A Min Max Min 0 0 - ns 25 20 ns 0 - 0 - ns 15 - ns II 20 - 25 - ns II Unit Note 20 Max • Refresh Cycle Parameter Symbol -6A -7A Min Max Min -lOA -SA Max Min Max Min -12A Max Min Max CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) !cHR 15 - 15 - 20 - 20 - 25 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - 10 - ns ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 803 HB56D51232 Series • Fast Page Mode Cycle Parameter Symbol -6A -SA -lOA -12A Min Max Min Max Min Max Min - 50 - 55 - 55 - ns - 15 - 65 10 10 - ns tpc 45 Fast Page Mode CAS Precharge Time tcp 10 Fast Page Mode RAS Pulse Width tRAsc Access Time from CAS Precharge tACP - RAS Hold Time from CAS Precharge tRHCP 40 10 40 - - 45 100000 45 - - 50 100000 Max Note 100000 - 100000 - 100000 ns 12 50 - 50 - 60 ns 13 - 50 - 60 - ns 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :S tRCD (max) and tRAD :S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD ~ tRCD (max) and tRAD :S tRAD (max). 5. Assumes that tRCD :S tRCD (max) and tRAD ~ tRAD (max). 6. tOFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIR (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIR and VIL' S. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. Early write cycle only (twcs ~ twcs (min». II. These parameters are referenced to CAS leading edge in an early write cycle. 12. An initial pause of 100 JJ-S is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). 13. tRASC is determined by RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tACP' 15. tREF is determined by 512 refresh cycles. ~HITACHI 804 Unit Max Fast Page Mode Cycle Time Notes: -7A Min Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56D51232 Series • TIMING WAVEFORMS • Read Cycle lRP tT Address tCAC tOFF Valid Output Dout tRAC Din High-Z ~ : Don't care 0097-6 ~HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 805 HB56D51232 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Early Write Cycle tR( Address Din Dout High-Z ~ : Don't care 0097-7 ~HITACHI 806 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56D51232 Series • RAS Only Refresh Cycle Address High-Z Dout 1 WE : Don't care 2 ~: Don't care 0097-8 • CAS Before RAS Refresh Cycle tRC lRP tCSR tCHR Address, Din, WE : Don't care 2 Dout: High-Z 3 ~: Don't care 0097-9 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 807 HB56D51232 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read Cycle tRAse Address Dout Valid Output 1 Valid Output 2 tRAe Din High-Z ~ : Don't care 0097-10 ~HITACHI 808 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HB56D51232 Series • Fast Page Mode Early Write Cycle tRASC RAS Address Din Dout High-Z ~ : Don't care 0097-11 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 809 HB56D132 Series - - - - - - - - - - - 1,048,576-Word x 32-81t High Density Dynamic RAM Module • PIN OUT • DESCRIPTION The HB56D132BRISBR is a 1M x 32 dynamic RAM module, mounted 8 pieces of 4 Mbit DRAM (HM514400JP/AJ) sealed in SOJ package. An outline of the HB56D132BRI SBR is 72-pin single in-line package. Therefore, the HB56D132BRISBR makes high density mounting possible without surface mount technology. The HB56D132BRISBR provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ. ~° I ·'·'·'·'·']0 0[ ... _................. _.]°0 0[,_,.,.,_,.,. _.... - - - . - - . f'\ . - . - - - - -'- . - J 37pin I Ipin I J 36 pin 72 pin 0155-1 • FEATURES • 72-pin Single In-line Package Lead Pitch ................................ 1.27mm • Single 5V (±5%) Supply • High Speed Access Time ....... 60 ns/70 ns/80 ns/100 ns (max) • Low Power Dissipation Active Mode ..... .4.62W/4.40W/3.96W/3.52W (max) Standby Mode ........................ 88 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycle ........................... (16 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible • ORDERING INFORMATION Part No. Access Time HB56D132BR-6A Package Contact Pad 60ns HB56Dl32BR-7A 70ns HB56D132BR-8A 80 ns HB56D132BR-IOA lOOns 72-pin SIP Socket Type Gold Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VSS 19 NC 37 NC 55 DQll 2 DQo 20 DQ4 38 NC 56 DQ27 3 DQI6 21 DQ20 39 57 DQ12 4 DQI 22 DQ5 40 VSS CASO 58 DQ2S 5 DQ17 23 DQ21 41 CAS2 59 Vee 6 DQ2 24 DQ6 42 CAS3 60 DQ29 7 DQI8 25 DQ22 43 CAS 1 61 DQ13 8 DQ3 26 DQ7 44 RASO 62 DQ30 9 DQI9 27 DQ23 45 NC 63 DQI4 10 Vee 28 A7 46 NC 64 DQ31 11 NC 29 NC 47 WE 65 12 AO 30 Vee 48 NC 66 DQI5 NC 13 Al 31 As 49 DQs 67 VSS 14 A2 32 50 DQ24 68 15 A3 33 A9 NC 51 DQ9 69 VSS NC NC HB56D132BR-8 80ns 16 A4 34 RAS2 52 DQ25 70 HB56D 132BR-1O lOOns 17 As 35 NC 53 DQIO 71 NC HB56D132SBR-6A 60ns 18 A6 36 NC 54 DQ26 72 VSS HB56D 132SBR-7A 70ns HB56DI32SBR-8A 80ns HB56D 132SBR-IOA lOOns HB56D 132SBR-8 80ns HB56D 132SBR-1O lOOns 72-pin SIP Socket Type • PIN DESCRIPTION Solder Pin Name Function Ao- A9 Address Input Ao-A9 Refresh Address Input DQo-DQ31 CASO-CAS3 Column Address Strobe RASO-RAS2 Row Address Strobe WE ReadIWrite Enable Vee Power Supply ( + 5V) VSS PD1-PD4 Ground NC No Connection Data-intData-out Presence Detect Pin ~HITACHI 810 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56D132 Series • BLOCK DIAGRAM §Q CASO OQO OQl OQ2 OQ3 110100 RAS 1102 1103 DO !12!1 ~OE r, OQ4 OQS OQ6 OQ7 1101 CAS RAS 1102 1103 02 !12!1 ~OE 00; OQ8 OQ9 OQ10 OQ11 1101 CAS RAS 1102 1103 04 !12!1 ~OE OQ12 OQB OQ14 OQ15 1101 CAS RAS 1102 1103 06 1104 £""OE ~ Em CAS2 OQ16 110100 RAS 1102 1103 01 1104 0017 OQ18 OQ19 £""OE ~ 110100 liAS 1102 1103 03 OQ20 OQ21 OQ22 OQ23 !12!1 ~OE r, em 110100 liAS 1102 1103 OS !!.Q9 OQ24 OQ25 OQ26 OQ27 #i"0E ~ OQ28 OQ29 OQ30 OQ31 110100 RAS 1102 1103 07 !!.Q9 £"OE AO-A9 ••--~~ 00-07 WE • * 00- 07 : HM514400JP/AJ ~ 00-07 Vee ••--:c-r----I~~DO - 07 =r- CO - C7 Vss ••- -.........---I~~;DO - 07 0155-2 eHITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 811 HB56D132 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • PHYSICAL OUTLINE . mm Unit: inch A 107.95 4.25 ~-------~'O'.'9~------~--~~ 3:98 0.25 min 0.01 c: 'E ON "'0 5.28 max 0_208 DDDDD R , .57 R 0.062 2.03 O. 08 6. 3 5""*_~_ _-=4:.:::4 .45::--_ _---,3>/ 1.27 typ 0.05 1E-_-.~~5.----3>I '-:-75 0:-25 ..... 0 1.75 0155-3 Detail A 60ns 70ns 80ns ~ l~B lOOns l~ l~ DetailB lli:1 2. 54M n. 0'00 Note' Following the specification of the contact pads. Part No. •• o 25max. 00'0 107max 0.042 Contact Pad HB56DI32BR-XX Gold HB56D132SBR-XX Solder 0155-4 • 812 HITACHI Hitachi America, Ltd. 0Hitachi Plaza 02000 Sierra Point Pkwy. 0Brisbane, CA 94005-1819 0(415) 589-8300 HB56D132 Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Vin Vout -1.0to +7.0 V -1.0to +7.0 V Supply Voltage Relative to Vss VCC - 1.0 to + 7.0 V Short Circnit Output Current lout 50 rnA I I Voltage on Any Pin Relative to Vss (Input) (Output) Power Dissipation PT Operating Temperature Topr Tstg Storage Temperature • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter Symbol Supply Voltage = 8 W Oto + 70 'C - 55 to + 125 'c 0 to + 70"C) Min Typ Max Unit Vss 0 0 0 V Note VCC 4.75 5.0 5.25 V I Input High Voltage VIH 2.4 5.5 V I Input Low Voltage VIL -1.0 - 0.8 V I Note: I. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to + 70'C, Vee ± 5%, Vss = 5V = OV) HB56D132BR/SBR Parameter -6A Symbol -7A -8A -lOA -10 -8 Unit Test Conditions Note Min Max Min Max Min Max Min Max Min Max Min Max Operating Current - 880 - 800 - 720 - 640 - 720 - 640 rnA tRC = Min - 16 - 16 - 16 - 16 - 16 - 16 TTL Interface rnA RAS, CAS = VIR Dout = High-Z - 8 - 8 - 8 - 8 - 8 - 8 CMOS Interface rnA RAS, CAS ~ VCC - 0.2V Dout = High-Z RASOnIy Refresh Current ICC3 - 880 - 800 - 720 - 640 - 720 - 640 rnA tRC 2 Standby Current ICC5 - 40 - 40 - 40 - 40 - 40 - 40 rnA I CAS Before RASRefresh Current ICC6 - 880 - 800 - 720 - 640 - 720 - 640 rnA tRe = Min Page Mode Current ICC7 - 880 - 800 - 720 - 640 - 720 - 640 rnA tpc = Min Input Leakage Current ILl Standby Current Icc! IcC2 1,2 = Min RAS = VIR CAS = VIL Dout = Enable 1,3 -10 10 -10 10 -10 10 -10 10 -10 10 -10 10 p.A OV S Vin S 7V Output Leakage IW Current -10 10 -10 10 -10 10 -10 10 -10 10 -10 10 p.A Output High Voltage VOR 2.4 VCC 2.4 VCC 2.4 Vcc 2.4 Vcc 2.4 VCC 2.4 VCC V High lout =- OntputLow Voltage VOL 0 0.4 0 0.4 0.4 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 rnA Notes: 0 OV S Vout S 7V Dout = Disable 5 rnA I. ICC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIL' 3. Address can be changed once or less while CAS = VIR. eH1TACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 813 HB56D132 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Capacitance (TA = 25°C, Vee = 5V ±5%) Symbol Typ Max Unit Note Input Capacitance (Address) Cn 6S pF I Input Capacitance (WE) CI2 76 pF I Input Capacitance (RAS) CI3 - 43 pF 1 Parameter Notes: Input Capacitance (CAS) CI4 - 29 pF 1 Output Capacitance (DQo- DQ31) Cvo - 17 pF 1,2 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS VIH to disable D out. = • AC Characteristics (TA = 0 to +70"C, Vee = 5V ±5%, Vss Read, Write and Refresh Cycle (Common Parameters) = OV)1, 12 HB56DI 32BR/SBR Parameter Symbol -SA -7A -6A -lOA -S -10 Unit Min Max Min Max Min Max Min Max Min Max Min Max - 130 - 150 ISO - 150 ISO - Random Read or Write CycieTime tRC 110 RAS Precharge Time tRP 40 - 50 60 - 70 - 60 - 70 - RAS Pulse Width tRAS 60 10000 70 10000 SO 10000 100 10000 SO 10000 100 10000 CAS Pulse Width teAS 15 10000 20 10000 20 10000 25 10000 25 10000 25 10000 Row Address Setup Time tASR 0 - 0 - 0 - 0 - 0 0 - Row Address Hold Time tRAH 10 10 - 10 - 15 - 12 Column Address Setup Time tASC 0 0 - 0 15 15 15 - 20 - 0 tCAH - 0 Column Address Hold Time - 15 - RAS to CAS Delay Time tRCD 20 45 20 50 20 60 25 75 22 55 RAS to Column Address Delay Time tRAD 15 30 15 35 15 40 20 55 17 RAS Hold Time tRSH 15 SO 100 CAS to RAS Precharge Time tcRP Transition Time tT (Rise and Fall) 10 - 10 - 10 10 - 25 70 - 25 60 - 20 tCSH - 20 CAS Hold Time 3 50 3 50 3 50 3 50 Refresh Period - 16 - 16 - 16 - tREF Note ns ns ns ns ns ns ns 15 - 0 20 - 25 75 ns S 40 20 55 ns 9 - 25 SO 100 - ns ns 5 - 10 - ns 3 50 3 50 ns 7 16 - 16 - 16 ms 15 Unit Note Max Min Max 80 - 100 25 - 25 ns ns 2,3 25 Min - 3,5 ns Read Cycle HB56D132BR/SBR Parameter -6A Symbol Min -SA -7A -lOA -S -10 Max Min Max Min Max Min Max 60 70 SO 40 - 100 20 35 - 45 - 40 - 45 ns ns tCAC - Access Time from Address tAA - 30 - Read Command Setup Time tRCS 0 - 0 - 0 - 0 - 0 - 0 Read Command Hold Time to CAS tRCH 0 - 0 - 0 - 0 - 0 - 0 - Read Command Hold Time to RAS tRRH 0 - 0 - 0 - 0 - 10 - 10 - ns Column Address to RAS Lead Time IRAL 30 - 35 - 40 - 55 - 40 - 45 - ns Output Buffer Turn-off Time toFF 0 15 0 20 0 20 0 25 0 20 0 25 ns Access Time from RAS Access Time from CAS tRAC 15 20 _HITACHI 814 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819' (415) 589-8300 3,4 ns 6 HB56D132 Series Write Cycle HB56D132BRISBR Parameter -6A Symbol -7A Min Max Write Command Setup Time twcs 0 Write Command Hold Time 15 Write Command Pulse Width tWCH twp Data-in Setup Time tDS 0 - Data-in Hold Time tDD 15 - 10 -SA Min Max 0 15 10 0 15 -lOA Min Max - 0 - 15 10 0 15 Max - 0 - 20 20 0 20 -10 -S Min Min Max - 0 - 15 - 15 0 15 Min Unit Note ns 10 Max - 0 20 20 0 20 ns ns ns 11 ns 11 Refresh Cycle HB56D132BR/SBR -6A Symbol Parameter -7A -8A Min Max Min Max -lOA Min Max Min -10 -S Max Min Max Min Unit Note Max CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 10 - 10 - 10 - 10 - 20 - 20 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - 10 - 10 - ns Fast Page Mode Cycle HB56DI32BR/SBR Parameter -6A Symbol -7A Min Max Min -8A Max Min -lOA Max -10 -S Min Max Min Max Unit Note Min Max Fast Page Mode Cycle Time tpc 40 - 45 - 50 - 55 - 55 - 55 - ns Fast Page Mode CAS Precharge Time tcp 10 - 10 - 10 - 10 - 10 - 10 - ns Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 - 100000 - 100000 - 100000 - 100000 ns 13 Access Time from CAS Precharge tACP - 35 - 40 - 45 - 50 - 50 - 50 ns 14 RAS Hold Time from CAS Precharge tRHCP 35 - 40 - 45 - 50 - 50 - 50 - ns Notes: 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :$ tRCD (max) and tRAD :$ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRcD ~ tRCD (max), tRAD :$ tRAD (max). 5. Assumes that tRcD :$ tRcD (max), tRAD ~ tRAD (max). 6. !oFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. Early write cycle only (twcs ~ twcs (min». 11. These parameters are referenced to CAS leading edge in an early write cycle. 12. An initial pause of 100 ",S is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). 13. tRASC is determined by RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tACP. 15. tREF is determined by 1,024 refresh cycles. ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 B15 HB56D132 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read Cycle tRC Address tCAC tOFF Valid Output Dout tRAC Din High-Z ~ : Don't care 0155-5 ~HITACHI 816 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 HB56D132 Series • Early Write Cycle tRC Address Din Dout High-Z ~ : Don't care 0155-6 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 817 HB56D132 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • RAS Only Refresh Cycle tRC Address High-Z Dout 1 WE : Don't care 2 ~: Don't care 0155-7 • CAS Before RAS Refresh Cycle tRC tRP tCSR tCHR Address, Din: Don't care 2 Dout: High-Z 3 ~: Don't care 4 WE=VIH 0155-8 • 818 HITACHI Hitachi America, Ltd.' Hitachi Plaza '2000 Sierra Point Pkwy.' Brisbane, CA 94005·1819' (415) 589·8300 HB56D132 Series • Fast Page Mode Read Cycle tRASC tT tASR Address tOFF Dout lid Valid Output 1 }---(I Output 2 Valid Output N tRAC High-Z Din ~ : Don't care 0155-9 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 819 HB56D132 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Early Write Cycle tRASC Address Din High-Z Dout ~ : Don't care 0155-10 • 820 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56D232B Series 2,097,152-Word x 32-81t High Density Dynamic RAM Module • DESCRIPTION The HB56D232B is a 2M x 32 dynamic RAM module, mounted 16 pieces of 4Mbit DRAM (HM514400JP) sealed in SOJ package. An outline of the HB56D232B is 72-pin single in-line package. Therefore, the HB56D232B makes high density mounting possible without surface mount technology. The HB56D232B provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ but only on the one side of its module board. • PIN OUT ,--------------------------------------, ~o00::::::::::::::::00 0 r'\ 38 pln l \ 1 pin 00::::::::::::::::00 , 37 pin 72 pin I 0132-1 • FEATURES • 72-pin Single In-line Package Lead Pitch ................................ 1.27mm • Single 5V (±5%) Supply • High Speed Access Time ............ 80 ns/100 ns/120 ns (max) • Low Power Dissipation Active Mode ............. 3.99W/3.57W/3.15W (max) Standby Mode ...................... 168 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycles .......................... (16 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible • ORDERING INFORMATION Part No. Access Time HB56D232B-8 80ns HB56D232B-1O lOOns HB56D232B-12 120ns Pin No. 1 2 3 Pin Name Pin No. Pin Name 19 NC 37 20 DQ4 38 0020 DQs Pin Name Pin No. VSS DQo 21 Pin No. Pin Name NC 55 DQ11 NC 56 DQ27 39 40 VSS CASO 57 DQI2 58 DQ28 0021 DQ6 41 CAS2 59 Vee 42 CAS3 60 DQ22 43 CASI 61 DQ29 DQ\3 44 45 46 RASO RASI 62 DQ30 63 DQI4 NC 64 DQ31 41 WE 65 4 DQI6 DQI 5 DQn 22 23 6 DQ2 24 8 DQI8 DQ3 25 26 DO? 9 DQI9 27 10 28 29 0023 A7 NC 7 Package 11 Vee NC 72-pin SIP Socket Type 12 Ao 30 Vee 48 NC 66 DQls NC 13 A8 49 DQ8 67 PDI 50 0024 DQ9 68 PD2 69 PD3 70 71 PD4 NC 72 Vss • PRESENCE DETECT PINOUT HB56D132BR Pin No. Pin Name 80ns lOOns 120ns 67 PDI VSS VSS VSS 68 PD2 PD3 VSS NC VSS 69 VSS VSS NC 70 PD4 VSS VSS NC Al 31 14 A2 32 15 A3 33 A9 RAS3 16 A4 34 RAS2 52 17 As 35 NC 53 0025 DQIO 18 A6 36 NC 54 0026 51 • PIN DESCRIPTION Pin Name Function Ao- A9 Address Input Ao- A9 Refresh Address Input 000-0031 CASO-CAS3 Column Address Strobe RASO-RAS3 Row Address Strobe WE ReadIWrite Enable Data-in/Data-out Vee Power Supply ( + 5V) VSS PDI-PD4 NC Ground Presence Detect Pin Non-Connection eHITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 821 HB56D232B Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM RASO CA50 1101 CAS RAS 1102 1103 DO DOD 001 002 003 .OE 1104 DQ4 1101 CAS RAS OOS 1102 1103 DQ6 V04 007 03 .~E VOl RAS CAS V02 V03 01 V04 .OE .OE VOl RAS CAS V02 V03 D2 V04 Ii: CASi DQ6 1101 CAS RAS 1102 0011 0010 1103 V04 0011 D4 .~ 0012 0013 0014 0015 1101 CAS RAS 1102 1103 .OE V04 07 VOl RAS CAS V02 V03 .OE .OE V04 os 1101 RAS CAS V02 V03 V04 D6 RAS3 RAS2 am 0016 0017 0018 00111 D8 0020 0021 0022 0023 011 010 0024 0025 0026 0027 012 013 0028 00211 0030 0031 015 014 CAs3 ·00-015 : HM514400JP AO-AII • • 00-015 WE. • 00-015 Vee .::co \Iaa -,= CO-C7 . 00-015 • 00-015 0132-2 • 822 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56D232B Series • PHYSICAL OUTLINE Unil:= 107.95 4.25 101.19 3.1184 9.144 maxi 0.36 2-0~ 6. 0.25 1.57 RO.062 44.45 1.75 0132-3 Detail B Detail A 80M 100no ]f~E ~E mrrnmm rHllllnlm 12000 YuaE mrrnmm f'51 _2.54 _min. _ 0.100 ,.-1.07 max. 0.042 ::-=:::f:::0.25 max. --I 0.010 0132-4 0132-5 Note: The plating of the contact finger is gold. • HITACHI Hitachi America, Ltd. • Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819' (415) 589·8300 823 HB56D232B Series • ABSOLUTE MAXIMUM RATINGS Parameter Value Unit (Input) Symbol Yin -1.0to +7.0 V (Output) Vout -1.0to +7.0 V Supply Voltage Relative to VSS VCC -1.0to +7.0 V Short Circuit Output Current lout 50 rnA I I Voltage on Any Pin Relative to Vss Power Dissipation PT 8 W Operating Temperature Topr Oto + 70 ·C Storage Temperature Tstg - 55 to + 125 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter = 0 Symbol Supply Voltage to + 70'C) Min Typ Max Unit VSS 0 0 0 V Note Vcc 4.75 5.0 5.25 V 1 Input High Voltage VIH 2.4 5.5 V 1 Input Low Voltage VIL -1.0 - O.S V 1 Note: I. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to +70'C, Vee = 5V ±5%, Vss = OV) Parameter Symbol Operating Current Standby Current ICCI HB56D232B-S HB56D232B-1O HB56D232B-12 Min Max Min Max Min Max - 760 - 680 - 600 Unit Test Conditions rnA tRC = Min - 32 - 32 - 32 rnA TTL Interface RAS, CAS = VIH, Dout = High-Z - 16 - 16 - 16 rnA CMOS Interface RAS, CAS i--1«:-_ _-= 1. 27 t 0.05 ·1.75 J o i~DDDDDDDi !! !! I!!I !! o!I I!I !!l !! 0156-3 Detail A 60ns 70ns r ~~~oc 80ns [IJJIIJJ( OObl O DO 0 DODD 0000000000 0000000000 lOOns ~BIIJJIIJJ( ,-~~blbI 0000000000 0000000000 OOObl DOD [IJJ[IJJ( Detail B Note: Following the specification of the contact pads. :f 2.54M:!ln. 0.100 1 7m x 0.042 Part No. o.25m... 0010 Contact Pad HB56D232BS-XX Gold HB56D232SBS-XX Solder 0156-4 ~HITACHI 832 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HB56D232BS/SBS Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol I I Value (Input) Yin -1.0to (Output) V out -1.0to Supply Voltage Relative to VSS VCC - 1.0 to Short Circuit Output Current lout Voltage on Any Pin Relative to Vss Power DIssIpation PT Topr V V Storage Temperature T stg rnA W S + 70 55 to + 125 ·C Oto - • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to Symbol Supply Voltage V 50 Operating Temperature Parameter Unit + 7.0 + 7.0 + 7.0 ·C + 70'C) Min Typ Max Unit VSS 0 0 0 V Note VCC 4.75 5.0 5.25 V 1 Input High Voltage VlH 2.4 - 5.5 V 1 Input Low Voltage VIL -1.0 - O.S V 1 Note: I. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to + 70'C, Vee = 5V ± 5%, Vss = OV) HB56D232BS/SBS Parameter Symbol -6A Min Operating Current ICC! Standby Current -SA -7A Max Min Max Min Unit -lOA Max Min Max ICC3 = - 920 - S40 - 760 - 680 rnA tRC - 32 - 32 - 32 - 32 rnA TTL Interface RAS, CAS = VlH D out = High-Z - 16 - 16 - 16 - 16 rnA CMOS Interface RAS, CAS;:: Vcc - 0.2V Dout = High-Z - 920 - 840 - 760 - 680 rnA tRC RAS CAS Dout ICC2 RASOnly Refresh Current Test Condition = = = = 1,2 Min Min 2 VlH VIL Enable 1 Standby Current ICC5 - SO - 80 - 80 - 80 rnA CAS Before RAS Refresh Current ICC6 - 920 - 840 - 760 - 680 rnA tRC = Min - 920 - 840 - 760 - 680 rnA tpc = Min Page Mode Current icC? Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 p,A OV S Yin S 7V Output Leakage Current ILO -10 10 -10 10 -10 10 -10 10 p,A OV S Vout S 7V, D out = Disable Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 Vcc 2.4 Vcc V High lout = - Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 V Low lout = Notes: Note 1,3 5 rnA 4.2 rnA 1. ICC depends on output load condition when the device is selected, Icc max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIL. 3. Address can be changed S 1 time while CAS = VlH. ~HITACHI Hitachi America, Ltd.' Hilachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 833 HB56D232BS/SBS Series • Capacitance (TA = 25'C, Vee 5V ±5%) = Parameter Notes: Symbol Typ Max Unit Note 121 pF 1 CI2 - 137 pF 1 Input Capacitance (RAS, CAS) CI3 - 4S pF I Output Capacitance (DQo-DQ3J) CliO - 29 pF 1,2 Input Capacitance (Address) Cn Input Capacitance (WE) I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIR to disable D ont . • AC Characteristics (TA = 0 to +70'C, Vee = 5V ±5%, Vss Read, Write and Refresh Cycle (Common Parameters) = OV)1, 12 HB56D232BS/SBS Parameter Symbol Random Read or Write Cycle Time RAS Precharge Time -6A -7A -SA Unit -lOA Min Max Min Max Min Max Min Max tRC 110 - 130 - 150 - ISO - ns - 50 - 60 - 70 - ns Note tRP 40 RAS Pnlse Width tRAS 60 10000 70 10000 SO 10000 100 10000 ns CAS Pulse Width tCAS 15 10000 20 10000 20 10000 25 10000 ns Row Address Setup Time tASR 0 - 0 - 0 - 0 - ns Row Address Hold Time tRAH 10 - 10 - 10 - 15 - ns Column Address Setup Time tASC 0 - 0 - 0 - 0 - ns Column Address Hold Time tCAH 15 - 15 - 15 - 20 - ns RAS to CAS Delay Time tRCD 20 45 20 50 20 60 25 75 ns S RAS to Column Address Delay Time tRAD 15 30 15 35 15 40 20 55 ns 9 25 RAS Hold Time tRSH 15 - 20 - 20 tCSH 60 - 70 - SO - 100 - ns CAS Hold Time CAStoRAS Precharge Time tCRP 10 - 10 - 10 - 10 - ns Transition Time (Rise and Fall) tT 3 50 3 50 3 50 3 50 ns 7 tREF - 16 - 16 - 16 16 ms 15 Refresh Period - ~HITACHI 834 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 ns HB56D232BS/SBS Series Read Cycle HB56D232BS/SBS Parameter Symbol -6A Min Max tRAC - Access Time from CAS tCAC Access Time from Address Read Command Setup Time Access Time fromRAS -8A -7A Min Max -lOA Max Min Min Unit Note Max 80 - 100 ns 2,3 - 20 - 25 ns 3,4 35 - 40 - 45 ns 3,5 0 - 0 - 0 - ns 60 - 70 - - 15 - 20 tAA - 30 - tRCS 0 - Read Command Hold Time to CAS tRCH 0 - 0 - 0 - 0 - ns Read Command Hold Time to RAS tRCH 0 - 0 - 0 - 0 - ns Column Address to RAS Lead Time tRAL 30 - 35 - 40 - 55 - ns Output Buffer Turn-off Time tOFF 0 15 0 20 0 20 0 25 ns 6 Unit Note 10 Write Cycle HB56D232BS/SBS Parameter Symbol -6A Min -7A Max Min -8A Max Min -lOA Max Min Max Write Command Setup Time twcs 0 - 0 - 0 - 0 - ns Write Command Hold Time tWCH 15 - 15 - 15 - 20 - ns Write Command Pulse Width twp 10 - 10 - 10 - 20 - ns Data-in Setup Time tos 0 - 0 - 0 - 0 - ns 11 Data-in Hold Time tDH 15 - 15 - 15 - 20 - ns 11 @HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 835 HB56D232BS/SBS Series Refresh Cycle HB56D232BS/SBS Parameter Symbol -6A -7A -SA Min Max Min Max Min tCSR 10 - 10 - 10 CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 10 - 10 - RAS Precharge to CAS Hold Time tRPC 10 - 10 - CAS Setup Time (CAS Before RAS Refresh Cycle) Unit -lOA Max Min Max - 10 - ns 10 - 10 - ns 10 - 10 - ns Note Fast Page Mode Cycle HB56D232BS/SBS Parameter Symbol -6A -7A -SA Unit -lOA Min Max Min Min Max Min Max tpc 40 - 45 - 50 - 55 - ns Fast Page Mode CAS Precharge Time tcp 10 - 10 - 10 - 10 - ns Fast Page Mode RAS Pulse Width tRASC - Access Time from CAS Precharge tACP RAS Hold Time from CAS Precharge tRHCP Fast Page Mode Cycle Time Notes: 35 Max 100000 - 100000 - 100000 - 100000 ns 13 35 - 40 - 45 - 50 ns 14 - 40 - 45 - 50 - ns 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD S tRCD (max) and tRAD S tRAD (max). If tRCD or tRAD is greater thaa the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD ~ tRCD (max), tRAD S tRAD (max). 5. Assumes that tRCD S tRCD (max), tRAD ~ tRAD (max). 6. tOFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) aad VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 10. Early write cycle only (twcs ~ twcs (min)). II These parameters are referenced to CAS leading edge in an early write cycle. 12. An initial pause of 100 p,s is required after power up followed by a minimum of eight initialization cycles (aay combination of cycles containing RAS clock such as RAS only refresh). 13. tRASC is determined by RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tACP. 15. tREF is determined by 1,024 refresh cycles. @HITACHI 836 Note Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HB56D232BS/SBS Series • TIMING WAVEFORMS • Read Cycle tRC Address WE tCAC tOFF Valid Output Dout tRAC Din High-Z ~ : Don't care 0156-5 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 837 HB56D232BS/SBS Series - - - - - - - - - - - - - - - - - - - - - - - - - - • Early Write Cycle tRC Address Dout High-Z Din ~ : Don't care 0156-6 • 838 HITACHI Hitachi America, Ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56D232BS/SBS Series • RAS Only Refresh Cycle tRe Address High-Z Dout 1 WE : Don't (are 2 ~: Don't (are 0156-7 • CAS Before RAS Refresh Cycle tRe tRP tesR teHR Address, Din: Don't care 2 Dout: High-Z 3 ~: Don't care 4 WE=VIH 0156-6 @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 839 HB56D232BS/SBS Series • Fast Page Mode Read Cycle tT tASR Address Dout Valid - - - - ' t - - - - - - - - - { I Output 1 High-Z Din ~ : Don't care 0156-9 ~HITACHI 840 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56D232BS/SBS Series • Fast Page Mode Early Write Cycle tRASC Address Dout Din High-Z ~ : Don't care 0156-10 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 841 HB56D25636 Series 262,144·Word x 36·Bit High Density Dynamic RAM Module • DESCRIPTION The HB56D25636B is a 256k x 36 dynamic RAM module, mounted 8 pieces of 1 Mbit DRAM (HM514256JP) sealed in SOJ package and 4 pieces of 256k-bit DRAM (HM51256CP) sealed in PLCC package. An outline of the HB56D25636B is 72-pin single in-line package. Therefore, the HB56D25636B makes high density mounting possible without surface mount technology. The HB56D25636B provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ and PLCC. • FEATURES • 72-pin Single In-line Package Lead Pitch ..................................................... 1.27mm • Single 5V (±5%) Supply • High Speed Access Time ................................. 85 ns/100 ns/120 ns (max) • Low Power Dissipation Active Mode ........................... 4.24 mW/3.57 mW/3.02 mW (max) Standby Mode ............................................ 126 mW (max) • Fast Page Mode Capability • 512 Refresh Cycle ................................................... (8 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TIL Compatible • ORDERING INFORMATION Part No. Access Time Package HB56D25636B-85 HB56D25636B-1O HB56D25636B-12 85 ns lOOns 120ns 72-pin SIP Socket Type • PIN OUT o 00----------------00 '1 pin 36 pin! o 00----------------00 '37 pin 72 pin! Pin No. Pin Name Pin No. Pin Name I Vss 37 DQ17 2 DQo 38 DQ35 3 DQI8 39 Vss 4 DQI 40 CASO 5 DQI9 41 CAS2 6 DQ2 42 CAS3 7 DQ20 43 CASI 8 DQ3 44 RASO NC 9 DQ2I 45 10 Vee 46 NC II NC 47 WE 12 Ao 48 NC 13 AI 49 DQ9 14 A2 50 DQ27 15 A3 51 DQIO 16 A4 52 DQ28 17 A5 53 DQII 18 A6 54 DQ29 19 NC 55 DQI2 20 DQ4 56 DQ30 21 DQ22 57 DQi3 22 DQ5 58 DQ3I 23 DQ23 59 Vee 24 DQ6 60 DQ32 25 DQ24 61 DQI4 26 DQ7 62 DQ33 27 DQ25 63 DQI5 28 A7 64 DQ34 29 NC 65 DQI6 30 Vee 66 NC 31 As 67 PDI 0128-1 32 NC 68 PD2 33 NC 69 PD3 34 RAS2 70 PD4 35 DQ26 71 NC 36 DQs 72 Vss ~HITACHI 842 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HB56D25636 Series • BLOCK DIAGRAM ~:::::::~::~::~~ ~ 001 OQO 002 0Q3 ~~~~§ 0Q4 DO!> 0Q8 02 007 0Q8 • Olnlou1 MIl CAS1 1101 CAS RAS 1102 04 1103 1104 0Q9 0010 0011 0012 0013 0014 0015 0016 mOE 1101 CAS RAS 1102 1103 os 1104 mOE I CAS RAS 0017··--------i~~nI~ou1~M~1~~ Rm::====::-, em 0018§~ 01 0019 0020 0021 0022:=~~r::~ 0023 0024 0025--------1 03 0026.:====:!:~~~:".J em 0027§~ 0028 0029 0Q30 05 0Q31 0Q32 0Q33 0034 0Q35.~------~~~~C=~ AO-A8 • • 00-07, MO-M3 • 00-07, MIl-M3 WE "00-07 : HM514256JP Vet; :::X=CO-C1,' 00-07, MO-M3 MO-M3 : HM51256CP Vss =r= . 00-07, MO-M3 0128-2 @HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 843 HB56D25636 Series • PHYSICAL OUTLINE 107.95 4.25 5 ~~;.ax 101.19 3.98 0000000 !J ~~ 1.194 1.75 1.75 I I II _ !1ll. (1.27 IYP) [lj5 1f.04'I' 0.054 Note: The plating of the contact finger is gold. Detail A 85 ns 100 ns 120 ns Detail B 0128-3 ~HITACHI 844 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56D25636 Series • PRESENCE DETECT PIN ARRANGEMENT • PIN DESCRIPTION Pin Name Function Pin No. Pin Name Refresh Address Input 67 PDI Data-in/Data-out 68 PD2 Column Address Strobe 69 Row Address Strobe 70 Ao-As Address Input Ao-As DQo-DQ35 CASO,CAS3 RASO,RAS2 WE Read/Write Enable Vee Power Supply ( + 5V) Vss PDI-PD4 Ground NC Non-Connection HB56D25636B 85 ns lOOns 120ns Vss NC Vss NC Vss NC PD3 NC Vss NC PD4 Vss VSS NC Presence Detect Pin • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value I (Input) VIN - 1.0 to I (Output) VOUT - 1.0 to Supply Voltage Relative to Vss Vee - 1.0 to Short Circuit Output Current lout 50 Voltage on Any Pin Relative to Vss Power Dissipation Topr Storge Temperature Tstg V V V rnA W 12 PT Operating Temperature Unit + 7.0 + 7.0 + 7.0 + 70 55 to + 125 'c 'c Oto - • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70'C) Parameter Supply Voltage Note: Min Typ Max Unit VSS Symbol 0 0 0 V Note Vee 4.75 5.0 5.25 V I Input High Voltage VIH 2.4 5.5 V I Input Low Voltage VIL -1.0 - 0.8 V I I. All voltage referenced to Vss. @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 845 HB56D25636 Series • DC Electrical Characteristics (TA = 0 to + 70·C, Vee = 5V ± 5%, Vss = OV) HB56D25636B Parameter Symbol Operating Current Standby Current -10 -85 Min Max - 808 ICCI Min - -12 Max 680 Min Unit Test Conditions - 576 rnA tRc = Min 1,2 - 24 - 24 - 24 rnA TTL Interface RAS, CAS = VIH, Dout = High-Z - 12 - 12 - 12 rnA CMOS Interface RAS, CAS ~ Vcc - 0.2V, Dou! = High-Z ICC2 RASOnly Refresh Current ICC3 - 808 - 680 - 576 rnA tRC Standby Current Iccs - 64 - 64 - 64 rnA RAS = VIH, CAS = VIL, DOU! = Enable CAS Before RAS Refresh Current ICC6 - 768 - 660 - 556 rnA tRc = Min Page Mode Current ICC7 - 764 - 680 - 576 rnA tpc = Min Input Leakage Current ILl -10 10 -10 10 -10 10 p,A OV S Yin S 7V Output Leakage Current ILO -10 10 -10 10 -10 10 p,A OV S yOU! S 7V, Dou! = Disable Output High Voltage VOH 2.4 Vcc 2.4 Vcc 2.4 Vcc V High lout Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 rnA Notes: Note Max = 2 Min = - 1 1,3 5 rnA I. Icc depends on output load condition when the device is selected, Icc max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIL. 3. Address can be changed once or less while CAS = VIH' • Capacitance (TA = 25·C, Vee = 5V ±5%) Parameter Symbol Typ Max Unit 88 pF I 104 pF 1 57 pF 1 36 pF I CliO I - 17 pF 1,2 CII02 - 22 pF 1,2 CI3 - CI4 - Output Capaoltance (DQo-DQ7' DQ9-DQI6, DQIs-DQ2S, DQ27- DQ34) Output Capacitance (DQs, DQ17, DQ26, DQ3S) Input Capacitance (Address) CIl Input CapacitRnce (WE) CI2 Input Capacitance (RAS) Input Cai'acitan.oc (CAS) Notes: I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D out . ~HITACHI 846 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589·8300 Note HB56D25636 Series • AC Characteristics (TA ~ 0 to +70'C, Vee ~ SV ±S'Yo, Vss Read, Write and Refresh Cycle (Common Parameters) Parameter Symbol ~ OV)1, 12 HB56D25636B-12 HB56D25636B-85 HB56D25636B-1O Min Max Min Max Min Max - 190 - 220 - Unit Random Read or Write Cycle Time tRC 160 RAS Precharge Time tRP 70 RAS Pulse Width tRAS 80 10000 100 10000 120 10000 ns CAS Pulse Width tCAS 25 10000 25 10000 30 10000 ns Row Address Setup Time tASR 0 Row Address Hold Time tRAH 12 Column Address Setup Time tASC 0 Column Address Hold Time tCAH 20 Column Address Hold Time to RAS tAR RAS to CAS Delay Time RAS to Column Address Delay Time 80 90 Note ns ns 0 - 0 - ns 15 - 15 - ns 0 - 0 - ns 20 25 - ns 75 - 90 - ns 55 25 75 25 90 ns 8 17 45 20 55 20 65 ns 9 25 - 30 - ns 100 - 120 - ns 10 - 10 - ns 3 50 ns 7 8 ns 15 Unit Note 60 - tRCD 22 tRAD RAS Hold Time tRSH 25 CAS Hold Time tcSH 85 CAS to RAS Precharge Time tCRP 10 - Transition Time (Rise and Fall) tT 3 50 3 50 Refresh Period tREF - 8 - 8 - Read Cycle Parameter Symbol HB56D25636B-85 HB56D25636B-IO HB56D25636B-12 Min Max Min Max Min Max 85 - 100 - 120 ns 2,3 25 25 - 30 ns 3,4 3,5 Access Time from CAS tcAC Access Time from Address tAA - 40 - 45 - 55 ns Read Command Setup Time tRCS 0 - 0 - 0 - ns Read Command Hold Time to CAS tRcH 0 - 0 - ns tRRH 10 10 10 tRAL 40 45 55 - ns Column Address to RAS Lead Time - - 0 Read Command Hold Time to RAS Output Buffer Tum-off Time !oFF 0 20 0 25 0 30 ns 6 Unit Note Access Time from RAS tRAC ns Refresh Cycle Parameter Symbol HB56D25636B-85 HB56D25636B-1O HB56D25636B-12 Min Max Min Max Min Max CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tcHR 20 - 20 - 25 - ns tRPC 15 - 15 - 15 - ns RAS Precharge to CAS Hold Time .HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 847 HB56D25636 Series Write Cycle Parameter Symbol HB56D25636B-S5 HB56D25636B-1O HB56D25636B-12 Min Min Min Max Max Max Unit Note - ns 10 ns 0 - ns 11 25 - ns 11 90 - ns Write Command Setup Time twcs 0 - 0 - 0 Write Command Hold Time tWCR 20 - 25 - 30 Write Command Hold Time to RAS tWCR 65 Write Command Pulse Width twp 15 - 20 Data-in Setup Time tos 0 - 0 Data-in Hold Time tOR 20 20 Data-in Hold Time to RAS tORR 60 - 80 75 95 25 ns ns Fast Page Mode Cycle Parameter Symbol HB56D25636B-S5 Max Min HB56D25636B-1O HB56D25636B-12 Min Min Max Max Unit Fast Page Mode Cycle Time tpc 55 - 55 - 65 - ns Fast Page Mode CAS Precharge Time tcp 10 - 15 - 20 - ns Fast Page Mode RAS Pulse Width tRASC SO Access Time from CAS Precharge tACP - 50 - 50 RAS Hold Time from CAS Precharge tRHCP 50 - 50 - Notes: 100000 100000 120 100000 ns 13 - 60 ns 14 60 - ns I. AC measurements assume tT = 5 ns. 2. Assumes that tRCO S tRCO (max) and tRAo S tRAD (max). If tRCO or tRAO is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL load and 100 pF. 4. Assumes that tRCO ~ tRCO (max), tRAo S tRAO (max). 5. Assumes that tRCO S tRCO (max), tRAO ~ tRAO (max). 6. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIR (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIR and VIL. S. Operation with the tRCO (max) limit insures that tRAC (max) can be met, tRCO (max) is specified as a reference point only, if tRCO is greater than the specified tRCO (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAO (max) limit insures that tRAC (max) can be met, tRAO (max) is specified as a reference point only, if tRAO is greater than the specified tRAO (max) limit, then access time is controlled exclusively by tAA' 10. Early write cycle only (twcs ~ twcs (min». II. These parameters are referenced to CAS leading edge in an early write cycle. 12. An initial pause of 100 /-,S is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). 13. tRASC defines RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tACP' 15. tREF defines is 512 refresh cycles. • 848 100 Note HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56D25636 Series • TIMING WAVEFORMS • Read Cycle tT RCD tCSH tCAS Address tCAC tM Dout Valid Ouut tRAC High-Z Din ~ : Don't care 0128-4 @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005·1819· (415) 589·8300 849 HB56D25636 Series - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ • Early Write Cycle tT RCD tCSH Address Dout Din High-Z WM ;Don't care 0128-5 ~HITACHI 850 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56D25636 Series • RAS Only Refresh Cycle Address Dout 1 WE : Don't care 2 WM :Don't care 0128-06 • CAS Before RAS Refresh Cycle tCSR tCHR 1 Address. Din: Don't care 2 Dout: High-Z 3 ~ : Don't care 0128-07 eHITACHI Hitachi America, Ltd.• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 851 HB56D25636 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read Cycle tRASC tRHCP ~\ II .!r... tpc tCSH tCAS tCAS tRCD ~ '----I Address ~ ~ ~tASe Row ~ i tcp tRAD R ~ Column 1 ~////////~ E lASH tRCH - I - CoIumn2 ~ IRCH ~t' tCAC I J Dout tCAC tM tACP ICRP ~ ColumnN ~ tRCS ~/////~ tRRH --'-=1 tRCS tM I " tRAl. tCAH ASe ~ ~ ~ I~CAH. tASe tRP tcAS ~" ~ tCAC 1M tACP tOFF !oFF Valid ~d ut2 oUiiiii 1 tOFF } Valid Outpl4 N tRAC High-Z Din WM :Don't care 0128-8 • 852 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-~819. (415) 589-8300 HB56D25636 Series • Fast Page Mode Early Write Cycle tRASe Address Dout High·Z Din E2822I :Don't care 0128-9 ~HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 853 HB56D51236 Series 524,288-Word x 36·Bit High Density Dynamic RAM Module • DESCRIPTION The HB56D51236B is a 512k x 36 dynamic RAM module, mounted 16 pieces of 1 Mbit DRAM (HM514256JP) sealed in SOJ package and 8 pieces of 256k-bit DRAM (HM51256CP) sealed in PLCC package. An outline of the HB56D51236B is 72-pin single in-line package. Therefore, the HB56D51236B makes high density mounting possible without surface mount technology. The HB56D51236B provides common data inputs and outputs. Decoupling capaCitors are mounted beneath each SOJ and PLCC but only on the one side of its module board. Pin No. Pin Name Pin No. Pin Name I Vss 37 DQI7 2 DQo 38 DQ35 3 DQI8 39 Vss 4 DQI 40 CASO • FEATURES 5 DQI9 41 CAS2 • 72-pin Single In-line Package Lead Pitch ..................................................... 1.27mm • Single 5V (±5%) Supply • High Speed Access Time ................................. 85 ns/100 ns/120 ns (max) • Low Power Dissipation Active Mode .................................. 4.58W/3.91W/3.36W (max) Standby Mode ............................................ 252 mW (max) • Fast Page Mode Capability • 512 Refresh Cycle ................................................... (8 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible 6 DQ2 42 CAS3 7 DQ20 43 CASI 8 DQ3 44 RASO RAS1 • ORDERING INFORMATION Part No. Access Time HB56D51236B-85 85 ns HB56D51236B-IO lOOns HB56D51236B·12 120ns Package 72-pinSIP Socket Type • PIN OUT I o 00--·-------------00 '1 pin 36 pinl o 00·---------------00 '37 pin 72 pin! 0129-1 $ 854 9 DQ21 45 10 Vee 46 NC 11 NC 47 WE 12 Ao 48 NC 13 Al 49 DQ9 14 A2 50 DQ27 15 A3 51 DQIO 16 A4 52 ~s 17 A5 53 DQll 18 A.(i 54 D~9 19 NC 55 DQ12 20 DQ4 56 DQ30 21 DQ22 57 DQ\3 22 DQ5 58 DQ31 23 DQ23 59 Vee 24 DQ6 60 DQ32 25 DQ24 61 DQI4 26 ~ 62 DQ33 27 D~5 63 DQI5 28 A7 64 DQ34 29 NC 65 DQI6 30 Vee 66 NC 31 67 PDI 32 As NC 68 PD2 33 RAS3 69 PD3 34 RAS2 70 PD4 35 DQ26 71 NC 36 DQ8 72 Vss HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 HB56D51236 Series • BLOCK DIAGRAM I RASO CASO 000 001 002 003 VOl CAS RAS V02 V03 DO V04 ~OE ~ OE ~~ ~ 008 • V02 V03 V04 ~OE 01 ~ VOl CAS RAS V02 03 V03 004 005 006 007 VOl RAS CAS VOl RAS CAS V02 V03 D2 V04 ~OE ~ CAS RAS Dinlau! MO RAS CAS Oinlou1 Ml VOl CAS RAS V02 04 V03 V04 VOl RAS CAS V02 V03 D5 CASI 009 0010 0011 0012 ~OE 0013 0014 0015 0016 0017 V04 ~OE ~ VOl CAS RAS V02 07 V03 V04 ~OE ~ VOl RAS CAS V02 V03 V04 ~OE ~ RAS CAS OinioUl M3 CAS RAS DiniOlA M2 • RAS3 I RAS2 CAS2 0018 0019 0020 0021 VOl CAS RAS V02 08 V03 V04 ~OE ~ 0022 0023 0024 0025 VOl RAS CAS V02 V03 V04 ~OE VOl RAS CAS V02 V03 V04 010 ~OE ~ • D9 ~ VOl CAS RAS V02 011 V03 V04 ~OE 0026 os ~ CAS RAS DiniOlA M4 RAS CAS Oinlou1 M5 VOl CAS RAS V02 V03 012 V04 VOl RAS CAS CAS3 0027 0028 0029 0030 ~Foif VOl CAS RAS V02 015 V03 V04 ~OE ~ 013 ~ ~ 0031 0032 0033 0034 V02 V03 V04 ~OE VOl RAS CAS V02 V03 V04 ~OE ~ I 014 I CAS RAS RAS CAS o035··--------i:o~i~nI~0IA~M6~~~------_t0~inl~O~UI~M~7~~ AO-A8. • DO-DIS, MO-M7 • 00-015, MO-M7 ~ Vee ::L::CO-Cl1' DO-015, MO-M7 Vss ::L:: • DO-DIS, MO-M7 0129-2 *00-015: HM514256JP MO-M7: HM51256CP @HITACHI Hitachi America, Ltd.' Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 855 HB56D51236 Series • PHYSICAL OUTLINE Unit: :~ 107.95 4.25 :~~'I 101.19 3.98 o CJODDDDDO ~~ ~ RO.052 1.15 1.ill _ 0.054 bill. 0.047 1.75 ~r~~ (1ll. 'YP) 0.05 II Note: The plating of the contact finger is gold. 0129-3 Detail A 85ns 100 ns 120 ns ~~I ~~I ~~l ----~- 0129-4 Detail B min~l 0.100 t1"I 2.54 - 4o.25ma,. 0.010 1.07 max. 0.042 0129-5 ~HITACHI 856 Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HB56D51236 Series • PRESENCE DETECT PIN OUT • PIN DESCRIPTION Pin Name HB56D51236B Function Pin No. Pin Name Refresh Address Input 67 DQo-DQ35 Data-in/Data-out 68 CASO-CAS3 Column Address Strobe 69 PD3 RASO-RAS3 Row Address Strobe 70 PD4 WE ReadIWrite Enable Ao-AS Address Input Ao-As Vee Power Supply ( + 5V) VSS Ground PDl-PD4 Presence Detect Pin NC Non-Connection 85 ns lOOns POI NC NC 120ns NC PD2 VSS VSS VSS NC VSS NC VSS VSS NC • ABSOLUTE MAXIMUM RATINGS Value Unit (Input) Vin -1.0to + 7.0 V (Output) Vout -1.0to + 7.0 V Supply Voltage Relative to Vss Vee -1.0to + 7.0 V Short Circuit Output Current lout 50 rnA Parameter Voltage on Any Pin Relative to Vss Symbol I I Power Dissipation PT 12 W Operating Temperature Topr Oto +70 Storage Temperature T stg - 55 to + 125 'c 'c • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70'C) Parameter Supply Voltage Note: Min Typ Max Unit VSS 0 0 0 V Symbol Note Vee 4.75 5.0 5.25 V I Input High Voltage VIH 2.4 - 5.5 V I Input Low Voltage VIL -1.0 - 0.8 V I I. All voltage referenced to Vss. ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 857 HB56D51236 Series • DC Electrical Characteristics (TA = 0 to +70'C, Vee = 5V ±5%, Vss = OV) Parameter Symbol HB56D51236B-1O HB56D51236B-12 Min Max Min Max Min Max 872 - 744 - 640 - Operating Current ICCI Standby Current HB56D51236B-85 Unit Test Conditions rnA tRC = Min 1,2 - 48 - 48 - 48 rnA TTL Interface RAS, CAS = VIR, D out = High-Z - 24 - 24 - 24 rnA CMOS Interface RAS, CAS ~ VCC - 0.2V, D out = High-Z ICC2 RASOnly Refresh Current ICC3 - 872 - 744 - 640 rnA Standby Current ICC5 - 128 - 128 - 128 mA CAS Before RAS Refresh Current ICC6 - 832 - 724 - 620 mA tRC = Min Page Mode Current ICC7 - 828 - 744 - 640 rnA tpc = Min Input Leakage Current ILl -10 10 -10 10 -10 10 /LA OV:$ Vin:$ 7V Output Leakage Current ILO -10 10 -10 10 -10 10 /LA OV :$ Vout :$ 7V, Dout = Disable Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 Vce V High lout =- Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 mA Notes: = Min RAS = VIR, CAS = VIL, D out = Enable 2 tRC I 1,3 5 mA I. Icc depends on output load condition when the device is selected, Icc (max) is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIL. 3. Address can be changed once or less while CAS = V!H' • CapaCitance (TA = 25'C, Vee = 5V ±5%) Parameter Symbol Typ Max Unit Input Capacitance (Address) CIl - 161 pF I Input Capacitance (WE) CI2 - 193 pF 1 Note Input Capacitance (RAS, CAS) CI3 - 62 pF 1 Output Capacitance (DQO-7' DQ9-16, DQI8-25, DQ27-34) CliO! - 29 pF 1,2 Output Capacitance (DQ8, 17, 26, 35) CII02 - 39 pF 1,2 Notes: I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIR to disable D out . ~HITACHI 858 Note Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HB56D51236 Series • AC Characteristics (TA = 0 to +70'C, Vee = 5V ±5%, Vss = OV)1, 12 Read, Write and Refresh Cycle (Common Parameters) Parameter Symbol HB56DS1236B-85 HB56DS 1236B-1O HB56D51236B-12 Min Min Max Min - 220 - ns 90 - ns Max Random Read or Write Cycle Time tRc 160 - 190 RAS Precharge Time tRP 70 - 80 RAS Pulse Width Max tRAS 80 10000 100 10000 120 10000 CAS Pulse Width tCAS 25 10000 25 10000 30 10000 Row Address Setup Time tASR 0 Row Address Hold Time tRAH 12 Column Address Setup Time tASC 0 Column Address Hold Time tCAH Column Address Hold Time to RAS tAR RAS to CAS Delay Time 20 - 60 - tRCO 22 55 RAS to Column Address Delay Time tRAO 17 RAS Hold Time tRSH CAS Hold Time CAS to RAS Precharge Time - Unit Note ns ns ns 0 - 0 15 - 15 0 - 0 - ns 20 - 25 - ns 75 - 90 - ns 25 75 25 90 ns 8 45 20 55 20 65 ns 9 25 - 25 30 85 100 120 tCRP 10 - - ns tCSH - 10 - 10 - ns Transition Time (Rise and Fall) tT 3 50 3 50 3 50 ns 7 Refresh Period tREF 8 ns 15 Unit Note 8 - 8 - - ns ns Read Cycle Parameter Symbol HB56DS 1236B-85 HB56D51236B-1O HB56D51236B-12 Min Min Max Min Max Max Access Time from RAS tRAC - 85 - 100 - 120 ns 2,3 Access Time from CAS tCAC - 25 - 25 - 30 ns 3,4 3,5 Access Time from Address tAA - 40 - 45 - 55 ns Read Command Setup Time tRCS 0 0 - 0 - ns Read Command Hold Time to CAS tRCH 0 - 0 - 0 - ns Read Command Hold Time to RAS tRRH 10 - 10 10 - ns Column Address to RAS Lead Time tRAL 40 - 45 - 55 - ns Output Buffer Turn-off Time !oFF 0 20 0 25 0 30 ns 6 Unit Note 10 Write Cycle Parameter Symbol HB56D51236B-85 HB56DS 1236B-1O HB56D51236B-12 Min Max Min Min Max 0 - 0 - ns 25 - 30 - ns Max Write Command Setup Time twcs 0 Write Command Hold Time tWCH 20 - Write Command Hold Time to RAS tWCR 65 - 80 - ns twp 15 - 20 - 95 Write Command Pulse Width 25 - ns Data-in Setup Time tos 0 0 - 0 - ns II Data-in Hold Time tOH 20 20 - 25 - ns II Data-in Hold Time to RAS tOHR 60 - 75 - 90 - ns @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 859 HB56D51236 Series Refresh Cycle Parameter Symbol HB56D51236B-85 Max Min HB56D51236B-1O HB56D51236B-12 Min Min Max Max Unit CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 20 - 20 - 25 - ns 15 - 15 - 15 - ns RAS Precharge to CAS Hold Time tRPC Note Fast Page Mode Cycle Parameter Symbol HB56D51236B-85 HB56D51236B-1O Min Max Min - 55 - 65 - ns 15 - 20 - ns Max Fast Page Mode Cycle Time tpc 55 Fast Page Mode CAS Precharge Time tcp 10 Fast Page Mode RAS Pulse Width tRASC 80 Access Time from CAS Precharge tACP - 50 - 50 RAS Hold Time from CAS Precharge tRHCP 50 - 50 - Notes: 100000 100000 Min Max Unit Note 100000 ns 13 - 60 ns 14 60 - ns 120 I. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :s tRCD (max) and tRAD :s tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD 2: tRCD (max) and tRAD :s tRAD (max). 5. Assumes that tRCD :s tRCD (max) and tRAD 2: tRAD (max). 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIR (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. Early write cycle only (twcs 2: twcs (min». II. These parameters are referenced to CAS leading edge in an early write cycle. 12. An initial pause of 100 I'-s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). 13. tRASC defines RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tACP' 15. tREF is defined as 512 refresh cycles. • 860 100 HB56D51236B-12 HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56D51236 Series • TIMING WAVEFORMS • Read Cycle tr RCD tcSH tCAS Address tCAC tAA Dout Valid au tRAC ut High·Z WM :Don't care Din 0129-6 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005· 1819· (415) 589·8300 861 HB56D51236 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Early Write Cycle tT RCD tCSH tCAS Address Dout Din High-Z WM :Don't care 0129-7 @HITACHI 862 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 HB56D51236 Series • RAS Only Refresh Cycle Address Dout 1 WE : Don't care 2 ~ : Don't care 0129-8 • CAS Before RAS Refresh Cycle tCSR tCHR 1 Address, Din: Don't care 2 Dout: High-Z 3 ~ : Don't care 0129-9 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 863 HB56D51236 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read Cycle lRASC IRHCP ~\ I .!L.. Ipc ICSH IRCO ICAS ICAS r\1'----/ I "~~ Icp lRAO lAS R Address ~ I.'CAH~ ~ IASC Row 0< Column 1 IRCS ~ IASC -, IRCH ~ CoIumn2 IRSH ICAS - ICAC lAA I ICAC lAA IACP ASC ~ Column N .~ ~ ~'/ ~/////h IRRH I ~ ICAC lAA IACP loFF IOFF Valid o)~:dut 1 Dout I lRAL ICAH ~ tRCH ~~/ r--- ICRP '\ IRCS ij'////////.o. V '\. IRP Output 2 IOFF } Valid OutputN lRAC Din HISh-Z WM :Don't care 0129-10 @HITACHI 864 Hitachi America, Ltd.• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300 HB56D51236 Series • Fast Page Mode Early Write Cycle tRASC Address Dout High-Z Din ~ : Don't care 0129-11 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 865 HB56D136B Series 1,048,576-Word x 36-Bit High Density Dynamic RAM Module • DESCRIPTION • PIN OUT The HB56D136B is a 1M x 36 dynamic RAM module, mounted 8 pieces of 4 Mbit DRAM (HM514400JP) sealed in SOJ package and 4 pieces of 1 Mbit DRAM (HM511000AJP) sealed in SOJ package. An outline of the HB56D136B is 72-pin single in-line package. Therefore, the HB56D136B makes high density mounting possible without surface mount technology. The HB56D136B provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ. • FEATURES • 72-pin Single In-line Package Lead Pitch ................................ 1.27mm • Single 5V (±5%) Supply • High Speed Access Time ............ 80 ns/100 ns/120 ns (max) • Low Power Dissipation Active Mode ............. 5.25W/4.62W/3.99W (max) Standby Mode ...................... 126 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycle ........................... (16 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TIL Compatible • ORDERING INFORMATION Part No. Access Time HB56D136B-8 80ns HB56Dl36B-1O 100 ns HB56D 136B-12 Package 72-pin SIP Socket Type 120 ns • PRESENCE DETECT PIN OUT Pin No. Pin Name 67 HB56Dl36B 80ns lOOns 120ns PDI VSS VSS VSS 68 PD2 VSS VSS VSS 69 PD3 NC VSS NC 70 PD4 VSS VSS NC ~° 00----------:0°0 00----------:00 ----0 ----36 pm I , 1 pIn '37 pm 0133-1 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name I VSS 19 NC 37 DQ17 55 DQ12 2 DQo 20 DQ4 38 DQ35 56 DQ30 3 DQI8 21 DQ22 39 VSS 57 DQ13 4 DQI 22 DQ5 40 CASo 58 DQ31 5 DQI9 23 DQ23 41 CAS2 59 Vee 6 DQ2 24 DQ6 42 CAS3 60 DQ32 7 DQ20 25 DQ24 43 CAS I 61 DQI4 8 DQ3 26 DQ7 44 RASo 62 DQ33 9 DQ21 27 DQ25 45 NC 63 DQI5 10 Vee 28 A7 46 NC 64 DQ34 11 NC 29 NC 47 WE 65 DQI6 12 AO 30 Vee 48 NC 66 NC 13 Al 31 A8 49 DQ9 67 PDI 14 A2 32 A9 50 DQ27 68 PD2 15 A3 33 NC 51 DQIO 69 PD3 16 A4 34 RAS2 52 DQ28 70 PD4 17 A5 35 DQ26 53 DQl1 71 NC 18 A6 36 DQ8 54 DQ29 72 VSS • PIN DESCRIPTION Pin Name Ao- A9 Ao- A9 Function Address Input Refresh Address Input DQo-DQ35 Data-in/Data-out CASO-CAS3 Column Address Strobe RASo,RAS2 Row Address Strobe WE ReadIWrite Enable Vee Power Supply ( + 5V) Vss Ground PDI-PD4 Presence Detect Pin NC Non-Connection ~HITACHI 866 I 72 pin , Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HB56D136B Series • BLOCK DIAGRAM RASO CASO I 000 001 002 003 VOl CAS RAS V02 V03 V04 ~OE 00 ?; VOl CAS RAS 004 005 006 007 V02 V03 ~~ 02 OE ?; 008 CASl 0010 009 0011 0012 I CAS RAS :========~:~~:'W:~~~MO~~~ ~~~~~~[!~~~~ 04 0013 0014 0015 0016 RAS D6 0017 ••--------~~~~~~ RAS2::==========~1 CAS2 0018§~ 0019 0020 0021 01 0022 0023 0024 0025 03 0026 RAS . Din/oo.( M2 CAS3 0027 0028 0029 0030 VOl CAS RAS V02 V03 V04 ~OE 05 ~ 0031 0032 0033 0034 VOl CAS RAS V02 V03 V04 ~OE ?; 0035 • I 07 CAS RAS Din/w M3 AO-A9 ••- - - - - - . 00-07, MO-M3 00-07, MO-M3 W£ '00-07 . HM514400JP Vee =CO-Cll' 00-07, MO-M3 MO-M3 . HM511000JP Vss = • 00-07, MO-M3 0133-2 ~HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 867 HB56D136B Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • PHYSICAL OUTLINE Un~: ::: A 107.95 4.25 101.19 3.984 2-0~ 5.28 max. 0.208 DDD DDDDDDD 6.35 025 44.45 1.75 44.45 1.75 0133-3 Detail B Detail A BOn, l00na 12On1 f1'I 2.54 min. 0.100 f1.07 max. 0.042 ::-:::±:0.25 max. . r 0.010 0133-4 Note: The plating of the contact finger is gold. ~HITACHI 868 Hitachi America, Ltd. • Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 0133-5 HB56D136B Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit (Input) Yin -\.Oto +7.0 V (Output) Vout -\.Oto +7.0 V Supply Voltage Relative to Vss VCC -\.Oto +7.0 V Short Circuit Output Current lout 50 mA Power Dissipation PT Voltage on Any Pin Relative to V88 I I Operating Temperature Storage Temperature 12 W Topr Oto +70 ·C T stg - 55 to + 125 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter Symbol Supply Voltage Note: = 0 to + 70'C) Min Typ Max Unit Vss 0 0 0 V Note Vcc 4.75 5.0 5.25 V I Input High Voltage V!H 2.4 5.5 V 1 Input Low Voltage VIL -\.O - 0.8 V I \. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to +70'C, Vee = 5V ±5%, Vss = OV) Parameter Operating Current Standby Current Symbol ICC! HB56D136B-8 HB56D 136B-1O HB56D136B-12 Min Min Min - Max 1000 - Max 880 - Max 760 Unit Test Conditions mA tRC = Min - 24 - 24 - 24 mA TTL Interface RAS, CAS = V!H, D out = High-Z - 12 - 12 - 12 mA CMOS Interface RAS, CAS ~ Vcc - 0.2V, D out = High-Z ICC2 RASOnly Refresh Current ICC3 - 960 - 840 - 740 mA tRC = Standby Current ICC5 - 60 - 60 - 60 mA RAS CAS D out = = = CAS Before RAS Refresh Current ICC6 - 960 - 840 - 720 mA tRC = Min - 920 - = Min Min V!H, VIL, Enable Page Mode Current ICC7 720 mA tpc ILl -10 10 -10 840 Input Leakage Current 10 -10 10 p.A OV S Yin S 7V Output Leakage Current ILO -10 10 -10 10 -10 10 p.A OV S Vout S 7V, Dout = Disable Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High lout Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 V Low lout Notes: Note 1,2 2 I 1,3 = - 5 mA = 4.2 mA I. ICC depends on output load condition when the device is selected. Icc max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 869 HB56D136B Series • Capacitance (TA = 25°C. Vee = 5V ±5%) Parameter Symbol Typ Input Capacitance (Address) CII Input Capacitance (WE) CI2 Input Capacitance (RAS) CI3 Input Capacitance (CAS) CI4 Output Capacitance (DQo-7. ~-16. DQI8-25. DQ27-34) CliO! - Output Capacitance (DQ8. 17. 26. 35) Notes: CII02 Max Unit Note 88 pF I 104 pF I 57 pF I 36 pF 1 17 pF 1.2 22 pF 1.2 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D oul ' • AC Characteristics (TA = 0 to +70"C. Vee = 5V ±5%. Vss = OV)l. 12 Read, Write and Refresh Cycle (Common Parameters) Parameter Symbol HB56D136B-8 Min Max - HB56D136B-1O HB56D136B-12 Min Max Min Max 190 - 220 - Unit Random Read or Write Cycle Time tRC 160 RAS Precharge Time tRP 70 RAS Pulse Width tRAS 80 10000 100 10000 120 10000 ns CAS Pulse Width tCAS 25 10000 25 10000 30 10000 ns Row Address Setup Time tASR 0 Row Address Hold Time tRAH Column Address Setup Time 80 90 Note ns ns 0 - 0 - ns 12 - 15 15 - ns tASC 0 - 0 0 - ns Column Address Hold Time tCAH 20 - 20 - 25 - ns RAS to CAS Delay Time tRCD 22 55 25 75 25 90 ns 8 RAS to Column Address Delay Time tRAD 17 45 20 55 20 65 ns 9 ns RAS Hold Time tRSH 25 - 30 tCSH 80 - 25 CAS Hold Time 100 - 120 CAS to RAS Precharge Time tCRP 10 - 10 - 10 - Transition Time (Rise and Fall) tT 3 50 3 50 3 50 ns 7 Refresh Period tREF - 16 - 16 - 16 ms 15 Unit Note ns ns Read Cycle Parameter Symbol HB56D136B-8 Min HB56D136B-1O HB56D136B-12 Max Min Max Min 80 - 100 - 120 ns 2.3 30 ns 3.4 55 ns 3.5 0 0 ns 10 - Max Access Time from RAS tRAC Access Time from CAS Access Time from Address !cAC tAA - Read Command Setup Time tRCS 0 Read Command Hold Time to CAS tRCH 0 - Read Command Hold Time to RAS tRRH 10 - 10 - Column Address to RAS Lead Time tRAL 40 - 45 - 55 - ns Output Buffer Turn-off Time laFF 0 20 0 25 0 30 ns 25 40 0 25 45 0 eHITACHI 870 Hitachi America. Ltd. 0 Hitachi Plaza 02000 Sierra Point Pkwy. 0 Brisbane, CA 94005-1819 0 (415) 589-8300 ns ns 6 HB56D136B Series Write Cycle Parameter Symbol HB56D136B-8 Min HB56D136B-1O Max Write Command Setup Time twcs 0 - 0 Write Command Hold Time tWCH 20 - 25 HB56D136B-12 Max Min Write Command Pulse Width twp 15 tDS 0 - 20 Data-in Setup Time 0 - Data-in Hold Time tDH 20 - 20 - Min Max - 0 30 25 0 25 Unit Note ns 10 ns ns ns 11 ns 11 Refresh Cycle Parameter Symbol HB56D136B-8 Min Max HB56D136B-1O HB56D136B-I2 Min Max Min Max Unit CAS Setup Time (CAS Before RAS Refresh Cycle) lcsR 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tcHR 20 - 20 - 25 - ns RAS Precharge to CAS Hold Time tRPC 15 - 15 - 15 - ns Note Fast Page Mode Cycle Parameter Symbol HB56D136B-1O HB56D136B-12 Min HB56D136B-8 Max Min Min Max - 55 - 65 10 - 20 - 100 100000 120 Max Fast Page Mode Cycle Time tpc 55 Fast Page Mode CAS Precharge Time tcp 10 Fast Page Mode RAS Pulse Width tRASC 80 Access Time from CAS Precharge tACP - 50 - 50 RAS Hold Time from CAS Precharge tRHCP 50 - 50 - Notes: 100000 Unit Note ns ns 100000 ns 13 - 60 ns 14 60 - ns 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD :S tRCD (max) and tRAD :S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD ~ tRCD (max) and tRAD :S tRAD (max). 5. Assumes that tRCD :S tRcD (max) and tRAD ~ tRAD (max). 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 10. Early write cycle only (twcs ~ twcs (min». II. These parameters are referenced to CAS leading edge in an early write cycle. 12. An inittal pause of 100 I-'s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh). 13. tRASC defines RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or !cAc or tACP. 15. tREF is 1,024 refresh cycles. eHITACHI Hitachi America, Ltd.• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 871 HB56D136B Series • TIMING WAVEFORMS • Read Cycle Address Dout Din ~:Don'I'" 0133-6 • Early Write Cycle Address Dout Din ~ :Don'I .... 0133-7 • 872 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HB56D136B Series • RAS Only Refresh Cycle Address Dout 2 ~ . Don'lcate 0133-B • CAS Before RAS Refresh Cycle tRP 1 Address, DIn: Don't care 2 IloUI:~gh-Z 3 ~ :Don'tcare • WE .VII 0133-9 @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 873 HB56D136B Series • Fast Page Mode Read Cycle IAASC Address Dout Din Hlgh-Z ~:Don'_ 0133-10 • Fast Page Mode Early Write Cycle Dout Din HIa!>Z 0133-11 ~HITACHI 874 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56D136B/S Series - - - - - - - - - 1,048,57S·Word x 3S·Bit High Density Dynamic RAM Module • DESCRIPTION • PIN OUT The HB56D136B/SB/BRISBR/BS/SBS is a 1M x 36 dynamic RAM module, mounted S pieces of 4 Mbit DRAM (HM514400JP/AJ) sealed in SOJ package and 4 pieces of 1 Mbit DRAM (HM511000JP) sealed in SOJ package (HB56D136B/SB/BRISBR) or 4 pieces of 1 Mbit DRAM (HM511000ATS) sealed in TSOP package (HB56D136SBI SBS). An outline of the HB56D136B/SB/BRISBR/BS/SBS is 72-pin single in-line package. Therefore, the HB56D136BI SB/BRISBR/BS/SBS makes high density mounting possible without surface mount technology. The HB56D136B/SBI BRISBR/BS/SBS provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ or beside each TSOP but only on the one side of its module board. ,-------------------------------, ~~[ 7 1 pm :.: : :: : : :: : :]D " DC::::::::::]; ! I ! 36 pin 37 pin ';'2 pm 0157-1 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name I VSS 19 NC 37 DQ17 55 DQ12 • FEATURES 2 DQo 20 DQ4 3S DQ35 56 DQ30 • 72-pin Single In-line Package Lead Pitch ............................... 1.27 mm • Single 5V (±5%) Supply • High Speed Access Time ....... 60 ns/70 ns/SO ns/100 ns (max) • Low Power Dissipation Active Mode ..... . 6.51W/5.SSW/5.25W/4.62W (max) Standby Mode ...................... 126 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycle ........................... (16 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TTL Compatible 3 DQIS 21 DQ22 39 VSS 57 DQJ3 4 DQI 22 DQ5 40 CASO 5S DQ31 5 DQI9 23 DQ23 41 CAS2 59 Vee 6 DQ2 24 DQ6 42 CAS3 60 DQ32 7 DQ20 25 DQ24 43 CASI 61 DQI4 S DQ3 26 DQ7 44 RASO 62 DQ33 9 DQl9 27 DQ25 45 NC 63 DQI5 10 Vee 2S A7 46 NC 64 DQ34 11 NC 29 NC 47 WE 65 DQl6 • ORDERING INFORMATION Access Time Part No. HB56DI36B/BR/BS-6A 60ns HB56D136B/BRlBS-7 A 70ns HB56D 136B/BR/BS-SA SOns HB56D136B/BR/BS-IOA lOOns Package 72-pin SIP Socket Type Contact Pad Gold 12 Ao 30 Vee 4S NC 66 NC 13 Al 31 As 49 DQ9 67 PDI PD2 14 A2 32 A9 50 DQ27 6S 15 A3 33 NC 51 DQIO 69 PD3 16 A4 34 RAS2 52 DQ2S 70 PD4 17 A5 35 DQ26 53 DQIl 71 NC IS A6 36 DQs 54 DQ29 72 VSS • PIN DESCRIPTION HB56DI36B/BR-S SOns HB56DI36B/BR-1O lOOns Ao- A9 Address Input Refresh Address Input Pin Name Function HB56DI36SB/SBRISBS-6A 60ns Ao-A9 HB56D I 36SB/SBR/SBS-7A 70ns DQo-DQ35 Data-inlData-out HB56DI36SB/SBR/SBS-SA SOns CASO-CAS3 Column Address Strobe HB56D 136SB/SBR/SBS-IOA lOOns 72-pin SIP Socket Type Solder RASO-RAS3 Row Address Strobe HB56DI36SB/SBR-S SOns WE Read/Write Enable HB56D I 36SB/SBR-1O lOOns Vee Power Supply ( + 5V) • PRESENCE DETECT PINOUT Pin Pin No. Name HB56DI36B/SB/BR/SBR/BS/SBS -6A -7A -SA -lOA -S I VSS Ground PDI-PD4 Presence Detect Pin NC No Connection -10 67 PDI VSS VSS VSS VSS VSS VSS 6S PD2 VSS VSS VSS VSS VSS VSS 69 PD3 NC VSS NC VSS NC VSS 70 PD4 NC NC VSS VSS VSS VSS ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 875 HB56D136B/S Series • BLOCK DIAGRAM Bm CASO I 1101 CAS RAS 1102 1103 DO 1104 000 DOl 002 003 ~OE 004 005 006 007 1101 CAS RAS 1102 1103 02 !!Q9 OE ,.r;:- W (AS • 008 em • 009 • 0010 • 0011 • 0012 • RAS lOin/out MO ] ] i 1 11/01 CAS RAS 11/02 11103 04 OE ~!!Q9 /;-1'% 00 I 3:====:j 110 1 CAS gg~;: I:~; 0016' RAS 06 1"04 r-I OE ~ ~--~----~ I CAS RAS 0017 ...-------1o'n/out Ml RASi I CAS2 0018 0019 0020 0021 1101 CAS RAS 1102 01 1103 1104 ~OE / '/ 0022 0023 0024 0025 1101 CAS RAS 1102 03 1103 !!Q9 di /-~ OE (AS RAS O,nlout M2 0026 em I 1101 CAS RAS 1102 1103 05 1104 0027 0028 0029 0030 di ~ 0031 0032 DOH 0034 ..c- w. OE 1101 CAS RAS 1102 1/03 07 1/04 OE CAS DO-D7: HM51400JP/AJ MO-M3: HM511000JP/ATS RAS O,nlout M3 0035 AO-A9 ...------c~~00-07. MO-M3 ~ 00-07. MO-M3 WE • Vee ••---------_~ 00-07. MO-M3 =CO-C11 • . ~ 00-07. MO-M3 Vss 0157-2 $HITACHI 876 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56D136B/S Series • mm Unit:-.Inch PHYSICAL OUTLINE • HB56D136B/SB ~07.9S ~.2S ~O1.19 I _ 1< 3.984 A I 5.28 max 0.208 ;i' ! CIl,,,, ",N ;;;1"': ! 11\ II I , ,I' -II ,t,-f-'I ..,.10",10 1.27 typ 0.05 VlI_ -,-.::r ",ioolo I -I 13 0157-3 -Detail A 60ns 70ns J J [U:Q) l~~ [D:Q) ,I J [D:Q) [Q]) ltrro II I lOOns 80ns II [Q]) [Q]) l~ J [Q]) [O]J l~ i Detail B i.-In· ~I o 100 Y I I ! L.-.I--Y..~ ~-r0o,o 1 :,1m!l • .,J I,.. I 0041 the specification of the contact pads. I Note: Following Contact Pad Part No. . HB56D136B-XX Gold HB56D136SB-XX Solder 0157-4 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 877 HB56D136B/S Series • PHYSICAL OUTLINE Unit: .mmh Inc • HB56D136BRISBR 107.95 4.25 r :1 ~-----_.l.-'IO"-!.1"9 _ _ _ _ _ _- - - ' ; : ; ),,(O.20min III 3.98 A 9.30max 0.008 0.366 .~ I'" .... CD N ... "":0 +0.10 I. 2 7 -0.0 II 0~05+' . -0.003 .14.45 1.75 B 0157-5 Detail A 60ns I 70ns fs8l fs8l 80ns lOOns lil lil Detail B Note: Following the specification of the contact pads. Part No. Contact Pad HB56D136BR-XX Gold HB56D136SBR-XX Solder ~HITACHI 878 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 0157-6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56D136B/S Series mm Unit:inch • PHYSICAL OUTLINE • HB56D136BS/SBS A 1 795 ..i. 5.28 max 0.208 10119 3.984 ,f; 10 ' i 1.75 =§ §§ §§ 13= §§ §§ §§ 13 !::ie !::ie 1=1; l=Ie be !::ie CI e 1° Ill! 'R 5e !!I::I !::ill ! Iit!! 88 liS 88 .... -' 8= 88 --' !!8 =::1 ::Ie s= 8; ~~ 88 83 !lI ES E33 83 8m 0 m !:! II !! 0157-7 Detail A 60ns 70n5 lOOns 80ns r r r r ~~~~ [J] ([]] ([]] a:Il ~!d~!d ~~!d!d 0000000000 0000000000 0000000000 [J] [J] [J] [J] ~!d~~ ! I 0000000000 Detail B ...-~ :ktt y~ 154MI". ~ I -":-0.010 , 7",.. 0.042 Note: Following the specification of the contact pads. t Part No. Contact Pad HB56D136BS·XX Gold HB56D136SBS·XX Solder 0157-8 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 879 HB56D136B/S Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit (Input) Yin -1.0to +7.0 V (Output) Vout -1.0to + 7.0 V Supply Voltage Relative to Vss VCC -1.0to +7.0 V Short Circuit Output Current lout 50 rnA Power Dissipation PT I I Voltage on Any Pin Relative to Vss Operating Temperature Topr Tstg Storage Temperature • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter Symbol Supply Voltage = 8 W Oto + 70 ·C - 55 to + 125 ·C 0 to + 70°C) Min Typ Max Unit Vss 0 0 0 V Note Vcc 4.75 5.0 5.25 V 1 Input High Voltage VIR 2.4 5.5 V 1 Input Low Voltage VIL -1.0 - 0.8 V 1 Note: I. All voltage referenced to Vss. • DC Electrical Characteristics (TA = 0 to + 70°C, Vee = 5V ± 5%, Vss = OV) HB56DI36B/SB/BR/SBR/BS/SBS Parameter -6A Symbol -7A -8A -lOA -8 -10 Unit Test Conditions Note Min Max Min Max Min Max Min Max Min Max Min Max Operating Current ICC! 1240 - 1120 - - 1000 - 880 - 1000 880 - rnA tRC = Min 1,2 TTL Interface rnA RAS, CAS = VIR Dout = High-Z CMOS Interface rnA RAS, CAS ~ Vcc - 0.2V Dout = High-Z - 24 - 24 - 24 - 24 - 24 - 24 - 12 - 12 - 12 - 12 - 12 - 12 RASOnly Refresh Current ICC3 - 1240 - 1120 - 960 - 840 - 960 - 840 rnA tRC = Min 2 Standby Current ICC5 - 60 - 60 - 60 - 60 - 60 - 60 RAS = VIR rnA CAS = VIL Dout = Enable 1 CAS Before RAS Refresh Current ICC6 - 1200 - 1080 - 960 - 840 - 960 - 840 rnA tRC = Min Page Mode Current ICC7 - 1200 - 1080 - 920 - 840 - 920 - 840 rnA tpc = Min Input Leakage Current ILl Standby Current ICC2 -10 10 -10 10 -10 10 -10 10 -10 10 -10 10 /LA OV:S Vin:S 7V Output Leakage ILO Current -10 10 -10 10 -10 10 -10 10 -10 10 -10 10 OV :S Vout :S 7V /LA D out = Disable Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V High lout = - 5 rnA Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 rnA Notes: I. ICC depends on outpnt load condition when the device is selected, IcC max is specified at the output open condition. 2. Address can be changed less than three times while RAS = VIL. 3. Address can be changed :S 1 time while CAS = VIH' .HITACHI 880 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 1,3 HB56D136B/S Series • Capacitance (TA = 25'C, Vee = 5V ±5%) Symbol Typ Max Unit Note Input Capacitance (Address) CII - SS pF I Input Capacitance (WE) CI2 104 pF I 57 pF I 36 pF I Parameter Input Capacitance (RAS) Cn Input Capacitance (CAS) CI4 - Output Capacitance (DQo-DQ7, 9-16,18-25,27-34) CliO! - 17 pF 1,2 Output Capacitance (DQ8, 17, 26, 35) CII02 - 22 pF 1,2 Notes: I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIR to disable D ont ' • AC Electrical Characteristics (TA = 0 to 70'C, Vee = 5V ±5%, Vss Read, Write and Refresh Cycle (Common Parameters) OV)1, 12 = HB56DI36B/SB/BRlSBRIBS/SBS Parameter -6A Symbol Min -7A Max -lOA -SA Min Max Min Max Min 130 - 160 - 190 - 70 -S Max -10 Unit Min Max Min Max - 160 - 190 - ns - 70 - ns Note Random Read or Write Cycle Time tRC RAS Precharge Time tRP 50 RAS Pulse Width tRAS 60 10000 70 10000 SO 10000 100 10000 SO 10000 100 10000 ns CAS Pulse Width tCAS 20 10000 20 10000 25 10000 25 10000 25 10000 25 10000 ns Row Address Setup Time tASR 0 - 0 0 - ns Row Address Hold Time tRAH 10 - 15 ns Column Address Setup Time tASC 0 0 - Column Address Hold Time tCAH 20 - ns RAS to CAS Delay Time tRCD 75 ns S RAS to Column Address Delay Time 9 120 - - 50 - SO - SO 0 - 0 - 0 10 - 12 - 15 12 - 0 - 0 - 0 15 - 15 - 20 - 20 - 20 - 20 40 20 50 22 55 25 75 22 55 25 0 ns tRAD 15 30 15 35 17 40 20 55 17 40 20 55 ns RAS Hold Time tRSH 20 - 25 - 25 - 25 - ns tCSH 60 70 - SO 100 - SO - 100 - ns CAS to RAS Precharge Time !cRP 10 10 - 10 - 25 CAS Hold Time - 20 10 - 10 - 10 - ns Transition Time (Rise and Fall) tT 3 50 3 50 3 50 3 50 3 50 3 50 ns 7 Refresh Period tREF - 16 - 16 - 16 - 16 - 16 - 16 ms 15 Min Read Cycle HB56DI36B/SB/BRISBR/BS/SBS Parameter -6A Symbol Min -7A Max Min -SA Max Min -lOA Max -S -10 Unit Note Min Max Min Max Max SO - 100 ns 2,3 25 - 25 ns 3,4 3,5 Access Time from RAS tRAC - 60 - 70 - SO - 100 Access Time from CAS - 20 - 20 - 25 - - 30 - 35 - 40 - 25 Access Time from Address !cAC tAA 45 - 40 - 45 ns Read Command Setup Time tRCS 0 - 0 - 0 - 0 - 0 - 0 - ns Read Command Hold Time to CAS tRCH 0 - 0 - 0 - 0 - 0 - 0 - ns Read Command Hold Time to RAS tRRH 10 - 10 - 10 - 10 - 10 - 10 - ns Column Address to RAS Lead Time tRAL 30 - 35 - 40 - 55 - 40 - 55 - ns Output Buffer Turn-off Time IoFF - 20 - 20 - 20 - 25 - 20 - 25 ns 6 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 881 HB56D136B/S Series Write Cycle HB56DI36B/SB/BR/SBR/BS/SBS -6A Symbol Parameter -7A Min Max Write Command PoIse Width twp 10 Data-in Setup Time tDS 0 - Data-in Hold Time tDH 15 - Write Command Setup Time twcs 0 Write Command Hold Time tWCH 15 -SA Min Max 0 0 - 15 - 15 10 Min -S -lOA Max Min Max -10 Max Min Min Max Unit Note 10 0 - 0 - 0 - 0 20 - 20 - 20 20 - 15 - 20 - ns 0 - - ns 20 0 0 11 20 - ns - - 0 20 - ns 11 15 20 20 ns Refresh Cycle HB56DI36B/SB/BR/SBR/BS/SBS Parameter -6A Symbol -7A Min Max Min -SA Max Min -S -lOA Max Min Max Min -10 Max Min Unit Note Max CAS Setup Time (CAS Before RAS Refresh Cycle) !eSR 10 - 10 - 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) !eHR 15 - 15 - 20 - 20 - 20 - 20 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - 10 - 10 - ns Fast Page Mode Cycle HB56DI36B/SB/BR/SBR/BS/SBS Parameter -6A Symbol Min -7A Max -SA -S -lOA Min Max Min Max Min Max Min -10 Max Min Unit Note Max Fast Page Mode Cycle Time tpc 45 - 50 - 55 - 55 - 55 - 55 - ns Fast Page Mode CAS Precharge Time !ep 10 - 10 - 10 - 10 - 10 - 10 - ns Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 - 100000 - 100000 - 100000 - 100000 ns 13 Access Time from CAS Precharge tACP - 40 - 45 - 50 - 50 - 50 - 50 ns 14 RAS Hold Time from CAS Precharge tRHCP 40 - 45 - 50 - 50 - 50 - 50 - ns Notes: 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD oS tRCD (max) and tRAD oS tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD Z 3 ~ : Don'ICile • \'ill.VIH 0134-9 • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 895 HB56D236B Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read Cycle IMIC Address Dout w.a Din :Don'I_ 0134-10 • Fast Page Mode Early WrIte Cycle Address Dout Din ~:Don'I'" 0134-11 $HITACHI 896 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HB56D236B/SB Series - - - - - - - - - 2,097,152-Word x 3S·Bit High Density Dynamic RAM Module • PIN OUT • DESCRIPTION The HB56D236B/SB/BS/SBS is a 2M x 36 dynamic RAM module, mounted 16 pieces of 4 Mbit DRAM (HM514400JP/AJ) sealed in SOJ package and 8 pieces of 1 Mbit DRAM (HM511000JP) sealed in SOJ package (HB56D236B/SB or 8 pieces of 1 Mbit DRAM (HM511000ATS) sealed in TSOP package (HB56D236SBI SBS). An outline of the HB56D236B/SB/BS/SBS is 72-pin single in-line package. Therefore, the HB56D236B/SB/BSI SBS makes high density mounting possible without surface mount technology. The HB56D236B/SB/BS/SBS provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ or beside each TSOP but only on the one side of Its module board. • FEATURES • 72-pin Single In-line Package Lead Pitch ............................... 1.27 mm • Single 5V (±5%) Supply • High Speed Access Time ....... 60 ns170 ns/80 ns/100 ns (max) • Low Power Dissipation Active Mode . 6.825W 16.195W15.565W I 4.935W (max) Standby Mode ...................... 252 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycle ........................... (16 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TIL Compatible • ORDI:RING INFORMATION Part No. Access Time HB56Ol36B/BS-6A 60ns HB56Ol36B/BS-7 A 70ns HB56Ol36B/BS-8A 80ns HB56D236B/BS-IOA 100 ns HB56D236B-8 80 ns HB56D236B-1O lOOns HB56Ol36SB/SBS-6A 60ns HB56D236SB/SBS-7 A --_. 70 ns HB56Ol36SB/SBS-8A 80 ns H~: ~D236SB/SBS-IOA lOOns HB56Ol36SB-8 80 ns HB56Ol36SB-1O 100 us Package Contact Pad 72-pin SIP Socket Type Gold ~ °0['_'_'_'_'_ --'-'-'-'-']0 _.- - - - -.-.- _.- - 7 0 U[·_·_·- -'-'-'-'-'- _·]°0 - - - - _.- - - - - -. ! 37pin ! 1 pin ! 36pin I 72 pin 0158-1 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name DQ12 1 VSS 19 NC 37 DQ17 55 2 DQo 20 DQ4 38 DQ3S 56 DQ30 3 DQlS 21 DQ22 39 57 DQ13 4 DQl 22 DQs 40 VSS CASO 58 DQ31 5 DQ19 23 DQ23 41 CAS2 59 Vee 6 DQ2 24 DQ6 42 CAS3 60 DQ32 DQ14 7 DQ20 25 DQ24 43 CASI 61 8 DQ3 26 DQ7 44 RASO 62 DQ33 9 DQ21 27 DQ25 45 RASI 63 DQIS 10 Vee NC 28 NC 64 DQ34 29 A7 NC 46 11 47 WE 65 DQ16 12 Ao 30 Vee 48 NC 66 NC 13 Al 31 As 49 DQ9 67 PD1 14 A2 32 A9 50 DQ27 68 POl 15 A3 33 RAS3 51 DQIO 69 PD3 16 ~ 34 RAS2 52 DQ2S 70 PD4 17 As 35 DQ26 53 DQll 71 NC 18 A6 36 DQs 54 DQ29 72 VSS • PIN DESCRIPTION Pin Name Ao- A9 Ao- A9 72-pin SIP Socket Type Solder • PRESENCE DETECT PINOUT HB56Ol36B/SB/BS/SBS Pin No. Pin Name -6A -7A -8A -lOA -8 -10 67 PDl NC NC NC NC NC NC 68 PD2 NC NC NC NC NC NC 69 PD3 NC NC Vss NC VSS 70 PD4 NC VSS NC VSS VSS VSS VSS Function Address Input Refresh Address Input DQo-DQ3S Data-iuIData-out CASO-CAS3 Column Address Strobe RASO-RAS3 Row Address Strobe WE ReadIWrite Enable Vee Power Supply ( + 5V) VSS Ground PDI-PD4 Presence Detect Pin NC No Connection ~HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 897 HB56D236B/SB Series • BLOCK DIAGRAM RASO CASO 000 001 002 003 1101 CAS RAS 1102 1103 DO 1/04 £""OE ~ ~ 004 DOS 006 007 1101 RAS CAS 1102 1103 01 c¥?4 *OE 1/01 CAS RAS 1102 1103 03 !!Q!I 1/01 RAS CAS 1/02 1/03 02 !!Q!I ~OE £OE % 008 CAS RAS Din/out MO RAS CAS Din/out Ml 1/01 CAS 1102 1101 RAS CAS 1/02 1103 05 1&4 CAS 1 009 0010 0011 0012 1103 RAS 04 !!Q!I ~OE £OE , '/ DOll 0014 0015 0016 % 1101 CAS 1102 1103 RAS 1101 RAS 1102 1103 07 1104 1104 ~OE *OE ~ 0017 CAS 06 CAS RAS Din/out M2 RAS CAS Din/out M3 1101 CAS RAS 1102 1103 08 1101 RAS CAS 1102 1103 09 1104 OE RAS2 CAS2 0018 0019 0020 0021 !!Q!I -ii" ~OE ~ 0022 0023 0024 0025 1101 CAS RAS 1102 1103 011 !il!..4 ~OE 1101 RAS 1102 1103 !il!..4 ~OE ~ % 0026 CAS 010 CAS RAS Din/out M4 RAS CAS Din/out MS 1101 CAS RAS 1102 1103 012 1104 1101 RAS CAS3 0027 0028 0029 0030 ~OE 1104 £"" OE 1101 CAS 1102 1103 £"" RAS 1101 RAS CAS 1102 1103 014 1104 015 1104 OE £"OE CAS RAS Din/out M6 0035 013 ~ % 0031 0032 DOll 0034 CAS 1102 1103 RAS CAS Din/out M7 AO - A9 ••---~~DO - 015. MO - M7 WE • Vee • Vss • .DO-D1S.MO-M7 OJ: .00-D15.MO-M7 TCO-Cll ~ 00-015. MO-M7 0158-2 'DO-DI5: HM514400JP/AJ MO-M7: HM511000JP/ATS ~HITACHI 898 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56D236B/SB Series • mm Unit:inch PHYSICAL OUTLINE • HB56D236B/SB 107.95 4.25 101.19 3.984 9.144max 0.36 i 2-¢~\ =000000= ~ jI.h R 1 57 ~RO:062~~D~~D 1- IL' IJ'I,~. "'I' 03 <00 2 --..:- - - 0.08 6.35 0.25" II (~~) t l'f'~'" I"", III: IIIlIItll.!!....... 1.27 / 0.05 6.35 R-1-.57 " , O. 25 -----i' RO.062 44.45 1.75 /' "" ~_'~ -,.-h ~\..' -I -,,-,,1.04 '1-0.041 44.45 , =f--+----"I I I"" '" 0 <0 0 IJ'I _ _ ",C;;C;;C;; - 1 27 typ, 0.05 " 1.75 I3 I o DDDDD 0156-3 Detail A 60ns ~-'=.V'~ 70ns ...... 000000000000 80ns lOOns ~__o . . . . 000000000000 000000000000 000000000000 Detail B :m 254Mln. 0T00 1 7m x 0042 :+ Note: Following the specification of the contact pads. 0.25ma,_ 0.010 Part No. Contact Pad HB56D236B-XX Gold HB56D236SB-XX Solder 0158-4 ~HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 899 HB56D236B/SB Series - - - - - - - - - - - - - - - - - - - - - - - - - - • mm Unit::--h Inc PHYSICAL OUTLINE (continued) • HB56D236BS/SBS A E(1"""<_ _ _ _ ...."...,,~'"""1_01-·~-~---1J.lW"...___------~ 9.30 max 0.366 ...;,J,~0.20min 1 ! '0 ~ c: EII'I "'" me """I U .27 "lY.OS R 1.57 1Ul.062 1. 2 7 t 0:05 0158-5 Detail A 60ns 70ns 80ns lOOns r r r r [[]] [[]] [[]] [[]] [[]] IIJJ [J] [J] bJbJ~~ bJbJbJ~ bJbJ~bJ bJbJbJbJ 0000000000 0000000000 0000000000 0000000000 Detail B :f 2.S4M:!ln. .. 0.100 107miu 0.042 Note: Following the specification of the contact pads. Q...ll!!!!!: 0010 Part No. Contact Pad HB56D236BS-XX Gold HB56D236SBS-XX Solder 0158-6 ~HITACHI 900 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HB56D236B/SB Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit (Input) Yin - \.0 to +7.0 V (Output) Vout - \.0 to +7.0 V Supply Voltage Relative to VSS VCC - \.0 to + 7.0 V Short Circuit Output Current lout 50 rnA I I Voltage on Any Pin Relative to Vss Power Dissipation PT 8 W Operating Temperature Topr Oto + 70 ·C Storage Temperature T stg -55to+125 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter Symbol Supply Voltage Note: 0 to + 70°C) = Min Typ Max Unit Vss 0 0 0 V Note Vcc 4.75 5.0 5.25 V I Input High Voltage VlH 2.4 - 5.5 V 1 Input Low Voltage VIL - \.0 - 0.8 V I 1. All voltage referenced to Vss. • DC Electrical Characteristics (TA = ± 0 to + 70°C, Vee = 5V 5%, Vss = OV) HB56D236B/SB/BS/SBS Parameter -6A Symbol Min Operating Current -7A Max Min -8A Max Min -8 -lOA Max Min Max Min -10 Max Min Unit Test Conditions = Min Note Max - 1300 - 1180 - 1060 - 940 - 1060 - 940 rnA tRC - 48 - 48 - 48 - 48 - 48 - 48 TTL Interface rnA RAS, CAS = VlH D out = High-Z - 24 - 24 - 24 - 24 - 24 - 24 CMOS Interface rnA RAS, CAS 2: VCC - 0.2V D out = High-Z RASOnly Refresh Current ICC3 - 1300 - 1180 - 1020 - 900 - 1020 - 900 rnA tRC 2 Standby Current Iccs - 120 - 120 - 120 - 120 - 120 - 120 rnA I CAS Before RAS Refresh Current ICC6 - 1260 - 1140 - 1020 - 900 - 1020 - 900 rnA tRC = Min Page Mode Current ICC7 - 1260 - 1140 - 980 - 900 - 980 - 900 rnA tpc = Min Input Leakage Current ILl Standby Current ICC! ICC2 Output Leakage ILO Current = Min RAS = VlH CAS = VIL Dout = Enable 1,3 -10 10 -10 10 -10 10 -10 10 -10 10 -10 10 p.A OV oS Yin oS 7V -10 10 -10 10 -10 10 -10 10 -10 10 -10 10 p.A 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V High lout =- 0.4 0 0.4 0 0.4 0 0.4 V Low lout = 4.2 rnA Output High Voltage VOH 2.4 VCC 2.4 VCC Output Low Voltage VOL 0 0.4 0 0.4 Notes: 1,2 0 OV oS Yin oS 7V D out = Disable 5 rnA 1. ICC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed less than three times while RAS = V IL. 3. Address can be changed oS 1 time while CAS = VlH. ~HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 901 HB56D236B/SB Series • Capacitance (TA = 25'C, Vee = 5V ±5%) Max Unit Input Capacitance (Address) Parameter Symbol Cu - 161 pF I Input Capacitance (WE) CI2 - 193 pF 1 62 pF 1 29 pF 1,2 39 pF 1,2 Input Capacitance (RAS, CAS) Cn Output Capacitance (DQO-7, 9-16,18-25,27-34) CliO I Output Capacitance (DQ8, 17,26,35) CII02 Notes: Typ Note I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable D oU!' • AC Characteristics (TA = 0 to +70'C, Vee = 5V ±5%, Vss Read, Write and Refresh Cycle (Common Parameters) = OV)1, 12 HB56D236B/SB/BS/SBS Parameter -6A Symbol Min -7A Max -8A -lOA -8 Unit -10 Min Max Min Max Min Max Min Max Min - 130 - 160 - 190 - 160 - 190 - 50 Random Read or Write Cycle Time tRC 120 RAS Precharge Time (RP 50 RAS Pulse Width tRAS 60 10000 70 10000 80 10000 100 10000 80 10000 100 10000 ns CAS Pulse Width tCAS 20 10000 20 10000 25 10000 25 10000 25 10000 25 10000 ns Row Address Setup Time tASR a Row Address Hold Time tRAH 10 Column Address Setup Time tASC a Column Address Hold Time tCAH 15 - RAS to CAS Delay Time tRCD 20 RAS to Column Address Delay Time - a 15 - 40 20 10 a 70 - a - 70 80 ns - ns - a - a - ns 15 - 12 - 15 - ns a a 20 - ns 20 - a 20 - 55 25 75 22 55 25 75 ns 8 20 55 17 40 20 55 ns 9 20 50 22 a - - a - 12 80 Note Max ns tRAD 15 30 15 35 17 40 RAS Hold Time tRSH 20 - 20 - 25 - 25 - 25 60 70 - 80 - 100 80 - 100 CAS to RAS Precharge Time tCRP Transition Time tT (Rise and Fall) 10 - - ns tCSH - 25 CAS Hold Time 10 - 10 - 10 - 10 - 10 - ns 3 50 3 50 3 50 3 50 3 50 3 50 ns 7 Refresh Period - 16 16 - 16 16 ms 15 tREF - 16 - - 16 - ns Read Cycle HB56D236B/SB/BS/SBS Parameter -6A Symbol -7A -8A -lOA -8 -10 Unit Note 100 ns 2,3 25 ns 3,4 45 ns 3,5 - ns - ns Min Max Min Max Min Max Min Max Min Max Min Max - 60 - 70 - 80 - 100 - 80 25 25 - - Access Time from RAS tRAC Access Time from CAS tCAC Access Time from Address tAA Read Command Setup Time tRCS Read Command Hold Time to CAS tRCH a a Read Command Hold Time to RAS tRRH Column Address to RAS Lead Time Output Buffer Turn-off Time 20 30 - a a 10 - tRAL 30 tOFF - 20 35 40 25 45 - - a a - a a 10 - 10 - 10 - ns - 55 - 40 - 55 - ns 20 - 25 - 20 - 25 ns - - a a - - a a 10 - 10 - - 35 - 40 20 - 20 - - 40 .HITACHI 902 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy,. Brisbane, CA 94005-1819. (415) 589-8300 6 HB56D236B/SB Series Write Cycle HB56D236B/SB/BS/SBS Parameter -6A Symbol Min -SA -7A Min Max Write Command Setup Time twcs 0 - 0 Write Command Hold Time tWCR 15 - 15 Write Command Pulse Width twp 10 - 10 Data-in Setup Time tDS 0 0 Data-in Hold Time tDD 15 - Max Min - - 15 -lOA Max Min 0 - 0 - 0 20 - 20 - 20 15 - 20 - 0 - 15 0 20 20 -10 -S Min Max Max - 20 Note ns 10 0 - ns 11 20 - ns 11 Max 0 20 20 - 0 Unit Min ns ns Refresh Cycle HB56D236B/SB/BS/SBS Parameter -6A Symbol Min -SA -7A Max Min Max -lOA Min Max Min -10 -S Max Min Max Min Unit Note Max CAS Setup Time (CAS Before RAS Refresh Cycle) tcSR 10 - 10 - 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCRR 15 - 15 - 20 - 20 - 20 - 20 - ns RAS Precharge to CAS Hold Time tRPC 10 - 10 - 10 - 10 - 10 - 10 - ns Fast Page Mode Cycle HB56D236B/SB/BS/SBS Parameter -6A Symbol Min -7A Max Min -SA Max Min -lOA Max Min Max -10 -S Min Max Min Unit Note Max Fast Page Mode Cycle Time tpc 45 - 50 - 55 - 55 - 55 - 55 - ns Fast Page Mode CAS Precharge Time tcp 10 - 10 - 10 - 10 - 10 - 10 - ns Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 - 100000 - 100000 - 100000 - 100000 ns 13 Access Time from CAS Precharge tACP - 40 - 45 - 50 - 50 - 50 - 50 ns 14 RAS Hold Time from CAS Precharge tRHCP 40 - 45 - 50 - 50 - 50 - 50 - ns Notes: 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD S tRCD (max) and tRAD S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that tRCD l!: tRCD (max), tRAD S tRAD (max). 5. Assumes that tRCD S tRCD (max), tRAD l!: tRAD (max). 6. !oFF (max) is defined as the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIR (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIR and VIL' S. Operation with the tRcD (max) limit insures that tRAc (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point ouIy, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 10. Early write cycle only (twcs l!: twcs (min». 11. These parameters are referenced to CAS leading edge in an early write cycle. 12. An initial pause of 100 ,...S is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS clock such as RAS only refrersh). 13. tRASC is determined by RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tACP' 15. tREF is determined by 1,024 refresh cycles. • HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 903 HB56D236B/SB Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read Cycle tRC tT tRP Address We tCAC tOFF Valid Output Dout tRAC Din High-Z ~ : Don't care 0158-7 ~HITACHI 904 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HB56D236B/SB Series • Early Write Cycle tRC Address Dout Din High-Z ~ : Don't care 0158-8 @HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 905 HB56D236B/SB Series • RAS Only Refresh Cycle tRC Address High-Z Dout WE : Don't care 2 ~: Don't care 0158-9 • CAS Before RAS Refresh Cycle tRC LRP tCSR tCHR 1 Address, Din: Don't care 2 Dout: High-Z 3 ~: Don't care 4 WE: VIH 0158-10 ~HITACHI 906 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819· (415) 589-8300 HB56D236B/SB Series • Fast Page Mode Read Cycle tRASC tT tASR Address tOFF Dout I}----;:: 1 : Invalid output ~ : Don'tcare 0098-7 @HITACHI 918 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 HB56A140 Series • Read-Modify-Write Cycle tRWC CAS Address WE Din Dout OE * 1 : Invalid output ~ : Don't care 0098-8 ~HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 919 HB56A 140 Series • RAS Only Refresh Cycle tRC Address High-Z Dout 1 WE, OE : Don't care 2 ~: Don't care 3 REFRESH ADDRESS: AO - A9 (AXO-AX9) 0098-9 • CAS Before RAS Refresh Cycle tRC tRP tCRP Dout OPEN WE:VIH 2 ~ : Don't care 0098-10 ~HITACHI 920 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HB56A140 Series • Fast Page Mode Read Cycle tRASC CAS Address Din Dout tOAC ~ : Don't care 0098-11 $HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 921 HB56A140 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Early Write Cycle tRASC Address Din High-Z Dout ~ : Don't care OE : Don't care 0098-12 eHITACHI 922 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 HB56A140 Series • Fast Page Mode Delayed Write Cycle tRASC CAS Address Din tOEH Hi-Z Dout toDD ~ : Don't care 0098-13 @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 923 HB56A 140 Series • Fast Page Mode Read-Modify-Write Cycle tRASC tT tRP tACP CAS Address Din tDZO Hi-Z Dout ~ : Don't care 0098-14 .HITACHI 924 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HB56A140 Series • TEST MODE CYCLE *1, *3 *1 Note * 1 CBR or RAS-only refresh *2 ~:Don'tcare *3 Address, Din, OE : Don't care 0098-15 • (1) Test Mode Set Cycle tRC tRAS tCSR tws tCHR tWH OPEN Dout ~ : Don't care 0098-16 $ HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 925 HB56A140 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • (2) Test Mode Reset Cycle CAS Before RAS Refresh Cycle tRC tRC Dout OPEN ~ : Don't care 0098-17 RAS Only Refresh Cycle tRC tRAH Address Dout OPEN 2 Refresh Address AO - A9 (AXO-AX9) ~ : Don't care 0098-18 ~HITACHI 926 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HB56A240 Series 2,097,152·Word x 40·Bit High Density Dynamic RAM Module • DESCRIPTION • PINOUT The HB56A240B/SB is a 2M x 40 dynamic RAM module, mounted 20 pieces of 4 Mbit DRAM (HM514400AS) sealed in SOJ package. An outline of the HB56A240B/SB is a 72-pin single in-line package. Therefore, the HB56A240BI SB makes high density mounting possible without surface mount technology. The HB56A240B/SB provides common data inputs and outputs. Its module board has decoupling capaCitors beneath the each SOJ but only on the one side of its module board. r--------------------------------------, ~~[ f D[ ........ _....... ]°0 I " - -! ! ! _... _._ ... _._ .... ]0 - - . - - - _.- - . - 1 pin 36 pin . .. _... . .. 72pin 37 pin 0099-1 • FEATURES • 72-pin Single In-line Package Lead Pitch ................................ 1.27mm • Single 5V (±5%) Supply • High Speed Access Time ....... 60 ns170 ns/80 ns/100 ns (max) • Low Power Dissipation Operation ........... 6038 mW/5513 mW/4988 mWI 4463 mW (max) Standby ............................ 210 mW (max) • Fast Page Mode Capability • 1,024 Refresh Cycles .......................... (16 ms) • 2 Variations of Refresh RAS Only Refresh CAS Before RAS Refresh • TIL Compatible • ORDERING INFORMATION Part No. Access Time HB56A24OB-6A 60ns HB56A24OB-7A 70 ns HB56A24OB-8A 80ns HB56A24OB-IOA Package Contact Pad 72-pin SIP Socket Type Gold lOOns HB56A24OSB-6A 60ns HB56A24OSB-7 A 70ns HB56A240SB-8A 80ns HB56A240SB-IOA lOOns 72-pin SIP Socket Type Solder Pin No. Pin Name Function Address Input AO-A9 Ao-As Refresh Address Input DQo-DQ39 Data-in/Data-out CASO,CASI Column Address Strobe RASO,RASO Row Address Strobe WE Read/Write Enable OE Output Enable Voo Power Supply ( + 5V) Vss PDt-PD4 Ground Presence Detect Pin NC No Connection Pin Name Pin No. Pin Name Pin No. Pin Name I VSS 19 OE 37 DQ33 55 DQl1 2 DQo 20 DQ4 38 DQ3S 56 DQ27 3 DQI6 21 DQ20 39 57 DQ12 4 DQI 22 DQs 40 Vss NC 58 DQ2S 5 DQ17 23 DQ21 41 CASO 59 VOO 6 DQ2 24 DQ6 42 CASI 60 DQ29 7 DQIs 25 DQ22 43 NC 61 DQ13 8 DQ3 26 DQ7 44 RASO 62 DQ30 9 DQI9 27 DQ23 45 RASI 63 DQI4 10 28 A7 46 DQ37 64 DQ31 11 VDO NC 29 DQ36 47 WE 65 DQIs 12 AO 30 VDO 48 GND 66 13 Al 31 As 49 DQs 67 DQ3S PDt 14 A2 32 A9 50 DQ24 68 PD2 15 A3 33 NC 51 DQ9 69 PD3 16 A4 34 NC 52 DQ2S 70 PD4 17 As 35 DQ34 53 DQIO 71 DQ39 18 A6 36 DS36 54 DQ26 72 VSS • PRESENCE DETECT PINOUT HB56A240B/SB Pin No. Pin Name ·6A -7A -8A -lOA 67 PDl NC NC NC NC 68 PDZ NC NC NC NC 69 PD3 NC NC Vss 70 PD4 NC VSS NC Vss Vss • PIN DESCRIPTION Pin Name Pin No. ~HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 927 HB56A240 Series • BLOCK DIAGRAM B8ll ~ RASO CASO I r-r-r-- I I 000 0016 001 0017 1/01 CAS RAS 1/02 1/03 DO 1/04 002 0018 003 0019 1/01 CAS' RAS 1/02 1/03 01 1/04 004 0020 005 0021 1/01 CAS RAS 1/02 1/03 02 1/04 006 0022 007 0023 1101 CAS RAS 1/02 1103 03 1/04 -- 0036 0034 0032 0033 1/01 CAS RAS 1/02 1103 04 1/04 -- 0035 0037 008 0024 1/01 CAS RAS 1/02 1/03 05 1/04 I - 1/01 CAS I - 1/02 009 0025 0010 0026 1/01 CAS RAS 1/02 1/03 06 1/04 I - 1/01 CAS 0011 0027 0012 0028 1/01 CAS RAS 1102 1/03 07 1/04 1/01 CAS r-- 1/02 r-'-- 0029 0013 0030 0014 1/01 CAS RAS 1102 1/03 08 1/04 - 0031 0015 0038 0039 1101 CAS RAS 1/02 1/03 09 1/04 I- 1/01 CAS RAS 1/02 1/03 010 1/04 I - 1/01 CAS r-r-- I- r-- 1/02 1/03 1/04 RAS 011 1/01 CAS I - 1/02 RAS - 1/03 1/04 - 1/01 CAS RAS 1/02 013 1/03 1/04 - 1/01 CAS RAS 1/02 1103 014 1/04 ~ r - - 1/03 012 RAS 015 I - 1/04 r-- - - 1/03 1/04 016 r-r-- RAS 017 1101 lAS RAS 1/02 1/03 018 1104 I - 1101 CAS I-- RAS 1/02 I - 1/03 I - 1/04 1/02 1/03 1/04 RAS 019 AOtoA9 _--""~~00to019 • WE ---...,~~ • DO to 019 DE.---~~ Vee • Vss • ::L 00to019 :r CO-C9 .. DO to 019 ~ DO to 019 0099-2 * DO to D9: HM514400AS ~HITACHI 928 Hitachi America, Ltd,' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HB56A240 Series • mm Unit:inch PHYSICAL OUTLINE 0099-4 Detail A 60ns 70ns 80ns lOOns l~ 0099-5 Note: Followmg the speclfication of the contact pad. Part No. Contact Pad HB56A240B-XXA Gold HB56A240SB-XXA Solder @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 929 HB56A240 Series • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Voltage on Any Pin Relative to Vss VT -1.0to +7.0 Unit V Supply Voltage Relative to Vss Vcc -1.0to + 7.0 V Short Circuit Output Current lout 50 rnA Power DissipatIOn PT 10 W Operating Temperature Topr Oto + 70 ·C Storage Temperature Tstg - 55 to + 125 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + 70°C) Symbol Min Typ Max Unit Note Supply Voltage Vcc 4.75 5.0 5.25 V 1 Input High Voltage VIH 2.4 - 5.5 V 1 Input Low Voltage VIL -1.0 - 0.8 V 1 Parameter Note: 1. All voltage referenced to V ss. • DC Electrical Characteristics (TA = 0 to + 70°C, Vee = 5V ± 5%, Vss = OV) HB56A24OB/SB Parameter Symbol -6A Min Operating Current Standby Current ICC! - -7A Max 1150 Min - -SA -lOA Max Min Max 1050 - 950 Min - Unit Test Conditions 850 rnA tRC = 1,2 Min - 40 - 40 - 40 - 40 rnA TTL Interface RAS, CAS = VIH D out = High-Z - 20 - 20 - 20 - 20 rnA CMOS Interface RAS, CAS " Vcc - 0.2V Dout = High-Z ICC2 RAS Only Refresh Current ICC3 - 1150 - 1050 - 950 - 850 rnA tRC Standby Current ICC5 - 100 - 100 - 100 - 100 rnA RAS CAS D out = VIL = 2 Min = VIH = Enable 1 CAS Before RAS Refresh Current ICC6 - 1150 - 1050 - 950 - 850 rnA tRC = Min Fast Page Mode Current ICC7 - 1150 - 1050 - 950 - 850 rnA tpc = Min Input Leakage Current ILl -10 10 -10 10 -10 10 -10 10 I"A OV Output Leakage Current ILO -10 10 -10 10 -10 10 -10 10 I"A OV :$ Vout :$ 7V Dout = Disable Output High Voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V lout Output Low Voltage VOL 0 0.4 0 0.4 0 0.4 0 0.4 V lout Notes: :$ Yin = = :$ 1,3 7V -5mA 4.2 rnA 1. Icc depends on output load condition when the device is selected, Icc max is specified at the output open condition. 2. Address can be changed less than three times while RAS = V IL. 3. Address can be changed once or less while CAS = V IH' ~HITACHI 930 Note Max Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HB56A240 Series • Capacitance (TA ~ 25'C, Vee ~ 5V ±5%) Parameter Max Unit Input Capacitance (Address Ao- A9) Cll - 140 pF I Input Capacitance (WE, OE) CI2 - 160 pF 1 Input Capacitance (RAS, CAS) CI4 - 90 pF 1 Input/Output Capacitance (DQo to DQ39) CliO! - 25 pF I Notes: Symbol Typ Note I. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. • AC Characteristics (TA ~ 0 to +70'C, Vee = 5V ±5%, Vss Read, Write and Refresh Cycles (Common Parameters) ~ OV)I, 14, 15, 16 HB56A240B/SB Parameter -6A Symbol Min Random Read or Write Cycle Time -7A Max -lOA -SA Max Min Min Max Min Unit Note Max tRC 110 - 130 - 150 - ISO - ns tRP 40 - 50 - 60 - 70 - ns RAS Pulse Width tRAS 60 10000 70 10000 SO 10000 100 100000 ns CAS Pulse Width tCAS 15 10000 20 10000 20 10000 25 10000 ns Row Address Setup Time tASR 0 - 0 - 0 - 0 - ns Row Address Hold Time tRAH 10 - 10 10 - ns tASC 0 0 0 tCAH 15 15 15 20 - ns Column Address Hold Time - - 15 Column Address Setup Time - RAS to CAS Delay Time tRCD 20 45 20 50 20 60 25 75 ns S RAS to Column Address Delay Time tRAD 15 30 15 35 15 40 20 55 ns 9 RAS Hold Time tRSH 15 - 20 - 20 - 25 - ns CAS Hold Time tCSH 60 - 70 - SO - 100 - ns CAS to RAS Precharge Time tCRP 10 - 10 - 10 - 10 - ns OE to Din Delay Time tODD 15 - 20 20 - 25 - ns OE Delay Time from Dm tDZO 0 0 0 0 0 - 0 0 - ns tDZC - 0 CAS Setup Time from Din - - Transition Time (Rise and Fall) tT 3 50 3 50 3 50 3 50 ns Refresh Period tREF - 16 - 16 - 16 - 16 ms RAS Precharge Time 0 ns ns • Read Cycle HB56A240B/SB Parameter -6A Symbol Min -7A Max Min -SA Max Min -lOA Max Min Max Unit Note 2,3,17 tRAC - 60 - 70 - SO - 100 ns Access Time from CAS tCAC - 15 - 20 - 20 - 25 ns 3,4,13 Access Time from Address tAA - 30 - 35 - 40 - 45 ns 3,4,13,16 Access Time from RAS Access Time from OE toAC - 15 - 20 - 20 - 25 ns Read Command Setup Time tRCS 0 - 0 0 - ns tRCH 0 0 0 0 - ns Read Command Hold Time to RAS tRRH 0 - - 0 Read Command Hold Time to CAS - 0 - 0 - 0 - ns Column Address to RAS Lead Time tRAL 30 - 35 - 40 - 45 - ns Output Buffer Tum-off Time tOFF! 0 15 0 20 0 20 0 20 ns 6 Output Buffer Tum-off Time to OE tOFF2 0 15 0 20 0 20 0 20 ns 6 CAS to Din Delay Time tCDD 15 - 20 - 20 - 25 - ns @HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 931 HB56A240 Series • Write Cycle HB56A240B/SB Parameter -6A Symbol Min Write Command Setup Time -7A Max -8A Min Max -lOA Min Max Unit Note ns 10 25 - Min Max 0 twcs 0 - 0 - 0 Write Command Hold Time tWCH 15 15 - 15 10 20 - 20 - 25 - ns Write Command Pulse Width twp 10 - Write Command to RAS Lead Time tRWL 15 - 20 Write Command to CAS Lead Time tCWL 15 - 20 - Data-in Setup Time tDS 0 - 0 - 0 - 0 - ns II Data-in Hold Time tDH 15 - 15 - 15 - 20 - ns 11 Unit Note 10 20 20 ns ns ns • Read-Modify-Write Cycle HB56A24OB/SB Parameter Symbol -6A -7A Min Max Min -8A Max Min -lOA Max Min Max Read-Write Cycle Time tRWC 150 - 180 - 200 245 - ns RAS to WE Delay Time tRwD 80 - 95 - 105 - 135 - ns 10 CAS to WE Delay Time tCWD 35 _. 45 - 45 - 60 - ns 10 Column Address to WE Delay Time tAWD 50 - 60 - 65 - 80 - ns 10 OE Hold Time from WE tOEH 15 - 20 - 20 - 25 - ns Max Min • Refresh Cycle HB56A24OB/SB Parameter Symbol -6A Min -7A Max Min -8A Max Min -lOA Unit CAS Setup Time (CAS Before RAS Refresh Cycle) tCSR 10 - 10 - 10 - 10 - ns CAS Hold Time (CAS Before RAS Refresh Cycle) tCHR 10 - 10 - 10 - 10 - ns tRPC 10 - 10 - 10 - 10 - ns Max Min Max - RAS Precharge to CAS Hold Time Note Max • Fast Page Mode Cycle HB56A24OB/SB Parameter Symbol -6A -8A -7A Max Min -lOA Min Max Min - 45 - 50 - 55 10 - 10 - 10 Fast Page Mode Cycle Time tpc 40 Fast Page Mode CAS Precharge Time tcp 10 Fast Page Mode RAS Pulse Width tRASC - 100000 - 100000 Access Time from CAS Precharge tACP - 35 - 40 - RAS Hold Time from CAS Precharge tRHCP 35 - 40 - Fast Page Mode Read-Modify-Write Cycle Time tpCM 80 - 95 - Unit ns ns 100000 - 100000 ns 12 45 - 50 ns 13.17 45 - 50 - ns 100 - 110 - ns ~HITACHI 932 Note Hitachi America. Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819' (415) 589-8300 HB56A240 Series • Test Mode Cycle HB56A240B/SB Parameter Symbol -6A -7A Min Max Min -SA Max Min -lOA Max Unit Min Max Test Mode WE Setup Time tws 0 - 0 - 0 - 0 - ns Test Mode WE Hold Time tWR 10 - 10 - 10 - 10 - ns Notes: Note 1. AC measurements assume tT = 5 ns. 2. Assumes that tRCD S tRCD (max) and tRAD S tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL load and 100 pF. 4. Assumes that tRCD l!: tRCD (max) and tRAD S tRAD (max). 5. Assumes that tRCD S tRCD (max) and tRAD l!: tRAD (max). 6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIR (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIR and VIL' 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC' 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA' 10. twcs, tRWD, tcwD' tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs l!: twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRwD l!: tRWD (min), tCWD l!: tCWD (min) and tAWD l!: tAWD (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of condition is satisfied, the condition of the data out (at access time) is indeterminate. II. These parameters are referenced to CAS leading in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. tRASC defines RAS pulse width in fast page mode cycle. 13. Access time is determined by the longer of tAA or tCAC or tACP' 14. An initial pulse of 100 fJ-s is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycle is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Test mode operation specified in this data sheet is 8-bit test function controlled by control address bits ... CAO. This test mode operation can be performed by WE and CAS before RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of eight test bits accord each other, the condition of the output data is low level. Data output pin is 1/03 and data input pin is 1/02' In order to end this test mode operation, perform a RAS only refresh cycle or a CAS before RAS refresh cycle. 17. In a test mode read cycle, the value of tRAC, tAA, tOAC and tACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. @HITACHI Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 933 HB56A240 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS • Read Cycle tRC tRAS tRP tT tRCD tCRP tCSH CAS Address tOFFl tAA Dout Hi-Z Valid Output tRAC Din ~ : Don't care 0099-6 .HITACHI 934 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 HB56A240 Series • Early Write Cycle tRC tT lRP Address Dout Din High-Z ~ : Don't care OE : Don't care 0099-7 @HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 935 HB56A240 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Delayed Write Cycles tRC CAS Address WE Din Dout OE >* 1 : Invalid output ~ : Don't care 0099-8 ~HITACHI 936 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56A240 Series • Read-Modify-Write Cycle tRWC CAS Address WE Din Dout OE * 1 : Invalid output ~ : Don't care 0099-9 @>HITACHI Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 937 HB56A240 Series • RAS Only Refresh Cycle tRC Address High-Z Dout WE, OE : Don't care 2 ~: Don't care 3 REFRESH ADDRESS: AO - A9 (AXO-AX9 ) 0099-10 • CAS Before RAS Refresh Cycle tRC tRC tRP tRP tCHR tRPC tCRP tCHR tCSR Dout OPEN WE :V 1H 2 ~ : Don't care 0099-11 ~HITACHI 938 Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HB56A240 Series • Fast Page Mode Read Cycle tRASC tRHCP CAS Address Din Dout toAC ~ : Don't care 0099-12 @HITACHI Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 939 HB56A240 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Early Write Cycle tRASC Address Din High-Z Dout ~ : Don't care OE : Don't care 0099-13 ~HITACHI 940 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HB56A240 Series • Fast Page Mode Delayed Write Cycle tRASC CAS Address Din tOEH Hi-Z Dout toDD ~ : Don't care 0099-14 @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 941 HB56A240 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Fast Page Mode Read-Modify-Write Cycle tRASC CAS Address Din Dout ~ : Don't care 0099-15 ~HITACHI 942 Hitachi America, Ltd.• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589-8300 HB56A240 Series • TEST MODE CYCLE Note * 1 CBR or RAS-only refresh *2 ~:Don'tcare *3 Address, Din, OE : Don't care 0099-16 • (1) Test Mode Set Cycle tRC tRAS tCSR tws Dout tCHR tWH OPEN ~ : Don't care 0099-17 ~HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 943 HB56A240 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • (2) Test Mode Reset Cycle CAS Before RAS Refresh Cycle Dout OPEN ~ : Don't care 0099-16 RAS Only Refresh Cycle tRC tRP tRAH Address Dout OPEN 2 Refresh Address AO - A9 (AXO-AX9 ) ~ : Don't care 0099-19 • 944 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 Section 5 Video RAM ~HITACHI 946 Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 HM63021 Series 2048-Word x 8-Bit Line Memory • DESCRIPTION HM63021 Series HM63021 is a 2048-word x 8-bit static Serial Access Memory (SAM) with separate data inputs and outputs. Since it has an internal address counter, no external address signal is required and internal addresses are scanned serially. Using five different address scan modes, It IS applicable to FI FO memories, double-speed conversions, 1H delay lines and 1H/2H delay lines for digital TV signals. Its minimum cycle times are 28 ns and 34 ns each corresponding to 8 fsc of PAL TV signals and NTSC TV signals. All intputs and outputs are TTL-compatible. This device is packaged in a 300 mil dual-in-line plastic package. • • • • • • • • • • • • FEATURES Five Modes for Various Applications Corresponds to Digital TV System with 4 fsc Sampling (PAL, NTSC) Decoder Signal Output Pin; Fewer External Circuits Asynchronous Read/Write Operation; Separate Address Counter for Read/Write No Address Input Required High Speed; Cycle Time .............................. 28 ns/34 ns/45 ns (min) Completely Static Memory; No Refresh Required 8-bit SAM with Separate I/O Low Power .............................................. 250 mW typo Active Single 5V Supply TTL Compatible 3DDP28N (DP-28N) • ORDERING INFORMATION Part No. Access Time Package HM63021P-28 HM63021P-34 HM63021P-45 28 ns 34 ns 45 ns 300 mil 28-pin Plastic DIP (DP-28N) PIN OUT D I IHI2H I TBC I DSC I TBCE MODEl CLK RES I I RCLK RRES DmO Dml Dm2 Dm3 Dm4 OmS Dm6 Dm7 WE DECI I WDEC I H,.bZ V" ModE'S TBCE I~~ ~ ~:tol ~ ~ ~ F; 4 ~ 24 ~ ~ j 0~ C::: ~ ~ 1 ~~ ~ ~ ~ ~ ~~ ~ 16 ~ Write C::: = Control ~ ~ n I DSC I I IHI2H I RDEC I DEC2 TBC 1 D V" MODE2 MODE3 DE DoutO Doutt Dout2 Dout3 001,114 DoutS Dout6 Dout7 WRES I DS I DEC3 WCLK J WT 1 DEC4 (Top Vl@W) 0106-1 @HITACHI Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 947 HM63021 Series • PIN DESCRIPTION Pin No. Function Pin Name I MODEl Mode Input I (All Modes) I RCLK/CLK Read Clock Input (fBCE, DSC, TBC) Clock Input (IH/2H, D) 3 4-11 12 RRES/RES Read Reset Input (TBCE, DSC, TBC) Reset Input (lH/2H, D) DinO-Din? Data Input (All Modes) WE Write Enable Input (All Modes) 13 High Z/WDEC/DECI High Impedance (TBCE, DSC) Write Decode Pulse Output (fBC) Decode Pulse Output I (IH/2H, D) 14 VSS Ground (All Modes) 15 WCLKIWTIDEC4 Write Clock Input (TBCE, DSC, TBC) Write Timing Input (IH/2H) Decode Pulse Output 4 (D) 16 WRESIDS/DEC3 Write Reset Input (TBCE, DSC, TBC) Delay Select Input (IH/2H) Decode Pulse Output 3 (D) 17-24 DonW-Dont7 Data Outputs (All Modes) 25 OE Output Enable Input (All Modes) 26 MODE3/RDEC/DEC2 Mode Input 3 (fBCE) Read Decode Pulse Output (TBC) Decode Pulse Output 2 (IH/2H, D) 27 MODE2 Mode Input 2 (All Modes) 28 Vee Power Supply ( + 5V) (All Modes) • MODE TABLE Mode Signals MODEl Note: Application Example Mode MODE2 MODE3 Note H H H Time Base Compression/Expansion (fBCE) H H L Double Speed Conversion (DSC) Picture in Picture Non Interface H L - Time Base Correction (fBC) Time Base Corrector I L H - IHl2H Delay (IH/2H) Vertical Filter I L L - Delay Line (D) Delay Line I I. Decoder Output Signal (RDEC, DEC2). • ABSOLUTE MAXIMUM RATINGS Value Unit Notes Voltage on Any Pin Relative to Vss VT -0.5 to + 7.0 V 1 Power Dissipation PT 1.0 W ·C Parameter Operating Temperature Topr Oto + 70 Storage Temperature T stg - 55 to + 125 ·C Tbias -lOto +85 ·C Storage Temperature Under Bias Note: Symbol I. - 3.5V for pulse width S 10 ns. ~HITACHI 948 Hitachi America, Ltd.· Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005· 1819. (415) 589·8300 HM63021 Series • BLOCK DIAGRAM DlnO WE v" I 4- I Write Address Control L 1204711 Address 1 Dm7 - I Decoder ~ r-- ........ ~ '-II Latch Latch f7-ff LLo-I~ Write Column Decoder Wflte Column RCLK/CLK- SWitch (Write Stop) RRES/RES;WCLK/W T LOIIC - Write Row Decoder MODE2 MODE3 \ Control WRES/D S MODEl "-./ Timing i Memory V - MatriX A B 1128.641 1128.641 ! Read Row Decoder \ ~/ 120471 1900.18101 Read Column SWitch Read Column Decoder ~ .. Decoder 1909.18191 111341 111251 Output Latch I Read Address Control ~--~ Dou1O Address - RDEC iiECi DEC2 m;3 DEC4 I 1. Dout7 OE 0106-2 • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA Parameter Supply Voltage Input Voltage Note: = 0 to + 70'C) Symbol Min Typ Max Unit Vee 5.0 0 5.5 0 V VSS 4.5 0 VIR 2.4 - 6.0 V VIL -0.5 - 0.8 V 1. - 3.0V for pulse width :s Note V I 10 ns. @HITACHI Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 949 HM63021 Series • DC and Operating Characteristics (TA = 0 to +70'C, Vee = 5V ±10%, Vss = OV) Parameter Symbol Min Typ Max Test Condition Unit Input Leakage Current IILlI - - 10 ftA Vee = 5.5V Yin = VsstoVce Output Leakage Current IILOI - - 10 ftA OE = VIH Vout = Vss to Vee Operating Power Supply Current Icc - 50 90 rnA Min. Cycle, lout VOL Output Voltage VOH Notes: = = 0 rnA - - 0.4 V 2.4 - IOH = - 4 rnA, DoutO to Dou!7 Pin - - V 2.4 V IOH = - 1 rnA, DEC Output Pin 2 25'C and for reference only. 25'C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Conditions Input Capacitance Cin - 6 pF Yin = OV Output Capacitance Cout - - 9 pF Vout = OV Notes: 1 IOL = 8 rnA, DoutO to Dout7 DEC Output Pin I. Typical values are at Vee = 5V, TA 2. IOL = 6 rnA for 45 ns version . • Capacitance (TA Note Note 2 I. This parameter is sampled and not 100% tested. 2. 13, 15-24, 26 pin. • AC Characteristics (Vee AC Test Conditions 5V ± 10%, T A = 0 to + 70'C, unless otherwise noted.) = Input and Output Timing Reference Levels: 1.5V Input Pulse Levels: Vss to 3V Input Rise and Fall Times: 5 ns HM63021-28/34 DEC Output Load Dout Output Load (A) Dout Output Load (B) (tOLZ' tOHZ) DEC 0--"""'--4 480Q 395Q Dout o---.--~ Dout 0---.---4 *1 30pF 255Q * 5pF I 25SQ 0106-3 0106-4 Note: 0106-5 *1. Including scope and jig. HM63021-45 DEC Output Load D out Output Load (A) +5V Dout Output Load (B) (tOLZ, tOHZ) +5V +5V DEC 0--.---+ Dout 30pF O 0--.---+ Dout 294Q \ 0-.---+ 0106-7 0106-6 Note: *1. Including scope and jig. ~HITACHI 950 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 0106-8 HM63021 Series Read Cycle Parameter HM63021-28 Symbol HM63021-34 HM63021-45 Unit Min Max Min Max Min Max 45 ns 15 - Read Cycle Time tRC 28 - 34 Read Clock Width tRWL 10 - 10 tRWH 10 - 10 - tAC - 20 - 25 - 30 ns 20 - 25 - 30 ns 50 - 60 ns 5 5 - ns 5 - Access Time Decode Output Access Time I I (Fall) tOA! (Rise) tOA2 Output Hold Time 40 15 ns ns tOH 5 (Fall) tOOHI 5 (Rise) tOOH2 5 - Output Enable Access Time tOE - 20 - 25 - 30 ns Output Disable to Output in High Z tOHZ 0 15 0 20 0 25 ns Output Enable to Output in Low Z tOLZ 5 - 5 - 5 - ns Decode Output Hold Time I I 5 5 5 ns ns Write Cycle Parameter HM63021-28 Symbol Min Max HM63021-34 Min Max HM63021-45 Max ns 15 - 7 - ns 7 - ns Write Cycle Time twc twc (lH/2H Mode) 28 - 34 - 45 56 - 68 90 Write Clock Width twwL 10 10 twwH 10 Input Data Setup Time tos 5 Input Data Hold Time tOH 5 5 - 5 - 7 - 7 Max Min WE Setup Time WE Hold Time WT Setup Time WT Hold Time tWESL 5 tWESH 5 tWEHL 5 - tWEHH 5 - 5 tWTSL 5 5 tWTSH 5 tWTHL 5 tWTHH 5 - 10 5 5 5 5 5 5 Unit Min 15 7 7 7 7 7 7 ns ns ns ns ns ns ns ns ns ns ns Reset Cycle Parameter Symbol HM63021-28 Min Reset Setup Time tRES 8 Reset Hold Time tREH 5 Clock Setup Time Before Reset tREPS 8 Clock Hold Time Before Reset tREPH 5 Max - HM63021-34 Min HM63021-45 9 - 10 5 - 7 9 5 10 7 Max - Unit ns ns ns ns @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 951 HM63021 Series with address 2047 in the read address counter. Using these pulses, the memory area can be extended easily (multiple-HM63021s can be used with ease). Mode Description • Time Base Compression/Expansion Mode This mode turns HM63021 into a 2048-word x 8-bit FIFO memory with asynchronous input/output. The HM63021 provides 2 clocks (RCLK, WCLK) and 2 resets (RRES, WRES), one each for read and write. The internal address counters increment by 1 address clock and are reset to address o. A write-inhibit function of HM63021 stops writing automatically after the data has been written into all addresses 0 to 2047. The write-inhibit function is released by reset using WRES, and the HM63021 restarts writing into address O. • Double-Speed Conversion Mode This mode turns HM63021 into a 1024-word x 8-bit x 2 memory with asynchronous input/output. It is used for generating non-interlaced TV Signals. When the original Signal and the interpolated signal (1 field delay) of interlaced sign Is are input to the HM63021, multiplexed per dot, it outputs non-interlaced signals for each line. 8 fsc should be input to RCLK and WCLK. A standard H synchronizing signal and a non-interlace H synchronizing signal are input to WRES and RRES respectively. A write-inhibit function is provided in this mode, making it applicable to PAL TV, where extra data (1135-1024 = 111 bits) is ignored. • TBC Mode This mode turns HM63021 into 2048-word x 8-bit FIFO memory with asynchronous input/output. The HM63021 provides 2 clocks (RCLK, WCLK) and 2 resets (RRES, WRES), one each for read and write. The internal address counters increment by 1 address at each clock and are reset to address o. The internal address counters return to address 0 after they reach address 2047. The HM63021 outputs a write decode pulse from WDEC, sychronizing it with address 2047 in the write address counter, and read a decode pulse frorn RDEC, synchronizing • 1H/2H Delay Mode This mode turns HM63021 into a 1024-word x 8-bit x 2 delay line with synchronous input/output. Delay time is defined by the reset period of RES. Since the HM63021 outputs a 901 decode pulse (DEC1) and a 910 decode pulse (DEC2), connecting DEC2 to RES, for example, outputs 1H- and 2H- delayed signals alternately at a 8- fsc cycle when the original signal is input at a 4- fsc cycle. A write-inhibit function is provided in this mode, making it applicable to PAL TV, where extra data (1135-1024 111 bits) is ignored. • Delay Line Mode This mode turns HM63021 into a 2048-word x 8-bit delay line with synchronous input/output. Delay time (3 to 2048 bits) is defined by the reset period of RES. The delay is 2048 bits when RES is fixed High. Signals delayed by 910 bits to 1135 bits for example, can be easily obtained without external circuits by just connecting selected decoded pulses on DEC1-DEC4 to RES. Notes on Using HM63021 • Hitachi recommends that pin 13 (high impedance) should be fixed by pulling up or down with a resistor (of several ko') in TBC or DSC mode. • Hitachi recommends that the mode Signal input pins and DS pin should be fixed by pulling them up or down with a resistor (of several ko'). • Data integrity cannot be guaranteed when mode is changed during operation. • When a read address coincides with a write address in TBCE, TBC or DSC mode, the data is written correctly but it is not always read correctly. (1) Read after Write (3 bits delay) l,?;twcmm 0106-9 (2) Write after Read (2048 bits delay) t ::a;Ons 0106-10 ~HITACHI 952 Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.' Brisbane, CA 94005-1819' (415) 589-8300 HM63021 Series • At power on, the output of the address counter is not defined. Therefore, operations before the system is reset cannot be guaranteed, and decode signal output is not defined until after the first reset cycle. • The decode signal is latched by a decode output latch circuit at the previous address of the internal counter address and is output synchronized with the next address. For example, WDEC in TBC mode is latched at write address 2046 and is output at write address 2047. If a write reset is performed on address 2047 at this time, the write address becomes 0 and WDEC is output. • In the reset cycle, the input levels of WRES, RRES, RES are raised to satisfy tREH, and are fixed high until tREPH in the next pre-reset cycle is satisfied. The rise timings of the reset signals (RES, WRES, RRES) are optionals provided that the tREPS specification is satisfied. The timings at which RES, WRES, and RRES fall after preset are also optional, provided that the tREPH and tRES specifications are satisfied. The same operation is performed in other modes. 0106-11 • Hitachi recommends that tm (time between mode set and the first cycle (Pre-reset» should be kept for 2 cycle time (56 ns/68 ns/90 ns) or more while the power supply is on. (1) TBCE, TBC, DSC and Delay Line Mode ~ ~ Valid 0106-12 @HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 953 HM63021 Series (2) 1H/2H Delay Mode ~ ~ mode.DS .ot:.>O.l~I'-_"":'::=- ~ ~ ____-+________+-_______-I_ 0106-13 Note: When mode pins are ftxed with Vee, GND in mode set while the power supply in on, t", spec is not needed. Decode Signal When internal address counter reaches the specified address as shown below, decode outputs become low. Pin No. Mode TBC Pin Name Internal Address Counter Timing of the Output Signal 13 WDEC Write 2047 After Write 2047 Completion of Writing on all bits is detected. 26 ROEC Read 2047 Output of 2046 Completion of Reading from all bits is detected. 13 DECI Read 900 (2H) Output of 900 (IH) By inputting this signal to pin #3, 901/1802-bit delay output is obtained. 26 DEC2 Read 909 (2H) Output of 909 (lH) By inputting this signal to pin #3, 91O/1820-bit delay output is obtained. Read 900 Output of 899 By inputting this signal to pin #3, 901-bit delay output is obtained. Read 1810 Output of 1809 By inputting this signal to pin # 3 after the frequency of DEC I is divided into two, 181 I-bit delay output is obtained. Read 909 Output of 908 By inputting this signal to pin # 3, 910-bit delay output is obtained. Read 1819 Output 1818 By inputting this signal to pin # 3 after the frequency ofDEC2 is divided into two, 1820-bit delay output is obtained. IH/2H 13 Delay Line Note: Operation 26 DECI DEC2 16 DEC3 Read 1134 Output 1133 By inputting this signal to pin # 3, I 135-bit delay output is obtained. 15 DEC4 Read 1125 Output 1124 By inputting this signal to pin # 3, 1126-bit delay output is obtained. 1. When counter is reset by Reset Signal (RRES, RES, WRES), address becomes 0. Write-Inhibit Function When internal address counter is as follows, writing is inhibited automatically for the next cycle. the write-inhibit function is cancelled by reset through WRES or RES. Note: Mode Write-Inhibit Function (Internal Counter Address) TBCE Write-inhibit after address 2047 DSC Write-inhibit after address 1023 x 2 TBC No function IH/2H Write-inhibit after address 1023 D No function When address counter is reset by WRES or RES, address becomes O. ~HITACHI 954 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 HM63021 Series Read Reset Cycle (TBCE, TBC Modes) RCLK RRES.t .s OOU,·1 .' 0106-14 Notes: *\. The read address counter is reset at the first falling edge of RCLK after RRES falls. meeting the specifications of tREPS and tREPH. and it is not reset at the next falling edge of RCLK even if RRES is kept low. When tRES. tREH. tREPS. and tREPH cannot meet the specifications. the reset operation is not guaranteed. *2. Output is from the read address of the previous cycle. *3. When RRES is fixed high. the data at the read address counter is reset after the data of address 2047 is output. and the same operation restarts. Write Reset Cycle (TBCE, TBC Modes) WE 0106-15 Note: The write address counter is reset at the first falling edge of WCLK after WRES falls. meeting the specifications of tREPS and tREPH. and it is not reset at the next falling edge of WCLK even if WRES is kept low. When tRES. tREH. tREPS. and tREPH cannot meet the specifications. the reset operation is not guaranteed. _HITACHI Hitachi America. Ltd. 0Hitachi Plaza 02000 Sierra Point Pkwy. 0Brisbane, CA 94005-1819 0(415) 589-8300 955 HM63021 Series Reset Cycle (DSe Modes) Din *2. *:\, ... RRES -,-,-...,,,, i"A--+-.l!..L.l.f.L.i"-L.ol¥..Jf Dout Reset Timing 1 Reset Tlmmg 2 0106-16 Notes: *1. The write address counter is reset at the first falling edge of WCLK after WRES falls, meeting the specifications of tREPS and tREPH, and it is not reset at the next falling edge of WCLK even if WRES is kept low. When tRES, tREH, tREPS, and tREPH cannot meet the specifications, the reset operation is not guaranteed. *2. The read address counter is reset at the first falling edge of RCLK after RRES falls, meeting the specifications of tREPS and tREPH, and it is not reset at the next falling edge of RCLK even if RRES is kept low. When tRES, tREH, tREPS, and tREPH cannot meet the specifications, the reset operation is not guaranteed. *3. When tREPH, tRES, tREH (WRES to WCLK), or tREPS, tREPH, tRES, tREH (pRES to RCLK) cannot meet the specifications, the output of video signal A is not guaranteed. (Reset Timing I). *4. When tREPS (WRES to RCLK), or tRES, tREH, tREPS, tREPH (PRES to RCLK) cannot meet the specifications, the interpolation signal B is not guaranteed. (Reset Timing II). ~HITACHI 956 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM63021 Series Reset Cycle (1H/2H Mode) _*2 RES *3 Dout I \ DS *3 \ (Hieh) or (Low) 0106-17 Notes: *1. WT is the input during half cycle of eLK, meeting the specifications of tWTSL, tWTHL, tWTSH, and tWTHH. Data is written when WT is low. Reset is possible when WT is high. *2. Read address counter is reset at the first falling edge of eLK after RES falls, meeting the specifications of tREPS and tREPH, and it is not reset at the next fa11ing edge of eLK even if RES is kept low. When tRES, tREH, tREPS, and tREPH cannot meet the specifications, the reset operation is not guaranteed. *3. When OS is fixed high, IH output data is delayed by n bits and 2H output data is delayed by 2n bits where 2n is the reset cycle of RES. When OS is fixed low, IH output data is delayed by n - S bits and 2H output data is delayed by 2n - 5 bits. @HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 957 HM63021 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Reset Cycle (D Mode) 0106-16 Note: *1. The read address counter is reset at the first falling edge of CLK after RES falls. meeting the specifications of tREPS and tREPH. and it is not reset at the next falling edge of CLK even if RES is kept low. When tRES. tREH. tREPS. and tREPH cannot meet the specifications. the reset operation is not guaranteed. Write Enable (TBCE, DSC, TBC, D Modes) WCLK 02 (CLK) WE o1 Din 0106-19 Notes: *1. When tWEHL. tWESH. tWEHH. and tWESL cannot meet the specifications. the write enable operation is not guaranteed. *2. In the delay line mode. CLK takes the place of WCLK. $ 958 HITACHI Hitachi America. Ltd.• Hitachi Plaza .2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819. (415) 589-8300 HM63021 Series Write Enable (1H/2H Mode) eLK Clfle) Wi' (4f.cl WE·) Do. 0106-20 Note: *\. When tWTSL, twrnL, tWEHL, and tWEHH cannot meet the specifications, the write enbable operation is not guaranteed. Decode Output (TBe, D Modes) 0106-21 Notes: *\. In TBC mode, WCLK or RCLK takes the place of CLK. *2. DEC is WDEC or ROEC in TBC, DECI, DEC2, DEC3 or DEC4 in D mode. Decode Output (1H/2H Mode) 0108-22 Note: .\. When tWTSL, tWTHL> tWTSH, and tWTHH cannot meet the specifications, the decde output operation is not guaranteed. ~HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 959 HM63021 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Output Enable (All Modes) OE High Z Data Valid Data Valid 0106-23 Note: * 1. Transition of tOHz and tWLz is measnred ± 200 mV from steady state voltage with Output Load B. This parameter is sampled and not 100% tested. • 960 HITACHI Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM53051 Series 262,144-Word x 4-Bit Frame Memory • DESCRIPTION HM53051P Series HM53051 P is a 262,144-word x 4-bit frame memory, using the most advanced 1.3 ).tm CMOS processes. It performs serial access by an internal address generator. It offers a high-speed cycle time of 45 ns or 60 ns (min). As input data and output data can be written or read in any cycle, synchronized with a system clock, and the delay between data read/write operations is freely settable. Y/C separation and frozen pictures can be realized easily in 4 fsc NTSC digital TV or VCR systems. Also, it enables random access in 32-word x 4-bit data block. With this function, picture in picture or a multiplexed picture can be displayed with ease. • FEATURES 3DDP188 (DP-18B) • PIN OUT • 262, 144-Word x 4-Bit Serial Access Memory • Organized with Dual Ports Serial Input ...................................................... x 4-Bit Serial Output .................................................... x 4-Bit • High Speed Read/Write Cycle Time ................................ 45 ns/60 ns (min) Access Time ......................................... 35 ns/40 ns (max) • Semi-Synchronous Read/Write Cycle • Low Power Active: 200 mW (typ) • Random Access in 32-Word x 4-Bit Blocks • External Refresh Control is Unnecessary • ORDERING INFORMATION HM53051P Series v. . ~ Dout2 Dout3 DE DoutO TAS Dln2 Part No. Access Time Package HM53051P-45 HM53051P-60 45ns 60ns 300 mil 18-pin Plastic DIP (OP-18B) Dmt 0107-1 (Top View) • PIN DESCRIPTION • BLOCK DIAGRAM Pin Name Din SAD Memory Array Row Decoder Function Data Input Oout Data Output OE Output Enable 262,144 X4 TAS Transfer Address Strobe CLK System Clock CGW Clock Gate (Write) CGR Clock Gate (Read) SAD Serial Address Control SAS Serial Address Strobe & Timing Generator WE ReadIWrite Enable Read/Wnte/Refresh DoutO Dout2 Dout J DIRO Dout3 Dm2 Din I WE Dm3 0107-2 ~HITACHI Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 961 HM53051 Series • FUNCTIONAL DESCRIPTION • Serial Access Memory with I/O Separated • Write Cycle by CGW Read cycle and write cycle of HM53051 can be operated independently synchronized with a system clock. It realizes time compression or expansion for picture in picture in digital TV, for example. Write data are taken in at the falling edge of the system clock CO< when CGW is low. If CGW is high, HM53051 does not enter write cycle (cycle time is defined by system clock cycle time). Time is compressed easily with CGW. eLK XXXXxxxxx :XX~_D_n_)@(D.+1 D,n D.+2 XXXXXXXX 0107-3 • Read Cycle by CGR Read data is output at the falling edge of the system clock CO< when CGR is low. If CGR is high, HM53051 does not enter read cycle (cycle time is defined by system clock time). Time is expanded is realized easily with CGA. CLK Dout __~D~.___~ D.+l ~~______D_._+2_________~______~D~.+~3~______ 0107-4 • RANDOM ACCESS The HM53051 is also capable of random access by serial address input, SAD. Random access by the unit of 32-word x 4-bit is performed, when 'fAS is low after read address (ARO-AR12), write address (AWO-AW12) and mode setting BAS flags, RF (Read Flag), WF (Write Flag) and MF (Mode Flag) are read into by SAD with synchronous ~. In order to output data continuously, the address specified by SAD increments automatically. u-u-L.rl..S --- SAD 0107-5 • MODE PROGRAMMING Operation mode in HM53051 is programmed by the combination of SAD 5-bit. MF WF RF AWO ARO Mode 0 0 0 x x Write/Read Address Asynchronous Transfer 0 0 1 x x Write Address Asynchronous Transfer 0 1 0 1 1 1 0 0 x x x x Read Address Asynchronous Transfer 0 x x 1 0 1 x x Write Address Synchronous Transfer 1 1 0 x x Read Address Synchronous Transfer 1 1 1 1 1 System Reset 1 1 1 1 1 1 1 1 1 0 0 1 0 1 Inhibit Write/Read Address Synchronous Transfer 0 Note: x means Don't Care. • 962 HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 HM53051 Series • READ/WRITE ADDRESS ASYNCHRONOUS TRANSFER MODE • Read Address Asynchronous Transfer Mode (1) Read address asynchronous transfer mode (1) (CGR: Low) --,1 CLK Dout r-----'L-I 31,-,32,-,33 r-----' 63,-,64,-,65 r--L.....J L-I L-I L-I L-I ,-, 2,-, 3 L.....J L-I L.....J ~------~2--- D31~ .1. .1. Add AR Add AR+I 0107-6 Note: The data block at read address AR, specified by SAD, is output starting from the 32nd system clock after the faIling of TAS. (2) Read address asynchronous transfer mode (2) (CGR: High) Dout 01 I. 0107-7 Notes: 1. The data block at read address AR, specified by SAD, is output starting from the 32nd system clock after the faIling of TAS. 2. If CGR is turned to low after 33rd clock from falling edge of TAS, the data at read address AR( D2, D3, D4 ... ) is output with synchronous CLK while CGR is low. • Write Address Asynchronous Transfer Mode (1) Write address asynchronous transfer mode (1) (GRW: Low) --, 1 ,-, 2 ,-, 3 CLK Din L-I L.....J r _____ , L.....J 31 , - , 32 , - , 33 L-.J L.....J r _____ , L-.J 63,-, 64,-, 65 L-.J L-I r- L-.J ~ - - - - - -,..~~v,....::.:~",,-.::D=-2--~ Add AW Add AW+I Add AW+2 0107-8 Note: The data block at write address AW, specified by SAD, is taken in startmg from the 1st clock after the falling edge ofTAS. (2) Write address asynchronous transfer mode (2) (CGW: High) CLK ~----- TAS """L..-J CGW D,n ------~ AddAW 0107-9 Note: If CGW is turned to low after falling of TAS, the data block at write address A W is taken in with synchronous CLK. • HITACHI Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 963 HM53051 Series • READ/WRITE ADDRESS SYNCHRONOUS TRANSFER MODE • Read Address Synchronous Transfer Mode ., 1 ~ 2 ~ elK n 31 32 33 34 1:;;n:1032 ( 63 64 65 66 .1~IILJL....rl..JLI/IlJL.....fLJl.. ----II~II II LJ LJ -----:Sl----:Sl----------Sl-------Dout ~~~~~\~ ~ Add ARN - I Add ARN+1 I AR 0107-10 Note: When TAS turns to low, the data block at read address AR, specified by SAD, is output after the data block at the present read address ARN, and the next address ARN + I is put out. • Write Address Synchronous Transfer Mode '{) Din ~~~::Emill)_ • I Add AW Add AW+l 0107-11 Note: When TAS turns to low, the data block being written is taken into write address AW. • SYSTEM RESET MODE System reset mode is the same as read/write address asynchronous transfer mode except that read/write address are reset to O. • System Reset by SAD Note: System reset mode starts when MF, WF, RF, A WO, and ARO are all high. o System Reset by SAS and TAS eLK LJLn SAS L-J TAS L-J I------ System reset mode 0107-12 Note: System reset mode starts when both SAS and TAS are low at the falling edge of the CLK. o 1 Field Delay Note: Field-delayed data is output, when CGR and CGW turn to high before the system reset at the beginning of every field, and tum to low simultaneously after the 33rd clock from the system reset. .HITACHI 964 Hitachi America, Ltd. 0Hitachi Plaza 02000 Sierra Point Pkwy. 0Brisbane, CA 94005-1819 0(415) 589-8300 HM53051 Series • NOTES ON USING HM53051 • Input/Output data of 32 words is not written or read in read/write address asynchronous transfer mode or during system reset. The data is written or read out in blocks of 32-word x 4-bit. Input data of less than 32 words is not written in write address asynchronous transfer mode or during system reset. When asynchronous read address transfer mode or system reset mode is activated, output from the current data block will continue. When output data from the current data block is finished, the next data block is not read out if it has less than 32 words. • Input data is not read out immediately. The data (32 word x 4-bit) is written into the memory array in the next 32 cycles after it is taken in. The data can be read out only after writing to the memory array is completed. If read address transfer mode is programmed after the 33 word clock from on input data block, new data can be read out. If this mode is programmed before the 33 word clock, new data or old data is output. (1) Read/write address asynchronous transfer mode eLK 32 32 32 cycle I 1 I D•• Dou' (Wnte Address IRud Ado!ns. ANI ANI 1 I I· 1 DID of Address AN Readml from Wntllll on ·1 Address AN Addn.. AN ·1 ·1· D61110f Address AN 0107-13 (2) Read/write address synchronous transfer mode 11 2 1 3 1"'1 32 11 2 1 3 1... 132 112131"'1321112131".1321 I (Read Address rWrite Address AN) ANI D •• Din of Address AN Wntullon Adcinss AN Dout Doutof Address AR Addr~~ from .1_ Readmg Dout of Addre&!!> AR t A~ 1 Dout of .1_ Addn.. AN 0107-14 • HITACHI Hitachi America. Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 965 HM53051 Series • Mode Programming Do not reprogram write address transfer mode or system reset mode before a write operation of the previous write address transfer mode or system reset mode is completed. If it is reprogrammed during a write operation, address becomes invalid, and the device may malfunction. Do not reprogram read address transfer mode before a read operation of the previous read address transfer mode or system reset mode is completed. If it is reprogrammed during a read operation, address becomes invalid, and the device may malfunction. (1) Read address asynchronous transfer mode _I ~ I (Read Addre!>!> AN) 11 2 1 3 1 ... 1 32 11 2 1 3 1 ... 1 32 11 2 1 3 1 ... 1 32 cyde 1 (Read Addrelts AM) Dout Readmg from Readmg from Doulof Addrf''i'' AN Address AM Addrf'~l> AM Dou! of Addr!'!),; AN 0107-15 (2) Read address synchronous transfer mode 1 1 2 1 3 1 . .. 1 32 eLK eyde 11 2 1 3 1 ... 1 32 11 2 1 3 1 ... 1 32 1121 I I (Read Addl't'l>l> AM I (Read Addre!>s AN) DOllt Readmg from Addresl> AN I· Readmg from Addrf'.... AM Dout of Addrt'ss AN -, 0107-16 (3) Write address asynchronous transfer mode 11 21 3 1 ... 1 32 eLK cycle - 11 2 1 3 1 ... 1 32 1 1 2 1 3 1 ... 1 32 1 ~ (Write Addles" AM (Wflte AddrC'''b AN) I Dm Om of Addrf'!>~ WrltmM on AN Addreo;s AN Om of Addrf"ss AM 0107-17 ~HITACHI 966 Hitachi America, Ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 HM53051 Series (4) Write address synchronous transfer mode 1 \ 2 \ 3 \ ... \ 32 eLK cycle 1\2\3\ .. -1 32 11 21 3 1··j32 I U- (Wnte Addres. AN) (W nte Address AM) DIn Din of Wrltllllon Address AN Address AN DID of Addre..'1 AM 0107-18 Before an address can be set, 32 ClK initialization cycles or more are required. • Addresses must be set by read and write address asynchronous transfer or system reset 100 I-'s after power on. • ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Voltage on Any Pin Relative to Vss VT -1.0to +7.0 V Power Dissipation PT 1.0 W Unit Operating Temperature Topr Oto + 70 'c Storage Temperature Tsta - 35 to + 125 ·C Storage Temperature (under Bias) Tbtas -lOto + 85 ·C • ELECTRICAL CHARACTERISTICS • Recommended DC Operating Conditions (TA = 0 to + lO'C) Parameter Symbol Min Typ Max Unit Supply Voltage Vee 4.5 5.0 5.5 V Input Voltage VSS 0 0 0 V VIR 2.7 - 6.5 V VIL -0.5 - 0.8 V Note I Note: 1. - 3.0V for pulse width S 10 ns. • DC and Operating Characteristics (TA Parameter = 0 to +lO'C, Vee Max Unit 60 mA Min. Cycle, lout = OmA -10 - 10 I-'A Vee = 5.5V Yin = Vss to Vee -10 - 10 I-'A OE = VIR Vout = Vss to Vee - 0.4 V IoL - V loR Max Unit 5 pF Yin = OV 7 pF Vout = OV lee Input Leakage Current ILl Output Leakage Current ILO Output Voltage VOL - VOR 2.4 = Parameter 25'C, f = 1.0 Symbol Input Capacitance Cin Output Capacitance Cout = OV) 40 - Operating Power Supply Current • Capacitance (TA ±10%, Vss Typ Min Symbol = 5V Test Conditions Note = 4.2mA = -2mA MHz) Min Typ - - Test Conditions Note Note: This parameter is sampled and not 100% tested. • HITACHI Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 967 HM53051 Series • AC Characteristics (Vee = 5V AC Test Conditions ± 10%, TA = 0 to + 70°C) Input and Output Timing Reference Levels: 1.5V Input Pulse Levels: Vss to 3V Input Rise and Fall Times: 5 ns 2 TTL + 50 pF Output Load: (Including scope and jig) Parameter Symbol HM53051-45 HM53051-60 Min Max Min Max System Clock Cycle Time tcc 45 300 60 300 ns CLK Pulse Width tCL 15 15 - ns tCH 15 - 15 - ns Access Time from CLK tAC - 35 - 40 ns Output Hold Time toH 5 - ns Output Enable Access Time tOEA 30 ns Output Enable to Output in Low Z tOLZ 5 - 5 - ns Output Disable to Output in High Z tOHZ 0 20 0 20 ns CGR Setup Time tGRS 15 - 15 ns CGR Hold Time tGRH 5 5 CGW Setup Time tGWS 15 - - 15 - ns CGW Hold Time tGWH 5 - 5 ns Write Command Setup Time twcs IS - 15 - Write Command Hold Time tWCH 5 - 5 - ns Data Input Setup Time tDS 15 - 15 ns Data Input Hold Time tDH 5 5 SAS Cycle Time tsc 45 60 - ns tSL 15 15 - ns tSH 15 15 - ns Serial Address Setup Time tSAS IS - - IS ns Serial Address Hold Time SAS Pulse Width - 25 - 8 - ns ns ns tSAH 5 - 5 - SAS Setup Time during Mode Programming tSSH 15 - 15 - ns SAS Hold Time during Mode Programming tSHH 5 - 5 - ns TAS Setup Time tTS 15 15 - ns TAS Hold Time tTH 5 - 5 - ns SAS Setup Time durin~ System Reset by SAS/TAS tSSL 15 - 15 - ns SAS Hold Time durin1LSystem Reset by SAS/TAS tSHL 5 - 5 - ns ~HITACHI 968 Unit Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.· Brisbane, CA 94005-1819. (415) 589-8300 ns HM53051 Series • TIMING WAVEFORMS • Read/Write Cycle CLK Don CGR OE Low 'ON DOllt 0107-19 Notes: 1. Write cycle starts when CGW is low and WE is low. Data are not written when WE is high. Time-compression mode is realized by controlling CGW. 2. Read cycle starts when CGR is low. Time-expansion mode is realized by controlling CGR. • Read Cycle (OE Control) IGI