1991_Fujitsu_CMOS_Channeled_Gate_Arrays 1991 Fujitsu CMOS Channeled Gate Arrays

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CMOS Channeled Gate Arrays
1991 Data Book and
Design Evaluation Guide

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1991
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FUJITSU

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........
........

Design Information
UHB Series Unit Cell Library
CG10 Series Unit Cell Library

IIIDII

Sales Information

1m

cO

FUJITSU

CMOS Channeled Gate Arrays
1991 Data Book
and Design Evaluation Guide

Fujitsu Microelectronics. Inc.
Integrated Circuits Division
3545 North First Street. San Jose. CA 95734-7804
Tel: (408) 922-9000
FAX: (408) 432-9044

Copyright@ 1990 Fujitsu Microelectronics, Inc., San Jose, California

All Rights Reserved.
Circuit diagrams using Fujitsu products are included to illustrate typical semiconductor applications. Information sufficient for
construction purposes may not be shown.
The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu
Microelectronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent rights or trademarks
claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.
Nopartofthispublicationmaybecopiedorreproducedinanyformorbyanymeans,ortrans!erred to any third party without prior
written consent of Fujitsu Microelectronics, Inc.
This document is published by the Publications Department, Integrated Circuits Division, Fujitsu Microelectronics, Inc.,
3545 North First Street, San Jose, California, U.S.A. 95134-1804; U.S.A.
Printed in the U.S.A.
Edition 1.0

Ethernet™ is a registered trademark of Xerox Corporation.
EtherStar™ is a trademark of Fujitsu Microelectronics, Inc.
StarLANTM is a trademark of AT&T.
UNIX"M is a trademark of Bell Telephone Laboratories, Inc.
Vl9wCADTM is a trademark of Fujitsu Limited
X Window System™ is a trademark of Massachusetts Institute of Technology (MIT)
VERILOGTM is a trademark of Cadence Design Systems
LASARTM is a trademark of Teradyne, Inc.
HILO@ is a registered trademark of GenRad, Inc.
IKOSTM is a trademark of IKOS Systems, Inc.
Synopsys@ Design Compiler™ is a trademark of Synopys Inc.

Contents
CMOS Channeled Gate Arrays
Preface .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. iii
Fujitsu ASIC Products ............................................................... xiii

Section 1 - Design Information
Chapter 1

Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Chapter 7

Fujitsu CMOS Channeled Gate Array Products ........................ 1-3
Data Sheet: UHB Series CMOS Gate Arrays ........................ 1-13
Data Sheet: CG10 Series CMOS Gate Arrays ....................... 1-41
Steps Toward Design ........................................... 1-69
Design Procedures ............................................ 1-73
Design Considerations .......................................... 1-61
Delay Estimation Principles ...................................... 1-93
Quality and Reliability ......................................... 1-103
Application Notes ............................................. 1-119
Developing Test Patterns that Work with the Physical Tester ........... 1-121
Selecting the Best Package for Your ASIC Design ................... 1-127

Section 2 - UHB Series CMOS Gate Array Unit Cell library
Section 3 - CG10 Series CMOS Gate Array Unit Cell library
Section 4 - Sales Information
Fujitsu Limited (Japan) ................................................... 10-3
Fujitsu Microelectronics, Inc. (U.S.A.) ........................................ 10-4
Fujitsu Electronic Devices Europe ........................................... 10-6
Fujitsu Microelectronics Asia PTE Ltd. (Singapore) ............................. 10-8
Integrated Circuits Corporate Headquarters - Worldwide ......................... 10-9
FMI Sales Offices for North and South America . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
FMI Representatives - USA .............................................. 10-11
FMI Representatives - Canada. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
FMI Representatives - Mexico ............................................ 10-13
FMI Representatives - Puerto Rico ........................................ 10-13
FMI Distributors - USA .................................................. 10-14
FMI Distributors - Canada ............................................... 10-18
FMG Sales Offices for Europe ............................................ 10-19
FMG Distributors - Europe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
FMAP Sales Offices for Asia Australia ...................................... 10-22
FMAP Representatives - Asia ............................................ 10-23
FMAP Distributors - ASia, Australia and Oceanian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24

III

Illustrations

Figures
1-1.
1-2.
1-3.
1-4.
1-5.
1-6.
1-7.
1-8.
1-9.
3-1.
4-1.
4-2.
4-3.
4-4.
4-5.
5-1.
5-2.

5-3.
6-1.
6-1.
6-2.

6-3.
6-4.
6-5.

Page

Physical Construction of the Unit Cell NAND Gate .................................. 1-4
The Basic Cell .............................................................. 1-5
The Basic Cell Configured as a 2-lnput NAND Gate ................................. 1-5
Input Buffer (12B) ............................................................ 1-6
Output Buffer (02B) .......................................................... 1-6
Channeled Gate Array Chip Structure ............................................ 1-8
Channeliess Gate Array Chip Structure ........................................... 1-8
Equivalent Gate Count vs. Processing Speed. Fujitsu CMOS Gate Array Technologies .... 1-10
Equivalent Gate Count. Fujitsu CMOS ASIC Technology Families ..................... 1-11
Workstation Design Flow ..................................................... 1-75
Arrangement of Hierarchical Blocks ............................................ 1-83
Recommended Hierarchial Organization of UHB/CG10 Designs ...................... 1-83
SSO-Generated Noise ....................................................... 1-87
SSO Pin Assignments ....................................................... 1-89
Scan Circuit Configuration .................................................... 1-90
Delay Time vs. Loading Factor ................................................ 1-94
Delay Path Sample Circuit .................................................... 1-95
Factors Influencing Delay .................................................... 1-99
Quality Control Processes at Fujitsu ........................................... 1-102
Quality Control Processes at Fujitsu (Continued) ................................. 1-103
Distribution of Component Failure ............................................. 1-107
Example of Life Test Data on IC .............................................. 1-108
Acceleration Rate vs. Junction Temperature .................................... 1-109
DigitallC Failures and Corrective Actions ....................................... 1-111

Figures - Test Patterns Application Note
1.
2.
3.
4.

Iv

Determining a Successful Test Cycle Length ....................................
Determining Preferred Cycle Length ...........................................
Input-to-Input Skew ........................................................
Input-to-Output Skew .......................................................

1-123
1-123
1-124
1-125

Illustrations (Continued)

Figures - Packaging Infonnatlon Application Note
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.

Tables
5-1.
5-2.
5-3.
6-1a.
6-1b.
6-1c.
6-1d.
6-2.

6-3.
6-4.

Page

Package Size versus Pin Count .............................................. 1-129
Minimizing Interconnect Length ............................................... 1-130
Impact of Noise on Speed ................................................... 1-130
PLCC Package Construction (Front View) ...................................... 1-133
PLCC Lead Frame Construction (Top View) ..................................... 1-133
321-Pin Ceramic Pin Grid Array .............................................. 1-136
Staggered Pin Grid Array Routing ............................................. 1-137
Flatpack Configurations ..................................................... 1-138
Defect Caused by Difference in Thermal Coefficient of Expansion .................... 1-139
PLCC Package ........................................................... 1-140
Cross-Section of a Plastic Small-Outline J-Iead Package ........................... 1-140
Surface Mount PGA ................. , ............................. , ........ 1-141
Solder Pad Design for Surface Mount Pin Grid Arrays ............................. 1-141
CMOS Output Buffer Model (Totem Pole) ....................................... 1-145
I/O Model, CMOS Input ..................................................... 1-145
I/O Model, TTL Input ....................................................... 1-146
CMOS Basic Gate Structure: The Pull-up/Pull-down Network ....................... 1-146
CMOS Basic Gate Structure: The Transmission Gate .............................. 1-147
Electrical Model of Simultaneously Switching Outputs ............................. 1-148
Effect of SSO Noise on Thresholds ............................................ 1-149
Variation in Inductance, Resistance, and Capacitance as a Function of Pin Position ...... 1-151
Measured Pin Capacitance by Package Position ................................. 1-152
Self-inductance in a Circuit .................................................. 1-153
Causes of Crosstalk ........................................................ 1-154
Heat Flow through a Cavity-down Ceramic PGA with an Annular Fin Heat Sink ......... 1-157

Page
AC Parameters of Unit Cells .................................................. 1-96
NDI vs. CL* ............................................................... 1-97
Pre-Layout Delay Multipliers ................................................. 1-100
Sampling Plan for Engineering Testing: Endurance Test ............................ 1-106
Sampling Plan for Engineering Testing: Environmental and Mechanical Test ........... 1-107
Sampling Plan for Engineering Testing: Environmental and Mechanical Test (Optional) ... 1-108
Sampling Plan for Engineering Testing: Continuity Test ............................ 1-108
Determination of Coefficient ................................................. 1-112
Process Defects Analysis ................................................... 1-114
Relationship between Failure Causes and Analytical Test Methods ................... 1-115

v

Illustrations (Continued)

Tables (Continued)

6-5.
6-7.

6-6.
6-8.

Sampling Plan for Reliability Testing ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example of Electrical Testing .................................................
Example of Reliability Testing ................................................
Example of Electrical Criteria ................................................

Page

1-116
1-117
1-117
1-118

Tables - Packaging Information Application Note

1.
2.
3.
4.
5.
6.

vi

Considerations for Package Selection ..........................................
Package Material Characteristics .............................................
Fujitsu Package Types ......................................................
PGAs Available from Fujitsu .................................................
Comparison of Critical Features ..............................................
ASIC CMOS Package Types and their Characteristics .............................

1-128
1-132
1-134
1-135
1-142
1-144

Preface

Fujitsu Microelectronics introduced its first commercially available gate array, a bipolar chip called the
B200, in 1974 (Fujitsu had been making them for internal use since 1972). Over the years it has been so
popular that it is regarded as the world's most widely implemented gate array. Since that first array, Fujitsu
has produced over 9000 successful bipolar and CMOS custom designs.
Fujitsu designs are successful because they are implemented using the most advanced design verification
CAD systems available, allowing the production of chips with 90% cell utilization (more functional logic per
chip than the industry standard) and one of the highest performance records in the industry.
This data book provides you with information necessary to choose an application specific IC (ASIC) design using one of Fujitsu's advanced CMOS channeled gate array technologies (UHB and CG10). The
data book describes Fujitsu's CMOS channeled gate array technologies, explains the benefits and specifications applicable to each, and outlines the process by which logic and circuit designers create a chip.
Except where noted, the material presented in this data book is common to all of Fujitsu's CMOS channeled technologies. The device (unit cell) libraries for these channeled gate array technologies are included at the end of this volume. Another volume in this series provides the same information for Fujitsu's
channelless or sea-of-gates ASIC technologies.
Fujitsu has pioneered and maintained a technological lead in the production of bipolar as well as CMOS
ASIC devices; data books describing Fujitsu's other ASIC product families, as well as any other technical
or sales-related information, may be obtained from any Fujitsu Technical Resource Center or Sales Office
listed at the end of this book or by calling or writing Fujitsu Microelectronics Inc., 3545 North First Street,
San Jose, CA 94135-1804, (408) 922-9000.

vII

Fujitsu ASIC Products Listing
CMOS Channeled Gate Arrays Data Book
UHB serJes High Drive CMOS Gate Arrays - 1.5p., 0.9 ns typical delay
Deacrlptlon

Name

Device Part Number

336 Gales, 58 I/O
530 Gales, 64 I/O
830 Gales, 741/0
1,233 Gales. 88 110
1,724 Gales, 102 I/O
2,220 Gales, 115 I/O
3,066 Gales, 140 110
4,174 Gales, 155 110
6,000 Gales, 155 110
8,768 Gales, 188110
12,734 Gales, 220 I/O

C330UHB
C530UHB
C830UHB
C1200UHB
C1700UHB
C2200UHB
C3000UHB
C4100UHB
C6000UHB
C8700UHB
CI2000UHB

MB625xxx
MB624xxx
MB623xxx
MB622xxx
MB621 xxx
MB620xxx
MB606xxx
MB605xxx
MB604xxx
MB603xxx
MB602xxx

CG10 Series High Drive CMOS Gate Arrays - 0.8fJ., 0.5 ns tYPIC~'d~I,;
3,256 G8tas, 108 I/O
4,032 Gales, 123 110
5,072 Gales, 148 110
6,510 Gales, 1631/0
7,684 Gales, 163110
11,080 Gales, 188 110
14,720 Gales, 220 110

CMOS Channelless
AU series

. .•"',,.

>,.

9G10272
·CG1·0342
CG1:0492
CG10s72
CG10692
ci:hil103
CG10133

Gate~t;:~.Data Book

CN!9SSe~ Gat~lt;;~\
~~:~u
GaleS:j~8
vo
1 ........
s.i381/O
2O,81S( 155 I/O
31,500·
s, 178 VO
41,184 Gales, 220 VO
52,164 Gales, 257 I/O
75,140 Gales, 300 I/O
102,144 Gales, 332 I/O

1.2J,1. 0.6 ns typical

MBCG10272xxx
MBCG10342xxx
MBCG10492xxx
MBCG10572xxx
MBCG10692xxx
MBCG10l03xxx
MBCG10133xxx

detli~":t

g:~~~ir
C2OKAU'''''
CSOKAU
C40KAU
C50KAU
C75KAU
Cl00KAU

MB637xxx
MB636xxx
MB635xxx
MB634xxx
MB633xxx
MB632xxx
t.(IB631xxx
MB630xxx

CG21 SerIeS CMOS Series Gate Arrays - 0.8fJ., 370 ps typical delay
10,224 Gales, 1081/0
15,486 Gales, 1421/0
20,876 Gales, 1551/0
31,500 Gales, 1781/0
41,184 Gales, 220 I/O
52,164 Gales, 245 1/0
75,140 Gales, 284.1/0
102,144 Gales, 332 I/O

viii

CG21103
CG21153
CG21203
CG21303
CG21403
CG21503
CG21753
CG21104

MBCG21103xxx
MBCG21153xxx
MBCG21203xxx
MBCG21303xxx
MBCG21403xxx
MBCG21503xxx
MBCG21753xxx
MBCG21104xxx

Fujitsu ASIC Products Listing

(Continued)

BiCMOS Gate Arrays Data Book
BC Series BICMOS Gate Arrays - 1.5IlI1.41J, 0.65 ns typical delay
Description

Nama

Device Part Number

645 Gates, 52 I/O
1,218 Gates, 721/0
1,872 Gates, 96 I/O
3,240 Gates, 112 I/O

B0400
B0800
BOl200
B02oo0

MB211xxx
MB212xxx
MB213xxx
MB214xxx

BC-H Series BICMOS Gate Arrays -

1.0J.l/O.5~. OA5

ns typical delay

4,312 Gates, 96 I/O
8,160 Gates, 128 110
11,968 Gates, 160 I/O
16,720 Gates, 200 1/0
7,920 Gates, 200 VO with 40Kb RAM

BC4oo0H
BC8oo0H
BCl2000H
BOl6000H
B08040HM

MB221xxx
MB222xxx
MB223xxx
MB224xxx
MB228xxx

~t750
ETl500
ET3000
ET4500
ET2004M

~i~~tt""""

MB121Kxxx
MB123Kxxx
MB125Kxxx
MBl28Kxxx
MB1811191xxx
MB1821192xxx
MB1831193xxx

El0000H
E5005HM

MB147/157xxx
MBI481158xxx
MBI851195xxx

ECl Gate Arrays Data Book
ET Series ECl Gate Arrays -1.0~. 220 ps typical delay \
1,056 Gates, 64 I/O
2,112 Gates, 881/0
4,224 Gates, 120 110
6,160 Gates, 120 1Iq...
2,640 Gates, 120 liO')iilith 4$'Kb RAM
2,640 Gates, 136 I/o, wjlb9:2~RAM
3,969Gate~t~ I/o, wiiljA.6 KbRAM

H Series

EC(~'te A;~YS - 0.~~.100 ps typical delay

:::~~=::=~

4,928 Gates, 200 VO, with 5.1 Kb RAM

Ultra High Performance ECl Gate Arrays -

0.5~.

75 ps typical delay

128 Gates, 23 /I/O
32 Gates, 13
128 Gates 16 I/O

va

VH Series ECl Gate Arrays -

0.4~.

mJ

EI28H
E32
El28

MBI800
MBI700
MBI600

E30000VH
El0040VHM
El0160VHR
ETZSOOVH

MBI621172xxx
MBI651175xxx
MBI681178xxx
MBBG31262xx

80 ps typical delay

38,948 Gates, 300 VO
. 13,440 Gates, 290 I/o, 40Kb RAM
13,440 Gilles, 2941/0, 160Kb ROM
2,544 Gates, 104 110

CMOS Standard Cell Data Book
AU Series Standard Cells -

1.2~.

0.6 ns typical delay

AS Series Standard Cells - O.BIL. 370 ps typical delay

Ix

11

- - - - - - - - - - - - - - - - - - Section 1
Design Information

I Page
1-3

Chapter 1

1-13

Fujitsu CMOS Products
Data Sheet: UHB Series CMOS Gate Arrays

1-41

Data Sheet: CG 10 Series CMOS Gate Arrays

1-69

Chapter 2

Steps Toward Design

1-73

Chapter 3

Design Procedures

1-81

Chapter 4

Design Considerations

1-93

Chapter 5

Delay Estimation Principles

1-103

Chapter 6

Quality and Reliability

1-119

Chapter 7

Application Notes

1-121

Developing Test Patterns
that Work with the Physical Tester

1-127

Selecting the Best Package for Your ASIC Design

1-1

Design Information

1-2

CMOS Channeled Gate Arrays

CMOS Channeled Gate AtTars

Fujhsu CMOS Products

Chapter 1 - Fujitsu CMOS Products
Contents of This Chapter
1.1
1.2
1.3
1.4

Introduction
CMOS Technology for ASICs
CMOS Gate Array Structure
Fujitsu's CMOS Channeled Gate Array Technologies: CG10 and UHB Data Sheets

1.1 Introduction
This section of the data book gives an overview of CMOS technology and introduces the CMOS
channeled gate array technology families developed by Fujitsu to implement ASIC designs.
1.2 CMOS Technology for ASICs
ASICs (Application Specific Integrated Circuits) are large scale integrated circuits that provide customers
with made-to-order functions. These ICs implement the unique value designed into customer products by
producing custom semiconductor deSigns that allow customers to take advantage of perc~ived market
opportunities in a timely manner. The customized solutions offered by ASICs combine the power of
personalized electronics and the advantage of increased system efficiency.
CMOS technology has long been chosen for ASIC applications because of its low power and high density
characteristics. AdvanCing process technology and new production and fabrication techniques have now
allowed device speed to increase to the point where it is competitive with bipolar devices. Fujitsu
manufactures CMOS gate arrays with advanced silicon gate technology utilizing two-layer and three-layer
metal. This fabrication process yields parts that:
a. require very low power dissipation (typically less than 500 mW per channeled array)
b. operate at speeds equaling existing bipolar technologies
c. feature higher gate densities than competing bipolar devices
d. use a Single power supply of 5 volts or less
e. provide top-grade noise immunity and programmable logic levels compatible with TTL and CMOS
logic families
1.3 CMOS Gate Array Structure
Fujitsu CMOS gate arrays are configured in a matrix of basic cells in the center of the chip with
input/output (1/0) cells on the device periphery. One basic cell is equivalent to a two-input NAND gate and
is the physical building block used to construct the unit cells that perform specific logic functions. The
custom logic function is realized by interconnecting basic cells with double- or triple-layer metallization.
Fujitsu's CMOS gate array products are fabricated using a twin-tUb polysilicon process to produce
high-speed, high-density arrays consisting of 300 to 100,000 basic cells.
1.3.1 Process Technology
The process by which the gate array is manufactured varies somewhat among Fujitsu's CMOS
technologies; however, the following explanation provides a good model of how a basic cell is fabricated

1-3

CMOS Channeled Gate Arrays

Fujitsu CMOS Products

in any of the CMOS families. The basic cell is constructed from an N-type silicon substrate upon which a
P-well is deposited. The surface of the substrate is then covered with a thin layer of silicon dioxide (glass)
and two strips of polysilicon are deposited perpendicular to the P-well and geometrically parallel.
(Polysilicon is a silicon-based compound chemically altered so that it has good electrical conduction
properties.) The polysilicon strips serve as the gate control elements of the basic cell and also as the two
electrical interconnections between the sources of the P and N transistor pairs. See Figure 1-1.
INPUT

INPUT

OUTPUT

Figure 1-1. Physical Construction ofthe Unit Cell NAND Gate
The silicon dioxide layer is then stripped away from all areas of the substrate not protected by polysilicon.
In two separate steps. the N-type and the P-type material of the twin tubs is diffused onto the substrate.
For the next step. N-type material is diffused or implanted into the P-well that was previously laid down. It
straddles the two strips of polysilicon close to their ends. The polysilicon resists the diffusion. which
results in the formation of three pads of N-type material separated by the two strips of polysilicon
(self-aligned processing). The center pad of N-type material serves as a common drain terminal for both
N-channel transistors. The outer pads are the separate source elements.
Then the P-type material is depoSited on the N-type substrate straddling the two polysilicon strips.
Similarly the center pad of P-type material forms the common source connection for both P-channel
transistors. Figure 1-2 diagrams the structure of a basic cell before the custom metallization is applied.
The basic cell is then converted to a unit cell by application of a custom metallization pattern that connects
(or wires) various points of the basic cell. or a number of basic cells. together. Figure 1-3 diagrams the
stl'\lcture of a basic cell configured as a NAND gate after metallization (represented by the solid bold line
connections) has been laid down.

1-4

CMOS Channeled Gate Arrays

Fujitsu CMOS Products

Some unit cells require two or even three layers of metal to be applied. Such layers are separated by an
insulating layer of silicon dioxide. Interconnections between the metal layers are made by means of "vias"
passing through the glass.
1.3.2 The Basic Cell
The basic cell of Fujitsu's CMOS gate array is a common building block consisting of one pair of
P-channel and one pair of N-channel MOS transistors interconnected as shown in Figure 1-2.

Figure 1-2. The Basic Cell
Since this is a "generic" basic cell, no connections are shown to the power supply (+5 volts). to ground, or
to the two common control gate terminals of the circuit. These connections are made as required during
the metallization phase of the manufacturing process. All CMOS gate arrays are built up of basic cells.
Figure 1-3 shows a schematic representation of the basic cell with the addition of the custom
metallization required to convert the generic basic cell into a 2-input NAND gate.
F

Output

A

Input

B

Input

Figure 1-3. The Basic Cell Configured as a 2-lnput NAND Gate

1-5

CMOS Channeled Gate Arrays

Fujitsu CMOS Products

1.3.3 Basic Cell Arrangement

Basic cells can be arranged as:
a. Fundamental logic function units called unit cells (for example, NAND gates, flip-flops, etc.).
b. User macros, which are composed of unit cells to form higher level logic block functions (e.g., shift
register or decoder). Such blocks are user-defined and may contain any unit cell configuration.
c. SuperMacros, which are very high level organizations performing complex functions such as ALUs
and progammable timers, as well as CRT, SCSI, and Ethernet controllers.
1.3.4 I/O Cells

110 cells are a specially configured type of unit cells which serve as input/output buffer cells and are
located on the periphery of the basic cell matrix. 1/0 cells are usually not included in the basic cell count.
These buffer cells convert external voltage levels into internal CMOS levels. The output buffers provide a
sufficient voltage level to drive TTL components but the input buffers must convert TTL levels to CMOS
levels when appropriate. Figure 1-4 shows the structure of a typical input buffer (12B) and Figure 1-5
shows the structure of a typical output buffer (02B).

PAD

EXTERNALVO

INTERNAL I/O

PROTECTION
CIRCUIT

X

)

A

...-

X

A

~t

IN

Figure 1-4. Input Buffer (12B)

INTERNALVO

EXTERNAL I/O

A

Figure 1-5. Output Buffer (02B)

1-6

PAD

X

Fujitsu CMOS Products

CMOS Channeled Gate Arrays

1.3.5 User Macros
Different user macros are available for each technology group. For a list of available user macros for each
technology, contact any of the Fujitsu Technical Resource Centers listed in the back of this volume.

1.3.6 Supermacro Implementations for CMOS ASIC
Fujitsu's next step upward in ASIC functionalHy is embodied in the concept of SuperMacros. SuperMacros
are large functional organizations implemented as an integral part of a chip. SuperMacros can be
large-scale compiled cells or core cells, as well as generic or proprietary LSI functions. Reduction of board
space, reduction of cost, and reduction of design cycle time, as well as extended functionality, reliability,
performance, and security of design are all advantages of SuperMacros. Since SuperMacros are not
bound to a particular CMOS technology, they may be migrated from one CMOS technology to another.
Fujitsu provides customers with gate and behavioral level models, macro symbols, and data
sheets/specifications as well as kit parts in order to provide complete support from development to system
integration. The SuperMacros listed in Table 1-1 below are the first to be developed for Fujitsu's CMOS
supermacro library.
Table 1-1. Fujitsu Supermacros
Compatible Device

Technology

Universal Synchronous/Asynchronous
ReceiverITransmitter (USARl)

Function

Gate Complexity

8251A

UHB/AU/CG10/21

2900

Universal Asynchronous ReceiverITransmitter (UART)

8868

UHB/AUlCG10121

608

Programmable Intervallimer

8253

UHB/AUlCG1 0121

5680

Programmable Peripheral Interface

8255A

UHB/AUlCG10121

785-1403 1

Programmable Interrupt Controller

8259A

UHB/AUlCG10121

2205

Programmable DMA Controller

8237

UHB/AU/CG10121

5100

Clock Generator/Driver

8284

UHB/AUlCG10121

99

Bus Controller

8288

UHB/AUlCG10121

250

Programmable Intervallimer

8254

UHB/AUlCG10121

3500

CRT Controller

6845

UHB/AUlCG10121

2843

SCSI Protocol Controller'!

87030

UHB/AUlCG10121

3630

EtherNet Controller'!

87012

UHB/AUlCG10121

4233

First In First Out (FIFO)

N/A3

UHB/AUlCG10121

360

4-bit Arithmetic Logic Unit (ALU) Slice

2901

UHB/AUlCG10121

917

Carry Lookahead

2902

UHB/AU/CG10121

33

Status and Shift Control

2904

UHB/AUlCG1 0121

449

4-bit Microprogram Sequencer

2909

UHB/AUlCG10121

428

2910

UHB/AUlCG10121

1682

12-bit Microprogram Controller
lSeveral options are available (Mode 0 IS 785 gates)
2Full-featured Fujitsu proprietary supermacro
3Na! Applicable

1-7

CMOS Channeled Gate Arrays

Fujitsu CMOS Products

1.3.7 Structure of the Chip

The arrangement of the basic cells on the chip differs according to the technology. The fundamental chip
layout is a matrix of basic cells surrounded by a perimeter 01 I/O cells. Basic cells are arranged in double
columns in the UHB and CG1 0 technologies (Figure 1-6). The channelless or sea-ol-gates technologies
are constructed with no wiring channels between the double columns, allowing the wiring to go over the
cells, rather than between the cells (Figure 1-7). The channelless technologies are covered in a separate
data book.

CI CI

Basic Cell (Double Column)
".c..................................... mil mil mil

11

n

m

.

a

n

ClCI·:I.: ..................................... mIImII

/

Typical UHB Chip Layout,
Double Column Structure

External 1/0

Figure 1-6. Channeled Gate Array Chip Structure
Basic Cell (Double Columllt

/---------

I

- ~r:: t;:
I
I
I
I
I
I
I
I

rr1.1
Extemal 110 '

~: ~
I
I
I

I
I

I
I

I
I

I I

::;:;
... -;

--------

I
I

I
I
I
I
I
I
I
I

··············
···•
··········· -------- ··,
.. ·· r···············
····-------- ·
I

I

I
I

I

I

I

I

;-

IJ

Typical Channelless Gate Array Chip Layout,
Double Column Structure with No Wiring Channels

Figure 1-7. Channelless Gate Array Chip Structure

1-8

CMOS Channeled Gate Arrays

Fujitsu CMOS Products

1.4 Fujitsu's CMOS Channeled Gate Array Technologies
Fujitsu offers over 30 different CMOS gate array devices, fabricated with advanced silicon gate
technology. Fujitsu's channeled CMOS gate arrays include the technology options described in detail in
the data sheets that follow:
•

UHB Series CMOS Gate Arrays

•

CG10 Series CMOS Gate Arrays

Complete information on Fujitsu's channelless (sea-ol-gates) CMOS gate array families is provided in a
separate data book.
All offer the same fast turnaround on design, simplified customer interface, full support by Fujitsu
ViewCAD system design software if requested, full design support on other major CAE workstations, and
a wide variety of packaging options.
The number of gates in relationship to the processing speed of each new CMOS technology is shown in
Figure 1-8. Figure 1-9 shows in tabular form the equivalent gate count for each CMOS technology family.

1-9

Fujitsu CMOS Products

CMOS Channeled Gats A"ays

Gate Delay
(In nslgate)
~--~--------------------------------------------------------,500K

10~------------------------------------------~~-----------------;100K

r---------------------------~~--,.~----------~~~----------_;10K

1980

Gate Length
(in microns)

1985
Year of Production
Start

1990

1K

1992

Gate Count
(Gates/Chip)

• = Gate Count
= Gate Length (In microns)
• = Gate Delay (in nslgate)

o

Figure 1-8. Equivalent Gate Count vs. Processing Speed, FujHsu CMOS Gate Array Technologies

1-10

Fujitsu CMOS Products

CMOS Channeled Gate Arrays

Increasing Gate
Count
'7

~"", C-100KAU

100K

,';,

I~I

""~' C-7SKAU
III~II
"~'" C-SOKAU
::,,'::: C-4OKAU
:::::: C-30KAU
,"/' C-20KAU
C-1SKAU

7SK

IIII ~

SOK
40K
30K
20K
1SK
12K

: : ~:

~

:::1:::::
IIIIII11

l

10K
SK

:::~:

C-12000UHB

~:
,~"

.t. C-10KAU
C-a700UHB

'~,,~,'
1-" C-6000UHB

6K
SK

~::

II~I C-4100UHB

~::
~~I
I~:

4K
3K

II ~I

C-3000UHB

~~:/",/' C-2200UHB

2K

l
,~
I~
~,/,

C-1700UHB

~

C-1200UHB

~

C-630UHB

1K

/"".

800

II~

~ C-530UHB

I~

SOO

~ C-330UHB

300

L...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _• •

UHB Version
0.9 nslgate

CG10 Version
O.S nslgale

AU Version
O.S nslgale
(Sea of Gates)

Increasing Speed

CG21 Version
0.37 nslgate
(Sea of Gates)

·planned
Figure 1-9. Equivalent Gate Count, Fujitsu CMOS ASIC Technology Families

1-11

Fujitsu CMOS Products

1-12

CMOS Channeled Gate Arrays

cO

September 1988
Edition 1.1
PRODUCT PROFILE

FUJITSU

UHB Series 1.5-micron CMOS Gate Arrays
DESCRIPTION
The UHB series of 1.S-micron CMOS gate arrays is a highly integrated low-power, ultra high-speed product family that derives ~s
enhanced performance and increased user flexibility from the use of a system-proven, dual-column gate structure and 2-layer
metal interconnect technology. The unique dual-column gate structure increases density and speed performance, as well as gate
utilization.
Internal high-drive clock buffers minimize clock skew across the chip while internal bus performance and integrity is assured by
incorporating 3-state transmission gate logic underneath the routing channels. The high-drive output buffers provide highly
symmetrical output waveforms.

FEATURES
•

High·dens~y silicon gate CMOS technology
- 330 to 12,000 usable gates
- 90% maximum utilization fully autorouted

•

Uttra high speed
- typical 0.9 ns gate delay
- narrow delay variation
High sink current capabil~y
- 3.2 mA, 8 mA, 12 mA, and 24 mA options available
- selectable edge rate control

•

•

•

Low-skew clock signal distribution
- High-performance clock drivers
- Hierarchical clock distribution
- Frequency·dependent clock routing

•
•

2·column gate structure that enhances macro
performance
High-performance internal 3-state bus
- buried cells w~hin the routing channels ensure
high density and reliable performance

•
•

Proven 1.5-micron 2-layer metal technology
Highest pin-toil ate count commercially available
- 60 logic 1/0 for 336 gates
- 222 logic I/O for 1200 gates

•
•

Input buffers w~h pull-up/pull-down resistance
Built-in feedback resistors for oscillators

•

User-defined hierarchy-driven placement

Automatic test pattern generation for 6K gates and up
- complete family of scan design macros available
Device Name

Utilizable Gates 1

Maximum
Signal Plns 2

336 gates
530 gates
830 gates

60

C-1700UHB
C-2200UHB
C...,'l()QOUHB

1233 gates
1724 gates
2220 gates

92
108
123

3066 gates

C-4100UHB
C-6OOOUHB

4t74 gates
6000 gates

148
163
163

C-330UH8
C-530UHB
C-830UHB
C-1200UHB

66

76

C-a700UHB

8768 gates

188

C-12000UHB

12734 gates

220

Gates available for logic (exclusive of I/O usage).
'Maximum signal pin numbers depend on the output drive
requirements and the package selected.

Copyright@ 1990 FWITSU LIMITED and Fujhsu Microelectronics. Inc.

1-13

UHB Series CMOS Gate Arrays
PRODUCT FAMILY DESCRIPTIONS1
Device Name

Part Number

2-lnput Gate Equivalent
Complexity

Maximum Signal Plns2

Total Number of Basic
Cells on Chlp304

C-330UHB

MB625xxx

336 gates

60

610 gates

C-530UHB

MB624xxx

530 gates

66

840 gates

C-830UHB

MB623xxx

830 gates

76

1176 gates

C-1200UHB

MB622xxx

1233 gates

92

1680 gates
2232 gates

C-1700UHB

MB621 xxx

1724 gates

108

C-2200UHB

MB620xxx

2220 gates

123

2800 gates

C-3000UHB

MB606xxx

3066 gates

148

3744 gates

C-4100UHB

MB605xxx

4174 gates

163

4888 gates

C-6000UHB

MB604xxx

6000 gates

163

6976 gates

C-8700UHB

MB603xxx

8768 gates

188

9720 gates

C-12000UHB

MB602xxx

12734 gates

220

13728 gates

Notes: 1Typical device gate speed, with FlO = 2, for a 2-input NAND gate, is 0.9 ns.
2'fhe maximum signal pin numbers depend on the output drive requirements and the package selection.
3A basic cell is equivalent to a 2-input gate.
4Basic cells on chip are also used for 110 buffer function.

AC CHARACTERISTICS
BESTIWORST CASE MULTIPLIERS FOR PROPAGATION DELAYS
Propagation delays characteristic of a gate array are a function of several factors, including operating temperature, supply voltage,
fanout loading, interconnection routing metal, process variation, input transition time, and input signal polarity. Temperature and
supply voltage factors affecting propagation delays in the UHB CMOS family of gate arrays are given in the table below.
Pre-Layout Simulation
Temperature
Range

VDo = 5 V ±5O/.

Post-Layout Simulation

VDO =5V±10%

VDo =5V±5%

VDO =5V±10%

Best Case

Worst Case

Best Case

Worst Case

Best Case

Worst Case

Best Case

Worst Case

0-70 0 C1

0.35

1.65

0.30

1.75

0.40

1.60

0.35

1.70

-20-70°C

0.35

1.65

0.25

1.75

0.35

1.60

0.30

1.70

-40-70°C

0.25

1.65

0.20

1.75

0.30

1.60

0.25

1.70

-40-85°C2

0.25

1.75

0.20

1.85

0.30

1.70

0.25

1.80

Notes: 1Commercial temperature range
21ndustrial temperature range

1-14

UHB Series CMOS Gate Arrays
REPRESENTATIVE PROPAGATION DELAYS
Constants for calculating the delays due to process variation, fanout loading, interconnection routing metal, transition time, and signal
polarity are given for each unit cell in the UHB Unit Cell library. Delays using these factors are calculated for a representative selection
of unit cells and are shown in the Propagation Delays tables below.
Calculations are representative of unit cells in the C12000UHB (UHB 12000-Gate CMOS gate array).
Typical values are indicated. Worst case multipliers are applied to typical values. Smaller arrays can exhibit significantly greater
speed.
Propagation Delays (in ns)
Unit Cell
Function

Unit Cell
Name

Equivalent
Gate Count

Input
Transition

NO! (Fan-out)
1

2

8

4

16

32

Inverter

V1N

1

tplH
tpHl

0.86
0.67

1.51
1.04

2.36
1.52

3.53
2.18

5.19
3.11

8.09
4.74

Power 2-lnput NAND

N2K

2

tplH
tpHl

0.66
0.68

.99
.97

1.41
1.34

1.99
1.85

2.83
2.58

4.27
3.85

Power 16-lnput NAND

NGB

11

tplH
tPHL

1.82
3.69

2.15
3.93

2.57
4.25

3.15
4.69

3.99
5.31

5.43
6.40

Power 2-lnput NOR

R2K

2

tplH
tpHl

0.95
0.67

1.53
0.91

2.27
1.23

3,29
1.67

4.75
2.29

7.28
3.38

Power Exclusive OR

X2B

4

tplH
tpHl

1.72
1.82

2.05
2.03

2.47
2.29

3.05
2.66

3.89
3.18

5.33
4.08

3-wide 2-AND 6-lnput

036

3

tpLH
tpHl

1.78
1.22

2.93
1.80

4.41
2.54

6.45
3.56

9.37
5.02

4.43
7.55

G24

2

tplH
tpHL

1.54
1.20

2.73
1.78

4.27
2.52

6.39
3.54

9.40
5.00

14.65
7.53

T28

11

tplH
tpHL

2.41
1.66

2.74
1.83

3.16
2.04

3.74
2.33

4.58
2.75

6.02
3.47

Power Clock Buffer

K2B

3

tplH
tpHl

1.30
1.38

1.57
1.58

1.90
1.83

2.30
2.13

2.81
2.51

3.61
3.11

Scan 8-bit 0 Flip-flop with
Clock Inhibit and 3:1

SHK

88

tpLH
tpHL

5.22
4.92

5.87
5.29

6.72
5.77

7.89
6.43

9.55
7.36

12.45
8.99

FDO

7

tpLH
tpHl

2.51
2.14

3.16
2.55

4.01
3.08

5.18
3.81

6.84
4.85

9.74
6.66

FD5

8

tplH
tpHl

2.17
1.89

2.50
2.10

2.92
2.36

3.50
2.73

4.34
3.25

5.78
4.15

C43

48

tplH
tpHL

2.18
1.10

2.83
1.43

3.68
1.85

4.85
2.43

6.51
3.27

9.41
4.71

C45

48

tplH
tpHl

2.52
1.68

3.22
2.05

4.12
2.53

5.36
3.19

7.13
4.12

10.21
5.75

AND-OR Inverter (A -+ Y)
2-wide 2-OR 4-input
OR-AND-Inverter (A -+ X)
Power 2-AND 8-Wide
Muttiplexer (A -+ X)

Data Muttiplexer (CK,IH -+ 0)
Non-Scan 0 Flip-flop
with Reset (CK -+ 0)
Non-Scan Power 0 Flip-flop
with Clear (CK -+ 0)
Non-Scan 4-bit Binary
Synchronous Up
Counter (CI -+ CO)
Non-Scan 4-bit Binary
Synchronous Up
Counter (CI -+ CO)
Note: Delays for inter-block wiring are not included
Conffnued on next page

1-15

UHB Series CMOS Gate Arrays
REPRESENTATIVE PROPAGATION DELAYS (Continued)
Propagation Delays (In ns)
Unit Cell
Function

Unit Cell
Name

Equivalent
Gate Count

Input
TransHlon
1

Non-Scan 4-bit Binary
Synchronous UplDown

NIlI (Fan-out)
4
8

2

16

32

047

68

IpLH
IpHL

2.87
3.30

3.32
3.63

3.90
4.05

4.70
4.63

5.85
5.47

7.84
6.91

MH

48

tpLH
IpHL

1.97
2.13

2.87
2.71

4.04
3.45

5.65
4.47

7.93
5.93

11.92
8.46

T5A

5

11.79

Counter (DU -+ CO)
4-bit Binary Full Adder
with Fast Carry (CI-+ 51)
4:1 Selector (55 -+ X)

tpLH

1.39

2.33

3.55

5.23

7.62

IpHL

1.12

1.77

2.62

3.79

5.45

8.35

4-bit Shift Register with
Synchronous Load

FS2

30

tpLH
tpHL

2.90
3.46

3.55
3.83

4.40
4.31

5.57
4.97

7.23
5.90

10.13
7.53

9-bit Odd Parity
Generator/Checker

P09

22

tpLH
tpHL

5.78
6.00

6.43
6.33

7.28
6.75

8.45
7.33

10.11
8.17

13.01
9.61

4-wide 2:1 Data

P24

12

tpLH
tpHL

1.24
0.97

1.57
1.14

1.99
1.35

2.57
1.64

3.41
2.06

4.85
2.78

MC4

42

tpLH
tpHL

3.17
2.60

4.36
2.93

5.90
3.35

8.02
3.93

11.03

4.n

16.28
6.21

~41

9

tpLH
tpHL

1.99

2.48

3.05

3.76

1.87

2.29

2.78

3.39

4.64
4.14

6.04
5.34

Selector (A -+ X)
4-bit Magnitude
Comparator (IS -+ OG)
4-bit Bus Driver (A -+ X)
Input Buffer (Inverter)

11B

5

tpLH
tpHL

1.84
1.78

2.11
2.05

2.44
2.38

2.84
2.78

3.35
3.29

4.15
4.09

Clock Input Buffer
(Inverter)

IKB

4

tpLH
tpHL

2.49
1.94

2.63
2.08

2.79
2.24

2.99
2.44

3.24
2.69

3.64
3.09

Unit Cell
Name

Equivalent
Gate Count

Input
TransHion

1/0 Cell
Function

Output Buffer Load In pF
25

200

028

2

IpLH
IpHL

2.37
3.24

3.10
4.85

4.50
7.95

7.30
14.15

12.90
26.55

24.10
51.35

Power Output Buffer
(True)

02L

2

tpLH
tpHL

2.53
2.47

3.02
3.01

3.94
4.03

5.79
6.08

9.49
10.18

16.89
18.38

3-State Output Buffer
(True)

04T

4

tpLH
tpHL

3.09
4.08

3.82

5.n

5.22
9.02

8.02
15.52

13.62
28.52

24.82
54.52

Power 3-State Output
Buffer (True)

04W

IpLH
tpHL

3.48
4.68

4.92
6.47

6.82
8.82

10.62
13.52

18.22
22.92

3-State Output and
Input Buffer (True)

H6T

8

IpLH
IpHL

3.09
4.08

5.n

3.82

5.22
9.02

8.02
15.57

13.62
28.52

24.82
54.52

Power 3-State Output
and Input Buffer (True)

H6W

8

tpLH
tpHL

3.48
4.68

3.97
5.30

4.92
6.47

6.82
8.82

10.62
13.52

18.22
22.92

4

Note: Delays for inter-block wiring are not included

1-16

3197
5.30

50

400

100

Output Buffer (True)

12

UHB Series CMOS Gate Arrays
DC CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS'
Symbol

Rating
Supply Voltage
Input Voltage
Output Voltage

Minimum

10l=BmA

Unit

VSS - 0.52

6.0

V

VI

VSS - 0.52

Voo +0.5

V

Vo

VSS - 0.52

Voo +0.5

V

1m = 3.2mA
Output Current3

Maximum

Voo

-40
-40

los

IOl= 12 mA

-60

10l = 24 mA

-90

mA

Storage Temperature

Ceramic
Plastic

-65
-40

+150
+125

5C

TSIg

Temperature Under Bias

Ceramic
Plastic

-40
-25

+125
+B5

5C

Tbias

..

Notes: 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be
restricted to the oonditions as detailed in the operation sections of the data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2Vss = 0 V.
30nly one output at a time may be shorted for more than one second.

RECOMMENDED OPERATING CONDITIONS
Symbol

Minimum

Typical

Maximum

Supply Voltage

Parameter

Voo

4.75

5.0

5.25

Unit
V

Input High Voltage for TTL Input

VIH

2.2

-

V

Input Low Voltage for TTL Input

V il

-

-

0.8

V

Input High Voltage for CMOS Input

VIH

Voo x 0.7

-

-

V

Input Low Voltage for CMOS Input

V il

-

-

Voox 0.3

V

Operating Temperature

TA

0

-

70

°C

Typical

Maximum

Unit

16

pF

16

pF

CAPACITANCE (TA = 2SoC. VDD = VI = 0 V. f =
Parameter

Symbol

1 MHz)
Minimum

Output Pin Capacitance
(l0l - 3.2 mAo 8 mAo or 12 mAl

COUT

-

Output Pin Capacitance
(lot. -24mA)

COUT

-

18

pF

I/O Pin Capacitance
(lot. -3.2 mAo 8 mAo or 12 mAl

ClIO

-

16

pF

I/O Pin Capacitance
(l0l-24mA)

Coo

-

23

pF

Input Pin Capacitance

C IN

1-17

UHB Series CMOS Gate Arrays
DC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Symbol

Condition

Minimum

1\'plcal

Maximum

Unit

Power Supply Current

loos

Steady State 1

0

-

100

~

Output High Voltage
for Normal Output (101.. - 3.2 rnA)

VOH

IQHm-2 rnA

4.0

-

Vee

V

Output High Voltage
for Driver Output (loL =.8 rnA)

VOH

IOH s-2 rnA

4.0

-

Veo

V

Output High Voltagefor Driver Output
(IoL -12 rnA)

VOH

IOH =-4mA

4.0

-

Veo

V

Output High Voltage
for Driver Output (101.. =24 rnA)

VOH

IOH

~-8mA

4.0

-

Voo

V

Output Low Voltage2
for Normal Output (IOL = 3.2 rnA)

VOL

IOL m3.2mA

Vss

-

0.4

V

Output Low Voltage
for Driver Output (loL = 8 rnA)

VOL

IOL=8mA

Vss

-

0.4

V

Output Low Voltage2
for Driver Output (IoL - 12 rnA)

VOL

IOL= 12 rnA

Vss

-

0.4

V

Output Low Voltage2
for Driver Output (loL = 24 rnA)

VOL

10L- 24 rnA

Vss

-

0.5

V

Input High Voltage
for TIL Input

V'H

-

2.2

-

-

V

Input Low Voltage
for TIL Input

V'L

-

-

-

0.8

V

Input High Voltage
for CMOS Input

V'H

-

Veo x 0.7

-

-

V

Input Low Voltage
for CMOS Input

V'L

-

-

-

Voox 0.3

V

-

2.5
0.7
1.1

3.3
1.4
1.9

4.0
2.0
2.7

V

1.4
0.8
0.4

1.9
1.3
0.6

2.5
1.8
0.7

V
V
V

25

50

100

ill

-

10

~

10

~

Parameter

Input3

Schmitt Trigger CMOS
Positive-going Threshold
Negative-going Threshold
Hysteresis

Vr•
Vr_
Vr.-Vr

Schmitt Trigger TTL Input3
Posnive-going Threshold
Negative-going Threshold
Hysteresis

Vr•
Vr_
Vr.-Vr

Input Puil-uplPuil-down Resistor

Rp

-

V'L to V'H. V'H. to V'L
V'H to Veo
V'L to Vss

Input Leakage Current

III

V,=O-Veo

-10

Input Leakage Current (3-state)

ILZ

V,=O-Voo

-10

Notes: lV'N = Veo. V'L = Vss
2With certain restrictions on pin assignment
3These values for reference only

1-18

V'L to V'H. V'H. to V'L

V
V

UHB Series CMOS Gate Arrays
ARRAY ARCHITECTURE
The typical UHB chip is composed of double columns of CMOS gates (basic cells) separated by dedicated wiring channels. Abasiccell
consists of a pair of N-channel and a pair of P-channeltransistors interconnected by polysilicon gate control terminals. Groups of basic
cells are interconnected by custom metallization into unit cells. Fujitsu unit cells provide a wide range of standard logic functions such
as exclusive OR gates, flip-flops, buffers, and counters. The UHB Series CMOS gate array family includesover250different unit cells.
These unit cells are the building blocks from which complex designs are constructed.
The spaces between the double columns of basic cells are occupied by channels for custom metallization. Nearly half of these wiring
channels contain transmission gates that implement internal3-state buses. Bus terminators located althe ends olthe double columns
of cells maintain the last value to be sent through the bus to ensure proper operation under all condHions.
The I/O cells around the perimeter of the matrix of cells are composed of internal cells wHh input protection networks and the potential
to be configured as input buffers, clock input buffers, output buffers, power output buffers, or bidirectional buffers.

Ell_ •••••.••.••.•.••••.••..•..••.•.•..••.•.• 1illlI1illlI1illlI
--~IU~,

D

I

tI>--

4

D

2 --+--EBiH

5

~
•

j

d

3---H.U~

'. 1illlI1illlI1illlI •• • •• • ••••••••••••••••••••••••••••••••••

6

m

m
_mm m

Typical Chip Layout, Double Column Structure

1.
2.
3.
4_
5_
6_

Dedicated Clock Network - for high frequency clocks
3-state Bus Logic -located in wiring channels
Bus Terminators - prevent floating state on buses
Driver Transistors and 110 Protection Networks - provide high I/O count
Double Columns - for optional macro utilization and speed
Wiring Channel Area - for metallization between unit cells

1-19

UHB Series CMOS Gate Arrays
DESIGN COMPONENTS
DESIGNING WITH THE UHB PRODUCT FAMILY
To implement logic functions, you build up the elements of the circuit from unit cells. Simple unit cells are used hierarchically to build
higher level functions until the logic is completely defined. Fujitsu offers acomplete line of standard logic functions inthe unit cell library.
Super macros are used to implement large super-cell functions such as expandable ALUs and multipliers.

1/0 BUFFERS
Each UHB 110 buffer around the perimeter of the array consists of an input protection network and large N-channel and P-channel
transistors capable of supplying the standard 3.2-mA, S-mA, and 12-mA output currents. Two of these large transistor pairs may be
connected in parallel, using high-output-current macros, to obtain 24-mA drive. One of the 110 pads whose output transistors have
been used for the 24-mA high-current option may still be used as an input.
Input 110 buffers convert external TTL levels to internal CMOS levels or may receive CMOS level signals directly. Output 110 buffers are
totem pole and may drive either CMOS and TTL levels, depending on their AC and DC loads. Any of the pins except the dedicated
power and ground pads can be designed to be an input buffer, an input buffer with pull-uplpull-down resistance, a clock input buffer, an
output buffer, a high-drive output buffer, an output buffer with noise limiting resistance, a 3-state output buffer, a bi-directional buffer, or
a Schmitt trigger Input buffer. There are some restrictions on the location of 24-mA buffers.

INPUT CLOCK DRIVERS
The large output 1/0 transistor pair is used in a high-drive input clock driver for high fanout applications within the array. This allows you
\0 fully utilize the high speed capabilities of the UHB technology.

TESTING UHB DEVICES
Two options are availablefortesting UHB designs: (1) the standard designer-supplied test patterns and test vectors (in Fujitsu's FTDL
format) and (2) the use of scan cells combined with Automatic Test Generation (ATG) performed by Fujitsu computers for additional
diagnostic test patterns. H you have designed with scan cells and other scan logic elements, Fujitsu will complete the scan test
program generation.
Regardless of the selected test option, you need to furnish Fujitsu with enough test patterns to guarantee that the submitted design
completely performs its intended logic functions. These patterns include the test function of each 110 pin.

Dlagramatlc Representation of Design Structure for ScanTesting

1-20

UHB Series CMOS Gate Arrays
Vee and Vss REQUIREMENTS
Each UHB Series gate array device has two options for each package type, both supporting a different number of power and
ground pins. The number of power and ground pins required depends on the number of simuttaneously switching outputs used in
the design. Simuttaneously switching outputs (SSOs) are output signals that change from H to L or L to H or from Z to H or Z to L
within a 20-ns window (including possible skew).
Muttiple outputs that switch althe same time can cause noise on Voo and Vss lines and affect the performance of a device:Therefore,
to achieve maximum reliability, Fujitsu limits the number of SSOs per Veo pin according to the table below. The maximum number of
SSOS per pin is determined by a representative value specifiedforthe driving capability of each type of output. The total representative
value of all SSOs used in a design must not exceed 80 per Vss pin. For example, 11 normaI3.2-mA outputs with edge rate control, four
12-mA outputs, or three 24-mA outputs per Vss pin may be SSOs.

Output Drive Type

Normal (3.2 rnA)

10

High Drive (12 rnA)

20

Normal (3.2 rnA) with
Edge Rate Control

..

Representative Value
per Output

7

High Drive (12 rnA)
with Edge Rate Control

14

High Drive (24 rnA)
with Edge Rate Control

26

1-21

UHB Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY
Note:

The load unn (Iu) is a normalized loading unn of capaenanee representing the input load of an inverter wnhout metal
interconnection.

Invener and Buffer Family
Basic Calls

Drive (Iu)

V1N

Inverter

1

18

Neg

V2B

Power Inverter

1

36

Neg

Description

UnltCaIl Name

Polarity

B1N

True Buffer

1

18

Pos

BD3

True Delay Buffer (> 5 ns)

5

18

Pos

BD4

Delay Cell (> 4 ns)

4

6

Pos

BD5

Delay Cell (>10 ns)

9

18

Pos

BD6

Delay Cell (>22 ns)

17

18

Pos

Clock Buffer Family
UnltCaIl Name

BasleCelis

Drive (Iu)

Polarity

K1B

True Clock Buffer

Description

2

36

Pos

K2B

Power Clock Buffer

3

55

Pos

K3B

Gated Clock (AND) Buffer

2

36

Pos

K4B

Gated Clock (OR) Buffer

2

36

Pos
Neg

KSB

Gated Clock (NAND) Buffer

3

36

KAB

Block Clock (OR) Buffer

3

55

Pos

KBB

Block Clock (OR x 10) Buffer

30

55

Pos

V1L

Double Power Inverter

2

55

Neg

NAND Family
UnltCaIl Name

Description

BasleCelis

Drive (Iu)

N2N

2-input NAND

1

18

N2B

Power 2-input NAND

3

36
36

N2K

Fast Power 2-input NAND

2

N3N

3-input NAND

2

14

N3B

Power 3-input NAND

3

36

N4N

4-input NAND

2

10

N4B

Power 4-input NAND

4

36

N6B

Power 6-input NAND

5

36

N8B

Power 8-input NAND

6

36

N9B

Power 9-input NAND

8

36

NCB

Power 12-input NAND

10

36

NGB

Power 16-input NAND

11

36

N3K

Fast Power 3-input NAND

3

28

N4K

Fast Power 4-input NAND

4

20
Convnued on next page

1-22

UHB Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued)
NOR Family
Description

Unit Cell Name

Drive (Iu)

Basic Cells

R2N

2-input NOR

1

14

R2B

Power 2-input NOR

3

36
36

R2K

Power 2-input NOR

2

R3N

3-input NOR

2

10

R3B

Power 3-input NOR

3

36
20

R3K

Power 3-input NOR

3

R4N

4-input NOR

2

6

R4B

Power 4-input NOR

4

36

R4K

Power 4-input NOR

4

12

R6B

Power 6-input NOR

5

36

RSB

Power S-input NOR

6

36

R9B

Power 9-input NOR

S

36

RCB

Power 12-input NOR

10

36

RGB

Power 16-input NOR

11

36

AND Family
Basic Cells

Drive (Iu)

N2P

Power 2-input AND

2

36

N3P

Power 3--input AND

3

36

N4P

Power 4-input AND

3

36

NSP

Power S-input AND

6

36

Basic Cells

Drive (Iu)

Unit Cell Name

Description

OR Family
Unit Cell Name

Description

R2P

Power 2-input OR

2

36

R3P

Power 3--input OR

3

36

R4P

Power 4-input OR

3

36

RSP

Power 8--input OR

6

36

Exclusive NOR/OR Family (EXOR/EXNOR)
Unit Cell Name

Basic Cells

Drive (Iu)

Polarity

X1N

Exclusive NOR

Description

3

1S

Neg

X1B

Power Exclusive NOR

4

36

Neg

X2N

Exclusive OR

3

14

Pos

X2B

Power Exclusive OR

4

36

Neg

X3N

3-input Exclusive NOR

5

14

Neg

X3B

Power 3--input Exclusive NOR

6

36

Neg

X4N

3--input Exclusive OR

5

14

Pos

X4B

Power 3--input Exclusive OR6

6

36

Pos

Con&nued on next page

1-23

UHB Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

(Continued)

AND·OR·lnverter Family (AOI)
Basic Cells

Drive (Iu)

D23

2-wide 2-AND 3-input AOI

2

14

D14

2-wide 3-AND 4-input AOI

2

14

D24

2-wide 2-AND 4-input AOI

2

14

D34

3-wide 2-AND 4-input AOI

2

10

D36

3-wide 2-AND 6-input AOI

3

10

Unit Cell Name

Description

2-wide 2-0R 2-AND 4-input AOI
D44
2
Note. AND-OR-Inverter Unit cells are uselulln Implementing sum-aI-products (SOP) expressions

10

OR·AND·lnverter Family (OAI)
Unit Cell Name

Basic Cells

Drive (Iu)

G23

2-wide 2-0R 3-input OAI

Description

2

18

G14

2-wide 3-0R 4-input OAI

2

10

G24

2-wide 2-0R 4-input OAI

2

10

G34

3-wide 2-0R 4-input OAI

2

10

G44

2-wide 2-AND 2-0R 4-input OAI

2

14

Note: OR-AND-Inverter Unit cells are uselulln Implementing product-aI-sums (POS) expressions.
Multiplexer Family
Unit Cell Name Type

Description

Basic Cells

Drive (Iu)

Function

T24'

4:1

Power 2-AND 4-wide Multiplexer

6

36

SOP

T26'

6:1

Power 2-AND 6-wide Multiplexer

10

36

SOP

T28'

8:1

Power 2-AND 8-wide Multiplexer

11

36

SOP

T32

2:1

Power 3-AND 2-wide Multiplexer

5

36

SOP

T33'

3:1

Power 3-AND 3-wide Multiplexer

8

36

SOP

T34'

4:1

Power 3-AND 4-wide Multiplexer

9

36

SOP

T42

2:1

Power 4-AND 2-wide Multiplexer

6

36

SOP

T43

3:1

Power 3-AND 3-wide Multiplexer

10

36

SOP

T44

4:1

Power 4-AND 4-wide Multiplexer

11

36

SOP

T54

4:1

Power 4-2-3-2 AND 4-wide Multiplexer

10

36

SOP

U24'

4:1

Power 2-0R 4-wide Multiplexer

6

36

POS

U26'

6:1

Power 2-0R 6-wide Multiplexer

9

36

POS

U28'

8:1

Power 2-0R 8-wide Multiplexer

11

36

POS

U32

2:1

Power 3-0R 2-wide Multiplexer

5

36

POS

U33'

3:1

Power 3-0R 3-wide Multiplexer

7

36

POS

U34'

4:1

Power 3-0R 4-wide

Mu~iplexer

9

36

POS

U42

2:1

Power 4-0R 2-wide

Mu~iplexer

6

36

POS

U43

3:1

Power 4-0R 3-wide Multiplexer

9

36

POS

U44
4:1
Power 4-0R 4-wide Multiplexer
\;onvenlent lor t yp leal mum pJleXer appJllcatlons

11

36

POS

Continued on next page

1-24

UHB Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

(Continued)

Data Selectors/MuHlplexers
Unit Cell
Name

Type

Description

Basic Cells

Drive (Iu)

Selects

Output

Bit
Width

P24'

2:1

Data Selector

12

36

S,XS

Q

4

T2E

2:1

Selector

5

18

S

XQ

2

T2F

2:1

Selector

8

18

S

XQ

4

T2B'

2:1

Selector

2

18

S,XS

XQ

1

T2C'

2:1

Selector

4

18

S,XS

XQ

2

T2D'

2:1

Selector

2

14

S,XS

XQ

1

T5A'

4:1

Selector

5

9

S,XS

XQ

1

V3A'

1:2

Selector

2

14

S,XS

XQ

1

..

S,XS
XQ
2
V3B'
Selector
4
14
1:2
..
, These are transmission gate devices whose outputs can be tied because they can be Inhlbaed wah truelinverted selects .

Decoders
Unit Cell
Name

Type

Description

Basic Cells

Drive (Iu)

Active Level
Outputs

DE2

2:4

Decoder

5

18

Low

DE3

3:8

Decoder

15

14

Low

DE4

2:4

Decoder

8

14

Low

Low

Low

1 High
2 Low

DE6

3:8

Decoder

30

18

Output

-

Internal Bus UnH Cells
Unit Cell Name
B41

I
I

Description
4-bit Bus Driver

I
I

Basic Cells

9

J

Drive (Iu)

I

36

I
1

Bus Size
4 bits

I Enable
L Low

Notes: 1The number of B41s used is limited by the chosen array series, as shown in the table below.
20 n-chip buses (managing more than one bus source and/or a bi-directional bus) may be implemented with either
muniplexer-type unit cells or bus drivers. While bus drivers impose certain design restrictions, the optimum choice is
dictated by the specHic design.
Device Name

Maximum B41s

C-330UHB

4

C-530UHB

5

C-830UHB

6

C-1200UHB

8

C-1700UHB

12

C-2200UHB

16

C-3000UHB

21

C-4100UHB

26

C-6000UHB

50

1-25

UHB Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued)
Data Latch Family
UnR Cell
Name

Basic
Cells

Drive
(Iu)

Enable

BRs

Output

VL2

Data Latch with TM

5

36

High

1

Q

VL4

Data Latch with TM

14

36

High

4

Q

LTK

Data Latch

4

18

Low

1

Q,XQ

Async

LTL

Data Latch with Clear

5

18

Low

1

Q,XQ

Async

LTM

Data Latch with Clear

16

18

Low

4

Q,XQ

-

LTI

S-R Latch with Clear

4

18

Low

1

Q,XQ

Async

LT4

Data Latch

14

18

Low

4

Q,XQ

-

Description

Clear

-

Note: V-type latches incorporate inhibit inputs and transparent mode (TM) to facilitate scan implementation.
Continued on next page

Scan Flip-flop Family (Positive-Edge Triggered)
UnRCeIl
Name

Description

Basic
Cells

Drive
(Iu)

BRs

Output

Clear

Preset

Clock
InhlbR

-

Ves

SOH'

Scan 0 Flip-flop with 2:1 Multiplex

14

36

1

Q,XQ

Async

SDJ'

Scan 0 Flip-flop with 4:1 Multiplex

15

36

1

Q,XQ

Async

SDK'

Scan 0 Flip-flop with 3:1 Mu~iplex

16

36

1

Q,XQ

Async

SJH

Scan J-K Flip-flop

16

36

1

Q,XQ

Async

-

SOD'

Scan OFlip-flop with 2:1

16

36

1

Q,XQ

Async

Async

Ves

SDA

Scan I-input 0 Flip-flop

12

36

1

Q,XQ

-

Ves

SOB

Scan I-input 0 Aip-f1op

42

36

4

Q,XQ

-

SHA

Scan I-input 0 Flip-flop

68

18

8

Q,XQ

-

Ves

SHB

Scan I-input 0 Flip-flop

62

18

8

Q

-

Ves

SHC

Scan I-input 0 Aip-f1op

62

18

8

XQ

SHJ'

Scan 0 Flip-flop with 2:1

Mu~iplex

78

18

8

Q,XQ

SHK'

Scan 0 Flip-flop with 3:1 Muniplex

88

18

8

Q,XQ

Note: ' Indicates 0 Flip-flop with

Mu~iplex

mu~iplexed

-

-

Ves
Ves
Ves

Ves

-

Ves

-

Ves

Ves

inputs.
Continued on next page

1-26

UHB Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

(Continued)

Non-Scan Flip-flop Family
Unit Cell
Name

Description

Basic
Cells

Drive
(Iu)

Bits

Output

Clear

Preset

-

Async

Clock
Inhibit

FDS

o Flip-flop
o Flip-flop with Set
o Flip-flop with Reset
o Flip-flop with Set and Reset
o Flip-flop
o Flip-flop with Clear
o Flip-flop

FD2

Power 0 Flip-flop

FD3

Power 0 Flip-flop with Preset

8

36

I

a,xa

-

Async

Neg

FD4

Power 0 Flip-flop with Clear and Preset

9

36

I

a,xa

Async

Async

Neg

FD5

Power 0 Flip-flop with Clear

8

36

I

a,xa

Async

Neg

FJD

Positive Edge Clocked
Power J-K Flip-flop with Clear

12

36

I

a,xa

Async

-

FDM
FDN
FDO
FOP
FDa
FOR

Note:

-

6

18

1

a,xa

7

18

1

a,xa

Pas

7

18

1

a,xa

Async

8

18

1

a,xa

Async

Async

Pas

21

18

4

a

-

-

Neg

26

18

4

a

Async

-

Pas

20

18

4

a

7

36

1

a,xa

-

Neg

-

-

Pas
Pas

Pas

Pas

Synchronous flip-flops my be constructed by adding a simple AND gate (such as N2P) to the input of a flip-flop to create
a synchronous clear.

Binary Counter Family
Unit
Cell
Name

Description

Basic
Cells

Drive
(Iu)

Bits

Outputs'

Load

Clear

Enable

Carry
In

Upl
Down

SCf'!

Scan 4-bit Synchronous Binary
Up Counter with Parallel Load

62

36

4

a,xa,
COtS)

Sync

-

Low

High

Up

SC82

Scan 4-bit Synchronous Binary
Down Counter with Parallel Load

66

36

4

a,xa,
COtS)

Sync

-

High

Low

Down

Cll"

Non-Scan Flip-Flop for Counter

11

18

-

a,xa

-

-

-

-

-

C41

Non-Scan 4-bit Binary
Asynchronous Counter

24

18

4

a,(A)

Async

-

-

Up

C42

Non-Scan 4-bit Binary
Synchronous Counter

32

18

4

a

-

Async

-

-

Up

C43

Non-Scan 4-bit Binary
Synchronous Up Counter

48

18

4

a,co (S)

Sync

Async

High

High

Up

C45

Non-Scan Binary Synchronous
Up Counter

48

18

4

a,co

Sync

Sync

High

High

Up

C47

Non-Scan Binary Synchronous
Up/Down Counter

68

18

4

a,co

Async

Low

Low

Upl
Down

-

Notes: l(S), (A) indicate the counter is (S)ynchronous or (A)synchronous.
2Scan counters include clock inhibit and high drive (CDR = 36 lu). For non-Scan counters CDR _ 18 lu.
'Ctt may by used for purposes other than counters.
Continued on next page

1-27

UHB Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued)
Shift Register Family
Unit
Cell
Name

Basic
Cells

Description

Drive
(Iu)

Bit
Width

Load

Outputs

Clock
Polarity

FSI

Serial-in Parallel-out Shift Register

18

16

4

Serial-In only

a-Parallel

Neg

FS2

Shift Register wtlh Synchronous Load

30

16

4

Sync-High

a-Parallel

Neg

FS3

Shift Register wtlh Asynchronous
Load

34

18

4

Async-Low

a-Parallel

Pos

SRI

Serial-in Parallel-out Shift Register
with Scan

36

36

4

Serial-In only

a-Parallel

Pos

Datapath Operators (Adder, ALU, Parity)
Unit
Cell
Name

Description

Basic
Cells

Drive
(Iu)

4

A>B,A=B,AB,A=B,ALB

-

AlA

I-btl HaH Adder

5

36

1

S,CO

AIN

I-bit Full Adder

8

18

1

S,CO

CI

A2N

2-btl Full Adder

16

14

2

S,CO

CI

A4H

4-btl Binary Full Adder w/Fast Carry

48

18(00)
14(S)

4

S,OO

CI

-

PE5

Even Parity GeneratorlChecker

12

36

5

EVEN,OOU

P05

Odd Parity Generator/Checker

12

36

5

ODD, EVEN

-

PE8

Even Parity GeneratorlChecker

18

18

8

EVEN,OOU

-

P08

Odd Parity Generator/Checker

18

18

8

ODD, EVEN

-

PEg

Even Parity Generator/Checker

22

18

g

EVEN,OOU

-

POg

Odd Partly Generator/Checker

22

18

g

ODD, EVEN

-

Miscellaneous Cells
Unit Cell Name

Description

Basic Cells

Function

ZOO

o Clip

0

lie to Vss

ZOI

1 Clip

0

lietoVoo

Continued on next page

1-28

UHB Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

(Continued)

Input Buffer Family
Unit Cell
Name

Description

Basic
Cells

Drive (Iu)

Logic
Level

Type

Input/Output
Polarity

11B
11BU
11BO

Input Buffer
11 B with Pull-up Resistance
11 B with Pull-down Resistance

5
5
5

36
36
36

TTL
TTL
TTL

Signal
Signal
Signal

Invert
Invert
Invert

12B
12BU
12BO

Input Buffer
12B with Pull-up Resistance
12B with Pull-down Resistance

4
4
4

36
36
36

TTL
TTL
TTL

Signal
Signal
Signal

True
True
True

IKB
IKBU
IKBO

Clock Input Buffer
IKB With Pull-up Resistance
IKB w~h Pull-down Resistance

4
4
4

72
72
72

TTL
TTL
TTL

Clock
Clock
Clock

Invert
Invert
Invert

ILB
ILBU
ILBO

Clock Input Buffer
ILB with Pull-up Resistance
ILB with Pull-down Resistance

6
6
6

72
72
72

TTL
TTL
TTL

Clock
Clock
Clock

True
True
True

11C
11CU
11CO

CMOS Interface Input Buffer
11 C with Pull-up Resistance
11 C with Pull-down Resistance

5
5
5

36
36
36

CMOS
CMOS
CMOS

Signal
Signal
Signal

Invert
Invert
Invert

12C
12CU
12CO

CMOS Interface Input Buffer
12C with Pull-up Resistance
12C with Pull-down Resistance

4
4
4

36
36
36

CMOS
CMOS
CMOS

Signal
Signal
Signal

True
True
True

11S
11SU
11S0

Schmitt Trigger Input Buffer
11S with Pull-up Resistance
11 S with Pull-down Resistance

8
8
8

18
18
18

CMOS
CMOS
CMOS

Schmitt
Schmitt
Schmitt

Invert
Invert
Invert

12S
12SU
12S0

Schm~t

Trigger Input Buffer
12S with Pull-up Resistance
12S with Pull-down Resistance

8
8
8

18
18
18

CMOS
CMOS
CMOS

Schmitt
Schmitt
Schmitt

True
True
True

11R
11RU
11RO

Schm~t

Trigger Input Buffer
11 R with Pull-up Resistance
11 R with Pull-down Resistance

6
6
6

18
18
18

TTL
TTL
TTL

Schmitt
Schmitt
Schmitt

Invert
Invert
Invert

12R
12RU
12RO

Schmitt Trigger Input Buffer
12R With Pull-up Resistance
12R with Pull-down Resistance

8
8
8

18
18
18

TTL
TTL
TTL

Schmitt
Schmitt
Schmitt

True
True
True

Note:

A "UK suffixed to the name of an input buffer indicates pull-up resistance of 5DK!} (typical) and a "0" indicates a
pull-down resistance of the equivalent value.
Continued on next page

1-29

UHB Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued)
Output Buffer Family
Unit Cell
Name

Description

Basic
Cells

Drive
(loJ

Logic2
Level

Type

Edge
Rate
Control

Input/Output
Polarity

01B

Output Buffer

3

3.2mA

TTUCMOS

Standard

No

Invert

01L

Power Output Buffer

3

12mA

TTUCMOS

Standard

No

Invert

01S

Power Output Buffer

5

12mA

TTUCMOS

Standard

Yes

Invert

02B

Output Buffer

2

3.2mA

TTUCMOS

Standard

No

True

02L

Power Output Buffer

2

12mA

TTUCMOS

Standard

No

True

02S

Power Output Buffer

4

12mA

TTUCMOS

Standard

Yes

True

04T'

Output Buffer

4

3.2mA

TTUCMOS

3-state

No

True

04W'

Power 3-state Output Buffer

4

12mA

TTUCMOS

3-state

No

True

04S!

Power 3-state Output Buffer

5

12mA

TTUCMOS

3-state

Yes

True

01R

Output Buffer

5

3.2mA

TTUCMOS

Standard

Yes

Invert

02R

Output Buffer

4

3.2mA

TTUCMOS

Standard

Yes

True

04R'

Output Buffer

5

3.2mA

TTUCMOS

3-state

Yes

True

02S2

High Power Output Buffer

6

24mA

TTUCMOS

Standard

Yes

True

0452'

High Power Output Buffer

7

24mA

TTUCMOS

3-state

Yes

True

01BF

Output Buffer

3

SmA

TTUCMOS

Standard

No

Invert

01RF

Output Buffer

5

SmA

TTUCMOS

Standard

Yes

Invert

02BF

Output Buffer

2

SmA

TTUCMOS

Standard

No

True

02RF

Output Buffer

4

SmA

TTUCMOS

Standard

Yes

True

04RF

3-state Output Buffer

5

SmA

TTUCMOS

3-state

Yes

True

3-state
No
True
3-state Output Buffer
4
SmA
TTUCMOS
04TF
Note: 'Whlle all outputs are totem-pole type, Open Drain and Open Source types can easily be defined for all3-state type
outputs.
Example of Open Drain Output
Rp.,lh4> (min) = Vee (max)

Z01

10L

(rated)

IN------I
Internal

L

Rpulldn(min) = Voo (max)

Provides
Wire OR

~LL>.r-T-

OUT

ZOO

Internal

OUT

L

Z

H

IN

X

OUT

o

H

H

1

Z

L

External

Example of Open Source Output

1-30

X

o

'-.r:":'-'-_ OUT

Provides
Wire AND

Note:

IN

10L

(rated)

External

2Totem pole outputs, such as these buffers have, can drive both TTL and CMOS levels. Voltage margins depend on
actual source or sink current (see DC specifications).

UHB Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued)
Bidirectional 110 Buffers (Buses)
Unit Cell
Name

Description

Basic
Cells

Drive (101..)

Logic
Level

Edge Rate
Control

Input/Output
Polarity

No
No
No

True
True
True

12mA
12mA
12mA

TTL
TTL
TTL
TTL
TTL
TTL

No
No
No

True
True
True

8
8
8

3.2mA
3.2mA
3.2mA

CMOS
CMOS
CMOS

No
No
No

True
True
True

Power 3-state Output and CMOS
Interface Input Buffer
H6E with Pull-up Resistance
H6E with Pull-down Resistance

8
8
8

12mA
12mA
12mA

CMOS
CMOS
CMOS

No
No
No

True
True
True

3-state Output and Schmttt
Trigger Input Buffer
H6S with Pull-up Resistance
H6S with Pull-down Resistance

12
12
12

3.2mA
3.2mA
3.2mA

CMOS
CMOS
CMOS

No
No
No

True
True
True

12
12
12

3.2mA
3.2mA
3.2mA

TTL

H6RU
H6RD

3-state Output and Schmitt
Trigger Input Buffer
H6R with Pull-up Resistance
H6R with Pull-down Resistance

True
True
True

H8T
H8TU
H8TD

3-state Output and Input Buffer
H8T with Pull-up Resistance
H8T with Pull-down Resistance

9
9
9

3.2mA
3.2mA
3.2 mA

Ves
Ves
Ves

True
True
True

H8W
H8WU
H8WD

Power 3-state Output and Input Buffer
H8W with Pull-up Resistance
H8W with Pull-down Resistance

9
9
9

12mA
12mA
12mA

Ves
Ves
Ves

True
True
True

H8W2
H8W1
H8WO

High Power 3-state Output and Input Buffer
H8W2 with Pull-up Resistance
H8W2 wtth Pull-down Resistance

11
11
11

24mA
24mA
24mA

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

No
No
No

Ves
Ves
Ves

True
True
True

H8C

3-state Output Buffer and CMOS
Interface Input Buffer
H8C with Pull-up Resistance
H8C with Pull-down Resistance

9
9
9

3.2mA
3.2mA
3.2mA

CMOS
CMOS
CMOS

Ves
Ves
Ves

True
True
True

Power 3-state Output Buffer and Interface
Input Buffer

9

12mA

CMOS

Ves

True

H6T
H6TU
H6TD

3-state Output and Input Buffer
H6T with Pull-up Resistance
H6T with Pull-down Resistance

8
8
8

3.2mA
3.2mA
3.2mA

H6W
H6WU
H6WD

Power 3-state Output and Input Buffer
H6W wtth Pull-up Resistance
H6W with Pull-down Resistance

8
8
8

H6C

3-state Output and CMOS
Interface Input Buffer
H6C with Pull-up Resistance
H6C with Pull-down Resistance

H6CU
H6CD
H6E
H6EU
H6ED
H6S
H6SU
H6SD
H6R

H8CU
H8eD
H8E

TTL

..

H8EU
H8E with Pull-up Resistance
9
12mA
CMOS
Ves
True
H8E with Pull-down Resistance
H8ED
9
12mA
CMOS
Ves
True
ft'
Note: A U suffixed to the name of a bidirectIOnal buffer Indicates a pull-up resistance of son (tYPical) and a D indicates a
pull-down resistance of the equivalent value.
Continued on next page

...

..

II

1-31

UHB Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

(Continued)

Bidirectional 110 Buffers (Buses) (Continued)
Basic
Cells

Drive (Iu)

Logic
Lavel

Type

High Power 3-state Output and Input
Buffer
HSE2 w~h Pull-up Resistance
HSE2 w~h PUll-down Resistance

11
11
11

24mA
24mA
24mA

CMOS
CMOS
CMOS

Ves
Ves
Ves

True
True
True

3-state Ou1put and Schmitt Trigger Input
Buffer True
HSS with Pull-up Resistance
HSS with Pull-down Resistance

13
13
13

3.2mA
3.2mA
3.2mA

CMOS
CMOS
CMOS

Ves
Ves
Ves

True
True
True

3-state Output and Schmitt Trigger Input
BufferTrue
HSR with Pull-up Resistance
HSR with Pull-down Resistance

13
13
13

3.2mA
3.2mA
3.2mA

TTL
TTL
TTL

Ves
Ves
Ves

True
True
True

H6TFU
H6TFD

3-state Output and Schm~tTrigger Input
BufferTrue
H6TF wnh Pull-up Resistance
H6TF wnh Pull-down Resistance

S
S
S

SmA
SmA
SmA

TTL
TTL
TTL

No
No
No

True
True
True

H6CF
H6CFU
H6CFD

3-state Output and Input Buffer
H6CF with Pull-up Resistance
H6CF with Pull-down Resistance

S
S
S

SmA
SmA
SmA

CMOS
CMOS
CMOS

No
No
No

True
True
True

HSTF
HSTFU
HSTFD

3-state Output and Input Buffer
HSTF with Pull-up Resistance
HSTF w~h Pull-down Resistance

9
9
9

SmA
SmA
SmA

TTL
TTL
TTL

Ves
Ves
Ves

True
True
True

HSCF
HSCFU
HSCFD

3-state Output and Input Buffer
HSCF with Pull-up Resistance
HSCF with Pull-down Resistance

9
9
9

SmA
SmA
SmA

CMOS
CMOS
CMOS

Ves
Ves
Ves

True
True
True

Unit Cell
Name
HSE2
HSEl
HSEO
HSS
HSSU
HSSD
HSR
HSRU
HSRD
H6TF

Note:

Description

While all outputs are totem-pole type, Open Drain and Open Source types can easily be defined for all3-state type
outputs, which includes all bidirectional buffers.

Oscillator Circuits
Unit Cell
Name

Description

Basic
Cells

Input Logic
Level

HOC

Output Buffer for Oscillator and Input
Buffer

S

CMOS

HOCS

Output Buffer for Oscillator and Schmitt
Trigger Input Buffer

S

TTL

HOCR

Output Buffer for Oscillator wnh feedback
Resistance

S

CMOS

ITlO

Input Buffer for Oscillator

0

-

1-32

Input/Output
Polarity

UHB Series CMOS Gate Arrays
UHB GATE ARRAY PACKAGE CHARACTERISTICS
Dual In-line Packages (Standard DIP)
Package Code
Pinout Code
DIP-16

Plastic

Ceramic

Number of Vee

Number of Vss

Available Number or
Signal Pins

DIP-16P-M02

DIP-16C-C03

1

2

13

1

2

17

1

1

18

DIP-22C-C02

2

2

18

1

1

20

DIP-24C-COl

2

2

20

1

1

22

DIP-28C-C02

2

2

24

1

1

26

DIP-40C-AOl

2

4

34

DIP-16P-M04
DIP-18

DIP-18P-MOl

DIP-18C-COl

DIP-18P-M02
DIP-20

DIP-20P-M02

DIP-20C-C02

DIP-20U
DIP-22

DIP-22P-M02
DIP-22P-M03

DIP-22U
DIP-24

DIP24P-MOl
DIP24P-M02

DlP-24U
DIP-28

DIP-28P-M02
DIP-28P-M03

DIP-28U
DIP-40

DIP-40P-MOl

DIP-40C-A02
DIP-40U
DIP-42

DIP-42P-MOl

1

1

38

DIP-42C-AOl

2

4

36

1

1

40

DIP-48C-AOl

2

4

42

1

1

46

DIP-42P-M02
DIP-42U
DIP-48

DIP-48P-MOl
DIP-48P-M02

DIP-48U

Continued on next page

1-33

UHB Series CMOS Gate Arrays
UHB GATE ARRAY PACKAGE CHARACTERISTICS (Continued)
Dual In-line Packages (Shrink DIP, 70 mil Pin Pitch)
Package Code
Available Number of
Signal Pins

Number of Voo

Number of Vss

DIP-28SH

2

2

24

DIP-28SHU

1

1

26

DIP-42SH

2

4

36

DlP-42SHU

1

1

40

DIP-48SH

2

4

36

Pinout Code

Plastic

Ceramic

DIP-48SHU

1

1

46

DIP~SH

2

4

58

DIP--04SHU

2

2

60

Number of V00

Number of Vss

Available Number of
Signal Pins

DIP-22SK

2

2

18

DIP-22SKU

1

1

20

DIP-24SK

2

2

20

DIP-24SKU

1

1

22

DIP-28SK

2

2

24

DIP-28SKU

1

1

26

Number of Voo

Number of Vss

Available Number of
Signal Pins

1

2

13

1

1

14

FPT-20P-M02

1

2

17

1

1

18

FPT-24-M02

2

2

20

1

1

22

FPT-28P-M01

2

2

24

1

1

26

Dual In-line Packages (Skinny DIP, 300 mil Body Pitch)
Package Code
Pinout Code

Plastic

Ceramic

Flatpack Packages (Dual-Leaded)
Package Code
Pinout Code
FPT-16

Plastic
FPT-16P-M03

FPT-16U
FPT-20
FPT-20U
FPT-24
FPT-24U
FPT-28
FPT-28U

Ceramic

Continued on next page

1-34

UHB Series CMOS Gate Arrays
UHB GATE ARRAY PACKAGE CHARACTERISTICS (Continued)
Flatpack Packages (Quad-Leaded)
Package Code
Pinout Code

Plastic

Ceramic

Number of VDD

Number of Vss

Available Number of
Signal Pins

FPT-44

2

4

36

FPT-44U

2

2

40

2

4

42

FPT-48U

2

2

44

FPT-48'

2

4

42

FPT-48U'

2

2

44
58

FPT-48

FPT-48P-M02

FPT-64'

FPT-64P-MOl

2

4

FPT-64U

FPT-70P-MOl

1

1

62

FPT-80

FPT-80P-MOl

2

6

72

FPT-80U
FPT-l00

FPT-l00P-MOl

FPT-l00U

2

4

74

4

8

88
92
102

4

4

FPT-120

6

12

FPT-120U

4

8

108

FPT-160

8

14

138

FPT-160U

6

12

142

-

• Small body size.
Subject to Change

Pin Grid Arrays (PGA, Thru-Hole, 100 mil Pin Pitch)
Package Code
Pinout Code
PGA-64

Plastic

Ceramic
PGA-64C-A02

PGA-64U
PGA-88

PGA-88C-AOl

Number of VDD

Number of Vss

Available Number of
Signal Pins
58

2

4

2

2

60

4

6

78

PGA-88U

4

4

80

PGA-135

8

12

115

PGA-135U

4

8

127

PGA-179

8

16

155
163

PGA-179U

8

8

PGA-208

12

18

178

PGA-256.

16

20

220
Conffnued on next page

1-35

UHB Series CMOS Gate Arrays
UHB GATE ARRAY PACKAGE CHARACTERISTICS (Continued)
Flatpack Packages (Dual-Leaded)
Package Code
Pinout Code

Plastic

LCC-28

Number of VDD

Number of Vss

LCC-28C-A02

2

2

24

1

1

26

2

4

42

1

2

45

LCC-28U
LCC-48

Available Number of
Signal Pins

Ceramic

LCC-48C-A01

LCC-48U

2

4

58

LCC-64U

LCC-64C-A01

2

2

60

LCC-68

2

4

62

LCC-68U

2

2

64

LCC-64

LCC-84

4

6

74

LCC-84U

3

4

77

Number of VDD
2

Number of Vss
2

Available Number of
Signal Pins
24

Plastic Leaded Chip carriers (PLCCs, 50 mil Pitch)
Package Code
Pinout Code
PLCC-28

Plastic
LCC-28P-M01

1

1

26

LCC-44P-M01

2

4

38

1

2

41

LCC-68P-M01

2

4

62

2

2

64

4

6

74

2

4

78

PLCC-28U
PLCC-44
PLCC-44U
PLCC-68
PLCC-68U
PLCC-84
PLCC-84U

Ceramic

LCC-84P-M01

Subject to Change

1-36

UHB Series CMOS Gate Arrays
UHB GATE ARRAY PACKAGE AVAILABILITY
C-330

C-530

C-830

C-1200

C-1700

C-2200

C-3000

C-4100

C-8000

C-8700

C-12000

C

C

C

C

C

C

C

C

C

C

C

UHB

DIP

16
18
20
22
24
28
40
42
48

SDIP
(SHRINK)

28
42
48
64

SKDIP
(SKINNy)

22
24
28

FPT
with leads on
two sides of
the package

16
20
24
28

FPT
with leads on
four sides of
the package

44
48
48"
64
80

P

UHB

P

UHB

P

UHB

P

UHB

•
•
• •
• •
• •
•
•

•

•
•
•
•
•
•
•
•

•
•
•
•
•
•
• • • •
•
•
•
•
•
•
•

•
•

28
44
68

•

84

•

88
135

•
•
•
• •

·••

• •
•

•

•

•
•
•

•
•

•
•

•

•
• •
•
•
•
• •

·
•
•
•

UHB

256

•
•

•

•

•
•
•
•

•

P

UHB

P

UHB

P

•
•

•

•

•

•
•
•

C=Ceramlc
P = Plastic
" = 48-pin FPT. smaller then the other 48 FPT

·••
•

•

•

•

•
•
•

•
•
•
•
•

•

•
•
•
• •
• •
•
•

•
•
•
• •
• •
•
•
•

•
•

•
•
•

·•
·•
·• · · ·• ·• ··
•

•
•
•
• •
• • •
• • •
•
•
•

· ·• ·• ·• ·•• ·• ··• ·•• ·•• ·• ·

179

28
48
64
68
84

P

•

•
•
•
•

208
LCC

UHB

UHB

P

•
•
• •
• • • • •
• • • • • •
• • • • • •

160

64

P

•
·
• • ·
•
• • •
•
•
•
• • •
•
•
•
·• ·• · ·· ·• ·• ·• ·• • ·• • ·• ·· ·•
• • • • •
•
•
•
•
• • • • • • •
•
•
·
•
•
•
•
•
•
•
·• • ·•
•
•
•
•
•
•
·• •
•
•
•
•

120

PGA

UHB

•

100

PLCC

P

•
•
•

•
•
•

0

0

0

0

0

0

· · ·•• ·•
·•
·
0

0: available now

a. under development

1-37

UHB Series CMOS Gate Arrays
PACKAGE DIMENSIONS

PGA-256C-A03

256-LEAD CERAMIC (METAL SEAL) PIN GRID ARRAY PACKAGE
(Case No.: PGA-256C-A03)

,

.100 ± .010

V

D

1.800 (45.72)
REF

-1--1._

INDEX AREA

~

sa

1.970 ± .020
(50.04 ± 0.51)

(O.4a~g:J:)

.050 ± .010
(1.27±0.51)

.130 ~:g

(3.30~g:iJ
.250 6.35)

MAX

1-38

)

UHB Series CMOS Gate Arrays
PACKAGE DIMENSIONS

(Continued)

..

PGA-20BC-A02

208-LEAD CERAMIC (METAL SEAL) PIN GRID ARRAY PACKAGE
(Case No.: PGA-208C-A02)

,

.100 ± .010

f

I.

D

.050 (1.27) OIA TYP

L~(4PLCS)
@G>@@@@@@@@@@@@@O
@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@
@@@@
@@@@
@@@@
@@@@

1.600 (40.64)
REF

@@@)@

@@@@

@@@)@

@@@@
@@@@

@@@@
@@@)@

INDEX

~

@@@@
@@@@

@@@@

@

@ @ @ @
@@@@

@@@@

@@@@

@@@@@@@@@@@@@@@@@

@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@
o@@@@@@@@@@@@@@@o

INDEX AREA

.005

1.693 + .020 sa
(43.00 ±0.51)

.018 .003

.1
.050 ± .010
(1.27 ± 0.51)

(O.46~
.134

g)!)

~ ..g1'!

(3.40:g·:J)
.240 6.10)

MAX

1-39

UHB Series CMOS Gate Arrays

1-40

cO

May 1990
Edition 1.0

FUJITSU

PRODUCT PROFILE

CG1D Series D.8-micron CMOS Gate Arrays
DESCRIPTION
The CG1 0 series of 0.8-micron CMOS gate arrays is a highly integrated low-power, ultra high-speed product family that derives its
enhanced performance and increased user flexibility from the use of a system-proven, dual-column gate structure and 2-layer
metal interconnect technology. The unique dual-column gate structure increases density and speed performance, as well as gate
utilization. CG10 architecture is fully compatible with Fujitsu's 1.5-micron UHB arrays.
Internal high-drive clock buffers minimize clock skew across the chip while internal bus performance and integrity is assured by
incorporating 3-state transmission gate logic underneath the routing channels. Input buffer options include pull-up and pull-down
resistance, Schmitt trigger, CMOS input, and clock driver. Output buffer options include 3-state, bidirectional, edge rate control,
and high-drive output. The high-drive output buffers provide highly symmetrical output waveforms.

FEATURES
•
•
•
-

High-dens~y silicon gate CMOS technology
3200 to 14,000 usable gates
90% maximum utilization fully autorouted

Ultra high speed
typical 0.5 ns/0.6 ns gate delay
(power type/normal type)
narrow delay variation

•
•
-

Low-skew clock signal distribution
High-performance clock drivers
Hierarchical clock distribution
Frequency-dependent clock routing
Automatic test pattern generation
complete family of scan design macros
available

High sink current capability
3.2 mA, 8 mA, 12 mA, and 24 mA options
available
selectable edge rate control

PRODUCT FAMILY
Device Name

Available
Gales'

Maximum
Sianal Pins'

Power
Disslpallon
all0 MHz

CG10272

3,256

t08

150mW

CGt0342

4,032

t23

200mW

CG10492

5,572

148

200mW

CG10572

6,510

163

200mW

CG10692

7,684

163

250mW

CG10l03

11,OBO

188

250mW

CG10133
14,720
220
250mW
1Gale counl based on 2-lnpul NAN D and Includes basIc cells to form I/O
buffer functions
2Maximum signal pin numbers depend on the outpul drive requirements
and Ihe package selected.

Copyrlght© 1990 FUJITSU LIMITED and Fujitsu Microelectronics. Inc.

1-41

CG10 Series CMOS Gate Arrays
AC CHARACTERISTICS
BESTIWORST CASE MULTIPLIERS FOR PROPAGATION DELAYS
Propagation delays characteristic of a gate array are a function of several factors, including operating temperature, supply voltage,
fanout loading, interconnection routing metal, process variation, input transition time, and input signal polarity. Temperature and
supply voltage factors affecting propagation delays in the OGl 0 OMOS family of gate arrays are given in the table below.
Pre-Layout Simulation
Temperature
Range

VDD

= 5 V ±SO/O

Voo

Post-Layout Simulation

= 5 V ±100/0

Voo

= 5 V ±50/0

Voo

= 5 V ±100/0

Best Case

Worst Case

Best Case

Worst Case

Best Case

Worst Case

Best Case

Worst Case

0-70°01

0.35

1.65

0.30

1.75

0.40

1.60

0.35

1.70

-20-70°0

0.35

1.65

0.25

1.75

0.35

1.60

0.30

1.70

-40-70°0

0.25

1.65

0.20

1.75

0.30

1.60

0.25

1.70

-40-85°02

0.25

1.75

0.20

1.85

0.30

1.70

0.25

1.80

Notes:

1-42

1Commercial temperature range
21ndustrial temperature range

CG10 Series CMOS Gate Arrays
REPRESENTATIVE PROPAGATION DELAYS
Constants for calculating the delays due to process variation, fanout loading, interconnection routing metal, transition time, and signal
polarity are given for each un~ cell in the CGl0 Unit Cell Library. Delays using these factors are calculated for a representative
selection of un~ cells and are shown in the Propagation Delay tables below.
Calculations are representative of unit cells in the CG10672 (CG10 6700-gate CMOS gate array).
Typical values are indicated. Worst case multipliers are applied to typical values. Smaller arrays can exhib~ significantly greater
speed.
Propagation Delays (In ns)
Unit Cell
Function

Unit Cell
Name

Equivalent
Gate Count

Input
Transition
1

2

NDI (Fan-out)
4
8

16

32

Inverter

V1N

1

tpLH
tpHL

0.38
0.38

0.60
0.57

0.91
0.79

1.34
1.13

2.33
1.88

5.00
0.12

Power 2-lnput NAND

N2K

2

tpLH
tpHL

0.33
0.38

0.45
0.56

0.60
0.74

0.82
0.99

1.16
1.38

1.91
2.25

Power 16-lnput NAND

NGB

11

tpLH
tpHL

1.06
1.11

1.17
1.28

1.33
1.46

1.55
1.68

1.89
2.02

2.64
2.78

Power 2-lnput NOR

R2K

2

tpLH
tpHL

0.46
0.38

0.60
0.50

0.92
0.65

1.31
0.87

1.90
1.21

3.20
1.96

Power Exclusive OR

X2B

4

tpLH
tpHL

1.00
1.01

1.11
1.14

1.26
1.28

1.49
1.46

1.83
1.74

2.58
2.36

3-wide 2-AND 6-lnput

036

3

tplH
tpHL

0.84
0.72

1.24
0.99

1.82
1.38

2.97
2.15

6.05
4.21

###
8.38

G24

2

tpLH
ipHL

0.68
0.55

1.09
0.82

1.70
1.21

2.89
1.98

6.07
4.04

###
8.21

T28

11

ipLH
tpHL

1.43
1.39

1.54
1.47

1.70
1.58

1.92
1.73

2.26
1.96

3.01
2.46

Power Clock Buffer

K2B

3

tplH
ipHL

0.71
0.81

0.77
0.86

0.85
0.94

0.96
1.05

1.13
1.26

1.43
1.52

Scan 8-b~ 0 Flip-flop with
Clock Inhibit and 3:1

SHK

88

tpLH
ipHL

3.10
3.07

3.33
3.25

3.63
3.48

4.07
3.81

5.05
4.56

7.72
2.80

FOO

7

tplH
tpHL

1.41
1.37

1.63
1.56

1.94
1.81

2.37
2.18

3.36
3.00

6.03
5.24

FD5

8

tpLH
tpHL

1.28
1.34

1.39
1.53

1.55
1.68

1.77
1.86

2.11
2.14

2.86
2.76

043

48

tpLH
tpHL

1.20
1.14

1.43
1.29

1.73
1.49

2.17
1.78

3.15
2.44

5.82
4.24

045

48

tpLH
tpHL

1.41
1.35

1.65
1.52

1.98
1.75

2.45
2.08

3.51
2.83

6.38
4.87

AND-OR Inverter (A -+ Y)
2-wide 2-OR 4-input
OR-AND-Inverter (A -+ X)
Power 2-AND 8-Wide
Multiplexer (A -+ X)

Data Mu~iplexer (CK,IH -+ 0)
Non-5can 0 Flip-flop
w~h

Reset (CK -+ 0)

Non-Scan Power 0 Flip-flop
wnh Clear (CK -+ 0)
Non-Scan 4-bn Binary
Synchronous Up
Counter (CI -+ CO)
Non-Scan 4-b~ Binary
Synchronous Up
Counter (CI -+ CO)

Note: Delays for inter-block wiring are not included

Continued on next page

1-43

..

CG10 Series CMOS Gate Arrays
REPRESENTATIVE PROPAGATION DELAYS (Continued)
Propagation Delays (in ns)
Unit Cell
Function

Unit Cell
Name

~ulvalent

Gate Count

Input
Transition

NDI (Fan-out)

8

16

32

C47

68

tpLH
IpHL

1.68
1.68

1.84
1.83

2.05
2.03

2.34
2.33

3.02
2.99

4.86
4.78

A4H

48

IpLH
tpHL

1.02
0.98

1.33
1.24

1.75
1.60

2.51
2.25

3.91
3.43

###
7.53

T5A

5

tpLH

0.64

0.97

1.50

2.45

###

###

tpHL

0.62

0.93

1.42

2.29

4.91

9.67

1
Non-Scan 4-btt Binary
Synchronous UpIDown

4

2

Counter (DU ~ CO)
4-bit Binary Full Adder
with Fast Carry (CI ~ 51)
4:1 Selector (55 ~ X)
4-bit Shift Register with
Synchronous Load

FS2

30

tpLH
tpHL

1.65
1.65

1.88
1.84

2.18
2.07

2.66
2.44

3.67
3.20

6.74
1.75

9-bit Odd Partty
Generator/Checker

P09

22

tpLH
tpHL

3.45
3.39

3.68
3.54

3.98
3.74

4.42
4.03

5.40
4.69

8.07
6.49

4-wide 2:1 Data

P24

12

tpLH
tpHL

0.70
0.66

0.81
0.74

0.96
0.84

1.19
0.99

1.53
1.22

2.28
1.73

MC4

42

tpLH
tpHL

1.70
1.52

2.11
1.69

2.72
1.91

3.91
2.35

7.09
-0.30

###
2.08

B41

9

tpLH

1.08

1.18

1.32

1.51

1.81

2.47

tpHL

1.09

1.21

1.36

1.58

1.92

2.67

Selector (A ~ X)
4-bit Magnitude
Comparator (IS ~ 00)
4-bit Bus Driver (A ~ X)
Input Buffer (Inverter)

lIB

5

tpLH
tpHL

1.05
1.07

1.11
1.15

1.19
1.25

1.30
1.40

1.47
1.63

1.84
2.14

Clock Input Buffer
(Inverter)

IKB

4

IpLH
IpHL

1.56
1.56

1.58
1.57

1.61
1.59

1.64
1.63

1.70
1.68

1.81
1.77

12

25

I/O Cell
Function

Unit Cell Equivalent
Input
Name
Gate Count Transition

Output Buffer Load In pF
50

100

200

Output Buffer (True)

02B

2

tPLH
tPHL

0.93
1.75

1.40
2.78

2.30
4.75

4.10
8.70

7.70
16.60

14.90
32.40

Power Output Buffer
(True)

02L

2

tpLH
tpHL

0.90
1.21

1.21
1.54

1.81
2.19

3.01
3.49

5.41
6.09

10.21
11.29

3-State Output Buffer

O4T

4

tpLH
tPHL

1.07
2.42

1.54
3.46

2.44
5.46

4.24
9.46

7.84
17.46

15.04
33.46

O4W

4

tPLH
tpHL

1.09
3.03

1.41
3.47

2.00
4.32

3.00
6.02

5.60
9.42

10.40
16.22

H6T

8

tpLH
tpHL

0.87
1.43

1.09
1.73

1.51
2.30

2.36
3.45

4.06
5.75

7.46
10.35

H6W

8

tPLH
tPHL

1.09
3.03

1.40
3.47

2.00
4.32

3.20
6.02

5.60
9.42

10.40
16.22

(True) (OT ~ X)
Power 3-State Output
Buffer (True) (OT ~ X)
3-State Output and
Input Buffer (True) (X ~ IN)
Power 3-State Output
and Input Buffer (True) (OT ~ X)

Note: Delays for inter-block wiring are not included

1-44

400

CG10 Series CMOS Gate Arrays
DC CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS'
Rating

Symbol

Supply Voltage
Input Voltage
Output Voltage

Unit

VSS -0.52

6.0

V

VI

VSS -0.52

Von +0.5

V

Vo

Vss-0.52

Voo +0.5

V

-40

101.=3.2 mA
Output Current"

Maximum

Minimum

Voo

IOl~8mA

-40

los

rnA

~O

10l= 12mA

~5

Storage Temperature

Ceramic
Plastic

-40

+150
+125

5C

T.1g

Temperature Under Bias

Ceramic
Plastic

-40
-25

+125
+85

5C

T biaa

Notes:

..

-90

IOl=24 rnA

damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the
conditions as detailed in the operation sections of the data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2VSS = 0 V.
"Only one output at a time may be shorted for more than one second.
1 Permanent device

RECOMMENDED OPERATING CONDITIONS
Symbol

Minimum

Typical

Maximum

Unit

Supply Vottage

Parameter

Voo

4.75

5.0

5.25

V

Input High Voltage for TTL Input

VIH

2.2

-

V

Input Low Vottage for TTL Input

Vil

-

0.8

V

Input High Voltage for CMOS Input

VIH

Voo x 0.7

Input Low Voltage for CMOS Input

Vil

-

Operating Temperature

TA

0

-

CAPACITANCE (TA = 25°C,

Voo = VI =

Parameter

-

V

Voo x 0.3

V

70

°C

Maximum

Unit

16

pF

16

pF

0 V, f = 1 MHz)

Symbol

Minimum

Typical

Output Pin Capacitance
(1m. - 3.2 rnA, 8 rnA, or 12 rnA)

COUT

-

Output Pin Capacitance
(Iol -24 rnA)

COUT

-

18

pF

Coo

-

16

pF

ClIO

-

23

pF

Input Pin Capac~ance

VO Pin Capac~ance
(Iol - 3.2 rnA, 8 rnA, or 12 rnA)

VO Pin Capacitance
(10I.-24mA)

C IN

1-45

CG10 Series CMOS Gate Arrays
DC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Parameter

Symbol

Condition

Minimum

Typical

Maximum

Unit

Power Supply Current

loos

Steady State1

0

-

100

J.1A

Output High Voltage
for Normal Output (IOL - 3.2 rnA)

VOH

IoH m-2 rnA

4.0

-

Voo

V

Output High Voltage
for Driver Output (lot. = SmA)

VOH

IOH =-2 rnA

4.0

-

Voo

V

Output High VoHagefor Driver Output
(lol-12 rnA)

VOH

IOH --4 rnA

4.0

-

Voo

V

Output High Voltage
for Driver Output (Iol =24 rnA)

VOH

1oH--SmA

4.0

-

Voo

V

Output Low Voltage2
for Normal Output (Iol = 3.2 rnA)

VOL

IOL =3.2 mA

Vss

-

0.4

V

Output Low Voltage
for Driver Output (IOL = SmA)

VOL

10l=SmA

Vss

-

0.4

V

Output Low Voltage2
for Driver Output (lel = 12 rnA)

VOL

IOl=12mA

Vss

-

0.4

V

Output Low Voltage2
for Driver Output (IOL - 24 rnA)

VOL

IOL=24mA

Vss

-

0.5

V

Input High VoHage
for TTL Input

VIH

-

2.2

-

-

V

Input Low Voltage
for TTL Input

Vil

-

-

-

O.S

V

Input High VoHage
for CMOS Input

VIH

-

-

-

V

Input Low Voltage
for CMOS Input

Vil

-

-

-

Voox 0.3

V

Schmitt Trigger CMOS Inpur
Positive-going Threshold
Negative-going Threshold
Hysteresis

VT•
VT_
VT.-VT

-

2.5
0.7
1.1

3.3
1.4
1.9

4.0
2.0
2.7

V
V
V

Schmitt Trigger TTL Input3
Positive-going Threshold
Negative-going Threshold
Hysteresis

VT•
VT_
VT.-VT

1.4
O.S
0.4

1.9
1.3
0.6

2.5
1.S
0.7

V
V
V

25

50

100

ItO

VI-O-VOO

,-10

J.1A

VI-O-VOO

-

10

-10

10

J.1A

Input Pull-uplPull-down Resistor

Rp

Input Leakage Current

III

Input Leakage Current (3-state)
Noles: 'VIN = Voo. Vil = Vss
2With certain resbictions on pin assignment
3These values for reference only

1-46

ILZ

-

Vil to VIH• VIH• to Vil

-

Vil to VIH• VIH • to Vil
VIHtO Voo
Vil to Vss

Voox 0.7

CG10 Series CMOS Gate Arrays

ARRAY ARCHITECTURE
The typical CG1 0 chip is composed of double columns of CMOS gates (basic cells) separated by dedicated wiring channels. A basic
cell consists of a pair of N-channel and a pair of P-channel transistors interconnected by polysilicon gate control terminals. Groups of
basic cells are interconnected by custom metallization into unit cells. Fuj~su un~ cells provide a wide range of standard logic functions
such as exclusive OR gates, flip-flops, buffers, and counters. The CG10 Series CMOS gate array family includes over 250 different
unit cells. These unit cells are the building blocks from which complex designs are constructed.
The spaces between the double columns of basic cells are occupied by channels for custom metallization. Nearly half ofthese wiring
channels contain transmission gates that implement internal3-state buses. Bus terminators located althe ends olthe double columns
of cells maintain the last value to be sent through the bus to ensure proper operation under all conditions.
The I/O cells around the perimeter of the matrix of cells are composed of internal cells with input protection networks and the potential
to be configured as input buffers, clock input buffers, output buffers, power output buffers, or bidirectional buffers.

_ D .....•.................................. _ _ _
--~I~

:

~

,~-

4

2 - -........i--I3:iH

5

•

J

v.rm

D

m
em III

d
3

--+1....
lem _ _ ••••..•••••..••••.•••.J •••••••••••••••••

6

Typical Chip Layout, Double Column Structure

1.
2.
3.
4.
5.
6.

Dedicated Clock Network - for high frequency clocks
3-state Bus Logic -located In wiring channels
Bus Terminators - prevent ftoating state on buses
Driver Transistors and 110 Protection Networks - provide high 110 count
Double Columns - for optional macro utilization and speed
Wiring Channel Area - for metallization between unit cells

1-47

CG10 Series CMOS Gate Arrays
DESIGN COMPONENTS
DESIGNING WITH THE CG10 PRODUCT FAMILY
To implement logic functions, you build up the elements of the circuit from unit cells. Simple unit cells are used hierarchically to build
higherlevelfunctions until the logic is completely defined. Fujitsu offers acomplete line of standard logic functions in the unit cell library.
Super macros are used to implement large super-cell functions such as expandable ALUs and multipliers.

1/0 BUFFERS
Each CGI 0 1/0 buffer around the perimeter of the array consists of an input protection network and large N-channel and P-channel
transistors capable of supplying the standard 3.2-mA, S-mA, and 12-mA output currents. Two of these large transistor pairs may be
connected in parallel, using high-output-current macros, to obtain 24-mA drive. One of the I/O pads whose output transistors have
been used for the 24-mA high-current option may still be used as an input.
Input VO buffers convert external TTL levels to internal CMOS levels or may receive CMOS level signals directly. Output I/O buffers are
totem pole and may drive either CMOS and TTL levels, depending on their AC and DC loads. Any of the pins except the dedicated
power and ground pads can be designed to be an input buffer, an input buffer with pull-uplpull-down resistance, a clock input buffer, an
output buffer, a high-drive output buffer, an output buffer with noise limiting resistance, a 3-state output buffer, a bi-directional buffer, or
a Schmitt trigger input buffer. There are some restrictions on the location of 24-mA buffers.

INPUT CLOCK DRIVERS
The large output VOtransistor pair is used in a high-drive input clock driver for high fanout applications within the array. This allows you
to fully utilize the high speed capabilities of the CGI 0 technology.

TESTING CG10 DEVICES
Two options are available for testing CGIO designs: (I) the standard designer-supplied test patterns and test vectors (in Fujitsu's
FTDL format) and (2) the use of scan cells combined with Automatic Test Generation (ATG) performed by Fujitsu computers for
additional diagnostic test patterns. If you have designed with scan cells and other scan logic elements, Fujitsu will complete the scan
test program generation.
Regardless of the selected test option, you need to furnish Fujitsu with enough test patterns to guarantee that the submitted design
completely performs its intended logic functions. These patterns include your test function of each 1/0 pin.

Diagramatlc Representation of Design Structure for ScanTestlng

1-48

CG10 Series CMOS Gate Arrays
Voo and Vss REQUIREMENTS
Each CG1 0 Series gate array device has two options for each package type, both supporting a different numberof power and ground
pins. The numberof power and ground pins required depends on the number of simultaneously switching outputs used in the design.
Simultaneously switching outputs (SSOs) are output signals that change from H to Lor L to H or from Z to H or Z to L within a 20-ns
window (including possible skew).
Muniple outputs that switch at the same time can cause noise on Voo and Vss lines and affect the performance of a device. Therefore,
to achieve maximum reliability, Fujitsu limits the number of SSOs per Voo pin according to the table below. The maximum number of
SSOs per pin is determined by a representative value specifiedforthedriving capability of each type of output. The total representative
value of all SSOs used in adesign must not exceed 80 per Vss pin. For example, 11 normaI3.2-mA outputs with edge rate control, four
12-mA outputs, or three 24-mA outputs per Vss pin may be SSOs.

Output Drive Type

Representative Value
per Output

Normal (3.2 mAl

10

High Drive (12 mAl

20

Normal (3.2 mAl with
Edge Rate Control

7

High Drive (12 mAl
with Edge Rate Control

14

High Drive (24 mAl
with Edge Rate Control

26

1-49

CG10 Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY
Note:

The load unit (Iu) is a normalized loading unit of capacitance representing the input load of an inverter without metal
interconnection.

Inverter and Buffer Family

Basic Cells

Drive (/u)

Polarity

V1N

Inverter

1

18

Neg

V2B

Power Inverter

1

36

Neg

B1N

True Buffer

1

18

Pas

BD3

True Delay Buffer (> 5 ns)

5

18

Pas

BD4

Delay Cell (> 4 ns)

4

6

Pas

BD5

Delay Cell (>10 ns)

9

18

Pas.

BD6

Delay Cell (>22 ns)

17

18

Pas

Description

Unit Cell Name

Clock Buffer Family
Basic Cells

Drive (Iu)

Polarity

K1B

True Clock Buffer

2

36

Pas

K2B

Power Clock Buffer

3

55

Pas

K3B

Gated Clock (AND) Buffer

2

36

Pas

K4B

Gated Clock (OR) Buffer

2

36

Pas

KSB

Gated Clock (NAND) Buffer

3

36

Neg

Description

Unit Cell Name

KAB

Block Clock (OR) Buffer

3

55

Pas

KBB

Block Clock (OR x 10) Buffer

30

55

Pas

V1L

Double Power Inverter

2

55

Neg

NAND Family
Unit Cell Name

Description

Basic Cells

Drive (Iu)

N2N

2-input NAND

1

18

N2B

Power 2-input NAND

3

36
36

N2K

Fast Power 2-input NAND

2

N3N

3-input NAND

2

14

N3B

Power 3-input NAND

3

36

N4N

4-input NAND

2

10

N4B

Power 4-input NAND

4

36

N6B

Power 6-input NAND

5

36

N8B

Power 8-input NAND

6

36

N9B

Power 9-input NAND

8

36

NCB

Power 12-input NAND

10

36

NGB

Power 16-input NAND

11

36

N3K

Fast Power 3-input NAND

3

28

N4K

Fast Power 4-input NAND

4

20
ConMued on next page

1-50

CG10 Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

(Continued)

NOR Family
Description

UnltCeIl Name

Drive (Iu)

Basic Cells

R2N

2-input NOR

1

14

R2B

Power 2-input NOR

3

36
36

R2K

Power 2-input NOR

2

R3N

3-inputNOR

2

10

R3B

Power 3-input NOR

3

36
20

R3K

Power 3-input NOR

3

R4N

4-input NOR

2

6

R4B

Power 4-input NOR

4

36

R4K

Power 4-input NOR

4

12

R6B

Power 6-input NOR

5

36

RaB

Power a-input NOR

6

36

R9B

Power 9-input NOR

8

36

RCB

Power 12-input NOR

10

36

RGB

Power 16-input NOR

11

36

Basic Cells

Drive (Iu)

AND Family
Unit Cell Name

Description

N2P

Power 2-input AND

2

36

N3P

Power 3-input AND

3

36

N4P

Power 4-input AND

3

36

Nap

Power a-input AND

6

36

OR Family
Basic Cells

Drive (Iu)

R2P

Power 2-input OR

2

36

R3P

Power 3-input OR

3

36

R4P

Power 4-input OR

3

36

RSP

Power B-input OR

6

36

Unit Cell Name

Description

Exclusive NORIOR Family (EXOR/EXNOR)
Unit Cell Name

Description

Basic Cells

Drive (Iu)

X1N

Exclusive NOR

3

18

Neg

X1B

Power Exclusive NOR

4

36

Neg

X2N

Exclusive OR

3

14

Pas

X2B

Power Exclusive OR

4

36

Neg

X3N

3-input Exclusive NOR

5

14

Neg

X3B

Power 3-input Exclusive NOR

6

36

Neg

X4N

3-input Exclusive OR

5

14

Pos

X4B

Power 3-input Exclusive OR6

6

36
Pos
Convnued on next page

Polarity

1-51

CG10 Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

(Continued)

AND-OR-Invener Family (AOI)
Basic Cells

Drive (Iu)

023

2-wide 2-ANO 3-input AOI

2

14

014

2-wide 3-ANO 4-input AOI

2

14

024

2-wide 2-ANO 4-input AOI

2

14

034

3-wide 2-ANO 4-input AOI

2

10

036

3-wide 2-ANO 6-input AOI

3

10

2

10

Basic Cells

Drive (Iu)

Unit Cell Name

Description

2-wide 2-0R 2-ANO 4-input AOI
044
Note: AND-OR-Inverter unit cells are useful in ImplemenUng sum-of-products (SOP) expressions
OR-AND-Invener Family (OAI)
Description

Unit Cell Name
G23

2-wide 2-0R 3-input OAI

2

18

G14

2-wide 3-0R 4-input OAI

2

10

G24

2-wide 2-0R 4-input OAI

2

10

004

3-wide 2-0R 4-input OAI

2

10

G44

2-wide 2-ANO 2-0R 4-input OAI

2

14

..

Note: OR-AND-Inverter Unit cells are useful In ImplemenUOg product-of-sums (POS) expressions.

Multiplexer Family
Unit Cell Name Type

Basic Cells

Drive (Iu)

Function

T24*

4:1

Power 2-ANO 4-wide MUHiplexer

Description

6

36

SOP

T26*

6:1

P.()wer 2-ANO 6-wide MuHiplexer

10

36

SOP

T2S*

S:l

Power 2-ANO S-wide Multiplexer

11

36

SOP

T32

2:1

Power 3-ANO 2-wide MuHiplexer

5

36

SOP

T33*

3:1

Power 3-ANO 3-wide Multiplexer

8

36

SOP

T34*

4:1

Power 3-ANO 4-wide Multiplexer

9

36

SOP

T42

2:1

Power 4-ANO 2-wide Multiplexer

6

36

SOP

T43

3:1

Power 3-ANO 3-wide MuHiplexer

10

36

SOP

T44

4:1

Power 4-ANO 4-wide MuHiplexer

11

36

SOP

T54

4:1

Power 4-2-3-2 ANO 4-wide Muniplexer

10

36

SOP

U24*

4:1

Power 2-OR 4-wide MuHiplexer

6

36

P~S

U26*

6:1

Power 2-0R 6-wide MUHiplexer

9

36

P~S

U28*

8:1

Power 2-0R 8-wide MuHiplexer

11

36

P~S

U32

2:1

Power 3-0R 2-wide Multiplexer

5

36

P~S

U33*

3:1

Power 3-0R 3-wide MuHiplexer

36

P~S

U34*

4:1

Power 3-0R 4-wide MUHiplexer

7
9

36

P~S

U42

2:1

Power 4-0R 2-wide MuHiplexer

6

36

P~S

U43

3:1

Power 4-0R 3-wide MuHiplexer

9

36

P~S

Power 4-0R 4-wide Multiplexer
U44
4:1
* Convenient for typical multiplexer apphcaUons

11

36

P~S

Continued on next page

1-52

CG10 Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

(Continued)

Data Selectors/Multiplexers

.

Unit Cell
Name

Type

Description

Basic Cells

Drive (/u)

Selects

Bit
Width

Outputs

P24·

2:1

Data Selector

12

36

S,XS

Q

4

T2E

2:1

Selector

5

18

S

XQ

2
4

T2F

2:1

Selector

8

18

S

XQ

T2B·

2:1

Selector

2

18

S,XS

XQ

1

T2C·

2:1

Selector

4

18

S,XS

XQ

2

T2D·

2:1

Selector

2

14

S,XS

XQ

1

T5A·

4:1

Selector

5

9

S,XS

XQ

1

V3A·

1:2

Selector

2

14

S,XS

XQ

1

V3B·

1:2

Selector

4

14

S,XS

XQ

2

..

These are transmission gate deVICeS whose outputs can be tied because they can be Inhibited With true/Inverted selects .

Decoders
Unit Cell
Name

lYpe

Description

Basic Cells

Drive (Iu)

Active Lavel
Outputs

DE2

2:4

Decoder

5

18

Low

-

DE3

3:8

Decoder

15

14

Low

-

DE4

2:4

Decoder

8

14

Low

Low

DE6

3:8

Decoder

30

18

Low

1. High
2. Low

Enable

Internal Bus Un" Cells
Unit Cell Name

Basic Cells

Drive (Iu)

Bus Size

Enable

B41

4-b~

Description
Bus Driver

9

36

4 bits

Low

Bll

l-b~

Bus Driver

5

36

1 bit

Low

1-53

CG10 Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued)
Data

Latch Family

UnHCeIINarne

Basic
Cells

Drive
(Iu)

Enable

BHs

Output

YL2

Data Latch with TM

5

36

High

1

Q

YL4

Data Latch with TM

14

36

High

4

Q

Description

Clear

-

LTK

Data Latch

4

18

low

1

Q,XQ

Async

LTL

Data Latch with Clear

5

18

low

1

Q,XQ

Async

LTM

Data Latch with Clear

16

18

Low

4

Q,XQ

LT1

S-R Latch with Clear

4

18

low

1

Q,XQ

Async

LT4

Data Latch

14

18

low

4

Q,XQ

-

-

Note: Y-type latches incorporate inhibit inputs and transparent mode (TM) to facilitate scan implementation.

Scan Flip-flop Family (Positive-Edge Triggered)
Unit Cell
Name

Description

Basic
Cells

Drive
(Iu)

Bits

Output

SDW

Scan D Flip-flop with 2:1 Multiplex

14

36

1

SDJ·

Scan 0 Flip-flop with 4:1 MuRiplex

15

36

1

SDK·

Scan D Flip-flop with 3:1 MuRiplex

16

36

Scan J.-K Flip-flop

16

SOD·

Scan OFIip-flop with 2:1 Multiplex

SDA

Clock
Inhibit

Clear

Preset

Q,XQ

Async

Async

-

Yes

Q,XQ

1

Q,XQ

Async

Yes

36

1

Q,XQ

Async

-

16

36

1

Q,XQ

Async

Async

Yes

Scan 1-input D Flip-flop

12

36

1

Q,XQ

-

Yes

SOB

Scan 1-input D Flip-flop

42

36

4

Q,XQ

-

Yes

SHA

Scan 1-input DRip-flop

68

18

8

Q,XQ

Scan 1-input DRip-flop

62

18

8

Q

-

Yes

SHB
SHC

Scan 1-input D Flip-flop

62

18

8

XQ

Scan D Flip-flop with 2:1 MuRiplex

78

18

8

Q,XQ

SHK·

Scan D Flip-flop with 3:1 MuRiplex

88

18

8

Q,XQ

SFDM

Scan 1-input 0 Flip-flop

10

18

1

Q,XQ

-

Yes

SHJ·

-

SFDO

Scan 1-input D Flip-flop

11

18

1

Q,XQ

Async

-

Yes

SFDP

Scan 1-input 0 Flip-flop

12

18

1

Q,XQ

Async

Async

Yes

SFDR

Scan 4-input D Flip-flop

36

18

4

QA-QD

Async

-

Yes

SFDS

Scan 4-input D Flip-flop

31

18

4

QA-QD

Scan J-K Flip-flop

14

18

1

Q,XQ

-

Yes

SFJD

SJH

Note: • Indicates 0 Flip-flop with muRiplexed inputs.

1-54

-

Yes

Yes

Yes

Yes
Yes
Yes

Yes

CG10 Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

(Continued)

Non-Scan Flip-flop Family
Unit Cell
Name

Description

FDS

o Flip-flop
o Flip-flop with Set
o Flip-flop with Reset
o Flip-flop with Set and Reset
o Flip-flop
o Flip-flop with Clear
o Flip-flop

FD2

Power 0 Flip-flop

FDM
FDN
FDO
FOP
FDQ
FOR

Basic
Cells

Drive
(Iu)

Bits

Output

Clear

Preset

Clock
Inhibit

6

18

1

Q,XQ

-

7

18

1

Q,XQ

-

Async

Pos

7

18

1

Q,XQ

Async

-

Pos

8

18

1

Q,XQ

Async

Async

Pos

21

18

4

Q

-

Neg

26

18

4

Q

Async

-

20

18

4

Q

7

36

1

Q,XQ

-

-

Pos

Pos

-

Neg

FD3

Power 0 Flip-flop with Preset

8

36

1

Q,XQ

FD4

Power 0 Flip-flop with Clear and Preset

9

36

1

Q,XQ

Async

FD5

Power 0 Flip-flop with Clear

8

36

1

Q,XQ

Async

-

Neg

FJD

Positive Edge Clocked
Power J-K Flip-flop with Clear

12

36

1

Q,XQ

Async

-

Pos

Note:

..

Pos

Async

Neg

Async

Neg

Synchronous flip-flops my be oonstructed by adding a simple AND gate (such as N2P) to the input of a flip-flop to create a synchronous
clear.

Scan Counter Family
Unit
Cell
Name

Description

Basic
Cells

Drive
(Iu)

Bits

Outputs'

Load

Clear

Enable

Carry
In

Upl
Down

SC72

Scan 4-bit Synchronous Binary
Up Counter with Parallel Load

62

36

4

Q,XQ,
COtS)

Sync

-

Low

High

Up

SC82

Scan 4-bit Synchronous Binary
Down Counter with Parallel Load

66

36

4

Q,XQ,
COtS)

Sync

-

High

Low

Down

High

Low

Up

Low

-

Up/
Down

SC43

Scan 4-bit Synchronous Binary
Up Counter with Asynchronous
Clear

59

18

4

QA,QD,

Sync

SC47

Scan 4-bit Synchronous Binary
Up/Down Counter

78

18

4

QA,QD,

Sync

Async

-

Notes: 1(5), (A) indicate the oounter is (S)ynchronous or (A)synchronous.
2Scan oounters include clock inhibit and high drive (CDR = 36 lu). For non-Scan oounters CDR = 181u.

Continued on next page

1-55

CG10 Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CEll LIBRARY

(Continued)

Non-Scan Counter Family
Unit
Cell
Name

Description

Basic
Cells

Drive
(Iu)

Bits

-

Outputs1

Load

Clear

Down

-

-

-

a,xa

-

4

a,(A)

-

Async

-

-

Up

18

4

a

-

Async

-

-

Up

48

18

4

a,CO(S)

Sync

Async

High

High

Up

48

18

4

a,co

Sync

Sync

High

High

Up

68

18

4

a,co

Async

Low

Low

Up/
Down

Cl1 3

Non-Scan Flip-Flop for Counter

11

18

C41

Non-Scan 4-b~ Binary
Asynchronous Counter

24

18

C42

Non-Scan 4-b~ Binary
Synchronous Counter

32

C43

Non-Scan 4-b~ Binary
Synchronous Up Counter

C45

Non-8can Binary Synchronous
Up Counter

047

Non-Scan Binary Synchronous
UplOown Counter

-

Upl

Carry
In

Enable

-

Notes: 1(S), (A) indicate the counter is (S)ynchronous or (A)synchronous.
2Scan counters include clock inhibit and high drive (CDR = 36lu). For non-Scan counters CDR = lSlu.
3C 11 may by used for purposes other than counters.

Shift Register Family
Unit
Cell
Name

Basic
Cells

Drive
(Iu)

Bit
Width

Serial-in Parallel-out ShiftRegister

18

16

4

FS2

Shift Register w~h Synchronous Load

30

16

FS3

Shift Register with Asynchronous
Load

34

SRl

Serial-in Parallel-out ShiftRegister
with Scan

36

1-56

Description

Outputs

Clock
Polarity

Serial-In only

a-Parallel

Neg

4

Sync-High

a-Parallel

Neg

18

4

Async-Low

a-Parallel

Pas

36

4

Serial-In only

a-Parallel

Pas

Load

CG10 Series CMOS Gate Arrays
Datapath Operators (Adder, ALU, Parity)
Unit
Cell·
Name

Description

Basic
Cells

Drive
(Iu)

Bit Width

MC4

Magnitude Comparator

42

18 (=)
10

«,»

4

Outputs
A>B,A=B,AB,A=B,ALB

AlA

I-bit Half Adder

5

36

1

S,OO

-

AIN

I-bit Full Adder

8

18

1

S,OO

CI

A2N

2-bit Full Adder

16

14

2

S,OO

CI

4-bit Binary Full Adder wlFast Carry

48

18(00)
14 (S)

4

S,CO

CI

A4H
PE5

Even Parity Generator/Checker

12

36

5

EVEN,OUU

-

P05

Odd Parity Generator/Checker

12

36

5

ODD,EVEN

PE8

Even Parity Generator/Checker

18

18

8

EVEN,OUU

-

P08

Odd Parity Generator/Checker

18

18

8

ODD,EVEN

-

PE9

Even Parity Generator/Checker

22

18

9

EVEN,OUU

P09

Odd Parity Generator/Checker

22

18

9

ODD, EVEN

-

Miscellaneous Cells
Unit Cell Name

Description

Basic Cells

Function

ZOO

o Clip

0

lie to Vss

ZOI

1 Clip

0

lie to VDD
Continued on next page

1-57

CG10 Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued)
Input Buffer Family
Unit Cell
Name

Basic
Cells

Drive (Iu)

logic
Level

lYpe

Input/Output
Polarity

11B
11BU
11BO

Input Buffer
11 B with Pull-up Resistance
11 B with Pull-down Resistance

5
5
5

36
36
36

TTL
TTL
TTL

Signal
Signal
Signal

Invert
Invert
Invert

12B
12BU
12BO

Input Buffer
12B with Pull-up Resistance
12B with Pull-down Resistance

4
4
4

36
36
36

TTL
TTL
TTL

Signal
Signal
Signal

True
True
True

IKB
IKBU
IKBO

Clock Input Buffer
IKB With Pull-up Resistance
IKB with Pull-down Resistance

4
4
4

72
72
72

TTL
TTL
TTL

Clock
Clock
Clock

Invert
Invert
Invert

IKC
IKCU
IKCO

Clock Input Buffer
IKC With Pull-up Resistance.
IKC with Pull-down Resistance

4
4
4

200
200
200

CMOS
CMOS
CMOS

Clock
Clock
Clock

Invert
Invert
Invert

ILB
ILBU
ILBO

Clock Input Buffer
ILB with Pull-up Resistance
ILB with Pull-down Resistance

6
6
6

72
72
72

TTL
TTL
TTL

Clock
Clock
Clock

True
True
True

ILC
ILCU
ILCO

Clock Input Buffer
ILC with Pull-up Resistance
ILC with Pull-down Resistance

6
6
6

200
200
200

CMOS
CMOS
CMOS

Clock
Clock
Clock

True
True
True

11C
11CU
11CO

CMOS Interface Input Buffer
11C with Pull-up Resistance
11 C with Pull-down Resistance

5
5
5

36
36
36

CMOS
CMOS
CMOS

Signal
Signal
Signal

Invert
Invert
Invert

12C
12CU
12CO

CMOS Interface Input Buffer
12C with Pull-Up Resistance
I2C with Pull-down Resistance

4
4
4

36
36
36

CMOS
CMOS
CMOS

Signal
Signal
Signal

True
True
True

11S
11SU
11S0

Schmitt Trigger Input Buffer
11S with Pull-up Resistance
11 S with Pull-down Resistance

8
8
8

18
18
18

CMOS
CMOS
CMOS

Schmitt
Schmitt
Schmitt

Invert
Invert
Invert

I2S
12SU
12S0

Schmitt Trigger Input Buffer
12S with Pull-up Resistance
12S with Pull-down Resistance

8
8
8

18
18
18

CMOS
CMOS
CMOS

Schmitt
Schmitt
Schmitt

True
True
True

11R
11RU
11RO

Schmitt Trigger Input Buffer
11 R with Pull-up Resistance
11 R with Pull-down Resistance

6
6
6

18
18
18

TTL
TTL
TTL

Schmitt
Schmitt
Schmitt

Invert
Invert
Invert

12R
12RU
12RO

Schmitt Trigger Input Buffer
12R With Pull-up Resistance
12R with Pull-down Resistance

8
8
8

18
18
18

TTL
TTL
TTL

Schmitt
Schmitt
Schmitt

True
True
True

Note:

1-58

Description

A "U" suffixed to the name of an input buffer indicates pull-up resistance of SOK!} (typical) and a "0" indicates a pull-down resistanoe of
the equivalent value.

CG10 Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued)
Output Buffer Family
Unit Cell
Name

Description

Basic
Cells

Drive
.rT-

ZOO
Internal
Note:

IN

OUT

lot. (rated)

External

ITotem pole outputs, such as these buffers have, can drive both TIL and CMOS levels. Voltage margins depend on actual source or
sink currant (see DC specifications).

1-59

CG10 Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

(Continued)

Bidirectional 110 Buffers (Buses)
Unit Cell
Name

Description

Basic
Cells

Drive (Iu)

Logic
Level

TTL

H6T
H6TU
H6TD

3-state Output and Input Buffer
H6T with Pull-up Resistance
H6T with Pull-down Resistance

8
8
8

3.2mA
3.2mA
3.2mA

TTL

H6W
H6WU
H6WD

Power 3-state Output and Input Buffer
H6W with Pull-up Resistance
H6W w~h Pull-down Resistance

8
8
8

12mA
12mA
12mA

H6C

3-state Output and CMOS
Interface Input Buffer
H6C with Pull-up Resistance
H6C with Pull-down Resistance

8
8
8

Power 3-state Output and CMOS
Interface Input Buffer
H6E with Pull-up Resistance
H6E with Pull-down Resistance

'TYpe

Input/Output
Polarity

TTL

No
No
No

True
True
True

TTL
TTL
TTL

No
No
No

True
True
True

3.2mA
3.2mA
3.2mA

CMOS
CMOS
CMOS

No
No
No

True
True
True

8
8
8

12mA
12mA
12mA

CMOS
CMOS
CMOS

No
No
No

True
True
True

3-state Output and Schmit!
Trigger Input Buffer
H6S with Pull-up Resistance
H6S with Pull-down Resistance

12
12
12

3.2mA
3.2mA
3.2mA

CMOS
CMOS
CMOS

No
No
No

True
True
True

H6RU
H6RD

3-state Output and Schmitt
Trigger Input Buffer
H6R w~h Pull-up Resistance
H6R with Pull-down Resistance

12
12
12

3.2mA
3.2mA
3.2mA

No
No
No

True
True
True

H8T
H8TU
H8TD

3-state Output and Input Buffer
H8T with Pull-up Resistance
H8T with Pull-down Resistance

9
9
9

3.2mA
3.2mA
3.2mA

TTL
TTL
TTL
TTL

True
True
True

H8W
H8WU
H8WD

Power 3-state Output and Input Buffer
H8W w~h Pull-up Resistance
H8W w~h Pull-down Resistance

9
9
9

12mA
12mA
12mA

Yes
Yes
Yes

True
True
True

H8W2
H8W1
H8WO

High Power 3-state Output and Input Buffer
H8W2 w~h Pull-up Resistance
H8W2 wah Pull-down Resistance

11
11
11

24mA
24mA
24mA

TTL
TTL
TTL
TTL
TTL
TTL
TTL

Yes
Yes
Yes

Yes
Yes
Yes

True
True
True

H8C

3-state Output Buffer and CMOS
Interface Input Buffer
H8C with Pull-up Resistance
H8C with Pull-down Resistance

9
9
9

3.2mA
3.2mA
3.2mA

CMOS
CMOS
CMOS

Yes
Yes
Yes

True
True
True

H8E

Power 3-state Output Buffer and Interface
Input Buffer

9

12mA

CMOS

Yes

True

H8EU
H8ED

H8E with Pull-up Resistance
H8E with Pull-down Resistance

9
9

12mA
12mA

CMOS
CMOS

Yes
Yes

True
True

H6CU
H6CD
H6E
H6EU
H6ED
H6S
H6SU
H6SD
H6R

H8CU
H8CD

Nole:

A ·U- suffixed to the name of a bidirectional buffer indicates a pull-up resistance of
resistance of the equivalent value.

TTL

SOn (typical) and a "D" indicates a pull-down
Continued on next page

1-60

CG10 Series CMOS Gate Arrays
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

(Continued)

Bidirectional 1/0 Buffers (Buses) (Continued)
Input/Output
Polarity

Basic
Cells

Drive (Iu)

Logic
Level

Type

High Power 3-state Output and Input
Buffer
H8E2 w~h Pull-up Resistance
H8E2 with Pull-down Resistance

11
11
11

24mA
24mA
24 rnA

CMOS
CMOS
CMOS

Yes
Yes
Yes

True
True
True

3-state Output and Schmitt Trigger Input
Buffer True
H8S with Pull-up Resistance
H8S with Pull-down Resistance

13
13
13

3.2 rnA
3.2mA
3.2mA

CMOS
CMOS
CMOS

Yes
Yes
Yes

True
True
True

3-state Output and Schmitt Trigger Input
BufferTrue
H8R with Pull-up Resistance
H8R with Pull-down Resistance

13
13
13

3.2 rnA
3.2 rnA
3.2 rnA

TIL
TIL
TIL

Yes
Yes
Yes

True
True
True

H6TFU
H6TFD

3-state Output and SchmittTrigger Input
BufferTrue
H6TF with Pull-up Resistance
H6TF with Pull-down Resistance

8
8
8

8mA
8mA
8 rnA

TIL
TIL
TIL

No
No
No

True
True
True

H6CF
H6CFU
H6CFD

3-state Output and Input Buffer
H6CF with Pull-up Resistance
H6CF with Pull-down Resistance

8
8
8

8mA
8mA
8mA

CMOS
CMOS
CMOS

No
No
No

True
True
True

H8TF
H8TFU
H8TFD

3-state Output and Input Buffer
H8TF with Pull-up Resistance
H8TF with Pull-down Resistance

9
9
9

8mA
8 rnA
8 rnA

TIL
TIL
TIL

Yes
Yes
Yes

True
True
True

H8CF
H8CFU
H8CFD

3-state Output and Input Buffer
H8CF with Pull-up Resistance
H8CF with Pull-down Resistance

9
9
9

SmA
8mA
8mA

CMOS
CMOS
CMOS

Yes
Yes
Yes

True
True
True

Unit Cell
Name
H8E2
H8El
H8EO
H8S
H8SU
H8SD
H8R
H8RU
H8RD
H6TF

Note:

Description

..

While all outputs are totem-pole type, Open Drain and Open Source types can easily be defined for all3-state type outputs, which
includes all bidirectional buffers.

1-61

CG10 Series CMOS Gate Arrays
CG10 GATE ARRAY PACKAGE CHARACTERISTICS
Dualln·llne Packages (Standard DIP)
Package Code
Pinout Code
DIP-16

Plastic

Ceramic

Number of Voo

Number of Vss

Available Number or
Signal Pins

DIP-16P-M02

DIP-16C-C03

1

2

13

1

2

17

1

1

18

DIP-22C-C02

2

2

18

1

1

20

DIP-24C-C01

2

2

20

1

1

22

DIP-28C-C02

2

2

24

1

1

26

DIP-40C-A01

2

4

34

DIP-16P-M04
DIP-18

DIP-18P-M01

DIP-18C-C01

DIP-18P-M02
DIP-20

DIP-20P-M02

DIP-20C-C02

DIP-20U
DIP-22

DIP-22P-M02
DIP-22P-M03

DIP-22U
DIP-24

DIP24P-M01
DIP24P-M02

DIP-24U
DIP-28

DIP-28P-M02
DIP-28P-M03

DIP-28U
DIP-40

DIP-40P-M01

DIP-40C-A02
DIP-40U
DIP-42

DIP-42P-M01

1

1

38

DIP-42C-A01

2

4

36

1

1

40

DIP-48C-A01

2

4

42

1

1

DIP-42P-M02
DIP-42U
DIP-48

DIP-48P-M01
DIP-48P-M02

DIP-48U

46
Continued on next page

1-62

CG10 Series CMOS Gate Arrays
CG10 GATE ARRAY PACKAGE CHARACTERISTICS (Continued)
Dual In-line Packages (Shrink DIP, 70 mil Pin Pitch)
Package Code
Number of VDD

Number of Vss

Available Number of
Signal Pins

DIP-28SH

2

2

24

DIP-28SHU

1

1

26

DIP-42SH

2

4

36

Pinout Code

Plastic

Ceramic

DIP-42SHU

1

1

40

DlP-48SH

2

4

36

DIP-48SHU

1

1

46

DIP-64SH

2

4

58

DIP-64SHU

2

2

60

Number of VDD

Number of Vss

Available Number of
Signal Pins

DIP-22SK

2

2

18

DIP-22SKU

1

1

20

DIP-24SK

2

2

20

DIP-24SKU

1

1

22

DIP-28SK

2

2

24

DIP-28SKU

1

1

26

Number of VDD

Number of Vss

Available Number of
Signal Pins

FPT-16P-M03

1

2

13

1

1

14

FPT-20P-M02

1

2

17

1

1

18

FPT-24-M02

2

2

20

1

1

22

FPT-28P-M01

2

2

24

1

1

26

..

Dual In-line Packages (Skinny DIP, 300 mil Body Pitch)
Package Code
Pinout Code

Plastic

Ceramic

Flatpack Packages (Dual-Leaded)
Package Code
Pinout Code
FPT-16

Plastic

FPT-16U
FPT-20
FPT-20U
FPT-24
FPT-24U
FPT-28
FPT-28U

Ceramic

Continued on next page

1-63

CG10 Series CMOS Gate Arrays
CG10 GATE ARRAY PACKAGE CHARACTERISTICS (Continued)
Flatpack Packages (Dual-Leaded)
Package Code
Pinout Code

Plastic

Ceramic

Number of Voo

Number of Vss

Available Number of
Signal Pins

FPT-44

2

4

36

FPT-44U

2

2

40

2

4

42

FPT-48U

2

2

44

FPT-48 •

2

4

42

FPT-48

FPT-48P-M02

2

2

44

FPT-64'

FPT-64P-M01

2

4

58

FPT-64U

FPT-70P-M01

1

1

62

FPT-80

FPT-80P-M01

2

6

72

2

4

74
88

FPT-48U'

FPT-80U
FPT-100

4

8

FPT-100U

FPT-100P-M01

4

4

92

FPT-120

6

12

102

FPT-120U

4

8

108

FPT-160

8

14

138

FPT-160U

6

12

142

• Small body size.
Subject to Change

Pin Grid Arrays (PGA, Thru-Hole, 100 mil Pin Pitch)
Package Code
Pinout Code
PGA-64

Plastic

Ceramic

Number of Voo

Number of Vss

Available Number of
Signal Pins

PGA-64C-A02

2

4

58

2

2

60

4

6

78

PGA-64U
PGA-88

PGA-88C-A01

PGA-88U

4

4

80

PGA-135

8

12

115

PGA-135U

4

8

127

PGA-179

8

16

155

PGA-179U

8

8

163

PGA-208

12

18

178

PGA-256

16

20

220
Continued on next page

1-64

CG10 Series CMOS Gate Arrays
CG10 GATE ARRAY PACKAGE CHARACTERISTICS (Continued)
Flatpack Packages (Dual-Leaded)
Package Code
Pinout Code

Plastic

lCC--28

Ceramic

Number of VDD

Number of Vss

Available Number of
Signal Pins

lCC--28C--A02

2

2

24

1

1

26

2

4

42

1

2

45

2

4

58

lCC--28U
lCC--48

lCC--48C--A01

lCC--48U
lCc-64

lCc-64C--A01

lCc-64U

2

2

60

lCC--68

2

4

62
64

..

lCc-68U

2

2

lCc-B4

4

6

74

lCc-B4U

3

4

77

Number of VDD
2

Number of Vss
2

Available Number of
Signal Pins
24

Plastic Leaded Chip carriers (PLCCs, 50 mil Pitch)
Package Code
Pinout Code
PlCC--28

Plastic
lCC--28P-M01

PlCC--28U
PlCC--44

1

1

26

lCC--44P-M01

2

4

38

1

2

41

lCC--68P-M01

2

4

62

2

2

64

4

6

74

2

4

78

PlCC--44U
PlCc-68
PlCc-68U
PlCC--84
PlCc-B4U

Ceramic

lCc-B4P-M01

Subject to Change

1-65

CG10 Series CMOS Gate Arrays
CG10 AVAILABLE PACKAGE TYPES
CG10272

CG10342

CG10492

CG10572

CG10692

CG1 01 03

CG10133

Number of
VDD
I Vss

DIP (Dual In-Line Package)
DIP28

C,P

C,P

P

P

-

-

2 (1)

C,P

C,P

P

P

P

2 (1)

4 (1)

DIP42

C,P

P

C,P

P

P

-

-

2(1)

DIP40

-

2 (1)

4(1)

C,P

C,P

P

P

-

-

2 (1)

4(1)

-

2 (1)

4(1')

2 (2)

4(2)

4

DIP48

C,P

SH-DIP (Shrink Dual In-Line Package)
SH-DIP42

C,P

C,P

P

P

P

-

SH-DIP64

P

P

P

P

P

-

QFP (Quad Flat Package)
OFP48

P

P

P

-

-

-

-

2

OFP64

P

P

P

P

P

P

-

2

4

OFP80

P

P

P

P

P

P

-

2 (2)

6 (4)

OFP100

P

P

P

P

P

P

-

4(4)

8(4)

OFP120

P

P

P

P

P

P

P

6 (4)

12 (8)

OFP160

-

-

P

P

P

P

P

8 (6)

14(12)

-

-

-

-

-

10

18

-

-

2

4

-

4(4)

8(4)

P

P

8

16

-

P

12

18

OFP196

SQFP (Shrink Quad Flat Package)
SOFP64

P

P

-

-

-

SOFP100

P

P

P

SOFP176

-

-

-

-

-

-

SOFP208

PGA (Pin Grid Array Package)
PGA64

C,P

C,P

C,P

C,P

C,P

C,P

C,P

2

4

PGA88

C,P

C,P

C,P

C,P

C,P

C,P

C,P

4(4)

6(4)

PGA135

C

C

C,P

C,P

C,P

C,P

C,P

8 (4)

12 (8)

PGA179

-

-

C,P

C,P

C,P

C,P

C,P

8 (8)

16(8)

-

-

C

C

C

12

18

-

-

-

C

C

16

20

-

-

-

C

16

20

-

2

4

4 (2)

6 (4)

PGA208
PGA256

PGA-SO mil (Pin Grid Array Package-50 mil)
PGA256

-

-

-

PLCC (Plastic Leaded Chip Carriers)
PLCC68

P

P

P

P

P

P

PLCC84

P

P

P

P

P

P

C = Ceramic, P = Plastic

1-66

CG10 Series CMOS Gate Arrays
PACKAGE DIMENSIONS

..

PGA-256C-A03

256-LEAD CERAMIC (METAL SEAL) PIN GRID ARRAY PACKAGE
(Case No.: PGA-256C-A03)

V

I.

o

1.800 (45.72)
REF

INDEX AREA

1.970 ± .020 sa
(50.04± 0.51)

.1
.050 ± .010
(1.27± 0.51)

~I.­
~

(0.46~g:J: )

.130 ~:8rg

(3·30~8.-:J

)

.250 6.35)
MAX

1-67

CG10 Series CMOS Gate Arrays
PACKAGE DIMENSIONS

(Continued)

PGA-208C-A02

208-LEAD CERAMIC (METAL SEAL) PIN GRID ARRAY PACKAGE
(Case No.: PGA-208C-A02)

.100.t..010

L

if
D +1 .. ....
REF

I.

INDEX AREA

1.693 : .020 so
(43.00 :0.51)

.1
.050%.010
(1.27±0.51)

(O.46~8.'~!

~.~~:

(3.40~8."~ )
.240 6.10)
MAX

1-68

••••

~
.134

(4PLCS)

••••••••••••••••
•••••••••••••••••
•••••••••••••••••
•••••••••••••••••
••••
•• •••
••••
••••
•• •••
•••
••••
••••
• •••
•••

1.600 (40.64)

V

.050 (1.27) DIA TYP

)

INDEX

~

....
..... ..

••••
•••
••••
•
•• •••
•••••••••••••••••
•••••••••••••••••
•••••••••••••••••

•••••••••••••••••

CMOS Channeled Gate Arrays

Steps Toward Design

Chapter 2 - Steps Toward Design
Contents of This Chapter
2.1
2.2
2.3
2.4
2.5
2.6

Introduction
Choosing Fujitsu as your ASIC Manufacturer
Choosing a Device
Choosing a Package
Technical Review
Design Interface Options

2.1 Introduction
This section of the data book takes a look at the issues that must be considered before a design is ready
to be entered on a computer-aided engineering (CAE) workstation.
2.2 Choosing FujHsu as Your ASIC Manufacturer
The first step in implementing a given ASIC design is to choose the manufacturer that offers semiconductor processes capable of actualizing the performance requirements of the IC. The manufacturer
should also offer consistent and easily accessible customer support, timely transfer of the design into
.
Silicon, and a highly reliable end product.
The data sheet and supplementary information in Chapter 1 enable customers to determine whether their
requirements fall within the broad range of Fujitsu's technical capability.
The second step is to discuss the design requirements with one of Fujitsu's Field Applications Engineers
at either a Regional Sales Office or a Technical Resource Center. Regional Sales Office and Technical
Resource Center addresses and telephone numbers are listed at the back of this volume. Fujitsu's Field
Applications Engineers work with each customer to determine which technology would be most suitable
for a given deSign, taking into account the factors outlined in more detail below.
Fujitsu's highly developed software tools, high-capacity manufacturing facilities (the largest in the world)
and long history of excellence in the field (Fujitsu has been producing custom gate arrays commercially
since 1974) enable customers to turn designs into highly reliable products in a cost-effective time frame.
2.3 Choosing A Device
Speed is usually the deciding factor in choosing the technology for a design, but sometimes special
requirements such as package availability or on-chip memory (available in the AU and CG21
technologies) influence the final decision.
Usually the device type is a requirement of the design and is chosen before the package size is
determined. The size of the package will depend on array size. partitioning, the number of power and
ground pins required by the SSOs (Simultaneously switching outputs) used in the design. and the high
power drive buffers and clock inputs used in the design.
To determine the most suitable device within a given technology. the designer must determine the gate
count and pinout requirements from the schematic diagram of the design to be implemented.
The functions in the schematic or logic block diagram may be described using standard logic functions,
programmable logic, or Fujitsu's Unit Cell Library.
Gate counts are calculated in terms of how many basic cells make up each component function (unit cell).
This number is given for each unit cell in the unit cell library for each technology. By adding up the number
of basic cells used in each logic element in a design, a designer can arrive at a good first estimate of the
design complexity.

1-69

..

Steps Toward Design

CMOS Channeled Gate Arrays

2.4 Choosing a Package

Before the final choice of an array can be made, however, the choice of a package must be considered.
The intended use of the IC generally determines the type of package used: packaging issues are
discussed in detail in the application note "Choosing the Best Package for Your ASIC DeSign" included in
Chapter 7 of Section 1 of this data book. The types of packages available for Fujitsu's CMOS channeled
arrays are shown in the data sheets in Section 1 and in Appendix D of the UHB Unit Cell Library (Section
2) and Appendix D of the CG10 Unit Cell Library (Section 3).
.
The size of the package chosen is regulated by the number of inputs and outputs required, the number of
Vss and Voo pins required, and the number of simultaneously switching outputs (SSOs) included in the
design.
Package Size vs. SSOs

The number of SSOs can influence the size of the package chosen because additional ground pins are
sometimes required in a design that has more simultaneously switching outputs than is acceptable for a
given package type. Simultaneously switching outputs are those that switch from a logiC low or a high
impedance (Z) to a logic high or from a logic high or Z state to a logic low within 20 nanoseconds of each
other.
A general rule is to use one ground pin for each group of 10 simultaneously switching low power outputs
or for 20 non-simultaneous outputs. Chapter 4 of Section 1 of this book and the Package Pin ASSignments
section of the Design Manuals cover pin requirement issues in more detail.
Although the Vss and Voo pins are preassigned in each package and cannot be changed, alternate
packages are available offering varying numbers of power and ground pins.
2.5 Technical Review

When the CMOS technology, the device, and the package have been decided upon, the customer and
Fujitsu's Field Applications Engineer hold a technical review to ensure that all the information necessary
to implement the design is available and to allow Fujitsu to derive a schedule and price.
2.6 Design Interface Options

The next step is to determine which computer-aided engineering (CAE) workstation will be used to enter
the design. The desired result of entering the design on a CAE workstation is the generation of a
successful net list or Fujitsu Logic Description Language (FLDL) file and a list of test vectors or Fujitsu
Test Description Language (FTDL) file. These two files (which may be generated on any of several
different CAE workstation systems) enable Fujitsu's host mainframe to perform automated layout and
rigorous test and simulation of the design.
Four popular dedicated CAE workstation systems (Valid, Mentor, Dazix, and the HP 9000) as well as
several hardware-independent CAE packages support Fujitsu's design software. In addition, Fujitsu now
offers design support on ViewCADTM, a computer-aided engineering system originated by Fujitsu for ASIC
designs.
ViewCAD is written in the C programming language and runs on any UNI)(TM platform that supports the
X Window System™ (such as the Sun 3 or 4 series of workstations). It includes in one package all of the
necessary functions for the deSign, Simulation, and analysis of an ASIC design. ViewCAD makes use of a
graphics-oriented interface that allows visual examination of all circuits, circuit test data, and simulation
results. Its final product is the logic and test data description files (FLDL and FTDL) that are required by
the host mainframe computer to process a design.
Through long experience, Fujitsu has found that by far the most efficient way to achieve a trouble-free end
product is for customers to implement the design on a workstation themselves. This can be done:

1-70

CMOS Channeled Gate Arrays

Steps Toward Design

a.

on CAD equipment that the customer is already using (Fujitsu provides cell library information files
and the expertise to help write a conversion program to produce the FLDL and FTDL files if
necessary)

b.

on one of the design systems that specifically support Fujitsu software (Daisy, Mentor, Valid, HP
9000) either at the customer's workplace or in one of the Technical Resource Centers

c.

on ViewCAD either on the customer's own Sun equipment or at a Technical Resource Center.

..

1-71

Stees Toward Design

1-72

CMOS Channeled Gate AlTBys

CMOS Channeled Gate Arrays

Design Procedures

Chapter 3 - Design Procedures
Contents of This Chapter
3.1
3.2
3.3
3.4
3.5

Introduction
Workstation Options
Workstation Design Procedures
Post-Design Process
Engineering Sample Testing

3.1 Introduction
This section of the data book explains the steps necessary to implement an ASIC design in one of
Fujitsu's channeled CMOS technologies using a computer-aided engineering (CAE) workstation. Designs
can be implemented with Fujitsu's ViewCAD design software or with one of the CAE systems or software
applications that support Fujitsu designs.
3.2 Workstation Options
3.2.1 VlewCAD
Fujitsu developed the ViewCAD design software to generate the logic circuit (net list) and test data files
necessary to design Fujitsu ASIC devices and to simulate the logic both before and after layout. ViewCAD
complements a wide range of customer third party design tools and includes:
•

A Schematic Capture Module utilizing the X Window System

•

A LogiC Design Rule Check Module that screens for design violations in the areas of fanout and
drive, gate count, 110 requirements, etc.

•

A Test Data or Waveform Entry Module for test vector entry

•

An Interactive Simulation Module that replicates the Fujitsu software for both functional and timing
simulation

•

Conversion Modules to define the net list in the Fujitsu LogiC Description Language (FLDL) and the
test vectors in the Fujitsu Test Data Description Language ( FTDL) formats required by Fujitsu's
design implementation software.

3.2.2 Generic (CAE-dedicated) Workstations
Fujitsu provides ASIC Design Software Kits for deSigners using some of the popular design tools on
generic hardware-dedicated CAE workstations. The kits offer support for Dazix, Mentor, Valid, and
HP9000 and include:
•

Fujitsu Symbol Model Libraries for the CAE system's schematic capture module

•

A Logic DeSign Rule Check module

•

Fujitsu TIming Model Libraries for the system's simulator

•

A Delay Calculator module

•

Conversion Modules to define the net list and test vectors in the FLDL and FTDL formats required
by Fujitsu software.

1-73

..

Design Procedures

CMOS Channeled Gate Arrays

In addition, Fujitsu now offers FAME (Fujitsu's ASIC Management Environment), a menu-driven design
management program. FAME enables the user to select the technology, the array size, and the package,
to assign the pinout, and to create a design database that is referenced by the other modules to ensure
correct-by-construction design. FAME includes a test vector module that allows designers to edit test
vectors, assists in defining test groupings, cycle times, and strobe settings, and checks created test files
against restrictions.
Fujitsu designs are also supported by several high-performance third party CAE tools. These include:
•

Verilog-XL® (Cadence Design Systems, Inc.) mixed-mode system simulator

•

LASARTM Version 6 (Teradyne) design simulator and test program generator with fault simulation

•

HIL0-3® (GenRad) design verification, fault Simulation, and test generation tools

•

IKOS'M 800 logic validation hardware accelerator

•

Synopsys® Design Compiler™ interactive behavioraVlogic synthesizer

3.3 Workstation Design Procedures

Figure 3-1 shows a flowchart of the design process. Because the function and file names used by each
design system may differ, generalized names for each operation are used rather than system-specific
names for each step in the process.

1-74

CMOS ChaflllfllBd Gate Anays

Design Procedures

CUstomerlDesl ner Environment

I

r---------------~ ~--~------,_--o.__;~nEn~y
A1 = B~ + 'BC
A2=C·D+A1+E
A3 = D(B+C)+(OE)

C InBPuAts
oUz>m
X X X H
L L L L
DO
L L H H
01
~----------~~------~~~
Boolean Equation
Truth Table

~D arl-~--'~-'~

inputclk;
input [7 : 0] data;
output [7 : 0] out;
wire clki, [7 : 0] datai;
~------------~
Behavioral Description

r - CK

----.J
Schematic Capture

..

Back Annotation

Fujitsu Softwa~e Environment

I,,'

i' .,i' .i'

.1

= Optional

Approval and
Purchase Order

Figure 3-1. Workstation Design Flow

1-75

Design Proceduf8/1

CMOS Channeled Gate Arrays

3.3.1 Design Entry
Design entry (schematic capture) is the first step in the design automation process. The designer can use
the schematic editor program of ViewCAD or the applicable workstation software and Fujitsu's symbol
model libraries for schematic capture. In most of the Fujitsu-compatible CAE applications, as in ViewCAD,
circuits can be defined as macros, for use as sub-parts of other circuits. DeSigns can also be entered
using Boolean equations, truth tables, or behavioral descriptions.
3.3.2 Design Synthesis/Optimization
The information entered in the design entry process can be subsequently subjected to design
synthesis/optimization using a behavioraViogic synthesizer such as the one offered by Synopsis.
3.3.3 Logic Data Conversion (FLDL Generator)
Fujitsu's FLDL Generator (FLDLGEN) is a program that uses the results of data input (and design
synthesis, Hused) to create the FLDL file or net list. The purpose of the FLDL file is to provide information
to the Fujitsu software environment for automatic layout and logic simulation.
The designer creates an FLDL control file containing the customer's name, the workstation type, the
revision, the date, and the designer. The FLDLGEN program receives this information from the FLDL
control file and combines it with the schematic data base file created at schematic capture. The FLDLGEN
program can then create an FLDL file that describes the design for the Fujitsu design implementation
software.
3.3.4 Logic Design Rule Check
The Logic Design Rule Check (LDRC) examines the files produced by the schematic capture and Fujitsu
formatting processes for conformity to the design rules of the technology in which the design is executed.
This program is run before simulation because it catches errors that, undetected under normal workstation
design rules, often cannot be tolerated in a Fujitsu gate array. LDRC checks that the design conforms to
the logic design rules applicable to all Fujitsu deSigns, to those unique to a technology, and to those
required by the chosen package type. When hierarchy is used, LDRC checks for hierarchy violations.
Even in the general workstation environment, LDRC is Fujitsu software, written specifically for each
trechnology.
In order to tailor the LDRC to a particular technology, device, and package, the customer enters required
information via an LDRC Control File, which supplies the device and package name and sets the LDRC to
output information in the form of a report either on all nets or only on nets that contain errors.
Errors detected during LDRC can then be corrected before the Logic Simulation Program is run.
3.3.5 Functional SlmulatlonlTlmlng Analysis
The steps that make up the functional simulation and analysis process vary between design
environments. For some workstations, as for ViewCAD, functional simulation is all one step, while jor
others it is three separate steps:
a. Logic simulator data base file compilation

1-76

b.

Delay calculation

c.

Logic simulation and analysis

CMOS Channeled Gate A"ays

Design Procedures

Logic Simulator Data Base File
The logic simulator data base file uses a Fujitsu-supplied library to apply behavioral characteristics such
as component functions, delay parameters, loading factors, and minimum pulse width, set-up time, and
hold time for flip-flops. These values are supplied by the Fujitsu libraries for the appropriate technology.
Input stimulus to the circuit is supplied by the designer in the form of the Control File.
Delay Calculator
Fujitsu provides the program for performing the delay timing calculations. The execution of the program
calculates the delay times unique to each net in accordance with the loading condition (fan-out and
hierarchy) in the schematic data file. These calculated delays are representative of pre-layout loading
conditions.
The calculations for metal loading are based on the same look-up tables and load equations used in the
Design Manual. These loads are subject to change after layout, reflecting the actual metal loads
experienced.
Logic Simulator
The event-driven logic simulator evaluates the outputs of each gate as a function of its inputs and displays
the results as either a waveform drawing or as a data file. Workstation simulations performed under the
influence of the Delay Calculator are vitally important to verification of design functionality and to the
creation of successful test vectors. Using in-circuit application stimulus from the Logic Simulator Data
Base File, simulations are executed in typical, maximum, and minimum modes, with timing checks
enabled, to ensure that the design is responding as expected and is stable under all conditions. The
results are written to a print-on-change file, which is a list of the signals that changed state, their new
state, and the time at which they changed.
3.3.6 Test Data Conversion (FTDL Generator)
Fujitsu's FTDL Generator (FTDLGEN) is a conversion program that translates the Functional Simulator's
output file into the FTDL file. In the process of doing this, it applies Fujitsu tester restrictions to the
simulator results. If any signal or timing violations are detected, the designer is informed so that the
necessary changes can be made to the data file. The final output file of the FTDL Generator becomes the
FTDL File, that is, the test vectors for Fujitsu's simulator as well as for the LSI tester.
3.4 Post-Design Process
At this point, the customer has gone as far as possible in designing a CMOS gate array on a CAE
workstation. Now the design is transferred to the Fujitsu software environment at one of the Technical
Resource Centers for Fujitsu's simulation.
3.4.1 LDRC and TORC
The designer provides the FLDL and FTDL files to a Technical Resource Center usually in the form of
magnetic tape or floppy disk. Fujitsu then checks the FLDL using its own proprietary and more detailed
logiC design rule check to confirm the validity of the logic data and for formatting errors, unconnected
inputs and outputs, loading conditions, etc. The FTDL file is checked by Fujitsu's proprietary test data rule
check, which flags any violations of the published test data restrictions.
3.4.2 Pre-layout Simulation
After the LDRC and TDRC have been run successfully on the FLDL and FTDL, the pre-layout simulation
can be performed. This is a logic simulation run at typical, maximum, and minimum propagation delay
times using estimated metallization capacitance values. If there is no discrepancy between simulation

1-77

Design Procedures

CMOS Channeled Gate Arrays

results and the expected outputs, the design is presumed to be correct. One of two simulators, LBS6 or
ViewCAD, runs functional simulations and timing verification including the checking of set-up and hold
time, pulse width, and removal times.
3.4.3 Automatic Layout
After a successful pre-layout simulation has taken place and customer approval has been obtained, a
proprietary Fujitsu application performs automatic placement and metal interconnection routing.
3.4.4 Post-Layout Simulation
Post-layout Simulation, also known as final validation, is again performed at typical, maximum, and
minimum propagation delay times, but using actual calculated capacitance based on the metal
interconnection routing resulting from automatic layout. Customers who are using ViewCAD can perform
the Fujitsu pre-layout and post-layout simulation themselves using the ViewCAD software to provide a
sign-off quality design before the design files are even turned over to Fujitsu.
3.4.5 Fault Grading
After post-layout simulation is completed, customers have the option of requesting that Fujitsu subject the
test data to a process called fault grading. This CPU-intensive process analyzes the customer's circuit
and test data to calculate the percentage of fault coverage. The input test data is analyzed to determine
the adequacy of the stimulus patterns to detect any "stuck" (malfunctioning) nodes. The result, a report of
all nodes not tested by the stimulus provided, is given to the customer. The customer then has the option
of either changing the test vectors or acknowledging that the untested nodes are acceptable.
3.4.6 Sample Fabrication
After a successful post-layout simulation has been performed and customer approval has again been
obtained, engineering samples of the array are fabricated for customer evaluation.
3.5 Engineering Sample Testing
3.5.1 LSI Tester
Once sample chips have been fabricated, they are tested on the LSI Tester, a test instrument located at
the manufacturing facility. Sample chips are tested with input test patterns and expected outputs obtained
from the FTDL file.
One of the most important tasks of post-layout simulation is to validate the test vectors for later use on the
LSI Tester. For this reason, simulation is executed under conditions adhering as closely as possible to the
conditions imposed by the tester. A device that passes all phases of simulation Is likely to pass the LSI
tester.
The limitations of the LSI Tester place various restrictions upon test data. These restrictions must be
respected when preparing the test data pattern and when creating the (stimulus) Control file for running
workstation simulations. A summary of test data restrictions for each technology is included in the
appropriate DeSign Manual.
Test data restrictions involve such issues at the numbers of test patterns acceptable for each test type, the
minimum test cycle length, input signal timing, output strobe timing, bidirectional buffer Simulation, input
and output cycle timing, tester skew, and the treatment of data Signals.
Tests performed on the LSI Tester include the function test, the delay test, the DC test, and the high
impedance ("Z function") test. Specific data found in the UHB or CG1 0 Design Manual must be included in
FTDL to perform each of these tests.

1-78

CMOS Channeled Gate Arrays

Design Procedures

3.5.2 Function Test
The function test guarantees the designed function of the gate array by exercising as many of the internal
nodes as possible and detecting functional failures. Fujitsu requires the function test because it is the
primary means of determining if an ASIC is functioning properly as it comes from manufacturing.
In the course of the function test, input signals are applied in accordance with customer timing
specifications, using worst-case input voltage at a clock frequency not to exceed 16 MHz (a period of
63 ns). The dynamic performance of this test also partially verifies the AC characteristics of the device.
The function test may be run in multiple units (blocks), allowing changes to be made in the test vectors to
assure thorough testing of the device. The transition from one block to the next requires that the device be
powered off, adjustments made to the tester, and pins regrouped as required. After all changes have been
made, the test is restarted. For this reason, each test block must re-initialize the circuit.
3.5.3 Z-Functlon Test
The Z-Function test is administered in the last block(s) of the function test. Its purpose is limited to the
verHication of the high-impedance function of 3-state and bidirectional output buffers. The Z-function test
is necessary only when there are two or more logic combinations that can generate the high-impedance
state for a given I/O cell. The test can verify all these logic combinations. If only one logic combination
generates the high-impedance condition, then the DC test is adequate.
3.5.4 DC Test
The DC test, as its name implies, verifies the DC characteristics of the array. It is not intended to check
circuit functionality, but it can be used as a function test of 3-state circuits having only one signal path that
generates the high-impedance condition.
The designer supplies the sequence of input signals and expected outputs in the FTDL. These test
patterns must generate every possible state for every type of output and input buffer being used (high,
low, and high-impedance).
The DC test applies the designer-specified input signals to measure the following DC parameters:
a.
b.
c.
d.
e.

Steady state power supply current (Ioos)
Output high voltage (VOH)
Output low voltage (Vou
Input leakage current (Ill)
High-impedance output leakage current (lLZ)

3.5.5 Delay Test
The delay test is optional. It is used to verify critical paths or as a means to characterize the device by
testing a small number of paths. The purpose of the delay test is to check that signal paths from various
inputs of the chip to their respective outputs meet the customer's standards for minimum and/or maximum
delay times. The paths may be sequential and/or combinatorial but only the propagation delay, not the
toggle frequency, is measured.
3.6 ATG Testing and Scan Design
ATG testing is a special technique that supplements the customer's submitted test patterns (FTDL) to
assure both Fujitsu and the customer of a highly reliable gate array by achieving a high degree of fault
coverage. ATG testing is implemented by using scan design techniques described at the end of
Chapter 4, Design Considerations. Scan test patterns (both applied input stimulus and expected outputs)
are automatically generated by Fujitsu's Automatic Test Generator (ATG) software. ATG is offered by
Fujitsu for partitioned arrays of the UHB and CG10 technologies and for all arrays in the channelless gate
array technologies (AU, CG21, and CG31).

1-79

..

Design Procedures

1-80

CMOS Channeled Gate Arrays

CMOS Channeled Gate Anays

Design Consid9f'ations

Chapter 4 - Design Considerations
Contents of This Chapter
4.1
Introduction
4.2
Basic Cell Usage
4.3
Designing for Reliability and Testability
4.4
Designing for Speed
4.5
Bus Circuit Design
4.6
I/O Design
4.7
Designing for Scan Test Technology

4.1 Introduction

This section of the data book gives an overview of the logic and I/O design considerations that are
important for a successful design in Fujitsu's CMOS channeled gate array technology. Specific design
recommendations for each technology can be found in the Design Manual for that technology.
4.2 BasiC Cell Usage

In order to benefit from fully automated layout, a designer may use no more than 90% of the actual cell
count of a UHB or CG1 0 gate array. The actual cell count is the number of basic cells used in the device.
In Fujitsu's channeled CMOS technologies, the unit cells are grouped in double columns alternating with
wiring channels. Within the columnar architectures, unit cells are always constructed on a double column,
Le., a unit cell cannot bridge the wiring channel between two basic cell columns. This limits the number
and complexity of unit cells that can be placed on a column.
The number of inputs and outputs and therefore input and output buffers required also limit the number of
basic cells available for logic design since internal basic cells are also used for input/output buffer cell
implementation.
4.3 Designing for ReliabliHy and Testability

Following the design guidelines below ensures maximum testability and therefore reliability of a design:
a.

External signal paths must be interfaced to the array by an I/O buffer.

b. Only one I/O buffer cell can be connected to an external terminal.
c.

Inputs to the same cell may not be tied together.

d.

Inputs to two or more input buffers may not be tied together.

e.

Unused inputs must be tied high or low using clip cells ZOO or Z01, never left floating.

f.

The outputs of a unit cell other than 3-state bus macros may not be wire-ANDed. Generally, if
output functions must be tied together, they must be combined through a logic function.

g. Outputs of unit cells should not be left open. In the case of flip-flops, latches, shift registers, or
counters, however, outputs may be left open if at least one output is connected.
h.

Functions such as one-shots and other monostable or astable circuits cannot be incorporated into
a Fujitsu CMOS gate array. All logic state changes detected at the output of the array must be
predictable for the purpose of test, and as such, be the direct result of changes of input stimulus.

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Design Considerations

CMOS Channeled Gate Anays

i.

Series inverters must not be used for the purpose of creating a delay. Fujitsu supplies delay unit
cells to assist the designer in solving timing problems such as set-up and hold time requirements.
The designer should not, however, use delay cells to construct asynchronous circuits (one-shots or
glitch generators).

j.

Circuits incorporating sequential devices (for instance, flip-flops, counters, shift registers, and so
on) must have a traceable method of initialization designed into the circuit, independent of
feedback loops.

k.

No logic function should be incorporated within the array if it cannot be directly or indirectly set or
initialized from a primary input.
Designers have two choices for initialization:
1. Supply an external signal (for CLEAR, LOAD, etc.).
2. Supply known inputs and allow time for them to propagate through the circuit. If the
propagation method is used, UNKNOWN ("X" state) must be an acceptable output state
until the initialization is completed.

4.4 Designing for Speed

In general, signal delays are caused by the Signal having to travel through more gates or over longer
distances, especially to enter a different block in gate arrays having block architecture (partitioned arrays).
Delay is proportional to length of interconnection metal along which the signal must travel. The following
recommendations are therefore made to optimize overall design speed by minimizing the interconnect
metal length.
4.4.1 Hierarchical Design

Devices that are not physically partitioned do not allow the designer to control relative path lengths. It is
highly recommended, therefore, to design hierarchically, dividing the cell into blocks and the blocks into
sub-blocks so that functional groups of unit cells are laid out in close proximity and signals have less far to
travel. When it becomes necessary to link blocks, the use of high-power "high-drive" unit cells is
recommended to drive signals in the inter-block metal.
It is especially helpful to use hierarchical design for the three largest arrays in the UHB and CG10 series.
Not using hierarchy design for these larger arrays imposes a risk of considerable difference between
estimated interconnection loading and actual layout loading values.

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Design Considerations

CMOS Channeled Gate A"ays

The suggested hierarchical structure for the larger arrays is a division of the array into four quadrants as
shown in Figure 4-1. Each of these quadrants is considered a level 1 listing under the CHIP level. See
Figure 4-2.

Figure 4-1. Arrangement of Hierarchical Blocks

Figure 4-2. Recommended Hierarchial Organization of UHB/CG10 Designs
The CHIP level is the highest level in the hierarchy and represents the entire chip. All 110 cells are defined
immediately below the CHIP level, along with any clip cells they may require.
Levell blocks must be defined immediately beneath the CHIP level and cannot exceed eight in number
(when used for digital logic). Unit cells cannot be described immediately beneath the CHIP level.
Level 2 is defined beneath the Levell blocks, Level 3 beneath Level 2, etc. Levels must always be
defined in numerical order. There is no limit to the number of Level 2, Level 3, or Level 4 blocks that may
be used (when defined below a higher block level). Unit cells may be defined beneath Levels 2, 3, or 4,
but the lower in the hierarchy the unit cells are defined, the greater the designer's control of delay will be.
Any level may be the first defined under the CHIP level and any of the levels may be omitted; however,
the more the designer deviates from the standard structure, the greater the differences between estimated
pre-layout delay and actual post-layout delay will be.
The recommended number of basic cells per each quadrant of an array is shown in Figure 4-1. It is highly
recommended that the designer adhere to the guidelines in this table since the tables of estimated
metallization load for the cells are based on these block sizes. The basic cell level counts overlap from
level to level. The designer may select either of the levels covered by the cell count, but must also use the
appropriate table of estimated metallization load for delay calculations.

1-83

CMOS Channeled Gate Arrays

Design Considerations

Table 4-1. Basic Cells per Quadrant
Array/Series

Minimum Bc/Block

6000UHB

1000

Maximum Bc/Block

2500

8700UHB
12000UHB

1500
2000

3000
4000

0010692

1200

2600

0010103

1700

3400

0010133

2300

4300

4.4.2 Clock Line Design
A clock network is a circuit used for the efficient distribution of an external clock signal to the clock input of
internal sequential and combinatorial unit cells. Clock skew is the differential delay of a clock signal as it
proceeds through a system; it is determined by the types and relative positions of the gates and blocks
within the array. Clock networks must be optimized to minimize skews for both internal and inter-chip
clock distribution to ensure accurate high-speed operation.
The designer can optimize clock networks by using dedicated input buffers called clock input buffers and
dedicated unit cells called clock distribution buffers.
Clocks must enter the array through the clock input buffers. They should be further distributed via the
clock distribution buffers. Proper use of clock buffers to boost signal strength and balance loads reduces
the problems of clock skew and clock pulse variation. The locations of clock input buffers for signals with
frequencies greater than 5 MHz are limited to paths on two sides of the die. The number of such buffers is
limited depending on the size of the array, as specified in the design manual for each technology.
External clock signals must be wired in parallel with chips; once inside the chip, clock signals must be
wired in parallel with logic blocks.
4.5 Bus Circuit Design
The UHB and CG10 families have special provisions for implementing high-performance internal3-state
buses. The internal 3-state bus can be implemented on the chip using bus driver cells and bus terminators
that maintain the last logic level on each bus line when all bus drivers switch to their high impedance
state. The bus terminator maintains this logic level until any bus driver begins to drive the bus line. The
bus terminator is invisible to a logic designer; it is connected to each of the bus lines automatically by
Fujitsu's CAD software. It uses only one basic cell per bus line.
The number of internal 3-state buses permitted depends on the technology and on the size of the gate
array and the bus width (number of bits per bus) required. Table 4-2 shows the number of bus driver cells
permitted per UHB chip; Table 4-3 shows the number of bus driver cells permitted per CG1 0 chip.

1-84

Design Considerations

CMOS Channeled Gate Arrays

Table 4-2. Maximum Number of Bus Driver Cells per Chip (UHB)
Maximum B41
Bus Driver Cells

Device Name
C330UHB

4

C530UHB

5

C830UHB

6

C1200UHB

8

C1700UHB

12

C2200UHB

16

C3000UHB

21

C4100UHB

26

C6000UHB

50

C8700UHB

70

C12000UHB

90

Table 4-3. Maximum and Recommended Number of Bus Driver Cells per Chip (CG10)
B41 Bus Driver Cells

B11 Bus Driver Cells

Device Name

Maximum

Recommended

Maximum

Recommended

CG10272

22

19

88

76

CC10392

26

23

104

92

CG10492

30

27

120

108

CGl0592

34

30

136

210

CG10692

72

64

288

256

CGl0l03

105

94

420

376

CGl0133

144

128

576

512

In the largest three arrays of both the UHB and CGl 0 technologies, there is also a limit on the number of
bus driver cells per block (UL, UR, LL, LR, as shown in Figure 4-1) if the array is divided into the four
recommended hierarchical blocks .
The maximum number of B41 bus driver cells (or CG10 Bl1 bus driver cells) permitted in each block is
calculated using the following formulas.
B41 Bus Driver Unit Cells
CG10692

(number of basic cells per block 11 00) - 1

CG10103

(number of basic cells per block 11 00) + 1

CG10303

(number of basic cells per block 1100) - 5

C6000UHB

(number of basic cells per block 11 00) - 2

C8700UHB

(number of basic cells per block 11 00) + 1

C12000UHB

(number of basic cells per block 11 00) - 4

1-85

Design Considerations

CMOS Channeled Gate Arrays

B11 Bus Driver UnH Cells
The maximum nuni>er of B11 bus driver cells permitted in each block is determined by multiplying the
permitted number of B41 bus driver cells by 4.
For example, if there are 3480 basic cells in a block of a CG10131 array:
3480/1 00 - 1 = 33.8
Therefore, a maximum of 33 B41 s can be used in that block.
33 x4 =132
A maximum of 132 B11s can be used in that block.
4.6 1/0 Design

4.6.1 Pin Assignment Guidelines
The following parameters apply to the assignment of I/O pins:
a. All Vss pins must be tied to ground.
b. All Voo pins must be tied to 5 volts.
c.

Voltage and ground pins are predetermined by the package type and cannot be altered.

d. Pins deSignated "No Connection" cannot be used.
e. Additional Vss and Voo pins may not be assigned by the designer without first negotiating this
deviation with Fujitsu.
f.

Fujitsu recommends thatthe designer assign the pin numbers to the circuit in the' ASSIGN or
'OPTION section of FLDL or submit the complete pin assignment table with the design. It is also
possible to allow the Technical Resource Center to do the assignment automatically using Fujitsu's
design software or manually from a customer-supplied form.

g. The maximum output low current (IoU must not exceed 70 mA per Vss Pin.
4.6.2 Simultaneously SwHchlng Outputs (SSOs)
Outputs are defined as switching simultaneously when they switch from a logic low (or a high impedance
state) to a logic high or switch from a logic high (or high impedance state) to a logic low within 20
nanoseconds of each other.
Simultaneously switching outputs increase the momentary charge/discharge current flow at the gate array
and cause noise in the form of momentary spikes or ringing in the power and ground lines.
When the ground level is raised by the nOise, the input threshold voltage of the gates is also raised,
relatively, for the duration of the impulse (as illustrated in Figure 4-3). If VTH rises, momentarily, above the
VIHmin level, a logic high with a level just above VIHmin will be recognized as a low level for the duration of
the spike. Similar problems are experienced when the ground level is depressed by the nOise, affecting
logic low levels close to VILrnax.
The greater the number of SSOs, the greater the noise produced. Therefore, this noise, which may
appear as signals to the CMOS logic, must be avoided.

1-86

Design Considerations

CMOS Channeled Gate Arrays

V1H

V
I
--------

I
I
I

V

r----------

I

A

I

o

V1H(min.) = -2.2 V

VTH

u

V 1L

V1dmax.) = .08 V

GND Level
! -

Figure 4-3. SSO-Generated Noise
The severity of the effect of SSOs is determined by:
•

The number of SSOs

•

The density and distribution of SSOs in the package

•

The size of the load capacitance being driven

The number of SSOs allowed in a package is restricted by the number of ground (Vss) pins available, the
drive capability of the output buffers, and the location of ground pins on the package (See the Available
Package and Pin Assignments section in the appropriate Design Manual). Representative values have
been assigned to the effects of output buffers per single ground pin. Output buffers are capable of 3.2 mA,
8 rnA, or 12 rnA drive capability, and each may be selected with an optional noise-limiting resistance
(NLR) value to minimize generated switching noise. The representative values are given in Table 4-4.
Table 4-4. Representative Value of Output Buffers
Output Buffer
Normal Drive wnh NLR (loL = 3.2 rnA)

Representative

Values

(per

Output)

7

High Drive with NLR (IOL = 8 rnA)

12

High Drive with NLR (loL = 12 rnA)

14

High Drive with NLR (loL = 24 rnA)

26

Normal Drive (loL = 3.2 rnA)

10

High Drive (IoL = 8 rnA)

16

High Drive (IoL = 12 rnA)

20

The sum of the representative values for each of the SSOs used in a design must not exceed 80 per Vss
pin, regardless of the type of package used.

1-87

..

CMOS Channeled Gate MayS

Design Considerations

4.6.3 Maximum Load per Ground Pin
The maximum total output load per ground pin is limited as a function of the output switching frequency.
The product of the output switching frequency in MHz and the total output load in pF per ground pin
cannot exceed 12,700 pF x (frequency in MHz), at the maximum junction temperature, Tjmax, of 70°C. As
the junction temperature increases, the allowable maximum load per ground pin decreases per the
following formula:

ex (s ( 12,700 x Kt) pF x (([MHz] I(number o( ground pins)
where

C = the output load, in pF

( = the output switching frequency, in MHz
Kt = the junction temperature coefficient of load, a constant determined from Table 4-5.
Table 4-5. Junction Temperature Coefficient of Load
Tjllax °C

Kt

70

1.0

85

0.7

100

0.5

125

0.3

150

0.2

4.6.4 Maximum Load per Output Pin
The maximum total output load per output pin is limited as a function of the output switching frequency.
The product of the output switching frequency in MHz and the total output load in pF of any pin cannot
exceed 1200 pF x (MHZ, at a maximum junction temperature (Tjmax) of 70°C. As the junction temperature
increases, the allowable maximum load per output pin decreases per the following formula:
C x (S (1200 x Kt)pF x (([MHz] I(number o( ground pins)

where

C

= the output load, in pF

(

= the output switching frequency, in MHz

Kt = the junction temperature coefficient of load, a constant determined from Table 4-2.

4.6.5 Pin Assignment Guidelines
The locations of all Vss and Voo pins are predetermined and fixed. Since the placement of SSOs on any
package is critical, SSOs must be assigned within certain pin groups. Within these pin groups, other
restrictions apply regarding the separation of SSOs from each other or their proximity to the Vss pins.
As noted above, the total representative value of any SSO group shown in Table 4-4 must not exceed 80.
The SSO pin groups differ between packages. The package outlines and designated grouping of SSO
pins for specific devices are shown in the Available Packages and Pin Assignment section of the
appropriate Design Manual.
As a general rule, however, the pins available for SSOs between two Vss pins are assigned as shown in
Figure 4-4.

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Design Considerations

CMOS Channeled Gate Affays

,

JL
2

a

/
0

~

~

0

0

, 0

0

"

~ ~

N Pins

Vss

Figure 4-4.
•

b

,,:/
,

Vss

ssa Pin Assignments

Assume that N pins exist between adjacent Vss pins
Find the center point on the package between the two Vss pins
There are N/2 pins in the area between the center point and the first Vss pin (part A), and N/2 pins
in the area between the center point and the second Vss pin (part B)
The SSOs must be equally distributed between parts A and B, within ±1

4.6.6

ssa Pin Placement Summary

The following is a general summary of recommendations for the placement of pins.
a.

SSOs must be placed in close proximity to Vss pins.

b.

High-drive SSOs should be placed closer to Vss pins than normal-drive SSOs.

c.

Asynchronous inputs such as clocks, presets, and clears should be kept away from SSOs. It is
preferable that these inputs be placed close to Vss pins, if available, and away from SSOs.

d.

Clock, preset, and clear inputs must not be placed on the corners of a package, especially when
the array is packaged in a DIP.

e.

Output signals to be used as clock, preset, or clear for other devices must be kept away from SSOs
and close to a Vss pin.

f.

SSOs should not be placed in the outer row of pins of PGA packages.

4.6.7 Test Pins
To facilitate testing, external pins should be provided whenever conditions warrant. The addition of
supplementary test pins often allows the reduction of the overall test complexity for a circuit, thus reducing
the number of test patterns required and the time necessary to determine functionality of the circuit.
4.7 Designing for Scan Test Technology
Scan testing is a supplementary, optional test technique that, when used in conjunction with the function
and DC test required of the designer, allows greatly increased fault coverage. This increased fault
coverage assures both Fujitsu and the designer of a highly reliable gate array.
4.7.1 Scan Test Design
The designer implements scan testing by arbitrarily connecting all the sequential logic elements to form an
enormous shift register. This shift register can contain up to 3000 stages and is formed by connecting the
Q-output of one stage to the dedicated scan input (SI) of the next. If the Q-output cannot be used for this

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CMOS Channeled Gate Arrays

Design Considerations

purpose, then the XQ-output may be used, but an inverter must be placed between the XQ-output and the
SI input of the following stage in order that the data not be inverted.
To implement scan testing, designers use special scan-compatible unit cells for all sequential logic
functions. With the use of the serial scan method, the difficult problem of testing a logic circuit containing
both combinatorial and sequential logic is simplified to testing combinatorial logic and a shift register, as
shown in Figure 4-5 below.

SFF

SFF

SFF

V1N

SFF

Q

Q
~------..

I

SI:

SI
SFF

SFF

Figure 4-5. Scan Circuit Configuration
Dedicated scan inputs are also used to isolate elements that are not part of the scan test path. Some of
these elements can also be tested during the scan test cycle by the use of an alternate scan test mode.
The scan chain design can be considered a data carrier with the ability to carry test input stimulus
provided by the LSI tester deep into the design and to apply it to the unit cells under test. Once a unit cell
has been tested, its output test result may be stored in the scan data chain and be carried out of the
design for comparison to that which was expected. To the deSigner, scan unit cells perform exactly the
same as non-scan unit cells, the only difference being the provision of additional basic cells to facilitate
the scan test.
Scan testing usually entails an extra 8 to 20 percent basic cell count, requires the use of seven extra 1/0
pins, and can cause some degree of propagation delay. Nevertheless, when absolute reliability is the
issue, designers find that these considerations are within an acceptable range.
4.7.2 Test Pattern Generation
A circuit that is designed for scan testing in this way allows Fujitsu automatic test pattern generation
(ATG) software to generate the scan test patterns automatically (both applied input stimulus and expected
outputs). The ATG software uses the logic design data from the FLDL file as input from which it generates
the test patterns for scan tests. The process requires that all sequential unit cells be of the scan type with
the exception of data latches YL2 and YL4. Inclusion of non-scan sequential circuits constructed with
combinatorial logic, (i.e., NAND-gate flip-flops, NOR-gate flip-flops, etc.), are discouraged in a scan
design because they reduce the overall fault coverage attainable with scan testing. If their use is
unavoidable, they must be disabled or isolated by one of the scan test signals discussed below during the
ATG process and the scan test.
Scan testing is optional and is applicable only to digital logic unit cells.

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Design Considerarions

CMOS Channeled Gate Arrays

4.7.3 Scan Test Signals
Scan test implementation requires the assignment of a dedicated output pin and up to six input pins, six of
which are in predefined package locations. The package locations for these pins in each device type are
shown in the Available Package and Pin Assignment section of the appropriate Design Manual.
Pin Name

Description

1. XACK is the scan input, scan output (5150) A-clock signal. It is generated by the LSI tester and is
applied, inverted, to all scan devices at their A-clock input. It writes data from the unit cell's
scan input to the master latch.
2. BCK is the SISO B-clock signal. It is generated by the LSI tester and is applied, inverted, to all scan
devices at their B-clock input. It transfers data between the unit cell's master and slave latches
(the output of the device).
3. XSM is the 5150 mode signal. It is used for set-up of bidirectional buffers, bus drivers, and RAM. If
bidirectional buffers or bus drivers are not used, then XSM is not required and need not be
included in the design.
4. XTST is the scan test signal. It is used to reconfigure the array to make it suitable for scan test and to
establish all conditions required for the use of Fujitsu's ATG software. This includes the
isolation or removal of certain circuits unsuitable for scan testing, such as non-scan sequential
functions and the asynchronous inputs of all sequential elements. (Since they are inaccessible
to scan testing, these circuits and disabled functions must, therefore, be tested with
user-prepared test patterns.)
If all sequential functions utilize scan type unit cells, if no asynchronous functions are
employed (including direct sets and clears), and if circuit isolation is not required, then XTST is
not required and is not provided for.
S. XTCK is the TC mode clock signal. It is generated by the LSI tester. It is applied, inverted, to the
IH-inputs of all sequential unit cells.
6. SOl
is the serial data input port to the first device of the scan path from outside the Chip. It is
connected to the 51 port of the unit cell. Test data entering the SI input in subsequent devices
in the scan path is derived either from the Q-Output of the immediately previous stage or via
an inverter from the XQ-output.

7. SOO

501 is the only one of the scan test ports that may be used for anoiher function. The designer
may use 501 as a prinCipal input by paralleling the user input with the scan data input.
is the serial data output port from the last device of the scan-configured shift register to the
environment outside the chip. Test data from 500 is taken from the C-output of the last stage
(or from the XC-output via an inverter) of the giant scan shift register. 500 is the only one of
the scan test ports whose location is not fixed; 500 may be placed by the designer at any
convenient location.

4.7.4 Scan Test Modes
Scan testing consists of two modes of operation: 5150 (Scan inpuVscan output) mode and TC (test clock)
mode. Sequential logic is primarily addressed by 5150 and combinatorial logic is addressed by TC; the
two modes are alternated during the scan test.
The SISO Mode
This mode causes all elements of the scan path to be written to and read from. In this mode of operation,
the following occurs:
a. The scan 5150 path is activated by making XSM

=

0

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Design Considerations

CMOS Channeled Gate Arrays

b. The scan clocks XACK and BCK are supplied
c.

The data to be written is supplied to SDI serial data input

d. The data is read out of SDO and compared with the expected values
These writing and reading operations are performed in parallel.
TheTC Mode
This mode tests the array as a normally configured device, but the data is clocked by special clocks
provided to the gate array by the LSI tester. In this mode of operation, the following occurs:
a. The scan SISO path is disabled by making XSM = 1.
b. All normal system clocks are disabled, forcing the clock inputs (CK) of all scan unit cells to a logic
low.
c.

Input signals are applied to the normal input pins' principal inputs.

d. The TC system clock, XTCK, is applied to the unit cells' IH-inputs.
e. Output signals are read from the normal output pins' principal output and compared with the
expected values.
The alternation of these two modes allows the correct functioning of logic elements not directly accessible
from a prinCipal input to be verified. The data scanned in is especially useful in providing control inputs to
otherwise difficuH-to-control internal logic. Prior to the input of the data to the scan path, some detectable
fauHs can be observed externally by application of data to some non-scan external inputs. After data has
been clocked into the scan path, other detectable faults can be observed externally. The remaining
detectable fauHs are observable externally after the data has been clocked into the scan path, the TC
system clock (XTCK) has been applied, and the resuHant data shifted out of the scan path.

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CMOS Chann9led Gate Arrays

Delay Estimation Principles

Chapter 5 - Delay Estimation Principles
Contents of This Chapter
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9

Introduction
Choosing Critical Paths
Load Units and Loading Guidelines
The Delay Equation
Estimating Gate Delay
Estimating Total Circuit Delay
Delay Calculations when Load Exceeds CDR
Delay Calculations and the Operating Environment
Clock Loading

5.1 Introduction
This section of the data book gives an overview of the engineering considerations important to the design
of an ASIC using Fujitsu's CMOS technologies. Included are the loading rules for CMOS gate arrays and
a demonstration of how to estimate the delay through a circuit. In addition to the basic delay equation, this
chapter also considers the loading limitations for clock signals and the effects of the operating
environment on typical delay figures.
5.2 Choosing Critical Paths
A critical path is a logic path whose timing requirements must be satisfied to ensure proper system
function. In an ordinary synchronous circuit, data propagates from one register through combinatorial logic
into another register. For the circuit to function properly, the sum of the clock-to-Q delay of the source
register, the propagation delay through the logic, and the set-up time on the target register must be less
than the worst-case system clock period. Correct timing of the signal along the critical path guarantees
that this condition is met.
Usually, the critical path is the one with the greatest number of gate levels. However, if such a path is
speeded up by redesign, another, less complex path may become the new critical path.
For example, in a design in which a path has eight levels of gating, the designer may determine upon
inspection that two groups of NAND-NAND structures can be changed to AND-OR inverters, an efficient
CMOS implementation that noticeably increases the speed of the path. In this case, aiter applying
DeMorgan's theorem and reducing the result, the designer finds that another path is now the critical path.
Since each logic state sensitizes different branches, logic paths must be analyzed using the inputs (rising
or falling) that will actually be applied to them (since riSing and falling delays are not equal) to determine
the longest path that will be sensitized and ensure that it meets critical path requirements.
The path delay calculation worked through in this section shows how a designer can analyze each
element of a Fujitsu CMOS circuit to make sure the design meets critical path requirements. In this case,
the effect of a riSing input on the sample circuit is calculated as it would be if this were a critical path and
the riSing input were forcing the transition of interest.

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Delay Estimation Principles

5.3 Load Units and Loading Guidelines
The Fujitsu CMOS load unit (Iu) is the input capacitance of an inverter used as the basic unit for
measurement and calculation of capacitive loads presented to unit cells within the gate array. Both the
output drive factor of a unit cell and its input load factor are defined in terms of load units. Both factors are
listed for each unit cell in the unit cell library for the appropriate technology.
5.3.1 Output Drive Factor
The output drive factor (CDR) is a parameter expressing the load driving capability of a unit cell. Unit cells
can drive loads greater than the output drive factor. The performance of CMOS circuits degrades
exponentially with increased loading; if too great a load is driven. an exaggerated increase in delay
through the unit cell may be experienced.
It is permissible for the load to exceed CDR if the associated additional delays are anticipated and
tolerable. Additional calculation factors are required to estimate delays of loads greater than CDR.
Figure 5-1 indicates the delays that may be generated when the load exceeds these guidelines.

-r-----

tpd
(ns)
3KcL

x (C -

2COR )

____________1____ _

t--------------------------- -~~~~---1.5KcL X CDR

-------------

to

o

o

2COR

3COR

Total Load (in terms of

4CoR

C(lu)

CDR)

Figure 5-1. Delay Time vs. Loading Factor
5.3.2 Input Load Factor
The input load factor of a unit cell is used to estimate the propagation delay of a critical path in a design.
The total propagation delay of a path is defined as the sum of the delay factor of each of the unit cells in
the path.
5.3.3 Delay Factor
The delay factor of each unit cell is made up of two types of capacitive loading:
a. Load capacitance inherent in the input of each cell (the input loading lactor)
b. Load capacitance due to the metal interconnection 01 unit cells (CLl
The total load (C) presented by a unit cell is estimated by adding the total cell input load or NF/o (the input
loading factors of all other cells connected to the output network of the cell in question) to the total metal
load (Ct.).
orC = NF/o + CL

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Delay Estimation Principles

CMOS Channeled Gate Arrays

5.4 The Delay Equation
The basic delay equation combines the AC parameters of a cell and its associated capacitive loads to
estimate the delay time through the cell. The rise and fall time of a unit cell may not be symmetrical due to
differences in the transconductivity of the Nand P transistors as well as to differences in the arrangement
of the transistors to form unit cells. The same equation is used with different variables for positive'going
and negative-going signals at the unit cell output. These signal polarity variables must be considered
separately.
fup
~

= toup + KCLup(NFIO + CL)
= todn + KCLdn(NFIO + CL)

where:
toxx

is the circuit delay through the unit cell under no-load conditions (a value given in ns for each
cell in the unit cell library).

KcLXX

is the load derating constant or delay time per loading unit conversion factor (ns/pF) defined
for each unit cell (and given in the unit cell library).

NFIO

is the sum total of the input loads of all unit cells driven on the net (expressed in load units).

CL

is the amount of loading, in load units, on the unit cell output due to interconnect metal (metal
load).

The term "net" refers to the network of metal wiring connecting all the unit cells driven by a specified unit
cell. Interconnect metal refers to the metal wiring, also called routing metal, that makes up each net.

5.5 Estimating Gate Delay
Figure 5-2 shows a sample circuit for the purposes of demonstrating how the total accumulated delay
(tpd) through a short path is estimated.
A

B

c

D

INo---;~

OUT

V2B

t

t

Figure 5-2. Delay Path Sample Circuit
Ordinarily a designer looks up the the specifications of each unit cell in the unit cell library of the
applicable technology. For this example, however, all of the necessary specifications have been
assembled in Table 5-1, using the values for UHB technology.

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CMOS Channeled Gate Arrays

Delay Estimation Principles

Table 5-1. AC Parameters of UnH Cells
Input
Load
Factor

Output
Drive
Factor

Propagation
t ...
to
I Kcl

Delay Time

Cell
Name

Basic
Cells
Used

2-lnputNOR

R2K"

2

2

36

0.45

0.14

0.45

0.06

2-lnput NAND

N2N

1

1

18

0.37

0.16

0.56

0.14

3-lnput NAND

N3B"

3

1

36

1.28

0.08

1.70

0.04

Inverter

V2B

1

2

36

0.25

0.08

0.25

0.05

Cell
Function

let.
to

Kcl

"These are high drive cells that operate faster than their low drive equivalents under these
circumstances.
The delays for rising (tup) and falling (tdn) edges of a pulse can differ widely. Digital pulses are either
lengthened or shortened while passing through a unit cell. It is therefore important to calculate the pulse
width variations along the entire signal path to verify that pulse width is sufficient to pass through each
gate.
In the example that follows, based on Figure 5-2, calculations are based on a rising pulse entering the
input of unit cell A and changing state several times as it proceeds through the sample circuit. To find the
total delay for the circuit, it would be necessary to calculate the values resulting from the opposite case, in
which a falling pulse enters the circuit at unit cell A.
5.5.1 Delay Parameter for Rising Edge (tup)
The unit cell library shows that the delay time (to) for an upward transitioning signal at the unit cell output
(tup) for R2K, a 2-input NOR, is 0.45. It shows that the load/delay conversion factor for an upward
transitioning signal (KCLup) for R2K is 0.14.
5.5.2 Number of Fan-outs (NF/O)
The sample schematic in Figure 5-2 shows that the NF/O, the number of cells that the R2K must drive, is
one (an N2N). The unit cell library shows that the N2N has an input load factor of 1 lu.
5.5.3 Number of Driven Inputs (NOI) and Metal Load (Cd
The value for CL is based on the number of inputs the cell in question must drive and is derived from the
Estimation Tables for Metal Loading at the beginning of the unit cell library. Table 5-2 is a sample metal
load table; each technology and device has unique load/delay characteristics. Since the number of driven
inputs (or NOI) for R2K, N2N, and V2B in Figure 5-2 is one, the amount of loading due to metallization (L)
is 1.0 lu. The NOI for N3B in Figure 5-2 is three; therefore the CL is 3.0.

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CMOS Channeled Gate Arrays

Delay Estimation Principles

Table 5-2. NOI vs. CL"

NOI

CL(lu)

1
2
3
4
5
6

1.0
2.2
3.0
3.5
3.9
4.2
4.6
4.8
4.9
5.0

7
8
9
10

• For a 330UHB gate array.
The value given for CL in the Estimation Tables for Metal Loading is an estimate of the loading effect of
the metallization capacitance on the output based on Fujitsu's careful statistical analysis of typical
designs. Actual metal loading is based on the effect of the routing and therefore may vary from these
estimates. To compensate for this uncertainty, Fujitsu incorporates a ± 5 percent variation into the
prelayout delay multipliers. After routing, another set of simulations is run to verify the effect of the actual
metal routing.
Note:

In an array partitioned into blocks, if the interconnected unit cells are located in different blocks,
the loading is greatly increased. The deSigner can avoid this worst-case situation by using the
hierarchical approach during the schematic capture process to confine circuits to one block
whenever path delay is critical.

5.6 Estimating Total Circuit Delay
Based on the values from Table 5-1 and Table 5-2, the propagation delay for R2K in the sample circuit is:

fdn A

tcJn
tcJn
fdn
fdn
fdn A

= Wn

+ KCLdn (NF/o + CL)
0.45 + 0.06 (1 +1.0)
0.45 + 0.06 (2.0)
0.45 + 0.12
0.57
0.6
(rounded up to the next 0.1 ns)

The propagation delay for N2N, found by following the same procedure, is:
lup B
lup
lup
lup
lup
lup B

= laup

+
= 0.37 +

KcLup (NF/o + CL)

0.16 (1 + 1.0)
= 0.37 + 0.16 (2.0)
= 0.37 + 0.32
= 0.69
= 0.7
(rounded up to the next 0.1 ns)

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CMOS Channeled Gate Arrays

Delay Estimation Principles

The propagation delay for N3B, found by following the same procedure, is:

too C

~dn + KCLdn (NF/o + CL)
1.70 + 0.04 (3 + 3.0)
1.70 + 0.04 (6.0)
1.70 + 0.24
1.94
2.0
(rounded up to the next 0.1 ns)

too

too
too

too
too C

The propagation delay for V2B, found by following the same procedure, is:
toup
0.25
0.25
0.25
0.41
0.5

+ KCLup (NF/o + CL)
+ 0.08 (1 +1.0)
+ 0.08 (2.0)
+ 0.16
(rounded up to the next 0.1 ns)

Therefore, the delay for a rising pulse through the sample circuit shown in Figure 5-2 is:

fpc!
fpc!
fpc!

too A+fupB+fcJn C+fup D
0.6 + 0.7 + 2.0 + 0.5
3.8 ns

5.7 Delay Calculations when Loads Exceed CDR

Fujitsu CMOS unit cells are capable of driving loads beyond their published Output Drive Factor (CDR)' It
must be emphasized, however, that the delays that result from this practice are considerably increased.
Unit cells may be loaded beyond their CORS provided that the increased delay is acceptable.
Anticipation of the effects of loading beyond the published CDR requires recalculation of delay. Different
delay equations must be used depending on the technology being used and the amount that the loading
exceeds CDR.
The different delay equations listed below for Fujitsu's channeled gate array technologies must be used
depending on the degree that the loading exceeds CDR.
When C is CDR or less:

fpc! = ~ + (KCL x C) where C = NF/o + CL
When C is between CDR and 2CDR:
fpc! = ~ + (KcL2 x CDR2) + KCL (CDR-CDR2) + 1.5 KcL(C- CDR)
When C is between 2CDR and 3CDR:
fpc! = ~ + (KcL2 x CoR2) + KcL (CDR - CDR2) + (1.5 KCL x CDR) + 3KcdC - 2CDR)
When C is greater than 3CoR: FORBIDDEN

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Oelay Estimation Principles

CMOS Channeled Gate Arrays

In these equations:
KcL2 is an initial delay time per load unit defined for cells that have been assigned a COR2 value.
COR2 is an initial output driving factor defined for certain cells. COR2 =
in the specification for the cell in the unit cell library.

awhen the value is not defined

Some additional calculations are required to estimate the delay of a downward transitioning signal through
certain cells for which the parameter COR2 has been assigned. For these cells, when C is equal to or less
than COR2, the following formula is used:

fpd

=

to + (KcL2 x C)

When C is between COR2 and COR, the following formula is used:
~d =

NOTE:

to + (KcL2 x COR2) + (KCL x (C-COR2))

Clock networks are never loaded beyond COR because clock timing is critical to the proper
functioning of the gate array. (See Section 5.9)

5.8 Delay Calculations and the Operating Environment
The operating environment of the array can cause variations from the calculated typical delay figures.
Influencing factors include ambient temperature, applied voltage, and variations in the manufacturing
processes. Figure 5-3 shows how supply voltage and temperature affect the performance of a sample
array. It is necessary, therefore, to simulate worst-case conditions during test. Revised estimates of delay
under these harsher circumstances may be arrived at by multiplying the typical delay figures by delay
multipliers. The actual multipliers used depend on the device technology and/or the device type.
Propagation Delay vs.
Ambient Temperature
(normalized)

Propagation Delay vs. Voo
(normalized)

1.4
1.3
1.2

1.4

f'.

1.1
tpd
(ns)

1.3

........

1.0
0.9

.......

I""-- ....

tpd
(ns)

............

.......

1.0

0.7
0.6
5.5

6

./'"

0.8

0.6
5

~

0.9

0.7

4.5

~

1.1

"'-

0.8

4

~

1.2

o

25

75

100

Voo(V)

Figure 5-3. Factors Influencing Delay

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Delay Estimation Principles

CMOS Channeled Gate Atrays

5.8.1 Minimum/Maximum Pre-Layout Delay Multipliers
The minimum delay multiplier and the maximum delay multiplier for Fujitsu's channeled CMOS
technologies given in Table 5-3 below incorporate process, power supply, and temperature variation.
Table 5-3. Pre-Layout Delay Multipliers
Technology

Minimum Delay Multiplier
(O·C, 2.5 V)

Maximum Delay Multiplier
(70·C, 4.75 V)

UHB Technology

0.35

1.65

0010 Technology

0.35

1.65

These delay multipliers are applied in one of two different ways, depending upon whether they are to be
used for the optional delay test calculations or for the other tests performed by Fujitsu using the
information in the Fujitsu Test Description Language (FTDL) file, such as DC test, function test, or high
impedance test.
5.8.2 Delay Calculations for Delay Test (AC Test)
The minimax delays for the delay test are determined by taking the sum of the typical delays and
multiplying it by the appropriate minimum or maximum delay factor. The maximum delay figure must be
rounded up to the next highest 0.1 ns, while the minimum delay figure must be rounded down to the next
lowest 0.1 ns. The result of the sample equation used in section 5.6 to show delay calculation is repeated
here and also shown in its modified form. The delay factors used are those for UHB technology.
Typical delay:
~d

=0.6 + 0.7 + 2.0 + 0.5 =3.B ns

Maximum delay (rounded upto 0.1 ns):
~

= (0.6 + 0.7 + 2.0 + 0.5) x 1.65 = 6.27 = 6.3 ns

Minimum delay (rounded down to 0.1 ns):
~d

= (0.6 + 0.7 + 2.0 + 0.5) x 0.35 = 1.33 = 1.3 ns

5.8.3 Delay Calculations for DC Test, Function Test, and High Impedance Test
The minimum and maximum delays for these tests are determined by multiplying the typical delays for
each cell individually by the delay factors. The resulting figures for both maximum and minimum delays
are rounded up to the next 0.1 ns for each cell. The final figures for each unit cell of the path are totaled.
The delay calculation used earlier is repeated here and is also shown calculated for the DC, function and
high impedance tests. The delay factors used are those for UHB technology.
Typical delay (rounded up to 0.1 ns):
~

= 0.6 + 0.7+ 2.0 + 0.5 = 3.B ns

Maximum delay (delay for each gate rounded up to the next 0.1 ns):
tpd =

(0.6 x 1.65) + (0.7 x 1.65) + (2.0 x 1.65) + (0.5 x 1.65)

= 0.99 + 1.155 + 3.3 + 0.825
= 1.0 + 1.2 + 3.3 + 0.9
= 6.4 ns

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CMOS Channeled Gate Arrays

Delay Estimarion Principles

Minimum delay (delay for each gate rounded up to the next 0.1 ns):
~=

=

(0.6 x 0.35) + (0.7 x 0.35) + (2.0 x 0.35) + (0.5 x 0.35)
0.21 + 0.245 + 0.7 + 0.175

= 0.3 + 0.3 + 0.7 + 0.2
= 1.5 ns

Minimum/maximum delays are also calculated this way for minimum clock pulse width, minimum data
set-up time, minimum data hold time, preset timing, and clear timing. The values of the maximum and
minimum delay multipliers shown above apply to pre-layout calculations only; different factors, specific to
each technology, are used for post-layout analysis.
5.9 Clock Loading
It is acceptable, though not a recommended design practice, to load the output of a unit cell that does not
carry a clock signal beyond its Output Drive Factor (CDR). To ensure maximum clock accuracy, however,
unit cells that output clock signals must never be loaded beyond CDR. These different loading limitations
for clock and non-clock unit cells can lead to "race conditions," in which the clock signal arrives at a
flip-flop before the data signal set-up time has elapsed. It is therefore most important, when loading a unit
cell beyond CDR, to modify the fundamental delay equation using the extra delay factors explained in
Section 5.7.

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CMOS Channeled Gate Anays

CMOS Channeled Gate Arrays

Quality and Reliability

Chapter 6 - Quality and Reliability
Contents of This Chapter

6.1
6.2
6.3
6.4
6.5
6.6

Introduction
Engineering Testing
In-process Inspection and Quality Control
Reliability Theory
Reliability Testing
Test Methods and Criteria

6.1 Introduction
Fujitsu's integrated circuits work. The reason they work is Fujitsu's single-minded approach to built-in
quality and reliability, and its dedication to providing components and systems that meet exacting
requirements allowing no room for failure.
Fujitsu's philosophy is to build quality and reliability into every step of the manufacturing process. Each
design and process is scrutinized by individuals and teams of professionals dedicated to perfection.
The quest for perfection does not end when the product leaves the Fujitsu factory. It extends to the
customer's factory as well, where integrated circuits are subsystems of the customer's final product.
Fujitsu emphasizes meticulous interaction between the individuals who deSign, manufacture, evaluate,
sell, and use its products.
Quality control for all Fujitsu products is an integrated process that crosses all lines of the manufacturing
cycle. The quality control process begins with inspection of all incoming raw materials and ends with
shipping and reliability tests following final test of the finished product. Prior to warehousing, Fujitsu
products have been subjected to the scrutiny of man, machine, and technology, and are ready to serve
the customer in the designated application.

1-103

..

CMOS Channeled Gate Arrays

Quality and Reliability

Process
Inspection of Incoming Material
Check Items
Wafer Processing
Inspection of Wafers,
Masks, Packages, Piece
Diffusion/Ion Implantation
Parts, Chemicals, Etc
Wafer Surface Inspection and
Photoetching
Sample Tests of Thickness,
Surface Resistance, Diffusion
Depth, Electrical Parameters, and Doping
Wafer Surface and Pattern Inspection
Wafer Surface Inspection,
Passivation (Insulating
Layer Formation)
Monitor Test of Film Thickness
Wafer Surface Inspection,
Monitor Test of Film Thickness
Wafer Shipping Inspection
Test of Electrical Characteristics, Stress Test
Dicing (CHIP Separation)
Wafer Surface and Pattern
Sampling Inspection

CHIP Selection
CHIP Shipping Inspection

Bond-Position and Surface Inspection,
Sample Wire Bond Strength Test,
Monitor Test of Sample run for Machine Calibration
Internal Visual Inspection

Internal Sampling Visual Inspection

Figure 6-1. Quality Control Processes at Fujitsu

1-104

PrlrCap Visual
Inspection
Internal Merchant
Inspection

CMOS Channeled Gate Amrys

Quality and Reliability

Sealing or Molding
Aging (After Encapsulation)
Leak Test (Hermetic Package Only)
Fine and Gross Leak Tests
External Sampling Visual Inspection
External Sampling Visual Inspection
External Sampling Visual Inspection

Curing
External Visual Inspection

External Visual Inspection

External Mechanical Inspection

External Sampling Visual Inspection

Shipping Tests

Test of AC/DC Characteristics and Functions
Hermeticity (Fine and Gross Leak Tests). External and Marking Inspection~
Electrical Characteristics Tests. All Sampling Tests

U

Endurance and Environmental Tests
Legend:

o

o

IQI

<>

Reliability Tests

0

Lot Tests/Periodic Tes

Production Process
Test/Inspection
Production Process
and Test/Inspection

ac Gate (Sampling)

Note:
The flow sequence may vary slighHy
with individual product type.

Figure 6-1. Quality Control Processes at Fujitsu (Continued)

1-105

CMOS Channeled Gate Amws

Quality and ReliabiHty

6.2 Engineering Testing
Engineering testing is the heart of reliability and quality control. The reliability engineering department
plans and performs most engineering testing. Whenever a device is developed, it must undergo
engineering approval tests. After the device passes these tests, production engineering approval tests are
performed on a representative sample of the device. All factors that could influence production of the
device are examined. Only if all conditions are favorable and the device passes thorough testing, can the
new device go into production.
Tables 6-1 a through 6-1d show a sampling plan for engineering testing. These tests are in compliance
with MIL-STD-883, Class B. When a change in production (e.g., a material change) is needed,
engineering tests are performed on specific items for the change.
Since the representative samples tested must accurately reflect the reliability of the device, the following
conditions must also be satisfied: the functions performed by the same basic circuit; the same processing
techniques, materials, parts and packages used; and the same processing followed at the same factory.
Table 6-1a. Sampling Plan for Engineering Testing: Endurance Test
T••tltem.

MIL-8TD-883

LTPD*
(%)

Acceptance
number-

l008C
l00S0

7
7

1
1

High-temperature continuous operation 12SoC

10S50

S

2

Low-temperature continuous operation --65°C
High-temperature high-humidity storage

(l05SCorO)

7
7

1
1

As applicable
Plastic package only

(I00SCorO)

7

1

Plastic package only

High-temll9l8ture sloraaG IS00C
High-temperature continuous operation

Note

lSOoC or 12SoC

8S0C,85%RH
High-temperature high-humidity continuous
operation asoc, 85% RH

Lot test percent defects
Number of failures permitted per lot

1-106

)

Quality and Reliability

CMOS Channeled Gats Arrays

Table 6-1b. Sampling Plan for Engineering Testing: Environmental and Mechanical Test
T.atltema

MIL-STD-883

External visual inspection
Physical cimensions
RaciophotoaraDhy
Internal visual insP&ction

2009
2016
2012
2013

Lead integrity:
Tension
Bending slnlss
Lead fatigue

2004 A
B
B

LTPD
(%)

Acceptance
number

15
15
3devicas
15

1
1
0
0

15
15
15

0
0
0

Not.

Same sample

Devices which failed
in electrical
characteristics test
ara acceptable to
this test. Each test
is performed on one
third of the leads of
each sample.
Same sample

Resistance to solderina heat
Temperatura cycling
Thermal shock
Vibration, variable-freQuency
Mechanical shock
Constent acceleration

-

Seal: (Fine and gross leak checks)

1014A
C

Resistance to solvents

2015

40 devices

1

Devices which failed
in electrical
characteristics test
ara acceptable to
this test.

Solderability (260°C)

2003

15

1

Devices which failed
in electrical
characteristics test
ara acceptable to
this test.

Solderability (230°C)

-

15

1

Devices which tailed
in electrical
characteristics test
ara acceptable to
this test.

Internal water-vapor content

1018

3 devices

0

Hermetic package
only

Electrostatic cischarge sensitivity
Prassure-Temperature-Humidity Storage

-

1010C
1011 A
2007 A
2oo2B
20010

3015A

7
7
7

1
1
1

10

1

7
7

1
1

15
15

1
1

Hermetic package
only

Plastic package only

(PTHS) 121°C, 2 atm.

1-107

CMOS Channe/ad Gate Arrays

Quality and ReHability

The following tests are performed only when required or when requested by the customer.
Table 6-1C. Sampling Plan for EngineerIng TestIng:
EnvIronmental and Mechanical Test (OptIonal)
Teatltema

MIL-8T[)'883

I.TPD
(%)

Acceptance
number

Bond strength
Die shear strength

2011 D(orC)
2019

15
3 devices

2 wires
0

Moisture resistance
Salt atmosphere corrosion
Vibration fatiaue
Immersion
SEM inspection of metallization
Particle impact noise detection (PINO) tast

1004
1009 A
2005
10028
2018
20208

15
15
15
15
3 devices
15

0
0
0
0
0
1

Lid torque

2024

Adhesion of lead finish

2025

Note

34 wiresJ4 devices
Hennetic package
only

Hermetic package
only
Frit sealed package
only. aSJll1Qlicable
As~icable

Table 6-1d. Sampling Plan for Engineering TestIng: Continuity Test
Te.tltem
Continuity check

MIL·STO·883

-

LTPD

Acceptance

(%)

number

Note

5

2

Plastic package only

6.3 In-process Inspection and Quality Control
Every department involved in the manufacturing process is responsible for the quality-control inspection in
Its sphere of operation. In-process checks, sampling tests, and other inspections are assigned so that
each department has certain allotted tasks for which It takes full responsibility. This total control system
has rationalized overall operations dramatically.
6.3.1 In-process Checks (Including screening)
In-process checks are performed after each step critical to the next process in wafer processing and
assembly. Defective or substandard products are weeded out at an early stage. Testing falls into the
following three categories:
(a) Probe testing, chip selection, and final testing. These are defined for each process.
(b) Voluntary checks. These include inspection of the wafer surface after window opening (before
the diffusion process) and inspection of the wafer surface after the metallization.
(c) 100 percent screening. This includes the aging and visual inspection performed during
wafer processing and assembly.
6.3.2 In-process Sampling Test
The in-process sampling test is performed as a part of process quality control. The Manufacturing and QC
departments check randomly drawn samples at key points in the manufacturing process to check process
and facility conditions. This helps in maintaining product quality at the customary high level. The following
Items are checked in these sampling inspections or monitoring:
(a) Surface resistance after diffusion, film thickness, evaporated or sputtered electrode thickness,
and device characteristics

1-108

Quality and Reliability

CMOS Channeled Gate Arrays

(b)

Product quality (checked by visual inspection of the chip surface)

(c)

Bonding machine calibration, visual inspection and bond strength after wire bonding, product
appearance, marking permanency

6.3.3 In-process Inspection

ac

The Manufacturing and
departments perform stringent quality checks between major processes to
ensure the highest quality. The following four types of inspections are performed:
(a)

Incoming materials, parts, and chemicals Inspection

(b)

Wafer shipping inspection

(c)

Chip shipping inspection

(d)

Shipping test

6.3.4 Lot Configuration
A "lot" consists of the same devices produced over a stated period, having the same design and using the
same processing techniques, materials, and production line. In addition to the Fujitsu logo, part number,
and other markings, each device is marked with a lot code as shown below.
Lot code
Last two digits of the year

xx xx

--=r "l:.-

Weokcodo

6.4 Reliability Theory
6.4.1 Estimating the Failure Rate
The graph of a component failure distribution is usually a downward-bowed curve, often called the
bathtub curve (Figure 6-2). Life tests show that the instantaneous failure rate decreases with time and
graphs as a straight line on a Weibull probability chart (Figure 6-3). Shape parameter m, which shows the
instantaneous failure rate, is between 0.3 and 0.7. (In an exponential distribution, the instantaneous failure
rate does not change and m = 1. As m becomes smaller than 1, the instantaneous failure rate decreases
with time.)
Instantaneous
failure rate

I.
.1.
I :::::Ia/uro I Random 'a/uro period

.1.I Wear·out

failure period

TIME

Figure 6-2. Distribution of Component Failure

1-109

CMOS Channeled Gate Arrays

Quality and Reliability

Usually, the failure rates during the initial and random failure periods are the most important for
semiconductors. Figure 6-3 shows an example of life test data graphed on a Weibull probability chart.
-n
1.0
2.0

Cumulative
-2.0
-1.0
0.0
failure
rate
99.9
99.0
95.0
90.0
70.0
SO.O
30.0
Sample size: 855
20.0
Test temperature: 1SOoC
15.0 _
Test time: 1000 hrs.
10.0
F(t)
5.0
[%]
3.0
2.0
1.5
1.0

3.0

4.0
2.0

;
1.0
0.0
-0.53
-1.0

=

l

0.5
0.3
0.2
0.15
0.1
0.1

0.2 0.3

0.5 0.7

--

1

l

Inln-11--1'(t)
-2.0
-3.0
m 1
Exponential distribution _

,/ a

.,..,- m=O.53
~

-4.0
-5.0

-6.0
-6.2

2

3

5

7

10

20

30

so

-7.0
70 100

Figure 6-3. Example of Life Test Data on IC

6.4.2 Accelerated Life Test
Modern applications require an extremely low failure rate for semiconductors. To guarantee such strict
quality requirements, Fujitsu uses an accelerated life test. There is no fixed acceleration rate for
semiconductors but, since semiconductor failure is usually caused by physical and chemical changes in
materials, an acceleration rate can be calculated from the Arrhenius equation below for the progress
speed of physical and chemical phenomena (assuming the R is proportional to the degradation speed):
R = A exp(-Ea/kT)
where:
R:
A:
Ea:
k:
T:

Reaction rate
Proportionality constant
Activation energy
Boltzmann constant
Absolute temperature

The proportionality constant A corresponds to the component reliability. The activation energy, Ea,
depends on the component's materials and their combination, but it ranges from 0.3 to 1.35 eV for
semiconductors. This equation does not fit the data perfectly because it assumes that the failure rate is
affected only by temperature when, in fact, there are many contributing factors. However, the equation
does give a good rough fit. Using the equation on data from the accelerated life test, engineers can
estimate and guarantee the field failure rate with reasonable accuracy.
The calculation method for the field failure rate is given below for Fujitsu semiconductor products.
Although this method is not generally accepted yet, it has been found to be useful.
(1)

Calculate the junction temperature (Tj(op)) for actual use from the temperature rise (Tj) and
the ambient temperature (Ta) under an average load (do not use the worst-case 10ad),Tj(op) =
6Tj + Ta.

(2) Calculate the junction temperature (Tjt) for a life test. For a high-temperature storage test, Tjt
equals Ta (the storage temperature). For a continuous operation test, the temperature rise

1-110

Quality and Reliability

CMOS Channeled Gate A"ays

under load plus the ambient temperature (25°C except for high-temperature operation) for an
operating temperature. Tjt = L\Tj + Ta .
(3)

Calculate the acceleration rate (a) from the difference of Tj(op) and T~ using Figure 6-4.
Acceleration
Rate
10.000
8.000
6.000
4.000
2,000

,
'\.

600
400
200

'\ ...

r\.

1,000
800

Ea .. a.SeV

~
~,

1\

Ea_ 0.358V'

100
80
60
40

20

10
8

Ea .. 0.7 eV

~,

~ ~~ \.. '\
~ ~~ ~ ~

"

.'- .'-'"'- ,~
"'-

" ~~

1\'

, ,1\

~, ,~

~,

~

1
250

°

200 175 150 120 100 80
60 50 40 T( C)
Junction tel11>8ralure at testing
,

1.8

2.0

2.2

2.4

,

2.6

I

2.8

,

3.0

3.2

3.4

Slanted tines show junction temperature at operation
Reciprocal of absolute junction t8rJ1)e1'ature llT~ (10 -31<)

Figure 6-4. Acceleration Rate VS. Junction Temperature
(4)

If planning reliability testing or calculating reliability in the field from data obtained in steps (1)
to (3). determine the coefficient yfor the 60% confidence level in Table 6-2 from the number of
defective units allowed or from the total number of failures found in the test.
Reliability = ~ x y x 109 [FIT)
where:
N: Number of samples
T: Total test time (hrs)
n: Number of failed samples in test

1-111

Quality and ReliabHity

CMOS Channeled Gate Arrays

Table 6-2. Determination of Coefficient
No. of failures
0
1
2
3
4
5
6
7
8
9
10

Confidence level
60%
(0.92)
2.02
1.55
1.39
1.31
1.26
1.22
1.20
1.18
1.16
1.15

90%
(2.30)
3.89
2.66
2.23
2.00
1.85
1.76
1.68
1.62
1.58
1.54

The above equation applies only when nlN is equal to or less than 10% for the total test time, T. If nlN
exceeds 10 percent, use the following method of calculation: divide the total test duration time, T, into
subsections, Ati (i = 1,2, ... , m), so that for each Ati the failure rate, (ni+ 1 - ni)/(N - nil (where ni is the
cumulative number of failed samples for Ati), does not exceed 10 percent. Calculate (N - nil Ati for each
time section Ati. Calculate the summation l:(N - nil Ati for all the time sections in T. The summation
I(N - nil Ati must then be substituted for NT in the above equation.
6.4.3 Failure and causes

Circuit format differences, package types, and operating environments can change the mechanisms of IC
failures, so it is difficult to foresee which factor will be the most important in a failure mechanism. Figure
6-5 shows specific electrical failures for ICs, their most common causes, and general corrective actions.
Causes of IC failures are largely the same as for planar transistor failures, but the following problems are
more common or specific to ICs:
(a)

Surface degradation

(b)

Flaws in an evaporated or sputtered metal film

(c)

Contact failures due to an increased number of wire bondings per package

(d)

Package failures due to an increased number of external leads

Table 6-3 lists failures with their most common causes, and Table 6-4 shows the relationship between
operating environments and failure causes. Test items can be listed only if the failure cause can be
pinpointed by the test.

1-112

Quality and Reliability

CMOS Channeled Gate Arrays

.Metal migration

Moisture penetratiqn

Gate~unction

short

Leakage or short between
package leads

Parasitic'transistor

Oxide filin impeife9~Qn

Channeling

Mask misalignmllnt

Figure 6-5. DlgltallC Failures and Corrective Actions

1-113

Quality and Reliability

CMOS Channeled Gate Arravs

Table 6-3. Process Defects Analysis
Defect
Area

Defect mechanism

Frequency

Sourcs

Design
Junction
(Internal)

Junction failure due to current crowding

High

Metal migration

Low

Junction
(Surface)

Oxide film imperfection (Pinhole, crack, void, etc.)

Interconnection

Impurity contamination

Wire

Others

Mask misalignment

Medium

Incomplete metallization

Medium

Improper metallization

Medium

•

Manuf.
Tech.

Operator
Skill

Medium

Aluminum migration

Medium·

Bonding peel

High

Purple plague

Medium

Wire over-stress

High

Particlelwire short

Low

•

•

•

•

•

•

•

•
•
•
•
•
•

•
•
•

•

Medium

Die bond failure

Low

lead breakage

Medium

Package corrosion

Medium

Chip crack

Medium
Low

User
Application

•
•
•
•
•

High

Aluminum corrosion

Seal contamination

1-114

High
Medium

leakage
Package

Medium

Metal peeling

Metal over-stress

•
•

Factory
Process
Control

•
•

•

•

•
•
•
•
•

•
•
•
•
•
•
•
•

•

•
•
•
•

•

QuaRt and ReHabHiry

CMOS Channeled Gate Arrays

Table 6-4. Relationship between Failure causes and Analytical Test Methods
Test
T....,.,·

Failure Cause

SoIdor·

ability

(2003.2)

ature
Cydirv
(1010.2)

Bond integrity
(Chip or wire)

•
•

Cracked chip

.-

Thermal
(1011.2)

•

Ilaro-

Conllant

Acceleration shock

(2001.2)

•

•

•

Wire or chip
breakage
Glass crack
Lead fatigue
contamination of
junction (Surface)

•

•

(20(2.2)

•

VlJratlon.
varlablo

Inoquancy
(2007.1)

_ric
preoaore

Load

fatigue

(2004.2)

reduoad
(1001)

Sal
Moiltura
...is.....

atmooph...

(100402)

(1008.2)

VIbration
l8Iiguo
(2005.1)

Vbration
noi..

(2008.1)

•

•

•

•

•

•

•

•

•
•

•

•

•

•

•

Internal
structural defect
Contamination-l
contact-induced
short

Mechanlca

•

•

•
•

•

•
•

Thermal fatigue
Seal integrity

•

•

•

•
•
•

Seal contamination
Leakage

•

•

Package/material
integrity

•

·

•

•

•

•
•

•

•

•

•

•

•

6.5 Reliability Testing

Reliability testing includes three types of tests-lot tests, periodic tests, and "occasional" tests. This
section explains the details of each test in turn.
6.5.1 Lot Tests

There are two types of lot tests, Group A and Group B. Group A and Group B tests are performed on
items that are tested regularly, usually every week. Table 6-5 lists the specific lot tests.
Details of individual tests vary with the product under test, but all samples are selected at random from
every weekly lot Tests are not performed in any particular order unless specified, but are performed for
each device type.
Note that the high-temperature storage and continuous-operation tests for Group B usually take 500
hours, although they may take only 168 hours in special cases. Good samples are returned to their lots
after non-destructive testing. No-good samples and samples that have undergone destructive testing are
destroyed.
6.5.2 Periodic Tests

Particulars of the periodic tests are also listed in Table 6-5. There are two types of periodic tests: Group C
tests and Group D tests. Group C tests are performed on items that are tested regularly, usually every 13
weeks. Group D tests include special reliability tests and very long life tests. The Group D tests are
usually done once every 26 weeks.

1-115

CMOS Channeled Gate Arrays

Quality and Reliability

Details of individual tests vary with the product under test, but all samples are selected at random. Tests
are not performed in any particular order unless specified, but are performed for each device type. Note
that the high-temperature storage and continuous-operation tests for Group C take 1000 hours and those
for Group D take 3000 hours.
Table 6-5. Sampling Plan for Reliability Testing
Group Subgroup

A

Al
A2
A3
A4

Bl
B2

Device classification
Test Items
External visual inspection
Function test
Electrical
Static characteristics
Characteristics
DynamiclSwitching
characteristics

Phvsical dimensions
Resistance to solvant
+temp-cycling
Environmental
tests
Thermal shock test

B

B6
B7

C3
01
0

Ac=O
Sample
size
6
9

18

9

9

18

9

1

9

1

Solderability (230°C, 5s)'

9

1

3

1

Solderability (260°C, 5s)'

9

1

3

1

Lead integrity'

9

1

3

1

Pressure-temperature-humidity
storage2

9

13

3

13

9

17

3

17

Mechanical
environmental test

Pressure-temperature-humidity
bias2
High-temperature storage

Endurance
test

14

I'

7

I'

Continuous operation
High-humidity storage
Bd'c 85%RH2
High-temperature
storage

24

I'

11

1-

24

I-

11

I-

14

15

7

15

Continuous operation
High-humidity storage
8!f'C 85%RH2
High-temperature
storage6

24

15

11

15

24

15

11

15

14

-

7

-

11

-

11

-

02

Continuous operation
24
High-humidity storage
03
24
Bd'c 85% RH2.6
Test cycle: Group A and B for every weekly-lot, Group C every 13 weeks, Group 0 every 26 weeks

-

Notes
IElectrical reject devices can be used in this test.
2'fhese tests are performed on resin-sealed devices.
3This test takes 96 hours.
4These tests normally take 500 hours. But if no defects are found in the first 168 hours, the Jot can be passed
and the test may be terminated.
5These tests take 1000 hours.
~ese tests take 3000 hours.
7This test takes 48 hours.
8These tests take 100 cycles.

1-116

Acceptance
number
1

18

Cl
C2

5%

Acceptance
number
1
18

B8
69

C

LTPO
Ssmple
size
9
9

B3

94-1
94-11
B5

Device group 2
I
SsmDlIna plan
100% test of sampled devices (All sariioled deviceS)
A" - 0
LTPD 5%
Ac-O
LTPO 5%
Device group 1

Quality and Reliability

CMOS Channeled Gate Arrays

6.5.3 Occasional Tests
Occasional tests are performed on products whenever necessary. The tests are similar to periodic tests,
but their details are specified by the QC/Reliability Engineering Division according to the purpose of the
test.
6.6 Test Methods and Criteria
The reliability of Fujitsu ICs is assured by severe environmental and endurance testing. Test methods are
usually based on Japan Industrial Standards (JIS), the standards of the Electronic Industrial Association
of Japan (EIAJ), and MIL standards.
Reliability tests are performed for two reasons. Firstly, they check or guarantee the reliability of a type or a
lot according to specified standards. Secondly, they are used to determine the failure rate or mode. The
most appropriate test method is chosen for each test, and test results are processed in the most suitable
manner. Fujitsu usually performs the tests listed in Tables 6-6, 6-7, and 6-8.
Table 6-6. Example of Reliability Testing
Teslilems

Condition

MIL-STD-4I83

-

Resistance to soldering heat

260°C, lOs

Temperature cycling

1010C

-65°C (lO min.) to 1500 C{lO min,), 100 C¥cles

Thermal shock
Vibration, variable-frequency
Mechanical shock
Constant acceleration
Fine leak'

1011 A
2007 A
2002 B
2001 E
1014A,

OOC (5 min.) to 100°C (5 min.), 100 cycles
20 to 2,OOOHz, 20G
1,SOOG, 0.5ms
lO,OOOG, 1 min. y, only
Using compressed helium 99.5 psig. 4 hrs.

Gross leak'

1014C

Using fluorocarbon 75 psig. 1 hr.• 125°C

-

Solderability

230°C.5s

2003
Lead fatigue

260°C.5s

2004 B2
-

PTHSIPTHB'
High-temperature storage

121°C. 2 atm

1008C

Continuous operation

1005 A to D

-

High-humidity storage'

0.25kgf. 90°. twice
150°C. 1.000 hrs.
125°C. 1.000 hrs.
85°C.85%RH. 1.000 hrs.

Notes: 1 Applies to hermetic packages.
2 Applies to plastic packages.

Table 6-7.
Circuit classlflcetlon
Gates
Flip-flops
Shift registers
Memories
Random-logic devices
Analog devices

Characteristics
DC
AC
DC
AC
DC
AC
DC
AC
DC
AC
DC
AC

Example of Electrical Testing
Bipolar
VOH, VOL. IIH. ilL. Icc (lEE)
Function
VOH• VOL. IIH. IlL. IOH' Icc (lEE)
Function
VOH. VOL. IIH. ilL. IOH. Icc (lEE)
Function
VOH, VOL. IIH. IlL. ICC (lEE)
Function
VOH• VOL. IIH, IlL. Icc (lEE)
Function
Via. 110, II. VOM. VOH.VOL•
Av. Koo. No

MOS
VoH, VoL. IIH. IlL. 100 (Isub)
Function
VOH• VOL. IIH. IlL. 100 (I. ub)
Function
VoH• VOL. IIH. IlL. 100 (I,ub)
Function
VoH• VOL. IIH, ilL. (IOH).(IOL)
100 (Isub) Function
VOH, VOL. IIH, IlL, (IOH),(IOL)
100 (I,ub) Function

-

1-117

CMOS Channeled Gate Anays

Table W. Example of Electrical Criteria
Paramater

VOH
VOl.

Umlt value (In mutdplee of the abaolute value)
Lo_r
Upper

Ux 1.1

-

IH

U x2
(No leak: U x
1.1)

IL

Ux2
(leak: U x2

-

IoH
1cc(1u)

Ux2

(Leak: U x2

-

Icc (/sus)

"U. and "L. stand for IIIe upper and /ower Nmhs

1-118

lxO.9

CMOS Channeled Gate Arrays

Application Note

Chapter 7 - Application Notes
Contents of This Chapter
Developing Test Patterns That Work with the Physical Tester
Selecting the Best Package for Your ASIC Design

1-119

APplication Note

1-120

CMOS Channeled Gate Arrays

00

March 1990
Edition 1.1

APPLICATION NOTE

lA'

FUJITSU

CAA·oS····ASI·C·······

....

Developing Test Patterns
That Work with the Physical Tester
by J. Scott Runner

..

Fujitsu Microelectronics, Inc.
Copyright© 1990 by Fujitsu Microelectronics, Inc.
Introduction
This application note briefly describes the process of developing test patterns for the simulation and test of
Fujitsu CMOS ASIC designs. This information supplements testing information found in the Design Manual for
the appropriate Fujitsu CMOS ASIC technology.

Tests to be Created
Fujitsu supports the following five types of test
a.

DC test

b. Dynamic function test
c.

High impedance test (Z-function test)

d. Delay test (AC test)
e.

Scan test (optional for certain Fujitsu technologies)

The DC test measures DC characteristics such as IDOS, YOH, ILl, and ILZ, while the function test screens for
manufacturing faults (metal and transistor faults, principally). The Z-function test augments the DC test and is
required for circuits in which one or more enable signals from a 3-state buffer can be generated by logic deeper than
one gate of complexity within the ASIC device. The delay test may be used to verify critical timing paths that are
necessary for proper system operation.
Scan test methods are used to simplify the [process of testing for manufacturing defects traditionally uncovered by
the function test. Automatic test generation is supported in conjunction with scan testing in the UHB/CGlO and
AU/CG21 technolOgies as an option.

1-121

CMOS Channeled Gate AlT8ys

Application Notes

Overview of Test Vector Creation
For each set of test patterns defined as a test block, the customer must specify input states and output
states (in either vector or wave format), and the timing of inputs and outputs (with bidirectionals being
considered both an input and an output). Many designers rely on one of the Fujitsu-supported CAE workstations when generating test vectors, easing the burden of test pattern development. In these cases, the
customer creates input stimuli for the workstation simulator, which then generates a print-on-change file
containing the resulting output response and the associated input stimulus previously defined by the designer. The print-on-change file is converted by Fujitsu's workstation software into FTDL (Fujitsu Test Description Language), which is the accepted test pattern description format regardless of the method by
which patterns are created.
Developing the Tester Timing Information
Whether or not the patterns are generated on the CAE workstation, it is necessary for the customer to generate in the FTDL file a Common Block file, containing administrative information and the test type, and a
Test Block file, containing the timing information for all chip inputs and outputs by group (discussed further in the Design Manual). The definition of this overall timing is critical to the success of the test program itself. For example, input timing defines when input signals will transition, while output timing defines when outputs will be compared with their expected values or measured at a transition point.
The designer is responsible for specifying the following timing parameters for the Test Block, depending on the specific type of test:
a.

Test cycle

b.

Grouping of inputs and, if necessary, outputs and bidirectionals

c.

Delay-to-transition (DT) time for each input group of non-return to zero (NRZ) signals

d.

Propagation time (tp) and pulsewidth (Wp) times for the positive-going pulse (PP) and negative-going pulse (NP) for each input group of return to zero (RTZ) signals

e."

Delay-to-strobe time (STB) point for each output group

f."

DT and STB times for bidirectionals

g..... T time in the SPAlli statement for AC tests
"Specified in DC, function, and Z-function tests
....Applicable only to AC tests.
This timing is established for the entire test block and is invariant until another test block is invoked.
Therefore, test pattern timing is periodic, that is, a group of inputs may only transition at the time specified in the Test Block, which is relative to the beginning of the test cycle. This delay to transition time for
inputs is programmed for each input group with the t" parameter in the FTDL INTIM or BUSTIM statement.
Similarly, common output groups are strobed, or sampled, periodically at a time determined by the test
cycle and the delay-to-strobe time specified in the OUTTIM or BUSTIM statement, or the Tp parameter in
the FTDL SPAlli statement in the case of an AC test.

Determining Input and Output Timing Parameters
During the function test, outputs should stabilize before being strobed. Therefore, the minimum permissible test cycle programmed by the TIMING statement in the Test Block should be set with consideration of
the maximum propagation delay from any input to any output, and the respective DT and STB times for
those groups should be set far enough apart in time to assure that the outputs are stable under maximum

1-122

Application Notes

CMOS Chaflflflltld Gate AlTBys

conditions. Similarly, if the output is strobed before the transition, it must be stable under minimum delay
conditions.
Test patterns are required to be invariant over minimum and maximum delay conditions. This is verified
in simulation by scaling the typical delays by multipliers representing process, temperature, and power
supply variations. Similarly, the strobed or expected output states must be identical under typical, maximum, and minimum conditions. If a propagation delay from input to output is greater than the test cycle
defined, output states may not fulfill this requirement (see Figure 1). Furthermore, designers should be
careful that glitches or short pulses do not occur anywhere within this minimum/maximum window (see
Figure 2).
FAILED
/'

IN 1
OUT 1 (MIN)

•

OUT 1 (TYP)
OUT 1 (MAX)
STROBE
STROBE VALUE

·
···
·.
[[]:· ·
[[]: ·
•
I : ••
·.
••·• .
·· ··•

•• •
• ••
/IIl~ .
•

•

Test Cycle
TooShortG)

FAILED

./

LUCKY

[I]

OJ

OJ
(]J

OJ
OJ

I

.I

!

Successful Test Cycle Length

<2>

X a State When Strobed; X - 0 or 1 as indicated.
The minImax variation results in inconsistent values being strobed if the test C)'cle is too short (1) or the strobe is
poorly located. Successful test programs therefore require the determination of a reasonable test cycle length. (2)

Figure 1. Determining a Successful Test Cycle Length
MIN
CASE

OUT 1
STROBE
STROBE VAL

I

I

lID

IW11

TYP
CASE
OUT 1
STROBE
STROBE VAL

I

J

lID

I@]

MAX
CAS~

OUT 1
TROBE
STROBE VAL

·••

I

lID
Dangerous Cycle Length

I

I@]

Preferred Strobe Range
Preferred Cycle Length

X - State when Strobed - X - 0 or 1 as indicated.
I!J
The output contains a pulse that goes undeteCted at minimum, typical or maximum simulations. However, since
any pulse or gl~ch appearl~ over the range of minimum to maximum may be strobed by the tester, or appear in
the end system, all pulses 0 this kind must be considered when placing the strobe and determining cycle length.

Figure 2. Determining Preferred Cycle Length

1-123

AppI~tion

CMOS Channeled Gate Arrays

Notes

Generating Functional Input Stimulus Given Test Pattern Timing
One issue that must be considered when determining test pattern timing is the relationship between input
signals, such as clockldata pairs, which must satisfy set-up and hold times. Other considerations guiding
the timing definition are dependent on the particular circuit being tested, and on restrictions imposed by
the tester. These restrictions are published in the Summary of Test Data Restriction section of Fujitsu's Design Manuals.
Tester Skew and Its Compensation of Test Timing
The designer must pay particular attention to the issue of tester skew when determining input and output
timing for Test Blocks; otherwise, the timing will not correctly represent the behavior of the device under
test. Tester skew, specified for each technology in the Summary of Test Data Restrictions, is a result of the
variation in the time at which a given signal generator triggers a transition or a comparator measures an
output state. Several timings are affected by this skew.
Input-to-Input Skew
For the purpose of estimating the skew between two signal generators, (one driving data and the other
driving its clock, for example), the driver skew, linearity of clocks, clock-to-clock skew, and jitter are collectively called driver accuracy, denoted tnSKEW.
In the case of datalclock pairs, the clocked data may fail either a set-up or hold time, depending on the
direction of the skew. Therefore, when determining DT and t" for datal clock pairs, the designer should
adjust times to satisfy the following relationships (see Figure 3):
Set-up Time Criteria for Testing: (t,,(CLOCK) - DT(DATA» >= ts(MIN) + 2
Hold Time Criteria for Testing: (DT(DATA) - t,,(CLOCK» >= fH(MIN) + 2

* toSKEW
* tDSKEW

Where ts(MIN) and fH(MIN) are the worst case set-up and hold times, respectively, sensitized from the
internal circuit to the inputs, toSKEW is not directly specified in the Summary of Test Data Restriction;
however, TACC, the overall system timing accuracy, is specified and can be substituted for tDSKEW.
Expected

Actual

'..:
D

Q

;,I
TLO

DATA

.. ,'

DT

,
,

tOSKEW

D

CK

Actual

'lIoI,

:~xpected',

,

W~

Ip

ClK

ClK

',..
CK

TLCK

,
,
,
, ;.....ts

.'

--.

Figure 3. Input-to-Input Skew
Input-to-Output Skew
In addition to the skew incurred by the signal driver, skew is also introduced by the output comparator of
the tester. This skew is dependent on the linearity of the strobe, pin-to-pin skew, skew between dual com-

1-124

Application Notes

CMOS Channeled Gate Arrays

Input-to-Output Skew

In addition to the skew incurred by the signal driver, skew is also introduced by the output comparator of
the tester. This skew is dependent on the linearity of the strobe, pin-to-pin skew, skew between dual comparators, and the driver-to-comparator timing error. All factors are considered in the overall system timing accuracy, tACC, which in tum affects output timing as shown in Figure 4.
Ipo (MIN) or tpo (MAX)

-13>----11

IN

IN

•

LOGIC

I-----ib>----...

OUT

DT (Expected) .

Actual Output
Possible
tOSKEW

OUT

__:_ .. '

Actual Strobe
Possible

,--

Expected Strobe

STB
IACC = IOSKEW

+

tCSKEW

Driver Plus Com aralor Skew

Figure 4. Input-to-Output Skew
Skew Effect on Input/Output Pairs - Minimum Delay Case
The 5TB (or T parameter in the SPATH statement) should expect an output transition at a time relative to

the stimulated input transition dictated by
(5TB - OT) >=tpD(MIN) - tACC

where 5TB is the strobe point of the output under consideration, OT is the OT time of the stimulating input of interest, and tpD(MIN) is the minimum propagation delay from this input to the strobed (or measured) output. In the case of the AC test, the quantity (5TB - on should be replaced by the minimum T
parameter in the SPATH statement. Note that if the path delay spans a test cycle boundary, 5TB should be
set to 5TB plus the test cycle period.
Skew Effect on Input/Output Pairs - Maximum Delay Case

The complementary case occurs for maximum delay measurements, as described by
(5TB - OT) <= tpd(MAX) + tACC

Note that these guidelines regarding the specification of test data timing as affected by tester skew apply
to DC and Z-function tests as well. In these cases, the same rules apply as for the function test.
Again, for the specific values of tAcC, and toSKEW, please refer to the Summary of Test Data Restrictions in
the Fujitsu Design Manual for the appropriate technology. A designer interested in a methodical approach
to the generation and verification of a good set of test vectors must consider the tester hardware on which
it is running. Fujitsu has simplified designer responsibility by providing this information as part of the
Test Block Information.
However, a lack of implementation and careful analysis of the timing characteristics of the circuit may result in a poor or unfeasible test, resulting in schedule delays or reduced device yield. Therefore, plan a test
approach early, design for testability, and consider the effect and operation of the physical tester.

1-125

CMOS Channeled Gate AlT!IJ(s

1-126

cO

March 1990
Edition 1.1

APPLICATION NOTE

FUJITSU
I

Selecting the Best Package
for Your ASIC Design
by J. Scott Runner

Fujitsu Microelectronics, Inc.
Copyright© 1990 by Fujitsu Microelectronics, Inc.
1.0 Introduction
The widely varying degrees of complexity (gate count) of Fujitsu's CMOS and BiCMOS devices and the flexibility of
their I/O configurations combine to produce devices that take advantage of the broad selection of packages available
from Fujitsu. However, the requirements for package selection go far beyond pin count as the sole determinant of the
best package. Selection issues include surface mount versus through-hole, plastic versus ceramic, and exotic versus
conventional packaging. In fact, Fujitsu offers over 100 packages and 1000 package-die combinations from which to
choose. Compounding the selection problem is the effect of increasingly faster outputs coupled with higher drive and
wider bus structure, resulting in greater numbers of simultaneously switching outputs (and thereby greater amounts of
noise).
The result is that designers are finding ASIC packaging implementation to be an increasingly complex task. This
application note provides information about ASIC packaging that is meant to simplify the designer's task. It provides
designers with a review of the various Fujitsu packages and their electrical, thermal, and mechanical characteristics, as
well as some problem-solving strategies for their use. Sections 2.0 and 3.0 address system requirements and package
availability; Sections 4.0 and 5.0 discuss noise and thermal issues.

1-127

..

CMOS Channeled Gate Anays

Application Notes

2.0 How System Requirements Affect Package Choice
Section 2.0 presents considerations involved in the selection of packages from a system designer's perspective. Table 1 lists issues a designer must consider when determining the optimal packaging for an
ASIC design.
Table 1. Considerations for Package Selection
Manufacturing and Cost

Speed Requirements

Board Integration

Package and Interconnect Delays

Double-sided Component Mounting

The Effect of Package on Noise

Number of Packages

Thermal Considerations

Package Outline Area
Power Densny Limitations
Produclbility

Quality

Board Layout

Package Quality and Reliability

Package Construction

Number of Devices

Packaging Complexity

Noise

Manufacturing Flow

Thermal Considerations

2.1 Manufacturing and Cost
The manufacturing-related factors discussed below, although not directly related to the design of the device or the number of power and ground pins it requires, are nonetheless important in the choice of an
ASIC package.
2.1.1 Board Area
One of the most important issues is the board area consumed by a circuit. Some of the factors affecting
overall board density are:

Integration (gates per square inch of board)
Double-sided mounting capability (integration)
Number of packages
Package outline area
Additional board space required (for spacing, resistors, capacitors, probe areas, etc.)
Power density area (discussed in Section 5.0)
The critical issue in board area reduction, however, is overall integration. For example, s :trface mount devices (SMDs) can be densely mounted on both sides of the board, making them ideal for systems demanding high package integration. But a large design integrated into a few very large Sea-of-Gates arrays, even
if packaged in large, through-hole packages, may well consume less board space than the same design
using surface mount plastic J-Ieaded chip carriers (PLCCs). The PLCC version would require more space
because the PLCCs, although small in outline, cannot house as large a die and therefore require the design
to be partitioned into a greater number of devices.
Figure 1 illustrates the board area taken up by the outline of each kind of package Fujitsu offers, excluding
any area around the package necessary for spacing, decoupling capacitors, series damping resistors, or
solder pads.

1-128

CMOS Channeled Gate Arrays

Application Notes

100

-----+1 .••...........
~1~00~M~il~P~in~G~ri~d~A~rr~ay~(~P~G~A~)____________~I ............. .
~5~0~M~i~IP~i~n~G~ri~d~A~rr~a~y~(P~G~A~)____________________

__~F~'a=t~P~ac~k~r~yp~e~(~FP~n~__-+1 ............. .
Leadless Chip CarriefJ~(ffPO°Oo'OoOo
'000'000'000
0'000'00 00
0000'000'000
0'00 000000
0000'0000000
0 000'00000
'000000 '000
0'00 '00000
'000'000'000
0'00 '00 00
'000'00 '000
0'000'00000
'000'000'000
00'000'00000
00000000'000
0'000000000
0000'000'000
0'000'00000
000
'00000
00'000'00000000000000000000000000000000000000000000000°00°00'000

ogg'OOo'OOoOoOo'OOo§qo~~~~OoOo~~O~OoOoOo"_

i

Oo'OOo'OOo'OOo'OOo'ltOo?Oo'OtlfOotlfOo'O

Z

'

,'-, ,......,

,-',

T~·10C

,

~,

0.050
0.070
0.100 0.100
As with all Fujitsu PGAs, corner pins have seating
rings

Figure 6. 321-Pin Ceramic Pin Grid Array

1-136

9'fl'JQ,OO? -

Application Notes

CMOS Channeled Gate Arrays

Figure 7 illustrates the footprint of the staggered PGA and the method for routing traces through the
leads. Note that the routing is oblique, with the traces offset 45 degrees compared to traditional routing.
At this angle, the lead spacing is 71 mils, providing the trace density available with standard through-hole
devices, while reducing the package outline by approximately 40 percent.
Two 32-bit buses routed through the PGA orthogonally
on two layers permits high interconnect density
Traces routed at
45°. Pass-through
clearance between
pins is 0.070'

...
..•...••...••...••..•.•..
····........
·····..........
··•·•..•.•..•.•

..

•

••
• •
•

•

0

•

0

•

•

•

•

0

•

•• • • • ••• 0 •• 0 •••• • • • ••• 0

•• • • • • • • • • • • • • • • • • • 0 • • •
•

•

•

•

•

•

•

•

•

•

•

•

0

;'!';;""i'!!flf!t~=f='"

Traces routed at
"

90°, pass-through
clearance between

pins is 0.050'

Figure 7_ Staggered Pin Grid Array Routing

The lead configuration of a package affects the pin assignment of the ASIC device. For example, Figure 7
shows a situation in which a 32-bit address bus and a 32-bit data bus are routed through the device, with
one offset 90 degrees from the other. If you assign consecutive bit significance to the bus, you will notice
that the resulting pinout is quite different from an equivalent circuit packaged in a traditional orthogonal
PGA. High drive buses can still be distributed around the ground pins, but the associated pads are not
concentrated in one specific area of the die, reducing the concentration of SSOs, thereby reducing signal
noise.
3.2 Surface Mount Devices (SMDs)
The demands of military applications, space-constrained systems, and boards containing large numbers of
memory devices were initially responsible for the development of surface mount technology (SMT). However, the accelerated push for physically reduced systems, the appearance of higher pin count ASICs, and
the cost of pin grid arrays have encouraged many more designers to consider surface mount options. Easing the strain of the migration to SMT is the broader availability of pick and place, vapor phase soldering,
and other necessary SMT equipment, as well as the availability of SMDs for an increasing percentage of
devices on the boards. SMT for VLSI is gaining momentum due to the smaller board area consumption,
smaller profile, and proven reliability.
3.2.1 Flatpacks
Plastic fiatpacks have been popular for years with manufacturers of peripherals in which the board area is
constrained and height is restricted. And recently, the low cost of flatpacks (in plastic) has made them an
attractive alternate to PGAs and even to DIPs in cases of higher pin count. As the following figures show,

1-137

CMOS Channeled Gate Arrays

Application Notes

flatpacks come in several lead type and location configurations. Figure Sa illustrates a small outline integrated circuit (SOlC), with gullwing leads on two sides, Figure 8b illustrates a quad flatpack (QFPT) with
gullwing leads on four sides. Flatpacks with axial leads require special assembly, and are generally used
only for ECL circuits in which leads may have to be trimmed and formed to tune impedance.

Sb. Quad Flatpack

Sa. Small Outline IC

Sc. Ceramic Leadless Chip Carrier

Figure 8. Flatpack Configurations
Because flatpacks feature pin pitches (pin spacing from center to center) down to 10 mils, they can support
high pin counts within a small board area. However, the narrow pin spacing means that accuracy in device placement, pad size and placement, and solder paste application tolerance are all more critical. PC
board designers also need to determine whether the true package dimensions are in metric or English dimensions, and, when converting between the systems of measure, ensure that enough precision is maintained so that pins on the end of large packages won't roll off due to inaccuracies in pad location.
Probing devices with fine pin pitches can be difficult because the pins do not pierce the bottom of the
board, and if probes are attached to the leads, they can easily slip off and short adjacent leads.
3.2.2 Leadless Chip carriers (LCCs)
Ceramic leadless chip carriers (CLCCs), such as the example shown in Figure 8c, have a long history in
surface mount packaging. Ceramic packages perform well in high temperature environments, explaining
their popularity in military applications. The term "chip carrier" comes from the process of mounting the
die directly to a thick-film chip carrier, which also has pads for external connection on the opposite side of
the substrate. This configuration differs from that of the PCA, in which the die is housed in the cavity of
the package, or the flatpack, in which the die is held by the lead frame and molded with the package.
CLCCs are available in pad counts ranging from 28 to 84 and beyond.
Pads, not leads, are located on the bottom of the carrier and are generally spaced at a 40-mil pitch (standard). Solder paste is applied to the pads on the board to which the device will be mounted, usually by
screen printing, and the board is then vapor phase or infrared reflow soldered. Because the pads are 10-

1-138

Application Notes

CMOS Channeled Gate Atrars

cated beneath the package, they are typically very difficult to probe and are subject to manufacturing defects such as solder voiding (gas bubbles in solder formed during reflow).
The most challenging problem inherent to LCC devices relates to TCE mismatch between the chip carrier
and the board to which it is mounted. As the temperature of boards and packages rises, the materials expand at different rates. This difference translates to mechanical shear force at the solder joint. This force
temporarily deforms the leads of PLCCs and flatpacks, but CLCCs have no leads. Consequently, the force
is directed at the solder joint, tending to promote thermal fractures, (shown in Figure 9).
Difference in thermal coefficient of expansion results in shear force applied at the solder joint.

..

Thermal Fracture

TeEpeB. t1T

FIgure 9. Defect caused by Difference In Thennal Coefficient of Expansion

Even though CLCC SMDs cost more than equivalent plastic packages, their resistance to high temperatures, availability in hermetically sealed (moisture resistant) packages, and low profile of the CLCC SMDs
make them very useful for applications in extreme environments. The TCE mismatch problem affecting
LCCs is less severe when they are mounted to ceramic hybrids or PC boards, making their disadvantages
acceptable in many circumstances.
3.2.3 Plastic J·leaded Chip carriers (PLCCs)
If cost and TCE mismatch are a Significant deterrent to the use of LCCs, leaded chip carriers may be more
attractive. Though the chip is still mounted on a carrier (see Figure 10), the electrical connections of PLCCs
are through pins that deform to absorb the TCE-induced thermal stress. Furthermore, while solvents used
in the post-soldering cleaning process may be retained beneath the low profile of the CLCC and flatpack,
the board offset of the PLCC permits it to remain free of these contaminants. In addition, the LCC in a
plastic package costs less than the eqUivalent CLCe.

When more pins are necessary (in the 44-, 68-, 84-pin packages necessary for ASICs), the LCC is called a
PLCe. It is also available in a ceramic body version; both are available in pin counts of 28 to 84 and beyond.

1-139

Application Nolas

CMOS Channeled Gate A"ays

Figure 10. PLCC Package
This package is tenned a small outline Head (SO}) when its bent leads are located on only two sides
(Figure 11). The leads are bent into the fonn of a J in order to pennit it to be placed on top of the solder
pad.

Metallic lead frame

Figure 11. Cross-Section of a Plastic Small-Outline J-Iead Package
On the list of drawbacks of the PLCC is its limited ability to withstand high case temperatures, and its unavailability as a hermetic package. It is nevertheless very well suited for industrial and commercial environments. With a 50-mil pin pitch and only slightly greater height and width, the profile of the PLCC is
nearly equivalent to the corresponding CLCC.
3.2.4 Advances In Surface Mounted Packages
While smaller process geometries themselves have few disadvantages, the associated increase in integration, speed, power, and particularly pin count place heavy burdens on packaging. The greatest challenges
CMOS faces is supporting pin counts in excess of 300 in packages with low lead inductance, capacitance,
and resistance.
To respond to these demands, Fujitsu has developed a clever solution in packaging to obtain the highest
average pin density per board area yet achieved. This is accomplished with surface mount PGAs, which
rely on narrow pin pitch (SO and even 25 mils) in a dense grid of multiple rows of pins. Since through-hole
packages cannot effectively support pin pitches narrower than 70 mils, these PGAs must be surface
mounted, though they still possess pins (see Figure 12).

1-140

CMOS Channeled Gate Arrays

Application Notes

Surface mount PGAs offer the greatest pin density and lowest inductance

.

:::
...

I

•

".:

I

,'''

: ....

..

I

....

... I
......

I
,

I

-

I

"

.,

6·

I

...

I

..

••

••

___olio

......
I

,.e

&.6

Figure 12. Surface Mount PGA

The surface mount technology also permits traces to run beneath the package leads, increasing available
trace density. Figure 13 shows the solder pad design required by these high-pin-density packages.

,

50 MIL

'"

..'

I

I~

A~ernatively.

0.6mm
Diameter

---:- t
t
-

an octagonal
pad geometry
may be employed
-200 - 300 11m

solder paste
- thickness

Figure 13. Solder Pad Design for Surface Mount Pin Grid Arrays

1-141

Application Notes

CMOS Channeled Gate Arrays

Table 5 provides an item-by-item comparison between PGAs, surface mount PGAs, and flatpacks of similar pin counts.
Table 5. Comparison of ernlcal Features

PACKAGE

TYPE

PIN PITCH

OUTliNE (MAX)

PIN DENSITY
(Pins Par Sq Inch)

FPT-160

Surface

25 mil

1.276" x 1.276" (1.63 sq In)

98

PGA-256

Through

100 mil

2" x 2" (4 sq In)

64

PGA-256

Surface

50 mil

1" x 1"(1 sq In)

256

PGA-321

Staggered

71 mil

1.72" x 1.72" (2.96 sq In)

109

PGA-401

Staggered

71 mil

1.922" x 1.922" (3.69 sq In)

109

The numerous electrical and mechanical advantages of surface-mount PGAs would seem to outweigh
their disadvantages. However, the general state of high volume manufacturing has not kept pace with the
rapid advances in semiconductor packaging. This is partly due to the requirement for state-of-the-art
manufacturing equipment, which is quite expensive, and also to the need to maintain board yields with
such complex devices. Therefore, in order to establish these packages as an attractive alternative, Fujitsu
personnel are available to assist customers in the mounting and inspecting of these highly complex packages.
3.3 A Comparison of Through-hole and Surface Mount Devices
SMDs provide improved electrical performance and reduced system size and costs. Furthermore, with
plastic flatpacks of up to 160 pins and beyond available, SMDs show promise in supporting the rapidly
advancing gate size complexities and high pin count of today's ASIC products at a substantially lower
cost than the large ceramic PGAs. However, as the manufacturing complexities that have just been reviewed indicate, surface mounting large ASIC devices may be difficult and risky, and the designer should
be cautious in their use.

If board space constraints are not critical, if the economic impact of scaling down the end system is not
great, if optimal electrical characteristics in packaging are not a critical concern, then through-hole packaging may be the best solution. On the other hand, if speed and integration requirements dictate the use of
very dense gate arrays, PGAs or SMT PGAs provide both through-hole and surface mount alternatives.
3.3.1 Socketing Surface Mount Devices
Some benefits of SMDsare available to manufacturers employing through-hole packages through the use
of sockets for SMDs. Sockets are available for QFPTs, small outline packages (SOPs), CLCCs and PLCCs;
however, the use of QFPT and SOP sockets is normally restricted to prototyping and bum-in, while lowcost, reliable production sockets are more commonly available for PLCCs and CLCCs. These production
sockets house the SMD (they are tightly tailored to the specific package) in one of two ways. Flatpacks and
LCCs use low/zero insertion force with a lid that closes down on the package. PLCCs use pressured socket contacts that drive a pin into the underside of the socket. Socket pins are arranged like those of PGAs:
they are through-hole, they have l00-mil spacing (generally), and they are most commonly oriented in a
grid of two rows.

One advantage of these sockets is that in applications where through-hole packaging is required and the
choice of through-hole packages is limited to PGAs, a plastic SM package plus the production socket will
cost less than the through-hole PGA. The scenario typically occurs when the reqUired number of pins is
between 40 and 84 for PLCCs and LCCs and up to 160 or more for the flatpacks.

1-142

CMOS Channeled Gate Arrays

Application Notes

Another significant reason to socket SMDs results from the manufacturing difficulties of SMDs that were
presented earlier. ASIC devices are usually among the largest in the system, and the most vital and expensive. For the purpose of field maintenance, many companies feel it is more economical and reliable not to
risk running an ASIC device through wave or reflow solder and risking stress fractures or other damage.
Furthermore, the test probing difficulties alluded to earlier are alleviated with sockets, which usually provide easy access to the contacts. Often, once reliability of the system is proven, the boards are re-laid out
with surface mount devices. Therefore, simply because a manufacturing facility isn't geared up for SMT
does not mean that SMT devices cannot be used there.

3.3.2 Noise Problems With Sockets
Sockets for SMDs are convenient for manufacturers not yet ready to go to SMT, or for initial prototyping
where the device may frequently be removed. Socketing permits the user to gain many of the benefits of
SMDs, such as reduced profile and support of high pin counts in plastic, while avoiding the drawbacks,
such as special manufacturing equipment and lead probing difficulties. Unfortunately a major electrical
advantage of SMDs, low pin inductance, is compromised when sockets are used. The primary result is
greatly increased noise, which adversely affects overall speed and signal quality. In fact, a socketed SMD
generally has a higher lead inductance than an equivalent through-hole PGA.
3.4 Summary of the Packaging Alternatives

Having reviewed the package selection alternatives presented in Section 2.0 and the various tradeoffs between the packages discussed in this section and summarized in Table 6 below, the designer can weigh the
benefits and limitations of the various packages and arrive at an optimal packaging scheme.

1-143

CMOS Channeled Gate Arrays

AepliC8lion Noles

Table 6. ASIC CMOS Package Types and their Characteristics
Package
Type

Range of Physical
Dimensions

Electrical
Characteristics'

Thermal
Characteristics
(CClWatt)

Usable
Gates3

Relative
Cost
(per Pin)

ThroughHole
DIP

# Pins:
Pin Pitch:
Body Length:
Body Width:

16 to 64
100 mils
.7S" to 2.3"
.300" to .700"

R: Medium
L: High
C: Low

Ceramic/Plastic
9JA2:
70 - 40/
120-80

Upto
17K gates

1

Surface
Mount
SOIC

# Pins:
Pin Pitch:
Body Length:
Body Width:

16t028
10 mils
SO to 70 mils
.300" to .400"

R:Medium
L: Medium
C:Low

Ceramic/Plastic
9JA2:
110 - 80/
130 -lOS

Up to 6S00
gates

1

# Pins:
Pin Pitch:
Body Width:

48 to 260
10 mils
.65" to 1.7"

Plastic
Surface
Mount
QFPT

R: Medium
L: Medium
C: Low

9JA2: 9S - 60

Upto 17K
gates

1

Ceramic
Surface
Mount
CLCC

# Pins:
Pin Pitch:
Body Width:

28 to 84
40 to SO mils
.45" to .97"

R: Medium
L: Medium
C: Medium

9JA2: 70-45

Upt02SK
gates

S

Plastic
Surface
Mount
PLCC

# Pins:
28 to 84
Pin Pitch:
SO mils
Body Width: .49" to 1.19"

R: Medium
L: Medium
C:Low

9JA2: 6S - SO

Upto 17K
gates

Ceramic/Plastic CeramiC/Plastic
ThroughHole
PGA

# Pins:
Pin Pitch:
Body Width:

64 to 299
.100 mils, 70 mils
1.033" to 1.7"

R: Low/Low
L: Lowllow
C: High/Low

9JN
40 -19/
46 -38

1.0S
Ceramic/Plastic

Upto 7SK
gates
11/3.S-S

Notes: 'R = Resistance, L = Inductance, C = Capacitance
2Assuming Static Airflow
3Assuming I.SI! CMOS Technology

4.0 Electrical Considerations for the Assignment of Signal, Power, and Ground Pins
Driven by the continual demand for high speed systems, CMOS ASICs that exhibit output drive levels,
rise and fall times, and propagation delays comparable to yesterday's ECL circuits are now being developed. Consequently, the problems intrinsic to ECL design (even thermal management> are now appearing
in CMOS designs. These problems, based on noise and its effect on the device, are introduced in this section and possible solutions are discussed.
4.1 Sources and Magnitude of Noise
CMOS circuits operate by charging and discharging node capacitances through pull-up or pull-down
transistor networks constructed of P channel and N channel enhancement mode (normally off) MOSFET
transistors. As a result, these circuits generate noise when switching. The following review of basic CMOS
circuits and how they work explains this phenomenon in greater depth.

1-144

Application Notes

CMOS Channeled Gate Arrays

4.1.1 Basic CMOS Circuits

Figure 14 shows a CMOS totem pole output buffer, the typical implementation for CMOS circuits, while
Figure 15 illustrates a CMOS-compatible input buffer, and Figure 16 depicts a CMOS input buffer configured to be TIL compatible.

Rp-ON

Bonding
Pad
Interconnect

T

cL

Figure 14. CMOS Output Buffer Model (Totem Pole)

Input

Package
Capac~ance

1KQ

Bonding Pad
Capacitance

Wire and Input Gate
Capacitance

Figure 15.110 Model, CMOS Input

1-145

CMOS Channeled Gate Arrays

Application Notes

The sw~ching threshold of an inverter is dependent on the supply voltages and mobility
(11) of the P and N type transistors, as well as
the W to L (transistor width to gate length)
ratio of the Nand P transistors. By varying
the effective width (W) of the P and N transistors, it is possible to devise inverters (input buffers) that will sw~ch at TTL levels
even though they are implemented with
FETs.

External
Input

Internal
Array

Thresholds of
P and N transistors
Supply vottage

Figure 16.1/0 Model, TTL Input

Internal CMOS circuits, such as the NAND gate shown in Figure 17 are typical of CMOS logic designs,
which can be represented as a pull-up network and a pull-down network, each with its own logic and
analog characteristics.

7
Pull-up
Network

I

T

O~tput

'--

Pull-down
Network

..l
General Structure:
Output Is either pulled up or down. Inputs
are never active or inactive simultaneously

An Example of a 2-lnput NAND Gate

Figure 17. CMOS Basic Gate Structure: The Pull-up/Pull-down Network

1-146

Application Notes

CMOS Channeled Gate Arrays

The other type of element used in CMOS circuits is the transmission gate, or T-gate, which is useful for the
efficient construction of multiplexers and sequential circuits (D-flops, latches, etc.) as shown in Figure 18.

!SE[
IN

0

I

t
I

SEL

OUT

P Transistor

0

o

OUT

Hi-Z

(floating)

IN

(pass)

N Transistor

SEL

Transmission gates either pass a signal or inhib~ ~ by floating, perm~ting another, active transmission gate to
drive the bus to which multiple transmission gates are often tied. Transmission gates are useful for constructing
multiplexers and flip-flops.

Figure 18_ CMOS Basic Gate Structure: The Transmission Gate
4.1.2 Output SwHchlng Noise and Simultaneous Switching Outputs (SSOs)
The greatest source of noise in a CMOS circuit is the result of an output switching either high to low or
low to high, particularly into or out of a high capacitive load. CMOS outputs drive two types of loads,
either CMOS loads, which are high in capacitance but low in leakage current, or TIL loads, which are
lower in capacitance but higher in leakage current. Therefore, the AC and DC currents that the buffers see
when they switch depend greatly on the type of driven load and its capacitance. When this load discharges through the N-type transistor of the totem pole output, as illustrated in Figure 14, the effect is that
of a capacitor discharging through resistance. Consequently, the initial current is high and decreases over
time as the output node capacitance becomes charged. Similar currents may be observed when charging
the node capacitance, as in the case of a low-to-high transition.

1-147

Application Notes

CMOS Channeled Gate Arrays

Figure 19 shows the characteristic resistance and capacitance of various parts of the output of an ASIC
device.
Chip Power Plane

C

0 ...•..
'"

d~ and it

' - - t - - Chip Ground Plane

-=

Vss
System Ground Plane

SSO noise is proportional to the number of SSOs, the current switched by each in a common
direction (H to L in this case), and the inductance between the load and the system ground. This
is represented as

.1. V (ground bounce) = (- L)
where N is the number of SSOs, assuming all have the same dildt.

Figure 19. Electrical Model of Simultaneously Switching Outputs

Although small, the total inductance becomes a critical factor when discharging or charging output capacitance, since the instantaneous current (i) is high. Recall that the self-induced voltage in an inductance,
(L) is expressed by
.1.VINDUCED =

L *di

----at

where t is time and d is rate of change.
In a high-drive CMOS device driving high loads, such as 200 pF, through a voltage swing approaching
5 volts with a rise/fall time of < 2 ns, the instantaneous current may be

i = C • dv

dt

... C • .1.v

M

(average over rise and fall time)

This induced voltage appears as noise on the receiving end of the signal as referenced to the ground. The
current on a high-to-low transition is sunk into ground, causing the current to "bounce" or rise relative to
other signals referenced to it. This ground bounce phenomenon may also apply to power on low-to-high
transitions, yielding a similar noise problem.
Noise on signals may cause false triggering on the input buffer(s) being driven, or at least create a window of ambiguity in the time at which the driven input should switch (see Figure 20). Therefore, noise
may result in degradation in speed resulting from adding settling time to a delay and may even result in

1-148

Application Notes

CMOS Channeled Gate Arrays

functional effects if false triggering occurs. Furthennore, if N multiple outputs under this condition switch
simultaneously, the induced voltage is increased as a multiple of the number of outputs

ill

nV =N· L· dt

V1N

•

E

2.0V

0.8 V

0.0 V
Noise Margin Reduction Due to SSOs
•

In this example, outputs switching H to L resu~ in a ground bounce or rise in the chip ground relative to
system ground.

•

The rise appears as IT the input signal voltage levels are reduced proportionally. If the bounce is too
great, the input voltage is below V1H causing false triggering.

•

In the L to H case, it is the low input levels (VIL ) that are affected.

Figure 20. Effect of SSO Noise on Thresholds

Not only inductance but also characteristic resistance can create noise problems. The following paragraphs summarize the types of noise that exist in CMOS systems and explain how packaging impacts this
noise.
4.1.3 Self·lnduced Noise

Self-induced noise results when high-speed, high-drive outputs switch and introduce a spike on the signal
relative to ground. The SSO effect, discussed previously, is an example of the level of self-induced noise
that can occur. It is predicted by

~VSI =L ill
f1t

where L is the inductance between the pin and ground as well as the trace inductance. ~i is the instantaneous current and M is the fall/rise time.
4.1.4 Mutually Induced Noise

Mutually induced noise (a fonn of crosstalk) occurs when a signal trace that has been running parallel to
another for some distance switches, inducing a voltage into the adjacent wire. Since both inductive and
capacitive coupling occur only during signal transition and propagation, the effect is additive, as the signal propagates down the trace. Resultant noise propagates in both the forward and backward directions
down the line. The forward crosstalk has a pulse duration equal to the rise and fall of the signal, with an
amplitude equal to the difference between the capacitive and inductive coupling. Backward crosstalk has
a pulse duration equal to the transition time down the trace and an amplitude dependent on the sum of
the inductive and capacitive coupling as well as the trace length.

1-149

CMOS Channeled Gate Arrays

Application Notes

4.1.5 capacitive Coupled Noise

Another form of crosstalk resulting from mutual signal coupling, this noise occurs in proportion to the
dielectric constant of the board, the distance of trace separation, and the trace length and width. Acting as
two thin parallel plates, these traces couple switching current as integrated over time.
4.1.6 Ringing on Signals

From basic circuit theory, the designer will recall that if the signal line impedance does not match the output impedance of the buffer, then the signal is not naturally dampened. If the impedance of the load is less
than that of the buffer, the signal is over-damped and will have a slow rise/ fall time. However, if the
buffer possesses lower impedance, then the signal is under-damped and may ring, as illustrated by
Figure 3. Typically, signal line impedances are in the range of 50 to 250 0, while in the past buffers possessed "on" resistances of 500 0 to 2 Kn. However, due to the need for higher current sourcing/sinking
and faster switching speeds, "on" resistances of output buffers have come down to the 10- to 50- 0 range,
requiring the use of special termination techniques, discussed in the Fujitsu Application Note ''Interfacing
CMOS and BiCMOS VLSls."
4.1.7IR Drop

Up to this point, the sources of noise discussed have depended on inductance or capacitance. Since the DC
current that a ground pin may sink, or that a power supply pin may source can be significant, the familiar
voltage drop across a resistor, as current passes through it, is also a source of noise. This iR drop is the
phenomenon that limits the sum of source and sink currents through power and ground pins respectively.
Ohm's Law describes the effect of this noise source in the following equation defining voltage rise or drop
due to iR effects:
N-l
~V=R

*

~

4.

n=O
where
R is the output pin-ta-ground (sink) resistance, or power pin return-loop (source) resistance (including the "on" resistance of the respective N or P channel device) and

4. is the current through the nth output pin connected to this common ground or power pin.
4.1.8 Current Spiking or "Crowbar Noise"
As Figure 14 illustrated, a CMOS output buffer is constructed as a totem pole in which the output is taken
from the common source (P type) and drain (N type) with the drain of the P type connected to power and
the source of the N type connected to ground. When the input to the totem pole (the P and N gates)
switches, the Miller capacitance of the gate causes the gates to charge or discharge at some specified time
constant. It is possible that both transistors can be on, one in saturation and the other passing through the
linear region, creating a current path between power and ground that can damage the device. This is less a
concern for internal transistors than it is for the "beefy" transistors at the I/O. This current spiking can not
only introduce noise on the power and ground planes, but may damage the device as well. For this reason, Fujitsu has taken precautions in the design of the CMOS output buffers to prevent this problem from

occurring.
4.2 Recommended Strategy for Pin Assignment

The assignment of Oock, Scan, and other signals, as well as power and ground, to specific pins on the
package affects electrical behavior (speed, noise, reliability, etc.), board manufacturing requirements, and
device reliability. Therefore, optimal pin assignment strategies should consider the variables over which
the user has control (placement of non-scan inputs, outputs and bi-directionals) and the variables over

1-150

Application Notes

CMOS Channeled Gate AmilYs

which the vendor has control (power, ground and scan signal placement). Out of these relationships a
method of placement can be developed, using the following approach:
(a) Prioritize the signals whose placement is most critical.
(b) Establish guidelines for the location of these signals, both in absolute position and relative to
other signals.
4.2.1 Prioritization of Signals for Placement
Noise minimization is used to establish signal prioritization. All of the various forms of noise discussed in
the last section are dependent on either i or di/ dt, and L, M, R, or C. The signals affect i and di/ dt, while
the package pin location affects L, Rand C. Figure 21 provides an illustration of how electrical characteristics vary by pin position.
l R C

~

t
Increasing

C::::'
:
::::
I
~

Ilncreasin g

l RC

Figure 21. Variation in Inductance, ReSistance, and Capacitance
as a Function of Pin POSition

In general, the further a pin's external contact is from the die connection, the greater its resistance, impedance, and capacitance. Therefore, signal prioritization is established according to current or its time derivative, while location is guided by package pin characteristics. Input signals are classified by their noise
sensitivity. If a spike on an input could be disastrous (as with a clock), that signal should be carefully located. Table 7 classifies signal type by electrical characteristics.
Table 7. Electrical Characteristics of Each Signal Type
Signal Type
Ground

Current Characteristics (General)
Highest i, DC, and di/dt

Power

High i, DC. and di/dt

High d rive outputs

High di/dt

Clocks

Highest noise sensitivity

low drive outputs

---

Other Signals

4.2.2 Characteristics of Package Pins by Location
The inductance, capacitance, and resistance, all of which are critical to minimizing noise, are related not
only to board construction, but also to the pin position on given packages, and the circuit to which the
pins are bonded. The pin, lead frame, bonding wires, pads, and buffers (input, output or bi-directional) all
influence the characteristic L, R, and C of the line. See Figure 22.

1-151

CMOS Channeled Gate Arrays

Application Notes

• 0
• 00
•
• 00
•
• 00
• 0
•
• 0
• 00
•
• 0
• 00
•

•
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0

0

I I II I "

76543210
(pF)

I I I I I I I I
o1 2 3 4 5 6 7

I

(pF)

•

Package Pin

Capac~ance

Total 110 Pin Capacitance
Figure 22. Measured Pin Capacitance by Package Position
4.2.3 Relating SlgnallYpe to Pin Location

Since power and ground pins demand a large DC current (i), iR drops are of great concern. Therefore,
Fujitsu assigns power and ground to pins with minimum resistance (and inductance). High-drive outputs
exhibit a large di/ dt, resulting from high capacitive loading, so the best pins for these signals are those of
minimum inductance. Furthermore, adjacent pins possess the greatest M, and thus couple the most M di/
dt noise. This means that noise-sensitive inputs, such as clock inputs, should be isolated from pins that
handle high di/ dt, such as high-drive outputs.
4.2.4 Minimizing IR Drops on Power and Ground Pins

Placement of ground pins is critical because noise on ground affects the voltage level of all signals referenced to it. For this reason, Fujitsu has preassigned power (VDD) and ground (VSS> signals for all packages
in a given gate array family according to the electrically optimal locations. Preassigning power pins permits Fujitsu to develop load boards (which interface the packaged device to the tester) advanced enough
to carry out high-speed functional testing of devices with high I/O count and to drive devices with relatively low noise. Fujitsu also took into consideration manufacturing issues such as adjacent pin shorting
due to probes and package rotation. The predefined power and ground assignments for Fujitsu devices
are found in the Package Pin ASSignment Guide in the Design Manual for the appropriate gate array family, and are used in conjunction with the Package Matrix to determine pin assignment.
4.2.5 Minimizing the Self-Inductance of a Signal

Fujitsu believes that an ASIC designer concerned about designing a mini-computer, PC, mainframe or
other complex system should not have to be concerned with determining specific on-chip noise issues,
particularly since board-level noise issues are demanding enough. Therefore, Fujitsu developed a straightforward grouping scheme for the placement of various types of signals relative to their distance from the
nearest power and ground pins. As Figure 23 shows, the self-inductance associated with a given signal is

1-152

Application Notes

CMOS Channeled Gate AlTays

a function of the length of wire between it and its nearest ground (for a falling transition) or power (for a
rising transition).

..

T
Second-order model of an output driving interconnect metal and four input buffers.
As wire-length increases. so does inductance and resistance.

Figure 23. Self-inductance In a Circuit

Since di/dt can vary greatly for outputs within a group, there are some general restrictions relating to
SSOs and their total current to the number of grounds on the chip. This is done by summing representative values like those shown in Table 5-4 in Chapter 4, which are weighed depending on the IOL of the
given output buffer. Notice that, if the output buffer employs noise limiting circuitry (edge rate grading)
then di/dt is less and the representative value is also less, meaning more of these outputs can be supported per ground pin.
In summary, to ensure that the iR drops and the ground bounce effect (L di/dt) are within reasonable
limitations, Fujitsu has established guidelines for determining the number of necessary grounds and defining the pinout.
4.2.6 Placement of Clock and Asynchronous Clear/Preset Signals
In addition to causing the ground bounce and iR drops that can deteriorate an output signal's quality and
alter the ground reference, output switching can also couple noise into adjacent sensitive inputs by mutual
inductance, as shown in Figure 24. For that reason, the designer should ensure that clocks and asynchronous clear and preset signals are not placed near outputs, particularly high drive outputs. To further isolate inputs from noise, the designer should minimize the inductance (length) of the return loop from the
input buffer to ground by placing this type of input near a ground pin. The mutual inductance of the input buffer itself can be minimized if it, and any outputs nearby, are not assigned to high inductance pins.
As discussed in Section 4.2.1, the center pins of a DIP, flatpack, or PLCC possess the lowest Land R, as do
the inner rows of PGAs, making them most suitable for VDD, Vss and high drive outputs. But the edges of
the package, while suitable for data signals, should be avoided when placing clock and other sensitive
Signals, as they exhibit a high mutual inductance and large iR drop.

1-153

CMOS Channeled Gate AlTars

Application Noles

0-' :
'
..

INput
Signal

fs1'\
0

; ~ :A_t;.;\

o-y:---::v 6
Ignored for simplicity

•

I

.'

Noise is introduced on the adjacent lead S2 as Sl is driven in a manner described by Faraday as
di 51

Vs= -M'"Cit
where M is the mutual inductance between the adjacent leads.
I! S2 is also being driven, then the mutually induced noise is superimposed on the
sel! induced noise already present, as described by

di 51

di 52

VS2 = -M '"Cit + L:!'"Cit
Figure 24. causes 01 Crosstalk
4.3 Summary: Choosing the Package and Assigning the Pins
This discussion of noise as related to packaging and its effect on pinout should help the designer appreciate the care Fujitsu has taken to ensure that noise margins within the device are restricted to maximize
system reliability. It should also provide the designer with a basis for establishing optimum pin assignments. A step-by-step procedure for choosing an optimal package and assigning pins to it follows.
4.4 Package Selection Checklist
When selecting a package for an ASIC device, the designer should consider the following points:

a.

Define a subset of the Fujitsu packages that can be supported by your company's manufacturing capabilities.

b.

Estimate, as closely as possible, the gate and I/O counts of the circuit(s) to be packaged.

c.

Determine the number of power and ground pins reqUired by considering the following:

1.

1-154

Representative value limitations for SSOs

2.

Limitation of the sum of the sink current (lOL) per ground pin

3.

Limitation of instantaneous current per ground pin to satisfy metal migration
restrictions

d.

Using the package and pin assignment section of the Design Manual, determine the packages
that satisfy the signal, power, and ground pin requirements of the circuit.

e.

Make sure that the electrical, mechanical, and thermal properties of the chosen packages are
suitable for the application.

f.

Check the mechanical dimensions in Fujitsu's ASIC Package Catalog and the power and
ground pin assignment tables and grouping charts in the appropriate package and pin assignment tables for the chosen technology. Please contact Fujitsu regarding pricing trade-offs when
evaluating packages or partitioning the system.

CMOS Channeled Gate Arrays

Ape/ication Notes

4.5 Pin Assignment Checklist
a.
Follow Fujitsu's pin assignments in the Package and Pin Assignment section of the Design
Manuals. Although multiple pinouts of the same package may be offered in some cases, all
power and ground signals indicated on the chosen package must be connected on the board.

b.

Assign input pins (in excess of 5 MHz) and high power output buffers (IOL = 24 mAl according to the appropriate pin assignment table.

c.

Place all high-drive (power and high power) outputs near ground pins; the higher the drive,
the closer they should be placed. SSOs should be placed particularly close to ground pins.

d.

Place SSOs in groups belonging to given ground pins.

e.

Distance noise-sensitive signals such as clock and asynchronous clear and preset signals away
from SSOs and high-drive outputs. Also, assign them to pins with low inductance and resistance, preferably near a ground, if one is available away from SSOs or high-drive outputs.

f.

Place SSOs on low inductance pins, such as those located on the inner rows and middle position of the PGAs.

These guidelines assist the designer in choosing the best package for the application, resulting in a device
with reliable and predictable electrical performance and without harmful DC and AC effects on the system. There are other system interface issues such as device decoupling and termination that should be
considered during design. These are discussed in Fujitsu's application note, "Interfacing CMOS and BiCMOSVLSls."
5.0 Thermal Issues In CMOS ASIC Packaging
CMOS has traditionally been associated with low power, one of the classic advantages it has over ECL.
While ECL continually draws high current to supply its internal differential amplifiers and emitter-follower circuits, CMOS draws current primarily when it is switching. The total power diSSipation of a
CMOS device is dependent on the number of gates, the switching frequency, and the loading on the output of the gates. The revolution in CMOS technology that has resulted in densities of lOOK gates has been
accompanied by increases in all of the factors influencing power dissipation. Prior to 1985, when FUjitsu
introduced the world's first 20,000 gate array, the C2ooooUH, CMOS gate arrays were not of sufficient integration density to warrant concerns about thermal control, but advancing CMOS technologies have
forced this issue to the surface.

Because power is the product of current and voltage, power dissipation is important when defining the
necessary power supply currents. Propagation delays and reliability of a device are also dependent on the
temperature at which the die operates, as discussed in Sections 2.3.3 and 2.4.4. To ensure that speed and
reliability requirements are satisfied, the designer needs to estimate the power diSSipation of the device
and, from this information, choose appropriate packages and system cooling techniques.
5.1 Estimation of Power Dissipation In CMOS Circuits
There are two constituent factors in the power dissipation of a semiconductor device: the DC power,
which is dependent on the steady-state (quiescent) current, and the AC or dynamic power.
5.1.1 Estimation of Dynamic (AC) Power Dissipation
CMOS circuits are constructed of PETs, which possess very small leakage currents. Therefore, CMOS possesses a low quiescent or steady-state current. CMOS dissipates power primarily while it is charging or
discharging node capacitance, or drawing switching current, which occurs as a gate changes state. This
can be modeled as the familiar pull-up/pull-down circuit discussed in Section 4.1, charging and discharging a node capacitance, CL (shown in Figure 14). This model holds true whether the node is internal or
off-chip.

1-155

..

Application Notes

CMOS Channeled Gate Arrays

The switching current is a result of charging and discharging the node capacitance which, for periodiC signals, occurs twice a cycle: once while charging the capacitance, and once while discharging it. The energy
involved in charging or discharging a capacitance is 1/2(CLV2). The power is the energy divided by the
period of time between successive changes (the clock period, T), multiplied by the two transitions that
occur per cycle. Therefore, the dynamic or switching current of a CMOS circuit is defined as
Pd-dyn=2

• (CL. V2)

2 • T

where V is the supply voltage and f is the frequency of the given signal.
This is the power calculation for a single gate. The power dissipation for entire chip, however is much
more complicated, since not all gates are simultaneously active. The degree of switching activity varies
greatly within a circuit and depends on the nature of the circuits (synchronous sequential gates tend to
switch concurrently, while combinatorial gates switch more randomly), the input stimulus (whether the
circuit is stimulated at a periodic interval or asynchronously), and other design-dependent issues. Based
on Fujitsu's experience, gate activity is on the average about 20 percent. This same figure is applied to the
power estimation for output and input buffers.
5.1.2 Estimation of Quiescent (DC) Power Dissipation
There are two sources/ sinks of DC current in a CMOS ASIC: the leakage current of the gates (gate leakage) and the DC current that flows through output and bidirectional buffers in output mode. The gate
leakage in CMOS devices, even dense ones, is in the range of tens of microamperes, and is negligible. The
DC current of the output buffers is the current that the buffer sources or sinks in steady state. This current
level depends on the leakage currents of the driven loads, but for simplicity will be assumed to be equivalent to the IOL and IoH rating of the buffers. The DC power can be estimated for each output buffer by
analyzing:

a.

the product of source current times the voltage difference from the power rail (V DO - VOH), and

b. the sink current times the low-level voltage (VOL).
This calculation is valid provided the duty cycle, or the portion of the cycle in which the output is low versus the portion of the cycle in which the output is high, weighs the sum of the two components. The total
DC power may be determined by extending this method to each output and bidirectional buffer.
5.1.3 Estimation of Total Power Dissipation
The total power dissipation of a circuit is the sum of the DC and AC components. I/O buffers dissipate
both DC and AC power when switching, while internal gates may be considered for the sake of simplicity,
to dissipate only AC. The theory behind CMOS power dissipation is simple; however, the task of calculating the power dissipation can be tedious and prone to error. Therefore, Fujitsu has devised methods for
estimating the power dissipation for each CMOS technology. These methods are presented in the Design
Manual for the appropriate technology, available through the Field Applications Engineers at local Fujitsu
Sales Offices or Technical Resource Centers.
5.2 The Relationship Between Power Dissipation and Temperature

A device draws current through the power supply pins and the I/O buffers. As it does so, it dissipates
thermal energy proportional to the power dissipated in the device. Assuming that the power diSSipation
of a device has been estimated as Pd, using the method described in Section 5.1.1, how can one relate this
power to the temperature of the die and the package, and also determine the warming effect on the surrounding environment?
The answer lies with two principles of heat transfer: conduction and convection. When an object is in a
state of thermal equilibrium it is isothermal, seeing a constant temperature across its body. As the tem-

1-156

Application Notes

CMOS Channeled Gate Arrays

perature of one end of the object is raised by the introduction of energy, it is no longer in equilibrium; heat
begins to flow from the warmer region to the cooler region through the process of conduction.
When a lake in winter is filled with water at a constant temperature, just above 32°F, it may still freeze. It
will freeze at the surface, however, not the bottom. This is because heat is drawn from the water into the
air through convection, the act of cooling by a gas.
These same mechanisms, conduction and convection, act upon a packaged semiconductor device and determine its junction temperature, the package or case temperature, and the warming effect on the surroundings.
5.2.1 Determining the Junction Temperature of a Device
Figure 25 shows the paths through which heat flows in a packaged device. Each interface of materials
with different properties of thermal conduction must be considered when determining the flow of heat
from the die to the surroundings. The back side of the die is attached to a lead frame or slug, usually by
means of a eutectic bond (material heat bonded with some conductive material, such as silver). Heat flows
through this path from the die to the package, then from the package to the surrounding air.

TA

VA

t..rv+
t..rv+
...t..rv+
"n
t..rv+
t..rv+
t..rv+
t..rv+

I
I:~~rrl

~

.JI

JI

,

~

..........

-----,,

ie

I

~ 9ii,!ity ••••••• _ ••T!. •• _:

.~~ u

rnJ=l

II

u

.ij-l

I

Figure 25. Heat Flow through a Cavity-down Ceramic PGA with an Annular Fin Heat Sink

From the die junction to the package, there is some associated thermal impedance (or resistance to the
flow of heat). This impedance can be calculated, but may also be estimated in the following way. Operate
a device and determine its power dissipation. Then, using some mechanism such as a thermal diode,
whose forward bias voltage tracks linearly with temperature, determine the junction temperature. Then,
after measuring the case temperature, determine the thermal impedance along the path from the die junction to the case (package body) using the following equation:
Sjc =

(Tc - TO
Pd

where Tc and Tj are the case and junction temperatures, respectively.
A similar procedure is followed when determining the thermal impedance between the junction and the
ambient environment, except that the case temperature is replaced by the measurement of the ambient
temperature

1-157

..

Application Notes

CMOS Channeled Gate AlTlIys

While OJ, relies on conduction as its cooling mechanism, 9p. reflects convective cooling. Therefore, 9j" varies with airflow and is specified at a given airflow, or as static (= 0).
Since thermal impedance depends on the heat conduction path between the die and some other interface,
it can be modeled the same way as current flOwing through real impedance or resistance. Therefore, as in
circuit theory, when multiple interfaces are oriented in parallel, the thermal impedance is lowered. However, the situation is different from circuit theory in that when a very low impedance interface, such as a
heat sink, is placed in the conduction path the flow capacity is increased, with the heat sink pulling heat
out at a faster rate, lowering the thermal impedance.

5.2.2 Using Thermal Impedance Data
Thermal impedance information and power dissipation information are used to estimate junction temperature and ambient temperature rise. Which impedance figure to use is based on how the device is to be
cooled. H the device is air cooled (convective), then 9ja should be applied, while 9jc should be used if conductive techniques such as heat pipes or cold plates are employed. For example, the junction temperature
may be obtained by multiplying the power dissipation of the device by the appropriate 8ja and adding
the ambient temperature. It is not surprising that this indicates that a small thermal impedance is desirable to achieve a low junction temperature.
Junction temperature is used to determine worst case delay multipliers and the package options for
Fujitsu's CMOS AU (Sea-<>f-Gates) family. The junction temperature also indicates whether reliability
goals are being met. The designer can trade off packages (which exhibit varying thermal impedances)
with cooling techniques (such as varying the amount of airflow in a system) to achieve the desired junction temperature and consequently, worst case delay multiplier and reliability targets.

5.3 Summary Of Thermal Issues
Although thermal factors in CMOS design have not previously been an issue, the increased frequency and
density of current generations of CMOS devices require such considerations to be made. This section ha.s
surveyed some of the issues involved in applying thermal analysis to CMOS devices and using the information gained from such analysis to determine the appropriate packaging and cooling techniques.
6.0 Summary of the Note
As VLSI circuits increase in complexity, pin count and die size increase as well, placing greater demands
on packaging, board layout, and manufacturing. Fujitsu has addressed these problems with exotic forms
of packaging such as the surface mount PGA and the staggered PGA, while also stressing the importance
of other surface mount packages. But simply making these packages available is not enough; FUjitsu must
also provide the technical support necessary to ensure that these packages can be used successfully by our
customers. Field Applications support in the local sales offices, technical information such as this Application Note, and packaging consultants at Fujitsu's San Jose headquarters all provide this support.

1-158

CMOS Channflled Gate Arrays

Application Notes

References
Applications Engineering Staff. Points and Problems on Reliability and Mounting of Surface Mount ICs. Fujitsu
Limited,1988.
Hoshino, H. and K. Gotanda. Reliability of Surface Mount ICs. Fujitsu Limited, 1987.
Kane, Jim. Surface Mount Technology. Santa Clara: Fujitsu Microelectronics Inc.; August 1986.
Fujitsu Limited, Semiconductor Marketing. Integrated Circuits Quality and Reliability. Tokyo, Japan: Fujitsu
Limited, 1984.
Mather, John C. "A Status Report on Multilayer Circuit Boards." Proceedings, 30th Electronic Components

Conference. 1980, pp 302-306.
Vest, Roger. "How to Design a Fine Pitch Footprint." Nepcon East: 1988.

..

1-159

Application Notes

1-160

CMOS Channeled Gate Arrays

Section 2
UHB Series CMOS Gate Array Unit Cell Library

I Page

Contents

2-2
2-5
2-15
2-31
2-47
2-53
2-59
2--69
2-77
2-85
2-107
2-117
2-157
2-185
2-217
2-225
2-243
2-255
2-283
2-287
2-293

Unit Cell Specification Information
Inverter and Buffer Family
NAND Family
NOR Family
AND Family
OR Family
EXNOR/EXOR Family
AND-OR-Inverter Family
OR-AND-Inverter Family
Multiplexer Family
Clock Buffer Family
Scan Flip-flop (Positive Edge Type) Family
Non-Scan Flip-flop Family
Binary Counter Family
Adder Family
Data Latch Family
Shift Register Family
Parity Generator/Selector/Decoder Family
Bus Driver
Clip Cells
110 Buffer Family

2-403
2-405
2-407
2-413
2-415
2-419

Appendix A: General AC Specifications
Appendix B: Hierarchical Structure
Appendix C: Estimation Tables for Metal Loading
Appendix D: Available Package Types
Appendix E: TTL 7400 Function Conversion Table
Appendix F: Alphanumeric Index of Unit Cells

I

2-1

UHB Series Unit Cell Library

CMOS Channeled Gate Arrays

Unit Cell Specification Information
This section contains specifications for all the unit cells available for the UHB Series CMOS Gate Arrays. The
unit cell (gate array) is a functional group of one or more basic cells or gates. A basic cell contains one pair of
P-channel and one pair of N-channel transistors.
How to Read a Unit Cell Specification
The following paragraphs numbered 1-10 explain how the information given in the UHB Unit Cell Library is
organized. Each of the numbers corresponds to an area of the Unit Cell Library page illustrated on the right.
1.

The unit cell name appears in the upper left corner of the page.

2.

The unit cell function is given on the same line as the unit cell name.

3.

The number of basic cells (BC) or equivalent that make up the unit cell is shown in the upper right
corner of the page.

4.

Propagation delay parameters for the unit cell are given in a table on the upper right side of the
page. The basic delay time of the unit cell (to) is given in ns. KCL, the delay constant for the cell (delay time per load unit) is given in ns/pF. KCL2 and COR2 are a delay constant and an output drivinm
factor used to calculate delay when a unit cell is loaded beyond its published output driving factor
(CDR)·

5.

The cell (logic) symbol is shown in the top left box under the cell name.

6.

Clock parameters (in ns) for unit cells such as flip-flops and counters that make use of clock signals
are given in a table directly below the propagation delay parameters.

7.

Input loading factors are shown in a table directly under the cell symbol box on the left side of the
page. The input loading factor is the value of the load placed on a net by the connection of the unit
cell input. Unit cell loading factors are shown in load units (Iu). The Fujitsu CMOS load unit is the
input capacitance of an inverter used for the measurement and calculation of capacitive loads presented to unit cells within the gate array.

8.

The output drive factor is shown directly under the input loading factor. The output drive factor is the
maximum number of load units the unit cell can drive while performing at published specifications.

9.

The function (truth) table, if applicable, is shown in a box at the lower left side of the page.

10.

The unil cell schematic, or equivalent circuit, illustrates how discrete components would be connected to perform the unit cell function. II is shown in the lower righl corner of the page or on the
page following.

2-2

CMOS Channeled Gate

AtTars

UHB Series Unit Call Ubrary

I

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

1

T2D

NumberofBC
2

2:1 SYlector

I

CeASymbol

Propagation Delay Parameter

I

2
3

A

to

KCL

to

KCL

0.50
0.54

0.15
0.15

0.56
0.41

0.10
0.10

Path

CDR2

A,B~X
S~X

p-X
'---

6

Parameter

Pin Name

Input Loading
Factor (Iu)

A,B
5

1
1

Pin Name

Output Driving
Factor (Iu)

X

14

8

Typ(ns)*

Equivalent Circuit

Inputs

Output

A

B

51

S2

X

L
H
X
X
L
L
H
H

X
X

L
L
H
H
L
H
L
H

H
H
L
L
L
H
L
H

H
L
H
L
INHIBIT
INHIBIT
INHIBIT
INHIBIT

L
H
H
H
L
L

Symbol

* Minimum values for the typical operating conditon.
The values for the worst case operating condition
are given by the maximum delay mUltiplier.

Function Table

9

KCL2

-

B:::O

SI
S2-

7

tdn

\up

4

5

UHB Version

Function

A

10

f-o
B

X

-

51

S2

UHB-T2D-E2

Sheet 111

I

I

Page 17-17

2-3

UHB Series Unit CfIIl LibrIllY

2-4

CMOS Channflled Gate Amrys

CMOS Channeled Gale AlTBys

UHB Series Unit Cell Ubrarr

Inverter and Buffer Family
Basic

UnRCeIl

Page

Name

2-7

V1N

Inverter

2~

V2B

Power Inverter

1

2-9

V1L

Double Power Inverter

2

2-10

B1N

True Buffer

2-11

BD3

True Delay Buffer

(> 5 ns)

Function

Cells

1

5

2-12

BD4

Delay Cell

(>4ns)

4

2-13

BD5

Delay Cell

(>10 ns)

9

2-14

BDS

Delay Cell

(>22 ns)

17

2-5

CMOS CharrnBIsd Gate Anays

2-6

I "URB" Version
I Number of BC

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name _I Function

I

I Inverter

V1N
Cell Symbol

to
0.28

A

~

Propagation Delav Parameter
tup
tdn
KCL
to
KCL
KCL2 CDR2
0.16

Pin Name
X

0.09

0.12

4

Path
A ... X

X

Parameter

Pin Name
A

0.35

1

Symbol

Typ(ns)*

Input Loading
Factor (Rou)
1

Output Driving
Factor (Rou)
18

*

UHB-V1N-E1 I Sheet 1/1 I

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum de1av multiplier.

I Page

1-1

2-7

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power Inverter

V2B
Cell Svmbol

A

-{>o-

I

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.25
0.08
0.05
7
0.25
0.08

Pin Name

Input Loading
Factor (R.u)

A

2

Path
A'" X

Symbol

Typ(ns)*

Output Driving
Factor (R.u)
36

*

UHB-V2B-El I Sheet 1/1 I

2-8

1

X

Parameter

Pin Name
X

I UHB Version
I Number of BC

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page

1-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Inverting Clock Buffer

V1L
Cell Symbol

A

I UHB" Version
I Number of BC

I

Propagation Delay Parameter
tup
tdn
KCL2 CDR2
KCL
to
KCL
to
0.04
0.03
0.67
0.35

--{»-

2

Path
A ... X

X

Parameter

Pin Name
A

Input Loading
Factor (.tu)
4

Pin Name
X

Output Driving
Factor (.tu)
55

Symbol

Typ(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-VIL-E2 I Sheet 1/1 1

JPaJ!:e

1-3

2-9

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I True Buffer

BIN
Cell Symbol

Pro~aEation

tup
to
0.58

A

-+-

KCL
0.16

to
0.68

I UHB Version
I Number of BC

I

Delav Parameter
tdn
KCL
KCL2 CDR2
0.08

1
Path
A .. X

X

Parameter

Pin Name
A

Input Loading
Factor (lu)
1

Pin Name
X

Output Driving
Factor (.tu)
18

Symbol

Typ(ns)'"

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-BIN-El I Sheet 1/1 I

2-10

I Page

1-4

----'--

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Delay Cell

BD3
Ce11 Symbol

A

I

Pro;agation Delay Parameter
tup
tdn
to
KCLZ CDRZ
KCL
to
KCL
4
5.33
0.16
4.71
0.12
0.13

5
Path
A .. X

-[>---x
Parameter

Pin Name
A

Pin Name
X

I ORB Version
I Number of BC

Symbol

Typ(ns)*

Input Loading
Factor (lu)
1

Output Driving
Factor (.r.u)
18

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multit:llier.

UHB-BD3-El I Sheet 1/1 I

I Page

1 5

2-11

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Delay Cell

BD4
Cell Symbol

Pro~a2ation

tup
to
KCL
3.56
0.57

A

to
4.10

I "ORB Version
I Number of BC

I

Delay Parameter
tdn
KCL2 CDR2
KCL
4
0.36
0.31

4
Path
A-+X

--[>--x
Parameter

A

Input Loading
Factor (lu)
4

Pin Name
X

Output Driving
Factor (1u)
6

Pin Name

Symbol

Typ(ns)*

* Minimum values

for the typical operating condition.
The valuea for the worst case operating condition
are 2iven bv the maximum delav multiplier.

UHB-BD4-E2 I Sheet 1/1 I

2-12

I Page 1-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Delav Cell

BD5
Cell Symbol

I "UHB Version
I Number of BC

I

Proilal/;ation Delav Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
10.92
0.16 10.35
0.15
4
0.10

9

Path
A-+X

A -{>-X

Parameter

Pin Name
A

Pin Name
X

Svmbol

1'yp(ns) *

Input Loading
Factor (R.ul
1

Output Driving
Factor (R.u)
18

*

UHB-BD5 E1 I Sheet 1/1 I

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Page

l-i

2-13

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

J Delay Cell

BD6
Cell Svmbol

I UHB Version
I Number of BC

I

Pronaltation Delav Parame"t1!T
tun
tdn
to
KCL
to
KCL
KCL2 CDR2
0.14
22.00
0.17 21.82
0.09
4

17
Path
A-+X

A-{>-X

Parameter

Pin Name
A

Pin Name
X

Symbol

Typ(ns)*

Input Loading
Factor (Jtu)
1

Output Driving
Factor (Jtu)
18

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multinlier.

UHB-BD6-El I Sheet 1/1 I

2-14

I Page

1-8

CMOS Channeled Gate Arrays

UHB Series Unit Cell Ubraty

NAND Family

Page

Unit Cell
Name

2-17

N2N

2-18

N2B

Power 2-input NAND

3

2-19

N2K

Fast Power 2-input NAND

2

2-20

N3N

3-input NAND

2

2-21

N3B

Power 3-input NAND

3

2-22

N4N

4-input NAND

2

2-23

N4B

Power 4-input NAND

4

2-24

N6B

Power 6-input NAND

5

2-25

N8B

Power 8-input NAND

6

2-26

N9B

Power 9-input NAND

8

2-27

NCB

Power 12-input NAND

10

2-28

NGB

Power 16-input NAND

11

2-29

N3K

Fast Power 3-input NAND

3

2-30

N4K

Fast Power 4-input NAND

4

Function

Basic
Cells

2-input NAND

2-15

UHB Series Unit Cell Library

2-16

CMOS Channeled Gate AlTBYs

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 2-input NAND

N2N
Cell Symbol

A1
A2

=C?-

I "UHB" Version
I Number of BC

I

Propagation Delav Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.37
0.16
0.56
0.14

1
Path
A~X

X

Parameter

Pin Name
A

Input Loading
Factor (J1.u)
1

Pin Name
X

Output Driving
Factor (J1.u)
18

Symbol

Typ(ns)'"

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-N2N E2 I Sheet 1/1 I

I Page

2-1

2-17

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 2-input NAND

N2B
Cell Svmbol

Al
A2

"UHB" Version
I Number of BC

I

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
1.10
0.08
1.42
0.04

=C?-

3

Path
A->X

X

Parameter

Pin Name
A

Input Loading
Factor (.tu)
1

Pin Name
X

Output Driving
Factor J.tu)
36

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-N2B-E2 I Sheet 1/1 I

2-18

I Page 2-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 2-input NAND

N2K
Cell Svmbol

Al
A2

I

Prota2ation Delav Parameter
tu'P
tdn
to
KCL
to
KCL
KCL2 CDR2
0.08
0.43
0.07
0.09
7
0.37

:::if-

2

Path
A-+X

X

Parameter

Pin Name
A

Input Loading
Factor (R.u)
2

Pin Name

Output Driving
Factor (R.u)
36

X

I UHB Version
I Number of BC

Svmbol

Typ(ns)'"

,., Minimum values for the typical operatins condition.
The values for the worst case operatins condition
are given by the maximum delay multi'Plier.

UHB-N2K-E2 I Sheet: 1/1 I

I Page

2--.3..

2-18

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 3-input NAND

N3N
Cell Svmbol

A1
A2
A3

=0-

I "UHB" Version
I Number of BC

I

ProJ:agation Delay Parameter
tup
tdn
to
to
KCL2 CDR2
KCL
KCL
0.52
0.16
0.69
0.19

2
Path
A"X

X

Parameter

Pin Name
A

Input Loading
Factor (.tu)
1

Pin Name
X

Output Driving
Factor (.tu)
14

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-N3N-E2 I Sheet 1/1 I

2-20

I Page

2-4

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 3-input NAND

N3B
Cell Svmbol

Pro~agation

to
1.28

Al
A2
A3

=:j}-

tUJ)
KCL
0.08

to
1.70

Pin Name
X

I

Delav Parameter
tdn
KCL
KCL2 CDR2
0.04

3
Path
A'" X

X

Parameter

Pin Name
A

L "UHB" Version
I Number of BC

Symbol

Typ(ns)*

Input Loading
Factor (R.u}
1

Output Driving
Factor (R.u)
36

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are ltiven bv the maximum delay multiplier.

UHB-N3B-E2 I Sheet 1/1 I

Page

2-5

2-21

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name .1 Function

I 4-input NAND

N4N
Cell Symbol

A1
A2
A3
A4

ill-

I UHB Version
1Number of BC

I

ProllaJtation Delay Parameter
tup
tdn
to
to
KCL
KCL
KCL2 CDR2
0.62
0.16
0.74
0.24

2
Path
A-+X

X

Parameter

Pin Name
A

Input Loading
Factor (R.u)
1

Pin Name
X

Output Driving
Factor (R.u)
10

Symbol

Typ(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are Jtiven by the maximum delay multiplier.

UHB-N4N-E2 I Sheet: 111 I

2-22

I Page

2-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 4-input NAND

N4B
Cell Symbol

Al
A2
A3
A4

I

Propagation Delav Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
1. 38
0.08
1. 90
0.04

m-

Pin Name
X

4
Path
A--X

X

Parameter

Pin Name
A

I UHB Version
I Number of BC

Symbol

Typ(ns)~'

Input Loading
Factor (.tu)
1

Output Driving
Factor (iu)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-N4B-E2 I Sheet lllL

I Page 2-7
2-23

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

I Power 6-input NAND

N6B
Cell Symbol

Al
A2
A3
A4
AS

A6

Pin Name
X

Pro,agation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.07
1..37
0.08
2.02
0.04
7

ID-

Pin Name
A

I UHB Version
I Number of BC
5

Path
A ... X

X

Parameter

Symbol

Typ(ns)*

Input Loading
Factor (lu)
1

Output Driving
Factor (lu)
.36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
Al
A2
A.3
X

A4
AS
A6

UHB-N6B-E2 I Sheet 1/1 I

2-24

I Page 2-8

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
N8B
Ce 11 Symbol

Al
A2
A3
A4
AS
A6
A7
A8

I ORB Version
I Number of BC

I

Power 8-input NAND

ProJ:a.l1;ation Delav ParameJ:er
tun
tdn
to
KCL
to
KCL
KCL2 CDR2
1.44
0.08
2.21
0.04
0.07
7

6
Path
A->X

_r-,

:>-- X
-,./
Parameter

Pin Name
A

Input Loading
Factor (R.u)
1

Pin Name
X

Output Driving
Factor (R.lll
36

*

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are ~iven bv the maximum de1av multiplier.

Equivalent Circuit
Al _r-,
A2 A3 A4 -L../
AS _r-,
A6 A7 A8 -L../

UHB-N8B-E2 I Sheet 1/1 I

X

Page

2-9

2-25

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
N9B
Cell Svmbol

Power 9-input NAND
Pro~agation

tup
to
1.42

KCL
0.08

to
2.66

I "UHll Version
I Number of BC

I

Delay Parameter
tdn
KCL
KCL2 CDR2
0.05
0.09
7

8
Path
A -+ X

A1-f"'I
A2A3 A4 ::>-- X

AS -

A6
A7
A8
A9

-,../
Parameter

Pin Name
A

Input Loading
Factor (.tu)
1

Pin Name
X

Output Driving
Factor (.tu)
36

Svmbol

1YP(ns)*

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are R:iven by the maximum delay multiplier.

Equivalent Circuit
Al
A2
A3
A4
AS
A6

X

A7
A8
A9

UHB-N9B-E2 I Sheet 1/1 I

2-26

I Pue 2-10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

NCB

Power 12-input NAND

Cell Symbol

Pro~a~ation

tup
to
1.52
Al
A2
A3
A4
AS

KCL
O.OS

to
2.S6

I UHB Version
I Number of BC

I

Delav Parameter
tdn
KCL2 CDR2
KCL
0.05
0.09
S

10
Path
A-+X

_r"I

-

A6
:>-- X
A7
AS
A9
AIO All A12 - . . /

Pin Name
A

Pin Name
X

Parameter

Symbol

~(ns)*

Input Loading
Factor (R.u)
I

Output Driving
Factor (R.u)
36

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
Al _r"I
A2 PA3 A4 - L . /
AS
A6
A7
AS

_ ......
-../

X

A9 - ,
AI0- p-AllAl2-J

UHB-NCB-E2 I Sheet 1/1 I

I Fag"

2-11

2-27

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
NGB
Cell SYDlbol

Al
A2
A3
A4
AS

A6
A7
A8
A9
AlO
All
AI2
Al3
AI4
Als
Al6

Power I6-in.p_ut NAND

I UHB Version
1 Number of BC

I

Prota2ation Delav Parameter
tup
tdn
to
KCL
KCL2 CDR2
to
KCL
1.53
0.08
3.47
0.06
0.09
8

--'"""
--

--

11
Path
A-+X

0-- X

-

Parameter

Symbol

Typ' ns)'~

-l,../

Pin Name
A

Pin Name
X

Input Loading
Factor (iu)
1

Output Driving
Factor (iu)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are 2iven by the maximum delay multiplier.

Equivalent Circuit
Al -'"""
A2 pA3 A4 - . "
AS _r-A6 A7 ~r-A8 -l,../
I......( ~X
A
9-W
AlO"cL/
A11AI2-L/
AI3-r--.
Al4AlS- PAI6 -L/
UHB-NGB-E2 I Sheet 1/1 I

2-28

I Page

2-12

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 3-input NAND

N3K
Cell Symbol

Al
A2
A3

I UHB Version
I Number of BC

I

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.48
0.07
0.65
0.08

=v-

3
Path
A'" X

X

Parameter

Pin Name
A

Input Loading
Factor (R.u)
2

Pin Name
X

Output Driving
Factor (R.u)
28

Symbol

Typ(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are ~iven bv the maximum delay multiplier.

UHB-N3K-El I Sheet 1/1 I

I Page 2-13

2-29

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 4-input NAND

N4K
Cell Symbol

Pro~agation

tup
to
0.56

Al
A2
A3
A4

~

KCL
0.07

Pin Name
X

4
Path
A -+ X

Symbol

Typ(ns)*

Input Loading
Factor. (.tu)
2

Output Driving
Factor (.tu)
20

*

UHB-N4K-E1 I Sheet 1/1 I

2-30

I

Delay Parameter
tdn
KCL
KCL2 CDR2
0.10

X

Parameter

Pin Name
A

to
0.76

I "UHB" Version
I Number of BC

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page

2-14

CMOS Channeled Gate Amlys

UHB Series Unit Cell Ubrary

NOR Family
UnRCeIl

Page

Name

Function

Basic
Cells

2-33

R2N

2-inputNOR

1

2-34

R2B

Power 2-input NOR

3

2-35

R2K

Power 2-input NOR

2

2-36

R3N

3-inputNOR

2

2-37

R3B

Power 3-input NOR

3

2-38

R4N

4-inputNOR

2

2-39

R4B

Power 4-input NOR

4

2-40

R6B

Power 6-input NOR

5

2-41

RaB

Power a-input NOR

6

2-42

R9B

Power 9-input NOR

a

2-43

RCB

Power 12-input NOR

10

2-44

RGB

Power 16-input NOR

11

2-45

R3K

Power 3-input NOR

3

2-46

R4K

Power 4-input NOR

4

2-31

UHB $erios Unit CoI'Library

lflii

2-32

CMOS Ch9nnol9d Gate AlTBYs

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 2-input NOR

R2N
Ce 11 Svmbo 1

Al
A2

=t>--

I

Pro.agation Delav Parameter
tup
tdn
to
to
KCL
KCL
KCL2 CDR2
0.40
0.29
0.44
0.08
0.11
4

Pin Name
X

1
Path
A -+ X

X

Parameter

Pin Name
A

I "UHB" Version
I Number of BC

Symbol

Typ(ns)*

Input Loading
Factor _CR.u)
1

Output Driving
Factor (R.u)
14

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-R2N-E2 I Sheet 1/1 I

I Page

3-1

2-33

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 2-input NOR

R2B
Cell Svmbol

Al
A2

=t}-

I

3

Propagation Delay Parameter
tdn
t~p
to
KCL
to
KCL
KCL2 CDR2
0.04
1.36
0.08
1.25

Path
A"" X

Symbol

Typ(ns

X

Parameter

Pin Name

Input Loading
Factor (.eu)

A

1

Pin Name
X

I UHB Version
I Number of BC

»'r

Output Driving
Factor (.eu)
36

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-R2B-E2 I Sheet 1/1 I

2-34

-

I Page 3-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Func.ion

I Power 2-input NOR

R2K
Cell Symbol

Al
A2

=V-

I "UHB" Version
I Number of BC

I

Propagation Delay PaTatneteT
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.45
0.14
0.45
0.06

2
Path
A .. X

X

Parameter

Pin Name
A

Input Loading
Factor (.h)
2

Pin Name
X

Output Driving
Factor (!u)
36

*

UHB-R2K-E2 I Sheet 1/1 I

Symbol

Typ(ns)'~

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page 3-3

2-35

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 3-input NOR

R3N
Cell SYlIIbol

Al
A2
A3

=&-

I

Prollaltation Delav Parameter
tUl)
tdn
to
KCL
to
KCL
KCL2 CDR2
0.84
0.41
0.46
0.09
0.12
4

A

Pin Name
X

2
Path
A -+ X

X

Parameter

Pin Name

I UHB Version
I Number of BC

SYlIIbol

Typ(ns)*

Input Loading
Factor (R.u)
1

Output Driving
Factor (R.u)
10

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are Itiven bv the maximum delay multiplier.

UHB-R3N-E2 I Sheet 1/1 I

2-36

r Page

3-4

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 3-input NOR

R3B
Cell Symbol

Al
A2
A3

=&-

Pin Name
X

Version
I Number of BC

"UH]"

I

Propagation Delav Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
0.08
1.37
0.04
1. 99

3
Path
A-+X

X

Parameter

Pin Name
A

J

Symbol

Tvo(ns)*

Input Loading
Factor (.tu)
I

Output Driving
Factor (.tu)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are J;:iven by the maximum delay multiplier.

UHB-R3B-E2 I Sheet 1/1 I

I Page

3-5

2-37

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 4-input NOR

R4N
Cell Svmbol

A1
A2
A3
A4

~

I

Propagation Delav Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
1.24
0.54
0.46
0.09
0.13
4

Pin Name
X

Path
A ... X

Symbol

TD(ns)'"

Input Loading
Factor (.tu)
1

Output Driving
Factor (.tu)
6

*

UHB-R4N-E2 I Sheet: 1/1 I

2-38

2

X

Parameter

Pin Name
A

I "UHB" Version
I Number of BC

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multi!llier.

_.

I Page

3-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 4-input NOR

R4B
Cell Symbol

Al
A2
A3
A4

~

I UHB Version
I Number of BC

I

Propa2ation Delay Parameter
tup
tdn
to
to
KCL2 CDR2
KCL
KCL
0.08
0.04
2.50
1.34

4
Path
A'" X

X

Parameter

Pin Name
A

Input Loading
Factor (Rou)
1

Pin Name
X

Output Driving
Factor (Rou)
36

Symbol

Tvp(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are Kiven bv the maximum delay multiplier.

UHB-R4B-E2 I Sheet 1/1 I

rPage

3-;

2-39

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 6-input NOR

R6B
Cell Symbol

Al
A2
A3
A4
AS

A6

l-

Pin Name
A

Pin Name
X

I UHB Version
I Number of BC

I

Propagation Delav Parameter
tdn
t~
to
·KCL2 CDR2
KCL
to
KCL
2.25
0.08
1.48
0.04

5
Path
A-+X

X

Parameter

Symbol

Typ(ns)*

Input Loading
Factor (Lu)
1

Output Driving
Factor Clu)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
A1-n.
A2

A3-b!

X

A4-n.
A5'--I:!
A6

UHB-R6B-E2 I Sheet 1/1 I

2-40

I Page 3-8

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function
RBB
Cell Symbol

I UHB Version
I Number of BC

I

Power B-input NOR

Pro!,agation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
2.B4
O.OB
1.51
0.04

6
Path
A'" X

A1-~

,A2 1A3 A 4 - f-p.X
rA5 IA6 IA7 AB - t 7

Parameter

Pin Name
A

Input Loading
Factor (.tu)
1

Pin Name
X

Output Driving
Factor (.tu)
36

*

Symbol

TvP(ns)"

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
A1 _c::.
A2 - ,A3 - :A4 -t7
X

A5 _c::.
A6 - IA7 - IAB -t7

UHB-RBB-E2

Sheet 1/1 I

Page

3-9

2-41

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
R9B
Cell Svmbol

"UHB" Version
I Number of BC

I

Power 9-input NOR

Prollagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
2.49
1.68
0.04
0.08

-

8
Path
A .. X

Al -P>
rA2 fA3 A 4 - fX

AS

A6 A7 A8 A9 - ' : ; J

Parameter

Pin Name
A

Pin Name
X

Symbol

Typ(nsl*

Input Loading
Factor (R.u)
1

Output Driving
Factor (R.u)
36

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiplier.

Equivalent Circuit
Al
A2
A3

-A.
-b!

-n.
~-b!
-n.
-b!
A4

A7
A8
A9

~

r

UHB-R9B-E2 I Sheet 1/1 I

2-42

X

I Page

3-10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power l2-input NOR

RCB
Cell Symbol

Al
A2
A3
A4
AS

I "UHB" Version
I NllIDber of BC

I

Propagation Delay Parameter
tuP
tdn
to
KCL
to
KCL
KCL2 CDR2
2.74
0.08
0.04
1. 75

10
Path
A .... X

-~

-

-

.....
~

~
~

A6
I-p-X
~
A7
IA8 ~
A9 ~
AlO IAll A12 -I::;:>

Pin Name
A

Input Loading
Factor (.tu)
1

Pin Name
X

Output Driving
Factor (.tu)
36

Symbol

Parameter

*

TVtl (ns ) ,',

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximlllD delay multiplier.

Equivalent Circuit
Al
A2
A3
A4
AS
A6
A7
A8
A9

--n
-b!

--A.
-bJ

-n.
-bJ

I

L-.cP
X

l--(b4-

Al0---F\
All
A12-b!

UHB-RCB-E2

Sheet 1/1 I

I Page

3-11

2-43

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
RGB
Cell Svmbol

Power I6-input NOR
tun

-p.

Al
A2
A3
A4
AS

A6
A7
A8
A9
AIO
All
AI2
Al3
Al4
AIS
Al6

--

KCL
0.08

I

Delav Parameter
tc1n
to
KCL
KCL2 CDR2
0.04
1.82

Pro~a2ation

to
3.43

I UHB Version
I Number of BC
11

Path
A -+ X

ffffff-

'-0-- X
,-

frrffr-t::;:>

Parameter

Pin Name
A

Input Loading
Factor (R.u)
1

Pin Name
X

Output Driving
Factor (R.u)
36

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
Al -I==:>

-i-

A2
A3 - t A4 -t::;

AS -::::,
A6 - A7
A8 -::;0

--f1

-1,J

A9
AIO-All-AI2-::::::

-c~

-ct::;{---t»-

X

A13-p

A14~
AIS
A16
UHB-RGB-E2 I Sheet 1/1 I

2-44

I Page 3-12

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 3-input NOR

R3K
Cell Symbol

Al
A2
A3

=t1-

I UHB Version
I Number of BC

I

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.66
0.17
0.32
0.04
0.07
7

3
Path
A .. X

X

Parameter

Pin Name
A

Input Loading
Factor (lu)
2

Pin Name
X

Output Driving
Factor (lut
20

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-R3K-El I Sheet 1/1

I Page

3-13

2-45

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 4-input NOR

R4K
Cell Symbol

Pro~agation

tup
to
1.08

Al
A2
A3
A4

~

KCL
0.23

to
0.35

I UHB Version
I Number of BC

I

Delay Parameter
tdn
KCL2 CDR2
KCL
0.03
0.05
7

4
Path
A->X

X

Parameter

Pin Name
A

Input Loading
Factor (.tu)
2

Pin Name
X

Output Driving
Factor (.tu)
12

Symbol

1"yp(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-R4K-El I Sheet 1/1 I

2-46

I Page

3-14

UHB Series Unit Cell UbraIY

CMOS Channeled Gate Amlys

AND Family
Basic

UnH Cell

Page

Name

2-49

N2P

Power 2-input AND

2

2-50

N3P

Power 3-input AND

3

2-51

N4P

Power 4-input AND

3

2-52

N8P

Power 8-input AND

6

Function

Cells

2-47

UHB Seri9$ Unit Ce/lLibraIy

2-48

CMOS Channeled Gate AmI)'s

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 2-input

N2P
Cell Symbol

Al
A2

=D-

L UHB Version

I Number of BC

I

AND

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
1. 01
0.08
0.86
0.04
0.06
7

2
Path
A ... X

X

Parameter

Pin Name
A

Input Loading
Factor (R.u)
1

Pin Name
X

Output Driving
Factor (R.u)
36

*

UHB-N2P-E21 Sheet 1/1

J

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page 4-1

2-49

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Funcdon

I Power 3-input

N3P
Cell Svmbol

A1
A2
A3

=v-

UHB" Version
I Number of Be

I

AND

Prooagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
1.32
0.08
1.07
0.04
0.06
7

3
Path
A .. X

X

Parameter

Pin Name
A

Input Loading
Factor (Jlu)
1

Pin Name
X

Output Driving
Factor (Jlu)
36

Symbol

TYPJns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-N3P-E2 I Sheet 1/11

2-50

Page

4-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 4-input

N4P
Cell Symbol

A1
A2
A3
A4

~

UHB" Version
I Number of BC

I

AND

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.08
0.04
0.06
8
1.58
1.19

3
Path
A .. X

X

Parameter

Pin Name
A

Input Loading
Factor _LR.u)
1

Pin Name
X

Output Driving
Factor (R.u)
36

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are g;iven by the maximum delay multiplier.

UHB N4P-E2 I Sheet 1/1 I

I Page 4-3
2-51

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
NSP
Cell Symbol

I "UHB Version
I Number of BC

I

Power S-input AND

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.04
0.06
1.72
0.14
1.45
S

Al _ r " I
A2 A3 A4AS -

6
Path
A .. X

t--- X

A6 A7 AS - L . , /
Parameter

Pin Name
A

Input Loading
Factor (iu)
1

Pin Name
X

Output Driving
Factor (iu)
36

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
Al -'"'"
A2 A3 A4 - , . - I
X
AS -'"'"
A6 A7 AS - , . - I

UHB-N8P-E2

2-52

Sheet 1/1 I

I Page

4-4

CMOS ChannslBd Gats .4mrys

UHB Series Unit Cell Ubrarr

OR Family
Basic

Unit Cell

Page

Name

2-55

R2P

Power 2-input OR

2

2-56

R3P

Power 3-input OR

2-57

R4P

Power 4-input OR

3
3

2-58

R8P

Power 8-input OR

6

Function

Cells

2-53

UHB Series Unit Cell Librsty

2-54

CMOS ChanneI8d Gate Arrays

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 2-input OR

R2P
Cell Symbol

Al
A2

=tJ-

I

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.78
0.08
1.14
0.05
0.07
8

Pin Name
X

2
Path
A -+ X

X

Parameter

Pin Name
A

I "UHB Version
I Number of BC

Symbol

Typ(ns)~'

Input Loading
Factor (Rou)
1

Output Driving
Factor (Rou)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-R2P-E2 I Sheet 1/1 I

I Page 5-1

2-55

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 3-input OR

R3P
Ce 11 Symbo 1

A1
A2
A3

=&-

I

Prollagation Delay Parameter
tup
tdn
to
KCL2 CDR2
KCL
to
KCL
0.90
0.08
1.84
0.06
0.08
8

Pin Name
X

3
Path
A -+ X

X

Parameter

Pin Name
A

I UHB Version
I Number of BC

Symbol

Typ(ns)~'

Input Loading
Factor (Rou)
1

Output Driving
Factor _CRou)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-R3P-E2 I Sheet 1/1 I

2-56

I Page 5-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 4-input OR

R4P
Cell Symbol

Al
A2
A3
A4

~

I

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.10
0.90
0.08
2.52
0.07
8

Pin Name
X

3
Path
A -+ X

X

Parameter

Pin Name
A

I "UHB Version
I Number of BC -

Symbol

Typ(ns);'

Input Loading
Factor (iu)
I

Output Driving
Factor (iu)
36

*

UHB-R4P-E2 I Sheet 1/1 I

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Page

5-3

2-57

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
R8P
Cell Symbol

I ORB Version
I Number of BC

I

Power 8-input OR

Prolla.v;ation Delav Parameter
tu'O
tdn
to
to
KCL
KCL
KCL2 CDR2
0.98
0.08
2.68
0.08
0.10
8

6
Path
A-+X

A1-=::'
A2 - , A3 - A4 - r--- X
AS -

i-

A6 - i IA7 A8 -t::;7
Parameter

Pin Name
A

Pin Name
X

Symbol

Typ(ns)*

Input Loading
Factor (.tu)
1

Output Driving
Factor (.tu)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are .v;iven by the maximum delay multiplier.

Equivalent Circuit
Al - p
A2 - IA3 - IA4 - b
AS -=::.
A6 - A7 - A8 -:::;;

UHB-R8P-El I Sheet 1/1 I

2-58

X

I Page

5-4

CMOS Chsflllflled Gate Amlys

UHB Series Unit Cell Ubra7

EXNOR/EXOR Family
Basic
Cells

Page

Un" Cell
Name

2-91

X1N

Exclusive NOR

2-92

X1B

Power Exclusive NOR

4

2-63

X2N

Exclusive OR

3

2-94

X2B

Power Exclusive OR

4

2-95

X3N

3-input Exclusive NOR

5

2-96

X3B

Power 3-input Exclusive NOR

6

2-97

X4N

3-input Exclusive OR

5

2-68

X4B

Power 3-input Exclusive OR

6

Function

3

2-59

UHB Series Unit CsII Ubraty

2-60

CMOS Channeled Gale Anays

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

I Exclusive NOR

XIN
Cell Symbol

Pro~agation

tup
to
1.16

Al
A2

=ID>-

KCL
0.29

Pin Name
X

I

Delay Parameter
tdn
KCL
KCL2 CDR2
0.13
4
0.16

3
Path
A'" X

X

Parameter

Pin Name
A

to
0.96

J UHB . Version
I Number of BC

Symbol

Typ(ns)*

Input Loading
Factor (1u)
2

Output Driving
Factor (R.u)
18

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
Al
A2

~

I

UHB-X1N-E2 I Sheet 1/1 I

cV-X

I Page

6-1

2-61

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power Exclusive NOR

XIB
Cell Svmbol

Prona~ation

tun
to
1.49

Al
A2

KCL
0.08

to
1.77

I "UHB" Version
I Number of BC

I

Delay Parameter
tdn
KCL
KCL2 CDR2
0.05
0.09
7

4

Path
A ... X

=W- x
Parameter

Pin Name
A

Input Loading
Factor (.tu)
2

Pin Name

Output Driving
Factor (.tu)

X

Svmbol

Typ(ns)*

36

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
Al
A2

=re

I

ORB XIB-E2 LSheet 1/1 I

2-62

tr»-x

I Pag;e 6-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Exclusive OR

X2N
Cell Svmbol

Al
A2

=ID-

I "UHB" Version
I Number of BC

I

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.29
1.17
0.13
0.16
4
1.11

3
Path
A ... X

X

Symbol

Parameter

Pin Name
A

Input Loading
Factor (lu)
2

Pin Name
X

Output Driving
Factor (lu)
14

Typ(ns)~'

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
A1
A2

~ L=-cV-

UHB-X2N-E2 I Sheet 1/1 I

X

I Page 6-3

2-63

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power Exclusive OR

X2B
Cell Symbol

Al
A2

I

Proj:agation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.07
1.43
0.08
1.64
0.05
7

=©-

Pin Name
X

4

Path
A-+X

X

Symbol

Parameter

Pin Name
A

I ORB" Version
I Number of BC

Typ(ns)~'

Input Loading
Factor (R.u)
2

Output Driving
Factor (R.u)
36

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

EqUivalent Circuit
Al
A2

=re

I

UHB-X2B-E2 I She.et 1/1 I

2-64

cV--V-

X

I Page

6-4

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 3-input Exclusive NOR

X3N
Cell Symbol

Al
A2
A3

I Number of BC

j

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
2.72
0.29
2.32
0.13
0.16
4

=9-

5

Path
A ... X

X

Parameter

Pin Name
A

Input Loading
Factor (R.u)
2

Pin Name

Output Driving
Factor (R.u)

X

1 "UHB Version

Symbol

Typ(ns)'"

18

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
A2
A3
Al

~

UHB-X3N-E2 I Sheet 1/1 I

X

_.

Page

6-5

2-65

I "UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 3-input Exclusive NORPropagation Delay Parameter I

X3B
Cell Svmbol

tup
to
2.64

Al
A2
A3

=w-

KCL
0.08

Pin Name
X

tdn
KCL
KCL2
0.05
0.09

CDR2
7

Path
A-+X

X

Parameter

Pin Name
A

to
3.39

6

Svmbol

Typ(ns)*

Input Loading
Factor (Rou)
2

Output Driving
Factor (Rou)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are ltiven by the maximum delay multiplier.

Equivalent Circuit
A2
A3
Al

~

UHB-X3B-E2 I Sheet 1/1 I

2-66

X

r Page

6-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name 'Function

I 3-input Exclusive OR

X4N
Cell Svmbol

Al
A2
A3

Version
, Number of BC

'''UHB

I

Propagation Delay Parameter
tup
tdn
to
to
KCL
KCL
KCL2 CDR2
4
2.82
0.29
2.53
0.13
0.16

5
Path
A'" X

=ID-x
Parameter

Pin Name
A

Input Loading
Factor (Lu)
2

Pin Name
X

Output Driving
Factor (Lu)
14

*

Svmbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
A2
AS
Al

~

UHB-X4N-E2 , Sheet 1/1 ,

X

Page

6-7

2-67

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I Power 3-inDut Exclusive ORProj:ag_ation Delay Parameter I

X4B
Cell Svmbol

to
2.4;

Al
A2
A3

=W-

tUD
Jct
0.08

to
3.13

tdn
KCt
KCt2
0.07
0.05

CDR2
7

6
Path
A .. X

x
Parameter

Pin Name
A

Input Loading
Factor (.tu)
2

Pin Name
X

Output Driving
Factor (lu)
36

Symbol

Typ(ns)*

* Minimum

valuea for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay lIul ti Dlier •

Equivalent Circuit

A2~

A3
A1

UHB-X4B-E2

2-68

Sheet 1/1 I

X

I Page

6-8

UHB Selie. Unit Cell Library

AND-OR-Inverter Family (AOt)
Unit Cell
Page

Name

Function

BasIC
Cells

2-71

023

2 AND Into 2 NOR AOI

2

2-72

014

3 AND Into 2 NOR AOI

2-73

024

2, 2 ANDS Into 2 NOR AOI

2
2

2-74
2-75

D34
D36

2 AND Into 3 NOR AOI

2

3, 2 ANDS Into 3 NOR AOI

3

2-76

D44

2 OR into 2 AND inot 2 NOR AOl2

2-69

CMOS ChannrIIed Gate Am.

2..70

"UHB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 2-wide 2-AND 3-input AOI ProJ:agation Delay Parameter I

D23
Cell Svmbol

tup
to
0.73
0.37

Al
A2
B

~

KCL
0.29
0.22

to
0.68
0.37

tdn
KCL
KCL2
0.14
0.09
0.12

CDR2

2
Path
A~X

4

B

~

X

X

Parameter

Pin Name
A
B

Input Loading
Factor (J1.u)
1
1

Pin Name
X

Output Driving
Factor (J1.u)
14

Symbol

Typ(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-D23-El I Sheet lLll

I Page

7-1

2-71

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I tJ1iB Version
J Number of BC

I 2-wide 3-AND 4-input AOI Pro;agation Delav Parameter I

D14
Cell Svmbol

tup
to
0.90
0.32

Al
A2
A3
B

~

KCL
0.29
0.20

Pin Name
X

tdn
KCL
KCL2
0.19
0.21
0.09
0.12

CDR2
4
4

Path
A ... X
B ... X

X

Parameter

Pin Name
A
B

to
0.70
0.36

2

Symbol

Typ(ns)*

Input Loading
Factor (tu)
1
1

Output Driving
Factor (tu)
14

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are lI:iven by the maximum delay multiplier.

UHB-DI4-El I Sheet 1/1 I

2-72

I Page

7-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I 2-wide 2-AND 4-input AO! Pro"J:agation DellaL Parameter I

D24
Cell Svmbol

tUt)
to
0.54
0.67

Al
A2
B1
B2

~

KCL
0.22
0.22

Pin Name
X

tdn
KCL
KCL2
0.14
0.14

CDR2

Path
A--X
B ... X

X

Parameter

Pin Name
A
B

to
0.62
0.83

2

Symbol

Typ(ns)*

Input Loading
Factor (iLu)
1
1

Output Driving
Factor (iLu)
14

*

UHB-D24-E2 I Sheet 1/1 I

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page 7-3
2-73

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB" Version
I Number of BC

I 3-wide 2-AND 4-input AD! Protal!;ation Delav Parameter I

D34
Cell Svmbol

tup
to
1.15
0.62

Al
A2
B1
B2

~

KCL
0.41
0.35

Pin Name
X

CDR2
4

Path
A .. X
B .. X

Symbol

Typ(ns)*

Input Loading
Factor (J1.u)
1
1

Output Driving
Factor (J1.u)
10

*

UHB-D34-E2 I Sheet 1/1 I

2-74

tdn
KCL
KCL2
0.15
0.09
0.12

X

Parameter

Pin Name
A
B

to
0.73
0.43

2

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page

7-4

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I "UMB Version
I Number of BC

I 3-wide 2-AND 6-input AOI Pro a2ation Delav Parameter I

D36
Cell Svmbol

tUl)
to
0.77
0.98
1.17

KCL
0.28
0.28
0.28

to
0.72
0.87
1.02

tdn
KCL
KCL2
0.14
0.14
0.14

CDR2

3
Path
A -+ X
B-+X
C-+X

Al
A2
B1
B2

X

C1
C2
Parameter

Pin Name
A
B
C

Pin Name
X

Svmbol

Typ(ns)*

Input Loading
Factor (tu)
1
1
1
Output Driving
Factor (.f.u)
10

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are 2iven by the maximum delay multiplier.

UHB-D36-E1 I Sheet 1/1 I

I Page

7-5

2-75

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

AOI
I 2-wide 2-0R 2-AND 4-in1:lutProllagation
I
Delay Parameter

D44
Cell Svmbol

tup
to
KCL
1.04 0.41
1.03 0.41
0.99
0.29

A1
A2
B

C

to
0.78
0.64
0.48

tdn
KCL
KCL2
0.14
0.14
0.09
0.11

CDR2
4

2
Path
A"X
B" X
C .. X

~,
Parameter

Pin Name
A
B
C

Input Loading
Factor (Iu)
1
1
1

Pin Name
X

Output Driving
Factor (lu)
10

Symbol

Ty1J(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-D44-E1J Sheet 1/1 I

2-76

r Page

7-6

CMOS Channeled Gale Arrays

UHB Series Unil Cell Ubta/l

OR-AND-Inverter Family (OAI)
UnItCel!

Basic
Cells

Page

Name

2-79

G23

2 OR Into 2 NAND OAi

2

2-60

G14

3 OR into 2 NAND OAI

2

2-61

G24

2, 2 OR into 2 NAND OAI

2

2-62

G34

2 OR Into 3 NAND OAI

2-63

G44

2 AND into 2 OR into 2 NAND OAI

2
2

Function

2-77

UHB Series Unit Ce/l1.!I1r!y

2-78

CMOS ChaMeIsd Galli Ami)'!

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 2-wide 2-0R 3-input OAI

G23
Cell Symbol

Al
A2
B

I

I
I

2
Path
A" X
B .. X

X

Parameter

Pin Name
X

L Number of BC

Propagation Delay Parameter
tup
tdn
KCL
to
to
KCL
KCL2 CDR2
0.14
0.72
0.29
0.55
0.16
0.14
0.28
0.55

~

Pin Name
A
B

I UHB Version

Symbol

Typ(ns)'"

Input Loading
Factor (.eu)
1
1

Output Driving
Factor (.eu)
18

*

UHB-G23 E1 j Sheet 1/1 I

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Page

8-1

2-79

FUJITSU CMOS GATE ARRAY
Cell Name I Function

u~ITCELL

SPECIFICATION

I 2-wide 3-0R 4-input OAl

G14
Cell Symbol

Al
A2
A3
B

2
Path
A -+ X
B -+ X

X

Parameter

Pin Name
X

I

Pro]:agation Delay Parameter
tuo
tdn
to
KCL
to
KCL
KCL2 CDR2
1.20
0.42
0.65
0.14
0.25
0.16
0.65
0.14

~

Pin Name
A
B

I "UHB" Version
I Number of BC

Symbol

Typ(ns)*

Input Loading
Factor (R.u)
1
1

Output Driving
Factor (R.u)
10
* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-G14-E1 I Sheet 1/1 I

2-80

I Page

8-2

FUJITSU CMOS GATE ARRAY
Cell Name I Function

u~IT

CELL SPECIFICATION

I 2-wide 2-0R 4-input OAI

G24
Cell Symbol

A1
A2
B1
B2

I "UHB Version
I Number of BC

I

Pro al1:ation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.50
0.14
0.29
0.70
0.90
0.29
0.14
0.60

~

Path
A-+X
B -+ X

X

Parameter

Pin Name
A
B

Input Loading
Factor (R.ut
1
1

Pin Name
X

Output Driving
Factor (R.u)
10

*

UHB-G24-E2 I Sheet 1/1 I

2

Symbol

Typ(ns)~'

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page

8-3

2-81

FUJITSU CMOS GATE ARRAY
Cell Name I Function

u~IT

CELL SPECIFICATION

I 3-wide 2-0R 4-input OAI

G34
Cell Svmbol

Al
A2
Bl
B2

I

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.95
0.29
0.70
0.19
0.70
0.19
0.45
0.16

~

Pin Name
A
B

Input Loading
Factor (Lul
1
1

Pin Name
X

Output Driving
Factor (Lu)
10

*

UHB-G34-E2 I Sheet 1/1\

2
Path
A-+X
B -+ X

X

Parameter

2-82

I "UMB" Version
I Number of BC

Symbol

Typ{ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

r Page

8-4

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I IJHB Version
I Number of BC

OAI
I 2-wide 2-AND 2-0R 4-inputProllaJ1;ation
I
Delav Parameter

G44
Cell Svmbol

tup
to
0.73
0.43
0.50

Al
A2
B
C

KCL
0.29
0.29
0.16

to
0.86
0.62
0.52

tdn
KCL
KCL2
0.19
0.19
0.14

CDR2

2

Path
A"X
B .. X
C .. X

~x
Parameter

Pin Name
A
B
C

Pin Name
X

Symbol

Typ(ns)>"

Input Loading
Factor (lu)
1
1
1

Output Driving
Factor (1u)
14

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are J1;iven bv the maximum delav multiplier.

UHB-G44-El I Sheet 1/1 I

I Page

8-5

2-83

2-84

CMOS Channeled Gate Arrays

UHB Series Unit Cell Ubrary

Multiplexer Family

Page

Un" Cell
Name

2--87

T24

2--88
2--89

Function

Basic
Cells

4:1 Power 4, 2 ANDs into 4 NOR Multiplexer

6

T26

6:1 Power 6, 2 ANDs into 6 NOR Multiplexer

10

T28

8:1 Power 8, 2 ANDs into 8 NOR Multiplexer

11

2-91

T32

2:1 Power 2, 3 ANDs into 2 NOR Multiplexer

5

2-92

T33

3:1 Power 3, 3 ANDs into 3 NOR Multiplexer

7

2-93

T34

4:1 Power 4, 3 AND into 4 NOR Multiplexer

9

2-94

T42

2:1 Power 2, 4 ANDs into 2 NOR Multiplexer

6

2-95

T43

3:1 Power 3, 4 ANDs into 3 NOR Multiplexer

10

2-96

T44

4:1 Power 4, 4 ANDs into 4 NOR Multiplexer

11

2-97

T54

4:1 Power 2, 2-3-4 ANDs into 4 NOR Multiplexer

10

2-98

U24

4:1 Power 4, 2 OR into 4 NAND Multiplexer

6

2-99

U26

6:1 Power 6, 2 OR into 6 NAND Multiplexer

9
11

2-100

U28

8:1 Power 8, 2 OR into 8 NAND Multiplexer

2-101

U32

2:1 Power 2, 3 OR into 2 NAND Multiplexer

5

2-102

U33

3:1 Power 3, 3 OR into 3 NAND Multiplexer

7

2-103

U34

4:1 Power 4, 3 OR into 4 NAND Multiplexer

9

2-104

U42

2:1 Power 2, 4 OR into 4 NAND Multiplexer

6

2-105

U43

3:1 Power 3, 4 OR into 3 NAND Multiplexer

9

2-106

U44

4:1 Power 4, 4 OR into 4 NAND Multiplexer

11

2-85

UHB Series Unit Cell Library

2-86

CMOS Channeled Gate AtTSYs

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I Power 2-AND 4-wide Multiplexer
I
Propagation Delay Parameter

T24
Cell Svmbol

tup
to
1.62
1.80
1.58
1.72

Al
A2
BI
B2
CI
C2

KCL
0.08
0.08
0.08
0.08

to
1.52
1. 76
1.64
1.88

tdn
KCL
KCL2
0.04
0.04
0.04
0.04

CDR2

6
Path
A-+X
B -+X
C -+ X
D -+X

~~

=:::(Yr =t;::;

X

DI
D2

Pin Name
A
B
C
D
Pin Name
X

Parameter

Symbol

Typ(ns)*

Input Loading
Factor (iu)
I
I
I
I
Output Driving
Factor (iu)
36

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
Equivalent Circuit

!~ =CD1

=C
g =Ct)J
=C
BI
B2

-"'"

J

X

"L/

DI
D2

UHB-T24-E1 I Sheet 1/1 I

Page

9-1

2-87

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function
T26
Cell Svmbol

Version
Number of BC

Power 2-AND 6-wide Multi

10

Dela
to

KCL

to

Parameter
tdn
KCL
KCL2 CDR2

1.88
2.07
1.88
2.04
1.90
2.06

0.08
0.08
0.08
0.08
0.08
0.08

1.57
1.81
1.66
1. 92
1.84
2.08

0.04
0.04
0.04
0.04
0.04
0.04

tup

Al
A2

B1
B2
CI
C2

Path
A'" X
B ... X
C ... X
D'" X
E ... X

F"'X

x

Dl
D2
EI
E2

Parameter

(ns)'"

F1

F2

Pin·· Name
A
B
C
D

Input Loading
Factor (Jl.u)
1

1
1
I

F

1
1

Pin Name

Output Driving
Factor (Jl.u

E

X

36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are iven b the maximum dela multi lier.

Equivalent Circuit
Al
A2

B1
B2
CI
C2

x

Dl
D2
EI
E2
Fl

F2
UHB-T26-EI

2-88

Pa e

9-2

I UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 2-AND 8-wide Multiplexer
I
Prooagation Delay Paramet:er

T28
Cell Svmbol

tuo
t:0
2.12
2.32
2.12
2.28
2.20
2.36
2.20
2.36

KCL
0.08
0.08
0.08
0.08
0.08
0.08
0.08
0.08

Parameter

Pin Name

tdn
KCL
KCL2
0.04
0.04
0.04

CDR2

0.04

0.04
0.04

0.04
0.04

Svmbo1

Path
A ... X
B ... X
C ... X
D ... X
E ... X
F ... X
G ... X
H ... X

Typ(ns)'"

Input Loading
Factor (.eu)

A
B

1

C
D

1

E

F

1
1

G
H

1

Pin Name
X

to
1.52
1. 80
1. 68
1. 96
2.16
2.08
1.92
2.18

11

1
1

1

Output Driving
Factor (.eu)
36
,~

UHB-T28-El I Sheet 1/2 I

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Page

9-3

2-89

FUJITSU

C~OS

GATE ARRAY UNIT CELL SPECIFICATION

Cell Name
T28

UHB

Version

Equivalent Circuit

Al
A2

Bl
B2
Cl
C2

Dl
D2

El
E2

x

F1
F2

Gl
G2

HI
H2

UHB-T28-El

2-90

Pa e 9-4

I UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 3-AND 2-wide Multiplexer
I
Pro,:agation Delay Parameter

T32
Cell Svmbol

tup
to
1.52
1.52

KCL
0.08
0.08

to
1. 68
1. 80

tdn
KCL
KCL2
0.04
0.04

CDR2

5
Path
A'" X
B ... X

Al
A2
A3
X

BI
B2
B3
Parameter

Pin Name
A
B

Pin Name
X

Svmbol

Typ(ns l'~

Input Loading
Factor (iuJ
1
1

Output Driving
Factor (iu)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiplier.

Equivalent Circuit
A1
A2
A3
B1
B2
B3

~

::J

X

'1../

UHB-T32-E1 I Sheet 1/1 I

I Page

9-5

2-91

FUJITSU CMOS GATE ARRAY UNIT CELl SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I Power 3-AND 3-wide Multiplexer
I
Propaltation Delay_ Parameter

T33
Cell Symbol

tup
to
1. 75
1. 75
1. 75

KCL
0.08
0.08
0.08

to
1.66
1. 78
1.95

tdn
KCL
KCL2
0.04
0.04
0.04

CDR2

7
Path
A ... X
B ... X
C ... X

A1
A2
A3
B1
B2
B3

X

C1
C2
C3

Pin Name
A
B
C

Pin Name
X

Parameter

TvP(ns)*

Input Loading
Factor (R.u)
1
1

1
Output Driving
Factor (R.u)
36

*

UHB-T33-E1 I Sheet 1/1 I

2-92

Svmbol

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page 9-6

I "UHB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 3-AND 4-wide Multiplexer
I
ProJ:agation Delay Parameter

T34
Cell Symbol

tup
to
2.08
2.08
2.18
2.18

A2 l = D A
A3

KCL
0.08
0.08
0.08
0.08

to
1.72
1.88
2.00
2.01

tdn
KCL
KCL2
0.04
0.04
0.04
0.04

CDR2

9

Path
A" X
B .. X
C .. X
D" X

B1~ :::,

B2
B3
C1
C2
C3

=Vr

P
- -

X

:::;:>

Parameter

D1
D2 = D D3

Pin Name
A
B
C
D

Input Loading
Factor (R.u)
1
1
1
1

Pin Name
X

Output Driving
Factor (R.u)
36

Symbol

Typ(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are ltiven by the maximum delay multiplier.
Equivalent Circuit
A1
A2
A3
B1
B2
B3
Cl
C2
C3

~1-v-

X

,c::7

Dl
D2
D3

UHB-T34-El I Sheet 1/1 I

Page

9-7

2-93

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
T42
Cell Symbol

I "UHB Version
I Number of BC

I

Power 4-AND 2-wide Multiplexer
Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
1.60
0.08
1.88
0.04
0.08
2.00
0.04
1.60

6
Path
A ... X
B ... X

Al-"""
A2 A3 A4 - . . /
X
Bl
B2
B3
B4

-"""
-../
Parameter

Symbol

TYPinsL*

Input Loading
Factor (.h)

Pin Name
A
B

1
1

Output Driving
Factor (iu)
36

Pin Name
X

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
A1
A2
A3
A4

h

-"""
--,../

-1-J

.........
:J-....,

X

B1
B2 B3 B4 -,../

UHB-T42-El I Sheet 1/1 I

2-94

I Page 9-8

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
T43
Cell Svmbol

Power 4-AND 3-wide Multiplexer
Pro~agation

tup
to
1.88
1.88
1.88

Al _r-A2 ~
A3 I
A4 - l . /
B l - .......
B2 1
B3 B4 -,.../

Lf\

to
1. 92
2.04
2.20

I

Delay Parameter
tdn
KCL
KCL2 CDR2
0.04
0.04
0.04

10
Path
A -+ X
B -+ X
C -+ X

X

I -b!

Cl _

KCL
0.08
0.08
0.08

I UHB Version
I Number of BC

.......

C2 }C3 C4 -,.../

Parameter

Svmbol

Typ(ns)*

Input Loading
Factor (Rou)

Pin Name
A
B
C

1

1
1

Output Driving
Factor (Rou)
36

Pin Name
X

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delav multiplier.

Equivalent Circuit
Al
A2
A3
A4

_r--

P-

-V

Bl _r-B2 B3 B4 - l . /

l;fj

rCbl

X

Cl _r-C2 p-C3 C4 - l . /

UHB-T43-El

Sheet 1/1 I

Page

9-9

2-95

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

T44
Cell Symbol
A1
A2
A3
A4

I UHB Version
I Number of BC

Power 4-AND 4-wide Multiplexer
Pro}:agation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
_f'
2.16
0.08
1.92
0.04
2.16
0.08
1.64
0.04
t2.16
0.08
2.20
0.04
-L/
2.16
0.08
2.32
0.04

B1 _ f '
B2 B3- ~~
B4 - L /

Symbol

Parameter

J:r-

11

Path
A-+X
B -+ X
C -+ X
D -+ X

Typ(ns)*

X

C
C2 1
- - Y r7
C3 C4 - l . . /
D1 _ f '

t

D2 D3 D4 - l . . /
Pin Name
A
B
C
D

Input Loading
Factor (R.u)
1
1
1
1

Pin Name
X

Output Driving
Factor (R.u)
36

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are J?;iven by the maximum delay multiplier.

Equivalent Circuit
A1 _ f '
A2 A3 A4 - L /
B1 _ f '

h

B2 B3 B4 - l . . /

,---<:::::'

-1-J ,--c::::;;}--{>o----

X

C1
C2 C3 C4 - L /
D1
D2
D3
D4

-""'"
-../

UHB-T44-E2 J

2-96

Sh,~et

1/1

I Page 9-10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
T54
Cell Symbol

Power 4-2-3-2 AND 4-wide Multiplexer
Pro~agation

tup
Al
A2
A3
A4

to
2.06
1.92
2.06
1. 92

_r'\

-

t--

KCL
0.08
0.08
0.08
0.08

to
1. 96
1.64
2.06
1. 88

I "UHB" Version
I Number of BC

I

Delay Parameter
tdn
KCL
KCL2 CDR2
0.04
0.04
0.04
0.04

10

Path
A ... X
B ... X
C ... X
D ... X

-L./

B1~ P
~X

B2
C1
C2
C3

=ifr

D1
D2

==D-

Pin Name
A
B
C
D
Pin Name
X

t7
Symbol

Parameter

Typ(ns)*

Input Loading
Factor (iu)
1

1
1
1

Output Driving
Factor (iu)
36
,~

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
Al _r'\
A2 A3 A4 - J
B1
B2
C1
C2
C3

L--(:::::'

,-c)-Vo-

X

Dl
D2

UHB-T54-E2

I Sheet 1/1 I

I Page 9-11

2-97

FUJITSU CMOS GATE ARRAY UNIT CELL
Cell Name I Function

I "UHB" Version
I Number of BC

SPECIFICATIO~

I Power 2-0R 4-wide Multiplexer
I
Propagation Delay Parameter

U24
Cell Symbol

tup
to
KCL
0.08
2.00
1.44
0.08
0.08
1.90
1.38
0.08

Al
A2
BI
B2
Cl
C2

to
1. 80
1. 75
1. 78
1. 70

tdn
KCL
0.05
0.05
0.05
0.05

KCL2
0.08
0.08
0.08
0.08

CDR2
7
7
7
7

6
Path
A'" X
B ... X
C ... X
D ... X

~r'\P-X
=lfrv

D1

D2

Parameter

Pin Name
A
B
C
D

Input Loading
Factor (R.u)
I
I
I
I

Pin Name
X

Output Driving
Factor (R.u)
36

*

UHB-U24-El I Sheet 1/1 I

2-98

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are_given by the maximum delay multiplier.

I Page

9-12

I "UHB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 2-0R 6-wide Multiplexer
I
Propagation Delay Parameter

U26
Cell Svmbol
Al
A2

tup
to
KCL
2.00
0.08
0.08
1.55
2.04
0.08
1.58
0.08
1.64
0.08
0.08
2.10

=4}-

Bl
B2

""
Cl~
C2
Dl~
D2

tdn
KCL
0.05
0.05
0.05
0.05
0.05
0.05

KCL2
0.08
0.08
0.08
0.08
0.08
0.08

CDR2
7
7
7
7
7
7

Path
A"X
B .. X
C .. X
D .. X
E .. X
F .. X

0--- X
../

El
E2
Fl
F2

to
2.34
2.26
2.40
2.40
2.58
2.58

9

Parameter

Symbol

Typ(ns)*

=4}-

Pin Name
A
B
C
D
E
F
Pin Name
X

Input Loading
Factor (R.u)
1
1
1
1
1
1

Output Driving
Factor (R.u)
36

*

UHB-U26-E1 I Sheet 1/1 I

Minimum values for the typical operating condition.
The values for the worst case operating condition
are .dven bv the maximum delay multiplier.

I Page

9-13

2-99

I UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 2-0R S-wide Multiplexer
Pro.agation Delav Parameter

U2S
Cell Symbol

tup
to

~=P-

2.11
1.55
1.51

B1~

=till

2.07

B2~

C2
C1
D1
D2

2.11
1.55

1.46
2.03

~

KCL
O.OS
O.OS
0.08
O.OS
O.OS
O.OS
O.OS
0.08

to
3.1S
3.14
2.S1
2.S6
3.14
3.09
2.54
2.63

tdn
KCL
0.06
0.06
0.06
0.06
0.06
0.06
0.06
0.06

KCL2
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10

CDR2
7
7
7
7
7
7
7
7

11

Path
A .. X

B"X
C" X

D"X

E" X

F"X
G"X
H"X

---P'L L::

---b'C

g~~

F1
F2

P--X
Parameter

Symbol

Typ(ns)*

1../

G1~
G2~

H1~
H2~
Pin Name
A
B
C
D
E
F
G
H

Pin Name
X

Input Loading
Factor (lu)
1
1
1
1
1
1

1
1

Output Driving
Factor (lu)
36
* Minimum values for the typical operating condition.
The values for the worst ease operating condition
are~iven bv the maximum delay multiplier.

UHB-U28 El I Sheet 1/1 I

2-100

I Page 9-14

I UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 3-0R 2-wide Multiplexer
I
Prolagation Delay PaTameteT

U32
Cell Svmbol

tup
to
2.15
2.11
A1
A2
A3
B1
B2
B3

KCL
0.08
0.08

to
1.66
1.63

tdn
KCL
KCL2
0.08
0.05
0.05
0.08

CDR2
7
7

5
Path
A ... X
B"'X

?x
Parameter

Pin Name
A

Svmbol

Typ(ns)*

Input Loading
Factor (lu)

B

1
1

Pin Name
X

Output Driving
Factor (lu)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-U32-E1 I Sheet 1/1 I

I Page 9-15

2-101

.

.

caos GmAARAr UNI.T CEU; JiPtGlnCATION

FUJJ;T_~U

Cell Name

Func.t:~ion

I }lowe,!; 3-0l'! 3-IJl,i4eMl,I,lt,ipl.:x.e:r

U.33
Cell SYlllbol

P~9iia2at,icn

tup

to.

Al
A2
A3
Bl
B2
B3

2.28
2.25
.2.31

-il

j$:C;L
0.08
0.08
0.0.8

--b'

---fl

--b'
C1 .---fl
C2 --b'
C3

Pin Name.
A
B
C

Pin Name
X

.

to
.2.28
2.38
2.52

I ORB Version
J Number of BC

I

Dday P;n.-~1:_
t\ln
KCL2 CDR2
KCt
O.OS·
0.11
7
0.11
0.05
7
0.05
0.10
7

7

Path
A .. X
B .. X
C .. X

X

.
Parp"'ter

SYlllbol

Typ(ns)*

Input LOl\din,
Factor. (.tu.)
1
1
1

Output Driving
Factor (.tu)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the. maximum delay multiplier.

UHB U33-El I Sheet 1/1 I

2-102

Page

9-16

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I Power 3-0R 4-wide Multiplexer
I
Prollagation Delay Par:mreter

U34
Cell Symbol

tup
to
2.11
2.13
1.92
2.11

--n
--bI
B1=eJ
Al
A2
A3

B2
B3

C1
C2

C3
Dl
D2
D3

}=trr

KCL
0.08
0.08
0.08
0.08

to
2.98
3.00
2.44
2.69

tdn
KCL
0.06
0.06
0.06
0.06

KCL2
0.10
0.10
0.10
0.10

CDR2
7
7
7
7

9
Path
A-+X
B -+ X
C -+ X
D-+X

X

../

-n
--bI

Parameter

Pin Name
A
B
C
D

Input Loading
Factor (R.u)
1
1
1
1

Pin Name
X

Output Driving
Factor (R.u)
36

*

UHB-U34-El I Sheet 1/1 I

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Page

9-17

2-103

I UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 4-0R 2-wide Multiplexer
I
Proj:agation Delay Parameter

U42
Cell Symbol

tup
to
2.60
2.53

AI-P
IA2 A3 - f - )
A4 - t /

KCL
0.08
0.08

Parameter

to
1.71
1.64

tdn
KCL2
KCL
0.05
0.08
0.05
0.08

CDR2
7
7

Symbol

6
Path
A .... X
B .... X

Typ(ns2*

X
Bl - PJ
B2 - I B3 -~
B4 - b

Pin Name
A
B

Input Loading
Factor (Jl.u)
1
1

Pin Name
X

Output Driving
Factor (Jl.u)
36

UHB-U42-E1 I Sheet 1/1 I

2-104

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Page

9-18

I "UHB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power 4-0R 3-wide Multiplexer
I
Propagation Delay Parameter

U43
Cell Symbol

tup
to
2.57
2.62
2.70

A1-:::::
A2 -rA3 A4 -=='

Bl-l-D-B2 - B3 - B4 -=='

KCL
0.08
0.08
0.08

Parameter

to
2.13
2.26
2.39

tdn
KCL
0.06
0.06
0.06

KCL2
0.08
0.08
0.08

CDR2
7
7
7

Symbol

9
Path
A-+ X
B -+ X
C -+ X

Typ(ns)*

X

C1 -:::::
C2 -rC3 C4 -=='

Pin Name
A
B
C

Input Loading
Factor (.h)
1
1
1

Pin Name
X

Output Driving
Factor (iu)
36

UHB-U43-E1 I Sheet 1/1 I

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Pal!;e

9-19

2-105

FCJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHlI Version
I Number of BC

I Power 4-0R 4-wide Multiplexer
J
Propaltation Delay Parameter

U44
Cell Svmbol

to
2.73
2.72
2.63
2.67

A1 -P>
A2 r-IrA3 A4 - t /

tup
KCL
0.08
0.08
0.08
0.08

to
3.00
2.88
2.44
2.69

tdn
KCL
0.05
0.05
0.05
0.05

KCL2
0.11
0.11
0.11
0.11

CDR2
7
7
7
7

11
Path
A-+X
B -+ X
C -+ X
D-+X

Bl -p>J
B2 - r -

B3-~ ......

B4 - t /

-jfr

Cl
C2 - r C3 - I C4 - t /

Parameter

P---

Svmbol

Typ(ns)*

X

./

D1 _=:::'J
D2 - D3
D4 --::;;

--r-

Pin Name
A
B
C
D
Pin Name
X

Input Loading
Factor (Iou)
1

1
1
1

Output Driving
Factor (Iou)
36

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier •

.

"

UHB U44-E1 I Sheet: 1/1 I

2-106

I Palte

9-20

CMOS Chann~ed ~te Arrays

UHB Sarles Unit Cell Ubrary

Clock Buffer Family

Page

Unit Cell
Name

Function

Basic
Cells

2-109

K1B

True Clock Buffer

2

2-110

K2B

Power Clock Buffer

3

2-111

K3B

Gated Clock (AND) Buffer

36

2-112

K4B

Gated Clock (OR) Buffer

36

2-113

K5B

Gated Clock (NAND) Buffer

2-114

KAB

Block Clock (OR) Buffer

55

2-115

KBB

Block Clock (OR x 10) Buffer

30

3

2-107

UHB Series UnIt Cell L.Ibn!y

2-108

CMOS Channeled Gate A/?'S}'S

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Ce 11 Name I Function

I True Clock Buffer

KlB
Cell Svmbol

A

-+-

I

Pronagation Delav Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
0.04
0.72
0.08
0.86

Pin Name
X

2

Path
A" X

X

Parameter

Pin Name
A

I t.'HB Version
Number of BC

Svmbol

Typ(ns)*

Input Loading
Factor (Lu)
1

Output Driving
Factor (R.u)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiplier.

Equivalent Circuit
A

-{>o----{>-

UHB-KlB-E1 I Sheet 1/1 I

X

I Pae;e 10-1

2-109

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Power Clock Buffer

K2B
Cell Symbol

Pro~agation

tup
to
1.06

A

-t>-

KCL
0.04

Pin Name
X

I

Delav Parameter
tdn
KCL
KCL2 CDR2
0.03

3
Path
A ... X

X

Parameter

Pin Name
A

to
1.20

I "UHB" Versl.on
I Number of BC

Symbol

1YP(ns)*

Input Loading
Factor (iu)
1

Output Driving
Factor (ill)
55

* Minimum values for the typl.cal operating condition.
The values for the worst case operating condition
are given bv the maximum delav multiplier.
Equivalent Circuit
A

-{>o-------c{>-

UHB-K2B-E1 I Sheet 1/1 I

2-110

X

I Page 10-2

FUJITSU CMOS GATE ARRAY UNIT CELL
Cell Name I Function

I Gated Clock

K3B
Cell Symbol

Al
A2

=D-

I UHB Version
I Number of BC

SPECIFICA'!'In~

I

(AND) Buffer

Propagation Delay Parameter
tup
tdn
KCL
to
KCL
KCL2 CDR2
to
0.04
1.00
0.08
1. 00

Pin Name
X

Path
A ... X

X

Svmbol

Parameter

Pin Name
A

2

Tvp(ns)~'

Input Loading
Factor (R.u)
1

Output Driving
Factor (R.u)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delav multiplier.

Equivalent Circuit

Al
A2

==C?---V-

UHB-K3B-E2 I Sheet 1/1 I

X

.

r Page

10-3

2-111

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Gated Clock (OR) Buffer

K4B
Cell Symbol

Pro~agation

tun

Al
A2

=Y-

to

KCL

0.78

0.08

Pin Name
X

I

Delay Parameter
tdn
KCL
KCL2 CDR2
0.05

0.07

8

2
Path
A ... X

X

Parameter

Pin Name
A

to
1.14

I UHB Version
I Number of BC

Symbol

1'yp(ns)*

Input Loading
Factor (iu)
1

Output Driving
Factor (iu)
36

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
Equivalent Circuit

A1
A2

==t>--V-

UHB-K4B-E1 I Sheet 1/1 I

2-112

X

I Page 10-4

FUJITSU cnos GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I Gated Clock (NAND) BufferProj:agation Delav Parameter I

KSB
Cell Svmbol

tup
to
KCL
1.14
0.08

Al
A2

=V-

Pin Name
X

tdn
KCL2
KCL
0.04

CDR2

Path
A-+X

X

Parameter

Pin Name
A

to
1.48

3

Symbol

Typ(ns)'"

Input Loading
Factor (Rou)
1

Output Driving
Factor (Rou)
36

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalent Circuit
Al
A2

=L>-----V---C>o

UHB-KSB-E2 I Sheet; 1/1 I

X

I Page 10-5
2-113

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Block Clock (OR

KAB
Ce1l Svmbol

Al
A2

=V-

Buffer

I "UHB Version
I Number of BC

I

Propagation Delav Parameter
tup
tdn
to
to
KCL
KCL2 CDR2
KCL
0.04
0.03
1.08
1.85

3

Path
A .. X

X

Parameter

Pin Name
A

Input Loading
Factor (Rou)
1

Pin Name
X

Output Driving
Factor (Rou)
55

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are J!;iven by the maximum delay multiplier.

Equivalent Circuit

Al
A2

=V---V-

UHB-KAB-E2 I Sheet 1/1 I

2-114

X

I Page 10-6

I ljHB Version
I Number of BC

FuJITSu CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

10)
I Block Clock Buffer (OR x Propagation
I
Delav Parameter

KBB
Cell Svmbol

tup
to
KCL
1.34
0.04
0.04
1.08
CK

-

IHO
IHI
IH2
IH3
IH4
IH5
IH6
IH7
IH8
IH9

-

f-f-f-f-f--

to
2.08
1.85

tdn
KCL
KCL2
0.03
0.03

CDR2

30
Path
CK .. X
IH .. X

XO
Xl
X2
X3
X4

r---- XS
r---- X6
I-- X7
f-f--

X8
X9

Pin Name
CK
IH

Input Loading
Factor (Rou)
10
1

Pin Name
X

Output Driving
Factor (Roll)
55

Parameter

Symbol

Typ(ns)*

* MinimUM values for the typical operating condition.
The values for the worst case operating condition
are -'iven /;l~ the \IIaximum delay multiplier.

UHB-KBB-E1 I Sheet 1/2 I

I Paj;(e 10-7

2-115

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
KBB

UltB

Version

Equivalent Circuit

CK
IHO

XO
~------------------~

Xl

IHl
~------------------~

X2

IH2
~------------------1

X3

IH3
~------------------~

X4

IH4
~------------------~

X5

IHS
~------------------~

X6

IH6
~------------------~

X7

IH7
~------------------i

XB

IHB
~------------------~

IH9

UHB-KBB-E1

2-116

X9

Pa e 10-8

CMOS Channeled Gale

AlTars

UHB Series Unit Cell Ubrary

Scan Flip-flop (Positive Edge Type) Family
UnnCeIl

Basic
Cells

Page

Name

2-119

SDH

Scan D Flip-flop with 2:1 Multiplex with
Clear and Clock Inhibit

14

2-122

SDJ

Scan D Flip-flop with 4:1 Multiplex with
Clear and Clock Inhibit

15

Function

2-125

SDK

Scan D Flip-flop with 3:1 Multiplex with
Clear and Clock Inhibit

16

2-128

SJH

Scan J-K F with Clear and Clock Inhibit

36

2-131

SDD

Scan D Flip-flop with 2:1 Multiplex, Preset
Clear, and Clock Inhibit

16

2-135

SDA

Scan 1-input D Flip-flop with Clock Inhibit

12

2-138

SDB

Scan 1-input D Flip-flop with Clock Inhibit

42

2-142

SHA

Scan 1-input D Flip-flop with Clock Inhibit

68

2-145

SHB

Scan 1-input D Flip-flop with Clock Inhibit
and QOutput

62

2-148

SHC

Scan 1-input D Flip-flop with Clock Inhibit
and XQ Output

62

2-151

SHJ

Scan D Flip-flop with 2:1 Multiplex and
Clock Inhibit

78

2-154

SHK

Scan D Flip-flop with 3:1 Multiplex and
Clock Inhibit

88

2-117

UHB Ssries Unit Cell /.ibraJy

2-118

CMOS Channeled Gate Anaya

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

& Clock-Inhibit
I SCAN 2-input DFF with ClearPropagation
I
Delay Parameter

SDH
Cell Svmbol

tup
to
3.72
. 2.35
3.79
~

SI A B --(

KCL2
0.08
0.12
0.08

CDR2
7
7
7

Path
CK,IH ... Q
CK,IH ... XQ
CL ... Q,

P--XQ
Parameter
Clock Pulse Width
Clock Pause Time

I

Q
XQ

tdn
KCL
0.04
0.06
0.04

Q

CL

Pin Name

to
2.98
2.15
1.07

XQ

Al A2 CK IR-

Pin Name
Al,A2
CK
IR
CL
SI
A,B

KCL
0.08
0.08
0.08

14

Input Loading
Factor (Rou)
1

Svmbol
tCW
tCWH

Typ(ns)*
5.4
4.5

Data Setup Time
Data Hold Time

tSD
tHD

3.7
1.0

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM
tINH

4.5
3.0
1.5

1

1
3
1

2

Output Driving
Factor (Rou)
36
36

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay_ mul tiplier.

Function Table
MODE

OUTPUT

INPUT
CLK

CL

D

A

B

SI

Q

XQ

CLEAR

X

L

X

X

X

X

L

H

CLOCK

L"'H

H

Di

L

L

X

Di

Di

H

H

X

L

L

X

Qo

XQo

H

H

X

L...H...L

H

Si

Qo

XQo

H

R

X

L

H"'L"'H

X

Si

Si

SCAN

Note : CLK
D
UHB-SDH-E2 I Sheet 1/3 I

= CK
= Al

+ IH

x A2

I Page 11-1

2-119

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
SDH

UHB

Version

Equivalent Circuit
CLK

XBCK XCLK

-.L

-.L -.L

Al
A2

Q

CL

XCLK ACK

-.L -.L

CLK

-.L

II
CLK

XACK

XACK

-.L
I

51

XBCK

I

XQ

ACK

A OI--1"~------ ACK

~XACK
B OI--1"~------ XBCK

~BCK

UHB-5DH-E2

2-120

Pa e 11-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPEC IFI CATION
Cell Name I
SDH
I

I

UHB

Version

Definitions of Parameters
i) Clock Mode
i'--tCWH Clock

----...

I'--tcw-

I--tSD' I-- tHD ....

Data

I--tpd --

Q. XQ

I

(Output)

I

ii) Clear Mode

tREM ...

CK

Clear

-

-tLW

---0

it-- tpd'"

Q. XQ

(Output)

I
CL

UHB-SDH-E2 I Sheet 3/3 I

I·"~ t

I

I Pas;e 11-3

2-121

I nUHB Version
I Number of BC

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

& Clock-Inhibit
I SCAN 4-inout DFF with ClearPropagation
I
Delav Parameter

SDJ
Cell Svmbol

tup
to
2.75
2.36
3.74
AlA2 BlB2 CK IH-

-

Pin Name
Q
XQ

KCL2
0.08
0.12
0.08

CDR2
7
7
7

Path
CK,IH'" Q
CK,IH .... XQ
CL ... Q,

P"--XQ

Symbol
tCW
tCWH

Typ(ns)*
5.4
4.5

Data Setup Time
Data Hold Time

tSD
tHO

4.4
0.8

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM
tINH

4.5
3.0
1.5

Parameter
Clock Pulse Width
Clock Pause Time

I

IH

tdn
KCL
0.04
0.06
0.04

Q

CL

CL
SI
A,B

to
3.02
2.14
1.06

XQ

SI A B --C

Pin Name
A1,A2
B1,B2
CK

KCL
0.08
0.08
0.08

15

Input Loading
Factor (.~u)
1
1
1
1
3
1
2

Output Driving
Factor (iu)
36
* Minimum values for the typical operating condition.
36
The values for the worst case operating condition
are given by the maximum dela~mult~lier.

Function Table
MODE
CLK

CL

D

A

B

SI

Q

XQ

CLEAR

X

L

X

X

X

X

L

H

CLOCK

L-+H

H

Di

L

L

X

Di

Di

H

H

X

L

L

X

Qo

XQo

H

H

X

L...H....L

H

Si

Qo

XQo

H

H

X

L

H....L-+H

X

Si

Si

SCAN

UHB-SDJ-Ell Sheel: 1/3 I

2-122

OUTPUT

INPUT

Note : CLK = CK + IH
D = (AI x A2) + (B1 x B2)

I Page 11-4

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
SDJ

UHB

Version

Equivalent Circuit

Al
A2

Bl
B2

Q

CL

XCLK ACK

CLK

--L

--L --L
II
CLK

XACK

XACK

--L
I

81

XBCK
XQ

I

ACK

CK~

IH

1:: :=

A0

4=~'
XACK

B0

4=~cr

XCLK

BCK

Pa e 11-5

2-123

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SDJ
I

I "1JlIB" Version

Definitions of Parameters
i) Clock Mode
-tCWHClock

-----..

I'--tcw-

Data

~tHD'"

-tSD

1~'Pdl

Q. XQ

(Output)

I

I

ii) Clear Mode

CK

Clear

tREM

-----.. j<--tLW ---"
I- tpd"

Q. XQ

(Output)

CL

UHB-SDJ-El I Sheet 3/3 I

2-124

I' '~ t
I Page 11-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB" Version
I Number of BC

& Clock-Inhibit
I SCAN 6-input DFF with ClearPropagation
I
Delay Parameter

SDK
Cell Svmbol

tup
to
3.70
2.32
3.74

AlA2 Bl B2 ClC2 CKIH -

KCL
0.08
0.08
0.08

to
3.00
2.16
1.02

tdn
KCL
0.04
0.06
0.04

KCL2
0.08
0.12
0.08

CDR2
7
7
7

16
Path
CK,IH'" Q
CK,IH ... XQ
CL ... Q,
XQ

-

Q

:>-- XQ

SI A B -(

Parameter
Clock Pulse Width
Clock Pause Time

I

Symbol
tCW
tCWH

Typ(ns)*
5.4
4.5

Data Setup Time
Data Hold Time

tSD
tHD

5.0
0.5

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM

4.5
3.0
1.5

CL

Pin Name
Al,A2
Bl,B2
Cl,C2
CK
IH
CL
SI
A,B
Pin Name
Q
XQ

Input Loading
Factor (lu)

tINH

1
1
1
1

1

3
1

2
Output Driving
Factor (lu)
36
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
MODE

OUTPUT

INPUT
CLK

CL

D

A

B

SI

Q

XQ

CLEAR

X

L

X

X

X

X

L

H

CLOCK

L"'H

H

Di

L

L

X

Di

Di

H

H

X

L

L

X

Qo

XQo

H

H

X

L..H...L

H

Si

Qo

XQo

H

H

X

L

H...L"'H

X

Si

5i

SCAN

UHB-SDK-El I Sheet 1/3 I

Note : CLK = CK + IH
D = (AI x A2) + (Bl x B2) + (Cl x C2)

Page 11-7

2-125

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
SDK

UHB

Version

Equivalent Circuit
Al
A2

Bl
B2

Cl
C2

Q

CL
XCLK ACK

CLK

--L

--L --L
II
CLK

XACK

XACK

--L
I

SI

XBCK
XQ

I

ACK

A

o>--...~----- ACK
L.{>o-XACK

B o-.,..~----- XBCK
L.{>o-BCK

UHB-SDK-El

2-126

Pa e 11-8

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SDK
I

I

lJllB" Vers ion

Definitions of Parameters

i) Clock Mode
---tCWH <--tcwClock

~

-tSD~ ....

Data

tHD->

-tpd-

Q, XQ
(Output)

I

I

ii) Clear Mode

r

CK

Clear

Q, XQ

tREM ...

~

-tLW-

-tpd""

I

(Output)

I
CL

UHB-SDK-EI I Sheet 3/3 I

f
I

,,~

t
I Page 11-9

2-127

FUJITSU C:10S GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I SCAN J-K FF with Clear & Clock-Inhibit
I
Propagation Delay Parameter

SJH
Cell Svmbol

tup
to
4.24
2.36
3.76
-Q

SI A B --C

0--- XQ

I

Q
XQ

KCL2
0.08
0.12
0.08

Parameter
Clock Pulse Width
Clock Pause Time

CL

Pin Name

tdn
KCL
0.04
0.06
0.04

to
3.37
2.16
1.39

CDR2
7
7
7

Path
CK,IH" Q
CK,IH .. XQ
CL .. Q,
XQ

J K --C
CK IH-

Pin Name
J,K
CK
IH
CL
SI
A,B

KCL
0.08
0.08
0.08

16

Symbol
tCW
tCWH

Typ(ns)*
5.4
4.5

Data Setup Time (J)
Data Setup Time (K)
Data Hold Time (J K)

tSD
tSD
tHD

4.4
4.8
0.5

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM
tINH

4.5
3.0
1.5

Input Loading
Factor (Rou)
1
1
1
3
1
2
Output Driving
Factor (Rou)
36
36

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
OUTPUT

INPUT
MODE
CLEAR

CLOCK

SCAN

CLK

CL

J

K

A

B

SI

Q

XQ

X

L

X

X

X

X

X

L

H

L..H

H

L

L

L

L

X

L

H

L->H

H

H

H

L

L

X

H

L

L-+H

H

L

H

L

L

X

Qo

XQo

L-+H

H

H

L

L

L

X

XQo

Qo

H

H

X

X

L

L

X

Qo

XQo

H

H

X

X

L-+H-+L

H

Si

Qo

XQo

H

H

X

X

L

H-+L-+H

X

Si

Si

Note : CLK
UHB-SJH-E1 I Sheet 1/3 I

2-128

= CK

+ IH

I Page 11-10

FUJITSU

C~OS

GATE ARRAY UNIT CELL

SPECIFICATIO~

Version

mill

Cell Name

SJH
Equivalent Circuit

J

Q
K

CLo-----4

XACK

-L

I

51

X1!CK

XQ

I
ACK

:=

..

A o-----..,.~----- ACK

~XACK

XCLK
B o-----..,.~----.. X1!CK

~BCK

Pap;e 11-11

2-129

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SJH
I

I

UHB

Version

Definitions of Parameters
i) Clock Mode
Io--tCWH Clock

------

-tcw-

<-tSD' I<- tHD-I

Data

I--tpd
Q, XQ
(Output)

-0

I

I

ii) Clear Mode

CK

Clear

tREM ..

-----.. I<---tLW I<- tpd ....

Q. XQ
(Output)

I

CL

UHB-SJH-~l

2-130

I Sheet 3/3 I

fu~ t
I Page

11-12

I "UHS" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

Clock-Inhibit
I SCAN 2-input DFF with Clear, Preset &Delay
Parameter

SDD
Cell Symbol

tup
PR

Al A2 CKIH-

1

Pin Name
Q
XQ

to
3.70
2.65
4.50

KCL
0.08
0.08
0.08

to
3.22
2.14
1.02

tdn
KCL
0.04
0.06
0.04

KCL2
0.08
0.12
0.08

3.84

0.08

2.35

0.06

0.12

CDR2
7
7
7

Path
CK,IH -+ Q
CK,IH -+ XQ
CL -+ Q,
XQ

I-- Q

7

PR

-+ Q,
XQ

Symbol
tCW
tCWH

Ty}l(ns)
5.4
4.5

I

Data Setup Time
Data Hold Time

tSD
tHD

5.4
1.0

CL

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM
tINH

5.0
3.0
1.5

Preset Pulse Width
Preset Release Time
Preset Hold Time

tPW
tREM
tlNH

6.8
3.7
1.0

SI A B ---c

Pin Name
Al,A2
CK
IH
CL
PR
SI
A,B

16

Pro~agation

Parameter
Clock Pulse Width
Clock Pause Time

P--XQ

Input Loading
Factor (~u)
1
1
1

*

3
3
1

2
Output Driving
Factor (~u)
36
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
MODE

INPUT

OUTPUT

CLK

CL

PR

D

A

B

SI

Q

XQ

CLEAR

X

L

H

X

X

X

X

L

H

PRESET

X

H

L

X

X

X

X

H

L

CLOCK

L-+H

H

H

Di

L

L

X

Di

Di

H

H

H

X

L

L

X

Qo

XQo

H

H

H

X

L-+H-+L

H

Si

Qo

XQo

H

H

H

X

L

H-+L-+H

X

Si

Si

X

L

L

X

X

X

SCAN

CL/PR

Note : CLK
D
UHB-SDD-E3 I Sheet 1/4 I

X

= CK
= Al

Prohibited
IH
x A2
+

I Page 11-13

2-131

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

SDD
Equivalent Circuit

Al
A2

CL

Q

II
CLK

XACK

XACK

--.L
I

SI

XBCK
L..-_ _ _- ,

XQ

IACK

PR

:=

XCLK

A O-'t"~----- ACK

L-f>o--

XACK

B O-'t"~----- XBCK

L-f>o--

UHB-SDD-E3

2-132

BCK

Pa e 11-14

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SDD
I

I

UHB

Version

Definitions of Parameters
i) Clock Mode

Clock

-

-tcw

Data

-tCWH----0

o-tSD o-tHD ""

-tpdQ. XQ

(Output)

ii) Clear Mode

CK

Clear

tREM

-

-tLW

----0

-tpd""
Q. XQ

(Output)

tINH
Clear

UHB-SDD-E3 I Sheet 3/4 I

I Page 11-15

2-133

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SDD
I

I

UHB Version

iii) Preset Mode

CK

Preset

IotREM ..

-

o-tpw-

.... tpd'"
Q. XQ

(Output)
tINH

Preset

'.

UHB-SDD-E3 I Sheet 4/4 I

2-134

I Page 11-16

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UllB" Version
I Number of BC

I SCAN I-input DFF with Clock-Inhibit
I
Propagation Delav Parameter

SDA
Cell Svmbol

tup
to
3.18
2.33

D

-

CK
IH
SI
A
B

-

KCL
0.08
0.08

tdn
KCL
KCL2
0.04
0.08
0.06
0.12

to
3.00
2.17

CDR2
7

7

12
Path
CK,IH .. Q
CK,IH .. XQ

r0-

f--

P-

Q
XQ

-

--C

Parameter
Clock Pulse Width
Clock Pause Time

'---

Data Setup Time
Data Hold Time

Pin Name
D
CK
IH
SI
A,B

Pin Name

Q
XQ

Symbol
tCW
tCWH

Typ(ns)*
5.4
4.5

tSD
tHD

3.5
1.4

Input Loading
Factor (.h)
1
1
1

1
2

Output Driving
Factor (Jl.u)
36
36

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
MODE

CLOCK

SCAN

OUTPUT

INPUT
CLK

D

A

B

SI

Q

XQ

L"H

Di

L

L

X

Di

Di

H

X

L

L

X

Qo

XQo

H

X

L-+H"L

H

Si

Qo

XQo

H

X

L

H"L..H

X

Si

Si

Note

UHB-SDA-El I Sheet 1/3 I

:

CLK

= CK

+

IH

Page 11-17

2-135

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

SDA
Equivalent Circuit
CLK

XBCK

-L

-L -L

XCLK

D

Q

I

II

XCLK

BCK

XCLK ACK

CLK

CLK

-L -L

-L

II
CLK

XACK

XACK

-L
I

SI

XBCK
XQ

I

ACK

V2B

A O)-~~------ ACK

:CLK
L.{>o-XACK
XCLK
B o>--~~----...., XBCK
L . { > o - BCK

UHB-SDA-El

2-136

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SDA
I

I "UHB" Version

Definitions of Parameters
i)

Clock Mode

Clock

-----

__ tcw --01'-- tCWH

Data

t t SD

t
Q, XQ

(Output)

UHB-SDA-El I Sheet 3/3 I

--0

.... tHD ....

-tpd-

I
I
I

I Page 11-19

2-137

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I SCAN I-input 4-bit DFF with Clock-Inhibit
I
Delay Parameter

SDB
Cell Symbol

42

Pro~agation

tup
to
4.24
3.25

KCL
0.08
0.08

to
3.94
3.32

tdn
KCL
KCL2
0.04
0.08
0.06
0.12

CDR2
7
7

Path
CK,IH'" Q
CK,IH'" XQ

r---

I - - Q1

D1D2 D3 D4 -

P-P--

XQl

I - - Q2

XQ2

I - - Q3

p-

CKIHSI A B -C

XQ3

I - - Q4

P--

XQ4

'---

Pin Name
D
CK
IH
SI
A,B

Pin Name
Q
XQ

Parameter
Clock Pulse Width
Clock Pause Time
Data Setup Time
Data Hold Time

Symbol
tCW
tCWH

Typ(ns)*
6.8
5.0

tSD
tHD

2.2
3.3

Input Loading
Factor (Rou)
1
1
1
I

2

Output Driving
Factor (Rou)
36
36

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
MODE

CLOCK

SCAN

INPUT

OUTPUT
Qn

XQn

X

Di

Di

L

X

Qn o

XQn o

L....H....L

H

Si

Qn o

XQn o

L

H...L....H

X

Si

Si

CLK

Dn

A

B

L...H

Di

L

L

H

X

L

H

X

H

X

SI Qn-1

Note : CLK = CK + IH
n =1 - 4
UHB-SDB-E2 I Sheet 1/4 I

2-138

I Page 11-20

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
SDB
Equivalent Circuit
Dl

D2

D3

XQl Ql

D

SIo-____________

XQ

D

QoQ-'r

QoQI-'i

S

~

FFl
CK 0-- CK CLK I--_~CLK
IH 0-- IH XCLK
XCLK
ACK
ACK
A0-- A XACK
XACK
BCK
BCK
B o-c ii XBCK
XBCK

p-

FFl
,..--CLK
_XCLK
r - - ACK
__ XACK
r- BCK
XBCK

Version

D4

XQ2 Q2

XQ ::>-

~S

UHB

XQ3 Q3

XQ

D

p-

XQ4 Q4

XQ ::>-

D

QoQI 'is Qo

Q-

S

FFl
_CLK
,------ XCLK
r - - ACK
,..- XACK
r- BCK
XBCK

FFI
_CLK
,------ XCLK
_ACK
,.-- XACK
_ BCK
XBCK

FFO

Equivalent Circuit (FFO)

CK
IH

)()-------+

CLK
XCLK

AO~~~K

4>r--------

XACK

BO~~ XBCK
BCK

Pa e 11-21

2-139

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB Version

Cell Name

SDB

CLK

-L

Equivalent Circuit (FFl)
XBCK XCLK

-L l

Q

D

t-------oQo
S

I
XBCK
XQ

V2B

UHB-SDB-E2

2-140

Pa e 11-22

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name J
SDB
I

I

UHB

Version

Definitions of Parameters
i) Clock Mode

Clock

----.... -

tcw --~- tCWH -

Data

0-

tSD.~

tHO ....

II-tpdQ. XQ

(Output)

UHB-SDB-E2 I Sheet 4/4 I

r-~------------------

I Page 11-23

2-141

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Fimction

I "UHB" Version
I Number of BC

Clock-Inhibit
I SCAN I-input 8-bit DFF withPropagation

SHA
Cell Symbol

tup

-

r--

Dl-

pr-p-

D2 D3 D4DS D6 D7 D8 -

r-Pr--

P-r--

PCKIH SI A B ----c

Pin Name
D
Cl<
IH
S1

'----

Q1
XQ1
Q2
XQ2
Q3
XQ3
Q4
XQ4

KCL
0.16
0.16

to
4.72
4.00

Path
CK,IH ... Q
CK,IH ... XQ

Parameter
Clock Pulse Width
Clock Pause Time
Data Setup Time
Data Hold Time

Symbol
tCW
tCWH

ryp ns
7.2
5.5

tSD
tHD

1.8
3.3

*

Input Loading
Factor (R.u)
1
1

B
Pin Name
Q
XQ

Output Driving
Factor (R.u)
18
18

UHB-SHA-E1 I Sheet 1/3 I

2-142

to
4.72
4.12

68

QS

XQS
I-- Q6
P- XQ6
r-- Q7
P- XQ7
r-- Q8
P- XQ8

1
1
1
1

A

I

Parameter
tdn
KCL
KCL2 CDR2
0.09
0.10
4
0.13
0.18
4

Del~

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are ltiven by the maximum delay multiplier .

.1 Page 11-24

FUJITSU

C~OS

GATE ARRAY UNIT CELL SPECIFICATION

Version

DuB

Cell Name
SHA

Equivalent Circuit

D1

CK
IH

DB

) O - - - -... CKI

XCKI

FFo
CKI
XCKI
AI
XAI
BI
XBI

FFo

X5Io X50 0

XSIo X50 0

x

x

5I

XSIo
X

Q

Ql
l---oXQI

Q

QB

Q2

l---oXQB

1---oXQ2

Equivalent

XQo

.-----0 XSOo
(VIN)

XAI

-L

II
CKI

XAI

XSIo

I

I
AI

XCKI

BI

-L
I

XBI
Pa e 11-25

2-143

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
Sa!

I

UHB Version

I

Definitions of Parameters
i) Clock Mode

I-- tcw -_01"-- tcWH Clock

~

Data

I>- tSD'~ tHD ...

Q, XQ

(Output)

UHB-SHA-El I Sheet 3/3 I

2-144

r Page

11-26

I "UHB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Func1:ion

Clock-Inhibit & Q
I SCAN I-input 8-bit DFF withPropagation
Delav Parameter

SHB
Cel1 Symbol

Output

tup

DlD2 D3 D4 D5 D6 D7 D8 CKIH SI A B ---<:

Pin Name
D
CK
IH
S1
A
B

Pin Name
Q

to
4.32

-

--

KCL
0.16

to
4.42

tdn
KCL
KCL2
0.09
0.10

1

62

CDR2
4

Path
CK.IH .... Q

Symbol
tCW
tCWH

lYP(ns)*
7.2
5.5

Ql
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Parameter
Clock Pulse Width
Clock Pause Time

-

Data Setup Time
Data Hold Time

tSD
tHD

1.9
3.3

Input Loading
Factor (Rou)
1
1
I
I
1
I
Output Driving
Factor (Rou)
18
* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-SHB-El I Sheet 1/3 I

fPage 11-27

2-145

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
SHB

UHB

Version

Equivalent Circuit
Dl
CK
IH

D8

X>----CKI
FFo
CKI
XCKI
AI
XAI
BI
XBI

~

XSIo XSOo

XSIo XSOo

XSIo
Q

SI

Q2

Ql

CKI

--.L

Q8

Equivalent Circuit (FFo)
XBI
XCKI

--.L --.L

,.------QXSO o
X>---0Qo
XAI

--.L

II
CKI

XAI

XS10 o------i

I

I
AI

XCKI

BI

--.L
I

XBI

UHB-SHB-El

2-146

Pa e 11-28

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SHB
I

I

ORB

Version

Definitions of Parameters
i) Clock Mode

Clock

-

tCWH -

~tcw

Data

Q. XQ
(Output)

UHB-SHB-El I Sheet 3/3 I

~tSD

... tHO'"

r'¢l

I

I
I

I Pall:e 11-29

2-147

I "UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

Clock-Inhibit
XQ
I
I SCAN l-inout 8-bit DFF withPro):altation
Delay_Parameter

SHC
Cell Symbol

&

tuo

DlD2 D3 D4 Ds D6 D7 D8 CK IH SI A B

to
4.18

-

Pin Name
XQ

tdh
KCL
KCL2
0.13
0.18

CDR2
4

Path
CK,IH .. XQ

o--XQ3
XQ4
XQs
XQ6
XQ7
o--XQ8

0-0-0-0--

Parameter
Clock Pulse Width
Clock Pause Time
'---

B

to
4.10

62

0-- XQI
0-- XQ2

-C

Pin Name
D
CK
IH
SI
A

KCL
0.16

Output

Data Setuo Time
Data Hold Time

Svmbol
tCW
tCWH

Typ(ns)'"
7.2
5.5

tSD
tHO

3.3

1.9

Input Loading
Factor (R.u)
I
I
1
1
1
1
Output Driving
Factor (R.u)
18

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiolier.

UHB-SHC-El I Sheet 1/3 I

2-148

I Page

11-30

FUJITSU
Cell Name
SHC

GATE ARRAY UNIT CELL SPECIFICATION

C~OS

UHB Version

Equivalent Circuit

Dl
CK
IH

D2

D8

CKI

AoV[t:
BoV[t:

FFo

FFo
=

XCKI

~

: XAI
AI
X5Io X50 0

XSlo XSOo
X

XSIo

X

X

::1
51
XQl

XQ8

XQ2

Equivalent Circuit (FF.)
XBI
XCKI

-L -L

; ; 0 - - - - - 0 XQo

Do

XCKI

XAI

-L
X5Io

BI

II
CKI

XAI

, . . - - - - - 0 XSOo

CKI

eKI

-L
I

I
AI

XeKI

BI

-L
I

XBI
Pa e 11-31

2-149

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SHC
I

I "UHB

Version

Definitions of Parameters
i) Clock Mode

Clock

Data

~tSD

.. tHD-o

------~r_~I~~Jr_--+-----------~

Q, XQ

(Output)

UHB-SHC-Elj Sheet 3/3 I

2-150

~tPd?
i =t=~I==========

I Page 11-32

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
SCAN 8-bit DFF with Clock-Inhibit
SHJ
78
& 2-to-1 Data Multiplexer
Cell Svmbol
ProJ:agation Delay Parameter
tup
tdn
Path
to
KCL
to
KCL
KCL2 CDR2
CK,IH -+ Q
0.08
4
4.82
0.16
4.84
0.12
CK,IH -+ XQ
0.11
0.20
4
4.12
0.16
4.00
Al -Q1
Bl ::>- XQ1
A2 -Q2
B2 ::>- XQ2
A3 -Q3
B3 P-- XQ3
A4r--Q4
B4 P--XQ4
f--QS
AS BS XQS
A6 f--Q6
B6 P--XQ6
A7 r--Q7
B7 P--XQ7
t--Q8
A8 B8 XQ8
AS --C
BS --C
CK1H SI Symbol
Typ(ns)*
Parameter
A 7.2
tCW
Clock Pulse Width
--C
B
5.5
tCWH
Clock Pause Time

I

I

P----

P----

-

Data Setll£Time
Data Hold Time
Pin Name
An,Bn
(n=1-8)
AS,BS
CK
IH
SI
A,B
Pin Name
Q
XQ

tSD
tHD

3.0
3.1

Input Loading
Factor (Rou)
1
1
1
1
1
1
Output Driving
Factor (Rou)
18
18

UHB-SHJ-E2 I Sheet 1/3 I

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Page 11-33

2-151

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
SHJ

UHB' Version

Equivalent Circuit

Al
CK
IH

CKI

Ao

XCKI

Ao-{>ol;

::1

Bo-{>ol;

::,

BI

A2

B2

A8

Bo

B8

Ao

Bo

FFo
CKI
XCKI
AI
XA1
BI
XBI
AS o
BS o
XSIo XSOo
Qo XQo

ASo-[)o- AS o

QI

XQI

XSIo XSOo
Qo XQo

Q2

XSIo XSOo
Qo XQo

XQ2

Q8

XQ8

BSo-[)o- BS o
S1
Equivalent

r-----{)

XSO o

(VIN)

XAI

-L

II
CK1

XAI

XS10 <>----1

I

I
AI

XCKI

BI

-L
I

XBI

lJHB-SHJ-E2

2-152

Pa e 11-34

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SHJ
I

I

UHB

Version

Definitions of Parameters
i) Clock Mode

Clock

_ I - - tcw

Data

-->1-- tCWH -

-- tSD·1-- tHO ....

Q. XQ
(Output)

UHB-SHJ-E2 I Sheet 3/31

I Page 11 35

2-153

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
SCAN 8-bit DFF with Clock Inhibit
SHK
& 3-to-1 Data Multiplexer
88
Cell Symbol
PrOfli&ation Delay Parameter
tup
tdn
to
to
Path
KCL
KCL
KCL2 CDR2
r--Al _
4.64
0.16
4.60
0.09
0.10
4
CK,IH'" Q
B1 _
-Q1
CK,IH ... XQ
4.08
0.16
4.00
0.13
0.18
4
C1_
:r-XQ1
A2 _
B2 _
-Q2
C2 _
:r-XQ2
A3 _
B3 _
-Q3
C3 _
:r-- XQ3
A4 _
B4 _
-Q4
C4 _
:r-XQ4
A5 _
B5 _
-Q5
C5 _
:r-- XQ5
A6 _
B6 _
:--Q6
C6 _
XQ6
A7 _
B7 _
r--Q7
C7 _
P-- XQ7
A8 _
B8 _
I--Q8
C8 _
P--XQ8
AS --(
BS --(
CS --(
CK IH Tvp(ns)'~
Parameter
Symbol
SI tCW
7.2
Clock Pulse Width
5.5
A Clock Pause Time
tCWH
B --(
tSD
3.8
Data Setup Time
2.9
Data Hold Time
tHD

I

I

P--

Pin Name
An,Bn,Cn
(n=1-8)
AS,BS,CS
CK
IH
SI
A,B
Pin Name
Q
XQ

Input Loading
Factor (Rou)
1
1
1
1
1
1
Output Driving
Factor (Rou)
18
18

UHB-SHK E2 I Sheet 1/3 I

2-154

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page 11-36

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

UHB

Version

SHK

A1 B1 C1

Equivalent Circuit
CK
IH

Ao-{)o L[>O

::1

Bo-{)o L[>O

::1

o--{>o--BS o--{>o--CS o--{>o---

AS

B2 CZ

A8

B8 C8

I

CKI
XCKI

A2

Ao Bo Co

Ao Bo Co

FFo
CKI
XCKI
AI
XAI
BI
XB1
AS o
BS o
CS o
XSIo XSOo
Qo XQ.

FFo

AS.

Ql

XQl

A. Bo Co

CKI
XCKI
AI
XAI
BI
XBI
AS o
BS o
CS.
XS10 XSOo
Qo XQo

Q2

XQ2

Q8

XQ8

BS.

lID

CS o

SI
Equivalent
Ao
AS.
B.
BS o
Co
CS o

XQo

.------0 XSO o
(VlN)
)O----0Qo
XAI

-L

II
CKI

XAI

XSI.o----

I

I
AI

XCK1

B1

-L
I

XB1
Pa e 11-37

2-155

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SHK
I

I

UHB

Version

Definitions of Parameters
i) Clock Mode
_

-

tcw - - - - tCWH

----0

Clock

Data

Q, XQ

(Output)

UHB-SHK-E2 I Sheet 3/3 I

2-156

1 P~e 11-38

UHB Series Unit Cell Ubrary

CMOS Charmeleel Gate Arrays

Non Scan Flip-flop Family

Page

Unit Cell
Name

2-159

FOM

Non-Scan 0 Flip-flop

2-161

FON

Non-Scan 0 Flip-flop with Set

7

2-163

FOO

Non-Scan 0 Flip-flop with Reset

7

2-165

FOP

Non-Scan 0 Flip-flop with Set and Reset

2-168

FDa

Non-Scan 0 Flip-flop

21

2-170

FOR

Non-Scan 0 Flip-flop with Clear

26

2-173

FOS

Non-Scan 0 Flip-flop

20

2-175

F02

Non-Scan Power 0 Flip-flop

7

2-177

F03

Non-Scan Power 0 Flip-flop with Preset

8

2-179

F04

Non-Scan Power 0 Flip-flop with Clear and Preset

9

2-181

F05

Non-Scan Power 0 Flip-flop with Clear

8

2-183

FJO

Non-Scan Positive Edge Clocked
Power J-K Flip-flop with Clear

Function

Basic
Cells

6

8

12

2-157

UHB Series. Unit Cell Ubraty

2-158

CMOS Channeled Gars ATJys

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Non-SCAN DIT

FDM
Cell Symbol

Pro]:agation
tup
to
1. 75
2.16

KCL
0.16
0.16

to
1.80
2.36

I UHB Version
I Number of BC

I

Parameter
tdn
KCL
KCL2 CDR2
0.09
0.09

Del~y

6
Path
CK -+ Q
CK -+ XQ

DU'
CK

XQ

Parameter
Clock Pulse Width
Clock Pause Time
Data Setup Time
Data Hold Time
Pin Name
D
CK

Input Loading
Factor (iu)
2
1

Pin Name
Q
XQ

Output Driving
Factor (iu)
18
18

*

Symbol
tCW
tCWH

Typ(ns)*
4.0
4.0

tSD
tHD

2.1
1.5

Minimum values for the typical operating condition.
The values for the worst case operating condition
are .ll:iven bv the maximum delay multiplier.

Function Table
Inputs

Outputs

D CK

Q

XQ

H t

H
L

L
H

L

t

UHB-FDM-E2 I Sheet 1/2

I Page 12-1

2-159

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

FDM
Equivalent Circuit

CLK

XCLK

-L

-L

Q
XQ

D

I

I

XCLK

ex

CLK
XCLK

CLK

-L

-L

ICLK

I

XCLK

o--tt:=

XCLK

Definition of Parameters

CK

D

tcw
tSD

Q,XQ

UHB-FDM-E2

2-160

Pa e

12-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name LFunction

I Non-SCAN DFF with SET

FDN
Cell Symbol

Pro~al!;ation

tup
to
1.80
2.46
2.24

8

D
CK

KCL
0.16
0.16
0.16

to
1. 75
2.42
1.07

I "UHB Version
I Number of BC

I

Delay Parameter
tdn
KCL2 CDR2
KCL
0.12
0.09
4
0.08
0.08

7
Path
CK .. Q
CK .. XQ
8 .. Q,XQ

=6=:,
8ymbol
tCW
tCWH

Typ(ns)*
4.0
4.0

Data Setup Time
Data Hold Time

tSD
tHO

2.1
1.5

Set Pulse Width
Set Release Time (8)
Set Hold Time

tSW
tREM
tINH

4.0
0.3
3.8

Parameter
Clock Pulse Width
Clock Pause Time

Pin Name
D
8
CK

Input Loading
Factor (Lu)
2
2
1

Pin Name
Q
XQ

Output Driving
Factor (Lu)
18
18

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
Inputs
S D CK

Outputs
Q XQ

L
H

X

X

H

H

L

t
t

H
H
L

UHB-FDN-E3 I Sheet 1/2 I

L
L
H

Page 12-3

2-161

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
FDN

UHB

Version

Equivalent Circuit
S

CKO

XCKO

-L

-L

Q

p---~~xr-----oXQ

D

CKO

-L
ICKO

IXCKO

cx~c~
XCKO
Definition of Parameters
1) tcw, tCWH' tSD, tHD and tpd (CK

~

Q,XQ)

CK

D

Q,XQ
2) tsw, tREM' tINH and tpd (5 ~ Q,XQ)

tcw

CK
tsw

s

))_..J
tREM
~----))

tpd

Q

XQ

............. ~----+----)) ....... .
))
))---+.............

UHB-FDN-E3

2-162

~lo...-_+--

_ _ _ _ )) ............

~

_ __

Pa e 12-4

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

1

FDO
Cell Symbol

Pro~aJ;tation

tup

D

I

Non-SCAN DFF with RESET
to
1.93
2.16
2.00

CK

I UHB Version
I Number of BC

KCL
0.16
0.16
0.16

to
1. 78
2.58
1.64

Delav Parameter
tdn
KCL2 CDR2
KCL
0.10
0.09
0.10

7

Path
CK -+ Q
CK -+ XQ
R -+ Q,XQ

=0=:,
Input Loading
Factor (Lu)

Pin Name
D
R
CK

Symbol
tCW
tClwll

Typ(ns)*
4.0
4.0

Data Setu~ Time
Data Hold Time

tSD
tHO

2.1
1.5

Reset Pulse Width
Reset Release Time (R)
Reset Hold Time

tRW
tREM
tINH

4.0
0.9
3.3

Parameter
Clock Pulse Width
Clock Pause Time

R

2
2

1
Output Driving
Factor (Lu)
18
18

Pin Name
Q
XQ

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
Inputs
R D CK

Outputs
Q
X

L
H
H

X

L

H

t
t

H

L

L

H

X
H
L

UHB-FDO-E31 Sheet 1/2 I

I Page 12-5

2-163

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
'Cell Name
FDO

UHB Version

Equivalent Circuit
XCKO

CKO.

--'-

--'-

Q

XQ

o

T

T

~CKO CKO
CK

XCKO

L

•

XCKO
R

Definition of Parameters
1) tCW. tCWH. tSD. tHO and tpd (CK • Q.XQ)
tcw --+--tCWH

CK

o
Q.XQ

tCW ---1I;:..::.:t~tL..:.:::;'l
CK

~~--I
tREM

"I~+-----~~

R

~~........

............. - I . , . - _ t - - - - - - ~~ ........... ., . . . - - - -

UHB-FDO-E3

2-164

--"1"'-

lo.-...--+_ _ _ _ _ ~~---+- '--_ __

Q

XQ

tINH

~~
Pa e 12-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

I UHB Version
I Number of BC

I Non-SCAN DFF with Set andProResetaltation Delay Parameter I

FDP
Cell Symbol

to
1.96
2.45
2.24
2.54

S

tup
KCL
0.16
0.16
0.16
0.16

to
1. 76
2.50
1.59
1.01

tdn
KCL
KCL2
0.10
0.09
0.10
0.09

CDR2

8
Path
CK .. Q
CK .. XQ
R .. Q.XQ
S .. Q.XQ

-Q

D-

CIt :>-- XQ

Parameter
Clock Pulse Width
Clock Pause Time

R

Input Loading
Factor (iu)
2
2
2
1

Pin Name
D

S
R
CIt

Symbol
tCW
tCWH

Typ(ns)*
4.0
4.0

Data Setup Time
Data Hold Time

tSD
tHO

2.1
1.5

Set Pulse Width
Set Release Time (S)
Set Hold Time

tSW
tREM
tlNH

4.0
0.3
3.8

Reset Pulse Width
Reset Release Time (R)
Reset Hold Time

tRW
tREM
tINH

4.0
0.9
3.3

Output Driving
Factor (iu)
18
18

Pin Name

Q
XQ

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
Function Table
Inputs

Outputs

S

R

D

CIt

Q

X
X
X

L

H

L

X

L

H

L

L

H

H
H

X
X
H

H

L

t
t

XQ
H

L
Inhibited
H
L

UHB-FDP-E3 I Sheet 1/3 I

H

L

H

I Page 12-7
2-165

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
FDP

UHB

Version

Equivalent Circuit

S

CKO

Q

-L
D

XQ

I

XCKO

CKO
XCKO

CKO

-L

-L

I

I

CKO

XCKO

R

CK

o----{>--rf)o
"

'VHB-FDP-E3

2-166

: exo

1
..._ "_____ XCKO

Pa e 12-8

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

FDP
Definition of Parameters
1) tcw, tCWH, tSD, tHO and tpd (CK

-

CK

-tcw

~

Q,XQ)

tCWH-

r---.... tSD ... tHO

D

..... tpdQ,XQ

2) tRW, tREM' tINH and tpd (R
CK

~

Q,XQ)

--"","I'"-tcW

))--'1
tREM

,-+----))
R

))---+-~

lo---+_ _ _ _ _ ))........

Q

XQ

,-----+-----)) ............'~---+---

~

3) tSW, tREM, tINH and tpd (S
CK

tcw
'SW

S

Q

XQ

"--_ __

tpd

.............

'REM

~

Q,XQ)

=i=

II

1,-+---))
~r------~~

tINH

----..Ir---1

.. ·...... ·1

~-----~~ ..........\ _ - - Pa e 12-9

2-167

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I "UHB Version
I Number of BC

I Non-SCAN 4-bit DFF

FDQ
Cell Svmbol

DA

I

Propagation Delay Parameter
tup
tdn
to
to
KCL
KCL2 CDR2
KCL
3.37
0.16
2.74
0.08

21
Path
CK ... Q

DC

(i (f
CK

-QA
-QB
-QC
-QD

--<

Parameter
Clock Pulse Width
Clock Pause Time
Data Setup Time
Data Hold Time
Pin Name
D
CK

Input Loading
Factor (iu)
1
1

Pin Name
Q

Output Driving
Factor (iu)
18

Svmbol
tCW
tCWL

TvP(ns)*
4.0
4.0

tSD
tHD

1.1
2.8

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by_ the maximum delay multiplier.
Function Table
Input
CK D

•
~

H
L

Output
Q
H
L

UHB-FDQ-E3 I Sheet 1/2 I

2-168

I Page 12-10

FUJITSU CXOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
FDQ

UHB

Version

Equivalent Circuit

r-------------------------,
XCKO

CKO

--L

--L
QA

DA 0 - - - - - - , - /
1
1

CK~:
v

CKO

~I

1

XCK0 1
XCKO

CKO

~-------------------------~
..l.....oQB

DB 0 > - - - - - - ' -

1

~-------------------------~

-}--o QC

DC 0>------'-1

~-------------------------~
DD o>------J...
..l.....o QD
1
L _________________________ 1
~

Definition of Parameters
~tcw

tCWL -

V-

CK
Io-tSD- tHD ....
D

.... tpd.....
Q

Pa e 12-11

2-169

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Non-SCAN 4-bit DFF with CLEAR

FDR
Cell Symbol

Pro~agation

to
2.64
DA

(r

-

DC

tup'
KCL
0.16

-

to
3.62
2.18

I UHB Version
~ Number of BC

I

Delay Parameter
tdn
KCL
KCL2 CDR2
0.08
0.08

26
Path
CK -+ Q
CL -+ Q

IDf
-QA
-QB
-QC
-QD

CK -

J

Symbol
tCW
tCWH

Typ(ns)*
4.0
4.0

Data Setup Time
Data Hold Time

tSD
tHD

1.1
2.8

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM
tINH

4.0
1.5
4.5

Parameter
Clock Pulse Width
Clock Pause Time

Pin Name
D
CK
CL

Input Loading
Factor (tu)
1
1
1

Pin Name
Q

Output Driving
Factor (tu)
18
• Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
CK
X

t
t

Inputs
D
X
L

H

CL

Output
Q

L
H
H

L
L
H

UHB-FDR-E4 I Sheet 1/3 I

2-170

I Page 12-12

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

FDR
Equivalent Circuit

r-------------------------,

I

CKO

XCKO

-L.

-1....

CLO

DAo-----r-i
I
I
I

CK~:
v

XCKO

~I
I

XCKO ,

I

CLO

I

I

I

CL~~ ______ ~K~ _________ X~K~ ______ ~
DB 0

'

I

...L.oQB
I

~-------------------------~

DC

O"~-----'-:

-{-o QC

~-------------------------~
DDO------'...L.oQD
IL _________________________

I

~

Pa e 12-13

2-171

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

FDR
Definition of Parameters

1) tCW. tCWH. tSD' tHD' and tpd (CK+QA-QD)
tcw
CK

D

QA-QD

2)

tLW' tREM. tINH and tpd
tcw
tv

tLW
CL
tpd
QA-QD

...... .......

UHB-FDR-E4

2-172

tREM

SS
SS

tINH

SS
SS··········· .

Pa e 12-14

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name -' Function
FDS
Cell Svmbol

I "UHB" Version

J Number of BC

I

Non-SCAN 4-bit DFF

Propaltation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
3.03
0.16
0.09
2.45

20
Path
CK .. Q

DA DB DC DD

CK

u~

QB
QC
QD

Parameter
Clock Pulse Width
Clock Pause Time
Data Setup Time
Data Hold Time
Pin Name
D
CK

Pin Name
Q

Symbol
tCW
tCWH

TypJns1*
4.0
4.0

tSD
tHD

1.1
2.5

Input Loading
Factor (Lu)
2
1

Output Driving
Factor (Lu)
18
* Minimum values for the typical operating condition.
The values for the worst case operating condition
are Itiven bv the maximum delay multiplier.

Function Table
Inputs

Outputs

CK

D

Q

t
t

L

L

H

H

UHB-FDS-E3 I Sheet 1/2 I

I Palte 12-15

2-173

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
FDS

UHB

Version

Equivalent Circuit

r----·---------~--------,

ICLK
I -L

XCLK

-L .-----i

)()----..--oQA

I

DAo-------------

MI

I

II
CK~

. LLK

I

IXCLK

CLK

I

XCLK

XCLK

CLK

-L

-L
I

XCLK

I

f- ~ - - - - - - - - - - - - - - - - - - - - - _--;--l_oQB
DBO~----------~

I
I

f- - - - - - - - - - - - - - - - - - - - - - - _--;--l_oQC
DCO~----------~

f- - - - - - - - - - - - - - - - - - - - - - -

_--;--l_oQD

DDO~----------~I
I
IL _______________________

I

~

Definition of Parameters

CK
DA-DD

QA-QD

UHB-FDS-E3

2-174

Pa e 12-16

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I Non-SCAN Power DFF

FD2
Cell Svmbol

I

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.08
1. 65
1.72
0.05
0.10
7
2.55
0.08
2.34
0.04
0.07
7

7

Path
CK ... Q
CK ... XQ

DU'
CK

XQ

Parameter
Clock Pulse Width
Clock Pause Time
Data Setup Time
Data Hold Time

Symbol
tCW
tCW

Typ(ns)*
4.0
4.0

tSD
tHD

1.1
2.4

Input Loading
Factor (R.u)
2

Pin Name
D
CK

1

Output Driving
Factor (R.u)
36
36

Pin Name
Q
XQ

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are ,given by the maximum delay multiplier.
Function Table
Inputs
CK
D

,,

~El2-E3

Outputs
XQ
Q

H

H

L

L

L

H

I Sheet 1/2 I

Page 12-17

2-175

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
FD2

UHB

Version

Equivalent Circuit

CKe

XCKO

--L

--L

Q
XQ

D

T

T

XCKO

CKO
CKO

XCKO

--L

--L

TCKO

T

XCKO

CK o---I)o-r!)o--XCKO

. L

CKO

Definition of Parameters
-tcw

tCWL -

V-

CK
- t S D - tHD'"
D

10- tpd-

Q,XQ

UHB-FD2-E3

2-176

Pa e 12-18

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Non-SCAN Power DFF with Preset

FD3
Cell Symbol

Pro~agation

tup
to
1.71
2.80
2.39

PR

XCL
0.06
0.06
0.06

to
1. 73
2.50
0.91

I "UHB" Version
I Number of BC

I

Delay Parameter
tdn
XCL2 CDR2
XCL
0.04
0.10
7
0.04
0.07
7
0.07
0.04
7

8

Path
CX .. Q
CX .. XQ
PR .. Q.XQ

'=0='
CK

XQ

Symbol
tCW
tCWL

Typ(ns)*
4.0
4.0

Data Setup Time
Data Hold Time

tSD
tHD

2.1
1.5

Preset Pulse Width
Preset Release Time
Preset Hold Time

tPW
tREM
tINH

4.0
0.3
3.8

Parameter
Clock Pulse Width
Clock Pause Time

Input Loading
Factor (tu)
2

Pin Name
D
CX
PR

1

2
Output Driving
Factor (tu)
36
36

Pin Name
Q

XQ

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay mul tiplier.

Function Table
PH
L
H
H

Inputs
CK

X

+
+

Outputs
D

Q

XQ

X

H
H
L

L
L
H

H
L

UHB-FD3-E2 I Sheet 1/2 I

I Page 12-19

2-177

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
FD3

UHB Version

Equivalent Circuit
PR
XCKO

CKO

l

l

r-~--------~ X~--~Q

I>---t---I )O-------oXQ
D

xeKO

l
IXeKO

cx~cxo
XeKO

Definition of Parameters
o--tcw

eK

'~=r

- t S D - tHIJ-4
D

io-tpd -

Q,XQ
i'-tREM ...
PR
PR

-tINH-

tpw

Q,XQ

UHB-FD3-E2

2-178

Pa e 12-20

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name J Function

I

FD4
Cell Symbol

Non-SCAN Power DFF with

PR

DCK---<

f---

I Number of BC

I

~lear and Preset
Pro~agation Delay

tup
to
1. 90
2.81
2.41
2.49

i UHB Version

KCL
0.01
0.06
0.06
0.01

to
1.12
2.12
1.46
0.92

Parameter
tdn
KCL2 CDR2
KCL
1
0.10
0.05
0.01
0.04
7
0.10
7
0.05
0.07
0.04
7

9
Path
CK .. Q
CK .. XQ
CL .. Q.XQ
PR .. Q.XQ

Q

P--XQ
CL
Parameter
Clock Pulse Width
Clock Pause Time

Input Loading
Factor (.tu)
2
1
2
2

Pin Name
D
CK
CL
PR

Output Driving
Factor (.tu)
36
36

Pin Name

Q
XQ

Symbol
tCW
tCWL

Typ(ns
4.0
4.0

Data Setup Time
Data Hold Time

tSD
tHD

2.1
1.5

Preset Pulse Width
Preset Release Time
Preset Hold Time

tPW
tREI1
tINH

4.0
0.3
3.8

Clear Palse Width
Clear Release Time
Clear Hold Time

tLW
tREM
tINH

4.0
0.9
3.3

*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are ~iven by the maximum delay multiplier.

Function Table
Outputs

In~uts

PR

CL

L

H
L
H
H

H
H
H

CK

D

Q

XQ

X
X

X
X

H
L
H
L

L
H
L
H

••

UHB-FD4-E2 I Sheet lL2 J

H
L

-,

I PaJ!:e 12-21

2-179

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
FD4

UHB

Version

Equivalent Circuit
PRo---~--------------~

XCKO

,..---r-----i X>---<>Q

-L
D

XQ

T

CKO

XCKO
CKO

XCKO

-L

-L

T

T

XCKO

CKO

~~

CL

"'---------XCKO

Definition of Parameters

I>--

tcw

:CKO

tCWL

--I

V-

CK
10- tSD- tJID"'

D

io-tpd .....

Q,XQ
I

I'-tREM ...

PR

!O--tINH .....

CL

PR
CL

Q,XQ
UHB-FD4-E2

2-180

Pa e 12-22

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I
I Non-SCAN Power DFF with CLEAR
Pro aRation Delay Parameter

FDS
Cell Symbol

tUIl
to
KCL
1.88
0.08
2.S7
0.08
2.36
0.08
DCK--<

-

to
1.71
2.57
l.S2

tdn
KCL
O.OS
0.04
O.OS

KCL2
0.10
0.07
0.10

CDR2
7
7
7

8
Path
CK .. Q
CK .. XQ
CL .. Q.XQ

r-Q
P--XQ

I

CL

Parameter
Clock Pulse Width
Clock Pause Time

Input Loading
Factor (lu)
2

Pin Name
D
CK
CL

Symbol
tCW
tCWL

Typ(ns)*
4.0
4.0

Data Setup Time
Data Hold Time

tSD
tHD

1.1
2.4

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM
tINH

4.0
l.S
4.S

1

2
Output Driving
Factor (lu)
36
36

Pin Name

Q
XQ

• Minimum values for the typical operating condition.
The values for the worst case operating condition
are Riven by the maximum delaY multiplier.
Function Table
CL

Inputs
CK

L

X

H
H

+
+

D

Out uts
XO
0

X

L

H

H

H

L

L

L

H

UHB-FDS-E4 I Sheet 1/2 I

I Page 12-23
2-181

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

UHB

Version

FD5
Equivalent Circuit

CKO

XCKO

-L .---------1 .",.,----vQ

-L

XQ

D

I

I

~XCKOCKO
CK

XCKO

L

r

CKO
CL
Definition of Parameters

CK

I'-tcw

tCWL~

It-tSD'" ...tHD •

D

I'-tpd -<

Q.XQ

-

CL

Q.XQ
CL

Io--tINH t-- tLW

I;-

f-tpd - -

I
X tREM

r

UHB';'FD5-E4

2-182

Pa e 12-24

I "UHB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

Power
with Clear I
I Non-SCAN Positive edge clocked
Propagation Delay Parameter

FJD
Cell Symbol

JKFF

tup
to
4.40
4.43
2.40

J

CK
K

KCL
0.08
0.08
0.08

to
2.96
2.48
1.29

tdn
KCL
0.05
0.05
0.05

KCL2
0.08
0.08
0.08

CDR2
7
7
7

12
Path
CK .. Q
CK .. XQ
CL .. Q.XQ

=1J=:,
r.L

Parameter
Clock Pulse Width
Clock Pause Time

Input Loading
Factor (tu)
2
1
1

Pin Name
CL
J

K
CK

Symbol
tCW
tCWH

Typ(ns)*
5.6
5.6

J K Setup Time
J K Hold Time

tSD
tHD

2.5
1.2

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM
tINH

4.0
2.5
4.5

1

Output Driving
Factor (tu)
36
36

Pin Name
Q
XQ

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
Inputs
CL

CK

J

L
H
H

X

X
L
L

H
H

+
+
+
+

H

H

Outputs

XQ

K

0

X

L

H

L
H
L
H

Qo

XQo

L
H

H
L

XQ.

Qo

UHB-FJD-E3 I Sheet 1/2 I

I Page 12-25

2-183

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name
FJD

Equivalent Circuit

J

K

XQ

CK

CL

Q

Definition of Parameters

CK

-------.

I--tcw

tCWH

---0

r----I'-tSD .... tllD •

J,K

!O-tpd-

Q,XQ

CL

I-- tINH
I-- r-- tLW

---0

r-

<-- I-tpd ~

Q,XQ

tHIB-FJD-E2

2-184

Pa e 12-26

UHB Series Unit Cell Ubrary

CMOS Channeled Gate Arrays

Binary Counter Family
Basic
Cells

Page

Un" Cell
Name

2-187

SC7

Scan 4-bit Synchronous Binary
Up Counter with Parallel Load

62

2-192

sea

Scan 4-bit Synchronous Binary
Down Counter with Parallel Load

66

2-197

C11

Non-Scan Flip-flop for Counter

11

2-199

C41

Non-Scan 4-bit Binary Asynchronous Counter

24

2-202

C42

Non-Scan 4-bit Binary Synchronous Counter

32

2-205

C43

Non-Scan 4-bit Binary Synchronous Up Counter

48

2-209

C45

Non-Scan Binary Synchronous Up Counter

48

2-213

C47

Non-Scan Binary Synchronous Up/Down Counter

68

Function

2-185

UH8 Series Unit Cell Ubrary

2-186

CMOS Channeled Gate Arrays

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB" Version
Cell Name I Function
I Number of BC
SCAN 4-bit Synchronous Binary
SC7
Up Counter with Parallel Load
62
Cell Svmbol
Propagation Delav Parameter
tup
tdn
to
KCL
to
KCL
Path
KCL2 CDR2
3.30
0.08
3.05
0.06
0.15
7
CK,IH'" Q
5.78
0.08
5.34
0.06
0.15
7
CK,IH'" XQ
7.80
0.08
5.23
0.04
CK,IH'" CO
DA2.00
0.08
1.00
0.04
CI ... CO
-QA
DB :>-XQA
DC -QB
DD :>-- XQB
CK-QC
IH:>-- XQC
-QD
L --<
Parameter
Symbol
Typ(ns)*
CI :>-- XQD
tCW
7.2
Clock Pulse Width
EN -CO
7.2
Clock Pause Time
tCWH
SI A Data Setup Time
tSD
2.0
B --<
Data Hold Time
tHD
3.3

I

I

-

-

Pin Name
D
CK
IH
L
CI
EN
S1
A,B

Input Loading
Factor (Rou)
1
1
1
1
2
1
1
1

Pin Name
Q
XQ
CO

Output Driving
Factor (Rou)
36
36
36

UHB-SC7-E2 I Sheet 1/5 I

Load Setup Time
Load Hold Time

tSL
tHL

6.3
3.6

CI Setuo Time
CI Hold Time

tSC
tHC

7.2
2.7

EN Setup Time
EN Hold Time

tSE
tHE

7.2
2.7

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are .e:iven bv the maximum delay multiplier.

Page 13-1

2-187

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
SC7

UHB

Version

Equivalent Circuit

DA

QA XQA

DB

QB XQB

DC

QC XQC

DD

QD XQD

XCKI

CKI
LDI
XLDI
XAI

AI

XBI
BI

SI

EN
CI
CO

C~CKI

AO-[>o

~XCKI
L 0>-------1[>0

~

LDI

Lt>o-- XLDI

UHB-SC7-E2

2-188

~XAI

Lt>o--AI
BO_[>o

~BI

Lt>o--XBI

Pa e 13-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
SC7

UHB

Version

Equivalent Circuit (FFu)

Q
D

XQ
BI

XCKI

I

XLDI

XAI

XCKI

-L

-L-L

I

II

CKI

QO

AI

S

AI

CKI

XAI

I

XBI

XTG o-+--------+-l X>---+

Pa e 13-3

2-189

UHB

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

Version

Cell Name

SC7
Function
Load

u

L

DA
DB
Data
Input

DC
DD

Clock CK+IH
Enable

EN
I

Data
Output

L-J

II

Carry in CI
QA

IL.J1J"L...JU

QB

~

.QC

I

QD

n

CO

Mode
Inhibit

UHB-SC7-E2

2-190

Load

Count

Inhibit

Pa e .13-4

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SC7
I

I

UHB

Version

Definitions of Parameters
i) Clock Mode
Clock

Data

L

CI

----""'I.

Io-tSD .... l--tHD-

_t=tSL~'HL=r_-

-Ftse-+i__________

EN

UHB-SC7-E2 I Sheet 5/5 I

I

P~e

13-5

2-191

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
"UHB Version
Cell Name I Function
I Number of BC
SCAN 4 bit Synchronous Binary
SCB
Down Counter with Parallel Load
66
Cell Symbol
ProJ:agation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
3.37
0.07
3.1B
0.06
0.13
7
CK,IH'" Q
4.40
0.06
4.32
0.04
CK,IH'" XQ
6.41
B.37
0.04
CK,IH ... BO
O.OB
DA 0.04
1.49
O.OB
2.27
BI ... BO
f--QA
DB P-XQA
DC f--QB
DD P-XQB
CKf--QC
IHP-XQC
L --<:
f--QD
Parameter
Symbol
Typ(nsJ*
BI - C
P-XQD
Clock Pulse Width
tCW
6.B
EN - C
6.B
Clock Pause Time
tCWH
SI P-BO
A Data Setup Time
tSD
2.0
B -C
tHD
3.3
Data Hold Time

I

I

Pin Name
D
CK
IH
L
BI
EN
SI
A,B

Input Loading
Factor (J1.u)
1
1
1
1
2
1
1
1

Pin Name
Q
XQ
BO

Output Driving
Factor (iu)
36
36
36

UHB-SCB-E2 I Sheet 1/5 I

2-192

Load Setup Time
Load Hold Time

tSL
tHL

6.3
3.6

EN Set1!P Time
EN Hold Time

tSE
tHE

B.1
loB

B1 Setup Time
BI Hold Time

tSB
tHB

B.1
loB

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiplier.

I Pa,l!:e 13-6

FUJITSU

C~OS

GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

sca
Equivalent Circuit

51

EN
BI

CTV--CKI
L[>o-t>o--XCKI
L

o----..,~ ~

LDI

~XLDI

AO>---~ ~XAI

~AI
BO>---~ ~BI

~XBI

Pa'e 13-7

2-193

FUJITSU
Cell Name
SC8

C~OS

GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Equivalent Circuit (FFu)
V2B

V2B

Q

D

XQ
XQO

XAI

XCKI

AI

..l

..l..l

I

II

XS

AI

CKI

XAI

I

XBI

XTG

o-+--------+--i

UHB-SC8-E2

2-194

X>---t

Pa e 13-8

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cel1 Name
sca

UHB

Version

Function
Load

u

L
DA
DB

Data
Input

DC
DD

Clock

CK+IH

Enable

EN

:I~----------------------~

Carry in BI
QA
QB
Data
Output

---+--'~
~'-----

QC
QD
BO

LJ

Mode
Inhibit

Load

Count down

Inhibit

Pa e 13-9

2-195

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
SC8

UHB

Version

Definitions of Parameters
i) Clock Mode
Clock

Data

tcw

tCWH

tSD

tHD

L

EN

BI

UHB-SC8-E2

2-196

Pa e 13-10

I UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I
I Non-SCAN Flip-Flop for Counter
Propagation Delay Parameter

Cll
Cell Symbol

tup
to
1.90
2.53
2.62

KCL
0.16
0.16
0.16

to
1. 75
2.97
1.73

tdn
KCL
XCL2
0.10
0.10
0.10

CDR2

11

Path
CX .. Q
CX .. XQ
CL .. Q.XQ

r---

DL-

~Q

CK TG -

P--XQ

CL

Pin Name
L
TG
CL
D.CX

Symbol
tCW
tCIr.'H

Typ(ns)*
4.0
4.2

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM
tINH

4.0
1.0
0.5

Input Loading
Factor (Lu)
2
2

Load Setup Time
Load Hold Time

(CX)
CK

tSL
tHL

2.3
0.5

2
1

Data Setup Time
Data Hold Time

(CX)
(CX)

tSD
tHD

2.5
0.5

TG Setup Time
TG Hold Time

CX)
(CX)

tST
tNT

2.9
0.0

Output Driving
Factor (Lu)

Pin Name

Parameter
Clock Pulse Width
Clock Pause Time

Q
XQ

18
18

* Hinimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
L

0

'I'G

CL

CK

X

X

X

L

X

L

H

H

X

H

t

H

H

L

X

H

t

L

L

X

L

H

t

Q(Qo)

L

X

H

H

t

Q(Qo)

tJHB-Cll-E3 I Sheet 1/2 I

Q(Qo)

I Page 13-11

2-197

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name
Cll
Equivalent Circuit

XLO

CL

-L
Q
D

XQ

LO

ICKO

I

XCKO

CL

TG 0--+-+1

C<~=

XCKO

Lt:

Definition of Parameters
tCWH

CK
CL

tREM

tiNH

CL
t
L
tSD

tIlL
tHD

D
tJIT

Pa e 13-12

2-198

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

Counter
I Non-SCAN 4-bit Binary Asynchronous
I
ProJ:agation Delav Parameter

C41
Cell Symbol

tup
to
2.00
3.67
5.13
6.60

-QA
-QB
-QC
-QD

-

KCL
0.14
0.14
0.14
0.14

-

to
1.86
3.28
4.75
6.20
4.19

tdn
KCL
KCL2
0.10
0.10
0.10
0.10
0.10
-

-

24

CDR2

Path
CK ... QA
CK ... QB
CK ... QC
CK ... QD
CL ... Q

-

-

-

CK -

CL

Pin Name
CK
CL

Input Loading
Factor (R.u)
1
1

Pin Name
Q

Output Driving
Factor (R.u)
18

Parameter
Clock Pulse Width
Clock Pause Time

Symbol
tCW
tCIYll

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM

Typ(ns)'~

4.3
4.6
3.9
2.1
6.7

tINH

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are .e:iven bv the maximum delay multiplier.

Function Table
InJ:uts
CL
eK
H
L

t
X

Outputs
Q
Count up
L

UHB-C41-E2 I Sheet 1/3 I

J

Pa.e:e 13-13

2-199

FUJITSU
Cell Name
C41

C~OS

GATE ARRAY UNIT CELL SPECIFICATION

Equivalent
Circuit

QA

UHB

QB

Version

QD

QC

CKO
FTO

FTO

FTO

FTO

XCKO

CLO
CL

o-{>o-{)o- CLO

CK~CKO

L- XCKO

v
FTO (Flip-Flop for Counter) (not Unit Cell)
Symbol
CKO
XCKO

8

Function Table
Q

CLO

CKO

Q

QO

L

X

L

XQO

H

t

Qn-l

CLO

CLO

Q

QO

I

I

XCKO

CKO
XCKO

CKO

-L

-L

ICKO

I

XCKO

~----------------------------~-----o

UHB-C41-E2

2-200

CLO
XQO

Pap;e 13-14

FUJITSU

C~OS

GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

C41
Definition of Parameters

CK

CL

I Page

13-15

I

2-201

I "UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

Counter
I Non-SCAN 4-bit Binary. Synchronous
I
Propaution Delay Parameter

C42
Cell Symbol

tup
to
3.18

-

XCL
0.14

-

to
2.34
3.36

tdn
XCL2
XCL
0.12
0.09
0.09
0.12

CDR2
4
4

32
Path
CX .. Q
CL .. Q

r--

r-QA
r-QB
r-QC
r-QD
CX -

CL

Pin Name
CL
CX

Pin Name
Q

Input Loading
Factor (iu)

Parameter
Clock Pulse Width
Clock Pause Time

Symbol
tCW
tCWH

Typ(ns)i'
4.3
4.6

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM
tINH

4.0
2.1
6.7

1
1

Output Driving
Factor (lu)
18

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
Inputs
CL
CX
H

L

+

X

Outputs
Q

Count up
L

UHB-C42-E3 I Sheet 1j31

2-202

Pa£e 13-16

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
C42
Equivalent
Circuit

QA

CKO

UHB

QB

CKO

Version

QD

QC

CKO

CKO

XCKO

CLO

. . XCKO
CK

o----{)o--+---'[)o--

CKO

FT2 (Flip-Flop for Counter)(not Unit Cell)
Function Table
Inputs
CKO

Q

XCKO
QO

XTG

Output

CLO

XTG

CKO

L

X

X

H
H

Q(QO}

L

H

,

Qn-l

L

t

Qn-l

CLO

UHB-C42-E3

Pa e 13-17

2-203

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name
C42
Equivalent Circuit of FT2

CLO
CKO

XCKO

Q

-L

QO

CLO
CKO

XCKO

I

CKO

XTG

CKO

-L
I

XCKO

0---+---+--1

Definition of Parameters
tcw --'1-- tCWH

CK

CL

UHB-C42-E3

2-204

~~-­
~......-+-----~~

tINH

--'1""-

Pa e 13-18

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

Up Counter
I Non-SCAN 4-bit Binary Synchronous
Propagation Delav Parameter

C43
Cell Svmbol

tup
to
2.96
5.60
1.60

-

-

r---

DADB DC DDL --<
CKENCI -

I--QA
f--QB
f--QC
f--QD

Input Loading
Factor (lu)
1
1

1
2
Output Dr! ving
Factor (lu)
18
18

Pin Name
Q
CO

-

to
2.40
3.56
0.81
3.88
2.64

tdn
KCL
KCL2
0.09
0.08
0.08
0.09
0.08

CDR2

48
Path
CK ... Q
CK ... CO
CI ... CO
CL'" Q
CL ... CO

f--CO

CL

Pin Name
D
L,EN
CK,CL
CI

KCL
0.16
0.16
0.16

j

Parameter
Clock Pulse Width
Clock Pause Time
Data Setup Time
Data Hold Time
Load Setup Time
Load Hold Time
CI Setull Time
CI Hold Tillie
EN Setup Time
EN Hold Time
Clear Pulse Width
Clear Release Time
Clear Hold Time

Symbol
tCW
tCWH
tSD
tHD
tSL
tHL
tSC
tHC
tSE
tHE
tLW
tREM
tINH

TV'P'ns
4.7
6.7
2.6
2.9
4.4
1.3
4.3
0.9
4.3
0.9
5.6

*

1.9

8.3

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay_multiplier.

Function Table
Im:uts
D
EN

CL

L

L
H
H
H
H
H

X

X

L
L
H
H
H

H
L

Note

:

X
X
X

X
X
X
X

L
H

Outputs
CI

CK

Q

X
X
X

X

L
X

X
X

H

t

L
H
L
No Counting
No Counting
Count up

t
t

The CO output produces a high level
output data when the counter overflows.

UHB-C43-E3 I Sheet 1/4 I

I Page 13-19

2-205

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

C43
Equivalent Circuit
DA

QA

DB

....
FT3

CKOXCKO~

"'"-

r-

LOXLO-C

FT3

CKO-

r-

XCKO-C

g:vf" Jo

QC

DC

"'"-

r-

LOXLO~

QB

r<

FT3

r-

LOXLO-C

CKO-

CKO-

~

r- XCKO-C

r<

r<

f- XCKO

QD

"'"-

r-

LOXLO~

DD

FT3

r-

CI

Jo

EN

r-

Jo
r-r-

Jo
r~
L-r'"

~

4>
CL

o---{>o----

L

UHB-C43-E3

2-206

CO

'-'

CLO

LO

XCKO

XLO

CKO

Pa e 13-20

FUJITSU CMOS GATE ARRAYA UNIT CELL SPECIFICATION

UHB

Version

Cell Name

C43
. FT3 (Flip-Flop for Counter)(not Unit Cell)
Function Table
D

LO

LO

CK

XLO
CKO

XTGO

CLO

X

X

X

L

H

X
X
X

H

H
H

L
L

H

H
I.

L
L

t
t
t
t

L
X
X

L

XCKO

Q(QO)

D

Q

L

L
Q(QO)
Q(QO)

XTGO

CLO
Equivalent Circuit of FT3

CLO

XLO

-.L
Q

D

LO

QO
O~--------~

CKa

XTGa

XCKa

0--++...,

UHB-C43-E3

Pa e 13-21

2-207

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

C43
Definition of Parameters

,~-~~;i
))
I
II

G'lNH=r-

L

Ir-----~--------------

CI

I~----~--------------

EN

UHB-C43-E3

2-208

~----~--------------

I Page

13-22

I

I "UMB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I FlUlction

Up COlUlter
I Non-SCAN 4-bit Binary Synchronous
I
Propagation Delav Parameter

C45
Cell Svmbol

tU1)
to
2.67
5.07
1.91

KCL
0.14
0.17
0.17

to
1. 87

2.82
1.36

tdn
KCL
KCL2
0.09
0.13
0.09
0.09

CDR2
4

48
Path
CK .... Q
CK .... CO
CI .... CO

,--

DADB DC DD L ---c
CK EN CI -

~QA
~QB
~QC
~QD

~CO

CL

Input Loading
Factor (R.u)
1
1
1
2

Pin Name
D
L,EN
CK,CL
CI

Parameter
Clock Pulse Width
Clock Pause Time
Data Setup Time
Data Hold Time
Load Setu1) Time
Load Hold Time
CI Setup Time
CI Hold Time
EN Setup Time
EN Hold Time
Clear Setup Time
Clear Hold Time

Symbol
tCW
tCWH
tSD
tHD
tSL
tHL
tSC
tHC
tSE
tHE
tSR
tHR

Typ(ns)''<
4.0
4.6
3.8
2.1
5.0
2.1
6.6
1.9
6.6
1.9
3.8
2.0

Output Driving
Factor (R.u)
18

Pin Name
Q
CO

18

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
Inputs
D
EN

CL

L

L
H
H
H
H
H

X

X

L
L
H
H
H

H
L
X
X
X

CI

CK

X
X
X
X

X
X
X

+
+
+

L
H

X

X
X

H

+

L

Outputs
Q
L
H
L
No Counting
No Counting
Count up

Note : The CO output produces a high level
output data when the cOlUlter overflows.

UHB-C45-E1 I Sheet 1/4 J

I Page 13-23

2-209

FUJITSU
Cell Name
C45

cnos GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Equivalent Circuit
DA

QA

"-

LO-

t-

IT!

XLO-<:

DC

QC

"-

~

LOXLO-(

QB

DB

tIT!

tIT!

LOXLO-(

CKO-

CKO-

CKO-

CKO-

XCKO -<:

t- XCKO-<:

t- XCKO-(

t- XCKO-(

~~r

r<

r<

r<

CI

EN

Jo

1

Jo
r

tIT!
t-

Jo

CLO

r-r-

QD

"-

LOXLO-(

DD

~
--....

~

LV
CL

o----{>o---

L

UHB-C45-E1

2-210

CO

'--'

CLO

LO

XCKO

XLO

CKO

Pa e 13-24

FUJITSU CMOS GATE ARRAYA UNIT CELL SPECIFICATION

UHB

Version

Cell Name
C45
. FTl (Flip-Flop for Counter)(not Unit Cell)
Function Table
D

LO

LO

Q

XLO
CKO

QO

XCKO
XTGO

L
H
H
L
L

D

XTGO

CLO

CK

Q(QO)

X

X
X
X

H
L

L
H

H
L

L
L

t
t
t
t
t

H

L
X
X

L

L
Q(QO)
Q(QO)

CLO
Equivalent Circuit of FT3
CLOo---------------~

XLO

-L
Q

D

LO

QO
O----------~

I

CKO

XTGO

I

XCKO

0--++--1

UHB-C45-EI

Pa e 13-25

2-211

FUJITSU CMOS GATE ARRAY UNIT CELL PECIFICATION

UHB

Version

Cell Name
C45
Definition of Parameters

ex

tcw

----of- tCWH

tSD
D

CL

L

CI
EN

UHB-C45-E1

2-212

Pa e 13-26

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name J Function
C47
Cell Symbol

I "UHB" Version
I Number of BC

I

Non-SCAN 4-bit Binary Synchronous Up/Down Counter
Propagation Delay Parameter
tup
tdn
KCL
to
KCL
KCL2 CDR2
to
3.59
0.16
0.25
4
3.99
0.16
5.41
6.12
0.08
0.11
5.54
4
0.25
5.01
0.16
0.16
0.08
2.47
0.11
3.01

.-DADB DC DDL --<
CKEN --<
DU-

68
Path
CK -+ Q
CK -+ CO
L-+Q
DU -+ CO

r--QA
r--- QB
r--- QC
r--- QD

P--- CO

-

Parameter
Clock Pulse Width
Clock Pause Time

Input Loading
Factor Clu)

Pin Name
D
L
DU
CK
EN

1

Symbol
tCW
tCWH

Typ(ns)*
5.6
8.9

Data Setup Time
Data Hold Time

tSD
tHO

0.7
1.8

DU Setup Time
DU Hold Time

tSU
tHU

5.3
0.8

EN Setup Time
EN Hold Time

tSE
tHE

5.0
1.2

2
1
I

3
Clear Release Time
tREH
2.3
11.1
Output Driving Clear Hold Time
tINH
Factor Clu)
tLW
4.6
Load Pulse Width
18
18
* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Pin Name
Q

CO

Function Table
0

L

H
L

L
L

X
X
X

H
H
H

Inputs
EN
DU
X
X
H
L
L

X
X
X
L
H

Outputs
CK
X
X

t

+
+

J
I

H

!

L

No Counting
Count Up
Count Down

Note : The CO output produces a low level output
pulse when the counter overflows or underflows.

UHB-C47-E2 I Sheet 1/4 I

I Page 13-27

2-213

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
C47
Equivalent Circuit

-

UHB

Version

""'"
.....-

CO

rDU

Y>oEN

L./

DA 0-:-:-LO-

;&-

-=v-

CKO- FT7
XCKO -{

CKO
0

QA

-

~J

I-

~
I

XCKO

r---

r--QB

LO-

CKO- FT7
CKO-{
I--

"-1
r---

I
I

DC

QC

0--

LOCKO - FT7
XCKO -{

I

r-

L..-

,-----r"

I--

"-~
r---

DD

QD

0-LO-

CKO- FT7
XCKO -{

r--

L-t-

J

UHB-C47-E2

2-214

Pa e 13-28

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

UHB

Version

C47

• FT7 (Flip-Flop for Counter)(not Unit Cell)

Function Table
In! uts

L~EQ

Out[luts

LO

D

TGO

CKO

QO(Q)

H

H

X

X

H

L

H

L

X

X

L

H

L

X

L

t

Qn-l

Qn-l

L

X

H

t

Qn-l

Qn-l

Q(QO)

FT7

CKO
XCKO
TGO

QO
XQO

Equivalent Circuit of FT7

r------------------------oXQO
t - - - - - - - { )O-------oQ

I
XCKO

I
XCKO

CKO

CKO

--L

--L
XDO
LO

DO
LO

CKO

XCKO

TGO o-f--+-i )0---;

D~DO
v

L- XDO
Pa c 13-29

2-215

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
C47

UHB

Version

Definition of Parameters

CK

tcw

~~

D

~~
~~

L

~~

EN

tSE

tsu
DU

UHB-C47-E2

2-216

tCWH

tHE

tINH

~)~

tHU

~~

Pa e 13-30

CMOS Channeled Gate Arrays

UHB Series Unit Cell UbralY

Adder Family
Basic
Cells

Page

Un" Cell
Name

2-219

A1A

1-bit HaH Adder

2-220

A1N

1-bit Full Adder

8

2-221

A2N

2-bit Full Adder

16

2-223

A4H

4-bit Binary Full Adder with Fast Carry

48

Function

5

2-217

UHB Series Unit Cell LibrB!}'

2-218

CMOS Channeled Gale Anays

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I I-bit Half Adder

AlA
Cell Svmbol

A

Input Loading
Factor (R.u)
2

B

2

I

Symbol

5

Path
A ... S

B ... S
A ... CO

B ... CO

Typ(ns)*

Output Driving
Factor (R.u)

Pin Name
CO

36
36

S

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiplier.
Equivalent Circuit

Function Table
A

B

CO

s

L
L
H
H

L
H
L
H

L
L
L
H

L
H
H
L

LSheet

1/1

UHB-AlA-E2

I Number of BC

Propagation Delay Parameter
tup
tdn
KCL
to
KCL
KCL2 CDR2
to
1.22
0.08
1.44
0.04
1.09
0.08
1.46
0.04
1.12
0.08
1.25
0.04
1.27
0.08
1.15
0.04

Parameter

Pin Name

J UHB" Version

I

A
B

I Page 14-1

2-219

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
AIN

I I-bit Full Adder

...£ill Symbol

B-

I--CO

A-

I--S

J

I

Pro]:a2ation Delav Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
2.64
0.16
3.15
0.08
1.35
0.08
1.25
0.16
2.98
0.16
2.38
0.08
1.02
0.16
1.17
0.08

Symbol

Parameter

Pin Name
A
B
CI

Input Loading
Factor (R.u)
3
3
3

Pin Name
CO
S

Output Driving
Factor (R.u)
18
18

*

Outputs

A

B

CI

S

CO

L

L
L

L
L
L
L

L
H
H

L
L
L

H

L
H

L
H

H
H

L
L
H
H

H
H
H
H

UHB-A1N-E2 I Sheet 1/1 L

2-220

Path
A,B .. S
CI .. S
A,B .. CO
CI .. CO

TypJns) *

Equivalent Circuit

Inputs

L

8

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table

H

I UHB Version
I Number of BC

L

H

H

L

L
L

H
H
H

H

A
B

I'""
II
11./

'""-

---tb

S

CI

~}-t>o-co
I

1../

I Page 14-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 2-bit Full Adder

A2N
Cell Svmbol

to
2.85
2.74
1.58
1.47
2.79
2.97
2.97
1.18
2.82
3.11
2.71
3.11
2.76

r--CO
r--52

r--51

J

I

Delay Parameter
tdn
to
KCL
KCL2 CDR2
2.81
0.14
2.87
0.14
1.36
0.09
0.12
4
1.36
0.09
0.12
4
0.14
2.58
2.75
0.14
2.75
0.14
1.19
0.14
0.14
2.75
0.14
2.95
2.81
0.14
0.14
2.95
0.14
2.52

Propa~ation

tUll

B2A2BlAl-

I UHB Version
I Number of BC

KCL
0.29
0.29
0.29
0.29
0.29
0.22
0.22
0.22
0.22
0.22
0.22
0.22
0.22

Svmbo1

Parameter

Pin Name
A,B
CI

Input Loading
Factor (Rou)
2
2

Pin Name
S
CO

Output Driving
Factor (Rou)
14
14

*

16
Path
Al ... CO
Bl ... CO
A2 ... CO
B2 ... CO
CI ... CO
Al ... 51
Bl .. 51
CI ... SI
A1 ... 52
A2 ... S2
Bl ... S2
B2 ... 52
CI ... 52
Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
Inputs
CI

=L

Outputs
CI

=H

Al

Bl

A2

B2

51

52

CO

Sl

S2

CO

L

H

L
L

H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L

L
L
L

H

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
L
L
L
H
L
L
L
H
H
H
H
H

H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H

L
H

L

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
L
L
L

L
H
L
H
L
H
L
H
L
H
L
H

UHB-A2N-E2 I 5heet 1/2 I

H
H
H
H
L
H
H
H
L
L
L
L
H

H
H
H
L
L
L
H
L
L
L
L
H
H
H

H
H
H
L
H
H
H
H
H
H
H

Page 14-3

2-221

FUJITSU CMOS GATE ARRAY
Cell Name
A2N

u~IT

CELL SPECIFICATION

UHB

Version

Equivalent Circuit

CO
A2

B2

S2

Al

B1
Sl
C1

UHB-A2N-E2

2-222

Pa e 14-4

J "UHB" Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Number of BC

I 4-bit

A4H
Cell Symbol

I

Binary Full Adder with Fast Carry
Propagation Delay Parameter
tup
tdn
to
to
KCL2 CDR2
KCL
KCL
1.18
0.22
1.63
0.14
2.65
0.29
3.07
0.14
0.14
3.03
0.29
2.98
-CO
3.14
0.29
3.54
0.14
-S4
2.87
0.16
3.21
0.08

B4 A4 B3 A3 B2 A2 B1 A1-

-S3
-S2
-Sl

I
CI

Pin Name
A
B
CI

Input Loading
Factor (R.u)
2
2
2

Pin Name
CO
Sl,S3,S4
S2

Output Driving
Factor (R.u)
18
14
18

Function Table

Al

B1

A2

B2

L
H
L
H
L
H
L
H
L
H
L
H
L

L
L
H

L
L
L
L
L

L
H
H

L
L
L
L
H
H
H
H
L
L
L
L

L
L

H
H

H

H
H

H
H

H
H

1\3- B3- 1\4- B4-

H

L
H

L
L
H
H

L

Path
CI -+
CI -+
CI -+
CI -+
CI -+

Sl
S2
S3
S4
CO

3.81
3.17
3.42
3.75
3.30

0.22
0.29
0.29
0.29
0.16

3.39
3.08
3.85
3.92
3.78

0.14
0.14
0.14
0.14
0.08

Al,Bl ... SI
A1,B1 -+ S2
A1,B1 -+ S3
A1,Bl ... S4
A1,Bl -+ CO

3.09
3.66
3.74
3.87

0.29
0.29
0.29
0.16

3.37
3.60
4.05
3.83

0.14
0.14
0.14
0.08

A2,B2
A2,B2
A2,B2
A2,B2

2.81
3.84
3.80

0.29
0.29
0.16

2.85
4.04
3.82

0.14
0.14
0.08

A3,B3 ... S3
A3,B3 .. S4
A3,B3 -+ CO

2.90
3.66

0.22
0.16

3.01
3.51

0.09
0.08

0.12

4

..
..
...
..

S2
S3
S4
CO

A4,B4 ... S4
A4,B4 ... CO

Note :
Input conditions at AI, A2,
OUTPUT
B1, B2 and CI are used to
determine outputs Sl and S2
CI
L
CI - H
-d ;; ii - -C2;; L - and the value of the interSl S2 C2
nal carry C2.
The values
Sl S2 C2
83- 84- CO- 83- 84- COat C2, A3, B3, A4 and B4
are then used to determine
outputs S3, 54 and CO.
L L L
H L L
H L L
L H L
H L L
L H L
L
H
H
L H L
H
H L
L H L
H
H
L
L L H
H
H
L
L L H
L L
H
H L H
L H L
H
H L
L H
H H L
L
L
L L H
H
H
L L
H
H L H
L L H
H
L H
H L H
L H H
H L H
L H H
L H H
H H H

=

INPUT

H

48

L
L

L
H
H
H

H
H

UHB-A4H-E3 I Sheet 1/2 I

I Page 14-5
2-223

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
A4H
I

UHB

I

Version

Equivalent
Circuit

" r------..

~"
~

CO

'---u

"
~

'u

p--

r--

B4

'u
r-..

H-J ri=k'

A4

D

..I""

I

pr

S4

V

~

B3]C

~

f-lJ
t- "
t-

t-

t-

~

IrV

~u

~

A3 cr--+-t7'

B2

L=" Ip-

~

t-

~

t-

s-.,

rl-bf

t-U

r-,

if

S3

~ ~

~

L-Us1:jd

A2

Vr--

f\

S2

I
u ~

Sl

~

I
L/

Bl

Al

CI~
UHB-A4H E3 I Sheet 2/2 I

2-224

W

t-

r-U

~

S=[V

I Page 14-6

UHB Series Unit Cell Ubrary

CMOS ChanneIBd Gate Arrays

Data Latch Family

Page

Unit Cell
Name

2-227

YL2

Data Latch with TM

5

2-229

YL4

Data Latch with TM

14

2-231

LTK

Data Latch

2-233

LTL

Data Latch with Clear

5

2-235

LTM

Data Latch with Clear

16

2-238

LT1

S-R Latch with Clear

2-240

LT4

Data Latch

Function

Basic
Cells

4

4
14

2-225

UHB Series Unit Cell Ubrary

2-226

CMOS Channeled Gate Arrays

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I I-bit Data Latch with

YL2
Cell Symbol

CK
IH
'I'M

I

'I'M

Propagation Delay Parameter
tup
tdn
KCL2 CDR2
KCL
to
to
KCL
0.04
2.73
0.08
2.81
0.08
0.04
1.16
1.28

D

D

I UHB Version
I Number of BC
5
Path
CK.IH ... Q
D ... Q

Q

Parameter

Symbol

Typ ns

Clock Pulse Width

tCW

6.8

Data Setup Time
Data Hold Time

tSD
tHD

3.2
2.5

*

Input Loading
Factor (iu)
2
1
1
1

Pin Name
D
CK
1H
'I'M

Output Driving
Factor (iu)
36

Pin Name

Q

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are d ven by the maximum de lay mul ti plier .

Note :
The 'I'M terminal must be kept LOW during the SCAN Mode.
Function Table
'I'M

L
H
H
H

Input
IH CK
X

H
X

L

X
X

H
L

D
D

Output
Q
D

X
X

Q.
Q.

D

D

trnB-YL2-E3 I Sheet 1/2 I

Mode
SCAN
LATCH

Page

15-1

2-227

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

B Version

Cell Name

YL2
Equivalent Circuit

:>0----0 Q

CKI

..L
D

I

XCKI

XCKI

..L
I
CKI

XCKI
eKI

Definitions of Parameters

ex

i'--- tew - - -

tSD
D

Q

UHB-YL2-E3

2-228

i

I

tHO
I
)j(

-tp~~

.II'

Pa e 15-2

I "UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 4-bit Data Latch with TK PrQl 8ltation Delay Parameter I

YL4
Cell Symbol

tup
to
ICCL
3.33 0.08
1.10 0.08
Dl D2 D3 D4 CIC -<
IH TK-<

to
3.43
1.29

tdn
ICCL2
ICCL
0.04
0.04

14

CDR2

Path
CIC.IH ," Q
D"Q

Symbol

Typ(ns)*

-Ql
-Q2
-Q3
-Q4

Parameter

Pin Name
D
CIC
IH
TK

Input Laadina
Factor. (lu)
2
1
1
1

Pin Name
Q

Output Drivina
Factor (1u)
36

Clock Pulse Width

(CIC)

tCW

7.2

Data Setu!) Time
Data Hold Time

(D)
(D)

tSD
tHD

1.8
4.0

* Minimum valuea for the tJPical operatina condition.
The value. for the wor.t ca.e operatina condition
are dven by the maximum delay multi1)Uer.
Note :
The TK terminal must be kept LOW durina the SCAN Kode.
Function Table
In~ut

TK

IH

CIC Dn

L

X

H
H

H

X
X

X

H

H

L

L
4

n '" 1 -

D

X
X

D

Output
Qn
D
Qno
Qno
D

UHB-YL4-E3 I Sheet 1/2 I

Kode
SCAN
LATCH

I Page 15-3

2-229

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

YL4
Equivalent Circuit

r----------------,

I

QI
CKI

-.L
Dl

I

XCKI

XCKI

D2

-.L

I
~------~~--------~
I
--r--o
C>---f
I
~----------------~

--r--o

I

D3

C>---f

Q3

1

~----------------~
D4

Q2

--r--o
I

I

<>---t-

Q4

L ______ ~---------J

, . . - - - - - _ XCKI

E~ Dv-Lf»-

CKI

Definitions of Parameters

CK

tcw

D

Q

UHB-YL4-E3

2-230

Pa e 15-4

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
LTK
Cel1 Symbol

D
G

I UHB Version
I Number of BC

I

Data Latch

Propagat:ion Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
1.03
0.16
0.08
1.15
1.45
0.16
1.63
0.08
1. 75
0.16
1.82
0.08
2.12
0.16
2.34
0.08

4
Path
D -fo Q
D -fo XQ

G -fo Q
G -fo XQ

u:
Parameter
G Input Pulse Width
Data Setup Time
Data Hold Time

Pin Name
D
G

Pin Name

Q
XQ

Symbol
tGW

Typ(ns)"<
4.0

tSD
tHD

1.6
2.3

Input Loading
Factor (.tu)
2
1

Output Driving
Factor (.tu)
18
18

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiplier.

Function Table
Inouts

Outputs

D

G

Q

X

H
L
L

Qo

XQo

H

L
H

H
L

L

XQ

UHB-LTK-E2 I Sheet: 1/2 I

Page 15-5

2-231

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
LTK

UHB

Version

Equivalent Circuit

Q

CO

-L
XQ

D

T

XCO

XCO

-L

T
CO
G

o---i>o-tI)o~

CO

Lxco

Definition of Parameters
(Casel)
G

D

tHD
Q,XQ

----~---------------JI

(Case2)
o..tSD
G

,..--

D

Q,XQ

UHB-LTK-E2

2-232

"---

I

r-

tpd Pa e 15-6

I nUHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I I-bit Data Latch with ClearPropagation Delay Parameter I

LTL
Cell Symbol

tup
to
1.39
1.18
1.52
1.96
2.22
D-

G

-

KCL
0.16
0.16
0.16
0.16
0.16

to
0.85
1.22
1.71
1.92
2.51

tdn
KCL
KCL2
0.09
0.09
0.09
0.09
0.09

LD2

5
Path
CL .. Q,XQ
D .. Q
D .. XQ
G .. Q
G .. XQ

Q

--<
:>-- XQ

cl

Symbol
tGW

Typ(ns)*
4.0

Data Setup Time
Data Hold Time

tSD
tHD

1.3
0.5

Clear Pulse Width

tLW

4.0

Parameter
G Input Pulse Width

Input Loading
Factor (R.u)
2
1
1

Pin Name
D
G
CL

Output Driving
Factor (R.u)
18
18

Pin Name
Q
XQ

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are lI:iven by the maximum delay multiplier.

Funcion Table
CL

Inputs
D G

L
H
H
H

X
X
H

UHB-LTL-E2

L

Outputs
X

H

L

H

Qo
H
L

L
L

J Sheet 1/2 I

H
XQo

L
H

I Page 15-7

2-233

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name
LTI.
Equivalent Circuit
CL
GO

Q

--.L
XQ

D

T
XGO

T

GO

G

o----,[>o~[>o~:

GO

XGO

Definition of Parameters
(Case 1)

(Case 3)
I'- tGW - -

CL

G

D

tHD

io--o

K

tLW-y--

G*

II""

Q,XQ

---.t1"____ 1

1-

Note*: G input must be high level
at the time this latch
is cleared.

tpd
(Case 2)

-~-.... L_

tSD

G

D

Q,XQ _ _ _-+____..,/

UHB-LTI.-E2

2-234

Pa e 15-8

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

I UHB Version
I Number of BC

I

LTM
Cell Symbol

4-bit Data Latch with Clear
ProJ:altation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
1.54
0.16
0.97
0.08
0.08
1.22
0.16
1.29
1. 79
0.08
1.60
o 16
0.08
0.16
2.45
2.61
I-- PA
2.73
3.15
0.08
o 16
P-NA
f-PB
P-NB
I-- PC
P-NC·
f-PD
P-ND

DA DB -

DC DD G ---c

I

Parameter
G Input Pulse Width

CL

16
Path
CL .. P,N
D .. P
D .. N
G .. P
G .. N

Symbol
tGW

Typ(ns)*
4.0

Clear Pulse Width

tLW

4.0

Data Setup Time
Data Hold Time

tSD
tHD

1.6
2.3

Input Loading
Factor (lu)
2
1
4

Pin Name
D
G

CL

Output Driving
Factor (lu)
18
18

Pin Name
P
N

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
Inputs

Outputs

CL

D

G

P

N

L

X
X

H
H
L
L

L
Po
H
L

H
No
L

H
H
H

H

L

H

UHB-LTM-E3 I Sheet 1/3 I

I Page 15-9

2-235

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB Version

Cell Name

LTM
Equivalent Circuit

r------------------------,
ct

I

I

PA

GO

-L
NA

DA

I

XGO
XGO

-L

GO

I

~----------~-------------~

r--<>

PB

I

DB

L--...o

I

NB

~------------------------~r--<> PC
DC

I

L--...o

NC

~------------------~-----~,--<>

PD

I

DD 0----1
IL ________________________ J L--...o NO

G~GO
r.

UHB-LTM-E3

2-236

LXGO

Pa e 15-10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

UHB

Version

LTM

Definition of Parameters
(Casel)
tGW
G

D

P,N

(Case2)
G

D

P,N

(Case3)

CL

-

-tLW-

*G

P,N
I'-tpd ....

Note *: G input must be high level at the time this latch is cleared.

Pa e 15-11

2-237

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Ce 11 Name I Function

I UHB Version
I Number of BC

I

I S-R Latch with CLEAR

LTl
Cell ~bol

Propagation Delay Parameter
tdn
tup
KCL
KCLZ CDRZ
to
KCL
to
0.16
0.08
0.86
1. 76
0.08
1.56
0.16
1.04
0.06
1.44
0.16
0.9Z

4

Path
S .. Q,XQ
R .. Q,XQ
CL .. Q,XQ

r--

S --<:

~Q

R --<:

P--XQ

CL
Symbol
tSW

Typ(ns)*
4.0

Reset Pulse Width

tRW

4.0

Clear Pulse Width

tLW

4.0

Parameter
Set Pulse Width

Pin Name
S
R

CL

Pin Name

Q
XQ

Input Loading
Factor (iu)
1
1
1
Output Driving
Factor (iu)
18
18
* Minimum values for the typical operating condition.
The values for the worst case operating condition
are J(iven by the maximum delay multiplier.

Function Table
CL
L
H
H
H
H

Inputs
S

Outputs
R

Q

H
H
H

H
H

L

H

Qo

XQo

L

L

L
L

H

H

H
L

L

XQ

Inhibited

UHB-LTl-E3 J Sheet l/Z I

2-238

I Page 15-12

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name
LTl

Equivalent Circuit
5

XQ

R

Q

CL

Definition of Parameters

5

Q. XQ

tJi
tpd

CL

Q. XQ

tJi
tpd

R

Q.XQ

Pa e 15-13

2-239

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 4-bit Data Latch

LT4
Cell Svmbol

DA
DB
DC
DD

-

G

--C

I "UHB" Version
I Number of BC

I

Propag"tion Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
2.50
0.16
2.28
0.08
3.05
0.08
2.50
0.16
1.05
o 16
1.18
0.08
0.08
1.40
0.16
1.60

14
Path
G -+ P
G-+N
D -+ P
D -+ N

-PA
J - NA
-PB
J - NB
-PC
J - NC
-PD
J-ND
Parameter
G Input Pulse Width
Data Setup Time
Data Hold Time

Pin Name
D
G

Input Loading
Factor (~u)
2
1

Pin Name
P
N

Output Driving
Factor (Rou)
18
18

Symbol
tGW

Typ(ns)*
4.0

tSD
tHD

1.6
2.3

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
Function Table
Inputs
D G
H
L
H
L

H
H
L
L

Outputs
P
N
Po
Po
H
L

No
No
L
H

UHB-LT4-E2 I Sheet 1/3 I

2-240

I Page 15-14

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

LT4
Equivalent Circuit

r---------------------,
1~

U

1.-L
1

DA

NA

1 XGO

I
GO

~---------------------~

- + - - 0 PB
- + - - 0 NB

1

DB

o----t

DC

o---!-1

~---------------------~

-+-~O

PC

-+-~O

NC

~---------------------~

--~I--~O

1

DD

G

o----tL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

o-t>o>----t---t>o------:

1

0

PD
ND

~

GO

L...------- XGO

UHB-LT4-E2

Pa e 15-15

2-241

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
LT4
I

I "UHB

Version

Definition of Parameters
(Case 1)
G

I<- tGW -

-

,r-

D
tHD Io--P,N

~

i'I---tpd

(Case 2)
G

V-

D
"'tSD- -tHD-o
P,N
-

tpd

UHB-LT4-E2 I Sheet: 3/3 I

2-242

---0

[\-

---

I Page 15-16

CMOS Channeled Gate Arreys

UHB Series Unit Cell Ubrarr

Shift Register Family
Basic

Un" Cell

Page

Name

Function

Cells

2-245

FS1

Serial-in Parallel-out Shift Register

18

2-247

FS2

Shift Register with Synchronous Load

30

2-249

FS3

Shift Register with Asynchronous Load

34

2-252

SR1

Serial-in Parallel-out Shift Register with Scan

36

2-243

UHB SerIBa Unit

2-244

c.n Lib!!ry

CMOS Channe/fld Gate Anays

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cel1 Name I Function

I UHB Version
I Number of BC

Shift Register
I 4-bit Serial-in Parallel-out
I
ProJ:agation Delay Parameter

FSI
Cell Svmbol

tup
to
2.42

SD
CK

KCL
0.16

to
3.14

tdn
KCL
KCL2
0.09
0.12

CDR2
4

18
Path
CK ... Q

DQ'
QB
QC
QD

Parameter
Clock Pulse Width
SD Setup Time
SD Hold Time

Pin Name
SD
CX

Input Loading
Factor (.tu)
1
1

Pin Name
Q

Output Driving
Factor (Jl.u)
16

Clock
Pause
Time

'*

C ;;; 16 I.u
I
I 16 < C ;;; 32 I.u
J 32 < C ;;; 48 I.u

Symbol
tCW

Typ(ns)*
4.0

tSSD
tHSD

0.6
0.2

tCWL**
tCWL**
tCWL**

5.8
8.4
10.9

Minimum values for the typical operating condition.
The values for the worst case operating
condition are given by the maximum delay
mul tiplier .

** The value of tCWL depends on the load(C)
connected to the output terminals, QA, QB, QC and
QD.

Function Table
In.uts
SD CK
SD

Outlluts
QA I QB QC I QD

• SD I

QAIl QBJ QCr

Note: ·SD

= H or

L

'QAn, QBn and QCn are levels of
QA, QB and QC respectively,
before the falling edge of CX, i.e.
1 bit shift by the falling edge of CX.

UHB-FSI-E1 I Sheet 1/2 I

Page 16-1

2-245

FUJITSU
Cell Name
FSl

C~OS

GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Equivalent Circuit

,-~-----------------~------------T1- -lrL
QA

QB

QC

QD

T

I

I

I
CKO

L

I

XCKO
CKO

XCKO

-L

-L

J_ pi 1i _____ ~:~~ _________________ ~~~ _________ .l.. ___ .l.. ___ .l.. ___ J
CK

o---Dx>-rf)o-•

CKO

LXCKO

Definition of Parameters
~tcw

tCWL-

CK

Io--tss
SD

Q

UHB-FS1-E1

2-246

V-

tHSD

riPa e 16-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I

FS2
14-bit Shift Register with Svnchronous Load
Cell Svrnbol
Propagation Delav Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
2.32
0.16
3.14
0.09
4
0.12

PA
PB
PC
PD

-

30
Path
CK ... Q

I--QA
I--QB
I--QC
I--QD

SD CK --C
L-

Symbol
tCW

Typ(ns)'·'
4.0

SD Setup Time
SD Hold Time

tSSD
tHSD

2.8
1.2

Load Setup Time
Load Hold Time

tSL
tHL

4.3
0.5

P SetuJl Time
P Hold Time

tSP
tHP

3.6
1.5

Parameter
Clock Pulse Width

Pin Name
CK
SD
L
P

Input Loading
Factor (Rou)
1
1
1
1

Pin Name
Q

Output Driving
Factor (Rou)
16

Clock
Pause
Time
*

C ~ 16 Rou
I
I 16 < C ::: 32 Rou
32 < C ::: 48 Rou

tCWL**
tCWL'~*
tCWL*'~

5.8
8.4
11.0

Minimum values for the typical operating condition.
The values for the worst case operating
condition are given by the maximum delay
mul tiplier.

** The value of tCWL depends on the load(C)
connected to the output terminals, QA, QB, QC and
QD.
Function Table
SD

Inputs
L
P CK

•

QA

SD

L

X

X

H

P

•

=H

or L

Note: ·SD

Outputs
QB QC

QD

SD

QArl QBn QCn

PA

PB

PC

PD

·QAn, QBn and QCn are levels of
QA, QB and QC respectively,
before the falling edge of CK, i.e.
1 bit shift by the falling edge of CK .
• p represents PA, PB, PC and PD.

UHB-FS2-E1j Sheet 1/2 I

Page 16-3

2-247

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
FS2

UHB

Version

Equivalent Circuit
PA

QA

PB

[-------------~o-- --------- --------~-- ------------if

r+jTrii
PC

PD

I

SD

I

I
CKO

XCKO
CKO

XCKO

_1-

-L

-11 bit

XCKO

CKO

~-------------------------------------------------------~---~---~---

CK~X::

L

0---{»-- XLO

Definition of Parameters
~tcw

tCWL-

CK

V-

tHSD
Io--tss
SD

t::.tsp P

L

l'
-i-tSL

i'- tHP-

X

'io..
tHL
-tEd

Q

UHB-FS2-E1

2-248

Pa e 16-4

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell :-lame I Function

I UHB Version
I Number of BC

I

FS3
14-bit Shift Register with Asvnchronous Load
Cell Symbol
Propagation Delav Parameter
tuo
tdn
to
KCL
to
KCL
KCL2 CDR2
2.28
0.17
2.12
0.11
4.64
0.17
3.50
0.11
2.03
0.17
3.02
0.11
PA
PB
PC
PD

-

34
Path
CK ... Q
L ... Q
P ... Q

i-QA
i-QB
i-QC
i--QD

SD CK L --C

Pin Name
CK
SD

Input Loading
Factor(.h)

Svmbol
tCW
tCWH

Typ(ns)*
4.0
4.0

Load Pulse Width

tLW

6.2

SD Setup Time
SD Hold Time

tSSD.
tHSD

1.0
1.7

P getup Time
P Hold Time

tSP
tHP

0.3
2.3

2
2

L

1

P

2

Pin Name
Q

Parameter
Clock Pulse Width
Clock Pause Time

Output Driving
Factor (J/.u)
18

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
L

Inouts
P SD

CK

Output
Q

L

L

H

X
X

X
X

L

L
H

X
X

L
H

t
t

L

H

H
H

UHB-FS3-El I Sheet 1/3 I

I Page 16-5

2-249

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

lJ1iB

Version

Cell Name

FS3
Equivalent
Circuit

SD

PA

QA

0----..,

ITO

PB

1 - - - - 1 ITO

QB

PC

I - - - - - - i ITO

QC

PD

QD

FFO

Equivalent Circuit of ITO

P

Q

DO

QO

CKO
XCKO
XLDO
LDO

DO

CKO

UHB-FS3-E1

2-250

XCKO

Pa e 16-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
FS3

I
J

I

UHB" Version

Definition of Parameters

.1

CK

I'- tCWH

1"----

SD

L

P

t='LWl
---t'sp-+~f=

UHB-FS3-E1 I Sheet 3/3 I

I Page

16-;

2-251

Ell

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I "UHB Version
I Number of BC

I

SRI
4-bit Serial-in Parallel-out Shift Register with SCAN
Cell Svmbol
Pro]:agation Delay Parameter
tup
tdn
to
to
KCL
KCL2 CDR2
KCL
3.27
3.37
0.07
0.11
7
0.09
2.58
0.09
2.90
0.07
0.11
7

36
Path
CK ... Q
B ... Q

r---

DCK IH SI AB -C

r--QA
I - QB
I - QC

r--QD

Parameter
Clock Pulse Width
Clock Pause TIme
Data Setup Time
Dau Hold Time

Pin Name
D
CK
IH
SI
AB
Pin Name
Q

Symbol
tCW
tCWH
tSD
tHD

Typ(ns)*
5.5
5.6
3.3
1.5

Input Loading
Factor (R.u)
1
1
1
1
1
Output Driving
Factor (R.u)
36

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-SRI-El I Sheet 1/3 I

2-252

I Page 16-8

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

SR1

QA

QB

QC

DO
QO
SDO 5QO
CLK
XCLK
ACK
XACK
BCK
XBCK

D
51

ITO

ITO

ITO

CLK

XBCK XCLK

-L

-L -L

DO

ITO

)O------0Qo

~~-~ xr~----o5QO

I

XCLK
XACK

XCLK ACK

-L

-L -L

I

II

CLK

SDO

ACK

CK

CLK

I

XACK

XCLK

CLK

I

IH
XCLK

XBCK

B~BCK

~XBCK

Pa e 16-9

2-253

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
SR1
I

I

UHB

Version

Definitions of Parameters
tcw
CK

}

~I

tSn- ~HD'"
D

lJHB-SR1-E1 I Sheet 3/3 I

2-254

I Page

16-10

CMOS Channeled Gate Arrays

UHB Series Unit Cell Ubrary

Parity Generator/Selector/Decoder Family

Page

Unit Cell
Name

Function

Basic
Cells

Parity Generators/Checkers
2-257

PE5

Even Parity Generator/Checker

12

2-258

POS

Odd Parity Generator/Checker

12

2-259

PE8

Even Parity Generator/Checker

18

2-260

P08

Odd Parity Generator/Checker

18

2-261

PE9

Even Parity Generator/Checker

22

2-262

P09

Odd Parity Generator/Checker

22

2:1 Data Selector

12

Data Selector
2-263

P24

Decoders
2-264

DE2

2:4 Decoder

5

2-265

DE3

3:8 Decoder

15

2-267

DE4

2:4 Decoder

8

2-268

DE6

3:8 Decoder

30

2-270

T2B

2:1 Selector

2

2-272

T2C

2:1 Selector

4

2-273

T2D

2:1 Selector

2

2-274

T2E

2:1 Selector

5

2-275

T2F

2:1 Selector

8

2-277

T5A

4:1 Selector

5

2-279

V3A

1:2 Selector

2

2-280

V3B

1:2 Selector

4

Selectors

Magnitude Comparator
2-281

MC4

Magnitude Comparator

42

2-255

UHB Series Unit Cell LIbr8!Y

2-256

CMOS Chamleled Gale AITIIYs

, "UHB" Version
, Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell l"

Input Loading
Factor (Rou)
2
2
2
Output Driving
Factor (Rou)
36

*

Equivalent Circuit

Function Table
Hnout

X

Odd

L

Even

H

Bl
B2

r-..

"

l/

X

Cl
C2
A

UHB-PE5-E1 , Sheet 1/1 I

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiplier.

r-..

"

Ir--

l/

Page 17-1

2-257

I "UHB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I s-bit Odd Parity Generator/Checker
I
Propagation Delay Parameter

POS
Cell Svmbol

tup
to
2.63
2.86
4.19

A
B1
B2
Cl
C2

KCL
0.08
0.08
0.08

to
3.07
3.04
4.56

tdn
KCL
KCL2
0.04
0.04
0.04

Path
A-+X
B ... X
C -+ X

{J-x
Svmbol

Parameter

C

Input Loading
Factor (R.u)
2
2
2

Pin Name
X

Output Driving
Factor (R.u)
36

Pin Name
A
B

*

Hnput

X

Odd

H

Even

L

Bl
B2

Cl
C2
A

UHB-POs-El I Sheet 1/1 I

Typ(ns)"

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
Equivalent Circuit

Function Table

2-258

CDR2

12

r-...

"

l

L./

r-...

"

.,u::::,.
X

Ir--.

L./

I Page 17-2

I UHB" Version
INumber of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

PE8
Cell Symbol

8-bit Even

Parit~

Prota~ation

tup
to
KCL
3.85
0.16
3.94
0.16
3.93
0.16
4.02
0.16
AlA2 BlB2 ClC2 DlD2 -

p-

I

Generator/Checker
to
4.33
4.42
4.40
4.49

Delay Parameter
tdn
KCL2 CDR2
KCL
0.08
0.08
0.08
0.08

D

Pin Name
X

Symbol

Typ(nsJ*

Input Loading
Factor (£u)
2
2
2
2
Output Driving
Factor (£u)
18

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
Equivalent Circuit

Function Table
!input

Path
A'" X
B ... X
C ... X
D ... X

X

Parameter

Pin Name
A
B
C

18

X

Odd

L

Even

H

UHB-PE8-El I Sheet 1/1 I

A1
A2
B1
B2

1["-"

JI

L/

r--

["-.,

II

L/

II
L./

C1
C2

iJ""..

D1
D2

1["-"

II
L/

X
II'"'-..

II

11../

II
L/

I Page 17-3

2-259

I "UHB" Version
I Number of BC

FUJITSU CMOS GArB ARRAY UNIT CELL SPECIFICATION
Ce11 Name I Function

I 8-bit Odd Parity Generator/Checker
I
Prollagation Delay parameter

P08
Ce11 Symbol

tup
to
KCL
3.77
0.16
3.86
0.16
3.87
0.16
3.96
0.16
AlA2 BlB2 Cl C2 Dl D2 -

tdn
KCL
KCL2
0.08
0.08
0.08
0.08

to
4.28
4.37
4.17
4.26

Pin Name
X

Path
A .. X
B .. X
C .. X
D .. X

I-- X

Parameter

Pin Name
A
B
C
D

CDR2

18

Symbol

1'yp(ns) *

Input Loading
Factor (R.u)
2
2
2
2

Output Driving
Factor (R.u)
18

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
Iinput
Odd
Even

X
H

Equivalent Circuit
Al
A2
Bl
B2

L
Cl
C2
Dl
D2

UHB-P08-r:2 I Sheet 1/1 I

2-260

r--

II
L/

It'..

II

It'..

II
L/

L/

X

t'..

II

11./

It'..

Ll

r-...

II
L/

1./

I Page 17-4

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I 9-bit Even Parity Generator/Checker
I
Pronagation Delav Parameter

PE9
Cell SYmbol

tup
to
S.29

A1A2 A3 A4 AS A6 A7 A8 A9 -

KCL
0.16

to
S.7l

tdn
KCL
KCL2
0.08

Pin Name
X

Path
A-+X

0-- X

Symbol

Parameter

Pin Name
A

CDR2

22

Typ(ns)*

Input Loading
Factor (lu)
2

Output Driving
Factor (lu)
18

*

MinilDUlD values for the typical operating condition.
The values for the worst case operating condition
are given by the maximUID delay multinlier.

Equivalent Circuit

Function Table
A3
!input

X

A8

Odd

L

Even

H

Al
A2

A9

A4

....,
r....

II....,
X

AS

A6
A7

UHB-PE9-E1 I Sheet 1/1 I

I Palte li-5

2-261

FUJITSU CMOS GATE
Cell Name I Function

AR~AY

I UHB Version
I Number of BC.

UNIT CELL SPECIFICATION

I 9-bit Odd Parity Generator/Checker
I
Prooa{tation Delay Parameter

P09
Cell Svmbol

tup
to
5.20

A1A2 A3 A4AS A6 A7 A8 A9 -

r--

KCL
0.16

to
5.71

tdn
KCL2
KCL
0.08

CDR2

22
Path
A~X

X

Symbol

Parameter

Pin Name
A

Input Loading
Factor (Rou)
2

Pin Name
X

Output Driving
Factor (Rou)
18

Typ(ns)*

* Minimum va~ues for the typical operating condition.
The values for the worst case operating condition
are ltiven by the maximum delay multiplier.
Equivalent Circuit

Function Table
A3
Iinput

X

A8
A9

Odd

H

Even

L

A1
A2
A4
AS

A6
A7

UHB-P09-E1 I Sheet 1/1 I

2-262

'-'"

_I'"'"

I~.

r

X

I Page 17-6

I UHB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 4-wide 2:1 Data Selector Propagation Delav Parameter I

P24
Cell Svmbol

tup
to
0.95
1.16
0.81
1.00
AIB1 A2 B2 A3 B3 A4 B4 SA SB -

r--

-

KCL
0.08
0.08
0.08
0.08

to
0.83
0.97
0.95
1.08

tdn
KCL2
KCL
0.04
0.04
0.04
0.04

CDR2

12
Path
A .. X
B .. X
SA .. X
SB .. X

Xl
X2
X3
X4
Parameter

Pin Name
A
B
S

Input Loading
Factor _(tu)
1
1
4

Pin Name
X

Output Driving
Factor (tu)
36

Symbol

Typ(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
Equivalent Circuit

Function Table
Al
SA

SB

Xn

Bl
L
H
L
H

L
L
H
H

L

An
Bn
An+Bn

A2
B2
A3
B3

-

Xl

..... -

X2

.....
...... -

X3

......

A4
...... 1-

B4
SA -

X4

!-

SB UHB-P24-E2 I Sheet 1/1 I

I Page 17-7

2-263

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Ce1l Name I Function

I 2:4 Decoder

DE2
Ce1l Svmbol

Pro~agation

tup
to
0.79
0.88
0.37
0.88
0.28
0.79

A~XC

KCL
0.16
0.16
0.16
0.16
0.16
0.16

to
1.08
0.97
0.45
0.97
0.56
1.08

I UHB Version
I Number of BC

I

Delav Parameter
tdn
KCL
KCL2 CDR2
0.14
0.14
0.14
0.14
0.14
0.14

5
Path
A ... XO
A ... Xl
A ... X2,X
B .. XO
B .. Xl,X
B .. X2

Xl
X2
X3

B

Symbol

Parameter

B

Input Loading
Factor (£u)
3
3

Pin Name
X

Output Driving
Factor (£u)
18

Pin Name
A

Typ(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
Function Table
InJ:uts
A
B

X3

Outputs
X2
Xl

XO

H
H

H

L

L

L

H
H
H

L

H

L

H

H
H

H
H
H

L
L

L

H
H

H

A

B

UHB-DE2-E2 I Sheet 1/1 I

2-264

~

XO

tg

X2

t»-~

Xl

X3

I Page 1 i-8

I "UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

I 3:8 Decoder

DE3
Cell Svmbol

f--XO
f--X1
-X2
-X3
-X4
-X5
-X6
-X7

ABC-

15

Prooagation Delay Parameter
tuo
tdn
to
KCL
to
KCL
KCL2 CDR2
1.44
1.67
0.16
0.19
2.44
0.16
2.44
0.19
1.33
0.16
0.19
1.72
0.16
2.49
0.19
2.33
1.23
0.16
1. 78
0.19
0.19
2.23
0.16
2.55

Path
A ... XO-X3
A ... X4-X7
B ... XO-X3
B ... X4-X7
C ... XO-X3
C ... X4-X7

Svmbol

Typ(ns)''<

Parameter

Input Loading
Factor (iu)
1
1
1

Pin Name
A
B
C

Output Driving
Factor (iu)
14

Pin Name
X

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiolier.

Function Table
Inputs
A B C
L
L
L
L

L
L
H
H

H

L

H
H
H

L
H
H

L
H
L
H
L
H
L
H

XO

Xl

X2

L
H
H
H
H
H
H
H

H
L
H
H
H
H
H
H

H
H
L
H
H
H
H
H

UHB-DE3-E2J Sheet 1/2 I

Outputs
X3
X4
H
H
H
L
H
H
H
H

H
H
H
H
L
H
H
H

X5

X6

X7

H
H
H
H
H
L
H
H

H
H
H
H

H
H
H
H
H
H
H
L

H

H
L
H

I Pal1;e 17-9
2-265

FUJITSU CXOS GATE ARRAY UNIT CELL SPECIFICATION

tJ1!B

Version

Cell Name

DE3
Equivalent Circuit

A

XO

Xl
B

X2

X3

c

X4

X5

X6

X7

UHB-DE3-E2

2-266

Pa e 17-10

"UHB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 2:4 Decoder with Enable

DE4
Cell Svmbol

I

Propagation Delay Parameter
tUl)
tdn
to
KCL
to
KCL
KCL2 CDR2
0.16
1.46
0.19
1.19
0.86
0.16
0.19
1.11
1.07
0.16
1.14
0.19

8

Path
G ... X
A ... X
B ... X

~xo

A
B

Xl
X2
X3

G

Symbol

Parameter

G

Input Loading
Factor (.Iou)
3
3
1

Pin Name
X

Output Driving
Factor (R.u)
14

Pin Name
A
B

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
Equivalent Circuit

Function Table
G

A

B

X3

X2

Xl

XO

G

H

X

X

H

H

H

H

A

L
L
L
L

L
L

L

H
H

H

L

L

L

H
H
H

H

L

H

H
H
H

H
H

H

Typ(ns ),,:

L

H
H

FirFir-n
- FirXO

'--

B

X2

~X3
UHB-DE4-E2 I Sheet 1/1 I

I Page 17-11

2-267

I "UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 3:8 Decoder with Enable

DE6
Cell Symbol

I

Propagation Delay Parameter
tup
tdn
to
KCL
KCL2 CDR2
to
KCL
3.0S
0.16
S.9S
0.08
2.89
0.16
3.28
0.08

G1G2 G3 SlS2 S3 -

30
Path
G"'X
S ... X

-XO
r-X1
~X2

r--- X3
r---- X4
r--- XS
r--- X6
r--- X7
Symbol

Parameter

Pin Name
G
S

Input Loading
Factor (R.u)
1
1

Pin Name
X

Output Driving
Factor (R.u)
18

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
G1

G2+G3

S3

S2

Sl

X7

X6

XS

X4

X3

X2

Xl

XO

X

H

L

X

X
X

X
X

X
X

H
H

H
H

H
H

H
H

H
H

H
H

H
H

H
H

H
H
H
H
H
H
H
H

L
L
L
L
L
L
L
L

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

H
H
H
H
H
H
H
L

H
H
H
H
H
H
L
H

H
H
H
H
H
L
H
H

H
H
H
H
L
H
H
H

H
H
H
L
H
H
H
H

H
H
L
H
H
H
H
H

H
L
H
H
H
H
H
H

L
H
H
H
H
H
H
H

UHB-DE6-E3 I Sheet 1/2 I

2-268

I Page 17-12

FUJITSU

cnos

GATE ARRAY UNIT CELL SPECIFICATION

UHB

Version

Cell Name

DE6
Equivalent Circuit

Gl

XO

G20-------~~~r+----------~--~

G3 o-------_+_-I

Xl

X2

X3

X4

XS

S2 0-----1

)(>------O---j.....,

S3 0-----1

)(>---------.....,

X6

X7

UHB-DE6-E3

)::>-----+------i

Pa e 17-13

2-269

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
J Number of BC

I

T2B
2:1 Selector
Cell Svmbo1

Pro.agation Delay Parameter
tU1)
tdn
to
KCL
to
KCL
KCL2 CDR2
0.52
0.16
0.78
0.09
0.61
0.16
0.99
0.09

2
Path
A,B .. X
S .. X

t{J-.
S2

Symbol

Parameter

Pin Name
A,B
S

Input Loading
Factor (iu)
2
1

Pin Name

Output Driving
Factor (iu)
18

X

*

Typ(ns)'~

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
Equivalent Circuit

Function Table

A

In1)uts
51
B

52

X

L
H

X
X

X

L
H
L
L
H
H

L
L
H
H
L
H
L
H

H
H
L
L
L
H
L
H

H
L
H
L
Inhibit
Inhibit
Inhibit
Inbibit

-L

Output
A

X
H
H
L
L

:E--

2-270

I 5heet 1/1 I

X

B

-r

51
52

UHB T2B-E2

H>

~

I Page 17-14

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

T2C
Dual 2:1 Selector
Cell Symbol

I UHB Version
I Number of BC

I

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.51
0.16
0.77
0.09
0.67
0.16
1.03
0.09

4

Path
A,B ... X
S ... X

Sl S2

~I
[)-XO

A1A2B1B2-

P--X1

Parameter

Pin Name
A,B
S

Input Loading
Factor (R.u)
2
2

Pin Name
X

Output Driving
Factor (R.u)
18

Symbol

Typ(ns)'"

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum de1av multiplier.

Function Table
Inputs
A1,B1
A2,B2
L
H
X
X
L

H
L
H

X
X
L
H
H
L

H
L

Sl

S2

L
L
H
H

H
H
L

L
L

L
L
L

H
H

H
H

UHB-T2C-E2 I Sheet 1/2

I

Outputs
XO
H
L
H

Xl
H
L
H

L

L

Inhibit
Inhibit
Inhibit
Inhibit

Inhibit
Inhibit
Inhibit
Inhibit

I Pa~e

17 15

I

2-271

FUJITSU

C~OS

GATE ARRAY UNIT CELL SPECIFICATION

Cell Name

UHB

Version

T2C
Equivalent Circuit

Al
) 0 - - - - 0 XO

A2

O---!----I

Bl
) 0 - - - - 0 Xl

B2 0---+---1
5lo--_--...J
52 O>-------...J

UHB-T2C-E2

2-272

Pa e 17-16

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I

T2D
2:1 Selector
Cell Symbol

Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.62
0.18
0.70
0.12
0.67
0.18
0.51
0.12

2·
Path
A,B ... X
S ... X

tD-x
52

Symbol

Parame.ter

Pin Name
A,B
5

Pin Name
X

Input Loading
Factor (iu)
1
1

Output Driving
Factor (iu)
14

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are ~iven bv the maximum delay multiplier.

Function Table
InJ:uts
S1

A

B

L

X

H
X
X

X
L

T~(ns)*

Equivalent Circuit

---L

Output
S2

X

H
H
L

H

A

L
L
H
H

H
H
H

L
L

L
L
H
H

L

L
L

H
L
H

H
L
H

L

=:E-

H
L

Inhibit
Inhibit
Inhibit
Inhibit

B

I Sheet 1/1 I

--r

Sl
S2

UHB-T2D-E2

r---oX

~

I Page Ii-Ii

2-273

I "ullB Version
1 Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I Dual 2:1 Selector

T2E
Cell Svmbol

A1A2 B1B2 -

I

5

Pro,agation Delay PaTameter
tup
tdn
to
to
KCL
KCL
KCL2 CDR2
0.54
0.16
0.54
0.10
0.14
4
4
1.64
0.16
1.62
0.10
0.14

Path
A,B ... X
S ... X

Symbol

Typ(ns)>"

:r-XO
:r-X1

-

S

Parameter

Pin Name
A,B

Input Loading
Factor (R.u)
2

S

1

Pin Name
X

Output Driving
Factor (R.u)
18

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Equivalet Ciruit

----:L
Al
---r--'--

~

XO

A2

f----3=
BI

--.---'--

~

Xl

B2

S

Lv

UHB-T2E-El I Sheet: I / 1 I

2-274

I

I Page 17-18

I UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 2:1 Selector

T2F
Cell Symbol

Pro~a,l1;ation

tup

A1A2 B1 B2 C1 C2 D1D2 S -

to
0.54

KCL
0.16

to
0.54

1.64

0.16

1. 62

I

Delay Parameter
tdn
KCL
KCL2 CDR2
0.10
0.14
4
0.10

0.14

4

8
Path
A,B,
C,D .. X
S .. X

::>-- XO
::>-- Xl
::>-- X2
t:r- X3

Parameter

Pin Name
A,B,C,n
S

Input Loading
Factor (R.u)
2
1

Pin Name
X

Output Driving
Factor (R.u)
18

Symbol

Typ(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-T2F-E1 I Sheet 1/2 I

I Pa,l1;e 17-19

2-275

FUJITSU
Cell Name
T2F

C~OS

GATE.ARRAY UNIT CELL SPECIFICATION

UHB

Version

Equivalent Circuit

Al

XO
A2

Bl
Xl
B2

-....--'--

Cl
X2
C2

-,Dl
X3
D2
S

UHB-T2F-E1

2-276

Sheet 2/2

Pa e 17-20

I "UHB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
T5A
14:1 Selector
Cell Svmbol

1
Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
1.00
0.23
1. 00
0.16
0.84
1.00
0.23
0.16
0.56
0.23
0.54
0.16

S1 S2 S3 S4

AI_
A2_
B1_
B2_

tiLl

5
Path
A,B -+ X
S1-4 -+ X
S5-6 -+ X

P--x

TI

S5 S6
Symbol

Parameter

Pin Name
A,B
S

Pin Name
X

Typ(ns)*

Input Loading
Factor (.tu)
1
1

Output Driving
Factor LR.ul
9

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are ltiven by the maximum delay multiplier.

Function Table
A1

A2

B1

B2

In uts
S2
S1

L

L

H

L
H
H

L
H

S3

S4

S5

S6

H
H
L
L

L
L
L
L
H
H
H
H

H
H
H
H
L
L
L
L

H
H
L
L

L
H
L
H

L
L
H
H

Output
X
H
L
H
L
H
L
H
L

A1=A2 -+ S1=S2 or S5=S6 Inhibit
B1=B2 -+ S3=S4 or S5=S6 Inhibit
A1,A2=B1,B2 or S5=S6 Inhibit

UHB-T5A-E2 I Sheet 1/2 I

I Page 1;-21

2-277

FUJITSU

C~OS

GATE ARRAY UNIT CELL SPECIFICATION

Cell Name

UHB

Version

T5A
Equivalnt Circuit

Al

A2

Sl

S2

x

S4
S3

Bl

B2

S5
S6

UHB-T5A-E2

2-278

Pa e 17-22

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name J Function
V3A
11: 2 Selector
Cell Svmbol

Sl

=[}=xo

S2

Xl

A

Input Loading
Factor (R.u)
1
1

Pin Name
X

Output Loading
Factor (R.u)
1

Pin Name
X

Output Driving
Factor (R.u)
14

I

*

Symbol

Inputs
Sl
S2

2
Path
A'" X
S ... X

Typ(ns)~'

Minimum values for the typical operating condition.
The values for the worst case operating condition
are .lti ven by the maximum delay multiplier.
Equivalent Circuit

Function Table

A

I Number of BC

Propagation Delay Parameter
tup
tdn
to
to
KCL
KCL
KCL2 CDR2
0.18
0.70
0.12
0.62
0.55
0.18
0.45
0.12

Parameter

Pin Name
A
S

J "UHB" Version

I-l-

Outputs
XO I Xl

-~XO

Inhibit

L

L

L

L

H

L

X

H

L

L

H

H

X

L

H

H

H

L

L

H

H

L

X

L

H

L

H

L

X

H

H

H

Inhibit

A

cr-[>oSl

~

~~~n
-r

S2

Inhibit

UHB-V3A-E1 I Sheet 1/1 I

I Page 17-23

2-279

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

V3B
Dual 1:2 Selector
Cell 5vmbol

Pro.a!l;ation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
0.64
0.18
0.76
0.12
0.48
0.12
0.57
0.18

ADxo

B
51
52

Pin Name
A
B
5
Pin Name
X

Pin Name
X

Path
A,B -+ X
5 -+ X

5ymbol

Output Loading
Factor (Rou)
1

Output Driving
Factor (Rou)
14

Inputs
51
S2

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given b~ the maximum delay multiplier.
Equivalent Circuit

Outputs
XO, X2 I Xl, X3

A~

L

L

L

L

H

L

X

H

L

L

H

H

X

L

H

H

Inhibit

Inhibit
H

L

1.

H

H

L

X

L

H

L

H

L

X

H

H

H

XO

=t=-

-~

B~-~
-~

Inhibit

5heet 1/1 I

-~

Xl

~

51
UHB-V3B-E2

Typ(ns)*

Input Loading
Factor (.h)
1
1
2

Function Table

2-280

4

Xl
X2
X3

Parameter

AB

I UHB Version
I Number of BC

52

X2

X3

-r

I Page 17-24

FUJITSU cnos GATE ARRAY
Cell Name I Funct:ion

L~IT

CELL SPECIFICATION

I URB Version
I Number of BC

I 4-bit Magnitude ComoaratorPrq]: agation Dela-v Paramet:e-r I

MC4
Cell Svmbol

tup

A3
A2
A1
AO

B3:=
B2:=
B1:=
BO:=
IG-

-OG
-DE
-OS

IEIS-

to
5.29
5.38
2.36
1. 93
5.18
5.27
2.25
2.13
5.69
5.58
2.14

KCL
0.29
0.29
0.29
0.29
0.29
0.29
0.29
0.29
0.16
0.16
0.16

to
6.32
6.21
2.78
2.41
6.53
6.42
2.99
2.31
4.36
4.45
1.43

tdn
KCL
0.08
0.08
0.08
0.08
0.08
0.08
0.08
0.08
0.09
0.09
0.09

KCL2
0.11
0.11
0.11
0.11
0.11
0.11
0.11
0.11
0.12
0.12
0.12

Symbol

Parameter

Pin Name
A
B
IE

Typ(ns)*

1

1
1

IS

as

Path
A .. as
B .. as
IE .. as
IG .. OS
A .. OG
B ... OG
IE ... OG
IS ... OG
A ... DE
B .. DE
IE .. OE

Input Loading
Factor (Rou)
3
3

IG

Pin Name
OE
OG

CDR2
4
4
4
4
4
4
4
4
4
4
4

42

Output Driving
Factor (Rou)
18
10
10

*

Minimum values for the typical operating condHion.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Function Table
Comoarin

Inputs

A3,B3

A2 B2

Al,Bl

AO,BO

A3>B3
A3B2
A2B1
AlBO
AOB) (AB)

Outouts
OS
OE
(A-

if

Version

Equivalent
Circuit

I
r"-

OG

l./

r"-

if

A2
B2
IS

-

t- j -

~

W

r---l./

f"\

>- ,.....

p--

r-rl./

r-IE

OE
l- t - t--l./

IG

f"\

Al

v-

Bl

~

I

:~

t--

'-

p--

v
j--r--

v

OS

r-..

~W

AO
BO

~

v

I

LJ1lB-MC4-E1 I Sheet 2/2 I

2-282

Q>

V-

V-

I Page 17-26

CMOS Channeled Gate Anays

UHB Series Unit Cell Ubrary

Bus Driver
Basic

UnRCeIl

Page

Name

2-285

B41

Function
4-bit Bus Driver

Cells

9

2-283

UHB Series Unit Cell Ubraty

2-284

CMOS Channeled Gate Arrays

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I 4-bit Bus Driver

B41
Cell SVlDDol

I

Prooagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
1.58
0.07
1.52
0.06
2.50
0.07
1.90
0.06

9
Path
A ... X
C ... X

r--XO
r--X1
r--- X2
I--- X3

AO AlA2 A3 C --<:

Parameter

Pin Name
A
C

I "UHB" Version
I Number of BC

Symbol

Typ(ns)'~

Input Loading
Factor (Iou)
1

1

Pin Name
X

Output Loading
Factor (Iou)
1

Pin Name
X

Output Driving
Factor (Iou)
36

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiplier.

Maximum Number of B41 used in each UHB device
Device Name

Max. B41

Device Name

Max. B41

C-330UHB

4

C-3000UHB

21

C-530UHB

5

C-4100UHB

26

C-830UHB

6

C-6000UHB

50

C-1200UHB

8

C-8700UHB

70

C-1700UHB

12

C-12000UHB

90

C-2200UHB

16

UHB-B41-E3 I Sheet 1/21

Page 18-1

2-285

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I
B41
I

I

DRB

Version

Equivalent Circuit

i .------------------.

r-±-i
J'
Ao---+--~l--~
)o-~:--~~ r-~-----+--- xo
I 'BD-----------------TJ-T-- J I
I

I

I

:

:

I

,

Al

A2

,
m
-l-;m-uum----mw--- - i I
i :~~:::::::::::::::~ fm-----j i

T'::

::J: :LL
'n-,
~

'sil-----------------

A3

~TG

I

I

~--·-·-·-4

I;

~ G

!
j

g~= ,L______

,

X3

I

,

I
,

r----~--------------:

C

X2

i

~------------------1

I, ;~BD----------------J

Xl

I

I ::
~Co
DC---------------,
L _________ .J
~Co

Note:
TG is configured using the special transmission gates buried in the
channel area of the DRB devices_
BD and DC use the regular internal baisc cells in the DRB devices.
A Bus Terminator is invisible to logic designers and is automatically
connected to each Bus line, when B41 is used.

UHB-B41-E3

2-286

J Sheet

2/2 I

LP~e

18-2

UHB Series Unit Cell Ubrary

CMOS Channeled Gate Arrays

Clip Cells

Page

UnH Cell
Name

2-289
2-290
2-291

ZOO
Z01
KD2

Function

o Clip
1 Clip

Basic
Cells

o
o

Load Gate (Fan-in = 2)

2-287

UHB Series Unit Cell Library

2-288

CMOS Channeled Gate Arrays

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

J

J o Clip

ZOO
Cell Symbol

to

Prol=agation Delav Parameter
tup
tdn
KCL
to
KCL
KCL2 CDR2

0

Path

X

~
Parameter

Pin Name

Pin Name
X

Symbol

Typ(ns)*

Input Loading
Factor (R.u)

Output Driving
Factor (R.u)
200

*

UHB-ZOO-E1 I Sheet 1/1 I

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page 19-1

2-289

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

ZOI

I 1 Clip

I UHB Version
I Number of BC

I

Cell Svmbol

to

Propagation Delav Parameter
tun
tdn
KCL
to
KCL
KCL2 CDR2

0
Pa1:h

r
X

Parameter

Pin Name

Input Loading
Factor (!u)

Pin Name
X

Output Driving
Factor (!u)
200

*

UHB-Z01-El I Sheet 1/1 I

2-290

Symbol

Typ (ns ) ,',

Minimum values for the typical operating condition.
The values for the worst case operating condition
are ltiven by the maximum delay multiplier.

I Page 19-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name -' Function

I Load Gate Fan-in = 2

KD2
Cell Symbol

Pro~agation

tup
to

A

KCL

to

I "UHB" Version
I Number of BC

I

Delay Parameter
tdn
KCL
KCL2 CDR2

1
Path

-t>
Parameter

Pin Name
A

Input Loading
Factor (iu)
2

Pin Name

Output Driving
Factor (iu)

Symbol

Typ(ns)1(

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-KD2-E1 I Sheet 1/1 I

Page 19-3

2-291

CMOS Channeled Gate Ana¥!

2-292

UHB Series Unit Cell Ub(alf

UHB SeIifIs Unit CslI LibraIy

CMOS Channeled Gale Anars

1/0 Buffer Family

Page

Unit Cell
Name

Function

Basic
Cells

Input BuHers
2-295
2-296
2-297
2-298
2-299
2-300
2-301
2-302
2-303
2-304
2-305
2-306
2-307
2-308
2-309
2-310
2-311
2-312
2-313
2-314
2-315
2-316
2-317
2-318
2-319
2-320
2-321
2-322
2-323
2-324

11B
11BU
11BO
12B
12BU
12BO
IKB
IKBU
IKBO
ILB
ILBU
ILBO
11C
11CU
11CO
12C
12CU
12CO
11S
11SU
11S0
12S
12SU
12S0
11R
11RU
11RO
12R
12RU
12RO

Input Buffer
11 B with Pull-up Resistance
11 B with Pull-down Resistance
Input Buffer
12B with Pull-up Resistance
12B with Pull-down Resistance
Clock Input Buffer
IKB with Pull-up Resistance
IKB with Pull-down Resistance
Clock Input Buffer
ILB with Pull-up Resistance
ILB with Pull-down Resistance
CMOS Interface Input Buffer
11 C with Pull-up Resistance
11 C with Pull-down Resistance
CMOS Interface Input Buffer
12C with Pull-up Resistance
12C with Pull-down Resistance
Schmitt t~er Input Buffer
11S with Pu -up Resistance
11S with Pull-down Resistance
Schmitt trigger I~t Buffer
12S with Pu -up esistance
12S with Pull-down Resistance
Schmitt tri~er Inre: Buffer
11 R with Pu -up esistance
11 R with Pull-down Resistance
Schmitt trefter Inre: Buffer
12R with Pu I-up esistance
12R With Pull-down Resistance

5
5
5
4
4
4
4
4
4
6
6
6
5
5
5
4
4
4
8
8
8
8
8
8
6
6
6
8
8
8

Output Buffer
Power Output Buffer
Output Buffer
Power Output Buffer
Output Buffer
Power Output Buffer
Output Buffer
Power Output Buffer
High Power Output Buffer
OUtput Buffer
Power 3-state Output Buffer
High Power Output Buffer
OUtput Buffer
Power 3-state Output Buffer
Output Buffer
Output Buffer
Output Buffer
Output Buffer
3-state Output Buffer
3-state Output Buffer

3
3
5
5
2
2
4
4
6
5
5
7
4
4
3
5
2
4
5
4

Output BuHers
2-325
2-326
2-327
2-328
2-329
2-330
2-331
2-332
2-333
2-334
2-335
2-336
2-337
2-338
2-339
2-340
2-341
2-342
2-343
2-344

01B
01L
01R
018
02B
02L
02R
028
0282
O4R
O4S
0482
O4T
O4W
01BF
01RF
02BF
02RF
O4RF
O4TF

Bidirectional 110 BuHers (Buses)
2-345
2-346
2-347

H6T
H6TU
H6TD

3-state Output and Input Buffer
H6T with Pull-up ReSistance
H6T with Pull-down Resistance

8
8

8

2-293

CMOS Channeled Gate Arrays

UHB Series Unit Cell UbrSry

I/O Buffer Family (Continued)

2-348
2-349
2-350
2-351
2-352
2-353

H6W
H6WU
H6WD
H6C
H7CU
H6CD

Power 3-state Out~ut and Input Buffer
H6W with Pull-up esistance
H6W with Pull-down Resistance
3-state Output and CMOS Interface Input Buffer
H6C with Pull-up Resistance
H6C with Pull-down Resistance

8
8
8
8
8
8

Output Buffers
2-354
2-355
2-356
2-357
2-358
2-359
2-360
2-361
2-362
2-363
2-364
2-365
2-366
2-367
2-368
2-369
2-370
2-371
2-372
2-373
2-374
2-375
2-376
2-377
2-378
2-379
2-380
2-3S1
2-3S2
2-3S3
2-384
2-3S5
2-3S6
2-3S7
2-3S8
2-389
2-390
2-391
2-392
2-393
2-394
2-395
2-396
2-397
2-39S

H6E
H6EU
H6ED
H6S
H6SU
H6SD
H6R
H6RU
H6RD
H8T
H8TU
H8TD
H8W
HBWU
HSWD
H8W2
H8W1
HSWO
HSC
H8CU
HSCD
H8E
HSEU
HSED
H8E2
HSE1
HSEO
HSS
HSSU
HSSD
HSR
HSRU
HSRD
H6TF
H6TFU
H6TFD
H6CF
H6CFU
H6CFD
HSTF
HSTFU
HSTFD
HSCF
H8CFU
HSCFD

Power 3-state Output and CMOS Interface Input Buffer
H6E with Pull-up Resistance
H6E with Pull-down Resistance
3-state Output and Schmitt trigger Input Buffer
H6S with Pull-up Resistance
H6S with Pull-down Resistance
3-state Output and Schmitt trigger Input Buffer
H6R with Pull-up Resistance
H6R with Pull-down Resistance
3-state Output and Input Buffer
H8T with Pull-up Resistance
H8T with Pull-down Resistance
Power 3-state Output and Input Buffer
HSW with Pull-up Resistance
HSW with Pull-down Resistance
High Power 3-state Output and Input Buffer
HSW2 with Pull-up Resistance
HSW2 with Pull-down Resistance 11
3-state Output and CMOS Interface Input Buffer
HSC with Pull-up Resistance
H8C with Pull-down Resistance
Power 3-state Output and CMOS Interface Input Buffer
HSE with Pull-up Resistance
HSE with Pull-down Resistance
High Power 3-state Output and Input Buffer
HSE2 with Pull-up Resistance
HSE2 with Pull-down Resistance
3-state Output and Schmitt trigger Input Buffer
HSS with Pull-up Resistance
HSS with Pull-down Resistance
3-state Output and Schmitt trigger Input Buffer
HSR with Pull-up Resistance
HSR with Pull-down Resistance
3-state Output and Schmitt trigger Input Buffer
H6TF with Pull-up Resistance
H6TF with Pull-down Resistance
3-state Output and Input Buffer
H6CF with Pull-up Resistance
H6CF with Pull-down Resistance
3-state Output and Input Buffer
H8TF with Pull-up Resistance
HSTF with Pull-down Resistance
3-state Output and Input Buffer
H8CF with Pull-up Resistance
HSCF with Pull-down Resistance

8
B
8
12
12
12
12
12
12
9
9
9
9
9
9
11
11
9
9
9
9
9
9
11
11
11
13
13
13
13
13
13
S
S
8
S
8
S
9
9
9
9
9
9

OSCillator Circuits

2-294

2-399
2-400
2-401

IT10
HOC
HOS

2-402

HOCR

Input Buffer for Oscillator
Output Buffer for Oscillator and Input Buffer
Output Buffer for Oscillator and
Schmitt trigger Input Buffer
Output Buffer for Oscillator

0
S
S
B

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

Input Buffer
11B
Cell Svmbol

X

--[>r--

(Inverter)

Pin Name
IN

I

Propagation Delav Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
1. 60
0.04
1.54
0.04

5

Path
X .. IN

IN

Parameter

Pin Name

I "UHB" Version
I Number of BC

Symbol

Typ(ns)*

Input Loading
Factor (Rou)

Output Driving
Factor (Rou)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delav multiplier.

UHB-IlB-E1 I Sheet 1/1 I

I Page 20-1
2-295

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Input Buffer (Inverter)
with Pull-up Resistance
IlBU
5
Cell Svmbol
Pro~agation Delay Parameter
tU1)
tdn
Path
to
KCL
to
KCL
KCL2 CDR2
0.04
0.04
X -+ IN
1.60
1.54

I

X

I

-[>-

IN

Parameter

Pin Name

Input Loading
Factor (lu)

Pin Name
IN

Output Driving
Factor (lu)
36

*

lJ1!B-IlBU-El

2-296

Sheet 1/1 I

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the. maximum delay multiplier.

I Page 20-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Input Buffer (Inverter)
!lBD
with Pull-down Resistance
5
Propagation Dela" Parameter
Ce 11 S"mbo I
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
0.04
1.54
0.04
X -> IN
1. 60

I

X

J

-[>0-

IN

Parameter

Pin Name

Input Loading
Factor (Rou)

Pin Name
IN

Output Driving
Factor (Rou)
36

*

UHB-IlBD-El

Sheet 1/1 I

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are_given bv the maximum delay multiplier.

I Paoe

20-3

2-297

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

I2B
Input Buffer
Cell Svmbol

-[>-

X

(True)

I "ORB" Version
I Number of BC

I

Prooagation Delay Parameter
tuo
tdn
to
KCL
KCL
KCL2 CDR2
to
0.04
1.06
1.84
0.04

4
Path
X ... IN

IN

Parameter

Pin Name

Input Loading
Factor (R.u)

Pin Name
IN

Output Driving
Factor (R.u)
36

*

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

TTL Equivalent Circuit
r'-- ....... .,

,

,

,

I" . . . . . . . . . . . .

,

~
,
,

I

I

,

t

I

I

I

I

I

I

L. ............

74S04
74LS04

I

L ........ .. .J

74S04
74LS04

UHB-I2B-E1 I Sheet 1/1 I

2-298

I Pa!!;8 20-4

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Input Buffer (True)
I2BU
with Pull-up Resistance
4
Propagation Delay Parameter
Cell Svmbol
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
X ... IN
0.04
1.84
0.04
1.06

I

X

I

---t>-

IN

Parameter

Pin Name

Input Loading
Factor (iu)

Pin Name
IN

Output Driving
Factor (iu)
36

*

UHB-I2BU-E1 I Sheet 1/1 I

Svmbol

Typ(ns)'"

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page 20-5

2-299

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Input Buffer (True)
I2BD
with Pull-down Resistance
4
Cell Symbol
Prollaltation Delav Parameter
tUJ)
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
X ... IN
1.06 0.04
1.84
0.04

I

X

I

-t>-

IN

Parameter

Pin Name

Input Loading
Factor (lu)

Pin Name
IN

Output Driving
Factor (lu)
36

Symbol

Typ(ns)*

... Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay mult:;plier.

UHB-I2BD-E1 I Sheet 1/1 I

2-300

I Page 20-6

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

IKB
Clock Input Buffer
Cell Svmbol

X

-[>0-

I "UHB" Version
I Number of BC

I

(Inverter)
Pro.agation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.02
2.37
0.02
1.82

4
Path
X ... CI

eI

Parameter

Pin Name

Input Loading
Factor (lu)

Pin Name
CI

Output Driving
Factor (lu)
150

Svmbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

TTL Equivalent Circuit
r-----.,

~
,

,
,

,

,

L ___ .. _.I

74S40

"1"

UHB-IKB-E2 I Sheet: III I

Page 20-7

2-301

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Clock Input Buffer (Inverter)
IKBU
with Pull-un Resistance
4
Cell Svmbol
Pronagation Delav Parameter
tup
tdn
to
to
KCL
KCL
KCL2 CDR2
Path
2.37
X -+ CI
0.02
1.82
0.02

I

X

I

-{>o-

CI

Parameter

Pin Name

Input Loading
Factor (R.u)

Pin Name
CI

Output Driving
Factor (J1.u)
150

*

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

TTL Equivalent Circuit
,. ... - .... .,

It
'

,,

,

,
,
,

,

';~~~~'

"1"

UHB-IKBU-E2

2-302

Sheet 1/1 I

I Page 20-8

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Clock Input Buffer (Inverter)
IKBD
with Pull-down Resistance
4
Cell Svmbol
Pro}: agation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
X ... CI
2.37
0.02
1.82
0.02

I

X

I

--{:>o-

CI

Parameter

Pin Name

Input Loading
Factor (Rou)

Pin Name
CI

Output Driving
Factor (Rou)
150

Symbol

Typ(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiplier.
TTL Equivalent Circuit
r-----"

~
,

,

,

,

';~~~~'

ttl"

UHB-IKBD-E2 I Sheet 1/1 I

I Page 20-9
2-303

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

ILB
Clock Input Buffer
Cell Svmbol

(True)
Pro~agation

tup
to
2.03

X

---t>-

KCL
0.02

I

Delay Parameter
tdn
KCL
KCL2 CDR2
0.02

6
Path
X -> CI

CI

Parameter

Pin Name

Input Loading
Factor (R.u)

Pin Name
CI

Output Driving
Factor (R.u)
150

*

UHB- ILB-E2 LSheet 1/1 I

2-304

to
2.56

I lJliB Version
I Number of BC

Svmbol

TVIJ(ns

~,

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delaJ'_multiplier.

I Pal1;e 20-10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB" Version
Cell !'lame I Function
J Number of BC
Clock Input Buffer (True)
ILBU
with Pull-up Resistance
6
Cell Svmbol
Pro.agation Delay Parameter
tUD
tdn
to
to
KCL
KCL2 CDR2
Path
KCL
X .. CI
2.03
0.02
2.56
0.02

I

X

I

-t>-

CI

Parameter

Svmbol

Typ(ns)*

!!...

Pin Name

Input Loading
Factor (Rou)

Pin Name
CI

Output Driving
Factor (Rou)
150
* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiplier.

TTL Equivalent Circuit

,r ..

~

...... '"

I

,L _____
74S04
74LS04

,
,

,
.I

,. .......... .,
,
,
, r"'\ ,
r--

~

~l../

p+,

CI

,

. . . . . . . . . . . . .,1

74540

UHB-ILBU-E2 I Sheet 1/1 I

Pa.;e 20-11

2-305

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Clock Input Buffer (True)
6
ILBD
with Pull-down Resistance
Prota2ation Delav Parameter
Cell Svmbol
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
X ... CI
0.02
2.56
0.02
2.03

I

X

I

-t>-

CI

Parameter

Pin Name

Input Loading
Factor (.eu)

Pin Name
CI

Output Driving
Factor (.eu)
150

*

UHB-ILBD-E2

2-306

Sheet 1/1 I

Symbol

TVtl(ns)i'

Minimum values for the typical operating condition.
The values for the worst case operating condition
are 2iven bv the maximum delay multiplier.

I Palte 20-12

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

I "UHB Version
I Number of BC

I

IlC
CMOS Interface Input Buffer (Inverter)
Cell Svmbol
Propagation Delay Parameter
tUD
tdn
to
KCL
to
KCL
KCL2 CDR2
0.04
1. 32
0.04
1.44

X

-[>-

Pin Name
IN

Path
X .. IN

IN

Parameter

Pin Name

5

Svmbol

Typ(ns

*

Input Loading
Factor (Rou)

Output Driving
Factor (R.u)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-IlC-EI I Sheet 1/1 I

I Pas:e 20-13

2-307

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
CMOS Interface Input Buffer (Inverter)
with Pull-ul) Resistance
ncu
5
Ce 11 SYlllbol
Proca2ation Delav Parame~er
tuc
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
X ... IN
0.04
1.44
0.04
1.32

I

X

I

~

IN

Parameter

Pin Name

Input Loading
Factor (lu)

Pin Name

Output Driving
Factor (R.u)
36

IN

SYlllbol

1'yp(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB- IlCU-EI

2-308

Sheet 1/1 I

1 Pal1;e 20-14

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I "UHB" Version
Cell Name I Function
I Number of BC
CMOS Interface Input Buffer (Inverter)
neD
wi th Pull-down Resistance
5
Cell Svmbol
Propagation Delav Parameter
tup
tdn
to
KCL2 CDR2
Path
KCL
to
KCL
1.44
0.04
X ... IN
1.35
0.04

I

X

I

----{>o-

IN

Parameter

Pin Name

Input Loading
Factor (Rou)

Pin Name
IN

Output Driving
Factor (Rou)
36

*

UHB-I1CD-E1

Sheet 1/1 I

Svmbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are_given bv the maximum delay multiplier.

I Page 20-15

2-309

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

I "u1fB" Version
I Number of BC

I

I2C
CMOS Interface Innut Buffer (True)
Cell Svmbol
Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0.92
0.04
1.33
0.04

X

-[>-

Path
X ... IN

IN

Parameter

Pin Name

4

Symbol

Typ(ns)*

Input Loading
Factor (J1.u)

IfJI
Pin Name
IN

Output Driving
Factor (J1.u)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-I2C-E2 I Sheet 1/1 I

2-310

I Page 20-16

FUJITSU CXOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB" Version
Cell Name I Function
LNumber of BC
CXOS Interface Input Buffer
I2CU
with Pull-up Resistance (True)
4
Propagation Delay Parameter
Cell Svmbol
tup
tdn
Path
to
KCL
to
KCL
KCL2 CDR2
X ... IN
0.92
0.04
0.04
1.33

I

X

I

-t>-

IN

Symbol

Parameter

Typ(ns)*

I

Pin Name

Pin Name
IN

Input Loading
Factor (iu)

Output Driving
Factor (iu)
36

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-I2CU-E2 LSheet 1/1 I

I Page 20-17

2-311

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I "UHB" Version
Cell Name I Function
I Number of BC
CMOS Interface Input Buffer
with Pull-down Resistance (True)
4
I2CD
Cell Svmbol
Propagation Delay Parameter
tup
tdn
to
Path
to
KCL
KCL
KCL2 CDR2
X ... IN
0.04
0.04
0.92
1.33

I

X

I

-t>-

IN

Parameter

Pin Name

Pin Name
IN

Symbol

Typ(ns)*

Input Loading
Factor (Rou)

Output Driving
Factor (Rou)
36

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delav multiplier.

UHB-I2CD-E2 I Sheet 1/1 I

2-312

I Page 20-18

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB" Version
Cell Name I Function
I Number of BC
Schmitt Trigger Input Buffer
11S
(CMOS Type Inverter)
8
Cell Symbol
Propagation Delay Parameter
tup
tdn
Path
to
KCL2 CDR2
KCL
to
KCL
X ... IN
3.90
0.16
2.68
0.08

I

X

I

--f9o-

IN

Parameter

Pin Name

Input Loading
Factor (R.u)

Pin Name
IN

Output Driving
Factor (R.u)
18

*

UHB-IlS-El I Sheet 1/1 I

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given bv the maximum delay multiplier.

r Page

20-19

2-313

FuJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
I "UHB" Version
Cell Name I Function
I Number of BC
Schad t1: Trigger Input Buffer
IlSU
(CMOS Type, Inverter) with Pull-up Resistance
6
Propagation Delav Parameter
Cell Svrnbol
tUll
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
X .. IN
0.16
2.68
0.06
3.90

I

X

I

~

IN

Parameter

Pin Name

Input Loading
Factor (iu)

Pin Name
IN

Output Driving
Factor (iu)
16

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum de1a.ymultilllier.

UHB-IlSU-El I Sheet 1/1 I

2-314

I Page 20-20

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Schmitt Trigger Input Buffer
(CMOS Type Inverter) with Pull-down Resistance
IlSD
8
Cell S~"Illbol
Pro;agation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
X ... IN
3.90
0.16
0.08
2.68

I

X

I

----iPo-

IN

Parameter

Pin Name

Input Loading
Factor _flU)

Pin Name
IN

Output Driving
Factor (lu)
18

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-IlSD-EI

Sheet 1/1 I

I Page 20-21

2-315

FUJITSU C~OS GATE ARRAY ~~IT CELL SPECIFICATION
I UHB Version
Cell Name I Func1:ion
I Number of BC
Schmitt Trigger Input Buffer
(CMOS Type, True)
I2S
8
Cell Symbol
Propagation Delav Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
Path
0.16
3.08
0.10
X -+ IN
2.48

I

X

I

~

IN

Parameter

Pin Name

Input Loading
Factor (iu)

Pin Name
IN

Output Driving
Factor (iu)
18

Svmbol

Typ(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-I2S El I Sheet 1/1 I

2-316

I Pal(e 20-22

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
I tiRE" Version
Cell Name I Function
I Number of BC
Schmitt Trigger Input Buffer
I2SU
(CMOS Type, True) with Pull-up Resistance
8
Cell Svmbol
Pro.agation Delav Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
X -+ IN
2.48
0.16
3.08
0.10

I

X

I

--i9-

IN

Parameter

Pin Name

Input Loading
Factor (iu)

Pin Name
IN

Output Driving
Factor (iu)
18

Svmbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are ~iven bv the maximum delay multiplier.

UHB-I2SU-El

Sheet 1/1 I

I Page 20-23

2-317

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB" Version
Cell Name I Function
I Number of BC
Schmitt Trigger Input Buffer
12SD
(CMOS Type True with Pull-down Resistance
8
Cell Svmbol
Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
X ... IN
2.48
0.16
3.08
0.10

I

X

I

--w-

IN

Parameter

Pin Name

Input Loading
Factor (R.u)

Pin Name
IN

Output Driving
Factor (R.u)
18

*

UHB-I2SD-El I Sheet 111 I

2-318

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

I Page 20-24

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Schmitt Trigger Input Buffer
IlR
(TTL Type Inverter)
8
Cell Symbol
ProJagationDelay Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
Path
4.48
0.16
2.36
0.08
X .. IN

I

I

I
!

X

--{Po-

IN

Parameter

Pin Name

Input Loading
Factor (iu)

Pin Name
IN

Output Driving
Factor (iu)
18

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-IlR-E2 I Sheet 1/1 I

I Page 20-25

2-319

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I "UHB" Version
Cell Name I Function
I Number of BC
Schmitt Trigger Input Buffer
(TTL Type, Inverter) with Pull-up Resistance
IlRU
8
Cell Symbol
Propagation Delay Parameter
tup
tdn
KCL
KCL2 CDR2
to
KCL
to
Path
2.36
0.08
4.48
0.16
X -+ IN

I

X

I

--P-

IN

Parameter

Pin Name

Input Loading
Factor (Lu)

Pin Name
IN

Output Driving
Factor (.tu)
18

I

Symbol

Typ(ns)*

Ell
* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-IlRU-E2

·2-320

Sheet 1/1 I

Page 20-26

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Schmitt Trigger Input Buffer
IIRD
(TTL Type Inverter) with Pull-down Resistance
8
Cell Symbol
Propagation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
KCL
to
Path
4.48
0.16
2.36
0.08
X -+ IN

I

X

I

----f9r-

IN

Parameter

Pin Name

Input Loading
Factor (tu)

Pin Name
IN

Output Driving
Factor (tu)
18

Symbol

Typ(ns)*

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB- IlRD-E2

Sheet 1/1 I

I Page 20 27

2-321

FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
I "UHB" Version
Ce11 Name I Function
I Number of BC
Schmitt Trigger Input Buffer
(TTL Type True)
I2R
8
Ce11 Symbol
Propagation Delay Parameter
tup
tdn
to
to
KCL
KCL
KCL2 CDR2
Path
2.24
3.72
0.13
0.16
X'" IN

I

X

I

--%>-

IN

Symbol

Parameter

Pin Name

Input Loading
Factor (J1.u)

Pin Name
IN

Output Driving
Factor (J1.u)
18

Typ(ns)'"

"\

* Minimum

values for the typical opera~ing condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

UHB-I2R-El I Sheet 1/1 I

2-322

I Page 20-28

FGJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION
I UHB" Version
Cell Name I Function
I Number of BC
Schmitt Trigger Input Buffer
I2RU
(TTL Type, True) with Pull-IlP Resistance
8
Cell Sv"lllbol
Propagation Delav Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Pa1:h
2.24
X -+ IN
0.16
3.72
0.13

I

X

I

--w-

IN

Parameter

Pin Name

Input Loading
Factor (iu)

Pin Name
IN

Output Driving
Factor (iu)
18

*

UHB-I2RU-E1 I Sheet 1/1 I

Symbol

Typ(ns)":

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Page 20-29

2-323

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Schmitt Trigger Input Buffer
CIT!. Type, True) with Pull-down Resistance
I2RD
8
1
Cell Svmbol
Propa2ation Delav Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
X .. IN
2.24
0.16
3.72
0.13

I

X

~

IN

Parameter

Pin Name

Input Loading
Factor (R.u)

Pin Name
IN

Output Driving
Factor (R.u)
18

*

UHB-I2RD-El

2-324

Sheet 1/1 I

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are 2iven by the maximum delay multiplier.

I Page 20-30

I UHB" Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

I

OIB
Output Buffer(IOL=3.2mA Inverter)
Cell Symbol
Pro~al!:ation Delay Parameter
tdn
tup
KCL2 CDR2
KCL
to
KCL
to
1. 93 0.056
2.24 0.124
(5.29)
(9.68)

OT

-{>-

3

Path
OT .. X

X

Parameter

Pin Name
OT

Input Loading
Factor (Lu)
2

Pin Name

Output Driving
Factor (Lu)

*

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are dven by the maximum delay multiplier.

Note: 1. The unit of KcL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-01B-E4 I Sheet 1/1 I

I Page 20-31

2-325

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

UHB Version
I Number of BC

I

OIL
Output Buffer(IOL=12mA
Cell Symbol

OT

Inverter)
Propagation Delay Parameter
tup
tdn
KCL
KCL2 CDR2
to
KCL
to
2.29 0.037
2.47 0.041
(4.51)
(4.93)

-t>-

3

Path
OT .. X

X

Parameter

Pin Name
OT

Input Loading
Factor (luJ
2

Pin Name

Output Driving
Factor (lu)

Symbol

Typ(ns)*

• Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
Note: 1. The unit of KcL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu'.
logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-OIL-E3 I Sheet 1/1

2-326

I Page 20-32

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I "UHB Version
Cell Name I Function
I Number of BC
Output Buffer(IOL=3.2mA, Inverter)
OlR
with Noise Limit Resistance
5
Cell Symbol
Propagation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
Path
3.30 0.056
5.18
0.13
OT ... X
(6.66)
(12.98)

I

OT

I

-{>-

X

Parameter

Pin Name
OT

Input Loading
Factor (R.u)
1

Pin Name

Output Driving
Factor _lR.u)

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are Itiven bv the maximum delay multiplier.

Note: 1. The unit of KCL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-01R-E3 I Sheet 1/1 I

I Page 20-33

2-327

UHB Version
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Ce1l Na-me I Function
I Number of BC
Output Buffer(IOL=12mA, Inverter)
01S
with Noise Limit Resistance
5
Ce1l Symbol
Propagation Delay Parameter
tup
tdn
lCL2 CDR2
lCL
Path
to
lCL
to
OT .. X
4.02 0.038
6.39 0.054
(6.30)
(9.63)

I

OT

I

-[>-

X

Parameter

Pin Name
OT

Pin Name

Symbol

Typ(ns)*

Input Loading
Factor (R.u)
1

Output Driving
Factor (R.u)

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are dven by the maximum delay multiplier.

Note: 1. The unit of KCL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-OIS-E3 I Sheet 1/1 I

2-328

I Page 20-34

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name J Function

I UHS Version
I Number of BC

J

J

02B
Output Buffer (lOL=3. 2mA True)
Cell Symbol
ProJ:agation Delay Parameter
tup
tdn
to
KCL
KCL2 CDR2
to
KCL
1. 70 0.056
1. 75 0.124
(9.19)
(5.09)

-[>-

OT

2
Path
OT ... X

X

Parameter

Pin Name
OT

Input Loading
Factor (.tu)
4

Pin Name

Output Driving
Factor (.tu)

*

Symbol

Typ(ns)~t

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum de lay mul tiplier.

TTL Equivalent Circuit
,. ..........

r ............

I

I

I

I

~
I

I

I

I

,
I

"
I

I

I
•

~

.......... ""

74S04
74LS04

0

............ J

74S04
74LS04

Note: 1- The unit of KCL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHS-02B-E4 I Sheet 1/1 I

Page 20-35

2-329

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

UHB Version
I Number of BC

I

I

02L
Output BufferOOL=12mA Truel
Cell Symbol
Pro~aJ;tation Delay. Parameter
tup
tdn
to
KCL
KCL2 .CDR2
to
KCL
1.98 0.041
2.09 0.037
(4.44)
(4.31)

OT

----[>-

2
Path
OT .. X

X

Parameter

Pin Name
OT

Input Loading
Factor (iu)
4

Pin Name

Output Driving
Factor (iu)

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delaj'multiplier.

Note: 1. The unit of KCL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-02L-E3 I Sheet 111 I

2-330

I Page 20-36

I "UHB Version
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
I Number of BC
Output Buffer(IOL=3.2mA, True)
02R
with Noise Limit Resistance
4
Cell Symbol
Pro~agation Delay Parameter
tup
tdn
J(CL2 CDR2
to
KCL
to
KCL
Path
2.99 0.056
4.69
0.13
OT .. X
(6.35)
(12.49)

I

OT

I

-[>--

X

Parameter

Pin Name
OT

Input Loading
Factor (lu)
2

Pin Name

Output Driving
Factor (lu)

*

Symbol

Typ(ns)*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Note: 1- The unit of KcL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-02R-E3 I Sheet III I

I Page 20-37

2-331

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Output Buffer(IOL=12mA, True)
02S
with Noise Limit Resistance
4
Cell Symbol
Pro~agation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
Path
3.71 0.038
5.87 0.054
OT .. X
(5.99)
(9.11)

I

OT

I

-[>-

X

Parameter

Pin Name
OT

Pin Name

Symbol

Typ(ns

*

Input Loading
Factor (.tu)
2

Output Driving
Factor (.tu)

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are Riven by the maximum delay multiplier.

Note: 1- The unit of KcL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's

logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-02S-E3 I Sheet 1/1 I

2-332

I Page 20-38

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Output Buffer(IOL=24mA, True)
0252
with Noise Limit Resistance
6
Cell Symbol
Propaution Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
Path
0.06
5.27 0.032
9.51
OT .. X
(7.19)
(13.11)

I

OT

I

-t>-

X

Parameter

Pin Name
OT

Input Loading
Factor Clu)
2

Pin Name

Output Driving
Factor Clu)

Symbol

TypCns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Note: 1. The unit of leL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's

logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-02S2-E3 I Sheet 1/1 I

I Page 20-39

2-333

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Tri-state Output Buffer(IOL=3.2mA, True)
04R
with Noise Limit Resistance
5
Cell Symbol
Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
0.13
3.12 0.056
5.66
OT" X
(6.76)
(14.11)

I

OT

I

--tr

X

C

to
2.22
(13.44)

Pin Name
OT
C

Pin Name

*

Input Loading
Factor (.tu)
2
2
Output Driving
Factor (.tu)

to
3.07
(13.44)

L" Z
KCL

to
6.47
(14.92)

*

H .. Z
KCL

*

to
3.20
(14.92)

Z .. L
KCL
0.13

C .. X

Z .. H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

wi"
LSI

21d2

e

~

-

3

Path
OT" X

X

Parameter

Pin Name
OT

Input Loading
Factor (tu)
2

Pin Name

Output Driving
Factor (tu)

Symbol

TY'P(ns)~t

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay_ multilllier.

Note: 1. The unit of KcL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's

logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-OIBF-El I Sheet 111 I

J Page 20-87
2-339

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
UHB Version
Cell Name I Function
I Number of BC
Output Buffer (IOL=8mA, Inverter)
01RF
with Noise Limit Resistance
5
Cell Symbol
PrQ~agation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
KCL
to
Path
OT .. X
3.39 0.056
5.60 0.063
(6.75)
(9.38)

I

OT

I

--[>-

X

Parameter

Pin Name
OT

Pin Name

Symbol

Typi

nsJ_*

Input Loading
Factor (iu)
1

Output Driving
Factor (iu)

* Minimum values

for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Note: 1. The unit of KCL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-01RF-EI I Sheet 1/1 I

2-340

-

I Page 20-88

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

02BF
Output Buffer (IOL=8mA
Cell Symbol

--[>-

I

True)
Pro~agation

tup
to
KCL
1. 76 0.056
(5.12)

OT

I UHB Version
I Number of BC

to
1.52
(5.30)

Delay Parameter
tdn
KCL2 CDR2
KCL
0.063

2
Path
OT ... X

X

Parameter

Pin Name
OT

Input Loading
Factor (lu)
4

Pin Name

Output Driving
Factor (lu)

Symbol

Typ(ns)*

* Minimum

values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

TTL Equivalent Circuit
,._a ___ ..

,.. -----

~

~
,
,
,

I

I

I

,

•

I

I

I

•

I

I

L _____ "

74S04
74LS04

L . ___ . "

74504
74LS04

Note: 1. The unit of RCL is ns/pF.

2. Output load capacitance of 60 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-02BF-EI

Sheet 1/1 I

j Page 20-89

2-341

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Output Buffer (IOL=8mA. True)
02RF
with Noise Limit Resistance
4
Cell Symbol
Prot:aJ!.ation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
KCL
to
Path
3.08 0.056
OT .. X
5.11 0.063
(6.44)
(8.89)

I

OT

I

-[>-

X

Parameter

Pin Name
OT

Pin Name

Symbol

Typlns

*

Input Loading
Factor (R.u)
2

Output Driving
Factor (R.u)
• Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

Note: 1- The unit of leL is ns/pF.
2. Output load capacitance of 60 pF is used for FUjitsu's

logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

UHB-02RF-El I Sheet 1/1 1

2-342

I Page 20-90

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Tri-state Output Buffer (IOL=8mA, True)
04RF
with Noise Limit Resistance
5
Cell Symbol
Propagation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
KCL
to
Path
OT .. X
3.21 0.056
5.96 0.070
(6.85)
(10.51)

I

OT

I

--i1

X

C

to
2.62
(15.89)

Pin Name
OT
C

Pin Name

*

Input Loading
Factor (tu)
2
2
Output Driving
Factor (tu)

to
3.30
(15.89)

L .. Z
KCL

Z .. L

to
6.82
(11.37)

*

H .. Z
KCL

*

C ..

KCL
0.070

X

Z .. H

to
3.21
(11. 37)

KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

~'

= 21dl

C

;:L

(a) Measurement of tpd at LZ and ZL.

J:l

lc

,-I

1"2

Idl

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KcL is ns/pF.
2. Output load capacitance of 65 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-04RF-EI

Sheet 1/1 I

I Page 20-91
2-343

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I

I

04TF
Tri-state Output Buffer (IOL=8mA True)
Cell Symbol
Pro~agation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
KCL
to
2.51 0.056
3.27 0.063
(6.15)
(7.37)

OT

---f1-

t+

Path
OT .. X

X

C

to
2.29
(14.80)

Pin Name
OT
C

Pin Name

Input Loading
Factor (R.u)
4
2
Output Driving
Factor (R.u)

to
3.12
(14.80)

L .. Z
KCL

*

H .. Z
KCL

*

to
3.35
(7.45)

to
2.37
(7.45)

Z .. L
KCL
0.063

C .. X

Z .. H
KCL
0.056

* These

values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ. ZL. HZ and ZH are as follows:

c=HR'2~
LSI
C

~

(a) Measurament of tpd at LZ and ZL.

W

lc 1'2~

~

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL is ns/pF.
2. Output load capacitance of 65 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-04TF-E1

2-344

Sheet 1/1 I

I Page 20-92

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I UHB Version
I Number of BC

I

I

H6T
Tri-state Output IOL=3.2mA) & Input Buffer (True)
Cell Symbol
ProJ:agation Delay Parameter
tup
tdn
KCL2 CDR2
KCL
to
KCL
to
1.84
0.04
1.06 0.04
2.42 0.056
2.52
0.13
(7.18)
(13.57)
IN
OT

=cr-

8
Path
X" IN
OT .. X

X

C

to
2.07
(15.35)

Pin Name
OT
C

Pin Name
IN

L .. Z
KCL

to
2.55
(13.60)

*

Z .. L
KCL
0.13

c..

X

Input Loading
Factor _(Lu~
4
2

Output Driving
Factor (Lu)
36

to
3.41
(15.35)

H .. Z
KCL

to
2.31
(13.60)

*

Z" H
KeL
0.056

* These

values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

c:H'-

2ldl

LSI

C

~

(a) Measurement of tpd at LZ and ZL.

LSI

lc

,I

1-

2kll

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for FUjitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the

simulation.
UHB-H6T-E4 I Sheet 1/1 I

I Page 20-45

2-345

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB" Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=3.2mA) & Input Buffer (True)
with Pull-up Resistance
H6TU
8
Cell Symbol
Pro~agation Delay Parameter
tup
tdn
XCL2 CDR2
to
to
XCL
XCL
Path
1.84
0.04
1.06 0.04
X -+ IN
2.42 0.056
2.52
0.13
OT -+ X
(13.57)
(7.18)

1

IN
OT

I

=rr

X

C

to
2.07
(15.35)

Pin Name
OT
C

Pin Name
IN

*

Input Loading
Factor. (.tut
4
2
Output Driving
Factor (.tu)
36

to
3.41
(15.35)

L'" Z
KCL

*

H-+ Z
KCL

*

to
2.55
(13.60)

to
2.31
(13.60)

Z -+ L
KCL
0.13

C ... X

Z ... H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

c:H

2idl
R
-

LSI

C

,;L

(a) Measurement of tpd at LZ and ZL.

r:l

lc

,I

1'.2kll

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KcL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6TU-E4 I Sheet 1/1 I

2-346

I Page 20-46

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I DBB Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=3.2mA) & Input Buffer (True)
H6TD
with Pull-down Resistance
8
Cell Symbol
ProJ:agation Delay Parameter
tdn
tup
KCL
KCL2 CDR2
KCL
to
to
Path
1.84
0.04
1.06 0.04
X .. IN
2.42 0.056
0.13
OT .. X
2.52
(7.18)
(13.57)

I

IN
OT

I

~

X

C

to
2.07
(15.35)

Pin Name
OT
C

Pin Name
IN

*

L .. Z
KCL

to
2.55
(13.60)

*

Z ... L
KCL
0.13

C ..

X

Input Loading
Factor (.tu)
4

2
Output Driving
Factor (.tu)
36

to
3.41
(15.35)

H ... Z
KCL

to
2.31
(13.60)

*

Z ... H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

cH'LSI

2iU2

c

~

(a) Measurement of tpd at LZ "and ZL.

I

LSI

I
I

lc

~

1"'"

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6TD-E4

Sheet 1/1 I

I Page 20-47

2-347

~ UHB

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

Version
I Number of BC

I

I

H6W
Tri-state Output(IOL=12mA) & Input Buffer JTrue)
Cell Symbol
Pr~ajgation Delay Parameter
tdn
tup
KCL2 CDR2
KCL
to
KCL
to
1.64 0.04
1.06 0.04
4.12 0.047
3.02 0.036
(6.25)
(8.12)
IN
OT

=cr-

8
Path
X oO IN
OToO X

X

C

to
2.96
(20.25)

Pin Name
OT
C

Pin Name
IN

*

Input Loading
Factor (lul
4
2
Output Driving
Factor (lu)
36

to
4.03
(20.25)

LoO Z
KCL

to
3.69
(7.69)

*

H .. Z
KCL

to
2.72
(7.69)

*

Z .. L
KCL
0.047

C oO X

Z .. H
KCL
0.036

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

cij'.

21d2

LSI

C

~

(a) Measurement of tpd at LZ and ZL.

LSI

lc

,I

1-

Ull

(b) Measurement of tpd at HZ and ZH.

Note: l. The unit of leL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6W-E3 I Sheet 1/1 I

2-348

I Page 20-46

1 "UHB" Version
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name J Function
I Number of BC
Tri-state Output(IOL=12mA) & Input Buffer (True)
with Pull-up Resistance
H6WU
8
Cell Symbol
Prougation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
Path
to
KCL
X .. IN
1.84 0.04
1.06 0.04
OT .. X
4.12 0.047
3.02 0.038
(8.12)
(6.25)

I

IN
OT

I

=rr

X

C

to
2.96
(20.25)

Pin Name
OT
C

Pin Name
IN

Input Loading
Factor (R.u)
4
2
Output Driving
Factor (R.u)
36

z ..

L .. Z
KCL

to
3.69
(7.69)

*

H ... Z

to
4.03
(20.25)

KCL

to
2.72
(7.69)

*

L
KCL
0.047

C ..

X

Z ... H
KCL
0.038

* These

values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

~R-

2ldl

LSI

LSI
C

,I

~

(a) Measurement of tpd at LZ and ZL.

lc

1'.2

ldl

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KcL for paths OT, C to

~

is ns/pF.

2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6WU-E3 I Sheet 1/1 I

I Pas:e 20-49

2-349

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I "UHB" Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=12mA) & Input Buffer (True)
H6 ..'D
with Pull-down Resistance
8
Cell Symbol
Propagation Delay Parameter
tup
tdn
to
to
KCL
KCL2 CDR2
KCL
Path
1.84 0.04
1.06 0.04
X .. IN
4.12 0.047
3.02 0.038
OT .. X
(6.25)
(8.12)
IN

I

OT

I

=rr-

X

C

to
2.96
(20.25)

Pin Name
OT
C

Pin Name
IN

Input Loadi%18
Factor (Lu)
4
2
Output Driving
Factor (Lu)
36

to
4.03
(20.25)

L ... Z
KCL

to
3.69
(7.69)

*

H .. Z
KCL

to
2.72
(7.69)

*

Z" L
KCL
0.047

C .. X

Z .. H
KCL
0.038

* These

values are subject to external loadi%18 condition.
Measurement circuits of propaga,tion delay time
at LZ, ZL, HZ and ZH are as follows:

~RLSI

2kS2

c

I

I
LSI

lc

,L

~

(a) Measurement of tpd at LZ and ZL.

I

1'"'"

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to

~

is ns/pF.

2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6WD-E3 I Sheet 1/1 I

2-350

I Page 20-50

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=3.2mA)
H6C
& CMOS Interface Input Buffer (True)
8
Cell Symbol
Pro]: agation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
Path
0.04
X .. IN
0.92 0.04
1.33
2.52
0.13
OToO X
2.42 0.056
(7.18)
(13.57)

I

IN
OT

I

=cr-

X

C

to
2.07
(15.35)

Pin Name
OT
C

Pin Name
IN

*

Input Loading
Factor (R.u)
4
2
Output Driving
Factor (R.u)
36

to
3.41
(15.35)

LoO Z
KCL

*

H ... Z
KCL

*

to
2.55
(13.60)

to
2.31
(13.60)

Z ... L
KCL
0.13

C oO

X

Z ... H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ. ZL. HZ and ZH are as follows:

c:B

2kSl
R
-

LSI

C

~

(a) Measurement of tpd at LZ and ZL.

~ lc
,I

1" ,..

(b) Measurement of tpd at HZ and ZH.

Note: 1- The unit of XcL for paths OTt C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6C-E4 I Sheet 1/1 I

I Page 20-51

2-351

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I "UHB Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=3.2mA) & CMOS Interface
H6CU
Input Buffer (True) with Pull-up Resistance
8
Cell Symbol
ProtaJ:(ation Delay Parameter
tup
tdn
KCL2 CDR2
KCL
to
KCL
to
Path
0.04
X .. IN
0.92 0.04
1.33
0.13
OT .. X
2.42 0.056
2.52
(7.18)
(13.57)
IN

I

OT

I

=cr-

X

C

to
2.07
(15.35)

Pin Name
OT
C

Pin Name
IN

*

Input Loading
Factor (.tu)
4
2
Output Driving
Factor (.tu)
36

to
3.41
(15.35)

L" 2
KCL

to
2.55
(13.60)

*

H .. 2
KCL

*

to
2.31
(13.60)

2 .. L
KCL
0.13

C .. X

2" H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at L2, 2L, H2 and 2H are as follows:

cH

21Ul
R
-

LSI

LSI

C

~

(a) Measurement of tpd at L2 and 2L.

lc

~

1'. "'"

(b) Measurement of tpd at H2 and 2H.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6CU-E4

2-352

Sheet 1/1 I

I Page 20-52

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
J "UHB" Version
Cell Name I Function
J Number of BC
Tri-state Output(IOL=3.2mA) & CMOS Interface
H6CD
Input Buffer =0

(b) Measurement of tpd at HZ and ZH.

e

to X is ns/pF.

2. Output load capacitance of 85 pF is used for FUjitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H8S-E2 I Sheet 1/1 I

I Page 20-81

2-381

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
UHB Version
Cell Name
Function
Number of BC
Tri-state Output(IOL=3.2mA) & Schmitt Trigger
Input Buffer(CMOS Type,True) wi Noise Limit Resistance
H8SU
w/ Pull-up Resistance
13
Cell Symbol
Pro~agation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
Path
0.10
2.48 0.16
3.08
X .. IN
0.13
3.12 0.056
5.66
OT .. X
(7.88)
(16.71)
IN

I

OT

=rr-

X

C

to
2.22
(16.44)

Pin Name
OT
C

Pin Name
IN

*

Input Loading
Factor (l.u)
2
2
Output Driving
Factor (lu)
18

to
3.07
(16.44)

z .. L

L .. Z
KCL

to
6.47
(17.52)

*

H .. Z
KCL

to
3.20
(17.52)

*

KCL
0.13

C .. X

Z .. H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

c=H'LSI

2kS2

.

C

~

(a) Measurement of tpd at LZ and ZL.

I

LSI

I
I

ic

~

1-

2>"

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H8SU-E21 Sheet 1/1 I

2-382

I Page 20-82

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name Function
Number of BC
Tri-state Output(IOL=3.2mA) & Schmitt Trigger
Input Buffer(CMOS Type ,True) wi Noise Limit Resistance
H8SD
w/- Pull-down Resistance
13
Cell Symbol
Pro.a.l(ation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
Path
X ... IN
2.48 0.16
3.08
0.10
OT ... X
3.12 0.056
5.66
0.13
(16.71)
(7.88)
IN
OT

~

X

C

to
2.22
(16.44)

Pin Name
OT
C

Pin Name
IN

Input Loading
Factor (tu)
2
2
Output Driving
Factor (tu)
18

to
3.07
(16.44)

L ... Z
KCL

to
6.47
(17.52)

*

H ... Z
KCL

to
3.20
(17.52)

*

Z ... L
KCL
0.13

C ...

X

Z ... H
KCL
0.056

* These

values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

cij'

= 21d2

C

~

(a) Measurement of tpd at LZ and ZL.

LSI

lc

,I

1'='

1d2

(b) Measurement of tpd at HZ and ZH.

Note: l. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for FUjitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-HBSD-E2! Sheet 1/1 I

I Page 20-83
2-383

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
1 UHB Version
Cell Name I Function
Number of BC
Tri-state Output(IOL=3.2mA) & Schmitt Trigger
H8R
Input Buffer (TTL Type True) wI Noise Limit Resistance
13
Cell Symbol
Propagation Delay Parameter
tup
tdn
J(CL
J(CL2 CDR2
J(CL
to
to
Path
2.24 0.16
0.13
X ... IN
3.72
OT ... X
3.12 0.056
5.66
0.13
(7.88)
(16.71)
IN

1

OT

I

=rr-

X

C

to
2.22
(16.44)

Pin Name
OT
C

Pin Name
IN

*

Input Loading
Factor (lu)
2
2
Output Driving
Factor (lu)
18

to
3.07
(16.44)

L ... Z
J(CL

to
6.47
(17.52)

*

H'" Z
J(CL

to
3.20
(17.52)

*

Z ... L
J(CL
0.13

C ... X

Z ... H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

cl
LSI

2kS2
R
-

c

,...:L

(a) Measurement of tpd at LZ and ZL.

I

I
LSI

I

lc
.I

t"' .

(b) Measurement of tpd at HZ and ZH.

Note: 1- The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for FUjitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H8R-E2 I Sheet 1}1 I

2-384

I Page 20-84

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Ce11 Name Function
Number of BC
Tri state Output(IOL=3.2mA) & Schmitt Trigger
Input Buffer(TTL Type, True) w/ Noise Limit Resistance
H8RU
wi Pull-up Resistance
13
Cell Symbol
Propa.e,ation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
KCL
to
Path
X .. IN
2.24 0.16
3.72
0.13
3.12 0.056
5.66
0.13
OT .. X
(7.88)
(16.71)
IN
OT

~

X

C

to
2.22
(16.44)

Pin Name
OT
C

Pin Name
IN

*

Input Loading
Factor (iu)
2
2
Output Driving
Factor (iu)
18

to
3.07
(16.44)

L .. Z
KCL

to
6.47
(17.52)

*

H .. Z
KCL

to
3.20
(17.52)

*

Z .. L
KCL
0.13

C ..

X

Z .. H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

cH

= 2 \ill
R

I LSI

C

I
I

lc

rI

rL

(a) Measurement of tpd at LZ and ZL.

1'0

2

\ill

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for FUjitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H8RU-E2

.§~~~1."",1 / 1

I

I Page 20-85
2-385

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name Function
Number of BC
Tri-state Output(IOL=3.2mA) & Schmitt Trigger
Input Buffer(TTL Type, True) wI Noise Limit Resistance
w/" Pull-down Resistance
H8RD
13
Cell Symbol
Pro.a~ation Delay Parameter
tup
tdn
KCL2 CDR2
KCL
to
KCL
to
Path
2.24 0.16
0.13
X -+ IN
3.72
OT .. X
0.13
3.12 0.056
5.66
(7.88)
(16.71)
IN
OT

=cr-

X

C

to
2.22
(16.44)

Pin Name
OT
C

Pin Name
IN

*

Input Loadins
Factor (R.u)
2
2
Output Driving
Factor (lu)
18

to
3.07
(16.44)

L-+ Z
lCL

to
6.47
(17.52)

*

H-+ Z
KCL

to
3.20
(17.52)

*

Z .. L
KCL

C -+ X

0.13

Z .. H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

CJ1'-

2kSl

LSI

C

~

(a) Measurement of tpd at LZ and ZL.

LSI

lc

.J:

1

02

..

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for FUjitsu's

logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H8RD-E2 I Sheet 1/1 I

2-386

I Page 20-86

I "UHB Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

I

H6TF
Tri-state Output IOL=8mA) & Input Buffer (True)
Cell Symbol
Propagation Delay Parameter
tup
tdn
to
KCL
KCL2 CDR2
KCL
to
1.06 0.04
1. 84 0.04
2.51 0.056
3.27 0.063
(8.63)
(7.27)
IN
OT

=tfl

8
Path
X .. IN
OT .. X

X

C

to
2.29
(18.62)

Pin Name
OT
C

Pin Name
IN

*

Input Loading
Factor (£u)
4
2
Output Driving
Factor (£u)
36

to
3.12
(18.62)

L .. Z
KCL

to
3.35
(8.71)

*

H .. Z
KCL

to
2.37
(8.71)

*

Z .. L
KCL
0.063

C ..

X

Z .. H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

D{'

= 2kSl

C

~

(a) Measurement of tpd at LZ and ZL.

I

LSI

I
I

lc

~

1'=2

kQ

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's

logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6TF-E1 I Sheet 1/1 I

I Page 20-93
2-387

Ell

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
UHB Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=8mA) & Input Buffer (True)
H6TFU
with Pull-up Resistance
8
Cell Symbol
Pro;agation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
Path
1.06 0.04
1.84 0.04
X .. IN
2.51 0.056
3.27 0.063
OT" X
(7.27)
(8.63)
IN

I

OT

I

~

X

C

to
2.29
(18.62)

Pin Name
OT
C

Pin Name
IN

Input Loading
Factor (Lu)
4
2
Output Driving
Factor (Lu)
36

to
3.12
(18.62)

L .. Z
KCL

to
3.35
(8.71)

*

H .. Z
KCL

to
2.37
(8.71)

*

Z .. L
KCL
0.063

C .. X

Z .. H
KCL
0.056

* These

values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

~RLSI

2kSl

c

~

(a) Measurement of tpd at LZ and ZL.

I

LSI

I
I

lc

,L

1-

nil

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6TFU-EI J Sheet 1/1 I

2-388

J Page 20-94

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I "UHB" Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=8mA) & Input Buffer (True)
H6TFD
with Pull-down Resistance
8
Cell Symbol
Pro~agation Delay Parameter
tup
tdn
J(CL
J(CL2 CDR2
J(CL
to
to
Path
X .. IN
1. 06 0.04
1.84 0.04
2.51 0.056
3.27 0.063
OT .. X
(7.27)
(8.63)

I

IN
OT

I

=cr-

X

C

to
2.29
(18.62)

Pin Name
OT
C

Pin Name
IN

Input Loading
Factor (lu)
4
2
Output Driving
Factor (lu)
36

to
3.12
(18.62)

z ..

L .. Z
J(CL

to
3.35
(8.71)

*

H .. Z
J(CL

to
2.37
(8.71)

*

L
lCL
0.063

C ..

X

Z .. H
leL
0.056

* These

values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

~R'2~
LSI
C

,;L

(a) Measurement of tpd at LZ and ZL.

I

I
LSI

I

lc 1"2~

,I

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of lCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for FUjitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6TFD-El I Sheet 1/) I

I Page 20-95

2-389

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
UHB Version
Cell Name I Function
J Number of BC
Tri-state Output(IOL=8mA)
H6CF
& CMOS Interface Inout Buffer (True)
8
Ce 11 Symbol
Pro~aJtation Delay Parameter
tdn
tuo
RCL2 CDR2
RCL
to
RCL
Path
to
1.33 0.04
X .. IN
0.92 0.04
3.27 0.063
OT .. X
2.51 0.056
(8.63)
(7.27)
IN

I

OT

I

=tr-

X

C

to
2.29
(18.62)

Pin Name
OT
C

Pin Name
IN

L .. Z
RCL

to
3.35
(8.71)

*

Z" L
RCL
0.063

C .. X

Input Loading
Factor (l.u)
4

2
Output Driving
Factor (lu)
36

to
3.12
(18.62)

H" Z
RCL

to
2.37
(8.71)

*

Z" H
KCL
0.056

* These

values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ. ZL. HZ and ZH are as follows:

~'.2~
LSI

I

I
LSI

C

lc

rL

~

(a) Measurement of tpd at LZ and ZL.

I

(b)

>R"2kSl

~

rr'r7

Measurement of tpd at HZ and ZH.

Note: 1. The unit of RCL for paths OT. C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6CF-El I Sheet 111 I

2-390

I Page 20-96

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=6mA) & CMOS Interface Input Buffer
H6CFU
(True) with Pull-up Resistance
8
Cell Symbol
ProFagation Delay~Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
Path
0.92 0.04
1.33 0.04
X" IN
OT .. X
2.51 0.056
3.27 0.063
(6.63)
(7.27)

I

IN
OT

I

~

X

C

to
2.29
(16.62)

Pin Name
OT
C

Pin Name
IN

*

Input Loading
Factor (iu)
4
2
Output Driving
Factor (iu)
36

to
3.12
(18.62)

L .. Z
KCL

to
3.35
(6.71)

*

H .. Z
KCL

to
2.37
(6.71)

*

Z .. L
KCL
0.063

C ..

X

Z .. H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

cB'

= 2k52

C

".L

(a) Measurement of tpd at LZ and ZL.

LSI

lc

~

t·,

k52

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 65 pF is used for FUjitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6CFU-El I Sheet 1/1 I

I Page 20-97
2-391

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
J UHB Version
Cell Name J Function
I Number of BC
Tri-state Output(IOL=8mA) & CMOS Interface Input Buffer
H6CFD
(True) with Pull-down Resistance
8
Cell Symbol
Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
0.92 0.04
1.33 0.04
X .. IN
OT .. X
2.51 0.056
3.27 0.063
(7.27)
(8.63)

I

IN
OT

I

=rr-

X

C

to
2.29
(18.62)

Pin Name
OT
C

Pin Name
IN

Input Loading
Factor (tu)
4
2
Output Driving
Factor (tu)
36

to
3.12
(18.62)

L .. Z
KCL

*

H .. Z
KCL

*

to
3.35
(8.71)

to
2.37
(8.71)

Z .. L
KCL
0.063

C .. X

Z .. H
KCL
0.056

* These

values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

cH

2kSl
R
-

LSI

C

~

(a) Measurement of tpd at LZ and ZL.

I:l

lc

rL

1=2""

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H6CFD-El I Sheet 1/1 1

2-392

I Page 20-98

J nUHB Version
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function
Number of BC
Tri-state Output(IOL=8mA) with Noise Limit Resistance
HBTF
& Input Buffer (True)
9
Cell Symbol
Pro~a2ation Delay Parameter
tup
tdn
KCL2 CDR2
KCL
Path
to
KCL
to
X .. IN
1.06 0.04
1.84 0.04
OT .. X
3.21 0.056
5.96 0.070
(7.97)
(11.91)
IN

I

OT

I

=cr-

X

C

to
2.62
(19.71)

Pin Name
OT
C

Pin Name
IN

Input Loading
Factor (tu)
2
2
Output Driving
Factor (tu)
36

to
3.30
(19.71)

L .. Z
KCL

*

H .. Z
KCL

*

to
6.82
(12.77)

to
3.21
(12.77)

Z" L
KCL
0.070

C ..

X

Z .. H
KCL
0.056

* These

values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

wr

21d2
R
-

LSI

C

~

(a) Measurement of tpd at LZ and ZL.

W

ic

~

1'=2kll

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H8TF-EI I Sheet 1/1 I

Page 20-99

2-393

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
UHB Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=8mA) with Noise Limit Resistance
H8TFU
& Input Buffer (True) with Pull-up Resistance
9
Cell Symbol
Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
1.06 0.04
1.84 0.04
X .. IN
3.21 0.056
5.96 0.070
OT .. X
(7.97)
(11.91)
IN

I

OT

I

=cr-

X

C

to
2.62
(19.71)

Pin Name
OT
C

Pin Name
IN

Input Loading
Factor (lu)
2
2
Output Driving
Factor (lu)
36

to
3.30
(19.71)

L .. Z
KCL

to
6.82
(12.77)

•
H .. Z
KCL

to
3.21
(12.77)

•

Z" L
KCL
0.070

C .. X

Z .. H
KCL
0.056

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

c:H

21d2
R
-

I

LSI

LSI

C

....:L

(a) Measurement of tpd at LZ and ZL.

I
I

lc

~

to,..

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KcL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H8TFU-El

2-394

Sheet 1/1 J

I

Pa~e

20-100

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=8mA) with Noise Limit Resistance
H8TFD
& Input Buffer (True) with Pull-down Resistance
9
Cell Symbol
Pro:pagation Delay Parameter
tup
tdn
KCL2 CDR2
to
KCL
to
KCL
Path
X .. IN
1.84 0.04
1.06 0.04
OT .. X
3.21 0.056
5.96 0.070
(7.97)
(11.91)

I

IN
OT

I

=tr-

X

C

to
2.62
(19.71)

Pin Name
OT

to
6.82
(12.77)

.,.

Z .. L
KCL
0.070

C ..

X

Input Loading
Factor (Lu)
2

c

2

Pin Name
IN

L .. Z
KCL

Output Driving
Factor (Lu)
36

to
3.30
(19.71)

H .. Z
KCL

to
3.21
(12.77)

.,.

Z .. H
KCL
0.056

.,. These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

~.-

2ldl

LSI

c

rL

(a) Measurement of tpd at LZ and ZL.

I LSI

I
I

lc

-I

1

0
'''''

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the

simulation.
UHB-H8TFD-El I Sheet 1/1 I

"-'-"'~'"

I Page 20-101

2-395

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=8mA) with Noise Limit Resistance
H8CF
& CMOS Interface Input Buffer. (True)
9
Proj:aJ1;ation Delay Parameter
Cell Symbol
tup
tdn
to
KCL
KCL2 CDR2
to
KCL
Path
X .. IN
0.92 0.04
1.33 0.04
5.96 0.070
3.21 0.056
OT" X
(11.91)
(7.97)

I

IN
OT

I

=rr-

X

C

to
2.62
(19.71)

Pin Name
OT

*

to
6.82
(12.77)

Z .. L
lCL
0.070

C ..

X

Input Loading
Factor (lu)
2
2

C

Pin Name
IN

L .. Z
KCL

Output Driving
Factor (lu)

to
3.30
(19.71)

H .. Z
KCL

*

to
3.21
(12.77)

Z" H
KCL
0.056

36

* These

values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

w!R-

2ld2

LSI

C

~

(a) Measurement of tpd at LZ and ZL.

r:l

lc

rL

1 "0'
=

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H8CF-E1 I Sheet 1/1 I

2-396

I PaJ!;e 20-10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=8mA) wI Noise Limit Resistance 6.
H8CFU
CMOS Interface Input Buffer (True) wI Pull-up Resistance
9
Cell Symbol
Prot a~ation Delav Parameter
tup
tdn
KCL
KCL2 CDR2
to
KCL
to
Path
0.92 0.04
1.33 0.04
X .. IN
OT .. X
3.21 0.056
5.96 0.070
(7.97)
(11. 91)

I

IN
OT

I

=cr-

X

C

to
2.62
'(19.71)

Pin Name
OT
C

Pin Name
IN

~,

Input Loading
Factor (luJ_
2
2
Output Dr! ving
Factor (lu)
36

to
3.30
(19.71)

L .. Z
KCL

to
6.82
(12.77)

'*

H .. Z
KCL

to
3.21
(12.77)

'*

Z .. L
KCL
0.070

C ..

X

Z .. H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

CJl'

= 2 kll

C

~

(a) Measurement of tpd at LZ and ZL.

LSI

lc

rL

1'.

,kO

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHB-H8CFU-E1 I Sheet 111 I

I Page 20-10

2-397

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Tri-state Output(IOL=8mA) wI Noise Limit Resistance &
H8CFD
CMOS Interface Input BufferCTrue) wI Pull-down Resistanc
9
Cell Symbol
Pro):8.ution Dela}' Parameter
tup
tdn
KCL2 CDR2
to
KCL
KCL
Path
to
0.92 0.04
X .. IN
1.33 0.04
OT .. X
3.21 0.056
5.96 0.070
C7.97)
(11.91)

:J

I

IN
OT

~

X

C

to
2.62
(19.71)

Pin Name
OT
C

Pin Name
IN

'*

Input Loading
Factor (lu)
2
2
Output Driving
Factor (lu)
36

to
3.30
(19.71)

L .. Z
KCL

'*

H .. Z
KCL

'*

to
6.82
(12.77)

to
3.21
(12.77)

Z .. L
KCL
0.070

C ..

X

Z .. H
KCL
0.056

These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

c:B

2kSl
R
-

LSI

C

~

Ca) Measurement of tpd at LZ and ZL.

W

lc

~

1"

Hll

Cb) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for Fujitsu's
logic simulation.
3. The parameters in parentheses are the values applied to the
simulation.
UHi-H8CFD-El I Sheet 1/1 I

2-398

J

Page 20-104

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name I Function

I

I "UHB" Version
jNumber of BC

I

Input Buffer for Oscillator Circuit
ITIO
Cell Symbol
Prollastation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
0
0
0
0

X

-1>-

0

Path
X'" IN

IN

Parameter

Pin Name

Input Loading
Factor (.tu)

Pin Name

Output Driving
Factor (.tu)

Symbol

Typ(ns)*

... Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.
This cell if for the oscillator circuit only. Please refer to the document
Fujitsu CMOS Gate Array 'UHB' Version User's Manual for I/O Cell for Oscillator
Circuit GATI0281d for the details.

UHB-ITlO-El I Sheet 1/1 I

I Pue 20-105

2-399

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I URB Version
Cell Name I Function
I Number of BC
Output Buffer for Oscillator
HOC
with CMOS Interface Input Buffer
8
Cell Symbol
ProJ:agation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
0.92 0.04
1.33
0.04
X -+ IN

I

IN
OT

J

~x
Parameter

Pin Name

Pin Name
IN

Symbol

Typ(ns)*

Input Loading
Factor (R.u)

Output Driving
Factor (R.u)
36

*

Minimum values for the typical operating condition.
The values for the worst case operating condition
are l!;iven by the maximum delay_ muitilllier.

This cell is for the oscillator circuit only. Please refer to the document
"Fujitsu CMOS Gate Array 'URB' Version User's Manual for I/O Cell for Oscillator
Circuit (GATI0281t.)" for the details.

URB-HOC-E1 I Sheet 1/1 I

2-400

I Page 20-10E

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
Cell Name I Function
I Number of BC
Output Buffer for Oscillator
HOS
with Schmitt Trigger Input Buffer
8
Cell Symbol
Propagation Delay Parameter
tup
tdn
KCL
KCL2 CDR2
Path
to
KCL
to
2.48 0.16
3.08
0.10
X'" IN

I

I

Parameter

Pin Name

Input Loading
Factor (Jl.u)

Pin Name
IN

Output Driving
Factor (Jl.u)
18

*

Symbol

Typ(ns)'~

Minimum values for the typical operating condition.
The values for the worst case operating condition
are given by the maximum delay multiplier.

This cell is for the oscillator circuit only. Please refer to the document
"Fujitsu CMOS Gate Array 'UHB' Version User's Manual for I/O Ce11 for Osci11ator
Circuit (GATI028lt.)" for the details.

UHB-HOS-E1

! Sheet

1/1 I

I Page 20-107
2-401

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I UHB Version
I Number of BC
Cell Name I Function
Output Buffer for Oscillator
HOCR
w/ CMOS Interface Input Buffer wi Feedback Resistance
8
Cell Symbol
Propagation Delay Parameter
tup
tdn
to
KCL
to
KCL
KCL2 CDR2
Path
X .... IN
0.92 0.04
1.33
0.04

I

IN
OT

I

=six
Parameter

Pin Name

Pin Name
IN

Symbol

Typ(ns)*

Input Loading
Factor (Jl.u)

Output Driving
Factor (Jl.u)
36

* Minimum values for the typical operating condition.
The values for the worst case operating condition
are Riven bv the maximum delav multiplier.
This cell is for the oscillator circuit only. Please refer to the document
"Fujitsu CMOS Gate Array 'UHB' Version User's Manual for I/O Cell for Oscillator
Circuit (GATI0281t.)" for the details.

UHB HOCR-E1

2-402

Sheet 1/1 I

I Page 20-10

UHB Series Unit Cell Ubrarr

CMOS Channeled Gate Atrars

Appendix A: General AC Specifications
SImulatIon Delay SpecifIcations
(Recommended OperatIng ConditIons, Ta

=0 to 70°C, Y =5 Y;t5%
DD

Delay MultIpliers

MIn.

Max.

Pre-layout Simulation

0.35

1.65

Post-layout Simulation

0.40

1.60

2-403

UHB Series Unit Cell Library

2-404

CMOS Channeled Gate Amoys

CMOS Channeled Gate Arrays

UHB Series Unit Cell Ubrary

Appendix B: Hierarchical Structure

Hierarchical blocks (or Functional Logic Blocks) within other hierarchical blocks are user-defined groups of
cells laid out in close proximity to each other in both X and Y dimensions of the array.
The hierarchical method of design allows circuit sections to be placed within the array at positions relative to
each other. This is made possible by the designer's defining and placing functional logic blocks within the hierarchy and thus controlling path lengths.
There are five levels of hierarchy, also referred to as Functional Logic Blocks (FLBs). Certain deSign rules regarding what may and what must appear at certain levels are condensed in the diagram below.
A: C-6000UHB Through C-12000UHB

B: C-330UHB Through C-4100UHB

Use of the hierarchical design method is mandatory for partitioned arrays and optional for non-partitioned arrays. Section A ofthe figure above addresses partitioned arrays C-6000UHB through C-12000UHB. Section B
of the figure above addresses non-partitioned arrays C330UHB through C41 OOUHB. Immediately below the
chip level, four Level 1 (FLB 1) blocks must be defined, giving identity to each ofthe four partitioned quadrants
of the array.

2-405

UHB Series Unit Cell Libraty

CMOS Channeled Gate Arrays

Appendix B: Hierarchical Structure (Continued)

All 110 buffers and their associated circuitry must be defined immediately beneath the chip level with the FLB1
blocks. Nothing but 1/0 buffers may be so defined. If pull-up or pull-down cells (A01 s or XOOs) are required for
unused inputs ofthe I/O buffers, they must also be defined atthis level. Unit cells (UC) may be defined at each
level.
For optimum delay characteristics, Level 2 blocks should be defined under each of the Level 1 blocks, Level 3
Blocks under Level 2 blocks, and so on. Unit cells should be defined under Level 4.

2-406

UHB Series Unit Cell Ubrary

CMOS Channeled Gate Arrays

Appendix C: Estimation Tables for Metal loading

C-330UHB

NOI

C-530UHB

CL(lu)

1
2
3
4
5
6
7
8
9

1.0
2.2
3.0
3.5
3.9
4.2
4.6
4.8
4.9

NOI
10
11
12
13
14
15
16--30
31-50
51-75
76-100

CL(lu)

5.0
5.0
5.1
5.2
5.3
5.3
5.7
6.6
6.7
7.4

C-830UHB

NOI

CL(lu)

1
2
3
4
5
6
7
8
9

1.1
2.5
3.4
3.9
4.4
4.7
5.1
5.4
5.5

NOI
10
11
12
13
14
15
16--30
31-50
51-75
76-100

CL(lu)

5.6
5.6
5.7
5.8
5.9
5.9
6.4
7.4
7.5
8.3

C-1200UHB

CL(lu)

1
2
3
4
5
6
7
8
9

NOI

1.3
3.0
4.0
4.7
5.2
5.6
6.1
6.4
6.6

NOI
10
11
12
13
14
15
16-30
31-50
51-75
76-100

CL(lu)

6.7
6.7
6.8
6.9
7.1
7.1
7.7
8.8
9.0
9.9

NOI
1
2
3
4
5
6
7
8
9

CL(lu)

1.7
3.6
4.9
5.7
6.3
6.8
7.4
7.8
8.0

NOI
10
11
12
13
14
15
16--30
31-50
51-75
76-100

CL(lu)

8.2
8.2
8.3
8.4
8.6
8.6
9.3
10.6
10.9
12.0

C-1700UHB

NOI
1
2
3
4
5
6
7
8
9

CL(lu)

1.8
3.9
5.3
6.2
6.8
7.4
8.1
8.4
8.6

NOI
10
11
12
13
14
15
16--30
31-50
51-75
76-100

CL(lu)

8.8
8.8
9.0
9.1
9.3
9.3
10.1
11.5
11.8
13.0

2-407

UHB Series Unit Cell Library

CMOS Channeled Gate Arrays

Appendix C: Estimation Tables for Metal Loading 4 (Continued)

C-3000UHB

C-2200UHB
NOI

1
2
3
4
5
6
7
8
9

CL(lu)

2.2
4.7
6.4
7.4
8.2
8.9
9.7
10.1
10.4

NOI

CL(lu)

NOI

CL(lu)

10
11
12
13
14
15
16-30
31-50
51-75
76-100

10.7
10.7
10.8
10.9
11.2
11.2
12.1
13.9
14.3
15.7

1
2
3
4
5
6
7
8
9

2.6
5.7
7.7
9.0
10.0
10.8
11.8
12.3
12.6

NOI

CL(lu)

10
11
12
13
14
15
16-30
31-50
51-75
76-100

14.8
14.8
15.0
15.2
15.5
15.5
16.8
19.3
19.8
21.8

NOI

10
11
12
13
14
15
16-30
31-50
51-75
76-100

CL(lu)

12.9
12.9
13.1
13.2
13.6
13.6
14.7
16.8
17.3
19.0

C-4100UHB
NOI

1
2
3
4
5
6
7
8
9

CL(lu)

3.0
6.6
8.8
10.3
11.4
12.4
13.5
14.0
14.4

C-6000UHB (Within Block)
NOI

1
2
3
4
5
6
7
8
9

CL(lu)

1.6
3.5
4.7
5.5
6.1
6.6
7.2
7.5
7.7

C-6000UHB (Inter-Block)

NOI

CL(lu)

NOI

CL(lu)

NOI

10
11
12
13
14
15
16-30
31-50
51-75
76-100

7.9
7.9
8.0
8.2
8.4
8.4
9.1
10.4
10.6
11.7

1
2
3
4
5
6
7
8
9

3.5
7.6
10.2
12.0
13.3
14.4
15.7
16.3
16.8

10
11
12
13
14
15
16-30
31-50
51-75
76-100

CL(lu)

17.2
17.2
17.4
17.6
18.1
18.1
19.6
22.4
23.0
25.3

Inter-Block tables must be applied to a net which has an inter-block connection. If a net, for
example, has 3 NOI in a block and 1 NOI in a different block, NOI = 4 of the Inter-Block table must be
applied.

2-408

UHB Series Unit Cell Ubrary

CMOS Channeled Gate Mllys

Appendix C: Estimation Tables for Metal Loading

c-B700UHB (Inter-Block)

C-S700UHB (Within Block)
NOI

1
2
3
4
5
6
7
8
9

CL(lu)

2.2
4.7
6.4
7.4
8.2
8.9
9.7
10.1
10.4

NOI

CL(lu)

NOI

CL(lu)

10
11
12
13
14
15
16-30
31-50
51-75
76--100

10.7
10.7
10.8
10.9
11.2
11.2
12.1
13.9
14.3
15.7

1
2
3
4
5
6
7
8
9

4.2
9.2
12.4
14.5
16.0
17.3
18.9
19.7
20.2

C-12000UHB (Within Block)
NOI

1
2
3
4
5
6
7
8
9

CL(lu)

2.6
5.7
7.7
9.0
10.0
10.8
11.8
12.3
12.6

(Continued)

NOI

10
11
12
13
14
15
16-30
31-50
51-75
76--100

CL(lu)

20.8
20.8
21.0
21.3
21.8
21.8
23.6
27.1
27.8
30.5

C-12000UHB (Inter-Block)

NOI

CL(lu)

NOI

CL(lu)

NOI

10
11
12
13
14
15
16-30
31-50
51-75
76--100

12.9
12.9
13.1
13.2
13.6
13.6
14.7
16.8
17.3
19.0

1
2
3
4
5
6
7
8
9

4.9
10.8
14.5
17.0
18.8
20.3
22.2
23.1
23.7

10
11
12
13
14
15
16-30
31-50
51-75
76--100

CL(lu)

24.3
24.3
24.6
25.0
25.6
25.6
27.7
31.7
32.6
35.8

Inter-Block tables must be applied to a net which has an inter-block connection. If a net, for
example, has 3 NOI in a block and 1 NOI in a different block, NOI = 4 of the Inter-Block table must be
applied.

2-409

CMOS Channeled Gate Anays

UHB Series Unit Cell Library

Appendix C: Estimation Tables for Metal Loading for Clock Nets

C-330UHB (for CK60, CK8D)

C-330UHB (for CK20, CK4D)
NOI

1-2
3-4
5-6
7-8
9-10

CL(lu)

5.1
9.5
11.9
12.2
12.4

NOI

11 -12
13-15
16-30
31-50
51-80

CL(lu)

NOI

CL(lu)

12.7
13.0
13.3
15.4
18.1

1-2
3-4
5-6
7-8
9-10

7.0
13.4
16.7
17.0
17.3

C-530UHB (for CK2D, CK4D)
NOI

1-2
3-4
5-6
7-8
9-10

CL(lu)

5.1
9.6
14.1
14.4
14.6

NOI

11 -12
13-15
16-30
31-50
51-80

NOI

CL(lu)

5.6
10.5
15.4
18.0
18.2

NOI

11 -12
13-15
16-30
31-50
51-80

CL(lu)

NOI

CL(lu)

14.9
15.1
15.4
17.3
19.8

1-2
3-4
5-6
7-8
9-10

7.3
14.0
20.7
20.9
21.2

NOI

2-410

CL(lu)

6.2
11.7
17.2
22.7
23.0

NOI

11 -12
13-15
16-30
31-50
51-80

17.6
17.9
18.1
20.2
23.0

NOI

11-12
13-15
16-30
31-50
51-80

CL(lu)

21.4
21.7
21.9
23.8
26.4

C-830UHB (for CK60, CK8D)
CL(lu)

NOI

CL«I~)

18.5
18.8
19.1
21.2
24.1

1-2
3-4
5-6
7-8
9-10

8.1
15.5
22.9
26.7
27.0

C-1200UHB (for CK20, CK4D)

1-2
3-4
5-6
7-8
9-10

CL(lu)

C-530UHB (for CK60, CK8D)

C-83DUHB (for CK20, CK4D)

1-2
3-4
5-6
7-8
9-10

NOI

11-12
13-15
16-30
31-50
51-80

NOI

11-12
13-15
16-30
31-50
51-80

CL(lu)

27.3
27.6
27.8
30.0
32.8

C-12DOUHB (for CK60, CK8D)
CL(lu)

NOI

CL(lu)

23.3
23.7
24.0
26.3
29.3

1-2
3-4
5-6
7-8
9-10

9.3
18.0
26.7
35.4
35.7

NOI

11-12
13-15
16-30
31-50
51-80

CL (Iu)

36.0
36.3
36.6
38.9
41.9

UHB Series Unit Cell Ubrary

CMOS Channeled Galli AITIIYS

Estimation Tables for Metal Loading for Clock Nets (Continued)

C-1700UHB (for CK60, CK80)

C-1700UHB (for CK20, CK40)

NOI
1-2
3-4
5-6
7-8
9-10

CL(lu)
6.6
12.6
18.6
24.5
27.7

NOI
11 -12
13-15
16-30
31-50
51-80

CL(lu)
28.0
28.3
28.6
31.0
34.2

NOI

CL(lu)
7.1
13.5
19.9
26.3
32.8

NOI
11 -12
13-15
16-30
31-50
51-80

CL(lu)
33.1
33.4
33.8
36.3
39.6

C-3000UHB (for CK20, CK40)

NOI
1-2
3-4
5-6
7-8
9-10

CL(lu)
7.7
14.8
21.8
28.9
35.9

NOI
11 -12
13-15
16-30
31-50
51-80

1-2
3-4
5-6
7-8
9-10

CL(lu)
8.4
16.2
24.0
31.7
39.5

NOI
11 -12
13-15
16-30
31-50
51-80

NDI
11 -12
13-15
16-30
31-50
51-80

CL(lu)
44.4
44.7
45.0
47.4
50.6

NOI
1-2
3-4
5-6
7-8
9-10

CL(lu)
11.2
21.8
32.3
42.8
53.4

NOI
11 -12
13-15
16-30
31-50
51-80

CL(lu)
53.7
54.1
54.4
56.9
60.2

c-3000UHB (for CK60, CK80)
CL(lu)

NOI

43.0
43.3
43.7
46.3
49.8

1-2
3-4
5-6
7-8
9-10

c-4100UHB (for CK20, CK40)

NOI

CL(lu)
10.3
19.9
29.5
39.1
44.1

C-2200UHB (for CK60, CK80)

C-2200UHB (for CK20, CK40)

1-2
3-4
5-6
7-8
9-10

NOI
1-2
3-4
5-6
7-8
9-10

CL(lu)
12.6
24.5
36.4
48.3
60.2

NOI
11 -12
13-15
16-30
31-50
51-80

CL(lu)
72.1
72.4
72.8
75.4
78.9

c-4100UHB (for CK60, CK80)
CL(lu)

NOI

47.3
51.4
51.7
54.6
58.4

1-2
3-4
5-6
7-8
9-10

CL(lu)
14.0
27.4
40.7
54.1
67.4

NOI
11 -12
13-15
16-30
31-50
51-80

CL(lu)
80.8
87.6
88.0
90.9
94.6

2-411

CMOS Channeled Gate Arrays

UHB Series Unit Cell Library

Estimation Tables for Metal Loading for Clock Nets

C·6000UHB (for CK20, CK40)

NOI
1
2
3
4

CL(lu)
9.9
14.9
24.1
29.2

C-8700UHB (for CK20, CK40)

NOI
1
2
3
4

CL(lu)
11.8
17.8
28.9
34.9

C-12000UHB (for CK20, CK40)

NOI
1
2
3
4

2-412

CL(lu)
13.7
20.7
33.7
40.8

(Continued)

c-6OOOUHB (for CK60, CK80)

NOI
1
2
3
4

CL(lu)
13.2
24.8
37.3
48.9

C-8700UHB (for CK60, CK80)

NOI
1
2
3
4

CL(lu)
15.7
29.7
44.8
58.7

C-12000UHB (for CK60, CK80)

NOI
1
2
3
4

CL(lu)
18.3
34.7
52.3
68.7

UHB Series Unit Cell Ubrary

CMOS Channeled Gate Arrays

Appendix D: Available Package Types
UHB CMOS Available Package Types
Plastic

Standard
16DIP
18 DIP
20 DIP
22 DIP
24 DIP
28 DIP
40 DIP
42 DIP
48 DIP

(100 mil pin pitch)

Shrink
28SHDIP
42SHDIP
48SHDIP
64SHDIP

(70 mil pin pitch)

Skinny
22SKDIP
24SKDIP
28 SKDIP

(300 mil wide body)

16FPT
20FPT
24FPT
28FPT

•
•
•
•
•
•
•
•

CH

•
•

•
•

•
•
•
•
•
•
•
•
•
•

48 FPT
48 FPT-S'
64 FPT
BOFPT
100FPT
120 FPT
160FPT

•
•
•
•
•

•
•
•
•
•
•

•
•
•
•

•

•
•
•

•
•
•
•

CH
NW

•
•
•

CH
CH

CH
CH

CH
CH

•

•
•

•
•

•

•
•

•

•

•

•

•
•
•
•

•
•
•
•

•
•
•
•
•

•
•
•
•

•
•
•

•

•
•

•
•

•
•
•

•
•

•

CH

•

•

•
•
•

•

•
•
•
•
•

•
•
•
•
•

CH

•
•
•
•

•
•
•

•
•

•
•
•

•

•

•
•
•
•

•

•

•
•
•
•
•

•

•
•
•
•
•
•
•

•

'smaller than the other 48-pin FPT

64PGA
88PGA
135PGA
NOTES:
•
UD
NW
CH

•

•

CH
CH
CH

•

CH
NW

(leads on all four sides)

44 FPT

•
•
•
•
•

•

•

•

•
•

•
•

•

•

•

•

•

•
•

•

Available
Not Available
Under Development
Newly Available
The availability 01 the package has changed, i.e., become unavailable

2-413

UHB Series Unit Cell Library

CMOS Channeled Gate AlTSys

Appendix D: Available Package Types (Continued)
UHB CMOS Available Package Types
Ceramic

20 DIP
22 DIP
24 DIP
28 DIP
40 DIP
42 DIP
48 DIP
Shrink
28SHDIP
42SHDIP

Ell

•
•
•
•
•

•
•
•
•

(70 mil pin pitch)

•

•

48FPT
80FPT
l00FPT
120FPT

•
•
•
•
•
•

•
•
•
•

•
•
•
•

•
•
•
•

•

•

•

•

•

•
•

•
•

•
•

•
•

•

•
•

•

•

•
•

•
•

•
•

NW

NW
NW

NW
NW

UD
UD

•

160FPT

64PGA
88PGA
135PGA
179PGA
208PGA
256PGA

•

•

CH

•
•

•
•
•

•

•

•

•

NOTES:

•

UD
NW
CH

2-414

Available
Not Available
Under Development
Newly Available
The availability of the package has been changed, i.e., become unavailable

•

•

•
•
•
•
NW
•

UD
CH
UD

•

UD

•

•
•

NW

UHB Series Unit Cell Ubrary

CMOS Chann6Ied Gats Arrays

Appendix E: TTL 7400 Function Conversion Table

TTl 7400

SarI. .

7400
7401
7402
7403
7404
7405
7406
7407
7408
7409
7410
7411
7412
7413
7414
7415
7418
7419
7420
7421
7422
7423
7424
7425
7426
7427
7428
7430
7432
7433
7434
7435
7437
743819
7440
7442
7443
7444
7445
7446
7447
7448
7449
7450
7451
7452
7453
7454
7455
7460
7461
7462
7464
7465

Fujitsu
BaalcCails

Function

Name

Qua:! 2-input NAND
Qua:! 2-input NAND, Open Collector Outputs
Qua:! 2-input NOR
Quad 2-input NAND, Open Collector Outputs
HexlnYerllllr
Hex InYerllllr, Open Collector Outputs
Hex Inverllllr/Bufler, Open Collector Outputs
Hex Buffer, Open Collector Outputs
Qua:! 2-input AND
Quad 2-input AND, Open Collector Outputs
Triple 3-input NAND
Triple 3-input AND
Triple 3-NAND, Open Collector Outputs
Dual4-input NAND, Schmitt Trigger
Hex Schmitt Trigger Inverter
Triple 3-input AND, Open Collector Outputs
Dual4-input NAND, Schmitt Trigger
Hex Schmitt Trigger Inverter
Dual 4-input NAND
Dual 4-input AND
Dual4-input NAND, Open Collector Outputs
Expended Dual 4-input NOR with Strobe
Quad Schmitt Trigger 2-input NAND
Dual 4-input NOR with Strobe
Quad 2-input NAND, High Voltage Output
Triple 3-input NOR
Qua:! 2-input NOR Buffer
8-inputNAND
Qua:! 2-input OR
Quad 2-input NOR Buffer, Open Collector
Outputs
Hex Noninverter
Hex Noninverter with Open Collector Outputs
Qua:! 2-input NAND Buller
Quad 2-input NAND Buller, Open Collector
Outputs
Dual 4-input NAND Buller
BCD to Decimal Decoder
EXS to Decimal Decoder
4 to 10 Una Decoder
BCD to Decimal Decoder/driwr (SOV)
BCD to 7....egment DecoderlDriver (30V)
BCD to 7....egment DecoderlDriver(15V)
BCD to 7....egment Decoder/Driver
BCD to 7-segment, Open Collector Outputs
Dual 2-input, 2-wide AOI (One Expandable)
AOI
Expendable 4-wide AND-OR
Expandeble o--X

Parameter

Pin Name

Input loading
Factor (Iu)

A

2

Pin Name

Output Driving
Factor (Iu)

X

36

Typ(ns) •

Symbol

• Minimum values for the typical oparating condition.
The values for the worst case oparating condition ara given by the maximum delay
multiplier.

C1Q-V2B-EO

3-8

Sheet 1/1

J

l

Page 1-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 • Version
Number 01 BC

Funcllon

I

True Buffer

B1N

Cell Symbol
!Up
to

KCL

0.363

0.067

Proplgallon Delay Parlmeter
tdn
KCL2
to
KCL
CDR2

0.425

1
Palh

AtoX

0.045

A~X
Parameter

Pin Name

Symbol

Typ(nl)'

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

18
• Minimum values lor Iha typical operating CXlndition.
The valuaslor Iha worst casa operating CXlnclition era givan by Iha maximum delay
multiplier.

C10-81N-EO I

Sheet 111

I

Page 1-3

3-9

I • CG10 • Version
I Number 01 BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
I

Cell Name

8D3

I

Delay Cell
Cell Symbol

tu
to

3.331

KCL

0.067

Propagation Delay Parameter
Jdn
KCL
to
KCL2
CDR2

2.944

0.067

0.073

5
Path

AtoX

4

A-[>-X

Parameter

Pin Name

Symbol

Typ (ns)'

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

18
• Minimum values for the typical operating oondition.
The values for the worst case operating oondition are given by the maximum delay
multiplier.

C1O-BD3-EO

Sheet 1/1

I

3-10

Page 1-4

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Call Nam.

Function

BD4

Delay Cell

Number 01 Be

I

Propagation Delay Parameter

Cell Symbol

1-X

Parameter

Pin Name

Input loading
Factor (Iu)

A

4

Pin Name

Output DrIving
Factor (Iu)

X

6

Symbol

Typ(ns) •

• Minimum values lor the typical operating condition.
The values lor the worst case operating concition are given by the maximum delay
multiplier.

C10-BD4-EO

Sheet 1/1

I

Page 1-5

3-11

.1 • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
I

• Version

Cell Name

805

NumberolBC

Delay Cell
Call Symbol
!Up
to

KCL

6.825

0.067

Propagation Delay Parameter
tdn
1'0
KCL
KCL2
CDR2

6.469

0.056

0.084

J

9
Palh

AtoX

4

A-{:>-X

Parameter

Pin Name

Input Loading
FactorClu)

A

1

Pin Name

Output Driving
FactorClu)

X

18

Symbol

Typ Cns)·

• Minimum values for Ihe typical operating condition.
The values for Ihe worst case operating condition Bra gill8n by !he maximum delay
multiplier.

C10-BD5-EO

3-12

Sheet 111

I

Page 1-6

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name

Function

BD6

Delay Cell

J

Cell Symbol
!up
to

KCL

13.750

0.072

I

Propagation Delay P...meter
II:In
to
KCL
KCL2
CDR2

13.638

0.051

0.079

Number 01 BC

17
Pall1

AtoX

4

A-[>-X
Parameter

PIn Name

Input loadIng
Factor (Iu)

A

1

PlnN.me

Output DrIving
F.ctor (Iu)

X

18

Symbol

Typ (na)'

• Minimum va\uallor Ihe typical Oparatinll c:oncition.
The values for lI1e worst case oparatinll condition are given by Ihe maximum dalay
multiplier.

C10-BD6-EO I

Sheet 111

I

Page 1-7

3-13

CGIO Series Unit CfII/ Ubraty

3-14

CMOS Channeled Gate Arrays

CGIO Series Unit CeO Library

CMOS Channeled Gats Arrays

NAND Family

Page

Unit Cell
Name

3-17

N2N

2-input NAND

3-18

N2B

Power 2-input NAND

3
2

Function

Basic
Cells

3-19

N2K

Fast Power 2-input NAND

3-20

N3N

3-input NAND

2

3-21

N3B

Power 3-input NAND

3

3-22

N3K

Fast Power 3-input NAND

3

3-23

N4N

4-input NAND

2

3-24

N4B

Power 4-input NAND

4

3-25

N4K

Fast Power 4-input NAND

4

3-26

N6B

Power 6-input NAND

5

3-27

N8B

Power 8-input NAND

6

3-28

N9B

Power 9-input NAND

8

3-29

NCB

Power 12-input NAND

10

3-30

NGB

Power 16-input NAND

11

3-15

CG10 Series Unit Cell Library

3-16

CMOS Channe/sd Gate AITBYs

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
CenName
Function

N2N

Number 01 BC

I

2-input NAND
Cen Symbol
\up

AI
A2

I • CG10 • Version

::={»--

to

KCL

0.231

0.067

Propagation Delay Parameter
Idn
to
KCL
KC12
CDR2
0.350

1
Palh

AtoX

0.079

X

Parameter

Pin Name

Input loading
FaClor(lu)

A

1

Pin Name

Output Driving
Flctor(lu)

X

18

Typ(ns)·

Symbol

lID

• Minimum values lor \he typical operating condition.
The values lor Ihe worst case operating condition are given by !he maximum delay
multiplier.

C1o-N2N-EO

Sheet 1/1

I

Page 2-1

3-17

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cel/Nama

N2B

Number 01 BC

Function

Power 2-input NAND
Propagation Delay Parameter
\dn

Cell Symbol
\up
to

KCl

to

KCl

0.688

0.034

0.888

0.023

KCL2

I

3
Path

CDR2

AtoX

~=D>-x
Parameter

Pin Name

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

36

Symbol

Typ (ns)'

• Minimum value. lor the typical operating condition.
The values for the worst case operating condition are given by Ihe maximum delay
multiplier.

C1Q-N2B-E

Sheel1/1

I

I

3-18

Page 2-2

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function

Cell Name

N2K

Number 01 BC

I

Power 2-input NAND
Propagation Delay Parameter

Cell Symbol
!Up

!dn

to

KCL

to

KCL

KCL2

CDR2

0.231

0.034

0.269

0.039

0.051

7

2
Path

AtoX

~=D>---x
Parameter

Pin Name

Input loading
Factor (Iu)

A

2

Pin Name

Output Driving
Factor (Iu)

X

36

Symbol

Typ (ns)·

• Minimum values lor the typical operating conation.
The values lor the worst case operating condition are gi\l8n by !he maximum delay
multiplier.

C10-N2K-EO

Sheet 1/1

I

I

Page 2-3

3-19

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
CeIlNlme

I • CG10 • Version
Number 01 BC

Function

I

3-input NAND

N3N

Cell Symbol

\Up

Al=!)-

A2

to

KCL

0.325

0.067

Propagallon Delay Parameter
!dn
KCL
to
KCL2
CDR2

0.431

2
Path

AloX

0.107

X

A3

Parameter

A

Pin Name

Typ (ns)·

Symbol

Input loading
Factor (Iu)

1

Pin Name

Output Driving
Factor (Iu)

X

14
• Minimum values lor !he typical operating condition.
The values lor the worst case operating condition ara given by the maximum delay
multiplier.

C10-N3N-EO

Shee 1/1

I

I

3-20

Page 2-4

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Numb.. 01 BC

Funellon

N38

I

Power 3-input NAND
Cell Symbol

Prop.g.tlon Delay P...m....

\up

AI=1}A2

Idn

10

KCL

10

KCL

0.800

0.034

1.063

0.023

KCL2

3
Pa'"

CDR2

AloX

X

A3

Parameter

A

Pin Name

Typ(ns)·

Symbol

Input loading
Factor (lu)

1

Pin Name

OUtput Driving
Faclor(lu)

X

36
• Minimum value. lor .... typical operating concition.
The value. lor "'e worst case operaling condition are given by Iha maximum delay
multiplier.

C1o-N3B-EO

Sheel1/1

I

I

Page 2-5

3-21

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Call Name
I
Funollon

N3K

I • CG10 • Version
I NumberolBC

I

Power 3-input NAND
Cell Symbol
IIJ

AI*-

A2
A3

10

KCL

0.300

0.030

A

0.406

3
Palh

AtoX

0.045

X

Para meier

Pin Name

PropegaUon Delay Parameter
Idn
10
KCL2
CDR2
KCL

Svmbol

Typ (no)'

Input loading
Faclor (Iu)
2

Pin Name

Output Driving
Facio. (Iu)

X

28
, Minimum values for the typical operating conation.
The values lor Ihe worst case operating concition are given by the maximum delay
multiplier.

C10-N3K-EO

Sheet 1/1

I

3-22

Page 2-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10 • Version

Function

Cell Name

Number 01 BC

I

4-input NAND

N4N

Cell Symbol
!Up

"illA2

.0

KCL

0.388

0.067

Propagation Delay Parame.er
Idn
10
KCL
KCL2
CDR2

0.463

2
Path

AtoX

0.135

X

A3
A4

Para meier

Symbol

Typ (ns)'

Inpul Laadlng
Factor (Iu)

Pin Name

A

1

Pin Name

OUIPUI Driving
Factor (Iu)

X

10
• Minimum values for the Iypicai operating conation.
The values lor the worsl case operating conation are given by the maximum delay
multiplier.

C1o-N4N-EO

I

Sheet 1/1

I

Page 2-7

3-23

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 • Version
Numb.olBC

FunctIon

N4B

Power 4-input NAND
CenSymbol

\Up

.oroA2

to

KCL

0.863

0.034

Propagation Delay Parameter
tdn
to
KCL
KCL2
CDR2

1.188

I

4
Palll

AtoX

0.023

X

AS
A4

Parameter

Pin Name

Input loadIng
Factor (Iu)

A

1

PIn Name

Output Drlvtng
Faclor(lu)

X

36

Typ (ns)·

Symbol

• Minimum value. lor the typical operating condition.
The values lor the worst case operating oondiIion are givan by \he maximum delay
multiplier.

C1O-N4B-EO

3-24

Sheet 1/1

I

Page2~

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 • Version

Function

N4K

Number 01 BC

I

Power 4-input NAND
Cell Symbol

!up

"~

A2
1>3
A4

to

KCL

0.350

0.030

PropaglUon DeilY Plrameter
teln
to
KCL
KCL2
COR2

0.475

4
Palh

AtoX

0.056

X

Parameter

Pin Name

Input loading
Factor (Iu)

A

2

Pin Nama

Output Driving
Factor (Iu)

X

20

Typ (ns)·

Symbol

..

• Minimum values for the typical operating concition.
The values lor Ih& worst case operating condition are given by Ih& maximum delay
multiplier.

C1o-N4K

EO I

Sheet 111

I

Page 2-9

3-25

I • CG1D • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

N6B

Number of BC

Power 6-input NAND
Cell Symbol

!Up
to

0.856

"ro-

KCL

0.034

PropaglUon Delay Parameter
teln
to
KCL
KCL2
COR2

1.263

0.023

0.039

I

5
Path

AtoX

7

A2

A3
A4
AS
A6

X

Parameter

Pin Name

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

36

Symbol

, Minimum values for !he typical operating condition.
The value. lor the worst case operating oondition 818 givan
mUIlip/ier.

Typ(ns)'

bY !he maximum delay

Equivalent Circuit

AI

A2
AS
X

A4
AS
AS

C1O-N6B-EO

3-26

Shee 1/1

I

Page2-10

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
CellNlme

Number of BC

Funcllon

NBB

I

Power a-input NAND
Cell Symbol
tup
10

KCL

0.900

0.034

Propagallon Delay Parameler
Idn
10
KCL
KCL2
CDR2

1.381

0.023

0.039

6
Path

AtoX

7

A l - ......
A2-

A3A4-

AS-

p.--X

A6A7AS-L,..I
Parameter

Pin Name

Inpul loading
Faclor (lui

A

1

Pin Name

Oulpul Driving
Faclor(lu)

X

36

Symbol

Typ (ns)'

• Minimum values for the typical operating condition.
The values for the worst case operating CXlndilion are given by the maximum delay
multiplier.

Equivalent Circuil
A t - ......

A2A3A4-~

X

A S - ......
A6A7AS-~

C10-N8B-EO

I

Sheet 1/1

I

Page 2-11

3-27

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

N98

Number olBC

I

Power 9-input NAND
Cell Symbol
\up

to

KCL

0.888

0.034

Propagation Delay Parameler
tdn
to
KCL
KCL2
CDR2

1.663

0.028

0.051

8
Path

AloX

7

Al-r"'I
A2-

1.3MAS:>-- X
A6A7A6A9-"",
Parameter

Pin Name

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

36

Symbol

Typ (ns)·

• Minimum values for !he Iypical operating condition.
The values lor the worst case operadng condition are given by the maximum delay
multiplier.

Equivalent Circuit

AI
A2

1.3
M
AS
A6

X

A7
A6
A9

Cl0-N9B-EO

3-28

I

Sheet 111

I

Page2-12

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Call Name

Function

NCB

Number 01 BC

Power 12-input NAND
Cell Symbol
tup

At-""
A2A3A4ASA6A7-

to

KCL

0.950

0.034

Propagation Delay Parameter
tdn
to
KCL
KCL2
CDR2

1.788

0.028

0.051

I

10
Palh

AtoX

8

;>-- X

MA9AtOAtlAI2-L..'

Parameter

Pin Name

Input Loading
Factor (Iu)

A

1

Pin Nama

Output Driving
Factor (Iu)

X

36

Symbol

Typ (no)·

lID

• Minimum values lor the typical operating conation.
The values lor Ihe worst case operating conation are given by the maximum delay
multiplier.

Equivalent Ciralit
Al-""

A2A3A4-.,;

ASA6A7-

l

J

X

M-.,;

A9-}-

Al0A12A12-l..oI

C1o-NCB-EO

Sheet 1/1

I

Page2-13

3-29

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

NumberolBC

I

Power1~nputNAND

NGB

Cell Symbol
IUp
to

KCL

0.956

0.034

Propagation Delay Parameler
ttln
io
KCL
CDR2
KCL2

2.169

0.034

0.051

11
Palh

AtoX

8

A 1 - .....

A2A3MASA6A7ASASA10A11A12A13A14A15A16-1.;'

P--- X
Parameter

Pin Name

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

36

Symbol

Typ (ns)'

• Minimum values for the typical operating condition.
The values lor Ihe worst case operating condition are given by !he meximum delay
multiplier.
Equivalent Circuit
A1-l

A2-

J

A3M-.,

M-hl )--t>o. . - VrAS-

'-< .....

A7-

AS -

.,

X

A 9 - .....

A11A12-.,
A13A14-

l

J

A15A16-.,

C1D-NGB-EO

3-30

Sheet 111

I

Page2-14

CMOS Channeled Gate Arrays

CG10 Series Unit Cell Library

NOR Family
Unit Cell

BasIc
Cells

Page

Name

3-33

R2N

3-34

R2B

Power 2-input NOR

3

3-35

R2K

Power 2-input NOR

2

3-36

R3N

3-inputNOR

2

3-37

R3B

Power 3-input NOR

3
3

FunctIon
2-input NOR

3-38

R3K

Power 3-input NOR

3-39

R4N

4-input NOR

2

3-40

R4B

Power 4-input NOR

4

3-41

R4K

Power 4-input NOR

4

3-42

R6B

Power 6-input NOR

5

3-43

R8B

Power 8-input NOR

6

3-44

R9B

Power 9-input NOR

8

3-45

RCB

Power 12-input NOR

10

3-46

RGB

Power 16-input NOR

11

lID

3-31

CGtO Series Unit Cell Library

3-32

CMOS Channeled Gale Arrays

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

R2N

Number of BC

!Up
to

0.250

AI
A2

I

2-input NOR
Cell Symbol

::::t;>---

KCL

0.122

PropagaUon Delay Parameter
Illn
to
CDR2
KCL
KC1.2

0.275

0.045

0.062

1
Path

Ato X

4

X

Parameter

Typ (ns) ,

Symbol

Input loading
Factor (Iu)

Pin Nama
A

1

Pin Name

Output Driving
Factor (Iu)

X

14
, Minimum values for the typical operating oondition.
The values for the worst casa operating oondition era gilllln by the maximum delay
multiplier.

C1D-R2N-EO

I

Sheet 1/1

I

I

Page 3-1

3-33

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I

I • CG10 • Version

Function

Number 01 BC

I

Power 2-input NOR

R2B

Cell Symbol
tup
to

KCL

0.850

0.034

Propagallon Delay Parameter
IIln
to
KCL
KCL2
CDR2

0.781

3
Pa'"

AtoX

0.023

Al~X
A2

Parameter

Pin Name

Typ (ns) ,

Symbol

Input loading
Flctor(lu)

A

1

Pin Nlme

Output Driving
Factor (Iu)

X

36
, Minimum values lor the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

C1o-R2B-EO I

3-34

Sheet 1/1

I

I

Page 3-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

R2K

Number 01 SC

I

Power 2-input NOR
Cell Symbol
IUp

10

0.281

Al
A2

I' CG10 ·Version

Funcllon

=t;>---

KCL

0.059

Propagation Delay Parameler
Idn
10
KCL
KCL2
CDR2

0.281

2
Palh

AtoX

0.034

X

Parameter

Pin Name

Input loading
Factor (Iu)

A

2

Pin Name

Output Driving
Factor (Iu)

X

36

Typ (ns)'

Symbol

• Minimum values lor Ihe Iypica/ operating condition.
The values for Ihe worsl case operaling condition 8/11 given by Ihe maximum delay
multiplier.

C10 R2K-EO

Sheel1/1

I

Page 3-3

3-35

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function
I

NumberolBC

I

3-input NOR

R3N

Cell Symbol
IUp

A1*-

A2

to

KCL

0.525

0.172

Propagallon Delay Parameter
IIIn
KCL2
to
KCL
CDR2
0.288

0.051

0.067

2
Path

4

AloX

X

A3

Parameter

A

Typ (ns) ,

Symbol

Input loading
Faclor(lu)

Pin Name

1

Pin Name

Output Driving
Faclor(lu)

X

10
• Minimum valuas lor the typical oparating oondition.
The values lor the worst case oparating oondition are given by the maximum delay
multiplier.

C10-R3N-EO

3-36

I

Sheet 1/1

I

I

Page

3-4

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 • Version

Function

R3B

Number 01 BC

I

Power 3-input NOR
CeIJSymbol
\up

Al=lt-

:

to

KCL

1.244

0.034

0.856

3
Path

AloX

0.023

X

Parameter

A

Propagallon Delay Parameter
tdn
to
KCL
KCL2
CDR2

Typ (ns •

Symbol

Input loading
Factor (Iu)

Pin Name

1

Pin Name

Output Driving
Factor (Iu)

X

36
• Minimum values lor the typical operating condition.
The values for the worst case operating condition . . given by the maximum delay
multiplier.

C10-R3B-EO

I

Sheel1/1

I

Page 3-5

3-37

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function

Cell Nam.

R3K

Number 01 BC

I

Power 3-input NOR
Cell Symbol

Propagation Delay Parameter
Idn

!Up

AI=&-

A2
AS

to

KCL

to

KCL

KCL2

CDR2

0.413

0.072

0.200

0.023

0.039

7

A

Palh

AtoX

X

Parameter

Pin Name

3

Symbol

Typ (ns)'

Input Loadlnll
Factor (Iu)

2

Pin Name

Output Driving
Factor (Iu)

X

20
• Minimum values lor the typical operating condition.
The values lor the worst case operating condition ara given by !he maximum delay
multiplier.

C10-R3K-EO

3-38

Sheet 1/1

I

I

Page 3-6

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number 01 BC

Function

I

4-input NOR

R4N

Cell Symbol
tup

"~

:

to

KCL

0.775

0.227

Propagation Delay Parameter
Jdn
KCL2
to
KCL
CDR2

0.288

0.051

0.073

2
Path

AtoX

4

X

A4

Parameter

Pin Name

Symbol

Typ (ns)'

Inpul Loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

6
• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

C1Q-R4N EO

Sheet 111

I

Page 3-7

3-39

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Nam.

R4B

I • CG10 • Version

Function

NumberolBC

Power 4-input NOR
Cell Symbol
IU

"~
A2

10

KCL

1.563

0.034

Propllllalion Delay Parameter
tdn
10
KCL
KCL2
CDR2

0.838

I

4
Path

AtoX

0.023

X

A3

A4

Parameler

Pin Name

Symbol

Typ na)'

Inpul loading
Faclor(lu)

A

1

Pin Name

OUlpul DrIving
Faclor(lu)

X

36
• Minimum values lor the typical operaling condilion.
The values lor the worst case operating condition are given by !he maximum delay
multiplier.

r.1G-R4B-EO

Sheet 1/1

I

I

3-40

Page 3-8

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name

Function

R4K

Number of BC

4

Power 4-input NOR
Cell Symbol
IUp

10

KCL

0.675

0.097

Propagallon Delay Parameler
Idn
10
KCL
KC12
CDR2

0.219

0.017

0.028

Path

AtoX

7

.,~ X

A2
A3
A4

Paramel.r

Pin Name

Input loading
Factor (Iu)

A

2

Pin Name

Output Driving
Faclor(lu)

X

12

Symbol

Typ (nl)'

• Minimum values for the typical oparating concition.
The values for the worsl case operating concition are given by the maximum delay
multiplier.

C10 R4K-EO

Sheet 1/1

I

Page 3-9

3-41

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
I

I • CG10 • Version

I

Call Name

R68

Power 6-input NOR
Cell Symbol
tup

~
"j-

to

KCL

1.406

0.034

Propagation Delay Parameter
tdn
KCL2
CDR2
1'0
KCL

0.925

Number 01 BC

I

5
Path

AtoX

0.023

X

AS

Parameter

Pin Name

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

36

Symbol

Typ(ns)*

* Minimum values lor the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Equivalent Circu~

Al-f\

~ ----bf
A4-f\

:!----bf

C10-R6B-EO

3-42

L

r

~

4:,.

Sheet 1/1

X

I

Page3-10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

J

RB8

I • CG10 • Version
Number 01 BC

Function

6

Power 8-input NOR
Cell Symbol
!Up

Al-:::::'
A2A3A4-

AS-

to

KCL

1.nS

0.034

Propagation Delay Parameter
IeIn
to
KCL
KCl2
CDR2

0.944

Path

AtoX

0.023

p.--X

A6A7-

AB-t::;
Parlmeter

Pin Name

Symbol

Typ (nl) "

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

36
" Minimum values for the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

h

Equivalent Circu~

MA2-

~=J

AS-~
AS-I-

.A:::l.

.(b.

X

A7-~

AB-t::;

C10-R8B-EO I

Sheet 111

I

Page 3-11

3-43

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

NumberolBC

Function

R98

8

Power 9-input NOR
Propagallon Delay Parameter
IeIn

Cell Symbol
to

1.556

KCl
0.034

to

1.050

KCl
0.023

KCL2

Pa!h

CDR2

AtoX

Al-P.
A2-1A3-1A4-iX

AS

AS-IA7-1AS-IA9-b
Parameter

Symbol

Typ(ns) •

Input loading
Faclor(lu)

Pin Name

A

1

Pin Nama

Output Driving
Faclor(lu)

X

36
• Minimum valuas for !he typical operating condition.
The values for !he worst casa operating condition are given by the maximum delay
multiplier.

Equivalent Circuit

Al-f\

~-t/

~

r

A4-f\

:-t/
A7-f\
AS
A9--bT

C10-R9B-EO

3-44

I

Sheet 1/1

X

I

I

Page3-12

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 • Version
NumberolBC

Funcllon

RCB

Power 12-input NOR
Coil Symbol
lup
to

KCL

1.713

0.034

Propagallon Delay Parameler
IIIn
to
KCL
KCL2
COR2

1.094

I

10
Palll

AtoX

0.023

AI-~
A2A:3A4M--

ASA7-

P--- X

ASASAIOAtlA12-::;;o

Parameler

Pin Name

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

36

Symbol

Typ (ns)·

• Minimum value. lor lIIe typical openating condition.
The vaIu.. lor !he worst case operating condition ere givan by !he maximum delay
multiplier.

Equivalent Circu~
Al--F\

:--w
:!--w
A4 - - - F \

A7---F\

I

L....(P\
X

I

r-x
Para meIer

Pin Name

Inpul loading
Faclor(lu)

A

2

Pin Name

Output Driving
Factor (Iu)

X

18

Typ (no)·

Symbol

lID

• Minimum values lor lIIe typical operating condition.
The values lor the worst case operating concfdion are given by \he maximum delay
multiplier.

ZTI2-rr-,
Equivalent Circuil

C10 X1N-EO

Function Table
Outpul

Inputs

AI

A2

X

H

H

H

L

H

L

H

L

L

L

L

H

Sheet 1/1

I

Page 6-1

3-61

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I

Function

Cell Symbol
\up

At
A2

I

Power Exclusive NOR

X18

=+V--

to

KCL

0.931

0.034

Propagation Delay Parameter
tdn
to
KCL
KCL2
CDR2

1.106

0.028

0.051

Number 01 BC

4
Path

AtoX

7

X

Symbol

Parameter

Pin Nama

Input loading
Factor (Iu)

A

2

Pin Nama

Output Driving
Faclor(lu)

X

36

Typ (ns)'

• Minimum values lor tha typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Equivalent Circuit

Function Table

::~

C10-X1B-EO

I

Inpuls

tJ>-+-x

Sheet 1/1

Output

At

A2

X

H

H

H
L

L

H

H

L

L

L

L

H

I

I

3-62

Page 6-2

I • CG10 • Version
I Number 01 BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
CeIlNlme
Function

I

I Exclusive OR

X2N

Cell Symbol
tup
to

KCL

0.694

0.122

Propagation Delay Plrlmeter
teln
to
KCL
KCL2
CDR2

0.731

0.073

0.090

3
Path

AloX

4

Al=+tjA2
X

Symbol

Plrlmeter

Pin Name

Input Loldlng
Flctor(lu)

A

2

Typ (nl)·

..

Output Driving
Factor (Iu)
14

Pin Name
X

• Minimum values lor the typical oparating condition.
The values lor the worst case oparating conation are given by the maximum delay
multiplier.

Equivalent Circu~

Function Table

:;~

C1D-X2N-EO

I

Inputs

tJ>-x

Output
X

AI

A2

H

H

L

L

H

H

H

L

H

L

L

L

Sheel1/1

I

Page 6-3

3-63

I • CG10 • Version
. I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
I

Cell Nam.

X28

I

Power Exclusive OR
Co"Symbol
tu

to

0.894

KCL

0.034

Propogatlon Delay Parameter
tdn
to
KCL
KCL2
CDR2

1.025

0.028

0.039

4
Palh

AloX

7

A1=©A2
X

Symbol

Parameter

Pin Name

Input loading
Factor (Iu)

A

2

PlnN......

Outpul Driving
Factor (Iu)

X

36

Typ (n.)·

• Minimum values for the typical operating ooncition.
The values for Ihe worst case operating oondition ara given by !he maximum delay
multiplier.

Function Table

Equivalenl Circuit

~~x

C10-X2B-EO

Shee 111

Inputs

0uIput

X

A1

A2

H

H

L

L

H

H

H

L

H

L

L

L

I

I

3-64

Page 6-4

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

NumberolBC

Function

X3N

I

3-input Exclusive NOR
Cell Symbol
tup
to

KCL

1.700

0.122

Propagation Delay Parameter
tdn
to
KCL
KCl2
CDR2

1.450

0.073

0.090

5
Path

AloX

4

At.

~

X

Symbol

Parameter

Pin Name

Input Loading
Factor (Iu)

A

2

Pin Name

Output Driving
Factor (Iu)

X

18

Typ (ns)·

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
mul~plier.

Fu~onTabie

Equivalent Circuit

:~,

C10-X3N-EO

Sheet 1/1

OUtput

Inputs

I

X

At

A2

A3

H

H

H

L

H

H

L

H
H

H

L

H

H

L

L

L

L

H

H

H

L

H

L

L

L

L

H

L

L

L

L

H

I

Page 6-5

3-65

r" CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
I

Cell Nlm.

X38

NumberolBC

Power 3-input Exclusive NOR
CellS1mboi
\up
to

KCL

1.650

0.034

Propagation Delay Parameter
tdn
to
KCL
KCL2
COR2

2.119

0.028

I

Path

AtoX

7

0.051

6

A
1*- x
A2
A3

Symbol

Parameter

Pin Name

Input Loading
Factor (Iu)

A

2

Pin Name

Output Driving
FaClor (Iu)

X

36

Typ (na)·

• Minimum values lor the typical operating ooncfition.
The values lor the worst case operating ooncition ana given by the maximum delay
multiplier.

Equivalent Circu~

Function Table

:~,

C10-X3B-EO I

Inputs

OUtput

A1

A2

A3

H

H

H

L

H

H

L

H

H

L

H

H

H

L

L

L

L

H

H

H

L

X

L

H

L

L

L

H

L

L

L

L

H

Sheel1/1

I

3-66

Page 6-S

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number 01 BC

Function

X4N

I

3-input Exclusive OR
Cell Symbol
tup

Al=&-

A2
A3

10

KCL

1.763

0.122

Propagation Delay Parameter
tdn
10
KCL
KCL2
CDR2

1.581

0.073

0.090

5
Palll

AloX

4

x

Parameter

PIn Name

Input loadIng
Factor (Iu)

A

2

PIn Name

Output DrIvIng
Faclor(lu)

X

14

Typ (no)·

Symbol

• Minimum values lor lIle typical operating condilion.
The values lor lIle worsl case operating condition are given by !he maximum delay
multiplier.

Function Tabla

Equivalent Circuil

Al

~~
:

C10-X4N-EO J

X

Sheel1/1

Output

Inputs

A2

A3

X

H

H

H

H

H

L

H

L

H

L

H

L

H

L

L

H

L

H

H

L

L

H

L

H

L

L

H

H

L

L

L

L

I

Page 6-7

3-67

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number 01 BC

Function

X48

Power 3-input Exclusive OR
Cell Symbol
\up

to

1.544

KCL

0.034

Propagation Delay Parameter
IIln
CDR2
to
KCL
KCL2

1.956

0.028

I

Pa!h

AloX

7

0.039

6

Al*- X
A2

A3

Pin Name

Input loading
Factor (Iu)

A

2

Pin Name

Output Driving
Factor (Iu)

X

36

Typ (ns) ,

Symbol

Parameter

• Minimum values lor !he typical operating condition.
The values for !he worst case operating condition are given by !he maximum delay
multiplier.

Function Table

Equivalent Circu~
A2
A3

.......

Al

C10-X4B-EO

3-68

OutpUt

Inputs

I

Sheet 1/1

X

Al

A2

A3

X

H

H

H

H

H

H

L

L

H

L

H

L

H

L

L

H

L

H

H

L

L

H

L

H

L

L

H

H

L

L

L

L

I

Page 6-8

CMOS Channeled Gale Arrays

CG10 Series Unit CeU Ubrary

AND-OR-Inverter Family (AOI)
Basic

UnH Cell

Page

Name

3-71

023

2-wide 2-ANO 3-input AOI

2

3-72

014

2-wide 3-ANO 4-input AOI

2

3-73

024

2-wide 2-ANO 4-input AOI

2

3-74

034

3-wide 2-ANO 4-input AOI

2

3-75

036

3-wide 2-ANO 6-input AOI

3

3-76

044

2-wide 2-0R 2-ANO 4-input AOI

2

Function

Cells

3-69

CG10 Seriss Unit Cell Library

3-70

CMOS Chann9led Gate Anays

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

023

• Version

I

Function

Cell Symbol
tup

A1~
A=

to

KCL

0.456
0.231

0.122
0.093

A
B

0.079
0.051

0.067

2
Path

AloX
BloX

4

X

Parameter

Pin Name

Propagation Delay Parameter
tefn
to
KCL
KCL2
CDR2

0.425
0.231

Number 01 BC

I

2-wide 2-AND 3-input AOI

Symbol

Typ (ns)'

Input loading
Factor (Iu)

1
1

Pin Name

Output Driving
Faclor (luJ

X

14
• Minimum values lor the typical operating condition.
The values lor the worst case operating ccndition ere given by the maximum delay
multiplier.

C1Q-023-EO

Sheel1/1

I

Page 7-1

3-71

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
CeUName

Number 01 BC

Function

D14

2-wide 3-AND 4-input AOI
Cell Symbol
IUp

"~

to

KCL

0.563
0.200

0.122
0.084

Propagation Delay Parameter
teln
to
KCL
KCL2
CDR2

0.438
0.225

0.107
0.051

0.118
0.067

I

2
Palh

AtoX
BtoX

4
4

A2
A3

B

X

Parameter

Pin Nama

Symbol

Typ (ns)'

Input loading
Faclor(lu)

A
B

1
1

Pin Name

Oulput Driving
Faclor(lu)

X

14
• Minimum values for !he typical operating con-- x
L..'

El
E2

Parameter

Symbol

Typ (ns)·

Fl=t}-

F2

Pin Name

Inpul Loading
Faclor(lu)

D
E
F

1
1
1
1
1
1

Pin Name

OulpUI Driving
Factor (Iu)

X

36

A

B

c

C1O-U26-EO

Sheet 111

• Minimum values lor Ihe typicei operating condition.
The values lor !he worsl case operaling condilion are given by 1he maximum delay
mulliplier.

I

Page 9-13

3-99

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
CeUName

Number 01 BC

FunctIon

U28

Power 2-QR 8-wide Multiplexer
Cell Symbol
!Up

AI={}A2
BI=tjB2

"=till
;;~
~~
FI
F2

r-.

to

KCL

1.319
0.969
0.944
1.294
1.319
0.969
0.913
1.269

0.034
0.034
0.034
0.034
0.034
0.034
0.034
0.034

Propagation Delay Parameler
Idn
io
KCL
KCL2
CDR2

1.988
1.963
1.756
1.788
1.963
1.931
1.588
1.644

0.034
0.034
0.034
0.034
0.034
0.034
0.034
0.034

0.056
0.056
0.056
0.056
0.056
0.056
0.056
0.056

I

11
Path

Ato X
BtoX
CtoX
DtoX
EtoX
Fto X
GtoX
H toX

7
7
7
7
7
7
7
7

:>-- x
Parameter

Symbol

Typ(n.)"

'-"

GI=tjG2
HI={}H2

PIn Name
A

B
C
D
E

F
G
H

Input loadIng
Factor (Iu)

1
1
1
1
1
1
1
1

PIn Name

Output DrIving
Faclor (Iu)

X

36
" Minimum values for the typical operating condition.
The values lor the worst case operating oondilion ere given by the maximum delay
multiplier.

C1o-U28-EO I

3-100

Sheet 1/1

I

Page9-14

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

U32

I

Propagation Delay Parameter

tdn

tup

to

1.344
1.319

A2
A3
Bl
B2
B3

----fI
--bJ
----fI

KCL

0.034
0.034

to

1.038
1.019

KCL

0.028
0.028

KCL2

0.045
0.045

Number 01 BC

I

Power 3-0R 2-wide Multiplexer
Cell Symbol

Al

"Version

Function

5
Path

CDR2

AloX
Slo X

7
7

X

---b'

Parameter

Pin Name

Typ (ns)'

Symbol

Input Loading
Factor (Iu)

A
B

1
1

Pin Name

Output Driving
Factor (Iu)

X

36
• Minimum values lor the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

C1Q-U32 EO

Sheel1/1

I

I

Page 9-15

3-101

IIDII

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

U33

Number of BC

Power 3-OR 3-wide Multiplexer
Cell Symbol
!Up

to

KCL

1.425
1.406
1.444

0.034
0.034
0.034

Propagation Delay Parameter
!dn
to
KCL
KCL2
CDR2

1.425
1.488
1.575

0.028
0.028
0.028

0.062
0.062
0.056

I

7
Path

AtoX
BtoX
CtoX

7
7
7

A1.~
A2--bJ
A3
B1

---F\

:----b'

x

C1~
C2 - - b J
C3

Pin Name
A

B
C

Parameter

Symbol

Typ (ns)'

Input loading
Factor (Iu)

1
1
1

Pin Name

Output Driving
Factor (Iu)

X

36
• Minimum values lor the typical operating condition.
The values for !he worst case operating condition are 9illlln by !he maximum delay
multiplier.

C10-U33-EO

3-102

Sheet 1/1

I

Page9-16

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

NumberolBC

Function

U34

Cell Symbol
rup

AI - - - f l

: ----bJ
Bl - - - f l

:---bJL:
C1
C2
C3

r.:
----bJ
------p\

10

KCL

1.319
1.331
1.200
1.319

0.034
0.034
0.034
0.034

Propagation Delay Parameler
Idn
10
KCL
KCL2
CDR2

1.863
1.875
1.525
1.681

0.034
0.034
0.034
0.034

0.056
0.056
0.056
0.056

9
Path

AtoX
BtoX
CtoX
DtoX

7
7
7
7

}-,
Parameter

Dl---fl
D2
D3

I

Power 3-OR 4-wide Multiplexer

Typ (ns)·

Symbol

----bJ

Pin Name

Inpul loading
Faclor(lu)

A
B
C
D

1
1
1
1

Pin Name

Oulpul Driving
Faclor(lu)

X

36
• Minimum values for lhe typical operating condition.
The values lor the worst case operaling oondition are given by the maximum delay
multiplier.

C1o-U34-EO

Sheet 111

l

Page 9-17

3-103

...

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

J

Cell Nlme

U42

Function

Number 01 BC

I

Power 4-0R 2-wide Multiplexer
Cell Symbol
III

to

1.625
1.581

KCL

0.034
0.034

Propagation Delay Parameler
teln
to
KCL
KCL2
CDR2

1.069
1.025

0.028
0.028

0.045
0.045

6
Pa!h

AtoX
BtoX

7
7

AlA2A3A4-

X
8182-

8384Para meier

Pin Name

Input loading
Factor (Iu)

A
8

1
1

Pin Name

Output Driving
Fac\or(lu)

X

36

Symbol

Typ nl)·

• Minimum valuel lor the Iypical operating condition.
The values lor !he worst case operating oondition are given by the maximum delay
multiplier.

C10-U42 EO

3-104

Sheet 1/1

I

Page9-18

I • CG10 ·Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Call Name

Numb.. olBC

FUnction

U43

Power 4-OR 3-wide Multiplexer
Cell Symbol
IUP

.. -~

10

KCL

1.606
1.638
1.688

0.034
0.034
0.034

PrODlalllon DeI.y P.r.m....
Irln
KCL
KCL2
to
CDR2

1.331
1.413
1.494

0.034
0.034
0.034

0.045
0.045
0.045

I

9
Palll

AloX
BloX
CloX

7
7
7

A2A3A4-

"-~
828384-

X

c,-~
C2-

Parame1er

C3C4-

Pin Name

Typ(ns) •

Symbol

Input loading
Factor (Iu)

A
8
C

1
1
1

Pin Name

Output Driving
Factor (Iu)

X

36
• Minimum values lor !he typical operating candition.
The values for lIle worst case operating condition are given by !he maximum delay
multiplier.

C1o-U43-EO

Sheet 1/1

I

I

Page 9-19

3-105

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nama

Numbar01 BC

Function

Power 4-OR 4-wide Multiplexer

U44

Cell Symbol
\up

.. -}
A2A3A4-:;:I

"-\1
828384-:;:1

c,-~
C2C3C4-

to

KCL

1.706
1.700
1.644
1.669

0.034
0.034
0.034
0.034

Propagation Delay Parameter
teln
to
KCL
KCL2
CDR2

1.875
1.800
1.525
1.681

0.028
0.028
0.028
0.028

0.062
0.062
0.062
0.062

7
7
7
7

I

11
Path

AtoX
BtoX
CtoX
DtoX

D--'

O,-}

Parameter

Symbol

Typ (ns)'

D2D304-:;:1

Pin Nama

Input loading
Factor (Iu)

A
B
C
D

1
1
1
1

Pin Nama

Output Driving
Factor (Iu)

X

36
• Minimum values for the typical operating condition.
The values for the worst case operating condition are gi1l9n by the maximum delay
multiplier.

C1D-U44-EO

3-106

Sheet 1/1

I

T Page9-20

CMOS Channeled Gate Arrays

CG 10 Series Unit Cell Library

Clock Buffer Family

Page

Unit Cell
Name

3-109

K1B

True Clock Buffer

2

3-110

K2B

Power Clock Buffer

3

3-111

K3B

Gated Clock (AND) Bl.Iffer

2

3-112

K4B

Gated Clock (OR) Buffer

2

3-113

K5B

Gated Clock (NAND) IBuffer

3

3-114

KAB

Block Clock (OR) Buffer

3-115

KBB

Block Clock (OR x 10) liIuffer

3-117

VIL

Inverting Clock Bufler

FwneUeA

Basic
Cells

3
30

2

3-107

CG10 Series Unit eeH Ubrary

..

3-108

CMOS Channeled Gate Arrays

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10 • Version

Funciion

Cell Nam.

K1B

Numb.r01 SC

I

True Clock Buffer
Cell Symbol
!Up

10

KCL

0.450

0.034

Propagallon Delay Parameler
IIIn
10
KCL
KCL2
CDR2

0.538

2
Path

AtoX

0.023

A~X
Parameter

Pin Name

Typ(ns) •

Symbol

Input loading
Factor (Iu)

A

1

Pin Name

Oulpul Driving
Factor (Iu)

X

36
• Minimum values lor the typical operating condition.
The values for the worsl case operating condition are giY8n by the maximum delay
multiplier.

Equivalent Circuit
At

---{>o----ct>-

C1o-K1B-EO

X

Sheet 111

I

Page 10-1

3-109

..

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

K2B

Function

I • CG10 • Version
I Number 01 BC

I

Power Clock Buffer
Cell Symbol
!Up
to

KCL

0.663

0.017

Propagation Delay Parameter
!dn
to
KCL
KCL2
CDR2

0.750

3
Palh

AtoX

0.017

A~X
Parameter

Pin Name

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

55

Symbol

Typ (ns)·

• Minimum valuas lor Ihe Iypical operating condition.
The values lor Ihe worst case operating condition are given by Ihe maximum delay
multiplier.

Equivalent Circun

AI

--t>o-------

C10-K2B-EO

3-110

X

Sheet 1/1

I

Page 10-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

K38

I • CG10 • Version
Number 01 BC

I

Gated Clock (AND) Buffer
Cell Symbol
!Up
to

KCL

0.625

0.034

Propagation Delay Parameter
!dn
to
KCL
KCl2
CDR2
0.625

2
Path

AtoX

0.023

AI::::[)- X
A2

Parameter

Pin Name

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

36

Symbol

Typ (ns)'

• Minimum values for Ihe typical operating condition.
The values lor Ihe worst case operating concilion are giWln by the maximum delay
multiplier.

Equivalent Circuit
AI
A2

:::[»---c{>--

C10-K3B-EO

J

X

Sheet 111

I

Page 10-3

3-111

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

NumberofBC

Function

K4B

2

Gated Clock (OR) Buffer
Cell Symbol
IUp
to

KCL

0.488

0.034

Propagation Delay Parameter
Idn
to
KCL
KCL2
CDR2

0.713

0.028

0.039

8

Path

AtoX

~=tr-x
Parameter

Pin Name

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

36

Symbol

Typ(ns)"

" Minimum values for the typical operating oondition.
The values for the worst case operating oonclition are given by the maximum delay
mul~plier.

Equivalent Circuit

~~x

C1o-K4B-EO

J

Sheet 1/1

I
Page 10-4

3-112

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

• CG10 • Version
Number 01 BC

Function

K58

I

Gated Clock (NAND) Buffer
Cell Symbol
\up

to

KCL

0.713

0.034

Propagation Delay Parlmeter
Idn
to
KCL
KCL2
COR2

0.925

3
Pa!h

AtoX

0.023

~:::[)-- X
Parameter

Pin Name

Symbol

Typ (ns)'

Input loading
Factor (Iu)

A

1

Pin Name

Output Driving
Factor (Iu)

X

36
• Minimum values for !he typical operating condition.
The values for !he worst case operating condition are given by !he maximum delay
mUltiplier.

Equivalent Circuit

AI
A2

=[»---c{>---t>

C1Q-K5B-EO

Sheet 1/1

I

X

I

Page 10-5

3-113

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Call Name

I • CG10 • Version
Number 01 BC

Function

KAB

I

Block Clock (OR) Buffer
Cell Symbol

!Up
to

KCL

0.675

0.017

Propagation Delay Parameter
ttln
to
KCL
KCl2
CDR2

1.156

3
Palh

AloX

0.017

Al=t;-X
A2

Parameter

Typ (ns)'

Input loading
Factor (Iu)

Pin Name

II1II

Symbol

A

1

Pin Name

Output Driving
Factor (Iu)

X

55
• Minimum values lor Ihe typical operating condition.
The values lor Ihe worst case operating condition are given by !he maximum delay
multiplier.

Equivalent Circu"

~~x

C1o-KAB-EO

3-114

I

Sheel1f1

I

I

Page 10-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Nama

KBB

1" CGtO

• Version

I

Function

I

Block Clock Buffer (OR x 10)
Cell Symbol
IlJp

to

KCL

0.838
0.675

0.017
0.017

Propagation Dalay Parameler
Idn
to
KCL
KCL2
CDR2

1.300
1.156

Number 01 Be

30
Palll

CKtoX
IHtoX

0.017
0.017

CKIHOIH1IH2IH3IH4IHSIH6IH7IHSIH9-

-XO
-XI
-X2
-X3
-X4
-XS
-X6
-X7
~X8

~X9

Pin Nama

Input loading
Factor (Iu)

CK
IH

10
1

Pin Nama

Output Driving
Factor (Iu)

X

55

Parameter

Symbol

Typ (ns)'

• Minimum values lor lIIe typical operating condition.
The values for ilia worst case operating condition are given by lIIe maximum delay
multiplier.

C10-KBB-EO

Sheet 1/2

I

Page 10-7

3-115

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

" CG10 • Version

Cell Name

KBB

Equivalent Circuit

r---------,

I

CK
IHO

XI

IHI

X2

IH2

X3

IH3

X4

IH4

X5

IH5

X6

IH6

X7

IH7

X8

IH8

IH9

C1G-KBB-EO

XO

X9
L _ _ _ _ _ _ _ _ ..1I

Sheet 212
Page 10-8

3-116

I • CG10 • Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

V1L

Function

Inverting Clock Buffer
Cell Symbol

Propagation Delay Parameler
IeIn

IUp

10

KCL

10

KCL

0.219

0.017

0.419

0.017

KCL2

I

2
Palh

CDR2

Ato X

A-{>o--X

Parameter

Pin Name

Inpul loading
Faclor(lu)

A

4

Pin Name

Oulpul Driving
Faclor(lu)

X

55

Symbol

Typ (no)'

• Minimum values for lIle Iypical operating condilion.
The values lor lIle worsl case operaling condilion are given by !he maximum delay
multiplier.

C10-V1L-EO

J

Sheet 1/1

I

Page 10-9

3-117

Ell

CGtO Series Unit CeH Ubrary

..

3-118

CMOS Channeled Gate Arrays

CMOS Channeled Gate A"ays

CG10 Serias Unit Cell Ubrary

Scan Flip-flop (Positive Edge Type) Family

Page

Unit Cell
Name

3-121

SDH

Scan D Flip-flop with 2:1 Multiplex with
Clear and Clock Inhibit

14

3-124

SDJ

Scan D Flip-flop with 4:1 Multiplex with
Clear and Clock Inhibit

15

3-127

SDK

Scan D Flip-flop with 3:1 Multiplex with
Clear and Clock Inhibit

16

Function

Basic
Cells

3-130

SJH

Scan J-K F with Clear and Clock Inhibit

16

3-133

SDD

Scan D Flip-flop with 2:1 Multiplex, Preset
Clear, and Clock Inhibit

16

3-137

SDA

Scan 1-input D Flip-flop with Clock Inhibit

12

3-140

SDB

Scan 1-input D Flip-flop with Clock Inhibit

42

3-144

SHA

Scan 1-input D Flip-flop with Clock Inhibit

68

3-147

SHB

Scan 1-input D Flip-flop with Clock Inhibit
and QOutput

62

3-150

SHC

Scan 1-input D Flip-flop with Clock Inhibit
and XQ Output

62

3-153

SHJ

Scan D Flip-flop with 2:1 Multiplex and
Clock Inhibit

78

3-156

SHK

Scan D Flip-flop with 3:1 Multiplex and
Clock Inhibit

88

3-159

SFDM

Scan 1-input D Flip-flop with Clock Inhibit

10

3-162

SFDO

Scan 1-input D Flip-flop with Clear and Clock Inhibit

11

3-165

SFDP

Scan 1-input D Flip-flop with Clear, Preset,
and Clock Inhibit

12

3-169

SFDR

Scan 4-input D Flip-flop with Clear and Clock Inhibit

36

3-173

SFDS

Scan 4-input D Flip-flop with Clock Inhibit

31

3-177

SFJD

Scan J-K Flip-flop with Clock Inhibit

14

3-119

CGIO Seriss Unit CeH Ubra2'

3-120

CMOS Channeled Gate A"ays

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name

Number 01 BC

Function

SOH

I

SCAN 2-input OFF with Clear & Clock-Inhibit
Cell Symbol

Propagallon Delay Parameter
!dn
to
KCL
KCL2
CDR2

\up

to

KCL

2.325
1.469
2.369

0.034
0.034
0.034

1.863
1.344
0.669

0.023
0.034
0.023

0.045
0.067
0.045

7
7
7

14
Path

CK,IHtoa
CK,lHtoXa
Cltoa, xa

r--AlA2-

-a

CKIH-

51 AB--<

p.- XO
Parameter
CL

Input loading
Factor (Iu)

Pin Name

Symbol
tew
tCWH

Clock Pulse Width
Clock Pause Time

1
1
1
3
1
2

Al,A2
CK
IH
CL

51
A. B

Typ (ns)'

3.4
2.9

Data SetuD Time
Data Hold Time

tso
tHO

2.4
0.7

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tRE!!

2.9

tiN'"

1.0

1.9

Output Driving
Factor (Iu)

Pin Name

a

36
36

XO

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table
INPUT

OUTPUT

MODE
CLK

CL

0

A

B

51

a

X

L

X

X

X

X

L

H

L10X

H

OJ

L

L

X

OJ

OJ

H

H

X

L

L

X

00

XOo

H

H

X LtoHtoL H

Si

00

XOo

H

H

X

x

Si

T

CLEAR
CLOCK

SCAN
L HtoLtoH

XO

Note: CLK • CK + IH
AtxA2

o•

C1o-SDH EO

Sheet 113

I

I

Page 11-1

3-121

. T APiF{AY UN)! CE J. SPE:CIFICATION

SOH

Equivalent Cirevit
CLK

XBCK

• CG10 • Version

XCLK

-L ...L

--L
Al

A2 .

Q

CL

Slo-....-,

T
XBCK

TACK

XQ

~~ ~

D>-t

::~~

AO

: ACK

{)o

XACK

BO

{)o

: ::K

Page 11-2

3-122

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

SDH
Definitions of Parameters

i) CLOCK MODE
_

,

CLOCK

ICWH _

lew

1--150 • . . tHO ..
DATA

_Ipd_

a,xa
(OUTPUT)

i i) CLEAR MODE
--IREM ....

CK

_ILW-

CLEAR

~

... Ipd .....

a,xa
(OUTPUT)

I--- tlNH_
CL

C1Q-SDH-EO

Sheet 3/3
Page 11-3

3-123

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

NumberolBC

Function

SDJ

I

SCAN 4-input OFF with Clear & Clock-Inhibit
Cell Symbol

PropaglUon Delay Parameler
KIn
10
KCL
KCL2
CDR2

!Up

10

KCL

1.719
1.475
2.338

0.034
0.034
0.034

1.888
1.338
0.663

0.023
0.034
0.023

0.045
0.067
0.045

7
7
7

15
Path

CK.IHloQ
CK.IHloXQ
CLio Q. XQ

r--AIA28182-

-0

CKIHSIA8--<

p-- XO
Parameler

Symbol
lew
ICWH

Clock Pulse Width
Clock Pause Time

CL

Pin Name

Inpul Loading
Factor (Iu)

AI.A2
81.82
CK
IH
CL
SI
A,8

1
1
1
1
3
1
2

Pin Name

Output Driving
Factor(lu)

0

36
36

XO

Typ(ns)'

3.4
2.9

Dala SetuD Time
Data Hold Time

Iso
IHO

2.8
0.5

Clear Pulse Width
Clear Release Time
Clear Hold Time

ILW
IREM

2.9
1.9
1.0

tlNW

• Minimum values for the typical operating condition.
The values for the worst cese operating condition are given by the maximum delay
multiplier.

Function Teble
INPUT

OUTPUT

MODE

XO

CLK

CL

0

A

8

SI

0

X

L

X

X

X

X

L

H

LIDH

H

Oi

L

L

X

Oi

Oi

H

H

X

L

L

X

00

XOo

H

H

X LIDHIDL H

Si

00

XQD

H

H

X

51

51

CLEAR
CLOCK

SCAN

L HIDLtoH X

Nota: CLK • CK+ IH
O. (AI xA2)+(81 x 82)

C10-SDJ-EO

3-124

I

Sheet 1/3

I

Page 11-4

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SOJ
Equivalent Circuit
Al
A2

Bl
B2

"'---'.J1

Q

CL o----i

T
XBCK

TACK

XQ

~~ ~

D>-t

:CLK

AO

: ACK

[>0

XCLK

BO

: XBCK

[>0

C1O-SDJ-EO

XACK

BCK

Sheet 213
Page 11-5

3-125

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

SOJ
Definitions of Parameters

i) CLOCK MODE
tCM-I_

I---tcw

CLOCK
~.

~
~tso

.. •

tHO ..

DATA

_tpd_

a,xa
(OUTPUT)

..

i i) CLEAR MODE

~tREM""

CK
!--tLW_

CLEAR

~
I--tpd ....

a,xa
(OUTPUT)

I«-- tlM!_
CL

C10-SDJ-EO

She

/3
Page 11-6

3-126

I· CG10

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name

• Version

I

Function

SDK

I

SCAN 6-input DFF with Clear & Clock-Inhibit
Cell Symbol

PropagaUon Delay Parameler
teln
10
KCl
KCl2
CDR2

!Up

-

AlA2Bl B2ClC2-

to

KCl

2.313
1.450
2.338

0.034
0.034
0.034

1.B75
1.350
0.638

0.023
0.034
0.023

0.045
0.067
0.045

7
7
7

Number 01 BC

16
Pa!h

CK,IHtoa
CK,lHto xa
CLIo a, xa

-a

CKIHSI AB --C

p-- xo
Symbol
lew

Parameter

Cl

Input loading
Factor (Iu)

Pin Name

1
1
1
1
1
3
1

Al,A2
Bl, B2
Cl,C2
CK
IH
Cl
SI
A,B

Typ (ns)'

tCWH

3.4
2.9

Data Setup Time
Data Hold Time

tSD
t"D

3.2
0.4

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
t REM

2.9
1.9
1.0

Clock Pulse Width
Clock Pause Time

tIN'"

2
Output Driving
Factor (Iu)

Pin Name

a

• Minimum values lor the typical operating condition.
The values lor !he worst case operating condition are given by tihe maximum delay
multiplier.

36
36

xa
Function Table

INPUT

OUTPUT

MODE
CLK

Cl

0

A

B

SI

a

x

L

X

X

X

X

L

H

LIIIH

H

Oi

L

L

X

Oi

Oi

H

H

X

L

L

X

00

H

H

X LIII Hili L H

Si

00

H

H

X

CLEAR
CLOCK

SCAN

L HIIILIIIH X
Note: CLK

a

o•

C1D-SDK-EO

I

Sheet 1/3

Si

xa

xc..
xc..
sr

CK + IH
(AI xA2)+(Bl x B2)+(Cl xC2)

I

Page 11-7

3-127

• CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SDK

Equivalent Circuit

Bl
B2

Q

Clo---+

-,-

-,-

ACK

XBCK
XQ

~~~

~

AO
:

ClK

:

[>

XCLK

BO

C1o-SDK-EO

XACK

:

[>

ACK

XBCK
BCK

Sheet 2J3
Page 11-6

3-128

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10, • Version

Cell Name

SDK

I

Definnions of Parameters

i) CLOCK MODE
ICWH_

I--Icw

CLOCK

.. Iso ..

I-- IHO ..

DATA

~Ipd-

a,xa
(OUTPUT)

i i) CLEAR MODE

f4-IREM ....

CK

CLEAR

--

:'-ILW_

... Ipd'"

a,xa
(OUTPUT)
_IIIH_

CL

C10-SDK EO

Sheet 3/3

I

Page 11-9

3-129

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

SJH

Function

Number 01 BC

SCAN J-K FF with Clear & Clock-Inhibit
Propagation Delay Parameler
kin
to
KCL
KCL2
CDR2

Cell Symbol
tup

to

KCL

2.650
1.475
2.350

0.034
0.034
0.034

2.106
1.350
0.869

0.023
0.034
0.023

0.045
0.067
0.045

7
7
7

I

16
Path

CK,lHtoQ
CK,lHtoXQ
CLtoQ,XQ

-

JK--<

I-Q

CKIHSI AB--<

P-XQ
Parameter

Symbol
lew
ICWH

Clock Pulse Width
Clock Pause Time

CL

Pin Name

Input loading
Factor (Iu)

J.K
CK
IH
CL
SI
A,B

1
1
1
3
1
2

Pin Name

Output Driving
Factor (Iu)

a
xa

36
36

Typ(n.) •

3.4
2.9

Data Setue Time J
Data Selue Time K
Data Hold Time(J Kl

Iso
Iso
IHO

2.8
3.0
0.4

Clear Pulse Widlh
Clear Release TIme
Clear Hold Time

I w
I REM

2.9
1.9
1.0

tlNI-4

• Minimum values lor the typical operating condition.
The values for the worst case operating condilion are given by !he maximum delay
multiplier.

Function Table
INPUT

OUTPUT

MODE
CLEAR

CLOCK

CLK

CL

J

K

A

B

SI

Q

X

L

X

X

X

X

X

L

XQ
H

LIoH

H

L

L

L

L

X

L

H

LIoH

H

H

H

L

L

X

H

L

Llo H

H

L

H

L

L

X

QD

XOo

Llo H

H

H

L

L

L

X

Xe.

QD

H

H

X·

X

L

L

X

QD

Xe.

H

H

X

X LIoHtoL H

Si

aD

xe.

H

H

X

X

Si

Si

SCAN
L HtoLtoH X

NOIII:CLK. CK+IH

C10-SJH-EO I

3-130

Sheet 113

I

I Page 11-10

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Ce"Name

SJH
Equivalent Circuit

c

T
XBCK

TACK

xc

~~ ~

Dt: ::~~

AO

: ACK

~
BO

: XBCK

~

C10-SJH-EO

XACK

BCK

Sheet 213
Page 11-11

3-131

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

SJH
Definitions of Parameters

i) CLOCK MODE
ICWH_

le--Ic;w

CLOCK

. . Iso ..

I-- IHO ...

DATA

I+--

Ipd_

a,xa
(OUTPUT)

i i) CLEAR MODE

lID

... tREM .....

CK

I+-CLEAR

tLW_

~

~tpd"'"

a,xa
(OUTPUT)

I-- tlNH_
CL

C10-SJH-EO

Sheet 3/3
Page 11-12

3-132

I • CG10 • Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

SDD

SCAN 2-input DFF with Clear, Preset & Clock-Inhibit
Cen Symbol

Propagation Delay Parameler
Idn
10
KCL
KCl2
CDR2

!Up

PR

AlA2-

10

KCL

2.313
1.656
2.813
2.400

0.034
0.034
0.034
0.034

2.013
1.338
0.638
1.469

0.023
0.034
0.023
0.034

7
7
7
7

0.045
0.067
0.045
0.067

I

16
Path

CK,lHtoQ
CK,lHto XQ
CLtoQ, XQ
PRtoQ, XQ

-a

CKIHSIAB ---<:

:>-- XO
Symbol
lew

Parameter

Pin Name

Input Loading
Factor (Iu)

Al.A2
CK
IH
CL
PR
SI
A.B

1
1
1
3
3
1
2

PIn Name

Output DrIving
Factor (Iu)

a

3.4
2.9

Data Setuo Time
Data Hold Time

tso
tHD

3.4
0.7

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM
tlNH

3.2
1.9
1.0

Preset Pulse Width
Preset Release Time
Preset Hold Time

tpw
tREM
tlNH

4.3
2.4
0.7

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by !he maximum delay
multiplier.

36
36

XO

Typ (ns)'

tcw~

Clock Pulse Width
Clock Pause Time

CL

Function Table
INPUT

OUTPUT

MODE
CLK

CL

PR

0

A

B

SI

a

XO

CLEAR

X

L

H

X

X

X

X

L

H

PRESET

X

L

X

X

X

X

H

L

X

Oi

Oi

X

00

XOo

Si

00

XOo

Si

Si

CLOCK

H

LIOH

H

H

Oi

L

L

H

H

H

X

l

l

H

H

H

X llOHlOl H

H

H

H

X

SCAN
CLJPR

X

l

L

X

l

X

HIOLIOH X

X

X

Prohibited
Note: ClK • CK + IH
_AlxA2

o

C1o-SDD-EO J

Sheet 1/4

I Page 11-13

3-133

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
CeIlN;,me

SDD
Equivalent Circuit
AI 0---;
A20---;
CL 0----..-1

c

51

1.-_ _ _---.

TACK

T
XBCK
xc

PR

~~ ~

D>E

: ClK

AO

: ACK

~

XCLK

BO

: XBCK

~

C1D-SDD-EO

XACK

BCK

Sheet 2/4
Page 11-14

3-134

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name

I

SDD

I

I • CG10

• Version

Definitions of Parameters

i) CLOCK MODE
~Icw

ICWH_

CLOCK

1--150 .. . . IHO ..

DATA

I---

IprJ-'

a,xa
(OUTPUT)

i i) CLEAR MODE

4-IREM'"

CK

_ILW_

~

CLEAR

4-lprJ'"

a,xa
(OUTPUT)

14- tINH_
CLEAR

C1D-SDD-EO

I

Sheet 3/4

I Page 11-15

3-135

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION

I • CG10 • Version

Cell Name

SDD I
iii) PRESET MODE
CK

PRESET

-

!--IPW-

a,xa
(OUTPUT)
!--IINH-

PRESET

C10-50D-EO

3-136

Sheet 4/4

I Page 11-16

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nama
Function
I

SDA

Number 01 BC

SCAN 1-input DFF with Clock-Inhibit
Cell Svmbol

PropagaUon Delay Paramaler
tdn
10
KCL
KCL2
COR2

rup
10

KCL

1.988
1.456

0.034
0.034

1.875
1.356

0.023
0.034

0.045
0.067

7
7

I

12
Palh

CK,lHtoQ
CK,lHtoXQ

DflD

CK
IH
51

~

xa
Para meIer
Clock Pulse Width
Clock Pause Time
Data SetuD Time
Data Hold Time

Symbol
lew
ICWH
Iso
IHO

Typ (no)'

3.4
2.9
2.2
0.9

Inpul Loading
Faclor(lu)

Pin Nama

0

1

CK
IH
51
A,B

1

1
1

2

Pin Nama

OUlpul Driving
Faclor(lu)

a
xa

36
36

• Minimum values lor the typical operating oondition.
The values lor Ihe worsl casa operaling oondition are given by !he maximum delay
multiplier.

Function Table
INPUT

OUTPUT

MODE
CLK

0

A

B

51

0

Llo H

Oi

L

L

X

Oi

Oi

H

X

L

L

X

00

XOo

H

X LIoHIoL H

Si

00

XOo

H

X

Si

51

CLOCK

SCAN

L HloLIoH X

XO

Note: CLK • CK + IH

C1D-SDA EO

I

Sheet 1/3

I

I Page 11-17

3-137

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SDA
Equivalent Circuit
CLK

XBCK

--L

XCLK

--L --L

00---1

Q

SI

IACK

IXBCK
XQ
V2B

~~ ~

7

: :~LK

AO

: ACK

l>o
BO

: XBCK

l>o

C1Q-SDA-EO

XACK

BCK

Sheet 213
Page 11-18

3-138

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I

SDA

I

I • CG10 • Version

Definitions of Parameters

i) CLOCK MODE

i---

ICW-~~- ICWH--

CLOCK

DATA

: - - - 1011--1

a,xa

+-____~rl~--~-------------------

(OUTPUn ________________

..
C1o-SDA EO

Sheet 3/3

I

I Page 11-19

3-139

• CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number 01 BC

Function

soa

SCAN 1-input 4- bit OFF with Clock-Inhibit
Cell Symbol

!Up
10

KCL

2.650
2.031

0.034
0.034

Propagation Delay Para meIer
tdn
10
KCL
KCL2
COR2

2.463
2.075

0.023
0.034

0.045
0.067

7
7

I

42
Path

CK,lHto Q
CK,lHtoXQ

r01020304-

-

01

: > - XOI

-02
:>-X02
-03
:>-X03
-04
:>-X04

CKIHSI A-

B--<

Symbol
Icw
ICWH

Parameter

'---

Clock Pulse Width
Clock Pause Time
Data SetuD Time
Data Hold Time

Iso
IHO

Typ (ns)'

4.3
3.2
1.4
2.1

Inpul loading
Faclor(lu)

Pin Name

1
1
1
1
2

0
CK
IH
SI
A,B
Pin Name

Oulpul Driving
Faclor(lu)

0

36
36

XO

• Minimum values for the typical operating ccndition.
The values lor the worst case operaling oondition ere given by the maximum delay
multiplier.

Function Table
INPUT

OUTPUT

MODE

B

SI,On-l

0

XOn

L

L

X

Oi

Di

H

X

L

L

X

H

X LIOHtoL H

Si

Ono xOno
Ono xOn o

CLK

On

LIOH

01

A

CLOCK

SCAN
H

X

L HtoLIOH X

Si

sr

NoIII:CLK. CK+IH
n • 1-4

C10-S0B-EO

3-140

Sheet 1/4

I

I Page 11-20

I • CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I

I

SDa

Equivalent Circuit
01

02

o

XO

P

03

o

04

o

XO

o

XO

xo b

510---------15

01--

FF1

=
CLK
XCLK
ACK
XACK
BCK
XBCK

CKe- CK CLK
IHe- IH XCLK
ACK
Ae- A XACK
BCK
BO-< B XBCK

.----

CLK
XCLK
ACK
r-- XACK
r- BCK
XBCK

-r - -

---

;--

-

r

CLK
XCLK
ACK
XACK
BCK
XBCK

.----

CLK
XCLK
ACK
XACK
r- BCK
XBCK

;--

--

FFO

=

Equivalent Circuit (FFO)

AO--"'~- ACK

BO---"~-I ::K

4>o-------+o------+XACK

C1o-SDB-E

Sheet 2/4

l Page 11-21

3-141

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Call Ham.

SDa

Equivalent CircuH (FF1)

CLK

.l

XBCK

XCLK

.l.l

o

Q

so---I

TACK

T
XBCK
XQ

V2B

C1D-SDB-E

Page 11-22

3-142

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I· CG10 • Version

Cell Name

SDB

I

Definitions of Parameters

i) CLOCK MODE
_

lew

-~14--

ICWH _

CLOCK

DATA
_ 1 .. _

a,xa
(OUTPUn

C10-SDB-EO

.....------------~-------I

Sheel4/4

I

I Page 11-23

3-143

I . CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function
I

SHA

Number of BC

SCAN 1-input B-bit OFF with Clock-Inhibit
CelfSymbof
III

-

01020304050607-

f - - 01

p-- XOI

.0

KCl

2.950
2.575

0.067
0.067

Propagation Delay Parame.er
IeIn
.0
KCl
KCL2
COR2
2.950
2.500

0.051
0.073

0.056
0.101

4
4

I

68
Path

CK,lHloQ
CK,lHloXQ

f - - 02

P-- X02
r--- 03

p-- XQ3
p-- XQ4

f - - Q4

08-

f - - OS

P-- XOS
~Q6

p-- XQ6

CKIHSI AB--<

f - - 07

Parame.er
Clock Pulse Width
Clock Pause Time

p-X07
~Q8

p-- XQ8

L.---

Data Setup Time
Data Hold Time
Pin Name

Inpu' loading
Faclor (Iu)

0
CK
IH
SI
A
B

1
1
1
1
1

Symbol
lew

'CWH
Iso

'HO

Typ (ns)·
4.5
3.5
1.2
2.1

1

Pin Name

OU.put Driving
Faclor (Iu)

0
XO

18
18

• Minimum values for Ihe typical operating condition.
The values lor the worst case operating condition ara given by Ihe maximum delay
multiplier.

Function Table
InpulS
Mode

CLOCK

OUUlpulS

CLK

On

A

B

SI

On xOn

S

01

l

l

X

01

H

X

l

l

X

H

X

n

H

Si

H

X

L

U

X

SCAN

OJ
Hold
Hold

Si

Si

Note: ClK g CK + IH
n • 1-8

C1O-SHA-EO

3-144

Sheet 113

I Page 11-24

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
CeUNam.

SHA

Equivalent Circuit
01

CK o---;"""\...

08

02

CKI

IH n - - - I - r '

Do
XCKI

£&.

:~
:

:~I

FFo
CKI
XCKI

CKI
XCKI
AI
XAI
BI
XBI
XSlo XSOo

xc.,

FFo

~

AI

AI

XAI
BI
XBI

XAI
BI
XBI

XSIo XSOo

xc.,

00

L...---o

X01

XSIo
XO

00

01

SI

CKI
XCKI

00

as

02

L...---o xas

L....--oX02

Equivalent Circuit (FFO)

) 0 - - - - - - 0 xc.,
Do

o----i
.-------0 XSOo
(V1N)

» - - 0 00

CKI

...L
XSlo

o------i

TAI
TXBI
C1D-SHA-EO

Sheet 213
Page 11-25

3-145

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SHA

I

T· CG10

• Version

I

Definitions of Parameters

i) CLOCK MODE

I---

lew --.114-- ICYM _ _

CLOCK

DATA

I_------.J

_ _ _ _-JI _ _-+-_.JI\.~_ _

i-Q,XQ
(OUTPUT) _ _ _ _ _ _ _ _

lpeI_

V

+-__-JJI\.

C10-SHA-EO

3-146

Sheet 3/3

I Page 11-26

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Call Name

NumberofBC

Function

SCAN 1-input 8-bit DFF with Clock-Inhibit & a Output

SHB

Call Symbol
IUp
10

KCL

2.700

0.067

62

Propagation Delay Parameter
IIln
10
KCL
KCl2
COR2

2.763

0.051

4

0.056

Palh

CK,lHto Q

r--0102030405060708-

-01
-02
-03
-04
-05
-06
-07
-08

CKIHSIAB--<

Parameter

Clock Pulse Width
Clock Pause Time

'---

Data Setup Time
Data Hold Time
Pin Name

Input Loading
Factor (Iu)

0
CK
IH
SI
A
B

1
1
1
1
1
1

Pin Name

Oulpul Driving
Factor (Iu)

a

18

Symbol
lew
ICWH
Iso
IHO

Typ(n.)·

4.5
3.5
1.2
2.1

• Minimum values for !he Iypical operating condition.
The values for !he worsl case operating condition ara given by !he maximum delay
multiplier.

Function Table
OUtpul

Inputs

Mcde

CLOCK

CLK

On

A

B

Sf

S

Oi

L

L

X

01

H

X

l

l

X

Hold

H

X

n

H

Si

Hold

H

X

l

U

X

Si

SCAN

On

Note: ClK - CK + IH
n • 1 ~8

C10-SHB-EO j

Sheet 113

I Page 11-27

3-147

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SHB

Equivalent Circuit
01

CK v---r"""l....

02

08

CKI

IH n-.....I...J"'

Do

Do

Do

FFo

£&.

£&.

XCKI

::1
:

:~I

CKI
XCKI
AI
XAI
BI
XBI

CKI
XCKI
AI
XAI
BI
XBI

XSIo XSOo

XSIo XSOo

00

SI

~

0

XSIo

00

0

01

CKI
XCKI
AI
XAI
BI
XBI

02

08

Equivalent Circuit (FFO)
CKI

-L
Do

XBI

XCKI

-L -L

o---i
.....----OXSOo

» - - 0 00
CKI

-L
XSlo

o-----i

TAI

TXBI
C1D- HB-EO

Sheet
Page 11-28

3-148

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10 • Version

Cell Name

SHB I
Definitions of Parameters

i) CLOCK MODE

i--- lew --14--

ICWH -

CLOCK

DATA

~tpd_

a,xa
(OUTPUT)

C10-SHB-EO

Sheet 3/3

I Page 11-29

3-149

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nam.

NumberolBC

Funcllon

SHe

SCAN 1-input 8-bit DFF with Clock-Inhibit & XQ Output
C.IISymbol
IUp_

1O
2.613

KCL

0.067

Propagation De/ay Parlmel..
IeIn
1O
KCL
KCL2
CDR2

2.563

0.073

0.101

4

I

62
Path

CK,lHtoXQ

r--D1D2D3D4D5D60708CKIHSIAB--<

:>-- X01
:>-- X02
:>--X03
:>--XQ4
:>--xas
:>--X06
:>-- X07
:>--xaa

Parameler
Clock Pulse Width
Clock Pause Time

-

Data SetuD Time
Data Hold Time
Pin Name

Inpul Loading
Faelor(lu)

0
CK
IH
SI
A
B

1
1
1
1
1
1

Pin Name

OUlpuI Driving
Faelor(lu)

XO

18

Symbol
lew
ICWH
Iso
IHO

Typ (ns)'

4.5
3.5
1.2
2.1

• Minimum values for !he typical operating condition.
The values lor the worsl case operating condition are given by !he maximum delay
multiplier.

Function Table
Inputs

Mode

CLOCK

CLK

Dn

Oulpul
xOn

A

B

S

Dn

L

L

X

Di

H

X

L

L

X

Hold

H

X

n

H

Si

Hold

H

X

L

U

X

Si

SCAN

SI

NOIe: CLK • CK + IH
n = 1 ~8

C1D-SHC-EO

3-150

Sheet 113

I Page 11-30

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SHe

Equivalent Circuit
01

CK v---r-,....

02

OS

CKI

IH n---'.....r'

D.

D.

D.

FF.

FF.

FF.

XCKI

::1
:

:~I

CKI
XCKI
AI
XAI
BI
XBI

CKI
XCKI
AI
XAI
BI
XBI

XSIo XSOo

XSIo XSOo

~

CKI
XCKI
AI
XAI
BI
XBI
XSI.

xc.

xc.

' - - - 0 XCI

L....--o

xc.

SI
XC2

L....--oxcs

Equivalent Circuit (FFO)

) 0 - - - - - - 0 XC.

0.0---1

.------0 XS~

CKI

-L
XSlo

0-----1

I AI

I XBI
C10-5HC-EO

Sheet 213
Page 11-31

3-151

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Call Nam.

SHe

1 • CG10 • Version

I

OefinHions of Parameters

i) CLOCK MODE
-

Ir;w--+Ot--- ICWH_

CLOCK

DATA

: - - - Ipd ___

a,xa
(OUTPUT)

C10-SHC-EO

3-152

--------1----'1"'-+----------

Sheet 313

I Page 11-32

I • CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number of 8C

Function

SCAN 8-bit DFF with Clock-Inhibit & 2-t0-1 Data Multiplexer

SHJ

Cell Symbol
!Up

-

Al81A282A3-

to
-

01

3.013
2.575

~XOI

-

KCL

0.067
0.067

Propagation Delay Parameter
teln
CDR2
to
KCL
KCL2

3.025
2.500

0.045
0.062

0.067
0.112

4
4

I

78
Path

CK,lHtoQ
CK,lHtoXQ

02

~X02

-

03

83-

~XQ3

A4-

,--- Q4

84-

~XQ4

A585A686A787A886-

-05
~X05

-06
~X06

-07
~X07

-08

Parameter

~X08

Clock Pulse Width
Clock Pause Time

--<
--<

AS
8S
CKIHSI A8

Data SetuD Time
Data Hold Time

Symbol
tcw
tcw><
tso
tHO

Typ (no)·

4.5
3.5
1.9
2.0

--<

'---

Input loading
Factor (Iu)

Pin Name

1

An, Bn
(n=I-8)
AS,BS
CK
IH
SI
A,B

1
1
1
1
1
Output Driving
Factor (Iu)

Pin Name

a

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by !he maximum delay
multiplier.

18
18

XO

Function Table
Inputs

Outputs

Mode

CLOCK

CLK

DO

A

B

SI

On

XOn

S

Di

l

l

X

Di

Di

H

X

l

l

X

H

X

n

H

Si

H

X

l

U

X

SCAN

Hold
Hold
Si

Si

=
=

Note: ClK
CK+ IH
DO = AO-ASC+1I0BSC
n
1-8

C1o-SHJ EO

Sheet 113

I Page 11-33

3-153

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nam.

SHJ

Equivalent Circuit
Al

CK
IH

Bl

A2

AS

B2

B8

CKI
Bo

Ao
XCKI

Lt:
,0---1)0 Lt:

.0---1)0

:~
:

AS~ASo

:~I

~

Ao

Ao

Bo

FFo

Bo

FFo

=

CKI
XCKI
AI
XAI
BI
XBI
ASo

As.

As.

BSo

BSo

BSo

XSIo XSOo

XSIo XSOo

XSIo XSOo

01

CKI
XCKI
AI
XAI
BI
XBI

XOI

02

~

CKI
XCKI
AI
XAI
BI
XBI

X02

00

XOo

as

X08

BS~BSo
SI

Equivalent Circuit (FFO)

) 0 - - - - - - 0 XOo

Ao

ASo
Bo
SSo

....------- XOI

A282-

-02

C2-

:>--XQ2

10383-

-03

C3A484C4A5-

:>--X03

-04
:>--XQ4
-

85C5A6-

86C6A7B7C7AS-

05

:>--xas

Parameter

-06

Clock Pulse Width
Clock Pause Time

Symbol
tew
tCWH

Typ (ns)·

4.5
3.5

:>--X06
-

07

Data SetuD Time
Data Hold Time

tso
tHD

2.4
1.9

:>-- X07
-

88C8-

08

:>--X06

AS--(

BS--(
CS--(
CKIHSI AB--(
'---

Pin Name

Input loading
Faclor (Iu)

An, Bn, Cn

1

(n-l

~8)

AS,BS,CS

1
1
1
1
1

CK
IH
SI
A,B
Pin Name

Output Driving
Factor (Iu)

0
XO

18
18

C10-SHK-EO

3-156

I

Sheet 1/3

• Minimum values for !he typical operating condition.
The values for Ihe worst case operating condition are gill9n by !he maximum delay
multiplier.

I Page 11-36

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SHK

Equivalent Circuit

CKv-"""""'T....

AI BI CI

A2 B2 C2

Ao Bo Co

Ao Bo

AS B8 CS

CKI

IHn...~-r

Co

Ao Bo Co

XCKl
FFo

: :1

:

:~I

CKI
XCKl
AI
XAI
BI
XBI
AS o
BS o
CSo
XSIj, Xso.,

01

XOI

FFo

FFo

CKl
XCKl

1'1

~
XAI
BI
XBI
AS o
BS o
CSo
XSIo Xso.,

02

CKl
XCKI
AI
XAI
BI
XBI
AS o
BS o
CS o
XSIo XSq,

X02

00

XOo

as

XOS

S l o - - - - I ) ( > - - - - - - -.......

Equivalent Circuit (FFO)
Ao
AS o
Bo

) 0 - - - - - - 0 xOo

BSo
Co
CSo

....----0() xsq,
(VIN)

) 0 - - - 0 00

CKI

--L
XSlo

0-----1

TAI
TXBI
C10-SHK-EO

Sheet 213
Page 11-37

3-157

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SHK

• Version

I

I

DefinHions of Parameters

i) CLOCK MODE

'CYM_

I---'cw
CLOCK

,

'(

.,so .. I--

IHO ..

DATA

I--

'peI_

a,xa
(OUTPUT)

Function Table
Inpuls
Mode

CLOCK

SCAN

Outpuls

ClK

DO

A

B

SI

an

XOn

S

Oi

l

l

l(

01

01

H

X

l

l

X

H

X

n

H

Si

H

X

l

U

X

Hold
Hold
Si

SI

Note: ClK = CK + IH
DO • AOeASO+BOeBSO+CO
n .1-8
-CSO

C1D-SHK EO

3-158

I

Sheet 3/3

I

I Page 11-38

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Call Name

SFDM

• Version

I

Function

SCAN 1-input OFF with Clock-Inhibit

Cell Symbol

!Up
to

KCL

1.444
1.831

0.067
0.067

Propagation Delay Parameter
teln
to
KCL
KCL2
COR2

1.481
1.806

0.056
0.045

0.095
0.056

4
4

Number 01 BC

I

10
Path

CKtoQ
CKtoXQ

'[fa

xc

CK
IH
SI
A
B

SO

Parameter

Clock Pulse Width
Clock Pause Time
Data Setup Time
Data Hold Time

Symbol
tew

Typ (ns)'

tew><

2.5
2.5

tso
tHO

1.0
0.9

Input loading
Factor (Iu)

Pin Name

2
1
1

0
CK
IH
SI
A.B

2
2

Pin Name

Output Driving
FactorClu)

18
18

C

SO

• Minimum values lor the typical opereting condition.
The values lor the worst case operating CXlndition are given by the maximum delay
multiplier.

Function Table
Outputs

Inputs
Mode

CLOCK

CLK

0

A

B

51

C.SO

XC

S

Oi

L

L

X

Oi

l5r

H

X

L

L

X

Hold

H

X

n

H

SI

Hold

H

X

L

1I

SCAN

X

SI

Sf"

NOla : CLK • CK + IH

C10-5FDM-EO

Sheet 113

I Page 11-39

3-159

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

SFDM
Equivalent Circuit
ClK

--L

XBCK

XClK

--L --L

00---1

xc

Slo---I

c

T
ACK

so

~~'----:::

AO-"'4O---~~~~~":.:,

BO_4O-==: :'
C10-SFDM-EO

Sheet 213
Page 11-40

3-160

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SFDM

I • CG10 • Version

I

Definitions of Parameters

i) CLOCK MODE

i---tcw--t--tCWHCLOCK

'{

DATA

i--tpda,xa
(OUTPUT)

C10-SFDM-EO

I

Sheet 3/3

I

I Page 11-41

3-161

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name

Function

SFDO

Number 01 BC

SCAN 1-input OFF with Clear and Clock Inhibit
Cell Symbol

Propagation Delay Parameler
Idn
10
KCL
KCL2
CDR2

\Up

10

KCL

1.669
1.850
1.963

0.072
0.067
0.067

1.594
2.044
1.700

0.062
0.045
0.062

0.101
0.056
0.101

4
4
4

I

11
Path

CKloQ
CKloXQ
ClloQ,XQ

r-0-

-a
:r--- xa
-so

CKIHSIAB

--<
CL

Parameter

Inpul Loldlng
Faclor(lu)

Pin Name
CK.IH
SI
A,B
CL

2
1
2
2
2

Pin Name

Oulput Driving
Factor (Iu)

0

..

a
xa

18
18
18

SO

Symbol

Typ (ns)'

Clock Pulse Width
Clock Pause Time

lew
lew!<

2.9
2.7

Data SetuD Time
Data Hold Time

Iso

1.7
1.1

Clear Pulse Width
Clear Release Time
Clear Hold Time

ILW

IHO

I REM

2.7
1.2

tlNH

3.0

• Minimum values lor the typical operating condition.
The values lor the worsl case operating oonation are given by !he maximum delay
multiplier.

Function Table
Outputs

Inputs
Mode
CL

0

A

S

H

Oi

H

H

X

B

SI

L

L

X

X

L

L

X

L

X

X

X

X

H

H

X

n

H

Si

H

H

X

L

U

X

CLK

CLOCK

SCAN

a,so xa
01

Di
Hold

L

H
Hold

Si

51

Note : CLK • CK + IH

C1~FD:>-EO

3-162

Sheet 1/3

J

I Page 11-42

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

SFDO
Equivalent Circuit
XBCK

CLK

.....L.
D

XCLK

.....L. .....L.

o-----i

xc

Slo---\

c

T
ACK

so

~~ ~L. ---I:~::
____

4-_::

AO_

BO-4---~=:

C1o-SFDO-EO

:

Sheet 2/3
Page 11-43

3-163

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

SFDO
Definitions of Parameters

i) CLOCK MODE
tCWH-

I---tcw
CLOCK

~tso"" -tHO....

,

DATA

-tpel-

a,xa
(OUTPUT)

i i) CLEAR MODE

i.-tRe.r--

CK

-tLW--'
CLEAR

~

-tpel....

a,xa
(OUTPUT)

-tlNHCL

C10-SFDO-EO

Sheet 313
Page 11-44

3-164

I • CG10 • Version
I Number 01 BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

SFDP

SCAN 1-input DFF with Clear, Preset, and Clock Inhibit
Cell Symbol

PropagaUon Delay Parameler
!dn
10
KCL
KCL2
COR2

!Up

PR

0-

KCL

1.688
2.231
2.269
2.844

0.072
0.067
0.067
0.072

1.588
2.044
1.675
0.644

0.062
0.045
0.062
0.045

0.101
0.056
0.101
0.056

4
4
4
4

12
Path

CKtoQ
CKto XQ
CLtoQ,XQ
PRtoQ,XQ

-0

CKIHSIA-

B

10

I

::>-

XO

-so

--<
Parameter

CL

Symbol
lew

Input loadIng
Factor (Iu)

Pin Name
CK,IH
SI
A, B
CL. PR

2
1
2
2
2

Pin Name

Oulput Driving
Factor (Iu)

0

2.9
2.7

Data SetuD Time
Data Hold Time

tso
tHO

1.7
1.1

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW

2.7
1.2
3.0

tREM
tlNH

Preset Pulse Width
Preset Release Time
Preset H old Time

18
18
18

0

xo
SO

Typ (ns)·

ICWH

Clock Pulse Width
Clock Pause Time

tpw
I REM
tlNH

3.9
0.6
3.9

• Minimum values for the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Outputs

Inputs
Mode

CLOCK

CLK

Cl

PR

0

A

B

SI

O,SO

XQ

S

H

H

OJ

L

l

X

Oi

Oi

H

H

H

X

L

l

X

Hold

X

L

H

X

X

X

X

L

H

X

H

l

X

X

X

X

H

L

X

l

l

X

X

X

X

Prohib"ed

H

H

H

X

n

H

Si

H

H

H

X

L

U

X

SCAN

Hold

Si

Si

Note: ClK • CK+ IH

C1D-SFDP EO

I

Sheet 1/4

I Page 11-45

3-165

IIIDIII

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nome

SFDP
Equivalent Circuit
Clo-------------~------------------------------~

XBCK

CLK

XClK

-L -L

-L
Oo---l

XQ

BCK

XClK

ClK

CLK
....---.J-J

XACK

PRo----------r------------~

XACK

-L
Slo----/

T

T

XBCK

ACK

Q

so

~~
---------:.. ::

AOl----f--c;-_: :

...

BO~-c;------~~~~~~: :
C10-5FDP-EO

Sheet 2/4
Page 11-46

3-166

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cefl Name

SFDP

I • CG10 "Version

I

I

Definitions 01 Parameters

i) CLOCK MODE
ICWH-

!---Icw

CLOCK

-Iso- -IHO....

DATA

f - - I .. Q,XQ

(OUTPUl)

i i) CLEAR MODE
-IREM-

'(

CK

CLEAR

-

i---llW-

:'-1 ..Q,XQ

(OUTPUl)

J
:'-IINH-

CLEAR

C10 SFDP EO

Sheet 3/4

I Page 11-47

3-167

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

1 • CG10 • Version

eeilN.me

SFDP

I

Definitions of Parameters

iii) PRESET MODE
CK

i---Ipw-

PLESET

-

a,xa
(OUTPUT)

1,----------------

i--IINH-

PLESET

C10-5FDP-EO

3-168

1

Sheet 4/4

1

I Page 11-48

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

_l

Cell Name

SFDR

• Version
Number 01 BC

Function

36

SCAN 4-input OFF with Clear and Clock Inhibit
Cen Symbol

Propeg.llon Delay Parameler
Idn
KCL
KCL2
COR2
10

IUp

10

KCL

2.325

-

0.072

-

2.344
2.400

0.062
0.062

0.101
0.112

4
4

Path

CKtoQ
CLtoQ

;--

DC-

-OA
OS
OC

00-

-00

OA-

osCKIHSIAB

-so

--<
Symbol

Typ (ns)'

Clock Pulse Width
Clock Pause Time

Icw
ICWH

3.2
3.5

Data Setup Time
Data Hold Time

Iso
IHO

0.7
1.5

Clear Pulse Width
Clear Release Time
Clear Hold Time

ILW
I R~"

3.2
1.8
3.6

Parameter

CL

Inpul loading
Factor (Iu)

Pin Name
CK.IH
Sl
A,B
CL

2
1
2
1
1

Pin Name

OulpUI Driving
Factor (Iu)

0

18
18

0

so

tlNH

• Minimum values for the typical operating oondition.
The values !orthe worsl case operaling condition are given by the maximum delay
multiplier.

Function Table
Inputs
Mode
CLK

CLOCK

CL

0

Outputs

A

a.,SO

B

SI

Pi
Hold

S

H

Di

L

L

X

H

H

X

L

L

X

X

L

X

X

X

X

L

H

H

X

n

H

Si

Hold

H

H

X

L

U

X

Si

SCAN

Note: CLK = CK+ IH

C1o-SFDR EO

Sheet 1/4

I Page 11-49

3-169

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
eellName

SFDR

Equivalent Circun

DA

DC

DB

DO

(

)

OB

QA

OC

00

)

o

0

0

(

0

Slo---------1 S

0-

SOl-FFO
CK

IH

g::

CK

IH

A 0-- A
B 0-<:8
Cl 0 -

ClKXClKACKXACKBCK
XBCK

ClK
XCLK
ACK
XACK
BCK
XBCcK

FFO

-,...-

CLK
XClK
,....-- ACK
; - XACK
BCK
xe~K

FFO
CLK
XClK
,....-- ACK
; - XACK
r- eCK
XB~K

r-

r-

ClK
XClK
ACK
; - XACK
r- BCK

so

XB~~

CNTO
Cl.

I
Equivalent Circun (CNTO)
CK

u----t-....

IH

) ( ) - - - - - - . ClK

)(>-...-.

XCLK

---~~

AO........

L-L..------XACK

C10-SFDR-EO

eO---I

)O--_XSCK

'------BCK

She t 214
Page 11-50

3-170

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SFDR

Equivalent Circuit (FFO)

XBCK

ClK

-'--

XCLK

-'-- -'--

00----;

t----oCl.

50----;

I

ACK

XBCK

' - - - - - - - - 1 )0---00
Equivalent Circuit (FF1)
ClK

-'--

XBCK

XClK

-'-- -'--

00----;

t----oCLo

50----;

ACK

I

XBCK

C10-SFDR-EO

~-------I

)0---00

L...-_ _ _ _- ;

)0---050

Sheet 3/4
Page 11-51

3-171

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 • Version

J

SFDR

I

Definitions of Parameters

i) CLOCK MODE
-lew

tcWH-

CLOCK

I--tso- ;---t HO-

DATA

-tpd-

a,xa
(OUTPUT)

i i) CLEAR MODE

~tRE"-

CK

CLEAR

-

-tLW-

-tpd-

a,xa
(OUTPUT)

i---t.NH-

CL

C10-SFDR EO

3-172

Sheet 4/4

I Page 11-52

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function
I

SFDS

'" CG10 • Version

I

Cell Symbol

Propagation Delay Parameter

\Up

Number 01 BC

I

SCAN 4-input DFF with Clock Inhibit
!dn

to

KCl

to

KCl

KCL2

CDR2

1.919
2.056

0.067
0.067

1.888
2.031

0.056
0.056

0.090
0.090

4
4

31
Path

CKto QA-QC
CKtoQD

~

DADSDC00-

r--- as
r-- oc

CKIHSIAS --<

r---

~

OA

~OD

SO

-

Parameter

Clock Pulse Widlh
Clock Pause Time
Data SetuD Time
Data Hold Time

Pin Name

Input loading
Factor (Iu)

0
CK.IH
SI
A.S

2
1
2
1

Pin Name

Output Driving
Factor (Iu)

18
18

a

so

Symbol
tew
tCWH
tso
tHO

Typ (ns)·

2.9
2.6
0.0
1.4

• Minimum values lor the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Inputs
Mode

CLOCK

Outputs

On

A

S

SI

S

Di

l

l

X

Di

H

X

l

l

X

Hold

H

X

n

H

Si

H

X

l

U

X

SCAN

an.

so

ClK

Hold
Si

Si

Nola: ClK = CK+ IH
n = A-D

Cl0 SFD5-EO I

Sheet 1/4

I Page 11-53

3-173

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SFDS

Equivalent Circuit
OA

SI

QA

DB

OB

DC

QC

DO

C>-------.. .
so

CK

CNTO~=~:d

IH

A
B

°iJ

S
ClK
XClK
ACK
XACK
BCK
XBCK

a
QQ

FFI

Equivalent Circuit (FF1)
XBCK

ClK

-.L

XCLK

-.L -.L

r--~~-----O

1-+----1

00---1

BCK

XClK
XACK

XClK

-.L

-.L -.L

I

II

a

» ......- - - - 0 QQ

ClK

ACK

s
ACK

ClK

XACK

I

XBCK

IH K B C L K
XCLK
C
CNTO
ACK
A
XACK
B
BCK
XBCK

CK v---r"""\...
IH

Equivalent Circuit
(CNTOl

A

o----j)o,--I)or

~XACK

»-----... ClK
B
) ( ) . - -.. XCLK

o----j)o,--I)o..

C10-5FDS-EO

ACK

XBCK

~BCK

Sheet 214
Page 11-54

3-174

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SFDS

ott
s

CLK
XCLK
ACK
XACK
BCK
XBCK

FF2

0

co

Equivalent CiraJit (FF2)

r---i)c>-----O so
XBCK

CLK

--L

XCLK

--L --L

...-.-~

)0------00

0

XCLK
XACK

XCLK

--L

--L --L

ACK

T

s

XCLK

T

ACK

T

CLK

T

BCK

-L

XACK

T

XBCK

C10-5FOS-EO

Sheet 3/4

Page 11-55

3-175

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10 .. Version

Cell Name

SFDS

I

Definitions of Parameters

i) CLOCK MODE

i---1cw--i---ICWHCLOCK

1\

:-Iso-I-IHO'"
DATA

1---1",,a,xa
(OUTPUl)

C10-SFD5-EO

3-176

I

Sheet 4/4

I Page 11-56

I • CG1D • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function
I

SFJD

Number of BC

SCAN J-K FF with Clock Inhibit
Cell Symbol

Propagation Delay Parameter
tdn
KCL
KCL2
COR2
to

!Up
to

KCL

2.025
2.163
1.750

0.072
0.067
0.067

1.875
2.369
1.544

0.067
0.045
0.051

0.112
0.056
0.095

4
4
4

I

14
Path

CKtoQ
CKtoXQ
CLtoQ,XQ

r-JK-

-a
::>-- xa

CKIHSIAB --C

-so

Symbol
tew
tcWH

Parameter

CL

Clock Pulse Width
Clock Pause Time

Pin Name

Input Loading
Factor (Iu)

J, K
CK,IH
SI
A,B
CL

1
1
2
2
2

Pin Name

Output Driving
Factor (Iu)

a
xa

Data SetuD Time
Data Hold Time

(J)
J

tso
tHO

2.4
0.4

Data SetuD Time
Data Hold Time

(K)
(K)

tso
tHO

2.0
0.1

tLW
t REM

2.7
1.3
2.7

Clear Pulse Width
Clear Release Time
Clear Hold Time

18
18
18

SO

Typ (ns)'
2.7
3.1

tlNI-f

• Minimum values lor the Iypical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Inputs
Mode

CLOCK

OLK

CL

S
S
S
S

H

L

H

H

H

J

K

Oulputs

a,so xa

A

B

SI

L

L

L

X

Hold

H

L

L

X

Toggle

H

L

H

L

L

X

L

H

H

L

L

L

X

H

H

X

X

L

L

X

X

L

X

X

X

X

X

H

H

X

X

n

H

Si

H

H

X

X

L

U

X

SCAN

Sheet 1/3

L
Hold
H

L
Hold
SI

Nole : CLK
C1D-SFJD-EO

H

SI
~

OK + IH

I Page 11-57

3-177

• CG10 • VersiOn

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SFJD
Equivalent Circuit

»--oxo
Ko----'

CLo-----------------4---~------~----------+_--------~

I
ACK

IIIDI

~~ ~--t---i[>o-e CLK

'------_e XCLK

I

XBCK

~----1 ~>------ XACK
B O----_~----------- XBCK

L-...j)c>- BCK

C1o-SFJD-EO

Sheet 213
Page 11-58

3-178

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

SFJD
Definitions of Parameters

i) CLOCK MODE
f---1cw

ICWH-

CLOCK

1\
1-190- -tHO....
DATA

~Ipd-

a,xa
(OUTPUT)

i i) CLEAR MODE
-IRE....

CK
-ILW-

CLEAR

~

-Ipd ....

a,xa
(OUTPUT)

f4- t INHCL

C10-SFJD-EO

Sheet 3/3
Page 11-59

3-179

CG 10 Series Unit can libra?,

..

3-180

CMOS Channeled Gate Arrays

CMOS Channeled Gate Arrays

CG10 Series Unit Cell Ubrary

Non-scan Flip-flop Family

Page

Unit Cell
Name

Function

Basic
Cells

3-183

FOM

Non-scan 0 Flip-flop

6

3-185

FON

Non-scan 0 Flip-flop with Set

7

3-187

FOO

Non-scan 0 Flip-flop with Reset

7

3-189

FOP

Non-scan 0 Flip-flop with Set and Reset

8

3-192

FOO

Non-scan 4-bit 0 Flip-flop

3-194

FOR

Non-scan 4-bit 0 Flip-flop with Clear

26

3-197

FOS

Non-scan 4-bit 0 Flip-flop

20

3-199

F02

Non-scan Power 0 Flip-flop

7

3-201

F03

Non-scan Power 0 Flip-flop with Preset

8

3-203

F04

Non-scan Power 0 Flip-flop with Clear and Preset

9

3-205

F05

Non-scan Power 0 Flip-flop with Clear

8

3-207

FJO

Non-scan Positive Edge Clocked
Power J-K Flip-flop with Clear

21

12

3-181

CG10 Series Unit CeR Ubraty

3-182

CMOS Channeled Gate Atrars

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name

I • CG10 • Version
Number of BC

Function

FDM

I

Non-SCAN OFF
Cell Symbol

tup
to

KCL

1.094
1.350

0.067
0.067

Propagation Delay Parameter
tdn
10
KCL
KCL2
CDR2

1.125
1.475

6
Path

CKtoQ
CKtoXQ

0.051
0.051

'={to

CK

XQ

Parameter

Symbol

Typ (ns)'

Clock Pulse Width
Clock Pause Time

tew
tCWH

2.5
2.5

Data SetuD Time
Data Hold Time

Iso

1.4
1.0

tHO

Input loading
Factor (Iu)

Pin Name

2
1

0
CK

Pin Name

Output Driving
Factor (Iu)

Q
XQ

18
18

• Minimum values for the typical operating conation.
The values for the worst case operating condition era given by the maximum delay
multiplier.

Function Table
Outputs

Inputs

0

CK

Q

H

i
i

H

L

L

H

L

C10-FDM EO

XQ

Sheet 1/2

I

I

Page 12-1

3-183

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

FDM
Equivalent Circuit
XCLK
-L
..------i ) 0 - - - - - - 0

ClK

-L

xc

00---1

TXClK

CK

c

TClK
XClK

CLK

-L

-L

TClK

TXCLK

o------J>orl)o- CLK
•

L-.XClK

Definitions of Parameters

I---- lew

ICWH-"

CK

~
I - - - I s o - 4-IHO'"

o

W'

JI\
+-Ipd-'

Q,XQ

C1D-FDM-EO

Sheel2l2
Page 12-2

3-184

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Funcllon

FDN

Number

I

Non-SCAN DFF with SET
Cell Symbol
rup
10

KCL

1.125
1.538
1.400

0.067
0.067
0.067

Propagation Delay Parameler
tdn
10
KCL2
KCL
CDR2
1.094
1.513
0.669

0.051
0.045
0.045

0.067

0' Be

7
Path

CKloQ
CKlo XQ
SIOQ,XQ

4

S

'=D=a

CK

XQ

Parameter

Clock Pulse Width
Clock Pause Time
Data SeluD Time
Data Hold Time
Inpul loading
faclor(lu)

Pin Name

Set Pulse Width
Set Release Time S
Set Hold Time

2
2
1

0
S
CK

OUlpul Driving
faclor(lu)
18
18

Pin Name

0

xo

Symbol
lew
lew><

Typ (ns)'
2.5
2.5
1.4
1.0

Iso
1"0

2.5
0.2
2.4

Isw
I REM
tlNH

• Minimum values for !he typical operating condition.
The values for the worsl case operaling condition are gillen bv the maximum delay
multiplier.

function Table
Inputs

Outputs

S

0

CK

0

XO

L

X

X

H

L

H

H

H

L

H

L

i
i

L

H

C1o-FDN EO

Sheet 1/2

I

I

Page 12-3

3-185

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

FDN

Equivalent Circuit
So-~r-----------~

CKO

XCKO

-L

0

-L

XQ

o

T

TCKO

XCKO

-L

XCKO

TCKO

CKO

-L

T
XCKO

CK~CKO

. L---.

XCKO

Dllfiniti9[lS Q.f Param!1ters

11 tCw, tGWH, tsD, tHD and tpd (CK- 0, XO)
ICWH-

I---Icw

CK

~

J
- I s o -!--IHO"

o
~Ipd'"

a,xa
2) t8W, tREM, tlNH, and tpd (8 _0, XO)

CK

S--JI
I,..-+-----S

s

--+------S-- --S--+-'
S--+-

a

xa

------ -------I"---+-----S -- ---

C1D-FDN-EO

Sheet 2/2
Page 12-4

3-186

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

Function

FDO

I • CG10 • Version
I Number of Be

Non-SCAN DFF with RESET
Cell Symbol
tup
to

KCL

1.206
1.350
1.250

0.067
0.067
0.067

Propagation Delay Parameter
tdn
to
KCL
KCl2
CDR2

1.113
1.613
1.025

J

7
Path

CKtoQ
CKto XQ
RtoQ, XQ

0.056
0.051
0.056

'yO

CK

XC

Parameter

R

Clock Pulse Width
Clock Pause Time

Input loading
Factor (Iu)

Pin Name
D
R
CK

2
2
1

Pin Name

Output Driving
Factor (Iu)

C
XC

18
18

Typ (ns)'

Symbol
tcw
tcw><

2.5
2.5

Data Setup Time
Data Hold Time

tso
tHO

1.4
1.0

Reset Pulse Width
Reset Release Time (R)
Reset Hold Time

tRW

2.5
0.6
2.1

tREM
ttNI-f

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Inputs

Outputs

R

D

CK

C

XC

L

X

X

L

H

H

H

H

L

H

L

l'
l'

L

H

C1Q-FDO-EO

Sheet 1/2

I

Page 12-5

3-187

lID

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

FDO

Equivalent CircuH
CKO

XCKO

-L

-L

c
xc

00---1

TCKO

T
XCKO

CK~CKO

. L--..

XCKO

R

Definitions of Parameters

1) tCW, tCWH, tSO, tHO and tpd (CK _Q, XQ)
ICWH-

I--tcw

CK

~
- I s o - ... tHO'"

D
.... tpel .....

a,xa
2) tRW, tREM, tINH, and tpd (R_ Q, XQ)

CK

\
1,.-+-----\

R

\---f-\

a

-I~--+-----\

-1_--+-----\ .... .

xa
C1~FDO-EO

.... .

\---+Sheet 212
Page 12-6

3-188

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

FDP

I • CG10 "Version
I Number of BC

I

Non-SCAN DFF with Set and Reset
Cell Symbol
!Up
10

1.225
1.531
1.400
1.588
S

D-

I--

KCL
0.067
0.067
0.067
0.067

Propagation Delay Parameler
Idn
KCL
KCL2
io
CDR2
1.100
0.056
1.563
0.051
0.994
0.056
0.631
0.051

8
Path

CKtoO
CKtoXO
RtoO. XO
StoO. XO

C

CK-

~XC

R

Parameter

Clock Pulse Width
Clock Pause Time

Inpul Loading
Factor (Iu)

Pin Name
D

2
2
2
1

S

R
CK

Oulpul Driving
Faclor(lu)
18
18

Pin Name
C

xc

Symbol
lew
ICWH

Typ (ns)'
2.5
2.5

Data SetuD Time
Data Hold Time

Iso
IHO

1.4
1.0

Set Pulse Wid1h
Set Release TimelS)
Set Hold Time

tsw
IRE\!

2.5
0.2
2.4

Reset Pulse Width
Reset Release Time (R)
Reset Hold Time

IRW
IRE\!

tlNH

2.5
0.6
2.1

tlNH

• Minimum values for the typical operating condition.
The values for the worsl case operaling condition are given by the maximum delay
multiplier.

Function Table
Inputs

Outputs

S

R

D

CK

C

XC

H

L

X

X

L

H

L

H

X

X

H

L

L

L

X

X

inhibited

H

H

H

H

H

L

C1Q-FDP-EO

I

t
t

Sheet 1/3

H

L

L

H

I

I

Page 12-7

3-189

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

FDP

Equivalent Circuit
SO-~~----------~

CKO

c

-L
o

xc

-,-

-,-

CKO

XCKO

R

CK~CKO
•

C1Q-FDP-EO

~XCKO

Sheet 213
Page 12-8

3-190

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

eellName

FOP

Definitions of Parameters

1} tCW, tCWH, tSD, tHD and tpd (CK-.O, XO)
tcWH-

: - - - tcw

CK

~

I--

tso- .. tHO"

W
Jr\.

o

~

tpd __

a,xa
2} tRW, tREM, tlNH, and tpd (R -.0, XO)
--+01--- tCWH
CK

~
Ir+-----~

R

~---t--\.

a

"'---+-----~ - - - --Ir--+-----~ ----~--+-'

xa

3} tSW, tREM, tlNH, and tpd (S-.O, XO)
tCWH-

:---tcw

CK

I--- tsw
~

s
a

xa

--=:

REM

...

~

Ipd_

-_._.- .-_...

~----~--+-'

...... .......

C10-FDP-EO

~-~

~-----

Sheet 3/3
Page 12-9

3-191

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 • Version

Function

FDQ

Number of BC

Non-SCAN 4-bit DFF
Cell Symbol
!Up

to

KCL

2.106

0.067

Propagation Delay Parameter
tdn
to
KCL
KCl2
CDR2

1.713

I

21
Path

CKtoQ

0.045

Dnsyy

r-- QA
CK

r-os
r-OC
r - OD

---<

Parameter

Clock Pulse Width
Clock Pause Time
Data SetuD Time
Data Hold Time

Symbol
tew
teWL
tso
tHO

Typ (ns)'

2.5
2.5
0.7
1.8

Input loading
Factor (Iu)

Pin Name
D
CK

1
1

Pin Name

Output Driving
Factor (Iu)

0

18
• Minimum values lor the typical operating condition.
The values for the worst case operating ccndition are given by the maximum delay
multiplier.

Function Table
Input

Output

CK

0

Q

J..
J..

H

H

l

L

C10-FDO-EO

3-192

Sheet 1/2

I Page 12-10

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

FDQ
Equivalent Circun

XCKO

CKO

..l

..l

DAo-------~

)0-";--0 OA

CK~CKO
•

LXCKO,

,,

ICKO

IXCKO

DB

.----------------------------------------4
0-------+
+-oOB

DC

0-------+

DD

+-oOC

+-OOD
0-------+
,
----------------------------------------,

Definitions of Parameters
ICWL-

i-"-Icw

CK

i

J

V-

- I s o - 4-IHO'"

o
- I .....

a

C10-FDQ-EO

Sheet 212
Page 12-11

3-193

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 • Version

Function

FOR

Number 01 BC

Non-SCAN 4-bit DFF with CLEAR
Cell Symbol

Propagation Delay Parameter
IeIn
KCL
KCL2
COA2
to

\up
to

KCL

1.650

0.067

-

-

2.263
1.363

I

26
Path

CKtoQ
CLtoQ

0.045
0.045

TrYT
-QA
,..-- OB

CK-

r

-00
-00

Parameter

Input loading
Factor (Iu)

Pin Name

1
1
1

0
CK
CL

Pin Name

Output Driving
FaClor(lu)

0

18

Symbol

Typ(ns) •

Clock Pulse Width
Clock Pause Time

tew
tcww

2.5
2.5

Data Setup Time
Data Hold Time

tso
tHO

0.7'
1.8

Clear Pulse Width
Clear Release Time
Clear Hold Time

tlW
tRE!!
tlNH

2.5
1.0
2.9

• Minimum values lor the typical operating condition.
The values lor the worst case operating condition 818 gill8n by the maximum delay
multiplier.

Function Table
Inputs

0

D

CL

X

X

L

L

l'
l'

L

H

L

H

H

H

C1G-FDR-EO

3-194

Output

CK

Sheet 113

I Page 12-12

• CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

FOR
Equivalent Circuit

CLO

DA

o---------!-I

CK

o---/:>orI)o-.
•

)(>--;--0 OA

CKO

LXCKO

CL~CLO

CLO
___ • _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 4

DBO~------~

+-oOB

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ • _ _ _ _ _ _ 4I

DC O~------+

+-ooc

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 4I

DO

O~------+

+-000
I

--------------------------------------_ ..

lID

C1D-FDR-EO

Sheet 213
Page 12-13

3-195

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Namlt

FDR

Definitions of Parameters

1) tCW. tCWH. tSD. tHD and tpd (CK - OA - OD)
CK

o

2) tLW. tREM. tINH. and tpd (CL_ OA - OD)

--14'-- I CWH
CK

~
r+-----~

CL

IINH

~-~
'--+-----~-- ---

C1Q-FDR-EO

Sheet 313
Page 12-14

3-196

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

I • CG10 • Version
I Number 01 BC

Non-SCAN 4-bit DFF

FOS

Cell Symbol

!Up
10

KCL

1.894

0.067

Propagation Delay Parameler
Idn
10
KCL
KCL2
COR2

1.531

I

20
Path

CKtoQ

0.051

Tyoror
-QA

-os

CK-

-OC

-00

Parameter

Clock Pulse Width
Clock Pause Time
Data Setup Time
Data Hold Time
Pin Name

Inpul Loading
Faclor(lu)

0

2
1

CK

Pin Name

Oulpul Driving
Faclor(lu)

0

18

Symbol
Icw

ICW"
Iso

'"0

Typ (ns)'

2.5
2.5
0.7
1.6

• Minimum values lor the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Inputs

Outputs

a

CK

0

i
i

L

L

H

H

C1o-FDS-EO

I

Sheet 112

I

I Page 12-15

3-197

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

FDS

Equivalent Circuit

p-----------_._._----------_._-----------.,
ClK

-L
DA

,

XCLK

)O-----!--o

-L

QA

0---------+---\

CK~ClK
•

L..XCLK

TClK

T
XCLK

DB O>---------i-· •••••••••••• - ••••••••••••••••••••••••••- - 0 OB
DCO>---------i-········································~

OC

DO 0>--------...,....· •••• - •• - • - •• - •••••••• - •••••••••••••••••~

00

Definitions 0 Parameters

---lew

ICWH-

CK

~

I--

180- !e-IHO""

OA-OO
I--Ipd~

OA-OO

C10-FD5-EO

Sheet 212
Page 12-16

3-198

I • CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

_L

Function

FD2

Non-SCAN Power OFF
Cell Symbol
!Up
to

KCL

1.031
1.594

0.034
0.034

PropagaUon Delay Parameter
\dn
fo
KCL
KCL2
CDR2

1.075
1.463

0.028
0.023

0.056
0.039

7
7

Number 01 BC

I

7
Palh

CKtoQ
CK to XQ

'1J=a

CK

XQ

Symbol

Typ (ns)'

Clock Pulse Width
Clock Pause Time

tew
tcw\'

2.5
2.5

Data Setup Time
Data Hold Time

tso
tHO

1.4
1.0

Parameter

Input loading
Factor (Iu)

Pin Name

2
1

0
CK

Pin Name

Output Driving
Factor (Iu)

Q
XQ

36
36

• Minimum values lor the typical operating condition.
The values lor Ihe worst case operating condition are given by !he maximum delay
multiplier.

Function Table
Inputs

Outputs

CK

0

Q

.l.
.l.

H

H

L

L

L

H

CID-FD2-EO

Sheet 112

XQ

I Page 12-17

3-199

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

FD2

Equivalent Circuit
XCKO

CKO

-L

-L

r-----~ ~-----------o

o

xa

T
XCKO

CK

a

TCKO
XCKO

CKO

-L

-L

TCKO

T
XCKO

o-----J>orf>o--

. L---.

XCKO
CKO

Definitions of Parameters
_lew

ICY.\.---

V-

CK

i"'-

I s o - - - .. IHO.....

D

J
_

a,xa

C1D-FDS-EO

Ipd-to

J~

Sheet 212
Page 12-18

3-200

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

FD3

Number 01 BC

Non-SCAN Power DFF with Preset
Cell Symbol

Propagation Delay Parameter
!Up
to
1.069
1.750
1.494

tdn

KCL
0.025
0.025
0.025

to
1.081
1.563
0.569

KCL
0.023
0.023
0.023

KCL2
0.056
0.039
0.039

CDR2
7
7
7

I

8
Path

CKtoQ
CKtoXQ
PRtoQ,XQ

PR

'=6=

CK

aXQ

Clock Pulse Width
Clock Pause Time

tCWl

Typ(ns) •
2.5
2.5

Data SetuD Time
Data Hold Time

tso
tHn

1.4
1.0

Preset Pulse Width
Preset Release Time
Preset Hold Time

tpw
tREM

2.5
0.2
2.4

Parame1er

Input Loading
Factor (Iu)

Pin Name

2
1
2

D

CK
PR

Output Driving
FaClor (Iu)
36
36

Pin Name
Q
XQ

Symbol
lew

tlNH

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Inputs

OulpUts

PR

CK

0

Q

XQ

L

X

X

H

L

H

J.
J.

H

H

L

L

L

H

H

C1o-FD3 EO

Sheet 112

I Page 12-19

3-201

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

FD3

Equivalent Circuit
PRo---~------------~

XCKO

CKO

-L

Q

-L
XQ

00----1

-,-

-,-

CKO

-L

CKO

XCKO

-,-

-,XCKO

CK

XCKO

-L

CKO

o------I>or/)o- CKO

. L---.

XCKO

Definitions of Parameters

f4---

Icw

IcW!. -

CK

~

~Iso- 4-I Ho"

o

J

,

_Ipd_

Q,XQ

JI\.
~IREM-

PR
_IINH-

PR

Q,XQ

C10-FD3-EO

Sheet 2/2
Page 12-20

3-202

~

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nam.

• CGtO • Version

I

Function

FD4

Non-SCAN Power OFF with Clear and Preset
Cell Symbol

Propagation Delay Parameler
tdn
to
KCL
KCL2
CDR2

\Up
to

KCL

1.188
1.756
1.544
1.556

0.030
0.025
0.025
0.030

1.075
1.700
0.913
0.575

0.028
0.023
0.028
0.023

0.056
0.039
0.056
0.039

7
7
7
7

PR

Number 01 BC

J

9
Path

CKtoC
CKto XC
CLtoC. XC
PRto C. XC

-0

0CK--<:

:>-- xo
Parameter

CL

Clock Pulse Width
Clock Pause Time

Input Loading
Factor (Iu)

Pin Name

2
1
2
2

0
CK
CL
PR

Symbol
tew
tCWL

Typ(ns) •

2.5
2.5

Data SetuD Time
Data Hold Time

tso
tHO

1.4
1.0

Preset Pulse Width
Preset Release Time
Preset Hold Time

tpw

2.5
0.2
2.4

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tR.M

tR.M
tlNH

tlNH

2.5
0.6
2.1

Output Driving
Factor (Iu)

Pin Name

36
36

0

xo

• Minimum values lor the typical oparating conation.
The values lor the worst case oparating condition are given by the maximum delay
multiplier.

Function Table
Inputs

Outputs

XO

PR

CL

CK

D

0

L

H

X

X

H

L

H

L

X

X

L

H

H

H

H

L

H

J.
J.

H

H

L

L

H

C10-FD4-EOI

Sheet 112

I Page 12-21

3-203

IDI

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

FD4

Equivalent Circuit

PRo--1-------------,
XCKO

o

.L
Do--~

XQ

XCKO

.L

TCKO

T
XCKO
CL
Definitions of Parameters

CK

o------C>orI)o- CKO

. L-----.

XCKO

CK

o

Q,XQ

PR
CL

PR

CL

Q,XQ
C10-FD4-EO

heet 212
Page 12-22

3-204

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
CenNam.
FunCllon
I

FD5

J • CG10 • Version
I Number 01 BC

Non-SCAN Power DFF with CLEAR
CenSymbol
IUp
10

1.175
1.606
1.475

KCL
0.034
0.034
0.034

PropagaUon Delay Parameler
!dn
10
KCL
CDR2
KCl2
1.069
0.028
0.056
7
1.606 0.023
0.039
7
0.950
0.028
7
0.056

I

8
Palh

CKtoQ
CKtoXQ
CLtoQ, XQ

,va

OK

xc

OL

Icwt

Typ (ns)'
2.5
2.5

Data SetuD Time
Data Hold Time

Iso
IHO

1.4
1.0

Clear Pulse Width
Clear Release Time
Clear Hold Time

ILW

2.5
1.0
2.9

Parameter

Clock Pulse Width
Clock Pause TIme

Pin Nam.

Input loading
Factor (Iu)

D
OK
OL

2
1
2

Pin Name

OUlput Driving
Factor (Iu)
36
36

C

xc

Symbol
lew

tREM
tlNH

• Minimum values lor the typical operating condition.
The values for Ihe worst case operating ooncfrtion are given by !he maximum delay
multiplier.

Function Table
Inputs
OL

Outputs

OK

D

L
H
H

C1Q-FD5 EO

C

XC

X

X

L

H

,I.
,I.

H

H

L

L

L

H

Sheet 112

I

I Page 12-23

3-205

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

FD5

Equivalent Circuit
XCKO

CKO

o

-L

-L
00---1

XO

TCKO

CK

T
XCKO

o---/>orI)o--+ XCKO

. L-.

CKO

CL

Definitions of Parameters
ICWl--

-1<::1<

CK

r-

... ISD .... ... IHD"

o
.... IpeI ....

a,xa
-IIIHIlW

Cl
~ r-lpel

It-

-

a,xa
I---IREM-

Cl

C1o-FD5-EO

If

Sheet 212
Page 12-24

3-206

,

, • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

FJD

Function

Number 01 BC

Non-SCAN Positive edge clocked Power JKFF with Clear
Cell Symbol

PropagaUon Delay Parameler
Idn
10
KCL
KCL2
CDR2

\Up
10

KCL

2.750
2.769
1.500

0.034
0.034
0.034

1.850
1.550
0.806

0.028
0.028
0.028

0.045
0.045
0.045

7
7
7

I

12
Palh

CKtoQ
CKtoXQ
CLto Q, XQ

'=9=0

CK

K

XC

CL

Typ(ns) •

lew
lew><

3.5
3.5

J K SetuD Time
J K Hold Time

Iso

1"0

1.6
0.8

Clear Pulse Width
Clear Release Time
Clear Hold Time

Inpul loading
Faclor(lu)

Pin Name

Symbol

Clock Pulse Width
Clock Pause Time

Parameter

CL

2
1
1
1

J

K
CK
Pin Name

OUlpul Driving
Faclor,'u)

C
XC

36
36

ILW
IR~"
tlNH

2.5
1.6
2.9

• Minimum values lor !he typical operating condition.
The values lor Ihe worsl cese operating oonditlon are given by !he maximum delay
multiplier.

Function Table
Inpuls

aulpUis

CL

CK

J

K

C

XC

L

H

X

X

H

l'
l'
l'
l'

L

L

L
CO

XCO

H
H
H

C10-FJD-EO

H

L

H

L

H

H

L

H

H

H

XCO

L
CO

Sheet 112

I Page 12-25

3-207

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Nlme

FJD

CK

Equivalent Circuit

;p---t1}+--_-I)p-I-r~-l=l~b---nc)----o

CLo-------------+--~------~----~

XQ

b--<~....nc~--_o Q

Definitions of Parameters
tCWH-

-tew

CK

'-.... tso"

f4- tHO""
W

J, K

J~

f4--

tpd'"

a,xa

,

CL

f....---tINHtLW

r-

~ ~tpd_

a,xa
~tREMCL

C1Q-FJD-EO

If

Sheet 212
Page 12-26

3 .... 208

CMOS Channeled Gate A"ays

CG 1DB Series Unit Cell Library

Scan Counter Family

Page

Unit Cell
Name

3-211

SC7

Scan 4-bit Synchronous Binary
Up Counter with Parallel Load

62

3-216

SC8

Scan 4-bit Synchronous Binary
Down Counter with Parallel Load

66

3-221

SC43

Scan 4-bit Synchronous Binary
Up Counter with Asynchronous Clear

59

3-225

SC47

Scan 4-bit Synchronous Binary Up/Down Counter

78

Function

Basic
Cells

l1li

3-209

CG10 Series Unit CsII LIbra?,

3-210

CMOS Channeled Gate Arrays

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

Number oieC

I

SCAN 4-bit Synchronous Binary
Up Counter with Parallel Load

Sel

Cell Symbol

Propagation Delay Parameter
tdn
to
KCL
KCl2
CDR2

!Up

DADBDCDD-

I---OA
P--XOA
I---oe
P--XOB
I---OC
p--XOC
I---OD
P--XOD

CKIHL--<
CIENSIAe--<

Input loadIng
Factor (Iu)

0
CK
IH
L
CI
EN
SI
A.B

1
1
1
1
2
1
1
1

Pin Name

Output Driving
Factor (Iu)

Q
XQ
CO

36
36
36

KCL

2.063
3.613
4.875
1.250

0.034
0.034
0.034
0.034

1.906
3.338
3.269
0.625

0.034
0.034
0.023
0.023

0.084
0.084

7
7

-

-

Path
CK,IHtoQ
CK,IHtoXQ
CK,IHtoCO
Clto CO

Symbol
tew
tcww

Parameter

Clock Pulse Width
Clock Pause Time

I---CO

Pin Name

to

62

Typ(ns)'
4.5
4.5

Data Setup Time
Data Hold Time

tso
tHO

1.3
2.1

Load Setup Time
Load Hold Time

tsL
tH

4.0
2.3

CI SetuD Time
CI Hold Time

tse
tHC

4.5
1.7

EN Setup Time
EN Hold Time

tsE

4.5
1.7

tHE

, Minimum values for the typical operating condition.
The values for the worst case operating condition ara given by the maximum delay
multiplier.

Function Table
Mode

CLOCK

SCAN

OUtputs

Inputs
CI

EN

L

CLK

On

A

e

SI

X

X

L

L

L

X

Oi

H

H

H

S
S
S
S

Di

X

L

L

X

Count Up

X

L

L

X

X

L

L

X
Si

X

L

X

H

X

L

H

X

X

X

H

X

n

H

X

X

X

H

X

L

U

On

NoCotmt

Si

Note: CLK • CK+ IH
n • A~O
C10-SC7 EO

I

Sheet 1/5

I

Page 13-1

3-211

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Ham.

sel

Equivalent Circuit
DA

QA XQA

DB

aB XQB

DC

QCxac

DO

aDxaD

XCKI
CKI

LDI
XLDI
XAI
AI
BI

FFu

XBI

00

SI

EN
CI

co

CK o--~L.
IH o---I-r

) ( ) - - - -... CKI

XCKI

Ao---I

»_---- XAI
X>---AI

B o - - - I X>--t----... BI

»---<~ XBI

C1Q-SC7-EO

Sheet 215
Page 13-2

3-212

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SC7

Equivalent CiraJit (FFu)

XLDI

XBI

CKL

..L

..L

XCKI

Q

-L ..L

XQ

0

'---.....000

CKI

XAI

XCKI

AI

..L

..L ..L

I AI

II

s
CKI

XAI

I

XTG

XBI

o--f---------+--t ,.,_---.

C1Q-SC7-EO

Sheet 3/5
Page 13-3

3-213

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

se7
Function

LJ

L

LOAD

DA
DB

DATA
INPUT

DC
DO

CLOCK

CK+IH

ENABLE
CARRY IN

EN

:1

CI

~

OA
DATA
OUTPUT

OB
OC

00

n

CO

I I

MODE
Inhibit

Cl0-SC7-EO

Load

Count

Inhibit

Sheet 4/5
Page 13-4

3-214

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

"CG10 "Version

Cell Name

SCl
Definitions of Parameters

i) CLOCK MODE
tewH-

-tew
CLOCK

i--tso- - t H O DATA

-tSl

tHL--

L

-tse
CI

---1
I---tSE

EN

C10-SC7-EO

tHe

tHE

'I

---1

Sheet 515
Page 13-5

3-215

I "CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

SGB

Cell Symbol

Propagation Delay Parameler
letn
Ie
KCL
KCL2
CDR2

lop

OAOSOC00-

t--QA
P--XQA
r--CB
p--XCS
t--CC
p--XCC
r--CO
p--XCO

CKIHL--C
SI--C
EN--C
SIAB--C

10

KCL

2.106
2.750
4.006
0.931

0.030
0.025
0.034
0.034

1.988
2.700
5.231
1.419

0.034
0.023
0.023
0.023

0.073

7

-

-

I

Palh

a

CK,lHto
CK,IHtoXQ
CK,lHto BO
BlloBO

Symbol
lew
!CWH

Parameter

Clock Pulse Width
Clock Pause Time

66

Typ (ns)·
4.3
4.3

p-so

Inpul Loading
Faclor(lu)

Pin Name

IDI

Number 01 BC

SCAN 4-bit Synchronous Binaly
Down Counter with Parallel Load

0
CK
IH
L
SI
EN
SI
A.S

1
1
1
1
2
1
1
1

Pin Name

Oulpu! Driving
Factor (Iu)

C

sa

1"0

1.3
2.1

Load Setup Time
Load Hold Time

I Sl
I "L

4.0
2.3

EN SetuD Time
EN Hold Time

ISE

5.1
1.2

Iso

I "E

BI Setup Time
BI Hold Time

36
36
36

xc

Data Setup Time
Data Hold Time

5.1
1.2

158
1"8

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay

multiplier.

Function Table
Mode

X
CLOCK

EN
X

L

CLK

On

A

S

SI

L

S
S
S
S

OJ

L

L

X

Oi

X

L

L

X

Counl Down

X

L

l

X

X

l

l

X

L

L

H

X

H

H

H
SCAN

Oulpuls

Inpu!s
BI

X

H

X

X

X

H

X

n

H

Si

X

X

X

H

X

l

U

X

On

NoCounl

Si

Nole: ClK = CK. IH
n s A-O
C10-SC8-EO

3-216

Sheet 1/5

I

I

Page 13-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

.. CG10 .. Version

Cell Name

SGB
Equivalent Circuit

51

EN
BI

so

CK
IH

o---+-",-

o---+-.r

) 0 - - - -... CKI

A 0----1

)(>-_---- XAI
)O---~AI

XCKI

B 0----1

)C:>-,.....---- BI
)O--~XBI

C10-SC8-EO

Sheet 2/5
Page 13-7

3-217

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

SGB

Equivalent Circun (FFu)

XLDI

CKL

XBI

--L

--L

XCKI
Q

--L --L

XQ

0

XCKI

XAI

XLDI

CKI

XCKI

...---+oxao

AI

--L

--L --L

TAI

T

xs

CKI

T

XAI

T

XBI

XTG

0--1--------+---1

C10-SC8-EO

)C)---i

Sheet 3/5
Page 13-8

3-218

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

" CG10 "Version

Cell Name

SGB
Function

LJ

L

LOAD

DA
DATA
INPUT

DB
DC
DO

CLOCK CK+IH
ENABLE
CARRY IN

EN
BI

IL..JL...JL.r'L

OA
DATA
OUTPUT

OB
OC

00

LJ

BO

I I

MODE
Inhibit

C10-SC8-EO

Load

Count down

Inhibit

Sheet 4/5
Page 13-9

3-219

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

SGB
Definitions of Parameters

i) CLOCK MODE
I cw--oi----1CWH

CLOCK

DATA

L

1

se---+...I;,::H:;,E-I

EN
1 5 B - -....

81

C10-SC8-EO

Sheet 5/5
Page 13-10

3-220

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name
Function

SCAN 4-bit Synchronous Binary Up Counter
with Asynchronous Clear

SC43

Cell Symbol

PropagaUon Delay Parameler
!dn
CDR2
1'0
KCL
KCL2

tup

r-DADSDCDD-

10

KCL

2.669
3.219

0.067
0.067

1.138

0.067

-

-OA
-as
-OC
-aD

CKIHL--<
CIEN51AS--<

0.045
0.045
0.045
0.045
0.045

2.569
3.438
1.631
0.781
2.231

-

-

0.067
0.067
0.067
0.067
0.067

4
4
4
4
4

"Version
I Number of BC

I

59
Path

CKtoQ
CK to CO
CltoQ
CltoCO
CltoCO

-co
-so
Symbol
lew

Parameter

Clock Pulse Widlh
Clock Pause Time
Data Setuo Time
Data Hold Time
load Setuo Time
load Hold Time
CI Setup Time
CI Hold Time
EN Setuo Time
EN Hold Time
Clear Pulse Width
Clear Release Time
Clear Hold Time

CL

Pin Name

Inpul Loading
Faclor(lu)

D
CK,IH
L. CL, 51
EN
A, B. CI

2
1
1
1
2

Pin Name
a

OUlpul Driving
Faclor(lu)
18
18
18

co
SO

tcw~

Iso
IHO
I Sl
I HL
Ise
IHe
I S~
I H~
IlW
t REt.!
t INI-4

Typ (ns)'
3.2
4.6
1.2
1.4
1.9
1.5
2.5
1.1
2.5
1.1
3.9
0.9
3.6

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay

multiplier.

Function Table
Outputs

Inputs
Mode

CLOCK

SCAN

CI

EN

CL

CLK

X

X

L

X

X

X

H

H

H

H

S
S

X

X

H

H

Dn

A

B

51

X

X

X

X

X

L

L

Di

L

L

X

Di
Count Up

L

H

X

L

L

X

H

X

L

L

X

an, sa

No Count

X

L

H

X

H

X

L

L

X

l

X

H

X

H

X

l

l

X

X

X

H

H

X

X

n

H

Si

Hold

X

X

H

H

X

X

l

U

X

Si

Note: ClK
n
C10-SC43 EO

Sheet 1/4

c

CK+ IH

= A- D

I Page 13-11

3-221

" CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

8C43
Equivalent Circuit

DA

OA

XCKI
CKI
LDI

DS

OS

DC

CKI

A

OC

DD

OD

XCKI
CKI
LDI
XLDI
XAI
AI
SI
XSI

XLDI
XAI
AI
SI
XSI

SI

EN
CI

CK

o--rl...

IH

0--+-:'''-

)O----~

XCKI

L~LDI
4»-XLDI

)0-..,...----

XAI

)O----AI

S

)0-..,...---)O--~

SI

XSI

CL~CLO

C10-SC43-EO

Sheet 2/4
Page 13-12

3-222

• CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SC43
Equivalent
XLDI

CKI

-L

-L

Circu~

(FFu)
XBI

XCKI

-L-L
X>----oo

o
XCKI

XLDI

BI

XCKI

XAI

-L

1.-..--_--0 xo

CKI

AI

-L-L

S

CL.

aa

II

I
AI

CKI

XAI

I

XBI

XTGo--t--------+--t

C 1O-SC43-EO

Sheet 3/4
Page 13-13

3-223

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nome

SC43

I
Definition of Parameters

-lew

lewH-

CK

~ll--'
Iso
IHO-

0

II
II

IREM

I---ILW

i--I'NH-

CL ~

'(

1

II

i---ISL- - I H L -

J

II

L

i - - - - I s c - -IHC'"

CI

II
i - - - - I s e - - I He'"

EN

1\

C10-SC43-EO

3-224

Sheet 4/4

II

I Page 13-14

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

FUnction

SC47

I

SCAN 4-bit Synchronous Binary Up/Down Counter
Cell Symbol

Propagation Delay Parameter

tup

DADBDCDD-

.--r--OA
i--- OB
i--- OC
i--- aD

CKIHL---<:
TMENDUSIAB---<:

tdn

10

KCL

10

KCL

2.813
3.825
5.375
1.469

0.067
0.067
0.067
0.067

2.938
5.438
6.781
1.838

0.101
0.045
0.135
0.045

KCL2
0.140

CDR2
4

-

4
-

0.179

.. Version
I Number of BC

78
Path

CKtoQ
CKto CO
Lto Q
DUtoCO

:>-co

-so
Symbol
lew

Parameter

Clock Pulse Width
Clock Pause Time
Data Setup Time
Data Hold Time
EN SetupTime
EN Hold Time
DU Input Setup Time
DU Input Hold Time
Load Pulse Width
Clear Release Time
Clear Hold Time

'--

Pin Name

Input Loading
Factor (Iu)

D
CK, IH, TM, L
EN
DU,A, B
SI

2
1
3
1
2
OUlput Driving
Factor (Iu)
18
18
18

Pin Name
a

so

CO

tCWI-I

Iso
I~o

I SE
I~E

I su
I~u

ILW
t f:lEM
t INH

Typ (ns)'
5.7
6.9
8.4
1.4
4.9
0.5
5.5
0.4
12.0
2.3
9.5

• Minimum values for Ihe typical operating condition.
The values for the worst case operating condition are given by the maximum delay

multiplier.

Function Table
Inpuls
Mode

CLOCK

SCAN

Oulputs

CLK

LO

EN

DU

On

A

B

SI

an, SO

S
S
S

L

H

X

X

L

L

X

No Counl

L

L

H

X

L

L

X

L

L

L

X

L

L

X

Count Down

X

H

X

X

Di

L

L

X

Di

H

L

X

X

X

L

L

X

No Count

H

X

X

X

X

n

H

Si

Hold

H

X

H

X

X

L

U

X

Si

Note: CLK = CK+ IH
LO=TMoL
n = A~ D
C1D-SC47-EO

Sheet 1/4

I Page 13-15

3-225

.. CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SC47

Ao--{)o~~-

LJ»-AI

Equivalent Circuit
f'"

eo--{)o

r---

l..-'
DU

~

~

EN

[ ~ ::~I
co

f'"

~

~

XAI

l..-'

DA D--=::: r - - -

==

510--::::

OA

FFu

=~:n

~~
_

as

FFu

=~Jl

~~~
_

ac

FFu

=~Jl

1"\

DDD--=:::-

-==
_

aD

FFu

,./

_1"\

==

-'--=:;::

~sa

,./

TM~ La
L

C10-SC47-EO

Sheet 2/4
Page 13-16

3-226

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

.. CG10 .. Version

Cell Name

SC47
Symbol

o

0

LO
CKO
XCKO
S

XAI
AI
81
XBI
TGO

FFu

00
XOo

Equivalent Circuit

xao

(FFu)

0

ao
CKO
BI

CKO

-L
DO
LO

s

XCKO

IDI

BI
AI

CKO

-L

XAI

TX81
TGOo--+------1-~

o

O>---..-~~---

XOO

~-----------DO

C10-SC47-EO

Sheet 3/4
Page 13-17

3-227

" CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SC47
Definition of Parameters

tew

tCWH

CK

II
tHO

II
II

D

tREM

tlW

II

L

tSE

tHE

ll~

EN

tsu

tHU

DU

II

C10-SC47-EO

Sheet 4/4
Page 13-18

3-228

CG10 Series Unit CeU Library

CMOS Channeled Gate Arnlys

Non-scan Counter Family

Page

Unit Cell
Name

Function

Basic
Cells

3-231

C11

Non-scan Flip-flop for Counter

11

3-233

C41

Non-scan 4-bit Binary Asynchronous Counter

24

3-236

C42

Non-scan 4-bit Binary Synchronous Counter

32

3-239

C43

Non-scan 4-bit Binary Synchronous Up Counter

48

3-243

C45

Non-scan 4-bit Binary Synchronous Up Counter

48

3-247

C47

Non-scan 4-bit Binary Synchronous Up/Down Counter

68

3-229

CG10 Series Unit Ceo Ubrary

3-230

CMOS Channeled Gate A"ays

I .. CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

Number of BC

I

Non-SCAN Flip-Flop for Counter

C11

Cell Symbol

Propagation Delay Parameter

Idn

!Up

10
1.188
1.581
1.638

;----

DL-

KCL
0.067
0.067
0.067

10
1.094
1.856
1.081

KCL

KCL2

11
Path

CDR2

CKtoO
CKto XO
CL toO,XO

0.056
0.056
0.056

-0

CK-

>--xo

TG-

Symbol
lew

Parameter

CL

Clock Pulse Width
Clock Pause Time

tCWI-I

Inpul Loading
Faclor (Iu)

L
TG
CL
D,CK

2
2
2
1

Pin Name

OulPUI Driving
FaClor (Iu)
18
18

0
XO

I, "

2.5
0.7
0.4

IlW

Clear Pulse Width
Clear Release Time
Clear Hold Time
Pin Name

TVp (ns)'
2.5
2.7

t REM

Load Setup Time
Load Hold Time

CK
CK

I Sl
I""

1.5
0.4

Data Setup Time
Data Hold Time

(CK)
CK

Iso

1.6
0.4

TG SetuD Time
TG Hold Time

(CK)
CK

1ST
I HT

'"0

1.9
0.0

• Minimum values for the typical operating condition.
Th~ values for the worst case operating condition are given by the maximum delay

mulliplier.

Function Table
L

D

TG

X

X

X

L

X

L

H

H

X

H

H

H

L

X

H

L

X

L

H

l'
l'
l'

l

X

H

H

l'

C1D-C11 EO

I

CL

Sheet 1/2

CK

0(00)

L
0(00)

--

0(00)

I

Page 14-1

3-231

• CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

e11

Equivalent Circuit
CL

XLO

..l
)0------00

o

Xo

T

T

xeo

XCKO
CL

TGo-~f-H

CK~CKO
V

~XCKO

Definition of Parameters
-lew

ICWH---

CK

~
I---ILW

I RE"-'

'(

CL

I
-I,NH

CL
ISL

IHL-

Iso

IHO-

1

L

o
1ST

TG
C10-C11-EO

IHr-

--'

Sheet 2/2
Page 14-2

3-232

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

I

Function

C41

Cell Symbol

Propagation Delay Parameter
tdn
1'0
KCL
KCL2
COA2

tup

-

I--OA

to

KCL

1.250
2.294
3.206
4.125

0.059
0.059
0.059
0.059

-

1--08

-

1.163
2.050
2.969
3.875
2.619

0.056
0.056
0.056
0.056
0.056

-

Number of BC

I

Non-SCAN 4-bit Binary Asynchronous Counter

24
Path

-

CKtoQA
CKto QB
CKtoQC
CKto QD
CLtoQ

Symbol

Typ (ns)'

-

-

I--OC

1--00
CK-

Parameter

CL

Clock Pulse Width
Clock Pause Time

tew

Clear Pulse Width
Clear Release Time
Clear Hold Time

tLW
tREM

2.7
2.9

tCWI-l

2.5
1.4
4.2

tllll,",

Input Loading
Factor (Iu)

Pin Name

CK
CL

1
1

Pin Name

Output Driving
Factor (Iu)

0

18

• Minimum values for the typical operating condition.
The values for the worst case operating oondition are given by the maximum delay
multiplier.

Function Table
Inputs

Output

CL

CK

Q

H

t

Count up

L

X

L

C1o-C41 EO

Sheet 1/3

I

I

Page 14-3

3-233

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

C41
Equivalent Circuit

as

OA

OC

00

CKO
FTO

XCKO

CLoo-----~~------------~------------~------------~

CK~CKO

~XCKO

V

FTO (Flip-Flop for Counter) (not Uint Cell )

e

Symbol

CKO

FTO

XCKO

Function Table

o

ao
xao

CLO

CKO

a

L

x
i

Or>--l

H

L

CLO

a
ao

-,XCKO

XCKO

CKO

CKO

--L

--L

-,-

-,-

CKO

XCKO

CLO

xao

C10-C41-EO

Sheet 2/3
Page 14-4

3-234

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

.. CG10 .. Version

Cell Name

C41
Definition of Parameters

CK

CL

C10-C41-EO

Sheet 3/3
Page 14-5

3-235

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

C42

• Version

I

Function

I

Non-SCAN 4-bit Binary Synchronous Counter
Cell Symbol

Propagation Delay Parameler
Idn

!Up
to

KCL

to

KCL

KCL2

COR2

1.988

0.059

1.463
2.100

0.051
0.051

0.067
0.067

4
4

-

-

Number of BC

32
Path

CKtoQ
CLtoQ

;--QA
-OB
-OC

-00

CK-

Parameter

Clock Pulse Width
Clock Pause Time

CL

Clock Pulse Width
Clear Release Time
Clear Hold Time

2.7
2.9

tCWH

2.5
1.4
4.2

tlW
t REM
tiN"

Input Loading
Factor (Iu)

Pin Name

CL
CK

1
1

Pin Name

Output Driving
Factor (Iu)

0

18

IDI

Typ (ns)'

Symbol
tew

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Inputs
CK

Q

H

i

Count up

L

X

C10-C42 EO

3-236

Outputs

CL

L

Sheet 1/3

I

I

Page 14-6

• CG10 " Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

C42
Equivalent Circuit

OC

08

OA

00

CKO
XCKO

CLOo---------~--_+--------~----~--~----~----r_--t_--~

'" r-:--

XCKO

CK~ CKO

CL

o-----{>o--{>o- CLO

FT2 (Flip-Flop for Counter) (not Unit Cell)
Symbol

Function Table

o

CKO

Inputs

CLO

XTG

Outputs

CKO

0(00 )

XCKO
XTG

QO

L

X

X

L

H

H

On-l

H

L

l'
l'

a;:;::;

CLO

C1D-C42-EO

Sheet 2/3
Page 14-7

3-237

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

C42
Equivalent Circuit of FT2
CLO

)0------00

/-T-+--;

)O-----o-

CLO

L~LO

-

C10-C43-EO

L-..{>o--

XLO

CK~XCKO

-

L-..{>o--

CKO

Sheet 2/4
Page14-10

3-240

• CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

C43
FT3 (Flip-Flop for Counter) (not Unit Cell)
Function Table

Symbol
0

LO

LO

0

XTGO CLO

CK

0

o.

XLO
CKO
XCKO
XTGO

0(00)

X

X

X

H

X

L

H

H

X

L

t
t
t
t

H

H

L

X

L

L

X

H

L

L

X

L

L

L
0(00)

0(00)

CLO

Eguivalent Circuit of FT3
CLO

o

)0---00

CKO

XTGO

T

XCKO

o---1f-H

C10-C43-EO

Sheet 3/4
Page14-11

3-241

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I

C43

I
Defin~ion

of Parameters

ICWH_

!---Icw

CK

I\--ll-'
Iso

IHo_

'I

0

II
II

t REM'

!---ILW

I--I'NH_

CL ~

'I

II
_ I S L _ f4-IHL....

'I

L

I--Isc

CI

IDI

'I
J

3-242

,
II

1--18E

C10 C43 EO

IHC

J

EN

I

Sheet 4/4

II

IHE

,
~

I

I

Page14-12

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

C45

Number 01 BC

I

Non-SCAN 4-bit Binary Synchronous Up Counter
Cell Symbol
\Up

r---OA
-OB
-OC
-OD

DADBDCDDL--<
CKENCI-

10

KCL

1.669
3.169
1.194

0.059
0.072
0.072

Propagation Delay Para meIer
Idn
10
KCL
KCL2
CDR2
1.169
0.051
4
0.073
1.763
0.051
0.051
0.850

-

48
Path

CKtoQ
CKtoCO
CltoCO

-co
Parameter

CL

Pin Name

Input Loading

D
L,EN
CK,CL
CI

1
1
1
2

Pin Name

OUlput Driving
Faclor(lu)

0
CO

18
18

Clock Pulse Width
Clock Pause Time
Data SetuD Time
Data Hold Time
Load SetuD Time
Load Hold Time
CI Setup Time
CI Hold Time
EN SetupTime
EN Hold Time
Clear SetuD Time
Clear Hold Time

FaClor (Iu)

Symbol
Icw

Typ (ns)·
2.5
2.9
2.4
1.4
3.2
1.4
4.2
1.2
4.2
1.2
2.4
1.3

ICWH
Iso
IHO
I Sl
IHl
Isc
IHC
I SE
I HE
ISR
I HR

the typical operating condition.
The values for the worst case operating condition are given by the maximum delay

* Minimum values for

multiplier.
Function Table
Outputs

Inputs
CL

L

D

EN

CI

CK

Q

L

X

X

X

X

H

L

H

X

X

H

H

L

L

X

X

't
't
't
X

No Counting

L

L

H

H

X

X

L

H

H

X

L

X

X

No Counting

H

H

X

H

H

't

Count up

Note: The CO output produces a high level
output data when the counter overflows.

C1Q-C45-EO

Sheet 114

I

I

Page14-13

3-243

"CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

C45
Equivalent

Circu~

DA

DB

OA

OB

DC

OC

DO

00

CI

EN

IDII
CL

L

C10-C4S-EO

0----[>0---

CLO

o----{)o---r-

- Lt>o--

LO
XLO

CK

o----{)o---r-

- Lt>o--

XCKO
CKO

Sheel2/4
Page14-14

3-244

• CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

C45
FTl (Flil>-Flop for Counter) (not Unit Cell)
Function Table

Symbol
0

0

XTGO

CLO

L

X

X

H

H

H

X

L

LO

a

LO
XLO

00

CKO

H

L

X

L

L

X

H

L

L

X

L

L

XCKO
XTGO

CK

i
i
i
i
i

0(00)
L

H
L

0(00)

--

0(00)

CLO

Eguivalent Circuit of FT3

CLO
XLO

-.L
Yl---Oo

0

10--.-......--1

CKO

)()-_+--O 00

I
XCKO

XTGO o--H~-I

Cl0-C45-EO

Sheet 314
Pagel4-15

3-245

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I

C45

Definition of Parameters

ICWH_

I---Icw

CK
f-Iso" i---IHO-

,

D

~If

1\
!--ISR.... _ I H R _

CL
_

ISL

IHL_

L

I--Isc

lHe-

I--ISE

IHE-

CI

EN

C10-C45-EO

3-246

,

j

Sheet 4/4

1 Page14-16

I "CG10 • Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

C47

I

Non-SCAN 4-bit Binary Synchronous Up/Down Counter
Cell Symbol

Propagation Delay Parameter

!dn

tup

r---DADSDC00L--<
CKEN--<
DU-

KCL

to
2.494
3.381
3.131
1.544

-aA

-as

0.067
0.046
0.067
0.046

to
2.244
3.825
3.463
1.881

KCL

KCL2

CDR2

0.090
0.045
0.090
0.045

0.140

4

0.140

4

-

-

68
Path

CKtoO
CKto CO
lIoO
DUto CO

-ac
-aD

::>-- co

-

Parameter

Clock Pulse Width
Clock Pause Time

Input Loading
Factor (Iu)

Pin Name

1
2
1
1
3

0
L
DU
CK

EN

Pin Name

Output Driving
Factor (Iu)

a
CO

18
18

Symbol
tew
tCWI-l

Typ (ns)'
3.5
5.6

Data SetuD Time
Data Hold Time

tso
tHO

0.5
1.2

D 'Setuo Time
DU Hold Time

t su
tHU

3.4
0.5

EN SetuD Time
EN Hold Time

t SE
tHE

3.2
0.8

Load Release Time
Load Hold Time

t REM
t INH

1.5
7.0

tLW

2.9

Load Pulse Width
• Minimum values for the typical operating condition.

The values for the worst ease operating condition are given by the maximum delay

mUltiplier.

Function Table
Inputs

0

Outputs

L

EN

DU

CK

0

H

L

X

X

X

H

L

L

X

X

X

L

X

H

H

X

No Counting

X

H

L

L

X

H

L

H

i
i
i

Count Up
Count Down

Note: The CO output produces a low level output
pulse when the counter overflows or underflows.

C10 C47

EO

Sheet 1/4

I Page14-17

3-247

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name

C47
Equivalent Circuit

.---

r-t>

»-

"'"

..

- - - 0 OA

OAe-LOCKOXCKO -C

FT7

~

~

~
I

CK

co

....

OU

EN

....

~XCKO
CKO

Lo-{>o-LO

CKOXCKO -C

~

---0
FT7

~
- - - 0 OC

DC 0-LOCKOXCKO -C

FT7

~

....

....

- - - 0 00

DOe-LOCKOXCKO -C

"""--

os

LO-

FT7

-

"'"

C10-C47-EO

Sheel2/4
Page14-18

3-248

• CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

C47
FT7 (Flip-Flop for Counter) (not Unit Cell)

00

LO

Function Table
InpulS

0

OutpulS

LO

0

TGO

CKO

QO(O)

H

H

X

L

L

X

x
x

H

H

L

H

L

X

L

On-1

a;;:;

a;;:;

On-1

0(00)

FT7

CKO
XCKO
TGO

00
XOO

L

X

H

;
;

Equivalent Circuit of FT7

XOO
0

CO

T
XCKO

XCKO

-L

T

CKO

CKO

-L

XDO
LO

DO
LO

CKO

XCKO

mo

D~DO
v

C10-C47-EO

~XDO

Sheel3/4

Page14-19

3-249

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 "Version

Cell Name

C47
Definition of Parameters

--to_-tCWH
CK

o

L

II
tSE

tHE

II

EN

tsu

tHU

DU

Ii

C10-C47-EO

Sheet 4/4
Page14-20

3-250

CMOS Channeled Gate Arrays

CGto Series Unit Cell LibraI}'

Adder Family
UnHCeIl

Basic
Cells

Page

Name

3-253

A1A

1-bil HaH Adder

5

3-254

A1N

1-bil Full Adder

8

Function

3-255

A2N

2-bil Full Adder

16

3-257

A4H

4-bil Binary Full Adder with Fast Carry

48

3-251

0010 Series Unit CeH Library

3-252

CMOS Channeled Gate Arrays

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell N.m.

I • CG10

"Version
Number 01 Be

Function

A1A

1-bit Half Adder
Cell Symbol

Prop'gaUon Delay P...m.'er
!dn
10
KCL
KCL2
CDR2

IIJp

10

KCL

0.763
0.681
0.700
0.794

0.034
0.034
0.034
0.034

0.900
0.913
0.781
0.719

15
Path

AloS
610S
AloCO
610CO

0.023
0.023
0.023
0.023

,=[}=oo
A

S

Symbol

Parameter

Pin Name

Inpul Loading
Faclor(lu)

A
B

2
2

Pin Nam.

Oulpul Driving
Faclor(lu)

CO
S

36
36

• Minimum values lor the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

Function Table

Equivalenl Circuil

A

B

CO

S

L

L

L

L

L

H

L

H

H

L

L

H

H

H

H

L

C1D-A1A-EO

Typ (ns)'

Sheel1/1

A
B

th) r:=~
I

Page 15-1

3-253

• CG10 'Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

A1N

I

Cell Symbol

Propagation Delay Parameter

Idn

!Up

10

KCL

to

KCL

1.650
0.781
1.863
0.638

0.067
0.067
0.067
0.067

1.969
0.844
1.488
0.731

0.045
0.045
0.045
0.045

KCL2

Number of BC

I

1-bit Full Adder

8
Path

CDR2

A.810S
ClloS
A. 810 CO
ClloCO

'=Q=OO
A

S

CI

Symbol

Parameter

Pin Name

Input Loading
Faclor (Iu)

A
B
CI

3
3
3

Pin Name

OUlput Driving
Factor (Iu)

CO
S

18
18

• Minimum values for the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

Equivalent Circuit

Function Table

CI

S

CO

L

L

L

L

L

H

L

L

H

L

L

H

L

H

L

H

H

L

L

H

L

L

H

H

L

H

L

H

L

H

L

H

H

L

H

H

H

H

H

H

C10-A1N EO

3-254

B

A
B

Outputs

Inputs
A

Typ (ns)'

Sheel1/1

,,......

,......

j]

S

,v

CI

~~oo
V

I

Page 15-2

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

Number 01 BC

Function

A2N

2-bit Full Adder
Cell 5ymbol
IUp

82A281A1-

f--

CO

f--

S2
51

r--

1.

10

KCL

1.781
1.713
0.988
0.919
1.744
1.856
1.856
0.738
1.763
1.944
1.694
1.944
1.725

0.122
0.122
0.122
0.122
0.122
0.093
0.093
0.093
0.093
0.093
0.093
0.093
0.093

I

Propagation Delay Parameler
Idn
1"0
KCL
KCL2
CDR2

1.756
1.794
0.850
0.850
1.613
1.719
1.719
0.744
1.719
1.844
1.756
1.844
1.575

0.079
0.079
0.051
0.051
0.079
0.079
0.079
0.079
0.079
0.079
0.079
0.079
0.079

Pa'"

-

-

0.067
0.067

-

A1 to CO
B1 to CO
A2toCO
B2toCO
CltoCO
Al to Sl
Bl to Sl
CI to Sl
Al to S2
A2 to S2
Bl to S2
82 to S2
Clto S2

4
4

-

---

Typ (ns)·

5ymbol

Parameter

16

Inpul Loading
Faclor (Iu)

Pin Name

A.B
CI

2
2

Pin Name

Oulput Driving
Faclor(lu)

5
CO

14
14

• Minimum values lor Ihe typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Oulputs

Inputs
A1
L
H
L
H
L

81
L
L
H
H
L

H
L
H
L
H
L
H
L
H
L
H

L
H
H
L
L
H
H
L
L
H
H

Cl0 A2N EO I

A2
L
L
L
L
H
H

H
H
L
L
L
L
H
H
H
H

82
L
L
L

51
L
H
H

L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L

Sheet 1/2

I

CI = L
52
L
L
L
H

H
H
H
L
H
H
H
L
L
L
L
H

CO
L
L
L

51
H
L
L

CI = H
52
L
H
H

L
L
L
L
H
L
L
L
H
H
H
H
H

H
H
L
L
H
H
L
L
H
H
L
L
H

H
H
L
L
L
H
L
L
L
L
H
H
H

CO
L
L

L
L
L
H
H
H
L
H
H
H
H
H
H
H

I

Page 15-3

3-255

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

" CG10 "Version

Cell Name

A2N

Equivalent Circuit

~

________________+-____-+J>-------oCO

A20-__- - l

B20--......-+7
0-----052

Alo-__- - l

Bl 0---4--+:,'
0-----051

Cl

0------1-~~-~--------~~

...
C10-A2N-EO

She' 212
Page 15-4

3-256

I "CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

A4H

Propagation Delay Parameter

tup

Idn

10

84A483A382A281AI-

r--

r--

CO
54

r--

53

I - - 52

r--

51

J
Inpul Loading
Faclor (Iu)

Pin Name

A
8
CI

2
2
2

10

KCL

KCL2

CO
51.53.54
52

Path

CDR2

0.738
1.656
1.894
1.963
1.794

0.093
0.122
0.122
0.122
0.067

1.019
1.919
1.863
2.213
2.006

0.079
0.079
0.079
0.079
0.045

-

Clto Sl
ClIo S2
ClIo S3
Clto S4
CltoCO

2.381
1.981
2.138
2.344
2.063

0.093
0.122
0.122
0.122
0.067

2.119
1.925
2.406
2.450
2.363

0.079
0.079
0.079
0.079
0.045

-

A1.
A1.
A1.
A1.
A1.

B1
B1
B1
B1
B1

to
to
to
to
to

Sl
S2
S3
S4
CO

1.931
2.288
2.338
2.419

0.122
0.122
0.122
0.067

2.106
2.250
2.531
2.394

0.079
0.079
0.079
0.045

A2.
A2.
A2.
A2.

B2 to
B2to
B2 to
B2 to

S2
S3
S4
CO

1.756
2.400
2.375

0.122
0.122
0.067

1.781
2.525
2.388

0.079
0.079
0.045

-

1.813
2.288

0.093
0.067

1.881
2.194

0.051
0.045

0.067

Function Table

-

A3. B3 to S3
A3. B3 to S4
A3. B3to CO

-

-

4

A4. B4to S4
A4. B410 CO

Nete;
Inputs

Al
Bl
- -A3 - - - 83-

L
H
H

L

L

H
H
L

L
L

L

H
H
H
H

L
L

L

C10 A4H-EO

L
L
L
L
H
H
H
H

L

L
L
H
H
H
H
H
H
H
H

=L

51
S2
C2
SI
- -S3 - - -$1,- - - 60 - - - - 53

L

L

H
H
L
L
H
H
L
L
H
H

and S2 and the value of the internal
cany C2.
The values at C2, A3. 83, A4 and B4

82

L

L

Inpul conditions al AI, A2, 81, 82 and

CI =H
-----Cz":C----- ------ci:'f(----

A2

- - 1.4 - - -84 - -

L
L

H

Outputs
CI

L
H

H
L
H
L
H
L
H
L
H

48

OulPUI Driving
FaClor (Iu)
18
14
18

Pin Name

L

I

4-bit Binary Full Adder with Fast Carry
Cell 5ymbol

H

"Version
I Number of BC

L
L
H
H
L

L
H
H

L
L
H
H

L

L
L

L
H
H
H
H

L
H
H
H
L
L
L

L
H

L

H

L
L
L
L
L

L

L
H

L
L
L
H
H
H
H
H

L
H
H

L
L
H
H
L
L
H
H

L
L
H

S2

C2

L
H
H
H
H
L

L

- - -S4 - - -co -

L
L
H
L
L
L
L
H
H
H

CI are used to determine outputs 51

are then used to determine outputs

S3, S4 and CO.

L
L
L
L
H
H
H
L
H
H
H
H
H
H
H

Sheet 1/2

I

Page 15-5

3-257

I "CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

1

A4H

I

V-

~)-.

-

u--t:7

'-~
~

83o-rrDI

A3 v -

ft>,
~

A2v-

CI

C10-A4H-EO

3-258

1

Sheet

;~
'-f:C~
r-V
'"

t1>
2121

r---

FU rt--bJ

~

~

81o-rrDI

A10

"
-U rt--tJ

H~
'"

82o-rrDI

co

P-

~

'-~

,--r-'---

r"1./

r--

.--l..I

~O-~
A4

"Version

Equivalent Circuit

~

"

rr~

rr
"

S3

S2

"
V'

~

'1...I~S1

Jr[

I

Page 15-6

CG10 Series Unit Cell Ubrary

CMOS Channeled Gate Arrays

Data Latch Family

Un" Cell
Page

Function

Name

Basic
Cells

3-261

YL2

1-bit Data Latch with TM

5

3-263

YL4

4-bit Data Latch with TM

14

3-265

LTK

Data Latch

4

3-267

LTL

1-bit Data Latch with Clear

5

3-269

LTM

4-bit Data Latch with Clear

16

3-272

LT1

S-R Latch with Clear

3-274

LT4

4-bit Data Latch

4
14

3-259

CG10 Series Unit Cell library

3-260

CMOS Channeled Gate Arrays

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

YL2

Function

I • CG10 "Version
I Number of BC

1-bit Data Latch with TM
Cell Symbol
IUP

to

KCL

1.706
0.725

0.034
0.034

Propagallon Delay Parameter
tdn
10
KCL
KCL2
CDR2

1.756
0.800

1

5

Path

CK,lHto 0

0.023
0.023

0100

'D'

CK
IH
TM

Parameter

Pin Name

Input loading
Factor (Iu)

D
CK
IH
TM

2
1
1
1

Pin Name

Output Driving
Factor (Iu)

a

36

Symbol

Typ (ns)·

Clock Pulse width

tew

4.3

Data SetuD Time
Data Hold Time

Iso

2.0
1.6

t"O

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Note:
The TM tenninal must be kept LOW during the SCAN Mode.
Function Table
Input
TM

Output

IH

CK

0

a

L

x

X

0

D

H

H

X

X

00

H

X

H

X

00

H

L

L

0

D

C10-YL2 EO

Sheet 1/2

Mode
SCAN

LATCH

I

I

Page 16-1

3-261

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

YL2

Equivalent Circu~
X>------------------~Q

o 0--------1

T

XCKI

-L

XCKI

TCKI

J~~---.: ::~I
Definitions of Parameters
-tew - -

CK
tso

tHO

D
4-t .. _
Q

C1D-YL2-EO

Sheet 2/2
Page 16-2

3-262

I • CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number of BC

Function

4-bit Data Latch with TM

YL4

Cell Symbol

Propagation Delay Parameter

tdn

tup

to

KCL

to

KCL

2.081
0.688

0.034
0.034

2.144
0.806

0.023
0.023

KCL2

COR2

I

14
Path

CK,lHto
DtoO

a

-01
-02

01 020304-

~03

-04

CK --C
IHTM--C
Parameter

Symbol

Typ (ns)'

Clock Pulse width (CK)

tew

4.5

Data Setuo Time (0)
Data Hold Time D

tso

1.2
2.5

t"D

Input Loading
Factor (Iu)

Pin Name

0
CK
IH
TM

2
1
1
1

Pin Name

Output Driving
Factor (Iu)

Q

36
• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Note:
The TM terminal must be kept LOW during the SCAN Mode.
Function Table
Input

Output
Mode

TM

IH

CK

On

On

L

X

X

0

0

H

H

X

X

Ono

H

X

H

X

Ono

H

L

L

0

0

SCAN

LATCH

n=I-4

C10 YL4 EO

I

Sheet 1/2

I Page 16-3
3-263

.. CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

YL4

Equivalent Circu~
~-----+-------------oOI

01

O-----------__H
TXCKI

XCKI

-.L
TCKI

,

02

.-----------------------------...,.,...-------------<0
0-----------.....,...

03

0-----------.....,...

02

• _____________________________ 4

..",...-------------<0

03

04 0>---------.-'------ - ----- - --- ----- -- -------'..--------004

J~ ~-----...,:~ ::~I
Definitions of Parameters

I--- lew

--Ii

CK
Iso

IHO

o

J

f.-

lpel - -

Q

C10-YL4-EO

Sheet 212
Page 16-4

3-264

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 "Version
Number 01 BC

Function

LTK

I

Data Latch
Cen Symbol

Propagation Delay Parameler
IeIn
10
KCL
KCL2
CDR2

IUp

10

KCL

0.644
0.906
1.094
1.325

0.067
0.067
0.067
0.067

0.719
1.019
1.138
1.463

4
Pa!h

0.045
0.045
0.045
0.045

DtoO
DtoXa
GtoO
GtoXa

:Da

XQ

Parameter

Pin Name

Inpul loading
Faclor(lu)

D

2
1

G

Pin Name

Oulpul Driving
Faclor(lu)

Q
XQ

18
18

Symbol

Typ (ns)·

G Inout Pulse Width

IGW

2.5

Data SetuD Time
Data Hold Time

Iso

1.0
1.5

I~D

• Minimum values lor Ihe Iypical operating condition.
The values lor !he worsl case operaling condilion are given by lIIe maximum delay
mull/pller.

Function Table
OulpulS

In puIS
D

G

Q

XC

X

H

CD

XCD

H

L

H

L

L

L

L

H

C 1O-LTK-EO I

Sheet 112

I

Page 16-5

3-265

..

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

LTK

Equivalent

Circu~

....----------1

)0----0 0

)0--'---1):>--_--0(>----0

0

xo

xco

Txco

-L

Tco

G~

:

:~o

Definitions of Parameters
(Case1)
G

D

a,XQ
(Case2)

o..-tso

-

~ tHO ....

'I

G

D
tpd

a,xa

C10-LTK-EO

Sheet 2/2
Page 1/1-6

3-266

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

LTL

"Version
I Number

I

1-bit Data Latch with Clear
Cell Symbol

Propagation Delay Parameter

tup

Idn

to

KCL

to

KCL

0.869
0.738
0.950
1.225
1.388

0.067
0.067
0.067
0.067
0.067

0.531
0.763
1.069
1.200
1.569

0.051
0.051
0.051
0.051
0.051

KCL2

0' BC

5
Path

CDR2

CLloQ, XQ
DloQ
DloXQ
GloQ
GloXQ

r---- a

DG--C

r

P-- xo
Parameter
G InDut Pulse Width

Pin Name

Input Loading
Factor (Iu)

0
G
CL

2
1
1

Output Driving
Factor (Iu)
18
18

Pin Name

a

xo

Symbol
tGW

Typ (ns)'
2.5

Data SetuD Time
Data Hold Time

tso
tHO

0.9
0.4

Clear Pulse Width

tew

2.5

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table

Inputs

Outputs

CL

0

G

a

XQ

L

X

H

L

H

a.

xOo

H

X

H

H

H

L

H

L

H

L

L

L

H

C10 LTL

EO

Sheet 1/2

l

Page 16-7

3-267

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

LTL
Equivalent Circuit

CLo--------------------,
...---------l
P---<~-i

o 0--------1

)0----0

c

)C>--"""'--i ) ( > - - - - 0 xc

XGO

IXGO

-L
I GO

Definitions of Parameters
(Case1)

taw

--~I

G

D

a,xa
(Case2)
G

J
-

tHO""

tso

D
t..,

a,xa

1\

G·
Note·: G input must be high level at the time this latch is cleared.

C1D-LTL-EO

Sheet 2/2
Page 16-8

3-268

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 .. Version
Number of Be

Function

LTM

I

4-bit Data Latch with Clear
Cell Symbol

Propagation Delay Parameler
Idn
CDR2
10
KCL
KCl2

lup

DADBDC-

00G --C

r

10

KCL

0.963
0.763
1.000
1.631
1.706

0.067
0.067
0.067
0.067
0.067

0.606
0.806
1.119
1.531
1.969

16
Palll

0.045
0.045
0.045
0.045
0.045

CL 10 P, N
010 P
010 N
GloP
GloN

f--PA
p--NA
f - - PB
p - - NB
I - - PC
p - - NC
f - - PO
NO

p--

Parameter

G Input Pulse Width

Pin Name

Input Loading
Factor (Iu)

D

2

Typ (ns)·

Symbol
IGW

2.5

Clear Pulse Width

ILW

2.5

Data Setup Time
Data Hold Time

Iso
1"0

1.0
1.5

1
4

G
CL

Pin Name

Output Driving
Factor (Iu)

P
N

18
18

• Minimum values for Ihe typical operating condition.
The values for lIIe worsl case operaling condilion are given by lIIe maximum delay
multiplier.

Funclion Table
Inputs

Outputs

CL

0

G

P

N

L

X

H

L

H

H

X

H

Po

No

H

H

L

H

L

H

L

L

L

H

C10 LTM-EO

Sheel113

I

I

Page 16-9

3-269

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

.. CG10 .. Version

Cell Name

LTM
Equivalent Circuit

CLo--~~-------,

PA

DA

0---+-----1

IXGO

p---4i---i)C>---,---;

)C>--~-o

NA

XGO

-L
I GO
~PB

DB o---+:
DC

DO

:---0

o---H

:---0

NC

~PD

C>------i

C1Q-LTM-EO

NB

~PC

:---0

NO

Sheet 21
Page 16-10

3-270

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

LTM
Definitions of Parameters
(Case1)

---'\1
G

o
lpO

P,N

(Case2)

G
~ISO- . . IHO-

I{

o
_Ipd_

P,N

(CaSe3)

~llW-

CL

"G

i--

Ipd ...

P,N
NOle" : G inpul must be high level al the time this latch is cleared.

C10-LTM-EO

Sheet 3/3
Page 16-11

3-271

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name

Function

LT1

I " CG10 .. Version
. I Number of BC

S-R Latch with CLEAR
Cell Symbol
tup
to

KCL

1.100
0.975
0.900

0.067
0.067
0.067

Propagation Delay Parameter
teln
fO
KCL
KCL2
CDR2

0.550
0.650
0.575

0.045
0.045
0.045

I

4
Path

SIOO, XO
RIOO, XO
CLio 0, xo

'=0=0
R

XO

Parameter

CL

Symbol

Typ (n5)'

Sel Pulse Width

tsw

2.5

Resel Pulse Width

tRW

2.5

Clear Pulse Width

tlW

2.5

Input loading
Faclor(lu)

Pin Name

1
1
1

S

R
CL

Oulpul Driving
Factor (Iu)

Pin Name

a

18
18

xo

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Inputs

S

R

a

L

H

H

L

H

H

H

H

00

XOo

H

H

L

L

H

H

L

H

H

L

H

L

L

Inhibited

C1o-LT1 EO

3-272

Outputs

CL

I

Sheet 1/2

XO

I

I Page 16-12

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

LT1
Equivalent Circuit
S

0---------1

»---------1r-----D::>-------<>

R

xc

C

CL

Definitions of Parameters
-Isw

--

S
..... I .......

Q,XQ

-IRW

--

R
..... I .......

Q,XQ

,

I4--ILW

CL

f4-

--

Ipd .....

Q,XQ

C10-LT1-EO

Sheet 2/2
Page 16-13

3-273

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

LT4

I .. CG10 .. Version
Number 01 BC

Function

4-bit Data Latch
Cen Symbol

Propagation Delay Parameler
Idn
KCL
KCL2
COR2
10

lup

I--

OAOB-

p--

r---

oc-

10

KCL

1.563
1.563
0.656
0.875

0.067
0.067
0.067
0.067

1.425
1.906
0.738
1.000

0.045
0.045
0.045
0.045

I

14
Path

GtoP
GtoN
Dto P
Dto N

PA
NA
PB
NB

p---p---- NC

00-

I-- pc

G-(

I--

po

~NO

Parameter

Pin Nama

Inpul Loading
Faclor(lu)

0

2
1

G

...

Symbol

Typ (ns)'

G Input Pulse Width

IGW

2.5

Data Setup Time
Data Hold Time

Iso
tHO

1.0
1.5

Output Prlvlng
Factor (Iu)

Pin Name

18
18

P
N

• Minimum values lor Ihe Iypical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Inputs

Pulputs

0

G

P

H

H

Po

No

L

H

Po

No

H

L

H

L

L

L

L

H

C1D-LT4-EO

3-274

N

Sheet 1/3

I Page 16-14

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

" CG10 " Version

Cell Name

LT4
Equivalent Circuit

PA

DA

0---'-------1

TXGO

NA

XGO

-L
TGO

DB

0---+

DC

0---+

DO

0---+

C10-LT4-EO

~P8

~NB
~pc

~NC

Sheet 2/3
Page H>-15

3-275

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 .. Version

Cell Name

LT4
Definitions of Parameters
(Case1)
G

D

1 4 - - - - - lpel

----~

P,N

(Case2)
G

j

-tso-

'I

I--

tHO-

o

1\
_t"._

P,N

C1D-LT4-EO

Sheet 3/3
Page 16-16

3-276

CG10 Series Unit Cell Ubrary

CMOS Channeled Gate Arrays

Shift Register Family

Page

UnH Cell
Name

3-279

FS1

4-bit Serial-in Parallel-out Shift Register

18

3-281

FS2

4-bit Shift Register with Synchronous Load

30

3-283

FS3

4-bit Shift Register with Asynchronous Load

34

3-286

SR1

4-bit Serial-in Parallel-out Shift Register with Scan

36

Function

Basic
Cells

II1II

3-277

CG10 Series Unit CeR Library

3-278

CMOS Channeled Gate Arrays

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name

Function

Number of BC

I

4-bit Serial-in Parallel-out Shift Register

FS1

Cell Symbol

Propagation Delay Parameter
tdn

!up
to

KCL

to

KCL

KCL2

COR2

1.513

0.067

1.963

0.051

0.067

4

18
Path

CKtoO

"D~

CK

as

OC

00

Symbol

Parameter

so

tew

2.5

SD Setup Time
SD Hold Time

tSSD
h-4S0

0.4
0.2

Clock
Pause
Time

Input Loading
Factor (Iu)

Pin Name

Typ (ns)'

Clock Pulse Width

C ~161u
I
I 16 < C <321u
32 < C

~481u

3.7
5.3
6.9

tCWl··

tcWL....
tcWLu

1
1

CK

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.
Pin Name

Output Driving
Factor (Iu)

a

16

•• The value of !Cwe depends on the load(c)
connected 10 the output terminals, OA, as,

oc and 00.

Function Table
Inputs

Outputs

SD

CK

OA

OB

SD

J.

SO

OAn

OC

OD

OBn OCn

NOTE: • SD = H or l
• OAn, OBn and OCn are levels of
OA, OB, and OC respectively,
before the falling edge of CK, i.e.
1 bit shift by the falling edge of CK.

C10-FS1-EO

Sheet 1/2

I

Page17-1

3-279

• CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

FS1
Equivalent Circuit

OA

as OC

00

------------------------------------------- --f---I- f-1
XCKO

CKO

-L

-L

so
I
I

T

T

XCKO

CKO
CKO

XCKO

-L

-L

T

T

XCKO

CKO

1 bil

----.----.------ .. ---------------------------~-CK~CKO
V

~XCKO

Definition of Parameters

lew

ICWL_

,--

CK

~ISSD

tHS~

so

-'pda

C1D-FS1-EO

Sheet 212
Page17-2

3-280

I . CG70

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

.. Version

I Number of BC

Function

FS2

I

4-bit Shift Register with Synchronous Load
Cell Symbol

Propagation Delay Parameter

tup
to

to
1.963

KCL

KCL2
0.067

Path

CDR2

4

CKtoO

Symbol
lew

Typ (ns)"
2.5

SO SetuD Time
SO Hold Time

t sso
'"so

1.8
0.8

Load Setup Time
Load Hold Time

I SL
t"L

2.7
0.4

P Setup Time
P Hold Time

I sp
I HP

2.3
1.0

tCWl'"

3.7
5.3
6.9

1.450

PAP8PCPD-

tdn
KCL

30

0.067

0.051

I--OA
1--08
I--OC
I--OD

SDCK--<
L-

Parameter

Clock Pulse Width

Pin Name

Inpul Loading
Faclor (Iu)

CK
L
P

1
1
1
1

Pin Name

Output Driving
Faclor (Iu)

0

16

so

C ~161u
16 < C <32 lu
I 32 < C ~481u

I

Clock
Pause
Time

ICWL"
tCWl·"

" Minimum values for Ihe typical operating condition.
The values for the worst case operating condition are given by the maximum delay

multiplier.
""The value of iCWL depends on the load(e)
connected 10 the output terminals. OA, 08, OC and 00.

Function Table
Inputs

Outputs

SO

L

P

CK

OA

OB

SO

L

X

J,.

SO

OAn

X

H

P

J,.

PA

PB

OC

00

OBn OCn
PC

PO

NOTE: • SO = H or L
• OAn, OBn and OCn are levels of
OA, OB, and OC respectively,
before the falling edge of CK, Le.
1 bit shift by the falling edge of CK .
• P represents PA, PB, PC and PD.
C1D-FS2-EO I

Sheet 1/2

I

Page 17-3

3-281

• CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

FS2
PA

Equivalent Circuit

SO C>--i---I-----

OA

PB

rr-r-r

'1-

• - - - • - - - - •• - - - - - - - - • - - - - - - - - - - - • - • --)O---+-!- - - - -

PC

PO

-r-

T

T
XCKO

CKO

, 1 bit
...............................................................................................
-'- .......................... ..

CK~CKO

L-

V

XCKO

Definition of Parameters
lew

tCWL

CK
_tsse

v---

tHSo-

If

so
_Isp

tHP-

)(

P
ISl

IHL

L
!--Ipd-

a

C10-FS2-EO

Sheet 2/2
Page17-4

3-282

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

FS3

I • CG10 • Version
I Number 01 BC

I

4-bit Shift Register with Asynchronous Load
Cell Symbol
!Up

PAPBPCPD-

to

KCL

1.425
2.900
1.269

0.072
0.072
0.072

Propagation Delay Parameter
!dn
to
KCL
KCL2
CDR2

1.325
2.188
1.888

34
Path

CKloQ
LloQ
PloQ

0.062
0.062
0.062

f--OA
f--os
f--OC
f--OD

soCKL--<
Parameter

Pin Name

Input Loading
Factor (Iu)

CK
SO
L
P

2
2
1
2

Pin Name

Outpul Driving
Factor (Iu)

0

18

Symbol
lew

Typ (ns)'

tCWH

2.5
2.5

Load Pulse Width

ILW

3.9

SD SetuD Time
SD Hold Time

I SSD

0.7
1.1

Clock Pulse Width
Clock Pause Time

P SetuD Time
P Hold Time

IHSD

0.2
1.5

I SP
I HP

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Outputs

Inputs
L

P

SD

CK

Q

X
X

X
X

H

i
i

H

L

L

L

H

H

X

L

H

X

H

C10-FS3-EO

I

L
L

Sheet 113

I

Page17-5

3-283

• CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cel/Name

FS3
PA

aA

PB

aB

pc

ac

PO

Equivalent Circuit

SO 0 - - - - - - 1

..

Equivalent Circuit of FFO

P

DO

CKO
XCKO
XLDO
LOO

a
a

ao

ao
DO

T

CKO

C10-FS3-EO

XCKO

Sheet 2/3
Page17-6

3-284

1 . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• Version

I

Cell Name

I

FS3

Definition of Parameters

CK

---""',

t---1cw

----1---

Icw><_

,

,

so

J
- I s s o - !---IHSO-

'k

l

ILW

P
r---ISp

IHP"

..
C1o-FS3 EO I

Sheet3~

l

Page17-7

3-285

I .. CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

Number of BC

Funcllon

Cell Name

I

4-bit Serial-in Parallel-out Shift Register with SCAN

SR1

Cell Symbol

Propagation Delay Parameter

!up

!dn

10

KCL

10

KCL

KCL2

CDR2

2.044

0.D38

2.106

0.039

0.062

7

36
Path

CKtoQ

'U~

CK

OB
OC
00

IH
SI
A
B

Parameter

Clock Pulse Width
Clock Pause Time
Data Setuo Time
Data Hold Time

Pin Name

3.5
3.5
2.1
1.0

tCWH

Iso
I"D

Inpul Loading
Faclor (Iu)

0
CK
IH
SI
A.B

1
1
1
1
1

Pin Name

Oulpul Driving
FaClor (luJ

a

36

C10-SR1 EO

Typ (ns)'

Symbol
lew

• Minimum values for Ihe typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Sheet 1/3

I

3-286

Page17-8

• CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

SR1
OA

D

OB

DO
00
SDO SOO
CLK
XClK
ACK
XACK
BCK
XBCK

51

CLK
XClK
ACK
XACK
BCK
XBCK

OC

OD

CLK
XClK
ACK
XACK
BCK
XBCK

XClK
ACK
XACK
BCK
XBCK

FFO

FFO

FFO

XBCK

ClK

---L

XClK

---L ---L

FFO

r - - - - i )0------000

1-+---1

DO

BCK

XClK
XClK

XACK

)O---t----o SOO

CLK

ACK

---L

---L ---L

I

I

SDO

ACK

ClK

I

I

XACK

XCLK

BCK

---L

ClK
CK
IH

IXBCK

XCLK

o---J>o--r---

A

.

C10-SR1-EO

XACK

L.[>o-ACK

o---J>o--r---

B

.

BCK

L . [ > o - XBCK

Sheet 2/3

Page 17-9

3-287

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I .. CG10 .. Version

Cell Name

SR1

Definition of Parameters

t - - - 1 c w - - - i - - - ICWH_
CK

o

..
C10 SR1-EO

3-288

Sheet 3/3

I Page17-10

CG 10 Series Unit Cell Library

CMOS Channeled Gate Arrays

Parity Generator/Selector/Decoder Family

Page

UnH Cell
Name

Function

Basic
Cells

Parity Generators/Checkers

3-291

PE5

5-bit Even Parity Generator/Checker

12

3-292

P05

5-bit Odd Parity Generator/Checker

12

3-293

PE8

8-bit Even Parity Generator/Checker

18

3-294

POB

8-bit Odd Parity Generator/Checker

18

3-295

PE9

9-bit Even Parity Generator/Checker

22

3-296

P09

9-bit Odd Parity Generator/Checker

22

2:1 Data Selector

12

Data Selector

3-297

P24

Decoders

3-298

DE2

2:4 Decoder

5

3-299

DE3

3:8 Decoder

15

3-301

DE4

2:4 Decoder

8

3-302

DE6

3:8 Decoder

30

3-304

T2B

2:1 Selector

2

3-305

T2C

2:1 Selector

4

3-307

T2D

2:1 Selector

2

3-308

T2E

2:1 Selector

5

3-309

T2F

2:1 Selector

8

3-311

T5A

4:1 Selector

5

3-313

V3A

1:2 Selector

2

3-314

V3S

1:2 Selector

4

..

Selectors

Magnitude Comparator

3-315

MC4

Magnitude Comparator

42

3-289

CG10 Series Unit CaN UbrSry

3-290

CMOS Channeled Gale Arrays

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 • Version
Number 01 BC

Function

PES

I

5-bit Even Parity Generator/Checker
Cell Symbol

Propagation Delay Parameler
Idn
10
KCL
KCL2
CDR2

lup

AD

Bl
B2
Cl
C2

10

KCL

1.638
1.638
2.S88

0.034
0.034
0.034

2.131
2.044
3.019

12
Palh

AtoX
BtoX
CtoX

0.023
0.023
0.023

X

Parameter

Symbol

Typ (ns)'

Inpul Loading
Faclor(lu)

Pin Name
B
C

2
2
2

Pin Name

OUlpul Driving
Faclor(lu)

X

36

A

• Minimum values lor Ihe Iypical operating condition.
The values lor Ihe worst case operating condilion are given by Ihe maximum delay
multiplier.

Function Table

Equivalent Circuit

l:input

X

Odd

l

Even

H

Bl

I'"'

B2

.......
X

Cl
C2

.....
II

.....

.......

A

C1o-PES EO

Sheet 111

I

Page 20-1

3-291

1m

I " CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function
I

POS

• Version

I

Propagation Delay Parameter
tdn

!Up

AD

Bl
B2
Cl
C2

to

KCL

1"0

KCL

1.644
1.788
2.619

0.034
0.034
0.034

1.919
1.900
2.850

0.023
0.023
0.023

KCL2

12

I

5-bit Odd Parity Generator/Checker
Cen Symbol

Number of BC

Path

CDR2

AtoX
Bto X
CtoX

X

Symbol

Parameter

Pin Name

Input Loading
Factor (Iu)

A
B
C

2
2
2

Pin Name

Output Driving
Factor (Iu)

X

36

Typ (ns)'

• Minimum values for the typical operating condition.

The values for the worst case operating condition are given by the maximum delay
multiplier.

Equivalent Circuit

Function Table

l:input

X

Odd

H

Even

L

Bl
B2

'r-..
,L/

X

Cl
C2

Ir-..

r-..

.L/

A

C1D-POS EO

3-292

Sheel1/1

I

Page 20-2

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

-'

Cell Name

PE8

Function

I • CG10 .. Version
I Number of BC

-r

5-bit Even Parity Generator/Checker
Cell Symbol

Propagallon Delay Parame.er
.dn
.0
KCL
KCL2
COR2

tup

.0
2.406
2.463
2.456
2.513
A1A28182C1C20102-

18

KCL

0.067
0.067
0.067
0.067

2.706
2.763
2.750
2.806

Palh

AtoX
Bto X
CtoX
DtoX

0.045
0.045
0.045
0.045

P-X

Symbol

Parameter

Pin Name

Input Loading
Fac'orClu)

A
8
C
0

2
2
2
2

Typ Cns)'

Output Driving

Pin Name

Fac.or Clu)

X

18
• Minimum values for .he typical operating condition.
The values for Ihe worst case operating condition are given by the maximum delay
multiplier.

Function Table

Equivalent Circuit

A1

l:input

A2

X

Odd

L

81

Even

H

82

Ir-...

II
......
Ir-...

II
......
X

, .......

01

'r-...

02

C1D-PE8 EO

Sheet 111

I

r-...

C1
C2

......
I

Page 20-3

3-293

..

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function

Cell Name

POS

I • CG10 • Version
I Number of BC

I

8-bit Odd Parity Generater/Checker
Cell Symbol

Propagation Delay Parameter
tdn
to
KCL
KCL2
CDR2

lup

A1A29192C1C201D2-

to

KCL

2.356
2.413
2.419
2.475

0.067
0.067
0.067
0.067

2.675
2.731
2.606
2.663

18
Path

AtoX
BtoX
CtoX
DtoX

0.045
0.045
0.045
0.045

-X

Symbol

Parameter

Pin Name

Input Loading
Factor (Iu)

A
8
C
D

2
2
2
2

Pin Name

Output Driving
Factor (Iu)

X

18

Typ (ns)'

• Minimum values for the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

Equivalent Circuit

Function Table

tinput

X

Odd

L

Even

H

A1
A2
81
82

11'"'

......

'"'

/I

I ......

X
C1
C2

I'"'

01

'"'

02

C10-P08 EO

3-294

Sheet 1/1

I

II
......

......

I

Page 20-4

I .. CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

PE9

Number of BC

Function

I

9-bit Even Parity Generator/Checker
Cell Symbol

Propagation Delay Parameter

lup

Idn

10

KCL

10

KCL

3.306

0.067

3.569

0.045

KCL2

22
Path

CDR2

Ato X

AlA2A3-

M-

~X

ASA6A7ASA9-

Symbol

Parameter

Pin Name

Inpul Loading
Factor (Iu)

A

2

Pin Name

Oulput Driving
Factor (Iu)

X

18

Typ (ns)·

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table

Equivalent Circuit

A3

l:input

X

Odd

L

AS
A9

Even

H

AI

C10-PE9-EO

I

Sheet 1/1

I

......

A2

+PTt7

A4

...u:::::..

AS

Tt7

A6
A7

--J..+::>..

......
X

Tt7

I

Page 20-5

3-295

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I . CG10 .. Version

_1

Function

P09

9-bit Odd Parity Generator/Checker
Prop~9a1ion

Cell Symbol
tup

AtA2A3A4ASA6A7ASA9-

to

KCL

to

3.250

0.067

3.569

Delay Parameter
tdn
KCL
KCL2
CDR2

Number of BC

I

22
Path

AtoX

0.045

t--x

Symbot

Parameter

Typ (n5)'

Input Loading
Factor (Iu)

Pin Name

A

2

Pin Name

Output Driving
Factor (Iu)

X

18
• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Equivalent Circuit

Function Table

A3

:Einput

X

AS

Odd

H

A9

Even

L

Al
A2

C10 P09-EO

3-296

I

Sheet 1'1

I

.....
~

II

Tt7

A4
AS

~

AS
A7

~

IV'

X

I

Page20-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 " Version
Number 01 BC

Function

P24

I

4-wide 2 : 1 Data Selector
Cell Symbol

PropagaUon Delay Parameter
!dn
io
CDR2
KCL
KCL2

!up

A181A282A3B3M84SAS8-

to

KCL

0.594
0.725
0.506
0.625

0.034
0.034
0.034
0.034

0.519
0.606
0.594
0.675

12
Path

AtoX
Bto X
SAtoX
SBto X

0.023
0.023
0.023
0.023

-X1
-X2
-X3
-X4
Symbol

Parameter

Pin Name

Input Loading
Factor (Iu)

A
8
S

1
1
4

Pin Name

Output Driving
Factor (lui

X

36

Typ (ns)'

• Minimum values lor the typical operating condition.
The values for the worst case operating condition are given by !he maximum delay
multiplier.

Function Table

Equivalent Circuit

SA

SB

Xn

L
H
L
H

L
L
H
H

L
An
Bn
An+Bn

A1

roo-B1

X1

-

A2
~

B2

X2

A3
~

B3

X3

A4
~

84

X4

~
SASB-

C10-P24-EO

I

Sheet 1/1

I

I

Page20-7

3-297

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10

• Version
Number 01 BC

Function

DE2

I

2: 4 Decoder
Cell Symbol
tup
to

KCL

0.494
0.550
0.231
0.550
0.175
0.494

0.067
0.067
0.067
0.067
0.067
0.067

Propagation Delay Parameter
tdn
to
KCL
KCL2
CDR2

0.675
0.606
0.281
0.606
0.350
0.675

5
Path

AtoXO
AtoX1
Ato X2,X3
Bto XO
B to X1,X3
BtoX2

0.079
0.079
0.079
0.079
0.079
0.079

'D"
X,
X2
X3

B

Symbol

Parameter

Pin Name

Input Loading
Factor (Iu)

A
B

3
3

Pin Name

Output Driving
Factor (Iu)

X

18

Typ (ns)'

• Minimum values lor the typical operating condition.
The values tor the worst case operating c:ondition are given by the maximum delay
multiplier.

Function Table

Inputs

Equivalent Circuit

Outputs

A

A

B

X3

X2

X1

XO

L
L
H
H

L
H

H
H
H
L

H
H
L
H

H

L
H
H
H

L

H

L

H
H

B

~

XO

x,

r~

X2

X3

Cl0 DE2 EO

3-298

Sheet 1/1

I

Page 20-8

I • CG10 " Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number of BC

Function

3: 8 Decoder

DE3

Cell Symbol

Propagation Delay Parameter

Idn

tup

-XO
-Xl
-X2
-X3
-X4
-X5
-X6

AB-

c-

15

I

to

KCL

to

KCL

0.900
1.525
0.831
1.456
0.769
1.394

0.067
0.067
0.067
0.067
0.067
0.067

1.044
1.525
1.075
1.556
1.113
1.594

0.107
0.107
0.107
0.107
0.107
0.107

KCL2

Path

CDR2

Ato
Ato
Bto
Bto
C to
C to

XO-X3
X4-X7
XO-X3
X4-X7
XO-X3
X4-X7

r--X7

Symbol

Parameter

Typ (ns)'

Inpul Loading
Faclor (Iu)

Pin Name

C

1
1
1

Pin Name

Oulpul Driving
Faclor (Iu)

X

14

A
B

• Minimum values for the typical operating condition.

The values for the worst case operating condition are given by the maximum delay
mul~plier.

Function Table
Inputs

Outputs

A

B

C

XO

X1

X2

X3

X4

X5

X6

X7

L

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

L
H
H
H
H
H
H
H

H
L
H
H
H
H
H
H

H
H
L
H
H
H
H
H

H
H
H
L
H
H
H
H

H
H
H
H
L
H
H
H

H
H
H
H
H
L
H
H

H
H
H
H
H
H
L
H

H
H
H
H
H
H
H
L

L
L

L
H
H
H
H

C10-DE3-EO

Sheet 1/2

I Page 20-9

3-299

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

.. CG10 .. Version

Cell Name

DE3
Equivalent Circuit

A 0----1

)0.-1>----------..--1
0 - - - 0 XO

B 0----1

c 0---1

)o.-1-----+-1f-4

b---o

Xl

b---o

X2

0---0

X3

b---o

X4

~-1-----+-

1}--xo
-Ff)
-- Ff)
L::f)

C10 DE4 EO

I

Sheet 111

I

XI

X2

X3

I Page 20-11

3-301

Ell

I .. CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

DE6

" Version
Number 01 BC

Function

3 : 8 Decoder with Enable
Cell Symbol

Propagation Delay Parameter

tdn

tup
to

KCL

fO

KCL

1.906
1.806

0.067
0.067

3.719
2.050

0.045
0.045

KCL2

CDR2

I

30
Path

GloX
Slo X

r-- XO

GtG2G3-

t--Xt
t--X2
t--X3
t--X4
t--X5
f--X6
t--X7

S1S2S3-

Symbol

Parameter

Typ (ns)'

Input Loading
Factor (Iu)

Pin Name

G
S

1
1

Pin Name

Output Driving
Factor (Iu)

X

18
• Minimum values tor the typical operating condition.
The values for the worst case operating condition arB given by the maximum delay
multiplier.

Function Table
Gl

G2+G3

S3

S2

Sl

X7

X6

X5

X4

X3

X2

Xl

XO

X
L

H

X
X

X
X

X
X

H
H

H
H

H
H

H
H

H
H

H
H

H
H

H
H

H
H
H
H
H
H
H
H

L
L
L
L
L
L
L
L

L
L
L
L

L
L

L

H
H
H
H

L

L

L

L

L
L

H
H
H
H
H

H
H
H

H

L

H

H
H
H
H
H
H

H
H

H
H

L

H
H

L

H
H
H
H
H
H
H

H

H

L

H

L

H

H
H

H
H
H

H
H
H
H

H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H
H

C10-DE6-EO

I

3-302

X

H
H
H
H

Sheet 1/2

L
L

I Page 20-12

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

.. CG10 • Version

Cell Name

DE6
Equivalent Circuit

Gl

" > - - - 0 XO

G2o-----4~r--+~-----~~~
G3O-----+~

) - - - 0 Xl

)---0

X2

>---<> X3

>---OX4

Sl

0----4 )o---H-I--t )c)--+--+-I--l---I

" > - - - 0 X5

)---OX6

)---OX7
S3

0----4

C10-DE6-EO

)O-----~ )(>---~--t

Sheet 2/2
Page 20-13

3-303

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function

Cell Name

I • CG10 "Version
I Number of BC

2 : 1 Selector

T2B

Cen Symbof

Propagation Delay Parameter
!dn
to
KCL
KCL2
CDR2

!Up
to

KCL

0.325
0.381

0.067
0.067

0.488
0.619

I

2
Path

A.BtoX
StoX

0.051
0.051

:D'

SI
S2

Parameter

Symbol

Typ (ns)'

Input Loading
Factor (Iu)

Pin Name
A.B
S

2
1

Pin Name

Output Driving
Factor (Iu)

X

18
• Minimum values lor the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table

Equivalent Circuit

Inputs

Outputs

A

B

S1

S2

X

L

H
H

L
L

H
H

H

L

H
H

H

...LA

H
X
X
L
L

H
H
H

H
H

L
L

L

L
L
L

H

H

L

L

H

H

L
L
Inhibit
Inhibit
Inhibit
Inhibit

=t-

~X

B

SI

-r

S2

C10 T2B-EO

3-304

Sheet 1/1

I

I Page 20-14

I • CG10 "Version
I Number 01 BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
I

Cell Name

T2C

Dual 2 : 1 Selector
Cell Symbol

Propagation Delay Parameter

Idn

lup

10

KCL

10

KCL

0.319
0.419

0.067
0.067

0.481
0.644

0.051
0.051

KCL2

CDR2

I

4
Path

A,Bto X
Sto X

lr
s

A1A2B1B2-

p..-XO

p.--X1

Symbol

Parameter

Typ (ns)'

Inpul Loading
Faclor (Iu)

Pin Name

S

2
2

Pin Name

Output Driving
Faclor (Iu)

X

18

A,B

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Tab)e
Inputs

Outputs

A1 ,B1

A2, B2

S1

52

XO

X1

L
H
X
X
L
H
L
H

X
X
L
H
H

L
L
H
H
L

L
H
L

L
H
H

H
H
L
L
L
L
H
H

H
L
H
L
Inhibit
Inhibit
Inhibit
Inhibit

H
L
H
L
Inhibn
Inhibn
Inhibit
Inhibit

C1Q-T2C-EO I

Sheet 1/2

I

I Page 2Q-15

3-305

" CG10 "Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

T2C
Equivalent Circuit

A1

0---+---1

XO

A2

0---/---1

Bl 0---/---1

Xl

B2

0---/---1

Slo------'

S20---------'

lID

C10-T2C-EO

Sheet 2/2
Page 20-16

3-306

" CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number of Be

Function

2 : 1 Selector

T2D

I

Cell Symbol

2

Propagation Delay Parameter

!up

tdn

to

KCL

0.388
0.419

0.076
0.076

1'0
0.438
0.319

KCL

KCL2

COR2

Path

A.Sto X
Sto X

0.067
0.067

:D'

SI
S2

Symbol

Parameter

Typ (ns)'

Input Loading
Factor (Iu)

Pin Name

5

1
1

Pin Name

Output Driving
Factor (Iu)

X

14

A.B

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Equivalent Circuit

Function Table
Inputs

Outputs

A

S

S1

S2

X

L

X

X

H
H

H

H

L
L

H
H
L
H

L
L

H

X
X
L

L
H
H

L

H
H
H
L
L

L

H

L
H
L
H

A

L
L
Inhibit
Inhibit
Inhibit
Inhibit

B

51

Etr-

-Ox

B--,-

52

C10 T20-EO

Sheet 1/1
Page 20-17

3-307

• CG10 .. Version

FUJITSU CMOS GATE ARRAY UNiT CELL SPECIFICATION
Cell Name
Function

T2E

Number 01 BC

Dual 2 : 1 Selector
Cell Symbol

Propagation Delay Parameter
tdn
to
KCL
KCL2
CDR2

tup
to

KCL

0.338
1.025

0.067
0.067

0.338
1.013

0.056
0.056

4
4

0.079
0.079

I

5
Path

A,BtoX
StoX

"D~
A2
Bl
B2

XI

S

Symbol

Parameter

Input Loading
Factor (Iu)

Pin Name

A.B
S

2
1

Pin Name

Outpul Driving
Faclor (Iu)

X

18

l1.li

Typ (ns)'

• Minimum values lor the typical operating condition.
The values lor the worst case operaling condilion are given by the maximum delay
mUltiplier.

Equivalent Circuit

Il
AI

::E-

~XO

A2

r---=c
Bl

::E-

~Xl

82

T

S

C10-T2E EO

3-308

I

Sheet 1/1

4
I Page 20-18

I "CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

T2F

I

2 : 1 Selector
Cell Symbol

Propagation Delay Parameter

!dn

tup

AlA2BlB2ClC2DlD2-

to

KCL

0.338
1.025

0.067
0.067

to
0.338
1.013

KCL

KCl2

0.056
0.056

0.079
0.079

"Version
Number of Be

CDR2

4
4

8
Path

A,B,C,DIO X
SloX

p.--XO
p-Xl
p.--X2
p.--X3

5Parameter

Pin Name

Inpul Loading
Faclor (Iu)

A,B.C,D
5

2
1

Pin Name

Oulpul Driving
Faclor (Iu)

X

18

Symbol

Typ (ns)'

• Minimum values for the typical operating condition.
The values for the worsl case operaling condilion are given by the maximum delay
multiplier.

C10-T2F-EO

I

Sheel1/2

I

I Page 20-19

3-309

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

"CG10 "Version

Cell Name

T2F
Equivalent Circuit

XO

Xl

X2

X3

s

C10-T2F-EO

Sheet 2/2
Page 20-20

3-310

I "CG10 " Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number of BC

Function

T5A

4 : 1 Selector
Cell Symbol

Propagation Delay Parameter
tdn
to
KCL
KCL2
CDR2

lup
to

KCL

0.625
0.625
0.350

0.097
0.097
0.097

0.625
0.525
0.338

I

5
Palh

A,810X
Sl-410X
S5-610 X

0.090
0.090
0.090

!SrrT
A1A2B1B2-

p..-X

IJs

Symbol

Parameter

Typ (ns)'

Input Loading
Factor (Iu)

Pin Name

A.B
S

1
1

Pin Name

Output Driving
Factor (Iu)

X

9

• Minimum values tor the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Oulput

Inputs
A1

A2

81

82

51

52

L

L

H

L
H
H

H
H
L
L

L
H
L
H
L
H

53

L
L
H
H

54

55

56

X

H
H
L
L

L
L
L
L
H
H
H
H

H
H
H
H
L
L
L
L

H
L
H
L
H
L
H
L

A1",A2 to Sl=S2 or S5=S6lnhibit
81",82 to 53=54 or S5=S6lnhibit
A1,A2",81,82 or SS=S6lnhibit
C10-TSA EO

I

Sheet 1/2

I Page 20-21

3-311

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version

Cell Name

T5A
Equivalent Circuit

A1 0 - - - 1 )o--+---1

A20---I )0--+-1

51o_------1
520_--------------~

+---<>x

540_----------,
530_-----,

B1 0 - - - 1

)o--+---1

B2 0----1 )0---+----1

~o_--------------------------~
~o_----------------~

Cl0-TSA-EO

Sheet 2/2
Page 20-22

3-312

I • CG10 • Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
I

Cell Name

V3A

I

1 : 2 Selector
Cell Symbol

PropagaUon Delay Parameter
tdn
to
KCL
KCL2
CDR2

tup

to

KCL

0.388
0.344

0.076
0.076

0.438
0.281

2
Path

Ato X
Sto X

0.067
0.067

'U'"

SI

S2

XI

Sy_mbol

Parameter

Typ (ns)'

Input Loading
Factor (Iu)

Pin Name

A

1
1

S

Output Loading
Factor (Iu)

Pin Name

1

X

Pin Name

Output Driving
Factor (Iu)

X

14

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

lID

Equivalent Circuit

Function Table
Inputs

Outputs
XO

Il-

X1

A

81

S2

L

L

L

L

H

L

X

H

L

L

H

H

X

L

H

H

xo

Inhibit

Ao-{>o-

r
XI

Inhibit

H

L

L

H

H

L

X

L

H

L

H

L

X

H

H

H

51

C10-V3A EO

--r

52

Inhibit

Sheet 1/1

I Page 20-23

3-313

" CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
Function

V38

J

Dual 1 : 2 Selector
Cell5ymbol
top

to

KCL

0.400
0.356

0.076
0.076

Propagation Delay Parameter
tdn
to
KCL2
CDR2
KCL
0.475
0.300

Number of BC

I

4
Path

A,Bto X
stoX

0.067
0.067

'D"

B
51
52

Xl
X2
X3

~mbol

Parameter

Pin Name

Input Loading
Factor (Iu)

A
B
5

1
1
2

Typ (ns)'

Output Loading
Factor (Iu)

Pin Name

X

1

Pin Name

Output Driving
Factor (Iu)

X

14

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay

multiplier.

Function Table

Equivalent Circuit

Inputs

Outputs

A,B

51

52

XO,

L

L

L

L

H

L

X

H

L

L

H

H

X

L

H

H

H

L

L

H

H

L

X

L

H

L

H

L

X

H

H

H

X2

X1, X3

Inhibit

I-l-

,~r~
~D

XO

Xl

-3:
Inhibit

,~r~
~~

Inhibit
51

X2

X3

-r

52
C10-V3B EO

3-314

Sheet 1/1

I Page 20-24

I " CG10 " Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number of BC

Funcllon

MC4

Propagation Delay Parameter

tup

A3B~==
A2 B: = =
BlA1 BO = =
AO " IGIEIS-

-OG
r--OE
r--OS

tdn

to

KCL

to

KCL

KCL2

CDR2

3.306
3.363
1.475
1.206
3.238
3.294
1.406
1.331
3.556
3.488
1.338

0.122
0.122
0.122
0.122
0.122
0.122
0.122
0.122
0.067
0.067
0.067

3.950
3.881
1.738
1.506
4.081
4.013
1.869
1.444
2.725
2.781
0.894

0.045
0.045
0.045
0.045
0.045
0.045
0.045
0.045
0.051
0.051
0.051

0.062
0.062
0.062
0.062
0.062
0.062
0.062
0.062
0.067
0.067
0.067

4
4
4
4
4
4
4
4
4
4
4

Path

Ato OS
BtoOS
IEtoOS
IGtoOS
AtoOG
BtoOG
IEtoOG
IStoOG
AtoOE
BtoOE
IEto OE

Symbol

Parameter

42

I

4-bit Magnitude Comparator
Cell Symbol

Typ (ns)'

Input Loading
Factor (Iu)

Pin Name

A
B
IE
IG
IS

3
3
1
1
1

Pin Name

Output Driving
Factor (Iu)

OE
OG
OS

18
10
10

• Minimum value. for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table
Comparing Inputs

Cascading Inputs

A3,B3

A2,B2

Al,Bl

AO,BO

A3>B3
A3B2
A2Bl
AlBO
AOB)

IS
(AB)

OS
(A

V-

if-Equivalent
Circuit

1

OG

r--

A2
B2~

V-

IS

f-

=>

-

~t~
P-

f--

.---L.I

r--

IE

OE

I-~l.-'

r--

IG

Al
Bl

-I

:~

~

Pl.-'

-f--r--

l.-'

OS

1\
U
1
1
AO
BO

C10 MC4-EO

3-316

1

Sheet 2/2

~

if-I Page 20-26

CMOS Channeled Gate Arrays

CGIO Series Unit CeO Library

Bus Driver Family
Basic

Unit Cell

Page

Name

Function

Cells

3-319

B11

1-bit Bus Driver

5

3-320

B41

4-bit Bus Driver

9

IDI

3-317

CG10 Series Unit CaN Ubrary

3-318

CMOS Channeled Gate Arrays

• CG10 .. Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

Number of BC

Function

I

1-bit Bus Driver

811

Cell Symbol

Propagation Delay Parameter

tdn

tup
to

0.931
0.738

KCL

0.038
0.038

1'0

KCL

0.869
0.606

0.028
0.028

KCL2

5
Path

CDR2

Ato X
Cto X

';=o-~
Symbol

Parameter

Typ (ns)'

fnput Loading
Factor (Iu)

Pin Name

1
1

A
C

Output Loading
Factor (Iu)

Pin Name

X

1

Pin Name

Output Driving
Factor (Iu)

X

36

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Function Table

Equivalent Circuit
Co

Inputs

--L
XO

AO

T
Co
C

h{»--c

Output

AO

C

XO

X

H

Z

L

L

L

H

L

H

o

Co

Cl0 Bll EO

I

Sheet 111

I

Page 18-1

3-319

I "CG10 "Version
I Number 01 BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

841

Function

4-bit Bus Driver
Cell Symbol

Propagation Delay Parameter

!Up

AOAlA2A3C

I

teln

to

KCL

to

KCL

0.988
1.563

0.030
0.030

0.950
1.188

0.034
0.034

KCL2

9
Path

CDR2

AtoX
CtoX

-XO
XI
-X2
-X3

--<

Symbol

Parameter

Typ (n$)'

Input Loading
Factor (Iu)

Pin Name

1
1

A
C

Output Loading
Factor (Iu)

Pin Name

X

1

Pin Name

Output Driving
Factor (Iu)

X

36

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
mul1iplier.

Function Table

Equivalent Circuit
Co

AO

; ................................... ... -(- ..... ~
,,
,,,
,,
,
,,
,,

Inputs

XO

:-------------~-:
CO

.------------------.
' - , - - - XI
... _--_ ... ----_ .
.._-----_
-------.----------.

Al---:
A2---:

Output

An

C

Xn

X

H

Z

L

L

L

H

L

H

n=0-3

: - - - X2

.,-----------------_
------------------..
A3---:,----_ ...................... --- -_.' - , - - - X3
C

[»-rl»-co

CO

C10-B41 EO

3-320

I

Sheet 1/1

I

Page 18-2

CMOS Channeled Gate Arrays

CG10 Series Unit Cell Library

Clip Cells

Page

Unit Cell
Name

3-323

zoo

0 Clip

3-324

Z01

1 Clip

Function

Basic
Cells

o
o

..

3-321

CG10 Series Unit Cell Ubrary

3-322

CMOS Channeled Gate Arrays

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I . CG10

• Version

I

Function

Cell Name

o Clip

ZOO

Cen Symbol
\Up

10

KCL

Number 01 Be

I

Propagation Delay Parameler
Idn
KCL
10
KCL2
CDR2

a
Path

X

~
Parameter

Pin Name

Inpul Loading
Faclor(lu)

Pin Name

OUlpul Driving
Faclor(lu)

X

200

Typ (ns)'

Symbol

• Minimum values for Ihe typical operating condition.
The values for the worsl case operating condilion are given by !he maximum delay
multiplier.

C1Q-ZOQ-EO

I

Sheet 1/1

I

Page 19-1

3-323

IDII

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10 • Version
Number 01 BC

Function

Z01

I

1 Clip
Cell Symbol
!Up

10

KCL

Propagallon Delay Parameler
!dn
10
CDR2
KCL
KCl2

0
Palh

Y
X

Parameter

Pin Name

Input Loading
Faclor(lu)

Pin Name

Output Driving
Faclor (Iu)

X

200

Typ (ns)·

Symbol

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

C10-Z01-EO

3-324

Sheet 1/1

I

Page

19-2

CMOS Channeled Gate Arrays

CG10 Series Unit Cell Library,

I/O Buffer Family

Page

Unit Cell
Name

Function

Basic
Cells

Input Buffers
3-329
3-330
3-331
3-332
3-333
3-334
3-335
3-336
3-337
3-338
3-339
3-340
3-341
3-342
3-343
3-344
3-345
3-346
3-347
3-348
3-349
3-350
3-351
3-352
3-353
3-354
3-355
3-356
3-357
3-358
3-359
3-360
3-361
3-362
3-363
3-364

11B
11BU
11BO
12B
12BU
12BO
IKB
IKBU
IKBO
IKC
IKCU
IKCO
ILB
ILBU
ILBO
ILC
ILCU
ILCO
11C
11CU
11CO
12C
12CU
12CO
11S
11SU
11S0
12S
12SU
12S0
11R
11RU
11RO
12R
12RU
12RO

Output Buffers
01B1
01BF2

3-365
3-366

Input Buffer (Inverter)
11B with Pull-up Resistance
11B with Pull-down Resistance
Input Buffer (True)
12B with Pull-up Resistance
12B with Pull-down Resistance
Clock Input Buffer (Inverter)
IKB with Pull-up Resistance
IKB with Pull-down Resistance
CMOS Interface Clock Input Buffer (Inverter)
IKC with Pull-up Resistance
IKC with Pull-down Resistance
Clock Input Buffer (True)
ILB with Pull-up Resistance
ILB with Pull-down Resistance
CMOS Interface Clock Input Buffer (True)
IKC with Pull-up Resistance
IKC with Pull-down Resistance
CMOS Interface Input Buffer (Inverter)
11Cwith Pull-up Resistance
11C with Pull-down Resistance
CMOS Interface Input Buffer (True)
12C with Pull-up Resistance
12C with Pull-down Resistance
Schmitt Trigger Input Buffer (CMOS, Inverter)
11 S with Pull-up Resistance
11S with Pull-down Resistance
Schmitt Trigger Input Buffer (CMOS, True)
12S with Pull-up Resistance
12S with Pull-down Resistance
Schmitt Trigger Input Buffer (TTL, Inverter)
11 R with Pull-up Resistance
11 R with Pull-down Resistance
Schmitt Trigger Input Buffer (TTL, True)
12R with Pull-up Resistance
12R with Pull-down Resistance
Output Buffer (Inverter)
Output Buffer (Inverter)

5
5
5
4
4
4
4
4
4
4
4
4
6
6
6
6
6
6
5
5
5
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
3
3
Continued on next page

110L=3.2 rnA
210L = 8 rnA
310L = 12 rnA

3-325

CG10 Series Unit Ceu Ubrary

CMOS Channeled Gate AmI)'s

1/0 Buffer Family

Page

Unit Cell
Name

Output Buffers
01L3
3-367
01Rl
3-368
01RF2
3-369
3-370
01S3
02Bl
3-371
02BF2
3-372
02L3
3-373
02Rl
3-374
3-375
02RF2
02S3
3-376
O4Tl
3-377
O4TF2
3-378
3-379
04W3
O4Rl
3-380
O4RF2
3-381
O4S3
3-382
3-383

02S24

3-384

O4S24

Basic
Cells

Function

Power Output Buffer (Inverter)
3
5
Output Buffer (Inverter) with Noise Limit Resistance
Output Buffer (Inverter)
5
Power Output Buffer (Inverter) with Noise Limit Resistance 5
Output Buffer (True)
2
Output Buffer (True)
2
Power Output Buffer (True)
2
4
Output Buffer (True) with Noise Limit Resistance
Output Buffer (True) with Noise Limit Resistance
4
Power Output Buffer (True) with Noise Limit Resistance
4
3-state Output Buffer (True)
4
4
3-state Output Buffer (True)
Power 3-state Output Buffer (True)
4
Output Buffer (True) with Noise Limit Resistance
5
3-state Output Buffer (True) with Noise Limit Resistance 5
Power 3-state Output Buffer (True) with Noise Limit
Resistance
5
High Power Output Buffer (True) with Noise Limit
Resistance
6
High Power Output Buffer (True) with Noise Limit
Resistance
7

Bidirectional 1/0 Buffers (Buses)
H6Tl
3-state Output and Input Buffer (True)
3-385
H6T with Pull-up Resistance
3-386
H6TU
3-387
H6TD
H6T with Pull-down Resistance
H6TF2
3-state Output and Input Buffer (True)
3-388
H6TFU
H6TF with Pull-up Resistance
3-389
3-390
H6TFD
H6TF with Pull-down Resistance
3-391
H6W3
Power 3-state Output and Input Buffer (True)
3-392
H6WU
H6W with Pull-up Resistance
H6W with Pull-down Resistance
3-393
H6WD
H6Cl
3-394
3-state Output and CMOS Interface Input Buffer (True)
H6CU
3-395
HSC with Pull-up Resistance
HSCD
3-396
H6C with Pull-down Resistance
HSCF2
3-397
3-state Output and CMOS Interface Input Buffer (True)
H6CFU
3-398
HSCF with Pull-up Resistance
HSCFD
3-399
HSCF with Pull-down Resistance
H6E3
3-400
Power 3-state Output and CMOS Interface Input
Buffer (True)
3-401
H6EU
H6E with Pull-up Resistance
1101. =3.2 rnA
2101._ 8 rnA
310L -12 rnA
4101L=24 rnA

3-326

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

Continued on next page

CMOS Channeled Gate Arrays

CG10 Series Unit Cell Library

1/0 Buffer Family

Page

Unit Cell
Name

Basic
Cells

Function

Bidirectional I/O Buffers (Buses)
3-402
H6ED
H6E with Pull-down Resistance
3-403
H6S t
3-state Output and Schmitt Trigger Input Buffer
(CMOS, True)
H6S with Pull-up Resistance
3-404
H6SU
H6SD
H6S with Pull-down Resistance
3-405
H6Rt
3-406
3-state Output and Schmitt Trigger Input Buffer
(TTL, True)
3-407
H6RU
H6R with Pull-up Resistance
3-408
H6RD
H6R with Pull-down Resistance
H8Tt
3-state Output with Noise Limit Resistance (True) and
3-409
Input Buffer
3-410
H8TU
H8T with Pull-up Resistance
3-411
H8TD
H8T with Pull-down Resistance
H8TF2
3-state Output with NOise Limit Resistance (True) and
3-412
Input Buffer
3-413
H8TFU
H8TF with Pull-up Resistance
H8TF with Pull-down Resistance
3-414
H8TFD
3-415
H8W3
Power 3-state Output and Input Buffer (True)
3-416
H8WU
H8W with Pull-up Resistance
3-417
H8WD
H8W with Pull-down Resistance
H8Ct
3-state Output with Noise Limit Resistance and
3-418
CMOS Interface Input Buffer (True)
3-419
H8CU
H8C with Pull-up Resistance
3-420
H8CD
H8C with Pull-down Resistance
H8CF2
3-421
3-state Output with Noise Limit Resistance (True) and
Input Buffer
3-422
H8CFU
H8CF with Pull-up Resistance
3-423
H8CFD
H8CF with Pull-down Resistance
H8E3
3-424
Power 3-state Output with Noise Limit Resistance
and CMOS Interface Input Buffer (True)
3-425
H8EU
H8E with Pull-up Resistance
3-426
H8ED
H8E with Pull-down Resistance
3-427
H8S t
3-state Output with NOise Limit Resistance and
Schmitt Trigger Input Buffer (True)
H8S with Pull-up Resistance
H8SU
3-428
3-429
H8SD
H8S with Pull-down Resistance
H8Rt
3-state Output with Noise Limit Resistance and
3-430
Schmitt Trigger Input Buffer (True)
3-431
H8RU
H8R with Pull-up Resistance
H8RD
3-432
H8R with Pull-down Resistance
H8W24
High Power 3-state Output and Input Buffer
3-433

8
12
12
12
12
12
12
9
9
9

9
9
9
9
9
9

9
9
9
13
13
13
13
13
13
11

Continued on next page

'loL -3.2 rnA
210L = 8 rnA
310L -12 rnA
4101L=24rnA

3-327

CGfO Ssrifls Unit Gel Library

CMOS Channelfld Gate Anays

1/0 Buffer Family
Page

Unn Cell
Name

Function

Bidirectional 110 Buffers (Buses)
3-434
H8W1
H8W2 with Pull-up Resistance
3-435
H8WO
H8W2 with Pull-down Resistance
3-436
H8E24
High Power 3-state Output with Noise Limit Resistance
and Input Buffer (True)
3-437
H8E1
H8E2 with Pull-up Resistance
3-438
H8EO
H8E2 with Pull-down Resistance

'101. - 3.2 mA
210l_8mA
31ot. _12 mA
4101L_24 mA

3-328

Basic
Cells
11
11
11
11
11

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

Function

I • CG10 • Version
I Number of Be

Input Buffer (Inverter)

118

Cell Symbol
tup
to

1.000

KCL

0.017

Propag.llon DeI.y P.r.m....
IIIn
KCL
KCL2
COR2
to

0.963

I

5
Path

XtolN

0.023

X-{:>o--IN

Parameter

Pin Name

Inpul Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

IN

Typ n••

Symbol

36
• Minimum values for the typical operating condition.
The values for the worst case operating oondition are given by lhe maximum delay
multiplier.

C10-11B-EO

Sheet 1/1

I

Page 21-1

3-329

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CGtO • Version
Number 01 Be

Function

Input Buffer (Inverter)
with Pull-up Resistance

11BU

Cell Symbol
\lJ

to

KCL

1.000

0.017

Propagation Delay Parameter
IIln
to
KCL
KCL2
CDR2

0.963

I

5
Path

XlolN

0.023

X-[::>o-IN

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

IN

Typ, n ••

Symbol

36
• Minimum values fOf lIle typical operating condition.
The values for lIle worst case operating condition are given by !he maximum delay
multiplier.

C10-11 B lJ-EO

3-330

Sheel1/1

J

I

Page 21-2

I • CG10 • Version
I Number 01 Be

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

Input Buffer (Inverter)
with Pull-down Resistance

1180

Cell Symbol

ProPIIgatlon Delay Parameter

!Up

I

!dn

to

KCL

to

KCL

1.000

0.017

0.963

0.023

KCL2

5
Path

CDR2

Xto IN

X-(:>o--IN

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

IN

Typ(nl) •

Symbol

36
• Minimum values for the typical operating condition.
The values for the worst case operating oondition are given by the maximum delay
multiplier.

C1G-11BD-EO_

I

Sheet 1/1

I

I

Page 21-3

3-331

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10

• Version
Number 01

Function

Cell Nam.

Input Buffer (True)

128

Cell Symbol

tu
10

KCL

0.663

0.017

Propagation Delay P.r.metor
1I:In
KCL
10
KCL2
CDR2

1.150

I

Be

4
Pa!h

Xto IN

0.023

X-{»-IN

Parame1er

Pin Nam.

Input L""dlng
Factor (Iu)

Pin Name

Output Driving
Feclor(lu)

IN

Tvp, n• •

Svmbol

36
• Minimum values for !he typical operating condition.
The values for !he worst case operating conation are given by !he maximum delay
multiplier.

C1o-I2B-EO

3-332

Sheet 1/1

I

Page 21-4

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nam.

• Version
Numbe.olBC

Input Buffer (True)
with Pull-pu Resistance

12BU

Cell Symbol
IUp

X

I . CG10

Function

----[:>--

to

KCL

0.663

0.017

1.150

4
Path

XtolN

0.023

IN

Parameler

Pin Name

Inpul Loading
Fletor(lu)

Pin Name

Output Driving
Fletor(lu)

IN

Propagation DeIlY Perimeter
USn
'10
KCL
KCl2
COR2

I

Typ n• •

Symbol

36
• Minimum values lor the typical operating condition.
The values lor the worsl case operating conation are given by the maximum delay
multiplier.

C1D-12BU-EO

Sheet 1/1

I

Page 21-5

3-333

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nam.

I • CG10

• Version
Numt>erol

Function

Input Buffer (True)
with Pull-down Resistance

128D

Cell Symbol
IUp
to

KCL

0.663

0.017

Propagation Dalay Parameler
tdn
CDR2
KCL
KCL2
to

1.150

I

Be

4
Path

Xto IN

0.023

X - - - [ : ) - - - IN

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

IN

Symbol

Typ (n.)·

36
• Minimum values for the typical operating conation.
The values lor the worst case operating condition are given by IhII maximum delay
multiplier.

C10-12BD-EO

3-334

Shee 1/1

I

Page 21-6

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10

• Version

I

Funcllon

Cell Name

IKB

Clock Input Buffer (Inverter)
Cell Symbol
III

x-{:>o--

to

KCL

1.540

0.006

Propagation Delay Parameter
IIIn
to
KCL
KCl2
CDR2

1.010

Number of Be

I

4
Path

Xlo CI

0.005

CI

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

CI

200

Symbol

Typ (nl)·

• Minimum values lor the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

C10-IKB-EO

I

Sheel1/1

I

Page 21-7

3-335

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• Version
Number 01 BC

Function

Cell Name

Clock Input Buffer (Inverter)
with Pull-up Resistance

IKBU

Propagation Delay Parameter

Cell Symbol

I

tdn

IUp
to

KCL

to

KCL

1.540

0.006

1.010

0.005

KCL2

4
Path

CDR2

XtoCI

X~CI

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

CI

200

Typ (no)·

Symbol

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

C1G-IKBU-EO

3-336

I

Sheet 1/1

I

I

Page21-8

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
Cell Name
I

I • CG10

NumberolBC

Clock Input Buffer (Inverter)
with Pull-down Resistance

IKBD

Cell Symbol

!Up
to

KCL

1.540

0.006

Propagation Delay P.r.m....
ttln
KCL2
CDR2
to
KCL
1.010

• Version

I

4
Path

XloCI

0.005

X-{::>o-CI

Parameter

Pin Name

Input Loading
Factor (tu)

Pin Name

Output Driving
Factor (Iu)

CI

200

Tn (nol'

Symbol

• Minimum values lor the typical operating conation.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

C1CHKBD-EO

Sheel1/1

I

Page 21-9

3-337

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

IKG

I

Numberolac

CMOS Interface Clock Input Buffer (Inverter)
Cell Symbol

tu

x--{»o-

to

KCL

1.320

0.006

Propagation Delay Parameter
IIIn
. to
KCL2
CDR2
KCL

0.960

I

4
Path

XtoCI

0.005

CI

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Flctor (Iu)

CI

I . CG10 • Version

Function

Symbol

Typ ns •

200
• Minimum values for the typical operating oondition.
The values lor the worst case operating oonation ere given by the maximum delay
multiplier.

C10-IKG-E

3-338

Sheet 1'1

I Page 21-10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I . CG10

CMOS Interface Clock Input Buffer (Inverter)
with Pull-up Resistance

IKCU

Cell Symbol
IUp

x-(::>o-

to

KCL

1.320

0.006

Propagation Delay Porameter
\dn
KCLZ
COR2
to
KCL

0.960

Number 01 BC

I

4
Path

XtoCI

0.005

CI

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Faclor (Iu)

CI

• Version

I

Function

Cell Name

Symbol

Typ (ns)·

200
• Minimum values lor the typical operating conation.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

C1o-IKCU-EO

Sheet 1/1

I Page 21-11
3-339

Ell

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
Cell Name

Number 01 BC

CMOS Interface Clock Input Buffer (Inverter)
with Pull-down Resistance

IKeD

Cell Symbol
\up

X

I • CG10 • Version

---[::>0--

to

KCL

1.320

0.006

0.960

4
Path

XtoCI

0.005

CI

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

CI

Pro...,gatlon DeIlY Parameter
Idn
KCL2
to
KCL
CDR2

I

Symbol

Typ no)'

200
, Minimum values for the typical operating conchon.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

1o-IKCD-EO

3-340

Sheet

1/1

I

Page 21-12

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

Number 01 Be

Function

Cell Name

ILB

Clock Input Buffer (True)
Cell Symbol

Propagation Delay Parameter
!dn

\up
to

KCL

to

KCL

0.530

0.006

1.300

0.005

KCLZ

CDR2

I

6
Path

XtoCI

X-[:::>-CI

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

CI

Symbol

Typ (no)'

200
• Minimum values for the typical operating conation.
The values for the worst case operating conation are given by lhe maximum delay
multiplier.

C1D-ILB-EO

Sheet 1/1

I Page 21-13
3-341

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
Cell Name

., • CG10 • Version
Number of BC

Clock Input Buffer (True)
with Pull-up Resistance

ILBU

6

Cell Symbol
!Up
to

KCL

0.530

0.006

Propagation Delay Parameter
IIln
CDR2
to
KCL
KCL2

1.300

0.005

Palh
XloCI

X-{::>--CI

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

CI

200

Symbol

TvD ns

•

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

C1o-ILBU-EO

3-342

Sheet

1/1

I Page 21-14

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION

I

Cell Name

NumberolBC

Clock Input Buffer (True)
with Pull-down Resistance

ILBD

Cell Symbol
IUp

X

• CG10 • Version

Function

---t:>--

to

KCL

0.530

0.006

1.300

Path

XloCI

0.005

CI

Parameter

Pin Name

Input LOIdlng
Fletor (Iu)

Pin Name

Output Driving
Factor (Iu)

CI

6
PropagaUon Delay Plr.meter
IIln
'to
KCL
KCl2
COR2

Symbol

Typ (ns)'

200
• Minimum values lor the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

C1Q-llBD-EO

Sheel1l1

I

I Page 21-15
3-343

IIDII

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10

• Version
NumberolBC

Function

Cell Name

CMOS Interface Clock Input Buffer (True)

ILC

Cell Symbol
III

to

KCL

0.900

0.006

Propaogatlon Delay ""ramet.
1I:In
to
KCL
KCl2
CDR2

1.550

I

6
Path

XtoCI

0.005

X-{::>--CI

Parlmeter

Pin Name

Input Loading
Factor (Iu)

PinNa_

Output Driving
Factor (Iu)

CI

Symbol

TypI nl) •

200
• Minimum values lor the typical operating concition.
The values lor the worst ease operating condition are given by the maximum dalay
multiplier.

C1o-ILC-EO

3-344

Sheet 1/1

I Page 21-16

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10

• Version
NumberolBC

Funcllon

CMOS Interface Clock Input Buffer (True)
with Pull-up Resistance

ILeU

Cell Symbol
IUP

10

KCL

0.900

0.006

Propagation DeI.y_ Par.m....
IIIn
KCL
KCL2
CDR2
10

1.550

I

6
Path

XtoCI

0.005

X-[::>-CI

Parameter

Pin Name

Inpul Loading
Faclor (Iu)

Pin Name

Oulpul Drlvtng
Faclor (Iu)

CI

Symbol

Typ (no)'

200
• Minimum values lor the typical oparating condition.
The values lor the worsl case operating condition are given by the maximum delay
multiplier.

C1D-ILCU-EO I

SheetH1

I

I Page 21-17
3-345

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

eellName

I • CG10

CMOS Interface Clock Input Buffer (True)
with Pull-down Resistance

fLCD

• Version

I

Function

Cell Symbol
IU

to

KCL

0.900

0.006

Propagation DeIlY P...meter
Idn
KCL2
to
KCL
CDR2

1.550

Number 01 BC

I

6
Path

XloCI

0.005

X-{::>--CI

Parameter

Pin Name

Input Loading
Flctor (Iu)

Pin Name

Outpul Driving
Factor (Iu)

CI

Symbol

TYI>(n.) •

200
• Minimum values lor the typical operating condition.
The values for Ihe worsl case operating condition are given by !he matimum dalay
multiplier.

C1Q-ILCD-EO

3-346

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I Page 21-18

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

f1C

Number 01 BC

CMOS Interiace Input Buffer (Inverter)
Cell Symbol
tup

10

0.600

X

I • CG10 • Version

Function

--[::>0--

KCL

0.017

Propagation Delay Parameler
!dn
KCL
to
KCL2
CDR2

0.100

I

5
Path

Xto IN

0.017

IN

Parameter

Pin Name

Input Loedlng
Foetor (Iu)

Pin Name

Oulpul Driving
Faclor (Iu)

IN

36

Symbol

Typ(ns) •

• Minimum values lor the typical operating condition.
The values lor the worsl case operating condition are given by the maximum delay
multiplier.

C10-11C-EO

Sheet 1/1

I Page 21-19
3-347

..

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
I

I . CG1D

CMOS Interface Input Buffer (Inverter)
with Pull-up Resistance

/1eU

Cell Symbol

lUI'

X

---{:>ao--

to

KCL

0.600

0.017

5

Propagation DeIlY Par.m....
1IIn
·to
KCL
KCL2
CDR2

0.100

• Version
NumberolBC

CellNlme

Path

XtolN

0.017

CI

Paramet..

Pin Name

Input LOIdlng
Fletor(lu)

Pin Name

Output Driving
FlCtor (lu)

IN

36

Symbol

Typ(no) •

• Minimum values lor the typical operating conation.
The values lor the woral case operating conation are given by the maximum delay
multiplier.

C10-ItCU-EO

I

Sheet 111
Page 21-20

3-348

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

"Version
Number 01 Be

CMOS Interface Input Buffer (Inverter)
with Pull-down Resistance

1teD

Cell Symbol
tup

X

I • CG10

Function

---[:>0--

to

KCL

Q.600

0.017

0.100

I

5
Path

XlolN

0.017

IN

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

IN

Propagation Delay Parameter
teln
KCL
10
KCl2
COA2

Symbol

Typ' nl •

36
• Minimum values lor the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

C1Q-11CD-EO

Sheell/1

I Page 21-21
3-349

IDI

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

NumberolBC

Function

Cell Name

12C

CMOS Interface Input Buffer (True)
Cell Symbol

Propagation
!Up

DeI.y Parameter
IIIn

to

KCL

to

KCL

0.575

0.017

0.831

0.023

KCl2

CDR2

I

4
Path

XtolN

X~IN

Parameter

Pin Name

Input Loedlng
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

IN

Symbol

Typ na •

36
• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

C10-12C-EO

3-350

Sheet 1/1

I Page 21-22

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

I

CMOS Interface Input Buffer
with Pull-up Resistance (True)

12CU

Cell Symbol

\Up

X

" CG10 • Version

Function

----{:::>--

to

KCL

0.575

0.017

0.831

1

4
Path

XtolN

0.023

IN

Parameter

Pin Name

Input LOldlng
Factor (Iu)

Pin Name

Output Drlylng
Flctor (Iu)

IN

Propagation DeIlY Plrlmeter
tdn
KCL2
CDR2
to
KCL

Number of BC

Symbol

Typ I ns •

36
• Minimum values lor the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
mUltiplier.

C1 D-12CU-EO

Sheet 1/1

I Page 21-23

3-351

lID

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Function
Cell Name

I "CG10

I

CMOS Interface Input Buffer
with Pull-down Resistance (True)

12CD

Cell Symbol
tup
to

KCL

0.575

0.017

Propagation Delay Parameter
tdn
to
KCL
KCL2
CDR2
0.831

• Version
Number of Be

I

4
Path

XtolN

0.023

X--t:>--IN

Parameter

Pin Name

Input loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

IN

Symbol

Typ (ns)'

36
• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay

multiplier.

C10-12CD-EO

3-352

Sheet 1/1

I

I Page 21-24

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10

Schmitt Trigger Input Buffer
(CMOS Type, Inverter)

11S

• Version

I

Function

Cell Name

Cell Symbol
\Up
to

KCL

2.438

0.067

Propagation Delay Parameter
tdn
·to
KCL
KCL2
CDR2

1.675

Number 01 Be

I

8
Path

XlolN

0.045

X~IN

Parameter

Pin Name

Inpul Loading
Factor (Iu)

Pin Name

Oulput Driving
Faclor (Iu)

IN

Symbol

Typ (ns •

18
• Minimum values lor the typical operating condition.
The values lor the worsl case operating condition are given by lhe maximum delay
multiplier.

C1(}--11S-EO

Sheel1l1

I Page 21-25
3-353

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• CG10 • Version
Number of BC

Function

Cell Name

Schmitt Trigger Input Buffer
(CMOS Type, Inverter) with Pull-up Resistance

11SU

CeIiSymbof
\up

10

KCL

2.438

0.067

Propagation Delay Parameler
Idn
KCL
10
KCL2
CDR2

1.675

I

8
Path

XtolN

0.045

X~IN

Parameter

Pin Name

fnput Loading
Factor (Iu)

Pin Name

OulpUI Driving
Factor (Iu)

IN

Symbol

Typ n• •

18
• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by lhe maximum delay
multiplier.

C1D-11SU-EO

3-354

Sheet 1/1

I

I Page 21-26

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION

I

Cell Name

Function

I • CG10 • Version
I Number 01 BC

Schmitt Trigger Input Buffer
(CMOS Type, Inverteri with Pull-down Resistance

115D

Cell Symbol
1\1

10

KCL

2.438

0.067

Propagltlon Delay Plrlmeler
Idn
10
KCL
KCL2
CDR2

1.675

l

8
Pa!h

XtolN

0.045

X~IN

Parameter

Pin Name

Inpul LOldlng
Faclor (Iu)

Pin Name

OUlpul Driving
Faclor (Iu)

IN

Symbol

Typ n• •

18
• Minimum values for !he Iypical operating condition.
The values for !he worsl case operating condition are given by !he maximum delay
multiplier.

C1 0-11 SO-EO

Sheet 1/1

I Page 21-27
3-355

..

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10

• Version
NumberofBC

Function

Schmitt Trigger Input Buffer
(CMOS Type, True)

128

Cell Symbol
l\Jp
to

KCL

1.550

0.067

Propagation DelaYPlramel..
tdn
to
KCL
KCl2
CDR2

1.925

I

8
Path

Xto IN

0.056

X~IN

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

IN

Symbol

Typ (nl)'

18
• Minimum values for the typical operating condition.
The values lor the worst case operating condition ere given by the maximum delay
multiplier.

C1o-I25-EO

3-356

Sheet 1/1

I Page 21-28

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• Version
Number of Be

Function

Cell Name

Schmitt Trigger Input Buffer
(CMOS Type, True) with Pull-up Resistance

12SU

Cell Symbol

ProjlaaaUon DeIlY Parameter
!dn

tup
to

KCL

to

KCL

1.550

0.067

1.925

0.056

KCL2

CDR2

I

8
Path

XtolN

X~IN

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

IN

Symbol

Typ, na •

18
• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

C10-12SU-EO

I

Sheet 111

I

I Page 21-29
3-357

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function

Cell Name

I " CG10 • Version
t Number of BC

Schmitt Trigger Input Buffer
(CMOS Type, True) with Pulklown Resistance

1280

Cell Symbol

tu
to

KCL

1.550

0.067

Propagation Delay Paramet..
IIIn
·to
KCL
KC1.2
COR2

1.925

I

8
Path

Xlo IN

0.056

X~IN

Parameter

Pin Name

Input Loading
Factor (Iu)

Pin Name

Output Driving
Factor (Iu)

IN

Symbol

Typ ,ns •

18
• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

C10-12SD-EO

3-358

Sheel1/1

I Page 21-30

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10 • Version
I

Function

Cell Name

Schmitt Trigger Input Buffer
(TTL Type, Inverter)

11R

Cell Symbol
tup
to

2.800

KCL

0.067

Propagation Delay Perameter
IIln
to
KCL
KCl2
CDR2

1.475

Number 01 Be

I

8
Path

Xto IN

0.045

X~IN

Parameter

Pin Nama

Input Loading
Foetor (Iu)

Pin Name

Output Driving
Factor (Iu)

IN

Symbol

Typ(ns) •

18
• Minimum values for the typical operating conation.
The values for the worst case operating condition are given by the maximum delay
multiplier.

C1 0-11 R-EO

Sheet 1/1

I Page 21-31

3-359

IDI

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10

Function

Cell Name

Number 01 BC

Schmitt Trigger Input Buffer
(TTL Type, Inverter) with Pull-up Resistance

11RU

• Version

Cell Symbol
!Up
to

2.800

KCL

0.067

Propagation Delar P.rameter
!dn
KCL
KCL2
CDR2
to

1.475

I

8
Path

XtolN

0.045

X~IN

Parameter

Pin Name

'nput Loading
Factor ('u)

Pin Name

Output Dr'vlng
Factor (Iu)

IN

Symbol

TYPln• •

18
• Minimum values lor the typical operadng condidon.
The values lor the worst case operadng condition are given by the maximum delay
mUldplier.

C1o-I1RU- EO

3-360

Sheet 1/1

I Page 21-32

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I • CG10

Schmitt Trigger Input Buffer
(TTL Type, Inverter) with Pull-down Resistance

11RO

• Version

I

Function

Cell Symbol
!Up

10

KCL

2.800

0.067

Pr-X

Parameter

Pin Name

Symbol

TYPln• •

Inpul Loading
Flclor (Iu)

2

OT

PinNlme

Oulpul Driving
Faclor (Iu)
• Minimum values lor the typical operating condition.
The values lor \he worsl case operating condition are given by the maximum delay
multiplier.

Note: 1. The unit of KCL is nslpF.
2. Output load capacitance of 60 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.

C1Q-01B-EO

Sheel1/1

I

I Page 21-37

3-365

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Funcllon

01BF

I • CG10 • Version
I Number 01 BC

Output Buffer (IOL=8mA, Inverter)
Cell Symbol

tu
10

KCL

0.850
(3.01)

0.036

Propagallon Delay Parameler
Idn
KCL
KCl2
COR2
10

0.980
(3.32)

I

3
Path

OTto X

0.039

OT--{>-X

Paramet ..

Pin Name

OT

Symbol

Typ ns •

Inpul Loading
Faclor Clu)

2

Pin Name

Oulpul Driving
FaclorClu)
• Minimum values lor the typical operating condition.
The values lor the worsl case operating condition are given by lhe maximum delay
multiplier.

Note: 1. The unit of KCL is nslpF.
2. Output load capacHance of 60 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the Simulation.

C1Q-01BF-EO I

3-366

Sheet 1/1

I Page 21-38

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I . CG10

• Version
Number 01 BC

Funcllon

01L

Power Output Buffer (IOl= 12mA. Inverter)
Cell Symbol

lup
to

KCL

0.870
(2.31)

0.024

Propagation Delay Parlmeter
1I:In
to
KCL
KCL.2
CDR2

1.100
(2.66)

I

3
Path

OTto X

0.026

OT----{>-X

Parameler

Pin Name

OT

Symbol

Typ(n.) •

Input LOlding
Factor (Iu)

2

Pin Name

Output Driving
Factor (Iu)

• Minimum values for the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Note: 1. The unit 01 KCL is ns/pF.
2. Output load capacHance 01 60 pF is used lor Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

C10-01L-EO j

Sheet 1/1

I

I Page 21-39
3-367

IDII

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Nam.

I • CG10 • Version

Funcllon

NumberolBC

Output Buffer (IOL=3.2mA, Inverter)
with Noise Limit Resistance

01R

Cell Symbol
IUp

10

1.nO
(3.93)

KCL

0.036

Propagallon Delay Parameler
ttln
. 10
KCL
KCL2
CDR2

4310
(9.11)

I

5
Path

OTto X

0.080

OT--{)o-X

Parameter

Pin Name

OT

Symbol

Tvp, na)'

Inpul Loading
Faclor (Iu)

1

Pin Name

OUlpul Driving
Factor (Iu)
• Minimum values lor the typical operating condition.
The values for the worst case operating condition are given by the maximum delay
multiplier.

Note: 1. The unit of KCL is nslpF.
2. Output load capacHance of 60 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

Cl0-01R-E

3-368

Sheet 1/1

I Page 21-40

I • CG10 • Version
I Number 01 Be

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Funcllon

Output Buffer (IOL=8mA, Inverter)
with Noise Limit Resistance

01RF

Cell Symbol

Propagallon Delay
Idn

IU

10

KCL

10

KCL

1.824
(3.99)

0.036

5.013

0.044

P.ram ...
CDR2

KCL2

I

5
Path

OTto X

(7.66)

OT-[>--X

Paramet ..

S~1I'bol

Typlno}·

Inpul Loading
Faclor(lu)

Pin Name

OT

1

OulpUI Driving
Faclor (Iu)

Pin Name

• Minimum values for the typical operating oondition.
The values for the worsl case operating oondition are given by the maximum delay
multiplier.

Note: 1. The unit 01 KCL is ns/pF.
2. Output load capacnance 01 60 pF is used lor Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

C10-01RF-EO

I

Sheet 1/1

I

I Page 21-41
3-369

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

J • CG10 • Version
NumberolBC

Function

CeIiHame

Power Output Buffer (IOl=12mA, Inverter)
with Noise limit Resistance

015

Cell Symbol
tup
to

KCL

1.992
(3.44)

0.024

Propagation Delay Parlmeter
IIIn
KCL
KCL2
CDR2
to

5.660
(7.70)

I

5
Path

OTto X

0.034

OT-l>-X

Parameter

Pin Name

Symbol

Typ{nl) •

Input Loading
Factor (Iu)

1

OT

Pin Name

Output Drlvlng
Factor (Iu)

• Minimum values for the Iypical operating oondition.
The values for the worst case operating oondition are given by the maximum delay
multiplier.

Note: 1. The unit 01 KCL is ns/pF.
2. Output load capacHance 01 60 pF is used lor Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

C10-015-EO

3-370

Sheet 111

I Page 21-42

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

028

• Version

I

Function

Output Buffer (IOL=3.2mA, True)
PropagaUon Delay Parameter
IIIn

Cell Symbol
!Up
to

0.500
(2.66)

KCL
0.036

to

0.803
(5.55)

KCL
0.079

CDR2

KC12

Number of Be

I

2
Path

OTtoX

OT-t>-X

Parameter

Pin Name

OT

S)'mbol

Typ(ns) •

Input Loading
Factor (Iu)

6

Pin Name

Output Driving
Flctor (Iu)
• Minimum values for the typical operating condition.
The values for the worsl case operating condition are given by the maximum delay
multiplier.

Note: 1. The unit of KCLis nslpF.
2. Output load capacitance of 60 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

C10-02B-EO

Sheet 111

I Page 21-43

3-371

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I • CG10 • Version

J

FuneUon

Cell Name

02BF

Output Buffer (IOL=8mA, True)
Cell Symbol
til

10

0.590
(2.75)

KCL

0.036

PropagaUon Delay Pa..m....
1IIn
10
KCL
CDR2
KCL2

0.773
(3.12)

Number 01 BC

I

2
Path

OTto X

0.039

OT-{>-X

P.ram....

Pin Nama

Input Loading
Faelor(lu)

OT

6

PlnNlma

Output Driving
Flclor (Iu)

Symbol

Typ n••

• Minimum values for the typical operating condition.
The values for the worst case operating condition ere given by the maximum delay
multiplier.

Note: 1. The unit of KCL is nslpF.
2. Output load capacnance of 60 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.

C1G-02BF-EO

3-372

Sheet 1/1

I Page 21-44

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

02L

I . CG10

• Version
Number 01 BC

Function

Power Output Buffer (IOL=12mA, True)
Cell Symbol
tup
to

KCL

0.610
(2.05)

0.024

PropagaUon DeIlY Plrlmel..
!dn
·to
KCL
KCl2
COA2

0.893
(2.46)

I

2
Path

OTtoX

0.026

OT-{>-X

Parameter

Pin Name

OT

Symbol

Typ(ns) •

Input Loading
Factor (Iu)

6

Pin Name

Outpul Driving
Faclor (Iu)
• Minimum values for the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

Nole: 1. The unit of KCL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

C10-02L-EO

Sheet 1/1

I Page 21-45
3-373

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nom.

I • CG10 • Version
Number of Be

FUnction

Output Buffer (IOL=3.2mA. True)
with Noise Limit Resistance

02R

Cell Symbol
tup
to

KCL

1.383
(3.55)

0.036

Propagation DelayParamet..
IIIn
KCL
to
KCl2
CDR2

3.335
(8.14)

I

4
Path

OTto X

0.080

OT---{>-X

Parameter

Pin Name

OT

IIDI

Symbol

Typ (ns)'

Input Loading
Factor (Iu)

2

Pin Name

Output Driving
Factor (Iu)

• Minimum values for the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

Note: 1. The unit of KCL is nslpF.
2. Output load capacHance of 60 pF is used for Fujitsu's logiC simulation.
3. The parameters in parentheses are the values applied to the simulation.

ClO-C2R-EO

3-374

Sheet 111

I Page 21-46

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

J • CG10 • Version
Number 01 BC

Function

Output Buffer (IOL=8mA. True)
with Noise Limit Resistance

02RF

Cell Symbol

tup
10

KCL

1.437
(3.60)

0.036

4
Propagation DeIlY Parameter
Idn
KCL
10
KCl2
CDR2

4.038
(6.68)

Path

OTto X

0.044

OT-[>-X

Parameter

Pin Name

Input Loading
Faclor (Iu)

OT

2

Pin Name

OUlput Driving
Faclor (Iu)

Symbol

Typ (no)'

• Minimum values for Ihe typical operating condition.
The values for Ihe worst case operating condition are given by the maximum delay
multiplier.

Note: 1. The unit of KCL is ns/pF.
2. Outpulload capacitance of 60 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simuiation.

C10-02RF-EO

Sheet 1/1

I

I Page 21-47
3-375

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
CeIlNlme

1

~•

CG10 • Version

I

Function

Power Output Buffer (IOL=12mA, True)
with Noise Umit Resistance

025

Cell Symbol
III

to

KCL

1.605
(3.05)

0.024

Propagation DeIlY Plramet..
IeIn
KCL
to
KCl2
CDR2

4.685
(6.73)

Number 01 BC

I

4
Path

OTto X

0.034

OT-[>--X

Par.meler

Pin Name

OT

Symbol

Tvp nl •

Input loading
Flctor (Iu)

2

Pin Name

Output Driving
Factor (Iu)
• Minimum values lor the typical operating condition.
The values lor the worst case operating condition are given by the maximum delay
multiplier.

Note: 1. The unit of KCL is nslpF.
2. Output load capacHance of 60 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.

C1G-02&-EO J

3-376

Sheet 1/1

J

I Page21-48

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number 01 BC

Function

04T

I

Tri-state Output Buffer (IOL=3.2mA, True)
Cell Symbol
III

to

KCL

0.639
(2.98)

0.036

Propagation Delay Parameter
tdn
KCL
KCL2
CDR2
10

1.460
(6.66)

4
Path

OTtoX

0.080

my'
C
ZtoL

LtoZ

1.780
(13.97)

Pin Name

Input Loading
Factor (Iu)

OT
C

6
2

Oulpul Driving
Faclor (Iu)

KCL

1.170
(6.57)

0.083

KCL

to

2.120
(13.97)

KCL

0.700
(6.57)

0.037

CtoX

Zto H

HtoZ
to

Pin Name

.

to

KCL

to

.

III

• These values are subject to external loading condition.
Measurement circuHs of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

DI ,-""
LSI

LSI

,Ic
(a) Measurement of tpd at LZ and ZL.

1c
,I

~

?-

R= 2kQ

",'"r7

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL is nslpF.
2. Output load capacHance of 65 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1C>-04T-EO

Sheet 1/1

I Page 21-49

3-377

..

I . CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Function

Call Nam.

04TF

I

Tn-state Output Buffer (IOL=8mA, True)
Call Symbol

Propagation Delay Parameter
tu

tdn

KCL

10

0.693
(3.04)

0.036

KCL

'10

2.343
(5.21)

KCL2

Number 01

BC

4
Path

CDR2

OTtoX

0.044

a'-t('
C

KCL

2.140
(15.68)

Pin Nam.

Input Loading
Factor (lu)

OT
C

6
2

.

10

KCL

1.575
(4.44)

0.044

KCL

10

KCL

0.700
(4.44)

0.037

HIDZ
10

2.120
(15.68)

Oulpul Driving
Faclor (Iu)

Pin Name

ZIDL

LtoZ
10

CtoX

ZIDH

.

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ. ZL. HZ and ZH are as follows:

DI.."n
LSI

LSI

lc

,1

,lC
(a) Measurement of tpd at LZ and ZL.

~

R.2kn

.1~Jn.

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL is nslpF.
2. Output load capacitance of 65 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

C1Q-04TF-EO I

3-378

Sheet 1/1

I

I Page 21-50

I • CG10 " Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number of BC

Function

04W

I

Power Tri-state Output Buffer (IOL=12mA, True)
Cell Symbol

!Up
KCL

10

0.804
(2.37)

0.024

Propagation Delay Parameter
tdn
10
KCL2
CDR2
KCL

2.620
(4.83)

4
Path

OTto X

0.034

my'
C
ZroL

LloZ
KCL

10

2.560
(16.44)

.

to

KCL

1.219
(4.60)

0.052

KCL

10

KCL

0.800
(4.60)

0.025

CtoX

Input Loading
Factor (Iu)

Pin Name

6
2

OT
C

Output Driving
Factor (Iu)

Pin Name

ZroH

HloZ
to

2.540
(16.44)

.

ID

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at 12, ZL, HZ and ZH are as follows:

DI

,.,.0
LSI

LSI
,IC

(a) Measurement of tpd at 12 and ZL.

1,

.•

R-2kn

m,"

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL is ns/pF.
2. Output load capacitance of 65 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1D-04W-EO

I

Sheet 1/1

I Page 21-51
3-379

I • CG10 • Version
I Number 01 BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

I

Tri-state Output Buffer (IOl=3.2mA, True)
with Noise limit Resistance

04R

Propagation Delay Parameter

Cell Symbol

tup

Ill"

to

KCL

to

KCL

un

0.036

3.190
(8.39)

0.080

(3.52)

my

KCL2

5
Path

CDR2

OTto X

x

c
ZtoL

LtoZ
KCL

to

1.730
(13.91)

KCL

3.575
(8.97)

0.083

KCL

to

KCL

1.300
(8.97)

0.037

CtoX

Input Loading
Factor (Iu)

Pin Name

2
2

OT
C

HtoZ
to

Output Driving
Factor (Iu)

Pin Name

lID

.

to

1.860
(13.91)

ZtoH

.

• These values are subject to extemalloading condition.
Measurement circuns of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

~. ,.,,0
LSI

l,C

(a) Measurement of tpel at LZ and ZL.

LSI

1,

~

R= 2kn

"'77

(b) Measurement of tpel at HZ and ZH.

Note: 1. The unit 01 KCL is ns/pF.
2. Output load capacitance of 65 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C10-04R-EO

3-380

Sheel1/1

I Page 21-52

L• CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

• Version

I

Function

Tri-state Output Buffer (IOL=8mA, True)
with Noise Limit Resistance

04RF

Cell Symbol
1u

to

KCL

1.231
(3.57)

0.036

Propagallon Delay Per.meter
IIIn
to
KCL
KCl2
CDR2

4.073
(6.94)

Number 01 BC

I

5
Path

OTto X

0.044

my'
C

ZtoL

LtoZ
KCL

.

to

KCL

3.980
(6.84)

0.044

to

KCL

to

KCL

1.860
(15.61)

.

1.300
(6.84)

0.037

to

2.240
(15.61)

CtoX

Input Loading
FlCtor (Iu)

Pin Name

OT

2
2

C

HtoZ

Output Drlvtng
Factor (Iu)

Pin Name

ZtoH

• These values are subject to extemalloading condition.
Measurement circuns of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

DI

,.,,0

LSI

LSI

,rc

(a) Measurement of tpel at LZ and ZL.

-1 ..
,rc

R=2kO

rTln

(b) Measurement of tpel at HZ and ZH.

Note: 1. The unn of KCL is ns/pF.
2. Output load capacnance of 65 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C10-04RF-EO

Sheet 111
Page 21-53

3-381

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

"Version
Number 01 BC

Function

Cell Name

I

Power Tri-state Output Buffer (IOL=12mA, True)
with Noise Limit Resistance

04S

Cell Symbol

Propagation Delay Parameter

!dn

!up

10

KCL

10

KCL

1.477
(3.04)

0.024

4.770
(6.98)

0.034

Path

CDR2

KCL2

5

OTtoX

O'Y'
C

LloZ

.

KCL

3.759
(7.14)

0.052

10

KCL

to

KCL

2.290
(16.37)

.

1.400
(7.14)

0.025

2.600
(16.37)

Pin Name

Input Loading
Faclor (Iu)

OT
C

2
2

C to X

Zle H

H leZ

OUlPUI Driving
Faclor (Iu)

Pin Name

Zle L
10

KCL

10

• These values are subject to extemalloading condition.
Measurement circuits of propagation delay time
at LZ, ZL. HZ and ZH are as follows:

DI ,., "
LSi

LSI

~c

~

(a) Measurement oftpd at LZ and ZL.

Note: 1. The unit of

KCL

R=2kO

Ic

",77

(b) Measurement oftpd at HZ and ZH.

is nS/pF.

2. Output load capacitance of 65 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1D-045-EO

3-382

Sheet 1/1

I Page 21-54

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

• CG10 • Version

I

Function

Power Output Buffer (IOL=24mA, True)
with Noise Limit Resistance

0252

Cell Symbol
IUp

10

KCL

2.625
(3.65)

0.017

Propagation DeIlY Parlmeler
IIln
KCL
KCL2
COR2
10

9.765
(11.99)

Number 01 BC

I

6
Path

OTtoX

0.037

OT-t>- X

Parameter

Pin Name

Inpul LOldlng
Faclor (Iu)

OT

2

Pin Name

Oulpul Driving
Faclor (Iu)

Symbol

Typ n5)'

• Minimum values lor !he Iypical operating condition.
The values for !he worsl case operating condition are given by the maximum delay
multiplier.

Nole: 1. The unit 01 KCL is nSlpF.
2. Output load capacnance 01 60 pF is used lor Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

C1D-02S2-EO

I

Sheet 1/1

I

I Page 21-103
3-383

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nam.

Number 01 BC

Function

I

Power Tri-state Output Buffer (IOL=24mA. True)
with Noise Limit Resistance

0452

Propagation Delay Parameler

Cell Symbol
!Up

\dn

10

KCL

10

KCL

KCL2

3.050
(4.16)

0.017

10.400
(12.81)

0.037

7
Palh

CDR2

OTtoX

mT'
C

L10Z

ZIOL

10

KCL

10

KCL

4.800
(18.52)

.

9.005
(11.67)

0.041

KCL

10

KCL

2.000
(11.67)

0.020

CtoX

Inpul Loading
Faclor (Iu)

Pin Nam.

2
2

OT

c

H toZ
10

Oulpul Driving
Faclor (Iu)

Pin Nam•

3.620
(18.52)

ZtoH

.

• These values are subject to external loading condition.
Measurement circuns of propagation delay time
at LZ. ZL. HZ and ZH are as follows:

c:rI

'.H"
LSI

LSI

1c

..~

R=2kO

,IC
,I

(a) Measurement of tpel at LZ and ZL.

min

(b) Measurement of tpel at HZ and ZH.

Note: 1. The unit of KCL is nslpF.
2. Output load capacitance of 65 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
Cl()....()4S2-EO

3-384

Sheet 1/1

I Page 21-104

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

"Version
Number of BC

Function

H6T

I

Tn-state Output & Input Buffer (IOL=3.2mA, True)
Cell Symbol
\Up

"=tr-

OT

to

KCL

0.663
0.639
(3.70)

0.017
0.036

Propagation Delay Parameter
Idn
KCL2
· to
KCL
CDR2

1.150
1.460
(8.26)

8
Path

XtolN
OTto X

0.023
0.080

X

C

Zte L

LtoZ
to

KCL

to

KCL

·

1.170
(8.23)

0.083

to

KCL

to

KCL

2.120
(17.72)

·

0.700
(8.23)

0.037

1.780
(17.72)

Pin Name

Input Loading
Factor Clu)

OT
C

6
2

H teZ

Pin Name

Output Driving
Factor Clu)

IN

36

CtoX

ZtoH

• These values are subject to external loading condition.
Measurement circuits of propagation delay lime
at LZ, ZL, HZ and ZH are as follows:

DI

,.,,0

LSI

LSI

,1

,IC

(a) Measurement of tpc! at LZ and ZL.

Note: 1. The unij of

1c .

R=2kil

rn77

(b) Measurement of tpc! at HZ and ZH.

KCL for paths OT, C to X is nslpF.

2. Output load capacitance of 85 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.
C1Q-H6T-EO

Sheet 1/1

I Page 21-55
3-385

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• Version

Function

Cell Name

Number 01 BC

I

Tn-state Output & Input Buffer (IOL=3.2mA, True)
with Pull-up Resistance

H6TU

Cell Symbol
tup

"~

OT

to

KCL

0.663
0.639
(3.70)

0.017
0.036

Propagation Delay Parameter
!dn
to
KCL
KCL2
CDR2

1.150
1.460
(8.26)

8
Path

XtolN
OTto X

0.023
0.080

X

C

ZtaL

LtoZ

.

to

KCL

1.780
(17.72)

Pin Name

Input Loading
Factor (Iu)

OT
C

6
2

Pin Name

Output Driving
Factor (Iu)

IN

36

1.170
(8.23)

2.120
(17.72)

CtoX

0.083

ZtoH

HtoZ
to

KCL

to

KCL

to

.

0.700
(8.23)

KCL

0.037

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

CJI ,_.

0

LSI

LSI

I

C

(a) Measurement of tpd at LZ and ZL.

Note: 1. The

un~

1,

~

Rc2kO

",'n

(b) Measurement of tpd at HZ and ZH.

of KCL for paths OT, C to X is nslpF.

2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1CHi6TU-EO

3-386

Sheet 1/1

I Page 21-56

I • CG10 • Version
I Number 01 BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

Function

I

Tn-state Output & Input Buffer (IOL=3.2mA, True)
with Pull-

R=2kO

",77

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT. C to X is nslpF.
2. Output load capac~ance of 85 pF is used for

Fuj~su's

logic simulation.

3. The parameters in parentheses are the values applied to the simulation.
C1O-H6CF-EO I

Sheet 1/1

I

I Page 21~7
3-397

I • CG10 • Version
I Number 01 BC
Tn-state Output & CMOS Interface Input Buffer (IOL=8mA, True)1
8
with Pull-up Resistance

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
j

Cell Name

H6CFU

Function

Cell Symbol
rup

"~

OT

to

KCL

0.575
0.693
(3.76)

0.017
0.036

Propagation Delay Parameter
!dn
to
KCL
KCL2
COR2

0.831
2.343
(6.09)

Path

XtolN
OTto X

0.023
0.044

X

C
LtoZ
to

Inpul Loading
Faclor(lu)

OT
C

4
2

KCL

to

.

2.140
(19.83)

Pin Name

ZtoL
KCL

1.575
(5.32)

HtoZ
10

Pin Name

OUlpul Driving
Faclor (Iu)

IN

36

2.120
(19.83)

CloX

0.044

Zlo H
KCL

KCL

10

.

0.700
(5.32)

0.037

• TheSe values are subject to external loading condition.
Measurement circuits of propagation delay time
atll, Zl, HZ and ZH are as follows:

04

,_,,0

LSI

LSI

lc

~

R_an

,Ic
,I
(a) Measurement oltpel at I I and Zl.

n:fn

(b) Measurement of tpel at HZ and ZH.

Note: 1. The unit 01 KCL for paths OT, C to X is nslpF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simutation.
C1~H6CFU-EO

3-398

Sheet 1/1

I Page 21-68

I • CG10 • Version
I Number 01 Be
Tn-state Output & CMOS Interface Input Buffer (IOL=8mA. True)
8
with Pull-down Resistance

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Function

Cell Name

H6CFD

Cell Symbol
!up

"=tr-

OT

10

KCL

0.575
0.693
(3.76)

0.017
0.036

Propagation Delay Per.meter
Idn
KCL
KCl2
CDR2
10

0.831
2.343
(6.09)

Path

XtoiN
OTtoX

0.023
0.044

X

C

LtoZ

to

.

2.140
(19.83)

Pin Name

Inpul Loading
Faclor (Iu)

OT
C

4
2

ZIDL

10

KCL

HroZ

10

Pin Name

Oulpul Driving
Faclor (Iu)

IN

36

2.120
(19.83)

KCL

CtoX

0.044

1.575
(5.32)

ZID H

10

KCL

.

KCL

0.700
(5.32)

0.037

Ell

• These values are subject to extemalloading condition.
Measurement circu~s of propagation delay time
at LZ. ZL, HZ and ZH are as follows:

D!

R.,.n

LSI

LSI

I

C

(a) Measurement of tpel at LZ and ZL.

Note: 1. The

un~

-1
I

~

R=2k{l

?>
C

n:frf

(b) Measurement of tpel at HZ and ZH.

of KCL for paths OT, C to X is nslpF.

2. Output load capac~ance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1Q-H6CFD-EO

Sheet 1/1

l Page 21~9
3-399

I • CG10 • Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell N.me

I

Function

I

Power Tri-state Output & CMOS Interface
Input Buffer (IOL=12mA, True)

H6E

Cell Symbol
III

"=tr-

OT

to

KCL

0.575
0.804
(2.85)

0.017
0.024

Propagation DeI.y Parameter
IIIn
. to
KCL
KCL2
COR2

0.831
2.620
(5.51)

8
Path

XtolN
OTto X

0.023
0.034

X

C

LtoZ

Input Loading
Factor (Iu)

OT
C

6
2

Output Driving
Factor (Iu)

IN

36

2.540
(20.71)

CtoX

KCL

0.052

1.219
(5.64)

HtoZ
to

Pin Name

to

.

2.560
(20.71)

Pin Name

ZtoL
KCL

to

ZtoH
KCL

to

.

0.800
(5.64)

KCL

0.025

• These values are subject to external loading condition.
Measurement circuns of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

DI'"""
LSI

LSI

~C

(a) Measurement of tpd at LZ and Zl.

1,

..

R-2kO

min

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is nsipF.
2. Output load capacitance of 85 pF is used lor Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.
C1o-H6E-EO I

3-400

Sheet 1/1

I Page 21-70

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

I

Function

H6EU

Propagation Delay Per.meter
ttln
to
KCL
KCl2
CDR2

Cell Symbol

tu

"~

OT

to

KCL

0.575
0.804
(2.85)

0.017
0.024

0.831
2.620
(5.51)

Number of BC

I

Power Tri-state Output & CMOS Interface
Input Buffer (IOL=12mA, True) with Pull-up Resistance

8
Path

XtolN
OTto X

0.023
0.034

X

C

LtoZ
to

Input Loading
Factor (Iu)

OT
C

6
2

KCL

to

.

2.560
(20.71)

Pin Name

ZtoL
KCL

H toZ
to

Pin Name

Output Driving
Factor (Iu)

IN

36

2.540
(20.71)

CtoX

0.052

1.219
(5.64)

ZtoH
KCL

KCL

to

.

0.800
(5.64)

0.025

• These values are subject to external loading condition.
Measurement circuHs of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

DI

,.,.0
LSI

LSI

l,

l,c

(al Measurement of tpd at LZ and ZL.

Ie

~
~

Rc2kQ

n+rT

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unH of KCL for paths OT, C to X is nslpF.
2. Output load capacHance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C10-H6EU-EO

Sheet 1/1

I Page 21-71
3-401

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

I

Function

H6ED

Cell Symbol

Propagation Delay Parameter
IIln
KCL
KCL2
CDR2
to

tup

"~

OT

to

KCL

0.575
0.804
(2.85)

0.017
0.024

0.831
2.620
(5.51)

Number 01 BC

I

Power Tri-state Output & CMOS Interface
Input Buffer (IOL=12mA. True) with Pull-down Resistance

8
Path

XtolN
OTto X

0.023
0.034

X

C

LtoZ
to

.

2.560
(20.71)

Pin Name

Input Loading
Factor (Iu)

OT
C

6
2

ZtoL
to

KCL

HtaZ
to

Pin Name

Output Drlvlng
Factor (Iu)

IN

36

2.540
(20.71)

CtoX

KCL

0.052

1.219
(5.64)

Zto H
to

KCL

.

KCL

0.800
(5.64)

0.025

• These values are subject to external loading condition.
Measurement circuns of propagation delay time
at LZ. ZL. HZ and ZH are as follows:

DI

""0

LSI

LSI

,I

,LC
(a) Measurement of tpd at LZ and ZL.

lc .•

R=2kO

m'7r

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unn of KCL for paths OT, C to X is nsipF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C10-H6ED-EO

3-402

Sheet 1/1

I Page 21-72

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

Function

Number 01 BC

Tri-state Output & Schmitt Trigger Input Buffer
(IOL=3.2mA. CMOS Type. True)

H6S

Cell Symbol
!Up

'"=tr-

OT

to

KCL

1.550
0.639
(3.70)

0.067
0.036

12

Propagation Delay Parameter
IIln
to
KCL
KCL2
CDR2

1.925
1.460
(8.26)

Path

XlolN
OTloX

0.056
0.080

X

C

LtoZ

.

1.780
(17.72)

Pin Name

Input Loading
Factor (Iu)

OT
C

6
2

ZtoL
KCL

to

to

KCL

1.170
(8.23)

0.083

Zte H

HteZ
to

Pin Name

Output Driving
Factor (Iu)

IN

18

2.120
(17.72)

CloX

KCL

.

to

KCL

0.700
(8.23)

0.037

• These values are subject 10 exlernalloading condition.
Measurement circuits of propagation delay lime
at LZ. ZL. HZ and ZH are as follows:

DI

,."n
LSI

LSI
,IC

(a) Measurement of tpd at LZ and Zl.

l'

:

R=2k{l
~

mw

(b) Measurement of tpd at HZ and 2H.

Note: 1. The unit of KCL for paths OT. C to X is nSlpF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1o-H6S-EO

Sheet 111

1

I Page 21-73
3-403

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

I

Function

Tri-state Output & Schmitt Trigger Input Buffer
(IOL=3.2mA, CMOS Type, True) with Pull-up Resistance

H6SU

Cell Symbol

Propagation Delay Parameler
Idn
CDR2
to
KCL
KCL2

tu

"~

OT

to

KCL

1.550
0.639
(3.70)

0.067
0.036

1.925
1.460
(8.26)

Number of BC

1

12
Path

XtolN
OTto X

0.056
0.080

X

C
ZtoL

LtoZ
to

KCL

.

1.780
(17.72)

Pin Name

Input Loading
Flctor (Iu)

OT
C

6
2

Output Driving
Flctor (Iu)

IN

18

KCL

1.170
(8.23)

0.063

2.120
(17.72)

CtoX

Zto H

HtoZ
to

Pin Name

to

KCL

.

to

KCL

0.700
(8.23)

0.037

• These values are subject to external loading condition.
Measurement circuits 01 propagation delay time
at LZ. ZL. HZ and ZH are as lollows:

Gi'·"O

LSI

LSI

,IC

(a) Measurement of tpd at LZ and ZL.

Nole:

l'

"

".

R~2kQ

min-

(b) Measurement of tpd at HZ and ZH.

1. The unH 01 KCL for paths OT, C to X is nslpF.
2. Output load capacHance 01 85 pF is used lor Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.

C1Q-H6SU-EO

3-404

I

Sheet 1/1

I Page 21-74

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

Numbarof BC

Function

Cell N8me

I

Tri-state Output & Schmitt Trigger Input Buffer
(IOL=3.2mA, CMOS Type, True) with Pull-down Resistance

H6SD

Cell Symbol

tup

"~

OT

to

KCL

1.550
0.639
(3.70)

0.067
0.036

Propagation Delay Parameter
Idn
KCL
COR2
to
KCl2

1.925
1.460
(8.26)

12
Path

XtolN
OTto X

0.056
0.080

X

C
LtoZ

.

1.780
(17.72)

Pin Name

Input Loading
Factor (Iu)

OT
C

6
2

ZtoL
KCL

to

to

KCL

1.170
(8.23)

0.083

ZtoH

H toZ
to

Pin Name

Output Driving
Factor (Iu)

IN

18

2.120
(17.72)

CtoX

KCL

.

to

KCL

0.700
(8.23)

0.037

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

D!

,.,.n

LSI

LSI
,IC

(a) Measurement of tpd at LZ and ZL.

Note: 1. The unit of

KCL for

1,

•

R.2kO

rr.77

(b) Measurement of tpd at HZ and ZH.

paths OT, C to X is nSipF.

2. OUtput load capacitance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C10-H8SD-EO

Sheet 1'1

I

I Page 21-75

3-405

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

• Version

I

Function

H6R

Cell Symbol

Propagation Delay Parameter
tdn
to
KCL
COR2
KCL2

tup

'"=tr-

OT

to

KCL

1.400
0.639
(3.70)

0.067
0.036

2.325
1.460
(8.26)

Number 01 Be

I

Tri-state Output & Schmitt Trigger Input Buffer
(IOL=3.2mA. TTL Type. True)

12
Path

XtolN
OTto X

0.073
0.080

X

C

LtoZ

.

1.780
(17.72)

Pin Name

Input Loading
Factor (lu)

OT
C

6
2

ZtoL
KCL

to

to

KCL

1.170
(8.23)

0.083

ZtoH

HtoZ
to

Pin Name

Output Driving
Factor (Iu)

IN

18

2.120
(17.72)

CtoX

.

KCL

to

KCL

0.700
(8.23)

0.037

• These values are subject to external loading condition.
Measurement circuHs of propagation delay time
at LZ. ZL. HZ and ZH are as fOllows:

04

'.Hn
LSI

LSI
,IC

(a) Measurement 01 t~ at LZ and ZL.

l'

•

•

Rc 2kO

,.,..'77

(b) Measurement 01 tpel at HZ and ZH.

Note: 1. The unit 01 KCL for paths OT. C to X is ns/pF.
2. Output load capacitance 0185 pF is used lor Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.
C1D-H6R-EO

3-406

Sheel1/1

I Page 21-76

Cell

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function
Name
I

• Version
Number of BC

Tri-state Output & Schmitt Trigger Input Buffer
(IOL=3.2mA, TIL Type, True) with Pull-up Resistance

H6RU

Cell Symbol
!Up

to
1.400
0.639
(3.70)

"~

OT

KCL
0.067
0.036

12

Propagation Delay Paramel ..
Idn
to
KCL
KCL2
CDR2
0.073
2.325
1.460 0.080
(8.26)

Path

XtolN
OTto X

X

C
LtoZ
to

ZtoL
KCL

to

.

1.780
(17.72)

KCL
0.083

1.170
(8.23)

CtoX

Input Loading
Factor (Iu)

Pin Name

6
2

OT

C

HtoZ

ZtoH
KCL

Pin Name

Output Driving
Factor (Iu)

IN

18

2.120
(17.72)

.

to

KCL

0.700
(8.23)

0.037

• These values are subject to external loading condition.
Measurement circuijs of propagation delay time
atU, ZL, HZ and ZH are as follows:

DI
LSI

,-,,0
LSI

,Lc

(a) Measurement of tpd atU and ZL.

lc
,I

,..

R~2kO

n-.fn

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unij of KCL for paths OT, C to X is nslpF.
2. Output load capacijance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1D-H6RU-EO

Sheet 1/1

l Page 21-n
3-407

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Neme

I

• Version

Function

Number 01 BC

Tri-state Output & Schmitt Trigger Input Buffer
(IOL=3.2mA, TIL Type, True) with Pull-down Resistance

H6RD

Cell Symbol

Propagation Delay Parameler
Idn
10
KCL
KCl2
COR2

tu

"~

OT

10

KCL

1.400
0.639
(3.70)

0.067
0.036

12

2.325
1.460
(8.26)

Palh

XtolN
OTto X

0.073
0.080

X

C
LtoZ

10

.

1.780
(17.72)

Pin Name

Inpul Loading
Factor (Iu)

OT
C

6
2

ZtoL
KCL

10

KCL

1.170
(8.23)

0.083

H toZ
to

Pin Name

Output Driving
Factor (Iu)

IN

18

2.120
(17.72)

CtoX

ZtoH
KCL

.

10

KCL

0.700
(8.23)

0.037

• These values are subject to external loading condition.
Measurement circuits of propagation delay lime
at LZ. ZL. HZ and ZH are as follows:

CJoI

,.nO

LSI

LSI
,IC

(a) Measurement of tpd at LZ and ZL.

l'

.•

R=2kO

m""

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is nslpF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1Q-H6RD-EO I

Sheet 111

I
Page 21-78

3-408

• CG10 ·Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

Number 01 Be

Function

Tri-state Output with Noise Limit Resistance
& Input Buffer (IOL=3.2mA. True)

HBT

Cell Symbol

9

Propagation Delay Paramel..

!Up

III"

to

KCL

to

KCL

0.663

0.017
0.036

1.150
3.190
(9.99)

0.023
0.080

un

(4.24)

"=tr-

OT

KCl2

Path

CDR2

Xto IN
OTto X

x

C

LtoZ

.

1.730
(17.65)

Pin Name

Input Loading
Factor (Iu)

OT
C

2
2

ZtoL
KCL

to

to

KCL

3.575
(10.63)

0.083

HtoZ
to

Pin Name

Output Driving
Factor (Iu)

IN

36

1.860
(17.65)

CtoX

ZtoH
KCL

.

to

KCL

1.300
(10.63)

0.037

• These values are subject to external loading condition.
Measurement circuns of propagation delay time
at LZ, ZL. HZ and ZH are as follows:

DI

,.,.n

LSI

LSI
,lC

(a) Measurement of tpd at LZ and ZL.

l'

~

1-

R=2kO

~~

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unn of KCL for paths OT, C to X is nsipF.
2. Output load capacHance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1o-H8T-EO

I

Sheet 1/1

I

I Page 21-79
3-409

I • CG10 • Version
I Number 01 BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Nam.

FUnction

I

Tri-state Output with Noise Limit Resistance
& Input Buffer (IOl=3.2mA, True) with Pull-up Resistance

H8TU

Cell Symbol

tu

'"~

to

KCL

0.663
1.177
(4.24)

0.017
0.036

. to

Propagation Delay Parameter
tIIn
KCL
KCl2
CDR2

1.150
3.190
(9.99)

9
Path

XtolN
OTto X

0.023
0.080

X

OT

C
LtaZ

ZtoL
KCL

to

.

1.730
(17.65)

to

KCL

3.575
(10.63)

0.083

CtoX

Input Loading
Factor (Iu)

Pin Name

2
2

OT

C

HtaZ
to

Pin Name

Output Driving
Flctor(lu)

IN

36

1.860
(17.65)

Zto H
KCL

.

to

KCL

1.300
(10.63)

0.037

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

DI

R."n

LSI

LSi
,lC

(a) Measurement of tpel at LZ and ZL.

i'

.~

R.2kO

mint

(b) Measurement of tpel at HZ and ZH.

Note: 1. The unH of KCL for paths OT, C to X is nsipF.
2. Output load capacHance of 85 pF is used for FujHsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1o-H8TU-EO

3-410

Sheet 1/1

I Page 21-80

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

J

Function

HBTD

Cell Symbol

Propagation Delay Parameler
!dn
10
KCL
KCL2
CDR2

IUp

'"~

or

10

KCL

0.663
1.177
(4.24)

0.017
0.036

1.150
3.190
(9.99)

Number 01 BC

I

Tri-state Output with Noise Limit Resistance
& Input Buffer (IOL=3.2mA, True) with Pull-down Resistance

9
Path

Xto IN
OTto X

0.023
0.080

x

C
LIDZ

10

ZIDL

.

10

KCL

3.575
(10.63)

0.083

KCL

10

KCL

1.300
(10.63)

0.037

KCL

1.730
(17.65)

CtoX

Inpul Loading
Faclor Clu)

Pin Name

or

2
2

C

Pin Name

Oulpul Driving
Faclor Clu)

IN

36

ZIDH

HloZ

10

1.860
(17.65)

.

• These values are subject to external loading condition.
Measurement circuHs of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

DI ,., "

LSI

LSI

~C
(a) Measurement of tpd at LZ and ZL.

l'

R-2kO

"'''"

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unH of KCL for paths OT, C to X is nslpF.
2. Output load capacHance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
Clo-H8TD-EO

Sheet 1/1

I Page 21-81

3-411

-' • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Funcllon
Cell Name

I Number 01 BC

I

Tn-state Output with Noise Limit Resistance
& Input Buffer (IOL=8mA, True)

HBTF

Cell Symbol
\up

to
0.663
1.231
(4.30)

'"=tr-

OT

KCL
0.017
0.036

"

9
Path

XtolN
OTto X

X

C

LIoZ

Input Loading
Factor (Iu)
2
2

Pin Name

Output Driving
Factor (Iu)

IN

36

ZIoL
KCL

to
2.240
(19.76)

Pin Name
OT
e

Prop8[allon Dela}' Parameter
IIIn
to
KCL
KCL2
CDR2
1.150 0.023
4.073 0.044
(7.82)

to
3.980
(7.72)

.

CtoX

ZIoH

HIoZ
to
1.860
(19.76)

KCL
0.044

KCL

to
1.300
(7.72)

.

KCL
0.037

• These values are subject to external loading condition.
Measurement circuHs of propagation delay time
at LZ, ZL, HZ and ZH are as fOllows:

D!

,.,.0
LSI

LSI

(a) Measuremel'll of Ipd at LZ and ZL.

Ie

,I

,rc

R=2kO

?'

.mfno

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unH of KeL for paths OT, C 10 X is nsipF.
2. Output load capacitance of 85 pF is used for Fujitsu'S logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C10-H8TF-EO

3-412

Sheet 1/1

I Page 21-82

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

Function

• Version
I Number 01 BC

Tri-state Output with Noise Limit Resistance
& Input Buffer (IOL=8mA, True) with Pull-up Resistance

H8TFU

Cell Symbol

I

Propagation Delay Plrlmeler
Idn

\up

"=cr-

OT

10

KCL

to

KCL

0.663
1.231
(4.30)

0.017
0.036

1.150
4.073
(7.82)

0.023
0.044

KCl2

9
P';'

CDR2

XlolN
OTtoX

X

C

LloZ

Pin Name

Inpul Loading
Factor (Iu)

OT
C

2
2

ZIDL

10

KCL

10

KCL

2.240
(19.76)

.

3.980
(7.72)

0.044

KCL

10

KCL

1.300
(7.72)

0.037

HloZ
10

Pin Name

Output Driving
Faclor (Iu)

IN

36

1.860
(19.76)

Clo X

ZID H

.

• These values are subject to exlernalloading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

c=rI

,.,.n

LSI

LSI
,IC

(a) Measurement of tpd at LZ and Zl.

11-

i' "''"

R= 2kil

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is nslpF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.
C1~H8TFU-EO

Sheet 1/1

I

I Page2Hl3
3-413

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

• Version

Function

NumberofBC

Tn-state Output with Noise Limit Resistance
& Input Buffer (IOL=8mA, True) with Pull-down Resistance

HBTFD

Cell Symbol

I

Propagation DeIlY Plrameter

tup

"~

OT

tdn

to

KCL

to

KCL

0.663
1.231
(4.30)

0.017
0.036

1.150
4.073
(7.82)

0.023
0.044

KCL2

9
Path

CDR2

XtolN
OTto X

X

C
LtoZ

Pin Name

Input LOldlng
Factor (Iu)

OT
C

2
2

ZtoL

to

KCL

to

KCL

2.240
(19.76)

.

3.9S0
(7.72)

0.044

KCL

to

KCL

1.300
(7.72)

0.037

ZtoH

Hlo Z
to

Pin Name

Output Driving
Factor (Iu)

IN

36

1.S60
(19.76)

CtoX

.

• These values are subject to external loading condition.
Measurement circuHs of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

DI

,.,,0

LSI

LSI

~C
(a) Measurement of tpd at LZ and ZL.

i'

~

R=2kO

",,,"

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unH of KCL for paths OT, C to X is nslpF.
2. Output load capacHance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1o-HSTFD-EO

3-414

Sheet 1/1

I Page 21-84

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION
Cell Name

Function

• Version
Number 01 BC

I

Power Tri-state Output with Noise Limit Resistance
& Input Buffer (IOL=12mA, True)

H8W

Cell Symbol

!up

"=t(L

OT

10

KCL

0.663
1.477
(3.52)

0.017
0.024

Propagation Delay Parameler
Idn
KCL
KCl2
CDR2
'to
1.150
4.770
(7.66)

9
Path

XtolN
OTto X

0.023
0.034

X

C

ZtoL

LtoZ
KCL

1O

.

2.600
(20.64)

1O

KCL

3.759
(8.18)

0.052

CtoX

Input Loading
Faclor (Iu)

Pin Name

2
2

OT

C

Pin Name

Outpul Driving
Factor (Iu)

IN

36

H toZ
'o
2.290
(20.64)

ZtoH
KCL

.

'o
1.400
(8.18)

KCL
0.025

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

CJI ,., "
LSI

LSI

~C
(a) Measurement of tpc! at LZ and Zl.

i'

R=2kQ

m'rr

(b) Measurement of tpc! at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is nslpF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C10--H8W-EO

Sheet 1/1

I Page 21-85
3-415

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

"Version

Funcllon

Cell Name

Number of BC

I

Power Tri-state Output with Noise Limit Resistance
& Input Buffer (IOL=12mA, True) with Pull-up Resistance

H8WU

Cell Symbol

tup
KCL

10

0.663
1.4n
(3.52)

'"~

OT

0.017
0.024

Propagation DeIlY Parameler
ttln
10
KCL
KCL2
CDR2

1.150
4.nO
(7.66)

9
Path

Xto IN
OTtoX

0.023
0.034

X

C

ZIO L

L to Z
KCL

10

.

2.600
(20.64)

10

KCL

3.759
(8.18)

0.052

Cto X

Inpul Loading
Faclor (Iu)

Pin Name

2
2

OT
C

Pin Name

Oulpul Driving
Faclor (Iu)

IN

36

Zto H

H 10Z

10

2.290
(20.64)

KCL

.

10

KCL

1.400
(8.18)

0.025

• These values are subject to external loading condition.
Measurement circuijs of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

c:rI '"'~

LSI

LSI

~c
(a) Measurement of tpd at LZ and ZL.

l'

~

~

R=2Kn

rrl77

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is nsipF.
2. Output load capacitance of 85 pF is used lor Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C10-H8WU-EO

3-416

I

Sheet 1/1

I

I Page 21-86

"CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function

Cell Name

Number 01 BC

I

Power Tri-state Output with Noise Limit Resistance
& Input Buffer (IOL=12mA, True) with Pull-down Resistance

HBWD

Cell Symbol

Propagation Delay Parameler
ldn
KCl2
10
KCL
CDR2

!up

"=tr-

OT

10

KCL

0.663
1.477
(3.52)

0.017
0.024

1.150
4.770
(7.66)

9
Path

XtolN
OTto X

0.023
0.034

X

C

L to Z
to

.

2.600
(20.64)

Pin Name

Inpul Loading
Faclor (Iu)

OT
C

2
2

ZtoL
KCL

to

KCL

3.759
(8.18)

0.052

H 10Z
10

Pin Name

Oulpul Driving
Faclor (Iu)

IN

36

2.290
(20.64)

Cto X

ZtoH
KCL

.

10

KCL

1.400
(8.18)

0.025

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

DI

,.,.n

LSI

LSI

,Ic

(a) Measurement of tpd at LZ and ZL.

t,

.
~

R=2kO

n+n

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KcLior paths OT, C to X is nsipF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1D-H8WD-EO

Sheet 1/1

I

I Page 21-87
3-417

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Function

Number 01 BC

Cell Nam.

Tri-state Output Buffer with Noise Limit Resistance
& CMOS Interiace Input Buffer (IOL=3.2mA, True)

HBC

Cell Symbol

9

Delay Paramet..
Idn
KCL
CDR2
KCL2
0.023
0.080

Prop~atlon

!Up

to
0.575
1.177
(4.24)

'"~

OT

KCL
0.017
0.036

to
0.831
3.190
(9.99)

Path

XtolN
OTtoX

X

C

LtoZ
to
1.730
(17.65)

ZtoL
KCL

.

to
3.575
(lo.s3)

KCL

to
1.300
(10.63)

KCL
0.083

CtoX

Input Loading
Factor (Iu)

Pin Name

0

2
2

OT

HtoZ
to
1.860
(17.65)

Output Driving
Factor (Iu)

Pin Name
IN

ZtoH

.

KCL
0.037

36

• These values are subject to external loading condition.
Measurement circuijs of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

Di,·.

n

LSI

LSI

,I0

(a) Measurement oltpd at LZ and ZL.

10
,I

:

R.2kG

~

m77

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unij of KOL for paths OT, C to X is nslpF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.
C1D-HSC-EO I

Sheet1f1

I
Page 21-88

3-418

I • CG10 • Version
~ L Number 01 BC
Tn-state Output Buffer wI Noise Limit Resistance & CMOS
9
Interface Input Buffer (IOL=3.2mA. True) wI Pull-up Resistance

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Function

Cell Name

HBCU

Propagation Delay Plrameler
!dn
to
KCL
KCL2
CDR2

Cell Symbol
hlp

to

KCL

0.575

un

0.017
0.036

(4.24)

"=er-

OT

0.831
3.190
(9.99)

Path

Xto IN
OTto X

0.023
0.080

x

C

LtoZ

to

.

1.730
(17.65)

Pin Name

Input Loading
Factor (Iu)

OT
C

2
2

Output Driving
Factor (Iu)

IN

36

to

KCL

3.575
(10.63)

0.083

HtoZ
to

Pin Name

ZtoL
KCL

1.860
(17.65)

CtoX

Zto H
KCL

.

to

KCL

1.300
(10.63)

0.037

• These values are subject to external loading condition.
Measurement circu~s 01 propagation delay time
at LZ. ZL. HZ and ZH are as follows:

D! ,., "
LSI

LSI

-1

;-

Rs2kCl

,Ic

,Ic

~'"
(a) Measurement of tpd at LZ and ZL.

Note: 1. The

un~

(b) Measurement of tpd at HZ and ZH.

of KCL for paths OT. C to X is nSlpF'.

2. Output load capacnance of 85 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.
C1O-H8CU-EO

Sheet 1/1

I Page 21-89
3-419

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

II

Tri-state Output Buffer wI Noise Limit Resistance & CMOS
Interface Input Buffer (IOL=3.2mA, True) wI Pull-down Resistance

HBCD

Cell Symbol

!Up
to

KCL

0.575

0.017
0.036

un

(4.24)

"=tr-

OT

Propagation Delay Parameter
Idn
. 10
KCL
KCl2
CDR2

0.831
3.190
(9.99)

NumberolBC

9
Path

XtolN
OTtoX

0.023
0.080

x

C

ZloL

LtoZ
KCL

10

.

1.730
(17.65)

Pin Name

Input Loading
Faclor (Iu)

OT
C

2
2

Output Driving
Faclor (Iu)

IN

36

KCL

3.575
(1M3)

0.083

1.860
(17.65)

CtoX

Zte H

H teZ

to
Pin Name

to

KCL

.

to

KCL

1.300
(10.63)

0.037

• These values are subject to external loading condition.
Measurement circu~s of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

~'."O
LSI

LSI

lc

,1

,lC

(al Measurement of tpd at LZ and ZL.

~

R.2kO

"'''"

(b) Measurement of tpd at HZ and ZH.

NOle: 1. The un" of KCL for paths OT, C to X is nslpF.
2. Output load capac~ance of 85 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.
C1Q-H8CD-EO

3-420

Sheet 1/1

I Page 21-90

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

I

Function

HBCF

Cell Symbol

!Up

"=tr-

OT

Propagation DeIlY Parameter
Idn
KCL
KCl2
COR2

to

KCL

to

0.575
1.231
(4.30)

0.017
0.036

0.831
4.073
(7.82)

Number 01 BC

I

Tri-state Output Buffer with Noise Limit Resistance
& CMOS Interface Input Buffer (IOL=8mA. True)

9
Path

XtolN
OTto X

0.023
0,044

X

C

ZtoL

LtoZ

Pin Name

Input Loading
Factor (Iu)

OT
C

2
2

to

KCL

2.240
(19.76)

.

to

KCL

3.980
(7.72)

H 10Z

Pin Name

Output Driving
Factor (Iu)

IN

36

CtoX

0.044

ZIO H

10

KCL

1.860
(19.76)

.

to

KCL

1.300
(7.72)

0.037

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ. ZL, HZ and ZH are as follows:

DI

,.,,0

LSI

LSI

lc

~C

~

(a) Measurement of tpd at LZ and ZL.

Note: 1. The unit of

..

RK2kQ

rr.f.n

(b) Measurement of tpd at HZ and ZH.

KCL for paths OT, C to X is nslpF.

2. Output load capacitance of 85 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the Simulation.
C10-H8CF-EO

Sheet 1/1

J

I Page 21-91
3-421

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• Version
Number 01 BC

Funcllon

Cell N.me

HBCFU

Tn-state Output Buffer wI Noise Limit Resistance & CMOS
Interface Input Buffer (IOL=8mA, True) wI Pull-up Resistance

Cell Symbol

tu

"~

OT

to

KCL

0.575
1.231
(4.30)

0.017
0.036

I

Propagation DeI.y P.r.m....
Idn
KCL
KCl2
CDR2
10

0.831
4.073
(7.82)

9
Path

Xto IN
OTtoX

0.023
0.044

X

C
LtoZ

Pin Name

Input Loading
Factor (Iu)

OT
C

2
2

ZIOL

10

KCL

2.240
(19.76)

.

to

KCL

3.980
(7.72)

ZIO H

HloZ
to

Pin N.me

Oulpul Driving
Faclor (Iu)

IN

36

1.860
(19.76)

CtoX

0.044

KCL

to

.

KCL

1.300
(7.72)

0.037

• These values are subject to extemalloading condition.
Measurement circuns of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

DI

,.,.0

LSI

LSI

~c

lc

,1

(a) Measurement of tpd at LZ and Zl.

~

••

R-2kO

min

(b) Measurement of Ipd at HZ and ZH.

Note: 1. The unn of KCL for paths OT, C 10 X is nslpF.
2. Output load capacnance of 85 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.
C 1D-H8CFU-EO I

3-422

Sheet 1/1

I

I Page 21-92

I "CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Function

Cell Name

HBCFD

Tri-state Output Buffer wI Noise Limit Resistance & CMOS
Interface Input Buffer (IOL=8mA, True) wI Pull-down Resistance

Cell Symbol
IUp

"~

OT

to

KCL

0.575
1.231
(4.30)

0.017
0.036

Propagation Delay Parameter
ldn
KCL
KCl2
CDR2
to

0.S31
4.073
(7.S2)

Number 01 BC

9
Path

Xto IN
OTto X

0.023
0.044

X

C

lto L

Ltol
to

KCL

.

2.240
(19.76)

Pin Name

Input Loading
Factor Clu)

OT
C

2
2

to

H tol
to

Pin Name

Output Driving
Factor Clu)

IN

36

1.S60
(19.76)

KCL

3.980
(7.72)

CtoX

0.044

ltoH
to

KCL

.

1.300
(7.72)

KCL

0.037

IDI

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ. ZL. HZ and ZH are as follows:

DI

,.,.0

LSI

LSI

,lc

(a) Measurement of tpd at LZ and ZL.

l'

l'
l'

R=2kO

",m

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is nslpF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.
C 1Q-HSCFD-EO I

Sheet 1/1

I

I Page 21-93
3-423

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

• Version
Number 01 BC

Function

I

Power Tri-state Output Buffer wI Noise Limit Resistance
& CMOS Interface Input Buffer (IOL=12mA. True)

HBE

Cell Symbol
lIJp

"~

OT

to

KCL

0.575
1.4n
(3.52)

0.017
0.024

Propagallon Delay Plramelar
II:In
10
KCL
KCL2
CDR2

0.831
4.nO

9
Palll

Xto IN
OTtoX

0.023
0.034

(7.66)

X

C
ZtoL

LtoZ

10

KCL

.

2.600
(20.64)

Pin Name

Inpul Loading
Faclor (Iu)

OT
C

2
2

10

KCL

3.759
(8.18)

0.052

HtoZ

10

Pin Name

Oulpul Drlvlng
Faclor(lu)

IN

36

2.290
(20.64)

Cto X

Zto H
KCL

.

10

KCL

1.400
(8.18)

0.025

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ. ZL. HZ and ZH are as follows:

DI

,.,,0

LSI

LSI

lc

,IC
,I

(a) Measurement QI tpd at LZ and ZL.

Note: 1. The unit of

KCL for

:•

R-2kO

m'rT

(b) Measurement of tpd at HZ and ZH.

paths OT. C to X is nsipF.

2. Output load capacitance of 85 pF Is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1Q-H8E-EO

3-424

Sheet 1/1

1

I Page 21-94

I . CG10 • Version
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
I Number 01 BC
Function
I
Power Tri-state Output Buffer wI Noise Limit Resistance & CMOSI
9
Interface Input Buffer (IOL=12mA, True) wI Pull-up Resistance

Cell Name

HBEU

Cell Symbol
IlJp

"=tr-

OT

to

KCL

0.575
1.477
(3.52)

0.017
0.024

Propagation Delay Plr8mel..
1I:In
KCL
· to
KCL2
CDR2

0.831
4.770
(7.66)

Pali1

XtolN
OTto X

0.023
0.034

X

C

LtoZ

ZtoL

to

KCL

to

KCL

2.600
(20.64)

·

3.759
(8.18)

0.052

to

KCL

to

KCL

2.290
(20.64)

·

1.400
(8.18)

0.025

CtoX

Input Loading
Faclor (Iu)

Pin Name

or

2
2

C

HtoZ

Pin Name

Output Driving
Faclor(lu)

iN

36

ZIOH

• These values are subject to external loading condition.
Measurement circuits 01 propagation delay time
at LZ, ZL, HZ and ZH are as lollows:

DI

,.,.n

LSI

LSI

lc

~ R a 2 kQ
l'

,IC
,I

(a) Measurement 01 tpd at LZ and Zl.

n:f77

(b) Measurement 01 tpd at HZ and ZH.

Note: 1. The unit 01 KCL lor paths OT, C to X is nSlpF.
2. Output load capacitance 0185 pF is used lor Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
CID-H8EU-EO

Sheet 111

I Page 21-95

3-425

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

• Version

Function

Call Nam.

NumberolBC

Power Tri-state Output Buffer wi Noise Limit Resistance & CMO~I
Interface Input Buffer (IOL=12mA, True) wi Pull-down Resistance

HBED

Call Symbol
!Up

"~

OT

to

KCL

0.575
1.477
(3.52)

0.017
0.024

Propagation Delay Parameter
IIln
to
KCL
KCl2
CDR2

0.831
4.770
(7.66)

9
Path

Xto IN
OTtoX

0.023
0.034

X

C
ZtoL

LtoZ
to

KCL

.

2.600
(20.64)

Pin Name

Input Loading
Factor (Iu)

OT
C

2
2

KCL

3.759
(8.18)

0.052

Pin Name

Output Driving
Factor (Iu)

iN

36

2.290
(20.64)

CtoX

ZtoH

HtoZ
to

l1li

to

KCL

.

to

KCL

1.400
(8.18)

0.025

• These values are subject to external loading condition.
Measurement circuHs of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

D!

,.,"0

LSI

LSI

~C
(a) Measurement of tpd at LZ and ZL.

i'

~

R=2kO

rrl77

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unH of KCL for paths OT, C to X is nslpF.
2. Output load capacHance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1D-H8ED-EO

3-426

Sheet 1/1

I Page 21-96

I • CG10 • Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Funcllon

Ce" Name

I

Tri-state Output & Schmitt Trigger Input Buffer
(IOl=3.2mA, CMOS Type, True) with Noise limit Resistance

HBS

Cell Symbol
IUp
10

KCL

1.550

0.067
0.036

un

(4.24)

"=er-

OT

Propagation DeIlY Parlmel..
Idn
10
KCL
KCL2
CDR2

1.925
3.190
(9.99)

13
Path

Xto IN
OTto X

0.056
0.080

x

C

LtoZ

ZtoL
KCL

10

t.730
(17.65)

.

10

KCL

3.575
(lo.s3)

0.083

KCL

10

KCL

1.300
(lo.s3)

0.037

CtoX

Inpul Loading
Flclor (Iu)

Pin Name

2
2

OT

C

Zto H

HtoZ
10

Pin Name

OulpUI Driving
Faclor (Iu)

IN

18

1.860
(17.65)

.

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
atl2, ZL, HZ and ZH are as follows:

DI

,.,.0

LSI

LSI

,lc
(a) Measurement of tpd atl2 and Zl.

1,

.•

R.2k(l

TTl 77

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is nSlpF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic Simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1Q-H85-EO 1

Sheet 111

J

I Page 21-97
3-427

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

H8SU

I

Number of BC

Function

Tri-state Output & Schmitt Trigger Input Buffer (IOL=3.2mA, CMO~
Type, True) wI Noise Limit Resistance wI Pull-up Resistance

Cell Symbol
tup

"=tr-

OT

to

KCL

1.550
1.177
(4.24)

0.067
0.036

Propagation Delay Parameter
tdn
KCL
KCL2
CDR2
to

1.925
3.190
(9.99)

13
Pam

Xto IN
OTtoX

0.056
0.080

x

C

LtoZ
to

.

1.730
(17.65)

Pin Name

Input Loading
Factor (Iu)

OT
C

2
2

Output Driving
Factor (Iu)

IN

18

to

KCL

3.575
(10.63)

0.083

HtoZ
to

Pin Name

ZtoL
KCL

1.860
(17.65)

Cto X

Zto H
KCL

to

KCL

.

1.300
(10.63)

0.037

• These values are subject to external loading condition.
Measurement circuHs of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

wI,·.

e

LSI

LSI

lc

,l

,Ic

(a) Measurement of tpd at LZ and ZL.

~

R=2kn

"'n

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unH of KCL for paths OT, C to X is nslpF.
2. Output toad capacHance of 85 pF is used for Fujitsu's logic simutation.
3. The parameters in parentheses are the values applied to the simulation.
Clo-H8SU-EO

3-428

I

Sheet 1/1

I Page 21-98

~•

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nlm.

HBSD

CG10 • Version
Number 01 BC

I
Function
ITri-state Output & Schmitt Trigger Input Buffer (IOL=3.2mA, CMOS
Type, True) wI Noise Limit Resistance wI Pull-down Resistance
Cell Symbol
1u~

to

KCL

1.550

0.067
0.036

un

(4.24)

"=tr-

OT

Propagallon Delay Parameter
IIdn
KCL
COR2
10
KCL2

1.925
3.190
(9.99)

13
Path

Xto IN
OTto X

0.056
0.080

X

C

L to Z
to

1.730
(17.65)

ZtoL
KCL

to

KCL

.

3.575
(1Q.63)

0.083

KCL

to

KCL

1.300
(1Q.63)

0.037

CtoX

Input Loading
Factor (luI

Pin Name

2
2

OT

C

HioZ
to

Pin Name

Outpul Driving
Factor (luI

IN

18

1.860
(17.65)

ZtoH

.

Ell

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

LSI

(a) Measurement of tpd at LZ and ZL.

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is nslpF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.

3. The parameters in parentheses are the values applied to the simulation.
C1D-H8SD-EO

Sheet 1/1

I
Page 21-99

3-429

I • CG10 • Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

Function

I

Tri-state Output & Schmitt Trigger Input Buffer
(IOL=3.2mA, TIL Type, Truej'with Noise Limit Resistance

HBR

Cell Symbol
tup

"~

OT

to

KCL

1.400
1.177
(4.24)

0.067
0.036

Propagation Delay Perameter
tdn
· 10
KCL
KCL2
COR2

2.325
3.190
(9.99)

13
Path

Xto IN
OTto X

0.073
0.080

X

C
LtoZ
to

1.730
(17.65)

ZtoL
KCL

10

KCL

·

3.575
(10.63)

0.083

KCL

to

KCL

·

1.300
(10.63)

0.037

CtoX

Input Loading
Factor (Iu)

Pin Name

2
2

OT
C

HloZ

10

Pin Name

Output Driving
Faclor(lu)

IN

18

1.860
(17.65)

ZtoH

• These values are subject to external loading condition.
Measurement circuHs of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

c:rI

,.,.0

LSI

LSI

,Ic

(a) Measurement of tpd at LZ and ZL.

Note: 1. The unit of

l'

~

R= 2kO

>

"'77

(b) Measurement of tpd at HZ and ZH.

KCL for paths OT, C to X is nsipF.

2. Output load capacitance of 85 pF is used lor Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the Simulation.

C1o-H8R-EO

3-430

J

Sheet 1/1

I

I Page 21-100

• CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

Tri-state Output & Schmitt Trigger Input Buffer (IOL=3.2mA, TTL
Type. True) wi Noise Limit Resistance wi Pull-up Resistance

HBRU

Cell Symbol
tup

to

KCl

1.400

0.067
0.036

un

(4.24)

"~

OT

I

Propagation Delay Parameter
Idn
KCl
KCl2
to
CDR2

2.325
3.190
(9.99)

Number of BC

13
Path

Xto IN
OTto X

0.073
0.080

X

C
ltoZ
to

1.730
(17.65)

Pin Name

Input loading
Factor (Iu)

OT
C

2
2

Ztol
KCl

to

KCl

.

3.575
(10.63)

0.083

KCl

to

KCl

.

1.300
(10.63)

0.037

ZtoH

HtoZ
to

Pin Name

Oulput Driving
Faclor (Iu)

IN

18

1.860
(17.65)

CtoX

• These values are subject to external loading condition.
Measurement circuns of propagation delay time
at LZ. ZL. HZ and ZH are as follows:

DI

'_H"

lSI

lSI
,IC

(a) Measurement of tpd at LZ and ZL.

l'

•
•

R=2kn

mn

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unn of KCl for paths OT. C to X is nslpF.
2. Output load capacnance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C10-H8RU-EO

Sheet 1/1

I

I Page 21-101
3-431

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

• Version

Function

Tri-state Output & Schmitt Trigger Input Buffer (IOL=3.2mA,TIL
Type, True) wI Noise Limit Resistance wI Pull-down Resistance

H8RD

Cell Symbol

tu
to

KCL

1.400
1.177
(4.24)

"~

OT

0.067
0.036

I

Propagation Delay Parameter
llin
to
KCL
KCl2
CDR2

2.325
3.190
(9.99)

NumberolBC

13
Path

XtolN
OTto X

0.073
0.080

X

C
ZtoL

LtoZ
KCL

to

1.730
(17.65)

KCL

3.575
(10.63)

0.083

KCL

to

KCL

1.300
(10.63)

0.037

CtoX

Input Loading
Factor (Iu)

Pin Name

2
2

OT
C

HtoZ
to

Pin Name

Output Driving
Factor (Iu)

IN

18

IDII

.

to

1.860
(17.65)

Zto H

.

• These values are subject to external loading condition.
Measurement circuHs 01 propagation delay time
at LZ, ZL, HZ and ZH are as lollows:

DIM"
LSI

LSI

lc

.

R=2kil

!"

1,C
1,

(a) Measurement 01 tpel at LZ and ZL.

IT. In

(b) Measurement 01 tpel at HZ and ZH.

Note: 1. The unH of KCL lor paths OT, C to X is nslpF.
2. Output load capacHance 0185 pF is used lor Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1Q-H8RD-EO

3-432

Sheet 1/1

I Page 21-102

I • CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Name

Function

"Version
I Number 01 BC

I

Power Tri-state Output with Noise Limit Resistance
& Input Buffer (IOL=24mA, True)

HBW2
Cell

Symbol
tup

to
0.663
3.050
(4.50)

"=tr

OT

KCL
0.017
0.017

LtoZ
to
4.800
(22.74)

Input Loading
Factor (Iu)
2
2

OT

C

Output Driving
Factor (Iu)

Pin Name
IN

Path
Xto IN
OTto X

X

C

Pin Name

Propagation Delay Parameter
tdn
·to
KCL
KCL2
CDR2
1.150 0.023
10.400 0.037
(13.55)

11

ZtoL
KCL

.

to
12.490
(9.01)

KCL

to

KCL

2.000
(12.49)

0.020

HtoZ
to
3.620
(22.74)

KCL
0.041

CtoX

Zto H

.

36

• These values are subject to external loading condition.
Measurement circuijs of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

~"""
LSI

LSI
,IC

(a) Measurement of tpd at LZ and ZL.

i'

;

>

R.2kQ

",In

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unij of KCLIor paths OT, C to X is nsipF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C10-H8W2-EO

Sheet 111

I Page 21-105
3-433

I . CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

"Version
NumberofBC

Function

I

Power Tri-state Output with Noise Limit Resistance
& Input Buffer (IOL=24mA, True) with Pull-up Resistance

HBW1

Cell Symbol

!Up

"~

10

KCL

0.663
3.050
(4.50)

0.017
0.017

Propagation Delay Parameter
!dn
10
KCL
KCl2
CDR2

1.150
10.400
(13.55)

11
Path

XtolN
OTto X

0.023
0.037

X

OT

C
ZtoL

LtoZ
to

KCL

.

4.800
(22.74)

Pin Name

Input Loading
Factor (Iu)

OT
C

2
2

KCL

12.490
(9.01)

0.041

HloZ
to

Pin Name

Output Driving
Factor (Iu)

IN

36

IDI

to

3.620
(22.74)

CtoX

ZtoH
KCL

.

to

KCL

2.000
(12.49)

0.020

• These values are subject to external loading condition.
Measurement circuits of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

c:rI

,.,.0

LSI

LSi
l,C

(a) Measurement of tpd at LZ and ZL.

l' "''"
>-

R = 2 kCl

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is nsipF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are It e values applied to the simulation.
C1D-H8Wl-EO\

3-434

Sheet 1/1

I

I Page 21-106

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Number 01 BC

Function

I

Power Tri-state Output with Noise Limit Resistance
& Input Buffer (IOL=24mA, True) with Pull-down Resistance

H8WO

Cell Symbol
tup

to

KCL

Q.663
3.050
(4.50)

"~

OT

0.017
0.017

Propagation Delay Parameter
tIln
to
KCL
KCl2
CDR2

1.150
10.400
(13.55)

11
Path

Xto IN
OTto X

0.023
0.037

X

C
LtoZ

.

4.800
(22.74)

Pin Name

Input Loedlng
Factor (Iu)

OT
C

2
2

ZtoL
KCL

to

to

KCL

12.490
(9.01)

0.041

HtoZ
to

Pin Name

Output Driving
Factor (Iu)

IN

36

3.620
(22.74)

CtoX

ZtoH
KCL

.

to

KCL

2.000
(12.49)

0.020

• These values are subject to external loading condition.
Measurement circuns of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

DI

,."e

LSI

LSI

,Ic

Ic ..
,I

(a) Measurement of tpd at LZ and ZL.

R=2kQ

",77

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unit of KCL for paths OT, C to X is nsipF.
2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C10-H8WO-EO

Sheet 1/1

I Page 21-107

3-435

I " CG10

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

"Version
Numbero! BC

Function

I

Power Tri-state Output wI Noise Umit Resistance
& CMOS Interface Input Buffer (IOL=24mA. True)

HBE2

Cell Symbol
IUp

'"~

OT

to

KCL

0.575
3.050
(4.50)

0.017
0.017

Propagation Delay Parameler
tdn
KCL
KCL2
CDR2
10

0.831
10.400
(13.55)

11
Path

XtolN
OTto X

0.023
0.037

X

C
LtoZ

.

4.800
(22.74)

Pin Name

Input Loading
Faclor(lu)

OT
C

2
2

ZIoL
KCL

10

to

KCL

12.490
(9.01)

0.041

ZIO H

HloZ
10

Pin Name

Oulput Driving
Faclor(lu)

IN

36

3.620
(22.74)

CtoX

KCL

.

10

KCL

2.000
(12.49)

0.020

• These values are subject to external loading condition.
Measurement circu~s of propagation delay time
at LZ. ZL, HZ and ZH are as follows:

DI
LSI

,.,.0
LSI

,Ic

(a) Measurement of tpd at LZ and ZL.

1c

,I

~

R=2kQ

?'

nh7

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unH of KCL for paths OT, C to X is nsipF.
2. Output load capacitance of 85 pF is used lor Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
Clo-H8E2-EO

3-436

Sheet 1/1

I Page 21-108

I " CG10 • Version
I Number of BC

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name

Function

Power Tri-state Output wI Noise Limit Resistance

HBE1

& CMOS Input Buffer (IOL=24mA, True) wI Pull-up Resistance
Cell Symbol
\Up

"=tr-

OT

to

KCL

0.575
3.050
(4.50)

0.017
0.017

I

Propagation Delay Parameter
!dn
to
KCL
KCl2
CDR2

0.831
10.400
(13.55)

11
Path

XtolN
OTto X

0.023
0.037

X

C

LtoZ
to

.

4.800
(22.74)

Pin Name

Input Loading
Factor (Iu)

OT
C

2
2

ZtoL
KCL

10

KCL

12.490
(9.01)

0.041

H 10Z
10

Pin Name

Oulput Driving
Faclor (Iu)

IN

36

3.620
(22.74)

CtoX

Zto H
KCL

.

to

KCL

2.000
(12.49)

0.020

• These values are subject to ex1ernalloading condition.
Measurement circuns of propagation delay time
at L2, ZL, HZ and ZH are as follows:

DI
LSI

,.an
LSI

,rc

(a) Measurement of tpd at L2 and ZL.

1,

R=2kQ

"77

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unn of KCL for paths OT, C to X is nsipF.
2. Output load capacnance of 85 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
C1D-H8E1-EO

Sheet 1/1

I Page 21-109

3-437

I • CG10 • Version

FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION

I

Cell Nam.

j Number of BC

Function

II

Power Tri-state Output wI Noise Umit Resistance
& CMOS Input Buffer (IOL=24mA, True) wI Pull-down Resistance

HBEO

Propagation Delay Parameter
Idn

Cell Symbol

tu

"=tr-

OT

to

KCL

0,575
3,050
(4.50)

0,017
0.017

KCL

' to

0,831
10,400
(13,55)

Path

CDR2

KCL2

11

XtolN
OTtoX

0,023
0.037

X

C

LtoZ

ZtoL
KCL

to

.

4,800
(22,74)

to

KCL

12.490
(9.01)

0,041

CtoX

Input LoadIng
Factor (Iu)

PIn Name

2
2

OT

C

HIoZ
10

Pin Name

Oulpul DrIvIng
Faclor (Iu)

IN

36

3,620
(22.74)

ZtoH
KCL

.

to

KCL

2.000
(12.49)

0,020

• These values are subject to external loading condition.
Measurement circuHs of propagation delay time
at LZ, ZL, HZ and ZH are as follows:

DI

,_,,0

LSI

LSI

lc

,I

,LC
(a) Measurement of tpd at LZ and ZL.

~ R~2kn

;.

nm

(b) Measurement of tpd at HZ and ZH.

Note: 1. The unH of KCL for paths OT, C to X is nslpF.
2. Output load capacHance of 85 pF is used for Fujitsu's logic sirrulation.
3. The parameters in parentheses are the values applied to the simulation.
C1D-H8ED-EO

3-438

Sheet 1/1

I Page 21-110

CMOS Channeled Gate Anays

CG10 Series Unit Cell Library

Appendix A: General AC Specifications

Mlmlmum/maxlmum Delay Multipliers
(Recommended Operating Conditions, Ta

=0 to 70°C, V

Delay Multipliers

Min.

Max.

Pre-layout Simulation

0.35

1.65

Post-layout Simulation

0.40

1.60

DD

= 5 V±S%

..

3-439

CG10 Series Unit Cell Ubrary

3-440

CMOS Channeled Gate Arrays

CMOS Channeled Gate A"ays

CG10 Series Unit Cell Library

Appendix B: Hierarchical Structure
Hierarchical blocks (or Functional Logic Blocks) within other hierarchical blocks are user-defined groups of
cells laid out in close proximity to each other in both X and Y dimensions of the array.

The hierarchical method of design allows circuit sections to be placed within the array at positions relative to
each other. This is made possible by the designer's defining and placing functional logic blocks within the hierarchy and thus contrOlling path lengths.

There are five levels of hierarchy, also referred to as Functional Logic Blocks (FLBs). The design rules regarding what may and what must appear at certain levels are condensed in the diagram below.

All 1/0 buffers and their associated circuitry must be defined immediately beneath the chip level with the FLB1
blocks. Nothing but 1/0 buffers may be so defined. If pull-up or pull-down cells (A01 s or XOOs) are required for
unused inputs of the 1/0 buffers, they must also be defined at this level. Unit cells (UC) may be defined at each
level.

For optimum delay characteristics, Level 2 blocks should be defined under each of the Level 1 blocks, Level 3
Blocks under Level 2 blocks, and so on. Unit cells should be defined under Level 4.

3-441

CG10 Series Unit Cell Ubraty

3-442

CMOS Channeled Gate A"ays

CG 10 Series Unit Cell Library

CMOS Channeled Gate AITBYs

Appendix C: Estimation Tables for Metal Loading
CG10272 (2700-gate device)
Clock Net
NO!

CL(lu)

NO!

CK20, CK40
CL (Iu)

CK60, CK80
CL(lu)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31-50
51-75
76 -100

2.3
4.9
6.7
7.8
8.5
9.3
10.2
10.5
10.8
11.0
11.0
11.3
11.4
11.7
11.7
12.7
14.4
14.8
16.3

1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31-50
51-80

8.3
8.3
15.8
15.8
23.3
23.3
30.7
30.7
34.7
34.7
35.0
35.0
35.4
35.4
35.4
35.8
38.8
42.8

12.9
12.9
24.9
24.9
36.9
36.9
48.9
48.9
55.2
55.2
55.5
55.5
55.9
55.9
55.9
56.3
59.3
63.3

NO!

CK20, CK40

CK60, CK80

CL(lu)

CL(lu)

8.9
8.9
16.9
16.9
24.9
24.9
32.9
32.9
41.0
41.0
41.4

14.0
14.0
27.3
27.3
40.4
40.4
53.5
53.5
66.8
66.8
67.2
67.2
67.7
67.7
67.7
68.0
71.2
75.3

CG10342 (3400-gate device)
Clock Net
NO!

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31-50
51-75
76-100

CL(lu)

2.8
5.9
8.0
9.3
10.3
11.2
12.2
12.7
13.0
13.4
13.4
13.5
13.7
14.0
14.0
15.2
17.4
17.9
19.7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31-50
51 -80

41.4

41.8
41.8
41.8
42.3
45.4
49.5

Continued on next page

3-443

CG10 Series Unit CeN Ubrary

CMOS Channeled Gate Anays

Appendix C: Estimation Tables for Metal Loading
CG10492 (490O-gate device)
Clock Net
NDI

CL(lu)

NDI

CK20,CK40
CL(Iu)

CK60,CKBO
CL(Iu)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31-50
51-75
76-100

3.3
7.2
9.7
11.3
12.5
13.5
14.8
15.4
15.8
16.2
16.2
16.4
16.5
17.0
17.0
18.4
21.0
21.7
23.8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31-50
51-80

9.7
9.7
18.5
18.5
27.3
27.3
36.2
36.2
44.9
44.9
53.8
53.8
54.2
54.2
54.2
54.7
57.9
62.3

15.8
15.8
30.7
30.7
45.5
45.5
60.4
60.4
75.3
75.3
90.2
90.2
90.5
90.5
90.5
91.0
94.3
98.7

CG10572 (5700-gate device)
Clock Net
NI)I

CL(lu)

NDI

CK20,CK40
CL (Iu)

CK60, CK80
CL (Iu)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31-50
51-75
76 -100

3.8
8.2
11.1
12.9
14.4
15.5
17.0
17.6
18.1
18.5
18.5
18.8
18.9
19.5
19.5
21.1
24.1
24.8
27.3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31-50
51-80

10.0
10.0
19.4
19.4
28.6
28.6
38.1
38.1
46.7
46.7
60.6
60.6
60.9
60.9
60.9
61.5
64.6
69.4

16.7
16.7
32.6
32.6
46.5
46.5
64.5
64.5
79.6
79.6
101.0
101.0
101.7
101.7
101.7
102.7
107.9
115.9
Contmued on next page

3-444

CG10 Series Unit Cell Library

CMOS Channeled Gate Arrays

Appendix C: Estimation Tables for Metal Loading
CG10672 (6700-gate device)
Not

Within Block
CL(lu)

Not

Inter-Block
CL(lu)

Not

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31 -50
51 -75
76 -100

2.0
4.4
5.9
6.9
7.7
8.3
9.0
9.4
9.7
9.9
9.9
10.0
10.3
10.5
10.5
11.4
13.0
13.3
14.7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31 -50
51 -80
76 -100

4.4
9.5
12.8
15.0
16.7
18.0
19.7
20.4
21.0
21.5
21.5
21.8
22.0
22.7
22.7
24.5
28.0
28.8
31.7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31 -50
51 -80

Clock Net
CK20, CK40 CK60,CKSO
CL(lu)
CL(lu)
12.4
18.7
30.2
36.5

16.5
31.0
46.7
61.2

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

CG10103 (10000-gate device)
Not

Within Block
CL(lu)

Not

Inter-Block
CL(lu)

Not

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 -30
31-50
51-75
76-100

2.8
5.9
8.0
9.3
10.3
11.2
12.2
12.7
13.0
13.4
13.4
13.5
13.7
14.0
14.0
15.2
17.4
17.9
19.7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31-50
51-80
76-100

5.3
11.5
15.5
18.2
20.0
21.7
23.7
24.7
25.3
26.0
26.0
26.3
26.7
27.3
27.3
29.5
33.9
34.8
38.2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-30
31 -50
51-80

Clock Net
CK20, CK40 CK60, CKSO
CL (Iu)
CL(lu)
14.8
22.3
36.2
43.7

19.7
37.2
56.0
73.4

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Continued on next page

3-445

CG10 Series Unit Cell Ubrary

CMOS Channeled Gate Arrays

Appendix C: Estimation Tables for Metal Loading
CG10133 (13000-gate device)
NOI

Within Block
CL(lu)

NOI

Inter-Block
CL (Iu)

NOI

1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16-30
31-50
51-75
76-100

3.3
7.2
9.7
11.3
12.5
13.5
14.B
15.4
15.B
16.2
16.2
16.4
16.5
17.0
17.0
1B.4
21.0
21.7
23.B

1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16-30
31-50
51-BO
76-100

6.2
13.5
1B.2
21.3
23.5
25.4
27.B
2B.9
29.7
30.4
30.4
30.B
31.3
32.0
32.0
34.7
39.7
40.B
44.B

1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16-30
31-50
51-BO

Clock Net
CK20, CK40
CK60, CK80
CL(lu)
CL(IU)
17.2
25.9
42.2
51.0

-

-

-

-

-

22.9
43.4
65.4
B5.9

-

-

-

-

"Inter-Block" tables must be applied to a net which has an inter-block connection. If a net, for example, has
three NDI in a block and one NDI in a different block, NDI = 4 of the "Inter-Block" table must be applied.

3-446

CMOS Channeled Gate Arrays

CG10 Series Unit Cell LibraI}'

Appendix 0: Available Package Types
CG10 CMOS Available Package Types
CG10272

CG10342

,.".

CG10492

•

•

•

DIP40

•
•
•

•

•

•

•
•

DIP48

SH-DIP42

•

SH-DIP64

CG10692

•
•

•
•
•
•

•
•
•

•
•

•

.....

OFP80
OFP100

•
•
•

CG10133

....
·.,.·,i,

•
•
•

OFP48
OFP64

CG10103

..

DIP28

DIP42

CG10572

..'.... ,.,

•
•
•

•
•
•

•
•
•

OFP120

•

OFP160

•

•
•

•
•
•

•

•
•

OFP196

SOFP64
SOFP100

•

•
•

•

•

SOFP176
SOFP208

P(lA (Pln~,.i~~~r~)'Packrigii)
PGA64
PGA88
PGA135

•
•
•

..

:,.',;.

•

•
•

PGA179

i··:i>

......

•
•
•
•

....

..,

•

•
•
•

•
•

PGA208
PGA256

. . .,......<>

..........

•
•
•
•
•
•

•
•
•
•
•
.

•

PGA256

PLCC68
PLCC84

•
•

•
•

•
•

•
•

... .. ,....
•

.,

,'

,

.. .
.

•
•

3-447

CG10 Series Unit Cell Ubrary

3-448

CMOS Channeled Gate Arrays

CG 10 Series Unit Cell Library

CMOS Channeled Gate Arrays

Appendix E: TTL 7400 Function Conversion Table
TIL 7400
Series
Name
7400
7401
7402
7403
7404
7405
7406
7407
7408
7409
7410
7411
7412
7413
7414
7415
7418
7419
7420
7421
7422
7423
7424
7425
7426
7427
7428
7430
7432
7433
7434
7435
7437
7438/9
7440
7442
7443
7444
7445
7446
7447
7448
7449
7450
7451
7452
7453
7454
7455
7460
7461
7462
7464
7465

Quad 2-input NAND
Quad 2-input NAND, Open Collector Outputs
Quad 2-input NOR
Quad 2-input NAND, Open Collector Outputs
Hex Inverter
Hex Inverter, Open Collector Outputs
Hex Inverter/Buffer, Open Collector Outputs
Hex Buffer, Open Collector Outputs
Quad 2-input AND
Quad 2-input AND, Open Collector Outputs
Triple 3-input NAND
Triple 3-input AND
Triple 3-NAND, Open Collector Outputs
Dual4-input NAND, Schmitt Trigger
Hex Schmitt Trigger Inverter
Triple 3-input AND, Open Collector Outputs
Dual4-input NAND, Schmitt Trigger
Hex Schmitt Trigger Inverter
Dual4-input NAND
Dual4-input AND
Dual4-input NAND, Open Collector Outputs
Expanded Dual 4-input NOR with Strobe
Quad Schmitt Trigger 2-input NAND
Dual 4-input NOR with Strobe
Quad 2-input NAND, High Voltage Output
Triple 3-input NOR
Quad 2-input NOR Buffer
8-input NAND
Quad 2-input OR
Quad 2-input NOR Buffer, Open Collector
Outputs
Hex Noninverter
Hex Noninverter with Open Collector Outputs
Quad 2-input NAND Buffer
Quad 2-input NAND Buffer, Open Collector
Outputs
Dual 4-input NAND Buffer
BCD to Decimal Decoder
EX3 to Decimal Decoder
4 to 10 Line Decoder
BCD to Decimal Decoder/driver (30V)
BCD to 7-segment Decoder/Driver (30V)
BCD to 7-segment Decoder/Driver (15V)
BCD to 7-segment Decoder/Driver
BCD to 7-segment, Open Collector Outputs
Dual 2-input, 2-wide AOI (One Expandable)
AOI
Expandable 4-wide AND-OR
Expandable 4-wide AOI
4-wideAOI
2-wide 4-input AOI
Dual 4-input Expander
Triple 3-input Expander
4-wide AND-OR Expander
4-2-3-2AOI
4-2-3-2 AOI (Open Collector)

Number
of Unit
Cells

Fujitsu
Basic Cells

Function

4
6
4
6
6
5
5
5
8
6
6
9
7

4x N2N
T24 multiplexer
4x R2N
T24 multiplexer
6x VIN
R6B
R6B
2 x N3N into R2N
4. N2P
N8P
3x N3N
3 x N3P
T33
2 x (4 x 12R to N4N)
6x 11R
N8P to N2P
2 x (4 x 12R to N4N)
6 xllR
2xN4N
2x N4P
2 x N4N + N2P
R4P to D23 + R4P to R2N
8 x 12R + 4 x N2N
2 x (R4P + R2N)
4 x N2N
3x R3N
4 x R2N
N8B
4 x R2P

68

48
8
68
48

4
6
6
9
68

8
4

6
4
6
8

4 x R2N + N4P

7

6 x BIN

6
5

2 x N3N into R2N
4 x N2B

12

4 x N2N + N4P
2 x N4B (N4N if not power)
4xV2B+ 10xN4N
4 x V2B + lOx N4N
4xV2B+l0xN4N
4 x V2B + lOx N4N
4 x VIN + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P
4 x VIN + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P
4 x VIN + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P
4 x VIN + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P
D36 + D24
2x D24
N3N + D36 + VI N into N3N
D36 + D23 into N2P
2 x N3N + 2 x N2N + N4N + VI N
T42
2 xN4P
3 xN3P
2 x N3N + 2 x N2N + N4N
T54
T54

7
8(4)
24
24
24
24
53
53
53
53

5
4
8

7
9

6
6

6
8
10
10

Continued on next page

3-449

CG 10 Series Unit CeO Ubrary

CMOS Channeled Gate Arrays

TTL 7400 Function Conversion Table
TIL 7400
Series
Name
7470

Function
ANO-gated positive-edge JK FF with Preset
and Clear

or:
7471
7472

AND-gated RS MIS FF with Preset
and Clear
or:
ANO-gated JK MIS FF with Preset
and Clear

or:
7473
7474
7475
7476
7477
7478
7480
7482
7483
7484
7486
7487
7489
7490
7491
7492
7493
7494
7495
7496
7497
7498
7499
74100
74101
74102
74103
74106
74107
74108
74109
74110
74111
74112

Dual JK FF with Clear
Dual positive-edge D-FF with Preset and
Clear
4-bit Bistable Latch
Dual JK FF with Preset and Clear
4-bit Bistable Latch
Dual JK FF with Preset and Common
Clear and Clock
Gated Full Adder
2-bit Binary Full Adder
4-bit Binary Full Adder with Fast Carry
4-bit Magnitude Comparator
Quad 2-input XOR
4-bit True/Complement Zero/One Element
64-bit (16 x 4) Memory
Decade Counter
(Different Implementation)
8-bit Shift Register
Divide-by-12 Counter
4-bit Binary Counter
4-bit Shift Register, 2 asynchronous Presets
4-bit Shift Register, 2 asynchronous
Presets, Full Implementation
4-bit Parallel-access Shift Register
5-bit Shift Register
Synch 6-bit Binary Rate Multiplier
4-bit Data SelectoriStorage Register
4-bit Universal Shift Register
8-bit Bistable Latch
AO-gated JK Negative-Edge FF,
with Preset
AND-gated JK Negative-Edge FF with
Preset and Clear
Dual JK FF with Clear
or:
Dual JK Negative-Edge FF with Preset
and Clear
Dual JK FF with Clear
Dual JK Negative-Edge FF with Preset
and Common Clear and Clock
Dual JK Positive-Edge FF with Preset and
Clear
AND-gated JK MIS FF with Data
Lockout
Dual JK MIS FF with Data Lockout
Dual JK Negative-Edge FF with Preset
and Clear

Number
of Unit
Cells

Fujitsu
Basic Cells
3 x V1N + 2 x N3N + N2N + R2N + FJD
FD4 + 2 x N2N + R2N + VI N + R2P + 024

21
17

FD4 + 2 x N3N + 2 x 023 + 2 x V1N
LT1+ 2 x N4N + N2P

19
10

V1N + 2 x N3N + N2N + R2N + FJD
FD4 + N3P + N3N + V1N + 024
2x FJD

19
17
24

2x FOP
LTM
2 x (FJD + N2N + R2N + VI N)
LTM
2 x (FJD + N2N + R2N + VI N)

16
16
30
16
30

A1N
A2N
A4H
MC4
4xX2N
4 x N2N + VI N + 4 x N2N
2 x DE6 + VI N + 16 x LT4
+ 5 x (V2B + TSA) + 10 x V2B
2 x (FOP + FDO + N2P + N2N + R2N) + V1N
4 x N2P + 2 x R2P + N2N + C41 + LTI
2x FDS+ V1N
4 x FDO + 2 x V1N + 2 x R2N + N2N
C41 + N2N (for the resets)
FS3

8
16
48
42
12
17
298
39
41
41
33
25
34

4 x FOP + 4 x 024 + 2 x V1N
FS2 + 024 + 2 x VI N
5 x FOP + 5 x N2N + VI N(clock)
FOR + 2 x FDO + 3 x VI N + 2 x N2N
+ 2 x N3N + 2 x N4N + 5 x N6B + 3 x N8B
+ R2B + X2N + 5 x X1B.
FDa + T2F +4x V1N
FS2 + LTK + 2 x 024 + 4 x V1N
2 x YL4 + 2 x VI N

42
34
46
122

FD3 + V1N + 3 x 024

15

FD4 + 024 + N3P + N3N
2 x FJD + 2 x V1N (for clock)
2 x (FD5 + 024 + VI N)

16
26
22

2 x (FD4 + 024 + V1N)
2 x (FJD + 2 x VI N)

24
22

2 x (FD4 + 024 + V1N)

24

2 x (FOP + V1N + 024)

22

FOP + 024 + N3P + N3N
2 x (FOP + 024 + V1N)

15
22

2 x (FD4 + 024 + V1N)

24

33
42
30

Continued on next page

3-450

CG10 Series Unit Cell Library

CMOS Channeled Gate Arrays

TTL 7400 Function Conversion Table
TTL 7400
Series
Name
74113
74114

74138
74139
74141
74145
74147

Dual JK Negative-Edge FF with Preset
Dual JK Negative-Edge FF with Preset and
Common Clear and Clock
Dual 4-bit Latch with Clear
Dual Pulse Synchronizer/Driver
Quad Bus Buller with 3-state Output
Quad Bus Buller with 3-state Output
Quad 2-input NAND Schmitt Trigger
IS-input NAND
12-input NAND with S-state Outputs
Quad 3-input EXORlEXNOR
Quad 2-input EXOR with Open-Collector
Outputs
3-line to 6-line Decoder with Address
Latch
3-line to 8-iine Decoder with Enable
Dual 2-line to 4-iine Decoder
BCD-to-Decimal Decoder
BCD-Io-323
FAX: (612) 454-{)601

Fujitsu Microelectronics, Inc.
14785 Preston Road
Suite 670
Dallas, TX 75240
Tel: (214) 23~394
FAX: (214) 386-7917

COLORADO (Denver)
Fujitsu Microelectronics, Inc.
5445 DTC Parkway
Suite 300
Englewood, C080111
Tel: (303) 740-8880
FAX: (303) 740-8988
GEORGIA (Atlanta)
Fujitsu Microelectronics, Inc.
3500 Parkway Lane
Suite 210
Norcross, GA 30092
Tel: (404) 449-8539
FAX: (404) 441-2016

4-10

NEW JERSEY (MI. Laurel)
Fujitsu Microelectronics, Inc.
Horizon Corporate Center
3000 Atrium Way
Suite 100
Mt. Laurel, NJ 08054
Tel: (609) 727-'il700
FAX: (609) 727-9797

CMOS Channeled Gate Arrays

Sales Informauon

FMI Representatives -

USA

For product information, contact your nearest Representative.
Alabama

Connecticut

Indiana

The Novus Group, Inc.
2905 Westcorp Blvd.
Suite 120
Huntsville, AL 35805
Tel: (205) 534-{)044
FAX: (205) 534-{)186

Conntech Sales. Inc.
605 Washington Avenue
Suite 33
New Haven, CT 06473
Tel: (203) 234-0577
FAX: (203) 234-0576

Fred Dorsey & Associates
3518 Eden Place
Carmel, IN 46032
Tel: (317) 844-4842
FAX: (317) 844-4843

Arizona

Florida

Aztech Component Sales Inc.
15230 N 75th Street
Suite 1031
Scottsdale, AZ 85260
Tel: (602) 991~00
FAX: (602) 991-{)563

Semtronic Associates, Inc.
657 Maidand Avenue
Altamonte Springs, FL 32701
Tel: (407) 83 t-8233
FAX: (407) 831-2844

Iowa

California
Harvey King, Inc.
6393 Nancy Ridge Drive
San Diego, CA 92121
Tel: (619) 587-8300
FAX: (619) 587-{)507
Infinity Sales, Inc.
4500 Campus Drive
Suite 300
Newport Beach, CA 92660
Tel: (714) 833-0300
FAX: (714) 833-{)303
Norcomp
3350 Scott Blvd.,
Suite 24
Santa Clara, CA 95054
Tel: (408) 727-7707
FAX: (408) 98S-1947
Norcomp
2140 Professional Drive
Suite 200
Roseville, CA 95661
Tel: (916) 782-8070
FAX: (916) 782-8073
Sonika Electronica of America
925 Hale Place
SuiteA-8
Chula Vista, CA 92013
Tel: (619) 482-8700
FAX: (619) 482-7598

Semtronic Associates, Inc.
1467 S. Missouri Avenue
Clearwater. FL 33516
Tel: (813) 461-4675
FAX: (813) 442-2234
Semtronic Associates, Inc.
3471 NW 55th Street
Ft. Lauderdale, FL 33309
Tel: (305) 731-2484
FAX: (305) 731-1019
Georgia
The Novus Group, Inc.
6115-A Oakbrook Pkwy
Norcross, GA 30093
Tel: (404) 263-0320
FAX: (404) 263-8946
Idaho
Intermountain Technical Marketing
1406 E. First Street
Suite 101
Meridan,lD 83642
Tel: (208) 888-6071
FAX: (208) 888 6074
Illinois
Beta Technology
1009 Hawthorne Drive
Itasca,IL60143
Tel: (708) 25S-9586
FAX: (708) 256-8592

Electromec Sales
Executive Plaza
4403 First Avenue, S.E.
Suite 302
Cedar Rapids, IA 52402
Tel: (319) 393-1637
FAX: (319) 393-1752
Kansas
Rothkopf & Associates, Inc.
1948 E. Santa Fe
Suite H
Olathe, KS 66062
Tel: (913) 829-8897
FAX: (913) 829-1664
Kentucky
Spectra-Com
303UHL Road
Melbourne, KY 41059
Tel: (606) 781-3904
Maryland
Arbotek Associates
1404 E. Joppa Road
Towson, MD 21204
Tel: (301) 825-{)775
FAX: (301) 337-2781
Massachusetts
Mill-Bern Associates
2 Mack Road
Woburn, MA 01801
Tel: (617)932-3311
FAX: (617) 932-{)511

4-11

Sales Information

CMOS Channeled Gate Arrays

FMI Representatives - USA
Michigan
Greiner Associates, Inc.
15324 E. Jefferson Avenue
Suite 12
Grosse Point Park, MI 48230
Tel: (313) 49~188
FAX: (313) 491Hl665

Minnesota
Electromec Sales
1601 E. Highway 13
Suite 200
Burnsville, MN 55337
Tel: (612) 894-<1200
FAX: (612) 894-9352

Missouri
Rothkopf & Associates, Inc.
8721 Manchester Road
SI. Louis, M063144
Tel: (314) 961-4485
FAX: (314)961-4736

New Jersey
BGR Associates
Evesham Commons
525 Route 73
Suite 100
Marlton, NJ 08053
Tel: (609) 983-1020
FAX: (609) 983-1879

(Continued)

Quality Components
116 Fayette Street
Manlius, NY 13104
Tel: (315) 682-8885
FAX: (315) 682-2277
Quality Components
2318litus Ave.
Rochester, NY 14622
Tel: (716) 342-7229
FAX: (716) 342-7227

North carolina
The Novus Group, Inc.
1026 Commonwealth Court
Cary, NC 27511
Tel: (919) 460--7771
FAX: (919) 460--5703

Ohio
Spectra-Com
3809 Wilmington Pike
Suite 209
Kettering, OH 45429
Tel: (513) 29~64
FAX: (513) 299-0865
Spectro-Com
8925 Galloway Trail
Novelty, OH 44072
Tel: (216) 338-5226
FAX: (216) 338-3214

Oregon

Technical Applications & Marketing
91 Clinton Road
Suite1D
Fairfield, NJ 07006
Tel: (201) 575-4130
FAX: (201) 575-4563

L--5quared Limited
15234 NW Greenbrier Pkwy
Beaverton, OR 97006
Tel: (503) 629-<1555
FAX: (503) 645--S196

New York

Texas

Quality Components
3343 Harlem Road
Buffalo, NY 14225
Tel: (716) 837--6430
FAX: (716) 837-0062

Technical Marketing, Inc.
3320 Wiley Post Road
Carrollton, TX 75006
Tel: (214) 387-3601
FAX: (214) 387-3605

4-12

Technical Marketing, Inc.
2901 Wilcrest Drive
Suite 139
Houston, TX 77042
Tel: (713) 763-4497
FAX: (713) 783-5307
Technical Marketing, Inc.
1315 Sam Bass Circle
Suite B-3
Round Rock, TX 78681
Tel: (512) 244-2291
FAX: (512) 338-1596

Utah
Wasatch Representatives
5282 S. 320 West
Suite 0-100
Salt Lake City, ut 84107
Tel: (801) 265-0286
FAX: (801) 26~15

Washington
L-Squared Limited
105 Central Way
Suite 203
Kirkland, WA 98033
Tel: (206) 827-<1555
FAX: (206) 828--6102

Wisconsin
Beta Technology
9401 W Beloit Street
Suite304C
Milwaukee, WI 53227
Tel: (414) 543--S609
FAX: (414) 543-9288

CMOS Channeled Gate Arrays

Sales Informaffon

FMI Representatives - Canada, Mexico and Puerto Rico
canada

Mexico

Puerto Rico

Pipe-Thompson Limited
5468 Dundas SlnIet W.
Suite 206
Islington, Ontario M9B 6E3
Tel: (416) 236-2355
FAX: (416) 236-3387

Solano Electronica (Sonika)
Ermita t039- to
Colonia Chapalita
Guadalajara, JAL. 45042
Tel: (52) 3647-4250
FAX: (52) 3647-3433

Semtronic Associates
Mercantil Plaza Building
Suite 816
Hato Ray, Puerto Rico 00918
Tel: (809) 766-0700

Pipe-Thompson Limited
RR2 North Gower
Ottawa, Ontario KOZ 2TO
Tel: (613) 258-4067
FAX: (613) 258-7649

Solano Electronics, S.A. De C.V.
Cienfuego tl651-A
07300 Mexico City, D.F.
FAX: (52) 5586-8443

..

4-13

..

CMOS Channeled Gate Arrays

Sales Information

FMI Distributors Alabama
Marshall Industries
3313 S. Memorial Highway
Suite 150
Huntsville, AL 35801
(205)881-9235
Repton Electronics
4950 Corporate Drive
Suite I05C
Huntsville, AL 35805
(205) 722-9565

Arizona
Insight Electronics
1515 W. University Drive
Suite 103
Tempe, AZ 85281
(602) 829-1800
Marshall Industries
9830 S. 51 st Street
Suite B121
Phoenix, AZ 85044
(602) 491Hl290

california
Bell Microproducts
18350 Mt Langley
Suite 207
Fountain Valley, CA 92708
(714) 963-0067
Bell Microproducts
550 Sycamore Drive
Milpitas, CA 95035
(408) 434-1150
Insight Electronics
28035 Dorothy Drive
Suite 2
Agoura, CA 91301
(818) 707-2100
Insight Electronics
15635 Alton Parkway
Suite 120
Irvine, CA 92718
(714) 727~111
Insight Electronics
6885 Flanders Drive
Suite C
San Diego, CA 92126
(619) 587-9757
Marshall Industries
9710 Desoto Ave.
Chatsworth, CA 91311
(818)407-4100

4-14

USA
Marshall Industries
9320 Telstar Ave.
EI Monte, CA 91731
(818)307~094

Marshall Industries
One Morgan
Irvine, CA 92718
(714) 458-5308
Marshall Industries
336 Los Caches Street
Milpitas, CA 95035
(408) 942-4600
Marshallinduslries
3039 Kilgore Ave.
Suite 140
Rancho Cordova, CA 95670
(916) 635-9700
Marshall Industries
10105 Carroll Canyon Road
San Diego, CA 92131
(619) 578-9600
Marit Electronics
2070 Ringwood Avenue
San Jose, CA 95131
(408) 434-
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