1991_Fujitsu_Static_RAM_Products 1991 Fujitsu Static RAM Products
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Static RAM Products
1991 Data Book
1991
0:>
FUJITSU
High-Speed CMOS SRAMs
High-Speed SiCMOS SRAMs
Low-Power CMOS SRAMs
Application-Specific CMOS SRAMs
Extended Temperature Range SRAMs
Quality and Reliability
Ordering and Package Information
Sales Information
Appendices -
De~n
Cross Reference Guide for High-S
Information
(CMOS. BiCMOS) SRAMs
..
ID
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FUJITSU
Static RAM Products
1991
Data
Book
Fujitsu Umlted
Tokyo. Japan
Fujitsu Microelectronics. Inc.
Son Jose. California. U.S.A.
Fujitsu Mikroelektronik GmbH
Frankfurt. Germany
Fujitsu Microelectronics Asia PTE Umlted
Singapore
Copyrighl@ 1991 Fujitsu MicroeIecIronic&, Inc., San Jose, califomia
All Rigills Reserved.
Cilalit diagrams using Fujitsu products are Included to ilultrale typical semlconduclar applications. Information sufficient for
conSlrUclion purposes may not be shown.
The information contained in 11118 document hu bean CBI8Iuly chackad and is believed to be reliable. However, Fujitsu
MicroeIeclranlca, Inc. _urnes no responsibility for Inacc:urac:ies.
The information conveyed in 1I1i8 document does not convey any license WIder Ihe copyrights, patent rights or II'IIdemarks
claimed and owned by Fujitsu Umitad, its subsidiaries, or Fujitsu Microeleclranics, Inc.
Fujitsu MicnIeIecIronic, Inc. resel'Y8ll1he righllD change producta or apecificationl wilhout notice.
No pa101111is publication may becopiedorraproclucedln any fonn orlly any I1188III, orlnlnllamld lDany 1I11rdpa1ywithout prior
written consent of Fujitsu Microeleclranics, Inc.
This document i8 published by Ihe Publication, Department, Fujitsu MicroeIecIronic, Inc.,
3545 Nor1h FiratStraeI, San Jose, California, U.S.A. 96134-1804; U.S.A.
Printed in 1he U.S.A.
Edition 1.0
PREFACE
This data book contains the latest product information for Fujitsu's line of Static RAM ICs. This year's
edition, however, does not include a section for SRAM modules. Both DRAM and SRAM modules are now
in a Modules Data Book which you can obtain from your nearest Fujitsu Sales Office or Sales
Representative. (See the Sales Information listing in this book.)
In addition to the collection of SRAM data sheets, you will find valuable information on ordering and
expanded packaging descriptions, both in the Order Information section. A cross reference for SRAMs is
in Appendix 4, and again in each respective product section. You will also find a new technical paper, Fast
SRAMs in Zero Wait-State Memory Intefaces, in the D,esign Information section.
If you are interested in obtaining other Fujitsu product Information, see the publications listing on the
following pages for titles and brief descriptions of other Fujitsu product literature. To obtain a copy of any
of the documents, call one 01 our sales offices.
m
FUJITSU PRODUCT PUBLICATIONS
The fOllowing is a list of the product publications available from Fujitsu Microelectronics, Inc. Call your nearest FMI Sales
Office or Sales Representative to order any document(s) you need. (See the Sales Information section for phone
numbers.)
AfEAfORYPRODUCTS
Dynamic RAM Products Data Book
Contains product data sheets for NMOS and CMOS DRAMs,
Including 1M and 4M devices, and MOS appIication-specWic
Static RAM Products Data Book
Contains product data sheets for high-speed CMOS and
BiCMOS SRAMs, low-power CMOS SRAMs and applicationspecific SRAMs.
ECl RAM Products Data Book
Contains product data sheets for ECl and TTL bipolar ECl
RAMs, BiCMOS ECl RAMs, and application-specWic RAMS
including self-timed RAMs (STRAMs).
Programmable Memory Products Data
Book
Contains product data sheets for programmable ROMs (including
registered and wide-temperature range PROMs); CMOS maskprogrammable ROMS, OTP ROMs, erasable PROMs, and
EEPROMs; NMOS erasable PROMs and non-volatile RAMs.
Memory Modules Data Book
Contains product data sheets for CMOS DRAM modules (including high density and low profile) and CMOS SRAM modules.
Memory Card Products Data Book
Contains product data sheets and programming information for
68-pin JEIDA and PCMCIA standard memory cards and connectors and for 38-pin memory cards.
Power Transistor Products Data Book
Contains product data sheets for RETs, Darlington arrays, and
FEls.
linear Products Data Book
Contains product data sheets for op amps, comparators, automotive audio amps, power supply controls, motor drivers, disk drivers, and converters (AID, D/A, AID-D/A, and FN).
RAMs.
Linear Products Selector Guide
Presents an overview of linear products.
Telecommunication Devices Data Book
Contains product data sheets for bipolar presealers and VCOs,
CMOS PlLs, BiCMOS single-chip PlLs and Presealers.
CODECs, CMOS telephone ICs, and cellular mobile radio ICs.
Telecommunication Devices Selector
Guide
Presents an qverview of telecommunication products and piezoelectric devices.
Interface and Logic Products Selector
Guide
Presents an overview of logic and interface devices.
CMOS 4-bit Microcontrollers Data Book,
Vol. I
Contains product information, including the development tool for
the MB8850 and MB88200 families of 4-bit microcontrollers.
CMOS 4-biI Microcontrollers Data Book,
Vol. II
Contains product information, including the development tool for
the MB88500 family of 4-bit microcontrollers.
CMOS 4-bit Microcontrollers Selector
Guide
Presents an overview of the MB88500 (high end), MB8850 (midrange), and MB88200 (low end) families of 4-bit microcontrollers.
'"
FUJITSU PRODUCT PUBLICATIONS (Continued)
ASIC PRODUCTS
CMOS Channeled Gate Arrays Data Book
and Design Evaluation Guide
Contains product information for UHB Series High Drive CMOS
Gate Arrays and CG10 Series High Drive CMOS Gate Arrays.
CMOS Channelless Gate Arrays Data
Book and Design Evaluation Guide
Contains product information for AU Series CMOS Series Gate
Arrays and CG21 Series CMOS Gate Arrays.
ASIC CMOS Products Selector Guide
Presents an overview of CMOS channeled and channelless gate
arrays and standard cell products.
BiCMOS Gate Arrays Data Book and
Design Evaluation Guide
Contains product information for BC Series BiCMOS Gate
Arrays and BC-H Series BiCMOS Gate Arrays.
ECl Gate Arrays Data Book and Design
Evaluation Guide
Contains product information for ET Series ECl Gate Arrays,
H Series ECl Gate Arrays, Ultra-High Performance ECl Gate
Arrays, and VH Series ECl Gate Arrays.
ASIC Bipolar Products Selector Guide
Presents an overview of BiCMOS and ECl gate array products.
ASIC SOFTWARE
The ASIC GalleryTM (catalog)
Discusses the trend in ASICs: migration from using gates as
primitives to using lSI and even VLSI macros as design elements.
The ASIC Design Environment (catalog)
Provides an overview of the third-party tools that work in concert
with Fujitsu's proprietary tools, ViewCADTM, BankCADTM, and
FAME. Also included are product profiles explaining how the
third-party tools fit within the design framework.
ViewCAD User's Guide
Provides a basic understanding of Fujitsu's proprietary CAD/CAE
system, ViewCAD. This book provides information necessary to
design, test, simulate, and analyze circuits using Fujitsu's unit cell
libraries for AU, UHB, CGl0, CG21, and CG31 CMOS technologies.
ViewCAD Installation Guide
Explains how to install Fujitsu's proprietary CAD/CAE system,
ViewCAD.
CMOS ASIC Reference Manual for
Valid
Provides a basic understanding of the Valid System on the Sun
platform as it interfaces with Fujitsu programs to build circuits
using Fujitsu's unit cell libraries for AU and UHB CMOS technologies.
FAME User's Guide
Provides a basic understanding of the Fujitsu ASIC Management
Environment (FAME) software as it interfaces with third-party
tools (Sun or PC) to build circuits using Fujitsu's unit cell libraries.
FAME Reference Manual
Provides installation and directory information for the Fujitsu
ASIC Management Environment (FAME) software, which uses
third-party tools (Sun or PC) to build circuits using Fujitsu's unit
cell libraries.
Synopsys User's Guide
Provides a basic understanding of the Synopsys® system as it
interfaces with Fujitsu programs to build circuits using Fujitsu's
un~ cell libraries.
v
FUJITSU PRODUCT PUBLICATIONS (Continued)
ASIC SOFTWARE (Continued)
Verilog-XL User's Guide
Provides a basic understanding of the Verilog-XL® system as it
interfaces with Fujitsu programs to build circuits using Fujitsu's
unit cell libraries.
Futur. Publication.
For Fujitsu Microelectronics, Inc.:
Master Product GuidelCatalog (1991)
Presents an overview of the entire range of products offered by
Fujitsu Microelectronics.
For Memory Products:
Hybrid Products (1991)
Presents Fujitsu's hybrid products and discusses thick- and thin-film
capabilities.
For ASIC Software:
ASIC Design Environment
Data Book (1991)
Provides detailed information about the ASIC Design Methodology
at Fujitsu. It contains an overview of the third-party tools that work
in concert with Fujitsu's proprietarylools, ViewCAD, BankCAD, and
FAME. Also included are product profiles explaining how the thirdparty tools fit within the design framework.
ASICOpen™ Catalog (1991)
Provides information about the Fujitsu ASIC Design framework. It
explains the design processes between two third-party tools, Synopsys and Verilog-XL, and Fujitsu's proprietary tools, ViewCAD
and BankCAD.
Synopsys® Is a ragistared trademark 01 Synopsys, Inc.
Verilog-XL@ is a regiBIIIr8d trademark 01 Cadence Design Sys18ms, Inc.
VlewCAOTM and BankCAOTM are trademarks of FujiISU Umi18d.
ASICOpen™ III1d ASIC GalleryTM are trademarks of FujilBu Maoelectronics, Inc.
iii
Contents and Alphanumeric Product List
SRAM Products
Introduction - Static RAM Products .................................•......... xi
Section 1 - High-Speed CMOS SRAMs - At a Glance ...................... 1-1
High-Speed CMOS SRAMs Cross Reference Guide ............................. 1-3
MB81C67-35/-45/-55
16K x 1 bit SRAM ............................ 1-5
MB81 C68A-25/-30/-35
4K x 4 bits SRAM .............. , ............ 1-17
MBB1C69A-251-30/-35
4K x 4 bits SRAM ........................... 1-29
MB81C71A-251-30/-35
64K x 1 bit SRAM .............. , ............ 1-41
MB81C74-25/-30/-35
16K x 4 bits SRAM .......................... 1-53
MB81 C75-25/-30/-35
16K x 4 bits SRAM .......................... 1-63
8K x 8 bits SRAM ........................... 1-75
MBB1C78A-35/-45
MB81C79A-35/-45
8K x 9 bits SRAM ........................... 1-91
256K x 1 bit SRAM ......................... 1-107
MBB1C81A-25/-35
MB81C84A-25/-35
64Kx4bitsSRAt.A ......................... 1-117
MBB289-251-35
32K x 9 bits SRAM ......................... 1-127
MB8298-251-35
32K x 8 bits SRAM ......................... 1-137
MBB299-251-35
32K x 9 bits SRAM ......................... 1-147
Section 2 - High-Speed BiCMOS SRAMs - At a Glance .................... 2-1
High-Speed BiCMOS SRAMs Cross Reference Guide ........................... 2-3
MB82B001-25/-35
1M x 1 bit SRAM ............................. 2-5
MB82B005-25/-35
256K x 4 bits SRAM ......................... 2-13
MB82BOO6-251-35
256K x 4 bits SRAM ......................... 2-21
MBB2B78-151-20
8K x 8 bits SRAM ........................... 2-29
8K x 9 bits SRAM ........................... 2-39
MB82B79-15/-20
MB82B81-15/-20
256K x 1 bit SRAM .......................... 2-49
MB82B84-151-20
64K x 4 bits SRAM .......................... 2-57
MB82B85-151-20
64K x 4 bits SRAM .......................... 2-65
32K x 8 bits SRAM .......................... 2-75
MB82B88-15/-20
MB82B89-151-20
32K x 9 bits SRAM .......................... 2-77
MBB2B008-25
128K x 8 bits SRAM ......................... 2-79
MB82B009-25
128K x 9 bits SRAM ......................... 2-81
MBB2B201-251-35
4M x 1 bit or 1M x 4 bits SRAM ................. 2-83
MBB2B206-251-35
1M x 4 bits SRAM ........................... 2-85
vii
Contents and Alphanumeric Product List (Continued)
SRAM Products
At a Glance ........................... 3-1
Low-Power CMOS SRAMs Cross Reference Guide ............................. 3-3
MB8464A -SO, -SOL and LL
8K x 8 bits SRAM .............................. 3-5
-10, -10L and LL
-15, -15L and LL
32K x 8 bits SRAM .............. '.............. 3-17
MB84256A-70, -70L and lL
-10, -10L and LL
-12, -12L and LL
-15, -15L and LL
MBB41000-80 and -SOL
128K x 8 bits SRAM ........................... 3-29
-10, -10L
-12, -12L
Section 3 - Low-Power CMOS SRAMs -
Section 4 -Application Specific CMOS SRAMs MB81C51-25/-30
MB81C79B-35I-45
MB8279RT-20/-25
MB8287-25/-35
MB8421-90, -90L and LL
-12, -12L and LL
MB8422-90L and LL
-12, -12L and LL
MB8431-90, -90L and LL
-12, -12L and LL
MB8432-90, -90L and LL
-12, -12L and LL
MB8441-451-55
At a Glance ...............
2K x 8 bits Dual-Port SRAM .................. 4- 53
2K x 8 bits Dual-Port SRAM ................... 4-67
2K x 8 bits Dual-Port SRAM .................. 4- 67
8K x 8 bits Dual-Port SRAM ................... 4-85
Section 5 - Extended Temperature Range SRAMs MB8464A-10-X and -10LL-X
-15-X and -15LL-X
MB84256A-70-X and -70LL-X
-10-X and -10LL-X
Section 6 - Quality and Reliability -
4-1
512 Entry x 4 Way or 1024 Entry x 2 way TAG RAM . 4-3
8K x 9 bits High-Speed SRAM ................. 4-17
8K x 9 bits High-Speed STRAM ................ 4-29
32K x 8 bits High-Speed SRAM with
Parity Generator and Checker ............... 4-41
2K x 8 bits Dual-Port SRAM ................... 4-53
At a Glance . ............... 5-1
8K x 8 bits SRAM ............................ 5-3
32K x 8 bits SRAM ......•................... 5-15
At a Glance ..........................
6-1
Quality Control at Fujitsu .............•..................................... 6-3
Quality Control Processes at Fujitsu .......................................... 6-4
At a Glance ...............
7-1
SRAM IC Product Marking ...................... ; ..........................
Ordering Code (Part Number) ..........•....................................
Package Codes - Plastic .•.....•..•..•......•.••.....•....................
Package Codes - Ceramic ...•...•.. ; ...•.•...•..•.......•...•.............
7-3
7-3
7-4
7-5
Section 7 - Ordering and Package Information -
11m
Contents and Alphanumeric Product List (Continued)
SRAM Products
Section 8 - Sales Information - At a Glance . .............................
8-1
Introduction to Fujitsu ..................................................... 8-3
Fujitsu Limited (Japan) ................................................. 8-3
Fujitsu Microelectronics, Inc. (U.S.A.) ...................................... 8-4
Fujitsu Electronics Devices Europe ....................................... 8-6
Fujitsu Microelectronics Asia PTE Ltd. (Singapore) ........................... 8-8
Integrated Circuits Corporate Headquarters - Worldwide .......................... 8-9
FMI Sales Offices for North and South America •............................... 8-10
FMI Representatives - USA ............•............•..................... 8-11
FMI Representatives - Canada ............................................. 8-13
FMI Representatives - Mexico ............................................. 8-13
FMI Representatives - Puerto Rico ......................................... 8-13
FMI Distributors - USA ................................................... 8-14
FMI Distributors-Canada ................................................ 8-18
FMG Sales Offices for Europe, FML and FMIL ................................. 8-19
FMG Distributors - Europe, FML and FMIL ................................... 8-20
FMAL Sales Offices for Asia, Australia, and Oceania ............................ 8-22
FMAL Representatives - Asia and Austraila ................................... 8-23
FMAL Distributors - Asia ................................................. 8-24
Section 9 - Appendices - Design Information - At a Glance ................
Appendix 1.
9-1
Design Applications. Internally timed RAMs build fast writeable control stores ....... 9-3
Appendix 2.
Application Note: Separate Data Inputs and Outputs SRAMs Provide New
Architectural Solutions for System Designers ................................. 9-9
Appendix 3.
Application Note: Fast SRAMs in Zero Wait-State Memory Interfaces ............. 9-27
Appendix 4.
Cross Reference Guide for High-Speed (CMOS, BiCMOS) SRAMs .............. 9-37
Ix
Contents and Alphanumeric Product List
(Continued)
SRAM PRODUCTS
Alphanumeric List of Fujitsu Part Numbers
MB81C51-25/-30 . . . . . . . . . . .. 4-3
MB81C67-35/-45/-55 . . . . . . . .. 1-5
MB81C68A-251-301-35 ...... 1-17
MB81C69A-251-301-35 ...... 1-29
MB81C71A-251-301-35 ...... 1-41
MB81C74-25/-301-35 . . . . . . •. 1-53
MB81C75-25/-301-35 . . . . . . .. 1-63
MB81C78A-351-45 ......... 1-75
MB81C79A-351-45 ......... 1-91
MBS1C79B-351-45 ......... 4-17
MB81C81A-251-35 ........ 1-107
MBS1C84A-251-35 ......... 1-117
MB82B001-251-35 ........... 2-5
MB82B005-251-35 .......... 2-13
MBS2B006-251-35 . . . . . . . . .. 2-21
MB82B008-25 ............. 2-79
MB82B009-25 ............. 2-81
MB82B7S-151-20 . . . . . . . . . .. 2-29
MB82B79-151-20 . . . . . . . . . .. 2-39
MBS2B81-151-20 ........... 2-49
MB82B84-151-20 . . . . . . . . . .. 2-57
MB81B85-151-20 . . . . . . . . . .. 2-65
MB81B88-151-20 ........... 2-75
MB82B89-151-20 . . . . . . . . . .. 2-77
MB82B201-251-35 .......... 2-63
MB82B206-251-35 . . . . . . . . .. 2-85
MB8279RT-201-25 . . . . . . . . .. 4-29
It
MB8287-251-35 ............. 4-41
MB8289-251-35 ............ 1-127
MB8298-251-35 ............ 1-137
MB8299-251-35 ............ 1-147
MBB421-90, 90l and II
-12, -12l and II ..... 4-53
MB8422-90, -90l and II
-12, -12l and II ..... 4-53
MB8431-90, -90l and II
-12, -12l and II ..... 4-67
MB8432-90, -90 l and II
-12, -12l and II ..... 4-67
MB8441-45/-55 ............. 4-85
MB8464A-SO. -SOL and II
-10, -10l and II
-15. -15l and II .... 3-5
MB8464A-10-X and -10ll-X
-15-X and -15ll-X ... 5-3
MB84256A-70, -70l and II
-10, -10l and II
-12, -12l and II
-15, -15l and II ... 3-17
MB84256A-70-X, -70ll-X
-10-X, -10ll-X .... 5-15
MB841000 -SO and -SOL
-10 and -10l
-12 and -12l ...... 3-43
Introduction
I
I
Page
Tille
xl
FU~I&U'B Static RAM Products
xi
Introduction
xii
Static RAM Data Book
Fujitsu's Static RAM Products
Introduction
Fujitsu manufactures a wide range of integrated circuits that
includes linear products, microprocessors, telecommunications
circuits, ASICs, high-speed ECl logic, power components
(consisting of both discrete transistors and transistor arrays),
and both static and dynamic RAMs.
-rhe static RAM product line offers devices for use in a wide
range of applications. These memories are manufactured to
meet the high standard of quality and reliability that is found
in all Fujitsu products.
This data book includes product information on the following
SRAM products:
High-speed CMOS SRAMs
Fujitsu's high-speed CMOS SRAMs offer the advantages of
low power diSSipation, low cost, and high performance.
Features include TTL compatibility and a separate
chip-select pin that simplifies multipackage systems design.
High-speed BICMOS SRAMs
Advanced BiCMOS technology adds ultra-fast access times
to CMOS low power dissipation in Fujitsu's new family of
static RAMs. Most devices feature an automatic power-down
mode and are generally available in small outline packages
with J-Ieads (SOJ).
Low-speed CMOS SRAMs
Our Iow-power CMOS SRAMs are ideally suited for use in
microprocessor systems and other applications where fast
access time and ease of use are reqUired. The memories
use asynchronous circuitry and may be maintained in any
state for an indefinite period of time.
Application-Specific CMOS SRAMs
To address the s).'stem needs of cache memories, Fujitsu's
application-specific memory line includes both cache TAG
RAM and high-speed static RAM, as well as dual-port RAMs
for multiprocessor systems.
xiii
Fujitsu's Static RAM Products (Continued)
Extended Temperature Range SRAIIa
For applications requiring devices that operate in the
industrial temperature range, Fujitsu offers a selection of
TTl-compatible CMOS SRAMs. These devices are specified
for operation In the range from -40°C to +85°C. The
des~nator "-X", following the standard part number,
identifies SRAMs that operate In the extended temperature
range. See specific data sheats for full product specification.
Section 1
..
High-Speed CMOS SRAMs - At a Glance
Maldmum
Pega
Device
A_
Capacity
Tlma(na)
(Organization)
1-3
High-Spsed CMOS SRAMs Product Cross RefeffHICB
1-6
MB81C67-35
35
-45
-65
45
55
1-17
1-,29
1-41
1-63
1-s3
MB81C68A-25
25
--30
30
-35
35
MB81C69A-25
25
--30
30
-35
35
MB81C71A-,25
25
--30
30
-35
35
MB81C74-25
25
--30
30
-35
35
MB81C75--,25
25
--30
30
35
-35
1-75
1-91
1-107
1-117
1-127
1-137
1-147
PlICluIga
Opllons
16384 bits
(16384 x 1)
2~in
~in
16384 bits
(4096x4)
2O-pin
DIP
Plastic
Ceramic DIP
2O-pad Ceramic LCC
2~in
Plastic
DIP,ZIP
Ceramic CERDIP
2~ad Ceramic LCC
16384 bits
(4096 x 4)
DIP
2~in Plastic
2O-pin Ceramic CERDIP
2O-pad Ceramic LCC
65536 bits
(65536 xl)
22-pin Plastic
DIP
24-pin Plastic
SOJ
22-pad Ceramic LCC
65536 bits
(16384 x4)
22-pin Plastic
DIP
22-pad Ceramic LCC
65536 bits
(16384 x 4,oE)
24-pin
24-pin
Plastic
Plastic
DIP,SOJ
LCC
MB81C78A-35
35
-45
45
65536 bits
(8192 x8)
28-pin Plastic
DIP, SOP, SOJ
32-pad Ceramic LCC
MB81C79A-35
-45
35
45
73728 bits
(8192 x9)
28-pin Plastic
DIP, SOP, SOJ
32-pad Ceramic LCC
MB81C81A-,25
-35
25
262144bils
(262144 x 1)
24-pin
Plastic
DIP,SOJ
35
MB81C84A-,25
-35
262144 bits
(65536 x 4)
24-pin
Plastic
DIP,SOJ
35
MB8289-25
-35
294912 bits
(32768 x 9)
32-pin
Plastic
DIP,SOP
35
MB8298--25
-35
25
35
262144b~s
28-pin
Plastic
DIP, SOP, SOJ
(32768x8)
MB8299-25
-35
32-pin
Plastic
DIP, SOP, SOJ
35
25
25
25
294912 bits
(32768x9)
1-1
High-speed CMOS SRAMs
1-2
Static RAM Data Book
High-speed CMOS SRAMs
Static RAM Data Book
High-Speed CMOS SRAMs Product Cross Reference
..
64K Static RAMs
FuJitsu Part Numbers
MB81C71A
(S4Kx 1)
MB81C74
(lSKx4)
MB81C75
(lSKx4l0E)
MB81C78A
(8Kx 810E)
M81C79A
(8Kx 9/0E)
Cypress
CY7C187
CY7Cl64
CY7C166
CY7C185
CY7C182
Hitachi
HM6287
HM6288
HM6289
lOT
IOT7187
IOT7188
IOT7198
IOT7164
IOT7169
Micron
MT5C6401
MT5C6404
MT5C6405
MT5C6408
Vendors
Mitsubishi
M5M5187A
M5M5188A
M5M5189A
M5M5178
M5M5179
Motorola
MCM6287
MCM6288
MCM6290
MCM6264
MCM6265
NEC
IlP04361
J.1P04362
J.LP04363
Performance
P4C187
P4C188
P4C198
P4CI64
P4CI63
Samsung
KM6165
KM6465
KM6466
KM6865
Sharp
LH5261
LH5262
LH5267
LH5165 and
5164
Sony
CXK5164
CXK5464
CXK5465
CXK5863
CXK5971
Toshiba
TC5562
TC55416
TC55417
TC5588
TC5589
256K Static RAMs
FuJitsu Part Numbers
Vendors
MB81C81A
(256Kx 1)
MB81C84A
(S4K x 4)
MB8298
(32Kx 810E}
Cypress
CY7C197
CY7C194
Hitachi
HM6207
HM6208
HM62832
lOT
IOT71257
IOT71258
IOT71256
Micron
MT5C2561
MT5C2564
MT5C2568
Mitsubishi
M5M5257
M5M5258
Motorola
MCM6207
NEC
MCM6208
MB8299
(32Kx9/0E)
CY7C199
MCM620S
IOT71259
MCM6205
J.LP043254
Performance
P4C1257
P4C1258
P4CI256
Samsung
KM61257
KM64257
KM68257
Sharp
LH52251
LH52252 and
52255
LH52254 and
52258
Sony
CXK51256
CXK54256
CXK58258
CX58289
TC55464
TC55328
TC55329
Toshiba
1·3
High-speed CMOS SRAMs
1·4
Static RAM Data Book
OJ
January 1990
Edition 3.0
FUJITSU
DATA SHEET
MB81 C67-351-451-55
CMOS 16K-BIT HIGH-SPEED SRAM
..
16K Words x 1 Bit High-Speed CMOS Static Random
Access Memory
~
The FujRsu MB81C67 is a 16.384 words x 1 bR static random access memory
fabricated wRh a CMOS silicon gate process. All pins are TTL compatible and a single
+5 V power supply is required.
A chip select (CS) pin permits the selection of an individual package when outputs are
OR-tied. and automatically powers down the device. The MB81C67 offers low power
dissipation. low cost. and high performance.
•
Organization:
•
Static operation: no clocks or refresh required
•
Access time:
•
CERAMIC PACKAGE CERDIP
DlP-20C-C03
16.384 words x 1 bit
~
35 ns max. (MB81C67-35)
45 ns max. (MB81C67-45)
55 ns max. (MB81C67-55)
,
CERAMIC PACKAGE
LCC-20C-F01
Single +5 V power supply ±1 0% tolerance
•
TTL compatible inputs and outputs
•
Three-state outputs wRh OR-tie capacRy
•
Chip select for simplified memory expansion. automatic power down
•
Electrostatic protection for all inputs and outputs
•
Standard 2O-pin Plastic Package:
DIP
MB81C67-xxP
PLASTIC PACKAGE
DIP-20P-M01
o Standard 20-pad Ceramic Package:
LCC
MB81C67-xxTV
•
Standard 20-pin Ceramic Package:
CERDIP MB81C67-xxZ
•
Pin compatible wRh Fujitsu MB8167A
PIN ASSIGNMENT
Absolute Maximum Ratings (See Note)
Symbol
Value
Unit
Supply Voltage
Rating
Vce
-0.5 to +7.0
V
Input Voltaae on any pin wRh
respect to ND
VIN
-{3.5 to +7.0
V
VOUT
-0.510+7.0
V
loUT
±50
mA
Output Vott~e on any pin wRh
respect to G D
Output Current
Power Dissipation
Temperature Under Bias
I
Storage Temperature Ceramic
Range
I Plastic
Po
1.2
W
TSIAS
-10 to +85
°C
TSTG
-65 to +150
-45 to +125
°C
Note: Pennanent device damage may occur if absolute maximum ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in !he operation
sections of !his data sheet. Exposure to absolute maximum rating conditions for extended periods may affect dellioa reliability.
This devIca contains circuitry to protect the Inputs agalnst
damage due to high static voltages or electric fields. However, h
II advised that normaf precau:lona be takan to avoid appUc:atIon
01 any vohage hlghSl" than maximum rated voltages to this high
lrJ1)8dance circuit.
CCpyrIght © 1990 by FUJrrsU LIMITED /Old Fujitsu M_1co, Inc.
1-5
MB81C67-35
MB81C67-45
MB81C67-55
Fig. 1 ...... MB81C67 BLOCK DIAGRAM
A,.
-----------ILA)----I
A13
---------1~~----~
•
~-----------------~I~~----I
ROW
SELECT
A, ----------------1~~-------~
~------------------I~~----~
v""
GND
CELL ARRAY
128 ROWS
128 COLUMNS
•
•
~--------------~~----------I
~--------------~~---L
D'N
..
..
____~
---------1
COLUMN 110 CIRCUITS
1 - - - 0 Dour
COLUMN SELECT
INPUT
DATA
CONT.
WE -
....+--i
POWER
DOWN
CIRCUIT
TRUTH TABLE
CAPACITANCE
Parameter
Input Capacitance (V .. =OV)
1-6
CS
WE
MODE
OUTPUT
POWER
H
X
NOT SELECTED
HIGH-Z
STANDBY
L
L
WRITE
HIGH-Z
ACTIVE
L
H
READ
Dour
ACTIVE
(TA= 25°C, f= 1MHz)
Symbol
Typ
Max
Unit
C'N
S
pF
CS Capacitance (Vci=OV)
Cos
7
pF
Output Clilpacitance (Vour=OV)
GoUT
8
pF
MB81C67-35
MB81C67-45
MB81C67-55
RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter
Symbol
Min
Typ
Max
Un"
Supply Voltage
V""
4.5
5.0
5.5
V
Input Low Voltage
V'L
-3.0'
0.8
V
Input High Voltage
V..
2.2
6.0
V
Ambient Temperature
T.
0
70
"C
..
'-3.0V Min. for pulse width less than 2Ons. (V'L Min~1.0V at DC level)
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
Input Leakage Current
V,N=OV to Vee
lu
-2.0
2.0
jIA
Output Leakage Current
CS=V'H.
VOUT=OV to Vee
11.0
-2.0
2.0
jIA
Active Supply Current
CS=V'L. IOUT=OmA
V1N=V1L or V1H
lee,
25
40
mA
Operating Supply Current
CS=V'L. IOUT=OmA
Cycle=Min. CL=OpF
IC02
35
60
mA
ISB1
2
15
mA
15
25
mA
0.4
V
Standby Supply Current
Cs;;'V~.2V
V,N?,VCC ..(j.2Vor V..s0.2V
Standby Supply Current
CS=V'H.
I...
Output Low Voltage
IOL=16mA
VOL
Output High Voltage
IOH~mA
VOH
2.4
V
1-7
MB81C67-35
MB81C67-45
MB81C67-55
AC TEST CONDITIONS
Input Pulse Levels:
Input Pulse Rise And Fall Times:
Timing Measurement Reference Levels:
Output Load:
0.6Vto 2.4V
5ns
Input
: 1.5V
Output : 1.5V
Fig.2
Load II
Load I
2V
2V
~~
~~
=: loon
:: loon
DOUT
-I'-
-I'-
30pF (Including Scope
and jig capacitance)
5pF (Including Scope
and jig capacitance)
(For 1Hz. Iu. Iwz and low)
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE *1
MB81C67-35
Parameler
MB81C67-05
Unll
Min
Read C~cle Time *2
MB81C67-45
Symbol
IRe
Address Access Time '3
1M
Max
Min
Max
35
45
Chip Select Access Time '4
t..cs
Output Hold from Address Change
to..
5
5
5
Chip Selection 10 Output in Low-Z '5
Iu
5
5
5
Chip Deselection 10 Output in High-Z '5
1Hz
0
Chip Selection 10 Power Up
t..u
0
Chip Deselection 10 Power Down
"'.
Nole:
*1
*2
*3
"4
*5
35
25
45
0
25
0
30
Max
55
45
35
Min
0
ns
55
ns
55
ns
ns
ns
30
ns
0
40
ns
50
WE is high for Read cycle.
All Read cycle are determined from the lasl address transition 10 the first address transition of the next address.
Device is continuously selected. CS=V...
Address valid prior 10 or coincident with CS transition low.
Transition is measured at the point of ±50OmV from steady state Voltage.
ns
MB81C67-35
MB81C67-45
MB81C67-55
READ CYCLE TIMING DIAGRAM *1*2
READ CYCLE: ADDRESS CONTROLLED ·3
..
ADDRESS
PREVIOUS DATA VALID
DATA VALID
READ CYCLE: CS CONTROLLED·4
t..cs - - - - - I
HIGH-Z
Dour
Ipu
Icc
50%
I..
~
Nole:
*1
*2
*3
*4
·5
: Undefined
WE is high for Read cycle.
All Read cycle are determined from the last address transition 10 the first address transition of the next address.
Device is continuously selected, CS=V L •
Address valid prior 10 or coincident with CS transition low.
Transition is measured at the point of ±500mV from steadY state voltage.
1-9
MB81C67-35
MB81C67-45
MB81C67-55
WRITE CYCLE "1'2
MB81C67-35
P....metar
MB81C67-t5
MB81C67-05
Symbol
Unll
Min
Max
Min
Max
Min
Max
Wrila Cycle Time '3
!we
35
45
55
ns
Chip Selection to End of Wrila
lew
30
35
50
ns
Address Valid to End of Wrila
lAw
30
35
50
ns
Address Setup Time
t..
0
0
0
ns
Wrila Pulse Width
'".
20
25
30
ns
low
20
20
25
ns
Wrila Recovery Tim",
IwA
0
0
0
ns
Data Hold Time
to..
0
0
0
ns
Wrila Enable to OutpUI in High-Z '4
Iwz
0
25
0
25
0
30
ns
OutpUI Active from End of Wrila '4
low
0
25
0
25
0
30
ns
Data Valid to End of Wrila
WRITE CYCLE TiMING DIAGRAM '1'2
WRITE CYCLE: WE CONTROLLED"
!we
ADDRESS
~
~
lew
'\ '\\ 1\\
11rLLLLLLLL
lAw
I-
t.. ...
I-t::
"'"
~\
!ott
I--Iow
DATA VALID
D'N
I-- Iwz"
DOUT
l... low"
~
Nole:
1-10
'1
'2
'3
'4
kxxx
~_HIG_~
: Undefined
CS or WE must be high during address tJansition.
If CS goes high simultaneously with WE high. the output remains in high impedance stala.
All WriIB cycle are delarmined from the last address 1ransition to the first address transition of next address.
Transition is measured at the point of ±500mV from steady stala voltage.
MBB1C67-35
MBB1C67-45
MBB1C67-55
WRITE CYCLE TIMING DIAGRAM '1'2
WRITE CYCLE: CS CONTROLLED
·3
..
twe
ADDRESS
lew
CS
tOH
D'N
HIGH-Z
HIGH-Z
DOUT
~
Nole:
'1
'2
'3
'4
: Undenfined
CS or WE must be high during address Iransistion.
If CS goes high simultaneously with WE high. the output remains in high impedance state.
All Write cycle are determined from the last address Iransistion to the lirst address transition of next address.
Transition is measured at the point of ±500mV from steady state voltage.
1-11
MB81C67-35
MB81C67-45
MB81C67-55
TYPICAL CHARACTERISTICS CURVES
Fig. 3 -NORMAUZED ACCESS TIME
va. SUPPLY VOLTAGE
Fig. 4 - NORMAUZED ACCESS TIME
va. SUPPLY VOLTAGE
w 1.2
w
::;;
i=
::;;
i=
~ 1.11--~--+_-----4
~
N
i1.o - - - - -
!
~ 0.9
::i
~II:
j
j
0.8'--_ _ _ _......_ _ _ _ _....
4.5
5.0
Vee. SUPPLY VOLTAGE (V)
w 1.2
'"'"w
0
4.5
w 1.2
V
c(
0
w 1.0
N
::i
~
:/"
0
0
....... V
c(
./'
0
w 1.0
N
V
::i
~
:/"
V
II:
0 0.9
z
j
j
0.8
o
0.8
20
40
60
80
100
T•• AMBIENT TEMPERATURE (DC)
20
40
60
80
100
Fig. 8 - NORMAUZED POWER SUPPLY CURRENT
va. SUPPLY VOLTAGE
!z
!z
ow
WII:
o
T•• AMBIENT TEMPERATURE (DC)
Fig. 7 - NORMAUZED POWER SUPPLY CURRENT
va. SUPPLY VOLTAGE
T.=25OC
fil~
NII:
::i:;)
/
gj
w 1.1
II:
0 0.9
z
~ 0
5.5
Vee,,4.5V
::;;
i=
/
1.1
5.0
Vee. SUPPLY VOLTAGE (V)
Fig. 6 - NORMAUZED ACCESS TIME
va. AMBIENT TEMPERATURE
Vcc=4.5V
0
1------+------1
0.8'--_ _ _ _......_ _ _ _ _....
5.5
Fig. 5 - NORMAUZED ACCESS TIME
va. AMBIENT TEMPERATURE
::;;
i=
--
I----~I----~
8
oc(
oW
1.1 t-----iI---:lr7"o...--t
II:~
00.
zo.
~
g; 1.25 1------+------71
~~
II:-'
~&
1.0
I-_===~~oe::::;;=====::=-!
j ~ 0.75
1£------+------1
0.5
L -_ _ _ _- ' -_ _ _ _-.J
!iii]l
gi]l
-II:
-w
~II:
a.
a.
-w
j~
5.0
Vee. SUPPLY VOLTAGE (V)
1-12
1.1
o
5.5
4.5
5.0
Ve<;. SUPPLY VOLTAGE (V)
5.5
MB81C67-35
MB81C67-45
MB81C67-55
Fig. 9 - NORMAUZED POWER SUPPLY CURRENT
va. AMBIENT TEMPERATURE
rr
1.1 .----.---~--..---...,
Fig. 10 - NORMALIZED POWER SUPPLY CURRENT
VL AMBIENT TEMPERATURE
10
w
~
Vcc=5.SV
rr
w
Il.I-
ez
ww
5:1-
Oz
Il. w
err
wrr
Nrr
::::;rr
~5
~~
~5
~~
rrll.
zll.
N~
.]Ul
Oil.
j
j
/
Z:::l
·Ul
O.SI...-_-'-_ _-'-_ _L..-_-A
o
20
40
60
80
TA• AMBIENT TEMPERATURE (CC)
..
20
40
60
SO
100
TA• AMBIENT TEMPERATURE (CC)
FIg. 12-0UTPUTVOLTAGE
va. OUTPUT CURRENT
3.4
Vcc=5.5V
T.=25CC
Vcc=4.SV
~
-
/
/
o
Fig. 11 - NORMAUZED POWER SUPPLY CURRENT
va. AMBIENT TEMPERATURE
3
V
/
~
/
V
J
w
~ 3.2
S
g
5 3.0
~o
~ ........
~ 2.S
~
>
...........
2.6
0
~
o
SO
20
40
60
100
TA• AMBIENT TEMPERATURE (CC)
w 0.3
Il.z
g
I- 0.2
rr
N
_:::l
""'0
~
rrll.
~
.....
f;J~
~~
:::l
1.0
Oil.
:::l
j
10
Fig. 14 - NORMALIZED POWER SUPPLY CURRENT
va. FREQUENCY
1.S
TA=25CC
Vcc=S.5V
rr
w
~I- 1.4
Fig. 13 - OUTPUT VOLTAGE
va. OUTPUT CURRENT
0.4
TA=25°C
Vcc=4.5V
Cl
0
5
10H. OUTPUT CURRENT (rnA)
Z:::l
0.1
jUl 0.6
0.2
10
10... OUTPUT CURRENT (mA)
20
V
10
I. FREQUENCY (MHz)
100
1-13
MB81C67-35
MB81C67-45
MB81C67-55
Rg. 16- NORIIAUZED ACCESS llllE
ve. LOAD CAPACITANCE
Rg. 15- NORIIAUZED ACCESS llllE
va. LOAD CAPACITANCE
w
::;;
i=
IIIw
0
w
::;; 1.3 I- T.=2SoC
i=
Vcc=4.SV
1.3 I- T.=2SOC
Vcc=4.SV
cw
1.1
::;
--
~
a: 1.0
0
z
j
0
0
/'
./
«
N
IIIw
./
1.2
0
0.9
o
./
1.2
«
c
w 1.1
V
N
~
a: 1.0
0
z
j
......
0.9
o
SO
100
150 200
CL, LOAD CAPACITANCE (pF)
-- -l.---
::;
so 100 150 200
CL, LOAD CAPACITANCE (pF)
PACKAGE DIMENSIONS
Suffix: CZ
2O-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE
(CASE No.: DIP-2OC-C03)
- -. rn
.288~:g~:
R.025(0.64)
REF·
(7.32~g:~~1
1--------
.950~:g~g
.319t.006
(8.10±0.15)
.300(7.62)TVP
--------1
(24.13~~:~~)
--1
.050(1.27)MAX
~I-----------------
.100±.010
(2.54'0.25)
II:> 1988 FUJITSU LIMITED D200065-4C
1-14
Dimensions in
inches (millimeterS)
MB81C67-35
MB81C67-45
MB81C67-55
PACKAGE DIMENSIONS
Suffix: TV
2Q-PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC·20C·FO')
'PIN NO.1 INDEX
\
..
R.012(0.30)TYP
(4 PLCS)
b
R.008(0.20)TYP
(20PLCS)
.025<.005
·(0.64<0.13)
.285~:~~
(1.27±0.15)
.065( 1.65)TYP
.045(1.14)
TYP
.100(2.54)MAX
• Shape of PIN NO.1 INDEX: Subject to change without notice.
Dimension in
inches (millimeters)
© 1988 FUJITSU LIMITED C20003S-2C
1·15
MB81C67-35
MB81C67-45
MB81C67-55
PACKAGE DIMENSIONS
Suffix: P
20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No.: DIP-20P-MOI)
.1,72(4.36) MAX
.118(3.00) MIN
.050(1.27)
MAX
.100(2.54)
TYP
© 1988 FUIITSU LIMITED D2D005S-3C
1-16
---I.j-.C'.0~18,:-,±.003
.020(0.51) MIN
(0.46 ± 0.08)
Dimensions in
inches (millimeters)
00
April 1990
Edition 3.0
FUJITSU
DATA SHEET
MB81 C68A-251-301-35
CMOS 16K-BIT HIGH-SPEED SRAM
..
4K Words x 4 Bits Static Random Access Memory with
Super High-Speed and Automatic Power Down
The Fuj~su MB81C68A is a 4,096 words x 4 bits static random access memory
fabricated w~h a CMOS silicon gate process. The memory uses asynchronous
circu~ry. All pins are TTL compatible and a single +5 V power supply is required.
A separate chip select (CS) pin simplHies multipackage systems design by perm~ing
the selection of an individual package when outputs are OR-tied, and then
automatically powering down the other deselected packages.
The MB81 C68A offers low power dissipation, low cost, and high performance.
•
•
•
•
•
•
•
•
•
•
•
4,096 words x 4 b~s
Organization:
Static operation: no clocks or timing strobe required
tM = tACS = 25 ns max. (MBSI C6SA-25)
Access time:
tM- tACS = 30 ns max. (MB81C6SA-30)
t M - tACS = 35 os max. (MB81C68A-35)
Low power consumption: 385 mW max. (Active)
138 mW max. (Standby, TTL level)
83 mW max. (Standby, CMOS level)
Single +5 V power supply ±1 0% tolerance
TTL compatible inputs and outputs
Three-state outputs w~h OR-tie capac~y
Chip select for simplified memory expansion, automatic power down
Electrostatic protection for all inputs and outputs
Standard 2O-pin Plastic Package:
DIP
MBS1C68A-xxP
ZIP
MB81C6SA-xxPSZ
Standard 20-pin Ceramic Package:
CERDIP MB81C68A-xxZ
PLASTIC PACKAGE
(DlP.20P·M01 )
PLASTIC PACKAGE
(ZIP.20P·M01 )
LCC: See page 12
PIN ASSIGNMENT
Absolute Maximum Ratings (See Note)
Rating
Supply Voltage
Symbol
Value
UnH
V
Vcc
-{).5 to +7.0
Input Voltaae on any pin w~h
respect to NO
VIN
--3.5 to +7.0
V
Output Voltage on any 110 pin
with respect to GND
VOUT
-{).5 to +7.0
V
Output Current
loUT
±20
rnA
Power Dissipation
Temperature Under Bias
Storage Temperature
Range
I
I
Ceramic
Plastic
Po
1.0
W
T BIAS
-10 to +85
·C
TSTG
(,
CERAMIC PACKAGE CERDIP
~5to+l50
-45 to +125
A,
Vee
A.
A.
Ao
A.
A.
Aa
Ao
A,o
Al1
liD,
A,
1/0:.
Ao
CS
1/03
GND
liD,
WE
°C
Note: Permanent deVICe damage may occur If absolute maximum ratings are exceeded.
Functional operation should be restricted to !he conditions as detailed in the operation
sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
This dev1D8 contains circullry to protect the Inputs against
damage due to high static voltages or eledrlc fieldl. However. k
II ac:Msed that norna precautions be taken to avoid application
of any voltage higher than maximum rated voltages t) this high
irJ1)8dance circuit.
eq,y,lghi © 19110 by FUJITSU LIMITED IIId Fujl10u MIcrooIeoI"",Ica.Inc.
1-17
MB81 C68A-25
MB81C68A-30
MB81C68A-35
Fig. 1 - MB81C68A BLOCK DIAGRAM
-Vee
A.
As
-
•
A.
•
•
ROW
SELECT
A7
GND
128 X 128
MEMORY CELL
ARRAY
A.
•••
A.
A,.
I/O CIRCUITS
I/O,
I/O.
INPUT
DATA
CONTROL
II<>.
COLUMN
SELECT
VO.
TRUTH TABLE
H
L
L
X
L
H
MODE
VO
POWER
NOT SELECTED
WRITE
READ
HIGH-Z
D,N
D
STANDBY
ACTIVE
ACTIVE
CAPACITANCE (TA= 25° C, f = 1MHz)
Parameter
Symbol
Typ
Max
UnH
Input Capacitance (V..~OV)
CIN
5
pF
CS Capac~ance (Vw-OV)
~
6
pF
Coo
7
pF
VO
1-18
Capac~ance
(V..,..OV)
MB81C68A-25
MB81C68A-30
MB81C68A-35
RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Vo~age
Vee
4.5
5.0
5.5
V
Ambient Temperature
T.
0
70
·C
..
DC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted.)
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
Input Leakage Current
V'N=OV to Vee
lu
-10
10
~A
Output Leakage Current
CS=V'H. Voo=OV to Vee
ILO
-10
10
~A
Active (DC) Supply Current
IOUT=OmA CS=V'L.
V'N=V'Lor V'H
lee.
25
50
rnA
Operating Supply Current
CS=V'L
IOUT-OmA. Cycle=Min
1=
40
70
rnA
Standby Supply Current
CS=Vcc-O.2V. V'NS,0.2V
or V,~Vcc ~.2V
I...
0.5
15
rnA
Standby Supply Current
CS=V'H
Is..
10
25
rnA
Input Low Vo~age
V'L
-2.0'
O.S
V
Input High Vo~age
V'H
2.2
6.0
V
0.4
V
Output Low Vottage
IOL-SmA
VOL
Output High Voltage
IOH=-4mA
VOH
Note:
•
2.4
V
-2.0V Min. for pulse width less than 20ns. (VL Min=-O.5V at DC level)
1-19
MB81 C68A-25
MB81C68A-30
MB81C68A-35
AC TEST CONDITION
OVto3.0V
5ns (Transient Time between O.SV and 2.2V)
Input : 1.5V
Output: 1.5V
Input Pulse Levels:
Input Pulse Rise and Fall TImes:
TIming Reference Levels:
Fig. 2
5.0V
Output Load:
;=4800
CL=30pF
CL=5pF for tlZ• t HZ• tow and Iwz
DOUT - -......- -. .
(Including Scope
and
Jig CapacHance)
I~
:2550
AC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted.)
READ CYCLE"
MB81 C68A·25
Parameter
MB81 C68A-30
MB81 C68A-35
Min
Min
Symbol
Unit
Min
Max
25
Max
30
Max
35
ns
Read Cycie TIme
tRe
Address Access Time"
t...
25
30
35
ns
Chip Select Access TIme"
t..cs
25
30
35
ns
Output Hold from Address Change
IoH
3
3
3
ns
Output Hold from CS
lotte
0
0
0
ns
Chip Selection to Output in Low-Z"
tlZ
5
5
5
ns
Chip Deselection to Output in High-ZO'
t,..
Power Up from CS
tpu
Power Down from CS
tpo
Note:
1-20
'1
'2
'3
'4
10
0
13
0
20
WE is high for Read cycle.
Device is continuously selected. CS=VIL•
Address valid prior to or coincident wHh CS transHion low.
TransHion is specHied at the point of ±SOOmV from steady state voltage.
15
0
25
ns
ns
30
ns
MB81 C68A-25
MB81 C68A-30
MB81C68A-35
READ CYCLE TIMING DIAGRAM"
..
READ CYCLE: ADDRESS CONTROLLED"
~----------------I~----------------~
ADDRESS
1 - - - - - - 1M
------------1
IoH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
READ CYCLE: CS CONTROLLED'3
~----------------I~----------------~
1 - - - - t ACS ---------I
DATA OUT
IPu
SUPPLY
CURRENT
Note:
HIGH-Z
DATA VALID
l .------_1
oo1Yl o
---",Is....
" _ _ _ _ _5_oo.J
IPo
Icc
~,--O_%
_ _ __
'1 WE is high for Read cycle.
'2 Device is continuously selected, CS=VIL •
'3 Address valid prior 10 or coincidenl with CS transnion low.
'4 Transnion is specHied at the point of ±500mV from sleady state voltage.
1-21
MB81C68A-25
MB81C68A-30
MB81C68A-35
WRITE CYCLE·' ••
MB81 C68A-25
Parameter
MB81 C68A-35
Unit
Max
Min
Wr~e
MB81 C68A-30
Symbol
Cycle Time
Max
Min
Min
Max
twe
25
30
35
ns
Chip Selection to End of Write
lew
20
25
30
ns
Address Valid to End of Wr~e
t.w
20
25
30
ns
Address Setup Time
tAS
0
0
0
ns
Wr~e
twp
20
25
30
ns
tow
13
15
15
ns
Write Recovery Time
tWR
2
2
2
ns
0
Pulse Width
Data Setup Time
Data Hold Time
tOH
Output High-Z from WE"'
twz
Output Low-Z from WE"'
lew
0
0
10
5
13
5
ns
15
5
WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: WE CONTROLLED"'
"2
twe
ADDRESS
~
---.-/
~
lew
VIIIIIIIIIIIIIIII
'\'\'\~ l\'\'\'\~
... tAS
tAw
twp
WE
tOH
_tow
DATA VALID
DATA IN
lew·'
-twz"'DATA OUT
Note:
HIGH·Z
"I CS or WE must be high during address trans~ions.
"2 If CS goes high simu~aneously with WE high. the output remains in a high impedance state.
"3 Trans~ion is specffied at the point of ±500mV from steady state vo~age.
1-22
ns
ns
MB81C68A-25
MB81C68A-30
MB81 C68A-35
WRITE CYCLE TIMING DIAGRAM
..
WRITE CYCLE: CS CONTROLLED""
....- - - - - - - - twe
---------1
ADDRESS
~-----------~W------------~~~~R~
~=-.---------Icw - - - - - - 1
....
---~p-----~~
...._ _ tow _ _ _........::to:::."......
DATA VALID
DATA IN
~
tWi3
_
HIGH-Z
DATA OUT ---------~~---+~----~~~--------------------
Nota:
'1 CS or WE must be high during address transitions.
'2 HCS goes high simultaneously with WE high, the output remains in a high impedance state.
'3 Transition is specHied at the point of ±500mV from steady state voltage.
1-23
MB81C68A·25
MB81C68A·30
MB81C68A·35
TYPICAL CHARACTERISTICS CURVES
Fig. 3 OPERATING SUPPLY CURRENT
vs. SUPPLY VOLTAGE
~
~
~
Fig. 4 OPERATING SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
i=
1.2
&a:i 1.1 H--I--Ir---::I~-""f-I
15 ....
&a:i 1.1
N::J
t::I::J
w ....
cO::
wO::
:::i" 1.0 H--I-~IL--I--H
~~
0::1l.
0.9 H-"7t'---1I--I--H
j
j
O.B H<---+--t--+--t-I
~
...J"
1.0
<~
cO::
wO::
!5 ~ 0.9
4.75
5.0
5.25
j
j
o
5.5
1.4
Z
~ ....
(/) a:i
I
~~
~~ O.B
J(/)
J 0.6
.........: ~
~
V I••,
--
j
4.75
5.0
5.25
o
5.5
Vee. SUPPLY VOLTAGE (V)
~
I
2.0
~
a:i
(/)0::
75
100
J
1.B
TA =25°C
Vcc=5.5V
f--V'N=V,otIV'L
~!z
~w 1.4
1.5
O~
C::J
W::J
t::I" 1.0
t!:J"
1.0
:::i~
~Il.
0:: ~ 0.6
~~
::!Ell.
!5 ~ 0.5
i---"
.,/'
O(/)
z(/)
Z
J
o
o
25
50
75
100
T A. AMBIENT TEMPERATURE (OC)
1·24
50
Fig. 8 OPERATING SUPPLY CURRENT
vs. FREQUENCY
~
cO::
j
25
i=
Vcc-5.5V
CS.V'H
Z ....
- roo-
TA• AMBIENT TEMPERATURE (OC)
Fig. 7 STANDBY SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
c
100
I
Vcc=5.5V
CS=Vee
V,N=GND or Vee
V
4.5
75
Fig. 6 STANDBY SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
/
1.2
0::1l.
50
I
T.=25°C
~" 1.0
::!E~
25
TA• AMBIENT TEMPERATURE (OC)
Fig. 5 STANDBY SUPPLY CURRENT
VS. SUPPLY VOLTAGE
Co::
~
0.8
Vee. SUPPLY VOLTAGE (V)
c~
~~
z(/)
4.5
I
Vee=5.5V
::!Ell.
o~
z(/)
I
1.2
0.2
5
10
50 100
f. FREQUENCY (MHz)
MB81C68A-25
MB81C68A-30
MB81C68A-35
TYPICAL CHARACTERISTICS CURVES
~
Fig. 9 "H" LEVEL OUTPUT VOLTAGE
VS. "H" LEVEL OUTPUT CURRENT
I
w 3.6
§>5
3.4
~
I->~
T.-25°C
Vee-5.0V
i'o...
.........
~
1=
:::>
o
~
3.2
i'-....
...........
2.8
2.5
5.0
0.3
0.2
W
0.1
;..
0
~
~
7.5
~
1.1
.........
W
N
::::;
1.0
,
~
T.=25°C -
o
j
j
-
5.0
I
1.0
V
/"
~
~ 0.9
0.8
o
5.5
Vee. SUPPLY VOLTAGE (V)
w
20
I
1.1
~
::::;
<
:::?;
i'-.
5.25
15
Vcx:=4.5V
j
4.75
10
~
0.8
4.5
5
f= 1.2
~
~ 0.9
/
Fig. 12 ACCESS TIME VS. AMBIENT
TEMPERATURE
W
:::?;
Cl
..............
..
/
IOL• "L"LEVEL OUTPUT CURRENT (mA)
Fig. 11 ACCESS TIME VS. SUPPLY
VOLTAGE
Cl
~
10
10H. "W LEVEL OUTPUT CURRENT (mA)
w
:::?;
f=
CI)
1.2
CI)
w
I
T.=250 C r /
Vee=5.0V
~
o..J
~ 3.0
o
I
0.4
~
..J
!t:
Fig. 10 "L" LEVEL OUTPUT VOLTAGE
VS. "L" L!:VEL OUTPUT CURRENT
25
50
75
100
T•• AMBIENT TEMPERATURE (OC)
Fig. 13 ACCESS TIME VS. LOAD
CAPACITANCE
:::?;
f=
CI)
1.4 f- T.-25°C
Vee-4.5V
CI)
w
~
./
1.2
Cl
w
N
1.0
o~
0.8
j
0.6
~
./
/'
/'
z
o
100
200
300
400
CL• LOAD CAPACITANCE (pF)
1-25
MB81C68A-25
MB81 C68A-30
MB81 C68A-35
PACKAGE DIMENSIONS
(Suffix: -Z)
2O-LEAD CERAMIC (CERDIPJ DUAL IN-LINE PACKAGE
(CASE No_: DIP-2OC-C03J
R.02510.64)
REF·
1 - - - - - - - - .950~:~~~
--rH-__
_ _ _ _ _ _-j
(24.13~6:~~)
.0_50_I_l_.2_7)_M_A_X___________________
.100t.01O
12.54±0.25)
Dimensions in
inches «millimeterS)
@1988 FUJITSU LIMITED D200065-4C
(Suffix: -P)
20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DlP-20P-MOI)
.050(1.27)
MAX
© 1988 FUIITSU LIMITED D2DD05S-3C
1-26
Dimensions in
inches (millimeters)
MB81C68A-25
MB81C68A-30
MB81C68A-35
PACKAGE DIMENSIONS
(Suffix: -PSZ)
20-LEAD PLASTIC ZIG-ZAG IN-LINE PACKAGE
..
(Case No. : ZIP-20P-MOI)
[
l
INDEX
112± 008
(2.85 ± 0.20)
1
__ 1
.260±.01O
(6.60±0.25)
d
! I
II
.050(1.27)
TYP
LEAD No.
.010±.002
(0.25±0.05)
.020± .004
(0.50±0.10)
.312l.013
(7.93±0.33)
;;~~
.118(3.00) MIN
--.I.
.100(2.54) TYP
(ROW SPACE)
\2.)
~
Dimensions in
©1988 FUJITSU LIMITED Z20001S-4C
inches (millimeters)
1-27
MB81C68A-25
MB81C68A-30
MB81C68A-35
PACKAGE DIMENSIONS (Conl'd)
(Suffix: -TV)
As 3'
A. 4=-1
~
A. ~-l TOP VIEW
A.
~-l
A,
~-l
As 8.J
~~ AtA,.
~~ vo,
A"
~4
1:.3
110.
110.
CERAMIC PACKAGE LCC
(LCC-20C-F01 )
2O-PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC-20C-F01)
'PIN NO.1 INDEX
\
R.012(O.30ITYP
(4 PLCSI
b
t
~~T3351.511
I
TYP
.250(6.351
TYP
.0875(2.221
TYP
.285~:~~
L--'~~~~~~~I
.050'.006
.045(1.14ITYP (1.27±0.151
.065(1.65ITYP
.100(2.54IMAX
.. Shape of PIN NO.1 INDEX: Subject to change without notice.
© 19BB FUJITSU LIMITED C20003S-2C
1-28
.~~3.811
.050±.006
(1.27±0.151
.045(1.141
TYP
.195(4.951
TYP
Dimension in
inches (millimeters)
OJ
April 1990
FUJITSU
Edition 3.0
DATA SHEET
MB81 C69A-251-301-35
CMOS 16K-BIT HIGH-SPEED SRAM
..
4K Words x 4 Bits Static Random Access Memory with
Super High-Speed
The Fuj~su MB81C69A is a 4,096 words x 4 bits static random access memory
fabricated w~h a CMOS silicon gate process. The memory uses asynchronous
circu~ry. All pins are TIL compatible and a single +5 V power supply is required.
A separate chip select (CS) pin simpl~ies mukipackage systems design by perm~ing
the selection of an individual package when outputs are OR-tied.
The MB81 C69A offers low power dissipation, low cost, and high performance.
CERAMIC PACKAGE CERDIP
(DIP-20C-C03)
4,096 words x 4 b~s
•
Organization:
•
Static operation: no clocks or timing strobe required
•
Access time:
tAA- 25 ns max, tACS -15 ns max. (MB81C69A-25)
tAA - 30 ns max, tACS = 18 ns max. (MB81 C69A-30)
tAA - 35 ns max, tACS _ 20 ns max. (MB81 C69A-35)
•
Low power consumption:
•
Single +5 V power supply ±1 0% tolerance
385 mW max. (Active)
•
TIL compatible inputs and outputs
•
Three-state outputs w~h OR-tie capacity
•
Chip select for simplified memory expansion
PLASTIC PACKAGE
(DIP-20P-M01 )
•
Electrostatic protection for all inputs and outputs
•
Standard 20-pin Plastic Package:
DIP
MB81 C69A-xxP
•
Standard 20-pad Ceramic Package:
LCC
MB81C69A-xxTV
•
Standard 20-pin Ceramic Package:
CERDIP MB81C69A-xxZ
Lee: See page 11
PIN ASSIGNMENT
Absolute Maximum Ratings (See Note)
A,
Symbol
Value
Vee
Un"
A.
Supply Voltage
Vcc
-0.5 to +7.0
V
As
A.
A,
Input Volta&e on any pin with
respect to NO
VIN
-3.5 to +7.0
V
Output Vokage on any 110 pin
w~h respect to GND
A.
A,
A,
VOU!
-0.5 to +7.0
V
Output Current
loUT
±20
mA
Po
1.0
W
TSIAS
-10to+85
·C
Rating
Power Dissipation
Temperature Under Bias
I
-65 to +150
Storage Temperature Ceramic
·C
TSTG
Range
I Plastic
-45 to +125
Note: Pennanent deVICe damage may occur If absolute maximum ratings are exceeded.
Functional operation should be restricted to the conditions as delailed in the operation
sections of this dala sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Copyr~hI
©
AlO
A"
1/0,
1/0,
1/0,
A,
Ao
CS
110.
GND
WE
LCC: See page 11
This deYk:e contains circuitry to protect the inputs against
damage due to high slatic vo~ages or electric fields. However. It
Is advised that normal precautions be takan to avoid application
of any vottage higher than maximum rated voltages to this high
ifl1l8dance circuit.
1990 by FUJITSU LIMITED and Fulliou M~"",loctronlcs.lnc.
1-29
MB81C69A-25
MB81 C69A-30
MB81 C69A-35
Fig. 1 - MB81C69A BLOCK DIAGRAM
4--0
Vee
-GND
•
---~:::::::1
A. ---~:::::1
A. ---~:::::::1
••
ROW
SELECT
A7
128x 128
MEMORY CELL
ARRAY
• • •
I/O CIRCUITS
1/0,
0 - - - _ - - 1 ")---1
VO.
0 - - -.....-+--1 :':---1
1/0,
0 - - _.......-+--1 ")_--1
1/0.
0 - -.....
INPUT
DATA
CONTROL
COLUMN
SELECT
++-+--1:.:---1
TRUTH TABLE
CS
WE
MODE
VO
H
L
L
X
NOT SELECTED
WRITE
READ
HIGH-Z
L
H
D'N
Dour
CAPACITANCE (TA= 25°C,f= 1MHz)
Parameter
Symbol
Typ
Max
Unit
5
pF
Input Capacitance (V,N=OV)
C'N
CS Capac~ance (Vcs.OV)
CCl!
6
pF
C,IO
7
pF
VO
1-30
Capac~ance
(V",-OV)
MB81C69A-25
MB81C69A-30
MB81C69A-35
RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Symbol
Min
Typ
Max
Unit
Supply VoHage
Vee
4.5
5.0
5.5
V
Ambient Temperature
T.
0
70
·C
Parameter
..
DC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted.)
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
Input Leakage Current
V'N=OV to Vee
III
-10
10
I1A
Output Leakage Current
CS=V'H. VIIO=OV to Vee
ILO
-10
10
I1A
Active Supply Current
CS.V,u IoUT=OmA
V'N=V'Lor V'H
Icc.
25
50
mA
Operating Supply Current
CS=V'L
1000=OmA. Cycle=Min
1=
40
70
mA
Input Low Voltage
V'L
-2.0·
0.8
V
Input High VoHage
V'H
2.2
6.0
V
0.4
V
Output Low VoHage
IOL=8mA
VOL
Output High Voltage
IOH--4mA
VOH
Note:
•
2.4
V
-2.0V Min. for pulse width less than 20ns. (VL Min.=-D.5V at DC level)
1-31
MB81C69A-25
MB81C69A-30
MB81C69A-35
AC TEST CONDITION
Input Pulse Levels:
Input Pulse Rise and Fall Times:
Timing Reference Levels:
OVt03.0V
5ns (Transient Time between 0.8V and 2.2V)
Input : 1.5V
Output: 1.5V
Output Load:
Fig. 2
5.0V
~ 4800
1.
DoUT
(Including sco. pe and
Jig Capacitance)
I
CL=30pF
CL=5pF for tlZ• tHZ• low and twz
~
2550
CL
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE"'
Parameter
MB81C69A·25
MB81C69A·30
MB81 C69A-35
Min
Min
Min
Symbol
Unit
Max
30
Max
Read Cycle Time"'
tRe
Address Access Time"'
t..A
25
30
35
ns
Chip Select Access Time"'
tACS
15
18
20
ns
Output Hold from Address Change
IoH
3
3
3
ns
Output Hold from CS
IoHC
0
0
0
ns
Chip Selection to Output in Low·Z"·
tlZ
0
0
0
ns
Chip Deselection to Output in High·Z"·
tHZ
Note:
25
Max
10
35
13
ns
15
"I WE is high for Read cycle.
"2 All read cycles are determined from the last address transttion to the first address transition of next cycle.
"3 Device is continuously selected. CS=V'L.
"4 Address valid prior to or coincident with CS transttion low.
"5 Transttion is specnied at the point of ±500mV from steady state Voltage w~h Load II in Fig. 2.
1-32
ns
MB81 C69A-25
MB81 C69A-30
MB81 C69A-35
READ CYCLE TIMING DIAGRAM"'
..
READ CYCLE: ADDRESS CONTROLLED
14--------- 1,.," - - - - - - - - - . j
ADDRESS
i------lu·'
DATA OUT
------t
PREVIOUS DATA VALID
DATA VALID
READ CYCLE: CS CONTROLLED*'
14---------1,.," -----------1
ADDRESS
14---- 1M - - - - I
DATA OUT
Nota:
*1
*2
*3
*4
HIGH-Z
DATA VALID
HIGH-Z
WE is high for Read cycle.
All read cycles are determined from the lasl address transition to the first address transition of next cycle.
Device is continuously selected, CS=V'L.
Address valid prior to or coincident with CS transition low.
*5 Transition is specified at the point of ±500mV from steady stale vollage wilh Load" in Fig. 2.
1-33
MB81C69A·25
MB81C69A·30
MB81 C69A·35
WRITE CYCLE·'·'
MB81 C69A-25
Parameter
MB81 C69A-30
MB81 C69A-35
Symbol
Un"
Max
Min
Max
Min
Min
Max
Write Cycle Time·'
!we
25
30
35
ns
Chip Selection to End of Write
lew
20
25
30
ns
Address Valid to End of Wr~e
low
20
25
30
ns
Address Setup Time
to.
0
0
0
ns
30
ns
Write Pulse Width
twp
20
25
Data Setup Time
tow
13
15
15
ns
Write Recovery Time-'
tWR
2
2
2
ns
Data Hold Time
to..
0
0
0
Output High-Z from WE*'
twz
Output Low-Z from WE*'
low
13
10
5
ns
15
5
5
WRITE CYCLE TIMING DIAGRAM
ns
ns
.,.2
WRITE CYCLE: WE CONTROLLED
t WC"3
ADDRESS
--...
--'
~
tew
'\'\'\'\' ~'\'\'\~
le-t..
y////////////////
low
twp
tDH
_tow
DATA VALID
DATA IN
low"
~twi'-
DATA OUT
Note:
HIGH Z
·*1 If CS are in the READ Mode during this period, 110 pins are in the output state so that the input signals of oppos~e
phase to the outputs must not be applied.
If CS goes high simu~aneously with WE high, the output remains in high impedance state.
*3 All wrke cycle are determined from last address trans~ion to the first address trans~ion of the next address.
*4 tWR is defined from the end point of WRITE Mode.
·2
*5 Transition is specHied at the point of ±500mV from steady state voltage with Load II in Fig. 2.
1·34
MB81C69A-25
MB81C69A-30
MB81C69A-35
WRITE CYCLE TIMING DIAGRAM
..
WRITE CYCLE: CS CONTROLLED*'*'
~--------
twc·'
----------.j
ADDRESS
1 - - - - - - - - t..w --------1...!tW~R~··~
~...:;t.:::s_ll_-----Icw ------_1
~----~p----~
DATA VALID
DATA IN
Q~'
DATA OUT
Note:
a-
HIGH-Z
*1 H CS are in the READ Mode during this period, I/O pins are in the output state so that the input signals 01 opposne
phase to the outputs must not be applied.
*2 II CS goes high simultaneously with WE high, the output remains in high impedance state.
*3 All wrne cycle are determined lrom last address transnion to the lirst address transnion 01 the next address.
*4 tWR is defined from the end point of WRITE Mode.
*S Transnion is specffied at the point of +SOOmV from steady state voltage with Load II in Fig. 2.
1-35
MB81C69A-25
MB81C69A-30
MB81C69A-35
TYPICAL CHARACTERISTICS CURVES
§i!
Fig. 3 OPERA11NG SUPPLY CURRENT
va. SUPPLY VOLTAGE
i=
~
1.2
o t!!
1.1
WIc..z
Oa:
w:::l
O:::l
0.9
ZIIl
j
0.8
I~ 1C2
T••25°C
!:j 0 1.0
~~
a: 8:
Fig. 4 OPERA'nNG SUPPLY CURRENT
va. AMBIENT TEMPERATURE
§i!
~
V
1/
~.
~I-
1.2
Vee=5.5V
wI-
ts iiJ 1.1
olf
~ :::l1.0
~
..JO
~~0.9
a:c..
O:::l
Z III
4.5 4.75 5.0 5.25 5.5
j
~
1.8
wI-
oa:
wa:
!:lI:::l
~~
~~ 0.6
15~
Z III 0.2
j
~
25
50
75
100
C!l
~
3.6
~
3.4
o
;:
1=:::l
3.2
iLl
3.0
iii
;'
2.8
o
0
:::l
fil
~ 0.3
1=
:::l
0.2
iLl
0.1
<
~•
1.1
!:jl.0
<
0
~
Fig. 8
::E
a:
~j
a
0.9
V
I
T.=25°C I -
""" ~ ........... ...........
0.8
-.J
~
a 2.5 5.0 7.5 10
5
a 5 10 15 20
j
> IoH. "H" LEVEL OUTPUT CURRENT (rnA) > lou "L" LEVEL OUTPUT CURRENT (rnA)
~
Fig. 9 ACCESS 11ME va. AMBIENT
TEMPERATURE
~
i=
i=
~ 12
~ 1.4
~
1.1
~
~
1.0
I!:l
o
..J
~
~
j
j
4.5 4.75 5.0 5.25 5.5
Vee. SUPPLY VOLTAGE (V)
Fig. 10 ACCESS 11ME VB. LOAD
CAPACITANCE
-
T.-25°C
Vcc=4.5V
1.2
0
1.0
.II'
V
./
V
~
0.9
... 0.8
~
0.8
a
j
25
50
75
100
T•• AMBIENT TEMPERATURE (OC)
1-36
I-
ACCe;;L~:~Evs. SUPPLY
III
0.4
--
1
5 10
50100
f. FREQUENCY (MHz)
m1.2
8
~
:::l
""""
T•• AMBIENT TEMPERATURE (OC),j
w
C!l
1.0
..JO
~ F~~ ~~~~~~~~'o~~~~~~~~~~E ~ F~; ~~~'~~~~~'o~~~~~~~~~E ~I-.
w
T.=25°C
Vcc=5.5V
V'N=V'HN'L
ts iiJ 1.4
0.8
a
Vee. SUPPLY VOLTAGE (V)
Fig. 5 OPERATING SUPPLY
CURRENT va. FREQUENCY
j
0.6
a 100 200 300 400
CL• LOAD CAPACITANCE (pF)
MB81C69A-25
MB81C69A-30
MB81C69A-35
PACKAGE DIMENSIONS
CERAMIC DIP (Suffix: Z)
20·LEAD CERAMIC (CERDIP) DUAL IN·LlNE PACKAGE
(CASE No.: DIP·20C·C03)
..
--. m
R.025(O.64)
.288~:~~:
REF
(7.32+ 0 . 36 )
-0.10 .319±.006
(8.10±0.15)
1-_ _ _ _ _ _ .950~:~~~
_ _ _ _ _ _-1
(24.13~~:~~)
.050(1.27)MAX
.100±.010
(2.54±0.25)
© 1988 FUJITSU LIMITED D20006S-4C
Dimensions in
inches (millimeters)
1-37
MB81C69A-25
MB81 C69A-30
MB81 C69A-35
PACKAGE DIMENSIONS (Cont'd)
PLASTIC DIP (Suffix: P)
20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No.: DIP-20P-MOI)
t
_--_+~}
Gl.-.172(4.361 MAX
18(300) MIN
.020(0.51) MIN
(0.46 ± 0.08)
© 1988 FUJITSU LIMITED D20005S-3C
1-38
Dimensions in
inches (millimeters)
MB81 C69A·25
MB81C69A·30
MB81C69A·35
PACKAGE DIMENSIONS (Cont'd)
CERAMIC LCC (Suffix: TV)
..
A.
A,.
A"
I/O,
110.
110.
CERAMIC PACKAGE
(LCC·20C-F01 )
2O-PAD CERAMIC (FRIT SEAL) lEADlESS CHIP CARRIER
(CASE No_: lCC-20C-F01)
-PIN NO.1 INDEX
\
R .012(0.30ITVP
(4 PLCSI
b
.OSO±.006
(1.27±0.1SI
.04S(1.141
TVP
.100(2.S4IMAX
* Shape of PIN NO.1 INDEX: Subject to change without notice.
Dimension in
inches (millimeters)
© 1988 FUJITSU LIMITED C20003S-2C
1·39
High-Speed CMOS SRAMs
1·40
Static RAM Data Book
00
March 1990
FUJITSU
Edition 3.0
DATA SHEET
MB81 C71 A-25/-30/-35
CMOS 64K-BIT HIGH-SPEED SRAM
64K Words x 1 Bit High-Speed CMOS Static Random
Access Memory
The Fujitsu MB81C71A is a 65,536 words x 1 bit static random access memory
fabricated with a CMOS technology. It uses fully static circuitry throughout and,
therefore, requires no clocks or refreshes to operate.
The MB81C71A is designed for memory applications where high performance, low
cost. large bit storage, and simple interfacing are required. It is compatible with TIL
logic, and requires a single +5 V supply.
•
•
65,536 words x 1 bit
Organization:
Static operation: no clocks or refresh required
•
Access time:
•
tM- tACS - 35 ns max. (MB81C71A-35)
Single +5 V power supply ±1 0% tolerance
•
Separate data inputs and outputs
•
•
•
•
•
TIL compatible inputs an!l outputs
Three-state outputs with OR-tie capability
Chip select for simplified memory expansion, automatic power down
Electrostatic protection for all inputs and outputs
Standard 22-pin Plastic Package:
DIP
MB81 C71 A-xxP
Standard 24-pin Plastic Package:
SOJ
MB81 C71 A-xxPJ
Standard 22-pad Ceramic Package:
LCC (metal seal) MB81C71A-xxCV
•
•
PLASTIC PACKAGE
DIP-22P-M04
1M-lAcs - 25 ns max. (MB81C71A-25)
1M-lAcs - 30 ns max. (MB81C71A-30)
PLASTIC PACKAGE
LCC-24P-M02
Absolute Maximum Ratings (See Note)
Rating
LCC : See page 12.
PIN ASSIGNMENT
A.
A.
A.
A2
A,
A7
A,
Ao
Ao
A14
A'3
A12
A15
A"
A,.
DouT
Ao
WE
GND
D'N
CS
Symbol
Value
Unit
Supply Voltage
Vee
-0.5 to +7
V
A.
Input VoI~e on any pin with
respect to NO
VN
-3.5 to +7
V
A3
A2
A,
Output Volt~~r on any pin with
respect to G 0
Vour
-0.5 to +7
V
Output Current
lour
±SO
mA
Power Dissipation
Po
1.0
W
Temperature Under Bias
Storage Temperature
Range
TslAS
I
I
Ceramic
Plastic
Tsro
-10to+85
-65 to +150
-45 to +125
°C
°C
Vee
Vee
A.
A7
A,
Ao
Ao
NC
A15
A'l
A,o
A14
NC
A'3
A12
Ao
DoUT
~
GND
'11::===="'"
D'N
CS
LCC : See 12 page.
Note: Permanent device damage may occur if absolute maximum ratings are exceeded.
Functional operation should be restricted 10 1he conditions as deleiled in 1he operation
sections oIlhis data sheet Exposure 10 absolute maximum rating conditions for extended periods may all8CI device reliability.
Thill_ oontaI.. clrou_ry to preted "'.Inp"'" agalnat
dIrnage due to ligh 1IIaIIc "",,- ... oIoctrlc flolda. However••
10 edvfood 1haI normal _lone be tal!an to avoid oppICOIlon
01 ony \IOItage higher _ moximJm _
YOlagoo 10 thlo high
irrI>OdanoOclroull
1-41
MB81 C71 A-25
MB81 C71 A-30
MB81C71A-35
Fig. 1 - MB81 C71 A BLOCK DIAGRAM
1.0
A,
·
·
·
r
A.
..
A.
A,.
ROW
SELECT
.:>
.
AI3
--
r---
:>
.
r
A..
t--
CELL
ARRAY
128 ROWS
512 COLUMNS
INPUT
DATA
GND
. . .I
I - - Dour
f--
COLUMN 1..0 CIRCUITS
D,N
Vo<;
COLUMN SELECT
:~~~.
Y
POWER
DOWN
CIRCUIT
TRUTH TABLE
cs
WE
H
L
L
X
L
H
MODE
NOT SELECTED
WRITE
READ
OUTPUT
HIGH-Z
HIGH-Z
Dour
POWER
STANDBY
ACTIVE
ACTIVE
CAPACITANCE (TA=25°C,f=1MHz)
Parameter
1-42
Symbol
Value
Typ
Max
Un"
Input Capacitance (V..=OV)
c,.
7
pF
CS Capac~ance (VCii=OV)
Ccs
7
pF
Output Capac~ance (Vour-OV)
Cour
7
pF
MB81 C71 A-25
MB81 C71 A-30
MB81 C71 A-35
RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter
Symbol
Value
Unit
Min
Typ
Max
5.0
5.5
V
70
·C
Supply Vottage
Vee
4.5
Ambient Temperature
T.
0
..
DC CHARACTERISTICS
(Recommended operating conditions unless othelWlse noted.)
Parameter
Test Condition
Symbol
Value
Min
Typ
Max
Unit
Input Leakage Current
V,N-OV to Vee
Vee=Max.
lu
-10
10
itA
Output Leakage Current
CS=V,H,
VOIIT=OV to 4.5V
Vee=Max.
leo
-10
10
itA
Operating Supply Current
CS=VIl, Vee=Max.
DolIT=Open,
Cycie=Min.
Icc
50
SO
mA
ISBl
1
10
mA
Is..
10
20
mA
O.S
V
6.0
V
0.45
V
Standby Current
Standby Current
Vee=Min. to Max.
CS~Vcc -0.2V
V,NsO.2Vor
V,"~VCc -Q.2V
Vcc=Min. to Max.
CS=V,
Input Low Vottage
Input High Voltage
V'L
-2.0'
V,H
2.2
Output Low Vottage
IOL=16mA
VOL
Output High Voltage
10H=-4mA
VOH
Peak Power on Current"
Vcc=OV to Vee Min.
CS=Lower of Vee or
V,H Min.
IPO
2.4
V
30
mA
• -2.0V Min, for pulse width less than 20 ns. (V'L Min=-Q.5V at DC level)
.. A pull·up resistor to Vee on the CS input is required to keep the device deselected; otherwise, power·on current approaches
Icc active.
1-43
MB81C71A-25
MB81C71A-30
MB81C71A-35
Fig. 2 - AC TEST CONDITIONS
• Input Pulse Levels:
• Input Pulse Rise And Fall Times:
• Timing Measurement Reference Levels:
O.SVto2.4V
Sns
Input
: 1.SV
Output : 1.SV
• Output Load:
5.0V
:=..
~
4800
Load I: CL=30pF
Load II: CL=5pF for tlZ• t HZ• tow and lwz
Do~ --------~------. .
(Including Scope and
Jig Capacttance)
..L
I~
:=
2550
-:~
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE"
Parameter
Symbol
MB81 C71 A-25
Min
Read Cycle Time'"
t""
Address Access Time"
t..
Max
25
MB81 C71 A·3D
Min
Max
30
25
MB81C71A-35
Min
35
30
25
30
Chip Select Access Time""
tACS
Output Hold from Address Change
tOH
5
5
5
Chip Selection to Output in Low-Z'B
tlZ
5
5
5
Chip Deselection to Output in High-Z'B
t.z
0
Chip Selection to Power Up Time
tpu
0
Chip Deselection to Power Down time
tPD
Note:
'1
'2
'3
'4
'5
'6
1-44
10
0
13
0
20
0
ns
35
ns
35
ns
ns
ns
15
ns
ns
0
25
Unit
Max
30
WE is high for Read cycle.
All Read cycles are determined from the last address transttion to the first address transition of next cycle.
Device is continuously selected. CS.V'L.
Address valid prior to or coincident wtth CS transttion low.
Chip deselection for a fintte time is less than tAC prior to selection.
Trans~ion is measured at the point of ±500mV from steady state voltage with specHied Load II in Fig. 2.
ns
MB81C71A-25
MB81 C71 A-30
MB81 C71 A-35
READ CYCLE nMING DIAGRAM .,••
READ CYCLE: ADDRESS CONTROLLED"
..
ADDRESS
IoH
DATA OUT
PREVIOUS DATA
VALID
DATA VALID
READ CYCLE : CS CONTROLLED····
t-----
tACS
----~
t HZ••
t L2*8
HIGH-Z
DATA OUT - - - - i - - - - - {
DATA VALID
-------u---~)~SO%-~juuu _
I..
~ Undefined
Note:
'1
'2
'3
'4
'5
'6
:mWJ
Don't Care
WE is high for Read cycle.
All Read cycles are determined from the last address transkionto the first address trans~ion of next cycle.
Device is continuously selected, CS".VIL•
Address valid prior to or coincident w~hCS" transHion low.
Chip deselection for a fin He time is less than tAC prior to selection.
Trans~ion is measured at the point of ±500mV from steady state voltage wHh specHied Load II in Fig. 2.
1-45
MB81 C71 A-25
MB81C71A-30
MB81 C71 A-35
WRITE CYCLE""
MB8l C7l A-25
Parameter
MB8l C7l A-35
Unit
Min
Wr~e
MB81C71A-30
Symbol
Cycle Time"
1wc
Max
Max
Min
Min
Max
25
30
35
ns
Chip Selection to End of Write
tcw
20
25
30
ns
Address Valid to End of Write
tow
20
25
30
ns
Address Setup Time
t AS,
0
0
0
ns
Address Setup Time
t_
O
0
0
ns
Wrile Pulse Width
Iwp
20
25
30
ns
Data Valid 10 End of Wr~e
low
15
18
20
ns
Wr~e
IWR
2
2
2
ns
IoH
2
2
2
ns
Iwz
il
low
0
Recovery Time
Dala Hold Time
Wr~e
Enable 10 OutpUI in High-Z"
OUlput Active from End of
Wr~e"
10
0
13
0
15
0
0
WRITE CYCLE TIMING DIAGRAM""
twc~3
ADDRESS
DATA IN
'.~
HIGH-Z DW
DATA OUT
IKZI
Note:
'I
'2
'3
'4
Undefined
It I
Don't Care
CS .or WE must be high during address trans~ions.
If CS goes high simuttaneously with WE high, the output remains in high impedance stale.
All Write cycles are determined from the last address transition to the first address trans~ion of next cycle.
Transition is measured at the point of ±500mV from steady state voltage with specWied Load II in Fig. 2.
ns
ns
MB81 C71 A-25
MB81 C71 A-30
MB81 C71 A-35
WRITE CYCLE TIMING DIAGRAM .,••
WRITE CYCLE: CS CONTROLLED·'
..
twc
ADDRESS
tew - - - - - - t
~------- ~w -------~~~~
DATA IN
DATA OUT
HIGH-Z
-------<
~ Undefined
Note:
*1
*2
*3
*4
It>1
Don't Care
CS or WE must be high during address transnions.
If CS goes high simu~aneously with WE high, the output remains in high impedance state.
All Wrne cycles are determined from the last address transition to the first address transnion of next cycle.
Transnion is measured at the point of ±500mV from steady state voltage with specnied Load II in Fig. 2.
1-47
MB81 C71 A·25
MB81 C71 A·30
MB81 C71 A-35
TYPICAL CHARACTERISTICS CURVES
Fig. 3 - OPERATING SUPPLY CURRENT
VS. SUPPLY VOLTAGE
Fig. 4 - OPERATING SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
T.=25·C
~ 1.2 '--- Cyclamin.
i=
~I
wi\':i
~~
fila 1.0
0.9
0:::::1
0 00 0.8
V
V
ffi i\':i
1.1
0:::1
1.0
~~
/
w()
!:l!>-
-
~~
~
i=
MB81 C71 A-25
MB81 C71 A-30
MB81 C71 A-35
TYPICAL CHARACTERISTICS CURVES (Cont'd)
Fig. 8 - "H" LEVEL OUTPUT VOLTAGE
VS. "H" LEVEL OUTPUT CURRENT
4.0
~
-
Fig. 9 - "L" LEVEL OUTPUT VOLTAGE
VS. "L" LEVEL OUTPUT CURRENT
T.=25°C
Vee=5.0V
0.4
~
3.8
0.
I-~
5~ 3.6
.............
ul~
0.3
I-~
5~0.2
..............
V
ul~
./
>~ 0.1
......
~5
~>
./
0
J
o
2.5 5.0 7.5 10
I"". "W LEVEL OUTPUT CURRENT (rnA)
o
NW
~;;!j 1.0
:::!;I-
~~0.9
10
15
20
Tee=4.5V
T.=25°C
1.1
5
Fig. 11 - ACCESS TIME VS. AMBIENT
TEMPERATURE
1.2
1.2
W
"",
101.. "L"lEVEL OUTPUT CURRENT (rnA)
Fig. 10- ACCESS TIME VS. SUPPLY
VOLTAGE
C
..
T.=25°C
Tee=5.0V
0.
~~ 3.4
...J'-'
• 0
~> 3.2
J
r--
..........
.........
C
W
./
1.1
t::lw
.........
~;;!j 1.0
~
/
:::!;I-
~~ 0.9
/
ZJ~
j~ 0.8
ZW
.U
j~0.8
j
j
o
4.5
5.0
5.5
Vee. SUPPLY VOLTAGE (V)
25
50
75
100
T•• AMBIENT TEMPERATURE (OC)
Fig. 12 - ACCESS TIME VS. LOAD
CAPACITANCE
T.=25°C
1.2
c
1.1
W
N W
::J:::!; 1.0
-- Vee=4.5V
~
...V
~
~i=
~~ 0.9
ZJ~
j~ 0.8
j
o 50 100 150 200
CL. LOAD CAPACITANCE (pF)
1-49
MB81C71A-25
MB81C71A-30
MB81C71A-35
PACKAGE DIMENSIONS
(Suffix: -P)
22-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-22P-M04)
...._=-I,.,__...__'"'_~""'~~+ 15° MAX
.05011.27)
MAX
.10012.54)
.018±.003
TYP
10.46±0.08)
© 1988 FUJITSU LIMITED D22DD8S-4C
1-50
Dimensions in
inches (millimeters)
MB81 C71 A-25
MB81 C71 A-30
MB81 C71 A-35
PACKAGE DIMENSIONS
(Suffix: -PJ
24-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCC·24P·M02)
..
~~-=n
-1=,
005
(8.64±0 .13)
.273±.020
(6.93±0.51 )
.050±.005
(1.27±0.13)
.550(13.97)REF
I
.091(2.31 )
NOM
--
11~
.025(0.64)
MIN
.144(3.661
MAX
.... ; This dimension includes resin protrusion. (Each side: .006(O.15)MAX.)
DimenSIons In
inches (millimeters)
01989 FUJITSU LIMITED C24052S·1C
1-51
MB81C71A-25
MB81 C71 A-30
MB81C71A-35
PACKAGE DIMENSIONS
(Suffix: -CV)
A. ~:
A,
: ~ J1
, ,[2.2!2.1: "'
:2]
1:
A7
As
~1] As
'1!
A" §:
A..
6' TOP VIEW '1
A12
8!
A.. 7:
A,.
:{E An
~1} A,o
As
Dour ~ !
:1!
'\. :{()11;{~{~
WEI eSD,.
CERAMIC PACKAGE
LCC·22C-A01
GND
22·PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC·22C·A01)
'PIN NO.1 INDEX
/
c5
R.012(0.30)TYP
(4 PLCS)
n
.495±.010
(12.57±0.25)
.065(1.65)
TYP
.045(1.14)
TYP
.083(2.11)
MAX
.050±.006
(1.27±0.15)
.045(1.14)
TYP
·Share of PIN NO.1 INDEX: Subject to changed without notice.
© 1988 FUJITSU LIMITED C22002S-2C
1-52
Dimensions in
inches (millimeters)
cP
March 1990
Edition 3.0
FUJITSU
DATA SHEET
MBS1 C74-25/-30/-35
CMOS 64K-BIT HIGH-SPEED SRAM
16K Words x 4 Bits High-Speed CMOS Static Random
Access Memory
The Fujnsu MB81C74 is a 16,384 words x 4 bns static random access memory
fabricated wnh a CMOS silicon gate process. The memory uses asynchronous
circunry and n may be maintained in any state for an indefinnB period of time. All pins
are TIL compatible and a single +5 V power supply is required.
The MB81C74 has low power dissipation, low cost, and high performance, and n is
ideally suned for use in microprocessor systems and other applications where fast
access time and ease of use are required.
16,384 words x 4 bits
t.u -lACs - 25 ns max. (MB81 C74-25)
t.u - tACS - 30 ns max. (MB81 C74-30)
t.u -lACs - 35 ns max. (MB81 C74-35)
• Static operation: no clock required
• TTl compatible inputs and outputs
o Three-state outputs
• Common data inputs and outputs
• Single +5 V power supply ±1 0% tolerance
• low power standby:
550 mW max. (Active)
55 mW max. (Standby, CMOS level)
110 mW max. (Standby, TIL level)
• Standard 22-pin Plastic Package:
DIP
MB81C74-xxP
• Standard 22-pad Ceramic Package:
lCC
(metal seal)
MB81C74-xxCV
•
•
Organization:
Access time:
PLASTIC PACKAGE
DlP-22P-M04
CERAMIC PACKAGE
LCC-22C-A01
PIN ASSIGNMENT
A,
Vec
At
At
At
A,
A,.
A,
A,
Absolute Maximum Ratings (See Note)
A"
A"
A"
00,
A,
Symbol
Value
Un"
Supply Voltage
Rating
Vee
-
::E..J
0:0.. 0.9
00..
z::J
.en
~
25
"
ICC1
50
75
100
Fig. 6 - STANDBY SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
>
al
C
z
~ ....
~lsB2
/
o
~CC2
T•• AMBIENT TEMPERATURE (OC)
Is~
T.=25°C
enrli
Co: 1.1
wo:
""
~~
Fig. 5 - STANDBY SUPPLY CURRENT
VS. SUPPLY VOLTAGE
>
al
C
z
~
::Eo.. 0.9
0:0..
O::J
zen 0.8
4.5
5.0
5.5
Vcc• SUPPLY VOLTAGE (V)
..
Vcc=5.5V
i=
T.=25°C
1.2
enrli
Co: 1.1
wo:
/
~5
«> 1.0
::E..J
0:0..
00.. 0.9
z::J
.en
~
..!!!
4.5
5.0
5.5
Vcc• SUPPLY VOLTAGE (V)
~
~02
"'
ISB1
0.8
J
j
~
o
25
50
75
100
T•• AMBIENT TEMPERATURE (OC)
Fig. 7 - OPERATING SUPPLY CURRENT
VS. FREQUENCY
(!)
z
i=
~ ....
1.8
O~
1.4
WZ
o..W
C::J
wU 1.0
!::::!>
..J..J
«0..
::Eo.. 0.6
0:::J
Oen
z
0.2
-
T.=25°C
Vcc=5.5V
VIN-VIHNll
/
J
1
5 10
50100
f. FREQUENCY (MHz)
1-59
MB81C74-25
MB81C74-30
MB81C74-35
TYPICAL CHARACTERISTICS CURVES (Cont'd)
Fig. 9 - "L" LEVEL OUTPUT VOLTAGE
vs. "L" LEVEL OUTPUT CURRENT
Fig. 8 - "H" LEVEL OUTPUT VOLTAGE
vs. "H" LEVEL OUTPUT CURRENT
I::I
3.8
::I>
3.6
I!:~
O~
...Jw
wCl 3.4
>~
w...J
:'0 3.2
r--
TA-25°C
Vcc-5.0V
I-
c..
I-~
::I>
......... .....
O~
r--
......
.........
0.3
w~
0.2
~>
0.1
Gi~
...JO
......
0
Fig. 10 - ACCESS TIME vs. SUPPLY
VOLTAGE
Fig. 11 - ACCESS TIME vs. AMBIENT
TEMPERATURE
2.5
5.0
7.5
10
Vcc=4.5V
T.-25°C
!:::Iw
...J::ii
::iiI-
1.1
a:U)
0U)
1.0
j<
0.9
1.2
c
w
!:::Iw
...J::ii
W
j
.......
.........
...........
L
1.1
~i=
a:U) 1.0
0U)
z.g
r--
j<
j
0.8
V
0.9
o
!:::Iw
...J::ii
~i=
1.2
1.1
a:U) 1.0
0U)
r-
T.=25°C
Vcc=4.5V
~
V
i"""
ZW
·8
j<
j
25
50
75
100
TA• AMBIENT TEMPERATURE (OC)
Fig. 12 - ACCESS TIME vs. LOAD
CAPACITANCE
cw
1/
0.8
4.5
5.0
5.5
Vcc. SUPPLY VOLTAGE (V)
0.9
0.8
o 50 100 150 200
C" LOAD CAPACITANCE (pF)
1-60
L
V
o 5 10 15 20
101.. "L" LEVEL OUTPUT CURRENT (rnA)
1.2
Z.g
V
10... "H" LEVEL OUTPUT CURRENT (rnA)
c
<-
r
/
.l
~
3.0
o
T.=25°C
Vcc=5.0V
...Jw
t:->
.j
0.4
::I
MB81C74-25
MB81C74-30
MB81C74-35
PACKAGE DIMENSIONS
(Suffix: P)
22-LEADS PLASTIC DUAL IN-LINE PACKAGE
(CASE No. : DIP-22P-M04)
.-----::;;Ii~--.."-,,.---""-~.,+
..
15° MAX
.300(7.62)
TYP
.050(1.27)
.100(2.54)
MAX
TYP
018±.003
(0.46±0.08)
Dimensions in
© 1988 FUJITSU LIMITED D22008S-4C
inches (millimeters)
1-61
MB81C74-25
MB81C74-30
MB81C74-35
PACKAGE DIMENSIONS (Cont'd)
(Suffix: CV
22·PAD CERAMIC (METAL SEAL) LEAD LESS CHIP CARRIER
(CASE No. : LCC-22C-A01)
'PIN NO.1 INDEX
/
6
R.012(0.30)TVP
(4 PLCS)
n
.495±.010
(12.57±0.25)
.065(1.65)
TYP
.045(1.14)
TVP
.083(2.11)
.050±.006
(1.27±0.15)
.045(1.14)
TVP
MAX
·Share of PIN NO.1 INDEX: Subject to changed without notice.
© 1988 FUJITSU LIMITED C22002S-2C
1-62
Dimensions in
inches (millimeters)
FU1hsu
March 1990
Edition 3.0
DATA SHEET
MB81 C75-251-301-35
CMOS 64K-BIT HIGH-SPEED SRAM
..
16K Words x 4 Bits High-Speed CMOS Static Random
Access Memory
The Fujitsu MB81 C75 is a 16,384 words x 4 bits static random IICC8IIS memory
fabricated with a CMOS silicon gate process. The memory uses asynchronous
circuitry and it may be maintained in any state for an indCifinite period of time. All pins
ara TTL compatible and a single ..s V power supply is required.
The MB81 C75 has low power dissipation, low cost, and high performance, and it is
ideally suited for use in microprocessor systems and other applications where fast
access time and ease of usa ara required.
•
•
•
•
•
•
•
•
•
•
18,384 words x 4 bits
iM-IAcs.25 ns max. (MB81C75-25)
toe -10 ns max.
iM - lAcs. 30 ns max. (MB81 C75-30)
toe -13 ns max.
tM - lAcs. 35 ns max. (MB81 C75-35)
toe - 15 ns max.
Static operation: no clock required
TTL compatible inputs and outputs
Three-state outputs
Common data inputs and outputs
Single ..s V power supply ±1 0% tolerance
Low power standby:
550 mW max. (Active)
55 mW max. (Standby, CMOS leval)
110 mW max. (Standby, TTL level)
Standard 24-pin Plastic Package:
DIP
MB81C75-xxP
SOJ
MB81C75-xxPJ
Standard 28-pad Ceramic Package:
LCC (matal saal) MB81C75-xxCV
PLASTIC PACKAGE
DIP-24P-M03
Organization:
Accasstime:
PLASTIC PACKAGE
LCC-24P·M02
PIN ASSIGNMENT
A"
Vee
A,
A"
A"
As
A"
A..
A,.
All
A,.
A,
A.
A,
N.C.
1/0,
1/0,
1/0.
1/0,
WE
A.
cs
Absolute Maximum Ratings (See Note)
OE
GND
Symbol
Value
UnH
Supply Voltage
Vee
-<1.5 to +7
V
Input Vo~e on any pin with
raspact to NO
V..
-3.5 to +7
V
Voor
-<1.5 to +7
V
A,
louT
±20
mA
A,
Rating
Output Vo~e on any
raspact to G 0
va pin with
Output Current
Power Dissipation
Temperature Under Bias
Storage Temperatura
Range
I
I
Ceramic
Plastic
A"
A,
A"
As
A.
A.
Po
1.0
W
TBIAS
-10 to +85
°C
Tsm
-65 to +150
-45 to +125
°C
Nota: Permanent device damllfiJlilnay occur if absolute maximum ratings are excaeded.
Functional operation should be rsslriclBd 111 the conditions as detailed in the operation
IIICIions of this data sheet Exposure 111 absolulll maximum rating conditions lor extended periods may atlact davice reliabUity.
c"s
OE
GND
_ _ _.. clrculbylO
_lito
InpIU ogainII
~duetohlg/t_~ar_IcIl.I
•• """""'••
II
0tM00d ..... _ _ _ botakontoavold..,.,_
01 any vaIIaQo higher ..... maximum _
voI\ageIlo IhIo high
~.!raI1t.
~@ lt1110brFWrraU LlllllBlnl F...... II_ooolcl, Inc.
1·63
MB81C75-25
MB81C75-30
MB81C75-35
Fig. 1 - MB81C75 BLOCK DIAGRAM
...~
- - 0 Vee
~
A,
-
... ~
ROW
SELECT
>
A,
~
A,
... >
A13
>
1/0,
~
1102
~
110,
~
··
-·
...
COLUMN
110 CIRCUITS
=
=
COLUMN
SELECT
INPUT
DATA
CONTROL
~
0-
--oGND
128x 128x4
MEMORY CELL
ARRAY
lit~
-D
~
ill
1\
~1
As
A,
A,
~
~
~
~
111
A.
A,. An
--ttr-
~
~
~
I--
A'2
-~
-1
TRUTH TABLE
POWER
DOWN
CIRCUIT
CS
WE
OE
MODE
VO
H
L
L
L
X
X
H
H
L
H
L
X
NOT SELECTED
OUTPUT DESABLE
READ
WRITE
HIGH·Z
HIGH·Z
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
D'N
CAPACITANCE (TA = 25°C,f= 1MHz)
Parameter
1-64
Symbol
Value
Min
Typ
Max
UnH
VO Capacitance (V,/O-OV)
Coo
7
pF
Input Capacitance (V,,=OV)
C'N
1
pF
MB81C75-25
MB81C75-30
MB81C75-35
RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter
Symbol
Value
Unit
Min
Typ
Max
5.0
5.5
V
70
·C
Supply Vottage
Vcc
4.5
Ambient Temperature
T,
0
..
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Test Conditions
Symbol
Value
Min
Max
Unit
CS2:Vcc-O.2V. V,N,,0.2V or
V'N2:VCC-O· 2V
ISB1
10
CS=V,H
ISB2
20
Active Supply Current
CS=VIL• V,N=V,L or
V,H• IOUT=OmA
Icc.
60
Operating Supply Current
Cycle=Min .• IOUT=OmA. CS=V..
1=
100
Input Leakage Current
V,N=OV to Vee
lu
-10
10
jJA
Output Leakage Current
CS=V,H• Vvo=OVto Vee
ILVO
-10
10
jJA
Input Low Vottage
V..
-2.0'
0.8
V
Input High Voltage
V..
2.2
6.0
V
VOH
2.4
Standby Supply Current
Output High Voltage
IOH=-4mA
Output Low Vottage
IoL=8mA
VOL
rnA
rnA
V
0.4
V
Note: All vokages are referenced to GND
• -2.0V Min. for pulse width less than 20ns. (V,L Min=-O.5V at DC Level)
Fig. 2 - AC TEST CONDITIONS
• Output Load
• Input Pulse Levels
• Input Pulse Rise & Fall Times
• Timing Reference Levels
+5V
OVt03.0V
5ns (Transient between 0.8V and 2.2V)
Input : 1.5V
Output: 1.5V
Q
~
R1
DoUT
(1/0)
I
• Including Scope and Jig Capacttance
I
I Load I I
I Load II I
R1
I R2 I CL I
Parameters Measured
I
4800 I 2550 I 30pF I except te", teHz• twu. tWHZ' loll ana 10Hz I
4800 I 2550 I 5pF I tell' teHz• twu. tWHZ' loll ana 10Hz
I
1-65
MB81C75-25
MB81C75-30
MB81C75-35
AC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted.)
READ CYCLE*1
Parameter
MB81C75-25
Symbol
Max
Min
Read Cycle Time
25
tRe
"
MB81C75-30
Min
Max
MB81C75-35
Max
Min
30
Unit
ns
35
Address Access Time '2
CS Access Time '3
OE Access Time '3
Output Hold from Address Change
IoH
5
5
5
ns
IoHc
3
3
3
ns
IeLZ
5
5
5
ns
0
0,
Output Hold from CS
CS to Output Low-Z '4
tM
25
30
35
ns
tACS
25
30
35
ns
10.
10
13
15
ns
OE to Output in Low-Z '4
IoLZ
CS to Output High-Z '4
IeHZ
10
13
15
ns
OE to Output High-Z '4
10HZ
10
13
15
ns
Power Up from CS
tpu
power Down from CS
tpo
0
0
ns
0
0
ns
25
20
30
ns
READ CYCLE TIMING DIAGRAM *1
READ CYCLE I '2
~--------------tRe--------------~
ADDRESS
ADDRESS VALID
i
_--=~~~::-------.
tM
'.
PREVIOUS
DATA VALID
DOUT
'3
_ _~~_'OH
_"
_
_ -
,
READ CYCLE II '3
ADDRESS
#i;mi¥i:M~"~:::::----------;;;A-D'"-D;:;;R;'E=;:;:O;:S~V;;A;L;;:;I-D;:::----------~"iTtfmMmbT%mmm¥Tdm}m""T""""m",m"",T"",,"m:mMT¥mJmt~Wi
HIGH-Z
HIGH-Z
t,.D~
________________~~~~----------I~C~C~---------5&Vol~__________
SUPPLY
CURRENT
~ Undefined
Note:
1-66
'1
'2
'3
'4
11m Don't Care
WE is high for Read cycle.
Device is continuously selected, CS-V,~E-V...
Address valid prior to or coincident with CS transition low.
Transition is measured at the point of ±50OmV from steady state voltage with specHied Load II in Fig. 2.
MB81C75-25
MB81C75-30
MB81C75-35
WRITE CYCLE *1
MB81C75-25
Parameter
Symbol
Max
Min
MB81C75-30
Min
MB81C75-35
Max
Max
Min
Unit
Write Cycle Time '2
!we
25
30
35
ns
Address Valid to End of Write
tAW
20
25
30
ns
Chip Select to End of Write
lew
20
25
30
ns
low
13
15
17
ns
Data Valid to End of Write
Data Hold Time
tot<
2
2
2
ns
Write Pulse Width
!wp
20
25
30
ns
Address Setup Time
tAS
0
0
0
ns
!wR
!wHZ
!wLZ
2
2
2
ns
Write Recovery Time
Output High-Z from WE '3
Output Low-Z from WE '3
0
0
10
0
..
ns
13
15
ns
WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE I: WE CONTROLLED '1'2
i----------!we-----------i
ADDRESS
~,t:i':""
ADDRESS VALID
tWA-=!
.It------!we
I • • • •·\1k,
I--t..
D'N
HIGH-Z
11---- tow
~~
~ Undefined
Note:
----o!e-- t -=!
oH
HIGH-Z
DATA VALID
HIGH-Z
I--lwu~
Il'i!I Don~ Care
'1 H CS goes high simuttaneously with WE high. the output remains in high impedance state.
'2 All write cycle are determined from last address transition to the first address transition of the next address.
'3 Transition is measured at the point of ±500mV from steady state voltage with specnied Load II in Fig. 2.
1-67
MB81C75-25
MB81C75-30
MB81C75-35
WRITE CYCLE II: CS CONTROLLED ·1·2
_ __
D'N
___
~H~IG~H~_Z~______________~r~~_-_~~~~_~~~~~·_'·
~_-;!L~H~IG~H~~~_
~
DATA VALID
::::jIKE Undefined
Note:
1-68
•
Don'tCare
·1 HCS goes high simultaneously with WE high, the output remains in high impedance state.
·2 All write cycle are determined from last address transition to the first address transition of the next address.
MB81C75-25
MB81C75-30
MB81C75-35
TYPICAL CHARACTERISTICS CURVES
Fig. 3 - OPERATING SUPPLY CURRENT
VS. SUPPL Y VOLTAGE
T.=25°C
Cl
~
~W
O~
l~\,
1.1
lila
1.0
!:::!>~~ 0.9
::!:n.
a:::J
~en 0.8
~
V
V
"
o 25 50 75 100
T•• AMBIENT TEMPERATURE (DC)
Fig. 5 - STANDBY SUPPLY CURRENT
VS. SUPPLY VOLTAGE
Fig. 6 - STANDBY SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
T.=25°C
f-f-
1.2
~lsB2
CI ~ 1.1
wa:
!:::!::J
() 1.0
::!:>a:~
On. 0.9
Z::J
.en
0.8
>[II
CI
Z
~fen zw
CIa:
wa:
!:::!::J
....I()
<>::!:....I
a:n.
On.
Z::J
ISB1
en Z
Jl
....
4.5
5.0
5.5
Vcc. SUPPLY VOLTAGE (V)
~
~
~ ~Iccl
Icc,
.J
>[II
CI
..
Vcc=5.5V
Iccl
1.2
~!z
Fig. 4 - OPERATING SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
~
V
V
Vcc=5.5V
1.2
1.1
1.0
~
0.9
Jen 0.8
I": ~B2
':"
ISBI
_m
o 25 50 75 100
T•• AMBIENT TEMPERATURE (DC)
4.5
5.0
5.5
vcc. SUPPLY VOLTAGE (V)
Fig. 7 - OPERATING SUPPLY CURRENT
VS. FREQUENCY
Cl
Z
i=
~!z
1.8 I - -
T.=25°C
Vcc=5.5V
V'N=V'HNIL
~w 1.4
O~
lila 1.0
~~
~& 0.6
a:::J
~ en 0.2
J
j
1
5 10
50100
f. FREQUENCY (MHz)
1-69
MB81C75-25
MB81C75-30
MB81C75-35
TYPICAL CHARACTERISTICS CURVES (Cont'd)
Fig. 9 - "L" LEVEL OUTPUT VOLTAGE
vs. "L" LEVEL OUTPUT CURRENT
Fig. 8 - "H" LEVEL OUTPUT VOLTAGE
vs. "H" LEVEL OUTPUT CURRENT
3.8
~
0..
3.6
I-~
5~
3.4
-
T.=25°C
V",,=5.0V
l-
r--....
Giw~I• 0
r: >
J
=>
0..
3.2
-
0.3
l/
5~ 0.2
irl~
.....
3.0
Gi...J...Ji5
0.1
;...§2
0
./
2.5 5.0 7.5 10
IOH • "W LEVEL OUTPUT CURRENT (rnA)
o 5 10 15 20
10L' "L" LEVEL OUTPUT CURRENT (rnA)
Fig. 10 - ACCESS TIME vs. SUPPLY
VOLTAGE
Fig. 11 - ACCESS TIME vs. AMBIENT
TEMPERATURE
V",,=4.5V
T.=25°C
Cl
W
~~
1.2
Cl
1.1
~f= 1.0
OC/)
zc/)
w~0.9
..9 0
"
~
~
./
1.1
...Jw
<::;
..........
~f= 1.0
r--
OC/)
zc/)
w~ 0.9
V
l/
..9 0
J< 0.8
j
J<0.8
j
o 25 50 75 100
TA• AMBIENT TEMPERATURE (OC)
4.5
5.0
5.5
V"". SUPPLY VOLTAGE (V)
Fig. 12 - ACCESS TIME vs. LOAD
CAPACITANCE
T.=25°C
1.4 r-- Vcc=4.5V
Cl
w
!:::!
~~
1.2
~i= 1.0
r-./
~~
~
r--
i-tAAI tACS
Oen
zen
~~0.8
-0
J<0.6
j
o 50 100 150 200
CL. LOAD CAPACITANCE (pF)
1·70
, ...V
>~
o
1.2
!:::!
T.=25°C
Vcc=5.0V
I-~
~
"'r--....
...Jw
...J...J
0.4
MB81C75-25
MB81C75-30
MB81C75-35
PACKAGE DIMENSIONS
Suffix: P)
24-LEAD PLASTIC SKINNY DUAL IN-LINE PACKAGE
(CASE No_: DIP-24P-M031
:::::l: :::,;,"~:: :~JI5~'
(29. 72~g:~g)
..
.300(7.62)
TYP
.010•. 002
(0.25'0.05)
.172(4.36)MAX
.05011.27)
MAX
.100(2.54)1
TYP
.118(3.oo)MIN
.018 •. 003
(0.46'0.08)
.020(0.51)MIN
Dimension. in
Inches (millimeter.)
© 1988 FUJITSU LIMITED D24017S-3C
1-71
MB81C75-25
MB81C75-30
MB81C75-35
PACKAGE DIMENSIONS
(Suffix: .PJ)
24-LEAD PLASTIC LEADED CHIP CARRIER
(CASE NO.: LCC-24P·M02)
Ffl
1
.340±.005
(8.64±0.13)
.273±.020
(6.93±0.51 )
~
.050±.005
(1.27±0.13)
.550(13.97)REF
I
9
.091(2.31 )
-b
NOM
Details of "A" part
1=r,....1=-:r-"I'-::r-.-=r-,-:II-...,-~-r-l=-r-1=-:r-"F-::r-.-=r--,-"'I-r-l=-r:~
.102(2.60)
.025(0.64)
MIN
.144(3.66)
MAX
032
(O'81)MAX
NOM
.::..
.004(0.10)
* : This dimension includes resin protrusion. (Each side: .006(O.15)MAX.)
01988 FUJITSU LIMITED C24052S·1C
1-72
• I I
--I.
.017±.004
(O.43±O.1 0)
p~~~~S:~7~i~eters}
MB81C75-25
MB81C75-30
MB81C75-35
PACKAGE DIMENSIONS
(Suffix: CV)
NC
A.NC Vcc NC
I
/
A7
As
1:
!~!?! 1 F_8!2J:
._.
5-
As ~!
A,
A.
A.
I:
~:
TOP VIEW
9-
CERAMIC PACKAGE
LCC-28C-A03
A,.
A,.
-2
:i1
A"
A12
:1J
{~
'\.
~2]
VO,
1/0.
:1_1 1/0,
A,
CS
-2.!
~2:C
1-0:
~ {1:
..
"'
;2} NC
'~2_
2} A.
;1-j'1-~{&{&{7:
J
./
OE-I NC 1/0,
GND WE
28-PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC-28C-AD3)
• PIN NO.1 INOEX
/
n
.460( 11.68)
.550<.010
(13.97<0.25)
R.008(0.20)TYP
(28PLCS)
.350<.010
(8.89<0.25)
.045(1.14lTYP
.065(1.65)TYP
.083(2.11 )MAX
·Shape of PIN NO.1 INDEX: Subject to change without notice.
© 1988 FUJITSU LIMITED C28009S-1C
.045(1.14)
TYP
Dimensions in inches
and (millimeters)
1-73
High-Sf188d CMOS SRAMs
1-74
Static RAM Data Book
00
April 1990
Edition 3.0
FUJITSU
DATA SHEET
MB81C78A-351-45
CMOS 64K-BIT HIGH-SPEED SRAM
..
8K Words x 8 Bits High-Speed CMOS Static Random
Access Memory with Automatic Power Down
The FujHsu MB81C78A is a 8,192 words x 8 bits static random access memory
fabricated with a CMOS process. The memory uses asynchronous circuHry and may
be maintained in any state for an indefinite period of time. All pins are TTL compatible
and a single +5 V power supply is required.
A separate chip select (CS1) pin simplifies mu~ipackage systems design by permHing
the selection of an individual package when outputs are OR-tied, and then
automatically powering down the other deselected packages.
PLASTIC PACKAGE
DIP-28P-M04
The MB81 C78A offers low power dissipation, low cost, and high performance.
•
•
8,192 words x 8 bHs
Organization:
Static operation: no clock or timing strobe required
•
Access time:
•
tM = tACS1 = 35 ns max.
tM = IAcS1 - 45 ns max.
Low power consumption: 495 mW max.
138 mW max.
83 mW max.
(MB81 C78A-35)
(MB81 C78A-45)
(Operating)
(Standby, TTL level)
(Standby, CMOS level)
•
•
o
Single +5 V power supply ±1 0% tolerance
TTL compatible inputs and outputs
Three-state outputs wHh OR-tie capacHy
•
Chip select for simplified memory expansion, automatic power down
•
Electrostatic protection for all inputs and outputs
•
Standard 28-pin Plastic Package:
Skinny DIP (300 mil) MB81C78A-xxPSK
SOP
MB81C78A-xxPF
SOJ
MB81C78A-xxPJ
•
Standard 32-pad Ceramic Package:
LCC
(metal seal)
MB81C78A-CV
PLASTIC PACKAGE
FPT·28p·M02
PLASTIC PACKAGE
LCC·28p·M04
PIN ASSIGNMENT
Absolute Maximum Ratings (See Note)
Rating
Supply Voltage
Symbol
Value
Unit
Vee
-
20
25
ns
Output Disable from OE"
10HZ
20
25
ns
-
Note:
'1
'2
'3
'4
..
MB81 C78A-45
Symbol
35
45
3
ns
3
15
ns
20
ns
WE is high for Read cycle.
Device is continuously selected. CS,=V,L. CS,=V.. and OE=V,L.
Address valid prior 10 or coincident wtth CS, transttion low. CS,lransition high.
Transnion is specHied at the point of ±500mV from steady state voltage with specified Load II in Fig. 2.
1-79
MB81C78A-35
MB81 C78A-45
READ CYCLE TIMING DIAGRAM·'
READ CYCLE I: ADDRESS CONTROLLED"
ADDRESS
______::=======_~__-_-_-_-_-_-_-_-1~ __-------------DATA OUT
PREVIOUS DATA VALID
)K
DATA VALID
READ CYCLE II: CS" CS. CONTROLLED"
ADDRESS
CS.
VO
•
Note:
1-80
: Don't Care
~ : Undefined
'1 WE is high for Read cycle.
'2 Device is c:ontinuously selected, CSt = V,L, CS. ~ VtH and OE = V..'
'3 Address valid prior to or c:oincident w~h CSt trans~ion low, Cs. transition high.
'4 Trans~ion is specified at the point of ±500mV from steady state voltage with specnied Load II in Fig. 2.
MB81 C78A-35
MB81 C78A-45
WRITE CYCLE"
MB81 C78A-35
Parameter
MB81 C78A-45
Symbol
Unit
Min
Max
Min
Wrne Cycle Time"
twe
35
45
ns
CS, to End of Write
lew,
30
40
ns
CS2 to End of Write
lew.
20
25
ns
Address Valid to End of Write
t.w
30
40
ns
Address Setup Time
tAS
0
0
ns
Wr~e
twp
20
25
ns
Data Setup Time
tow
17
20
ns
Wr~e
tWR
3
3
ns
Data Hold Time
to..
0
0
ns
Output High-Z from WE"
twz
Output Low-Z from WE"
low
Note:
Pulse Width
Recovery Time"
'1
'2
'3
'4
15
0
20
0
..
Max
ns
ns
HCS, goes high simultaneously wnh WE high. the output remains in high impedance state.
All wr~e cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of Wr~e Mode.
Transnion is specffied at the point of ±500mV from steady state voltage with specified Load II in Fig. 2.
1-81
MB81C78A-35
MB81C78A-45
WRITE CYCLE TIMING DIAGRAM~1
WRITE CYCLE I: CS" CS. CONTROLLED
14-----------1,.0·· ------------<-1
ADDRESS
CS,
CS.
I/O
•
Note:
:Don'tCare
~ : Undefined
*1 If OE, CS" and CS. are in thE! READ Mode during this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
*2 All write cycle are determined from the last address transition to the first address transition of next address.
*3 tWR is defined from the end point of WRITE Mode.
*4 Transition is specified at the point of ±500mV from steady state voltage with specffied Load II in Fig. 2.
1-82
MB81 C78A·35
MB81 C78A·45
WRITE CYCLE TIMING DIAGRAM>'
WRITE CYCLE II: WE CONTROLLED
1----------- t
wc·'
..
-----------"'-1
ADDRESS
1--------- tAW ----------+00- tWR'
~-------Icw,------~
CS,
110
[£I : Don't Care
Note:
~ : Undefined
"1 H OE, CS" and CS, are in the READ Mode during this period, 110 pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
"2 All write cycles are determined from the last address transition to the first address transition of next address.
"3 tWR is defined from the end point of WRITE Mode.
"4 Transnion is specified at the point of ±500mV from steady state voltage with specified Load II in Fig. 2.
1·83
MB81C78A-35
MB81 C78A-45
Fig. 3 - NORMALIZED ACCESS
TIME VS. SUPp,LY VOLTAGE
o
Fig. 4 - NORMALIZED ACCESS
TIME VS. AMBIENT TEMPERATURE
o
T.= 25°C
W
!::!
;;!
~~
~i=
1.2
1.1
JgJ
1.0
j~
0.9
-~
0.8
.~
~
~.
t.cs"
toe ""
t, lS2
1.2
JgJ
1.0
-~
0.8
l/
.~
III 0
~< 0.9
j
4.5
5.0
020406080
5.5
Vee. SUPPLY VOLTAGE (V)
T•• AMBIENT TEMPERATURE (OC)
Fig. 6 - NORMALIZED POWER SUPPLY
CURRENT VS. AMBIENT TEMPERATURE
Fig. 5 - NORMALIZED POWER SUPPLY
CURRENT VS. AMBIENT TEMPERATURE
ffi
~!z
c.. tt!
Vee m5.5V
ffi
3:;tOZ
c..tt!
1.2
1.1
00::
I:!:j:::l
::::;0 1.0
~~
0::8:: 0.9
O:::l
zCl)
0.8
"
Vee = 5.5V
1.2
1.1
" '"
00::
w:::l
~o 1.0
~
<>
I"'-
:::!1-'
0::8:: 0.9
O:::l
ZCl)
j
0.8
~
"~
020406080
020406080
T•• AMBIENT TEMPERATURE (OC)
T •• AMBIENT TEMPERATURE (OC)
Fig. 7 - NORMALIZED POWER SUPPLY
CURRENT VS. SUPPLY VOLTAGE
0::
UJ
~t- 1.2
c..z
filtt!
1.1
;;!o
1.0
!::!~
:::!1>
0::-'
~8:: 0.9
Jiil
j
0.8
T. = 25°C
I..,(oc)
Is02 = Cycle min
Is..
~
V
j
1/
~
ISB'
V
4.5
5.0
5.5
Vee. SUPPLY VOLTAGE (V)
1-84
-
~ ~:t.c...tOE
~i=
j
J
~
~~ 1.1
--
"'-
I
Vee =4.5V
W
MB81 C78A-35
MB81 C78A-45
Fig. 8 - NORMALIZED POWER SUPPLY
CURRENT VS. SUPPLY VOLTAGE
I
ffi
:1:1-
1.2
OZ
/
Occ
~::>10
::::iQ
.
<>~..J
cc & 0.9
0::>
Zoo
0.8
V
/
I
UJ
~
T. = 25°C
Icc = Cycle min.
c..~ 1.1
Fig. 9 - NORMALIZED ACCESS
TIME VS. LOAD CAPACITANCE
i= 1.6 T. = 25°C
V
Vee
00
00
UJ
Q
Q
1.4
0
1.2
<
UJ
= 4.5V
N
::::i
,.,.. ---
/
< 1.0
~
cc
0
Z
0.8
j
4.5
5.0
o
5.5
Fig. 10 - NORMALIZED ACCESS
Fig. 11 - NORMALIZED ACCESS
TIME VS. LOAD CAPACITANCE
UJ
~
00
00
UJ
~
I
1.6
i=
T. = 25°C
Vee = 4.5V
00
00
UJ
Q
Q
0
UJ
1.4
,.,..
1.2
< 1.0
~
....
Z
~
T. = 25°C
Vee = 4.5V
Q
Q
1.4
0
1.2
<
UJ
,.,.."'"
/'"
/
N
::::i
/
< 1.0
~
cc
0
I
1.6
UJ
<
N
::::i
200
C" LOAD CAPACITANCE (pF)
TIME VS. LOAD CAPACITANCE
i=
100
Vee, SUPPLY VOLTAGE (V)
/
'"
cc
0
0.8
Z
j
0.8
w
o
100
200
.3
o
C" LOAD CAPACITANCE (pF)
100
200
C" LOAD CAPACITANCE (pF)
Fig. 12 - NORMALIZED POWER SUPPLY
CURRENT VS. FREQUENCY
T. = 25°C
Vee = 5.5V
V,N = V,NIV"
/
----
L
10
t, FREQUENCY (MHz)
1-85
MB81C78A-35
MB81C78A-45
PACKAGE DIMENSIONS
PLASTIC DIP (Suffix: P-SK)
28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-28P-M04)
=t
- _---1·20715.251 MAX
J.11813.001 MIN
-.05011.271
MAX
-----
.02010.511 MIN
TYP
© 1988 fUJITSU LIMITED D28D18S-2C
1-86
-
Dimensions in
inches (millimeters)
MB81 C78A-35
MB81 C78A-45
PACKAGE DIMENSIONS
PLASTIC FPT (Suffix: PF
28-LEAD PLASTIC FLAT
PACKAGEt----+,c,.1",1",0(=-2.cc80",)=M.,.,A-::::X
(Case No. : FPT -28P-M02)
(SEATED HEIGHT)
0(0) MIN
..
r--699+.010(17.75+0.25)~
IR RR.
-.008
-0.20
~I
I
TYP
"A"
i l
,
:'
.008(0.20)
.004(0.10)
.024(0.60)
.650(16.51)
REF---~
.007(0.18)
MAX-.027(0.68)
I
~~~----~
Dimensions in
© 1988 FUJITSU LIMITED F28UlIS-3C
inches (millimeters)
1-87
MB81 C78A-35
MB81C78A-45
PACKAGE DIMENSIONS (Cont'd)
PIN ASSIGNMENT
<:>
CERAMIC PACKAGE
LCC-32C-A02
CERAMIC LCC (Suffix: CV)
32·PAD CERAMIC (METAL SEAL) LEAD LESS CHIP' CARRIER
(CASE No.: LCC·32C-A02)
'PIN NO.1 INOEX
C.Q15(0.38)TYP
.550~:g~~
(13.97
.450~:~~
.460(11.681
TYP
~~:~~)
.065(1.65)
TYP
MAX
• Shape of PIN NO.1 INDEX: Subject to change without notice.
©1988 FUJITSU LIMITED C32011S-3C
1-88
Dimensions in inches
(millimeters)
MB81 C78A-35
MB81 C78A-45
PACKAGE DIMENSIONS
Plastic (Suffix: PJ)
..
28-LEAD PLASTIC LEADED CHIP CARRIER
(Case No. : LCC-28P-M04)
,.
.144(3.66) MAX
.091 (2.31) NOM
.725±.005
(18.42±0.13)
cf
i I
I ·
._n. .
L..J L..O L..J L..O
.050+.005
(1.27±0.13)
1----.650(16.51) REF
=:;~T
J .!j
.340±.005
(8.64±0.13)
o
INDEX
" 't' L..O L..O L..O L..O
.025(0.64) MIN
.273±.020
(6.93±0.51)
.300(7.62)
NOM
•
~
d)-----.l
LJ.
r-----------l
!
II
Details of "A" part
ij032(0.81)
MAX
I
I
II
I
I
I
I
I
i
I
I
I
I
II .017±.004
'(0.43±0.10)
I
I
L _________ .....JI
• : This dimension includes resin protrusion. (Each side: .006 (0.15) MAX)
© 1989 FUJITSU LIMITED &28D54S-1 &
Dimensions in
inches (millimeters)
1-89
High-Speed CMOS SRAMs
1·90
Static RAM Data Book
00
April 1990
Edition 3.0
FUJITSU
DATA SHEET
MB81 C79A-351-45
CMOS 72K-BIT HIGH-SPEED SRAM
..
8K Words x 9 Bits High-Speed CMOS Static Random
Access Memory with Automatic Power Down
The Fujitsu MB81C79A is a 8,192 words x 9 b~s static random access memory
fabricated with a CMOS process. The memory uses asynchronous circuitry and may be
maintained in any state for an indefinite period of time. All pins are TTL compatible and a
single +5 V power supply is required.
A separate chip select (CSj) pin simplifies multipackage systems design by permitting
the selection of an individual package when outputs are OR-tied, and then
automatically powering down the other deselected packages.
•
•
8,192 words x 9 bits
Organization:
Static operation: no clocks or refresh required
•
Access time:
•
tM - tACS1 - 35 ns max.
tACS2 - tOE - 45 ns max.
Low power consumption: 495 mW max.
138 mW max.
83 mW max.
(MB81 C79A-35)
(MB81 C79A-45)
(Operating)
(Standby, TTL level)
(Standby, CMOS level)
PLASTIC PACKAGE
FPT·28p·M02
•
Single +5 V power supply ±1 0% tolerance
•
TTL compatible inputs and outputs
o
Three-state outputs with OR-tie capac~y
•
Chip select for simplified memory expansion, automatic power down
•
Electrostatic protection for all inputs and outputs
•
Standard 28-pin Plastic Packages:
Skinny DIP (300 mil) MB81C79A-xxPSK
SOP
MB81C79A-xxPF
SOJ
MB81C79A-xxPJ
•
Standard 32-pad Ceramic Package:
LCC
(metal seal)
MB81C79A-CV
PLASTIC PACKAGE
LCC·28p·M04
PIN ASSIGNMENT
Absolute Maximum Ratings (See Note)
Rating
Symbol
Value
Unit
Supply Voltage
Vcc
-
~(.) 1.0
<~
~8: 0.9
0::>
j
~
T.- 25°C
Icc - Cycle min.
/
CI)
CI)
/
/
Co::
2(j)
FIg. 9 - NORMALIZED ACCESS
TIME vs. LOAD CAPACITANCE
w
(.)
(.)
I
I
1.4
<
w 1.2
~
/'
<
:::I!
1.0
0
0.8
...
....~
C
.....I
..
T.-25°C
Voo-4.5V
1.6
0::
0.8
2
j
4.5
I
w
:::I!
T.- 25°C
Voo - 4.5V
CI)
CI)
I
1.6
~
~
C
w 1.2
~
.".".
.....I
~
0::
1.0
2
0.8
j
I
<
~
w 1.2
.....I
<
:::I!
a::
1.0
2
0.8
j
100
"
V
~V
~
.".".
~V
1.4
C
0
o
I
T.", 25°C
Vee - 4.5V
1.6
w
(.)
(.)
1.4
<
0
200
Fig. 11 - NORMALIZED ACCESS
TIME vs. LOAD CAPACITANCE
w
(.)
(.)
100
Fig. 10 - NORMALIZED ACCESS
TIME vs. LOAD CAPACITANCE
:::I!
CI)
CI)
o
5.5
Cc. LOAD CAPACITANCE (pF)
w
~
5.0
Voo• SUPPLY VOLTAGE (V)
o
200
100
200
CL• LOAD CAPACITANCE (pF)
CL• LOAD CAPACITANCE (pF)
Fig. 12- NORMALIZED POWER SUPPLY
CURRENTvS.FREQUENCY
ffi
1.4
~~
1.2
3:1-
T•• 25°C
Vee =5.5V
V.. - V"/v,L
Co::
w::>
~(.) 1.0
<~
:::I! a...
25a... 0.8
2~
j
0.6
/
---
,,/'
10
f. FREQUENCY (MHz)
1·101
MB81C79A-35
MB81 C79A-45
PACKAGE DIMENSIONS
PLASTIC DIP (Suffix: P-SK)
28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-28P-M04)
.05011.27)
MAX
© 1988 FUJITSU LIMITED D28018S-2C
1-102
Dimensions in
inches (millimeters)
MB81 C79A·35
MB81 C79A-45
PACKAGE DIMENSIONS
PLASTIC FPT (SUffix: PF)
28-LEAD PLASTIC FLAT PACKAGE
.110(2.80) MAX
J---.....,I;;(S;;:E7
AT;;E:;;O:-;H:;;E:;;IG:::H;:;T)
(Case No. : FPT -28P-M02)
1RiiRI-·&li"'''·[~~
l
·465±.012
(11.80±0.30)
.339±.008
(8.60±0.20)
Lff;;='ii"i'Fi'i"T'Fi'Fi'FiTTi"i'Frr=ftl~
'A"
i i
. :'
.031±.OO8
(0.80±0.20)
.006±.OO2
(0.15±0.05)
r------------,
: Details of "Au part
:
:
.008(0.20)
:
I
I
o
.004(0.10)
I
I
I
I
.650(16.51) REF=---.J
© 1988 FUJITSU LIMITED F28011S-3C
.024(0.60)
I
.007(0.18)
MAX I
I
.027(0.68)
I
I ____________
MAX
L
JI
I
Dimensions in
inches (millimeters)
1·103
MB81C79A-35
MB81C79A-45
PACKAGE DIMENSIONS (Cont'd)
PLASTIC (SUffix: PJ)
28-LEAD PLASTIC LEADED CHIP CARRIER
.
(Case No. : LCC-28P-M04)
144(366) MAX
.091 (2.31) NOM
.725±.005
(18.42±0.13)
.025 (0.64) MIN
==:-T
.273±.020
(6.93±0.51)
.300(7.62)
NOM
s:b~
Ll
,----------l
I
I
i
Details of "A" part
ij03
(0.a1)
2
MAX
I
~--.
,
_--..1.
.102 (2.60) NOM
~
O:OO~~iCJ
\_~
I
I
I
I
I
I
I
I
I
I
I
"A"
I
I
II
.017+.004
I
I
•
(0.43±0.10)
I
L _________
--.J
IE : This dimension includes resin protrusion. (Each side: .006 (0.15) MAX)
© 1989 FUJITSU LIMITED C28054S-1C
1·104
Dimensions in
inches (millimeters)
MB81 C79A-35
MB81 C79A-45
PACKAGE DIMENSIONS (Cont'd)
PIN ASSIGNMENT
N.C
Vee
o
CERAMIC PACKAGE
LCC-32C-A02
CERAMIC LCC (Suffix: CV)
32·PAD CERAMIC (METAL SEAL) LEAD LESS CHIP CARRIER
(CASE No.: LCC·32CA02)
'PIN NO.1 INDEX
.36019.14)TVP
C.01510.38)TVP
MAX
* Shape of PIN NO.1 INDEX: Subject to change without notice.
.30017.62)TVP
Dimensions in inches
(millimeters)
©1988 FUJITSU LIMITED C32011S-3C
1-105
High-Speed CMOS SRAMs
1-106
Static RAM Data Book
cO
May 1990
Edition 1.0
FUJITSU
DATA SHEET
MB81 C81 A-25/-35
CMOS 256K-BIT HIGH-SPEED SRAM
..
256K Words x 1 Bit High-Speed CMOS Static Random
Access Memory
The Fujnsu MB81C81A is a 262,144 words x I bn 51atic random access memory
fabricated wnh a CMOS technology. The MB81C81A uses NMOS cells and CMOS
peripherals and has 300 mil plastic DIP and SOJ packages. It uses fully 51atic circunry
throughout and, therefore, requires no clocks or refreshes to operate.
The MB81C81A is designed for memory applications where high performance,low
co51, large bit storage, and simple interfacing are required. It is compatible w~h TTL
logic and requires a single +5 V supply.
•
•
Organization:
262,144 words x I bit
Static operation: no clocks or refresh required
•
Access time:
PLASTIC PACKAGE
DIP-24P-M03
•
25 ns max. (MB81C8IA·25)
35 ns max. (MB8IC8IA-35)
Single +5 V power supply ±1 0% tolerance with low current drain:
100 mA max. (Active operation)
55 mA max.
(Standby, CMOS level)
30 mA max.
(Standby, TTL level)
•
•
•
Separate data inputs and outputs
TTL compatible inputs and outputs
Chip selected for simplified memory expansion, automatic power down
•
•
Electro51atic protection for all inputs and outputs
Standard 24-pin Plastic Packages:
MB8IC8IA-xxPSK
Skinny DIP
(300 mil)
MB8IC81A-xxPJ
SOJ
(300 mil)
PLASTIC PACKAGE
LCC-24P-M02
PIN ASSIGNMENT
TOP VIEW
AI
Ao
As
AI6
Als
A4
As
A7
A2
Absolute Maximum Ratings (See Note)
Symbol
Value
Unit
Supply Voltage
Rating
Vee
-0.510+7
V
Input Voltaae on any pin w~h
respect to NO
V".
-3.010 +7
V
Output Volt~e on any pin with
respect to G 0
VOUT
-0.5 to +7
V
Output Current
lour
±20
mA
Power Dissipation
Po
1.0
W
Temperature Under Bias
TBIAS
-10to+85
°C
Slorage Temperature Range
TSTG
-45 to +125
°C
Nota: Pennanent davice damage may occur Habsolute maximum ratings are exceeded.
Functional operation should be restriCled to the conditions as detailed in Ihe operation
sections of this data sheet Exposure to absoluta maximum rating conditions for exlanded periods may allect device reliability.
OOUT
WE
GND
Thla _
~.
Vee
All
A12
AS
A9
Alo
A17
AI4
AI3
A3
DIN
CS
contains clraJlUyto proted 1I1e Inputs again"
due to high OIaIlcvollagOloroled,IcI_.
_',I
Is adYIlMId .hal normal prec:au1lons be taken to avoid appIIcalloo
01 any vottage higher than maximum rated voltages to this high
-...crcuh.
Coprrlght © 19110 by FUJITSU LlMIlED and Fo4iIIu M_Ico.lnc.
1-107
MB81 C81 A·25
MB81 C81 A-35
Flg.1- MB81C81A BLOCK DIAGRAM
M
vee
At
•
A2
GND
CELL
RO~
SELE T
A3
ARRAY
•
A4
As
256 ROWS
1024 COLUMNS
•
As
A7
•
•
DIN
•
COLUMN 110 CIRCUITS
I¥I
NT.
WE
DOUT
COLUMN SELECT
As
A9
AtD All A12
A13 A14 A15 A16 A17
POWER
DOWN
CIRCUIT
TRUTH TABLE
a
H
L
L
WE
Mode
X
L
H
Not Selected
Write
Read
CAPACITANCE
1·108
Power
(TA
Legend:
DOUT
Active
H - High level
L- Low level
X- Don't Care
=25°C. f =1 MHz)
Max
Unit
CIN
6
pF
CS Capacitance (ves - 0 V)
ccs
8
pF
Output Capacitance (VOUT - 0 V)
COUT
8
pF
Parameter
Symbol
Input Capacitance (VIN - 0 V)
Typ
MB81 C81 A-25
MB81C81A-35
PIN DESCRIPTION
Symbol
AOtoA17
DIN
Dour
Pin Name
Address Input
Data Input
Data Output
Chip Select
~
Pin Nama
Write Enable
Symbol
"WE
PowerSupp~(5V±10%)
Vee
GND
Ground
RECOMMENDED OPERATING CONDITIONS
Referenced to GND)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Vottage
vee
4.5
5.0
5.5
V
Ambient Temperature
TA *
0
70
·C
* The operating ambient temperature range is guaranteed wnh transverse airflow exceed 2m/sec.
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Condition
Unit
-10
10
ItA
-50
50
ItA
Min
III
Typ
Input Leakage Current
VIN
Output Leakage Current
CS= VIH,
YOUr - OV to vee
ILO
Power Supply Current
CS - VIL, VIN = VIH or VIL
lOur - OmA, Cycle - Min.
ICe
100
mA
cS~Ve~.2V
VIN~Ve~.2V
ISBl
15
mA
CS = VIH, VIN _ VIH or VIL
ISB2
30
mA
vee - ov to vee Min.,
CS - Lower of vee or VIH Min.
IPO
30
mA
z
OV to vee
Max
Symbol
or VINSO.2V
Standby Supply Current
Peak Power on Current
*1
Input High Vottage
VIH
2.2
6.0
V
Input Low Vottage
VIL
-{l.5 *2
O.B
V
2.4
Output High Voltage
IOH --4mA
VOH
Output Low Vottage
IOL" BmA
VOL
V
0.4
V
*1 A pull-up resistor to Vee on the CS input is required to keep the device deselected; otherwise, power-on current
approaches Icc active.
*2 -2.0 V Min. lor pulse width less than 10 ns.
1-109
MB81C81A-25
MB81 C81 A-35
AC TEST CONDITIONS
•
•
•
•
Output Load:
Input Pulse Levels:
0.6 Vto 2.4 V
Input Pulse Rise and Fall Times:
2 ns (0.8V to 2.2V)
Timing Reference Levels:
Input:
VIL - 0.8, VIH - 2.2 V
Output: VOl.. _ 0.8, VOH _ 2.2 V
OOUT
Fig. 2
TR'
I l~
CL-.l
Rt
R2
CL
Parameters Measured
Load I
4800
2550
30pF
except tLl, tHZ, tOW and tWZ
Load II
4800
2550
5pF
tLl, tHZ, tOW and tWZ
"Including Scope and Jig capacHance
AC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted.)
Parameter
"1 ""WE is high for Read cycle.
"2 All Read cycles are determined from the last address transHion to the first address transition of next cycle.
"3 Device is continuously selected, ~-VIL.
"4 Address valid prior to or coincident wHh ~transHion low.
"5 TransHion is measured at the point of ±500mV from steady state voltage with specnied Load II in Fig. 2.
1-110
MB81C81A-25
MB81C81A-35
READ CYCLE TIMING DIAGRAM
READ CYCLE: ADDRESS CONTROLLED *1 *3
..
*2
~---------tRC------------~
Valid
ADDRESS
tOH
DATA OUT
Previous Data
Valid
Data Valid
READ CYCLRS CONTROLLED *1 *4
*2
~----------tRC----------~
Valid
ADDRESS
*4
~------tACS'------~
Data Valid
DATA OUT
IcC
ISB
__
b~~'"-~~tPD~
-'f
SO%
SO%
__
jL
I8EI :Undefined lZ3: Don't Care
*l~is high for Read cycle.
*2 All Read cycles are determined from the last address transnion to the first address transition of next cycle.
*3 Device is continuously selected, 'Cs-.VIL
*4 Address valid prior to or coincident wnh ~ transnion low.
*S Trans"ion is measured at the point of ±SOOmV from steady state voltage w~h specHied Load II in Fig. 2.
1-111
MB81C81A-25
MB81C81A-35
AC CHARACTERISTICS (Continued)
conditions unless otherwise noted.)
Parameter
WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE:WE CONTROLl.ED *1 *2
tWC*::,3--------,---t
1--------
ADDRESS
Valid
~---- tCW-----~
~------~W-----~~
I:=
~S
tWP --~
1,-------
DATA IN
DATA OUT
*1 CS or WEmust be high during addrU!.,transitions.
*2 " CS goes high simultaneously with WE high. the output remains in high impedance state.
*3 All Write cycles are determined from the last address transition to the first'address transition of next cycle.
*4 Transition Is measured at the point of ±500mV from steady state voltage with specified Load II in Fig. 2.
1-112
MB81C81A-25
MB81 C81 A-35
WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: CS CONTROLLED 'I '2
..
~------------- tWC~3------------~
Valid
ADDRESS
~---:-------- tAW
----------.j
~------- tCW------~
~-----tWP-----~
....- - - - tOW
DATA IN
DATA OUT
____~(
~
~~__________
H_g_h-_Z___________
a:
Undefined
1Z1: Don~ Care
'I CS or WE must be high during address trans~ions.
'2 If CS goes high simukaneously with WE high, the output remains in hgh impedance stale.
'3 All Write cycles are determined from the last address trans~ion to the first address trans~ion of next cycle.
'4 Transition is measured at the point of ±500mV from steady state voltage with specified Load II in Fg. 2.
1-113
MB81 C81 A-25
MB81 C81 A-35
PACKAGE DIMENSIONS
24-LEAD PLASTIC SKINNY DUAL IN·LlNE PACKAGE
(CASE No.: Dlp·24p·M03)
:::::~: :::,;":~::: ~ ~5~l:'
.300(7.621
rvp
(29. 72:g:~gl
! !"'"~'."
.050(1.271
MAX
.100(2.541
TYP
.118(3.00IMIN
I .1
.018±.003
(0.46±0.081
.02Q(0.51IMIN
Dimensions in
inches (millimeters)
© 1988 FUJITSU LIMITED D24017S-3C
1-114
MB81C81A-25
MB81C81A-35
PACKAGE DIMENSIONS Continued
24-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCC-24P-M02)
I
o
1-
005
(S.64< 0.13)
.273±.020
(6.93±0.51)
.30017.62)
=;=;=;=a=~::;::;?I~r
I9,rcf;=;=r=;=;=r'NDE=n=;X
~
r
<=:tJ~
r-
.050<.005
(1.27<0.13)
.550(13.97)REF
•. 615±.005(15.62±0.13)
.
..
r-F?1I
.025(0.64)
MIN
.091(2.31)
NOM
"b
.144(3.66)
MAX
~032(0'S1)MAX
Detadsof"A"part
~ooo"",
nnn :, ;nnnililil
NOM
--,
"A"
1..::..1
004(01011
*. This dimensIOn Includes resin protrusion (Each Side .006(0 15)MAX)
. I
I<
--1.
0171004
(O.43::tO.l0)
DimenSions In
Inches (millimeters)
C1989 FUJITSU LIMITED C24052S·1C
1-115
High-Speed CMOS SRAMs
1-116
Static RAM Data Book
cO
May 1990
Edition 1.0
FUJITSU
DATA SHEET
MB81 C84A-251-35
CMOS 256K-BIT HIGH-SPEED SRAM
64K Words x 4 Bits High-Speed CMOS Static Random
Access Memory
The Fujitsu MB81C84A is a 65,536 words x 4 bits static random access memory
fabricated with CMOS silicon gate process technology. The MB81 C84A uses NMOS
cells and CMOS peripherals and is housed in 300 mil plastic DIP and SOJ packages.
The MB81 C84A uses fully static circuitry and, therefore, requires no clocks or
refreshes to operate. It is compatible with TTL logic and requires a single +5 V supply.
It is designed for memory applications where high performance, low cost, large bit
storage, and simple interfacing are required.
•
•
•
•
•
•
•
•
•
•
Organization:
65,536 words x 4 bits
Static operation: no clocks or refresh required
Access time:
25 ns max. (MB81 C84A-25)
35 ns max. (MB81C84A-35)
Single +5 V power supply ±1 0% tolerance with low currant drain
100 mA max. (Active operation)
15 mA max.
(Standby operation, TTL level)
30 mA max.
(Standby operation, CMOS level)
PLASTIC PACKAGE
DIP-24P-M03
Common data inputs and outputs
TTL compatible inputs and outputs
Chip select for simplified memory expansion, automatic power down
Three-state outputs with OR-tie capacity
Electrostatic protection for all inputs ansi outputs
Standard 24-pin Plastic Packages:
Skinny DIP (300 mil) MB81C84A-xxPSK
SOJ
(300 mil) MB81C84A-xxPJ
PLASTIC PACKAGE
LCC-24P-M02
PIN ASSIGNMENT
TOP VIEW
Absolute Maximum Ratings (See Note)
Rating
Supply Voltage
Input Vo~e on any pin with
respect to NO
Symbol
Value
Unit
Vee
-{l.5 to +7.0
V
VIN
-3.0 to +7.0
V
Output Volta2e on any pin with
respect to G 0
VOUT
-(l.5 to +7.0
V
Output Current
lour
±20
rnA
Power Dissipation
Po
1.0
W
Temperature Under Bias
TSIAS
-10to +85
"C
Storage Temperature Range
TSTG
-45 to +125
"C
Note: Permanent devioB damage may occur HabsoIul8 maximum ratings II1II exceeded.
Functional operation should be reslricled 10 Ihe conditions as detailed in the operation
sections of this data sheet Exposure 10 ebsolul8 maximum rating conditions far 8Xlanded periods may allect devioB reliabi6ty.
AI
vee
AD
All
AI2
As
AI4
AI3
As
1.9
AIO
AIS
V04
1!03
V02
A4
As
A7
A2
A3
CS
GND
ThIo _
VOl
WE
_Io_·_r.1
00IIIaI.. _HI)' to pruIoc:IlholnpUlO against
_due"'hIuII
.....lovolblgoo ...
lIodv1oodlhlll _ _ 1onI be-' t o _ appIcallan
01.., WIIIago hlgha'''''' naxlnllm _
Irnpodonco _L
votau- II> this high
1-117
MB81 C84A-25
MB81 C84A-35
Fig. 1 - MB81C84A BLOCK DIAGRAM
AD
vee
A1
•
A2.
ROW
SELECT
A3
•
A4
As
GND
CELL
ARRAY
256 ROWS
1024 COlUMNS
•
As
A7
•
•
•
COLUMN va CIRCUITS
INPUT
DATA
CONT.
COLUMN SELECT
As
A9 A10 A11 A12 A13 Ai4 A15
WE'~~~------------------------------------------------------------~
POWER DOWN CIRCUIT
TRUTH TABLE
CS
WE
Moda
110
Ii
X
L
L
L
H
N01 SeleC1ed
WrHe
Read
DIN
DOUT
Power
AC1iYe
AC1iYe
Legend:
H = High leyel
L= Lowleyel
X =Don1 Care
CAPACITANCE, ITA =25°C f =1 MHz)
1·118
Max
Un"
CIN
6
pF
CS CapacHance (VeS - 0 V)
C~
8
pF
Output Capacitance (VOUT - 0 V)
caUT
8
pF
Paramatar
Symbol
Input Capacitance (VIN _ 0 V)
Typ
MB81 C84A·25
MB81C84A-35
PIN DESCRIPTION
Symbol
AotoA15
1/01 to 1104
Pin Name
Address Input
Data InputslData Outputs
Chip Select
~
Symbol
Pin Name
WE
vee
GND
Wr~eEnable
..
Power Supply (5V±10%)
Ground
RECOMMENDED OPERATING CONDITIONS
Referenced to GND)
Parameter
Symbol
Min
Typ
Max
Unit
vee
4.5
5.0
5.5
V
70
·C
Supply VoHage
,
Ambient Temperature
TA
0
, The operating ambient temperature range is guaranteed with transverse airflow exceed 2m/sec.
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Condition
Parameter
Symbol
Min
Typ
Max
Unit
Input Leakage Current
VIN = OV to Vee
III
-10
10
J.LA
Output Leakage Current
CS- VIH,
VOUT _ OV to 4.SV
ILO
-50
50
J.LA
Power Supply Current
CS • VIL, VIN = VIH or VIL,
lOUT _ OmA, Cycle _ Min.
Icc
100
mA
"US"6C1~~_ _ _ _~~~~_toH
__-::~~p~XX~____________
READ CYCLE II: CS CONTROlLED *3
....--------tRC--------~
DOUT
•
Nota:
1-140
*1
*2
*3
*4
: Don't Care
~: Undefined
WE Is high for Read Cycle.
Device Is continuously selected. CS = VIL, and OE=VIL
Address valid prior to or coincident with CStransition low.
Transition Is specified at the point of ±500mV from steady state voltage with specified Load II in Fig. 2.
MB8298-25
MB8298-35
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
WRITE CYCLE·'
MB8298-35
MB8298-25
Parameter
Unit
Symbol
Min
Min
Mall
Mall
Write Cycle Time"'
twe
25
35
ns
Address Valid to End of Write
tAW
18
28
ns
CS to End of Write
tew
16
26
ns
Data Setup Time
tOW
8
12
ns
Data Hold Time
tDH
0
0
ns
Write Pulse Width
IWP
15
20
ns
Write Recovery Time"'
tWR
0
0
ns
Address Setup Time
lAS
0
0
ns
Output Low-Z from WE"'
lOW
0
0
ns
Output High-Z from WE"'
IWZ
0
8
0
14
ns
WRITE CYCLE llMING DIAGRAM ·1
WRITE CYCLE I: WE CONTROLLED
ADDRESS
twe"'
Valid
tM@iF@@it)
J[t~@lttnn
flili@##
f- tWR"·..j
tAW
~-----tWP------~
tOH
tOW
I-- tWZ"'~
va
~
~
lEI :Don't Care
Nota:
"I
"2
"3
"4
tOW"'
DIN ValidJQ{
~: Undefined
HCS goes high simultaneously with WE high, the output remains in high impedance state.
All Write Cycles are determined from the last address transition to the first address transition of nell! address.
IWR is defined from the end point of Write Mode.
Transition is specHied at the point of ±500mV from steady state voltage with specHied Load II in Fig. 2.
1-141
MB8298·25
MB8298-35
WRITE CYCLE TIMING DIAGRAM*'
WRITE CYCLE No.2 (CS CONTROLLED)
ADDRESS
110
•
Note:
1·142
*1
*2
*3
*4
: Don't Care
~ : Undefined
If CS goes high simultaneously with WE high, the output remains in high impedance state.
All Write Cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of Write Mode.
Transition is specnied at the point of ±500mV from steady state voltage with specified Load" in Fig. 2.
MB8298-25
MB8298-35
PACKAGE DIMENSIONS
28-LEAD PLASTIC DUAL-IN-LiNE PACKAGE
(CASE No.: DlP-28P-M04)
..
.050(1.27)
MAX
Dimensions in
© 1988 FUJITSU LIMITED D28018S-2C
inches (millimeters)
1-143
MB8298-25
MB8298-35
PACKAGE DIMENSIONS (Continued)
Plastic FPT (Suffix: PJ)
28-LEAD PLASTIC FLAT PACKAGE
(CASE NO.: FPT-28P-M02)
.11 02
I. BO) MAX
ISEATED HEIGHT)
010) MIN
ISTAND OFF)
iRRHI'''·&\ii'''·'''&~iifll
l
d
-
·465±.012
111.BO±0.30)
r-
.339±.00B
IB.60±0.20)
INOEX
~:;;::;:;:::n=:n=;:;::::;:t=i;;=;;=n=;~~
'-
1.-=
II
"A"
J
.402±.012
110.20±0.30)
.031 ±.O08
10.BO±0.20)
.006 ± .002
10.15±0.05)
r------------
:
Details of "A" part
:00810.20)
I
I
I
.02410.60)
1---.650(16.51)
.00710.18)
MAX
.02710.68)
REF--~-I
-
© 1990 FUJITSU LIMITED F2BD11S-4C
1-144
I
-- -~~~ ----~
Dimensions in
inches (millimeters)
MB8298-25
MB8298-35
PACKAGE DIMENSIONS (Continued)
Plastic FPT (Suffix: PJ)
..
28-LEAD PLASTIC LEADED CHIP CARRIER
(CASE NO.: LCC-28P-M04)
h
IJ", .:'jMI ."
1441366) MAX
* .725±.005
t
0911231) NOM
11B.42±0.13)
.340±.005
IB.64±0.13)
.30017.62)
NOM
.273±.020
16.93±0.51)
!)~
Ll
I----------l
I
I
I
Details of "A" part
.03210.B1)
MAX
I
~-.
-----.L
.10212.60) NOM
I
~
l_~ "A"
CloI00410 .10)
I
I
I
I
I
I
I
I
I
:
I
I
:L _________
·11· Ig~~!g~)
I
i
----.I
....--: This dimension includes resin protrusion. (Each side: .006 (0.15) MAX)
© 1989 FUJITSU LIMITED C28054S-1 C
Dimensions in
inphes (millimeters)
1-145
High-Spsed CMOS SRAMs
1-146
Static RAM Data Book
cP
September 1990
Edition 1.0
FUJITSU
DATA SHEET
MB8299-251-35
GMOS 288K-BIT HIGH-SPEED BiGMOS SRAM
32K Words x 9 Bits BiCMOS High-Speed Static
Random Access Memory
The Fujitsu MB8299 is a high-speed static random access memory organized as
32,768 words x 9 bits and fabricated with CMOS technology. To obtain a smaller chip
size, the cells use NMOS transistors and resistors.The MB8299 is housed in 300 mil
plastic DIP and SOJ packages, and a 450 mil SOP package. All pins are TIL
compatible and a single +5 V power supply is required.
A separate chip select (CS,) pin simplifies multipackage systems design by permitting
the selection of an individual package when outputs are OR-tied, and then
automatically powering down the other deselected packages.
Plastic Package
(01 P-32P-M02)
The MB8299 offers low power dissipation, low cost, and high performance.
•
Organization:
•
Static operation: no clocks or timing strobe required
32,768 words x 9 bits
•
Access time:
Plastic Package
(LCC-32P-M04)
1M = tACS = 25 ns max. (MB8299-25)
tM - tACS = 35 ns max. (MB8299-35)
•
Low power consumption:
715 mW max.
605 mW max.
138 mW max.
27.5 mW max.
o
Single +5 V power supply ±1 0% tolerance
•
TTL compatible inputs and outputs
(Operating) for 25 ns
(Operating) for 35 ns
(TTl Standby)
(CMOS Standby)
Plasdc Package
(FPT-32P·M02)
•
Three-state outputs with OR-tie capability
•
Electrostatic protection for all inputs and outputs
•
Standard 32-pin Plastic Packages:
Skinny DIP (300 mil) MB8299-xxPSK
SOJ
(300 mil) MB8299-xxPJ
SOP
(450 mil) MB8299-xxPF
Pin Assignment
ITOPVIEWI
Absolute Maximum Ratings (See Note)
Rating
Symbol
Value
Unit
Supply Voltage
Vee
-0.510+7
V
Input Vohaae on any pin with
respect to NO
VN
-3.510+7
V
VOUT
-0.5 to +7
V
Output VOha~e on any
respect to G 0
va pin with
Output Current
lOUT
±20
mA
Power Dissipation
Po
1.0
W
Temperature Under Bias
TBlAs
-10to+85
°C
Storage Temperature Range
TSTG
-45 to +125
°C
Note: Permanent device damage may occur il absolute maximum ratings are exceeded.
Functional operation should be restricted to !he conditions as detailed in the operation
sections of this data sheet. Exposure to absolute maximum rating conditions for axtended periods may aHect device reliability.
NC
NC
VCC
A7
AS
AS
A4
A3
A2
AI
AO
A12
A13
1/01
CS2
1102
1/03
1/04
GND
WE
AS
A9
Al0
All
OE
A14
CSI
1/09
1/08
V07
vas
V05
Th. device contans clrQ,lItry 10 pl'Ol8cl the Inputs against
Howew'.
damage due to high sialic " " ' - or oIec1rlc 1101ds.
n
Is adviaed that normal precautions be taken to avoid applcatlon
of any wtIage highaf' than maximum rated voltages to thi8 high
lJT1)8danceclrwlt.
Copyright © 1990 by FUJITSU LIMITED and Fujllau Mlcroeloclronlco. Inc.
1-147
..
MB8299-25
MB8299-35
Fig. 1 - MB8299 BLOCK DIAGRAM
Ao
Al
~
A2 A3
ADDRESS
BUFFER
A4-
---•
M_
106
A7
•
•
-
. - Vee
•
•
•
ROW
DECODER
. - GND
256 x l28x9
MEMORY CELL ARRAY
t--
I'"---
I •
As
As
Al0 ::
All
A12 A13 _
A14
ADDRESS
BUFFER
•
•
•
•
•
I/O GATE &
COLUMN DECODER
I
OE
•
•
•
DATA 110 BUFFER
BUFFER
WE
~ ~ ~ ~ ~ ~
11(
VOl 1102 1103 V04 1105 1106 1107 1108 V09
CS1U-1CfJCS2o_
Y
POWER DOWN
CIRCUIT
TRUTH TABLE
CS1
H
L
L
L
L
CS2
WE
X
L
H
H
H
X
X
H
H
L
OE
X
X
H
L
X
SUPPLY
CURRENT
ISB
STANDBY
ICC
DESELECT
ICc
DouT DESABLE
READ
ICC
WRITE
ICC
MODE
110 PIN
HIGH·Z
HIGH·Z
HIGH·Z
DOUT
DIN
CAPACITANCE (TAl: 25°C,'= 1MHz)
Parameter
CondIUon
Symbol
MIn
Typ
Max
Unit
Input Capacitance (CS1, CS2 OE. WE)
VIN-OV
Cll
8
pF
Input Capacitance (Other Input)
VIN-OV
012
7
pF
110 Capacitance
VIIO-OV
eve
8
pF
1·148
MB8299-25
MB8299-35
RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter
Supply Vo~age
Ambient Temperature
Symbol
Min
Typ
Max
vee
4.5
5.0
5.5
V
TA
0
70
·C
Unit
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
I 25ns
135ns
Min
Max
Unit
ISSI
CS1:!: vee -o.2V
VIN :!: VeC-O.2V or VIN S0.2V
5
mA
1SB2
VINsO.2V
CSl-VIH
25
mA
ICC
lOUT - OmA. CSI - Vil
Cycle-Min.
130
110
mA
Standby Supply Current
Operating Supply
Current
Test Condition
III
VIN - OV 10 vee. vee - Max.
-5
5
JIA
Output Leakage Current
IlltO
CSI - VIH or CS2 - Vilor
WE - Vil or OE _ VIH.
VIIO - OV to Vee
-5
5
JIA
Input Low Voltage
Vil
-2.0·'
O.S
V
Input High Voltage
VIH
2.2
6.0
V
Output High Voltage
VOH
IOH--4mA
Output Low Voltage
VOL
IOl_SmA
Input Leakage Current
V
2.4
V
0.4
Note: ·1 -2.0V Min. for pulse width less than 20% of cycle time. (Vll min.-·.·ii . . . . . . . . .·. . i.·.i·.i\.·.···.i
Max.
Min.
··i).}\
··········r
Read Cycle TIme '2
tRC
Address Access TIme '3
fAA
25
35
ns
fAcs
25
35
ns
15
ns
Chip Select Access Time
'4
25
35
ns
Output Enable Access TIme
tOE
Output Hold from Address Change
IOH
5
5
ns
5
ns
10
Chip Selection toOutput in low·Z
'5
's
telZ
5
Chip Selection to Output in High·Z
'5'S
teHZ
2
Output Enable to Output in low-Z
'5'S
IOlZ
0
Output Enable to Output in High-Z '5 's
10HZ
0
Chip Selection to Power Up time
If'U
0
Chip Deselection to Power Down
If'D
15
2
15
0
15
0
20
ns
ns
15
0
'I WE is high lor Read cycle.
'2 All Read cycles are determined from the last address transition to the first address transition of next cycle.
'3 Device is continuously selected, CS=Vll OE=VL
'4 Address valid prior to or coincident with CS transition low.
'5 Transition is measured at the point of ±5OOmV from steady state voltage.
's This parameter is measured with specified load II in Fig. 2.
2-16
Max.
ns
ns
30
ns
MB82BOO5-25
MB82BOO5-35
READ CYCLE TIMING DIAGRAM
READ CYCLE: ADDRESS CONTROLLED 'I '3
'2
~-------------tRC------------~
Jr-~~~
Valid
ADDRESS
DATA OUT
Previous Data
Valid
Data Valid
READ CYCLE: CS CONTROLLED 'I '4
ADDRESS
t--------- tACS
--------~
DATA OUT
Icc
ISB
~
:Undefined
o:
Don't Care
'I WE is high for Read cycle.
'2 All Read cycles are determined from the last address transition to the first address transition of next cycle.
'3 Device is continuously selected, CS=VIL, OE=VL
'4 Address valid prior to or coincident with CS transition low.
'5 Transition is measured at the point of ±5OOmV from steady state voltage.
'6 This parameter is measured with specified Load II in Fig. 2.
2·17
MB82BOO5-25
MB82BOO5-35
AC CHARACTERISTICS
(Continued)
(Recommended operating conditions unless otherwise noted.)
Parameter
Unit
Symbol
Min.
.· . . . i i
IWi-liTgC'f£lE
.i{/
......... \;.
ii
( i i .iiii.
} t• i
Write Cycle TIme '3
twe
25
35
ns
Chip Selection to End of Write
tcw
16
26
ns
Address Valid to End of Write
tAW
18
28
ns
Address Setup TIme
tAs
0
0
ns
Write Pulse Width
twp
15
20
ns
Data Valid to End of Write
lOw
8
12
ns
Write Recovery Time
twA
0
0
ns
Data Hold TIme
tDH
0
0
ns
twz
0
tow
0
Write Enable to Output in High-Z
'4 °5
°4 °5
Output Active from End of Write
8
14
0
WRITE CYCLE TIMING DIAGRAM
-
°3
twe
ADDRESS
CS
~
---
\\\\
~
WE
Valid
tew
I/
t AS
---1
tWA
/
/
/
/
tAW
twp
\\
V
---
- t ow Valid
DATA IN
I-
~ '4°5
wz"
DATA OUT
~ r;:;";"';;:::::~;;;;;;;;::
t
/
XXXXXXXXXX1/
I\.
tOH
~
'4°5
tow-
High-Z
~
:Undefined
ns
ns
0
WRITE CYCLE: WE CONTROLLED'l '2
[2J
'1 C~ WE must be high during addredanco circuit.
Copyright © 1890 by FWrrsU LIMITED IOId Fullt8u M_ronico. Inc.
2-21
MB82BOO6-25
MB82B006-35
Fig. 1 - MB82B006 BLOCK DIAGRAM
Vee
•
GND
ROW
SELECT
CELL
ARRAY
512 ROWS
512COLUMNS
x4
•
•
•
11 - - - - - - - - 1
12--------1
13--------1
•
•
01
•
INPUT
DATA
CONTROL
•
CotUMN
02
va CIRCUITS
03
•
04
14--------1'y,
COLUMN SELECT
POWER
DOWN
CIRCUIT
TRUTH TABLE
cs
WE
Mode
Oulput
Po_
H
X
Not Selected
High-Z
Standby
L
H
Read
Dour
Ache
L
L
Write
High-Z
Actiw
Legend: H =High level
L=Low lewl
X = Don't Care
CAPACITANCE (TA = 25°C f =1 MHZ)
Param_
2·22
Symbol
Typ
Mu
Unll
Inpul Capacitance (VIN = 0 V)
CIN
6
pF
CS Capacitance (~ = 0 V)
CllS
7
pF
Oulpul Capacitance (Vour = 0 V)
Cour
7
pF
MB82BOO6-25
MB82BOO6-35
PIN DISCRIPTION
Symbol
Pin name
Symbol
Pin name
AOtoA17
Address Input
Write Enable
11 to 14
Date Input
WE
Va;
01 to 04
Data Output
GND
Ground
CS
ChipSeiect
NC
No Connect
Power SupplYU-10%)
RECOMMENDED OPERATING CONDITIONS
Referenced to GND)
P.r8JII.....
Symbol
Supply Voltage
Va;
Ambient Temperature
TA
Min
Typ
Max
Unit
4.5
5.0
5.5
V
70
°c
0
DC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted.)
Par.m.....
Teat Condition
Symbol
Min
III
-1
1
IJA
VOUT = OV to Va;
Va; = Max.
ILO
-1
1
IJA
CS = VIL, louT- OmA
Vrr. • Msov . VIN • VII nr VI"
Va; = Max., CS = V,L
Cycle = Min., lOUT = OmA
1a;1
Y,N = OV to Va;
Va; = Max.
Input Leakage Current
Typ
Max
Unit
CS=VIH
Output Leakage Current
Actiw Supply Current
Va; = Min. to Max.
CS ;" Va; ..{).2V
VIN;" Va; - 0.2V or VIN
Standby Current
~
50
80
rnA
1CC2
80
120
1581
2
15
0.2V
rnA
Output
Low Voltage
1582
rnA
VOL
IOL =8
OullllJ t Hiah Voltaae
'1
Peak Power on Current
Va; = Min. to Max.
CS=VIH
10H=-4mA
VOH
Va; = OV to Va; Min.
CS = Lower 01 Va; or
VIH Min.
Ipo
Input Low Voltage
VIL
Input High Voltage
VIH
10
25
0.4
2.4
V
50
..{).5'2
2.2
V
rnA
0.8
V
6.0
V
'1 A pull-up resistor to Vcc on the CS input is required to keep the device deselected; otherwise, power-on current approaches Icc active.
'2 --,1.0 V Min. lor pulse width less !han 20 ns.
2·23
MB82BOO6-25
MB82BOO6-35
AC TEST CONDITIONS
•
Input Pulse Levels:
0.6 VIII 2.4 V
•
Input Pulse Rise and Fall Times:
3 ns (Transient between 0.8V and 2.2V)
•
Timing Reference Levels:
Input:
Output:
•
Output Load:
VIL = 0.8, VIH = 2.2 V
VOL = 0.8, VOH = 2.2 V
Fig. 2
5V
R1
Dou~----~--------~
R2
Paremeters Measured
except tLZ, 1HZ, tOW and tWZ
tLZ, 1HZ, tOW and tWZ
'Including Scope and Jig capacitanos
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Chip Select Access Time
'4
Output Hold from Address Change
lACS
25
35
ns
25
35
ns
IOH
5
2
Chip Selection III Power Up time
IPU
Chip Deselection 10 Power Down
lPo
5
t5
o
2
o
20
'I WE is high for Read cycle.
'2 All Read cycles are determined from the last address transition III the first address transition of next cycle.
'3 Device is continuously selected, ~=VL,'4 Address valid prior III or coincident with CS transition low.
'5 Transition is measured at the point of ±5OOmV from steady state voltage.
'6 This parameter is measured with specified Load II in Fig. 2.
2-24
ns
15
ns
ns
30
ns
MB82BOO6-25
MB82BOO6-35
READ CYCLE TIMING DIAGRAM
READ CYCLE: ADDRESS CONTROLLED '1 '3
'2
~------ tAC~-----"""'"
..Irr,..,.,~..,..,..
Valid
ADDRESS
DATA OUT
Previous Data
Valid
Data Valid
READ CYCLE: CS CONTROLLED'1 '4
'2
~------ tAC
-------1
Valid
ADDRESS
~---tACS
----I
DATA OUT
Icc
Isa
g
:Undefinad
E2J :Don't Care
'1 We is high for Read cycle.
'2 All Read cycles are detanninad from the last adaess transition to the first address transition of next cycle.
'3 Device is continuously selectad, CS=VL.
'4 Address valid prior to or coincident with CS transition low.
'5 Transition is measured at the point 01 ±5OOmV from staady stale voltage.
'6 This pararnetar is measured with specified Load II in Fig. 2.
2-25
MB82BOO6-25
MB82BOO6-35
AC CHARACTERISTICS (Continued)
(Recommended .. N
••Atln ..
conditions unless otherwise noted.)
Write Cycle Time *3
!We
25
35
ns
Chip Selection to End 01 Write
tcw
16
26
ns
Address Valid 10 End 01 Write
lAW
18
28
ns
Address Setup Time
lAS
0
o
Write Pulse Width
IWP
15
20
ns
Data Valid 10 End 01 Write
tow
10
15
ns
Write Recovery Time
IWR
0
o
ns
Data Hold Time
IDH
0
o
ns
IWZ
0
low
0
Write Enable 10 Output in High-Z
Output Active from End 01 Write
*4 *5
*4 *5
_
10
o
15
o
ns
WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: WE CONTROLLED *1 *2
*3
~-------------------twc~------------------~
Valid
ADDRESS
.....------------- tew
---------------10/
~------twp------~
DATA IN
DATA OUT
~ ~~ ~~~
_
__
__
____
~~ ~
t~*4~~
__~
~____________
High-Z
~
CS WE
: Undefined
EZJ :Don't Care
*1
or
must be high during address transitions.
*211 ~ goes high simultaneously with WE high, the output remains in high impedance state.
*3 All Write cycles are determined from the last address transition 10 the lirst address transition 01 next cycle.
*4 Transition is measured at the point 01 ±50OmV from steady state Voltage.
*5 This parameter is measured with specified Load II in Fig. 2.
2-26
ns
MB82BOO6-25
MB82BOO6-35
WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE: CS CONTROLLED "1 *2
"3
~---------------t~~------------~
Valid
ADDRESS
....- - - - - - - tAW -----------~
~-------- tew
--------.I
DATA IN
Valid
High-Z
DATA OUT
~
<: ~~_______________
~
:Undefined
H_i9_h_-Z
______________
(Zl :Don't Care
"1 Cs or WE must be high during address transitions,
"2 If ~ goes high simultaneously with ~high, the output remains in high impadanos state.
"3 All Write cycles are determined from the last address transition to the first address transition of next cycle.
"4 Transition is measured at the point of ±5OOmV from steady state voltage.
"5 This parameter is measured with specified Load II in Fig. 2.
2-27
MB82BOO6-25
MB82B006-35
PACKAGE DIMENSIONS
32-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCC-32P-M(3)
14413 66) MAX
t=",. -""".,.~
•
1
0
O
.09112.31) NOM
.02SI0.64) MIN
I
440±00S
11118±013)
.400(10.16)
o--INDEX
T·. . . . . . . . . . . . . . . . . . . . . . . . . . ·
~~
~M
.050±.00S
11.27 ±0.13)
.370±.020
19.40±0.SI )
r------------------------,
I
:
I
Details of "A" part
I
I
1-'--.7S0119.0S) REF---
"A"
:-,
r------------------+-,~---.
R-...............'I""FI"...,A"""FrR"R""F.............lrRrFI.1 0212.60) NOM
, ----...1...
:
I
I
I
I
I
I
I
I
I
l
I
.03210.81)
MAX
I
I
.
I
I
:
.017±.004
l______ --'JJ·___ ~~~~_±_O~~~)__ •
!IE :
This dimension includes resin protrusion. (Each side: .006(0.15) MAX)
© 1990 FUJITSU LIMITED C32020S-1 C
2-28
Dimensions in
inches (millimeters)
OJ
September 1990
Edition 1.0
FUJITSU
DATA SHEET
MB82B78-151-20
64K-BIT HIGH-SPEED BiGMOS SRAM
8K Words x 8 Bits High-Speed Static Random
Access Memory
The Fujitsu MB82B78 is a static random access memory organized as 8,192 words x 8
b~sand fabricated with CMOS silicon gate process. BiCMOStechnology is used in the
peripheral circuits 10 provide lower power dissipation and higher speed. To obtain a
smaller chip size, the cells use NMOS transistors and resislors.
The MB82B78 is housed in 300 mil plastic DIP and SOJ packages, and a450milplastic
SOP package. The memory uses asynchronous circuitry and requires +5 V power
supply. All pins are TTl compatible.
The MB82B78 has low power dissipation, low cost, and high performance, and it is
ideally suited for usa in microprocessor systems and other applications where fast
access time and ease of use are required.
•
•
Organization:
8,192 words x 8 bits
Static operation: no clocks or timing strobe required
•
•
Access time:
1M - tACS1 -15 ns max., W:sz - toe - 8 ns max (MB82B78-15)
1M - tACS1 - 20 ns max., W:sz - toe - 10 ns max (MB82B78-20)
Single 5 V power supply ±1 0% tolerance with low current drain:
120 mA max. (Operating)
30 rnA max. (TTl Standby)
15 mA max. (CMOS Standby)
•
BiCMOS peripheral circuits
Plastic Package
(DIP-2aNl04)
Plastic Package
(FPT-28P-II02)
Plastic Package
• TTl compatible inputs and outputs
(LCC-28P-M04)
•
Three-state outputs
•
•
Electrostatic protection for all inputs and outputs
Standard 28-pin Plastic: Packages:
Skinny DIP (300 mil)
MB82B78-xxPSK
SOP (450 mil)
MB82B78-xxPF
MB82B78-xxPJ
SOJ(300mil)
PIn Assignment
(TOP VIEW)
Supply Voltage
Input Volt:'ae on any pin with
respectto NO
Symbol
Value
Unit
Vee
-0.510+7
V
V..,
-3.510+7
V
Output vo~e on any 110 pin with
respect to G 0
VI'O
-0.510+7
V
Output Current
lOUT
±20
mA
Power Dissipation
Temperature Under Bias
~
As
WE
CS.
A.
Absolute Maximum Ratings (See Note)
Rating
NC
PD
1.0
W
TslAS
-1010+85
°C
A.
A.,
A.
A.
A,.
A"
A,.
110,
1.0.
110.
GND
A.
A,
~
OE
~
CS,
110.
110,
110.
110.
110.
Slorage Temperature Range
--45 10 +125
Tsm
°C
Note: PermanentclaY1C8 damage may occur If absolu1ll maxll11U/n ratings are exceeded.
Functional operation should be reslricted 10 1he conditions as detailed in the operation
sections of this clala sheet Exposure to absolu1ll maximum rating condition. for exlanded periods may atlect device relabiUty.
~'"© 11111ObrFWrrsULIlinetlllldFujIIoull-,1nc.
2-29
MB82B78-15
MB82B78-.20
Fig. 1 - MB82B78 BLOCK DIAGRAM
As
A,
A.
A.
A.
•
Address
Buffer
As
As
•
•
Row
Decoder
•
4-()
Vee
4-()
GND
256x32x8
Memory Cell Array
•
•
A,
•
CS·
As
As
A,.
•
•
•
Address
Buffer
A"
A,.
•
•
110 Gate
&
Column Decoder
•
•
•
OE
Buffer
110 Buffer
CS
WE
CS
CS,
CS_
110,
110.
IlO_
1107
110.
110.
IlO,
110.
CAPACITANCE (T.= 25°C,f= 1MHz)
Parameter
Symbol
Min
Typ
Max
Unit
VO Capacitance (V",-OV)
C",
8
pF
Input Capacitance (V..-OV)
CIM
7
pF
2-30
MB82B78-15
MB82B78-20
PIN DESCRIPTION
Symbol
Pin Name
Po" to A,.
Symbol
Pin Name
Address input.
OE
Output Enable.
Data input/output.
WE
Write Enable.
CS,
Chip Select 1.
Vee;
Power Supply (+5V ±10%)
CSt
Chip Select 2.
GNO
110, to 110.
Ground.
TRUTH TABLE
cs,
cs.
WE
OE
Mode
110 Pin
Power Supply Current
H
X
X
X
Standby
High-Z
Standby
L
L
X
X
Not selected
High-Z
Active
L
H
H
H
Dout disable
High-Z
Active
L
H
H
L
Read
Data out
Active
L
H
L
X
Write
Data in
Active
Lagend: H-High level. L-Low level. X-Don't care
RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Symbol
Min
Typ
Max
Unit
Supply VoRage
Vee;
4.5
5.0
5.5
V
Ambient Temperature
T:
0
70
·C
Parameter
• The operating ambient temperature range is guaranteed with transverse airflow exceeding 2m/sec.
2-31
MB82B78-15
MB82B78-20
DC CHARACTERISTICS
(Recommended operating condHlons otherwise noted.)
Parameter
Taat Conditions
Input laakaga Current
V..-GNO to Vee
Vee-max.
Output laakage Current
~-VIt or CS",V'L or
Symbol
Min
Max
Un"
Iu
-10
10
II-'
ILI/O
-10
10
II-'
Icc
120
rnA
lsa,
15
rnA
....
30
mA
2.2
6.0
V
O.S
V
VI.O-GNO to Vee
WE-V.. or OE-V'H
Operating Supply Current
CS,-V... llO-Open
Cycle-min.
Standby Supply Current
~-Vcc-o.2V. V..,0.2V or
Vee-min. to max.
V,~Vee-o·2V
CS,-V.,
V,.-V,H or V'L
Standby Supply Current
Input High Voltage
V,H
Input low Voltage
V..
-0.5"'
Output High Voltage
I"H-4mA
VOH
2.4
Output low Voltage
lot-SmA
VOL
0.4
V
Peak Power-on Current "2
Vcc-GNO to 4.SV
~-lower of Vee or V.. min.
IPO
50
rnA
Nota:
V
"1 -2.0V min. for pulse width less than Sns.
"2 The CS, input should be connected to Vee to keep the device deselected.
Fig. 2 - AC TEST CONDITIONS
• Output load
..§iL.
0.6Vto2.4V
• Input Pulse levels:
• Input Pulse Rise & Fall Time: 3ns (Transient between O.SV and 2.2V)
Input: V'L-O.SV. V..-2.2V
• Timing Reference levels:
Output: VOL-O.SV. VoH -2.2V
>
>4800
~>
0 ...
c"l
'I
~2550
;>
rlr
"Including Scope and jig CapacHance.
2-32
Paramatars Measured
I
I C
I
I load I I 30pF I excepll,z. tHZ' low. Io..z ana ' I load II I SpF I I,z. tHZ• low. Io..z ana ' -
I
I
I
MB82B78-15
MB82B78-20
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE *1
Symbol
Paramal8r
MB82B78-15
MB82B78-20
Max
Min
Max
Min
Read Cycle Time
tAC
Address Access Time *2
t..
15
20
ns
tACS,
15
20
ns
tACS2
8
10
ns
10
ns
CS, Access Time *3
CS. Access Time
20
Unit
15
ns
8
OE Access Time
Ioe
Output Hold from Address Change
10.
3
3
ns
Output Low-Z from CS, *4
t L2,
3
3
ns
Output Low-Z from CS. *4
t122
2
2
ns
2
Output Low-Z from OE *4
1012
Output High-Z from CS, *4
tHZ1
8
10
ns
Output High-Z from CS. *4
t....
8
10
ns
tOHZ
8
10
ns
Output High-Zfrom OE *4
2
ns
READ CYCLE TIMING DIAGRAM *1
READ CYCLE I: ADDRESS CONTROLLED *2*3
tAC
ADDRESS
Previous Data V:;d
XX4. ----.....:=::..;.='------'p<-~
...._ _ _ __
READ CYCLE II: CS,. CS. CONTROLLED *4
ADDRESS
CS.
•
Nota:
*1
*2
*3
*4
: Don't Care
~: Undefined
WE is high for Read cycle.
Device is oontinuously selected, CS,-<>E-V... cs.-V...
Address valid prior to or ooincident with ~ and CS. transition low and high, respectively.
Transition is measured at the point of ±500mVfrom steady state voltage with specWied Load II in Fig. 2.
2-33
MB82B78-15
MB82B78-20
WRITE CYCLE *1
Parameter
Wr~e
Symbol
Cycle Time
MB82B78-15
Max
Min
MB82B78-20
Max
Min
Unit
!wo
15
20
ns
Address Valid to End of Write
tAW
10
15
ns
CS, to End of Write
tow!
10
15
ns
CS. to End of Write
tOM
6
8
ns
10
ns
tow
7
Data Hold Time
tDH
3
3
ns
Wr~e
!w.
8.
10
ns
tWA'
3
3
ns
~
5
5
ns
Data Setup Time
Wr~e
Pulse Width
Recovery Time *2
CS,.WE
CS.
Address Setup Time
CS,.WE
tAO'
0
0
ns
CS.
t...
2
2
ns
taw
0
Output Low-Z from WE *3
Output High-Z from WE *3
0
ns
10
8
Iw.
ns
WRITE CYCLE TIMING DIAGRAM *1
WRITE CYCLE I: WE CONTROLLED
ADDRESS
Iwc--------...
WWAFfWJti
XWfJF @Wtjlti~mw.&
·!wRl*· ...j
tAW
....- - - - - taw. - - - - -.....
CS.
~@.w~mw#f;4tjlW¥%#WiWtffit~MtiT
b- t,,'_-:--L
----~------~~~~-
tot------!w. - -.....
_ Iw.*3 --t
110
~----------
I-" tow
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _~}(.~~.}Ul
• toH --1 taw*3
Data Valid ~)(.
II]] : Don't Care
Note:
2·34
~: Undefined
*1 II CS,. OE and CS. are in the READ Mode during this period. VO pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
*2 ~ is defined from the end point of WRITE Mode.
*3 Transition is measured at the point of ±500mV from steady state voltage with specHied Load II in Fig. 2.
MB82B78·15
MB82B78·20
WRITE CYCLE II: CS, CONTROlLED
ADDRESS
/:'WMMWWt
t..,::I'
.....--------wc----------tX:ml\(:::.W¥mft
....- - - - - - - - tAW --------~ .IwRl·,·--I
1--
~,
.....-----Icw,
- - - - -.....________
~~~~~+-------------------~
......-----Icw. ----~
~.
- Iw."
--I
t-" tow
--------------..;;;....,X~od.)(I).__("~X
110
•
.t",,-eoj
Data Valid
lew"
](Y
: Don't Care
IKE: Undefined
WRITE CYCLE III: ~. CONTROlLED
~--------Iwc--------~
ADDRESS
CS.
WlP1W4¥W'
t...
-I
Y-Ir--,/r")[-t------------------Icw.~-----:..-:..-:..-:..-:..~nl-------t-" tow ~ t"" -eoj
110
:X Data Valid
•
Note:
](
: Don't Care
'XX
IKE: Undefined
'1 If ~,. OE and ~. are in the READ Mode during this period. 110 pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
'2 t.... is defined from the end point of WRITE Mode.
'3 Transition is measured at the point of ±500mV from steady state voltage with specHied Load II in Fig. 2.
2·35
MB82B78·15
MB82B78-20
PACKAGE DIMENSIONS
28-LEAD PLASTIC DUAL-IN-L1NE PACKAGE
(CASE No.: DIP-28P-M04)
.050(1.27)
MAX
© 1988 FUJITSU LIMITED D28018S-2C
2·36
Dimensions in
inches (millimeters)
MB82B78·15
MB83B78·20
PACKAGE DIMENSIONS (Continued)
Plastic FPT (Suffix: PF)
28-LEAD PLASTIC FLAT PACKAGE
(CASE NO.: FPT-2SP-M02)
.110(2.S0) MAX
(SEATED HEIGHT)
0(0) MIN
iRRRI·","·~,,·,,"gl:'iifll
l
(STAND OFF)
·465±.012
(11.S0±0.30)
cf
lR=;:;=:;:;=n=;:;=;:;=n=;:;=n=r;=;:;=;:;=;4l~
INDEX
.339±.00S
(S.60±0.20)
"""._-+- .031 ±.OOS
(0.SO±0.20)
11·01S±.004
• (0.45±0. 10) 1$1 ¢.005(0.13)~
..".
.006±.002
(0.1 5 ± 0.05)
!- D-;tails~f'A':- part --!
:
.00S(0.20)
:
I
I
I
I
I
I
I
I
1----.650(16.51)
© 1990 FUJITSU LIMITED F28011S-4C
REF--~-(
.024(0.60)
I
.007(0.lS)
I
MAX
I
I
.027(0.6S)
I
IL ____________
MAX
JI
Dimensions in
inches (millimeters)
2-37
MB82B78-15
MB82B78-20
PACKAGE DIMENSIONS (Continued)
PLASTIC FPT SUffix: PJ
lIE
28-LEAD PLASTIC LEADED CHIP CARRIER .144(3.66) MAX
(CASE No.: LCC-2SP-M04) 11---+--.0 -91--'(2-.3-1-'--)-NO-M-
.725±.005
(lS.42±0.13)
.025(0.64) MIN
F~
.340±.005
(S.S4±0.13)
.300(7.S2)
NOM
Li
I
.
.273±.020
(S.93±0.51)
~bD~
-.-: This dimension includes resin protrusion. (Each side: .006 (0.15) MAX)
Dimensions in
2-38
cO
May 1990
Edition 1.0
FUJITSU
DATA SHEET
M882879-151-20
72K-BIT HIGH-SPEED BiGMOS SRAM
8K Words x 9 Bits High-Speed CMOS Static Random
Access Memory
The Fuj~su MB82B79 is a8, 192words x 9 b~ static random access memory fabricated
w~h a CMOS silicon gate process. For lower power dissipation and higher speed, the
peripheral circu~s use BiCMOS technology. To obtain a smaller chip size, cells use
NMOS transistors and resistors. The MB82B79 has 300 mil plastic DIP and SOJ
packages, and a 450 mil SOP package. The memory uses asynchronous circuitry and
requires a +5 V power supply. All pins are TTL compatible.
PLASTIC PACKAGE
FPT-28P-M02
The MB82B79 has low power dissipation, low cost, and high performance, and it is
ideally su~ed for use in microprocessor systems and other applications where fast
access time and ease of use are required.
•
•
8,192 words x 9 b~s
Organization:
Static operation: no clocks or refresh required
•
Access time:
•
1M - tACS1 - 20 ns max.
IACS2 -toe - 10 ns max. (MB82B79-20)
Single +5 V power supply ±1 0"10 tolerance w~h low current drain:
120 mA max. (Active operation)
15 mA max.
(Standby CMOS level)
30 mA max.
(StandbyTTL level)
tAA - tACS1 - 15 ns max.
PLASTIC PACKAGE
LCC-28P-M04
1ACS2 -toe = 8 ns max. (MB82B79·15)
•
BiCMOS peripheral circuits
•
TTL compatible inputs and outputs
•
Three-stale outputs
•
28-pin Plastic Packages:
Skinny DIP (300 mil)
SOJ
(300 mil)
SOP
(450 mil)
PLASTIC PACKAGE
DlP-28P-M04
MB82B79-xxPSK
MB82B79-xxPF
MB82B79-xxPJ
PIN ASSIGNMENT
(TOP VIEW)
Absolute Maximum Ratings (See Note)
Rating
Symbol
Value
Unit
Supply Voltage
Vee
-{l.5 10 +7.0
V
Input Volta&e on any pin w~h
respect to ND
VIN
-3.510 +7.0
V
Output VoHage on any LO pin
w~h respect to GND
VIJO
Output Current
loUT
±20
mA
Po
1.0
W
T BIAS
-10 to +85
·C
Power Dissipation
Temperature Under Bias
-{l.5 10 +7.0
V
-40 to +125
·C
TSTG
Note: Permanent deV1C8 damage may occur HabsolUIB maxmum ratings are exceeded.
Functional operation should be reslridad to 1he conditions as detailed in the operation
sections of this data sheet Exposure to absolu1& maximum rating conditions for ex1&f\ded periods may alfect device reliability.
Slorage Temperature Range
Capvflght
©
A.
Vee
A,
WE
A,
CS2
A2
A,
A,
A,
A.
A,.
A,
OE
A"
A,
A12
CS,
110.
110,
110,
1/0,
110,
110,
1/°2
110,
110.
GND
This device COntaJOI clraJitry to protect the Inputs against
damage due to high static voltages or electric fields. However••
Is advised that normal prec&lilona be taken to avoid application
of any voltage higher than maximum rated vohages to this high
in1::Iedanoe circuit.
1lIII0 by FWITSU LIMITED Md FLjIOlu M_",.1ea, Inc.
2-39
MB82B79-15
MB82B79-20
Fig. 1 - MB82B79 BLOCK DIAGRAM
A.
- - 0 Vee
A,
•
A.
A.
A,
Address
Buffer
A.
•
•
Row
Decoder
•
A,
--oGND
256x32x9
Memory Cell Array
•
•
A7
•
CS'
A,
•
•
•
A.
A,.
Address
Buffer
Al1
•
•
1/0 Gate
&
Column Decoder
A,.
•
CS'
•
•
OE
1/0 Buffer
Buffer
CS
WE
CS
CS,
CS.
110.
1/0,
110.
CAPACITANCE
Parameter
2-40
1107
1/0.
110.
1/0,
110.
110,
(Ta =25°C,f=1MHz)
Symbol
Min
Typ
Max
Un"
1/0 Capacitance (V,/O=OV)
C'IO
8
pF
Input Capacitance (V,N=OV)
C'N
7
pF
M882879-15
M882879-20
PIN DESCRIPTION
Symbol
Pin Name
A. to A,.
110, to 110.
Symbol
Pin Name
Address input.
WE
Write Enable.
Data inpUt/output.
Vee
Power Supply (+5V ±1 0%)
CS,
Chip Select 1.
CS.
Chip Select 2.
OE
Output Enable.
GND
Ground.
TRUTH TABLE
CS,
CS,
WE
OE
Mode
110 Pin
Power Supply Current
H
X
X
X
Standby
High-Z
Standby
l
l
X
X
Not selected
High-Z
Active
l
H
H
H
Dout disable
High-Z
Active
l
H
H
l
Read
Data out
Active
l
H
l
X
Write
Data in
Active
legend: H=High level, l=low level, X=Don't care
RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vee
4.5
5.0
5.5
V
Ambient Temperature
T·
A
0
70
·C
• The operating ambient temperature range is guaranteed with transverse airflow exceed 2m/sec.
2-41
MB82B79-15
MB82B79-20
DC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
Test Conditions
Parameter
Symbol
Min
Max
Unit
IL'
-10
10
pA
-10
10
pA
Input Leakage Current
V,.-GND to Vee
Vee=max.
OutpU1 Leakage Current
VI/O=GND to Vee
CS,=V'H or CS2=V'L or
WE=V,L or OE=V,H
IUfo
Operating Supply Current
CS,=V,L.I/O=Open
Cycle-min.
lee
120
mA
Standby Supply Current
Vee=min. to max.
CS,=Vee--o.2V. V,.S,0.2V or
V,..?Vee--o·2V
IS81
1S
mA
Standby Supply Current
CS,=VIH
V,.=V'H or V'L
ISB2
30
mA
Input High Voltage
V'H
2.2
6.0
V
Input Low Voltage
V~
--o.S"
0.8
V
VOH
2.4
Output High Voltage
IOH=-4mA
Output Low Voltage
IOL=8mA
Peak Power-on Current '2
Vee=GND to 4.SV
CS,=Lower of Vee or V'H min.
Note:
V
VOL
0.4
V
IPO
SO
mA
'1 -2.0V min. for pulse width less than 20ns.
'2 The CS, inpU1 should be connected to Vee to keep the device deselected.
Fig. 2 - AC TEST CONDITIONS
• Output Load
0.6Vto 2.4V
• Input Pulse Levels:
• Input Pulse Rise & Fall Time: 3ns (Transient between 0.8V and 2.2V)
Input: V'L=0.8V. V'H=2.2V
• Timing Reference Levels:
Output: VoL=0.8V. VOH=2.2V
SV
4BOn
<
D~,
c,l
'I
<
2ssn
•
rlr
'Including Scope and jig Capacftance.
2-42
Parameters Measured
I
I C
I
I Load I I 300F I excepttu • tHZ ' tow. tou and 10HZ
I Load" I SoF I lu. 1Hz, low. Iou and 10Hz
I
I
I
MB82B79-15
MB82B79-20
AC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted.)
READ CYCLE '1
MB82B79-15
Parameter
MB82B79·20
Symbol
Unit
Min
Max
Min
Max
Read Cycle Time
lAC
Address Access Time "2
1M
15
20
ns
CS, Access Time "3
tACSt
15
20
ns
CS, Access Time
IACS2
8
10
ns
loe
8
10
ns
OE Access Time
15
20
ns
Output Hold from Address Change
IoH
3
3
ns
Output Low-Z from CS, "4
tu,
3
3
ns
Output Low-Z from CS,"4
t122
2
2
ns
lou
2
2
ns
Output Low-Z from OE "4
tHZ'
8
10
ns
Output High-Z from CS, "4
tHZ2
8
10
ns
Output High-Z from OE "4
tOHZ
8
10
ns
Output High-Z from CS, "4
READ CYCLE TIMING DIAGRAM '1
READ CYCLE I: ADDRESS CONTROLLED "2"3
::RESS ~j:;~;::O=US=D=a=t=a:-vt.:~:-id==xxxq=:::::j:;;j.--:-----------------D~at~a~-v--a11--t~rj~I~I~i!~ i~?~(~(~ :~i~}i~"r':~"-" ~"'-"·'~.·.'.~._-. ~~~~:
READ CYCLE 11: CS" CS, CONTROLLED "4
ADDRESS
.mLn~r.--------.-,t_AC_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-~~=""~"""'.~"""T~:T:" m" "m" im" ",m".,.,..m.....77.
CS,
CS,
mEl :Don't Care
Note:
"1
"2
"3
"4
~: Undefined
WE is high for Read cycle.
Device is continuously selected, CS,=OE=V1L, CS,.V'H'
Address valid prior to or coincident with CS, and CS, trans~ion low and high, respectively.
Trans~ion is measured at the point of ±500mV from steady state voltage with specified Load 11 in Fig. 2.
2-43
MB82B79-15
MB82B79-20
WRITE CYCLE *1
MB82B79·15
Parameter
Symbol
Min
Write Cycle Time
Max
MB82B79·20
Max
Min
UnH
fwc
15
20
ns
Address Valid to End of Write
tAW
10
15
ns
CS, to End of Write
lew.
10
15
ns
CS. to End of Y,frite
lew.
6
8
ns
Data Setup Time
tow
7
10
ns
tDH
3
3
ns
Data Hold Time
tw.
a
10
ns
CS"WE
twR'
3
3
ns
es.
twR2
5
5
ns
es"WE
t..,
0
0
ns
es.
tAS2
2
2
ns
Output Low-Z from WE *3
tow
0
0
Output High-Z from WE *3
twz
Write Pulse Width
Write Recovery Time *2
Address Setup Time
ns
8
10
ns
WRITE CYCLE TIMING DIAGRAM *1
WRITE CYCLE I: WE CONTROLLED
.!~fr::;2::·
ADDRESS'Iftfttf)
J - - - - - - - - - tAW - - - - - - - -.... ~
twR'*''''
J------Icw, ------1
CS,
1/0
EliI :Don't Care
Note:
2-44
~: Undefined
*1 HCS,' OE and CS, are in the READ Mode during this period, 1/0 pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
*2 twR is defined from the end point of WRITE Mode.
*3 Transition is measured at the point of ±500mV from steady state voltage with specnied Load II in Fig. 2.
MB82B79-15
MB82B79-20
WRITE CYCLE II: CS, CONTROLLED
~-------------------~c------------------~
ADDRESS
"'tM'f'f¥t+
X • tII • • i • •mif'• •'
14--------- tAW --------~ I-"_tWR,"...t
_ _ _ _ _ _ __
_ _~tM~'~--~~~~~~I4-------~W'------~i
'f\,\"\j,
~------ ~
------..j
CS,
1/0
•
: Don't Care
~: Undefined
WRITE CYCLE III: CS, CONTROLLED
~-------------------~c-----------------~
t_
CS2
-l
V:r-7--+-1--_-_-_-_-_-_-_-_-_~_'':::::_-_-_-_~-.l.1
/ ./f
"f-------
~tow
110
I4-tDH~ low"
e)[ Data Valid
Iilii :Don't Care
Note:
.AAJ'o,
~: Undefined
'I H CS" OE and CS, are in the READ Mode during this period, 110 pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
'2 ~R is defined from the end point of WRITE Mode.
'3 Transition is measured at the point of ±500mV from steady state voltage with specified Load II in Fig. 2.
2-45
M882879-15
M882879-20
PACKAGE DIMENSIONS
PLASTIC DIP (Suffix: P-SK)
28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-28P-M04)
rr:t
JI
I-:J± .010 .300(7.62)
(6.60±0.25) TYP
---1
r--'::='4
~
15'MAX
____: _
.010±.OO2
(0.25±0.05)
.050(1.27)
MAX
Dimensions in
© 1988 FUJITSU LIMITED D28018S-2C
2-46
inches (millimeters)
MB82B79-15
MB82B79-20
PACKAGE DIMENSIONS (Continued)
PLASTIC FPT (Suffix: PF)
28-LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT -28P-M02)
11012.80) MAX
1----fI"'S"'EA:::T'=:ED:::--::H=EIC:G:':::HT)
0(0) MIN
IRRR· "".g:g"",,gl~Ufll
ISTANO OFF)
1
·465±.012
(11.80±0.30)
.402± .012
110.20±0.30)
.339±.008
18.60±O.20)
~:;::r=n=;:;=;=;=;:;=n=;n=n=r;=;ffl~
.031 ±.008
10.80±0,20)
TYP
''A''
.006±.002
10.15±0.05)
:- -D-;~ils ~f'i;7 part I
I
I
I
I
o
.00410.10)
I
.00810.20)
~
02410.60)
.650116,51)
REF--~-1
.00710.18)
MAX
, ,02710.68)
MAX
___________
JI
Dimensions In
© 1988 FUJITSU LIMITED F28011S-3C
inches (millimeters)
2-47
MB82B79-15
MB82B79-20
PACKAGE DIMENSIONS (Continued)
PLASTIC FPT (Suffix: PJ)
28-LEAD PLASTIC LEADED CHIP CARRIER
(Case No. : LCC-28P-M04)
144 (3 66) MAX
"
.091 (2.31) NOM
.725±.005
(18.42±0.13)
.025 (0.64) MIN
Fi"I _ _
I
IJ
o
.050±.005
(1.27±0.13)
.273± .020
(6.93±0.51)
bd)~
~
i-De~i;;;:;:':·-:-p~t--l
II
-.650(16.51) REF
r032(0'81)
MAX
I
~.
~~(2.60)NOM
~.
=1
.004(0.10)
U,~
I"
A"
II
I
I
I
I
I
I'
I
I
I
I
I
.017±.004
I
I
(0.43±0.10)
I
L _________ ...J
II
If : This dimension includes resin protrusion. (Each side: .006 (0.15) MAX)
© 19S9 FUIITSU LIMITED C2SD54S-1 C
2-48
Dimensions in
inches (millimeters)
00
September 1990
Edition 1.0
FUJITSU
DATA SHEET
M882881-151-20
256K-BIT HIGH-SPEED BiGMOS SRAM
256K Words x 1 Bit BICMOS High-Speed Static
Random Access Memory
The Fujitsu MB82B81 is a static random access memory organized as 262.144 words
x 1 bit and fabricated with a CMOS silicon gate process. BiCMOS technology is used in
the peripheral circuits to provide lower power dissipation and higher speed.
The MB82B81 is housed in a300 mil plastic DIPorsmall outlineJ-lead (SOJ) package.
The memory uses asynchronous circuitry and requires a +5 V power supply. All pins
are m compatible.
The MB82B81 has low power dissipation. low cost. and high performance. and it is
ideally suited for use in microprocessor systems and other applications where fast
access time and ease of use are required.
Plastic Package
(DIP-28P-M04)
•
•
262.144 words x 1 bit
Organization:
Static operation: no clocks or refresh required
•
Fast access time:
•
Single +5 V power supply ±1 00/0 tolerance with low current drain:
120 mA max
(Active operation)
15 mA max.
(Standby Operation)
25 mA max.
(Standby Operation)
w. -tACS -15 ns max. (MB82B81-15)
w. - tACS - 20 ns max. (MB82B81-20)
•
BiCMOS peripheral circuits
Plastic Package
•
TTL compatible inputs and outputs
(LCC-28P-M04)
•
•
Three-state outputs
Standard 24-pin Plastic Packages:
Skinny DIP (300 mil)
MB82B81-xxPSK
SOJ
(300 mil)
MB82B81-xxPJ
•
Pin compatible with MB81C81A
Pin Assignment
(TOP VIEW)
Absolute Maximum Ratings (See Note)
Rating
Symbol
Value
Unit
Supply Voltage
Vee
-0.5 to +7
V
Input Volta&e on any pin with
respect to NO
V..
-0.5 to +7
V
Output vo~a2e on any pin with
respect to G 0
At
v..
A,
A,
A.
A,
II,;
A"
A,
A"
A"
A"
VIIO
-0.5 to +7
V
A"
A"
A"
Output Current
lOUT
±20
mA
Power Dissipation
PD
1.0
W
WE
0",
GND
Ci
Temperature Under Bias
TBIAS
-10 to +85
°C
Storage Temperature Range
TSTG
-45 to +125
°C
Nota: Permanent device damage may ocoor Habsolute maximum I"Blings are exceeded.
Functional operation should be resbicled to the conditions as detailed in the operation
sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliabUity.
A"
Thla device contains clrcuhry to protect
til,
inputs against
:=~~;~:'~~===~~f~:Jd=:i~
d any YOItage higher thM maximum rated voltages to this high
Irrpedanc:a circuit
COpyrIght © 1990 by FUJITSU LIMITED IIId F"1IIu M_"",IcI.Inc.
2-49
MB82B81-15
MB82B81-20
Fig. 1 - MB82B81 BLOCK DIAGRAM
Ao
vee
Al
•
A2
A3
A4
~~======I
ROW
SELECT
•
As
GND
CELL
ARRAY
256 ROWS
1024 COLUMNS
•
As
A7
•
DIN
•
•
Dour
COLUMN 1/0 CIRCUITS
INPUT
DATA
CONT.
WE
COLUMN SELECT
As
A9
Al0 All A12
A13 A14 A15 A16 A17
POWER
DOWN
CIRCUIT
CAPACITANCE (TA=25°C,f=1MHz)
Parameter
Symbol
Min
Typ
Max
Unh
110 Capacitance (V1IO-0V)
Coo
8
pF
Input Capacitance (Vc;-OV)
~
8
pF
Input Capacitance (V.. -OV)
C'N
6
pF
2-50
MB82B81-15
MB82B81-20
PIN DESCRIPTION
Pin Name
Symbol
Ao to A17
Address input.
WE
Write Enable.
0,.
Dete input.
Vee
Po_ Supply (+5V ±10%).
DOUT
DetaOulput.
GND
Ground.
as
Chip Select.
Symbol
Pin Name
TRUTH TABLE
Ci
WE
Mode
Output
Pow., Supply Current
H
X
Not Selected
High-Z
Standby
L
L
Write
High-Z
Active
L
H
Read
~
Active
Legend: H = High level, L = Low lewl, X = Don't care
RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
p.,.Supply Voltage
Ambient Temperature
Symbol
Min
Typ
Mall
Unit
Vee
4.5
5.0
5.5
V
T. *
0
70
"C
'; The opelllling ambientl8mperalUre range is gueranl8ed with tranSWrB9 airflow exceeding 2m/sec.
2-51
MB82B81-15
MB82B81-20
DC CHARACTERISTICS
(Recommended operating conditions othelWlse noted.)
T.at Condldona
Par.......
Symbol
Min
Max
UnIt
lu
-10
10
IIA
-10
10
IIA
Input Leakage Current
V.. - GND to V""
V",,=max.
Output Leakage Current
e"§ = V.. or~ = VL
IUIO
Operating Supply Current
cs
= V.. Dour = Open
Cycle = min.
I""
120
rnA
Stenclly Supply Current
V"" = min. to max.
CS. V"" -O.2V. V.. s 0.2V
or V,. ~ Vee -O.2V
I..,
15
rnA
StencIIy Supply Current
CS=V"
Vee = min. \0 max.
1-
25
rnA
Vour = GND to V""
Input High Voltage
V..
2.2
6.0
V
Input Low Voltage
VL
-0.5"'
O.B
V
2.4
Output High Voltage
1000=-4mA
VOlt
Output Low Voltage
IOL=8mA
VOL
0.4
V
Peak Power-on Current".
V"" = GND to 4.5V
CS = Lower of V"" or V," min.
IPO
50
mA
V
Note: "' -2.0V min. for pulse widIh less then 8ns.
"2 The OS Input should be connected 10 Vee to keep the device deselected.
Fig. 2 - AC TEST CONDITIONS
• Input Pulse lewis:
• Input Pulse Rise" FBI Tme:
• liming ReleIllIlC8 Levels:
• Output Loed
Dour
~j
0.6Vto 2.4V
1ns (Transient between O.BV and 2.2V)
Input V,. = O.BV. V" = 2.2V
Output: VOL = O.BV. VON = 2.2V
2550
.... ~
·lndudlng Soapoond Jig ~
2·52
C.
Parametars m&aSUllId
Loedl
30pF
except Itz. 1Hz. low and Iwz
Loedll
5pF
Itz. 1Hz. low and Iwz
MB82B81-15
MB82B81-20
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE
Para_
Symbol
Read Cycle Time
Address Aa:ess Time
"'t..."
CS Aa:ess Time
t..cs
Output Hold from Address Change
Output lDw-Z 110m CS
Output High-Z from CS
Power Up from CS
Ipu
MB82881·15
Min
Min
15
Unit
ns
20
20
ns
15
20
ns
to..
0
Iu
3
3
"'"
Ma.
15
0
Ittz
Power Down from CS
M882881-20
M811
ns
ns
8
8
ns
20
ns
ns
0
0
15
READ CYCLE TIMING DIAGRAM"'
....----""' .. _----...
READ CYCLE*3
ADDRESS
...
'''''I1OUS
o"..",oX
~!IO/,X~~__
41r----DA-T-A-V-AL-ID-to..--:
...
...
READ CYCLE: CS CONTROLLED'"
ADDRESS
HIGH-Z
HIGH-Z
SUPPLY
CURRENT
Icc-----f:.':.~-----------------:1_;;;:
50%~
Icc
~
t.fBl
1m
Undellned
Doni. Care
WE is high for Reed c:rcle.
"2 All Read c:ycIe timing are I81an!nced from the last valid address to the first trensitioning address.
"3 Device Is oontinuously selected, CS = V,L.
"4 Address valid prior to or coincident with CS transition low.
"5 Transition is measured at the point of :I:5OOmV from steady state voltage with specified Load II in Fig. 2.
Note: "1
2-53
MB82B81-15
MB82B81-20
WRITE CYCLE
......m..er
11882881-15
Symbol
Min
11882881-20
IIIn
118.
lin
UnI'
Wri1e Cyde rune
!we
15
20
Address Valid m End 01 WrilB
It.w
11
15
n8
CS to End 01 WrilB
lew
11
15
ns
Data Setup Time
ns
low
4
8
ns
Data Hold Time
!ott
0
0
na
Write Pulse Width
tw.
tw.
11
15
na
0,
0
n8
WrilB Recovery Time
Address Setup Time
It.s
0
0
ns
Output Low-Z from WE
low
0
0
ns
Output High-Z from WE
Iwz
6
10
ns
WRITE CYCLE TIMING DIAGRAM*'
WRITE CYCLE I: WE CONTROLLED
t----------- twc··----------.....
ADDRESS ~',.':'
~------ Iew------~
It.w--------~~
0,.
Dour
1&81
Undellned
No'.: '1 CS or WE must be high during address lransitions.
'2 II CS goes high simultaneously with WE high. the output remains in high impedence stala.
'3 All Read cycle timings 1118 referenced from the last valid address to firstlransilions address.
'4 Transition measured at ±5OOmV from staeely staIB voltage wilh specified load II in 1'"1g. 2.
2-54
(ttk'
Don" Care
MB82B81·15
MB82B81·20
WRITE CYCLE TIMING DIAGRAM (Continued)·'·...
WRITE CYCLE TI: CS CONTROLLED*1*2
ADDRESS
14-------- t..w ---------I~
- _......._-oL.
~----Icw -----.,~
.004(0.10)
:lie : This dimension includes resin protrusion. (Each side: .006(0.15) MAX)
© 1990 FUJITSU LIMITED C24052S-1 C-2
2-56
.11 ..017±.004
L _ _ _ _ _(0.43±0.10)
_____ _
Dimensions in
inches (millimeters)
cP
July 1990
Edition 1.0
FUJITSU
DATA SHEET
MB82B84-151-20
GMOS 256K-BIT HIGH-SPEED BiGMOS SRAM
64K Words x 4 Bits BiCMOS High-Speed Static Random
Access Memory with Automatic Power Down
The Fujitsu MB82B84 is a 65,536 words x 4 bits static random access memory
fabricated with a CMOS silicon gate process. For lower power dissipation and higher
speed, peripheral circuits use BiCMOS technology. To obtain a smaller chip size, cells
use NMOS transistors and resistors. The MB82B84 is housed in 300 mil plastic DIP
and small outline J-Iead (SOJ) packages. The memory uses asynchronous circuitry
and requires a +5 V power supply. All pins are TTL compatible.
The MB82B84 has low power dissipation, low cost, and high performance, and it is
ideally suited for use in microprocessor systems and other applications where fast
access time and ease of use are required.
•
•
•
•
•
•
•
•
•
•
Organization:
Access time:
PLASTIC PACKAGE
DIP·24P·M03
65,536 words x 4 bits
1M a lACS - 15 ns max. (MB82B84-15)
tM - tACS - 20 ns max. (MB82B84-20)
BiCMOS peripheral circuits
TTL compatible inputs and outputs
Static operation: no clock required
Three-state outputs
Common data inputs and outputs
Single +5 V power supply ±1 0% tolerance with low current drain:
120 mA max.
(Active operation)
15 mA max.
(Standby, CMOS level)
25 mA max.
(Standby, TTL level)
Standard 24-pin Plastic Package:
Skinny DIP
(300 mil)
MB82B84-xxPSK
SOJ
MB82B84-xxPJ
Pin compatible with MB81 C84A
PLASTIC PACKAGE
LCC·24P·M02
PIN ASSIGNMENT
(TOP VIEW)
A.
A.
A.
A.
Absolute Maximum Ratings (See Note)
A.
Symbol
Value
Unit
A,
Supply Voltage
Vee
~.5to+7.0
V
A.
Input Volt~e on any pin with
respect to NO
VN
-3.5 to +7.0
V
Output Volt~e on any 110 pin with
respect to G 0
V'IO
~.5to+7.0
V
Output Current
lOUT
±20
mA
Power Dissipation
Po
1.0
W
Rating
Temperature Under Bias
TslAS
-10 to +85
°C
Storage Temperature Range
TSTG
-40 to +125
°C
Note: Pennanent device damage may occur if absolute maximum ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in the operation
sections of this deta sheet Exposure to absolute maximum rating conditions lor extended periods may affect device reliability.
A.
A,.
A"
CS
GND
Vee
A,
Ao
A,.
A,.
A14
A..
1/0.
1/0.
VO.
1/0,
WE
(DIP & SOJ Package)
Thll_ contains clrQJItry to prot8d"'.lnputs against
. - . - duo to high stallcvoltagos o'.I....1c fields. However. h
II adviIed that normal precaajions be taken to avoid appUcation
01 any WJItago higher th.. maximum _
vohagos 10 this high
IqIocfanoo clraJlt.
Ccipjright © 1lIII0 by FUJITSU LlMIlED and F"1IIu M_1ca, Inc.
2-57
M882884-15
M882884-20
FIg. 1 - MB82B84 BLOCK DIAGRAM
......
A,
.
-
-Vee
-GND
~
•
~
~
~
Row
Select
256 x 256 x 4
Memory Cell Array
•
~
~
•
A,
:>
f--
VO,
>
1/0.
~
110.
>
1/0.
~
•
•
•
0-
I
Column Select
W
=:[)-
~
W
iI'I
A.
~
v..
iI'I
A,.
A.
~
•
Column
&
110 Circuits
1/0
Buffer
t
•
•
i
f--
A'2
A ..
A"
A..
v..
A..
Power Down
Circuit
CAPACITANCE (T.=25°C,f= 1MHz)
Parameter
Symbol
Min
Typ
Max
Unit
1/0 Capacitance (V,/O&OV)
Coo
8
pF
Input Capacitance (VICS.OV)
CICS
8
pF
Input Capacitance (V,,=OV)
C'N
6
pF
2-58
MB82B84-15
MB82B84-20
PIN DESCRIPTION
Symbol
Pin name
A" to A,s
1I0,to 110.
Address input
WE
Wrtte Enable
Data input/output
Vee
Power Supply (+5V ±1 0%)
Chip Select 1
CS
Pin name
Symbol
GND
Ground
TRUTH TABLE
CS
WE
Mode
110 pin
Power Supply Current
H
X
Standby
High-Z
Standby
L
L
Write
D'N
Active
L
H
Read
Dour
Active
Legend: H=High level, L=Low level, X=Don't care
RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Symbol
Min
Typ
Max
Unit
Supply Vokage
Vee
4.5
5.0
5.5
V
Ambient Temperature
T."
0
70
·C
Parameter
" The operating ambient temperature range is guaranteed wtth transverse airflow exceeding 2m/sec.
2-59
MB82B84-15
MB82B84-20
DC CHARACTERISTICS
(Recommended operating !:ondltlons otherwise noted.)
Parameter
Test CondHlons
Symbol
Min
Max
Unit
Input leakage Current
V,N=GND to Vee
Vee=max.
lu
-10
10
I1A
Output leakage Current
V'K).GND to Vee
CS=V'H or WE=V'L
IUK)
-10
10
I1A
Operating Supply Current
CS=V,L.I/O.Open
Cycle=min.
Icc
120
rnA
ISB1
15
rnA
Is..
25
rnA
Vee=min. to max.
CS=Vee-0.2V. V'N~0.2V or
Standby Supply Current
V'N"?Vee-O.2V
CS=V'H
Vee=min. to max.
Standby Supply Current
Input High Voltage
V'H
2.2
6.0
V
Input low Voltage
VL
-0.5"
O.B
V
IoH=-4mA
VOH
2.4
Output low Voltage
IOL=BmA
VOL
0.4
V
Peak Power·on Current '.
Vcc=GND to 4.SV
CS=Lower of Vee or V'H min.
IPO
50
rnA
Output High Voltage
Note:
V
'1 -2.0V min. for pulse width less than Bns.
'2 The CS input should be connected to Vee to keep the device deselected.
Fig. 2 - AC TEST CONDITIONS
0.6Vto 2.4V
• Input Pulse levels:
• Input Pulse Rise & Fall Time: 1ns (Transient between O.BV and 2.2V)
SV
• Timing Reference levels:
4BOO
DWI
Input: V'L=O.BV. V'H=2.2V
Output: VOL=O.BV. VOH=2.2V
• Output Load
o----------r----.,
2550
Parameters measured
exce t t L2• t HZ• low and Iwz
t L2• tHZ• tow and twz
'Including Scope and jig capacitance
2-60
MB82B84-15
MB82B84-20
AC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted.)
READ CYCLE
MB82B84-15
Parameter
Symbol
Read Cycle Time
tAC
Max
Min
15
MB82B84-20
Unit
Max
Min
20
ns
Address Access Time
tM
15
20
ns
CS Access Time
t.cs
15
20
ns
Output Hold from Address Change
to..
0
0
OutpUI Low-Z from CS
ILZ
3
3
OUlput High-Z from CS
tHZ
Power Up from CS
Ipu
Power Down from CS
tpD
ns
ns
8
8
0
ns
ns
0
20
15
ns
READ CYCLE TIMING DIAGRAM *1
READ CYCLE 1'3
ADDRESS
DOUT
READ CYCLE:
ADDRESS
CS CONTROLLED '4
~"'.:~~~~~~~~~~~~~~~~~~_tRC_-_-_-_-_-_-_-_-_-_-_-_-_-_-_----'---t~\\......:.\\\..\\r
CS
Dour
SUPPLY
CURRENT
Icc ______
t=_t~_~
HIGH-Z
DATA VALID
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _t_PD_=L5_0';,'O____ _
~
Undefined : ~
Note:
'I
'2
'3
'4
'5
~
Icc
Don't Care:
"
1]11
WE is high for Read cycle.
All Read cycle timings are referenced from the last valid address to the first transitioning address.
Device is continuously selected. CS=V'L.
Address valid prior to or coincident with CS transition low.
Transition is measured at the point of ±500mV from steady slate vo~age.
2-61
MB82B84-15
MB82B84-20
WRITE CYCLE
MB82B84-1S
Parameter
Symbol
MB82B84-20
Max
Min
Max
Min
Unit
Write Cycle Time
twe
15
20
ns
Address Valid to End of Write
t. w
11
15
ns
CS to End of Wr~e
lew
11
15
ns
Data Setup Time
low
4
8
ns
Data Hold Time
tOH
0
0
ns
Wr~e
Iwp
11
15
ns
0
ns
ns
Pulse Width
tw.
0
Address Setup Time
tAS
0
0
Output Low-Z from WE
tow
0
0
Output High-Z from WE
twz
Wrtte Recovery Time
ns
6
10
ns
WRITE CYCLE TIMING DIAGRAM *1
WRITE CYCLE I: WE CONTROLLED
~--------------------tWC·3--------------------~
ADDRESS
CS
,.,."
,.,.,.,.,.".,.,.,.,
;::;;:~: :::::::::::::::::~~
,.,.".,.,.,.,.,.,.".,.,.,.,.
;:;::::;;:::::::::;::
::~:::::::
" , . I - - - - - - I e w ------eo! :.".".,:w.".".,".,'.".".,--I".",.".,
..".,.".".".".".,.,.,.,.,.,.,.,.".,""""""""".":""".'. '.'.;.'.'..". '..".'',.'.,',',',',',',',.,',"'.,.....
".,','.,','.,'".,'".,','.,'J.,.",
..
~----------------t..w----------------~
f----- tAS,
~------- twp --------.....
-----t
-----+----~~~~
D,N
XXXXXXXXXXXXXXXXX
r--IXXXXXXX~
I~-------
tow -
t-- tOH ...
DATA VALID
,XXXXXXX
~1ow··1
HIGH-Z
DOUT
Undefined:
Note:
2-62
~
~
Don't Care: •
'1 CS or WE must be high during address transttions.
'2 If CS goes high simultaneously with WE high, the output remains in high impedance state.
'3 All Read cycle timings are referenced from the last valid address to first transitioning address.
'4 Trans~ion measured at ±500mV from steady state voltage w~h specffied load in Fig. 2.
'5 If CS is in the Read Mode during this period, VO pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
MB82B84-15
MB82B84-20
WRITE CYCLE II: CS CONTROLLED·1·2
i~i"'-tA"-1-'~~~~~-t_Aw~-t_~_3~~~-_~~--=:-1:-'~-tWR-J-tr-"~
ADDRESS =t/=)=;
....
l'~
__
____________________~1
~
xxxxxxxxxxxxxxx
~~
Ir-·_ _ _
D'N
t_" -; :;,-~-c:--~-:-:-,-=----li_~_t_DH_-___,j·If'f:70'O'O'~
Undefined : ~
Note:
~XXXXXX
DATA VALID
Don't Care: •
·1 CS or WE must be high during address transitions.
·2 If CS goes high simuttaneously with WE high, the output remains in high impedance state.
·3 All Read cycle timings are referenced from the last valid address to first transitioning address .
• 4 Trans~ion measured at ±500mV from steady state vottage with specified load in Fig. 2.
·5 If CS is in the Read Mode during this period, 110 pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
2-63
M882884-15
M882884-20
PACKAGE DIMENSIONS
24·LEAD PLASTIC DUAL·IN LINE PACKAGE
(CASE No.: DIP·24P·M03)
.30017.621
TYP
MAX
-J I..
.10012.S41 1
TYP
01S±.003
10.46±0.OSI
Dimensions in
inches (millimeters)
© 1988 FUJITSU LIMITED D24017S·3C
24·LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCC-24P·M02)
ED>ll
1
,.-
I
o
~~~~IND~E~XnT~~~~~.~
.340±.oos
IS.64±0.131
.273±.020
16.93±0.S11
.300(7.621
r
.09112.311
NOM
.SS0I13.97IREF
b
,..-_ _ _ _ _ _ _ _ _ _ _- ,
1=rR""l=r-.=r.....i.-.Io...................or-o...,..............-
0.
~etaols
.004(0.10)
2-64
.02S(0.641
MIN
S
.14413.661
MAX
032(0.S1IMAX
of 'A' part
.10212.601
NOM
* : This.dimension includes resin protrusion. (Each side: .006(O.151MAX.)
e1l189 FUJITSU LIMITED C240528-1C
-==D~
r-
.OSO±.OOS
11.27±0.131
.
I
~
I
.
.017±.004
(0.43±O.10)
?~~~~Si~~~'j~eters)
cO
September 1990
Edition 1.0
FUJITSU
DATA SHEET
MB82B85-151-20
256K-BIT HIGH-SPEED BiCMOS SRAM
64K Words x 4 Bits BICMOS High-Speed Static
Random Access Memory With Automatic Power Down
The Fujitsu MB82B85 is a static random access memory organized as 65,536 words
by 4 bits and fabricated with a CMOS silicon gate process. BiCMOStechnology is used
in the peripheral circuits to provide lower power dissipation and higher speed. To obtain
a smaller chip size, the cells use NMOS transistors and resistors.
The MB82B85 is housed in 300 mil plastic DIP and small outline J-lead (50.1)
packages. The memory uses asynchronous circu~ry and requires +5 V power supply.
All pins are TTl compatible
The MB82B85 has low power dissipation, low cost, and high performance, and ~ is
ideally su~ed for use in microprocessor systems and other applications where fast
access time and ease of use are required.
•
Organization:
65,536 words x 4 bits
•
Access time:
lM - lACS - 15 ns max. (MB82B85-15)
•
BiCMOS peripheral circuits
•
TTL compatible inputs and outputs
Plastic Package
(DIP-28P-M04)
tM - lACS - 20 ns max. (MB82B85-20)
•
Static operation: no clock required
•
Three-state outputs
•
•
Common data inputs and outputs
Single +5 V power supply ±1 0% tolerance w~h low current drain:
120 mA max.
(Active operation)
15 mA max.
CMOS Standby)
25 mA max.
(TTL Standby)
•
Plaatlc Package
(LCC-28P-M04)
Pin Assignment
(TOP VIEW)
Standard 28-pin Plastic Packages:
Skinny DIP
MB82B85-xxPSK
50.1
MB82B85-xxPJ
NC
Rating
A,.
A7
A.
As
Absolute Maximum Ratings (See Note)
Symbol
Value
Unit
Supply Voltage
Vee
-0.5 to +7
V
Input VoI~e on any pin w~h
respect to NO
VN
-3.5 to +7
V
Output Vo~e on any VO pin w~h
respect to G 0
Vvo
-0.5 to +7
V
Output Current
lOUT
±20
mA
Power Dissipation
PD
1.0
W
Temperature Under Bias
TBIAS
-10 to +85
°C
Storage Temperature Range
TSTG
-<15 to +125
°C
Vee
A..
A.
As
A,.
A.
At
A,
~
CS
OE
GND
A,.
A,.
A"
A,.
NC
NC
VO,
VOl
VOl
.!!2.
WE
(DIP & SOJ Package)
Note: Permanent device damage may occur if absolUIII maximum ratings ara exceedad.
Functional operation should be res1ricllld to Ihe conditions as detailed in Ihe aperaIion
sections of this data sheet. Exposure to absolu18 maximum rating conditions for ex1Bndad periods may affect davice relabUity.
2-65
MB82B85-15
MB82B85-20
Fig. 1 - MB82B85 BLOCK DIAGRAM
I--
>
-Vee
_
~
GND
•
.. >
~-
..
..
Row
Select
>
256x256x4
Memory Cell Array
•
~-
•
~
~
~
• •
I
•
~
110,
~
110.
>
110.
~
110.
>
•
•
•
Column
&
110 Circu~s
va
Column Select
Buffer
D-
~
lI\
A.
" "
O-rL~
A,.
A.
~
A,.
Al1
ill
"~r "
A,.
A..
A.,
Power Down
Circu~
CAPACITANCE (To= 25
Parameter
ill
~
0
C, f = 1MHz)
Symbol
Min
Typ
Max
Unh
110 Capac~al1C8 (V,.,-OV)
Coo
8
pF
Input Capacitance (Vcs-OV)
Cci
8
pF
Input Capacitance (V..-OV)
CIM
6
pF
2-66
MB82B85-15
MB82B85-20
PIN DESCRIPTION
Symbol
Pin name
Ao to A..
va, to va.
Symbol
Plnname
Address input
WE
Wr~eEnable
Data inpulloutput
Va;
Power Supply (+5V ±100/0)
"OS"
Chip Select
"OE"
Output Enable
TRUTH TABLE
WE
«
«
GND
Ground
Mode
110 pin
Power Supply Current
H
X
X
Standby
High-Z
Standby
l
l
X
Wr~e
D'N
Active
l
H
H
Output Desable
High-Z
Active
l
H
l
Read
DOUT
Active
Legend: H-High level. l-low level. X-Don' care
RECOMMENDED OPERATING CONDITIONS
Referenced to GND)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Va;
4.5
5.0
5.5
V
Ambient Temperature
T:
0
70
'c
Parameter
• The operating ambient temperature range is guaranteed w~h transverse airflow exceeding 2m/sec.
2·67
MBS2BS5-15
MBS2B85-20
DC CHARACTERISTICS
(Recommended operating conditIOns otherwise noted.)
Parameter
Test Conditions
Symbol
Min
Max
Unit
Input Leakage Current
V..-GNOtoV""
V"".max.
lu
-10
10
!IA
Output Leakage Current
V..,-GNO to Vcc
~V'H or 'WE.V'L
Iwo
-10
10
!IA
Icc
120
rnA
I..,
15
rnA
Ie..
25
rnA
-cs;.V,,, I/O.Opan
Cycle.min.
~cc.mln. to max.
CS'-Vcc-o.2V. V":;'0.2Vor
Operating Supply Current
Standby Supply Current
V,,,~Vcc-o·2V
"CS'.V'H
Vcc.min. to max.
Standby Supply Current
Input High Voltage
V..
2.2
6.0
V
O.S
V
VL
-0.5"
Output High Voltage
IoH-4mA
VOH
2.4
Output Low Voltage
IoL·SmA
VOL
0.4
V
Peak Power-on Current '.
V"".GNO to 4.5V
CS'.Lower of VO(; or V'H min.
I,..,
50
rnA
Input Low Voltage
Nota:
V
'1 -2.0V min. tor pulSe width less than Sns.
'2 The "CS'input should be connected to VO(; to keep the device deselected.
Fig. 2 - AC TEST CONDITIONS
5V
• Input Pulse Levels:
0.6V to 2.4V
• Input PulSe Rise & Fall Time: 1ns (Transient between O.SV and 2.2V)
• Timing Reference Levels:
Input: V'L-O.SV. V.,,-2.2V
Output: VOL-O.SV. vOH-2.2V
• Output Load
Og
o---------r---~
'Including Scope and jig capacitance
2-68
MB82B85-15
MB82B85-20
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE
Parameter
Read Cycle Time
Symbol
lAC
MB82B85-15
MIn
Max
15
MB82B85·20
Unit
Max
Min
20
ns
Address Access Time
1M
15
20
ns
"'CS" Access Time
"OE" Access Time
lACS
15
20
ns
10.
a
10
ns
Output Hold from Address Change
0
ns
ns
10.
0
Output Low-Z from "'CS"
IcLZ
3
3
Outpul Low-Z from""OE
IoLZ
3
3
Outpul High-Z from "'CS"
tOHZ
Output High-Z from oe-
DHZ
Power Up fromCS"
!"u
Power Down from "'CS"
lPO
ns
a
a
0
a
ns
8
ns
0
ns
15
20
ns
READ CYCLE TIMING DIAGRAM *1
READ CYCLE 1"3
...._ _ _ _ _ _ _ "",'2 _ _ _ _ _ _ _..
READ CYCLE: ""CS" CONTROLLED "4
ADDRESS
~~.:,:,:,:,:,:,:,:,:,:,:,:,:,:,:,:,:,:,::_IAC";""-_-_-_-_-_-_-_-_-_-_-_-_-_-----...,....
~gNW$8R#A*j.I-
CS
Dour
HIGH-Z
DATA VALID
~~~~~~T 6 ............:-·;;}----------:-Icc-----t,.,,-=tso% ---Undefined : ~
Note:
"I
"2
"3
"4
"5
Don't Care:
II
WE is high for Reed cycle.
All Reed cycle timings are referenced from the lasl valid address to the first transitioning address.
Device is continuously selected, CS..o~.
Address valid prior to or coincident with CS Iransition low.
Transition is measured at Ihe point 01 ±500mV from steady slale voltage with specified Load II in Fig. 2.
2-69
MB82B85-15
MB82B85-20
WRITE CYCLE
Parameter
MB82B85-15
Symbol
Min
Max
MB82B85·20
Min
Max
Unit
WrRe Cycle Time
Iwc
15
20
Address Valid 10 End of Wme
tAW
11
15
ns
Wto End of Write
few
11
15
ns
4
8
ns
ns
t. . ,
Data Setup Time
ns
Data Hold Time
tDH
0
0
WrRe Pulse Width
11
15
ns
Write Recovery Time
!wP
!w.
0
0
ns
Address Setup Time
tAS
0
0
ns
0
0
Output low-Z from WE
Iwu
Output High-Z from WE
!wHZ
ns
10
6
ns
WRITE CYCLE TIMING DIAGRAM ·1
WRITE CYCLE I: WE CONTROLLED
!we.'
1 - - - - - - few ----~ I-!w.-r
---------1
....- - - - - - - - tAW
r-- tAS
i----Iw,
---t
-----+--~---~~~~I
-----t
1;-----------
!--t....,- I--t
DH . .
XXXXXXXXXXXXXXXXX IXXXXXXXJCI
D'N
Dour
Undefined : ~
Note:
2-70
'1
'2
'3
'4
'5
Don'tCare:
II
CS or WE must be high during address transitions.
If CS goes high simultaneously with WE high, the output remains in high impedance state.
All Read cycle timings are referenced from the last valid address to first transitioning address.
Transition measured at ±500mV from steady state voltage with specified load II in Fig. 2.
IICS, OE are in the Read Mode during this period, I/O pins are in the output state so that the input signals of
opposite phase to the outputs must not be applied.
MB82B85-15
MB82B85-20
WRITE CYCLE II: "OS" CONTROLLEO*1*2
~------------------_t~·3--------------------~
~---------------
tAW
------------------1
- t.a1t------ tcw - - - - - - I I- ' - ------------'11
1)---------------
'-
0,.
Undefined : ~
Note:
i'-"'~
DATA VALID
*1
*2
*3
*4
*S
Oon'tCare:
mill
CS or WE must be high during address transitions.
H CS goes high simuHaneously with WE high, the output remains in high impedance state.
All Read cycle timings are referenced from the last valid address to first transitioning address.
Transition measured at ±50OmV from steady state voHage with specHied load II in Fig. 2.
HCS, OE are in the Read Mode during this period, ItO pins are in the output state so that the input signals of
opposite phase to the outputs must not be applied.
2·71
MB82B85-15
MB82B85-20
PACKAGE DIMENSIONS
28-LEAD PLASTIC DUAL·IN·LlNE PACKAGE
(CASE No.: DlP·28p·M04)
INDEX-1
INDEX-2 ~~=;=;=r=;=;:::r=n==;=;:::r=;=r::;=;=;=;:=;==r=r=;=;n=:;:iI.
.050(1.27)
. 100(2.54)
MAX
TYP
© 1988 FUJITSU LIMITED D28018S-2C
2·72
.018±.OO3
(0.46;100.08)
Dimensions in
inches (millimeters)
MB82B85-15
MB82B85-20
PACKAGE DIMENSIONS
28-LEAD PLASTIC LEADED CHIP CARRIER
(CASE NO.: LCC-28P-M04)
144 (3 66) MAX
rL
*.725±.005
(18.42±0.13)
.091 (2.31) NOM
.025 (0.64) MIN
d>JJ-~!
.340±.005
(8.64±0.13)
o
INDEX
cf
.273±.020
(6.93±0.51)
.300(7.62)
NOM
J)~
Ll
J
.050±.005
(1.27±0.13)
,----------l
I
.650(16.51) REF
Details of "A" part
.032(0.81)
I
I
MAX
I
I
~-.,
.102 (2.60) NOM
~
~
=1
.004(0.10)
1
l_~ "A"
*= This dimension includes resin
© 1989 FUJITSU LIMITED C28054S-1 C
I
I
I
I
I
i
I
I
I
I
I
I
II
••
I
.017±.004
(0.43±0.10)
I
I
L _________ .--l
protrusion. (Each side: .006 (0.15) MAX)
Dimensions in
(millimeters)
in~hes
2-73
High-Speed BiCMOS SRAMs
2-74
Static RAM Data Book
00
September 1990
Edition 1.0
FUJITSU
DATA SHEET
M882888-151-20
256K-BIT HIGH-SPEED BiGMOS SRAM
32K Words x 8 Bits BICMOS High-Speed Static
Random Access Memory
The Fujnsu MB82B88 is a high-speed static random access memory organized as
32,768 words x 8 bns and fabricated wnh CMOS technology. BiCMOS technology is
used in the peripheral circuits to provide lower power dissipation and higher speed. To
obtain a smaller chip size, the cells use NMOS transistors and resistors.
The MB82B88 is housed in 300 mil plastic DIP and SOJ packages. All pins are TTL
compatible and a single +5 V power supply is required.
The MB82B88 has low power dissipation, low cost, and high performance, and ~ is
ideally su~ed for use in microprocessor systems and other applications where fast
access time and ease of use are required.
•
Organization:
Plastic Package
(DIP-28P-M04)
32,768 words x 8 bits
•
Static operation: no clocks or timing strobe required
•
Access time:
•
Low power consumption:
•
Single +5 V power supply ±1 0% tolerance
•
TTL compatible inputs and outputs
•
Three-state outputs wnh OR-tie capabil~y
•
Electrostatic protection for all inputs and outputs
•
Standard 28-pin Plastic Packages:
Skinny DIP (300 mil) MB82B88-xxPSK
SOJ
(300 mil) MB82B88-xxPJ
tM - tACS - 15 ns max. (MB82B88-15)
tM - tACS - 20 ns max. (MB82B88-20)
715 mW max.
138 mW max.
83 mW max.
(Operating)
(TTL Standby)
(CMOS Standby)
Plastic Package
(LCC-28P-M04)
Pin Asslgnmenl
(TOP VIEW)
Absolute Maximum Ratings (See Note)
Symbol
Value
Unit
Supply Voltage
Rating
Vee
-0.5 to +7
V
Input Volta&e on any pin w~h
respect to ND
VN
-3.5 to +7
V
Output Vo~age on any VO pin with
respect to GND
VOUT
-0.5 to +7
V
Output Current
lOUT
±20
mA
Power Dissipation
Po
1.0
W
Temperature Under Bias
T BlAs
-10 to +85
·C
Storage Temperature Range
Tsm
-45 to +125
·C
Note: Permanent device damage may occur Habsolute maximum ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in the operation
sections 01 this data sheet Exposure to absolute maximum rating conditions for extended periods may affect deviOB reliability.
A7
Vee
As
As
AI.
A3
A2
AI
~
As
As
Al0
All
N
Ao
A14
A12
A13
1101
1102
1103
CS
GND
1/04
1100
1107
1100
IIOs
This ckMoe contalns clrcuhry to protect the Inputs against
:~:.:;:~~~ott;:ne::=~~of:!:d =~r~
of any wttage higher than maximum rated vOhages to this high
lrT1*iance circuit
Copyright © 1990 by FUJITSU LIMITED.,., Fujitsu Mlcroeloclronlca.lnc.
2-75
High-Speed BiCMOS SRAMs
2-76
Static RAM Data Book
cP
September 1990
Edition 1.0
FUJITSU
DATA SHEET
M882889-151-20
288K-BIT HIGH-SPEED BiGMOS SRAM
32K Words x 9 Bits BiCMOS High-Speed Static
Random Access Memory
The Fujitsu MB82B89 is a 32,768 words x 9 bits high-speed static random access
memory fabricated with CMOS technology. For lower power dissipation and higher
speed, the peripheral circuits consist of BiCMOS technology. For smaller chip size, the
cells use NMOS transistors and resistors.
The MB82B89 is housed in 300 mil plastic DIP and SOJ packages. All pins are TIL
compatible and a single +5 V power supply is required.
The MB82B89 has low power dissipation, low cost, and high performance, and it is
ideally suited for use in micropl'OCllssor systems and other applications where fast
access time and ease of use are reqllired.
Plastic Peckage
•
•
•
•
•
•
•
•
•
Organization:
32,768 words x 9 bits
Static operation: no clocks or timing strobe required
Access time:
tM - tACS - 15 ns max. (MB82B89-15)
tM - tACS - 20 ns max. (MB82B89-20)
Low power consumption:
715 mW max. ~ratingl
138 mW max.
Standby)
83 mW max.
CMOS Standby)
(LCC-32P-M02)
,
Single +5 V supply ±1 0% tolerance
TTL compatible inputs and outputs
Three-state outputs with OR-tie capability
Electrostatic protection for all inputs and outputs
Standard 32-pin Plastic pack~es:
MB82B89-xxPSK
Skinny DIP (300 mi
SOJ
(300 mi
MB82B89-xxPJ
Plastic Package
(LCC-32P-M04)
Pin Assignment
(TOP VIEW)
NC
NC
Absolute Maximum Ratings (See Note)
Rating
Symbol
Value
Unit
Supply Voltage
Vee
-0.5 to +7
V
Input Vo~e on any pin with
respect 10 ND
VN
--'3.5 to +7
V
Output VOl!a2e on any 110 pin with
respect 10 G D
VOUT
-0.5 to +7
V
Output Current
lour
±20
mA
Power Dissipation
Po
1.0
W
Temperature Under Bias
TBIAS
-10 to +85
°C
Storage Temperature Range
Tsro
-4510+125
°C
AS
AS
A4
A3
A2
AI
AO
AI2
AI3
1/01
1/02
1/03
1/04
GND
VCC
A7
CS2
WE
M
A9
AID
All
~
AI4
CSI
1/09
1108
007
1108
V06
Note: Pennanent device damage may occur Wabsolute maximum ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in 1I1e operation
sections of this data sheet. Exposure to absolute maximum reting coriditions for extended periods may affect device reliabnity.
ThIs _
cantaI.. clrcullrylO proI8CI1he Inputs again"
. - . - duo 10 high OIaIIevollagOl.,eIec1rIc _ . _ r••
• _
.... normal jII8CaIlIonl be1alaon1O avcId appllca1lan
:::::....
~lhor ..... maxlrrum rated volagoo 10 !hie high
CopyrIght@ 18BObyAJJIlSU LIMITED ... Fujillu M - . I n c .
2-77
High-Speed BiCMOS SRAMs
2-78
Static RAM Data Book
cO
September 1990
Edition 1.0
FUJITSU
DATA SHEET
MBB2BOOB-25
1M-BIT HIGH-SPEED BiGMOS SRAM
128K Words x 8 Bits BiCMOS High-Speed Static
Random Access Memory
The Fujitsu MB82B008 is a high-speed static random access memory organized as
131,072 words x 8 bits and fabricated with CMOS technology. BiCMOS technology is
used in the peripheral circuits to provide lower power dissipation and higher speed. To
obtain smaller chip size, the cells use NMOS transistors and resistors.
The MB82B008 is housed in a 400 liIiI plastic SOJ package. All pins are TTL
compatible and a single +5 V power supply is required.
The MB82B008 has low power dissipation, low cost, and high performance, and it is
ideally suited for use in microprocessor systems and other applications where fast
access time and ease of use are required.
•
•
Organization:
131,072 words x 8 bits
Static operation: no clocks or timing strobe required
•
•
Access time:
1M - tACs - 25 ns max. (MB82B008-25)
Lowpowerconsumplion:
715mWmax. (Operating)
138 mW max. (TTL Standby)
83 mW max. (CMOS Standby)
•
Single +5 V power supply ±1 0% tolerance
•
TTL compatible inputs and outputs
•
Three-state outputs with OR-tie capability
•
•
Electrostatic protection for all inputs and outputs
Standard 32-pin Plastic Package:
SOJ (400 mil)
MB82B008-xxPJ
Plastic Package
(LCC-32P-MXX)
Pin A•• lgnment
(TOP VIEW)
Symbol
Value
Unit
110
110
Supply Voltage
Vee
-8
1107
K>8
1105
1104
A12
Absolute Maximum Ratings (See Note)
Storage Temperature
Range
vee
CS2
A2
AI
AO
VOl
1102
1/03
GND
Standard 32-pad Ceramic Package:
LeC
(metal seal)
MBS464A-xx(LlLL)CV
Rating
<:>
NC
A12
A7
11 mW max.
(MB8464A-SOI-10/-15)
0.55 mW max. (MB8464A-SOU-l0U-15L)
0.55 mW max. (MB8464A-SOLU-10LU-15LL)
Data retention current:
~I '
PIN ASSIGNMENT
•
•
~~
~~ I ' .
NC
WE
AS
A9
A11
NC
AS
,..,
....
A3
A2
AI
TOP VIEW
OE
Al0
AO
CSI
NC
1101
V07
K>8
°C
* -2.0 V for pulse width less than 20 ns.
Note: Permanent device damage may occur if absolUlia maximum ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in !he operation
sections of this data sheet Exposure to absolula maximum rating conditions for exlanded periods may alfect device reliability.
_Ihe
contains clrallUy10
Inpo.es agalnsl
damage due to high static voltages or electric fields. Hovvaver, It
Is advised Ihat normal ~ be takon 10 avoid application
Q/ ""1 voltage higher Ihan maxlrrom . - voIIag.. 10 this high
Irrpodanos clroult.
This _
Cqljolght © 19110 by FWITSU LIMITED and Fi4hu M _...Ica,Inc.
3·5
MB8464A-80/80U80ll
MB8464A-1 0l10U1 Oll
MB8464A-15/15U15ll
Fig. 1 - MB8464A BLOCK DIAGRAM
A,.
r--
A"
A.
·
·
·
A.
r--
A,.
A.
Aa
A7
-
ADDRESS
BUFFER
-
·
·
·
256x32x8
MEMORY CELL
ARRAY
I--
. . .
•
110 GATE
··
ADDRESS
BUFFER
-:::::
-
flOW
DECODER
--aGND
Tcs
:::::
:::::
--avec
r--
&
COLUMN DECODER
. . .
Tcs
I-- CS
DATA 110 BUFFER
BUFFER
t cs
1
110, I!O. 110, 110,110. 110. IIOr 110.
TRUTH TABLE
cs,
cs. oe
H
X
X
L
H
H
L
L
L
H
WE
MODE
X
X
X
X
H
L
H
H
X
L
NOT SELECTED
NOT SELECTED
DOUT DISABLE
READ
WRITE
SUPPLY CURRENT
110 PIN
Is.
HIGH-Z
HIGH-Z
HIGH-Z
DOOT
D,N
Is.
Icc
Icc
Icc
CAPACITANCE (TA=25°C,f=1MHz)
Parameter
3-6
Symbol
Min
Typ
Max
Unit
110 Capac~ance (VllO-0V)
Coo
8
pF
Input Capacitance (V..=OV)
C,N
6
pF
MB8464A-SO/80U80LL
MB8464A-10/10U10LL
MB8464A-15/15U15LL
RECOMMENDED OPERATING CONDITIONS
(Referenced to GND)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Vo~age
Vee
4.5
5.0
5.5
V
Ambient Temperature
T.
0
70
·C
DC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted.)
MB8464A·
Parameter
Symbol
80110/15
Min
Test Condition
Iss,
2
0.1
mA
CS2,s0.2V. CS,~Vee -
• Input Pulse Levels:
O.SV to 2.4V
• Input Pulse Rise and Fall Times: 5ns (Transient Time between O.SV and 2.2V)
• Timing Reference Levels:
Input: V'L-O.SV. V'H-2.2V
Output : VOL-O.SV. VOH-2.0V
• Output Load:
Load I
R,
R.
CL
Parameters Measurad
1.Bkn
990n
100pF
except teL2. t0L2• te... 10HZ. tWL2 and tWHZ
+5V
DOUT o - - - T " " " - - - j
(I/O)
I
LI
C ·..L.
..L::;o:;.;;a;.;:d...:.II:...L.1.;.;..;;Skn;;::.L...:9.::.90;:;:n:.:....L_5:::J;p:;.;;IF......r......:::te~L2.:....:t~ot.Z.~tc.~z~•.:::tc.::::..:...;tc.=z...:tw::::L2~•.;::an;.:;d:..t:::WH::::z'--...J • Including jig and stray capacitance
3-7
MBS464A-SO/SOLJSOLL
MBS464A-1 0/1 OLJ1 OLL
MBS464A-15/15LJ15LL
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
READ CYCLE
Symbol
Parameter
MB8464A8OI80U80LL
NlB8464A10/10Ul0LL
MB8464A15115U15LL
Min
Min
Min
Max
80
Max
100
Unit
Max
150
ns
Read Cycle Time
tAC
Address Access Time
t...
80
100
150
ns
CS, Access Time
!..c,
80
100
150
ns
CS. Access Time
!..c.
80
100
150
ns
Output Enable to Output Valid
IoE
35
45
55
ns
Output Hold from Address Change
IoH
10
10
10
ns
tc.z
10
10
10
ns
5
Chip Select to Output Low-Z"
5
ns
5
Output Enable to Output Low-Z"
Iotz
Chip Select to Output High-Z"
IeHZ
35
35
40
ns
Output Enable to Output High-Z"
10HZ
30
35
40
ns
READ CYCLE TIMING DIAGRAM ..
REAOCVCLE~
ADDRESS=~==:1L-~:~~~Io~H~~~'~~~~~~C======:::=::=::=========
Door
READ CYCLE
PREVIOUS DATA VALID
~-J
ADDRESS~I-~=~=~=~-:"=~
__ __
__==t..
===========================
CS,
CS.
Dour
Note:
3-8
'I
'2
'3
'4
Transition is measured at the point of ±500mV from steady state vo~age.
WE is high for Read Cycle.
Device is continuously selected, CS,.OE'-V,Lo CS.=V'H.
Address valid prior to or coincident with CS, transition low, CS. transition high.
1-----
MB8464A-80/80LJ80LL
MB8464A-1 011 OLJ1 OLL
MB8464A-15115LJ15LL
WRITE CYCLE
Parameter
Symbol
MB8464A8O/80U80LL
MB8464A10/1 OU1 OLL
MB8464A15115U15LL
Min
Min
Min
Max
Max
Unit
Max
Write Cycle Time
two
80
100
150
ns
Address Valid to End of Write
t..w
60
80
100
ns
Chip Select to End of Write
tew
60
80
100
ns
Data Valid to End of Wrne
tow
30
35
40
ns
Data Hold Time
tOH
5
5
5
ns
Write Pulse Width
twp
60
70
90
ns
Address Setup Time
tAS
0
0
0
ns
Wrne Recovery Time
tWR
5
5
5
ns
Wrne Enable to Output Low-Zo,
tWLZ
5
5
5
Wrtte Enable to Output High-Zo,
tWHZ
30
35
ns
40
ns
WRITE CYCLE TIMING DIAGRAM ..
WRITE CYCLE I : WE CONTROLLED
CS,
D,N
DOUT
Note:
°1 Transttion is measured at the point of ±500mV from steady state voltage.
°2 If OE, CS, and CS, are in the READ Mode during this period, I/O pins are in the output state so that the input signals
of oppostte phase to the outputs must not be applied.
3-9
MB8464A·80/80LJ80LL
MB8464A·10/10LJ10LL
MB8464A·15115LJ15LL
WRITE CYCLE II : CS, CONTROLLED*'
ADDRESS
CS.
IIDI
DIN
Dour
WRITE CYCLE III : CS. CONTROLLED*'
ADDRESS
CS.
DIN
Dour
Note:
3·10
*1 HOE, CS. and WE are in the READ Mode during this period, 110 pins are in the output state so that the input signals
01 opposite phase to the outputs must not be applied.
*2 HOE, CS, and WE are in the READ Mode during this period, 110 pins are in the output state so that the input signals
01 opposite phase to the outputs must not be applied.
*3 Transition is measured at the point 01 ±500mV lrom steady state voltage.
MB8464A-80/80U80ll
MB8464A-1 0/1 OU1 Oll
MB8464A-15/15U15ll
DATA RETENTION CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted)
Parameter
Data Retention Supply Voltage
Symbol
Min
VDR
2.0
Max
Typ
5.5
V
1.0
mA
1.0
25
I1A
1.0
2.0
I1A
Standard
Data Retention
Supply Current"'
L-Version
IDR
LL-Version"3
Data Retention Setup Time
Operation Recovery Time
Note:
Unit
tDRS
0
ns
tR
tRC
ns
"2 CS, controlled: VDR=3.0V, CS,:S0.2V
CS, conlrolled: V",,=3.0V, CS,2:VDR -o.2V (CS,:S0.2V or CS,2:VDR -o.2V)
"3 VOR=3.0V, T.=O·C 10 40·C
DATA RETENllON llMING
DATA RETENTION I:cs, CONTROLLED
Vee
r---___ ~~--::~::::-~~E--~~L"---1
-.@
. . h...,
2....
v.....
M '®"T
ri
!SS,>VDR -o.2V
\2.....2....
DATA RETENTION II: CS, CONTROLLED
V~
TTTI"n
CS,
I
~~--::~~~~::=~-~~:t
IORS -
\\\\\\'!MV
IR
CS,:S0.2V
1,
oJ/I$Il
3-11
MBS464A-80/SOLlSOll
MBS464A-1 0l10Ll1 Oll
MBS464A-15115L115ll
TYPICAL CHARACTERISTICS CURVES
Fig. 3 - NORMALIZED POWER SUPPLY
CURRENT vs. SUPPLY VOLTAGE
~
c..
!5
fill-
1.0
.A ~
(/)
!:::!ffi
...Ja:
0.9
~a: 0.8
a::::l
~o 0.7
Icc.
:/
~r
T.- 25°C
Fig. 4 - NORMALIZED POWER SUPPLY
CURRENT vs. AMBIENT TEMPERATURE
~
c.. 1.0
c..
:::l
~I- 0.9
..........
l!;Iffi
leve = min.
<:::l
IsB•
~o
0.7
J
0.6
--
Vee = 5.5V
::::i~ 0.8
z
j
0.6
4.5 4.75 5.0 5.25 5.5
Vee. SUPPLY VOLTAGE (V)
020406080
T•• AMBIENT TEMPERATURE (OC)
Fig. 6 - NORMALIZED POWER SUPPLY
CURRENT vs. AMBIENT TEMPERATURE
Fig. 5 - NORMALIZED POWER SUPPLY
CURRENT vs. CYCLE TIME
"
T.- 25°C
Vee = 5.5V
..........
Ql
r-....
/
./
...........
1
10
Fig. 7 - NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
IT•• 25°C
1M • 1.c•• !..c. _
o
~
1.0
...J
9danc:e circuit
Copyright
©
1990 by FUJITSU LIMITED and Fujitsu Microelectronics, Inc.
3-17
MB84256A-70n0U70LL
MB84256A-10/10U10LL
MB84256A-12112U12LL
MB84256A-15115U15LL
FIg. 1 - MB84256A BLOCK DIAGRAM
AoA, o-----r--,
At. 0------1
At. 0 - - - - 1
Ao 0 - - - - 1
AoAt.
~Vcc
•
ADDRESS
BUFFER
ROW
DECODER
•
•
o----i
0----1
•
•
~GND
256 x 128x8
MEMORY CELL ARRAY
•
o---"L__-'
A7
• • •
OS
Aoo-----r--,
~o::===1
Au 0-----1 ADDRESS
BUFFER
•
•
•
1--------1
A,lg::::::~::::~
A..
At.
I/OGATE &
COLUMN DECODER
aeo----f--'
W£
~-------I
OS
'-r--r-T"'""1--r"""""""'r-'
TRUTH TABLE
os
OE
WE
MODE
SUPPLY
CURRENT
I/O PIN
H
X
X
Not Selected
I..
Hig~
L
H
H
Dour Disable
Higll-Z
L
L
H
Read
L
X
L
Wrilll
Icc
Icc
Icc
Dour
D,N
CAPACITANCE
Par.......
3-18
(TA" 25"C, f • 111Hz)
Symbol
IIIn
Typ
llex
Un"
I/O Caped\ance (VIIO - OV)
Cuo
8
pF
Input CepacItanoe (V... OV)
CII
7
pF
MB84256A-70n0U70ll
MB84256A-10/1 OU1 Oll
MB84256A-12112U12ll
MB84256A-15/15U15ll
RECOMMENDED OPERATING CONDITION
(Referenced to GND)
Par.met.
Symbol
Min
Typ
Mn
Unit
Supply Voltage
V""
4.5
5.0
5.5
V
Ambient Temperature
T.
0
70
"C
DC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
M884256A-70110
P.r8met.
112115
Ta.t Condition
Symbol
Min
M8.
M884256A-70U70LL
110lf10Llf12LJ12LL
115LJ15LL
Min
Unit
Ma.
I..,
CS l! Vee -O.2V
1
0.1
mA
I...
OS =V'H
3
3
mA
VIN
= V1H or V1L
CS = V... lOUT = OmA
60
60
mA
Cycle = Min.
Duly = 100%
louT =OmA
60
80
70
70
lID
Standby Supply Current
Actiw Supply Current
Operating Supply
Currant
I
J
I"",
-70
1=
-10112115
Input Leakage Currant
lu
Output Leakage Currant
lulO
Input High Voltage
V'H
rnA
V'N =OVtoV""
-1
1
-1
1
IIA
V'IO = OV to Vee
= V..
~=V"or~=V'L
-1
1
-1
1
IIA
2.2
Vee +0.3
2.2
Vee +0.3
V
~.O'
0.8
~.O'
0.8
V
cs
Input Low Voltage
V'L
Output High Voltage
VON
ION=-1.0mA
Output Low Voltage
VOL
10L = 2.1mA
2.4
2.4
V
0.4
0.4
V
Note: All voltages are referenced to GND.
': ~.OV min. lor pulse width less than 20 ns.(V'L min. = -O.3V at DC level.)
Fig. 2 - AC TEST CONDITIONS
• Output Load
+5V
)
DOUT
(I/O)
•
•
±~.
•
:
"l7
•
•
Input Pulse Levels:
Input Pulse Rise & Fall Times:
0.6V to 2.4V
5ns (Transient between 0.8V and 2.2V)
•
Timing Reference Levels:
Input:
Output:
R,
V'L=O.8V. V'H=2.2V
VOL=O.8V. VOH=2.0V
• Including Jig and stray capadtanca
R,
R:.
R:.
CL
Parametars Measured
Load I
1.8K'1
990'1
l00pF
except IeLZ.
Load II
1.8K'1
990'1
5pF
1cLz. Iou. tc.z. 10Hz. IwLZ. and ' -
Iou. IeHZ. 10HZ. IwLZ. and ' -
3-19
MB84256A-70/70U70ll
MB84256A-1 0/1 OLJ1 Oll
MB84256A-12112LJ12ll
MB84256A-15/15LJ15ll
AC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
READ CYCLE *1
Symbol
Parameter
Read Cycle Time
70
"'t..."
Address Access Time '.
MB84256A·
7onOl.J7OLL
Min
Max
MB84256A·
1011 OU1 OLL
Min
Max
MB84256A·
12112U12LL
Min
M.x
MB84256A·
15115U15LL
Min
Max
100
120
150
ns
70
100
120
150
n.
n8
CS Access Time '.
Output Eneble to Output Valid
t..cs
70
100
120
150
toe
35
40
50
60
Output Hold Irom Address Change
IoH
10
10
10
5
n8
10
n.
10
10
10
10
n.
5
5
5
Chip Select to Output Low-Z "
leu
Output Eneble to Output Low-Z "
lou
Chip Select to Output High-Z "
IeHZ
25
40
40
50
n8
Output Eneble to Output High-Z "
10HZ
25
40
40
50
ns
n8
READ CYCLE TIMING DIAGRAM *1
READ CYCLE 1: ADDRESS CONTROLLED'2
ADDRESS
Dour
-"iI8c:Ilho Inpula "8_
II18IIcYOltaga .. _ _ • _
••
10 _oed 1haI narmol _ _ be _n 10 avoid app_
::::""'~~hor ilion maximum ratadvollages 10 1hIa high
~dU8lOhIgh
Copyrlght@ 1I18ObJRJJITSULIMIlmIlldF...,II-,1nc.
3-29
MB841000-80/-80L
MB841 000-10/-1 OL
MB841000-12/-12L
Fig. 1 - MB841000 BLOCK DIAGRAM
-
I--
ADDRESS
BUFFER
•
At
At 3
At
At
At
•
•
•
·
·
·
ROW
DECODER
-
I--
- - 0 Vee
·
·
·
ADDRESS
BUFFER
t
·
·
·
1/0 GATE &
COLUMN DECODER
··
·
DATA 1/0 BUFFER
. . .
lCS
OE
BUFFER
1cs
512x 16xBx 16
MEMORY CELL ARRAY
. . .
lCS
IIIDI
--oGND
_CS
! ! ! ! ! ! ! !
VO t 1/0. 1/03 1/0. 1/0, 110s 1/0, 1/0.
CSt~
CS
Cs.
CAPACITANCE
Parameter
1/0 Capacitance (V..,=OV)
Input Capacitance (V..=OV)
3-30
(TA= 25°C,f = 1 MHz)
Symbol
Coo
CI"
Min
Typ
Max
Unit
10
pF
S
pF
MBS41000-S0/-S0L
MBS41 000-1 0/-1 OL
MBS41000-121-12L
PIN DESCRIPTION
Symbol
Pin name
Symbol
Pin name
Acto A,.
Address Input
WE
Write Enable
110, to 110.
Data InputlOutput
Vcc
Power Supply (50±10%)
OE
Output Enable
GND
Ground
CS,
Chip Select 1
NC
No Connect
Cs,
Chip Select 2
FUNCTION TRUTH TABLE
cs,
cs.
OE
WE
MODE
SUPPLY
CURRENT
1/0 PIN
H
X
X
X
Not Selected
ISB
High-Z
X
L
X
X
Not Selected
ISB
High-Z
L
H
H
H
Dour Disable
Icc
High-Z
L
H
L
H
Read
Icc
Dour
L
H
X
L
Write
Icc
D'N
RECOMMENDED OPERATING CONDITION
(Referenced to GND)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vee
4.5
5.0
5.5
V
Ambient Temperature
T.
70
·C
Parameter
0
3-31
MB841000-80/-80L
MB841 000-1 0/-1 OL
MB841000-121-12L
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Test Condition
Symbol
MB841000
-80110/12
Min
Max
MB841QOO
-80LilOU12L
Min
Max
Unit
CS",g).2V or CS,~Vcc-n.2V
(CS.,ro.2V or CS,,2Vcc-n.2V)
188,
1
0.2
mA
CS,=V'H or CS",V'L
ISB2
3
3
mA
Active Supply Current
or V1L •
CS,=V'L, CS,=V'H
louT=OmA
Icc,
5
5
mA
Operating Supply Current
Cycle=Min.
Duty= 100%, louT=OmA
1002
80
80
mA
Input Leakage Current
V'N=OV to Vcc
lu
-1
1
-1
1
IIA
Output Leakage Current
VI/O=OV to Vcc
CS,=V'H or CS",V'L
or OE=V'H or WE=V'L
lulO
-2
2
-2
2
IIA
Input High Voltage
V'H
2.2
Vcc +0.3
2.2
Vcc +0.3
V
Input Low Voltage
V'L
-n.3·
0.8
-n.3·
0.8
V
2.4
Standby Supply Current
V1N=V1H
Output· High Voltage
IOH=-1.0mA
VOH
Output Low Voltage
IOL=2.1mA
VOL
.
Note:
2.4
0.4
V
0.4
V
AII1IOltaQes are referenced to GND.
-3.0V min. for pulse width less than 20 ns. (V'L min. = -n.3V at DC leve!.)
Fig.2 - AC TEST CONDITIONS
?
+5V
• Output Load
....~
~
DoUT
(1/0)
CL•
I
I
I
3-32
Load I
Load II
I
I
I
R,
• Input Pulse Levels: 0.6V to 2.4V
• Input Pulse Rise & Fall Times: 50s (Transient between 0.8V and 2.2V)
• Timing Reference Levels: Input : V'L=D.8V,V'H=2.2V
Output : VOL=0.8V, VOH=2.0V
-L
1
R,
1.8KO
1.8KO
rlT
I
I
I
R"
9900
9900
. Including Jig and stray capacitanoe
I
I
I
CL
loopF
5pF
I
Paramelers Measured
I except IeLZ. 00. leta. Iooa. Iwu and IwHZ
I Iccz. 00. IeHZ. 10Hz. IwLZ and IwHZ
I
I
I
MB841 DOO-SO/-SOL
MB841000-10/-10L
MBS4100o-121-12L
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE *1
MB84100CHIO/BOL
Parameter
MBM84100D-12/12L
Unit
Min
Read Cycle Time
MB84100D-10/10L
Symbol
Address Access Time '2
"'to.."
CS, Access TIme '3
Max
80
Min
Max
100
Min
Max
120
ns
80
100
120
ns
t..c,
80
100
120
ns
Cs,. Access TIme '3
t..c.
80
100
120
ns
Output Enable to Output Valid
foe
35
40
50
ns
Output Hold from Address Change
lot.
10
Chip Select to Output Low-Z '4
IeLZ
10
10
10
Output Enable to Output Low-Z'4
IoLZ
5
5
5
Chip Select to Output High-Z '4
IeHZ
30
35
40
ns
10HZ
30
35
40
ns
Output Enable to Output High--Z'4
Note:
10
10
ns
ns
'1
WE is high lor Read cycle.
'2
'3
Device is continuously selected. CS,=OE=V,L• CS,=V,H•
Address valid prior to or coincident with CS, transition low. CS, transition high.
'4
Transition is measured at the point of ±500mV from steady state voltage with specified Load" in Fig.2.
ns
3-33
MB841000-S0/-80L
MB841 00D-1 0/-1 OL
MB841000-12/-12L
AC CHARACTERISTICS
(Recommended operatIng conditIons unless otherwIse noted.)
READ CYCLE TIMING DIAGRAM *1
READ CYCLE 1: ADDRESS CONTROLLED '2
"'"
t...
PREVIOUS DATA VALID
Dour
1<
X X
i
DATA VALID
READ CYCLE 2: CS" CS, CONTROLLED'3
ADDRESS
"'"
==>{r.o:[=======i~======:=;j-----_-J~]<----.'
CS,
Dour
~ : Undefined
Nota:
3-34
'I
'2
'3
WE is high for Read Cycle.
Device is continuously selected, CS,=OE=VIL, CS.=V'H.
Address valid prior to or coincident with CS, transition low, CS,transition high.
'4
Transition is measured at the point of ±500mV from steady state voltage with specified load II in Fig. 2.
MBS41000-S0/-S0L
MBS41 000-1 0/-1 OL
MBS41000-12/-12L
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
WRITE CYCLE *1*2
MB84100~80L
Parameter
MBM8410OD-12112L
Unit
Min
·s
MB84100D-1OJ10L
Symbol
Max
Min
Max
Min
Max
Iwe
80
100
120
ns
Address Valid to End of Write
t..w
60
80
85
ns
Chip Select to End of Write
lew
60
80
85
ns
Data Valid to End of Write
tow
30
40
45
ns
Data Hold Time
to..
Iwp
0
0
0
ns
50
60
70
ns
Address Setup Time
r..s
0
0
0
ns
Write Recovery Time·4
IwR
5
5
5
ns
Write Enable to Output Low-Z ·5
IwLZ
5
Write Enable to Output High-Z ·5
IwHZ
Write Cycle Time
Write Pulse Width
Note:
·1
5
5
SO
S5
ns
40
ns
·2
·S
·4
If OE. CS, and CS, are in the READ Mode during this period. I/O pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
If CS, goes high or CS, goes low simultaneously with WE high. the output remains in high impedance stale.
All write cycle are determined from last address transition to the first address transition of the next address.
IwR is defined from the end point of WRITE Mode.
·5
Transition is measured at the point of ±500mV from steady state voltage with specified Load 1/ in Fig.2.
3-35
MB841ooo-8o/-8oL
MB841 000-10/·1 oL
MB841ooo-12/-12L
AC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted.)
WRITE CYCLE TIMING DIAGRAM *1 *2
WRITE CYCLE 1: WE CONTROLLED
twe"
ADDRESS
~
--.Ji
t..w
///
~///////////////////
I--tw..' V///
///////
lew
///////////
"" ""
lew
Cs.
//
"""""""""""
//
~t..s--l
twp
"]\""""
D,.
~Iow-
HIGH Z
twHZ"5
~
DouT
-IoH
--I
HIGH Z
DATA VALID
XXXXXXXXX
HIGH Z
L
tWl.Z"
XXXX
~ : Undefined
NOle:
'1
'2
'3
'4
'5
3-36
If OE, CS, and Cs. are in the READ Mode during this period, 1/0 pins are in the output state so that the input signals of
opposite phase to the outputs must not be applied,
If CS, goes high or CS2 goes low simultaneously with WE high, the output remains in high impedance state.
All write cycle are determined from last address transition to the first address transition of the next address.
twR is defined from the end point of WRITE Mode.
Transition is measured at the point of ±500mV from steady state voltage with specified Load II in Fig. 2.
MBS41000-S0/-S0L
MBS41 OOD-1 0/-1 OL
MBS41000-121-12L
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
WRITE CYCLE TIMING DIAGRAM *1 *2
WRITE CYCLE 2: CS, CONTROLLED
twe"
ADDRESS
-
~
~
!.Aw
/ / / ~///////////////////
////
///////
!.As
~
lew
i--twR' -
lew
Cs.
"""""""""""
/////
twp
"""""" """""'"
f/////L//LL
t--lew- I-- IoH
HIGH Z
Dour
HIGH Z
-.(
DATA VALID
D'N
~.
I
HIGH Z
twHZ ·5
~
X X
HIGH Z
~ : Undefined
Note:
-I
-2
-3
-4
If OE, Cs, and Cs. are in the READ Mode during this period, I/O pins are in the output state so that the input signals of
opposite phase to the outputs must not be applied.
If CS, goes high or CS2 goes low simultaneously with WE high, the output remains in high impedance state.
All write cycle are determined from last address transition to the first address transition of the next address.
twR is defined from the end point of WRITE Mode.
-5
Transition is measured at the point of ±500mV from steady state voltage with specified Load II in Fig. 2.
3-37
MB841000-80/-80L
MB841 000-1 0/-1 OL
MB841000-12/-12L
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
WRITE CYCLE TIMING DIAGRAM *1 *2
WRITE CYCLE 3: CS2 CONTROLLED
ADDRESS
-
Iwc
K:
t..w
///
///////////////////
////
///////
lew
"", ~
""
/ / / /V//////
~IwR-
lew
es.
""""" """"
D'N
tw..
///////////
........
t-- tow - - I-- IoH ......
HIGH-Z
DATA VALID
!CU ••
Dour
HIGH-Z
X
~
HIGH Z
HIGH Z
X
~ : Undefined
Note:
3-38
"2
"3
"4
If OE, es, and es. are in the REAP tAode during this period, 110 pins are in the output state so that the input signals of
opposite phase 10 the outputs must not be applied.
1IC5; goes high or es. goes low simultaneously with
high, the output remains in high impedance stale.
All write cycle are determined from last address transition to the first address transition of the next address.
IwR is defined from the end point of WRITE Mode.
"5
Transition is measured III the point of ±500mV from steady stale voltage with specified Load II in Fig. 2.
"t
wr:.
MBS41000-S0/-S0L
MBS41 000-10/-1 OL
MBS41000-12/-12L
DATA RETENTION CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Data Retention Supply Voltage
Symbol
Min
VCR
2.0
Data Retention Supply I Standard
Current '1
L-Version
IDR
Data Retention Setup Time
to...
Operation Recovery Time '2
...
Note:
Unit
Max
Typ
5.5
V
0.5
0.1 '2
mA
mA
0
ns
t..:
ns
'I V",,=VDR =3.0V
"Cg;",V DR -O.2V, CS",VDR -O.2V or CS.SO.2V (at"Cg; CONTROLLED)
CS.SO.2V (at Cs. CONTROLLEO)
'2 t..:: Read Cycle Time
DATA RETENTION TIMING
1
cs, CONTROLLED
I- :~v
Vee
IVA
2.2V'
cs. CONTROLLED
\
r~0.4V
Data Retention Mode
4:5V ...
~
t
L _________ !.'!. _______ -'
IoRS
CS2
t
cs,"'VOR-O.2V
1
4.5V
,~---
L _________ !.'!. _______ -'
4.5V
...
CS.SO.2V
--j ITT7
O.4V_--f-.LLL
3-39
MB841000-80/-80L
MB841 000·10/·1 OL
MB841000·121·12L
PACKAGE DIMENSIONS
(Suffix: P)
32-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No.: DIP-3ZP-MOI)
t------1.592:!::8~~ (40M,:g:~g)-----·-t1
-.------II'_iiiiiia::::+ 15° MAX
I
.543±.010
(13.BO±0.25)
.600(15.24)
~~~~~~
II ..
~
TYP
~
032:':Jl12
(0.62:,:g·30)
~-=i1197(5.00) MAX
~125(3.1B) MIN
.050(1.27)
MAX
.100(2.54)
O1B:,::gg~
TYP
(045:':8:6~)
.020(0.51) MIN
Dimensions in
© 1988 FUJITSU LIMITED 032001S-1 C
3·40
inches (millimeters)
MBS41000-S0/-S0L
MBS41 000-10/-1 OL
MBS41000-121-12L
PACKAGE DIMENSIONS
(Suffix: PF)
32-LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT-32P-M03)
,---------------,I
I
Details of "A" part
I
I
W~'00610'15):
I
o
I
o
I
101210.30)
:
I
I
II
~M~l~
I
I
:
MAX
.025(0.63)
I
L_______~~ ______ ~
~.817~:g6gI20.75~8:~~)1
!nnnDDnD~nl1Dn D~
.050(1.27)
TYP
.,
.D16+· 004
-.002
10.40~8:6g)
';';-""<0'".1
-$ ~.OO510.13)@
.750 (19.05) REF
© 1990 FUJITSU LIMITED F32008S-3C
.567±.OO8
114.40±0.20)
.09812.50) MAX
ISEATED HEIGHT)
.031 ±.008
10.BO±0.20)
010) MIN
ISTAND 0 FF)
I
.441 ±.004
111.20±0.10)
•
I
bJ (r----.hJ
.11.
.504±.008
112.80±0.20)
.006 ±.002
10.15±0.05)
I
Dimensions in
inches (millimeters)
3-41
Low-Power CMOS SRAMs
3-42
Static RAM Data Book
Section 4
Application Specific CMOS SRAMs -
At a Glance
"axlmum
A_
Page
Device
4-3
MB81C51-25
Capadty
TIme (na) (Organization)
--00
Package
Optlona
25
30
2048 bits
(512 x 4-way) or
(1024 x 2-way)
64-pin
Ceramic PGA
4-17
MB81C79B-35
-45
35
45
73728 bits
(8192x9)
28-pin
Plastic
DIP,SOP
4-29
MB8279RT-20
-25
20
25
73728 bits
(8192 x 9)
32-pin
Plastic
DIP,SOP
4-41
MB8287-25
25
Plastic
DIP,SOP
35
262144 bits
(32768 x 8)
32-pin
-35
16384 bits
(2048x8)
48-pin
52-pin
64-pin
Plastic
Plastic
Plastic
DIP
DIP
SOP
16384 bits
(2048x8)
48-pin
52-pin
64-pin
Plastic
Plastic
Plastic
DIP
DIP
SOP
65536 bits
(8192x8)
64-pin
Plastic
QFP
4-63
MB8421-90, --SOL and LL 90
-12, -12L and LL 120
III
MB8422-90,--90Land LL 90
-12, -12L and LL 120
4-67
MB8431-90, -90L and LL 90
-12, -12L and LL 120
MB8432-9O, -90L and LL 90
-12,-12LandLL 120
4-65
MB8441-45
45
-55
55
4-1
Application Specific SRAM
4-2
Static RAM Data Book
cO
February 1990
Edition 2.0
DATA SHEET
FUJITSU
MB81C51-251-30
CMOS TAG RANDOM ACCESS MEMORY
CMOS Tag Random Access Memory
The Fujitsu MB81 C51 is a 512 entry x4 way or 1024 entry x2 way tag random access
memory (Tag RAM) fabricated with CMOS technology.
The MB81 C51 is ideal for use in cache memory systems with other RAMs. This device
offers the advantages of compact design and high performance in cache systems for
use with 32-bit CPUs.
•
Organization:
512 Entry x 4 way or
1024 Entry x 2 way
•
Access time:
30 ns max from Address Inputs
18 ns max from Compare Data Inputs
•
Power consumption:
•
Single +5 V power supply ±1 0% tolerance
1375 mW max.
• TIl. compatible inputs and outputs
•
LRU (Least Recently Used) replacement logic
•
Purge function (All-purge and partial-purge)
•
Internal parity generalor/checker
•
Standard 64-pin Ceramic Pin Grid Array Package:
PGA MB81C51-xxCR
Absolute Maximum Ratings (See Note)
Rating
PGA-64C-A02
(PIN GRID ARRAY)
Symbol
Value
Supply Voltage
Vex;
-0.5 to +7
Un"
V
Input Vo~e on any pin with
respect to ND
VN
--3.0 to +7
V
Output VoHage on any pin with
respect to GND
Voor
-Q.5 to +7
V
Output Current
lour
±20
mA
Power Dissipation
PD
1.5
W
Temperature Under Bies
TaN
-10 to +85
°C
Storage Tempereture Range
TSTG
~!ito+125
°C
Note: Permanent device damage may ocaJr Habsolulll maximum ratings are exceeded.
Functional operation should be rastriclad to !he oondilions as detaIed in Ihe operation
sections 01 this data sheat Exposure to absolulll maximum rating conditions lor exIIInded periods may aflect devios re.ability.
4·3
MB81C51-25
'MB81C51-30
Fig. 1 - MB81C51 BLOCK DIAGRAM 1
ENTRY
I-- PURGE
I-- BUFFER
AD
.
0-
•
I----
••
~
ADDRESS
BUFFER
&
DECODER
•
•
•
•
r
512 ENTRY
X 23 BIT
X4WAY
•
AS
/'- ~
,
MEMORY CELL
Ii
~
l\r
A
V
PU
--
I'r-
r'
PARITY
DATA
PARITY
GENERATOR
512 ENTRY
X 6 BIT
y-
"
O-
;.-
MEMORY CELL
I--
~
REPLACE INFO,
T
A
G
,;.-
GSENSE OUT
J,.
D
A
T
A
~I
COMe.,AW'
L..-
PARITY
CHECKER
WI
r-
LRU
LOGIC
NEW LRU DATA
TDO
0-
•
•
•
•
•
TD19
0-
HIT
INF~.
REPLACE INFO.
TAG
DATA
BUFFER
-
-
,
7'
...
MPX &
OUTPUT CONTROL
6....... 6
HITIREPLACE
INFO.
4-4
,
;.OUTPUT CONTROL
6
PARITY ERROR
VCC
GND
MB81C51·25
MB81C51·30
Fig. 2 - MB81C51 BLOCK DIAGRAM 2
TOO - TD19
MHENBl Vee EXTH
20
MmT
COMPARE
88
HiT
& VALIDITY
CHECK
HITOI
REPO
HIT11
REP1
AO - A8
HIT21
REP2
HIT31
REP3
HCOI
RCO
HC11
RC1
'PEAR
RlATCH
CAPACITANCE
(TA
SBO
SB1
SBlK
H/R
.
= 25°C f = 1 MHZ)
Parameter
Input Capacitance (VIN = OVj
Symbol
CIN
Typ
Max
Unit
10
pF
lEI
MB81C51·25
MB81C51·30
PIN ASSIGNMENT
64 PIN PIN GRIO ARRAY(PGA-64C-A02)
BOTTOM VIEW
PIN FUNCTION
Pin No.
4-6
Function
Pin No.
Function
Pin No.
Function
1
N.C.
23
A4
45
2
MHIT
24
A5
46
T09
3
HITO/REPO
25
A7
47
Vee
T06
4
HIT2/REP2
26
A9
48
T013
5
HIT3/REP3
27
N.C.
49
T015
6
TOO
28
N.C.
50
T017
7
T02
29
PINV
51
T019
8
EXTH
30
SBlK
52
AO
9
MHENBl
31
SBl
53
A2
10
N.C.
32
INH
54
GNO
11
T07
33
INVl
55
A6
12
T08
34
SET
56
A8
13
T010
35
H/R
57
PURGE
14
TOll
36
HIT
58
MODE
15
T012
37
HCO/RCO
59
VINV
16
T014
38
HC1/RCl
60
SBO
17
T016
39
HIT1/REPl
61
Vee
18
T018
40
GNO
62
WRITE
19
N.C.
41
TOl
63
RlATCH
20
N.C.
42
T03
64
PERR
21
Al
43
T04
22
A3
44
T05
MB81C51-25
MB81C51-30
PIN DESCRIPTION
OUTPUTS
INPUTS
HIT OUTPUT. "NOR" OF HITO TO HIT3
HIT
HCn/RCn
CODED OUTPUTS OF HIT OR REPLACE INFORMATION ( n = 0 - 1 )
HITn/REPn
UNCODED OUTPUTS OF HIT OR REPLACE INFORMATION ( n = 0 - 3 )
PERR
PARITY ERROR
MHIT
HIT OUTPUT MODIFIED BY MHENBL AND EXTH
MODE
MODE SELECTION
MODE = 1 : 512 Entry x 4 Way
MODE = 0: 1024 Entry x 2 Way
AO-A9
ADDRESS INPUTS (A9 Is not used for 4 way)
TDO-19
TAG INFORMATION INPUTS
PURGE
ALL-PURGE TIMING PULSE
INVL
PARTIAL-PURGE. V-BIT FORCED TO "0".
LRU IS REVERSIVELY UPDATED
SBLK
ENABLE WAY-SELECTION EXTERNALLY AT REPLACEMENT AND INVALIDATION
SBO, SBI
EXTERNAL WAY-ADDRESS INPUTS
WRITE
WRITE CYCLE SIGNAL
SET
TIMING PULSE
Write: Reglstrate TAG, V-bit "H", LRU update
Read : LRU updated
PARTIAL PURGE : LRU reverslvely update, V-bit "L"
INH
ALL FUNCTIONS EXCEPT PURGE ARE INHIBITED
H/R
OUTPUT SELECTION
H/R = 1 : Hit Information
H/R = 0 : Replace Information
RLATCH
LATCH CONTROL FOR REPLACE INFORMATION
PINV
USE FOR "TESTING" ONLY (GENERALLY "H")
VINV
USE FOR "TESTING" ONLY (GENERALLY "H")
MHENBL
ENABLE MHIT OUTPUT
EXTH
FORCE MHIT OUTPUT TO "L"
FUNCTION TABLE
1) BASIC FUNCTION (Any combination except below are inhibited.)
Input
TAG Inlo.
INH
PURGE
SET
WRITE
INVL
L
H
X
X
X
N-CNG
H
H
H
X
X
N-CNG
H
H
H
H
N-CNG
Control Inlo.
TAG
P bit
V bit
LRU
LRU
Function Mode
N-CNG
N-CNG
INHIBIT3
N-CNG
N-CNG
N-CNG
TAG READ
N-CNG
N-CNG
N-CNG1
or UP-D
TAG READ
TAG WRITE
N-CNG
H
H
1f
1f
L
H
TOO to TD19
SET
H
UP-D
X
L
H
X
X
UNDEFINED
UNDEFINED
L (All)
INCLZ
ALL PURGE
H
H
1f
H
L
N-CNG
N-CNG
N-CNG/L2
N-CNG 1
or RUP-D
PARTIAL PURGE
X : "W or "L"
N-CNG : No Change
INCLZ : INITIALIZE
UP-D : Up Dated
RUP-D : Reverslvely Updated
1. When SBLK = "L" and no-HIT, then LRU Is no change (N-CNG).
2. When SBLK = "L" and.!lQ:HIT, then V-Bit Is no change (N-CNG).
3. During INHIBIT mode, HIT and PERR outputs are • W but the other outputs are • L" •
4·7
..
MB81C51-25
MB81C51-30
2) OUTPUT PIN FUNCTION
Internal Info. 1. 2
Input
Output
Mode
AS
hitOI
repO
hlt11
repl
hlt21
rep2
hlt31
rep3
HITOI
REPO
HIT11
REPl
HIT21
REP2
HIT31
REP3
HCOI
RCO
HCll
RCl
~
H
X
L
L
L
L
L
L
L
L
L
L
H
H
X
H
L
L
L
H
L
L
L
L
L
L
4
H
X
L
H
L
L
L
H
L
L
H
L
L
W
HIT
Mode
H
X
L
L
H
L
L
L
H
L
L
H
L
A
H
X
L
L
L
H
L
L
L
H
H
H
L
y
L
L
L
X
L
X
L
L
L
L
L
L
H
L
L
H
X
L
X
H
L
L
L
L
L
L
2
L
L
L
X
H
X
L
L
H
L
L
H
L
W
L
H
X
L
X
L
L
L
L
L
L
L
H
A
L
H
X
H
X
L
L
H
L
L
H
L
L
y
L
H
X
L
X
H
L
L
L
H
H
H
L
X: "H" or "L"
1. Internal Information. repO to rep3 are determined by on-chip LRU logic when SBLK "L". When SBLK
Information are determined by external signal of SBO & SB 1.
2. Correct ol!!!:,atlon Is not guaranteed If 2 ways or more become HIT at the same time.
3. Output of HIT Is valid when H/R "H".
=
= "H".
the Internal
=
3) PARTIAL PURGE (INVL
= "L")
INPUT
PURGE BLOCK
HIT
BLOCK
SET
LJ
MODE
AS
SBLK
SBO
SBl
0
1
2
3
0
1
2
3
LRU
H
X
L
X
X
L
L
L
L
-
-
-
---
H
X
L
X
X
H
L
L
L
Q
-
H
X
L
X
X
L
H
L
L
-
Q
-
H
X
L
X
X
L
L
H
L
-
-
Q
-
H
X
L
X
X
L
L
L
H
-
-
H
X
H
L
L
X
X
X
X
Q
H
X
H
H
L
X
X
X
X
H
X
H
L
H
X
X
X
X
-
H
X
H
H
H
X
X
X
X
L
L
L
X
X
L
X
L
X
L
L
L
X
X
H
X
L
X
L
L
L
X
X
L
X
H
L
L
H
L
L
X
X
X
L
L
H
L
H
X
X
X
X
-
-
L
H
L
X
X
X
L
X
L
-
-
L
H
L
X
X
X
H
X
L
-
Q
RUP-O
MODE
4
RUP-O
RUP-O
W
Q
-
-
Q
RUP-O
-
-
-
RUP-O
-
---
Q
-
-
Q
-
RUP-O
X
-
-
Q
-
X
Q
-
-
-
RUP-O
Q
-
RUP-O
W
-
-
--RUP-O
A
y
L·
H
L
X
X
X
L
X
H
L
H
H
H
L
X
X
X
X
L
Note:
4-8
INTERNAL INFO.
-
-
Q
-
X
X
X
X
H
H
H
H
Correct operation Is not guaranteed If 2 ways or more become HIT at the same time.
Q
RUP-O
A
-
RUP-O
Y
RUP-O
RUP-O
Q
RUP-O
-
RUP-O
Q
RUP-O
2
MB81C51·25
MB81C51·30
4) PARITY ERROR & V·BIT 1
( n . 0 to 3 )
HIT Inlo. 2
pen
vnO
vn1
PEn
l
l
l
l
---
l
l
H
H
HIT
l
H
l
H
HIT
l
H
H
l
HIT
H
l
l
l
---
H
l
H
H
HIT
H
H
l
H
HIT
H
H
H
H
HIT
pen
vnO/vnl
PEn
Internal parity error 01 way "n'
Duplicate validity bits.
Determined by the following equation.
PEn = (vnO + vnl) • p~n + (vnO
0
vnl)
1. PERR Is "NOR" 01 PEO to PE3
2. Output Inlormatlon when Internal "HIT" Is valid.
BASIC FUNCTIONS
TAG READ
A comparison between the TAG Input data (TDO-19) and the
contents 01 the addressed location Is performed. If both data
are the same. that Is "FOUND". Then HiT will be "lOW" and
outputs of HCn. HITn Indicate hltted "Associative way". In the
case 01 " NOT·FOUND" • the TAG RAM will specify the "way".
which should be replaced, by using the lRU logic automatically.
The replacement Information will be preaented at the outputs of
RCn and REPn by forcing the H/R Input Into "lOW". These
signals will be latched and used for the data Memory move-In
operation.
lEI
ALL PURGE
By asserting Pui'iGE Input "lOW", the V-bit are reset and lRU
logic Is Initialized.
In this operation, the contents of each TAG and Its parity will
not be Identified.
PARTIAL PURGE
The partial purge operation Is performed by iNV[ "lOW· and
SET pulse Input.
TAG WRITE
The V -bit, which Is specified by the address Inputs, will be
reset, and lRU logic will be reverslvely updated.
When "NOT-FOUND" Is occurred, the TAG-RAM also should
be updated. The write operation Is performed by WFii"fE
"lOW" and SET pulse Input. The TAG data will be written Into
the proper "way" by the InternailRU logic.
TAG-WRITE mode, V-bit (Validity bit) and the parity are set,
and LRU logic Is updated.
On the other hand, It will be able to specify the "way"
externally by using SBlK, SBO and SBI Inputs.
4-9
MB81C51·25
MB81C51·30
RECOMMENDED OPERATING CONDITIONS
Parameter
(Referenced to GND)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vee
4.5
5.0
5.5
V
Ambient Temperature
TA
0
70
·C
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Input Leakage Current
Operating Supply Current
=0 V to Vee
DOUT =Open, Cycle =min.
VIN
Symbol
III
Min
Max
-10
10
!LA
250
mA
Icc
Unit
Input Low Voltage
VIL
-0.5-
O.S
V
Input High Voltage
VIH
2.2
6.0
V
0.4
V
Output Low Voltage
Output High Voltage
Note:
--3.0V min. for pulse width less than 20ns.
4·10
Test Condition
=SmA
IOH =-4mA
IOL
VOL
VOH
2.4
V
MB81C51·25
MB81C51·30
Fig. 3 INPUT PULSE LEVELS
AC TEST CONDITION
O.OV to 3.0V
INPUT PULSE RISE AND FALL TIMES:
5ns (Transient time between O.BV and 2.2V)
TIMING REFERENCE LEVELS
Input
: 1.5V
Output : 1.5V
OUTPUT LOAD:
5.0V
-r-
DOUT"-
••
4BOO
•
2550
...L.
30pF
(Including JlgI
~
lEI
AC CHARACTERISTICS
4-11
MB81C51·25
MB81C51·30
..
4-12
MB81C51-25
MB81C51-30
TAG READ CYCLE (MOli= "H" or "L", PURGE = "H", WRITE = "H", INVL = "H", PIN V = "H" or "l", VINV = "H" or
"l", INH = "H")
AO - A9
TOO - TD19
H/R
HIT,
HCn, HITn
(Note 1)
RCn, REPn
(Note 2)
MHENBl,
EXTH
r--
OUTPUT VALID
tAP
-------'-----1
---:.....:..,~,b
OUTPUT VALID ~
to--
IRlATCH
(Note 5)
SBlK
tAS
1-======. .
tAS
1+----
---too+=-!~=-~
l
Note 4
tSBR
---...J
tSBH
INPUT VALID
1+----SBO, SBl
(Note 6)
1+ \SR
tTS
tSBS -----<~
INPUT VALID
Iii
Notes 1:
2:
3:
4:
5:
6:
Don't Care
Valid at H/R = "H",
Valid at H/R = "l",
lRU is updated at SET = "l",
Replace latched at RlA TCH = "H" ,
Valid at SBlK = "l",
Valid at SBlK = "H",
4-13
MB81C51-25
MB81C51-30
TAG WRITE CYCLE (MODE
= "W
or "l",
P'U'RGE ="W, WRiTE = "l",
INVl
= "W,
INH
="W)
AO - A9
H/R
RCn, REPn
..
TOO - TD19
RlATCH
(Note 3)
SBlK
SBO,SBl
(Note 4)
IMU
Notes 1.
2.
3.
4.
4-14
Reglstrate TAG, V-bit "W, lRU update.
Replaoe latched at Ri:A'i'CH = "H" .
Valid at SBlK "l".
Valid at SBlK = "W.
=
Don't Care
MB81C51·25
MB81C51·30
PARTIAL PURGE CYCLE (MODE = ·W or..::.b:.... PURGE = "W, WRITE = "W, INVl
RlATCH = "l", PINV = "W or "l", VINV = "W or "l")
= "l",
H/R
= "W
or "l",
iNH = "W,
AO - A9
TOO - TD19
(Note 1)
SBlK
lEI
SBO, SBI
(Note 3)
Imml
Don't Care
Notes:
1, Valid at SBlK = "l",
2, lRU Is reverslvely updated, V-bit "l".
3. Valid at SBlK = "W.
All purge (SET
= "H",
OTHER CONTROL INPUTS ARE "W or "L")
AO - A9
\.
r---tppw
\.
INPUT VALID
tPR
I{
tAPe
4-15
MB81C51-25
MB81C51-30
PACKAGE DIMENSIONS
(Suffix: -CR)
64·LEAD CERAMIC (METAL SEAL) PIN GRID ARRAY PACKAGE
(CASE No.: PGA-64C·A02)
.050(1.27IDIA TYP
/
@
0
0
o
INDEX A REA
\
h
D
U
o
0
0
o
0
o
0
0
000
0
@
0
O@
."""~"Q ]
IIEII
TYP
1.032+. 018
-.012
sa
©1988 FUJITSU LIMITED R64008S.2C
4-16
Dimensions in
inches (millimeters)
OJ
October 1989
Edition 1.0
FUJITSU
DATA SHEET
MB81C79B-351-45
CMOS 72K-BIT HIGH-SPEED SRAM
8K Words x 9 Bits High-Speed CMOS Static Random
Access Memory with Automatic Power Down
The Fujitsu MB81C79B is a 8,192 words x 9 bits static random access memory
fabricated with CMOS technology. The 9-bit organization of this device is desirable for
use in a parity check function. This device also has two fast cOlumn addresses, making
it very suitable to use as cache buffers. To make power dissipation lower, peripheral
circuits use CMOS technology, and to obtain smaller chip size, cells use NMOS
transistors and resistors. All pins are TTLcompatible and asingle +5 V power supply is
required.
The MB81 C79B offers low power dissipation, low cost, and high performance.
•
o
Organization:
8,192 words x 9 bits
Static operation: no clock or timing strobe required
•
Access time:
•
Low power consumption: 550 mW max. (Operation)
138 mW max. (TTL Standby)
83 mW max. (CMOS Standby)
Single +5 V power supply ±1 0% tolerance
TTL compatible inputs and outputs
Three-state inputs and outputs
Chip select for simplified memory expansion, automatic power down
Electrostatic protection for all inputs and outputs
Standard 28-pin Plastic Packages:
Skinny DIP (300 mil) MB81C79B-xxPSK
SOP
(450 mil) MB81C79B-xxPF
PLASTIC PACKAGE
DIP-28P-M04
t.v. - tACS1 - 35 ns max, toe - 10 ns max.
A11, A12 aocesstime _12 ns max. (MB81C79B-35)
t.v. - tACS1 - 45 ns max, toe - 15 ns max.
A11, A12 aocesstime -15 ns max. {MB81C79B-45)
•
•
•
•
•
•
PLASTIC PACKAGE
FPT-28P-M02
PIN ASSIGNMENT
Absolute Maximum Ratings (See Note)
Rating
Symbol
Value
UnR
Supply Voltage
Vcc
-{l.5 to +7.0
V
Input Volla&e on any pin with
respect to ND
VIN
-3.5 to +7.0
V
Output Voltage on any 110 pin
with respect to GND
VOUT
-{l.5 to +7.0
V
Output Current
loUT
±20
mA
Power Dissipation
Po
1.0
W
Temperature Under Bias
TslAS
-10 to +85.
OC
Storage Temperature Range
Tsro
-40 to +125
OC
"-
Veo
''""
WE
t.,
'"
'"
A,
A"
An
Note: Permanent device clemage may occur if absolU1le maximum ratings are excesdad.
CSt
A,
A"
110,
A,
DE
'"
CS,
IIC,
IIC,
IIC,
IIOa
110,
110,
IIC,
GNO
IIOa
Functional oparetion should be restrk:led to the conditions as detailed in lIIe operation
sections 01 this data sheet Exposure to absoluta mBJCimum rating condition,lor exlanded periods may affect device re.ability.
_ _ _ clrcUlttylO_1heI",UllagaN1
'--duelOhlgh_"""-or _ _
••
• _ _ n..·marpnlC8lOlonobe1ak8nlO avoid appllcalion
.~
Ill...,. ...... higher 1hen """"""'" rated voItaaaa OJ this high
in1Iodanco circuit.
Capjrlghl@ 1980 by FWnsU LIMITED IIId FI4I11u U - . I n c .
4-17
MB81C79B-35
MB81C79B-45
Fig. 1 - MB81C79B BLOCK DIAGRAM
-
-
ADDRESS
BUFFER
·
·
-
-v""
•
·
-·
ROW
DECODER
-·
Js·
-GND
256.32.9
MEMORY CELL
ARRAY
.
1•
Ao
A,.
·Au
.~
1/0 GATE
&
ADDRESS
BUFFER
COLUMN DECODER
.
I•
JS'
BUFFER
•I
DATA I/O BUFFER
-
cs
b_1/0, b b1/0.b b_b
b1/0,b ~Vo.
Vo"
ds
va.
CS, -----------....
CS" --,-~_1
•I
00,
1/0.
1/0.
TRUTH TABLE
CS,
H
L
L
L
L
CS" WE
X
L
H
H
H
X
X
H
H
L
OE
X
X
H
L
X
C~::€JT
MODE
STANDBY
DESELECT
Dour DISABLE
READ
WRITE
Sfr"E
HIGH-Z
HIGH-Z
HIGH-Z
DOUT
D'N
I••
I""
I""
Icc
Icc
• Fast address
CAPACITANCE (T'A--25°C, f-1MHz)
-
Max
Unit
Input Capacitance (V,.=n Current
IPO
Standby Supply Current
2.4
50
rnA
Vcc=OV to Va; Min.
CS,=Lower of Vee or V'H Min.
4-19
MB81C79B-35
MB81C79B-45
AC TEST CONDITIONS
Input Pulse Levels:
O.SVto 2.4V
Input Pulse Rise And Fall Times:
5ns (Transient time between O.BV and 2.2V)
Timing Measurement Reference Levels: Input: 1.5V
Output:l.5V
Fig. 2
Output Load I.
Output Load II.
For all except Iu. !"z. twz. low. Iou. and to..z.
For Iu. !"z. Iwz. low. IoLZ. and 10HZ.
5V
5V
Dour
30pF
(Including Scope
and Jig Capacitance)
4-20
T
rfr
5pF
(Including Scope
and Jig Capacitance)
255(1
MB81 C79B-35
MB81 C79B-45
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE·'
Paramalar
Symbol
Read Cycle Time
t..,
Address Access Time ••
1M
CS, Access Time ·3
MB81C79B-35
MB81C79B-45
Min
Min
Max
35
Max
Unit
ns
45
35#1
45#2
ns
t..cs,
35
45
ns
Cs, Access Time ·3
t..cs.
15
20
ns
Output Hold from Address Change
IoH
OE Access Time
to.
Output Active from CS, ·.·s
tu.
5
5
ns
Output Active from Cs,···s
tu:.
2
2
ns
Output Active from OE ••• ,
lou
2
2
ns
Output Disable from CS, ••• ,
It.z,
20
25
ns
Output Disable from Cs,·.·s
It...
20
25
ns
Output Disable from OE ·.·s
10Hz
20
25
ns
Note: ·1
·2
·3
·4
·5
#1
#2
3
ns
3
10
15
ns
lEI
WE is high for Read cycle.
Device is continuously selected, CS,=V... Cs,=V" and OE=V'L.
Address valid prior to or coincident with CS, transition low, CS.transition high.
Transition is specified at the point of ±5OOmV from steady state voltage.
This parameter is specified with Load II in Fig. 2.
All, A12 address access time is 12ns max.
A II, A 12 address access time is 15ns max.
4-21
MB81C79B-35
MB81C79B-45
READ CYCLE TIMING DIAGRAM "1
READ CYCLE I: ADDRESS CONTROLLED-2
ADDRESS
l~
DATAOUT _______p_R_EV_I_O_US
__
DA_T_A_:_A_L_ID_______
___
D_A_T_A_V_A_L_ID_______
READ CYCLE II: CS" Cs. CONTROLLED-s
""'''' II
~101~'-::~~~:::::-t...-----------------t--""'-----------'l~ht@@;mwB
Cs.
VO
101 :Undefined II: Don't Care
Note: -1 WE is high for Read cycle.
-2 Devica is continuously selected, CS,=V'L, Cs.=V1H and OE=VL .
-3 Address valid prior to or coincident with CS, transition low, CS2 transition high.
-4 Transition is specified at the point of ±500mV from Sleady state voltage.
-5 This parameter is spacified with Load II in Fig. 2.
4;'22
MB81 C79B-35
MB81 C79B-45
WRITE CYCLE"
Parameter
Symbol
MB81C79B-35
MB81C79B-45
Min
Min
Ma.
Ma.
Unit
Write Cycle Time *.
!we
35
45
ns
CS, to End of Write
lew,
30
40
ns
Cs. to End of Write
Icwz
20
25
ns
Address Valid to End of Write
low
30
40
ns
Address Setup Time
los
0
0
ns
Write Pulse Width
fwp
20
25
ns
Data Setup Time
low
17
20
ns
Write Recovery Time *3
IwA
3
3
ns
Data Hold Time
!ott
0
0
ns
Output High-Z from WE *. *.
Iwz
Output low--Z from WE *. *.
low
Note: *1
*2
*3
*4
*5
15
0
20
0
lEI
ns
ns
If CS, goes high simultaneously wilh WE high, the output remains in high impedance state.
All writa cycles are detarmined from Ihe last address transition to the first address transition of next address.
IwR is defined from the end point of Writa Mode.
Transition is specified at the point of ±5OOmV from steady state voltage.
This parameter is specified wilh Load II in Fig. 2.
4-23
MB81C79B-35
MB81C79B-45
WRITE CYCLE TIMING DIAGRAM .,
WRITE CYCLE I: CS" Cs., CONTROLLED
ADDRESS
CS,
Cs.,
1/0
~
Note:
: Undefined
I:
Don't Care
·1 If OE, CS" and CS2 are in the READ Mode during this period, 1/0 pins are in the output state so that the input signals of
opposite phase to the outputs must not be applied.
·2 All write cycles are determined from the last address transition to the first address transition of next address.
·3 twR is defined from the end point of WRITE Mode.
·4 Transition is specified at the point of ±500mV from steady state voltage.
·5 This parameter is specified with Load II in Fig. 2.
4-24
MB81 C79B-35
MB81 C79B-45
WRITE CYCLE TIMING DIAGRAM
"1
WRITE CYCLE II: WE CONTROLLED
ADDRESS
Cs.
1/0
101 :Undefined II: Don't Care
Note:
'I If OE, Cs" and Cs. are in the READ Mode during this period, I/O pins are in the output state so that the input signals of
opposite phase to the outputs must not be applied.
'2 All write cycles are determined from the last address transition to the first address transition of next address.
'3 twR is defined from the end point of WRITE Mode.
'4 Transition is specified at the point of ±500mV from steady state voltage.
'5 This panuneter is specified with Load II in Fig. 2.
4-25
MB81C79B-35
MB81 C79B-45
PACKAGE DIMENSIONS
28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-28P-M04)
1.392~ :g?~(35.36 ~8:~g,
INDEX-1
-----II
~~~~~~~~~-~
r--
.260±.010 .300(7.62)
(S.60±0.25) TYP
INDEX-2 ~=i=;:=;=;O:::;=:;=;==rT=;=;r=;=r;=::r:=T=;=;r=;=n=::r:=T=;=;=rjoI.--I
~
Ell
.050(1.27)
MAX
© 1988 FUJITSU LIMITED D28018S-2C
4-26
Dimensions in
inches (millimeters)
MB81 C79B-35
MB81 C79B-45
PACKAGE DIMENSIONS
28-LEAD PLASTIC FLAT PACKAGE
(Case No.: FPT-28P-M02)
0(0) MIN
1iiIRI'~·&l:",·,··gl~~
l
d
INDEX
.110(2.BO) MAX
I----
2
2
ns
tPU'2
2
2
ns
Do~
1.22
2
8
2
10
ns
t,.,.Z2
2
8
2
10
ns
IoH
tpH
2
2
ns
2
2
ns
PE
Do~
PE
D~
PE
IoH'
tpH•
10
2
2
ns
2
2
ns
4-33
MB8279RT-20
MB8279RT-25
READ CYCLE TIMING DIAGRAM
READ CYCLE (INH-l. ClR.H)
--.-j
J---IcLL - - . - j
ClK
ADDRESS
..
CS.
DATAI~ ------------;-------rr--~
Note 1: PE output remains High-Impedance state through undefined area.
4-34
MB8279RT-20
MB8279RT-25
WRITE CYCLE
Parametar
Wr~e
Symbol
Cycle Time
!we
Clock "H" level Pulse Width
MB8279RT-20
Min
20
8
Clock "l" level Pulse Width
IeLH
Ie
InpU1 Setup Time
t,.
Input Hold Time
tH
4
2
CS. Setup Time
Ie.
2
CS. Hold Time
Data Setup Time
IeH
tos
tDH
0
6
Data Hold Time
ClK to OU1put High-Z
ClK to OU1put low-Z
DOUT
PE
tHZ
DoUT
PE
t12
tpHZ
tP12
Max
a
a
2
2
a
a
2
2
MB8279RT-25
Min
25
Max
Unit
ns
10
10
4
2
2
ns
10
0
6
ns
2
2
2
ns
ns
ns
ns
ns
ns
10
10
ns
ns
ns
ns
2
CLOCK INHIBIT TIMING
Parameter
Symbol
MB8279RT-20
Max
MB8279RT-25
Min
2
2
Max
Unit
Clock Inhibit Setup Time
leus
Clock Inhibit Hold Time
IeUH
Min
2
2
Clock Enable Setup Time
let..
2
2
ns
Clock Enable Hold Time
IelEH
0
0
ns
ns
ns
REGISTER CLEAR TIMING
Parameter
Symbol
MB8279RT-20
Max
MB8279RT-25
Min
Max
7
Clear Pulse Width
IeRW
Min
7
Clear Hold Time
IeRH
10
10
Clear Recovery Time
IcAA
10
IeRHZ
2
10
2
Clear to Output High-Z
a
Unit
ns
ns
ns
10
ns
4-35
MB8279RT-20
MB8279RT-25
WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE (INH-l, ClR-H)
.....------fwc-------.t
ClK
ADDRESS
CS.
DATA 110
Note 1: When CS.="W level, write operation is excuted and when CS.= "l"level, write operation is cancelled.
4-36
MB8279RT-20
MB8279RT-25
CLOCK INHIBIT TIMING DIAGRAM
CLOCK INHIBIT
ClK
INH
REGISTER CLEAR TIMING
REGISTER CLEAR
ClK
\
~
--l
'----IeRR
DATA 110
\----
HIGH-Z
+-+-1..-+-+-+-1..-+-1+----------------------HIGH-Z
~--r-_,__r__7--r-_,__h----------------------
4-37
MB8279RT-20
MB8279RT-25
EXAMPLE OF MB8279RT BASIC FUNCTION
CASE
READ a
WRITEb
READd
READe
ClK
ADD.
1/0
PREVIOUS DATA DATA OUT
CS.
CASE
DATA IN
DATA OUT
DATA OUT
B=CANCEl
READ a
WRITEb
DUMMY
READe
ClK
INH
CS.
4-38
____--J/
\'-------B=CANCEl
MB8279RT-20
MB8279RT-25
PACKAGE DIMENSIONS
32-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No_: DIP-32P-M02)
15"MAX
1
.01O±.0021
1O.25±0.051
~
1~·20715.25IMAX
I••
I Illf If If
1.10012.541
TYP
.J
~
11.27~g.301
--II ..
01S±.003
1O.45±0.OSI
lEI
=P.12513.1SIMIN
.02010.511
MIN
Dimensions in
inches (millimeters)
© 1988 FUJITSU LIMITED D32009S-1C
4-39
MB8279RT-20
MB8279RT-25
PACKAGE DIMENSIONS (Continued)
32·LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT·32P·M02)
rmoc cr''-
1--:=:1
, • ISTAND OFFI
I
~
i ---1.050(127)
I
,.
I
.465+.012
111.S0iO.30)
339 ± .OOS
TYP
I.
l~ ~ J
~00510 13)@]
01S' 004
10 45+0 101 l':"J"C
~ •
I
.799::g~~(20.29~g:ig)
Jl.061O.151
.402' .012
031
=r_SO+:20~ .
--IL!J!l~·002
1O.15tO.05)
.09S12.501 MAX
bd
~~.
FdQQDDJ1QrmQ~
I-[91004r.~~iJ
~----
1988 FUJITSU LIMITED F32004S-1C
4-40
ISEATED HEIGHT)
Deta"s of "Au pact
.00710. HII,
---- - - - - - - - - - - - - , - - - - - , - - - - - - - - - - -
.750119.051 REF
±1~~s20l±0'301
MAX
Dimens'lons in
Inches {millimeters)
cO
April 1990
FUJITSU
Edition 2.0
DATA SHEET
MB8287-251-35
CMOS 288K-BIT HIGH-SPEED SRAM
32K Words x 8 Bits Static Random Access Memory with
Automatic Power Down
The Fujitsu MB8287 is a 32,768 words x 8 bits static random access memory with
parity generator and checker, and fabricated with CMOS technology. To obtain a
smaller chip size, the cell uses NMOS transistors and resistors. This device is housed
in a 300 mil DIP package with low (605 mW max.) power dissipation. All pins are TTL
compatible and a single +5 V power supply is required.
A separate chip select ~ pin simplffies multipackage systems design by permitting
the selection of an individual package when outputs are OR-tied, and then
automatically powering down the other deselected packages.
PLASTIC PACKAGE
(DIP-32P-M02)
The MB8287 offers low power dissipation, low cost, and high performance.
•
•
•
•
•
•
•
•
•
•
Organization:
32,768 words x 8 bits
Static operation: no clocks or timing strobe required
Access time:
tM -I.\csl _25 ns max, tACS2 - 14 ns max. (MB8287-25)
1M -I.\csl _35 ns max, I.\cs2 - 15 ns max. (MB8287-35)
Low power consumption: 715 mW max. (Operating) for 25 ns
605 mW max. (Operating) for 35 ns
138 mW max. (TTL Standby)
83 mW max. (CMOS Standby)
Single +5 V power supply ±1 0% tolerance
TTL compatible inputs and outputs
Three-state outputs with OR-tie capacity
Chip select for simplified memory expansion
Electrostatic protection for all inputs and outputs
Standard 32-pin Plastic Packages:
Skinny DIP (300 mil) MB8287-xxPSK
SOP
(450 mil) MB8287-xxPF
PIN ASSIGNMENT
As
A.
A,
A2
A,
Absolute Maximum Ratings (See Note)
Rating
Po.
Symbol
Value
Unh
Supply Voltage
Vee
- < X X X
READ CYCLE: CS" CS, CONTROLLED"
ADDRESS
CS.
I/O
DOI1T VALID
•
Note:
'1
'2
'3
'4
:DonlCare
~ : Undefined
WE is high for Read Cycle.
Device is continuously selected, CS, = V,L, CS. = V,H and OE = V,L.
Address valid prior to or coincident w~h CS, trans~ion low, CS. transition high.
Trans~ion is specHied at the point of ±500mV from steady state voltage with specHied Load II in Fig. 2.
4-45
MB8287-25
MB8287-35
PARITY READ FUNCTION TIMING DIAGRAM·"1) ADDRESS CONTROLLED"'
INPUT VALID
ADDRESS
t..PA
DATA VALID
2) CS" CS. CONTROLLED"'
ADDRESS
INPUT VALID
t..PCS, ----101
CS.
•
Note:
: Don't Care
~ : Undefined
"1 WE is high for Read Cycle.
"2 Device is continuously selected, CS, ~ "L", CS, - "H" and OE - "L"
"3 Address valid prior to or coincident w~h CS, trans~ion low, CS, transition high.
"4 Transition is specHied at the point of ±SOOmV from steady state voltage with specHied Load II in Fig. 2.
"S When error occurred,PE pin outputs "L". But when no error,PE pin is in High-Z state.
4-46
MB8287·25
MB8287-35
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
WRITE CYCLE'" 'o. '.
MB8287-25
Parameter
MB8287-35
Symbol
Unit
Min
Max
Min
Max
Write Cycle Time"
twe
25
35
ns
Address Valid to End of Write
tAW
18
28
ns
CS, to End of Write
lew,
16
26
ns
CS. to End of Write
tem
13
20
ns
Data Setup Time
tow
8
12
ns
Data Hold Time
tOH
a
a
ns
Write Pulse Width
twp
15
20
ns
Wrtte Recovery Time"
tWR
a
a
ns
Address Setup Time
tAS
a
a
ns
Output Low-Z from WE"
low
a
a
ns
Output High-Z from WE"
twz
a
-
Nole:
'1
'2
'3
'4
'5
'6
8
a
14
lEI
ns
HCS goes high simultaneously with WE high, the output remains in high impedance state.
All Wrtte Cycle are determined from the last address transttion to the first address transition of next address.
IwR is defined from the end point of Write Mode.
Transttion is specified at the point of ±500mV from steady state voltage with specified Load II in Fig. 2.
In normal Write Cycle, fiE pin must be pulled-up to High.
Hdata "L" is written infiEpin under the same timing as data input on 110 pins, "Error" information is written in the parity
bit addressed forcibly.
4·47
MB8287·25
MB8287·35
WRITE CYCLE TIMING DIAGRAM· t , oS ••
WRITE CYCLE No.1 (WE CONTROLLED)
ADDRESS
..
CS•
I/O
•
Note:
4·48
'1
"2
'3
'4
'5
'6
: Don't Care
~ : Undefined
HCS goes high simultaneously with WE high, the output remains in high impedance state.
All Write Cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of Write Mode.
Transition is specified at the point of ±500mV from steady state voltage with specified Load II in Fig. 2.
In normal Write Cycle,PE pin must be pulled-up to High.
Hdata "L' is written in PE pin under the same timing as data input on I/O pins, "Error" information is written in the parity
bit addressed forcibly.
MB8287-25
MB8287-35
WRITE CYCLE TIMING DIAGRAM'" ",
,5
WRITE CYCLE No.2 (CS" CS, CONTROLLED)
1+---------- t we" - - - - - - - - - - - t
ADDRESS
VALID
1-0-------- tAW - - - - - - - - l
OE
I + - - - - - - tew, ---------t
CS,
CS,
twp
1/0
0,,, VALID
D :Don't Care
Note:
'1
'2
'3
'4
'5
~ : Undefined
If CS goes high simultaneously with WE high, the output remains in high impedance state.
All Write Cycles are determined from the last address transition to the first address transition of next address.
tWR is defined from the end point of Write Mode.
In normal Write Cycle,PE pin must be pulled-up to High.
If data "L" is written inPEpin underthe same timing as data input on 1/0 pins, "Error" information is written in the parity
bit addressed forcibly.
4-49
MB8287-25
MB8287-35
PACKAGE DIMENSIONS
32-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No_: DIP-32P-M02)
15·MAX
~~i :::::::~: ::r~~'
1.57 i'iUSv R
C> INTR (Nole)
NOTES: MB8421 only.
I/O CAPACITANCE
(TA = 25
°e,
f = 1 MHz)
Max
Unit
Input Capacitance (VIN
Symbol
CIN
10
pF
1/0 Capacitance
CliO
10
pF
Parameter
= OV)
(Vila = OV)
Typ
4-55
MB8421/22-901-90Ll-90LL
MB8421/22-12/-12L1-12LL
PIN ASSIGNMENTS
MB8421 - Top View
(DIP-52P-M01 )
CsL
¥VEL
..
MB8422 - Top View
(DIP-48P-M02)
VCC
GsR
B\!.§.Yl
INTL
NC
~
~L
NC
.t.!.oR
OER
AOR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
OEl
AOl
A1l
A2l
A3l
A4l
A5l
A6l
All
A8l
A9l
I/OOl
MB8421 - Top View
(FPT-64P-M01)
MR
I/Oll
I/07R
I/OBR
I/02L
I/03L
lI04 L
I/05R
I/04R
I/06l
1I05L
I/03R
I/02R
I/OlL
I/01R
VSS
I/OOR
vce
CsL
WEl
64636261605958575655545352
BUSYR
INC)
1
51
50
OEL
AOl
A1l
A2l
A3l
A4l
A5l
A6l
A7l
A8l
A9l
INC)
INC)
INC)
I/OOl
1/01 L
I/02L
I/03L
NC
NC
~
>lll1l
OEl
AOl
A1l
A2l
OER
AOR
A1R
A2R
A3R
A4R
ASR
A6R
A7R
A8R
A9R
NC
NC
NC
11
12
13
14
15
16
17
18
19
~
BuSvL
~SYR
Al0R
OER
AOR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
A3l
A4l
ASl
A6l
A7l
A8l
A9l
I/OOl
I/07R
I/D6A
I/05R
20212223242526272829303132
II01l
I/07R
1I02L
I/03L
I/04L
I/05L
IID6l
1I07L
I/06R
I!OSR
1/04R
lJ03R
I/02R
1I01R
VSS
IIOOR
PIN DESCRIPTIONS
Left Port
Right Port
Function
WEl
WER
Write Enable
CSl
CSR
Chip Select
OEl
OER
Output Enable
BUSYl
BUSYR
Busy Flag
Left Port
INTl
AOl
--
IIOOl--
A10l
IIO~
Right Port
FUnction
INTR
Interrupt Flag
AOR-- A10R
Address
I/OOR"- I/07R
Data Input/Output
Vee
Power (Commonj
Vss
Ground (Commonj
FUNCTIONAL OPERATION
The MB8421 and MB8422 provide two ports with separate
control signals, address inputs, and input/output data pins that
allow asynchronous read and write operations to any memory
location, Each device has an on-chip automatic po",er-down
feature controlled by CS that places the respective port in the
standby mode when the chip is deselected (CS is HIGHj.
4-56
When a port is enabled, access to the entire memory array is
permitted.
Each port has an independent Output Enable (OEj control that Is active In the read mode and enables
the output drivers. Non-contention Read/Write conditions are
shown in the following Truth Table; a simplified block diagram
of the dual-port SRAM is shown In Fig. 1.
MB8421/22-90/-90Ll-90LL
MB8421122-12/-12L1-12LL
NON-CONTENTION READIWRITE CONTROL
RIGHT PORT INPUTS'
LEFT PORT INPUTS'
R/WL
CSL
OEL
X
H
X
R/WR
CSR
X
X
X
X
X
X
X
L
L
L
L
X
H
X
X
L
X
X
X
X
H
NOTES:
1. AOL -Al0ut AOR - A10R
2. H = HIGH, L = LOW, X = Don't
FLAGS
OER
BUSYL
FUNCTION
BUSYR
X
X
H
H
Left Port In Power Down Mode
H
X
X
L
L
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
Richt
Data
Data
Data
Data
Port In Power Down Mode
on Left Port Written Into Memorv
In Memorv Outout on Left Port
on Richt Port Written Into Memorv
In Memorv Outout on Richt Port
Care
ARBITRATION LOGIC
The arbitration logic resolves an address match or chip-enable
match and determines the access priority. In both cases, an
active BUSY flag Is set for the port-In-waiting. Since both
ports are asynchronous, there Is the possibility of accessing
the same memory location from both sides. In the read mode,
this condition Is not a problem. However, this Is a problem
when both ports are In a write mode with different data words
or when one port Is reading and the other is writing. When both
ports access the same memory location, the on-chip
arbitration logic determines which port has access and the
1i'USY flag for the delayed port Is set active LOW and all
operations on that port are Inhibited. The delayed port can be
accessed when the BUSY flag becomes inactive. Basic modes
of abltratlon are described In subsequent paragraphs.
1. When addresses for both the left and right ports match
and are valid before CS Is active, the on-chip control
logic arbitrates between
CSL and CSR for device
access. Refer to the following Truth Table for signal
states; timing detail Is shown later In this data sheet
under "Data Contention Cycle No.2 (CS controlled)."
2.
When CS Land CSR are LOW before an address match,
on-chip control logic arbitrates between the left and right
Signal states for this
addresses for device access.
condition are shown in the following Truth Table; timing
detail is shown under "Data Contention Cycle No. 1
(Address Controlled) ."
ARBITRATION WITH ADDRESS MATCH BEFORE CS
LEFT PORT
R/WL CSL
OEL
RIGHT PORT
AOL-Al0L R/WR
CSR
OER
FLAGS
AOR-Al0 R BUSYL
FUNCTION
BUSYR
X
LBR
X
MATCH
X
L
X
MATCH
H
L
Left Operation Permitted
Right Operation Not Permitted
X
L
X
MATCH
X
LBL
X
MATCH
L
H
Right Operation Permitted
Left Operation Not Permitted
X
LST
X
MATCH
X
LST
X
MATCH
H
L
Arbitration Resolved
NOTES: X
= Don't Care,
L
= Low,
= High,
H
LST= Low Same Time, LBR = Low Before Right, LBL
= Low Before Left
ADDRESS ARBITRATION WITH CS LOW BEFORE ADDRESS MATCH
R/WL CSL
LEFT PORT
OEL AOL-Al0L
R/WR
RIGHT PORT
FLAGS
OER AOR-Al0 R BUSYL BUSYR
CSR
FUNCTION
X
L
X
VBR
X
L
X
VALID
H
L
Left Operation Permitted
Right Operation Not Permitted
X
L
X
VALID
X
L
X
VBL
L
H
Right Operation Permitted
Left Operation Not Permitted
X
L
X
VST
X
L
X
VST
H
L
Arbitration Resolved
NOTES: X
= Don't Care,
L
= Low,
H
= High,
VST
= Valid Same
Time, VBR
= Valid
Before Right, VBL = Valid Before Left
4-57
lEI
MB8421/22-90/-90Ll-90LL
MB8421/22-12/-12L1-12LL
When both CSL and CSA are low at the same time
(CS controlled) or when both left-and-rlght addresses are
valid at the same time (address controlled), the BUSYAflag for
the right port Is set to the active LOW state and access is
granted to the left port.
For the Intel 8086 and Fujitsu's MBL8086 as well as most other
microprocessors, the asynchronous BUSY signal can be
directly tied to the READY Input, providing setup~and-hold
time requirements are met.
INTERRUPT FUNCTION
The Interrupt (INT) function provides communication between
systems on both sides of the dual-port RAM.
INTL is set
LOW when the processor on the right port writes to address
7FE (AO = Land Al-Al0 = H). When the left port
acknowledges by reading address 7FE, INTL Is then reset to
HIGH. In essence, address 7FE serves as an 8-blt mailbox
that transfers Information from the right port to the left port.
When iNi'A is set LOW, the processor on the left port writes
When the right port
to address 7FF (AO-A 1O=H).
acknowledges by reading address 7FF, INTA Is then reset to
HIGH. Hence, address 7FF serves as a second 8-blt mailbox,
transferring Information from the left port to the right port.
On power-up, INTL and INTA are set to a HIGH state.
However, if one port Is in the standby mode, the standby port
can stili be Interrupted by the processor on the other port. But
If the BUSY flag Is set to the LOW state, the port associated
with that flag cannot set or reset the INT flag.
RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Parameter
Symbol
Value
Unit
Min
Tva
Max
5.0
5.5
V
70
°c
Supply Voltage
Vcc
4.5
Operating Temperature
TA
0
DC CHARACTERISTICS
Recommended Operating Conditions unless otherwise noted.)
MB8421!
Symbol
Condition
Parameter
MB8422-90!12
Min
Max
Cycle - Min
ICC
Operating Supply Current
120
ports
Active)
[but'!r
==
lJl~A
(Both
ISBl
ISB2
Standbl(
Supply Current
ISB3
.i!Q!h poL1.s at Standby
CS & CSA= VIH
Qr1e por1.i!t Standby
CSL or CSA =VIH,
lOUT = 0 mA
§2th por!.!!.. at Full Standby
CSL & CS A ::: Vce -0.2V
MB8421/MB8422
-90L/-90LL/-12L/-12LL
Min
Max
Unit
90
mA
7
5
mA
70
50
mA
2
0.2
mA
ISB4
Qne porilt Full Standby
CSL or CS A ::: Vcc -0.2V
lOUT = 0 mA
50
mA
Input Leakage Current
III
VIN = OV to Vcc
-10
10
-10
10
J.lA
Output Leakage Current
ILO
f;,SYc~IH, VOUT = OV
-10
10
-10
10
J.lA
Input High Voltage
VIH
2.2
Vec +0.3
2.2
Vce +0.3
V
Input Low Voltage
VIL
-0.3
0.8
-0.3
0.8
V
70
Output High Voltage
(~g~)
lOUT = -1.0 mA
Output Low Voltage
VOL
lOUT = 3.2 mA
0.4
0.4
V
g~~,:tD~~~ Voltage for
VOL
lOUT = 8 mA
0.4
0.4
V
NOTE:
4-58
2.4
2.4
The BUSY and INT pins require pull-up resistors because they are open-drain outputs.
V
MB8421/22-90/-90Ll·90LL
MB8421/22·12/·12L1·12LL
AC CHARACTERISTICS
Recommended ODerations Conditions unless otherwise noted.)
MB8421-90190L190LL
MB8422-90190Ll90LL
Symbol
Parameter
Min
ii\/i··.··.·
Read Cycle Time
t RC
MBB421-12112L112LL
MBB422-12112L112LL
Max
Min
I
····.·· .........
120
90
Unit
Max
Address Access Time
tAA
90
120
ns
Chip Select Access Time
t ACS
90
120
ns
Output Enable Access Time
t AOE
50
ns
Output Hold from Address Change
tOH
10
10
ns
Chip Select to Output Low-Z (Note 1)
tCLZ
5
5
ns
Output Enable to Output Low-Z (Note 1)
tOLZ
5
5
Chip Select to Output Hlgh-Z (Note 1)
tCHZ
40
50
ns
Output Enable to Output High-Z (Note 1)
tOHZ
40
50
Power up from Chip Select
tpu
ns
ns
Power down from Chip Select
tpD
60
ns
Read Cycle No. 1 2, 3.
~14~
Address
______________
ns
0
50
lEI
t R C - - - - - - - -________~~
----~*'--------------------------~*~----
j4
tAA
!--- tOH - . j
DOUT
40
0
...
ns
-I
I
M"'*.,"'
__-_-_-_-_-_-_-_-_-_-D~at~a~v~al~ld~~~~~~~~~~~~~~~=
,
Previous Data Valid
'
Read Cycle No. 2 2 :
14
Address
===*------------~----------~~~----j4
CS
-I
tRC
-,,!
tAA
tmmz07ll
.....
\\,.....\"\\"'\'T"\"«
OE
I
l
:
DOUT
ICC
Vcc Current
ISB
Hlgh-Z
I
I--- tA10E
I+-
I
:
I
I
-I
'H't
tOLZ...j:
~
1
i- -l
--------------...J"f
Data Valid
'
t pu
1.J
OHZ ---.,
~
1
Hlgh-Z
I+- tpD~
50% ~
50%
Legend:
1m
Don't Care
~
Undefined
NOTES:
1. Transition Is measured at a point of:!: 500 mV from steady-state voltage with an output capacitance of 5pF.
2. WE Is High during read cycle.
_
_
3. Device is continuously selected (CS OE VIL) .
=
=
4-59
MB8421/22-90/-90L/-90LL
MB8421/22-12/-12L/-12LL
AC CHARACTERISTICS (Continued)
MBB421-90/90Ll90LL
MBB422-90/90Ll90LL
Min
Max
Symbol
Parameter
two
Write Cycle Time
Address Valid to End of Write
Chip Select to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output Low-Z (Note 4)
Write Enable to Output Hich-Z Note 4
MBB421-12/12L112LL
MBB422-12/12L112LL
Min
Max
tow
tow
tOH
tow
twz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
120
100
100
0
70
0
40
0
0
90
85
85
0
60
0
40
0
0
40
Unit
50
Write Cycle No. 1 (WE Controlled) 1,2
*li~~~==];::::::::::::~~~w~~::::::::::::::.[I====:i*. .____
I~
~I,..-____
two
Address---.....
t
I~
tow---'''I:
\\\\\\}\smV01WIIZO010
~~S
WE
zmo7.I---
.~~~~--- twp---~.rt~~tw~R~1~,,~'_ _ _ ___
¥\\Si-
High-Z
DIN
OE
~
I+--
_1
tow
Data Valid
tOHZ~
Hlgh-Z
Write Cycle No.2 (CS Controlled) 1,2,3
I~
two -------------l·..tl
Address--.......*,....---------------~)(~--
I~ I
I
~w
.. I
i
_ _ _~'~~~.•. - - - - - - - tow-------~..~I.rr.MM~:~~Tr~
SWs
H i
I.
\\\\\\\\\\S;\\\\\\N
+t/llllJjlJJ///O
twR=;[
f
:
~I.
i
tAS
WE
Hlgh-Z
DIN
DOUT
I
t
,
twp
::
tLZ
J.t---- tov"
.~ twz"--.j ~
-------+r----J(~
Data
valld~
tOH::"i
tov/'
~
~
Hlgh-Z
Legend:
Hlgh-Z
1m Don't Care
~
Undefined
NOTES:
1. The Write Enable (WE) signal must be high during an address transition.
2. If the Output Enable (OE) and Chip Select iCS) signals are In the Read Mode. the associated 1/0 pins are In the output
state; accordingly, Input signals of opposite phase must not be applied to the outputs.
3. If CS goes high prior to or coincident with the low-to-hlgh transition of WE, the output remains In high-Impedance state.
4. This parameter Is specified at a point:!: 500 mV from steady-state voltage with an output capacitance of 5 pF.
4-60
M88421/22-90/-90Ll-90LL
M88421/22-12/-12L1-12LL
AC CHARACTERISTICS (Continued)
Symbol
Parameter
MSB421-90/90L
MSB422-90/90L
I
Min
Max
Min
.·····}edanceclrcult.
Inc.
4-85
MB8441-45
MB8441-55
PIN ASSIGNMENTS
Top View
(FPT-64P-M06)
A12L
OEL
AOL
AlL
A2L
A3L
A4L
A5L
A6L
A7L
ABL
A9L
(NO)
(~
BE
IlOOL
II01L
II02L
I/03L
4-86
64 63 6261605958 57 56 55 5453 52
1
51
2
3
4
5
6
7
8
W
9
10
11
12
13
14
15
16
17
18
19
33
202122 23 24 2526272829 30 3132
AllR
A12R
O'ER
AOR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
ABR
A9R
(NO)
(NO)
(NO)
I/07R
I/OBR
I/05R
MB8441·45
MB8441·55
PACKAGE DIMENSIONS
54-LEAD
(0 PLASTIC F LAT PACKAGE
t";===.972±.016(24.70±04~se
I'1:MJ"""""
No.: FPT-64P-M06)
.132(3.35) MAX
,,~'" """""
.642±.016
(16.30 ± 0.40)
.472 (12.00)
REF
© 1990 FUJITSU LIMITED F64013S-2C
Dimensio~; i~
-----
inches (millimeters)
4-87
Application Specific CMOS SRAMs
4-88
Static RAM Data Book
Section 5
Extended Temperature Range SRAMs Maximum
Acceaa
At a Glance
Package
Page
Device
TIme (n.)
Capacity
Option.
5-3
MB8464A-10-X,-10LL-X
-15-X,-15LL-X
100
150
65536 bits
(8192x8)
28-pin Plastic
DIP,SOP
32-pad Ceramic LCC
5-15
MB84256A-70-X, -70LL-X
-lO-X, -10LL-X
70
100
262147b~s
28-pin
(32768x8)
Plastic
DIP,SOP
5-1
Extended Temperature Range SRAMs
5-2
Static RAM Data Book
cO
January1990
Edition 1.0
FUJITSU
DATA SHEET
MB8464A-10-Xl-10LL-Xl-15-Xl-15LL-X
CMOS 64K-BIT LOW-POWER SRAM
8K Words x 8 Bits CMOS Static RAM for Extended
Temperature Operation
The Fuj~su MB8464A-X is an 8,192 words x 8 b~s static random access memory
fabricated w~h a CMOS silicon gate process. The memory uses asynchronous
circu~ry and may be maintained in any state for an indefinite period oftime. All pins
are TTL compatible and a single +5 V power supply is required.
The MB8464A-X has low power dissipation,low cost and high performance, and ~
is ideally suited for use in microprocessor systems and other applications where
fast access time and ease of use are required.
•
Organization:
8,192 words x 8 b~s
•
Access time:
100 ns max.
150 ns max.
(MB8464A-10-Xl-10LL-X)
(MB8465A-15-Xl-15LL-X)
•
Operating temperature: -40°C to +85°C
•
Static operation: no clock required
•
TTL compatible inputs and outputs
•
Three-state outputs
•
Single +5 V supply ±1 0% tolerance
•
PLASTIC PACKAGE
DIP-28P-M04
PLASTIC PACKAGE
FPT-28P-M02
CERAMIC PACKAGE
LCC-32C-A02
NC
A12
A7
Low power consumption:
1.1 mW max.
(CMOS standby)
27.5 mW max. (TTL standby)
Data retention: 2.0 V min.
•
Standard 28-pin Plastic Packages:
DIP
(600 mil)
MB8464A-xx(LL)P-X
MB8464A-xx(LL)PSK-X
Skinny DIP (300 mil)
SOP
(300 mil)
MB8464A-xx(LL)PF-X
I::
C
C
All C
ASC
M~
A3~
:~
10
11
12
13
I:
14
15
1/01
Unit
Supply Voltage
Vee
-0.5 to +7.0
V
Input Voltage
V IN
-0.5 to Vee +0.5
V
Output Vo~age
VIIO
-0.5 to Vee +0.5
V
T BIAS
-50 to +95
I Ceramic
I Plastic
TSTG
PM
TOP VIEW
I:
Ali
Value
~
20
1.
18
17
16
A7
Storage Temperature
Range
26
•
5
6
7
EI
pvcc
27 PIVE
8
Absolute Maximum Ratings (See Note)
Temperature Under Bias
28
~~ •
GND
Symbol
1
2
3
CS2
A8
25
2.
23 PAll
22
Ala
21
A21:
Standard 32-pad Ceramic Package:
LCC
(metal seal)
MB8464A-xx(LL)CV-X
Rating
o
PIN ASSIGNMENT
•
•
PLASTIC PACKAGE
DIP-28P-M02
NC
NC
~OE
~ CSl
1.08
P
t:J1.06
1.07
fJ
1.05
1:11.04
WE
I vec""! CS2
-6510 +150
-40 to +125
Note: Pennanentdevice damage may occur if absolute maximum ratings are exceeded.
Functional operation should be restricted to the conditions as datailed in the operation
sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
This device contains circuitry to protect the Inputs against
damage due to high static voltages or electric fields. However. it
Is advised that normal precautions be taken to avoid application
d any voltage higher than maximum rated voltages to this high
l!Tl)EIdance
circu~.
Copyr~ht © 1900 by FUJITSU LIMITED and Fufltsu Microelectronics. Inc.
5-3
MB8464A-10-Xl-10LL-X
MB8464A-15-Xl-15LL-X
Fig. 1 - MB8464A-X BLOCK DIAGRAM
-
A12
Al1
Al0
•
•
•
ADDRESS
BUFFER
As
As
A7
As
At.
-
- - 0 Voo
--0 GND
•
•
•
ROW
DECODER
256x32x8
MEMORY CEll ARRAY
-
-
I
Tcs
•
I/OGATE &
COLUMN DECODER
•
•
ADDRESS
BUFFER
I
• • •
I
Tes
I
• • •
f--
DATA 110 BUFFER
BUFFER
CS
11111111
Tes
~ -------~
1/01 1102 1103 110< 1105 vOe 1107 VCl6
TRUTHTAIiLE
MODE
SUPPLY
CURRENT
CSI
CS2
OE
WE
H
X
X
X
X
X
NotSeIeded
NoISeIeded
lsa
High-Z
High-Z
H
Dour Disable
100
High-Z
L
H
H
Read
100
OouT
X
L
Write
Icc
DIN
X
L
L
H
H
H
L
L
!sa
110 PIN
CAPACITANCE (TA =25°C, f =1MHz)
PII_
5-4
Symbol
IIln
Typ
lIax
UnIt
I/O Cepedtance (YIIO z OV)
ClIO
8
pF
Inpul Cepadlance (YIN = OV)
CIN
6
pF
M88464A·1~x/·10LL·X
M88464A·15-x/·15LL·X
RECOMMENDED OPERATING CONDITION
Param...
IIIn
Typ
Vee
4.5
5.0
TA
-40
Symbol
Supply Voltage
Ambient TemperalUre
(ReferencedtoGND)
II..
Unit
5.5
V
85
"C
DC CHARACTERISTICS
(Recommended operating condnlons otherwise noted.)
Param...
Symbol
1IB8464A-1o.XI10LL·X
1IB8464A·15-XI15LL·X
IIIn
Standby Supply Current
....
UnIt
T_t Condition
CS2 S 0.2V or ~1 ~ Vee -O.2V
(with CS2 S 0.2V or CS2 ~ VCO-O.2V)
ISB.
0.2
mA
ISB2
5.0
mA
CSI = Vif or CS2 = VI.
Actiw Supply Current
Icc.
60
mA
V.. = Vif or VI., lour = 0mA
~1 = VI., CS2 = Vif
Operating Supply Current
1CC2
70
mA
Cyde = Min.
Duty = 100%, louT = 0mA
Input Leakage Current
III
-10
10
IIA
VIN = OV to Vee
Output Leakage Currant
ILK!
-50
50
IIA
VK! = OV to Vee
CSI = Vif or CS2 = VI. or
OE = VIH or WE = VI.
Input High Voltage
VIH
2.4
Vee..o.3
Input Low Vohage
Vil
-0.3"
Output High Voltage
VOH
2.4
Output Low Voltage
VOL
0.6
0.4
V
V
V
1DH=-1.0mA
V
IOL=2.1mA
Note: AI voltages are referenced to GND.
" : -3.0V min. for pulse width less \han 20 ns. (Vll min. = -O.3V at DC lewl.)
:rl
Fig. 2 - AC TEST CONDITIONS
+ 5V
• Input Pulse lewis: 0.6V to 2.4V
• Input Pulse Rise & Fall Times: Sns (Transient between 0.6V and 2.4V)
• Timing Reference Lewis Input VII. = 0.6V, VIH = 2.4V
Output VOL = O.BV, VOH = 2.0V
• Output Load
R.
DouT
(110)
Cl"
I
R2
" Inclucing Jig and stray c:apacitance
Cl
Paramelars Measured
Load!
1.BKn
9900
l00pF
except ICLZ, 1IllZ, ICHZ, 10HZ, IWLZ, and IWHZ
Loadll
1.BKn
9900
SpF
ICLZ, IOlZ, ICHZ, 10HZ, IWLZ, and IWHZ
Rl
R2
5·5
MB8464A·1 0-x/·1 OLL·X
MB8464A·15-X/·15LL·X
AC CHARACTERISTICS
(Recommended operating condHlons otherwise noted,)
READ CYCLE *1
Par.met..
Read Cyda lima
Symbol
tRe
MB8464A·1C1-Xl10LL·X
Min
Max
MB8464A·15·Xl15LL·X
Min
Max
150
100
ns
ns
Address Access lima
1M
100
150
CSl Access lima
1AC1
100
150
ns
CS2 Access lima
IAC2
100
150
ns
60
ns
Output Enable to Output Valid
toe
Output Hold from Address Changa
10
10
ns
Chip Select
to to
to to
ICH
tcLZ
10
10
ns
IDLZ
5
5
Output Low-Z '4
Output Enable
Chip Select
Output Low-Z '4
Output High-Z '4
Output Enable
Output High-Z '4
45
ns
tcHZ
40
50
ns
IDHZ
40
50
ns
READ CYCLE TIMING DIAGRAM *1
READ CYCLE 1: ADDRESS CONTROLLED '2
ADDRESS
DouT
~~:~=toH=~===IM==~~tRe~*========~~~--PREVIOUS DATA V~*
XXX X
DATA VALID
READ CYCLE 2 : CS1, CS2 CONTROLLED '3
ADDRESS
~....._ _ _ _ _ _ _ _ _tRC_ _ _ _ _ _ _ _ _>¢,.___
--"'"t..----- IM---~·'
DoUT
~
: Undefined
Nola: "1 WE' is high for Read cycle.
'2 Device is continuously salacI8d, CS1 = OE = VIL, CS2 = VIH.
*3 Address valid prior to or coincident with e51 transition low, CS2 transition high.
'4 Transition is measured at the point of ±5OOmV from steady staIB voltage with specified Load II in Fig. 2.
5-6
Unit
MB8464A-1~XI-10LL-X
MB8464A-15-Xl-15LL-X
AC CHARACTERISTICS
(Recommended operating condHlons otherwise noted.)
WRITE CYCLE ·1·2
P.ram....
Symbol
MB8484A·1O-Xl10Ll·X
Min
M811
MB8464A-15-XI15LL-X
Min
M.II
Unit
Write Cycle Time .,
\We
100
150
na
Address Valid to End of Write
lAW
80
100
ns
Chip Select to End of Write
ICW
80
100
ns
Data V.lid to End 01 Write
tow
40
50
ns
Data Hold Time
IDH
0
0
ns
Write Pulse Width
IWP
60
90
ns
ns
Address Setup Time
lAs
0
0
Write Recovery Time ••
IWR
5
5
ns
Write Enable to Output Low-Z '5
IWLZ
5
S
ns
Write Enable to Output High-Z
WiZ
"5
50
40
ns
WRITE CYCLE TIMING DIAGRAM ·1"2
WRITE CYCLE 1 : WE CONTROLLED
ADDRESS
os,
DIN
DouT
~
:Undaftned
Not.: 1· If OE, OS, and CS2 are in the READ Mode during this period, I/O pins are in the output state so that the input signals 01 opposite
phase to the outputs must not be applied.
2' If CS, goes high or CS2 goes low simultaneously with WE high, the output remains in high impedance state.
3· All write cycle are determined from last address transition to the first address transition of the next address.
4" twR is defined from the end point 01 WRITE Mode.
S· Transition is measured at the point of ±5OOmV from staady atate IIOltage with specified Load II in Fig. 2.
5-7
MB8464A-1G-x/-10LL-X
MB8464A-15-X/-15LL-X
AC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
'WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE 2 : CS1 CONTROLLED *1
~----------------~----------------~
ADDRESS
cS:!
DIN
DouT
~
Nole: *1
HCE, CS:! and WE _ in the READ Mode during this period, 110 pins _ in the outpulslBlB 80 thai the input signals of opposiIB
phase 10 the ouIpUlS musl nol be appled.
5-8
:UncleII.....
MB8464A-1G-Xl-10LL-X
MB8464A-15-Xl-15LL-X
AC CHARACTERISTICS
(Recommended operating condHlons otherwise noted.)
WRITE CYCLE TIMING DIAGRAM
WRITE CYCLE 3 : CS2 CONTROLLED "I
14---------IWC---------.t
ADDRESS
DIN
DoUT
DATAVAUD
HIGH-Z
~
: Unclellned
Note:"1 II OE. CSI and WE are in 1he READ Mode during 1his period. 110 pins are in the output staIB so 1ha1the input signals 01 opposiIB
phase to 1h8 outputs must not be applied.
5-9
MB8464A-1Q-Xl-10LL-X
MB8464A-15-Xl-15LL-X
DATA RETENTION CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
Paramet.,
Data Retention Supply Voltage
Symbol
Min
VDR
2.0
Typ
Standard
Data Retantion SUpply Currenl '1
Operation Recovery Time
UnIt
5.5
V
50
IIA
50
IIA
lOR
LL-Version "2
Data Retention Setup Time
Ma.
toRS
0
ns
IR
IRe
ns
Note: 'I Va; = VOR = 3.0V
CS1 l! VOR -fJ.2V. CS2l! VOR -fJ.2V or CS2:S; 0.2V (a1OS1 CONTROLLED)
CS2 :s; 0.2V (al CS2 CONTROLLED)
'2 lOR max. = 2.011A al VOR = 3.0V. TA = -40"C to +40"C.
DATA RETENTION TIMING
CSl CONTROLLED
Va;
r ~1------::::-~-----t:-1
...,...,..,.;,-'"
///'1
CS1 l! VOR -fJ.2V
,
I
UU12.2V
CS2 CONTROLLED
""
2.2VI~
______'b--
47v\ _____ :~:;:n:
Va;
r-----.l'-L- 1
CS2
5-10
~O'4V
CS2:S;0.2V
0.4V~
MB8464A-10-x/-10LL-X
MB8464A-15-x/-1SLL-X
PACKAGE DIMENSIONS
(SuffiX: P)
28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-28P-M(2)
I
.543±.010
INDEX
I~=====~~==;Z======~IJ''''
.600115.24)TVP
f-------1.407~:~~~135.73~g:;~ )----~.-jl
.06211.58)MAX
.060~0020
.-H-
+0 50
11.52_0. )
.018±.003
10.46±0.08)
" 1988 FUJITSU LIMITED ~
5·11
MB8464A·10-x/·10LL·X
MB8464A·15-x/·15LL·X
PACKAGE DIMENSIONS (Continued)
(SuffiX: P-SK)
28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No. : DIP-28P-M04)
INDEX-1 r¢:!::::!::::::!:::!::::!::::!:::==::!:::~::::!:::::!:::===~::::!::::::!:::!::=:!::::!~1
~;;;;;;:;;:::::::=1::::::..'15oMAX
.260±.010
(6.6±0.25)
INDEX-2
::::::::::::::~1.=39~2~~:=~~~~~(3~5.~36T~~~:~~)~~~~~~~~~~~~~I
.300(7.62)TVP
~
.010±.002
(0.25±0.05)
b!:].207(5.25)MAX
~.118(3.0)MIN
.100(2.54)
TVP
I
.018±.003
(0.46±0.08)
.020(0.51 )MIN
Oimonslono In
o 1988 FWITSU LIMITED D28018S-2.C
5·12
Inchoo (mA_)
MB8464A-10-Xl-10LL-X
MB8464A-15-Xl-15LL-X
PACKAGE DIMENSIONS (Continued)
(SuffiX: PF)
28-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-28P-M02)
.11O( 280)
.
MAX
(SEATED HEIGHT)
1RRR1·'''·&lg",·",glg'iif~l
l
cf
INDEX
.-I-
·465±.012
(11.80±0.30)
.402±.012
(1020±030)
.339±.008
(8.60±0.20)
~::::;:r:;:r::;::;::::;::;:::;:;:y::::;::;::::~-j
TYP
0(0) MIN
(STAND OFF)
018 ±004
1I (0.45±0.10)~05(0.13)®
I
"A"
--
1l--
II
.031±.OO8
(080±0.20)
.006±002
(0.15±0.05)
~------------
Details of "A" part
.008(0.20)
1 - - - - 650(16.51) R E F - - - - I
.007(0.18)
MAX
.027(0.68)
L _____ ~~~ ___ _
Cl1988 FUJITSU LIMITED F280118-3C
5-13
MB8464A-1 D-Xl-1 OLL-X
MB8464A-15-Xl-15LL-X
PACKAGE DIMENSIONS (Continued)
(SuffiX: CV)
32-PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC-32C-A02)
'PIN NO.1 INOEX
C.040(1.02)TYP
(3PLCS)
.360(9.14)TYP
C.015(0.38)TYP
.460(11.68)
TYP
I
n~~~
.065(1.65)
TYP
.045(1.14)
TYP
.085(2.16)
MAX
• Shape of PIN NO.1 INDEX: Subject to change without notice.
01988 FWITSU LlMITEDC32011S-3C
5-14
I
.050±.006
(1.27±0.15)
.300(7.62)TYP
cP
October 1990
Edition 1.0
FUJITSU
DATA SHEET
MB84256A-70-Xl-70LL-Xl-10-Xl-10LL-X
CMOS 256K-BIT LOW-POWER SRAM
32K Words x 8 Bits CMOS Static RAM for Extended
Temperature Operation
The Fujitsu MB84256A·X is a 32.768 words x 8 bits static random access memory
fabricated with a CMOS silicon gate process. The memory uses asynchronous
circuitry and may be maintained in any state for an indefinite period oftime. All pins are
TTL compatible and a single +5 V power supply is required.
The MB84256A·X has low power dissipation. lowcost. and high performance. and it is
ideally suited for use in microprocessor systems and other applications where fast
access time and ease of use are required.
PLASTIC PACKAGE
DIP·28P·M02
•
Organization:
32.768 words x 8 bits
•
Access time:
70 ns max.
100 ns max.
•
Operating temperature: -40°C to +85°C
•
Static operation: no clock required
o
TTL compatible inputs and outputs
•
Three·state outputs
(MB84256A·70/·70LL·X)
(MB84256A·l 0/·1 OLL·X)
PLASTIC PACKAGE
Dlp·28p·M04
•
Single +5 V power supply ±1 0% tolerance
o
Low power consumption:
1.1 mW max. (CMOS standby)
16.5 mW max. (TTL standby)
•
Data retention: 2.0 V min.
•
Standard 28·pin Plastic Packages:
DIP
(600 mil)
MB84256A·xx(LL)P·X
Skinny DIP (300 mil)
MB84256A·xx(LL)PSK·X
SOP
(450 mil)
MB84256A·xx(LL)PF·X
TSOP (Normal bend)
MB84256A·xx(LL)PFTN·X
TSOP (Reverse bend)
MB84256A·xx(LL)PFTR·X
PLASTIC PACKAGE
FPT·28p·M02
PIN ASSIGNMENT
A"
Absolute Maximum Ratings (See Note)
Rating
Supply Voltage
Symbol
Value
-0.5 to +7.0
Vee
Unit
V
Input Voltage
VIN
-0.5 to Vee +0.5
V
Output Voltage
Vvo
-0.5 to Vce +0.5
V
TSIAS
-40 to +85
°C
TSTG
-40 to +125
Temperature Under Bias
Storage Temperature Range
°C
Note: Permanent devioe damage may occur nabsolute maximum ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in the operation
sections of this data sheel Exposure to absolute maximum rating conditions for ex·
tended periods may affect device reliability.
A"
A,
A,
A.
v"
WE
.
A"
A,
A,
A,
DE
A,
A"
A"
A,
C§
Ao
va.
I/O,
vo,
110,
iIO,
110,
GNO
110,
vo,
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However, •
Is advised that normal precatJ:lons be taken to avoid appDcation
of any votIage higher than maximum rated vohages 10 thl8 high
~ancecircult
Copyright © 1990 by FUJITSU LlMIlED and Fujlleu M_nlca. Inc.
5-15
MB84256A-70170LL-X
MB84256A-10/10LL-X
FIg. 1 - MB84256A BLOCK DIAGRAM
---OVcc
•
•
•
ADDRESS
BUFFER
ROW
DECODER
•
•
•
---OGND
256 x 12BxB
MEMORY CELL ARRAY
• • •
CS
•
•
•
ADDRESS
BUFFER
OE
I/O GATE &
COLUMN DECODER
0-----f--11 - - - - - - - 1
CS
WEo---~
.....--r-~
110.
110.
110,
I/O, 110.
110,
110.
110.
TRUTH TABLE
cs
MODE
SUPPLY
CURRENT
110 PIN
X
Not Selected
I.B
High-Z
H
DOUT Disable
Icc
High-Z
L
H
Read
Icc
Dour
X
L
Write
Icc
D'N
OE
WE
H
X
L
H
L
L
CAPACITANCE
Parameler
5-16
(TA
Symbol
Min
Typ
=25"C, f =1UHz)
Max
Unit
VO Capacitance (VI/O = OV)
C'IO
B
pF
Input Capacitance (V,. = OV)
C,.
7
pF
MB84256A-70/70LL-X
MB84256A-1 011 OLL-X
RECOMMENDED OPERATING CONDITION
(Referenced to GND)
Parameter
Symbol
Supply Voltage
Min
Typ
Vee
4.5
5.0
T.
-40
Ambient Temperature
Max
Unit
5.5
V
+85
·C
DC CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
Parameter
MB84256A-70170LLll0110U-X
Test Condition
Symbol
Min
CS ~ Vee -O.2V
ISBt
Unit
Max
0.2
mA
mA
mA
Standby Supply Current
Active Supply Current
Operating Supply
Current
I
I
Is..
CS =V'H
3
lee,
V1N = V1H or V1L
Os = V,~ lOUT = OmA
70
70ns
100ns
Input Leakage Current
lu
Output Leakage Current
lu.o
Input High Voltage
V'H
Input Low Voltage
V'L
90
Cycle = Min.
Duty = 100%
lOUT =OmA
leeo
mA
80
V'N = OV to Vee
-1
1
JIA
VI/O = OV to Vee
Os =V'H
OE = V'H or WE = V'L
-1
1
JIA
2.4
Vee +0.3
V
-0.3"
0.6
V
Output High Voltage
VOH
10H = -1.0mA
Output Low Voltage
VOL
101. = 2.1mA
V
2.4
0.4
V
Note: All wltages are referenosd 10 GND.
": -3.0V min. lor pulse width less than 20 ns.
Fig. 2 - AC TEST CONDITIONS
• Output Load
+5V
)
•
•
Input Pulse Levels:
Input Pulse Rise & Fall Times:
0.4 10 2.6V
5ns (Transient between O.SV and 2.2V)
•
Timing Relerence Levels:
Input:
Output:
~
Dour
(I/O)
±~.
·•
•
,,~
R,
V'L:!).6V. V'H=2.4V
VOL=0.8V. VOH=2.0V
" Including Jig and stray capacitance
R,
Ra
Parameters Measured
Load [
1.8Kn
9900
100pF
except lell. Iou. 10Hz. 10HZ. Iwtz. and IwHz
Load"
1.8Kn
9900
5pF
lou. loll. IeHZ. 10HZ. Iwll. and IwHZ
5-17
MB84256A-70170LL-X
MB84256A-10/10LL-X
AC CHARACTERISTICS
(Recommended operating condHlons otherwise noted.)
READ CYCLE
*1
Parameler
Symbol
MB84256A-70nOLL-X
Min
Read Cycle Time
"'r..."
Max
70
MB84256A-10110LL-X
Min
100
ns
70
100
lAcs
70
100
n8
35
40
ns
Output Hold from Address Change
IoE
IoH
10
10
ns
Chip Select to Output Low-Z "
IeLz
10
10
ns
Oulput Enable 10 Output Low-Z "
IoLz
5
5
Chip Select to Output High-Z "
IcHz
25
40
n8
Output Enable 10 Outpul High-Z "
10Hz
25
40
ns
Address Access Time '.
CS Access Time ,.
Output Enable to Outpul Valid
READ CYCLE 1: ADDRESS CONTROLLED*2
DATA VALID
READ CYCLE 2: CS CONTROLLED'3
ADDRESS
-V. . .________" '_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_--=~_:-----
----"1:""-1----- r...
n8
ns
READ CYCLE TIMING DIAGRAM *1
-----1_0011
HIGH-Z
HIGH-Z
~
Note: '1 WE is high for Read cycle.
__
'2 Device is continuously selected, CS =OE =V,L.
'3 Address valid prior to or coincident with CS transition low.
'4 Transition is measured al the point of ±5oomV from steady state voltage with specified Load II in Fig. 2.
5-18
Unit
lIax
: Undellned
MB84256A-70nOLL-X
MB84256A-10/10LL-X
WRITE CYCLE
"02
Parameter
MB84256A-70170LL-X
Symbol
Min
MB84256A-10/10LL-X
Min
Max
Unit
Mall
Write Cycle TIme ".
!we
70
100
ns
Address Valid to End of Write
t..w
50
80
ns
Chip Select to End of Write
lew
50
80
ns
DalB Valid to End of Write
low
25
40
ns
DalB Hold TIme
to.
0
0
ns
Write Pulse Width
twp
SO
60
ns
Address Setup TIme
t.s
0
ns
Write Recovery Time ".
twA
0
S
5
ns
WE to Output Low-Z "S
twl2
S
5
WE to Output High-Z "s
twHZ
WRITE CYCLE TIMING DIAGRAM
ns
40
25
ns
.1.2
WRITE CYCLE 1 : WE CONTROLLED
!we
'::X
~I..-
ADDRESS
iot-lwR-
t..w
I
lew
"'-" X
"///////
twp
-t..s-
~"'-~
D'N
HIGH Z
XXXXXXX
twHZ
DOOT
I:::::.
-to.~
Iow--
DATA VALID
HIGH-Z
-twl2
HIGH-Z
I
~
X X
:Undellned
Note: "I lICE. CS are in the READ Mode during this period. I/O pins are in the output slBte so that the input signals of opposite phase to
Ihuutputs must not be applied.
_
'2 If CS goes high simultaneously with WE high. the output remains in high impedance slBte.
'3 All write cycles are determined from last address transition to the first address transition of the next address.
"4 twA is defined from the end point of WRITE Mode..
"S Transition is measured at the point of ±500mV from steady slBte vollBge with specified Load I in Fig. 2.
5-19
MB84256A-70170LL-X
MB84256A-10/10LL-X
WRITE CYCLE TIMING DIAGRAM
.1.2
WRITE CYCLE 2: ~ CONTROLLED
!we '.
ADDRESS
~
!"w
IwR ,.
~
lew
\wP
\\\ 1\ \
_Iow_ "///////;
\ '
i--foH-
0 ..
HIGH-Z
HIGH-Z
- leu "5
DOUT
HIGH-Z
DATA VALID
twHZ "5
'X X'
HIGH-Z
~
:Undefined
Nole: 'I II OE, CS are in the READ Mode during Ihis period, 110 pins are in the output stete so that the input signals of opposite phase to
the outputs must not be appUed.
'211 CS goes high simultaneously with WE"high, the output remains in high impedance state.
'3 All write cycles are determined from last address transition to the first address transition of the nexi address.
'41wR is defined from the end point of WRITE Mode ..
'5 Transition is measured at the point of ±5OOmV from steady stete vllltege with specified Load II in Fig. 2.
5-20
MB84256A-70170LL-X
MB84256A-1 0/1 OLL-X
DATA RETENTION CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
Paramel.
Data Retention Supply Voltage "
Symbol
IIln
V""
2.0
Standard
LL-Version
Operation Recovery Time
Note: '1 OS '" V"" -O.2V
'2 VOR = 3.0V. CS?: V"" -O.2V
'3 V"" = 3.0V. T. = 40·C
Max
Unh
5.5
V
0.001
0.05
mA
1
5.0
!IA
lOR
Data Retention Supply Current"
Data Retention Setup Time
Typ
'0
to...
0
ns
'"
IRe
ns
DATA RETENTION TIMING
DATA RETENTION
Vee
5-21
MB84256A·70170LL·X
MB84256A·10/10LL·X
PACKAGE DIMENSIONS
(Suffix: P)
28·LEAD PLASTIC DUAL IN·LlNE PACKAGE
(CASE No.: DIP·28P-M02)
I
.543±.010
INDEX
1~==========~;====;Z===========~I~n~1
I
.039~20 (O.99~.50.
~
,.,=rF<-.=r-.=r..,....,..,...,F=r.........,...,rF'I""1=r~~
.195(4.96)MAX
~"18(3'OO)M'N
.0201O.S1 )MIN
Dimensions in
©1988 FUJITSU LIMITED D28006S·2C
inches (millimeters)
(Suffix: P-SK)
28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-Z8P-M04)
,::::i>:II :0: ::::II :: :0: :
.034~g'2
.oso~g'2
10.86~g·301
11.27~g301
Ch].207IS.2SI MAX
+.11813.001 MIN
.OSOII.27)
MAX
© 1988 FUJITSU LIMITED D28018S-2C
5-22
.02010.S11 MIN
Dimensions in
inches (millimeters)
MB84256A-70/70LL-X
MB84256A-1 0/1 OLL-X
PACKAGE DIMENSIONS (Continued)
(Suffix: PF)
28-LEAD PLASTIC FLAT PACKAGE
.110(2BOI MAX
t----t"'(S-;:-EA:-::T:;:;ED~H~EI:::cGHc::T)
(Case No.: FPT-28P-M02)
OiO) MIN
1RRRI''''&W'''.'''8l!'iifli
(STAND OFF)
l
·465±.OI2
(1'.BO±O.30)
.339 ± .OOB
(B.60±0.20)
cf
INDEX
.402±.012
(l0.20±0.30)
ll!i=iFir=n=n=n==n=n=n=n=;;=n=;rn?J~
01B ±.004
1I·(0.45
± 0.10) [$/ ¢.005(0.13) ~
.050(1.27)
TYP
··A"
J
"""'---+
[
i ,\
Jl.lLl.U 1n rn ri !g
1L =
.031±.00B
(0.BO±0.20)
.006±.002
(0.15 ± 0.05)
r------------,
: Details of . 'A' . part
:
I
I
.00B(0.20)
I
I
.004(0.10)
/
1
.024(0.60)
f----.650(16.51)
© 1990 FUJITSU LIMITED F28011S-4C
REF--~-l
007(0.1 B)
MAX
.027(0.6B)
,
----~~~----;
Dimensions in
inches (millimeters)
5-23
MB84256A-70/70LL-X
MB84256A-10/10LL-X
PACKAGE DIMENSIONS (Continued)
(Suffix: PFTN)
PIN ASSIGNMENT
(NORMAL BEND)
.....
6E
..."
III
.........
110,
....
IIOa
We
IIOa
IIOa
Vee
A"
A"
GND
I/O,
lIDs
A,
110,
....
I/O,
....
A.
....
FPT-28P-M03
....
...,
....
28-LEAD PLASTIC FLAT PACKAGE
(Case No.: FPT-28P-M03)
: :lP
i--------------l
@.
I
@
'=rr====="i\d
INDEX
LEAD No.
o
.004(0.10)
.488±.008
(12.40±0.20)
© 1990 FUJITSU LIMITED F28018S-3C
5-24
.IIL
i
~
.315±. 008
(8.00±0.20)
1
.281 (7.1S)
REF
.006±.002
(0. lS±O.OS)
oiL ___ ___________________ \ld
~=I
I
I
006(015) I
iL ______________
010(02:~X
.528±.008
(13.40±0.20)
465+.008
(1180±020)
01~~~35)_:
I
I
I
006(015)
t-
1
Details of "A" part
.0217 (O.SS)
TYP
.02 0+.004
(0.SO±0.10)
II
.OSO (1.27) MAX
(SEATED HEIGHT)
I
1
.008±.004
(0.20±0.10)
0(0) MIN
(STAND OFF)
-$1
.004(009)
iMl
Dimensions in
inches (millimeters)
1
MB84256A-70/70LL-X
MB84256A-10110LL-X
PACKAGE DIMENSIONS (Continued)
(Suffix: PFTR)
PIN ASSIGNMENT
(REVERSE BEND)
A,
...
A,
A,
A,
""
A"
110,
tKl,
110,
GNO
A,
A"
A"
V"
110.
WE
uo.
A"
tKl,
110,
110,
A"
A"
A"
DE
FPT-28P-M04
CS
A"
BOTTOM VIEW
28-LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT -28P-M04)
'--De~il;~~-::-~~--i
:
I
:
.014(0.35) I
II
MAX
:
MAX
.010(0.25)
I
1
~=tt006(015)
~1-
I
I
1006(0. ~5)
:
I
L ____________ ~
.4BB±.OOB
.020±.004
.2Bl (7.151
REF
.0217(0.55)
TYP
.008+.004
11~0.20 ± 0.1 01
:'171.004 (0.091 Q'.lJ
-1
J
J
.315± .008
(8.00±0.201
©1990 FUJITSU LIMITED F28019S-3C
t.050(1.27) MAX
(SEATED HEIGHT)
0(01 MIN
(STAND OFF)
Dimensions in
inches (millimeters)
5-25
Extended Temperature Range SRAMs
5-26
Static RAM Data Book
Section 6
Quality and Reliability -
I
At a Glance
Page
11118
6-3
6-4
Quality Control al Fujitsu
Quality Control Processes al Fujitsu
6-1
Quality and Reliability
6-2
Static RAM Data Book
Static RAM Data Book
Quality and Reliability
Quality Control at Fujitsu
Built-In QualHy and Reliability
Fujitsu's integrated circuits work. The reason they work is Fujitsu's
single-minded approach to built-in quality and reliability, and its dedication
to providing components and systems that meet exacting requirements
allowing no room for failure.
Fujitsu's philosophy is to build quality and reliability into every step of the
manufacturing process. Each design and process is scrutinized by
individuals and teams of professionals dedicated to perfection.
The quest for perfection does not end when the product leaves the Fujitsu
factory. It extends to the customer's factory as well, where integrated
circuits are subsystems of the customer's final product. Fujitsu emphasizes
meticulous interaction between the individuals who deSign, manufacture,
evaluate, sell, and use its products.
Quality control for all Fujitsu products is an integrated process that crosses
all lines of the manufacturing cycle. The quality control process begins with
inspection of all incoming raw materials and ends with shipping and
reliabiUty tests following final test of the finished product. Prior to warehousing, Fujitsu products have been subjected to the scrutiny of man,
machine, and technology, and are ready to serve the customer in the
designated application.
6·3
Static RAM Data Book
Quality and Reliability
Quality Control Processes at Fujitsu
Proce..
Inspection of Incoming Material
Check Item.
Wafer Processing
Inspection of Wefers,
Masks, Packages, Piece
Diffusion/lon Implantation
Parts, Chemicals, Etc.
Wafer Surface Inspection and
Photoetching
Sample Tests of Thickness,
Surface Resistance, Diffusion
Deplh, Electrical Parameters, and Doping
Wafer Surface and Pattern Inspection
Wafer Surface Inspection,
Passivation (Insulating Layer Formation)
Monitor Test of Film Thickness
Probing Test
Wafer Surface Inspection,
Monitor Test of Film Thickness
Wafer Shipping Inspection
Test of Electrical Characteristics, Stress Test
Dicing (CHIP Saparation)
CHIP Salection
Wafer Surface and Pattem
Sampling Inspection
CHIP Shipping Inspection
Assembly
Die Bonding
Sample Surface Inspection
Bond-Wetting and Surface Inspection, Monitor Test 01 I
n
for Machine Calibration
Bond-Position and Surface Inspection, Sample Wire Bond Strength Test,
Monitor Test of Sample run for Machine Calibration
Internal Visual Inspection
Pre-Cap Visual
Inspection
Internal Sampling VISual Inspection
Continued on next page
6-4
Internal Merchant
Inspection
Static RAM Data Book
Quality and Reliability
Quality Control Processes at Fujitsu (Continued)
Sealing or Molding
Aging (After Encapsulation)
Leak Test (Hennetic Package Only)
Fine and Gross Leak Tests
External Sampling Visual Inspection
External Sampling Visual Inspection
External Sampling Visual Inspection
External Visual Inspection
External Mechanical Inspection
External Sampling Visual Inspection
Shipping Tests
Test of ACIOC Characteristics and Functions
HeRneticity (Fine and Gross Leak Tests). External and Marking Inspection~
Electrical Characteristics Tests. All Sampling Tests
U
Endurance and Environmental Tests
0'
Reliability Tests
Lot TestslPeriodic Tests
Legend:
o
o
IQJ
<>
Production Process
Test/Inspection
Production Process
and Test/Inspection
QC Gate (Sampling)
Note:
The flow sequence may vary slighUy
with individual product type.
6-5
Quality and Reliability
6-6
Static RAM Data Book
Section 7
Ordering and Package Information - At a Glance
Page rnle
I
I
7-3
7-3
7-4
7-6
SRAM Ie Package MarkIng
Part Number
Ie Package MarkIng and Ordering Information - Plastic
Ie Package Marking and Ordering Information - Ceramic
l1li
7-1
Ordering and Package Information
7-2
Static RAM Data Book
Static RAM Data Book
Ordering and Package Information
SRAM Ie Package Marking
Fujitsu Logo
Die Revision Designator
Note:
Marking formals may vary,
depending on Ihe procfuct. The country of
origin appears on 811 finished parts.
Part Number
Low Power Designator (When applicable)
Speed Designator (When applicable)
Device Type
Manufacturer Designator
MB
MBM
Note:
Identifies an IC designed and manufactured by Fuj~su w~h a Fujbu-designated device number.
Identifies an IC designed and manufactured by Fujbu w~h a device number, designated by the industry, that
is the industry standard number.
Please contac\ your nearest Fujitsu sales ofti08, representative, or disbibulllr for exact part number/order information.
7·3
Ordering and Package Information
Static RAM Data Book
Ie Package Marking and Ordering Information
This ordering information is presented as a guide to Fujitsu's package options. The codes shown here indicate the current selections available for Ie packaging. Since device packages are subject to changes and updates, you should contact your closest
Fujitsu Sales Office or Representative for the latest package information.
IDI
1Package ordering code appears as a suffix to Fujitsu's part number and speed designator (MBXXXXX-XXPKG).
Ipackage codes in the U.S.A do not use the "-"; e.g., PSK is the same as P-SK.
aM Is used on bipolar devices only.
Contlnu«l",nextpage
7-4
OrdlJring and PackagB Information
Static RAM Data Book
Ie Package Marking and Ordering Information (Continued)
Fujitsu
Ordering
Code1'!
Dual In-line Package, 400 mil Wide
Slim DIP
Z-SLorZ
T-SLorT
C-SLorC
Dual In-line Package, 300 mil Wide
Skinny DIP
Z-SKorZ
T-SK or T
C-SKorC
Dual In-line Package, 1.778 mm Lead P~ch
Shrink DIP
Quad Flat, Gullwing Lead, Package with
CERPACK
QFP
ZFLorZF
Quad Flat, Gullwing Lead, Package w~h Metal
Seal
QFP
CFLorCF
Small Outline, Gullwing Lead, Package with
CERPACK
SOP
ZFLorZF
Small Outline, Gullwing Lead, Package with Metal
Seal
SOP
CFLorCF
III
lPackage ordering code appears as a suffix to Fujitsu's part number and speed designator (MBXXXXX-XXPKG)
Ipackage codes in the U.S.A do not use the "-"; e.g., ZSK is the same as Z-SK.
31
.f
CEROIP
\
7-5
Ordering and Package Infonnation
7-6
Static RAM Data Book
Section 8
Sales Information - At a Glance
I
Page
l1de
~
Introduction 10 Fujitsu
Fujitsu Umited (Japan)
Fujitsu Microeleclronics, Inc. (U.S.A.)
Fujitsu Electronic Devices Europe
Fujitsu Microeleclronics Asia PTE lid. (Singapore)
Integrated CilQlits Corporate Headqual1llrs - Worldwide
FMI Sales Offices for Nor1h and Sou1h America
FMI Representstiws-USA
FMI Representstiws-Canada, Mexico, and Puerto Rico
FMI Dis1ribulOrs - USA
FMIDis1ributors-Cenede
FMG, FMl, and FMIL Sales Offices for Europe
FMG, FMl, and FMIL Dis1ribulOrs - Europe
FMAP Sales Offices lor Asia, Australia and Oceania
FMAP Represenlaliws - Asia and Aus1ralia
FMAP Dis1ribulOrs - Asia
~
8-4
8-6
8-6
8-9
8-10
8-11
8-13
8-14
8-18
8-19
8-20
8-22
8-23
8-24
8·1
5ams Information
8-2
Static RAN Data Book
Sales Information
Static RAM Data Book
Introduction to Fujitsu
FujHsu Limited (Japan)
Fujitsu Umited was founded as a telecommunications equipment
manufacturer in 1935, and today is not only one of Japan's leading
telecommunications companies, but also one of the world's largest
computer manufacturers.
This leadership has resulted, at least in part, from the superb quality of the
company's semiconductors and electronic components. Manufactured by
the company's Electronics Devices Operations Group, these vital
electronic devices also contribute to the high reliability and performance of
products made by many other manufacturers around the world.
Today, Fujitsu is one of the world's top manufacturers of semiconductors
and electronic components. In Japan, Fujitsu's R&D laboratories for
semiconductor and electronic components are situated in Kawasaki and
Mie, and manufacturing works are located in Iwate, Aizu, Wakamatsu and
Suzaka. Fujitsu also has six affiliated manufacturing works in the country.
Overseas facilities in the U.S, Europe, and Asia also help to meet the
growing global demand for Fujitsu semiconductors and electronic
components.
Fujitsu enforces strict quality control at all stages of production, from
materials selection through manufacturing to final testing. As a result,
Fujitsu's electronic devices are known for their extremely high reliability
and excellent cost-to-performance ratio.
Fujitsu manufactures a full line of semiconductors and electronic components to meet the diverse applications of a wide v~ety of customers.
Backed by Fujitsu's extensive R&D commitment equal to over 10 percent
of annual sales, Fujitsu's electronic devices stay on the cutting edge of
electronics technology.
Continued on next pag9
8-3
Sales Information
Static RAM Data Book
Introduction to Fujitsu
Fujitsu Microelectronics, Inc. (U.S.A.)
Fujitsu Microeledronics, Inc. (FMI), with headquarters in San Jose,
CaUfomia, was established in 1979 as a wholly-owned Fujitsu Limited
subsidiary for the marketing, sales, and distribution of Fujitsu integrated
circuit and component products. Since 1979, FMI has grown to three
marketing divisions, two manufacturing divisions and a subsidiary. FMI
offers a complete array of semiconductor products for its customers
throughout North and South America.
The AdvanCed Products Division (APD) is responsible for designing and
selling a full line of SPARC processors, peripheral chips, and the
EtherSta..... LAN controller that it designed. The EtherStar LAN controller is
the first VLSI device to integrate both StarLAN"M and Ethernet® protocols
into one device. The core of APD's EtherStar chip was the result of a
cooperative venture with Ungerrnann-Bass.
The Microwave and Optoeledronics Division (MOD) markets GaAs FETs
and FET power amplifiers, tightwave and microwave devices, optical
devices, emitters, and SI transistors.
The largest FMI marketing division is the Integrated Circuits Division (ICD)
which markets the following standard devices, components, and ASICs.
Memory Products
DRAMs
EPROMs
EEPROMs
NOVRAMs
CMOS masked ROMs
CMOSSRAMs
BiCMOS SRAMs
Bipolar PROMs
ECLRAMs
STRAMs (self-timed RAM)
Hi-Rei PROMs and SRAMs
Memory cards
Memory modules
Telecommunication Products
PLLs
Prescalers
Piezoelectric devices
CODECs
VCOS
Telephone ICs
Modems
Continued on next page
8·4
Static RAM Data Book
Sales Information
Introduction to Fujitsu
Microprocessor Products
4-bit microcontrollers
DSPs
Logic Products
Standard and ultra high-speed ECl
Translator circuits
Interface devices
Analog Products
UnearlCs
Transistors
Hybrid Products
Thick- and Thin-film
CustOIn modules
Stepper motor drivers
Special Purpose Controller
Products
ASIC Products
SCSI controllers
Serial protocol controllers
Video controllers (TV text,
CRT, and picture-In-picture)
CMOS gate arrays
ECl gate arrays
BiCMOS gate arrays
GaAs gate arrays
CMOS standard cells
ASIC GalieryTM (SuperMacrosn., Compiled Cells)
ASICOpen"" CAD Software Framework (ViewCADTM,
a design and verification tool that integrates with
third-party CAD tools)
Third-party EWS (engineering workstation) support
Customer support and customer training for ASIC products are available
through the following FMI design centers:
San Jose
Dallas
Atlanta
Gresham
Chicago
Boston
FMl's manufacturing divisions are in San Diego, California and Gresham,
Oregon. The San Diego Manufacturing Division (SMD) assembles and
tests memory devices. The Gresham Manufacturing Division (GMD) began
manufacturing in 1988. GMD fabricates wafers, and produces ASIC
products and DRAM memories. This facility, when completed, will have
one million square feet of manufacturlng-the largest Fujitsu manufacturIng plant outside Japan.
FMl's subsidiary, FujHsu Component of America, markets connectors,
keyboards, thermal printers, plasma displays, and relays.
Continued on next page
8-5
Static RAM Data Book
Sales Information
Introduction to Fujitsu
Fujitsu Electronic Devices Europe:
Fujitsu Mlkroelektronlk GmbH (RIG), West Getmany
Fujitsu Microelectronics Llmltsd (FML), U.K.
Fujitsu Microelectronics ltalla S.R.L (FMIL), Italy
Fujitsu Microelectronics Ireland, Ltd. (FME), Ireland
Fujitsu Mikroelektronik GmbH (FMG) was established in June 1980 in
Frankfurt, West Gennany, as Fujitsu's European headquarters and is a
totally owned subsidiary of Fujitsu Umited, Tokyo. Fujitsu Microelectronics
Umited (FML) is a sister company based In Maidenhead, England and
dedicated to serving the U.K., Ireland, and Scandanavia. Fujitsu Microelectronics ltalia (FMIL) is based In Milan, Italy and serves Italy, Spain,
Portugal, and the rest of Southem Europe. Together, FMG, FML, and
FMIL supply the European market with a full range Of semiconductors and
electronic components. Sales offices are located in Munich, Frankfurt,
Stuttgart, Paris, Eindhoven, Milan, Maidenhead, and Stockholm.
Fujitsu Microelectronics Ireland, Ud. (FME) was established in 1980, in
Dublin, Ireland, as Fujitsu's European Assembly Center for integrated
circuits. FME produces DRAMs, EPROMs, and other LSI memory
products.
Fujitsu has two European VLSI design centers, both in the U.K. The
Manchester Design Center, in operation since 1983, is equipped with two
mainframe computers and is Inked by satelUte to production plants in
Japan and the U.S. Staffed with a team of experienced engineers, the
center is involved In the design of VLSI standard products, SuperMacros,
CAD tools and ASICs. A second design center was set up in London in
1990 for deSigning telecommunication ICs. Additionally, Fujitsu offers a
network of 17 ASIC design centers in eight European countries.
Fujitsu has further demonstrated Its commitment to the European market
by commencing construction of a full wafer fabrication plant in Durham in
the North of England. The new plant is due to start production of 4
megabyte DRAMs and ASICs in 1991.
Continued on next page
8-6
Sales Information
Static RAM Data Book
Introduction to Fujitsu
The range of semiconductor products offered by FMG, FMl, and FMll for
the European market includes:
Memory Products
DRAMs
SRAMs
EPROMs
EEPROMs
Mask ROMs
Bipolar PROMs
Video RAMs
EClRAMs
Memory modules
Memory cards
ASIC Products
CMOS gate arrays
BiCMOS gate arrays
Bipolar (ECl) gate arrays
Gallium Arsenide gate arrays
CMOS standard cells
ECl gate masterslice devices
Wide range of ASIC design software
MIcroprocessor Products
4-Bit Microcontrollers
4- 8- and 16-bit F2MC flexible Microcontrollers
32-Bit SPARC"" RISC microprocessors
32-Bit GMICRO"" TRON-based CISC microprocessors
TelecommunIcation Products
Prescalers
Plls
CODECs
LAN devices
DSPs
SCSI and LAN devices
ISDN products
Telecom devices for the GSM
Pan-European digital cellular telephone system.
Analog Products
OPAmps
Comparators
ND and D/A Converters
Application Specific ICs
The range of electronic components offered by FMG, FMl, and FMll
incudes relays, connectors, keyboards, thermal printers, plasma displays,
liquid crystal displays, hybrid ICs, and piezoelectric devices.
Continued on next page
8-7
Sales Information
Static RAM Data Book
Introduction to Fujitsu
Fujitsu Microelectronics Asia PTE Ltd. (Singapore)
Fujitsu Microelectronics Asia PTE ltd. (FMAP) opened in August 1986, in
Hong Kong, as a wholly-owned Fujitsu subsidiary for sales of electronic
devices to the Asian, AustraUan, and Southwest Pacific mar1196
Technical Marketing, Inc.
2901 Wilcrest Drive
Suite 139
Houston, TX 77042
Tel: (713) 783-4497
FAX: (713) 783-5307
Technical Marketing, Inc.
1315 Sam Bess Circle
Suite B-3
Round Rock, TX 78681
Tel: (512) 244-2291
FAX: (512)338-1596
Utah
R-Squared Marketing
340 W. 500 South
Suite 105
Salt Lake City, UT 84101
Tel: (801) 595- 63044
(314)291-4650
Bell Microproducts
16 Upton Drive
Wilmington, MA01887
(508)658-0222
Interface Electronic Corp.
228 South Street
Hopkinton, MA 01748
(508)435-6858
Marshallinduslries
33 Upton Drive
Wilmington, MA 01887
(508)658-0810
Milgray Electronics
187 BaUardvale Street
Wilmington, MAOI887
(508)657-5900
Vantage Components, Inc.
200 Bulfinch Drive
Andover, MA 01810
(508)687-3900
Marshallinduslries
6990 Corporate Drive
Indianapolis, IN 46278
(317)297-0483
Western Microtechnology
20 Blanchard Road
9 Corporate Place
Burlington, MA 01803
(617) 273-2800
Kansas
Michigan
Marshallinduslries
10413 W. 84th Terrace
Lenexa, KS66214
(913) 492-3121
Marshallinduslries
31067 Schoolcraft Road
Uvonia, MI48150
(313)525-5850
Milgray ElecIronics
Replron Electronics
34403 Glendale
Uvonia, M148150
(313)525-2700
6400 Glenwood
Suite 313
Over1and Perk, KS 66202
(913)236-8800
Reptron Electronics
5929 Baker Road
Suite 360
Minnetonka, MN 55345
(612)938-3995
Missouri
Marshall Industries
New Jersey
Marshall Industries
101 Fairfield Road
Fairfield, NJ 07006
(201)882-0020
Marshall Industries
158 Gaither Drive
MI. Laurel, NJ 08054
(609)234-9100
Milgray Electronics
3001 Greentree Exec. Campus
SuiteC
Marlton, NJ 08053
(609)983--5010
Milgray Electronics
1055 Parsippany Blvd.
Parsippany, NJ 07054
(201)335-1766
Vantage Components, Inc.
23 Sebago Street
P.O. Box 2939
Clifton, NJ07013
(201) n7-4100
Westem Microtechnology, Inc.
387 Passaic Avenue
Fairfield, NJ 07006
(201)882-4999
8-15
Static RAM Data Book
Sales Information
FMI Distributors - USA (Continued)
New York
Marshallinduslries
275 Oser Avenue
Hauppauge, NY 11788
(516) 273-2424
Marshallinduslries
129 Brown Slreet
Johnson City, NY 13790
(607) 798-1611
Marshall Industries
1250 Scottsville Road
Roches1llr, NY 14624
(716) 235-7620
Mast Distributors
71~ Union Parllway
Ronkonkoma, NY 11779
(516) 471-4422
M'ICI'OGenesis
90-10 Colin Driw
Holbrook, NY 11741
(516)472-6000
Milgray Electronics
77 Schmitt BlIId.
Farmingdale, NY 11735
(516) 42G-9800
Milgray ElecIlOnics
1170 Pittsford VielDr Road
Pittsford, NY 14534
(716) 381-9700
Vantage Components, Inc.
1056 West Jericho Turnpike
Smithtown, NY 11787
(516) 543-2000
HI
North Carolina
Marshall Industries
5224 Greens Dalry Road
Raleigh, NC 27604
(919) 878-9882
ReplrOn ElecIrOnics
5954-A Six Fork Road
Raleigh, NC 27609
(919) 870-5189
Ohio
Marshallinduslries
3520 Park Cen1llr Drive
Davton, OH 45414
(513) 898-4480
Marshall Industries
30700 Bain Bridge Road
Unit A
Solon, OH 44139
(216)248-1788
8·16
Milgray ElecllOnics
6156 Rockside Road
Clewland, OH 44131
(216)447-1520
RepIlU!1 ElecInlnics
404 E. Wilson Bridge Road
Sui1llA
WorIhinglDn, OH 43085
(614)4~75
Oklahoma
Radio Inc.
1000 South Main
Tulsa,OK74119
(918) 587-9123
Oregon
Marshallinduslries
9705 S.W. Gemin Drive
Beaverton, OR 97005
(503)~
Western Microtechnology
1800 N.W. 1691h Place
Sui1llB300
Beaverton, OR 97006
(503) 629-2082
Pennsylvania
Interface Electronic Corp.
7 Great Valley Parllway
MaJvem, PA 19355
(215) 889-2060
Marshallinduslries
401 Parkway View Dr.
Pittsburg, PA 15205
(412) 788-0441
Texas
Insight ElecIlOnics, Inc.
1778 Plano Road
Sui1ll320
Richardson, TX 75081
(214) 783-4800
Marshallinduslries
8504 Cross Park Drive
Austin, TX 78754
(512)837-1991
Marshallinduslries
2045 Chenault
Carro.IOn, TX 75006
(214) 233-6200
Marshall Industries
1200 Barranca
Bldg. 5, Sui1ll A
EI Paso, TX 79935
(915)~706
Marshall Industries
2635 Soulh Highway 77
Harlingen, TX 78550
(512) 421-4621
Marshall Industries
7250 Langtry
HouslDn, TX 77040
(713) 995-9200
Milgray ElecIrOnics
16610 N. Dallas Pkwy
Suite 1300
DaUas, TX 75248
(214)248-1603
Wes1llm Micro18Chnology, Inc.
2545 Tarpley Road
Suite 151
Dallas, TX 75006
(214) 416-0103
Western Micro18Chnology, Inc.
2500 Wilcrest, 3rd Roor
HouslDn, TX 77042
(713) 954-4850
Utah
Marshall Industries
466 Lawndale Drive
Sui1llC
Salt Lake City, UT 84115
(801)485-1561
Milgray Electronics
4190S. Highland Driw
Sui1ll102
Salt Lake City, UT 84124
(801) 272-4999
Waahlngton
Insight Electronics, Inc.
12OO21151h Avenue, NE
Kirkland, WA 98034
(206)820-8100
Marshall Industries
11715 N. Creek Parllway
Sui1ll112
Bolhwell, WA 9801
(206) 488-5747
Sales Information
Static RAM Data Book
FMI Distributors - USA (Continued)
Washington (Continued)
Wisconsin
Marshallinduslries
15359 NE 90th Street
Redmond, WA 98052
(206) 869-7557
Classic Components
2925 S. l60th Street
New Berfin, WI 53151
(414) 786-5300
Western Microtechnology
14636 N.E. 95th Street
Redmond, WA 98052
(206) 881-6737
Marsh Electronics
1563 S. 101s1 Street
Milwaukee, WI 53214
(414)4~0
Marshallinduslries
20900 Swenson Driw
Suite 150
Waukesha, WI 53186
(414) 797-6400
8·17
Sa/ss Information
Static RAM Data Book
FMI Distributors - Canada
BrHlsh Columbia
MarshaH Incllstries
auebec
ITT Industries
3455 Gardner Court
Burnaby, B.C. V5G 4J7
(604) 291-as66
4 Paget Road
Units 10& 11
Bramton, ON 16T 5G3
Marshalllncllstries
148 Brunswick Blw.
Poinlll Claire, au H9R SP9
(S14) 683-9440
Active Components
1695 Boundry Road
Vancouver, Be. V5K 4X7
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8·24
Section 9
Design Information - At a Glance
9-3
Appendix 1.
Design Applications. Jnlllmally limed RAMs build
fast writable c:on/rr)/ stores
9-8
Appendix 2.
Application Now: SBparaIB Deta Inputs and OutpuIS, SRAMs Provide New Artlhitsctural Solutions
9-27
AppendixS.
Application Now: Fast SRAMs in Zero Wait-Stats
AIrImoIy JnlBtfaces
9-37
Appendix 4.
CI'III8 Reference Guide for High-speed (CMOS,
BiCMOS) SRAMs
9-1
Design Information
9-2
Static RAM Data Book
Appendix 1
Self-Timed RAMs
9-3
SsH-rlfTled RAMs
9-4
StatIc RAM Data Book
DESIGN APPLICATIONS
Internally timed RAMs build
fast writable control stores
Mohammad Shakaib Iqbal
Fujitsu Microelectronics Inc" 3545 N. First St., San Jose, CA 95134-1804; (408) 922-9000.
The increasing speed of mainframes and minicomputers produces a need for memory access even
faster than that supplied by ECL RAMs. One way
to cut into IS-ns memory-access times is through
process improvements, but this avenue quickly
reaches its limits. Another method is to rework tbe
architecture of the writable control store, which
holds the microinstructions that implement the
machine's assembly-language instructions. For instance, adding registers in the address and data
lines to the control
memory causes a pipeline effect that speeds
Create faster comput- up
both read and write
ers without sacrificing operations.
board space. SelfBut the number of
timed RAMs do the
registers needed to process the size of control
trick, replacing stanwords in some of todard ECl RAMs in
day's minicomputers
control memories.
can be prohibitive. The
solution lies in the new
~
I
I
Program
status
word
Arithmetic
logic unit
II
self-timed RAMs (STRAMs)-pipelined memory
devices containing on-board registers or latches, as
well as a write-pulse generator. STRAMs not only
shrink access times to 7 ns, but they also cut board
space and reduce the number of lengthy connections between discrete parts. The latter is important
because at ECL speeds these leads act as transmission lines, generating reflections and crosstalk.
To better understand how a STRAM can help a
designer perform a specific task, consider a minicomputer's basic architecture. Both mainframes
and minicomputers use microprogrammed processors in their CPUs. A microprogram is a flexible
way to generate the control signals that implement
assembly language. These control sequences or microinstructions reside in a control memory, usually
a set of PROMs addressed by a microprogram
counter.
In a microprogrammable machine, however, the
control memory consists of fast RAMs, so a user
can alter the control signals and modify the instructions. For example, a typical minicomputer CPU
: Accumulator
I
1
2
3
.
Generalpurpose
registers
16
Internal bus
I
~
Control
unit
Instruction
register
I
I
I
Memory
signals
Memory
function
complete
I
1
Program
counter
! !
Memory
address register
l
I
I
I
!
Memory
data register
I
l
1. In a typical microprogrammed CPU, a control unit holds a control word employed for register
loading, identification, and reading.
Reprinted with permiSSion from ELECTRONIC DESIGN - August 25, 1988
Copyright 1988 VNU Business Publications, Inc.
9-5
DESIGN APPLICATIONS • Increase memory speed
contains 12 kbytes of microprogrammable memory in its
writable control store to diagnose problems, perform certain instructions, and change the microcode. For the sophisticated user, the CPU has an extra 12 kbytes of writable control store. This architecture lets a user chan~e the
way the computer responds to machine-language instructions.
A microprogrammable CPU usually contains generalpurpose registers, an instruction register, a memory data
register, a memory address register, a program counter, a
16-function arithmetic logic unit, a temporary register
called an accumulator, and a control unit (Fig. 1). The
memory data register holds the data word to be sent to the
memory, and the memory address register holds the address to the memory. The control unit sends a control
word for register identification, loading, and reading. It
generates signals like memory read and write, accumulator read and load, and ALU operations. The accumulator
holds the ALU inputs and outputs.
The writable control store is implemented within the
System data
Systein
bus
address
bus
Instruction
decoder
Control
signals
To registers
ToALU
2. Adding registers to a writable control store's data
and address paths speeds up the computer but at
a steep price In board space. An alternative Is to
replace the components In the highlighted area
with a self-timed RAM, which contains a write-pulse
generator and registers.
9·6
control unit (Fig. 2). Its task is to generate the correct sequence of steps to execute the assembly-language instruction. Included in the-controller are a starting address generator, microprogram counter, control memory, and
control register. The control memory, addressed by the
microprogram counter, stores the microinstructions. The
control register holds the control word.
The process begins when the CPU fetches a machinelanguage instruction from -the main memory and loads it
into the instruction register. MiCroprogramming then
takes over. The instruction register puts the instruction
into the starting address generator, which decodes the address of the first microinstruction in the control memory
and loads this address into the microprogram counter.
Next, the contents of the control memory pointed to by
the microprogram counter are fetched and loaded into
the control-word register. The microprogram counter is
then updated to point to the next microinstruction in the
desired sequence.
Minicomputers have control words 10 to 100 bits long.
Each bit placed into the control-word register controls a
part of the computer, including the instruction register,
program counter, accumulator, memory, and ALU control. Hence, each bit is connected to a specific destination.
The various control signals open or close data paths to
these destinations or instruct the locations to perform an
operation. For example, to transfer data between two registers, a control signal must instruct the source register to
place the data on the bus, and a second signal must tell the
destination register to read the data on the bus.
If the control store is writable, there must be a multiplexer between the microprogram counter and the control memory, because the address can come from either
the microprogram counter or the system address bus. The
system address bus's only task is to write to the control
memory.
This is where a register between the counter and control memory input is beneficial. While the microprogram
counter is generating an address during a read cycle
(when it increments), the previous address can be in the
register pointing to the control memory. That's the desired pipeline effect.
The computer gains a similar advantage during write
_cycles-that is, when the instructions in the microprogram are being altered. In this case, the new data is carried over the system bus and written in the control memory. If the memory consists of standard ECL RAMs and
no registers, the address-hold time requirement will slow
down the process.
Adding a register again creates a pipeline effect because the address and the data are both placed in the register. The address remains valid on the register's outputs
until a new clock edge arrives, bringing a new address
from the microprogram counter. The data and the address inputs are placed in the register on the true ongoing
edge of the clock. The Write Enable signal is also placed
in the register (Fig. 3a).
The several nanoseconds saved on each read and write
cycle can add up to a considerable speed increase during
normal computer operation. As noted, using STRAMs
gives the designer this speed boost without the space penalty exacted by discrete registers.
In the example noted, a totally pipelined architecture
was desired, so the registered STRAMs were used. This
configuration yields the highest bit rate at the system level because the succeeding cycle can begin while the output
signal is slewing and propagating. The data isn't available
at the outputs until the next clock edge.
In some computers, however, the control store might
have to read data from the RAM in one memory cycle.
When this is the case, the control memory's inputs must
have latches to hold the input data and address for saving
the hold times. The output lines are also latched so that
data can be placed on the data bus in one cycle. A latched
STRAM fills the bill. This device's timing diagrams show
that in read cycles the data is read in the same memory
cycle (Fig. 3b).
In a STRAM, the Address, Data In, Chip Enable, and
Write Enable signals are latched into the on-chip registers
or latches by the true-going edge or level of the clock
pulse at the start of the memory cycle. All these signals
remain valid throughout the memory cycle until the next
true-going clock edge or level. As a result, signals need
not be held stable during the entire cycle. They can slew
down during one cycle to prepare for the next one.
It's advantageous to trigger the write operation at the
true going clock edge by latching the Address, Data, and
Write Enable signals. Then the new Data and Address
signals can be placed at the inputs while the old data is being written to the RAM cells. Also, this technique eliminates address skew because all the timing is clock-edge
driven.
The basic difference between the registered and the
latched STRAM, in fact, is that the former is clock-edge
sensitive, while the latter is level sensitive (Fig. 4). During
a registered STRAM's read cycle, the data is available in
the next clock cycle. For the latched STRAM, the data is
available during the same memory cycle.
An advantage of both the latched and the register
STRAM, however, is the built-in write-pulse generator,
which eliminates an annoying problem associated with
(a)
(b)
3. Timing diagrams show that in a registered STRAM (a) the control word is read in the second
clock cycle, while a latched STRAM (b) reads the data in the same clock cycle.
9-7
DESIGN APPLICATIONS • Increase memory speed
4. Both the registered (a) and latched versions (b) of the STRAM include a write-pulse generator. The devices have differential clock inputs-Clock and Clock-but single-ended operation is possible by connecting either clock line to an internal reference voltage.
fast ECL RAMs-the generation of a narrow write pulse.
This on-board capability not only simplifies the designer's task, since creating very narrow pulses can be difficult, but it also speeds up the write cycle.
For instance, the length of a write cycle for a typical
static RAM, MBMI0474-15, employed without input
and output latches is the sum of the minimum setup time,
2 ns; the write-pulse length, 12 ns; and the minimum hold
time, 1 ns. That comes to 15 ns. For a latched STRAM
with an internal write pulse generator, MBMI0476LL-9,
the write cycle time is the minimum setup time, 1 ns, plus
the minimum high or low clock time, 6 ns-a total of7 ns.
Another advantage of the STRAM is that the data
written in the RAM is transparent to the outputs. This
boosts the speed of the system for a cache write-through
and improves the write-cycle timing for the writable control store. Also, the input data is transparent to the output
in the same clock cycle for the latched STRAM and in the
next cycle for the registered version. The transparent feature is helpful in diagnostic tasks and for writing back the
data into the next location.
In both types ofSTRAMs the setup and hold times are
identical for all inputs, simplifying the timing. The sum of
the setup and hold times, also called the required valid
window, is only 30% of the overall cycle time. For example, a lk-by-4IatchedSTRAM, theMBMI0476LL, has a
clock cycle of 10 ns and a setup time plus hold time of 3 ns.
This low ratio leaves enough time for the inputs to get
ready for the next cycle.
9·8
The read and write cycles also have the same timing,
because the data-input registers and latches are loaded at
the start of each cycle, regardless ofthe type of cycle. This
balanced read-write configuration is helpful for systems
integration. When Write Enable is low at the beginning of
a cycle, an internal write operation writes the data into
memory and restores internal write lines to their original
values.
The devices have differential clock inputs-Clock and
"ClOCK-to increase timing accuracy. They can be connected in either the differential or single-ended mode. In
the differential mode, data is latched at the cross point of
the rising edge of Clock and at the falling edge of "ClOCK.
Connecting either Clock or Clock to the internal reference voltage configures the STRAM in the single-ended
mode, latching data at the true going edge of the clock. 0
Mohammad Shakaib Iqbal, an application engineering
supervisor at Fujitsu Microelectronics Inc., works on localarea networks, microcontrol/ers, small computer system
interfaces, a!ld memory products. He holds a BSEE from
NED University, in Karachi, Pakistan, and an MSEE
from Oregon State University.
Appendix 2
Static RAMs
9-9
Static RAMs
9·10
Static RAM Data Book
cP
November 1989
Edition 1.1
APPLICATION NOTE
FUJITSU
Separate Data Inputs and Outputs SRAMs
Provide New Architectural Solutions
for System Designers
Applications Engineering Department
Fujitsu Microelectronics, Inc.
Integrated Circuits Division
Copyright© 1990 by Fujitsu Microelectronics, Inc.
ABSTRACT
Traditionally; Static Random Access Memories (SRAMs) which can store greater than one-bit-wide words are
available in packages with common data inputs and outputs. This is a consequence of the package size
constraints for wider word widths. Fujitsu also offers byte wide and word-wide devices such as MB81C78A,
MB81 C79 and MB81C40. In the case ofSRAMs with four-bit wide words or less, the increase in package size is
not significant. Instead, the advantages of separate I/Os for system designers more than outweigh the slight
increase in package size. The basic benefit of having separate data inputs and outputs is that it does not require
the data bus direction to be changed during a read-modify write cycle. Thus, the need for multiplexing and
demultiplexing in the data paths is eliminated. This application note deals with some specific usage areas
which take advantage of the separate data input and output SRAMs.
A large variety of new applications, as well as some old memory designs have a need for separate data input
and output pins on the SRAMs. Some of the key application areas are as follows: writeable microprogram
control stores, cache memory systems, and deep FIFO data buffers for disks and LANs. The following
discussion covers each of these application areas, highlighting the importance of the separate data input and
output SRAMs.
9-11
9-12
Contents
Page
Chapter
Abstract .............................................................................. 9-9
Microprogramming and Writeable Control Store .......................................... 9-13
The Main Parts of a Control ............................................................ 9-14
Some Thoughts on Application Areas ................................................... 9-16
Cache Memory Systems ............................................................... 9-16
Basic Blocks of a Cache Memory ........................................................ 9-17
Buffer Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-18
Tag/Directory Block .................................................................. 9-18
Priority Update List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-18
Control Logic ........................................................................ 9-18
Building a Large Disk Cache ........................................................... 9-20
Building Deep FIFO Buffers .... " ...................................................... 9-21
Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-23
References ........................................................................... 9-23
Illustrations
Figures
Page
1.
Arrangement of a Control Store Memory ......................................... 9-14
2.
Writeable Control Store Memory ................................................. 9-15
3.
Common Memory Hierarchies: (a) Two-level, (b) Three-level ........................ 9-17
4.
Typical Cache Memory Structure ................................................ 9-17
5.
Cache Capacity Trends by Typical Cache Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-19
6.
Cache Capacity Trends by Typical Cache Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-19
7.
A Large Disk Cache for a Disk Drive Enhances System Performance .................. 9-21
8.
Basic FIFO Design ............................................................. 9-22
9-13
9-14
Fujitsu Microelectronics.
Inc.
Static RAMs
Microprogramming and Wrlteable Control Store
Microprogramming has become one of the most powerful tools currently available to designers of
high-speed, microprocessor-based systems. It provides a degree of flexibility previously unattainable in
sophisticated processors and controllers.
Microprogramming is actually accomplished by execution of a machine Ianguage program that is made
up of a sequence of microinstructions. This execution is performed at a microinstruction level by having
each microinstruction interpreted on the host machine hardware through a microprogram1•
Microprograms comprise a sequence of microinstructions that activate the control primitives of the host
machine. Individual sequences contain all the elemental steps required to perform system function. The
microprogram is kept in a high-speed, random access storage unit that is called a control store or control
memory. Control storage is normally found implemented as a ROM. However, control storage may also
exist as a dynamically alterable memory known as a writeable control store. A read only memory cannot
be modified by an executing microprogram. The contents of the control ROM are unalterable and provide
a fixed interpretation sequence for a given microinstruction set. On the other hand, the contents of the
writeable control store can be modified by executing a microprogram. This allows the architecture of the
host machine to be redefined under microprogram control since a different microprogram module may be
loaded in the writeable control store under the control of the user program. A processor having this
capability is called a flexible architecture machine.
A writeable control store memory provides the main application for the static RAM with separate data
inputs and outputs. This will be evident from the arrangement of the control store as shown in Figure I.
9-15
Fujitsu Microelectronics. Inc.
Static RAMs
Sequenoe
through
~~\
Prog~
e
M"
Control
MernOlY
Counter
Dala
Register
[:]
External
Source
ConIlOI
Store
-~
Register
Control
Primitives
lObe
Activated
(Floppy Diskl
~ hS-232
ConllOl
SlOre
,
~
Control
Store
....-
Dala
Register
-
Addresse&
orWrireabie
ControI Store
Figure 1. Arrangement of a Control Store Memory
The Main Parts of a Control Store
1.
Microprogram Counter
The microprogram counter contains the address of the next microinstruction which is loaded in
the control store. Usually, it is incremented by one, and the program sequencing is done by
adding one (1) to the current contents of the microprogram counter.
2.
Microprogram Instruction Register
The microinstruction register contains the current microinstruction being executed by the host
machine. For a read only store, the microinstruction register would not provide leads for data to
be written into the control memory - it would only receive data from the control store.
3.
Control Store Data Register
Since many microprogrammed machines use a combination of read only storage and writeable
storage, another register must be provided to supply data to be written in the writeable control
memory. This register can be called the control store data register.
4.
Control Stan: Address Register
Generally, the microcode which is loaded in the writeable control store is not written into the
same location as that of the next instruction; therefore, a fourth register is needed. This register is
called the control store address register. It points to the location in the writeable control store
where the data word in the microcode is to be stored.
It is possible to combine the functions of the microprogram counter and the control address register as
well as the functions of the microinstruction register and the control store data register. In general, these
four registers will be kept separated, with the control store address register and
9-16
Static RAMs
Fujitsu Microel9CIronics. Inc.
the control store data register fonning a pair that references writeable control store and functions
independently of the register pair fonned by the microprogram counter and the microinstruction register.
The microprogram counter and the microinstruction register, in tum, reference read-only control storage
in terms of microprogram execution. Thus, a block of microcode could be loaded from a system
peripheral, such as a floppy disk, into the writeable control store for usage by a specific microprogram.
Similarly, data from either writeable control store or control ROM could be copied by control memory
over into the main storage. The precise reasons for perfonning these operations would be dictated by the
reqUirements of the user. In this application it is desirable to use an SRAM with separate data inputs and
outputs to avoid the multiplexing and demultiplexing in the data paths.
Some systems use only writeable control store as control memory. In this case, the sequencer needs the
addresses for read cycles of the RAM, while the microprocessor sends the addresses for the write cycle of
the RAM. 'IYPically the outputs of the writeable control store are to be configured in a very wide
micro word, anywhere between 64 to % bits wide. This is a horizontal microword implementation. The
tenn horizontal here implies that the microword has enough bits to directly control all the significant
machine resources without additional decoding, encoding. or other hardware interpretation. The inputs,
however, are configured into an 8- or 16-bit wide data bus, in order to be loaded direct1y from the host
microprocessor. Figure 2 shows the more detailed arrangement of a typical system which uses only a
writeablecontrol store.
Addresses
,.----------,
S
E
Q
U
E
N
C
E
64
R
K
x
4
Microword
I
I
I
I
I
I
64Kx72
8 bits,
Bank of SRAMs I
L
__________
.JI
16 bits
or
32 bits
depending on j1P
Ac:IdI'ess
Bus
Data bus
FIgure 2. Wrlteable Control StQre Memory
9-17
Static RAMs
Fujitsu Microelectronics, Inc.
For this type of architecture, a static RAM with separate data inputs and outputs is required. If this design
is implemented by devices having a common data input and output bus, then the design would require
numerous buffers or transceivers to accomplish this function. Thus, by using a separate data input and
output static RAM like the Fujitsu MB81C86, which is 64K x 4 bits wide, the designer realizes a significant
savings in IC count, as well as PC board real estate.
Some Thoughts on Application Areas
Due to the flexibility and cost reductions throughout the design development and maintenance,
microprogrammed (MP) systems extend across large product and application areas, ranging from simple
control functions to complex real time control systems.
Aside from the more common applications, such as emulation of other systems, and upward/downward
compatibility among series configured minicomputer systems, microprogram control units (because of
their cost effectiveness) can be applied to functions previously performed only by special circuits or
custom made devices. For example:
I.
Process control systems (factory automation).
2.
Instrumentation systems (signal generators, synthesizers etc.).
3.
Intelligent terminal for off-line editing (supermarket checkouts, terminals of investment houses).
4.
Real time data processing (spectral analysis, pattern recognition, etc.).
5.
Data communications systems that have MP systems controlling polling, scheduling tasks, or buffer
management (front end processors, communication processors, etc.).
Applications of MP systems are virtually unlimited because of their high performance, low cost
implementation. Hence, the availability of static RAMs with separate data inputs and outputs has a
substantial impact on the design of MP systems which, in tum, find their way into a wide variety of
applications, as discussed previously. Another area of system architecture which benefits from the
separate data inputs and outputs on the static RAMs is cache memory system design.
Cache Memory Systems
In a cache-based system, a small, fast memory known as the buffer or the cache, (with roughly the same
speed as the processor registers) is interposed between the processor and the main memory. This cache
serves as a transparent bridge between their speeds. The "cache bridge" is transparent in the sense that is
is invisible, making it inaccessible to the users, since it is completely hidden from them and not directly
addressable (cache means "a hiding place"). However, by providing the processor with all the current
information it requires at a faster speed, the cache creates an illusion of having a large main memory
operating.'
During the era of early computing, the main memory technology was quite slow compared to the speed of
the CPU. In order to overcome the slow access of the main memory, a small high performance cache
buffer memory was placed between the CPU and the main memory. Figure 3 shows two of the most
common memory hierarchies.
The two-level cache has already been discussed; i.e., slow memory communicates with a fast CPU. The
three-Ievel case takes into account the advantages of having a cache. With this memory hierarchy scheme,
the CPU executes data from the very fast cache buffer and only has to slow down when this buffer
9-18
Static RAMs
Fujitsu Microelectronics. Inc.
requires new data from the slow main memory. Thus, with a small fast buffer, the overall performance of
the large, slow main memory approaches that of the buffer.
~
CPU
~
Main
Memory
Secondary
Memory
1.
(a) Two-/ewl
~
CPU
~
Cache
Main
Memory
~
Secondary
Memory
I
~
(b) ThreH!wl
Figure 3. Common Memory Hierarchies: (8) 1\vo-level, (b) Three-level
Basic Blocks of a Cache Memory
As already discussed, the philosophy behind the concept of buffering or caching is to use a fast, relatively
small memory between the processor and the main memory. Figure 4 shows a typical way of
implementing a cache memory system.
Switch
Address Bus
-
I
Control
Priority
Update
Usl
--
Tag
Directory
RAM
1
BulferlData
-
RAM
Main
Memory
Data
Data
I
I
Switch
Figure 4. 'tYpical cache Memory Structure
9-19
Static RAMs
Fujitsu Micro9lectronics, Inc.
Buffer Block
A cache memory is basically a small, high-speed memory with main memory information. This
information may be addresses, data, or instructions. Hence, the cache can be an address cache, data cache,
or an instruction cache. Its speed is typically an order of magnitude faster than that of the main memory,
while its capacity is typically one or two orders of magnitude less than that of the main memory.
Tag/Directory Block
A cache memory system requires an identifier or tag store to indicate which entries of main memory have
been copied into the cache store. Data in the large main memory has to be mapped into the smaller cache
buffer, where it is partitioned or subdivided into small segments called blocks. Each block is identified
with a label called the tag address. These tag addresses are stores in an associative RAM called the
tag/directory RAM. It operates like a search memory.
Priority Update List
A buffered memory requires a logical network that selects words or blocks to be removed when the new
entries (words or blocks) need to be brought into the cache. This structure is called the priority update list.
Control logic
A cache memory system also requires control logic to generate all timing for synchronizing various
activities; for example: searching the tag store, getting the data out of the cache, and replacing proper
entries in the cache.
The operation of the total system is quite simple. Whenever the CPU requests the data from the main
memory, the first operation that takes place is the matching of addresses coming from the CPU with the
addresses inside the directory RAM. H this matches, then the data associated with this tag address is sent
to the CPU. This is known as "hif' or address match. H the directory RAM does not contain the address
being accessed by the CPU, then a "miss" takes place. When this happens, the data from the main
memory is sent to the CPU. It will also be simultaneously stored in the buffer RAM. Hence, if this address
is accessed again then the data will come from the cache.
The cache buffer design involves many parameters such as type of memory mapping schemes, (fully
associative, direct and set associative), cache size, block size, data replacement algorithm, and a variety of
other features which will not be covered in this paper.
In the earlier cache-based, systems, the capacity and performance of main memory were modest in
comparison to today's systems. Designers were using expensive bipolar RAM technology for performance
considerations. Due to the improvements in semiconductor process technology, both bipolar and MOS,
the size and performance of cache memories have continued to grow as shown in Figures 5 and 6.
9-20
Static RAMs
Fujitsu Microelectronics. Inc.
600
•
Very high performance computer
B3
High performance computer
500
400
Typical
Cache
Size
(KBytes)
300
200
100
0
1970
YEAR
Figure 5. cache capacity Trends by Typical cache Size
Very high performance computer
High performance computer
180~~-------------------------1~_r--~~~---------------------Typkal
Cache
1~_r------~~~-----------------_+-~~
Performance
(ns)
________________
~~~
_____________________________
100
80
-+____
80
_r-----------~~~--_;-~_.~------
-.,;:::::.._~-------...;:3"""_;~-----------
~_r----------------------------~~~=_--~~-----
~_r----------------~-----~~~-
o
1970
1980
YEAR
85
86
87
88
89
1990
Figure 6. cache Capacity Trends by Typical cache Perfonnance
9-21
Static RAMs
Fujitsu Microelectronics, Inc.
As shown in Figure 6, the typical CPU cache times are approaching 55 ~or less. As far as the
performance or hit rate of the cache is concemed, it is primarily determined by the buffer size.
Consequently; if a cache buffer size is large, in the order of 256K or 5121<, the miss rate is low (see Figures
5 and 6). Hence, a RAM 64K deep is an excellent choice.
Word width is another imPO$nt consideration. Historically; a RAM with a large number of output
drivers is slower than a device with fewer outputs because of high ground noise. Wider word widths,
however, will give the system designer a large number of unused bits/word. A by-1-organization
provides the highest performance and exact word widths' but it uses a large number of devices.
Therefore, a by-4-organization usually provides a better alternative. This choice also affects the board
layout.
The majority of by-4-bits and by-8-bits wide SRAMs have their inputs and outputs multiplexed over the
same pins. This arrangement, however, increases turnaround and settling delays, thereby slowing system
performance. As shown in Figure 4, if the tag and data RAM have a separate data input and output
channel, then the glue logic for comparisons will not be followed by multiplexers and demultiplexers.
Thus, a SRAM with a separate data input and output pus is ideal for this case. The Fujitsu MB81C86 is a
CMOS 64K x 4 SRAM, with an access time of 55 ns, and a separate data input and output bus. For systems
which require very high performance, and no board layout constraints, MB8IC71A (the 64K x 1 CMOS
SRAM with access times as fast as 25 ns) provides a unique solution. It is also useful for high-speed
minicomputers and mainframe applications.
Building a Large Disk Cache
Real time interactive graphics and CAD systems are two high-speed computing applications which
require a large on-line data base. Only mass storage can deal with such huge quantities of data. Disk
drives, as well as mag tapes, are extremely slow, although their capacity is sufficient. These devices
transfer data much too slowly for todays high performance mainframes, minicomputers, or
microcomputers.
One solution to increase the transfer data rate is to place a semiconductor cache memory between the CPU
and the disk subsystem. The cache should be large enough to hold a significant percentage of the data the
CPU requires from an I/O device. This cache not only improves the disk data transfer rate, but also more
closely matches the speed of the central processing unit of the host system. Incidentally; this cache does
not place a heavy demand on the power from either the system or battery back-up.
The Fujitsu MB81C81A-35/45 is a prime candidate since the cache would be several megawords in size.
This is a 256K x 1 CMOS SRAM. This device has separate data inputs and outputs. In order to design a
5I2K-byte disk cache for an 8-bit wide data bus, only 16 of these devices are needed. If the hosfs main
memory access time is 80 ns, then a 45 ns device shortens the system throughput time. A typical system is
shown in Figure 7.
9-22
\
Static RAMs
Fujitsu Microelectronics. Inc.
~
CPU
512KDisk
Cache and
Cache
Conlroller
t~
,
t
Address
Bus
Main
Memory
Memory Data
OuIputBus
Memory Data
InpuIBus
Sy8lllmiJO
DataBu8
Printer
*
Disk
Drive
Figure 7. A Large Disk cache for a Disk Drive Enhances System Performance
Building Deep FIFO Buffers
Separate data input and output SRAMs have a wide variety of applications. They are useful in building
deep FIFO buffers. FIFO is a First-In-First-Out memory which can be implemented in different ways. The
main function of this type of memory is to read out the data in the same order that it was written. The
basic design of a FIFO implemented from the separate data input and output SRAM is shown in Figure 8.
9-23
Fujitsu Microelectronics, Inc.
Static RAMs
Flags
-----,
CCR
r----
I
W
FIFO
R
ConlrOl
Block
Sequential+_ _ _
WRDY
RRDY
~
Addresses
SRAM
Banks
Data Input
I
I
I
I
I
I
I
IL________________ ~I
I
I
Data Output
Figure 8. Basic FIFO Design
The FIFO control logic consists of two ring counters for generating read and write addresses. When the
FIFO is empty, then both of these counters are initialized to location zero in the SRAM. In the case of a
write to the SRAM, the write counter is incremented, thus pointing to the next empty location. The read
counter always points to the full location i.e., the location which has data written into it. When all the data
has been read, and the read and write counters point to the same location, the FIFO control logic generates
an empty flag. A full flag is generated when the write counter points to an address that is less than the
read counter. At this point no further data dumps are allowed in the FIFO. This FIFO control block is
commercially available as FIFO RAM controller, which can easily create 64K deep buffers from the
separate data input and output SRAMs.
FIFO devices are marketed with onboard RAMs. These commercially available FIFO devices provide
asynchronous operation, but are not deep enough for such applications as buffers for disk systems,
printers, and local area networks where the data usually comes in the form of large blocks. Designers
cannot afford to lose the data; consequently, the FIFO buffer should be large enough to hold the complete
block. The deepest commercially available devices are 2K words deep.
In order to implement a deep FIFO buffer, it is desirable to have a SRAM with separate data inputs and
outputs. This avoids the turnaround delays and muxes/ demuxes. Another advantage of using the SRAMs
over commercially available devices is that the data can be accessed by the CPU. Therefore, in the disk
environment the error correction can be done on the fly. This is not possible in commercially available
FIFO devices because they do not have an address bus.
9-24
Fujitsu Microelectronics. Inc.
Static RAMs
Conclusion
Fujitsu offers the following CMOS static RAMs with separate data inputs and outputs: a MK x 4 SRAM,
MB81C86 (with 55 ns access speed), a MK xl SRAM, MB81C71A, (with 25 ns access speed), and a 256K x
1 SRAM, MB81C81A (with 35 ns access speed). These SRAMs help system designers develop not only an
efficient system, but also a less expensive system because of smaller board space.
References
1.
Brick, Jim and John Mick. "Microprogramming Ups Your Options in Microprocessor System
Design," EON. January 20, 1978.
2.
Brunner, Dick. "High Performance Cache Memory." IEEE Conference Proceedings. WesCon 1986
3.
Pohm, A.V. and D.P. Agrawal. High Speed Memory Systems. Reston Publishing Company.
4.
Hartwig. Knorpp, Mears and Osman. "Large Disk Cache Uses Fast MK by 1 SRAMs to Speed
Database Accesses." Electronic Design. September 19, 1985.
9-25
Static RAMs
9-26
Fujitsu Microelectronics. Inc.
- - - - - - - - - - - - - - - - Appendix 3
FastSRAMs
9·27
Intelligent Cache Tag RAMs
9-28
Static RAM Data Book
\
OJ
November 1990
Edition 1.0
FUJITSU
Fast SRAMs in Zero Wait-State Memory Interfaces
By Adrian B. Cosoroaba
and
Barry Boulton
Standard Products Marketing Department
Fujitsu Microelectronics, Inc.
Integrated Circuits Division
Copyright© 1990 by FUjitsu Microelectronics, Inc.
Abstract
With the introduction of high-speed microprocessors, running at up to 50 MHz and executing close to one instruction per clock cycle, the performance of stat~f-the-art systems has become limited by memory access
times. In order to harness the power available from these contemporary microprocessors, it is necessary to design systems capable of accessing memory without waiting for additional clock cycles. This capability is
known as Hzero wait-stateHaccess, and it demands new techniques and devices in order to maximize system
performance.
9·29
\
9·30
Fujitsu Microelectronics. Inc.
Fast Static RAMs
This Application Note discusses two approaches to maximizing system performance: first, the
DRAMs-plus-SRAM cache, the choice for most current designs, and second, the SRAM bank, a choice that
offers higher performance, albeit at a higher cost.
This Application Note will also show the choices that present and future high-performance SRAMs
offer in terms of granularity (xl, x4, x8, x9) for high performance memory system designs.
High Performance Memory Interfaces
To implement a zero wait-state memory in a high-performance system, some use of SRAMs is
necessary because DRAMs have access times that are much slower than a microprocessor cycle time.
SRAMs, however, continue to stay with the fastest microprocessors (in terms of access time relative to one
clock cycle).
The concept of a SRAM cache to reduce wait-states (first introduced in mainframes) is now
commonly used in both workstations and high-performance personal computers. This demand for zero
wait-state access has also reached the world of embedded control applications where, although data
memory size requirements are generally smaller than in operating system applications, fast access to data
is necessary in order to make critical, time-dependent decisions.
There are two possible configurations for a memory interface: (1) a zero wait-state memory could be
composed of SRAMs only, or (2) a zero wait-state could have DRAMs (as the primary source) with a
SRAM cache. The choice of options is normally dependent on relative cost and component count. Both
memory interface options are described as follows.
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Fujitsu MicroBlectronics, Inc.
Fast Static RAMs
1. DRAM Bank with SRAM cache
This option interposes a fast SRAM caChe between the processor and the DRAM memory to
maintain high system perfonnance (see Figure 1). The cache saves the most frequently used data and
provides the processor with fast access to this data. H the processor could always access only the cache,
then system performance would be maximized (zero wait-state). However, the prococessor cannot always
access the cache because it inevitably requires additional data from the main memory. Thus, only a
portion of memory accesses are with the (zero wait-state) cache itself, while the remaining portion is with
the (non-zero wait-state) main memory.
(0 Wait-stale)
rl
SRAM
Cache
(64 Kbyte)
I
'---
8x(8Kx8)
Microprocessor
•
I ..
I
I
TagSRAMs
5x (4kx 4)
32 bit Bus
I
I
Cache
Controller
I
I
DRAM
Controller
I
DRAM
Memory
(1Mbyte)
ax (256Kx4)
(3 Wait-states)
Figure 1. SRAM eache Plus DRAM Memory Option
Given this mix of accesses, the system performance is dependent on the Hit Ratio of the cache,
where the Hit Ratio is defined as:
Hit Ratio = Number of Cache Accesses
Total Number ofMemory Accesses
To calculate the number of wait-states of this system, the following formula applies:
Number of wait-states =Hit Ratio x number of wait-states (cache)
+ Miss Ratio x number of wait-states (DRAM).
where the Miss Ratio = 1 - Hit Ratio
In a typical i486-VM33MHz system, a fast SRAM cache would have a zero wait-state access, while
the much slower DRAM would have a three-wait-state access (based on 80 ns DRAM access time). In the
i486-1M33MHz system, the Hit Ratio would quite likely be around 70 percent (this is dependent upon the
size of the application program).
9-32
\
Fujitsu Microelectronics, Inc.
Fast Static RAMs
Using the preceding fonnula:
Number of wait-states =0.70 x 0 + 0.30 x 3
=0.90
Thus, on the average, the cache implementation adds 0.90 wait-states, or approximately one
wait-state that substantially reduces overall system performance. A high-performance RISC, or even i486
processor, averages close to one clock per instruction. A wait-state representing an added clock cycle will
reduce the performance of the system dramatically because it takes the processor twice as long to read an
instruction from memory. In actual practice, one wait-state will typically reduce system performance by
around 30 percent The 30 percent compares well with the reduction of around 65 percent that occurs
when using only DRAMs (wait-states) without the SRAM cache.
The addition of a SRAM cache to improve performance of a system has been the standard to
improve performance because the cost impact is minimal. SRAMs cost more than DRAMs, but since the
cache is normally around 10 percent of the size of the total memory size, the overall cost addition is
modest. Thus, the DRAM plus SRAM cache provides a significant system performance improvement at a
modest cost, but it stillieavesa potential improvement of 43 percent [1/(1- 03)] untapped. This
potentially available improvement leads us to the SRAM·(mly option.
2. SRAM Bank Only
Whereas the cache plus DRAM performance is dependent on the Hit Ratio of the cache, and the
number of wait-states it takes to access the DRAM bank, the SRAM Bank option offers a true 0 wait-state
implementation. The straight SRAM Bank option does not limit the performance of the microprocessor,
and it does pick up the 43 percent improvement that was left untapped with the DRAM plus SRAM cache
option.
(0 Wait-state)
i
Microprocessor
32·bitBus
SRAM
Memory
1 Mbyte
32 x (256kx 1, 64Kx 4)
or 8 x (128K x 8, 256K x 4)
Figure 2. SRAM Memory Option
This option has been used rarely because the cost is significantly higher than for the cache scheme.
However, with the current trend to smaller physical sizes in state-of-the-art SRAMs, along with the drive
to extract maximum performance, it begins to look very attractive.
9-33
\
Fujitsu MicfOBlectronics, Inc.
Fast Static RAMs
Let's take a look at the two approaches, the DRAM plus Cache with a SRAM Bank and the SRAM
Bank, side by side.
Comparison of DRAM Plus cache with the SRAM Bank
For a typical system with a microprocessor running a one clock memory access cycle, the access time
requirement for the cache option is the sum of the 'Illg comparison and the SRAM data access. Since the
SRAM memory option does not require a Tag comparison, the system has more time for SRAM memory
access, and it can use slower SRAM devices than the DRAM plus cache that is only achieving a one
wait-state interface. Oearly, if sheer system performance is the goal, the SRAM bank is the superior
option.
Another consideration (when choosing which option to use) is the component count, and here too,
the SRAM bank may well offer the optimum solution. Of course, the number of devices also impacts the
board space requirement, as well as the power consumed by memory, and normally, it is desirable to
make both as low as possible.
The cache plus DRAM option requires additional logic for two controllers (a cache controller and a
DRAM controller), each commonly being implemented with three phase-lock demodulators (PLDs) each.
In comparison, the SRAM bank option requires no additional devices.
Table 1 shows that if both options use 1 Mb devices, then the SRAM bank would use 8 devices
compared to 27 for the DRAM plus cache option, with concomitant power dissipation reduction from
6.2W to 2W. Thus, in addition to a 42 percent performance improvement, the SRAM bank option
Significantly reduces both required board space and power dissipation.
It may be that in new high-performance systems the additional cost for SRAMs (as the complete
memory) may be more than compensated for by the enhanced performance, simpler design, less power
dissipation and less board space.
Table 1. System Characteristics
System Factors
Number of
Walt-states
Option 1:
Cache plus DRAM
(64Kbyte plus 1Mbyte)
0.9 to 3.0
Option 2:
SRAM (1mbyte) Bank
0
Number of Devices
Sea.
8 ea.
8ea
6 ea.
27
Power
Consumption
TagSRAMs
DaiaSRAMs
DRAMs
PLDs
Total Devices
6.2W
32 ea. (256Kb) SRAMs, or
8 ea. (1 Mb) SRAMs
4.8W
2W
Memory Devices as Building Blocks
The traditional memory architectures in operating system-based applications, as well as embedded
control systems, have been based on DRAMs. With advances in microprocessor speed, DRAMs are no
longer fast enough to take advantage of the full performance of the leading microprocessors. The access
9-34
Fujitsu Microel9CIlOnics, Inc.
Fast Static RAMs
time of the DRAM is too long to satisfy a zero wait-state configuration, so SRAMs must be used in one of
the configurations outlined here.
Fujitsu and other vendors are developing high density, high performance CMOS and BiCMOS
SRAMs to provide design engineers with a variety of options in implementing these high-performance
memory interfaces. Thble 2 shows the memory size versus number and type of SRAMs needed in a
typical application for a 32-bit bus system.
Table 2. Memory Size vs. Type and Number of SRAM DevIces (32-blt Bus)
M.morySlza
SRAM
32KB
8Kx 8, 8Kx 9·
64KB
8Kx8,8Kx9·,
16Kx4
12S KB
32KxS,
32Kx 9·
256KB
32KxS,
32Kx9·, 64Kx4
512KB
32K x 8, 32K x 9·
64Kx4
12SK x S, 12SK x 9·
Numb.rof
SRAMe
SRAM
1 MB
128KxS, 12SKx9·
256Kx4256Kx 1
2MB
128K x 8, 128K x 9·
256Kx4
160r 18·
4MB
128K x 8, 128K x 9·
256Kx4,lMx 1
32 or 36·
4
80r9·
4
S or 9·
Numb.rof
SRAMs
Memory Size
80r9·
32 or 36
16 or lS·
4
·For Parity applications
The table shows the choices available for each memory configuration. The size of the memory places
limitations on the individual memory architecture: a 128K memory cannot be built with a 64K by 4-bit
device (since the width, which is 32 bits, dictates the depth to be 256K as a minimum). Obviously, the by
8-bit devices give most options; that is, they give better granularity than by 1-bit or by 4-bit devices.
FuJitsu's CMOS and BiCMOS Fast SRAMs
Current and future high-performance microprocessors demand faster and larger memory, and
Fujitsu is continuing to develop memory devices that satisfy these requirements. The present Fujitsu
asynchronous CMOS and BiCMOS SRAMs meet JEDEC standards to provide second source compatibility.
The variety of 64K bit, 256K bit, and 1M CMOS and BiCMOS fast SRAMs offered by Fujitsu are
shown in Table 3. These SRAMs are the building blocks of memory interfaces, with BiCMOS technology
evolving to speeds of 10 ns, and densities over 1Mbit.
From cache applications of 32K byte to 1 Megabyte SRAM memory banks, this choice of fast SRAMs
gives design engineers maximum flexibility, whichever memory access technique is chosen.
9-35
Fujitsu Microelectronics, Inc.
Fast Static RAMs
Table 3. Fast CMOS and BICMOS SRAMs from Fujitsu
64K
64Kx1
16Kx4
16K x 410E
4Kx8
8Kx9
CMOS
MB81C71A35/-301-25
MB81C7435/-301-25
MB81C7535/-30/-25
MB81C78A45/-35
MB81C79A45/-35
MB82B78201-15
MB82B7920/-15
BiCMOS
256K
256Kx1
64Kx4
64Kx 410E
32Kx8
32Kx9
CMOS
MB81C81A35/-25
MB81C84A35/-25
MB81C85A45/-351-25
MB829835/-25
MB829935/-25
BiCMOS
MB82B81201-15
MB82B8420/-15
MB82B8520/-15
MB82B88201-15
MB82B8920/-15
1M
1Mx1
256Kx4
256Kx 410E
128Kx8
128Kx9
CMOS
MB81C81A35/-25
MB81C84A35/-25
MB81C85A45/-351-25
MB829835/-25
MB829935/-25
BiCMOS
MB82B00135/-25
MB82BOO635/-25
201-15
MB82B85201-15
MB82B88201-15
MB82B8920/-15
Conclusion
Contemporary microprocessor-based systems are becoming faster and more powerful, demanding
memory subsystems that ensure this power is achieved in real applications. Because traditional DRAM
interfaces severely limit the system power actualIy achieved, cache architectures have become relatively
common in high-performance systems. However, it may be that for some user applications, where
maximum performance is desirable, the memory interface should be fulI-SRAM. SRAM devices are
available to make that poSSible, with some impact on cost, but also with significant improvement in board
space and power dissipation, in addition to performance.
In either case, Fujitsu offers fast SRAMs able to meet the system requirements.
9·36
Appendix 4
Cross Reference Guide for High-Speed
(CMOS and BiCMOS) SRAMs
I
Page
TlU.
9-37
High-8peed CMOS SRAMs
9-37
64KSRAMs:
Product Selection
Product Cross Referance
9-38
256KSRAMs
Product Selection
Product Cross Reference
9-39
High-8peed BiCMOS SRAMs
9-39
64KSRAMs:
Product Selection
Product Cross Reference
9-40
256KSRAMs
Product Selection
Product Cross Reference
9-41
1MSRAMS:
Product Selection
Product Cross Reference
9--42
LOW-POWfH CMOS SRAMs
9-42
641<, 256K, and 1M SRAMs:
Product Selec1ion
Product Cross Reference
9-37
SRAM Cross Reference Guide
9·38
Static RAM Data Book
SRAM Cross Reference Guide
Static RAM Data Book
High-Speed CMOS SRAMs
64K Static RAMs - Product Selection
Max. Power (mW)
Dascrlption
Address
Access
TImaMax.
(ns)
Output
Enabla
Accesstima
Max. (ns)
Actlva
Standby
Pin Count
MB81C71A
64Kx 1
Separate 110
35
30
25
N/A
440
55
22
24
Dlp1
SOJ
P
PJ
MB81C74
16Kx4
Common 110
35
30
25
NlA
550
55
22
OIP1
P
MB81C75
16Kx4
Common 110
with OE
35
30
25
15
13
10
550
55
24
24
DIP1
P
PJ
8Kx8
MB81C78A Common 110
withOE
35
45
20
15
495
83
28
28
28
Olp1
SOP
SOJ
PSK
PF
PJ
83
28
28
28
Dlp1
SOP
PSK
PF
Fujitsu
Part No.
8Kx9
MB81C79A Common 110
withOE
45
35
20/15
15/10
4951550
PaCka1as
Avalla Ie
Suffix
SOJ
1300-mi1 wide package: Skinny DIP
64K Static RAMs - Product Cross Reference
Fujitsu Part Numbar.
Vandors
MB81C71A
(64Kx 1)
MB81C74
(16Kx 4)
MB81C75
(16KX4l0E)
MB81C78A
(8Kx8/0E)
M81C79A
(8Kx 9)
CY7Cl85
CY7C182
IDT7169
Cypress
CY7C187
CY7Cl64
CY7C166
Hitachi
HM6287
HM6288
HM6289
lOT
IDT7187
IOT7188
IDT7198
IDT7164
Micron
MT5C6401
MT5C6404
MT5C6405
MTSC6408
Mitsubishi
M5M5187A
M5MSl88A
MSMS189A
MSMS178
M5M5179
Motorola
MCM6287
MCM6288
MCM6290
MCM6264
MCM6265
NEC
1JP04361
IJPD4362
1JP04363
Performance
P4C187
P4C188
P4C198
P4Cl64
P4Cl63
Samsung
KM6165
KM6465
KM6466
KM6865
Sharp
LH5261
LH5262
LH5267
LH5165 and
5164
Sony
CXK5164
CXK5464
CXK5465
CXK5863
CXK5971
Toshiba
TC5562
TC55416
TC55417
TC5588
TC55389
9-39
Static RAM Data Book
SRAM Cross Reference Guide
High-Speed CMOS SRAMs (Continued)
256K Static RAMs - Product Selection
Max. Power (mW)
Fujitsu
Part No.
Description
Address
Access
Tim. Max.
(ns)
MB81C81A 256Kx 1
Separate LO
35
MB81C84A 64Kx4
CommonLO
35
MB8298
32Kx8
Common LO
withOE
35
MB8299
32Kx9
Common LO
withOE
35
25
25
25
25
ou:ut
Ena Ie
Access time
Max. (ns)
Active
paCka~8"
Standby
Pin Count
Avalla Ie
Suffix
Dlp1
SOJ
PSK
PJ
NlA
550
82.5
24
24
NlA
550
82.5
24
24
Dlp1
SOJ
PSK
PJ
14
12
605
715
27.5
28
28
28
Dlp1
SOP
PSK
PF
PJ
14
12
605
715
27.5
32
32
Dlp1
SOP
32
SOJ
SOJ
PSK
PF
PJ
'300-mil wide package, Skinny DIP
256K Static RAMs - Product Cross Reference
Fujitsu Part Numbers
Vendore
MB81C81A
(256K x 1)
MB8298
(32Kx8l0E)
Cypress
CY7C197
CY7C194
CY7C199
Hitachi
HM6207
HM6208
HM62832
lOT
IDT71257
IDT71258
IDT71256
Micron
MT5C2561
MTSC2564
MTSC2568
Mitsubishi
MSMS257
MSMS258
Motorola
MCM6207
MCM6208
NEC
MCM6206
MB8299
(32Kx9/0E)
IDT71259
MCM6205
1JPD43254
Performance
P4CI257
P4CI258
P4CI256
Samsung
KM61257
KM64257
KM68257
Sharp
LH52251
lH52252 and
52255
lH52254and
52258
Sony
CXK51256
CXK54256
CXK58258
CXK58289
TC55464
TC55328
TC55929
Toshiba
9-40
MB81C84A
(64Kx4)
SRAM Cross Reference Guide
Static RAM Data Book
High-Speed BiCMOS SRAMs
64K Static RAMs - Product Selection
Max. Power (mW)
Address
Access
11meMax.
(ns)
Out~ut
Ena Ie
Access time
Max. (ns)
MB82B78
8Kx8
Common I/O
withOE
20
15
10
8
660
82.5
28
28
MB82B79
8Kx9
Common I/O
withOE
20
15
10
8
660
82.5
28
28
Fujitsu
Part No.
Description
Pin Count
Active
paCka~e.
Standby
Avalla Ie
Suffix
DIP'
SOJ'
SOP
PSK
PJ
PF
DIP'
PSK
PJ
PF
SOJ1
SOP
1300-mil wide package, Skinny DIP
64K Static RAMs - Product Cross Reference
Fujitsu Part Numbers
Vendors
Cypress
MB82B78
(SKxS)
MBS2B79
(SK x 9)
CY7B185
H~achi
lOT
IDT7164
Micron
MT5C640S
IDT7169
Mitsubishi
MSMS17SA
Motorola
MCM6264
MCM6265
Performance
P4C163
P4C164
M5MS179A
Samsung
Sony
CXK5S63A
Toshiba
TC558S
TC5589
9-41
/
/
Static RAM Data Book
SRAM Cross Reference Guide
High-Speed BiCMOS SRAMs
256K Static RAMs - Product Selection
Max. Power (mW)
Fujitsu
Part No.
Description
Address
Access
TIme Max.
(ns)
oU!'but
Ena I.
Access time
Max. (ns)
Active
Standby
Pin Count
packar.:
Avalla Ie
Suffix
Dlp1
SOJ
PSK
PJ
PSK
PJ
MB82B81
256Kx 1
Separate 110
20
15
N/A
660
82.5
24
24
MB82B84
64Kx4
Common 110
20
15
NlA
660
82.5
24
24
Dlp1
MB82B85
64Kx4
Common 110
withOE
20
15
10
8
660
82.5
28
28
Dlp1
MB82B88
32Kx8
Common 110
withOE
20
15
10
8
715
83
28
28
Dlp1
SOJ
PSK
PJ
MB82B89
32Kx9
Common 110
withOE
20
15
10
8
715
83
32
32
Dlp1
SOJ
PSK
PJ
SOJ
SOJ
PSK
PJ
130O-mil wide package, Skinny DIP
256K Static RAMs - Product Cross Reference
FulHsu Part Numbers
MB82B81
(256K x 1)
MB82B84
(64Kx 4)
Cypress
CY7C197
Hitachi
HM6707/A
Vendors
MB82B85
(64Kx4l0E)
MB82B88
(32Kx8l0E)
CY7C194
CY7C196
CY7C199
HM6708/A
HM6709/A
IDT
IDT71257
IDT71258
IDT61298
IDT71256
Micron
MT5C2561
MT5C2564
MT5C2565
MTSC2568
Mitsubishi
MSM5257B
M5MS258B
Motorola
MCM6207
MCM6208
MCM6209
MCM6206
Performance
P4C1257
P4C1258
P4C1298
P4C1256
TC55464
TC55465
Sony
Toshiba
1-42
MB82B89
(32Kx9/0E)
IDT71259
MCM6205
CXK58258
CXK58289
TC55328
TC55329
SRAM Cross Refef8ncs Guide
Static RAM Data Book
High-Speed BiCMOS SRAMs
1M Static RAMs - Product Selection
Max. Power (mW)
Description
Address
Access
nmeMax.
(ns)
MB82BOOI
lMx 1
Separate 110
ou~ut
Ena Ie
ACC8sstlme
Max. (ns)
Active
standby
Pin Count
35
25
N/A
660
138
MB82B006
256Kx4
Separate 110
35
25
N/A
660
MB82B005
256Kx4
Common 110
withOE
35
25
MB82B008
128K x 8
Common 110
withOE
MB82B009
128Kx9
Common 110
withOE
Fujitsu
Part No.
1M Static RAMs -
packa~e.
Avalla Ie
Suffix
28
SOJ
PJ
138
32
SOJ
PJ
660
138
32
SOJ
PJ
25
715
138
32
SOJ
PJ
25
715
138
36
SOJ
PJ
Product Cross Reference
Fujitsu Part Number.
Vendors
MB82BOO1
(1M x 1)
MB82BOO5
(256Kx4)
Hitachi
HM621100A
HM624256/A
Micron
MTSC100l
MTSC100S
Mitsubishi
MSMS100l
M5MS1004
Samsung
KM611001
Sony
MB82BOO6
(256Kx4)
MB82BOO8
(128K x 8)
M82BOO9
(128Kx 9)
HM624257
CXK581 020
9·43
/
Static RAM Data Book
SRAM Cross Reference Guide
Low-Power CMOS SRAMs
64K, 256K, and 1M Static RAMs -
Product Selection
Max. Power (mW)
Out~ut
Fujitsu
Part No.
Description
Address
Access
Time Max.
(ns)
MB8464Al/-LL
8Kx8
Common 110
150
100
80
55
MB84256l/-LL
32Kx8
Common 110
withOE
150
120
100
70
60
50
40
MB841 000L
128Kx8
Common 110
120
100
70
50
40
Ena Ie
Access tim.
Max. (ns)
Pin Count
Active
Standby
330
11/0.55
440
5.5/0.55
440
5.5/1.1
45
35
35
35
Avalla I.
Dlp1
DlpI
SOP
28
28
28
28
Dlp1
DlpI
SOP
TSOP
PSK
P
PF
PFTNI
PFTR
32
32
DlpI
SOP
SOJ
TSOP
P
PF
PJ
PFTNI
PFTR
64K, 256K, and 1M Static RAMs - Product Cross Reference
Fujitsu Part Number.
Vendors
Hitachi
9-44
HM6264 and
6264A
Suffix
28
28
28
1300-mil wide package: Skinny DIP
2SoO-mii wide package
MB8464A
(8Kx8)
packa~ea
MB84256A
(32Kx 8/0E)
MB841 000
(128K x8/0E)
HM62256
HM628128
MSMS1008
Mitsubishi
MSM5165
M5M52~6
Motorola
MCM6064
MCM60256
NEC
¢>04464
¢>D43256A
OKI
MSM5165
MSM51256 and
51257
Samsung
KM6264
KM62256
Sharp
LH5164
LH51256
Sony
CXK5864
CXK58257
CXK581000
Toshiba
TC5565 and
5563
TC55256 and
55257
T0551 001
¢>D431000A
KM681 000
PSK
P
PF
High-Speed CMOS SRAMs
IfJI
Ell
IIEII
..
DI
..
Ell
lUll
High-Speed SiCMOS SRAMs
Low-Power CMOS SRAMs
Application-Specific CMOS SRAMs
Extended Temperature Range SRAMs
Quality and Reliability
Ordering and Package Information
Sales Information
Appendices - Desian Information
Cross Reference Guide for High-Speed(CMOS. BiCMOS) SRAMs
FUJITSU LIMITED
Marunouchi Headquarters
6-1 , Marunouchi 1-chome
Chiyoda-ku , Tokyo 100, Japan
Tel: (03) 216-3211
Telex: 781-22833
FAX: (03) 213-7174
For further information, please contact:
Japan
FUJITSU LIMITED
Integrated Circuits and Semiconductor Marketing
Furukawa Sogo Bldg.
6-1, Marunouchi 2-chome
Chiyoda-ku , Tokyo 100, Japan
Tel: (03) 3216-3211
Telex: 781 -2224361
FAX: (03) 3211-3987
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
6072 Dreieich-Buchschlag
Germany
Tel: (06) 103-6900
Telex: 411963
Fax: (06) 103-690122
Asia
FUJITSU MICROELECTRONICS ASIA PTE. LTO .
06-04/06-07 Plaza By the Park
No. 52 Bras Basah Road
Singapore 0718
Tel: (65) 336-1600
Telex: 55573
FAX: (65) 336-1609
North and South America
FUJITSU MICROELECTRONICS, INC.
Integrated Circuits Division
3545 North First Street
San Jose, CA 95134-1804 USA
Tel: (408) 922-9000
Telex: 910-338-0190
FAX: (408) 432-9044
RECYCLABLE
© 1991 FUJITSU LIMITED and Fujitsu Microelectronics, Inc.
Printed in USA
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