1991_Harris_CDP6805_CMOS_Microcontrollers_and_Peripherals 1991 Harris CDP6805 CMOS Microcontrollers And Peripherals

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El)HARRIS
THE NEW HARRIS SEMICONDUCTOR
In December 1988, Harris Semiconductor acquired the General Electric
Solid State division, thereby adding former GE, RCA, and Intersil devices to
the Harris Semiconductor line.
This CDP6805 microcontro"ers and peripherals databook represents the
full line of Harris Semiconductor CDP6805 products for commercial
applications and supersedes previously published CDP6805 databooks
under the Harris, GE, RCA or Intersil names. For a complete listing of a"
Harris Semiconductor products, please refer to the Product Selection
Guide (SPG-201 R; ordering information below).
For complete, current and detailed technical specifications on any Harris
device please contact the nearest Harris sales, representative or distributor
office; or direct literature requests to:

Harris Semiconductor Literature Department
P.O. Box 883, MS CB1-28
Melbourne, FL 32901
(407) 724-3739
FAX 407-724-3937

u.s. HEADQUARTERS

EUROPEAN HEADQUARTERS

Harris Semiconductor
1301 Woody Burke Road
Melboume, Florida 32902
TEL: (407) 724-3000

Harris Semiconductor
Mercure Centre
Rue de la Fusse 100
1130 Brussels, Belgium
TEL: (32) 2-246-21.11

SOUTH ASIA

Harris Semiconductor HK Ltd
13/F Fourseas Building
208-212 Nathan Road
Tsimshatsui, Kowloon
Hong Kong
TEL: (852) 3-723-6339

See our
specs in

NORTH ASIA

Harris KK
Shinjuku NS Bldg. Box 6153
2-4-1 Nishi-8hinjuku
Shinjuku-Ku, Tokyo 163 Japan
TEL: 81-3-345-8911

CApS
1\

Copyright @ Harris Corporation 1991
(All rights reserved)
Printed in U.s.A., 12/1991

Harris Semiconductor products are sold by description only. All specifications in this
product guide are applicable only to packaged products; specifications for die are
available upon request. Harris reserves the right to make changes in circuit design,
specifications and other information at any time without prior notice. Accordingly,
the reader is cautioned to verify that information in this publication is current
before placing orders. Reference to products of other manufacturers are solely
for convenience of comparison and do not imply total equivalency of design,
performance, or otherwise.

m

HARRIS

ii

FOR COMMERCIAL APPLICATIONS
Generallnformation

a

Microcontrollers •
Microprocessors
Customized Microcontrollers
a-Bit Bus Peripherals •
SPI Serial Bus Peripherals •
. Application Notes •

paCkaging.
Operating And Handling

8-3

Ordering Information
ROM Ordering Information

Sales Office Information •

ill

CDP6805 PRODUCT TECHNICAL ASSISTANCE
For technical assistance on the Harris products listed in this databook, please
contact Field Applications Engineering staff available at one of the following
Harris Sales Offices:

UNITED STATES
CALIFORNIA

San Jose .................. 408-922-0977
Woodland Hills ............ 818-992-0686

FLORIDA

Melbourne ................ 407-724-3576

GEORGIA

Norcross ..... '............. 404-246-4660

ILLINOIS

Schaumburg .............. 708-240-3480

MASSACHUSETTS

Burlington ................ 617-221-1850

NEW JERSEY

Mt. Laurel ................. 609-727-1909
Rahway ................... 201-381-4210

TEXAS

Dallas .................... 214-733-08oo

INTERNATIONAL
FRANCE

Paris ..................... 33-1-346-54046

GERMANY

Munich ................... 49-8-963-8130

ITALY

Milano .................... 39-2-262-0761

JAPAN

Tokyo .................... 81-3-345-8911

SWEDEN

Stockholm ................ 46-8-623-5220

U.K.

Camberley ................ 44-2-766-86886

For literature requests, please contact Harris Telemarketing at 407-724-3739.

iv

GENERAL INFORMATION
PAGE
Alpha Numeric Product Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-3

Product Index By Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-4

Product Overview ...............................................................................

1-5

Z

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< ....
a:<
w:;:

Za:
We

c::Iu..
Z

1-1

ALPHA NUMERIC PRODUCT INDEX
PAGE
CDP6402
CDP6402C

CMOS Universal Asynchronous Receiver/Transmitter (UART) ............... . 5-3

CDP65C51

CMOS Asynchronous Communications Interface Adapter (ACIA) ............ . 5-11

CDP6818

CMOS Real-Time Clock With RAM ...................................... . 5-29

CDP6818A

CMOS Real-Time Clock Plus RAM ...................................... . 5-48

CDP6823

CMOS Parallel Interface ................................................ . 5-67

CDP6853

CMOS Asynchronous Communications Interface Adapter (ACIA) ............ . 5-81
with MOTEL Bus

CDP6805E2, E2C
CDP6805E3, E3C

CMOS 8-Bit Microprocessor ........................................... . 3-16

CDP6805F2
CDP6805F2C

CMOS High Performance Silicon Gate 8-Bit Microcontroller ................ . 2-127

... S!
~~

CDP6805G2
CDP6805G2C

CMOS High Performance Silicon Gate 8-Bit Microcontroller ................ . 2-149

Za::

CDP68EM05C4
CDP68EM05C4N

CMOS High Performance Silicon Gate 8-Bit Microcontroller Emulator ....... . 3-3

CDP68EM05D2
CDP68EM05D2N

CMOS High Performance Silicon Gate 8-Bit Microcontroller Emulator ....... . 3-9

CDP68HC05CO

8-Bit Microcontroller .................................................. . 2-3

CDP68HC05C4, C8, C7
CDP68HCL05C4,C8,C7
CDf'68HSC05C4, C8, C7

8-Bit Microcontroller Series ............................................ . 2-5

CDP68HC05D2

HCMOS Microcontroller ............................................... . 2-77

CDP68HC05J3

8-Bit Microcontroller .................................................. . 2-123

CDP68HC05W4

8-Bit Microcontroller .................................................. . 2-125

CDP68HC68A2

CMOS Serial 1O-Bit A/D Converter ...................................... . 6-3

CDP68HC68P1

CMOS Single Port Input/Output. ........................................ . 6-19

CDP68HC68P2

CMOS Octal Serial Solenoid Driver ...................................... . 6-27

CDP68HC68Rl
CDP68HC68R2

CMOS 128 Word (CDP68HC68R1) and 256 Word (CDP68HC68R2) ........ . 6-32
By 8-Bit Static RAMs

CDP68HC68S1

Serial Bus Interface .................................................... . 6-38

CDP68HC68Tl

CMOS Real-Time Clock With RAM and Power Sense/Control .............. . 6-52

CDP68HC68T2

CMOS Real-Time Clock With Serial Peripheral Interface (SPI) Bus ........... . 6-70

CDP68HC68W1

Digital Pulse Width Modulator ........................................... . 6-72

Z

W:::IE

WCI

ClI ....

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1-3

. PRODUCT INDEX BY FAMILY
MICROCONTROLLERS

PAGE

CDP68HC05CO

8-Bit Microcontroller • • . . • • . . • . . • . . . . . . . • • . . . . • . . • . . . . . . . • . . . . . . . . . . . .. 2-3

CDP68HC05C4, C8, C7
CDP68HCL05C4, C8, C7
CDP68HSC05C4, C8, C7

8-Bit Microcontroller Series. . . . . . . • . • • . . . . . . . . . • • . • • . . . . . . . . . . . . . . . . . •. 2-5

CDP68HC05D2

HCMOS Microcontroller . •• . . . . •. . .. . .• . •. . • . . . .. . . . . . . . •. . . . . .. . . . . . .. 2-77

CDP68HC05J3

8-Bit Microcontroller . . . . . . • . . . • . . . . . • . . . . . . . . . . . . . • . . . . . . . . . . . . . . . • . .• 2-123

CDP68HC05W4

8-Bit Microcontroller . . . . • • . • . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-125

CDP6805F2
CDP6805F2C

CMOS High Performance Silicon Gate 8-Blt Mlcrocontroller ........•...... 2-127

CD P6805G 2
CDP6805G2C

. CMOS High Performance Silicon Gate 8-Bit Microcontroller ............... 2-149

MICROPROCESSORS
CDP68EM05C4
.CDP68EM05C4N

CMOS High Performance Silicon Gate 8-Bit Microcontroller Emulator. . . . . . . . . . .. 3-3

CD P68EM05D2
CDP68EM05D2N

' CMOS High Performance Silicon Gate 8-Bit Mlcrocontroller Emulator .. . • . . . . . . .. 3-9

CDP6805E2, E2C
CDP6805E3, E3C

CMOS 8-Bit Microprocessor. • . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-16

8-BIT BUS PERIPHERALS
CDP6402
CDP6402C

CMOS Universal Asynchronous Recelver/Transmitter (UART) . . . . . . . . . . . . . . . • . . .. 5-3

CDP65C51

CMOS Asynchronous Communications Interface Adapter (ACIA) . . . . . . . • • . . . . . . .. 5-11

CDP6818

CMOS Real-'Time Clock With RAM . . . . . • . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • . . .. 5-29

CDP6818A

CMOS Heal-Time Clock Plus RAM ••. . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-48

CDP6823

CMOS Parallel Interface ...........................................••........ 5-67

CDP6853

CMOS.Asynchronous Communications·lnterface Adapter (ACIA). . . . . . . . .. . . . . . .. 5-81
with MOTEL Bus

SPISERIAL BUS PERIPHERALS
CDP68HC68A2

CMOS Serial 1O-Blt NO Converter •....................•....•....•. , . . . . . . . .. 6-3

CDP68HC68P1

CMOS Single Port InpuVOutput. . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-19

• CDP68HC68P2

CMOS Octal Serial Solenoid Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . . . . . . .. 6-27

CD P68HC68R 1
CDP68HC68R2

CMOS 128 Word (CDP68HC68R1) and 256 Word (CDP68HC68R2) . . . . . . . . . . . .. 6-32
By 8-Bit Static RAMs

CDP68HC68S1

Serial Bus Interface. . . . • • . . . • • . . . . . • . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . •. 6-38

CDP68HC68T1

CMOS Real·Time Clock With RAM and Power Sense/Control ....•.............. 6-52

CDP68HC68T2

CMOS Real-Time ClocI< With Serial Peripheral Interface (SPI) Bus. . . . . . . . . . • . . . •• 6-70

CDP68HC68W1

Digital Pulse Width Modulator ................................................ 6-72

1-4

Product Overview
An all CMOS line of microprocessor, microcontroller and
peripheral integrated circuits for use in a broad range of
diverse industrial, consumer and military applications is
available. These devices offer the user all the advantages
unique to CMOS technology, including:
• Low Power Drain - makes CMOS integrated circuits a
natural choice for battery operated systems, battery
backed-up systems and systems in which heat dissipation is a prime consideration.
• High Noise Immunity and Wide Operating Temperature Range (Up To -SSoC to +12S 0 C)* - allows CMOS
integrated circuits to be used in the most demanding
industrial environments.
• Wide Operating Voltage Range - reduces the need for
expensive regulated power supplies and thereby allows
the design engineer greater freedom to concentrate on
other aspects of system design.

Surface Mounted Packages
The CMOS microprocessor/microcontroller/peripheral
product line now includes chips in a new generation of IC
miniaturized packages.
Microprocessors, microcontrollers and peripherals are now
offered in three versions of the surface mounted package
configuration as follows:
• Small Outline Package (SOP)
• Plastic Leaded Chip Carrier (PLCC)
• Metric Plastic Quad Flatpack (MPQFP)
The Small Outline Package (SOP) will be offered in 16, 20,
24 and 28 lead versions with 50 mil lead centers; the Plastic
Leaded Chip Carrier (PLCC) will be offered as 28 and 44
lead packages with 50 mil lead centers; and the Metric
Plastic Quad Flatpack (MPQFP) in a 44 lead version.
Enhanced Product

CDP680S Series (See Table 1)
The CDP6805 series offers a wide selection of 8-bit CMOS
microprocessors, microcontrollers and associated peripheral devices. The series is based on a familiar architecture,
optimized for controller applications. The architecture includes features such as on-chip timer/counter with interrupt, external interrupt, multiple subroutine nesting, true bit
manipulation, and an index register. Table I shows the wide
variety
of
6805
Series
microprocessors
and
microcontrollers available to the designer. In addition, the
6805 micros are supported by a broad line of CMOS
peripherals that include both serial and parallel bus
interfaces. The serial peripheral interface (SPI) featured on
most 6805 series microcontrollers is a full duplex, three
wire synchronous data transfer system. In addition, many
microcontroller types also utilize an on-chip UART to provide a full duplex asynchrounous serial communication
interface (SCI) featuring a standard non-return-to-zero
format and a variety of software programmable baud rates.
The series offers pin for pin replacements for Motorola's
MC146805 and MC68HC05 series of microprocessors,
microcontrollers and peripherals.

*

Most microprocessor, microcontroller and peripheral parts
are available with burn-in to enhance commercial reliability.
This cost effective approach is provided by the Enhanced
Product. Enhanced product is identified with the suffix 'X',
e.g., CDP68HC05C4EX.
68HCOS Core Macrocells
The development of application specific microcontrollers
based on the UH68HC05 core macrocells is supported. The
UH68HC05 is an enhanced version of the CDP68HC05
8-bit microcontroller architecture. Macrocore designs offer
many benefits, including improved system reliability,
reduced system cost, lower power consumption, and
reduced overall system size. Typical applications include
automotive instrument cluster, automotive cruise control,
security systems, telephones, pagers, sonar, printers,
scales, consumer electronics, modems and smart cards.
Several alternatives for supporting 68HC05 macrocore
hardware design and software development is offered.
Refer to "Customized Microcontrollers" in Section 4 of this
data book for more information.

Maximum Rating

1-5

Z

..... S!

C

I BIT (CC)

POWER· ON RESET

INTERRUPT
PIN

EXTERNAL RESET
EXTERNAL INTERRUPT
BBNG SERVICED
(READ OF VECTORS)

(al Interrupt Function Diagram

IRQ = u - - - t : - " I L - I H - - - - - . , U , . . - - - - -

I--IRQ1

~

t lUL

tlLlH

---I

====-',..---- }
r

IRQn°---------,L..-_ _ _ _...J

r

NORMALLY
USED WITH
WlRE·OREo
CONNECTION

IRQ ---.'L_ _ _ _ _ _ _ _ _--'
(MCU)

NOTE:

Serial Peripheral Interface (SPI) Interrupts

EXTERNAL
INTERRUPT
REQUEST

o

An interrupt In the serial peripheral interface (SPI) occurs when
one of the interrupt flag bits in the serial peripheral status
register (location $06) is set; provided the I bit in the condition
code register is clear and the enable bit in the serial peripheral
control register (location $OA) is enabled. When the interrupt is
recognized, the current state of the machine is pushed onto the
stack and the I bit in the condition code register is set. This

Edge-Sensitive Trigger Condition - The minimum pulse width (tILlH) is
either 125ns (VOO = 5V) or 250ns (VOO = 3V). The period tlLll should
not be less than the number of tcyc cycles H takes to execute the
interrupt service routine plus 21 tcyc cycles.
level-Sensitive Trigger Condition - H after servicing an interrupt the
IRQ remains low, then the next interrupt is recognized.

(bl Interrupt Mode Diagram
FIGURE 3-4.

• Refer to Table 3.2 for C7 locations.

2-20

EXTERNAL INTERRUPT

LOW POWER MODES
STOP Instruction
The STOP instruction places the MCU In its lowest power
consumption mode. In the STOP mode the internal oscillator is
turned off, causing all internal processing to be halted; refer to
Rgure 3-3. During the STOP mode, the I bit in the condition
code register is cleared to enable external Interrupts. All other
registers and memory remain unaltered and all input/output
lines remain unchanged. This continues until an external
interrupt (IRQ) or reset is sensed at which time the internal
oscillator Is turned on. The external interrupt or reset causes
the program counter to vector to memory location $1 FFA* and
$IFFB* or $1 FFE* and $1 FFF* which contains the starting
address of the interrupt or reset service routine respectively.

Internal clock remains active, and all CPU processing is
stopped; however, the programmable timer, serial peripheral
interface, and serial communications interface systems remain
active. Refer to Rgure 3-3. During the WAIT mode, the I bit in
the condition code register is cleared to enable all interrupts.
All other registers and memory remain unaltered and ali
parallel input/output lines remain unchanged. This continues
until any interrupt or reset is sensed. At this time the program
counter vectors to the memory location ($1 FF4 through
$1 FFF)* which contains the starting address of the interrupt or
reset service routine.
DATA RETENTION MODE

WAIT Instruction
The WAIT Instruction places the MCU in a low power
consumption mode, but the WAIT mode consumes somewhat
more power than the STOP mode. In the WAIT mode, the

The contents of RAM and CPU registers are retained at supply
voltages as low as 2 V dc. This is referred to as the DATA
RETENTION mode, where the data is held, but the device Is not
guaranteed to operate.

en

a:

~

CI

a:

I-

z

CI

.....
CI
a:
.....
iiE

*

Refer to Table 3.2 for C7 locations.

2-21

Programmable Timer
INTRODUCTION

The programmable timer, which is preceded by a fixed divideby-four prescaler, can be used for many purposes, including
input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from several
microseconds to many secods. A block diagram of the timer is
shown in Figure.4-1 and timing diagrams are shown In Figure
4-2 through 4-5.
Because the timer has a 16-bit architecture, each specific
functional segment (capability) is represented by two registers.
These registers contain the high and low byte of that functional
segment. Generally, accessing the low byte of a specific timer
function allows full control of that function; however, an access
of the high byte inhibits that specific timer function until the low
byte is also accessed.

reading the free running counter or counter alternate register, if
the most significant byte Is read, the least significant byte must
also be read In order to complete the sequence.
The free running counter is configured to $FFFC during reset
and is always a read-only register. During a power-on-reset
(POR), the counter Is also configured to $FFFC and begins
running after the oscillator startup delay. Because the free
running counter Is 16 bits preceded by a fixed dlvlde-by-four
prescaler, the value in the free running counter repeats every
262,144 MPU internal processor clock cycles. When the
counter rolls over from $FFFF to $0000, the timer overflow flag
(TO F) bit is set. An interrupt can also be enabled when counter
rollover occurs by setting its interrupt enable bit (TOlE).
OUTPUT COMPARE REGISTER

NOTE: The I bit in the condition code r.egister should be
set while .manipulating both the high and low byte
register of a speCific timer function to, ensure that an
interrupt does' not occur. This pr.events interrupts from
occurring between the time that the high and low bytes
are accessed.
The programmable timer capabilities are provided by using the
following ten addressable 8-bit registers (note the high and
low represent the significance of the byte). A description of
'each register is provided below.
Timer Control Register (TCR) locations $12,
Timer Status Register (TSR) location $13,
Input Capture High Register location $14,
Input Capture Low Register location $15,
Output Compare High Register location $16,
Output Compare Low Register location $17,
Counter High Register location $18,
Counter Low Register location $19,
Alternate Counter High Register location $1 A, and
Alternate Counter Low Register location $1 B.

The output compare register is a 16-bit register, which Is made
up of two 8-bit registers at locations $16 (most significant
byte) and $17 (least significant byte). The output compare register can be used for several purposes such as, controlling an
output waveform or Indicating when a period of time has
elapsed. The output compare register is unique in that all bits
are readable and writable and are not altered by the timer hardware. Reset does not affect the contents of this register and if
the compare function is not utilized, the two bytes of the output
compare register can be used as storage locations.
The contents of the output compare register are compared with
the contents of the free running counter once during every four
internal processor clocks. If a match is found, the corresponding output compare flag (OCF) bit is set and the corresponding
output level (OLVL) bit is clocked (by the output compare
circuit pulse) to an output level register. The values in the
output compare register and the output level bit should be
changed after each successful comparison in order to control
an output waveform or establish a new elapsed timeout. An
interrupt can also accompany a successful output compare
provided the corresponding interrupt enable bit, OCIE, is set.

COUNTER

The key element In the programmable timer is a 16-bit free
running counter, or counter register, preceded by a prescaler
which divides the Internal processor clock by four. The
prescaler gives ·the timer a resolution of 2.0 microseconds if
the internal processor clock is 2.0MHz. the counter Is clocked
to increasing values during the low portion of the internal
processor clock. Software can read the counter at any time
without affecting its value.
The double byte free running counter can be read from either
of two locations $18 - $19 (called counter register at this
location), or $1A - $1 B (counter alternate register at this
location). If a read sequence containing only a read of the least
significant byte of the free running counter or counter alternate
register first addresses the most significant byte ($18, $1A) it
causes the least significant byte ($19, $1 B) to be transferred to
a buffer. This buffer value remains fixed after the first most
significant byte "read" even if the user reads the most
significant byte several times. This buffer is accessed when

After a processor write cycle to the output compare register
containing the most significant byte ($16), the output compare
function Is inhibited until the least signigicant byte ($17) Is also
written. The user must write both bytes (locations) If the most
significant byte is written first. A write made only to the least
significant byte ($17) will not inhibit the compare function. The
free running counter is updated every four internal processor
clock cycles due to the Internal prescaler. The minimum time
required to update the output compare register is a function of
the software. program rather than the internal hardware.
A processor write may be made to either byte of the output
compare register without affecting the other byte. The output
level (OLVL) bit is clocked to the output level register regardless of whether the output compare flag (OCF) is set or clear.
Because neither the output compare flag (OCF bit) or output
compare register Is affected by reset, care must be exercised
when Initializing the output compare function with software.
The following procedure is recommended:

2-22

I

I

MCU INTERNAL BUS
INTERNAL
PROCESSOR
CLOCK
I

~4

I

f
8-BIT
BUFFER

I

I

If
HIGH
BYTE
$16
$17

LOW
BYTE

HIGH
BYTE

OUTPUT
COMPARE
REGISTER

LOW
BYTE

16-BIT FREE
RUNNING
COUNTER

LOW
BYTE

INPUT
CAPTURE
REGISTER

$18
$19

COUNTER
ALTERNATE
REGISTER

OUTPUT
COMPARE
CIRCUIT

HIGH
BYTE

$14
$15

$lA
$lB

OVERFLOW
DETECT
CIRCUIT

EDGE
DETECT
CIRCUIT

I
D

Q f--

>CLK
OUTPUT
LEVEL
REG.

TIMER
STATUS I
REG.

ICF

OCF

I TOF I

-

$13

----

I ICIE I OCIE I TOlE IIEDG

I

I

I
INTERRUPT
CIRCUIT

I
FIGURE 4-1.

C

OLVL

~
RESET

TIMER
CONTROL
REG.
$12

OUTPUT EDGE
LEVEL INPUT
{TCMP (TCAP
PIN 35) PIN 3 7)

I
PROGRAMMABLE TIMER BLOCK DIAGRAM

2-23

INTERNAL
PROCESSOR
CLOCK

I

TOO

INTERNAL
TIMER
CLOCKS

J1J1JhJi

TOl

Tl0

T1l

COUNTER
(lS-BIT)

I

1\11
I I I
1 I I 1
I
I
1
I
I
I
1
1
1
I
I

(INTERNAL
RESET)

n
I

+
!I/I/Il

n

n

n

n

X

I

RESET
(EXTERNAL OR
ENDOFPOR)

I
1
1 1
1 1
1 I
I
1
1 1
I
I
I
I
I I I
1
1
,

n
n

n

X

$FFFD

n

n
IL

X

$FFFE

$FFFF

NOTE: The Counter Register and Timer Control Register are the only ones affected by RESEr.
FIGURE 4-2_

TIMER STATE TIMING DIAGRAM FOR RESET

INTERNAL
PROCESSOR
CLOCK

n

TOO

INTERNAL
TIMER
CLOCKS

T01~

n

T10

Tll

COUNTER
(1S-BIT)

INPUT
EDGE

INTERNAL
CAPTURE
LATCH
INPUT
CAPTURE
REGISTER

$FFEB

n
n

n

X

n

$FFEC

n
n

n

X

n

$FFED

i

X

I

n
n

n

IL
$FFEE

X

$FFEF

II LIILrZZEZIl I

,. . T'""T"
yyy
""'~

I

$7711

\
X

$FFED

/

INPUT
CAPTURE
FLAG

NOTE: If the Input edge occurs In the shaded area from one timer - . T10 to the other timer state T10 the Input capture flag Is set during the next state T11.
FIGURE 4-3_

TIMER STATE TIMING DIAGRAM FOR INPUT CAPTURE

2-24

INTERNAL
PROCESSOR
CLOCK

n

TOO

INTERNAL
TIMER
CLOCKS

T01~

n

Tl0

n

Tll

COUNTER
(16-BIT)

COMPARE
REGISTER

$FFEB

n

X

n
n

n

X

$FFEC

n

n
n

n

X

$FFEO

(NOTE1)~

n
IL

X

$FFEE

$FFEF

~r-----------------$-F-FE-O------------------

------------C-P-U--W-R-IT-E-S-$-F-F-E-0------

(NOTE2)~

COMPARE
REGISTER
LATCH

n

I

\'----

OUTPUT COMPARE
FLAG (OCF) AND
TCMP (PIN 35)
NOTES:

1. The CPU wrfte to the compare regislar may take place at any time, but a compare only occurs aI timer state T01. Thus, a 4-cycle difference may exist
between the write to the compare register and the actual compare.
2. Internal compare takes place during timer state T01.

3. OCF is set at the timer state T11 which follows the comparison match ($FFED in this example).
FIGURE 4-4.

TIMER STATE TIMING DIAGRAM FOR OUTPUT COMPARE

INTERNAL
PROCESSOR
CLOCK

n

TOO

INTERNAL
TIMER
CLOCKS

T01~

n

Tl0

Tll

COUNTER
(16-BIT)

$FFFE

n

X

$FFFF

n

n
n

n

X

$0000

n

n
n

n

X

I

n

n
IL

$0001

X

$0002

/

TIMER OVERFLOW
FLAG (TOFI

NOTE: The TOF bft is set at timer stale T11 (transition of counter from SFFFF to SoooO). It is cleared by a read of the timer status register during the internal
processor clock high time followed by a read of the counter low register.
FIGURE 4-5.

TIMER STATE DIAGRAM FOR TIMER OVERFLOW

2-25

(1)

Write the high byte of the output compare register to
inhibit further compares until the low byte is written.

(2)

Read the timer status register to arm the OCF if it is
already set

(3)

Write the output compare register low byte to enable the
output compare function with the flag clear.

The advantage of this procedure is to prevent the OCF bit from
being set between the time it is read and the write to the output
compare register. A software example Is shown below.
B716

STA

OCMPHI;

INHIBIT OUTPUT COMPARE

B613

LOA

TSTAT;

ARM OCF BIT IF SET

BF17

STX

OCMPLO;

READY FOR NEXT COMPARE

free running counter are the only sections of the timer affected
by reset The TCMP pin Is forced low during external reset and
stays low until a valid compare changes it to a high. The timer
control register is illustrated below followed be a definition of
each bit
7

IICIE

6

I I I
OCIE TOlE

The result obtained by an input capture will be one more than
the value of the free running counter on the rising edge of the
internal processor clock preceding the external transition (refer
to timing diagram shown in Figure 4-3). This delay Is required
for Internal synchronization. Resolution is affected by the
prescaler allowing the timer to only Increment every four
Internal processor clock cycles.
After a read of the most significant byte of the Input capture
register ($14), counter transfer is inhibited until the least significant byte ($15) of the input capture register is also read. This
characteristic forces the minimum pulse period attainable to be
determined by the time used in the capture software routine
and Its interaction with the main program. The free running
counter Increments every four internal processor clock cycles
due to the prescaler.
A read of the least significant byte ($15) of the input capture
register does not Inhibit the free running counter transfer.
Again, minimum pulse periods are ones which allow software
to read the least significant byte ($15) and perform needed
operations. There is no conflict between the read of the input
capture register and the free running counter transfer since
they occur on opposite edges of the internal processor clock.
TIMER CONTROL REGISTER (TCR)
The timer control register (TCR, location $12) is an a-bit read!
write register which contains five control bits. Three of these
bits control Interrupts associated with each of the three flag
bits found in the timer status register (discussed below). The
other two bits control: 1) which edge is significant to the capture edge detector (i.e., negative or positive), and 2) the next
value to be clocked to the output level register In response to a
successful output compare. The timer control register and the

4

3

0

o

2

o

B7,ICIE

If the input capture interrupt enable (ICIE) bit
is set, a timer interrupt Is enabled when the ICF
status flag (In the timer status register) Is set
If the ICIE bit is clear, the interrupt is inhibited.
The ICIE bit Is cleared by reset

B6,OCIE

If the output compare interrupt enable (OCIE)
bit Is set, a timer interrupt is enabled whenever
the OCF status flag Is set. If the OCIE bit is
clear, the interrupt is inhibited. The OCIE bit is
cleared by reset.

B5,TOIE

If the timer overflow interrupt enable (TOlE)
bit is set, a timer interrupt is enabled whenever
the TOF status flag (in the timer status
register) is set If the TOlE bit is clear, the
Interrupt Is Inhibited. The TOlE bit is cleared
by reset

B1,IEDG

The value of the input edge (IEDG) bit
determines which level transition on pin 37 will
trigger a free running counter transfer to the
input capture register. Reset does not affect
thelEDG bit
o negative edge
1 = positive edge

INPUT CAPTURE REGISTER
The two a-bit registers which make up the 16-bit Input capture
register are read-only and are used to latch the value of the
free running counter after a defined transition is sensed by the
corresponding input capture edge detector. The level transition
which triggers the counter transfer is defined by the
corresponding input edge bit (IEDG). Reset does not affect the
contents of the Input capture register.

5

=

BO,OLVL

The value of the output level (OLVL) bit is
clocked into the output level register by the
next successful output compare and will appear
at pin 35. This bit and the output level register
are cleared by reset.
o = low output
1 = high output

TIMER STATUS REGISTER (TSR)
The timer status register (TSR) Is an a-bit register of which the
three most significant bits contain read-only status Information. These three bits indicate the following:
1) A proper transition has taken place at pin 37 with an
accompanying transfer of the free running counter contents
to the input capture register,
2) A match has been found between the free running counter
and the output compare register, and
3) A free running counter transition from $FFFF to $0000 has
been sensed (timer overflow).

2-26

The timer status register is illustrated below followed by a
definition of each bit. Refer to timing diagrams shown in
Figures 4-2, 4-3, and 4-4 for timing relationship to the timer
status register bits.
6

7

ICF

5

IOCF ITOF I

4

3

2

0

o

o

o

o

o

$13

B7,ICF

The input capture flag (ICF) is set when a
proper edge has been sensed by the input
capture edge detector. It is cleared by a
processor access of the timer status register
(with ICF set) followed by accessing the low
byte ($15) of the input capture register. Reset
does not affect the input compare flag.

B6,OCF

The output compare flag (OCF) is set when
the output compare register contents match
the contents of the free running counter. The
OCF is cleared by accessing the timer status
register (with OCF set) and then accessing the
low byte ($17) of the output compare register.
Reset does not affect the output compare flag.

B5,TOF

The timer overflow flag (TOF) bit is set by a
transition of the free running counter from
$FFFF to $0000. It is cleared by accessing the
timer status register (with TOF set) followed
by an access of the free running counter least
significant byte ($19). Reset does not affect
theTOFbit.

2-27

Accessing the timer status register satisfies the first condition
required to clear any status bits which happen to be set during
the access. The only remaining step is to provide an access of
the register which is associated with the status bit. Typically,
this presents no problem for the input capture and output
compare functions.
A problem can occur when using the timer overflow function
and reading the free running counter at random times to
measure an elapsed time. Without incorporating the proper
precautions into software, the timer overflow flag could
unintentionally be cleared if: 1) the timer status register is
read or written when TOF is set, and 2) the least significant
byte of the free running counter Is read but not for the purpose
of servicing the flag. The counter alternate register at address
$1A and $1B contains the same value as the free running
counter (at address $18 and $19); therefore, this alternate
register can be read at any time without affecting the timer
overflow flag In the timer status register.
During STOP and WAIT Instructions, the programmable timer
functions as follows: during the wait mode, the timer continues
to operate normally and may generate an interrupt to trigger
the CPU out of the wait state; during the stop mode, the timer
holds at Its current state, retaining all data, and resumes
operation from this point when an external Interrupt is received.

Serial Communications Interface (SCI)
INTRODUCTION
A full-duplex asynchronous serial communications interface
(SCI) Is provided with a standard NRZ format and a variety of
baud rates. The SCI transmitter and receiver are functionally
independent, but use the same data format and bit rate. The
serial data format is standard mark/space (NRZ) which provide
one start bit, eight or nine data bits, and one stop bit. "Baud"
and "bit rate" are used synonymously In the following
description.

1. A high level indicates a logiC one and a low level Indicates
a logic zero.
2.

The idle line is In a high (logiC one) state prior to transmission/reception of a message.

3.

A start bit (logiC zero) is transmitted/received indicating the
start of a message.

4.

The data is transmitted and received least-signlficant-bit
first

• Standard NRZ (mark/space) format

5.

• Advanced error detection method includes noise detection
for noise duration of up to 1/16 bit time.

A stop bit (high In the tenth or eleventh bit position)
indicates the byte is complete.

6.

A break is defined as the transmission or reception of a low
(logiC zero) for some multiple of the data format.

SCI Two Wire System Features

• Full-duplex operation (simultaneous transmit and receive)
• Software programmable for one of 32 different baud rates
• Software selectable word length (eight or nine bit words)

CONTROL BIT V
SELECTS 8 OR

• Separate transmitter and receiver enable bits.

an DATA

o

• SCI may be interrupt driven

I I

IDLE UNE

• Four separate enable bits available for interrupt control

1

2

3

4

5

6

7

0

S

T

o

A

P

R

• Receiver wake-up function (idle or address bit)

6

I ,I I I I I I-I C

S
T

SCI Receiver Features

a

~

T

S

T
A
R
T

• Idle line detect
• Framing error detect
- Stop bit is always high.

• Noise detect

FIGURE 5-1.

• Overrun detect

DATA FORMAT

• Receiver data register full flag

WAKE-UP FEATURE

SCI Transmitter Features

DATA FORMAT

In a typical multiprocessor configuration, the software protocol
will usually identify the addressee{s) at the beginning of the
message. In order to permit uninterested MPUs to ignore the
remainder of the message, a wake-up feature is included
whereby all further SCI receiver flag (and interrupt) processing
can be inhibited until its data line returns to the idle state. An
SCI receiver is re-enabled by an idle string of at least ten (or
eleven) consecutive ones. Software for the transmitter must
provide for the required idle string between consecutive
messages and prevent it from occurring within messages.

Receive data in (ROI) or transmit data out (TOO) is the serial
data which is presented between the internal data bus and the
output pin (TOO), and between the input pin (ROI) and the
internal data bus. Data format is as shown for the NRZ in
Figure 5-1 and must meet the following criteria:

The user is allowed a second method of providing the wake-up
feature in lieu of the idle string discussed above. This method
allows the user to insert a logiC one in the most significant bit of
the transmit data word which needs to be received by all
"sleeping" processors.

• Transmit data register empty flag
• Transmit complete flag
• Break send
Any SCI two-wired system requires receive data in (ROI) and
transmit data out (TOO).

2-28

RECEIVE DATA IN
Receive data in is the serial data which is presented from the
input pin via the SCI to the internal data bus. While waiting for a
start bit, the receiver samples the input at a rate which is 16
times higher than the set baud rate. this 16 times higher-thanbaud rate is referred to as the RT rate in Figures 5-2 and 5-3,
and as the receiver clock in Figure 5-7. When the input (idle)
line is detected low, it is tested for three more sample times
(referred to as the start edge verification samples in Figure
5-2). If at least two of these three verification samples detect a
logic low, a valid start bit is assumed to have been detected (by
a logic low following the three start qualifiers) as shown in
Figure 5-2; however, if in two or more of the verification
samples a logic high is detected, the line is assumed to be idle.
(A noise flag is set if one of the three verification sample
detects a logic high, thus a valid start bit could be assumed
and a noise flag still set.) The receiver clock generator is
controlled by the baud rate register (see Figures 5-6 and 5-7);
however, the serial communications interface is synchronized
by the start bit (independent of the transmitter).
Once a valid start bit is detected, the start bit, each data bit,
and the stop bit are sampled three times at RT intervals of aRT,
9RT, and 1ORT (1 RT is the position where the bit is expected to
start as shown in Figure 5-3. The value of the bit is determined
by voting logic which takes the value of the majority of samples
(two or three out of three). A noise flag is set when all three
samples on a valid start bit or a data bit or the stop bit do not
agree. (As discussed above, a noise flag is also set when the
start bit verification samples do not agree).

PREVIOUS BIT

PRESENT BIT

SAMPLES

v

RDI
16

R

T

1

R

T

FIGURE 5-3.

NEXT BIT

v

v

8

9

R
T

R
T

10
R
T

16

R

T

SAMPLING TECHNIQUE USED ON ALL BITS

START BIT DETECTION FOLLOWING
A FRAMING ERROR
If there has been a framing error without detection of a break
(10 zeros for a-bit format or 11 zeros for 9-bit format), the
circuit continues to operate as if there actually were a stop bit
and the start edge will be placed artificially. the last bit received
in the data shift register is inverted to a logic one, and the three
logic one start qualifiers (shown in Figure 5-2) are forced into
the sample shift register during the interval when detection of a
start bit is anticipated (see Figure 5-4); therefore the start bit
will be accepted no sooner than it is anticipated.

=

=

H the receiver detects that a break (RDRF 1, FE 1, receiver
data register = $00) produced the framing error, the start bit
will not be artificially induced and the receiver must actually
receive a logiC one bit before start. See Figure 5-5.

16.x INTERNAL SAMPUNG CLOCK

1
R
T

RT CLOCK EDGES (FOR AU. THREE EXAMPLES)

3
R
T

2
R
T

5
R
T

4
R
T

6
R
T

7
R
T

RDll
START
1

1

1

0

'-----v---'

.

0

0

0

V'
START EDGE VERIFICATION SAMPLES

START
QUAUAERS

NOISE

IDLE
RD12

START

0

0

n

0

__
ID_LE
_ _ _ _ _ _ _ _-.NOISEi-_ _ _ _ _ _ _ _ _ _-.
RD13

U

START

o

FIGURE 5-2.

1

R

T

o

o

EXAMPLES OF START BIT SAMPLING TECHNIQUE

2-29

o

o

8
R
T

REGISTERS
There are five different registers used in the serial communications interface (SCI) and the internal configuration of these
registers is discussed in the following paragraphs. A block
diagram of the SCI system is shown in Figure 5-6.

B7,Ra

If the M bit is a one, then this bit provides a
storage location for the ninth bit In the receive
data byte. Reset does not affect this bit.

B6,T8

If the.M bit is one, then this bit provides a
storage locations for the ninth bit in the transmit data byte. Reset does not affect this bit.

B4,M

The option of the word length is selected by the
configuration of this bit and is shown below.
Reset does not affect this bit.
o "" 1 start bit, 8 data bits, 1 stop bit
1 "" 1 start bit, 9 data bits, 1 stop bit

B3,WAKE

This bit allows the user to select the method for
receiver "wake up". If the WAKE bit is a logiC
zero, an idle line condition will "wake up" the
receiver. If the WAKE bit is set to a logic one,
the system acknowledges an address bit (most
significant bit). The address bit is dependent on
both the WAKE bit and the M bit level (table
shown below). (Additionally, the receiver does
not use the wake-up feature unless the RWU
control bit in serial communications control
register 2 is set as discussed below). Reset
does not affect this bit.

Serial Communications Data Register (SCDAT)
7

6

5

4

3

2

o
$11

Serial Communications Data Register

The serial communications data register performs two
functions in the serial communications interface; i.e. it acts as
the receive data register when it is read and as the transmit
data register when it is written. Figure 5-6 shows the register
as two separate registers, namely: the recieve data register
(RDR) and the transmit data register (TDR). As shown in Figure
5-6, the TDR (transmit data register) provides the parallel
. interface from the internal data bus to the transmit shift register
and the receive data register (RDR) provides the interface from
the receive shift register to the internal data bus.
When SCDAT is read, it becomes the receive data register and
contains the last byte of data received. The receive data
register, represented above, is a read-only register containing
the last byte of data received from the shift register for the
internal data bus. The RDRF bit (receive data register full bit in
the serial communications status register) is set to indicate that
a byte has been transferred from the input serial shift register
to the serial communications data register. The transfer is
synchronized with the receiver bit rate clock (from the receive
control) as shown in Figure 5-6. All data is received leastsignificant-bit first.
When SCDAT is written, it becomes the transmit data register
and contains the next byte of data to be transm itted. the
transmit data register, also represented above, is a write-only
register containing the next byte of data to be applied to the
transmit shift register from the internal data bus. As long as the
transmitter is enabled, data stored in the serial
communications data register is transferred to the transmit
shift register (after the current byte in the shift register has
been transmitted). The transfer from the SCDAT to the transmit
shift register is synchronized with the bit rate clock (from the
transmit control). as shown in Figure 5-6. All data is transmitted
least-significant-bit first.

WAKE

M

METHOD OF RECEIVER "WAKE-UP"

0

X

Detection of an idle line allows the next data byt"
received to cause the receive data register to fill
and produce an RDRF flag.

1

0

Detection of a received one in the eighth data bit
allows an RDRF flag and associated error flags.

1

1

Detection of a received one in the ninth data bit
allows an RDRF flag and associated error flags.

~DATA--i_­

I

6

R8

T8

5

432

I

~

-----, /

RECEIVE
DATA IN - - l

i

-Ht

ARTIFICIAL
EDGE

r----

START BIT

I

r-DATA~

DATA SAMPLES

Serial Communications Control Register 1 (SCCR1)
7

EXPECTED
STOP

(al

Case 1, 'Recelve Line Low During Artificial Edge

o
~DATA--i~

$OE

RECEIVE ~
DATA IN

The serial communications control register
(SCCR1)
provides the control bits which: 1) determine the word length
(either 8 or 9 bits), and 2) selects the method used for the
wake-up feature. Bits 6 and 7 provide a location for storing the
ninth bit for longer bytes.

~I

U

-ttt

DATA SAMPLES

(b)

START EDGE

I~TARTBITI

r-

DATA- -

Case 2, Receive Line High During Expected Start Edge
FIGURE 5-4.

2-30

EXPECTED
STOP

SCI ARTIFICIAL START FOLLOWING
A FRAMING ERROR

Serial Communications Control Register 2 (SCCR2)
7
TIE

6

I I
TCIE

5

4

3

2

RIE

ILiE

TE

RE

0

I I I
RWU

SBK

When the receive enable bit is set, the receiver
is enabled. When RE is clear, the receiver is
disabled and all of the status bit associated with
the receiver (RDRF, IDLE, OR, NF, and FE)
are inhibited. Reset clears the RE bit.

B1,RWU

When the receiver wake-up bit is set, it enables
the "wake up" function. The type of "wake up
mode for the receiver is determined by the
WAKE bit discussed above (in the SCCR1).
When the RWU bit is set, no status flags will be
set. Flags which were set previously will not be
cleared when RWU is set. If the WAKE bit is
cleared, RWU is cleared after receiving
10(M "" 0) or 11(M "" 1) consecutive ones.
Under these conditions, RWU cannot be set if
the line is idle. If the WAKE bit is set, RWU is
cleared after receiving an address bit. The
RDRF flag will then be set and the address byte
will be stored in the receiver data register. Reset
clears the RWU bit.

$OF

The serial communications control register 2 (SCCR2)
provides the control bits which: individually enable/disable the
transmitter or receiver, enable the system interrupts, and
provide the wake-up enable bit and a "send break code" bit.
Each of these bits is described below. (The individual flags are
discussed in the Serial Communications Status Register
Section.)
B7,TIE

When the transmit interrupt enable bit is set,
the SCI interrupt occurs provided TDRE is set
(see Figure 5-6). When TIE is clear, the TDRE
interrupt is disabled. Reset clears the TIE bit.

B6, TCIE

When the transmission complete interrupt
enable bit is set, the SCI interrupt occurs
provided TC is set (see Figure 5-6). When TCIE
is clear, the TC interrupt is disabled. Reset
clears the TCIE bit.

B5,RIE

B2,RE

When the send break bit is set the transmitter
sends zeros in some number equal to a multiple
of the data format bits. If the SBK bit is toggled
set and clear, the transmitter sends 10(M "" 0)
or 11 (M "" 1) zeros and then reverts to idle or
sending data. The actual number of zeros sent
when SBK is toggled depends on the data
format set by the M bit in the serial communications control register 1; therefore, the break
code will be synchronous with respect to the
data stream. At the completion of the break
code, the transm itter sends at least one high
bit to guarantee recognition of a valid start bit.
Reset clears the SBK bit.

BO,SBK

When the receive interrupt enable bit is set, the
SCI interrupt occurs provided OR is set or
RDRF is set (see Figure 5-6). When RIE is
clear, the OR and RDRF interrupts are disabled.
Reset clears the RIE bit.

B4,ILlE

When the idle line interrupt enable bit is set, the
SCI interrupt occurs provided IDLE is set (see
Figure 5-6). When ILiE is clear, the IDLE
interrupt is disabled. Reset clears the ILiE bit.

B3,TE

When the transmit enable bit is set, the transmit
shift register output is applied to the TDO line.
Depending on the state of control bit M in serial
communications control register 1, a preamble
of 10 (M = 0) or 11(M '" 1) consecutive ones is
transmitted when software sets the TE bit from
a cleared state. If a transmission is in progress,
and TE is written to a zero, then the transmitter
will wait until after the present byte has been
transmitted before placing the TDO pin in the
idle high-impedance state. If the TE pin has
been written to a zero and then set to a one
before the cu rrent byte Is transm itted, the
transmitter will wait until that byte is
transmitted and will then initiate transmission
of a new preamble. After the preamble is
transmitted, and provided the TDRE bit is set
(no new data to transmit), the line remains idle
(driven high while TE "" 1); otherwise, normal
transmission occurs. This function allows the
user to "neatly" terminate a transmission seQuence. After loading the last byte in the serial
communications data register and receiving the
interrupt from TDRE, indicating the data has
been transferred into the shift register, the user
should clear TE. The last byte will then be transmitted and the line will go idle (high impedance).
Reset clears the TE bit.

~

EXPECTED ~
STOP

--- BREAK--~----..,
RECEIVE ......,..,...,.._ _-..,..,...,.......J

DATA IN

2-31

tH

tH

-......-

--.,.-

t

t

DATA SAMPLES

FIGURE 5-5.

I

I

DETECTED AS
VAUD START
EDGE

ttt -.....HH t t,
-----t

START
OUAUFIER

START BITI

START EDGE
VERIFICATION
SAMPLER

SCI START BIT FOLLOWING A BREAK

CI)

a:

....
....
LU

o
a:
~

:z:

o

<.:I

o
a:

<.:I

il

....

.A

~

SCI INTERRUPT

TRANSMIT
DATA
REGISTER

/

W

}

(SEE
NOTE)

I"'"

(SEE
NOTE)

TIE

~

RECEIVE
DATA
REGISTER
.II

RIE

,~

-

r--

-

~

SBK

-

RECEIVE
DATA
SHIFT
REGISTER

RWU

r

IFE

I

I

I

-

RDI(PDO,
PIN 29)

I'

OR

~

TE
RE

NF

$11

IUE

-

TRANSMIT
DATA
SHIFT
REGISTER

"

$OF
SCCR2

TCIE

r+ TDO
(PD1,
PIN 30)

.......

/~

A

v"
$11

INTERNAL BUS

I' 2

I IDLE 1RDRF

TC

TDRE

I

1SCSR
$10

i
WAKE
UP
UNIT

SBK

I' ~

TE

FLAG
CONTROL

YTRANSMIT
CONTROL

RECEIVE I
CONTROL I

1
INTERNAL

I

RATE GENERATOR

1_ PROCESSOR
CLOCK

$OD

I -

$OE

I

BAUD

- I SCP11 SCPO - I SCR21 SCRl I SCRO I RATE
REGISTER
I

R8

T8

- I

M

1WAKE 1 - I - I - I

SCCR1

1
NOTE: The Serial Communications Data Reglsler (SCDAT) is conlrolled by the Internal RIW signal. II ialhe transmit dala registet when wrKIen and receive data
register when reed.

FIGURE 5-8.

SERIAL COMMUNICATIONS INTERFACE BLOCK DIAGRAM

2-32

Serial Communications Status Register (SCSR)
7

6

543

!TORE! TC !RORF !IOLE ! OR

o

2
NF

FE

B4,IDLE

When the idle line detect bit is set, it indicates
that a receiver idle line is detected (receipt of a
minimum number of ones to constitute the
number of bits in the byte format). The minimum
number of ones needed will be 10(M = 0) or
11 (M = 1). Th is allows a receiver that is not in
the wake-up mode to detect the end of a
message, detect the preamble of a new
message, or to resynchronize with the
transmitter. The IDLE bit is cleared by accessing the serial communications status register
(with IDLE set) followed by a read of the serial
communications data register. The IDLE bit will
not be set again until after an RDRF has been
set; i.e., a new idle line occurs. The IDLE bit is
not set by an idle line when the receiver "wakes
up" from the wake-up mode. Reset clears the
IDLE bit.

B3,OR

When the overrun error bit is set, it indicates
that the next byte is ready to be transferred
from the receive shift register to the serial
communications data register when it is already
full (RDRF bit is set). Data transfer is then
inhibited until the RDRF bit is cleared. Data in
the serial communications data register is valid
in this case, but additional data received during
an overrun condition (including the byte causing the overrun) will be lost. The OR bit is
cleared when the serial communications status
register is accessed (with OR set), followed by a
read of the serial communications data register.
Reset clears the OR bit.

$10

The serial communications status register (SCSR) provides
inputs to the interrupt logic circuits for generation of the SCI
system interrupt. In addition, a noise flag bit and a framing error
bit are also contained in the SCSR.
B7, TDRE

B6, TC

The transmit data register empty bit is set to
indicate that the contents of the serial communications data register have been transferred
to the transmit serial shift register. If the TDRE
bit is clear, it indicates that the transfer has not
yet occurred and a write to the serial communications data register will overwrite the previous
value. The TDRE bit is cleared by accessing
the serial communications status register (with
TDRE set), followed by writing to the serial
communication data register. Data can not be
transmitted unless the serial communications
status register is accessed before writing to the
serial communications data register to clear the
TDRE flag bit. Reset sets the TDRE bit.
The transmit complete bit is set at the end of a
data frame, preamble, or break condition if:
1. TE = 1, TDRE = 1, and no pending data,
preamble, or break is to be transmitted; or
2. TE = 0, and the data, preamble, or break
(in the transmit shift register) has been
transmitted.
The TC bit is a status flag which indicates that
one of the above conditions has occurred. The
TC bit is cleared by accessing the serial
communications status register (with TC set),
followed by writing to the serial communications data register. It does not inhibit the
transmitter function in any way. Reset sets the
TCbit.

B5, RDRF

B2,NF

When the receive data register full bit is set, it
indicates that the receiver serial shift register
is transferred to the serial communications data
register. If multiple errors are detected in any
one received word, the NF, FE, and RDRF bits
will be affected as appropriate during the same
clock cycle. The RDRF bit is cleared when the
serial communications status register is
accessed (with RDRF set) followed by a read of
the serial communications data register. Reset
clears the RDRF bit.

2-33

The noise flag bit is set if there is noise on a
"valid" start bit or if there is noise on any of the
data bits or if there is noise on the stop bit. It is
not set by noIse on the idle line nor by invalid
(false) start bIts. If there is noise, the NF bit is
not set until the RDRF flag is set. Each data bit
is sampled three times as described above in
RECEIVE DATA IN and shown in Figure 5-3.
The NF bit represents the status of the byte in
the serial communications data register. For the
byte being received (shifted in) there will also be
a "working" noise flag the value of which will be
transferred to the NF bIt when the serIal data is
loaded into the serial communications data
register. The NF bit does not generate an interrupt because the RDRF bit gets set with NF and
can be used to generate the interrupt. The NF
bit is cleared when the serial communications
status register is accessed (with N F set),
followed by a read of the serial communications
data register. Reset clears the NF bit.

~

~
.....

c
a:

I-

z

C
c.:I

c
a:

c.:I

:E

B1,FE

The framing error bit is set when the byte
boundaries in the bit stream are not synchronized with the receiver bit counter (generated
by a "lost" stop bit). The byte is transferred to
the serial communications data register and the
RDRF bit is set. The FE bit does not generate an
interrupt because the RDRF bit is set at the
same time as FE and can be used to generate
the interrupt. Note that if the byte received
causes a framing error and it will also cause an
overrun if transferred to the serial communications data register, then the overrun bit will
be set, but not the fram ing error bit, and the
byte will not be transferred to the serial
communications data register. The FE bit is
cleared when the serial communications status
register is accessed (with FE set) followed
by a read of the serial communications data
register. Reset clears the FE bit.

Baud Rate Register
6

7

543

2

1

0

I I I
SCP1 SCPO

The baud rate register provides the means for selecting
different baud rates which may be used as the rate control for
the transmitter and receiver. The SCPO - SCP1 bits function as
a prescaler for the SCRO - SCR2 bits. Together, these five bits
provide multiple, baud rate combinations for a given crystal
frequency.
B5,SCP1
B4,SCPO

These two bits in the baud rate register are
used as a prescaler to increase the range of
standard baud rates controlled by the SCRO SCR2 bits. A table of the prescaler internal
processor clock division versus bit levels is
provided below. Reset clears SCP1 - SCPO bits
(divide-by-one).

SCR1

SCRO

PRESCALER OUTPUT
DIVIDE BY

0

0

0

1

0

0

1

2

0

1

0

4

0

1

1

6

1

0

0

16

1

0

1

32

1

1

0

64

1

1

1

128

The diagram of Figure 5-7 and Tables 5-1 and 5-2 illustrate
the divided chain used to obtain the baud rate clock (transmit
clock). Note that there is a fixed rate divide-by-16 between the
receive clock (RT) and the transmit clock (Tx). The actual
divider chain is controlled by the combined SCPO - SCP1 and
SCRO - SCR2 bits in the baud rate register as illustrated. All divided frequencies shown in the first table represent the final
transmit clock (the actual baud rate) resulting from the internal
processor clock division shown in the "divide-by" column only
(prescaler division only). The second table illustrates how the
prescaler output can be further divided by action of the SCI select bits (SCRO - SCR2). For example, assume that a 9600Hz
baud rate is required with a 2.4576MHz external crystal. In this
case the prescaler bits (SCPO - SCP1) could be configured as
a divide-by-one or a dlvide-by-four. If a divide-by-four
prescaler is used, then the SCRO - SCR2 bits must be
configured as a divide-by-two. This results in a divide-by-128
of the internal processor clock to produce a 9600Hz baud rate
clock. USing the same crystal, the 9600 baud rate can be obtained with a prescaler divide-by-one and the SCRO - SCR2
bits configured for a dlvlde-by-eight.
NOTE: The crystal frequency is internally divided-by-two to
generate the internal processor clock.

INTERNAL PROCESSOR
CLOCK DIVIDE BY

SCP1

SCPO

0

0

1

0

1

3

1

0

4

1

1

13

B2,SCR2
B1,SCR1
BO,SCRO

SCR2

OSCIUATOR
FREQUENCY

These th ree bits in the baud rate register are
used to select the baud rates of both the
transmitter and receiver. A table of baud rates
versus bit levels is shown below. Reset does
not affect the SCR2 - SCRO bits.

ch-

2-34

SCPO- SCP1
PRESCALER
CONTROL
+N

FIGURE 5-7.

SCRO- SCR2
SCI SELECT
RATE
CONTROL
+M

SCI
, RECEIVE
CLOCK (AT)

RATE GENERATOR DIVISION

TABLE 5-~.

SCPBIT

PRESCALER HIGHEST BAUD RATE FREQUENCY OUTPUT

CRYSTAL FREQUENCY MHz

CLOCK·
DIVIDED BY

8.0t

4.194304

4.0

2.4576

2.0

1.8432

0

1

250.000 kHz

131.072 kHz

125.000 kHz

76.80 kHz

62.50 kHz

57.60 kHz

1

3

83.332 kHz

43.691 kHz

41.666 kHz

25.60 kHz

20.833 kHz

19.20 kHz

1

0

4

62.500 kHz

32.768 kHz

31.250 kHz

19.20 kHz

15.625 kHz

14.40 kHz

1

1

13

19.200 kHz

10.082 kHz

9600Hz

5.907 kHz

4800Hz

4430Hz

1

0

0
0

• The clock in the "CLOCK DIVIDED BY" column is the internal processor clock.

t

CDP6BHSC05C4. CDP6BHSC05CB. CDP6BHSC05C7 types.

NOTE:

The divided frequencies shown In Table 5-1 represent baud rates which are the highest transmH baud rate (Tx) that can be obtained by a specific crystal
frequency and only using the prescaler division. Lower baud rates may be obtained by providing a further diviSion using the SCI rate select bits as shown
below for some representative prescaler outputs.

en

a:
w

::l
CI
a:
.....
z

TABLE 5-2.

CI
U

TRANSMIT BAUD RATE OUTPUT FOR A GIVEN PRESCALER OUTPUT

~

u

iiE

SCRBITS

t

REPRESENTATIVE HIGHEST PRESCALER BAUD RATE OUTPUT

2

1

0

0

0

0

1

-

0

0

1

2

0

1

0

4

0

1

1

1

0

1
1
1

DIVIDE BY 250.000 kHz t

131.072 kHz

32.768 kHz

76.80 kHz

19.20 kHz

9600Hz

131.072 kHz

32.768 kHz

76.80 kHz

19.20 kHz

9600Hz

125.000 kHz

65.536 kHz

16.384 kHz

38.40 kHz

9600Hz

4800Hz

62.500 kHz

32.678 kHz

8.192 kHz

19.20 kHz

4800Hz

2400Hz

8

31.250 kHz

16.384 kHz

4.096 kHz

9600Hz

2400Hz

1200Hz

0

16

15.625 kHz

8.192 kHz

2.048 kHz

4800Hz

1200 Hz

600Hz

0

1

32

7.813 kHz

4.096 kHz

1.024 kHz

2400Hz

600Hz

300Hz

1

0

64

3.906 kHz

2.048 kHz

512 Hz

1200 Hz

300Hz

150Hz

1

1

128

1.953 kHz

1.024 kHz

256Hz

600Hz

150Hz

75Hz

CDP68HSC05C4. CDP68HSC05C8. CDP68HSC05C7 types.

NOTE:

Table 5-2 illustrates how the SCI select bits can be used to provide lower transmitter baud rates by further dividing the prescaler output frequency. The five
examples arB only representative samples. In all cases, the baud rates shown are transmit baud rates (transmit clock) and the receiver clock is 16 times
higher in frequency than the actual baud rate.

2-35

Serial Peripheral Interface (SPI)
INTRODUCTION AND FEATURES
Introduction
The serial peripheral interface (SPI) is an interface built into the
MCU which allows several MCUs, or one MCU plus peripheral
devices, to be interconnected within a single "black box" or on
the same printed circuit board. In a serial peripheral interface
(SPI), separate wires (signals) are required for data and clock.
In the SPI format, the clock is not included in the data stream
and must be furnished as a separate signal. An SPI system
may be configured as one containing one master MCU and
several slave MCUs, or in a system in which an MCU is
capable of being either a master or a slave.

• Master bit frequency
.. 1.05 MHz maximum (CDP68HC05C4, CDP68HC05C8,
and
CDP68HCL05C4,
CDP68HC05C7
CDP68HCL05C8, CDP68HCL05C7)
.. 2.0 MHz maximum (CDP68HSC05C4, CDP68HSC05C8,
CDP68HSC05C7)
• Slave bit frequency
.. 2.1 MHz maximum (CDP68HC05C4, CDP68HC05C8,
and
CDP68HCL05C4,
CDP68HC05C7,
CDP68HCL05C8, CDP68HCL05C7)

Rgure 6-1 illustrates a typical multicomputer system
configuration. Figure 6-1 represents a system of five different
MCUs in which there are one master and four slave (0, 1, 2, 3).
In this system four basic line (Signals) are required for the
MOSI (master out slave in), MISO (master in slave out), SCK
serial clock, and SS (slave select) lines.

.. 4.0 MHz maximum (CDP68HSC05C4, CDP68HSC05C8,
CDP68HSC05C7)
• Four programmable master bit rates
• Programmable clock polarity and phase

Features

• End of transmission interrupt flag

• Full duplex, three-wire synchronous transfers

• Write collision flag protection

• Master or slave operation

• Master-Master mode fault protection capability

C068HC05C4 SlAVE 0

MISO
MOSI
SCK
SS

C068HC05C8
MASTER

:=
p
0

I - - VOO

l
II

I

MISO SCK_
MOSI
SS

I

MOSI SS
MISO SCK

0
1
2
3

R
T

I

II

I

MOSl'SS
MISO SCK

CD68HC05C4 SLAVE 3

I I

r

MOSI
SS
MISO SCK

C068HC05C4 SLAVE 2

SINGLE MASTER, FOUR SLAVES
FIGURE 6-1.

MASTER-SLAVE SYSTEM CONFIGURATION

2-36

C068HC05C4 SlAVE 1

SIGNAL DESCRIPTION
The four basic signals (MOSI, MISO, SCK, SS) discussed
above are described in the following paragraphs. Each signal
function is described for both the master and slave mode.
Master Out Slave In (MOSI)

Configuration of the MOSI pin is a funtion of the MSTR bit in
the serial peripheral control register (SPCR, location $OA).
When a device is operating as a master,the MOSI pin is an
output because the program in firmware sets the MSTR bit to a
logic one.

The MOSI pin is configured as a data output in a master (mode)
device and as a data input in a slave (mode) device. In this
manner data is transferred serially from a master to a slave on
this line; most significant bit first, least significant bit last. The
timing diagrams of Figure 6-2 summarize the SPI timing
and show the relationship between data and clock (SCK). As
shown in Figure 6-2, four possible timing relationships may be
chosen by using control bits CPOL and CPHA. The master
device always allows data to be applied on the MOSI line a
half-cycle before the clock edge (SCK) in order for the slave
device to latch the data.
NOTE: Both the slave device(s) and a master device must be
programmed to similar timing modes for proper data transfer.
When the master device transmits data to a second (slave)
device via the MOSlline, the slave device responds by sending
data to the master device via the MISO line. This implies full
duplex transmission with both data out and data in
synchronized with the same clock signal (one which is
provided by the master device). Thus, the byte transmitted is
replaced by the byte received and eliminates the need for
separate transmit-empty and receiver-full status bits. A single
status bit (SPIF) is used to signify that the I/O operation is
complete.

SS

Master In Slave Out (MISO)
The MISO pin is configured as an input in a master (mode)
device and as an output in a slave (mode) device. In this
manner data is transferred serially from a slave to a master on
this line; most significant bit first, least significant bit last. The
MISO pin of a slave device is placed in the high-impedance
state if it is not selected by the master; i.e., its SS pin is a logic
one. The timing diagram of Figure 6-2 shows the relationship
between data and clock (SCK). As shown in Figure 6-2, four
possible timing relationships may be chosen by using control
bits CPOL and CPHA. The master device always allows data to
be applied on the MOSIline a half-cycle before the clock edge
(SCK) in order for the slave device to latch the data.
NOTE: The slave device(s) and a master device must be
programmed to similar timing modes for proper data transfer.
When the master device transmits data to a slave device via the
MOSI line, the slave device responds by sending data to the
master device via the MISO line. This implies full duplex
transmission with both data out and data in synchronized with
the same clock signal (one which is provided by the master
device). Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate transmit-empty
and receiver-full status bits. A single status bit (SPIF) in the
serial peripheral status register (SPSR,location $OB) is used to
signify that the I/O operation Is complete.

l

SS

SCK
(CPOL

=

0, CPHA

=

0)

(CPOL

=

0, CPHA

=

1)

(CPOL = 1, CPHA

=

0)

=

1)

SCK

SCK

SCK
(CPOL
MISOI
MOSI

=

1, CPHA

!I/ZII/lJJ

MSB

6

5

4

a

2

LSB

INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)

FIGURE 6-2.

DATA CLOCK TIMING DIAGRAM

2-37

v!lZ//IIIIII

In the master device, the MSTR control bit in the serial peripheral control register (SPCR, location $OA) is set to a logic one
(by the program) to allow the master device to receive data on
its MISO pin. In thE! slave device, its MISO pin Is enable by the
logic level of the SS pin; i.e., if SS = 1 then the MISO pin is
placed in the high-Impedance state, whereas, ifSS = 0 the
MISO pin is an output for the slave device.
Slave Select (SS)
The slave select (SS) pin is a fixed Input (PDS, pin 34), which
receives an active low signal that is generated by the master
device to enable slave devlce(s) to accept data. To ensure that
data will be accepted by a slave device, the SS signal line must
be a logic low prior to occurrence of SCK (system clock) and
must remain low until after the last (eighth) SCK cycle. Figure
6-2 illustrates the relationship between SCK and the data for
two different level combinations of CPHA, when SS Is pulled
1, the first bit of data Is
low. These are: 1) with CPHA
applied to the MISO line for transfer (SS must go high between
0 the slave
successive characters), and 2) when CPHA
device Is prevented from writing to its data register (SS can
remain low between characters). Refer to the WCOl status flag
in the serial peripheral status register (location SOB) description for fu rther information on the effects that the SS input and
CPHA control bit have on the I/O data register. A high level SS
signal forces the MISO (master in slave out) line to the highimpedance state. Also, SCK and the MOSI (master out slave in)
line are Ignored by a slave device when its SS signal is high.

=

=

When a device is a master, it constantly monitors its SS signal
input for a logic low. The master device will become a slave
device any time Its SS signal Input Is detected low. This
ensures that there is only one master controlling the SS line for
a particular system. When the SS line is detected low, it clears
the MSTR control bit (serial peripheral control register, location
$OA). Also, control bit SPE in the serial peripheral control
register is cleared which causes the serial peripheral interface

(SPI) to be disabled (port D SPI pins become Inputs). The
MODF flag bit in the serial peripheral status register (location
SOB) is also set to indicate to the master device that another
device Is attempting to become a master. Two devices attempting to be outputs are normally the result of a software error;
however, a system could be configured which would contain a
default master which would automatically "take-over .. and
restart the system.
Serial Clock (SCK)
The serial clock Is used to synchronize the movement of data
both in and out of the device through Its MOSI and MISO pins.
The master and slave devices are capable of exchanging a
data byte of Information during a sequence of eight clock
pulses. Since the SCK is generated by the master device, the
SCK line becomes an input on all slave devices and synchronizes slave data transfer. The type of clock and It relationship
to data are controlled by the CPOl and CPHA bits In the serial
peripheral control register (location $OA) discussed below.
Refer to Figure 6-2 for timing.
The master device generates the SCK through a circuit-driven
by the internal processor clock. Two bits (SPRO and SPR1) in
the serial peripheral control register (location $OA) of the
master device select the clock rate. The master device uses the
SCK to latch incoming slave device data on the MISO line and
shifts out data to the slave device on the MOSI line. Both
master and slave devices must be operated in the same timing
mode as controlled by the CPOl and CPHA bit in the serial
peripheral control register. In the slave device, SPRO, SPR1
have no effect on the operation of the serial peripheral
interface. Timing Is shown in Figure 6-2.
FUNCTIONAL DESCRIPTION

A block diagram of the serial peripheral interface (SPI) is
shown in Figure 6-3. In a master configuration, the master start
SEE NOTE

INTERNAL
PROCESSOR

33

CLOCK

READ
INTERNAL

t.!~:.;=~..!!;~~.t:?~t-I-"

NOTES:

SPCR

CONTROL

lOA

BITS

BUS
DATA

The SS, SCI<, MOSI and MISO are external pins which provide the following functions:
Provides serial output to slave unR(s) when device is configured as a master. Receives serial input from master unR when device is
a. MOSI
configured as a slave unR.
Receives serial input from slave unR(s) when device is configured as a master. Provides serial output to master when device is
b. MISO
configured as a slave unit.
Provides system clock when device is configured as a master unll Receives system clock when device Is configured as a slave unft.
c. SCK
Provides a logic low to select device for a transfer wHh a master device.
d. Sa

-

FIGURE 8-~

SERIAL PRIPHERAL INTERFACE BLOCK DIAGRAM

2-38

logic receives an input from the CPU (in the form of a write to
the SPI rate generator) and originates the system clock (SCK)
based on the internal processor clock. This clock is also used
internally to control the state controller as well as the 8-bit shift
register. As a master device, data is parallel loaded into the
8-bit shift register (from the internal bus) during a write cycle,
data is applied serially from a slave device via the MISO pin to
the 8-bit shift register. After the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer and then is made
available to the internal data bus during a CPU read cycle.
In a slave configuration, the slave .:!!art logic receives a logic
low (from a master device) at the SS pin and a system clock
input (from the same master device) at the SCK pin. Thus, the
slave is synchronized with the master. Data from the master is
received serially at the slave MOSI pin and loads the 8-bit shift
register. After the 8-bit shift register is loaded, its data is
parallel transferred to the read buffer and then is made
available to the internal data bus during a CPU read cycle.
During a write cycle, data is parallel loaded into the 8-bit shift
register from the internal data bus and then shifted out serially
to the MISO pin for application to the master device.
Figure 6-4 illustrates the MOSI, MISO, and SCK master-slave
interconnections. Note that in Figure 6-4 the master SS pin is
tied to a logic high and the slave SS pin is a logic low. Figure
6-1 provides a larger system connection for these same pins.
Note that in Figure 6-1, all SS pins are connected to a port pin
of a master/slave device. In this case any of the devices can be
a slave.

FIGURE 6-4.

The serial peripheral control register bits are defined as
follows:
B7,SPIE

When the serial peripheral interrupt enable is
high, it allows the occurrence of a processor
interrupt, and forces the proper vector to be
loaded into the program counter if the serial
peripheral status register flag bit (SPIF and/or
MODE) is set to a logic one. It does not inhibit
the setting of a status bit. The SPIE bit is cleared
by reset.

B6,SPE

When the serial peripheral output enable
control bit is set, all output d rive is applied to the
external pins and the system is enabled. When
the SPE bit is set, it enables the SPI system by
connecting it to the external pins thus allowing
it to interface with the external SPI bus. The pins
that are defined as output depend on which
mode (master or slave) the device is in. Because
the SPE bit is cleared by reset, the SPI system
is not connected to the external pins upon reset.

B4, MSTR

The master bit determines whether the device is
a master or a slave. If the MSTR bit is a logic
zero it indictes a slave device and a logic one
denotes a master device. If the master mode is
selected, the function of the SCK pin changes
from an input to an output and the function of
the MISO and MOSI pins are reversed. This
allows the user to wire device pins MISO to
MISO, and MOSI to MOSI, and SCK to SCK
without incident. The MSTR bit is cleared by
reset; therefore, the device is always placed in
the slave mode during reset.

B3,CPOL

The clock polarity bit controls the normal or
steady state value of the clock when data is not
being transferred. The CPOL bit affects both
the master and slave modes. It must be used in
conjunction with the clock phase control bit
(CPHA) to produce the wanted clock-data
relationship between a master and a slave
device. When the CPOL bit is a logic zero, it
produces a steady state low value at the SCK
pin of the master device. If the CPOL bit is a
logic one, a high value is produced at the SCK
pin of the master device when data is not being
transferred. The CPOL bit is not affected by
reset. Refer to Figure 6-2.

B2,CPHA

The clock phase bit controls the relationship
between the data on the MISO and MOSI pins
and the clock produced or received at the SCK
pin. This control has effect in both the master
and slave modes. It must be used in conjunction
with the clock polarity control bit (CPOL) to
produce the wanted clock-data relation. The
CPHA bit in general selects the clock edge
which captures data and allows it to change
states. It has its greatest impact on the first bit
transmitted (MSB) in that it does or does not
allow a clock transition belore the first data
capture edge. The CPHA bit is not affected by
reset. Reterto Figure 6-2.

SERIAL PERIPHERAL INTERFACE
MASTER-SLAVE INTERCONNECTION

REGISTERS
There are three register in the serial parallel interface which
provide control, status, and data storage functions. These
registers which include the serial peripheral control register
(SPCR, location $OA), serial peripheral status register (SPSR,
location $OB), and serial peripheral data I/O register (SPDR
location $OC) are described below.
'
Serial Peripheral Control Register (SpeRl

765

4

3

2

1

0

I I I
SPIE

SPE

2-39

'"
a:

~

~
~
~
~
c.:>

L-_:E__

B1,SPR1
BO,SPRO

These two serial peripheral rate bits select one
of four baud rates to used as SCK if the device
is a master; however they have no effect in the
slave mode. The slave device is capable of
shifting data In and out at a maximum rate
which Is equal to the CPU clock. A rate table is
given below for the generation of the SCK from
the master. The SPR1 and SPRO bits are not
affected by reset.

before the second SPIF In order to prevent an
overrun condition. The SPIF bit Is cleared by
reset.
Be,WCOl

INTERNAL PROCESSOR
CLOCK DIVIDE BY

SPR1

SPRO

0

0

2

0

1

4

1

0

16

1

1

32

Serial Peripheral Status Register (SPSR)
7

6

5

4

3

2

o
SOB

The status flags which generate a serial peripheral interface
(SPI) interrupt may be blocked by the SPIE control bit in the
serial peripheral control register. The WCOl bit does not cause
an interrupt. The serial peripheral status register bits are
defined as follows:
B7,SPIF

The serial peripheral data transfer flag bit
notifies the user that a data transfer between
the device and an external device has been
completed. With the completion of the data
transfer, SPIF is set, and if SPIE is set, a serial
peripheral interrupt (SPI) Is generated. During
the clock cycle that SPIF is being set, a copy of
the received data byte in the shift register is
moved to a buffer. When the data register Is
read, it is the buffer that is read. During an
overrun condition, when the master device has
sent several bytes of data and the slave device
has not responded to the first SPIF, only the first
byte sent is contained in the receiver buffer and
all other bytes are lost.
The transfer of data is initiated by the master
device writing its serial peripheral data register.
Clearing the SPIF bit is accomplished by a
software sequence of accessing the serial
peripheral status register while SPIF is set and
followed by a write to or a read of the serial
peripheral data register. While SPIF is set, all
writes to the serial peripheral data register are
inhibited until the serial peripheral status
register Is read. This occurs in the master
device. In the slave device, SPIF can be cleared
(using a similar sequence) during a second
transmission; however, It must be cleared

2-40

The function of the write collision status bit is to
notify the user that an attempt was made to
write the serial peripheral data register while a
data transfer was taking place with an external
device. The transfer continues uninterrupted;
therefore, a write will be unsuccessful. A "read
collision" will never occur since the received
data byte is placed in a buffer In which access
is always synchronous with the MCU operation.
If a ''write collision" occurs, WCOl Is set but no
SPI interrupt is generated. The WCOl bit is a
status flag only.
Clearing the WCOl bit is accomplished by a
software sequence of accessing the serial
peripheral status register while WCOl is set,
followed by 1) a read of the serial peripheral
data register prior to the SPIF bit being set, or
2) a read or write of the serial peripheral data
register after the SPIF bit is set. A write to the
serial peripheral data register (SPDR) prior to
the SPIF bit being set, will result In generation of
another WCOl status flag. Both the SPIF and
WCOl bits will be cleared in the same
sequence. If a second transfer has started while
trying to clear (the previously set) SPIF and
WCOl bits with a clearing sequence containing
a write to the serial peripheral data register,
only the SPIF bit will be cleared.
A collision of a write to the serial peripheral
data register while an external data transfer is
taking place can occur in both the master mode
and the slave mode, although with proper
programming the master device should have
sufficient information to preclude this collision.
Collision in the master device is defined as a
write of the serial peripheral data register while
the internal rate clock (SCK) is in the process of
transfer. The signal on the SS pin is always high
on the master device.
A collision in a slave device is defined in two
separate modes. One problem arises in a slave
device when the CPHA control bit is a logic
zero. When CPHA is a logiC zero, data is
latched with the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs
when it attempts to write the serial peripheral
data register after its SS pin has been pulled
low. The SS pin of the slave device freezes the
data in its serial peripheral data register and
does not allow it to be altered if the CPHA bit is
a logic zero. The master device must raise the
SS pin of the slave device high between each
byte it transfers to the slave device.

Clearing the MODF Is accomplished by a
software sequence of accessing the serial
peripheral status register while MODF is set
followed by a write to the serial peripheral
control register. Control bit SPE and MSTR may
be restored to their original set state during this
cleared sequence or after the MODF bit has
been cleared. Hardware does not allow the user
to set the SPE and MSTR bit whlle MODF is a
logic one unless it is during the proper clearing
sequence. The MODF flag bit indicates that
there might have been a multi-master conflict
for system control and allows a proper exit from
system operation to a reset or default system
state. The MODF bit is cleared by reset.

The second collision mode Is defined for the
state of the CPHA control bit being a logic one.
With the CPHA bit set, the slave device will be
receiving a clock (SCK) edge prior to the latch
of the first data transfer. This first clock edge
will freeze the data In the slave device I/O
register and allow the msb onto the external
MISO pin of the slave device. The SS pin low
state enables the slave device but the drive onto
the MISO pin does not take place until the first
data transfer clock edge. The WCOl bit will
only be set if the I/O register is accessed while
a transfer is taking place. By definition of the
second collision mode, a master device might
hold a slave device SS pin low during a transfer
of serveral bytes of data without a problem.
A special case of WCOl occurs in the slave
d~vice. This happens when the master device
starts a transfer sequence (an edge on SCK for
CPHA = 1; or an active SS transition for
CPHA = 0) at the same time the slave device
CPU is writing to its serial peripheral interface
data register. In this case it Is assumed that the
data byte written (in the slave device serial
peripheral interface) is lost and the contents of
the slave device read buffer becomes the byte
that is transferred. Because the master device
receives back the last byte transmitted, the
master device can detect that a fatal WCOl
occurred.
Since the slave device is operating asynchronously with the master device, the WCOl bit
may be used as an Indicator of a collision
occurrence. This helps alleviate the user from a
strict real-time programming effort. The WCOl
bit is cleared by reset.
B4,MODF

The function of the mode fault flag is defined for
the master mode (device). If the device is a slave
device the MODF bit will be prevented from
toggling from a logic zero to a logic one;
however, this does not prevent the device from
being in the slave mode with the MODF bit set.
The MODF bit is normally a logic zero and is set
only when the master device has its SS pin
pulled low. Toggling the MODF bit to a logic
one affects the internal serial peripheral interface (SPI) system in the following ways:
1. MODF is set and SPI interrupt is generated
ifSPIE= 1.
2. The SPE bit Is forced to a logic zero. This
blocks all output drive from the device,
disables the SPI system.
3. The MSTR bit is forced to a logic zero, thus
forcing the device into the slave mode.

Serial Peripheral Data I/O Register (SPDR)
7

6

5

4

3

2

o
SOC

Serial Peripheral Data I/O Register

The serial peripheral data I/O register is used to transmit and
receive data on the serial bus. Only a write to this register will
initiate transmission/reception of another byte and this will only
occur in the master device. A slave device writing to its data I/O
register will not initiate a transmission. At the completion of
transmitting a byte of data, the SPIF status bit Is set in both the
master and slave devices. A write or read of the serial
peripheral data I/O register, after accessing the serial
peripheral status register with SPIF set, will clear SPIF.
During the clock cycle that the SPIF bit is being set, a copy of
the received data byte in the shift register is being moved to a
buffer. When the user reads the serial peripheral data I/O
register, the buffer is actually being read. During an overrun
condition, when the master devi.ce has sent several bytes of
data and the slave device has not internally responded to clear
the first SPIF, only the first byte is contained in the receive
buffer of the slave device; all others are lost. The user may read
the buffer at any time. The first SPIF must be cleared by the
time a second transfer of data from the shift register to the read
buffer is initiated or an overrun condition will exist.
A write to the serial peripheral data I/O register is not buffered
and places data directly Into the shift register for transmission.
The ability to access the serial peripheral data I/O register is
limited when a transmission is taking place. It Is important to
read the discussion defining the WCOl and SPIF status bit to
understand the limits on using the serial peripheral data I/O
register.
SERIAL PERIPHERAL
CONSIDERATIONS

INTERFACE

(SPI)

SYSTEM

There are two types of SPI systems; single master system and
mUlti-master systems. Figure 6-1 illustrates a single master
system and a discussion of both is provided below.

2-41

Rgure 6-1 illustrates how a typical single master system may
be configured, using a CDP68HC05 family device as the
master and four CDP68HC05 family devices as slaves. As
shown, the MOSI, MISO, and SCK pins are all wired to
equivalent pins on each of the five devices. The master device
generates the SCK clock, the slave device all receive It Since
the CDP68HC05 master device Is the bus master, it internally
controls the function of its MOSI and MISO lines, thus writing
data to the slave devices on the MOSI and reading data from
the slave devices on the MISO lines. The master device selects
the Individual slave devices by using four pins of a parallel port
to control the four SS pins of the slave devices. A slave device
is selected when the master device pulls its SS pin low. The SS
pins are pulled high during reset since the master device ports
will be forced to be inputs at that time, thus disabling the slave
devices. Note that the slave devices do not have to be enabled
In a mutually exclusive fashion except to prevent bus contention on the MISO line. For example, three slave devices,
enabled for a transfer, are permissible If only one has the
capability of being read by the master. An example of this Is a

write to several display drivers to clear a display with a single
operation. To ensure that proper data transmission Is
occurring between the master device and a slave device, the
master device may have the slave device respond with a
previously received data byte (this data byte could be Inverted
or at least be a byte that is different from the last one sent by
the master device). The master device will always receive the
previous byte back from the slave device If all MISO and MOSI
lines are connected and the slave has not written its data
register. Other transmission security methods might be
defined using ports for handshake lines or data bytes with
command fields.

va

va

A multi-master system may also be configured by the user. An
exchange of master control could be Implemented using a
handshake method through the I/O ports or by an exchange of
code messages through the serial peripheral Interface system.
The major device control that plays a part In this system Is the
MSTR bit in the serial peripheral control register and the
MODF bit in the serial peripheral status register.

2-42

Effects of Stop and Wait Modes on the Timer and Serial Systems
INTRODUCTION
The STOP and WAIT instructions have different effects on the
programmable timer, serial communications interface (SCI),
and serial peripheral interface (SPI) systems. These different
effects are discussed separately below.

(baud rate generator stops) and the rest of the data is lost. For
the above reasons, all SCI transactions should be in the idle
state when the STOP instruction is executed.
SPI During Stop Mode

STOP MODE
When the processor executes the STOP instruction, the
internal oscillator is turned off. This halts all internal CPU
processing including the operation of the programmable timer,
serial communications interface, and serial peripheral
interface. The only way for the MCU to " wake up" from the
stop mode is by receipt of an external interrupt (logic low on
IRQ pin) or by the detection of a reset (logic low on RESET pin
or a power-on reset). The effects of the stop mode on each of
the MCU systems (Timer, SCI, and SPI) are described
separately.
Timer During Stop Mode
When the MCU enters the stop mode, the timer counter stops
counting (the internal processor is stopped) and remains at
that particular count value until the stop mode is exited by an
interrupt (if exited by reset the counter is forced to $FFFC). If
the stop mode is exited by an external low on the IRQ pin, then
the counter resumes from its stopped value as if nothing had
happened. Another feature of the programmable timer, in the
stop mode, is that if at least one valid input capture edge
occurs at the TCAP pin, the input capture detect circuitry is
armed. This action does not set any timer flags or "wake up"
the MCU, but when the MCU does "wake up" there will be an
active input capture flag (and data) from that first valid edge
which occurred during the stop mode. If the stop mode is
exited by an external reset (logic low on RESET pin), then no
such input capture flag or data action takes place even if there
was a valid input capture edge (at the TCAP pin) during the
MCU stop mode.
SCI During Stop Mode
When the MCU enters the stop mode, the baud rate generator
which drives the receiver and transmitter is shut down. This
essentially stops all SCI activity. The receiver is unable to
receive and transmitter is unable to transmit. If the STOP
instruction is executed during a transmitter transfer, that
transfer is halted. When the stop mode is exited, that particular
transmission resumes (if the exit is the result of a low input to
the IRQ pin). Since the previous transmission resumes after an
IRQ interrupt stop mode exit, the user should ensure that the
SCI transmitter is in the idle state when the STOP instruction is
executed. If the receiver is receiving data when the STOP
instruction is executed, r-eceived data sampling is stopped

When the MCU enters the stop mode, the baud rate generator
which drives the SPI shuts down. This essentially stops all
master mode SPI operation, thus the master SPI is unable to
transmit or receive any data. If the STOP instruction is
executed during an SPI transfer, that transfer is halted until the
MCU exits the stop mode (provided it is an exit resulting from a
logic low on the IRQ pin). If the stop mode is exited by a reset,
then the appropriate control/status bits are cleared and the SPI
is disabled. If the device is in the slave mode when the STOP
instruction is executed, the slave SPI will still operate. It can still
accept data and clock information in addition to transmitting its
own data back to a master device.
At the end of a possible transmission with a slave SPI in the
stop mode, no flags are set until a logic low IRQ input results in
an MCU "wake up". Caution should be observed when
operating the SPI (as a slave) during the stop mode because
none of the protection circuitry (write collision, mode fault, etc.)
is active.
It should also be noted that when the MCU enters the stop
mode all enabled output drivers (TOO, TCMP, MISO, MOSI,
and SCK ports) remain active and any sourcing currents from
these outputs will be part of the total suply current required by
the device.
WAIT MODE
When the MCU enters the wait mode, the CPU clock is halted.
All CPU action is suspended; however, the timer, SCI, and SPI
systems remain active. In fact an interrupt from the timer, SCI,
or SPI (in addition to a logic low on the IRQ or RESEr pins)
causes the processor to exit the wait mode. Since the three
systems mentioned above operate as they do in the normal
mode, only a general discussion of the wait mode is provided
below.
The wait mode power consumption depends on how many
systems are active. The power consumption will be highest
when all the systems (timer, TCMP, SCI, and SPI) are active.
The power consumption will be the least when the SCI and SPI
systems are disabled ( timer operation cannot be disabled in
the wait mode). If a non-reset exit from the wait mode is
performed (i.e., timer overflow interrupt exit), the state of the
remaining systems will be unchanged. If a reset exit'from the
wait mode is performed all the systems revert to the disabled
reset state.

2-43

en

a:

w
.....
.....

o

a:
Iz:
o

<-:>

o

a:

<-:>

:E

Instruction Set and Addressing Modes
INSTRUCTION SET

Register/Memory Instructions

The MCU has a set of 62 basic Instructions. They can be
divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type. All the
instructions within a given type are presented In Individual
tables.

Most of these Instructions use two operands. The first operand
Is either the accumulator or the Index register. The second
operand is obtained from memory using one of the addressing
modes. The operand for the jump unconditional (JMP) and
jump to subroutine (JSR) instr~ctlons Is the program counter.
Refer to Table 8-1.

All of the instructions used In the CDP6805 CMOS Family are
available in the CDP68HC05C4 family of MCU's, plus an
additional one; the multiply (MUL) Instruction. This instruction
allows for unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high order
product is then stored In the index register and the low order
product is stored in the accumulator. A detailed definition of
the MUL Instruction Is shown below.

Read-Modlfy-Wrlte Instructions
These Instructions read a memory location or a register, modify
or test its contents, and write the modified value back to
memory or to the register. The test for negative or zero (TST)
instruction is an exception to the read-modify-wrlte sequence
since it does not modify the value. Refer to Table 8-2.

Operation:

X:A .... X*A

Description:

Multiplies the eight bits in the index register by the eight bits In the accumulator to obtain a
16-bit unsigned number in the concatenated accumulator index register.

Condition Codes:

H:
I:
N:

Z:
C:

Cleared
Not affected
Not affected
Not affected
Cleared

Source Form(s):

MUL
Addressing Mode
Inherent

I
I

Cycles
11

2-44

J
I

Bytes
1

1
1

Opcode
$42

TABLE 8-1.

REGISTER/MEMORY INSTRUCTIONS
ADDRESSING MODES

IMMEDIATE

EXTENDED

DIRECT

I

INDEXED
(NO OFFSET)

INDEXED
(8-BIT OFFSET)

INDEXED
(16-BIT OFFSET)

NO.
BYTES

NO.
CYCLES

OP
CODE

NO.
BYTES

NO.
CYCLES

OP
CODE

NO.
BYTES

NO.
CYCLES

OP
CODE

NO.
BYTES

NO.
CYCLES

OP
CODE

NO.
BYTES

NO.
CYCLES

OP
CODE

NO.
BYTES

NO.
CYCLES,

2

4

06

3

5

FUNCTION

MNEM.

OP
CODe

Load A from Memory

LDA

A6

2

2

B6

2

3

C6

3

4

F6

1

3

E6

Load X from Memory

LOX

AE

2

2

BE

2

3

CE

3

4

FE

1

3

EE

2

4

DE

3

5

Siore A in Memory

STA

-

-

-

B7

2

4

C7

3

5

F7

1

4

E7

2

5

D7

3

6

Store X in Memory

STX

-

-

-

BF

4

CF

3

5

FF

1

4

EF

2

5

OF

3

6

Add Memory 10 A

ADD

AB

2

2

BB

2

3

CB

3

4

FB

1

3

EB

2

4

DB

3

5

Add Memory and
Carry 10 A

ADC

A9

2

2

B9

2

3

C9

3

4

F9

1

3

E9

2

4

09

3

5

Subtract Memory

SUB

AO

2

2

BO

2

3

CO

3

4

FO

1

3

EO

2

4

DO

3

5

Subtract Memory
From A with Borrow

SBC

A2

2

2

B2

2

3

C2

3

4

F2

1

3

E2

2

4

02

3

5

AND Memory 10 A

AND

A4

2

2

B4

2

3

C4

3

4

F4

1

3

E4

2

4

D4

3

5

OR Memory with A

ORA

AA

2

2

BA

2

3

CA

3

4

FA

1

3

EA

2

4

OA

3

5

3

E8

2

4

D8

3

5

,
!

,

I\)

k

2

Exclusive OR
MemorywHhA

EOR

AS

2

2

B8

2

3

C8

3

4

F8

1

Arahmelic Compare
A with Memory

CM!>

AI

2

2

Bl

2

3

Cl

3

4

Fl

1

3

El

2

4

01

3

5

Arithmetic Compare
X with Memory

CPX

AS

2

2

B3

2

3

C3

3

4

F3

1

3

E3

2

4

03

3

5

Bit Test Memory

BIT

A5

2

2

B5

2

3

C5

3

4

F5

1

3

E5

2

4

05

3

5

Jump Unconditional

JMP

-

-

-

BC

2

2

CC

3

3

FC

1

2

EC

2

3

DC

3

4

Jump to Subroutine

JSR

-

-

-

BO

2

2

CD

3

3

FD

1

5

ED

2

6

OD

3

7

wHh A (logical
Compare)

~------.----

'----

------

~

-

-

-

-~

MICROCONTROLLERS

TABLE 8-2.

READ-MODIFY-WRITE INSTRUCTIONS
ADDRESSING MODES

INHERENT (A)

k

DIRECT

INDEXED
(NO OFFSET)

INDEXED
8-BIT OFFSET)

MNEMONIC

OP
CODE

NO.
BYTES

NO.
CYCLES

OP
CODE

NO.
BYTES

NO.
CYCLES

OP
CODE

NO.
BYTES

NO.
CYCLES

OP
CODE

NO.
BYTES

NO.
CYCLES

OP
CODE

NO.
BYTES

NO.
CYCLES

Increment

INC

4C

1

3

5C

1

3

3C

2

5

7C

1

5

6C

2

6

FUNCTION

I\)

INHERENT (X)

Decrement

DEC

4A

1

3

5A

1

3

3A

2

5

7A

1

5

6A

2

6

Cleer

CLR

4F

1

3

5F

1

3

3F

2

5

7F

1

5

6F

2

6

Complement

COM

43

1

3

53

1

3

33

2

5

73

1

5

63

2

6

Negate (2's Complement)

NEG

40

1

3

50

1

3

30

2

5

70

1

5

60

2

6

Rotate Left Thru Carry

ROL

49

1

3

59

1

3

39

2

5

79

1

5

69

2

6

Rolate Right Thru Carry

ROR

46

1

3

56

1

3

36

2

5

76

1

5

66

2

6

Logical Shift Left

LSL

46

1

3

58

1

3

38

2

5

78

1

5

68

2

6

Logical Shift Right

LSR

44

1

3

54

1

3

34

2

5

74

1

5

64

2

6

Ar~hmetic Shift

ASR

47

1

3

57

1

3

37

2

5

77

1

5

67

2

6

Test for Negative or Zero

TST

40

1

3

50

1

3

3D

2

4

70

1

4

60

2

5

Multiply

MUL

42

1

11

-

-

-

-

-

-

-

-

-

-

-

-

Right

Branch Instructions
Most branch instructions test the state of the condition code
register and if certain criteria are met, a branch Is executed.
This adds an offset between -127 and +128 to the current
program counter. Refer to Table 8-3.
TABLE 8-3.

port registers, port DDRs, timer, two serial systems, on-chip
RAM, and 48 bytes of ROM reside In the first 256 bytes (page
zero). An additional feature allows the software to test and
branch on the state of any bit within the first 256 locations. The
bit set, bit clear, and bit test and branch functions are all
implemented with a single instruction. For the test and branch
instructions, the value of the bit tested is automatically placed
in the carry bit of the condition code register. Refer to Table
8-4.

BRANCH INSTRUCTIONS
RELATIVE ADDRESSING
MODE

FUNCTION

MNEM.

OP
NO.
CODE BYTES

NO.
CYCLES

Branch Always

BRA

20

2

3

Branch Never

BRN

21

2

3

Branch IFF Higher

BHI

22

2

3

Branch IFF Lower or Same

BLS

23

2

3

Branch IFF Carry Clear

BCC

24

2

3

(BHS)

24

2

3

(Branch IFF Higher or Same)
Branch IFF Carry Set
(Branch IFF Lower)
Branch IFF Not Equal
Branch IFF Equal
Branch IFF Half Carry Clear
Branch IFF Half Carry Set
Branch IFF Plus

BC~

25

2

25

2

3

BNE

26

2

3

BEQ

27

2

3

BHCC

28

2

3

BHCS

29

2

3

BPL

2A

2

3

Branch IFF Minus

BMI

2B

2

3

Branch IFF Interrupt Mask
Bit is Clear

BMC

2C

2

3

Branch IFF Interrupt Mask
Bit Is Set

BMS

2

TABLE 8-S.

FUNCTION

3

Branch IFF Interrupt Line
is Low

BIL

2E

2

3

Branch IFF Interrupt Line
is High

BIH

2F

2

3

Branch to Subroutine

BSR

AD

2

6

CONTROL INSTRUCTIONS
INHERENT

3

(BLO)

20

Control Instructions
These instructions are register reference instructions and are
used to control processor operation during program execution.
Refer to Table 8-5.

NO.
CYCLES

Transfer A to X

TAX

97

1

2

Transfer X to A

TXA

9F

1

2

Set Carry Bit

SEC

99

1

2

Clear Carry Bit

CLC

98

1

2

Set Interrupt Mask Bit

SEI

9B

1

2

Clear Interrupt Maak Bit

CU

9A

1

2

Software Interrupt

SWI

83

1

10

Return from Subroutine

RTS

81

1

6

Retum from Interrupt

Rll

80

1

9

Reset Stack Pointer

RSP

9C

1

2

No-Operation

NOP

90

1

2

Stop

STOP

SE

1

2

Wait

WAIT

SF

1

2

Alphabetical Listing
The complete instruction set is given In alphabetical order in
Table 8-6.

Bit Manipulation Instructions
The MCU is capable of setting or clearing any bit which resides
In the first 256 bytes of the memory space except for ROM,
port D data location ($03), serial peripheral status register
($OB), serial communications status register (10), timer status
register ($13), and timer input capture register ($14 - $15). All

TABLE 8-4.

Opcode Map
Table 8-7 is an opcode map for the instructions used on the
MCU.

BIT MANIPULATION INSTRUCTIONS
ADDRESSING MODES
BIT TEST AND BRANCH

BIT SET/CLEAR
FUNCTION

MNEMONIC

NO.
BYTES

NO.
CYCLES

2-n

3

5

01 + 2· n

3

5

-

-

OP
CODE

NO.
BYTES

NO.
CYCLES

OP
CODE

-

-

-

-

Branch IFF Bit n is Set

BRSETn(n=0 ... 7)

Branch IFF Bit n is Clear

BRCLRn(n =0 ... 7)

Set Bitn

BSETn (n =0 ...7)

10 + 2. n

2

5

Clear Bit n

BCLRn(n=0 ...7)

11 +2-"

2

5

2-47

-

•
CI)

OP
NO.
MNEM. CODE BYTES

a:

....
....
LLI

0

a:
.....
z:

0
c.:I
0

a:
c.:I
[i

'---

TABLE 8-8.

INSTRUCTION SET
CONDITION
CODES

ADDRESSING MODES

INDEXED
BIT
BIT
(NO
INDEXED INDEXED SETI TEST &
MNEM. INHERENT IMMEDIATE DIRECT EXTENDED RELATIVE OFFSET) (BBITS) (18 BITS) CLEAR BRANCH H

ADC

X

X

X

X

X

X

ADD

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

AND

X

ASl

X

X

ASR

X

X

BCC

X

BEQ

X

BHCC

X

BHCS

X

BHI

X

BHS

X

BIH

X

Bil

X

BIT

X

X

X

X

BlO

X

BlS

X

BMC

X

BMI

X

BMS

X

BNE

X

BPl

X

BRA

X

BRN

X

X

X

• A

BRClR

X

BRSET

X

BSET

X

BSR

X

ClC

X

CLI

X

ClR

X

·
·
·• • • •
·
•
· ···
·• · •• •• ••
·
··• • ·
·• ·• ·• ·• ·•
·• • ··
·• ·• · · ·•
··
· ··
·· ·
· · · ·• ·
··· ·
· ·• · ·• ·
·• • · ·
···
· •• · · •
· ···
·• ·• • · ·
·
· · • ·•
· · ·• ·•
·· ·
·• • •• ·• •
• ·
·
• ·
• A A A

BClR
X

N Z C

A • A AA
A • A AA
• A • A
• A A A

X

BCS

I

A •

• A
A

0

0

X

CMP

X

X

X

X

X

X

X

0 1

X

Condition Code Symbols:
H

Half Carry (from BH 3)

I

Interrupt Mask

N

=

A

=

Test and Set ij True Cleared Otherwise
Not Affected
Load CC Register From Stack

Negate (Sign Bit)

Z

Zero

o

= Cleared

C

Carry/Borrow

1

Set

2-48

AA A

TABLE 8-6.

INSTRUCTION SET (Continued)
CONDITION
CODES

ADDRESSING MODES

INDEXED
BIT
BIT
(NO
INDEXED INDEXED SETI TESTA
MNEM. INHERENT IMMEDIATE DIRECT EXTENDED RELATIVE OFFSET) (8 BITS) (16 BITS) CLEAR BRANCH H
COM

X

X

CPX
DEC

X
X

X

X

EaR
INC

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

JSR

X

X

X

X

X

X

X

X

X

X

X

X

X

X

LOX

X

X

LSL

X

X

X

X

LSR

X

X

X

X

MUL

X

NEG
Nap

X

N Z C

• A A 1
• A AA
• A A •
• A A •

·
·•
·• ·• · • ·•
··
·•
·
·
· ·• • •
• A

JMP

LOA

•
•

I

X

• A A •
A A •
• A AA
0

0

X

X

X

A •

AA
0

• • A AA
• • • • •

X

X

ROL

X

X

X

X

·•

ROR

X

X

X

X

•

• A A •
• A AA
• A AA

RSP

X

RTI

X

?

?

RTS

X

X

ORA

sec

X

SEC

X

SEI

X

X

X

X

X

X

X

X

X

X

X

X

X

X

STX

sue

X
X
X

TST

X

TXA

X

WAIT

X

? ?

• A AA

• A

A •

0

X

SWI

?

1

X

TAX

·• • • ·
···• •
· •
·• · ·
···
· •
· · ·
·
· ••
·• • • • ·•
·• •
· ··
• • ·•
1

STA
STOP

X

X

X

X

X

X

X

X

X

X

X

• A A •
• A AA

1

X

X

X

• A

0

Condnion Code Symbols:
H

Half Carry (from Bn 3)

I

Interrupt Mask

N

=

A

Not Affected

= Load CC Register From Stack

Negate (Sign Bit)

Z

Zero

C

Carry/Borrow

Test and Sell True Cleared Otherwise

o

= Cleared
Set

2-49

A •

.............a:

en
CI

a:
~

z

CI

u

CI

a:

u

&

'---

TABLE 8-7. HCMOS INSTRUCTION SET OPCODE MAP
BIT
MANIPULATION BRANCH
REL
DIR
BTB
BSC
3
2
0
1
HI
0010
0011
0000
0001

LOW

5

0
0000

BRSETO BSETO
3

BTB 2

BSC

5

1
0001

0010

0011

'}'
UI

o

BRCLR1 BCLR1
3 BTB 2 esc
5

4
0100

5
0101

6

BRSET3 BSET3

5
0110

3

BTB

0111

2

BLS
2

NEG

INH 2

RTI

IX 1

1

1

3

INH

2

5
CIR

3

3

1

1

INH
3

1

INH

INH

2

IXl

INH

1

INH

3

3

BNE

2

5

2

3

ROR

REL 2

RORA

CIR

1

5

3

3

ASRA

ASR

REL 2

CIR

3

1

,-

INH

INH

ROR
2

3

ASRX
1

INH

ASR
2

ROR

IXl

1

IXl

IX

1

INH

2

STA

EXT 3

---

-

INH

Inherent

-

Accumulator

X

-

Index Register

IMM

s

Immediale

CIR

= Cirect

EXT

-

Extended

REL

Relative

IX2 2

IXl

BSC

= Bft SetlClear

BTB

BftTestand Branch

LEGEND
OPCOOEIN
1111 +:-+----S~,.. HEXADECIMAL

MNEMONIC~ l '
BYTES--t:

CYCLES----

Lt-I

;- \

f

OPCOOE IN
BINARY

ACCRESS

MODE

0101

3

6

IX

5

-------- ------

'-....;==::a:=::;?>~-7
:;;

1

0110

4

STA

Abbreviations for Address Modes:
A

5
IX

LOA

IXl

2

6

STA

CIR 3

LOA

IX2

5

STA

1

4

LOA

EXT 3

3

4

TAX

ASR
1

CIR

5

LOA

LOA
2

2

5

6

IMM

4

3

LOA
2

IX

BIT

IXl

0100

3

BIT

IX2 2

4

IX

1

4

BIT

EXT 3

3

AND

IXl

5

4

3
0011

3

4

2

0010

3

IX

1

AND

IX2

BIT

CIR

2

IXl

5

AND

EXT 3

3

2

5

6

RORX

INHY 1

3

BIT

IMM

IX2 2

4

AND

CIR

2

BIT

REL

BEQ

3
2

CPX

CPX

2

IX

1

4

CPX

EXT 3

SBC

IXl

5

4

CPX

AND

IMM

2

0001

3

SBC

IX2

1

IX

1

4

SBC

EXT 3

CIR 3

2

BCS
2

2

AND
2

IX

1

3

CPX

IMM

2

LSR

IXl

CIR
3

CPX

5

LSR
2

SWI

IX

1

6

LSRX
1

COM

2

CMP

IXl

0000

3

4

5

4

SBC

0

IX

1

CMP

IX2 2

LOW
3

SUB

IXl

5

CMP

EXT 3

3

3

2

10

5

6

COM

3

LSRA

CTR

CIR

SBC

IMM

2

COMX

LSR

REL 2

2

2

COMA
5

3

Bec

IMM

HI

F

1111

SUB

IX2 2

4

CMP

IX

4

SUB

EXT 3

3

CMP

SBC

INH

SUB

CIR 3

2

CMP

11

COM

2

5

4

SUB

IMM

2

MUL
1

3

SUB

INH

REGISTER/MEMORY
EXT
1X2
IX1
D
C
E
1100
1101
1110

DIR
B
1011

2

9

NEG

IXl

1001

5

8

NEG X
1

1000

6

REL 2

2

5

BRCLR3 BCLR3
3 BTB 2 esc

3

9

IMM
A
1010

RTS

REL

BSC 2

5

7

INH

1

3

5
2

0110

NEGA

CIR

2

BHI

5

BRCLR2 BCLR2
3 BTB 2 esc

5

0101

REL

2

5

BRSET2 BSET2
3 BTB 2 esc

0100

8

3

5

5

3

6

CONTROL
INH
INH

IX
7
0111

BRN

5

BRSET1 BSET1
3 BTB 2 esc

5
3

NEG

REL

5

BRCLRO BCLRO
3 BTB 2 esc
5

2

BRA
2

4
5

3

5

READ/MODIFYIWRITE
INH
INH
1X1

STA
1

IX

7
0111
-

TABLE 8-7.
BIT
MANIPULATION BRANCH

HI
LOW

8

1001

1010

DIR

INH

INH

IX1

IX

INH

INH

IMM

DIR

EXT

IX2

IX1

IX

0
0000

1
0001

2
0010

3
0011

4
0100

5

6

7

8

9

0101

0110

0111

1000

1001

A
1010

B
1011

C
1100

D
1101

E
1110

F
1111

lOll
I\,)
I

en
~

0
1101

1110

1111

6

3

2

5

LSL

4

3

5

4

CLC
EOR
EOR
EOR
EOR
EOR
INH 2 IMM 2
DIR 3
EXT 3
IX2 2
IXI

6

5

ROLA
ROLX
ROL
ROL
BRCLR4 BCLR4 BHCS
DIR I
INH I
INH 2
IXI
3 BTB 2 BSC 2 REL 2

ROL
I
IX

2
4
5
4
2
3
SEC
ADC
ADC
ADC
ADC
ADC
I
INH 2 IMM 2
DIR 3 EXT 3
IX2 2
IXI

3

5

3

5

5

3

6

5

DEC
DECA
DECX
DEC
BRSET5 BSET5
BPL
DIR I
INH 2
IXI
INH I
3 BTB 2 BSC 2 REL 2

DEC
I
IX

5

5

3

3

3

I

2

I

I

3

5

5

3

3

INCX
BMC
INC
INCA
BRSET6 BSET6
DIR I
INH lINH
3 BTB 2 BSC 2 REL 2

6

2

INC
IXI

5
5
3
4
3
3
5
TSTX
TST
BMS
TST
TSTA
BRCLR6 BCLR6
INH 2
IXI
I
INH I
3 BTB 2 BSC 2 REL 2DIR

4

I

IX

3

5

BIL
BRSET7 BSET7
3 BTB 2 BSC 2 REL
3

5

I
5

3

3

6

CLR
CLRA
CLRX
CLR
BIH
BRCLR7 BCLR7
IXI
DIR 1
INH I
INH 2
3 BTB 2 BSC 2 REL 2

I

INH

Inherent
Accumulator

X
IMM

-

Dirac!

EXT

Extended

REL
BSC
BTB

-

Relative
Bft sal/Clear
Bft Test and Branch

9

1010

5

A

3
lOll

2
4
2
3
3
JMP
JMP
JMP
JMP
JMP
DIR 3 EXT 3
IX2 2
IXI I
IX

1100

2
5
7
5
6
6
6
NOP
BSR
JSR
JSR
JSR
JSR
JSR
I
INH 2 REL 2
DIR 3
EXT 3
IX2 2
IXI I
IX

1101

2
RSP
INH

2
STOP
INH

2

2

4

2
4
3
LOX
LOX
LOX
IMM 2
DIR 3
EXT

2
2
WAIT
TXA
IX I
INH I
INH

5

1111

;/}nJ

CyCLES,----------

~CRO~ONTROLLERS

E

LOX

4
5
6
5
4
STX
STX
STX
STX
STX
2 DIR 3
EXT 3
IX2 2
IXI 1
IX

-

I

0

1110

OPCODE IN

~ HEXADECIMAL

1 ___~~::~.::::~~>~----~7OPCOOEIN

MNE~~=+,

C

IX

,:,,: I

..

B

3

4

LOX
LOX
3 IX2 2
IXI

LEGEND

Index Register
Immediate

DIR

3

2
2
4
5
4
3
3
CU
ORA
ORA
ORA
ORA
ORA
ORA
INH 2 IMM 2
DIR 3 EXT 3
IX2 2
IXI I
IX

Abbreviations for Address Modes:

A

8
1000

1001

5

CLR

EOR
IX

ADD
I
IX

I

TST

I

4

5

IX

LOW
3

ADD
ADD
ADD
3 EXT 3
IX2 2
IXI

INC
I

HI

ADC
I
IX

2
2
3
SEI
ADD
ADD
I
INH 2 IMM 2
DIR

3

BMI
BRCLR5 BCLR5
3 BTB 2 BSC 2 REL

5

F

3

IX

5

E

5

LSLA
LSLX
LSL
LSL
BRSET4 BSET4 BHCC
INH 2
IXI
DIR 1
INH I
3 BTB 2 BSC 2 REL 2

5

C
1100

3

5

5

B

REGISTER/MEMORY

REL

5

A

CONTROL

BSC

5

9

READ/MODIFY/WRITE

BTB

5
1000

HCMOS INSTUCTION SET OPCODE MAP (Continued)

II1II

54

f

BINARY

~~ESS

I

F

ADDRESSING MODES

Indexed, No Offset

The MCU uses ten different addressing modes to provide the
programmer with an opportunity to optimize the code to all
situations. The various indexed addressing modes make it
possible to locate data tables, code conversion tables, and
scaling tables anywhere in the memory space. Short indexed
accesses are single byte instructions, while the longest
instructions (three bytes) permit accessing tables throughout
memory. Short absolute (direct) and long absolute (extended)
addressing are also included. One and two byte direct
addressing instructions access all data bytes in most
applications. Extended addressing permits jump instructions
to reach all memory. Table 8-7 shows the addressing modes
for each instruction, with the effects each instruction has on the
condition code register.

In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first 256
memory locations. These instructions are only one byte long.
This mode is used to move a pointer through a table or to
address a frequently referenced RAM or I/O location.
EA = X; PC +- PC + 1
Address Bus High ..... 0; Address Bus Low ..... X

The term "effective address" (EA) is used in describing the
various addressing modes, and is defined as the byte address
to or from which the argument for an instruction is fetched or
stored. The ten addressing modes of the processor are
described below. Parentheses are used to indicate "contents
of" the location or register referred to; e.g., (PC) indicates the
contents of the location pointed to by the PC. An arrow
indicates "is replaced by", and a colon indicates
concatenation of two bytes.

Indexed, 8-Bit Offset
Here the EA is obtained by adding the contents of the byte
following the opcode to that of the index register; therefore, the
operand is located anywhere within the lowest 511 memory
locations. For example, this mode of addressing is useful for
selecting the mth element in a n element table. All instructions
are two bytes. The content of the index register (S) is not
changed. The content of (PC + 1) is an unsigned 8-bit integer.
One byte offset indexing permits look-up tables to be easily
accessed in either RAM or ROM.
EA = X + (PC + 1); PC ..... PC + 2
Address Bus High ...... K; Address Bus Low ..... X + (PC + 1)
where: K = the carry from the addition of x + (PC + 1).
Indexed, 16-Bit Offset

Inherent
In inherent instructions, all the information necessary to
execute the instruction is contained in the opcode. Operations
specifying only the index register or accumulator, and no other
arguments, are included in this mode.
Immediate
In immediate addressing, the operand is contained in the byte
immediately following the opcode. Immediate addressing is
used to access constants ·which do not change during
program execution (e.g., a constant used to initialize a loop
counter).
EA = PC + 1; PC _ PC + 2
Direct
In the direct addressing mode, the effective address of the
argument is contained in a single byte following the opcode
byte. Direct addressing allows the user to directly address the
lowest 256 bytes in memory with a single two byte instruction.
This includes most on-chip RAM and all I/O registers. Direct
addressing is efficient in both memory and time.
EA = (PC +1);' PC +- PC + 2
Address Bus High ..... 0; Address Bus Low ..... (PC + 1)
Extended
In the extended addressing mode, the effective address of the
argument is contained in the two bytes following the opcode.
Instructions with extended addressing modes are capable of
referencing arguments anywhere in memory with a single
three-byte instruction.
EA = (PC + 1) : (PC + 2); PC ..... PC + 3
Address Bus High ..- (PC + 1); Address Bus Low _ (PC + 2)

In the indexed, 16-bit offset addressing mode, the effective
address is the sum of the contents of the unsigned 8-bit index
register and the two unsigned bytes following the opcode. This
addressing mode can be used in a manner similar to indexed
8-bit offset, except that this three byte instruction allows tables
to be anywhere in memory (e.g., jump tables in ROM). The
content of the index register is not changed.
EA = X + [(PC + 1) : (PC + 2)]; PC ..... PC + 3
Address Bus High ..... (PC + 1) + K
Address Bus Low ..... X + (PC + 2)
where: K = The carry from the addition of X + (PC + 2)
Relative
Relative addressing is only used in branch instructions. In
relative addressing, the content of the 8-bit signed byte following the opcode (the of/set) is added to the PC if and only if the
branch condition is true. Otherwise, control proceeds to the
next instruction. The span of relative addressing is limited to
the range of -126 to +129 bytes from the branch instruction
opcode location.
EA = PC + 2 + (PC + 1); PC +- EA if branch taken;
otherwise, EA = PC +- PC + 2
Bit Set/Clear
Direct addressing and bit addressing are combined in instructions which set and clear individual memory and 1/0 bits. In the
bit set and clear instructions, the byte is specified as a direct
address in the location following the opcode. The first 256
addressable locations are thus accessed. The bit to be
modified within that byte is specified in the first three bits of the
opcode. The bit set and clear instructions occupy two bytes,
one for the opcode (including the bit number) and the other to
address the byte which contains the bit of interest.
EA = (PC + 1); PC +- PC + 2
Address Bus High _ 0; Address Bus Low _ (PC + 1)

2-52

Bit Test and Branch
Bit test and branch Is a combination of direct addressing, bit
seVclear addressing, and relative addressing. The actual bit to
be tested, within the byte, is specified within the low order
nibble of the opcode. The address of the data byte to be tested
is located via a direct address in the location following the
opcode byte (EA1). The signed relative 8-bit offset is in the
third byte (EA2) and is added to the PC if the specified bit is set
or cleared in the specified memory location. This single three

byte Instruction allows the program to branch based on the
condition of any bit In the first 256 locations of memory.

2-53

EA1 = (PC +1)
Address Bus High _ 0; Address Bus Low _ (PC + 1)
EA2 = PC + 3' + (PC + 2); PC _ EA2 If branch taken;
otherwise, PC _ PC + 3

Electrical Specifications
INTRODUCTION
This section contains the electrical specifications and associated timing information.
MAXIMUM RATINGS (Voltages Referenced to Vss)
SYMBOL

VALUE

UNIT

Supply Voltage

VOO

-0.5 to +7

V

Input Voltage

Vln

VSS-0.3to
VOO + 0.3

V

Self-Check Mode (IRQ Pin Only)

Yin

VSS-0.3to
2xVOO +0.3

V

Current Drain Per Pin Excluding
VOOandVss

I

25

rnA

Operating Temperature Range

TA

RATINGS

oC

CDP68HC05C4, CDP68HC05C8,
COP68HC05C7 (Standard)

-40 to +125

COP68HCL05C4, COP68HCL05C8,
COP68HCL05C7 (Low-Power)

Oto+70

COP68HSC05C4, COP68HSC05C8,
COP68HSC05C7 (High-Speed)

Oto+70

Storage Temperature Range

oC

-6510+150

Tstg

This device contains circuitry to protect the inputs against
damage due to high stalic voltage. of electric fields; however, H is
advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages to this high
impedance circuit. For proper operation it is recommended that
Vin and Vout be constrained to the range VSS < (Vin or Vou \) <
Voo. Reliability of operation is enhanced if unused inputs except
OSe2 are connected 10 an appropriate logic voltage level (e.g.,
either VSS or Vee).

THERMAL CHARACTERISTICS
CHARACTERISTICS

SYMBOL

Thermal Resistance

VALUE

UNIT
ocm

OJA

CeramiC Oual-In-Line

50

Plastic Oual-In-Line

100

Plastic Chip Carrier

70

Metric Plastic Quad Flat Pack

120

R2
(SEE TABLE)
TEST
POINT

PINS

R1

R2

C

3.26kO

2.38kO

50pF

1.9kO

2.26kO

200pF

10.19kO

6.32kO

50pF

6kO

6kO

200pF

VOO=4.5V
PAO - PA7, PBO - PB7
PCO-PC7,P06
P01-P04
VOO=3.0V

FIGURE 9.1.

PAO - PA7, PBO - PB7
PCO - PC7, P06
P01-P04

R1
(SEE TABLE)

C
(SEE
TABLE)

EQUIVALENT TEST LOAD

POWER CONSIDERATIONS
The average· chip-junction temperature, TJ, in oc can be
(1)
obtained from: TJ = TA + (PO • 9JA)
Where: TA = Ambient Temperature, oc
9JA = Package Thermal Resistance,
Junction-to-Ambient, 0c/w
Po = PINT + PvO
PINT ICC x VCC, Watts - Chip Internal Power
PI/O Power Oissipation on Input and Output Pins User Oetermined

=
=

For most applications PI/O

< PINT and can be neglected.

An approximate relationship between Po and TJ (if PI/O is
(2)
neglected) is: Po = K + (TJ + 2730 C)
Solving equations 1 and 2 for K gives:
K = Po • (TA

+ 2730 C) + 9JA

• P02

(3)

Where K is a constant pertaining to the particular part. K can
be determined from equation 3 by measuring Po (at
equilibrium) for a known TA. Using this value of K the values of
Po and TJ can be obtained by solving equations (1) and (2)
iteratively for any value of TA.

2-54

CDP68HC05C4, CDP68HC05C8, CDP68HC05C7 ELECTRIOAL SPECIFICATIONS
CDP68HC05C~CDP68HC05C8,CDP68HC05C7

DC ELECTRICAL CHARACTERISTICS (VDO

= 5V de :I: 10%, VSS = OV dc, TA = -400C to +125OC unless otherwise noted)
UMITS

CHARACTERISTIC

SYMBOL

Output Voitage,lLOAO < 10 jJA

Output High Voltage
(ILOAD 0.8 rnA) PAO - PA7, PBO - PB7, PCO - PC7, TCMP
(ILOAD

=
= 1.6 rnA) POl - P04

Output Low Voltage
(I LOAD 1.6 rnA) PAO - PA7, PBO - PB7, PCO - PC7, POl - PD4, TCMP

=

UNIT
V

-

-

0.1

VOO-O.l

-

-

VOH

VOO-0.8

VOH

VDO-0.8

-

-

VOL

-

-

0.4

V

0.7xVOO

-

VOO

V

VSS

-

0.2 xVOO

V

2

-

-

V

3.5

7

rnA

1.6

4

Input Low Voltage
PAO - PA7, PBO - PB7, PCO - PC7, PD~ - P05, P07, TCAP, IRQ,
REsET, OSCl

VIL

VRM

V

25°C

100

-

2

50

00 to 700C

100

-

-

140

-400 to +850 C

100

-400 to +1250 C

100

-

-

-

-

:1:10

pA

-

-

:1:1

pA

-

-

12

pF

100

Walt
Stop

MAX.

VOL

VIH

Supply Current (See Notes)
Run

TYP.

VOH

Input High Voltage
~A7, PBO - PB7, PCO - PC7, POO - PD5, PD7, TCAP, IRQ,
RESET,OSCl

Data Retantion Mode (00 to 700C)

MIN.

100

I/O Ports Hi-Z Leakage Current
PAO-PA7, PBO- PB7,PCO- PC7, POl - P04

IlL

InputCur~

lin

RESET, IRQ, TCAP, OSC1, POO, PD5, P07
Capacitance Ports (as Input or Output)
RESET,IRQ, TCAP, 08Cl, POO - P05, P07

COUT
CIN

pA

180
250

8

NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpcint of voWage range, 250C only.
3. WaH 100: Only timer system active (SPE - TE - RE = 0). If SPI, SCI active (SPE - TE - RE

= 1) add

10% current draw.

4. Run (Operating) 100, WaH 100: Measured using external square-wave clock source (fOSC - 4.2MHz), all Inputs 0.2V from rail, no DC loada, less than 50 pF on all
outputs, CL - 20pF on OSC2.
5. WaH, Slop lee: All ports configurad as Inputs, VIL - O.2V, VIH - Vee - 0.2V.
6. Stop 100 measured with OSCl - VSS.
7. Wait 100 Is affected linearly by the OSC2 capacftanee.

2-55

CDP68HC05C4,CDP68HC05C8,CDP68HC05C7
OC ELECTRICAL CHARACTERISTICS (VOO

= 3.3V dc ±

10%, VSS

= OV dc, TA = -400 C to +1250C unless otherwise noted)
UMITS

CHARACTERISTIC

SYMBOL

Output Voitage,ILOAO ;$ 10 jlA

Output High Voltage
(ILOAO = 0.2 rnA) PAO - PA7, PBO - PB7, PCO - PC7, TCMP
(ILOAO = 0.4 rnA) POl - P04
Output Low Voltage
(I LOAD = 0.4 rnA) PAO - PA7, PBO - PB7, PCO - PC7, POl - P04, TCMP

MIN.

TYP.

-

0.1

V

VOL

VOO-O.l

VOH

VOO-0.3
VOO-0.3

-

-

V

VOH
VOL

-

-

0.3

V

0.7xVOO

-

VOO

V

VSS

-

0.2xVOO

V

-

-

VIH

Input Low Voltage
PAO - PA7, PBO - PB7, PCO - PC7, POO - P05, P07, TCAP,IRO,
RESET,OSCl

VIL

Data Retention Mode (0 0 to 700 C)

VRM

2

Supply Current (See Noles)
Run

100

-

Wait

100
250 C

100

00 to 70 0 C

100

-400 to +850 C

IDO

-400 to +125 0 C

100

I/O Ports Hi-Z Leakage Current
PAO - PA7, PBO - PB7, PCO - PC7, POl - PD4

IlL

Input Current
RESET,IRO, TCAP, OSC1, POO, P05, P07

lin

Capacitance Poris (as Input or Output)
RESET,IRO, TCAP, OSC1, POO - P05, P07

UNIT

VOH

Input High Voltage
PAO - PA7, PBO - PB7, PCO - PC7, POO - P05, P07, TCAP,IRO,
RESET,OSCl

Stop

MAX.

COUT
CIN

-

1

2.5

0.5

1.4

V
rnA

1

30

-

-

120

-

-

±10

jlA

-

-

±1

f1A

-

-

12

pF

-

8

80

jlA

175

NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 2S oC only.
3. Wait 100: Only timer system active (SPE = TE = RE

= 0). If SPI, SCI active (SPE = TE =

RE

= 1) add

10% current draw.

4. Run (Operating) 100, Wait 100: Measured using external square-wave clock source (IOSC = 2.0MHz). ali inputs 0.2V from rail. no DC loads. less than 50 pF on all
outputs, Cl = 20pF on OSC2.
5. Wait, Slop 100: All ports configured as inputs, Vil = 0.2V. VIH = VOO - O.2V.
6. Stop 100 measured wnh OSC1 = VSS.
7. Wait 100 is affected linearly by the OSC2 capacnance.

2-56

CDP68HCOSC4,CDP68HCOSC8,CDP68HCOSC7
CONTROL TIMING (VOO

= S.OV de ± 10%. VSS = OV de. TA = -40 to +12S0 C)
LIMITS
CHARACTERISTIC

SYMBOL

MIN.

MAX.

UNIT
MHz

Frequency of Operation
Crystal Option

fOSC

-

4.2

External Clock Option

fOSC

dc

4.2

Internal Operating Frequency
Crystal (fOSC + 2)

fop

-

2.1

External Clock (fOSC + 2)

faD

dc

2.1

MHz

!eve

480

-

ns

Crystal Oscillator Startup Time for AT-cut Crystal (See Figure 3-1)

tOXOV

-

100

ms

Stop Recovery Start~p Time (AT-cut Crystal Oscillator) (See Figure 9-2)

tilCH

-

100

ms

tRl

1.5

-

!eve

Cycle Time (See Figure 3-1)

RESET Pulse Width (See Figure 3-1)
Timer
Resolution··

tRESl

4.0

-

Input Capture Pulse Width (See Figure 9-3)

ITH.lTl

125

-

Input Capture Pulse Period (See Figure 9-3)

ITlTl

-*

Interrupt Pulse Width low (Edge-Triggered) (See Figure 3-4)

tlllH

125

Interrupt Pulse Period (See Figure 3-4)

tllll

.

-

tOH.tOl

90

-

OSC1 Pulse Width

!eve
ns
!eve
ns

= 3.3V de ± 10%. VSS = OV de. TA = -40 to +1250 C)
LIMITS
SYMBOL

Frequency of Operation
Crystal Option
External Clock Option

MIN.

MAX.

UNIT

fOSC

-

2.0

MHz

fOSC

dc

2.0

Internal Operating Frequency
Crystal (fOSC + 2)

fop

-

1.0

External Clock (fOSC + 2)

fop

dc

1.0

Cycle Time (See Figure 3-1)

!eyC

1000

Crystal Oscillator Startup Time for AT-cut Crystal (See Figure 3-1)

tOXOV

Stop Recovery Startup Time (AT-cut Crystal OSCillator) (See Figure 9-2)

tilCH

-

RESET Pulse Width (See Figure 3-1)

tRl

Timer
Resolution*·

-

ns
ms

100

ms

-

!eve

iRESl

4.0

Input Capture Pulse Width (See Figure 9-3)

ITH.ITL

250

Input Capture Pulse Period (See Figure 9-3)

ITlTl

.**

-

tlllH

250

-

!eyC
ns

Interrupt Pulse Width low (Edge-Triggered) (See Figure 3-4)
Interrupt Pulse Period (See Figure 3-4)
OSC1 Pulse Width

*
**
***

MHz

100

1.5

!evc
ns

tllll

*

-

!eve

tOH.tol

200

-

ns

The minimum period tlllL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcye.
Since a 2-bit prescaler in the timer must count four internal cycles (tcyd. this is the limiting minimum factor in determining the timer resolution.
The minimum period trLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 241cyc'

2-57

a:

I-

z

c.:>

CI

a:

c.:>

iiE

CDP68HC05C4,CDP68HC05C8,CDP68HC05C7

CHARACTERISTIC

a:

::l
CI
CI

!eve
ns

* The minimum period tlLlL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 'eye.
** Since a 2-bit prescaler in the timer must count four internal cycles (tcyC>. this is the limiting minimum factor in determining the timer resolution.
*** The minimum period tTlTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 teye'

CONTROL TIMING (VOO

tn

w

CDP68HC05C4,CDP68HC05C8,CDP68HC05C7
SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9-4)
(VOO = 5.0V de ± 10%, VSS = OV de, TA = -40 to +1250 C)
LIMITS
NUMBER

CHARACTERISTIC
Operating Frequency
Master
Slave

1

CyeleTime
Master
Slave

2

Enable Lead Time
Master
Slave

3

Enable Lag Time
Master
Slave

4

Clock (SCI<) High Time
Master
Slave

5

Clock (SCK) Low Time
Maater
Slave

6

Data Setup Time (Inputs)
Master
Slave

7

Data Hold Time (Inputs)
Master
Slave

SYMBOL

MIN.

MAX.

UNIT

foolml

dc

0.5

fop***

fop(a)

dc

2.1

MHz

tcvclm)

2.0

tcyc(a)

480

-

lcvc
na

tlead(m)

*

tlead(a)

240

-

tlaolm)

*

-

tlag(a)

240

-

na

lw(SCKH)m

340

-

na

tw(SCKH)s

190

-

na

tw(SCKLlm

340

-

ns

tw(SCKL)s

190

-

na

tau(m)

100

tsu(s)

100

-

thlm)

100

-

ns

this)

100

-

ns

na

ns
ns

8

Access Time (Time to data active from high impedance state)
Slave

ta

0

120

ns

9

Disable Time (Hold time to high impedance state)
Slave

tdis

-

240

ns

Data Valid
Maater (Before Capture Edge)

tv(m)

0.25

-

tcvc(m)

240

ns

10

11

Slave (After Enable Edge)**

tv(a)

-

Data Hold Time (Outputs)
Master (After Capture Edge)

!holm)

0.25

-

tcye(m)

tho(s)

0

-

na

trim)

-

100

ns

tr(s)

-

2.0

I'S

100

ns

2.0

I'S

Slave (After Enable Edge)
12

Rise Time (20% VDD to 70% VDD, CL
SPI Outputs (SCK, MOSI, MISO)

= 200 pF)

SPI Inputs (SCK, MOSI, MISO, SS)
13

Fall Time (20% VDD to 70% VDD, CL
SPI Outputs (SCK, MOSI, MISO)

= 200 pF)
tf(m)

SPI Inputs (SCK, MOSI, MISO, SS)

t,(s)

-

* Signal production depends on software.
** Assumes 200 pF load on all SPI pins.
*** Notelhatlhe unH this specification uses is fop (internal operating frequency), nol MHzlin the master mode the SPI bus is capable of running at one-helf of the de·
vice's internal operating frequency, therefore 1.05 MHz maximum.

2-58

CDP68HC05C4,CDP68HC05C8,CDP68HC05C7
SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9-4)
(VDO = 3.3V de ± 10%, VSS = OV de, TA = -40 to +1250 C)
LIMITS
CHARACTERISTIC

NUMBER
Operating Frequency
Master
Slave
1

Cycle Time
Master
Slave

2

Enable Lead Time
Master
Slave

3

Enable Lag Time
Master
Slave

4

Clock (SCK) High Time
Master

Clock (SCK) Low Time
Master
Slave

6

Data Setup Time (Inputs)
Master
Slave

7

Data Hold Time (Inputs)
Master
Slave

8

Access Time (Time to data active from high impedance state)
Slave

9

Disable Time (Hold time to high impedance state)
Slave

10

Data Valid
Master (Before Capture Edge)

11

dc

0.5

fop***

fop(s)

de

1.0

MHz

!eve(ml

2.0

!eyc(s)

1.0

-

!eve
ns

-

ns

-

ns

tlead(ml

*

tlead(s)

500

tlaalm)

*

tlag(s)

500
720

-

ns

tw(SCKH)s

400

tw(SCKLlm

720

Iw(SCKL)s

400

Isu(m)

200

-

ns

tsu(s)

200

-

ns

th(m)

200

ih(s)

200

-

Ie

0

250

ns

'dis

-

500

ns

-

ns

:is

'--

ns
ns

500

!evc(ml
ns

Data Hold Time (Outputs)
Master (After Capture Edge)

iho(m)

0.25

tho(s)

0

-

!eYClm)
ns

trim)

-

200

ns

tr(s)

-

2.0

JlS

200

ns

2.0

JIS

Fall Time (20% VDD to 70% VDD, CL
SPI Outputs (SCK, MOSl, MISO)

=200 pF)
tf(m)
tf(s)

-

Signal production depends on software.

** Assumes 200 pF load on all SPI pins .
•-

Note that the unit this specHicatlon uses is fop linternal operating frequency), not MHz! In the master mode the SPI bus is capable of running at one-half of the device's internal operating frequency, therefore 0.05 MHz maximum.

2-59

a:
.....
z

co
u
co
a:
u

ns

-

=200 pF)

.............

ns

0.25

Rise Time (20% VDD to 70% VDD, CL
SPI Outputs (SCK, MOSI, MISO)

..,a:
co

tv(s)

SPllnputs (SCK, MOSI, MISO, SS)

*

fop(ml

IvIm)

SPllnputs (SCK, MOSI, MISO, SS)
13

UNIT

Slave (After Enable Edge)**

Slave (After Enable Edge)
12

MAX.

Iw(SCKH)m

Slave
5

MIN.

SYMBOL

CDP6BHCL05C4, CDP6BHCL05CB, CDP6BHCL05C7 ELECTRICAL SPECIFICATIONS

CDP68HCL05C4,CDP68HCL05C8,CDP68HCL05C7
OC ELECTRICAL CHARACTERISTICS (VOO

= 5V de ±

10%, VSS

= OV dc, TA = OOC to +700 C unless otherwise noted)
UMITS

CHARACTERISTIC

SYMBOL

MIN.

TYP.

Output Voltage,ILOAO.S 10 pA

Output High Voltage
(ILOAD 0.8 mAl PAC - PA7, PBO - PB7, PCO - PC7, TCMP
(ILOAD

=
= 1.6 mAl PD1 - PD4

Output Low Voltage
(ILOAD = 1.6 mAl PAC - PA7, PBO - PB7, PCO - PC7, PD1 - PD4, TCMP

VDD-0.1

VOH

VDD-0.8

-

-

VOH

VDD-0.8

-

-

VOL

-

-

0.4

V

0.7xVDD

-

VDD

V

O.2xVDD

V

-

V

5.0

mA

Input Low Voltage
PAO- PA7, PBO- PB7,PCO- PC7,PDO- PD5,PD7, TCAP,IRQ,
RESET,OSC1

VIL
VSS
VRM

100

Wait
Stop

100
250 C

100

OOt0700 C

'DO

I/O Ports HI-Z Leaksge Current
PAO - PA7, PBO - PB7, PCO:- PC7, PD1 - PD4

IlL

Input Current
RESET, IRQ, TCAP, OSC1, PD~, PD5, PD7

lin

Capacitance Ports (as Input or Output)
RESET,IRQ, TCAP, OSC1, PD~ - PD5, PD7

V

VOL
VOH

VIH

Supply Current (See Notes)
Run

UNIT

0.1

-

Input High Voltage
PAO - PA7, PBO - PB7, PCO - PC7, PD~ - PD5, PD7, TCAP, IRQ,
RESET,OSC1

DaJa Retention Mode (00 to 700 C)

MAX.

-

COUT
CIN

2

-

~

-

-

-

-

V

2.75
15
25

pA

-

±1

pA

-

-

±1

pA

-

-

12

pF

8

NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint 01 voRage range, 250 C only.
3. Walt 100: Only timer system active (SPE = TE = RE

= 0).11 SPI, SCI active (SPE =

TE

= RE =

1) add 10% current draw.

4. Run (Operating) 100, Wail 100: Measured using external square-wave clock source (IOSC - 4.2MHz), all inputs 0.2V Irom rail, no OC 10ads,Iees than 50 pF on all
outputs, CL K 20pF on OSC2.
5. WaH, Stop 100: All ports configured as inputs, VIL - O.2V, V'H = VOO - 0.2V.
6. Stop '00 measured with OSCI = VSS.
7. WaH '00 is affected linearly by the OSC2 capacHance.

2-60

CDP68HCL05C4,CDP68HCL05C8,CDP68HCL05C7
OC ELECTRICAL CHARACTERISTICS (VOO = 2AV de - 3.6V dc, VSS = OV dc, TA = OOC to +700C unless otherwise noted)
UMITS
CHARACTERISTIC

SYMBOL

Output Voltage, ILOAO S 10 jJA

Output High Voltage
(ILOAO = 0.2 mAl PAO - PA7, PBO - PB7, PCO - PC7, TCMP
(ILOAD = 0.4 mAl P01 - P04
Output Low Voltage
(ILOAD = 0.4 mAl PAO - PA7, PBO - PB7, PCO - PC7, P01 - P04, TCMP

MIN.

TYP.

MAX.

UNIT
V

VOL

-

-

0.1

VOH

VOO-0.1

-

-

VOH

VOO-0.3

-

-

VOH

VOO-0.3

-

-

-

0.3

V

0.7 x VOO

-

VOO

V

VSS

-

0.2xVOO

V

2

-

-

V

VOL

Input High Voltage
PAO- PA7, PBO- PB7, PCO- PC7,POO- P05,P07, TCAP,IRO,
RESET,OSC1

VIH

Input Low Voltage
PAO - PA7, PBO - PB7, PCO - PC7, POO - P05, P07, TCAP,IRO,
RESET,OSC1

VIL

-

Data Retention Mode (00 to 700C)

VRM

Supply Current (3.6 V de at fOSC = 2MHz)
Run

100

-

100

-

250 C

100

-

-

0°to700C

100

-

Supply Current (2.4V de at fOSC = 1 MHz)
Run

100

Wait
Stop

Wait
Stop

1.75

mA

900

jJA

5

jJA

-

10

jJA

-

-

750

jJA

400

jJA

-

-

2.0

jJA

5.0

jJA

-

-

:1:1

jJA

-

-

:1:1

jJA

COUT

-

pF

-

-

12

CIN

100
250 C

100

00to700 C

100

I/O Poris Hi-Z Leakage Current
PAO - PA7, PBO - PB7, PCO - PC7, P01 - P04

IlL

Input Current
RESET, IRO, TCAP, OSC1, POO, P05, P07

lin

Capacitance Ports (as Input or Output)
RESET, fRO, TCAP, OSC1, POO - P05, P07

V

8

NOTES:
1. All values shown reflect average measurements.

2. Typical values at midpoint of voltage range, 2SoC only.
3. Wait 100: Only timer system active (SPE = TE

= RE = 0).11 SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.

4. Run (Operaling) '00, WaH 100: Measured using external square-wave clock source, all inputs 0.2V from rail, no DC loads, less than 50 pF on all outputs,
CL - 20pF on OSC2.
5. WaH, Slop 100: All ports configured as inputs, VIL = O.2V, VIH

= VOO -

0.2V.

6. Stop 100 measured wHh OSCI = Vss.
7. WaH 100 is affected linearly by the OSC2 capacHance.

2-61

CDP68HCLOSC4,CDP68HCLOSC8,CDP68HCLOSC7
CONTROL TIMING (VOO

= S.OV de ±

10%, VSS

= OV dc, TA" 0 to +700C)
UMITS

CHARACTERISTIC

SYMBOL

MIN.

MAX.

UNIT
MHz

Frequency of Operation
Crystal Option

fOSC

-

4.2

External Clock Option

fOSC

de

4.2

Internal Operating Frequency
Cyratal (fOSC + 2)

fop

-

2.1

External Clock (fose + 2)

fOD

de

2.1

Cycle Time (See Figure 3-1)

!eve

480

-

ns

100

ms

MHz

Crystal Oscillator Startup Time for AT-cut Crystel (See Figure 3-1)

tOXOV

Stop Recovery Startup Time (AT-cut Cryetel Oscillator) (See Figure 9-2)

tlLCH

-

100

ms

tRL

1.5

-

!eve

4.0

-

RESET Pulse Width (See Figure 3-1)
Timer
Resolution'"

tRESL

-

!eve
ns

trLTL

...

-

!eyc

Interrupt Pulse Width Low (Edge-Triggered) (See Figure 3-4)

tlLlH

125

ns

Interrupt Pulse Period (See Figure 3-4)

tlLlL

.

-

tOH,tOL

90

-

!eve
ns

Input Capture Pulse Width (See Figure 9-3)

trH,trL

Input Capture Pulse Period (See Figure 9-3)

OSC1 Pulss Width
• The minimum period tlLll should not be less than the number of cycle times ft lake.

125

to execute the Interrupt service routine plus 21 Icyc.

•• Since a 2-bit prescaler In the timer must count four internal cycles (lcye)' this is the limiting minimum factor in dalermining the timer resolution .
.... The minimum period tTlTl should not be less than the number of cycle limes. lakes to execute the capture interrupt service routine plus 241cye.

CDP68HCLOSC4,CDP68HCLOSC8,CDP68HCLOSC7
CONTROL TIMING (VOO

= 2.4V de -

3.6 V dc, VSS .. OV dc. TA

= 0 to +700C)
UMITS
@3.6Vdc

CHARACTERISTIC
Frequency of Operation
Crystal Option
External Clock Option

SYMBOL

MIN.

MAX.

fOSC

-

fOSC

dc

@2.4Vdc
MIN.

MAX.

UNIT

2.0

-

1.0

MHz

2.0

dc

1.0

MHz

Internal Operating Frequency
Cyratal (fOSC + 2)

fop

-

1.0

-

0.5

MHz

External Clock (fOSC + 2)

fOD

dc

1.0

dc

0.5

MHz

tcve

1000

-

2000

-

ns

-

100

ms

Cycle Time (See Figure 3-1)

-

100

fJLCH

-

100

'AL

1.5

Crystal Oscillator Startup Time for AT-cut Crystal (See Figure 3-1)

tOXOV

Stop Recovery Startup Time (AT-cut Crystal Oscillator) (See Figure 9-2)
RESET Pulse Width (See Figure 3-1)
Timer
Resolution--

tRESL

4.0

Input Capture Pulse Width (See Figure 9-3)

trH. trL

250

Input Capture Pulse Period (See Figure 9-3)

trLTL

._.

Interrupt Pulse Width Low (Edge-Triggered) (See Figure 3-4)

fJLlH

250

Interrupt Pulse Period (See Figure 3-4)

ItLiL

.

toH.tOL

200

OSC1 Pulse Width

*

The minimum period tlUL should not be less than the number of cycle limes ft takes

•• Since a 2-bft prescaler In the timer must count four Internal cycles

(lcycl. this

100

ms

-

1.5

-

!eve

-

4.0
500

-

-

-

_.*

500

*
400

to execule the Interrupt service routine plus 21 'eye.

is the limiting minimum factor in delermining the timer resolution.

.... The minimum period ITlTL should not be less than the number of cyele limes • lakes to execute the capture interrupt service routine plus 24 'eye.

2-62

!eve
ns
!eve
ns
!eyc
ns

CDP68HCL05C4,CDP68HCL05C8,CDP68HCL05C7
SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9-4)
(VOO 5.0V de ± 10%, VSS OV de, TA 0 to +700c)

=

=

=

UMITS
NUMBER

CHARACTERISTIC
Operating Frequency
Master
Slave

1

Cycle Time
Master
Slave

2

Enable Lead Time
Master
Slave

3

Enable Lag Time
Master
Slave

4

Clock (SCK) High Time
Master
Slave

5

Clock (SCK) Low Time
Master
Slave

6

Data Setup Time (Inputs)
Master
Slave

7

Data Hold Time (Inputs)
Master
Slave

6

Access Time (TIme to data active from high impedance state)
Slave

SYMBOL

MIN.

MAX.

UNIT

foolm}

dc

0.5

fop'"

fop{s)

dc

2.1

MHz

levelm)

2.0

-

leyc(s)

480

-

tlead(m)

*

-

lieed(s)

240

-

ns

-

ns

tlaalm)

.

tlag(s)

240

tw(SCKH)m

340

tw(SCKH)s

190

twISCKL)m

340

iw(SCKL)s

190

isu(m)

100

tsu(s)

100

th(m}

100
100

-

ns

it!(s)

Ie

0

120

ns

240

ns

9

Olsable Time (Hold time to high Impedance state)
Slave

idis

-

10

Data Valid
Master (Before Capture Edge)

11

!vIm)

0.25

Slave (After Enable Edge)"

!vIs)

-

Data Hold Time (Outputs)
Master (After Capture Edge)

!holm)

0.25

tho(s)

0

Slave (After Enable Edge)
12

Rise Time (20% VOO to 70% VOO, CL
SPI Outputs (SCK, MOSI, MISO)

=200 pF)
trIm)

SPllnputs (SCK, MOSI, MISO, SS)
13

Fall Time (20% VOO to 70% VOO, CL
SPI Outputs (SCK, MOSl, MISO)

tr(s)

=200 pF)
tf(m)

SPllnputs (SCK, MOSI, MISO, SS)

leve
ns

tf(s)

-

-

240

-

ns
ns
ns
ns
ns
ns

ns

leyc(m)
ns
leyc{m)
ns

100

ns

2.0

JIll

100

ns

2.0

JIll

• Signal production depends on software.
•• Assumes 200 pF load on all SPI pins.
••• Nole that the unit this specification uses is fop (internal operating frequency), not MHzl In the master mode the SPI bus Is capable of running at one-half of the davice's Internal operating frequency, therefore 1 .oS MHz maximum.

2-63

CDP68HCL05C4,CDP68HCL05C8,CDP68HCL05C7
SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9-4)
(VOO 2.4V de - 3.6V dc, Vss OV dc, TA 0 to +700C)

=

=

=

UMITS
C!il3.6Vdc
NUMBER

CHARACTERISTIC
Operating Frequency
Master
Slave

1

Cycle Time
Master
Slave

2

Enable Lead Time
Master
Slave

3

Enable Lag Time
Master
Slave

4

Clock (SCK) High Time
Master
Slave

5

Clock (SCK) Low Time
Master
Slave

6

Data Setup Time (Inputs)
Master
Slave

7

Data Hold Time (Inputs)
Master
Slave

8

Access Time (Time to data active from high impedance state)
Slave

MIN.

MAX.

MIN.

MAX.

UNIT

fop(m)

dc

0.5

dc

0.5

fop***

fop(s)

dc

1.0

dc

0.5

MHz

leyc(m)

2.0

2.0

leyc(s)

1.0

-

tleadlm}

*

tlead(s)

500

-

2.0

Icvc
liS

-

*

-

TBD

-

ns

-

*
TBD

-

ns

TBD

-

ns

TBD

-

ns

-

tlag{m)

*

lrag(s)

500

twlSCKHlm

720

iw(SCKH)s

400

iw(SCKL)m

720

-

TBD

tw(SCKL)s

400

-

TBD

tsu(ml

200
200

-

TBD

tsu(s)
!hIm)

200

thIs)

200

-

ta

0

-

ns
ns

TBD

-

TBD

-

ns

TBD

-

ns

250

0

TBD

ns

500

-

TBD

ns

ns
ns

9

Disable Time (Hold time to high impedance state)
Slave

idls

-

10

Data Valid
Master (Before Capture Edge)

tvlml

0.25

-

TBD

Slave (After Enable Edge)**

Iy(s)

-

500

-

Data Hold Time (Outputs)
Master (After Capture Edge)

tho(m)

0.25

-

TBD

tho(s)

0

-

0

-

-

TBD

ns

TBD

liS

TBD

ns

TBD

liS

11

Slave (After Enable Edge)
12

Rise Time (70% VDD to 20% VDD, CL
SPI Outputs (SCK, MOSI, MISO)

=200 pF)
trIm)

SPllnputs (SCK, MOSI, MISO, SS)
13

Fall Time (70% VDD to 20% VDD, CL
SPI Outputs (SCK, MOSl, MISO)

tr(s)

=200 pF)
tllml

SPllnputs (SCK, MOSI, MISO, SS)

*
**
***

C!il2.4Vdc

SYMBOL

t,CS)

-

200
2.0
200
2.0

-

-

levc(ml
ns
leyc(m)
ns

Signal production depends on software.
Assumes 200 pF load on all SPI pins.
Note tha/ the unft this specification uses is fop (internal operating frequency), not MHzl In the master mode the SPI bus is capable of running at on.... half of the d....
vice's Internal opera/ing frequency.

2-64

CDP68HSC05C4, CDP68HSC05C8, CDP68HSC05C7 ELECTRICAL SPECIFICATIONS

CDP68HSC05C4,CDP68HSC05C8,CDP68HSC05C7
DC ELECTRICAL CHARACTERISTICS (VDD

= 5V dc :

10%, VSS

=OV dc, TA = OOC to +700 C unless otherwise noted)
UMITS

CHARACTERISTIC
Output Voitage,lLOAD ~ 10 IlA

Output High Voltage
(ILOAD o.a mAl PAC - PA7, PBO - PB7, PCO - PC7, TCMP
(ILOAO

=
=1.6 mAl P01 - P04

Output Low Voltage
(ILOAD 1.6 mAl PAC - PA7, PBO - PB7, PCO - PC7, P01 - P04, TCMP

=

SYMBOL

MIN.

TYP.

MAX.

UNIT

-

0.1

V

VOL

-

VOH

VOO-0.1

VOH

VOO-o.a

-

VOo-o.a

-

-

V

VOH
VOL

-

-

0.4

V

0.7xVOO

-

VOO

V

Input High Voltage
PAC - PA7, PBO - PB7, PCO - PC7, POO - P05, P07, TCAP,IRO,
RESET,OSC1

VIH

Input Low Voltage
PAC - PA7, PBO - PB7, PCO - PC7, POO - P05, P07, TCAP,IRO,
RESET,OSC1

VIL
Vss

Data Retention Mode (00 to 700C)

VRM

-

•
(I)

a:
....
....
....

0.2xVOO

-

V

CI

a:
z

ICI

V

u

CI

a:

u

Supply Current (See Notes)
Run

100

Wait
Stop

2

-

-

100
250C

100

OOt0700C

100

I/O Ports Hi-Z Leakage Current
PAO-PA7,PBO-PB7,PCO- PC7,P01-P04

IlL

InputCu~

lin

RESET,IRO, TCAP, OSC1, POO, P05, P07
Capacitance Ports (as Input or Output)
RESET,IRO, TCAP, OSC1, POO - P05, P07

COUT
CIN

-

6.7

13.3

3.0

7.6

mA

2.0

50

-

140

pA

-

-

:10

pA

-

-

:1

pA

-

-

12

pF

8

NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage ranga, 250C only.

3. Wait 100: Only timer system active (SPE - TE = RE - 0). If SPI, SCI active (SPE = TE - RE = 1) add 10'!& current draw.
4. Run (Operating) 100, Wait 100: Measured USing externsl square-wave clock source (fose - B.oMHz~ all Inputs 0.2V from rail, no DC 10ads,Iass than 50 pF on all
outputs, CL = 20pF on OSC2.
5. Wait, Stop 100: All ports configured as Inputs, VIL - O.2V, VIH - VOO - 0.2V.
B. Stop 100 measured with OSC1 - VSS'
7. Wait 100 is affected linaarly by the OSC2 capacftance.

2-65

iii

'--

CDP68HSC05C4,CDP68HSC05C8,CDP68HSC05C7
DC ELECTRICAL CHARACTERISTICS (VDD

= 3.3V de ±

10%, VSS

= OV dc, TA = OOC to +700C unless otherwise noted)
UMITS

CHARACTERISTIC
Output Voltage, ILOAD ~ 10 IIA

Output High Voltage
(ILOAD =0.8 rnA) PAO - PA7, PBO - PB7, PCO - PC7, TCMP
(lLOAD

= 1.6 mAl PD1 - PD4

Output Low Voltage
(ILOAD = 1.6 mAl PAO - PA7, PBO - PB7, PCO - PC7, PD1 - PD4, TCMP

SYMBOL

MIN.

TYP.

MAX.

UNIT

0.1

V

VOL

-

-

VOH

VDO-0.1

-

-

VOH

VDD-0.3

-

VDD-0.3

-

-

V

VOH
VOL

-

-

0.3

V

0.7 x VDD

-

VDD

V

VSS

-

0.2xVDD

V

-

-

V

Input High Voltage
PAO - PA7, PBO - PB7, PCO - PC7, PD~ - PD5, PD7, TCAP,IRO,
RESET,OSC1

VIH

Input Low Voltage
PAO - PA7, PBO - PB7, PCO - PC7, PD~ - PD5, PD7, TCAP,IRO,
RESET,OSC1

VIL

Data Retention Mode (00 to 70 0 C)

VRM

2

Supply Current (See Notes)
Run

IDD

-

1.0

2.5

IDD

-

0.5

1.4

-

1.0

30

-

80

IIA

-

-

±10

IIA

-

-

±1

IIA

-

-

12

pF

-

8

Wait
Stop

250 C

IDD

0 0 to 700 C

IDD

I/O Ports Hi-Z Leakage Current
PAO - PA7, PBa - PB7, PCO - PC7, PD1 - PD4

IlL

Input Current
RESET,IRO, TCAP, OSC1, PD~, PD5, PD7

lin

Capacitance Ports (as Input or Output)
RESET,IRO, TCAP, OSC1, PDO- PD5, PD7

COUT
CIN

mA

NOTES:

1. All values shown reflect average measurements.
2. Typical values at midpoint of voUage range, 250 C only.
3. Wait 100: Only timer system active (SPE

= TE = RE = 0). If SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.

4. Run (Operating) 100, Wait 100: Measured using external square-wave clock source (fOSC = 2.0MHz), all inputs 0.2V from rail, no DC 10ads,Iess than 50 pF on all
outputs, CL = 20pF on OSC2.
5. Wait, Stop 100: All ports configured as inputs, VIL = 0.2V, VIH = VOO - 0.2V.
6. Stop 100 measured with OSC1 = VSS'
7. Wait 100 is affected linearly by the OSC2 capacnance.

2-66

CDP68HSC05C4,CDP68HSC05C8,CDP68HSC05C7
CONTROL TIMING (VOO

= 5.0V dc ±

10%. VSS

= OV dc. TA = 0 to +700 C)
LIMITS

CHARACTERISTIC

SYMBOL

Frequency 01 Operation
Crystal Option
External Clock Option

MIN.

MAX.

UNIT

IOSC

-

8.0

MHz

IOSC

dc

8.0

Internal Operating Frequency
Cyrstal (IOSC + 2)

lop

-

4.0

External Clock (IOSC + 2)

lop

dc

4.0

Cycle Time (See Figure 3-1)

MHz

-

ns

!eve

250

Crystal Oscillator Startup Time lor AT-cut Crystal (See Figure 3-1)

tOXOV

-

100

ms

Stop Recovery Startup Time (AT-cut Crystal Oscillator) (See Figure 9-2)

tlLCH

-

100

ms

tRL

1.5

-

!eyC

tRESL

4.0

-

!eve

lTH.lTL

63

-

ns

RESET Pulse Width (See Figure 3-1)
Timer
Resolution"
Input Capture Pulse Width (See Agure 9-3)
Input Capture Pulse Period (See Figure 9-3)

-

!eye

,

-

ns

!eyC

45

-

ns

lTLTL

'"

Interrupt Pulse Width Low (Edge-Triggered) (See Agure 3-4)

tiltH

63

Interrupt Pulse Period (See Figure 3-4)

tlLtL

OSC1 Pulse Width

tOH.toL

CDP68HSC05C4,CDP68HSC05C8,CDP68HSC05C7
= 3.3V dc ± 10%. VSS = OV dc. TA

LIMITS
CHARACTERISTIC

MIN.

MAX.

UNIT
MHz

Frequency 01 Operation
Crystal Option

IOSC

-

2.0

External Clock Option

IOSC

dc

2.0

Internal Operating Frequency
Cyrstal (tosc + 2)

top

-

1.0

External Clock (IOSC + 2)

too

dc

1.0

Cycle Time (See Figure 3-1)

!eyC

1000

Crystal Oscillator Startup Time lor AT-cut Crystal (See Figure 3-1)

tOXOV

Stop Recovery Startup Time (AT-cut Crystal Oscillator) (See Figure 9-2)

tlLCH

-

RESET Pulse Width (See Figure 3-1)

tRL

Timer
Resolution"

ns
ms

100

ms

t(:yC

-

!eve

tRESL

4.0
250

Input Capture Pulse Period (See Figure 9-3)

tri.TL

'"

Interrupt Pulse Width Low (Edge-Triggered) (See Rgure 3-4)

tlLlH

250

Interrupt Pulse Period (See Figure 3-4)

tlLlL
tOH.toL

100

-

lTH.lTL

OSC1 Pulse Width

MHz

1.5

Input Capture Pulse Width (See Rgure 9-3)

,

200

ns

!eyC
ns

!eye

.,. The minimum period tJUL should not be less than the number of cycte times it takes to execute the interrupt service routine plus 21 leyc.

**
***

Since a 2-bit prescaler in the timer must count four internal cycles (tcye)' this is the limiting minimum factor in determining the timer resolution.
The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 241eyc'

2-67

......a:
w

0

a:
....
z:

0
0

a:

eo;,

iiE
'"--

= 0 to +700 C)
SYMBOL

C/O

eo;,

..
* The minimum
period tlllL should not be less than the number of cycle times it takes to execute the Interrupt service roullne plus 21 Icyc** Since a 2-bit prescaler in the timer must count four internal cycles (leyd. this is the limiting minimum factor in determining the timer resolution.
*** The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24lcyc.

CONTROL TIMING (VOO

•

ns

CDP68HSC05C4,CDP68HSC05C8,CDP68HSC05C7
SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9-4)
(VOO
5.0V de ± 10%, VSS OV dc, TA
0 to +70OC)

=

=

=

LIMITS
NUMBER

CHARACTERISTIC

SYMBOL

Operating Frequency
Master
Slave
1

Cycle Time
Master
Slave

2

Enable Lead Time
Master

Enable Lag Time
Master

Clock (SCK) High Time
Master
Slave

5

Clock (SCK) Low Time
Master
Slave

6

Oats Setup Time (Inputs)
Master
Slave

7

Oats Hold Time (Inputs)
Master
Slave

8

foplml

dc

0.5

fop·'"

fop(s)

dc

4.0

MHz

tcvc
ns

TBD

-

ns

tlag(m)

.
.

-

tlag(s)

TBD

-

ns

twlSCKHlm

TBD

tw(SCKH)s

TBD

twlSCKLlm

TBD

tw(SCKL)s

TBD

tcvclm\

2.0

tcyc(s)

250

Access Time (Time to dats active from high Impedance state)
Slave

TBD

-

ns

~(s)

TBD

-

ns

ta

0

TBD

ns

TBD

ns

-

tv(m)

TBD

Slave (After Enable Edge)··

tv(s)

-

Data Hold Time (Outputs)
Master (After Capture Edge)

~o(ml

TBD

tho(s)

0

13

Fall Time (20% VDD to 70% VDD, CL
SPI Outputs (SCK, MOSI, MISO)

=200 pF)
trIm)
tr(s)

=200 pF)
tf(ml

SPllnputs (SCK, MOSI, MISO, SS)

ns

th(ml

tdis

SPllnputs (SCK, MOSI, MISO, SS)

ns

TBD

Oats Valid
Master (Before Capture Edge)

Rise Time (20% VDD to 70% VDD, CL
SPI Outputs (SCI<, MOSI, MISO)

-

ns

TBD

10

12

-

ns

tsu(s)

Disable Time (Hold time to high impedance stste)
Slave

Slave (After Enable. Edge)

-

tsu(m)

9

11

*

UNIT

tlead(s)

Slave
4

MAX.

tleadlml

Slave
3

MIN.

tf(s)

-

TBD

-

ns
ns

tcyc(m)
ns

tcyc(ml
ns

TBD

ns

TBD

p8

TBD

ns

TBD

I'S

Signal production depends on software.

•• Assumes 200 pF load on all SPI pins.
••• Note thatlhe unft this specftication uses is fop (internal operating frequencyl, not MHz! In the master mode the SPI bus 18 capable of running at one-half of the davice's internal operating frequency, therefore 2.0 MHz maximum.

2-68

CDP68HSC05C4,CDP68HSC05C8,CDP68HSC05C7
SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9-4)
(VOO
3.3V de ± 10%, VSS OV dc, TA 0 to +700 C)

=

=

=

LIMITS
NUMBER

CHARACTERISTIC
Operating Frequency
Master
Slave

1

Cycle Time
Master
Slave

2

Enable Lead Time
Master

Enable Lag Time
Master

Clock (SCK) High Time
Master
Slave

5

Data Setup Time (Inputs)
Master
Slave

7

Data Hold Time (Inputs)
Master
Slave

8

dc

0.5

fop·....

fop(s)

dc

1.0

MHz

lovclml

2.0

-

loyc(s)

1.0

-

love
ns

500

-

ns

tlaalml

.
.

tlag(s)

500

-

ns

tw(SCKHlm

720

-

ns

tw(SCKH)s

400

-

ns

tw(SCKL)m

720

-

ns

tw(SCKL)s

400

-

ns

tsu(m)

200

-

ns

tsu(s)

200

-

ns

thlml

200

-

ns

thIs)

200

-

Access Time (lime to data active from high impedance state)
Slave

ns

la

0

250

ns

500

ns

Disable Time (Hold time to high impedance state)
Slave

Idis

-

10

Data Valid
Master (Before Capture Edge)

12

13

~

'vIm)

0.25

-

Iv(s)

-

500

Data Hold Time (Outputs)
Master (After Capture Edge)

Iho(m)

0.25

-

loyc(m)

Slave (After Enable Edge)

tho(s)

0

-

ns

trlml

-

200

ns

tr(s)

-

2.0

"S

II(m)

-

200

Rise Time (20% VOO 10 70% VOO, CL
SPI Outputs (SCK, MOSI, MISO)

Fall Time (20% VOO to 70% VOO. CL
SPI Outputs (SCK, MOSI, MISO)

~
.....
o

a:

Slave (After Enable Edge)'"

= 200 pF)

SPllnputs (SCK, MOSI, MISO, SS)

= 200 pF)

SPllnputs (SCK, MOSI, MISO, SS)

*

fop(m)

9

11

**
***

UNIT

I-

z:

o

c.:I

o
a:

c.:I

Clock (SCK) Low Time
Master
Slave

6

MAX.

tlead(s)

Slave

4

MIN.

tlead(m)

Slave

3

SYMBOL

tf(s)

2.0

'cyc(ml
ns

ns

,,8

Signal production depends on software.
Assumes 200 pF load on all SPI pins.

Note that the unit this specification uses is fop (internal operating frequency), not MHz! In the master mode the SPI bus is capable of running at one-half of the de·
vice's internal operating frequency. therefore 2.0 MHz maximum.

2-69

:E

Control Timing Diagrams (All types)

OSC1'

RESET

~11l1IJ7711III1111III11IIIII1111 ~

---.I'
~

~

I---

K

r---

ll/llll

tRL -

I

f-

tIUH-

K

,

7tlLCH

~<-

4064tCYC -

INTERNAl
CLOCK

~~~~ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX~
-v--'
RESET OR INTERRUPT
VECTOR FETCH
NOTES:
1. Represents the internal gating 01 the OSC 1 pin.
2.

"iFiQ pin edge-sensitive

mask option.

3. IRQ pin level and edge-sensRive mask option.
4. CDP6BHC05C4

RESET vector address shown 'or timing example.
FIGURE

9~2.STOP

RECOVERY TIMING DIAGRAM

---I
nJ1J1J1J1Jl
tTLTLr--

EXTERNAl SIGNAl
(TCAPPIN

3n

---ItTHI----jtTLt-

------------~
FIGURE 9-3.

~-----------TIMER RELATIONSHIPS

2-70

Serial Peripheral Interface (SPI) Timing Diagrams (All types)

HElD HIGH ON MASTER
SS
(lNPUn

SCK
(OUTPUn

MISO
(INPUT)

001

MOSI
(OUTPUn

(a) SPI Master Timing CPOL

= 0, CPHA = 1

HELD HIGH ON MASTER

ss
(INPUn

SCK
(OUTPUT)

MISO
(INPUT)

001

MOSI
(OUTPUT)

NOTE:

Measurement points are VOL. VOH. VIL. VIH.

(b) SPI Master Timing CPOL = 1, CPHA = 1
FIGURE 9.4. TIMING DIAGRAM

2-71

HELD HIGH ON MASTER

ss
(lNPUn

SCI<
(OUTPUn

MISO
(INPUn

MOSI
(OUTPUn

(e) SPI Master Timing CPOL

= 0, CPHA = 0

HELD HIGH ON MASTER

ss
(INPUn

SCI<
(OUTPUn

MISO
(INPUn

MOSI
(OUTPUn

NOTE:

Measurement points are VOL' VOH. VIL and VIH'

(d) SPI Master Timing CPOL = 1, CPHA
FIGURE 9-4.

=0

TIMING DIAGRAMS (Continued)

2-72

SS
(INPUn

SCK
(INPUn

MISO
(OUTPUn

MOSI
(INPUn

(a) SPI Slave Timing CPOL = 0, CPHA = 1

SS
(IN PUn

SCK
(INPUT)

MISO
(OUTPUT)

MOSI
(INPUT)

NOTE:

Measurement pOints are VOL, VOH, VIL, and VIH.

(f) SPI Slave Timing CPOL = 1, CPHA = 1

FIGURE 9-4.

TIMING DIAGRAMS (Continued)

2-73

SS
(INPUT)

SCK
(INPUT)

MISO
(OUTPUT)

MOSI
(INPUT)

(g) SPI Slave Timing CPOL = 0, CPHA = 0

SS
(INPUT)

SCK
(INPUT)

MISO
(OUTPUT)

MOS!
(INPUT)

NOTE:

Measurement points are VOL. VOH. VIL and VIH-

(h) SPI Slave Timing CPOL
FIGURE 9-4.

= 1, CPHA = 0

TIMING DIAGRAMS (Continued)

2-74

Mechanical Data
This section contains the pin assignment diagrams for the HCMOS family microcomputers.

Pinouts

RESET
IRQ

NC

V DD
OSCl
OSC2
TCAP

PA6

PD7

PAS

TCMP

r-

PAS

'3.

",'38
"r'37
"r'36
",'35
",'34
"-

PA4

PA4

PDSiSS

PA3

PD41SCK

PA2

PD3IMOSI

PAl

'2J
-,
'2J

PAl

PD21MISO

PAO

1!]

PAO

PD1/TDO

PBO 1;1

PBO

PDO/RDI

PBl

PBl

PCO

PB2

PB2

PCl

PB3

PC2

PB4

PC3

PBS

PC4

PB6

PCS

PB7

PC6

VSS

PC7

PA3
PA2

-,

_.
-,

PD7
TCMP
PDSiSS
PD4JSCK
PD3IMOSI

en
a:

PD21MISO

:::::
Q

PD1/TDO

':,J
-,

PDO/RDI

PB3

'!'J

PCl

PB4

17]

':J
-,

PCO

PC2

r-, ,-, r-, ,-, ,-, ,-, r-, ,-, ,-, ,-, r-,
11811191120112111221123112411251126112711281

D Suffix - 4O-Lead Dual-In-Llne Side-Brazed Ceramic Package
E Suffix - 40-Lead Dual-In-Llne Plastic Package

2-75

N Suffix - 44 Lead Plastic Chip-Carrier (PLCC) Package

w

a:

IZ

Q

Co)

Q

a:

Co)

iiE

Pinouts (Continued)

6f(1~·~Ill!llt;!Il~~

PA6

1

33

TCMP

PAS

2

32

PDSISS

PM

3

31

PD4ISCK

PM

4

30

PD3JMOSI

PA2

5

29

PD2JMISO

PAl

6

28

PD1ITOO

PAC

7

27

PDOJRDI

PBO

6

26

PBl

9

25

PCO
Pel

PB2

10

24

Pe2

PB3

11

23

Pe3

~,~

:!! l!?

~ ~ ~!il z;j z;j

Q SUFFIX - 44 LEAD METRIC PLASTIC QUAD FLATPACK

2-76

CDP68HC05D2

mlHARRIS

HCMOS Microcontroller

January 1991

Features
• Typical Power. Operating ...•••••••.••.•• 17.SmW
• WAIT .•••..•..•..••.••.•••.• 8mW
• STOP ••.•••••.•.••••••...• 10.0jlW
• Fully Static Operation
• On-Chip RAM •..•...•••.•..•••.•..•..•.••. 96 Bytes
• On-Chip ROM ......•••...•.•..•••.•.•.. 2176 Bytes
.1/0 Lines
• Bidirectional I/O Lines ••••••.••••••••.•••••••.• 28
• Input Only Lines •••.•••••••••..•.•••••••••.••••• 3
• Programmable Open Drain Output Lines ..•...•..• 12
• On-Chip Oscillator for Timer
• Internal 16-Bit Timer
• Serial Peripheral Interface (SPI)
• External (IRQ), Timer, Port B and Serial Interrupts
• Self Check Mode
• Single 2.SV to 6V Supply (2V Data Retention Mode)
• RC or Crystal On-Chip Oscillator
• axa Multiply Instruction
• True Bit Manipulation
• Indexed Addressing for Tables
• Memory Mapped I/O

General
The COP68HC05D2 Microcontroller Unit (MCU) belongs to
the CDP6805 Family of Microcontrollers. This 8-bit MCU
contains on-chip oscillator, CPU, RAM, ROM, I/O, and Timer.
The fully static design allows operation at frequencies down
to DC, further reducing its already low power consumption. It
is a low power processor designed for low end to mid range
applications in the telecommunications, consumer, automo'
tive and industrial markets where very low power consump·
tion constitutes an important factor.
The COP68HC0502 is supplied in a 40 lead hermetic dualin-line sldebrazed ceramic package (0 suffix), a 40 iead

Pinouts

dual-in-line plastic package (E suffix), a 44 lead plastic chip
carrier (N suffix), and a 44 lead metric plastic quad flatpack
(0 suffix).

Functional Pin Descriptions
voo and VSS
Power is supplied to the MCU using these two pins. VOO is
power and VSS is ground.
N.C•
The pin labelled N.C. should be left disconnected.
IRQ (Maskable Interrupt Request)
IRO is a programmable option which provides two different
choices of interrupt triggering sensitivity. These options are:
1. Negative edge sensitive triggering only, or
2. Both negative edge sensitive and level sensitive
triggering.
In the latter case, either type of input to the IRO pin will produce the interrupt. The MCU completes the current instruction
before it responds to the interrupt request. When the IRQ pin
goes low for at least one tILlH, a logic one is latched internally
to signify that an interrupt has been requested. When the
MCU completes its current instruction, the interrupt latch is
tested. If the interrupt latch contains a logiC one, and the interrupt mask bit (1 bit) in the condition code register is clear, the
MCU then begins the interrupt sequence. If the option is selected to include level sensitive triggering, then the IRO input
requires an external resistor to VDD for "wire-OR" operation.
See the INTERRUPTS information for more detail.
RESET
The RESET input is not required for startup but can be used
to reset the MCU internal state and provide an orderly software startup procedure. Refer to the RESETs information for
a detailed description.

40 LEAD CERAMIC SIDEBRAZE DIP
40 LEAD PLASTIC DIP
TOP VIEW

44 LEAD PLAST1C CHIP CARRIER
TOPV1EW

~ ~ ~ ~ !~ l~ ~ ~ ~ ~ ~
ti

:.!.: ~!!~ :.~.: :.lU :.~.:

PAS

n

L~j

•

- N ..

:.'!!: :.t:i";

~.: ~;iU

:'i'!.

[!9

PD3/MOSl

PA3

!J

PA2

lj]

PO?

l~8 TeMP

PA4 !]

[!7 PD5JSS

L~6 PlJ4;SCK

PA 1 lJ]

[is

P03/MOSI

13]

L!-c

PD2IMISO

PAD

PDO/fOSC1

1~]
PB1 1~]

PCO

PB2

1~1

[~1 PCO

PB3

1!1

[!o

Pel

PB4

'I]

LiD

PC2

P01/T0SC2

L~3 PD1/TOSC2
[~2 POO/TOSC1

P80

PC,
PC:!
PC>

:--.,

~-"t

r'" roO., roO, roO, roO., r-... r-.,

11811101120:

F("A

~ ~

f

:211 :221 ,281 IN! L251

""'1 ,.-.,

I?tII 1211 1281

~ ~ ~ ~ ~ ~ ~ ~

NOTE: 44 LEAD METRIC PLASTIC QUAD FLATPACK TBD
Copyright

©

Harris Corporation 1991

File Number

2-77

1557.1

c:n

a::
....

::.::I
CI
a::
:z

ICI

u

~
u

is

CDP68HC05D2
TCMP
Internal
.--_ _ _ _ _ _-'-1 RESET

_------=2:.,. IRQ
Port
A
I/O
lines

Port
B
I/O
Lines

PAO
PA1
PA2
PA3
PA4
PA5PA6
PAl,

PBO
PB1
PB2
PB3
P'B4
PB5
PB6
PB7

PCO

Accumulator
A

8
Data
Dir
Reg

8

5

6
Data
Dir
Reg

Index
Register

X
Condition
Code
Register CC
CPU
Stack
Pointer

S

5

Program
Counter
High PCH

8

Program
Counter
low PCl

f

CPU
Control

Data
Dir
Reg

Port
C
Reg

~=~::::c~~~~
Data

Dir
Reg

Port
0
Reg

AlU

PC1 Port
PC2
C
PC3 I/O
PC4 Lines
PC5
PC6
PC7
To Timer System
PD7
TOSCt (PDO)I
TOSC2 (PDt)

Timer
Oscillator

MISO {PD21
MOSI {PD31
SCK {P041
55 {PD51

SPI
System

SPI
S tern
Internal
Processor
Clock

240 x 8
Self-Check
ROM

92CM-38117RI

Fig. 1 - CDP68HC05D2 CMOS microcomputer block diagram.

'TCAP
The TCAP input controls the input capture feature for. the
on-Chip programmable timer system. Refer to the INPUT
CAPTURE REGISTER section for additional information.

TeMP
The TCMP pin (35) provides an output for the output compare feature of the on-Chip timer system. Refer to the OUTPUT COMPARE REGISTER section for additional informa- .
tion.

OSC1,OSC2
The CDP68HC05D2 can be configured to accept either a
crystal input or an RC network to control the internal oscillator. This.option is mask selectable. The internal clocks are
derived by a divide-by-two of the internal oscillator frequency (fose).

_CERAMIC RESONATOR (CRYSTAL OPTION")
A ceramic resonator may be used in place of the crystal in
cost-sensitive applications. The circuit in Fig. 2(b) is
recommended when using a ceramic resonator. Fig. 2(a)
lists the recommended capacitance and feedback resistance
values. The manufacturerofthe partk:ular.ceramic resonator
being considered should _be consulted for specific information.
RC. (RESISTOR OPTION*)
If the RC oscillator option is selected. then a resistor is
connected to the oscillator pins as shown in Fig. 2(d).
EXTERNAL CLOCK.

An external clock should be applied to the OSC1 input with
the OSC2 Input not connected, as shown In Fig. 2{e). An
external clock may be used with either theRC or crystal ascii.
··Iatar option, however, the crystal option Is recommended to
reduce loading on the external clock source. The toxov or
CRYSTAL. (CRYSTAL OPTION*)
tlLCH specifications do not apply when using an external
The circuit shown in Fig. 2(b) is recommended when using clock Input. The equivalent specification of the external clock
a crystal. The internal oscillator is designed to interface should be used In lieu of toxov or tILCH'
with an AT-cut parallel resonant quartz crystal resonator in
PAO-PA7
the frequency range specified for fose in the control timing
charts. Use of an external CMOS oscillator is recommended These eight VO Input comprise port A. The state of any pin Is
when crystals outside the specified ranges are to be used. software programmable and all port A lines are configured as
T·he crystal and components should be mounted as Close as
input during power-on or reset. These lines are open drain
possible to the input pins to minimize output distortion and
startup stabilization time. Refer to the Electrical Character- software programmable. Refer ta INPUT/OUTPUT PROGRAMMABLE Information below for a detailed description of
istics Table.
VO programming.
.. Intemal oscillator Input mask options

2-78

CDP68HC05D2

Crystal
RSMAX
Co
C,
Casc,
Casc2
Rp

a

Ceramic Resonator

2MHz

4 MHz

Units

400
5
0.008
15-40
15-30
10
30

75
7
0.012
15-30
15-25

0

pF
pF
pF
pF

10
40

2-4 MHz
10
40
4.3
30
30
1-10
1250

Rs (typical)
Co
C,
Casc,
CaSC2
Rp

MO

a

K

Units

0

pF
pF
pF
pF
MO

-

(a) Crystal/Ceramic Resonator Parameters

L

CDP68HC0!5D2
OSC1

OSC 2

39

OSC I

39

38

OSC2

38

Rp

_38_________U~I----------39(c) Equivalent Crystal Circuit

(b) Crystal Oscil/ator Connections

CDP'68HC05D2

CDP68HC0!5D2
OSC1

39

OSC2

6
38

R

UNCONNECTED
-

REsEr

4.7K

CDP&8HCOSD2
2

10K
...AA

+¢V

..Y

2NU04

iRQ

'-'-_-+-I"O~
f-1

iiffiT,

10K

-----l

-=-

N·C,

10K

~

-

TCAP
PA7

1

.........!
L----.!.
10
II

PA5
PA4

ISEENOTEI
P07

PD5/SS

PA2

PD4/SCK

PAl

P03/MOSI

PAO

P02/MISO

POO/TOSCI

?

.-- ~

14

15

L...!!
L...-...!!.
18
19

3.

-=-

~

TCMP~

PA3

POIITOSC2

12

20pF
!-i..

39

10M ~4 MHZ-=~M~
_ _ _~~-i~
OSC 2 ,-\...L

~ PA6
6

-=-

VOO 1-4;:.:0=--......~O + 5V
OSC I

37

10K

I

PBO

PCO

PBI

PC 1

34

33

1M

32
r'=-----?-_-_VI~VKv_-;
31
30
t-"-_"I"~,,AK_-oU
+5V
29
2B
27

2N39O

I

...,
......

L-_ _ _-,:!
1<;>+ 5 V
4.7K

I'

I~'

L...

4.7K

PB2
PB3
PB4
PBS
PBS
PB7

PC71-"-'21_ _+_--,
92CM-39369

NOTE~E

RC OSCILLATOR OPTION MAYilLSO BE USED IN THIS CIRCUIT

Fig. 7 - Self-Check Circuit Schematic Diagram

2-84

CDP68HC05D2
Self-Check
The CDP68HC05D2 contains in mask ROM address locations $1 FOO to $1 FEF, a program designed to check the
part's integrity with a minimum of support hardware. The
self-check capability of the CDP68HC05D2 MCU provides
an internal check to determine if the device is functional.
Self-check is performed using the circuit shown in the
schematic diagram of Fig. 7. As shown in the diagram, port
C pins PCO-PC3 are monitored (light-emitting diodes are
shown but other devices could be used) for the self-check
results. The self-check mode is entered by aP.2!Ying a 9Vdc
input (through a 4.7 kilohm resistor) to the IRQ pin (2). a
5Vdc input (through a 10-kilohm resistor) to the TCAP pin
(37). a 5Vdc input (through a 10K resistor) to Port B, bit 2
(pin 14). and then depressing the reset switch to execute a
reset. After reset, the following six tests are performed automatically:
I/O - Functionally exercises ports A, B, and C
RAM - Counter test for each RAM byte
Timer - Tracks counter register and checks OCF flag
ROM - Exclusive OR with odd ones parity result
SPI - Transmission test with check for SPIF, WCOl,
and MODF flags
INTERRUPTS - Tests external, timer, Port Band SPI
interrupts.
Self-check results (using LEOs as monitors) are shown in
Table III. The following subroutines are available to user
programs and do not require any external hardware.
Table III. Self-Check Results
PC3 PC2 PCl PCO
0

0

1

Bad liD

1

0

1

0

Bad RAM

1

0

1

1

Bad Timer

1

1

0

0

Bad Port 0 andlor Timer Oscillator

1

1

0

1

Bad ROM

1

1

1

0

Bad SPI

1

1

1

1

Flashing
All Others

RESETS
The CDP68HC05D2 has two reset modes: an active low
external reset pin (RESET) and a power-on reset function;
refer to Fig. 8.
RESET Pin
The RESET input pin is used to reset the MCU to provide an
orderly software startup procedure. When using the external reset mode, the ~pin must stay lowfora minimum
of one and one-half tcyc. The RESET pin contains an internal
SchmiltTrigger as part of its inputto improve noise immunity.
Power-On-Reset
The power-on reset occurs when a positive transition is
detected on V DD . The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any drops in the power supply voltage. There is no provision
for power-down reset. The power-on circuitry provides for a
delay from the time that the oscillator becomes active upon
power-up or when exiting the STOP mode.
Associated with the mask programmable CPU oscillator
option in the 02 is a mask option for controlling the timeout
which occurs at power-on or when exiting the STOP mode.
The user has a mask option of selecting a 4064 tcyc delay
(which is required for the on-chip crystal OSCillator) or a 2 cycle timeout permitting faster startups with the RC oscillator
mask option or external oscillator.
To permit use of an external oscillator with crystal mask
option and a two cycle delay when exiting from STOP, bit 2
(Dl V) of the Special Port Control/Status Register (memory
location $001 E). when set, will override the 4064 cycle
mask-programmable delay and force a two cycle timeout.
Since this bit is reset at power-on, the power-on delay will
remain as mask-programmed.

Remarks

1

to compute a checksum of the entire ROM pattern. Upon
return to the user's program, X=O. If the test passed, A=O.
RAM locations $OOAO through $00A3 are overwritten.

If the external RESET pin is low at the end of the delay
timeout, the processor remains in the reset condition until
the RESET goes high. Table IV shows the actions of the two
resets on internal circuits, but not necessarily in order of
occurrence.

Bad Interrupts or IRQ Request
Good Device

Interrupts

Bad Device, Bad Port C, etc.

o indicates lED on; 1 indicates lED is off.
TIMER TEST SUBROUTINE
This subroutine returns with the Z bit cleared if any error is
detected; otherwise, the Z bit is set. This subroutine is
called at location $1 FOE. The output compare register is
first set to the current timer state. Because the timer is
free-running and has only a divide-by-four prescaler, each
timer count cannot be tested. The test reads the timer once
every 10 counts (40 cycles) and checks for correct counting. The test tracks the counter until the timer wraps
around, triggering the output compare flag in the timer
status register. RAM locations $OOAO and $00A1 are overwritten. Upon return to the user's program, X=40. If the test
passed, A=O.

ROM CHECKSUM SUBROUTiNE
This subroutine returns with the Z bit cleared if any error is
detected; otherwise, the Z bit is set. This subroutine is
called at location $1 F93 with RAM location $00A3 equal to
$01 and A = O. A short routine is set up and executed in RAM
2-85

Systems often require that normal processing be interrupted so that some external event may be serviced. The
CDP68HC05D2 may be interrupted by one of five different
methods: either one of four maskable hardware interrupts
(i"RU, SPI, PBINT, or Timer) and one non-maskable software interrupt (SWI). Interrupts such as Timer and SPI have
several flags which will cause the interrupt. Generally, interrupt flags are located in read-only status registers, while
their equivalent enable bits are located in associated control registers. If the enable bit is a logic zero it blocks the
interrupt from occurring but does not inhibit the flag from
being set. Reset clears all enable bits to preclude interrupts
during the reset procedure.
The general sequence for clearing an interrupt is a software
sequence of first accessing the status register while the
interrupt flag is set, followed by a read or write of an associated register. When any of these interrupts occur, and if
the enable bit is a logic one, normal processing is suspended at the end of the current instruction execution.
Interrupts cause the processor registers to be saved on the
stack (see Fig. 6) and the interrupt mask (I bit) set to prevent

en

a::

....w
....

CI

a::

I-

z

CI

u

CI

a::

u

:iE

CDP68HC05D2

2

tcyc OR

4064 tcyc

****

INTERNAL
PROCESSOR
CLOCK

*

INTERNAL
ADDRESS
BUS

*

INTERNAL
DATA - - - - i
BUS*

*"**
"* **
"****

RESET-------------------------~.~+---tR-t-~--rr--------------------------~*If~¥
INTERNAL TIMING SIGNAL AND BUS INFORMATION NOT AVAILABLE EXTERNALLY.
92CM-39377
OSC1 LINE IS NOT MEANT TO REPRESENT FREQUENCY. IT IS ONLY USED TO REPRESENT
TIME.
THE NEXT RISING EDGE OF THE INTERNAL PROCESSOR CLOCK FOLLOWING THE RISING
EDGE OF JtESE't INITIATES THE RESET SEQUENCE.
DELAY IS MASK PROGRAMMABLE. (REFER TO THE SECTION D£SCRIBING POWER-ON-RESET IN THE RESETS
INFORMATION OF THIS DATA SHEET).

Fig. 8 - Powe;-On Reset and RESET

Table IV. Reset Action on Internal Circuit
Condition
Timer Prescaler reset to zero state
Timer counter configured to $FFFC
Timer output compare (TCMP) bit reset to zero
All timer interrupt enable bits cleared (lCIE. OCIE. and TOlE) to disable timer interrupts.
The OlVl timer bit is also cleared by reset.
All data direction registers cleared to zero (input)
Configure stack pointer to $OOFF
Force internal address bus to restart vector ($1 FFE-$1 FFF)
Set I bit in condition code register to a logic one
Clear STOP latch"
Clear external 'interrupt latch
Clear WAIT latch _
Disable SPI (serial output enable control bit SPE=O). Other SPI bits cleared by reset include:
SPIE. MSTR. SPIF, WCOl, and MODF.
Clear serial interrupt enable bit
Place SPI system in slave mode (MSTR=O)
Extemal timer oscillator disabled and 3-stated

CPU oscillator connected to timer
Reset Port B interrupt enable
DWOM bit reset
PAOD bit reset
Reset Dl Y bit in special control/status register
"Indicates that timeout still occurs with RESET pin
2-86

CDP68HC05D2

additional interrupts. The appropriate interrupt vector then
points to the starting address ofthe interrupt service routine
(refer to Fig. 4 for vector location). Upon completion of the
interrupt service routine, the RTI fnstruction (which is normallya part of the service routine) causes the register contents to be recovered from the stack followed by a return to
normal processing. The stack order is shown in Fig. 6.

Note: The interrupt mask bit (I bit) will be cleared upon returning
from the interrupt if and only if.the corresponding bit stored in the
stack is zero. The priority of the various interrupts is as follows
(highest priority to lowest priority:
RESET - ' - EXT INT - TIMER - SPI - PortS
'is any instruction or the SWI service routine.
A discussion of interrupts, plus a table listing vector addresses for
all interrupts including reset, in the CDP68HC05D2 is provided in
TableV.

Table V. Vector Address for Interrupts and Reset
Register
N/A
N/A
N/A
Timer Status
SPI Status
Special
Port cis

Flag
Name

Interrupts

N/A
N/A
N/A
ICF
OCF
TOF
SPIF
MODF

Reset
Software
External Interrupt
Input Capture
Output Compare
Timer Overflow
Transfer Complete
Mode Fault

PBIF

Port B

Hardware Controlled Interrupt Sequence
The following three functions (RESET, STOP, and WAIT)
are not in the strictest sense an interrupt; however, they are
acted upon in a similar manner. Flowcharts for hardware
interrupts are shown in Fig. 9, and for STOP and WAIT are
provided in Fig. 10. A discussion is provided below:
• A low input on the RESET input pin causes the program to
vector to its starting address which is specified by the
contents of memory locations $1 FFE and $1 FFF. The I bit
in the condition code register is also set. Much of the
MCU is configured to a known state during this type of
reset as previously described in the RESET paragraph.
• STOP - The STOP instruction causes the oscillator to be
turned off and the processor to "sleep" until an external
interrupt (mo), Port B interrupt, Timer interrupt (if using
an external timer clock), or RESE occurs.
• WAIT - The WAIT instruction causes all processor
clocks to stop, but leaves the Timer and SPI clocks running. This "rest" state of the processor can be cleared by
reset, an external interrupt (mo), Timer interrupt, SPI
interrupt, or Port B interrupt. There are no special wait
vectors for these individual interrupts.

2-87

CPU
Interrupt

Vector
Address

RESET
SWI
IRQ
TIMER

$1 FFE-$1 FFF
$1 FFC-$1FFD
$1 FFA-$1 FFB
$1 FF8-$1 FF9

SPI

$1 FF4-$1 FF5

PB

$1 FF2-$1 FF3

Software Interrupt (SWI)
The software interrupt is an executable instruction. The
action of the SWI instruction is similar to the hardware
interrupts. The SWI is executed regardless of the state of
the interrupt mask (I bit) in the condition code register. The
interrupt service routine address is specified by the contents of memory location $1 FFC and $1 FFD.
External Interrupt
Ifthe interrupt mask (I bit) of the condition code register has
been cleared and the external interrupt pin (IRQ) has gone
low, then the external interrupt is recognized. When the
interrupt is recognized, the current state of the CPU is
pushed onto the stack and the I bit is set. This masks further
interrupts until the present one is serviced. The interrupt
service routi ne add ress is specified by the content of memory location $1 FFA and $1 FFB. Either a level-sensitive and
negative edge-sensitive trigger, or a negative edge-sensitive only trigger are available as a mask option. Fig. 11
shows both a functional and mode timing diagram for the
interrupt line. The timing dia9@!!1 shows two different
treatments of the interrupt line (fRO) to the processor. The
first method shows single pulses on the interrupt line

CDP68HC05D2
spaced far enough aPlirt to be serviced. The minimum time
between pulses is a function of the number of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the next pulse should not occur
until the MCU software has exited the routine (an RTI occurs). The second configuration shows several interrupt
lines "wire-ORed" to form the interrupts at the processor.

Thus, if after servicing one interrupt the interrupt line remains low, then the next interrupt is recognized.
Nole: The internal interrupt latcl:! is cleared in the first part of the
service routine, therefore, one (and only one) external interrupt
pulse could be latched during t'LiL and serviced as soon as the I bit is
cleared.

FROM
RESET

CLEARiRQ
REQUEST
LATCH

.J&AD PC FROM
IRQ: $1FFA-$1FFB
TIMER: $1FF8-$1FF9
PB: $1 FF2-$1 FF3
SPI: $1 FF4-$1 FF5

COMPLETE
INTERRUPT
ROUTINE
AND EXECUTE
RTI
NO

92CM-39385

Fig. 9 - Hardware Interrupt Flowchart

2-88

CDP68HC05D2

OSCILLATOR ACTIVE
TIMER, AND $PI
CLOCKS ACTIVE
PROCESSOR CLOCKS STOPPED
CLEAR I BIT

STOP OSCILLATOR
AND ALL CLOCKS
CLEAR I BIT

tn

a:
....

::::l
o

a:

IZ

...
o

...ii~

YES

(1) FETCH RESET VECTOR OR
(2) SERVICE INTERRUPT
a.STACK
b. SET I BIT
c. VECTOR TO INTERRUPT
ROUTINE

(1) FETCH RESET VECTOR OR
(2) SERVICE INTERRUPT
a. STACK
b. SET I BIT
c. VECTOR TO INTERRUPT

ROUTINE

*DELAY IS PROGRAMMABLE AS 4064 OR 2 MACHINE CYCLES.

92CL - 39386

Fig. 10 - STOP/WAIT Flowcharts

Timer Interrupt
There are three different timer interrupt flags that will cause
a timer interrupt whenever they are set and enabled. These
three interrupt flags are found in the three most significant
bits of the timer status register (TSR, location $13) and all
three will vector to the same interrupt service routine
($1 FF8-$1 FF9). The three timer interrupt conditions are
timer overflow, output compare, and input capture.

All interrupt flags have corresponding enable bits (ICIE,
OCIE, and TOlE) in the timer control register (TCR, location $12). Reset clears all enable bits, thus preventing an
interrupt from occurring during the reset period. The actual
processor interrupt is generated only if the I bit in the condition code register is also cleared. When the interrupt is
recognized, the current machine state is pushed onto the
stack and I bit is set. This masks further interrupts until the
present one is serviced. The interrupt service routine address is specified by the contents of memory location $1 FF8

2-89

and $1 FF9. The general sequence for clearing an interrupt
is a software sequence of accessing the status register
while the flag is set, followed by a read or write of an
associated register. Refer to the PROGRAMMABLE TIMER
section for additional information about the timer circuitry.
Serial Peripheral Interface (SPI) Interrupts
An interrupt in the serial peripheral interface (SPI) occurs
when one of the interrupt flag bits in the serial peripheral
status register (Location $OB) is set, provided the I bit in the
condition code register is clear and the enable bit in the
serial peripheral control register (location $OA) is enabled.
When the interrupt is recognized, the current state of the
machine is pushed onto the stack and the I bit in the condition code register is set. This masks further interrupts until
the present one is serviced. The SPI interrupt causes the
program counter to vector to memory location $1 FF4 and
$1 FF5 which contains the starting address of the interrupt

CDP68HC05D2

LEVEL-SENSITIVE
TRIGGER
MASK OPTION

-----

VDDr---""'I

o

EXTERNAL
INTERRUPT
REQUEST

Q~--"'-""

INTERRUPT __~__-a~C
PIN

I BIT (CC)

POWER - ON RESET
EXTERNAL RESET
EXTERNAL INTERRUPT
BEING SERVICED
(READ OF VECTORS)

92CS-39364

(a) Interrupt Function Diagram

Edge-Sensitive Trigger Condition
The minimum pulse width (t,ltH) is
either125 ns (Voo=5 V) or250 ns (Voo
= 3 V). The period t,LtL should not be
less than the n umber of tCYC cycles it
takes to execute the interrupt service
routine plus 21 tCYC cycles.

IRQn

______

NORMALLY
USED WITH
WIRE-O RED
CONNECTION

~r

IRQ --,. _____________________________~r
(MCU)

Level-Sensitive Trigger Condition
If after servicing an interrupt the IRQ
remains low, then the next interrupt is
recognized.

92CS-39365

(b) Interrupt Mode Diagram
Fig. 11 - External Interrupt

service routine. Software in the serial peripheral interrupt
service routine must determine the priority and cause ofthe
SPI interrupt by examining the interrupt flag bits located in
the SPI status register. The general sequence for clearing
an interrupt is a software sequence of accessing the status
register while the flag is set, followed by a read orwrite of an
associated register. Referto SERIAL PERIPHERAL INTERFACE section for a description of the SPI system and its
i nterru pts.

2-90

Port B Interrupt

A Port B interrupt will occur when anyone of the eight port
lines (PBO-PB7) is pulled to a low level, provided the interrupt mask bit of the condition code register is clear and the
enable bit (Bit 1) in the Special Port control register (Memory location $001 E) is enabled. Before enabling Port B interrupts, PBO through PB7 should be programmed as inputs,
i.e., their corresponding DDR bits must be O.

CDP68HC05D2
A Port B interrupt will set the Port B interrupt flag (PBIF)
located in the Special Port Control/Status register (bit 7),
cause the current state of the machine to be pushed onto
the stack, and set the I-bit in the condition code register.
This masks further interrupts until the present one is serviced. The Port B interrupt causes the Program Counter to
vector to memory locations $1 FF2 and $1 FF3 which contain
the starting address of the interrupt service routine. To clear
a Port B interrupt, the user must read the Special Port
Control/Status register followed by a read of Port S.

STOP Instruction
The STOP instruction places the CDP68HC05D2 in its lowest power consumption mode. In the STOP mode the intenal oscillator is turned off, causing all internal processing to
be halted; refer to Fig. 10. During the STOP mode, the I bit in
the condition code register is cleared to enable external
interrupts. All other registers and memory remain unaltered
and all input/output lines remain unchanged. This continues until an external interrupt (rna), port B interrupt,
external timer oscillator interrupt, or reset is sensed, at
which time the internal oscillator is turned on. These interrupts cause the program counter to vector to their respective interrupt vector locations ($1 FFA and $1 FFB, $1 FF2
and $1 FF3, $1 FF8 and $1 FF9, and $1 FFE and $1 FFF, respectively) which contain the starting addresses of the interrupt service routines.

The purpose of this interrupt is to provide easy use of the
PBO-PB7Iines as sensor inputs, such as in keyboard scanning. For systems where the keyboard response is not interrupt driven, this interrupt can be disabled. Programming
any of these lines as outputs inhibits them from generating
an interrupt.
Port B interrupts will cause an exit from the stop mode
provided that the Port B interrupt enable bit is set. Port B
interrupt vector is located at $1 FF2, $1 FF3.

t--t--t--PORT
A

[
4
3
2
1
0

>-

"
,. "
"
" "
>-

)<

)<

'" "
"" >->~

>-

"

WAIT Instruction
The WAIT instruction places the CDP68HC05D2 in a low
power consumption mode, but the WAIT mode consumes
somewhat more power than the STOP mode. In the WAIT
mode, the internal clock remains active, and all CPU processing is stopped; however, the programmable timer and
serial peripheral interface systems remain active. Refer to
Fig. 10. During the WAIT mode, the I bit in the condition
code register is cleared to enable all interrupts. All other
registers and memory remain unaltered and all parallel input/output lines remain unchanged. This continues until
any interrupt or reset is sensed. At this time the program
counter vectors to the memory location ($1 FF2 through
$1 FFF) which contains the starting address of the interrupt
or reset service routine.

+
OPEN DRAIN
] SOFTWARE
PROGRAMMABLE
OUTPUTS

>-

t--I---

t--PORT

d'l

KEYBOARD
INTERRUPT

Data Retention Mode

I---

The contents of RAM and CPU registers are retained at
supply voltages as low as 2 Vdc. This is referred to as the
data retention mode, where the data is held, but the device
is not guaranteed to operate.
92C S-37512RI

Fig. 12 - Keyboard interface.

PROGRAMMABLE TIMER
The programmable timer, which is preceded by a fixed
divide-by-four prescaler, can be used for many purposes,
including input waveform measurements while simultaneously generating an output waveform. Pulse widths can
vary from several microseconds to many seconds. A block
diagram ofthe timer is shown in Fig. 15 and timing diagrams
are shown in Figs. 16 through 19.

The programmable timer capabilities are provided by using
the following ten addressable 8-bit registers (note the high
arid low represent the significance of the byte). A description of each register is provided in the following pages.
Timer Control Register (TCR) location $12,
Timer Status Register (TSR) location $13,
Input Capture High Register location $14,
Input Capture Low Register location $15,
Output Compare High Register location $16,
Output Compare Low Register location $17,
Counter High Register location $18,
Counter Low Register location $19,
Alternate Counter High Register location $1A, and
Alternate Counter Low Register location $1 B.

Because the timer has a 16-bit architecture, each specific
functional segment (capability) is represented by two registers. These registers contain the high and low byte of that
functional segment. Generally, accessing the low byte of a
specific timer function allows full control of that function;
however, an access of the high byte inhibits that specific
timer function until the low byte is also accessed.
Note: The I bit in the condition code register should be set while
manipulating both the high and low byte register of a specific timer
function to ensure that an interrupt does not occur. This prevents
interrupts from occurring between the time that the high and low
bytes are accessed.

External Timer Oscillator
In addition to clocking the CDP68HC05D2's internal 16c bit
timer with the CPU clock, a separate oscillator circuit may

2-91

c:n

a:

~
.....
CI

a:
~
:z

CI
<.)

...:i

CI

a:

CDP68HC05D2
be used by connecting an RC or crystal circuit to pins 29
and 30 (TOSCl and TOSC2). The circuits shown in Figs.
13(b) and 13(c) are recommended when using a crystal.
Th is osci lIator is desig ned to interface with an AT-cut parallel resonant quartz crystal resonator in the frequency range
specified for f.os o in the Control Timing Tables at the end of
this specification. See Fig. 13(a) for the RC circuit.
When not using the external timer oscillator feature these
pins function as input lines. However, once the external
timer oscillator has been enabled, PDl will become an output only line until the processor is reset.
The EOE (External Oscillator Enable bit 4) and ECC (External Clock Connect bit 3) bits in the Timer Control Register
control the external timer oscillator. If bit 3 (ECC) in the
timer control register is set, the internal clock input to the
timer is disabled and the clock to the timer is connected to
the external timer oscillator. This clock can be either a
crystal or RC oscillator. Since this mode of operation permits the timer to continue running when the CPU is in the
stop mode, timer interrupts, if enabled, will still occur and
can be used to exit from the stop mode. Fig. 14 shows the
timer oscillator controls. The frequency of the external oscillator must be less than one-quarter the CPU oscillator
frequency.

The procedures for using this circuit are:
• Crystal Oscillator Operation - First set the EOE bit to
start the crystal oscillating. When oscillation has stabilized, the ECC bit can be set to begin clocking the timer
with the external timer oscillator. This time delay may
vary depending upon crystal frequency and manufacturer.
• RC Oscillator Operation - When it is desired to clock the
timer from an RC timer oscillator, set both the EOE and
the ECC bits at the same time in order to keep power
consumption minimal.
• No external timer oscillator being used -If the EOE bit is
never set, the oscillator will remain in its high impedance
state allowing its pins to be used as PDO and PDl input
lines. In this case, these pins function as normal inputs
and should not be left floating.
• Timer Oscillator used for event counting - Set both the
EOE and ECC bits and drive the timer oscillator input pin
with the event signal which is to be counted. If EOE
remains reset and only ECC is set, the event signal can be
connected to the timer oscillator output pin, and the input
can be used as a Port D input line.

Fig. 13 - External Timer Oscillator Connections
(a) RC Oscillator Connections

CDP68HC05D2
TOSC2

TOSCI
29

fO

.A~
v
CDP68HC05D2

i

TOSC2

TOSCI
29

CDP68HC05D2
C
TOSCI
29

30
Rt

TOSC2
30
Rt

COUT
39pf

10Mn

I

CIN
.5

PF

0

COUT
1120 PF

92CS-39464

(b) Crystal Oscillator connections for crystal speeds above
approx. 400 KHz. The C;n and Cout values may vary depending upon crystal manufacturer.

I--

(c) Crystal Oscillator connections for crystal speeds below
approx. 400 KHz. The C;n, C. and R, values shown work well
for most 32.768 KHz crystals; however, sizes may vary depending upon crystal frequency and manufacturer.

--------,

I
I
I

I

I ~~E::A\LLE

'N~~NAL

EXTERNAL CLOCK:
CONNECT

I

I

I

I

I
92CS-39368

TO TIMER
INPUT

Fig. 14 - External Timer Oscillator Controls

2-92

CDP68HC05D2

\

(

CDP68HC05D2 INTERNAL BUS

,..--- .....

(
I

CPU

I CLOCK

I

\

EXT. I
TIMER
CLOCK I
0
ECC BIT I

OUTPUT
COMPARE
REGISTER

$17

8-BIT
BUFFER

I

I

74
$16

I

--1-- ./

LOW
BYTE

HIGH
BYTE

\

/

HIGH
BYTE

OUTPUT
COMPARE
CIRCUIT

LOW
BYTE

16-BIT FREE
RUNNING
COUNTER

$18

COUNTER
ALTERNATE
REGISTER

$1A

LOW
BYTE

HIGH
BYTE

$14

INPUT
CAPTURE
REGISTER

$19

$15

$1B

OVERFLOW
DETECT
CIRCUIT

EDGE
DETECT
CIRCUIT

I
I
TIMER
STATUS
REG.

ICF

OCF

~ ,13
ICIE IOCIE

I

Q

D

TOlE

I

IEDG

I I
OLVL

OUTPUT
LEVEL
REG.

TIMER
CONTROL
REG.
$12

-

CLK

C

~

I

I

INTERRUPT
CIRCUIT

92CM-39388

1

Fig. 15 - Programmable Timer Block Diagram

2-93

OUTPUT
LEVEL
{TCMP
PIN 35)

ED GE
IN PUT
(T CAP
PIN 37)

CDP68HC05D2
INTERNAL~

PROCESSOR
CLOCK

I

:

TOl

1
: I lin
111111
n,_~:. :. .: -+-1_~n

I 1 I

J1JlITl.Il
I

INTERNAL
TIMER
CLOCKS

I

I

I
-t-

1

iiESEi

I EXTERNAL
OR END OF POR)

I

X

$FFFC

'------

n

n

1

I

COUNTER
116-BIn

'--------'

--'n~~------'n. . ---~nL--I

I
I

n.......- - - - n

I I I I

I

Tlo _ _ _-'--_ _
Til

_

I

"~,--:I;-I-I-L-_+-+-

I

TOO

I

I

~ _________________

I

(INTERNAL
RES"n)

I

X

$FFFO

rL
X4

+FFFE

FFFF

111/11

NOTE:
THE COUNTER REGISTER .ND TIMER CONTROL REGISTER ARE THE ONLY ONES
AFFECTED BY

'2CM-39380

mrr.

Fig. 16 - Timer State Timing Diagram For Reset

INTERNAL
PROCESSOR
CLOCK

n

TOO

-----~

INTERNAL

cll~~~s

n

T01.Jl__________InL.____--'n
TIO

~_ _ _ _ _ _ ___'n~

n

Til _ - - - - '
COUNTER
116-BIT)

-;;;;;;;\.j

n

L -_ _----!

.I.

X\,.-+i-------'
l
*FFED

X

n

r

n
rL

4

FFEE

X

$FFEF

~:

ISEE

""~X,'-------

INPUT
CAPTURE __________~???? _________ _ J
REGISTER
T~·_·_·_·

INPUT
CAPTURE
FLAG

n

n

______I

~,-_ _ _'i'_FF_EC_ _--J

INPUT
EDGE

INTERNAL
CAPTURE
LATCH

n

~----------~

~--------------------------------

~

$ FFED

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

~---------------------------/
•
NOTE:
IF THE INPUT EDGE OCCURS IN THE SHADED AREA FROM ONE TIMER STATE Tl0 TO THE
OTHER TIMER STATE T10, THE INPUT CAPTURE FLAG IS SET DURING THE NEXT STATE
T11.

Fig. 17 - Timer State Timing Diagram For Input Capture

2-94

92CM-39381

CDP68HC05D2
INTERNAL
PROCESSOR
CLOCK

________

TOO

INTERNAL
TIMER
CLOCKS

n

~

L ________

n

TO'Jl

"~----~

n

~

L ________

n

~----~

n

n

r

~

n

~----~

n

n

TIO

-----1n 1.........____--' '--____---' '--____---'

Til

__---In

COUNTER
(16- BITI

n~

~

X

$FFEC

~

__~n
rL
x'-__----'X
$FFEE

$FFED

J

$FFEF

(NOTEII-,.
COMPARE
REGISTER

CPU WRITES $FFED

COMPARE
REGISTER
LATCH

INOTE

r --------:---------$FFED

21----y;jf

OUTPUT COMPARE
FLAG tOCFI AND
TCM P (PI N 351

(NOTE

\

31-y

NOTES:
1. THE CPU WRITE TO THE COMPARE REGISTER MAY TAKE PLACE AT ANY TIME, BUT A
COMPARE ONLY OCCURS AT TIMER STATE T01. THUS, A 4-CYCLE DIFFERENCE MAY
EXIST BETWEEN THE WRITE TO THE COMPARE REGISTER AND THE ACTUAL COMPARE.
2. INTERNAL COMPARE TAKES PLACE DURING TIMER STATE T01.
3. OCF IS SET AT THE TIMER STATE T11 WHICH FOLLOWS THE COMPARISON MATCH
($FFED IN THIS EXAMPLE).

92CM-39378

Fig, 18 - Timer State Timing Diagram For Output Compare

INTERNAl,
PROCESSOR
CLOCK

n

TOO

INTERNAL
TIMER
CLOCKS

TO'Jl

TIO~

n

Til

COUNTERB
FFFE
116-BITI

4

TIMER
OVERFLOW
FLAGITOFI

$FFFF

n

n
n

n

X

$0000

n

n
n

n

X

40001

n

r

n
rL

X

$0002

/

NOTE:
THE TOF BIT IS SET AT TIMER STATE T11 (TRANSITION OF COUNTER FROM $FFFF TO
$00001. IT IS CLEARED BY A READ OF THE TIMER STATUS REGISTER DURING THE
INTERNAL PROCESSOR CLOCK HIGH TIME FOLLOWED BY A READ OFTHE COUNTER LOW
REGISTER.

Fig, 19 - Timer State Diagram For Timer Overflow

2-95

92CM-39379

CDP68HC05D2
Counter
The key element in the programmable timer is a 16-bit
free-running counter, or counter register, preceded by a
prescaler which divides the internal processor clock by
four. The prescaler gives the timer a resolution of 2.0 microseconds if the internal processor clock is 2.0 MHz. The
counter is clocked to increasing values during the low portion of the internal processor clock. Software can read the
counter at any time without affecting its value.
The double-byte free-running counter can be read from
either of two locations $18-$19 (called counter register at
this location), or $1A-$1 B (counter alternate register at this
location). A read sequence containing only a read of the
least significant byte of the free-running counter ($19, $1 B)
will receive the count value at the time ofthe read. If a read
of the free-running counter or counter alternate register
first addresses the most significant byte ($18, $1A) it causes
the least significant byte ($19, $1 B) to be transferred to a
buffer. This buffer value remains fixed after the first most
significant byte "read" even if the user reads the most significant byte several times. This buffer is accessed when reading the free-running counter or counter alternate register
least significant byte ($19 or $1B), and thus completes a
read sequence of the total counter value. Note that in reading either the free-running counter or counter alternate
register, If the most significant byte is read, the leastsignificant byte must also be read in order to complete the sequence.
The free-running counter is configured to $FFFC during
reset and is always a read-only register. During a power-onreset (POR), the counter is also configured to $FFFC and
begins running after the oscillator startup delay. Because
the free-running counter is 16 bits preceded by a fixed
divide-by-four prescaler, the value in the free-running
counter repeats every 262,144 MPU internal processor
clock cycles. When the counter rolls over from $FFFF to
$0000, the timer overflow flag (TOF) bit is set. An interrupt
can also be enabled when counter rollover occurs by setting its interrupt enable bit (TOlE).

Output Compare Register
The output compare register is a 16-bit register, which is
made up of two 8-bit registers at locations $16 (most significant byte) and $17 (least significant byte). The output compare register can be used for several purposes, such as,
controlling an output waveform or indicating when a period
of time has elapsed. The output compare register is unique
in that all bits are readable and writeable and are not altered
by the timer hardware. Reset does not affect the contents of
this register and if the compare function is not utilized, the
two bytes of the output compare register can be used as
storage locations.
The contents of the output compare register are compared
with the contents of the free-running counter once during
every four internal processor clocks. If a match is found, the
corresponding output compare flag (OCF) bit is set and the
corresponding output level (OLVL) bit is clocked (by the
output compare circuit pulse) to an output level register.
The values in the output compare register and the output
level bit should be changed after each successful comparison in order to control an output waveform or establish a
new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit, OCIE, is set.
After a processor write cycle to the output compare register
containing the most significant byte ($16), the output com-

pare function is inhibited until the least significant byte
($17) is also written. The user m.ust write both bytes (locations) if the most Significant byte is written first. A write
made only to the least significant byte ($17) will not inhibit
the compare function. The free-running counter is updated
every four internal processor clock cycles due to the internal prescaler. The minimum time required to update the
output compare register is a function of the software program rather than the internal program.
A processor write may be made to either byte of the output
compare register without affecting the other byte. The output level (OLVL) bit is clocked to the output level register
regardless of whether the output compare flag (OCF) is set
or clear.
Because neither the output compare flag (OCF bit) nor
output compare register is affected by reset, care must be
exercised when initializing the output compare function
with software. The following procedure is recommended:
(1) Write the high byte of the output compare register to
inhibit further compares until the low byte is written.
(2) Read the timer status register to arm the OCF if it is
already set.
(3) Write the output compare register low byte to enable
the output compare function with the flag clear.
The advantage of this procedure is to prevent the OCF bit
from being set between the time it is read and the write to
the output compare register. A software example is shown
below.
B7 16 STA OCMPHI
B6 13 LOA TSTAT
BF 17 STX OCMPLD

INHIBIT OUTPUT COMPARE
ARM OCF BIT IF SET
READY FOR NEXT COMPARE

Input Capture Register
The two 8-bit registers which make up the 16-bit input
capture register are read-only and are used to latch the
value of the free-running counter after a defined transition
is sensed by the corresponding input capture edge detector. The level transition which triggers the counter transfer
is defined by the corresponding input edge bit (lEDG).
Reset does not affect the contents of the input capture
register.
The result obtained by an input capture will be one more
than the value of the free-running counter on the rising
edge of the internal processor clock preceding the external
transition (refer to timing diagram shown in Fig. 17). This
delay is required for external synchronization. Resolution is
affected by the prescaler allowing the timer to only increment every four internal processor clock cycles.
The free-running counter contents are transferred to the
input capture register on each proper signal transition regardless of whether the input capture flag (ICF) is set or
clear. The input capture register always contains the freerunning counter value which corresponds to the most recent input capture.
After a read ofthe most significant byte of the input capture
register ($14), counter transfer is inhibited until the least
significant byte ($15) of the input capture register is also
read. This characteristic forces the minimum pulse period
attainable to be determined by the time used in the capture
software routine and its interaction with the main program.
A polling routine using instructions such as BRSET, BRA,
LOA, STA, INCX, CMPX, and BEG might take 34 machine
cycles to complete. The free-running counter increments

2-96

CDP68HC05D2
every four internal processor clock cycles due to the prescaler. A read of the least significant byte ($15) of the input
capture register does not inhibit the free-running counter
transfer. Again, minimum pulse periods are ones which
allow software to read the least significant byte ($15) and
perform the needed operations. There is no conflict between the read of the input capture register and the freerunning counter since they occur on opposite edges of the
internal processor clock.

Timer Control Register (TCR)
The timer control register (TCR, location $12) is an 8-bit
read/write register which contains seven control bits. Three
of these bits control interrupts associated with each of the
three flag bits found in the timer status register (discussed
below). The other four bits control: 1) which edge issignificant to the input capture edge detector (i.e., negative or
positive), 2) the next value to be clocked to the output level
register in response to a successful output compare, 3) the
source of the timer clock, and 4) whether the external timer
oscillator is enabled. The timer control register and the
free-running counter are the only sections of the timer affected by reset. The TCMP pin is forced low during external
reset and stays low until a valid compare changes it to a
high. The timer control register is illustrated below followed
by a definition of each bit.

BO,OLVL The value of the output level (OLVL) bit is
clocked into the output level register by the next
successful output compare and will appear at
pin 35. This bit and the output level register are
cleared by reset.
o= low output
1 = high output

Timer Status Register (TSR)
The timer status register (TSR) is an 8-bit register of which
the three most significant bits contain read-only status information. These three bits indicate the following:
1. A proper transition has taken place at pin 37 with an
accompanying transfer of the free-running counter contents to the intput capture register,
2. A match has been found between the free-running counter and the output compare register, and
3. A free-running counter transition from $FFFF to $0000
has been sensed (timer overflow)
The timer status register is illustrated below followed by a
definition of each bit. Refer to timing diagrams shown in
Fig. 16, 17, and 18 fortiming relationship to the timer status
register bits.

7
7

6

5

4

3

2

o

If the input capture interrupt enable (lCIE) bit is
set, a timer interrupt is enabled when the ICF
status flag (in the timer status register) is set. If
the ICIE bit is clear, the interrupt is inhibited.
The ICIE bit is cleared by reset.

86,OCIE

If the output compare interrupt enable (OCIE)
bit is set, a timer interrupt is enabled whenever
the OCF status flag is set. If the OCIE bit is clear,
the interrupt is inhibited. The OCIE bit is cleared
by reset.

85, TOlE

If the timer overflow interrupt enable (TOlE) bit
is set, a timer interrupt is enabled whenever the
TOF status flag (in the timer status register) is
set. If the TOlE bit is clear, the interrupt is inhibited. The TOlE bit is cleared by reset.

83, ECC

5

4

3

2

o

LI_C_F~I_o_C_F~I_T_O_F~I~0~__o~_0__~0__L-~$13

87, ICIE

84, EOE

6

External Oscillator Enable - If set, the external
timer oscillator is enabled. If it is then cleared,
the inverter between pins 29 and 30 is prevented
from switching and cannot be used in a crystal
or RC oscillator. This bit is cleared by reset
which configures both TOSC1 and TOSC2 as
inputs.
If the external clock connect (ECG) is set, the
internal clock input to the timer is disabled and
the timer oscillator is connected to the input to
the timer. It is cleared by reset. Accuracy of the
timer count is not guaranteed while this bit is
switched.

81, IEDG The value of the input edge (IEDG) bit determines which level transition on pin 37 will
trigger a free-running counter transfer to the
input capture register. Reset clears the IEDG
bit.
o = negative edge
1 = positive edge
2-97

B7,ICF

The input capture flag (ICF) is set when a proper
edge has been sensed by the input capture edge
detector. It is cleared by a processor read of the
timer status register (with ICF set) followed by
reading the low byte ($15) of the input capture
register. Reset does not affect the input compare flag.

B6, OCF

The output compare flag (OCF) is set when the
output compare register contents matches the
contents of the free-running counter. The OCF
is cleared by reading the timer status register
(with the OCF set) and then writing to the low
byte ($17) of the output compare register. Reset
does not affect the output compare flag.

B5, TOF

The timer overflow flag (TO F) bit is set by a
transition of the free-running counter from
$FFFF to $0000. It is cleared by reading the
timer status register (with TOF set) followed by
a read of the free-running counter least significant byte ($19). Reset does not affect the TOF
bit.

Reading the timer status register satisfies the firstcondition
required to clear any status bits which happened to be set
during the access. The only remaining step is to provide an
access of the register which is associated with the status bit.
Typically, this presents no problem for the input capture
and output compare functions.
A problem can occur when using the timer overflow function and reading the free-running counter at random times
to measure an elapsed time. Without incorporating the
proper precautions into software, the timer overflow flag
could unintentionally be cleared if: 1) the timer status register is read when TOF is set, and 2) the least Significant byte
of the free-running counter is read but not for the purpose
of servicing the flag. The counter alternate register at
address $1 A and $1 B contains the same value as the freerunning counter (at address $18 and $19); therefore, this

CDP68HC05D2
alternate register can be read at any time without affecting
the timer overflow flag in the timer status register.
During STOP and WAIT instructions, the programmable
timer functions as follows if using the CPU clock: during the
wait mode, the timer continues to operate normally and may
generate an interrupt to trigger the CPU out of the wait

state; during the stop mode, the timer holds at its current
state, retaining all data, and resumes operation from this
point when an external interrupt is received. If usfng an
external timer oscillator the timer will continue to count and
generate interrupts.

Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is a four wire synchronous serial communication system with separate
wires for input data, output data, clock and slave select. A
master MCU, which produces the clocking Signal, initiates
the exchange of data bytes with a slave MCU or peripheral
device such as an LCD display driver or an A/D converter.
A diagram of the control, status, and data registers may be
found in the section labelled "Registers". The SPI system
registers are found at addresses $OOOA-$OOOC. The SPI
output drivers may be switched off to allow the user access to external pins for use as parallel inputs to Port D.
Upon power-up or reset the SPI output drivers will be
initialized in the off state. The serial system enable bit
which controls the output drivers and other functional
inhibits is the SPE bit found in the serial control register.
Fig. 20 illustrates two different system configurations. Fig.
20a represents a system of five different MCUs in which
there are one master and four slaves (0, 1,2,3). In this
system four basic lines (signals) are required forthe MOSI
(master out, slave in), MISO (master in, slave out), SCK
(serial clock), and SS (slave select) lines. Fig. 20b represents a system of three MCUs in which each MCU is
capable of being a master or a slave. The SPI interface is
well-suited for multiprocessor communications.

Features
•
•
•
•
•
•
•
•
•

Full duplex, three-wire synchronous transfers
Master or slave operation
1.05 MHz (maximum) master bit frequency
2.1 MHz (maximum) slave bit frequency
Four programmable master bit rates
Programmable clock polarity and phase
End of transmission interrupt flag
Write collision flag protection
Master-Master mode fault protection capability

When the master device transmits data to a second (slave)
device via the MOSlline, the slave device responds by sending data to the master device via the MISO line. This implies
full duplex transmission with both data out and data in synchronized with the same clock Signal (one which Is provided
by the master device). Thus, the byte transmitted Is replaced
by the byte received and eliminates the need for separate
transmit-empty and receiver-full status bits. A single status
bit (SPIF) is used to signify that the I/O operation is complete.
Configuration of the MOSI pin is a function of the MSTR
bit in the serial peripheral control register (SPCR, loction
$OA). Setting the MSTR bit will place the device in the
Master mode and cause the MOSI pin to be an output.
Note: The Port 0 Data Direction Register bit 3 must be set for the
MOSI pin to transfer data in the Master mode.

Master In Slave Out (MISO)
The MISO pin is configured asan input in a master (mode)
device and as an output in a slave (mode) device. In this
manner data is transferred serially from a'slave to a master
on this line; most significant bit first, least significant bit
last. The MISO pin of a slave device is placed in the highimpedance state if it is not selected by the master; I.e., its
SS pin is a logic one. The timing diagram of Fig. 21 shows
the relationship between data and clock (SCK). As shown
in Fig. 21" four possible timing relationships may be
chosen by using control bits CPOL and CPHA. The master
device always allows data to be applied on the MOSIline a
half-cycle before the clock edge (SCK) in order for the
slave device to latch the data.
Note: The slave device (s) and a master device must be programmed to similar timing modes for proper data transfer.

Signal Description
The four basic signals (MOSI, MISO, SCK, and ~) discussed above are described in the following paragraphs.
Each signal function is described for both the master and
slave mode.

Master Out Slave In (MOSI)
The MOSI pin is configured as a data output in a master
(mode) device and asadata input in a slave (mode) device.
In this manner data is transferred serially from a master to
a slave on this line; most significant bit first, least significant bit last. The timing diagrams of Fig. 21 summarizethe
SPI timing diagram and show the relationship between
data and clock (SCK). As shown in Fig. 21 four possible
timing relationships may be chosen by using control bits
CPOL and CPHA. The master device always allows data to
be applied on the MOSI line a half-cycle before the clock
edge (SCK) in order for the slave device to latch the data.
Note: Both the slave device(s) and a master device must be programmed to similar timing modes for proper data transfer.

2-98

When the master device transmits data to a slave device
via the MOSI line, the slave device responds by sending
data to the master device via the MISO line. This implies
full duplex transmission with both data out and data in
synchronized with the same clock signal (one which is
provided by the master device). Thus, the byte transmitted
is replaced by the byte received and eliminates the need
for separate transmit-empty and receiver-full status bits. A
single status bit (SPIF) in the serial peripheral status register (SPSR, location $08) is used to signify that the I/O
operation is complete.
In the master device, the MSTR control bit in the serial
peripheral control register (SPCR, location $OA) is set to a
logic one (by the program) to allow the master device to
receive data on its MISO pin. In the slave device. its MISO
pin is enabled by the logic level of the SS pin; I.e., if SS=1
then the MISO pin is placed in the high-impedance state,
whereas, if 85=0 the MISO pin is an output for the slave
device.
Note: The Port 0 Data Direction Register bit 2 must be set for the
MISO pin to transfer data in the slave mode.

CDP68HC05D2
CD68HCOSD2 SLAVE 0
MISO

SC~I

MISO
MOSI SS

MOSI
SCK

58 - V D D
CD68HCOS'02MASTER

-

0

p

0

1

R
T

2
3 f--

I

I

II

MOSI

MOSI SS
MISO SCK

II MOSI SS
MISO SCK

CD68HC05D2 SLAVE 3

CD68HCOSD2 SLAVE 2

MISO

SS

SCK

CD68HCOSD2 SLAVE 1
92CM- 39384

(a) Single Master, Four Slaves

.
~

>

++

??
><

;> > >
MASTER
No.1
MISO
MOSI
SCK
SS

MASTER
No.2

MASTER
No.3

MISO

MISO

MOSI

---4

CDP6805D2

--4

SCK
SS

MOSI
SCK f - - SS r--

~

-

CDP6805D2

CDP6805D2

(b) Multimaster System
Fig. 20 - Master-Slave System Configuration

2-99

92CS-37494

CDP68HC05D2

ss

l

L -__________________________________________________________________

-J~

SCK
ICPOl-O, CPHA= 0)

S CK
I CPO l - 0, CPH A - I)

SCK
ICPOl-I,CPHA-O

SCK
ICPOl- I,CPHA-I)
M ISO/
MOSI

w:a

MSB

6

5

3

4

2

lSB

INTERNAL STROBE FOR OATA CAPTURE IAll MODES)
92CM-39316

Fig. 21 - Data Clock Timing Diagram

Slave Select (SS)
In the slave mode the slave select (SS) pin is an input (PD5.
pin 34), which receives an active low signal that is generated
by the master device to enable slave device(s) to accept
da.ta. To ensure that data will be accepted by a slave device,
the SS signal line must be a logic low prior to occurrence of
SCK (system clock) and must remain low until after the last
(eighth) SCK cycle. Fig. 21 illustrates the relationship between SCK and the data for two different level combinations
of CPHA, when SS is pulled low. These are: 1) with CPHA=1
of 0, the first bit of data is applied to the MISO line for
transfer. and 2) when CPHA = 0 the slave device is prevented from writing to its data register. Refer to the WCOl status
flag in the serial peripheral status register (location $08)
description for further information on the effects that the SS
input and CPHA control bit have on the I/O data register. A
high level SS signal forces the MISO (master in, slave out)
line to the high-impedance state. Also, SCK and the MOSI
(master out, slave in) line are ignored by a slave device
when its SS signal is high.
When a device is a master, it monitors its SS signal for a
logic low, provided that Port 0 bit 5 is cleared. See Note.
The master device will become a slave device any time its
SS signal is detected low. This ensures that there is only one
master controlling the SS line for a particular system. When
the SS line is detected low, it clears the MSTR control bit
(serial peripheral control register, location $OA). Also, control bit SPE in the serial peripheral control register is
cleared which causes the serial peripheral interface (SPI) to
be disabled (port 0 SPI pins become inputs). The MODF

flag bit in the serial peripheral status register (location $08)
is also set to indicate to the master device that another
device is attempting to become a master. Two devices attempting to be outputs are normally the result of a software
error; however, a system could be configured which would
contain a default master which would automatically "take
over" and restart the system.
Note: In the master mode Port D DDR bit 5 determines whether Port
D bit 5 (SS) is an error detect input to the SPI (DDR bit 5 clear) or a
general-pu.r:2.0se output line (DDR bit 5 set), that can be used to
strobe the SS lines of slaves.

Serial Clock (SCK)
The serial clock is used to synchronize the movement of
data both in and out of the device through its MOSI and
MISO pins. The master and slave devices are capable of
exchanging a data byte of information during asequence of
eight clock pulses. Since the SCK is generated by the master device, the SCK line becomes an input on all slave
devices and synchronizes slave data transfer. The type of
clock and its relationship to data are controlled by the
CPOl and CPHA bits in the serial peripheral control register (location $OA) discussed below. Refer to Fig. 21 for
timing.
The master device generates the SCK through a circuit
driven by the internal processor clock. Two bits (SPRO and
SPR1) in the serial peripheral control register (location
$OA) of the master device select the clock rate. The master
device uses the SCK to latch incoming slave device data on

2-100

CDP68HC05D2
the MISO line and shifts out data to the slave on the MOSI
line. Both master and slave devices must be operated in the
same timing mode as controlled by the CPOL and CPHA bit
in the serial peripheral control register. In the slave device,
SPRO and SPR1 have no effect on the operation of the Serial
Peripheral Interface. Timing is shown in Fig. 21.
Note: The Port D Data Direction Register bit 4 must be set for the
SCK pin to generate (output) a SCK signal.

Functional Description
A block diagram of the serial peripheral interface (SPI) is
shown in Fig. 22. In a master configuration the master start
logic receives an input from the CPU (in the form of a write
to the SPI rate generator) and originates the system clock
(SCK) based on the internal processor clock. This clock is
also used internally to control the state controller as well as
the 8-bit shift register. As a master device, data is parallel
loaded into the 8-bit shift register (from the internal bus)
during a write cycle and then shifted out serially to the
MOSI pin for application to the slave device(s). During a
read cycle, data is applied serially from a slave device via the
MISO pin to the 8-bit shift register. After the 8-bit shift

register is loaded, its data is parallel transferred to the read
buffer and then is made available to the internal data bus
during a CPU read cycle.
In a slave configuration, the slave start logic receives a logic
low (from a master device) at the SS pin and a system clock
input (from the same master device) at the SCK pin. Thus,
the slave is synchronized with the master. Data from the
master is received serially at the slave MOSI pin and loads
the 8-bit shift register. After the a-bit shift register is loaded,
its data is parallel transferred to the read buffer and then is
made available to the internal data bus during a CPU read
cycle. During a write cycle, data is parallel loaded into the
8-bit shift register from the internal data bus and then shifted out serially to the MISO pin for application to the master
device.
Fig. 23 illustrates the MOSI, MISO, and SCK master-slave
interconnections. Note that in Fig. 23 the master 55 pin is
tied to a logic high and the slave ~ pin is a logic low. Fig.
21 a provides a larger system connection for these same
pins. Note that in Fig. 20(a), all 55 pins are connected to a
port pin of a master/slave device. In this case any of the
devices can be a slave.

CI)

a:
......o
LU

SEe NOTE

a:
z
o
<.:I
o
a:

IINTERNAL

PROCESSOR
CLOCK

33

<.:I

:i

~f--t~--~~

INTERNAL

DATA
BUS

SPCR
SOA

NOTES:
THE 5$, SCK, MOSI, AND MISO ARE EXTERNAL PINS WHICH PROVIDE THE
FOLLOWING FUNCTIONS;
(a) MOSI-PROVIDES SERIAL OUTPUT TO SLAVE UNIT(S) WHEN DEVICE IS
CONFIGURED AS A MASTER. RECEIVES SERIAL INPUT FROM MASTER
UNIT WHEN DEVICE IS CONFIGURED AS A SLAVE UNIT.
(b) MISO-RECEIVES SERIAL INPUT FROM SLAVE UNIT(S) WHEN DEVICE IS
CONFIGURED AS A MASTER. PROVIDES SERIAL OUTPUT TO MASTER
WHEN DEViCe IS CONFIGURED AS A SLAVE UNIT.
(c) SCK -PROVIDES SYSTEM CLOCK WHEN DEVICE IS CONFIGURED AS A
MASTER UNIT. RECEIVES SYSTEM CLOCK WHEN DEVICE IS CONFIGURED AS A SLAVE UNIT.
(d) Ss -PROVIDES A LOGIC LOW TO SELECT A SLAVE DeVICE FOR A
TRANSFER W!TH A MASTER DEVICE.

92C~-39390

Fig. 22 - Serial Peripheral Interface Block Diagram
2-101

CDP68HC05D2

MASTER

rl

8-BIT SHIFT REGISTER

I

I

MISO

MISol

I

I

I

I

I
I
I

I

SLAVE
--8-BIT SHIFT REGISTER

r---

I
MOSI

MOSI

I
I

I
I

I
SCK

ISCK

SPI
CLOCK GENERATOR

ISS

+
,5V

I
I

n

OV~

92CS-39389

Fig. 23 - Serial Peripheral Interface Master-Slave Interconnection

Registers

B4, MSTR

The master bit determines whether the device
is a master or a slave. If the MSTR bit is a logic
zero it indicates a slave device and a logic one
denotes a master device. If the master mode is
selected, the function of the SCK pin changes
from an input to an output and the function of
the MISO and MOSI pins are reversed. This
allows the user to wire device pins MISO to
MISO, and MOSI to MOSI and SCK to SCK
without incident. The MSTR bit is cleared by
reset; therefore, the device is always placed in
the slave mode during reset.

B3, CPOL

The clock polarity bit controls the normal or
steady state value of the clock when data is not
being transferred. The CPOL bit affects both
the master and slave modes. It must be used in
conjunction with the clock phase control bit
(CPHA) to produce the wanted clock-data relationship between a master and a slave device. When the CPOL bit is a logic zero, it
produces a steady state low value at the SCK
pin of the master device. If the CPOL bit is a
logic one, a high value is produced at the SCK
pin ofthe master device when data is not being
transferred. The CPOL bit is not affected by
reset. Refer to Fig. 21.

B2, CPHA

The clock phase bit controls the relationship
between the data on the MISO and MOSI pins
and the clock produced or received at the SCK
pin. This control has effect in both the master
and slave modes. It must be used in conjunction with the clock polarity control bit (CPOL)
to produce the wanted clock-data relation.
TheCPHA bit in general selects the clock edge
which captures data and allows it to change
states. It has its greatest impact on the first bit
transmitted (MSB) in that it does or does not
allow a clock transition before the first data
capture edge. The CPHA bit is not affected by
reset. Refer to Fig. 21.

B1, SPR1
BO, SPRO

These two serial peripheral rate bits select one
of four baud rates to be used as SCK if the
device is a master; however, they have no effect in the slave mode. The slave device is

There are three registers in the serial parallel interface
which provide control, status, and data storage functions.
These registers, which include the serial peripheral control
register (SPCR,location $OA), serial peripheral status register (SPSR, location $OB), and serial peripheral data 110
register (SPDR, location $OC) are described below.
Nole: In addition, the Port D Data Direction Register (DDR) must be
properly configured. See note in the section labelled "Input/Output
Programming-Special-Purpose Port".

Serial Peripheral Control Register (SPCR)
76543210
ISPIEI SPE IDWOMI MSTR ICPOL ICPHAISPR11SPROI $OA
The serial peripheral control register bits are defined as
follows:
B7, SPIE

When the serial peripheral interrupt enable bit
is high, it allows the occurrence of a processor
interrupt, and forces the proper vector to be
loaded into the program counter if the serial
peripheral status register flag bit (SPIF and/or
MODF) is set to a logic one. It does not inhibit
the setting of a status bit. The SPIE bit is
cleared by reset.

B6, SPE

When the serial peripheral output enable control bit is set, all output drive is applied to the
external pins and the system is enabled. When
the SPE bit is set, it enables the SPI system by
connecting ilto the external pins thus allowing
it to interface with the external SPI bus. The
pins that are defined as output depend on
which mode (master or slave) the device is in.
Because the SPE bit is cleared by reset, the
SPI system is not connected to the external
pins upon reset.

B5, DWOM The Port D Wire-OR Mode bit controls the
output buffers for Port D bits 2 through 5. If
DWOM=1, the four Port D output buffers behave as open-drain outputs. If DWOM=O, the
four Port D output buffers operate as normal
CMOS outputs. DWOM is cleared by reset.

2-102

CDP68HC05D2
capable of shifting data in and out at a maximum rate which is equal to the CPU clock
(maximum = 2.1 MHz). A rate table is given
below for the generation of the SCK from the
master. The SPR1 and SPRO bits are not affected by reset.

SPR1

SPRO

Internal Processor
Clock Divide By

0
0
1
1

0
1
0
1

2
4
16
32

Serial Peripheral Status Register (SPSR)
7

6

5

4

3

2

o

LIS_P_IF~lw_c_O_L~I__~IM_O_D_F~I__~__L - - L_ _~I$OB
The status flags which generate a serial peripheral interface
(SPI) interrupt will not be blocked by the SPIE control bit in
the serial peripheral control register; however, the interrupt
will be blocked. The WCOL bit does not cause an interrupt.
The serial peripheral status register bits are defined as
follows:
B7, SPIF

The serial peripheral data transfer flag bit notifies the user that a data transfer between the
device and an external device has been completed. With the completion of the data
transfer, SPIF is set, and if SPIE is set, a serial
peripheral interrupt (SPI) is generated. During
the clock cycle that SPIF is being set, a copy of
the received data byte in the shift register is
moved to a buffer. When the data register is
read, it is the buffer that is read. During an
overrun condition, when the master device has
sent several bytes of data and the slave device
has not responded to the first SPIF, only the
first byte sent is contained in the receiver
buffer and all other bytes are lost.
The transfer of data is initiated by the master
device writing its serial peripheral data
register.
Clearing the SPIF bit is accomplished by a
software sequence of accessing the serial peripheral status register while SPIF is set and
followed by a write to or a read of the serial
peripheral data register. While SPIF is set, all
writes to the serial peripheral data register are
inhibited until the proper clearing sequence is
followed. This occurs in the master device. In
the slave device, SPIF can be cleared (using a
similar sequence) during a second transmission; however, it must be cleared before· the
second SPIF in order to prevent an overrun
condition. The SPIF bit is cleared by reset.

B6, WCOL

The function of the write collision status bit is
to notify the user that an attempt was made to
write the serial peripheral data register while a
data transfer was taking place with an external
device. The transfer continues uninterrupted;
therefore, a write will be unsuccessful. A "read
collision" will never occur since the received
data byte is placed in a buffer in which access
is always synchronous with the MCU opera-

2-103

tion. If a "write collision" occurs, WCOL is set
but no SPI interrupt is generated. The WCOL
bit is a status flag only.
Clearing the WCOL bit is accomplished by a
software sequence of accessing the serial peripheral status register while WCOL is set, followed by 1) a read of the serial peripheral data
register prior to the SPIF bit being set, or 2) a
read or write ofthe serial peri pheral data reg ister after the SPI F bit is set. A write to the serial
peripheral data register (SPDR) prior to the
SPIF bit being set, will result in generation of
another WCOL status flag. Both the SPI F and
WCOL bits will be cleared in the same sequence. If a second transfer has started while
trying to clear (the previously set) SPIF and
WCOL bits with a clearing sequence containing a write to the serial peripheral data register, only the SPIF bit will be cleared.
A collision of a write to the serial peripheral
data register while an external data transfer is
taking place can occur in beth the master
mode and the slave mode, although with the
proper programming the master device should
have sufficient information to preclude this
collision.
Collision in the master device is defined as a
write of the serial peripheral data register
while the internal rate clock (SCK) is in the
process of transfer. The signal on the SS pin is
always high on the master device.
A collision in a slave device is defined in two
separate modes. One problem arises in a slave
device when the CPHA control bit is a logic
zero. When CPHA is a logic zero, data is
latched with the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs
when it attempts to write the serial peripheral
data register after its SS pin has been pulled
low. The SS pin of the slave device freezes the
data in its serial peripheral data register and
does not allow it to be altered if the CPHA bit is
a logic zero. The master device must raise the
S"S pin of the slave device high between each
byte it transfers to the slave device.
The second collision mode is defined for the
state of CPHA control bit being a logic one.
With the CPHA bit set, the slave device will be
receiving a clock (SCK) edge priorto the latch
of the first data transfer. This first clock edge
will freeze the data in the slave device 1/0 register and allow the MSB onto the external
MISO pin of the slave device. The SS pin low
state enables the slave device but the drive
onto the MISO pin does not take place until the
first data transfer clock edge. The WCOL bit
will only be set if the 1/0 register is accessed
while a transfer is taking place. By definition of
the second collision mode, a master device
might hold a slave device SS pin low during
a transfer of several bytes of data without a
problem.
A special case of WCOL occurs in the slave
device. This happens when the master device

CDP68HC05D2
startsa transfer sequence (an edge of SCK for
CPHA=1; or an active SS transition for
CPHA=O) at the same time the slave device
CPU is writing to its serial peripheral interface
data register. In this case it is assumed that the
data byte written (in the slave device serial
peripheral interface) is lost and the contents of
the slave device read buffer become the byte
that is transferred. Because the master device
receives back the last byte transmitted, the
master device can detect that a fatal WCOl
occurred.
Because the slave device is operating asynchronously with the master device, the WCOl bit
may be used as an indicator of a collision occurrence. This helps alleviate the user from a
strict real-time programming effort. The
WCOl bit is cleared by reset.
Bit 4 MODF The function of the mode fault flag (MODF) is
defined for the master mode device. If the device is a slave device, the MODF bit will be
prevented from toggling from a logic zero to a
logic one; however, this does not prevent the
device from being in the slave mode with the
MODF bit set. The MODF bit is normally a
logic zero and is set only when the master
device has its SS pin pulled low. Toggling the
MODF bit to a logic one affects the internal
serial peripheral interface (SPI) system in the
following ways:
1. MODF is set and SPI interrupt is generated

if SPIE=1.
2. The SPE bit is forced to a logic zero. This
blocks all output drive from the device, disabled the SPI system.
3 .The MSTR bit is forced to a logic zero, thus
forcing the device into the slave mode.
Clearing the MODF is accomplished by a
software sequence of accessing the serial peripheral status register while MODF is set followed by a write to the serial peripheral control
register. Control bits SPE and MSTR may be
restored to their original set state during this
clearing sequence or after the MODF bit has
been cleared. Hardware does not allow the
user to set the SPE and MSTR bit while MODF
is a logic one unless it is during the proper
clearing sequence. The MODF flag bit indicates that there might have been a multi-master conflict for system control and allows a
proper exit from system operation to a reset or
default system state. The MODF bit is cleared
by reset.

Serial Peripheral Data 1/0 Register (SPDR)
7

6

5

4

3

2

Serial Peripheral Data I/O Register

o

ISOC

The serial peripheral data I/O register is used to transmit
and receive data on the serial bus. Only a write to this
register will initiate transmission/reception of another byte
and this will only occur in the master device. A slave device
writing to its data I/O register will not initiate a transmission.
At the completion of transmitting a byte of data, the SPIF
status bit is set in both the master and slave devices. A write

or read of the serial peripheral data I/O register, after accessing the serial peripheral status register with SPIF set,
will clear SPIF.
During the clock cycle that the SPIF bit is being set, a copy
of the received data byte in the shift register is being moved
to a buffer. When the user reads the serial peripheral data
I/O register, the buffer is actually being read. During an
overrun condition, when the master device has sent several
bytes of data and the slave device has not internally responded to clear the first SPIF, only the first byte is contained in the receive buffer of the slave device; all others are
lost. The user may read the buffer atanytime. Thefirst SPIF
must be cleared by the time a second transfer of data from
the shift register to the read buffer is initiated or an overrun
condition will exist.
A write to the serial peripheral data I/O register is not buffered and places data directly into the shift register for
transmission.
The ability to access the serial peripheral data I/O register is
limited when a transmission is taking place. It is important
to read the discussion defining the WCOl and SPIF status
bits to understand the limits on using the serial peripheral
data I/O register.

Serial Peripheral Interface (SPI)
System Considerations
There are two types of SPI systems: single master system
and multi-master systems. Figure20 illustrates both of
these systems and a discussion of each is provided below.
Figure20a illustrates how a typical single master system
may be configured, using a CDP6805 CMOS Family device
as the master and four CDP6805 CMOS Family devices as
slaves. As shown, the MOSI, MISO, and SCK pins are all
wired to equivalent pins on each of the five devices. The
master device generates the SCK clock, the slave devices all
receive it. Because the CDP6805 CMOS master device is the
bus master, it internally controls the function of its MOSI
and MISO lines, thus writing data to the slave devices on the
MOSI and reading data from the slave devices on the MISO
lines. The master device selects the individual slave devices
by using four pins of a parallel port to control the four SS
pins of the slave devices. A slave device is selected when the
master device pulls its SS pin low. The SS pins are pulled
high during reset because the master device ports will be
forced to be inputs at that time, thus disabling the slave
devices. Notice that the slave devices do not have to be
enabled in a mutually exclusive fashion except to prevent
bus contention on the MISO line. For example, three slave
devices enabled for a transfer are permissible if only one
has the capability of being read by the master. An example
of this is a write to several display drivers to clear a display
with a single I/O operation. To ensure that proper data
transmission is occurring between the master device and a
slave device, the master device may have the slave device
respond with a previously received data byte (this data byte
could be inverted or at least be 1i byte that is different from
the last one sent by the master device). The master device
will always receive the previous byte back from the slave
device if all MISO and MOSI lines are connected and the
slave has not written to its data I/O register. Other transmission security methods might be defined using ports for
handshake lines or data bytes with command fields.
A multi-master system may also be configured by the user.
A system ofthistype isshown inFigure20b. An exchange of

2-104

CDP68HC05D2

master control could be implemented by an exchange of
code messages through the serial peripheral interface system. The major device control that plays a part in this system is the MSTR bit in the serial peripheral control register
and the MOOF bit in the serial peripheral status register.

Note that the OWOM bit would also be set to prevent bus
contention. For additional information on this configuration and SPI in general, refer to RCA Application Note ICAN
7264 entitled "Versatile Serial Protocol for a Microcomputer-Peripheral Interface."

Effects of Stop and Wait Modes on the
Timer and Serial System
The STOP and WAIT instructions have different effects on
the programmable timer and serial peripheral interface
(SPI) system. These different effects are discussed separately below.

Stop Mode
When the processor executes the STOP instruction, the
internal oscillator is turned off. This halts all internal CPU
processing and the serial peripheral interface. The programmable timer will only continue to count if an external
timer oscillator is used. The only way for the MCU to "wake
up" from the stop mode is by receipt of an external interrupt
(logic Iowan IRQ pin), an external timer oscillator interrupt,
a Port B interrupt or by the detection of a reset (logic Iowan
RESET pin or a power-on reset). The effects of the stop
mode on each of the MCU systems (Timer and SPI) are
described separately.

Timer During Stop Mode
When the MCU enters the STOP mode, the timer will continue to count and generate interrupts if using an external
timer oscillator. If using the CPU clock to clock the timer,
the timer counter stops counting (the internal processor
clock is stopped) and remains at that particular count value
until the stop mode is exited by an interrupt (if exited by
reset the counter is forced to $FFFC). If the stop mode is
exited by an external Iowan the iR"Q pin, then the counter
resumes from its stopped valueas if nothing had happened.
Another feature of the programmable timer, in the stop
mode, is that if at least one valid input capture edge occ,urs
at the TCAP pin, the input capture detect circuitry is armed.
This action does not set any timer flags or "wake up" the
MCU, but when the MCU does "wake up" there will be an
active input capture flag (and data) from that first valid edge
which occurred during the stop mode. If the stop mode is
exited by an external reset (logic Iowan RESET pin), then
no such input capture flag or dalaaction takes place even if
there WaS a valid input capture edge (at the TCAP pin)
during the MCU stop mode.

SPI During Stop Mode
When the MCU enters the stop mode, the baud rate generator which drives the SPI shuts down. This essentially stops

all master mode SPI operation, thus the master SPI is unable to transmit or receive any data. If the STOP instruction
is executed during an SPI transfer, that transfer is halted
until the MCU exits the stop mode (provided it is an exit
resulting from a logic Iowan the IRQ pin). If the stop mode
is exited by a reset, then the appropriate control/status bits
are cleared and the SPI is disabled. If the device is in the
slave mode when the STOP instruction is executed, the
slave SPI will still operate. It can stili accept data and clock
information in addition to transmitting its own data back to
a master device.
At the end of a possible transmission with a slave SPI in the
STOP mode, no flags are set until a logic low i'R'Q input
results in an MCU "wake up". Caution should be observed
when operating the SPI (as a slave) during the stop mode
because none of the protection circuitry (write collision,
mode fault, etc.) is active.
It should also be noted that when the MCU enters the stop
mode all enabled output drivers (TOO, TCMP, MISO, MOSI,
and SCK ports) remain active and any sourcing currents
from these outputs will be part of the total supply current
required by the device.

Wait Mode
When the MCU enters the wait mode, the CPU clock is
halted. Ail CPU action is suspended; however, the timer and
SPI systems remain active. In fact an interrupt from the
timer or SPI (in addition to a logic Iowan the 1RQ or RESET
pins or a Port B interrupt, if enabled) causes the processor
to exit the wait mode. Since the three systems mentioned
above operate as they do in the normal mode, only a general
discussion of the wait mode is provided below.
The wait mode power consumption depends on how many
systems are active. The power consumption will be highest
when all the systems (timer, TCMP and SPI) are active. The
power consumption will be the least when the SPI system is
disabled (timer operation cannot be disabled in the wait
mode). If a non-reset exit from the wait mode is performed
(i.e., timer overflow interrupt exit), the state of the remaining systems will be unchanged. If a reset exit from the wait
mode is performed all the systems revert to the disabled
reset state.

2-105

-

z

o(.)

o

a:

(.)

SE

CDP68HC05D2

Instruction Set
The MCU has a set of 62 basic instructions. They can be
divided into five different types: register/memory, read/
modify/write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type. All the instructions within a given type are presented in individual
tables.

Z: Not affected
C: Cleared
Source
Form(s):

All of the instructions used in the CDP6805 CMOS Family
are used in the CDP68HC05D2 MCU, plus an additional
one; the multiply (MUL) instruction. This instruction allows
for unsigned multiplication ofthe contents ofthe accumulator (A) and the index register (X). The high order product is
then stored in the index register and the low order product
is stored in the accumulator. A detailed definition of the
MUL instruction is shown below.
Operation:

X:A

Description:

Multiplies the eight bits in the index register
by the eight bits in the accumulatorto obtain
a 16-bit unsigned number in the concatenated accumulator and index register.

Condition
Codes:

~

Table VI -

Cycles
11

Bytes Opcode
1
$42

Register/Memory Instructions
Most ofthese instructions use two operands. The first operand is either the accumulator or the index register. The
second operand is obtained from memory using one of the
addressing modes. The operand forthe jump unconditional
(JMP) and jump to subroutine (JSR) instructions is the
program counter. Refer to Table VI.

X'A

H: Cleared
I: Not affected
N: Not affected

MUL
Addressing
Mode
Inherent

Ready-Modify-Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value
back to memory or to the register. The test for negative or
zero (TST) instruction is an exception to the read/modify/write sequence since it does not modify the value. Refer
to Table VII.

Register/Memory Instructions
Addressing Modes

Immediate

Direct

Extended

Indexed
(No Offset)

Indexed
Offset)

Indexed

(8~Bit

(16-BiIOffset)

Function

Mnem.

Code

By'••

•

Cycles

•

Code

Bytes

•

Cycles

•

Cod.

Bytes

•

Cycles

•

Code

Bytes

•

Cycles

•

Code

Byles

•

Cycles

•

Code

Bytes

Load A from Memory

LOA

A6

2

2

B6

2

3

C6

3

4

F6

1

3

E6

2

4

06

3

5

Load X from Memory

LOX

AE

2

2

BE

2

3

CE

3

4

FE

1

3

EE

2

4

DE

3

5

Store A in Memory

STA

-

-

2

4

C7

3

5

F7

1

4

E7

2

5

07

3

6

STX

-

B7

Store X in Memory

BF

2

4

CF

3

5

FF

1

4

EF

2

5

OF

3

6

Add Memory to A

ADD

AB

2

2

BB

2

3

CB

3

4

FB

1

3

EB

2

4

DB

3

5

Add Memory and
Carry to A

ADC

A9

2

2

B9

2

3

C9

3

4

F9

1

3

E9

2

4

09

3

5

Subtract Memory

2

2

. BO

2

3

CO

3

4

FO

1

3

EO

2

4

DO

3

5

C2

3

4

F2

1

3

E2

2

4

02

3

5

Op

Op

Op

Op

Op

•

Op

•

Cycles

SUB

AD

Subtract Memory from
A with Borrow
SBC

A2

2

2

B2

2

3

AND Memory to A

AND

A4

2

2

B4

2

3

C4

3

4

F4

1

3

E4

2

4

04

3

5

OR Memory with A

OAA

AA

2

2

BA

2

3

CA

3

4

FA

1

3

EA

2

4

DA

3

5

Exclusive OR Memory
EOA
with A

AB

2

2

B8

2

3

C8

3

4

F8

1

3

E8

2

4

08

3

5

Arithmetic Compare A
with Memory
CMP

A1

2

2

B1

2

3

C1

3

4

F1

1

3

E1

2

4

01

3

5

Arithmetic Compare X
with Memory
CPX

A3

2

2

B3

2

3

C3

3

4

F3

1

3

E3

2

4

03

3

5

3

E5

2

4

05

3

5

Bit Test Memory with
A (Logical Compare)

BIT

A5

2

2

B5

2

3

C5

3

4

F5

1

Jump Unconditional

JMP

-

-

BC

2

2

CC

3

3

FC

1

2

EC

2

3

DC

3

4

Jump to Subroutine

JSA

-

-

-

BD

2

5

CD

3

6

FD

1

5

ED

2

6

DO

3

7

Table VII -

Read-Modify-Write Instructions
Addressing Modes

Inherent (A)

Inherent (X)

Direct

Indexed
(No Offset)

Indexed
(a-Bit Offset)

Mnemonic

Code

Bytes

•

Cycles

•

Code

Bytes

•

Cycles

•

Code

Bytes

•

Cycles

•

Code

Bytes

Cycles

•

Code

Bytes

Increment

INC

4C

1

3

5C

1

3

3C

2

5

7C

1

5

6C

2

6

Decrement

DEC

4A

1

3

5A

1

3

3A

2

5

7A

1

5

6A

2

6

Clear

CLR

4F

1

3

5F

1

3

3F

2

5

7F

1

5

6F

2

6

Complement

COM

43

1

3

53

1

3

33

2

5

73

1

5

63

2

6

Negate
(2's Complement)

NEG

40

1

3

50

1

3

30

2

5

70

1

5

60

2

6

Rotate Left Thru Carry

ROL

49

1

3

59

1

3

39

2

5

79

1

5

69

2

6

Rotate Right Thru
Carry

AOA

46

1

3

56

1

3

36

2

5

76

1

5

66

2

6

Logical Shift Left

LSL

3

58

1

3

38

2

5

78

1

2

6

1

3

54

1

3

34

2

5

74

1

5
5

68

LSA

64

2

6

Arithmetic Shift Right

ASA

48
44
47

1

Logical Shift Righi

1

3

57

1

3

37

2

5

77

1

5

67

2

6

Test for Negative
or Zero

TST

40

1

3

5D

1

3

3D

2

4

7D

1

4

60

2

5

Multiply

MUL

42

1

11

-

-

-

-

-

-

-

-

-

-

-

-

Op
Function

Op

2-106

Op

Op

#

Op

•

•

Cycles

CDP68HC05D2

Branch Instructions
Most branch instructions test the state of the condition
code register and, if certain criteria are met, a branch is

Table VIII -

executed. Thisadds an offset between -127 and +128to the
current program counter. Refer to Table VIII.

Branch Instructions
Relative Addressing Mode
Mnemonic

Op
Code

#
Bytes

#
Cycles

Branch Always

BRA

20

2

3

Branch Never

BRN

21

2

3

Branch IFF Higher

BHI

22

2

3

Branch IFF lower or Same

BlS

23

2

3

Branch IFF Carry Clear

BCC

24

2

3

(BHS)

24

2

3

Function

(Branch IFF Higher or Same)
Branch IFF Carry Set

BCS

25

2

3

(BlO)

25

2

3

Branch IFF Not Equal

BNE

26

2

3

Branch IFF Equal

BEQ

27

2

3

Branch IFF Half Carry Clear

BHCC

28

2

3

Branch IFF Half Carry Set

BHCS

29

2

3

BPl

2A

2

3

(Branch IFF lower)

Branch IFF Plus
Branch IFF Minus

BMI

2B

2

3

Branch IFF Interrupt Mask Bit is Clear

BMC

2C

2

3

Branch IFF Interrupt Mask Bit is Set

BMS

20

2

3

Bil

2E

2

3

Branch IFF Interrupt Line is low
Branch IFF Interrupt Line is High

BIH

2F

2

3

Branch to Subroutine

BSR

AD

2

6

Bit Manipulation Instructions
The MCU is capable of setting or clearing any bit which
resides in the fi rst 256 bytes of the memory space except for
ROM, port 0 data location ($03) bits 0,1,6,7, serial peripheral status register ($OB), timer status register ($13), and timer
input capture register ($14, $15). All port registers, OORs,
timer, serial system, on-chip RAM, and 128 bytes of ROM

Table XI -

...::::l
In

II:

CI

II:
IZ

CI
..,.

i..,.
iiE

reside in the first 256 bytes (pages zero). An additional
featu re allows the software to test and branch on the state of
any bit within the first 256 locations. The bit set, bit clear,
and bit test and branch functions are all implemented with a
single instruction. For the test and branch instructions, the
value of the bit tested is automatically placed in the carry bit
of the condition code register. Refer to Table IX.

Bit Manipulation Instructions

Addressing Modes
Bit Set/Clear
Function

Mnemonic

Branch IFF Bit n is Set

BRSET n (n=0 ... 7)

Branch IFF Bit n is Clear

BRClR n (n=0 ... 7)

Op
Code

-

Bit Test and Branch

#
Cycles

Op
Code

#
Bytes

#
Cycles

-

-

2-n

3

5

01 + 2-n

3

5

-

-

#
Bytes

Set Bit n

BSET n (n=0 ... 7)

10 + 2-n

2

5

Clear Bit n

BCLR n (n=0 ... 7)

11 + 2-n

2

5

2-107

-

-

CDP68HC05D2

Control Instructions
These instructions are register reference instructions and

are used to control processor operation during a program
execution. Refer to Table X.

Table X - Control Instructions
Inherent
Function

Mnemonic

Op
Code

#
Bytes

#
Cycles

Transfer A to X

TAX

97

1

Transfer X to A

TXA

9F

1

2
2

Set Carry Bit

SEC

99

1

2

Clear Carry Bit

CLC

98

1

2

Set Interrupt Mask Bit

SEI

9B

1

2

Clear I nterrupt Mask Bit

CLI

9A

1

2

Software Interrupt

SWI

83

1

10

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

80

1

9

Reset Stack Pointer

RSP

9C

1

No-Operation

NOP

90

1

2
2

Stop

STOP

8E

1

2

Wait

WAIT

8F

1

2

Alphabetical Listing
The complete instruction set is given in alphabetical order
in Table XI.

Opcode Map
Table XII is an opcode map for the instructions used on the
MCU.

Addressing Modes
The MCU uses ten different addressing modes to provide
the programmer with an opportunity to optimize the code to
all situations. The various indexed addressing modes make
it possible to locate data tables, code conversion tables, and
scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions, while the longest instructions (three bytes) permit accessing tables

throughout memory. Short absolute (direct) and long absolute (extended) addressing are also included. One and two
byte direct addressing instructions access all data bytes in
most applications. Extended addressing permits jump instructions to reach all memory. Table XII shows the addressing modes for each instruction, with the effects each
instruction has on the condition code register.
The term "effective address" (EA) is used in describing the
various addressing modes, and is defined as the byte address to or from which the argument for an instruction is
fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate
"contents of" the location or register referred to; e.g., (PC)
indicates the contents of the location pointed to by the PC.
An arrow indicates "is replaced by", and a colon indicates
concatenation of two bytes.

2-108

CDP68HC05D2
Table XI -

Instruction Set

Addrelslng Mod••

Condition Codes

Indexed
(NoOH,.I)

Indexed
(8 BIIs)

Indexed
(16 BII_)

Immediate

Oirect

Exlended

ADC

X

X

X

X

X

X

ADD

X

X

X

X

X

X

ANO

X

X

X

X

X

X

X

X

X

X

Mnemonic

Inherent

ASl

X

X

ASR

X

X

Relative

Bit
S.tl
Clear

Bit
Test &
Branch

X

BCC

BelA

X

BCS

X

BEQ

X

BHCC

X

BHCS

X

BHI

X

BHS

X
X

BIH
Bil

X

X

BIT

X

X

X

X

X

X

BlO
BlS

X

BMC

X

BMI

X

BMS

X

BNE

X

BPl

X

BRA

X

BRN

X

BRCLR

X

BASET

X
X

BSET
BSR

X

ClC

X

CLI

X

ClR

X

DEC
INC

X

X

X

X

X

X

X

X

X

X

X

x

X

X

X

X

X
X

X

X

x

X
X

X

x

EaR

X
X

X

JMP

X
X
X

X

X

X

X

X

X

X

X

X

X

LOA

X

X

X

X

X

X

lOX

X

X

X

X

X

X

X
X

JSR

lSl

X

X

X

lSR

X

X

X

MUl

X

NEG

X

NOP

X

ROl

X
X

X

RSP

X

RTI

X

RTS

X

SEC

X

SEI

X

X

X

X

X

X

X

X

X

X

X

X

X

X

TAX

X

TST

X

TXA

X

WAIT

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Half Carry (From Bit 3)
Interrupt Mask
Negate (Sign Bit)

A

A

A

A

A

A

A

A

A

A
A

0

1

A

A

A

A

1

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

0

A

A

A

A

A

A

A

A

A

A

A

A

A

?

?

?

A

A

A

0

?

A

A

A

A

A

A

A

A

A

1

X

X

X

0

Condition Code Symbols:
H
I
N

A

A

0

STX

X

A

1

X

SWI

A

1

X

SUB

A

A

?

STA
STOP

X

X

X

X

SBC

X

X

X

ROR

C

A

0

X

ORA

Z

A

I

0

X

CPX

N

A

0

X

CMP
COM

·
·· ··· ·
··· ··· ·· ·· ··
··· ··· ··· ··· ···
··· ··· ··· ··· ···
·· ·· ·· ·· ··
·· ·· · · ··
··· ··· ··· ··· ···
·· ·· ·· ·· ··
·· ·· ·· ·· ··
·· ·· ·· ·· ·
··· ··· ··· ··· ··
·· · ·· ·· ·
·· ·· ·
·· ··
··· ··· ···
·· ·· ·· ·· ··
·· ·· ··
·· ··· · ·
··· ··· · · ··
·· ··
·····
·· ·· · · ·
··· ·· ·· ·· ··
·· · · · ··
·· · · · ·
·· ·· · · ··
·· · ·· ·· ··
H

Z
C
A

•

Zero
Carry/Borrow
Test and Set if True Cleared Otherwise

2-109

Not Affected
Load CC Register From Stack

o

Cleared

1

Set

CDP68HC05D2

Table XII - CDP68HC05D2 HCMOS Instruction Set Opcode Map

~

"'''nlpu''Uon

....• ...,
aTa

HI

Low

5

0
0000
1
0001

a ......
REL

DIR

INH

1

2
001.

3
0011

4

BRSETO
3 BTB

5
BSETO
2 BSC

5
BRCLAO

BClRO

•

BTB

5
2

BSC

2
0010

5
SASETl
BTB

5
BSET1
2 BSC

0011

5
BReLA1
BTB

5
BelR1
2 BSC

4
0100

5
BRSET2
BTB

5
BSET2
2 BSC

5

5

BACLR2
BTB

BCLR2
2 BSC

5

5

•
• •
•
•
5

0101

6
0110

3

BRSET3
BTB

BSET3
2 BSC

7
0111

5
BRCLR3
3 BTB

5
BClA3
2

•

5
BRSET4
3 BTB

5
BSET4
2 BSC

5

5

BRCLR4
BTB

BCLR4
2 BSC

5
BASET5
3 BTB

5
BSETS
2 BSC

5

5

3

BACLR5
BTB

BCLR5
2 BSC

5
BRSElS
3 BTB

5
BSET6
2 BSC

5

BRCLR6
BTB

5
BCLA6
2 BSC

5
BRSET7
BTB

5
BSET7
2 BSC

5

5

BRCLA7
BTB

BCLR7
2 BSC

1000

9
1001
A

lOla
B

101'
C

1100
0
"01
E
1110

F
1111

,

,
,
,

RHdlModlfrlWrlle

asc

BSC

INH

•

IX

0110

7
0111

•

0101

.'00

Control
IXI

3

5

3

3

BRA
2 REL

NEG
2
DIR

NEG
1
INH

NEG
1
INH

•

NEG
2
IXI

,•

NEG
1
IX

BHI
REL

2

BLS
REL

2

3
BCC
2 REL

•
•

5
COM
DIR

•

3
COMA
1
INH

•

5

LSR
2 DTR

LSAA
1
INH

BNE
REl

2

BED
REL

5
2

•
SHes•

2

2

2

REL

ROR
DIR

3
RORA
1
INH

5

3

ASR
DIR

1

ASRA
INH

5

BHCC
2

•
•

COMX
1
INH
LSRX
1
INH

2

lSl
DIR

LSLA
'NH

1

•

5

REl

ROLA
1
INH

3

5

3

2

DEC
DIR

RDAX
1

2

COM
IXI

1

COM
IX

lSR
2
IXI

5

4

RT1
1
INH

SUB
2 lMM

SUB
2
DIR

SUB
EXT

SUB
IX2

SUB
2
IXI

6

2

5

4

RTS
INH

2

2

2

2

,

BMS
REl

,

1

1

OECA
INH

•

SWI
INH

1

2

CPX
IMM
2

IX

AND
2 IMM

ROR
2. IXI

6

LSlX

•

INH

1

•
•

ROLX
1
INH

1

2

6

3
ASRX
INH

OECK
INH

2

ASR
IXI

1

lSl
IXI

ASR

1

IX

DEC
IXI

1

IX

X
IMM
DIR
EXT

Inherent
Accumulator
Index Register
Immediate
Direct
Edended

2

INC
DIR

1

INCA
INH

•

4

2

TAX
INH
ClC
INH

2
2
2

EOR
IMM

TST
DIR

1

TSTA
INH

1

1

INCX
INH

,

TSTX
INH

2

INC
IXI
TST
IXI

2
ORA
IMM

SEI
INH

5
2

ClR
DIR

IX

1

2

ADD
IMM

TST
IX

1

RSP
INH
Nap
INH

2

6
2

1

CLAA
INH

1

CLRX
INH

2

ClR
IXI

BSR
REl

IX

1

INH

1

ADD
DIR

lOX
IMM

TXA
INH

JMP
DIR

2

JSR
DIR

,

lOX
DIR
STX
DIR

3

CMP
IX2

·•
.

3

STA
EXT

,

EOR
EXT
4

lOA
IX2

3

STA
IX2
EOR
IX2

•
•

2

2

5
0101

LOA
IXI

3
LOA'
1
,X

0110

5

4

STA
IXI
EOR
IXI

ADD
IX2

JSH
EXT
lOX
EXT

3

STX
EXT

2

ADD
IXI

JSR
IX2

2

JMP
IXI

2

JSR
IXI

2

lOX
IXl

STX
IX2

EOR

STX
IXI

IX

0111

IX

1000

,
,

1001

• •
,

ADC

1

IX

1

ORA
IX

1

ADD
IX

9
A

'9..~
B
1011

2
JMP

C
IX

1

1100

5

0

JSR
IX

1

1101

3
LDX

E
IX

1

1110

4

5
2

6

7

1

4

6
3

STA

1

6

5
lOX
IX2

1

3

4

•

CPX

1

4

2

0010

• •
•
•

,X

4

2

2

,X

BIT

BIT
IXI

ADD
EXT

7

SBC

1

4

4

JMP
IX2

1
0001

•

4
0100

IX'"

5

5
3

2

ADC
,X2

6

CMP
IX

0011

4

JMP
EXT

1

'X

ORA
IX2

3

0
0000

•

AND
1
'X

AND

5

5

IX

4

4

ORA
EXT

4

3

CPX
IXI

5

, ,
,
, ,
3

2

6
3

1

4

ADC
2
'XI
4
ORA
IXI
2

ADC
EXT
4

3

SBC
IXI

5

4

3

2

5
BIT
IX2

Low

SUB

4

5

AND
IX2

3

CMP
IXI

5

CPX
,X2

•

2

5

SBC
,X2

5

4

2

LOA
EXT

•

HI

3

F

STX
1

IX

1111

LEGEND

Relative
Bit Set/Clear
Bit Test and Branch
IndeKed (No Offset)
IndeKed, 1 Byte (S·Bit) Offset
Indexed, 2 Byte (t6·Bit) Offset

I-F~=l------70PCODE

---+--

CYCLES------J

Inherent
In inherent instructions, all the information necessary to
execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, and
no 0ther arguments, are included in this mode.
Immediate
In immediate addressing, the operand is contained in the
byte immediately following the opcode. Immediate addressing is used to access constants which do not change
during program execution (e.g., a constant used to initialize
a loop counter).

= PC +1; PC -

2

2

WAIT

ClR

1

2

2

3

5

2

STOP
INH

5

6

2

•
,

ORA
DIR

2

2

4

1

•

3

2

2

2

INC

1

EOR
DIR

2

5
2

STA
DIR

5

5
1

LOA
DIR

IX

2

4

4

ADC
2
DIR

5

5

.AND
EXT

BIT
EXT

ADC
2 IMM

Cli
INH

4

3

SEC
1
INH

1

CPX
EXT

3
2

4

BIT
DIR

3

IX

SBC
EXT

CPX
DIR

2

DEC

1

2

4

•
•
•
•
•
•
•

AND
DIR
2

2

4

CMP
EXT

•

SBC
DIR

2

.. NE .. ONIC
BYTES

EA

2

•

4

2

,

REl
BSC
BTB
IX
IXI
IX2

2

5
ROl

1

LOA
IMM

2

lSL

1

6
2

1

5

6
ROL
IXI
2

2

CMP
DIR

3

2

5

Abbreviations for Address Modes
INH
A

2

2

ROR
IX

6
2

BIT
IMM

5

1
3

5

Bil
REl
BIH
REl

•

2

5

BMI
REl
BMC
REl

SBC
IMM

2

3
2

CMP
IMM

10

LSR

1

IX
F
1111

E
1110

4

5

6

IXI

IX'
D
1101

c

3

3
2

1100

•

2

6

INH

3

ROl
2
DIR

BPl
REl

EXT

1001

a
1011

2

3
2

DIR

A
1010

2

BCS
REl

2

I ....

2

1
11
MUL
1
INH

./

Aqlllter/Memory
INH

9

5

3
BRN
2 REL

•
•

...

INH

PC + 2

Direct
In the direct address'ing mode, the effective address of the
argument is contained in a single byte following the opcode
byte. Direct addressing allows the user to directly address
the lowest 256 bytes in memory with a single two byte
instruction. This includes all on-chip RAM and I/O registers, and 128 bytes of on-chip ROM. Direct addressing is
efficient in both memory and time.

IN HEXADECIMAL

OPCOOE 1 N BINARY

' - - - - - - A O O R E S S .. ODE

EA = (PC +1); PC - PC + 2
Address Bus High - 0; Address Bus Low - (PC+1)
Extended
In the extended addressing mode, the effective address of
the argument is contained in the two bytes following the
opcode. Instructions with extended addressing modes are
capable of referencing arguments anywhere in memory
with a single three-byte instruction.
EA = (PC +1):(PC + 2); PC - PC + 3
Address Bus High - (PC + 1); Address Bus Low - (PC+2)
Indexed, No Offset
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first
256 memory locations. These instructions are only one byte
long, This mode is used to movea pointer through a tableor
to address a frequently referenced RAM or I/O location.

2-110

EA = X; PC - PC + 1
Address Bus High - 0; Address Bus Low - X

CDP68HC05D2

Indexed, 8-Bit Offset
Here the EA is obtained by adding the contents of the byte
following the opcode to that of the index register; therefore,
the operand is located anywhere within the lowest 511 memory locations. For example, this mode of addressing is useful for selecting the mth element in a n element table. All
instructions are two bytes. The content of the index register
(X) is not changed. The content of (PC+1) is an unsigned
8-bit integer. One byte offset indexing permits look-up tables to be easily accessed in either RAM or ROM.

EA = X + (PC +1); PC - PC +2
Address Bus High - K; Address Bus Low - X + (PC + 1)
where;
K = The carry from the addition of X + (PC +1)

Indexed, 16-Blt Offset
In the indexed, 16-bit offset addressing mode, the effective
address is the sum of the contents of the unsigned 8-bit
index register and the two unsigned bytes following the
opcode. This addressing mode can be used in a manner
similar to indexed 8-bit offset, except that this three byte
instruction allows tables to be anywhere in memory (e.g.,
jump tables in ROM). The content ofthe index register is not
changed.

EA

=X+

[(PC +1):(PC + 2))]; PC - PC +3
Address Bus High - (PC + 1) + K;
Address Bus Low - X + (PC +2)

where:

K = The carry from the addition of X + (PC + 2)
Relative
Relative addressing is used only in branch instructions. In
relative addressing, the content of the 8-bit signed byte
following the opcode (the offset) is added to the PC if and
only if the branch condition is true. Otherwise, control pro-

ceeds to the next instruction. The span of relative addressing is limited to the range of -126 to +129 bytes from the
branch instruction opcode location.
EA = PC + 2 + (PC +1); PC - EA if branch taken;
otherwise, EA = PC - PC + 2
Bit Set/Clear
Direct addressing and bit addressing are combined in instructions which set and clear individual memory and 1/0
bits. In the bit set and clear instructions, the byte is specified
as a direct address in the location following the opcode. The
first 256 addressable locations are thus accessed. The bit to
be modified within that byte is specified in the first three bits
ofthe opcode. The bit set and clear instructions occupy two
bytes, one for the opcode (including the bit number) and
the other to address the byte which contains the bit of
interest.

EA = (PC +1); PC - PC + 2
Address Bus High - 0; Address Bus Low - (PC +1)
Bit Test and Branch
Bit test and branch is a combination of direct addressing, bit
set/clear addressing, and relative addressing. The actual bit
to be tested, within the byte, is specified within the low order
nibble of the opcode. The address of the data byte to be
tested is located via a direct address in the location following the opcode byte (EA 1). The signed relative 8-bit offset is
in the third byte (EA2) and is added to the PC ifthe specified
bit is set or cleared in the specified memory location. This
single three-byte instruction allows the program to branch
based on the condition of any bit in the first 256 locations of
memory.
EA1 = (PC+ 1)
Address Bus High - 0; Address Bus Low - (PC + 1)
EA2 = PC + 3 + (PC + 2); PC - EA2 if branch taken;
otherwise, PC - PC + 3

2-111

CDP68HC05D2

Device Characteristics
MAXIMUM RATINGS (Voltages Referenced to Vss)
Ratings

Symbol

Value

Unit

Supply Voltage

Voo
V,n

-0.5 to +7.0

V

Vss -0.5 to Voo +0.5

V

I

25

mA

-40 to +125

DC

-65 to +150

°C

Input Voltage
Current Drain Per Pin Excluding Voo and Vss
Operating Temperature Range

TA

Storage Temperature Range

T....

THERMAL CHARACTERISTICS
Characteristics
Thermal Resistance
Ceramic
Plastic
Plastic Chip Carrier

Symbol

Value

Unit

8JA

50
100
70

°C/W

This device contains circuitry to protect the inputs against
damage due to high static voltages of electric fields; however, it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it
is recommended that V'n and Vou, be constrained to the
range Vss'S" (V,n or VDU.)'S"Voo. Reliability of operation is enhanced if unused inputs except OSC2 are connected to an
appropriate logic voltage level (e.g., either Vss or Voo).

Voo = 4.5 V
Pins
PAC-PA7,
PBO-PB7,
PCO-PC7,
PD6
PD1-PD4

R1

R2

3.26 kO

2.38 kO

C
50 pF

1.9 kO

2.26 kO

200 pF

R2
(SEE TABLE)
TEST
POINT

c

Voo= 3.0 V
Pins
PAO-PA7,
PBO-PB7,
PCO-PC7,
PD6
PD1-PD4

R1

R2

10.91 kO 6.32 kO

6kO

6kO

( SEE
TABLEl

C

RI

(SEE TABLE)

50 pF

92CS-39387

200pF

Fig. 24 - Equivalent Test Load

Power Considerations
The average chip-junction temperature, TJ, in °C can be
obtained from:
TJ=TA+(Poo8JA)
(1)
Where:
TA = Ambient Temperature, DC
8JA = Package Thermal Resistance. Junctionto-Ambient, °C/W
Po = P,NT + P'iO
P,NT = Icc x Vee, Watts - Chip Internal Power
PI/O = Power Dissipation on Input and Output
Pins - User Determined

An approximate relationship between Po and TJ (if P'iO is
neglected is:
Po = K + (TJ + 273°C)
(2)
Solving equations 1 and 2 for K gives:
K = Po"(TA + 273°C) + 8JA"Po2

(3)

Where K is a constant pertaining to the particular part. K can
be determined from equation 3 by measuring Po (at equilibrium) for a known TA. Using this value of K the values of Po
and TJ can be obtained by solving equations (1) and (2)
iteratively for any value of T A.

For most applications P,iO < P,NT and can be neglected.
2-112

CDP68HC05D2

=

DC ELECTRICAL CHARACTERISTICS (Voo 5.0 Vdc
TA = -40°C to +125°C unless otherwise noted)

± 10%, V•• = 0 Vdc,

Characteristic
Output Voltage, ILoAO ~ 10.0 pA

Symbol

Min

VOL
VOH

-

Voo-0.1

VOH
VOH

Voo-0.8
Voo-0.8

VOL

-

Limits
Typ

Input High Voltage
PAO-PA7, PBO-PB7, PCO-PC7, PDO-PD5, PD7, TCAP,

mn, Fi"ESET, OSC1

V'H

0.7 x Voo

-

Input Low Voltage
PAO-PA7, PBO-PB7, PCO-PC7, PDO-PD5, PD7, TCAP,

1'Rn, ~, OSC1

V'L

V••

-

-

3.5
1.6
2

Output High Voltage
(!coad = 0.8 mAl PAO-PA7, PBO-PB7, PCO-PC7, TCMP
(ILoad = 1.6 mAl PD1-PD4
Output Low Voltage
(ILoad = 1.6 mAl PAO-PA7, PBO-PB7, PCO-PC7, PD2-PD5, TCMP

Total Supply Current (CL = 50 pF on Ports, no dc Loads, tcye = 500 ns,
(V'L 0.2 V, V'H = Voo - 0.2V) No external timer oscillator.
RUN
WAIT (See Note)
STOP (See Note)

=

Total Supply Current (CL = 50 pF on Ports, no dc Loads, tc,c = 500 ns,
(V'L = 0.2 V, V'N = Voo - 0.2V) 32.768 KHz external timer
crystal oscillator for circuit as shown in Fig. 13(c).
RUN
WAIT (See Note)
STOP (See Note)
I/O Ports Hi-Z Leakage Current
PAO-PA7, PBO-PB7, PCO-PC7, PD1-PD5

In~ikwrent

, 1'Rn, TCAP, OSC1, PD~, PD7

100
100
100

,I

100
100

IOD

NOTE: Measured under the following conditions:
1. All ports are configured as input, V'L = 0.2 V, V'H = Voo - 0.2 V.
2. No load on TCMP, CL = 20 pF on OSC2.
3. OSC1 is a square wave with V'L = 0.2 V, V'H = Voo - 0.2 V.
4. SPE=O
5. Typical values at midpoint of voltage range, +250 C only.

2-113

V
V

-

-

-

V
V

0.4

V

Voo

V

0.2

X

Voo

7
4
250

V

mA
mA
pA

-

4

2.1
0.5

8
5.5
1

mA
mA

rnA

f2

::l
....a:z

-

-

±10

pA

lin

-

-

±1

pA

-

12
8

pF
pF

-

CI

c.:I

CI

a:

c.:I

:E

I'L

Cout
C in

, TCAP, OSC1, PDO-PD5, PD7

Unit

0.1

CI

Capacitance

~EgE+a~~ut or output)

Max

-

CDP68HC05D2

=

DC ELECTRICAL CHARACTERISTICS (Voo 3.3 Vdc
TA = -40°C to +125°C unless otherwise noted)

± 10%, Vss = 0 Vdc,
Limits

Characteristic
Output Voltage, ILOAO

Symbol

:s: 10.0 IlA

Output High Voltage
(ILOB. = 0.2 mAl PAO-PA7, PBO-PB7, PCO-PC7, TCMP, PD5
(leoo. = 0.4 mAl PD1-PD4
Output Low Voltage
(I Loa• = 0.4 mAl PAO-PA7, PBO-PB7. PCO-PC7, PD2-PD5. TCMP

Min

-

Typ

-

Max

Unit

0.1

V
V

VOL
VOH

Voo-0.1

-

VOH
VOH

Voo-0.3
Voo-0.3

-

-

V
V

0.3

V

Voo

V

0.2 X Voo

V

-

-

mo, RESET, OSC1

V'H

0.7 x Voo

-

Input Low Voltage
PAO-PA7, PBO-PB7, PCO-PC7, PDO-PD5, PD7, TCAP, IRQ, RESET, OSC1

V'L

Vss

-

100

-

1
0.5
1

2.5
1.4
175

mA
mA
IlA

-

1.1
0.6
100

2.75
1.8
275

mA
mA
IlA

Input High Voltage
PAO-PA7, PBO-PB7, PCO-PC7, PDO-PD5, PD7, TCAP,

Total Supply Current (CL = 50 pF on Ports, no dc Loads, tc,c = 1000 ns,
(V'L = 0.2 V, V'H = Voo - 0.2V) No external timer oscillator.
RUN
WAIT (See Note)
STOP (See Note)
Total Supply Current (CL = 50 pF on Ports, no dc Loads, tc,c = 1000 ns,
(V'L = 0.2 V, V'H = Voo - 0.2V) 32.768 KHz external timer
crystal oscillator circuit as shown in Fig. 13(c) ..
RUN
WAIT (See Note)
STOP (See Note)

VOL

100
100

100
100

-

-

-

100

-

I/O Ports Hi-Z Leakage Current
PAO-PA7, PBO-PB7, PCO-PC7, PD1-PD5

hL

-

-

±10

IlA

In~Ws1trent
, ma, TCAP,

lin

-

-

±1

IlA

-

-

12
8

pF
pF

OSC1, PDO, PD7

Capacitance
~Erts as input or output)
SE ,iFill, TCAP, OSC1, PDO-PD5, PD7

t

Cout
Cin

NOTE: Measured under the following conditions:
1. All ports are configured as input, V'L = 0.2 V, V'H = Voo - 0.2 V.
2. No load on TCMP, CL = 20 pF on OSC2.
3. OSC1 is a square wave with V'L = 0.2 V, V'H = Voo - 0.2 V.
4. SPE= 0
5. Typical values at midpoint of voltage range, +250 C only.

2-114

CDP68HC05D2
CONTROL TIMING (Voo = 5.0 Vdc ± 10%, Vss = 0 Vdc, TA = -40°C to +125°C)
Limits
Characteristic

Symbol

Frequency of Operation
Crystal Option
External Clock Option
Internal Operating Frequency
Crystal (fo•c -;- 2)
External Clock (fo•c -;- 2)

Min

Max

Unit

f08C

-

f08C

dc

4.2
4.2

MHz
MHz

fop
fop

dc

2.1
2.1

MHz
MHz

tcyc

480

-

ns

-

100

ms

t.LCH

-

100

tRL

1.5

-

4.0
125

-

Cycle Time (See Figure 8)
Crystal Oscillator Startup Time for At-Cut Crystal (See Figure 8)

toxov

Stop Recovery Startup Time (At-Cut Crystal Oscillator) (See Figure 25)
RESET Pulse Width (See Figure 9)
Timer
Resolution"
Input Capture Pulse Width (See Figure 26)
Input Capture Pulse Period (See Figure 26)

-

tRESL

Interrupt Pulse Width Low (Edge-Triggered) (See Figure 11)

t.LlH

Interrupt Pulse Period (See Figure 11)

t.LlL

...
.

tOH, tOL

90

\rH, hL
\rLTL

OSC1 Pulse Width
External Timer Oscillator frequency of operation

ftosc

125

-

f05C

ms
tCYC

tCYC

ns
tcyc

ns
tcyC

ns

-+- 4

fose

'The minimum period t. L•L should not be less than the number of cycle times it takes to execute the interrupt service
routine plus 21 tcyc.
"Since a 2-bit prescaler in the timer must count four internal cycles (tCyc), this is the limiting minimum factor in
determining the timer resolution.
"'The minimum period hLTL should not be less than the number of cycle times it takes to execute the capture interrupt
service routine plus 24 tcyc.

o""~/&7L17~fl
tRL

RESET

~------tILCH

INTERNAL
CLOCK

RESET OR INTERUPT

NOTES:
t. REPRESENTS THE INTERNAL GATING OF THE OSCI PIN.
2. IRQ PIN EDGE-SENSITIVE MASK OPTION.
3. IRQ PIN LEVEL AND EDGE-SENSITIVE MASK OPTION.
4. REm VECTOR ADDRESS SHOWN FOR TIMING EXAMPLE.

V ECTOR FETCH

92CM-39375

Fig. 25 - Stop Recovery Timing Diagram
2-115

CDP68HC05D2

CONTROL TIMING (Voo

= 3.0 Vdc ± 10%,

Vss

= 0 Vdc,

TA

= -40°C to +125°C)
Limits

Characteristic

Symbol

Frequency of Operation
Crystal Option
External Clock Option
Internal Operating Frequency
Crystal (f05C 7 2)
External Clock (f05c 7 2)

Min

fose

-

fose

dc

fop
fop

dc

teye

1000

-

Max

Unit

2.0
2.0

MHz
MHz

1.0
1.0

MHz
MHz

-

ns

-

100

ms

tAL

1.5

-

teye

tRESL

4.0
250

-

teye

hH, hL
tTLTL

"*

-

teye

Interrupt Pulse Width Low (Edge-Triggered) (See Figure 11)

tlLlH

250

-

ns

Interrupt Pulse Period (See Figure 11)

tlLlL

teye

200

-

Cycle Time (See Figure 8)
Crystal Oscillator Startup Time for At-Cut Crystal (See Figure 8)

toxov

Stop Recovery Startup Time (At-Cut Crystal Oscillator) (See Figure 25)

t'LCH

RESET Pulse Width - Excluding Power-Up (See Figure 8)
Timer
Resolution"
Input Capture Pulse Width (See Figure 26)
Input Capture Pulse Period (See Figure 26)

OSC1 Pulse Width

to H ,

External timer oscillator frequency of operation

tOl

1t05C

,

-

100

fose -;-

ms

ns

ns

4

fose

'The minimum period t'LIL should not be less than the number of cycle times it takes to execute the interrupt service
routine plus 21 tCyc.
"Since a 2-bit prescaler in the timer must count four internal cycles (tCyc). this is the limiting minimum factor in
determining the timer resolution.
"'The minimum period hLTl should not be less than the number of cycle times it takes to execute the capture interrupt
service routine plus 24 tcyc.

EXTERNAL

j.-ITLTL--.j

~~~~~~"'--""";I

I

L

",1___
92CS -39382

Fig. 26 - Timer Relationships

2-116

CDP68HC05D2

SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 29)
(Voo = 5.0 Vdc ± 10%, Vss = 0 Vdc, TA = -40°C to +125°C)
Limits
Num.

Characteristic

Operating Frequency
Master
Slave

1

2

3

4

5

6

7

Unit

fOPlmJ

de
de

0.5
2.1

MHz

2.0
480

-

tCYClrnl

Enable Lead Time
Master
Slave

tleadlml

teYelS)

t1ag(ml

.
.

tlag(S)

240

tleadlSI

Enable Lag Time
Master
Slave

ns

ns
ns

340
190

-

ns
ns

100
100

-

ns
ns

100
100

-

this)

ns
ns

t.

0

120

ns

-

240

ns

0.25
-

240

0.25
0

-

twlSCKLlm

twlSCKUs

Data Setup Time (Inputs)
Master
Slave

tsulml

Data Hold Time (Inputs)
Master
Slave

thlml

tsulsl

tdis

tvlml
tvls)

Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)

-

ns

-

Clock (SCK) Low Time
Master
Slave

Data Valid
Master (Before Capture Edge)
Slave (After Enable Edge)*'

-

tcye

340
190

twlSCKHJs

10

-

op

ns

tw(SCKHlm

Disable Time (Hold Time to High-Impedance State)
Slave

240

-

f ...

-

Clock (SCK) High Time
Master
Slave

9

13

Max

Cycle Time
Master
Slave

Access Time (Time to data active from high impedance state)
Slave

12

Min

, fOPISI

8

11

Symbol

tholml
tholsl

-

-

tCVClmJ

ns
tCYCfml

ns

Rise Time (20% Voo to 70% Voo, CL = 200 pF)
SPI Outputs (SCK, MOSI, MIS0Js
SPI Inputs (SCK, MOSI, MISO,
)

t,m
t",

-

100
2.0

jlS

Fall Time (70% Voo to 20% Vr;JD, CL = 200 pF)
SPI Outputs (SCK, MOSI, MISO)
SPI Inputs (SCK, MOSI, MISO, gs)

I'm
tts

-

100
2.0

jlS

'Signal production depends on software .
•• Assumes 200 pF load on all SPI pins.
"'Note that the unit this specification uses is fop (internal operating frequency), not MHz! In the master
mode the SPI bus is capable of running at one-half ofthe device's internal operating frequency, therefore
1.05 MHz maximum.

2-117

ns

ns

~

:!o
....a:
z

oCo)
o
a:
Co)

1:i

CDP68HC05D2

SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 29)
(Voo = 3.3 Vdc ± 10%, Vss = 0 Vdc, TA = -40°C to +125°C)
Limits
Num.

1

2

3

4

5

6

7

Characteristic
Operating Frequency
Master
Slave

Symbol

dc
dc

0.5
1.0

op
MHz

2.0
1.0

-

500

-

ns

500

-

ns

720
400

-

jlS

-

ns

720
400

-

jlS

-

ns

tauls)

200
200

-

ns
ns

thlm'
thIs'

200
200

-

-

ns
ns

t.

0

250

ns

-

500

ns

Cycle Time
Master
Slave

tCYClm)

Enable Lead Time
Master
Slave

tleadlmJ

!cYCIS'

tleadfSJ

Enable Lag Time
Master
Slave

t1ag(mJ
tleglS)

Clock (SCK) High Time
Master
Slave

tw(SCKHlm

Clock (SCK) Low Time
. Master
Slave

tw(SCKUm

tw(SCKH)s

twlSCKlJs

Data Setup Time (Inputs)
Master
Slave

tsufmJ

Data Hold Time (Inputs)
Master
Slave

9

Disable Time (Hold Time to High-Impedance State)
Slave

10

Data Valid
Master (Before Capture Edge)
Slave (After Enable Edge)"

13

Unit

foPls•

Access Time (Time to data active from high impedance state)
Slave

12

Max

fOPlml

8

11

Min

tdis

tvlml
tv(s)

Data Hold Time (Outputs)
Master (After Capture Edge)
• Slave (After Enable Edge)

tholm)
tholS)

.
.

0.25

-

-

500

0.25
0

-

-

Rise Time (20% Voo to 70% Voo, C L = 200 pF)
SPI Outputs (SCK, MOSI, MISO~
SPI Inputs (SCK, MOSI, MISO,
)

t,m
trs

-

200
2.0

Fall Time (70% Voo to 20% Voo, C L = 200 pF)
SPI Outputs (SCK, MOSI, MISO)
SPI Inputs (SCK, MOSI, MISO, SS)

t.m
tis

-

200
2.0

-

f···

tCYC

/IS

tCYClmJ

ns
tCYClml

'Signal production depends on software .
•• Assumes 200 pF load on all SPI pins.
"'Note that the unit this specification uses is fop (internal operating frequency), not MHzlin the master
mode the SPI bus is capable of running at one-half ofthe device's internal operating frequency, therefore
0.5 MHz maximum.

2-118

ns
ns
jlS

ns
jlS

CDP68HC05D2

HELD HIGH ON MASTER

SS
(INPUT)

SCK
lOUTPUT)

MISO
(INPUT)

001

MOSI
lOUTPUT)

000

(a) SPI Master Timing CPOL

S9
(INPUT)

= 0, CPHA = 1

92CM -39312

HELO HIGH ON MASTER

SCK
lOUTPUT}

MISO
\INPUT)

DOl

MOS!'
I OUTPUT)

000

(b) SPI Master Timing CPOL

= 1, CPHA = 1

NOTE: MEASUREMENT POINTS ARE VOL'VOH'VIL 'VIH

Fig. 27 - Timing Diagrams

2-119

92CM-39372

CDP68HC05D2

is

HELD HIGHONMASTER

(INPUT)

SCK
(OUTPUT)

MISO
(INPUT)

MOSI
\OUTPUT)

(c) SPI Master Timing CPOL

== 0, CPHA == 0

(d) SPI Master Timing CPOL

== 1, CPHA == 0

92CM-39372

SCK
\ OUTPUT)

MISO
liN PUT)

MOSI

\OUTPUT)

92CIoI- 39372

Fig. 27 - Timing Diagrams (Continued)

2-120

CDP68HC05D2

IT
( INPUT)

SCK
!INPUT)

001

92CM-39372

(e) SPI Slave Timing CPOL

en

a:
~

= 0, CPHA = 1

....

o
a:

I-

Z

oy

o
a:
y

:is

IT
(INPUT)

SC K
(INPUT)

MISO
(OUTPUT)

MOS I
(INPUT)

(f) SPI Slave Timing CPOL

= 1, CPHA = 1
92CM-39312

NOTE: MEASUREMENT POINTS ARE VOL' VOH'V I

L'

AND VIM"

Fig. 27 - Timing Diagrams (Continued)

2-121

CDP68HC05D2

55
IINPUT)

SCK
(INPUT)

---t-----=~

MISO

HIGH-Z

000

(OUTOUTI

MOSI
(INPUT)

001

(g) SPI Slave Timing CPOL

= 0, CPHA = 0

n

IINPUT)

SCK
\INPUT)

M ISO
(OUTPUT)

MOSI
\INPUT)

'--~:.L....:.J r-+t---:--:::----'
(h) SPI Slave Timing CPOL = 1, CPHA = 0

92CM-39372

NOTE: MEASUREMENT POINTS AilE VOL 'VOH,V IL ANDV IH

Fig. 27 - Timing Diagrams (Concluded)

2-122

CDP68HC05J3

mHARRIS
PRELIMINARY

8-Bit Microcontroller

January 1991

Hardware Features

Description

• Standard 8-Bit Architecture
• On-Chip Memory
~ ROM •••••...•••....•....•....•..••... 2,352 Bytes
~ RAM •••.••••.•••••.••••..•••..•••.•..• 128 Bytes
• 12 Bidirectional 1/0 Lines
~ 8 Software Programmable As Open Drain
~ 4 Interruptable Inputs
• 16-Bit, Free Running Timer
~ Output Compare
~ Input Capture
~ Separate Timer Oscillator Allows Timing During
Power Saving Modes
• HCMOS Technology
• Fully Static with Power Saving WAIT, STOP, and Data
Retention Modes
• Operating Range .•••.••••••.••••• -400 C to +125 0 C
• Operation •••..•••...••....•.•.•.......•. 3V to 5.5V
• Data Retention ••••••••.••.••••..••••.•.••.••.••. 2V
• 4.2MHz Crystal - 2.1 MHz CPU Clock
• Supplied in 20 Lead DIP or 20 Lead Small Outline
Packages

The CDP68HCOSJ3 is a member of the CDP68HCOS family
of 8-bit, HCMOS microcontrollers. This single chip
microcontroller contains 2,3S2 bytes of masked ROM, 128
bytes of RAM, a flexible l6-bit timer with input capture and
output compare features, 12 bidirectional I/Os (eight programmable as open drain and four interruptable), an on chip
oscillator, and an optional, independent oscillator for the
timer. The timer can be used for pulse width measurements,
timing, or event counting. Optionally, the timer can run off
an oscillator that is independent of and typically at a lower
frequency than the CPU oscillator. The dedicated timer
oscillator allows timekeeping functions to be maintained
during the low power STOP mode. In conjunction with the
open drain outputs, the four interruptable port lines can be
used for switch scanning. The interruptable port lines
provide additional external interrupts for systems requiring
additional interrupts and can be used to exit the power down
modes.

Software Features

The CDP68HCOSJ3 is supplied in a 20 lead dual-in-line
plastic package (E suffix) and in a 20 lead small outline
plastic package (M suffix).

• Supports Full CDP68HC05 Instruction Set
~ 8x8 Multiply
~ Bit Set, Clear, and Test

Pinout

The CDP68HCOSJ3 supports the full CDP68HCOS instruction set. Development can be performed with tools supplied
by Harris or offered by numerous third party vendors. Available tools include assemblers, C compilers, and ICE
systems.

Block Diagram

PACKAGE TYPES E AND M
TOP VIEW

OSC1

TCMPIT0SC2

OSC2

RESET
IRQ

PORT
A

I/O
UNES

ACCUMULATOR

PM
PA1
PA2
PA3
PM
PAS

8
DATA
DIR
REG

PAS
PA7

A

8

INDEX
REGISTER

5

CONDITION
CODE
REGISTER

cc

STACK

PAG
PORT
B

110
UNES

POO
PB1
PB2
PB3

PORT
B
REG

DATA
DIR
REG

CPU
CONTROl.

X

6

POINTER SP

4

PROGRAM
COUNTER
HIGH PCH

8

PROGRAM
COUNTER
LOW PCl

CPU

AW

2112x8
ROM

240.8
SELF ·ClECK
ROM

Copyright

© Harris Corporation 1991

File Number
2-123

2757

CDP68HC05J3

0000

$()()()()

PORTS
7 BYTES

110
32 BYTES
$OOlF
$0020
$OO4F

USER ROM
48 BYTES

$005()

UNUSED
48 BYTES

0031
0032
0079

UNUSED
11 BYTES

\
\

ooeo

\
\

RAM
128 BYTES

$OOBF
$OOCO

l-

TIMER
10 BYTES

\
0127
0128

$007F
$0080

\

UNUSED
4 BYTES

0031

0191
0192

\

STACK -

\

64 BYTES

$ooFF
$0100

$08FF
$0900
$OEFF
$OFoo
$OFDF
$OFEO

USER
ROM
2048 BYTES
UNUSED

$OFFF

\
\

2303
2304

\
\

3640
/$OFFO

/

4063

4064
SELF -CHECK
VECTORS
16 BYTES

$OFEF
$OFFO

\

0255
0256

3839

SELF -CHECK
ROM
224 BYTES

/

/
4079

USER
VECTORS
BYTES

PORT A DATA REGISTER
PORT B DATA REGISTER
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT A OPEN DRAIN REGISTER
PORT B INTERRUPT ENABLE REGISTER
PORT B INTERRUPT FLAG REGISTER
UNUSED
10 BYTES
OSCILLATOR CONTROL REGISTER

0000

$OFF6

PORT B VECTOR

$OFF8

TIMER VECTOR

$OFFA

IRQ VECTOR

$OFFC

SWI VECTOR

$OFFE

RESET VECTOR

4080
4095
--

UNUSED
6 BYTES

TIMER STATUS REGISTER

$13

INPUT CAPTURE HIGH REGISTER

$14

:

INPUT CAPTURE LOW REGISTER

$15

OUTPUT COMPARE HIGH REGISTER

$16

OUTPUT COMPARE LOW REGISTER

$17

COUNTER HIGH REGISTER

$18

COUNTER LOW REGISTER

$19

ALTERNATE COUNTER HIGH REGISTER

$lA

ALTERNATE COUNTER LOW REGISTER

$lB

$lC
UNUSED
~___________4
__
B_YT_E_S__________~J$lF

\1

-

CDP68HC05J3 ADDRESS MAP

2-124

TIMER CONTROL REGISTER

$00
$01
$02
$03
$04
$05
$06
$07
$10
$11
$12

CDP68HC05W4

9)HARRIS
PRELIMINARY

8-Bit Microcontroller

January 1991

Hardware Features

Description

• Standard 8-bit Architecture
• On Chip Memory
~ ROM •••••••••••••.••••.•••.•••.•••••. 3,866 bytes
~ RAM ••••••••••••••••••••••••••••••••••• 192 bytes
• Two 8-Bit Pulse Width Modulators
• 24 Bidirectional I/O Lines
~ 8 with Data Transfer Handshaking
~ 4 Interruptable Inputs
• Synchronous Serial Port (SPI)
• Programmable 8-Bit Timer with 7-Bit Prescaler
• Computer Operating Properly (COP) Circuitry
~ Watchdog nmer
~ Slow Clock Detect
~ Illegal Opcode Trap

The CDP68HC05W4 is a member of the Harris CDP68HC05
family of 8-bit, HCMOS microcontrollers. This single chip
microcontroller contains 3,866 bytes of masked ROM, 192
bytes of RAM, two pulse width modulators, an 8-bit timer, a
synchronous serial (SPI) port, 24 bidirectional II0s (8 with
data transfer handshaking), six external interrupts, a
computer operating properly (COP) Circuitry, an on chip
OSCillator, and a built in prototyping mode. The PWMs can
be used as 8-bit 0 to A converters, speed controllers, or
tone generators. The timer with 7-bit prescaler can be used
for pulse width measurements, timing, or event counting.
InterfaCing to external serial peripherals is easy with the SPI
port. The interruptable VPORT C can be used for switch
scanning or to exit the power down modes. The COP
circuitry provides a level of failsafe system security.

• HCMOS Technology
• Fully Static with Power Saving WAIT, STOP, and Data
Retention Modes
• Supplied in 40 Pin DIP or 44 Pin PLCC & QFP Packages
• Operating Range •••.•••••••••.••• -400 C to +12S 0 C
• Operation. • . . • • • . • • • • . . • • • • • • • . . • • • .• +3V to +S.SV
• Data Retention .•..•••..•••••••..••..•.••....••.. 2V

The CDP68HC05W4 supports the full CDP68HC05
instruction set. Development can be performed with tools
supplied by Harris or offered by numerous third party
vendors. Available tools include assemblers, C compilers,
and ICE systems. The prototyping mode facilitates bread·
boarding.
The CDP68HC05W4 is supplied in a 40 lead dual-in-Iine
plastiC package (E suffix), a 44 lead plastiC leaded chip carri·
er (N suffix), and a 44 lead metric quad fiatpack (O suffix).

Software Features
• Supports Full CDP68HCOS Instruction Set
~ 8x8 Multiply
~ Bit Set, Clear, and Test

Block Diagram

Pinout
PACKAGE TYPE E
TOP VIEW

OSCI

PCO

VDD

PCI

TIN

NMI
r~========: MODE

ACCUMULATOR

8

CNTLB
DATA

POI

DlR

8

REG

P02

8

MOSI

OSCI

RESET

PAD

IRQI

PBO

PA2

PBI

PA3

PB2

PM

PB3

PAS

PB4

PAS

PBS

PA7

PB8

VSS

PBT

DtR

REG

REGISTER

I-~V~PORr~~C~1--~- :;LA

co

STACK
POINTER SP

VPORT _PC2
C
_PCa PORT
REG
_PC4
C
_PC6 1,0
PCB UNES

CPU

CONTROL

CNTL B

PROGRAM
8

PORT

PAl

DATA
X

CONDfT1ON

5

MISO

_PCI

A

INDEX

REGISTER

CODE

SCI<

MODE

r;::========
r--..,..---,_pco

RESET
IRQl

CNTLA

OSC2

0SC2

DATA

B

DIR

REG

REG

COUNrER
HIGH PCH

AW

PROGRAM
COUNTER

LOW

Pel
POI

P02

Copyright @ Harris Corporation 1991

File Number
2-125

2761

CDP68HC05W4

$0000

LQ

0000

PORTS

0063
0064

$OO3F
$0040
RAM
192 BYTES

$OOBF
$OOCO
$OOFF

-r

0191
0192
STACK 64 BYTES

SOl00

0255
0256

USER
ROM
3840 BYrES
$lFFF

4095

$2000

4096
UNUSED
4070 BYTES

$3FE5
$3FE6

$3FFF

USER
VECTORS
26 BYrES

0000

4 BYTES

64 BYTES

8165
8188

CPU

REGISTERS
4 BYTES

\
\
\
\
\
\
\
\

UNUSED
2 BYTES

$OO3F

SOl
$02

$03
$04
$05

COP RESET REGISTER
OPTION REGISTER
UNUSED
UNUSED
SERIAl PEmPHERAL CONTROL REGISTER

$08
$J11
$08
$09
$OA

UNUSED
9 BYTES

SERIAL PERIPHERAL STATUS REGISTER
SERIAl PERIPHERAL DATA LC REGISTER

SOB
SOC

TIMER

UNUSED

3 BYTES

\
\
\
\
\

$00

LQ INTERRUPT ENABLE REGISTER

SERIAl
PERIPHERAL
INTERFACE
3 BYTES

\
\

PORT A DATA REGISTER
PORT B DATA REGISTER
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
LQ INTERRUPT FLAG REGISTER

TIMER CONTROL REGISTER
TIMER RELOAD REGISTER

UNUSED

TIMER COUNTER REGISTER
UNUSED
.p PWMl.PRESCALE REGISTER
PWMI CONTROL REGISTER

PWM
8 BYTES
UNUSED

PWMI FREQUENCY REGISTER

TlMEIWWM

PWMI WIDTH REGISTER

V PORT C
4 BYTES

PWM2 FREQUENCY REGISTER
PWM2 PRESCALE REGISTER
PWM2 CONTROL REGISTER

UNUSED
24 BYrES

0063

8191

$17
$18
$19
$lA
$lB
$lC
$10
$lE
$lF

$20
$21

TIMEIWWM STATUS REGISTER

$23

V PORT C DATA REGISTER
V PORT C DATA DIRECTIOIOOONTROL2 REG

$24
$25

V PORT C CONTROLI REGISTER

$28
$27
$28
$3F

UNUSED

2-126

$15
$18

PWM2 WIDTH REGISTER
UNUSED

V PORT C STATUS REGISTER

CDPS8HCOSW4 ADDRESS MAP

$00

$22

CDP6805F2
CDP6805F2C

mHARRIS

CMOS High Performance Silicon Gate
a-Bit Microcontroller

January 1991

Pinout

Hardware Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Typical Full Speed Operating Power @ 5V •••••••••••••••.••. 10mW
Typical WAIT Mode Power .•••••••••••••••••.••..•••••••••••• 3mW
Typical STOP Mode Power ••..•••.••••••.•.•..•••.•••••••••••• 51lW
64 Bytes of On-Chip RAM
1089 Bytes of On-Chip ROM
16 BidirectionalI/O Lines
4 Input-Only Lines
Internal 8-Blt Timer With Software Programmable 7-Blt Prescaler
External Timer Input
External and Timer Interrupts
Master Reset and Power-On Reset
Single 3V to 6V Supply
On-Chip Oscillator
11ls Cycle Time

PACKAGE TYPES D AND E
TOP VIEW
RESET

YRll"

28
27

voo
peo

TIMER

NUM

3

26
25
24

PCt
PC2

23
22
21

PC3
PBO

OSCI

4

OSC2

5

PAO

6
7

PAt

PA4

8
9
10

19

PB3

PA5

II

18

PA6
PA7

12

17

PB4
PB5

13
14

16
15

PA2
PA3

Vss

Description

Software Features

The CDP6805F2 Microcomputer Unit (MCU) belongs to the
CDP6805 Family of CMOS Microcomputers. This 8-bit MCU
contains on-chip oscillator, CPU, RAM, ROM, I/O, and Timer.
Fully static design allows operation at frequencies down to
DC, further reducing its already low-power consumption. It is
a low-power processor designed for low-end to mid-range
applications in the consumer, automotive, industrial, and
communications markets where very low power consumption
constitutes an important factor.

•
•
•
•
•
•
•

PBt
PB2

20

PB6
PB7

Versatile Interrupt Handling
True Bit Manipulation
10 Addressing Modes
Efficient Instruction Set
Memory-Mapped I/O
User-Callable Self-Check Routines
Two Power-Saving Standby Modes

Block Diagram

PBO
Accumulator
A

B

CPU
Control

Index

. Data
Direction

Register
PAO
Port PAl
PA2
A
PA3
1/0
lines
PA6
PA7

~!~

X

B
Port
A

Condition

Data

Port
8

~~~

Port
PB3 B
PB4 1/0
PB5 Lines
PB6
PB7

Code

irectic

Register

Register Register

CC

CPU

Stack
Pointer

S

Program

Counter
High

B

PCH

AlU

Program
Counter
low
PCl

1089 x B
ROM

92CS-37994

Self-Check

ROM

CDP6805F2 CMOS MICROCOMPUTER
Copyright

e

Harris Corporation 1991

File Number

2-127

1369.1

CDP6805F2, CDP6805F2C
The COP6805F2 and COP6805F2C devices are available in
a 28-lead dual-tn-line plastic package (E suffix), in a 28-lead

dual-in-line ceramic package (0 suffix); and In a 28-lead
plastic chip-carrier package (N suffix).

MAXIMUM RATINGS (Voltages Referenced to VSS)
Ratings

Symbol

Supply Voltage
All Input Voltages Except

Value

ascI

Current Drain per Pin Excluding VDD and VSS

Storage Temperature Range

V

Yin

VSS-0.5 to VDD+0.5

V

I

10

mA

TA

TL to TH
to 70
-40 to +85

°c

Tstg

-55 to + 150

°c

Operating Temperature Range
CDP6805F2
CDP6805F2C

Unit

-0.3 to +8

VDD

o

VDD=4.5V

4.27 k
Test Point
20.5 k

92C8-37995

Fig. 2 - Equivalent test load.

«

E 2.5

I

C'

~

I-

Z

6V
2.0

w
a:
a:

5V

:::l
U

(!)

Z
j::

«
a:

w

II.

0

...J

«

u
1L
>-

I-

INTERNAL FREQUENCY (lItcyc)-MHz

Fig. 3 - Typical operating current VB. internal frequency.

2-128

92C8-37996

CDP6805F~CDP6805F2C
DC ELECTRICAL CHARACTERISTICS IVDD= 51Vdc ± 10% VSS=O Vdc, TA= TL to TH, unless otherwise noted) ISee Note 1)
Characteristics

Symbol

Output Voltage, )Load" 10.0 p.A

VOL
VOH

200 p.A) PAO-PA7, PBO-PB7
Output High Voltage II Load Output Low Voltage, IILoad-800 p.A) PAO-PA7, PBO-PB7
Input High Voltage
Ports PAO-PA7, PBO-PB7, PCO-PC3
TIMER, iRQ, RESET
OSCl

VOH
VOL
VIH

Input Low Voltage, All Inputs

VIL

Total Supply CurrentlCL - 50 pF on Ports, No dc Loads, tcyc= 1 p.s)
RUN IMeasured During Self-Check, VIL = 0.2 V, VIH = VOD - 0.2 VI
WAIT ISee Note 2)
STOP I See Note 21

IDD

liD Ports Input Leakage -

PAO-PA7, PBO-PB7

Max

Unit

0.1
-

V

VDD-2
VDD-O.S
VDD-l.5

VDD
VDD
VDD
0.8

IlL

Input Current - RESIT, T1'm, TIMER, OSC1, PCO-PC3
Output Capacitance - Ports A and B
Input Capacitance -

Min
VDD-O.l
4.1
-

lin
Cnut

RESET, IRQ, TIMER, OSC1, PCO-PC3

Cin

VSS

-

V

0.4

V
V
V

-

4
1.5
150

rnA
rnA
p.A

-

±10

p.A
p.A

-

±1
12

-

8

pF
pF

NOTES'
1 Electrical Characteristics for VOO=3 V available soon.
2. Test Conditions for IOD are as follows:
All ports programmed as inputs
VIL =0.2 V (PAO-PA7, PBO-PB7, PCO-PC31
VIH = VDO-0.2 V for RESET, TAO, TIMER
OSCl input is a square wave from 0.2 V to VDO - 0.2 V
OSC2 output load = 20 pF IWAIT IDD is affected linearly by the OSC2 capacitancel
TABLE 1 -

CI)

a:
...o...
w

a:

I-

:z

oCo)

o
a:
Co)

CONTROL TIMING CHARACTERISTICS IVOO= 5 Vdc ± 10%, VSS=O, TA = h to TH, fosc=4 MHz, tcyc= 1 p.sl
Characteristics

Symbol

Crystal Oscillator Startup Time (See Figure 51
Stop Recovery Startup Time - Crystal Oscillator ISee Figure 61

tOXOV

Min
-

Max

Unit

100

ms

100
-

ms

Timer Pulse Width (See Figure 41

tlLCH
tTH, tTL

Reset Pulse Width ISee Figure 51
Timer Period (~ee Figure 41

tRL
tTLTL

Interrupt Pulse Width (See Figure 151

tiltH

1

-

teye

Interrupt Pulse Period (See Figure 151

tlLtL
tOH, tOL

*
100
1000

-

teyc
ns
ns

dc

4
4

OSCl Pulse Width I See Figure 71
Cycle Time

teye

Frequency of Operation
Crystal
External Clock

fosc

0.5
1.5
1

tcyc
tcyc
tcye

MHz

*The minimum penod, 1jLtL, should not be less than the number of tcyc cycles it takes to execute the interrupt service routines plus 20 tcyc
cycles.

TERMINAL ASSIGNMENT

DSCZ

PCl

PAD

PC2

PA I

PC3

PAZ

PBD

PA3

PBl

PA4

PB2

PA~

PB3

(Q

....

cn,...~IOV

:':':~:f:
92CS-40952

28-Lead Plastic Chip-Carrier Package
(N Suffix)

2-129

~

External
Clock

Timer)
( PIn
27

r

I---

tTL TL-.J

--+l

tTH

I---

-./

tTL

k-

~

92CS-37997

Fig. 4 - Timer relationships.

I

Ir---_ _ __
VDD

Yr
I

i

OSC1

-r ~1\\\\\\\\\\\\\\~\\\\\\\\~\\\\\~\\~\\\~\\\~\\\\\\\\\\
I
I

I

I

I
)01

1920 tcye

10(

~toxOV

f\)
I

k-

~
~

I

I

C1!

teye . ,

~

I

-'

f:l

I

~~I~~~~~~~~ITTI~~~~~~~~

~

<1>2*

~
C)

Internal
Address

C1!

~

Bus*

o

Internal
Data

Bus*

RESET
---./'

f= "'=}

* Internal timing signal not available externally.
Fig. 5 - Power-on RESET and RESEr.

92CS-3799B

CDP6805F~CDP6805F2C

OSC2**

-----~

---r-1

~ IIIIIIIIIII
- - - - - - · ·...
ICt---1920tCyC

V'

; III

----;...,·~I__....

~2* ----------------------~

* Internal timing signals not available externally.
** Repre""nts the internal gating of the ascI input pin.

92C5-37999

Fig. 6 - Stop recovery.

FUNCTIONAL PIN DESCRIPTION

OSC1. OSC2
The CDP6805F2 can be configured to accept either a
crystal input or an RC network. Additionally. the internal
clocks can be derived from either a divide-by-two or divideby-four of the external frequency (fosc!. Both of these options are photomask selectable.

VDD and VSS
Power is supplied to the MCU using these two pins. VDD
is power and VSS is ground.
IRQ (MASKABLE INTERRUPT REQUEST)
IRQ is photomask option selectable with the choice of interrupt sensitivity being both level and negative edge or
negative edge only. The MCU completes the current instruction before it responds to the request. If IRQ is low and the
interrupt mask bit (I bit) in the condition code register is
clear. the MCU begins an interrupt sequence at the end of
the current instruction.
If the photomask option is selected to include level sensitivity. then the IRQ input requires an external resistor to
VDD for "wire-OR" operation. See the Interrupt section for
more detail.

RC - If the RC oscillator option is selected, then a resistor
is connected to the oscillator pins as shown in Figure 7(b!.
The relationship between Rand fosc is shown in Figure 8.
CRYSTAL - The circuit shown in Figure 7(a) is recommended when using a crystal. The internal oscillator is
designed to interface with an AT-cut parallel resonant quartz
crystal resonator in the frequency range specified for fosc in
the electical characteristics table. USing an external CMOS
oscillator is suggested when crystals outside the specified
ranges are to be used. The crystal and components should
be mounted as close as possible to the input pins to minimize
output distortion and start-up stabilization time. Crystal frequency limits are also affected by VDD. Refer to Table 1,
Control Timing Characteristics, for limits.

RESET
The RESET input is not required for start-up but can be
used to reset the MCU's internal state and provide an orderly software start-up procedure. Refer to the Resets section
for a detailed description.

EXTERNAL CLOCK - An external clock should be applied to the OSC1 input with the OSC2 input not connected.
as shown in Figure 7(c!. An external clock may be used with
either the RC or crystal oscillator mask option. toxOV or
tlLCH do not apply when using an external clock input.

TIMER
The TIMER input may be used as an external clock for the
on-chip timer. Refer to the Timer section for a detailed
description.
NUM (NON-USER MODE)
This pin is intended for use in self-check only. User applications should leave this pin connected to ground through
a 10 kilohm resistor.

PAD-PA7
These eight I/O lines comprise Port A. The state of any pin
is software programmable. Refer to the'lnput/Output Programming section for a detailed description.

2-131

CDP6805F2, CDP6805F2C
Crystal Parameters

RSMAX

1 MHz

4 MHz

Units

400

75

0

5

7
0.012
15-30
15-25
10
40k

Co
C,

0.008

COSCl

15-40

COSC2
Rp

15-30
10

Q

Oscillator Waveform

30k

pF
"F
pF
pF
MO
-

(a) Crystal Oscillator Connections and Equivalent Crystal Circuit

CDP6805F2
OSCl
4

OSC2
Rp

5

-5'---------110

4

t - I_ _ _

COSCl

(b)

RC Oscillator Connection

(c) External Clock Source Connections

CDP6805F2
OSCl

CDP6805F2

OSC2

OSCl

OSC2

!5

4

R

Unconnected

'---<,
Fig. 7 - Oscillator connections.

2-132

External Clock

9208-38000

CDP6805F2, CDP6805F2C

'0,

PBO-PB7
These eight lines comprise Port B. The state of any pin is
software programmable. Refer to the Input/Output Programming section for a detailed description.

PCO-PC3
These four lines comprise Port C, a fixed input port. When
Port C is read, the four most-significant bits on the data bus
are "'s" . There is no data direction register associated with
Port C.
INPUT/OUTPUT PROGRAMMING
Any Port A or B pin may be software programmed as an
input or output by the state of the corresponding bit in the
port data direction register (DDR l. A pin is configured as an
output if its corresponding DDR bit is set to a logic "'''. A
pin is configured as an input if its corresponding DDR bit is
cleared to a logic "0". At reset, all DDRs are cleared, which
configures all port pins as inputs. A port pin configured as an
output will output the data in the corresponding bit of its
port data latch. Refer to Figure 9 and Table 2.

0.01
468

10

468

100
RESISTANCE(K.n)

•

•

8

1000

9ZCS-42274

R (kO)
Fig. 8 - Typical frequency vs. resistance
for RC oscillator option only.

la!

Internal
CDP6805F2

Connections

Ib!
Typical Port
Data Direction
Register
Typical Port
Register

Pin

P-7

P-6

P-5

P-4

P-3

Fig. 9 - Typical I/O port circuitry.

P-2

P-l

P-O
92CS.{l8001

TABLE 2 - 110 PIN FUNCTIONS

R/W
0
0
1
1

DDR

0
1
0
1

110 Pin Function
The 110 pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch and output to the 110 pin.
The state of the I/O Pin is read.
The 110 pin is in an output mode. The output data latch is read.

2-133

CDP6805F2, CDP6805F2C
The RAM test must be called with the stack pointer at $7F
and the accumulator zeroed. When run, the test checks
every RAM cell except for $7F and $7E which are aSSl!lmed to
contain the return address.
A and X are modified. All RAM locations except the top 2
are modified. (Enter at location $788.1

SELF-CHECK
The CDP6805F2 self-check is performed using the circuit
in Figure 10. Self-check is initiated by tying NUM and TIMER
pins to a logic "I" then executing a reset. After reset, the
following five tests are executed automatically:
1/0 - Functionally Exercise Ports A, B, C
RAM - Walking Bit Test
ROM - Exclusive OR with ODD "Is" Parity Result
Timer - Functionally Exercise Timer
Interrupts - Functionally Exercise External and Timer Interrupts
Self-check results are shown in Table 3. The following
subroutines are available to user programs and do not require any external hardware.

ROM CHECKSUM SUBROUTINE
Returns with Z bit cleared if any error was found; otherwise Z= 1, X=O on return, and A is zero it the test passed.
RAM locations $41-$44 are overwritten. (Enter at location
$7A4.1

TIMER TEST SUBROUTINE
Return with Z bit cleared if any error was found; otherwise
Z=I.
This routine runs a simple test on the timer. In order to
work correctly as a user subroutine, the internal clock must
be the clocking source and interrupts must be disabled.
Also, on exit, the clock will be running and the interrupt
mask will not be set, so the caller must protect himself from
interrupts if necessary.
A and X register contents are lost; this routine counts how
many times the clock counts in 128 cycles. The number of
counts should be a power of two since the prescaler is a
power of two. If not, the timer probably is not counting correctly. The routine also detects if the timer is running at all.
(Enter at location $7BE.I

TABLE 3 - SELF-CHECK RESULTS
Remarks

PB3
1

PB2

PBI
1

PBO

a

t

Bad Timer

1

I
1

a

1

1

0
1
0

Bad RAM

0

1
1

All Cycling
All Others

Bad ROM
Bad Interrupt or Request Flag
Good Part
Bad Part

RAM SELF-CHECK SUBROUTINE
Returns with the Z bit clear if any error is detected; otherwise, the Z bit is set.

.
>:

+5 V +5 V
10 k

+5V +5V

!I: ~ > 10 k

$,10 k

•

1

16:1
-ci

2

Voo

RESET
IRQ

TIMER

!.......1

NUM

PCO

XTAL...!

ascI

PCl

XTAL..2 OSC2

PC2

~

7

8
9

~
~
12
13
GNO.2!

PAO

PC3

~
27

~
~ I24
23

PA2

PBl

~
~ I-

PA3

PB2

20

PM

PB3

PAl

CDP6805F2

PBO

PA5

PB4

PA6

PB5

PA7

PB6

VSS

PB7

19
18
17
16

} 'w Sm" ,,,.,,,..

15
92CS-38OO2

Fig. 10 - Self-check pinout configuration.

2-134

CDP6805F2, CDP6805F2C
MEMORY

The stack pointer is used to address data stored on the
stack. Data is stored on the stack during interrupts and
subroutine calls. At power-up. the stack pointer is set to $7F
and it is decremented as data is pushed on the stack. When
data is removed from the stack. the stack pointer is incremented. A maximum of 32 bytes of RAM are available for
stack usage. Since most programs use only a small part of
the allocated stack locations for interrupts and/ or subroutine
stacking purposes. the unused bytes are available for program data storage.

The CDP6805F2 has a total address space of 2048 bytes
of memory and 110 registers. The address space is shown in
Figure 11.
The first 128 bytes of memory (first half of page zero) is
comprised of the I/O port locations. timer locations. and 64
bytes of RAM. The next 1079 bytes comprise the user ROM.
The 10 highest address bytes contain the reset and interrupt
vectors.

$()()()()
Access
[
Via
Page 0
Direct
Addressing

0

1/0 Ports

0

Timer
RAM

127
128

$007F

2

$0060

3

255
256

$ooFF
$0100

I
1079 Bytes
User ROM

1206
1207
1279
1280

2037
2038
User
Defined
Interrupt
Vectors

[

SWI

* Reads of unused locations undefined

4

Port A Data Direction Register

$0004

5

Port B Data Direction Register

$0005

6

Unused *

$0006

7

Unused *

$0007

8

Timer Data Register

$0008

9

Timer Control Register

$0009
$oooA

$003F
$0040

63

$077F
$0780

95

96

$07F5

-

$005F

,/

$07F6 $07F7

,

,-

$07F8 $07F9

;"

;"
;"

+
92C5-38003

Fig. 11 - Addrsss map.

2-135

'"

;" ;" Stack 132 Bytes Max)

$07FC $07FD
$07FE $07FF
L
127

/

/ / $0060

/

$07FA$07F8
I

RESET

.......,....,
CI')

$0003

RAM
164 8ytes)

f----------Timer Interrupt
f----

1--- - -

$0002

64

1------------Timer Interrupt From Wait State Only

2047

Port C

Unused *

54 Bytes
Unused*

$04FF
$0500

118 Bytes
Self-Check ROM

External Interrupt

I

1 1 1 1

10

$0486
$04B7

73 Bytes
Self-Check ROM

~---

$()()()()
$0001

II:
Q

....
z

II:

Q

Co)

Q

6408ytes
Unused*
1919
1920

Port A Data Register
Port 8 Data Register

$007F

II:

Co)

iii

CDP6805F2, CDP6805F2C
PROGRAM COUNTER (PC)

REGISTERS

The program counter is an 11-bit register that contains the
address of the next instruction to be executed by the processor.

The CDP6805F2 contains five registers as shown in the
programming model (Figure 12), The interrupt stacking order
is shown in Figure 13.

STACK POINTER (SP)
The stack pointer is an 11-bit register containing the address of the next free location on the stack. When accessing
memory, the six most-significant bits are appended to the
five least-significant register bits to produce an address
within the range of $7F to $60. The stack area of RAM is
used to store the return address on subroutine calls and the
machine state during interrupts. During external or power-on
reset, and during a "reset stack pointer" instruction, the
stack pointer is set to its upper limit ($7FI. Nested interrupts
and! or subroutines may use up to 32 (decimal) locations
beyond which the stack pointer "wraps around" and points
to its upper limit thereby lOSing the previously stored information. A subroutine call occupies two RAM bytes on the
stack, while an interrupt uses five bytes.

ACCUMULATOR (A)
This accumulator is an a-bit general purpose register used
to hold operands and results of the arithmetic calculations
and data manipulations.

INDEX REGISTER (X)
The X register is an a-bit register which is used during the
indexed modes of addressing. It provides the a-bit operand
which is used to create an effective address. The index
register is also used for data manipulations with the readmodify-write type of instructions and as a temporary storage
register when not performing addressing operations.

0

7

I

A

I Accumulator

0

7

I

10

X

I

Index Register

I

Program Counter

0

I

PC

10
5 4
1 0 10 1 0 I 0 I 11 I

0
SP

I Stack Pointer
Condition Code Register
Carry I Borrow
Zero
' - - - - - Negative

' - - - - - - - Interrupt Mask
Half Carry

L...._ _ _ _ _ _

92C5-38004

Fig. 12 - Programming modal.

o

7
1

11 11 1 Cond.i.tion Code Register
Accumulator

Increasing Memory
Addresses

n

Decreasing Memory
Addresses

Index Register

0101010101

Stack

PCH

PCl
Unstack

T

NOTE: Since the Stack Pointer decrements during pushes. the PCl is
stacked first. followed by PCH, etc. Pulling frQm the stack is in
the reverse order.

Fig. 13 - Stacking order.

2-136

92CS-38005

CDP6805F2 CDP6805F2C
1

CONDITION CODE REGISTER (CCI

for a power-down reset. The power-on circuitry provides for
a 1920 tcyc delay from the time of the first oscillator operation. If the external RESET pin is low at the end of the '920
time out, the processor remains in the reset condition.
Either of the two types of reset conditions causes the
following to occur:
• Timer control register interrupt request bit (TCR7) is
cleared to a "0".
• Timer control register interrupt mask bit (TCRS) is set
to a"'''.
• All data direction register bits are cleared to a "0". All
ports are defined as inputs.
• Stack pointer is set to $7F.
• The internal address bus is forced to the reset vector
($7FE, $7FFI.
• Condition code register interrupt mask bit (I) is set to a

The condition code register is a 5-bit register which indicates the results of the instruction just executed. These
bits can be individually tested by a program and specific action taken as a result of their state. Each bit is explained in
the following paragraphs.

HALF CARRY BIT (HI - The H bit is set to a "'" when a
carry occurs between bits 3 and 4 of the ALU during an ADD
or ADC instruction. The H bit is useful in binary coded
decimal subroutines.
INTERRUPT MASK BIT (I) - When the I bit is set, both
the external interrupt and the timer interrupt are disabled.
Clearing this bit enables the above interrupts. If an interrupt
occurs while the I bit is set, the interrupt is latched and is
processed when the I bit is next cleared.

"'' .

• STOP and WAIT latches are reset.
• External interrupt latch is reset.
All other functions, such as other registers !including output ports), the timer, etc., are not cleared by the reset conditions.

NEGATIVE (NI -

Indicates that the result of the last
arithmetic, logical, or data manipulation is negative (bit 7 in
the result is a logical "'''1.

ZERO (ZI - Indicates that the result of the last arithmetic,
logical, or data manipulation is zero.

INTERRUPTS

CARRY IBORROW (CI - Indicates that a carry or borrow
out of the arithmetic logic unit (ALUI occurred during the
last arithmetic operation. This bit is also affected during bit
test and branch instructions, shifts, and rotates.

Systems often require that normal processing be interrupted so that some external event may be serviced. The
CDP6805F2· may be interrupted by one of three different
methods, either one of two maskable interrupts (external input or timer) or a non-maskable software interrupt (SWII.
Interrupts cause the processor registers to be saved on the
stack and the interrupt mask set to prevent additional interrupts. The RTI instruction causes the register contents to be
recovered from the stack and return to normal processing.
The stacking order is shown in Figure '3.
Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered
pending until the current instruction execution is complete.
When the current instruction is complete, the processor
checks all pending hardware interrupts and if unmasked,
proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Note that masked interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed as any other instruction. Refer to Figure'4 for the interrupt and instruction
processing sequence.

RESETS
The CDP6805F2 has two reset modes: an active low external reset pin (RESET) and a power-on reset function; refer
to Figure 5.

RESET
The RESET input pin is used to reset the MCU to provide
an orderly software start-up procedure. When using the external reset mode, the RESET pin must stay low for a
minimum of one tRL. The RESET pin is provided with a
Schmitt Trigger input to improve its noise immunity.

POWER-ON RESET
The power-on reset occurs when a positive transition is
detected on VDD. The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any drops in the power supply voltage. There is no provision

2-137

CDP6805F2, CDP6805F2C
TIMER INTERRUPT
Each time the timer decrements to zero (transitions from
$01 to $(0), the timer interrupt request bit (TCR7) is set. The
processor is interrupted only if the timer mask bit (TCR6) and
interrupt mask bit (I bit) are both cleared. When the interrupt
is recognized, the current state of the machine is pushed onto the stack and the interrupt mask bit in the condition code
register is set. This mask prevents further interrupts until the
present one is serviced. The processor now vectors to the

timer interrupt service routine. The address for this service
routine is specified by the contents of $7F8 and $7F9 unless
the processor is in a WAIT mode, in which case the contents
of $7F6 and $7F7 specify the timer service routine address.
Software must be used to clear the timer interrupt request
bit (TCR7). At the end of the timer interrupt service routine,
the software normally executes an RTI instruction which
restores the machine state and starts executing the interrupted program.

1-1 Bit (in CCR)
07F-SP
O-DDRs
CLR IRQ Logic
FF-Timer
7F-Prescaler
7F-TCR

lear
IRQ
Request
Latch

Stack
PC,X,A,CC

Timer
Put 7FE on
Address Bus

Load PC From:
SWI: 7FC17FD
IRQ: 7FA17FB
TIMER: 7F817F9
Timer Wait: 7F617F7
Fetch
Instruction

SWI
PC-PC+ 1 I - - - J "
Load PC
from
7FE17FF

Execute All
Instruction
Cycles

9208-$006

Fig. 14 -

RESET and INTERRUPT processing flowchart.

2-138

CDP6805F2, CDP6805F2C
EXTERNAL INTERRUPT
Either level- and edge-sensitive or edge-sensitive only inputs are available as mask options. If the interrupt mask bit
of the condition code register is cleared and the external interrupt pin (iRO) is "low" or a negative edge has set the internal interrupt flip-flop, then the external interrupt occurs.
The action of the external interrupt is identical to the timer
except that the service routine address is specified by the
contents of $7FA and $7FB. Figure 15 shows both a functional diagram and timing for the interrupt line. The timing
diagram shows two different treatments of the interrupt line
(mLl) to the processor. The first method is single pulses on
the interrupt line spaced far enough apart to be serviced. The
minimum time between pulses is a function of the length of
the interrupt service routine. Once a pulse occurs, the next
pulse should not occur until the MPU software has exited the
routine (an RTI occurs). This time (tIUL) is obtained byadding 20 instruction cycles (tcyc) to the total number of cycles
it takes to complete the service routine including the RTI in-

struction; refer to Figure 15. The second configuration
shows many interrupt lines "wire ORed" to form the interrupts at the processor. Thus, if after servicing an interrupt
the IRQ remains low, then the next interrupt is recognized.

SOFTWARE INTERRUPT (SWI)
The software interrupt is an executable instruction. The
action of the SWI instruction is similar to the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask in the condition code register. The service
routine address is specified by the contents of memory locations $7FC and $7FD.
The following three functions are not strictly interrupts,
however, they are tied very closely to the interrupts. These
functions are RESET, STOP, and WAIT.
RESET - The RESET input pin and the internal power-on
reset function each cause the program to vector to an initialization program. This vector is specified by the contents

(a) Intarrupt Functional Diagram

en

a:

:i

Level Sensitive

~

Mask Option

I-

Voo

o

External
Interrupt
Request

0..------1

Interrupt Pin - - - - - 4 _ - - - Q C

o

I Bit (CCRI

R
Power-On Reset
External Reset
External Interrupt
Being Serviced
(bl Interrupt Mode Diagram

111

IRO~tIUH

~

U

tIUL~~

Edge Condition
The minimum pulse width (tIUHI is one
tcyc. The period tlUL should not be less
than the number of tcyc cycles it takes to
execute the interrupt service routine plus
20 tcyc cycles.

IROIMPUI~L-____________________________~
Mask Optional Level Sensitive

121

:z
o
o
a:

u

If after servicing an interrupt the IRO remains low. then the next interrupt is
recognized.

(R.Ol~ tUH==--..J
•
•
IROn

92CS-38007

Fig. 15 - External interrupt.

2-139

u

il

CDP6805F2CDP6805F2C
of memory locations $7FE and $7FF. The interrupt mask of
the condition code register is also set. See preceding section
on Reset for details.
STOP - The STOP instruction places the CDP6805F2 in
its lowest power consumption mode. In the STOP function,
the internal oscillator is turned off causing all internal processing and the timer to be halted; refer to Figure 16.
During the STOP mode, timer control register (TCR) bits 6
and 7 are altered to rernove any pending timer interrupt requests and to disable any further timing interrupts. External
interrupts are enabled in the condition code register. All
other registers and memory remain unaltered. All 1/0 lines
remain unchanged. The processor can only be brought out
of the STOP mode by an external IRQ or RESET.

WAIT - The WAIT instruction places the CDP6805F2 in
a low-power consumption mode, but the WAIT mode consumes somewhat more power than the STOP mode. In the
WAIT mode, the internal clock is disabled from all internal
circuitry except the timer circuit; refer to Figure 17. Thus, all
internal processing is halted, however, the timer continues
to count normally.
During the WAIT mode, the I bit in the condition code
register is cleared to enable interrupts. A~ ,other registers,
memory, and 1/0 lines remain in their last state. The timer
may be enabled by software prior to entering the WAIT
mode to allow a periodic exit from the WAIT mode. If an external and a timer interrupt occur at the same time, the external interrupt is serviced first; then, if the timer interrupt request is not cleared in the external interrupt routine, the normal timer interrupt (not the timer WAIT interrupt) is serviced
since the MCU is no longer in the WAIT mode.

Stop

TIMER

S top Oscillator
And All Clocks
TCR Bit 7-0
Bit 6-1
Clear I Mask

Yes

92C5-38008

The MCU timer contains an 8-bit software programmable
counter with a 7-bit software selectable prescaler. Figure 18
contains a block diagram of the timer. The counter may be
preset under program control and decrements towards zero.
When the counter decrements to zero, the timer interrupt request bit (i.e., bit 7 of the timer control register (TCR)) is set.
Then, if the timer interrupt is not masked (i.e., bit 6 of the
TCR and the I bit in the condition code register are both
cleared) the processor receives an interrupt. After completion of the current instruction, the processor proceeds to
store the appropriate registers on the stack and then fetches
the timer vector address from locations $7F8 and $7F9 (or
$7F6 and $7F7 if in the WAIT mode) in order to begin servicing.
The counter continues to count after it reaches zero allowing the software to determine the number of internal or external input clocks since the timer interrupt request bit was
set. The counter may be read at any time by the processor
without disturbing the count. The contents of the counter
become stable, prior to the read portion of a cycle, and do
not change during the read. The timer interrupt request bit
remains set until cleared by the software. TCR7 may also be
used as a scanned status bit in a non-interrupt mode of
operation (TCR6= 1l.
The prescaler is a 7-bit divider which is used to extend the
maximum length of the timer. Bit 0, bit 1, and bit 2 of the
TCR are programmed to choose the appropriate prescaler
output within the range of + 1 to + 128 which is used as the
counter input. The processor cannot write into or read from
the prescaler, however, its contents are cleared to all "Os" by
the write operation into TCR when bit 3 of the written data
equals one. This allows for truncation-free counting.
The timer input can be configured for three different
operating modes plus a disable mode depending on the value
written to the TCR4 and TCR5 control bits. Refer to the
Timer Control Register section.
TIMER INPUT MODE 1
If TCR5 and TCR4 are both programmed to a "0", the input to the timer is from an internal clock and the TIMER input pin is disabled. Th!l internal clock mode can be used for

Fig. 16 - Stop function flowchart.

2-140

CDP6805F2, CDP6805F2C

Oscillator Active
Clear I-Bit
Timer Clock Active
All Other Clocks
Stop

tn

g
II:

....
Z

II:
CI

No

No

Fetch External
Interrupt, Reset.
or Timer Interrupt
Vector (from Wait

92CS-38009

Mode only)

Fig, 17 - WAIT function flowchart.

periodic interrupt generation as well as a reference in frequency and event measurement. The internal clock is the instruction cycle clock. During a WAIT instruction, the internal
clock to the timer continues to run at its normal rate.

TIMER INPUT MODE 2
With TCR5=O and TCR4= 1, the internal clock and the
TIMER input pin are ANDed to form the timer input signal.
This mode can be used to measure external pulse widths.
The external timer input pulse simply turns on the internal
clock for the duration of the pulse. The resolution of the
count in this mode is ± one internal clock and therefore, accuracy improves with longer input pulse widths.

2-141

TIMER INPUT MODE 3
If TCR5= 1 and TCR4=O, ali inputs to the timer are disabled.
TIMER INPUT MODE 4
If TCR5= 1 and TCR4= 1, the internal clock input to the
timer is disabled and the TIMER input pin becomes the input
to the timer. The timer can, in this mode, be used to count
external events as well as external frequencies for generating
periodic interrupts. The counter is clocked on the falling
edge of the external signal.
Figure 18 shows a block diagram of the timer subsystem.
Power-on reset and the STOP instruction invalidate the contents of the counter.

~

Co)

iii

CDP6805F~CDP6805F2C

Enable/Disable

Write

Read

Interrupt

Internal
Clock

,~--------------------------~--------------------~/
Software Functions
NOTES:
1. Prescaler and 8-bit counter are clocked falling.edge of the internal clock (AS) or external

Input.
2.

Counter is written to during Data Strobe (DS).and counts down continuously.
92CM- 38034R1

Fig. 18 - Programmabla timer/counter block diagram.

TCR3 - Timer Prescaler Reset bit: writing a "1" to this bit
resets the prescaler to zero. A read of this location always indicates "0". (Unaffected by RESIT.)

TIMER CONTROL REGISTER (TCR)
76543210
ITCR71TCR61TCR51TCR41TCR31TCR21TCR11TCROI

TCR2, TCR1, TCRO - Prescaler select bits: decoded to
select one of eight outputs on the prescaler. (Unaffected by

All bits in this register except bit 3 are read/write bits.

lrrSTI.)

TCR7 - Timer interrupt request bit: bit used to indicate
the timer interrupt when it is logic" 1".
1 - Set whenever the counter decrements to zero or
under program control.
o - Cleared on external RESIT, power-on reset, STOP
instruction, or program control.

Prescaler
TCR2
0
0
0
0
1
1
1
1

TCR6 - Timer interrupt mask bit: when this bit is a logic
"1", it inhibits the timer interrupt to the processor.
1 - Set on external ~, power-on reset, STOP instruction, or program control.
o - Cleared under program control.
TCR5 - External or internal bit: selects the input clock
source to be either the external timer pin or the internal
clock. (Unaffected by RESET.)
1 - Select external clock source.
o - Select internal clock source.

TCRl
0
0
1
1
0
0
1
1

TCRO
0
1
0
1
0
1
0
1

Result
+1
+2
+4
+8
+16
+32
+64
+128

INSTRUCTION SET
The MCU has a set of 61 basic instructions. They can be
divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type. All the instructions within a given type are presented in individual
tables.

TCR4 - Externatenable bit: control bit used to enable the
external TIMER pin. '(Unaffected by RESEI.l
1 - Enable external TIMER pin.
o - Disable external TIMER pin.
TCR5 TCR4
0
0 Internal Clock to Timer
0
1 AND of Internal Clock and TIMER
Pin to Timer
1
Illputs to Timer Disabled
0
1
1 TIMER Pin to Timer

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One
operand is either the accumulator or the index register. The
other ope(and is obtained from memory using one of the addressing modes. The operand for the jump unconditional
IJMP) and jump to subroutine IJSRl instructions is the program counter. Refer to Table 4.

2-142

CDP6805F2, CDP6805F2C
"contents of," an arrow indicates "is replaced by," and a
'colon indicates "concatenation of two bytes."

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register,
modify or test its contents, and write the modified value
back to memory or to the register. The test for negative or
zero (TST) instruction is an exception to the read-modifywrite sequence since it does not modify the value. Refer to
Table 5.

INHERENT
In inherent instructions, all the information necessary to
execute the instruction is contained in the opcode. Operations specifying only the index registers or accumulator and
no other arguments are included in this mode.

BRANCH INSTRUCTIONS
Most branch instructions test the state of the condition
code register and, if certain criteria are met, a branch is executed. This adds an offset between -127 and + 128 to the
current program counter. Refer to Table 6.

IMMEDIATE
In immediate addreSSing, the operand is contained in the
byte immediately following the opcode. Immediate addressing is used to access constants which do not change during
program execution (e.g., a constant used to initialize a loop
counter!'
EA=PC+l; PC .... PC+2

BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any bit which
resides in the first 128 bytes of the memory space where all
port registers, port DDRs, timer, timer control, and on-chip
RAM reside. An additional feature allows the software to
test and branch on the state of any bit within the first 256
locations. The bit set, bit clear, and bit test and branch functions are implemented with a single instruction. For the test
and branch instructions, the value of the bit tested is also
placed in the carry bit of the condition code register. Refer to
Table 7.

DIRECT
In the direct addressing mode, the effective address of the
argument is contained in a single byte following the opcode
byte. Direct addreSSing allows the user to directly address
the lowest 256 bytes in memory with a Single two-byte instruction. This includes all on-chip RAM and I/O registers
and 128 bytes of on-Chip ROM. Direct addressing is efficient
in both memory and time.
EA=(PC+1); PC+PC+2
Address Bus High .... O; Address Bus Low .... (PC+ 1)

CONTROL INSTRUCTIONS
These instructions are register reference instructions and
are used to control processor operation during program execution. Refer to Table 8.
OPCODE MAP
Table 9 is an opcode map for the instructions used on the
MCU.

EXTENDED
In the extended addreSSing mode, the effective address of
the argument is contained in the two bytes following the opcode. Instructions with extended addreSSing modes are
capable of referencing arguments anywhere in memory with
a Single three-byte instruction.

ALPHABETICAL LISTING
The complete instruction set is given in alphabetical order
in Table 10.

EA=(PC+1l:(PC+2); PC .... PC +3
Address Bus High"" (PC + 1); Address Bus Low .... (PC+2)

ADDRESSING MODES
INDEXED, NO-OFFSET
In the indexed, no-offset addreSSing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addreSSing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is used to move a pointer through a table or
to address a frequently referenced RAM or I/O location.
EA=X; PC .... PC+l
Address Bus High .... O; Address Bus Low .... X

The MCU uses ten different addressing modes to provide
the programmer with an opportunity to optimize the code to
all situations. The various indexed addressing modes make it
possible to locate data tables, code conversion tables, and
scaling tables anywhere in the memory space. Short indexed
accesses are single-byte instructions while the longest instructions (three bytes) permit tables throughout memory.
Short and long absolute addressing is also included. Twobyte direct addreSSing instructions access all data bytes in
most applications. Extended addreSSing permits jump instructions to reach all memory. Table 10 shows the addressing modes for each instruction with the effects each instruction has on the condition code register. An opcode map is
shown in Table 9.
The term "Effective Address" (EA) is defined as the byte
address to or from which the argument for an instruction is
fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate

INDEXED, 8-BIT OFFSET
Here the EA is obtained by adding the contents of the byte
following the opcode to that of the index register, therefore,
the operand is located anywhere within the lowest 511
memory locations. For example, this mode of addressing is
useful for selecting the mth element in an n element table. All
instructidns are two bytes. The content of the index register

2-143

CDP6805F2, CDP6805F2C
BIT SETICLEAR
Direct addressing and bit addressing are combined in instructions which set and clear individual memory and 110
bits. In the bit set and clear instructions, the byte is specified
as a direct address in the location following the opcode. The
first 128 addressable locations are thus accessed. The bit to
be modified within that byte is specified with three bits of the
opcode. The bit set and clear instructions occupy two bytes:
one for the opcode (including the bit number) and the second for addressing the byte which contains the bit of interest.
EA=(PC+ll; PC-PC+2
Address Bus High-O; Address Bus Low-(PC+l)

(X) is not changed. The content of (PC+ 1) is an unsigned
.B-bit integer. One-byte offset indexing permits look-up tables
to be easily accessed in either RAM or ROM.
EA=X+(PC+1); PC-PC+2
Address Bus High-K; Address Bus Low-X+(PC+l)
where K=The carry from the addition of X+ (PC+ 1)

INDEXED, l6-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit
index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar
to indexed 8-bit offset, except that this three-byte instruction
allows tables to be anywhere in memory (e.g., jump tables in
ROM) The content of the index register is not changed.
EA=X+[(PC+l):(PC+2)]; PC-PC+3
Address Bus High-(PC+1)+K;
Address Bus Low-X+(PC+2)
where K = The carry from the addition of X + (PC + 2)

BIT TEST AND BRANCH
Bit test and branch is a combination of direct addressing,
bit addressing, and relative addressing. The bit address and
condition (set or clear) to be tested is part of the opcode.
The address of the byte to be tested is in the single byte immediately following the.opcode byte (EA1). The Signed
relative B-bit offset is in the third byte (EA2) and is added to
the PC if the specified bit is set or cleared in the specified
memory location. This Single three-byte instruction allows
the program to branch based on the condition of any bit in
the first 256 locations of memory.
EA1=(PC+l)
Address Bus High-O; Address Bus Low-(PC+ll
EA2 = PC + 3 + (PC + 2); PC - EA2 if branch taken;
otherwise, PC-PC+3

RELATIVE
Relative addressing is o'nly used in branch instructions. In
relative addressing, the contents of the 8-bit signed byte
following the opcode (the offset) is added to the PC if and
only if the branch condition is true. Otherwise, control proceeds to the next instruction. The span of relative addressing
is limited to the range of - 126 to + 129 bytes from the
branch instruction opcode location.
EA=PC+2+(PC+1l; PC-EA if branch taken;
otherwise, PC-PC+2

2-144

TABLE 4 -

REGISTER/MEMORY INSTRUCTIONS
Addressing Modes

Immediate
Mnemonic

Op
Code

Load A from Memory

LOA

A6

Load X from Memory

LOX
STA

AE

Function

Bytes

#
Cycles

Op
Code

2
2

2
2

B6

-

-

2

Indexed
INo Offset)

Extended

Indexed
IS-Bit Offset)

Op
Code

#

#

#

Cycles

Op
Code

#

Bytes

Bytes

Cycles

Op
Code

3

C6

3

4

F6

1

3

3

CE

3

4

FE

1

2

4

C7

3

5

F7

1

3
4

BF

2

4

CF

3

CB

5
4

1

2

3
3

FF

BB

FB

1

#

#

Bytes

Cycles

BE

2
2

B7

2

Indexed
116-Bit Offset)

I

I

Bytes

Cycles

4

Op
Code
06

3

5

4

DE

3

5

2

5

07

3

6

EF

2

3

6

2

5
4

OF

EB

DB

3

5

#

#

Bytes

Cycles

E6

2

EE

2

E7

4
3

Store X in Memory

STX

-

Add Memory to A
Add Memory and
Carry to A

ADD

AB

ADC

A9

2

2

B9

2

3

C9

3

4

F9

1

3

E9

2

4

09

3

5

Subtract Memory

SUB

AD

2

2

BO

2

3

CO

3

4

FO

1

3

EO

2

4

DO

3

5

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

3

C2

3

4

F2

1

3

E2

2

4

02

3

5

Store A in Memory

AND Memory to A

AND

2
2

B4

C4
CA

3
3

1

04

3

5

FA

1

E4
EA

4

4

3
3

2

BA

3
3

F4

2

2
2

4

ORA

A4
AA

2

OR Memory with A

2

4

DA

3

5

Exclusive OR Memory
with A

EOR

AB

2

2

B8

2

3

C8

3

4

F8

1

3

E8

2

4

08

3

5

CMP

Al

2

2

B1

2

3

C1

3

4

F1

1

3

E1

2

4

D1

3

5

c;)

CPX

A3

2

2

B3

2

3

C3

3

4

F3

1

3

E3

2

4

D3

3

5

.~

BIT

A5

2

2

B5

2

3

C5

3

4

F5

1

3

E5

2

4

05

3

5

Jump Unconditional

JMP

-

-

-

BC

2

CC

3

3

FC

1

2

EC

DC

3

4

JSR

-

-

-

BD

5

CD

3

6

FD

1

5

ED

2
2

3

Jump to Subroutine

2
2

6

DO

3

7

N

Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory

~

Bit Test Memory with
A (Logical Compare)

.!.

,

Direct

~

01

TABLE 5 -

READ-MODIFY-WRITE INSTRUCTIONS
Addressing Modes

Inherent IA)
Op
Code

#

Inherent (X)

Cycles

1

5

1

3A

3
3

3F

2

53

1
1

33

50

1

3

30

3

39

2

5

79

1

5

69

2

6

3

36

2

5

76

1

5

66

2

6

3B
34

2

5

78

1

5

6

74

2

6

77

1
1

5

37

5
5

66
64

2

2
2

5

67

2

6

3D

2

4

7D

1

4

6D

2

5

1
1

3
3

5~

Negate
12's Complement)

NEG

40

1

3

Rotate Left Thru Carry

ROL

49

1

59

1

Rotate Right Thru
Carry

ROR

46

,

3
3

56

1

Logical Shift Left

LSL

3

3

1

3

58
54

1

LSR

48
44

1

Logical Shift Right

1

Arithmetic Shift Right

ASR

47

1

3

57

1

3
3

Test for Negative
Dr Zero

TST

40

1

3

50

1

3

Complement

Bytes

3

4F
43

Clear

1

,

3C

CLR
COM

Decrement

Bytes

#

3

1

INC

I

Cycles

DEC

Mnemonic

#

#
Bytes
2
2

5C
5A

#
Bytes
1
1

#

4C
4A

Function

Indexed
IS-Bit Offset)

Op
Code

Op
Code

#
Cycles
3
3

Increment

Indexed
INo Offset!

Direct

I

#
Cycles
5

Op
Code

Bytes

Cycles

2

6

5

6C
6A

2

6

6F
63

2

2

6
6

60

!2

6

5

7C
7A
7F
73

1

2

5
5

1

5
5

2

5

70

1

5

MICROCONTROLLERS

II

Op
Code

B
"b

~~

C")

CDP6805F~CDP6805F2C
TABLE 6 - BRANCH INSTRUCTIONS

,

,

Bytes
2

Cycles

2
2

3
3
3
3

Relative Addressing Mode
Op
Code

Mnemonic

Function
Branch Always
Branch Never
Branch IFF Higher
Branch IFF lower or Same
Branch IFF Carry Clear
(Branch IFF Higher or Same)

BRA
BRN
BHI

20
21
22
23
24
24
25
25
26
27
28
29
2A
2B
2C
2D
2E
2F
AD

BlS
BCC
(BHS)

Branch IFF Carry Set
(Branch IFF lower!
Branch )FF Not Equal
Branch IFF Equal

BCS
(BLG)
BNE
BEQ
BHCC

Branch IFF Half Carry Clear

BHCS

Branch IFF Half Carry Set
Branch IFF Plus

BPl
BMI
BMC
BMS

Branch IFF Minus
Branch IFF Interrupt Mask Bit is Clear
Branch IFF Interrupt Mask Bit is Set
Branch IFF Interrupt Line is low
Branch IFF Interrupt Line is High

Bil
BIH

Branch to Subroutine

BSR

3

2
2
2

3
3
3

2
2
2
2

3
3

2

3

2
2
2
2
2

3
3
3

2
2

3
3

2

6

3
3

TABLE 7 - BIT MANIPULATION INSTRUCTIONS

Bit Setl Clear
Function
Branch IFF Bit n is Set
Branch IFF Bit n is Clear
Set Bit n
Clear Bit n

Mnemonic
BRSET n (n=O .. 7)
BRClR n In = O... 7)
BSET n (n=O. .7)
BClR n (n=0 ... 7)

Addressing Modes
Bit Test and Branch
Op
I
I
Cycles
Bytes
Cycles
Code
2-n
3
5

,

Op
Code

Bytes

-

-

-

-

-

01 +2-n

3

5

10+2-n
11 +2-n

2

5
5

-

-

-

-

-

#

2

TABLE 8 - CONTROL INSTRUCTIONS

Op

,

,

Code

Bytes

CycIee

97
9F

1
1
1
1
1

2

Inherent
Function

Mnemonic

Transfer A to X
Transfer X to A
Set Carry Bit

TAX
TXA
SEC

Clear Carry Bit
Set Interrupt Mask Bit
Clear Interrupt Mask Bit
Software Interrupt

ClC
SEI
CLI
SWI
RTS

Return from Subroutine
Return from Interrupt
Reset Stack Pointer
No-Operation
Stop

RTI
RSP
NOP
STOP

Wait

WAIT

2-146

99
9B
9B
9A

B3
B1

eo
9C
90
BE
SF

1
1
1
1
1
1
1
1

2
2
2
2

2
10

6
9

2
2
2
2

TABLE 9- INSTRUCTION SET OPCODE MAP

Bit Manipulation

~

,

000'

2
00'0

3

0011

4
0'00

5

0'
BRSEJ~.
5

3BRCL:~.

~

BRCLR'
3
BT

2
5

, BSE~~c

5

5

5

5

7
at 11

BRCL:lB

,~

BRSEJ,4,.

B

,foo

5

2 BCL~~c

5

2 BSE~~c
5

BCL~~c

5

, BSE1~(
5
2 BCL~~c

BRCL:fe
5
5
BSE1~c
I ,BRSEJi.
5
5
BRCLR5 .2 BClR5
3
BTB
esc

0"

13BRSEJf.
5
,~,
13BRCL:fB
5
13BRSEl'?B
5
F
BRCLR7
1111 - - ~BTB

11~0

5

,

BSE~~;

5
2 BCL~~c

BRA'
REI
3
2 BRNREl
3
BHI

INH

NEG'
-DIR

NEG

BLS
R

BHC~FI

3

BHC~El

3
BPLRFI
3
BMI
2
Rl
3
BMC
REl
3
2 BM~EI
2
2

BIL
BIH

1

INH

,

3
NEG
INH

o~o
6

,

NEG

,

0111

'000

NEG'
IX

llitL

lMM
A

DIR
B

'00'

1010

1011

9

8

,
, RTS
RTI

6

3

5

,

SUB '
IMM
2
CMP
IMM

5

lSf))TR

,

,

COMA
INH
3
LSRA
INH

X
, COM INH

3

3
, ROR~NH

6

, COM

3

, LSRXINH

SBC
IMM
2
CPX
2
IMM
2
AND
2
IMM
2
2

3

IX'

6

,

LSR

IX'

5

, COM IX ,
5
, LSR IX

10

SWI
INH

BI~M~

5
2 RORDIR
5
2 ASRDI •
5
, LSLnlR
5
ROLDJR
5

,

DECOIR

5

2 INC

DIR
4

TSTDIR

RORA
1

,

,
,
,

,
,

INH

3
ASRA
INH
3
LSLA
INH
3
ROLA
INH
3
DECA
INH

3

INCA
INH
3
TSTA
INH

,
,
,
,
,
,

ROR

IX'

3

ASRX
INH
3
LSLX
INH
3
ROlX
INH
3
DECX
INH

ASR

3
2

CLR

5

DIR

3

6

,

LSL

IX'

6

L

6

5

,
,

IX'

2

TST

5

IX'

DEC

INC

,

,
,

IXl

6

2

2
LOA
2
IMM

5

, IX
5
, ASR IX
5
, LSL IX
ROR

, IX
5
, DEC IX

ROl

5

IX'

ROL

, IX
, TST IX
INC

4

,
,

3

, CLRAINH , CLRXINH

6

IX'

3

INCX
INH
3
TSTX
INH

6

5

6

CLR
2

CLR
IX'

I

IX

,

2
STOP
INH
2
WAIT
INH

2
TAX
INH
2
2
EOR
ClCIN >
IMM
2
2
ADC
SEC
INH 2
IMM
2
ORA
Cli
INH 2
IMM
SEI

INH
2
RSP
INH
2
NOP
INH

Inherent
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
Indexed INo Offset)
Indexed. 1 Byte 18-Bill Offset
Indexed. 2 Byte 118-Bill Offset

1101

1100

,

2

ADD
IMM

2
2

BSR
REl

01.

3

CPX
01.

AND 3
2

-01.
3

SU~XT

3 SUB

CMP
EXT
3
4
SBC
3
EXT
4
CPX
EXT
3
4
AND

CMP

•

L SUB ,x ,

IX
5

3
3

2

JSR '
DIR

3

IX2

2

SBC 5
1X2

2

CPX 5

2 CPX

3

IX2

5

AND

EXT

3

JSR
EXT

3

CMP

JSR

IX2

2

•

IX'
4
SBC
IX'
4
IX'
4

AND

IX'
4
L BIT IX
4
LOA
2
IX'
STA '
2
IX'
4
EOR
... IXl
2
4
ADC
2
IX'
ORA 4
2
IX'
ADD'
IX'
JMP ,
2
IX'
JSR 0
2
IX'
2

4

,

2
TXA
INH

H~

1111

1110

IX2
3
4
5
BIT 01. I 3 BITEXT 3 BIT IX2
4
5
3
LOA
LOA
LOA
01. 3
EXT 3
IX2
2
4
STA "
STA
STA
01. 3
IX2
2
EXT 3
5
3
4
EOR
EOR
EOR
DIR 3
EXT 3
IX2
2
4
3
5
ADC
ADC
ADC
01. 3
IX2
2
EXT 3
4
ORA'
ORA'
ORA
DIR 3
EXT 3
IX2
2
4
ADD'
ADD
ADD
IX2
DIR 3
EXT 3
2
4
2
3
JMP
JMP
JMP
DIR 3
EXT 3
IX2
2

6

2

SUB '
-DIR
3
CMP
DIR
3
SBC

LDX
IMM
2

lDX '
DIR
2
STX 4
DIR
2

AbbreviMiona for Add_ Modes
INH
IMM
DIR
EXT
REL
BSC
BTB
IX
IX1
IX2

E

0

C

4

"
INH

2

RE~
REl

IX'

IN!:!

,

R~is1.r/Memory

Control
IX
7

INH

, COMol •

3
2 BCC.E[
3
BCS. El
3
BNE
R
3
BEQ
R
3

oil.,

0:00

•3

5

2 BSE~~c
5
BCLR7
BSC
2

.:.,

DIR

clto

BCL~lc

3BRSEJl.

o~o

"~n

5
5

BRSEllB

1011

5

, BCL~~c
, BSE~lc

3BRCL:lB

'00'

, BSE~~c

5

0101

9

'"

,'

BRSETl'
3
.TB

5

.!..

.ri"

0£,

Road-Modify-Write
IX,
INH

Branch
REL

~i

LDX
3
EXT

lDX '
IX2
3

2

6

3

STX
EXT

3

STX

IX2

2

lDX
IX'
STX 5
IX'

SUB '
,
IX
3
CMP
IX
I

,

SBC '
IX

, CPX IX'
3
, AND IX
3
BIT IX
3
LOA
IX

,
, STA IX
3
, EOR IX
, ADC IX3
, ORA''x
, ADD'IX
, JMP IX2

~

,

000'

2
00'0

rJ.,
o;'m
o~,
6
0110

4

,

JSR '
IX

,

LDX 3
IX
4

, STX IX

7
0111

8
'000

9
'00'

A
1010

B

1011

C
1100

D

1101

E
11'0

F
1111

LEGEND

F ...

Mnemonic
Bytes

~.
1

~

7

l

~

,JX

Cycles - - - - - - -

MICROCONTROLLERS •

Opcode in Binary

OOJO c-=
"

Address Mode
92CS-380"

I

Opcode in Hexadecimal

~

0)

Qo

C
C1i

,~

~

~~
~

COP6805F2, COP6805F2C
TABLE 10 -

INSTRUCTION SET
Condition Codas

Addressing Modes
Mnemonic

Inherent

ADC
ADD
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BRA
BRN
BRCLR
BRSH
BSET
BSR
CLC
CLI
ClR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
LOA
LOX
LSL
lSR
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT

Immediate

Direct

Extended

X

X

X

"X

"X

1\

X
X

Relative

Indexed
(No Offset!
X
X
X
X
X

X

X
X

Indexed
(8 Bits!

Indexed
(16 Bits!

X
X
X
X
X

X
X
X

Bit

Setl
Clear

Bit
Teet &
Branch

A
• A
A -~
A
A
A
A

••
•
••

X
X
X
X
X
X
X
X
X
X

X

X

X

A A
A iA
A
A A
A A

•

••
• ••• •••
•• ••
•• ••
•• ••

X

X

H I N Z C

X

A

A

X
X
X
X
X
X
X
X
X
X
X

A

••
0

X
X
X
X
X

0
X

X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X

X
X
X

0

1

X

A
A

X

I\.

A
A
A
A
A
A

X
X
X
X
X

X

X

X

X

X

X

X

X

X

X
X

X
X

X
X

X

X

X

X
X
X
X
X

X
X

X
X

1
A

I\.

A
A
A
A
A

A

A

•
A
A
A

••• •• • • ••
••• • • • •
•• •• • • •
•• •1 •• •• •1
•• •0 • • ••
•
•• •
1
•• • •• •• •
•• •• • ••
•
• u • • •
I·

X

X
X

X

A
A
A

o

X

x

I\.

A

X

A

••
•• •• •••
•
A

X
X
X

••

I\.

J\.

A

A

A

A

A

A

A

A
A

A
A

A

A

•

I\.

•

A

•

A

I·

X

Condition Code Symbols
H

Half Carry (From Bit 3)

I

Interrupt Mask

N

Negative (Sign Bitl

Z

Zero

C

Carry/Borrow

A
•

o

Test and Set if True. Cleared Otherwise.
Not A ffeeted
Load CC Register From Stack
Cleared
Set

2-148

CDP6805G2
CDP6805G2C

mHARRIS

CMOS High Performance Silicon Gate
8-Bit Microcontroller

January 1991

Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Typical Full Speed Operating Power at 5V •••••••••••••••••••••••••••• 12mW
Typical WAIT Mode Power ••.••••••••••••••••••••••••••••••••••••••••• 4mW
Typical STOP Mode Power •.••••..••••.••.••••.••.••••••••.•.•••••.••.• 51lW
Fully Static Operation
On-Chip RAM •••••••••••••••••••••••••••••••••••••••.••••••••••• 112 Bytes
On-Chip ROM •.•••••.••••••••.•••••••••.••••••••••••••••••••••• 2106 Bytes
Bidirectional 110 Lines •••••••••••.••.••.•.••.••••..•••.•.•.•••.••••••..•• 32
High Current Drive
Internal S-Blt Timer With Software Programmable 7-Blt Prescaler
External Timer Input
External Interrupts And Timer Interrupts
Self Check Mode
Master Reset And Power On/Reset
Single 3V to 6V Supply
On-Chip Oscillator With RC or Crystal Mask Options
True Bit Manipulation
Addressing Modes With Indexed Addressing for Tables

Pinout
PACKAGE TYPES D AND E
TOPV1EW
REm

.....

ascI

PA7

TINEA

VOO

0SC2

PA.

P07
PO.
PO'
PO.
PO'
PO'
PO.
POO
PCO
PC,

PA,
PAO

PA'
PA'
PAl
PAO
PBO
PB'
PB'
PB3
PB'
PB'
PB.
P.'

V"

PC'
PC'

17

PC.
PCO
PC.
PC1

I.
I.
20

Description
The CDP6805G2 Microcomputer Unit (MCU) belongs to the
CDP6805 Family of Microcomputers. This 8-bit MCU contains on chip oscillator, CPU, RAM, ROM, I/O, and Timer.
The fully static design allows operation at frequencies down
to DC, further reducing its already low power consumption.
It is a low power processor designed for low end to mid

range applications in the consumer, automotive, industrial
and communications markets where very low power
consumption constitutes an important factor. The
CDP6805G2 and CDP6805G2C are available in a 40 lead
dual-in-Iine plastic package (E suffix) and in a 40 lead
dual-in-Iine sidebrazed ceramic package (D suffix).

Block Diagram

Port
B

1/0
Lines

1'80
PSI
PB2
PB3
PB4
PS5
PB6
P87

Index
Register

CPU
Control

Data
Oir
Re~

X

Port
C
Reg

C()!ldltlon

Code
Register CC

CPU

PCO
PCI
PC2
PC3
PC4
PC5
PC6
PC7

Port
C

110
lines

Slack

Port
A

1/0

PAO
PAl
PA2
PA3
PA4

6

Data
Dir

5

POUller

S

Program
Counter
High PCH

ALU

Reg

Lines

8
PA7

Data
Dor
Reg

Port
D
Reg

PDO
PDI
PD2
P03
PD4
P05
P06
PD7

Port
D

1/0
Lines

198x8
Self·Check

ROM

Copyright @ Harris Corporation 1991

File Number
2-149

1364.1

CDP6805GZCDP6805G2C
MAXIMUM RATINGS (Voltages Referenced to VSS)
Ratings
Supply Voltage
All Input Voltages EXGept OSC1
Current Drain Per Pin Excluding VOl) and V.SS
Operating Temperature Range
COP6805G2
COP6805G2C
Storage Temperature Range
Current Drain Total (P04-P07 only)

Value
-0.3 to +8
VSS-0.5 to VOO+0.5
10
TL
TH
o to +70
-40 to +85
-55 to +150
40

Symbol
VOO
Vin

I
TA
T.1g
IOH

Unit
V
V
mA

°C
°C
mA

THERMAL CHARACTERISTICS
Symbol

Characteristics
Thermal Resistance
Plastic
I Ceramic

8JA

Value

Unit

100
50

°C/W

This device contains circuitry to protect the
inputs against damage due to high static
voltages of electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages. to this high impedance circuit. For proper operation it is
recommended that Yin and Vout be constrained to the range VSSS(Vin or
Vout)sVOO. Reliability of operation is
enhanced if unused inputs except OSC2 and
NUM are tied to an appropriate logic voltage
level (e.g., either VSS or VOO).
VOO=4.5V

Port
Band C
A, POO-P03

R1
24.3 kD
1.21 kO

R2
4.32 kD
3.1 kD

PD4-P07

3000

1.64 kD

-

ILoad

Test Point··

R2

0----4.--4.--14---..
50 pF

(mA)

5.0

Fig. 2 - Equivalent test load.

4.0

0

-R

VOO=6V

E
~
:::J

u
Cl
.c:
!'!

.,

3.0
VOO=5V

III

'"

0

~

'0.
>-

I--

2.0

1.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Internal Frequency (1/teye)

Fig. 3 - Typical operating current vs. Internal frequency.

2-150

0.9

1.0
(MHz)

,CDP6805GZCDP6805G2C
DC ELECTRICAL CHARACTERISTICS. (VOO=3 Vdc, VSs=O Vdc, TA=TL to TH, uri less otherwise noted)
Symbol
VOL
VOH

Characteristics
Output Voltage Iloads IliA

Min

-

VOO-O.l

Output High Voltage

-

Unit
V
V

-

V

Max
0.1

(fload= - 50 IIA) PBO-PB7, PCO-PC7

VOH

1.4

(fLoad= -0.5 mA)PAD-PA7, PDQ-P03

VOH

1.4

V

(fload-' -2 rnA) P04-P07

V

VOH

1.4

Output low Voltage
(fload = 300 IIA) All Ports
PAD-PA7, PBD-PB7, PCD-PC7, POO-P07

VOL

-

0.3

V

Input High Voltage
Ports PAD-PA7, PBD-PB7, PCD-PC7, POD-PD7
TIMER, IRQ, RESET
OSCI
Input low Voltage All Inputs
Total Supply Current (no dc loads, tcyc=5I1S)

VIH
VIH
VIH
Vll

2.7
·2.7

VOO

P

VOO
VOO

VSS

0.3

V
V
V
V

100
100
100

0.5

rnA

-

200
100

"A

III

-

5

"A

lin

-

±l

"A

Cout
Cin

-

12

pF
pF

RUN (measured during self-check, VIL=O.1 V, VIH=VOO-O.l V)
WAIT (See Note)
STOP (See Note)
I/O Ports Input leakage
PAO-PA7, PBD- PB7, PCD-PC7, POO-P07
Input Currl!!!L
RESET, IRQ, TIMER, OSCI
Capacitance
Ports
RESET, IRQ, TIMER, OSCI

-

8

pA

DC ELECTRICAL CHARACTERISTICS (VOo=5 Vdc ± 10%, VSs=O Vdc, TA=TL to TH, unless otherwise noted)
Symbol
VOL
VOH

Characteristics
Output Voltage Iloads 10!"A

Min

-

Max
0.1

VOO-O.l

-

Unit
V
V

Output High Voltage
(fload= -100 "A) PBD-PB7, PCO-PC7

VOH

2.4

-

V

(fload= -2 rnA) PAD-PA7, POD-P03

VOH

2.4

-

V

'(fload- -8 rnA) PD4-P07

VOH

2.4

-

V

Output low Voltage
(fload = 800 "Al All Ports
PAD-PA7, PBD-PB7, PCD-PC7, POD-P07

VOL

-

0.4

V

Input High Voltage
Ports PAD-PA7, PBD-PB7, PCD-PC7, POD-P07
TIMER, IRQ, RESET,'OSCI

~
VIH

Voo-2
VOO-O.S

VOO
VOO

V
V

Vll

VSS

O.S

V

100
100
100

4

-

1.5
150

rnA
rnA

Input low Voltage All Inputs
Total Supply Current ICl =50 pF
on Ports, no dc loads, tcyc = 1 ,.s)
RUN Imeasured during selt-check,
Vll=0.2 V, VIH=VOO-0.2 VI
WAIT (See Note)
STOP (See Note)

-

"A

1/ 0 Ports Input leakage
III

-

±10

"A

Input Currl!!!L
RESET, IRQ, TIMER, OSCI

lin

-

±l

"A

Capacitance
Ports
RESET, IRQ, TIMER, OSCI

~ut
Cin

-

12
8

pF
pF

PAD-PA7, PBD- PB7, PCO-PC7, POO-P07

NOTE·: Test conditions for 100 are as follows:
All ports programmed as inputs
Vll = 0.2 V IPAD-PA7, PBD-PB7, PCO-PC7, POD-P07)

VIH = VOO-0.2 V for RESET, IRQ, TIMER
OSCI input is a squarewave from 0.2 V to VOO - 0.2 V
OSC2 output load = 20 pF Iwait 100 is affected linearly by the
OSC2 capacitance).

2-151

CDP6805G2,CDP6805G2C
TABLE 1 - CONTROL TIMING
(VOO=5 Vdc

± 10%, VSS=O, TA'fTL to TH. fosc=4 MHz)

Characteristics
Crvstal Oscillator Startup Time (FiQure 5)
Stop Recovery Startup Time (Crystal Oscillator) (Figure 6)
Timer Pulse Width (FiQure 4)
Reset Pulse Width (Figure 5)
Timer Period (Figure 4)
Interrupt Pulse Width low (Figure 15)
Interrupt Pulse Period (Figure 15)
OSC1 Pulse Width
(;ycle Time
Frequency of Operation
Crystal
External Clock

Symbol

Min

tOXOV
tilCH
tTH. tTL
tRl
tTLTl
tlUH
tlUl
tOH. tOl
tcyc'

-

0.5
1.5
1
1

Max
100
100

100
1000

-

fosc

-

4

losc.

DC

*

Unit
ms
ms
tCYC
tcyc
tcyc
tcyc
tcyc
ns
ns
MHz
MHz

"The minimum period tlUl should not be less than the number of tcyc cycles it takes to execute the interrupt service routines plus 20 tcyc cycles.

External
Clock

( Timer)
Pin 37

Fig. 4 - Timer relationships.

Voo

~~-----------------------------------------------------

~~ZZl77Z1ZZ777J77J7ZZ727ZZlZZ7777ZZZZl/ZZl7ZZZZZZ77777ZZ/
I
I
I
'oxov

I
,. "I'-

I

)

I

rLS

I

"I

1920 'ere

i'e'.1

INTERNAL
ADDRESS
BUS *

INTERNAL
DATA
BUS*

"-.f.

RESET

*INTERNAL TIMING SIGNAL AND BUS INFORMATION NOT AVAILABLE EXTERNALLY

IUIOSCI LINE IS NOT MEANT TO REPRESENT FREQUENCY.
IT IS ONLY USED TO REPRESENT TIME.

Fig. 5 - Power-on RESET and RESET.

2-152

92CM-38103

CDP6805G~CDP6805G2C

(O~~~:~*~~~~~?::/0/ffi~7(#Z
I

SENS ITiVE
ONLY
I ~~
RESET

1920 'eye

, LCH

~~--------~----~~---------

~2* ------------------------~

*"

**

INTERNAL TIMING SIGNALS NOT AVAILABLE EXTERNALLY,

REPRESENTS THE INTERNAL GATING OF THE OSCI

INPUT PIN.
92CS '38101

Fig. 6 - Stop recovery and power-on RESET.

FUNCTIONAL PIN DESCRIPTION
VDD and VSS
Power is supplied to the MCU using these two pins. VOO
is power and VSS is ground.
IRQ (MASKABLE INTERRUPT REQUEST)
IRO is mask option selectable with the choice of interrupt
sensitivity being both level- and negative-edge or negativeedge only. The MCU completes the current instruction
before it responds to the request. If I RO is low and the interrupt mask bit (I bit) in the condition code register is clear, the
MCU begins an interrupt sequence at the end of the current
instruction.
If the mask option is selected to include level sensitivity,
then the IRO input requires an external resistor to VOO for
"wire-OR" operation. See the Interrupt section for more
detail.

OSC1, OSC2
The CDP6805G2 can be configured to accept either a
crystal input or an RC network. Additionally, the internal
clocks can be derived by either a divide-by-two or divideby-four of the external frequency (fOSC). Both of these
options are mask selectable.

:::l
o
a::

I-

z:

o

<.:>

o

a::

<.:>

:is
RC - If the RC oscillator option is selected, then a resistor
is connected to the oscillator pins as shown in Figure 7(b)'
The relationship between Rand fosc is shown in Figure 8.

CRYSTAL - The circuit shown in Figure 7(al is recommended when using a crystal. The internal oscillator is
designed to interface with an AT-cut parallel resonant quartz
crystal resonator in the frequency range specified for fosc in
the electrical characteristics table. Using an external CMOS
oscillator is suggested when crystals outside the specified
ranges are to be used. The crystal and components should
be mounted as close as possible to the input pins to minimize
output distortion and start-up stabilization time. Crystal frequency limits are also affected by VOO. Refer to Control
Timing Characteristics for limits. See Table 1.

RESET
The RESET input is not required for start-up but can be
used to reset the MCU's internal state and provide an orderly
software start-up procedure. Refer to the Reset section for a
detailed description.
TIMER
The TIMER input may be used as an external clock for the
on-chip timer. Refer to Timer section for a detailed description.
NUM -

en
a::
w

EXTERNAL CLOCK - An external clock should be applied to the OSC1 input with the OSC2 input not connected,
as shown in Figure 7(e). An external clock may be used with
either the RC or crystal oscillator mask option. toxOV or
tlLCH do not apply when using an external clock input.

NON-USER MODE

This pin is intended for use in self-check only. User applications should connect this pin to ground through a 10 kO
resistor.

2-153

CDP6805G2,CDP6805G2C
1 MHz

4MHz

Units

400
5
0.008
15-40

75
7

Il
pF

0.012
15-30

I'F
pF

RSMAX
Co

'21
COSCI

15-30
10
30

COSC2

Rp
Q

15-25

pF

10

Mil

40

-

Crystal Parameters

CDP6805G2
OSCI

39

~~

OSC2

Rp

38

~

COSCI

-3-8----~IO~I----~39

COSC2

Crystal Oscillator Connections

Equivalent Crystal Circuit
(a)

CDP6805G2

CDP6805G2
OSCI

OSCI

OSC2

39

OSC2

!38

Unconnected

R

External Clock

fbI

RC Oscillator Connection

(c) External Clock Source Connections

Fig. 7 - Oscillator connections.

'0.6

.

1;
z
:I

g

2
I

r----.

•

IL

0:

6
4

0:
0

2

!c

r-,..

4

~

!

......

,

"

::::0, •

.,u
0

•
6
4

2
D.CII

z

•

•

0

10

•

4

•

RESISTANCE 'kill

100

Z

4

•

o·

1000

92CS-S8I02

Fig. 8 - Typical frequency vs. resistance for RC oscillator option only.

2-154

CDP6805G~CDP6805G2C
PAO-PA7
These eight I/O lines comprise Port A. The state of any
pin is software programmable. Refer to Input/Output Programming section for a detailed description.

PDQ-P07
These eight lines comprise Port D. PD4-PD7 also are
capable of driving LED's directly. The state of any pin is software programmable. Refer to the Input/Output Programing
section for a detailed description.

PBO-PB7
These eight lines comprise Port B. The state of any pin is
software programmable. Refer to Input/Output Programming section for a detailed description.

INPUT/OUTPUT PROGRAMMING
Any port pin may be software programmed as an input or
output by the state of the corresponding bit in the port Data
Direction Register (DDR)' A pin is configured as an output if
its corresponding DDR bit is set to a logic' 1.' A pin is configured as an input if its corresponding DDR bit is cleared to
a logic '0.' At reset, all DDRs are cleared, which configures
all port pins as inputs. A port pin configured as an output
will output the data in the corresponding bit of its port data
latch. Refer to Figure 9 and Table 2.

PCO-PC7
These eight lines comprise Port C. The state of any pin is
software programmable. Refer to the Input/Output Programming section for a detailed description.

Internal
CDP6805G2
Connections

Typical Port
Data Direction
Register

7

6

5

4

P-7

P-6

P-5

P-4

2

0

Typical Port
Register

Pin

P-3

P-2

P-l

p-o

Ibl
Fig. 9 - Typical port I/O circuitry.

TABLE 2 - I/O PIN FUNCTIONS
R/W
0
0

1
1

DDR
0

1
0
1

I/O Pin Function
The I/O pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch and output to the I/O pin.
The state of the I/O pin is read.
The I/O pin is in an output mode. The output data latch is read.

2-155

COP6805G~COP6805G2C

SELF-CHECK
The CDP6805G2 self-check is performed using the circuit
in Figure 10. Self-check is initiated by tying NUM and
TI MER pins to a logic 1 then executing a reset. After reset,
five subroutines are called that execute the following tests:
1/0- Functionally exercise port A, B, C, D
RAM - Walking bit test
ROM-Exclusive OR with odd l's parity result
Timer- Functionally exercise timer
Interrupts- Functionally exercise external and timer interrupts
Self-check results are shown in Table 3. The following
subroutines are available to user programs and do not require any external hardware.
RAM SELF-CHECK SUBROUTINE
Returns with the Z-bit clear if any error is detected; otherwise the Z-bit is set.
The RAM test must be called with the stack pointer at
$07F. When run, the test checks every RAM cell except for
$07F and $07E which are assumed to contain the return address.
A and X are modified. All RAM locations except the
top 2 are modified. (Enter at location $1 F80.)

ROM CHECKSUM SUBROUTINE
Returns with Z-bit cleared if any error was found,
otherwise Z = 1. X = 0 on return, and A is zero if the test
passed. RAM locations $040-$043 are overwritten.
(Enter at location $1 F9B.)
TIMER TEST SUBROUTINE
Return with Z-bit cleared if any error was found; otherwise
Z=l.
This routine runs a Simple test on the timer. In order to
work correctly as a user subroutine, the internal clock must
be the clocking source and interrupts must be disabled.
Also, on exit, the clock will be running and the interrupt
mask not set so the caller must protect himself from interrupts if necessary
A and X register contents are lost; this routine counts
how many times the clock counts in 128 cycles. The
number of counts should be apower of two since the
prescaler is a power of two. If not, the timer probably is
not counting correctly. The routine also detects if the
timer is running at all. (Enter at location $1 FB5.)

MEMORY
The CDP6805G2 has a total address space of 8192 bytes
of memory and I/O registers. The address space is shown in
Figure 11.

r----

lE
c.:>

ii

EA= PC+ 1; PC-PC+2

BIT MANIPULATION INSTRUCTIONS
The MPU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space, where all
port registers, port DDR's, timer, timer control, and on-chip
RAM reside. An additional feature allows the software to
test and branch on the state of any bit within these 256 locations. The bit set, bit clear and bit test and branch functions
are all implemented with a single instruction. For the test
and branch instructions the value of the bit tested is also
placed in the carry bit of the Condition Code Register. Refer
to Table 8 for instruction cycle timing.

o
a:

CDP6805GZCDP6805G2C
INDEXED, 8-BIT OFFSET

added to the PC ifllM'ld only if the branch condition is
true. Otherwise, control proceeds to the next
instruction. The span of relative addressing is limited to
the range of -126 to +129 bytes from the branch
instruction opcode location.

Here the EA is obtained by adding the contents ofthe
byte following the opcode to that of the index register.
The operand is therefore located anywhere within the
lowest 511 memory locations. For example, this mode
of addressing is useful for selecting the m-th element in
an n element table. All instructions are two bytes. The
contents of the index register (X) is not changed. The
contents of (PC + 1) is an unsigned 8-bit integer. One
byte offset indexing permits look-up tables to be easily
accessed in either RAM or ROM.

BIT SET/CLEAR
Direct addressing and bit addressing are combined in instructions which set and clear individual memory and I/O
bits. In the bit set and clear instructions, the byte is specified
as a direct address in the location following the opcode. The
first 256 addressable locations are thus accessed. The bit to
be modified within that byte· is specified with three bits of the
opcode. The bit set and clear instructions occupy two bytes,
one for the opcode !including the bit numbed and the
second to address the byte which contains the bit of interest.
EA=(PC+1); PC-PC+2
Address Bus High-O; Address Bus Low-(PC+ 1)

EA= X + (PC + 1); PC-PC +2
Address Bus High-K; Address Bus Low-X+ (PC+ 1)
Where: K=The carry from the addition of X+ (PC+ 1)
INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode the
effective address is the sum of the contents of the
unsigned 8-bit index register and the two unsigned
bytes following the opcode. This addressing mode can
be used in a manner similar to indexed 8-bit offset,
except that this three byte instruction allows tables to
be anywhere in memory (e.g., jump tables in ROM).

BIT TEST AND BRANCH
Bit test and branch is a combination of direct addressing,
bit addressing and relative addressing. The bit address and
condition (set or clead to be tested is part of the opcode.
The address of the byte to be tested is in the single byte immediately following the opcode byte (EA1). The signed
relative 8-bit offset is in the third byte (EA2) and is added to
the PC if the specified bit is set or clear in the specified
memory location. This single three byte instruction allows
the program to branch based on the condition of any bit in
the first 256 locations of memory.

EA=X+[(PC+l):(PC+2)]; PC-PC+3
Address Bus High - (PC + 1) + K;
Address Bus Low-X+(PC+2)
Where: K = The carry from the addition of X + (PC + 2)
RELATIVE

EA1=(PC+l)
Address Bus High-O; Address Bus Low-(PC+ 1)
EA2= PC+ 3+ (PC+2); PC-EA2 if branch taken;
otherwise PC-PC+3

Relative addressing is only used in branch
instructions. In relative addressing the contents of the
8-bit signed byte following the opcode (the offset) is

2-166

TABLE 5 - REGISTER/MEMORY INSTRUCTIONS
Addressing Modes
Immediate

Op
Code

#

#

Bytes

Cycler.

3

E6

2

4

D6

3

5

3

EE

2

4

DE

3

5

E7

2

5
5

D7

3

6

Op
Code

#

#

#

#

Bytes

Cycles

Op
Code

#

Cycles

Op
Code

#

Bytes

Bytes

Cycles

Load A from Memory

LDA

A6

2

2

B6

2

3

C6

3

4

F6

1

Load X from Memory

LDX

AE

2

2

BE

2

3

CE

3

4

FE

1

Store A in Memory

STA

-

-

-

87

2

4

C7

3

F7

i

4

STX

-

-

-

BF

2

4

CF

3

5
5

FF

1

4

EF

3

6

AB

2

2

BB

2

3

CB

3

4

FB

1

3

EB

2
2

DF

ADD

4

DB

3

5

AOC

A9

2

2

89

2

3

C9

3

4

F9

1

3

E9

2

4

09

3

5

SUB

AO

2

2

BO

2

3

CO

3

4

FO

1

3

EO

2

4

DO

3

5

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

3

C2

3

4

F2

1

3

E2

2

4

02

3

5

AND Memory to A

AND

A4

2

2

B4

2

3

C4

3

4

F4

3

E4

2

4

04

3

5

OR Memory with A

ORA

AA

2

2

BA

2

3

CA

3

4

FA

1
1

3

EA

2

4

DA

3

5

A8

2

2

B8

2

3

C8

3

4

F8

1

3

E8

2

4

D8

3

5

A1

2

2

B1

2

3

C1

3

4

Fl

1

3

E1

2

4

Dl

3

5

0::1
CJ!

In

Memory

Exclusive OR Memory
with A

EOR

Arithmetic Compare A
L with Memory
Arithmetic Compare X
with Memory

I

I

i

i

Memory with
A I Logical Compare}

CPX

A3

2

2

B3

2

3

C3

3

4

F3

1

3

E3

2

4

D3

3

5

BiT

A5

2

2

B5

2

3

C5

3

4

F5

1

3

E5

2

4

D5

3

5

I Jump Unconditional

JMP

-

-

--

BC

2

2

CC

3

3

FC

1

2

EC

2

3

DC

3

4

LJurnP to Subroutine

JSR

=_1

-

--

BD

2

5

CD

3

6

FD

1

5

ED

2

6

DD

3

7

TABLE 6 - READ/MODIFY/WRITE INSTRUCTIONS

!

Inherent (X)

Ci'l

Op
Code

#

#

Bytes

Cycles

Op
Code

Indexed
(No Offset)

Direct

#

#

Bytes

Cycles

Op
Code

#

#

Bytes

Cycles

~

Indexed
(8-Bit Offset)

Op
Code

#

#

Bytes

Cycles

(")

Op
Code

#

#

Bytes

Cycles

Increment

INC

4C

1

3

5C

1

3

3C

2

5

7C

1

5

6C

2

6

Decrement

DEC

4A

1

3

5A

1

3

3A

2

5

7A

1

5

6A

2

6

CLR

4F

1

3

5F

3

3F

2

5

7F

1

2

6

43

1

3

53

3

33

2

5

73

1

5
5

6F

COM

1
1

63

2

NEG

40

1

3

50

1

3

30

2

5

70

1

5

60

2

Clear
Complement

Negate
12'5 Complement!
i
Rotate Left Thru Carry

I Rotate Right Thru
Carry
. Logical Shift Left

I

\

I

6

I

ROL

49

1

3

59

1

3

39

2

5

79

1

5

69

2

6

46

1

3

56

1

3

36

2

5

76

1

5

66

2

6

3

1

3

38
34

2

5

78

1

5

66

2

5

74

1

64

3

37

2

5

17

1

5
5

2
2

6

3

67

2

6

3

3D

2

4

7D

1

4

6D

2

5

LSL

48

1

LSR

1

3

58
54

Aflthmetlc Shift Right

ASR

44
47

1

3

57

1
1

TST

4D

1

3

5D

1

for Negative
or Zero

6

-----1

ROR

Logical Shift Right

I Test
I

I Mnemonic

~

m
CJ!

Addressing Modes

Function

Ci'l

!'3

<:)

Inherent (A)

I

"t:J
<:)

I

I Bit Test

I

g
0)

CMP

I
I

#
Cycles

#
Cycles

I Subtract Memory

-..j

#
Bytes

#
Bytes

Store X

(j)

Op
Code

Op
Code

Add Memory to A
Add Memory and
Carry to A

f\)

Indexed
(l6-Bit Offset)

Indexed
(8-Bit Offset)

Mnemonic

Function

..'..

Indexed
(No Offset)

Extended

Direct

I

~CROCONTROL~;R-;a

I

I

6

j

CDP6805G~CDP6805G2C
TABLE 7 - ItRANCH INSTRUCTIONS

,

Relative Addressing Mode
Function
Branch Always
Branch Never
Branch IFF Higher

IFF
IFF
IFF
IFF

23
24
24
25
25
26
27
28

3
3
3
3
3
3
3
3

29
2A

2
2

3
3

2B
2C
20
2E
2F
AO

2
2
2
2

3
3
3
3
3
6

BNE
BEQ
BHCC
BHCS

Plus
Minus
Interrupt Mask Bit is Clear
Interrupt Mask Bit is Set

BPl
BMI
BMC
BMS
Bil
BIH
BSR

Branch I FF Interrupt Line is Low
Branch IFF Interrupt line is High
Branch to Subroutine

3
3

2
2
2
2
2
2
2
2

BCS
(BlO)

Branch IFF Half Carry Set

Cycles
3

2
2
2

21
22

BlS
BCC
(BHS)

#

Bytes

20

BRA
BRN
BHI

Branch I FF lower or Same
Branch I FF Carry Clear
IBranch IFF Higher or Same)
Branch IFF Carry Set
(Branch IFF lower)
Branch IFF Not Equal
Branch I FF Equal
Branch I FF Half Carry Clear
Branch
Branch
Branch
Branch

Op
Code

Mnemonic

2
2

TABLE 8 - BIT MANIPULATION INSTRUCTIONS

Bit Setl Clear
Function
Branch IFF Bit n is Set
Branch IFF Bit n is Clear
Set Bit n
Clear Bit n

Mnemonic
BRSET n (n~O .. 7)
BRClR n (n~O .. 71
BSET n (n~0 ... 7)
BClR n

(n~0 ... 7)

#

Op
Code
-

Bytes
-

-

-

10+2-n

2

11 +2-n

2

Addressing Modes
Bit Test and Branch
Op
#
#
#
Cycles
Cycles
Code
Bytes
2-n
3
5
01 + 2-n
3
5
5
5

TABLE 9 - CONTROL INSTRUCTIONS
Inherent
Function
Transfer A to X
Transfer X to A
Set Carry Bit
Clear Carry Bit
Set Interrupt Mask Bit
Clear Interrupt Mask Bit
Software Interrupt
Return from Subroutine
Return from Interrupt
Reset Stack Pointer
No-Operation
Stop
Wait

Mnemonic
TAX
TXA
SEC
ClC
SEI
CLI
SWI
RTS
RTI
RSP
NOP
STOP
WAIT

2-168

Op
Code
97
9F

99
9B
9B
9A

83
81

80
9C
90
8E
8F

#

#

Bytes
1
1
1
1
1
'1

Cycles

1
1
1
1
1
1
1

2
2
2
2
2
2
10
6
9
2
2

2
2

TABLE 10 - INSTRUCTION SET OPCODE MAP

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5

n~o

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9
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fro
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5

, BCl~~c
7

2
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s
BSE!~c 2
5

BRCl:i:

2 BCl~~c

BRSEJ~

5

2 BSE~tc

5

5

BRCL::'

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i3BRSEJ¥B . 2 8SE~~c
5

13BRCl:T5B

2
2
2
2

5

2 BCl~~c

2

0'

13BRSEJ~B 2 BSE~~c 2

.•'
I ,BRCl~T6A I ,BCl~~c
o •

5

5

' ,BRSEJ1. i ,BSE!~c
5

BRClR7
BTB
3

2

BClR7 •
esc

3
BRNREl
3
BHIREl
5
3
BlSREl 2 COMDIA
3
5
BCCREL • 2 lS~TA
3
BCSA..
5
3
BNEAFl , RORDIA
3
5
ASRDIA
BEOREL
5
3
BHC~EL 2 lSlDIA
5
3
BHC~EL 2 ROlDIA
3
5
BPlAEL . 2 DECDIA
3
BMIREl
5
3
BM~EL 2 INC DIA

, BM~ ..
3
, Bll A..
BIH
2

•
AEl

TSTolA

0'':0

01~'

NEG·
INH

NEG
1

2 NEG

IXI

8

0111

,000

NEG'

RTI

IX

1

1

9
INH

1

RTS'NH

3

1

COM~H

1

3

1

lSR~H

3
ROR~>
3

1

ASR~H

3

1

LSl~NH

1

1
1

1
1

3
INCA
INH
3
TSTA
NH

6

3

6

COM~H 2 COMIXI
lSRX

INH

3

1

,
1

3

ROlA
INH
3
DECA
INH

3

9

A

DIR
8

,001

1010

1011

1

,
1
1

2

COM
1

LSR

lSR
IX'

1

6
3
INCX
INC
INH 2
IX'
3
5
TST
TSTX
IXI
INH 2

1

SWI
INH

5

IX

ROR
IX

1

,

ASR

5

IX

1

5

LSL
IX

1

5

ROl
1

IX

1

5

, DEC IX

1
1

5

INC
1

,

IX

1

4

TST

IX

2

CLR

5

DIA

1

3
ClRA
INH

1

3
6
ClRX
ClR
INH 2
IXI

1
1

5

CLR
1

IX

,

IMM

2

2
TAX
INH
2
2
ClC'NH 12 EOR
IMM
2
2
SEC
ADC
INH 2
IMM
2
ORA L
CLI
INH 2
IMM
SEI L
ADD L
INH 12
IMM
2
RSP
INH
2
6
NOP
BSR
INH 2
AEl

2

STOP
INH
2
WAIT
INH

SUB '
IMM
2
CMP

12 SBCIMM
2
CPX
IMM
2
2
AND
IMM
2
I, BI\M"
2
12 LD~MM

5

6

RORX
2 ROR
I
IXI
3
6
ASR
ASRX
IXI
INH
6
3
LSLX
2 LSL
INH
IX'
3
6
ROLX
2 ROl
lNH
IX'
3
6
DECX
DEC
INH 2
IXI

IX

2

10

5

1

2
TXA
INH

2
2
2

Inherent
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
Indexed (No Offset)
Indexed, 1 Byte (S-Bill Offset
Indexed,2 Byte (l6-Bit) Offset

1X2

,too

SUB 3
~DI
3
CMP
DIA
3
SBC
DIA
3
CPX
DIA
3
ANDOIA

4

13 SUB"T

,

5

3

CMP

4

SBC
EXT

3

SBC

3

CPX
EXT

3

CPX

4

, SUB,.,
4

IX2

CMP
IXI
2

5

4

IX2
5

4

IXL

2

SBC

IXI

.~ CPX IXI

3 AN'ln

3. ANDIX2

4

5

4

DlA I, BIT"T
4
3
LDA
LDA
EXT
DIA 3
2

3 BIT IX2

2 BIT IX.

5

4

BIT

,

3

,

4

2 STADIA 13 ST";,XT
4
3
EOR
DIA 1 3 EOREXT
4
3
ADC
ADC
DIA 3
EXT
2
ORA •
ORA
DIA 3
EXT
2

3
3

LDA
STA

1X2

2

2
2

EOR

IX2

3
3

2

EOR

STX
EXT

IX2

2

ORA'
IX2

2

STX
3

Ix2

IXI

IXI

s

IXI

1

1

CPX 3
IX
3
AND
IX
3
BIT IX
3
lDA
IX

IXI

1

2
0010

3
0011

4

O1~'

EOR
1

ADC

IX
3

'000

IX

'00'

ORA'
IX

,010

lOll
1100

ADD
IXI

1

2

JMP 3
IXI

1

JMP 2
IX

2

JSR 6
IXI

, JSR IX'
, LDX IX

3

5

IXI

STX
1

U!

Ci)

~

~

A

m

8

<:)

C

U!

Ci)

',01D

I\)

C")

E
1110

4

IX

<:)

9

1

IXI

00

8

1

STX

0)

7

IXI

LDX

'"

6
0110

ORA
IX'

4

g

0100

0111

2

2

,

0001

IX
3

ADD'
IX

2

J:n

4

STA

4

ADC

6

3

1

SBC 3
IX

4

4

STX 4
DIR

lDA
STA

5

ADC

ADD 5
ADD'
ADO
2
DIA 3
EXT 3
1<2
4
2
3
JMP
JMP
JMP
DIA 3
EXT 3
1<2
2
JSR 5
JSR 6
JSR
DIA 3
EXT 3
1<2
2
LDX 2
LDX 3
lDX 4
LDX •
2
IMM 2
DIA 3
EXT 3
IX2
2

AND

5

3

1

4

0

IX2

SUB 3
1
IX
3
CMP
I
IX

4

5

2

H~Low

1111

1110

SUB","

4

CMP
EXT
3
3

E

D

1101

4

Abbreviations for Address Modes
INH
IMM
DIR
EXT
REL
BSC
BTB
IX
IXl
IX2

,

Reaister/Memorv

Control
I

o~o

3

INH

,

6

4

3

R..d/Modily/Wr~.
IN

F
1111

,

LEGEND

•

Mne~~~

~~

:;;;>

,?1xl

Cycles - -_ _ _ _- '

IM'CROCONTROLLER~-lI

(XXX)

"

:.j

Opcode in Hexadecimal

Opcode in Binary

Address Mode

CDP6805GZCDP6805G2C
TABLE 11 -INSTRUCTION SET
Addressing Modes
Mnemonic

Inherent

ADC
ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
CLI
CLR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
LDA
LDX
LSL
LSR
NEG
NOP
ORA
ROL
ROR
RSP
RT!
RTS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT

Indexed
(8 Bits)

Indexed
(16 Bits)

X
X
X

X
X
X

Immediate

Direct

Extended

X
X
X

X

X

X

X

I<

I<

X
X
X

X

X
X

X
X

Relative

Condition Codes

Indexed
INo Offset)

X

Bit

Setl
Clear

Bit
Test &
Branch

A
A

•
•••
•

X
X

X
X

X
X
X
X
X
X

X

X

X

I

••

N Z C
A

A

A

A IA

A
A
A

A
A
A

•••
•
•••
•••

••
••
••

X
X
X

X

H

A

X

X
X
X
X
X
X
X
X
X

X
X
X
X

0
X

X

X

X
X

X

X

X
X
X
X
X
X
X
X
X

X

X
X

X
X
X
X
X
X

X
X
X
X
X
X
X

X
X
X
X
X

X

0

X
X

X
I<

X
X
X
X
X
X
X
X
X
X
X

X
X
X

X

X
X
X
X

X

X

X

X

X

X

X

X

X

X

X

X
X

X
X

X
X

X
X

X
X

X

X

X

Condition Code Symbols

H Half Carry IFrom Bit 31
I

Interrupt Mask

N Negative ISign Bitl
Z Zero
C

Carry I Borrow

A
•

Test and Set ,f True. Cleared Otherwise.
Not Affected
Load CC RegIster From Stack
Cleared

Set

2-170

A

1
A A
A 1
A A
A
A
A

0

A
A
A
A

A

ilL

A

A

A

•

A

A

A

A

A

A

A

A

A
1

A

A

A
A

A

A

A

A
A
A

• •

X
X
X

X
X

••
•••
••
•
••
••
••
• 1""•• ••
•• •
•• •
••• ••0
•

••
•• •• •••
•

X

X
X

X
X
X
X
X

II.
A
A
A
A
A

X

X
X
X
X
X
X
X
X
X
X
X

X

X
X
X
X

A

II.

A
A

X

X
X
X

•

~.

X

X

A

•
A
A

••• • • •
•• • • •
••• ••• •• •• •
• •1 • • ••
•0
••• •• • •A ••
•1•••
• •• • • ••
•·1°
•••
A

MICROPROCESSORS
PAGE

CDP68EM05C4
CDP68EM05C4N

CMOS High Performance Silicon Gate 8-Bit Microcontroller Emulator ... . . . . . . . . . 3-3

CDP68EM05D2
CDP68EM05D2N

CMOS High Performance Silicon Gate 8-Bit Microcontroller Emulator .. . . . . . . . . ..

3-9

CDP6805E2, E2C
CDP6805E3, E3C

CMOS 8-Bit Microprocessor. . . . • . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-16

3-1

I
I
I
I
I
I
I

I
I
I
I
I

I
I
I
I
I
I
I
I
I
I

mHARRIS
January

1991

CDP68EM05C4
CDP68EM05C4N
CMOS High Performance Silicon Gate
8-Bit Microcontroller Emulator

Features

Pinouts

• CDP68HC05C4 Mlcrocontroller Emulation
~

CDP68EM05C4
40 LEAD PIGGYBACK PACKAGE

All CDP68HC05C4 Hardware and Software Features,
Except as Noted In this Data Sheet

• Full 8K Byte Address Space Available (7984 Bytes
Available Externally)
• 176 Bytes of On-Chip RAM, No ROM
• Also Can be Used for CDP68HC05C8 Emulation
• Un-Multiplexed External Address and Data Lines
• Available in Two Package Types:
~

CDP68EM05C4 - 40 Lead Piggyback Package with
2764 EPROM Socket Capability

~

CDP68EM05C4N - 68 Lead Plastic Chip Carrier (PLCC)

Description
The CDP68EM05C4 and CDP68EM05C4N Emulator devices
CDP68HC05C4
are functionally equivalent to the
microcomputer, and are designed to permit prototype development and preproduction of systems for mask programmed
applications. Data bus, address bus and control signals are
externally available to provide off chip address capability.

TOP VIEW
RES ET

'iRO
NC
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

3
4
!:)

6
7

B
9
10
11
12
13
14
15
16
17
18
19

(1 )
I
Vp
(2)
2
A12
3
A7
4
2764
A6
5 EPROM
A5
6
A4
7
A3
8
A2
9
Al 10
AODBO..!..!..
DB 1 12
DB2 13
GND 14

28
27 VCC
26 ~
25 VCC

24
23
22
21
20
19

16
17

16

15

CDP68EM05C4
EM UlATOR

VSS

~~
A II

OE

AID
CE
087
086
OBS
0B4
0B3

40
39
38
37
36

VOO
OSCI
OSC2
TCAP
PO-'
3~
TeMP
34
PDS
33
P04
32
P03
31
P02
30
P01
29
poo
28
PCO
27
PCI
26
PC2
25
PC3
24
PC4
23
PCS
22
PC6
21
PC7

CDP68EM05C4N
68 LEAD PLASTIC CHIP CARRIER
TOP VIEW

PAl
PAO_'1
PSO 12
PSI 13

a) CPU oscillator type: C = crystal/ceramic
resonator; R = resistor.

The CDP68EM05C4 and CDP68EM05C4N represent two
package types. The CDP68EM05C4 is available in a piggyback package having the footprint of the 40 lead dual-in-line
package of the CDP68HC05C4 microcomputer. The top of the
piggyback package has socket capability for a 28 lead
EPROM. The CDP68EM05C4N is avaiiable in a 68 lead Plastic
Chip Carrier (PLCC).

© Harris Corporation 1991

60
59
58
57

PD3
PD2
POI
PDO

55
54
53

PC2
PC3

~PCO
PCl

~~; ~:i:i

b) External interrupt sense: EL = negative
edge and ievel sensitive; E = edge only
sensitive.

PB4 --_.
PBS 17
PB6 18
PB7 19
VSS 20
087 _ 21

~~ PC4
SOPC5
49 PC6

I

,!~~~7

DB6-'?-~

DR5 -. ~-~
004 --2"5

I~LWE
~~-CE
~FS

OB3-26
082-

~~~-r~rT~~~~~~~

~RD

File Number

3-3

en
co:

i
en

....

u

c::I

co:

a...

c::I

a:

u

:E

In addition to this feature, the Emulator devices differ from the
CDP68HC05C4 microcomputer as follows: 1) Memory
locations which are occupied as ROM on the CDP68HC05C4
are accessed as external locations with the Emulators.
2) Mask-programmable
options
available
on
the
microcomputer (i.e., CPU oscillator type and external interrupt
sense) are fixed in hardware in the Emulator devices, and are
available as separate Emulator types identified with suffix
letters EC, ELC, ER or ELR. The corresponding option for each
suffix letter is shown below:

Copyright

1
2

2754

CDP68EM05C4, CDP68EM05C4N
Block Diagram
'=:'.L.-!::::.L-,
~-!:=::!!..-l

~ P~ri~:::~R
.--_C""l=OC=KC-_ _ _!l - RESET

L------,--l
PAO
PAl
PORT PA2
A
PA3
110
LINES PAA
PAS
PA6
PA7

DATA
DIR
REG

PORT
B

PB"
PB3
110 PB4
LINES PBS
PB6
PB7

·WE
• DS
• FS

8

ACCUMULATOR
A

CPU
CONTROL

INDEX
REGISTER
X
CONDITION
CODE
S REGISTER CC

DATA
DIR
REG

8

DATA
DIR
REG

6

S

S

PROGRAM
COUNTER
HIGH PCH

8

PROGRAM
COUNTER
lOW PCl

PCO
PCl
PC2
PC3

PC4
PCS
PC6
PC7

PORT
C
1/0
liNES

CPU

STACK
POINTER

PBO
PBl

CE
- iiii.

2 IRQ

AlU

PORTD

PD7

SCI
SYSTEM

RDI (POO)
TDO (PD1)
MISO (PD2)
MOSl (PD3)
SCK(PD4)
SS(PDS)

SPI
SYSTEM
BAUD RATE
GENERATOR

46
BUS
CONTROL

*Not available in the Piggyback package

mmmmIDIDIDt:D
QQQQCQCQ

O_C\lCI)'ltanlD,...

~:c~~~~~:c~~~~~

DATA BUS

ADDRESS BUS

**Pin numbers are for PLCC
package

Memory
The CDP68EM05C4 and CDP68EM05C4N Emulators
each have a total address space of 8192 bytes. The
Emulators have implemented 208 bytes of the address
locations for I/O and internal RAM. The remainder is
available for external memory. The first 256 bytes of
memory (page zero) are comprised of the I/O port locations,
timer locations, 48 bytes of external address space and 176
-bytes of RAM. The next 7936 bytes are available to add ress
external memory. The address map is shown in Figure 1. A
description of the remaining internal addressable functions
can be found in the CDP68HC05C4 data sheet, File No.
2748, see Section 2 of this Data Book.

RD, (CE*) -

Read: A status output which indicates
direction of data flow with respect to external
or internal memory (a low level indicates a
read from memory space). A read from
internal memory or I/O will place data on the
external data bus.

WE** -

Write Enable: An active low strobe pulse
output for use in writing data to external
RAM memory. A low level indicates valid
data on the data bus.

DS** -

Data Strobe: An output signal for use as a
strobe pulse when address and data are
valid. This output is used to transfer data
to or from a peripheral or memory and
occurs any time the Emulator reads or
writes. DS is a continuous signal at fosc + 2
when the Emulator is not in the WAIT or
STOP mode.

FS** -

Fetch Status: An output which indicates an
op code fetch cycle

Signal Descriptions
The following list includes only those additional Signals that
are not available on the CDP68HC05C4 microcomputer.
See the CDP68HC05C4 data sheet for a description of the
remaining signals which are common to the Emulators and
the CDP68HC05C4 microcomputer.
AO-A12 -

Address lines othrough 12.

DBO-DB7 -

Bidirectional 8-bit non-multiplexed data bus
with TIL inputs.

CE, (OE*) -

Chip Enable: An output signal used for_
selecting external memory or I/O. A low level
indicates when external RAM or I/O is being
accessed. The Chip Enable signal will not go
true, however, when addressing the 7
unused locations in the 32 bytes of I/O
space even though the address lines will be
valid.

• CE and Rii are used as OE (Output Enable) and CE (Chip Enable) Signals,
respectively in the Piggyback package.
•• Not available in the Piggyback package.

3-4

CDP68EM05C4, CDP68EM05C4N
0000--

$0000

0000--PORTS
7 BYTES

1/0
32 BYTES

PORT A DATA REGISTER

$00

PORT B DATA REGISTER

SOl

PORT C DATA REGISTER
$OOIF
$0020

0031
0032
EXTERNAL ADDRESS
SPACE
48 BYTES

PORT 0 FIXED INPUT REGISTER

UNUSED
3 BYTES

PORT A DATA DIRECTION REGISTER

\
\

0079

$OO4F
$0050

SERIAL PERIPHERAL
INTERFACE
3 BYTES

OO~O

\
RAM
176 BYTES

SOOBF
$COCO

1

r------

\
\
\
~~:~ \

STACK
64 BYTES

SOOFF
$0100

SERIAL
COMMUNICATIONS
INTERFACE
5 BYTES

0255
0256

\
\
\

TIMER
10 BYTES

\
UNUSED
4 BYTES

\

.OB
SOC

SERIAL COMMUNICATIONS BAUD RATE REGISTER

SOD

SERIAL COMMUNICATIONS CONTROL REGISTER 1

SOE

SERIAL COMMUNICATIONS CONTROL REGISTER 2

'OF

SERIAL COMMUNICATIONS STATUS REGISTER

.,0

SERIAL COMMUNICATIONS DATA REGISTER

$11

\
\
\

i

S08

SERIAL PERIPHERAL DATA I/O REGISTER

\

.,FFF

$07

UNUSED

'OA

\

\

TIMER CONTROL REGISTER

$12

TIMER STATUS REGISTER

$13

INPUT CAPTURE HIGH REGISTER

$14

INPUT CAPTURE LOW REGISTER

$15

OUTPUT COMPARE HIGH REGISTER

$18

OUTPUT COMPARE LOW REGISTER

.17

Co)

COUNTER HIGH REGISTER

$18

CI.

COUNTER LOW REGISTER

$19

Co)

ALTERNATE COUNTER HIGH REGISTI!R

.,A

ii

ALTERNATE COUNTER LOW REGIS~ER

$IB

UNUSED

\

SPACE FOR
USER VECTORS
lBBYTES

UNUSED

SERIAL PERIPHERAL STATUS REGISTER

0031

8175
8178

$06

.09

\

r------

$05

PORT C DATA DIRECTION REGISTER

UNUSED

\

SIFEF
$IFFO

$04

PORT B DATA DIRECTION REGISTER

SERIAL PERIPHERAL CONTROL REGISTER

\
EXTERNAL ADDRESS
SPACE
7936 BYTES

$02
.03

\
8191

.,C

UNUSED

$1D

UNUSED

$IE

UNUSED

.'F

FIGURE 1. ADDRESS MAP.

IRQ (Maskable Interrupt Request)

OSC1,OSC2

Interrupt input trigger sensitivity is available as either
1) negative edge-sensitive only, or 2) both negative edgesensitive and level-sensitive triggering. In the latter case,
either type of input to the IRQ pin will produce the interrupt.
The Emulator completes the current instruction before it
responds to the interrupt request. When the IRQ pin goes
low for at least one tlLlH as defined in the CDP68HC05C4
data sheet, a logic one is latched internally to signify that an
interrupt has been requested. When the Emulator
completes it's current instruction, the interrupt latch is
tested. If the interrupt latch contains a logic one, and the
interrupt mask bit (I bit) in the condition code register is
clear, the Emulator then begins the interrupt sequence. The
IRQ input requires an external resistor to VDD for
"wire-OR" operation.

Oscillator (fOSC) connections. Depending on the Emulator
CPU oscillator type, which is fixed in hardware, the pins can
be configured for either a crystal or ceramic resonator
oscillator, or for an RC oscillator. Alternatively, with either
CPU oscillator type*, an external clock may be used by
applying the external clock signal to the OSC1 input with
the OSC2 pin not connected. The internal clocks are
derived by a divide-by-2 of the oscillator frequency (fOSC).

• The crystaf/ceramic resonator CPU oscillator .type is recommended to
reduce loading on the external clock source.

3-5

en
a:

CI

...enen

CI

a:

CI

a:

Specifications CDP68EM05C4
READ CYCLE TIMING CDP68EM05C4 (Piggyback Emulator)
VDD = 5.0V :t 10%, VSS = OV, TA = 2SOC
UMITS
PARAMETER

MIN

Extemallnput Oscillator Pulse Width, Low or High

TCPL, TCPH

90

Read Cycle

TRC

476

Address Before OE

TOA

50

Access Time From OE

TAO

Access Time From Stable Address

TM

Access Time From CE

TM

-

Data Bus Driven From OE

TEX

0

Address Hold Time Altar OE

TAH

0

MAX

UNITS

-

ns
ns
ns

200

ns

350

ns

350

ns

Data Hold Time Altar Address

TOH

0

Data Hold Time After OE

TDH

0

-

OE High to Data Bus not Driven

THZ

0

60

ns
ns
ns
ns
ns

OSC'

REAO CYCLE

AooR

~~___~_-J~__-J~_-J~_~~_-A

_ _-A_ _
AO-A12

=:t==========~==

OE--t---,I

~TOH

DBO-DR7

____-1__1§~~~~~~~~~~~TDH
DATA VAll 0

--I

o80-OB7 _.r--".J\..Y--...-"-.r---~J'-J

I-- THZ

DATA VALID

FIGURE 3. CONTROL T1MING DIAGRAM FOR
THE CDP68EM05C4 EMULATOR.

FIGURE 2. TYPICAL CYCLE TIMING FOR THE
CDP68EM05C4 EMULATOR.

3-6

Specifications CDP68EM05C4N
READ CYCLE TIMING CDP68EM05C4N (PLCC Emulator)
VDD = 5.OV ± 10%, VSS = OV, TA = 250 C
LIMITS
MIN

MAX

UNITS

Extemallnput Oscillator Pulse Width, Low or High

PARAMETER
TCPL,TCPH

90

-

ns

Read Cycle

TRC

476

-

ns

Address Before Chip Enable

TCA

50

-

ns

Access Time From ChIp Enable

TAC

-

200

ns

Access Time From Address

TM

-

350

ns

Access Time From RD

TM

-

350

ns

Data Bus DrIven From CE

TEX

0

Address Hold Time After CE

TAH

0

Data Hold Time After Address

TOH

0

-

Data Hold Time After CE

TDH

0

-

ns

CE High to Data Bus Not Driven

THZ

0

60

ns

MAX

UNITS

ns
ns
ns

WRITE CYCLE TIMING CDP68EMOSC4N (PLCC Emulator)
VDD = S.OV ± 10%, VSS = OV, TA = 250 C
LIMITS
PARAMETER

MIN

Extemallnput Oscillator Pulse Width, Low or High

TCPL,TCPH

90

-

ns

Write Cycle

TWC

476

-

ns

Address Before CE, WE

TAS

50

DS, WE Pulse Width

TDSP,TWP

200

WE = L to CPU Driving Bus

TWHZ

-

0

Data Set-Up Time

TDS

150

Data Hold Time After WE

TDH

50

Address Valid After WE

TWR

50

WE High to Bus Not Driven

TDOZ

50

I

-

I

INTERNAL FETCH
WRITE

BUS DRIVERS
TURN ON

DATA VALID

FIGURE 4. CDP68EM05C4N EMULATOR TYPICAL CYCLE TIMING

3-7

ns
ns
ns
ns
ns
ns
ns

I

CDP68EM05C4N

--I

OSCt

I--

TCPL

I

READ CYCLE

--I

TCPH

TRC

I'

:::x

AOoA12

-, r-

TCA

~n

I

DS

I

I

I.

f=?AC
080-087

.--1

AO-A12

TAH

CE

'I

AD

:1 ~-lF~~~

C

.....j

~

r-TWR~

,-

m

1

TASr:=-

m

TWp

I(H

-J

I

'-

~

~TDSP

I

OBO-oB7

!-THZ

x:::

r

TAS

,

DS

-I

TWC

I

WE

{DRIVER-S TURN ONX DATA VALID } - TEX

I'

:::J(

=j

[

I

=l

iiii

WRITE CYCLE

x::::

--I r

CE

I-

L-I

I

8.7

,I

1

J

"-

TDH~

TDOZ

TD:ATAVALID

I=TWHZ

FIGURE S. CDP68EMOSC4N EMULATOR CONTROL TIMING DIAGRAMS.

v
ANALOG SIGNALS

55

PORTI-----..{
CDP68EMOSC4

~Kr:==::r:;:::~~~::~;:~-1

MOS1J-

MISO~====1=t=1f===::::::~~~======~

PORT/PORTj---j-Hf-----,

AD

CE

CE

DE

CDP68EM05C4N
EMULATOR
CPU

PORT

AO-A12

.

A

DBO'DB7

FIGURE 6. SERIAL PERIPHERAL INTERFACE (SPI)
BUS SYSTEM.

.
.
..
..

2764
EPROM

ADDR

DATA

FIGURE 7. CDP68EMOSC4N EMULATOR INTERFACED
WITH 2764 EPROM.

Customer Ordering Information
The four available variations should be ordered by the following part number designations:
CDP68EM05C4EC CDP68EM05C4NEC

Edge only sensitive interrupts with
crystal or ceramic resonator osciIiator network.

CDP68EM05C4ELC - Edge and level sensitive interrupts
CDP68EM05C4NELC with crystal or ceramic resonator
oscillator network.

CDP68EM05C4ER CDP68EM05C4NER

Edge only sensitive interrupts,
resistor oscillator network.

CDP68EM05C4ELR CDP68EM05C4NELR

Edge and level sensitive interrupts,
resistor oscillator network.

3-8

mHARRIS

CDP68EM05D2
CDP68EM05D2N
CMOS High Performance Silicon Gate
8-Bit Microcontroller Emulator

January 1991

Pinouts

Features
• CDP68HC05D2 Mlcrocontroller Emulation
~

CDP68EM05D2
40 LEAD PIGGYBACK PACKAGE

All CDP68HC05D2 Hardware and Software Features,
Except as Noted In this Data Sheet

• Full 8K Byte Address Space Available (8064 Bytes
Available Externally)
• 96 Bytes of On Chip RAM, No ROM
• Un-Multiplexed External Address and Data Lines
• Available In Two Package Types
~

CDP68EM05D2 - 40 Lead Piggyback Package with
2764 EPROM Socket Capability

~

CDP68EM05D2N - 68 Lead Plastic Chip Carrier (PLCC)

Description
The CDP68EM05D2 and CDP68EM05D2N Emulator devices
are functionally equivalent to the CDP68HC05D2
microcomputer, and are designed to permit prototype development and preproduction of systems for mask programmed
applications. Data bus, address bus and control signals are
externally available to provide off chip
address
capability.
In addition to this feature, the Emulator devices differ from the
CDP68HC05D2 microcomputer as follows: 1) Memory
locations which are occupied as ROM on the CDP68HC05D2
are accessed as external locations with the Emulators.
2) Mask
programmable
options
available
on
the
microcomputer (i.e., CPU oscillator type, external interrupt
sense and timeout delay for power on Reset or exit from STOP
mode) are fixed in hardware in the Emulator devices, and are
available as separate Emulator types identified with suffix
letters. See "Customer Ordering Information" in this data sheet
for a description of available emulator types.
The CDP68EM05D2 and CDP68EM05D2N represent two
different package types. The CDP68EM05D2 is available in a
piggyback package having the footprint of the 40 lead dual-inline package of the CDP68HC05D2 microcomputer. The top of
the piggyback package has socket capability for a 28 lead
EPROM. The CDP68EM05D2N is available in a 68 lead PlastiC
Chip Carrier (PLCC).

TOP VIEW
RESET

TRO
NC
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAD
PBO
PBI
PB2
PB3
PB4
PB5
PB6
PB7
VSS

1991

(1 )

Vp
(2)
Al
~
A7
6
A6
7
All
8
A4
9
2764
A3
10
EPROM
A2
11
A1
12
AO
13
14 OBO
OBI
III
OB2
16
GNO
17
18
COP68EM0502
19
EM ULATOR

VCC
j5(l"g

VCC
A8
A9
Al1

Of

AID
CE
OB7
OB6
OB5
OB4
OB3

40
39 VOO
OSCI
38
OSC2
37
TCAP
36 P07
35 TCMP
34 PO!!
33
PO'!
32 P03
31
P02
30
POI
29
POO
28 PCO
27 PCI
26 PC2
25
PC3
24
PC4
23 PC5
22 PCS
21 PC7

CDP68EM05D2N
68 LEAD PLASTIC CHIP CARRIER
TOP VIEW

PAl
PAD
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
VSS

11
12
13
14
15
16
17
18
19
20
21

OB7
OB6 22
23
OB5 24
OB4 25
OB3 26
OB2

Copyright @ Harris Corporalion

1
2
3
4

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
.!5
44

File Number

3-9

P03
PD2
POI
POO
PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7
OS
WE
CE
FS
fill

2755

U)

a:

CI

U)
U)

w

u

CI

a:

a...

CI

a:

u
ji

CDP68EM05D4CDP68EM05D2N
OSCI

OSC2
INTERNAL
PROCESSOR CLOCK

.---------------~
.-------------IRQ
PAO
PAl
PORT
A
I/O
LINES

PA2
PA3
PA4
PA5

ACCUMULATOR
DATA
DIR
REG

PA6
PA7

PBO
PBl
PORT PB2
B
PB3
I/O
PB4
LINES PB5

A

8

CPU
CONTROL

INDEX
REGISTER

8

X

5

CONDITION
CODE
REGISTER CC

DATA
DIR
REG

PORT
C
REG

PC6
PC7
CPU

TO TIMER SYSTEM
PD7

STACK
POINTER
6
DATA
DIR
REG

PB6
PB7

5

S
PROGRAM
COUNTER
HIGH PCH

6

PROGRAM
COUNTER
LOW PCL

PCO
PCl
PC2
PORT
PC3
C
PC4
I/O
PC5 LINES

DATA
DIR
REG

ALU

TOSCI (POO)
TOSC2 (POI)
MISO(PD2)
MOSI (PD3)
(PD4)
SS (PD5)

~K

!

I

TIMER
OSCILLATOR

SPI
SYSTEM

SPI
SYSTEM

BUS
CONTROL

*NOT AVAILABLE IN PIGGYBACK
PACKAGE.

Memory
The CDP68EM05D2 and CDP68EM05D2N Emulators
each have a total address space of 8192 bytes. The
Emulators have implemented 128 bytes of the address
locations for I/O and internal RAM. The remainder is
available for external memory. The first 256 bytes of
memory (page zero) are comprised of the I/O port locations,
timer locations, 128 bytes of external address space and 96
bytes of RAM. The next 7936 bytes are available to address
external memory. The address map is shown in Figure 1. A
description of the remaining internal addressable functions
can be found in the CDP68HC05D2 data sheet, File No.
1557.1, see Section 2 of this Data Book.

RO, (CE*) -

Read: A status output which indicates
direction of data flow with respect to external
or internal memory (a low level indicates a
read from memory space). A read from
internal memory or I/O will place data on the
external data bus.

WE** -

Write Enable: An active low strobe pulse
output for use in writing data to external
RAM memory. A low level indicates valid
data on the data bus.

OS** -

Data Strobe: An output signal for use as a
strobe pulse when address and data are
valid. This output is used to transfer data
to or from a peripheral or memory and
occurs any time the Emulator reads or
writes. OS is a continuous signal at fosc + 2
when the Emulator is not in the WAIT or
STOP mode.

FS** -

Fetch Status: An output which indicates an
op code fetch cycle

Signal Descriptions
The following list includes only those additional signals that
are not available on the CDP68HC05D2 microcomputer.
See the CDP68HC05D2 data sheet for a description of the
remaining signals which are common to the Emulators and
the CDP68HC05D2 microcomputer.
AO-A 12 -

Address lines 0 through 12.

OBO-OB7 -

Bidirectional8-bit non-multiplexed data bus
with TIL inputs.

CE, (OE*) -

Chip Enable: An output signal used for
selecting external memory or I/O. A low level
indicates when external RAM or I/O is being
accessed. The Chip Enable signal will not go
true, however, when addressing the 10
unused locations in the 32 bytes of I/O
space even though the address lines will be
valid.

* CE and RD are used as Oe (Output Enable) and CE (Chip Enable) signals,
respectively In the Piggyback package.
** Not available in the Piggyback package.

3-10

CDP68EM05D2, CDP68EM05D2N

000"0--

SOOOO

1/0
32 BYTES
S001F
S0020

0031
0032
EXTERNAL
ADDRESS SPACE
128 BYTES

RAM
96 BYTES

SOOBF
SOOCO

UNUSED
2 BYTES

\
SERIAL PERIPHERAL
INTERFACE
3 BYTES

0159
0160

S009F
SOOAO

t-------

t

UNUSED
5 BYTES

\
\
~~:~ \

TIMER
10 BYTES

\

$02

PORT D DATA REGISTER

S03
S04

PORT C DATA DIRECTION REGISTER

S08

PORT D DATA DIRECTION REGISTER

$07

.09

SERIAL PERIPHERAL CONTROL REGIST·ER

SOA

SERIAL PERIPHERAL STATUS REGISTER

SOB

SERIAL PERIPHERAL DATA 1/0 REGISTER

SOC

UNUSED

SOD

\

\

\
\

SPACE FOR
USER VECTORS
18 BYTES

\

$OF

UNUSED

$10

UNUSED

$11
$12
$13

INPUT CAPTURE HIGH REGISTER

$14

INP!,T CAPTURE LOW REGISTER

$15

OUTPUT COMPARE HIGH REGISTER

$16

OUTPUT COMPARE LOW REGISTER

$17

COUNTER HIGH REGISTER

$18

COUNTER LOW REGISTER

$19

ALTERNATE COUNTER HIGH REGISTER

S1A

ALTERNATE COUNTER LOW REGISTER

$1B

UNUSED

S1C

\

8175
8178

SOE

UNUSED

TIMER STATUS REGISTER

\

\

UNUSED

TIMER CONTROL REGISTER
0031

\

S08

UNUSED

UNUSED
1 BYTE

\

\

S1FFF

PORT C DATA REGISTER

.05

SPECIAL PORT
CONTROLI
STAT REGISTER

\

\

i

SOl

PORT A DATA DIRECTION REGISTER

UNUSED 2 BYTES

\
\

r-------

SOO

PORT B DATA REGISTER

UNUSED

\

EXTERNAL
ADDRESS SPACE
7936 BYTES

$1FEF
S1FFO

PORT A DATA REGISTER

PORT B DATA DIRECTION REGISTER

\

STACK
64 BYTES 0255
0258

SOOFF
$0100

0000--PORTS
8 BYTES

UNUSED

$1D

SPECIAL PORT CONTROL/STAT REGISTER

S1E

UNUSED

S1F

8191

FIGURE 1. ADDRESS MAP.

IRQ (Maskable Interrupt Request)

OSC1,OSC2

Interrupt input trigger sensitivity is available as either
1) negative edge sensitive only, or 2) both negative edge
sensitive and level sensitive triggering. In the latter case,
either type of input to the IRQ pin will produce the interrupt.
The Emulator completes the current instruction before it
responds to the interrupt request. When the IRQ pin goes
low for at least one tlLlH as defined in the CDP68HC05D2
data sheet, a logic one is latched internally to signify that an
interrupt has been requested. When the Emulator
completes it's current instruction, the interrupt latch is
tested. H the interrupt latch contains a logic one, and the
interrupt mask bit (I bit) in the condition code register is
clear, the Emulator then begins the interrupt sequence. The
IRQ input requires an external resistor to VDD for
"wire-OR" operation.

Oscillator (fOSC) connections. Depending on the Emulator
CPU oscillator type, wh ich is fixed in hardware, the pins can
be configured for either a crystal or ceramic resonator
oscillator, or for an RC oscillator. Alternatively, with either
CPU oscillator type*, an external clock may be used by
applying the external clock signal to the OSC1 input with
the OSC2 pin not connected. The internal clocks are
derived by a divide by 2 of the oscillator frequency (fOSC).

* The

3-11

crystal/ceramic resonator CPU oscillator type is recommended to
reduce loading on the external clock source.

Vol

a:

C)
Vol
Vol

...

~

C)

a:
CI-

C)

a:
...,

:i

Specifications CDP68EM05D2
READ CYCLE TIMING CDP68EMOSD2 (Piggyback Emulator)
VDD = S.OV ± 10%, VSS = OV, TA = 2SoC
LIMITS
PARAMETER

MIN

Extemallnput Oscillator Pulse Width, Low or High

TCPL,TCPH

90

Read Cycle

TRC

476
SO

Address Before OE

TOA

Access Time From OE

TAO

Access TIme From Stable Address

TM

Access Time From CE

MAX

UNITS

-

ns
ns
ns

200

ns

350

ns

TM

-

350

ns

-

ns

Data Bus Driven From OE

TEX

0

Address Hold TIme After OE

TAH

0

Data Hold Time After Address

TOH

Data Hold Time After OE
OE High to Data Bus not Driven

ns

0

-

TDH

0

-

ns

THZ

0

60

ns

ns

OSC'

osc

t

READ CYCLE

AO-A12

.:::t==========~==

I..-TOH
I.-TOH
DATA VAll 0

BUS DRIVERS
TURN ON

DATA VALID

FIGURE 3. CONTROL TIMING DIAGRAM FOR
THE CDP68EM05D2 EMULATOR.

FIGURE 2. TYPICAL CYCLE TIMING FOR THE
CDP68EM05D2 EMULATOR.

3-12

Specifications CDP68EM05D2 N
READ CYCLE TIMING CDP68EM05D2N (PLCC Emulator)
VDD = 5.0V ± 10%, VSS = OV, TA = 2SOC
LIMITS
PARAMETER

MIN

Extemallnput Oscillator Pulse Width, Low or High

TCPL,TCPH

90

Read Cycle

TRC

476

Address Before Chip Enable

TCA

50

Access Time From Chip Enable

TAC

-

Access Time From Address

TAA

Access Time From RD

MAX

-

UNITS
ns
ns
ns

200

ns

-

350

ns

TAA

-

350

ns

Data Bus Driven From CE

TEX

0

-

ns

Address Hold Time After CE

TAH

0

Data Hold Time After Address

TOH

0

Data Hold Time After CE

TDH

CE High to Data Bus Not Driven

THZ

ns

0

-

0

60

ns

MAX

UNITS

ns

ns

WRITE CYCLE TIMING CDP68EM05D2N (PLCC Emulator)
VDD = 5.0V ± 10%, VSS = OV, TA = 2So C
LIMITS
MIN

PARAMETER
Extemallnput Oscillator Pulse Width, Low or High

TCPL,TCPH

90

Write Cycle

TWC

476

Address Before CE, WE

TAS

50

OS, WE Pulse Width

TDSP,TWP

200

WE = L to CPU Driving Bus

TWHZ

Data Set-Up Time

TDS

150

Data Hold Time After WE

TDH

50

Address Valid After WE

TWR

50

WE High to Bus Not Driven

TDOZ

50

3-13

0

-

ns
ns
ns
ns
ns
ns
ns
ns
ns

CDP68EM05D2, CDP68EM05D2N

OSCI
OSC2
CYCLE

I FETCH

I

READ

IIN~~:~All

WRITE

I

FETCH

I

READ

I

INTERNAlIFETCH/
WRITE

I

ADDR~~____~____~~__~~____~____~____~~__~~_ _

I

I
DS
FS
DIIOoDB7

BUS DRIVERS

DATA VALID

TURN ON

FIGURE 4. CDP88EM05D2N EMULATOR TYPICAL CYCLE TIMING.

OSCI

. READ CYCLE

AO-A12

I"

TRC

:::x
-1 r
TCA

DS

c:

il-TAH

-i, I '1'

FI'
Ir----~\....!....__
~~AC :1 ~-lF~~:

I

I.

OBO-087

AO-A12

"I

--I

(DRIVER'S TURN ON
TEX

1=

X DATA VALID

>--

DS

DBa-DB7

--l I-THZ

FIGURE 5. CDP88EM05D2N EMULATOR CONTROL TIMING DIAGRAMS.

3-14

CDP68EM05D2, CDP68EM05D2N

ANALOG SIGNALS

ss
PORT\-----+i
CDP68EM05D2

SCK~====4=~==~:t~===+:;===-~
PORTtMI~~====4=~4=====~===+=+========~J
PORT 1-----+-+-+-----,

MOS1~

iffi

CE

CE

OE
2764
EPROM

COP68EM05D2N
EMULATOR

CPU
PORT

ADDR

AO-A12

DBO·DB7

FIGURE 6. SERIAL PERIPHERAL INTERFACE
(SPI) BUS SYSTEM.

.

DATA

FIGURE 7. CDP68EM05D2N EMULATOR CONTROL
TIMING DIAGRAMS.

r---

rr-

PORT
A

+

,. ,.

4
3

2

,

~

><

>'

,.'"
,-

,.

,
~

, , ,
, ,. ,- ,

1
0

>-

l

OPEN DRAIN
SOFTWARE
PROGRAMMABLE
OUTPUTS

r---

;.{]3~
PORT

rrrf-+---

KEYBOARD
INTERRUPT

RGURE 8. KEYBOARD INTERFACE TO ILLUSTRATE USE OF OPEN DRAIN OUTPUT PORT.

Customer Ordering Information
The eight available variations should be ordered by the
following part number designations:
Edge only sensitive interrupts with
crystal or ceramic resonator oscillator network.

CDP68EMOSD2ERF,
Edge only sensitive interrupts with
CDP68EMOSD2NERF resistor oscillator, 2 Tcycle startup
delay.

CDP68EMOSD2ECF,
Edge only sensitive interrupts with
CDP68EMOSD2NECF external clock source, 2 Tcycle
startup delay.

CDP68EMOSD2LCF,
Edge and level sensitive interrupts
CDP68EMOSD2NLCF with external clock source, 2
Tcycle startup delay.

CDP68EMOSD2ELC,
Edge and level sensitive interrupts
CDP68EMOSD2NELC with crystal or ceramic resonator
oscillator network.

CDP68EMOSD2LR,
CDP68EMOSD2NLR

Edge and level sensitive interrupts
with resistor oscillator network.

CDP68EMOSD2LRF,
CDP68EMOSD2NLRF

Edge and level sensitive interrupts
with resistor oscillator, 2 Tcycle
startup delay.

CDP68EMOSD2EC,
CDP68EMOSD2NEC

CDP68EMOSD2ER,
CDP68EMOSD2NER

Edge only sensitive interrupts with
resistor oscillator network.

3-1S

CDP6805E2,2C
CDP6805E3,3C

mHARRIS

CMOS 8-Bit Microprocessor

January 1991

Hardware Features

Pinouts

• Typical Full Speed Operating Power @ 5V ••••• 35mW
• Typical WAIT Mode Power •••••••••••••••••••••• 5mW
• Typical STOP Mode Power •••••..••••.•••••••••• 251lW

CDP6805E2 40 LEAD DIP
TOP VIEW
RESET

.112 Bytes of On-Chip RAM

L1

os
R,W

• 16 Bidirectional I/O Lines on COP 6805E2

AS

* PA7

.13 Bidirectional I/O Lines on CDP6805E3

~

PA6

* PAS
PA'
PA3
PA2
PAl
PAD
A12
A11
Al0
A9
A8

• Internal 8-Bit Timer with Software Programmable
7-81t Prescaler
• External Timer Input
• Full External and Timer Interrupts
• Multiplexed Address/Data Bus

Vss

10
11
12
13

,."
,.
15

17
18
20

mET

VDD

'0
39
38
37
3.
3'
3.
33
32
31
30
2.
2.
27
2.
2.
2.
23
22
21

TAC

CDP6805E3 40 LEAD DIP
TOP VIEW

....
.. ."''"
..,". ......"••,
.,
... ...

"

TIMER

lIii

P80
PBl
P82
P83
PB.
P8'
PB.
PB7
BO
Bl
B2
B3
B.
B.
B.
87

.,.......

•u
m

..".."

v"

voo

51

LX

OSC2

• Master Reset and Power-On Reset
• CDP6805E2 is Capable of Addressing up to 8K Bytes
of External Memory

'0

m

OSC1

II

OSC2
TINER

51

PI.

II
II

PI.

'01

.

,

so

"
",.
"

'10

t.

,.""

I.

••"

22

17

CDP6805E2 44 PLCC
TOP VIEW

• CDP6805E3 is Capable of Addressing up to 64K Bytes
of External Memory
• Single 3V to 6V Supply
• On-Chip Oscillator
• 40-Pln Dual-In-Llne Package

AS

39

PB'

PA7

38

PIIZ

P"
P"

• 44 Lead Plastic Chip Carrier Package

P,>

P"

•••

P••

• -40 0 C to +85 0 C Operation With CDP6805E2C and
CDP6805E3C

Software Features
• Efficient Use of Program Space

P'>

•••

P••

P,7

PAt

BO

P.O

81

Ne
Ne

8.
29
2~

'8 '9 20 21 22 23 24

• Versatile Interrupt Handling

63

26 27 28

• True Bit Manipulation
• Addressing Modes With Indexed Addressing for
Tables

CDP6805E3 44 PLCC
TOP VIEW

• Efficient Instruction Set
• Memory Mapped I/O
• Two Power Saving Standby Modes

The CDP6805E2 and CDP6805E3 Microprocessors Unit
(MPUs) belong to the CDP6805 FamUy of CMOS Microcomputers. These 8-bit fully static and expandable
microprocessors contain a CPU, on-chip RAM, I/O and Timer.
They are low power, low cost processors designed for midrange applications In the consumer, automotive, industrial and
communications markets where very low power consumption
constitutes an important factor. The major features of
the CDP6805E2 and CDP6805E3 MPUs are listed under
"Hardware Features" and "Software Features".

Copyright

...
•••
...•••

6

5

..

© Harris Corporation 1991

.•••....,
'AO

Ne
Ne

)

2

1 44 43 42 4, 40
H

51

" -t . .a.

.u

12-- -

t!

-

---3,

.

14

••
••

3'S

Pl7

32

80

8'

17

11 "

20 21 22 23 2'4 IS 28 27 28

••

File Number

3-16

.a.pa'

... ..a..

AS

Description

8'a•

2746.1

CDP6805E~CDP6805E2~CDP6805E~CDP6805E3C

PAD

PA2

Port
A

A

PA3

Reg

110

PA4

Port

lines

Data
0"

Bos
Drlye

Condition
Code

PA5
5

6

PBO

PB2
PB3

PorI
B

Da,.

Reg

Reg

Bl
B2
B3

MultlpteKed

Address!

Data

B4

Register CC

Bus

B5

CPU

B6

Stack
POinter Sp

B7

rogram
Counter
High PCH
Program
Counter

PBl

110

M"

Register

PA7

Lines

CPU
Control

Index

Reg

PAB

Port
B

BO

Accumulator
A

PAl

ALU

AB

Address

A9

Address

AID

Bus

Drive

low pel

0"

All
A12

PB4
PB5
PBB
PB7

112x8

Bus

RAM

Control

Address Strobe
AS
OS
Data Strobe 1.21
R/W Read/Write

tn

a:::

CI

...
tn
tn

CI
'"
a:::

82CS~38015

a..

CI

Fig. 1a - CDP6805E2 block diagram.

a:::

c..>

:i

BO
PAO

Pon

Accumulator

PAl

A

PA2

110
lines

PA3

Port
A
Reg

CPU

A

Data
Oor
Reg

Bl

Mu,
Bus
Drive

B2
B3

Control

Index

B4

Register
Condition

Bus

B6

Code
Register CC

Data

B5

X

PA4

Multiplexed
Addressl

B7

CPU

Stack
6

lines

PB3

18
17
ALU

Program

PBl
PB2

19

rogram
Counler

HIgh PCH

PBO

Port
B
110

POinter SP

Port

Data

B
Reg

Dor
Reg

Address
Oflve

Counter
Low peL

16
15

AB
A9
Al0

Address
Bus

All
A12
A13
A14

PB4

A15

PB5
PB6

6

PB7

112xB
RAM

Bus
Control

4
5

AS

Address Strobe

DS

Data Strobe 1.21

R/W

Read/Wnte

92c:;·a71B5Rl

Fig. 1b - CDP6805E3 block diagram.

3-17

CDP6805E~CDP6805E2~CDP6805E~CDP6805E3C
MAXIMUM RATINGS (voltages referenced to VSS)
Ratings
Supply Voltage
All Input Voltages Except OSCl
Current Drain Per Pin Excluding VDD and VSS
Operating Temperature Range
CDP6805E2,CDP6805E3
CDP6805E2C,CDP6805E3C
Storage Temperature Range

Symbol

Value

Unit

VDD

-0.3 to +8.0

V

Yin

VSS-0.5 to VDD+0.5

V

I

10

mA

TA

TL to TH
to 70
-40 to 85

°c

Tstg

-55 to +150

°c

o

DC ELECTRICAL CHARACTERISTICS 3.0 V (VOO=3 Vdc, VSS=O, TA=TL to TH, unless otherwise noted)
Characteristics
Output Voltage ILOADS 10.0 p.A
Total Supply Current (CL =50 pF - no DC loads) tcyc=5

Symbol

Min

Max

Unit

VOL
VOH

-

V

VDD-O.l

0.1
-

IDD

-

IDD

-

IDD

p's

Run (VIL=0.2 V, VIH=VDD-0.2 VI
Wait IT est Conditions - See Note Belowl
Stop (Test Conditions - See Note Belowl

rnA
p.A

-

1.3
200
100

VOH

2.7

-

V

VOH
VOH

2.7

-

V

2.7

-

V

VOL

-

0.3

V

VOL

0.3

VOL

-

0.3

V
V

PAD·PA7, PBO-PB7, BO-B7
TIMER, IRO, RESET

VIH
VIH

2.1
2.5

-

OSCl

VIH
VIL

2.1
-

fOSC
fOSC

p.A

Output High Voltage
(I LOAD = 0.25 mAl A8-A15, Bo-B7
II LOAD = 0.1 mAl PAO-PA7, PBO-PB7
(/LOAD=0.25 rnA) DS, AS, R/W
Output Low Voltage
(I LOAD = 0.25 mAl A8-A15, BO-B7
(/LOAD-0.25 mAl PAD-PA7, PBO-PB7
(/LOAD=0.25 rnA) DS, AS, R/W
Input High Voltage

Input Low Voltage (All inputsl

-

V
V

-

V

0.5

V

0.032

1.0

MHz

DC

1.0

MHz

lin

-

±1

p.A

ITSL

-

±10

p.A

Cin

-

B.O

pF

Cout

-

12.0

pF

Frequency of Operation
Crystal
External Clock
Input Current
RESET, IRO, Timer, OSCl
Three-State Output Leakage
PAO-PA7,PBO-PB7,BO-B7
Capacitance
RESET, IRO, Timer
Capacitance
OS, AS, R/W, A8-A15, PAC-PA7, PBO-PB7, BO-B7

NOTE: Test conditions for Ouiescent Current Values are:
NOTE: References to PA5-7 pertain to CDP6805E2 and
Port A and B programmed as inputs.
references to A 13-15 pertain to COP6805E3.
VIL =0.2 V for PAO-PA7, PBO-PB7, and BO-B7.
VIH=VDD - 0.2 V for RESET, IRO, and Timer.
OSCl input is a squarewave from VSS+0.2 V to VDD - 0.2 V.
OSC2 output load (including tester! is 35 pF maximum.
Wait mode IDD is affected linearly by this capacitance.

3-18

CDP6805EZCDP6805E2~CDP6805E~CDP6805E3C
DC ELECTRICAL CHARACTERISTICS 5.0 V (VOO=5 Vdc

±

10%. VSs=O, TA=TL to TH, unless otherwise noted)

Characteristics

Symbol

Min

Max

Unit

VOL

-

VDH

VDD-O.l

0.1
-

V
V

IDD

-

10

mA

IOD

-

1.5

mA

IDD

-

200

J'...A

Output High Voltage
(I LOAD
1.6 mAl A8-A1S, BO-B7

VOH

4.1

-

V

Ii LOAD = 0.36 mAl PAO-PA7. PBO-PB7
Ii LOAD = 1.6 mAl DS. AS. R/W

VOH
VOH

4.1
4.1

-

V
V

= 1.6 mAl A8-A lS, BO-B7

VOl
VOL

0.4
0.4

VOL

-

V

(iLOAD= 1.6 mAl PAD-PA7, PBO-PB7

0.4

V

-

V
V

Output Voltage ILOADs 10.0 I"A
Total Supply Current (CL = 130 pF - On Bus. CL =50 pF - On Ports,
No DC Loads, tcyc = 1.0 I"S
Run (VIL = 0.2 V. VIH = VDD - 0.2 V)
Wait (Test Conditions - See Note Below)
Stop (Test Conditions - See Note Below)

=

-

Output Low Voltage
(ILOAD

(iLOAD = 1.6 mAl DS. AS, R/W
Input High Voltage

V

PAD-PA7. P80-PB7, 8O-B7

VII"

Vnn-2.0

TIMER, IRO, RESET

VIH

VDD-OB

OSCl

VIH

VDD-l.5

-

V

VIL

-

.0.8

V

i.os.c..

0.032

5.0

MHz

10SC

DC

5.0

MHz

lin

-

±1

I"A

ITSI

-

±1O

/All

Cin

-

8.0

pF

Cout

-

12.0

pF

Input Low Voltage (All Inputs!
Frequency 01 Operation
Crystal
External Clock
Input Currp.nt
RESET, IRO. Timer. OSCl
Three-State Output Leakage
PAO-PA7, P80-PB7. BO-B7
Capacitance
RESET. IRO, Timer
Capacitance
OS, AS, R/W, A8-A1S, PAQ-PA7, PBO-PB7, BO-B7
NOTE: Test conditions lor Ouiescent Current Values are:
Port A and B programmed as inputs.
VIL =0.2 V lor PAO-PA7, PBO-PB7, and BO-B7.
VIH = VDD - 0.2 V lor RESET, iRQ, and Timer.

OSCl input is a squarewave lrom VSS+O.2 V to VDD - 0.2 V.
OSC2 output load (including tester! is 35'pF maximum.
Wait mode liDD! is affected linearly by this capacitance.

NOTE: References to PAS-7 pertain to CDP680SE2 and
references to A13-1S pertain to CDP680SE3.

3-19

CDP6805E2, CDP6805E2C, CDP6805E3, CDP6805E3C
TABLE 1 - CONTROL TIMING (VSs=O, TA=TL toTH)

Symbol

VOO=3 V
fOSC=l MHz
Min
Typ
Max

I/O Port Timing - Input Setup Time I Figure 3)
Input Hold Time I Figure 3)

tpVASl

500

tASLPX

Output Delay Time I Figure 3)
Interrupt Setup Time IFigure 6)

Characteristics

VOO=5V ± 10%
fOSC=6 MHz
Min
Typ
Max

-

250

100

-

tASLPV

-

-

0

-

tlLASL

2

-

-

0.4

Crystal Oscillator Startup Time IFigure 5)

tOXOV

Wait Recovery Startup Time I Figure 7)

WASH

30
-

.Stop Recovery Startup Time ICrystal Oscillator) IFigure 8) tlLASH
Required Interrupt Release I Figure 6)
tOSLIH

-

300
10
300
5

Timer Pulse Width (Figure 7)

tTH, tTL

0.5

Reset Pulse Width (Figure 5)

tRL

5.2

Timer Period (Figure 7)

tTLTL

1.0

Interrupt Pulse Width Low (Figure 16)

tlLlH

1.0

Interrupt Pulse Period (Figure 16)

tlLlL

Oscillator Cycle Period (1/5 of t cyc )
OSCl Pulse Width High

tOLOL
tm

OSCl Pulse Width Low

tOL

30

-

-

-

15

100

-

2

15

100

ms

1.0

0.5

-

-

1 s
tcyc
,.s

-

-

100

..

-

-

1.0

-

1.0

-

..

200
75
75

-

ns
ns

0

ns

-

,.s

1.05

1000

350
350

-

Unit

-

ms
~s

~c
tcyc
t<:yc
ms
ns
ns

.. The minimum period tlLlL should not be less than the number of tcyc cycles it takes to execute the interrupt service routine plus 20 tcyc
cycles.

VOO=4.5 V

CMOS Equivalent

TTL Equivalent
R2
Test
Point

,

...

Test Point
1

C

~

Rl

1,
1

~
Pin
PAO-PA7, P80-P87
BO-B7, AS-A15,
R/W, OS AS

~

C

Rl
11.3 k

R2
2.1 k

50 pF

2.5 k

2 k

130 pF

1

r

C=50 pF, PAO-PA7, P80-P87
= 130 pF, A8-A12, BO-B7, OS, AS,
with VOO=5 V ± 10%

RIW

92cs-seo16

Fig. 2 - Equivalent test-load circuits.

3-20

CDP6805E~CDP6805E2~CDP6805E~CDP6805E3C
IVLOW=0.8 V, VHIGH=VOO-2 I V, VOO=5 ± 10%
Temp=Oo to 70°C, CL on Port=50 pF, fOSC=5 MHz)

Address
Strobe

Port
Input

-----<
1 4 - - - - t p V A S L - - - -. .-----tASLPX--~

Port
Output

92C8-38017

*The address strobe of the first cycle of the next instruction as shown in Table 11.

Fig. 3 - I/O port timing waveforms,

TABLE 2 - BUS TIMING (TA=TL 10TH, VSS=O V) See Figure 4

Num

1
2
3
4
8
9
11
16
17
18
19
21
23
24
25
26
27

28

Characteristics

Symbol

Cycle Time
Pulse Width, 0:; Low
Pulse Width, OS High or RO, WR, Low
Clock Transition
R/W Hold
Non-Muxed Address Hold
R/W Delay from OS Fall
Non-Muxed Address Delay from AS Rise
MPU Read Data Setu'p
Read Data Hold
MPU Data Delay, Write
Write Data Hold
Muxed Address Delay from AS Rise
Muxed Address Valid to AS Fall
Muxed Address Hold
Delay OS Fall to AS Rise
Pulse Width, AS Hiah
Delay, AS Fall to OS Rise

teye
PWEL
PWEH
t ,tf
tRWH
tAH
tAD
tAOH
tDSR
tDHR
to OW
tDHW
tBHD
tASL
tAl
tASD
PWASJi
tASED

3-21

fose=1 MHz,
VOO=3V
50 pF Load

fose=5 MHz
VOO=5 V ± 10%,
1 TTL
and 130 pF Load

Min
5000
2800
1800

Max

-

Min
1000
560
375

-

100

-

30

10
BOO

-

10
100

-

-

500

-

300

0
200
0

200
-

0
115

100

1000
0

0

-

160
120

-

55

-

250

0

-

55

120
-

750

60
160
175
160

800
0
600
250
800
850
800

DC

-

-

Unit

Max'DC

-

-

160.
-

-

ns
ns
ns
ns
ns
nS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

VHiGH*

III-- @ ----1\

AS

..,

VLOW

-I ~

~------------~l'

0~~
'26'---+
~

~

--~~------~~----- Q)------~

OS

~------~~----

~

CJI

.~

~

R/IN

®

®

$')

(,)

I

I\)
I\)

~~

AS-A15

B
Valid
Write

SO-S7
MPU Write

=tt®

---- ~~-,~~~
F

Valid

SO-S7
MPU Read

II

Addr

t

.....

.@.
Valid Read Data

~~~®
~ r+-@
~

II

-

92C8-38018R1

VH1GH = VOO -2 V. VLOW = 0.8 V for VOO = 5 V ± 10 %

Fig. 4 - BUB timing waveforms.

~

CJI

•~

B

~
'"----

• VHIGH= -2 V. VLOW = 0.5 V for VDO = 3 V

~

i
~
~

~
tJIIIIJl17771II111Ir!!J/IlTdIOlIJ//////ITUZ7777!!l1lll!/!:..L/:!/:/!:71=1=
______________
O"'---I--=='»=~_
~ mmzllJ/////JlZVVOZllJ7!I!!I7!!77!!m!llZlt
'00

_

RESET~+
I"
_

:920

lCYC~

g

AS _ _ _---'

"l:I

os _ _ _ _----'

0')

Unmux
A8-A15
Address Bus

Mux BO-B7
Address/Data
Bus

R/W

Co

..

\":....!.........

.. \"..

,,"<:iH' '-'"

(:)

"--F\...:...:.-,-'._. .:..'I'-":":"'''::''':''!''-J'--''--'-''!''-J'-_-'--'-...''_--'-_'

1\

f\

CJI

,~

. .L.J....'-LL.J.LLJ..j~~I..LI..J.LI!"-~.J.L~I'_~~_:::_::A--J'-:-*--';,.......I\.....-~I\....J\...--/\.......A--...A...JI~-~,_/'~~iJI
.i.

FE (FE)

FE (FE)

New PCH

New PCl

l/iffl/llfl

~

'CJ

\

0')

~
CJI

Oscillator Waveform

Co:>

Crystal Oscillator Connec\JOns

~

Crystal Parameters Representative Frequencies

$')

I

'"

Co:>

~,o,t=:}OSCI Pin

~

tOlOl

CDP6805E2

10 Mil
38~39
OSC2

L--.lnW OSCI

ICOSC2

I

RS max
CO
C1
Q

COSCI
COSC2

5 MHz
501l
8 pF
0.02 pF
50k
15-30 pF
15-25 pF

4 MHz
751l
7 pF
0.012 pF
40 k
15-30 pF
15-25 pF

1 MHz
4001l
5 pF
0.008 pF
30 k
15-40 pF
15-30 pF

g
"l:I

0')

Co

(:)

CJI

~

COSCI

~

Crystal CirCUit

38~~39

0')

Co

(:)

0~~1
0~C2

101

CJI

~

(')

0~9C1
92CS-38019

Fig. 5 - Power-on reset and reset timing waveforms.

rMICROPROCESSORS II

f----n

AS

-.n

--t-- n + l--t--- n+2--t-- n +3 --+-n + 4--1---n + 5-+--n +6---+-n + 7 -+-n + 8-+- n+9--1

n

I

OS

n

n

n

n

n

n

~

n

~

r

g

'"

0)

00

Mux BO-B7
Address/Data
Bus

Riw

~I ___ ~

._.

r'_--,_

f"\_

llU

\

A_

<::)

~_"_

/

01

"'4

'92CS-38020

*tDSLIH -

,~

g

'~"

The Interrupting device must release the IRQ line within this time to prevent subsequent recognition of the same Interrupt

0)

~

Fig. 6 - IRQ and TCR7 interrupt timing waveforms.

n

Ul

I
I\)

g

-1>0

'"

Timer

~

ICOUnler~$OOf.-1TL TL--I

I---!-tTl

'"'"'""Clock
"",m.

<::)

01

~

I----i-tTH
TCRb7

AS~

n

n

~

•

t---1IVASH----t::I-- n

n

--+-= n + l-+--n + 2-+-=-n + 3-+--n + 4-+-::-n+ o-+--n+ 6-+-=:n + 7--1

n

n

n

n

n

n

n

~

Unmux
AB-A15
Address Bus

00
<::)
.. ,--,

R/W

ffi

.. '" "'

~Addf+i;..--------.~S~P;-----;::S-;::P---;1---;::S-;::P--;2;---~~C;~:;-::;-~--c--;:;---;.---<--;_c:_:-~-'---J
""

BFlI/ffllOlTffi.

MuxBO-B7
Address/Data
Bus

~

0)

OS

. 0

71!7717l1Tm

Walt

C d

poe

New PCrl

'"

" \

OIJ.tm8

/
92CS-36021

Fig. 7 - Timer interrupt after WAIT instruction timing waveforms.

(")

New PCl 1st Op Code Rlnt

OSC2'

Wfl/7/Wllfffffl/J1 ~

IRQ

'-=cnTT77Z0llTllfl!/i7/t;yZdlTlIIII!fllIPlllflIITIIIJl/ffllflfl7/l!fl/Il!J'J'IIIIIJIIJ//JIIIi/d/ll III
t_tll_.A_SH_~
____
19_20_tc~yt_*__~~r-____________________________________________

\

g
"tJ

0)

0:)

o

AS

CJ'J

~

OS

Unmux

Int Routine
Starting Addr

Op Code Address

Ad~~;~1~us ~
Mux BO-B7
Address! Data
Bus

c.:>
I

R/W

BE
Stop Op Code

§I

\\

I

~

"tJ

0)

gg
CJ'J

)0\'\\\\\\

~

g
~

•

,I.....________~_______~

I\)

CJ1

1st Op Code
I nt Routine
92C5-38022

fJ

g
"tJ

0)

0:)

o

. : Represents the internal gating of the OSC1 input pin.
tcye is one instruction cycle Ifor fOSC = 5 MHz, teye = 1 I's)

CJ'J

~

g
"tJ

~

o
Fig. 8 - Interrupt recovery from STOP instruction timing waveforms.

r-;I~~PROCESSORS

a

ffi

C")

CDP6805EZCDP6805E2~CDP6805E~CDP6805E3C

Functional Pin Description
VDD and VSS - VDD and VSS provide power to the chip.
VDD provides power and Vss is ground.
IRQ (Maskable Interrupt Request) - IRQ is a level
sensitive and edge sensitive input which can be used to
request an interrupt sequence. The MPU completes the
current instruction before it responds to the request. If IRQ
is low and the interrupt mask bit (I-bit) in the Condition
Code Register is clear, the MPU begins an interrupt
sequence at the end of the current instruction. The interrupt
circuit recognizes both a "Wire ORed" level as well as
pulses on the IRQ line (see Interrupt Section for more
details). IRQ requires an external resistor to VDD for "Wire
OR" operation.
RESET - The RESET input is not required for start up but
can be used to reset the MPU's internal state and provide an
orderly software start up procedure. Refer to the RESET
section for a detailed description.
TIMER - The TIMER input is used for clocking the on chip
timer. Refer to TIMER section for a detailed description.
AS (Address Strobe) - Address Strobe (AS) is an output
strobe used to indicate the presence of an address on the
8-bit multiplexed bus. The AS line is used to demultiplex the
eight least significant address bits from the data bus. A
latch controlled by Address Strobe should capture
addresses on the negative edge. This output is capable of
driving one standard TTL load and 130pF and is available at
fOSC -;- 5 when the MPU is not in the WAIT or STOP states.
OS (Data Strobe) - This output is used to transfer data to
or from a peripheral or memory. DS occurs anytime the
MPU does a data read or write. DS also occurs when the
MPU does a data transfer to or from the MPU's internal
memory. Refer to Table 2 and Figure 4 for timing characteristics. This output is capable of driving one standard TTL

load and 130pF. DS is a continuous signal at fOSC -;- 5
when the MPU is not in WAIT or STOP state. Some bus
cycles are redundant reads of op code bytes.
R/W (ReadlWrite) - The RtW output is used to indicate the
direction of data transfer for both internal memory and I/O
registers, and external peripheral devices and memories.
This output is used to indicate to a selected peripheral
whether the MPU is going to read or write data on the next
Data Strobe (R/W low = processor write; RiW high = processor read). The RtW output is capable of driving one
standard TTL load and 130pF. The normal standby state is
Read (high).
A8-A15 (High Order Address Lines) - The A8-A15
output lines constitute the higher order non-multiplexed
addresses. Each output line is capable of driving one
standard TTL load and 130pF.
BO-B7 (Address/Data Bus) - The 80-87 bidirectional
lines constitute the lower order addresses and data. These
lines are multiplexed, with address present at Address
Strobe time and data present at Data Strobe time. When in
the data mode, these lines are bidirectional, transferring
data to and from memory and peripheral devices as
indicated by the R/W pin. As outputs in either the data or
address modes, these lines are capable of driving one
standard TTL load and 130pF.
OSC1. OSC2 - The CDP6805E2/3 provides for two types
of oscillator inputs - crystal circuit or external clock. The
two oscillator pins are used to interface to a crystal circuit,
as shown in Figure 5. If an external clock is used, it must be
conected to OSC1. The input at these pins is divided by five
to form the cycle rate seen on the AS and DS pins. The
frequency range is specified by fOSC. The OSC1 to bus
transitions relationships are provided in Figure 9 for system
designs using oscillators slower than 5 MHz.

ascI
AS

DS

R/W

60-67
MPU Read - - - - - f
60-67
MPU Write

Mux. Addr

----ir-------nf----------------i1r-Mux. Addr

MPU Write Data

• Read data "latched" on DS fall.
92CS-38023R I
Fig. 9 - OSC1 to bus transitions timing waveforms

3-26

CDP6805E~CDP6805E2~ CDP6805E~CDP6805E3C

Crystal - The circuit shown in Figure 5 is recommended when using a crystal. The internal oscillator IS
designed to interface with an AT -cut parallel resonant
quartz crystal resonator in the frequency range
specified for fOSC in the electrical characteristics
table. An external CMOS oscillator is recommended
when crystals outside the specified ranges are to be
used. The crystal and components should be mounted
as close as possible to the input pins to minimize output distortion and start-up stabilization time.

LI (Load Instruction) - This output is used to indicate that
a fetch of the next opcode is in progress. LI remains low dur
ing an External or Timer interrupt. The LI output is only used
for certain debugging and test systems. For normal operations this pin is not connected. The LI output is capable of
driving one standard TTL load and 50 pF. This signal
overlaps Data Strobe.

PAO-PA7 - These eight pins constitute Input/Output
Port A. Each line is individually programmed to be either an
input or output under software control via its Data Direction
Register as shown below. An I/O pin is programmed as an
output when the corresponding DDR bit is set to a "1," and
as an input when it is set to a "0". In the output mode the
bits are latched and appear on the corresponding output
pins. An MPU read of the port bits programmed as outputs
reflect the last value written to that location. When programmed as an input, the input data bit Is) are not latched. An
MPU read of the port bits programmed as inputs reflects the
current status of the corresponding input pins. The
Read/Write port timing is shown in Figure 3. See lYpicall/O
Port Circuitry in Figure 11. During a Power-On Reset or external RESET all lines are configured as inputs Izero in Data
Direction Registerl. The output port register is not initialized
by reset. The TTL compatible three-state output blJffers are
capable of driving one standard TTL load and 50 pF. The
DDR is a read/write register.

External Clock - An external clock should be applied to the OSCl input with the OSC2 input not connected, as shown in Figure 10.

OSCI 39

05C2 38

No
Connection

CDP6805E2

INC}

PBO-PB7 - These eight pins interface to Input/Output
Port B. Refer to PAO-PA7 description for details of operation.
Fig. 10 - External clock connection.

Oata Direction
Register

$0004

Port A
Register

$0000

Pin

PA7

PA6

PA5

PA4

PA3

PAl

PAl

PAO

Data Direction
Register

$0005

Port B
Register

$0001

Pin

PB7

PB6

PB5

PB4

PB3

PB2

PB 1

PBO
92C5-38025

3-27

CDP6805E2, CDP6805E2C, CDP6805E3, CDP6805E3C

To
And

From

CPU

Fig. 11 - Typical I/O port circuitry

subroutine calls. At power up, the stack pointer is set to $7F
and it is decremented as data is pushed onto the stack.
When data is removed-from the stack, the stack pointer is
incremented. A maximum of 64- bytes of RAM is available
for stack usage. Since most programs use only a small part
of the allotted stack locations for interrupts and/or
subroutine stacking purposes, the unused bytes are usable
for program data storage.

TABLE 3 I/O PIN FUNCTIONS
RIW

DDR

1/0 PIN FUNCTIONS

0

0

The I/O pin is in input mode. Data is written
Into the output data latch.

0

1

Data is writeen into the output data latch
and output to the I/O pin.

1

0

The state of the I/O pin is read

1

1

The I/O pin is in an output mode. The output
data latch is read.

Functional Description
Throughout the following sections references to
CDP6B05E2 I imply both the CDP6805E2 and the
CDP6805E3. VallJes in parenthesis refer to the
CDP6805E3.

Memory Addressing
The CDP6805E2 is capable of addressing 8192 (65,536)
bytes of memory and I/O registers. The address space is
divided Into internal memory space and external memory
space, as shown in Figure 12.
The internal memory space is located within the first 128
bytes of memory (first half of_page zero) and Is comprised
of the I/O port locations, timer locations, and 112 bytes of
RAM. The MPU can read from or write to any of these
locations. A program write to on chip locations is repeated
on the external bus to permit off chip memory to duplicate
the content of on chip memory. Program reads to on chip
loacations also appear on the external bus, but the MPU
accepts data only from the addressed on chip location. Any
readdata,'appearing on the input bus is ignored.
The stack pointer is used to address data stored on the
.stack. Data is stored on the stack during interrupts and

All memory locations above location $OO7F are part of the
external memory map. In addition, ten locations in the I/O
portion of the lower 128 bytes of memory space, as shown
in Figure 12, are part of the external memory map. All of the
external memory space is user definable except the highest
10 locations. Locations $1 FF6 to $1 FFF ($FFF6 to $FFFF)
of the external address space are reserved for interrupt and
reset vectors (see Figure 12).

Registers
The CDP6805E2 contains five registers as shown in the
programming model in Figure 13. The interrupt stacking
order is shown in Figure 14.
Accumulator (A) - This Accumulator is an 8-bit general
purpose register used for arithmetic calculations and data
man ipulations.
Index Register (X) - The X register Is an 8-blt register
which Is used during the indexed modes of addressing.
It provides an 8-bit operand which is used to create an
effective address. The index register is also used for
data manipulations with the Read/Modify/Write type of
instructions and as a temporary storage register when not
performing addressing operations.
Program Counter (PC) - The program counter is a 13-bit
(16-bit) register that contains the address of the next
instruction to be executed by the processor.

3-28

CDP6805E~CDP6805E~CDP6805E2~CDP6805E3C
soooo

1,0 Ports
Timer

V,a {
"co'

Page 0

RAM

127
128

S007F

-- --------

255
256

Port A Data Register

soooo

1

Port B Data Register

S0001

2

External Memorv Space

S0002

3

External Memory Space

S0003

SooFF

4

Port A Data Direction Register

SIJOO4

SOloo

5

Port B Data Direction Register

S0005

External Memory Space

S0006

External Memory Space

S0007

SOO8O

Direct
Addressing

0

\

7

External
Memory

8

Timer Data Register

SOOO8

9

T,mer Control Register

S0009

Ie

Space

$ oooA

18064 Bytes)

External Memory

Space
SoooF

5
6

S0010

RAM
1112 Bytes}

63

S003F

/ 7 SOO4O

64
/

f----------

f-

~Im_~ l_~er~! ~o:.W.!t ~at:.3n~

Interrupt

{

- ---Timer Interrupt

8191

-

-

-

-

-

SIFF6-S1FF7

/

\

./

/

SIFF8-S1FF9
I

External Interrupt

~ -

Vectors

/'

/

/
. / ' " Stack (64 BVles Max)

SIFFA-S1FFB

-

I

,

SWI

SIFF(.SIFFD

RESET

SI FFE-Sl FFF
12

f--------

/

7V

t

./

S007F

Fig. 12a - CDP6805E2 address map.

{

~..
V,a
Page 0
Direct

soooo

1/0 Ports
Timer

soooo
S0001

2

External Memory Space

S0002

3

External Memory Space

S0003

SooFF

4

1 1 1[ Port A ODA

SIJOO4

00

5

Port B Data Direction Register

S0005

6

External Memory Space

S0006

7

External Memory Space

S0007

S007F
SOO8O

\

AddreSSing

255
256

LPort A Data Register

Port B Data Register

1

RAM

127
128

a0a

0

f--

--------

SOl

External
Memory

8

Timer Data Register

S0008

9

Timer ContrOl Register

S0009
$ oooA

C

Space
(65408 Bytes)

External Memory
Space

5

SoooF

6

S0010

RAM
(112 Bytesl

3

S003F

/ 7 SOO4O

64

---------.!I~ I~er~t .::o~
~at~On~
W,!'

Inlerrupt

Timer Interrupt

{

Vectors

-

-

-

E,,;;;;;ailnl;ru~ -

~

-

-

-

.....

65535

-

SWI

_. -

------RESET

/
/'

/

$FFF6-$FFF7

/

\

/

$FFF8·$FFF9

-

$FFFA·$FFFB
I

$FFFC.$FFF,D
$FFFE.$FFFi2

/

7~./

Fig. 12b - CDP6805E3 address map.

3-29

./

/
"',,',,, Stack 164 Bytes Max)

I

t

S()()7F

CDP6805EZCDP6805E~CDP6805E2~CDP6805E3C

o
A __--.l1 Accumulator
I......__....;~
7
o
I......_ _...:.:X___.....1Index Register
15* _
12
o
PC ____--II Program Counter
I _____~=I_- ~
7

15*

12

6

0

IQ1 Q.l0 I 0 I 0 I 0 I 0 I 0 I 0 11 I

SP

·CDP6805E3

CC
' N Z C

I Stack Pointer

~

Condition Code Register
Carry/Borrow
Zero
Negative
Interrupt Mask
Half Carry

Fig. 13 - Programming model.

Stack

1 11 11 1Condition Code Register

i

Increasing Iv1emoryj
~
Addresses

N

Accumulator
Index Register

010101

PCH
PCl

I

i1
R

Decreasing Iv1emory
Addresser

u
P
T

Unstack

NOTE: Since Ihe Stack Pointer decrements during pushes, the PCl is stacked
first, followed by PCH, etc. Pulling from the stack is in the reverse order.

Fig. 14 - Stacking order.

STACK POINTER (SP) - The stack pointer is a l3-bit
(16-bit) register containing the address of the next free
location on the stack. When accessing memory, the seven
most significant bits are permanently set to 0000001
(0000000001). They are appended to the six least-significant register bits to produce an address within the range of
$007F to $0040. The stack area of RAM is used to store the
return address on subroutine calls and the machine state
during interrupts. During external or power-on reset, and
during a "reset stack pointer" instruction, the stack pointer
is set to its upper limit ($007F). Nested interrupts and/or
subroutines may use up to 64 (deCimal) locations, beyond
which the stack pointer "wraps around" and points to its
upper limit thereby losing the previously stored information.
A subroutine call occupies. two RAM bytes on the stack,
while an interrupt uses five bytes.

bits can be individually tested by a program and specific
action taken as a result of their state. Each of the five bits is
explained below.
Half Carry Bit (H) - The H-bit is setto a one when a carry
occurs between bits 3 and 4 of the ALU during an ADD or
ADC instruction. The H-bit is useful in Binary Coded
Decimal addition subroutines.
Interrupt Mask Bit (I) - When the I-bit is set, both the
external interrupt and the timer interrupt are disabled.
Clearing this bit enables the above interrupts. If an interrupt
occurs while the I-bit is set, the interrupt is latched and will
be processed when the I-bit is next cleared.
Negative Bit (N) - When set, this bit indicates that the
result of the last arithmetic, logical, or data manipulation
was negative (bit 7 in the result is a logical one).

CONDITION CODE REGISTER (CC) - The condition.
Zero Bit (Z) - When set, this bit indicates that the result
code register is a 5-bit register in which each bit is used to
indicate the results of the instruction just executed. These of the last arithmetic, logical, or data manipulation was zero.

3-30

CDP6805E~CDP6805E2~CDP6805E~CDP6805E3C
Carry Bit (C) - The C-bit is set when a carry or a borrow out
of the ALU occurs during an arithmetic instruction. The
C-bit is also modified during bit test, shift, rotate, and
branch types of instruction.

Resets
The CDP6805E2 has two reset modes: an active low
external reset pin (RESET) and a Power On Reset function;
refer to Figure 5.
RESET (Pin #1) - The RESET input pin is used to reset the
MPU and provide an orderly software start up procedure.
When using the external reset mode, the RESET pin must
stay low for a minimum of one !eyc. The RESET pin is
provided with a Schmitt Trigger to improve its noise
immunity capability.
Power On Reset - The Power On Reset occurs when a
positive transition is detected on VDD. The Power On Reset
is used strictly for power turn on conditions and should not
be used to detect any drops in the power supply voltage.
There is no provision for a power down reset. The power on
circuitry provides for a 1920 tcyc delay from the time of the
first oscillator operation. If the external reset pin is low at the
end of the 1920 tcyc time out, the processor remains in the
reset condition.
Either of the two types of reset conditions causes the
following to occur:
• Timer control register interrupt request bit (bit 7) is
cleared to a "0" .
• Timer control register interrupt mask bit (bit 6) is set to
a "1".
• All data direction register bits are cleared to a "0" (inputs).
• Stack pointer is set to $007F
• The address bus is forced to the reset vector ($1 FFE,
$1 FFF ($FFFE, $FFFF)
• Condition code register interrupt mask bit (I) is set to a "1"
• STOP and WAIT latches are reset.
• External interrupt latch is reset.
All other functions, such as other registers (including output
ports) the timer, etc., are not cleared by the reset conditions.

Interrupts
The CDP6805E2 is capable of operation with three different
interrupts, two hardware (timer interrupt and external interrupt) and one software (SWI). When any of these interrupts
occur, normal processing is suspended at the end of the
current instruction execution. All of the program registers
(the machine state) are pushed onto the stack; refer to
Figure 14 for stacking order. The appropriate vector pointing to the starting address of the interrupt service routine is
then fetched; refer to Figure 15 for the interrupt sequence.
The priority of the various interrupts from highest to lowest
is as follows:
RESET -+

* -+ External Interrupt -+ Timer Interrupt

from $01 to $00) an interrupt request is generated. The
actual processor interrupt is generated only if the interrupt
mask bit of the codition code register is also cleared. When
the interrupt is recognized, the current state of the machine
is pushed onto the stack and the I-bit in the condition code
register is set. This masks further interrupts until the present
one is serviced. The processor now vectors to the timer
interrupts service routine. The address for this service
routine is specified by the contents of $1 FF8 and $1 FF9
($FFF8 and $FFF9). The contents of $1 FF6 and $1 FF7
($FFF6 and $FFF7) specify the service routine. Also, software must be used to clear the timer interrupt request bit
(TCR7). At the end of the time interrupt service routine, the
software normally executes an RTI instruction which
restores the machine state and starts executing the
interrupted program.
External Interrupt - If the interrupt mask bit of the condition code register is cleared and the external interrupt pin
IRQ is "low", then the external interrupt occurs. The action
of the external interrupt is identical to the timer interrupt with
the exception that the service routine addres is specified by
the contents of $1 FFA and $1 FFB ($FFFA and $FFFB). The
interrupt logic recognizes both a "wire ORed" level and
pulses on the external interrupt line. Figure 16 shows both a
functional diagram and timing for the interrupt line. The timing diagram shows two different treatments of the interrupt
line (IRQ) to the processor. The first configuration shows
many interrupt lines "wire ORed" to form the interrupts at
the processor. Thus, if after servicing an interrupt the IRQ
remains low, then the next interrupt is recognized. The
second method is single pulses on the interrupt line spaced
far enough apart to be serviced. The minimum time between
pulses is a function of the length of the interrupt service
routir.e. Once a pulse occurs, the next pulse should not
occur until the MPU software has exited the routine (an RTI
occurs). This time (tILlL) is obtained by adding 20 instruction cycles (one cycle tcyC = 5/fOSC) to the total number of
cycles it takes to complete the service routine including the
RTI instruction; refer to Figure 6.
Software Interrupt (SWI) - The software interrupt is an
executable instruction. The action of the SWI instruction is
similar to the hardware interrupts. The SWI is executed
regardless of the state of the interrupt mask in the condition
code register. The service routine address is specified by
the contents of memory locations $1 FFC and $1 FFD
($FFFC and $FFFD). See Figure 15 for interrupt and
instruction Processing Flowchart.
The following three functions are not strictly interrupts;
however, they are tied very closely to the interrupts. These
functions are RESET, STOP, WAIT.
RESET - The RESET input pin and the internal Power On
Reset function each cause the program to vector to an
initialization program. This vector is specified by the
contents of memory locations $1 FFE and $1 FFF ($FFFE
and $FFFF). The interrupt mask of the condition code
register is also set. Refer to RESET section for details.

Timer Interrupt - If the timer mask bit (TCR6) is cleared,
then each time the timer decrements to zero (transitions
*Any current instruction including SWI

3-31

CDP6805EZCDP6805E2~CDP6805E~CDP6805E3C

Force Interrupt
Execution, Set
Interrupt Mask,
Fetch Ext Int
Vector, Reset
Interrupt Latch

Force Interrupt
Execution, Set
Interrupt Mask,
Fetch Timer
Vector * Note

* NOTE:

The clear of TeR bit 7 must be accomplished with software.

Fig, 15 - Interrupt and instruction processing flowchart.

3-32

92CS-38030

CDP6805E~CDP6805E2~CDP6805E~CDP6805E3C

lal Interrupt Functional Diagram

VDD
D

Interrupt Pin

External
Interrupt
Request

Q.~---~

>--_~-~ClC

Q

I Bit ICCRI

Power·On Reset
External Reset
External Interrupt
Being Serviced

Ibl Interrupt Mode Diagram

111

Wire OR'ed Condition

I~Ol~L______________~

Ilf after servicing an interrupt the IRQ reo
mains low, then the next interrupt is re~
cognized I

•
•

IROn

IRQIMPUI~L______________________________~

121

IRQ~tILIH

~

Pulse Condition

U

The minimum pulse width ItlLiHI is one
tcyc· The period liUL should not be less
than the number of tcyc cycles it takes to
execute the interrupt service routine plus
20 tcyc cycles.

l)LlL~~

92CS-38031

Fig. 16 - External interrupt.

3-33

CDP6805EZCDP6805E2~CDP6805E~CDP6805E3C
STOP - The STOP instruction places the CDP6805E2 in a
low power consumption mode. In the STOP function the
internal oscillator is turned off, causing all internal processing and the timer to be halted; refer to Figure 17. The DS
and AS Ilnes go to a low state and the RiW line goes to a
high state. The multiplexed address/data bus goes to the
data input state. The high order address lines remain at the
address of the next instruction. The MPU remains in the
STOP mode until an external interrupt or reset occurs; refer
to Figure 8 and 17.

Stop Oscillator
And All Clocks
TCR Bit 7-0
Bit 6-1
Clear I Mask

except the Timer, which is allowed to count in a normal
sequence. The R/W line goes to a high state, the multiplexed address/data bus goes to the data input state, and
the DS and AS lines go to the low state. The high order
address lines remain at the address of the next instruction.
The ~PU remains in this state until an external interrupt,
timer interrupt, or a reset occurs; refer to Figures 7 and 18.
During the WAIT mode, the I-bit In the condition code
register is cleared to enable Interrupts. All other registers,
memory, and I/O lines remain in their last state. The timer
may be enabled to allow a periodic exit from the WAIT
mode. If an external and a timer interrupt occur at the same
time, the external interrupt is serviced first; then, if the timer
Interrupt request is not cleared in the external interrupt
routine, the normal timer interrupt (not the timer WAIT
interrupt) is serviced since the MCU is no longer in the WAIT
mode.

Timer
The MPU timer contains a single 8-bit software programmable counter with 7 -bit software selectable prescaler. The
counter may be preset under program control and decrements towards zero. When the counter decrements to zero,
the timer interrupt request bit, i.e., bit 7 of the Timer Control
Register (TCR) Is set. Then If the timer interrupt is not
masked, i.e., bit 6 of the TCR and the I-bit in the Condition
Code Register are both cleared, the processor receives an
Interrupt. After completion of the current instruction, the
processor proceeds to the store the appropriate registers
on the stack, and then fetches the timer vector address from
locations $1 FF8 and $1 FF9 ($FFF8 and $FFF9) in order to
begin servicing the interrupt, unless it was in locations
$1 FF6 and $1 FF7 ($FFF6 and $FFF7) the WAIT mode.

Yes

The counter continues to count after it reaches zero,
allowing the software to determine the number of internal or
external input clocks since the timer interrupt request bit
was set. The counter may be read at any time by the
processor without distrubing the count. The contents of the
counter becomes stable prior to the read portion of a cycle
and does not change during the read. The timer interrupt
request bit remains set until cleared by the software. If this
happens before the timer interrupt is serviced, the interrupt
is lost. TCR7 may also be used as a scanned status bit In a
non-interrupt mode of operation (TCR = 1).

Fig. 17 - Stop function flowchart

During the STOP mode, timer control register (TCR) bits 6
and 7 are altered to remove any pending timer interrupt
requests and to disable any further timer Interrupts. External
interrupts are enabled in the condition code register. All
other registers and memory remain unaltered. All I/O lines
remain unchanged.
WAIT - The WAIT instruction places the CDP6805E2 in
a low power consumption mode, but the WAIT mode
consumes somewhat more power than the STOP mode;
refer to Table 1. In the WAIT function, the internal clock Is
disabled from all internal circuitry except the Timer circuit,
refer to Figure 18. Thus, all internal processing is halted

The prescaler is a 7-bit divider which is used to extend the
maximum length of the timer. Bit 0, bit 1, and bit 2 of the
TCR are programmed to choose the appropriate prescaler
output which is used as the counter input. The processor
cannot write into or read from the prescaler; however, its
contents are cleared to all "O's" by the write operation into
TCR when bit 3 of the written data equals 1, which allows
for truncation free counting.
The Timer input can be configured for three different
operating modes, plus a disable mode depending on the
value written to the TCR4, TCR5 control bits. Refer to the
Timer Control Register section.
Timer Input Mode 1 - If TCR4 and TCR5 are both
programmed to a "0", the input to the Timer is from an Internal clock and the Timer input is disabled. The internal clock
mode can be used for periodic interrupt generation, as well

3-34

CDP6805EZCDP6805E2~CDP6805E~CDP6805E3C

Wait

Oscillator Active
Clear I-Bit
Timer Clock Active
All Other Clocks
Stop

No

No

Fetch External Interrupt
Reset, or Timer Interrupt
(from WAIT Mode only)

92C8-38033

Fig, 18 - Wait function flowchart.

as a reference in frequency and event measurement. The internal clock is the instruction cycle clock and is coincident
with Address Strobe (ASI except during a WAIT instruction.
During a WAIT instruction the AS pin goes to a low state but
the internal clock to the Timer continues to run at its normal
rate.
Timer Input Mode 2 - With TCR4= 1 and TCR5=O, the
internal clock and the TIMER input pin are ANDed together
to form the Timer input Signal. This mode can be used to
measure external pulse widths. The external pulse simply
turns on the internal clock for the duration of the pulse. The
resolution of the count in this mode is ± 1 clock and
therefore accuracy improves with longer input pulse widths.

Timer Input Mode 3 - If TCR4=O and TCR5= 1, then all
inputs to the Timer are disabled.
Timer Input Mode 4 - If TCR4= 1 and TCR5= 1, the internal clock input to the Timer is disabled and the TIMER input pin becomes the input to the Timer. The external Timer
pin can, in this mode, be used to count external events
as well as external frequencies for generating periodic interrupts.
Figure 19 shows a block diagram of the Timer subsystem.
Power-on Reset and the STOP instruction cause the counter
to be set to $FO.

3-35

CDP6805E2, CDP6805E2C, CDP6805E3, CDP6805E3C

Timer
(Pin 37)

Write

Read

Interrupt

Internal
Clock

~~--------------------------~--------------------~/
Software Functions
NOTES:
1. Prescaler and 8-blt counter are clocked falling edge of the internal clock (AS) or external

input.
2. Counter is written to during Data Strobe (OS) and counts down continuously. ,
92CM- 38034R1

Fig. 19 - Timer block diagram.

Timer Control Register (TCR)
765432'

TCR5 TCR4

o

~

0

ITCR7ITCR6ITCR5ITCR4ITCR3ITCR2ITCR,ITCROI
All bits in this register excep't bit 3 are Read/Write bits.
TCR7 - Timer interrupt request bit: bit used to indicate
the timer interrupt when it is logic """'.
, - Set whenever the counter decrements to zero, or under prograrn control.
o - Cleared on external reset, power-on reset. STOP instruction, or program control.

o

,

,
,

0
,

Internal clock (AS) to Timer
AND of internal clock (AS) and TIMER
pin to Timer
Inputs to Timer disabled
TIMER pin to Timer

Refer to Figure '9 for Logic Representation.

TCR3 - Timer Prescaler Reset bit: writing a """' to this bit
resets the prescaler to zero. A read of this location always indicates a "'0."' (Unaffected by RESET.I

TCR6 - Timer interrupt mask brt: when this bit rs a logic
"""' it inhibits the timer interrupt to the processor.
, - Set on external reset, power-on reset, STOP rnstruction, or program control.
o - Cleared under program control.

TCR2, TCR1, TCRO - Prescaler address bits: decoded to
select one of eight taps on the prescaler. (Unaffected by
RESET.I
Prescaler
TCR2
TCR1
TCRO
Result
0
0
0
+1
0
0
+2
0
1
0
+4
0
1
1
+8
0
0
+16
0
1
+32
1
0
+64
-+- 128

TCR5 - External or internal bit: selects the input clock
source to be either the external timer pin or the internal
clock. (Unaffected by RESET.I
, - Select external clock source.
Select internal clock source (ASI.

,

o-

,,,
,

TCR4- External enable bit: control bit used to enable the
external timer pin. (Unaffected by RESET.I
, - Enable external timer pin.
o - Disable external timer pin.

3-36

,

,

CDP6805E~CDP6805E2~CDP6805E~CDP6805E3C

INSTRUCTION SET
The MPU has a set of 61 basic instructions. They can be
divided into five different types: register/memory,
read/modify/write, branch, bit manipulation, and control.
The following paragraphs briefly explain each type. All the
instructions within a given type are presented in individual
tables.
REGISTER/MEMORY INSTRUCTIONS - Most of these
instructions use two operands. One operand is either the accumulator or the index register. The other operand is obtained from memory using one of the addressing modes. The
jump unconditional (JMP) and jump to subroutine IJSR) instructions have no register operand. Refer to Table 4.
READ/MODIFY/WRITE INSTRUCTIONS - These instructions read a memory location or a register, modify or
test its contents, and write the modified value back to
memory or to the register. The test for negative or zero
ITST) instruction is an exception to the, read/modify/write
sequence since it does not modify the value. Refer to
Table 5.
BRANCH INSTRUCTIONS - This set of instructions
branches if a particular condition is met, otherwise no operation is performed. Branch instructions are two byte instructions. Refer to Table 6.

direct addressing instructions access all data bytes in most
applications. Extended addressing permits jump instructions
to reach all memory. Table 9 shows the addressing modes
for each instruction, with the effects each instruction has on
the Condition Code Register. An opcode map is shown in
Table 10.
The term" Effective Address" or EA is used in describing
the various addressing modes, which is defined as the address to or from which the argument for an instruction is fetched or stored. The ten addressing modes of the processor
are described below. Parentheses are used to indicate "contents of ," an arrow indicates "is replaced by" and a colon indicates concatenation of two bytes.

Inherent - In inherent instructions all the information
necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, and no other arguments, are included in this
mode.
Immediate - In immediate addressing, the operand is
contained in the byte immediately following the opcode. Immediate addressing is used to access constants which do not
change during program execution le.g., a constant used to
initialize a loop counter).
EA= PC+ 1; PC-PC+2

BIT MANIPULATION INSTRUCTIONS - The MPU is
capable of setting or clearing any bit which resides in the first
256 bytes of the memory space, where all port registers, port
DDRs, timer, timer control, and on-chip RAM reside. An additional feature allows the software to test and branch on the
state of any bit within these 256 locations. The bit set, bit
clear and bit test and branch functions are all implemented
with a single instruction. For the test and branch instructions
the value of the bit tested is also placed in the carry bit of the
Condition Code Register. Refer to Table 7 for ;nstruction cycle timing.

Direct - In the direct addressing mode, the effective address of the argument is contained in a single byte following
the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two
byte instruction. This includes all on-chip RAM and I/O
registers and up to 128 bytes of off-chip ROM. Direct addreSSing is efficient in both memory and speed.
EA= IPC+ 1); PC-PC +2
Address Bus High-O; Address Bus Low-IPC+ 1)

CONTROL INSTRUCTIONS - These instructions are
register reference instructions and are used to control processor operation during program execution. Refer to Table 8
for instruction cycle timing.
ALPHABETICAL LISTING - The complete instruction set
is given in alphabetical order in Table 9.

Extended - In the extended addressing mode, the effective address of the argument is contained in the two bytes
following the opcode. Instructions with extended addressing
modes are capable of referencing arguments anywhere in
memory with a single three byte instruction.

OPCODE MAP SUMMARY - Table 10 is an opcode map
for the instructions used on the MCU.

EA= IPC+ l):IPC+ 2); PC-PC+3
Address Bus High-IPC+1); Address Bus Low-IPC+21

ADDRESSING MODES
The MPU uses ten different addressing modes to give the
programmer an opportunity to optimize the code to all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling
tables anywhere in the memory space. Short indexed accesses are single byte instructions, while the longest instructions Ithree bytes) permit tables throughout memory. Short
and long absolute addressing is also included. Two byte

Indexed, No-Offset - In the indexed, no offset addressing
mode, the effective address of the argument is contained in
the 8-bit index register. Thus, this addressing mode can access the first 256 memory locations. These instructions are
only one byte long. This mode is used to move a pointer
throug!;l a table or to address a frequently referenced RAM or
I/O location.
EA=X; PC-PC+l
Address Bus High-O; Address Bus Low- X

3-37

TABLE 4 -

REGISTER/MEMORY INSTRUCTIONS
Addressing Modes

Immediate
Function
load A from Memory

Mnemonic

Op
Code

lDA

A6

load X from Memory
Store A in Memory

lDX
STA

AE
-

Store X in Memory

STX

Add Memory to A
Add Memory and
Carry to A

I

~

I

Op
Code

Indexed
(No Offset)

Extended

#

#

#

Cycles

Op
Code

#

Bytes

Bytes

Cycles

3
3

C6

3

4

F6

CE

3

4

FE

4
4

C7

3

5

F7

CF

3

3

CB

3

5
4

FF

BB

2
2
2
2
2

B9

2

3

C9

3

4

3

CO

3

3

C2

3

#

#

Bytes

Cycles

2

B6

2

BE

-

B7

-

2
2
-

-

BF

ADD

AB

2

2

ADC

A9

2

2

Subiract Memory

SUB

AO

2

2

BO

2

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

Op
Code

Indexed
(S-Bit Offset)

Indexed
(l8-Bit Offset)

#

#

Bytes

Cycles

#

#

Bytes

Cycles

Op
Code

3

E6

3
4

EE

4

EF

FB

1
1
1
1
1

3

EB

2
2
2
2
2

F9

1

3

E9

4

FO

1

3

4

F2

1

3

Op
Code

#

#

Bytes

Cycles

4

D6

3

5

4

DE

3

5

5

6

D7
DF

3

5
4

3

6

DB

3

5

2

4

D9

3

5

EO

2

4

DO

3

5

E2

2

4

D2

3

5

E7

B
"tI
~
01

,~

AND Memory to A

AND

2
2

B4

C4

F4

1

3

E4

D4

3

3

CA

4

FA

1

3

EA

2
2

4

SA

3
3

4

2

2
2

3

ORA

A4
AA

2

OR Memory with A

4

DA

3

5
5

Exclusive OR Memory
with A

EOR

AB

2

2

B8

2

3

C8

3

4

F8

1

3

E8

2

4

D8

3

5

CMP

A1

2

2

B1

2

3

C1 ,

3

4

F1

1

3

El

2

4

Dl

3

5

CPX

A3

2

2

83

2

3

C3

3

4

F3

1

3

E3

2

4

D3

3

5

BIT

A5

2

2

B5

2

3

C5

3

4

F5

1

3

E5

2

4

D5

3

5

$')

-

BC

2

2

CC

3

3

FC

1

DC

3

4

5

CD

3

6

FD

1

ED

2
2

3

2

2
5

EC

BD

6

DD

3

7

B
"tI

Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory
Col

Direct

Bit Test Memory with
A (logical Compare)
Jump Unconditional

JMP

-

-

Jump to Subroutine

JSR

-

-

Addressing Modes
Inherent (A)
Op
Code
4C

Inherent (X)

#
Cycles
3
3

Op
Code

3

5F

Direct

01

Indexed
(S-Bit Offset)

#
Cycles
3
3
3
3

Op
Code
3C

#
Bytes

#
Cycles

Op
Code

#
Bytes

#
Cycles

2

5

3A

2

5

7C
7A

3F

5

7F

Complement

COM

43

3

53

#
Bytes
1
1
1
1

33

2
2

5

73

1
1
1
1

5

63

2

6

Negate
(2's Complement)

NEG

40

1

3

50

1

3

30

2

5

70

1

5

60

2

6

Rotate left Thru Carry

ROL

49

1

3

59

1

3

39

2

5

79

1

5

69

2

6

Rotate Right Thru
Carry

ROR

46

1

3

56

1

3

36

2

5

76

1

5

66

2

6

lSL
LSR

1
1

3

58

1

3

38

2

6

1

3

34

5
5

68

54

78
74

1

6

57

1

3

37

5

64
67

2

1

3
3

2
2
2

5

ASR

48
44
47

2

6

TST

4D

1

3

5D

1

3

3D

2

4

4

6D

2

5

Mnemonic

Increment

INC

Decrement

DEC

Clear

ClR

4A
4F

logical Shift left
logical Shift Right
Arithmetic Shift Right
Test for Negative
or Zero

5C
5A

5
5

~

C)
Indexed
(No Offset)

#
Bytes
1
1
1
1

Function

~
~

TABLE 5 - READ/MODIFY/WRITE INSTRUCTIONS

---

~

n

1
1

7D

1

Op
Code

#
Bytes

#
Cycles

5

6C

2

6

5

6A

2

6

5

6F

2

6

,~

~

0)

~

01

~

C')

I

CDP6805E~CDP6805E2~CDP6805E~CDP6805E3C

TABLE 6 -

BRANCH INSTRUCTIONS
Relative Addressing Mode
Mnemonic

Function

#

#

Bytes

Cycles

BRA
BRN

20
21

2
2

3
3

Branch IFF Higher

BHI

22

2

3

Branch IFF Lower or Same

BLS

23

2

3

Branch IFF Carry Clear

BCC

24

2

3

IBHSI

24

2

3

Branch IFF Carry Set

BCS

!Branch IFF Lower!
Branch IFF Not Equal

IBLOI
BNE

25
25

2
2

3
3

26

2

3

27

2

3
3

Branch Always
Branch Never

IBranch IFF Higher or Samel

Branch IFF Equal

BEO

Branch IFF Half Carry Clear

BHCC

28

2

Branch IFF Half Carry Set

BHCS

29

2

3

BPL

2A

2

3

Branch IFF Plus
8ranch IFF Minus

BMI

2B

2

3

Branch IFF Interrupt Mask Bii is Clear

BMC

2C

2

3

Branch IFF Interrupt Mask Bit is Set

BMS

2D

2

3

BIL

2E

2

3

Branch IFF Interrupt line is Low
Branch IFF Interrupt line is H.igh

BIH

2F

2

3

Branch to Subroutine

BSR

AD

2

6

TABLE 7 -

BIT MANIPULATION INSTRUCTIONS

------

I

Op
Code

Bit Setl Clear

Addressing Modes
Bit Test and Branch

Branch I FF Bit n is Set

BRSET n

__ 71

-

Bytes
-

Branch IFF Bit n is Clear

BRCLR n In~O _.71
BSET n In~O __ 71

-

-

-

Op
Code
2-n
01 + 2-n

10+ 2-n
11 + 2-n

2

5

-

-

2

5

-

-

Function

Op
Code

Mnemonic

Set Bit n
Clear Bit n

BCLR n

In~O

In~O

_.71

TABLE 8 -

#

#
Cycles
-

#
Bytes
3
3

CONTROL INSTRUCTIONS

'--Inherent-~
Function

Mnemonic

Op
Code

Transter A to X
TAX
97
f-T"'r-a-ns-f-er-X-t-o-A----f--T-X-A--+-9c-F=--

#
Bytes

#
Cycles_

1
1

2
2

99

1

2

Set Carry Bit

SEC

Clear Carry Bit

CLC

98

1

2

Set Interrupt Mask Bit

SEI

9B

1

2

Clear Interrupt Mask Bit

Cli

9A

1

2

Software Interrupt

SWI

83

1

10

I

Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
Reset Stack Poi nter"-'---+--::Rc;S,..'P,----l-9"'C;;---+--:-1-+-c::
2- - \
No.Operation
.-- +--N-O""P,.--f--"9"o-D-+--1--+--c2:---l
f-S=-t-o-p-'---------I--S,-,T=-cC,-P-+- -~f---'-1-+------=-2--1
~~~~~~~-+--~~---~~=--+~~4-~~

Wait

WAIT

3-39

8F

1

2

#
Cycles
5
5
-

CDP6805EZCDP6805E2~CDP6805E~CDP6805E3C

TABLE 9 - INSTRUCTION SET
Addressing Modes
Mnemonic
ADC
ADD
AND
ASl
ASA
BCC
BClA
BCS
BEG
BHCC
BHCS
BHI
BHS
BIH
Bil
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BAA
BAN
BAClA
BASEl
BSH
BSA
ClC
CLI
ClA
CMP
COM
CPX
DEC
EOA
INC
JMP
JSA
lOA
LOX
lSl
lSA
NEG
NOP
OAA
AOl
AOA
ASP
AT!
AlS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT

Inherent

Immediate

Direct

Extended

Relative

Condition Codes

Indexed
(No Offset)

Indexed
(8 Bits)

Indexed
(16 Bits)

Bit

Setl
Clear

Bit
Test &
Branch

X
X

X

X

X

h

X

X

/\

X

X_
X

X
X

X

x

X

X

X

X

X
X

X

X
X

X
X

I N Z C

H

•

X

X
X
X

X
X
X
X
X
X
X

X

X

X

/\

/\

h
1/\

h
h
h

h
h
h

h

•••
••
••
•
••

X

X

h

I-

X

h

h

•h

• •·
••

•••
••
•
•h

X
X
X
X
X
X
X
X
X

X
X

h

X
X

X
X

0

X

X
X
X
X

X
X
X
X
X

X

X

X
X

X
X
X
X
X
X
X
X

X

X
X
X
.X
X
X
X
X
X
X
X

X
X
X
X
X

X
X

X
X
X
X
X
X
X

X
X

iI
X

X
X
X
X

X
X
X
X
X
X
X

X

X
X
X

X
X
X

X

X

X

X

X
X
X

X

X

X-

X
X
X
X
X

X
X
X
X

X
X
X

X

X

X

X

X
X

X
X

X
X

X
X

X
X

X
X
X
X
X
X
X

X

X

X

Condllton Code Symbols
H
I

Half Carry (From Bit 3)
Interrupt Mask.

A

N

NegatIve (Sign Bit I

"1

Z

Zero

o

C

Carry/Borrow

•

Test and Set If True', Cleared Otherwise
Not Affected
Load CC Register From Stack
Cleared

Sel

3-40

-••
•

X

••
••
•
••
••
••
•

h
h
h
h
h
h

h
0

h
h

1

h

1

h

••
•• •• •••
h h •
h /\

X

X

0
h
h
h
h
h
h

••
0
••

A

h
h

A

• • • ••
~

·
•

A

•

••
•••

h

h/\

•
•
A
••
•0 A

"h "h

••
•A •A

••A ••
•••
A A •
•
•• • •A •A •A
,•• -•• •A A• ••
•0 •••

-

1

1

1

I-

TABLE 10 - CDP6805E21NSTRUCTION SET OPCODE MAP
B~

~

,g.,
I
000'

2
00'0

.rk.

, BSE1~~

5

5

, BCl~~~ I,

5

,"
2 BSE~~c_ L2

3BASEJie
5

0'00

4

BASEJfB

5

BRCl~fe

O1~'

5

~

5

13BACl~?B

5

13BASEJ~B

9

BAClR4
3
BTR

'00'
(0)

13BASEJfB

B

,00(1

,:'n

5
5

,BRSEJiR
5

B
1011

BAClA5
BTB
3
5

,fro

.rSEJfB

,Po,

13BAClt6e

E

BRSEJle
!3

5
5

1110

F
1111

5

2 BCl~~c

5

5
0110

I,

BRCl~fe

BRCl~T'e

6

5

BRSEJfR

rJ"

0101

00'\0

00(11
5

5

BRClA7
BTe
3

I2

5

2

Raad/Modifv/Wr~e

Branch
R

Manipulation

T

BSE~~c

'2

5

2 BCl~~c I 2
5

ooh

3

BRAR"
3
BRNRFl
3
BHIRFl
3
BlSREl
3
BCCREl
3
BCSREl
3

,

IX

n1~'

,~

n~
5

NEGDIR

3

n1~n
3

, NEGAINH , NEGXINH

2

NEG
IX'

,:,.,

5

6

I

Control
I H

INH

NEG

RTI

I

IX

,

IMM

,00,

2 COM

DIR

5
2 lSRDIA

3

, COMAINH
3
, lSRAINH

3

, COM~H
3
LSRX
I
INH

6

COM
2

IXl

6

2

LSR

IXI

3

4

INH

SUB
IMM

2 SUBO;R

3 SUBEXT

6

2

3

4

CMP
OIR
2 CM;MM 12

CMP
3
EX'

RTS
INH

2

,

10

SWI
I~H

2

CPX
IMM

2

AND
IMM

2

IX

RORDIR
5

ASRDIR
5

lSl
DIR
5

ROl
DIR

5
5
3
2 BSE~~c_ I 2 BPlREl 2 DECDIR
5
3
2 BCl~~c 12 BMIREl
5
3
5
INC
2 BSE~~c ! 2 BMCREl 2
DIR
4
3
•5
TSTDIR
2 BCL~~c 12 BM~El
5
3
2 BSE~~c 12 Bll R"
5
3
5
BIH
ClR
BClR7
REl 2
L
esc_ 2
DIR

,

3
RORA
INH

,

ASRA
INH
3
lSlA
INH
3
ROlA
INH
3
DECA
INH

,
,
,

3

,

,
,

,
,

3
RORX
INH

6
2 ROR

3

IX'6

ASRX
2 ASR
INH
IX'6
3
lSlX
lSL
INH 2
IX'
3
6
ROlX
ROL
IXI
INH _L
6
3
DECX
DEC
INH 2
IX'

,

,
,

ASR

5

,

IX

,
,

INCA
INH
3
TSTA
INH

,

,

3
INCX
INH
3
TSTX
INH

6

2

IX'

,

5

TST
2

,

,

3
CLRX
INH

6

ClR
2

IX'

,

4

4

5

STA
EXT
3

2

STA
DIR
2
3
EOR
DIR
2
3

ADC
DIR
2

3

ADC
ExT

ORA j
DIR

3

ORA
EXT

eLi

2

INH

, SEI INH
2
, RSPINH
2
, NOPINH

IX

IX

ORA 2
IMM

2

IX
4

5

2

, STOPINH
TXA
, WAIT'
INH ,
INH

2

2

ADD
IMM

2

INH

Inherent
Immediate
Direct
Eytended
Relative
Bit Set/Clear
Bit Test and Branch
Indexed (No Offsetl
Indexed, 1 Byte (8·Bit) Offset
Indexed, 2 Byte (l6-Bitl Offset
CMOS Versions Only

ADD
DIR

ADD
EXT
3
JMP
EXT
3

JMP
DIR
2

2

lDX
IMM
2

2

3

5

6

DIR

JSR
EXT
3

LOX J
DIR
2

LOX
EXT
3

6

BSR
REl
2

JSR
2

3

4

4

5

STX
DIR
2

STX
EXT
3

,Xl
4

'X'

,

,x'

I

SBC
2

CPX

x~

2

AND
,X-

3

1)(2

'x2

5'

EOR

EOR
:X2

2

5

ORA

ADD
3

2

,Xl

2

ADD
JMP

JMP
J

IX2

2

7

3

JSR

.x2

3

'Xi

,

ORA

IX"

J

I,

,x'

2

IX2

2

IX

:;100

3

,

4

:;1~1

X

6

:,,"C

7

x

,

,"
I,

x

'XX;

9

'X'

J

ADD

A
3
,x

,

B
C

"X

5

JSA

,

LOX

,

0

"

..

,E

4

STX 51
IX 1

I1

STX

,

F,

..

r--~.=4---------::::-,
F •
~ Opcode in Hexadecimal

~

r ,?1xl

# of Cycles - - - - - - -

(XXX)

"

C1i

,~

~

~

~

$")

g
"l:J

0)

00

C1i

,~

~

LEGEND

Mne~~~~

"l:J

~
Q

Q

3

I

g

0)
8

x

JMP

j

LDX
1X2
6

"3

3

ADC

4

5

STX

•

,

2 JSR,x:

LOX
3

EOR

4

4

3
)jl1

4

STA

4

'x2
5

2
XIG

3

J!

ADC
2

ORA
3

i,

IX 1 '

5

IXI

,x

1

3

IX'

2

5
3

BIT

;X 1 : '

STA

3

AND

LDA

2

:0;1

CPX

4

6

ADC

I

IX 1

LDA

STA

3

I

BIT
2

'x

3

IX'

5
3

SBC

4

LDA

=

3

4

AND

0

3

"

4

2

BIT

SUB
CMP

2

'Xl
5

3

3

4,

5

4

4

2

'XI

3

i~

SUB,Xl

5

4

3

2

Abbreviations for Address Modes

IMM
DIR
EXT
REL
BSC
BTB
IX
IXl
(X2

EOR
ExT
3

2

I

"
SBC

4

ADC
IMM
2

INC

CLR

EXT

lDA
EXT
J

12 LDAIMM

2

3
ClRA
INH

3

3

2

5

TST

BIT

SEC
INH

I

3

Hi~w

1111

CMP

4

5

5

,

AND
EXT

3

~

CPX

"EXT
4

3

AND
DIR
3
2 BIT
DIR
2

,X2
5

CPX
3

IX

, DEC IX

IX'

INC

CPX
DIR

2

EOR
ClC
I
I H I?
IMM

IX

ROl

2

SUB

IX
F

I
4 ,

CMP

4

2

2

I

SBC
ExT

3

3

TAX
INH

5

LSl

DIR

lDA
DIR
2

IX

I
3

BIT,
IMM

5

ROR

I

2

SBC
2

5

4

3

Xl

,,~.

,~,

2

12
5

,fro

,~,

9

5

, COM IX ,
5
, LSR

Reaister I Memory
EX
1X2

DIR

,t,.

9

SBC
IMM
5

2 BSE~1c I 2 BNEREl 2
5
3
2 BCl~~c 2 BEQREl 2
3
5
2 BSE1~c I 2 BHC~El 2
3
5
2 BCl~~~ , BHC~ 2

l

INH X

;j

Opcode in Binary

Address Mode

~

Q

~

C")

CDP6805E~CDP6805E2~ CDP6805E~CDP6805E3C

Indexed, 8-bit Offset - Here the EA is obtained by adding
the contents of the byte following the opcode to that of the
index register. The operand is therefore located anywhere
within the lowest 511 memory locations. For example, this
mode of addressing is useful for selectinq the m-th element in
an n element table. All instructions are two bytes. The contents of the index register (XI is not changed. The contents
of (PC + 11 is an unsigned 8-bit integer. One byte offset indexing permits look-Up tables to be easily accessed in either
RAM or ROM.

EA = PC + 2+ (PC + 1); PC-EA if branch taken;
otherwise PC- PC + 2

Bit Set/Clear - Direct addressing and bit addressing are
combined in instructions which set and clear individual
memory and I/O bits. In the bit set and clear instructions, the
byte is specified as a direct address in the location following
the opcode. The first 256 addressable locations are thus accessed. The bit to be modified within that byte is specified
with three bits of the opcode. The bit set and clear instructions occupy two bytes, one for the opcode !including the bit
number! and the second to address the byte which contains
the bit of interest.
EA= (PC+ 11; PC-PC+ 2
Address Bus High-O; Address Bus Low-(PC+ 11

EA= X+ (PC+ 11; PC-PC+ 2
Address Bus High-K; Address Bus Low-X+(PC+11
Where: K = The carry from the addition of X + (PC + 1)
Indexed, l6-Bit Offset - In the indexed, 16-bit offset addressing mode the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This addressing mode
can be used in a manner similar to indexed 8-bit offset, except that this three byte instruction allows tables to be
anywhere in memory (e.g., jump tables in ROM I. The content of the index register is not changed.

Bit Test and Branch - Bit test and branch is a combination of direct addressing, bit addressing and relative addressing. The bit address and condition (set or clear! to be tested
is part of the opcode. The address of the byte to be tested is
in the single byte immediately following the opcode byte
(EA 11. The signed relative 8-bit offset is in the third byte (EA21 and
is added to the PC if the specified bit is set or clear in the
specified memory location. This single three byte instruction
allows the program to branch based on the condition of any
bit in the first 256 locations of memory.
EA1 = IPC+ 1)
Address Bus High-O; Address Bus Low-IPC + 11
EA2 = PC + 3 + I PC + 21; PC - EA2 if branch taken;
otherwise PC- PC + 3

EA=X+[(PC+1):(PC+21); PC-PC+3
Address Bus High- (PC + 1) + K;
Address Bus Low-X+(PC+2)
Where: K = The carry from the addition of X + (PC + 2)

Relative - Relative addressing is only used in branch instructions. In relative addressing the contents of the 8-bit
signed byte following the opcode (the offset) is added to the
PC if and only if the branch condition is true. Otherwise,
control proceeds to the next instruction. The span of relative
addressing is limited to the range of - 126 to + 129 bytes
from the branch instruction opcode location.

SYSTEM CONFIGURATION
Figures 20 through 24 show in general terms how the
CDP6805E2 bus structure may be utilized. Specified interface details vary with the various peripheral and memory
devices employed.

Chip
Enable

AS-A12

Typical CMOS
Peripheral

CDP6S05E2
CMOS
Microprocessor

BO-B7

AS
DS
R/W
IRQ
OSCl

Address/ Data Bus
Address Strobe
Data Strobe
Read/Write
Interrupt
~19~H.L

ADO-AD7

AS
DS

R/W

iRQ
CKOUT
RESET

RESET

92CS-38035

Fig. 20 - Connection to CMOS peripherals.

3-42

CDP6805E~CDP6805E2~CDP6805E~CDP6805E3C

CDP6805E2

Peripherals

DS~____~D~a~ta~S~tr~o~be~__~

R/IN ~____-,R..;.;e""a",d,--/W="",te'-___"""R lIN
IRO

Interrupt

IRO
RESET

RESET
NOTE: In some cases, pullup resistors or other level
shifting techniques may be required on signals
gOing from NMOS to CMOS parts.

92CS-38037

Fig. 21 - Connection to peripherals.

BO-B7,/l

Address/Data Bus

Data

"-.r

CDP6805E2

A~

AS-A12

R/IN
OS

AS

)

Address

Readl
Write

Read

Data Strobe

J
]

U
Address
Decode

l

Output
Enable

I

Chip
Enable

Address
Strobe

00-07
CMOS
Non-Muxed
AO-A7 ROM or
EPROM

AS

S-

E
92CS-38038

Fig. 22 - Connection to latch non-multiplexed CMOS ROM or EPROM.

3-43

CDP6805EZCDP6805E2~ CDP6805E~CDP6805E3C

CMOS
Static
RAMs

CDP6805E2

CMOS
Microprocessor

DO-D7

A8

A8A12

A9

r----tE

DS~~-----i-~

Readl

R/W Write

92CS-38039

Fig. 23 - Connection to static CMOS RAMs.

Address/ Data Bus

Data

0007
CMOS
AO AI

CDP6805E2

Non MUXt~d

RAM

AS

Address

A8A12

Output

Data
Strobe

tllable

S

DS
Read!

Wllte

Write

R/Vii

AS

Address
Strobe
Chip
E:nable

E

92CS-36040

Fig. 24 - Connection to latched non-multiplexed CMOS RAM.

3-44

CDP6805E~CDP6805E2~ CDP6805E~CDP6805E3C
pected results during debug of both software and hardware
as the control program is executed. The information is
categorized in groups according to addressing mode and
number of cycles per instruction.

Table 11 provides a detailed description of the information
present on the Bus, the Read/Write (R/W) pin and the Load
Instruction (LI) pin during each cycle for each instruction.
This information is useful in comparing actual with ex-

TABLE 11 - SUMMARY OF CYCLE BY CYCLE OPERATION
Address Mode
Instructions
Inherent
LSR LSL
ASR NEG
CLR ROL
COM ROR
DEC INC TST
TAX CLC SEC
STOP CLI SEI
RSP WAIT NOP TXA

I

R/W
Pin

LI
Pin

3

Op Code Address
Op Code Address + 1
Op Code Address + 1

1
1
1

1
0
0

Op Code
Op Code Next Instruction
Op Code Next Instruction

1
2

Op Code Address
Op Code Address + 1

1
1

1
0

Op Code
Op Code Next Instruction

1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1

1
0
0
0
0
0
1
0
0
0
0
0
0
0

Op Code
Op Code Next Instruction
Irrelevant Data
Irrelevant Data
Irrelevant Data
New Op Code
Op Code
Op Code Next Instruction
Return Address (LO Byte)
Return Address (HI Byte)
Contents of Index Register
Contents of Accumulator
Contents of CC Register
Address of Int. Routine (HI Byte)
Address of Int. Routine (LO Byte)
Interrupt Routine First Opcode
Op Code
Op Code Next Instruction
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data

Cycles

Cycle #

3

1
2

2

1
2
RTS

6

3
4

5
6
1
2

3
4
SWI

10

5
6
7
8
9
10
1
2

3
4
RTI

9

5
6
7

8
9
Immediate
ADC EOR CPX
ADD LOA LOX
AND ORA BIT
SBC CMB SUB
Bit Setl Clear
BSET n
BClR n

2

5

Address Bus

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
i Stack Pointer + 2
New Op Code Address
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Vector Address 1 FFC (FFFC) (Hex)
Vector Address 1 FFD (FFFD) (Hex)
Interrupt Routine Starting Address
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
New Op Code Address

1
2

Op Code Address
Op Code Address + 1

1
1

1
2
4
5

Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand
Address of Operand

1
1
1
1

1
2

op Code Add ress

3

0

0
0
1
0
0
0
0
0
0
0

Data Bus

Irrelevant Data

0

New Op Code

1

0

Op Code
Operand Data

1
0
0
0
0

Op Code
Address of Operand
Operand Data
Operand Data
Manipulated Data

1
0

Bit Test and Branch
BRSET n
BRCLR n

5

Address of Operand
Op Code Address + 2
Op Code Address + 2

1
1
1
1
1

0
0
0

Op Code
Address of Operand
Operand Data
Branch Offset
Branch Offset

3

Op Code Address
Op Code Address + 1
Op Code Address + 1

1
1
1

1
0
0

Op Code
Branch Offset
Branch Offset

1
2
3
4
5
6

Op Code Address
Op Code Address + 1
Op Code Address + 1
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1
0
0

1
0
0
0
0
0

Op Code
Branch Offset
Branch Offset
First Subroutine Op Code
Return Address (lO Byte)
Return Address (HI Byte)

3
4

5
Relative
BCC BHI BNE BEQ
BCS BPl BHCC BLS
Bil BMC BRN BHCS
BIH BMI BMS BRA

BSR

3

6

1
2

Op Code Address

+1

3-45

CDP6805E~CDP6805E2~CDP6805E~CDP6805E3C
TABLE 11 -

I

Address Mode
Instructions

I

Cycles

SUMMARY OF CYCLE BY CYCLE OPERATION (CONTINUED)

Cycles I

R/W
Pin

LI
Pin

Op Code Address
Op Code Address + 1

1
1

0

Op Code Address
Op Code Address + 1
Address of Operand

1
1
1

0
0

Op Code Address
Op Code Address + 1
Address of Operand
Op Code Address + 2
Op Code Address
Op Code Adrress + 1
Op Code Address + 1
Address of Operand

1
1
1
1

0
0
0

Address Bus

Data Bus

Direct
JMP

2

ADC EOR CPX
ADD LDA LDX
AND ORA BIT
SBC CMP SUB

3

TST

4

STA
STX

4

1

2
1

2
3
1
2
3
4
1

2
3
4
1

LSL LSR DEC
ASR NEG INC
CLR ROL
COM ROR

2
5
----

5

JSR

3
4
5
1

2
3
4
5

1
1

1

1
1
1

1

0
0
0

0

._-

Op Code Address
Op Code Address + 1
Operand Address
Operand Address
Operand Address
._--------Op Code Address
Op Code Address + 1
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1

1

0
0
0
0

-,
0

1

0
0
0
0

1
1

0
0

Op Code
Jump Address
Op Code
Address of Operand
Operand Data
Op Code
Address of Operand
Operand Data
Op Code Next Instruction
Op Code
Address of Operand
Address of Operand
Operand Data
Op Code
Address of Operand
Current Operand Data
Current Operand Data
New Operand Data
Op Code
Subroutine Address (LO Bytei
1st Subroutine Op Code
Return Address (LO Bytei
Return Address (HI Bytei

Extended
1

3

JMP

2
3
1

ADC BIT ORA
ADD CMP LOX
AND EOR SSC
CPX LOA SUB

..

---

4

2
3

f-----

4
1

STA
STX

5

2
3
4

--

----

5
1

2
JSR

6

3
4
5
6

Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Address of Operand
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

--

1
1
1

1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0

1
1
1
1
- - - ----1
1
1
1
-----

0
1
1
1
1

0
0

Op Code
Jump Address (HI Bytei
Jump Address (LO Bytei
Op Code
Address Operand (HI Bytei
Address Operand (LO Bytei
Operand Data
Op Code
Address of Operand (HI Bytei
Address of Operand (LO Bytei
Address of Operand (LO Bytei
Operand Data
Op Code
Address of Subroutine (HI Bytei
Address of Subroutine (LO Bytei
1st Subroutine Op Code
Return Address I LO Bytei
Return Address (HI Byte)

Indexed, No-Offset

2

JMP
ADC EOR CPX
ADD LOA LOX
AND ORA BIT
SBC CMP SUB

-- - - _ . 3

TST

4
- - - _ .. _..

STA
STX

-_.4

--1----LSL LSR DEC
ASR NEG INC
CLR ROL
COM ROR

5

Op Code Address
1
Op Code
1
1
Op Code Next Instruction
2
Op Code Address + 1
1
0
_._-- - - - - - - - - - 1---- ----Op Code
1
1
Op Code Address
1
Op Code Next Instruction
2
Op Code Address + 1
1
0
Index Register
1
0
Operand Data
3
_._-_._------ - -_.
1
Op Code
1
Op Code Address
,I
Op Code Next Instruction
Op Code Address + 1
1
0
2
Operand Data
3
Index Register
1
0
4
1
0
Op Code Address +.J __.___ - _ . _ - - . - --_._-_2p Cod~<:"!..lnstructlon
---Op Code
1
1
Op Code Address
1
Op Code Next Instruction
2
Op Code Address + 1
1
0
Op Code Next Instruction
3
Op Code Address + 1
1
0
Operand Data
4
Index Register
0
0
--::------------ ..._._-_._-- ---- - --_ ...
- --------1
1
1
Op Code
Op Code Address
Op Code Next Instruction
2
Op Code Address + 1
1
0
Current Operand Data
Index Register
1
0
3
4
Index Register
1
0
Current Operand Data
5
Index Register
0
0
New Operand Data
------------ -- - -'. -------------1
Op Code Address
1
Op Code
Op Code Next Ins true lion
Op Code Address + 1
1
0
2
Index Register
1
0
1st Subroutine Op Code
3
Return Address {LO By tel
4
Stack POinter
0
0
Return Address (HI By tel
Stack Pain ter
0
5
1
0

-1---;-

JSR

5

I

3-46

CDP6805E~CDP6805E2~CDP6805E~CDP6805E3C

TABLE 11 -

SUMMARY OF CYCLE BY CYCLE OPERATION (CONTINUEDI

1-___A. : ~. : ~:; r~:.: :.:ct_=~: :o~:.: ~=_
_e _ _L_C_Y_C_le_:_"l~YCleS # I-~=----

-'::d:re:-~=- -

- - __

_ -_-:_-_-_-_-_-_--D_-_a-t_a~-B_-u_S~~~~~~-.

I~~I-f;~J-_-

Indexed 8-Bit Offset

1

3

JMP
ADC
ADD
AND
SUB

EOR CPX
LOA LOX
ORA CMP
BIT SBC

STA
STX

2
3
1

4

2
3
4
1

5

2
3
4
5

1
2
TST

LSL LSR
ASR NEG
CLR ROL
; COM ROR
, DEC INC

JSR

5

6

Op Code Address
Op Code Address + 1
Op Code Address + 1
Op Code Address + 1
Index Register + Offset

1

Op Code Address
Op Code Address + 1
Op Code Address -r 1
Index Register + Offset
Index Register + Offset
Index Register + Offset

3
4

5
6
1
2
3
4
5
6

Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Stack Pointer
Stack Pointer - 1

Op Code
Offset
Offset

1

Op Code
Offset
Offset
Operand Data

o

o

o
1
1
1
1

o

1

o

o
o

o
1

Op Code Address
Op Code Address + 1
p Code Add ress + 1
Index Register + Offset
Op Code Address + 2

o

1

o
o

Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset

3
4
5

2
6

Op Code Address
Op Code Address + 1
Op Code Address + 1

o

o
o
o
1
1
1
1

1

o
1

1

o
o
o

o
o
1

o

1
1
1

o
o

o

o

o

o

Op Code
Olfset
Offset
Olfset
Operand Data
Op Code
Olfset
Offset
Operand Data
Op Code Next Instruction
Op Code
Offset
Offset
Current Operand Data
Current Operand Data
New Operand Data
Op Code
Offset
Offset
1st Subroutine Op Code
Return Address LO Byte
Return Address HI Byte

Indexed, 16-Bit Offset

JMP

ADC CMP SUB
ADD EOR SBC
AND ORA
CPX LOA

4

5

BIT LOX

1
2
3
4
1
2
3
4
5
1

2
STA

I STX

6

3
4

5
6
1
2

3
JSR

7

4

5
6
7

Op Code Address
1
1
Op Code
1
0
Offset (HI Byte)
Op Code Address + 1
Op Code Address + 2
1
0
Offset (LO Byte)
fs::ee2-t..::(L:..:O:...:::B-,-yt:.:e21- - - - - - 1
Op Code Address + 2 ______+_1:--+-_..::0:--+-:0:-:f..::
Op Code Address
1
1
Op Code
1
0
Offset (HI Byte)
Op Code Address + 1
Op Code Address + 2
1
0
Offset (LO Byte)
Op Code Address + 2
1
0
Offset (LO Byte)
Index Register + Offset
______+_c-l--j_ _-'-O_t-::0"'p-'-e:;:ra:c-n..::d_DC-'-at"'a_ _ _ _ _ _- l
Op Code Address
1
1
Op Code
Op Code Address + 1
1
0
Offset (HI Byte)
Op Code Address + 2
1
0
Offset (LO Byte)
Op Code Address + 2
1
0
Offset (LO Byte)
Op Code Address + 2
1
0
Offset (LO Byte)
~dex Register + Offse_t_______-t--__ ..::O_t-__O:--+O:::-p:;ce=:rO'a..::nd=--::D--=a-=-ta=--_ _ _ _ _---t
Op Code Address
1
1
Op Code
Op Code Address + 1
1
0
Offset (HI Byte)
Op Code Address + 2
1
0
Offset (LO Byte)
Op Code Address + 2
1
a Offset (LO Byte)
Index Register + Offset
1
1st Subroutine Op Code
Return Address (LO Byte)
Stack Pointer
0
Stack Pointer - 1
0
Return Address (HO By tel

a
a
a

3-47

CDP6805E~CDP6805E2~CDP6805E~CDP6805E3C

TABLE 11 - SUMMARY OF CYCLE BY CYCLE OPERATION (CONTINUEDI

CYCI~~- CYCle~{ __

Instructions
Other Functions

Power on Reset

1922

Cycles

0

1

0

Irrelevant Data

$1 FFE ($FFFE)

0

1

0

Irrelevant Data

$1 FFE ($FFFE)
$1 FFE ($FFFE)

1

1

0

Irrelevant Data

2

1

1

0

Irrelevant Data

3

$1 FFE ($FFFE)

1

1

0

Vector High

4
5

$1 FFF ($FFFF)

1

Reset Vector

1
1

1

Vector Low
Op Code

1

$1 FFE ($FFFE)

1

1

0
0
0

•
•
•

•
•
•

•
•
•

1

1

0

Irrelevant Data

1920
1921

$1 FFE ($FFFE)
$1 FFE ($FFFE)
$1 FFF ($FFFF)

1

1
1

0
0

Vector High

1

1922

Reset Vector

1

1

0

Op Code

iRQ

R/W

Pin

Pin

LI
Pin

•
•
•

•
•
•

Cycles #

Address Bus
Last Cycle of Previous

10

•
•
•

Vector Low

Data Bus

0

X

0

X

Next Op Code Address

0

1

0

Irrelevant Data

Instruction

IRQ Interrupt
ITimer Vector $1FF8, $1FF9)

I rrelevant Data

1

I

I

Data Bus

$1 FFE ($FFFE)

1919

Instruction

LI
Pin

Pin

1

5

- -

Pin

---c--

Hardware RESET

----~~----7ESrrpfW-r

Address Bus

2

Next Op Code Address

X

1

0

3

SP

X

0

0

Irrelevant Data
Return Address ILO Byte)

4
5
6
7

SP-1
SP-2
SP-3

X
X
X

0
0

0
0

Return Address IHI Byte)
Contents Index Reg

a

a

Contents Accumulator

SP-4

X

0

0

Contents CC Register

8

$1 FFA ($FFFA)

X

1

0

Vector High

9

$1 FFB ($FFFB)

X

1

0

Vector Low

X

1

a

Int Routine First

10

i IRQ Vector

3-48

CUSTOMIZED MICROCONTROLLERS
PAGE
CUSTOMIZED CDP68HC05 MICROCONTROLLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3

General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4-3

...t!

1:2 ...

w'"
NC
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::IE ...

oZ

I-C
c:nc.:l
::IC

UII:

c.:I

i

4-1

Customized CDP68HC05 Microcontrollers
General Information
Harris Semiconductor supports the development of application specific microcontrollers based on the UH68HC05, an
enhanced version of the 68HC05.
You need not share a design with others to take advantage
of our offering and can be sure that our core based methodology is both quick turn and cost effective even without the
prospect of high volume production. We pride ourselves on
its flexibility and know that, regardless of your custom
microcontroller application, our methodology is general
enough to meet your needs.
Our approach has many benefits. Improved system
reliability and reduced system cost are two of the most
important. This is due to the need for fewer components, the
resulting requirement for less board level testing, as well as
the reduction in size of the PC board itself. Other
advantages are lower power consumption and reduced
overall system size. Finally, the unique features of your
design are realized in proprietary silicon. Clearly, all of these
benefits help to significantly improve the competitive
position of your product.

resemble microprocessors. Access to the micro's address
and data busses permit the user to interface memory and
peripherals externally and evaluate the microcontroller.
They can be used to support both hardware design and
software development on stand alone breadboards or in
code development systems.
In addition, once customer specific devices have been fabricated, a standard "expansion" IC in combination with the
customer specific design can be used for further in circuit
software debugging with or without the help of a code development system. Table 3 summarizes the availability of
hardware/software for the core.
The suitability of either of our core macrocell for a given
application can be explored in detail with your local Harris
Sales Office or Representative.
TABLE 1. TYPICAL APPLICATIONS
UH68HCOS
Automotive instrument cluster, automotive cruise control,
security systems, telephones, pagers, sonar, printers, scales,
consumer electronics, modems, smart cards.
TABLE 2. AVAILABLE LANGUAGES

The UH68HC05 offers the mid range performance of one of
the industry's most popular 8-bit MCU's. Table 1 contains
typical applications of each of the UH68HC05 core.
Table 2 summarizes the programming languages available
to support the UH68HC05 core. Today's code development
systems provide the design engineer with a complete
closed loop development capability from source code generation through in circuit debugging. Figure 1 illustrates the
American Automation EZ-Pro'· code development
system. Several alternatives are provided for prototype
development.

ASSEMBLY

C

x

x

UH68HC05

NOTE: UH68HC05 fully compatible with Harris/Motorola 68HC05

Evaluation ICs are available for the UH68HC05 core and
can be used for breadboarding prototypes. These IC's are
packaged versions of the UH68HC05 core macrocell that

TABLE 3. HARDWARE/SOFTWARE SUPPORT
EVALUATION
IC

EXPANSION
IC

AMER.
AUTO.
DEVSYS.

X

X

X

UH68HC05

NOTE: Inquiries on evaluation and expansion les should be directed
to your Harris Sales Office or Representative.
For Development System contact Amedean Automation,

2651 Dow Ave, Tustin, CA 92680 (714) 731-1661

ADDR/DATA..cNTL

GENERAL POD
ELECTRONICS
EVALUATION IC
OR PLUG -IN
BREADBOARD OR
ASIC PROTOTYPE

EZ-PRO
BOX
WITH 16K
RAM

PLUG
INTO
TARGET
BOARD

EXp~~SION I+---::'PO"'R"'T;:;S'--A~AN""D;::-;;B:--""
ASIC MICRO
EQUIVALENT
PINOUT
5-Brr
DIPSWITCH
TO DlALIN
MEMORY SIZE

--f--+------'
FIGURE 1. EZ-PRO CODE DEVELOPMENT SYSTEM

EZ-Pro"" is a trademark of American Automation Inc.

4-3

V-

...

a:
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........
NC

- a:

==1-

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:iii

initiated since it is often known early in the design process
that much of the functionality of the application must be
based in software.

Support for Enhanced Testability Assures
Your Success
The testability of your design is enhanced by built in
features of the Harris core. It can be operated in up to three
modes. These modes are called SCM (Single Chip Mode),
PTM (Prototype Mode), and NUM (Non User Mode). Table 4
summarizes the available modes for each of the cores.
Single chip mode is the normal operational mode of each
customer specific microcontroller.

Software development is a significant component of any
custom core design effort. Code development systems exist
for each of Harris' core macrocells as indicated in Table 3.
TABLE 4. BUILT-IN TEST FEATURES

I

When operated in prototype mode, the internal ROM is
inhibited and instructions are fetched from an external
source. This mode is used to test the CPU independent of
the I/O.

SCM

PTM

NUM

x

x

x

UH68HC05

For the UH68HC05 core, there are two ports which are
considered to be components of the basic core. In
prototype mode they are reconfigured to provide access to
_the internal memory address and'data bus. An expansion IC
is available which - recreates the two ports and in
conjunction with the signals from the micro, provides an
interface to industry standard EPROM where program
memory can be stored. All the functions of the customer's
core based microcontroller are available and, as was
mentioned above, memory transfers can be monitored for
code development and debugging of the final system.

PRE - LAYOUT DESIGN VERIFICATION

Non user mode is intended to be used for testing of the
customer's I/O functions independent of the CPU. In this
mode, the CPU is inhibited and internal memory and
memory mapped I/O functions are exercised with
predetermined test programs.

f".----'---+!

POST -LAYOUT DESIGN VERIFICATION

The support· that Harris provides for enhancing the
testability of your custom core microcontroller and the
system in which it resides increases the reliability of your
product while reducing the cost of testing it.

IN - SYSTEM PROTOTYPE DEBUG

I

MANUFACTURING

h

:.:'-~:"":·:::·:;:'y';y'~.:.:,;.:«..:·x~·:.:::;:;:-:-:-:;:.:.:·:-:.:·:;:;:.(.;:

Explore Your System Design Alternatives
Figure 2 depicts the custom core based microcontroller
development process. The initial phase of the custom core
design flow, as illustrated in Figure 3, begins with the partitioning of the application at the board level into on
versus off chip functions and at the chip level into hardware
and software. This is followed by the hardware design of the
I/O at the chip level, the supporting core functions, and the
glue logic to be implemented in dedicated silicon, and the
development of the balance of the application's functionality
in software.
During this phase of the design process, hardware/software
tradeoffs are examined repeatedly. This activity is facilitated
by the use of the code development system in conjunction
with the available evaluation IC for the core of your choice.
Typically, the more functionality embedded in software, i.e.
the larger the software development effort, the smaller the
chip. Of course, functionality implemented in software will
generally not be as fast as that same function imbedded in
hardware. Consequently, the hardware/software tradeoffs
evolve during that part of the system development effort
devoted to hardware design.

FIGURE 2. CORE BASED MICROCONTROLLER
DEVELOPMENT FLOW

I

I

I
HARDWARE
DESIGN

HARDWARE!
I"l~t--___
S_O__
FT
__W
__A
__R
__E____

11

:-:~':'~:':';';':-:':';':'r':':';':':';';';-:-:-:';':';';';'~'::

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TRADEOFFS

4-4

DESIGN

I

r-------.. .
SCHEMATICS

-.':1:r,

Il~

FIGURE 3. SYSTEM DESIGN

I:'
I

«Y:v:.:.;.;v:.:.;.J~

';·:·:·:';';';«·:V',;·:r:·;..

ROM :.g.ERNS

Once the hardware design is completed, the software
development effort is fully defined. However, the design and
implementation of the software may have -already been

I
SOFTWARE

Each system consists of hardware support for high level
or assembly level programming, including a compiler or
assembler, and a debugger. Such systems are employed to
facilitate the writing and debugging of the dedicated application software (firmware) in the context of the application.

l

SCHEMATICS

AND

S~~TwE.~/E

~
REDES~

II

l

~~~m~J

B~:D~Els~I?G:NARED r~

.........u. . ····r·..

SYSTEMI
SOFTWARE
REDESIGN

1~~ FAIL

k.d ~~~i,~~~~~~~ ~LA.,..·~"'····"'····.,..···"'····"'

...,..····"'····""·
.. ·j

.~N ••••W··· . .··r;~;;;;··mm

FIGURE 4. PRE-LAYOUT DESIGN VERIFICATION

I

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--1---

llo-:

:,.:.:.;;~:.:.:.:.:.~~:.:.;.:.:,.;;:,.:,.:.~;.;.:.:.:.;.;.y;.;.;.;.:.::-;

ADDRESS
& DATA

Third party assemblers and compilers for the standard
68HC05 may also be used to develop code for the corresponding Harris core macrocell. They are especially useful
for developing code to be down loaded into an EPROM for
debugging in a breadboard before committing patterns to
on chip ROM. At the conclusion of the software development phase, the system that you are implementing is
defined by the hardware schematics and the ROM
patterns that you have generated in the course of software
development. At this point, the system verification phase of
the custom core deSign process begins.

---+---_
-----t
1,0 PORTS

t';~j-'

68 LEAD
EVALUATION

1

t

Ie
:~
"""""'.>0''''''''''''''''''''''''''''''''''''''''

1-·0-------·,I".,.,,,.,,w:::.WhL)
•••
••
•

Proving Your System Concept Through
Design Verification

Figure 5 illustrates how reprogramming of the prototype is
facilitated by the use of the EPROM on the breadboard. This
is the infamous "burn and crash" apPfoach to microcode
development. At each iteration of the system verification
process, new microcode is generated and then burned into

I

BREADBOARD IF.,,_Y_ES_ _-,
PROTOTYPE

As was mentioned earlier and is illustrated in Figure 1, AA's
EZ-Pro development system can be employed to support
software development in conjunction with the use of both
evaluation and expansion IC's. Any custom I/O is prototyped on a plug in card. The evaluation and expansion IC's
are mounted on the EZ-Pro code development system pod.
The custom I/O card is plugged into the pod which is then
plugged into the target system. Code is written, compiled
and linked on the PC. The programmer then downloads the
patterns to the RAM in the EZ-Pro box. The evaluation IC on
the EZ-Pro pod is then driven from the RAM in order to verify the performance of the software in the system. When
problems are uncovered, the software is easily modified on
the PC and the process is repeated until the developer is
satisfied that the software meets its speCifications.

The system verification phase of the development process
is illustrated in Figure 4. If you haven't previously breadboarded your design for use with a code development
system, at your option, you can now build a hardware prototype. You ·can verify the logical function of your system by
incorporating on the breadboard an evaluation IC for the
core of your choice, an EPROM to facilitate reprogramming,
a dedicated device to reproduce your custom I/O (e.g., by
means of a programmable gate array), and available evaluation ICs for any other megafunctions (Tables 6a & 6b) which
have been implemented as macrocells in your design.

:;;

. . . . . ,.,.".·,·d

~.w"'r

. w •.•

The potential ineffiCiency of compiler generated code must
be taken into account when choosing the programming language for your application. Tables 5a & b illustrate this issue
by comparing 68HC05 assembly language and machine
code for a simple task to that generated from high level C
code for the same task. Note that in this example both ROM
efficiency and speed efficiency of the compiled C code is
90% of the corresponding hand written machine code. This
is an example of an acceptable trade off when choosing a
compiler based code development methodology.

JJi~:~

ROM PATIERNS

•••

, ,:,::::~:,::'::."."I
••
•

FIGURE 5.

the EPROM for subsequent execution on the breadboard.
Clearly, the use of a code development system in conjunction with the hardware prototype is a better alternative. In
this case, the code development system is interfaced directly to the breadboard. At each iteration, new microcode is
downloaded into the RAM in the code development system
box from which the evaluation IC on the breadboard is driven. The code development system provides a sophisticated
level of support for the isolation and subsequent
correction of problems as they are detected. At the
successful completion of this optional phase of the design
verification process, a simulation of the design is
undertaken.

4-5

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TABLE SA. "C n

VS.

68HC05 ASSEMBLY

1* Least significant nibble (4 bits) of Port B set as inputs reading switches. Most significant nibble of Port B set as outputs driving
common-anode LEOs. */
1* Routine to repeatedly read Port B switches and, if value read is less than or equal to 9, copy to Port B LEOs. */
CSOURCE
#pragma portrw
#pragma portw
main 0
{
intn;
ddrb = OxfO;

portb
ddrb

COBJECT

HAND CO.DED ASSEMBLY
#asm
PORTB
DDRB

@1;
@5;

LOA
STA

#$FO
$05

LOA
STA
CMP
BHI
LSLA
LSLA
LSLA
LSLA
COMA
STA

$01
$50
#$09
$****

BRA
RTS

$0104

EQU
EQU

$01
$05

LDA
STA

#$FO
DDRB

LOA

PORTB

CMP
BHI
LSLA
LSLA
LSLA
LSLA
COMA
STA

#$09
LOOP

for (;;)

I
n= portb;
If (n <= 9) portb = - (n«

4);

LOOP

$01

PORTB

}

}

BRA
RTS

LOOP

#endasm
TABLE 5B. "C n

VS.

68HC05 ASSEMBLY

CSOURCE
Statements

COBJECT

MACHINE
20

8

Byles

22

20

Machine
Cycles

46

42

TABLE 6A.

ADVANCELL~

COMPATIBLE MEGAFUNCTIONS

INDUSTRY PART #

DESCRIPTION

8237

Direct Memory Access Controller

8250

UART

8252

Serial Controller Interface

8254

Timer

8255

Programmable Peripheral Interface

8259

Interrupt Controller

TABLE 6B. 68HC05 COMPATIBLE MEGAFUNCTIONS
MODULE NAME

DESCRIPTION

SPI

Serial Peripheral Interface

SPI2

Serial Peripheral Interface II

SCI

Serial Communication Interface

SBCI

Serial Bus Communication Interface

PWM

Pulse Width Mudulator

PortC

8-Bit Bidirectional Port

Programmable Timer

16-Bit free running counter with
compare and capture capabilities

ADVANCEll

-. a
IS

At the successful conclusion of this simulation, the design is
considered to be verified and your custom core
microcontroller is ready to be physically implemented with
automatic placement and routing tools. Your level of
involvement in the various phases of the design process is
up to you; Harris has the flexibility to support the develop·
ment of your core based m icrocontroller in the
manner that works best for you.
Prototypes Make Your Idea a Reality
After place and route has been completed, a post layout
nellist is generated with back annotated loading which reo
flects the actual wiring in the design. This netlist is then
used to drive another simulation in order to reverify both the
function and timing of the design but now with the parasitics
of the layout taken into account. You are now ready to have
your prototypes fabricated.
Harris provides prototype devices to you so that the correct
functionality of your custom controller can be verified in
your system. The use of prototypes in the prototype mode in
conjunction with an expansion IC will facilitate your hardware verification and final in system revisions to your software when necessary.
The process of implementing changes in the software can
be supported in either of two ways. If a code development
system is unavailable, this is done on a breadboard and the
on-chip ROM is functionally replaced by an external
EPROM as illustrated in Figure 6. In the other case, the
code development system is used as an in-circuit emulator.
Figure 1 would illustrate this use of the prototype if the incircuit emulation breadboard were plugged into the ASIC

trademark of Hams Corporation

4-6

prototype socket on the EZ -Pro pod. In either case, you can
drive the core macrocell in your prototype from off chip
allowing revisions to your software. The difference is that
you must reload the new firmware in EPROM in the first
case, whereas, in the second it is downloaded to RAM in the
code development system pod from which the core
macrocell is then driven.

UH68HC05

~~~~g~
CONTROLLER

At the successful conclusion of in system verification of
your prototypes, your design is finally ready to go to
production.

'" CONTROL

F~~A~H~~__~i
:1 AlJD

EXPANSION
IC

AL

t--l/o

cs

L -____.IAH

'--_______1 D

EPROM

Taking The Next Step
To get started with your design, contact your local Harris
Sales Office. We're confident that no matter which option
you select, Harris' custom core design methodology
assures you of receiving proprietary parts of the highest
quality in a timely manner. The resulting devices will
enhance your product's competitive position in many ways,
contributing to the overall success of your efforts.

CS = CONTROL
D DATA
AH = HIGH ORDER ADDRESS BYTE
AL = LOW ORDER ADDRESS BYTE

=

FIGURE 6. IN-CIRCUIT EMULATION BREADBOARD
UTILIZING CUSTOM UH68HC05 CORE
MICRO PROTOTYPE

~
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8-BIT BUS PERIPHERALS
PAGE
CDP6402
CDP6402C

CMOS Universal Asynchronous Receiver/Transmitter (UART). . . . . . . . . . . . . . . . . . ..

5-3

CDP65C51

CMOS Asynchronous Communications Interface Adapter (ACIA) . . . . . . . . . . . . . . . ..

5-11

CDP6818

CMOS Real-Time Clock With RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-29

CDP6818A

CMOS Real-Time Clock Plus RAM .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-48

CDP6823

CMOS Parallel Interface. ....................................................

5-67

CDP6853

CMOS Asynchronous Communications Interface Adapter (ACIA) . . . . . . . . . . . . . . . ..
with MOTEL Bus

5-81

en

en...!

::I~

=
...
.... :c

-D.,

=Ia::
......
D.,

5-1

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CDP6402
CDP6402C

mlHARRIS

CMOS Universal Asynchronous
Receiver/Transmitter (UART)

January 1991

Features

Pinout

• Low Power CMOS Circuitry ...... 7.5mW Typ at 3.2MHz (Max. Freq.) at VDD = SV
• Baud Rate .. DC to 200K Bitsls (Max) at ..•...•.••.••.••.••.•...•... 5V, +S5 0 C
.. DC to 400K Bitsls (Max) at ............•...•...••..... 10V, +S5 0 C
• 4V to 10.5 Operation
• Automatic Data Formatting and Status Generation
• Fully Programmable With Externally Selectable Word Length (5-S Bits), Parity
Inhibit, EvenlOdd Parity and 1,1.5 or 2 Stop Bits
• Operating Temperature Ranges
.. CDP6402D, CD ..........•...........................•..... -55 0 C to +125 0 C
.. CDP6402E, CE ......................................•...... -400 C to +85 0 C
• Replaces Industry Types IM6402 and HD6402

Description

PACKAGE TYPES D AND E

TOP VIEW
Voo

,p,

NC
GNO

ClSI
ClS2

RRO
R8RB
RBR7
R8R6

S8S
PI

eRL
TBRS
TSR7
TeR6
TBR5
TBR4
TBR3
T8R2

RaR5
RBR4
R8R3
RBR2

p,

RBR I
FE

0'
SFO

TBRI

TRO
TR'

RRC

The CDP6402 and CDP6402C are silicon gate CMOS Universal Asynchronous Receiverl
Transmitter (UART) circuits for interfacing computers or microprocessors to
asynchronous serial data channels. They are designed to provide the necessary
formatting and control for interfacing between serial and parallel data channels. The
receiver converts serial start, data, parity, and stop bits to parallel data verifying proper
code transmission, parity and stop bits. The transmitter converts parallel data into serial
form and automatically adds start parity and stop bits.

ORR

TBRL
TBRE

OR
RRI

MR

The data word can be 5, 6, 7 or 8 bits in length. Parity may be odd, even or inhibited. Stop
bits can be 1, 1.5 or 2 (when transmitting 5 bit code).

Block Diagram
rn
rn ....

:::I~

TRE_r--------,

.... :

IlCIw

-II..
1lCI_

,=
""w
II..

Tlffi ~ TRA;,~~~;ER
TRC-

II

AND

CONTROL

I

~------------~~·TRO

I

I

CLSI--L---t---------+---------~--~~--~----------------------------------------------~I--sBS
CLS2--L----+---------+----------~

~-----------------------------------------------~I-EPE

I

CRL--r---t-------·--t---------~___r_--~-------

I
I

MR

PI

I
I

r---------------------~_+__+_RRI

I

RRC

I

I

r---------.;-RRD

SFD·-

DR

Copyright

OE

TBRE

FE

PE

RSRB f MSB)

© Harris Corporation 1991

RBRI(LSB)

File Number

5-3

1328.1

CDP640ZCDP6402C
The COP6402 and COP6402C can be used in a wide range
of applications including modems, printers, peripherals,
video terminals, remote data acquisition systems, and serial
data links for distributed processing systems.

operating voltage range of 4 to 10.5 volts, and the COP6402C
has a recommended operating voltage range of 4 to 6.5
volts. Both types are supplied in 40-lead dual-in-line ceramic
packages (0 suffix), and 40-lead dual-in-line plastic
packages (E suffix).

The COP6402 and COP6402C are functionally identical.
They differ in that the COP6402 has a recommended

MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VOO)
(Voltage referenced to VSS Terminal)
COP6402 ....................................................................................... -0.5 to +11 V
COP6402C.: ..................................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE,. ALL INPUTS ........................................................ -0.5 to VOO +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................. ± 100 I1A
POWER DISSIPATION PER PACKAGE (PO):
For T A = -40 to +60° C (PACKAGE TYPE E .............................................................. 500 mW
For T A = +60 to +85°C (PACKAGE TYPE E) ............................... Derate Lineary at 12 mW/o C to 200 mW
For T A = -55 to 100° C (PACKAGE TYPE D) ............................................................. 500 mW
For T A = + 100 to +125° C (PACKAGE TYPE D) ............................ Derate Lineary at 12 mW/o C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................. 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 .............................................................................. -55 to +125°C
PACKAGE TYPE E ................................................................................-40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) .......................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ..................................... +265°C

OPERATING CONDITIONS at TA = Full Package-Temperature Range. For maximum reliability, operating conditions
should be selected so that operation Is always within the following ranges:
LIMITS
CHARACTERISTIC

CDP6402C
Min.
Max.
4
6.5
VSS
VOO

CDP6402
Min.
4
VSS

DC Operating Voltage Range
Input Voltage Range

Max.
10.5
VOO

UNITS
V

STATIC ELECTRICAL CHARACTERISTICS at TA=-40 to +85°C, VDD ±10%, Except as noted
CONDITIONS
CHARACTERISTIC
Quiescent Device
Current
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage
Low-Level
Output Voltage
High Level
Input Low
Voltage
Input Hlgn
Voltage
Input Leakage
Current
3-State Output Leakage
Current

rv~
10D

-

IOH

0.4
0.5
4.6
9.5

VOLt

-

IOl

VOHt
Vil
V~

1m

Operating Current,

lOUT
IOD1t

Input Capacitance
Output Capacitance

CIN
COUT

0.5,4.5
0.5,9.5
0.5,4.5
0.5 9.5
Any
Input
0,5
0, 10

-

-

~~~

0,5
0, 10
0,5
0, 10
0,5
0, 10
0,5
0, 10
0,5
0, 10

-

-

0,5
0, 10
0,5
0, 10
0,5
o 10

-

-

~~?
5
10
5
10
5
10
5
10

LIMITS
CDP6402C
CDP6402
Typ.Max.
Min.
Typ.Min.
0.Q1
0.02
50
1
200
2
4
1.2
2.4
5
7
-0.55
-1.1
-0.55
-1.1
-1.3
-2.6
0
0.1
0
0.1
0

-

-

-

5

4. !:I

5

10
5
10
5
10
5
10
5
10

9.9

10

5
10

-

-

-

VOD-2
7

-

-

-

±10-'1
±10-4
±10-'1
±10-4

4.11

~:8
0. 2VOO

-

±1
±2
±1
±10

1.5

10
5
10

7.5
15

-

VOD-2

-

-

-

5
-

±10-'1

1.5
5
10

UNITS
Max.
200

-

-

-

I1A

mA

0.1

-

U.1i

V

±1

±1

I1A

-

-

mA

7.5
15

pF

-Typical values are for T A=25°C and nominal VOD.
tlOL =IOH=111A.
ilOperating current is measured at 200 kHz or VDD = 5 V and 400 kHz for VDD = 10 V, with open outputs (worst-case
frequencies for COP1802A system operating at maximum speed of 3.2 MHz).
5-4

CDP640~CDP6402C
DESCRIPTION OF OPERATION

Receiver Operation
Data is received in serial form at the RRI input. When no
data is being received, RRI input must remain high. The
data is clocked through the RRC. The clock rate is 16 times
the data rate. Receiver timing is shown in Fig. 4.

Initialization and Controls
A positive pulse on the MASTER RESET (MR) input resets
the control, status, and receiver buffer registers, and sets
the serial output (TRO) High. Timing is generated from the
clock inputs RRC and TRC at a frequency equal to 16 times
the serial data bit rate. The RRC and TRC inputs may be
driven by a common clock, or may be driven independentiy
by two different clocks. The CONTROL REGISTER LOAD
(CRL) input is strobed to load control bits for PARITY
INHIBIT (PI), EVEN PARITY ENABLE (EPE), STOP BIT
SELECTS (SBS), and CHARACTER LENGTH SELECTS
(CLS1 and CLS2). These inputs may be hand wired to VSS
or VDD with CRL to VDD. When the initialization is
completed, the UART is ready for receiverandlor transmitter
operations.

BEGINNING OF ARST STOP BIT·
RRI

I

I I

}J
DR

I

-

FE ,PE
A

The transmitter section accepts parallel data, formats it,
and transmits it in serial form (Fig. 2) on the TRO terminal.

START BIT

I

ILSBI

IMSBI

CYCLE

92CS-54!S!59R2

~

X=LLL

*IF ENABLED

to-- 112CLOC K

C

Fig. 4 - Receiver timing waveforms.

I,H/2DR 2 STOP BITS

i\ 'I- - - - - - ' - 1 - - - - - - .1

-~L~~KT~y~~:S

RBRI-8 ,DE

Transmitter Operation

5-8 DATA BITS

~

DATA

PARITY
92CS-34554

Fig. 2 - Serial data formal.
Transmittertiming is shown in Fig. 3. (A) Data is loaded into
the transmitter buffer register from the inputs TBR1 through
TBR8 by a logic low on the TBRL input. Valid data must be
present at least tOT prior to, and tTD following, the rising
edge of TBRL. If words less than 8 bits are used, only the
least significant biis are used. The character is right
justified into the least significant bit, TBR1. (B) The rising
edge of TBRL clears IBRE. V, to 1V, cycles later, depending
on when the TBRL pulse occurs with respect to TRC, data is
transferred to the transmitter register and TRE is cleared.
TBRE is set to a logic High one cycle after that.

(A) A low level on B"RR clears the DR line. (B) During the
first stop bit data is transferred from the receiver register to
the RBRegister. If the word is less than 8 bits, the unused
most significant bits will be a logic low. The output
character is right justified to the least significant bit RBR1. A
logic high on OE indicates overruns. An overrun occurs
when DR has not been cleared before the present character
was transferred to the RBR. (C) 1/2 clock cycle later DR is
set to a logic high and FE is evaluated. A logic high on FE.
indicates an invalid stop bit was received. A logic high on
PE indicates a parity error.
Start Bit Detection
The receiver uses a 16X clock for timing (Fig. 5). The start
bit could have occurred as much as one clock cycle before it
was detected, as indicated by the shaded portion. The
center of the start bit is defined as clock count 71/2. If the
receiver clock is a symmetrical square wave, the center of
the start bit will be located within ±1/2clock cycle, ±1/32 bit
or ±3.125%. The receiver begins searching for the next start
bit at 9 clocks into the first stop bit.

Output data is clocked by TRC. The clock rate is 16 times
the data rate. (C) A second pulse on TBRL loads data into
the transmitter buffer register. Data transfer to the
transmitter register is delayed until transmission of the
current character is complete. (D) Data is automatically
transferred to the transmitter register and transmission of
that character begins.

COUNT 71/2
DEFINED CENTER
OF START BIT

CLOCK

RRI INPUT-m

I.. I...

START

112CLOC~

7 CYCLES
8 1/2 CLOCK
CYCLES

92CS- 34558

Fig. 5 - Start bit timing waveforms.

92CS-38054R1

Fig. 3 - Transmitter timing waveforms.

5-5

rn
rn .....

=...
...=-...
::::Jill!

....
:c
-Q,.
'1:1:
Q,.

CDP640~CDP6402C
Table I - Control Word Function
C( INTRnl

CLS2
L
L
L
L
L
L
L
L
L
L
L
L

CLS1
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H

wn~

n

PI
L
L
L
L
H
H
L
L
L
L

EPE
L
L
H

SBS
L
H
L

H

H
H
L
L
L
L
H
H
L
L
L
L
H
H

X
X

H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

X
X
L
L
H
H

L
L
H
H

X
X
L
L
H
H

X
X

DATA BITS
5
5
5
5
5
5

6
6
6
6
6
6
7
7
7
7
7
7
8
8
8
8
8
8

PARITY BIT
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED

STOP BITtS\
1
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2

X = Don't Care

Table II - Function Pin Definition
PIN
1
2

3
4

5

6
7

8
9
10
11
12
13

14

SYMBOL
DESCRIPTION
Positive Power Supply
VDD
N/C
No Connection
GND
Ground (VSS)
RRD
A high level on RECEIVER REGISTER
DISABLE forces the receiver holding
register ouputs RBR1-RBR8 to a high
impedance state.
The contents of the RECEIVER BUFFER
RBR8
REGISTER appear on these three-state
outputs. Word formats less than 8
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE

FE

r:':

~i:h:~~:'fi'd RBR1
to

A high level on PARITY ERROR
indicates that the received parity does
not match parity programmed by control
bits. The output is active until parity
matches on a succeeding character.
When parity is inhibited, this output
is low.
A high level on FRAMING ERROR
indicates the 'first stop bit was invalid.
FE will stay active until the next valid
character's stop bit is received.

5-6

PIN

SYMBOL

DESCRIPTION

15

DE

16

SFD

17

RRC

18

DRR

19

DR

20

RRI

21

MR

22

TBRE

A high level on OVERRUN ERROR
indicates the data received flag was not
cleared before the last character was
transferred to the receiver buffer
register. The Error is reset at the next
character's stop bit if DRR has been
performed (i.e., DRR; active low).
A high level on STATUS FLAGS
DISABLE forces the outputs PE, FE, DE,
DR, TBRE to a high impedance state.
The RECEIVER REGISTER CLOCK is
16X' the receiver data rate.
A low level on DATA RECEIVED RESET
clears the data received output (DR), to
a low level.
A high level on DATA RECEIVED
indicates a character has been received
and transferred to the receiver buffer
register.
Serial data on RECEIVER REGISTER
INPUT is clocked into the receiver
register.
A high level on MASTER RESET (MR)
clears PE, FE, DE and DR, and sets TRE,
TBRE, and TRO. TRE is actually set on
the first rising edge of TRC after MR
goes high. MR should be strobed after
power-up.
A high level on TRANSMITTER BUFFER
REGISTER EMPTY indicates the
transmitter buffer register has
transferred its data to the transmitter
register and is ready for new data.

CDP640~CDP6402C
Table II • Function Pin Definition (Cont'd)
PIN
23

24

25

26

27
28
29
30
31
32
33

SYMBOL
DESCRIPTION
TBRL
A low level on TRANSMITTER BUFFER
REGISTER LOAD transfers data from
inputs TBR1-TBR8 into the transmitter
buffer register. A low to high transition
on TBRL requests data transfer to the
transmitter register. If the transmitter
register is busy, transfer is automatically
delayed so that the two characters are
transmitted end to end.
TRE
A high level on TRANSMITTER
REGISTER EMPTY indicates completed
transmission of a character including
stop bits.
TRO
Character data, start data and stop bits
appear serially at the TRANSMITTER
REGISTER OUTPUT.
TBR1
Character data is loaded into the
TRANSMITTER BUFFER REGISTER via
inputs TBR1-TBR8. For character
formats less than 8-bits, the TBR8, 7,
and 6 Inputs are ignored corresponding
to the programmed word length.
TBR2
TBR3
TBR4
TBR5
See Pin 26 - TBR1
TBR6
TBR7
TBR8

PIN
34
35

36

37

38
39

40

SYMBOL
DESCRIPTION
CRL
A high level on CONTROL REGISTER
LOAD loads the control register.
PI'
A high level on PARITY INHIBIT inhibits
parity generation, parity checking and
forces PE output low.
SBS'
A high level on STOP BIT SELECT
selects 1.5 stop bits for a 5 character
format and 2 stop bits for other lengths.
CLS2'
These inputs program the CHARACTER
LENGTH SELECTED. (CLS1 low CLS2
low 5-bits) (CLS 1 high CLS210w 6-bits)
(CLS110w CLS2 high 7-bits) (CLS1 high
CLS2 high 8-bits).
CLS1' See Pin 37 - CLS2
EPE'
When PI is low, a high level on EVEN
PARITY ENABLE generates and checks
even parity. A low level selects odd
parity.
TRC
The TRANSMITTER REGISTER
CLOCK is 16X the transmit data rate.

'See Table I (Control Word Function)

}

5-7

CDP6402, CDP6402C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
VIH

=-40 to +85°C, VDD ± 5%, tr, tf =20 ns,

= 0.7 VDD, VIL = 0.3 VDD, CL = 100 pF
LIMITS
CDP6402C

CDP6402
CHARACTERISTIC

t

VDD
(V)

Typ.-

I

Max. A

Typ.-

I

Max. A

UNITS

System Timing (See Fig 6)
Minimum Pulse Width:
CRl

5
10

50
40

150
100

50

150

tCRl

Minimum Setup Time
Control Word to CRl

5
10

20
0

50
40

20

50

tcwc

Minimum Hold Time
Control Word after CRl

5
10

40
20

60
30

40

60

tccw

-

-

Propagation Delay Time
SFD High to SOD

5
10

130
100

200
150

130

200

tSFDH

5
10

130
40

200
60

130

-

-

-

-

-

ns

200

SFD low to SOD

tSFDl

RRD High to Receiver Register
High Impedance

5
10

80
40

150
70

80

tRRDH

-

-

RRD Low to Receiver Register
Active

5
10

80
40

150
70

80

150

tRRDl

5
10

200
100

400
200

200

400

-

-

Minimum Pulse Width:

MA

-

-

-

150

-

-Typical values for T A = 25° C and nominal VDD.
AMaximum limits of minimum characteristics are the values above which aI/ devices function.

t All measurements are made at the 50% point of the transition except tri-state measurements.
CONTROL INPUT WORD TIMING

---=-------""""'1,...---BYTE

CONTROL WORD - - - "..- - - . . , . -__.........__
INPUT
CONTROL WORD

I---------'CWC
CRL

"'1"

tccw

I,...--------'"'\~------

~I

--------{If.-o.......

- - - - , C R L - - - - - <..

STATUS OUTPUT TIMING

1§90%

7()%~

-=========~_;_--------=-:-~

OUTPUTS_
STATUS

'SFDH--!

10%

~%

'SFDL

SFD _ _ _ _ _ _ _~~~------~n~-----~

RECEIVER REGI'HER DISCONNECT TIMING

R BUS 0 _--.,...-~90"l0
R BUS 7
'RRDH RRO _ _ _ _ _

I

70"10*

-

10%
I
~ 30%
'RROe
~rl--~---------------ftR----~~--------9lCM - 38055

Fig. 6 - System timing waveforms.

5-8

CDP640ZCDP6402C
OYNAMIC ELECTRICAL CHARACTERISTICS al TA
VIH =0.7 Voo, VIL =0.3 VOD, CL =100 pF

=-4010 +85

0

C, VOO ± 5%, Ir, If

=20 ns,

LIMITS
CHARACTERISTIC

CDP6402

t

Transmitter Tlmmg (See Fig 7)

Minimum Clock Period (TRC)

tcc

Minimum Pulse Width:
Clock low level

tCl

~~

TYP. -

I
1 Max.~l

5
10

250
125

5
10

CDP6402C
Typ.-l

Max.~

310
155

250

310

100
75

125
100

100

125

-

125

-

-

Clock High level

tCH

5
10

100
75

125
100

100

"'fi3R'[

tTHTH

5
10

80
40

200
100

80

5
10

175
90

275
150

175
-

275
-

5
10

20
0

50
40

20
-

50
60

Minimum Setup Time:
TBRl to Clock
Data to TBRl

tTHC

J.

tOT

--

-

200

--

-

Minimum Hold Time:
Data after TBRl

5
10

40
20

60
30

40

tTD

Propagation Delay Time:
Clock to Data Start Bit

5
10

300
150

450
225

300
--

450

tCD

_.

-

--

tCT

5
10

330
100

400
150

330
-

400

TBRl to TBRE

tTTHR

5
10

200
100

300
150

200

300

--

-

Clock to TRE

tTTS

5
10

330
100

400
150

330
-

400

--

--

-Typical values for T A = 25 C and nominal VDD.

t All measurements are made at the 50% point of the transition except tri-state measurements.

** TRANSMITTER
SHIFT
REGISTER LOADED

I

I

j.j-

'i'BRI~

I

I

I
I I
I I
I I
III
i1o--tCD
II

U

1-1
TRO
I
I
TBRE

tTTH~
I
I
I
I
I

TRE

T BUS 0T BUS7

I
I
I

11

~-1l--tCT

-U

X

If THE HOLDING REGISTER IS LOADED ON THE TRAILING EDGE OF
If If

J---tCD
/ I ST DATA BIT

11

~TTS
I

:E;.t DT-t-tTDj
DATA

I
I

--I

Ii

TmIT.

~

92CM-34556

mVKR~~~~~T6&~~~'I.i L~~~n~Rc'[lcl~tJl~fo~O:~~~c0MHE~F+~~T ~~~~LI1~-~~\H'6AnM/f1'?6 THE
TRANSMISSION OF A START BIT OCCURS 112 CLOCK PERIOD

+ tCD

LATER

Fig. 7 - Transmitter timing waveforms.

5-9

=...
=1=
"'w
I-::C

II-

~Maximum limits of minimum characteristics are the values above which all devices function.

TRC

'"....
"'
::I~
-II-

0

TRANSMITTER BUFFER
REGISTER LOADED

ns

---

Clock to TBRE

*

UNITS

CDP6402,CDP6402C
DYNAMIC ELECTRICAL CHARACTERISTICS al TA = -4010 +850 C, VDD ± 5%, Ir, If = 20 ns,
VIH

=0.7 VDD, VIL =0.3 VDD, CL =100 pF
LIN ITS
CHARACTERISTIC

CDP6402

t

~~p

Receiver Timing (58e Fig...!!.
Minimum Clock Period (RRC)

Max. d

TVD.-

M..".d

250

310

1?1;

11;1;

250

310

100
75
100

125
100
125

100

125

100

125

50

75

21;

4n

100
50

150
75

100

150

tDDA

5
10

150
75

250
125

150

250

tCDV

5
10

275
110

400
175

275

400

tCDA

5
10
5
10
5
10
5
10

275
110
275
100
240
120
200
100

400
175
400
150
375
175
300
150

275

400

!GJ.

Clock High Level

tCH

DATA RECEIVED RESET

too

Clock to Data Valid

UNITS

TVD.-

5
10
5
10
5
10
5
_10
5
10

tcc

Minimum Pulse Width:
Clock Low Level

Minimum Setup Time:
Data Start Bit to Clock
I proea~ation ue a:l Ime:
DATA RECEIVED RESET to
Data Received

CDP6402C

tDe

Clock to DR
Clock to Overrun Error

tCOE

Clock to Parity Error

tCPE

Clock to Framing Error

tCFE

71;

-

-

1nn

50

75

-

-

-

-

-

-

275
240
200
-

375
300
-

400

-TYPical values for T A = 25 0 C and nominal VDD .
.ll.Maxlmum limits of minimum chara~terlstics are the values above which all devices function.
tAli measurements are made at.the 50% point of the transition except tri-state measurements.

j,..h 'CC

CLOCK 71/2
SAMPLE
\.

'CH i-+1-'CL

.

CLOCK 71/2 LOAD
HOLDING REGISTER

RRC~1l

--J i--tDC*

RRI

R
R

START BIT

PARITY

BUSO----------------------------------------------------rt-~~F"
7

BUS

DR--------------y---------------------------------t1-r-----j

I-tDDA
DmR------------4------------;r------------------------rt------

I--- DD----l
t

OE**--------------------------------------~--------~L----PE------------------------------------------------~--~--

FE------------------------------------------------~~~--

*

**

92CM-34555

IF A START BIT OCCURS AT A TIME LESS THAN tDC BEFORE A HIGH-TO-LOWTRANSITION
OF THE CLOCK, THE START BIT MAY NOT BE RECOGNIZED UNTIL THE NEXT HIGH-TOLOW TRANSITION OFTHE CLOCK. THE $TART BIT MAY BE COMPLETELY ASYNCHRONOUS
WITH THE CLOCK.

IF A PENDING DA·HAS NOT BEEN CLEARED 8Y A READ OF THE RECEIVER HOLDING
REGISTER BY THE TIME A NEW WORD IS LOADED INTO THE RECEIVER HOLDING
REGISTER, THE OE SIGNAL WILL COME TRUE.

Fig. 8 - Receiver timing waveforms.

5-10

ns

CDP65C51
CDP65C51A

mHARRIS
January 1991

CMOS Asynchronous Communications
Interface Adapter {ACIA}

Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Pinout

Compatible With 8-Bit Microprocessors
Full Duplex Operation With Buffered Receiver and Transr.,itter
Data Set/Modem Control Functions
Internal Baud Rate Generator With 15 Programmable Baud Rates
(50 to 19,200)
Program Selectable Internally or Externally Controlled Receiver
Rate
Operates at Baud Rates Up To 250,000 Via Proper Crystal or Clock
Selection
Programmable Word Lengths, Number of Stop Bits and Parity Bit
Generation and Detection
Programmable Interrupt Control
Program Reset
Program Selectable Serial Echo Mode
Two Chip Selects
4MHz, 2MHz or 1MHz Operation (CDP65C51 and CDP65C51A-4,
-2, -1 Types, Respectively)
Single 3V to 6V Power Supply
Full TTL Compatibility
Synchronous CTS Operation

PACKAGE TYPES D, E AND M
TOP VIEW
vss
eso

28

R/W
+2

RES

4

27
26
25

Rx C
XTLI
XTL

~

24

6

23

D6
05

CSI

!l!ll
D7

7

22

D4

8
9

21
20

TXO
OTR

10

19

D3
02
Dl

II

III

DO

RXO
RSO
RSI

12
13
14

17
16

DSlf
DCD

ffi
C'fll

I~

VOO

TOP VIEW

Description
The CDP65C51 and CDP65C51A Asynchronous Communications Interface Adapters (ACiA) provide an easily
implemented, program controlled interface between 8-bit
microprocessor based systems and serial communication
data sets and modems. The CDP65C51A is identical to the
CDP65C51 except for the implementation of the CTS function. If a not-clear-to-send signal is received during the
transmission of a character, the CDP65C51A will first allow
completion of that transmission, and then disable the
transmitter.
The CDP65C51 and CDP65C51A have an internal baud
rate generator. This feature eliminates the need for multiple
component support circuits, a crystal being the only other
part required. The Transmitter baud rate can be selected
under program control to be either 1 of 15 different rates
from 50 to 19,200 baud, or 1/16 times an external clock
rate. The receiver baud rate may be selected under program
control to be either the transmitter rate, or at 1/16 times an
external clock rate. The CDP65C51 and CDP65C51A have
programmable word lengths of 5, 6, 7 or 8 bits; even, odd or
no parity; 1, 1Y2 or 2 stop bits.
The CDP65C51 and CDP65C51A are designed for maximum programmed control from the CPU, to simplify
hardware implementation. Three separate registers permit

Copyright

©

the CPU to easily select the CDP65C51A operating modes
and data-checking parameters and determine operational
status.

rn
rn ....

=...
=......
:::Iii!!

..... ::c

The Command Register controls parity, reciever echo
mode, transmitter interrupt control, the state of the RTS line,
receiver interrupt control, and the state of the DTR line.
The Control Register controls the number of stop bits,
word length, receiver clock source and baud rate.
The Status Register indicates the states of the IRQ, DSR
and DCD lines, transmitter and receiver data registers, and
overrun, framing and parity error conditions.
The transmitter and receiver data registers are used for temporary data storage by the CDP65C51A transmit and receive circuits.
The CDP65C51 and CDP65C51A-1, -2 and -4 types are
capable of interfacing with microprocessors with cycle
times of 1 MHz, 2MHz and 4MHz, respectively.
The CDP65C51 and CDP65C51A are supplied in 28 lead
hermetic dual-in-line sidebrazed ceramic packages (D suffix), in 28 lead dual-in-line plastic packages (E suffix) and in
28 lead dual-in-line small outline (SO) packages (M) suffix.

Harris Corporation 1991

File Number
5-11

2747

-0..
ICC
0..

CDP65C57,CDP65C57A
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to Vss terminal) •..........•..•...•....••.....................•........••...•....... -0.5 to +7 V
INPUT VOLTAGE RANGE,ALL INPUTS ......................................................•.... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ..................•...........................•.............•..•...• ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +6O"C (PACKAGE TYPE E) •..•..........•.....................•.......•.......•.•...•.•• 500 mW
ForTA = +SO to +85°C (PACKAGE TYPE E) ..•...•...••..................... Derate Linearly at 8 mW/oC to 300 mW
For T A= -55 to +100° C (PACKAGE TYPE D) .•..••............•..................•...•.................•. 500 mW
For TA +100 to +125°C (PACKAGE TYPE D) ............................... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +85°C (PACKAGE TYPE M)* •.....•...•.........................••..•...................• 425 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 ....••..•....•...•........•....•............•.....•..•......................... -55 to +125°C
PACKAGE TYPE E and M ..••...••..•.............••...•........................................... -40 to +85° C
STORAGE-TEMPERATURE RANGE (Tstg) ......................••...•...•................•....•...••.. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s maximum ..••...............••....•.......... +265°C
• Printed.circuit board mount: 57 mm x 57 mm minimum area x 1.6 mm thick G10 epoxy glass: or equivaleni.

=

-RECOMMENDED OPERATING CONDITIONS al TA = -40° 10+85°C
For maximum rellablllly, nominal operallng condHlons should be selecled so Ihal operallon Is always
within Ihe following ranges:
LIMITS
Min.
Max.
3
6
Vss
Voo

CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range

UNITS
V

STATIC ELECTRICAL CHARACTERISTICS al TA = -40° 10+85°C, Voo = 5V ± 5%
CHARACTERISTIC

-

LIMITS
Typ.
50

Max.
200

1.6

-

-

mA

-1.6

-

-

mA

-

-

0.4

V

4.6

-

-

V

0.8

V

-

Voo
Voo

V

±1

pA

-

±1.2
2
10
10

pA
pA
pF
pF

Min.

Quiescent Device Current
Output Low Current (Sinking): VOL =0.4 V
(00-07, TxD, RxC, RTS, DTR, IRQ
Output High Current (Sourcing): VOH =4.6 V
(00-07, TxD, RxC, RTS, DTR)
Output Low Voltage: ILOAO =1.6 mA
(00-07, TxD, RxC, RTS, DTR, IRQ)
Output High Voltage: ILOAO =-1.6 mA
(DO-D7,TxD,RxC,~,DTR)
Input Low Voltage
Input High Voltage
(Except XTLI and XTLO)
(XTLI and XTLO)
Input Leakage Current: V,N =0 to 5 V
(1/>2, RIW, RES, CSO, CS1, RSO, RS1, CTS, RxD, DCD, DSR)
Input Leakage Current for High Impedance State (00-07)
Output Leakage Current (off state): VOUT - 5 V (TRQ)
Input Capacitance (except XTLI and XTLO)
Output Capacitance

5-12

100
10L
10H
VOL
VOH
V,L
V,H

Vss
2
3

liN
iTsl

IOFF
C 'N
COUT

-

-

-

UNITS
pA

CDP65C51,CDP65C51A
CDP65C51/51A INTERFACE REQUIREMENTS

This Is a description of the interface requirements for the
CDP65C51 and CDP65C51A. Fig. 1 Is the Interface Diagram
and the Terminal Diagram shows the pinout configuration for
the CDP65C51A.

00-07 (Data Bus) (18-25)
The DO-D7 pins are the eight data lines used to transfer data
between the processor and the CDP65C51/51A. These lines
are bidirectional and are normally high impedance-exceptduring Read cycles when the CDP65C51/51A are selected.
CSO, CSl (Chip Selects) (2, 3)

00·07

The two chip select inputs are normally connected to the processor address lines either directly or through decoders. The
CDP65C51/51A are selected when CSO is high and CS1 is
low.

TxO

RSO, RSl (Register Selects) (13, 14)
The two register select lines are normally connected to the processor address lines to allow the processor to select the various CDP65C51/51A Internal registers. The following table
shows the Internal rel1ister select coding.

RxC
XTLI
XTLO

110
CONTROL

TABLE I
RSl

RSO

0

0

0

1

1
1

0

RxO

1

Read
Write
Transmit Data
Receiver Data
Register
Register
Programmed Reset
Status Register
(Data is "Don't
Care")
Command Register
Control Register

Only the Command and Control registers are read/write.
The Programmed Reset operation does not cause any data
transfer, but is used to clear bits 4 through 0 in the
Command Register and bit 2 in the Status Register. The
Control Register is unchanged by a Programmed Reset. It
should be noted that the Programmed Reset is slightly
different from the Hardware Reset (RES); these differences
are shown in Figs. 3, 4 and 5.

92CM-36860

Fig. 1 - CDP65C51/51A interface diagram

MICROPROCESSOR INTERFACE
SIGNAL DESCRIPTION
RES (Reset) (4)
During system initialization a low on the RES input will
cause a hardware reset to occur. The Command Register
and the Control Register will be cleared. The Status
Register will be cleared with the exception of the indications
of Data Set Ready and Data Carrier Detect, which are
externally controlled by the DSR and iX:D lines, and the
transmitter Empty bit, which will be set. A hardware reset is
required after power-up.
f/)2 (Input Clock) (27)

The input clock is the system f/)2 clock and is used to clock
all data transfers between the system microprocessor and
the CDP65C51/51A.
R/W (ReadlWrite) (28)
The R/W input, generated by the microprocessor, is used to
control the direction of data transfers. A high on the R/W pin
allows the processor to read the data' supplied by the
CDP65C51/51A, a low allows a write to the CDP65C51/51A.

"..

tn~

=B

1-::1

=.....

-a
I

II

a

ACIAIMODEM INTERFACE
SIGNAL DESCRIPTION
XTLI, XTLO (Crystal Pins) (6, 7)
These pins are normally directly connected to the external
crystal (1.8432 MHz) used to derive the various baud rates
(see "Generation of Non-Standard Baud Rates"). Alternatively, an externally generated clock may be used to drive
the XTLI pin, in which case the XTLO pin must float. XTLI is
the input pin for the transmit clock.
TxD (Transmit Data) (10)
The TxD output line is used' to transfer serial NRZ
(nonreturn-to-zero) data to the modem. The LSB (least
significant bit) of the Transmit Data Register is the first data
bit transmitted and the rate of data transmission is
determined by the baud rate selected or under control of an
external clock. This selection is made by programming the
Control Register.

IRQ (Interrupt Request) (26)

RxD (Receive Data) (12)

The IRQ pin is an interrupt output from the interrupt control
logiC. It is an open drain output,~mitting several devices
to be connected to the common TRO' microprocessor input.
Normally at high level, IRQ goes low when an interrupt
occurs.

The RxD input line is used to transfer serial NRZ data into
the ACIA from the modem, LSB first. The receiver data rate
is either the programmed baud rate or under the control of
an externally generated receiver clock. The selection is
made by programming the Control Register.

5-13

CDP65C51,CDP65C51A
CDP65C51/51A INTERFACE REQUIREMENTS (Cont'd)

RxC (Receive Clock) (5)

DTR (Data Terminal Ready) (11)

The RxC is a bidirectional pin which serves as either the
receiver 16X clock input or the receiver 16X clock output.
The latter mode results if the internal baud-rate generator is
selected for receiver data clocking.

This output pin is used to indicate the status of the CDP65C51/
51A to the modem. A low on DTR indicates the CDP65C51/
51A is enabled, a high indicates it is disabled. The processor
controls this pin via bit 0 of the Command Register.
DSR (Data Set Ready) (17)

RTS (Request to Send) (8)
The RTS output pin is used to control the modem from the
processor. The state of the RTS pin is determined by the
contents of the Command Register.

The DSR Input pin is used to indicate to the CDP65C51/51A
the status of the modem. A low indicates the "ready" state and
a high, "not ready".
DCD (Data Carrier Detect) (16)

CTi (Clear to Send) (9)
The CTS input pin is

used to control the transmitter
operation. The enable state is with CTS low. The transmitter
is automatically disabled if CTS is high.

The DCD input pin is used to indicate to the CDP65C51/51A
the status of the carrier detect output of the modem. A low indicates that the modem carrier signal is present and a high, that it
is not.

CDP65C51 AND CDP65C51A INTERNAL ORGANIZAnON
This is a functional description ofthe CDP65C51/51A. A block
diagram of the CDP65C51/51A is presented in Fig. 2.
DATA BUS BUFFERS
The Data Bus Buffer interfaces the system data lines to the internal data bus. The Data Bus Buffer is bi-directional. When the
R/W line Is high an the chip is selected, the Data Bus Buffer
passes the Data to the system data lines from the CDP65C51/
51A internal data bus. When the R/Wline is low and the chip is
selected, the Data Bus Buffer writes the data from the system
data bus to the intem"al data bus.
INTERRUPT LOGIC
The Interrupt Logic will cause the IRQ line to the
microprocessor to go low when conditions are met that

can cause an interrupt will set bit7 and the appropriate bit of
bits 3 through 6 in the Status Register if enabled. Bits5 and6
correspond to the Data Carrier Detect (DCD) logiC and the
Data Set Ready (DSR) logic. Bits 3 and 4 correspond to the
Receiver Data Registerfull and the Transmitter Data Register
empty conditions. These conditions can cause an interrupt
request if enabled by the Command Register.
I/O CONTROL
The 1/0 Control Logic controls the selection of internal
registers in preparation for a data transfer on the internal
data bus and the direction of the transfer to or from the
register.
The registers are selected by the Register Select and Chip
Select and Read/Write iines as described in Table I,
previously.

DO-D7

TxD

DcD
DSR

RxC
XTLI
XTLO

DTR

iffi
RxD

Fig. 2 - Internal organization.

5-14

92CMw 36890Rr

CDP65C51,CDP65C51A
CDP65C51/51A INTERNAL ORGANIZATION (Cont'd)

TIMING AND CONTROL

Receiver Data Register Full (Bit 3)

The Timing and Control logic controls the timing of data
transfers on the internal data bus and the registers, the Data
Bus Buffer, and the ,microprocessor data bus, and the
hardware reset features.

This bit goes to a "1" when the CDP65C51/51A transfers data
from the Receiver Shift Register to the Receiver Data
Register, and goes to a "0" when the processor reads the
Receiver Data Register.

Timing is controlled by the system ~2 clock input. The chip
will perform data transfers to or from the microcomputer
data bus during the ~2 high period when selected.

Transmitter Data Register Empty (Bit 4)

All registers will be initialized by the Timing and Control
Logic when the Reset (RES) line goes low. Seethe individual
register description for the state of the registers following a
hardware reset.
TRANSMITTER AND RECEIVER
DATA REGISTERS
These registers are used a temporary data storage for the
CDP65C51/51A Transmit and Receive circuits. Both the
mitter and Receiver are selected by a Register Select 0
(RSO) and Register Select 1 (RS1) low condition. The
Read/Write line determines which actually uses the internal
data bus; the Transmitter Data Register is write only and the
Receiver Data Register is read only.
Bit 0 is the first bit to be transmitted from the Transmitter
Data Register (least significant bit first). The higher order
bits follow in order. Unused bits in this register are "don't
care".
The Receiver Data Register holds the first received data bit
in bit 0 (least significant bit first). Unused high-order bits
are "0". Parity bits are not contained in the Receiver Data
Register. They are stripped off after being used for parity
checking.

This bit goes to a "1" when the CDP65C51/51A transfers data
from the Transmitter Data Register to the Transmitter Shift
Register, and goes to a "0" when the processor writes new
data onto the Transmitter Data Register.
Data Carrier Detect (Bit 5) and
Data Set Ready (Bit 6)
These bits reflect the levels of the DCi5 and DSR Inputs to the
CDP65C51/51A A "0" indicates a high (false). Whenever
either of these inputs changes state, in immediate processor
interrupt occurs, unless the CDP65C51/51A is disabled (bit 0 of
the Command Register is a "0"). When the interrupt occurs, the
status bits will indicate the levels of the inputs immediately
after the change of state occu rred, Subsequent level changes
will not affect the status bits until the Status Register is
interrogated by the processor. At that time, another interrupt
will immediately occur and the status bits will reflect the
new input levels.
Framing Error (Bit 1), Overrun (Bit 2), and
Parity Error (Bit 0)
None of these bits causes a processor interrupt to occur,
but they are normally checked at the time the Receiver Data
Register is read so that the validity of the data can be
verified.
Interrupt (Bit 7)

STATUS REGISTER
Ag. 3 indicates the format ofthe CDP65C51/51A Status Register. A description of each status bit follows.

This bit goes to a "0" when the Status Register has been
read by the processor, and goes to a "1"whenever any kind
of interrupt occurs.

76543210

CONTROL REGISTER

I I I I I I I I I

L

PARITY ERROR·
NO PARITY ERROR
1 - PARITY eRROR DETECTED

a'---

~

FRAMING ERROR'"
0- NO FRAMING eRROR
1 - FRAMING ERROR DETECTED

OVERRUN'"
0- NO OVERRUN
1 - OVERRUN HAS OCCURRED
RECEIVER DATA REGISTER FULL
0- NOT FULL
1 - FULL
TRANSMITTER DATA REGISTER EMPTY
0- NOT EMPTY
1 - EMPTY
DATA CARRIER DETECT (0C0)
0- oeD LOW (DETECT)
1 - oeD HIGH (NOT DETECTED)
DATA SET READY (DSR)
0- DBR LOW I READY)
1 - DSR HIGH (NOT READy)
INTERRUPT (IRQ)

O· NO INTERRUPT (IRQ PIN HIGH)
1 • INTERRUPT HAS OCCURRED (iJfQ PIN LOW)
·NO INTERRUPTS OCCUR FOR

76543210

THESE CONDITIONS

REseT (RES)
I.-°1-1-111°10101~IHARDWARE
.-.-.-.-. 0 .- .-.PROGRAM RESET
92CM·36783A1

Fig. 3 - Status rflglstflr format.

The Control Register selects the desired transmitter baud
rate, receiver clock source, word length, and the number of
stop bits.
Selected Baud Rate (Bits 0,1,2,3)
These bits, set by the processor, select the Transmitter
baud rate, which can be at 1/16 an external clock rate or one
of 15 other rates controlled by the internal baud-rate
generator as shown in Fig. 4.
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A "0"
causes the Receiver to operate at a baud rate of 1116 an
external clock. A "1" causes the Receiver to operate at the
same baud rate as is selected for the transmitter as shown in
Fig. 4.
Word Length (Bits 5, 6)
These bits determine the word length to be used (5, 6, 7 or 8
bits). Fig. 4 shows the configuration for each numberof bits
desired.
Stop Bit Number (Bit 7)
This bit determines the number of stop bits used. A "0"
always indicates one stop bit. A "1" indicates 1'h stop bits if
the word length is 5 with no parity selected, 1 stop bit if the
word length is 8 with parity selected, and 2 stop bits in all
other configurations.

5-15

CDP65C51, CDP65C51A
CDP65C51/51A INTERNAL ORGANIZATION (Cont'd)

I

Data Terminal Ready (Bit 0)

o

8

WL
SBR
SBN WL1 WLO Res seRa S9M SBRl SBRO

L-1

1'------ !1.!12

SELECTED BAUD RATE (SBR)

0000 1/18X EXTERNAL CLOCK
SO'

0001
0010
0011

75
108.12
134.58
150
300
600
1200
1800
2400
3600
4800
7200
88GO
19200

0100
0101

0110
0111
1000
1001
1010

1011
1100
1101
1110

1111

BAUD
BAUD
BAUD
BAUD
BAUD
BAUD
BAUD
BAUD
BAUD
BAUD
BAUD
BAUD
BAUD
BAUD
BAUD

RECEIVER CLOCK SOURCE (RCS)
0- EXTERNAL RECEIVER CLOCK
1 - BAUD RATE I
1-_ _ _ _ _ _ _ _ _ _ _ WORD LENGTH (WI.!

J}'

01 7 BITS
10 6 BITS
11 SBITS
STOP BIT NUMBER (SBN)
0-1 STOP BIT

10- 10- 1°- 1°- 1°- 1°- 10- 1°1
HARDWARJ; RESET (RES)
- PROGRAM REseT

FOR WL=5 AND NO PARITY

-1 STOP BIT

92CM- 36781

COMMAND REGISTER
The Command Register controls specific modes and
functions (Fig. 5).

:1

PME

I RENI

J IRD

TIC
TICl TlCO

L --.l

Receiver Echo Mode (Bit 4)

This bit enables parity bit generation and checking. A "0"
disables parity bit generation by the Transmitter and parity
bit checking by the Receiver. A "1" bit enables generation
and checking of parity bits.
Parity Mode Control (Bits 6, 7)

Fig. 4 - CDP65C51/51A control ragistar.

PMe
PMel PMeo

Transmitter Interrupt Control (Bits 2, 3)
These bits control the state of the Ready to Send (RTS) line
and the Transmitter interrupt. Fig. 5 shows the various
configurations of the RTS line and Transmit Interrupt bit
settings.

Parity Mode Enable (Bit 5)

1 - 2 STOP BITS
- 1"'1/2 STOP BITS
FOR WL=8 AND PARITY

I

Receiver Interrupt Control (Bit 1)
This bit disables the Receiver from generating an interrupt
when set to a "1". The Receiver interrupt is enabled when
this bit is set to a "0" and Bit 0 is set to a "1".

This bit enables the Receiver Echo Mode. Bits 2 and 3 must
be zero. In the Receiver Echo Mode, the Transmitter returns
each transmission received by the Receiver delayed by 'h bit
time. A "1" enables the Receiver Echo Mode. A "0" bit
disables the mode.

00 8 BITS

78543210

This bit enables all selected interrupts and controls the
state of the Data Terminal Ready (DTR) line. A "0" indicates
the microcomputer system is not ready by setting the DTR
line high. A "1" indicates the microcomputer system is
ready be setting the DTR line low. When the DTR bit is setto
a "0", the receiver and transmitter are both disabled.

These bits determine the type of parity generated by the
Transmitter, (even, odd, mark or space) and the type of
parity check done by the Receiver (even, odd, or no check).
Fig. 5 shows the possible bit configurations for the Parity
Mode Control bits.

IDTR I

L
I---

DATA TERMINAL READY IOTA)
o ~ DATA TERMINAL NOT READY {OTR PIN HIGH,
1 ~ DATA TERMINAL READY (OTR PIN LOW)
RECEIVER INTERRUPT CONTROL (IRD)
0- RECEIVER INTERRUPT ENABLED
1 - RECEIVER INTERRUPT DISABLED

L -_ _ _ _ _ TRANSMITTER INTERRUPT CONTROL (TIC) - See Note

3 2

i5 0: RTs - HIGH, TRANSMIT INTERRUPT DISABLEO"
a 1 ifB- LOW, TRANSMIT INTERRUPT ENABLE
1 0 m - LOW. TRANSMIT INTERRUPT DISABLED
1 1 m - LOW. TRANSMIT INTERRUPT DISABLED
TRANSMIT BREAK ON T x 0
' - - - - - - - - - - - RECEIVER ECHO MODe (REM)
0- RECEIVER NORMAL MODE
1 - RECEIVER ECHO MODe"
L---_ _ _ _ _ _ _ _ _ _ PARITY MODE ENABLE (PME)

a - PARITY MODE DISABLED
NO PARITY 81T GENERATED
PARITY CHECK DISABLED
1 - PARITY MODE ENABLED
L -_ _ _ _ _ _ _ _ _ _ _ _ _ PARITY MODe CONTROL (PMC)

I!

a a ODD PARITY TRANSMITTED/RECEIVED
o 1 EVEN PARITY TRANSMITTED/RECEIVED
1 a MARK PARITY 81T TRANSMITTED
PARITY CHECK DISABLED
1 1 SPACE PARITY BIT TRANSMITTED
PARITY CHECK DISABLED

.. BITS 2 AND 3 MUST BE ZERO FOR RECEIVER ECHO MODE. RTS Will BE LOW.

Fig. 5 - CDP65C51/51A command registar

92CM-36790A1

5-16

NOTE: When changing command register
bits 3 and 2 from 0,1 to 1 ,0 a 'break' may be
generated. To avoid the generation of this
break, always change from 0,1 to 0,0 to 1,0.

CDP65C51,CDP65C51A
CDP65C51/51A INTERNAL ORGANIZATION (Cont'd)

...-"""'1,.....--RxD

TRANSMITTER AND RECEIVER
Bits 0-3 of the Control Register select the divisor used to
generate the baud rate for the Transmitter. If the Receiver
clock is to use the same baud rate as the transmitter. then
RxC becomes an output and can be used to slave other circuits to the CDP65C51151A Fig. 6 shows the Transmitter and
Receiver layout.

~-------------RxC

XT1.--r------,

XTLO

TxD
92CS~36791

Fig. 6 - Transmitter receiver clock circuits.

CDP65C51/51A OPERATION
TRANSMITTER AND RECEIVER OPERATION
Contlnous Data Transmit (Fig. 7)
processor must then identify that the Transmit Data Register is
ready to be loaded and must then load it with the next data
word. This must occur before the end of the Stop Bit, otherwise
a continuous "Mark" will be transmitted.

In the normal operating mode, the processor interrupt (IRQ) is
used to signal when the CDP65C51151A Is ready to accept the
next data word to be transmitted. This interrupt occurs at the
beginning of the Start Bit When the processor reads the Status
Register of the CDP65C51/51A, the interrupt is cleared. The
CHAR#n

/

CHAR#n+1

~/

I

CHAR#n+2

~

I

T""~_..;S:!.:T.:::O:;P

CHAR#n+3

~

I

STOP

STOP

TxDl GET-GEl I [BOGrGEI I GOf8tI_:GEJ I
~ART

~TART

I

I

I

I

PROCESSOR

INTERRUPT
(TRANSMIT DATA
REGISTER EMPTY)

fTART

,

I

,
STOP

L

GB]~;o8

I

fTART

,

I

I

I

I

I

/

l

)

.....a

I CI

PROCESSOR MUST
LOAD NEW DATA

IN THIS TIME

92CM-3619ZR1

PROCESSOR READS STATUS
REGISTER, CAUSES IRQ
TO CLEAR

Fig. 7 - Continuous data transmit.

Similar to the above case, the normal mode Is to generate a
processor interrupt when the CDP65C51/51A has received a
full data word. This occurs at about the 8/16 point through the

Stop Bit The processor must read the Status Register and rad
the data word before the next interrupt, otherwise the Overrun
condition occurs.

CHAR #n+1

CHAR #n+2

/r-------~------~,/
RxD

l

START

CHAR #n+3

'/r--------~I--------~,

,/

,...--._.,SrT~O:;P

GB~:GliJ

STOP

STOP

STOP

I f%IB]_GEJ I GGrBiJ I [BOB E8 L
I

)I
START

I

I

Lru'

PROCESSOR
INTERRUPT OCCURS

coB

1-::11

a
co_

INTERVAL; OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTED

CHAR#n

CI

rn-

:::I"

START

:

!

/Lru

~f~:&\!;::~~T~~WwIS~,

I START

I
I

Lru

l

OVERRUN OCCURS

92CM·38793R1

ABOUT 8/18 INTO

LAST STOP BIT.
PARITY, OVERRUN,
AND FRAMING ERROR
UPDATED, ALSO

PROCESSOR READS STATUS
REGISTER, CAUSES IRQ
TO CLEAR

Fig. 8 - Continuous data receive.

5-17

I

~

CDP65C51,CDP65C51A
CDP65C51/51A OPERATION (Conl'd)

Transmit Data Register Not Loaded
By Processor (Fig. 9)
processor finally loads new data, a Start Bit immediately
occurs, the data word transmission is started, and another
interrupt is initiated, signaling for the next data word.

If the processor is unable to load the Transmit Data Register
in the allocated time, then the TxD line will go to the
"MARK" condition until the data is loaded. When the

CONTINUOUS "MARK"

CHAR#n

nI
STOP

Tx D

/~--------~I--------~,/r--------~---------

STOP

r-

STOP

I

[ii0f:J]:~~ljJ

START

CHAR #n+2

CHAR#n+1

/r--------~I--------~~

FF[EJi] IJ"TART[%El]~
ISTART

CHARACTER~

TIME

I

......------

/

\

PRocLSOf
INTERRUPT

WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY

FOR DATA

REGISTER
EMPTY

INTERRUPTS
CONTINUE AT
CHARACTER RATE
EVEN THOUGH
NO DATA IS
TRANSMITTED

PROCESSOR
READS
STATUS
REGISTER

92CM- 36794RI

Fig. 9 - Transmit data register not loaded by processor.

Effect of CTS on CDP65C51 Transmitter (Fig. 10)
CTS is the Clear-to-Send signal generated by the modem.
It is normally low (true state) but may go high in the event of
some modem problems. When this occurs, the TxD line
immediately goes to the "Mark" condition. Interrupts continue at the same rate, but the Status Register does not
CHAR #n

indicate the Transient Data Register is empty. Since there is
no status bit for CTS, the processor must deduce that CTS
has gone to the False (high) state. This is covered later. CTS
is a transmit control line only, and has no effect on the
CDP65C51 Receiver Operation.

CHAR #n+ 1

CONTINUOUS "MARK"

______~I__________~,/~----------~IL------------,

TXDEL.I 9N I P ISTOPlsTARTI

Do

I

9,1--, 9N I

I

r---~--~T/~============:'======::

P ISTOP STARTI

Do

I

9,

H

NOT ClEAR-TO-SEND

CLEAR-TO-SEND

_/

CTS GOES HIGH.
INDICATING MODEM
IS NOT READY TO
RECEIVE DATA. Tx 0
IMMEDIATELY GOES
TO "MARK" CONDITION

NEXT

PROCESSOR
INTERRUPT
AT NORMAL
START BIT
TIME

PROCESSOR READS
STATUS REGISTER.
SINCE DATA REGISTER
IS ~ EMPTY, PROCESSOR
MUST DEDUCE THAT
IS
OF
INTERRUPT (THIS IS
COVERED ELSEWHERE
IN THIS NOTE).

rn SOURCE

92CM- 36795

Fig. 10 - Effect of CTS on CDP65C51 transmitter

5-18

CDP65C51,CDP65C51A
CDP65C51/51A OPERATION (Cont'd)

TRANSMITTER AND RECEIVER OPERATION (Cont'd)
Effect of CTS on CDP65C51A Transmitter (Fig. 10A)
shifted out of the Transmitter Sh ift Register. Since there is
no status bit for CTS, the processor must deduce that CTS
has gone to the False (high) state. This is covered later. CTS
is a transmit control line only, and has no effect on the
CDP65C51 A Receiver Operation. Normal transmission will
resume when CTS goes low again.

CTS is the Clear-to-Send signal generated by the modem. It
is normally low (true state) but may go high in the event of
some modem problems. When this occurs, the TxD line
goes to the "MARK" condition following the complete
transmission of any character which is currently being

CONTINUOUS "MARK"

CHAR#n
CHAR#n+1
______-L___________ .~~------~IL---------~,

BO

/~

I I I I ISTOPISTARTI I
B,

BN

Bo

p

____~IL-_______

B,

I

u

III

7
iRQ IS NOT ASSERTED
AGAIN UNTIL ITs
GOES LOW

NOT CLEAR· TO-SE N 0

CLEAR-TO-SEND

CTS GOES HIGH,
INDICATING MODEM

IS NOT READY TO
RECEIVE DATA. T.O
GOES TO "MARK" CONDITION
AFTER COMPLETE CHARACTER
IS TRANSMITTED.

Fig. 10A - Effect of CTS on CDP65C51A transmitter

v.

=eI
=fl:
=......

0-

'-:E

Effect of Overrun on Receiver (Fig. 11)

-Q.

If the processor does not read the Receiver Data Register in
the allocated time, then, when the following interrupt
occurs, the new data word is not transferred to the Receiver
CHAR#n
~

STOP

I

Data Register, but the Overrun status bit is set. Thus, the
Data Register will contain the last valid data word received
and all following data is lost.

CHAR#n+1

,/~

STOP

CHAR#n+2

________LI______~,/

CHAR#n+3

I

,/~

STOP

STOP

________~I_____

AXOn GGIEEJ I GET EEl I GGIGEJ I r;GI~H
111-."..----RECEIYER DATA REGISTER
NOT UPDATED BECAUSE
PROCESSOR DID NOT READ
PREVIOUS DATA. OVERRUN
BIT SET IN STATUS
REGISTER.

~---,.-----~/ ~
OVERRUN BIT SET IN
STATUS REGISTER
92CM-36796RI

Fig. 11 - Effect of overrun on receiver.

5-19

10:

Q.

CDP65C51,CDP65C51A
CDP65C51/51A OPERATION (Cont'd)

TRANSMITTER AND RECEIVER OPERATION (Cont'd)
Echo Mode Timing (Fig. 12)
In Echo Mode, theTxD linere-transmits thedataon the RxD

line, delayed by 'h of the bit time.

Fig. 12 - Echo mode timing.

Effect of CTS on Echo Mode Operation (Fig. 13)
See "Effect of eTS on Transmitter" for the effect of eTS on
the Transmitter. Receiver operation is unaffected by eTS,
so, in Echo Mode, the Transmitter is affected in the same
way as "Effect of eTS on Transmitter".lnthis case however,

CHAR#n

CHAR#n+1

---.....,/r----....
' ----\J
STOP

I~

-uu

CHAR#n+:2

'

STOP

f%GT~bEJ

RXD]l

the processor interrupts signify that the Receiver Data
Register is full, so the processor has no way of knowing that
the Transmitter has ceased to echo.

'oj
STOP

[BOIBtJ]~EJ

I

STOP

GJ3~:EEJ

I

GGI]~[

I~

I~

I~

LlII

LlII

lJlJrTT""--

m+--+-I_I
IRb

I

CHAR#n+3

'-./r----.L.'- - - -

'

NOT-CLEAR-T()'SEND

I

STOP

TxD

=:TLEGI IBNI pI
START

I
I IBo1·,1 B2 Jj

STOP

[TART-

)

CTS GOES TQ

I

"FALSE" CONDITION

NORMAL
RECEIVER DATA

L - - - - - - - - - - - - R E G I S T E R FULL - - - - - - - - - - - - - - '
INTERRUPTS

92CM-36798

Fig. 13 - Effect of CTS on echo mode.

5-20

CDP65C51,CDP65C51A
CDP65C51/51A OPERATION (Conl'd)

TRANSMITTER AND RECEIVER OPERATION (Cont'd)
Overrun In Echo Mode (Fig. 14)
If Overrun occurs in Echo Mode, the Receiver is affected the
same way as described in "Effect of Overrun on Receiver".

line goes to the "MARK" condition until the first Start Bit
after the Receiver Data Register is read by the processor.

For the re-transmitted data, when overrun occurs, the TxD
CHAR #n

STOP

STOP

R3J~El

R'OJl

I

I~

rna

L-ill"

+1

!

!

STOP

STOP

f%REEJ I GG[E0] I GTiitrH

~

/LJI]

~

~

Llll

11

fSTOP f

TXD:II
I

CHAR #x

CHAR #x

~/r---------L!--------~~

LllI. . .- - -

, , /

[BOEf EG

START

PROCESSOR
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
PROCESSOR
READS
STATUS
REGISTER

PROCESSOR FINALLY
READS RECEIVER
• DATA REGISTER,
LAST VALID
CHARACTER (#nl
PROCESSOR
INTERRUPT
FOR CHAR #x

oveRRUN OCCURS
T x D GOE8TO
"MARK"
CONDITION

IN RECEIVER
DATA REGISTER
92CM-3678B

Fig. 14 - Overrun in echo mode.

Framing Error (Fig. 15)
Framing Error is caused by the absence of Stop Bit(s) on
received data. The status bit is set when the processor
interrupt occurs. Subsequent data words are tested for

Framing Error separately, so the status bit will always
reflect the last data word received.

R,O
(EXPECTED)

RxO
(ACTUAl)

I

NOTES:
1. FRAMING ERROR DOES NOT

PROCESSOR
INTERRUPT,

INHIBIT RECEIVER OPERATION.
2. IF NEXT DATA WORD IS OK.
FRAMING ERROR IS CLEARED.

FRAMING
ERROR
BIT SET
92CM- 36789

Fig. 15 - Framing error.

5-21

CDP65C51,CDP65C51A
CDP65C51/51A OPERATION (Cont'd)

TRANSMITTER AND RECEIVER OPERATION (Cont'd)
Effect of OeD on Receiver (Fig. 16)
Once such a change of state occurs, subsequent transitions
will not cause interrupts or changes in the Status Register until
the first interrupt is serviced. When the Status Register is read
by the processor, the CDP65C51/51A automatically checks
the level of the DCD line, and if it has changed, another interrupt occurs.

DCD is a modem output used to indicate the status of the carrier frequency detection circuit of the modem. This line goes
high for a loss of carrier. Normally, when this occurs, the modem will stop transmitting data (RxD on the CDP65C51/51A
some time later). The CDP65C51/51A will cause a processor
interrupt whenever DCD changes state and will indicate this
condition via the Status Register.
,-_,--~S~T~O~P

RxD

r--r__r--r,-____~C=O~N~T~IN~U~O=US~.~.M=A~R=K·_·_____,~S~TO~P

\ \BolI B,\ B2\\

80\ B, IB2\ J~;}o::J

1

START

START

r':,~~~1

~

1':,~~~1

____________~---JI

I~-----+------------~--

I

I

LJIrLlI]rc,===:::;:t===::7i/LJ]]

IRQ

t

;~6'~EAs~OR
INTERRUPT

STOP

B I [%G[GE] L

r

I

AS LONG AS

PROCESSOR
INTERRUPT

~~~N~C~IGH

r5e6IS HIGH.

PROCESSOR

FOR RECEIVER

INTERRUPT

~N~~~:~~~;

WILL OCCUR

~~~N~OW

Iii

I
III
L __ 1Ll

t

NO INTERRUPT
WILL OCCUR
HERE, SINCE
RECEIVER IS NOT
ENABLED UNTIL
FIRST START BIT
DETECTED

PROCESSOR
INTERRUPT

FOR
RECEIVER
DATA

92CM-36786

Fig. 16 - Effect of DC D on receiver.

Timing with 1'12 Stop Bits (Fig.17)
It is possible to select 1 V, Stop Bits, but this occurs only for
5-bit data words with no parity bit. In this case, the

processor interrupt for Receiver Data Register Full occurs
halfway through the trailing half-Stop Bit.

CHAR#n

CHAR#n+1

I

I

RxD

un

L

1

PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGH THE 1/2
STOP BIT

Fig. 17 - Timing with 1-1/2 stop bits.

5-22

92CM- 36787

CDP65C51,CDP65C51A
TRANSMITTER AND RECEIVER OPERATION (Cont'd)
Transmit Continuous "BREAK" (Fig. 18)
The mode is selected via the CDP65C51/51A Command
Register and causes the Transmitter to send continuous
"BREAK" characters after both the transmitter and transmitter-holding registers have been emptied.

When the Command Register is programmed back to nor·
mal transmit mode, a Stop Bit is generated and normal
transmission continues.

/
STOP

BN

P

I~G

STOP

I GEl

IRO

I-----------j NORMAL
INTERRUPT

POINTATWHI~

PERIOD DURING
WHICH PROCESSOR
SELECTS
CONTINUOUS

PROCESSOR
SELECTS
NORMAL
TRANSMIT
MODE

"BREAK" MODE

/
PROCESSOR.
INTERRUPT
TO LOAD
TRANSMIT
DATA
92CM-36785

Fig. 18 - Transmit continuous "BREAK".

Receive Continuous "BREAK" (Fig. 19)
In the event the modem transmits continous "BREAK"
characters, the CDP65C51/51A will terminate receiving.

-------~
T"-'r--rSc:;TO~P,
RxD

E~OEB

I

I

Reception will resume only after a Stop Bit is encountered
by the CDP65C51/51 A.

CONTINUOUS ".REAK"

,/~------

/
STOP

,.o,B,

START

,BN, P

STOP

~TOP, ~-:s:::::J

I

I

I

START

-

--wrb:!J '<

I

START

n----

----,~...-:
PROCESSOR
INTERRUPT
FOR
RECEIVER
DATA REGISTER
FULL

I I;;;

PROCESSOR
INTERRUPT
WITH FRAMING
ERROR (PARITY
AND OVERRUN
CHECKS NORMAL)

NO INTERRUPT
SINCE RECEIVER
DISABLED UNTIL
FIRST STOP BIT

Fig. 19 - Receive continuous "BREAK".

5-23

92CM- 36784

NORMAL
nEelEVER
INTERRUPT

CDP65C51,CDP65C51A
CDP65C51/51A OPERATION (Cont'd)

STATUS REGISTER OPERATION

Because of the special functions of the various status bits.
there is a suggested sequence for checking them. When an
interrupt occurs, the CDP65C51/51A should be interrogated,
as follows:
1. Read Status Register
This operation automatically clears Bit 7 (IRQ).
Subsequent transitions on DSR and DCD will cause
another interrupt.
2. Check IRQ Bit

If not set. interrupt source is not the CDP65C51/51A.

2. If Bit a of Command Register is "a" (disabled). then:
a) All interrupts disabled. including those caused by
DCD and~ transitions.
b) Receiver disabled. but a character currently being
received will be completed first.
c) Transmitter is disabled after both the Transmit Data
and Transmit Shift Registers have been emptied.
3. Odd parity occurs when the sum of all the "1" bits in the
data word (including the parity bit) is odd.
4. In the Receive Mode. the received parity bit does not go
into the Receiver Data Register. but is used to generate
parity error for the Status Register.
5. Transmitter and Receiver may be in full operation
simultaneously. This is "full-duplex" mode.

3. Check DCD and DSR
These must be compared to their previous levels. which
must have been saved by the processor. If they are both
"a" (modem "on-line") and they are unchanged then the
remaining bits must be checked.

6. If the RxD line inadvertently goes low and then high
during the first 9 receiver clocks after a Stop Bit; a false
Start Bit will result.
For false Start Bit detection, the CDP65C51/51A does not
begin to receive data, instead, only a true Start Bit initiates
receiver operation.

4. Check RDRF (Bit 3)
Check for Receiver Data Register Full.

7. A precaution to consider with the crystal oscillator
circuit is:
The XTLI input may be used as an external clock
input. The XTLO pin must be floating and may not be
used for any other function.

5. Check Parity. Overrun. and Framing Error (Bits 0-2)
Only if Receiver Data Register is Full.
6. Check TDRE (Bit 4)
Check for Transmitter Data Register Empty.
7. If none of the above. then CTS must have gone to the
False (high) state.
PROGRAMMED RESET OPERATION

A program reset occurs when the processor performs a write
operation to the CDP65C51/51A with RSO high and RS1
low. The program reset operates somewhat different from
the hardware reset (RES pin) and is described as follows:
1. I nternal registers are not completely cleared. The data
sheet indicates the effect of a program reset on internal
registers.
2. The DTR line goes high immediately.
3. Receiver and transmitter interrupts are disabled
immediately. If IRQ is low when the reset occurs. it stays
low until serviced. unless interrupt was caused by DCD
or DSR transition.
4. DCD and DSR interrupts disabled immediately. If IRQ is
low and was caused by DCD or DSR. then it goes high.
also""iJCD and DSR status bits subsequently will follow
the input lines. although no interrupt will occur.

8. DCD and DSR transitions. although causing immediate
processor interrupts. have no effect on transmitter
operation. Data will continue to be sent. unless the
processor forces transmitter to turn off. Since these are
high-impedance inputs. they must not be permitted to
float (un-connected). If unused. they must beterminated
either to Gnd or Voo.
GENERATION OF NON-STANDARD BAUD RATES
Divisors

The internal counter/divider circuit selects the appropriate
divisor for the crystal frequency by means of bits 0-3 of the
CDP65C51/51A Control Register.
The divisors. then. are determined by bits 0-3 in the Control
Register and their values are shown in Table II.
Generating Other Baud Rates

By using a different crystal. other baud rates may be
generated. These can be determined by:
Baud Rate = Crystal Frequency
Divisor

5. Overru n cleared. if set.
MISCELLANEOUS NOTES ON OPERATION

1. If Echo Mode is selected. RTS goes low.

Furthermore, it is possible to drive the CDP65C51/51A with an
off chip oscillator to achieve the same thing. In this case, XTU
(pin 6) must be the clock input and XTLO (pin 7) must be a no
connect.

5-24

CDP65C51,CDP65C51A
CDP65C51/51A OPERATION (Cont'd)

Table II - Divisor Selection

3
0

CONTROL
REGISTER
BITS
2
1
0
0

DIVISOR SELECTED
FOR THE
INTERNAL COUNTER
0
0

No Divisor Selected

BAUD RATE GENERATED
WITH 1.8432 MHz

1/16 of External Clock at Pin XTLI 1/16 of External Clock at Pin XTLI

1.8432 x 10·
0

0

0

1

36.864

0

0

1

0

24,576

24576
1.8432 x 10·

0

0

1

1

16,768

16768
1.8432 x 10·

0

1

0

0

13.696

0

1

0

1

12,288

36.864
1.8432 x 10·

50
75

= 109.92

= 134.58
13.696
1.8432 x 10·
150
12288
1.8432 x 10·

0

1

1

0

6.144

0

1

1

1

3.072

- 300
6144
1.8432 x 106
600
3.072
1.8432 x 10·

1

0

0

0

1.536

1

0

0

1

1,024

1

0

1

0

768

768
1.8432 x 10·

1

0

1

1

512

512
1.8432 x 106

1

1

0

0

384

384
1.8432 x 10·

1

1

0

1

BAUD RATE GENERATED
WITH FREQUENCY (F)

1536
1.8432 x 10·
U124
1.8432 x 10·

256

256
1.8432 x 10·

1

1

1

0

192

192
1.8432 x 10·

1

1

1

1

96

96

= 1200
= 1800

= 2400
= 3600
= 4800
= 7200
= 9600
= 19200

DIAGNOSTIC LOOP-BACK OPERATING MODES
A simplified block diagram for a system incorporating a CDP65C51/51A Is shown in Fig. 20.

TO DATA LINK

Fig. 20 - Simplified system diagram.

5-25

F
36.864
F
24576
F
16768
F
13.696
F
12288
F
6144
F
3072
F
1536
F
1024
F
768
F
512
F
384
F
256
F
192
F
96

CI.I

CI.I...I

::Ii:!
r:r:I
w

I-::C

-a..
r:r:I_
1

a::

"'w
a..

CDP65C5~CDP65C51A
CDP65C51/51A OPERATION (Cont'd)

DIAGNOSTIC LOOP·BACK OPERATING MODES

(Confd)
Occasionally it may be desirable to include in the system a
facility for "loop-back" diagnostic testing, of which there
are two kinds:

3. Connects transmitter outputs to respective receiver
inputs:
a) TxDto RxD

1. local loop-Back

b) DTR to DCD

loop-back from the pOint ofview ofthe processor. In this
case, the Modem and Data link must be effectively
disconnected and the ACIA transmitter connected back
to its own receiver, so that the processor can perform
diagnostic checks on the system, excluding the actual
data channel.

c) RTStoCTS
llB may be tied to a peripheral control pin to provide
processor control of local loop-back operation. In this way,
the processor can easily perform local loop-back diagnostic
testing.

2. Remote Loop-Back
Remote loop-back does not require this circuitry, so llB
must be set low. However, the processor must select the
following:

loop-back from the point of view of the Data link and
Modem. I n this case, the processor, itself, is disconnected
and all received data is immediately retransmitted, so the
system on the other end of the Data Link may operate
independent of the local system.

1. Control Register bit 4 must be "1 ", so thatthe transmitter
clock = receiver clock.
2. Command Register bit 4 must be "1" to select Echo
Mode.

The CDP65C51/51A does not contain automatic loop back
operating modes, but they may be implemented with the
addition of a small amount of external circuitry.

3. Command Register bits 3 and 2 must be "1" and "0",
respectively, to disable transmitter interrupts.

Fig. 21 indicates the necessary logic to be used with the
CDP65C51151A.

4. Command Register bit 1 must be "0" to disable receiver
interrupts.

The lLB line is the positiv&-true signal to enable local loopback operation. Essentially, LlB = high does the following:

In this way, the system retransmits received data without
any effect on the local system.

1. Disables outputs TxD, DTR, and RTS (to Modem).
2. Disables inputs RxD, DCD, CTS, DSR (from Modem).

CDPS5C51 1S1A

I

• RTS

Di'ii

RxD

TxD

SEL

LL8

DCD

CTS

DSA

I

1VJ
2V

~

-~

-

SEL

1V

ST8

3V

ST8

3V

CDHC157 4V
18
1A
28
38

2A
3A

48

4A

+5

t=-

CDHC157 4V
18

1A

28
38

2A
3A

48

4A

CTS
DSA
ODEM
TxD
DTA

2V

~

AxD
DCD

ATS

92CM- 36799

-

-

NOTES: 1. HIGH ON LL8 SELECTS LOCAL LOOP·BACK MODE.
2. HIGH ON HC157 SELECT INPUT GATES "B" INPUTS
TO "YO OUTPUTS; LOW GATES "A" TO ·V".

Fig. 21 - Loop-back circuit schematic.

5-26

CDP65C51,CDP65C51A
DYNAMIC ELECTRICAL CHARACTERISTICS-READ/WRITE CYCLE
VOO

= 5V ±

5%, TA

= -40 o C to +850 C,

CL

= 75pF
LIMITS
CDP65C51-1
CDP65C51A-1

CDP65C51-2
CDP65C51A-2

MIN

MAX

MIN

MAX

MIN

MAX

tCYC

1

-

0.5

-

0.25

-

~s

tc

400

-

200

-

100

-

ns

Address Setup Time

tAC

120

-

60

-

30

Address Hold Time

tCAH

0

-

0

-

0

R/W Setup Time

twc

120

60

tCWH

0

Data Bus Setup Time

tDCW

120

Data Bus Hold Time

tHW

20

10

-

30

R/W Hold Time

-

5

-

Read Access Time (Valid Data)

tCDR

-

200

-

150

-

50

ns

tHR

20

-

10

20

-

10

-

ns

tCDA

-

10

40

CHARACTERISTIC
Cycle Time
$2 Pulse Width

Read Hold Time
Bus Active Time (Invalid Data)

.2 _____-'

0
60

CDP65C51-4
CDP65C51A-4

0
35

'c----i

~---4-------~-~~D~~~~7T7Tr-~H

CSO , CST, RSO,RS'

'---+-------1---1 \L..<~.4L"-"-""""'"""''"'-VIL
..It:-------VIH

R/W

VIL

7?77777777~i"?":i"?":'7.1 j.-r-_'_DC____
DATA BUS

'H_W_=1........

~

-

-

r

V'H

V///////////
-'"----------'N~VIL

Write-timing waveforms
V1H

"~=!/~w~eDR -.J 'HR ~
DATA BUS

/////////

'eDA

V1L
-----1-~~#VOH
VOL

Read-timing waveforms

Fig. 22 - Timing waveforms.

5-27

92CM-3677S

UNITS

ns
ns
ns
ns
ns
ns

ns

CDP65C51,CDP65C51A
DYNAMIC ELECTRICAL CHARACTERISTICS-TRANSMIT/RECEIVE, See Figs. 23, 24 and 2S.
VDD = SV ±S%,TA = -400C to +8So C
LIMITS
CDP6SCS1/S1A-1
CHARACTERISTIC

CDP6SCS1/S1A-2

CDP6SCS1/S1A-4

MIN

MAX

MIN

MAX

MIN

tcCY

400·

-

325

-

250

Transmlt/Receive Clock High Time

tCH

175

145

tCL

175

145

-

110

Transmit/Receive Clock Low Time

-

XTLI to TxO Propagation Delay

too

-

500

-

410

tOLY

-

500

-

410

Transmit/Receive Clock Rate

IRO Propagation Delay (Clear)

tiRO

-

500

-

410

RES Pulse Width

tRES

400

-

300

-

200

= 10ns to 30ns)

(t r• tf

UNIT

-

110

-

RTS Propagation Delay

MAX

ns
ns
ns

315

ns

315

ns

315

ns

-

ns

1

• The baud rate with extemal clocking is: Baud Rate

= --

16 x TCCY

\

+2
tCCY

-t OLY-

-tCH--j

XTLI
( TRANSMIT)
CLOCK INPUT)

~

1\

J

~

OTR. RTS

.f-1
-tCL---1

I---

too

TRCi

'{

hO

(CLEAR)

NOTE: TxO RATE IS 1116 TxC RATE

r~

tiRo

r-

92CS ·36777

92CS-36776

Fig. 23 - Transmit timing waveforms with external clock.

RxC
tlNPUT)

~ F'''=l

Fig. 24 - interrupt and output timing waveforms.

1.8432 MHz
CRYSTAL

rm
XTLO

1]

TRANSMITTER
~"~,,
CLOCK

XTLI

OPEN
CIRCUIT

XTLO

I=

ICL=-:,.j

C' 10-50 pF
NOTE:

RxO RATE IS 1/16 RxC RATE

INTERNAL CLOCK

92CS-36778

Fig. 25 - Receive external clock timing waveforms.

EXTERNAL CLOCK
92CS-4230'

Fig. 26 - Transmitter clock generation.

5-28

CDP6818

EIIHARRIS

CMOS Real-Time Clock
With RAM

January 1991

Features

Description

•
•
•
•
•
•

The COP6818 Real-Time Clock pluse RAM is a
peripheral device which includes the unique
MOTEL concept for use with many 8 bit
microprocessors, microcomputers, and larger
computers. This device combines three unique
features a complete time-of- day clock with alarm
and one hundred year calendar, a programmable
periodic interrupt and square wave generator, and
50 bytes of low power static RAM. The COP6818
uses high speed CMOS technology to interface
with 1 MHz processor buses, while consuming
very little power.

Low Power, High Speed, High Density CMOS
Internal Time Base and Oscillator
Counts Seconds, Minutes and Hours of the Day
Counts Days of the Week, Date, Month and Year
3V to 6V Operation
Time Base Input Options •.••.•••••••••••••••• 4.194304MHz,
1.048576MHz, or 32.768kHz
• Time Base Oscillator for Parallel Resonant Crystals
• Typical Operating Power
~ Low Frequency Time Base .••••.••.••••••• 40/lW to 200/lW
~ High Frequency Time Base •••••••••••••.• 4.0mW to 20mW
• Binary or BCD Representation of Time, Calendar and Alarm
.12 or 24 Hour Clock with AM and PM In 12 Hour Mode
• Daylight Savings Time Option;
• Automatic End of Month Recognition
• Automatic Leap Year Compensation
• Microprocessor Bus Compatible
• MOTEL Circuit for Bus Universality
• Multiplexed Bus for Pin Efficiency
• Interfaced with Software as 64 RAM Locations
• 14 Bytes of Clock and Control Registers
• 50 Bytes of General Purpose RAM
• Status Bit Indicates Data Integrity
• Bus Compatible Interrupt Signals (IRQ)
• Three Interrupts are Separately Software Maskable and
Testable
~ Time-of-Day Alarm, Once-Per-Second to Once-Per-Day
~ Periodic Rates From 30.5/1S to 500ms
~ End-of-Clock Update Cycle
• Programmable Square Wave Output Signal
• Clock Output May Be Used As Microprocessor Clock Input
~ At Time Base Frequency +1 or +4
• 24 Pin Dual In Line Package

Pinout

PACKAGE TYPES D AND E
TOP VIEW

The Real-Time Clock plus RAM has two distinct
uses. First, it is designed- as a battery powered
CMOS device (in an otherwise NMOSmL system)
including all the common battery backed-up functions such as RAM, time, and calendar. Secondly,
the COP6818 maybe used with a CMOS
microprocessor to relieve the software of the
timekeeping workload and to extend the available
RAM of an MPU such as the COP6805E2.
The CO P6818 is supplied in a 24 lead dual-in-line
plastic package (E suffix) and in a 24 lead dual-Inline sidebrazed ceramic package (0 suffix).

'".....
"'
::::I~
c:a ....
I-::C

-Q..

c:a_
'a::

.......
Q..

Block Diagram

VDD

sow

OSC1

OSC2

"
"
"

ADO
A01
AD'
AD'
AD.

IRO

REm
DS
NC

AD.
AD.

15

A07
Vss

CI( OUT

CleFS

RtWAS

"

"

iRo
RffiT

a
RIW

Copyright

© Harris Corporation 1991

File Number
5-29

1375.1

CDP6818
MAXIMUM RATINGS (Voltages referenced to VSSI
Ratings

Symbol

Unit

Value
-0.3 to +8

Supply Voltage

VOO

All Input Voltages

Yin

VSS-0.5 to VOO+0.5

V

I

10

rnA

TA
Tstg

-55 to +150

Current Orain per Pin Excluding
VOO and VSS
Operating Temperature Range
Storage Temperature Range

o to

V

+70

°C
°C

DC ELECTRICAL CHARACTERISTICS (VOO=5 Vdc ± 10% V$S=O Vdc TA=O' to 70°C unless otherwise notedl
Characteristics

Symbol

Min

Max

Unit

fosc
VOL

32.768

4194.304

kHz

-

0.1

Frequency of Operation
Output Voltage

V

ILoad < 10 "A
100 - Bus Idle (External clock)
CKOUT=fosc , CL = 15 pF; SOW Oisabled, CE=VOD-0.2; CL (OSC21= 10 pF
fos c =4.194304 MHz
fosc = 1.048516 MHz
fosc=32.768 kHz
IDO - Ouiescent
fosc = DC; OSC1 = DC;
All Other Inputs=VOO-0.2 V;
No Clock

VOH

VOO-0.1

-

10D1
1002
1003

3
0.8
50

IDD4

-

50

"A
"A

Output High Voltage ADO-AD7 CKOUT
II Load = -1.6 rnA, SOW, ILoad= -1.0mAI

VOH

4.1

-

V

VOL

-

0.4

V

VIH

VDD-2
VOD-0.8
VOD-1

VIL

VSS
VSS
VSS

VDD
VOO
Vnn
0.8
0.8
0.8

-

±1
±10

Output Low Voltage ADO-AD? CKOUT
II Load = 1.6 rnA, IRa, and SOW, ILoad= 1.0 mAl
Input High Voltage

CKFS, ADO-AD7, OS, AS, R/W, CE, PS
RESET
OSC1

cr

ADO-A07, DS, AS, R/W,
CKFS, PS, RESET
OSC1

Input Low Voltage

Input Current
Three-State Leakage

All Inputs

lin

ADO-A07

ITSL

rnA
rnA

V

V
"A
"A

DC ELECTRICAL CHARACTERISTICS (Voo = 3 Vde, Vss = 0 Voe, TA = O' to 70'e unless otherwise noted)
Characteristics
Frequency of Operation
Output Voltage
IL'Ao<10JlA
IDD - Bus Idle
CKOUT = fo.c, CL = 15 pF, SOW Disabled,
fosc = 32.768 kHz
100 - Ouiscent
fosc= OS; OSC1=DC;
All Other Inputs = Voo-0.2 V;
No Clock'
Output High Voltage
(LLcad= -0.25 rnA, All Outputs)
Output Low Voltage
(lLOad = 0.25 rnA, All Outputs)
Input High Voltage

e"E =

Symbol

Min

Mex

Unit

fose·

32.768

kHz

VOL
VOH

32.768
0.1

Voo-D.1

1003
1004

-

50
50

J1A
JlA

VOH

2.7

-

V

-

0.3
Voo
Voo

V
V

U.I>

V
JlA
JlA

Voo-0.2, CL (OSC2) = 10 pF

ADD-AD7, OS, AS, R/W, CE,
~,CKFS,PS,OSC1

Input Low Voltage (All Inputs)
nput vurrent
Three-State Leakage

VOL
V,H
V,L

J"I!iO,
5-30

All Inputs
ADO-AD7

. in

hSL

2.1
2.5
vss

±1
±1u

V

CDP6818
BUS TIMING

= 5.0 V

Voo

±
Ident.
Number

Characteristics

Symbol

1
2
3
4
8
13
14
15
18
21
24
25
26
27
28
30
31

Cycle Time
Pulse Width, DS/E Low orlID/WR High
Pulse Width, DS/E High or '!rn/WR' Low
Input Rise and Fall Time
R/W Hold Time
R/W Setup Time Before DS/E
Chip Enable Setup Time Before AS/ALE Fall
Chip Enable Hold Time
Read Data Hold Time
Write Data Hold Time
Muxed Address Valid Time to AS/ALE Fall
Muxed Address Hold Time
Delay Time DS/E to AS/ALE Rise
Pulse Width, AS/ALE High
Delay Time, AS/ALE to DS/E Rise
Peripheral Output Data Delay Time from DS/E or RD
Peripheral Data Setup Time

!e,e
PWEL
PWEH
I.,t,

Voo = 3.0 V
50 pF Load
Min
Max

-

5000
1000
1500

-

-

100

tRwS

tcs
tCH
tOHR
tOHW

tASl

lAHL
tAse

PWASH
lASEO
tooR

tosw

130 pF Load
Max
Min
953
300
325

dc

-

30

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

-

10

10
200
200
10
10
100
200
100
500
600
500
1300
1500

tRWH

10%

2 TTL and

*
1000

-

-

-

-

-

80
55
0
10
0
50
20
50
135
60
20
200

*
100

-

-

240

-

m

NOTE: Designations E, ALE, 'RD, and
refer to signals from alternative microprocessor signals.
*See Important Application Notice (refer to Fig. 23).

/~

AS

os

--:l

1\

-

-

....

kY

~

VHIGH
~\

vLOW

....

~

I

+0
@- .. ...

®
2

/

-

0- I-

1\

3

V

~

®

(I)
(I) ....

:::Iii!!
2

DS

Read Enable

R/W

R/IN

Write Enable

Fig. 9 -

Functional diagram of MOTEL circuit.

"'::)~'"....

= .... '
=Ia::
COw
I-::C

SIGNAL DESCRIPTIONS

AT cut crystal at 4.194304 MHz or 1.048576 MHz frequencies. The crystal connections are shown in Figure 11 and the
crystal characteristics in Figure 12.

The block diagram in Figure 1, shows the pin connection
with the major internal functions of the CDP6818 Real-Time
Clock piUS RAM. The following paragraphs describe the function of each pin.

CKOUT -

Voo,VSS
DC power is provided to the part on these two pins, VDD
being the most positive voltage. The minimum and maximum voltages are listed in the Electrical Characteristics
tables.

The CKOUT pin is an output at the time-base frequency
divided by 1 or 4. A major use for CKOUT is as the input
clock to the microprocessor; thereby saving the cost of a second crystal. The frequency of CKOUT depends upon the
time-base frequency and the state of the CKFS pin as shown
in Table 2.

OSC1, OSC2 - TIME BASE, INPUTS
The time base for the time functions may be an external
signal or the crystal oscillator. External square waves at
4,194304 MHz, 1.048576 MHz, or 32.768 kHz may be connected to OSCl as shown in Figure 10. The time-base frequency to be used is chosen in Register A.
The on-chip oscillator is designed for a parallel resonant

CKFS -

CLOCK OUT, OUTPUT

CLOCK OUT FREQUENCY SELECT, INPUT

The CKOUT pin is an output at the time-base frequency
divided by 1 or 4. CKFS tied to VDD causes CKOUT to be
the same frequency as the time base at the OSCl pin. When
CKFS is at VSS, CKOUT is the OSCl time-base frequency
divided by four Table 2 summarizes the effect of CKFS.

5-35

-Q,.

Q,.

CDP6818

J
~

4.194304 MHz
or
1.048576 MHz

VD:ptional
IVDD-l.0V)

I

I

2

•

•

OSC1

or
3

32.768 kHz

----4

IOpen)

OSC2

CDP6818

Fig. 10 - External Time-base connection.

2

r-------~---._~OSC1

4.194304 MHz
or
1.048576 MHz

Rf

or
32.768 KHz

3

_-V'V'V---"'1

OSC2

CDP6818
Cout'T

'32.768 KHz - Consult manufacturers specification

Fig. 11 - Crystal oscillator connection.
Crystal Equivalent Circuit

----.'C~
L1

C1

AS

:J~2

-3------~ID~1

a

4.194304 MHz
750
7 pF
0.012 pF
15-30 pF
50 k

R
R,

-

-

10M

10M

'osc

Rs max
CO max
Cl
Cin/Cout

______

1.048576 MHz
7000
5 pF
0.008 pF
15-40 pF
35 k

Fig. 12 - Crystal parameters.

5-36

2

32.768 KHz
50K
1.7 pF
0.003 pF
10-22 pF
30 k
300-470 K
22M

CDP6818
the case with the CDP6805 family of multiplexed bus processors. To insure the competitor mode of MOTEL, the OS pin
must remain high during the time ASI ALE is high.

TABLE 2 - CLOCK OUTPUT FREQUENCIES
Time Base
(aSCII
Frequency

Clock Frequency
Select Pin
(CKFS)

Clock Frequency
Output Pin
(CKOUT)

4.194304 MHz

High

4.194304 MHz

4.194304 MHz

Low

1.048576 MHz

1.048576 MHz

High

1.048576 MHz

1.048576 MHz

Low

262.144 kHz

32.768 kHz

High

32.768 kHz

32.768 kHz

Low

8.192 kHz

SQW -

R/W -

SQUARE WAVE, OUTPUT

The SOW pin can output a signal one of 15 of the 22
internal-divider stages. The frequency and output enable of
the SOW may be altered by programming Register A, as shown
in Table 5. The SOW signal maybe turned on and off using a bit
in Register B.

CE -

Multiplexed bus processors save pins by presenting the
address during the first portion of the bus cycle and uSing the
same pins during the second portion for data. Address-thendata multiplexing does not slow the access time of the
CDP6818 since the bus reversal from address to data IS occurring during the internal RAM access time.
The address must be valid just prior to the fall of ASI ALE at
which time the CDP6818 latches the address from ADO to
AD5. Valid write data must be presented and held stable during
the latter portion of the OS or WR pulses. In a read cycle, the
CDP6818 outputs 8 bits of data during the latter porllOn of the
OS or RD pulses, then ceases driving the bus (returns the
output drivers to three-state) when OS falls in this case of
MOTEL or RD rises in the other case.

IRQ -

INTERRUPT REOUEST, OUTPUT

The IRO pin is an active low output of the CDP68UU,.hal may
be used as an interrupt input to a processor. The IRO output
remains low as long as the status bit causing the interrupt is
present a~the corresponding interrupt-enable bit is set. To
clear the IRO pin, the processor program normally reads Register C The RESET pin also clears pending interrupts.
When no interrupt conditions are present, the IRO level is in
the high-impedance state. Multiple interrupting devices may
thus be connected to an IRO bus with one pullup at the
processor.

MULTIPLEXED ADDRESS STROBE, INPUT

A positive going multiplexed address strobe pulse serves to
demultiplex the bus. The lalling edge of AS or ALE causes the
address to be latched within the CDP6818. The automatic
MOTEL circuitry in the CDP6818 also latches the state of the
OS pin with the falling edge of AS or ALE.

OS -

CHIP ENABLE, INPUT

The chip-enable (CE) signal must be asserted (low) for a
bus cycle in which the CDP6818 is to be accessed. CE is not
latched and must be stable during OS and AS (in the 6805
mode of MOTEL) and during RD and WR (in the competitor
mode) Bus cycles which take place without asserting CE
cause no actions to take place within the COP6818. When CE
is high, the multiplexed bus output is in a high-impedance
state.
_
When CE is high, all address, data, OS, and R/W inputs from
the processor are disconnected within the CDP6818. ThiS
permits the CDP6818 to be isolated from a powered-down
processor. When CE is held high, an unpowered device cannot
receive power through the input pins from the real-time clock
power source. Battery power consumption can thu~be reduced by using a pullup resistor or active clamp on CE when
the main power is off.

ADO-AD7 - MULTIPLEXED BIDIRECTtONAL
ADDRESS/DATA BUS

AS -

READ/WRITE, INPUT

The MOTEL circuit treats the R/W pin in one of two ways.
When a 6805 type processor is connected, R IW is a level
which indicates whether the current cycle is a read or write. A
read cycle is indicated with a high level on..£!/\iV while OS is
high. whereas a write cycle is a lo~on R/W during OS. .
The second interpretation of R/W is as a negative write
pulse, WR, MEMW, and I/OW from competit<.!.!:..type processors. The MOTEL circuit in this mode gives R/W pin the same
meaning as the write (W) pulse on many generic RAMs.

DATA STROBE OR READ, INPUT

RESET -

The OS pin has two interpretations via the MOTEL circuit.
When emanating from a 6800 type processor, OS is a positive
pulse during the latter portion of the bus cycle, and is variously
called OS (data strobe), E (enable), and -©",c--=-f'l
(SEE
NOTE
21

(SEE NOTE 11

39k

®(SEE

=a::
......
a..
I

1M

-+12 V(>BBV)

=I£~
=
...
-a..

.... :z;

92CM-37725

20 k

®
NOTE 21
Fig_ 23 -

Typical Application Circuit

5-47

CDP6818A

EHARRIS

CMOS Real-Time Clock
Plus RAM

January 1991

Features

Description

•
•
•
•
•
•

The CDP6818A Real-Time Clock plus RAM is a
peripheral device which includes the unique
MOTEL concept
for
use
with
various
microprocessors, microcomputers and larger
computers. This part combines three unique
features: a complete time-of-day clock with alarm
and one hundred year calendar, a programmable
periodic interrupt and square wave generator, and
50 bytes of low power static RAM. The CDP6818A
uses high speed CMOS technology to interface
with 1 MHz processor buses, while consuming
very little power.

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•

Low Power, High Speed CMOS
Internal Time Base and Oscillator
Counts Seconds, Minutes and Hours of the Day
Counts Days of the Week, Date, Month and Year
3V to 6V Operation
Time Base Input Options: 4.194304MHz, 1.048576MHz or
32.768kHz
Time Base Oscillator for Parallel Resonant Crystals
40/lW to 200/lW Typical Operating Power at Low Frequency
Time Base
4.0mW to 20mW Typical Operating Power at High Frequency
Time Base
Binary or BCD Representation of Time, Calendar and Alarm
12 or 24 Hour Clock with AM and PM in 12 Hour Mode
Daylight Savings Time Option
Automatic End of Month Recognition
Automatic Leap Year Compensation
Microprocessor Bus Compatible
Selectable Between Motorola and Competitor Bus Timing
Multiplexed Bus for Pin Efficiency
Interfaced With Software as 64 RAM Locations
14 Bytes of Clock and Control Registers
50 Bytes of General Purpose RAM
Status Bit Indicates Data Integrity
Bus Compatible Interrupt Signals (IRQ)
Three Interrupts Are Separately Software Maskable and
Testable
~ Time-of-Day Alarm, Once-Per-Second to Once-Per-Day
~ Periodic Rates From 30.5/ls to 500ms
~ End-of-Clock Update Cycle
Programmable Square Wave Output Signal
Clock Output May Be Used as Microprocessor Clock Input at
Time Base Frequency + 1 or + 4

The Real-Time Clock plus RAM has two distinct
uses. First, it is designed as a battery powered
CMOS part (in an otherwise NMOSmL system)
including all the common battery backed-up
functions such as RAM, time and calendar.
Secondly, the CDP6818A may be used with a
CMOS microprocessor to relieve the software of
the timekeeping workload and to extend the
available RAM of an MPU such as the
CDP6805E2.
The. CDP 6818A is supplied in a 24 lead dual In
line plastic package (E suffix), in a 24 lead dual in
line sidebrazed ceramic package (D suffix) and in
a 28 lead plastic chip carrier package (N suffix).

Pinouts
PACKAGE TYPES D AND E
TOP VIEW

PACKAGE TYPE N
TOP VIEW

'"
0

MOT

1

24

OSCI

2

23

VOO
SQW

22

PS

21

CKOUT

20

CKFS

ADO

OSC2
ADO

4

ADI
6

19

liTh

AOI

7

18

RESET

A02

AD4
A05

8
9

17

OS
ST8Y

A03

A06

10

15

R/W

A04

A07

11
12

14
13

AS

A05

VSS

16

'"0

4

3

I/)

A02
A03

cs

;:;

0

...

~

o ,.

~

z

>o

2

1

28 27 26

0

0

I/)

I/)

Q.

PIN1~

25

CKOUT

24

CKFS

22

RESET

IRQ

TOPVIEW

N/C

21

OS

20

STBY

19

R/W

13 14 15 16 17 18

.. ....
0

~

Copyright © Harris Corporation 1991

~

z

0

>!flll~l

.

I/)

....0
z

File Number
5-48

2041.1

CDP6818A
CKOUT

., Clock
Output

OSC1
T"ne Base
Input/Osc

OSC2

~~

-4

~~

~

- 32

M

~
VDD
VSS

DS

AS

ADO-AD?

MOT

--------

f~

+32

~HZ

+32

Periodic Interrupt/ Square Wave Rate
Selection
11 ot-15 Selectorl

y

(')

DIvider
Control

~ I ~~

- 32

CKFS

(/)

a:

0

(/)

a:

-2

~rl

Square
Wave Out

1-

~

SOW

DVO-DV2

Bus
Interface

- •

..:.f

.....
-c
~

MOT

MC3870
CDP6805
8021

{;

"-

8

8

Address/ Data

ADO-AD7

VDD

saw
STBY

Address Strobe
AS
Read
{;

CKFS

OS

Write

A/Vii

"-

CKOUT

VSS

I
I

I

L_____ _
* NOTE: CS can be controlled

Port
Lines

by a port pin (if available!.

92CS-42710

Fig. 19- CDP6818A Interfaced with the ports of A typical single
chip microcomputer.

5-65

......:.
I

CDP6818A

Descriptionl

C

C

CDP6818A
Active High Chip S e l e c t - - - - - - - - - - - - ,

E I--.....-----f

i-----iDS
CDP6818A

AO I--+_----f
N.C.N.
VDD

MC6800,
MC6802,
MC6808,

R/W

t--+-....-I

MOT
Power
Failure
Circuit

r-----tAS

or
(See STBY

MC6809

Description)

L---------------~R/W

DO-D7

VSS
92CS-42723

Fig. 20 - CDP6818A interfaced with Motorola Processors.

READ

STA
LDAB
RTS

RTC
RTC + 1

Generate AS and Latch Data from ACCA
Generate OS and Get Data

WRITE

STA
STAB
RTS

RTC
RTC + 1

Generate AS and Latch Data from ACCA
Generate OS and Store Data

Fig. 21 - Subroutine for reading and writing the CDP6818A with a
non-multiplexed bUB.

5-66

CDP6823

tl:)HARRIS

CMOS Parallel Interface

January 1991

Features

Description

• 24 Individual Programmed I/O Pins
• MOTEL Circuit for Bus Compatibility With Many
Micro processors
• Multiplexed Bus Compatible With CDP6805E2 and
Competitive Microprocessors
• Data Direction Registers for Ports A, Band C
• Reset Input to Clear Interrupts and Initialize Internal
Registers
• Four Port C I/O Pins May Be Used as Control Lines
~ Four Interrupt Inputs
~ Input Byte Latch
~ Output Pulse
~ Handshake Activity
• 15 Registers Addressed as Memory Locations
• Handshake Control Logic for Input and Output Peripheral
Operation
• Interrupt Output Pin
• 3V to 5.5V Operating VDD

The COP6823 CMOS parallel interface (CPI) provides a
universal means of interfacing external signals with the
COP6805E2 CMOS microprocessor and other multiplexed bus microprocessors. The unique MOTEL circuit
on chip allows direct interfacing to most industry CMOS
microprocessors, as well as many NMOS MPUs.

Block Diagram

Pinouts
1------",

The COP6823 CPI includes three bidirectional 8-bit
ports or 24 I/O pins. Each I/O line may be separatelyestablished as an input or an output under program control
via data direction registers associated with each port.
USing the bit change and test instructions of the
COP6805E2, each individual I/O pin can be separately
accessed. All port registers are read/Write bytes to
accomodate read-modify-write instructions.
The COP6823 is supplied in a 40 lead hermetic dual-Inline sidebrazed ceramic package (0 suffix), in a 40 lead
dual-in-line plastiC package (E suffix) and in a 44 lead
plastic chip carrier package (N suffix).
The COP6823 Is equivalent to and is a direct replacement for the industry type MC146823.
PACKAGE TYPES D AND E
TOP VIEW

.----.....-PAO

PC.

VDO
PC.

PCI
PCO
PAD
PA'
PAl

PAl

PC4/CA1
pe5/CAl
PC6/CB
PC7lCB2

pn

PM

PA,
PAS
PAS
PA7
ADO
AD'
AD.
AD.
AD'
AD'
AD.
AD'

PA'

PAS

AD'

AD5
PB2

VSS

PB3

PBO
PO,
PO.
PO,
PO.
POS

'0

....""

,."

",.'0

.0

fiiii
,.,. ......27

PO'

24
2
2
21

DS

R/W

AS

17

PM

'"

PACKAGE TYPE N

PB1

""'-----1
DS
ASE

R/W

Con1rol

Arm

Inputs

'A'
'A'
'A.
PA'

cr
VDO-----

•••

VSS---loo

'A?

2

,

ADO
PCO
POl
PC2
PCl
PC4/CAI

PC5/CA2
pe6/Cal

Copyright @ Harris Corporation 1SS1

Ne
3.

PC7IC82

37

PIO

::-- ---L ____:: ."'
.a.
"
I
3S

...

14

32

ADZ

tS

31

AD3

16

30

Plr

Ne

11

29

fRo

AD'

t.

PI.

19 20 2f

File Number
5-67

.a.

.a,

1377.1

CDP6823
MAXIMUM RATINGS (Voltages reference to VSS)
Ratings
Symbol
Value
Supply Voltage
-0.3 to +8
VDD
All Input Voltages
VSS-0.5 to VDD+0.5
Yin
Current Drain per Pin Excluding
I
10
VDD and VSS
Operating Temperature Range
TA
-40 to +85
Storage Temperature Range
-55 to +150
Tstg
THERMAL CHARACTERISTICS
Characteristics
Thermal !'leslstance
Ceramic Oual-In-Line
Plastic Oual-In-Line
Plastic Chip-Carrier

Unit
V
V
mA
°C
°C

Symbol

Velue

Unit

8JA

50
100
70

°C/W

This device contains circuitry to protectthe
inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions betaken to
avoid application·of any voltage higher than
maximum rated voltages to this high-impedance circuit. For proper operation it is
recommended that Vln and V. o• be constrained to the range Vss S (Vln or V.o.) s
Voo. Leakage currents are reduced and
reliability of operation is enhanced if unused
inputs are tied to an appropriate logic
voltage level (e.g., either Vss or Voo).

DC ELECTRICAL CHARACTERISTICS (VDO=5 Vdc ± 10%, VSs=O Vdc, TA=OoC to 70°C, unless otherwise noted)
Symbol
Parameter
Min
Max
0.1
Output Voltage II Load:S 10 ,.AI
VOL
VOO-O.l
VOH
Output High Voltage
4.1
Ii Load = -1.6 mAl ADO-A07
VOH
VDO
Ii Load = -0.2 mAl PAO-PA7, PCO-PC7
4.1
VOH
VOO
II Load = -0.36 mAl PBO-PB7
4.1
VOH
VOD
Output Low Voltage
IiLoad= 1.6 mAl ADO-AD7, PBO-PB7
0.4
VOL
VSS
0.4
Ii Load = 0.8 mAl PAO-PA7, PCO-PC7
VOL
VSS
0.4
Ii Load = 1 mAl IRQ
VOL
VSS
Input High Voltage, ADO-AD7, AS, OS, R/Vii, cr, PAO-PA7, PBO-PB7, PCO-PC7
VIH
VOD 2.0
VDD
VOD-O.B
RESET
VIH
VDD
Input Low Voltage (All Inputs)
O.B
VIL
VSS
Quiescent Current - No de Loads
(All Ports Programmed as Inputs, Alllnputs=VDD - 0.2 V)
160
100
Total Supply Current
(All Ports Programmed as Inputs, CE= VIL, teye= 1 ,.s)
3
100
±1
Input Current, cr, AS, R/Vii, OS,
lin
Hi-Z State Leakage, ADO-AD7, PAD-PA7, PBO-PB7, PCO-PC7
±10
ITSL

Unit
V
V

V

V
V
V
,.A
mA

m:sn

,.A
,.A

VDD
TTL Equivalent

CMOS Equivalent

Test
Point o--~~-~~-I+---'

C=50 pF; All Ports
'" 130 pF; ADo-AD7
for VDD=5 V ± 10%

C

Pin
ADO-AD7
PAO-PA7, PCO-PC7
PBO-PB7

Rl
2.55k
L)k

11.5k

R2
2Jk
4.32k
2.1k

TestPoint~

For all outputs exceptiRO

C

I

..L
C

_

4.02k

130 pF
50 pF
50 pF

90pF

Fig. 2 - Equivalent tast loads.

5-68

CDP6823
BUS TIMING IVDD;5 Vde ± 10% VSS;O Vde TA;O° to 70°C, unless otherwise notedl
Ident.
Number
Cycle Time

2

Pulse Width, DS/E Low or

3

Pulse Width, DS/E High or
Input Rise and Fall Time

4

Symbol

Min

Max

Unit

teye

1000

de

ns

FID/WR High

PWEL

300

Rl5/WR

PWEH

325

-

nS

-

ns

Characteristics

1

Low

13

R/W Hold Time
R/Vii and ct Setup Time Before DS/E

15

Chip Enable Hold Time

8

ns

tRWH

10

30
-

tRWS

25

-

ns

tCH

0

. 100

ns

t r , tf

ns

18

Read Data Hold Time

tDHR

10

21

Write Data Hold Time

tDHW

0

24

Muxed Address Valid Time to ASI ALE Fall

tASL

25

-

ns

25

Muxed Address Hold Time

tAHL

20

-

ns

26

Delay Time DS/E to ASI ALE Rise

tASD

60

-

ns

27

Pulse Width, ASI ALE High

PWASH

170

-

ns

28
30

Delay Time, ASI ALE to DS/E Rise

tASED

60

-

ns

Peripheral Output Data Delay Time from DS/E or RD

tDDR

20

240

ns

31

Peripheral Data Setup Time

tDSW

220

-

ns

ns
ns

NOTE: DeSIgnations E, ALE, RD, and WR refer to sIgnals from alternatIve mIcroprocessor SIgnals.

AS

DS
(I)

(I)
.....

::::>~
II:I w

I-::C

-Il..

11:1_

10:

""w
Il..
R/W

~---(31l----.r

ADO·
AD7
WRITE

~r-~~r-----------~=2~~
Write Data Valid

ADO·
AD7
READ

Read Data
Valid

NOTE: VHIGH;VDD-2 V, VLOW;0.8 V, for VDD;5 V ±10%

Fig. 3 - Bus timing diagram.

5-69

CDP6823

ALE (Address Latch Enable)
(AS Pin)

RD (Read Output Enable)
(oS Pin)

WR (Write Enable)
(R/W Pin)

CE (Chip Enable)

ADO-AD7
(Address/Data B,;;U,;;;S)_ _ _ _ _ _ _ _ _ _ _

-<

Read Data
Valid

Fig. 4 - BUB READ timing competitor multiplexed bus.

ALE (Address Latch Enable)
(AS Pin)

RD (Read Output Enable)
(oS Pin)

iiiiR

(Write Enable)
(R/VV Pin)

ADO-AD7
(Address/Data::.,::B.::;us;::.)_ _ _ _ _ _ _ _ _ _ _

<1

NOTE: VHIGH=VDD-2 V. VLOW=O.B V. for VDD=5 V

Write Data
Valid

± 10%

Fig. 5 - Bus WRITE timing competitor multiplexed bus.

5-70

CDP6823
CONTROL TIMING (VDD

= 5.0Vdc :I: 10%, Vss = OVdc, TA =OOC to 700 C)
PARAMETER

SYMBOL

MIN

MAX

UNIT

1.0

I's

1.0

I's

Delay, CA1 (CB1) Active Transition to CA2 (CB2) High (Output Mode 0)

tc2

-

Delay, CA2 Transition from Positive Edge of AS (Output Modes 0 and1)

tA2

-

1.0

I's

Delay, C02 Transition from Negative Edge of AS (Output Modes 0 and 1)

tB2

-

1.0

I's

CA2/CB2 Pulse Width (Output Mode 1)

tpw

0.5

1.5

Delay, VDD Rise to RESET High

tRLH

1.0

Pulse Width, RESET

tRW

1.0

-

Interrupt Response (Input Modes 1 and 3)

tlRQR

CA2

9

~------------------------------

AS

IR_O_R
_____________t_

rna

I'S

CA2/CB2 DELAY (OUTPUT MODE 1)

IRO RESPONSE (INPUT MODES 1 AND 3)

CA1--Vb

I'S
I's

~--CA2/CB2
CA2/CB2 DELAY (OUTPUT MODEOl

CA1/CBl ,

_ _ _ _ _ _ _ _ _ _ _ __

~

VDD
OV

tC2

en
en ....

=>j:il!

COw
....
:;
-a...
CO_

'=

"'w
a...

CA2/CB2

AS

Fig. 6 - Control timing diagrams.

5-71

CDP6823
GENERAL DESCRIPTION
The CDP6823, CMOS parallel Interface (CPI), contains 24
individual bidirectional I/O lines configured In three 8-bit
ports. The 15 internal registers, which control the mode of
operation and contain the status of the port pins, are
accessed via an 8-blt multiplexed address/data bus. The
lower four address .bits (ADO-AD3) of the multiplexed
address bus determine which register Is to be accessed (see
Register Address Map shown below). The four address bits
(AD4., A05, AD6, and AD7) must be separately decoded to
position this memory map within each 256-byte address
space available via the 8-bit multiplexed address bus. For
more detailed information, refer to REGISTER DESCRIPTION.
REGISTER ADDRESS MAP

o

Port A Data, Clear CA 1 Interrupt

P1DA

Port A Data, Clear CA2 Interrupt

P2DA

2

Port A Data

PDA

3

Port B Data

PDB

4

Port C Data

PDC

5

Not Used

-

6

Data Direction Register for Port A

DDRA
DDRB

7

Data Direction Register for Port B

8

Data Direction Register for Port C

DDRC

9

Control Register for Port A

CRA

A

Control Register for Port B

CRB

B

Pin Function Select Register for Port C

FSR

C

Port B Data, Clear CB1 Interrupt

P1DB

D

Port B Data, Clear CB2 Interrupt

P2DB

E

Handshakellnterrupt Status Register

HSR

F

Handshake Over-Run Warning Register

HWR

The CPI is implemented with the MOTEL circuit which
allows direct Interface with either of the two major multiplexed microprocessor bus types. A detailed description of
the MOTEL circuit is provided in the MOTEL section.
6800 Family
MPU Signals

Competitor Type
MPU Signals

Three data direction registers (DDRs), one for each port,
determine which pins are outputs and which are inputs. A
logic zero on a DOR bit configures its associated pin as an
input; and a logic one configures the pin as an output. Upon
reset, the OORs are cleared to logic zero to configure all
port pins as Inputs.
.
Actual port data may be read or written via the port data
registers (PDA, POB, and POC). Ports A and B each have
two additional data registers (P1 DA and P2DA - P1 DB and
P2DB) which are used to clear the associated handshake/interrupt status register bits (HSA 1 and HSA2 - HSB1
and HSB2), respectively. Port A may also be configured as
an 8-bit latch when used with CA 1. Reset has no effect on
the contents of the port data registers. Users are advised to
initialize the port data registers before changing any port
pin to an output.
Four pins on port C (PC4/CA1, PC5/CA2, PC6/CB1, and
PC7/CB2) may additionally be programmed as handshake
lines for ports A and B via the port C function select register
(FSR). Both ports A and B have one input-only line and one
bidirectional handshake line each associated with them.
The handshake lines may be programmed to perform a
variety of tasks such as interrupt requests, setting flags,
latching data, and data transfer requests and/or acknowledgments. The handshake functions are programmed via
con-trol registers A and B (CRA and CRB). Additional
information may be found in PIN DESCRIPTIONS,
REGISTER DESCRIPTION, or HANDSHAKE OPERATION.
MOTEL.
The MOTEL circuit is a concept that permits the C0P6823
to be directly interfaced with different types of multiplexed
bus microprocessors without any additional external logic.
For a more detailed description of the multiplexed bus, see
MULTIPLEXED BIDIRECTIONAL ADDRESS/DATA BUS
(ADO-AD7). Most multiplexed microprocessors use one of
two synchronous buses to interface peripherals. An industry
standard bus structure is now available.
The MOTEL circuit is built into peripheral and memory ICs
to permit direct connection to either type of bus. The
MOTEL concept is shown logically in Fig. 7.
The microprocessor type is automatically selected ~ the
MOTEL circuit through latching the state of the DS/RU pin
with AS/ALE. Since OS is always low during AS and"Rl5 is
always high during ALE, the latch automatically indicates
with which type microprocessor bus it is interfaced.

CDP6823
Pin Signals

Competitive Bus
D

AS

ALE

AS

Internal
Signals

Q

C

0-

Motorola
Bus

DS, E, orcf>2

DS

Read Enable

R/W

R/W

Write Enable

Fig. 7 - Functional diagram of MOTEL circuit.

5-72

CDP6823
PIN DESCRIPTION
The following paragraphs contain a brief description of the
input and output pins. References (if applicable) are given
to other paragraphs that contain more detail about the
function being performed.
Multiplexed Bidirectional Address/Data Bus (ADO-AD7)
Multiplexed bus processors save pins by presenting the
address during the first portion of the bus cycle and using
the same pins during the second portion ofthe bus cycle for
data. Address-then-data multiplexing does not slow the
access time of the CDP6823 since the bus reversal from
address to data is occurring during the internal register
access time.
The address must be valid tASL prior to the fall of AS/ALE at
which time the CDP6823 latches the address present on the
ADO-AD3 pins. Valid write data must be presented and held
stable during the latter portion of the DS or WR pulses, In a
read cycle, the CDP6823 outputs eight bits of data during
the latter portion of the DS or RD pulses, then ceases
driving the bus (returns the output drivers to high impedance) tDHA hold time after DS falls in this case of MOTEL
or RD rises in the other case.
Address Strobe (AS)
The address strobe input pulse serves to demultiplex the
bus. The falling edge of AS or ALE causes the addresses
ADO-AD3 to be latched within the CDP6823. The automatic
MOTEL circuit in the CDP6823 also latches the state of the
DS pin with the falling edge of AS or ALE.
Data Strobe or Read (OS)
The DS input pin has two interpretations via the MOTEL
circuit. When generated by a Motorola microprocessor, DS
is a positive pulse during the latter portion of the bus cycle,
and is variously called DS (data strobe), E (enable), or ~2
(~2 clock). During read cycles, DS or RD signifies the time
that the CPI is to drive the bidirectional bus. In.write cycles,
the trailing edge of DS or rising edge of WR causes the
parallel interface to latch the written data present on the
bidirectional bus.
The second MOTEL interpretation of DS is that of RD,
MEMR, orl7OR originating from a competitor-type micro
processor. In this case, DS identifies the time period when
the parallel interface drives the bus with read data. This
interpretation of DS is also the same as an output-enable
signal on a typical memory.

Chip Enable (eE)
The CEinput signal must be asserted (low) for the bus cycle
in which the CDP6823 is to be accessed. CE is not latched
and must be stable prior to and during DS'(in the 6805 mode
of MOTEL) and prior to and during RD and WR (in the
competitor mode of MOTEL). Bus cycles which take place
without asserting"CE cause no actions to take place within
the CDP6823. When ITis high, the multiplexed bus output
is in a high-impedance state.
When CE is high, all data, DS, and RM inputs from the
microprocessor are disconnected within the CDP6823. This
permits the CDP6823 to be isolated from a powered-down
microprocessor.
Reset (RESET)
The RESET input pin is an active-low line that is used to
restore all register bits, except the port data register bits, to
logical zeros. After reset, all port lines are configured as
inputs and no interrupt or handshake lines are enabled.
Interrupt Request (IRQ)
The fRO output line is an open-drain active-low signal that
may be used to interrupt the microprocessor with a service
request. The "open-drain" output allows this and other
interrupt request lines to be wire ORed with a pullup
resistor. The iRQ line is low when bit 7 of the status register
is high. Bit 7 (IRQF) of the handshake/interrupt status
register (HSR) is set if any enabled handshake transition
occurs; and its associated control register bit is set to allow
interrupts. Refer to INTERRUPT DESCRIPTION or HANDSHAKE OPERATION for additional information.
Port A, Bidirectional 110 Lines (PAO-PA7)
Each line of port A, PAC-PA7, is individually programmable
as either an input or output via its data direction register
(DDRA). An I/O pin is an input when its corresponding DDR
bit is a logic zero and an output when the DDR bit is a logic
one. See Fig. 8 for typical I/O circuitry and Table 1 for I/O
operation.
TABLE 1 -

The second interpretation of RIW is as a negative write
pulse, WR, 1Iiil:fiilW, andTlOWfrom competitor-type micro
processors. The MOTEL circuit in this mode gives the R/W
pin the same meaning as the write (W) pulse on many
generiC RAMs.

= ....

I-:J:

The MOTEL circuit, within the CDP6823,Iatches the state of
the DS pin on the falling edgeof AS/ALE. When the modeof
MOTEL is desired DS must be low during AS/ALE, which is
the case with the multiplexed bus microprocessors. To
insure the competitor mode of MOTEL, the DS pin must
remain high during the time AS/ALE is high.
Read/Write (R/W)
The MOTEL circuit treats the R/W input pin in one of two
ways. The microprocessor is connected, RM is a level
which indicates whether the current cycle is a read or write.
A read cycle is indicated with a high level on R/Wwhile DS is
high, whereas a write cycle is a low on RM while DS is high.

PORT DATA REGISTER ACCESSES (ALL PORTSI

en
en ....
::I~

R/Iii

DDR
Bit

0

0

The I/O pin is in input mode. Data is written into the
output data latch.

0

1

Data is written into the output data latch and output to the I/O pin.

1

0
1

The state of the I/O pin is read.

1

Results

The 1/ 0 pin is in an output mode. The output
data latch is read.

There are three data registers associated with port A: PDA,
P1 DA, and P2DA. P1 DA and P2DA are accessed when
certain handshake activity is desired. See HANDSHAKE
OPERATION for more information.
Data written to the port A data register, PDA, is latched into
the port A output latch regardless of the state of the DDRA.
Data written to P1 DA or P2DA is ignored and has no affect
upon the output data latch or the I/O lines. An MPU read of
port bits programmed as outputs reflect the last value
written to the PDA register. Port A pins programmed as
inputs may be latched via the handshake line PC4/CA 1 (see

5-73

-a...
='a:
.......
a...

CDP6823

To
And
From

CPU

Fig. 8 - Typical port liD circuitry.

HANDSHAKE OPERATION) and latched input data may be
read via any of the three port A data registers. If the port A
input latch feature is not enabled. an MPU read of any portA
data register reflects the current status of the port A input
pins if the corresponding DORA bits equal zero. Reset has
no effect upon the contents of the port A data register;
however. all pins will be placed In the input mode (all DORA
bits forced to equal zero) and all handshake lines will be
disabled.
Port B Bidirectional 1/0 Lines (PBO-PB7)
Each line of port B. PBO-PB7. is individually programmable
as either an input or an output via its data direction register
(DDRB). An 1/0 pin is an input when its corresponding DDR
bit is a logic zero and an output when the DDR bit is a logic
one.
There are three data registers associated with port B: PDB.
P1 DB. and P2DB. PDB is used for simple port B data reads
and writes. P1 DB and P2DB are accessed when certain
handshake activity is desired. See HANDSHAKE OPERATION for more information.
Data written to PDB or P1 DB data register is latched into the
port B output latch regardless of the state of the DDRB. An
MPU read of port bits programmed as outputs reflect the
last value written to a port B data register. An MPU read of
any port B register reflects the current status of the input
pins whose DDRB bits equal zero. Reset has no effect upon
the contents ofthe port B data register; however. all pins will
be placed in the input mode (all DDRB bits forced to equal
zero) and all handshake lines will be disabled.
Port C, Bidirectional I/O Lines (PCO-PC3)
Each line of port C. PCo-PC3. is individually programmable
as either an input or an output via its data direction register
(DDRC). An 1/0 pin is an input when its corresponding DDR
bit is a logic zero and an output when the DDR bit is a logic
one. Port C data register (PDC) is used for simple port C
data reads and writes.
Data written into PDC is latched into the port C data latch
regardless of the state of the DDRC. An MPU read of port C
bits programmed as outputs reflect the last value written to
the PDC register. An MPU read ofthe portC register reflects

the current status of the corresponding input pins whose
DDRC bits equal zero. Reset has no effect upon the
contents of the port C data register; however. all pins will be
placed in the input mode (all DDRC bits forced to equal
zero) and all handshake lines will be disabled.
Port C Bidirectional I/O Line or Port A Input Handshake
Line (PC4/CA1)
This line may be programmed as either a simple port CliO
line or as a handshake line for port A via the port C function
select register (FSR). If programmed as a port C I/O pin.
PC4/CA1 performs as described in the PCO-PC3 pin
description. If programmed as a port A handshake line.
PC4/CA 1 performs as described in HANDSHAKE OPERATION.
Port C BidirectionalI/O Line or Port A Bidirectional
Handshake Line (PCS/CA2)
This line may be programmed as either a simple port CliO
line or as a handshake line for port A via the port C function
select register (FSR). If programmed as a port C I/O pin.
PC5/CA2 performs as described in the PCO-PC3 pin
description. If programmed as a port A handshake line.
PC5/CA2 performs as described in HANDSHAKE OPERATION.
Port C Bidirectional 1/0 Line or Port B Input Handshake
Line (PC6/CB1)
This line may be programmed as either a simple port C I/O
line oras a handshake line for port Bvia the portC function
select register (FSR). If programmed as a port C I/O pin.
PCS/CB1 performs as described in the PCO-PC3 pin
description. If programmed as a port B handshake line.
PCS/CB1 performs as described in HANDSHAKE OPERATION.
Port C BidirectionalI/O Line or Port B
Bidirectional Handshake Line (PC7/CB2)
This line may be programmed as either a simple port C I/O
line or as a handshake line for port B via the port C function
select register (FSR). If programmed as a port C I/O line.
PC7/CB2 performs as described in the PCO-PC3 pin
description. If programmed as a port B handshake line.
PC7/CB2 performs as described in HANDSHAKE OPERATION.

5-74

CDP6823
HANDSHAKE OPERATION
Up to four port C pins can be configured as handshake lines
for ports A and B (one input-only and one bidirectional line
for each port) via the port C function select register (FSR).
The direction of data flow for the two bidirectional handshake lines (CA2 and CB2) is determined by bits 5 and 7,
respectively, of the port C data direction register (DDRC).
Actual handshake operation is defined by the appropriate
port control register (CRA or CRB).
The control registers allow each handshake line to be
programmed to operate in one of four modes. CA2 and CB2
each have four input and four output modes. For detailed
information, see Tables 2 and 3.

four different modes as defined by the control registers (see
Table 2). A bit in the handshake/interrupt status register
(HSR) is set to a logic one on an active transition of any
handshake line programmed as an input. Modes 0 and 1
define a negative transition as active; modes 2 and 3 define a
positive transition as active. If modes 1 or 3 are selected on
any input handshake line then the active transition of that
line results in the IRQF bit of the HSR being set to l!..!Qgic
one and causes the interrupt line (IRQ) to go low. IRQ is
released by clearing the HSR bits that are input handshake
lines which have interrupts enabled.
If an active transition occurs while the associated HSR bit is
set to a logic one, the corresponding bit in the handshake
warning register (HWR) is set to a logic one indicating that
service of at least one active transition was missed. An HWR
bit is cleared to a logiC zero by first acceSSing the appropriate
port data register, to clear the appropriate HSR status bit,
followed by a read of the HWR.

A summary of the handshake modes is given in the input
and output sections that follow. All handshake activity is
disabled by reset.
Input
Handshake lines programmed as inputs operate in any of

TABLE 2 - INPUT HANDSHAKE MODES
Control
Mode Register Bits*
0

00

Active
Edge
-Edge

1

01

-Edge

Set high on
active edge.

Goes low when corresponding
status flag in HSR goes high.

2

10

+ Edge

Set high on
active edge.

Disabled

3

11

+ Edge

Set high on
active edfle.

Goes low when corresponding
status flag in HSR goes high.

* Cleared to logIC zero on

Status Bit
In HSR
Set high on
active edge.

iRQ Pin
Disabled

reset.

en
en ....

::::Ia'!l

=w

TABLE 3 - OUTPUT HANDSHAKE LINES (CA2 AND CB2 ONLYI

.... ::c

=-a..

-a..

Mode

Control
Register
CRA(BI
Bits
3 and 4*

0

Ia:

COw

00

Handahake Line Set High
Handshake set high on active
transition of CAl input.

Handshake Line Cleared Low
Read of PlDA or a read of P2DA
while HSA1 is cleared.

1

01

Handshake set high on active
transition of CB 1 input.
High on the first positive
(negativel transition of AS
while CA2 (CB2) is low.

2

10
11

Never
Always

Write of port B PlDB or write
of P2DB while HSB1 is cleared.
Low on the first positive
(negativel transition on AS 101lowing a read (writel 01 port
A(B) data registers PlDAIB) or
P2DAIBI.
Always
Never

3

* Cleared to logIC zero on reset.

5-75

Default
Level
High

High

Low
High

CDP6823
'Input Latch
Port A input-only handshake line (PC4/CA1) can be
programmed to function as a latch enable for port A input
dataviaCA1 LE (bit2 ofCRA).lfCA1 LE isprogrammedtoa
logic one, an active transition of PC4/CA 1 will latch the
current status of the port A input pins into all three port A
data registers (PDA, P1DA, and P2DA). When CA1 LE is
enabled, port A and PC4/CA 1 function as an 8-bit transparent latch; that is, if the HSA 1 bit in the HSR is a logic zero
then a read of any portA register reflects the current'state of
the port A input pins and corresponding bits of the output
data latch for port A output pins. If HSA1 is a logic one, a
read of any port A data register reflects the state of the port
A input pins when HSA 1 was set and the corresponding bits
of the port A output data latch for port A output pins.

REGISTER DESCRIPTION
The CDP6823 has 15 registers (see Fig. 1) which define the
mode of operation and status of the port pins. The following
paragraphs describe these registers.
Register Names:
Control Register A (CRA)
Control Register B (CRB)
Register Addresses:
$9 (CRA)
$A (CRB)
Register Bits:

Further transitions of PC4/CA 1 result only in setting the
HWA1 bitin the HWR and do not relatch data into the portA
registers. Latched data is released only by clearing HSA 1 in
the HSR to a logic zero (HSA 1 is cleared by reading P1 DA).
Output
Each bidirectional handshake line programmed as an
output by the DDRC operates in one of four modes as
described in Table 3. Modes 2 and 3 force the output
handshake lineto reflect the state of bit4 in the appropriate
control register.

$9
$A

7

6

5

x

x

X

X

X

X

4

3

CA2
Mode

CB2
Mode

o

2

CAl
lE

CAl
Mode

X

Mode

CBI

Purpose:
These two registers control the handshake and interrupt
activity for those pins defined as handshake lines by the
port C function select register (FSR).

In modes 0 and 1, PC5/CA2 is forced low during the cycle
following a read of P1 DA or a read of P2DA while HSA1 is
cleared. PC7/CB2 is forced low during the cycle following a
write to P1 DB or a write to P2DB while HSB1 is cleared.
Because of these differences, port A is the preferred input
port and port B is the preferred output port.

Description:
CA2 and CB2 are programmed as inputs or outputs via the
associated DDRC bits. Each handshake line is controlled by
two mode bits. Bit 2 of CRA enables the Port A latch for an
active CA 1 transition. Table 2 describes the input handshake
modes (CA1, CB1, CA2, CB2) and Table 3 describes the
output handshake modes for CA2 and CB2.

In mode 0, PC5/CA2 (PC7ICB2) is set high by an active
transition of PC4/CA1 (PC6/CB1). In mode 1, PC5/CA2
(PC7/CB2) is set high in the cycle following the cycle in
which PC5/CA2 (PC7/CB2) goes low. Mode 1 forces a lowgoing pulse on PC5/CA2 (PC7/CB2) following a read
(write) of P1 DA (P1 DB) or P2DA (P2DB) that is approximately one cycle time wide.

Register Names:
Port A Data Registers (PDA, P1DA, P2DA)

When entering an output handshake mode for the first time
after.a reset, the handshake line outputs the default level as
listed in Table 3.

Register .Addresses:
$2 (PDA), $0 (P1DA), $1 (P2DA)
Register Bits:
765432

0

I Bit 7 I Bit 6 I Bit 5 I Bit 4 I Bit 3 I Bit 2 I Bit I I Bit 0 I
INTERRUPT DESCRIPTION
The CDP6823 allows an MPU interrupt request (IRQ low)
via the input handshake lines. The input handshake line,
operating in modes 1 or3 as defined by the control registers
(CRA and CRB), causeslAO" to go low when IRQF (interrupt
flag) in the HSR is set to a logic one.lAO" is released when
IRQF is cleared. See Handshake/Interrupt Status Register
underREGISTER DESCRIPTION for additional information.

Purpose:
These three registers serve different purposes. PDA is used
to read input data and latch data written to the port A output
pins. P1DA and P2DA are used to read input data and to
affect handshake and status activity for PC4/CA 1 and
PC5/CA2. If enabled, port A input data may be latched into
the three port A data registers on an active PC4/CA1
transition as described in HANDSHAKE OPERATION.

5-76

CDP6823
Description:
Data written into PDA is latched into the port A output latch
(see Fig. 3) regardless of the state of DORA. Output pins, as
defined by DORA, assume the logic levels of the corresponding bits in the PDA output latch. The PDA output
latch allows the user to read the state of the port A output
data. If the input latch is not enabled, a read of any port A
data register reflects the current state of the port A input
pins as defined by DORA and the contents of the output
latch for output pins. Writes into P1DA or P2DA have no
effect upon the output pins orthe output data latch. Users
are recom mended to initial ize the port A output latch before
changing any pin to an output via the DORA.
MPU accesses of P1 DA or P2DA are primarily used to affect
handshake and status activity. A summary of the effects on
the status and warning bits of port A data register accesses
is given in Table 4. For more information, see HANDSHAKE
OPERATION and Control Register A (CRA) under REGISTER DESCRIPTION. Reset has no effect upon the
contents of any port A data register.
Register Names:
Port B Data Registers (PDB, P1 DB, P2DB)
Register Addresses:
$3 (PDB), $C (P1 DB), $0 (P2DB)
Register Bits:
7

6

5

4

3

I Bit 7 I Bit 6 I Bit 5 I Bit 4 I Bit 3

2
Bit 2

Purpose:
These three registers serve different purposes. The Port B
data registers are used to read input data and to latch data
written to the port B output pins. Writes to POB and P1 DB
affect the contents of the output data latch while writes to
P2DB do not affect the output data latch. P1 DB and P2DB
accesses additionally affect handshake and status activity
for PC6/CB1 and PC7/CB2.
Description:
Data written into PDB and P1 DB port B registers is latched
into the port B output latch (see Fig. 3) regardless of the
state of DDRB. Output pins, as defined by DDRB, assume
the logic levels of the corresponding bits in the port B
output latch. Reads of any port B data registers reflect the
contents of the output data latch for output pins and the
current state of the input pins (as determined by DDRB).
Users are recommended to initialize the port B output latch
before changing any pin to an output via the DDRB.
MPU accessesofP10B orP2DB are primarily used to affect
handshake and status activity. A summary of the effects on
status and warning register bits of port B data register
accesses is given in Table 5. For more information, see
HANDSHAKE OPERATION or Control Register B (CRB)
under REGISTER DESCRIPTION. Reset has-no effect upon
the contents of any port B data register.

'0

Bit 1

I Bit '0 I

en
en-l
::I~

=w
='=

TABLE 4 - SUMMARY OF EFFECTS ON HANDSHAKE STATUS, WARNING BITS,
AND OUTPUT LATCH BY PORT A DATA REGISTER ACCESSES

....
::z::
-&:I..

CICIw

Register
Accessed

Output Latch
HSR Bit

Handshake Reaction

HWR Bit

Read

Write

PDA

None

None

None

Yes

Yes

PlDA

HSAl cleared
to a logic

CA2 goes low if output modes
'0 or 1 are selected in the CRA.

Yes

No

zero.

HWAl loaded
into buffer
latch.

HSA2 cleared
to a logic
zero.

HWA210aded
into buffer
latch.

CA2 goes low if output modes

Yes

No

P2DA

'0 or 1 are selected in the CRA.

TABLE 5 - SUMMARY OF EFFECTS ON HANDSHAKE STATUS, WARNING BITS,
AND OUTPUT LATCH BY PORT B DATA REGISTER ACCESSES
Register
Accessed

Output Latch
HSR Bit

HWR Bit

Handshake Reaction

PDB

None

None

None

PlDB

HSBl cleared
to a logic

CB2 goes low if output modes
'0 or 1 are selected in the CRB.

zero.

HWBl loaded
into buffer
latch.

HSB2 cleared
to a logic
zero.

HWA210aded
into buffer
latch.

P2DB

CB2 goes low if output modes

'0 or 1 are selected in CRB.

5-77

Read

Write

Yes
Yes

Yes
Yes

Yes

No

&:I..

CDP6823
Purpose:
The port C pin function select register defines whether the
multifunction port C pins are to operate as "normal" port C
lines or as handshake lines.

Register Name:
Port C Data Register (PDC)
Register Address:

$4
Register Bits:
765432

I Bit 7 I

Bit 6

I Bit 5

0

I Bit 4 I Bit 3 I Bit 2 I Bit 1 I Bit 0 I

Purpose:
The port C data register (PDC) is used to read input data
and to latch data written to the output pins.
Description:
Data is written into the port C output latch (see Fig. 3)
regardless of the state of DDRC. Any port C pin defined as a
handshake line by the port C function select register (FSR)
is not affected by PDC. Output pins, as defined by DDRC,
assume logic levels of the corresponding bits in the port C
output latch. A read of PDC reflects the contents of the
output latch for output pins and the current state of the
input pins (as reflected in the DDRC). Reset has no effect
upon the contents of PDC. Users are recommended to
initialize the port C output data latch before changing any
pin to an output via the DDRC.

Description:
A log ic zero in any FSR bit defines the correspondi ng port
C pin as a "normal" I/O pin. A logiC one in any valid FSR bit
defines the corresponding port C pin as a handshake line.
Pins defined as handshake lines function according to the
contents of control register A (CRA) or control register B
(CRB). The port C data direction register (DDRC) is valid
regardless of FSR contents for all pins except PC4/CA 1 and
PCS/CB1. Transitions on port C pins not defined as
handshake pins do not effect the handshake/interrupt
status register. Reset clears all FSR bits to a logic zero.
Users are recommended to initialize the data direction and
control registers before modifying the FSR.

Register Name:
Handshake/Interrupt Status Register (HSR)
Register Address:
$E
Register Bits:
7

Register Bits:
765432

Bit 6

I XX

5
XX

43210

XX

I HSB21 HSA21 HSBl IHSAll

Purpose:
The handshake interrupt status register is a read-only flag
register that may be used during a polling routine to
determine if any enabled input handshake transition, as
defined by the control register (CRA and CRB), has
occurred.

Register Address:
$6 ($7) ($8)

I Bit 7 I

6

IIRQF

Register Name:
Data Direction Register for Port A (B) (C)

0

I Bit 5 I Bit 4 I Bit 3 I Bit 2 I Bit 1 I Bit 0 I

Purpose:
Each of the three data direction registers (DORA, DDRB,
and DDRC) define the direction of data flow ofthe port pins
for ports A, B, andC.
Description:
A logic zero in a DDR bit places the corresponding port pin
in the input mode. A logic one in a DDR bit places the
corresponding pin in the output mode. Any port C pins
defined as bidirectional handshake lines also use the port C
DDR (DDRC). Input-only handshake lines are not affected
by DDRC. Reset clears all DDR bits to logic zero configuring
all port pins as inputs. The DDRs have no write-inhibit
control over the port data output latches. Data may be
written to the port data registers even though the pins are
configured as inputs.

Description:
If an enabled input handshake transition occurs then the
apPr:2E!iate HSR bit (HSB2, HSA2, HSB1, or HSA1) is set.
The rnQ flag bit (bit 7, IRQF) is set when one or more of the
HSR bits 0-3 and their corresponding control register bits
are set to a logic one as shown in the following equation:
Bit 7=IRQF=[HSB2·CRB2(3»)+[HSA2.CRA2(3»)
+[HSB1.CRBl (0»)+[HSA1.CRAl (0»)
The numbers in ( ) indicate which bit in the control register
enables the interrupt.
Handshake/interrupt status register bits are cleared by
accessing the appropriate port data register. The following
table lists the HSR bit and the port data register that must be
accessed to clear the bit.
To Clear
Access
HSR Bit
Register
HSB2..
. ............... P2DB
HSA2 ............................. P2DA
HSBl ................
. ..... P1DB
HSA1 ............................. P1DA

Register Name:
Port C Pin Function Select Register (FSR)
Register Address:
$B
Register Bits:
7

6

5

4

3

ICFB21 CFBl I CFA21 CFAl I XX

o

2

xx

xx

Reset clears all handshake/interrupt status register bits to a
logic zero.

xx

5-78

CDP6823
Register Name:
Handshake Warning Register (HWR)

without affecting the other three handshake warning
register bits. The upper four bits, HWR4-HWR7, always read
as logic zeros. If a port data register is not read before
reading the handshake warning register, then the handshake
warning register bits will remain unaffected. Reset clears all
HWR bits to a logic zero.

Register Address:
$F

Register Bits:
7

I XX I

6

5

XX

XX

4

3

2

1

0

Recommended status register handling sequence:
1. Read status
register

Purpose:
The warning register is a read-only flag register that may be
used to determine if a second attempt to set a handshake/interrupt status register bit has been made before the
original had been serviced.
Description:
Each bit in the handshake/interrupt status register, except
IRQF, has a corresponding bit in the handshake warning
register. If an attempt is made to set a bit in the
handshake/interrupt status register that is already set, then
the corresponding bit in the handshake warning register is
also set. An attempt is the occurrence of any enabled input
handshake transition as defined by the control registers.
A handshake warning register bit is cleared by first reading
the appropriate data register then reading the handshake
warning register. Reading the data register (either P1DA,
P2DA, P1 DB, or P2DB) loads a buffer latch with the proper
bit in the handshake warning register (HWA1, HWA2,
HWB1, and HWB2, respectively). The next read of the
handshake warning register clears the appropriate bit

(User determines which if any
enabled handshake transition
occurred)

2. Read/write port (Clears associated status bit and
data indicated by latches appropriate warning
status register
register bit in the buffer latch)
3. Read warning
register

(Latched warning bit is cleared
and the remaining bits are
unaffected)

TYPICAL INTERFACING
The CDP6823 is best suited for use with microprocessors
which generate an address-then-data-multiplexed bus. Fig.
9 shows the CDP6823 in a typical CMOS system that uses
the CDP6805E2 CMOS MPU. Other multiplexed microprocessors can be used as easily.
A single-chip microcomputer (MCU) may be interfaced
with 11 port lines as shown In Fig. 10. This interface also
requires some software overhead to gain up to 13 additional
I/O lines and the CDP6823 handshake lines.

CDP6818
Real- Time Clock
Plus RAM

I

Clock
Bus Control

NO

High Addr

~e

a..c.

Interrupt

()~

Reset

00

c

e

16K ROM

16K ROM

ICDP655161
16K ROM

en

tn ....

.....
:::I~

3

8

8

3

3

5

8

5

8

3

00 .....

5

-a..
00_

Ia:
........
a..

3

Mux Addr/Data

w'"
",8l

lCDP6551~

ICDP65516J

8

/

5

ChiPV
Enables

5

8

8

74HCl38
Decoder

3

8

3

8

8

An 8-Chip CMOS Microprocessor System Includes:
8-Bit Microprocessor
6K Bytes of ROM
162 Bytes of RAM
64 Parallel 1/ 0 Pins
RTC Function

CDP6823

CDP6823

CMOS Parallel Interface

CMOS Parallel Interface

111
8

8

8

Fig. 9 - A typical CMOS microprocessor system.

5-79

1 t
8

l8

8

CDP6823
CDP6823

g

20

8

Microcomputer

Ports

ADO-AD7

a..

r-Address Strobe
Read
1::

Write

AS

CA1

DS

CB1

R/W

0

a..
VSS

CA2
CB2

CE
IRQ

RESET

r

Port
Lines

Fig. 10 - CDP6823 Interfaced with the ports of a typical single-chip microprocessor.

5-80

Port
Lines

CDP6853

Ei)HARRIS
January 1991

CMOS Asynchronous Communications
Interface Adapter {ACIA} with MOTEL Bus

Features

Pinout

• Compatible With 8-Blt Microprocessors

PACKAGE TYPES D AND E
TOP VIEW

• Multiplexed Address/Data Bus (MOTEL Bus)
• Full Duplex Operation With Buffered Receiver and Transmitter

Rrii-~I--VDD
cso-

2

Cii-:5

• Data Set/Modem Control Functions

RfS -

• Internal Baud Rate Generator with 15 Programmable Baud Rates (50
to 19,200)
• Operates at Baud Rates Up to 250,000 Via Proper Crystal or Clock
Selection
• Program-Selectable Internally or Externally Controlled Receiver Rate

4

27r-- os
2.~11RI
25r-OT

RlIC-!5
XTLr 6

24r--OS
23~ 05

XTLD -

22'- D4
2.
0'

1!TlI ~-.
TIO 10

r-

2D~D2
19 -ADI

15TII-1I

.a-ADO

RaD- 12
CE- 13

1'Tf--lIIW

Vss- 14

15 -AS

16-~

• Programmable Word Lengths, Number of Stop Bits, and Parity Bit
Generation and Detection
• Programmable Interrupt Control
• Program Reset
• Program-Selectable Serial Echo Mode
• Two Chip Selects
• One Chip Enable
• Single 3V to 6V Power Supply
• Full TTL Compatibility

en
en .....

• 4MHz, 2M Hz, or 1MHz Operation
(CDP6853-4, CDP6853-2, CDP6853, Respectively)

::::I~

a:I..,

....
:c
-D..

.=

a:I_

Description

00..,
D..

The COP6853 Asynchronous Communications Interface
Adapter (ACIA) provides an easily Implemented, program
controlled interface between 8 bit microprocessor-based
systems and serial communication data sets and
modems.
The COP6853 has an internal baud rate generator. This
feature eliminates the need for multiple component support
circuits, a crystal being the only other part required. The
Transmitter baud rate can be selected under program
control to be either 1 of 15 different rates from 50 to 19,200
baud, or at 1/16 times an external clock rate. The Receiver
baud rate may be selected under program control to be
either the Transmitter rate, or at 1/16 times an external
clock rate. The CDP6853 has programmable word lengths
of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1'12, or 2 stop
bits.
The COP6853 is designed for maximum programmed
control from the CPU, to simplify hardware implementation.
Three separate registers permit the CPU to easily select the
CDP6853 operating modes and data checking parameters
and determine operational status.

The Command Register controls parity, receiver echo
mode, transmitter interrupt control, the state of the RTS line,
receiver interrupt control, and the state of the DTR line.
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
The Status Register indicates the states of the IRQ, OSR,
and OCD lines, Transmitter and Receiver Data Registers,
and Overrun, Framing and Parity Error conditions.
The Transmitter and Receiver Data Registers are used for
temporary data storage by the CDP6853 Transmit and
Receiver circuits.
The MOTEL Bus allows interfacing to 6805 and 8085 type
multiplexed address data bus.
The CDP6853, CDP6853-2, and CDP6853-4 are capable
of interfacing with microprocessors with cycle times of
1MHz, 2MHz, and 4MHz, respectively.
The CDP6853 is supplied in 28 lead, hermetic, dual-in-line
sldebrazed ceramic (0 suffix) and in 28 lead, dual-in-line
plastic (E suffix) packages.

Copyright @ Harris Corporation 1991

File Number
5-81

1487.1

CDP6853
MAXIMUM RATINGS, Absolute-Maximum Ve/ues:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to Vss terminal) ....................................................................................-0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS •....•••••••.•••..••.....•....••.•.•••••.•••.•.....•••..•••••..••...•••••. -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ..••....•..•.•...•••••••.•••••..•.....•....•••••.....•..•....•••••......•.••••••.•. ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
ForTA=-40 to +60·C (PACKAGE TYPE E) ......•..•........•..•......................•.......•..•.••••••...••••••••••.••• 500 mW
For'TA=+60 to +85·C (PACKAGE TYPE E) •••...•.••..••••••••...••••.....••••••••••.•...•••• Derate Linearly at 8 mW/·C to 300 mW
For TA=-55 to +100· C (PACKAGE TYPE D) ........•••......•..••....••••.....•.•...•••••.•••••....•.•.••....•..•..•••••.• 500 mW
ForTA=+100 to 125·C (PACKAGE TYPE D) •••.•.••...•••••..•..••••......••••••.•••..•..•••• Derate Linearly at 8 mW/·C to 300 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ForTA=FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .•••.••••••••..•..••••..•••••......•••••.......•.... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 •..••••..•.•.•...••.•........•........•••••••••........••.•.•••.•.....•.•..••••••••.•..••••.... -55 to +125·C
PACKAGE TYPE E •.•..••..•••••••••.•.••••••••.••••.......•••...•••.•...•..•......••.••.••••...•...••.•....•••••• -40 to +85· C
STORAGE-TEMPERATURE RANGE (T...) .......••••.....••••....•........••••..•••........•....••••••••.••••••.••.. -65 to +15O"C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1132 in. (1.59 ± 0.79 mm) from case for 10 s max.
• ..•.••.••...•.......••....••••.....•••••..•.....•... +285·C

RECOMMENDED OPERATING CONDITIONS at TA = -40· to +85·C
For maximum reliability, nominal operating conditions should be selected so that operation Is always
within the following ranges:
LIMITS

CHARACTERISTIC

Min.

DC Operating Voltage Ranoe
Input Voltaoe Ranoe

UNITS

Max.
6
Voo

3
Vas

V

STATIC ELECTRICAL CHARACTERISTICS at TA=-40· to +85·C, Voo = 5 V ± 5%
CHARACTERISTIC

-

LIMITS
Typ.
50

Max.
200

1.6

-

-

mA

-1.6

-

-

mA

-

-

0.4

V

4.6

-

-

V

0.8

V

VDD
VDD

V

Min.

Quiescent Device Curr,ent
Output Low Current (Sinking): VOL =0.4 V
(00-07, TxO, RxC, RTS, OTR, IRQ)
Output High Current (Sourcing): VOH =4.6 V
(00-07, TxO, RxC, R'fS, OTR)
Output Low Voltage: ILOAD =1.6 mA
(00-07, TxO, RxC, RTS, OTR, IRQ)
Output High Voltage: 1LOAD = -1.6 mA
(00-07, TxO, RxC, RTS, OTR)
Input Low Voltage
Input High Voltage
(Except XTLI and XTLO)
(XTLI and XTLO)
Input Leakage Current: VIN =0 to 5 V
(R/W,
CSO, CS1, CE, OS, AS, CTS, RxO, oco, OSR)
Input Leakage Current for High Impedance State (00-07)
Output Leakage Current (off state): VOUT =5 V (TAO)
Input Capacitance (except XTLI and XTLO)
Output Capacitance

m,

5-82

IOD
10L
IOH
VOL
VOH
VIL
VIH

Vss
2

3
liN
hSI
IOFF
CIN
CO UT

-

-

UNITS
pA

±1

pA

± 1.2

pA
pA
pF
pF

2
10
10

CDP6853
CDP6853 INTERFACE REQUIREMENTS

D2-D7 (Data Bus) (20-25)

This section describes the interface requirements for the
CDP6853 ACIA. Fig. 1 is the Interlace Diagram and the
Terminal Diagram shows the pin-out configuration for the
CDP6853.

The 02-07 pins are the eight data lines used to transfer data
between the processor and the CDP6853. These lines are
bi-directional and are normally high-impedance except
during Read cycles when the CDP6853 is selected.
CE, CSO, CS1 (Chip Selects) (2,3,13)
The two chip select and the one chip enable inputs are
normally connected to the processor address lines either
directly or through decoders. The CDP6853 is selected
when CSO is high, CS1 is low, and CE is high.

02·07
AOD,A01

TxO

RxC
XTLI
XTLO

110
CONTROL

RxO

ADO, AD1 (Multiplexed Bidirectional Address/Data Bits)
(18,19)
Multiplexed bus processors save pins by presenting the
address during the first portion of the bus cycle and using
the same pins during the second portion for data. Addressthen-data multiplexing does not slow the access time ofthe
CDP6853 since the bus reversal from address to data is
occurring during the internal RAM access time.
The address must be valid just prior to the fall of AS/ALE at
which time the CDP6853 latches the address from ADO to
AD1. Valid write data must be presented and held stable
during the latter portion of the OS or WR pulses. In a read
cycle, the CDP6853 outputs 8 bits of data during the latter
portion of the OS or RD pulses, then ceases driving the bus
(returns the output drivers to three-state) when OS falls in
this case of MOTEL or RD rises in the other case. The
following table shows internal register select coding:
TABLE I
AD1
0

ADO
0

0

1

92CM-37024

Fig, 1 - CDP6853 Interface diagram.

MICROPROCESSOR INTERFACE
SIGNAL DESCRIPTION
RES (Re..t) (4)
During system initialization a low on the RES input will
cause a hardware reset to occur, The Command Register
and the Control Register will be cleared. The Status
Register will be cleared with the exception ofthe indications
of Data Set Ready and Data Carrier Detect, which are
externally controlled by the DSR and f5Ci5 lines, and the
transmitter Empty bit, which will be set. A hardware reset is
required after power-up.

1
1

Only the Command and Control registers are read/write.
The programmed Reset operation does not cause any data
transfer, but is used to clear bits 4 through 0 in the
Command register and bit 2 in the Status register. The
Control Register is unchanged by a Programmed Reset. It
should be noted that the Programmed Reset is slightly
different from the Hardware Reset (RES); these differences
are shown in Figs. 4, 5, and 6.
ACIAIMODEM INTERFACE
SIGNAL DESCRIPTION

RIW (ReadIWrlte) (1)
The MOTEL circuit treats the R/W pin in one of two ways.
When a 6805 type processor is connected, R/W is a level
which indicates whether the current cycle is a read or write.
A read cycle is indicated with a high level 0ILR/W while OS is
high, whereas a write cycle is a low on R/W during OS.
The s~nd JE'M~retati~ R/W is as a negative write
, and I/OW from competitor ,!lpe propulse, WR,
cessors. The MOTEL circuit in this mode gives R/W pin the
same meaning as the write (W) pulse on many generic
RAMs.
IRQ (Interrupt Request) (26)
The IRQ pin is an interrupt outputfrom the interrupt control
logic. It is an open drain output, permitting several devices
to be connected to the commonlRtl'microprocessorinput.
Normally a high level, TIm goes low when an interrupt
occurs.

0
1

Wrlta
Read
Transmit Data
Receiver Data
Register
R~ster
Programmed Reset
Status Register
(Data is "Don't
Care'1
Command R~ster
Control Register

XTLI, XTLO (Crystal Pins) (8,7)
These pins are normally directly connected to the external
crystal (1.8432 MHz) used to derive the various baud rates
(see "Generation of Non-Standard Baud Rates"). Alternatively, an externally generated clock may be used to drive
the XTLI pin, in which case the XTLO pin must float. XTLI is
the input pin for the transmit clock.
TxD (Transmit Data) (10)
The TxD output line is used to transfer serial NRZ
(nonreturn-to-zero) data to the modem. The LSB (least
significant bit) of the Transmit Data Register is the first data
bit transmitted and the rate of data transmission is
determined by the baud rate selected or under control of an
external clock~ This selection is made by programming the
Control Register. .

5-83

....

",
",

::I~

......

....
:c
-a..,
...1«:

......a..,

CDP6853
CDP6853 INTERFACE REQUIREMENTS (Cont'd)
The second MOTEL interpretation of OS is that of RD,
MEMR, or I/OR emanating from an 8085 type processor. In
this case, OS identifies the time period when the real-time
clock plus RAM drives the bus with read data. This
interpretation of OS is also the same as an output-enable
signal on a typical memory.

RxD (Receive Data) (12)
The RxD input line is used to transfer serial NRZ data into
the ACIA from the modem, LSB first. The receiver data rate
is either the programmed baud rate or under the control of
an externally generated receiver clock. The selection is
made by programming the Control Registe~.
The RxC is a bi-directional pin which serves as either the
receiver 16x clock input or the receiver 16x clock output.
The latter mode results if the internal baud rate generator is
selected for receiver data clocking.

The MOTEL circuit, within the CDP6853 latches the state of
tHe OS pin on the falling edge of AS/ALE. When the 6800
mode of MOTEL is desired OS must be low during AS/ALE,
which is the case with the CDP6805 family of multiplexed
bus processors. To insure the 8085 mode of',MOTEL, the OS
pin must remain high during the time AS/ALE is high.

RTS (Request to Send) (8)

AS (Multiplexed Address Strobe) (15)

The RTS output pin is used to control the modem from the
processor. The state of the lii"S" pin is determined by the
contents of the Command Register.

A positive-going multiplexed address strobe pulse serves to
demultiplex ADO and AD1. The falling edge of AS or ALE
causes the address to be latched within the CDP6853. The
automatic MOTEL circuitry in the CDP6853 also latches the
state of the OS pin with the falling edge of AS or ALE,

RxC (Receive Clock) (5)

CTS (Clear to Send) (9)
The CTS input pin is used to control the transmitter
operation, The enable state is with CTS low. The transmitter
is automatically disabled if CTS is high:
DTR (Data Terminal Ready) (11)

MOTEL

This output pin is used to indicate the status of the CDP6853
to the modem. A low on DTR indicates the CDP6853 is
enabled, a high indicates it is disabled. The processor
controls this pin via bit 0 of the Command Register,

The MOTEL circuit is a new concept that permits the
COP6853 to be directly interfaced with many types of
microprocessors. No external logic is needed to adapt to
the differences in bus control signals from common
multiplexed bus microprocessors.

DSR (Data Set Ready) (17)
The DSR input pin is used to indicate to the CDP6853 the
status of the modem. A low indicates the "ready" state and a
high, "not-ready".

Practically all' microprocessors interface with one of two
synchronous bus structures.
The MOTEL circuit is built into peripheral and memory ICs
to permit direct connection to either type of bus. An
industry-standard bus structure is now available, The
MOTEL concept is shown logically in Fig. 2.

DCD (Data Carrier Detect) (16)
The DCD input pin is used to indicate to the CDP6853 the
status of the carrier-detect output of the modem. A low
indicates that the modem carrier signal is present and a
high, that it is not.

MOTEL selects one of two interpretations of two pins, In the
6805 case, OS and R/W are gated together to produce the
internal read enable. The internal write enable is a similar
gating of the inverse of R/W. With 8085 Family buses, the
inversion of ROand WR create functionally identical internal
read and write enable signals.

OS (Data Strobe or Read) (27)
The OS pin has two interpretations via the MOTEL circuit.
When emanating from a 6800 type processor, OS is a
positive pulse during the latter portion of the bus cycle, and
is variously called OS (data strobe), E (enable), and t/12 (t/12
clock). During read cycles, OS signifies the time that the
ACIA is to drive the bidirectional bus. In write cycles, the
trailing edge of OS causes the ACIA to latch the written
data.

6800

8085

FAMILY TYPE
MPU SIGNALS

FAMILY TYPE
MPU SIGNALS

AS

OS, E, or 02

R/W

ALE

The COP6853 automatically selects the processor type by
using AS/ALE to latch the state of the OS/RO pin. Since OS
is always low and RO is always high during ASand ALE, the
latch automaticallY'indicates which processor type is
connected.

8085
FAMILY BUS

CDP6853
PIN SIGNALS

AS

1----+-1

INTERNAL

01------,

o

SIGNALS

6805
FAMILY

C

Q

BUS

OS

READ ENABLE

R/W

WRITE ENABLE

92CM-37025

Fig. 2 - Functional diagram of MOTEL circuit.

5-84

CDP6853
CDP8853 INTERNAL ORGANIZATION
This section provides a functional description of the
CDP6853. A block diagram of the CDP6853Is presented in
Fig. 3.
CTS

02-D7
AOO,AOI

TxO

R/W
CSO
CSI

I
N
T
E
R
N
A
L
0
A
T
A
B
U
S

DcD
OSR

RxC
XTLI
XTLO

OTR

CE

RTS

RxO

92CM-37026R1

Fig. 3 - Intflrnal organization.

DATA BUS BUFFERS
The Data Bus Buffer interfaces the system data lines to the
internal data bus. The Data Bus Buffer is bl-directional.
When the R/W line is high and the chip is selected, the Data
Bus Buffer passes the data to the system data lines from the
CDP6853 internal data bus. When the R/Wline Is low and
the chi p is selected, the Data Bus Buffer writes the data from
the system data bus to the internal data bus.
INTERRUPT LOGIC
The Interrupt Logic will cause the IRQ line to the microprocessor to go low when conditions are met that require
the attention of the microprocessor. The conditions which
can cause an interrupt will set bit 7 and the appropriate bit of
bits 3 through 6 in the Status Register If enabled. Bits 5 and 6
correspond to the Data Carrier Detect (DCD) logic and the
Data Set Ready (DSRflogic. Bits 3 and 4 correspond to the
Receiver Data Registerfull and the Transmitter Data Register
empty conditions. These conditions can cause an interrupt
request If enabled by the Command Register.
I/O CONTROL
The I/O Control Logic controls the selection of internal
registerS' in preparation for a data transfer on the internal
data bus and the di rectlon of the transfer to or from the
register.
The registers are selected by the Register Select and Chip
Select and ReadlWrite lines as described in Table I,
previously.

Bus Buffer, and the microprocessor data bus, and the
hardware reset features.
Timing is controlled by the system 1/12 clock input. The chip
will perform data transfers to or from the microcomputer
data bus during the 1/12 high period when selected.
All registers will be initialized by the Timing and Control
LogiC when the Reset (RES) line goes low. See the individual
register description forthe state of the registers following a
hardware reset.
TRANSMITTER AND RECEIVER
DATA REGISTERS
These registers are used as temporary data storage for the
CDP6853 Transmit and Receive Circuits. Both the Transmitter and Receiver are selected by a Register Select 0
(RSO) and Register Select 1 (RS1) low condition. The
ReadlWrite line determines which actually uses the internal
data bus; the Transmitter Data Register is write only and the
Receiver Data Register is read only.
Bit 0 is the first bit to be transmitted from the Transmitter
Data Register (least significant bit first). The higher order
bits follow in order. Unused bits in this register are "don't
care".
The Receiver Data Register holds the first received data bit
in bit 0 (least significant bit first). Unused high-order bits
are "0". Parity bits are not contained in the Receiver Data
Register. They are stripped off after being used for parity
checking.

TIMING AND CONTROL

STATUS REGISTER

The Timing and Control. logic controls the timing of data
transfers on the internal ciata bus and the registers, the Data

Fig.4 indicates the format of the CDP6853 Status Register.
A description of each status bit follows.

5-85

w
w ....
:::ICil!
a:l

w

I-::C
Il.
a:I_

Ia:

"'w
Il.

CDP6853
CDP6853 INTERNAL ORGANIZATION (Cont'd)
78543210

CONTROL REGISTER

I I I I I I I I I

L

'--

-

The Control Register selects the desired transmitter baud
rate, receiver clock source, word length, and the number of
stop bits.
Selected Baud Rate (Bltl 0,1,2,3)

PARITY ERROR*
0- NO PARITY ERROR
1 - PARITY ERROR DETECTED
FRAMING ERROR*
0- NO FRAMING ERROR
1 - FRAMING ERROR DETECTED

These bits, set by the processor, select the Transmitter
baud rate, which can beat1/16an external clock rate or one
of 15 other rates controlled by the internal baud rate
generator as shown in Fig. 5.

OVERRUN*
0- NO OVERRUN
1 - OVERRUN HAS OCCURRED
RECEIVER DATA REGISTER FULL
0"- NOT FULL
1 - FULL
TRANSMITTER DATA REGISTER EMPTY
0- NOT EMPTY
1- EMPTY

o

4

I

WL
SBR
SBN WL1 WLO Res SBR3 SBM SBR11SBRO

DATA CARRIER DETECT (DCD)
0- iiCD LOW (DETEC'T)
1 - i5l:I5 HIGH (NOT DETECTED)

L,I

l'--___

DATA SET READY (DSFi)
LOW (READY)
1 - DSR HIGH (NOT READy)

o-!im!

3210

0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

INTERRUPT (IRQ)
o . NO INTERRUPT (fiiQ PIN HIGH)
1 - INTERRUPT HAS OCCURRED (Bm PIN LOW)

I.-.-.-.-.-. °.-

76543210

SELECTED BAUD RATE (SBR)

0000

*NO INTERRUPTS OCCUR FOR
THESE CONDITIONS

°1-1-111°101010IHARDWARE RESET (RES)
.-.PROGRAM REseT
9ZCM-31783A1

FIg. 4 - Status regIster format.

RECEIVER CLOCK SOURCE (RCS)
0- EXTERNAL RECEIVER CLOCK
1 - BAUD RATE

Receiver Data Regllter Full (Bit 3)
This bit goes to a "1" when the CDP6853 transfers data from
the Receiver Shift Register to the Receiver Data Register,
and goes to a "0" when the processor reads the Receiver
Data Register.

L -_ _ _ _ _ _ _ _ _ _ WORD LENGTH (WL)

§l!
00
01
10
11

TranlmlUer Data Regllter Empty (Bit 4)
This bit goes to a "1" when the CDP6853 transfers data from
the Transmitter Data Register to the Transmitter Shift
Register, and goes to a "0" when the processor writes new
data onto the Transmitter Data Register.
Data Carrier Detect (Bit 5) and
Data Set Ready (Bit 6)
These bits reflect the levels of the DCD and DSR inputs to
the CDP6853. A "0" indicates a low level (true condition)
and a "1" indicates a high (false). Whenever either of these
inputs change state, an immediate processor interrupt
occurs, unless the CDP6853 is disabled (bit 0 of the
Command Regillter is a "0"). When the Interrupt occurs, the
status bits will indicate the levels of the inputs immediately
after the change of state occurred. Subsequent level
changes will not affect the status bits until the Status
Register is interrogated by the processor. At that time,
another interrupt will immediately occur and the status bits
will reflect the new input levels.

1/16X EXTERNAL CLOCK
50
BAUD
75
BAUD
109.92
BAUD
134.58
BAUD
150
BAUD
300
BAUD
600
BAUD
1200
BAUD
1800
BAUD
2400
BAUD
3800
BAUD
4800
BAUD"
7200
BAUD
9600
BAUD
19200
BAUD

76543210

I°1 010 1° 1° 1° 10 I°1 HARDWARI; RESET (ReS)
-

-

-

-

-

-

-

-

PROGRAM RESET

8 BITS
781TS
sBITS
5 BITS

STOP BIT NUMBER (SBN)
0-1 STOP BIT
1 - 2 STOP BITS
- 1-1/2 STOP BITS
FOR WL=5 AND NO PARITY
-1 STOP BIT
FOR WL=B AND PARITY
92CM- 3678 I

Fig. 5 - CDP6853 control register.

Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A "0"
causes the Receiver to operate at a baud rate of 1/16 an
external clock. A "1" causes the Receiver to operate at the
same baud rate as is selected for the transmitter as shown in
Fig.5.
Word Length (Bltl 5,6)

Framing Error (Bit 1), Overrun (2), and
Parity Error (Bit 0)
None of these bits causes a processor interrupt to occur,
but they are normally checked at the time the Receiver Data
Register is read so that the validity of the data can be
verified.
Interrupt (Bit 7)
This bit goes to a "0" when the Status Register has been
read by the processor, and goes to a "1" whenever any kind
of interrupt occurs.

5-86

These bits determine the word length to be used (5,6,7 or 8
bits). Fig. 5 shows the configuration for each number of bits
desired.
.
Stop Bit Number (Bit 7)
This bit determines the number of stop bits used. A "0"
always indicates one stop bit. A "1" indicates 1'h stop bits if
the word length is 5 with no parity selected, 1 stop bit if the
word length is 8 with parity selected, and 2 stop bits in all
other configurations.

CDP6853
CDP68S3 INTERNAL ORGANIZATION (Cont'd)
Parity Mode Control (Bltl 6,7)

COMMAND REGISTER

These bits determine the type of parity generated by the
Transmitter, (even, odd, mark or space) and the type of
parity check done by the Receiver (even, odd, or no check).
Fig. 6 shows the possible bit configurations for the Parity
Mode Control bits.

The Command Register controls specific modes and
functions (Fig. 6).
Data Terminal Ready (Bit 0)

This bit enables all selected interrupts and controls the
state ofthe Data Terminal Ready (DTR) line. A "a" indicates
the microcomputer system is not ready by setting the DTR
line high. A "1" indicates the microcomputer system is
ready by setting the DTR line low. When the DTR bit is set to
a "a", the receiver and transmitter are both disabled.

TRANSMITTER AND RECEIVER

Bits 0-3 of the Control Register select divisor used to
generate the baud rate for the Transmitter. If the Receiver
clock is to use the same baud rate as the transmitter, then
RxC becomes an output and can be used to slave other
circuits to the CDP6853. Fig. 7 shows the transmitter and
Receiver layout.

Receiver Interrupt Control (Bit 1)

This bit disables the Receiver from generating an interrupt
when set to a "1". The Receiver interrupt is enabled when
this bit is set to a "a" and Bit a is set to a "1".

....-_--RxD

Tranlmltter Interrupt Control (Bltl 2,3)

These bits control the state of the Ready to Send (RTS) line
and the Transmitter interrupt. Fig. 6 shows the various
configurations of the RTS line and Transmit Interrupt bit
settings.
/+------------RxC

Receiver Echo Mode (Bit 4)

This bit enables the Receiver Echo Mode. Bits 2 and 3 must
also be zero. In the Receiver Echo Mode, the Transmitter
returns each transmission received by the Receiver delayed
by'h bit time. A "1" enables the Receiver Echo Mode. A "a"
bit disables the mode.

XTLr·-~-----,

XTlO

Parity Mode Enable (Bit S)

TxD

This bit enables parity bit generation and checking. A "a"
disables parity bit generation by the Transmitter and parity
bit checking by the Receiver. A "1" bit enables generation
and checking of parity bits.

92CS-36791

Fig. 7 - Transmitter receiver clock circuits.

0

7

8

PMC
PMC1 PMCtJ

I
I RENI

TIC
TIC1 TICO

IROJ DTR

L

I-::C

I

-a..
CD_

Ia:
a..

COw
DATA TERMINAL READY (OTR)

o~ DATA TERMINAL NOT READY (OTA PIN HIGH)
1 - DATA TERMINAL READY (i:ii1i PIN LOW)

' - - - - - RECEIVER INTERRUPT CONTROL (IRD)
O· RECEIVER INTERRUPT ENABLED
1 - RECEIVER INTERRUPT DISABLED

L-_ _ _ _ _ TRANSMITTER INTERRUPT CONTROL (TIC)

~~

o

1

iffii -

fR-

HIGH. TRANSMIT INTERRUPT DISABLED"
LOW, TRANSMIT INTERRUPT ENABLE

1 0 Rft - LOW, TRANSMIT INTERRUPT DISABLED
1 1 ii'f!- LOW, TRANSMIT INTERRUPT DISABLED
TRANSMIT BREAK ON, T

xD

' - - - - - - - - - RECEIVER ECHO MODe (REM)
a - RECEIVER NORMAL MODE
1 - RECEIVER ECHO MODE"

' - - - - - - - - - - - PARITY MODE ENABLE (PME)
0- PARITY MODE DISABLED

NO PARITY BIT GENERATED
PARITY CHECK DISABLED
1 - PARITY MODE ENABLED
' - - - - - - - - - - - - - PARITY MODE CONTROL (PMC)

78543210

.....

w

4
:
PME

o

::»;!
CD

1010101010101
0101 HARDWARE
RESET(W,
- - - ° ° ° 00
PROGRAM RESET

°~ °S

ODD PARITY TRANSMITTED/RECEIVED
1 EVEN PARITY TRANSMITTED/RECEIVED
MARK PARITY BIT TRANSMITTED
PARITY CHECK DISABLED
1 1 SPACE PARITY BIT TRANSMITTED
PARITY CHECK DISABLED

1

"BITS 2 AND 3 MUST BE ZERO FOR RECEIVER ECHO MODE. iiTi WILL BE LOW.

nc....JI7IGR1

Fig. 8 - CDP8853 command register.

5-87

CDP6853
CDP8853 OPERATION (Cont'd)
TRANSMITTER AND RECEIVER OPERATION

the Status Register of the CDP6853, the interrupt is cleared.
The processor must then identify that the Transmit Data
Register is ready to be loaded and mustthen load it with the
next data word. This must occur before the end of the Stop
Bit, otherwise a continuous "MARK" will be transmitted.

Continuous Data Transmit (Fig. 8)

In the normal operating mode, the processor interrupt
(iRCi) Is used to signal when the CDP6853 is ready to accept
the next data word to be transmitted. This interrupt occurs
at the beginning of the Start Bit. When the processor reads

CHAR.n

/r------~IL-------~~

TxDlr

""'T'--,fST:,::o,P

G"GT]~li]

I

ART

CHAR#n+1

CHAR#n+2

r:-r:-r
~]~~

STOP

I

FAAT

I
I

I
I

PROCESSOR

,

I

"

r:-r:-r_
~ ~ ITARTrsot"'l_~

r:-r:-r

STOP

STOP

fTAAT
I
I

r

L
I

I
I

I
I

/

l

)

INTERRUPT

CHAR#n+3

~r--------~I------~,,/

I

(TRANSMIT DATA
REGISTER EMPTY)

PROCESSOR MUST
LOAD NEW DATA

.NTHIBTIME
INTERVAL; OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTED
I2CM-38'1&2R1

PROCESSOR READS STATUS
REGISTER, CAUSES IRQ
TO CLEAR

Fig. 8 - Continuous data transmit.

Continuous Data Receive (Fig. 9)

data word. This occurs at about the 8/16 point through the
Stop Bit. The processor must read the Status Register and
read the data word before the next interrupt, otherwise the
Overrun condition occurs.

Similar to the above case, the normal mode is to generate a
processor interrupt when the CDP6853 has received a full

CHAR#n

CHAR #n+2

CHAR#n+1

/r------~L-------~v
Rx D

l

""'""T_;.STO.:.=.P

A3]~~]iJ
START

I

I

CHAR #n+3

,/.I
STOP

I

roE]]~EJ

START

:

I

)1
U]'

STOP

rq;q]~G

START

I

f

,/

/LID

:=~~SRO~A~~~~ ~~~:

I

I

:
I

LID

OVERRUN OCCURS

INTERRUPT OCCURS
ABOUT 1118 INTO
LAST STOP BIT.

t2CM4I7I3R1

PARITY, OVERRUN,

AND FRAMING ERROR
UPDATED, ALSO

PROCESSOR READS STATUS
REGISTER, CAUSES IRQ
TO CLEAR

Fig. 9 - Continuous data rscflivfI.

5-88

L

[g31~;}iJ

~ START
I

TIME INTERVAL; OTHERWISE,

PROCESSOR

"
STOP

L

CDP6853
CDP6853 OPERATION (Cont'd)
Transmit Data Register Not Loaded
By Processor (Fig. 10)
If the processor is unable to load the Transmit Data Register
in the allocated time. then the TxD line will go to the
"MARK" condition until the data is loaded. IRQ interrupts
CONTINUOUS "MARK"

CHAR #n

n

/~--------~I--------"

STOP

TxD

continue to occur at the same rate as previously. except no
data is transmitted. When the processor finally loads new
data. a Start Bit immediately occurs. the data word
transmission is started. and another interrupt is initiated.
signaling for the next data word.

________L -______

[BOJ8f-I9iJ I

r-

START

~,/~

________L -________

STOP

STOP

I

CHAR #n+2

CHAR#n+1

/~

r;Qy\[EE] I [%E[H
CHARACTER
TIME

,

--l
I

START

ISTART

nr---

\

PROCESSOl
INTERRUPT
FOR DATA
REGISTER
EMPTY

INTERRUPTS
CONTINUE AT

CHARACTER RATE
EVEN THOUGH
NO DATA IS
TRANSMITTED

PROCESSOR
READS
STATUS
REGISTER

WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY

92CM- 36794RI

Fig. 10- Transmit data register not loaded by processor.

Effect of CTS on Transmitter (Fig. 11)
CTS is the Clear-to-Send Signal generated by the modem.
It is normally low (True State) but may go high in the event
of some modem problems. When this occurs. the TxD line
immediately goes to the "MARK" condition. Interrupts

continue at the same rate. but the Status Register does not
indicate that the Transmit Data Register is empty. Since
there is no status bit for CTS. the processor must deduce
that CTS hal!..Jl2!:!e to the FALSE (high) state. This is
covered later. CTS is a transmit control line only. and has no
effect on the CDP6853 Receiver Operation.
CONTINUOUS "MARK"
I

.,. .,.....

=~
=
...
.... :c

=......
-A.,

ICC:
A.,

NOT CLEAR-To-SEND

CLEAR-To-SEND

oa_.",~
INDICATING MODEM
IS !'!Q! READY TO
RECEIVE DATA. Tx D
IMMEDIATELY GOES
TO "MARK" CONDITION

PROCESSOR
INTERRUPT
AT NORMAL
START BIT
TIME

PROCESSOR READS
STATUS REGISTER.
SINCE DATA REGISTER

=J:.~TD~':,~E ~~~~ESSOR
C'I'IIS SOURCE OF
INTERRUPT (THIS IS
COVERED ELSEWHERE
IN THIS NOTE).

92CM-36795

Fig. 11 - Effect of CfSon transmitter.

5-89

CDP6853
CDP8853 OPERATION (Cont'd)
Effect of Overrun on Receiver (Fig. 12)

Data Register, but the Overrun status bit is set. Thus, the
Data Register will contain the last valid data word received
and all following data Is lost.

Ifthe processor does not read the Receiver Data Register in
the allocated time, then, when the following interrupt
occurs, the new data word is not transferred to the Receiver
CHAR#n

~

STOP

CHAR#n+1

V

I

I

CHAR:l:n+2
"-/

STOP

STOP

RXDD rs;G[Ed:J I rs;GIbG I
I~

I~

~

PROCESSOR
INTERRUPT

~~~::~:::~:R

v~

I

pJESSOR

=====

REGISTER

FULL

SfB1T~bG

I r;GIH

I~

nr----

RECEIVER DATA REGISTEA
NOT UPDATED BECAUSE
PROCESSOR DID NOT READ
PREVIOUS DATA. OVERRUN
BIT SEr IN STATUS
REGISTER.

~OVERRUN

BIT SET IN
STATUS REGISTER
92CM-36796RI

Fig. 12 - Effect of overrun on receiver.

Echo Mode Timing (Fig. 13)

In Echo Mode, the TxD line re-transmlts the data on the RxD
line, delayed by 'h of the bit time.

Fig. 13 - Echo mode timing.

5-90

....!I_ _-

STOP

I~

READS
STATUS

CHAR#n+3
____

CDP6853
CDP6853 OPERATION (Cont'd)
Effect of CTS on Echo Mode Operation (Fig. 14)

way as "Effect of CTS on Transmitter". In this case,
however, the processor interrupts signify that the Receiver
Data Register is full, so the processor has no way of
knowing that the Transmitter has ceased to echo.

See "Effect of CTS on Transmitter" for the effect of CTS on
the Transmitter. Receiver operation is unaffected by CTS,
so, in Echo Mode, the Transmitter is affected in the same
CHAR#n
~/

RxO

CHAR#n+1

\J

I

STOP

CHAR#n+2

'j

I

STOP

CHAR#n+3
\j~_ _ _-L.I_ _ __

I

STOP

STOP

Il GGLffJ I [%GIbJiJ I fD:GIH:J I
I~

I~

-un

I~

un

Llll

~

[%I~rH

I~

UJrn----

NOT-CLEAR-To-SEND

I

I

STOP

STOP

TxO

~Jl_l~I~~[ I I
BN

START

P

[)
1180I B lI B·1I

CTsGOESTO
"FALSE" CONDITION

I

NORMAL
RECEIVER DATA
REGISTER FULL
INTERRUPTS

92CM-36798

Fig. 14 - Effflct of CTS on flcho modfl.

Overrun In Echo Mode (Fig. 15)

If Overrun occurs in Echo Mode, the Receiver is affected the
same way as described in "Effect of Overrun on Receiver".

For the re-transmitted data, when overrun occurs, the TxD
line goes to the "MARK" condition until the first Start Bit
after the Receiver Data Register is read by the processor.

CHAR#n

~/

CHAR#x

I "

STOP

STOP

mEEJ

RXoIl ~_G'EJ I
LJIJ'
/LlJ]
I~

nI

STOP

I R3I3iJ I [%E[~H
~

~

UJrrr-----

LJI]

i!

fSTOP f

TxO

CHAR#x+1
,>j~_ _ _ _.J..I_ __

I

STOP

~

iRa

/

, /

[BOEI~
START
PROCESSOR FINALLY
READS RECEIVER
OATA REGISTER,
LAST VALID
CHARACTER (#n)

PROCESSOR
INTERRUPT

FOR RECEIVER
DATA REGISTER
FULL
PROCESSOR
READS
STATUS
REGISTER

PROCESSOR
INTERRUPT
FOR CHAR #x
IN RECEIVER
DATA REGISTER

OVERRUN OCCURS

Tx o Goes TO
"MARK"
CONDITION

92CM-36788

Fig. 15 - OVflrrun in flcho modfl.

5-91

'"
=
me:. .

rn-

....
:z
-a.

.....

01:1_
I ..

a.

CDP6853
CDP8853 OPERATION (Cont'd)
Framing Error (Fig. 18)

interrupt occurs. Subsequent data words are tested for
Framing Error separately, so the status bit will always
reflect the last data word received.

Framing Error is caused by the absence of Stop Bit(s) on
received data. The status bit is set when the processor

RxD
(EXPECTED)

RxD
(ACTUAL)

NOTES:
1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.
2. IF NEXT DATA WORD IS OK.
FRAMING ERROR IS CLEARED.

PROCtsSOR
INTERRUPT,
·FRAMING
ERROR

BIT$ET
92CM-36789

Fig. 16 - Framing error.

Effect ofDCD on Receiver (Fig. 17)
.DCD is a modem output used to indicate the status of the
carrier-frequency-detection circuit of the modem. This line
goes high for a loss of carrier. Normally, when this occurs,
the modem will stop transmitting data (RxD on the CDP6853
some time later. The CDP6853 will cause a processor
interrupt whenever DCD changes state and will indicate this

~-r~rST~O~P

RxD

I

801 B, I B21 J3M~

condition via the Status Register.
.Once such a change of state occurs, subsequent transitions
will not cause interrupts or changes in the Status Register
until the first interrupt is serviced. Wilen the Status Register
is read by the process..Q!....the CDP6853 automatically
checks the level of the DCD line, and if it has changed,
another Interrupt occurs.

~,--,__,-~____C_O_N_TI_N_UO_U_S_"_MA_R_K_"____~~ST~O~P

START

I

I

START

r~~~~1

DCD _ _ _ _ _ _ _ _ _ _ _ _

1~~~~1

~--~I

I~----_+------------_+--

I

IRQ

I

LJIJLJI]I'='==:::;:::t==:::7]/LllJ
t

~~6'~EAS~OR
INTERRUPT

STOP

G I Gl3J3iJ L

I Bol B,I B211

1

AS LONG AS

PROCESSOR
INTERRUPT
FOR fKjlj
GOING HIGH

r

~F~R~WEHR
INTERRUPTS

PROCESSOR

FOR RECEIVER
WILL OCCUR

INTERRUPT
FOR iil:Ii
GOING LOW

'"
IiL __.LLI
III

/L

t

NO INTERRUPT
WILL OCCUR
HERE, SINCE
RECEIVER IS NOT
ENABLED UNTIL
FIRST START BIT
DETECTED

PROCESSOR

INTERRUPT
FOR
RECEIV~

DATA

92CM-361B6

Fig. 17 - Effect of l5Ci5 on receiver.

5-92

CDP6853
CDP8853 OPERATION (Cont'd)

l't. Stop Bltl (Fig. 18)

Timing with

S-bit data words with no parity bit. In this case, the
processor interrupt for Receiver Data Register Full occurs
halfway through the trailing half-Stop Bit.

It is possible to select 1'h Stop Bits. but this occurs only for
CHAR#n

CHAR#n+1
I

I

/
RxD

I III

L

t

PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGH" THE 1/2
STOP BIT

92CM- 36787

Fig. 18- Timing with 1-1/2 stop bits.

Tranlmlt Continuoul "BREAK" (Fig. 19)
This mode is selected via the CDP68S3 Command Register
and causes the Transmitter to send continuous "BREAK"
characters after both the transmitter and transmitter-holding
registers have been emptied.

nI
STOP

TxD

When the Command Register is programmed back to
normal transmit mode, a Stop Bit is generated and normal
transmission continues.

'J

/
STOP

I

GET~GI:J

START

STOP

I BO

BN

81 I

P

STOP

START

IRQ

POINTATWHI~

1 - - - - - - - 1 - PERIOD DURING
WHICH PROCESSOR
SELECTS
CONTINUOUS

NORMAL
INTERRUPT

PROCESSOR
SELECTS
NORMAL
TRANSMIT
MODE

"BREAK" MODE

CI)
CI)-I

:::Ii::!!
=w
-a...
=-a...
"'w

/

..... :J:

PROCESSOR
INTERRUPT
TO LOAD
TRANSMIT
DATA

Ia:

92CM-36785

Fig. 19 - Transmit continuous "BREAK".

Receive Continuoul "BREAK" (Fig. 20)
In the event the modem transmits continuous "BREAK"

------------,
E~EEJ .I

/

,-y_-;S",T",O,P

Rx 0

characters, the CDP6853 will terminate receiving. Reception
will resume only after a Stop Bit is encountered by the
CDP6853.

CONTINUOUS "BREAK"
I

Bo

I~

I B1

STOP

N.l,_P-L,S_T.,..0.lP'_lIl1-..J'_..J....--In
.1,_B_

I

,/~------

STOP

rqq- EL:J I I I I
80

I~

I~

-------.~.....----~~ ~
I t
PROCESSOR

INTERRUPT
FOR
RECEIVER
DATA REGISTER
FULL

PROCESSOR
INTERRUPT
WITH FRAMING
ERROR (PARITY
AND OVERRUN
CHECKS NORMAL)

5-93

...----

NO INTERRUPT

NORMAL

SINCE RECEIVER
DISABLED UNTIL
FIRST STOP BIT

REelEVER
INTERRUPT

Fig. 20 - Receive continuous "BREAK".

81

92CM-367B4

CDP6853
CDP8853 OPERATION (Confd)
STATUS REGISTER OPERATION

5. Transmitter and Receiver may be in full operation
simultaneously. This is "full-duplex" mode.

Because of the special functions of the various status bits,
there is a suggested sequence for checking them. When an
interrupt occurs, the CDP6853 should be interrogated, as
follows:

6. If the RxD line inadvertently goes low and then high·
during the first 9 receiver clocks after a Stop Bit; will
result in a false Start Bit.

1. Read Status Register

For false Start Bit detection, the CDP6853 does not
begin to receive data, instead, only a true Start Bit
initiates receiv~r operation.

This operation automatically clears Bit 7 (IRQ). Subsequent transitions on DSR and DCD will cause another
interrupt.

7. Precautions to consider with the crystal oscillator
circuit:
The XTLI input may be used as an external clock
input. The XTLO pin must be floating and may not
be used for any other function.

2. Check IRQ Bit
If not set, interrupt source is not the CDP6853.
3. Check DCD and DSR

8. 'DCD and'D'S'R' transitions, aithough causing immediate
processor interrupts, have no effect on transmitter
operation. Data will continue to be sent, unless the
processor forces transmitter to turn off. Since these are
high-impedance inputs, they must not be permitted to
float (un-connected). If unused, they must be terminated
either to GND or Voo.

These must be compared totheir previous levels, which
must have been saved by the processor. Ifthey are both
"0" (modem "on-line") and they are unchanged then
the remaining bits must be checked.
4. Check RDRF (Bit 3)
Check for Receiver Data Re.Qister Full.
5. Check Parity, Overrun, and Framing Error (Bits 0-2)
.only if Receiver Data Register is Full.

GENERATION OF NON-STANDARD BAUD RATES

6. Check TDRE (Bit 4)

Divisors

Check for Transmitter Data Register Empty.

The internal counter/divider circuit selects the appropriate
divisor for the crystal frequency by means of bits 0-3 of the
CDP6853 Control Register.

7. If none of the above, then CTS must have gone to the
FALSE (high) state.

The divisors, then, are determined by bits 0-3 in the Control
Register and their values are shown in Table II.

PROGRAMMED RESET OPERATION
A program reset occurs when the processor performs a
write operation to the CDP6853 with ADO high and ADl
low. The program reset operates somewhat different from
the hardware reset (RES pin) and is described as follows:
1. Internal registers are not completely cleared. The data
sheet indicates the effect of a program reset on internal
registers.
2. The DTR line goes high immediately.
3. Receiver and transmitter interrupts are disabled immediately. If iRQ is low when the reset occurs, it st~ow
until serviced, unless interrupt was caused by OCO or
DSR transition.
4. DCD and DSR interrupts disabled immediately. If IRQ
is low and was caused by DCD or DSR, then it goes
high, also "[)"C[) and 'DS"A status bits subsequently will
follow the input lines, although no interrupt will occur.
5. Overrun cleared, if set.
MISCELLANEOUS NOTES ON OPERATION

Generating Other Baud Rates
By using a different crystal, other baud rates may be
generated. These can be determined by:
Crystal Frequency
Baud Rate = - - - - - - Divisor
Furthermore, it is possible to drive the CDP6853 with an
off-chip oscillator to achieve the same thing. In this case,
XTLI (pin 6) must be the clock input and XTLO (pin 7) must
be a no-connect.

DIAGNOSTIC LOOP-BACK OPERATING MODES
A simplified block diagram for a system incorporating a
CDP6853 ACIA is shown in Fig. 21.
Occasionally it may be desirable to include in the system a
facility for "loop-back" diagnostic testing, of which there
are two kinds:

1. If Echo Mode is selected, RTS goes low.

1. Local Loop-Back

2. If Bit 0 of Command Register Is "0" (disabled), then:
a) All interrupts~isabled, including those caused by
DCD and DS transitions.
b) Receiver disabled, but a character currently being
received will be completed first.
c) Transmitter is disabled after both the Transmit
Data and Transmit Shift Registers have been
emptied.
3. Odd parity occurs when the sum of all the"l" bits in the
data word (Including the parity bit) is odd.
4. In the receive mode, the received parity bit does not go
into the Receiver Data Register, but is used to generate
parity error for the Status Register.

5-94

Loop-back from the point of view of the processor. In
this case, the Modem and Data Link must be effectively
disconnected and the ACIA transmitter connected
back to its own receiver, so that the processor can
perform diagnostic checks on the system, excluding
the actual data channel.
2. Remote Loop-Back
Loop-back from the point of view of the Data Link and
Modem. In this case, the processor, itself, is disconnected and all received data is immediately retransmitted, so the system on the other end of the Data Link
may operate independent of the local system.

CDP6853
CDP6853 OPERATION (Cont'd)
Table II - Divisor Selection for the CDP6853
CONTROL
REGISTER
BITS

DIVISOR SELECTED
FOR THE
INTERNAL COUNTER

3
0

2
0

1
0

0
0

No Divisor Selected

0

0

0

1

36,864

0

0

1

0

24,576

0

0

1

1

16,768

0

1

0

0

13,696

0

1

0

1

12,288

0

1

1

0

6,144

0

1

1

1

3,072

1

0

0

0

1,536

1

0

0

1

1,024

1

0

1

0

768

1

0

1

1

512

1

1

0

0

384

1

1

0

1

256

1

1

1

0

192

1

1

1

1

96

PR~~:S~-OR

BAUD RATE GENERATED
WITH 1.6432 MHz
CRYSTAL

BAUD RATE GENERATED
WITH A CRYSTAL
OF FREQUENCY (F)

1/16 of External Clock at Pin XTLI 1/16 of External Clock at Pin XTLI
1.8432 x 10·
F
50
36.864
36.864
F
1.8432 x 10·
75
24576
24576
F
1.8432 x 10·
16768
16768 = 109.92
1.8432 x 10·
F
13696
13696 = 134.58
1.8432 x 10·
F
150
12288
12288
1.8432 x 10·
F
6144
6144 =300
1.8432 x 10·
F
3072
3.072 = 600
F
1.8432 x 10·
1536
1536 = 1200
1.8432 x 10·
F
= 1800
1024
1.024
1.8432 x 10·
F
= 2400
768
768
1.8432 x 10·
F
= 3600
512
512
1.8432 x 10·
F
= 4800
384
384
1.8432 x 10·
F
= 7200
256
256
1.8432 x 10·
F
= 9600
192
19~
F
1.8432 x 10'
= 19200
96
96

1--_>-----_---_---_--

TO DATA LINK
92CS-37022

Fig. 21 - Simplified system diagram.

5-95

en
en-'

::t~
=
...
-a..
I-::Z:

=......
ICC

a..

CDP6853
CDP6853 OPERATION (Cont'd)
CDPSSS3

l

iiTs iiiR

RxD

TxD

SEL

LLB

DCD CTS

DSR

J

lvJ
2V

.,;;- STB

3V

4V
CD74HC157
lA
~ lB
2A
2B
3A
3B

~
' - - SEL

IV

STB

3V

4B

4A

+5

E
-

4V
CD74HC157
lB
lA
2B

CTS
DSR
MODEM
TxD
DTR

2V

~

RxD
DCD

RTS

t-92CM- 37032

2A

3B

3A

r--

4B

4A

f--

NOTES: 1. HIGH ON LLB SELECTS LOCAL LOOP-BACK MODE.
2. HIGH ON CD74HC157 SELECT INPUT GATES ".B" INPUTS
TO "V" OUTPUTS: LOW GATES "A" TO "V".

Fig. 22 - Loop-back circuit schematic.

The CDP6853 does not contain automatic loop-back
operating modes, but they may be implemented with the
addition of a small amount of external circuitry,
Fig. 22 indicates the necessary logic to be used with the
CDP6853.
The LLB line is the positive-true signal toenable local loopback operation. Essentially, LLB=hlgh does the following:

LLB may be tied to a peripheral control pin to provide
processor control of local loop-back operation. In this way.
the processor can easily perform local loop-back diagnostic
testing.
Remote loop-back does not require this circuitry, so LLB
must be set low. However, the processor must select the
following:
1. Control Register bit 4 must be "1". so thatthe transmitter
clock=receiver clock.

1. Disables outputs TxD. DTR. and RTS (to Modem).
2. Disables Inputs RxD, DCD, CTS. DSR (from Modem).
3. Connects transmitter outputs to respective receiver
inputs:
a) TxD to RxD
b) DTR to i5CD
c) R'fs to CTS

2. Command Register bit 4 must be "1" to select Echo
Mode.
3. Command Register bits 3 and 2 must be "1" and "0",
respectively, to disable transmitter interrupts.
4. Command Register bit 1 must be "0" to disable receiver
interrupts.
In this way, the system re-transmlts received data without
any effect on the local system.

5-96

CDP6853
DYNAMIC ELECTRICAL CHARACTERISTICS-BUS TIMING, Voo = 5 V de ± 5%, Vss = 0 V dc,
TA =-40 to +85°C, CL =75 pF, See Figs. 23, 24, 25.
IDENT.
NUMBER

1
2
3
4

8
13
14
15
18
21
24
25
26
27
28
30
31

LIMITS
CDP6853 CDP6853-2 CDP6853-4 UNITS
Min. Max. Min. Max. Min. Max.
953 DC 500 DC 250 DC

CHARACTERISTIC
Cycle Time
Pulse Width, DS/E Low or RD/WR High
Pulse Width, DS/E High or RD/WR Low
Clock Rise and Fall Time
R/W Hold Time
R/W Set-up Time Before DS/E
Chip Enable Set-up Time Before AS/ALE Fall
Chip Enable Hold Time
Read Data Hold Time
Write Data Hold Time
Muxed Address Valid Time to AS/ALE Fall
Muxed Address Hold Time
Delay Time, DS/E to AS/ALE Rise
Pulse Width, AS/ALE High
Delay Time, AS/ALE to DS/E Rise
Peripheral Output Data Delay Time
From DS/E or RD
Peripheral Data Set-up Time

!evc
PWEL 300
PWEH 325
t"t,
10
tRWH
15
tRWS
55
tcs
0
tCH
10
tOHR
0
tOHW
50
tASL
50
tAHL
50
tASO
PWASH 100
90
tASEO
tooR
tosw

125
145
30 10
10
20
0
100 10
0
20
15
0
45
20
-

20 240 10
220 110

-

90
70

30

-

-

40
-

5
5
10
0
10
0
10
5
0
20
10

70
-

5
55

-

-

-

30
-

20
-

ns

-

-

35
-

NOTE: Designations E, ALE, RD and WR refer to signals from non-6805 type microprocessors.

AS

---.I]

CI)
CI)....r

DS

::IC2
COw
I-::J:

-a..
COla::
COw
a..

A/W

CE

AOO,AOI
WRITE

------<

ADO, AOI
REAO
NOTE: VHIGH • VOO -2.0V, VLOW -O.SV, FOR VOO 5.0V!; 10"

92CM- 37029

Fig. 23 - Bus timing waveforms of CDP6853.

5-97

CDP6853

ALE (ADDRESS LATCH ENABLE)
(AS PIN)

Rii (READ

ViR

OUTPUT ENABLE)
(OS PIN)

(WRITE ENABLE)
(RiWPIN)

CE CHIP (ENAB

ADO- AD7
(ADDRESS/DATA" .:.B;;.;US~)_ _ _ _ _ _ _ _ _{

92CM-37031

Fig. 24 - Bus-read timing waveforms of 8085 multiplexed bus.

ALE(ADDRESS LATCH ENABLE)
(AS PIN)

iiii

(READ OUTPUT ENABLE)
(OS PIN)

~----~3r-----~

WR (WRITE ENABLE)
(R/W PIN)

CE (CHIP ENABLE)

__~~WW~LL~L4~

ADO-AD7

--<

(ADDRESS/.;;.DA",T",A;..;B;.;;U.;;.S:..)_ _ _ _ _ _ _

NOTE: VHIGH • VOD -2.V. V LOW ' 0.8V. FOR VDD -5V:!:.10 %

82CM-37030

Fig. 25 - Bus-writs timing waveforms of 8085 multiplexed bus.

DYNAMIC ELECTRICAL CHARACTERISTICS - TRANSMIT/RECEIVE, See Figs. 28, 27 and 28.
Voo = 5 V ± 5%, TA = -40· to +85·C
CHARACTERISTIC
Transmit/Receive Clock Rate
Transmit/Receive Clock High Time
Transmit/Receive Clock Low Time
XTLI to TxD Propagation Delay
RTS Propagation Delay
IRQ Propagation Delay (Clear)
RES Pulse Width
(t,.tl = 10 to 30 nsl
"The baud rate with external clocking is: Baud

CDP6853
Min.
Max.

tccv
tcH
teL
too
tOLY
tiRO

IRES
Rate==--::~__

16xTccv

5-98

400·
175
175

-

400

-

-

LIMITS
CDP6853-2
Min.
Max.

325
145
145

-

500
500
500

-

410
410
410

-

300

-

CDP6853-4
Min.
Max.

250
110
110

-

200

UNITS

315
315
315

-

ns

CDP6853
DS _ _ _ _- J
XTLI
( TRANSMIT)
CLOCK INPUT)

TxO
TRQ
(CLI::AR)

NOTE: TxD RATE

IS 1116 TxC RATE
92C5-36776

~36777RI

92CS

1]

Fig. 27 - Interrupt- and output-timing waveforms.

Fig. 26 - Transmit-timing waveforms with external clock.

EXTERNAL
TRANSMITTER
CLOCK

XTLl

1.8432 MHz
CRYSTAL

OPEN
CIRCUIT

NOTE:

R.O RATE IS 1/16 R.C RATE

XTLO

C'" 10-50 pF
INTERNAL CLOCK

92C5-36778

EXTERNAL CLOCK
92CS-42341

Fig. 29 - Transmitter clock generation.

Fig. 28 - Receive external clock timing waveforms.

0

o

.....

=:!
=w

1-::1:
-0...

=-

'IZ:
"'w
0...

5-99

SPI SERIAL BUS PERIPHERALS
PAGE
CDP68HC68A2

CMOS Serial 1O-Bit ND Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3

CDP68HC68P1

CMOS Single Port Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-19

CDP68HC68P2

CMOS Octal Serial Solenoid Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-27

CDP68HC68R1
CDP68HC68R2

CMOS 128 Word (CDP68HC68R1) and 256 Word (CDP68HC68R2) . . . . . . . . . . . .. 6-32
By 8-Bit Static RAMs

.CDP68HC68S1

Serial Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-38

CDP68HC68T1

CMOS Real-Time Clock With RAM and Power Sense/Control ................... 6-52

CDP68HC68T2

CMOS Real-Time Clock With Serial Peripheral Interface (SPI) Bus. . . . . . . . . . . . . . .. 6-70

CDP68HC68W1

Digital Pulse Width Modulator. ............................................... 6-72

6-1

(I)

HARRIS

CDP68HC68A2
CMOS Serial 1 O-Bit AID Converter

January 1991

Pinout

Features
•
•
•
•
•
•
•
•
•
•
•
•
•

16 LEAD PLASTIC DIP
TOP VIEW

10-Bit Resolution
8-Bit Mode for single Data Byte Transfers
SPI (Serial Peripheral Interface) Compatible
Operates Ratiometrically Referencing VDD or an External Source
14~s 10-Bit Conversion Time
8 Multiplexed Analog Input Channels
Independent Channel Select
Three Modes of Operation
On Chip Oscillator
Low Power CMOS Circuitry
Intrinsic Sample and Hold
16 Lead Dual-In-Line Plastic Package
20 Lead Dual-In-Line Small Outline Plastic Package

voo
All
AI2
MOSI

AI3
AI.
AIS

AIOI

AI6

EXT.REF.

Description
The CDP68HC68A2 is a CMOS 8-bit or 10-bit successive
approximation analog to digital converter (ND) with a standard
Serial Peripheral Interface (SPI) bus and eight multiplexed analog
inputs. Voltage referencing is user selectable to be relative to
either VDD or analog channel 0 (AIO). The analog inputs can
range between VSS and VDD.

the selected channels to be specified as the "starting" channel.
Conversions proceed sequentially beginning with the starting
channel. Nonselected channels are skipped. Modes can be
selected to: sequence from channel to channel on command;
sequence through channels automatically, converting each
channel one time; or sequence repeatedly through all channels.

The CDP68HC68A2 employs a switched capacitor, successive
approximation AID conversion technique which provides an
inherent sample-and-hold function. An onchip Schmitt oscillator
provides the internal timing for the AID converter. The Sch mitt
input can be externally clocked or connected to a single, external
capacitor to form an RC oscillator with a period of approximately
10-30ns per picofarad.

The results of 10-bit conversions are stored in 8-bit register
pairs (one pair per channel). The two most significant bits
are stored in the first register of each pair and the eight least
significant bits are stored in the second register of the pair. To
allow faster access, in the 8-bit mode, the results of conversions
are stored in a single register per channel.

Conversion times are proportional to the oscillator period. At the
maximum specified frequency of 1Mhz, 1O-bit conversions take
14 microseconds per channel. At the same frequency, 8-bit
conversions consume 12 microseconds per channel.
The versatile modes of the CDP68HC68A2 allow any combination of the eight input channels to be enabled and anyone of

A read-only STATUS register facilitates monitoring the status of
conversions. The STATUS register can simply be polled or the
INT pin can be enabled for interrupt driven communications.
The CDP68HC68A2 is available in a 16 lead dual-in-line plastic
package (E suffix) or in a 20 lead dual-in-line small oulline
plastic package (M suffix).

Block Diagram

STATUS REGISTER

INTERRUPT
LOGIC

~I

TNT

I

SPI CONTROL LOGIC

CONTROL LOGIC

ADDRESS CONTROL
LOGIC

8T ATUS
REGISTERS

ANALOG MULTIPLEXER

CONTROL
REGISTERS

-}a
ANALOO INPUTS

·USED AS VOLTAGE INPUT

Copyright

REFERENCE

dri· .... · rikl

IN EXTERNAL REFERENCE
MODE.

© Harris Corporation 1991

File Number

6-3

1963.1

CDP68HC68A2
Pinout
VDD
INT

AI1

MISO

AI2
AI3

NC

NC

NC

NC
AI4

CE

AIS

AIOI
EXT.REF.

AIS

VSS 1

AI7

20 LEAD SOP DIP 1M SUFFIX)
TOP VIEW

Pin Descriptions

(Numbers in parenthesis are pin numbers for DIP version)

OSC (1) Oscillator (Input/Output)

CE (6) Chip Enable (Input)

This pin is user programmable. In the "external" mode, the
clock input for the successive approximation logic is
applied to OSC from an external clock source. The input is
a Schmitt trigger input which provides excellent noise
immunity. In the "internal" mode, a capacitor is connected
between this pin and a power supply to form a "one pin
oscillator". The frequency of the oscillator is inversely
dependent on the capacitor value. Differences in period,
from one device to another, should be anticipated. Systems
utilizing the internal oscillator must be tolerant of
uncertainties in conversion times or provide trimming
capability on the OSC capacitor. See Figure 7 for typical
frequencies versus capacitance.

An active HIGH device enable. CE is used to synchronize
communications on the SPllines (MOSI, MISO, and SCK).
When CE is held in a low state, the SPI logic is placed in
a reset mode with MISO held in a high impedance state.
Following a transition from low to high on CE, the
CDP68HC68A2 interprets the first byte transferred on
the SPI lines as an address. If CE is maintained high,
subsequent transfers are interpreted as data reads or
writes.

INT (2) Interrupt (Open Drain Output)
INT is used to signal the completion of an AID conversion.
This output is generally connected, in parallel with a pullup
resistor, to the interrupt input of the controlling
microprocessor. The open drain feature allows wireNOR'ing with other interrupt inputs. The inactive state of INT
is high impedance. When active, INT is driven to a low level
output voltage. The state of INT is controlled and monitored
by bits in the Mode Select and Status Registers.
MISO (3) Master-In-Slave-Out (Output)
Serial data is shifted out on this pin. Note: data Is provided
most significant bit first.

AIO/EXT REF (7) Analog Input O/External Reference
(Input)
This input is one of eight analog Input channels. Its function
is selectable through the Mode Select Register (MSR). If VR
is set high in the MSR, AIO/EXT REF provides an external
voltage reference against which all other inputs are
measured. AIO/EXT REF must fall within the VSS and VDD
supply rails. If VR is set low in the MSR, VDD is used as the
reference voltage and AIO/EXT REF is treated as any other
analog input (see AI1-7).
A11-7 (9-15) Analog Inputs 1-7 (Inputs)
Together with AIO/EXT REF, these pins provide the eight
analog inputs (channels) which are multiplexed within the
CDP68HC68A2 to a single, high-speed, successive
approximation, AID converter. A11-7 must fall within the
VSS and VDD supply rails.

MOSI (4) Master-Out-Slave-In (Input)

VSS (8) Negative Power Supply

Serial data is shifted in on this pin. Data must be supplied
most significant bit first. Note: this is a CMOS input and
must be held high or low at all times to minimize device
current.

This pin provides the negative analog reference and the
negative power supply for the CDP68HC68A2.

SCK (5) Serial Clock (Input)
Serial data is shifted out on MISO, synchronously, with each
leading edge of SCK. Input data from the MOSI pin is
latched, synchronously, with each trailing edge of SCK.

VOO (16) Positive Power Supply
This pin provides the positive power supply and, depending
on the value of the VR bit in the MSR, the positive analog
reference for the CDP68HC68A2.

6-4

Specifications CDP68HC68A2
Maximum Ratings Absolute Maximum Values
DC Supply Voltage Range, (VDD) ................•• -0.5V to + 7V
(Voltage Referenced to VSS Terminal)
Input Voltage Range, All Inputs .............. -0.5V to VDD +0.5V
DC Input Current, Any One Input. .••....••.............. ±1 OmA
Power Dissipation Per Package (PD)
TA = -40 0 C to +60 0 C (Package Type E) ......••.••••. 500mW
TA = +600 C to +85 0 C (Package Type E) ..•... Derate Linearly at
12mW/oC to 200mW
TA = -40 0 C to + 70 0 C (Package Type M)* ............. 400mW
TA =-70 0 C to +85 0 C (Package Type M)* •.... Derate Linearly at
6.0mW/oC to 310mW

Device Dissipation Per Output Transistor ................. 40mW
TA = Full Package Temperature Range (All Package Types)
Operating Temperature Range (TA) ............ -40 0 C to +85 0 C
Storage Temperature Range (TSTG) ....•..... -65 0 C to +150 0 C
Lead Temperature (During Soldering) .........•••...•.. +265 0 C
At Distance 1/16 ± 1/32 In. (1.59 ± 0.79mm) From Case for
lOs Max
*Printed circuit board mount: 57mm x 57mm minimum area x 1.6mm thick
G10 epoxy glass, or equivalent.

Recommended Operating Conditions TA = -400 C to +85 0 C. For maximum reliability, device should always be
operated within the following ranges:
LIMITS
CHARACTERISTIC
DC Operating Voltage Range

MIN.

I

MAX.

UNITS

3

I

6

V

Electrical Characteristic TA = +25 0 C, VDD = 5V, except as noted.
TEST
CONDITIONS

CHARACTERISTICS

LIMITS
MIN.

TYP.

MAX.

UNITS

±1.25

±2

LSB

±1.25

±2

LSB

ACCURACY
Differential Linearity Error
Integral Linear Error

10-Bit Mode
10-Bit Mode

Offset Error

10-Bit Mode

-1

3

4

LSB

Gain Error

10-Bit Mode

-1

1

2

LSB

ANALOG INPUTS: AIO THRU AI7
Input Resistance
Sample Capacitance

In Series With Sample Caps
During Sample State

Input CapaCitance

During Hold State

Input Current

@ VIN - VREF+ During Sample

pF

20

pF

From Input RC Time Constant

Input Voltage Range: AIO

VR=1

~A

±1
VSS

Input Bandwidth (3dB)

JJA

+30

During Hold or Standby State
Input + Full Scale Range

n

85
400

V

VDD+·3
4.68

3.0

-

MHz
V

VDD

High Input Voltage

VIH

VDD = 3t06V

Low Input Voltage

VIL

VDD-3t06V

70
30

%ofVDD

rna:

~D..

±1

~A

TA-+25 0 C
DIGITAL OUTPUTS: MISO, INT, TA - -40 0 C to +850 C

10

pF

0.4

V

±10

~A

1

MHz

High Level Output

4.25

VOH,MISO

ISOURCE6mA
VOL, MISO,INT ISINK=6mA
3 State Output Leakage
lOUT, MISO INT
TIMING PARAMETERS TA = -40 0 C to +85 0 C
Oscillator Frequency
10-Bit Mode
fSAMPLE

V

Low Level Output

Conversion Tim e
(Including Sample Time)

10-BitMode
8-BitMode

Sample Time (Pre-Encode)

8 Time Constants (8<) Required

14 Oscillator Cycles
12 Oscillator Cycles
First 1.5 Oscillator> 8<

Serial Clock (SCK) Frequency
SCK Pulse Width

Tp

MOSI Setup Time
MOSI Hold Time
MISO Propagation Delay

MHz

150

ns

TDSU

Either SCKA or SCKB
Prior to Leading Edge of TP

60

ns

TDH

After Leading Edge of TP

60

TDOD

200pFLoad
From Trailing SCK Edge

MISO Rise & Fall Time
IDD

1.5

VDD - 5 Volts, Continuous Operation

6-5

ns
100
1.4

::I .....

%ofVDD

Input Leakage
Input Capacitance

rnrn

:i:2
<:::::::>C:::::::x:::::::)<:::::::)(:::::::>

(READ ONLy)

FIGURE 3. TIMING DIAGRAM FOR SERIAL PERIPHERAL INTERFACE
Hardware Interfacing to 68HCOS Controllers
When interfacing the A2 to 68HCOS controllers, set CPHA = 1
and CPOL = (0 or 1) in the SPI control register. Note that
SCK pulses are generated only when data is written to the
SPI Data Register in a 68HCOS. Reading data from or
writing data to the A2 requires writing data to the SPI Data
Register. The data will be ignored by the A2 for read
operations. The read data is available to the 68HCOS in
the SPI Data Register when SPIF is true in the SPI Status
Register.
Hardware Interfacing to Non-68HCOS Controllers
Most popular microcontrollers have a synchronous communications facility which can be adapted to work with the A2.
Those that don't can be easily interfaced using port lines to
synthesize a SPI bus.

is advanced to the Low Data Register of the same channel.
Reading the Low Data Register then increments the read
address to the next (as specified in the CSR) active
channel's High Data Register. Following a read of the last
(closest to 7) active channel's Data Register(s), the address
recycles to the first (closest to 0) active channel's Data
Reg iste r(s).
-

----

\.......

CE - - - - - - " /

MOSI

~

MISO

ADDRESS BYTE

I

DATA BYTE

~

________H~I_-~Z_________«~__R_~_D__J)~--~H-I-~Z---

TRANSFER CYCLE:

2

PHASE:

Software Interface
Reading and writing to the A2 can be performed in either
single byte or multiple byte (burst) modes. Both modes
begin the same way: a positive transition is applied to CE (if
CE is high, it must first be brought low, then returned high);
an address/control byte is transferred (requires 8 clocks on
SCK and 8 bits of data on MOSI); and the first byte of data is
transferred (requires 8 clocks of SCK). In the case of single
byte mode, the transfer is complete. For multiple byte
transfers, each series of 8 pulses on SCK produces another
8 bit transfer (see Figure 4.)

(4a) Single Byte Transfer. (Requires 2 SPI Transfers)

MaSi

~ ADDRESS
BYTE

When transferring multiple bytes of data, the type of transfer
- read or write - is fixed by bit seven of the initial address/
control byte. After the initial data transfer, the address will
automatically be adjusted for each subsequent transfer.
When reading Data Registers in the 8 bit mode, each read
will advance the address by two, to the next (as specified in
the CSR) active channel's Low Data Register. In the 10 bit
mode, following a read of a High Data Register, the address

DATA
BYTE

DATA

•••

MISO~
~
ADDRESS: WRITE ADDR:1
TRANSFER CYCLE:

The format of the address/control byte is shown in Figure S.
The most significant bit is the R/W bit. When R/W is 0, read
operations are to be performed. If R/W is 1, write operations
are to be performed. AO through A4 specify the register to
access. Data Registers are mapped to address $00 through
$OF. The Control and Status Registers are at locations $10
through $13 (see Figure 2.).

tntn

•••

PHASE:

ADDR:1

2

IOATA~

... <8>

ADDR:2 • • •
3

:::I .....

•••

H1a Z

ADDR:N
N+1

•••

(4b) Multiple (N) byte Transfer. (Efficient Device Communication
Requiring N+1 SPI Transfers)
FIGURE 4. TIMING DIAGRAMS FOR (4a) SINGLE BYTE
TRANSFER AND (4b) MULTIPLE (N) BYTE
TRANSFER.
When reading or writing control registers, the address will
increment to the next register after each transfer. Once
address $13 has been reached no more increments are
performed. This facilitates polling of the Status Register
(SR) which is located at address $13. If the A2 remains
selected following a read of SR, each successive 8 bit
transfer will read the SR again without the need for an
address/control byte.

6-7

:i!2
-:c
ceo..

ffia...
tna:
-o..
~a...

CDP68HC68A2
Programming the CDP68HC68A2 Registers
This read/write register is used to select the various modes of
operation of the A2. Bits 6 and 7 are "don't cares" and can be
set as either 1 or o. The functions of bits 0 through 5 are as
follows:

Intlallzlng the A2
The A2 is equipped with a power on reset circuit which clears
the MSR to all O's. ·This ensures that INT is In a high
impedance state and conversions are inhibited. The contents
of all other registers·are unknown until explicitly initialized. No
other provisions are made for resetting the A2.

EXT (External OSCillator): EXT is used to select between an
external or an internal (single pin oscillator) clock source at
pin 1 (OSC) of the A2. If EXT is low, an external clock is
selected and the OSC pin functions as an input. If EXT is
high, an internal clock is selected and the OSC pin functions
as a one pin oscillator. See Figure 7 for typical frequencies of
the internal oscillator.

Systems which can be reset after power up must reset the A2
by explicitly writing O's to the MSR. Designs which utilize the
INT line must be certain that the MSR is cleared, or the A2 is
initialized to a known state,. before enabling interrupts.
It is good practice to include code which initializes the
A2, to a known state, at the earliest practical point. In
systems which utilize INT, if a system reset occurs· after
power-up, A2 initialization code must be executed
before processor interrupts are enabled.

VR (Voltage Reference): VR is used to select the source of
the voltage reference. When VR is 0, VDD is used as the full
scale reference for the ND converter. When VR is 1, the
voltage at AIO serves as the full scale reference for the ND
converter. With VR = 1, the digital reading of any active
channel which exceeds the AIO reference voltage will be
"clipped" to the full scale value of $3FF ($FF for 8 bit mode).

Address/Control Byte
The Address/Control Byte is a dual purpose word which
performs register addressing and read/write control. The
AddresS/Control Byte is the first byte transferred to the A2
following activation of CEo If CE is active, it must first be
brought low, then reactivated prior to transferring an
AddresS/Control Byte.

7

6

5

A4

A3

4

3

I A2

A1

M8 (Eight Bit Mode): This bit selects the 10-bit or 8-bit
mode of operation. A low (0) in this bit enables the 10-bit
mode, while a high (1) enables the 8-bit mode.
IE (Interrupt Enable): IE is used to enable the INT output
function on pin 2. A low (0) disables the interrupt function and
maintains INT in a high impedance state. A high enables the
interrupt function, allowing INT to be driven low at the appropriate times in Modes 1 and 2.

AO

o

2

FIGURE 5. ADDRESS/CONTROL BYTE

The most significant bit (MSB) of the Address/Control byte is
R/W. This bit is used to cntrot the flow of data during the
subsequent SPI data transfers. IfR/W is a 0, reads take place.
If RIW is a 1, writes take place. During read transfers, data is
shifted out on MISO. During writes, data is shifted in on MOSI
and MISO is held in a high impedance state.

M1, MO (Mode Select 1 and 0): These two bits are used to
selectthe conversion mode of the A/D converter. The modes
are as follows:
M1

M2

MODE

0

0

0

DESCRIPTION
Idle

1
1
Single Conversion
0
The least significant five bits (AO through A4) provide the read
1
2
Single Scan
0
address. Bits 5 and 6 are not required and can be sent as
1
Continuous Scan
1
3
either 0 or 1 (O's are assumed throughout this speCification).
When addressing Data Registers in 8 bit mode, AO is interFIGURE 6. CONVERSION MODES
nally forced to a 1. Attempting to read a High Data Register in
8 bit mode will result in a read of the Low Data Register (after
Channel Address Register (CAR)
which the address will advance to the Low Data Register of,
the next active channel).
Address/Control: Not Addressable

CAUTION: When addressing Data Registers, the user
must ensure that the contents of the CAR match the
address portion of the Address/Control Byte. Failure to
do so may result In corrupted data. This condition
is generally met in Modes 1 and 2. When running in
Mode 3 special care must be taken to meet this
requirement. See further explanation under SAR, SR,
Modes, and Applications Information.
Mode Select Register (MSR)
AddresS/Control: (RIW)OO10000 - $10
ReadlWrite: Yes

7

6

EXT

VR

M8

IE

5

4

3

2

M1

MO

o

The CAR contains the address of the next channel to convert
during Modes 1, 2, and 3. During multiple byte reads of the
Data Registers, the CAR contains the address of the channel
to read and is advanced, to the next higher active channel,
following each read. When advancing, the CAR skips any
channel not selected in the CSR. After incrementing to the
highest active channel, the CAR will return to the lowest
active channel.
The CAR is not directly accessible. It can be Jammed via a
write to the SAR or by transmitting an Address/Control Byte
which addresses any Data Register. Note: addressing a
Data Register to set the CAR is valid only under certain
circumstances - see the following boxed caution. When
Jamming the CAR via the SAR, the specified channel does
not need to be selected In the CSR. The CAR's contents are

6-8

CDP68HC68A2
ENC (Enable Conversions): ENC is used to, synchronously, switch on and off the successive approximation A
to D converter. When this bit is set high, the appropriate
conversion operation (as defined in the MSR) is initiated.
Setting the ENC bit low stops the conversion operation. If a
channel is being converted when ENC is cleared, the
conversion of that channel will complete and further
conversions will be inhibited.

read as part of the SR. See the descriptions of the SAR and
the SR for details.
CAUTION: When addressing Data Registers, the user
must ensure that the contents of the CAR match the
address portion of the Address/Control Byte. Failure
to do so may result in corrupted data. This condition
is generally met in Modes 1 and 2. When running in
Mode 3 special care must be taken to meet this
requirement. See further explanation under SAR, SR,
Modes, and Applications Information.

SAE (Starting Address Enable): If the SAR is written to,
with the SAE bit high, the CAR is jammed with the value
defined by CA2, CA 1, and CAD. If SAE is low, the CA2, CA 1,
and CAD bits are ignored.

Channel Select Register (CSR)
Address/Control: (R/W)0010001 - $11
Read/Write: Yes
C7

C6

C5

C4

C3

C2

7

6

5

4

3

2

Cl

CO

o

This read/write register is used to designate the active
analog input channels. Channels which are not active will
be skipped during conversions and multiple byte reads,
unless specifically selected by writing to the SAR. Setting a
bit high in CSR selects the associated channel, while setting
a bit low deselects the channel. Each Cn bit in the CSR
corresponds to an Aln pin on the A2 device. Example:
setting C7 = C4 = 1 and setting all other bits to 0 will select
AI7 and AI4 as inputs to the A/D multiplexer.
Starting Address Register (SAR)
Address/Control: (R/W)OOl 001 0 - $12
Read/Write: Yes

I

ENC

7

6

5

4

3

Fi/L (High/Low): For most applications, the SAR should be
written with Fi/L as a O. In combination with CA2, CA 1, and
CAD, this bit is used to select a specific High or Low Data
Register. Fi/L only has significance in 1O-bit mode. The 10bit read sequence is High Data Register followed by Low
Data Register for each channel read. When jamming the
CAR prior to reads, Fi/L should be set low, unless the user
specifically wants to skip the first High Data Register. When
read, this bit, indicates whether the next Data
Register read will access the High or Low Data Register. In
8-bit mode, Fi/L is ignored by the A2.
Status Register (SR)

I SAE I CA2 I CA 1 I CAD I H/L

I

CA2, CAl, CAO (Channel Address): When writing to the
SAR with SAE high, CA2, CAl, and CAD form a 3 bit
channel address which is used to set the CAR and select
the first channel to be converted or read. Reading the SAR
returns the previously written values for these three bits. To
determine the contents of the CAR a read of the Status
Register (SR) must be performed.

2

Address/Control: 00010011 - $13
Read/Write: Read Only

o

This register is used to enable conversions in all modes and
to set the address of the current channel in the CAR. Prior to,
or simultaneously with, enabling conversions, the CAR must
be set to a known state via the SAR. Once set, the contents of
the CAR determine the first channel to be converted when
conversions are enabled - hence the name "Starting Address
Register". The CAR may be jammed with the number of a
channel which is not selected in the CSR. After the specified
channel is converted, subsequent conversions proceed in
ascending order, skipping channels not selected in the CSR.
Therefore, jamming the CAR with a non-selected channel
number will cause a conversion to be performed on that
channel once and only once.
After stopping a Mode·2 or 3 conversion (by setting ENC
low), the CAR must be jammed to match the channel address
prior to initiating Data Register reads. If an Address/Control
Byte is sent to begin reads from a Data Register other than
the one currently addressed by the CAR, the contents of the
Data Register may be corrupted. If the CAR contents are
known, single or multiple byte reads can be properly made,
by sending a matching Address/Control Byte.
Bits 5 and 6 in the SAR are "don't cares" and can be set to
either D's or l's. The functions of the remaining bits are
as follows:

INT
7

IACC I CIP
6

5

o
4

I CA2 I CAl I CAD I
3

2

0

o

This is a read only register used to monitor the status of the
A to D converter. If an Address/Control Byte of $13 is sent
to the A2, the Status Register will be addressed and will
remain addressed until the CE pin is brought low. This
provides efficient polling of the SR by allowing multiple
reads of the SR with only one Address/Control Byte
transmission.
Bits 0 and 4 of the SR are always read as lows. The
significance of each of the other bits is:
INT (Interrupt): In Modes 1 and 2, this bit is set high under
the same conditions that the INT pin would be activated (see
Conversion Modes). Once set, the INT bit can be cleared be
reading the SR, reading any Data Register, or writing to the
MSR or CSR. The INT bit is not affected by the state of the IE
bit in the MSR.
ACe (All Conversions Complete): When high, this status
bit indicates that conversions have been completed on all
channels selected in the CSR. It is cleared by reading any of
the Data Registers or by writing to the MSR or CSR. In 10bit mode, ACC = 1 implies that the DV bits of all active
channels are true (see Data Registers). This bit is often

6-9

CDP68HC68A2
used in Modes 2 and 3. In Mode 1, ACC will only be set if
conversions are el4J)licitly invoked (via writes to the SAR) for
each channel selected in the CSR.
CIP (Conversion In Progress): This bit is logically high
when a conversion is initiated and goes low when a
conversion completes. In the scanning modes, Modes 2
and 3, CIP will go low momentarily between successive
channels and cannot be used in lieu of ACC in Mode 2.

Two status flags are maintained for each channel. In 10-bit
mode these status flags are provided in the High Data
Register. In 8-bit mOde they are not available to the user.
Their functions are:
DV (Data Valid): DV indicates whether the corresponding
channel has been converted since it was last read. DV is set
upon completion of a conversion on the corresponding
channel. DV is cleared by reading the Data Register or by a
write to the MSR or the CSR.

NOTE: Following a write of $00 to the SAR, to
terminate Mode 3 conversions, CIP may remain high
until cleared with a write to the MSR or the CSR or
with the read 01a Data Register or with a write to the
SAR with ENC or SAE = 1. CIP = 1 is not a true
indication of an ongoing conversion. See "Mode 3 Continuous ·Scan".
CA2, CAl, CAO (Channel Address Register): This three
bit binary number indicates the current contents of the CAR.
The CAR is originally set by the user via the SAR (see SAR).
The CAR is automatically Incremented following reads of
Data Registers and following conversions in the scanning
modes (Modes 2 and 3). The Status Register can be read at
any time. Reading CA2 - CAO during Modes 2 and 3 will
produce changing channel addresses as the conversions
proceed.
Data Registers
Address/Control: OOOOooO(H/l) to 0000111 (H/l) $00 to $OF
Read/Write: Read Only

o

o

o

4

3

2

High
H/l=O

IDV IDovl 0

low
H/l= 1

I 07 I 06 I 05 I 04 I 03 I 02 I 01 I DO I

7

7

6

6

5

5

4

3

2

109 108

0

o

The Data Registers are used to store the results of A to 0
conversioris. There are two registers, a High Data Register
and a low Data Register, associated with each channel.
In 8-blt mode, the High Data Registers are inaccessible,
and each low Data Register holds the 8-bit result of the
most recent conversion of its associated channel. The
values range from $00 (Aln = VSS) to a full scale reading of
$FF. During multiple byte Data Register reads, the address
(held in the CAR) is advanced to the low Data Register of
the next active channel (as specified in the CSR) following
each read.
In 10-blt mode, bits 0 and 1 of the High Data Register
together with the contents ofthe low Data Register hold the
result of the most recent conversion to the associated
channel. The values range from $000 (Aln = Vss) to a full
scale reading of $3FF. During multiple byte Data Register
reads, the address (held in the CAR) is automatically
advanced from the High Data Register to the low Data
Register. Following a read of the low Data Register, the
address advances to the High Data Register of the next
active channel (as specified in the CSR).

NOTE: A write to the SAR does not clear the DV flag
for each channel. This implies that if: conversions
are completed on all registers selected In CSR;
conversions stopped; an incomplete read of the Data
Registers is performed; and conversions reinitiated
with a write to the SAR - some DVs will still be set. In
Mode 2, which terminates when all DVs are true (ACC
goes true), unread channels may not be converted,
unless CSR is written to, before setting ENC.
DOV (Data Overrun): DOV indicates that more than one
conversion has been performed on a channel since it was
last read. This bit is only valid in Modes 1 and 3. DOV is
cleared by reading the Data Register or by performing a
write to the CSR or the MSR.

Conversion Modes of the
CDP68HC68A2
Mode 0 - Idle: On power_up, the MSR is reset to all O's
placing the A2 into Mode O. After power_up, the user can
effectively reset the A2 by selecting Mode 0 via the MSR.
Setting the A2 to Mode 0, at any time. will abort any
current conversions and force the INT pin to a high impedance state. In mode 0, if EXT is high in the MSR, the one pin,
internal oscillator is placed in a low power, shutdown mode
and internal clocking of the A to 0 converter is inhibited. if
EXT is low In the MSR, internal clocking of the A to 0
converter is inhibited.
Mode 1 - Single Conversion: In Mode 1, conversions are
performed on command. After setting Mode 1 in the MSR,
a write to the SAR with ENC high will initiate a conversion
on the channel currently selected by the CAR. Note: this
channel does not have to be active in the CSR. When using
the internal oscillator, the oscillator is enabled. The CIP flag
in the SR will be set when the conversion begins.
Upon completion of the conversion, the INT bit in the SR will
be set, the CIP flag will be cleared, and, if IE is true in the
MSR, the INT pin will be driven low (if all channels specified
in the CSR have been converted since the last Data
Register read the ACC bit in the SR will also be set). Finally,
if it's active, the internal oscillator will be stopped.
Another conversion can be initiated with a write to the SAR.
However, the normal procedure is to read the results of the
first conversion. This does two things: first it clears the INT
flag (the INT pin is returned to a high impedance state);
second a conversion is automatically started on the next
channel selected in the CSR. This read-convert pattern can
be continued indefinitely.
When reading Data Registers in Mode 1, the user can be
certain that the contents of the CAR equal the channel

6-10

CDP68HC68A2
number which was just converted. Thus the Address/
Control Byte sent prior to the read will automatically match
the CAR. If a read from a Data Register, other than the one
just converted, is performed, the CAR must be set to the
desired register prior to sending the Address/Control Byte.
Setting CAR is done by writing the SAR with ENC = 0,
SAE = 1, and the CA2 - CAO bits equal to the desired
channel.
Mode 2 - Single Scan: In Mode 2, when ENC is set in the
SAR, conversions are performed on all channels selected in
the CSR. Conversions begin on the channel specified by the
CAR (this channel does not have to be active in the CSR)
and proceed in ascending order until all channels selected
in the CSR have been converted. If the starting channel
is not the lowest active channel, when the highest active
channel is done converting, the CAR advances to the lowest
active channel and continues from that point until all
channels have been converted once.

Prematurely stopping the conversions leaves the CAR in an
unknown state. One remaining task, before Data Registers
are read, is to be certain the contents of the CAR match the
address sent in the Address/Control Byte. This is done be
jamming the CAR with a write to the SAR with ENC = 0,
SAE = 1, and CA2 - CAO equal to the desired channel
address.
Mode 3 - Continuous Scan: In Mode 3, when ENC is set
in the SAR, conversions are performed on all channels
selected in the CSR. Conversions begin on the channel
specified by the CAR (this channel does not have to be
active in the CSR) and proceed in ascending order for all
channels selected in the CSR. Each time the highest active
channel is done converting, the CAR advances to the lowest
active channel and continues from that point.
When ENC is set in the SAR, the internal clock is activated
(if selected) and conversions begin.

When ENC is set in the SAR, the internal clock is activated
(if selected), the CIP flag is set in the SR, and conversions
begin. The CIP flag doesn't remain high, as it momentarily
goes low between each channel conversion.

When all channels have been converted one time the ACC flag
in the SR is set. This is the only valid status flag in Mode 3.
The CIP flag is not valid in Mode 3. The INT flag and the INT
pin are both held in a disabled state during Mode 3.

When all channels have been converted the INT and ACC
flags in the SR are set, the INT pin is driven low (If IE is true
in the MSR), the CIP flag is cleared, and, if active, the
internal oscillator is disabled.

Data Registers cannot be read until Mode 3 conversions
have been termInated. There are two ways to stop
conversons in Mode 3. The first is to perform any "abort"
action (see Abort Modes). Performing an abort, may
produce spurious conversion values. The second, and
preferred means to stop a Mode 3 conversion, is to clear the
ENC bit by writing a $00 to the SAR. Clearing ENC will
synchronously stop conversions at the end of the current
conversion. CIP Is not valid following the clearing of ENC.
The CIP flag cannot be used to determine when the current
conversion is complete. Instead, a time delay equal to
one conversion time must be built into the software. The
appropriate delay will ensure the last conversion is
complete before Data Register reads begin.

Data Registers can safely be read after all channels have
been converted. If the starting channel was a channel active
in the CSR then the CAR will once again be pointing to that
channel (providing all channels had been read or CSR or
MSR written since the last set of conversions - see Note
below). If a read from a Data Register, other than the one
first converted, is performed, the CAR must be set to the
desired register prior to sending the Address/Control Byte.
Setting CAR is done by writing the SAR with ENC = 0,
SAE = 1, and the CA2 - CAO bits equal to the desired
channel.
NOTE: a write to the SAR does not clear the DV flag
for each channel. This implies that if: conversions
are completed on all registers selected in CSR;
conversions stopped; an incomplete read of the Data
Registers is performed; and conversions reinitiated
with a write to the SAR - some DVs will still be set. In
Mode 2, which terminates when all DVs are true (ACC
goes true), unread channels may not be converted
unless CSR is written to before setting ENC.

The Data Registers can safely be read after ENC is cleared
and one conversion time has elapsed. One remaining task
is to be certain the contents of the CAR match the address
sent In the Address/Control Byte. This is done be jamming
the CAR with a write to the SAR with ENC = 0, SAE = 1, and
CA2 - CAO equal to the desired channel address.
Abort Modes - Any active mode can be aborted by anyone
of the following means:
1. A write to the MSR

There are two ways to prematurely stop conversons in
Mode 2. The first is to perform any "abort" action (see Abort
Modes). Performing an abort, may produce spurious
conversion values. The second, and preferred means to
stop a Mode 2 conversion, is to clear the ENC bit by writing
a $00 to the SAR. Clearing ENC will synchronously stop
conversions at the end of the current conversion. When
prematurely stopping coversions, CIP is not valid. The
CIP flag cannot be used to determine when the current
conversion is complete. Instead, a time delay equal to one
conversion time must be built into the software. The
appropriate delay will ensure the last conversion is
complete before Data Register reads begin.

2. A write to the CSR
3. A write to the SAR with ENC and/or SAE

=1

4. A read of any Data Register
The contents of Data Registers are not guaranteed
following an abort. Writing a $00 to the MSR is equivalent to
a reset.
To synchronously stop conversions in Modes 2 or 3 set the
SAR to $00 (See Mode 2 and Mode 3).

6-11

CDP68HC68A2
Analog Inputs
Shown in Figure 6 is a simplified equivalent circuit representing the input to the Analog to Digital Converter through
the multiplexer as seen from each Aln pin.

Vce

81: is required during the first 1.5 sample clock cycles to
sufficiently encode 10-blt conversion. Therefore, 1.5 TS ~
81: and TS ~ 5.33 REFFC.
TS = 1lfSAMPLE, then fSAMPLE ~ [5.33 (RS
4oopFI-1, fSAMPLE 5 (4.688 x 108)/Rs + 850).

850)

=

01

R1

ss.n.

SIGNAL
INPUT

For example, if RS
1000, fSAMPLE must be less than
432kHz, and TS = 2.3I1S. This yields a 10-bit conversion
time of 3211S. An internal COSC ~ 68pF, see chart.

C1
400pF

V1
2.5V

02

The maximum frequency is limited by the device specification (see characteristics) and by the (RS) Series input
resistance:
RS

5 [(4.688 x 108)lfSAMPLE1- 850.

For example, for a 1MHz sample clock RS max

Agure 8 shows a simplified model of the Schmitt oscillator
used to help familiarize the user with Its operation. Figure 7
shows typical Internal oscillator frequency versus
capaCitance at 5 volts and 250 C.

01

>-______~------

= 3850.

The Internal Schmitt Oscillator

(a) During Sample Time

SIGNAL
INPUT

+

OPEN
CIRCUIT

C(pF)

C(pF)

f(MHz)

18

1.0-3.0

218

0.148-.40

38

0.65-2.0

318

0.111 -.25

48

0.54 -1.6

409

0.107-.23

68

0.38-1.1

528

0.072 - .17

118

0.26-.75

1018

0.040-.10

02

(b) During Hold and Idle Time

f(MHz)

FIGURE 7. TYPICAL OSCILLATOR FREQUENCY vs.
CAPACITANCE AT VDD = 5V, TA = 250 C

FIGURE 6. EQUIVALENT CIRCUIT FOR SIGNAL INPUT
(a) DURING SAMPLE TIME AND (b) DURING
HOLD AND IDLE TIME

Due to the nature of the switched capacitor array used by
the successive approximation A to D, two important points
are noted here:

When measuring the oscillator, probe capacitance will
affect frequency. An alternative to direct frequency
measurement of the oscillator input is to measure the
interval between successive interrupts in modes 1 and 2.

1. A property of a capacitive input is the intrinsic sample
and hold function. This provides all that is necessary to
accurately sample a point on an input waveform within
the input bandwidth shown in the speCifications (under
1.5 conversion oscillator cycles).
2. The input to the capaCitor network appears as an RC
network with a time constant and therefore places
constraints on the source impedance. The charging time
and therefore the accuracy of the conversion will be
adversely affected by increasing the source impedance.
It is recommended to set the conversion oscillator frequency
in accordance with the input impedance In order to allow
sufficient time (the 1.5 Tosc cycles) to sample a ch,1nging
waveform through the modeled input low pass filter network
which Includes the Input source in a series circuit with the
internal impedance.

..L EXTERNAl.
.....
1 CAP

330pF
1

~

vss

The time constant (1:) for the input network is REFFCNET.
REFF
1:

=

= RS + RNET, CNET = 400pF, and RNET = 500.

REFFCNET

FIGURE 8. EQUIVALENT CIRCUIT FOR OSCILLATOR INPUT

= (RS + 500) 400pF.
6-12

CDP68HC68A2
Applications Examples
The following code samples are based on a CDP68HC05
processor. The listings were generated with the Harris
HASM5 assembler for the CDP68HC05 processor. The
examples are based on a system which has CE of the

A2 connected to PAO of the CDP68HC05. Some of the
fundamental SPI communication routines called by the
examples are shown first.

SPI Communication Routines
***************************************************************
HCA2.inc
* File:
Include file with 68HC05A2 definitions and
common subroutines

*
* Date:

Mon

09-24-1990

***************************************************************
***************************************************************
Map of 68HC05 Hardware Registers

***************************************************************
0000

Section

Registers,$OOOO

0000
0001
0002
0003
0004
0005
0006
0007

PortA
PortB
PortC
PortD
DDRA
DDRB
DDRC
DDRD

ds
ds
ds
ds
ds
ds
ds
ds

0008

_Free1

ds

2

SPCR
_SPE
_MSTR
_CPHA

ds
equ
equ
equ

1
01000000b
00010000b
00000100b

;SPI Control Register
;SPI Enable bit
;SPI Master Mode bit
;SPI CPHA = 1 bit

SPSR
_SPIF
_SPIF

ds
equ
equ

1
10000000b
7

;SPI Status Register
;SPI Flag bit for ANDs, CMPs, etc.
;SPI Flag bit for BRSETs & BRCLRs

SPDR

ds

OOOA
0040
0010
0004
OOOB
0080
0007
OOOC

64
16
4

= 128
7

;Port A

;SPI Data Register

=» ....
""""

:~

c(w

-::c

ffia..
""cc
-w
g,a..

-

6-13

CDP68HC68A2
***************************************************************

*

A2 Constants

***************************************************************
HC68A2

equ

0

;A2 is connected to bit 0 of Port A

A2_Write

equ

$80

;Write bit for A2's Address/Control Byte

16
32
16
8
4
0
1
2
3

A2_MSR
A2_notEXT
A2_VR
A2_M8
A2_IE
A2_ModeO
A2_Mode1
A2_Mode2
A2_Mode3

equ
equ
equ
equ
equ
equ
equ
equ
equ

$10
100000b
010000b
001000b
000100b
0
1
2
3

;Mode Select Register

0011

17

A2_CSR

equ

$11

;Channel Select Register

0012
0080
0010

18
= 128
16

A2_SAR
A2_ENC
A2_SAE

equ
equ
equ

$12
;StartAddress Register
10000000b
00010000b

0013
0007
0006
0005
OOOE

19
7
6
5
14

A2_SR
A2_INT
A2-ACC
A2_CIP
A2_CARm

equ
equ
equ
equ
equ

$13
;Status Register
7
6
5
00001110b ;CA2 - CAO mask

0000

0

0080

= 128

0010
0020
0010
0008
0004
0000
0001
0002
0003

***************************************************************
Common Subroutines

***************************************************************
0400

Section

0400 A654
0402 B70A
0404 81

Set-A2_SPI_Mode
*_SPE+ _MSTR+_CPHA ;Set SPI to Master with CPHA=1,
Ida
sta
SPCR
;CPOL=O
rts

SPI_Xmit
sta
SPI_wait
0407 OFOBFD
brclr
040A B60C
Ida
040C 81
rts
0405

Su broutines,$0400

B70C

SPDR

;send A to SPI device

_SPIF, SPSR, SPI_wait
SPDR

;wait until transmit complete
;read the returned value into A

HC68A2,PortA
HC68A2,PortA

;deselect then reselect the A2

040D 1100
040F 1000
0411 81

Select-A2
bclr
bset
rts

0412
0414
0416

Initialize-A2
bclr
HC68A2,PortA
bset HC68A2,DDRA
rts

1100
1004
81

;turn on PAO output pin to drive
;the A2's CE pin

6-14

CDP68HC68A2
Running the A2 in Mode 1

--*._•••••._••••••••__._•••••••••

* ••**••• _-_••*** •••••
*********
* File:
A2MODE1.S
Demo program for 68HC68A2 in Mode 1
*

*
* Date:

Mon

09-24-1990

*******************•••******.*.*******••• ****.******** •••••••••
#include

HCA2.inc

;common routines

************* Main routine to set Mode 1 and read each channell time
Section

0100
0100 CD0412
0103 CD0400

0106 CD040D
0109 A690
010B CD040S
010E
0110
0113
011S
0118
011A

CD0136
CD040D
9F
48
CD040S
CD040S

isr
jsr

DoConversions
isr
Ida
jsr

A629
CD040S
A6FF
CD040S
A690
CD040S

0110 AEOO
011F
0122
012S
0126
0127
012A

main

Ida
jsr
Ida
jsr
Ida
jsr
ReadResults
Idx
Read Loop
jsr
jsr
txa
Isla
jsr
jsr

code,$Ol00
InitializeJ2
SetJ2_SPI_Mode

;turnonPAO
;Setup the 68HCOS SPI control

;Set the A2's CE
;Send Address/Control Byte to ...
;write to the A2's MSR
;Select Mode 1 and internal clock
#A2--'1otEXT+A2_Model +A2_M8 ;and 8-bit mode,
SPI-,emit

;SettheA2's CE
;send Address/Control Byte to ...
;read channel 0

#8

;use X as loop counter

SPI_xmit

;read the Data Register
;do something with the read data

ReadLoop

;decrement the loop counter
;if not done read another channel

HC68A2,PortA

;deselect the A2

Finis
014D 1100
014F 81

bclr
rts

6-17

enen

::1-1

:~
ce .....

-:c
ffiD..
en a:

- .....
~D..

CDP68HC68A2
Summary of CDP68HC68A2 Registers
Address/Control Byte

7
R/W:

6

5

Status Register (SR)
A4

A3

A2

4

3

2

A1

AO

o
liNT

O=read
1 =write

Address/Control: (R/W)001ooo0 - $10
Read/Write: Yes

I - I - I EXT I VR I M8
6

IACC I CIP I

7

Mode Select Register (MSR)

7

Address/Control: 00010011 - $13
Read/Write: Read Only

5

4

IE

M1

2

3

MO
0

5

6

0

4

I CA2 I CA1 I CAO I

0

2

o

3

INT:

1 = Interrupt condition has occurred

ACC:

1 = Ail Conversions Complete

CIP:

1 = Conversion In Progress

CA2,
CA1,
CAO

Value of CAR

EXT:

0 = external oscillator
1 = internal, one-pin oscillator

Data Registers

VR:

0 = VDD is positive reference
1 = AIO is positive reference

Address/Control: OOOOOOO(H/l) to 0000111 (H/l) $00 to $OF
Read/Write: Read Only

M8:

0 = 1O-bit Mode
1 = 8-bit Mode

IE:

High
H/l=O

0 = INT pin held in high impedance
1 = INT pin is active

M1,MO: 00 =
01 =
10 =
11 =

low
H/l=1

Idle Mode
Single Conversion
Single Scan
Continuous Scan

Channel Select Register (CSR)
Address/Control: (R/W)001ooo1 - $11
Read/Write: Yes

C7

C6

C5

C4

C3

C2

7

6

5

4

3

2

C1

CO

o

Starting Address Register (SAR)
Address/Control: (R/W)001oo10 - $12
Read/Write: Yes

IENC I - I - I SAE I CA2 I CA1 I CAO I H/l
7

6

5

4

3

2

o

ENC: 0 = disable conversions
1 =enable conversions
SAE:

0 = ignore CA2, CA 1, and CAO
1 = jam CAR with CA2, CA 1, and CAO

CA2,
CA1,
CAO

3 bit number to jam into CAR when
SAE = 1

H/l:

This bit should always be set to 0
0= High Data Register
1 = low Data Register

6-18

10V loovi
7

109 los I

0

o

o

o

6

5

4

3

2

o

6

5

4

3

2

o

mHARRIS

CDP68HC68P1
CMOS Single Port Input/Output

January 1991

Pinout

Features
• Fully Static Operation

PACKAGE TYPES D, E AND M
TOP VIEW

• Operating Voltage Range 3-6V

10 0
10,

• Compatible with Harris/Motorola SPI Bus

• 2 External Address Pins Tied to VDD or VSS to Allow Up to 4 Devices
to Share the Same Chip Enable
• Versatile Bit-Set and Bit-Clear Capability
• Accepts Either SCK Clock Polarity - SCK Voltage Level Is Latched
When chip Enable Goes Active

MI50

,.

IS

VDD

'5

0'
02

MQSI

13

03

seK

'2

CE

11

D'
05

DO

'0

DS
D7

Vss

• All Inputs are Schmitt-Trigger
• 8-Bit I/O Port - Each Bit can be Individually Programmed as an Input
or Output Via an 8-Bit Data Direction Register
• Programmable On Board Comparator
• Simultaneous Transfer of Compare Information to CPU During Read or
Write - Separate Access Not Required

Description
The single port I/O is a serially addressed 8 bit InpuVOutput
port that allows byte ~r individual bit control. It consists of
three registers, an output buffer and control logic. Data is
shifted in and out of the port via a shift register that utilizes
the SPI (Serial Peripheral Interface) bus. The I/O port data
flow is controlled by the Data Direction Register and data is
stored in the Data Register that outputs or senses the logic
levels at the buffered I/O pins. All inputs, including the serial
interface are Schmitt triggered. The device also features a
compare function that compares the data register and port

pin values for 4 programmable conditions and sets a software accessible flag if the condition is satisfied. The user
also has the option of bit-set or bit-clear when writing to the
data register.
The CDP68HC68P1 is supplied in 16 lead, hermetic, dual in
line sidebrazed ceramic (0 suffix), 16 lead dual in line
plastic (E suffix) and 16 lead, surface mount, (small outline),
(M suffix) packages.

Maximum Ratings Absolute Maximum Values
DC Supply Voltage Range, (VDD) ••.••••••.•••••••• -O.5V to +7V
(Voltage Referenced to VSS Terminal)
Input Voltage Range, All Inputs •..•••....•... -O.5V to VDD +O.5V
DC Input Current, Any One Input. .•.•..•••••....••..••.• ±1 OmA
Power Dissipation Per Package (PO)
TA =-400 C to +60 0 C (Package Type E) ......••••.... 500mW
TA = +600 C to +85 0 C (Package Type E) •••••. Derate linearly at
12mW;oC to 200mW
TA =-550 C to +100 0 C (Package Type D) ••••••••••.•• 500mW
TA = +1 OOoC to +125 0 C (Package Type D) .•• Derate linearly at
2mW/oC to 200mW
TA = -400 C to +600 C (Package Type M)* •••••.•••••.• 300mW
TA = +600 C to +850 C (Package Type M)* •••• Derate Linearly at
5mW/oC to 175mW

Device Dissipation Per Output Transistor . • • • • . . • • • • . . .. 100mW
TA = Full Package Temperature Range (All Package Types)
Operating Temperature Range (TA)
Package Type 0 ..••..••••.•....•••••...... -55 0 C to +125 0 C
Package Type E, M ••..••..•••••.•••...•••.. -550 C to +850 C
Storage Temperature Range (TSTG) •••.•....• -650 C to +150 0 C
Lead Temperature (During Soldering) •.••...•••..•••••• +2650 C
At Distance 1/16 ± 1/32 In. (1.59 ± 0.79mm) From Case for
lOs Max

*Prlnted circuit board mount: 57mm x 57mm minimum area x 1.6mm thick Gl 0 epoxy glass, or equivalent.

Copyright

©

Harris Corporation 1991

File Number
6-19

1858.1

CDP68HC68P1
RECOMMENDED OPERATING CONDITIONS AT TA =-40° to+8SoC
For maximum reliability, operating conditions should be selected so that operation Is always within the following ranges:
LIMITS
CHARACTERISTIC

ALL TYPES

UNITS

MIN.

MAX.

3

6

1.05

Voo = 4.5 V

-

V,H

-

Voo + 0.3

V,L

-0.3

-

DC Operating Voltage Range
Serial Clock Frequency

V

fSCK

Voo= 3 V

2.1

MHz

Input Voltage Range

M O S I - - - - -....

MISO

CE-----~

101
SCK
100

======::j

INPUT/OUTPUT

!

00-07

92CM-40404

Fig. 1 - Single port I/O block diagram.

CoP6BHC6BPt

110 PORT

DATA IN

DATA
IN lOUT

DATA OUT
CLOCK

10 1

92CS-40405

Fig. 2 - Single port I/O.

6-20

V

CDP68HC68P1
STATIC ELECTRICAL CHARACTERISTICS AT TA = -40 to +85°C, Voo = 3.3 V ± 10%, Except as Noted
LIMITS
UNITS

CONDITIONS

CHARACTERISTIC

MIN.

TYP.-

MAX.

Standby Device Current

loos

-

1

15

Output Voltage High Level

VOH

IOH = -0.4 mA, Voo = 3 V

2.7

-

Output Voltage Low Level

VOL

IOL = 0.4 mA, Voo = 3 V

-

-

-

pA

0.3

Input Voltage
00-07
Positive Trigger Threshold

Vp

-

1.85

Negative Trigger Threshold

VN

0.85

Hysteresis

V,H

-

0.85

-

2.4
1.35
1.25

V

Input Voltage

IDO, 101, MOSI, SCK, CE
Positive Trigger Threshold

Vp

Negative Trigger Threshold

VN

Hysteresis

V,H

Input Leakage Current

-

liN

3-State Output Leakage
Current
Operating Device Current
Input Capacitance

louT

-

1.9

0.8
0.5

-

0.95

-

-

±1

-

-

±10

1.3

1.2

pA

IOPER #

V,N = V'L, V,H

-

0.1

1

mA

C'N

V,N = 0 V, f= 1 MHz, TA= 25°C

-

4

6

pF

- Typical values are for TA = 25° C and nominal Voo.

# Outputs open circuited; cycle time = Min. teyel., duty = 100%.

STATIC ELECTRICAL CHARACTERISTICS AT TA = -40 to +85°C, Voo = 5 V ± 10%, Except as Noted
LIMITS
CONDITIONS

CHARACTERISTIC

UNITS
MIN.

TYP.-

MAX.

loos
VOH

-

-

1

15

Output Voltage High Level

IOH = -1.6 mA, Voo = 4.5 V

3.7

-

-

Output Voltage Low Level

VOL

IOL = 1.6 mA, Voo = 4.5 V

-

0.4

Output Voltage High Level

VOH

IOH :5 20 pA, Voo = 4.5 V

4.4

Output Voltage Low Level

VOL

IOL :5 20 pA, Voo = 4.5 V

-

-

3.05

3.85

Standby Device Current

pA

rnrn
:::1--,

::!
"' ...
-::c
ffia..
-g;a.....

0.1

rna:

Input Voltage
00-07
Vp

-

2.15

Negative Trigger Threshold

VN
V,H

-

1.35

Hysteresis

Positive Trigger Threshold

0.8

2

V

1.2

Input Voltage
100, ID1.MOSI, SCK, CE
Positive Trigger Threshold

Vp

-

3.15

Negative Trigger Threshold

VN

1.7

-

Hysteresis

V,H

1.3

-

1.7

-

-

±1

lOUT

-

-

±10

IOPER#

V,N = V'L, V,H

-

0.2

2

mA

CIN

V,N = 0 V, f = 1 MHz, T A = 25° C

-

4

6

pF

Input Leakage Current

liN

3-State Output Leakage
Current
Operating Device Current
Input Capacitance

- Typical values are for TA = 25°C and nominal Voo.

2.25

pA

# Outputs open circuited; cycle time = Min. tcyel., duty = 100%.

6-21

•

CDP68HC68P1

cr----....

SHIFT 1~;rtW~~y

~"

SCK
(CPOL=11~
CE---~

\
SHLJW::1

SCK~

(CPOL=O 1

MOSI~SB
MSB - I
OR
MISO
92CS-40397
NOTE:
CPOLAND CPHA ARE BITS IN THE CDP68HC05C4 and CDP68HC05D2
MCU CONTROL REGISTER AND DETERMINE INACTIVE CLOCK
POLARITY AND PHASE. CPHA MUST ALWAYS EOUAl1.

Fig. 3 - Data transfers utilizing clock input.

Introduction

The single port I/O is serially accessed via a 3wire plus chip
enable synchronous bus. It features 8 data pins that are
programmed as inputs oroutputs. Serial access consists of
a two-byte operation. The first byte shifted in is the control
byte that configures the device. The second byte transferred
is the data byte that is read from or written to the data
register or data direction register. This data byte can also be
programmed to act as a mask to set or clear individual bits.
Functional Description

The si~gle ~ort I/O consists of three byte-wide registers,
(data direction, data and shift) an input/output buffer and
control logic circuitry. (See fig. 1, block diagram). Data is
transferred between the I/O data and data direction registers
via the shift register. Once the I/O port is selected, the first
byt~ shifted in to the shift register is the control byte that
reglste~ selects, (the Data or Data direction register),
determines data transfer direction (read or write) and sets
the compare feature and function (mask or data) of the byte
immediately following the control byte, the data byte. (See
Addressing the Single Port I/O) Each bit of the data register
may be individually programmed as an input or output. A
!ogic low i~ a ?ata direction bit programs that pin as an
Input, a logiC high makes it an output. A read operation of
data register pins programmed as inputs reflects the current
logic level present at the buffered port pins. A read operation
of those data register pins programmed as outputs indicates
the last value written to that location. At power-up, all port

pins are configured as unterminated inputs. Two chip
identify pins are used to allow up to 41/0 ports to share the
same Chip enable Signal. The first two bits shifted in are
compared with the hardwired levels at the chip identify pins
to enable the selected I/O for serial data transfer. Note that
when chip enable becomes true, the compare flag is latched
for all devices sharing the same chip enable.
Compare Function

The value of a port pin (00-07), configured as an input, is
compared with the corresponding bit value (ORO-DR?)
stored in the Data Register. Pins configured as outputs are
assumed to have the same value as the corresponding bit
stored in the Data Register. The compare function is
programmed via C01 and COO (CM1, CMO) of the Address
Byte. The following values for CM1 and CMOwili sense one
of four separate conditions:
CMl

CMO

0
0
1
1

0
1
0
1

Condition

-

at
all
all
at

least one non-match
match
are non-match
least one match

The compare flag is set to one when the programmed
condition is satisfied. Otherwise, the flag is cleared to zero.
The compare~g is latched when the device is enabled (a
transition of CE from "High" to "Low").

6-22

CDP68HC68P 1
Data Format
and DF1) change the interpetation of this data as listed
below. Note that one or more bits can 'be set or cleared in
either register without having to write to bits not requiring
change.

During write operations, the data byte that follows the
control byte is normally the data word that is transferred to
the data ordata direction register. Control bits 2 and 3 (DFO

CO2

C03
DF1

DFO

OPERATION

o

X

Data following the control word will
be written to the selected register.
Data following the control word is
a mask. Those bits which are a 1
will cause that register flip-flop to
be cleared to O. Those which are
a 0 will cause that register flip-flop
to be unchanged.
Data following the control word is
a mask. Those bits which are a 1
will cause that register flip-flop to
be set to 1; those which are a 0
will cause that register flip-flop
to be unchanged.

o

for example,

DATA

PREVIOUS
REGISTER
VALUE

NEW
REGISTER
VALUE

11110000
11110000
11110000
00000000

10101010
10101010
10101010
10101010

11110000
11111010
00001010
10101010

CONTROL
C07 COS COS 1 0 X C01
C07 COS COS 1 1 1 C01
C07 COS COS 1 1 0 C01
C07 COS COS11 X C01

COO
COO
COO
COO

X = Don't Care
Addressing the Single Port I/O
When the 1/0 port is selected by bringing the chip enable
pin low, the logic level at the SCK input is sampled to
determine the internal latching and shift polarity for input
and output signals on the SPI. (See Fig. 3).

The Serial Peripheral Interface (SPI) utilized by the 110 Port
is a serial synchronous bus for control and data transfers. It
consists of a SCK clock input pin that shifts data out of the
1/0 port (MISO, MASTER IN, SLAVE OUT) and latches data
presented at the input pin, MOSI (master out, slave in). Data
Is transferred most significant bit first There is one SCK clock
for each bit transferred and bits are transferred in groups of
eight.

The first byte shifted in when the chip is selected is always
the control byte followed by one or more bytes that become
data or a mask for the data and data direction register. As
the control byte is being shifted in one the MOSlline, data
on the MOSI line shifts out. (See Fig. 4).

ce---,
SCK
OR
SCK
MOSI
MISO

Z

C07

C06

cos

coo

C03

C02

C01

Z

Z

C07

C06

cos

coo

C03

coo

OUTPUT

x . DON'T CARE
Z

HIGH IMPEDANCE
- COMPARE FLAG

92CS- 40400

Fig. 4 - Control byte.

6-23

INPUT

CDP68HC68P1
C07 (101), C06 (100):

C03 (OF1), C02 (OFO); Data Format Bits. These have
meaning only when R/W is high. During a write operation,
DF1 and DFO control how the byte following the control
word is·interpret~d. See "DATA FORMAT".

Chip-Identify bits

COS. (RS): Register Select. When RS is low, the data
register is selected. When RS is high, the Direction Register
is selected.

C01 (CM1), COO (CMO): Compare Mode Select. These bits
select one offourevents which will setthe internal Condition
Flag. (See "COMPARE OPERATION")

C04 (R/w); Read/Write. Low when data is to be transferred
from the SPIIIO to the CPU (read) and high when the 110 is
receiving data from the CPU (write).

Read Operation

chip-selected 110 sends compare information followed by
one or more data bytes on the MISOline.

During a read operation, the CPU transfers data from the
I/O by first sending a control byte on. the MOSlline while the

~~~----------------------------.-------------~
xxxxxxxx
coo
C07
Z

MOSI
MISO Z

C06
Z

COS
C07

0
C06

C03

C02
0

cos

C01
C03

8-BIT DATA WORD

x = DON'T CARE
Z
•

~
~

92CS - 40401

HIGH IMPEDANCE
COMPARE FLAG

Fig. 5 - Read bytes.

The selected register will be continuously read if CE is held
low after the first data byte is shifted out.
Write Operation

During a write operation, the data byte follows the control
byte for the selected register. While this byte is being shifted
in, old data from that register is shifted out. If CE remains

low after the data byte is shifted in, MISO becomes high
impedance and the new data is placed in the selected
register.

~~--~--------------------------------~--------------------coo
cos
MOSI
MISO Z

C07
Z

COG
Z

C07

1
C06

C03

C01
C03

C02
1

cos

8-BIT DATA WORD
PREVIOUS 8·BIT WORD

Z ~ HIGH IMPEDANCE
•

~

92CS-40403

COMPARE FLAG.

At the time thaeighth data bit is strobed into the data pins
(00-07) will change as indicated in Fig. 7.
Fig. 6 - Write bytes.

MOSI • • •
SCK

03

01

02

DO

I ...

•••

00-07

'::"='---======~""'--""'::::O'--~==::N"'EW';-:"':
'32CS-40402

Fig. 7 - Port-pin data changes.

Pin Description

100,101

MOSI

Chip identify pins, normally tied to VDD or Vss. The 4
possible combinations of these pins allow 4 1I0s to share a
common chip enable. When the levels at these pins match
those of the identify bits in the control word, the serial bus is
enabled. The chip identify pins will retain their previous
logic state if the lines driving them become Hi-Z.
MISO

Master-out, Slave in pin. Data bytes are shifted in at this pin
most significant bit first. This pin will retain its previous
logic state if its driving line becomes Hi-Z.

Master-in, Slave out pin. Data bytes are shifted out at this
pin most significant bit first. When the chip enable Signal is
high, this pin is Hi-Z.

SCK
Serial clock input. This input causes serial data to be
latched from the MOSI input and shifted out on the MISO
output.

6-24

CDP68HC68P1
CE

00-07

A negative chip enable input. A high to low transition on this
pin latches the inactive SCK polarity and compare flag and
indicates the start of a data transfer. The serial interface
logic is enabled only when CE is low. This pin will retain its
previous logic state if its driving line becomes Hi-Z.

I/O Port pins. Individual programmable inputs or outputs.
Voo and Vss
Positive and negative power supply line.
All pins except the power supply lines and MISO have
Schmitt-trigger buffered inputs.

DYNAMIC ELECTRICAL CHARACTERISTICS - BUS TIMING Voo
See Figs. 8 and 9.

± 10%, Vss =0 V dc, TA =-40· to +85°C, CL =200 pF.
LIMITS (ALL TYPES)

CHARACTERISTIC

Voo = 3.3 V
MIN.

Voo = 5 V

UNITS

MAX.

MIN.

MAX.

-

Chip Enable Set-Up Time

tEvev

200

-

100

Chip Enable after Clock Hold Time

tevEx

250

-

125

-

Clock Width High

tWH

400

-

200

-

Clock Width Low

IWL

400

-

200

-

Data In to Clock Set-Up Time

tovev

200

-

100

-

Data In after Clock Hold Time

levox

200

-

100

Clock to Data Propagation Delay

tcvov

-

200

-

100

Chip Disable to Output High Z

texoz

-

200

-

100

-

Output Rise Time

I,

......

200

t,

-

200

-

100

Output Fall Time

200

-

100

200

-

Clock to Data Out Active

tevox

Clock Recovery Time

tREe

ns

100
-

200

•-.
.,..,.
=» ....
:~

MISO

HIZ

~ll

COMPARE

FLAG

'GQ.

06

--II--t"t,

.... 1

COO

07

06

::
1

SCK

92CM-40398

Fig.-S - Write cycle timing waveforms.

6-25

cCw

DO

~

CCQ..

~a:

-w

~Q..
DO

X
...__x__

~

CDP68HC68Pt
x

--=.:..:....=--___--+-:"l-=.:......J",,;='-t:

MISO _ _ _

COMPARE

FLAG

~~-=-DO=-_...,.,F-=
I EXQZ

SCK

IEVCV
92CM-40399

Fig. 9 - Read cycle tIming waveforms.

6-26

m

HARRIS

CDP68HC68P2

PRELIMINARY

CMOS Octal
Serial Solenoid Driver

January 1991

Pinout

Features

PACKAGE TYPE Z
TOP VIEW

• Eight Open Collector Drivers Capable Of Driving Up
To O.SA Per Output.
•
•
•
•
•

Transient Protection
Current Limiting
Individual Output Latch
Individual Fault Unlatch
Individual Fault Feedback

•
•
•
•

Common Reset Line
High Voltage Power BiMOS
Automotive Temperature Range
For Inductive or Lamp Loads

OUTPUT
OUTPUT
OUTPUT
OUTPUT
RESET
V DD
MISO

4
5
6
7

vss
MOSI
SCK

CE

OUTPUT  3V

tPHL

Tum-On Delay

10 = 500mA, No Reactive Load

IpLH

Tum-Off Delay

10 = 500mA, No Reactive Load

Fault Reference Voltage

Output Programmed ON,
Fault Detected ifVO > VOREF

Fault Reset Delay
(Aller CE L to H Transition)

See Figure 2

Output OFF Voltage

Output Programmed OFF, Output Pin Aoating

10 LIMIT

VOREF
tUD
VOFF

1.05

-

A

-

10

lIS

10

I'S

1.62

1.98

V

75

250

I'S

-

1.0

V

LOGIC INPUTS (MOSI, CE, SCK And RESET)
VT-

Threshold Voltage at Failing Edge

VDD=5V:l:10%

0.2VDD

-

V

VT+

Threshold Voltage at Rising Edge

VDD=5V:l:10%

-

O·7VDD

V

Hysteresis Voltage

VT+-VT-

0.85

2.25

V

II

Input Current

VDO = 5.50V, 0 < VI < VOD

-10

+10

!lA

CI

Input Capacitance

O .....

FIGURE 2A. DATA AND CLOCK TIMING

""cC
cCw

..... c:

-::z::

(INP~~ -iF-----------------l~--------_'1
LJ2)
.1 •
(1)

ffie...

"'cc
-w
~e...

(3)

SCK
(INPUT)

MISO
(OUTPUT)

MOSI
(INPUT)
FAULT - INDUCE
TURN -OFF
DRIVER
OUTPUT

OLD

FIGURE 2B. SPI TIMING

6-29

CDP68HC68P2
Signal Descriptions
Output 0 - Output 7 - Power Output Drivers. The input
and output bits corresponding to Output 0 thru Output 7 are
transmitted and received most significant bit (MSB) first via
the SPI bus. The outputs are provided with current limiting
and voltage sense functions for fault indication and
protection. The nominal load current for these outputs is
500mA, with current limiting set to a minimum of 1.05A. An
on chip clamp circuit capable of handling 500mA is
provided at each output for clamping inductive loads.
RESET - Active low reset input. When this input line is low,
the shift register and output latches are configured to turn
off all output drivers. A power on clear function may be
implemented by connecting this pin to VDD with an external
resistor, and to VSS with an external capacitor. In any case,
this pin must not be left floating.
CE - Active low chip enable. Data is transferred from the
shift register to the outputs on the rising edge of this signal.
The falling edge of CE loads the shift register with the
output voltage sense bits coming from the output stages.
The output driver for the MISO pin is enabled when this pin
is low. CE must be a logic low prior to the first serial clock
(SCK) and must remain low until after the last (eighth) serial
clock cycle. A low level on CE also activates an internal
disable circuit used for unlatching output states that are in a
fault mode as sensed by an out of saturation condition. A
high on CE forces MISO to a high impedance state. Also,
when CE is high, the octal driver ignores the SCK and MOSI
signals.
SCK, MISO, MOSI - See Serial Peripheral Interface (SPI)
section in this data sheet.
VDD and VSS - Positive and negative power supply lines.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) utilized by the
CDP68HC68P2 is a serial synchronous bus for control and
data transfers. The clock (SCK), which is generated by the
microcomputer, is active only during data transfers. In
systems using CDP68HC05 family microcomputers, the
inactive clock polarity is determined by the CPOL bit in the
microcomputer's control register. The CPOL bit is used in
conjunction with the clock phase bit, CPHA to produce the
desired clock data relationship between the microcomputer
and octal driver. The CPHA bit in general selects the clock
edge which captures data and allows it to change states.
For the CDP68HC68P2, the CPOL bit must be set to a logic
zero and the CPHA bit to a logic one. Configured in this
manner, MISO (output) data will appear with every rising
edge of SCK, and MOSI (input) data will be latched into the
shift register with every falling edge of SCK. Also, the steady
state value of the inactive serial clock, SCK, will be at a low
level. Timing diagrams for the serial peripheral interface are
shown in Figure 2.
SPI Signal Descriptions
MOSI (Master Out/Slave In) - Serial data input. Data bytes
are shifted in at this pin, most significant bit (MSB) first. The
data is passed directly to the shift register which in turn

controls the latches and output drivers. A logic "0" on this
pin will program the corresponding output to be ON, and a
logic "1" will turn it OFF.
MISO (Master In/ Slave Out) - Serial data output. Data
bytes are shifted out at this pin, most signficant bit (MSB)
first. This pin is the serial output from the shift register and is
tri stated when CE is high. A high for a data bit on this pin indicates that the corresponding output is high. A low on this
pin for a data bit indicates that the output is low. Comparing
the serial output bits with the previous input bits, the
microcomputer Implements the diagnostic data supplied by
the CDP68HC68P2.
SCK - Serial clock input. This signal clocks the shift register. New MISO (output) data will appear on every rising
edge of SCK and new MOSI (input) data will be latched into
the shift register on every falling edge of SCK. The SCK
phase bit, CPHA, and polarity bit, CPOL, must be set to 1
and 0, respectively in the microcomputer's control register.

Functional Description
The CDP68HC68P2 is a low operating power, high voltage,
high current, octal, serial solenoid driver featuring eight
channels of open collector drivers. The drivers have low saturation voltage and output short circuit protection, suitable
for driving resistive or inductive loads such as lamps, relays
and solenoids. Data is transmitted to the device serially
using the Serial Peripheral Interface (SPI) protocol. Each
channel is independently controlled by an output latch and
a common RESET line that disables all eight outputs. Byte
timing with asynchronous reset is shown in Figure 3. The
circuit receives 8 bit serial data by means of the serial input
(MOSI), and stores this data in an internal register to control
the output drivers. The serial output (MISO) provides 8 bit
diagnostic data representing the voltage level at the driver
output. This allows the microcomputer to diagnose the condition at the output drivers. The device is selected when the
chip enable ICE) line is low. When CE is high, the device is
deselected and the serial output (MISO) is placed in a tri
state mode. The device shifts serial data on the rising edge
of the serial clock (SCK), and latches data on the falling
edge. On the rising edge of chip enable (CE), new input
data from the shift register is latched in the output drivers.
The falling edge of chip enable ICE) transfers the output
driver fault information back to the shift register. The output
drivers have low ON voltage at rated current, and are monitored by a comparator for an out of saturation condition, in
which case the output driver with the fault becomes
unlatched and diagnostic data is sent to the microcomputer
via the MISO line. A typical microcomputer interface circuit
is shown in Figure 4. This circuit is also cascadable with
another octal driver.
Shift Register
The shift register has both serial and parallel inputs and
outputs. Serial output and input data are simultaneously
transferred to and from the SPI bus. The parallel outputs
are latched Into the output latch in the CDP68HC68P2
at the end of a data transfer. The parallel inputs jam diagnostic data into the shift register at the beginning of a data
transfer cycle.

6-30

CDP68HC68P2
RESET

CE

SCK

MOSI

0

MISO

OUTPUTS

OLD
_____________________
--'X NEW

¥7

RESET

FAULTS

FIGURE 3. BYTE TIMING WITH ASYNCHRONOUS RESET

output is high, a logiC one will be loaded into that bit in the
shift register. If the output is low, a logic zero will be loaded.
During the time that CE is low, data bytes controlling the
output drivers are shifted in at the MOSI pin most significant
bit (MSB) first. A logic zero on this pin will program the corresponding output to be ON, and a logiC one will turn it OFF.

CDP68HC68P2

CDP68HC05C4
MICROCOMPUTER

PORT

CE

MOSI

MOSI

MISO

MISO

SCK

CE Low to High Transition

SCK

--

--

RESET

RESET

FIGURE 4. TYPICAL MICROCOMPUTER INTERFACE WITH
THE CDP68HC68P2

Output Latch
The output latch holds input data from the shift register
which is used to activate the outputs. The latch circuit may
be cleared by a fault condition (to protect the overloaded
outputs), or by the RESET signal.
Output Drivers
The output drivers provide an active low output of 500mA
nominal with current limiting set to 1.0SA to allow for high
inrush currents. In addition, each output is provided with a
voltage clamp circuit to limit inductive transients. Each output driver is also monitored by a comparator for an out of
saturation condition. If the output voltage of an ON output
pin exceeds the saturation voltage limit, a fault condition is
assumed and the latch driving this output is reset, turning
the output off. The output comparators, which also provide
diagnostic feedback data to the shift register, contain an
internal pulldown current which will cause the cell to
indicate a low output voltage if the output is programmed
OFF and the output pin is open circuited.
CE High to Low Transition
When CE is low, the tri-state MISO pin is enabled. On the
falling edge of CE, diagnostic data from the output voltage
comparators will be latched into the shift register. If an

When the last data bit has been shifted into the
CDP68HC68P2, the CE pin should be pulled high. At the
rising edge of CE, shift register data is latched into the output latch and the outputs are activated with the new data. An
internal 1S0llsec delay timer will start at this rising edge to
compensate for high inrush currents in lamps and inductive
loads. During this period, the outputs will be protected only
by the analog current limiting circuits since resetting of the
output latches by fault conditions will be inhibited during
this time. This allows the device to handle inrush currents
immediately after turn on. When the 1S0llsec delay has
elapsed, the output voltages are sensed by the comparators
and any out of saturation outputs are latched off. The serial
clock input pin (SCK) should be low during CE transitions to
avoid false clocking of the shift register. The SCK input is
gated by CE so that the SCK input is ignored when CE is
high.
Detecting Fault Conditions
Fault conditions may be checked as follows. Clock in a new
control byte and wait approximately 1S0llsec to allow the
outputs to settle. Clock in the same control byte and note
the diagnostic data output at the MISO pin. The diagnostic
bits should be identical to the data clocked in. Any differences will indicate a fault at the corresponding outputs. For
example, if an output was programmed ON by clocking in a
zero, and the corresponding diagnostic bit for that output is
a one, indicating the driver output is still high, then a short
circuit or overload condition may have caused the output to
unlatch. Alternatively, if the output was programmed OFF by
clocking in one, and the diagnostic bit for that output shows
a zero, then the probable cause is an open circuit resulting
in a floating output.

6-31

....en
::i2
"'7'7"'7"'7"7'7'7"7'7'7'71:~
E
ByT----r.

MISO _ _ _ _ _ _ _ _-{~------,.

wiii

ADDRESS {

ADDRESS
ADDRESS
ADDRESS BYTE

r-----__,.

:~ DATA BYTE

))-_ __

{1~

+ (n-1I-------

Fig. 5 - Multiple-byte transfers.

92CM- 37718

DYNAMIC ELECTRICAL CHARACTERISTICS - BUS TIMING VOO ±10%,
VSS = 0 V dc, T A = -40 0 to +85 0 C, CL = 200 pF. See Figs. 6, 7 and 8.
10ENT.
NUMBER

LIMITS (ALL TYPES)
1"00=3.3 V VOO-5 V UNITS
Min. Max. Min. Max.

CHARACTERISTIC

(!)

Chip Enable Set-Up Time

tEvev

200

-

100

-

®

Chip Enable after Clock Hold Time

tevEx

250

-

125

-

@

Clock Width High

tWH

400

-

200

-

~

Clock Width Low

tWL

400

-

200

-

®
®
CD

Data In to Clock Set-Up Time

tovev

200

-

100

-

Data In after Clock Hold Time

tevox

200

-

100

-

Clock to Data Propagation Delay

tcvov

-

200

-

100

tEXQZ

-

200

-

100

(!)

Chip Disable to Output High Z

®

Output Rise Time

t,

-

200

-

100

@

Output Fall Time

t.

-

200

-

100

®
®

Clock to Data Out Active

tCVQX

-

200

-

100

Clock Recovery Time

tREC

200

-

200

-

6-36

ns

CDP68HC68R1,CDP68HC68R2

92CS-37714

Fig. 6 - Page/Device byte timing waveforms.

MOSI

~0~

~

W/R

~t-,,--+--£t-'-'-I....J...I....J....J...L...J...I

)))))) )})

1'-1_ _ _.1

CE·SS

SCK

Fig. 7 - WRITE cycle timing waveforms.

MOSI

""0

=» ...

:il!
ce ....
=:
a..
~ii:
- ....

MISO

~a..

CE·SS

SCK

Fig. 8 - READ cycle timing waveforms.

DATA RETENTION CHARACTERISTICS at TA = -40· to +8S·C
TEST
CONDITIONS

CHARACTERISTIC
Minimum Data Retention Voltage
Data Retention Quiescent Current

VOR
looDR

6-37

CS;:O:Voo -0.2 V
Voo = 2 V,
CE = Vss

LIMITS
ALL TYPES
MIN.
MAX.
2

-

UNITS

-

V

1

pA

mHARRIS

CDP68HC68S1
Serial Bus Interface

January 1991

Features

Pinouts

• Differential Bus for Minimal EMI
• High Common Mode Noise Rejection

PACKAGE TYPE E
TOP VIEW

PACKAGE TYPE M
TOP VIEW

• Ideal for Twisted Pair Wiring

Vnn

• Data Collision Detection

CONTROL

• Bus Arbitration
• Idle Detection
• Programmable Clock Divider
• Power-On Reset

Description
The CDP68HC68S1 Serial Bus Interface Chip (SBIC)
provides a means of interfacing in a Small Area Network
configuration, various microcomputers (MCUs) containing
serial ports. Such MCUs include the family of 68HC05
microcontrollers. The SBIC provides a connection from an
MCU's Serial Communication Interface (asynchronous
UART type interface) or Serial Peripheral Interface (synchronous) to a medium speed asynchronous two wire differential signal bus designed to minimize electromagnetic
interference. This two wire bus forms the network bus to
which ail MCUs are connected (through SBI chips). See
Figure 2. Each MCU operates independently and may be
added or deleted from the bus with little or no impact on bus
operation. Such a bus is ideal for inter-microcomputer communication in hazardous electrical environments such as
automobiles, aircraft or industrial control systems.
In addition to acting as bus arbitor and interface for
micrcomputer SCI port to differential bus communication,

the CDP68HC68S1 contains all the circuitry required to
convert and synchronize Non-Return-to-Zero (NRZ) 8-bit
data received on the differential bus and clock the data into
a microcomputer's SPI port. Likewise, data to be sent by a
microcomputer's SPI port is converted to asynchronous
format by appending start an stop bits before transmitting to
other microcomputers.
Refer to the data sheet for the CD P68HC05C4 for additional information regarding CDP68HC05 microcomputers and
their Serial Communications and Serial Peripheral
Interfaces.
The CDP68HC68S1 is supplied in a 14 lead dual-in-Iine
plastic package (E suffix), and in a 20 lead small outline
plastic package (M suffix).
Operating voltage ranges from 4V to 7V and operating
temperature ranges from -400 C to +105 0 C.

Block Diagram
SCK

i~OM

(

"MIT

MCU

BUS-

REC

cs

TO OTHER
SSX CHIPS

CLK

92CM-41214RI

Copyright @ Harris Corporation 1991

File Number
6-38

1918.1

CDP68HC68S1
MAXIMUM RATINGS, Absolute Maximum Values: (Voltages referenced to Vss)
SUPPLY VOLTAGE (VDD) ••••••..•.•.••••••••••••••...•.•.•.•••.•••••.•.••••••.••.•••.•••••.••..•..••.••.•••••••.•••• -0.3 to +7.0 V
INPUT VOLTAGE AT ANY PIN (V'N) .•••••...•••..••.•.•..•.••••.•..•.••......••.•....•.••.••..••.••.••.••.... Vss -0.3 to VDD +0.3 VDC
DC INPUT CURRENT PER PIN (I'N) ••..•••.•.••..•.••.•.••.•.••••.••.•.•.••••••.••••••••.•••..••••••••..•.••.•••.•.•.•.•••• ±10 mA
PACKAGE DISSIPATION (PD) •.•..•••.••••...•.••••••...••.•..•.•.••.•.•••.•••••••••••••••••••.••.••..•••..•••••.••••••••. 500 mW
STORAGE TEMPERATURE (T... ) .•.••••..•.•.••••••••••.•••••••.•••.••...•.•••.••.•.•••.•••••••.•.•.•.•••••.••..•• -55°C to +125° C
OPERATING TEMPERATURE (TA) •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• -40°C to +105°C
DC OPERATING VOLTAGE RANGE (VDD) •.•.••••••••••..••••••••••..••••••••.••••.••••...•.•••••.•••••.•.••.•••.•..•••• +4 to +7 V

MCU

MCU

MCU

92CS-42273

Fig. 2 - Possible network configuration - various microcomputers
using SBI chips to communicate along differential bus.

The Serial Bus IC offers the user three possible modes of
operation as defined by Table 1 - SCI t , SPI, and Buffered SPI.
Also included is a "tri-state mode" entered by pulling the CS
pin high while in the Buffered SPI mode. As the name implies,
the SCI mode is used when communicating through the
microcomputer's SCI port. In this mode, asynchronous NRZ
data format (1 start bit, 8 data bits 'least significant bit firsf, and
1 stop bit) and baud rate remain the same on each "side" of the
SBIC, i.e. to and from the micro and to and from the differential
network bus.
TABLE I - MODE AND CHIP SELECT DEFINITION
SBI CHIP MODE

MODE PIN

SCI

1

1

SPI

1

0

Buffered SPI

0

0

Tri-State'

0

1

CSPIN

• The tri-state mode Is only entered when using the Buffered
SPI mode. In the trl-state mode. only the XMIT, REC, and
SCK pins aretri-stated. The CONTROL and IDLE pins are
always active.
During data transmission, while a byte is being transmitted
from the MCU through the SBI chip onto the differential
bus, it is also reflected and simultaneously received back at
the micro, (this is required for bus arbitration as described
later).
In addition to performing a framing error check in the SCI
mode, other advantages gained by using the SBIC (in any
mode) include greater system EMI tolerance and automatic
bus "monitoring". The Serial BUS Interface chip handles bus
arbitration, data collision detection, and provides short. circuit
protection.

A 68HC05 MCU's SPI port may instead be used for bus
communication. Two modes of SPI operation are available
with the SBIC - one essentially places the 68HC05
microcomputer in the slave mode and the other allows the
MCU to remain a master. In the normal SPI mode the SBIC
acts as a master and supplies a data-synchronizing serial
clock signal to the micro (which operates in the slave mode)
for shifting data in or out of the micro's 8-bit SPI data
register. Again, baud rates are the same on each side of the
SBIC, however, the user must reverse the bit order of a byte
transmitted or received via the SPI port due to the SPl's
most significant bit first serial data nature. In addition, since
the user microcomputer is operating in the slave mode it
must signal the SBI chip (by pulling the CONTROL line low)
to initiate a transmission. As in the SCI mode, during a
transmission, the byte originally in the SPI data register is
replaced by the byte reflected from the bus.
Transmission and reception of data in the Buffered SPI
mode allows the user to free the micro's SPI port by
allowing fast data communication (1M bits/sec) between
the SPI port and SBIC. For instance, if the MCU is
transmitting, the SBIC converts the data stream from the
MCU's SPI port to a slower speed for transmission along the
differential bus when the bus becomes idle. Data speed
conversion is accomplished via a two-byte (16-bit) data
buffer register residing in the serial bus Chip. In this mode
the MCU operates as a master and provides the serial clock
signal to the slave SBIC peripheral. After fast data has been
sent to or received from the SBIC, the micro can pull the
SBIC's CS pin high (placing the SBIC chip in the tri-state
mode) and then use the SPI port to access other SPI
peri pherals.
All transfers between the user MCU and the SBIC in the
Buffered SPI mode consist of two bytes, I.e. a message
consists an even number of 8-bitlransfers. A microcomputer
wishing to transmit loads two-bytes into the serial bus IC
data register and then pulls the control pin low to initiate
transmission. During transmission the two bytes placed
t Note: SCI is the UART Interface of a 66HC05 MCU. The CDP66HC66S1 is
compatible with most UART interfaces.

6-39

•

CDP68HC68S1
DC ELECTRICAL CHARACTERISTICS AT TA = -40·C to +1OS·C UNLESS OTHERWISE NOTED
External bl81 (Yo) shall be 1.8 to 3.13 volll unless otherwise noted
LIMITS
CHARACTERISTIC

TEST CONDITIONS

UNITS
MIN.

MAX.

Signal 1/0 Section
Output Voltage

Input Voltage

High Level

VOL

Open Circuit

-

0.05

Vdc

Low Level

VOH

Open Circuit

VOD"'0.05

-

Vdc

Low

V'L

-

0.3 Voo

Vdc

V'H

0.7 Voo

-

Vdc

High

Output High Drive (Source) Current
(REC pin)
10H

vOH = 4.6V, voo = 5V

-0.12

-

mA

Output High Drive (Source) Current
(IDLE, Control pins)

vOH = 4.6V, Voo = 5V

-0.04

-

mA

10L

VOH = 0.4V, VOO = 5V

0.36

-

mA

DIFFERENTIAL TRANSCEIVER (See Fig. 4)
TransmlHer
BUS+
l"oL

Vo = Vool2, RL = 120n

2.75

-

mA

IAOH

Vo = Vool2, RL = 120n

-1.0

1.0

pA
mA

ou~ut Low Drive (Sink) Current
{ID E. Control, RECl

BUS-

IAOL - laoL Match

10H

laoL

Vo = Vool2, RL = 120n

-

-2.75

IBOH

Vo = Vool2, RL = 120n

-1.0

1.0

pA

1M

Vo = Voo/2, RL = 120n

-

5

%

Voo = 5 V ± 0.5 V
t,

Voo = 5V, CL = 25pF

-

1.5

ps

Output Fall Time (BUS-)

t,

voo = 5V, CL = 25pF

-

1.5

ps

Transition Match (50% point)

tm

VOO = 5V, CL = 25pF

-50

50

ns

-

120

mV

20

-

mV

20

-

mV

Output Rise Time (BUS+)

Receiver
Differential Sensitivity

V'OH

Vo = 2.5V, RL = 1200
VDO = 5V

V'OL

Vo = 2.5V, RL = 1200
VOO = 5V

Hysteresis

VH

(Within V'OH, VIDL Limits)
Propagation Delay
Out of Range

Vo = 2.5V, RL = 1200
Voo = 5V
VIOH = 120mV, Voo = 5V

-

700

ns

Vma•

Voo = 5V

3.8

-

V

Vm'n

Voo = 5V

-

1.2

V

tp

Quiescent Device Current

100

Voo = OV, Vo = 2.5V

-10

10

pA

Clock Speed

f. p

Voo=5, RL=120, CL=25.pF

-

TBD'

MHz

• Although 1 MHz is generally used as an example throughout this data sheet, the maximum speed limit may be higher
and depends upon user's noise tolerance requirements.

6-40

CDP68HC68S1
into the buffer are replaced by the two reflected bytes
received from the bus. After every two-byte transmission
the user micro should transfer the two reflected bytes out of
the buffer and the next two bytes to be transmitted into the
buffer.

8.

In the SCI mode this data input shall come from the
microcomputer standard NRZ asynchronous
communications output port (68HCOS SCI port pin
TxD). In the SPI modes, it shall come from the
microcomputer's synchronous output port (68HCOS
SPI port pin MOSI or MISO).

TABLE II - CLOCK PROGRAMMING
9.
CLOCK INPUT
DIVIDE FACTOR

APIN

BPIN
0

+1

0

+2

0

1

+4

1

0

+10

1

1

10.

ClK Input
This is the clock input that shall be divided by the
SBIC (as described in Table II) and used as an
internal synchronizing clock. The internal clock is
then further divided by 128 to determine baud rate,
Le. 128 internal clock periods constitute one bit
length.

4.

BUS+ and BUS- Input/Output
This is the two wire differential bus I/O used to
transmit and receive data to and from the differential
bus. BUS+ is both responsive to, or driven positive
by sourcing current from an externally established
bias point. Thissourcing current matches the BUSI/O's sinking current. BUS- is both responsive to, or
driven negative by sinking current from a externally
established bias point. This sinking current matches
the BUS+ I/O's sourcing current.

14,7.

Voo and Vss
Power and ground reference are supplied to the
device via these pins. Voo is power and Vss is
ground.

6-41

CS Input
This input shall be used in conjunction with the
mode input and shall be used as a chip select (see
Table I).lt may be permanently wired to +Voo orVss
or driven high or low by MCU I/O lines.

12.

iDLE Input/Output
The microcomputer shall monitor this signal to
determine the bus condition and also pull this line
low to generate a break. The IDLE signal goes low
when the bus is idle (after sensing an End of
Message condition) and high when the bus is active.
On reset, this pin is set to a logic zero.

Mode Input
This input shall be used in conjunction with CS
input to define the mode of operation (see Table I).
It may be permanently wi red to +Voo or Vss or driven
high or low by MCU I/O lines.

S, 6.

11.

Inputs A and B
Programing inputs of the. clock divider. These
inputs are tied to +Voo or Vss depending upon speed
of external clock source. (See Table II)

SCK Input/Output
In the SCI mode, this I/O is not required. In both SPI
modes this pin is connected to the 68HCOS's SPI
port SCK pin. In the normal SPI mode, the SBIC
shall produce shift clock pulses via this pin for
synchronously shifting data into and out of the
microcomputer. In the Buffered SPI mode this pin is
an input and the microcomputer shall generate the
shift clock pulses. Figure 3 shows the relationship
between the serial clock signal and other SBIC
signals in the SPI mode.

Pin #

2, 3.

REC Output
In the SCI mode this data output shall be fed into the
microcomputer asynchronous communications
input port (68HCOS SCI port pin RxD). In the SPI
modes it shall be fed into the microcomputer's
synchronous input port (680S SPI port pin MOSI or
MISO).

FUNCTIONAL PIN DESCRIPTION·
1.

XMIT Input

13.

Control Input/Output
The microcomputer shall monitor this I/O pin in the
SPI mode to handle transmission and reception of
data. In the SCI and SPI modes, as an output, this
pin will go low to indicate that a data byte is
currently active on the bus. In the Buffered SPI
mode the control pin indicates whether the user
microcomputer has current access to the SBI chip's
internal two-byte buffer (signified by a logic high on
the control pin).ln both SPI modes the control pin is
also effective as an.input. I n these modes the control
pin is pulled low by the user microcomputer to
initiate a transmit operation by the SBIC.
The control pin is normally high when the bus is
inactive. On reset, this pin is set to a logic high.

CDP68HC68S1
IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE
STOP BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT

9.,.....;'.;;.O,-'_'_
lS~TA~R~T.L-~....L....2.....J...."":--L~....J.~~""'::'-.L-~....L...!.-rB.:..:IT-r....;1~.....:::2-r....;3:""'r-'4-._5:.....,.:6~....;..7-r-8:"",r
0
3
4
5
6
7 I

DIFFERENTIAL
BUS - , BIT

SCK
XMIT
REC

c=x:::x:::x::x:
c=x:::x:::x::x:
MSB

6

5

4

3

2

1

LSB:~------------------------------------~--

MSB

6

5

4

3

2

1

L~B ~------------------------------------~--

r:-:--------------------------------;--

CONTROL(I)(3)--,t...:.__--.:______________________________

(4)

CONTROL(2)

~l___________________________J-----------------------------~-

IDLE~r----------------------------------------------------------,L___

NOTES: 1 - THE CONTROL SIGNAL AT THE TRANSMITTING NODE.
2 - THE CONTROL SIGNAL AT THE RECEIVING NODE.
3 - THERE IS A DELAY BETWEEN THE CONTROL PIN BEING
PULLED LOW AND THE ACTUAL BEGINNING OF THE START BIT.
4 - IF THE CONTROL PIN IS AGAIN PULLED LOW BEFORE THE
END OF THE STOP BIT, THEN THE NEXT START BIT WILL
BEGIN AT THE END OF THE PREVIOUS STOP BIT.

92CM·42519

Fig. 3 - SCK, CONTROL and IDLE Signals during the SPI mode of
operation.

Differential Transceiver Cell
The differential transceiver is a serial interface device which
accepts digital signals and translates this information for
transmitting on the two wire differential bus.

In addition to the transmission of data, the differential data
transceiver accepts at its bus "+" and bus "-" I/O's, serial
differential data which is translated into the standard digital
logic levels. This reception of data also occurs while
transmitting, thus reflecting the data seen on the bus back
into the SBIC data register.

The transmitter section (shown in figure 4), when
transmitting, provides matched constant current sources to
the bus "+" and bus "-" inputs/outputs sourcing and sinking
respectively. When transmitting, a logic zero at the "transmit
data" input causes the bus "+" I/O to provide source current
and the bus "-" I/O to provide a matched sink current. A
logic one at the "transmit data" input causes the bus "+" and
bus "-" liD's to simultaneously provide a high impedance
state. The bus depends on external resistor components for
bias and termination. Recommended resistor sizes are
shown in figure 4.

The differential transceiver cell allows bus activity by other
devices on the bus "+" and bus "-" I/O's when power to the
cell is shut off. Therefore, this powered off condition places
the transceiver outputs, bus "+" and bus "-", in a high
impedance state. When the cell is either being powered up
or down, with or without bus activity, SCR latch-up
protection is provided such that this activity is not affected.

A zero transmitted on the bus will appear as a large voltage
drop across the Bus+ and Bus- pins, i.e. Bus+ might
typically sit at +2.8 volts and Bus- at +2.2V for a logic zero.
For a logic level one, the SBIC actually tri-states the Bus+
and Bus- pins and relies on external resistors to bias the bus
lines. The lines are both biased to sit at approximately 2.5
volts with a small (perhaps 20 mV) voltage drop across the
two lines. In this condition the Bus- line actually sits at a
slightly higher potential than the Bus+ line. See figure 5.
Thus, the bus actually "floats" to a logic level one, but must
be driven to a logic level zero. Logic zero bits always
dominate over logic one bits on the bus. If two MCU's
simultaneously transmit a zero and a one on the bus, the
zero will override the one and the bus will merely appear to
be transmitting a zero. The "marking" or idle signal on the
bus is a logic one. If the bus is idle or if a micro is sending a
logic one, then a one will appear on the bus.

Twisted wire pair (or adjacent PC board traces) Is
recommended for the two differential bus lines.

Receive data is an output from the differential transceiver
cell. It is the output of a differential amplifier which decodes
the bus "+" and "-" I/O. When the bus "+" and "-" has been
driven positive and negative respectively to a differential
voltage value greater than VIDH, the output of the differential
amplifier is a logic one, which is inverted and considered a
zero bit from the bus. Otherwise, for level below VIDL the
differential amplifier output is a logic zero, which, in turn, is
inverted and considered a one bit from the bus.

The BREAK input, when held at a logic zero, (low) causes
the differential transmitter driver to generate a continous
logic level zero on the differential bus. This action can
generate a data collision which can be either used as a
break or a request for arbitration by the system. When held
at logic one, (high) this input has no effect on the operation
of the cell.

6-42

CDP68HC68S1
Differential Transceiver Cell (Continued)
The out of range output is normally a logic zero but goes to a
logic one when the common mode voltage on both differential
bus inputs exceeds a voltage value greater than V max or less
than V min (see device specifications). This output is used by a
latch to hold the received data at the logic level it was before
the over range signal occurred.

Provided on chip is a power-on reset function. The transceiver
cell's reset output is held to a logic zero on power up and
switches to a logic one at or before VDD rises to 4.0 volts. This
output is used to ensure that other on-board logic has been
properly initiated. During this reset time, the bus "+" and the
bus "-" I/Os provide a high impedance state to the bus.

I/O SECTION IN S81 CHIP AS WELL AS
REQUIRED EXTERNAL RESISTORS.

r-- -- I

---------1
SBI CHIP

Voo

I

LOADING ON THE BUS.

:

voo

I

I
I

I
I

I

I
I
I

I

I

I RECEIVE

I

eL MERELY REPRESENTS CAPACITIVE

OATA

13K~

BUS+

120n

}

I-+---..-H:) BUS-

DIFFERENTIAL
BUS

'--+--+-+.-t-.-..--{)

I
I
I

13 Kn.

I

I

iL ____________= ---1I

eaCS·42524

Fig. 4 - Differential Driver/Receiver.

LOGIC 1

LOGIC 0

LOGIC 1
92CS-424528

Fig. 5 - Typical voltage levels seen on BUS+ and BUS-I/O pins for
logic ZERO and logic ONE bits. Notice that the BUS- pin is
biased to actually sit at a higher voltage potential than the
BUS+ pin for a logic ONE. Values shown are for Voo =5 V.

6-43

CDP68HC68S1
Bus Speed

Reflected Data

SBIC systems typically use a bus speed of 7812.5
bits/sec which is accomplished by using a 1 MHz internal
clock. However, no restriction on any other baud rate is
designed into the chip, except its upper speed limit (see
device specifications).

Whenever a microcomputer sends data through the SBIC
and onto the differential bus, it will always receive reflected
data back. The reflected data is the data that was actually
seen on the bus. Keep in mind that during data collisions
between simultaneously transmitting micros, zeroes
override ones. In addition, any noise that may have been
induced on the bus may alter the resultant reflected byte.

Bus Byte Format

All bytes transmitted on the bus follow the standard UART
style asynchronous non-retu rn-to zero data format
consisting of 1 start bit (logical zero) followed by 8 data bits
(LSB first), and 1 stop bit (logical one).
Bus Message Format

All messages transmitted on the bus consist of a number of
bytes, from 1 to N, with no restriction on length. The user
must be aware, however, that the longer the message
length, the greater the probability of collision with messages
being transmitted at random from other masters on the bus.
Typical message lengths of systems now in use range from
1 to 4 bytes.
The actual definition of each byte sent is left for the user to
determine, I.e. the user must define the system protocol. For
instance, a typical (and recommended) protocol might
dictate that the first byte of each message sent be a unique
address/identification byte. The first byte sent by a node
(an MCU coupled with an SBI chip) might contain address
information telling where (to which node[s]) the message is
targeted for or where the message came from.
Other possibilities would be to identify the type of message
sent (e.g. an instruction or just information) orthe length of
the message. The remaining bytes in each message can b'e
merely data bytes that comprise the actual messsage. The
user can even use the last byte as a checksum so that all
receiving nodes can check for errors in transmission.
Messages are normally received by all nodes on the bus and
may be processed by one or more micros, I.e., each MCU
may decide, after receiving the first byte (address/ID byte)
that this particular message is not needed for its operation.
The MCU can then ignore the remainder of the message.

BUS ARBITRATION

Bus arbitration is the attempted transmission onto the
differential bus of an initial byte (preferably an address/ID
byte) by one or more user microcomputers. The purpose of
bus arbitration is to enable a single microcomputer to
obtain sole usage ofthe bus forthe purpose oftransmitting
a message.
Bus arbitration is accomplished via a combination of
methods which include an MCU software comparison of
transmitted bytes to reflected bytes, the SBIC's collision
detection circuit, and its start bit arbitration detector circuits.
Collision Detection

The SBIC's collision detector circuit compares the bits
being sent from a user microcomputer to the reflected byte
simultaneously received back from the differential bus. If
the collision detector detects a difference in the data, it
immediately blocks the user microcomputer's transmitted
data from further reaching the bus. This will happen, as
stated in the "Prioritization" section, when a micro with a
higher priority address/ID byte attempts "simultaneous"
transmission (actually, I.e. within a time window of 1/4 bit
time). That micro, with a higher priority I D byte, is obviously
sending a zero bit and its reflected byte matches the byte it
is sending. Not detecting a collision, it continues to transmit
its message, while the lower priority MCU Is cut off from
transmitting on the bus. The lower priority micro will be
inhibited from transmitting on the bus until the mess.age
presently on the bus has ended (EOM = "End of Message"
condition).
End of Message Condition

Prioritization

Since simultaneous transmission of address/ID bytes from.
several microcomputers is a possibility, a system of
prioritization should be determined for bus arbitration. Due
to the electrical characteristics of the differential data bus,
each unique address/ID byte can automatically contain
priority information used for bus arbitration. Merely use
"Iower"value ID bytes for higher priority messages. "Lower"
value, in the SBIC case, means an ID byte with more zero's
in its least significant locations. To further explain, since the
differential bus transmits data least Significant bitfirst and a
zero overrides a one bit simultaneously transmitted by
different nodes, an ID byte with least significant bit equal to
zero will override an ID byte from a micro whose least
significant bit is a one. If this does occur on-chip bus
arbitration will automatically allow only one SBIC chip
(with the highest priority address/ID byte) to continue
transmitting. In this case it is the micro who transmitted the
zero bit. Assuming both ID bytes contain identical LSB's
(bit 0) then arbitration is carried on to the next bit (bit 1), and
so on.

Aftertransmitting the last byte of a message, thetransmitting
MCU must generate an End of Message (EOM) condition.
An EOM condition is defined as a 10 bit-length idle
condition,i.e., the bus must remain idle (logic 1) for a period
of 10 bit times (1280 internal clock periods). This can be
done by merely creating a 10-bit delay in MCU software.
Start Bit Arbitration Detection

Arbitration, as discussed above, is only necessary when two
or more micros attempt to transmit within 1/4 bit time (32
internal clock periods) of each other. Otherwise, once a
micro begins a transmission on the differential data bus, all
other SBI chips sense the start bit and inhibit their
microcomputers from transmitting (again, after a 32 clock
period arbitration window delay). Once the arbitration
detector circuit has blocked an MCU's transmission, access
to the bus will be blocked until an End of Message
condition.

6-44

CDP68HC68S1
receiving a start bit. During the 10 bit-time delay, if a nonidle condition such as noise is detected on the bus, the
delay period counter will be restarted.

Start of Message Delay
In order to properly synchronize various MCU's (which may
be using different modes of operation) for impartial
arbitration, each node must delay 2 bit-times (256 internal
clock periods) after detecting the IDLE signal drop low
before transmitting, i.e., before the start bit of the next
message reaches the bus. When using the SPI or Suffered
SPI modes, this delay is automatically designed into the SSI
chip. However, when using the SCI mode, the MCU must
support this required delay. Fortunately, 68HC05
microcomputers using the SCI port will inherently
experience a delay between the time that the SCI data
register is loaded and the time that the start bit actually
appears on the SCI port transmit pin (TxD). Ata baud rate of
7812.5 bps this delay can be as long as 256 SSI chip internal
clock periods. If this is so, then the user MCU does not have
to worry about providing this delay.

Due to the 10 bit time idle delay period, once an MCU wins
bus arbitration, it should send the next data byte to be
transmitted within a period of 10 bit times (1280 internal
clock periods). Each subsequent data byte to be sent
should also not exceed the interbyte maximum of 10 bit
times. If this maximum is exceeded, all SSIC chips will have
detected the idle condition and now pull their idle lines low
and reset their bus arbitration and collision detection
circuits, thereby allowing other SBI chips with messages to
send to arbitrate for the bus. Figure 6 shows the detailed
operation of the serial bus interface chip during bus
arbitration. This example shows the arbitration of a single
byte (e.g. the address/lD byte) from three different user
microcomputers. Two full arbitration cycles are shown.

Idle Detection

Break Generator

An idle detector circuit is used to detect when the differential
bus is in the idle condition, i.e., no user microcomputer has
control of the bus and the bus is sitting at a mark condition
(a logic one). The idle detector senses a received stop bit
and delays for a short idle period of 10 bit times, during
which the bus must remain idle. The idle output pin is then
set to a logic zero (true). It is later set to a logic one by

A request for arbitration can be generated by a node that
needs to interrupt transmission of a long data string. This
can be accomplished by forcing the SSIC's IDLE pin to a
logic zero; this forces a data collision (by sending zero bits)
after three data bytes have been transmitted, and the
transmitting MCU is required to detect this break condition
and stop transmitting. It is, however, allowed to re-arbitrate
for the bus and the interrupting mode may not generate a
second break condition if it loses arbitration.

,

10 BYTE FOR A MESSAGE
START
BIT
0

10 BYTE FOR A DIFFERENT MESSAGE
7

STOP
BIT

START
BIT 0

~

7

STOP
BIT

111'

XMIT#1
REC#1

~
XMIT#2
REC#2

~
XMIT#3

REC#3
THE
DIFFERENTIAL

BUS

0'

~~~SCONTROL ~L.'~'---'-"""'_'--'-""""_J....Icr;;;-r.... (7)
ALL iiiLE
PINS

~r---r--.-r-..,......-r--'--...---.-.--l'II 2~
10 IDlk BITS

NOTES: 1 234 5 -

10 IDLE BITS

USER #1 IS NOT TRANSMITTING = MARKING.
POINT AT WHLCH USER #2 LOSES BUS ARBITRATION.
POINT AT WHICH USER #3 LOSES BUS ARBITRATION.
POINT AT WHICH USER #3 LOSES BUS ARBITRATION.
THIS '1' BIT IS NOT OVERRIDDEN BY THE '0' BITS FROM USERS 2 & 3
BeCAUSE BOTH USERS2 & 3 HAVE PREVIDUSLYBEEN BLOCKED FROM
BUS ACCESS DUE TO DATA COLLISIONS.

8 - THE CONTROL PIN ON THE TRANSMITTING NODE GOES LOW EARLIER IN
BOTH SPI MODES (IT IS PULLED LOW BY MICRO).

7 - THE CONTROL PIN REMAINS LOW UNTIL THE END OFTHELAST DATA BIT OF
THE TWO-BYTE SET WHEN USING THE BUFFEREDSPI MODE, BUT GOES HIGH
ATTHE~OFTHELASTDATABIT

IN OTHER MODES.

Fig. 6 - Example of the S81 chip operating during bus arbitration.

6-45

CDP68HC68S1
USING THE CDP68HC68S1
Following are some hardware and software
recommendations for using RCA's CDP68HC68S1 Serial
Bus Interface Chip. Requirements may vary depending
upon the user's system configuration.
HARDWARE (GENERAL)
The differential bus lines (BUS+ and BUS-) must be
term i nated with external resistors as shown in fig u re 4. Th is
applies, however, only to one node (an MCu/SBIC pair)
along the bus. Since all SBI chips are wired in parallel
across the network bus, there is no need for additional 13K
bias resistors at each node. The 120 ohm termination
resistors should, however, be present at two nodes if the
network does indeed contain two or more nodes. The 120
ohm resistor provides the voltage drop across which the
SBI chip senses logic zero and logic one bits. If two nodes
each utilize 120 ohm termination resistors as shown in
figure 7a, the effective resistance across the BUS+ and
BUS- pins drops to 60 ohms total (due to the parallel wiring
method). Any less resistance would not provide an ample
voltage drop for the receiver cell op amp to sense. Following
these guidelines, typical systems might look like those
shown in figure 7. +VDD
(a)
13 KI1

BUS-

0

BUS-

MCU

0

III

III
II:

12011

SBIC

0

II:

120n

MCU

0

0:

0:

III

III

BUS+
13 KI1

92C&-42522

Hardware configuration for a network consisting of two
microcomputers. Notice that the pul/up resistor is connected
to the BUS- pin and the pul/down to BUS+.

(a)

(b)

120{1

13KD

'vvyo

.A

13,':.4
v~

+YDD
BUS- BUS+

(b)

auS+

The microcomputer must then confirm transmission by
reading the byte reflected back from the bus. If this byte
matches the byte transmitted then the MCU has gained
control of the bus and may continue to transmit the
remainder of the message (if any).
If the reflected byte does not match the 10 byte sentthen the
MCU has not gained control of the bus and may not
presently transmit. It should, however, check the reflected
10 byte to see if the incoming message (i.e. the message
from the arbitration-winning MCU) is of any interest. If so, it
should save the incoming message (the length of which
may be specified in the 10 byte) and then wait forthe IDLE
line to go high before re-attempting transmisssion (if still
desired). The flowchart in figure 8 reflects this procedure.
THE SCI MODE
HARDWARE
In the SCI mode, the TxD and RxD pins on the user
microcomputer must be connected to the XMIT and REC
pins on the SBIC chip, respectively, as shown in figure 9.
The MCU's SCI port should be configured for the same
baud rate and character format as that used by the bus
interface (i.e. 1 start bit, 8 data bits and 1 stop bit). The start
and stop bits are used to synch ronize the data a byte
transfers between the user microcomputer and the SBI
chip.
When using the SCI mode, the SBI chip should always be
properly mode and chip selected. This can be accomplished
by either a user microcomputer output signal or by
permanent wiring. This is required in order to always be
able to receive messages from other microcomputers on
the bus, which can happen at random. For the SCI mode,
the SBI chip's MODE pin must be set to 1 and the CS pin to
1.
SOFTWARE

120n

The procedure to follow for transmitting/receiving in the
SCI mode is basically identical to that stated in the "Using
the CDP68HC68S1-Software" section above, with the
following exception:

>'I/IIIr
BUS-

When a microcomputer is preparing to transmit a message
it should monitor the SBIC's IDLE pin and wait for it to go
low (logic zero) indicating the bus is idle. Then the MCU
attempts to transmitthe first byte (preferably an AddressilD
byte). If no other MCUs are transmitting at this time, or if
this MCU has the highest priority ID byte, the SBI chip's
collision detector circuit will permit transmission.

BUS- BUS+

SBle

SBle

SBle

[1

r n ...

BUS-

auS+

SBle

Start of Message Delay

f1

SPIORsel

SPIORSCI

Spt OR SCI

SPIORsel

MCU

MCU

MCU

MCU

Hardware configuration for a network consisting of 3 or more
MeU's. Notice that the bus utilizes no more than 1 set of 13K
bias resistors and no more than two 1200 termination resistors.

Fig. 7 - Hardware configuretlon for a network of microcomputers.

SOFTWARE (GENERAL)
Although each user's protocol may vary, the following
general procedure should be followed when using the SBI
chip in any mode:

Transmitting a byte via the 68HC05 SCI port basically
requires loading the byte into the MCU's SCI data register
(once the SCI port is initialized). However, after the SBIC's
IDLE pin drops low, the user may have to create a delay
before transmitting the FIRST byte of a message; this
necessary 2 bit-time (256 internal clock periods) delay is
called the Start of Message (SOM) delay. Fortunately, SCI
ports exhibit an inherent delay between the loading of the
transmit data buffer and the actual beginning of the start bit
appearing on the TXD pin. This delay, at 7812.5 Baud, can
be as long as 256 SBI chip internal clock periods and can be
used to synchronize SCI users with SPI and Buffered SPI
users to ensure impartial bus arbitration. The delay for a
particular microcomputer must be determined by the user.
If this inherent delay is less than 256 clock periods, then the
user must delay the loading of the first byte enough to
ensure that the total delay including the inherent delay of
the SCI port is 256 clock periods.

6-46

CDP68HC68S1

"TRANSMIl" AN END OF
MESSAGE CONDITION.

ABORT THIS MESSAGE
TRANSMISSION DUE TO A
COLLISION.

IZCIl-42U1

Fig. 8 - General message processing procedure.

MCU

SBIC
Tl Va
VI
(For Va Not Internally
Connected to VOO)
Power-On Reset (POR) Pulse Width

-

-

pA

0.4

-

0.1
±1
±10
0.08
0.1
0.5
0.6
0.84
0.7
1.2
1
0.024
0.02
0.12
0.1
0.24
0.2
0.4
0.5
25
20
200
250
300
360
600
500
10
la
10
la
25
15
30
20
0.08 0.15 0.1 0.18
0.15 0.25 0.18 0.3
0.3 0.4 0.36 0.5

V

pA

mA

pA

-

32kHz

-

10

12

pA

-

-

2

pF

2

JlS

0

10

12

-

0.7

-

100

75

-

VIN = O. TA = 25°C

-

4.4

1

-

UNITS
MAX.
10

32kHz
1 MHz
2MHz
4MHz
Ib

CIN
tr.tl
10)

3.7

TYP.-

-

mA

V

-

• Typical values are for TA = 25° C and nominal Vee.
# Clock Out (Pin 1) disabled. outputs open-circuited. No serial access cycles.

6-54

ns

CDP68HC68Tt

-- 0

$00

32

32 RAM LOCATIONS

31

$1F

32

$20
CLOCK/CALENDAR

r,w $20
r,w $21

SECONDS

33

MINUTES

34

HOURS

35

DAY OF WEEK

36

DATE

37

MONTH

r,w $24
r,w $25

36

YEARS

r,w $26

39

NOT USED

40

SEC ALARM

W

$28

41

MIN ALARM

W

$29

W

$2A

r,w $22
r,w $23

$27

50

$32

42

HRSALARM

51

$33

43

NOT USED

44

NOT USED

$2C

45

NOT USED

$20

46

NOT USED

$2E

47

NOT USED

48

STATUS REGISTER

$3F

49

CONTROL REGISTER

$55

50

13 BYTES UNUSED

63

-- -85

r = readable

TEST MODE
W

= writable

$2B

$2F

r

$30

r,w $31
INTERRUPT CONTROL REGISTER r,w $32
92CS~38051

Fig. 2 • Address map.

TABLE I - Clock/Calendar and Alarm Data Modes
BCD DATE e
EXAMPLE

ADDRESS
LOCATION (H)

FUNCTION

DECIMAL
RANGE

BCD DATA
RANGE

20

Seconds

0-59

00-59

18

21

Minutes

0-59

00-59

49

22

* Hours
12 Hour Mode

1-12

81-92 (AM)
A1-B2 (PM)

A3

Hours
24 Hour Mode

0-23

00-23

15

23

Day of the Week
(Sunday = 1)

1-7

01-07

03

24

Day of the Month
(Date)

1-31

01-31

29

25

Month
Jan= 1, Dec= 12

1-12

01-12

10

26

Years

0-99

00-99

85

28

Alarm Seconds

0-59

00-59

18

29

Alarm Minutes

0-59

00-59

49

2A

*. Alarm Hours
12 Hour Mode

1-12

01-12 (AM)
21-32 (PM)

23

Alarm Hours
24 Hour Mode

0-23

00-23

15

• Example: 3:49:18, Tuesday, Oct. 29,1985.
• Most significant Bit, 07, is "0" for 24 hours, and "1" for 12 hour mode.
Data Bit 05 is "1" for P.M. and "0" for A.M. in 12 hour mode.

6-55

•• Alarm hours, Data Bit 05 i:;."1"
"0" for A.M. in 12 hour mode .

fnr

P.M. and

Data Bits 07 and 06 are DON'T CARE.

CDP68HC68T1
PROGRAMMERS MODEL - CLOCK REGISTERS

I

HEX ADDRESS

I

NAME

WRITE/READ REGISTERS
DB7

DBO
SECONDS (00-59)---

20
TENS 0-5
21

22

23

DB7,1 = 12 HR, 0 = 24 HR
DB5 = 1 PM, 0 = AM
HOURS (01-12 OR 00-23)

12
PM/AM
HR. X TENS 0-2
24
X

X

X

X

SUNDAY = 1
DAY OF WK (01-07)---

X

01-28 )
(29
(DATE)
DAY OF MONTH
~~-

TENS 0-3
24

MONTH (01-12)- JAN = 1 _
DEC = 12

25

YEARS (00-99) - - - -

26
7

CONTROL-----

7

INTERRUPT-----

31

32

WRITE ONLY REGISTERS

28

TENS 0-5

UNITS 0-9

ALARM SECONDS'(00-59) -

29

TENS 0-5

UNITS 0-9,

ALARM MINUTES (00-59) -

X
2A

X

PM/AM
TENS 0-2

ALARM HOURS (01-12 or 00-23)
PLUS AM/PM IN12 HR. MODE
PM = 1, AM = 0

UNITS 0-9

READ ONLY REGISTER

o

30
NOTE:

X = DON'T CARE WRITES
X =0 WHEN READ

RAM DATA BYTE

STATUS

~71 :'1 :·j":'I:'I·: I·: 1·:1
HEX ADDRESS 00-lF
92CM-38059

6-56

CDP68HC68T1
FUNCTIONAL DESCRIPTION
The SPI real-time clock consists of a clock/calendar and a
32 x 8 RAM. Communications is established via the SPI
(Serial Peripheral Interface) bus. In addition to theclock/calendar data from seconds toyears, and system flexibility
provided by the 32-byte RAM, the clock features computer
handshaking with an interrupt output and a separate
squarewave clock output that can be one of 7 different
frequencies. An alarm circuit is available that compares the
alarm latches with the seconds, minutes and hours time
counters and activates the interrupt output when they are
equal. The clock is specifically designed to aid in powerdown/up applications and offers several pins to aid the
designer of battery back-up systems.
Mode Select
The voltage level that is present at the Vsys input pin at the
end of power-on-reset selects the device to be in the single
supply or battery back-up mode.
Single-Supply Mode-If VsyS is a logic high when poweron-reset is completed, CLK OUT, PSE and CPUR will be
enabled and the device will be completely operational.
CPUR will be placed low if the logic level at the VSy~oes
low. If the output signals CLK OUT, PSE and CPUR are
disabled due to a power-down instruction, VsyS brought to a
logic low and then to a logic high will re-enable these
outputs. An example of the single-supply mode is where
only one supply is available and Voo, VBATT and VSYS are tied
together to the supply.
Battery Back-up Mode-If VSYS is a logic low at the end of
power-on-reset, CLK OUT, PSE and CPUR will be
disabled (CLK OUT, PSE and CPOR low). This
condition will be held until VSYS rises to a threshold (about
0.7 volt) above VBATT. The outputs CLK OUT, PSE and CPUR
will then be enabled and the device will be operational. If
VsyS falls below a threshold above VBATT, the outputs CLK
OUT, PSE and CPUR will be disabled. An example of
battery back-up operation occurs if Vsys is tied to Voo and
Voo is not connected to a supply when a battery is
connected to the VBATT pin. (See Pin Functions VBATT for
Battery Back-up Operation)

seconds, minutes and hours registers. When their outputs
equal the values in the seconds, minutes and hours time
counters, an interrupt is generated. The interrupt output
will go low if the alarm bit in the Interrupt Control register is
set high. The alarm interrupt bit in the Status register is set
when the interrupt occurs! To preclude a false interrupt
when loading the time counters, the alarm interrupt bit
should be set low in the Interrupt Control register. This
procedure is not required when the alarm time is set.
WATCHDOG FUNCTION (See Fig. 6.)
When bit 7 in the Interrupt Control register is set high, the
Clock's CE (chip enable) pin must be toggled at a regular
interval without a serial data .transfer. If the CE is not
toggled, the clock will supply a CPU reset pulse and bit 6 in
the Status Register will be set. Typical service and reset
times are listed below.

Min. Max.
Service Time

-

10ms

Reset Time

20

40ms

XTAL

Min.

Max.

Min.

Max.

-

8.3ms

-

7.8ms

16.7

33.3ms

15.6 31.3m!

CLOCK OUT
The value in the 3 least significant bits of the Clock Control
register selects one of seven possible output frequencies.
(See Clock Control Register). This squarewave signal is
available at the CLK OUT pin. When Power-Down operation
is initiated, the output is set low.
CONTROL REGISTERS AND STATUS REGISTERS
The operation of the Real-Time Clock is~ontrolled by the
Clock Control and Interrupt Control registers. Both registers
are read-write legisters. Another register, the Status register,
is available to indicate the operating conditions. The Status
register is a read-only register.
POWER CONTROL

CLOCK/CALENDAR (See Figs. 1 and 2.)

Power control is composed of two operations, Power Sense
and Power Down/Up. Two pins are involved in power
sensing, the LINE input pin and the INT output pin. Two
additional pins are utilized during power-down/up operation. They are the PSE (Power Supply Enable) output pin
and VSYS input pin.

The clock/calendar portion of this device consists of a long
string of counters that is toggled by a 1-Hz input. The 1-Hz
input is generated by a prescaler driven by an on-board
oscillator that utilizes one of four possible external crystals
or that can be driven by an external clock source. The 1-Hz
trigger to the counters can also be supplied by a 50 or60-Hz
input source that is connected to the LINE input pin.

POWER SENSING (See Fig. 3.)

The time counters offer seconds, minutes and hours data in
12 or 24-hour format. An AM/PM indicator is available that
once set, toggles every 12 hours. The calendar counters
consist of day (day of week), date (day of month), month
and years information. Data in the counters is in BCD
format. The hours counter utilizes BCD for hour data plus
bits for 12/24 hour and AM/PM. The 7 time counters are
accessed serially at addresses 20H through 26H. (See Table
I).
RAM
The real-time clock also has a static 32 x 8 RAM that is
located at addresses 00-1 FH. Transmitting the address/control word with bit Slow selects RAM access. Bits 0 through 4
select the RAM location.

When Power Sensing is enabled (Bit 5 = 1 in Interrupt
Control Register), AC transitions are sensed at the LINE
input pin. Threshold detectors determine when transitions
cease. After a delay of 2.68 to 4.64 ms plus the external input
circuit RCtime constant, an interrupt is generated and a bit
is set in the status register. This bit can then be sampled to
see if system power has turned back on. See PIN
FUNCTIONS, LINE PIN. The power-sense circuitry operates
by sensing the level of the voltage presented at the line input
pin. This voltage is centered around Voo and as long as it is
either plus or minus a threshold (about 1 volt) from Voo a
power-sense failure will not be indicated. With an ac signal
present, remaining in this Voo window longer than a
minimum of 2.68 ms will activate the power-sense circuit.
The larger the amplitude of the ac signal, the less time it

ALARM
The alarm is set by accessing the three alarm latches and
loading the required data. The alarm latches consist of

60 Hz

50 Hz

'See PIN FUNCTIONS, INT PIN.

6-57

CDP68HC68T1

CPU
C DP6805 02

REAL-TIME CLOCK
VOO

CD~68HC68T1

I I I

I

I

J!

I

STATUS REGISTER
92CS-37941 Ifl

Fig. 3 - Powflr-sflnsing functional diagram.

spends In the Voo window and the less likely a power failure
will be detected. A 60-Hz. 10 V..P sinewave voltage Is an
applicable signal to present at the LINE input pin to set up
the power-sense function.
POWER DOWN (5•• Fig. 4.)
Power down is a processor-directed operation. A bit is set in
the Interrupt Control Register to initiate operation. 3 pins
are affected. The PSE (Power Supply Enable) output.
normally high. is placed low. The ClK OUT Is placed low.
The CPUR output. connected to the processors reset Input
Is also placed low. In addition. the Serial Interface is
disabled.
TO SYSTEM
POWER CONTROL

FROM SYSTEM
POWER

MOS:t
REAL-TIME CLOCK
CDP68HC68TI

L

v sys

92CS-37943RI

PSEll

IIIIII

I III
INTERRUPT
CONTROL
REGISTER

I
I

CLK
OUT
CPUR

t

SERIAL
~..k
INTERFACEJ"-I

REAL-TIME CLOCK
CDP68HC68T1

L
L

Fig. 5 - Powflr-up functional diagram (initiatfld by Interrupt Signal).
OSC

REsEi'
I
I

M:tSO
MOS:t

~--~

CPU
CDP680502

.--------,.I
I
I

I.-}--I --::...:. v svs

PSE

92C8- 37942

CPUR

Fig. 4 - Powflr-down functional diagram.
CLK
OUT

POWER UP (5•• Fig •• 5 and 8.)
Two conditions will terminate the Power-Down mode. The
first condition (See Fig. 5) requires an interrupt. The
interrupt can be generated by the alarm circuit. the
programmable periodic interrupt signal. or the powersense circuit.
The second condition that releases Power Down occurs
when the level on the Vava pin rises about 1 volt above the
level at the VIATT input. after previously falling to the level of
VBATT (See Fig.6) in the Battery Back-up Mode or Vsva falls
to logic low and returns high in the Single Supply Mode.

6-58

I

t---

i

--r
n

-'

r-

LJ

MXSO
SERI AL
INTERFACE

MOS!.

REAL-TIME CLOCK
CDP68HC68TI
92CS-37944RI

Fig. 6 - Powflr-up functional dlegram (/nitiatfld by a riSfl in voltagfl
on thfl "Vavs" pin).

CDP68HC68T1
PIN FUNCTIONS
ClK OUT-Clock output pin. One of 7 frequencies can be
selected (or this output can be set low) by the levels of the
three LSB's in the clock-control register. If a frequency is
selected, it will toggle with a SO% duty cycle except 2 Hz in
the SO-Hz timebase mode. (Ex. If 1 Hz is selected, the output
will be high for SOO ms and lowforthe same period.) During
power-down operation (bit 6 in Interrupt Control Register
set to "1"), the clock-output pin will be set low.
CPUR-CPU reset output pin. This pin functions as an
N-chan nel only, open-drai n output and req ui res an external
pull-up resistor.

setting bit 6 in the Clock Control Register. The second
function enables the line input to sense a power failure.
Threshold detectors operating above and below Voo sense
an ac voltage loss. Bit S must be set to "1" in the Interrupt
Control Register and crystal or external clock source
operation is required. Bit 6 in the Clock Control Register
must be low to select XTAL operation.

INT-Interrupt output pin. This output is driven from a
single NFET pull-down transistor and must be tied to an
external pull-up resistor. The output is activated to a low
level when:
1. Power-sense operation is selected (BS = 1 in Interrupt
Control Register) and a power failure occurs.
2. A previously set alarm time occurs. The alarm bit in the
status register and interrupt-out signal are delayed 30.S
IJS when 32-kHz operation is selected and 1S.31JS for
2-MHz and 7.61JS for4-MHz. (See important application
note.)
3. A previously selected periodic interrupt signal activates.

OSCillATOR CIRCUIT -The CDP68HC68T1 has an onboard 1S0K resistor that is switched in series with its
internal inverter when 32-kHz is selected via the clockcontrol register. Note: When first powered up the series
resistor is not part of the oscillator circuit. (The
CDP68HC68T1 sets up for a 4-MHz oscillator.)
r---::X=C
T A:-;L""
IN

22M

T1

XTAL 1----I",*"RJ'4
OUT

10 -40 pF

C2

The status register must be read to set the Interrupt output
high after the selected periodic interval occurs. This is also
true when conditions 1 and 2 activate the interrupt. If power
down had been previously selected, the interrupt will also
reset the power-down functions.

ALL FREQUENCYS
RECOMMENDED OSCILLATOR CIRCUIT:
Cl. C2 VALUES CRYSTAL DEPENDENT
OR USED FOR 32 KHz OPERATION ONLY.
100 K • 300 K RANGE AS SPECIFIED
BY CRYSTAL MANUFACTURER.
92CS-42272

SCK, MOSI, MISO-See Serial Peripheral Interface (SPI)
section in this data sheet.

Fig. 7 - Oscillator circuit.

CE-A positive chip-enable input. A low level at this input
holds the serial interface logic in a reset state. This pin is
also used for the watchdog function.
Vss- The

5 - 30 P F

~~~~~~~

negative power-supply pin that is connected to

ground.
PSE-Power-supply enable output pin. This pin is used to
control power to the system. The pin is set high when:
1. VSYS rises above the VBATT voltage after VSYS was placed
low by a system failure.
2. An interrupt occurs.
3. A power-on reset (if VSYS is a logic high).
The PSE pin is set low by writing a high into bit 6 (powerdown bit) in the Interrupt Control Register.
POR-Power-on reset. A Schmitt-trigger input that generates a power-on internal reset signal using an external R-C
network. Both control registers and frequency dividers for
the oscillator and line Input are reset. The status register is
reset exceptfor the fi rstti me up bit (B4), which is set. Si ngle
!!!Ill>ly or battery back-up operation is selected at the end of
POR.
LINE-This input is used for two functions. The first
function utilizes the input signal as the frequency source for
the timekeeping counters. This function. is selected by

Vsys- This input is connected to the system voltage. After
the CPU initiates power down by setting bit 6 in the
Interrupt Control Register to "1", the level on this pin will
terminate power down if it rises about 0.7 volt above the
level at the VBATT input pin after previously falling below
VBATT + 0.7 volt. When power down is terminated, the PSE
pin will return high and the Clock Output will be enabled.
The CPUR output pin will also return high. The logic level
present at this pin at the end of POR determines the
CDP68HC68T1's operating mode.
V BATT- The oscillator power source. The positive terminal of
the battery should be connected to this pin. When the level
on the VSYS pin falls below VBATT +0.7 volt, the VBATT pin will
be internally connected to the Voo pin. When the voltage on
VSYS rises a threshold above (- 0.7 V) the voltage on VBATT,
the connection from VBATT to the Voo pin is opened. When
the "LINE" input is used as the frequency source, VBATT may
be tied to Voo or Vss. The "XTAL IN" pin must be at Vss if
VBATT is at Vss. If VBATT is connected to Voo, the "XTAL IN" pin
can be tied to Vss or Voo.

XTAl IN, XTAl OUT-These pins are connected to a
32,768-Hz, 1.048S76-MHz, 2.0971S2-MHz or 4.194304-MHz
crystal. If an external clock is used, it should be connected
to "XTAL IN" with "XTAL OUT" left open.
Vo o -

6-59

The positive power-supply pin.

CDP68HC68T1
REGISTERS
CLOCK CONTROL REGISTER (Write/Read) - Address 31 H
D7

D6

D5

D4

D3

D2

D1

DO

START

liNE

ClK OUT

ClK OUT

ClK OUT

XTAl

XTAl
SEl
0

50 Hz

STOP

XTAl
SEl
1

soliz

2

1

0

CLOCK CONTROL REGISTER

INTERRUPT CONTROL REGISTER

START-STOP-A high written into this bit will enable the
counter stages of the clock circuitry. A low will hold all bits
reset in the divider chain from 32 Hz to 1 Hz. A clock out
selected by bits 0, 1 and 2 will not be affected by the stop
function except the 1 and 2-Hz outputs.

WATCHDOG-When this bit is set high, the watchdog
operation will be enabled. This function requires the CPU to
toggle the CE pin periodically without a serial-transfer
requirement. In the event this does not occur, a CPU reset
will be issued. Status register must be read before reenabling watchdog.

lINE-XTAl-When this bit is set high, clock operation will
use the 50 or 60-cycle input present at the LINE input pin.
When the bit is low, the crystal input will generate the 1-Hz
time update.
XTAl SELECT-One of 4 possible crystals is selected by
value in these two bits.
o = 4.194304 MHz
2 = 1.048576 MHz
1 = 2.097152 MHz
3 = 32,768 Hz
50-60 Hz-50 Hz is selected as the line input frequency
when this bit is set high. A low will select 60 Hz. The powersense bit in the Interrupt Control Register must be set low
for line frequency operation.
CLOCK OUT-The three bits specify one of the 7 frequencies to be used as the squarewave clock output.
o = XTAl
4 = Disable (low output)
5 = 1 Hz
1 = XTAU2
2 = XTAl/4
6 = 2 Hz
7 = 50 or 60 Hz
3 = XT AU8
XT Al Operation = 64 Hz
All bits are reset by a power-on reset. Therefore, the XTAl is
selected as the clock output at this time.

POWER DOWN-A high in this location will initiate a power
down. A CPU reset will occur, the ClK OUT and PSE output
pins will be set low and the serial interface will be disabled.
POWER SENSE-This bit is used to enable the line input
pin to sense a power failure. It is set high for this function.
When power sense is selected, the input to the 50/60-Hz
prescaler is disconnected. Therefore, crystal operation is
required when power sense is enabled. An interrupt is
generated when a power failure is sensed and the power
sense and Interrupt True bit in the Status Register are set.
When power sense is activated, a "0" must be written to this
location followed by a "1" to re-enable power sense.
ALARM-The output of the alarm comparator is enabled
when this bit is set high. When a comparison occurs
between the seconds, minutes and hours time and alarm
counters, the interrupt output is activated. When loading
the time counters, this bit should be set low to avoid a false
interrupt. This is not required when loading the alarm
counters. See PIN FUNCTIONS, INT for explanation of
alarm delay.
PERIODIC SELECT-The value in these 4 bits will select
the frequency of the periodic output. (See Table J).

INTERRUPT CONTROL REGISTER (Write/Read) - Address 32H
D7
WATCHDOG

D6
POWER
DOWN

D5
POWER
SENSE

D4
ALARM

I

DO

D1

D2

D3

I

I

PERIODIC SELECT

I
All bits are reset by power-on reset.

6-60

I

I

CDP68HC68T1
Table I - Periodic Interrupt Output
FREQUENCY TIMEBASE
00-03
VALUE

PERIODIC-INTERRUPT
OUTPUT FREQUENCY

0

Disable

XTAL

1

2048 Hz

X

2

1024 Hz

X

3

512 Hz

X

4

256 Hz

X

5

128 Hz

X

6

64 Hz

X

LINE

50 or 60 Hz

X

7

32 Hz

X

8

16 Hz

X

9

8 Hz

X

10

4 Hz

X

11

2 Hz

X

X

12

1 Hz

X

X

13

Minute

X

X

14

Hour

X

X

15

Day

X

X

STATUS REGISTER (Read Only) - Address 30H

Ww
07

06

05

04

03

02

01

DO

=» .....

-.
::~

Cw

0

WATCHDOG

TEST
MODE

FIRST
TIME
UP

WATCHDOG - If this bit is set high, the watchdog circuit
has detected a CPU failure.

INTERRUPT
TRUE

POWER
ALARM
CLOCK
SENSE
INTERRUPT INTERRUPT
INTERRUPT

POWER-SENSE INTERRUPT - This bit set high signifies
that the power-sense circuit has generated an interrupt.
ALARM INTERRUPT - When the seconds, minutes and
hours time and alarm counter are equal, this bit will be set
high. Status Register must be read before Loading Interrupt
Control Register for valid alarm indication after alarm
activates.

TEST MODE - When this bit is set high, the device is in the
TEST MODE.
FIRST-TIME UP - Power-on reset sets this bit high. This
signifies that data In the RAM and Clock is not valid and
should be initialized.

CLOCK INTERRUPT - A periodic interrupt will set this bit
high,

INTERRUPT TRUE - A high in this bit signifies that one of
the three interrupts (Power Sense, Alarm, and Clock) is
valid.

All bits are reset by a power-on reset except the "FIRSTTIME UP" which is set. All bits except the power-sense bit
are reset after a read of this register.

6-61

ffia..

wii:

-w

~a..

CDP68HC68T1
SERIAL PERIPHERAL INTERFACE (SPI)
PIN SIGNAL DESCRIPTION

CE (Chip Enable)·· - A positive chip-enable input. A low
level at this input holds the serial interface logic in a reset
state, and disables the output driver at the MISO pin.

SCK (Serial Clock Inpul)· - This input causes serial data to
be latched from the MOSI input and shifted outon the MISO
output.
MOSI (Master Out/Slave In)· - Data bytes are shifted in at
this pin, most significant bit (MSB) first.

• These Inputs will retain their previous state lithe line driving them
goes into a Hlgh-Z state.

MISO (Master In/Slave Out) - Data bytes are shifted out at
this pin, most signficant bit (MSB) first.

•• The CE Input has as Internal pull-down device-lIthe input is in a
low state belore going to a High Z, the input can be left in a High Z.

TRUTH TABLE
SIGNAL

MODE
CE

SCK*

DISABLED
RESET

L

INPUT
DISABLED

WRITE

H

CPOL = 1

J

CPOL= 0

'--

READ

H

CPOL = 1
CPOL= 0

'-.r

MOSI

MISO

INPUT
DISABLED

HIGHZ

DATA BIT
LATCH

HIGHZ

X

NEXT DATA
BIT SHIFTED
OUTa

a MISO remains at a High Z until 8 bits of data are ready to be shifted out during a READ. It remains at a High Z during
the entire WRITE cycle .
• When interfacing to CDP6BHC05 microcontroliars, serial clock phase bft, CPHA, must be sat - 1 in the microcomputer's control ragister.

E

FUNCTIONAL DESCRIPTION

CPOL=

The Serial Peripheral Interface (SPI) utilized by the
CDP68HC68T1 is a serial synchronous bus for address and
data transfers. The clock, which is generated by the
microcomputer, is active only during address and data
transfers. In systems using the CDP68HC05C4 or
CDP68HC05D2, the inactive clock polarity is determined by
the CPOL bit in the microcomputer's control register. A
unique feature ofthe CDP68HC68T1 is that it automatically
determines the level of the inactive clock by sampling SCK
when CE becomes active (see Fig. 8). Input data (MOSI) is
latched internally on the Internal Strobe edge and output
data (MISO) is shifted out on the Shift edge, as defined by
Fig. 8. There is one clock for each data bit transferred
(address as well as data bits are transferred in groups of 8).

{
I
SCK

CPOL=O{E
SCK

MOSl: _ _ _ _ _ _- {

NOTE'

"CPOL" IS A BIT THAT IS SET IN THE
MICROCOMPUTER'S CONTROL REGISTER
92CS-:37945

Fig. 8 - Serial RAM clock (SCK) as a function of MCU clock
polarity (CPOL).

6-62

CDP68HC68T1
BIT-7

ADDRESS AND DATA FORMAT

6

There are three types of serial transfer.

11 wAi

1. Address Control - Fig. 9
2. READ or WRITE Data - Fig. 10
3. Watchdog Reset (actually a non-transfer) - Fig. 11
The Address/Control and Data bytes are shifted MSB first,
into the serial data input (MOSI) and out of the serial data
output (MISO).
Any transfer of data requires an Address/Control byte to
specify a Write or Read operation and to select a Clock or
RAM location, followed by one or more bytes of data.
Data is transferred outof MISOfora Read and into MOSI for
a Write operation.
ADDRESS/CONTROL BYTE - Fig. 9

It is always the first byte received after CE goes true. To
transmit a new address, CE must first go false and then true
again. Bit 5 is used to select between Clock and RAM
locations.
CE

5

3

2

A3

A2

4

I I~ I"I I 1" I" I
0

0-4

AO-A4

5

CLOCK/RAM

6

o

7

W/R

Selects 5-Bit HEX Address of
RAM or specifies Clock Register.
Most Significant Address Bit.
If equal to "1", AO through A4
selects a Clock Register.
If equal to "0", AO through A4
selects one of 32 RAM locations.
Must be set to "0" when not in
Test Mode
W/R = "1" initiates one or more
WRITE cycles.
W/R ="0", initiates one or more
READ cycles.

~

MOS:t~
*

o

WiR

A3

A4

A2

AO~

AI

SCK CAN BE EITHER POLAR ITY.

92CM-37946

Fig. 9 - Address/Control byte-transfer wavefvrms.

•

READ/WRITE DATA - (See Fig. 10)

Read/Write data follows the Address/Control byte.
BIT 7
6
5

I

D7

I

I

D6

D5

4

I

D4

I

D3

I

D2

......
=»-01

o

2

3

I

D1

I

DO

:~

CW

-:c
a::Q..
~a:

I

-w
~Q..

L

CE

MOSl:~

MISO~
*

0

07

06

05

04

07

06

05

04

03

03

02

01

02

01

OO~
92CM - 37948

SCK CAN BE EITHER POLARITY

Fig. 10 - Read/Write data-transfer waveforms.

6-63

CDP68HC68T1
WATCHDOG RESET - (See Fig. 11)

ADDRESS AND. DATA

When watchdog operation is selected, CE must be toggled
periodically or a CPU reset will be outputted.

Data transfers can occur one byte at a time (Fig. 12) or in a
multi byte burst mode (Fig. 13). After the Real-Time Clock is
enabled, an Address/Control word is sent to select the
CLOCK or RAM and select the type of operation (i.e., Read
or Write). For a single-byte Read or Write, one byte is
transferred to or from the clock register or RAM location
specified in the Address/Control byte and the Real-Time
Clock is then disabled. Write cycle causes the latched clock
register or RAM address to automatically increment.
Incrementing continues after each transfer until the device
is disabled. After incrementing to 1FH the address will
"wrap"..to OOH and continue. Therefore, when the RAM is
selected the address will "wrap" to OOH and when the clock
is selected the address will "wrap" 20H.

I

I

SERVI CE
SERvICL-l
I-"TIME ~TlME - ,

n

n

CE _ _ _ _ _ _ _

:

SCK-------------------------------------

92CS-37947

Fig. 11 - Watchdog operation waveforms.

L

CE

WRITE

III I I I II

II I III II

SCK

{MOSI~

,.£..t.:L..::A._____
A_D_D_R_E_SS__B_V_T_E____..L________W_R_I_TE
__
D_AT_A____

.....I~
"'_'.L. t. £. I.~"'_'." " ':. : . .: . .: . .:. . :.~

ADDRESS BVTE
READ {MOS:I

MISO------------------------~(~

D_A_~

___________
R_E_AD
___

________________

_'~

92CM-37949

Fig. 12 - Single-byte transfer waveforms.

CE

W R IT E {MOS:I

I II II I II 111111111: IIII11111

11111111

SCK

~W:1'7"'>. .,. . ,. ,.- A-D-D-R-E-S - B-YT-E- . - D-AT-A-.-B-V-T-E- - . -D-A-T-A-B-V-T-E- -:! !;-D-AT-A- B-YT-E- - .,~,. . .rT'T'"l'
:

...

~'?

.

MOSI

7"77~~ADDR-ESS-BYTE---v?~'7"7"7"77?'777.
'777'777"7"7"7'7'7'7.: ~i7'7-?'7'7777'7777'7"77'7'7"

{
READ

,...-------,.

~

II.

,..-------.,.

M:ISO----------------~

ADDRESS

WiR

ADDRESS {

ADDRESS
ADDRESS

Fig. 13 - Multiple-byte transfer waveforms.

6-64

92CM-37950

CDP68HC68T1
DYNAMIC CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS-BUS TIMING Voo
C L = 200 pF, s•• Figs. 14 and 15

± 10%, Vss = 0 V dc, TA = -40'C to +85'C,
LIMITS (ALL TYPES)

IDENT.NO.

Voo = 5 V

Voo = 3.3 V

CHARACTERISTIC

UNITS

Min.

Max.

Min.

Max.

CD

Chip Enable Set-Up Time

tevcv

200

-

100

-

0
®
CD
®
CD
®

Chip Enable After Clock Hold Time

tevex

250

-

125

-

Clock Width High

tWH

400

-

200

-

Clock Width Low

tWL

400

-

200

-

Data In to Clock Set-Up-Time

tovev

200

-

100

-

Clock to Data Propagation Delay

tevov

-

200

-

100

Chip Disable to Output High Z

lexQz

-

200

-

100

CD)

Output Rise Time

I,

-

200

-

100

@

Output Fall Time

tf

-

200

-

100

®
®
©

Data In After Clock Hold Time

tevox

200

-

100

-

Clock to Data Out Active

tevQx

-

200

-

100

Clock Recovery Time

tRec

200

-

200

-

ns

DON

))))))

CE

SCK

92CM-37951RI

Fig. 14 - WRITE-cycle timing waveforms.

6-65

m

CDP68HC68T1

OIOS1

MISO

+I+t+N

----t----+---t----ti\!I:-~~l\.::j \-~,~--...;;r

CE

SCK

Fig. 15 - READ-cycle timing waveforms.

SYSTEM DIAGRAMS

AC
LINE

I

I

BRIDGE
I REGULATORI

.r
~
VOO POR

-"

~

VOO
J:RQ

INT
VSYS I - LINE

~r

COP68HC68TI

rOOf

~ VBATT CPUR

CE
SCK

COP
68HC0502

RESET
PORT
SCK

MOSJ:

MOS:!:

M.ISO
XTAL IN

MISO

~

92CM-37953R2

Example of a system in which power is always on. Clock
circuit driven by line input frequency.

Fig. 16 - Power-on always system diagram.

6-66

t

CDP68HC68T1

ill
I
qf1

VBATT VOOI
POR

J

Voo

VSYS

INT I--:-:---:;o,-----,~-~ IRQ
COP68HC68T1
COP
68HC05D2
CPUR I-----+---<'--~ RESET
CLK OUT f------~~ OSC 1
CE 1 - - - - - - - - - 1 PORT( •. g.PCO
MISO I-------~ MISO
MOSI 1 - - - - - - - - - 1 MOSI
SCK

1---------1 SCK
,,?:CM-37954R2

Example of a system in which the power is controlled by an
external source. The LINE input pin can sense when the
switch opens by use of the POWER-SENSE INTERRUPT.
The CDP68HC68T1 crystal drives the clock input to the
CPU using the CLK OUT pin. On power down when VSYS <
VBATT + 0.7 V. VeArr will power the CDP68HC68T1. A
threshold detect activates a p-channel switch, connecting
VeATT to Voo. VeATT always supplies power to the oscillator,
keeping voltage frequency variation to a minimum.
Fig. 17 - Externally-controlled power system diagram.

A Procedure for Power-Down Operation might consist of
the following:

4. The CPU reads the status register again after several
milliseconds to determine validity of power failure.
5. The CPU sets power-down bit 6 and disables all
interrupts in the Interrupt Control Register when power
down is verified. This causes the CPU reset and clock
out to be held low and disconnects the serial interface.
6. When power returns and Vsys rises above VeATT, power
down is terminated. The CPU reset is released and
serial communication is established.

1. Set power-sense operation by writing bit 5 high in the
Interrupt Control Register.
2. When an interrupt occurs, the CPU reads the status
register to determine the interrupt source.
3. Sensing a power failure, the CPU does the necessary
housekeeping to prepare for shutdown.

6-67

CDP68HC68T1

(EPS)
ENABLED

POWER
SUPPLY

XTAL

CPUR 1-----.--+-4-0"'1 RESET
CDP

6BHC05D2

INT

.....- - - - - - - - - i L I N E

f------------t~

IRQ

~b~ f-----------t~OSC1
CE~----------~PORT

"DO RTC

VSS

SPI~----~r_---~~SPI

92CM-42270RI

Fig. 18 - Example of a system with a battery back-up.

6-68

CDP68HC68T1

r+----l.. ENABLED

CLOCK
BUTTON
...L.

.---------------+----1-----.

+

12 v-=-

1

Voo

VBATT
POR

~

PORT
PSE

XTAL
2MHz
CPUR

RESET

J-

Tl

• OSC1

elK OUT

COP
68HC05C4

TNT

IRQ

SPI

SP.I

CE

PORT

VSS

Vss

92CM-42271

Example of an automotive system. The VSYS and LINE
inputs can be used to sense the ignition turning on and off.
An external switch is included to activate the system
without turning on the ignition. Also, the CMOS CPU is not
powered down with the system Voo, but is held in a low
power reset mode during power down. When restoring
power the CDP68HC68T1 will enable the ClK OUT pin and
set the PSE and CPUR high.
Fig. 19 - Automotive system diagram.

IMPORTANT APPLICATION NOTE:
Those units with a code of 6PG have delayed alarm interrupts
of 8.3ms regardless of CDP68HC68T1's operating frequency.
(See PIN FUNCTIONS, INT.) In addition, reading the status register before delayed alarm activates will disable alarm signal.

6-69

Ell HARRIS

CDP68HC68T2

PRELIMINARY

CMOS Real-Time Clock
With Serial Peripheral Interface (SPI) Bus

January 1991

Features

Pinout

• SPI (Serial Peripheral Interface)

16 LEAD CERAMIC
TQPVIEW

DIP

• 12 Hour Clock with AM/PM

VDD

• 1 Hz Output Line
• 1 per Minute Interrupt Output

XTAL OUT
XTAL IN

• Low Current Operation
~ 251lA @ 3V, 32kHz
~ 1mA @ 5V, 4.194MHz

TEST IN
FSEL1

• Low Minimum Timekeeping Voltage of 2.2V

FSEL2

• Available in 16 pin DIP or 16 pin SOP
RESET
MON

Description
The CDP68HC68T2 Real-Time Clock provides a 12 hour
AM/PM clock function and a serial peripheral interface (SPI)
bus. The primary function of the clock is to divide down a
frequency Input that can be supplied by the on board
oscillator in conjunction with an external crystal or by an
external clock source. The clock operates with either a
32+kHz, l+MHz, 2+MHz, or 4+MHz crystal or by an
external clock source at these frequencies. The time
registers furnish seconds, minutes, and hours data. The
data in the time registers is in the BCD formal During
normal operation, the T2 provides a continuous 1 Hertz
square wave clock output after oscillator power up. In the

test mode, the clock output after power up is at the oscillator
rate divided by 2.
Computer handshaking is established with a "wired-OR"
interrupt output. The interrupt goes active low (with open
drain) whenever the minute counter advances, and remains
low until either CE goes high (reading the data) or if RESET
goes low (resets all counters and prescalers).
The CD P68HC68T2 Is available in a 16 lead hermetic dualin-line ceramic package (0 suffix), in a 16 lead dual-in-line
plastic package (E suffix), and in a 16 lead small outline
plastiC package (M suffix).

I

Blo ck Diagram

-TEST IN

CE
XTAL IN
XTAL OUT I OSCILLATOR
FSEL1
FSEL2

I-H

Y

I

PRESCALE I

.1

PRESCALE
.1 SELECT

I

H

CLOCK OUT

o RESET

CLOCK
LOGIC

,

POWER
SENSE
CONTROL

I

r-.
T

~ I
SCK
MISO
MOSI

SECOND

MINUTE

CLOCK
SELECT

t

~
~

,

Y

t

II

,

MON

t
CLOCK
CONTROL
REGISTER

AM·PMAND
HOUR
LOGIC

,

I

t
I ,

HOUR

I

8- BIT DATA BUS

h

INTERRUPT ~
CONTROL
REGISTER

f

rt--Aw

SERIAL
INTERFACE
INT

Copyright @ Harris Corporation 1991

Ale Number

6-70

2753.1

CDP68HC68T2

Functional Description
The CDP68HC68T2 real time clock employs three time
counters for seconds (0-59), minutes (0-59), and hours
(01-12). Data in the time registers is in the BCD format with
most significant bit (MSB) first; the hours counter includes
an AM/PM bit. The Serial, Peripheral Interface (SPI) utilized
by the CDP68HC68T2 IS a serial synchronous bus for
address and data transfers. SPI transfers can be one, two,
or three bytes, but the order is always minutes, hours, and
seconds. The MISO output is active only while CE is high,
otherwise it is three state. Each SPI transfer includes
bidirectional data, each register is read out while it is being
written to. If only a read is required, then dummy data
should be written to the register. The logic checks for
certain illegal BCD code which inhibit the latching of written
data, however, writing FFH for dummy write data is
preferred. The seconds register cannot be written to, but is
reset whenever data is written to the minutes register. When
reset is active (RESET low or power on reset), the counters
and prescalers are reset to 00:00:00 AM. The SPI clock
(SCK) input rate should be equal to, or less than 1MHz. SPI
transfers less than 8 clock cycles will be ignored, therefore,
SPI transmission can be terminated during this time by
pulling CE low.
For correct SPI transmission, there must be at least 3
oscillator cycles (approx. 90llS @ 32kHz) delay for the

following: a) between any SPI byte transmission, b) after CE
goes active and before the first byte is transferred and,
c) between successive CE active signals.
Clocking of seconds-minutes-hours is prevented whenever
chip enable (CE) is high. Any clocking of the seconds counter will be acted on after the enable signal falls (becomes
inactive). This prevents erroneous data from being read.
Note that this freeze circuit is only active for 250-500mS.
After this time it automatically releases so that any potential
seconds clock pulse will not be lost. Also after this time, the
chip will automatically terminate the internal enable line and
tri-state the data output line, MISO. This timeout is to prevent erroneous loss of data if the CE signal becomes hung
up in the active high state due to the CPU being put into the
sleep/wait state during a data transfer.
In the open drain configuration, the INT pin goes active low
whenever the minute counter advances and remains low
until either CE goes high (reading the data), or RESET goes
low (resets all counters and prescalers). With a mask option,
the open drain can be replaced with a full CMOS inverter.
In the normal operating mode, the clock output (ClK OUT)
after powerup is a one hertz square wave output. In the
TEST mode, the clock output frequency after powerup is
equal to the oscillator frequency divided by two.

Crystal Frequency Selection - One of 4 possible crystal frequencies is selected by the logic level on FSEl1 and FSEl2.
CRYSTAL FREQUENCY

4.194304MHz

1.048S76MHz

2.0971S2MHz

32,768Hz

FSEL1

1

1

0

0

FSEL2

1

0

1

0

Clock Registers Data Format HEX ADDRESS

DB7

20

0

21

0

22

0

DB6

lOBS

I

DB4

DB3

_O-SBCD_
_ O-SBCD_
0

lAM/PM

I

X*

*X=Oor1

6-71

I

DB2

I

DB1

lOBO

REGISTER NAME

_0-9 BCD_

Seconds (Read only)

_0-9 BCD _

Minutes (R/W)

_0-9 BCD_

Hours (R/W)

fl)HARRIS

CDP68HC68W1
Digital Pulse Width Modulator

January 1991

Features

Pinout

• Programmable Frequency and Duty Cycle Output
• Serial Bus Input; Compatible With Motorola/Harris SPI Bus, Simple ShiftRegister Type Interface
• 8 Lead Mini DIP Package
• Schmitt Trigger Clock Input

PACKAGE TYPE E
TOP VIEW

CLKG.
2

7

PWM

VT

3

6

SCK

5

DATA

VSS -

• 4V to 6V Operation, -40 0 C to +S5 0 C Temperature Range

Voo

CS

4

92CS-41211

• SMHz Clock Input Frequency

Description
The CDP68HC68W1 modulates a clock input to supply a variable frequency and
duty-cycle output signal. Three 8-bit registers (pulse width, frequency and control)
are accessed serially after power is applied to initialize device operation. The value
in the pulse width register selects the high duration of the output period. The
frequency register byte divides the clock input frequency and determines the overall
output clock period. The input clock can be further divided by two or a
low power mode may be selected by the lower two bits in the control register. A
comparator circuit allows threshold control by setting the output low if the input at
the VT pin rises above 0.75 volt. The CDP68HC68W1 is supplied in an 8 lead mini
DIP plastic package (E suffix).

Block Diagram

CONTROL REGISTER
2-STAGE SHIFT
LOAD

92CL-41213

FIGURE 1
Copyright © Harris Corporation 1991

File Number

6-72

1919.1

CDP68HC68W7
Maximum Ratings Absolute Maximum Values
DC Supply Voltage Range, (VDD) ••••••..•••••••••• -0.5V to + 7V
(Voltage Referenced to VSS Terminal)
Input Voltage Range, All Inputs ..••••.••....• -0.5V to VDD +0.5V
DC Input Current, Any One Input •••••••••••••••••••••••• ±1 OmA
Power Dissipation Per Package (PO)
TA =-400 C to +600 C (Package Type E) •••••••••••••• 500mW
TA = +600C to +85 0 C (Package Type E) .•••.. Derate Linearly at
12mW/oC to 200mW

Device Dissipation Per Output Transistor. • • • • • • • • • • . • •• 100mW
TA = Full Package Temperature Range (All Package Types)
Operating Temperature Range (TAl .•••.••••••. -400C to +850 C
Storage Temperature Range (TSTG) •••.•••.•. -650 C to +1500 C
Lead Temperature (During Soldering) ••.•••••••••••••.• +2650 C
At Distance 1/16 ± 1/32 In. (1.59 ± 0.79mm) From Case for
10s Max

Recommended Operating Conditions TA = -400 C to +850 C. For maximum reliability, device should always be
operated within the following ranges:
LIMITS
CHARACTERISTIC

SYMBOL

DC Operating Voltage Range
Input Voltage Range (Except VT Pin)
VT Pin Output Voltage Threshold
Sedal Clock Frequency, SCK (VDD

=4.5V)

Clock Frequency

Static Electrical Characteristic TA

MIN.

MAX.

UNITS

-

4

6

V

VIH
Vil

0.7VDD
-0.3

VDD+O.3V
0.3VDD

V

VIT

0.4

0.15VDD

V

FSCK

DC

2.1

MHz

FClK

DC

8

MHz

= -40o C to +850 C, Voo = 5V ±

10%
liMITS

CHARACTERISTIC

SYMBOL

MIN.

MAX.

UNITS

Device Current in "Power Down" Mode, Clock Disabled

IpD

1

IIA

low level Output Voltage (IOl = 1.6mA)

VOL

-

0.4

V

VOH

VDD-0.4V

-

V

liN

±1

IJA

IOPER

-

1

mA

CIN

-

10

pF

High level Output Voltage (IOH

=-1.6mA)

Input leakage Current
Operating Device Current (fClK = 1 MHz)
Clock Input Capacitance (VIN = OV, fClK = 1 MHz, TA = +250 C

Pin Signal Functions
PIN
NO.

PIN
PIN
SIGNAL FUNCTION

PIN1:

ClK

(INPUT)*

CLOCK - The clock signal to be altered by the PWM circuitry. This is the source of the PWM output
This input frequency can be Internally divided by either one or two, depending on the state of the CD bit
in the control register.

PIN 2:

CS

(lNOUT)

CHIP SELECT -. A high-ta-Iow (1 to 0) transition selects the chip. A low-ta-high (0 to 1) transition
deselects the chip and transfers data from tbe shift registers to the data registers.

PIN 3:

VT

(INPUT)

VOLTAGE THRESHOLD - An analog voltage greater than 0.75V (at VDD 5V) on this pin willimmedlately cause the PWM output to go to logic ''0''. This will be the status until the VT input is retumed to a
voltage below 0.4V, the W1 Is deselected, and then one or more of the data registers is written to.

=

An analog voltage on this pin less than 0.75V (at VDD
by the values in the registers.
PIN 4:

VSS

(POWER)

PIN 5:

DATA

(INPUT)

PIN6:

SCK

(INPUT)

PIN 7:

PWM.- (OUTPUT)

PIN 8:

VDD

(POWER)

=5V) will allow the device to operate as specified

GROUND - Establishes the low (logic 0) voltage level.
Data input at this pin is clocked Into the shift register O.e., latched) on the rising edge of the serial clock
lSCK), most significant bits first.
SERIAl: CLOCK - A rising edge on this pin will shift data available at the (DATA) pin into the shift register.
This pin provides the resultant output frequency and pulse width. After VDD power up, the output on
this pin will remain a logic "0", until the chip Is selected, 24 bits of information clocked in, and the chip
deselected.
Establishes the high (logic 1) voltage level.

*Schmftttrigger input.

6-73

CDP68HC68W1
Functional Description

appear at the output only after the end of the previous total
output period.

Introduction
The digital pulse width modular (DPWM) divides down a
clock signal supplied via ClK Pin 1 as specified by its
control, frequency and pulse width data registers. The
resultant output signal, with altered frequency and duty
cycle, appears at PWM Pin 7.
Serial Port
Data are entered into the three DPWM registers serially
through the data pin, Pin 5, accompanied by a signal
applied to SCK Pin 6. The user can supply these serial data
via shift register(s) or a microcomputer's serial port, such as
the SPI port available on most 68HC05 microcomputers.
Microcomputer I/O lines can also be used to simulate a
serial port.
Data are written serially, most significant bit first, in 8, 18, or
24-bit increments. Data are sampled and shifted into the
PWMs shift register on each rising edge of the SCK. The
serial clock should remain low when inactive. Therefore,
when using a 68HC05 microcomputer's SPI port to provide
data, program the microcomputer's SPI control register bits
CPOl, CPHA to 0, O.
The CDP68HC68W1 latches data words after device
deselection. Therefore, CS must go high (inactive) following
each write to the W1.

Altering the Frequency: The frequency can be changed
by selecting the chip, inputting 16-bits (frequency information followed by pulse width information), and deselecting
the chip. Deselection will transfer 16 bits of data from the
shift register into the frequency register and PW register.
The updated frequency and PW information will appear at
the PWM output pin only after the end of the previous total
output period.
Altering the Control Word: Changing the clock divider
and/or power control bit in the CDP68HC68W1 control register requires full 24-bit programming, as described under
Power Up Initialization.

Pulse Width Modulator Data Registers
Control Register
Bit

x ~ rol

x

x

x

x

6

5

4

320

Byte One:

Control Register
These bits are don't care.

Bit 1 (PC)

Power Control Bit. If this bit is a "0", the chip
will remain in the active state. If the bit is set
to a "1", internal clocking and the voltage
comparator (VT) circuit and voltage reference will be disabled. Thus the chip will
enter a low current drain mode. The chip may
only reenter the active mode by clearing
this bit and clocking In a full 24 bits of
information.

Bit 0 (CD)

Clock Divider Bit. If this bit is a "0", the chip
will set internal clocking (ClK) at a divideby-one rate with respect to the (ClK). If this
bit is set to "1", the internal clocking will be
set to a divide-by-2 state.

1. The chip is selected (CS pin pulled low).
2. 24 bit of information are shifted in.
The 24-bits of necessary information pertain to the loading
of the three PWM 8-bit registers, in the following order:

1. Control register

3. Pulse width register

7

Bits 7-2

Upon VDD power up, the output of the PWM chip will
remain at a low level (logic zero) until:

2. Frequency register

_ _ _ _ _ _ _ _ _ _ _ _ _....

X = Don't Care

Power-Up Initialization

3. The chip is deselected (CS pin pulled high).

~

Ix

Byte Two:

Frequency Data Register

Bits 7-0

This register contains the value that will
determine the output frequency or total
period by:

See section entitled "Pulse Width

Modulator Data
Registers" for a description of each register. Once
initialized, the specified PWM output signal will appear until
the device is reprogrammed or the voltage on the VT pin
rises above the specified threshold. Reprogramming the
device will update the PWM output after the end of the
present output clock period.
Reprogramming Shortcuts

(N+1)(CD+1)
Where FOUT

=resultant PWM output
frequency

FIN

=the frequency of input ClK

n = value In frequency register

After the device has been fully programmed upon power up,
it is only necessary to Input 8 bits of information to alter the
output pulse width, or 16 bits to alter the output frequency.
Altering the Pulse Width: The pulse width may be
changed by selecting the chip, Inputting 8 bits, and
deselecting the chip. By deselecting the chip, data from the
first 8-bit shift register are latched into the pulse width
register (PWM register). The frequency and control registers
remain unchanged. The updated PWM information will

6-74

CD

=value of clock divider bit In
control register

For a case of n (binary value in frequency

=

register) equal to 5, and CD (clock divider)
the PWM output will be a
frequency 1/6 that of the input crock (ClK).
Likewise, the output clock period will be
equal to 6 input ClK periods.

o (divide-by-1),

CDP68HC68W1
Byte Three:

Pulse Width Data Register

Bits 7-0

This register contains the value that will
determine the pulse width or duty cycle (high
,duration) of the output PWM waveform.

OR: To then alter the frequency (and possIbly PW):
1.
2.
3.
4.

PW=(N+1)(CD+1)
Where PW = Pulse width out as measured in number of input
ClK periods.
CD = Value of clock divider bit in
control register.
N = Value in PW register.
For a case of n (binary value in PW register)
equal to 3 and CD (clock divider) = 0
(divide-by-1), the output will be 4 input clock
periods of a high level followed by the
remaining clocks of the total period which
will be a low level.
Assuming the frequency register contains a
value of 5, the resultant PWM output would
be high for 4 ClK periods, low for 2.

Using the CDP68HC68W1

*All writes use a-bit words
CDP68HC68W1 Registers
1. Control Register:
- Bit 0 = ClK + 2 if set ("CD bit")
- Bit 1 = Power down if set
2. Frequency Register:
- A value of N written to the frequency register yields an
output frequency of:
Frequency Output =

ClK Frequency
(N+1) (CD+1)

3. Pulse Width Register:
- Determines duty cycle (high duration) of PWM output
signal. A value of N written to the PW register yields a
pulse width of:
Pulse Width = (N+1) (CD+1)

(Summary)

EXAMPLE: when CD = 0,
frequency regisfer = 4, pulse width
register = 1; output = high for 2 input ClK
periods, low for 3:

Programming the CDP68HC68W1
1.
2.
3.
4.
5.

Select chip
Write to frequency register*
Write to pulse width register*
Deselect chip

Select chip
Write to control register*
Write to frequency register*
Write to pulse width register*
Deselect chip

1. Select chip
2. Then write (most significant bit first) to the
control, the frequency, and pulse width registers (control = 00, frequency = 04, PW = 1)
3. Deselect the chip

NEXT: To then alter the pulse wIdth:
1. Select chip
2. Write to pulse width register*
3. Deselect chip

~ (~)~~-----------------------------------------------------Curves
continued
immediately
below

SERIAL elK (SCK)

DATA

I
I
DON'T

CARE

=•

I
I

DON'T DON'T DON'T
CARE CARE CARE

=•

=•

=•

DON'T

CARE

=•

DON'T POWER CLOCK
CONT DIVIDE
CARE

=•

=•

=•

BIT

7

=•

BIT

BIT

=•

=•

•

5

BIT

BIT

•
=.

3

=•

elK =0
PWM-OUT=O

(~)--------------------------------------------------~,---I
I

SCK

I

I
I

DATA

ClK

PWM·OUT

BIT 2

BIT 1

BIT 0

alT 7

BIT 6

BIT 5

BIT 4

=1

=0

:0

",0

=0

=0

=0

I
I
I

I

---------------------~r__
6-75

Curves
) continued
below

CDP68HC68W1
New pulse width out begins and PWM goes high when CS
is raised after last SCK pulse (assuming no previous timeout). PWM then toggles on falling ClK edges.

Resulting output waveform: Control = 00 = Oivide-by-1.
frequency = 4:
Frequency =

INPClK
(04+1){0+1)
PW

INPClK

= --5--

= 1: (1+1) (0+1) = 2 ClKs high time
INPUT
CLOCK(CLK)

I

'------!·I

r

\ .... _ _ _.J.

OUTPUT
(PWM)

TOTAl. OUTPUT PERIOD =
5 X (INPUT CLOCK PERIOD)

Serial Peripheral Interface (SPI) Timing
CS
(INPUT)

SCK
(INPUT)

--!--.....,..I

Timing Characteristics Voo

= 5.0 VOC ±10%. VSS = 0 VOC. TA = -400 C to +85 0 C
LIMITS

I. D. NO.

MIN.

MAX.

UNITS

Serial Clock Frequency. fSCK

CHARACTERISTICS

DC

2.1

MHz

CycleTlme

480

ns

2

Enable Lead Time

240

-

3

Enable Lag Time

-

200

ns

4

Serial Clock (SCI<) High Time

190

-

ns

5

Serial Clock (SCK) Low Time

190

-

ns

1

6

Data Setup Time

100

7

Data Hold Time

100

8

=20OpF)
Risa Time (20% VOO to 70% VOO. CL =200pF)

9

Fall Time (70% VOO to 20% VOO. CL

6-76

-

ns

-

ns

100

ns

100

ns

ns

CP68HC68W1
PWM Timing

eLK
PWM------'

Timing Characteristics VDO = 5.0 VOC ±10%, VSS = 0 VDC, TA = -400 C to +85 0 C
LIMITS
I.D.NO.

CHARACTERISTICS

MIN.

MAX.

UNITS

Clock Frequency, fCLK

DC

B.O

MHz

1

Cycle Time

125

-

ns

2

Clock to PWM Out

-

125

ns

3

Clock High Time

50

-

ns

4

Clock Low Time

50

ns

5

Rise Time (20% VOD to 70% VOO)

-

100

ns

6

Fall time (70% VOO to 20% VOO)

-

100

ns

CDP68HC68W1 Application Example
The following example was written for a system which has
the COP68HC68Wl connected to the SPI bus of a
COP68HC05C4 microcontroller. The program sets the Wl
to run a divide by 200 frequency with a duty cycle of 30% by
writing to the Control Register, the Frequency Data

Register, and the Pulse Width Data Register. The frequency
and pulse width are then modified. Finally the pulse width is
modified without changing the frequency. The program was
assembled using the Harris HASM5 assembler.

*****.*******************.*.*****•••*******",*******•••******* •••***********

* File:
*
*
*
* Date:

Wl.S
Example Wl routines - sets Wl to a divide by
200 output with 30% duty cycle
Tue 09-25-1990

***********************************************************",***************
***************************************************************************

*

Partial Map of 68HC05C4 Hardware Registers

******************.,,*.*******•••************************************.*******
Registers,$OOOO

Section

0000

;PortA

0000
0001
0002
0003
0004
0005
0006
0007

PortA
PortB
PortC
PortO
DORA
DDRB
DDRC
DDRD

ds
ds
ds
ds
ds
ds
ds
ds

0008

_Freel

ds

2

;two unused locations

OOOA
0040=
0010=
OOOB
OOSO=
0007=
OOOC

SPCR
_SPE
_MSTR
SPSR
_SPIF
_SPIF
SPDR

ds
equ
equ
ds
equ
equ
ds

1
01000000b
00010000b
1
10000000b

;SPI Control Register
;SPI Enable bit
;SPI Master Mode bit
;SPI Status Register
;SPI Flag bit for ANDs, CMPs, etc.
;SPI Flag bit for BRSETs & BRClRs
;SPI Data Register

64
16
128
7

;Port A Data Direction Register

7
1

6-77

=
""""....
:~
c ...

-:
cca..

~ii2

...

-g;a..

CDP68HC68Wl
***************************************************************************

*
0000=

o

0002=

2

0001

=

W1 Constants

***************************************************************************
equ

o

;W1 is connected to bit 0 of Port A

equ
equ

00000010b
oooo0001b

;Power Control: 1 = power down
;Clock Divider: 1 = divide by 2

***************************************************************************

*

Main Routines

***************************************************************************
0100

Section Code,$0100

0100 CD0143 main

jsr

Inltiallze_W1

bclr
jsr

Set2oo_30
W1,PortA
SeLW1_SPI_Mode

0103
0105

1100
CD0138

;turn on PAO

;select W1 (CE is active low)
;Setup the 68HC05 SPI control ...
;to talk to the W1
*********************Set Up Control, Frequency, and Pulse Width
SendAIiCommands
0108 A601
#W1_CD
;set divide by two clock on W1
Ida
010A CD013D
jsr
SPI-xmit
010D A663
Ida
#99
;set frequency to divide by 200
jsr
010F CD013D
SPLxmit
0112 A61D
Ida
#29
;set pulse width to 30% duty cycle
jsr
0114 CD013D
SPI_xmit
DeselectW1_1
;deselect the W1 which loads registers
W1,PortA
bset
0117 1000
;with values transmitted
;do something else, then ....
********************* Modify Frequency and Pulse Width
ChangeFreq_and_Width
bclr
W1,PortA
0119 1100
;select W1 (CE is active low)
jsr
SeLW1_SPI_Mode
;Setup the 68HC05 SPI control ...
011B CD0138
;to talk to the W1
011E
0120
0123
0125

A631
CD013D
A609
CD013D

0128 1000

SendCommands2
Ida
jsr
Ida
jsr
DeselectW1_2
bset

#49
SPI_xmit
#9
SPLxmit

;setfrequencyto divide by 100 (the
;divide by 2 is still in effect)
;set pulse width to 20% duty cycle

W1,PortA

;deselect the W1 which loads registers
;with values transmitted
;do something else, then ...

*********************Modify Pulse Width
ChangeWidth
012A 1100
bclr
W1,PortA
SeLW1_SPI_Mode
jsr
012C CD0138

012F A611
0131 CD013D
0134 1000

SendCommands3
#17
Ida
Jsr
SPLxmit
DeselectW1_3
bset
W1,PortA

;select W1 (CE is active low)
;Setup the 68HC05 SPI control...
;to talk to the W1
;set pulse width to 38% duty cycle

;deselect the W1 which loads registers
;with values transmitted

Finis
0136 20FE

*

bra

6-78

;Ioop forever

CDP68HC68W1
.***.....*******.........****.................****.........*******..........

*

Common Subroutines

......*.............**.....................................***.............
Section Subroutines, *

0138
0138 A650
013A B70A
013C 81

SeLW1_SPLMode
Ida
#_SPE+_MSTR
sta
SPCR
rts

;Enable SPI as a Master with ...
;CPHA..CPOL=O,

SPLXmlt
013D B70C

sta

SPDR

;send A to SPI device

__SPIF, SPSR, SPLwait

;walt untU transmit complete

SPI_walt
013F OFOBFD
0142 81
0143 1000
0145 1004
0147 81

brelr
rts
Inltialize_W1
bset
bset
rts

W1,PortA
W1,DDRA

6-79

;disable the W1 (CE Is active low)
;byactlvatlng PAO as a high

APPLICATION NOTES
PAGE
AN-S601.1

CDP6SHC05C4 Monitor and Real-Time Controller . . . . . . . . . . . . . • . . . . . . . . • . . . . •• 7-3

AN-7200.1

Monitor ForThe CDP6S05G2 Microcomputer .•.......•....•.•••.....•••....••. 7-30

AN-S633.1

Versatile Serial Perlpherallnterface . . . . • . . • . . . . . . • • . . • • • • . . . . . . . • . . . . . . . . . . • •• 7-45

AN-S723.1

Interfacing Serial EEPROMs to CDP6S05 Microcomputers. . . • . . . . . . . . . . . . . . . . .. 7-53

AN-S759.1

Low Cost Data Acquisition System Features SPI AID Converter ........ . . . . • . . . .. 7-61

AN-7199.1

CDP6S05 CMOS Family Emulators.. •.. . .. . •. . .. . . . .. .. . .. • .. . . . . .• . . . . . . • . .. 7-70

AN-7197.1

Keyless Entry System Using The CDP6S05F2 S-Bit Microcomputer Unit ....••.... 7-79

AN-7364.1

CDP6805 Micros: Converting Interrupts. . . . . . . . . . . . . . . . . . . . . • . . . . . .. • . . . . . . . .. 7-S7

AN-S756.1

A Comparative Description of the UART - Universal. • . . . • . • •• . . . . . • . . . . . . . . . . . •• 7-91
Asynchronous Receiver/Transmitter

AN-S761.1

User's Guide to the CDP6SHC6ST1 Real-Time Clock

7-1

7-1 OS

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Harris Semiconductor

---------- ---

--

::::::='
-=.. -===
-=
-- ---- - ----

-

===

-

-

-

= ====

CDP68HC05C4 Monitor and
Real-Time Controller
The CDP68HC05C4 is a high-speed CMOS single-chip
microcomputer (MCU) containing on-chip RAM, ROM,
CPU; and I/O ports. Other advanced features include a
16-bit timer, a serial peripheral interface (SPI), and a serial
communications interface (SCI).
The ROM in the CDP68HC05C4 samples contains a monitor
routine that enables users to evaluate the device. Also
included is application software for producing a real-time
controller with a minimum hardware interface. The monitor
and real-time controller routines are discussed in detail in
this Application Note.
The CDP68HC05C4 is evaluated by use of a standard RS232 terminal. Registers and memory can be examined and
changed, and short programs can be entered and executed
out of RAM. Fig. 1 (a) shows the evaluation hardware.
Because the serial communications interface is used to
communicate with the terminal,' the SCI registers should
not be manipulated. A 500-kHz crystal is recommended for
optimum operation; a 500-kHz clock will generate 1200baud serial communication. Doubling the clock speed will
double the baud rate. Baud rates above 1200, however, are
not recommended without handshaking. The terminal
should also be set for full-duplex ASCII communication
with seven or eight data bits, one stop bit, no parity, and no
handshaking.
Short programs may be entered into theon-chip RAM and
executed by using the monitor. Any area of RAM from
location $0050 to $OOFF can be used for program storage
except for locations $OOBE to $00C1, which are used by the
monitor. Upper locations $OOCO to $OOFF, however, may be
needed for the user stack.

S - Display State of I/O
I - Information
These commands are described in detail below.
R - Display the Registers-The processor registers are
displayed as they appear on the ,stack. The format of the
register printout is:
HINZC AA XX PPPP
The first field shows the state of the condition-code register
bits. Each bit is identified by a single letter corresponding to
the bit name. If the letter is present, the bit is a logic 1. If a"."
is printed in place of the letter, that bit is a logic O. For
example, H .. ZC means that the H, Z, and C bits are logic 1's,
and the I and N bits are logic O's. The remainder of the line
shows the status of the accumulator, index register, and
program coun~er, respectively. The values shown are the
values loaded into the CPU when a C or E command is
executed. All register values except the condition-code
register can be changed with other commands.
A - Examine the Accum,ulator-This command prints the
current value of the accumulator and then waits for more
input. To change the current value, type in a new value (two
hexadecimal digits). To leave the accumulator unchanged,
type any non-hexadecimal character (a space is a good
choice).
X· Examine/Change the Index Register-The X is the same
as the A command, but affects the index register instead of
the accumulator.
M • Examine/Change Memory-Any memory location
(except ROM) may be examined or changed with the M
cOmmand. To begin, type M followed by a hexadecimal
address in the range $0000-$1FFF. The monitor responds
by beginning a new line and printing the memory address
followed by the current contents of that location. At this
pOint, the user may type:

MONITOR OPERATION
A description of the monitor operation is given in this
section. An assembled listing of the Monitor Routine is
included as Appendix A.

1. "." and re-examine the same byte. (Try this command
with location $0019.)
2. "1\" and go to the previous byte. Typing "/\" at location
$0000 causes the monitor to go to $1 FFF.
3. CR and go to the next byte. CR is the carriage-return
character. The byte after $1 FFF is $0000.
4. DD, where DD is a valid tWO-digit hexadecimal number.
This new data is stored at the current address; the
monitor then goes to the next location. To enter a
program, then, it is only necessary to go to the starting
address of the program and start typing in the bytes. To
see if the byte was really input, use the "1\" character to
return to the last byte typed in.
5. Any character other than those described above causes
the memory command to return to the prompt level ofthe
monitor and to print ".".

Commands
When the microcomputer is reset, a power-up message is
printed. Following the message, the prompt character ..... Is
printed, and the monitor waits fo~ a response. The response
may consist of single-letter c'ommands, with some commands requiring additional input. Unrecognized commands
are responded to by a printed "7". Valid commands are:
R - Display the Registers
A - Display/Change the 'Accumulator
i< - Display/Change the Index Register
M - Display/Change Memory
C - Continue Program Execution
E - Execute Program at Address

June 1986

AN-8601.1
7-3

Application Note AN-8601.1
C - Continue Program Execution-The C command merely
executes an RTI (Return from Interrupt) instruction: All of
the registers are reloaded exactly as they are shown in the
register display. Execution continues until the reset switch
is depressed or the processor executes an SWI (Software
Interrupt). Upon execution of an SWI, the monitor gains
control and prints the prompt character. This feature can be
used for an elementary form of breakpoints.

E - Start Execution at Address-The E com mand waits for a
valid memory address ($0020-$1 FFF) and places the address
typed !nto a temporary RAM location. The command then
executes a jump to the specified location.

Because there is no way for the monitor to know where the
stack pointer is after an SWI, the monitor assumes that the
pointer is at $OOFF. This location will not be correct if an
SWI is part of a subroutine. In this case, the monitor will be
re-entered, but the stack pointer will point to its valid
location. This condition is perfectly valid, and typing C will
pick up the program from where it left off. However, the A, X,
and R commands all assume that the stack starts at $OOFF
and will not function properly. If the stack location is
known, it is still possible to examine the registers by means
of the M command.

The data displayed is simply memory locations $0000$0002. Ports A, B, and C may be written to (changed)
regardless of whether they are an input or an output.
However, in order to display the change, they must all be
outputs. For example, to display the c.hange for port A,
change location $0004 (port A DDR) to $FF (otherwise, the
changed data cannot reach the RS-232 terminal). Port D
cannot be written to because it is an input-only port.

S- Display I/O States-The S command displays ports A, B,
C, and D data. The format olthe display is:
ABCD

I-Informatlon-The I command will dump a brief description
of the CDP68HC05C4 along· with a list of the monitor
commands.

+5
100 K
-L.

+S 1 MHz (2400 BAUD) FOR RTC
500 kHz (1200 BAUD) FOR MONITOR
CDP68HC05C4
1 RST
VDD 40
2 IRQ
OSC1 39
3 NC
OSC2 38
2
4 PA7
TCAP 37
4
5 PA6
PD7 36
6
6 PA5
PD6 35
PDS 34
7PA4
PD4 33
8 PA3
9 PA2
74~~ 13
PD3 32
15
10 PAl
PD2 31 MISO
17
2
3
3
11 PAO
PDl 30 TOO
1488
12 PBO
POO 29 RDl
1 RS232
D
13 PBl
PCO 28
B
-12 DRIVER
2
14 PB2
PC1 27
5
26
15 PB3
PC2
NOT USED
16 PB4
PC3 2S
KEYPAD
24 SEE FIG.l(d)
17 PBS
PC4
23
18 PB6
PC5
19 PB7
PC6 22
20 vss
PC7 21
-12
MALLORY SC628
SONALERT
TIE ALL UNUSED INPUTS TO +VDD OR Vss
I12CM-40l58!5

~~F
18
t6
14
12
9

SOCKET

PORT CONTROL
OUTPUT

7
S
3

-1CI

j:::CI)

$00
$00
TEMP

PRAM,X
#EOS
ODTIME
PUTC

..:w

PORT A

END OF 11SG·'
OIJTPUT CURRENT TIME TO LCD

PAM1

0SR
RT8

DTIME

BSET
JSR
LDA
JSR
0SR
CLRA
JSR

1. NOPRNT
CLEAR DISPLAY
CLR
#$DO
l.
DISPLY PRINT AN L
PUT OUT 4 BLANKS
BL4

DISPLY

7-13

11Ai'.E THAT 5 BLANKS

~z

0..

..:

Application Note AN-8601.1
041a
041d
041f
0421
0423
0424
0425
0426
0427
042a

cd
al
27
b7
48
48
48
97
cd
cc

06 40
0"
Oc
bO

04 32
04 09

JSR
CMP
BEQ
STA
LSLA
LSLA
LSLA
TAX
JSR
JMP

SALARM
SS

SCAN
#$OE
PTIME2
TEMP

GET INPUT
E FOR EX IT
SAVE BIT TO SET
11UL TIPLY BY EIGHT

042d 13 b8
042f cc 03 5d

PTIME2

BCLR
JMP

1, NOPRNT
ENABLE ALL PRINTS
PTIMEI TOO FAR TO BRANCH

0432
0434
0437
043a
043c
043"
0440
0442
0443
0444
0446

bf
cd
cd
b7
a6
b"
27
48
5a
27
cc

SAL ARM

STX
JSR
')SR
STA
LDA
LDX
BEQ
LSLA
DECX
BEQ
JMP

TEMPI
CU
SCAN
TEMP5
#$01
TEMP
SPRSET

0449
044c
044"
0450
0452
0455
0458
045b
045"
0460
0463
0466
0469

cd
b7
b"
a6
cd
cd
cd
cd
a6
cd
cd
cd
cd
a6
cd
cd
cd
cd
a6
cd
cd
cd
cd
81

046c
046e

0471
0474
0477
047a
047c
04H
0492
0485
0488

b1
02 5f
06 40
b5
01
bO
07

SHIFT2
03
04 42
07
00
bl
77
02
02
02
04

5b

SPRSET

bb
51
bb

8c

f4

02
02
02
04
d1
02
02
02
04
,,6
02
02
02
04

bb
51
bb
8c

JSR
STA
LDX
LDA
JSR
JSR
JSR
JSR
LDA
JSR
JSR
JSR
JSR
LDA

bb

JSH

51
bb
8c

,",SR

JSR
')SR
LDA
JSR
')SR
JSR
JSR
RTS

bb
51
bb
8c

BS
$00
TEMPI
#$77
DISPLY
BL4
DISPLY
SSETIM
#$F4
DISPLY
BL4
DISPLY
SSETIM
1+$Dl
DISPLY
BL4
DISPLY
SSETIM
#$E6
DISPLY
BL4
DISPLY
SSETIM

SGOBAK

JI1P

G013ACK

048c
048f
0491
0493
0495
0496
0497
0498
0499
049b
049"
04aO
04a2
04a4
04a5
04a8
04aa
04ab
04ac
04ad
04a"
04bO
04b3
04b5
04b7
04b9
04bb
04bc
04bf

SSETIM

JSR
CMP
BEQ
STA
LSLA
LSLA
LSLA
LSLA
STA
JSR
STA
ORA
STA
INCX
JSR
STA
LSLA
LSLA
LSLA
LSLA
STA
JSR
STA
ORA
STA
STX
CLRA
JSR
JSR

SCAN
#$OC
SGOBAK
TEMP

06 40
Oc
f6
bO

b4
06 40
bl
b4
55
06 40
b2

b4
06 40
b3
b4
55
b5
02 bb
02 bb

GET CURRENT STATE
SAVE IT
CONDITION ACC TO INDICATE BIT TO SET
GET VALUE OF BIT TO SET

SPRSET
SHIFT2

0489 cc 07 fO
cd
al
27
b7
48
48
48
48
b7
cd
b7
ba
,,7
5c
cd
b7
48
48
48
48
b7
cd
b7
ba
,,7
bf
4f
cd
cd

SAVE X

CONDITION ACC TO TOGGLE ONE BIT ONLY
SET B IT (OR NOT>
GET OFFSET
PRINT A
4 BLANKS
AND ANOTHER
SERIAL SET TIME
PRINT B
4 BLANKS
AND ANOTHER
SERIAL SET TIME
PRINT C
4 BLANKS
AND ANOTHER
SERIAL SET TI~IE
PRINT D
4 BLANKS
AND ANOTHER
SERIAL SET TIME

GET FIRST #
C FOR CONTINUE

TEMP4
SCAN
GET SECOND II
TEMPI
SAVE IT
TEMP4
BUILD HOURS
TTIMES, X
SCAN
TEMP2

GET THIRD II
SAVE IT

TEMP4
SCAN
GET LAST #
TEMP3
SAVE IT
TEMP4
BUILD MINS
TTIMES, X
TEMP5
SAVE X
DISPLY
DISPLY

7-14

OUTPUT A BLANK
OUTPUT A BLANK

Application Note AN-8601.1
04c2
04c4
04c7
04ca
04cc
04c~

04d2
04d4
04d7
04da
04dc
04de
04d1'
04e2
04,,4
04,,7
04,,9
04"b
04"c
04""
04fO
04f2
04f4

b"
db
cd
be
d6
cd
be
d6
cd
be
26

b3
02
02
b2
02
02
b1
02
02
bO
lc

LDX
LDA
JSR
LDX
LDA
JSR
LDX
LDA

c1
bb
c1
bb
c1
bb

.JSR

4~

cd
be
cd
al
26
5a
.. 6
aa
,,7
a6
cd
04~7 5c
04f8 5c
04~9 81

02 bb
b5
06 40

NONZ2

O~

18
55
80
55
73
02 bb

LDX
BNE
CLRA
JSR
LDX
JSR
CMP
BNE
DECX
LDA
ORA
STA

LDA
JSR

TEMP3
GET
CTABLE.X
DISPLY
TEMP2
GET
CTABLE.X
DISPLY
TEMPI
GET
CTABLE.X
DISPLY
TEMP
GET
NONZI
DISPLY
TEMP5
SCAN
II$OF
SAROND
TTIMES.
11$80
TTIMES.
11$73
DISPLY

TENS OF tllNS
HOURS
TENS OF HOURS

RESTORE X
GET AM OR PM
F FOR PI1
X
GET HOURS
SET MSB FOR PM
RESTORE HOURS
X
P

INeX
SGOON

INCX
RTS

04fa d6 02 cl
04~d cd 02 bb
0500 cc 04 ,,2

NONZI

LDA
JSR
JMP

CTABLE.X
DISPLY
NONZ2

0503 a6 77
0505 cd 02 bb
0508 cc 04 f8

SAROND

LDA
JSR
JMP

11$77
DISPLY
SGOON

050b
050c
050i'
0512
0513
0514
0515
0516
0518
051b
051d
05H
0522
0523
0524
0525
0526
0528
052b
052d
052f
0530
0532
0533
0536
0538
053a
053c
053"
0541

SINTIM

SEI
JSR
JSR
LSLA
LSLA
LSLA
L.SLA
STA
JSR
ORA
STA
JSR
LSLA
LSLA
LSLA
LSLA
STA
JSR
ORA
STA
CLRA
STA
CLI
JSR
CMP
BNE
CLR
BSET
JSR
RTS

9b
cd 02 43
cd 06 40
48
48
48

48
b7 53
cd 06 40
ba 53
~7 53
cd 06 40
48
48
48
48
b7 54
cd 06 40
ba 54
b7 54
4~

b7
9"
cd
al
;26
3f
1"
cd
81

MINS

52
06 40
O~

08
50
50
02 6d

0542 39 50
0544 cd 02 6d
0547 81

SAM

0548
0548 Oa Od
054a 46 52
55 53
54 48
43 52
50 55
43 41
4c 20
48 45
4c 44

MSQ

*
*

4f
54
45
4.
54
50
49
20

4d
49
20
43
45
49
46
57

20
4"
4d
4f
52
54
20
49

41
2c
49
4d
20
41
54
52

CLR
JSR
RTS
EOU
FCB
FCC

PR
SCAN

HRS
SCAN
HRS
HRS
SCAN

MINS
SCAN
MINS
MINS

A

GET FIRST II

GET SECOND II
BUILD HOURS
GET THIRD II

GET LAST II
BUILD MINS
Z

0

i=f3

SECS
SCAN
II$OF
SAM
APM
7.APM
DTIME
APM
DTIME

*

GET AM OR PM
F FOR PM
SET PM

SET AM

$OA ••OD
IFROM AUSTIN. THE MICROCOMPUTER CAPITAL OF THE WORLD I

7-15

~:;
~z

a..

c:

Application Note AN-860 1. 1
057e Os Od
057f 20 20
20 20
54 48
48 43
20 44
05ge Oa Od
059f 54 4f
20 54
45 4"
54
05b2 Od Oa
05b4 54 4f
20 43
4f 4e
45 53
45 52
05dO Od Oa
05d2 46 4f
4d 20
54 4f
54 45
05e9 00
05es Od Os
OSee 53 49
47 20
41 54
05fe 00

Os
20
20
45
30
45
Os
20
49
54

20
20
20
35
4d

20
20
36
43
4f

20
20
38
34

53 45 54
4d 45 2<
45 52 20

20
4f
20
2e
20

53
4e
54
45
53

45
54
49
4e

54
52
4d
54

52
4d
52
52

20
4f
2e
20

52 4f
4e 49
45 4.
4d
TIME

47 4e 49 4e
4f 46 46 20
2d 20

05fd
05fd Od Os 00
0600
06000d
0602 45
4e
4d
48
06la 00

INT
Oa
4e
45
45
48

061b Od Oa
061d 41 4d
50 4d
45 4e
41 20
29 20
0637 00
0638
063b
063e
063f

LFEED

54
57
20
4d

45
20
41
4d

52
54
53
20

20
49
20
20
AMPM

20
20
54
4f

20 41 4d
00
20 50 4d
00

4f
3f
45
52

52
20
52
20

20
28
20
50

PRAM
PRPM

FCB
FCC

SOA. SOD. SOA

FCB
FCr.

SOA. $00. SOA
ITO SET TIME. ENTER TI

FCB
FCC

SOD.SOA
ITO SET CONTROL TIMES. ENTER 51

FCB
FCC

SOD.SOA
IFOR ROM MONITOR. ENTER MI

FCB
FCB
FCC

SOO
SOD.SOA
ISIGNING OFF AT- I

FCB

$00

EGU
FCB

*

THE 68HC05C4 DEMOI

I

SOD. SOA. SOO

*

EGU
FCB
FCC

SOD.SOA
IENTER NEW TIME AS HHMM

FCB

$00

FCB
FCC

SOD.SOA
lAM OR PM ? (ENTER A OR P) I

FCB

SOO

FCC
FCB
FCC
FCB

I AMI
SOO

I

I

PI11

SOO

*
**.;I-':'***"*****':f**********':l-1I*******1I-********.;I-******iI·;t*******if-****itit.. *******·)t
**
SCAN - SCAN THE. ENTIRE KEYPAD ONCE AND RETURN (IN A) THE NUMBER
*
OF THE KEY THAT WAS HIT. THIS ROUTINE USES A NEGATIVE
*
KEYBOARD SCAN. WITH A COLUMN BEING SELECTED BY A 0 IN PORTC.
*
IN PORTC. BITS 0-3 ARE ROW INPUTS. BITS 4-7 ARE COLUMN

*

OUTPUTS.

*

*****·.. ***if****** ..... ***********.. ***iI·,... *******·...**** ... *** .. ***********.. *******.;t

0002

OOaO
OOal
00a2

*PORTC EGU
** STORAGE FOR
*
COL
DELYHI
DELYLO

EGU
EGU
EGU

S02

ADDRESS OF PORTC

RAM VARIABLES
SAO
I'.EYPAD COLUMN COUNTER
COL+l
COUNTER USED FOR DEBOUNCING KEYS (HI BYTE)
DELYHI+l
LOW BYTE

*

*
*,.*******.;1-*
it·Jt·lt-*,* "-"**"'-11-.*** ** ...... it" .... *******iI *****.,. ,**,»***********-:t*********

0640 a6 Of
0642 b7 02
0644 bf a3

*
** FIRSt CHECK
*
SCAN
LOA
STA

STX

THAT ALL

~.EYS

*X00001111
PORTC
COL+3

7-16

HAVE BEEN. RELEASED
ACTIVATE ALL COLUMNS
SAVE X

Application Note AN-8601.1
0646
0648
064a
064c
064e

0650
0652
0654
0656
0658
0659
065b
065d

10
b6
a4
al
26

a6
b7
3f
b6
97
a4
al
27

b8
02

KEYREL

O~

Of
f8

* START SCAN
*
*
SCANl
LDA

ef
02
aO
02

STA

Of
Of
lb

ff

CNTDWN

a2
a2
fa

al
al
f4

**
*

0688
068a
068c
068d
068e
0690
0691
0692

3c
a6
bl
27
38
18
20

LDA
STA
LDA
STA
LDA
DEC
CMP
BNE
DEC
CMP
BNE

LP5

0693 5c

0694 20 f7

II$OF
II$OF
NOKEY

11$11
DELYHI
II$BO
DELYLO
II$FF
DELYLO
DELYLO
CNTDWN
DELYHI
DELYHI
CNTDWN

PORTC
KEYHIT

INC
LDA
CMP
BEG
LSL
BSET
BRA

COL
114
COL
SCANl
PORTC
4.PORTC
LP2

ADD
CLRX
LSRA
BCC
INCX
INCX
INCX
INCX
BRA

*
* CHECK THAT
*CHECK AND

0696 a4 Of
0698 al Of
069a 26 a4

11%11101111
PORTC
COL
PORTC

TXA
CMP
BEG

** DETERMINE
*KEYHIT AND

a4 Of
ab fO
5f
44
24 06
5c
5c
5c

OF KEYPAD
ACTIVATE COLUMN 1
INITIALIZE COL COUNTER TO 0
CHECK KEYS IN THIS COLUMN
SAVE INITIAL READING
CHECK INPUT PINS
IF NO KEY PRESSED.
... BRANCH

SET UP COUNTER HIGH BYTE
SET UP LOW BYTE
COUNTDOWN TO $FF BEFORE DECREMENTING HIGH BYTE
HIGH BYTE = $FF?
IF NOT. CONTINUE COUNTDOWN

CHECK KEYPAD AGAIN

*
*NOKEY

aO
04
aO
ce
02
02
ce

DISABLE PRINT TO TERMINAL
NOW CHECK ROWS
CLEAR OUT COLUMN INFO
ALL ROWS CLEAR?
IF NOT LOOP UNTIL THEY ARE

DEB OUNCE KEY FOR ABOUT lOOMS (ASSUMING A 1 MHl OSCILLATOR FREGUENCY;
PHASE 2 FREGUENCY = 500KHZ)

*

11
al
bO
a2

06'75 9f
0676 bl 02
0678 27 Oe
067a
067c
067.,
0680
0682
0684
0686

CLR
LDA
TAX
AND
CMP
BEG

LP2

*
*
*
065f a6
0661 b7
0663 a6
0665 b7
0667 a6
0669 3a
066b bl
066d 26
066f 3a
0671·bl
0673 26

O.NOPRNT
PORTC
II$OF
II$OF
KEYREL

BSET
LDA
AND
CMP
BNE

CMP
BNE

GET INITIAL READING BACK
COMPARE WITH CURRENT KEYPAD CONDITION
IF THE SAME (VALID KEYSTROKE) COMPUTE KEY
ELSE IGNORE AND CONTINUE SCAN
INC COL COUNT
FINISHED SCAN?
IF FINISHED START SCANNING FROM FIRST COLUMN AGAIN
IF NOT. ACTIVATE NEXT COLUMN AND SCAN AGAIN
SET IN CASE A ZERO WAS SHIFTED INTO UPPER NIBBLE
CONTINUE SCAN

WHICH KEY WAS PUSHED
II$OF
II$FO
CHECK

LP5

CLEAR UPPER NIBBLE. SAVE LOWER NIBBLE
SET UPPER NIBBLE TO ALL l'S
SET TO CHECK 1ST ROW OF KEYPAD
ROTATE LSB INTO CARRY BIT
IF ROW IS FOUND. CHECK FOR ONE KEY PUSHED
MOVE TO NEXT ROW ON KEYPAD

CONTINUE ROW CHECK

ONLY ONE KEY WAS INITIALI_Y PUSHED.
II$OF
II$OF
SCAN

CLEAR OUT UPPER NIBBLE
LOWER NIBBLE SHOULD BE ALL l'S AT THIS POINT
IF NOT THEN BAD KEYSTROKE. START SCAN OVER

*

069c
069d
069f
06aO
06a3
06a6
06a8

9F
bb
97
d6
cd
be
81

06a9
06ad
06bl
06b5

01
04
07
00

*
aO
06 a9
01 ae
a3

TXA
ADD
TAX
LDA
.J5R
LDX
RTS

COMPUTE KEY NUMBER
PUT NUMBER BACK IN X FOR USE AS OFFSET
KEYPAD. X
GET KEY FROM TABLE
BEL
COL+3
RESTORE X

FCB
FCB
FCB
FCB

1.
4.
7.
O.

COL

*
02
05
08
Of

03
06
09
Oe

Oa
Ob
Oc
Od

*KEYPAD

5.
8.

3.
6.
9.

II$F.

II$E.

2.

*

7-17

II$A
II$B
II$C
II$D

Application Note AN-860 1. 1
06b9 Oa Od
06bb 45 4"
4< 49
30 2d
52 20
20 44
20 45
06df 00
06eO
06e2
06e3
06e6
06e9
06ea
06ed
06ef
06fl
06f4
06f6
06fB
06fa
06fc
06fd
06fe
06ff
0700
0703
0706
0709
070b
070e
0710
0712
0714

12
5f
d6
cd
5c
d6
al
26
cd
al
27
a4
b7
4B
4B
4B
97
cd
cc
cd
13
cd
a6
b7

MSGI
54
4"
37
43
20
58

20
2B
4f
4c
4f
29

bB

S

06 b9
09 e5

OUT2

06 b9
00
f5
09 d7
04
Oe
Of
bO

07
06
09
bB
03
2c
Of
10 bB
BO

0715 Oa Od
0717 43 55
54 20
45 3f
4f 52
072" 00

2f
eO
91

RETURN

5d

MSG2
52
53
20
20

072f
0731
0733
0736
0737
073a
073d
073e
0741
0743

bf
b7
cd
5f
d6
cd
5c
d6
al
26

bl
b2
02 5f

0745
0746
074a
074c
074"
0750

10 fd
11
Of
b5
01
bO
12

0754
0755
0756
075B

Ob
b6
a4
b7
a6
be
27
46
5a
27
cc

075b
075d
075f
0761
0762
0763
0765

b"
27
ba
61
43
b4
Bl

b5
03
00

0766
0769
076b
076d
0770
0772
0775
0776

cd
b7
b"
cd
a6
cd
cd
cd

07
00
b1
09
61
09
07
09

0752

45 52
45 20
29 20
54 52
2B 54
49 54

07 15
09 .,5

52
54
2B
31

45 4e
41 54
30 20
29
ALARM

OUT3

07 15
00
f5

SHIFT!
Oe
07 54
BS

COM AND
00
5b
91
"S
9a
91

PRSET

FCB
FCC

$OA.$OD
/ENTER LINE (0-7) OR CTRL D (TO EXIT)/

FCB

$00

BSET
CLRX
LDA
JSR
INCX
LDA
CMP
BNE
JSR
CMP
BEG
AND
STA
LSLA
LSLA
LSLA
TAX
JSR
JMP
JSR
BCUl
JSR
LDA
STA
BSET
RTI

1. NOPRNT
MSGI. X
PUTC
MSGI. X
#$00
OUT2
GETC
#$04
RETURN
#$OF
TEMP

OUTPUT THE MESSAGE

EOS?
CTRL D?
TAKE OFF HIGH NIBBLE
SAVE FOR POSTERITY
OK. NOW 11ULTIPLY
BY EIGHT

SET UP OFFSET
ALARM
S
CRLF
1. NOPRNT
PTiMEI
#$2C
$OF
ENABLE RCVR INT
O.NOPRNT
DISABLE TERMINAL DISPLAY

FCB
FCC

$OA.$OD
/CURRENT STATE? (0 OR 1)/

FCIl

$00

STX
STA
JSR
CLRX
LDA
JSR
INCX
LDA
CMP
BNE

TEMPI
TEMP2
CU

SAVE X
SAVE A

MSG2. :<
PUTC
MSG21 X

#$000
OUT3

BRCLR
LDA
AND
STA
LDA
LDX
BEG
LSLA
DECX
BEG
JMP

S. $10.
$11
#$OF
TEMP5
#$01
TEMP
PRSET

LDX
BEQ
ORA
RTS
COMA
AND
RTS

TEMP5
COMAND
$00

JSR
STA
LDX
JSR
LDA
JSR
JSR
JSR

BS
$00
TEMPI
CRLF
#$61
PUTC
SETIME
CRLF

*

WAIT FOR RDRF
GET INPUT
11ASK HIGH BYTE
SAVE CURRENT STATE
SET UP ACC TO INDICATE BIT TO SET
GET VALUE OF BIT TO SET

PRSET
SHIFT!

$00

7-18

FETCH AND TEST CURRENT STATE
IF ZERO. BRANCH
IF ONE. OR IT WITH PORTA
AND RETURN
COM ACC TO PRESERVE EXISTING BITS
ON PORTA
CmmITION ACC TO TOGGLE ONE BIT ONLY
SET THE BIT ON PORT A
RESTORE X
PRINT A

Application Note AN-8601.1
077b
077d
0780
0783
0786
0788
078b
078 ..
0791
0793
0796
0799

a6
cd
cd
cd
a6
cd
cd
cd
a6
cd
cd
81

62
09
07
09
63
09
07
09
64
09
07

079a
079d
07aO
07a2
07a4
07a5
07a6
07a7
07a8
07aa
07ad
07af
07b1
07b3
07b4
07b7
07b8
07b9
07ba
07bb
07bd
07cO
07c2
07c4
07c6
07c8
07c9
07cc
07cf
07dO
07d3
07d5

cd
cd
a1
27
48
48
48
48
b7
cd
a4
ba
.. 7
5c
cd
48
48
48
48
b7
cd
a4
ba
.. 7
bf
5f
d6
cd
5c
d6
a1
26

09 91
09 d7
Od
4c

07d7
07d9
07dc
07d.,
07.,0
07.,1
07.,3
07.,5
07.,7
07.,8
07.,9

b ..
cd
a1
26
5a
.,6
aa
.,7
5c
5c
81

07ea
07.,c
07.,.,
07.,f

a1 41
26 d8
5c
81

07fO
07f1
07-1'3
07-1'4
07f6
07f7

43
.,,7 55
5c
,,7 55
5c
81

LOA
JSR
JSR
JSR
LOA
JSR
JSR
JSR
LOA
JSR
JSR
RTS

#$62
PUTC
SETIME
CRLF
#$63
PUTC
SETIME
CRLF
11$64
PUTC
SETIME

JSR
JSR
CMP
BEG
LSLA
LSLA
LSLA
LSLA
STA
JSR
AND
ORA
5TA
INCX
JSR
LSLA
LSLA
LSLA
LSLA
STA
J5R
AND
ORA
STA
STX
CLRX
LOA
JSR
INCX
LOA
CMP
BNE

CRLF
GETC
IICR
GOBACK

LOX
JSR
CMP
BNE
DECX
LOA
ORA
STA
INCX
INCX
RTS

TEMP
GETC
II'P
AROUND

AROUND

CMP
BNE
INCX
RTS

#'A
AGN

GOBACK

COMA
STA
INCX
STA
INCX
RTS

.. 5
9a
91

.. 5
9a
91
.. 5
9a
SETIME

bO
09 d7
Of
bO
55
09 d7

bO
09 d7
Of
bO
55
bO

AGN

06 1b
09 .. 5

Dun

06 lb
00
f5
bO
09 d7
50
Oa
55
80
55

7-19

PRINT B

PRINT C

PRINT 0

INDEX REGISTER HAS OFFSET

TEMP
GETC
#$OF
TEMP
BUILD HOURS BYTE
TTIMES.X
GETC

TEMP
GETC
#$OF
TEMP
BUILD MINUITS
TTIMES. X
TEMP
SAVE X
AMPM.X
PUTC
AMPM. X
#$00
OUT1

OUTPUT

AM OR PM?

EOS?
RESTORE X
GET ANSWER

TTIMES. X
#$80
sn HIGHEST BIT
TTIMES.X
INDICATES PM

Z
0

~ffi

y ......
-0

~z

TTIMES.X
TTIMES. X

a..

C

THIS PUTS $F2 IN
AS A NO TIME
INDICATOR

Application Note AN-860t.t
*********-It·lt*·:t**"*"'**~**·lt******·;to*iI*·'lt·"*****iI*·"*"'** ***************************·:t-it**

*

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

ROM

OOOd
002e
OOOd
005e
002e
OOOa
0020
0000
OOH
OOfa

00b9
OObe
00c2
00c3
00c4
00c5

0000
0001
0003
0004

*
*LF
BL
EOS
*
INITSP
STACK
*
*
*
RAM
GET
ATEMP
XTEMP
CHAR
COUNT
*
*
*

*
PORTA

A --

PRINT/CHANGE A ACCUMULATOR.
PRINTS THE REGISTER VALUE, THEN
WAITS FOR NEW VAI,.UE.
TYPE
ANY NON-HEX CHARACTER TO EXIT.

X

PRINT/CHANGE X ACCUMULATOR.
WORKS THE SAME AS 'A'. EXCEPT MODIFIES X INSTEAD.

M --

MEMORY EXAI1INE/CHANGE.
TYPE M AAA TO BEGIN.
THEN TYPE:
TO RE-EXAMINE CURRENT
-- TO EXAMINE PREVIOUS
CR -- TO EXAMINE NEXT
DD -- NEW DATA
ANYTHING ELSE EXITS MEMORY COMMAND.

C --

CONTINUE PROGRAM.
EXECUTION STARTS AT
THE LOCATION SPECIFIED IN THE PROGRAM
COUNTER. AND
CONTINUES UNTIL AN SWI IS EXECUTED
OR UNTIL RESET.

E

EXECUTE FROI~ ADDRESS.
FORMAT IS
E AAAA.
AAAA IS ANY VALID MEMORY ADDRESS.

S --

DISPLAY MACHINE STATE.
DISPLAYED.

EQU
EQU
EQU
EQU
EQU

$OD

CARRIAGE RETURN
PROMPT CHARACTER
GO TO NEXT BYTE
GO TO PREVIOUS BYTE
RE-EXAMINE SAME BYTE

CR

CHARACTER CONSTANTS
EQU
$OA
LINE FEED
EQU
$20
BLANK
EQU
$00
END OF STRING
EQU
EQU

$FF
INITIAL STACK POINTER VALUE
INITSP-5 TOP Or STACK

RAM VARIABLES
EQU
EQU
EQU
EQU
EQU
EQU

NOPRNT+l START OF TEMPORARY STORAGE
RAM+5
4-BYTE NO-MANS LAND. SEE PICK AND DROP SUBROUTINES
RAM+9
ACCA TEMP FOR GETC,PUTC
RAM+l0 X REG. TEMP FOR GETC.PUTC
RAM+ll CURRENT INPUT/OUTPUT CHARACTER
RAM+12 NUMBER OF BITS LEFT TO GET/SEND

I/O REGISTER ADDRESSES

PORTS
*PORTC
PORTD
DDR

*
*

STATE --- PRINT MACHINE STATE

*

*
*
*

ALL IMPORTANT REGISTERS ARE

SPECIAL EQUATES

EQU
EQU
EQU
EQU
EQU

*
*

6 8 H C 0 5 C 4

PRINT REGISTERS.
FORMAT IS CCCCC AA XX PPP

*

*
*
*
*
*
*
*
*
*
*
*
*
CR
PROMPT
FWD
BACKB
SAME

FOR THE

R

.*
*
*
*
*
*
*
*

M 0 NIT 0 R

THE MONITOR HAS THE FOLLOWING COMMANDS:

$000
$001
$002
$003
4

I/O PORT 0
1/0 PORT 1
1/0 PORT 2
1/0 PORT 3
DATA DIRECTION REGISTER OFFSET

ABC D
DD DD DD DD
HEADER STRING FOR I/O REGISTER DISPLAY

7-20

Application Note AN-860 1.1
071'8 Od Oa
07fa 20 41 20 20 42 20
20 43 20 20 44 20
0806 Od Oa 00
0809
080a
080d
0801'
0811
0814
0815

0817
0818
0819
081c
08lf
0820
0822

51'
d6
al
27
cd
5c
20

51'
1'6
cd
cd
5c
a3
26

*STATE
07 1'8
00
06
09 .. 5

*
*
*
STATE3
PIO
09 72
09 91'
04
1'4

0829 48 49 4e 5a 43
b6
48
48
48
b7
51'
a6
38
24
d6
cd
5c
a3
25
81

fb

2 ..
be
03
08 29
09 .. 5

085d
0851'
0862
0864
0866
0868
086b
086e

n

*
*
*
*
*CCSTR
*
PCC

PCC2

PCC3

05
.. 1'

*
*
*
SETA
*
*
*
SETX
*
*
*SETANY

084c ae 1'd

1'6
cd
cd
cd
25

*

be

0848 a .. 1'c
084a 20 02

084e
0841'
0852
0855
0858
085a
085b

STATE2

1'3

0824 cd 09 91'
0827 20 48

082 ..
0830
0831
0832
0833
0835
0836
0838
083a
083c
0831'
0842
0843
0845
0847

IOMSG

09 72
09 9"
09 a8
17

20 14

ad
cd
31'
a6
b7
cd
cd
cd

cf
09
bf
1'c
cO
09
09
09

*
*
*REGS
9"

FCB
FCC

CR,LF
/ A B

FCB

CR,LF,EOS

CLRX
LDA
CMP
BEQ
JSR
INCX
BRA

GET NEXT CHAR
QUIT?
YES, NOW PRINT VALUES
NO, PRINT CHAR
BUI1P POINTER
DO IT AGAIN

,X
PUTBYT
PUTS

START WITH I/O PORTS

114
PIO

END OF I/O?
1110, DO MORE

JSR
BRA

PUTS
MONIT

PCC

PRINT CONDITION CODES

ALL DONE

STRING FOR PCC SUBROUTINE
FCC

/HINZC/

LDA
ASLA
ASLA
ASLA
STA
CLRX
LDA
ASL
BCC
LDA
JSR
INCX
CPX
BLO
RTS

STACK+l CONDITION CODES IN ACCA
MOVE H BIT TO BIT 7
GET

SAVE IT

11'.
PUT BIT IN C
GET
BIT OFF MEANS PRINT
PCC3
CCSTR, X PICKUP APPROPRIATE CHARACTER
PRINT
OR CHARACTER
PUTC
POINT TO NEXT IN STRING
QUIT AFTER PRINTING ALL 5 BITS
115
PCC2

SETA

EXAMINE/CHANGE ACCUMULATOR A

LDX
BRA

IISTACK+2 POINT TO A
SETANY

SETX

EXAMINE/CHANGE ACCUMULATOR X

LDX

Z

IISTACK+3 POINT TOX

C)

SETANY --- PRINT (X) AND CHANGE IF NECESSARY
LDA
JSR
JSR
JSR
BCS
STA
BRA
REGS
BSR
JSR
LDA
STA
JSR
JSR
JSR

*
*
*
*
*

STATE2

D /

NOW PRINT VALUES UNDERNEATH THE HEADER
CLRX
LDA
JSR
JSR
INCX
CPX
BNE

CLR

5F
51'
57

IOMSG,X
IIEOS
STATE3
PUTC

C

,X
PUTBYT
PUTS
GETBYT
MONIT
, X
MONIT

PICK UP THE DATA,
PRINT IT

AND

SEE IF IT SHOULD BE CHANGEu
ERROR, NO CHANGE
ELSE REPLACE WITH NEW VALUE
NOW RETURN

PRINT CPU REGISTERS
PCC
PRINT CC REGISTER
PUTS
SEPARATE FROM NEXT STUFF
GET+i
POlNT ro PAGE ZERO,
lISTACK+2
GET+2
OUT2HS CONTINUE PRINT WITH A
OUT2HS X AND FINALLY THE
OUT4HS PROGRAM COUNTER

FALL INTO MAIN LOOP
MONIT --- PRINT PROMPT AND DECODE COMMANDS

7-21

i=~

~~
~z

a..

cC

Application Note AN-860 1.1
0871
0874
0876
0879
087c
087"
0881
0883
0885
0887
0889
088b
088d
088P
0891
0893
0895
0897
0899
089b
089d
089f
OBal

cd
036
cd
cd
034
cd
al
27
031
27
031
27
031
27
031
27
al
27
031
27
al
26
cc

09 91
2"
09 ,,5
09 d7

MONIT

7f

09 9P
41
c3
58
c3
52
dO
45
la
43
2b
4d
28
49
M

53
03
08 09

OBa4
08034 036 3P
08036 cd 09 ,,5
08039 20 c6

*MONIT2

09 aB
c1

08cl
08e4
08e6
08e8
08eb
08ed
08cf
08d2
OBd4
08d6
08d9
08db
08d"
08,,1
08,,3
08,,6
08 .. 9
08"e
08""
08fO
08f2
08f4
08f6
08f8
08fa
08fe
08f"
0900
0902
0904
0906
0908
09003

cd
25
b7
cd
25
b7
cd
b6
034
cd
b6
cd
cd
ad
cd
cd
cd
25
ad
ad
20
031
27
al
27
031
26
303
b6
031
26
303
20

09 a8
ab
bf
09 038
034
cO
09 91
bf

*#'?

JSR

PUTC
MONIT

NONE OF THE ABOVE
LOOP AROUND

*
EXEC

JSR
BCS
TAX
JSR
BCS
STA
STX
LDA
STA
JMP

*

*
*
*CONT
*
*
*MEMORY

MEM2

if

09
cO
09
09
57
09
09
09
06
50
5"
db
2"
d7
Od
f4
5"
37
cO
cO
H
c7
bf
c3

EGU
LDA

EXEC --- EXECUTE FROM GIl/EN ADDRESS

09 038
bb
b2
bl
cc
bO
bO

08cO 80

GO TO NEXT LINE
CRLF
IIPROMPT
PUTC
PRINT THE PROMPT
GETC
GET THE COMMAND CHARACTER
117.1111111 MASK PARITY
PUTS
PRINT SPACE (WON'T DESTROY A)
II'A
CHANGE A
SETA
II'X
CHANGE X
SETX
II'R
RECISTERS
REGS
II'E
EXECUTE
EXEC
II'C
CONTINUE
CONT
II'M
14EMORY
MEMORY
11'1
INFORM"TION
INFO
DISPLAY MACHINE STATE
II'S
MONIT2
COi1MANDS ARE GETT I NG TOO FAR AWAY
STATE

BRA

*

08ab cd
08ae 25
OBbO 97
08bl cd
OBb4 25
OBb6 b7
OBb8 bf
08ba a6
08bc b7
08b" bc

JSR
LOA
JSR
JSR
AND
JSR
CMP
BEG
CMP
BEG
CMP
BEG
CMP
BEG
CMP
BEG
CMP
BEG
CMP
BEG
CMP
BNE
JMP

72
72
9f
72
9f
038
MEM4
MEM3

CONT

GETBYT
MONIT
GETBYT
MONIT
TEMP2
TEMP!
#$CC
TEMP
TEMP

CONTINUE USERS PROGRAM

RTI
MEMORY
JSR
BCS
STA
JSR
BCS
STA
JSR~

LDA
AND
JSR
LDA
JSR
JSR
BSR
JSR
JSR
JSR
BCS
BSR
BSR
BRA
CMP
BEG
CMP
BEG
CMP
BNE
DEC
LDA
CMP
BNE
DEC
BRA

GET HIGH NYBBLE
BAD DIGIT
SAVE FOR A SECOND
NOW THE LOW BYTE
BAD ADDRESS
PROGRAM COUNTER LOW
PROGRAI1 COUNTER HIGH
'JUMP'

SIMPLE ENOUGH
MEMORY EXAMINE/CHANGE
GETBYT
MONIT
GET+l
GETBYT
MONIT
GET+2
CRLF
GET+l
1I$IF
PUTBYT
GET+2
PUTBYT
PUTS
PICK
PUTBYT
PUTS
GETBYT
MEM3
DROP
BUMP
MEM2
"SAME
MEM2
IIFWD
MEM4
IIBACKB
XMONIT
GET+2
GET+2
II$FF
MEM2
GET+l
MEM2

7-22

BUILD ADDRESS
BAD HEX CHARACTER
BAD HEX CHARACTER
ADDRESS IS NOW IN GET+l&2
BEGIN NEW LINE
PRINT CURRENT LOCATION
MASK UPPER 3 BITS (8K MAP)

A BLANK, THEN
GET THAT BYTE
AND PRINT IT
ANOTHER BLANK.
TRY TO GET A BYTE
MICHT BE A SPECIAL CHARACTER
OTHERWISE, PUT IT AND CONTINUE
GO TO NEXT ADDRESS
AND REPEAT
RE-EXAMINE SAME?
YES. RETURN WITHOUT BUMPING
GO TO NEXT?
YES. BUMP THEN LOOP
GO BAC~. ONE BYTE?
NO, EXIT MEMORY COMMAND
DECREMENT LOW BYTE
CHECK FOR UNDERFLOW
NO UNDERFLOW

Application Note AN-8601.1
090c
090d
0910
0912
0915
0916
0918

5'
d6
27
cd
5c
27
cc

091b
091 ..
0920
0923
0924
0926
0929
092c
092e
0931
0932
0934

d6
27
cd
5c
27
cc
d6
27
cd
5c
27
cc

Oc 4b
25
09 .. 5

INFO
INF01

03
09 Od
Od 4b
17
09 e5
03
09 1b
Oe 4b
09
09 e5

INF02

INF03

03
09 29

0937 cc 08 71

093a bf c3
093c ae d6
093e 20 04

**
*XMONIT
**
**
*
*
**
*
*
*PICK
*
**
*
*
*
*

*

0940 bi' c3
0942 a.. d7
0944
0946
0948
094a
094b
094d
094f

0950
0952
0954
0956

0957
0959
095b
095d

bf
a..
bf
5f
bd
be
81

be
81
c1

*DROP
*
*COMMON

ad .. 1
a4 i f
ad 15
ad f1

BUMP2

INF02
INF01

DO NEXT PAGE

DUMP+$100, x GET CHARACTER
XMONIT IF OO,RETURN
PUTC
OUTPUT CHAR
INF03
DO NEXT PAGE
INF02
DUMP+$200,X GET CHARACTER
XMONIT IF OO,RETURN
PUTC
OUTPUT CHAR
XMONIT
INF03

END OF DUMP SO RETURN

CONVENIENT TRANSFER POINT BACK TO MONIT
JMP

MONIT

RETURN TO MONIT

UTILITIES
PICK --- GET BYTE FROM ANiWHERE IN MEMORY
THIS IS A HORRIBLE ROUTINE (NOT MERELY
SELF-MODIFYING, BUT SELF-CREATING)
OET+1~2 POINT TO ADDRESS TO READ,
BYTE IS RETURNED IN A
X IS UNCHANGED AT EXIT

STX
LDX
BRA

XTEMP
*$D6
COMMON

SAVE X
D6=LDA 2-BYTE INDEXED

DROP --- PUT BYTE TO ANY MEMORY LOCATION.
HAS THE SAME UNDESIRABLE PROPERTIES
AS PICK
A HAS BYTE TO STORE, AND· GET+1~2 POINTS
TO LOCATION TO STORE
A AND X UNCHANGED AT EXIT
STX
LDX

XTEMP
*$D7

SAVE X
D7=STA 2-BYTE INDEXED

STX
LDX

GET
*"'81
GET+3

PUT OPCODE IN PLACE
81=RTS
I\;OW THE RETURN
WE WANT ZERO OFFSET
EXECUTE THIS MESS
RESTORE X
ANI) EXIT

CLRX
JSR
LDX
RTS

*
*
**
*BUMP

DUMP, X GET CHARACTER
XMONIT IF OO,RETURN
PUTC
OUTPUT CHAR

LDA
BEG
JSR
INCX
BEG
JMP
LDA
BEG
JSR
INCX
BEG
JMP

STX

be
c3

3c cO
26 02
3c bf
81

CLRX
LDA
BEG
JSR
INCX
BEG
JMP

GET
XTEI1P

BUMP --- ADD ONE TO CURRENT MEMORY POINTER
A AND X UNCHANGED
INC
BNE
INC
RTS

GET+2
BUMP2
GET+l

INCREMENT LOW BYTE
NON-ZERO MEANS NO CARRY
INCREMENT HIGH NYBBLE

*
**
*
*OUT4HS

OUT4HS --- PRINT WORD POINTED TO AS AN ADDRESS, BUMP POINTER
X IS UNCHANGED AT EXIT

*
*

OUT2HS

*
*

BSR
AND
BSR
BSR

PICK
*$1F
PUTBYT
BUMP

GET HIGH NYBBLE
MASK HIGH BITS
AND PRINT IT
GO TO NEXT ADDRESS

PRINT BYTE POINTED TO, THEN A SPACE. BUMP POINTER
X IS UNCHANGED AT EXIT

7-23

Application Note AN-860 1. 1
ad
b7
44
44
44
44
ad
b6
ad
ad
096~ ad
0971 81
095~

0961
0963
0964
0965
0966
0967
0969
096b
096d

d9
be

OUT2HS

16
be
12
.. 1
2 ..

**
*
0972
0974
0975
0976
0977
0978
097a
097c
097"

097~

0981
0983
0985
0987
0989
098b
098"
0990

0991
0993
0995
0998
099a
099c
099"

099~

09a1
09a3
09a5
09a7

09a8
09aa
09ac
09ad
09ae
09a~

09bO
09b2
09b4
09b6
09b8

b7
44
44
44
44
ad
b6
ad
81

b7
a4
ab
a1
23
ab
cd
b6
81

b7
a6
cd
a6
ad
b6
81

b7
a6
ad
b6
81

ad
25
48
48
48
48
b7
ad
25
bb
81

b"

*PUTBYT

05
b"
01

c1
Of
30
39
02
07
09 ,,5
c1

b"
Od
09 ,,5
Oa
49
be

be
20
40
be

Of
Oc

**
*
*
*PUTNYB

PUTNY2

**
*
*CRlF

BSR
STA
LSRA
LSRA
LSRA
LSRA
BSR
LDA
BSR
BSR
BSR
RTS

STA
LSRA
LSRA
LSRA
LSRA
BSR
LDA
BSR
RTS

STA
AND
ADD
CMP
BLS
ADD
JSR
LDA
RTS

STA
LDA

NOBYT

GET

SAVE A

PUTNYB
GET
PUTNYB

SHIFT HIGH NYBBLE DOWN
PRINT IT
PRINT LOW NYBBlE

GET+3
#$F
#'0

SAVE A IN YET ANOTHER TEMP
MASK OFF HIGH NYBBlE
ADD ASCII ZERO
CHECK FOR A-F

#'9
PUTNY2
#'A-'9-1 ADJUSTMENT FOR HEX A-F
PUTC
GET+3
RESTORE A

GET
#CR
PUTC

SAVE

#IF

PUTC
GET

RESTORE

PUTS --- PRINT A BLANK (SPACE)
A AND X UNCHANGED
STA
LDA
LDA
RTS

**
*

GO TO NEXT
FINISH UP WITH A BLANK

CRLF --- PRINT CARRIAGE RETURN, LINE FEED
A AND X UNCHANGED

BSR

be
05
02
be

SHIFT HIGH TO LOW
PUTNYB
GET
PUTNYB
BUMP
PUTS

PUTNYB --- PRINT LOWER NYBBLE OF A IN HEX
A AND X UNCHANGED, HIGH NYBBLE
OF A IS IGNORED.

LDA
BSR
LOA
RTS

*
*
**
*
*
*
*GETBYT

GET THE BYTE
SAVE A

PUTBYT --- PRINT A IN HEX
A AND X UNCHANGED

~5R

**
*
*
PUTS

PICK
GET

GETBYT

GET
#Bl
PUTC
GET

SAVE
RESTORE

GET A HEX BYTE FROl1 TERMINAL

A GETS THE BYTE TYPED IF IT WAS A VALID HEX NUMBER,
OTHERWISE A GETS THE LAST CHARACTER TYPED.
fHE C-BIT IS
SET ON NON-HEX CHARACTERS;
CLEARED
OTHERWISE.
X
UNCHANGED IN ANY CASE.
BSR
BCS
ASLA
ASlA
ASLA
ASlA
STA
BSR
BCS
ADD
RTS

GETNYB
NOBYT

BUILD BYTE FROM 2 NYBBLES
BAD CHARACTER IN INPUT

GET
GETNYB
NOBYT
GET

SHIFT NYBBLE TO HIGH NYBBLE
SAVE IT
GET LOW NYBBLE NOW
BAD CHARACTER
C-B IT CLEARED

GETNYB --- GET HEX NYBBLE FROM TERMINAL

7-24

Application Note AN-8601.1

*
*
*
*
*GErNYB

09b9 ad Ie
09bb a4 7f
09bd b7 c1
09b~ aO 30
0gel 2b 10
0ge3 al 09
09<5 23 Oa
0ge7 aO 07
0ge9 al Of
0geb 22 06
0ged al 09
0gef 23 02
09d 1 9B
09d2 Bl
09d3 b6 < 1
09d5 99
09d6 Bl

GOTIT
NOTHEX

*
*
*
**
*
*
*
**
*GETC

09d7 Ob 10 fd
09da cd 01 ae
09dd b6 11
09d~ cd 09 ,,5
09,,2 a4 7f
09,,4 81

**
**
*
PUTC

09,,5 Of 10 fd
09"B b7 11
09"a Bl

*
*

*
09,,1>
09"d
09"f
09fl
09f3

09f5
09f6
09f9
09fb
09fd
OaOO
OaOI

12
a6
b7
a6
b7

Sf
d6
al
27
cd
5e
20

*RESEr

bB
30
Od
Oe
Of

*
*
*
Oa 06
00
06
09 ,,5

BABBLE

f3

*MSTART

Oa03 B3
Oa04 20 .,5

**
Oa06 Od Oa
Oa09 52 4f
4" 49
46 4f
45 20
30 35
Oa25 Od Oa
Oa27 46 4f
46 4f
49 4f
50 45

A GETS THE NYBBLE TYPED IF IT WAS IN THE RANGE O-F.
OTHERWISE A GETS THE CHARACTER TYPED.
THE C-BIT IS SET
ON NON-HEX CHARACTERS,
CLEARED
OTHERWISE.
X
IS
UNCHANGED.
BSR
AND
STA
SUB
BMI
CMP
BL.S
SUB
CMP
BHI
CMP
BLS
CLC
RTS
LDA
SEC
RTS

20
4f
20
3B
34

52
52
4"
20

20 49 4"
4d 41 54
2c 54 59
49

4d
52
54
4B

4f
20
4B
43

GET+3

GEr SAVED CHARACTER
RETURN WITH ERROR

S E R I AL

I

0

R 0 UTI N E S

DEFINITION OF SERIAL liD LINES
GETC --- GET A CHARACTER FROM THE TERMINAL
A GETS THE CHARACTER TYPED, X IS UNCHANGED.
BRCLR
J5R
LDA
JSR
AND
RTS

5.$10.*
BEL

WAIT FOR RDRF
GET CHARACTER
ECHO BACK
MASK PARITY
AND RETURN

$11

PUTC
#$7F

PUTC --- PRINT A ON THE TERMINAL

X AND A UNCHANGED
BRCLR
STA
RTS

7.$10.*

BSET
LDA
STA
LDA
STA

WAIT FOR TDRE
OUTPUT THE CHARACTER

$11

RESET ---

POI~ER

ON RESET ROUTINE

1. NOPRNT
#$30
$OD
SET UP FOR 9600 BAUD(AT 4MHZ)
#$OC
$OF
TURN ON RECVR AND XMITER

PRINT SIGN-ON MESSAGE
CLRX
LDA
CMP
BEG
.JSR
INCX
BRA

MONMSG.X
GET NEXT CHARACTER
#EOS
LAST CHAR?
MSTART YES. START MON~TOR
PUTC
AND PR I·NT IT
ADVANCE TO NEXT CHAR
BABBLE MORE MESSAGE

SWI
BRA

RESET

PUSH MACHINE STATE AND GO TO MONITOR ROUTINE
LOOP AROUND

MONMSG --- POWER UP MESSAGE

*MONMSG

Oa
4d
54
52
36
43

GETC
GET THE CHARACTER
#7.1111111 MASK PARITY
GET+3
SAVE IT JUST IN CASE
#'0
SUBTRACT ASCII Z£RO
NOTHEX WAS LE5S THAN '0'
#9
GOTIT
#'A-'9-1 FUNNY ADJUSTMENT
#$F
TOO BIG?
NOTHEX WAS GREATER THAN 'F'
#9
CHECK BETWEEN 9 AND A
NOTHEX
C=O MEANS GOOD HEX CHAR

FCC

FCB

CR. LF. LF
IROM MONITOR FOR THE 6BHC05C41

FCB
FCC

CR, LF
.
IFOR INFQR;1ATION. TYPE II

7-25

Application Note AN-8601.1
0 .. 3d Od 0 ..
0 .. 3f 54 4f
55 52
20 44
45 58
45 20
20 30
0 .. 62 00

20
4e
45
45
46
31

52
20
4d
43
52
32

45
54
44'
55
44'
42

54
4f
2c
54
4d

FCB
FCC

CR.LF
ITO RETURN TO DEMO. EXECUTE FROM 01281

FCB

EOS

*

*
*
**

*

MASTER CONTROL PROGRAM
*ENTRY POINT IS FROM RESET VECTOR
*THIS ROUTINE DETERMINES WHAT TO DO
*
*
MCP
7. PTD.SPIR
*IF PD7=0 THEN DO SPI ROUTINES
BRCLR
JMP
DEMOA
*OTHERWISE DO DEMO
*
*
*
*

Oa63 Of 03 03
Oa66 cc 01 00

Oe4b Oa Od
Oe4d 20 20
48 45
38 48
34 20
53 20
4f 43
54 45
20 41
42 45
Oc80 0.. Od
Oe82 4f 46
20 4d
30 35
49 4c
20 4c
4f 53
4e 47
48 49
Ocaf 0 .. Od
,Oeb1 4d 49
4. 4d
52 53
49 53
49 54
52 4.
55 54
4f' 4e

DUMP
20
20
43
48
4d
4f
52
20
52

29
4d
30
43
49
4d
20
4d

20
43
35
4d
43
50
49
45

54
36
43
4"
52
55
53
4d

20
36
20
59
4f
54
4e
50

54
38
46
20
57
20
45

48
48
41
4f
20
53
2d

45
43
4d
46
43
49
43

43 52 4.
50 55 54
2e 20 54
20 38 2d
20 4d 49
43 4f 4d
45 52 20
54 41 49

43
45
48
42
43
50
43
4e

FCB
FCC

SOA.SOD
I
THE MC68HC05C4 HCMOS MICROCOMPUTER IS A t1EMBERI

FCB
FCC

SOA.SOD
10F THE M68HC05 FAMILY OF LOW COST SINGLE-CHIPI

FCB
FCC

SOA.SOD
IMICROCOMPUTERS.

FCB
FCC

SOA.SOD
*AN'ON CHIP OSCILLATOR. CPU. RAM. 1/0. TWO SERIAL*

FCB
FCC

SOA.SOD
I INTERFACE SYSTEMS. AND TIMER. THE FULLY STATIC DESIGNI

FCB
FCC

SOA.SOD
IALLOWS OPERATION AT FREQUENCIES DOWN TO DC. FURTHERI

THIS 8-BIT MICROCOMPUTER CONTAINSI

53

Oce2 Oa Od
Oc,,4 41 4e 20 4f' 4"
43 48 49 50 20
53 43 49 40 4c
54 'If 52 2.: 43
55 2t 52 41 4d
49 2f 4f 2c 54
4f 20 53 45 52
41 4e
Od10 Oa Od
Od12 49 4e 54 45 52
41 43 45 20 53
53 54 45 4d 53
41 4e 44 20 54
4d 45 52 2 .. 54
45 20 46 55 4t
59 20 53 54 41
49 43 20 44 45
49 47 4.
Od45 0" Od
Od47 41 4c 4c 4f 57
20 4f 50 45 52
54 49 4f 4 .. 20
54 20 46 52 45
55 45 4" 43 49
53 20 44 'If' 57
20 54 4f 20 44
2e 46 55 52 54
45 52

20
4f
41
50
2t
57
49
46
59
2t
49
48
4t
54
53
53
41
41
51
45
4e
43
48

7-26

Application Note AN-860 1. 1
Od79 Oa Od
Od7b 52 45
4e 47
20 41
44 59
2d 50
20 43
4d 50
2e
Oda6 Oa Od
Oda9 54 4B
4e 49
4B 41
45 20
4f 57
43 4f
44 53
OddO Oa Od
Odd2 52 20
50 52
52 45
45 52
OdeB Oa Od
Odea 41 20
50 52
43 4B
20 41
55 4d
4f 52
OeOb Oa Od
OeOd 5B 20
50 52
43 4B
20 5B
55 4d
4f 52
Oe2e Oa Od
Oe30 4d 20
4d 45
20 45
4e 45
4e 47
Oe4c Oa Od
Oe4e 43 20
43 4f
55 45
47 52
Oe65 Oa Od
Oe67 45 20
45 58
45 20
20 41
53 53
0,,82 Oa Od
0,,84 53 20
44 49
59 20
49 4e
41 54
OeaO Oa Od
Oea2 49 20
49 4"
Oeac Oa Od
Oeae 00

44
20
4c
20
4f
4f
54

55
49
52
4c
57
4e
49

43
54
45
4f
45
53
4f

49
53
41
57
52
55
4e

Oa
45
54
53
46
49
4d
3a

20
4f
20
4f
4e
4d

4d
52
54
4c
47
41

4f
20
4B
4c
20
4e

2d
49
47
53

2d 20 20
4e 54 20
49 53 54
2e

2d
49
41
20
55
2e

2d
4e
4e
41
4c

20
54
47
43
41

20
2f
45
43
54

2d
49
41
20
55
2e

2d
4e
4e
41
4c

20
54
47
43
41

20
2f
45
43
54

2d
4d
58
2f
45

2d
4f
41
43

20
52
4d
48

20
59
49
41

2d
4e
20
41

2d
54
50
4d

20 20
49 4e
52 4f
2e

2d
45
46
44
2e

2d
43
52
44

20
55
4f
52

20
54
4d
45

2d
53
4d
45
45

2d
50
41
20
2e

20
4c
43
53

20
41
48
54

2"

Oa
OebB 20
20
20
2a
20
20
Oed9 Oa
Oedb 20
20
20
2a
20
20
Oefd Oa

Oa
20
20
20
20
20
20
Od
20
20
20
2a
20
2a
Od

Oa
20
20
20
20
20
2a

20
20
20
20
20

20
20
20
20
20

20
20
20
20
20

20
20
20
20
20
2a

20
20
20
20
20
2a

20
20
20
20
20

20
20
2a
20
20

$OA.$OD
/REOUCING ITS ALREADY LOW-POWER CONSUMPTION. /

FCB
FCC

$OA.$OD.$OA
/THE MONITOR HAS THE FOLLOWING COMMANDS: /

FCB
FCC

$OA.$OD
/R -- PRINT REGISTERS. /

FCB
FCC

$OA.$OD
*A -- PRINT/CHANGE A ACCUMULATOR ....

FCB
FCC

$OA.$OD
*X -- PR WT /CHANGE X ACCUMULATOR. *

FCIl
FCC

$OA.$OD
*M -- MEMORY EXAMINE/CHANGE.

FCIl
FCC

$OA.$OD
/C -- CONTINUE PROGRAM. /

FCIl
FCC

$OA.$OD
/E -- EXECUTE FROM ADDRESS. /

FeB
FCC

SOA.SOD
/S -- DISPLAY MACHINE STATE. /

*

Z

CI

~~

ulCI
~z

2d 2d 20 20
46 4f

Oeaf Oa Od Oa Oa Oa 0 ..

FCB
FCC

BATWIN

a...

FCB
FCC

$OA.$OD

FCB
FCB

$OA.$OD
$00

FCB

$OA.$OD.$OA.$OA.$OA.$OA.$OA.$OA.$OA

FCC

/

FCIl
FCC

$OA.$OD

FCIl

$OA.$OD

/

7-27

C

INFO/

/1 --

*

*/

***

***/

Application Note AN-8601.1
Oeff 20
20
20
2a
20
2a
Of22 Oa
Of24 20
20
20
2a
20
2a
OF48 Oa
Of4a 20
20
20
2a
20
2a
2a
Of6f Oa
0f71 20
20
20
2a
20
2a
2a
Of97 Oa
Of99 20
20
2a
2a
2a
2a
2a
OfrO Oa
Ofc2 20
20
2a
20
2a
20
2a
Ofea Oa
Ofec 20
20
2a
20
20
20
2a
1015 Oa
1017 20
20
2a
20
20
20
20
1041 Oa
1043 20
20
20
20
20
20
20
2a
106" Oa
1070 20
20
20
20
20
20
20
2a
109c Oa
109" 20

20
20
20
2a
20
2a
Od
20
20
20
2a
20
2a
Od
20
20
20
2a
20
2a
Od
20
20
2a
2a
20
2a
2a
Od
20
20
2a
2a
20
2a
2a
Od
20
20
2a
20
2a
20
2a
Od
20
20
2a
20
2a
20
2a
Od
20
20
20
20
20
20
20
Od
20
20
20
20
20
20
20
Od
20
2a
20
20
20
20
20
2a
Od
20

20
20
20
2a
20
2a

20
20
20
20
20
2a

20
20
2a
20
20
2a

20
20
2a
20
20

20
20
20
2a
20
2a

20
20
2a
2a
20
2a

20
20
2a
20
20
2a

20
20
2a
20
2a
2a

20
20
2a
2a
20
2a

20
20
2a
2a
20
2a

20
20
2a
2a
2a
2a

20
20
2a
20
2a
2a

20
20
2a
2a
20
2a

20
20
2a
2a
2a
2a

20
20
2a
2a
2a
2a

20
20
2a
2a
2a
2a

20
20
2a
2a
2a
2a
2a

20
20
2a
2a
2a
2a

20
20
2a
2a
2a

20
20
2a
20
2a
20
2a

20
20
2a
20
20
20
2a

20
20
2a
20
20
2a

20
2a
20
20
20
2a

20
20
2a
20
20
20
2a

20
20
20
20
20
20
2a

20
2a
20
20
20
20
2a

20
2a
20
20
20
20

20
20
20
20
20
20
2a

20
2a
20
20
20
20
2a

20
2a
20
20
20
20
2a

20
2a
20
20
20
20
2a

20
2a
20
20
20
20
20

20
2a
20
20
20
20
20

20
2a
20
20
20
20
2a

20
20
20
20
20
20
2a

20
2a
20
20
20
20
20

20
2a
20
20
20
20
20

20
20
20
20
20
20
20

20
20
20
20
20
20
2a

20
20
2a
2a
2a
2a 2a

20 20 20 20

FCC

FCB
FCC

$OA.$OD

FCB
FCC

$OA.$OD

FCB
FCC

$OA.$OD

FCB
FCC

$OA.$OD

FCB
FCC

$OA.$OD

FCB
FCC

$OA.$OD

FCB
FCC

$OA.$OD

FCB
FCC

$OA.$OD

FCB
FCC

$OA.$OD

FCB
FCC

$OA.$OD

*it·jt.**

*****1

*.******

*·l!-il··****1

******.***

******"'***/

***********

******~****/

/

I

I

*****.******** *******-41'**'***1

/

/

*****~

/

*****

/

*.II--n*

**-11-

/

1

/

7-28

*iI·)f.

**

***

*

******1

*****/,

****1

***1

***/

**1

Application Note AN-860 1. 1

10cb
10ed

10fb
10fe

20
20
20
20
Os
20
20
20
20
20
20
20
20
Oa
00

20
20
20
2a
Od
20
20
20
20
20
20
20
20

20 20 20 20
20 20 20 20
20 20 20 20
2a
20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
2a

20
20
20
20
20
20
20

10fd 20 fe
10ff 80
1100 00
00
00
00
00
00
00
00
00
00

00
00
00
00
00
00
00
00
00
00
00 00

0020
0020
0021
0024
0026
0029
002a
002e
002"
0031
0033
0036
0037
0039
003b
003e

00
00
00
00
00
00
00
00
00
00
00

00
00
00
00
00
00
00
00
00
00
00

00
00
00
00
00
00
00
00
00
00

FCB
FCC

$OA,$OD

FCB
FCB

$OA
$00

SPINT
llNT

BRA
RTI

*

*

BSZ

$lFOO-*

2a
20
20
20
20
20
20

00
00
00
00
00
00
00
00
00
00

*
*
*
*
*
*
*
**
*
*
5f
d6
27
ed
5e
27
be
d6
27
cd
5e
27
be
d6
27
cd
Sc
26
a6
cd
ce

0040
0043
0044
0046
0048
004b
004 .. 00

0" af
25
09 eS

*1

*

SPlINT ROUTINE
INT INT ROUTINE(JUST IN CASE)
FILL THE 3584 BYTES OF UNUSED ROM SPACE WITH O'S.

$lFOO IS AT THE BEGINNING OF SELFCHECK. THOUGH
THERE IS ACTUALLY NO ROM IN THIS SPACE TO BE
PROGRAMMED, THE PART IS DESIGNED SUCH THAT THIS
THIS SPACE READS AS ALL O'S. THE BSZ IS USED
SIMPLY TO REMIND THE USER OF THIS FACT.

DEFINITION OF PAGE ZERO OF ROM. THIS ROUTINE WRITES OUT THE BATWING
PATTERN SHOWN ABOVE.

BAT
BAT1

02
21
Of af
18
09 .. 5

BAT2

02
2 ..
10 af
Ob
09 e5

BAT3

fS
Oa
09 .. 5
09 37
00

I

GETOUT

ORG
CLRX
LOA
BEG
.J5R
INCX
BEG
.IMP
LOA
BEG
JSR
INCX
BEG
JI1P
LOA
BEG
JSR
INCX
BNE
LOA
.JSR
JMP
FCB

$20
BATWIN,X
GETOUT
PUTC
BAT2
BATi
BATWIN+$100,X
GET OUT
PUTC
BAT3
BAT2
BATWIN+$200,X
GETOUT
PUTC
BAT3
#$OA
PUTC
XMONIT
$00,$00

FILL IN EXTRA SPACE

*
*
*

*******·"*****·»*******·:'******4**************************************
INTERRUPT VECTORS

*
1ffO 10 H
1ff2 10 H
1ff4
1ff4
lff6
1ff8
1ffa
1ffe
1ff ..

*
10
01
02
10
08
Oa

fd
Sc
d1
ff
71
63

VEC

FOB
FOB

lINT
lINT

ORG
FOB
FDB
FOB
FOB
FOB
FOB
END

$1FF4
SPINT
START
TINT
lINT
MONIT
MCP

INCLUDED PER CIRCUITS' REGUEST

7-29

Harris Semiconductor

__-_-§§E

Monitor For The
CDP6805G2 Microcomputer

INTRODUCTION

R-

The CDP6805G2 is a fully static single-chip CMOS
Microcomputer. It has 112 bytes of RAM, 2106 bytes of user
ROM, four 8-bit inpuVoutput ports, a timer, and an on-chip
oscillator. The CDP6805G2 ROM containsa monitor routine
which provides the user with the ability to evaluate the
CDP6805G2 using a standard RS232 terminal. The user can
enter short programs into the on-chip RAM and execute
them via the monitor. A description of the monitor operation
follows along with an assembled listing of the actual
program.

The processor registers are displayed as they appear on the
stack. The format of the register print is:
HINZC AA XX PP
The first field shows the state of the condition code register
bits. Each bit in the register has a single letter corresponding
to the bit name. If the letter is present, the bit is 1. If a "." is
printed in place of the letter, that bit is O. For example,
"H .. ZC" means that the H, Z, and C bits are 1 and that the I
and N bits are O. The remainder of the line shows the status
of the accumulator, index register, and program counter,
respectively. The stack pointer is always at a fixed address
(in this case $7A). The values shown are the values loaded
into the CPU when a "C" or "E" command is executed. All
register values except the condition code register can be
changed with other commands. To change the condition
code register, it is necessary to use the memory change
command and modify location $7B.
A - Examine/Change the Accumulator

MONITOR MODE

In this mode the CDP6805G2 Microcomputer is connected
to a terminal capable of running at 300,1200,4800, or 9600
baud. Fig ure 1 contains a schematic diagram of the monitor
mode connections and a table showing CO and C1 switch
settings to obtain a baud rate that matches the terminal. Be
sure the oscillator frequency is 3.579545 MHz. Any area of
RAM from locations $18 to $7A may be used for program
storage; however, upper locations may be needed for user
stack.
When the microcomputer is reset, a power-up message is
printed. Following the message, the prompt character "." is
printed and the monitor waits for a response. The response
may consist of single letter commands with some commands
requiring additional input. Unrecognized commands
respond by printing "?". Valid commands are:
R - Display the Register
A - Display/Change the Accumulator
X - Display/Change the Index Register
M - Display/Change Memory
C - Continue Program Execution
E - Execute Program at Address
S - Display State of I/O and Timer

Display the Register

This command begins by printing the current value of the
accumulator and then waits for more input. In order to
change the current value, type in a new value (two hex
digits). To leave the accumulator unchanged, type any nonhex digit (a space is a good choice).
X - Examine/Change the Index Register
This procedure is the same as the "A" command, but affects
the index register instead.
M - Examine/Change Memory
Any memory location may be examined or changed with
this command (except of course, ROM). To begin, type "M"
followed by a hexadecimal address in the range $0000$1 FFF. The monitor responds by beginning a new line and
printing the memory address followed by the current

June 1985

AN-7200.1
7-30

Application Note AN-7200. 1

+5V
10 k
20 pF

Baud Rate Switch

. r -=l

Cl
0
0

Reset

-1

iRO

Rate
300
1200
4800
9600

0= Closed
1 = Open

NUM

::::r: 20 pF

PA7

CO
0
1
0

To Terminal

2
3

5
6

8

-12V
3

Serial Out

10
7

10 k
+5V

PC7

DB25 Connector

Fig. 1 - Monitor mode schematic diagram.

contents of that location. At this point you may type:
1. "." and re-examine the same byte. (Try this with
location $0008.)
2. "N' ~nd go to the pr~vious byte. Typing "1\" at
location $0000 causes the monitor to go to $1 FFF
3. "CR" and go to the next byte. "CR" is the carriage
return character. The byte after $1 FFF is $0000.
4. ''~O'', where ''~O'' is a valid 2-digit hexadecimal
number. The new data is stored atthe current address
and the monitor then goes to the next location. This
means that to enter a program it is only necessary to
go ~o t~e starting address of the program and start
!YPlng In the bytes. To see if the byte was really
Inputted, you can use the "1\" character to return to
the last byte typed in.
5. Finally, any character other than those described
above causes the memory command to return to the
prompt level of the monitor and prints " ....

C - Continue Program Execution
The "C" command merely executes an RTJ instruction. This
means !hat all th~ regi~ters are reloaded exactly as they are
shown In the register display. Execution continues until the
reset switch is depressed or the processor executes an SWI.
U~on executing an SWI, the monitor regains control and
prints the prompt character. This feature can be used for an
elementary form of breakpoints. Si nee there is really no way
to know where the stack pointer is after an SWI, the monitor
assumes that it is at $7 A. This will not be the case if an SWI is
part of a-subroutine. In this case, the monitor will be reentered but the stack pointer will pOint to $78. This is
perfectly valid and typing "C" will pick up the program from
where it left off. However, the A, X, R, and E commands all
assume the stack starts at $7A and will not function
properly. If the stack location is known, it is still possible to
examine the registers by using the M command.

7-31

Application Note AN-7200. 1
E - Start Execution at Address
The" E" com mand waits for a valid memory address ($0000$1 FFF) and places the address typed on the stack at
locations $7E and $7F. The command then executes an RTI
just like the "C" command. If the address typed is not a valid
memory address, the command exists to the monitor
without changing the current program counter value.

The data displayed is simply memory (RAM) locations
$0000-$0003 with $0008 and $0009. Ports A, B, and D may
be written to by first making them all outputs, i.e., for portA,
change location $0004 (port A DDR) to $FF. Port C and the
timer registers cannot be changed as they are used by the
monitor.

S - Display 1/0 States and Timer

MONITOR PROGRAM

The "S" command displays ports A, B, C, and D data along
with the timer data and control register contents. The
format of the display is:
ABC D TIM TCR

A flowchart for the monitor mode program is provided in
Figure 2. A listing for the ROM monitor program is attached
to the end of this application note.

Fig. 2 - Monitor mode operating flowchart.

7-32

Application Note AN-7200. 1

CDP680SG2 ROM Monitor

'"

CDP680SG2 ROM Pattern

'"
...'"
'"
'"
'"
'..."

The CDP6805G2 single-chip microcomputer is a 40-pin CMOS device with
2096 bytes of ROM, 112 bytes of RAM, four 8-bit I/O ports, a timer and an
external interrupt input. The ROM contains two separate programs. Either
of these programs may be selected on reset by wiring port C as follows:

...'"

...

...'"

'"
...'"
'"
'"
'"
...'"

C7

C1

CO

1
1
1
1
0

0
0
1

0
1
0

1

1

X

X

function

-------monitor
monitor
monitor
monitor
bicycle

(300 baud)
(1200 baud)
(4800 baud)
(9600 baud)
odometer

The monitor is substantially the same as all previous
monitors for the 6805.
The monitor uses serial I/O 'or
its communication with the operator.
Serial input is C2
and serial output is C3.

*---------------------------------------------------------------------...
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000

00
00
00
00
00
00
00
00
00
01
20

00
00
00
00

"
..'porta

I/O Register Addresses

portb
portc
portd
ddr
timer
tcr
RAM
ZROM
ROM
MEMSIZ

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

...'"

'"

Character Constants

Od

CR

Oa
20
00

LF

equ
equ
equ
equ

00
01
02
03
04
08
09
10
80
00
00

BL
EOS

$000
$001
$002
$003
4

$008
$009
$010
$080
$100
$2000

$00
$OA
$20
$00

I/O port 0
110 port 1
I/O port 2
I/O port 3
data direction register o'fset
8-bit timer register
timer control register
start of on-chip ram
start of page zero rom
start of main rom
memory add"ess space size

(e.

g.

porta+ddr)

carriage return

line feed
blank
end of string

...
...
***********************************************************************
...

...'"

...
...
...
...
...

ROM Monitor for the CDP680SG2

The monitor has the following commands:

Copyright 1982 MOTOROLA INC.

7-33

Application Note AN-7200.1
CDP6805G2 ROM Monitor

R -- Print registers.
*
format is CCCCC AA XX PPP
*
*
A -- Print/changeA accumulator.
*
Prints the register value, then
*
waits for new value.
Type
*
any non-hex character to exit.
*
*
x -- Print/change X accumulator.
*
Works the same as 'A',. except modifies X instead .
*
M -- Memory examine/change.
*
Type M AAA to begin,
*
then type:
to re-examine current
*
to examine previous
*
CR
to examine next
*
DD
new data
*
Anything else exits memory command.
*
*
Execution starts at
C -- Continue program.
*
the location specified in the program
*
counter, and
*
continues until an swi is executed
*
or unti 1 reset.
*
*
E -- Execute from address.
Format is
*
E AAAA.
AAAA is any valid memory address.
*
*
All important registers are
S -- Display Machine State.
*
d i sp laved.
*
*
*
Special Equates
*
*PROMPT equ
prompt character

.

0602
0602
0602
0602

00
00
00
00

2e
Od
5e
2e

0602 00 7f
0602 00 7a

0602
0602
0602
0602
0602

00
00
00
00
00

10
14
15

16
17

FWD
BACK
SAI1E

*
*
*initsp
stack

*
*
*get
atemp
xtemp
char
count

*
*
*
*
*

equ
equ
equ

go to next byte
go to previous byte
re-examine same byte

CR

Other
equ
equ

S7F
initial stack pOinter value
initsp-S top of stack

ram variables
equ
equ
equ
equ
equ
state

RAM+O
RAM+4
RAM+S
RAM+6
RAM+7

4-byte no-mans land, see pick and drop subroutines
acca temp for getc,putc
x reg. temp for getc,putc
current input/output character
number of bits left to get/send

print machine state

ABC D TIM TCR
dd dd dd dd dd dd

7-34

Application Note AN-7200. 1
CDP6805G2 ROM Monitor

*
*
*iomsg

iJbO';~

01 0,..3

\:)h{.,.14

20 20 42 20
20 43 20 20 44 20
5'1 4', 4d 20 54 43
~.:()

4l.

header string for 110 register display
fcb
fcc

CR,LF

fcb

CR,LF,EOS

/

A

B

C

0 TIM TCR/

5~:Z

\)617 Od 003 00
'')61~

061b

5f
d6 06 02

*state
stat.e2

061e a1

00
0620 27 06
0622 cd 08 01
010,25 50
0626 20 t~ 3
0628

0628
0629
06201
062d
0630
0631
0633

5f
f6
cd
cd
5c
013
26

0635
0638
06301
063d
0640
0643
0645
0648

cd
b6
cd
cd
cd
b6
cd
20

pio
07 5e
07 8b
04
f4
8b

064f
0651
0652
0653
0654
0656
0657
0659
065b
065d
0660
0663

b6
48
48
48
b7
5f
016
38
24
d6
cd
5c

*

5e
8b
8b
5e

064011 48 49 4e 501 43
7b

*
*
*
*
*ccstr
*pee

10
2e
10
03
06 401
08 01

iomsg, x get next char
Q.uit?
state3 yes, now print values
no, print char
putc
bump pointer
state2 do it again

ItEOS

state3

*
*
*

07
08
07
07
07
09
07
48

clr.
Ida
cmp
beQ.
Jsr
incx
bra

pcc2

pcc3

now print values underneath the header

.

clrx
Ida
Jsr
Jsr
incx
cpx
bne

,
putbyt
puts

start wi th I/O ports

1t4
pio

end of liD?
no, do more

Jsr
Ida
Jsr
Jsr
Jsr
Ida
Jsr
bra

puts
timer
putbyt
puts
puts
tel'
putbyt
monit

pcc

print condition codes

string

TOT'

pee

now print the value in the timer

the control T'eg i ster too
all done

subroutine

fcc

IHINZC/

Ida
asIa
asIa
asIa
st-a
clrx
Ida
as1
bcc
Ida
Jsr
incx

stack+1 condition codes in acca
move h bit to bit 7

z

Q

~~

get

save it

~z
c..

It'.

get

put bit in c

pcc3
bit qff means print
ccstr, x pickup appropriate character
putc

7-35

~:;

or character
print
point to next in string

cC

Application Note AN-7200. 1
CDP6805G2 ROM Monitor
0664- a3 05
0666 25 ef'
0668 81

cpx
blo
rts

*
*
*seta

0669 a" 7c
066b 20 02

*

*
*setx
*
*
*setany

066d 

el
2e

*
*
*
075e b7
0760 44
0761 44
076~ 44
076:3 44
0764 ad
0766 b6
0768 ad
076a 81

076b
076d
076f
0771
0773
0775
0777
07701
077c

b7
a4
ab
al

23
ab
cd
b6
81

10

"putbyt

05
10
01

13
Of
30
39
02
07
08 01
13

*
*
*
"*
putnyb

putny2

"

*
*
077d
077f
0781
0784
0786
0788
078a

b7 10
a6 Od
cd 08 01
a6 Oa
ad 79
b6 10
81

"crlf

putbyt
bump

out2hs

and prin.t it
go to next address

print byte pointed to.

then a space.

bump pointer

X is unchanged at exit

bsr
sta
Isra
Isra
Isra
Isra
bsr
Ida
bsr
bsr
bsr
rts
putbyt

sta
Isra
Isra
Isra
Isra
bsr
Ida
bsr
rts
putnyb

sta
and
add
cmp
bls
add
Jsr
Ida
rts
crlf

sta
Ida

Jsr
Ida
bsr
Ida
rts

pic k
get

get the byte
save A

sh i ft high to low
putnyb
get
putnyb
bump
puts

go to next
finish up with a blank

----

print A in hex
A and X unchanged
get

save A

putnyb
get
putnyb

shiH high nybble down
print it
print low nybble

print lower nybble of A in hex
A and X unchanged, high nybbI"
of A is ignored.

~.--

get+3
save A in yet another temp
#$F
mask Qff high nybble
#'0
add ascii zero
#'9
check for A-F
putny2
#'A-'9-1 adjustment for hex A-F
p u tc
get+3
restore A

z

C)

print carriage return,
A and X unchanged
9"t
lIeR
putc
IILF
putc
get

7-39

save

restore

line feed

~~
u~
-

ct
a..
C

C)

Z

Application Note AN-7200. 1

CDP680SG2 ROM Monitor

07Bb
078d
078f
0791
0793

b7
a6
ad
b6

10
20
70
10

*
*
*
*puts

81

*
*
**
*
*
0794
0796
0798
0799
079a
079b
079c
07ge
07aO
07a2
07a4

ad
25
48
48
48
48
b7
ad
25
bb
81

Of

*
*getbyt

Oc

10
05

02
10

nobyt

*
*

**
*

*
*

07a5
07a7
07a9
07ab
07ad
07af
07b1
07b3
07b5
07b7
07b9
07bb
07bd
07be

ad

1e

'getnyb
"

a4 7f

b7
aO
2b
a1
23
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a1
22
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98
81

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10
09

Oa
07
Of
06
09
02

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print a blank '

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16

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6 Bytes
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8064

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CIl

CIl

CIl

CIl

~

.... .... .... .... .... .... .... ....
TRANSMITTER
BUS

H

23
THRL

a.

.,"'

"'

W

a.
w

"';0-' "';0-'

W
0:

CRL

SFO

CONTROL INPUT
PINS

....z

W
0:

~

W

a.

W

u.

W

0

"
OAR

STATUS OUTPUT
PINS

'"
.,:>"' "':> .,"':> "'::> :>"'
~

0

CIl

CIl

0:

0:

0:

"' .,:>"'

:>

CIl
0:

0:

CIl
0:

0:

RRO

RECEIVER
BUS

92CM-42431

Fig. 1 - Block diagram of a representative first-generation UART, the CDP1854A (Mode 0).

ffi

DO~D7

Txo

DcD
OSR

Z

RxC
XTLI

XTLO

OTR

ASYNCHRONOUS SERIAL
COMMUNICATIONS INTERFACE

MICROPROCESSOR INTERFACE

92CM-42430

Fig. 2 - Block diagram of a representative second-generation UART, the CDP65C51.

7-93

CI

i=f3
~S
~z

a..
cc

Application Note AN-8756.1
The lists of features in Table I are not exhaustive. The set of
features listed for each category includes only those which,
on one hand, are common to most UARTs in that category
but, on the other hand, help distinguish that category from
the other. Consequently, features inherent in all UARTs,
and therefore common to both categories, are not listed.
Furthermore, the entries in Table I are not as specific for
second generation UARTs as for first generation UARTs for
the reason that there is more variation among second
generation parts.

+125° C. The maximum clock frequency of these parts at 5
volts and 85°C is 3.2 MHz, which translates to a maximum
baud rate of 200 kbits per second. The maximum clock
frequency of the CDP6402 at 10volts and 85°C is6.45 MHz,
which yields a baud rate of 400 kbits per second. The block
diagram for the CDP1854A, shown in Fig. 1, also applies to
the CDP6402.

Note in Fig. 1 that the control signals and clock signals will
be supplied, by the system, to input pins of the UART, that
the status signals are available on output pins of the UART,
and that there are two separate unidirectional data buses.

This device is also available in 5 and 10-volt versions, the
CDP1854AC and the CDP1854A, respectively. Both of
these devices have two modes of operation, Mode 0 and
Mode 1. (Mode 1 is discussed later in this Application Note;
Mode 0 is discussed here.) When the CDP1854A and
CDP1854AC are used in Mode 0, they are functionally
identical to the CDP6402 and CDP6402C, respectively, and
all information contained in the preceding paragraph for
the CDP6402 devices also applies to the CDP1854A devices.
The one physical difference is that pin 2 is a no-connect on
the CDP6402 devices, whereas it is the mode select pin on
the CDP1854A devices. The CDP1854A devices are also
available in hi-rei versions, the CDP1854A/3 and
CDP1854AC/3.

Note in Fig. 2 that command and control information is
written to the UART, and status information read from the
UART, via a single bidirectional data bus (not via dedicated
pins, as in Fig. 1). Note also that the microprocessor
interface signals and the communications handshaking
signals, which did not appear at all in Fig. 1, are shown in
Fig. 2 with dedicated input and output pins.
First Generation UARTs - Individual Device Descriptions
Following is a description of each Harris device that falls under
the heading of first generation UART. To reiterate, these are the
CDP6402, CDP1854A,IM6402 and IM6403. All these devices
are, functionally, either very similar or identical to one another.
However, there are a number of differences among them with
respect to ac and dc electrical specifications. Where
there are functional differences, they will be discussed
within the individual device descriptions, since this is one of
the objectives of this Note. On the other hand, variations in
electrical speCifications will not be discussed, since it
would not be practical to do so. The user should refer to the
individual data sheets for each part when a comparison of
electrical specifications is necessary.
In addition to being similar to each other, these parts are
very much like all other devices in this category, and
consequently are accurately described by the list of features
for first generation UARTs in Table I. This list is not
repeated for each part, but it is hereby implied. The
individual device descriptions, then, are dedicated to listing
the various package types, operating voltage ranges,
temperature ranges, maximum operating frequencies, and
additional features.
CDP6402
This widely used first generation UART is available in both a
5-volt version, the CDP6402C, and a 10-volt version, the
CDP6402. The CDP6402C operates from 4 to 6.5 volts, and
the CDP6402, from 4 to 10.5 volts. Each version is available
in either a plastic DIP package, with an operating
temperature range of -40 to +85°C, or a ceramic DIP
package, with an operating temperature range of -55 to

CDP1854A

IM6402
There are three fundamental versions of this device: the
IM6402, IM6402-1, and IM6402A. Again, the list of features
for these devices is identical to that which appears in Table I
for first generation UARTs and, again, the block diagram in
Fig.1 applies. The IM6402 and IM6402-1 are5-voltparts (4.5
to 5.5 volts) and the I M6402A is a 10-volt part (4.0 to 11.0
volts). The maximum clock frequency for the IM6402 is 1
MHz, and for the IM6402-1, 2 MHz, both at 5 volts; the
maximum clock frequency for the IM6402A is 4 MHz at 10
volts. These frequencies yield baud rates of 62.5, 125, and
250 kbits per second, respectively. Each of these parts is
available in either a plastiC DIP or a CERDIP package, each
with an operating temperature range of -40 to +85°C. The
IM6402-1 and IM6402A are also available in a CERDIP
package (with or without hi-rei processing) with an
operating temperature range of -55 to +125°C.

Comparison of 6402 Types
The IM6402 types are functionally identical to the
HD-6402
types;
however,
the
CDP6402
types
contain subtle differences. In most applications these
differences are transparent to the user, but it may be helpful
for the user to be aware of what these dissimilarities are.
Table II provides a brief description of certain signals that
are mentioned in the following discussion.
The CDP6402 types differ, functionally, from the IM6402
and HD-6402 types in the following ways.

7-94

Application Note AN-8756. 1
TABLE II - DESCRIPTION OF VARIOUS 6402 SIGNALS
6402
SIGNAL

DESCRIPTION

MR

All 6402 devices require a positive pulse on the Master Reset
input after power-up.

TRE

This output goes high when the transmitter shift register
becomes empty.

TBRl

A negative pulse is applied to this normally high input to
load data into the transmitter holding register.

1854A - MODE 0
EQUIVALENT SIGNAL
MR
TSRE

THRl

TBRE

This output goes high when the transmitter holding register
becomes empty.

THRE

TRO

This is the serial data output pin. It is high when the
transmitter is inactive and it goes low for a start bit.
The start bit is then followed by the data bits, an optional
parity bit, and a high stop bit(s).

SDO

DR

This output pin goes high when received data becomes
available on the receiver data bus.

DA

Note: This table includes the 1854A type signal names because those names are shown in the block diagram in Fig. 1.

Master Reset: Following a master reset, the IM6402 and
HD-6402 require approximately 18 transmitter clock cycles
before the TRE signal is set and before transmission can
begin. This is not a requirement for the CDP6402, in which
TRE is set on the first low-to-high transistion of the transmit
clock (TRC), and in which transmission can begin
immediately. Moreover, a master reset on the CDP6402 will
clear the receiver holding register, while on the other types
it will not.
Transmitter Timing: In all 6402 types, loading of the
transmitter (by means of a low pulse on TBRl) when it is
inactive causes the data to be "immediately" transferred
from the holding register to the shift register. When this
happens, TBRE will go high to indicate that the holding
register is empty, TRE will go low to indicate that the shift
register is not empty, and TRO will go lowto begin the start
bit. However, these signal changes do not occur at the same
time in the CDP6402 as they do in the IM6402 and HD-6402.
In the IM6402 and HD-6402, all three of these signal
changes occur as a result of the first low-to-high transition
of TRC after the low pulse on TBRL. This particular
transition of TRC is hereafter referred to as "transition X." In
the CDP6402, TBRE is set by the high-to-Iow transition of
TRC that occurs 1-1/2 cycles after transition X, TRE is
cleared by the high-to-Iow edge of TRC that occurs 1/2

cycle after transition X, and TRO goes low as a result of the
low-to-high edge that occurs 1 cycle after transition X. This
sequence is shown in Fig. 3.
Receiver Timing: In all UARTs, received data is completely
asynchronous to the receiver clock (RRC). Therefore, while
the leading edge of any given bit may occur at any point
within an RRC cycle, it will not be "recognized" until the
occurence of the next clocking edge of the RRC (assuming
that the bit meets the minimum set-up time prior to this
edge). In all 6402 types, serial data is received at the RRI
(Receiver Register Input) pin, and the clocking edge in
question is the next high-to-Iow transition of RRC. It is this
edge that is defined as the pOint of reference for the
following timing parameters. In the IM6402 and HD-6402,
the Overrun Error (OE), Parity Error (PE), and received data
(RBR1-8) will all appear on their respective output pins as a
result of the RRC transition that occurs 7-1/2 cycles (from
the reference edge) into the first stop bit. The Framing Error
(FE) and Data Received (DR) signals will appear as a result
of the transition that occurs one cycle later. In the CDP6402,
the OE signal and the received data appear as a resultofthe
RRC transition 8-1/2 cycles into the first stop bit. The PE,
FE, and DR signals all appear as a result of the RRC
transition 1/2 cycle later. This sequence is shown in Fig. 4.

7-95

Application Note AN-8756. 1

f
TRC

~

TRANSITION X

r--;

rL h

----..J

L-iL

--. !<--'su
~
A LOW PULSE

ON fiiit
OCCURS

WITHIN THIS
TIME FRAME

1\

TRO

IM6402 [

\\\\\\' ,\ il

TBRE

HD-6402

~

:\

I

TRE

TBREGOES

LOW WITH
THEAISING
EDGE OF

i'iiiiL

\

\

..

1 CYCLE ..

I'll CYCLES

~\\\\\~
1fICYCLE

\

I

-1\
92CM-42428

Fig. 3 - 6402-type transmitter timing differences.

r

REFERENCE EDGE

RRC

RRI

THE FIRST STOP BIT ]
BEGINS WITHIN THIS

TIME FRAME

~:R~~8 ---1:;::=====--=-=-=-=-=::.-;'7'h~C~Y~C~LE;'S;=======:;...::r
1M840Z
HD-6402

(
~.OR

---_-+__________________________________________-¥
1---------

RBR~~'
CDPG402 ( PE, FE, DR

8VtCYCLES

- - - - - - - - - - l..P

------+---------------------------------------------1'
1--------- •

CYCLES

- - - - - - - - - - - - 1.... 1

92CM-42423

Fig. 4 - 6402-type receiver timing differences.

7-96

Application Note AN-8756. 1
IM6403

CDP1854A - Mode 1

The IM6403 differs from ali other devices in the first
generation category in that a crystal oscillator circuit and a
selectable divider are included on-chip. The user can either
connect a crystal across the two clock input pins of the
UART or supply a clock signal to one of the pins. This
provision may eliminate the need for a baud rate generator
IC in systems where such a device is used solely to generate
a common receive and transmit clock signal for the UART.

As mentioned, the CDP1854A has two modes of operation,
ModeOand Mode 1; only ModeO has been discussed sofar.
It is appropriate to discuss Mode 1 now, between the
discussions of the first generation UARTs and the second
generation UARTs. The CDP1854A in Mode 1, while similar
in some respects to its Mode 0 configuration, is directly
compatible with the CDP1800-series microprocessor family
and, as such, is really a cross between a first generation and a
second generation UART.

Except for the oscillator/divider section, and the
corresponding frequency and baud rate specifications, the
IM6403 type is identical to the IM6402 type. The maximum
clock frequencies of the IM6403, IM6403-1, and IM6403A
are 2.46 MHz, 3.58 MHz, and 6 MHz, respectively. The
resulting maximum baud rates are 9600 baud, 13.98 kbaud,
and 23.4 kbaud, also respectively. The IM6403, IM6403-1,
and IM6403A are each available with the same packaging
options, temperature ranges, and voltage ranges as the
IM6402, IM6402-1, and IM6402A, respectively.
The differences between the IM6403 types and the IM6402
types are summarized in Table III and shown schematically
in Fig. 5. Note in Table III that the transmit clock input is
used when supplying a CMOS-level clock signal, and that
the receive clock input is used when supplying a TTL-level
clock signal. Fig. 5 shows that the TBREand DR outputs are
three-state outputs on the IM6402, but are always active on
the IM6403.

Like the first generation UARTs, the CDP1854A is a 40-pin
device with input pins for the receive and transmit clock
signals, and two 8-bit data buses. A reduced set of dedicated
output pins for status signals is also provided. Specifically,
a pin is provided for each of the following status conditions:
data available, framing error, parity or overrun error, and
transmit holding register empty. But unlike the case with
first generation UARTs, the two 8-bit buses will be tied
together in the system and, through the control of the
microprocessor, will effectively become one bidirectional
data bus. Further, a more complete set of status signals is
available via an internal register, as are the mode control
signals. The reader should recognize these as attributes of
second generation UARTs.
Other similarities of the CDP1854A, Mode 1, to second
generation UARTs include the microprocessor interface

TABLE III - DIFFERENCES BETWEEN IM6403 AND IM6402 TYPES

PIN

IM8403 w/EXT
TTL CLOCK

IM6402 w/EXT
CMOS CLOCK

IM8402

IM8403 w/XTAL

2

N/C

Divide Control

Divide Control

Divide Control

17

RRC

XTAL

External Clock Input

No Connection

Always Active

Always Active

Always Active

19

Tri-State

22

Tri-State

Always Active

Always Active

Always Active

40

TRC

XTAL

Vss

External Clock Input

z

0

S1~

u
....
-0
~z

D..

RECEIVER REGISTER
16X CLOCK

PIN 40

TRANSMITTER REGISTER

RRC

TRC

RECEIVER REGISTER

PIN 17

16XCLOCK

I

TRANSMITTER REGISTER ",
16XCLOCK

I

16X CLOCK

I

HIC

PIN 2

PIN 19

DR

PIN22
TBRE

I

}-. 3-STATE

PIN 16

DIVIDE CONTROL

I

N/C

L" DIVIDE BY 2048

H " DIVIDE BY 16
PIN19

\

DR

\

\

}

\

TORE

\
I
\

\
\

SFD

BUFFERS ARE

ALWAYS ACTIVE

PIN 22

PIN 16
SFD
IM64Q3

IM6402

92Ct.4-42433

Fig. 5 - Functional difference between IM6402 and IM6403 UART - IM6403 has on-chip 4/11 stage divider.

7-97

C

Application Note AN-8756.1
and two dedicated output pins for modem control signals.
The microprocessor interface includes one active-low and
two active-high chip selects. one register select (address)
line, a read/write select line, a data strobe, an external
status input, an interrupt input, and an inte.!!!pt request
output. The two modem control signals are CTS (Clear to
Send) and Fi'fS" (Request to Send).

CDP65C51
There are a number of manufacturers of both the 6551 type
(NMOS) and the 65C51 type (CMOS), but only the Harris
CDP65C51 offers the user the ability to operate with up to a
4 MHz receive and/or transmit clock. In fact, competitors'
parts of this type limit the user to 2.5 MHz for these clocks.
In terms of maximum baud rates, the CDP65C51 can
operate at baud rates up to 250K, whereas the maximum
baud rate ofthe competition is 156.25 kbaud. The CDP65C51
is also capable of interfacing with microprocessors having a
bus cycle time of 250 ns (4 MHz).

The CDP1854A, Mode 1, offers a flexible combination ot'
hardware and software control, and while intended for use
with the CDP1800 series of microprocessors, may be suited
for use in systems with similar timing. The block diagram of
the CDP1854A in Mode 1 is shown in Fig. 6. For information
concerning packages. temperature ranges, voltage ranges,
and maximum frequencies, refer to the Mode 0 description
presented earlier in this Application Note.

The CDP65C51 is a 28-pin device with internal registers for
transmit data, received data, commands, control, and status.
These registers are accessed via the microprocessor
interface, which consists of an 8-bit bidirectional data bus,
two register select (address) lines. a read/write select line,
an input clock (data strobe), an interrupt request output,
and two chip selects (one active high and one active low).
The block diagram for the CDP65C51 is shown in Fig. 2.

Second Generation UARTs-lndlvldual Device Descriptions

Harris offers four types of second generation UARTs: the Industry type CDP65C51 and two functional variations of that
type (the CDP65C51 A and the CDP6853), and the IM26C91.
Again, all of these devices are fabricated in CMOS technology.

In addition to an internal programmable baud rate generator
(programmable divider) circuit, the CDP65C51 also contains
an on-chip crystal oscillator circuit. The user has theoption
of either using or bypassing each of these circuit functions
in the generation of the desired l6x transmit clock.
Specifically, the user can attach a crystal to both pins of the
oscillator (XTLI and XTLO) and then either bypass the
divider (when the crystal is already 16 times the desired
transmit baud rate) orselectthe appropriate divisor. Instead
of using a crystal, the user may elect to provide a clock
signal to XTLI and then either bypass the divider or select
the divisor, as before. When a clock signal is provided to

A description for each of the above devices is provided in
the paragraphs that follow. Each description begins with a
discussion of the primary distinction associated with the
subject device and then goes on to compare the features of
that device to the "minimum set" of attributes listed in Table
I for second generation UARTs. If in Table I there is only a
general reference, or none at all, to a particular feature, that
feature will be described in detail here. In describing these
second generation devices, the emphasis will again be
placed on functionality ratherthan electrical specifications.
TRANSMITTER SECTION
u
0"
..J

I~

U

I-

t

CoPl800
INTERFACE

~

j::CI.

q; ...
ul-

-c

~z

I

Do

q;

CONTROL
REGISTER

.00.

BITS 0-3

DIVISOR

00.'
0010

BYPASS

.,00
0011

0101

0110
0111

1000
1001
1010

1011
1100
1101

1110
1111

.30.

1536
1048
'56
766
36_

..
,.

,.3
6_
_.

TRANSMIT
BAUD
RATE

BYPASS DIVIDER

32
24

RECEIVE

"

BAUD
RATE

6

CONTROL REGISTER

BIT4

FUNCTION OF Axe PIN
RECEIVER CLOCK SIGNAL INPUT (16x DESIRED BAUD RATE)
RECEIVER AND TRANSMITTER 16x CLOCK SIGNAL OUTPUT

Fig. 7 - CDP65C51 clock options.

7-99

92CM-42427

Application Note AN-8756.1
CDP65C51, the receiver and transmitter circuits must both
be either enabled or disabled, while the other parts provide
for individual software control of these circuits. Such
independent enabling/disabling of the receiver and
transmitter circuits is not a major concern, since, in most
cases, the independent control of the transmitter interrupts
is sufficient.
With respect to the RTS output, it is a simple software task
to have the CDP65C51 behave like the other parts of this
type, but the converse is not true. A common use of the RTS
output is to bring it active whenever the transmitter is
enabled and to bring it inactive whenever the transmitter is
disabled. If a character is in the process of being shifted out
by the transmitter when the disable command is given, the
transmitter does not disable until that character is
completed. In this case, RTSshould notgo inactive until the
character is completed. In all parts of this type other than
the CDP65C51, this step is taken care of automatically.
Users of the CDP65C51 must first issue the disable
command, and then, after waiting for the character to finish,
must take RTS inactive. In other words, the user simply
writes to bit 1 of the Command Register, waits for the next
transmitter-holding-register-empty interrupt, and then
writes to bits 2 and 3 of the Command Register. On the other
hanQ...!.here will be applications that require the control of
the RTS output and the control of the transmitter to be
independent of each other, especially since the RTS output
can be used as a general purpose output. The CDP65C51 is
ideal In these situations, while competitors' parts simply
cannot operate in this manner.

CHAR#n
______L__________, /

(TRANJ~I~DATE \

8N \

CDP65C51A

Ali 6551/65C51 ~s on the market provide an input pin for
a clear-to-send (CTS) signal, and all terminate transmission
if the signal at that input goes inactive. Most, if not all, of
these devices (the CDP65C51 included) take this action
immediately upon receiving such a signal transition. This
means that if a character is in th!!.J!!9cess of being shifted
out by the transmitter when the CTS signal goes inactive,
that character will be cut off. Ifthe system software does not
supervise this activity, or if external hardware is not provided,
a character could be lost. The CDP65C51A eliminates the
need for this additional hardware or software.
The CDP65C51A is identical to the CDP65C51 except that
the CDP65C51Awili not cut off aCha!!£!.er upon receiptofa
clear to not-clear transition on the CTS input. This device
may be the only part of this type in the industry that provides
this advantage. When such a transition does occur on the
CTS input of the CDP65C51A while a character is being
shifted out, the device first completes the transmission of
that character and then deactivates the transmitter circuit.
This sequence is shown in Figs. 8 and 9. Note that the
character is cut off in Fig. 8 (CDP65C51), but not in Fig. 9
{CDP65C51 A).
The'CDP65C51A is also available in three versions, the
CDP65C51A-1, the CDP65C51A-2, and the CDP65C51A-4;
ali information contained in the description ofthe CDP65C51
type applies, as well, to the CDP65C51A type.

CHAR#n+1
I

p \STopISTARTI

80

I

8,

CONTINUOUS "MARK"
I'

,

I I 8N I p ISTOplSTARTI

Bo

I

IRQ - - - - - - - - - ;

(INTERRUPT REQUEST)

NOT CLEAR-tO-SEND

CLEAR-YO-SEND

_/

eTS GOES HIGH.
INDICATING MODEM
IS NOT READY TO
RECEIVE DATA. Tx 0
IMMEDIATELY GOES
TO "MARK" CONDITION

NEXT
PROCESSOR
INTERRUPT
AT NORMAL
START BIT
TIME

PROCESSOR READS
STATUS REGISTER.
SINCE DATA REGISTER
IS NOT EMPTY, PROCESSOR

Ml..iS'T'"OEDUCE THAT

C'fl!

IS SOURCE OF

INTERRUPT

92CM- 42424

Fig. 8 - Effect of CTS

on transmitter (CDP65C51).

7-100

Application Note AN-8756.1
CH~R #n

(TRAN;~,~

CHAR,#n+ 1

/

-------L----------~'/r--~==~==~~==~===;==~,
DATAH-

I BN

I IST0-!sTARTI BO I I
B,

I

I

.LI_B_N....LI_...IIL.s_T_Op...ll~s_TA_R_T1.I_B_°--LI_B_'_ILB...J2:_ ~-..I...I_B_N...IL._p-.JIL..S_TO_PJI

I

LJU

III

(INTEARU~~QREQU-E-ST-)-------------""';I

CONTINUOUS "MARK"

7

iiiQ IS NOT ASSERTED
AGAIN UNTIL CTS
GOES LOW

NOT CLEAR·TO-SEND
CLEAR-TQ-SEND

__

i

ers GOES HIGH,
INDICATING MODEM
IS NOT READY TO
RECEIVE DATA. TxO
GOES TO "MARK" CONDITION
AFTER COMPLETE CHAAACTER
IS TRANSMITTED.
92CM-42429

Fig. 9 - Effect of CTS on transmitter (CDP65C51A).

CDP6853

TI')e CDP6853 is a MOTEL bus version of the CDP65C51
and, as such, is functionally identical to the CDP65C51,
except for the microprocessor interface. The microprocessor interface of the CDP6853 consists of an 8-bit
bidirectional data bus, a read/write select line, a data
strobe, an address strobe, an interrupt request output, an
active-high chip enable, an active-high chip select, an
active-low chip select, and two address lines that are
multiplexed with the two least significant bits of the data
bus. The address information is latched internally, under
control of the address strobe.

As the MOTEL acronym implies, this device facilitates the
interface to either a Motorola type or Intel type bus. The
technique for interfacing to a Motorola type microprocessor
bus is similar for the CDP6853 and the CDP65C51, except
that when using the CDP6853, there is no need to provide
latches for address data; see Figs. 10 and 11. To interface
the CDP6853 to an Intel type microprocessor bus, the user
should si mply feed the read enable and write enable Signals
of the microprocessor to the data strobe and read/write
select inputs of the CDP6853, respectively; see Fig. 12. The
?Ioc.k diagram for this device is similar to the block diagram
In Fig. 2; the only differences are in the microprocessor
interface signals, as described above.

TO

TO

OTHER
PERIPHERALS

OTHER
PERIPHERALS

A12
AS

CSl

cso
~

RM

t---------+------~ A/W

OS

••

iRa

IRQ

AiW t--------.....------~ Aiw

CDP65C51
UART

AS

CDI'tI805E2
MICROPROCESSOR

or
8.

CDP6805E2
MICROPROCIESSOA

07

..
I

I

AS

TO

CDP6853
OS
1iiO

UART

Interfacing the CDP65C51 to the
microprocessor (Motpro/a type bus).

I
I

02
ADl
ADO

92CS-42436

OTHER
PERIPHERALS

10 -

AS

07
87

D.

I

Rg.

I-====:::===j

OS
IAQ~

/'--------------..1\.

"r--...,CE

CDP6805E2

Rg. 11. -Interfacing the CDP6853 ro the CDP6805E2 microprocessor
(Motorola type bus).

7-101

Application Note AN-8756. 1
TO
OTHER

PERIPHERALS

A12

Cs1
CSO
CE

A8

101M
01

so
DS

Ao
W.

B085

.!Vi

ALE

AO

INTH

IRo

MICROPROCESSOR

CDP6853
UART

D7

,

I

AD7

D.
AD1
ADO

ADO

92CS-42437

Fig. 12 - Interfacing the CDP6853 to an 8085 microprocessor (Intel
type bus).

The three versions of this device are the CDP6853-1, the
CDP6853-2, and the CDP6853-4. Once again, with the
exceptions noted above, all information pertaining to the
CDP65C51 type applies as well to the CDP6853 type.
To summarize the three 'CDP' type 2nd generation UARTs:
CDP65C51

An "industry standard" device type, but
faster than any other part of that type on the
market.

CDP65C51A

Has the same speed advantages as the
CDP65C51, but with the added benefit that it
will not cut off a character in response to an
active-to-inactive CTS transition.

CDP6853

A MOTEL bus version of the CDP65C51.
Interfaces to microprocessors having either
Motorola-type or I ntel-type bus structures.

Another second generation UART offered is the IM26C91.
This device is a relatively new introduction to the second
generation UART market, and is described in the following
section.

IM26C91
The IM26C91 is a more recent development in the area of
second generation UARTs, and accordingly includes a number of new features and Improvements over some of the more
established parts.
The IM26C91 is a 24-pin device which, like most other parts
in this category, contains internal registers for commands,
mode control, status, received. data, and transmit data.
However, unlike most of the other parts, the IM26C91 also
contains two additional received-data registers, two
additional mode-control registers, two counter/timer
registers, a clock select register, an interrupt status register,
and an interrupt mask register. The additional registers
onboard the IM26C91 translate to increased programmability;the additional programmability, in turn, is indicative
of the new features and improvements associated with this

device. Alii M26C91 registers are 8-bit registers, but the two
counter/timer registers can be cascaded to implement one
16-bit counter. The registers are accessed via the
microprocessor interface, which consists of an 8-bit
bidirectional data bus, three address lines, a read strobe, a
write strobe, an active-low chip enable, and an interrupt
request output. The functional block diagram for the
IM26C91 is shown in Fig. 13.
Before continuing the discussion of the architectural and
functional features of the IM26C91, it will be helpful to
mention that there are two pins on the device that have
several possible uses. The MPO (Multi-Purpose Output)
and MPI (Multi-Purpose Input) pins each may be used for
anyone of a number of special functions, which are
described in the following paragraphs. In addition, the MPI
may also be used simplyas a general purpose input pin that
may be polled via the Interrupt Status Register of the part.
The IM26C91 contains, on-chip, both a crystal oscillator
circuit and a counter/timer circuit in addition to the
programmable baud rate generator (programmable divider)
circuit. Therefore, the user is provided with a relatively large
number of options when dealing with receive and transmit
clock generation. Basic parts in this category require a
system generated clock signal for the programmable divider;
advanced parts, like the CDP65C51 types, provide a number
of options by offering the use of either a crystal oscillator
circuit and/or a programmable divider circuit; now the
IM26C91 increases the number of options available by
providing a counter/timer circuit and more involved clock
selection cicuitry.
As with the CDP65C51, the crystal oscillator circuit of the
IM26C91 can operate from either a crystal or an input clock
signal. The crystal would be connected to both the input
(X1/CLK) and output (X2) pins of the circuit, whereas the
clock signal would be connected only to the input pin. The
output signal from the oscillator circuit is the input signal
for the programmable divider, and is also one of several
possible input sources for the counter/timer circuit. Other
possible input sources for the counter/timer circuit are the
oscillator output divided by 16, an input clock signal on the
MPI pin, or the transmitter clock itself. The signal from the
MPI may go directly to the counter/timer, or it may be
routed through a divide-by-16 circuit first.

7-102

Application Note AN-8756.1
r8/
DO·D7

",)I

~

BUS BUFFER

/

~

TRANSMIT
HOLDING REG
TRANSMIT
SHIFT REGISTER

OPERATION

RO N

>--

CONTROL

WRN

eEN

A.

AG-

RES ET

3/

I

I

ADDRESS
DECODE

R/W CONTROL

I

I

-

.

f---t
~

RECEIVE
HOLDING REG
(3)

RECEIVE
SHIfT REG

J

-

TKO

.,0

88
eR

SR

INTERRUPT

:-

CONTROL

B8

INTAN

~

I.R

~

-"

r--

~

..!!I

INPUT PIN

rS
TIMING

I

I
I
"

lelK
X2

I
t.

BAUD RATE

GENERATOR

I

CLOCK

I

SELECTORS

COUNTERI
TIMER

XTALOSC

POWER DOWN
LOGIC

I

I

.

"

"

;;I
z

~

!...

>-- I--

~

CHANGE OF
STATE
DETECTOR

.-- MPI

OUTPUTPIH

'--

fUNCTION
SELECT
LOGIC

I - - MPO

V

J

'"

~

--

r--cs;;-

i--ACR

---cTiiR

~

Vee
aND

92CL-42434

Fig. 13· Functional block diagram of tha IM26C91.

So far, the crystal oscillator, the programmable divider, and
the counter/timer circuits have been mentioned; the next,
step is to discuss the derivation of the receive and transmit
clocks from these or other circuits. The receiver and the
transmitter each have a separate clock selector. Both clock
selectors have the same four possible clock sources, but
each selector is individually programmable. Consequently,
distinct receive and transmit clocks can be generated. The
four clock sources are the programmable divider output,

the counter/timer output, the signal on the MPI pin (directly),
or the signal on the MPI pin divided by 16.lt should be noted
that either a clock signal or a crystal, with a frequency of
between 2 and 4 MHz, must be connected to the oscillator
circuit, even if the transmit and receive clocks are derived
from the MPI pin. This is necessary for operation of certain
internal circuits of the IM26C91. The clock options for the
IM26C91 are shown in Fig. 14.

7-103

Application Note AN-8756.1
THE SOURCES OF THE BAUD RATE CLOCKS FOR THE
RECEIVER AND THE TRANSMITTER ARE SELECTED VIA THE
CSR. IF THE PROGRAMMABLE DIVIDER IS TO III! USED, THE

~

...., •

ACTUAL DIVISOR WILL 8E SELECTED•

C8R(3:O)I(7:4)

r"" TO OTHER

Bx. GJ-

ON-CHIP
LOCATIONS

X1/CLK

J

CRYSTAL
OSCILLATOR

L

PROGRAMMABLE
DIVIDER

I--

1 OF 2 SETS OF
DIVISORS IS SELECTED
BVAeR BIT 7

.... ..

---

~
ACR(6:4)

MO DE

o

0

MPI Pin

o

o

0
1
1

1

Co unleT
Co unter
CounteT
Counter

0
1
0

Timer

MPIPln

Timer

MPI Pin divided b 16

1

0
0
1

Timer

Crystal or external clock

1

1

1

Timer

x l/CLK
Crystal or external ClOCk

o

0

CLOCK SOURCE
MPI in divided by 16
TXC-1 x clock of the transmitter

!!I
[;!I

oil
=1
81
°1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

ACR(7}=O

ACR(7) = 1

50
110
134.5
200
300
600
1,200
1,050
2,400
4.800
7,200
9,600
38.4k

75
110
134.5
150
300
600
1,200
1,050
2,400
4,800
1,800
9,600
19.2k

Timer

MPI-16x

Timer
MPI-16x

MPI-1X

MPI-,X

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

10F4

COUNTERI

RECEIVE
CLOCK
_ _ BAUD
SELECTOR
RATE
(CSA BITS 7-4)

TIMER

.... ~ I
~I

MODE AND CLOCK SOURCE
SELECTED BY AeR 8-4

4
10F4
L--t CLOCK
TRANSMIT
SELECTOR ~ BAUD
L--..t. (CSR
BITS 3-0)
RATE

Crystal or external clock
x l/CLK divided by 16
92CM-42539

(x l/CLK) divided by 16

Fig. 14 - IM26C91 clock options.

There are no input or output pins on the IM26C91 dedicated
solely to modem control; however, the MPI and MPO pins
can be used for that function. If these pins are not needed
for any of their other functions, the MPI and MPO pins can
be used as CTS and RTS, respectively.
To facilitate a discussion of the individual registers and
related device functionality, it is necessary to first describe
the receiver buffering operation of this device. All UARTs
contain a receiver shift register and a receiver holding
register, which combine to provide double buffering of the
received data. The IM26C91 contains two additional holding
registers that are combined with the above receiver shift
and receiver holding registers to provide quadruple
buffering of the received data. The receiver holding register
and the two additional holding registers are collectively
referred to as the receiver FIFO; the receiver holding
register itself is referred to as the "top" of the FI FO. A status
bit (RXRDY) indicates whether the receiver holding register
is full, and another status bit (FFULL) indicates whether the
entire FIFO is full. As characters are received via the
receiver shift register, they are transferred to the FIFO and
stored from the top down. A read of the receiver holding
register'always reads the top location of the FIFO. Each
character stored in the FIFO has its associated error status
information stored along with it. The user may opt to look at
the error information for each character individually, or for
one or more characters collectively. Also, the user may opt
to have an interrupt generated by either RXRDY or FFULL
gOing active.
The Command Register of the IM26C91 is used to enable or
disable the receiver, to enable or disable the transmitter, to
start or stop transmitting a break, and to control the state of
the RTS output (if the MPO is programmed to be RTS). The

Command Register is also used to reset the MR (Mode
Register) pointer, the transmitter, the receiver, the break
change interrupt bit, the MPI change interrupt bit, and the
error status bits.
The mode of operation of the IM26C91 is controlled via
mode registers MR1 and MR2, which are usually written to
sequentially. The first mode register write cycle executed
after either an MR pOinter reset or a hardware reset is
directed to MR1. As a result of this write, the pointer
increments, and the next write is directed to MR2. The MR
pOinter operates the same way for mode register read
cycles.
The MR1 register is used to select the error mode, parity
mode, type of parity, wake-up mode, character length, and
the source of the receiver interrupt. This register is also
used to specify the functionality of the RTS output for
handshaking. Either character error mode or block error
mode may be selected. In the character error mode, the
framing error, parity error, and received break status bits
are resetfor each character, so that the information provided
by these bits reflects the conditions for the current character
only. In the block error mode, errors accumulate from
character to character, and are not reset until an error reset
command is executed via the Command Register.
The parity mode options for the IM26C91 are the same as
for the CDP65C51: odd or even parity on both transmitted
and received data, a forced high or low parity bit on the
transmitted data with no parity check on the received data,
or no parity at all. However, the parity mode select bits in
, MR1 are also.used to select a special wake-up mode. In this
mode, the parity bit in each character is used not for parity,
but rather for indicating whether that character is an

7-104

Application Note AN-8756.1
address character or a data character. When an address
character is received, the RXRDY status bit is activated.
Otherwise, normal receiver operation is suspended. The'
wake-up mode is intended for use in a system composed of
a number of slave stations, each with a UART, a
microprocessor, and an assigned address character. The
microprocessor in each station examines address characters
received by its corresponding UART until its assigned
address character is received. The processor then instructs
the UART to resume normal receiver operation, and takes
any other action that may be appropriate at that time.
The character length can be 5, 6, 7, or 8 data bits per
character. A receiver interrupt can be generated by either
the RXRDY or FFULL status bit signals going active. The
state of the the RTS output is "manually" controlled via the
Command Register; however, it is also possible to program
the device to automatically bring the RTS output inactive
when the start bit of a character is received at a time when
the FIFO is already full. In this case, the RTS output will
return active when a FIFO location becomes available. This
feature may be used for handshaking by connecting the
RTS output to the CTS input of the sending device.
The MR2 register of the IM26C91 is used to select the
general mode of operation of the device, to program the
number of stop bits per character, and to specify the
functionality of the CTS input pin. The MR2 register also
provides another functional option for the RTS output. The
general modes of operation for this device are normal,
echo, localloopback, and remote loopback. The echo mode
in the IM26C91 issimilarto the echo mode in the CDP65C51,
where received characters are retransmitted serially in
addition to being available on the bus. The two loopback
modes are special modes provided for diagnostic purposes.
In the localloopback mode, the serial output of the UART is
fed back into the serial input, thereby allowing the testing of
the local microprocessor/UART circuit. In the remote
loopback mode, the parallel received data is fed into the
transmitter circuit, thereby allowing the testing of the
remote microprocessor/UART circuit and the link between
the local and remote stations. The number of stop bits may
be programmed from 9/16 to 1 bit orfrom 1-9/16 to 2 bitsfor
characters with 6, 7, or 8 data bits. For characters with 5 data
bits, the numberof stop bits may range from 1-1/16to 2 bits.
In all cases, the number of stop bits is programmable in 1/16
bit increments.
If the MPI pin is programmed as the CTS input, the user may
choose to program the device so that the tr.ansmitter checks
the CTS input before loadmg a character for transmission.
Otherwise, the CTS input has no effect on the transmitter.
When this option is selected, the transmitter always waits
for CTS to be active before initiating the transmission of a
character. This feature is intended for use in handshaking.
It was mentioned above that the RTS output may be
controlied by the Command Register, and that it may also
be programmed to respond automatically when the receiver
is full, but there is also another possibilty. Under control of
the MR2 register, the RTS output can be programmed to
deactivate automatically when the transmitter is empty.
When so programmed, the RTS output goes inactive after
transmission of the last of a string of characters or, more
accurately, after the completion of. any character when
another has not been loaded to follow it. '

The Auxiliary Control Register (ACR) of the IM26C91 is
used to select the baud rate, counter/timer operating mode,
power-down mode, and the function of the MPO pin. As
discussed, the programmable divider may be used to
generate the desired baud rate for the receiver and/or
transmitter. By programming the ACR, the user selects one
of the two sets of divisors available. When using a 3.6864
MHz clock or crystal frequency, these divisors provide
standard baud rates ranging from 50 to 38.4K,
The counter/timer circuit can be used either to count a
specified number of input clock cycles, or to generate a
square wave with a cycle time equal to a specified multiple
of that of the input clock. The desired number of cycles, or
the desired multiplication factor, is stored in the
Counter/Timer Registers by the user. The source of the
input clock for the counter/timer circuit is also selected, via
the ACR, from the listof possible sources already presented.
When the UART is not being used, it may be placed in the
power-down mode, In this mode, the oscillator is stopped
and all related functions are suspended, thereby reducing
device power consumption. The ACR can be programmed
to provide any of the following functions on the MPO pin:
RTS, the counter/timer output, the receiver clock, the
transmitter clock, a transmitter-holding-register-empty
signal, or the complement of either RXRDY or FFULL.
If the baud rate generator is to be used for generating the
receiver (transmitter) clock, then the specific divisor must
be selected via the Clock Select Register (CSR). Otherwise,
one of the other three receiver (transmitter) clock sources
must be selected, also via the CSA.
The Status Register (SR) indicates parity, framing and
overrun errors, and receiver'holding register full, receiver
FIFO full, transmit holding register empty, and receiver
break conditions.
The IM26C91 can be programmed to generate an interrupt
based on anyone or more of seven conditions, or the user
may elect not to generate interrupts at all. The seven
conditions are a change of state on the MPI pin, a high level
on the MPI pin, a change in break, transmitter shift register
empty, transmitter holding register empty, RXRDY or FFULL,
and a counter ready condition. The counter ready condition
occurs whenever the counter/timer counts the full number
of cycles that have been programmed into the
Counter/Timer Registers, or each time it reaches a multiple
of that number. The Interrupt Mask Register (IMR) allows
the user to enable or disable each of these seven sources
individually; the Interrupt Status Register (ISR) contains a
bit representing each of these seven conditions.
The IM26C91 is a TTL compatible device available in a
24-pin plastic narrow-body-DIP or a 28-pin PLCC package.
It is a 5-volt part (±10%) and has an operating temperature
range of 0 to +70·C. The maximum frequency for the 16x'
receive or transmit clock is 2 MHz, which translates to a
baud rate of 125 kbaud. A 1x mode is also available. In this
mode the device has a maximum clock frequency of 1 MHz,
and since this clock is not divided by 16 to generate the
baud rate, a maximum baud rate of 1 Mbaud can be
achieved.
The architectural and functional features of the CDP65C51
types and the IM26C91 are compared In Table IV.

7-105

Application Note AN-8756. 1
TABLE IV - ARCHITECTURAL AND FUNCTIONAL FEATURES OF THE CDP85C51 TYPES
AND THE IM28C91 TYPE COMPARED
CDP85C51

IM28C91

28-pin plastic DIP
Packages

Modem control signals
(handshaking)

28-pin ceramic DIP

24-pin Narrow-Body-DIP

28-pin plastic small outline DIP

28-pin PLCC

Inputs: CTS, DCD, DSR

The MPI pin can be selected to function

Outputs: RTS, DTR

as CTS and the MPO pin as RTS.

Motorola type (65C51)
1 active-high chip select
1 active-low chip select

Intel type

Microprocessor Interface

1 active-low chip enable
. Motorola or Intel type (6853)
2 active-high chip selects
1 active-low chip select
1 hardware interrupt (pin), and 1 software

Interrupts

1 hardware Interrupt pin. Seven status

interrupt (status bit). Four status bits

bits indicate source. Each source is

indicate source. Interrupts for receiver

individually maskable.

and transmitter are individually maskable.
RxC can be selected to be a 16x clock
Clock outputs

The MPO can be selected to output lx or
16x the receiver or transmitter clock, or

output.

the counter/timer output.
Transmitter:

Clock sources

Transmitter:

Use either a crystal or a clock signal,

Use either a crystal or a clock signal to

and then either program or bypass the

feed the oscillator, and then either the

Internal divider. (This generates a 16x

programmable divider (generates a 16x

clock for the transmitter.)

clock), orthe counter/timer (any
multiple); or use the MPI to supply a lx

Receiver:
Use the transmitter clock
(from any source) or a 16x
clock signal on RXC.
Max. baud rate

or 16x clock.
Receiver:
Same options as transmitter.

250 kbaud

125 kbaud

None

can be the MPI, the transmitter clock, or

with 16x clock
On-board 18-bit counter/timer. The input
CounterlTimer

the oscillator output; the output can be
the MPO or the receiver or transmitter
Receiver buffering
Diagnostic
loop back
Wake-up mode

Double

Quadruple

None

Automatic (internal) local and remote

(Must use external components.)

loopback.

None

Able to look for a specific character. (To

1,1.5, or 2

9/16 to 2, in 1/16 bit increments.

be used as a means for slave selection.)
Programmability
of stop bits

7-106

Application Note AN-8756.1
Related Devices
Harris Semiconductor also offers the ICL232, +5V Powered
Dual RS-232 Transmiter/Receiver, and the IM4702/4712
Baud Rate Generator, ICs. The ICL232 replaces 1488 type
transmitters, which require both +12V and :'12V power
supplies, and 1489 type receivers. Consequently, users can
implement entire data communication systems that require
only a single 5V supply voltage. The IM4702/4712 provides
16x clocks for first and second genertion UARTs that do not
have internal baud rate generators.
Summary
A wide variety of first and second generation UART devices
are offered. Designers can choose the appropriate type of

UART for a particular system based on whether the system is
more hardware or more software oriented, and can then
chose the specific UART device that provides the desired
functionality for that system. In addition, Harris
Semiconductor offers a number of other data communication
ICs, as well as an entire array of product lines that include
many other "general use" devices that are also needed in
data communication systems. These product lines include
microprocessors/microcomputers and peripherals, memory
ICs, high speed logic devices, linear ICs, and discrete/power
components, and together these devices offer the data communication system designer a complete integrated solution.

7-107

Harris Semiconductor

-

----------------------------------------------------------------------------------------------------------------------------------------------

User's Guide to the CDP68HC68T1
Real-Time Clock
The CDP68HC68T1 Real-Time Clock provides time and
calendar information, a 32-byte static RAM, and a three-wire
serial peripheral interface (SPI bus) that allows simple shiftregister type clocking to write to or read from the RAM or
clock registers and counters. The CDP68HC68T1 operates
at 3 to 6 volts over a temperature range of -40 to 85°C. It is
packaged as a 16-pin dual-in-line in plastic or ceramic, and
is also available in a 20-pin small outline plastic package
(SOP). The functional block diagram is shown in Fig. 1, and
the terminal assignment diagrams in Fig. 2; Appendix A
defines pin functions. Fig. 3 shows the real-time clock interfaced to an MPU. (This Note assumes a familiarity with the
contents of the CDP68HC68T1 Data Sheet. ')

by D. J. Derkach
elK OUT

16

CiiUii
1liT

VDD

"

XTAL OUT

SCK

13
12

XTAL IN

I'

MOS:r

MISO
CE

"

ID

"BATT
'1SYS

LINE

POi
PS.

VSS
TDP

VIEW
92C$-38052

CLOCK
OUT
CONNECT XTAL

CLKour
}

CPuR

OR EXTERNAL SIGNAL
,«mTIMEBASE
ALWAYS OSCILLATOR

l

13 BATT =~:~~:~yL:~~NNECT
TO Voo PIN

CDPtI.HCtlT1

OVERVIEW OF FEATURES

VSYS

INTERRUPT

Time and calendar: Seconds, minutes, hours, day of week,
date, month and year (including auto leap year), and 12 or
24-hour operation with AM/PM indicator are available. Information is in BCD format.
Control and status registers: Included are two control registers, one for configuring the clock and one to enable other
functions, such as interrupts. A status register is available to
monitor function operation.

"I[~

BUS

DATA IN

MOSI

DATA OUT

MISO

CHIPI'!NABLE

TlE TO HIGHEST

DC POTENTIAL
POWERSEN'E
OR 50110 Hz TIMIEBASE

SCI<

,..

POW£R SUPPLY
ENABLE SIGNAL
FOR POWER CONTROL

Fig. 2 - CDP68HC68Tt t 6 lead package terminal assignments and
functions.

SERIAL
INTERFACE

Fig. t. - CDP68HC68T1 functional block diagram.

January 1988

AN-8761.1
7-108

Application Note AN-8761.1
the CDP68HC68T1 samples the voltage level at the VSYS pin
at the end of POR (power-on-reset, pin 10). Vsys is normally
tied to the highest dc potential in a single supply system, so
thatthe voltage at this pin isa logic high in this mode, and in
a typical battery-backed system, a logic low.

SYSTEM
VOLTAGE

~II~_~--r--------.--t~-_+..

Fig. 4 - CDP68HC68T1 outputs.
Fig. 3 - The real-time clock interfaced to an MPU.

Serial bus: Provided are data in, data out, and clock input
plus chip enable pins to shift data in and out serially, most
significant bit first. The serial clock frequency range is from
dc to 2.1 MHz (at a Voo of 4.5V). Data is transferred in bytes.
The first eight bits shifted in after the chip is enabled are
always clock or RAM address and data direction information. Subsequent clocks transfer data with address autoincrementing.

Single supply: Both power pins and VSYS are tied together,
as shown in Fig. 5. At the end of power-on-reset, the voltage
on VSYS is a logic high, and the single supply mode is
selected; the outputs are enabled and the real-time clock is
fully operational. In this mode, if VSYS subsequently goes to
a logic low, the CPUR pin is set low.
.../

::.]11

Memory-map: The clock counters and registers are addressed at locations 20 to 32H when reading, and AO to B2H
when writing. The RAM is written to at addresses 80 to 9FH
and read from at 00 to 1FH. (The most significant bit determines data direction.)

POrt

vsvs

I

Other Features
Power loss detection begins with loss of ac signal at line pin
11. The loss activates an interrupt signal at pin 3 and sets a
status register bit.
In the power-down/power-up circuitry, a power down instruction disables outputs and the serial bus. A change of the
VSYS voltage at pin 12 or an interrupt activation terminates
power down.
In the alarm circuit, any combination of seconds, minutes,
or hours activates interrupt output pin 3.
The timebase can be external-signal/external-crystal set at
1+,2+, 4+MHz, 32+kHz, or 50/60 Hz at the line input pin.
The battery pin always powers the on-board oscillator, and
in the battery back-up mode, the entire device.
Three independent interrupt sources include power loss
detection, 15 periodic signals, and alarm.

PC POWER

CONTROL

Fig. 5 - CDP68HC68T1 in single supply circuit.

Battery back-up: Fig. 6 shows a system in which the battery
is installed before the main power is supplied. At the end of
power-on-reset in this circuit, the voltage on Vsvs is a logic
low, and the battery back-up mode is selected. The three
outputs are held low and the CE disabled until the power is
turned on and the voltage on Vsys rises to a threshold level
(about 0.7V) above VBATT. When this occurs, the clock circuit
becomes operational. In this mode, the outputs follow VSYS,
and if VSYS falls below a certain threshold level above VB1iTT
(VSYS < VBATT + O.7V), the outputs are set low.

System auto-sensing is provided to configure either single
supply or battery back-up operating modes.
In addition, in the CDP68HC68T1, the first time-up bit is set
in the status register, and a watchdog timer supplies the
reset pulse if the circuit is not toggled periodically. There
are 2.2 volts of minimum timekeeping voltage, and seven
. buffered clock output signals are provided.

:]11
ISOLATING
DIODE

'00

DETAilS OF FEATURES

'00

CPP68HctlT1

CPiJif--'+--.jAEUT

Battery Back-Up and Single-Supply Modes
Three CDP68HC68T1 outputs interface with a processor or
control system power, as shown in Fig. 4. They are the PSE
(power supply enable), the CPUR (reset to CPU), and the
ClK OUT (clock out) outputs. Since the real-time clock can
operate from battery power alone, these outputs should be
held low in an unpowered system. To assure this condition,

7-109

.
t

POWER
CONTROL

Fig. 6 - CDP68HC68T1 in circuit equipped with battery back-up.

Application Note AN-8761.1
I

Power-Down Operation

I

A power-down functional diagram is shown in Fig. 7; timing
diagrams showing outputs controlled by VSYS, interrupts,
and the power-down instruction are shown in Fig. 8.

--=l--~
~ --~

.---~--,--f
1

PSEI--l

"5YS

CPuR-f

TO SYSTEM
POWER CONTROL

FROM SYSTEM

L':SYS
MOS:I.

REAL-TIME CLOCI(
CDP68HC68TI

Fig. 10 - Power-up functional diagram (initiated by a rise in voltage
on the V SYS pin).

MUD

lINSTEE~~kcE
REAL-TIME CLOCK
CDPeSHce8TI

Power down can also be terminated by any of the three
interrupts. Therefore, when power down is invoked, either a
change in the VSYS voltage as described or an interrupt activation caused by the alarm, power sense, or periodic signal
terminates power down and sets the real-time clock circuit
operational again.

oP"

COP680502

Fig. 7 - Power-down functional diagram.
SINGLESUPPLV

'O~L----'I_ _ _ _-'-_ _ __
I

CCK

0".:/1111111111111
I

mrm
I

I

/O~

orr

A typical use of the above power-down capability might be
in a system where power is controlled by a CPU. In this
battery driven system, possibly a data collection system, the
power would only be on when data is to be collected. Once
this occurred, the CPU would issue a power-down instruction and use an alarm or periodic interrupt to terminate
power down and allow data collection to initiate.

_ _- ._ ___

rrnmm IIIITIIIT

I

Automatic Battery Switching

I

c;u;;~~

TNT

J

I

,

INT

VBATT always powers the oscillator section of the
CDP68HC68Tl to assure a stable voltage source and to
avoid oscillator frequency changes. However, this function
also powers the rest of the real-time clock when the main
power fails. It performs this necessary function by comparing the voltages on the VSYS and VBATT pins. Regardless of
the operating mode, either single or battery back-up, whenever the voltage on the VsyS pin is less than VBATf + 0.7V,
VBATf connects internally to the Voo pin.

I

L.:ESE/----tr------

I

I
I
I
".~~
I
L pow':11~WN j
I

Fig. 8 - Timing diagram showing outputs controlled by
interrupts, and power-down instruction.

VSYS>

Power down is initiated by writing a 1 into bit 6 of the interrupt control register. The three outputs are set low during
power down and the CE is disabled. If VSYS falls to a logic
low and then goes to a logic high in the single supply mode,
power up occurs, and the circuit becomes operational. The
three outputs are enabled and serial data transfers can
occur. If power down is initiated in the battery back-up
mode, Vsys must fall to less than VBATf + 0.7V and then rise
above that value to power-up the circuit.
Fig. 9 shows a power-up functional diagram initiated by an
interrupt signal. Fig. 10 shows a power-up functional diagram initiated by a rise in voltage on the VSYS pin.

This feature is generally used in the battery back-up mode
to allow the real-time clock to operate if system power is
lost. For example, in Fig. 11, if VBATf is 3 volts and VSYS 5
volts, the p-channel transistor at the VSYS input (01) is
turned on. After two signal inversions, the p-channel transistor between Voo and VBATf (02) is turned off, since its gate is
at a logic high, and Vsm is disconnected from Voo. When
the voltage at VSYS in the CDP68HC68Tl falls below 3.7
volts, the Vsys input transistor (01) is turned off and the
connecting transistor (02) is turned on, connecting VBATf
and Voo. In most battery-backed designs using the
CDP68HC68Tl, an external diode is required to isolate the
Voo pin from the main dc supply when power fails and the
battery voltage connects to the Voo pin.
Voo

VBATT

'"

~
D'

~

Yv.,~",,,

REAL-TIME CLOCK
CDP68HC68T1

Fig. 11 - Automatic battery-switching circuit.

Fig. 9 - Power-up functional diagram (initiated by interrupt signal).

7-110

Application Note AN-8761.1
Table 1- Static electrical characteristics of the CDP68HC68T1.
STATIC ELECTRICAL CHARACTERICS at TA = -40 to +85°C, Voo = VBATT = 5 V ± 5%, Except as Noted
LIMITS
ITEM

CHARACTERISTIC

CONDITIONS

CDP6BHC68T1

1

2

3

Quiescent Device Current

IOD

Output Voltage High Level

Vo><

-

Output Voltage Low Level

VOL

Output Voltage High Level

VOH

= -1.6 rnA, VDO = 4.5 V
10L = 1.6 rnA, Voo = 4.5 V
IOH :510 pA, Voo = 4.5 V

Output Voltage Low Level

VOL

10L:5 10 pA, Voo = 4.5 V

Input Leakage Current

IOH

-

liN

3-State Output Leakage Current

lOUT

Operating Current#
(10

+ Ib) Voo =

32 kHz

V. = 5 V

1 MHz

Crystal Operation
4

2 MHz
4MHz
32kHz

Pin 14
External Clock (Squarewave)#
(10

1 MHz

+ Ib) Voo = V. = 5 V

2 MHz
4 MHz

Standby Current'
5

32kHz

Ib

MAX.

-

1

10

3.7

-

-

4.4

-

±10

-

O.OB

0.1

-

10

Input Voltage (Line Input Pin
Only, Power-Sense Mode)

11

VSys>V.
(For V. Not Internally
Connected to Voo)

12

Power-On Reset (P<5R) Pulse Width

~ypical values are for T. = 25°C and nominal

1.2
0.024

0.1

0.12

0.2

0.24

0.4

0.5

rnA

25

10

12

pA

-

2

pF

-

-

-

+2

JJS

-

0

10

12

-

-

0.7

-

100

75

-

32 kHz

9

1
0.02

-

Ib

C 'N

0.84

-

Crystal Operation

1" t,

0.6

0.7

4MHz

32kHz

Input Capacitance

0.5

pA

-

=3 V

Maximum Rise and Fall Times
(Except XTAL Input and POR PIN 10)

±1

-

2 MHz

8

0.1

1 MHz

Crystal Operation

Standby Current#
V.=2.2V
Crystal Operation

V

-

-

Operating Current'

7

0.4

2 MHz

1 MHz
4 MHz

6

pA

20
200
300
500
10
la
25 15
O.OB 0.15
0.15 0.25
0.3 0.4

V.=3V

Voo = 5 V, V.

UNITS

TYP.-

MIN.

V,N = 0, T.

= 25°C

-

250
360

pA

600
10

la

30

20

0.1 O.lB
O.lB 0.3

rnA

0.36 0.5

V,

V

ns

VDD.

#Clock Out (Pin 1) disabled, outputs open-circuited. No serial access cycles.

Static Electrical Characteristics and Memory-Maps

Table I lists the static electrical characteristics of the
CDP68HC68Tl. Note that the maximum limits apply over
the full operating temperature range; typical values are
observed at room ·temperature. (The paragraph numbers
that follow refer to the Item numbers in the left column of
Table I.)
1. Quiescent device current is the current drawn when the
circuit is in a total static state with the oscillator nonfunctional. All inputs are terminated and the outputs unloaded.
2. The next four rows list the output voltages under two
conditions: when the device is sinking or sourcing a TTL
load of 1.6 milliamperes, and under a lightly loaded condition such as can be expected in a CMOS system. The clock
circuit outputs swing very close to the rails.

3. Input leakage current is essentially a measure of the input
diode protection leakage, because of the high impedance
inputs. The output leakage is a measure of the current at
the MISO pin.
4. Below the leakage values are the operating current specifications. The first four rows list the operating currents
when the battery and Voo pins are both at 5 volts. The next
four rows show the appreciable current drop under the
same conditions when an external signal is driving the realtime-clock's oscillator section.
5. Standby current at 3 volts occurs in the battery back-up
mode where, in a typical situation, the main power fails and
the circuit is powered entirely by the battery.

7-111

Application Note AN-8761.1
6. The next four rows indicate the current consumption at
both the Voo and VSATT pins for the four operating frequencies at two different supply voltages.
7. This entry lists the minuscule current drain that can be
expected under timekeeping-only conditions when the realtime clock is powered at its minimum standby voltage.
8. This item notes the capacitance at room temperature for
the input pins.

9. This is the specification for the maximum rise and fall
times, with the exception of power-an-reset and XTAL input.
The XTAL input signal can take considerably longer to
change levels under 32-kHz operation.
10. The line input pin can accept a much higher voltage
than Voo when power sense is selected. With a Voo of 5
volts, an ac voltage of 10Vp-p at 60 Hz at the line pin swings
the voltage centered at Voo to the typical high specification
of 10 volts and down to 0 volts.
11. The automatic battery switching circuit (Fig. 11) connects the two power supply pins if the condition VSYS >
VBATT is not met.
12. The final specification listed is the power-an-reset pulse
width. This pulse can be designed, with the proper RC circuit, to be considerably longer than the specified requirement in systems where longer reset times are required of
the clock circuit to allow the oscillator crystal time to
stabilize.
Fig. 12 shows the address map used in accessing the various clock registers and RAM locations. Table" lists examples of the BCD code expected when the clock counters are
read.
Fig. 13 is a programmer's model of the CDP68HC68T1
showing its RAM and clock locations. The values shown
ignore the read or write data direction bit. For example, if

--

0

location 00 in the RAM is to be written to, the first byte
shifted in serially after chip enable is activated is SOH, with
the following byte the data to be entered. If the same location is read, the first byte shifted in is 00 after CE is activated, with the next eight clocks at the SCK pin shifting out
the data in location 00. 2
Clock/Calendar
Clock/calendar data are held in seven write/read counter/
registers. The registers are pulsed by the 1-Hz input from
the prescaler. The prescaler is driven by the on-board oscillator, which can be used with an external crystal or driven at
the XTAL-in pin by an external signal. The 1-Hz input can
also be derived from a 50- or 6o-Hz input source connected
to the line input pin. T.he time/calendar counters are
accessed at locations 20 through 26H. Seconds, minutes,
and hours (with 12 or 24-hour selection and an AM/PM
indicator that toggles every 12 hours) are available for the
time counters; day of week, date, month, and year comprise
the calendar section. Data in the counters are in BCD format, with the hours counter also utilizing bits for 12124-hour
and AM/PM features. Incrementing of the address beyond
the interrupt control register at location 32 causes the circuit to wrap to 20H.
RAM
The CDP68HC68T1 incorporates a static 32-byte RAM
located at addresses 00 to 1FH. Transmission of the address/
control word with bit 5 low selects RAM access. Bits 0
through 4 select the RAM location. After incrementing to 1F,
the RAM wraps to 00.
Alarm
When enabled by the setting of bit 4 in the interrupt control
register, the alarm activates the interrupt output. At the
same time it sets bits 1 and 3 in the status register when the
. values in the seconds, minutes, and hours counter match

$00

32 RAM LOCATIONS

r,w $20
r,w $21

32

SECONDS

33

MINUTES

34

HOURS

35

DAY OF WEEK

36

DATE

r, W $24
r,w $25
r,w $26

r,w $22
r,w $23

37

MONTH

31

$1F

38

YEARS

32

$20

39

NOT USED

40

SEC ALARM

W

$28

41

MIN ALARM

W

$29

42

HRSALARM

W

$2A

43

NOT USED

$2B

44

NOT USED

$2C

45

NOT USED

$2D

46

NOT USED

$2E

47

NOT USED

46

STATUS REGISTER

$3F

49

$55

50

r,w $31
INTERRUPT CONTROL REGISTER r,w $32

CLOCK/CALENDAR
50

$32

51

$33

13 BYTES UNUSED

63

-- -85

r = readable

TEST MODE

7-112

$2F

r

CONTROL REGISTER

writable
Fig. 12 - Address map used in acceSSing the various cloak registers and RAM locations.
W=

$27

82CS-3I051

$30

Application Note AN-8761.1
Table II - Clock/calendar and alarm data modes.

ADDRESS
LOCATION (H)

FUNCTION

DECIMAL
RANGE

BCD DATA
RANGE

20

Seconds

0-59

00-59

18

21

Minutes

0-59

00-59

49

22

' Hours
12 Hour Mode

1-12

81-92 (AM)
A1-B2 (PM)

A3

Hours
24 Hour Mode

0-23

00-23

15

23

Day of the Week
(Sunday =1)

1-7

01-07

03

24

Day of the Month
(Date)

1-31

01-31

29

Month

1-12

01-12

10
85

25
Jan

BCD DATEEXAMPLE

=1, Dec =12

26

Years

0-99

00-99

28

Alarm Seconds

0-59

00-59

18

29

Alarm Minutes

0-59

00-59

49

2A

"Alarm Hours
12 Hour Mode

1-12

01-12 (AM)
21-32 (PM)

23

Alarm Hours
24 Hour Mode

0-23

00-23

15

•• Alarm hours, Data Bit 05 is "1" for P.M. and

-Example: 3:49:18, Tuesday, Oct. 29, 1985.

"0" for AM. in 12 hour mode.

*Most significant Bit, 07, is "0" for 24 hours, and "1" for 12 hour mode.

Data Bit 05 is "1" for P.M. and "0" for A.M. in 12 hour mode.

Data Bits 07 and 06 are DON'T CARE.

the values in the seconds, minutes, and hours alarm latches.
These alarm latches are located at addresses 28 through
2AH. To prevent a false interrupt from occurring when
setting the time counters, the alarm should be disabled in
the interrupt control register. This precaution is not required
when setting the alarm latches.
After an alarm activates, the status register must be read to
set the interrupt pin high. The alarm latches are write only.
When an interrupt occurs, it is important to note that, for a
true alarm indication, the status register must be read before
the interrupt control register is loaded again.
Control and Status Registers

The operation and functions of the real-time clock are controlled by the selected values in the read/write clock control
and interrupt control registers located at addresses 31 and
32. Note that both registers are cleared by the power-onreset signal at pin 10. Therefore, when power is first applied,
4-MHz crystal operation is selected with the clock-out set at
the crystal frequency. All interrupts and the watchdog
circuit (described below) are also disabled.
The status register is also cleared, with the exception of the
first-time-up bit. This register responds to interrupt and
watchdog activations by setting indicating bits. With the
exception of power sense, these bits are cleared when the
. status register is read.
Watchdog Circuit

When bit 7 in the interrupt control register is set, watchdog

operation is initiated to guard against a runaway program. If
the CE pin is not toggled periodically, without an accompanying clock pulse, as shown in Fig. 14, a reset pulse is
output at the open drain CPUR output pin, and bit 6 is set in
the status register. The procedure to re-enable the watchdog involves reading the status register and then setting bit
7 in the interrupt control register.
Interrupts

There are three sources of interrupts: the power sense, the
alarm, and the periodic signal. Appropriate bits are set in
the status register for identification. The status register must
be read to reset the open-drain interrupt-output-pin high if
any of these interrupt sources activates. The status register
read resets the alarm, periodic signal, and interrupt-true
bits. The power-sense interrupt bit remains set, if the power
sense failure remains active, until the interrupt control regiSter is written to with a low in power sense bit 5. To re-enable
the power sense, this same bit must be set high again.
When the alarm is used to generate an interrupt, a debounce
time interval occurs before the interrupt signal and alarm bit
is set in the status register. This is not a concern when only
the alarm is used, but may be when there are concurrent
interrupts; that is, when two or more interrupts are enabled
and all activate at the same time. The debounce times are
30.5 microseconds when 32+kHz and 1+MHz are used as
the time base, and 15.3 microseconds and 7.6 microseconds
for 2+ and 4+MHz operation, respectively. After the delay
times noted, the alarm interrupt activates again.

7-113

Application Note AN-8761.1
PROGRAMMERS MODEL - CLOCK REGISTERS

I

HEX ADDRESS

I

NAME

WRITE/READ REGISTERS
DB7

DBO

TENS 0-5

SECONDS (00-59)---

00
TENS 0-5
01
DB7, 1 =12 HR, 0 =24 HR
DB5 = 1 PM, 0 = AM
HOURS (01-12 OR 00-23)

12
PM/AM
HR. X TENS 0-2
24

02

X

03

X

X

SUNDAY = 1
DAY OF WK (01-07) - - -

X

01-28)(DATE)
(29
DAY OF MONTH
~~

TENS 0-3
04

JAN = 1
MONTH (01-12)- DEC = 1205
YEARS (00-99) - - - 06
X

6

5

4

3

CONTROL-----------

2

11
INTERRUPT---------

7
12

WRITE ONLy REGISTERS

08

TENS 0-5

UNITS 0-9

ALARM SECONDS (00-59) -

09

TENS 0-5

UNITS 0-9

ALARM MINUTES (00-59) -

x

OA

PM/AM
TENS 0-2

ALARM HOURS (01-12 or 00 =
PLUS AM/PM IN 12 HR. MOD
PM = 1,AM = 0

UNITS 0-9

READ ONLY REGISTER

10
NOTE:

STATUS

X = DON'T, CARE WRITES
X = 0 WHEN READ

6

7
07

RAM DATA BYTE

06

1

5 BIT4

2

3
03

1 05 1 04 1

1

02

1

HEX ADDRESS 00-1F

Fig. 13 - Programmer·s model of the CDP68HC68T1.

7-114

01

1

0

II
DO

92CM-38059

Application Note AN-8761.1

r

1_

Sr:RYICE+SERVICE

TIME

.

TIME

I

power loss is valid or that a transient glitch occurred and
power is back again.

J

e,~

Min.

XTAL

60 Hz

50 Hz

Max. Min.

-

If, after an interrupt, a monitoring of the status register indicates that the signal at the line input pin has returned (bit 2
= 0) and that a momentary glitch has occurred, the power
sense can be re-enabled by writing a logic low to bit 5 in the
interrupt control register, the power sense bit, and then writing back a logic high to the same location. If several reads
of the power sense interrupt bit in the status register after
an interrupt indicate that a power failure has indeed
occurred (bit 2 = 1), appropriate action can be taken to save
the necessary data, perhaps in the RAM.

Max.

Min.

Max.

-

7.8ms

Service Time

-

10ms

Reset Time

20

40ms 16.7 33.3ms 15.6 31.3ms

8.3ms

Fig. 14 - Watchdog waveforms, and reset and service times.

Power Sense

A prime feature of the real-time clock is its ability to sense
an imminent power loss and flag the CPU by activating an
interrupt signal, Figs. 15 and 16. The crystal oscillator must
be in operation to supply the required timing signals.

1"
"

I

WHENS1
CLOSES

Fig. 15 - Power sense application. Power sense is generated when
S, is closed. Interrupt is activated if power sense is
enabled and line pin remains at Voo longer than 2.68
milliseconds.

In a circuit like the one in Fig. 3, for example, and depending on the supply load at the time of the power failure, the
rectified dc level can take several milliseconds to fall to a
value at which the CPU and system operation are affected.
During that time period, the CPU can employ the necessary
housekeeping instructions to prepare for a subsequent reset.
With power failing, and the clock circuit operating in the
battery back-up mode (similar to Fig. 3, and Fig. 6, where
the battery was installed before system power was applied).
a power-down instruction disconnects the serial interface
and places the reset, clock out and PSE pins low to assure
an orderly power-down situation.
If the power-down instruction is not issued, the outputs are
set low anyway as the voltage on the VSYS pin falls to a voltage less than VSIUT -0.7V. However, in this situation, the
CPU and other system components may behave erratically
as VOD falls. Using the power sense function to flag the CPU
before the voltage falls to a level that affects the system
allows the system time to prepare for the power loss and
initiate an orderly power down.

The line input pin is used for power sense, Figs. 15 and 16.
To enable the power sense function, a high is written into
bit 5 of the interrupt control register; the input to the 50/60Hz prescaler is disconnected. The input circuit consists of
two quasi-clamps (saturated transistors) that limit the voltage swings at the line input pin and two threshold detectors that sense whether the input voltage level is outside the
limit ±0.7V + Voo. The clamps and detectors are only
connected when power sense is enabled; when power
sense is disabled, the line input pin is the input to the
Schmitt triggered 50/6o-Hz time base circuit.

(a)

,..----,

I

---I

I

I

CPU

I

I

CDP6805D2

f.---l------I
GENERAL FORMULA "'MAX ~ ~ WHERE w - hi
SIN",!,
".'.32mB
\/, ~'.5V

Fig. 16 - Circuit demonstrating power sense function.

"'p_p' 2\YMAX)

In operation, as long as the line input is Voo ±0.7V, no power
failure is indicated, and an interrupt signal is not generated.
However, if the voltage at the line input pin falls below this
threshold for a minimum of 2.68 milliseconds to a maximum
required period of 4.64 milliseconds, Fig. 17, a power sense
interrupt activates the interrupt output pin and bits 2 and 3
in the status register are set. When the status register is read
after a power sense interrupt, the interrupt true bit 3 and the
interupt out pin are reset. But the status register power
sense interrupt bit is connected internally to the nearest
point in the input detecting logic before the latched power
failure signal, so that subsequent status register reads
provide and immediate level-sensitive indication that a

EXAMPLE@60Hz:

VMAX·

Sl~~t·· SiNIan'~~.32. 10-3) - 3.14 V

Vp-p"3.14(2)·S.2BV
MINIMUM VOLTAGE REQUIRED TOJiQI
ACTIVATE INTERRUPT OUTPUT SIGNAL.

(b)

Fig. 17 - Power sense operation. (a) Power sense threshold
detectors sense loss of ac signal. Signal must pass
through points A and B faster than 2.64 milliseconds to
avoid a power sense activation. (b) Minimum peak-to-peak
voltage calculation (must be >3V) and a sinewave voltage
waveform assuming a threshold-plus margin of 1.5V.

7-115

Application Note AN-8761.1
Line Input Signal
As explained above, the power sense operation is centered
around Voo. As long as the voltage at the line pin is within
the limits of Voo ±0.7V, the power sense is not activated.
One way to make use of this function istoapplyan ac signal
(capacitively coupled) to the Voo-centered line pin and keep
the transitions of the ac in the Voo threshold area less than a
minimum of 2.68 milliseconds. For the same f~equency, a
larger-amplitude signal passes through the threshold area
in less time. At 60 Hz, allowing for a threshold margin, a
minimum of7volts (and a recommended value of 10Vp- p ata
Voo of 5 volts) sets up the power sense function before it is
enabled.
Fig. 18 shows a circuit that can be used to couple the ac
into the line pin. The values of Rand C depend on the frequency and the amplitude of the driving ac signal. The
capacitor arui the resistors form a voltage divider for the ac
signal. The time constant should be as short as possible to
allow the power sense to generate the interrupt as soon as
possible, but the smaller the capacitance value, the greater
the input amplitude needed to generate the input signal
across Rune. This statement implies that larger ac driving
signals are preferred for power sense operation. Higher
input frequencies require smaller amplitude swings to avoid
staying in the line input threshold area too long. When the
ac fails, an interrupt is generated after the external time
constant plus the internal delay of 2.64 to 4.64 milliseconds.
YDD

"

The first byte shifted in after CE becomes active is always
the address/control word, with the most significant bit determining data direction. For example, if RAM location 00 is to
be loaded with data 55H and then read out, the procedure
would be to activate CE and shift in 80H followed by 55H.
To read the data, the chip enable is deactivated, then activated, and 00 is clocked in. The next eight clocks shift out
data 55H at the data out pin, MISO. Note that the MISO pin
is only active when reads are performed. If an I/O interface
is used, as in Fig. 20 , only one I/O pin can be used for the
data in/data out function. Fig. 21 shows another way to
interface to the real-time clock circuit using four I/O pins on
the MPU. Appendix B lists the bit-bang software for a
CDP6805 system interface for this circuit.

I
'"

t

RESET

INT

r-J.--,pu

c.

u.

s"'

,m
,m

MISO
MOSI

W

He68T,
MOS. - MASTER OUT SLAVE IN (DATA IN)
MISO _ MASTER IN SLAVE OUT (DATA OUT)

Fig. 20 - Real-time-clock/MPU interface using three I/O lines. MISO
is tristated until the reads are required. Input pin must be
set for input during that time.

A
LINE

20K

V ,~30Yp

/'\

••
@60Hz

INPUT SIGNAL

""n
-_-'LJf--''--'-3.L,

SET-UP

VOD" +5 V

POWER SENSE ON

POWER SENSE DISABLED

Fig. 18 - Setting up the power sense.

Fig. 21 - Real-time-clock/MPU interface using four I/O lines. MOSI
is master-out-slave-in (data in), MISO is master-in-slaveout (data out).

Data Protocol and Connections
Fig. 19 shows the edges where the CDP68HC68T1 latches
and shifts data. The full 8-bit data word is transferred internally in the circuit on the next edge after the required clocks
are shifted in or when CE goes inactive at that time. For
example, written RAM data would be latched in the selected
location on the next edge after the 16th clock latching edge
if this was the first write data after the real-time clock circuit
was enabled. The 16th clock latching edge comprises eight
clocks for the address/control word and eight clocks to shift
in the data.

CPOL-'

{

'

t"[h}=IIFT
's,\ViraNl L

''"

MOSI:~

NOW ~~g~o~~~~U\Ht:,~S csgJi.:oI'1t~GJSTER
Fig. 19 - Serial RAM clock (SCK) as a function of MCU clock
polarity (CPOL).

Certain MPU's, such as the CDPHC05C4, have a built-in SPI
bus and instructions to ease the software burden of transferring data. Appendix C lists the software needed by these
systems to access the CDP68HC68T1. (For a functional
description of the SPI, a pin Signal description and truth
table, address and data formats and descriptions, and read/
write data information, see the appropriate sections of
reference 1.)
Timebase Generation
The real-time clock circuit uses an input from its on-board
oscillator or from the 50/60-Hz line input Signal to generate
the 1-second pulse that toggles the time and calendar counters and provides the timing signals for other functions,
such as watchdog and power sense. The oscillator can be
driven from an external source, in which case the oscillatorout pin is left open, or as shown in Fig. 22, where it is used
with an external crystal and components to create the timebase frequency.
The large feedback resistor across the oscillator pins in Fig.
22 is required to place the input inverter in the linear area
and can range from 10 to 22 megohms. The capaCitors and

7-116

Application Note AN-8761.1
crystal form the rest of the feedback circuit, which supplies
the positive feedback and sustains oscillation.
The layout of the crystal oscillator circuit is extremely
important. Stray capacitances should be minimized, and
circuit traces, which must not be paralleled, should be less
than an inch in length. Signal and power source lines
should not cross or be placed near the oscillator circuit
lines. A 0.1 microfarad capacitor between Voo and Vss
decouples unwanted signals. If separate supplies at different voltage levels are used for VBATT and Voo, a small decoupiing capacitor from VBATT to ground eliminates oscillation at
the VBATT pin.
Fig. 22 is a typical external oscillator circuit. The oscillator
runs at anyone of four frequencies. 3 A 150-kilohm internal
resistor is placed in series with the oscillator output, Fig. 23,
when 32 kHz is selected via the clock control register. An
external resistor is required to guarantee 32 kHz oscillator
start-up when power is first applied since, as mentioned
above, the real-time clock circuit powers up in the 4-MHz
mode and the internal 150k resistor is not switched in. The
total value of the external crystal series resistor, R in Fig. 22,
is a combination of this internal 150k resistor, when used,
and an external resistance recommended by the manufacturer of the crystal.
5.3DpF

Voo

e-::-r;--~---1 ill

CDP

68HC0502

r-~--+----I REffi
f-----~ OSC1

~====~PORT("Q'p
MIsa

MOSI

MOSI:

SCKi--------j

Fig. 24 - Externally controlled power system.

resistor at the VSYS pin to assure the correct logic levels at
the VSYS pin after power has failed and as the supply floats.
The diode associated with the real-time clock circuit isolates the clock's Voo pin from the rest of the system when in
the battery back-up mode. The other diode drop keeps the
system and clock circuit supply voltages equal.
The reset pulse in the circuit of Fig. 24 is supplied at the
open drain CPUR output by the resistor and capacitor
combination. If many devices are to be reset from the CPUR
Signal, the RC combination can be moved to the VSYS pin to
assure that system power is present before Vsys releases the
clock circuit's output signals when power returns.

C211O-511Pf

Fig. 25 shows a battery back-up system. In this circuit, a
charging resistor is added in the battery hook-up. When
power sense is activated and a power-down instruction
issued, the PSE goes low, removing power from the rest of
the circuit. Fig. 26 shows the timebase being driven by the
60-Hz line signal. The diodes clamp the input swings one
diode drop from the rails.

ALL FREQUENCIES
RECOMlilENOED OSCILLATOR CIRCUIT;
fI, Ct, C2 VALUES CRYSTAL DEPENDENT
• R useD fOR 32 kHz OPERATION ONLY, MOST CRYSTALS
100 K· 300 K flANGE AS SPECifiED
BY CRYSTAL MANUFACTURER.

Fig. 22 - External oscillator circuit.

Fig. 27 illustrates another use for the CDP68HC68T1 in an
automotive application. In this circuit, a power failure is
sensed at the line pin when the ignition switch or clock button is opened. A power-down instruction is then sent to the
real-time clock, which holds the system in reset. Either an
interrupt or the closure of the clock or ignition switch brings
the clock circuit out of power down by placing a voltage on
the VSYS pin.

VSATT

Special Operating Considerations
TO

There is a Voo internal power-on-reset in the CDP68HC68T1;
it is used to tristate the MISO (data out) pin.

I

PRESCALERI

I

I

~

I
I

______ =________________ J

Fig. 23 - CDP68HC68T1 oscillator circuit. 150k resistor is placed in
series with oscillator output only when 32+kHz is selected
in clock control register.

APPLICATION CIRCUITS

Fig. 24 is a system set-up for power sense operation. In this
system, a power failure detected by the CDP68HC68T1
alerts the MPU by causing an interrupt. After establishing
that there is a power failure by monitoring the status register for a few milliseconds, the MPU issues a power-down
instruction. Some power supplies may require a pull-down

When power is initially supplied, assuming a proper paR
signal at pin 10, the real-time clock circuit sets up for crystal
operation at 4+MHz with the clock output equal to the crystal frequency. Most of the power consumed in the
CDP68HC68T1 is in the oscillator and clock out pin (especially at the higher frequencies).
If data transmission to the real-time clock circuit is stopped
after the address/control byte has been sent, there is no
problem. The circuit accepts data only after the required
clocks plus an additional transition at the SCK pin, or an
inactive chip enable after the required clocks, are input.
If the isolating diode is used with the real-time clock in a
battery back-up application, the system runs a diode-drop
above the clock circuit and the serial interface from the system violates the input limit of Voo + 0.5V. One way to
remedy this situation is to use another diode to drop the

7-117

Application Note AN-8761.1
(EPS)
ENABLED
POWER
SUPPLY

Voo

PSE i---JVVIJ--i
XTAL
C PUR

t-----.---t----t......-tREffi
Voo

COP

68HCQ5D2

CDP68HC68T1

;----------~ LINE

INT

i-----~----_o-l

~~

f-----------o-i OSC1

IRQ

CE~----------~PORT

Voo RTC

VSS

SPI~----~._---~-iSPI

Fig. 25 - Example of a system with battery back-up.

AC

LINE

SC"I------ISC"
MOO!
M.ISO

XTAL IN

M~I

MISO

Fig. 26 - Power-an-always system.

Tii'Tt------*----+->-\iRo

'ss

Fig. 27 - Automotive system diagram.

7-118

92CM-4227QRI

Application Note AN-8761.1
system Vee. If this method is not feasible, a 100- to 200-ohm
resistor in the MPU's driving line to the real-time clock will
safely limit th~ current.
While it is always a good idea to terminate all CMOS inputs,
including SPI lines, note that the SCK and MOSI inputs in
the real-time clock lines have weak feedback inverters,
which means that they will be pulled to some level even if
left unterminated. The CE pin has a pull-down transistor at
its input pin, so that leaving this pin floating disables the
circuit.
The problem with not terminating the SPI pins is reflected
on the MPU side, since these devices usually power up in

the input mode with their I/O pins floating. This situation
causes excessive current drain in CMOS components. All
inputs can be terminated properly by using 47k pull-down
or pull-up resistors.

REFERENCES
1. CDP68HC68T1, SPI Real-Time Clock. File No. 1547.
2. See Data Protocol and Connections section of ref. 1.
3. See Clock Control Register section of ref. 1.

Appendix A - Pin Functions
ClK OUT-Clock output pin. One of 7 frequencies can be
selected (or this output can be set low) by the levels of the
three lSB's in the clock-control register. If a frequency is
selected, it will toggle with a 50% duty cycle except 2 Hz in
the 50-Hz timebase mode. (Ex. if 1 Hz is selected, the output
will be high for 500 ms and low for the same period.) During
power-down operation (bit 6 in Interrupt Control Register
set to "1"), the clock-output pin will be set low.
CPUR-CPU reset output pin. This pin functions as an
N-channel only, open-drain output and requires an external
pull-up resistor.

Jiiif-Interrupt output pin. This output is driven from a single NFET Pull-down transistor and must be tied to an external pull-up resistor. The output is activated to a low level
when:
1. Power-sense operation is selected (B5 = 1 in Interrupt
Control Register) and a power failure occurs.
2. A previously set alarm time occurs. The alarm bit in the
status register and interrupt-out Signal are delayed 30.5
ms when 32-kHz operation is selected and 15.3 ms for
2-MHz and 7.6 ms for 4-MHz.
3. A previously selected periodic interrupt signal activates.
The status register must be read to set the Interrupt output
high after the selected periodiC interval occurs. This is also
. true when conditions 1 and 2 activate the interrupt. If power
down had been previously selected, the interrupt will also
reset the power-down functions.
SCK, MOSI, MISO-See Serial Peripheral Interface (SPI)
section in the data sheet.'
CE-A positive chip-enable input. A low level at this input
holds the serial interface logic in a reset state. This pin is
also used for the watchdog function.

Vss- The negative power-supply pin that is connected to
ground.
PSE-Power-supply enable output pin. This pin is used to
control power to the system. The pin is set high when:
1. VsyS rises above the VBATT voltage after VSYS was placed
low by a system failure.
2. An interrupt occurs.
3. A power-on reset (if Vsvs is a logic high).
The PSE pin is set low by writing a high into bit 6 (powerdown bit) in the Interrupt Control Register.

POR-Power-on reset. A Schmitt-trigger input that generates a power-on internal reset signal using an external R-C
network. Both control registers and frequency dividers for
the oscillator and line input are reset. The status register is
reset except for the first time up bit (84). which is set.
Single supply or battery back-up operation is selected at the
end of paR.
liNE-This input is used for two functions. The first function utilizes the input Signal as the frequency source for the
timekeeping counters. This function is selected by setting
bit 6 in the Clock Control Register. The second function
enables the line input to sense a power failure. Threshold
detectors operating above and below Vee sense an ac voltage 1055. Bit 5 must be set to "1" in the Interrupt COntrol
Register and crystal or external clock source operation is
required. Bit 6 in the Clock Control Register must be low to
select XTAl operation.
VSYS- This input is connected to the system voltage. After
the CPU !nitiates power down by setting bit 6 in the Interrupt Control Register to "1", the level'on this pin will terminate power down in the battery back-up mode if it rises
about 0.7 volt above the level at the VBATT input pin after
previously falling below VBATT + 0.7 volt. When power down
is terminated, the PSE pin will return high and the Clock
Output will be enabled. The CPUR output pin will also
return high. The logic level present at this pin at the end of
paR determines the CDP68HC68T1's operating mode.

VBATT- The oscillator power source. The positive terminal of
the battery should be connected to this pin. When the level
on the VSYS pin falls below VBATT + 0.7 volt, the VBATT pin will
be internally connected to the Vee pin. When the voltage on
VSYS rises a threshold (0.7V) above the voltage on VBATT, the
connection from VBI
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