1991_Harris_Digital_Signal_Processing 1991 Harris Digital Signal Processing

User Manual: 1991_Harris_Digital_Signal_Processing

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mHARRIS
HARRIS SEMICONDUCTOR DSP PRODUCTS
This digital signal processing databook represents the full line of Harris
Semiconductor asp products for commercial and military. applications
and supersedes previously published asp material under the Harris, GE,
RCA or Intersil names. For a complete listing of all Harris Semiconductor
products, please refer to the Product Selection Guide (SPG-201 R;
ordering information below).
For complete, current and detailed technical specifications on any Harris
device please contact the nearest Harris sales, representative or distributor
office; or direct literature requests to:
Harris Semiconductor Literature Department
P.O. Box 883, MS CB1-28
Melbourne, FL 32901
(407) 724-3739
FAX 407-724-3937
For general information regarding Harris Semiconductor and its products,.
call 1-800-4-HARRIS

U.S. HEADQUARTERS

EUROPEAN HEADQUARTERS

Harris SemiConductor
1301 Woody Burke Road
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TEL: (407) 724-3000

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TEL: (32) 2-246-2111

SOUTH ASIA

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Hong Kong
TEL: (852) 3-723-6339

. See o~r
specs In

NORTH ASIA

Harris KK
ShlnJuku NS Bldg. Box 6153
2-4-1 Nishi-Shlnjuku
Shinjuku-Ku, Tokyo 163 Japan
TEL: 81-03-3345-8911

CA··PS

Copyright @ Harris Corporation 1991
(All rights reserved)
Printed in U.S.A., 1991

· &'
."~"

"

Harris Semiconductor products are sold by description only. All specifications in this
product guide are applicable only to packaged products; specifications for die are
available upon request. Harris reserves the right to make changes.in circuit design,
specificationsaild other,'information at any time without prior notice. Accordingly,
the reader is cautioned to ,verify that information intlJis public~(ion is c~rrent
before placing orders. Reference to products of other manufacturers are solely
for convenience of comparison and do not imply tota/requiva/enc;y of design,
performance, or otherwise.

ii

FOR COMMERCIAL AND MILITARY APPLICATIONS
General Information _
Multipliers _
1-0 Filters _

2-0 FilterS_

Signal Synthesizers"
I
I

Special Function.
Application Notes

III

Quality and Reliability

III

Packaging a n d .
Ordering Information •
Sales Offices.

iii

>

~

!

DIGITAL SIGNAL PROCESSING
PRODUCT TECHNICAL ASSISTANCE
For technical assistance on the Harris products listed in this databook, please
contact Field Applications Engineering staff available at one of the following
Harris Sales Offices:

UNITED STATES
CALIFORNIA

Costa Mesa ............... 714-433-0600
San Jose .................. 408-922-0977
Woodland Hills ............ 818-992-0686

FLORIDA

Melbourne ................ 407-724-3576

GEORGIA

Norcross .................. 404-246-4660

ILLINOIS

Itasca .................... 708-250-0070

MASSACHUSETTS

Burlington ................ 617-221-1850

NEW JERSEY

Mt. Laurel ................. 609-727-1909
Rahway ................... 201-381-4210

TEXAS

Dallas .................... 214-733-0800

INTERNATIONAL
FRANCE

Paris ..................... 33-1-346-54090

GERMANY

Munich ................... 49-8-963-8130

ITALY

Milano .................... 39-2-262-22127

; JAPAN

Tokyo .................... 81-3-345-8911

SWEDEN

Stockholm ................ 46-8-623-5220

U.K•

Camberley ................ 44-2-766-86886

.. ,;f

For literature requests, please contact Harris at 407-724-3739.

iv

GENERAL INFORMATION
ALPHA NUMERIC PRODUCT INDEX
PAGE
DECI- MATE'"

Harris HSP43220 Decimating Digital Filter Development Software ................. . 3-31

HMA510

16 x 16-Bit CMOS Parallel Multiplier Accumulator .................... ~ .......... . 2-29

HMA51 0/883

16 x 16-Bit CMOS Parallel Multiplier Accumulator ............................... . 2-36

HMU16/HMU17

16 x 16-Bit CMOS Parallel Multipliers .......................................... . 2-3

HMU16/883

16 x 16-Bit CMOS Parallel Multiplier ........................................... . 2-13

HMU17/883

16 x 16-Bit CMOS Parallel Multiplier ........................................... . 2-21

HSP43168

Dual FIR Filter ............................................................... . 3-102

HSP43220

Decimating Digital Filter ...................................................... . 3-3

HSP43220/883

Decimating Digital Filter .......................... :............................ . 3-23

HSP43481

Digital Filter ................................................................. . 3-81

HSP43481/883

Digital Filter ................................................................. . 3-96

HSP43881

Digital Filter ................................................................. . 3-58

HSP43881/883

Digital Filter ................................................................. . 3-73

HSP43891

Digital Filter ................................................................. . 3-35

HSP43891/883

Digital Filter ................................................................. . 3-50

HSP45102

12 Bit Numerically Controlled Oscillator ....................................... .. 5-43

HSP45106

16 Bit Numerically Controlled Oscillator ........................................ . 5-26

HSP451 06/883

16 Bit Numerically Controlled Oscillator ........................................ . 5-36

HSP45116

Numerically Controlled Oscillator/Modulator .................................... . 5-3

HSP45116/883

Numerically Controlled Oscillator/Modulator .................................... . 5-18

HSP45240

Address Sequencer .......................................................... . 6-3

HSP45240/883

Address Sequencer .......................................................... . 6-14

HSP45256

Binary Correlator ............................................................. . 6-33

HSP48901

3

HSP48908

Two Dimensional Convolver ................................................... . 4-3

HSP48908/833

Two Dimensional Convolver ................................................... . 4-19

HSP9501

Programmable Data Buffer .................................................... . 6-21

HSP9520/9521
ISP9520/9521

Multilevel Pipeline Register ..... '.' ............................................. . 6-28

x 3 Image Filter ............................................................. : 4-26

DEClo MATE~ Is a Trademark of Harris Corporation

1-1

z
..... 5!


C.IIu..

==

PRODUCT INDEX BY FAMILY
MULTIPLIERS:
HMA510

~AGE

' 16 x 16-Bit CMOS Parallel Multiplier Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-29

HMA51 0/883

16 x 16-Bit CMOS Parallel Multiplier Accumulator . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . .. 2-36

HMU16/HMU17

16 x 16-Bit CMOS Parallel Multipliers .................... , .. . . .. . .. .. .. .. . . .. ... 2-3

HMU16/883

16 x 16-Bit CMOS Parallel Multiplier. .. . .. . .. . .. . .. . . .. .. . . .. . .. . .. . .. .. .. . .. ... 2-13

HMU17/883

16x 16-BitCMOS Parallel Multiplier ............................................ 2-21

ONE DIMENSIONAL FILTERS
DECI-MATE

Harris HSP43.220 Decimating Digital Filter Development Software .................. 3-31

HSP43168

Dual FIR Filter ................................................................ 3-102

HSP43220

Decimating Digital Filter ....................................................... 3-3

HSP43220/883

Decimating Digital Filter ....................................................... 3-23

HSP43481

Digital Filter ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-81

HSP43481/883

Digital Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-96

HSP43881

Digital Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-58

HSP43881/883

Digital Filter .................................................................. 3-73

HSP43891

Digital Filter .......................................•.............. , . . . . . . . . . .. 3-35

HSP43891/883

Digital Filter ...................................... , . . . . . . . . . . . ... . . . . . . . . . . . . .. 3-50

TWO DIMENSIONAL FILTERS
HSP48901

3 x 3 Image Filter ............................................................ "

HSP48908

Two Dimensional Convolver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3

4-26

HSP48908/833

Two Dimensional Convolver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-19

SIGNAL SYNTHESIZERS
HSP45102

12 Bit Numerically Controlled Oscillator

5-43

HSP45106

16 Bit Numerically Controlled Oscillator

5-26

HSP451 06/883

16 Bit Numerically Controlled Oscillator

5-36

HSP45116

Numerically Controlled Oscillator/Modulator ., .... '... '......'. . . . . . . . . . . . . . . . . . . . .. 5-3

HSP45116/883

Numerically Controlled Oscillator/Modulator.; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-18

SPECIAL FUNCTION
HSP45240

Address Sequencer .......................................................... , 6-3

HSP45240/883

Address Sequencer ........................................................... 6-14

HSP45256

Binary Correlator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-33

HSP9501

Programmable Data Buffer .......................... : ........................... 6-21

HSP9520/9521
ISP9520/9521

Multilevel Pipeline Register ...........................•............. " . . . . . . . . .. 6-28

1883 Data Sheet Format - In the interests of conserving space. data sheets for 1883 qualified products have been printed without the Pinouts. Pin
,
Description, Waveforms, AC Test Load Circuit and Design Informatio"n sections. The information in these sections can be
obtained from the corresponding portion of the commercial data sheet.

1-2

MULTIPLIERS
PAGE
DATA SHEETS
HMU16/HMU17

16 x 16-Bit CMOS Parallel Multipliers ...•............•................•...•..... 2-3

HMU16/883

16 x 16-Bit CMOS Parallel Multiplier ..•......................................... 2-13

HMU17/883

16 x 16-Bit CMOS Parallel Multiplier ........................................... . 2-21

HMA51 0

16 x 16-Bit CMOS Parallel Multiplier Accumulator ............................... . 2-29

....a:
::i

HMA51 0/883

16 x 16-Bit CMOS Parallel Multiplier Accumulator ............................... . 2-36

5
:::»

tn

0...

~

2-1

mHARRIS HMU16/HMU17
16 X 16-Bit CMOS
Parallel Multipliers.

May 1991

Features

Description

• 16 x 16-Blt Parallel Multiplier with Full 32-Blt
Product

The HMU16/HMU17 are high speed, low power CMOS
16 x 16-bit multipliers ideal for fast, real time digital signal
processing applications.

• High-Speed (35ns) Clocked Multiply Time
• low Power Operation:
~ ICCSB = 50011A Maximum
~ ICCOp
7.0mA Maximum @ 1MHz

=

• Supports Two's Complement, Unsigned Magnitude
and Mixed Mode Multiplication
• HMU16Is Compatible with the AM29516, lMU16,
IDT7216 and the CY7C516
• HMU17Is Compatible with the AM29517, lMU17,
IDT7217 and the CY7C517
• TTL Compatible Inputs/Outputs
• Three-State Outputs
• Available In a Ceramic 68 Pin Grid Array (PGA) and
68 Pin Plastic leaded Chip Carrier (PlCC)

Applications
• Fast Fourier Transform Analysis
• Digital Filtering
• Graphic Display Systems
• Image Processing
• Radar and Sonar
• Speech Synthesis and Recognition

The X and Y operands along with their mode controls (lCX
and TCY) have 17-bit Input registers. The mode controls
independently specify the operands as either two's
complement or unsigned magnitude format, thereby
allowing mixed mode multiplication operations.
Two 16-bit output registers are provided to hold the most
and least significant halves of the result (MSP and lSP). For
asynchronous output these registers may be made
transparent through the use of the feedthroughcontrol (FT).
Additional Inputs' are provided for format adjustment and
rounding. The format adjust control (FA) allows the user to
select either a left. shifted 31-bit product or a full 32-bit
product, whereas the round' control (RNO.) provides the
capability of rounding the most significant portion .of the
result.
The HMU16 has independent clocks (ClKX, ClKY, ClKl,
ClKM) associated with each of these registers to maximize
throughput and simplify bus interfacing. The HMU17 has
only a single clock input (ClK), but makes use of three
register enables (EiiiX, ENY and EN'i5). The ENX and ENY
inputs control the X and Y input registers, while ENP
controls both the MSP and lSP output registers. This
configuration facilitates the use of the HMU17 for
microprogrammed systems.
The two halves of the product may be routed to a single
l6-bit three-state output port via a multiplexer, and in
addition, the lSP is connected to the V-input port through a .
separate three-state buffer.
All outputs ofthe HMU l6/HMU 17· multipliers also offer threestate control for multiplexing results onto muitl-use busses.

CAUTION: Electronic devices are sensllive to electroslatlc discharge. Proper I.C. handling procedures should be followed.
Copyright @ HarriS CorPoration 1991

File Number

2803

""

'$\

'."

,>'

';Cti~A~C 68j:1INGR'i~ ~R~AY1PGA'

~<.: ~."

Package Pinouts'<'

TOP VIEW

N/C

"

<

X13

X15
",

<

X11

X12

X9

. Xl0
" \

RND

•..

,

ClKX
TCX
(ENX) , '

Xl.

TCY

Vcc

",vCC

GND

"

GND

-OEP

FT

- - -FA
MSPSEL

CLKM

N/C

(ENP)
P30/

P311

Pl.

P15

P291
P13

,

X7

X8

P28J.
P12

X5

xs

P261
Pl0

X3

x.

Xl

X2

-OEl

XO

CLKY

68 lEAD
PIN GRID ARRAY
TOP VIEW

I"

pa71
Pll

P241
,P8 '

P25/
P8

P22/

P23/
P7

P6
,

P201
P4

(ENV)

CLKL
(ClK)',

N/C

YOI
PO

,Y21
P2

Y.I,'
P.

Y61
P6

V61
P8

Yl01
Pl0

Yl21
Pl.

Y1/,
PI

,V31
P3

Y51
P5

Y71
P7

Yal
P9

YI1/
P11

VI 3/
P13.' .

P21/

, P5

P181
P2

P19t

Yl.1
Pl.

P1S1
PO

P171
PI

VISI
PI5

N/C

P3

68 PINPLASnc'LEADED CHIP CARRIER (PLCC)
,
"
TOP VIEW

,216887660584838281

•

NC
X12
XII
Xl0
X9
X8
X7
X6

HMU16
(HMUI7)

X5
X4
X3
X2
Xl
XO
OEl
CLKL (CLK)
ClKY (ENy)

..

N
0
a:: a:: '"
a:: a:: a:: a:: ~fS:ff:e~fS!a:f~
..; cO oj
<5 ¢'~~~~~~~;::¢
;:: ;:: ;:: ;:: ;:: ;::
It)

ICi

2-4,

HMU16/HMU17
Functional Block Diagram
HMU16
XO -15 TCX

CLKX -

RND

TCY YO - 15JPO -15

-..::r"""

.......

CLKY--4------------+----~~

FA

FORMAT ADJUST

FT

til

IX:

w

::::;

CLKM
CIJQ.

j:::

MSPSEL

-'

D..

=>

::E
OEP

P16 - 31JPO -15

HMU17
XO -15 TCX

RND

TCY YO - 151PO - 15

CUK-.~~------~~~----'
ENX-+-~d[~
ENY-+~-----------r----~~

FA

-+-----------1

FT

-+------1

FORMAT ADJUST

~=====~§~~~~~5

MSPSEL
ENP -

OEP------------------~~

P16 - 31/PO -15

2-5

H Mf./J6/HIY/U;1.7
Pin Description
SYMBOL

PLCC
PIN NUMBER

VCC

1,68

DESCRIPTION

TYPE

VCC' The +5V power supply pins. A O.lI'F capacitor between the VCC and GND pins
is recomm~nded.
GND. The device groun~.

GND

2,3

XO-X15

47-59,61-63

I

X-Input Data. These ,16 data inputs provide the multiplicand which may be in two's
complement or unsiQned magnitude format.

YO-Y15/
PO-P15

27-42

I/O

Y-lnpuVLSP Output DatI!-. This .16~Blt port is used to provide the multiplier which
may be in two's complement .or unsigned magnitude formal It may also be used for
output of the Least Significant Product (LSP).

P16-P31/
PO-P15

10-25

0

TCY, TCX

66,67

'1

•.

Output Data. This 16-Bit port may provide either the MSP (P16-31) or the
LSP (PO-151.

.

. Two's Complemenl'Control. Input data Is interpreted as two's complement when this
control is HIGH. A LOW indicates the data is to be interpreted as unsigned
magnitude format.

FT

5

I

FE\9dthrough Control. When this control is HIGH, both the MSP and LSP registers are
tranllparent. When ·LOW, the registers are latched by their associated clock signals.

FA

6

I

Format Adjust Control. A full 32-bit product is ,selected when this control line
is HIGH. A LOW on this control line selects a left shifted 31-bit product with the sign
hit replicated in the LSP. This control is normally HIGH except for certain two's
complement integer and fractional applications.

RND

65

I

Round ·Cdntrol. When this control is HIGH, a one is added to the Most Significant Bit
(MSB) otthe LSP. This position is dependent on the FA control; FA = HIGH indicates
RND adds to the 2-15 bit (P15), and FA = LOW indicates RND adds to the 2- 16
bit (P14).

MSPSEL

4

I

Output Multiplexer Control. When this control is LOW, the MSP is available for output
at the dedicated output port, and the lSP is available at the Y-inpul/lSP output
port. When MSPSEL is HIG H, the lSP is available at both ports and the MSP is not
available for output.

OEL

46

I

Y-ln/PO-15 Output Port Three-state Control. When OEl is HIGH, the output drivers
are in the high impedance state. This state is required for V-data input. When OEl
is lOW, the port is enabled for lSP output.

OEP

7

I

P16-31/Po-15 Output Port Three-state Control. A lOW on this control line enables
the output port. When OEP is HIGH, the output drivers are in the high impedance
state.

The following Pin Descriptions apply to the HMU16 only.
ClKX

64

I

ClKY

44

I

ClKM

8

I

ClKL

45

I

X-Register Clock. 1he' rising edge of this clock loads the X-data input register along
with the TCX and RND regrsters•.

,

V-Register Clock. The rising edge ,of this clock loads the V-data input register along
with the TCY and RND registers.
MSP Register..CloCk. The rising edge of ClKM loads the most significant product
(MSP) register.

..

lSP Register Clock. The rising edge of ClKL loads the least significant product
..
(lSP) register.

The following Pin Descriptions apply to the HMU17 only.

,

..

~.tock: !he rish~g edge of this clock ~iIIload all enabled registers.

ClK

45

I

ENX

64

I

Enable. Wheh ENX is lOW, theX-register is enabled; X-input data and
TCX will be latched at the rising edge of ClK,When ENX is high, the X-register
is iMfhold mode.

ENY

44

I

Y-Register.Enable. ENY enables the Y-rElgister. (See ENX).

ENP

8

I

Product Register Enable. ENP ena~he product register. Both the MSP and LSP
sections are enabled by ENP. (See ENX).

X~RegIster

2-6

HMU16/HMU17
Functional Description
The HMU16/HMU17 are high speed 16 X 16-bit multipliers
designed to perform very fast multiplication of two 16-bit
binary numbers. The two 16-bit operands (X and Y) may be
independently specified as either two's complement or
unsigned magnitude format by the two's complement
controls (TCX and TCY). When either of these control lines
is LOW, the respective operand is treated as an unsigned
16-bit value; and when it is HIGH, the operand is treated as
a signed value represented in two's complement format.
The operands along with their respective controls are
latched at the rising edge of the associated clock signal.
The HMU16 accomplishes this through the use of independent clock inputs for each of the input registers (CLKX and
CLKY), while the HMU17 utilizes a single clock signal (CLK)
along with the X and Y register enable inputs (ENX and ENY).
Input controls are also provided for rounding and format
adjustment of the 32-bit product. The Round input (RND) is
provided to accomodate rounding of the most significant
portion of the product by adding one to the Most Significant
Bit (MSB) of the LSP register. The position of the MSB is
dependent on the state of the Format Adjust Control (See
Pin Descriptions and Multiplier Input/Output Format
Tables). The Round input is latched into the RND register
whenever either of the input registers is clocked. The
Format Adjust control (FA) allows the product output to be
formatted. When the FA control is HIGH, a full 32-bit
product is output; and when FA is LOW, a left-shifted
31-bit product is output with the sign bit replicated in bit
position 15 of the LSP. The FA control must be HIGH for
unsigned magnitude, and mixed mode multiplication

operations. It may be LOW for certain two's complement
integer and fractional operations only (See Multiplier Input/
Output Formats Table).
The HMU16/HMU17 multipliers are equipped with two
16-bit output registers (MSP and LSP) which are provided
to hold the most and least significant portions of the
resultant product respectively. The HMU 16 uses independent clocks (CLKM and CLKL) for latching the two output
registers, while the HMU17 uses a single clock input (CLK)
along with the Product Latch Enable (ENP). The MSP and
LSP registers may also be made transparent for asynchronous output through the use of the Feedthrough control (FT).
There are two output configurations which may be selected
when using the HMU16/HMU17 multipliers. The first
configuration allows the simultaneous access of the most
and least significant halves of the product. When the
MSPSEL input is LOW, the Most Significant Product will be
available at the dedicated output port (P16-31/PO-15). The
Least Significant Product is simultaneously available at the
bi-directional port shared with the V-inputs (YO-15/PO-15)
through the use of the LSP output enable (OEL). The other
output configuration involves multiplexing the MSP and
LSP registers onto the dedicated output port through the
use of the MSPSEL control. When the MSPSEL control is
LOW, the Most Significant Product will be available at the
dedicated output port; and when MsPSEI. is HIGH, the
Least Significant Product will be available at this port. This
configuration allows access of the entire 32-bit product by
a 16-bit wide system bus.

2-7

rn
II:
LU

::::;
0-

5

~

==

HMI:116/HMU17
Multiplier Input/Output Formats Table
FRACTIONAL TWO'~-COMPLEMENT NOTATION

• In this format an overflow occurs in the aUempted multiplication of the two's complement number 1,000 ••. 0
with 1,000 ••• 0 yie!di"ll an erroneous product of -1 in the fraction case and -:z30 in the integer case.

FRACTIONAL UNSIGNED MAGNITUDE NOTATION
BINARY POINT

FRACTIONAL MIXED MODE NOTATION
BINARY POINT

2-8

HMU16/HMU17
Multiplier Input/Output Formats Table

(Continued)

INTEGER TWO'S COMPLEMENT NOTATION
IINARY POINT

* In this lormat an overflow occurs in the attempted multiplication 01 the two's complement number 1,000 ••• 0
wHh 1,000 ••. 0 yielding an erroneous product 01-1 in the fraction case and -230 in the integer case.

INTEGER UNSIGNED MAGNITUDE NOTATION
BINARY POINT

SIGNAL

1:f.T:-;;t::;;t:T.t:*t-::;!Gr:;;t:;::;t:T.t-:f.t-:;;;!r:;;~;t:;:;t:*:-:;t'7.i-'-*r.:r.it:-=+-*'::i-:;'!p.+::r;r*:*'it-:;;, DIGIT VALUE

IFA = 1 I

MANDATORY

INTEGER MIXED MODE NOTA.TION
BINARY POINT

2-9

SpecificationsJ-lJYIUl6/HMU17
Absolute Maximum Ratings
Supply Voltage ., •.••.•••.••.••.••••••••.•••••••• ; •.•.•••••••• ;, •••••••• '•• : •••••••••••.••••••••••.••••.••.•••• +8.0 Volts
,Input, Output or I/O Voltage Applied ••••••••••..••.•••.•••••••..•.•••••••••..•••••••••••••••••••• GND-0.5V to VCC+0.5V
Storage Temperature Range .•.••.••••••••• , •••.•••.•••••••••..•.•••••.•••..••••••••.••••••••• , ••••••• -650 C to +1500 C
Gate Count •••••••••••.••••••.••••.•.••••••••••••••••..•.••••••••••••••••••••..•••••••••••••.••..•..••.••• 4500 Gates
aja •.•.••...••••• , •••• , : ••..•',. ',' '" ••.•,.•• , • ,,' " ", .,~':'. '" ~ '.•••••••••••••....••••••••• 43.2OCIW (PLCC), 42.690 CIW (PGA)
ajc ••..•.••.••• ;, •••• ,., ••••.••••• , •• : ••••• ". i •• , •••••••••••••••• , . . . . . . . . . . . . . . . . . . 15.1 0 CIW(PLCC), 1O.OoCIW (PGA)
Maximum Package Power Dissipation at 70 0 C .................................................... 1.7W (PLCC), 2.46 (PGA)
Junction Temperature; ...... ;' ................. ",' ............. ',o''' " , ' . . . . . . . . . . . . . . . . . . . +l50o C (PLCC), +1750 C (PGA)
Lead Temperature (Soldering, Ten S!!C<;mds) .,," .... ; ................ , ............................................ +3000 C
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress only rating,
and operation at these or any other conditions above those indicated in the operatio~.s sections of this speciflcatio.n is not implied.
Opera'ting Conditions
Operating Voltage Range ........... '•.• o' . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . o' . . . . . . . . . . . . . . . . +4.7SVto +5.25V
Operating Temperature 'Range ..........-.................................................................. OoC to + 700C
D.C. Electrical Specifications (VCC
SYMBOL

= 5.0V + 5%, TA = OOC to HOOC)

PARAMETER

MIN

MAX

UNITS

TEST CONDITIONS

VIH

Logical One Input Voltage

2.0

-

V

VCC=5.25V

VIL

Logical Zero Input Voltage

-

0.8

V

Vcc= 4.75V

2.6

-

V

'IOH = -400llA, VCC = 4.75V

VOH

Qutput High Voltage

-

0.4

V

10L = +4.0mA, VCC = 4.75V

II

Input Leakage Current

-10

10

!lA

VI =VCC orGND,VCC = 5.25V

10

Output or I/O Leakage Current

-10

10

!lA

Vo = VCC or GND, VCC = 5.25V

ICCSB

Standby Power Supply Current

-

500

!lA

VI =VCCorGND, VCC = 5.25V
, Outputs C?pen

ICCOp

Operating Power Supply Current

-

7.0

mA

VI =VCCorGND, VCC = 5.25V
f = 1 MHz (Note 1)

VOL

Output Low Voltage

CapaCitance (TA = +250 C, Note 2)
SYMBOL
CIN
COUT
CI/O

TYPICAL

UNITS

Inp'ut Capacitance

15

pF

Frequency = 1 MHz.
All measurements referenced

OulputCapacitance

10

pF

to device Ground.

I/O Capacitance

10

pF

PARAMETER

NOTES:
1. Operating Supply Current is proportional to frequency. Typical rating is
SmNMHz.
'
2. Not tested. but characterized allnltlal design and at major processl
design changes.

TEST CONDITIONS

Specifications HMU 16/HMU 17
A.C. Electrical Specifications (Vcc = 5.0V + 5%, TA = ooc to +700C, Note 3)
HMU16/HMU17-35
,SYMBOL

·PARAMETER

MIN

HMU16/HMU17-45

MAX

MIN

MAX

UNITS

Unclocked MultiplyTime

-

55

-

70

ns

TMC

Clocked Multiply Time

-

35

-

45

ns

TS

X, Y, R ND Setup Time

15

-

18

-

ns

TMUC

X, Y, RND Hold Time

2

-

2

-

ns

TpWH

Clock Pulse Width High

10

-

15

-

ns

TpWL

Clock Pulse Width Low

10

-

15

-

ns

TpDSEL

MSPSEL to Product Out

-

22

-

25

ns

Output Clock to P

22

-

25

ns

TH

TEST
CONDITIONS

TpDY

Output Clock to Y

-

22

-

25

ns

TENA

3-State Enable Time

-

22

-

25

ns

TOIS

3-Stale Disable Time

-

22

-

25

ns

TSE

Clock Enable Setup Time
(HMU17 only)

15

-

15

-

ns

THE

Clock Enable Hold Time
(HMU17 only)

2

-

2

-

ns

Clock Low Hold Time CLKXY
Relative to CLKML
(HMU160nly)

0

-

0

-

ns

TR

Output Rise Time

-

8

ns

From 0.8V to 2.0V

Output Fall Time

-

8

TF

8

ns

From 2.0V to 0.8V

TpDP

THCL

8

Note 1

Note 2

NOTES:

1. TransHion is measured at ±200mV from steady state voltage with loading
specified in Figure 1, V1
1.5V, R1 = 5000 and C1
40pF

=

=

3. For A.C. Test load, Refer to Figure 1, with V1
C1 = 40pF

2. To ensure the correct product is entered in the output registers, new data
may not be entered into the input registers before the output registers
have been clocked.

2-11

= 2.4V, R1 = 5000 and

HM'U16/HMUI7
A. C. Testing Input; OutputWalieforms

A.C. Test Circuit

3.0V~

~VOH

oV~------~VOL

* Includes Stray and Jig Capacitance

A.C. Testing: All parameters testildasper test circuit. Input rise and fall times
'
are driven at 1nsN.

Timing Diagram
SET-UP AND HOLD TIME

I~~~ 'OOOC )()()(

~~,

)()OOOOO()d:~

I

.t-'

I TS

,TH

THREE STATE CONTROL
THREE
STATE
CONTROL

OV

!~~

OUTPUT - - - - - ,
HIGH IMPEDANCE
THREE
~~------~--(I
STATE

HMU16 TIMING DIAGRAM'

1.7V

1.3V

, HMU17 TIMING QIAGRA,""
j"TPWH. j

C~ __----~I
ENX

~I'

____~L

I-

..

TpWL

E~y~~L-~+---~~~~~~~~~~"

INPUT ~,I~=:!:::~:::::::j~,.,...,..,.....,.....,b...,....~.,....,~

~~~ ~~I'--~--',I~~~~~~~~~~'

~i~-------+---------~
OUTPUTY~~~~~~~~~~~~I~_ _ ___

2-12

HMU16/883

mHARRIS

16

May 1991

X

16-Bit CMOS Parallel Multiplier

Features

Description

• This Circuit is Processed in Accordance to Mil-Std883 and is Fully Conformant Under the Provisions
of Paragraph 1.2.1.

The HMU16 is a high speed, low power CMOS 16 x 16-bit
parallel multiplier ideal for fast, real time digital signal
processing applications. The 16-bit X and Y operands may
be independently specified as either two's complement or
unsigned magnitude format, thereby allowing mixed mode
multiplication operations .

.16 x 16-Bit Parallel Multiplier with Full 32-Bit
Product
• High-Speed (45ns) Clocked Multiply Time
• low Power CMOS Operation:
~

ICCSB

~ ICCOp

= 500,..A Maximum
= 7.0mA Maximu'm @ lMHz

• HMU16 is compatible with the AM29516, lMU16,
IDT7216, and the CY7C516
• Supports Two's Complement, Unsigned Magnitude
and Mixed Mode Multiplication
• TTL Compatible Inputs/Outputs
• Three-State Outputs
• Available in a 68 lead Pin Grid Array Package

Additional Inputs are provided to accommodate format
adjustment and rounding of the 32-bit product. The Format
Adjust control allows the user to select a 31-bit product
with the sign bit replicated in the LSP. The Round control
provides for rounding the most significant portion of the
result by adding one to the most significant bit of the LSP.
Two 16-bit output registers (MSP and LSP) are provided to
hold the most and least significant portions of the result,
respectively. These registers may be made transparent for
asynchronous operation through the use of the feedthrough
control (FT). The two halves of the product may be routed to
a Single 16-bit three-state output port via the output
multiplexer control, and in addition, the LSP is connected to
the V-input port through a separate three-state buffer.
The HMU16 utilizes independent clock signals (ClKX,
CLKV, CLKL, CLKM) to latch the input operands and output
product registers. This configuration maximizes throughput
and simplifies bus interfaCing. All outputs of the HMU16
also offer three-state control for multiplexing onto mUlti-use
system busses.

Functional Diagram

XO-15 TCX

RND

TCY YO - 15A'O -15

CU:.:
u

~

..J

u

Ig

0

X

><
§:

~

><

§;

., ...
><

><
§:

on

><

"

e

~

...

0

><

><

ex>

><
'"

e e

e

e

co

><

C?

c;;-

o

'"
X X
Cil ;::e e
~

X
0;
e


...'" ,,;...'" ...'"'" ,:...'" ...'" ... ,;... ....,:'" '"... ...'"'" ... ,,;...
...ci M... ...- ... ...uS c;;-... ...uS ... 0: 0: ...ci ...M 0: 0:
;::- Cil 0; 0
C?
;::ex>

0:

~

0:'"

~

0

..

~

~

0
M

",-

!2.

~

!2.

!2.

!2.

2-19

"

!2.

~

M

~

on

!2.

Cil
!2.

~

~

!2.

Cil
!2.

0;

!2.

0

~

j::
.....
::::.

:e

HMU16/883
Packaging t
68 PIN CERAMIC PIN ·GRID ARRAY

I
.120

"l4Ol
I
.040
.060

SEATING PLANE

~r:~~

1.140
1.180
G

.100

F

1.000

sse

sse

B
A
9

10

11

[~003

MIN

1. INCREASE MAXIMUM LIMIT BY .OOJ" WHEN SOLDER
DIP OR TIN PLATE LEAD FINISH APPLIES.

LEAD MATERIAL: Type B
'.
LEAD FINISH: Type C "
PACKAGE MATEi'lJAl;:'Ceramic, A12039Q%
PACKAGE SEAL:'
.
Material: Gold/Tin
Temperature: 32pOC ± 100 C
Method: Furnaci:(Braze
.

NOTE: All Dimensions are

INTERNAL LEAD WIRE:
Material: Aluminum
DiamEitEir: 1.25 Mil
Bonding Method: Ultrasonic Wedge
COMPLIANT OUTLINE: 38510 P-AC

..Min.. . Dimensions are in inches.

tMil-M-38510 Compliant Materials, Finishes, and Dimensions.

Max

2-20

m

HMU17/883

HARRIS

16

May 1991

16-Bit CMOS Parallel Multiplier

X

Features

Description

• This Circuit is Processed in Accordance to
Mil-Std-883 and is Fully Conformant
Under the Provisions of Paragraph 1.2.1.

The HMU17 is a high speed, low power CMOS 16 x 16-bit parallel
multiplier ideal for fast, real time digital signal processing applications.
The 16-bit X and Y operands may be independently specified as
either two's complement or unsigned magnitude format, thereby
allowing mixed mode multiplication operations.

• 16 x 16-Bit Parallel Multiplier with Full
32-Bit Product
• High-Speed (45ns) Clocked Multiply Time
• Low Power CMOS Operation:
~

ICCSB = 5001lA Maximum

~

ICCOp = 7.0mA Maximum @ 1MHz

• HMU17 is compatible with the AM29517,
LMU17, IDT7217, and the CY7C517
• Supports Two's Complement, Unsigned
Magnitude and Mixed Mode Multiplication
• TTL Compatible Inputs/Outputs
• Three-State Outputs
• Available in a 68 Lead Pin Grid Array
Package

Additional inputs are provided to accommodate format adjustment
and rounding of the 32-bit product. The Format Adjust control allows
the user the option of selecting a 31-bit product with the sign bit
replicated lSP. The Round control is provided to accommodate
rounding of the most significant portion of the result. This is accomplished by adding one to the most significant bit of the lSP.
Two 16-bit output registers (MSP and lSP) are provided to hold the
most and least significant portions of the result, respectively. These
registers may be made transparent for asynchronous operation
through the use of the feedthrough control (FT). The two halves of the
product may be routed to a single 16-bit three-state output port via
the output multiplexer control, and in addition, the lSP is connected to
the Y -input port through a separate three-state buffer.
The HMU17 utilizes a single clock signal (ClK) along with three
register enables (ENX, ENY, and ENP) to latch the input operands and
the output product registers. The ENX and ENY inputs enable the
X and Y input registers, while ENP enables both the lSP and MSP
output registers. This configuration facilitates the use of the HMU17
for micro-programmed systems.
All outputs of the HMU 17 also offer three-state control for multiplexing
onto multi-use system busses.

Functional Diagram
XO ·15 TCX

CLK

RND

TCY YO· 15A'O -15

-..+-i:---->+-t-t--....

ENX -t-I--Cl["""""",

ENY-+-+---------r-----r~

OEP------------------~

P16 - 31A'O -15

Copyright

©

Harris Corporation 1991

File Number
2-21

2805

Specifications HMU17/883
'''I''

".

':.::..

.'

:

'\.,

.,

Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••••••••••••••••••••••.•.••••.•..•. +8.0V
Input or Output Voltage Applied •.•••••• GND-0.5V to VCC +0.5V
Storage Ter;nperature Range .•••••••••••.••• , -650C to +1500 C
Junction Temperalure .••••••••••....•••...•••.••..••. +1750 C
Lead Temperatur&(Solderlng 10 sec) •..•• '............... 3000C
ESD Classification ••••••.•••••••••••••••••••••••••••• ',Glass 1

Thermal Resistance
6ja
6jc
Ceramic PGA Package. • . . • • • • • • • •• 42.690 C/W 10.00 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic PGA Package .••••••••••••••••.•••..••••. 1.17 Watt
Gate Count ..•........••.•.•.. ,•••••••••••••.•..•. 4500,Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the deviqe at these or any other condlt!ons above those indicated in the operatjon~1 section'~ of this specification IE! ~t. implied..

Operating Conditions
Operating Voltage Range •••.•••••.••.• , •••••••• +4.5V to +5.5V
Operating Temperature Range •••• ',' •• " ••• ,"' -550 e to +1250 e
TABLE 1. HMU16/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
"

PARAMETER

SYMBO!-

CONDITIONS

Logical One Input
Voltage

VIH

Vee =5.5V

Logical Zero Input'
Voltage

VIL

Vec=4.5V

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

1,2,3

-550C ~TA!> +1250 e

2.2

-

V

1,2,3

-55°C !>TA S+1250 e

-

0.8

V

Output HIGH Voltage

VOH

' 10H =-400"A
'V ce =' 4.5V (Note 1)

1,2,3

-55°C!> TA S +1250 C

2.6

-

V

Output LOW Voltage

VOL

IOL=+4.0mA
'Vce= 4.5V {Note 1)

1,2,3

-550 e!> TA S +125 0 e

-

0.4

V

VIlIt= Vee or GND
,Vr;0=5.5V

1;2,3

-55°C STA S +125 0 C

-10

+10

JlA

Input Leakage, Current

II

Output or I/O Leakage
Current

10

ilbuT'=VCCorGND
Vee = 5.5V

1,2,3

-550C !>TAS +1250 0

-10

+10

JlA

Standby Power Supply
Current

ICCSB

'VIN = VCC or GND,
VCC = 5.5V, Outputs
Open

1,2,3

-550C!> TA!> +1250 C

-

500

JlA

Operating Power
Supply Current

ICCOp

f= 1.0MHz,
'VIN = VCC:Or GND
VCC = 5.5V (Note 2)

1,2,3

-55Oe !>TA~ +12500

-

1.0

mA

'7,8 '

-55°C S TA S +1250 C

-

-

Functional Test

FT

(Note 3)

NOTES:

=,

1. Interchanging of force and sense conditions. is, J)ermiHed.
2. Operating Supply Current is proportiori8J to frequency, typical rating Is
SmA/MHz.

=

3. Tested as follows: f
MHz. VIH (Clock Inputs)
3.0. VIH (All other
inpuls) ';' 2,6. VIL = 0.4. VOH :!: , .SV. and VOL
l.SV.

CAUTION: ThesE! ~evices are sensitive to electrostatic discharge. Proper IC handling procedures should be followed.

2-22

:s.

Specifications HMU17/883
TABLE 2. HMU17/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER
Unclocked Multiply
Time

SYMBOL

(NOTE 1)
CONDITIONS

-45

GROUP A
SUBGROUPS

TEMPERATURE
::5+ 125 0

MIN

-60

MAX

MIN

MAX

UNITS

-

70

-

90

ns

TMUC

9,10,11

-55 0

Clocked MultiplyTime

TMC

9,10,11

-550C :5TA::5+125OC

-

45

-

60

ns

X, Y, RND Setup Time

TS

9,10,11

-550C < TA:::: +125 0 C

18

20

-

ns

Clock HIGH Pulse
Width

TpWH

9,10,11

-550C ::::TA:::: +125 0 C

15

-

20

-

ns

Clock LOW Pulse
Width

TpWL

9,10,11

-55°C :5,TA::S: +125 6 C

15

-

20

-

ns

TpDSEL

9,10,11

-55°C :STA ::S:+125 0 C

-

25

-

30

ns

Output Clock to P

TpDP

9,10,11

-550C::5 TA::S: +125 0 C

-

25

ns

TpDY

9,10,11

-55°C 
::E

/tMU17/883.
Packaging t
68 PIN CERAMIC PIN GRID ARRAY

.120
.140
.040
.060

l
I

I
I

.
.
SEA TING PLANE

.080

.

~rT20

1.140
1.180
.100
1.000

BSe

BSe

B

A

9

10

11 [

:.

.~.

.003 MIN

~
1. INCREASE MAXIMUM LIMIT BY .003"· WHEN SOLDER·
DIP. OR TIN PLATE LEAD . FINiSH APPLIES.

LEAD MATERIAL: Type B
LEAD FINISH: Type C
PACKAGE MATERIAL: Ceramic, AI203 9.0%
PACKAGE SEAL:
Material: Gold/Tin
Temperature: 32()OC ± 1QoC
Method: Furnace Braze

NOTE: All Dimensions are

~:x

INTERNAL LEAD WIJlE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultr~sonic Wedge
. COMPLIANT OUTLINE: 38510 P-AC

.

tMil-M-38510 Compliant Materials, Finishes, and Dimensions.

Dimensions are in inches.

2-28

HMA510

mlHARRIS

16 x 16-Bit CMOS Parallel
Multiplier Accumulator

May 1991

Features

Description

• 16 x 16-bit Parallel Multiplication with
Accummulation to a 35-Bit Result

The HMA51 0 is a high speed, low power CMOS 16 x 16-bit
parallel multiplier accumulator capable of operating at 45ns
clocked multiply-accumulate cycles. The 16-bit X and Y
operands may be specified as either two's complement or
unsigned magnitude format. Additional inputs are provided
for the accumulator functions which include: loading the
accumulator with the current product, adding or subtracting
the accumulator contents and the current product, and
'preloading the accumulator registers from the external
inputs.

• High-Speed (45ns) Multiply Accumulate Time
• Low Power CMOS Operation:
~ ICCSB = 500llA Maximum
~ ICCOp = 7.0mA Maximum @ 1.0MHz
• HMA510 is Compatible with the CY7C510 and the
IDT7210
• Supports Two's Complement or Unsigned Magnitude
Operations
• TTL Compatible Inputs/Outputs
• Three-State Outputs
• Available in 68 Pin Plastic Leaded Chip Carrier
(PLCC) and 68 Lead Pin Grid Array (PGA)

All inputs and outputs are registered. The registers are all
positive edge triggered, and are latched on the rising edge
of the associated clock signal. The 35-bit accumulator
output register is broken into three parts. The 16-bit least
significant product (LSPi, the 16-bit most significant prod·
uct (MSP), and the 3-bit extended product (XTP) registers.
The XTP and MSP registers have dedicated output ports,
while the LSP register shares the V-inputs in a multiplexed
fashion. The entire 35-bit accumulator output register may
be preloaded at any time through the use of the bidirectional
output ports and the preloaded control.

Block Diagram
XO ·15

RND

SUB

YO ·15 PO ·15

ClKY---r-rT----+-+---~

ClKX - -......-1---1

35

PRELOAD
ClKP

16

OEX - - - - - - - '

P16 ·31

OEM----~------~
OEl-----~------------~

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

2-29

File Number

2806

HMA510

Pinouts ,', j"

HMA510 PLCC
YOI Y1/
X14 X13 X12 XII Xl0 X9 X8 X7 X6 xs X4 X3 X2 Xl XO PO PI

•

XIS

Y2IP2
Y3IP3

RND

Y4/P4

SUB

Y5/ F>5

ACC

Y6/,P6
Y7/P7
GND
GND

68 LEAD PLCC
TOP VIEW

Y6/P8
W/P9

Yl0/Pl0
Yl1/ Pll
YI21 P12
YI31 P13
Y14/P14

Y151 PIS
P18

P34

, P33 P32 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17

HMA510 CERAMIC PGA
11

NIC

XIS

RND

ACC

ClKY

TC

PREl

ClKP

P33

-OEl

SUB

ClKX

VCC

OEX

OEM

P34

P32

N/C

10

X13

X14

9

;Xll

X12

P30

P31

a

X9

Xl0

P28

P29

7

X7

X8

P28

P27

P24

P25

P22

P23

P20

P2f

PIa

Pf9

P17

a

XS

X6

5

X3

X4

4

Xf':' • X2

3

YOI
PO

2

'HIC

A

68 'LEAD
PIN GRID ARRAY
TOP VIEW

,

xo

-'Vfl
PI

YIlI
P3

Y51
P5

Y71
P7

YBI
P8

YfOI
Pl0

YI21
P12

Y141
P14

PIa

Y21
1'2

Y41
P4

Y61
P6

GND

Y91
P9

Ylll
Pll

Y131
P13

Y1S1
PIS

N/C

B

C

o

E

F

G

H

2-30

K

l

HMA510
Pin Descriptions
NAME

PLCC
PIN NUMBER

VCC

17-20

The +5V power supply pins. O.l~F capacitors between the VCC and GND pins are
recommended.

GND

53,54

The device ground.

XO-X15

1-10,63-68

I

X-Input Data. These 16 data inputs provide the multiplicand which may be in two's
complement or unsigned magnitude format.

YO-Y15/
PO-P15

45-52, 55-62

I/O

Y-lnpuVLSP Output Data. This 16-bit port is used to provide the multiplier which
may be in two's complement or unsigned magnitude format. It may also be used for
output of the Least Significant P.roduCt (PO-P15) or for preloading the LSP
register.

P16-P3

29-44

I/O

MSP Output Data. This 16-Bit port is used to provide the Most Significant Product
Output (P16-P31 ).It may also be used to preload the MSP register.

P32-P34

26-28

I/O

XTP Output Data. This 3-Bit port is used to provide the Extended Product Output
(P32-P34).lt may also be used to preload the XTP register.

TC

21

I

Two's Complement Control. Input data is interpreted as two's complement when
this control is HIGH. A LOW indicates the data is to be interpreted as unsigned
magnitude format. This control is latched on the rising edge of CLKX or CLKY.

ACC

14

I

Accumulate Control. When this control is HIGH, the accumulator output register
contents are added to or subtracted from the current product, and the result
is stored back into the accumulator output register.

TYPE

DESCRIPTION

When LOW, the product is loaded into the accumulator output register overwriting
the current contents. This ..control Is also latched on the rising edge of CLKX or
CLKY.
SUB

13

I

Subtract Control. When both SUB and ACC are HIGH, the accumulator register
contents are subtracted from the current product. When ACC is HIGH and SUB is
LOW, the accumulator register contents and the current product are summed. The
SUB control input is latched on the rising edge of CLKX or CLKY.

RND

12

I

Round Control. When this control is HIGH, a one is added to the most significant
bit of the LSP. When LOW, the product is unchanged.

PREL

23

I

Preload Control. When this control is HIGH, the three bidirectional ports may be
used to preload the accumulator registers. The three-state controls (OEX, OEM,
OEL) must be HIGH, and the data will be preloaded on the rising edge of CLKP.
When this control is LOW, the accumulator registers function in a normal manner.

OEL

11

I

Y-lnpuVLSP Output Port Three-state Control. When OEL .is HIGH, the output
drivers are in the high impedance state. This state is required for V-data input
or preloading the LSP register. When OEL is LOW, the port is enabled for LSP
output.

OEM

24

I

MSP Output Port Three-state Control. A LOW on this control line enables the port
for output. When OEM is HIGH, the output drivers are in the high impedance state.
This control must be HIGH for preloading the MSP register.

OEX

22

I

XTP Output Port Three-state Control. A LOW on this control line enables the port
for output. When OEX is HIGH, the output drivers are in the high impedance state.
This control must be HIGH for preloading the XTP register.

CLKX

15

I

X-Register Clock. The rising edge of this clock latches the X-data input register
along with the TC, ACC, SUB and RND inputs.

CLKY

16

I

V-Register Clock. The rising edge of this clock latches the V-data input register
along with the TC, ACC, SUB and RND inputs.

CLKP

25

I

Product Register Clock. The rising edge of CLKP latches the LSP, MSP and XTP
registers. If the preload control is active, the data on the I/O ports is loaded into
these registers. If preload is not active, the accumulated product is loaded into the
the registers.

2-31

HMA510
Functional Description

PRELOAD FUNCTION TABLE

The HMA510 is a high speed 16 x 16-bit multiplier
accumulator (MAC). It consists of a 16-bit parallel multiplier
follower by a 35-bit accumulator. All inputs and outputs are
registered and are latched on the rising edge of the
associated clock signal. The HMA510 is divided into four
sections: the input section, the multiplier array, the
accumulator and the outpuVpreload section.

OUTPUT REGISTERS
PREL

0Ex

i5'EM

OEL

XTP

MSP

LSP

0

0

0

0

Q

Q

Q

0

0

0

1

Q

Q

Z

0

0

1

0

Q

Z

Q

The input section has two 16-bit operand input registers for
the X and Y operands which are latched on the rising edge
of ClKX and ClKY respectively. A four bit control register
(TC, RND, ACC, SUB) is also included and is latched from
either of the input clock sighals.

0

0

1

1

Q

Z

Z

0

1

0

0

Z

Q

Q

0

1

0

1

Z

Q

Z

0

1

1

0

Z

Z

Q

The 16 x 16 multiplier array produces the 32-bit product of
the input operands. Two's complement or unsigned
magnitude operation can be selected by the use of the TC
control. The 32-bit result may also be rounded through the
use of the RND control. In this case, a '1' is added to the
MSB of the lSP (bit P15). The 32-bit product is zero-filled
or sign-extened as appropriate and passed as a 35-bit
number to the accumulator section.

0

1

1

1

Z

Z

Z

1

0

0

0

Z

Z

Z

1

0

0

1

Z

Z

PL

1

0

1

0

Z

PL

Z

1

0

1

1

Z

PL

PL

1

1

0

0

PL

Z

Z

The accumulator functions are controlled by the ACC, SUB
and PREl control inputs. Four functions may be selected:the accumulator may be loaded with the current product;
the product may be added to the accumulator contents; the
accumulator contents may be subtracted from the current
product; or the accumulator may be loaded from the
bidirectional ports. The accumulator registers are updated
at the rising edge of the ClKP signal.

1

1

0

1

PL

Z

PL

1

1

1

0

PL

PL

Z

1

1

1

1

PL

PL

PL

The output/preload section contains the accumulator/
output register and the bidirectional ports. This section is
controlled by the signals PREl, OEX, OEM and OEL. When
PREl is high, the output buffers are in a high impedance
state. When one of the controls OEX, OEM or 00 are also
high, data present at the outputs will be preloaded into the
associated register on the rising edge of ClKP. When PREl
is low, the signals OEX, OEM and OEl are enable controls
for their respective three-state output ports.

Z

= Output Buffers at High Impedance (Disabled).

Q

=

Output Buffers at LOW Impedance. Contents of Output Register
Available Through Output Ports.

PL = Output disabled. Preload data supplied to the output pins will be
loaded into the register at the rising edge of elKP.

2-32

ACCUMULATOR FUNCTION TABLE
PREL

ACC

SUB

P

OPERATION

L

L

X

Q

Load

L

H

L

Q

Add

L

H

H

Q

Subtract

H

X

X

PL

Preload

HMA510
INPUT FORMATS
Fractional Two's Complement Input

y

x

L..:II~5~14---.:.13=--:1~2-=.;:---.:.1O=--:9_-=-----'------'6_'------'4----"----''----~1---C....JOI liS

6
4
2
01
14 13 12 II 10 9
_20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-92-102-112-122-1l2-142-15
(Sign)

_20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2- 10 2-112-122-132-142-15
(Sign)

Integer Two's Complement Input
y

X

liS

14 13

12

II

6

10

4

2

_215214 213 212 211 210 29 2 8 27 26 2 5 24 23 22
(Sign)

21

01
20

liS

12 11

14 13

10

9

4

_215214 21l 212 211 210 29 28 27
(Sign)

2

26 2 5 24 2 3 22

01
21

20

Unsigned Fractional Input
X

y

I liS

liS

14 13 12 11 10 9
6
4
I 0
"-2_-1-2--2-2--3-2--4-2--5-2--6-2--7-2--8-2--9-2--10-2--11-2--12-2--13-2--14-2--15-2--'16

654
14 13 12 II 10 9
01
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-122-132-142-152-16

Unsigned Integer Input
y

X

OUTPUT FORMATS
Two's Complement Fractional Output
XTP

MSP

LSP

1343332113130292827262524232221 20
_2423 22
(Sign)

19

18

17

4
6
01
2-152-162-172-182-192-202-21 2-222-232-242-252-262-212-282-292-30

161115

21 202-1 2-22-32-42-52-62-72-82-92-102-11 2-122-132-14

14

13

12

II

10

9

Two's Complement Integer Output
XTP
134

MSP

LSP

33 321131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161115 14 13

_234 233 232
(Sign)

231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216

12

II

10 9 8

7

6 5 4 3 2

I 0

I

215 214 21l 212 211 210 29 28 27 26 25 24 23 22 21 20

Unsigned Fractional Output
XTP

MSP

LSP

134333211313029282726252423 22 .21

20

19

18

17

161115

14 1312

11

10

9

4

I

0

I

2221 20 2-12-22-32-42-52-62-72-82-92-102-11 2-12 2-13 2-14 2-15 2-16 2-172-182-192-202-21 2-222-232'242-252-262-272-282-29.2-302-31 2-32

Unsigned Integer Output
XTP

MSP

134 33 321131

LSP

30 29 28 27 26 25 24 23 22 21 20 19 18 17 161115 14 13

I

2-33

12

11

10 9 8

7

6 5 4 3 2

I

oj

Specifications HMA510
Absolute Maximum Ratings

Operating CondItions

Supply Voltage •••..••••..• , •••••••.•.••••..••••••••••• +8.0V Operating Voltage Range ••••••••••.•••••.••• +4.75V to +5.25V
Input, Output or I/O Voltage Applied .•.. G ND -0.51/ to VCC +0.5V
Operating Temperature Range ••••••••••••.•••... OoC to + 700C
Storage Temperature Range ••••...•••.•..•.. -65 0 C to +150 0 C
Reliability Information
Gate Count •••••••••••.•••••..•.
4800 Gates
Oja •••••.••••••••••••••.•• 43.2 0 C/W (PLCC), 42.690 C/W (PGAl
Junction Temperature ...••• , '<' ••• 1500 C (PLCCl, +175OC (PGAl
Lead Temperature (Soldering, Ten Seconds) •• ; , ••..••.• +3000 C
0jc •••.•.••••••••••••••.••• 15.1 oc/w (PI-CCl, 1O.Ooc/W (PGAl
ESD Classification •..•...•...••••.•••••••••.••...•.••• Class 1 , Maximum Package Power Dissipation at 700 C .••••• 1.7W (PLCC)
2.46/W (PGAl
<• • • • • • • • • • • • • • • • •

D.C. Electrical Specifications (Vcc = 5.0V ±5%, TA = OOc to H00C)
PARAMETER

SYMBOL

MIN

Logical One Input Vo~age

VIH

2.0

-

V

VCC = 5.25V

Logical Zero Input Vo~ge

VIL

-

0.8

V

VCC=4.75V

Output HIGH Voltage

VOH

2.6

-

V

10H = -400"A, VCC = 4.75V

Output LOW Voltage

VOL

-

0.4

V

10L = +4.0mA, VCC = 4.75V
VIN = VCC or GND, VCC = 5.25V

f = 1.0MHz, VIN = VCC or GND
VCC = 5.25V (Note 1l

I n put Leakage Current

MAX

UNITS

II

-10

10

10

-10

10

Standby Power Supply Current

ICCSS

-

500

IlA
IlA
IlA

Operating Power Supply Current

ICCOp

-

7.0

rnA

SYMBOL

MIN

MAX

UNITS

CIN

-

10

pF

COUT

10

pF

CI/O

-

15

pF

Output or 110 Leakage

C~rrent

TEST CONDITIONS

VOUT = VCC or GND, VCC = 5.25V
VIN = VCC or GND, VCC = 5.25V, Outputs Open

Capacitance (TA = +250 C, Note 2l
<

PARAMETER

Input Capacitance
Output Capacitance
I/O Capacitance

TEST CONDITIONS
FREQ = 1 MHz, VCC = Open all Measurements
are Referenced to Device Ground.

NOTES:
1. Operating Supply Current is proportional to frequency. typical rating is

2. Not tested, but characterized at initial design and at major process/design

S.OmNMHz.

changes.

A.C. Electrical Specifications (VCC = 5.0V ±5%, TA = oOC to +700 C)

PARAMETER

SYMBOL

HMA51 0-45

HMA51 0-55

MIN

MAX

MIN

MAX

UNITS

45

-

55

ns

25

-

30

ns

30

ns

Note 1

30

ns

Note 1

-

20
2

ns

-

20
20

-

8

-

8

ns

From 0.8V to 2.0V

8

-

8

ns

From 2.0V to 0.8V

3-State Enable Time

TENA

3-State Disable Time

TDIS

-

Input Setup Time

TS

18

Input Hold Time

TH

2

TpWH

15

TpWL

15

Multiply Accumulate Time

TMA

Output Delay

Clock High Pulse Width
Clock Low Pulse Width

TD

,

Output Rise Time

TR

Output Fall Time

TF

25
25

-

«<

TEST CONDITIONS

ns
ns

<

ns

NOTES:
1. Transition is measured at :t2oomV from steady state voltage wnh loading
specified in A.C. Test Circuit; V1 - 1.SV, R1 - soon and CL a 4OpF.

2. For A.C. Test load, refer to A.C. Test CircuH wHh V1 = 2.4V, R1 = 5000
and CL = 40pF.

CAUTION: These devices are sensitive to electrostatic discharge. Proper tC. handling procedures should be followed.

2-34

HMA510
A.C. Test Circuit

A.C. Testing Input, Output Waveforms

V"",--- VOH
-J7""'\ 1.5'1
VOL

3.0V - - -.....~

ov

1.5V7"':......_ _ _ _ _ _

A.C. Testing:

*Includes Stray and Jig Capacitance

All Parameters tested as per test circuit.
Input rise and fall times are driven at 1nsN.

Timing Diagram
SET-UP AND HOLD TIME

DATA
INPUT

)OOOOOOOC t~

>OOOOoc)(

I

THREE STATE CONTROL

T8

TH

I

THREE
STATE
CONTROL

OV

~~~~ =============.~~~=.=='============!J~

TOIS 1-----1

OUTPUT - - - - - ,
THREE
STATE

HMA510 TIMING DIAGRAM

PRELOAD TIMING DIAGRAM

TpWL

TpWH

TpWH

cUk----

2-35

"'"~t;::i::=~/-::'7'V"":7"'::"",,,""7-::'7'V"":~A"'7

mHARRIS

'HMA51 0/883
16

May 1991

16-Bit CMOS Parallel
Multiplier Accumulator

X

Features

Description

• This Circuit is Processed in Accordance to Mil-Std883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

The HMA510/883 is a high speed, low power CMOS
16 x 16-bit parallel multiplier accumulator capable of operating at 55ns clocked multiply-accumulate cycles. The
16-bit X and V operands may be specified as either two's
complement or unsigned magnitude format. Additional
inputs are provided for the accumulator functions which
include: loading the accumulator with the !TA.s +1250 C

30

-

30

-

35

ns

"

Output Delay
3-State
Enable Time

(Note 2)

TENA

NOTES:
1, AC Testing as follows: Input levels OV and 3,OV (OV and 3,2V for clock
Inputs), Timing reference levels = 1 JjV. Input rise and fall times driven at
1nsN, Output load per test load circuit, with V1 = 2.4V, R1 = soon and
CL = 40pF.
'

T!,I.BLE 3. HMA51 0/883

2. Transijion is measured at ±200mV from steady state voltage,Output
loading per test load circuit, wijh V, = 1.5V, R, = soon and CL= 40pF.

ELECT~ICAL

PERFORMANCE CHARACTERISTICS
-55

PARAMETI;R

SYMBOL

CONDITIONS

NOTE

TEMPERATURE

MIN

CIN

VCc=Open,
f=1MHz All
measurements are
referenced to
devlceGND.

1

TA=+250C

1

TA=+250C

1

TA=+250C

-

Input Capacitance,
Output Capacitance

VO Capacitance

COUT
CVO

.

-75

-6,5

MAX ,MIN MAX MIN

15

-

10
10

15

-

10
10

MAX UNITS
10

pF

10

pF

15

pF

Input Hold Time

TH

1

-550C!5 TA.s +1250 C

3

-

3

-

3

-

ns

3-State Disable
Time

TDIS

1

-55°C 5, TAS +1250 C

-

30

-

30

-

30

n8

-

10

-

10

-

10

n8

10

10

ns

Output Rise Time
Output Fall Time

TR

From 0.8V to 2.0V

1

-5SOCSTAS +12506

TF

From 2.0V to 0.8V

1

-550C.s TAS +1250 C

10

NOTE:
1. The parameters listed in Table 3 are controlled via design ~r process parameters and afe nof directly tested. These parameters "are characterized
upon initial design and after major process and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

Initial Test

100%/5004

Interim Test

100%/5004

SUBGROUPS

-

PDA

100%

1

FinalTest

100%

2,3, 8A, 8B, 10,11

-

1,2,3, 7,8A, 8B,9,10,11

SamplesJ5005

1,7,9

Group A
GroupsC&D

CAUTION: These devices are sensitive to electrostatic discharge. Proper IC handUng procedures should be followed.

2-38

HMA510/883
A. C. Testing Inputf Output Waveform

Test Load Circuit

..JX

VIH - - - . . . ,
VIL

1.5V

~'-_ _ _ _ _ _

A.C. Testing:
"'Includes Stray and Jig Capacitance

, . . - - - - V OH

1.5V

All Parameters tested as per test circuM.
Input rise and fall times are driven at 1nsN.

Timing Diagram
SET-UP AND HOLD.TIME

I~~~~

THREE STATE CONTROL

)OOOOO()()( ~:~

)S200()()()(

THREE
STATE
CONTROL

~~~~ ======I=}:.....Sf====== ~

OUTPUT -----~
THREE
STATE

HMA5l0 TIMING DIAGRAM

PRELOAD TIMING DIAGRAM

TPWL
TpWH
CLIO(
CLKY

TH

~

XIN, YIN
RND, TC ~
ACC, SUB

)l(.XXX

CLKP

---

TMA

-

I-- THCL
X

XXX

To

f--OUTPUT P, Y

HIGH IMPEDANCE

>-----------<1

XXXX X XX X X X X X X*______

2-39

HMA510/883
Burn-In. Circuit
N/C

X1.

RNO

ACC

CLKY

TC

PREL

CLKP

paa

X1.

X14

DEL

SUB

CLKX

VCC

0Ei

OEM

P34

P ••

NlC

X11

X1,

P3D

P.,

X9

X1.

P'.

P.9

X7

X.

P'B

P'7

P.4

P••

11

10

X.

68 LEAD
PIN GRID ARRAY

XB

TOP VIEW

4

Xa

X4

P ••

P,.

X1

X.

P20

P.,

YO/
.. 0

xo

P18

P19

P18

P17

N/C

V1/
P1

V3/
P.

V./
P.

Y7/
P7

V8/
P8

V101

Y12/

P1.

P1'

Y14!
P14

VO/
P,

V4/
P4

VB/
P8

"NO

VO/
P9

Y11/

Y13!

Y15/

P11

P1.

P1.

C

o

A

PGA
PIN

PIN
NAME

BURN-IN
SIGNAL

PGA
PIN

PIN
NAME

H/C

K

G

BURN-IN
SIGNAL

PGA
PIN

PIN
NAME

BURN-IN
SIGNAL

PGA
PIN

PIN
NAME

BURN-IN
SIGNAL

66

X6

F1

F1

Y9/P9

F2

K7

P26

VCC/2

E11

ACC

F1

A6

X5

F2

G2

Y10/P10

F3

L7

P27

VCC/2

010

SU6

F2

65

X4

F3

Gl

Y11/P11

F5

KS

P2S

VCC/2

011

RNO

F3

A5

X3

F4

H2

Y12/P12

F4

L8

P29

VCC/2

C10

OEL

VCC

VCC/2

C11

X15

FS

X14

F9

.

64

X2

F5

H1

Y131P13

F4.·

K9

P30

A4

X1

F6

J2.

Y14/P14

FS

L9

P31

VCC/2

610

63

XO

F7

J1

Y15/P15

F9

K10

P32

VCC/2

A10

X13

F10

A3

YO/PO

FS

K2

P16

VCC/2

K11

P33

VCC/2

B9

X12

F11

62

Y1/P1

F9

L2

P17

VCC/2

J10

P34

VCC/2

A9

X11

F12

61

Y2/P2

F10

K3

P1S

VCC/2

J11

CLKP

FO

6S

X10

F13

C2

Y3/P3

F11

L3

P19

VCC/2

H10

OEM

GND

AS

X9

F14

C1

Y4/P4

F12

K4

P20

VCC/2

H11

PREL

F6

B7

XS

F15

02

Y5/P5

F13

L4

P21

VCC/2

G10

OEX

GND

A7

X7

F7

01

Y6IP6

F14

K5

P22

VCC/2

G11

TC

F5

A2

N.C.

N.C.

E2

Y7/P7

F15

L5

P23

Vcc/2

F10

VCC

VCC

K1

N.C.

N.C.

E1

GND

GND

K6

P24

Vcc/2

F11

CLKY

FO

l10

N.C.

N.C.

F2

YS/PS

F1

L6

P25

VCC/2

E10

CLKX

FO

B11

N.C.

N.C.

NOTES:
1. Vee
2. FO

= 5.5V

+0.5V/-0.OV with 0.1pF decoupling capacitor to GND

= 100kHz. F1 =FO/2. F2 = F1/2 • •..•.•.•.• 10%

3. VIH = Vee - 1V ± 0.5V (Min). VIL

4. 47kO load resistors used on all pins except Vee and GND (Pin-Grid
identifiers F1 O. G 1O. G 11 and H 11 )

= 0.8V (Max)

2-40

HMA510/883
Die Characteristics
DIE ATTACH:
Material: Si-Au Eutectic Alloy
Temperature: Ceramic PGA - 4200 C (Max)

DIE DIMENSIONS:
184 x 176 x 19 ± 1 mils
METALLIZATION:
Type: Si-AI
Thickness: 8kA

WORST CASE CURRENT DENSITY: 0.9 x 105A/cm 2

GLASSIVATION:
Type: Nitrox
Thickness: 10kA

Metallization Mask Layout
HMA51 0/883

..

x

x...

...x x'"

.

x

o
... x., x'" X
X
... ...

x

..

... ...

x x
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Y2/P2 60

NC

c..

5

Y3/P3 59

11

X15

Y4/P4 58

12

OEL

Y5/P5 57

13

RND

Y6/P6 56

14

SUB

Y7/P7 55

15

ACC

16

CLKX

17

CLKY

18

Vcc

19

Vce

20

TC

GND 54

GND 53

Y8/P8 52
Y9/P9 51
Y10/P10 50
Y11/P11 49
21

OEX

22

PREL

23

OEM

24

CLKP

25

P34

Y12/P12 48
Y13/P13 47
·Y14/P14 46
Y15/P15 45
P16 44

...... ...'"
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HMA510/883
Packaging t
68 PIN CERAMIC PGA

.120

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1.180

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1.000

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1. INCREASE MAXIMUM LIMIT BY .003" WHEN SOLDER
DIP OR TIN PLA~ LEAD FINISH ApPLIES.

LEAD. ¥ATE.~I~L:; Type B
LEAD FINISH: ,Type C
PACKAGEIViATERIAL: CeramicAI203 90%
PACKAGE SEAL:
Material: Gold/Tin
Temper,atu ri{ 3200 C ± '1 OoC
Method:. Fu'rnac~ Braze

NOTE: All Dimensions are

INTERNAL LEAD WIRE:
Material: Aluminum
, Diameter: 1.25 Mil
Bonding Method: Ultrasonic Wedge
COMPLIANT 38510 OUTLINE: P-AC

..Ml!:!... • Dimensions are in inches.

tMil-M-38510 Compliant Materials, Finishes. and Dimensions.

Max

2-42

ONE DIMENSIONAL FILTERS
PAGE

DATA SHEETS
HSP43220

Decimating Digital Filter ......................................................• 3-3

HSP43220/883

Decimating Digital Filter ..........................•............................ 3-23

DECI • MATE

Harris HSP43220 Decimating Digital Filter Development Software .................. . 3-31

HSP43891

Digital Alter ................................................................. . 3-35

HSP43891/883

Digital·Alter ..•..•......................................•..................... 3-50

HSP43881

Digital Filter ..•...•.•..•..............•..........................•.....•....... 3-58

II:

HSP43881/883

Digital Filter .............................................•.................... 3-73

!:i

HSP43481

Digital Alter ..•..............•..•........••....•........•..................... 3-81

aI

HSP43481 1883

Digital Filter •.....•......•...............................•..•.....•........... 3-96

HSP43168

Dual FIR Filter ...•....•....•....•.......................•...........•.•....... 3-102

3-1

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HSP43220

HARRIS

Decimating Digital Filter

May 1991

Features

Description

• Single Chip Narrow Band Filter with up to 96dB
Attenuation

The HSP43220 Decimating Digital Filter is a linear phase
low pass decimation filter which is optimized for filtering
narrow band signals in a broad spectrum of a signal
processing applications. The HSP43220 offers a single
chip solution to signal processing application which have
historically required several boards of IC's. This reduction in
component count results in faster development times as
well as reduction of hardware costs.

• DC to 33MHz Clock Rate
.16 Bit 2's Complement Input
• 20 Bit Coefficients in FIR
• 24 Bit Extended Precision Output
• Programmable Decimation up to a Maximum of
16,384
• Standard 16 Bit Microprocessor Interface
• Filter Design Software Available DECI.MATE'"
• Available in 84 Pin PGA and PLCC

Applications
• Very Narrow Band Filters
• Zoom Spectral Analysis

The HSP43220· is implemented as a two stage filter
structure. As seen in the block diagram, the first stage is a
high order decimation filter (HDF) which utilizes an efficient
decimation (sample rate reduction) technique to obtain
decimation up to 1024 through a coarse low-pass filtering
process. The HDF provides up to 96dS aliasing rejection in
the signal pass band. The second stage consists of a finite
impulse response (FIR) decimation filter structured as a
transversal FIR filter with up to 512 symmetric taps which
can implement filters with sharp transition regions. The FIR
can perform further decimation by up to 16 if required while
preserving the 96dS aliasing attenuation obtained by the
HDF. The combined total decimation capability is 16,384.
The HSP43220 accepts 16 bit parallel data in 2's
complement format at sampling rates up to 33MSPS. It
provides a 16 bit microprocessor compatible interface to
simplify the task of programming and three-state outputs to
allow the connection of several IC's to a common bus. The
HSP43220 also provides the capability to bypass either the
HDF or the FIR for additional flexibility.

• Channelized Receivers
• Large Sample Rate Converter
• Instrumentation
• 512 Tap Symmetric FIR filtering

Block Diagram
DECIMATION UP TO 1024
INPUT CLOCK
DATA INPUT
CONTROL
AND
COEFFICIENTS

",16
,,16

,

DECIMATION UP TO 16

l

l

HIGH ORDER
DECIMATION
FILTER

FIR
DECIMATION
FILTER

I

_,"24

T

DATA OUT
DATA
READY

FIR CLOCK

DECI' MATEN is a registered trademark of Harris Corporation.
IBM Pc ... XT1IiI. AT III , PS/2- are registered trademarks of mternational Business Machines, Inc.
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-3

File Number

2486.2

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HSP43220

.~

:Packlige Pinouts
84 PIN GRID ARRAY (PGA)

'0
L

.&•.&•.&•...2. JLDht. 0 09A... oQA... DPA:..:"D~1_
oo66cro~
o 0 0 0
c....aus
66' 'ENooo
o 0
out-

OUT 23 CUT 21 OUT 20 OUT 18

CLBUS (LJIUS

GND

H

0

CJK,IS OUL-

CLBUS

6

.....

Vee

GNO

GND

Fit-

DATA.... DATA- DATA... DATA....
OUT 22 OUT , . OUT 17 OUT 16
DATA... DATA....

eK

~s Vee
G

.&•.&•.&.
12

11

13

000

(LBUS C-BUS (LBUS

000

~'.

()14

DA~A...

DATA-

OUT 18 OUT 12

HSP43220
BOTTOM VIEW
PINS

UP

9.

09A...
000

DQA...

OUT 10

~:~~

o

Vee

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OUT 11

~~~

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DATA- DATA- DATA...
OUT 5
8 OUT 7

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DATA.... DATA....

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OUTO

OUT.

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DATA....
OUT,

0
0

GND

84 PLASTI.C LEADED CHIP CARRIER (PLCC)

•

GND

DATA....OUT D
DATA...DUT 1
DATA..DUT 2
DATA..OUT 3

DATA...DUT 4
DATA....OUT S
DATA..OUT8
DATA..OUT 7

84 LEAD PLCC

'aAl-AlDOra
..oAT~Ta·

DATA..DUT 10
DAT~Tl1

GND

Vee
DATA....OUT 12
DATA.DUT 13

DATA.£jUT 1-4

DATA...DUT

us

DATA...,OUT 18

DATA....OUT 17

0
0

lIND

,

HSP43220
Pin Description
DESCRIPTION

NAME

PLCCPIN

TYPE

VCC

13,28,42, 45,
60,75,78

The +5V power supply pins.

GND

11,29,43,46,
61,74,77

The device ground.

CK....JN

76

I

Input sample clock. Operations in the HDF are synchronous with the rising edge of this
clock signal. The maximum clock frequency is 33M Hz. CK.....IN is synchronous with FI~CK
and thus .the two clocks may be tied together if required, or CICJN can be divided down from
FIR CK. CK.....IN is a CMOS level signal.

FIR_CK

44

I

Input clock for the FIR filter. This clock must be synchronous with CICJN. Operations in
the FIR are synchronous with the rising edge of this clock signal. The maximum clock
frequency is 33 MHz. FIR CK is a CMOS level Signal.

DINO-15

1-10,79-84

I

Input Data bus. This bus is used to provide the 16-bit input data to the HSP43220. The data
must be provided in a synchronous fashion, and is latched on the rising edge of the
CIC..IN signal. The data bus is in 2's complement fractional format.

C_BUSO-15

21-27,30-38

I

Control Input bus. This input bus is used to load all the filter parameters. The pins WR#, CS#
and AO , A 1 are used to select the destination of the data on the Control bus and write the
Control bus data into the appropriate register as selected by AO and A 1.

DATA.....OUT

48-59,62-73
0-23

0

Output Data bus. This 24-Bit· output port is used to provide the filtered result in 2's
complement format. The upper 8 bits of the output, DATA.....OUT16-23 will provide extension
or growth bits depending on the state of OUT_SELH and whether the FIR has been put in
bypass mode. Output bits DATA.....OUTO-15 will provide bits 2 0 through 2- 15 when the FIR
is not bypassed and will provide the bits 2- 16 through 2-31 when the FIR is in bypass mode.

DATA.....RDY

47

0

An active high output strobe that is synchronous with FIR_CK that indicates that the result
of the just completed FIR cycle is available on the data bus.

RESET#

16

I

RESET# is an asynchronous signal which requires that the input clocks CK.....IN and FIR_CK
are active when RESET# Is asserted. RESET# disables the clock divider and clears all of the
internal data registers in the HDF. The FIR filter data path is not initialized. The control register
bits that are cleared are F BYP,H STAGES, and H DRATE. The F DIS bit is set.

WR#

19

I

Write strobe. WR# is used for loading the internal registers of the HSP43220. When CS#
and WR# are asserted, the rising edge of WR# will latch the C_BUSO-15 data into the
register specified by AO and A 1.

CS#

20

I

Chip Select. The Chip Select Input enables loading of the internal registers. When CS# and
WR# are low, the AO and A1 address lines are decoded to determine the
destination of the data on C_BUSO-15. The rising edge of WR# then loads the appropriate
register as specified by AO and A 1 •

AO,A1

18,17

I

Control Register Address. These lines are decoded to determine which control register is the
deslination for the data on C_BUSO-15. Register loading is controlled by the AO and A1,
WR# and CS# inputs.

ASTARTIN#

15

I

ASTARTIN# is an asynchronous signal which is sampled on the rising edge of CK.....IN. It is
used to put the DDF in operational mode. ASTARTIN# is internally synchronized to CK.....IN
and is used to generate STARTOUT#.

STARTOUT#

12

0

STARTOUT# is a pulse generated from the internally synchronized version of ASTARTIN#.
It is provided as an output for use in multi-chip configurations to synchronously start
multiple HSP43220's. The width of STARTOUT# is equal to the period of CICJN.

STARTIN#

14

I

STARTIN# Is a synchronous input. A high to low transition of this signal is required to start
the part. STARTIN# is sampled on the rising edge of CK.....IN. This synchronous signal
can be used to start single or multiple HSP43220's.

OUT_SELH

39

I

Output Select. The OUT_SELH input controls which bits are provided at output pins
DATA.....OUT16-23. A HIGH on this control line selects bits 28 through 21 from the
accumulator output. A LOW on this control line selects bits 2- 16 through 2-23 from the
accumulator output. Processing is not interrupted by this pin.

OUT_ENP#

40

I

Output Enable. The OUT_ENP# input controls the state of the lower 16 bits of the output
data bus, DATA.....OUTO-15. A LOW on this control line enables the lower 16 bits of the
output bus. When OUT_ENP# is HIGH, the output drivers are in the high impedance state.
Processing is not Interrupted by this pin.

OUT_ENX#

41

I

Output Enable. The OUT_ENX# input controls the state of the upper 8 bits of the output
data bus, DATA.....OUT16-23. A LOW on this control line enables the upper 8 bits of the
output bus. When OUT_ENX# is HIGH, the output drivers are in the high impedance state.
Processing is not interrupted by this pin.

3-5

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HSP43220
The HOF

implemented as an adder followed by a register in the feed
forward path. The integrator is clocked by the sample clock,
CLIN as shown in Figure 2. The bit width of each
integrator stage goes from 66 bits at the first integrator
down to 26 bits at the output of the fifth integ rator. Bit
truncation is performed at each integrator stage because
the data in the integrator stages is being accumulated and
thus is growing, therefore the lower bits become
insignificant, and can be truncated without losing significant
data.

The first filter section is called the High Order Decimation
Filter (H DF) and is optimized to perform decimation by large
factors. It implements a low pass filter using only adders
and delay elements instead of a large number of multiplier/
accumulators that would be required using a standard FIR
filter.
The HDF is divided into 4 sections: the HDF filter section,
the clock divider, the control register logic and the start
logic (Figure 1).

There are three signals that control the integrator section;
they are H_STAGES, H_BYP and RESET#. In Figure 2
these control signals have been decoded and are labelled
INT_EN1 - INT_EN5. The order of the filter is loaded via
the control bus and is called H_STAGES. H_STAGES is
decoded to provide the enables for each integrator stage.
When a given integrator stage is selected, the feedback
path is enabled and the integrator accumulates the current
data sample with the previous sum. The integrator section
can be put in bypass mode by the H_BYP bit. When
H_BYP or RESET# is asserted, the feedback paths in all
integrator stages are cleared.

Data Shifter
After being latched into the Input Register the data enters
the Data Shifter. The data is positioned at the output of the
shifter to prevent errors due to overflow occurring at the
output of the HDF. The number of bits to shift is controlled
by H_GROWTH.
Integrator Section
The data from the shifter goes to the Integrator section. This
is a cascade of 5 integrator (or accumulator) stages, which
implement a low pass filter. Each accumulator is
/10 -1

WR.#

CS.#

C

BUS

CK...IN
H

RESET.#

RESET.# CK...IN ASTARTIN.#

ORATE
CLOCK
DIVIDER

BY?

H

ISTART

START
LOGIC

STARTOUT.#

5
H- GROWTH

I NT_ EN1 -5 COMB EN1 -5
-

CK...DEC

HDF FILTER SECTION
ISTART

H GROWTH

INT_EN1 -5

RESET.#

RESET.#

TO FIR

16

TO FIR

FIGURE 1. HIGH ORDER DECIMATION FILTER

FROM
SHIFTER

CK..IN

FIGURE 2. INTEGRATOR

3-6

HSP43220
Decimation Register
The output of the Integ rator section is latched into the
Decimation Register by CLDEC. The output of the
Decimation register is cleared when RESET# is asserted.
The HDF decimation rate = H_DRATE +1. which is defined
as Hdec for convenience.
Comb Filter Section
The output of the Decimation Register is passed to the
Comb Filter Section. The Comb section consists of S
cascaded Comb filters or differentiators. Each Comb filter
section calculates the difference between the current and
previous integrator output. Each Comb filter consists of a
register which is clocked by CLDEC. followed by an
subtractor. where the subtractor calculates the difference
between the input and output of the register. Bit truncatfons
are done at each stage as shown in Figllre 3. The first stage
bit width is 26 bits and the output of the fifth stage is 19 bits.

The Rounder performs a symmetric round .of the 19' bit
output of the last Comb stage, Symmetric rounding is done
to prevent the synthesis of a OHz spectral component by the
rounding process and thus causing a reduction in.
spurious free dynamic range, Saturation logiC is also
provided to prevent roll over from the largest positive value
to the most negative value after rounding, The output of the
last comb filter stage in the HDF section has a 16 bit integer
portion with a 3 bit fractional part in 2's complement format.
The rounding algorithm is as follows:

There are three signals that control the Comb Filter; H_
STAGES. H_BYP and RESET#. In Figure 3these'control
signals are decoded as COMB_EN1 - COMB_ENS. The
order of the Comb filter is controlled by H_STAGES. which
is programmed over the control bus. H_BYP is used to put
the comb section in bypass mode. RESET# causes the
register output in each Comb stage to be cleared. The H_
BYP and RESET# control pins. when asserted force the
output of all registers to zero so data is passed through the
subtractor unaltered. When the H_STAGES control bits
enable a given stage the output of the register is ,subtracted
from the input.
It is important to note that the Comb' filter section has a
speed limitation. The Input sampling rate divided by the
decimation factor in the HDF (CLIN/Hdec) should not
exceed 4MHz. Violating this condition causes the output of
the filter to be incorrect. When the HDF is put in bypass
mode this limitation does not apply. Equation 1,0 describes
the relationship between F.:....TAPS. F_DRATE. H_DRATE.
CLIN and FIR_CK,
Rounder
The filter accuracy is limited by the 16 bit data input. To
maintain the maximum accuracy. the output of the comb is
rounded to 16 bits,

COMILEN5

COMILEN4

POSITIVE NUMBERS
Fractional Portion Greater Than or
Equal to 0,5

Round Up

Fractional Portion Less Than 0,5

Truncate

NEGATIVE NUMBERS
Fractional Portion Less Than or
Equal to 0.5

Round Up

Fractional Portion Greater Than 0,5

Truncate

The output of the rounder is latched into the HDF output
register with CLDEC, CLDEC is generated by the
Clock Divider section. The output of the register is cleared
when RESET# is asserted,

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Clock Divider and Control Logic
The clock divider divides CLIN by the decimation factor
Hdec to produce CLDEC. CLDEC clocks the
Decimation Register. Comb Filter section. HDF output
register, In the FIR filter CLDEC is used to indicate that a
new data sample is available for processing. The clock
generator is cleared by RESET# and is not enabled until the
DDF is started by an internal start signal (see Start logic).
The Control Register logiC enables the updating of the
Control registers which contain all of the filter parameter
data, When WR# and CS# are asserted. the control
register addressed by bits AO and A 1 is loaded with the
data on the C_BUS,

COMILEN3

FIGURE 3, COMB FILTER

3-7

COMILEN2

COMILEN1

HSP43220
DDF Contro/Registers
F_Register (A1 i:: 0, AO=O)

15

,FBO

ESO

TO

14

13

o

F_TAPS
Bits TO-T8 are used to specify the number of FIR filter taps.
The number entered is one less than the number 'of taps requiFed. For example, to specify a 511 tap filter F_TAPS
would be programmed to 510.
' - - - - - - - - - . F_ORATE
Bits 00-03 are used to specify the amount of FIR
decimation. The number entered is one less than the
decimation required. For example, to specify decimation of
16, F_ORATE woutd be programmed to 15. FOr no FIR
decimation, F-.:DRATE would be set equal to o.FDRATE
.+1 is defined as Fdec.
~------------------~'F_ESYM

. BitESO is used to selectthe FIR symmetry.F_ESYM is set
equal to one to select even symmetry and set equal to zero
to select odd symmetry. When F_ESYM is one, data is
added in the pre-adder; when it is zero, data is .subtracted.
Normally set to orie.
F_BYP
Bit FBO is used to select FIR bypass mode. FIR bypass
mode is selected by setting F_BYP=l. When FIR bypass
mode is selected, the FIR is internally set up for a 3 tap even
symmetric filter, no decimation (F_DRATE=O) and F_OAD
is set equal to one to zero one side of the preadder. In FIR
bypass mode all FIR filter parameters are ignored, including
the contents of the FIR .coefficient RAM. In FIR bypass
mode the output data is brought output on the lower 16 bits
of the output bus OAT~OUT 0-15. To disable FIR bypass
mode, F_BYP is set equal to zero. When F_BYP is
returned to zero, the coefficients must be reloaded.

F_OAD
Bit FAO is used to select the zero the preaddermode. This
mode zeros one of the Inputs to the pre-adder. Zero
preadder mode Is selected by setting F_OAD equal to one.
This feature is useful when implementing arbitrary phase
filters or can be used to verify the filter coefflclEmts. To
disable the Zero Preadder mode F_OAD Is set equal to
zero.

FIGURE 4

3-8

HSP43220
DDF Control Registers
FC_Reglster (A 1

(Continued)

=0, AO =1)
C4

C19

x
15

co
14

13

12

11

10

9

8

7

c:

5

6

4

2

3

o

F_CF
Bits CO-C19 represent the coefficient data, where C19 Is the MSB.
Two writes are required to write each coefficient which is 2's
complement fractional format. The first write loads C19 through C4;
C3 through CO are loaded on the second write cycle. As the
coefficients are written into this register they are formatted into a 20
bit coefficient and written Into the Coefficient RAM sequentially
starting with address location zero. The coefficients must be loaded
sequentially, with the center tap being the last coefficient to be
loaded. See coefficient RAM, below.
FIGURE 5

H_Reglster 1 (A1

=1, AO =0)
tn

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15 14

13

12

11

7

6

5

4

3

2

H_DRATE
Bits RO-R9 are used to select the amount of decimation in the HDF.
The-amount of decimation selected is programmed as the required
decimation minus one; for instance to select decimation of 1024
H-':'DRATE Is set equal to 1023. HDRATE +1 is defined as Hdec.

H_BYP
Bit HBO is used to selact HDF bypass'mode. This mode is selected
by setting H_BYP =1. When this mode is selected the input data
passes through the HDF unfiltered. Internally H_STAGES and
H.-DRATE are both set to zero and H.-GROWTH Is set to 50.
H_REGISTER 2 must be reloaded when H_BYP Is returned to O.
To disable HDF bypass mode H_BYP=O. In this mode CLIN must
be slower than FIR-,-CK In order to-satisfy equation 1.0.
F_CLA
Bit FCO is used to select the clear aGCUmulator mode in the FIR. Thismode is enabled by setting F_CLA=l and is disabled by setting
F_CLA=O. In normal operation this bit should be set equal to zero.
This mode zeros the feedback path in the accumulator of the
multipller/accumualator (MAC). It also .alows the multipUer output to
be clocked off the chip by FIA.-CK,- thus DAT~RDY has no
meaning In this mode. This mode call be used in conjunction with the
F_OAD bit to read out the FIR coefficients from the coefficient RAM.
FJ)IS
Bit FDO is used to select the FIR disable mode. This feature enables
the RR parameters to be changed. This feature is selected by setting
F_DIS=l. This mode terminates the current FIR cycle. While this
feature is selected, the HDF contino to process data and write it into
the FIR data RAM. When the FIR re-programming is completed, the
FIR can be re-enabled either by clearing F_DIS, or by asserting one
of the start inputs, which automatically clears F_DIS.
FIGURES

3-9

u:
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.-I

HSP43220
DDF Control Registers
H_Reglster 2 (A1

15

14

13

12

(Continued)

= 1, AO =1)

11

!!

10

8

7

6

5

4

3

Bits NO-N2 are used to select the number of stages or order
of the HDF filter. The number that Is programmed in is equal
to the required number of stages. For a 5th order filter,
H_STAGES would be set equal to 5.
". ~ .;..

H-":'GROWTH
, Bits GO-G5 are used to select the proper amount of growth
bits. H_GROWTH Is calculated, using the follOWing
equation:
"
,'
H_GROWTH = 50 - CEILING
Iog(2»)
"

{H_STAGESX~og

(,",dec)1

where the CEILING { ) means use the next largest Integer'of
the result of' the value In brackets and log Is the log to the
,,""J~llSe 10.
'
'
.
.~ The value of H_GROWTH represents the pOSition of the
:, " tSe on the output of the data shIfter.
..

~,

FIGURE 7

..

' ";

~

..
.'

./

'. '.

3-10

HSP43220
Start Logic
The Start Logic generates a start signal that is used
internally to synchronously start the DDF. If ASTARTIN# is
asserted (STARTIN# must be tied high) the Start LogiC
synchronizes it to CtC-IN by double latching the signal and
generating the signal STARTOUT#, which is shown In
Figure 8. The STARTOUT# signal is then used to
synchronously start other DDFs in a multi-chip configuration (the STARTOUT# signal of the first DDF would be tied
to the STARTIN# of the second DDF). The NAND gate
shown in Figure 8 then passes this synchronized signal to
be used on chip to provide a synchronous start. Once
started, the chip requires a RESET# to halt operation.
When STARTIN# is asserted (ASTARTIN# must be tied
high) the NAND gate passes STARTIN# which is used to
provide the internal start, ISTART, for the DDF. When
RESET# is asserted the internal start signal is held
inactive, thus it is necessary to assert either ASTARTIN# or
STARTIN# in order to start the DDF.
In using ASTARTIN# or STARTIN# a high to low transition
must be detected by the rising edge of CK_IN, therefore
these signals must have been high for more than one
CtC-IN cycle and then taken low.

RESET#

The coefficients are loaded into address 01 in two writes.
The first write loads the upper 16 bits of the 20 bit
coefficient, C4 through C19. The second write loads the
lower 4 bits of the coefficient, CO th rough C3, where C 19 is
the MSB. The two 16 bit writes are then formatted into the
20 bit coefficient that is then loaded into the Coefficient
RAM starting at RAM address location zero, where the
coefficient at this location is the outer tap (or the first
coefficient value).
To reload coefficients, the Coefficient RAM Address pointer
must be reset to location zero so that the coefficients will be
loaded in the order the FIR filter expects. There are two
methods that can be used to reset the Coefficient RAM
address pointer. The first is to assert RESET#", which
automatically resets the pointer, but also clears the HDF
and alters some of the control register bits. (RESET# does
not change any of the coefficient values.) The second
method is to set the F_DIS bit in control register
H_ REGISTER1. This control bit allows any of the FIR
control register bits to be re-programmed, but does not
automatically modify any control registers. When the
programming is completed, the FIR is re-started by clearing
the F_DIS bit or by asserting one of the start inputs
(ASTARTIN# or STARTIN#). The F_DIS bit allows the filter
parameters to be changed more quickly and Is thus the
recommended reprogramming method.

a:
w

Data RAM

!:i

u::

The Data RAM stores the data needed for the filter
calculation. The format of the data is:

ISTART

2°.2-12-22-32-42-52-62-72-82-92-1°2-112-122-132-142-15

where the sign bit is in the 20 location.

' - - - - - STARTOUT #

CK..IN

The 16 bit output of the HDF Output Register is written into
the Data Ram on the riSing edge of CtC-DEC.

FIGURE 8. START LOGIC

The FIR Section
The second filter in the top level block diagram is a Finite
Impulse Response (FIR) filter which performs the final
shaping of the signal spectrum and suppresses the aliasing
components in the transition band of the HDF. This enables
the DDF to implement filters with narrow pass bands and
sharp transition bands.
The FIR is implemented in a transversal structure using a
single multiplier/accumulator (MAC) and RAM for storage of
the data and filter coefficients as shown in Figure 9. The FIR
can implement up to 512 symmetric taps and decimation up
to 16.
The FIR is divided into 2 sections: the FIR filter section and
the FIR control logiC.
Coefficient RAM
The Coefficient RAM stores the coefficients for the current
FIR filter being implemented. The coefficients are loaded
Into the Coefficient RAM over the control bus (C_BUS). The
coefficients are written into the Coefficient RAM
sequentially, starting at location zero. It is only necessary to
write one half of the coefficients when symmetric filters are
being implemented, where the last coefficient to be written
in is the center tap.

RESET# initializes the write pointer to the data RAM. After a
RESET# occurs, the output of the FIR will not be valid until
the number of new data samples written to the Data RAM
equals TAPS.
The filter always operates on the most current sample and
the taps-1 previous samples. Thus if the F_DIS bit is set,
data continues to be written into the data RAM coming from
the HDF section. When the FIR is enabled again the filter
will be operating on the most current data samples and thus
another transient response will nof occur.
The maximum throughput of the FIR filter is limited by the
use of a single Multiplier/Accumulator (MAC). The data
output from the HDF being clocked into the FIR filter by
CtC-DEC must not be at a rate that causes an erroneous
result being calculated because data is being overwritten.
The equation shown below describes the relationship
between, FIR_CK, CtC-DEC, the number of taps that can
be implemented in the FIR, the decimation rate in the HDF
and the decimation rate in the FIR. (In the Design Considerations section of the OPERATIONAL SECTION there Is a
chart that shows the tradeoffs between these parameters.)
CtC-IN[(TAPS/2)+4+Fdec]
FIR_CK'= _ _--:--:-:--=-:-_ __
Hdec Fdec

3-11

en

(1.0)

Q

I

yo-

H$P43220
This equation, ,expresses Jhe minimum FIR_CK,
called FIR"':"CK'. FIR-.:.:.CK must be the smallest Integer
multiple of CLINwhich is greater'than or eciuai to
FIR_CK'. For example,: if CLIN Is 15 MHz and
equation 1.0 indicates that FIR..:..'CK' is 29 MHz, then
FIR_CK.tnust be equal to 30 MHz. Fdec Is the decimation
rate inthe FIR {Fdec ';;, F_ORATE +1); where TAPS = the
number of taps' in the FIR for even length filters and equals
the number of tap's+1 for odd length filters.
'
Solving the above equation for the maximum number of
, '
taps:
TAPS = 2 (

FIR~~~ec

Fdec - Fdec -4)

(2.0)

In using this equation, it must be kept In mind that CLIN/
Hdec mustbe less than or equal to 4MHz (unless the HDF Is
in bypass mode in which case this limitation in the HDF
does not apply). In the OPERATIONAL SECTION under the
Design ConSiderations, there is a table that shows the
trade;'offs of these parameters. In addition, Harris provides
a software package called DECI-MATE which designs
the DDF filter from System specifications.
N

The registered outputs of the data RP.M"are added or
subtrac~ed in the 17 bit pre-adder. The F_OAD control bit
allows zeros ~o be Input Into ore side of the pre-adder. This
provides the capability to implement non-symmetric filters.
The selection of adding the register outputs for an even
sym,metric filter or for subtracting the register outputs for
odd symmetric filter Is provided by the control bit F_ESYM,
which is programmed over the control bus. When
subtraction is selected, the' new data' is subtracted from the
old data. The 17 bit output of the adder forms one input of
the multiplier/accumulator.
A control bit F_CLA provides the capability to clear the
feedback path In the accumulator such that niultlplier
output will not be accumulated, but will instead flow directly
to the output register. The bit welghtlngs of the data and
coefficients as they' are processed In the FIR Is shown
below.
Input Data (from HDF)
Pre-adder Output
CoefficIent
. Accumulator

2°.2- 1 ••• 2- 15

2l20 .2- 1 : ••• 2:- 15

20 .2-1"; •. 2- 19,
2 8 ••• '20 .2 1 ., •• 2- 34 ,

FIR Output
The 40 most signifipant bits of ll1e a~c!Jmulatorar~ latched
into the output register. TheJow,er 3 bits are, not brought to
the output. The, 4Obit~o.u,tof the output register are
selected to be output by a pair of multiplexers. This register
Is clocked by FIR-,-CK (see Figure ,9).
" '
'

There are two multiplexers that route 24 of the 40 output
bits from the output register to the output pins. The first
multiplexer selects the output register bits that will be
routed to output pins DATLOUTt6~23 and the second
multiplexer selects the output register bits that will be
routed to output pins DATA_OUTO-15.
The multiplexers are controlled ,by the control Signal F_
BYP and,the OUT_SELH ph,. F~BYP and OUT_SELH
both control the first multiplexer that selects the upper 8 bits
of the output bus, DATLOUT16-23. F_BYP conlrols the
second multiplexer that selects the lower 16 bits of the output bus, DATA_OUTO:-15. The output formatter is shown in
detail in Figure 10.
FIR Control Logic
The DATA_ROY strobe indicates that new data Is available
on the output ofthe FIR. The rising edge of OATLRDY can
be used to load the output data into an external register or
RAM.
Data Format
The DDF maintains 16 bits of accuracy In both the HDF and
FIR filter stages. The data formats and bit weightings are
shown in Figure 11.

Operational Section
Start Configurations
The scenario to put the DDF into operational mode is:' reset
the DDF by asserting the RESET# input, configure the DDF
over the control bus, and apply a start ~ignal, either by
ASTARTIN# or STARTIN#. Until the DDF is put in
operational mode with a start pulse, 'the DDF ignores all
data in puts.
To use the asynchronous start, an asynchronous' active low
pUlse is applied to the ASTARTIN# input. ASTARTIN# Is
internally synchronized to the sample clock, CLIN, and
generates STARTOUT#. This Signal is also used internally
when the asynchronous mode is selected. It puts the 0 OF in
operational mode' and allows the DDF to begin accepting
data. When the ASTARTIN# input is being used,the
STARTIN# input must be tied high to ensure proper
. operation.
"
To start the'DDF synchronously, theSTARTIN# is aSserted
with a active low pulse that has been" 'externally
synchronized to CLIN. Internally the DDF then uses this
start pulse to put the DDF in operate mode and start accept'ing data inputs. When STARTIN#is used to start the DDF
the ASTARTIN# input must be tied high to prevent false
starts.

,3:-12

HSP43220

,

FROM HDF

16"

.

16

16 x 512
DATA
RAM

20 x 256
FROM COEFFICIENT -"';''''~+I COEFFICIENT t-'----'~----.
20
FORMATTER
20'"
RAM

I MULTIPUER/
I ACCUMULATOR
I SECTION

FROM CONTROL REGISTERS
F

DRATE

F

TAPS

F

BVP

F

r-----........---......,

I
I

DIS

I
I

FIR CONTROL LOGIC

F_CLA

en
c:
w
~

FIFL-CK

;:;:

FIFL-CK

CI
I

DATA_RDY

DATA_RDY
DATA_ OUTO- 23
FIGURE 9. FIR FILTER

F

BVP = 0

OUT_SELH = 1

F

BYP

2". 2- 31

F
F

BVP

=

BVP =

0

OUT_SELH = 0
OR
F BVP =

DATA_ 0UT16 - 23

FIGURE 10. FIR OUTPUT FORMATTER

3-13

O~_ _.....,F

BVP =

F

BYP

HSP43220
INPUT DATA FORMAT
Fractional Two's Complement Input

FIR COEFFICIENT FORMAT
Fractional Two's Complement Input

119118117116115114113112111 110

I I
9

81 7

I I
6

5 141· 13

20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-92-102-112-122-132:-142-15

I

I

2

0

2-162-172-182-19

OUTPUT DATA FORMAT
Fractional Two's Complement Output

FOR: OUT_SELH = 1
F_BYP = 0

123122121 120 1191181171161
28 27 26 25 24 2~22 21

FOR: OUT_SELH
F_BYP 0

=

I

I I I

I I

115114113112111 110 9
8
7
6
5
4
3
2
0
20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-92-102-112-122-132-142-15

=0

115114113112111 110

I

9

8

7

6

5

4

3

2

I I
0

20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-102-112-122-132-142-15

123122121 120 1191181171161
2-162-172-182-192-202-212-222-23

FOR: OUT_SELH = X
F_BYP = 1

123122121 120 1191181171161
2-162-172-182-192-202-212-222-23

I I I I

I I

I I

115114113112111 110 19
8
7
6
5 14
3
2 11
0
2-182-17 2-182-192-202-212-222-232-242-252-262-27 2-282-292-302-31

FIGURE 11

3-14

HSP43220
Multi-Chip Start Configurations
Since there are two methods to start up the OOF, there are
also two configurations that can be used to start up
multiple chips.
The first method is shown in Figure 12. The timing of the
STARTOUT# circuitry starts the second OOF on the same
clock as the first. If more OOPs are also to be started
synchronously, STARTOUT# is connected to their
STARTIN#'s.

The second method to start up OOPs in a multiple chip
configu ration is to use the synch ronous start scenario.
The STARTIN# input is wired to all the chips in the chain,
and is asserted by a active low synchronous pulse that has
been externally synchronized to CLIN. In this way all
OOF's are synchronously started. The ASTARTIN# input on
all the chips is ti.ed high to prevent false starts. The
STARTOUT# outputs are all left unconnected. This
configuration is illustrated in Figure 13.

TO OTHER DDF'S

+5V-

•

STARTIN#

ASTARTIN#

+sv-- ASTARTIN#

DDF

STARTOUT#

STARTIN#

CICIN

CICIN

FIR_CK

FIR _CK

STARTOUT#

-

NC

DDF

1

1

en

a:
w

:;
u::

FIGURE 12. ASYNCHRONOUS START UP

C
I

I
+5V-

STARTIN#

ASTARTIN#

STARTOUT# f-- NC

+5V- ASTARTIN#

DDF

STARTOUT#

-

STARTIN#

CICIN

CICIN

FIR - CK

FIR_CK

I

I

I

FIGURE 13. SYNCHRONOUS START UP

3-15

DDF

f/SP43220
Chip S,t Applica1ion
The HSP43-220is ideally suited for narroW band filtering in
Communications, .Instrumentation and Signal Processing
applications. The HSP43220 'prQvides a fully integrated
.
.
solution to high order decimation filtering.
The combination of the HSP43220 and the HSP45116
(which .is a NCOM Numerically Controlled Oscillator!
Modulator) provides a complete solution to'digital receivers.
The diagram in Figure.14111ustrates this concept.
The HSP45116 down converts.. the signal of interest to
baseband, generating a real component and an imaginary

component. A HSP43220 then performs low pass filtering
and' reduces the sampling rate of .each of the signals,
The system scenario for the use. of the DDF involves a
narrow band signal that has been over-sampled. The Signal
is over-sampled in order to capture a wide frequency band
containing many narrow band signals. The NCOM is
"tuned" to the frequency of the signal of interest and
performs a complex down conversion to baseband of this
signal, which results in a complex signal centered at
baseband. A pair of DDPs then low pass filters the NCOM
output, extracting the signal of interest.

HSP45116

NCOM
HSP43220

DDF

SAMPLED
INPUT
DATA

l------I----f.
\

ll'~

..

I

HSP43220

DDF

Ii\
o

10MHz

o

20MHz

FIGURE 14. DIGITAL CHANNELIZER

.3-16

o

HSP43220
Design Trade-Off Considerations
Equation 2.0 in the Functional Description section
expresses the relationship between the number of TAPS
which can be implemented· in the FIR as a function of
CK-IN, FIR_CK, Hdec, Fdec. Figure 15 provides a

SPEED
GRADE (MHz)

*

FIR_CK
CLIN

MIN
Hdec

tradeoff of these parameters. For a given speed grade and
the ratio of the clocks, and assuming minimum decimation
in the HDF, the number of FIR taps that can be implemented
is given in equation 2.0.

TAPS
Fdec=·1
8
4

Fdec=2

Fdec=4

Fdec=8

Fdec = 16

24
16
4

56
40
16

120
88
40

248
184
88

28
20
4

64
48
16

136
104
40

280
216
88

80
48
16

168
104
40

344
216
88

112
48
48

232
104
104

472
216
216

33
25.6
15

1
1
1

9
7
4

33
25.6
15

2
2
2

5
4
2

10
6

33
25.6
15

4
4
4

3
2
1

14
6

*

36
20
4

33
25.6
15

8
8
8

2
1
1

22
6
6

52
20
20

*

*

Filter Not Realizable

en

FIGURE 15. DESIGN TRADE· OFF FOR MINIMUM Hdec

....a::
~

u:
DECI-MATE

CI
I

Harris provides a development system which assists the
design engineer to utilizing this filter. The DECI- MATE
. software package provides the user with both filter design
and simulation environments for fllter evaluation and
design. These tools are integrated within one standard
DSP CAD environment, The Athena Group's Monarch
Professional DSP Software package.

This software package runs on an IBM- PC-, XT-, AT-,
PS/2- computer or 100% compatible with the following
configuration:

The software package 15 designed specifically for the DDF.
It provides all the filter design software for this proprietary
architecture. It provides a user-friendly menu driven
interface to allow the user to input system level filter
requirements. It provides the frequency response curves
and a data flow simulation of the specified filter design
(Figure 16). It also creates all the Information necessary to
program the DDF, including a PROM file for programming
the control registers.

IBM PC-. XT-. AT-. PS/2- are registered tredemarks of Internallonal BUSiness Machines, Inc.

3-17

640K RAM
5.25" or 3.5" Floppy drive
hard disk
math co-processor
MS/PC-DOS 2.0 or higher
CGA, MCGA, EGA, VGA and
Hercules graphics adapters

HSP43220

HSP43220 DDF FILTER SPECIFICATION
Filter F i l e · : vectors\example. DDF
.'
Input Sample Rate:
33;MHz
Design Mode
output Rate
100 kHz
Generate Report
Passband
20 kHz
Display Response
Transition. Band
7.5 kHz
Save Freq Responses:
Passband Atten
0.5 dB
Save FIR Response
Stopbc;\nd Atten.
80 dB
FIR Type

AUTO
YES
LOG

YES
YES

PRECOMP

HDF Ord'er
HDF Decimation
HDF Scale Factor

FIR
FIR
FIR
FIR

4
110
0.54542

Input Rate
Clock (min)
Order
Decimation

.

300 kHz
33 MHz
135
3

'

.

(C) Harris Semiconductor 1990

-5, 2653~-""""---'--"---"'"
,

.",
,
................................
,
,

: <,

~

,
........."",, ................................
.
,,
,,
,,,
,
,
,

,
o

o
o
o

0

···············~·························l··

,

0

..········,····\..··..····~··························.I··· .. ········........

o

••••••••••••••••••••••••••~ ••••••••••••••••••••••••• ~ •••••,•••••••••,•••••\ ...,•••j. .....,••~ •• "'•••• " •••J.... ; ...... ,....... ".••••''"•••• ,.~
o
,

0

>0

U~''I+···············,············~·························t··························~·····················
o
o

....

o
o

····· . _···· . __ ·· . ·· . ·· . . . f· . ··· . . ·. . . . . ····· . . ··· . ·:·· . . . . ····· . ······ . ··· . . . ·r . ·. ·. . . . ····· . ·········. ·:. ······. ·. ··--------------i
o
o
o

0
0

0

-21617~~,~--------~*o~------~~'~-------r.~~------~~~------~~~'A

FIGURE 16. DECI-MATE DESIGN MODULE SCREENS

Specifications HSP43220
Absolute Maximum Ratings
Supply Voltage •.....••••...............•..••...•••........•...•......••..•.••.•....•.....•................•..•• +8.0V
Input, Output or I/O Voltage Applied •••..•..••..•••....••...•••••......••••••...••...•••••••...•. GND -0.5V to VCC +0.5V
Storage Temperature Range ••••.........•••••...............................•..•...•........••.••.•.. -650C to +1500 C
Maximum Package Power Dissipation .....•.•....................••..•........••.•.•••.....••••• 2.4W (PLCC), 3.2W (PGA)
0jc ..••••...•••.••....•.......•.••.••••..•..•.•.••••.••••......••....••.•••......•... 10.90 C/W (PLCC) , 7.2 0 C/W (PGA)
0ja .............................•..•.••........•.•••.•..•...•..•...•..•..••..•.••... 33.80 C/W (PLCC) , 32.9 0 C/W (PGA)
Device Count ••••••••.•••••••••.......••••••............•.•.•.............•.•..................•.. 193,000 Transistors
Junction Temperature ••••••.••••....••••..•••.....•.•....•.•.•.•••.........••............. 150oC (PLCC), +175 0 C (PGA)
Lead Temperature (Soldering,Ten Seconds) ............•..........•••.•.......••.....••.....•••.•.••......•••.••• +3000 C
ESD Classification •....•..••..•........••••...........••••.............•..•.•.....................•.•.•......•. Class 1
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may CBuse permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range •.......•..........•.........................•.............•.......•...•••... +4.75V to +5.25V
Operating Temperature Range ••.•......••.•••..............•••.•........•..•••......•••..•••.•.•...•..... OoC to + 700C

D.C. Electrical Specifications VCC = +4.75V to +5.25V (VCC = 5.0V ± 5%), TA = ooc to +70 oC
PARAMETER

SYMBOL

MIN

MAX

UNITS

TEST CONDITIONS

Logical One Input Voltage

VIH

2.0

-

V

VCC=5.25V

Logical Zero Input Voltage

VIL

-

0.8

V

VCC=4.75V

3.0

-

V

VCC= 5.25V

High Level Clock Input

VIHC

Low Level Clock Input

VILC

-

0.8

V

VCC=4.75V

Output HIGH Voltage

VOH

2.6

-

V

IOH=-400flA
VCC=4.75V

Output LOW Voltage

VOL

-

0.4

V

IOL=+2.0mA
VCC = 4.75V

Input Leakage Current

II

-10

10

flA

VIN=VccorGND
VCC=5.25V

1/0 Leakage Current

10

-10

10

flA

VOUT = VCC or GND
VCC= 5.25V

Standby Power Supply Current

ICCSB

-

500

flA

VIN = VCC or GND,
VCC = 5.25V, Note 3

Operating Power Supply Current

ICCOp

-

120

mA

f= 15 MHz, VIN = VCC orGND
VCC = 5.25V, Note 1, Note 3

SYMBOL

MIN

Capacitance (TA = +250 C, Note 2)
PARAMETER

MAX

UNITS

Input Capacitance

CIN

12

pF

Output Capacitance

Co

10

pF

NOTES:
1. Power supply current is proportional to operating frequency. Typical rat·
ing for leeop is SmA/MHz.

2. Not tested, but characterized
process/design changes.

at

initial

design

and

at

TEST CONDITIONS
FREQ = 1 MHz, VCC = Open,
all measurements are referenced
to device ground.

3. Output load per test toad circuit and CL = 40pF.

major

3-19

II>

....a:

~

u:

C

I

Specifications HSP43220
A.C. Electrical Specifications vcc = +4.75V to +5.25V, TA = OOC to HOoC
-15
PARAMETER

-25

-33

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

Input Clock Frequency,

FCK

0

15

0

25.6

0

33

MHz
MHz

FIR ClOck Frequency

FFIR

0

15

0

25.6

0

33

Input Clock Period

TCK

66

39

-

ns

TFiR

66

30

-

,ns

Clock Pulse Width Low

TSPWL

26

16

-

30

FIR Clock Period

13

-

ns

Clock Pulse Width High

TSPWH

26

-

16

-

13

-

ns

TSK

0

TFIR-25

0

TFIR-15

0

TFIR-15

ns

4TCK

-

ns

8TCK

ns

TCK+10

-

Clock Skew Between FIR_CK and
CK-IN
RESET# Pulse Width Low

TRSPW

4TCK

RecoveryTime on RESET#

TRTRS

8TCK

TAST

TCK+10

-

ASTARTIN# Pulse Width Low

39

4TCK

-

TCK+10

-

8TCK

TSTOD

-

35

-

20

-

18

ns

STARTIN# Setup to CK-IN

TSTIC

25

-

15

10

ns

Setup Time on DATA-IN

TSET

20

-

15

-

THOLD

0

.-

0

TWL

26

15

TWH

26

-

Setup Time on Address Bus Before
the Rising Edge of Write

TSTADD

26

Setup Time on Chip Select Before
the RiSing Edge of Write

TSTCS

Setup Time on Control Bus Before
the Rising Edge of Write

Hold Time on All inputs
Write Pulse Width Low
Write Pulse Width High

..

20

-

18

-

20

-

20

-

26

-

20

-

20

-

ns

TSTCB

26

-

20

-

20

-

ns

0
12

.

ns

STARTOUT# Delay from CK-IN

14

TEST
CONDITIONS

ns
ns
ns
ns
. ns

TDRPWL

2TFIR-20

-

2TFIR-10

-

2TFIR-10

-

ns

DATA-OUT Delay Relative
toFIR_CK

TFIRDV

-

50

-

35

-

28

ns

DATA ROY Valid Delay Relative
tOFIR_CK

TFIRDR

-

35

-

25

-

20

ns

DATA-OUT Delay Relative
toOUT_SELH

TOUT

-

25

-

20

-

20

ns

Output Enable to Data Out Valid

TOEV

ns

Note 2

15

-

15

15

-

15

TOEZ

-

15

Output Disable to Data Out
Three State

15

ns

Note 1

Output Rise, Output Fall Times

TR,TF

-

8

-

8

-

6

ns

from .8V to 2V,
Note 1

DATA-ROY Pulse Width Low

NOTES:
1. Controlled by design or process parameters and not directly tested. Characterized upon in~.ial design and after major process and/or design changes.
2. Transition is measured at ±200mV from steady state voltage with loading as
specified in test load circuit with and Cl = 40pF.

3. A.C. Testing is performed as follows: Input levels (ClK Input) 4.0V and OV,
. Input levels (all. other Inputs) OV and 3.0V, Timing reference
levels (ClK) = 2.0V, (Others) = 1.5V, Input rise and fall times driven at 1 nsN,
Output load per test load CircuH and Cl = 40pF.

3-20

HSP43220
Test Load Circuit

1- - - - - - - - - - - - --1
1

1

1

1

1

1
1
1
1
1
1
1

·INCLUDES STRAY AND

JIG CAPACITANCE

I

1 _ _ _ _EaUIVALEN~CIRCUrr_ _ _ _

Sw~ch

Timing Waveforms

1

I

S1 Open for ICCSB and ICCOp Tests

INPUT TIMING
~TFIR~
U)

a:
w
~

u:
Q
I

foo--~-t""- T SPWH

CILIN

- - T SPWL ~
TSK I . r - - - -...... I
1;----

1 - - - - - T CK

--~-I

START TIMING

ASTARTIN# tTAST1~----------

RES ET#
TRSPW

X
TRTRS
WR#

CICIN

-TWL-

""-TWH~

I'

I::::::l

AD -1

STARTOUT#

T HOLD

)I(
C_BUS
CICIN

TSTADD

THOLD

TSTCB

THOLD

~

;1fTS~
STARTIN~

_ _ _ __

CS#

i:=TSTCS-

1:

3-21

HSP43220
Timing Waveforms

(Continued)
OUTPUT TIMING
DATA_OUT 16 -23
UPPER 8 BITS

LOWER 8 BITS

I

OUT SELJ-I
TOUT
=';";;=~-'{
1'-______________________

CURRENT OUTPUT

OUT_ENP#
OUT_ENX#
TOEZ
DATA-OUT

3-22

EliHARRIS

HSP43220/883
Decimating Digital Fi.lter

May 1991

Features

Description

• This Circuit is Processed in Accordance to Mil-Std883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

The HSP43220/883 Decimatin Di ital Filter is a linear
phase low pass decimation filter which is optimized for fil·
terin narrow band si nals in a broad spectrum of a si nal
processin applications. The HSP43220/883 offers a
sin Ie chip solution to si nal processin application which
have historically required several boards of IC's. This
reduction in component count results in faster development
times as well,as reduction of hardware costs.

• Single Chip Narrow Band Filter with up to 96dB
Attenuation
• DC to 33MHz Clock Rate
• 16 Bit 2's Complement Input
• 20 Bit Coefficients in FIR
• 24 Bit Extended ,Precision Output
• Programmable Decimation up to a Maximum of
16,384
• Standard 16 Bit Microprocessor Interface
• Filter Design Software Available DECI.MATE lM
• Available in 84 Pin PGA

Applications

The HSP43220/883 Is implemented as a two sta e filter
structure. As seen in the block dia ram, the first sta e is a
hi h order decimation filter (HDF) which utilizes an efficient
decimation (sample rate redu'ctioo) technique to obtain
decimation up to 1024 ihrou h a coarse low-pass filterin
process. The HDF provides up to 96 dB aliasin rejectlonin
the si nal pass band. The second sta e consists of a finite
impulse response (FIR) decimation filter structured as a
transversal FIR filter with up to 512 symmetric taps which
can implement filters with sharp transition re lons.The FIR
can perform further decimation by up to 16 if required while
preservin the 96 dB aliasin attenuation obtained by the
HOF. The combined total decimation capability is 16,384.
The HSP43220/883 accepts 16 bit parallel data in 2's
complement format at samplin rates up to 30MSPS. It
provideS a 16 bit microprocessor compatible interface to
simplify the task of pro ram min and three-State oUtputs to
allow the connection of several IC'. to a common bus. The
HSP43220/883 also provides the capability to bypass
either the HDF or the FIR for additional flexibility." ' .

• Very Narrow Band Filters
• Zoom: Spectral Analysis
• Channelized Receivers
• Sample Rate Converter'
• Instrumentation
.512 Tap Symmetric FIR Filtering

Block Diagram
DECIMATION UP TO 1024

INPUT CL.OCK
DATA INPUT
CONTROL
AND
COEFFICIENTS

.. 18

.

..16

DECIMATION UP TO 18

~

~

HIGH ORDER
DECIMATION
FILTER

FIR
DECIMATION
FILTER

r

I

..

.. 24

DATA OUT
DATA
READY

T
FIR CLOCK

DECI • MATE- is a re istered trademark of Harris Corporation.
IBM PC-, Xl-, AT-, PS/2- are re latered trademarks of International Business Machines, Inc.
CAUTION: Theae devices' are sensHive to electrostatic diachar e. 'Proper I.C. h8ndlin procedures should be followed.
Copyright C) Harris Corporation 1991

3-23

Flle Number

2802

Specifications HS1!!;4322 0/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage , ....................................... +8.0V
Input, Output Voltage Applied ........... GND-0.5V toVCC+0.5V
Storage Temperature Range •.••....•.•...... -650C to +150oC
Junction Temperature .... ~ ........................... +1750 C
Lead Temperature (Soldering, Ten Seconds) ••.•........ +300o C
ESD Classification .................................... Class 1

Thermal Resistance '
Sja
Sjc
7.2oC/W
Ceramic PGA Package. . •• •. . .• . • .. 32.90 C/W
Maximum Package Power... Dissipation at +1250 C
Ceramic PGA Package ...,......................... 1.52 Watt
Gate Count • .. . . . .. • .. .. • .. .. .. . . .. . . . .. .. • .. •. 48,250 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation.
of the device at Ihese or any olher conditions above those indicated in the operational sections of this' specification is' not Implied. .
.

Operating Conditions
Operating Voltage Range ..•..••.•.••....••...•• +4.5V to +5.5V
Operating Temperature Range .••....•.....•. '-SsoC to +12So C
TABLE 1. D,C.ELECTRicAL PERFORMANCE CHARACTERISTICS
Devices Guaranteed and.100% Tested

•.
PARAMETER

SYMBOL

Logical One Input
Voltage

VIH

Logical Zero Input
Voltage

VIL.

,"

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

VCC=S.SV

1,2,.3

-SSoc ~TA~ +12SoC

2.2

-

V

YCC=4.SV

1,2,3

-SSOC ~TA ~ +12SoC

-

0.8

V

CONDITIONS

Output HIGH Voltage

VOH

IOH = -400pA'
VCC = 4.SV (Note 1)

1,2,3

-sSOC ~TA~ +12SOC

2.6

-

V

OUljlut LOW Voltage

VOL.

IOL = +2.0mA·
VCC ~4.SV(Note 1)

1,2,3

-sSOC ~ TA ~+12.SoC

-

0.4

V

II

VIN:" VCC or GND
VCC=5.SV

1,2,3

-SSOC,$TA ~ +12SQC

'-10

+10

pA

VOUT =VCC ()/"dNQ
Vcc'=S.SV
.

1,2,3

-SSOC !iTA~ +12SOC

-10

+1q

pA

Vcc"=fi.SV

1,2,3

-SSOC ~TA <+12SOC

3.0

-

V

I

Input Leakage Current
QutpuU.eakage
Current

..

Clock Input High .

10
VIHC

,.

VCC=4.SV

1,2,3

-SSOC~TA~+12SOC

-

0.8

V

Standby Power Supply
Current

ICCSB

VIN = VCC or GND
VCC = S.5V,
Outputs Open .

1,2,3

-sSOC ~TA So +12SoC

-

SOO

pA

Operating PoWer
Supply Current

ICCOp"

f=1S.0MHz
VCC = S.SV (Note 2)

1,2,3

-SSOC~TA~.j.12S0C

-

120.0

mA

7,8

-SSOC SoTA So +12SoC

-

-

Clock InPill Low

Functional Test

VILC

FT

(Note 3)

NOTES:
1. interchanging 01 force and sensa cond_ 18 parmlHad.
2. Operaling Supply CUrrent 18 proportion.rIo frfIquancy, tYPical rating is
.
IlmAIMHz.

3. Tasted as IoRowa: f - 1MHz, VIH - 2.8, Vil
VOL So 1~5V, VIHC'!!' 3.4V, and VllC - 0.4V.

.c·,·

3-24

=

0.4, VOH ~ 1.5V,

Specifications HSP43220/883
TABLE 2. A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
LIMITS

PARAMETER

(NOTE1)
CONDITIONS
SYMBOL

-15 (15MHz)

GROUPA
SUBGROUPS

TEMPERATURE

-25 (25.6MHz)

MIN

MAX

MIN

MAX

UNITS

-

39

-

ns

TCK

9,10,11

-550C

s: TA s: +1250C

66

TFIR

9,10,11

-55°C s:TA s: +1250 C

66

TSPWL

9,10,11

-55°C

+1250 C

26

TSPWH

9,10,11

-550C S:TA s: +1250 C

26

16

-

ns

TSK

9,10,11

-55°C s: TAS: + 125°C

0

TFIR
- 25

a

TFIR
-19

ns

RESET# Pulse
Width Low

TRSPW

9,10,11

-55°C s:TA s: +1250 C

4TCK

-

4TCK

-

ns

Recovery Time
OnRESET#

TRTRS

9,10,11

-55°C s:TA s: + 125°C

8TCK

-

8TCK

-

ns

ASTARllN# Pulse
Width Low

TAST

9,10,11

-55°C s:TAS: +1250C

TCK
+10

-

TCK
+10

-

ns

STARTOUT# Delay
FromCK-IN

TSTOD

9,10,11

-55°C s:TAS: +125OC

-

35

-

20

ns

STARTIN# Setup
ToCK-IN

TSTIC

9,10,11

-55°C s:TAS: +1250 C

25

-

15

-

ns

Setup Time on DATA....JN

TSET

9,10,11

-55°C s:TAS: +1250C

20

16

-

ns

THOLD

9,10,11

-55°C s: TAS:+1250C

0

-

0

-

ns

Write Pulse Width Low

TWL

9,10,11

-55°C

s: TAS: +1250C

26

Write Pulse Width High

TWH

9,10,11

-550C s:TAS: +1250C

26

Setup Time on Address
Bus Before the Rising
Edge of Write

TSTADD

9,10,11

-55°C s:TAS: +1250C

Setup Time on Chip
Select Before the
Rising Edge of Write

TSTCS

9,10,11

Setup Time on Control
Bus Before the Rising
Edge of Write

TSTCB

Input Clock Period
FIR Clock Period
Clock Pulse Width Low
Clock Pulse Width High
Clock Skew Between
FIR_CK and CK-IN

Hold Time on All Inputs

s: TA s:

39
16

ns
ns

U)

;:;:

20

28

-

24

-

-55°C s: TAS: +1250C

28

-

24

-

ns

9,10,11

-55°C s: TAS: +1250C

~8

-

24

-

ns

TDRPWL

9,10,11

-55°C s:TAS: +1250 C

2TFIR
-20

-

2TFIR
-10

-

ns

DATA.....OUT Delay
Relative to FIR_CK

TFIRDV

9,10,11

-55°C s:TAS: +1250 C

-

50

-

35

ns

DATA.....RDYValid Delay
Relative to FIR_CK

TFIRDR

9,10,11

-55°C s: TA s: +1250 C

-

35

-

25

ns

DATA.....OUT Delay
Relative to OUT_SELH

TOUT

9,10,11

-55°C s: TA s: +1250 C

-

30

-

25

ns

Output Enable to
Data Out Valid

TOEV

9,10,11

-55°C s:TA s: +1250 C

-

20

-

20

ns

DATA.....RDY Pulse
Width Low

2

NOTES:
1. A.C. Testing: Inputs are driven at 3.0Vfor a Logic "1" and O.OV for a logic
"0". Input and output liming measurements are made at 1.5V for both a
LogiC "1" and "0". Inputs driven at lV/ns. elK is driven at 4.0V and OV
and measured at 2.0V.

15

ns
ns
ns

2. Transition is measured at ±200mV from steady state voltage with loading
as specWied by test load circuit and CL = 40pF.

3-25

a:
w

!:i
C

I

HSP43220/883 ,
TABLE 3. ELECT>RICAL PEfU'ORMANCE'CHARACTERISTICS

..

.~
,,~

..

'.'

LIMITS
-15 (15MHz)

"
TEMpERATURE

MIN

':.... 1,

TA=+;!5 0C

-

.. 12

1

TI\.=+250 C

-

TOEZ

1,2

-550C~TA~+1250C

-

Output Rise Time

TOR

1,2

-550C~TA <+1250 C

Output Fall Time

'TOF

1,2

-550C~TA~+1250C

NOTES

PARAMETERS

SYMBOL

CONDITIONS

Input Capacfiande ,

CIN

"cc'=open,
f= 1 !VI Hz, All
mea~urements are
referenced to
deviceGND.

Output Capacitance

COUT

·V.CC = Open,

f';'

l~Hz,AlI

MAX

-25 (25.6MHz)
MIN

MAX

UNITS

-

12

pF

10

-

10

pF

20

-

20

ns

8

-

8

ns

8

-

..8

ns

.. ,..,

measurements are
referenced to
deviceGND.
, Output Disable
Delay

NOTES:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon
initial design and after major process 'and/or d~sign changes.

-

2. Loading is as spacWied in the test load circuH with CL = 40pF.

,

,

TABLE 4. APi>LlCABLE SUBGROUPS
"'

CONFORMANCEGROUPS;

.

Initial Iest
InterjmTest

.METHOD

SUBGROUPS

100%/5004

-

100%/5004

-

PDA

100%

1

Final Test

100%

2,3,8A,8B,10,11

-

1,2,3,7, 8A,8B, 9,10, 11

Sampll'lsJ5005

1,7,9

Group A
GroupsC&D

...

"

..

,

.-

..

...
"

3-26

HSP43220/883
Burn-In Circuit
DATA.....

A

IN.

DATA.....
IN.

C

G

A1

RESET

CS'"

w_

AG

c~us

CJUS

CJlUS

10

16

,.

"

C.....BUS
11

CJlUS

,,-"us

CJUS

OND

K

DATAIN 7

DATAIN.

DATAIN 11

IN 14

DATAIN8

DATA.....
IN 13

DATAIN 12

DATAIN 15

DATA.....
IN6

DATAIN 9

DATA.....
IN 10

DATA.....

10

11

Vee

GND

GND

CK-IN

Vec

DATA...
OUT 1

DAT"-.

DATA.....

OUT 0

OUT 2

13

Vec
C_BUB

7

eJlUs

CJUS
8

rn
a:
PIN
NAME

PIN
LEAD

BURN-IN
SIGNAL

PIN
LEAD

BURN-IN
SIGNAL

PIN
NAME

PIN
LEAD

PIN
NAME

BURN-IN
SIGNAL

GND

GND

el

ASTARTIN#'

F1S

Fll

DATA-OUT 3

VCC/2

A2

DATA-IN 1

F2

e2

Vee

Vee

Gl

C_BUS12

FS

A3

DATA-IN 2

F3

es

DATA_INS

F6

G2

C_BUSll

F4

A4

DATA-IN 4

FS

e6

DATA-IN 9

F2

G3

C_BUS13

F6

AS

DATA-IN 7

F8

e7

DATA-IN 10

F3

G9

DATA-OUT 10

Vce/2

A6

DATA-IN 8

Fl

el0

DATA-OUT 0

Vee/2

Gl0

GND

GND

A7

DATA-IN 11

F4

ell

DATA_OUT 2

Vee/2

Gll

DATA-OUT 11

Vce/2

A8

DATA-IN 14

F7

01

Al

F14

Hl

C_BUS9

F2

A9

Vee

Vee

D2

RESET#'

F16

H2

Vec

VCC

Al0

GND

GND

Dl0

DATA-OUT 3

Vee/2

Hl0

DATA-OUT 13

Vec/2

All

GND

GND

011

DATA_OUT 4

Vec/2

Hl1

DATA-OUT 12

VCC/2
GND

91

STARTIN#'

F1S

El

es#'

Fll

Jl

GND

B2

STARTOUT#'

Vee/2

E2

WR#'

Fll

J2

C_BUS7

FS

B3

DATA-IN 0

Fl

E3

AO

F13

JS

OUT_SELH

FlO

B4

DATA-IN 3

F4

E9

DATA-OUTS

VCC/2

J6

GND

GND

BS

DATA-IN 6

F7

El0

DATA-OUT 6

VCC/2

J8

FIR_CK

FO

B6

DATA--'N 13

F6

Ell

DATA-OUT 7

VCC/2

Jl0

DATA-OUT 16

Vce/2

B7

DATA--'N 12

FS

Fl

C_BUS10

F3

Jll

DATA-OUT 14

Vce/2

B8

DATA--'N 16

F8

F2

C_BUS1S

F8

Kl

C_BUS8

Fl

B9

elCJN

FO

F3

C_BUS14

F7

K2

C_BUSS

F6

Bl0

Vee

Vee

F9

DATA-OUT 9

VCC/2

K3

C_BUS4

FS

Bll

DATA-OUT 1

Vee/2

FlO

Vcc

K4

C_BUSl

F2

NOTES:
1. Vee/2 (2.7V ±1 0%) used for outputs only.
2. 47KO (±20%) resistor connected to all pins except Vee and GND.
3. Vee = 5.5 ±0.5V.

5. FO = 100kHz ±1 0%, F1
Duty Cycle.

=FO/2, F2 =F1 12 ..... F1 6 =F1 512, 40% - 60%

6. Input voHage limits: VIL

= 0,8 max, VIH = 4.5V ±10%.

4. 0.1pF (min) capacitor between Vee and GND per position.

3-27

i:i:
CI

Al

Vec

LU

!:i
I

HSP43220/883
Burn-In Circuit

PIN
LEAD

PIN
NAME

(Con,t1nued)

BURN,..IN
SIGNAL

PIN
LEAD

PIN
'NAME

BURN-IN
SIGNAL

PIN
LEAD

PIN
NAME

BURN-IN
SIGNAL

K5

OUT_ENP#

F9

K11

DAT~OUT15

Vcc/2

L6

DAT~RDY#

VCC/2

K6

Vcc

Vcc

L1

C_BUS6

1"7

L7

VCC

VCC

K7

GND

GND

L2

'C_BUS3.

F4

L8

DAT~OUT23

VCC/2

K8

DAT~OUT22

Vcc/2

L3

C_BUS2

F3

L9

DAT~OUT21

VCC/2

K9

DAT~OUT19

Vcc/2

L4

C_BUSO

Fl

L10

DAT~OUT20

VCC/2

K10

DAT~OUT17

Vcc/2

L5

OI:lT_ENP#

F9

L11

DAT~OUT18

VCC/2

I

NOTES:

1. Vee/2 (2.7V ±10%) used for outputs only,
2. 47KO (±20%) resistor connected to all pins except Vee a!,d GND.
3. Vee
4.

= 5,5 ±0.5V.

0.1~F

5. FO = 100kHz ±10%, F1
Duty Cycle.
6. Input

(min) capacitor between Vee and GND per position.

3-28

vo~age

= FO/2,F2 =F1/2 ..... F16 = F15/2, 40%- 60%
'

limits: VIL = O.B max, VIH = 4.5V ± 10%.

HSP43220/883
Metal Topology
DIE DIMENSIONS:
348 x 349.2 x 19±1 mils

WORST CASE CURRENT DENSITY:
1.18 x 105 A/cm 2

METALLIZATION:
Type: Si - AI or Si - AI - Cu
Thickness: 8k.B.

GLASSIVATION:
Type: Nitrox
Thickness: 10k.B.

DIE ATTACH:
Material: Silver Glass

Metallization Mask Layout
HSP43220/883

0
Z

Z

.. '"

Z

Z

... "'
Z

~ J~~ ~

0
Z

l-

I- I- lI«
«
«
« «
0
0
0 0
0

Cl

;=

Z

.

Z

-I

S«~
0

S
0

0

...

N

0

en

Z

Z

~

l-

'" Z "'Z
Z Z
I
~ « ~ l-~ I-~
I- l- IZ

«
0

e(

0

e(

e(

0

0

«
0

e(

0

Z
00
OZ l<:
>Cl 0

I

0
0

>

STARTOUT# (12)
Vcc (13)
STARTIN# (14)

en

a:
w

ASTARTIN# (15)

~

u:::

RESET# (16)

CI
I

A1 (17)
AO (18)
WR# (19)
CS# (20)
C_BUS15 (21)
C_BUS14 (22)
C_BUS13 (23)
C_BUS12 (24)
C_BUS11 (25)
C_BUS10 (26)
C_BUS9 (27)
VCC (28)
GND (29)
C_BUS8 (30)
C_BUS7 (31)
C_BUS6 (32)

M

.,

;;; iO ;:: iO c;;-

e e e e e e e

"'::> ...::> ::>'" '"::>
fIl

fIl

fIl

fIl

ID

ID

ID

ID

0

1

0

1

0

1

0

1

(ij
::>

ID

0

1

0

fIl

::>
ID

0

1

J:

oJ

UJ

j

::>
0

.,

o

N M
:!. ~ :!. :!. :!.

,.. ,..

...

)(

UJ

UJ

Z

1

l-

::>
0

Z

1
I-

0
0

>

0
Z

Cl

l<:

0
1

II:

ii:

::>

0

;;; iO ;:: ;0 me ~
M
:!. :!. :!. :!. :!..!e !e!e. e
o
en
0
0
;;j N ~ co
Z )0- N N
0
Cl 0 l- I- l- I- I- ~
>

,..

II:

~
«
0

3-29

'"

'" '"

::> ::> ::> ::> ::> ::>

0

00 00 0

JJ ~ ~ I-«
~ ~ « e( «
«
0 00 00 0
1

e(

I-

1

1

1

HSP43220/883
Packaging t
84 PIN CERAMIC PIN GRID ARRAY
SEA TING PLANE }

E_~;+:~_I_o_·_·

.g,'g

---hL------,

K
J

H

G

®®®® ®®®®@l-t---.
®®®®®$®®®®®
®®
®®®
®®
®®
I
®® .000
®®®
I
® ® ® s~e

e-e --

+ - - -e-e-e- - --.l

I

®®®

h-c::I~:;g

1.140
1.180

1.000

.100

sse

sse

=

~

.ooi

1. INCREASE MAXIMUM LIMIT BY
WHEN SOLDER
DIP OR TIN pl..,An:;' LEAD FINISH APPLIES.

LEAD MATERIAL: Type B
LEAD FINISH: :Type C
PACKAGE MATERIAL: Ceramic, AI203 90%
PACKAGE SEAL:
Material: Gold/Tin
Temperature: 3200C ± 100C
Method: Furnace Braze '

NOTE: All Dimensions are

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method:·. Ultrasonlp Wedge
COMPLIAfilT OUTLINE: 38510 P-AC

MMin ,Dimensions are in inches.
ax

tMA-M-38S10 Compllant Materials, Finishes, and Dimensions.

3-30

mHARRIS

DECleMATE™
Harris HSP43220 Decimating Digital
Filter Development Software

May 1991
Harris DECI- MATE Development Software assists the
design engineer to prototype designs for the Harris
HSP43220 Decimating Digital filter (DDF). Developed
specifically for the DDF, this software consists of three
integrated modules: DDF Design, DDF Simulator and DDF
PROM. The Design module designs a filter from a set of
user specifications for the DDF. The Simulator module
models the DDPs internal operation. The PROM module
uses the device configuration created by the Design module
to build a PROM data file that can be used to store and
download the DDF configuration.
DDF System Design
The DDF consists of two stages: a High Decimation Filter
(HDF) and a Finite Impulse Response (FIR) filter. Together
these provide a unique narrow band, low pass filter.
Because of this unique architecture, special software is
required to configure the device for a given set of filter
parameters. This software uses system level filter
parameters (listed below) to perform the trade off analysis
and calculate the values for the DDPs configuration
registers,and FIR coefficients.
Design specifications are supplied by the user in terms of:

Frequency response curves are then displayed showing the
resulting responses in the HDF, FIR and for the entire chip
using the given filter design. Figure 2 is a typical display.
ThE! user may save this frequency response data for further
analysis. The design module, also creates a report file
documenting tile filter design and providing the coefficients
and setup register values for programming the device.
DDF Simulator
The simulator provides an accurate simulation of the device
before any hardware is built. It can be used to simulate any
filter designed with DECI- MATE. The simulator takes into
account the fixed point bus widths and pipeline delays for
every element in the DDF.
The simulator provides the user with an input signal which
can be used to stimulate the filter. This signal is created
from the options shown in Table 1. The user can select a
pure step, impulse, cosine, chirp, uniform or Gaussian noise
as the input signal, or a more complex signal can be
generated by combining that data with an option selectE!d
from thE! Signal #2 column, with the combining operator
chosen from the middle column. The user can also import a
signal from an outside source.

1. Input sample frequency
SIGNAL #1
Step
Impulse

2. Required output sample frequency
3. Passband signal bandwidth
4. Transition bandwidth

COSINE
Chirp
Uniform Noise
Gaussian Noise

5. Amount of attenuation allowed in the passband
6. Amount of stopband attenuation required for signals
outside of the band of interest.
This information is entered into a menu screen (See Figure
1), providing immediate feedback on the design validity. The
design module calculates the order of the HDF, HDF
decimation required, the FIR input data rate, minimum clock
frequency for the FIR, FIR order and decimation required in
the FIR.
The design module will then generate the FIR filter. Four
different methods are provided for the FIR design:
1. A Standard FIR automatically designed by the module
using the Parks-McClellan method to compute the
coefficients of an equiripple (Chebyshev) filter.
2. Any FIR imported into the Design module from another
FIR design program.
3. A precompensated FIR which is automatically designed
by the module to compensate for the roll-off in the
passband of the HDF frequency response.
4. The FIR may also be bypassed in which case the optimal
HDF is designed from the user specifications.

OPERATION
No Operation
Add
Concatenate
Multiply

SIGNAL #2
Step
Impulse

COSINE
Chirp
Uniform Noise
Gaussian Noise
Imported From Outside

Probes are provided to select specific areas to graphically
display data values as well as save into data files for further
processing. The DDF Simulator has two levels; the DDF
Simulator Specification screen and the DDF Simulator Main
Screen.
The specification screen (see Figure 3) is used to input the
simulation parameters. The users selects display modes in
either continuous or decimated format and data formats in
either decimal or hexadecimal. The specification screen
also provides for selection of the input signal.
The simulator main screen (see Figure 4) defines the
simulator test probes and displays the data values per clock
cycle. The interactive simulator screen consists of the
HSP43220 block diagram, test probes and register
contents. The user selects the step size of the input sample
clock and also selects the probes to be monitored. The
simulator will then clock through the specified number of
clock cycles and display the resulting time domain
response. Figure 5 shows a typical probe display.

Copyright © Harris Corporation 1991
DECI- MATETM is a Trademark of Harris Corporation

3-31

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DEC/-MATE
Monarch 2.0'DSP Design 'Software

System Requirements

DECI- MATE is fully, integrated with Monarch 2.0
professional ·DSP design· software. Monarch is a fiJlIfeatured DSP. package. with FIR, IIR . filter design and
analysis, Two dimensional and Three dimensional viewing,
a programmable'sigFlal/systems laboratory with 100+ DSP/
, Math ..,unctions, extensive fixed-point support and FFTs/
IFFTs. Monarch ·.is available separately from The Athena
. Group, Inc.

IBM PC"', XT"', AT"', PS/2'" computer or 100% compatible
with 640k RAM running MS/PC.,.DOS 2.0 or higher. One
MegaByte of fixed-disk space with 5.25" or 3.5" floppy
drive. CGA, MCGA, EGA, VGA,8514, or Hercules graphics
adapter, A Math co-processor is strongly recommended.

When used with Monarch 2.0, DECI- MATE becomes a full
feature design environment for a DSP system." Data can
easily be transferred from DECI- MATE modules to the
Monarch modules for further analysis.
.

I

"DESIGN MODULE

SIMULATOR MODULE

PROM MODULE

HSP43220 DDF FILTER SPECIFICATION
D
E
C
I

-

Filter File
: PRES.DDF
Input .Sample Rate:
33 MHz
Output Rate
100 kHz
Passband
5 kHz
Transition Band
700 Hz
Passband Atten
1 dB
Stopband Atten
96 dB
FIR Type

Design Mode
Generate 'Report
Display Response
Save Freq Responses
Save FIR Response

AUTO
YES
LOG
YES
YES

STANDARD

M
A
T

HDF Order
HDF'Decimation
HDF Scale Factor

4
330
0.6903

E

FIR
FIR
FIR
FIR

Input Rate
Clock (min)
Order
Decimation

FIGURE 1. FILTER SPECIFICATION MENU

IBM PC-. XT". AT-. PS/2- are Registered Trademarks of IBM

3-32

100 kHz
33 MHz
509
1

II

DEC/-MATE

3.220~~=---~-----r----~-----,

1.3'1i4.t ... ,.. t .....

r.--l---·+. ,·. ·. ·. ,.

1

-O.0065r=====~-----:-----------:-----------:------------:-----------,

-47.6682 +...... ".....

.,.
II:

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Q

I

-238.31.4~r-------~ndbrrr-------~~~------~~~------~~v.------~~~~

FIGURE 2. FREQUENCY DISPLAY

I

SIMULATOR MODULE

DESIGN MODULE

PROM MODULE

II

HSP43220 DDF SIMULATOR SPECIFICATION
D

E

Filter File
Probe Display
Save Cont. Output
Display Mode

PRES.DAR
HEX
YES
CONTINUOUS

Input Rate
Output Rate

33 MHz
100 kHz

C

INPUT SIGNAL SPECIFICATION

I

-

M
A

T

Signal Origin
Signal U
Operator
Signal it2

GENERATED
Amplitude
COSINE
1. 00

Frequency
5 kHz

+
GAUSS

Mean
0.00

StdDev
0.500000

E
FIGURE 3. SPECIFICATION MENU

3-33

Phase
0.00

DEC/-MATE

DESIGti

VIEW

tWtLYSIS

co,tFIG

OsSHELL'

HSP43228 DBF S II'IJLATOR - PIA I"

BDrDES

rmIGI

DDrpJro"

~J

out_seU. HIGH
out_sel" LOU

~!.L!,;,!;L!J

Step Size
....hel'· Sa.ples In
....'bar Sa.p lea Out:

FIGURE 4. SIMULATOR - MAIN MENU

76~H""f""""""""'"

•••••••••••••••••••••••••••••••••••••••••••

45IU+··································· .. ·············...............

•••••••••••••••••••••••••••••••••••••••••••••••••••••.•••••••••

...........................,...,..............

-0.
FlGI.IRE 5. SIMULATOR PROBE DISPLAY

:,l-34

1
It
It

HSP43891

mHARRIS

Digital Filter

May 1991

Features

Description

• Eight Filter Cells

The HSP43891 is a video-speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells
cascaded internally and a shift and add output stage, all in a
single integrated circuit. Each filter cell contains a 9x9 two's
complement multiplier, three decimation registers and a
26-bit accumulator. The output stage contains an
additional 26-bit accumulator which can add the contents
of any filter cell accumulator to the output stage accumulator shifted right by 8 bits. The HSP43891 has a maximum
sample rate of 30M Hz. The effective mUltiply-accumulate
(mac) rate is 240M Hz. The HSP43891 DF can be
configured to process expanded coefficient and word sizes.
Multiple DFs can be cascaded for larger filter lengths without degrading the sample rate or a single DF can process
larger filter lengths at less than 30MHz with multiple
passes. The architecture permits processing filter lengths of
over 1000 taps with the guarantee of no overflows. In practice, most filter coefficients are less than 1 .0, making even
larger filter lengths possible. The DF provides for 8-bit
unsigned or 9-bit two's complement arithmetic, independently selectable for coefficients and signal data.

• 0 to 30M Hz Sample Rate
• 9-Blt Coefficients and Signal Data
• 26-Blt Accumulator per Stage
• Filter Lengths Over 1000 Taps
• Shift-and-Add Output Stage for Combining Filter
Outputs
• Expandable Coefficient Size, Data Size and Filter
Length
• Decimation by 2, 3 or 4
• CMOS Power Dissipation Characteristics

Applications
• 1-0 and 2-D FIR Filters
• Radar/Sonar
• Digital Video and Audio
• Adaptive Filters
• Echo Cancellation
• Correlation/Convolution

Each DF filter cell contains three re-sampling or decimation
registers which permit output sample rate reduction at rates
of 1/2, 1/3 or 1/4 the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and NxN spatial correlations/
convolutions for image processing applications.

• Complex Multiply-Add
• Butterfly Computation
• Matrix Multiplication
• Sample Rate Converters

Block Diagram
Vss

DING-DIN'

iiiENi
CIENB
DCMO-1
EiiAsE

C>---cf---i--;:::::==t=:;=±=t=:;===t=:;===t=:;===t=:;===t=:;===!-----,
COUTO-'

CINO-'

iiESei'
ClK
ADRO-2

26

iiffiT
ClK

SHADD C>~------------------I°S~~UET
SENBl

SfNi'ij

C>~-~if-----------.-----~
26

SUMO-25
CAUTION: These devices are sensHive \0 electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-35

File Number

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HSP43891

PiJl-out~'
85 PIN GRID ARRAY (PGA)

,.
0

DCM1
K

0

0

0

SENBH 9UN14

0

e

Vee
H

D

0

0

0
Vee

0

SUMt.

0

0

v••

Vee

0

0 0 0
Vss SutUt

0

0

SUNil

SUNtS SUllt2 SUNtO

0

0

0

8U ..7.

0

SUMS

0eLK

HSP43891

0

0

BOTTOM VIEW

COUTO SHADD

0

coun

Vss

0

0

0

SUM'

0

SUMO

PINS UP

0

0

CIN,

COUTO

0

0

coo,..

0

0

coon

Vee

0

eOENB

0

AUGH

DIENB

PIN

0
COOTe

O .Q 0
Vss

Vee

0

EiiME

0
"ESET

0

DINB

0

D",7

0

DIN.

0

DIN1

0

DINe

0

DIN<

0

DIN2

SUM23

10

II

8

7

8

6'

4

3

2

1

B4 83 a2 81

•

80 79 78 77 78 7&

COUla
COUT7

SUM..

vs.

Vee

COUTS

BUMlt
9U ..20
SUM18

.......

SUM18

VS.
SUMl7
9UM18

HSP43891
TOP VIEW

IIE8ET

DiENii
DINO

Vee

0lN7

BUYllS

DIN8

SUMt.

DIN5

8UM13

DIN4

8UM1.

Y,ss

DINI

SUMt1

DJN1.

8UNl10

D ...
CIENS

8UMa

SUMO

CINa

8UM7

Vee

3-36

0

DINa

84 PIN PLASTIC LEADED CHIP CARRIER (PLCC)

11

0

SUMS

0

0

elENS

0

DIN.

0

0

VS,

0

su ...

0

8UM2

0

vs.

0

0

cOHO iENii.

0

Vee

0

0

elNO

GIN3

0

eIN7

CINa

0

0

CINa

0

su ...

Vee

0

COUTS COUT4

ceUT5

0

SUM.

0

SUN20 8UMU' 8UM1.

0

DelIO

"

0

8UMlS

0

0

G

0

ADRO

ADA!

0

0

v,.

0

0

Vss

0

8UM25

AD"'

G

0

SUM23 SUNn SUM2l 8UM18 8U"'4

Vee

0

c_

0

vs •

HSP43891
Pin Description
SYMBOL

PIN
NUMBER

TYPE

NAME AND FUNCTION

VCC

Bl,Jl,A3,
K4,L7,Al0,
FlO, Dll

+5 power supply input

VSS

Al, Fl, E2,
K3,K6,L9,
All,E11,
Hll

CLK

G3

I

The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz.

01NQ-8

A5-8,
B5-7
C6,C7

I

These nine inputs are the data sample Input bus. Nine-bit data samples are synchronously
loaded through these pins to the X register of each filter cell of the OF simultaneously.
The DIENB signal enables loading, which is synchronous on the rising edge of the clock signal.

Power supply ground input

.The data samples can be either 9-bit two's complement or 8-bit unsigned values. For 9-bit
two's complement values, 0lN8 is the sign bit. For 8-bit unsigned values, 0lN8 must be
held at logical zero.
DlENB

CINO-8

C5

A9, B9-11,
Cl0,Cl1,
010, E9,

I

I

A low on this input enables the data sample Input bus (0INO-8) to all the filter cells. A rising
edge of the CLK signal occurring while DIENB is low will load the X register of every
filter cell with the 9-bit value present on DINO-8. A high on this Input forces all the
bits of the data sample input bus to zero; a rising CLK edge when OIENB is high will load
the X register of every filter cell with all zeros. This signal is latched inside the
device, delaying its effect by one clock internal to the device. Therefore it must be
low during the clock cycle Immediately preceding presentation of the desired data
on the 01NO-8 inputs. Detailed operation is shown in later timing diagrams.
Thllse nine inputs are used to input the 9-bit coefficients. The coefficients are synchronously
loaded into the C register of filter CELLO if a rising edge of CLK occurs while CIENB is low.
The CIENB signal is delayed by one clock as discussed below.
.

El0

The coefficients can be either 9-bit two's complement or 9-bit u\1signed values. For 9-bit
two's complement values, CIN8 is the sign bit. For 8-bit unsigned values, CIN8 must be
held at logical zero.

ALIGN
PIN

C3

Used for aligning chip on socket or printed circuit board. This pin must be left as a no connect
in circuit

CIENB

B8

I

A low on this input enables the C register of every filter cell and the 0 (decimation) registers
of every filter cell according to the state of the DCMO-l inputs. A rising edge of the ClK
signal occurring while CIENB is low will load the C register and appropriate 0 registers with
the coefficient data present at their inputs. This provides the mechanism for shifting
coefficients from cell to cell through the device. A high on this input freezes the contents
of the C register and the D registers, ignoring the ClK signal. This signal is latched and
delayed by one clock internal to the OF. Therefore it must be low during the clock cycle
immediately preceding presentation of the desired coefficient on the CINO-8 inputs.
Detailed operation is shown in later timing diagrams.

COUTO-8

B2,B3,Cl,
01,El,C2,
02,F2,E3

0

These nine three-state outputs are used to output the 9-bit cosfficients from filter CEll7.
These outputs are enabled by the COENB signal low. These outputs may be tied to the
CINQ-8 inputs of the same OF to recirculate to coefficients, or they may be tied to the
CINQ-8 inputs of another DF to cascade DFs for longer filter lengths.

COENB

A2

I

A low on the COENB input enables the COUTO-8 outputs. A high on this input places all these
outputs in their high impedance state.

L1,G2

I

These two inputs determine the use of the internal decimation registers as follows:

. DCMO-l

OCM1
0

DECIMATION FUNCTION

DCMO
0

Decimation registers not used

0

1

One decimation register is used

1

0

Two decimation registers are used

1

1

Three decimation registers are used

3-37

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HSP43891,
Pin Description

(Continued)

PIN
NUMBER

TYPE

NAME AND FUNCTION

DCMO-1
(Cont)

L1,G2

I

The coefficients pass from cell to cell at a rate determined by the number of decimation
registers used. When no decimation registers are used, coefficients move from cell to cell
on each clock. When one decimation register Is used, coefficients move from cell to cell on
every other clock, etc. These signals are latched and delayed 'by one clock Internal to the
device.

. SUMO-25

J2,J5-8,
J10,K2,
K5-11
L2-6, LB,
L10,L11

0

These 26 three-state outputs are used to output the resuits of the internal filter cell
computations. Individual filter cell results or the result of the shift-and-add output
stage can be output If an individual filter cell result is to be output, the ADRO-2 signals
seiect the filter cell result. The SHADD signal determines whether the selected filter cell
result or the output stage adder result is output. The signals SENBH and SENBL enable
the most significant and least significant bits of the SUMO-25 result respectively. Both
SENBH and SENBL may be enabled simu!taneously if the system has a 26-bit or larger bus.
HoWever individual enables are provided to facilitate use with a 16-bit bus.

SENBH

K1

I

A low on this Input enables result bits SUM16-25. A high on this input places these bits in
their high impedance state.

SENBL·

E11

I

A low on this input enables result bits SUMG-15. A high on this input places these bits in
their high impedance state.

ADRG-2

G1, H1, H2

I

These three inputs select the one cell whose accumulator will be read through the output
bus (SUMG-25) or added to the output stage accumulator. They also determine which
accumulator will be cleared when ERASE is low. These inputs are latched in the OF and
deiayed by one clock internal to the device. If ADRO-2 remains at the same address for
more than one clock, the outPut at SUMO-25 will not change to reflect any subsequent
accumulator updates in the addressed cell. Only the result available during the first clock,
when ADRG-2 selects ths cell, will be output This does not .hinder normal operation
since the ADRG-2 Hnes are changed ssqusntially. This feature facilitates the interface
with slow memories where the output is required to be fixed for more than one clock.

SHADD

F3

I

The SHADD input controls the activation of the shift and add operation in the output stage.
This signal is latched on chip and delayed by one clock Internal to the device. Detailed
explanation is given in the OF OutputStage section .

RESET

A4

I

. A low on this input synchronously clears all the internal registers, except the cell accumulators It can be used with ERASE to also clear all the accumulators simultaneously. This
signal is latched in the OF and delayed by one clock internal to the device.

ERASE

B4

I

A low on this input synchronously clears the cell accumulator selected by the ADRO-2
signals. If RESET is also low simultaneously, all cell accumulators are cleared.

SYMBOL

3..,38

HSP43891
Functional Description
The Digital Filter Processor (DF) is composed of eight filter
cells cascaded together and an output stage for combining
or selecting filter cell outputs (See Block Diagram). Each
filter cell contains a multiplier-accumulator and several
registers (Figure 1). Each 9-bit coefficient is multiplied by a
9-bit data sample, with the result "added to the 26-bit
accumulator contents. The coefficient output of each cell-is-cascaded to the coefficient input of the next cell to its right.

DF Filter Cell
A 9-bit coefficient (CINO-8) enters each cell through the C
register on the left and exits the cell on the right as signals
COUTO-8. The 'coefficients may move directly from the C
register to the output, exiting the cell on the clock following
its entrance. When decimation is selected the coefficient
exit is delayed by 1, 2 or 3 clocks by passing through one or
more decimation registers (D1, D2 or D3).

adder output is loaded synchronously into both the
accumulator and the TREG.
The TREG loading is disabled by the cell select signal,
CELLn, where n is the cell number. The cell select is
decoded from the ADRO-2 signals to generate the TREG
load enable. The cell select is inverted and applied as the
load enable to the TREG. Operation is such that the TREG is
loaded whenever the cell is not selected. Therefore, TR EG is
loaded every clock except the clock following cell selection.
The purpose of the TREG is to hold the result of a sum-ofproducts calculation during the clock when the accumulator
is cleared to prepare for the next sum-of-products
calculation. This allows continuous accumulation without
'
wasting clocks.
The accumulator is loaded with the adder output every
clock unless it is cleared. It is cleared synchronously in two
ways. When RESET and ERASE are both low, the accumulator is cleared along with all other registers on the device.
Since ERASE and RESET are latched and delayed one
clock internally, clearing occurs on the second CLK
following the onset of both ERASE and RESET low.

The combination of D registers through which the coefficient passes is determined by the state of DCMO and
DCM1. The output signals (COUTO-8) are connected to the
CINO-8 inputs of the next cell to its right. The COENB input The second accumulator clearing' mechanism clears a
signal enables the COUTO-8 outputs of the right most cell single accumulator in a selected cell. The cell select signal,
"CELLn, decoded from ADRO-2 and the ERASE signal
to the COUTO-8 pins of the device.
enable clearing of the accumulator on the next CLK.
The C and D registers are enabled for loading by CIENB.
Loading is synchronous with CLK when CIENB is low. Note The ERASE and RESET signals clear the DF internal
that CIENB is latched internally. It enables the register for registers and states as follows:
loading after the next CLK following the onset of CIENB low.
ERASE
RESET
CLEARING EFFECT
Actual loading occurs on the second CLK following the
onset of CIENB low. Therefore CIENB must be low during
No clearing occurs, internal state '
1
1
the clock cycle immediately preceding presentation of the
remains same.
coefficient on the CINO-8 inputs. In most basic FIR
1
RESET only active, all registers except
0
operations, CTEiiJB will be low, throughout the prqcess, so
accumulators are cleared, including,
this latching and delay sequence is onlY'important during
the internal pipeline registers.
the initialization phase. When CIENB is high, the
coefficients are frozen.
EiRASE only active, the accumulator
0
1
whose address is given by the ADRo-2
inputs is cleared.

These registers are cleared synchronously under control of
RESET, which is latched and delayed exactly_like CIENB.
0

The output of the C register (CO-a) is one input to 9x9 multiplier.
The other input to the 9x9 multiplier comes from the output
of the X register. This register is loaded with a data sample
from the device input signals DINO-8 discussed above. The
X register is enabled for loading by DIENB. Loading"is
synchronous with CLK when DIENB is low. Note that
DIENB is latched internally. It ,enables the register for
loading after the next CLK following the onset of DIENB low.
Actual loading occurs on the second CLK following the
onset of DIENB low; therefore, DIENB must be low during
the clock cycle immediately preceding presentation of the
data sample on the DINO-8 inputs. In most basic FIR
operations, DIENB will be low throughout the process, so
this latching and delay sequence is only important during
the initialization phase. When DIENS"is high, the X register
is loaded with all zeros.
The multiplier Is pipelined and is modeled as a multiplier
core followed by two pipeline registers, MREGO and
MREG1 (Figure 1). The multiplier output is sign extended
and input as one operand of the 26-bit adder. The other
adder operand is the output of the 26-bit accumulator..The

0

Both" RESET and ERASE active, all
accumulstors as '!'Iell as all, other
registers are cleared.

The DF Output Stage
The output stage consists of a 26-bit adder, 26-bit register,
feedback multiplexer from the register to the adder, an output
multiplexer and a 26-bit three-state driver stage (Figure 2).
The 26-bit output adder can add any filter cell accumulator
result to the 18 most significant bits of the output buffer.
This result is stored baCk in the output buffer. This operation
takes place in one clock period. The eight LSBs of the
output buffer are lost. The filter cell accumulator is selected
by the ADRO-2 inputs.
The 18 MSBs of the output buffer actually pass through the
zero mux on their way to the output adder input. The zero
mux is controlled by the SHADD input signal and selects
either the output buffer 18 MSBs or all zeros for the adder
input. A low on the SHADD input selects zero. A high on the
SHADD input selects the output buffer MSBs, thus activating the shift-and-add operation. The SHADD signal is
latched and delayed by one clock internally.

3-39

'"a:w

!:i

u:

CI

..--I

HSP438!!1

DCM1.D >---'----------'--------------~-------,
DCMO.D,

>-..,--.,----,--.,.--,----...:...-...:...----,

RESET.D >---,-,--.,.~T_--.,.-------T_--+~----__1t_--__,
CIENB.D

>------'---'-----.

DIENI.D'

>-------,
1- - - -

LD CLR

X REO'
XO-8

DINO-a

I
I

C
MUL TI-

":==~L1'o--lc===============::;:==JlX

PLiER
CORE

L

P8-17
CLK

I
LATCHES

RESET.D

rc>--+

DCMO.O

'iiEsif L>--~r
, DIENI

RESET.D

C>----«I

DIEN •• D

Cifrii
ADRO

I
I
I
I
I
I

DCM1.D

DCMl
DCMO

>-_---~I-_...._l

CIENB.D

C>---i

ADRO.D
AQR1.D

lDRl
ADR2

C>---ii--

AD!l2.D

ERASE

.->----11--

ERASE.D

SIGN EXTENSION

ACC:DO-25

CLK ) -_ _ _---'

ERASE.D
CLK
ERASE
CELL.
CELL 0

ADRO
ADRl
ADR2

DEC,ODER

•••

CELL 1

CELL 7

CELL •• D

AOUTO-25

FIGURE 1. HSP43891 DF FILTER CELL

3-40

I

COUTO-I

I
I
I

HSP43891

CELL RESULTS

o

1

6

This does not hinder normal FIR operation since the
ADRO-2 lines are changed sequentially. This feature
facilitates the interface with slow memories where the
output is required to be fixed for more than one clock.

7

The SUMO-25 output bus is controlled by the SENBH and
SENBl signals. A low on SENBl enables bits SUMO-15. A
low on SENBH enables bits SUM16-25. Thus all 26 bits
can be output simultaneously if the external system has a
26-bit or larger bus. If the external system bus is only 16
bits, the bits can be enabled in two groups of 16 and 10 bits
(sign extended).

DF Arithmetic
Both data samples and coefficients can be represented as
either 8-bit unsigned or .9-bit two's complement numbers.
The 9x9 bit multiplier in each cell expects 9":bit two's
complement operands. The binary format 'of 8-bit two's
complement is shown below. Note that if the most significant or sign bit is held at logical zero, the 9-bit two's
complement multiplier can multiply 8-bit unsigned
operands. Only the upper (positive) half of the two's
complement binary range is used.

SHADD

eLK

The multiplier output is 18 bits and the accumulator is 26
bits. The accumulator width determines the maximum
possible number of terms in the sum of products without
overflow. The maximum number of terms depends also on
the number system and the distribution of the coefficient
and data values. Then maximum numbers of terms in the
sum products are:

SUMO-25

FIGURE 2. HSP43891 DFP OUTPUT STAGE

The,26 least significant bits (lSBs) from either a cell
accumulator or the output buffer are output on the
SUMO-25 bus. The output mux determines whether the cell
accumulator selected by ADRO-2 or the output buffer is
output to the bus. This muxis controlled by the SHADD
input signal. Control is based on the state of the SHADD
during two successive clocks; in other words, the output
mux selection contains memory. If SHADD is low during a
clock cycle and was low during the previous clock, the
output mux selects the contents of the filter cell accumulator addressed by ADRO-2. Otherwise the output mux
selects the contents of the output buffer.
If the ADRO-2 lines remain at the same address for more
than one clock, the output at SUMO-25 will not change to
reflect any subsequent accumulator updates in the
addressed cell. Only the result. available during the first
clock when ADRO-2 'selects the cell· will be output.

MAX # OF TERMS
NUMBER SYSTEM

8-BIT

9-BIT

Two unsigned vectors

1032

N/A

Two two's complement vectors:
• Two positive' vectors
• Negative vectors
• One positive and one negative vector

2080
2047
2064

1032
1024
1028

One unsigned 8 bit vector and one two's
complement vector:
• -Fostive two's complement vector
• Negative two's complement vector

1036
1028

1032
1028

For practical FIR filters, the coefficients are never all near
maximum .value, so even larger vectors are possible in
practice.

3-41

en

...a:~

u:
C

I

HSP43S91
Basic FIR Operation
ft., siropl~,30MH;Z; s:"taP filter ex~mple'~erves

to Illustrate

mor~ clea~!y 'tlie oper~tion' of the; OF. The~eqU~n.fe fable

(Table 1) shows the results of the multiply abcurilUlate in
each ce'lIafter each clock. The cbefficient sequence,Cn; ellters the DF on the left· and moves from left to right titrough
,the cells. The data sample sequence,Xn, enters the DF from
HS.~43891

TABLE 1.'

the top, ,with each cell r~eivirig the same sample simultaneously; !=ach cell accumulates the sum of products for one
output point. Eight.sums of products are calculated simultaneously. but staggered. in time I!O lllat a new output is
available every system cloCk.

30M Hz, 8-TAP FIR FILTER SEQUENCE

X15' .. X9. Xa. X7· . ,Xl'XO .----,------..
.

CLK'

CELLO

0
2

'. C7 xXO
+Ca xXl
+C5 XX2 .

a·
4
5

+C4 X Xa
+C3' x "",
+C2 xX 5

L.

. I

a
7,
a
9
10
11
12
13
14
15

..

+Cl xXa
-l:CoXXT:
C7 XXa
+Ca xX9
+C5 xX l0
' +C4 xX l l
+C3 xX12
+C2 xX13
+C1 XX14
+COX~15

CELL 1
0

O.
0
Cn,x2
+CaxXa
+C5 xX4
+C4 xX5

C7 xX l
+Ca.x l.<2
+C5 XXa
+C4 xX4
+C3 xX5

"

+C3XX~

+<;2 xXa
+C1 XXT
+CoxXa,
C7 XX 9·
+Ca xX l0
+C5 xX l l
+C4 XX12
+C3 xX 13
+C2 xX 14
+Cl, xX 15

~1·Hsp4aa911---~
.....

CELL 3 .

CELL 2

+C2x.X7
+Cl xXa
+CO xX9
C7 xX l0
+Ca xX l1
+C5 XX12
+C4 xX 13
+C3 xX14
+C;!X,X15

,.'(,<

Y15. Y14· •. Ya. Y7

CELL 4

CELLS

CELLS

CELL 7

-

-

-

-

0
0
0

-

C7 XXa'
+Ca XX4
C7 xX4
,+Ca xX5
+C5 xX5
+C4 XXa
+C5 xXa
+C3 xX7
+C4 XX7
+C2 XXa' +C3 xXa
+Cl XX9' +C2 XX9
+CO xX l0 +Cl xXl0
C7 xX l1 +COxXl1
+Ca xX 12
C7 xX 12
+C5 XX 13 +Ca XX13
+C4 XX14 +C5 XX14
+C3~X15 +C4 xX 15

-

,.
-

-

C7 xX 5
+CaxXEi
+C5 xX 7
+C4 XXa
+C3 xX9
+C2 xX l0
+Cl xXll
+COXX12
C7 XX 13
+Ca XX'14
+C5 xX 15

,

C7 xX a
+Ca xX7
C7 XX7
+CaxXa
+C5 xXa
+C4 xX9
+C5 XX9
+C3 xX l0 +C4 xX 10
+C2 XX l l +C3 xXl1
+Cl XX12 +C2 xX12
+CO XX 13 +C1 xX13
+C7 XXt4 ,+CO XX14
+Ca XX 15
C7 xX 15

SAMPLE
DATA IN
(X.)

30MHz
CLOCK

>--

3 BIT
COUNTER'

. Y2 . Yl'

+5V

Yo

J
;

'

I

.

,~PR2

~

r

l

I

I

ADR1 ADRO VCC SHADD

DINO-8

"

DIENB

...

L

1

SENBHSENB~

"

26.

SUMO-25 ~

ClK
HSP43981
A2

Al

AO

00-08
9x8 COEFF.
RAM/ROM

it-+-

9

CINO-B

CiENi DCMl

COUTO-8
DCMO RESET ERASE VSS COENB

1 I I
SYSTEM
RESET

-+- NC

1

I

..I

T

ERASE

FIGURE 3.

HSP43891 30MHz, 8-TAP FIR FILTER APPLICATION SCHEMATIC

'SUM1CLR

-

-

Cell o (Y7)
Cell 1 (Ya)
Cell 2 (Y9)
Cell 3 (yl0)
CeIl4(yll)
Cell 5 (Y12)
cella (y13).
Cell 7 (Y14)
CeIl0(y15) •

HSP43891
Detailed operation of the DF to perform a basic 8-tap, 9-bit
coefficient, 9-bit data, 30MHz FIR filter is best understood
by observing the schematic (Figure 3) and timing diagram
(Figure 4). The internal pipeline length of the DF is four (4)
clock cYcles, corresponding to the register levels CREG (or
XREG), MREGO, MREG1, and TREG (Figures 1 and 2).
Therefore the delay from presentation of data and
coefficients at the DINO-8 and CINO-8 inputs to a sum
appearing at the SUMO-25 output is: k + Td, where k = filter
length and Td 4, the internal pipeline delay of the DF.

After the pipeline has filled, a new output sample is available
every clock. The delay to last sample output from last
sample input is Td.
The output sums, Yn, shown in the timing diagram are
derived from the sum-of-products equation:

=

C{O) x X{n) + C(1) x X{n-1) + C(2) x X{n-2) + C(3)
Y{n)
x X{n-3) + C(4) x X{n-4) + C(5) x X{n-5) + C(6) x X{n-6)
+ C(7) x X{n-7)

=

0123456789

10 11

12 13 14

15 16

17)8

19

20

ClK

ERASE

L--.J

DINO-B
DIENI ~
CINO-B
CIEN.

%Z0l

ADRO-2

1011121314151617101

I~I~I~I~I~I~I~I~I

SUMO-25

...a:
rn

SHADD ~$WWWA

~

SENll ~~400'M

u::

C

SEN.H ij'h0/~~~~
DCMO-l

I

1 1-1------------------------------..
0

7
YN = L CK x XN-K
K=O

FIGURE 4. HSP43891 30M Hz, 8-TAP FIR FILTER TIMING
SAMPLE
DATA IN
(X nl

r=D
C

30MH z
CLOC K

Q

I

I I I +jV-n

1 I 1+t-FI h
ADR1 ADR' ADU Vee .HADD IENIH IENII.
.}. DIND-I

r

ClK
YO
4 BIT YI
CTR, yz
Y3

HSP43891

Ixl. COEFF.
AORAM/RDM
AI

-

AZ

>----OA3

00-01

~

DINa-I

If

iiiiiii

'----

CLl

IUMI..2&

rt

DF1

COUTI-'

CINO-,

ffiiji DCM1 DeMO

f+ Z'

HSP43891

DFO

iiiiET Eiiiii

'SI

1L

~

, REr
8YSTEM
RESET

:.

iiiENi

' - - - CLI

.......... 'r-

IUMI-25

h

ADR1 ADRO ADRZ Vee SHADD SlNlM IENIL

Ciiiii

I

COUlI-'

CI.O-I

Ciiii

'r'

DCM1 DCMO

I

I

r'--.

NC

iiiiU iiiiii ',. Ciiiiii

¥

'r'

I

I I~

'r'
SUM
OUT

(Y.I
FIGURE 5. HSP43891 30M Hz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC

3-43

HSP43891
Extended FIR Filter Length .'

Cascade Configuration

Filter lengths greater that eight taps can be created by
either cascading together multiple OF devices or "reusing"
a single device. Using multiple devices, an FIR filter of over
1000 taps can ,be constructed to operate ata 30MHz
sample rate. Using a single device clocked at 30M Hz, an
FIR filter of over 500 taps can be constructed to operate at
less than a 30MHz sample rate. Combinations of these two
techniques are also possible.

10 design

a

filter length L>8, L/8 OFs are cascaded by
connecting the COUTO-8 outputs of the (i)th OF to the
CINO-8 inputs of the (1+1)th OF. The OINO-S inputs and
SUMO-25 outputs of all the OFs are also tied 'together. A
speCific example of two cascaded OFs illustrates' the
technique (Figure 5). Timing (Figure 6) is similar to the
simple 8-tap FIR, except the ERASE and SENBLiSENBH
signals must be enabled independently for the two OFs in
order to clear the correct accumulators and enable the
SUMO-25 output signals at the proper times.

DATA SEQUENCE
TABLE 2.
INPUT
X30'" X9,X8,X22 ",Xl'XO
COEFFICIENT SEQUENCE
:t
INPUT
Co ",C14,C15,0 ... O,CO ... C14,C15 4HSP43891r. ... 0, Y30'"

!

CLK

CELL 0

CELL 1

CELL2

CELL 3

6

C15XXo

0

o

7
8

+C14XXl
+C13xX2

C15XX1

0
0

9
10
11
12

+C12xX3
+Cll xX4

13

+Cl0 xX5
+C9 xX6
+C8 xX7

14
15

+C7 xX8
+C6 xX9

16
17
18

+C5 xX1O
+C4 XX11
+C3 xX 12

19

+C2 XX13
+Cl x X14

20

o
C15xX2

CELL 4

CELL 7

SUM/CLR

0

+C12 XX6
+Cll xX7
+C1O xX8

C15 XX7
+C14 XX8
+C13 xX 9

+C9 xX 9
+C8 XX 1O,
+C7 XX l l
+C6 xX 12
+C5 xX 13

+C12 XX 1O
+Cll xX11
+Cl0 xX12
+C9 XX13
+C8 xX 14

+C4 XX 14
+C3 xX 15

+Co x X15

o

CO xX 16

23
24

o

Co x X17

+COxX18
CO xX 19

o
o

o

o
o
o

0

26
27

o
o
o

o

25

o
o
o

+C2 xX 16
+Cl x X17

o

o

0
0
0
0

o
o
o

o

CELL 6

C15 xX3
+C14 XX4
+C13 xX 5

21
22

28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

CELLS

Y23,0 ... 0,Y22 .•. Y15,0 ... 0

+C7 XX15
+C6 xX 16

o
o
o
C15 XX8
o
0
o
+C14 xX 9 +C15 xX9
+C15xX1O
0
o
+C13 xX1O
+C12 x X11
o
+C15 XXl l
+C11 XX12
+C15 XX12
+C1O xX 13
+C9 xX14
+C8 xX 15
+C7 XX16
+C6 xX 17
+C5 xX 18
+C4 x X19
+C3 xX20
+C2 xX21
+Cl XX22
+CO xX 23
o
o
o
o

3-44

CeIlO(Y15)
Celll(Y16)

+C5 XX17
+C4 XX 18
+C3 xX 19

CeIl2(Y17)

COXX21

+C2 XX20
+Cl xX21

CeIl5(Y20)
CeIl6(Y21)

o

o

+CoxX22

CeIl7(Y22)

o

o

o
o

COXX20

o

o
o
o
o

o
o
o
o
o

CeIl3(Y18)
CeIl4(Y19)

o

o
o
o
o
C15 xX 15
+C14 XX 16
+C13 xX 17
+C12 XX 18
+Cll xX19
+C1O XX20
+CgxX21
+C8 XX22
+C7 XX23
+C6 xX 24
+C5 xX 25
+C4 XX 26
+C3 xX27

CeIl0(Y23)
Cell 1(Y24)
CeIl2(Y25)
CeIl3(Y26)
CeIl4(Y27)

HSP43891

o

1

2

3

4

5

I

1

•

I

1811

12

13

14

15

11

17

,.

,.

20

21

2223241 25212728283831

32333431

31

37

31

3.

48

CLK

DFOERASE-=======================================;=============:;==============~========:
_____________________________________________________________________________
DFliiiiii' _
DIND~8

I Xo I X, I X2 I X3 I X4 I X, I x,1

X7 I X.

I X,I X,ol Xl1l

X121 X131 X141 X,sl

X,.I Xnl Xl.IX111X20 IX21I X221)(231 12411251121112711211121IX311131 1132I X33I X34 1135 1131' X371

D".'--'~

tING-.

IC,51I:'4I C'3I C12I C11I C,oIC. ICa' C71 c.I C51 C4 1t 31 tzl

CII

Ca ICISIC'4IC'3IC12ICnIC,ol Cg Ie. It7 Ic.1c51c41c31C21 e,1 C.IC15lc'4Ic13lc12lc11lclll

.".'--.L________________________________________________________--------------------I • l' I ' I

'D"-'

3

I' IS I • I

7

I• I

1

I' I, I• I

5

I' I

7

I' I

1

I, I• I

OFO SUMO-ZS

OFt SUMO-2S

DfD

ifriiIiii

SHADD
OF. SENIUH

0.0'-'

=====================~;;;;;;;~~~~~~~~~;;;
I ' ~I----------------------------------------------------------------------------....
IS

K ••

FIGURE 6. HSP43891 16-TAP 30MHz FILTER TIMING USING TWO CASCADED HSP43891s

Single DF Configuration
Using a single DF, a filter of length L>8 can be constructed
by processing in Ll8 passes, as illustrated in Table 2, for
a 16-tap FIR. Each pass is composed of Tp = 7 + L cycles
and computes eight output samples. In pass i, the sample
with indices i*8 to i*8 +(L-1) enter the DINO-8 inputs. The
coefficients Co - CL - 1 enter the CINO-8 inputs, followed
by ~even zeros. As these zeros are entered, the result
samples are output and the accumulators reset. Initial filing
of the pipeline is not shown in this sequence table. Filter
outputs can be put through a FIFO to even out the sample
rate.

bine these partial products by shifting and adding to obtain
the final result. The shifting and adding can be accomplished with external adders (at full speed) or with the DF's
shift-and-add mechanism contained in its output stage (at
reduced speed).

Decimation/Resampling

Extended Coefficient and
Data Sample Word Size

The HSP43891 DF provides a mechanism for decimating
by factors of 2, 3, or 4. From the DF filter cell block diagram
(Figure 1), note the three D registers and two multiplexers in
the coefficient path through the cell. These allow the
coefficients to be delayed by 1, 2, or 3 clocks through the
cell. The sequence table (Table 3) for a decimate-by-twofilter illustrates the technique (internal cell pipelining ignored for simplicity).

The sample and coefficient word size can be extended by
utilizing several DFs in parallel to get the maximum sample
rate or a single DF with resulting lower sample rates. The
technique is to compute partial products of 9x9 and com-

Detailed timing for a 30MHz input sample rate, 15MHz output sample rate (I.e., decimate-by-two), 16-tap FIR filter, including pipelining, is shown in Figure 7. This filter requires
only a single HSP43891 DF.

3-45

en

a:
....

!:i
u:
Q

•

T"-

HSP43891
TABLE 3. HSP4389116-TAP DECIMATE-BY-TWO FIR FILTER SEQUENCEj 30MHz IN, 15MHz OUT
DATA
SEQUENCE
INPuT
COEFRCIENT
SEQUENCE
INPuT
CLK
6
7
8
9
10
11
12
13
14
15
16
17
18
19
-20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
36
36
37

eLK

CELLO

CELL 1

CELL 2

0
0
C15 xXO
0
0
+C14 xX 1
0
+C13 xX2
C15 xX 2
0
+C12 xX3 +C14 XX3
+C11 xX4 +C13x~
C15 xX4
+C10 xX 5 +C12 xX 5 +C14 xX5
+C9 xX6 +C11 xXa +C13 xX6
+C8 xX7 +C10 XX7 +C12 xX7
+Cg xX8 +C11 xX8
+C7 XX8
+C6 xX9
+C8 xX9 +C10 XX9
+C5 XX 10 +C7 XX10 +C9 xX10
+C4 xX11 +C6 xX11 +C8 xX11
+C3 xX12 +C5 xX 12 +C7 XX12
+C2 x X13 +C4 xX13 +C6 xX13
+C1 xX14 +C3 xX 14 +C5.xX 14
+CO XX15 +C2 XX15 +C4 xX 15
C15 XX 16 +C1 XX16 +C3XX1l~
+C14 XX17 +COxX17 +C2 XX17
+C13 xX 18 C15 XX 18 +C, XX18
+C12 xX 19 +C14 xX 19 +CO xX 19
+C1.1 XX20 +C13 xX 20 C15 x.X20
+C10 XX 21 +C12 XX 21 +C14 xX21
+C9 xX22 +C11 xX22 +C13 xX 22
+C8 xX23 +C10 xX 23 +C12 xX 23
+C7x X24 +C9 xX 24 +C,1 xX24
+C6 xX25 +C8 xX 25 +C,.O XX25
+C5 xX26 +C7 XX 26 +C9 xX26
+C4 XX27 +C6 xX27 +C8 xX27
+C3x X28 +C5 xX28 +C7 xX 28
+C2 xX29 +C4 xX 29 +Cs xX 29
+C1 xX30 +C3 xX30 +C5 XX30
+COXXa1 +C2 XX31 +C4 XX31

a

1

2

3

..

I

•

7

•

•

l'

11 12

CELL 3

CELL4

CELL 5

CELL 6

CELL 7

SUM/CLR

0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

0
0

0
0
0
·0
0
0
0
0
0
0
0
0
0
0

-

C15 XX6
+C14 xX7
+C13 xX8
+C12 xX9
+C11 XX10
+C10 XX 11
+C9 xX 12
+C8 xX13
+C7 xX14
+C6 xX15
+C5 XX16
+C4 XX17
+C3 xX 18
+C2 xX 19
+C1 xX20
+COXX21
C15 x X22.
+C14 xX 23
+C13 xX 24
+C12 XX25
+C11 lrX26
+C1Q xX27
+C9 xX 28
+C8 xX 29
+C7 X)(30
+C6 xX 31

13 14

11

1.

C15 xX8
+C14 xX9
+C13 xX 10
+C12 x X11
+C11 xX12
+C10 xX 13
+C9 xX 14
+C8 xX 15
+C7 XX16
+C6 x X17
+C5 XX18
+C4 XX 19
+C3 xX20
+C2 XX21
+C1 XX22
+CO xX23
+C15 x X24
+C14 X X25
+C13 x X26
+C12 xX27
+C11 xX28
+C10 xX29
+C9 X XaO
+C8 x Xa1

17 11

1. ZI

21

1)

0
0
0
0
0
0
0
0
0

C15 xX10
+C14 XX11
+C13 xX12
+C12 xX13
+C11 xX14
+C10 xX15
+C9 xX 16
+C8 xX 17
+C7 xX18
+C6 xX 19
+C5 xX 20
+C4 XX21
+C3 xX 22
+C2 xX 23

C15 XX 12
+C14 XX13
+C13 xX 14
+C12 xX 15
+C11 xX16
+C10 xX 17
+C9 xX 18
+C8 xX 19
+C7 xX 20
+C6 xX21
+C5 xX 22
+C4 xX 23
+C1 xX24 +C3 xX24
+CO xX 25 +C2 xX 25
+C15 xX26 +C1 xX26
+C14 XX 27 +COxX27
+C13 xX 28 +C15 xX28
+C12 xX29 +C14 xX29
+C11 xX30 +C13 xX30
+C10 xX31 +C12 xX 31

22

23 24 21 21

27 2. 2t

30

-

-

C15 xX 14
+C14 xX 15
+C13 XX16
+C12 xX 17
+C11 xXHi
+Cl0 xX 19
+C9x X20
+C8 xX21
+C7'XX22

CeIlO(Y15)

Cell 1(Y17)

CeIl2(Y19)

CeIl3(y21)

CeIl4(Y23)

+C6 xX 23
+C5x X24
+C4 XX25
+C3 xX 26
+C2 XX27

CeIl5(Y25)

CeIl6(Y27)

-

+C1 xX28
+COx X29
C15 xX30
+C14 xX31

31

32

33

CeIl7(Y29)

CeIl8(Y31)

34 31i 3.

37

3'

3. ...

mAsl----------------------------------------~
DIND-'

~--,~------------------------------------------------------------------------------

CINa-1

~--,~--------------------------------------------~--------------------------------

ADRa-!

o I

,

1 •

1

3

1 •

1 •

1 •

1

7

1

0

1 ,

1

SUMI-21
1y,,1 1y,,1 1y,,1 1y,,1 1Y..1 1y,,1 1y.,1 1y,,1 1Y.,1 1y,.1
S.A.O _______________________________________________________________________________

1Ein _________________________________________________________________________________
HNIm ____-----------------------------------------------------------------------------

.eMO-'

I, 11--------------------------------------------------------------------------------+
FIGURE 7. HSP4389116-TAP DECIMATE-BY-TWO FIR FILTER TIM1NGj 30MHz IN, 15MHz OUT

3:..46

Specifications HSP43891
Absolute Maximum Ratings
Supply Voltage ••.••.••.•••••.•••.•••••••••••••.••.•••••••••••••••••••••.••.••.•.•••.•••••..••••.•••••••.••••... +8.0V
Input, Output Voltage .••••••••••••••••••••••••.••••.••••...•••••.••...•...•.•...•••.•.••.•••.•• GND -0.5V to VCC +0.5V
Storage Temperature •.••••••.•..••..•...••.••••••....•••.•••••••••.•• " ••• " ••..• , .• " ...•.• '" .•.••. -650 C to +1500 C
ESD •••••...•••.••••. : •••...••...••....•••.••...••.••.•••.•••••••••••••••.••••• :.: .•••••.••••••••••••.••••••• Clas81
Maximum Package Power Dissipation at700 C ••••••••••••••• -• ••.•••••••••.••••.•...•..•..•••..• 2.4W (PLCC), 2.88W (PGA)
Sjc .•••.•••.••••.•...•••..•••..••••••••.•••••••.•••••••••.••••••••••••••••.••••••••• 11.1 0 CIW (PLCC),7.780 C/W (PGA)
Sja •.••••••.•••••••.•• : •••••••••••••..•••.•.•..•••.•••.•..••••••.•••••.•.•••••••••• 33.7OCIW (PLCC), 34.66OCIW (PGA)
Gate Count •••••.••••.•••••.••••.•.•..••••.••••• ,--••.••.••••••••.••••••••.•.••.•.•••••••••.••.•••••••••••••••••• 17763
Junction Temperature .••••••••.••••• :. • • • • • • • • • • . • • • • • • • • • . • • • • • • . • • • . • . • • • • • • • • • • • • • • . • • •• 1500 C (PLCC), 1750 C (PGA)
Lead Temperature (Soldering 1Os) •••••.•.•••••••..•••.••••.••••.••••••••••••••••••••• : ••.••••••••••••••••••••••• 3000C
CAUTION: Stresses above those listed In the "Absolute Maximum Ratings" may cause permanent damage to the clev;ce~ This ;s a· stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not imp/led.

Operating Conditions
Operating Voltage Range •••••••••••••••.••••••••••••.••••••••••••••••••••••••..••••••••••••••••••••••••••••••• 5V ±5%
Operating Temperature Range ............................................................................ OoC to + 700C

D.C. Electrical Specifications
SYMBOL
ICCOp

PARAMETER
Power Supply Current

MIN

MAX

UNITS

-

160

mA

TEST CONDITIONS
VCC=Max
CLK Frequency 20M Hz
Note 1, Note 3

c:n

CI
I

-

500

pA

VCC = Max, Note 3

II

Input Leakage Current

-10

10

pA

VCC = Max, Input = OV or VCC

10

Output Leakage Current

-10

10

pA

VCC = Max, Input = OV or Vee

VIH

Logical One Input Voltage

2.0

-

V

Vcc=Mex

VIL

Logical Zero Input Voltage

0.8

V

VeC=Min
10H = -400pA, Vec = Min

ICCSB

Standby Power Supply Current

VOH

Logical One Output Voltage

2.6

-

V

VOL

Logical Zero Output Voltage

-

0.4

V

10L = 2mA, Vee = Min

VIHC

Clock Input High

Vee-0.8

-

V

Vee = Max

VILe

Clock Input Low

0.8

V

Vce=Min

elN

Input Capacitance

PLeC
PGA

10
15

pF
pF

Output Capacitance

PLee
PGA

10
15

pF
pF

CLK Frequency 1 MHz
All measurements referenced
toGND
TA=25OC. Note 2

COUT

-

NOTES: 1. Operating supply current Is proportional to frequency. Typical
rating is BmA/MHz.
2. Controlled via design or process parameters and not directly
tested. Characterized upon initial design and after major process
and/or design changes.
3. Output load per test load circuit and CL - 40pF.

3-47

ex:
w

!:i
u:

...

Specifications HSP43891
A.C. Electrical Specifications

-

vcc

= 5V ± 5%, TA = (lOC to +70OC

-20 (20MHz)
SYMBOL

PARAMETER

MIN

TCp

Clock Period

50

TCl'

Clock low

,20

TCH

Clock High

20

TIS

IIlPutSetup

16

TIH

Input Hold

0

TODC

ClK to Coefficient
Output Delay

MAX

-25 (25.6MHz)
MIN

-

39
16

-

-

16
14

-

0

24

-

TOED

Output Enable Delay.

TODD

Output Disable Delay

TODS

ClKtoSUM
Output Delay

-

27

TOR

Output Rise
Output Fall

-

6

TOF "

20
20

6

MAX

-

-'30 (30MHz)
MIN

MAX

33

-

ns

-

13

0

-

ris

20

-

18.

ns

15

ns

15

ns

13

ns
ns

15

-

25

-

21

ns

6

-

6

ns

Note 1

6

-

6

ns

Note 1

-

15

-

Note 1

NOTE: 1. Conlrolled by design or process parameters and not directly
tested. Characterized upon initial design and after major process

and/or design changes,

Test Load Circuit

r- - - - - - - - - - - -

~,,""-,-

1

:

1

1

1

1

1

1
1
1
1

1.5V

1

IOL

.1

1

I ,

"INCLUDES STRAY AND
JIG CAPACITANCE
1_ _ _ _

EQUIVALENT~IRcurr _

Swftch S1 Open for ICCSS and ICCOp Tests

3-48

TEST
CONDITIONS

'ns

-

13

UNITS.,

--'- ~ _

1

J

HSP43891
Waveforms

~;-TCL=1

cu<~VSV_

INPUT·

.r---~--------VCC

CLK

O.OV

.

3.0V-----....,

y.2.-sv-""'""'L
.

O.OV------'

- - --- -------

• Input includes: DINO-7, CINO-7, DIENB, CIENB, ERASE, RESET,
DCMO-', ADRO-', TCS, TCCI, SHADD

CLOCK AC PARAMETERS

I

·0.4V

INPUT SETUP A1IID HOLD

\ . . . ---

CLK 2. 5V

25~
__...;...---, rTODC1'.SVTODS

SUMO -

r

COUTO-8

OUTPUT

-----I

SUMO-25, COUTO-S, OUTPUT DELAYS

ENABLE

RISE AND FALL TIMES

1.5V

TOED
OUTPUT

1.5V

~.~______________~~TODD
1.3V

A.C. Testing: Inputs are driven at3.0V for a logic "'" and O.OV for a logic
"0". Input and output liming measurements are made at'.5V for both a logic
"'" and "0". Inputs driven at' V/ns. ClK is driven at VCC -0.4 and OVand
measured at 2.5V.

A.C. TESTING INPUT, OUTPUT WAVEFORM

OUTPUT ENABLE, DISABLE TIMING

3-49

H$P43891/88.3

mHARRIS

Digital Filter'

May 1991

Features'

Description

• This Circuit Is Processed In Accordance to Mil-Std-883C
and Is Fully Conformant Under the Provisions of
Paragraph 1.2.1
-

The HSP43891/883 is a video-speed Digital Filter (DF)
designed to efficiently implement vector operations
such as FIR digital filters. It Is comprised of eight filter
cells cascaded internally and a shift and add output
stage, all in a single integrated circuit. Each filter cell
contains a 9x9 two's complement multiplier, three
decimation registers and a 26-bit accumulator.
The output stage contains an additional 26-bit
accumulator which can add the contents of any filter
cell accumulator to the output stage accumulator
shifted right by 8 bits. The HSP43891/883 has
a maximum sample rate of 25.6MHz. The effective
multiply-accumulate (mac) rate is 204M Hz. The
HSP43891/883 DF can be configured to process
expanded coefficient and word sizes. Multiple DFs
can be cascaded for larger filter lengths without
degrading the sample rate or a single DF can process
larger filter lengths at less than 25.6MHz with multiple
passes. The architecture permits processing filter
lengths of over 1000 taps with the guarantee of no
overflows. In practice, most filter coefficients are less
than 1.0, making even larger filter lengths possible.
The DF provides for 8-bit unsigned or 9-bit two's
complement arithmetic, Independently selectable for
coefficients and signal data.

• 0 to 25.6MHz Sample Rate
• Eight Filter Cells
• 9-Bit Coefficients and Signal Data
• Low Power CMOS Operation
~ ICCSB
500jiA Maximum
~ ICCOp = 160jiA Maximum @ 20MHz

=

• 26-Blt Accumulator per Stage
• Filter Lengths Up to 1032 Taps
• Shlft-and-Add O·utput Stage
Outputs
"

for

Combining

Filter

• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4

Applications
• 1-0 and 2-D FIR Filters
• Radar/Sonar
• Digital Video and Audio
• Adaptive Filters
• Echo Cancellation
• Correlation/Convolution

Each DF filter cell contains three re-sampllng or
decimation registers which permit output sample rate
reduction at rates of 1/2,1/3 or 1/4 the Input sample
rate. These' registers also provide the capability to
perform 2-D operations such as matrix multiplication
and NxN spatial correlations/convolutions for image
processing applications.

• Complex Mldtlply-Add
• Butterfly Computation
• Matrix Multiplication
• Sample Rate Converters

Block Diagram
'ss

CINa-1

DINI-DINI

c:,..:;,'-----I

COUTa-1

iiEffi
ADR~~: c:....:,'-t---:+--~-+--~+---+--I----4---+--'-'-+---+--I----4---+---'

RESET

CLK
SHADD D-------------------I0SU::O~T

UiIL c:~-~-------------~

SENIH

21

SUMI-ZI

CALrrION: These deviceS are sensftlve to electrostatic discharge. Preper t.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-50

File Number

2451.1

HSP43891/883

Pinouts
85 PIN GRID ARRAY (PGA)

4

"
VS•

COEiifs

Vee

RESET

DIN7

.,NO

DiNa

OINO

coo.

Vee

I.

0 0 0 0 0 0 0 BUNl13
0 0
DCMt SUM23 8UM22 SUM2t SUM18 SUMI4 Vee

Vso

v.s

0 0 0
BeNBH BUMU

Vee

Vso

0

0 0
BUMla

Vee

v ••

0

ADAI

0

ADAI

0

V••

"ss

....

0

SUM7

0

0

SUMIS

ADAD

0

DeMO

0

0C1.K
0

0

HSP438911B83
BOTTOM VIEW

COUTO SHADD

0

0

COUTl

"ss

0

0

0

0

0

.ORI

0 0 0 0 0
BUNtS SUNI2 SUMIO 8UMB SUMB

0 0 0
SUM20 8UM17 8UMI8

0 0
Vee SUMIS

SUMI

0

SUMO

PINS UP

0

0

COUT2

OINI

e

COUll!! COUTI

0
Vee
A

DCM.

0

Vso

0
0

0

Vee

0
OINO

0lN2

0

0

iiiENi

AUGN
PIN

0

COUT7 COUTS

eOENB

0

8UM3

0

COUT3 COUT4

vee

0

Vee

0
ERASE

0
RESEr

0

DIN5

0

0

DINS

OINI

0
DIN7

"

0 0
SUMl1 SUMa

0

01N4

0

0

OINO

DIN2

0
DIN3

0

ClENB

0

0",.

0

0

v..

0

SUM4

0

SUMO

0

Vss

0
SENIL

0

vee

0

0

CIN5

0lN3

0

0

0lN7

elNo

elN4

0

0

0

CINa

Vee

v••

tn

a:
w

~
;:;:
CI
I

84 PIN CERAMIC QUAD FLATPACK

COUT8

COUT7

VSS
COUT8

SUM21

COENB

Vee

EAA8e

HSP43891/883
TOP VIEW

RESET

DIENB

DIN8
DIN7

DIN8
DIN&
01N4

DIM3
DIN2
DINI

BUM',

DINO

CiENi
CINS

Vee

3-51

Specifications H8P43891 /883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ••••••••••••.•••.•.•••••••••••••••••••.. +8.0V
Input, Output Voltage Applied •••••••••• GND-0.5V to VCC+0.5V
Storage Temperature Range •••••••••••••••.• -650C to +1500 C
Junctian Temperature • .' ••••••••••••••••.•• "' ••••••••• +1750 C
Lead Temperature (Solderirig, Ten Seconds) : •••.••••••• +3000 C
ESD Classificaticm ••••••••. , .......................... Class 1

Thermal Re~istance
Dia
Dic
Ceremic PGA Package ••••••••••••• 34.660 C/W 7.780 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic PGA Package ............................ 1.44 Watt
Gate Count .......... ~ •. ;; ............. ~'. ....... 17762 Gates

permanent

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause
darjlage to the device. This is a stress only rating and op&'~tion
of the device a"t these or . any. ot~r conditions above those >indicatSd in the operations' sections of this: specification is not implled~
.

Operating Conditions
Operating Voltage Range •••••••••••••••••.••••• +4.5V to +5.5V
Operating Temperature Range •••••••••••••• , -550 C to +1250 C
TABLE 1. HSP43891/883 D.C. ELECTRICAL PERFORMANCECHARACTERISnCS
Devices Guaranteed and 00% Te~ted

1

PARAMETER

SYMBOL

CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

2.2

-

V

Logical One Input
Voltage

VIH

VCC=5.5V

1,2,3

-550C :$.TA$ +1250 C

Logical Zero Input
Voltage

VIL

VCC;=4.5V

1,2,3

-55°C $ TA !i;t1250 C

-

0.8

V

Output HIGH Voltage

Voi;

IOH=-400fJA
VCC = 4.5V(Note 1)

1',2,3

-550C :$.TA$ +1250 C

2.6

-

V

Output lOW Voltage

VOL

IOL=+2.0mA
VCC = 4.5V (Note 1)

1,2,3

-550C :$.TA:$. +1250 C

-

0.4

V

Input leakage Current

II

VIN = VCC or GND
VCC=5.5V

1,2,3

-550C $TA:$. +1250 C

-10

+10

fJA

Output leakage Current

10

VOUT = VCC or GND
" VCC= 5.5V

1,2,3

-55°C,,:$.TA:S..+1250 C

-10

+10

fJA

-

V

0.8

V

-55°C :$.TA:$. +125Oc

-

500

fJA

1,2,3

-550 C$TA:$+1250C

-

160.0

mA

7,8

-550 C$TA$+1250C

-

Clock Input High

VIHG

VCC"'5.5V

1,,2,3

-550C :S..TA < +1250 C VCC-0.8

Clock Input Low

VllC

VCC=4.5V

1,2,3

-550 C,:S..TA:$.+1250 C

1,2,3

Standby Power Supply
Current

ICCSB

VIN = VCC or GND
VCC = 5.5 V,
Outputs Open

Operating Power
Supply Current

'oCOP

f=20.0MHz
VCC = 5.5V (Note 2)

Functional Test

-',

FT

(Note 3)

=

NOTES: 1. Interchanging of force' and sense conditions is permitted.
2. Operating Supply,Cu(rent is proportional to frequency,typical
rating is 8mA/MHz. ' '.

= 0.4.

3. Tested as follows: f
1 MHz. VIH -, 2.6. VIL
VOL :5. 1.5V. VIHC = VCC -0.4V. a.~d VILC = 0.4V.

3-52

VOH 2: 1.5V.

Specifications HSP43891/883
TABLE 2. HSP43891/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
-20 (2OMHz)

GROUP A
SYMBOL CONDITIONS SUBGROUPS

PARAMETER

-25 (25.6MHz)

TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

TCp

Note 1

9,10,11

-550 C 5. TA 5. +1250 C

50

39

-

ns

TCl

Note 1

9,10,11

-550 C 

.ooa&--L.012

1iQIE;
A

INCREASE MAXIMUM LIMIT BY .00:5" WHEN SOLDER
DIP OR TIN PLATE LEAD FINISH APPLIES.

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C ± 100 C
Method: Furnace Seal
NOTE: All Dimensions are

MMin

ax

• Dimensions are in inches.

INTERNAL LEAD WIRE.:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510C-G6

tMil-M-38510 Complianl Malerial •• Finishes, and Dimensions.

3-57

m

HSP4388 ,1

HARRIS-

Digital Filter

May 1991

Features

Description

• Eight Filter Cells
• 0 to 30MHz Sample Rate

The HSP43881 is a video speed Digital Filter (OF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells
cascaded intein'idly and a shift and add output stage, all in a
single integrated circuit. Each filter cell contains a 8x8 bit
multiplier, three decimation registers and a 26-bit
accumulator. The output stage contains an additional 26-bit
accumulator which can add the contents of any filter cell
accumulator to the output stage accumulator shifted right
by 8 bits. The HSP43881 has a maximum sample rate of
30M Hz. The effective multiply "accumulate (mac) rate is
240M Hz. The HSP43881 OF can be configured to process
expanded coefficient and word sizes. MultipleDFs can be
cascaded for larger filter lengths without degrading the
sample rate or a single DF can process larger filter lengths
at less than 30M Hz with multiple passes. The architecture
permits processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter
coefficients are less than 1.0, making even larger filter
lengths possible. The DF provides for 8-bit unsigned or
two's complement arithmetic, independently selectable for
coefficients and Signal data.

• 8-Bit Coefficients and Signal Data
• 26-Bit Accumulator Per Stage
• Filter Lengths Over 1000 Taps
• Shift and Add Output Stage for Combining Filter
Outputs
• Expandable Coefficient Size, Data Size and Filter
Length
• Decimation by 2, 30r4.
• CMOS Power Dissipation Characteristics

Applications
• 1-0 and 2-D FIR Filters
• Radar/Sonar
• Digital Video and Audio
• Adaptive Filters
• Echo Cancellation
• Correlation/Convolution
• Complex Multiply-Add

Each OF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
of 1/2, 1/3.or 1/4 the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multipliCation and NxN spatial correlations/convolutions for image processing applications.

• Butterfly Computation
• Matrix Multiplication
• Sample Rate Converters

Block Diagram
VCC

vss

rr

DINo- DlN7

TCS

DIENB
CIENB 5
DCMO-l ~~,---+---~---r-+~~~~--.---+----.---i--~~--r---~---r--~
ERASE
TCCI

TCCO

COUTO •
COUTo-7
RESET

AD~>75~7'+-r---~--+---~~~----~~r---~~~--~+--+----~--r---~

RESET

COENB

~=---------.C:::'

ClK
SHADD,>-____________________
- -____------_I

SENBL,)-__~2~/~----------~---------------I
SENBH'
;"

__~-J

SUMo-25

CAUTION: 'These devices are-sensRiveto electrostatic dlsc~arge. Users should follow proper IC Handling Procedures.
Copyright @ Harris Corporation 1991

3-58

File Number

2758. f

HSP43881

Pinouts
85 PIN GRID ARRAY (PGA)

Vss

RESET

DIN1

D'NS

Vcc

EiiAS£

TCS

DIN'

DIN3

D'IOI

TCCI

Vcc

Vss

D'"

CiENii

elN7

C'NS

C,...

e,NS

C,...

0

0

0

0

0

0

DCM, SUN2a SUN22 SUM2l SUMl8 SUM14

0

SENiiH

0

SUM24

0

Vss

0

Vee

0 0
Vee

0

SUM20

SUMts

0

ADA,

coun
Vss
G

H

AOAt

A"'"

Vee

K

0

Vss

A"".

0

COUTO

v..

DeMO

SUM3

SUMS

A"...

SUM2

0

0

SUM'S SUNIl SUN10

0

0

SUM'7 SUM I .

0

SUM5

0eLK

HSP43881

0

0

BOTTOM VIEW

COUTO SHADD

0

0

0

0
0

Vcc

0

0

SUMI

0

SUMO

PINS UP

0

0

coun

CINI

0

P'"

0

COUT7 TCCO

V..

0

vee

0

CINO

0

Q. 0

D'ENa

0

EiiASi!

0

Tes

0 ~ 0 RESET
0 0
C"""B Vee

SU ...

0

SUM3

CIN2

eOUTB AUGH

0

0

SUMS

SUNT

0

DeNa

0

SUMI,

0

0

0

COUT5

SUMB

D CN,

0

0

Vss

COUTa COUT4

Vss

SUMI5

0

Vss

0

SUM1S

A. . .

coun Vss
D

su...,

0

SUMI.

0

Vee

DIN7

DINS

0

DINI

0

DIN6

0

0

c, ..

0lN4

0

DIN2

0

DINa

0

e'ENB

0

DINa

0

0

elN7

CINe

0

0

TCCI

Vcc

0

SUMa

0

SUMe

0

Vss

0

SUN4

0

SUM2

0

Vss

0

9ENii

0

vee

0
elN3

0

CIN4

0

Vss

tn

a::
....

~

u::
C

84 LEAD PLCC PACKAGE
~

~

SUM23

I

&!

~

•

COUT8

COUT1

SUM22

vss

Vee

Teeo

SUM2l

SUM20

COENB

SUM19

Vee

SUM18

ERASE

Vss
BUM17

SUM18

HSP43881
TOP VIEW

RESET
DIENB
TeS
DIN7

Vee
SUM15

DINS

SUM14

DINS

BUM12

D''''
DIN.

Vss

DIN2

SUM11

DIN1

SUM13

DIND

SUM10
SUMe

elEND

8UMB

Teel

SUM7

Vee

NOTE: An overbar on a signal name represents an active LOW signal.

3-59

HSP43881
Pin Description
SYMBOL

PIN
NUMBER

TYPE

NAME AND FUNCTION

VCC

A3;A10,B1, '
'D11,F10,J1;
'K4,L7

+5V Power Supply Input

VSS

A1,A11,E2,F1;
E11,H11,K3.
K6,l9

Power Supply Ground Input

CLK

G3

I

The CLK Input provides the OF system sample clock. The maximum clock frequency is
is30MHz. '

DIND-7

A5-8,B&-7,
C6-7

I

These eight inputs are the data sample input bus. Eight'bftdata samples are synchronously
loaded through these pins to the X register of each filter cell simultaneously.
The DiENe signal enables loading, which Is synchronous on the rising edge of the clock signal.

TCS

B5

I

The TCS input determines the number system interpretation of1l1e data input samples
on pins DlNO-7 as follows:
TCS Low _ Unsigned Arithmetic
TCS

=
=High _

..

Two's Complement Arithmetic

The TCS signal is synchronously loaded into the X register in the same way
as the DINO-7 inputs.
. DIENB

C5,

A low on this enables the data sampie input bus (DINO-7) to all the fiHer cells. A riSing
edge of the CLK signal occurring while DIENB is low will load the X register of
every filter cell with the 8 tiit value present on DINO-7. A high on this inputforces
all the bits ofthe data sample input bus to zero; a riSing CLK edge when DIENB is high
will load the X register of every filter cell with all zeros. This signal is latched inside
the OF, delaying its effect by one clock Intemal to the OF. Therefore, It must be low
during the clock cycle immediately preceding presentation of the desired data on the
DINO-7 inputs. Detailed operation Is shown In later timing diagrams.

I

..

CIND-7

TCCI

B9-11,C1D-11,
D10,E9-10

I

A9

I

,

, ..

,

these eight i(lputs are used to input the ,8 bit coefficients. The coefficients are synchronously
synchronously loaded Into the C register of filter CELL 0 if it rising edge of ClK
occurs'While GIENB'is low; The CIENB signal is delayed tiy one clock as discussed below.
The TCCI Input determines the number system interpretation of the coefficient
inputs on pins CINO-7 as follows:
TCCI LOW _ Unsigned Arithmetic
TCCI

=
=HIGH _

Two's Complement Arithmetic

The TCCI signal is synchronously loaded into the C register in the same way as
the CINO-7 inputs.
CIENB

B8

I

A low on this Input enable the C register of every filter cell and the 0 registers (decimation)
of every filter cell according to the state ofthe DCMO-1 inputs. A rising edge of
the ClK signal occur,ring while CIENB is low will load the C register and appropriate
o registers with the coefficient data present at their inputs. This prlvides the mechanism
for shifting the coefficients from cell to cell through the device. A high on this input
freezes the contents of'the C register and the 0 registers, ignoringthe 'ClK signal.
This signal is latched and delayed by one clock internal to the OF; Therefore, It must be
low during the clock cycle immediately preceding presentation of the desired coefficient
on the CINO-7 inputs. Detailed operation is shown In the Timing Diagrams section.

0

These eight three-state outputs are used to output the 8 bit coefficients from filter cell 7.
These outputs are enabled by the COENB signal low. These outputs may be tied to the CINO-7
Inputs ofthe same OF to recirculate the coefficients, or they may belied 10 the
CINO-7 Inputs of another DFto cascade DFs for longer filter lengths.

,
"

COUTO-7

B2, C1-2;01-2
E1,E3,F2

TCCO

B3

0

The TCCO three-state output determines the number system raprase(llation of the coefficients
output on COUTO-7.ltlracks the TCCI signallo this same OF. II shOuld be tied to the TCCI
input ofthe next OF in a cascade of DFs for increased filter lengths. This,signal is enabled
by CoEiiiB low.

COENB

A2

I

A"low on the C,OENJ;i input enables the COUTD-7 and the TCCOoutput. A high on this Input
places allth~sEl ~tputs in their;hiQli Impedance state:
'

,,'

3-60

HSP43881
Pin Description (Continued)
SYMBOL

PIN
NUMBER

TYPE

DCMO-1

G2,L1

I

NAME FUNCTION
These two inputs determine the use of the intemai decimation registers as follows:
DCM1
DCMO
Decimation Function

----0
0
0
1
1

1
0
1

Decimation registers not used
One decimation register is used
Two decimation registers are used
Three decimation registers are used

The coefficients pass from cell 10 cell at a rate determined by the number of decimation
registers used. When no decimation registers are used, coefficients move from cell to cell
on each clock. When one decimation register is used, coefficients move from cell to cell on
every other clock, etc. These signals are latched and delayed by one clock internal to the OF.
J2,J5-8,
J10,K2,
K5-11,
L2-6,L6,
L1o-11

0

SENBH

K1

I

A iow on this input anables result bits SUM16-25. A high on this input placas these
bits in their high impedance state.

SENBL

E11

I

A low on this Input enables result bits SUMO-15. A high on this input placas these

ADRo-2

G1, H1-2

I

These inputs select the one cell whose accumulator will be resd through the output bus
(SUMo-25) or added 10 the output stage accumulator. They also determine which accumulator
will be cleared when ERASE is low. For selection of which accumulator to read through the
output bus (SUMO-25) or which 10 add of the output stege eccumulalor, these inputs are
latched in the OF and delayed by one clock Internal 10 the device. II the ADRO-2 linea remain
at the same address for more than one clock, the output at SUMO-25 will not change to reflect
any subsequent accumulator updates In the addressed cell. Only the result available during
the first clock, when ADRO-1 selects the cell, will be output. This does not hinder normal
operation since the ADRO-1 lines are changed sequentially. This feature facilltstea the
Interface with slow memories where the output is required to be fixed for more than one clock.

SHADD

F3

I

The SHADD input controls the activation of the shift-and-add operation in the output stage.
this signal is latched in the OF and delayed by one clock internal 10 the device. A detailed
explanation is given in the OF Output Stage section.

RESET

A4

I

A low on this input ~ousIy clears aI the Internal registers, except the cell accumulators.
It can be used with ERASE 10 also clear all the accumulators simultaneously. This signal is
latched In the OF and delayed by one clock internal to the OF.

ERASE

B4

I

A ~this Input synchronously clears the cell accumulator selected by the ADRO-1 signals.
II RESET Is also low Simultaneously, all cell accumulators are cleared.

ALIGN PIN

C3

SUMO-25

These 26 three-slate outputs are used 10 output the results of the internal filter cell
computations. Individual filter cell results or the result of the shift-and-add output stage
cen be output. If an individual filter cell result is to be output, the ADRo-2 signals select
the filter cell result The SHADD signal determinea whether the sel~ter cell result
or the output stage adder result Is output. The signals SENBH and SENBL enable the most
significant and least significant bits of the SUMO-25 result, respectively. Both SENBH
and SENBL may be enabled simultaneously if the system has a 26 bit or larger bus. However,
individual enables are provided to facilitate use with a 16 bit bus.

...
rn

a:

Used for aligning chip in socket or printed circuit board. Must be left as a no connect in circuit.

3-61

~

u::
CI
.,...I

HSP43881
Functional Description

adder operand Is the outP\lt of the 26-bit.accumulator. The
adder output is loaded synchronously into both the
accumulator and the TREG.
The TREG loa(jing is disabled by.the c:;ell sel~tsignal,
CELLn, where n. is the cell number. The cell select is
decoded from the ADRO-2 signals to generate the TREG
load enable. The cell select is loverted and applied as the
load enable to the TREG. Operation is such that the TREG is
loaded whenever the cell is not selected. Therefore, TREG is
loaded every clock except the clock following cell selection.
The purpose of the TREG is to hold the result of a sum-ofDF Filter Cell
products calculation during the clock when the accumulator
A 8-bit coefficient (CINO:"7) enters each cell through the C . is cleared to prepare for the next sum-ot-products
register on the left and exits the cell on the right as signals calculation. This allows continuous accumulation without
COUTO,.7. The coefficients may move directly from theC wasting cloc.ks.
register to the output, exiting the cell on the clock following
The accumulator is loaded with the adder output every
its entrance. When decimation is selected the coefficient
clock unless it is. cleared. It Is cleared synch ronously in two
exit is delayed by 1,2 or 3 clocks bypassing through one or
ways. When RESET and ERASE are both low, the
.
more decimation registers (D1, 02 or D3).
accumulator is cleared along with all other registers on the
The combination of D· registers through which the device. Since ERASE and RESET are latched and delayed
coefficient passes is determined by the state of DCMO and one clock internally, clearing occurs on the second CLK
DCM1. The output signals (COUTO-7) are connected to the following the onset of both ERASE and RESET low.
CINO-7 inputs of the next cell to its right. The COENBinput The second accumulator clearing mechanism clears a
signal enables the COUTO-7 outputs of the right most cell single accumulator in a selected cell. The cell select signal,
to the COUTO-7 pins of the:device.
CELLn, decoded from ADRO-2 and the ERASE signal
enable clearing of the accumulator on the next CLK.
The C and· D registers are enabled for loading by CIENB.
Loading is synchronous with CLK when CIENB is low: Note The ERASE and RESET Signals clear' the DF internal
that CIENB is latched internally. It enables the register for registers and states as follows:
loading after the next CLKfo.llowing the onset ofC'iENiflow.
ERASE
RESET
CLEARING EFFECT
Actual loa(jing occurs on the second CLK following the
No clearing occurs, internal slate
onset of CIENB low. Therefore ·CIENB must be low during
1
.1
remains same
the 'cioCk cycle immediately preceding presentation of the
coefficient on. the CINO-7 inputs. In mo::;t. basic FIR
1
0
RESET only active, all registers except
.operations, CIENa will be low throughout the process, so
accumulators are cleared, including
this latching and delay sequence is only important during
the internal pipeline registers.
the initialization phase. Wi')en CIENB is high, the
1
ERASE only active, the accumulatOr
0
coefficients are frozen.
whose address is given by the ADRO-2
The Dig Hal Filter Processor (DF) is composed of eight filter
pells cascaded together and an output stage for combining
or selecting tllter cell outputs (See Block Diagram). Each
filter cell contains a multiplier-accumulator and several
registers (Figure 1). Each8-bit cQ9fflcient is multiplied by a
8- bit data sample, with the result added to· the 26-bit
accumulator contents. The coefficient output of each cell is
cascaded to the coefficient input of the next cell to its right

inputs is cleared.

These registers are cleared synchronously under control of
RESET, which is latched and delayed exactly like CIENB.

0

The output of the C register (CO..,8) is one input to 8 x 8 multiplier..
.
The other input to the 8x8 multiplier comes· from the output
.of the x register. Tills register is loaded with a data sample
from the device input signals DINO-7 discussed above. The
X register is enabled for loading by DIENB. Loading is
synchronous with CLK when DIENB is low. Note that
DIENB is latched internally. It enables the register for loading after the next CLK following the onset of DIENB low. Actual loading occurs on the second CLK following the onset
of DIENB low; therefore, DIENB must be low during the
clock cycle immediately preceding presentation of the data
sample on the DINO-7 inputs. In most basic FIR operations,
DIENB will be low throughout the process, so this latching
and delay sequence is only important during the
initialization phase. When DIENB is high, the X register is
loaded with all zeros.
The multiplier is pipelined and is
core followed by two pipeline
MREG1 (Figure 1). The multiplier
and input as one operand of the

modeled as a multiplier
registers, MREGO and
output is sign extended
26-bit adder. The other

0

Both RESET and ERASE active, all
accumulators as well as ail other
registers are cleared.

The DF Output Stage
The output stage cons isis of a 26-blt adder, 26-bitregister,
feedback multiplexer from the register' to the adder, an
output multiplexer and a 26-bit three-state driver stage
(Figure 2).
The 26-bit output adder can add any filter cell accumulator
result to the 18 most significant bits of the output buffer.
This result is stored back in the output buffer. This operation
takes place in one clock period. The eight LSBs of the output buffer are lost. The filter cell accumulator is selected by
the ADRO-2 inputs.
The 18 MSBs of the output buffer actually pass through the
zero mux on their way to the output adder input. The zero
mux is controlled by the SHADD input signal and selects
either the output buffer 18 MSBs or all zeros for the adder
input. A low on the SHADD input selects zero. A high on the
SHADD input selects the output buffer MSBs, thus
activating the shift-and-add operation. The SHADD signal
is latched and delayed by one clock internally.

3-62

HSP43881

DCM1.D
DCMO.D

>---------------------------------,
>-------------------,

~>------~--------~--_r-----~----_,
CIENaD>-------~~------------~_r----_r-------~_t-----,
TCCI

3-STATE BUFFERS
ON CEll 7 ONLY

-------1

>--...-----1

1
1

I
1
TCCO

COUTO-7

1

1
RESEtD
DIENB.D

>-----------,
>-----,

TCS >-...------1

C
XO-I

~==~~..L>..JC==========~====:::;===~X

DINO-7 L

MUlTIPLiER
CORE
U>

PO-17

ClK

a:
w

~
;:;:
LATCHES

C

I

iiEiffi

DCMl

DCM1.D

DCMO

DCMO.D

iiffiT
iiiiNi
CIENB

iiEffiii
iiiiiii.ii
CiENB.ii

ADRO

ADRO.D

ADRI

ADR1.D

ADR2

ADR2.D

rnm

iiiAsf.ii

SIGN EXTENSION

ACC.DO-25

18-25

ClK

fAAif.ij
ClK
ERASE
CEll.
CEllO

ADRO
ADR1
ADR2

DECODER

•••

CEllI

CEll 7

CEll •• D

ADUTO-25

FIGURE 1.

HSP43881 FILTER CELL

3-63

HSP43881
o

--ADBD.D- ADR2.D

1

The SUMO-25 output bus is controlled by the SENBH and
SENBL signals. A low on SENBL enables bits SUMO-15. A
low on SENBH enables bits SUM16-25. Thus all 26 bits
can be output simultaneously if the external system has a
26-bit or larger bus. If the external system bus is only 16
bits, the bits can be enabled in two groups of 16 and 1_ 0 bits
(sign extended).

6 7

~

DF Arithmetic
Both data samples and coefficients can be represented as either unsigned or two's complement numbers. The TCS
Bnd TCCI inputs determine the type of arithmetic
representation. Internally all values are represented by a
9-bit two's complement number. The value of the additional
ninth bit depends on the arithmetic representation selected.
For two's complement arithmetic, the sign is extended into
the ninth bit. For unsigned arithmetic, bit 9 is O.
16 MSB'S SHIFTED
6 BfTS TO RIGHT
(BfTS 0 - 17)

The multiplier output is 18 bits and the accumulator is 26
bits. The accumulator width determines the maximum
possible number of terms in the sum of products without
overflow. The maximum number of terms depends ,also on
the number system and the distribution of the coefficient
and data values. Then maximum numbers of terms in the
sum products are:

NUMBER SYSTEM
CLK

FIGURE 2.

SUMQ-25

HSP43881 OF OUTPUT STAGE

The 26 least significant bits (LSBs) from either a cell
_accumulator or the output buffer are output on the
SUMO-25 bus. The output mux determines whether the cell
accumulator selected by ADRO-2 or the output buffer is
output to the bus. This mux is controlled by the SHADD
input signal. Control is based on the state of the SHADD
during two successive clocks; in other words, the output
mux selection contains memory. If SHADD is low during a
clock cycle and was low during the previous clock, the
output mux selects the contents of the filter cell
accumulator addressed by ADRO-2. Otherwise the output
mux selects the contents of the output buffer.
If the ADRO-2 lines remain at the same address for more
than one clock, the output at SUMO-25 will not change to
reflect any subsequent accumulator updates in the
_addressed cell. Only the result available during the first
clock when ADRO-2 selects the cell will be output. This
does not hinder normal FIR operation since the ADRO-2
lines are changed sequentially. This feature facilitates the
interface with slow memories where the output is required
to be fixed for more than one clock.

MAX #
OFTERMS

Two unsigned vectors

1032

Two two's complement
• Two positive vectors
• Negative vectors
• One positive and one negative vector

2080
2047
2064

One unsigned and one two's complement
vector:
• Positive two's complement vector
• Negative two's complement vector

1036
1028

For practical FIR filters, the coefficients are never all near
maximum value, so even larger vectors are possible in
practice.

Basic FIR Operation
A simple, 30MHz 8-tap filter example serves to illustrate
more clearly the operation of the DF. The sequence table
(Table 1) shows the results of the multiply accumulate in
each cell after each clock. The coefficient sequence, Cn,
enters the DF on the left and moves from left to right through
the cells. The data sample sequence, Xn, enters the DF from
the top, with each cell receiving the same sample
simultaneously. Each cell accumulates the sum of products
for one output point. Eight sums of products are calculated
simultaneously, but staggered in time so that a new output
is available every system clock.

3-64

HSP43881
TABLE 1.

HSP43881 '30MHz, 8 TAP FIR FILTER SEQUENCE

CO· .. Ca, C7, Co ... Ca, C7
CLK

CELLO

0
1

C7 XXO
+Ca xX1
+CSXX2
+C4 XX3
+C3 xX4
+C2 XXS

2
3
4
S
a
7
a
9
10
11
12
13
14
lS

CELL 1

CELL2

CELL 3

0

0
0

0
0
0

C7 xX 1
+Ca XX2
+CS XX3
+C4 xX4
C3 xX S
+C2 XXa

+C1 xXa
+COxX7
C7 XXa
+CaxXg
+Cs xX 10
+C4 XX 11
+C3 XX 12
+C2 xX 13

C7 XX2
+Ca xX3
+CSxX4
+C4 XXS
+C3 xXa
+C2 xX7

+C1 xX7
+CoxXa
C7 xX9
+Ca xX 10
+CSxX11
+C4 xX 12
+C3 xX 13
+C2 xX14
+C1 XX1S

+C1 xX14
+CO xX1S

- - . HSP43aa1

+C1 xXa
+COxXg
C7 xX 10
+Ca xXl1
+CSXX12
+C4 xX 13
+C3 xX 14
+C2 XX 15

~

CELL4

CELLS

... Y1S, Y14 ... Ya, Y7
CELL 6

CELL 7

SUM/CLR

-

-

C7 XX3
+Ca xX4
+CSxXS
+C4 XXa
+C3 xX7

C7 xX4
+CaxXs
+CsxXa
+C4 xX7

+C2 XXa
+C1 xXg
+CO XX 10
C7 xX 11
+Ca XX12
+CS xX 13

+C3 xXa
+C2 xX9
+C1 xX10
+Cox X11
C7 XX 12
+Ca xX 13

+C4 xX 14
+C3 xX15

+Cs x X14
+C4 xX15

C7 xX S
+CaxXa
+CSXX7
+C4 XXa
+C3 xX 9
+C2 xX 10
+C1 XX11
+COXX12
C7 xX13
+Ca XX 14
+C5 XX15

C7 XXa
+Ca xX7
+CsxXa
+C4 xX9
+C3 xX 10
+C2 xX 11
+C1 xX12
+CO xX 13
+C7 xX 14
+Ca XX15

-

Cell o (Y7)
Cell 1 (ya)
Cell 2 (yg)

C7 XX7
+CaxXa
+CsxXg
+C4 x X10
+C3 XX 11
+C2 XX 12
+C1 xX13

Cell 3 (Y10)
Cell 4 (Y11)
CeIlS(Y12)
Cella (Y13)
Cell 7 (Y14)
Cell 0 (Y15)

+COxX14
C7 XX15

en
a:
w

:;
u::
C

SAMPLE
DATA IN

I

(X n )

30MHz
CLOCK

>-

>

3 BIT
COUNTER

Y2

Y1

+5V

Yo

I

I
, /8

~
A2

A1

AO

DQ-D7

8x8 COEFF.
RAMiROM

SYSTEM
RESET

,

ADR2 ADR1 ADRO VCC SHADD SENBH SENBL
DINQ- 7
SUMO· 25

r:

i5iENB

t--

TCS
HSP43881

/8

2a"

NC

TCCO

TCCI
CINO·7
CIENB DCM1 DCMO

r

1 1

ERASE

FIGURE 3.

~

CLK
~

r---,

I 1 1

- -RESET ERASE

r
I

COUTQ-7
VSS COENB

11

*-

HSP43881 30M Hz, 8 TAP FIR FILTER APPLICATION SCHEMATIC

3-65

8"

,

NC

HSP43881
Detailed operation of the DF to"perform a basic a-tap, a-bit
coefficient, a-bit data, 30MHz FIR filter is best understood
by observing the schematic (Figure 3) and timing diagram
(Figure 4). The Internal pipeline length of the DF is four (4)
clock cycles, corresponding to the register levels CREG (or
XREG), MREGO, MREG1, and TREG (Figures 1 and 2).
Ther.efore the delay ·from presentation of data and
coefficients at the DINO-7 and CINO-7 Inputs to a sum
appearing at the SUMO-25 output is:

The output sums, Yn, shown in the timing diagram are
derived from the sum-of-products equation:
Y(n) = C(O) x X(n) -+- C(l) x X(n-l) + C(2) x X(n-2) + C(3)
x X(n-3) + C(4) x X(n-4) + C(5) x X(n-5) + C(6) x X(n-6)
+ C(7) x X(n-7)

Extended FIR Filter Length
Filter lengths greater that eight taps can be created by
either cascading together multiple DF devices or "reusing"
a single device. Using multiple devices, an FIR filter of over
1000 taps can be constructed to operate at a 30MHz
sample rate. Using a single device clocked at 30M Hz, an
FIR filter of over 1000 taps" can be constructed to operate at
less than a 30MHz sample rate. Combinations of these two
techniques are also possible.

k+Td
where
k

= filter length
= 4, the internal pipeline delay of DF

Td

After the pipeline has filled, a new output sample is available
every clock. The delay to last· sample output from last
sample Input Is Td.

o

1

2

3

4

5

6

7

8

9

10 11

12 13 14 15 16

17 18 19

20

ClK

ERASE ~r-------~--~------------1-

_______________________

DINO-7
DIENI _______________________________________________________

IC71 C& I Csl C4 I C31 C21 c, ICo I C7 Ic&1 Cs I C41

CINO-7

C31 C21 c,

I Co I C71

c&1 C.

I

CIENi _______________________________________________________

ADRO-2

101,1213141.1&17101

I~I~I~I~I~I~I~I~I

SUMO-24
SHADDWV~A

ifrii[ ~A000WffiW00VA

iffiif~A
DCMO-l

1 1-1----------------------------------------"--------0

7

YN=IcK,XN-K
K

FIGURE 4.

=0

HSP43881 30MHz, 8 TAP FIR FILTER TIMING

SAMPLE

MfA .N

Ir=D

(X,.I

D

3DMHz
CLOCK

Q

I I I T~

I

h

10111 MU.I ADD Vee 'HADD IEIiIN SEMIL

!r-

DINI-7

,......

iiiiii

' - TCI

--.£ I-

,---. 7 -

1111 COEFF.
AI RAM/ROM

eLK VI

AI

.. liT Y1
erR Y2

n

SYSTEM
RElET

fI---

T
FIGURE 5.

O2

AI

01-07

aUMO-U

DFO
TceD

' - TCCI

~

CINO-7

Ciiii DC.1

COUTl-7
DCMa

I I I T~

iiiiiT iiiiii va Ciiiiii

I 4·

:--l

ADlil ADRI ADRI Vee 'MADD liNIM IEIIL

t+

£

HSP43881

Cl.

..
-+-

DJ•• -1

IUMI-2"

~

TeeD

r-

DiEiii

reI

H$P43881

ClK

DF1

-- I---

TCCI

4- I---

CINO-7

Ciiiii

DCMl DC"

COUTI-1

iiUif iiiiii '.

~

COl••

I I•

HSP43881 3OMHz, 16 TAP FIR FILTER CASCADE APPLICATION SCHEMATIC.

3-66

-.
...
Ie

OUT

""I

HSP43881
Cascade Configuration
To design a filter length L>8. L/8 OFs are cascaded by
connecting the CQUTO-7 outputs of the (i)th OF to the
CINO-7 inputs of the (i+l)th OF. The OINO-7 inputs and
SUMO-25 outputs of all the OFs are also tied together. A
specific example of two cascaded OFs illustrates the
technique (Figure 5). Timing (Figure 6) is similar to the
simple 8-tap FIR. except the ERASE and SENBL/SENBH
TABLE 2.

X30'"

X9. X8. X22 ... Xl. Xo

Coefficient
Sequence co ... C14.015.0 ... O.. Co ... C14.C15
Input.
CLK

6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

30
31
32
33
34
35

CELLO

CELL 1

CELL 2

CELL 3

0
C15 XX1

o

0

C15 xX8
+C14 XX9
+C13 xX lO
+C12 x Xll

42

+C2 xX21
+C1 xX22
+CO XX 23

44

48

o
o
o
o

HSP43881l---+ ... o. Y3Ci ... Y23.0 ... O. Y22· .. Y15.0 ... 0

CELL 4

CELLS

CELL 6

C15 xX6
C15 xX7
+C14 xX8
+C13 xX9

o
o
o

o

o
o
o
o

+C4 XX14
+C3 xX15
+C2 xX 16
+C1 xX17
+CO xX 18

o

o

o
o
o
o
o
C15XX11

(I)

a:
w

!:i

u::
Q

+C12 xXlO
+C11 XX11
+C10 XX12
+C9 xX 13

+C6 xX 12

o

SUM/CLR

C15 XX5

+CS XX 13

o

CELL 7

C15 xX 4

+C9 xX 9
+C8 x XlO
+C7 XX 11

+C11 xX12
+C10 xX 13

+C5 xX 18
+C4 XX19
+C3 xX 20

.

+C12XX6
+C11 XX7
+ClO xX8

+CO xX 15

39
40
41

45
46
47

0
C15"X3
+C14 xX4
+C13xX5

+C3 xX 12
+C2 xX13
+C1 XX14

38

43

0

+C5 xX lO
+C4 xX 11

+C9 xX 14
+C8 xX 15
+C7 XX 16
+C6 xX 17

36
37

o

C15xX2

+C7 xX8
+C6 xX9

o
o
o

Using a singie OF. a filter of length L>8 can be constructed
by processing in L/8 passes as illustrated in the following
table (Table 2) for a l6-tap FIR. Each pass is composed of

---1

~

C15xXO
+C14XX1
+C13 xX 2
+C12 xX3
+C11 xX4
+ClO xX5
+C9 xX6
+C8 xX7

o
o
o
o

Single OF Configuration

HSP4388116-TAP FIR FILTER SEQUENCE USING A SINGLE OF

Data
Sequence
Input

signals must be enabled independently for the two OFs in
order to clear the correct accumulators and enable the
SUMO-25 output signals at the proper times.

COxX19

0
0
0
0
0
0
0
C15 xX 12

o

o

Co x X21
o

o
o
o

o
o
o
C15XX14

+C8 xX 14
+C7 XX 15
+C6 xX 16
+C5 XX 17
+C4 XX 18
+C3 xX 19
+C2 xX 20
+C1 x X21
+COXX22

I

CELLO(Y15)
CELL 1 (Y16)
CELL 2 (Y17)
CELL3(Y18)
CELL4(Y19)
CELL 5 (Y20)
CELL6(Y21)
CELL 7 (Y22)

0
0
0
0
0
0
0
C15 XX15
+C14 XX16
+C13 xX17
+C12 XX18
+Cl1 xX19
+Cl0 xX 20
+C9 xX21
+C8 xX22

o
o

3-67

+C7 XX 23
+C6 xX 24

CELL o(Y23)

+C5 XX25
+C4 xX 26

CELL 2 (Y25)
CELL 3 (Y26)

+C3 xX27

CELL 4 (Y27)

CELL 1 (Y24)

HSP43881
Tp= 7 + L cycles and computes eight output samples. In
pass I, the sample with indices 1*8 to i*8 +(L-l) enter the
OINO-7 Inputs. The c6efficients Co - CL - 1 enter 'the
CINO-7 inputs, followed by seven zeros. As these zeros are
entered, the result samples are output and the accumulators reset Initial filln.g of the pipeline Is not shown In this
sequence table. Alter outputs can be put through a FIFO to
even out the sample rate.

accomplished with external adders (at full speed) or with the
OF's shift-and-addmechanlsm contained in its output
stage (at reduced sPl*ld).

Decimatio'n/Resampling
The HSP43881 OF provides a mechanism for decimating
by factors of 2, 3, or 4. From the OF filter cell block diagr;lm
(Figure 1), note the three 0 registers and two multiplexers In
the coefficient path through the cell. These allow the coefficients to be delayed by 1, 2; or '3 clocks through the cell.
The sequence table (Table 3) for a decimate-by-two- fHter
illustrates the technique (internal cell pipelinlng Ignored for
Simplicity).

Extended Coefficient and
Data Sample Word Size
The sample and coefficient word size can be extended by
utilizing several OFs in parallel to get the maximum sample
rate or a single OF with resulting lower sample rates. The
technique is to compute partial products of 8x8 and
combine these partial products by shifting and adding to
obtain the final result The shifting and adding can be

ClK

•

1

!

:I

4

5

I

1

•

t

"

11

12

13

M

15

11

11

11

Detailed timing for a 30MHz Input sample rate, 15M!"Iz
output sample rate (I.e., declmate-by-two), 16-tap FIR filter,
Including plpelinlng, is shown In Figure 7. This filter requires
only a single HSP43881 OF.

"

2f

21

22 23

24 ZI

2.

II

2.

ZI

a8

31

32

33 14

H

31

J7

31 It

41

OflMAl<-ILJ~~==================================J===============~============~======:::
ERiii' _
DIIII->

OFt

IXo I x, I x,l x,l x. lis I x,l x,l XI I X,I X,ol X,,1 XIZI x"l X,,1 x..1X"I x"IX"lx"lx"lx" IX"'X.. IX"lx"IX,"II,,II.. ,I.. IX3I113IIX.,IXull.. ,I,,113I11.,1

m.M--'~

CIIII-'

____________________________________________________________________________
ICISIC" IC"IC"ICIIIC,.IC, ICI I C,I CI' c, 'c" c" c" c" c"clSlc"lc",c"lclI,c", C, IC. IC, Ic. 'c, 'c. I c. 'c, 'c, ,CIIC15,C",C"lclZ ICu,c,ol

..... --,~---------------------------------------------------------------------------,1"I'I"'15,1"I'I""'1'1 5 11I',I""j"

ADRI-!

OF. SUMO-ZS
DF1 SUMO-IS

:::

::::~ =Wb.===?="z=w.===u==&=,,=,============~;;;;;;;E~~~~~~5;;;;
OCMI-' 'I

1 - ,- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

I.e.

YH ..
I XN· •
• ·1

FIGURE 6.

HSP4388118-TAP 30M Hz FIR FILTER TIMING USING TWO CASCADED HSP43881a

3-68

HSP43881
TABLE 3.

HSP43881 l6-TAP DECIMATE-BY-TWO FIR FILTER SEQUENCE; 30MHz IN, l5MHz OUT
Data
Sequence
Input

Coefficient
Sequence ... C15. Co· .. C13. C14. C15
Input

1

--..J HSP43881 ~ ... Y19.-. Y17.-. Y15

CLK

CELLO

CELL 1

CELL 2

CELL 3

CELL 4

CELLS

CELL 6

CELL 7

SUM/CLR

6
7
8
9
10
11
12
13
14

C15 XXO
+C14 XX1
+C13 xX2
+C12 XX3
+C11 XX4
+ClO xX5
+C9 xX6
+C8 xX7

0
0
C15 XX 2

0
0
0
0
C15 XX4

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

-

C15 XX 6

0
0

0

0
0
0
0

0
0
0
0

0
0

0
0

C15 XX 12

0
0

+C7 XX8
+C6 XX9
+C5 XX 10
+C4 xX 11
+C3 xX12

15
16
17
18
19
20
21
22
23
24
25
_26
27
28
29
30
31

0
0
0

C15 XX8

C15 xX lO

+C2 xX13
+C1 XX14
+COxX15
C15 xX 16
+C14 XX17
+C13 xX 18
+C12 XX19
+C11 xX20
+C10 xX 21
+C9 xX 22
+Ca xX 23
+C7 XX24

33
34

-

-

-

-

C15 XX 14
+C14 XX 15
+C13 xX 16
+C12 xX 17
+C11 xX18
+ClO xX 19
+C9 xX 20
+Ca xX 21
+C7 xX 22
+C6 xX 23

CELLO(y15)

-

36
37

1 1 1 1 l
1

eLK

2

3

..

S

I

1

8'

9

10

11

14

15

CELL 2 (Y19)

C

CELL3(Y21)

_ CELL 4 (Y23)

CELL 5 (Y25)

CELL 6 (Y27)

CELL 7 (Y29)

CELL 8 (Y31)

1 1 1 1
11

17

18

19 20

Z1

22

23

24

25 2&

27

28 29

30

32

33

1

12

13

IX10

IX111 x121 x'3P:141 x'51 1161 X171 X111 x 19 I1201 Xzt IX22lx231x241 X25Ix28lx27lx28Ix2!dx~o Ix3I1 x321 1331 x3 .. 1136 1X361 X371

:f1

34

35

36

37

31

39

40

ERASE

I Ie I x, I X2 I X3 I X.. 1Xs I x, I Xl I x. I X,

DINt-1

DIENI ---.L________________________________________________

CIN.·,
elENa

_______________________________________

I C"I c" I C"I C,,1 cnl c,,1 c, I c, I c, I c, I c, I c. I c, I c, I c, I c. I C,.I c" I cill c,,1 cnl c,,1 c, I c;-I c, I c. I c, I c. I c, I c, I c, I c. I C,.lc" I c,,1 c,,1 cnlc" I

---,L-_________________________________________________________________________________________

ADRO-2

•

I

Iv,,1

SUMO-25

DCM'-'

~

I,

,

I

Iv,,1

,

I ,

1>,,1

I

Iv~1

•

I

Iv,,1

,

f • I ,

Iv,,1

Iv,,1

I

Iv,,1

•

I

Iv,,1

,

I

Iv,,1

~I----------------------------------------------------------------------------------------+

FIGURE 7.

HSP43881 l6-TAP DECIMATE-BY-TWO FIR FILTER TIMING; 30M Hz IN, l5MHz OUT

3-69

ffii
!:i
u:::

-

+C3 xX 28
+C1 xX28
+C2 XX29
+CO xX 29
+C1 xX30
C15 XX30
+CO xX 31 +C14 XX 31 +C14 XX31 +C14 XX31 +C14 XX31 +C14 XX31 +C14 xX31 +C14 XX31

35

.,.

-

CELL 1 (Y17)

+C5 xX 24
+C4 XX25
+C3 xX 26
+C2 xX 27

+C6 xX 25
+C5 xX 26
+C4 XX27

32

-

I

Specifications HSP43881
Absolute Maximum Ratings
Supply Voltage •••••••••••.•••••••••••••••••••••••••••••••.••••••••.••••..•••••••••••••••••••••..•••••.••••••••. +8.0V
Input. Output Voltage ••••••.••••••••••••••••••••••••••••.••••••.•••••••••..•••••••••••••••••••• GND -0.5V to VCC +0.5V
Storage Temperature ••••••••• , •.•••••••...•• " •••.•..••••.•.•••.•.••.•••••.••••....•••.•••.•••••• " •• -650 C to +1500C
ESD ••••••••••••••••••••••••••••••••••.••••••••.•....•••••.••••••••.••.••••.•..•.••.•••....•.....•........••• Class1
Maximum Package Power Dissipation at 700 C ••••••••• , •.•.• , ••••••••.•• , • " •••••••••• " •.••.•• 2.4W (PLCC). 2.88W (PQA)
0jc ••••.•••..•.•••••••••••••••.••••••.•••••••••••••••..•••••••••••••• , •••••••••••••• 11.1 0 CIW(PLCC).7,780 CIW(PGA)
0ja ................................................................................ 33.7OCIW (PLCC). 34.66o CIW (PGA)
Gate Count .................................................................................................... 17763
Junction Temp~rature ...................................................................... 1500 C (PLCC). 1750 C (PGA)
Lead Temperature (Soldering 10s) ............................................................................... 3000C
CAUTI9N: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damagp to the device. This is a stress only rating
and operation of the device at these or any other conditIons above those indicated in the operational sections of this specification ;8 not implied.

Operating Conditions
Operating Voltage Range ...................................................................................... 5V ±5%
Operating Temperature Range ............................................................................ OoC to + 700 C

D.C. Electrical Specifications
SYMBOL
ICCOp

PARAMETER
Power Supply 'Current

MIN

MAX

UNITS

-

160

mA

VCC=Max
CLKFrequency 20MHz
Note 1. Note 3

TEST CONDITIONS

-

500

IlA

Vce = Max. Note 3

II

Input Leakage Current

-10

10

IlA

VCC = Max. Input = OV orVCC

10

Output Leakage Current

-10

10

"A

VCC = Max. Input = OV orVCC

VIH

Logical One Input Voltage

2.0

-

V

VCC=Max

VIL

Logical Zero Input Voltage

0.8

V

VCC=Min

2.6

-

V

IOH = -4001lA. VCC = Min

ICCSB

Standby Power Supply Current

VOH

Logical One Output Voltage

VOL

Logical Zero Output Voltage

VIHC

Clock Input High

VILC

Clock Input Low

CIN

Input Capacitance

Cour

PLCC
PGA

Output Capacitance PLCC
PGA

-

0.4

V

10L = 2mA. VCC = Min

VCC-0.8

-

V

Vcc=Max

-

0.8

V

VCC=Min

-

10
15

pF
pF

10
15

pF
pF

CLK Frequency 1 MHz
All measurements referenced
toGND
TA = +250 C, Note 2

-

NOTES:
1. Operating supply current is proportional to frequency. Typical rating is
8mNMHz.
2. Controlled via design or process parameters and nol directly tested. Cha....
ecterized upon initial design and after major process and/or design
changes.
3. Output load per test load circuit and CL = 40pF.

3-70

Specifications HSP43881
A.C. Electrical Specifications

vcc = 5V ±5%, TA = ooc to +700 C
-20 (20MHz)

SYMBOL

PARAMETER

-25 (25.6MHz)

-30 (30MHz)

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

39

33

-

ns

0

-

TCp

Clock Period

50

TCl

Clock low

20

TCH

Clock High

20

TIS

Input Setup

16

TIH

Input Hold

0

-

TODC

ClK to Coefficient
Output Delay

-

24

-

TOED

Output Enable Delay

20

TODD

Output Disable Delay

-

TODS

ClKtoSUM
Output Delay

-

27

-

TOR

Output Rise

TOF

Output Fall

-

16
16
14

20

-

6
6

13

TEST
CONDITIONS

ns

13

-

ns

0

-

ns

20

-

18

ns

15

-

15

ns

15

ns

21

ns

-

6

ns

Note 1

6

ns

Note 1

15
25
6
6

13

ns

Note 1

...

NOTE:
1. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.

IX:

w

!:i

u::

...

CI
I

Test Load Circuit
r---------------

Sl
DUT~

I
I
I
I

I
I
I

,i
,
,
,

'CLt
,

I

1.5V

*INCWDES STRAY AND
JIG CAPACITANCE
, ____

EQUIVALENT~IRCUrr _ _ _ _

SwHch 51 Open for ICCSB and ICCOp Tests

3-71

i
I

J

HSP43881
Waveforms

or--""-------- VCC· 0.4V

INPUT'

0.011

CLK

3.0V----.......,

O.ov-----'-l
• Input includes: DINO-7, CINO-7, DIENB, CIENB, ERASE,
RESET, DCMO-1, AD RO-2, TCS, TCCI, SHADD

CLOCK AC PARAMETERS

,,~-----

5V
CLK 2 . ; (
SUMO - 25

INPUT SETUP AND HOLD

~.-:::j_...;...--. r=l.~5VODC' TODS

'lll[V

COUTO-7
~
TCCO----'

O.~

--TO-R-~-

• SUMo-25, COuro-7, TCCO are assumed nol to be in
high-impedance state

SUMO-25, COUTO-7, TCCO OUTPUT DELAYS

OUTPUT RISE AND FALL TIMES

SENBl
SENBH---,
1.5V
COENB

3.0V---,
INPUT
O.OV---"

TOED
SUMO -25
COUTO. 7 _ _ _ _ _~ 1.7V
TCCO
HIGH
j\.1.;.;."'3V-'-_ _ _ _ _ _..J
HIGH
IMPEDANCE
IMPEDANCE

AC. Testing: Inputs are driven at 3.0V for logic "1" and O.OV for logiC "0"'.
Input and output timing measurements are made at 1.5V for both a logic "1"
and "0". ClK is driven at VCC -0.4 and OV and measured at 2.5V. All inputs
driven at 1VIns

OUTPUT ENABLE, DISABLE TIMING

A.C. TESTING INPUT, OUTPUT WAVEFORM

3-72

mHARRIS

HSP43881/883
Digital Filter

May 1991

Features

Description

• This Circuit is Processed in Accordance to Mil-Std883C and is Fully Conformant Under the Provisions
of Paragraph 1.2.1.

The HSP43881/883 is a video speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells
cascaded internally and a shift and add output stage, all in a
single integrated circuit. Each filter cell contains a 8x8 bit
multiplier, three decimation registers and a 26-bit
accumulator. The output stage contains an additional 26-bit
accumulator which can add the contents of any filter cell
accumulator to the output stage accumulator shifted right
by 8 bits. The HSP43881/883 has a maximum sample rate
of 25.6MHz. The effective multiply accumulate (mac) rate is
204M Hz. The HSP43881/883 DF can be configured to
process expanded coefficient and word sizes. MultipleDFs
can be cascaded for larger filter lengths without degrading
the sample rate or a single DF can process larger filter
lengths at less than 25.6MHz with multiple passes. The
architecture permits processing filter lengths of over 1000
taps with the guarantee of no overflows. In practice, most
filter coefficients are less than 1.0, making even larger filter
lengths possible. The DF provides for 8-bit unsigned or
two's complement arithmetic, independently selectable for
coeffiCients, and signal data.

• 0 to 25.6MHz Sample Rate
• Eight Filter Cells
• 8-Bit Coefficients and Signal Data
• Low Power CMOS Operation
~
~

ICCSB 500/JA Maximum
ICCOp 1601JA Maximum @ 20MHz

• 26-Bit Accumulator Per Stage
• Filter Lengths Up to 1032 Taps
• Shift and Add Output Stage for Combining Filter
Outputs
• Expandable Coefficient Size, Data Size and Filter
Length
• Decimation by 2, 3 or 4

Applications
• 1-0 and 2-D FIR Filters

Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
of 1/2, 1/3 or 1/4 the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and NxN spatial correlations/convolu·
tions for image processing applications.

• Radar/Sonar
• Digital Video and Audio
• Adaptive Filters
• Echo Cancellation
• Correlation/Convolution
• Complex Multiply-Add
• Butterfly Computation
• Matrix Multiplication
• Sample Rate Converters

Block Diagram
Vee

Vss

Ir

DIENB

DIND- DIN7

TCS

c'ENB)~5~~~:::t:;:E:t~:;:E::~;:t:::~;':E:::~~::~~;1::~~J

DCMO-1

ERASE

TCOO

COUTO COUT().7
RESET

MR~~5~~~r---1--+--~~+---~~t----4~r---~~----~-+--~

RESET
C~~~

S~DD»

:~::~,

__

~

COENB

-+I

______________________

________________________+I

~/
SUMJ-25

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright @ Harris Corporation 1991

3-73

File Number

2449.1

rn

a:
w

!:i
u::
C

I

HSP43881/883

Pinouts
85 PIN GRID ARRAY (PGA)

COENi

Vee

Vee

CDUTY

Tceo

e0UT5

COUTO

Vss

e

ALION
PIN

RESEr

--

DI...

DINT

TCS

DINa

DIN1

""'II'

DIM2

DIN5

D...

DINO

11

Vee

Vos

elNo

CI. .

Tea

CIN7

aS3A-ISP43881
P4388101.Gf!M

10

10

elNO

0

DCN1

0

0

0

iENiH SUNM

0

C.NS

Vee

0
0

v••

0
V• •

0

SUN1.

0

0

v••

0

.,

." "i .," II
iii

!II

:I

IiQ 1

:I

:I

til

II)

>

:I

N

:I

0

.," >=
:I

0

..

" lE lE ~ lE
"""" " "

~ i

N

>

WI

... ..

>

lE

"

Note: An overbar on a signal name represents an active LOW signal.

3-74·

0

Vee

0
CONO

0

COUT7 TCCO

eOENB

0

SUMS

elN2

8UM21

:I

0

SUMO

PINS UP

eOUTS

.. .. . .
." "" " g .." .," .,"i

SUN'

BOTTOM VIEW

COUT7

SUMtS

0

HSP43881

eOJ(

SUM23

Vss

0

0

0

0

SUMS

SUM7

COUT4

0

0

SUM11

0

SUM22

SUM17

0

0

0
.,< § ~ ., S S 5 S
" " 8 ~ 8 8 8 " ~"

51 !S

0

0

Vss

SUN1S SUM'. SUM10

84 LEAD CERAMIC QUAD FLATPACK PACKAGE

~

0

SUM13

SUM.

COUTO SHADD

0
0

0

Vee

SUM20 ,SUN,7 SUN1.

0

DeMO

CDUTS eDUTO

Vee

Vee

0

0

0
0

0

0

AD...

CDUn

coun

0
Vso

0

0

AD. .

0

81,1MIII

ADAI

G

0

SUM23 8UN22 SUMI, SUM18 SUM14

0

elENS

0

DINa

0

0

su .. t

0

SUMe

0

v••

0

SUN4

0

SUMII

0

V••

0

iiEiiiii.

0
Vce

0

0

CINS

elNS

0

0

el. .

e"7

CINe

0

0

0

Vee

V••

Tcel

Specifications HSP43881/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ••.•••••••....••••.......••••..••.••.•.. +8.0V
Input, Output Voltage Applied ..•.•.•.• , GND-0.5V to VCC+0.5V
Storage Temperature Range ••••••.•••••••••• -650C to +1500 C
Junction Temperature •••....•••.•.•••••••.••.•.•.•••• +175 0 C
Lead Temperature (Soldering, Ten Seconds) .••.......•• +3000 C
ESD Classification ••.••.•..•••••••.•.•...••••.•....... Class 1

Thermal Resistance
Sja
Sjc
Ceramic PGA Package ...•.••••••.. 34.660 C/W 7.78 0 C/W
Maximum Package Power Dissipation at +125 0 C
Ceramic PGA Package .....•••......•.•....•...••• 1.44 Watt
Gate Count ••••...••••.•..•.•••..•...••.•••..... 17762 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to tbe device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range •...•.••...•.••••••.... +4.5V to +5.5V
Operating Temperature Range •...••••••••.•• -550C to +1250 C
TABLE 1. HSP43881/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Devices Guaranteed and 100% Tested

PARAMETER

SYMBOL

CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

2.2

-

V

Logical One Input
Voltage

VIH

VCC=5.5V

1,2,3

-550 C.:<;TA':<; +1250 C

logical Zero Input
Voltage

VIL

VCC=4.5V

1,2,3

-55°C ~TA~ +1250 C

-

0.8

V

Output HIG H Voltage

VOH

10H = -400flA
VCC = 4.5V (Note 1)

1,2,3

-550C.:<; TA:$; +1250 C

2.6

-

V

Output LOW Voltage

VOL

IOL=+2.0mA
VCC = 4.5V(Note 1)

1,2,3

-550 C.:<;TA.:<;+1250C

-

0.4

V

VIN = VCC or GND
VCC=5.5V

1,2,3

-550C~TA':<;+1250C

-10

+10

I'A

VOUT = VCC or GND
VCC=5.5V

1,2,3

-550C':<;TA~+1250C

-10

+10

flA

Input Leakage Current

II

!::i

10

Clock Input High

VIHC

VCC=5.5V

1,2,3

-550 C.:<;TA.:<;+1250C VCC-0.8

-

V

VILC

VCC=4.5V

1,2,3

-550C':<;TA~

+125 0 C

-

0.8

V

Standby Power Supply
Current

ICCSB

VIN = VCC or GND
VCC=5.5V,
Outputs Open

1,2,3

-550 C.:<;TA':<; +125 0 C

-

500

I'A

Operating Power
Supply Current

ICCOp

f=20.0MHz
VCC = 5.5V (Note 2)

1,2,3

-550C':<;TA~+1250C

-

160.0

mA

7,8

-550C .:<;TA~ +125 0 C

-

-

Functional Test

FT

(Note 3)

NOTES:
1. Interchanging

u::

C

I

Output Leakage
Current

Clock Input Low

fI)

a:
w

of force and sense conditions is permitted.

2. Operating Supply Current is proportional to frequency, typical rating is
8.0mA/MHz.

3. Tested as follows: f = 1MHz, VIH = 2.6, VIL = 0.4, VOH ~ 1.5V,
VOL S. 1.5V, VIHC VCC -0.4V, and VILC 0.4V.

3-75

=

=

Sp8cifications HSP43881/883
TABLE 2. HSP43881/883 A.C.ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

GROUP A
SYMBOL CONDITIONS SUBGROUPS

PARAMETER

-20 (20M Hz)

25 (25.6MHz)

TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

50

-

39

-

ns

16
16

-

ns

17

-

ns

0

-

ns

-

20

ns

-

1.5

ns

25

ns

Clock Period

TCp

Note 1

9,10,11

-550 CSTA·S.+1250C

Clock Low

TCL

Note 1

9,10,11

-550C.s:TA.s:+1250C

20

Clock High

TCH

Note 1

9,10,11

-550C5 TA5+1250C

20

TIS

Note 1

9,10,11

-55°C 5TA.s: +1250 C

20

-

9,10,11

-55°C 5 TA.s: +1250 C

Input Setup

TIH

Note 1

0

-

CLK to Coefficient
Output Delay

TODC

Note 1

9,10,11

-550C.s:TA~+1.250C

-

24

Output Enable Delay

TOED

Note 1

9,10,11

-550 C5TA.s:+1250C

-

20

CLKtoSUM
Output Delay

TODS

Note 1

9,10,11

-55°C .s:TA.s: +1250 C

-

31

Input Hold

..

ns

'.'

NOTE: 1. Loading is as specified in .the test load circuit with CL = 4OpF.

TABLE 3. HSP43881/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
-20
PARAMETER
Input Capacitance

-25

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

CIN

VCC=Open, f=1 MHz
All measurements
are referenced to
deviceGND.

1

TA=+250C

-

15

-

15

pF

1

TA=+250C

-

15

15

pF

1,2

-550 C.s:TA.s:+1250C

-

20

15

ns

6

ns

-

7

-

6

ns

Output Capacitance

COUT

Output Disable Delay

TODD

Output Rise Time

TOR'

1,2

-550C5TA <+1250 C

Output Fall Time

TOF

1,2

-55 0 C5TA5+1250C

7

NOTES:
1. The parameters listed in Table 3 are controlled via design or process
parameters and are not directly tested. These parameters are character..
ized uPQn initial design and after major process and/or design changes.
2.. Loading is as specified in the te~tload eireuR, CL = 4OpF.

TABLE 4. APPLICABLE SUBGROUPS
METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

-

CONFORMANCE GROUPS

PDA

100%

1

Final Test

100%

2,3,8A,8B, 10, 11

-

1,2,3, 7,8A, 8B,9, 10, 11

Samples/5OD5

1,7,9

Group A
GroupsC&D

3-76

HSP43881/883
Burn-In Circuit

8UM2!

COUT8

SUM22

eoUT7
Vss

VCC
8UM21

TCCO

COiNi
Vee

EFiASE

ReSeT

HSP43881j883

DIENS

TOP VIEW

TCS
DIN7

DiNe
DIN6

01. .
DIN3

0lN2
DIN1

SUM11

DINO
CIENa

Teel

.,.

Vee

....a:

!:i
u:::
CI

.-I
OFP
LEAD

PIN
NAME

BURN-IN
SIGNAL

OFP
LEAD

PIN
NAME

BURN-IN
SIGNAL

OFP
LEAD

PIN
NAME

BURN-IN
SIGNAL

OFP
LEAD

PIN
NAME

BURN-IN
SIGNAL

1

SUM23

Vee/2

22

SUM6

Vecl2

43

Vee

Vee

64

Vee

2

SUM22

Vecl 2

23

VSS

GND

44

Teel

F9

65

eOUT5

Vecl2

3

Vee

Vee

24

SUM5

Vce/2

45

elENB

FlO

66

eOUT4

Vecl2

Vee

4

SUM21

Vect2

25

SUM4

VCcl2

46

DINO

FO

67

eOUT3

Vee/2

5

SUM20

Vecl2

26

Vee

Vee

47

DINl

Fl

66

eOUT2

Vee/2

6

SUM19

Vce/2

27

SUM3

Vecl2

48

DIN2

F2

69

VSS

GND

7

SUM18

Vee/2

28

SUM2

Vecl2

49

DIN3

F3

70

eOUTl

Vee/2

8

VSS

GND

29

SUMl

Vccl2

50

DIN4

F4

71

COUTO

Vee/2

9

SUM17

Vee/2

30

SUMO

Vecl2

51

DIN5

F5

72'

SHADD

F9

10

SUM18

Vee/2

31

VSS

GND

52

DIN6

F6

73

CLK

FO

11

vee

Vee

32

SENBL

FlO

53

DIN7

F8

74

ADDR2

F2

12

SUM15

Vee/2

33

elNO

FO

54

TeS

F7

75

DeMO

F5

13

SUM14

Vee/2

34

CINl

F1

55

DIENB

FlO

76

VSS

GND

14

SUM13

Vee/2

35

Vee

Vce

56

RESET

Fll

77

ADDRl

F1

15

SUM12

Vee/2

36

elN2

F2

57

ERASE

FlO

78

ADDRO

FO

18

VSS

GND

37

elN3

F3

58

Vee

Vce

79

Vce

Vce

17

SUMll

vecl 2

38

elN4

F4

59

eOENB

FlO

80

SENBH

FlO

18

SUM10

Vccl2

39

elN5

F5

80

Tceo

vecl2

81

SUM25

Vect2

19

SUM9

Vect2

40

VSS

GND

61

VSS

GND

82

DeM1

F6

20

SUM8

Vee/2

41

CIN6

F6

62

eOUT7

Vecl2

83

SUM24

Vee/2

21

SUM7

Vect2

42

CIN7

F7

63

eOUT6

Vee/2

84

VSS

GND

NOTES: 1. Vee/2 (2.7V ±10%) used for outputs only.

2. 471<0 (:1:20%) resis10r connected to all pins except
Vee snd GND.
3. Vee - 5.5 :l:0.5V.

4. 0.1 ~F (min) cspacRor between Vee and GND per pooRion.
5. FO = 100KHz :1:10%. Fl = FO/2, F2 = Fl/2 •••.•• Fl I = Fl012.
40% - 60% Duty Cycle.
6. Input voltage limits: VIL = 0.8V max. VIH = 4.5V :I: 10%

3-77

HSP43'881/883
Burn-In Circuit

HSP43881/883 PIN GRID ARRAY (PGA)

,

1

b

L

0

0

SENiii

0

J

0

0

0

0

0

V88

9UM24

0

0

Vee

0

V.S

8UMI.

0

Vee

0

0

0

Vsa

0

BUtoUS 8UM12 SUU10

0

8UM20

0

BUNlt3

•

0

0

HSP43881

0

0

BOTTOM VIEW

COUTO SHADD

0

0

SUMI

0

SUMO

PINS UP

0
COUT2

0

0

COUTIS

0

S

Vee

0

A

v••

PGA
PIN

PIN
NAME

BURN-IN
SIGNAL

PGA
PIN

0

0

au ...

aUMa

0

v••

0

0

COUTe

0
0

0

0

8UM2

0

0

Vsa

Veo

0

0
elNO

0

iiNii.

0

0

HSP/43881/4388102.GEM

vee

OINZ

0

0

ALIGN

0

OIENB

DINS

PIN

0
DIN"

0 .RAB.
0 DINI
0 0
0 Tea
0 RESET
0 0 0 0

COU17 TCCO

co....

SUM<

SUM3

OIN.

caUT3 OOUT4

e

8UMS

0

0eLK

S•

0

0

SUM11

SUM7

0

0 0
• coun
V

11

BUMS

DeMO

"sa

.

,

0

9UMt7 BUMI.

0

0

D

0

•

,7

AORO

ADR'
F

0, 0

8UM215

ADRt

G

•

0

Vee
H

•

BUM23 BUMD 8UM21 SUM1. 8UM14

DeNt

K

•

3

Vee

PIN
NAME

DIN7

DIN8

BURN-IN
SIGNAL

0

DIN2

CiENi

DIN3

DINO

PGA
PIN

0

0

0

0

CIN8

0lN3

0

0lN7

CIHI

0

0

TeCI

PIN
NAME

0

0lN4

0

Vee

V••

BURN-IN
SIGNAL

PGA
PIN

PIN
NAME

BURN-IN
SIGNAL

Al

VSS

GND

el

eOUT5

Veel2

F'10

Vee

Vee

K4

Vee

Vee

A2

eOENB

FlO

e2

eOUT6

Veel2

Fll

VSS

GND

K5

SUM19

Vee/2

A3

Vee

Vee

C3

ALIGN

Ne

G1

ADR2

F2

K6

VSS

OND

A4

hESET

Fl1

e5

DlENB

F10

G2

DeMO

F5

K7

SUM15

Vee/2

A5

DIN7

FS

e6

DIN5

F5

G3

elK

FO

KS

SUM12

Vee/2

A6

DlN6

F6

e7

DIN4

F4

G9

SUM1

Voe/2

K9

SUM10

Vee/2

A7

DIN3

F3

el0

elN5

F5

010

SUM3

Vee/2

K10

SUMS

Veel2

AS

DINO

FO

e11 , elN3

F3

011

SUM2

Vee/2

Kl1

SUM6

Veel2

A9

elNS/Teel

FS

01

eOUT3

Veel2

H1

ADR1

Fl

II

DeMl

F6

Al0

Vee

Vee

02

eOUT4

Veel2

H2

ADRO

FO

L2

SUM23

Vee/2

A11

VSS

GND

010

elN2

F2

H10

SUM5

Vee/2

L3

SUM22

Vee/2

B1

Vee

Vee

011

Vee

Vee

Hl1

SUM4

Veel 2

L4

SUM21

Veel 2

B2

eOUT7

Vee /2

E1

eOUT1

Vee /2

J1

Vee

Vee

l5

SUM1S

Vee/2

B3

eOUTS/TeeO Veel2

E2

VSS

GND

J2

SUM25

Veel2

l6

SUM14

Vee/2

B4

ERASE

F10

E3

eOUT2

Vee/ 2

J5

SUM20

Vee/2

l7

Vee

Vee

B5

DINS/TCS

F7

E9

elN1

F1

J6

SUM17

VoelZ

L8

SUM13

Veel2

B6

DIN1

Fl

E10

elNO

FO

J7

SUM16

Voe/2

L9

VSS

GND

B7

DIN2

F2

E11

SENBl

F10

Jl0

SUM7

Voel2

l10

SUM11

Veel2

l11

SUM9

Vee/2

BS

elENB

F10

F1

VSS

OND

J11

VSS

OND

B9

elN7 '

F7

F2

eOUTO

Veel2

Kl

SENBH

FlO

B10

elN6

F6

F3

SHADD

F9

K2

SUM24

Veel2

B11

elN4

F4

F9

SUMO

vee/2

K3

VSS

OND

NOTES:
1. VCC/2 (2.7V ± 10%) used for outputs ,only.
2. 47KO (±20%) resistor connected to all pins except Vcc and GND.
3. VCC

= 5.5V ± 0.5V.

.

4. 0.1 ~F (min) capacitor between VCC and GND per device.
5. FO = 100kHz ± 10%. Fl
Duty Cycle.
6. Input voltage Limits: VIL

3-78

= FO/2.F2 = F1/2 .... Fl1 = Fl0/2. 40% - 60%
= 0.8V Max. VIH = 4.5V ±10%

HSP43881/883
Die Characteristics
DIE DIMENSIONS:
328 x 283 x 19 ±1 mils

DIE ATTACH:
Material: Si-Au Eutectic Alloy (PGA)
Silver Glass (QFP)

METALLIZATION:
Type: Si-AI or Si-AI-Cu
Thickness: 8kA

WORST CASE CURRENT DENSITY: 1.2 x 105A/cm 2

GLASSIVATION:
Type: Nitrox
Thickness: 10kA

Metallization Mask Layout
HSP43881/883

.
..'"
N



::l

i0

C

on

.



0
0:

a:

C

C

" "
" "

0

II:

N

;c-

U

"~

!;

'c"



"~

~
u

!!>

::l
C
U

>

=

0

U

:I:

fA

::l

12::l

>

U

U

0-

0

"

0
0

0

>

SUM23

COUTS

SUM22

COUT7

Vee

Vss

SUM21

Teeo

SUM20

COENB

U)

SUM18

Vee
SUMi8

a:
w

!:i
u:::
C

V__

ERASE
RESET
DIENB

SUM17

TeS

SUMil

DIN7

Vee
DINS
SUMi5

DINS

SUM14

DIN4

SUM13

DIN3

DIN2

SUM12

V__

olNi

DINO
SUM11

elENa

SUM10

Teel

SUMD

Vee
SUMB
SELECT 891

SUM7

.
.'"
::l



.

0

.'" .l!! i. .'"
::l

::l

::l

::l



N

!;

u

.. .
z

ij

z

ij

.. . .
t•

on
!; ~
u

w



!;

u

~

!;

u

I

HSP43881/883
". Paokaging t

85 PIN CERAMIC·PIN·GRID ARRAY (PGA)

r - - - - - ::::

----j

LEAD MATERIAL: Type B
LEAD FINISH: Type C
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: . GoldfTin
Temperature: 3200C ± 100 C
. Method: Furnace Seal

.~

INTERNAL LEAD WIRE:
'Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 P-AC

84 PIN QUAD FLATPACK (QFP)

1.1&71~mm I'.
I
!!~I'
I
20
.360

..k.

.105

MAX

'.

.J

.050
BSC

.OIZ

r
M1N

= f D ·.
•

L.ll!!

1.167

····EJ

. .

.012

.

HI~

.~

.090
(lOTT[14

or

L

leAD)

.J!.Q!!A-L.,
.012

1lQ!E;

.&. INCREASE MAXINUN UNIT BY .OOY WHEN SOLDER
DIP OR TIN PLATE LEAD fiNISH APPliES.

LEAD MATERIAL: Type B
LEAD FINISH: Type C
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: GoldfTin
TemperatiJre: 3200c ± 100 C
Method: Furnace Braze
NOTE: All Dimensions are

e'

Dimensions are in inche.:

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic Wedge
COMPLIANT OUTLINE: 38510 C-G6

tMI-M-38510 Compliant Materials, Finishes, and Dimensions.

3-80

;II

HSP43481

HARRIS

Digital Filter

May 1991

Features

Description

• Four Filter Cells

The HSP43481 is a video-speed Digital Filter (OF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of four filter cells cascaded
internally and a shift-and-add output stage, all in a single
integrated circuit. Each filter cell contains an 8x8 multiplier,
three decimation registers and a 26 bit accumulator which
can add the contents of any filter cell accu mulator to the
output stage accumulator shifted right by eight bits. The
HSP43481 has a maximum sample rate of 30M Hz. The
effective multiply-accumulate (MAC) rate is 120M Hz.

• 0 to 30MHz Sample Rate
• 8 Bit Coefficients and Signal Data
• 26 Bit Accumulator per Stage
• Filter Lengths Up to 1032 Tap
• Shlft-And-Add Output Stage for Combining Filter
Outputs
• Expandable Coefficient Size, Data Size and Filter
Length

The HSP43481 can be configured to process expanded
coefficient and word sizes. Multiple devices can be
cascaded for larger filter lengths without degrading the
sample rate or a single device can process larger filter
lengths at less than 30M Hz with multiple passes. The architecture permits processing filter lengths of over 1000 taps
with the guarantee of no overflows. In practice, most filter
coefficients are less than 1 .0, making even larger filter
lengths possible. The HSP43481 provides for unsigned or
two's complement arithmetic, independently selectable for
coefficients and signal data.

• Decimation by 2, 3 or 4
• CMOS Power Dissipation Characteristics

Applications
• 1-0 and 2-D FIR Filters
• Radar/Sonar
• Digital Video and Audio
• Adaptive Filters
• Echo Cancellation
• Correlation/Convolution

Each OF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
of 1/2, 1/3 or 1/4 the input sample rate. These registers also
provide the capability to perform 2-D operations such as
NxN spatial correlations/convolutions for image processing
applications.

• Complex Multiply-Add
• Butterfly Computation
• Matrix Multiplication
• Sample Rate Converters

Block Diagram
DINO-7

TCS

TCCI C > - - - - - f
CINO-7

TCCD

L>--+-----i

CDUTa-7

iiffiT

CLKC>-~~~~-~--~-+---~+----"
ADRO-l

L--_<= COiNs

21

iiffiT
CLK
SHADD

L....:'f-----------f

C>----------~ol 0:r~~T

fiiBLc=>---~-------~

iTNiii

SUMO-25

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper Ie Handling Procedures.
Copyright @ Harris Corporation 1991

3-81

File Number

2759.1

U>

c:
w

::;
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C
1

HSP43481
Pinouts"
68 PIN CERAMIC PIN GRID ARRAY (PGA)
BOnOMVIEW

TCCO

CUt

COENB COOTe COUT4 C0UT2 SHADD

DCMl

J

iiiAiiE

H

iiEiiEi DENii

G

TC8

....
DIIS

D

D..,

C

DOlO

coun

COUTo

C0UT7

1?0UT5 COIJT8

68 PIN CERAMIC PIN GRID ARRAY (PGA)
TOP VIEW

ADDRl ADDAo SUMas

DCMD

SUMI5 ADDM ADDRl

cue

COU1O

court

COUT8 COUTS coim

iENiH

DCN1

SHADD

coun

C0UT4 COUllI

COEiii

TCCO

911MB SUM..

·cc

.....

SUM.. SU....

.-

RESEr

DIN7

TC8

SENBH SUM.. SU".

K

SUMII SU....

SUM.. SUM..

J

·cc

DIN7

BU".

au....

SUM17

BUMto

G

DCMo

SU"" SUMn

88 LEAD

PIN GRID AARAY
BOTTONIIIEW

D...

....
....

SUIUS &ulna

CiNii

ClN7

C_

CINa

c.,

SEta.

...

,88 LEAD

SUMt

auMa

SUMS

F

SUM1.

su....
y.

y ..

su.. ,.

•

su ....

sulua

SUM ..

D

SU".. SUM'.

SUMIO SUM"

C

SUUl1

SU"1O

SUU8

8UMa

PIN GRID AARAY
TOPIIIEW

D...

D",

Ciiii

,.

SUM1.

BUM7

,.

11

SU_

SUIM

....

8UMJ

CNI

CINI

CIN4

CINI

SUMi

SUMa

aull,

iEiiii:

c.,

CINII

CNi

CIN7

68 PIN PLASTIC LEADED CHIP CARRIER (PLCC)
TOP VIEW

~ IIIIII II

~ ~ ~

I

Ci

I !

l ~

"

I I~

D

I!

u
u

>

elN7

elNS
elNS
elN<
CINa

elNa

COUT'

CIN1

SHADD

SENSL

Cl...

auMO
DCM'

auM'
au ...

ADR1

au ....
au ...
au ....
SU"

au ...

;;

i
iil

:I

iil

3-82

D...

...

...,

....
TCCI

HSP43481
Pin Description
SYMBOL

PIN
NUMBER

Vee

61

+5V Power Supply Input

VSS

27

Power Supply Ground Input

ClK

19

I

The ClK input provides the DF system sample clock. The maximum clock frequency is
is30MHz.

DINo-7

64-68
1-3

I

These eight inputs are the data sample input bus. Eight bit data samples are synchronously
loaded through these pins to the X register of each filter cell simultaneously.
The DIENB signal enables loading, which is synchronous on the rising edge of the clock signal.

TCS

4

I

The TCS input determines the number system interpretation of the data Input samples
on pins DINO-7 as follows:

NAME AND FUNCTION

TYPE

TCS
TCS

=low -+ Unsigned Arithmetic
= High -+ Two's Complement Arithmetic

The TCS signal is synchronously loaded into the X register in the same way
as the DINO-7 inputs.
DIENB

5

I

A low on this enables the data sample input bus (DINO-7) to all the filter cells. A rising
edge olthe ClK signal occurring while DIENB is low will load the X register of
every filter cell with the 8 bit value present on DINO-7. A high on this input forces
all the bits of the data sample input bus to zero; a rising ClK edge when DIENB is high
will load the X register of every filter cell with all zeros. This signal is latched inside
the DF, delaying its effect by one clock internal to the DF. Therefore, it must be low
during the clock cycle immediately preceding presentation of the desired data on the
DINO-7 inputs. Detailed operation is shown in later timing diagrams.

CINO-7

53-60

I

These eight inpuls are used to input the 8 bit coefficients. The coefficients are synchronously
synchronously loaded into the C register of filter Cell 0 if a rising edge of ClK
occurs while elENB is low. The CIENB signal is delayed by one clock as discussed below.

TCCI

62

I

The TCCI input determines the number system interpretation of the coefficient
inputs on pins CINO-7 as follows: ...
TCCI
TCCI

=lOW -+ Unsigned Arithmetic
=HIGH -+ Two's Complement Arithmetic

The TCCI Signal is synchronously loaded into the C register in the same way as
the CINo-7 inputs.
CIENB

63

I

A low on this input enable the C register of every filter cell and the D registers (decimation)
of every filter cell according to the state olthe DCMO-1 inputs. A rising edge of
the ClK signal occurring while CIENB Is low will load the C register and appropriate
D registers with the coefficient data present at their inputs. This privides the mechanism
for shifting the coefficients from cell to cell through the device. A high on this input
freezes the contenls of the C register and the D registers, ignoring the ClK signal.
This signal is latched and delayed by one clock internal to the DF. Therefore, it must be
low during the clock cycle Immediately preceding presentation of the desired coefficient
on the CINO-7Inputs. Detailed operation is shown In the Timing Diagrams section.

COUTO-7

10-17

0

These eight three-state outputs are used to output the 8 bit coefficients from filter cell 7.
These outputs are enabled by the COENB signal low. These outputs may be tied to the CINO-7
inputs of the same 0 F to recirculate the coefficients, or they may be tied to the
CINo-71nputs of another OF to cascade DFs for longer filter lengths.

TCCO

9

0

The TCCO three-stale output determines the number system representation of the coefficients
output on COUTO-7. Ittracks the TCCI signal to this same OF. It should be tied to the TCCI
input of the next OF in a cascade of DFs for Increased filter lengths. This signal is enabled
byCOENB low.

3-83

....,

rr:
....

!:i

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Q

I

HSP43481
Pin Descriptions
SYMBOL

PIN
NUMBER

TYPE

COENB

8

I

A low on the COENB input enables the COUTQ-7 and the TCCO output A high on this input
places all these outputs In their high Impedance state.

DCMQ-1

20-21

I

These two Inputs determine the use of the internal decimation registers as follows:
DCM1
DCMO
Decimation Function

NAME FUNCTION

0
0
1
1

0
1
0
1

Decimation registers not u!ied .
Onll decimation register is used
Twodecimation registers are used
Three decimation registers are used

The coefficients p13SS from cell to cell at a rate determined by the nu';'ber of decimation
registers used. When no decjm-.,....-.......------,---------~-;......------.........---.:...,
OCMO.O'>----_-------'---------,
RESEtO>-----------~--------~------+_--~~----------~------~

CIENB.O >------~r_+_--_--_----~r_+_----~--------...,..--+----_,
TCCI

THREE-STATE BUFFERS
ON CEll 3 ONLY

-------1

>-1r----i

I
I

CIND-7~==~

I
I
TCtO

COUTO-7

RESEtO > - - - - - - - .
D,IENB.D >-------,.-,
TCS

>-r----.j
X REG

01NO-7

MUlTI-

~~=::::::L.A~c==========~====:::;:::=~~x
L

ClK

LATCHES
DCMl

C>---i

OCMe

L-~----T

mrr C>----"--q

DCM1.D
OCMD.D

DIENB.D
CIE'NB.D

AORO

L--;----'

AORO.O

ADRI

C>----i

AORtD

liim L>------li-

RESET.D >-~---------=----....--l

RESET.D

C>--c+,

CffiiI

CORE
PLiER

P<0.17>

ERAU.D

ClK >----------'

ERASE,D
ClK
ERASE

ADRD~.,
"

.
AORI

DECODER

CEllo
CEllO
CELL 1
CELL 2
CELL 3

CELlo.D

>------1

--:»_-----1

AOUT 0-25

FIGURE 1.

HSP43481 FILTER CELL

3-86

I
I
I
I
I

HSP43481

CEll RESULTS

o

1

2

3

lines are changed sequentially. This feature facilitates the
interface wtith slow memories where the output is required
to be fixed for more than one clock.
The SUMO-25 output bus is controlled by the SENBH and
SENBL signals. A low on SENBL enables bits SUMO-15. A
low on SENBH enables bits SUM16-25. Thus all 26 bits
can be output simultaneously if the external system has a
26 bit or larger bus. If the' external system bus is only 16
bits, the bits can be enabled in two groups of 16 and 9 bits
-(Sign extended).

DF Arithmetic
Both data samples and coefficients can be represented as
either unsigned or two's complement numbers. The TCS
and TCCI input signals determine the type of arithmetic
representation. Internally all values are represented by a 9
bit two's complement number. The value of the additional
ninth bit depends on arithmentic representation selected.
For two's complement arithmetic, the sign is extended into
the ninth bit. For unsigned arithmetic, bit 9 is O.

SHADD

ClK

FIGURE 2.

SUMO-25

HSP43481 OUTPUT STAGE

The 26 Least Significant Bits (LSBs) from either a cell accumulator or the output buffer are output on the SUMO-25
bus. The output mux determines whether the cell accumulator selected by ADRO-1 or the output buffer is output to the
bus. The mux is controlled by the SHADD input signal.
Control is based on the state of the SHADD during two
successive clocks; in other words, the output mux selection
contains memory. If SHADD is low during a clock cycle and
was low during the previous clock, the output mux selects
the contents of the filter cell accumulator addressed by
ADRO-1. Otherwise the output mux selects the contents of
the output buffer.
If the ADRO-1 lines remain at the same address for more
than one clock, the output at SUMO-25 will not change to
reflect any subsequent accumulator updates in the
addressed cell. Only the result available during the first
clock when ADRO-1 selects the cell will be output. This
does not hinder normal FIR operations since the ADRO-1

The multiplier output is 18 bits and the accumulator is 26
bits. The accumulator width determines the maximum
possible number of terms in the sum-of-products without
overflow. The maximum number of terms depends also on
the number system and the distribution of the coefficient
and data values. As a worst case assume the coefficients
and data samples are always at their absolute maximum
values.
Then the maximum numbers of terms in the sum products
are:
NUMBER SYSTEM

MAX #
OF TERMS

Two unsigned vectors

1032

Two two's complement vectors:
• Two positive vectors
• Two negative vectors
• One positive and'one negative vector

2080
2047
2064

One unsigned and one two's complement
vector:
• Positive two's complement vector
• Negative two's complement vector

1036
1028

For practical FIR filters, the coefficients are never all near
maximum value, so even larger vectors are possible in
practice.

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HSP43481
Basic FIR. Operation
A simple 30M Hz 4 tap fHter'example serves to illustrate
more,clearly the operation :of the OF. ,Table 1 'showslhe
results of the multiply accumulate·.!n each cell afte~ each'
·'cloek. The coefficient sequence,Cn, enters the DF on the
left and moves .from left to right through the cells. The data
sample sequence, Xn, enters the OF from.thetop, with each
·cel. recelvlng the same sample'slmultaneously. Each cell'
l'ABLE 1..

accumulates the sum-of-products for one output pOint.
Four sums-of-products are calculated simultaneously, but
staggered In time so that a new output Is available every
system clock.
Detailed operation of the DF to perform.a basic 4 tap, 8 bit
coefficient, 8 bit data, 30MHz FIR filter is best understood
by observing the'schematic (Figure 3) and timing diagram

25MHz, 4 TAP FIR FILTER SEQUENCE

DATA
SEQUENCE
INPUT
COEFFICIENT
SEQUENCE
INPUT

CLK

CELLO

CELL 1

CELL 2

. CELL 3

SUM/CLR

,

C3 x Xo
+C2 xX,

0

0
0

2
3
4
5

+C, XX2
+COxX3

0
0
0

-

C3 xX3
+C2 xX4
+C, xXs

CeIlO(Y3)
Cell, (Y4)

0

C3 xX,

C3x~

+C2 XXS
+CpxXS
-+COXX7

S
7
SAMPLE
DATA IN
(X..)
30MHz
CLOCK

C3 xX2
+C2 xX3
+C, xX4
<+-CoxXs
C3 xXS
+C2 xX7

' +C2 XX2
+C, xX3
+COxX4
C3 xX S
+C2 XX S
. +C, XX7

Cell 2 (yS)
CelI3(yS)
CeIlO(Y7)

+CoxXS
C3 xX7

RESET ~

2B1T

rp- ~

+5V

COUNTER

Y1

[J

Yo

+1

.r-

Lf!

I I

DINO-7

AD
DO-

TCCO

HSP4348I

COUTO-7

CINO-7

CiEiii

DCM1 DCMO

I I

MsiT iiiiSE

T

I

SYSTEM ,
RESET

VSS

Ciifrii

..

T

I

iiiiSE
30MHz, 4 TAP FIR FILTER APPUCATION SCHEMATIC

,

)

-+-

SUM
OUT

-

NC

TCS

T

FIGURE 3.

..

1
SENll

(Ynl

"- TCCI

n- ~

411 COEFF.
RAMJROM

1

SUMO-25

ClK
A1

I

'DIENI ADR1ADRO VCC SHADD SENIH

3-88

.!-- NC

HSP43487
(FIgure 4). The Internal pipeline length of the DF is four (4)
clock cycles, corresponding to the register levels CREG (or
XREG), MREGO, MREG1, and TREG (Figures 1 and 2).
Therefore, the delay from. 'presentation of data and coefficients at the DtNO-7 and CINO~7 inputs to a sum appearing
at the SUMO-25 output is:
k + Td where
k = filter length
Td

After the pipeline has filled, a new output sample is available
ellery clock. The delay to last sample output from last
sample input is Td.
The output sums, Y(n), shown in the timing diagram are
derived from the sum-of-products equation:
YIn)

~

C(O) x X(n)

+ C(l) x X(n-l) + C(2) x X(n-2) + C(3) x X(n-3)

= 4, the internal pipeline delay olDF
2

3

CLK
RIiIR~-------------------------------------------------------

~~----------------~---------------------------------01NO-1

iiiiiii~
CINO-1

CiEiii ~
AORO-l

101,lz13101t1Z131
I v31 v41 v51 VI I V1 1v,1 Vg 1

8UMO-Z5
8HAOO~hWA

en

iiiiii W///////~/A

....a:

~

. Wiiii W///I/////ff//////h00WffiW/hi
OCMO-t

1 1-1-----------------------------------------------------..

i:i:

c

0

FIGURE 4.

I

30MHz 4 TAP FILTER TIMING

SAMPLE
DATA IN ) (X.)

.--, PROM PI
P4
ClK
P3
P2
, - A2
Pt, - At

30MHz
CLOCK

7

.-

YI

3C:~T

SYSTEM
RESET

I

Y1
yz

'--

I.a COEFF.
.... AI RAMIROM

-

...... Al
A2

00-7

SUMO-25

f-!!I

HSP43411
DFI

ClK

~ CIHD-7

~

~

TCCO
COUTO-7

+iVYl

~

DIENI ADRt ADROVcc IHADD IENIH IENll

•

TCI

TCCI

SUMD-Z5 ~Z.

DIND-7
TCI
H8P43411
DF1

ClK

TCCO r-

TCCI

•

COUTO-7

CIHD-7

WiOCM1 DCMe REm mAshss Giifii

miii DCM1 DCMO iiiiiT iiiAsi VSI Giifii

1

I

.

DDERAS~
FIGURE 5.

~I I

h

~ DINO-1

DiiiW
ClK

~

DIENI ADRl ADRD Vcc SHADDSENIH SENll

DDERAS

--.. >--

I

I I +iV~

iiiiiiii~

30MHz 8 TAP FILTER USING TWO CASCADED HSP43481s

3-89

..

r-- NC

~ r-- HC
SUM
OUT
(Y.)

HSP43481
Extended FIR Filter Length
Filter IEulgths'greater than four taps 'can be created by either
cascading together multiple OFs or "reusing" a Single OF.
.using multiple devices, an FIR filter of over 1024 taps can
be construct8dto operate at a ,,30MHz sample rate. Using
a single DE clocked at 30M Hz, an FIR filter of over 1024
taps can be constructed to operate at less than a 30MHz
sample rate. Combinations of these two techniques are also
possible.

Cascade Configur;,Jtion
To design a filter length L> 4; LJ4 'OFs are cascaded by
connecting the COUTO-7 outputs of the (i)th OF to the
CINO-7 inputs of the (i + 1)th OF. The OINO-7 inputs and
SUMO-25 outputs of all the OFs areslso tied together. A
specific example of two cascaded OFs illustrates the technique (Figure 5). Timing (Figure 6) is similar to the simple 4
tap FIR, except the ERASE and SENBLJSENBH signals
must be enabled independently of the two OFs in order to
clear the correct accumulators and enable, the SUMO-25
output signals at the proper times.

TABLE 2.

Single 'OF Configuration
Using a OF, a filte'r of length L > 4 can

be constructed by
processlngj" Li4passes as'illustrated in Table :2 fpi
8
tap FIR; Each paSs is composed of Tp =7+L cycles and
computes four output samples. In pass i, the samples with
Indices I x 4 to i x 4 + (L+2) enter the DINO-7 Inputs. The
coefficients CO-CL-1 enter the CINO-7 inputs, followed by
three zeros. As these zeros are entered, the result samples
are output and the ' accumulators reset. Initial tilling of the
pipeline is not shown in this sequence table. Filter outputs
can be put through a 'FIFO to even out the sample rate.

Extended Coefficient And,
Data Sample Word Size
The sample and coefficient word size can be extended by
utilizing seileraJ OFsin parallel to get the maximum sample
rate or a Single OF with resulting lower sample rates. The
technique is to compute partial products of axa and
combine these partial products by shifting and adding to
obtain the final result The shifting and adding can be
accomplished with external adders (for full speed) or with
the OFs shift-and-add mechanism contained in Its output
stage (at reduced speed). ,

8 TAP FIR FILTER SEQUENCE USING SINGLE OF

DATA
SEQUENCE
INPUT
DATA
SEQUENCE
INPUT
CLK

CELLO

0
1

C7 X Xo
+Ca XX1
+CSxX2
+C4 xX3

2
3
4

CELL 2

CELL 3

SUM/CLR

0

0
0

0
0

-

C7 XX2

0

+Ca xX 3
+CSxX4
+C4 XXS

C7 xX3
+Ca xX4
+CsxXs
+C4 XXa
+C3 X,X7
+C2 xXa

-

S

+C3 xX4
+C2 XXS

a

+C1 xXa

+C3 xXS
+C2 XXa

7

+COxX7
0
0

+C1 xxi''''
+CO XX8'
0

8
9
10
11

,

CELL 1

C7 xX 1
+Ca xX2
+CS xX3
+C4 xX4

12
13
14
1S
1a
17
1a
19
20
21

0
C7x~

+CaxXs
+CsxXa
+C4 XX7
+C3 XXa
+C2 xX9
+C1'X'X10
+COxX11
()

0
0

0
0
C7 XXS
+CaxXa
+CSXX7
+C4 XXa
+C3 XX,9
+C2 XX 10
+C1 xX11
+CoxX12
0
0

ar

+C3 xXa
+C2 XXT
+C1 xXa
+Co xX9
0
0
0
C7 xX a
+Ca xX7
+CsxXa
+C4 xX9
+C3 xX 10
+C2 xX11
+C1 xX12
+CO XX13
0

3-90

+C1 xX9
+Co xX 10
0
0
0
C7 xX7
+Cax.xa
+CsxXg
+C4 xX10
+C3 xX11
+C2 XX 12
+C1 XX13
+COXX14

Cell 0(Y7)
CeIl1(Ya)
CeIl2(Yg)
Cell 3 (Y1O)

-

-

Cell o (Y11)
Cell 1 (Y12)
Cell 2 (Y13)
Cell 3 (Y14)

HSP43481

2

3

4

5

6

7

L-

DFO ERAsE ~

DF1ERAsE~--------------------------------------'L-______~'----

DINO-7

iiiENa

WZI

I c71 c61 c51 c41 c31 c21 c, I Co I c71 c61 C5 I c41 c31 C2 IC, I Col

CINO-7

• •

CiENa ~
ADRO-1

101'1213101'1213101'1

IV71 Val VgI V101
IV151
IV111 V121 V131 V141

DFO SUMO-25
DF1 SUMO-25

SHADD~/.&l

SftiBiTti ---..J
DF1 SftiBiTti -----,L________--.J

L

DFO

DCMO-1

1

0

'------',

1-1- - - - - - - - - - - - - - - - - - - - - - - - - - - -

7
VN = 2: CK x XN-K
K=O
FIGURE 6.

30MHz 8 TAP FIR FILTER TIMING

Decimation/Resampling
The HSP43481 provides a mechanism for decimating by
factors of 2, 3 or 4. From the DF filter cell block diagram
(Figure 1), note the three D registers and two multiplexers in
the coefficient pass through the cell. These allow the coefficients to be delayed by 1, 2 or 3 clocks through the cell. The

sequence table (Table 3) for a decimate-by-two filter
illustrates the technique.
Detailed timing for a 30M Hz input sample rate, 15MHz
output sample rate (I.e., decimate-by-two), 8 tap FIR filter,
including pipelining, is shown in Figure 7.

3-91

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HSP43481
TABLE 3. 8 TAP DECIMATE-BY-TWO FIR FILTER SEQUENCE, 30MHz IN, i5MHz OUT
DATA
SEQUENCE
INPUT
. COEFFICIENT
SEQUENCE
INPUT

CLK

CELLi

CELLO

CELL 2

CELL 3

SUM/CLR

6

+Cl xX6

+C3 xX6

+C5 xX6

+C7 xX6

-

7

+COxX7

+C2 xX7

+C4 XX7

+C6 xX7

CelIO(Y7)

a

C7 x Xa

+Cl xXa

+C3 xXa

+C5 xXa

CeIlO(Y7)

9

+C6 xX9

+CoxXg

+C2 xX9

+C4 xX9

Cell 1 (Yg)

10

+C5 XX10

C7 XX10

+C1 XX10

+C3 xXl0

Cell 1 (Yg)

11

+C4 XX1l

+Ca XXl l

+COXX11

+C2 XX 11

CeIl2(Yl1)

0

C7 X Xo

0

1

+C6 xXl

0

2

+C5 XX2

C7 xX2

3

+C4 xX3

+C6 xX3

4

+C3 xX4

+C5 XX",

C7 XX4

5

+C2 xX5

+C4 XX5

+C6 xX5

12

+C3 xX12

+C5 xX12

C7 XX12

+C1 XX12

Cell 2 (Yll)

13

+C2 xX13

+C4 XX13

+Ca XX13

+CO XX 13

Cell 3 (Y13)

14

+C1 xX14

+C3 xX14

+C5 XX14

C7 XX14

CeIl3(Y131

15

+CO XX15

+C2 XX15

+C4 XX15

+CS xX 15

Cell o (Y15)

3

4

S

•

7

ClK

iiEffi L.J
iiiAii

I Xo I Xl I Xz I X31 ~ I X51 Xi I X71

DINO-7

iii'ENi ~

I e71 e&1 csi

CINO-7

e41

cal ez I Cl I Co I . . .

Ciftii ZZZl
ADRO-l
SUMO·Z5

Va

SHADD&~M

SENBl 0"/&000W~~/ffffh1
iENiii ;;mrffh00'/00W~ffiW/~$Al

D~O~

I

1

I~------------------------------------------------------~·

FIGURE 7.

8 TAP DECIMATE-BY-TWO FIR FILTER TIMING, 30MHz IN, i5MHz OUT

3-9?

Specifications HSP43481
Absolute Maximum Ratings
Supply Voltage •••••••••••••••••••••••••••••••.••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• +8.0V
Input, Output Voltage .......................................................................... GND -0.5V to VCC +0.5V
Storage Temperature ........' ......................................................................... -650 C to +1500C
ESD ......................................................................................................... Class1
Maximum Package Power Dissipation a1700 C ••••••••••••••••••••••••••.••••••••••••••••••••••.• 1.9W (PLCC), 2.6W (PGA)
Bjc ..•••••.•••••••••••••••••••••.•••••••.••••••••••••••••••••• '•••••••..•••••••.••... 15.0W,JOC (PLCC), 9.92WJOC (PGA)
Bja ..•••••..••••••••••••••••••••.•••••.•••••••••••••••••••••••••.••••••••••••.••••• 43.0WJOC (PLCC), 38.44WJOC (PGA)
Gate Count ..................................................................................................... 9371
Junellon Temperature. • • • • • • • • . • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • . • • • • • •• 1500 C (PLCC), 1750 C (PGA)
Lead Temperature (Soldering 1Os) •••••.•.•••..•.••..••.••••....•••••••....••.••...•••••••••••••••••••••••••••••• 3000 C
CAUTION: Stresses above those listed in the "Absoluttt Maximum Ratings" may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range .•••••••••..••.•.•.••••••••••••••••••••••••••••••••••••••••••••••..••.••.••••••••••••• 5V ±5%
Operating Temperature Ranges ••••..•••.••.•• , ••••••••••••••••••••.••••••••••••••••••••.••.•..••••••••••• OoC to + 700C

D.C. Electrical Specifications
SYMBOL

a:
'"
w

MAX

UNITS

ICCOp

Power Supply Current

PARAMETER

MIN

110

mA

VCC=Max
CLK Frequency 20M Hz
Note 1, Note 3

TEST CONDITIONS

ICCSB

Standby Power Supply Current

500

"A

VCC = Max, Note 3
VCC= Max,lnput=OVorVCC

Input Leakage Current

-10

10

pA

10

Output Leakage Current

-10

10

pA

VCC = Max,lnput = OVorVCC

VIH

Logical One Input Voltage

2.0

V

VCC=Max

VIL

Logical Zero Input Voltage

0.8

V

VCc=Min

V

10H = -400pA, VCC = Min

0.4

V

10L = 2mA, VCC = Min

II

2.6

VOH

Logical One

VOL

Logical Zero Output Voltage

VIHC

Clock Input High

VILC

Clock Input Low

CIN

Input Capacitance
Output CapacRance

COUT

V

Vcc=Max

0.8

V

Vcc=Mln

PLCC
PGA

10
15

pF
pF

PLCC
PGA

10
15

pF
pF

CLK Frequency 1 MHz
All Measurements
Referenced to GND
TA = +250 C Note 2

VCC-O.8

NOTES: 1. Operaling supply currenl is propcrtional 10 frequency. Typical
rating is 5.5mNMHz.
2. Controlled via design or process paramelers and nol direclly
tested. Characterized upon initial design and after major process
andlor design changes.

3. Oulpulload per lesl circuil and CL = 40pF.

3-93

!:i
u:::
Q
I

!

Specifitations HSP43481
A.C. Electrical Specifications

Characterized Over Commercial Temperature Range OOC. to +700 C
-20 (20MHz)

SYMBOL

PARAMETER

-25 (25.6MHz)

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

33

-

n8

13
13

-

0

-

TCI?

Clock Period

50

-

39

TCl

Clock Low

20

-

16

TCH

Clock High

20

TIS

Input Setup

16

TIH

Input Hold

0

-

-

26

-

22

20

-

15

TODC

ClK to Coefficient
Output Delay

TOED

Output Enable Delay

-30 (30MHz)

-

30

TODD

Output Disable Delay

TODS

ClKtoSUM
Output Delay

TOR

Output Rise

-

6

TOF

Output Fall

-

6

16
14

-

20

15

13
0

-

6

-

Ii

-

26

TEST
CONDITIONS

n8
na

-

na

19

n8

15

na

na

15

ns

21

ns

Note 1

6

ns

Note 1

6

na

Note 1

NOTE: 1. Contrclled by design or process parameters and not d~ectly
tested. Charecterized upon inRiai design and after maior process
and/or design changes.

Test Load Circuit

r - - - - - - - - - - - - - --I
1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1.5V

1

1

IOL

1

1

'INCLUDES STRAY AND 1
JIG CAPACITANCE
1____

1

EQUIVAlENT~IRCUrr _ _ _ _ j

SwHch 51 Open for ICCSB and ICCOp Tests

3-94

HSP43481
Waveforms

..r---~-------- VCC '0.""

INPUT"

OV

CLK

3.OV-----OV-----J
• Input includes: DlNo-7. CINo-7. DIENB, CIENB. ERASE. RESET. DCMo-l.
ADRO-l. TCS. TCCI. SHADD

CLOCK AC PARAMETERS

INPUT SETUP AND HOLD

QK~-------

SUMO-25
COUTO -7
TCCO

f-':=TODCo TODS ______ _

r

1.5V
OUTPUT

-------

RISE AND FALL TIMES

SUMO-25, COUTO-7, TCCO OUTPUT DELAYS

tn
a:
w

!:i

u:

CI
I

3.0V
INPUT

----v::-:;-1 DEVICE

r-----v::-::-

OV _ _ _ _~U:~~~

A.C. TesUng: Inpuls are driven al3.0V for a Logic "1" and OV for a Logic "0".
Inpul and outpuillming measurements are made all.5V for bolh a Logic "1·
and "0". Inputs are driven al1V/ns. CLK is driven al VCC -0.4 and O.OV and
measured al 2.5V.

A.C. TESTING INPUT, OUTPUT WAVEFORM

3-95

{lJHARRIS

HSP43481/883
Digital Filter

May 1991

Features

Description

• This Circuit Is 'Processed In accordance to MII-Std-883C
and Is Fully Conformant Under the Provisions of
Paragraph 1.2.1

The HSP43481/883 is a Video-speed Digital Filter
(OF) designed to efficiently implement vector
operations such as FIR digital filters. It is, comprised of
four filter cells cascaded internally and a shift-andadd output stage, all ina single integrated circuit.
Each filter cell contains an 8x8 multiplier, three
decimation registers and a 26 bit accumulator which
can add the contents of any filter cell accumulator to
the output stage accumulator shifted right by eight
bits. The HSP43481/883 has a maximum sample rate
of 25.6MHz. The effective multiply-accumulate (MAC)
rate is 102MHz.

• 0 to 2S.6MHz Sample Rate
• Four Filter Cells
• 8 Bit Coefficients and Signal Data
• Low Power CMOS Operation
~ Iccse = SOOIlA Maximum
~ ICCOp = 11 OIlA Maximum @ 20MHz
• 26 Bit Accumulator Per Stage
• Filter Lengths Up To 1032 Taps
• Shlft-And-Add Output Stage for Combining Filter Outputs
• Expandable Coefficient Size. Data Size and Filter Length
• Decimation by 2. 3 or 4

Applications
• 1-0 and 2-D FIR Filters
• Radar/Sonar
• Digital Video and Audio
• Adaptive Filters
• Echo Cancellation

The HSP43481/883 can be configured to process
expanded coefficient and word sizes. Multiple
devices can be cascaded for larger filter lengths
without degrading the sample rate or a single device
can process larger filter lengths at less than 25.6MHz
with multiple passes. The architecture permits
processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter
coefficients are less than 1.0, making even larger
filter lengths possible. The HSP43481/883 provides for
unsigned or two's complement arithmetic, independently
selectable for coefficients and signal data.

• Correlation/Convolution

Each OF filter cell contains three resampling or
decimation registers which permit output sample rate
reduction at rates of 1/2, 1/3 or 1/4 the input sample
rate. These registers also provide the capability to
perform 2-D operations such as NxN spatial correlations/convolutions for image processing applications.

• Complex Multiply-Add
• Butterfly Computation
• Matrix Multiplication
• Sample Rate Converters

Block Diagram

01NO-7

Tes

TCCI L > - - - - - - - i
CINO-7

TCCD

C>-''+----I

CQUTD-7

iiffiT

CLKC=>-~~~~4-----~~----~-+----~

AORO-1

26

iiffii

CLK c.-;~--------I

SHADD c:::::>---------------___t DSU::'~T

~Lc=>--~~-----___t

iENiii

28

SUMD-25

CAUTION: These devices are SlOnsHive to eleclroslstic discharge. Users should follow proper IC Handling Procedures.
Harris Corporation 1991
Copyright

e

3-96

File Number

2450.1

Specifications HSP43481/883
Absolute MaxImum RatIngs

Reliability Information

Supply Voltage ••••••••••.•••••••••••••••••••••••••••.. +8.0V
Input, Output Voltage Applied ••.•••.•.• GND-0.5VtoVCC+0.5V
Storage Temperature Range •••••••••••••••.• -650C to +1500 C
Junction Temperature .••••••••••••••••••••••••••••••• +1750 C
Lead Temperature (Soldering, Ten Seconds) ••.••••••••• +3000 C
ESD Classification •••••••••••••.•••••••••...•.•••••••• Class 1

Thermal Resistance
Dja
Djc
Ceramic PGA Package •••.•.••••••• 38.440 CIW 9.920 CIW
Maximum Package Power Dissipation at +125OC.
Ceramic PGA Package ••••••••.••••••••••••••••••• 1.30 Watt
Gate Count •••••••••.•••••••.••.••••••••••••••••• 9370 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is.a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range ••••••••••.•••••.•••••• +4.5V to +5.5V
Operating Temperature Range ••••••••••••••• -550C to +1250C
TABLE 1. HSP43481/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Devices Guaranteed and 100% Tested

PARAMETER

TEMPERATURE

MIN

MAX

UNITS

VIH

VCC=5.5V

1,2,3

-550 C.$.TA.$.+1250C

2.2

-

V

Logical Zero Input
Voltage

VIL

VCC=4.5V

1,2,3

-550 C.$.TA.$.+1250C

-

0.8

V

10H = -400,.A
VCC=4.5V(Note1)

1,2,3

-550 C.$.TA.$.+1250C

2.6

-

V

Output LOW Voltage
Input Leakage Current

VOH
VOL
II

CONDITIONS

LIMITS

Logical One Input
Voltage

Output HIGH Voltage

SYMBOL

GROUP A
SUBGROUPS

0.4

-550 C.$.TA.$.+1250C

-10

+10

,.A

1,2,3

-5SOC.$.TA.$.+1250C

-10

+10

,.A

-

V

1,2,3

VIN=VCCorGND
VCC=5.5V

1,2,3

VOUT= VCC orGND
VCC=5.5V

-550 C.$.TA.$.+1250C

V

I

10

Clock Input High

VIHC

VCC=5.5V

1,2,3

-5SOC.$.TA.$.+1250C VCe-° B

Clock Input Low

VILC

VCC=4.5V

1,2,3

-550C .$.TA.$. +1250 C

-

0.8

V

Standby Power Supply
Current

ICCSB

VIN = VCC or GND
VCC=5.5V,
Outputs Open

1,2,3

-550 C.$.TA.$.+1250C

-

500

,.A

Operating Power
Supply Current

ICCOp

f=20.0MHz
VCC = 5.5V (Note 2)

1,2,3

-550 C.$.TA.$.+1250C

-

110.0

mA

7,8

-550 C.$.TA.$. +1250 C

-

-

FT

;:;:
Q

Output Leakage
Current

Functional Test

w

!:i

-

IOL=+2.0mA
VCC=4.5V(Note1)

en

a:

(Note 3)

NOTES: 1. Interchanging of force and sense conditions is permitted.
2. Operating Supply Current is proportional to frequency, typical
rating is 5.5mNMHz.

3. Tested as, follows: f - 1MHz. VIH - 2.6, VIL = 0.4, VOH :!: 1.5V,
VOL
1.5V, VIHC = VCC -0.4V, and VILC = 0.4V.

3-97

s:

Specifications HSP43481/883
TABLE 2. HSP43481'/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
-20 (20M Hz)

GROUP A
SYMBOL CONDITIONS SUBGROUPS

PARAMETER

-25 (25.6MHz)

TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

-

39

ns

TCH

Note 1

Input Setup

TIS

Note 1

9,10,11

-550 C 

!2

B~

4-4

!
u

It It "
~ ~::>
i§ ::>

II

.

~
::>

~::>

§

8 8 8 8 8

HSP48908
Block Diagram

CASOO-7
CINO-9 ---..,..-~

FRAME-#~
RESET-#~

rn
a:::
w

OE-#~

u:

CASIO-15

3

AO-2----../-J.~
ADDRESS
DECODER

1 I r-c

CLOCK
CU<
HOLD---. GEN

'

!:;
CI
I
N

LD.#" -------__ooo
..-li ......~--__,
.. 1 T COH

X

CINO-9

----------------------~ I

X

SYNCHRONOUS LOAD TIMING

HOLD TIMING
CLK

I..

..I ..

1 THS

HOLD

1

THH

J--,----:------

INTERNAL
CLOCK

FRAME#IRESET# TIMING

CLK
_ _ _ _..... 1 ..

RESET#'

TRPW"I ,-.,....-_ _ _ _ _ _ _ ___

~I

1"·Ii-F~1

FRAME#'

-----~-------------------

4-18

~----

mHARRIS

HSP48908/883
Two Dimensional Convolver

May 1991

Features

Description

• This Circuit is Processed in accordance to Mil-Std883C and is Fully Conformant Under the Provisions of
Paragraph 1.2.1

The Harris HSP48908/883 is a high speed Two Dimensional
Convolver which provides, a single chip implementation of a
video data rate 3 x 3 kernel convolution on two dimensional
data. It eliminates the need for externaL data storage through
the use of the on-chip row buffers which are programmable
for row lengths up to 1024 pixels.

• Single Chip 3x3 Kernel Convolution
• Programmable On-Chip Row Buffers
• DC to 27MHz Clock Rate
• Cascadable for Larger Kernels and Images
• On-Chip 8-Bit ALU
• Dual Coefficient Mask Registers, Switchable in a
Single Clock Cycle
• 8-Bit Signed or Unsigned Input and Coefficient Data

Data is provided to the HSP48908/883 in a raster scan non~
interlaced fashion, and is internally buffered on images up to
1024 pixels wide for the 3 x 3 convolution operation. Images
with larger rows and convolutiolT with larger kernel sizes can
be accommodated by using external row buffers and/or
multiple HSP48908/883's. Coefficient and pixel input data
are 8-bit signed or unsigned integers, and the 20 bit
convolver output guarantees no overflow for kernel sizes up
to 4 x 4. Larger kernel sizes can be implemented however,
since the filter coefficients will normally be less than their
maximum 8-bit values.

• 20-Bit Extended Precision Output
• Standard ",p Interface
• TTL Compatible Inputs/Outputs
• Low Power CMOS
• Available in 84 Pin PGA Package

Applications
• Image' Filtering

The HSP48908/883 is manufactured using an advanced
CMOS process, and is a low power fully statiC design. The
configuration of the device is controlled through a standard
microprocessor' interface and all Inputs/outputs are TTL
compatible. The 2-D convolver is available In 84 pin P.GA..
package.

• Edge Detection'
• Adaptive Filtering
• Real Time Video Filters
• Image Warping

Pinout
HSP48908/883 (PGA)
TOP VIEW

There are internal register banks for storing two independent
3 x 3 filter kernels, thus facilitating the implementation of
adaptive filters and multiple filter operations on the same
data. The pixel data path also includes an on-chip ALU for
performing real-time arithmetic· and logical pixel point
operations.

11

CASCO

DOUTO

10

CAS04

CAS06 CA807

9

CA803

GND

B

CASa1

CA803

7

oe#

GND

DOUT1

DOUT8 DOUT10 DOUT1! DOUT13 D0UT1S

GND

DOUTS

DOUT8

DOU12

DOUT4

DOUT8

GND

D0UT3

DOUT7

"cc

D0UT11 D0UT1

"cc

GND

Vee

REIIEI'

CAS..

CASM

CASI3

CASI7

CASB

CASI10

CAS.

CAB.,3 CASn1

CASB

DIND

5

0lN2

DIN3

DI...

4

DIN&

DIN6

3

DIN7

C0N1

2

elNO

elM3

C1N4

CINT

GND

. vee

1

c.,.

elMI

CINe

C ...

CLI<

A1

cs#

III

CASI1S

A

B

e

o

E

F

G

H

J

LD#
EAW

DOUT1

CAS..

CA80D

.

DOUT1O

CAS"

DIN1

HOLD

DOUT1

_ME

6

CINI

#

IT

CASI14 CAB"!

K

CAUTION: These devices are .ens.ive to electrostatic discharge. Proper I.e. handling procedures should be followed.
Copyright @ Harris ColJloration 1991

4-19

D0UT1

CASn

84 PINPGA
TOP VIEW

GND

L

File Number

2783.1

en

a:
!:;
LU

u:::

C

I

N

Specifications HSP48908/883
Abs9lvteJl!laXlmum~ Ratings

ReUabU)ty Information

Supply Voltage •••••••••••••••••••••••••••••••••••••••• +8.0V
Input, Output or I/O Voltage Applied •••• GND-0.5V to VCC+O.5V
Storage Temperature Range ••••••••••••••••• ,:650 C to +1500C
Junction Temperature, ••••••••••••••••••••••••' •••••••• +175OC
Lead Temperature (Soldering 10 sac) •• , ••••••••••••••• +3000C
ESD Classification •••••••••••••••••••••••••••••••••••• Class 1

Thermal Resistance
Sja
Sjc
Ceramic PGA Package •••••••••••••••• 34.56OC/W 7.730C/W
Maximum Package Power Dissipation at +12SOC
Ceramic PGA Package ............................... '. 1.45W
G~ Count •••.••.••• , ..••••••••.•••••••• 190,OOQTransistors

.

CAUTION: Absolute maximum ratings are limmng valuss, appJiedindlvidual/y beyond which the servlceabiHIy of the circuit may be impaired. 'Functional
operabiNly under any of these conditions is not necessarUy Implied.
.

'

Recommended Operating Conditions
Operating Temperature Range, , , , , , ••••••••••• ~5SOC to +12SOe
Operating Voltage Range .... , ...... ;' ........... +4.5Vto +5.511
TABLE 1. ,D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

D.C. PARAMETERS

SYMBOL

logical 1 Input Voltage

VIH

VCC=5.5V

Logical 0 Input Voltage

VIL

Vec= 4.5V ,

VIHe
VILe

Clock Input High
ClockJnpuj Low

CONDITIONS

GROUP A
SUBGROUP

UMITS
TEMPERATURE

MIN

MAX

UNITS

1,2,3

-550C~TA~+1250e

2.2

-

V

1,2,3

-5SOC

i5

C
Z

~

0
-0:
0

(f)

(f)

(f)

-0:
0

-0:
0

<'l

0
-0:
.0
(f)

~

0
-0:
0

'"

0
-0:
0

c

(f)

(f)

Z

~

to

C

.,
C

(72) DOUTO
(71) DOUT1
(70) DOUT2
(69) GND
(68) DOUT3
(67) DOUT4
(66) DOUT5
(65) DOUT6
(64) DOUT7
(63)

Vcc

(62) DOUT8
(61) GND
(60) DOUT9
(59) DOUT10
(58) DOUT11
(57) DOUT12
(56) DOUT13
(55) DOUT14
(54) GND

CASI12

M ;~

'.,

to

~ .~ ~

... ..

r:- com s
~

co ....

0

~~

CD

0

.,

..

N M ;!. !. !. !. !. !.

~

.~

<'l

0

0

0

0

'" iii iii iii (f) iii iii 0
iii
iii iii -0: -0: -0: -0: -0: -0: -0: >
-0:
0

-0:
0

0

0

0

'"

~CJ

.... ..
0

iii iii
-0:
0

5

4-24

.,

s
e

to

r:-

'II

'II C
I- Z

l-

'"

I-

l:;)

:;)

I-

:;)

I-

:;)

(f)

0

0

0

0

0

!. !. !.
w

~
a:

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HSP48908/883
Packaging t
84 LEAD PIN GRID ARRAY (PGA)

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SEA TING

I

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4

5

6

7

8

.080 MAX

9

10

11

.100

L

L

.003 MIN

LEAD MATERIAL: Type B
LEAD FINISH: Type C

~
Max

sse

.080

.120

INTERNAL LEAD W,IRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic Wedge
COMPLIANT 38510 OUTLINE: P-AC

PACKAGE MATERIAL: Ceramic, 90% AI203
PACKAGE SEAL:
Material: Gold/Tln
Temperature: 3200C ± 100 C
Method: Furnace Braze

NOTE: All Dimensions are

J40

.040
.060

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tMd-M"38510 Compliant Mlllerials, Finishes, and Dimensions.

, Dimensions are In inches.

4-25

HSP48901

mHARRIS

3

May 1991

X

3 Image Filter

Features

Description

• DC to 30MHz Clock Rate

The Harris HSP48901 is a high speed 9-Tap FIR Filter
which utilizes 8-bit wide data and coefficients. It can be
configured as one dimensional (1-0) 9-Tap filter for a
variety of signal processing applications, or as a two
dimensional (2-D) filter for image processing. In the 2-D
configuration, the device is ideally suited for implementing
3 x 3 kernel convolution. The 30MHz clock rate allows a
large number of image sizes to be processed within the
required frame time for real-time video.

• Configurable for 1-D and 2-D Correlation/
Convolution_
• Dual Coefficient Mask Registers, Switchable in a
Single Clock Cycle
• Two's Complement or Unsigned 8-Bit Input Data
and Coefficients
• 20 Bit Extended Precision Output

a:

Data is provided to the HSP48901 through the use of
programmable data buffers such as the HSP9500 or any
other programmable shift register. Coefficient and pixel
input data are 8-bit signed or unsigned integers, and the 20
bit extended output guarantees no overflow will occur
during the filtering operation .

• Standard liP Interface
• TTL Compatible Inputs/Outputs
• Low Power CMOS
• Available in 68 Pin PGA and PLCC Packages

Applications
• Image Filtering

There are two internal register banks for storing independent 3 x 3 filter kernels, thus facilitating the implementation
of adaptive filters and multiple filter operations on the same
data.
The configuration of the HSP48901 .Image Filter is controlled through a standard microprocessor interface and all
inputs and outputs are TTL compatible. The HSP48901 is
available in 68 pin PGA and PLCC packages.

• Edge Detection/Enhancement
• Pattern Matching
• Real Time Video Filters

Block Diagram
DIN3 (0-7)
DIN2 (0 - 7)
DIN.

(o· 7)

FRAME#

-~_ _....J

ADDRESS
DECODER

I

INTERNAL

C L K - I CLOCK
HOLO ----+
GEN

CL~K

rz:;"]

~DOUTO-'9

CAUTION: Electronic devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

4-26

File Number

2459.1

HSP4890t
Package Pinouts
68 LEAD PLCC
TOP VIEW

§:"

-

Ii ! ! ! ! E

>"
"

iii
0

;.

Ii

~ ~

i

0

B

8

7

•

4

a

0

5

iii

i iii
• •

iIS

0

•

"D1N2 (7)
DlN2 (8)

§~
0
0

0

.

~ i!!
80 !i00 80 80 >8

~

.

88 87 .. B5 84

.. 8 •
DOUT8
DOUT7

DlN2C5J

DOUTI

DIN2 C41

DOUTB

DoNo cal

qND

DIN2 COl

DOUT10

DIN2 C'I

DOUTt 1

DIN2 COl

DOUTt.

qND

DOUT13

DINa ClI

DOUTt.

DINa COl

DOUTt5

DlN3C5J

DOUTt'

DINa C4I

DOUTt7

DINa cal

DOUTt.

DIN3(2)

DOUTt'

DINa C'I

Vee

DINa COl
3D

~d iIS

a.

.

.

33 34 35 38 37

S " I" !" i""; "iii
II

~

. ......

FRAMES#"

4.

.. ~ ; 1I
0

z

42 43

:c

i

68 PIN GRID ARRA V
TOP VIEW
DOUT8 DOUTt DOUTt DOUT10 DOUT12 DOUTt. DOUTt. DOUTt.

II

FRAME
#'

AD

DOUT4

A2

A.

DOUT.

DOUTO

I.D#

HOLO

GND

DOUTD

elND

GND

DOurs

Vee

•

DOUTS

I

7

'0

Vee

DOUT8

GND

DOUT" OOUT1S DOUT15 DOUT17 DOUTt.

•

DIN. CII DIN1

(7)

elN2

elN1

5

DII. C4I DIN. C"

elM4

elNS

4

011. C2I 011. COl

CIN.

elNI

a

DII. COl 011. C'I

GND

elM7

Vee

CLK

2

VCC

DIN2f11 01121111 0112131 DIN21'1

GND

DINSCII OIlS C41 OIlS C2I

01121111 DlN2 C4I DIN2 C2I 0112 COl DINSfII DINS,..
A

8

C

D

E

F

4-27

Q

DINS ''''

H

DII"'I DINS COl
K

HSP4S901
,:'';.' ...

Pin Descriptions
,

NAME

PlCCPIN

TYPE

VCC

9,27,45,61

GND

18, 29, 38, 56

CLK

28

I

Input and System clock. Operations are synchronQu$ with the rising edge of this
clock signal.

DIN1{O-7)

1-8

I

Pixel Data Input bus #1. These inputs are,u~ed to provide B-bit pixel data to
the HSP48901. The data must be provided in a synchronous fashion, and is
latched on tha rising edge of the ClK signal. The OINt{O-7) inputs are also used to
Input data when operating In the 9 Tap FIR mode.

DIN2(Q-7)

10-17

I

Pixel Data Input bus #2. Same as above. Th,ese inputs should be grounded when
operating in the 1D mode.

DIN3(O-7)

19-26

I

Pixel Data Input bus #3. Same as above. These inputs should be grounded when
operating In the 1D mode.

CINQ-7

30-37

I

Coefficient Data Input bus. This input bus is lJBed to load the Coefficient Mask
register{s) and the Initialization register. The register to be loaded is defined by
the register address bits AO-2. The CINO-7 data Is loaded to the addressed register
through the use of the LD# input.

DOUTO-19

46-55,57-60,
62-67

0

Output Date bus. This 20-Bit output port is ussd to provide the convolution result.
The result is the sum of products of the input data,samples and their corresponding
coefficients.

FRAME#

44

I

Frame# is an asynchronous new frame or, vertical sync input A low on this input
resets all internal circuitry except for the Coefficient and INT registers. Thus,
after a Frame# reset has occurred, a new frame of pixels may be convolved without
reloading these registers.

HOLD

40

I

The Hold Input is used to gate the clock from all of the Internal circuitry of the
HSP48901. This signal is synchronous, is sampled on the rising edge of ClK and
takes effect on the following cycle. While this signal is active (high), the clock will
have no effect on the HSP48901 and Internal dala will remain undisturbed.

AO-2

41-~

I

Control Register Address. These lines are decoded to determine which register in
the control logic is the destination for the data on the CINQ-7 inputs. Register
loading is controlled by the AO-2 and lD# Inputs.

lD#

39

I

load Strobe. LD# is ussd for loading the internal registers of the HSP48901. The
rising edge of lD# will latch the CINQ-7 data into the register specified by AQ-2.
The Address on AQ-2 must be set up with respect to the falling edge of lD# and
must be held with respect to the rising edge of LD#.

DESCRIPTION
The, +5V power 'supply, pins. 0.11'F capacitors between the VCC and GND pins are
recommended.
The dllvk;e grou'nd.

4-28

HSP489 0 1
Functional Description

8-Bit Multiplier Array

The HSP48901 can perform convolution of a 3 x 3 filter
kernel with 8-bit image data. It accepts the image data in a
raster scan, non-interlaced format, convolves it with the
filter kernel and outputs the filtered image. The input and
filter kernel data are both 8-bits, while the output data is
20-bits to prevent overflow during the convolution operation. Image data is input via the DIN1, DIN2, and DIN3
busses. This data would normally be provided by programmable data buffer such as the HSP9500 as illustrated in the
operations section of this specification. The data is then
convolved with the 3 x 3 array of filter coefficients. The resultant output data is then stored in the output register. The
HSP48901 may also be used in a one-dimensional mode.
In this configuration, it functions as a 1-D 9-tap FIR filter.
Data would be input via the DIN1(O-7) bus for operation in
this mode..

The multiplier array consists of nine 8 x 8 multipliers. Each
multiplier forms the product of a filter coefficient with a corresponding pixel in the input Image. Input and coefficient
data may be in either two's complement or unsigned integer
formal The nine coefficients form a 3 x 3 filter kernel which
is multiplied by the input pixel data and summed to form a
sum of products for implementation of the convolution operation as shown below:

Initialization of the convolver is done using the CINO-7 bus
to load configuration data and the filter kernel(s). The
address lines AO-2 are used to address the internal
registers for initialization. The configuration data Is loaded
using the AO-2, CINO-7 and LD# controls as address, data
and write enable, respectively. This interface is compatible
with standard microprocessors without the use of any
additional glue logiC.
Filtered image data is output from the convolver over the
DOUTO-19 bus. This output bus is 20-bits wide to provide
room for growth during the convolution operation.

FILTER KERNEL

INPUT DATA

A

8

C

P1

P2

P3

0

E

F

P4

P5

P6

G

H

I

P7

P8

P9

OUTPUT = (A x P1) + (8 x P2) + (C x P3)
+ (0 x P4) + (ExP5) + (F xP6)
+ (G x P7) + (H xP8) +(1 x P9)

Control Logic
The control logiC (Figure 1) contains the Initialization
Register and the Coefficient Registers. The control logic is
updated by placing data on the CINO-7 bus and using the
AO-2 and LD# cOntrol lines'to write to the addressed
register (see Address Decoder). All of the control logiC
registers are unaffected by FRAME#.

.,.
a::
w
~

u::
CI

AO -2
LD-#

I

ENCRO-#
ENCR1-#
CAS-#
CR1-#
CRO-#

3
- - - - ; f - - -... ADDRESS

DECODE

N

INITIALIZATION
DATA

CINO -7

COEFFICIENT
REGISTER 0
CRO-#
H

G

F

E

o

C

B

A

CR1-#--~::=F~~JI~1:!EjJ~il~~~~ii~J[~~[[~:!~~~~!]
COEFFICIENT
fJEGISTER 1

ENCR1-#
ENCRO-#

FIGURE 1. CONTROL LOGIC BLOCK DIAGRAM

4-2~

HSP48901

Initialization Register
The initialization register is used to appropriately configure
the convolver for a particular application. It is loaded
through the use of the CINO-7 bus along with the lD# Input. Bit 0 defines the input data and coefficients format
(unsigned or two's complement); Bit 1 defines the mode of
operation (1-Dor 2- D); and Bits 2 and 3 determine the type
of rounding to occur on the DOUTO-19 bus; The complete
definition of the initialization register bits is given in Table 1.
TABLE 1 •.INITIALIZATION REGISTER DEFINITION

The address decoder (See. Figure 1) is used for writing to
,the control logic of the HSP48901. Loading an internal register is done by selecting the destination register with the
AO-2 address lines, placing the data on CINO-7, and asserting lD# control line. When lD# goes high, the data on
CINO-7Is latched into the addressed register. The address
map for the AO-2 bus is shown in Table 2.

FUNCTION = Input & Coefficient
Data Format

0

Unsigned Integerformat

1

Two's complement format
FUNCTION = Operating Mode

BIT1

1-0 9-tap fllter

0

2-D 3 x 3 filter

1

3

BIT

2

FUNCTION = Output Rounding

0

0

No Rounding

0

1

Round to 16 bits (I.e. DOUT4-19)

1

0

Round to 8 bHs (i.e. DOUT12-19)

1

1

Not Valid

The nine coefficients mlJst !:Ie loaded sequentially over the
CINO-7 bus from A to I. The address of CREGO or CREG1
is placed on AO-2, arid then the coefficients are written to
the, corresponding coefficient register,one at a time by using
the lD# input.
Address Decoder

INITIALIZATION REGISTER

BITO

cient mask Is used to process the data. Thus, no clock
cycles have been lost when changing between alternate
3 x 3 filter kernels.

Coefficient Registers ~CREGO, CREG1)
The control logic contains' two coefficient register banks,
CREGO and CREG1. Each of these register banks Is capable of storing nine 8-bit filter coefficient values {3 x3
Kernel}. The output of the registers are connected to the
coefficient Input of the corresponding multiplier in the 3 x 3
multiplier array (designated A through I). The register bank
to be used for the convolution is selectable by writing to the
approprlte address (See address decoder). All registers In a
given bank are enabled simultaneously, and one of the
banks is always active.

While loading of the control logic registers is asynchronous
to ClK, the target· register in the control logic is being read
synchronous to the internal clock. Therefore, care must be
taken when modifying the convolver setup parameters during proceSSing to avoid changing the contents of the registers near a rising edge of ClK. The required setup time
relative to ClK is given by the specification TlCS. For example, in order to change the active coefficient register from
CREGO to CREG 1 during an active convolution operation, a
write will be performed to the address for selecting CREG1
for internal processing (AO-2 = 110). In order to provide
proper uninterrupted operation, lD# should be deasserted
at least TlCS prior to the next rising edge of ClK. Failure to
meet this setup time may result in unpredictable results on
the output of the convolver. Keep in mind that this requirement applies only to the case where changes are being
made in the control logic during, an active convolution operation. In a typical convolver configuration routine, where the
{configuration data is loaded prior to the actual conVolution
operation, this specification would not apply.
TABLE 2. ADDRESS MAP
CONTROL LOGIC ADDRESS MAP
A

For most applications, only one of the register banks is necessary. The user can simply load CFiEGOafier power up;
and use it for the entire CQnvolution operation. (CREGO is
the default register). The alternate register bank allows the
user to maintain two sets ,of filter coefficients and switch between them in real time. The coefficient masks are loaded
via the CINO-:r bus by using AO-2 and lD#. The selection
of the particular register bank to be used in proce$Slng is
also done by writing to the .approprlate address (See
address decoder). For example, if CREGO is being used to
provide coefficients to the multipliers, CREG1 can be
, updated at a low rate by an external processor; then, at the
proper time, CREG1 can be selected,so thaUhe new coeffi-

FUNCTION

2 1 0
0 0 0

Reserved for future use

0 0 1

Reserved for future use

0

1 0

Load Coefficient Register 0 (CREGO)

0

1 1

Load Coefficient Register 1 (CREG1)

1 0 0

Load Initialization Register (INT)

1 0 1

Select CREGO for Internal Processing

1 1 0

Select CREG1 for Internal Processing

1 1 1

No Operation

4-30

HSP489 0 1

Control Signals

8

20

Hold

DOUT 0 -19

The HOLD control input provides the ability to disable internal clock and stop all operations temporarily. HOLD is
sampled on the rising edge of ClK and takes effect during
the following clock cycle (Refer to Figure 2). This signal can
be used to momentarily ignore data at the input of the
convolver while maintaining its current output data and
operational state.

FILTERED
IMAGE
DATA

HSP48901

INITIALIZATION
DATA

ClK

.....J/

HOLD _ _ _ _

,'-------

INTERNAL

A

B

C

PM -l,N-1

PM -1,N

PM -l,N+ 1

D

E

F

PM,N -1

PM,N

PM,N+1

F

H

PM + l,N-1

PM+ l,N

PM+ l,N+ 1

CLOCK

FIGURE 2. HOLD OPERATION
ALTER KERNEL

FRAME#
The FRAME# input initializes all internal flip flops and registers except for the coefficient and initialization registers. It
is used as a reset between video frames and eliminates the
need to re-initialize the entire HSP489D1 or reload the coefficients. The registers and flip flops will remain in a reset
state as long as FRAME# is active. FRAME# is an asynchronous input and may occur at any time. However, it must
be deasserted at least tFS ns prior to the rising clock edge
that is to begin operation for the next frame in order to ensure the new pixel data is properly loaded.
Operation
A single HSP489D1 can be used to perform 3 x 3 convolution on 8-bit image data. A block diagram of this configurationis shown in Figure 3. The inputs of an external data
buffer (such as the HSP95DD) are connected to the input
data in parallel with the DIN1 (D-7) lines; the outputs of the
. data buffer are 'connected to the DIN2(D-7) bus. A second
external data buffer is connected between the outputs of the
first buffer and the DIN3(D-7) inputs. To perform the convolution,operation, a group of nine image pixels is multiplied
by the 3 x 3 array of filter coefficients and their products are
summed and sent to the output. For the example in figure 3,
the pixel value in the output image at location m,n is given
by:
DOUT(m,n) =

A x Pm-1,n-1 + B x Pm-1,n + C x Pm-1,n+1
+ 0 x Pm,n-1
+ E x Pm,n
+ F x Pm,n+1
+ GxPm+1,n-1 +HxPm+1,n +lxPm+1,n+1

IMAGE DATA

FIGURE 3. 3 x 3 KERNEL ON AN 8-BIT IMAGE

Multiple filter kernels can also be used on the same image
data using the dual coefficient registers CREGD and
CREG1. This type of filterIng Is used when the
characteristics of the input pixel data change over the
image in such a way that no one filter produces satisfactory
results for the entire image. In order to filter such an image,
the characteristics of the filter itself must change while the
image is being processed. The HSP489D1 can perform this
function with the use of an external processor. The
processor is used to calculate the required new filter
coeffiCients, loads them into the coefficient register not in
use, and selects the newly loaded coefficient register at the
proper time. The first coefficient register can then be loaded
with new coefficients in preparation for the next change.
This can be carried out with no interruption in processing,
provided that the new register is selected synchronous to
the convolver ClK signal.
The HSP489D1 can also operate as a one dimensional 9 tap
FIR filter by programming the initialization register to 1-D
mode (i.e. INT bit 1 = 'D'). This configuration will provide for
nine sequential input values to be multiplied by the coefficient values in the selected coefficient register .and provide
the proper filtered output The input bus to be used when
operating in this mode is the DIN1(D-7) inputs.
The equation for the output in the 1-D 9-tap FIR case becomes:

This process is continually repeated until the last pixel of the
last row of the image has been input. It can then start again
with the first row of the nextframe. The FRAME# pin is used
to clear the internal multiplier registers and DOUTD-19 registers between frames. The row length of the image to be
convolved is limited only by the maximum length of the external data buffers.
The setup is straightforward. The user must first setup the
HSP489D1 by loading a new value into the in itialization register. The coefficients can now be loaded one at a time from
A to I via the CIND-7 coefficient bus, and the AD-2 and lD#
control lines.

OOUTn =

Ax On-8 + B xOn-7 + C xOn-6 + 0 x On-5
+ Ex On-4 + F x On-3 + G x On-2 + H x Dn-1
+ IxOn

Frame Rate
The total time to process an image is given by the formula:
T= RxC/F
where:
T = Time to process a frame

4-31

R = number of rows in the image
C = number of pixels in a row
F = clock rate of the HSP489D1

...!:ia:
C'I)

;:;:
C

I
N

Specifications HSP48901
Absolute Maximum Ratings
Supply Voltage .....•..................•.•.•.........•..••••...............................••.•......•.......... +8.0V
Input, Output or 110 Voltage Applied .......•...•..•.......••.•................................•.• GND -0.5V to VCC +0.5V
Storage Temperature Range ....••.•.......•••••.•.•..............••..................••.....•.....••• -650 C to +1500 C
Gate Count .••.•.•• : ........•.••.••...•..••.•••••.......•.........................•.••...••......•••.... 1:3,594 Gates
Junction Temperature (TJ) . . . . . . . . • • . . . . • . • . . . . . • . . . • . • . . • • • • . . . . . . . . . . . . . . . . . . . . . . . . . • •. + 1500 C (PLCG), + 1750 C (PGA)
Lead Temperature (Soldering, Ten Seconds) .••.•••••••.............•.................•.•........................ +3000 C
ESD Classification ......••.•••••••..•.......................•••••...............•............•.••.........•••.. Class 1
CAUTION: Stresses above those listed ;n the 'IAbsolute Maximum Ratings l l may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range .....•.•••••...•.•••••••••..........••...•....•............••••...••.......•• +4.75V to +5.25V
Operating Temperature Range •.•..•.......••••..••...............•.................•.••...••......•••.••. OoC to + 700 C

D.C. Electrical Specifications (Vcc

= 5.0V ±

PARAMETER

5%, TA

= Ooc to +700 G)

SYMBOL

MIN

MAX

UNITS

Logical One Input Voltage

VIH

2.0

-

V

VCC

Logical Zero Input Voltage

VIL

-

0.8

V

VCC=4.75V

High Level Clock Input

VIHC

VCC
-0.8

-

V

VCC= 5.25V

Low Level Clock Input

VILC

-

0.8

V

VCC

Output HIGH Voltage

VOH

2.6

-

V

10H

Output LOW Voltage

VOL

-

0.4

V

Input Leakage Current
110 Leakage Current
Standby Power Supply Current

II

-10

10

fJA

10

-10

10

fJA

ICCSS

-

500

fJA

ICCOp

-

120

mA

TEST CONDITIONS

= 5.25V

= 4.75V
= -400fJA, VCC = 4.75V
10L = +2.0mA, VCC = 4.75V
VIN = VCC or GND, VCC = 5.25V
VOUT = VCC or GND, VCC = 5.25V
VIN = VCC or GND, VCC = 5.25V,
Outputs Open

Operating Power Supply Current

f = 20MHz, VIN = VCC or GND
VCC = 5.25V (Note 1)

Capacitance (TA = +250 C, Note 2)
PARAMETER
Input Capacitance
Output Capacitance

SYMBOL

MIN

MAX

UNITS

TEST CONDITIONS

CIN

-

10

pF

15

pF

FREQ = 1 MHz, VCC = Open, all measurements
are referenced to device ground.

Co

-

NOTES: 1. Power supply current is proportional to operating frequency.
Typical rating for ICCOp is 6mAlMHz.
2. Not tested. but characterized at initial design and at major
process/design changes.

CAUTION: These devices are sensitive to electrostatic discharge. Proper

Ie handling

4-32

procedures should be followed.

Specifications HSP489 0 1
A.C. Electrical Specifications

(Vcc

= 5.0V ± 5%, TA = Ooc to +700 C)
-30 (30M Hz)

PARAMETER

SYMBOL

MIN

MIN

MAX

UNITS

50

ns

0

-

TCYCLE

33

Clock Pulse Width High

TpWH

13

Clock Pulse Width Low

TpWL

13

Data Input Setup Time

TDS

14

Data Input Hold TIme

TDH

0

-

Clock Period

-20 (20MHz)

MAX

20
20
16

ns
ns
ns
ns

TOUT

-

21

-

30

ns

Address Setup Time

TAS

5

5

-

ns

Address Hold Time

TAH

2

2

TCS

10

12

-

ns

Configuration Data
Setup Time

-

Configuration Data
Hold Time

TCH

0

-

0

-

ns

LD# Pulse Width

TLPW

13

ns

TLCS

28

HOLD Setup Time

THS

10

HOLD Hold Time

THH

0

FRAME# Pulse Width

TFPW

TCYCLE

FRAME# Setup Time

TFS

28

-

20

LD# Setup Time

Output Rise Time

TR

Output Fall Time

TF

Clock to Data Out

-

TEST CONDITIONS

ns

40

-

ns

Note 2

8

-

8

ns

From 0.8V to 2.0V

8

-

8

ns

From 2.0V to 0.8V

40
12
0
TCYCLE

NOTES:
1. This specification applies only to the case where a change in the active
coefficient register is being selected during a convolution operation. It
must be met in order to achieve predictable results at the next rising clock
edge. In most applications, this selection will be made asynchronously.

and the T lCS specification may be disregarded.
2. While FRAME# is asynchronous wHh respect to ClK, it must be

ns

Note 1

ns
ns
ns

3. A.C. Testing is performed as follows: Input levels (ClK Input) = VCC -O.4V
and OV; Input levels (All other Inputs) = OV to 3.0V;
Input timing reforence levels: (ClK) = 2.5V, (Others) = 1.5V;
Other timing references: VOH?: 1.5V, VOL ~ 1.5V; Input rise and fall time.
driven at 1nsN; Output load per test load circuR with Cl = 4OpF.

begin loading new pixel data for the next frame.

1---------------

I
I
I
I
I
I
I
I
I

81
DUT~

'Clt
"INCLUDES STRAY AND
JIG CAPACITANCE

a:

ILl

!:i

u::

,

c

N

deasserted a minimum of T FS ns prior to the rising clock edge which is to

Test Load Circuit

Cf.I

I
I
I

i

1 5V
.

I

OL

I
I
I
I
I

I

i____ EQUIVALENT~IRCUrr _ _ _ _ j

SwHch 51 Open for ICCSB and ICCOp Tests

4-33

HSP48901
Timing Waveforms

ClK

LD#

DIN 0 -7

DOUT.O ~9

AOl!

TOUT~
..

-----------------------

CINO'1

---------------'

FUNCTIONAL TIMING

CONFIGURATION TIMING

INTERNAL
CLOCK

SYNCHRONOUS LOAD TIMING

HOLD TIMING

FRAME. TIMING

4-34

SIGNAL SYNTHESIZERS
PAGE

DATA SHEETS
HSP45116

Numerically Controlled Oscillator/Modulator ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

HSP45116/883

Numerically Controlled Oscillator/Modulator ..................................... 5-18

5-3

HSP45106

16 Bit Numerically Controlled Oscillator .........................................

5-26

HSP451 06/883

1 6 Bit Numerically Controlled Oscillator ..•..........................•...........

5-36

HSP45102

12 Bit Numerically Controlled Oscillator ....................•.................•.. 5-43

...
c-

(I)

cc

.... N

z(l)

Cl'"
_::r:

m!Z
~

5-1

mHARRIS

HSP45116
Numerically Controlled
Oscillator/Mod ulator

May 1991

Features

Description

• NCO and CMAC on One Chip

The Harris HSP45116 combines a high performance quadrature numerically controlled oscillator (NCO) and a high
speed 16-bit Complex Multiplier/Accumulator (CMAC) on a
single IC. This combination of functions allows a complex
vector to be multiplied by the internally generated (cos, sin)
vector for quadrature modulation and demodulation. As
shown in the block diagram, the HSP45116 is divided into
three main sections. The Phase/Frequency Control Section
(PFCS) and the Sine/Cosine Section together form a
complex NCO. The CMAC multiplies the output of the Sine/
Cosine Section with an external complex vector.

• 15MHz, 25.6MHz, 33MHz Versions
• 32-bit Frequency Control
• 16-bit Phase Modulation
• 16-bit CMAC
• O.008Hz Tuning Resolution at 33MHz
• Spurious Frequency Components

< -90dBc

• Fully Static CMOS
.145 Pin PGA

Appliclltions
• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, CAM
• Demodulation, PLL
• Phase Shifter
• Fast Fourier Transforms (FFT)

The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than O.008Hz at 33M Hz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC
multiplies this (cos, sin) vector by an external complex vector and can accumulate the result. The resulting complex
vectors are available through two 20-bit output ports which
maintain the 90dB spectral purity. This result can be accumulated internally to implement an accumulate and dump
filter.
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be downconverted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.

• Polar to Cartesian Conversions

Block Diagram
VECTOR INPUT

R

MICROPROCESSOR
INTERFACE
INDIVIDUAl
CONTROL SIGNALS

PHASE!
FREQUENCY
CONTROL
SECTION

SINE!
COSINE
ARGUMENT

SIN
SINE!
COSINE
SECTION

1 1
CMAC

COS

! !
R
VECTOR OUTPUT

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

5-3

File Number

2485.2

CI)

a:

LU

..... N

<:zCl)
c.::JLU
_::I:

CI) ....

:z
>-

CI)

HSP45116

Pinouts

145 PIN PGA
TOP VIEW
3

4

•

IMIN

IMIN

IMIN

IMIN

I.

IMIN

IMIN

IMIN

10

11

I.

12

13

14

15

10

10

10

10

GND

Vee

12

10

10

10

10

10

7

•

10

10

10

RO

GND

Vee

,.

10

10

18

14

11

8

10
17

10

10

10

13

8

8

A

Vee

IMIN

4

8

8

11

B

GND

IMIN

IMIN

IMIN

1

7

10

13

14

e

•

IMIN

RIN

RIN

IMIN

IMIN

2

3

1M IN
8

IMIN
12

IMIN
17

4

1

18

0

RIN

13

RIN
17

IMIN INDEX
0

10

RO

o

3

18

RO
17

E

RIN

RIN

RIN

10

14

18

10

RO

RO

E

0

18

F

RIN

RIN

RIN

11

12

RO

RO

I.
7

18

18

18

10

IMIN

18

2

I.

13

11
RO

G

Vee

RIN

8

8

•

12

10

H

GND

RIN

RO

RO

8

RIN
5

GND

RIN

RIN

RIN

3

1

4

K

RIN

RIN

SH

2

0

1

L

SH

ACO

""',
-#

0
M

'N....

REG

N

BINFMT

TICO

PACt

-#

-#

Vee

GND

EN""
-#

P

a

-#
-#

RO

RO

.MOD LOAD

-#

....... """""
-#

.N""" 'ENI

ENCF
REO

-#

""-

MODA
lIP'

-#

es

K

-#

1

3

OEI

RO

-#

-#

0

=-.-0

0......

DET

1

-#

0
GND

P

Vee

a

...,

oorr-

M

e

e

e

I.

8

2

e

e

•

e

e

e

OER

10

8

3

1

-#

GND

e

e

e

e

e

e

4

0

13

14

16

Vee

A

GND

I.

B

RIN

e
o

AD

1

8

8
RO

13

Vee

-#

2
DET

e

-#

4

RO

1
PACO

14

WR

-#

Vee

0

-#

3

RO

H

AD

eLK

-#

4

G

0""""'

1
0

7
RO

•

PEAK MOD

...

-#

8

B

e

RO

14
RO

RO

RIN

A

e

12
8

11

7

•

10

11

12

4

3

IMIN

IMIN

IMIN

IMIN

11

9

8

4

IMIN

IMIN
7

IMIN
5

IMIN

10
IMIN

IMIN

IMIN

RIN

2

18

N

BOTTOM VIEW

I.
11

10

10

10

15

1.

13

12

A

Vee

GND

10

10

10

12

B

10
2

10
6

10
7

10

10

'10

10

8

11

14

18

e

I.
,. "
8

Vee

18

GND
10

8

1M IN
18

IMIN

IMIN

IMIN

14

IMIN' IMIN
17 ' 12

1

RO

10

10

10

10

10

10

IMIN

18

1

4

8

9

13,

17

18

o

RO

RO

10

RIN

RIN

17

19

3

0

17

13

E

RO

RO

10

RIN

RIN

RIN

18

0

18

14

10

RO

RO

RO

RIN

RIN

RIN

11

13

14

12

11

7

G

RO

RO

RO

RIN

RIN

10

12

9

8

9

Vee

G

H

GND

RO
7

RO

RIN

•

RIN

GND

H

Vee

RO

RIN

RIN

4

RO
5

4

1

3

RO

RO

RO

SH

RIN

RIN

8

2

1

1

0

2

RO

DET

PACO

ACO

SH

1

-#

."."..

3
RO

OEI

0 ••. . ,

0

-#

-#

DET

OEOEXO"

0

-#

OU""'

GND

K

M

N

P

a

I.

Vee

15

8

3'

INDEX IMIN

8

8

MOD PEAK

-#

-#

0

-#

es

ENT_

PAel

TICO

-#

c""".

PM8a.

-#

-#

-#

GND

Vee

....

OUTIIaJ

e

e

e

e

AD

0

1

2

8

13

14

OER

e

e

e

e

e

e

AD

-#

1

3

8

9

10

I.

0

1

e

e

e

e

e

e

GNO.

WR

eLK

4

5

7

11

12

Vee

0
14

13

12

11

10

8

5-4

.N...

"'"-#
EN""
"""-#

MO""

"P'
-#

REO

1
LOAD MOD

-#

.ENI

-#

-#

8

4

EN"''''
-#
3

-#
•• NHIT

F

RIN

0

-#

E

K

L
M
N
p

a

HSP45116

Pin Description
NAME

NUMBER

VCC

A1,A9,A15,G1,
J15, a1, 07, 015

TYPE
+5 Power supply input

GND

A8,A14,B1,H1,
H15, P15, 02, a8

Power supply ground input

CO-15

N8-11,P8-13,
09-14

ADO-1
CS#

DESCRIPTION

I

Control input bus for loading phase and frequency,data into the PFCS. C15 is the MSB.

N7,P7

I

Address pins for selecting destination of CO-1 5 data

P6

I

Chip select (Active low)

WR#

a6

i

Write enable. Data is clocked into the register selected by ADO-1 on the rising edge of
WR# when the CS# line is low.

ClK

05

I

Clock. All registers, except the control registers clocked with WR#,are clocked (when
enabled) by the rising edge of ClK.

ENPHREG#

M1

I

Phase register enable. (Active low) Registered on Chip, by ClK. When active, after being
clocked onto chip, ENPHREG# enables the clocking of data into the phase register.

ENOFREG#

N1

I

Frequency offset register enable.-(Active low) Registered on chip by ClK. When active,
after being clocked onto chip, ENOFREG# enables clocking of data into the frequency
offset register.

ENCFREG#

N5

I

Center frequency register enable. (Active low) Registered on chip by ClK. When active,
after being clocked onto- chip, ENCFREG# enables clocking of data into the center
frequency register.

ENPHAC#

03

I

Phase accumulator register enable. (Active low) Registered on chip by ClK. When active,
after being clocked onto chip, ENPHAC# enables clocking of the phase accumulator
register.

ENTIREG#

P5

I

Time interval control register enable. (Active low) Registered on chip by ClK. When active,
after being clocked onto chip, ENTIREG# enables clocking of data into' the time
accumulator register.

ENI#

a4

I

Real and imaginary data input register (RIR, IIR) enable. (Active low) Registered on chip by
ClK. When active, after being clocked onto chip, ENI# enables clocking of data into the
real and imaginary input data register.

MODPV
2P/#

N6

I

Modulo n/2n select. When low, the Sine and Cosine ROMs are addressed modulo 2n (360
degrees). When high, the most significant address bit is held low so thaI- the ROMs are
addressed modulo n (180 degrees). This input is registered on chip by clock.

ClROFR#

P4

I

Frequency offset register output zero. (Active low) Registered on chip by ClK. When active,
after being clocked onto chip, ClROFR# zeros the data path from the frequency offset
register to the frequency adder. New data can still be clocked into the frequency offset
register; ClROFR# does not affect the contents of the register.

lOAD#

N4

I

Phase accumulator load control. (Active low) Registered on chip by ClK. Zeroes feedback
path in the phase accumulator without clearing the phase accumulator register.

MODO-1

M3,N3

I

External modulation control bits. When selected with thePMSEl line, these'bits add a 0,90,
180, or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits
of the phase control path are set to, zero.
These bits are loaded into the phase register when ENPHREG# is low.

PMSEl

P3

I

Phase modulation select line. This line determines the source of the data clocked into the
phase register. When high, the--phase control register is selected. When low, the external
modulation pins (MODO-1) are selected, for the most Significant two bits and the least
significant two bits and the least significant 14 bits are set to zero. This control is registered
byClK.

RBYTllD#

l3

I

ROM bypass, timer load. Active low, Registered by ClK. This input bypasses the sinel
cosine ROM so that the 16 bit phase adder output and lower 16 bits of the phase
accumulator go directly to the CMAC's sine and cosine inputs, respectively. It also enables
loading of the timer accumulator register by zeroing the feedback in the accumulator.

5-5

en

a:
W

.... N

cCzen

w
Cl
_:x:

en

IZ

~

HSP45116
Pin Description
NAME

(Continued)

NUMBER

TYPE

DESCRIPTION

PACI#

P2

I

Phase accumulator carry Input. (Active 'low) A low on this pin' causes the phase
accumulator to increment by one In addition to the values In the phase accumulator
register and frequency adder.

PACO#

L13

0

Phase accumulator carry output Active'low and registered by Cll<. A low on this output
indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle
has been reached.

TICO#

P1

0

Time interval accumulalor carry output Active low, registered by ClK. This output goes low
when a carry is generated by the time interval accumulator. This function is provided to time
out control events such as synchronizing register clocking to date timing.

RINO-18

C1, C2, 01, 02,
E1-3, F1-3,
G2,G3,H2,
H3, J1-3, K1, K2

I

Real input data bus. This is the external real coniponent into the complex multiplier. The bus
is clocked into the real input data register by ClK when ENI# is asserted.

IMINO-18

A2-7,B2-7,
C3-8,03

I

Imaginary input data bus. This is the external imaginary component into the complex
multiplier. The bus is clocked into the real input data register by ClK when ENI# is
asserted.

SHO-1

K3,L1

I

Shift control Inputs. These lines control the input shifters of the RIN and liN inputs of the
complex'multiplier. The shift controls are common to the shifters on both ofthe busses.

ACC

l2

I

Accumulate/dump control. This input controls the complex accumulators and their holding
registers. When high, the accumulators accumulate and the holding registers are disabled.
When low, the feedback in ihe accumulators is zeroed to cause the accumulators to
load.
The holding registers are enabled to clock in the results of the accumulation. This input is
registered by ClK

BINFMT#

N2

I

This input is used to convert the two's complement output to offset binary (unsigned) for
applications using O/A converters. When low, bits R019 and 1019 are inverted from the
Internal two's complement representation. This Input Is registered by ClK

PEAK#

M2

I

This input enables the peak detect feature of the block floating point detector. When high,
the maximum bit growth In the output holding registers Is encoded and output on the
OETO-1 pins. When the PEAK# input ia asserted, the block floating point detector output
will track the maximum growth in the holding registers, Including the data in the holding
registers at the time that PEAK# is activated.

OUTMUXQ-1

N12,N13

I

These inputs selectthe data to be output on ROO-19 and 100-19.

ROO-19

C15, 014, 015
E14, E15, F13-15,
G13-15, H13, H14,
J13,J14;K13-15,
l15,M15

0

Real ,output data bus. These three state outputs are controlled by OER# and OEREXT#.
OUTMUXO-1 select the data output on the bus.

100-19

A10-13, B8-15,
C9-14, 013, E13

0

Imaginary output data bus.These three state outputs are controlled by OEI# and OEIEXT#.
OUTMUXO-1 select the data output on the bus.

DETO-1

N15,L14

0

These output pins indicate the number of bits of growth in the accumulators. While PEAK#
is low, these pins indicate the peak growth. The detector examines bits 15-18, real
and Imaginary accumulator holding registers and bits 30-33 of the real and imaginary
CMAC holding registers. The bits indicate the largest growth ofthe four registers.

OER#

P14

I

T~ree state control for bits ROO-15• .outputs are enabled when the line Is low.

OEREXT#

M13

I

Three state control for bits R016-19. Outputs are enabled when the line is low.

OEI#

M14

I

Three state control for bits 100-15. Outputs are enabled when the line is low.

OEIEXT#

N14

I

Three stete control for bits 1016-19. Outputs are enabled when the line is low.

5-6

HSP45116
Functional Description

Phase and Frequency Control Section

The Numerically Controlled Oscillator/Modulator (NCOM)
produces a digital complex sinusoid waveform whose
amplitude, phase and frequency are controlled by a set of
input command words. When used as a Numerically
Controlled Oscillator (NCO), it generates 16 bit sine and
cosine vectors at a maximum sample rate of 33MHz. The
NCOM can be preprogrammed to produce a constant (CW)
sine and cosine output for Direct Digital Synthesis (DDS)
applications. Alternatively, the phase and frequency inputs
can be updated in real time to produce a FM, PSK, FSK, or
MSK modulated waveform. The Complex Multiplier/
Accumulator (CMAC) can be used to multiply this waveform
by an input signal for AM and QAM signals. By stepping the
phase input, the output of the ROM becomes an FFT
twiddle factor; when data is input to the Vector Inputs (see
Block Diagram), the NCOM calculates an FFT butterfly.

The phase and frequency of the internally generated sine
and cosine are controlled by the PFCS (Figure 1). The PFCS
generates a 32 bit word that represents the current phase of
the sine and cosine waves being generated: the Sine/
Cosine Argument. Stepping this phase angle from
o through full scale (232 - 1) corresponds to the phase
angle of a sinusoid starting at 0 0 and advanCing around the
unit circle counterclockwise. The PFCS automatically
increments the phase by a preprogrammed amount
on every rising edge of the external clock. The frequency of
the two sinusoid is determined by the number of clocks it
takes for the phase to step through its full range. For example, if the NCOM is clocked at 30M Hz, and the PFCS is program med with an incremental phase of n/2, it takes 4 clocks
for the phase to step through a full cycle; the output frequency is 30MHz/4, or 7.5MHz.

As shown in the Block Diagram, the NCOM consists of
three parts: Phase and Frequency Control Section (PFCS),
Sine/Cosine Generator, and CMAC. The PFCS stores the
phase and frequency inputs and uses them to calculate the
phase angle of a rotating complex vector. The Sine/Cosine
Generator performs a lookup on this phase and outputs the
appropriate values for the sine and cosine. The sine and
cosine form one set of inputs to the CMAC, which multiplies
them by the Input vector to form the modulated output.

The PFCS is divided into 2 sections: the Phase Accumulator
uses the data on CO-15 to compute the phase angle that is
the input to the Sine/Cosine Section (Sine/Cosine
Argument); the Time Accumulator supplies a pulse to mark
the passage of a preprogrammed period of time.
The Phase Accumulator and Time Accumulator work on the
same principle: a 32 bit word is added to the contents of a
32 bit accumulator register every clock cycle; when the sum

CLK_-....._--II---PACO#

PHASE
ADDER

18 LSB'.
CLK

32
PHASE
ACCUMULATOR
PACI#"

-;@=ffi
§

ADO
CS#"
WR#"

ENCFREG#"
ENOFREG#"
CLROFR#"
LOAD#"
PMSEL
ENPHREG#
ENPHAC#
MODPIf2PI#"

~

REG

PHEN#"
MSEN,#"
LSEN#"

32

TIME
INCREMENT

R.ENCFREG#"
R.ENOFREG#
R.CLROFR#
R.LOAD#"
R.PMSEL
R.ENPHREG#"
R.ENPHAC#
R.MODPIJ2PI

TIME
ACCUMULATOR

I TICO#
I
I
I
I
I
I
I

1 _ _ _ _ _ _ _ _ _ _ _ _ _ --'

ClK

FIGURE 1. PHASE/FREQUENCY CONTROL SECTION BLOCK DIAGRAM

5-7

HSP45116
causes .the adder tooverflow,the accumulation continues
with the 32 bits of the adder going Into the accumulator
register. The overflow bit is'used as an outputto Indicate the
timing 'of the accumuiation 'overflows. In the Time
Accumulator, tlie overflow bit generates TICO#, the Time
Accumulator carry out (which is the only output of the Time
Accumulator). In the Phase Accumulator, the overflow Is
inverted to generate the Phase Accumulator Carry Out,
PACO#.
The output of the Phase Accumulator goes to the Phase
Adder, which adds an offset to the top 16 bits of the phase.
This 32 bit number forms the argument of the sine and
cosine, which is passed to the Sine/Cosine Generator.
Both' accumulators are loaded 16 bits at a time over the
CO'-15 bus. Data on CO-15 is loaded Into one ofthiHhree
input registers when CS# and WR# are low. The data in the
Most Significant Input Register and Least Significant Input
Register forms a 32 bit word that is the input to the Center
Frequency Register, Offset Frequency Register and Time
Accumulator. These registers are loaded by enabling the
proper register enable signa]; for example, to load the
Center Frequency Register, the data Is loaded into the LS
and MS Input Registers, and ENCFREG# Is set to zero; the
next rising edge of CLK will pass the registered version of
ENCFREG#,R.ENCFREG#, to the clock enable of the
Center Frequency Register; this register then gets loaded
on the following rising edge of CLK. The contents of the
Input Registers will be continuously loaded into the Center
Frequency Register as long as R.ENCFREG# is low.
The Phase Register is loaded In a similar manner. Assuming
PMSEL Is low, the contents of the Phase Input Register is
loaded into the Phase Register on every rising clock edge
that R.ENPHREG Is low. If PMSE:L is high, MODO-1 supply
the two most Significant bits Into the Phase Register (MOD1
is the MSB) and the I,east significant 14 bits are loaded with
O. When PMSEL Is high, MODO-1 are used to generate a
Quad Phase Shift Keying (QPSK) signal (Table 2).

PSK modulation schemes. These three values are used by
the Phase Accumulator and Phase Adder to form the phase
of the Internally generated sine and cosine.
The sum of the values in Center and Offset, Frequency
Registers corresponds to the desired phase increment
(modulo 232) from one clock to the next. For example, loading both registers with zero ,will cause the Phase
Accumulator to add zero to Its current output; the output of
the PFCS will remain at its current value; i.e., the output of
the NCOM will bea DC signal. H a hexadecimal 00000001
Is loaded Into the Center Frequency Control Register, the
output of the PFCS will increment by one after every clock.
This will step through every location in the Sine/Cosine
,Generator, so that the output will be the lowest frequency
above DC that can be generated by the NCOM, i.",., the
clock frequency divided by 232. If the input to the Center
Frequency Control Register is hex 80000000, the PFCS will
step through the Generator with half of the maximum step
size, so that frequency of the output waveform will be half of
the sample rate.'
The operation of the Offset Frequency Control Register Is
Identical to that of the Center Frequency Control Register;
having two separate registers allows the user to generate an
FM signal by loading the carrier frequency in the Center
Frequency 'Control Register and updating the Offset
Frequency Control Register with ,the value of the frequency
offset - the difference between the carrier frequency and
the frequency of the output signal. A logic low on
CLROFR# disables the outpuf of the Offset Frequency
Register without clearing the contents of the register.
TABLE 2. MODo-1 DECODE,

TABLE 1. ADO-1 DECODING
AD1

ADO

CS#

WR#

FUNCTION

0

0

0

t

Load least significant bits of
frequency input

0

1

0

t

Load most significant bits of
frequency input

1

0

0

t

Load phase register

1

1

X

X

Reserved

MOD1

MODO

PHASE SHIFT (DEGREES)

0

0

0

0

1

90

1

0

270

1

1

180

Initializing the Phase Accumulator Register is done by
putting a low on the LOAD# line. This zeroes the feedback
path to the accumulator, so that the register is loaded with
the current value of the phase increment summer on the
next clock.

The final phase value going to the Generator can be adJusted using MODPI/2PI# to force the range of the phase to
be 0 0 to 1800 (modulo n) or 0 0 to 3600 (modulo 2n).
X
X
1
X
Reserved
Modulo 2n Is the mode used for modulation, demodulation,
, direct digital synthesis, etc. Modulo n Is used to calculate
The Phase Accumulator consists of registers and adders FFTs. This is explained in greater detail in the Applications
that compute the value of. the current phase at every clock. It section.
has three inputs: Center Frequency, which corresponds to
the carrier frequency ota signal; Offset Frequency, which Is The Phase Register adds an offset to the output of the
the deviation from the Center Frequency; and Phase, which Phase Accumulator. Since the Phase Register is, only 16
is a 16 bit number that is added ,to the current ,c phase for bits, It Is added to the top 16 bits of the Phase AccumUlator.

5-8

HSP45116
The Time Accumulator consists of a register which is
incremented on every clock. The amount by which it
increments is loaded into the Input Registers and is latched
into the Time Accumulator Register on rising edges of ClK
while ENTIREG# is low. The output of the Time
Accumulator is the accumulator carry out, TICO#. TICO#
can be used as a timer to enable the periodic sampling of
the output of the NCOM. The number programmed into this
register equals 232 x ClK period/desired time interval.
TICO# is disabled and its phase Is initialized by zeroing the
feedback path of the accumulator with RBYTllD#.

Sine/Cosine Section
The Sine/Cosine Section (Figure 2) converts the output of
the PFCS into the appropriate values for the sine and
cosine. It takes the most significant 20 bits of the PFCS
output and passes them through a look up table to form the
16 bit sine and cosine inputs to the CMAC.

32r-_---..~

r - -_ _ _

"

Complex Multiplier/Accumulator
The CMAC (Figure 3) performs two types of functions:
complex multiplication/accumulation for modulation and
demodulation of digital signals, and the operations necessary to implement an FFT butterfly. Modulation and
demodulation are implemented using the complex mUltiplier and its associated accumulator; the rest of the circuitry in
this section, i.e., the complex accumulator, input shifters
and growth detect logic are used along with the complex
multiplier/accumulator for FFTs. The complex multiplier
performs the complex vector multiplication on the output of
the Sine/Cosine Section and the vector represented by the
real and Imaginary inputs RIN and liN. The two vectors are
combined In the following manner:
ROUT = COS x RIN - SIN x liN
lOUT COS x liN + SIN x RIN

=

RIN and liN are latched into the input registers and passed
through the shift stages. Clocking of the Input registers is
enabled with a low on ENI#. The amount of shift on the
latched data is programmed with SHO-1 (Table 3). The output of the shifters is sent to the CMAC and the auxiliary accumulators.
TABLE 3. INPUT SHIFT SELECTION

....._...
Q

SH1

SHO

SELECTED BITS

0

0

RINO-15,IMINO-15

0

1

RIN1-16,IMIN1-16

1

0

RIN2-17,IMIN2-17

1

1

RIN3-18,IMIN3-18

11-+-_ _ _----'

RB;LD:r=tD

eLK

CLK __L -________

~

FIGURE 2. SINE/COSINE SECTION

The 20 bit word maps into 2" radians so that the angular
resolution is 2"/220. An address of zero corresponds to 0
radians and an address of hex FFFFF corresponds to 2"(2"/2 20) radians. The outputs of the Generator section are
2's complement sine and cosine values. The sine and
cosine outputs range from hexadecimal 8001, which
represents -1, 'to 7FFF, which represents +1. Note that the
normal range for two's complement numbers is 8000 to
7FFF; the output range of the NCOM is scaled by one so
that it is symmetriC about O.

The 33 bit real and imaginary outputs of the Complex
Multiplier are latched in the Multiplier Registers and then go
through the accumulator section of the CMAC. If the ACC
line Is high, the feedback to the accumulators is enabled; a
low on ACC zeroes the feedback path, so that the next set
of real and imaginary data out of the complex multiplier is
stored In the CMAC Output Registers.
The data in the CMAC Output Registers goes to the
Multiplexer, the output of which Is determined by the
OUTMUXO- 1 lines (Table 4). BINFMT# controls whether
the output of the Multiplexer is presented In two's
0 inverts
complement or unsigned format; BINFMT#
ROUT19 and IOUT19 for unsigned output, while BINFMT#
= 1 selects two's complement

The sine and cosine values are computed to reduce the
amount of ROM needed. The magnitude of the error in the
computed value of the vector is less than -90.2dB. The error
in the sine or cosine alone is approximately 2dB better.
If RBYTllD# is low, the output of the PFCS goes directly to
the inputs of the CMAC. If the real and imaginary inputs of
the CMAC are programmed to hex 7FFF and 0 respectively,
then the output of the PFCS will appear on output bits 0
through 15 of the NCOM with the output multiplexers set to
bring out the most significant bits of the CMAC output
00). The most significant 16 bits out of the
(OUTMUX
PFCS appears on IOUTO-15 and the least significant bits
come out on ROUTO-15.

=

5-9

=

TABLE 4. OUTPUT MULTIPLEXER SELECTION
OUT
MUX
1

OUT
MUX
0

0

0

Real
CMAC
31-34

RealCMAC Imag
15-30
CMAC
31-34

ImagCMAC
15-30

0

1

Real
CMAC
31-34

O,Real
CMAC
0-14

O,lmag
CMAC
0-14

1

0

RealAcc' RealAcc
16-19
0-15

ImagAcc ImagAcc
16-19
0-15

1

1

Reserved Reserved

Reserved Reserved

R016-19

ROO-15

1016-19

Imag
CMAC
31-34

100-15

Cf.I

II:
W

.... N
cC
zCf.l

c:s W
_:z:

Cf.I!z
~

HSP45116

R.ENI.#

--..,...--4----,

R.SHO -1 -_..,...--/_ _--,

SIN
COMPLEX
MULTIPlIER

o
COMPLEX
ACCUMULATOR

Rl.ACC _ . l -_ __+=---+=-~-..L.---------'---_+=--------...J

IOUT16 -19

ENI.#

R.ENI.#

SHO-l

R.SHO -1

Rl.ACC

ACe

PEAK.#

FIGURE 3. COMPLEX MUlTIPUER/ACCUMULATOR; All REGISTERS CLOCKED BY ClK

5-10

IOUTO -15

HSP45116
The Complex Accumulator duplicates the accumulator in
the CMAC. The input comes from the data shifters, and its
20 bit complex output goes to the Multiplexer. ACC controls
whether the accumulator is enabled or not OUTMUXO-1
determines whether the accumulator output appears. on
ROUT and lOUT.

while the binary point of ROUT and lOUT is to the right of
the fifth most significant bit. These CMAC external
input and output busses are aligned with each other to
facilitate cascading NCOM's for FFT applications.
TABLE 5. GROWTH ENCODING

The Growth Detect circuitry outputs a two bit value that
signifies the amount of growth on the data in the CMAC and
Complex Accumulator. Its output, DETO-1, is encoded as
shown in Table 5. If PEAK#" is low, the highest value of
DETO-1 is latched in the Growth Detect Output Register.

DET1

DETO

NUMBER OF BITS OF GROWTH ABOVE 2 0

0

0

0

The relative weighting of the bits at the inputs and outputs of
the CMAC is shown in figure 4. Note that the binary point of
the sine and cosine is to the right of the most significant bit,

0

1

1

1

0

2

1

1

3

SIN/COS INPUT
15

14

13

12

11

I I I I I

10

9

8

7

6

5

4

3

2

o

2

o

-20 . 2-1

t
Radix Point

COMPLEX MULTIPLIER/ACCUMULATOR INPUT (RIN, liN)
SH =00
15

14

-20 . 2-1

I I I I I I I I

13 112 111 110
2-2

2-3

2-4

2-5

9

8

7

2-6

2-7

2-8

6

5

4

3

2-9 2-10 2-11 2-12 2-13 2-14 2-15

t
Radix Point

COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (ROUT, lOUT)
OUTMUX=OO
19

18

17

16 115 114 113 112 111 110

-24

23

22

21

20 .2-1. 2-2

2-3

2-4

2- 5

I I I I I I I
9

8

7

6

2-6

2-7

2-8

2-9

5

4

3

2

o

2-10 2-11 2-12 2-13 2-14 2-15

t
Radix Point

COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (ROUT, lOUT)
OUTMUX = 01
19

18

17

16 115 114 113 112 111 110

I I I
9

8

71 6

I I
5

41 3

2

o

5

4

2

o

COMPLEX ACCUMULATOR OUTPUT (ROUT, lOUT)
OUTMUX = 10
19

18

17

16

15

-24

23

22

21

20. 2-1

14 113 112 111 110
2-2

2-3

2-4

2-5

I I I I I
9

8

7

6

2-6

2-7

2-8

2-9

t
Radix Point

FIGURE 4. BIT WEIGHTING

5-11

3

2-10 2-11 2-12 2-13 2-14 2-15

HSP45116
Applications
The NCOM can be used for Amplitude, Phase and
Frequency .modulation, as well as in variations and
combinations of these techniques, such as QAM. It is most
effective in applications requiring multiplication of a rotating
complex sinusoid .by an external vector. These include AM
and QAM modulators and digital receivers. The NCOM
implements AM and QAM modulation on a single chip, and
is a element in demodulation, where it performs complex
down conversion. It can be "combined with the Harris
HSP43220 DeCimating Digital Filter to form the front end of
a digital receiver.

eLK
1 _______ _

Modulation/Demodulation
'Figure 5 shows a block diagram of an AM modulator. In this
example, the phase increment for the carrier frequency is
loaded into the center frequency register, and the modulating input is clocked into the real input of the CMAC, with the
imaginary input set to O. The modulated output is obtained
at the real output of the CMAC. With a sixteen bit, two's
complement Signal input, the output will be a 16 bit real
number, on ROUTO-15 (with OUTMUX = 00).
SIGNAl. INPUT

FIGURE 6.'QUADRATURE AMPLITUDE MODULATION IQAM)

Frequency Control Section, the frequency tuning resolution
equals the clock frequency divided by 232. For example, a
25MHz clock gives a tuning resolution of 0.006Hz.
The NCOM also works with the HSP43220 DeCimating Digital Filter to Implement down conversion and low pass filterIng In a digital receiver (Rgure 7). The NCOM performs
complex down conversion on the wideband input signal by
multiplying the input vector and the internally generated
complex sinusoid. The resulting signal has components at
twice the center frequency and at DC. Two HSP43220's,
one each on the real and imaginary outputs of the
HSP45116, perform low pass filtering and decimation on
the down converted data, resulting in a complex baseband
signal.
HSP45116
NCOM

cos

HSP43220
DDF

(wt)

FIGURE 5. "AMPLITUDE MODULATION

By replacin.g the real.input with a complex vector, a similar
setup can generate'QAM signals (Figure 6). In this case, the
carrier frequency is loaded into the center frequency register as before, but the modulating vector now carries both
amplitude and phase Information. Since the input vector
and the internally generated sine and cosine waves are both
'16 bits, the number-of states is onlY'limited by the characteristics of the transmission medium and by the analog electronics in the transmitter and receiver.

SAMPLED
INPUT
DATA

The phase and amplitude resolution for the Sine/Cosine
section (16 bit output), delivers a spectral purity of greater
than 90dBc. This means that the unwanted spectral components due to phase uncertainty (phase noise) will be greater
than 90dS below the desired output (dBc, decibels below
the carrier). With a 32 bit phase accumulator in the Phase/

5-12

INPUT·

DDF
OUTPUT

NCOM
OUTPUT

niL
o

20 MHz

0

,FIGURE7. CHANNELIZED RECEIVER CHIP SET

HSP45116
FFT Butterfly
Figure 8 shows a Fast Fourier Transform (FFT) implementation. The FFT is a highly efficient way of calculating the Discrete Fourier Transform (1). The basic building block in
FFTs is called the butterfly. The butterfly calculation involves adding complex numbers and multiplying by complex sinusoids. The Phase/Frequency Control Section and
Sine/Cosine Generator provide the complex sinusoids and
the CMAC performs the complex multiplies and adds.

B~
~

B,A

B,A

ACC

CMAC calculates (A - B)Wk as AWk + B(_Wk). -Wk is generated by phase shifting the ROM address 180 degrees using the phase modulation inputs. For radix-2 decimation in
frequency FFTs, the phase of the complex sinusoid starts at
o degrees and increments by a fixed step size (for each
pass) after each butterfly. The phase/frequency section is
initialized to" 0 degrees and the frequency control loaded
with the appropriate phase step size for the pass. The resulting words, A' and B', are held in output registers and
multiplexed through the output pins for writing to memory.
Using a single NCOM clocked at 25MHz, a 1024 point
radix-2 FFT can be computed in (ClK .period) x (N1092N),
or 410 microseconds..
A ...,..._ _ _ _ _ _ _ _ _- - . . . . . " . . . _ - - _ - -... A'

-

-

--

~

CMAC

R

-

r--

--""----+;:--_ B'

B ""'-_ _ _ _ _ _ _ _ _
- 1

T wK

T
ROM

so,o

MOD

FIGURE 9. DECIMATION· BY FREQUENCY BUTTERFLY

..

f
• ; SEQUENCER

A'=A+B
B'={A. B)W K
RGURE 8. RADIX-2 FFT BUTTERFLY

The NCOM circuit shown implements the butterfly sbown in
Figure 9. The two complex inputs A and B produce two
complex outputs A' and B' using the equations A' = A + B,
B'
(A - B)Wk where Wk
e-jwk
cos(wk) + jsin(wk).
Two clock cycles are required to calculate the butterfly. A is
clocked into the chip first and then B" is clocked in. The complex accumulator in the CMAC section adds A and B. The

=

=

wk

=

Circuitry is included to implement block floating point FFTs.
In block floating point, an exponent is generated for an entire block of data. To implement block floating point, the
maximum bit growth during a set of calculations is detected. The number "of bits of growth is used to adjust the
block's exponent and to scale the block on the next set of
calculations to" maintain a desired-number of bits of precision. This technique requires less memory than true floating
point and yields better performance than fixed point implementations, though its resolution does not meet that of true
floating point implementations.
References
(1) Oppenheim, A. V. and Schafer, R. W., Discrete Time
Signal Processing, Prentice Hall

5-13

rn

a:
.....

.... N

cCzrn
c:I
.....
_x

en

I-

z

rn

Specifications HSP45116
Absolute Maximum Ratings
Supply Voltage •.•••••••••••••• , ••••••• '•.••••••••..•••••••••••••••••••••.•.•••.•••••••••••••••.•••••..••..•••••• +8.0V
Input, Output orl/O Voltage Applied •••• ' ••.•......•••••••••.••..•.•••••••••••••.•••••••.•••••.••• GND -0.5Vto VCC +0.5V
Storage Temperature Range. " ••••••••••.••.••..••••••••••••...•••• , • " •.•.••..•••• , •.•.••••••..••••. -650 C to +1500C
Maximum Package Power Dissipation .•....•.....•.........., ....•..................•... '" •....• '•••••••••••.••.•.• ~ 2.16W
9jc .•..• '....... '. '••••••••.•••..•.• : ..........•.••.••••.••.•.•.•.•..•••••••••••••••••..••••.•••• .' • • • • • . • • • • . .. 8.30 C/W
9ja •••..•••..•••••..•...•.••...•.•...•••••••••••.. : ..••.••.•••••..•.•..•.••.•••.•.•••••.••••••••••..••.••.. 23.1 o C/W
Component Count ••••••••••••••...••.•..•••.. ; •...••••.. '. • • • . • • • • • . • • . • . . . • • • . • • • . . . • • • . • • • . • . • • •• 103,000 Transistors
Junction Temperature ...••.••••.•.•••.• ; ........... , '" .••••..•.•••••.•..•.• , ••...••••••••••••.•••••• : ••.•••.•• +1750 C
Lead Temperature (Soldering, Ten Secondsi ••••. " ••..••••••••...••...••.•.•..••••••••••••••••••.•••.•...•••...• +3000C
ESD Classification ••..•.••.•••••••••••.•••••.•••.... '••••.••••..••.•.••..........••. '............................. Class 1
cAurioN: Stresst:ti above those listecJ in the uAbsolute Maximum Ratings" may cause permanent damage to the device. This is a stress only fating
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

and

Operating Conditions
Operating Voltage Range ••••.•••.•.•••.•..•.•..••••.•...............• " ..•...•.•..•••..•.•...•.••••.. +4.75V to +5.25V
Operating Temperature Range •••.•••••••••••••••••••.•••••••••..••......•••.••••..••... ',' •.•.••..•.••••.. OoC to + 700C

D.C. Electrical Specifications
SYMBOL
VIH

PARAMETER
Logical One Input Voltage

MIN

MAX

UNITS

2.0

-

V

TEST CONDITIONS
VCC =5.25V

-

0.8

V

VCC=4.75V

3.0

-

V

VCC= 5.25V

Low Level Clock Input

-

0.8

V

VCC=4.75V

VOH

Output HIGH Voltage

2.6

-

V

IOH = -400flA, VCC = 4.75V

VOL

Output LOW Voltage

VIL

Logical Zero Input Voltage

VIHC

High Level Clock Input

VILe

-

0.4

V

IOL = +2.0mA, VCC = 4.75V

II

Input Leakage Current

-10

10

flA

VIN = VCC or GND, VCC = 5.25V

10

I/O Leakage Current

-10

10

flA

VOUT = VCC or GND,
VCC= 5.25V

ICCSB

Standby Power Supply Current

-

500

flA

VIN=VCCorGND
VCC = 5.25V, Note 3

ICCOp

Operating Power Supply Current

-

150

mA

f= 15MHz, VIN =VCC orGND
VCC = 5.25V, Notes 1 and 3

Capacitance (TA = +250 C, Note 2)
MIN

MAX

UNITS

CIN

Input Capacitance

-

15

pF

Co

Output Capacitance

-

15

pF

SYMBOL

PARAMETER

TEST CONDITIONS
FREQ = 1 MHz, VCC = Open,
All measurements are referenced
to device ground

NOTES:
1. Power supply current is proportional to operating frequency. Typical
rating for ICCOp is 10mNMHz.

3. Output load per test load circuit with switch open and CL = 40pF.

2. Not tested, but characterized at initial design and at major process/design
changes.

5-14

Specifications HSP45116
A.C. Electrical Specifications (Note 1)
-15(15MHz)
SYMBOL

PARAMETER

MIN

-25 (25.6 MHz)

MAX

MIN

MAX

-33 (33MHz)
MIN

MAX

UNITS

TCp

CLKPeriod

66

39

30

ns

TCH

CLKHigh

26

15

12

ns

TCL

CLKLow

26

15

12

ns

TWL

WR#Low

26

15

12

ns

TWH

WR#High

26

15

12

ns

TAWS

Set-up Time; ADO-1,
CS# to WR# going high

18

13

13

ns

TAWH

Hold Time; ADO, AD1,
CS# from WR# going high

0

0

0

ns

TCWS

Set-up Time CO-15
from WR# going high

20

15

15

ns

TCWH

Hold Time CO-15 from
WR# going high

0

0

0

ns

TWC

Set-up time WR# high to
CLKhigh

20

16

12

ns

TMCS

Set-up Time MOOO-1 to
CLK going high

20

15

15

ns

TMCH

Hold Time MOOO-1 from
CLK going high

0

0

0

ns

TpCS

Set-up Time PACI# to CLK
going high

25

15

11

ns

TPCH

Hold Time PACI# from CLK
gOing high

0

0

0

ns

TECS

Set-up ENPHREG#, ENCFREG#,
ENOFREG#, ENPHAC#,
ENTIREG#, CLROFR#, PMSEL,
LOAO#, ENI#,ACC, BINFMT#,
PEAK#, MOOPI/2PI#, SHo-1,
RBYTILO# from CLK going high

18

12

12

ns

Note 3

'"a:
W

.... N

Hold Time ENPHREG#, ENCFREG#
ENOFREG#, ENPHAC#,
ENTIREG#, CLROFR#, PMSEL,
LOAD#, ENI#,ACC, BINFMT#,
PEAK#, MOOPI/2PI#, SHO-1,
RBYTILO# from CLK going high

0

TOS

Set-up Time RINO-18,
IMlNo-18to CLKgoing high

18

12

12

ns

TOH

Hold TimeRINo-18,
IMINO-18 from CLK going high

0

0

0

ns

TOO

CLK to Output Delay ROO-19,
100-19

40

24

TOEO

CLK to Output Delay OETO-1

40

27

20

ns

TpO

CLK to Output Delay PACO#

30
30

20

12

ns

TECH

TEST
CONDITIONS

0

<:z:'"
W

ns

0

C!l
_:r:

"'!z
~

19

ns

TTO

CLK to Output Delay TICO#

20

12

ns

TOE

Output Enable Time OER#, OEI#,
OEREXT#,OEIEXT#

25

20

20

ns

TMO

OUTMUXO-1 to Output Delay

40

28

26

ns

TOO

Output disable time

20

15

15

ns

Note 2

TRF

Output rise, fall time

8

8

6

ns

Note 2

NOTES:
1. AC. testing is performed as follows: Input levels (ClK Input) 4.0V and OV;
Input levels (all other inputs) OV and 3.oV; Timing reference levels (ClK) 2.0V;
All others 1.SV. Input rise and fall times driven at 1noN. Output load par test
load circu~ with sw~ch closed and Cl = 40 pF. Output transition is measured
at VOH ~ 1.SV and VOL ~ 1.5V.

2. Controlled via design or process parameters and not directly tested.
Characterized upon In~iaI design and after major process and/or design
changes.
3. Applicable only when outputs are being monHered and ENCFREG#.
ENPHREG#. or ENTIREG# is active.

5-15

HSP45116
Waveforms

WR# ....,...._ _--...

CS#

ADO -1

-----------~~~-+--'~-----------~---

------------------------~~--+--'~-------------------

CO-15 __________________________- - / ' -______- J ' -______________________

CONTROL BUS. TIMING

CP
TCH
T

ClK

7

~

TCl

~

TM)k
MODO-1

T)k
PAC/#:.

CONTROL

-,

7 f-

...

lMCH
.:*.

IPCH

TE*

*ECH

TOl

*OH

INPUTS

mNO-19
IINO -19

=*00

ROUTO-19
IOUTO -19

OETO

3(DEO
-1

~ITPO

-*-

PACO#

3

TlCO#:

INPUT AND OUTPUT TIMING

5-16

TO

HSP45116
Waveforms

(Continued)

OER#
OEI#
OEREXT#
OEIEXT#

OUTMUXO -1

TOO
ROO -19 _ _ _ _~ 1.7V
100 - 19
HIGH
1'-1"'.3V;;.;..._ _ _ _ _--'
IMPEDANCE

ROO -19
100 -19
HIGH
IMPEDANCE

OUTPUT ENABLE, DISABLE TIMING

MULTIPLEXER TIMING

-F-T;:[ 1r:-T-R
OUTPUT RISE AND FALL TIMES

Test Load Circuit

DUTT

eLI

1------------1
I
I
I
I
I
I
I
I
I
I
t I
lOLl

*INCWDES STRAY AND
JIG CAPACITANCE

I

EQUIVALENT CIRCUIT

1_ _ _ _ _ _ _ _ _ _ _ _

Swilch 51 open for ICCSB and ICCOp lesls

EQUIVALENT CIRCUIT

5-17

I
I

1

HSP45116/883

{IlHARRIS

Numerically Controlled
Oscillator/Modulator

May 1991

Features

Description

• This Circuit is Processed in Accordance to Mil-Std-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1

The Harris HSP45116/883 combines a high performance
quadrature numerically controlled oscillator (NCO) and a
high speed 16-bit Complex Multiplier/Accumulator (CMAC)
on a single IC. This combination of functions allows a complex vector to be multiplied by the internally generated (cos,
sin) vector for quadrature modUlation and demodulation. As
shown in the block diagram, the HSP45116/883 is divided
into three main sections. The Phase/Frequency Control
Section (PFCS) and the Sine/Cosine Section together form
a complex NCO. The CMAC multiplies the output of the
Sine/Cosine Section with an external complex vector.

• NCO and CMAC on One Chip
• 15MHz and 25.6MHz Versions
• 32-bit Frequency Control
• 16-bit Phase Modulation
• 16-bit CMAC
• O.006Hz Tuning Resolution at 25.6MHz
• Spurious Frequency Components

< -90dBc

• Fully Static CMOS
• 145 Pin PGA

Applications
• Frequency Synthesis
• Modulation - AM, FM, PSK, FSK, QAM
• Demodulation, PLL

The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than O.OO6Hz at 25.6MHz. The
output of the PFCS is the argument of the sine and cosine .
The spurious free dynamic range of the complex sinusoid is
greater than 90dSc.
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC
multiplies this (cos, sin) vector by an external complex vector and can accumulate the result. The resulting complex
vectors are available through two 20-bit output ports which
maintain the gOdS spectral purity. This result can be accumulated internally to implement an accumulate and dump
filter.
A quadrature down converter can be implemented by loading a center frequency into the Phase/Frequency Control
Section. The signal to be downconverted is the Vector Input
of the CMAC, which multiplies the data by the rotating vector from the Sine/Cosine Section. The resulting complex
output is the down converted signal.

• Phase Shifter
• Fast Fourier Transforms (FFT)
• Polar to Cartesian Conversions

Block Diagram
VECTOR INPUT

R

MICROPROCESSOR
INTERFACE
DISCRETE
CONTROL
SIGNALS

PHASE!
FREQUENCY
CONTROL
SECTION

SINE!
COSINE
ARGUMENT

SIN
SINE!
COSINE
SECTION

1 J
CMAC

COS

1 1
R
VECTOR OUTPUT

CAUTION: These devices are sensHive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

5-18

File Number

2813

Specifications HSP45116/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •.••.•••••••••••..•.•.....••..•..••••••• +8.0V
Input or Output Voltage Applied •.•.•.•• GND-0.5V to VCC+0.5V
Storage Temperature Range ..••••••••..•.... -650 C to +150 0 C
Junction Temperature •..............•.........•...... +175 0 C
Lead Temperature (Soldering 10 sec) •••................ 3000 C
ESD Classification ........••........••.•.............. Class 1

Thermal Resistance
0ja
0jc
Ceramic PGA Package. . . • . • • • • . . . . . .• 23.1 0 C/W 8.30 C/W
Maximum Package Power Dissipation at +125 0 C
Ceramic PGA Package ...•.•.......••••......••••. 2.16 Watt
Device Count ••..•••..........•..•....... 103,000 Transistors

CAUTION: Stresses above those listed in "Absolute Maximum Ratjngs" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range •.••••.•.•..••...•.•••. +4.5V to +5.5V
Operating Temperature Range ...........•••• -55 0 C to +1250 C
TABLE 1. HSP45116/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Logical One Input
Voltage

VIH

VCC= 5.5V

1,2,3

-550C~..TA.s. +1250 C

2.2

-

V

Logical Zero Input
Voltage

VIL

VCC= 4.5V

1,2,3

-550C~TA:5.+1250C

-

0.8

V

Logical One Input
Voltage Clock

VIHC

VCC=5.5V

1,2,3

-550 C.s.TA.s.+1250 C

3.0

-

V

Logical Zero Input
Voltage Clock

VILC

VCC=4.5V

1,2,3

-550C~TA.s.+1250C

-

0.8

V

Output HIGH Voltage

VOH

10H =-4OOflA
VCC = 4.5V (Note 1)

1,2,3

-550C~TA~+1250C

2.6

-

V

Output LOW Voltage

VOL

IOL=+2.0mA
VCC = 4.5V (Note 1)

1,2,3

-550 C :5.TA.s. +125 0 C

-

0.4

V

VIN = VCC or GND
VCC=5.5V

1,2,3

-550 C 5. TA:::; +125 0 C

-10

+10

flA

.... N

VOUT = VCC or GND
VCC=5.5V

1,2,3

-550 C 5.TA:::; +1250 C

-10

+10

f1A

0:.:1 ....
_:I:
1"1>"-

1"1>

a:

Input Leakage Current

II

Output or I/O Leakage
Current

10

Standby Power Supply
Current

ICCSB

VIN=VCCorGND,
VCC= 5.5V,
(Note 4)

1,2,3

-550 C :::;TA:::; +125 0 C

-

500

flA

Operating Power
Supply Current

ICCOp

f= 15MHz,
VIN = VCC or GND
VCC = 5.5V (Notes 2, 4)

1,2,3

-550 C:5.TA.s.+1250 C

-

150

mA

7,8

-550C.:5TA:S +1250 C

-

-

Functional Test

FT

(Note 3)

1. Interchanging of force and sense conditions is permitted.

3. Tested as follows: f = 1MHz, VtH (clock inputs) = 3.4V, VIH (all other
inputs) = 2.6V, VIL = O.4V, VOH ~ 1.5V, and VOL.5 1.5V.
4. Output per test load circuH wHh swHch open and CL = 40pF.

CAUTION: These devices are sensHive to electrostatic discharge. Proper IC handling procedures should be followed.

5-19

Z

~

NOTES:

2. Operating Supply Current is proportional to frequency. typical rating is
10mNMHz.

....

cCzl"l>

Specifications HSP45.116/883
TABLE 2. HSP45116/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
(NOTE 1)
PARAMETER
ClKPeriod

15 (15MHz) -25 (25.6MHz)

GROUP A

SYMBOL CONDITIONS SUBGROUPS

TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

TCp

9,10,11

-550 C:$.TA:$.+125OC

66

-

39

-

ns

TCH

9,10,11

-550C:>. TA:$. +1250 C

26

15

ns

ClKlow

TCl

9,10,11

-550 C:$.TA:$.+125OC

26

-

15

-

WR#Low

TWl

9,10,11

-550 C,5TA:$.+125OC

26

-

15

-

ns

WR#High

TWH

9,10,11

-55°C ®®®®®®®
... ®®®
®®®
L
®®®
®®® .000
K
®®®
®®® sse
J
®®®
®®®
H e - B - - - - + -----@-@_@_
1.4-00
®®®
sse
®®®
®®®
®®®
c ®®®®®®®$®®®®®®®
B
®@®®®®®$®®®®®@®
A.
®®®®®.®® ®®®®®®{~+-_-.....
a
P

I
I
I

1.560
1.590

I

I

. 003 MIN
.!!QliS;

£ INCREASE MAXIMUM UMIT BY .003" WHEN SOLDER DIP
OR TIN PLATE LEAD FINISH APPLIES.
2. ACTUAL STANDOFF CONFIGURATION MAY VARY. STANDOFFS
SHOULD BE LOCATED ON THE PIN MATRIX OIAGONALS.
J. THERE ~usr BE AN A1 CORNER IDENTIFIER ON BOTH
TOP AND BOTTOM SURFACES. 10 TYPE 15 OpnONAl.
AND MAY CONSIST OF NOTCHES. METALLIZED MARKINGS
OR OTHER FEATURES.

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500C ± 100 C
Method: Furnace Seal

NOTE: All Dimensions are

~:::.

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 P-AC

tMH-M-38510 Compliant Materials, Finishes, and D&nenslons.

,Dimensions are in inches.

5-25

en

ex:
W

-' N

<
zen

c:l W
_:z::
en ....
:z

~

HSP45106

mJHARRIS

16 Bit Numerically Controlled Oscillator

May 1991

Features

Description

• 25.6MHz, 33MHz, 40MHz Versions

The Harris HSP45106 is a high performance 16-bit
quadrature numerically controlled oscillator (NC016). The
NC016 simplifies applications requiring frequency and
phase agility such as frequency-hopped modems, PSK
modems, spread spectrum communications, and precision
signal generators. As shown in the block diagram, the
HSP45106 is divided into a Phase/Frequency Control
Section (PFCS) and a Sine/Cosine Section.

• 32-Bit Center and Offset Frequency Control
• 16-Bit Phase Control
• 8 Level PSK Supported Through Three Pin Interface
• Simultaneous 16 Bit Sine and Cosine Outputs
• Output in Two's Complement or Offset Binary
• <0.01 Hz Tuning Resolution at 40MHz
• Serial or Parallel Outputs
• Spurious Frequency Components < -90dBc
• 16 Bit Microprocessor Compatible Control Interface
• 85 Pin PGA, 84 Pin PLCC

Applications

The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The frequency resolution is 32 bits, which provides for
resolution of better than 0.01 Hz at 40MHz. User programma·
ble center frequency and offset frequency registers give the
user the capability to perform phase coherent switching
between two sinusoids of different frequencies. Further, a
programmable phase control register allows for phase
control of better than 0.0060 • In applications reqUiring up to
a-level PSK, three discrete inputs are provided to simplify
implementation.
The output of the PFCS is a 32-bit phase which is input to
the Sine/Cosine Section for conversion into sinusoidal
amplitude. The outputs of the sine/cosine section are two
16-bit quadrature signals. The spurious free dynamic range
of this complex vector is greater than 90dSc.

• Direct Digital Synthesis
• Quadrature Signal Generation
• Modulation - FM, FSK, PSK (BPSK, QPSK, 8PSK)

For added flexibility when using the NC016 in conjunction
with DAC's, a choice of either parallel of serial outputs with
either two's complement or offset binary encoding is provid·
ed. In addition, a synchronization signal is available which
signals serial word boundaries.

• Precision Signal Generation

Block Diagram

MICROPROCESSOR
INTERFACE
DISCRETE
CONTROL SIGNALS
CLOCK

PHASE!
FREQUENCY
CONTROL
SECTION

SIN/COS
ARGUMENT
32

Copyright @) Harris Corporation 1991

/

SINE
SINE!
COSINE
SECTION

16
/

COSINE/16
/

File Number
5-26

2809

HSP45106
Pinouts

.

81N4

BINFUT

OES

Vee

SER

OEC

'"

'"
"

PACO

COS2

#

J

1'"';Ae

H

IEN~AC
R£B

"

F

Vee

.AC
STRB

SlN9

ENOF
REG#'

es".

PARI

'"

I"'"T
AC#

""PO

REO#'

co..

C085

Rd

:~

85 LEAD PGA
TOP VIEW

C087

e088

H

PIN
Vee

SIN14

81N18

91N12

COSO

OE.
#

SINlIl

OND

C081

OEe
#

COS3

coss

0

Vee

e084

e088

ON.

COS"

D

co."

COSIS

COS"

e

co." COSIS

IT'eo# COS,.

•

e08"

1!~1::

A

II

PIN 'AI'

ptN 'AI'

10

10

•

84 LEAD PLCC
TOP VIEW

5-27

SlNl0

91N11

.ONO

81N7

10

81NI

SIN3

SIN1

Vee

.IN'

elX

....

11

SINO

GND

vee

.'":;."T

PARI
.ER
#

'N";AC

PAC'

EN";lAe

INRT
Ae#

-~~

#

INHOF

coae

R#

85 LEAD PGA
BOTTOM VIEW

eoss I e087

E

e,

.... ....

C092

C099

WR#

INDEX

PMSEL

.

"
coso

INHOf

Vee

A

DAC
.TRB
#

l

~:~
WOW

COSIO leo."

ON.
INDEX

PON

ee

e8

e,.

TOCO#

e'

c.

Vee

e"

cO2

e05

e,

e.

e.

e7

e.

e"

e,.

..
ON.

::;'},.

ENCF
REG#'

GN.

e","

TEST

Vee

MODD

I0Il002

A2

MOOl

..

PMSEl

HSP45106
Pin Description
NAME

PGAPIN
NUMBER

TYPE

DESCRIPTION

VCC

85,011, F1,
K7,K10

+5 power supply pin.

GNO

A9,02,E10,
K4, L11

Ground

CQ-15

A1-8,B3-4
B6-8,C5-7

I

Control input bus for loading phase, frequency, and timer' data intothe PFCS; CO is LSB.

AO-2

A10,B9'-10

I

Address pins for selecting destination of CQ-15 data (Table 2)•.-

CS#

E11

I

Chip select (Active low). Enables data to be written into control registers by WR#.

WR#

E9

I

Wrije enable' (Active low). Data Is clocked into the regisief. selected by AQ-2 on the rising edge
of WR# when CS# is low.

CLK

K9

I

Clock. All registers, except the control registers clocked with WR#, are clocked (when
enabied) by the rising edge of CLK.

NPOREG#

F10

I

Phase Offset Registar Enable (Active low). Registered on chip by CLK. When active, after being
clocked onto chip, ENPOREG# enables the clocking of data into the Phase Offset Register. Allows
ROM address to be updated regardless of ENPHAC#.

ENOFREG#

F9

I

Offset Frequency Register Enable (Active low). Registered on chip by ClK. When active, after being
clocked onto chip, ENOFREG# enables the clocking of data into the Offset Frequency Register.

ENCFREG#

F11

I

Center Frequency Register Enable (Active low). Registered on chip by ClK. When active, after being
clocked onto chip, ENCFREG#enabies the clocking of data into the Center Frequency Register.

ENPHAC#

H11

I

Phase Accumulator Register Enabie (Active low). Registered on chip by CLK. When active, efter
being clocked onto chip, ENPHAC#enables the clocking of data into the Phase Accumulator Registar.

ENTIREG#

G11

I

Timer Increment Register Enable (Active low). Registered on chip by CLK. When active, after being
clocked onto chip, ENTIREG# enables the clocking of data into the Timer Increment Register.

INHOFR#

G9

I

Inhibit-Offset Frequency Register Output (active low). Registered on chip by ClK. When active, after
being clocked onto chip, INHOFR# zeroes the data path from the Offset Frequency Register to the
Frequency Adder. New-data can be still clocked into the Offset Frequency Register. INHOFR# does
not affect the contents of the register.

INITPAC#

J11

I

Initialize Phase Accumulator (Active low). Registered on chip by ClK. Zeroes the feedback path in the
Phase Accumulator. Does not clear the Phase Accumulator Register.

MOOO-2

B11,
C10-11

I

Modulation Control Inputs. When selected with the PMSEl line, these bits add an. offset of 0, 45, 90,
135, 180, 225, 270, or 315 degrees to the current phase (i.e., modulate the output). The lower 13 bits
of the phase control are set to zero. These bits are registered when. the. Phase Offset Register is
enabled.

PMSEl

A11

I

Phase Modulation Select input. Registared on chip by CLK. This input determines the source of the
data clocked into the Phase Offset Registar. When high, the Phase.lnput Register is selected. When
low, the extemal modulation pins (MOOQ-2) control the three most significant bits of the Phase
Offset Register and the 13 least significant bits are set to zero.

PACI#

H10

I

Phase Accumulator Carry Input (Active low). Registered on chip by CLI~.

INITTAC#

G10

I

Ini.tialize Timer Accumulator (Active low). This input is registered on chip by CLK. When active, after
being clocked onto chip, INITTAC# enables the clocking of data into the Timer increment Register,
and also zeroes the feedback path in the Timer Accumulator.

TEST

010

I

Test select input. Registered on chip by CLK. This input is ective high. When active, this input enables
test busses.to the outputs instead of the sine and cosine data;

PAR/SER#

J10

I

ParaileVSerial Output Select. This input is registered on chip by ClK. When low, the sine and cosine
outputs are in serial mode. The output shift registers will load In new data after ENPHAC# goes low
and will atar! shifting the data out after ENPHAC# goes high. When this input is high, the output
registers are loaded every clock and no shifting takes place.

BINFMT#

K11

I

Format This input Is registered on chip by CLK. When low, the MSB of the SIN and COS are inverted
to form an offset binary (unsigned) number.

OES#

K2

I

Three-state control for bits SINQ-15. Outputs are enabled when OES# is low.

OEC#

J2

I

Three-state control for bits COSO-15. Outputs are enabled when OEC# is low.

TICO#

B2

0

Timer Accumulator Carry Output. Active low, registered. This output goes low when a carry is
generated by the Timer Accumulator.

5-28

HSP45106
Pin Description

(Continued)

NAME

PGAPIN
NUMBER

TYPE

DESCRIPTION

DACSTRB#

L1

0

DAC Strobe (Actove low). In serial mode, this output will go low when the first bit of a new output
word is valid at the shift register output.

SINO-15

J5-7, K3,
K5-6, K8,
L2-10

0

Sine output data. When parallel mode is enabled, data is output on SINO-15. When serial mode is
enabled, output data bits are shifted out of SIN15 and SINO. The bit stream on SIN 15 is provided
MSB first while the bit stream on SINO is provided LSB first.

COSG-15

B1, C1-2,
D1,E1-3,
F2-3,G1-3,
H1-2,J1, K1

0

Cosine output data. When parallel mode is enabled, data is output on COSO-15. When serial
mode is enabled, output data bits are shifted out of COS15 and COSO. The bit stream-on COS15
is provided LSB first.

Index Pin

C3

Used to align chip in socket or on circuit board. Must be left as a no connect in circuit.

Functional Description
The 16-bit Numerically Controlled Oscillator (NC016)
produces a digital_ complex sinusoid waveform whose
frequency and phase are controlled through a standard
microprocessor interface and discrete inputs. The NC016
generates 16-bit sine and cosine vectors at a maximum
sample rate of 40MHz. The NC016 can be preprogrammed
to produce a constant (CW) sine and cosine output for
Direct Digital Synthesis (DDS) applications. Alternatively;
the phase and frequency inputs can be updated in real time
to produce a FM, PSK, FSK, or MSK modulated waveform.
To simplify PSK generation, a 3 pin interface is provided to
support modulation of up to 8 levels.

supplies a pulse to mark the passage of a user programmed
period of time.
Input Section
The Input Section loads the data on CO-15 into one of the
seven input registers, the lSB and MSB Center Frequency
Input Registers, the lSB and MSB Offset Frequency
Registers, the lSB and MSB Timer Input Registers, and the
Phase Input Register. The destination depends on the state
of AO-2 when CS# and WR# are low (Table 1).
TABLE 1
A2-0 DECODING

As shown in the Block Diagram, the NC016 is comprised of
a Phase and Frequency Control Section (PFCS) and Sinel
Cosine Section. The PFCS stores the phase and frequency
control inputs and uses them to calculate the phase angle of
a rotating complex vector. The Sine/Cosine Section
performs a lookup on this phase and generates the
appropriate amplitude values for the sine and cosine. These
quadrature outputs may be configured as serial or parallel
with either two's complement or offset binary-format

The PFCS is comprised of a Phase Accumulator Section,
Phase Offset adder, Input Section, and a Timer Accumulator
Section. The Phase Accumulator computes the
instantaneous phase angle from user programmed values
in the Center and Offset Frequency Registers. This angle is
then fed into the Phase Offset adder where it is o.ffset by the
preprogrammed value in the Phase Offset Register. The
Input Section routes data from a microprocessor
compatible control bus and discrete- input signals into the
appropriate configuration registers. The Timer Accumulator

A1

AO

0

0

0

CS# WR#
0

t

FUNCTION
Load least significant bits of
Center Frequency input.

0

0

1

0

t

Load most significant bits of
Center Frequency input.

0

1

0

0

t

Load least significant bits of
Offset Frequency input.

0

1

1

0

t

Load most significant bits of
Offset Frequency input.

1

0

0

0

t

Load least significant bits of
Timing Interval input.

1

0

1

0

t

Load most significant bits of
Timing Interval input.

rn

a:
W

.... N

<_:r:

z-

rn

___ - - - - - - - - - - - - ___
CO-15

~
PHEN#,

~ENCOOERI

_ '0'

:~3

PHASE OFFSET REGISTER

Ir!;l

, r:1
'6 1

PHASE OFFSET ADDER

,16

1r71

,1.

'r

PHASE INPUT
PHASE
INPUT

REG (18}

-----l

CO-15

PHASE ACCUMUlATOR
REGISTER

MSCFEN#,

32

CO-15

E
G

LSCFEN#,

INPUT

CO-15

SECTION

,

(II

c.l

o

,.
is

c

:D

m

ENPOREG

ENOFREG
ENCFREG
ENPHAC
ENTIREG
INHOFR
INITPAC

PMSEl
PAC.
INmAC

R
E

G

MSOFEN#,_

MSB
OFFSET
FREQUENCY

INPUT
REG(18}

R.ENOFREG
R.ENCfREG

LSOFEN#'

R.ENPHAC
R.ENTIREG

RJNHOFR
R.INITPAC

CO-15

INPUT

R.PAC#'

REG(16J

CO-1S

LSTIEM#

1

I
I
I
I

~
~

01

MSB

------------

INCREMENT
INPUT

TIMER 'NCRE.

REG(18}

ClK

32

_____ J

FREQUENCY

TIMER

MSTIEN#

R.PMSEL
R.PACI

R.lNITTAC

PHASE
ACCUMULATOR
SECTION

LSB
OFFSET

R.ENPOREG

CO-1.

R

I
II

I

,1.

.....

C)
0)

HSP45106
clock enable of the Center Frequency Register; this register
then gets loaded on the following rising edge of CLK. The
contents of the input registers are downloaded to the
control registers every clock if the control inputs are
enabled.

TABLE 2
MOD2-0 DECODING

Phase Accumulator Section
The Phase Accumulator adds the 32 bit output of the
Frequency Adder with the contents of a 32 bit Phase
Accumulator Register on every clock cycle. When the sum
causes the adder to overflow, the accumulation continues
with the least significant 32 bits of the result.
Initializing the Phase Accumulator Register is done by
putting a low on the INITPAC# and ENPHAC# lines. This
zeroes the feedback path to the accumulator, so that the
register is loaded with the current value of the Frequency
Adder on the next clock.
The frequency of the quadrature outputs is based on the
number of clock cycles required to step from 0 to full scale.
The number of steps required for this transition depends on
the phase increment calculated by the frequency adder. For
example, if the Center and Offset Frequency registers are
programmed such that the output of the Frequency Adder is
4000 0000 hex, the Phase Accumulator will step the phase
from 0 to 360 degrees every 4 clock cycles. Thus, for a 30
MHz CLK, the quadrature outputs will have a frequency of
30/4 MHz or 7.5MHz. In general, the frequency of the
quadrature output is determined by N x FCLKl2 32, where N
is the output of the Frequency Adder and FCLK is the
frequency of CLK.
The Frequency Adder sums the contents of both the Center
and Offset Frequency Registers to produce a phase
increment. By enabling INHOFR#, the output of the Offset
Frequency Register is disabled so that the output frequency
is determined from the Center Frequency Register alone.
For 8FSK modems, INHOFR# can be asserted/
de-asserted to toggle the quadrature outputs between
two programmed frequencies. Note: enabling/disabling
INHOFR# preserves the contents of the Offset Frequency
Register.
Phase Offset Adder
The output of the Phase Accumulator goes to the Phase
Offset Adder, which adds the 16 bit contents of the Phase
Offset Register to the 16 MSB's of the phase. The resulting
32-bit number forms the instantaneous phase which is fed
to the Sine/Cosine Section.
The user has the option of loading the Phase Offset
Registers with the contents of the Phase Input Register or
the MODO-2 inputs depending on the state of PMSEl.
When PMSEL is high, the contents of the Phase Input
Register are loaded. If PMSEL is low, MODO-2 encode the
upper 3 bits of the Phase Offset Register while the lower
13 bits are cleared. The MODO-2 inputs simplify PSK
modulation by providing a 3 input interface to phase
modulate the carrier as shown in Table 2. The control
input ENPOREG# acts as a clock enable and must be
low to enable clocking of data into the Phase Offset
Register.

PHASE SHIFT
(DEGREES)

MOD2

MOD1

MODO

0

0

0

0

0

0

1

45

0

1

0

90

0

1

1

135

1

0

0

270

1

0

1

315

1

1

0

180

1

1

1

225

Timer Accumulator Section
The Timer Accumulator consists of a register which is
incremented on every clock. The amount by which it increments is loaded into the Timer Increment Input
Registers and is latched into the Timer Increment Register
on rising edges of CLK while ENTIREG# is low. The output
of the Timer Accumulator is the accumulator carry out,
TICO#. TICO# can be used as a timer to enable the
periodic sampling of the output of the NCO-16. The number
programmed into this register equals (2 32 x CLK period)/
(desired time interval).

Sine/Cosine Section
The Sine/Cosine Section (Figure 2) converts the instantaneous phase from the PFCS Section into the appropriate
amplitude values for the sine and cosine outputs. It takes
the most significant 20 bits of the PFCS output and passes
them through a Sine/Cosine look up to form the 16 bit
quadrature outputs. The sine and cosine values are
computed to reduce the amount of ROM needed. The
magnitude of the error in the computed value of the
complex vector is less than -90.2dB. The error in the sine or
cosine alone is approximately 2dB better. The 20 bit phase
word maps into 211 radians so that the angular resolution is
(211)/220. An address of zero corresponds to 0 radians and
an address of hex FFFFF corresponds to 211-«211)/220)
radians. The outputs of the Sine/Cosine Section are two's
complement sine and cosine values. The ROM contents
have been scaled by (2 16 -1)/(2 16+1) for symmetry about
zero.
To simplify interfacing with D/A converters, the format of the
sine/cosine outputs may be changed to offset binary by
enabling BINFMT#. When BINFMT# is enabled, The MSB
of the Sine and Cosine outputs (SIN 15 and COS15 when
the outputs are in parallel mode) are inverted. Depending
upon the state of BINFMT#, the output is centered around
midscale and ranges from 8001 H to 7FFFH (two's complement mode) or 0001 H to FFFFH (offset binary mode).
Serial output mode may is chosen by enabling PAR/SER#.
In this mode the user loads the output shift registers with
Sine/Cosine ROM output by enabling ENPHAC#. After
ENPHAC# goes inactive the data is shifted out serially. For

5-31

CI)

a:
W

-'N

cC-

:zCl)
t::!w
_:t:
Cl)1:z

>-

CI)

HSP45106
example. to clock out one 16 bit sine/cosine output,
ENPHAC#· would be active for one cycle to load the output
shift register, and would then go inactive for the following
15 cycles to clock the remaining bits out Output bit streams
are provided iriformats with either MSB .first or LSBfirsl
The MSB. first. forrnlilt is available on ..the SIN15 and COS15
output pins. The LSB first format is available on the SINO
and COSO output pins. InMSB first format, zero's follOw the
LSB if a new output word is not loaded into the shift register.
In LSB first format, the sine extension bit follows the MSB if

a new. data word is not loaded. The output signal
DACSTRB# is provided t()signal the first bit ofa new output
word is valid (Figure 3). Note: all unused pins of SINO-15
and COSO-15 should be left floating.
A test mode is supplied which enables the user to access
the phase input to the Sine/C()sine ROM. if TEST and PARI
SER# are both high, the 28 MSB's of the phase input to the
Sine/Cosine Section are made available oil SINO:"15 arid
COS4-15. The SINO-15 outputs represent the MSW ofthe
address. .
.

16 COSINE
SINICOS
ARGUMENT

DACSTRB#

16 SINE
OUTPUT

CONTROL

SlNO-15

1-+1.:,:6:.....

COSO-.15

16- --1-1
1-+-

BINFMT#-----------------------I
ENPHAC#. TEST. PAR/SER#

OES#
OEC# ______________

~--

__- -______________________________________

FIGURE 2.SINEICOSINE BLOCK DIAGRAM

~.~.34."'~
ENPHAC#

DACSTRB#

.

. . .

SERIAL DATA OUTPUT

BIT>(I)

HSP45106
A.C. Electrical Specifications (Note 1)
25.6MHz
PARAMETER

SYMBOL

MIN

33M Hz

40MHz

MAX MIN' MAX MIN MAX

TCp

ClKPeriod

39

-

30

25

12

-

TCH

ClKHigh

15

-

12

10

-

25

-

12

-

10

COMMENTS
ns
ns.

TMCS

Set-up Time MODO-2 to ClK going high

15

TMCH

Hold Time MODO-2 from ClK going high

0

TECS

Set-up Time ENPOREG#, ENOFREG#, ENCFREG#, ENPHAC#,
ENTIREG#, INHOFR#, PMSEl#,INITPAC#, BINFMT#,
TEST, PARISER#, PACI#,INITTAC#to ClKgoing high

12

-

TECH

Hold Time ENPOREG#, ENOFREG#, ENCFREG#, ENPHAC#,
ENTIREG#, INHOFR#, PMSEl#,INITPAC#, BINFMT#,
TEST,PARISER# ,PACI#,INITTAC# from ClK going high

0

-

0

-

0

-

ns

TOO

CLK to Output Delay SINO-15, COSO-15, TICO#

-

18

-

15

-

13

ns

ClK to Output Delay DACSTRB#

2

18

2

15

2

13

ns

TOE

Output Enable Time

12

-

12

ns

Output Disable Time

15

-

13

ns, Note 3

TRF

Output rise, fall time

-

12

TOO

-

8

-

8

ns, Note 3

TCl

ClKlow

15

Twp

WR#Period

39

TWH

WR#High

15

TWl

WR#low

15

TAWS

Set-up Time AO-2, CS# to WR# going high

13

TAWH

Hold Time AO-2, CS# from WR# going high

1

TCWS

Set-up Time CO-15 to WR# going high

15

TCWH

Hold Time CO-15 from WR# going high

0

TWC

Set-up time WR# high to ClK high

16

TDSO

15
8

12
30
12
12
13
1
15
0
12
15
0

-

10
10
12
1
12
0
10

-

12
0

ns
ns
ns
ns
ns
ns
ns
ns
ns, Note 2
ns
ns
ns

NOTES:
1. A.C. testing is performed as follows: Input levels (ClK Input) 4.0V and OV;
Input levels (all other inputs) OV and 3.0V; Timing reference levels (ClK)
2.0V; All others 1.5V.lnput rise and fall times driven at 1nsN. Output load
pertest load.circuit w~h switch closed and Cl = 40 pF. Output transftion
is measured at VOH ::: 1.5V and VOL:$. 1.5V.

2. W ENOFREG#, ENCFREG#, ENTIREG#, OR ENPOREG# are active,
care must be taken to not violate set-up and hold times to these registers
when wrfting data into the chip via the CO-15 port.
3. Controlled via design or process parameters and not directly tested. Char·
acterized upon initial design and after major process and/or changes.

A.C. Test Load Circuit
r-----------------,
1

1

1

1

1

1

1

1
1
1
1
1

1.5V

IOL

1
1

Switch S1 open for ICCSS and ICCOp

1

1

1____

EQUIVALENT CIRCUIT _ _ _ _ I

·5-34

HSP45106
Waveforms

CLK

MODO -2

ENABLE!
CONTROL
SIGNALS

SINO - 15, COSO - 15, TICO# _ _.....,r'-_ _J

DACSTRB#

WR#

AO -2, CS#

...a:
cc-

C'I>

co -15

..... N

zC'l>

c:s
...
_:I;
rn ....
Z

>-

C'I>

OUTPUT ENABLE, DISABLE TIMING

OES#,OEC#

COSO -15,
SINO -15

OUTPUT RISE AND FALL TIMES

5-35

m

HARRIS

HSP451 06/883
16 Bit Numerically Controlled Oscillator

May 1991

Features

Description

• This Circuit is Processed in Accordance to Mil-Std, 883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1

The Harris HSP45106/883 is a high performance 16-bit
quadrature numerically controlled oscillator (NC016). The
NC016 simplifies applications requiring frequency and
phase agility such as frequency-hopped modems, PSK
modems, spread spectrum communications, and precision
signal generators. As shown in the block diagram, the
HSP451 06/883 is divided into a Phase/Frequency Control
Section (PFCS) and a Sine/Cosine Section.

• 25.6MHz and 33MHz Versions
• 32-Bit Center and Offset Frequency Control
• 16-Bit Phase Control
• 8 Level PSK Supported Through Three Pin Interface
• Simultaneous 16 Bit Sine and Cosine Outputs
• Output in Two's Complement or Offset Binary
• <0.01 Hz Tuning Resolution at 33MHz
• Serial or Paranel Outputs
• Spurious Frequency Components < -90dBc
• 16 Bit Microprocessor Compatible Control Interface
·85 Pin PGA

The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The frequency resolution is 32 bits, which provides for
resolution of better than 0.01 Hz at 33M Hz. User programmable center frequency and offset frequency registers give the
user the capability to perform phase coherent switching
between two sinusoids of different frequencies. Further, a
programmable phase control register allows for phase
control of better than 0.006 0 • In applications requiring up to
8 level PSK, three discrete inputs are provided to simplify
implementation.
The output of the PFCS is a 32-bit phase argument which
is input to the sine/cosine section for conversion into sinusoidal amplitude. The outputs of the sine/cosine section are
two l6-bit quadrature signals. The spurious free dynamic
range of this complex vector is greater than 90dBc.

Applications
• Direct Digital Synthesis
• Quadrature Signal Generation

For added flexibility when using the NC016 in conjunction
with DAC's, a choice of either parallel of serial outputs with
either two's complement or offset binary encoding is provided. In addition, a synchronization signal is available which
signals serial word'boundaries.

• Modulation - FM, FSK, PSK (BPSK, QPSK, 8PSK)
• Precisio'n Signal Generation

Block Diagram

MICROPROCESSOR
INTERFACE
DISCRETE
CONTROL SIGNALS
CLOCK

PHASE!
FREQUENCY
CONTROL
SECTION

PHASE
32
/

SINE
SINE!
COSINE
SECTION

CAUTION: Electronic devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

5-36

16
/

COSIN~16

File Number

2815

Specifications HSP45106/883
Absolute Maximum Ratings

Reliability Information

SupplyVoitage ........................................ +8.0V
Input, Output Voltage Applied ...•...... GND-0.5V to VCC+0.5V
Storage Temperature Range ..•...........•.. -650C to +150 0 C
Junction Temperature ................................ +175 0 C
Lead Temperature (Soldering, Ten Seconds) ••.......... +3000 C
ESD Classification ....•••...•.•..........•..••.•...... Class 1

Thermal Resistance
Sja
Sjc
Ceramic PGA Package. . . . . . . . . . • .• 36.0 0 C/W 11.60 C/W
Maximum Package Power Dissipation at +125 0 C
Ceramic PGA Package ............................ 1.39 Watt
Gate Count ....••...............•....••........ 18,750 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions.
Operating Voltage Range .•••..................• +4.5V to +5.5V
Operating Temperature Range ............•.. -550C to +125 0C

TABLE 1. HSP45106/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Devices Guaranteed and 100% Tested

PARAMETER

SYMBOL

CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

1,2,3

-55°C ;$TA5 +1250 C

2.2

-

V

Logical One Input
Voltage

VIH

VCC=5.5V

Logical Zero Input
Voltage

VIL

VCC=4.5V

1,2,3

-550C ;$TA 5 +125 0 C

-

0.8

V

Output HIGH Voltage

VOH

10H =-400~A
VCC = 4.5V (Note 1)

1,2,3

-55°C 5TA;$ +1250 C

2.6

-

V

Output LOW Voltage

VOL

IOL=+2.0mA
VCC = 4.5V (Note 1)

1,2,3

-550C 5TA 5 +125 0 C

-

0.4

V

Input Leakage Current

II

VIN = VCC or GND
VCC=5.5V

1,2,3

-550C ;$TA::::' +125 0 C

-10

+10

~A

Output Leakage
Current

10

VOUT = VCC or GND
VCC=5.5V

1,2,3

-550C5TA5 +125 0 C

-10

+10

~A

W

Clock Input High

VIHC

VCC=5.5V

1,2,3

-550C ;$TA::::' +125 0 C

3.0

-

V

Clock Input Low

VILC

VCC=4.5V

1,2,3

-55°C ;$TA5 +125 0 C

-

0.8

V

Standby Power Supply
Current

ICCSS

VIN = VCC or GND
VCC=5.5V,
(Note 4)

1,2,3

-550C!> TA!> +125 0 C'

-

500

~A

Operating Power
Supply Current

ICCOp

f=25.6MHz
VCC = 5.5V (Notes 2, 4)

1,2,3

-55°C :5.TA;$ +1250 C

-

256

rnA

7,8

-550C :5.TA:5. +125 0 C

-

-

-

Functional Test

FT

~

a:

(Note 3)

NOTES:

=

1. Interchanging of force and sense conditions is permitted.
'2. Operating Supply Current is proportional to frequency. typical rating is
10mNMHz.

3. Tested as follows: f = 1 MHz, VIH
2.6. Vll
VOL ~ 1.5V. VIHC = 3.4V. and Vile = 0.4V.

= 0.4.

4. Loading is as specified in the test load circuit with CL

5-37

VOH

= 40pF.

~

1.5V,

-' N

c(z:~

t!:Iw

_:C

~

I-

z:
>~

HSP45 to 6/883
TABLE 2. A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested.

PARAMETERS

SYMBOL

(NOTE 1)
CONDITIONS

GROUP A
SUBGROUP

LIMITS
-25
-33
(25.6MHz)
(33M Hz)
TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

ClKPeriod

TCp

9,10,11

-55°C ~TA:::; +1250C

39

-

30

-

ns

ClKHigh

TCH

9,10,11

-55°C :::,TA:::' +1250 C

15

-

12

-

ns

ClKlow

TCl

9,10,11

-550C~TA$+125OC

15

12

TWp

-550C~TA.5+1250C

39

30

-

ns

9,10,11

-

15

WR#Period

ns

WR#High

TWH

9,10,11

-550C ~TA $ +1250 C

-

ns

TWl

9,10,11

-550C ~TA::;' +1250 C

15

-

12

WR#low

12

ns

Set-up Time AO-2, CS# to WR#
going high

TAWS

9,10,11

-550C .5TA$ +125OC

13

-

13

-

Hold Time AO-2; CS# from WR#
going high

TAWH

9,10,11

-550C ~TA~ +125OC

2

-

2

-

ns

Set-up Time CO-15 to WR#
going high

TCWS

9,10,11

-550C.5TA~ +1250C

15

-

15

-

ns

Hold Time CO-15 from WR#
going high

TCWH

9,10,11

-550C $TA.5 +1250C

1

-

1

-

ns

ns

Set-up Time WR# high to CLK high

TWC

9,10,11

-550C .5TA~ +1250C

16

-

12

-

ns

Set-up Time MODQ-2 to ClK
gOing high

TMCS

9,10,11

-550C :::;TA.5 +1250C

15

-

15

-

ns

Hold Time MODO-2 from ClK
going high

TMCH

9,10,11

-550C~TA::> +1250C

1

-

1

-

ns

Set-up Time ENPOREG#,
ENOFREG#, ENCFREG#,
ENPHAC#, ENTIREG#, INHOFR#,
PMSEl#, INITPAC#, BINFMT#,
TEST, PARISER#, PACI#,
INITTAC# to ClK going high

TECS

9,10,11

-550C:::,TA5+1250C

12

-

12

-

ns

Hold Time ENPOREG#,
ENOFREG#, ENCFREG#,
ENPHAC#, ENTIREG#, INHOFR#,
PMSEl#, INITPAC#, BINFMT#,
TEST, PARISER#, PACI#,
INITTAC# from CLK going high

TECH

9,10,11

-550C~TA.5+1250C

1

-

1

-

ns

TOO

9,10,11

-550C:::,TA~+125OC

-

18

-

15

ns

9,10,11

-550C::;,TA.5.+1250C

2

18

2

15

ns

9,10,11

-550C 

...a:
<-

.... N

:zCl>
c:s
...
_::c
CI>!:z
~

HSP45106/883
Burn-In Circuit

HSP4510S/883 PIN GRID ARRAY (PGA)
10

8

8

7

8,

SINO

SINt

SlM3

SINS

SIN.

11
, L

·GND

•

•

4

6

SINS

SIN12

SIN1.

SlN13

--

1
DAC
~TR8

L

#

Vee,

FMY

K

CLK

SIN.

Yeo

SINS

SI~10

SINa

SIN7

SINtt

0",
.#

COSO

OEC
#

COSI

COS2

CQS3

H

cosa

C0S4

cos.

G

COIJ7

cosa

Yec

F

CDS11

COS10

coss

E

GND

SlN1S

K

,.

J

H

I'N'TPAC

PARI

SEL
#:

IENj,HAC

PACI

ENTI

IMITT
AC#:

G

REG
#:

#:

F

REG#

EMPO
REG#:

E

CS#:

GND

D

Vcc

TEST

C

MO,,"

MODO

ENCF

PIN
NAME

::-#:
WR#:

85 LEAD PGA
TOPV1EW

Cl0

. C8

IHDE:"

CB

--

PIN

GND I COS1'

D

I C081.

C

ITICO# IC0814

B

COS15

B

MOO1

A2

Al

Cl.

C12

Cl'

VCC

C4

Cl

A

PMSEL

AD

GND

C14

Cl1

C8

C7

C.

C3

C2

8

8

7

e

•

4

3

•

10

11

PGA
PIN

IMHOF

R#

BURN-IN
SIGNAL

PGA
PIN

PIN
NAME

BURN-IN PGA
SIGNAL PIN

PIN
NAME

J

A

PIN 'At'

ID

1

BURN-IN
SIGNAL

PGA
PIN

PIN
NAME

BURN-IN
SIGNAL

Al

CO

F7

Bl1

MOOl

F13

F9

ENOFREG#

F8

K2

OES#

F14

A2

C2

F7

Cl

COS13

VCcJ2

FlO

ENPOREG#

F4

K3

SIN15

VCC/2

A3

C3

F7

C2

COS15

VCC/2

Fll

ENCFREG#

F7

K4

GNO

GNO

A4

C5

F8

C5

C6

F8

Gl

COS5

VCcJ2

K5

SIN10

VCcJ2

AS

C7

F8

C6

C9

FlO

G2

COS4

VCC/2

K6

SIN8

VCcJ2

A6

C8

FlO

C7

Cl0

FlO

G3

C056

VCC/2

K7

VCC

VCC

A7

Cl1

FlO

Cl0

MODO

F12

G9

INHOFR#

Fll

K8

SIN2

VCC/2

AS

C14

Fl1

Cl1

M002

F14

Gl0 INITTAC#

F13

K9

CLK

FO

A9

GND

GNO

01

COS12

VCcJ2

Gl1

ENTIREG#

F12

Kl0

AO

F8

02

GNO

GND

Hl

COS3

VCcJ2

Kll

VCC
BINFMT#

VCC

Al0
All

PMSEL

F14

010 TEST

F14

H2

COS2

L1

OACSTRB#

VCcJ2

F6

Bl

COS14

VCC/2

011

VCC

VCC

Hl0

PACI#

VCcJ2
Fl1

L2

SIN14

VCcJ2

B2

TICO#

El

COS9

VCcJ2

Hl1

ENPHAC#

FlO

L3

51N13

VCcJ2

B3

Cl

VCcJ2
F7

E2

C0510

VCcJ2

Jl

COSl

L4

51N12

VCC/2

B4

e4

F8

E3

COS11

J2

OEC#

L5

SIN9

VecJ2

B5

Vec

Vec

E9

WR#

VCcJ2
F4

VCcJ2
F14

J5

SIN11

VecJ2

L6

SIN4

VecJ2

B6

C13

Fl1

El0

GNO

GND

J6

SIN7

VecJ2

L7

SIN5

VCcJ2

B7

C12

Fll

Ell

CS#

F6

J7

SIN6

VCcJ2

18

SIN3

VecJ2

B8

e15

Fll

Fl

Vec

Vec

Jl0

PAR/5ER#

F13

La

SINl

VecJ2

B9

Al

F7

F2

COS8

VCcJ2

Jl1

INITPAe#

F12

Ll0

SINO

VecJ2

Bl0

A2

FlO

F3

eOS7

Vee/2

Kl

COSO

VCcJ2

Ll1

GNO

GNO

NOTES:

1. Vee/2 (2.7V :1:10%) used for outputs only.

4. 0.1pF (min) capacitor between Vee and GND per p08ftion.

2. 47KO (:1:20%) resistor connected to all pins except Vee and GND.

5. FO = 100kHz :1:10%, F1 = FO/2, F2 - F1/2 ... , F11 = F10/2, 40% - 60%
Duty Cycle.
6. Input voltage limas: VIL = O.BV Max VIH = 4.5V :1:10%

3. Vee = 5.SV ±C.5V.

5-40

HSP45106/883
Die Characteristics
DIE DIMENSIONS:
251 x 240 x 19 ±1 mils

DIE ATTACH:
Material: Silver Glass

METALLIZATION:
Type: Si-A/ or Si-A/-Cu
Thickness: akA
GLASSIVATION:
Type: Nitrox
Thickness: 10kA

Metallization Mask Layout
HSP451 06/883

o
o

>

...

0

co

0

PMSEL
MODO
MODi
MOD2
TEST
VCC
WR#
GND
CS#
ENCFREG#
ENOFREG#
INHOFR#
ENTIREG#
INITTAC#
ENPOREG#
ENPHAC#
PACI#
INITPAC#
BINFMT#
PAR/SER#
VCC

5-41

'"a:

W
.... N

eez:'"
w
c::I
_:I;

"' ....z:
>'"

I
I

HSP45106/883
Packaging t
85 PIN GRID ARRAY (PGA)

t-----,:;~,,~
.--+m@@@@@@@@@

@@@@@@@@@@@K
@@
@@@
@@J
@@
@@ H
@@@
@@@G
@@@
@@@F
@ @ @ INDEX PIN @ @ @ E
@@ /
@@ D
@@e @@@
@@ c
@@@@@@@@@@@s
@@0.@@@@@®€)A
9

10

11

.100

L

J

L

sse

.080
.120

.003 MIN

LEAD MATERIAL:. Type B
LEAD FINISH: Type C
PACKAGE MATERIAL: Ceramic, AI203 90%
PACKAGE SEAL:
Material: Gold/Tin
Temperature: 3200C ± 100 C
Method: .Furnace Braze

NOTE: All DImensiOns are

..M!!:!...
Max

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic Wedge
COMPLIANT OUTLINE: 38510 P-AC

tMil-M-38510 Compliant Materials, Finishes, and Dimensions.

,Dimensions are In inches.

5-42

Ell HARRIS

HSP45102

PRELIMINARY
12-Bit Numerically Controlled Oscillator

May 1991

Features

Description

• 33M Hz, 40MHz, 50MHz Versions

The Harris HSP45102 is a 12 bit Numerically Controlled
Oscillator (NC012) for Direct Digital Synthesis Applications
where low cost is important. As shown in the block diagram,
the chip consists of a Frequency Control Section, a 32 bit
phase accumulator, a phase offset adder and a Sine ROM.

• 32-Bit Frequency Control
• Binary FSK Modulation
• Quadrature Phase Modulation

Two frequency control words are loaded serially, MSB or
LSB first. A Single control pin, SELLlM#, selects which
word is used to determine the output frequency. This pin is
toggled for FSK modulation. The output of the Frequency
Control Section is two 32 bit phase increments to the Phase
Accumulator, of which one is selected using SELLlM#.

• Serial Frequency Load
• 12-Bit Sine Output
• Offset Binary Output Format
• O.012Hz Tuning Resolution at 50MHz
• Spurious Frequency Components < -69dBc
• Fully Static CMOS
• Available in 28 Pin DIP and 28 Pin SOIC
• Low Cost

Applications

The 13 bit output of the Phase Offset Adder is mapped to
the sine wave amplitude via the Sine ROM. The output data
format is offset binary to simplify interfacing to D/A
converters. Spurious frequency components in the output
sinusoid are less than -69dBc.
The NC012 has applications as a Direct Digital Synthesizer
and modulator in low cost digital radios, satellite terminals,
and function generators.

• Direct Digital Synthesis
• Modulation -

Two pins are provided for phase modulation. These two
bits, PO-1, are encoded and added to the top two bits of the
phase accumulator to offset the phase in 900 increments.

QPSK and FSK

CI'lI

a:
W

.... N

cczCl'll

w
c:l
_:z::
CI'lI I Z

Block Diagram

~

CLK
PO -1
MSBILSB#_
SFTEN#_
SD_
SCLK_

FREQUENCY
CONTROL
SECTION

~

~

PHASE
ACCUMULATOR

L
~

PHASE
OFFSET
ADDER

4

SINE
ROM

12
aUTO -11

~~~: ----1 J If

ENPHAC#~
SEL..LJM#

Copyright

© Harris Corporation 1991

File Number
5-43

2810

HSP45102

Pinout
28 PIN DIP, 28 PIN sOle
TOP VIEW
OUT6

OUT5

oun

OUT4

OUT8

OUT3

OUT9

OUT2

OUT10

OUT1
OUTO

OUT11

vee

GND

GND

VCC
SEL:l.JM#

PO

SFTEN#

P1

MSBILSB#

LOAD#

ENPHAC#

TXFR#

SD

eLK

SCLK

GND

Pin Description
NAME

PIN
NUMBER

VCC

8,22

GND

7,15,21

PO-1

19,20

I

TYPE

DESCRIPTION
+5V power supply pin.
Ground
Phase modulation inputs,(become active after a pipeline delay of four clocks). A phase shift
of 0, 90, 180, or 270 degrees can be selected (Table 1).

CLK

16

I

NCO clock.,(CMOSJevel)

SClK

14

I

This pin clocks the frequency control shift register.

SELL/M#

9

I

A high on this input selects the least significant 32 bits of the 64 bit frequency register as
the Input to the phase, accumulator; a low selects the most significant 32 bits.

SFTEN#

10

I

The active low input enables the shifting of the frequency register.

MSB/lSB#

11

I

This input selects the shift direction of the frequency register. A low on this input shifts in the
data lSB first; a high shifts in the data MSB first.

ENPHAC#

12

I

This pin, when low, enables the clocking of the Phase Accumulator. This input has a pipeline delay of four clocks.

SO

13

I

Data on this pin is shifted Into the' frequency register by the rising edge of SCLK when
SFTEN# is low.

TXFR#

17

I

This active low input is clocked onto the chip by ClK and becomes active after a pipeline
delay of four clocks. When low, the frequency control word selected by SELL/M# is
transferred from the frequency register to the phase accumulator's input register.

LOAD#

18

I

This input becomes active after a pipeline delay of five clocks. When' low, the feedback In
the phase accumulator is zeroed.

OUTO-11

1-6,23-28

a

Output data. aUTO is lSB.

All Inputs are TTL level, with the exception of elK.
# sign designates active low signals.

5-44

HSP45102

Functional Description
The NC012 produces a 12 bit sinusoid whose frequency
and phase are digitally controlled. The frequency of the sine
wave is determined by one of two 32 bit words. Selection of
the active word is made by SELl/M#. The phase of the
output Is controlled by the two bit input PO-1, which is used
to select a phase offset of 0 0 , 90 0 ,1800 , or 2700 .
As shown in the Block Diagram, the NC012 consists of a
Frequency Control Section, a Phase Accumulator, a Phase
Offset Adder and a Sine ROM. The Frequency Control
section serially loads the frequency control word into the
frequency register. The Phase Accumulator and Phase
Offset Adder compute the phase angle using the frequency
control word and the two phase modulation inputs. The Sine
ROM generates the sine of the computed phase angle. The
format of the 12 bit output is offset binary.
Frequency Control Section
The Frequency Control Section (Figure 1), serially loads the
frequency data into a 64 bit, bidirectional shift register. The
shift direction is selected with the MSB/LSB# input.
When this input is high, the Jrequency control word on the
SD input is shifted into the register MSB first. When
MSB/LSB# is low the data is shifted in LSB first. The
register shifts on the rising edge of SCLK when SFTEN# is
low. The timing of these signals is shown in Figure 2.

32 bits of the frequency control word. For example, if the
control word is 20000000 hexadecimal and the clock
frequency is 3OMhz, then the output frequency would be
Fclk/8 or 3.75Mhz.
The frequency control multiplexer selects the least
significant 32 bits from the 64 bit frequency control register
when SELl/M# is high, and the most significant 32 bits
when SELl/M# is low. When TXFR# is asserted, the 32
bits selected by the frequency control multiplexer are
clocked into the phase accumulator input register. At each
clock, the contents of this register are summed with the
current contents of the accu mulator to step to the new
phase. The phase accumulator stepping may be inhibited
by holding ENPHAC# high. The phase accumulator may
be loaded with the value in ttie input register by asserting
LOAD#, which zeroes the feedback to the phase
accumulator.
The phase adder sums the encoded phase" modulation bits
PO-1 and the output of the phase accumulator to offset the
phase by 0, 90, 180 or 270 degrees. The two bits are
encoded to produce the phase mapping shown in Table 1.
This phase mapping is provided for direct connection to the
in-phase and quadrature data bits for QPSK modulation.
TABLE 1

The 64 bits of the frequency register are sent to the Phase
Accumulator Section where 32 bits are selected to control
the frequency of the sinusoidal output.

PO-1 CODING
P1

PO

PHASE SHIFT (DEGREES)

Phase Accumulator Section

0

0

0

The phase accumulator and phase offset adder compute
the phase of the sine wave from the frequency control word
and the phase modulation bits PO-1. The architecture is
shown in Figure 1. The most significant 13 bits of the 32 bit
phase accumulator are summed with the two bit phase offset to"generatethe 13 bit phase input to the Sine Rom. A
value of 0 corresponds to 0 0 , a value of 1000 hexadecimal
corresponds to a value of 1800.

0

1

90

1

0

270

1

1

180

The phase accumulator advances the phase by the amount
programmed into the frequency control register. The output
frequency is equal to N*Fclk/232 , where N is the selected

en

a:

LU

.... N

<:zen
LU
I".:l
_:J:

en

ROM Section
The ROM section generates the 12 bit sine value from the
13 bit output of the phase adder. The output format is offset
binary and ranges from 001 to FFF hexadecimal, centered
around 800 hexadecimal.

5-45

I-

:z

~

HSP4'5tIJ2
PHASE OFFSET ADDER

,..
"

R.PO,l

R
E
G,

13 MSB'S

!l'NE
ROM

2,.DI.:Y,
R.,
E .

OUTO,ll

G

.

:r

I
I
I

'0'

I '
I

,32 •

R.LOAD#

r

. ,A

ACCUMULATOR
INPUT .,
REGISTER'

I
I

o
o

E
R

SD'+I..-+-I-+.--I

~

SFTEN#
, MSBA.SB #

..,..-_--1.

II

1_ _ _ _ _

J l_

~

(HIGH SELECTS FRCTRLO - 31,'
:"OW

,SELECTSFRCTRL32~~ _ ~ _.~ ~ _ ~'_
PHASE ACCUMULATOR

,

PO ·1
R.PO -1
ENPHAC#, 4 - DLY 1')-,":"::;=":':'::=1:
TXFR#,
R,
E'
LOAD # ,
G'
CLK

R.LOAD.#

CLK

FIGURE 1. NCO-12 FUNCTIONAL BLOCK DIAGRAM

SCLK~~

.'

'~.

SO.~~

MSBA.S~

___

~
__~__________~"~____________~;:==

CLK
TXFR#
SEL.IJM#

ENPHAC#

OUTO -11

~'<-_--"'-.J''-'''-.J''--''''''-.J''--''''''-.J'-''''''-'
FIGURE 2. I/O TIMING

5-46

I
I

I
I
'1
I
I
I
I

J

Specifications HSP45102
Absolute Maximum Ratings
Supply Voltage ....•.•••••.................•••••.......•••.•....•..........•••.•••.•.••••••••...••..••.•.......• +8.0V
Input, Output or I/O Voltage Applied ...........••.•.....•..•••••..•..........•...•••......•••••.. GND -0.5V to VCC +0.5V
Storage Temperature Range •••••................••••.••...••••....... " .........•••••..•••••.•....... -65 0 C to +1500 C
Junction Temperature ........................................................................•.••••..•.••..... +1500 C
Lead Temperature (Soldering, Ten Seconds) .......•.•..•.....••••.•.....•..•........•••••......•......•......... +3000 C
ESD Classification •.•.••....•••••............••.••••••••...•••..•.....•..•••.•...••••••••......••••.•••...••••• Class 1
CAUTION: Stresses above those listed in the IIAbsolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range •....•••••.•.......•.•••....•••••••.••..•...••.••••.••••.••••.••••.•.•....•.• +4.75Vto +5.25V
Operating Temperature Range ••••..••........•........•....•......•••.••••........•....•....••••••••..•.• OoC to + 700C

D.C. Electrical Specifications
SYMBOL

PARAMETER

MIN

MAX

UNITS

TEST CONDITIONS

VIH

Logical One Input Voltage

2.0

-

V

VCC=5.25V

VIL

Logical Zero Input Voltage

-

0.8

V

VCC=4.75V

VIHC

High Level Clock Input

3.0

-

V

VCC= 5.25V

VILC

Low Level Clock Input

-

0.8

V

VCC=4.75V

VOH

Output HIGH Voltage

2.6

-

V

10H = -400flA, VCC = 4.75V

VOL

Output LOW Voltage

-

0.4

V

10L = +2.0mA, VCC = 4.75V

II

Input Leakage Current

-10

10

f1A

VIN = VCC or GND, VCC = 5.25V

10

I/O Leakage Current

-10

10

f1A

VOUT = VCC or GND,
VCC=5.25V

ICCSB

Standby Power Supply Current

-

500

f1A

VIN = VCC or GND
VCC = 5.25V, Note 3

ICCOp

Operating Power Supply Current

-

TBD

mA

f=33MHz, VIN =VCCorGND
VCC = 5.25V, Noles 1 and 3

Capacitance (TA = +250 C, Note 2)
SYMBOL

MIN

MAX

UNITS

CIN

Input Capacitance

PARAMETER

-

10

pF

Co

Output Capacitance

-

10

pF

TEST CONDITIONS
FREQ = 1 MHz, VCC = Open,
All measurements are referenced
to device ground

NOTES:
1. Power supply current is proportional to operating frequency. Typical
rating for ICCOp is 10mAlMHz.

3. Output load per test load circuit with switch open and CL = 40pF.

2. Not tested, but characterized at initial design and at major process/design
changes.

5-47

Specifications HSP45102
A.C. Electrical Specifications

SYMBOL

(Note 1)

PARAMETER

-33 (33MHz)

-40 (40MHz)

-50 (50MHz)

MIN

MAX

MIN

MAX

MIN

MAX

TCp

Clock Period

30

-

25

-

TCH

Clock High

12

-

-

20

10
10

18

-

15

-

Hold Time SFTEN#, MSB/lSB#
from SClK going high

0

-

0

TSS

Set-up Time SClK high to ClK
going high

23

-

TpS

Set-up Time PO-1 toClK going high

18

TpH

Hold Time'PO-1 from ClKgoing high

0

TES

Set-up Time lOAD#, TXFR#,
ENPHAC#, SEL-LlM# to ClK
gOing high.

TEH

Hold Time lOAD#, TXFR#,
ENPHAC#, SEL-LlM# from ClK
going high

TOH
TRF

TCl

Clock low

12

TSW

SCLI( High/Low

16

TDS

Set-up Time SO to SClK going high

15

TDH

Hold Time SO from SClK going high

0

TMS

Set-up TUne SFTEN#, MSB/lSB#
to SCLI( going high

TMH

14
13

COMMENTS
'ns

-

8
8

ns
ns

-

13
12

ns
ns
ns

12

-

-

0

-

ns

20

-

15

-

ns, Note 2

-

15

-

12

18

-

15

-

12

-

ns

0

-

0

-

0

-

ns

elK to Output Delay

2

20

2

16

2

12

ns

Output Rise, Fall Time

TBD

-

TBD

-

TBD

-

ns, Note 3

0

0

0

ns

-

0

ns
ns

NOTES
1. A.C. testing is performed ss follows: Input levels (ClK Input) 4.0V and OV;
Input levels (all 'other inputs) OV and 3.0V; Timing reference levels (ClK)
2.0V; All others 1.5V.lnput 'rise and fall times driven at 1nsN. Output load
per test load circuft wHhswitch 'closed and Cl = 40 pF. Output trans,Hion
is measured at VOH ~ 1.5V and Vol::' 1.5V.

2. If TXFR# Is active, care must be taken to nol violate set-up and hold times
as d'ata from the shift registers may not have settled before ClK occurs.
3. Controlled via design or process parameters and not directly tested. Charac·
terized upon inHial design and after majOr process and/or design changes.

A.C. Test Load Circuit
,- -

'I

-c-- -

-

-

-

-

-

~,-

-

--

"

1
1

I

I

1

1

I
I

I
I

1

I

I

I

:
*TEST HEAD
CAPACITANCE

1.5V

I

_

_

t

IOl

_

1
1 _ _ _ _EQUIVALENT
_ _ _ _CIRCUIT
_____

Switch 51 open for ICCSS and ICCOp

5-48

:
1

_

J

HSP45102
Waveforms

CLK

PO -1

LOAD#. TXFR#.

TES

TEH

ENPHAC#,.SEL.I..JM.#

OUTO -11

TSW
SCLK
TOS

TOH

SO
TMS

TMH

MSBILSB#,

en

....a:

.... N

<
zen
c.:I ....
_:c

.... !Z
~

5-49

SPECIAL FUNCTION
PAGE
DATA SHEETS
HSP45240

Address Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

6-3

HSP45240/883

Address Sequencer..................................................... ......

6-14

HSP9501

Programmable Data Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

6-21

HSP9520/9521
ISP9520/9521

Multilevel Pipeline Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

6-28

HSP45256

Binary Correlator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

6-33

6-1

HSP45240

EIIHARRIS

Address Sequencer

May 1991

Features

Description

• Block Oriented 24-Bit Sequencer

The Harris HSP45240 is a high speed Address Sequencer
which provides specialized addressing for functions like
FFT's,1-0 and 2-D filtering, matrix operations,and image
manipulation. The sequencer 'supports block oriented
addressing of large data sets up to 24 bits at clock speeds
up to 50MHz.

• Configurable as Two Independent 12-Bit
Sequencers
• 24 x 24 Crosspoint Switch
• Programmable Delay on 12 Outputs

Specialized addressing requirements are met by using the
onboard 24 x 24 crosspoint switch. This feature allows the
mapping of the 24 address bits at the output of the address
generator to the 24 address. outputs of the chip. As a result,
bit reverse addressing, such as that used in FFT's, is made
possible..

• Multi-Chip Synchronization -Signals
• Standard ",p Interface
• TTL Compatible Inputs/Outputs
• 100pF Drive on Outputs
• DC to 50MHz Clock Rate
• Available in 68 Pin PGA and·PLCC Packages

Applications

A single chip solution to read/write addressing is also made
possible by configuring the HSP45240 as two 12-bit
sequencers. To compensate for system pipeline delay, a
programmable delay is provided on 12 of the address
outputs.
The HSP45240 is manufactured using an advanced CMOS
process, and is a low power fully static design. The configuration of the device is controlled through a standard
microprocessor interface and all inputs/outputs, with the
exception of clock, are TTL compatible. The Sequencer is
available in 68 pin PGA and PLCC packages..

• 1-0,2-0 Fittering.
• Pan/Zoom Addressing
• FFT Processing
• Matrix Math Operations

Block Diagram"
~----------------------------------------------------------------+-STNrrOUT~

r-------------------------------------------------------------+

AOOV~
OONE~

BLOCKDONE#
0UT12- 23
STARTIN ~

STNrr
CIRCUITRY

SEQUENCE
GENERATOR

24

1--"'-.:--11

CROSS- POINT
SwrrCH

1...-_ _ OEH#

12
OUTo- 11
OLYBLK
1...-_ _ OEL#
BUSY~

DO- 8,

cs~.

AD,

WR~.

CLK.

RST~

CAUTION: Electronic devices are sensHiv. to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

6-3

File Number

2489

...... z
<2
IUu

""z

~~

HSP45240
-~

,h

. .

.,'

'pJckagjjJ:Piribirts'";"

;,NADDRESS SEQUENCER HSP45240
68 PIN PLASTIC LEADED CHIP CARRIER (PLCC)
~ ~

==

~ ~

~ ~

~.

~

~55855~§§8~~~§§~O
~OO>oo~oo>55~oo5z

NC

DO
01

02
03
Q4

VCC

05
06

OUT8

OUT1D
OUT9

'GNO

,wR#'

GNO,

'k

OUT7

0'

OUT6

"AD

CS#

GNO
CLK

OUT4

VCC

GNO

,RST#

OUT3

NC

NC
~~~~~.~M~~D~$~~~~

§ $ ~~
~~~i~~·'$1!~~~ 5
t'Hj6~B~ '~~~ 0 0
~ ~ ~
Ig
Q

I/)

I/)

""
CD

68 PIN GRID ARRAY (PGA)
(BOTTOM VIEW)
"

GND

ADD BUSY. DON,,#,
VAl#

OUT1

OUT2

Ne

OUTO

VCC

Ne

Ne

RST.

Vee

GND

H

CLK

GND

OUTS

Vce

,,8'

e,S#

AO

'OUTe

OUp'

~

WAN

GND

E

De

05

0

04

03

OUT10

e

02

01

GND

OUT12

B

DO

NC

OUT22

OUT21

GND

OUT18

OUT17

GND

Ne

Ne

GND

OUT23

Vee

OUT20

OUT19

Vee

OUTle

2

3

4

5

e

7

8

,,/

,

A

0,

START
IN.

0El#

BLOCK
DONE#

VCC

Ne

K

,

DLYBLK START
OUT.

OEIi#'

L

,

"

.......

'

OUT3

"OUT,4

,

GND",

", :.oU'Ill

~. ""'

I

OUT14

oute

Vee

OUTll, ,

OUllS OUT13
9

10

11

",-,

j"

,";":

6-4

HSP45240
Pin Descriptions
PLCC
PIN
NUMBER

DESCRIPTION

NAME

TYPE

VCC

I

6,24,34,41
49,55,68

+5V power supply pin.

GND

I

3,9,18,22
38,46,52
58,65

GROUND

RST#

I

25

RESET: The "RST#" signal is a TIL, asynchronous input which causes the switch to be
configured in a 1:1 mode; After "RST#" has been asserted and then taken away, it will take
26 clocks to configure the switch. During the 26 clocks after rstB has been de-asserted,
"WR#" will be disabled to the chip. The clock must be running during reset.

CLK

I

23

CLOCK: The "CLK" signal is a CMOS input which provides the basic timing for address
generation.

WR#

I

19

WRITE: This asynchronous input is used to clock the data on DO-6 into the address
counter or the switch and configuration registers.

CS#

I

21

CHIP SELECT: A "low" on this jnput enables the data on DO-6 to be clocked into the
address counter or the switch and configuration registers. This input is synchronous
to "WR#".

AO

I

20

Address 0: AO being High enables DO-5 to be written to the Address Counter, AO being
Low enables DO-5 to be written to the Configuration Registers. This signal is·
synchronous to "WR#".

DO-6

I

11-17

DATA BUS: The Data Bus lines are input only, and are used to input address and data to
the configuration registers for the switch and sequencer. These are latched inputs, and are
synchronous to "WR#".

OEH#

I

28

OUTPUT ENABLE HIGH: This asynchronous input is used to enable the output buffers for
OUT12-23.

OEL#

I

29

OUTPUT ENABLE LOW: This asynchronous input is used to enable the output buffers for
OUTO-11.

STARTIN#

I

31

START-IN: This synchronous Input is used for synchronizing several of these chips
together. This pin is tied to "STARTOUT#" of a-master sequencer chip when cascading
two or more chips together.

DLYBLK

I

30

DELAY BLOCK: This synchronous input is sampled every clock. If it is "high" at the end
of a block, the next block of addresses will not be sequenced until this line goes "low". The
sequence will be resumed 5 clocks after "DLYBLK" has been de-asserted.

OUTo-23

0

39,40,42,45,
47,48,50,51,
53,54,56,57,
59,62-64,66,
67,1,2,4,5,
7,8

OUTPUT BUS: Addresses tha\ are being generated are output on this bus. Output
"OUTo-l1" have a user programmable delay. This bus can be tristated with "OEH#" and
"OEL#".

BLOCKDONE#

0

36

BLOCK DONE: This output is used as a flag for completion of a block of addresses within
a sequence. It is valid for one clock when the end of a block is reached
within a sequence, and will remain low when a sequence is completed.

DONE#

0

37

DONE: This output Is used as a flag for completion of a sequence of addresses. If the chip
is programmed In Continuous Mode, this signal will never become active. If One-Shot mode
with Restart Is selected, the flag will go active for one clock and then go inactive. -

ADDVAL#

0

33

ADDRESS VALID: This output is used as a flag to indicate when the first valid address is
available at the output pads.

STARTOUT#

0

32

START-OUT: This output Is used for synchronizing several of these chips together. When
an internal "start" has been generated or a restart, this signal will pulse "low". This Signal
is tied to "STARTIN#" of slave sequencer chips.

BUSY#

0

35

This output will go low, and stay low during a reset to the chip. While this signal is low,
all writes to the chip will be disabled. This signal will go inactive 28 clocks after
"RST#" goes high.

# Denotes active low.

6-5

..... z:

-ce5?
....
Wz:

Uu

~~

Functional Description

block. The muxes are then configured to feed-back-the adder outpu~ along with the co_ntents of th_e "step ~ize" register

The Address Sequencer Is a 24"'bitprogrammable address
'generator. As shown in the Block Diagram, the sequencer for generation of the next,Ci,ddress.
consists of 4 functional blocks: the start circuitry, the When "block size" ':lumber of addresses have been gener'seql.Je"cegenerCl!c;>r,the cro~polnt swit~ti,al1jft!1e p[pces- ated, the block Is complete and the "blockidone" signal Is
sor interface. The addresses produced by the sequence as'serte~.Atthjs poi!!t, -tile muxes areconflgur9d to pass the
generator are input Into the crosspoint switch. The contents oi'the "block starfadQress" and "block step size'.'
'crosspoint switch maps 24 bits of address input to a 24 bit registers. The corresponding addition produces the ,first adoutput This allows for addressing schemes like "bit- dress of the next block. This address is stored in the "block
reverse" addressing for FFT's. A programmable delay block start address" register, and )he muxes are configured to
,is provided to allow. the MSW of the output to be skewed feed back the adder outpuf along witl) the contents of "step
from the LSW. This ,feature may be used to compensate for, size" register.
processor pipeline delay when the sequence generator Is The addre!!s SequElnCe Is complete when the programmed
configuredas'two-lndependent12 bit sequencers. Address' "number blOCks" have been generated. At this point the
Sequencer operation is controlled by values 10'Sded into' "done" .and "block done!' signals are asserted. In addition,
configuration- registers assOciated with the sequence gen- _' the sequencer-generator either halts or restarts addre' ssing
erator, crosspoint switch, and start circuitry. The configura- cjepending uporittle mode of operatiofl.
tion registers are"loaded through the processor interface.
The sequence generator is configured by programming five
Start Circuitry
'24-bit registers associated with ,add res,s generationanc;l
The start circuitry receives configuration data from the pro- one 6-bit register associated with mode of operation. The
cessor interface and is responsible for providing the configuration registers holding the address generation
"START" signal to li:leseqUence generator block,. The parameters conta~n the following: :
,"START'~ is produced internally througl)t the processor
1) Start Address
Interface, externally by the "STARTIN#" Input, or from a
2) BloCk Size - Number of addresses generated per
:restart issued by the sequence generator. If programmed
block'
for delay, internal/external, "START" and restarts for the
sequel)ce generator can be delayed from 1 to 31cinfigured'for.the first stage of
addres!!lng by writing Ii 0. to switch output register 2, a 2 to
!!witch output regi!!ter 1, and a 0. to switch output register 2.
These' values are loaded' by flr!!t, writing the add res!! of

6-10.

• x(O)
x(1)
x(2)
x(3)
x(4)
x(5)
x(6)
x(7)
FIGURE 7. COMPLETE EIGHT-poniJT IN-PLACE
DECIMATION-IN-FREQUENCY FFT.

Specifications HSP45240
Absolute Maximum Ratings
Supply Voltage ......•••................•.•....•••.........•••...............•...•..........••..••............•. +8.0V
Input, Output or I/O Voltage Applied .••••••••..•••••••••.••.••.•.......•••••.••..........•.••••.. GND-0.5V to VCC+0.5V
Storage Temperature Range ....•......•...•............••........•.................................•. -65 0 C to +1500C
Maximum Package Power Dissipation at + 700 C .........••..............•.••.••.•..........••• 1.86W (PLCC), 2.84W (PGA)
9jc ......•••...•••.•.....••...•.•...•........•.•••...••..•.•.•.••••••.••••••...•••.• 15.1 0C/W (PLCC), 10.1 oCIW (PGA)
9ja .....••.•...•.......•......•....•......••...••............••••.•.•..........•••.. 43.1 0 CIW(PLCC),37.1 0 CIW(PGA)
Gate Count •.....•.....•••.................•.............•.....•...........••..•••............•.•.•....... 8388 Gates
Junction Temperature •.....•.•.....••••••.•...•••••••••••........•...•••.•....•......... +l50o C (PLCC), +1750 C (PGA)
Lead Temperature (Soldering, Ten Seconds) •.•.••••••••.•.•..•.......•.•••.............•....•........•••........ +3000C
ESD Classification ...•....•••••.•..•.......••..........•..........•..............•.........•........•••......... Class 1
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device .. This is a stress only rating.and
operation of the device at these or any other conditions above those indicated ·in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range •••......•...........••••.................•.........•....•••••.....•....•...••••.•. +5.0V ± 5%
Operating Temperature Range ....•.•.•.••••........•••••••••••.•...............•..........•.••..•.•...... OOC to + 700C

D. C. Electrical Specifications (Vcc = 5.0V + 5%, TA = OOC to +700 C)
PARAMETER

SYMBOL

MIN

MAX

UNITS

Logical One Input Voltage

VIH

Logical Zero Input Voltag.e

VIL

2.0

-

V

VCC=5.25V

-

0.8

V

VCC=4.75V

VIHC

3.0

-

V

VCC=5.25V,

Low Level Clock Input

VILC

-

0.8

V

VCC=4.75V

Output HIGH Voltage

VOH

2.6

-

V

10H

Output LOW Voltage

VOL

-

0.4

V

10L = +2.0mA, VCC = 4.75V

Input Leakage Current

II

-10

10

.,A

VIN = VCC or GND, VCC = 5,25V

I/O Leakage Current

10

-10

10

.,A

VOUT = VCC or GND, VCC = 5.25V

Standby Power Supply
Current

ICCSB

-

500

.,A

VIN = VCC or GND,
VCC = 5.25V, Outputs open

Operating Power
Supply Current

ICCOp

-

99

rnA

f=33MHz,
VIN = VCC or GND, VCC = 5.25V,
Outputs Open, (Note 1)

Input Capacitance

CIN

-

10

pF

Output Capacitance

Co

-

10

pF

f = 1 MHz, VCC = Open,
all measurements are referenced
to device GND. (Note 2):

High Level Clock Input

TEST CONDITIONS

= -400.,A, VCC = 4.75V

NOTES:
1. Power supply current is proportional to operating frequency. Typical
rating for ICCOp Is 3mA/MHz.

2. Not tested, but characterized
process/design changes.

at ,.,Initial

design

and

at. major

Specifications HSP45240
A. C. Electrical SpecificatIons

(VCC = 5.0V

+ 5%. TA = OOC to +700 C) (Note 2)

TEST
CONDITIONS

Hold Till)eDO-6 from
WR#High

TDf..,

:0,

0

Set-up Time AO. CS#. to
WR#Low

TAS

5

5

0

0

0

0

Hold Time AO. CS#. from
WR#High

TIH

,

' ns

"

ns

ns

Clock to Output Prop.
Delay on OUTO-23

TpOO

15

13

ns

Clock to Output Prc5ii. '
Delay on,STAAT.QUT.4t.
BLKDONE;#,DONE#.
ADDVAL#,and BUSY#'

TpDS

15

'13

ns

1. Controlled by de;,ig~' or ,!?rocess 'Pa;ain~ers and not direclly tested.
Characterized 'upon Inilial design and after major process and/or design
"',
"
changes:

2. A.C. Tesling is performed ail follows: Input levels (ClK Input) = 4.0V and
, oV;lnpii\ levels (All other InpulS) = oV and 3.0V; Input liming
ief.rence level.: (ClK) - 21JV. (Others) - 1.5V; Output liming references:
VOH'~ 1.5V;VOl ~ l.6V; Input'iise arid fall time. driven"8i 1 nsN::'
'

A.C. Test Load Circuit,

r - - - - - - -'- - - - -'---,

I
I

I
'~~"!cO;;::~EAND I

EQUIVALENT CIRCUIT

I
I
I
I
I
I
I
I
I

_ _ _ _ _ _ _ _ _ _ _ --1

"Test Head Capacftance
SwHch Sl Open for ICCSB and ICCOp Tests.

OUTPUT PIN

CL

BlOCKDONE#'
DONE#'
ADDVAl#'
STARTOUT#
BUSY#'

40pF

OUTo-23

100pF

HSP45240
Timing Diagrams

t

CLK _ _ _ _

~

j

,cHT 'c,-*---TCp

CLOCK AC PARAMETERS

DATA SETUP AND HOLD

ADDRESS/CHIP SELECT SETUP AND HOLD

WR# AC PARAMETERS

%

CLK~

---f

STARTIN#'
DLYBLK _ _ __

TIS

+

,,~

TIH

Jc

CLK----'

~~~g~~:
DONE#
ADDVAL#

.... z:

--i--,

<2

- - i - _J

~~

-

Wz:

BUSY#
INPUT SETUP AND HOLD

OUTPUT PROPOGATION DELAY

J
OUTPUT ENABLE, DISABLE TIMING

OUTPUT RISE AND FALL TIMING

6-13

I-

e.:>e.:>

~.8V
'W

TORF

mHARRIS - HSP45240/883
Address Sequencer

May 1991

Features

Description

• This Circuit Is Processed in Accordance to Mil-Std883 and is Fully Conformant Under the Provisions
of Paragraph 1.2.1.

The Harris HSP45240 is a high speed Address Sequencer
which provides specialized addressing for functions like
FFT's, 1-D and 2-D filtering, matrix operations, and image
manipulation. The sequencer supports block oriented
addressing of large data sets up to 24 bits at clock speeds
up to 4OMHz.

• Block Oriented 24-8it Sequencer
• Configurable as Two Independent 12-8it
Sequencers

Specialized addressing requirements are met by using the
onboard 24 x 24 crosspoint switch. This feature allows the
mapping of the 24 address bits at the output of the address
generator to the 24 address outputs of the chip. As a result,
bit reverse addreSSing, such as that used in FFT's, is made
possibie.

• 24 x 24 Crosspoint Switch
• Programmable Delay on 12 Outputs
• Multi-Chip Synchronization Signals
• Standard liP Interface

A single 9hip solution to read/write addressing is also made
possible by configuring the HSP45240 as two 12-bit
sequencers. To compensate for system pipeline delay, a
programmable delay is provided on 12 of the address
outputs.

• TTL Compatible Inputs/Outputs
• 100pF Drive on Outputs
• DC to 40MHz Clock Rate
• Available in 68 Pin PGA Package

The HSP45240 is manufactured using an advanCed CMOS
process, and is a low power fully static deSign. The configu·
ration of the device is controlled through a standard
microprocessor interface and all inputs/outputs, with the
exception of clock, are TTL compatible. The Sequencer is
available in a 68 pin PGA package.

Applications
• 1-D, 2-D Filtering
• Pan/Zoom Addressing
• FFT Processing
• Matrix Math Operations

Block Diagram
STARTOUT#'

r-------------------------------------------------------------+

ADDV~
DONE#"
BlOCKDONE#'
OUT12 ·23

STARTIN #'

START
CIRCUITRY

SEQUENCE
GENERATOR

24

1-"':::'...,...-01

CROSS, POINT
SWITCH

' - - - - - - OEH#'
OUTO·11

DlYBLK
'---"..;-- OEl#'
BUSY#'

DO • 6, CS#', AO, WR#', CLI<, RST#'

CAUTION: Electronic devices are sensilive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

6-14

File Number

2816

Specifications HSP45240/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ••••••••.•••.••.••••.•••.•.•••••.••••.•. +8.0V
Input, Output Voltage Applied ••••••••.. GND-0.5Vto VCC+0.5V
Storage Temperature Range ••••••••••••••••• -650 C to +1500 C
Junction Temperature •••••••••••••••••••••..•••.••.•• +175 0 C
lead Temperature (Soldering, Ten Seconds) .• '" .•.•••• +3000 C
ESD Classification ..................................... Class 1

Thermal Resistance
Dja
Djc
CeramicPGAPackage ••••••••••••. 37.1 0 C/W 10.1 0 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic PGA Package ••...••••..•.•••••••••••..•• 1.35 Watt
Gate Count •.•••.••.•.•.•..•••.......•••••••••.• 8,388 Gates

CAUTION: Stresses above those listed in f~Absolute Maximum Ratings" may cause permanent damage to the device. This;s a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range ••••.•••••••••••••..••• +4.5V to +5.5V
Operating Temperature Range •...••••...••.• -55 0 C to +1250 C
TABLE 1. D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Devices Guaranteed and 100% Tested

PARAMETER

SYMBOL

CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Logical One Input
Voltage

VIH

VCC"'5.5V

1,2,3

-550 C $.TA$. +1250 C

2.2

-

V

Logical Zero Input
Voltage

VIL

VCC"'4.5V

1,2,3

-550 C $.TA $. +1250 C

-

0.8

V

Output HIGH Voltage

VOH

10H '" -400,.A
VCC '" 4.5V (Note 1)

1,2,3

-550 C$.TA$. +1250 C

2.6

-

V

Output LOW Voltage

VOL

IOL",+2.0mA
VCC '" 4.5V(Note 1)

1,2,3

-550 C $.TA$. +1250 C

-

0.4

V

Input Leakage Current

II

VIN '" VCC or GND
VCC"'5.5V

1,2,3

-550 C $. TA $. +1250 C

-10

+10

,.A

Output Leakage
Current

10

VOUT",VccorGND
VCC",5.5V

1,2,3

-550 C.::;TA.::;+1250 C

-10

+10

,.A

Clock Input High

VIHC

VCC"'5.5V

1,2,3

-550 C $.TA$. +125 0 C

3.0

-

V

VCC"'4.5V

1,2,3

-550 C $.TA$. +1250 C

V

1,2,3

-550 C $.TA$. +1250 C

-

0.8

VIN '" VCC or GND
VCC",5.5V,
Outputs Open

500

,.A

Clock Input Low
Standby Power Supply
Current
Operating Power
Supply Current
Functional Test

VILC
ICCSB

ICCOp

FT

-I

f",33MHz
VCC '" 5.5V (Note 2)

W

1,2,3

-550 C $. TA $. +1250 C

-

99

7,8

-550 C $.TA$. +1250 C

-

-

(Note 3)

mA

NOTES:
1. Interchanging of force and sensa cond itions is permitted.
2. Operating Supply Current is proportional to frequency. typical rating is
3mAlMHz.

3. Tested as follows: f = 1MHz. VIH = 2.6, VIL = 0.4, VOH ~ 1.5V, VOL $.
1.5V. VIHC = 3.4V, and VILC = O.4V.

6-15

Z

-<5!
.....
Uu
z

~i:c

Specifications HSP45240/883
TABLE 2. A.C. ELECTRICAL PERFORMANCE CHARACTERISTics'
Device Guaranteed and 100% Tested
'.
UMITS

PARAMETERS

SYMBOL

CONOITIONS

~33(33MHz)

-40 (40MHz)

MIN

MIN

MAX

UNITS

25

ns

GROUP A
SUBGROUP

TEMPERATURE
-550C~TA~+12SOC

30

MAX

Clock Period

TCp

9,10,11

Clock Pulse Width High

TCH

9,10,11

-550 C  TA

:s + 125°C

-

20

-

15

ns

Output Rise Time

TOR

1,2

-55OC!>TA~+1250C

-

3

ns

TOF

1,2

-55OC~TA!> +1250 C

-

5

Output Fall Time

5

-

3

ns

Input Capacitance

NOTES: 1. Parameters listed in Table 3 are controlled via design or process

2. Loading is as specKled in the test load circuit with CL

= 4OpF.

parameters and are nol directly tested. These parameters. are
characterized upon initial design and after major process and/or
deSign changes.

TABLE 4. ELECTRICAL TEST REQUIREMENTS
CONFORMANCE GROUPS

,

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

-

PDA

100%

1

FinalTest

100%

2,3, 8A,8B, 10, 1 1

Group A-

-

1,2,3, 7,8A,8B, 9,10,11

Samples/5005

1,7,9

GroupsC&D

..... z
<2
-I-

(,)(,)

W

z

3i~

.6-17

HSP4524 0/883
Burn-In Circuit
START
OEH#" "DLYBLM OUT#"

.L

G

START

ADD
BUSY#" DONE#"
VAL#"

OUT2

Ne

OUTO

Vee

Ne

OUT3

RST#"

"Vee

GND

OUT4

e"LK

GND

OUT5

Vee

OUTe

OUT7

GND

OUT8

:
·cs#

IN#"

"0
68 LEAD
PIN GRID ARRAY
BOTTON VIEW

F

WR#"

GND

E

D6

D.

OUTe

Vee

D

D4

03

ouno

OUT11

e

D.

Dt

GNO

OUT12

B

DO

Ne

OUT22

OUT21

GND

OUT23

Vee

GNO

BURN-IN
SIGNAL

PGA
PIN

PIN
NAME

DUT18

aun7

GND

OUT14

NC

Vee

OUT1a

OUT15

OUT13

8

9

OUT20 OUT1.

5

4

"'PIN
NAME

oun

Ne

A

PGA
"'IN

GND

Ne

K

H

OEL#"

BLOCK
DONE.#"

Vec

BURN-IN
SIGNAL

PGA
PIN

PIN
"I:'IAME

Ne

to

BURN-IN
SIGNAL

11

IPGA
PIN

PIN
NAME

BURN-IN
SIGNAL

A2

GNO

GND

B9

OUT14

Vecl2

Fl1

0UT8

Vee/2

K8

BUSYB

Vecl2

A3

'OlJT23

Vecl2

el

02

FlO

Gl

eSB

F5

K7

OONEB

Vecl2

A4

Vee

Vee

e2

01

F9

G2

AO

F6

K8

OUTO

Vee/2

AS

OUT20

vecl'(.

el0

GND

GNO

Gla

OUT6

Vee/2

K9

Vee

Vee

A6

0UT19

'vecl2

" ell

OUT12

Vecl2

Gl1

QUT7

'Vecf2

Kl1 OUT3

F12

Hl

eLK

A7

Vee

AS
A9

Vee

01

'04

OUT16

vecl2

02

03

Fl1

H2

OUT15

Vecl2

010

OUT10

Vee/2

Hl0

Al0

OUT13

Vecl2

011

OUT11

Vee/2

Bl

DO

F8

El

06

F7

B3

OUT22

Vecl2

E2

05

F13

Vecl2

OEHB

F13

FO

L2

GND

GND

L3

DLYBLK

Fll

OUT5

Vecl2

L4

STARTOUTB

Vecl2

Hll

Vee

Vee

L5

Vee

Vee

Jl

RSTB

F14

L6

BLoeKDONEB Vecl2

J2

Vee

Vee

L7

GND

GND

B4

OUT21

vecl2

El0

OUT9

vecl2

Jl0

GND

GND

La

OUTl

Vee/2

B5

GND

GND

Ell

Vee

Vee

Jll

OUT4

Vecl2

L9

OUT2

Vecl2

B6

OUT18

Vecf2

'Fl

WRB

F4

K3

OELB

F12

B7

0UT17

vee/2

F2

GND

GND

K4

STARTINB F6

B8

GND

GND

FlO

GND

GND

K5

ADVALB

vecl2

NOTES:
1. Vee/2 (2.7V·±1 G'lb) used for outputs only.

4. O.1j1F·(mln) capacitor between Vee and GND per position.

2. 47KO (±20'lb) resistor connected to all pins except Vee and GND.

5. FO -" 100KHz ±10'lb, F1 ~ FO/2, F2
60% Duty Cycle.

3. Vee - 5.5 ±O.5V.

= F1/2 •.••• , F11

~

6. Input .oKaga limits: VIL - O.8V max., VIH = 4.5V ±10%.

6-18

F10/2, 40%-

HSP4524 0/883
Metallization Topology
DIE DIMENSIONS:
186 x 222 x 19 ±1 mils
METALUZATION:
Type: SI - AI or Si-AI-Cu
Thickness: 8kA
GLASSIVATION:
Type: Nltrox
Thickness: 10kA
DIE ATTACH:
Material: Silver/Glass
WORST CASE CURRENT DENSITY:
1.8 x 105A/cm 2

Metallization Mask Layout
HSP45240/883

OUT12

DO

GND

0.1

OUT11

02
03

OUT10

04

vee
OUT9

05

OUT8

06

GND

GNO
WR#..

OUT7

AO

OUT6

vee

es#

OUTS

GNO

eLK
Vee

OUT4

GND
OUT3

•w •w
J:

0

oJ

0

~

oJ

~

C

•i= • <• >o en• z•w z•w czCI
Z

a:
~

VI

I-

:J

0

I-

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HSP45240/883
Packaging t
68 PIN GRID ARRAY (PGA)
SEATING. PLANE

1.140
1.180
1.000
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• DIP D~ TIN PLATE LEAD FlNISH APPLIES.

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LEAD MATERIAL: Type B .
LEAD FINISH: TyPe C
PACKAGE MATERIAL: Ceramic, AI293 90%
PACKAGE SEAL: ':
Material: Gold/Tin
Temperature: 3200C ± 100 C
Method: Furnace Braze'

INTERNAL LEAD WIRE:
. ,':' Material: Aluminum
:'Oiameter: 1~2p Mil"
Bondl~g Method: Ultrasonic Wedge
CONlPL,iANT OUTLINE: 38Pl0 P-AC

""

NOTE: All Dimensions are

t MII-M-38510 Compliant Malerials, Finishes, and Dimensions.

..M!!l.. . Dimensions ara in Inches.
Max

6-20

HSP9501

mHARRIS

Programmable Data Buffer

May 1991

Features

Description

• DC to 30MHz Operating Frequency

The HSP9501 is a 1O-Bit wide programmable data buffer
designed for use in high speed digital systems. Two
different modes of operation can be selected through the
use of the MODSEL input. In the delay mode, a programmable data pipeline is created which can provide 2 to
1281 clock cycles of delay between the input and output
data. In the data recirculate mode, the output data path is
internally routed back to the input to provide a programmable circular buffer.

• Programmable Buffer Length from 2 to 1281 Words
• Supports Data Words to 10-Blts
• Clock Select Logic for Positive or Negative Edge
System Clocks
• Data Recirculate or Delay Modes of Operation
• Expandable Data Word Width or Buffer Length

The length of the buffer or amount of delay is program med
through the use of the 11-bit length control input port
(LCO-10) and the length control enable (LCEN#). An
11-bit value is applied to the LCO-l0 inputs, LCEN# is
asserted, and the next selected clock edge loads the new
count value into the length control register. The delay path
of the HSP9501 consists of two registers with a programmable delay RAM between them, therefore, the value- programmed into the length control register is the desired
length - 2. The range of values which can be programmed
into the length control register are from 0 to 1279, which
in turn results in an overall range of programmable delays
from 2 to 1281.

• Three-State Outputs
• TTL Compatible Inputs/Outputs
• Low Power CMOS
• Available in 44 Pin PLCC Package

Applications
• Sample Rate Conversion
• Data Time Compression/Expansion
• Software Controlled Data Alignment
• Programmable Serial Data Shifting
• Audio/Speech Data Processing

Video/Image Processing
• l-H Delay Line of 910 NTSC, 1135 PAL or 1280
Samples:
~

High Resolution Monitor Delay Line

~

Comb Filter Designs

~

Progressive Scanning Display

~

TV Standards Conversion

~

Image Processing

CAUTION: These devices are sensHlve
Copyright © Harris Corporation 1991

Clock select logic is provided to allow the use of a positive
or negative edge system clock as the CLK input to the
HSP9501. The active edge of the CLK input is controlled
through the use of the CLKSEL input. All synchronous
timing (i.e. data setup, hold and output delays) are relative
to the clock edge selected by CLKSEL. An additional
clock enable input (CLKEN#) provides a means of disabling the internal clock and holding the existing contents
temporarily. All outputs of the HSP9501 are three-state
outputs to allow direct interfacing to system or multi-use
busses.
The HSP9501 is recommended for digital video processing or any applications which require a programmable
delay or circular data buffer.

to electrostatic discharge. Proper I.C. handling procedures should be followed.

6-21

File Number

2786

-JZ

<:!
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~~

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~

HSP9501

,

.....:.

.' ~"

.,,:,1-'1<:

.

Pinout
44 PIN PLASTIC LEADED CHIP CARRIER (PLCC)
TOP VIEW
...I

Iffi9 u~

I~

~

d g

Q

0
:;

010

000
001

011

002

012

003

013

004

014

Vec

Vce

GNO 1

GNO

005
006

016

007 1

Dl7

008 1

018

.,

0

Q

I~

.,

0

§ § § 9

....
9 9 g !!!
Q

U

Z

Block Diagram
010- 9

MOOSEL

CLKSEL_r----...,
CLKEN .#

10
LC 0 -10
EN.#

0-12790ELAYS

LCEN.# _ _ _- - I

OE.#

000-9

6-22

HSP9501
Pin Descriptions

NAME

PIN
NUMBER

TYPE

DESCRIPTION

VCC

12,34

The +5V power supply pin. A 0.1 /IF capacitor between the VCC and GND pin is recommended.

GND

13,33

ClK

1

I

Input Clock. This clock signal is used to control the data movement through the programmable
buffer. It is also the signal which latches the input date, length control word and mode· select. Input
setup and hold times with respect to the clock must be met for proper operation.

010-9

27,29-32,
35""39

I

Data Inputs. This 1O-bit input port is used to provide the input data. When MODSEl is low, data
on the 010-9 inputs is latched on the clock edge selected by ClKSEl.

000-9

7-11,
14-18

0

Data Outputs. This 10-bit port provides the output data from the intllmal delay registers. Data
latched into the 010-9 inputs will appear at the 000-9 outputs on the Nth clock cycle, where N is
the total delay programmed.

lC0-10

20-28,
41-'-44

I

Length Control Inputs. These inputs are used to specify the number of clock cycles of delay
between the 010-9 inputs and the 000-9 outputs. An integer value between 0 and 1279 is placed
on the lCO-1 0 inputs, and the total delay length (N) programmed is the lCO-10 value plus 2. In
order to properly load an active length control word, the value must be presented
to the lCO-10 inputs and lCEN# must be asserted during an active clock edge selected by
ClKSEL.

lCEN#

6

I

Length Control Enable. lCEN# is used in conjuction with lCO-10 and ClK to load a new length
control word. An 11-bit value is loaded on the lC0-10 inputs, lCEN# is asserted, and the next
selected clock edge will load the new count value. Since this operation is synchronous, lCEN#
must meet the specified setup/hold times wilh respect to ClK for proper operation •.

OE#

19

I

Output Enable. This input controls the state of the 000-9 output port. A low on this control line
enables the port for output. When OE# is high, the output drivers are in the high impedance state.
Internal latching or transfer of data is not affected by this input.

MOOSEl

40

I

Mode Select. This input is used to control the mode of operation of the HSP9501. A low on
MOOSEl causes the device to latch new data at the 010-!} inputs on every Clock. cycle, artd
operate as a programmable pipeline register. When MOOSEl is high, the HSP9501 is in the
recirculate mode, and will operate as a programmable length circular buffer. This control signal
may be used in a synchronous fashion during device operation, however, care must be taken to
ensure the required setup/hold times with respect to ClK are met.

ClKSEl

5

I

Clock Select Control. This input is used to determine which edge of the ClK signal Is used for
controlling all Internal events. A Iowan CLKSEl selects the negative going edge, therefore, all
setup, hold, and output delay times are with respect to the negative edge of ClK. When ClKSEL is
high, the positive going edge is selected and all synchronous timing is with respect to the positive
edge of the ClK signal.

ClKEN#

2

I

Clock Enable. This control signal can be used to enable or disable the ClK input. When low, the
CLK Input is enabled and will operate in a normal fashion. A high on CLKEN# will disable the ClK
input and will "hold" all internal operations and data. This control signal may also be used in a
synchronous fashion, however, setup and hold requirements with respect to CLK must be met for
proper device operation.

The device ground.

HSP9501
Functional Description
The HSP9501 is a 10-bit wide programmable length data
buffer. The length of delay Is programmable from 2 to 1281
delays In single delay increments.
Data into the delay line. may be selected from the data Input
bus (010-9) or as recirculated output, depending on the
state of the mode select (MOOSEl) control input.
Mode Select
The MOOSEl control pin selects the source of .the data
moving into the delay line. When MOOSEl is low, the data
input bus (010-9) Is the source of the data. When MOOSEl
is high, the output of the HSP9501 Is routed back to the input to form a circular buffer,
The MOOSEl control line Is latched at the input by the ClK
signal. The edge which latches this control signal is determined by the ClKSEl control line. In either case, the
MODSEl line is latched on one edge of the ClK signal with
the following edge moving data into and through the
HSP9501. R'eler to the functional timing waveforms for
specific timing references.

Delay Path Control
The HSP9501 buffer length Is programmable from 2 to
1281 data words in one word Increments. The minimum
number of delays which can be programmed is two,
consisting 01 the input and output buffer registers only.
The length control Inputs (lCO-10) are used to set the
length of the programmable delay ram which can vary In
length from 0 to 1279. The total length of the HSP9501 data
buffer will then be equal to the programmed value on
lCO-10 plus 2. The programmed delay is established by
the 11-blt Integer value of the lCO-10 inputs with lC 10 as
the MSB and lCO as the lSB.
For example,

I LCO I

LC10

9

8

7

6

5

4

3

2

1

0

0

0

0

1

0

0

0

0

01

1

1

programs a length value of 26 + 2 0 = 65. The total length of
the delay will be 65, + 2 or 67 delays.

Clock, Select Logic
The clock select logic is provided to allow the use of
positive or negative edge system clocks. The active edge of
'the CLK input to the HSP9501 is controlled through the use
of theClKSEl input.
When ClKSEl is low, the negative going edge of ClK is
used to control all internal operations. A high on ClKSEl
.'selects the positive 1l0ing edge of ClK.

'Table 1 Indicates several programming values. The decimal
value placed on lCO-10 must not exceed 1279. Controlled
operation with larger values is not guaranteed.
Values on lCO-10 are latched on the ClK edge selected by
the ClKSEl control line, when lCEN# is active. lCO-10
and lCEN# must meet the specified setup and hold times
relative to the selected ClK edge for proper device
operation:

All synchronous timing (l.e. setup, hold and output
propagation delay times are relative to the ClKedge
selected by ClKSEL. Functional timing waveforms for each
state of ClKSEl are provided (refer to timing waveforms for
details).
TABLE 1. LENGTH CONTROL PROGRAMMING EXAMPLES

LC10

LC9

!.Sa

LC7

LC6

LC5

LC4

LC3

LC2

LC1

LCO

2 10

29

28

27

26

25

24

23

22

21

20

0

0

0

0

0

0

0

0

0

0

0

0

2

0

0

0

0

1

1

1

0

1

1

0

118

120

PROGRAMMED
LENGTH

TOTAL
LENGTH
N

0

1

1

0

0

1

0

1

0

0

0

808

810

1

0

0

0

0

0

1

1

0

0

1

1049

1051

1

0

0

1

1

1

1

1

1

1

1

1279

1281

6".24

Specifications HSP9501
Absolute Maximum Ratings
Supply Voltage ••••••...••••••••••••.....•••••••••••.•••••.•.••••••••••...•••••••••••••••••••••••••••••••••••••• +8.0V
Input or Output Voltage Applied ••••...•••••••••••......••••••.•.••.••..•...•••.••••••...•••••••• GND -0.5V to VCC +0.5V
Storage Temperature Range •....•.••.•..••••••••••••••••••••••.•••••••••••••••••••••••• " ••••••• , •.•• -650 C to +1500 C
Junction Temperature ••••••....••••••••..•..••••••.•••••••..•••...•.•..•••••••••••••....•••••••••.•••••..••••• +1500C
Lead Temperature (Soldering, Ten Seconds) .•.....••••••.•••..•••••••••••••••.••••••••••••••.••••••.•••...••..•• +3000C
CAUTION: Stresses above those listed in the ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range ................................................................. +4.75Vto +5.25V (Commercial)
Operating Temperature Range ............................................................... OoC to +70 0 C (Commercial)

D.C. Electrical Specifications
PARAMETER
Logical One Input Voltage

(Vcc = 5.0V + 5%, TA = Ooc to +700 C, Commercial)
SYMBOL

MIN

MAX

UNITS

VIH

2.0

-

V

VCC= 5.25V

TEST CONDITIONS

VIL

-

0.8

V

VCC= 4.75V

Output HIGH Voltage

VOH

2.4

-

V

IOH=-4mA
VCC= 4.75V

Output LOW Voltage

VOL

-

0.4

V

IOL=+4.0mA
VCC= 4.75V

Input Leakage Current

II

-10

10

IJA

VIN = GND or VCC
VCC= 5.25V

Output Leakage Current

10

-10

10

IJA

VOUT=GNDorVcc
VCC= 5.25V

Standby Current

ICCSB

-

SOO

IJA

VIN =VccorGND, VCC = 5.25V
Outputs open

Operating Power Supply Current

ICCOp

-

125

mA

f = 25M Hz, VIN = VCC or GND
VCC = 5.25V, Outputs open

Logical Zero Input Voltage

A.C. Electrlcai Specifications

(VCC = 5.0V-+ 5%, TA = ooC to +700 C, Commercial)

r-----~----~~----~--------~
TEST
CONDITIONS

NOTES:
1. Controlled by design or process parameters and not directly tested.
Characterized upon inaial design and after major process and/or design
changes.

2. A.C. Testing is performed as follows: Input levels: OV and 3.0V, Timing
reference levels = 1.5V, Input rise and fall times driven at 1 noN, Output
load CL = 40pF.

6-25

HSP9501

r--------

Test Load Circuit
51
OUT~

--,
I

I
I

I
I
I

.cct

t
·'.:~:::C~::~tND

1 ___

10L

EaUfVALENT~IRCUI~ _ _

I
I
I
I

J

SwHch S 1 Open for ICCSS and ICCOp Tests

Timing Waveforms
CLK

MOOSEL - - - - . .

010 -9

O~

+-_____/

_________

TENA

000 -9

FUNCTIONAL TIMING (CLKSEL = LOW)

INTERNAL
CLOO<

CLKEN# TIMING (CLKSEL = LOW)

CLK

LCEN#

LC 0 -10 -------"""--+-.J.~---------------

LENGTH CONTROL TIMING (CLKSEL'= LOW)

6-26

HSP9501
Timing Waveforms

(Continued)

CU<

MOOSEL

010,9

O~

----------------r-----------/

000- 9

FUNCTIONAL TIMING (CLKSEL= HIGH)

INTERNAL

CLOCK
CLKEN# TIMING (CLKSEL = HIGH)

CU<

LCEN#

LCO-l0 ________~,---+~~----------------

LENGTH CONTROL TIMING (CLKSEL = HIGH)

6-27

HSP9520/HSP9521

mHARRIS

ISP9520llSP9521

Multilevel Pipeline Register

May 1991

Features

Description

• Four 8-Bit Registers

These devices are multilevel pipeline registers implemented
using a low power CMOS process. Jhey are pin for pin
compatible replacements for, industry standard multilevel
pipeline registers such as the L29C520 and L29C521. The
HSF',9520 and HSP5921 ijre direct replacements for the
AM29520/21 and WS59520/21.

• Hold, Transfer and Load Instructions
• Single 4-Stage or Dual-2 Stage Pipelining
• All Register Contents Available at Output
• Fully TTL Compatible
• Three-State Outputs
• High Speed, Low Power CMOS
• Available in 24 Pin Dual-In-Line and SOIC Packages

Applications
• Array Processor
• Digital Signal Processor
• AID Buffer
• Telecommunication
• Byte Wide ShiH Register
• Mainframe Computers

They consist of four 8-bit registers which are dual ported.
,They can be configured as a Single four level pipeline or a
dual two level pipeline.. A single 8,.bit input is provided, and
the pipelining configuration is determined by the instruction
code input to the 10 and 11 inputs (see instruction control).
The contents of any of the four registers is selectable at the
multiplexed outputs through the use of the SO and S1
multiplexer control inputs (see register select). The output is
8-bits wide and is three-stated through the use of the OE#
input.
The '9520 and '9521 differ only in the way data is loaded
into and between the registers in dual two-level operation.
In the '9520, when data is loaded into the first level the
existing data in the first levei is moved to the second level. In
the '9521, loading the first level simply causes the current
data to be overwritten. Transfer of data to the second level is
"aChieved using the single four level mode (11,10 = '0'). This
instruction also causes the first level to be, loaded. The
HOLD instruction (11, 10 = '1') provides a means of holding
the countents of aU "registers.

Pinout
HSP9520/HSP9521 (24 PIN SOle)
'9520/'9521 (24 PIN DIP)
TOP VIEW

Y1

Y2
Y3
Y4

Y5

Y8
Y7

OE#

are

CAUTION':' These devices
sensHive to electrostatic' discharge. Proper I.C. handling procedures should' be lollowed.
Copyright @ Harris Corporation 1991

6-28

Fiie Number

2811

HSP9520/HSP9521

/SP9520//SP9521

Block Diagram
laC>-

DO -D7

'" '"

8

CLKC>-

11C>-

REG.Al

REG.A2

I L------

-[B-1 ~EF
REG.Bl

MUX

rr

H:(8/

YO -Y7

~

OE#

<=J so

c::J

Sl

Pin Descriptions
NAME

DIPPIN

VCC

24

TYPE
The +5V power supply pin.
recommended.

GND

12

The device ground.

ClK

11

I

Input Clock. Data is latched on the low to high transition of this clock signal. Input setup and
hold times with respect to the clock must be met for proper operation.

00-7

3-10

I

Data Input Port. These inputs are used to supply the a bits of data which will be
latched into the selected register on the next rising clock edge.

YO-7

21-14

0

Data Output Port. This a-bit port provides the output data from the four internal registers.
They are provided in a multiplexed fashion, and are controlled via the multiplexer control
inputs (SO and Sl).

10,11

1,2

I

Instruction Control Inputs. These inputs are used to provide the instruction code
which determines the internal register pipeline configuration. Refer to the Instruction Control
Table forthe specific codes and their associated configurations.

DESCRIPTION
A 0.1 flF capacitor between the VCC and GND pin is

SO,Sl

23,22

I

Multiplexer Control Inputs. These inputs select which of the four internal registers' contents
will be available at the output port. Refer to the Register Select Table for the codes to select
each register.

OE#

13

I

Output Enable. This input controls the state of the output port (YO-Y7). A lOW on this control
line enables the port for ouput. When OE# is HIGH, the output drivers are in the high
impedance state. Internal latching or transfer of data is not affected by this pin.

6-29

-I

Z

c:c:!

-I(.)(.)
W z

~~

$pecificationsHSP9!j2()/HSP9521 '
Absolute Maximum Ratings

Operating Conditions

Supply Voltage •••••••••••••••••.•••••••••••••••••••••• +8.0V
Input or Output Voltage Applied •••••••. GND -0.5V to VCC +0.5V
Storage Temperature Range •••••..•••••••••• -650 C to +1500 C
Junction Temperature •••••••••••••••••••••••••••••••• +150o C
Lead Temperature (Soldering, Ten Seconds) •••••••••••• +300o C

Operating Voltage Range. • • • • • • • • • • • • • • • • • •• +4.75V to +5.25V
Operating Temperature Range ••••••••••••••••••• OOC to + 700C
Reliability Information
0ja '••••••••• ~ •••••••••••••••••••••••.•••••.••••• 51.40 CIW
"Ojc .•••••••••••••••••••• , ••••••••••••.• ",' ••••••• ' 22.30 CIW
Maximum Package Power Dissipation .••• : •••••••••••••••• 1.5W

D.C. Electrical Specifications
PARAMETER

(Vcc = 5.0V ± 5%, TA = ooc to +700C)
SYMBOL

MIN

MAX

UNITS

Logical One 'Input Voltage

VIH

2;0

-

V

Vcc= 5.25V

Logical Zero Input Voltage

VIL

TEST CONDITIONS

-

0.8

V

VCC=4.75V

Output HIGH Voltage

VOH

2.4

-

V

10H = -6.5mA, VCC = 4.75V

Output LOW Voltage

VOL

-

0.5

V

10L = +20.0mA, VCC = 4.75V

Input Leakage Current

II

-10

10

I'A

VIN =VeeorGND, VCC = 5.25V

Output Leakage Current

10

-10

10

JJA

Standby Power Supply Current

ICCSB

-

500

JJA

VIN=VCCorGND
VCC = 5.25V Outputs Open

Operating Power Supply Current

Iceop

-

12

mA

f = 5.0MHz, VIN = Vce or G NO
VCC = 5.25V, Ouputs Open

A.C. Electrical Specifications
PARAMETER
Clock to Data Out
Mux Select to Data Out
Input Setup Time ,(00-7/10-7)
Input Hold Time {DO:"7 ilO-7) ,

~

... ,

VOUT=VCCorGND
,V,CC =; 5.25V

(Vcc = 5.0V:!: 5%, TA = ooc to +700 C)
MIN

MAX

UNITS

-

22

ns

,TSELD

20

ns

TS

10

ns

TH

3

-

SYMBOL
TpD

TEST CONDITIONS (NOt82)

ns

Output Enable Time

TENA

-

21

ns

. Output DisableTime

TDiS

-

15

ns

Clock Pulse Width

TpW

10

-

ns

Note 1

,NOTES:

1. Controlled by design or process paramelers and not directly tested.
Characterized upon InHial design and a/ler .major design and/or process

changes.

2. A.C. T'Isting!l! performed as follows: Input levels: OV ,;"d 3.0V. Timing
reference lev';ls = 1.5V. Input riae and fall tilTiea driVen at 1naN. Output
load CL - 40pF.

0,6-30

Specifications /SP9520//SP9521
Absolute Maximum Ratings

Operating Conditions

Supply Voltage ••••••••••••••••.••••••.••..•••••••••••• +8.0V
Input or Output Voltage Applied ••••••.. GND -0.5V to VCC +0.5V
Storage Temperature Range •••••••••••.••••• -650C to +1500 C
Junction Temperature •••.. " ., •••.•••••••..•••••.•••• +1500 C
Lead Temperature (Soldering, Ten Seconds) •••••••••••. +3000 C

Operating Voltage Range. • • • • . • . • • • • • • • • • • •• +4.75V to +5.25V
Operating Temperature Range ••••••••••••••••••. OoC to + 700C

D.C. Electrical Specifications (Vcc = 5.0V ± 5%, TA = Ooc to HOOC)
PARAMETER

SYMBOL

MIN

MAX

UNITS

TEST CONDITIONS

Logical One Input Voltage

VIH

2.0

-

V

VCC=5.25V

Logical Zero Input Voltage

VIL

-

0.8

V

VCC=4.75V

Output HIGH Voltage

VOH

2.4

-

V

IOH = -2.0mA, VCC = 4.75V

Output LOW Voltage

VOL

-

0.5

V

IOL = +12.0mA, VCC = 4.75V

Input Leakage Current

II

-10

10

VIN = GND orVcC, VCC = 5.25V

Output Leakage Current

10

-10

10

JJA
JJA

Standby Power Supply Current

ICCSB

-

500

JJA

VIN=VccorGND
VCC = 5.25V Outputs Open

Operating Power Supply Current

ICCOp

-

12

mA

f = 5.0MHz, VIN = VCC or GND
VCC = 5.25V, Ouputs Open

VOUT=VCCorGND
VCC=5.25V

A.C. Electrical Specifications (Vcc = 5.0V ± 5%, TA = Ooc to HOOC)
PARAMETER

SYMBOL

MIN

MAX

UNITS

TpD

-

25

ns

TSELD

25

ns

Input Setup Time(DQ-7,10-1)

TS

15

-

ns

Input HoldTlme(DO-7,1Q-1)

TH

3

-

ns

Output Enable Time

TENA

-

25

ns

Output Disable Time

TDiS

-

20

ns

Clock Pulse Width

TpW

13

-

ns

Clock to Data Out
Mux Select to Data Out

TEST CONDITIONS (Note 2)

.... z
Note 1

NOTES:

1. Controlled by design or process parameters and not directly tested.
Characterized upon initial design and after major design and/or process

changes.

2. A.C •. Testing is performed as follows: Input levels: OV and 3.0V. Timing
referen99 levels • 1.5V, Input rise and fall times driven at losN, Output
load CL = 40pF.

6-31

c:c!:

-IUu
W z

~~

HSP9520/HSP9521

/SP9520//SP9521

Timing Waveform
CLOCK
(CLK)

INST
(10 -11)

DATA
(DO -07)

MUXSEL
(SO -Sl)

OUTPUT
(YO - Y7)

THREE STATE
OUTPUT
(YO -Y1)

i"r:- i'N

An 8 bit counter is configured to count modulo l+N-1. To
initialize the system, the first l-1 data samples are passed
through FIFO #1 and written into FIFO #2. While this
occurs N more samples are clocked into FIFO #1. Following that a repetitive steady state sequence begins as shown
below:
1. Clock the firstl-1 samples from FIFO #2 into the DF.
2. Clock N samples from FIFO #1 into the DF.
3. Clock the last l-1 samples of the sequence in steps 1
'
and 2 back into FIFO #2.
4. Clock the next N samples into FIFO #1 concurrently
with steps 1-3.

The example above leads to the more general case of implementing an l tap filter with an N cell device (l>N). When an
l tap fnter is implemented using an N cell DF (where l>N),
the DF computes a block of N filter output samples at a time.
Between these output blocks there are l-1 ClK cycles
during wh ich no valid output points are available. Therefore,
generating a block of N output points requires l+N-1
ClKs. During these l+N-1 ClKs there are l+N-1 new
input samples being clocked into the DIN (Data IN) port.
It can be seen from Table 1 that N·outputs are read out of
the DF during the last N· ClKs of each l+N-1 ClK
sequence. After inputting the first l data samples N-1 ClKs
are required to flush the coefficients from the cells. The final
l-1 of the previous l+N-1 input samples must be
re-submitted at the input port. After the outputs are read out
an additional l+N-1 samples are fed in and the process
repeats itself until no more data is available.

This sequence of steps 1 through 4 can be repeated ad
infinitum.
The output data is available in blocks of N points separated
by l-1 ClK cycles. FIFO #3 acts as a rate buffer for the
output and is optional. The coefficient memory contains the
l coefficients followed by the necessary N-1 zeros.
A design example using the above technique might include
a 57 tap filter with a sample rate of 2.5MHz. This can be
done with a single 8 cell device operating at 20M Hz.

In this paper, throughput is defined as the average rate at
which outputs are computed by the DF. When the number
of taps exceeds the number of filter cells, the necessity to
re-access the data stream determines the maximum
throughput. The generalized performance of an l tap, 8x8
FIR filter is shown below. let:

Higher Precision Filters and Correlators
Several digital filtering applications require wider wordwidth
calculations to maintain precision. The DFs are designed to
be flexible in creating filters with input precision levels of 8,
16, 24, 32 bits or greater.

l = Number of taps
N = Number of filter cells in DF
R = Maximum clock rate of DF (20,25.6, or 30MHz)
Fs = Desired throughput (MHz) where R>Fs

The first step is to restructure the data and/or coefficients
into 8 bit quantities which can be processed by the DF.

7-5

Application Note 116

CAOO

INPUT
DATA

OUTPUT
DATA

HSP43881

fIFO #1

iii

iii

DIN

BLOCK DIAGRAM OF AN 8 CELL OF CONFIGURED TO IMPLEMENT EXTENDED FILTER LENGTHS
(UP TO 249 TAPS)

These quantities are used to form the partial products of the
larger multiplication involving the full precision data and
coefficients. An example of segmenting the partial products
of a 16x8 multiplication (16 bit coefficients and 8 bit data)
would be:
C(16 bit) CH x 2 8 + CL x 20
H High Order Byte

=

X(8 bit) = X X20 .

AO-2

ClK

Of

Wi

FIGURE 3.

IiiAsE

COEffICIENT
MEMORY

=

L = Low Order Byte

Care must be taken when combining the upper and lower
p
18 (lSBo)
<0.17>

RESElD

z

CI

RESET.D

SHADD

;:::.,.
eC w

y"-

CI

~z

D-

eC

0'0

RESET.D

SUMO-25

ClK

FIGURE 7,

OF OUTPUT STAGE

7-11

Application Note 116
A1ter the partial products' are made available to the output
bus they are stored in, temporary registers. This allows the
two sections of the final result to be combined properly,
Following this the full result may be stored directly Into
som'e form of memory. Figure' 6' shows a'block diagram
illustrating the complete concept.
'
The following summary describes the sequence of events
listed In Table 3 (also refer to Figures 6 and 7).
CLK 0-5
• Each Cell Is Accumulating Partial Product Data
• SHADD Not Asserted
CLK,6
• Cell 0 Selected (ADRO-l = 0)
• Erase Accumulator of Cell 0 (ERASE = 0)
• SHADD Not Asserted
CLK7
• Cell 0 Contents Added to Zero and Available at Input to
Output Buffer
• Cell 0 Contents Available at SUMO-15
• Cell 1 Selected (ADRO-l = 1)
• Erase Accumulator of Cell 1 (ERASE = 0)
• SHADD Not Asserted
CLK8
• External 8 Bit Register Clock Asserted. Lower 8 Bits of
SUMO-15 (least Significant Byte of Y(3» Entered Into
External 8 Bit Register
• Cell 0 Contents Entered Into Output Buffer
• Cell 1 Contents Added to Zero and Available at Input to
Output Buffer
• SHADD Asserted
CLK9
• Shift Cell 0 Contents Down 8 Bits and Add to Contents of
Cell 1 (Output Buffer). This 16 Bit Value Becomes Available at SUMO-15
• SHADD Not Asserted
CLK 10
• External 16 Bit Register Clock Asserted. All 16 Bits:Of
SUMO-15 (Most Significant Word of Y(3» Entered Into
External 16 Bit Register
'
• Cell 2 Selected (ADRO-l = 2)
• Erase Accumulator of Cell 2 (ERASE = 0)
• SHADD Not Asserted

CLK 11
• Cell 2 Contents Added to Zero arid Available at Input to
Output Buffer
• Cell 2 Contents Available at SUMO-15
• Cell 3 Selected {ADRO-l = 3)
• Erase Accumulator of Cell 3 (ERASE = 0)
• Write Y(3) Into Output FIFO (Optional)
• SHADD Not Asserted
CLK 12
• External 8 Bit Register Clock Asserted. lower 8 Bits of
SUMO-15 (least Significant Byte of Y(4» Entered Into
External 8 Bit Register
• Cell 2 Contents Entered Into Output Buffer
• Cell 3 Contents Added to Zero .and Available at Input to
Output Buffer
• SHADD Asserted
CLK 13
• Shift Cell 2 Contents Down 8 Bits and Add to Contents of
Cell 3 (Output Buffer). This 16 Bit Value Becomes Available at SUMO-15
• SHADD Not Asserted
CLK 14
• External 16 Bit Register Clock Asserted. All 16 Bits of
SUMO-15 (Most Significant Word of Y(4» Entered Into
External 16 Bit Register
• SHADD Not Asserted
This same pattern repeats until the input data Is exhausted.
Note that the value stored in the External Register must be
stored elsewhere before the low byte of the next output
value is sequenced.
The performance specifications for the'16x8 filter are listed
below.
• 2 Outputs/l0 ClKS = 1 Output/5.0 ClKS
= 200ns/Output (25.6MHz Device)
= 5MHz Throughput (25.6MHz Device)
The results for the 16x8 design used in this implementation
can be extended to the general case. Let:
L = Number of taps
Fs = Sample rate (MHz)
N2 = Number of 2 cell groups
R = M~ximuni clock rate of OF (20, 25.6, or 30MHz)
(R>Fs)
Then:

7-12

Fs = (N2 x R)/{2l+2{N2-1»
N2 = 2Fs {L-l)/R-2Fs)

Harris Semiconductor

No.9102

Harris Signal Processing

May 1991

NOISE ASPECTS OF APPLYING
ADVANCED CMOS SEMICONDUCTORS
By: R. Kenneth Keenan, Ph.D.
and David F. Bennett

Introduction and Summary
This report is about noise aspects of high-speed logic, with
a focus on Advanced CMOS semiconductor applications.
The present report pertains to supression of ringing for both
short and long traces, with experimental evidence provided
for long traces.

For long traces with distributed loading, AC shunt
termination-a resistor in series with a small-value
capacitor-is used from a trace to ground at the receiving
end of a trace. The value of the capacitor depends on clock
frequency, but it is typically 50pF to 200pF. Larger values
result in improved pulse fidelity at the expense of increased
power dissipation in the terminating resistor. Atthe exp-ense
of a capacitor, AC shunt termination consumes much less
power than purely resistive shunt termination. AC shunt
termination does not appear to materially effect propagation
and transition times, except insofar as it removes the ringing
contributing to shorter transition and propagation times.

Although termination and decoupling techniques cited here
minimize ringing for all semiconductor technologies (AC!
ACT, LSTTL, HCMOS, AS, etc.), external resistive
termination is usually not required for slower semiconductor
technologies. Decoupling is an important aspect of design
for all semiconductor technologies.
The preferred termination technique is a resistor, RT, equal
in value to the trace's characteristic impedance, ZO, in
series with a trace at the driving end of that trace. For AC!
ACT, series termination results in a modest (1 ns to 3ns)
increase in propagation and transition times. the increase
in transition times incurred with series termination helps to
minimize interference generation.

Series Termination with a Single
Receiver
Resistive Termination
Figure 1 illustrates the waveforms at the receiver for the
case of no termination and for the case where the line is
terminated at the driver end of the line. The termination
resistor is 800, approximately equal to the 780
characteristic impedance of the line on the board. In this
and all succeeding Figures, the line is 12 inches long.

The length of traces with distributed loading to which series
termination can be applied is limited by the increased
transition times at intermediate points along those traces.

:z:
Q

;::(1.)
CC w

(.)1-Q

~:z:
Q..

cc
5V

n.

-50.000
Ch. 1
Ch. 2
Tll'lebase

•
•
-

.

i

80n.

i

. . . . . .M
. 4. . . . . ._~. ._._:~R~_MN __~ __NJ_.NN. . . . ._~._. NN.__. . . .
0.00000.'

2.000 volh/dlv
2.000 volh/div
10.0 ns/d1v

Offset

Off.et
Delay

50.000

•
•
•

n.

/

2;500 volt.
2.500 volts
0.00000 •

FIGURE 1. UNTERMINATED AND TERMINATED (RT '" Zo) LINES
This work was supported by Harris Semiconductor (Harris I and The Keenan Corporation (TKCI_ The authors thank the external reviewers. Mr. Richard E. Funk.
Manager, Applications Engineering, Harris Semiconductor, and Dr. Leonard Rosi, EMC Engineer, of Howlett-Packard'. Corvallis Workstation Operation, for
their helpful comments.
Copyright Notice: Copyrighf 1989, TKC. Reprinted by Harris Semiconductor, April 1989, with permission of TKC.

7-13

Application Note 9102
..

. ,

Zero and five-vQlt reference lines are shoWn in e.ach of the
above oscillograms.lt is Clear from Figure 1 that termination
a~sists In reducing both the undershoot for the low-to-high'
transition and the overshoot for the high-to-Iow transition.
The noise immunity limits for CMOS are given in Table 1.
• TABLE 1. NOISE IMMUNITIES AND MARGINS
D.C. SPECIFICATION

VOLTAGE LEVEL
(V)

Maximum Low-Level Input Voltage (Max VIL)

O.S

Minimum High-Level Input Voltage (Min VIH)

2.0

Maximum.Low-LeveIOutput
Voltage (Max VOt.>

0.4

Minimum High-Level Output
Voltage (Min VOH)

2.4

Low-Level Noise Margin (VNML

=VIL - VOt.>

.... __ ... 1..
-50.000 "5
eh. I
Ch. 2
fiMebase

..
'"
•

Table 1 summarizes the effects of terminating resistance on
transition times and propagation delays. The propagation
delay of the line, 1.8ns, has been subtracted from the
experimentally-measured propagation delay in the data in
Table 1. The propagation delay was measured as illustrated
in Figure 3.

0.4

=

The relative sensitivity of the value of termination resistor
was assesed. Figure 2 Hlustrates experimental results.
From Figure 2, the pulse waveform is marginally improved
for termination resistance greater than the characteristic
impedance, but it becomes more unterminated-like when a
terminating resistance less than the characteristic
impedance is used.

0.4

High-Level Noise Margin
(VNMH VOW VIH)

Off •• t
Of fset
Delay

eon.

/

aon.

/

130n.

/

n.

- - 0.00000 --" - -- -- --

2.000 vol h/div
2.000 volts/div
10.0 n~/dl"

•
•

2.500 volt.
2.500 volh
0.00000 •

FIGURE 2. SENSITIVITY OF PULSE TO TERMINATING· RESISTANCE

R
T

L

..

For the unterminated line In Fi.gure1, the maximum VII:. 0.8V
is breached . Therefore, CMOS gates driven -with the
unterminated-line' (upper) waveform inF~gure 1 can
mistake the "bump" between t == 20ns and t = 30ns for a
"high". Thus, for the unterminated-line waveform, CMOS
gates are subject to logic errors. The terminated line rings
less and provides a signal which is well within the noise
immunity limits for AC/ACT.

F

"I

1 .s ns
TRANSITION TIMES, ~
SPECTRA
~

PROPAGATION DELAY-.::J

FIGURE 3. MEASUREMENTS

7-14

Application Not.e 9102
Figure 4 illustrates the effects of AC shunt termination for
two different values of capaCitors.

TABLE 2. SUMMARY OF TRANSITION TIMES AND
PROPAGATION DELAYS
TRANSISTION
TIMES (ns)

PROPAGATION
DELAYS (ns)

(0)

tr

tf

tplh

0

4.0

2.6

3.1

5.0

30

4.6

3.6

3.8

6.0

RT

In designing an AC shunt termination. the value of the
resistor is equal to the characteristic impedance of the
line: RT ",. ZOo To allow for complete charging and
discharging of the terminating capacitor (C1) during
one-half the clock period: C1 < 1/6Z0fC. Then the power
dissipated in RT is VCC 2fCC1 (see Table 7). For the present
case of fC '" 12MHz. and Zo '" 80n. C1 < 1/6Z0fC '"
174pF. At the extreme. where C1 .... oo. the power dissipation
approaches that of a resistive terminator: VCC2/2Z0 for a
50% duty cycle clock.

tphl

BO(=ZOl

5.4

5.B

4.8

B.O

130

8.4

7.4

5.6

10.6

Transition times are measured in the conventions 10%/90%
and 90%/10%. and. similarly. propagation delay is
measured between the 50% points of the waveforms.
Termination with a resistor equal to the characteristic
impedance of the line adds 1.7ns to 3.0ns to the
propagation delays and increases the transition times. From
the perspective of the emissions problems discussed in
Section 9.0. an increase in transition times is good.
However. increased propagation delays may be
undesirable from a functional standpoint. With AC/ACT.
some termination resistance must be used to prevent
ringing which could exceed the noise immunity limits.

For the case C1 '" 56pF. the power dissipation in the
terminating resistor is relatively small: 16.8mW. For the
case C1 '" 560pF. the power dissipation approaches that of
a resistive terminator: 156mW (the power dissipation in the
driver is approximately 30mW). However. the waveform with
C1 = 560pF is somewhat better than that with C1 '" 56pF.
In shunt termination. one is always trading power
dissipation in the terminating resistor for pulse fidelity.
Table 3 summarizes propagation and transition times for
AC shunt termination.
TABLE 3. PROPAGATION AND TRANSITION TIMES

Shunt Termiliation with a Single
Receiver
AC shunt termination is a means of approximating a
resistive termination without incurring the power dissipation
of resistive termination. In laptop computers. power drain is
a battery life issue. In computers and other powerlinepowered digital equipment. power drain causes heat
dissipation and implies a diminution in reliability. CMOS.
in spite of its speed. consumes relatively little power while
operating and near zero power while in standby (or high-Z)
states. Therefore. in a total power "budget". it is
important to consider the power dissipation of termination
resistors.

TRANSISTION
TIMES (ns)
TERMINATION

tplh

tphi

None

4.0

2.6

3.1

5.0

BOO/56pF

5.0

4.2

4.6

7.2

800/560pF

5.8

4.6

4.2

7.0

AC shunt termination at the sending end (only) was not
tried. However. in the context of distributed loads with both
ends of the bus AC shunt terminated. the driving-end
termination did not improve the waveform.

[>
[>
Ch. t
Ch. 2
TI",ebae8

•

•
•

2.000 volh/dlv
2.000 volh/dlv
1111.' ns/dlv

o" •• t
orr •• t
Delay

•
o
o

PROPAGATION
DELAYS (ns)

2.500 volh
2.500 volta
1.00008 a

FIGURE 4. AC SHUNT TERMINATION AT RECEIVER

7-15

Application Note 9102
Since computer bus lines may be in the active high state for
relatively long periods of time;'the DC blocking capacitor,
C1 (56pF and,560pF in Figure 4), can be of considerable
benefit when driving CMOS logic. However, when driving
bipolar logic, the current required by the inputs of driven
gates can total much more than that required by a
terminating resistor without a DC blocking capacitor. Then,
AC termination offers insignificant advantages over
conventional 'resistive termination.

Terminations Applicable to Distributed
Loads

The measurements and wavefo'rms cited beloW were made
at the gate four inches from'the driver and at the gate at the
end of the line. The points designated by arrows in the
figure are referred to as the "interr1;edi!ite gate" and "end
gate" in the measurements to follow. In all cases, the
waveform at the end gate was the worst case with respec!t
to ringing.
'
When a load is distributed along a trace, the characteristic
impedance of that trace is modified in accordance with
[2, p. 148]
Zo '" Zoo/[1 + distributed load capacitance on line/
capacitance of line]'h
(1)

Description of Board with Simulated, Load
The circuit shown in Figure 5 is the simulated load used
along the bus-like structure on the test board. It is patterned
after the equivalent input curcuitry. The inductor was
formed by a small loop of wire.

Vcc

Zoo '" Characteristic
distributed loading.

impedance

of

line

without,

In the case of the test board, the capacitance along the
unloaded line of 0.72pF/in. x 12in. '" B.6pF, and the
distributed load, Including that at the last gate, was (4 x 5pF)
+ 7.5pF '" 27.5pF. Then, Zo '" BO/[1 + 27.5pF/B.6pF]'h ..,

400.
Series Termination
Figure 7 illustrates waveforms, along the line for
unterminated lines, with and without distributed loading,
and for the series-terminated line with RT '" ZOo It is clear
from a comparison of the top two oscillograms that the
presence of distributed loading-:-even without terminationtends to smooth the waveforms. At least In part, this is
probably due to the diodes in the simulated loads, which are
also present in CMOS Input gates.

5pF

FIGURE 5. SIMULATED'CMOS LOAD

The average value of the input capacitarice ota CMOS gate
is 7.5pF. That value was not available, so 5pF capacitors
were used. The above load was distributed along one olthe
bus traces at points shown in Figure 6. The diodes are
1N914's, high-speed silicon types.

=12"

"

2"1 __~ 2"f4"12"i
t
FIGURE 6, DISTRIBUTION OF SIMULATED LOADS ALONG
BUS TRACE

Distributed loading increases line propagation delays by
the same factor by which the characteristic impedance is
decreased, which is a factor of approximately two in the
present case. Propagation delay measurements were taken
as indicated in Figure 2, with 2 x 1.B '" 3.6ns subtracted
from the measured propagation delays to provide the
"distributed load" propagation times in Tables 4 and 5.
The problem with using series termination with distributed
loading is that the waveform along the line will tend to
become a three-level waveform [2, p. 53]. This tendency is
clear in the third OSCillogram from the top In Figure 7. Thus,
in Table 5 the transition times. aUhe intermediate point on
the line are greater than those at the end of the line given in
Table 4. If the bus was longer, the "kink" at a line voltage of
2.5 volts would be more noticeable. However, in the present
case, transition times are great enough to smooth the
otherwise'sharp three-level waveform. In some applications, an increase in transition times may be acceptable,
and the extra component In the form of the capacitor necessary for AC shunt termination-which does not "three-level"
the waveform along the bus-is not necessary. AC shunt
,
termination is discussed in the next section.'

7-16

Application Note 9102
o

/

S0. ~00

'I,
I.tl.

I
?

r r r1~bi'!'1!"

0.00000

.

50.000

orr,et

2.000 ,",oit,/dl ...
2.1'100 vol t,/dlv
10.0 n!l/dlv

..

Oft!let

Oellty

2.500

vol fa

2.500 volt!!
0.00000

,

FIGURE 7. WAVEFORMS FOR DISTRIBUTED LOADING

the terminating resistor when C = 560pF is substantially
greater than when C = 56pF.

TABLE 4. TRANSITION AND PROPAGATION TIMES-END
GATE

RT
(0)

TRANSISTION
TIMES (ns)

PROPAGATION
DELAYS (ns)

tr

tf

tpih

tphl

O(NoDist.
load)

4.0

2.6

3.1

5.0

o (Dis!.

4.4

3.6

4.4

6.4

Table 6 summarizes propagation and transition time data.
As in the preceding section, gate propagation delay
measured delay -3.6ns.
TABLE 6. SUMMARY OF TRANSITION TIMES AND
PROPAGATION DELAYS

40(=ZO)+
Disl.load

4.8

5.2

5.2

RT
(0)

7.8

PROPAGATION
DELAYS (ns)

TRANSISTION
TIMES (ns)

load only)

TR

I

TF

TpLH

I

TpHL

6.0

3.3

I

4.4

400/56pF
TABLE 5. TRANSITION TIMES-INTERMEDIATE GATE

RT
(0)

o (Dis!.

TRANSISTION
TIMES (ns)

PROPAGATION
DELAYS (ns)

tr

tf

tpih

6.6

5.6

Not measured

8.0

7.8

Not measured

I

6.0
9.0

I

8.3

8.0

I
I

8.3

Not measured

400/560pF
End Gate

tphi

IntGate

I

8.8

9.0

3.7

I

I

8.0

Not measured

z

o
;::<1>
c:c w

(..)1-

load only)
40(=ZO)+
Dist.load

I

End Gate
IntGate

AC Shunt Termination
This termination technique was previously explored in the
context of a single load. For the case of loads distributed
along a single line, the advantage of shunt termination is
that the tendency toward a three-level waveform with series
termination is absent. Figure 8 illustrates the waveforms
obtained with AC shunt termination. As previously
discussed, the corrected (for distributed loading) value of
the characteristic impedance is 400,.
The discussion of trading off waveform integrity for power
dissipation also applies here. The power consumed by

As is evident from a comparison of Tables 5 and 6, shunt
termination with a small capacitor (56pF) does not extract
as much propagation delay "penalty" as does series
termination-nor does a 56pF shunt termination cause a
tendency toward a three-level waveform on the bus. With a
560pF capacitor, the waveform is better in the sense that
there is less ringing, but, as indicated earlier, the power
dissipation of the terminating resistor is' substantially
increased.
From a comparison of Figures 7 and 8, series termination
appears to suppress ringing better than shunt terminationat least that shunt termination where, in order" to reduce
power consumed by termination resistors, the value of the
capacitor is relatively small. Also, the increased transition
times associated with series termination are very desirable
from the standpoint of minimizing both ringing and
ground bounce.

7-17

-0

~Z
c...

c:c

Application Note 9102
Termination Techniques
Table 7 illustrates termination techniques which can be
used ~at the receiving end of a trace; CI is the 'input
capacitance of the driven semiconductor. The first three
techniques require that the characteristic impedance of the
trace structure be well-defined and constant along the trace
run, which is complicated when a trace is to be run on both
interior and exterior layers of a PCB.
Diode termination allows uncontrolled impedance-such as
that obtained on a two-sided board where the trace-toground trace spacing is variable-but requires more
expensive components than other iechniques. In effect,
CMOS input circuitry is a mixture of the series and diode
termination techniques shown in Table 7.
In Table 7, the Termination Dissipation has been computed
by assuming a (worst-case) on source resistance. The
power dissipation expressions apply to use of the
terminating networks at either end of the line. For example,
the expression given for the dissipation of a series
termination applies whether the termination is used on the
sending (proper) end of the line or the receiving (improper)
end of the line.
Series termination has been analyzed in some detail. For
use at either the receiving or sending end, maximum clock
frequency is determined by assuming that, after a high-tolow transition, the input capacitor, CI, must discharge to a
voltage below 5% of VCC before the next clock low-to-high
transition. This requires that three ZOCI time constants
occur during one-half of the clock period, which leads to
the clock-frequency limitation shown for series termination
in Table 7.
The relatively large power consumed in termination
resistors can be a problem. AC shunt termination, as
defined in Table 7 and used in Figures 4 and 8, provides a
worthwhile low-power alternative, tei be applied at the
receiving end of a trace. In AC ,shunt termination, pulse
fidelity is traded off for power diSSipation: the larger the
value of the DC blocking capacitor, C1, the better the pulse,
but the higher the power consumption of the terminating
resistor.
In the limit as the value of C1 is made very large, the power
dissipation of the terminating network approaches that of
purely resistive termination. The improved pulse fidelity with
larger values of C1 is apparent from Figure 8. The maximum
value of C1 which still permits adequate charging/
discharging of t!1e shunt termination network over one-half
of the clock cycle is C1 < 1/SfCZO; this inverse clock-frequency limitation is given in the "Max fC" column of Table 7.
However, for C1 » 1/SfC ZO, the network is slow enough
that full charging never occurs, the network begins to
approach a purely resistive shunt terminator, and clock
frequencies are limited only by the driver.
AC shunt termination should be used whenever the DC
drive capability of the driving device is approached via
heavy TTL loading.

Decoupling CMOS
Clock-related noise on the VCC bus can arise if too
few decoupling capacitors are used [5, p.3.11-1]. It

is recommended that all board layouts allow for one
decoupling capacitor per semiconductor package. However, it is sometimes possible to remove some of the
decoupling capacitors after a working prototype is
developed. This is best done experimentally while carefully
monitoring emissions, particularly at frequencies less than
200M Hz:.' At those frequencies, cable radiation dominates
radiated emissions spectra. Assuming good grounding,
cable radiation is an accurate indicator of VCC bus
contamination.
On large (> 50-pin) devices with more than one VCC pin,
use one decoupling capacitor at each VCC pin. In these
cases, then, more than one decoupling capacitor per
semiconductor package is recommended.
Choosing the Value of a Decoupling CapaCitor
A simplified diagram of the equivalent circuit for the output
of a Harris CMOS device is shown in Figure 10. When the
circuit shown transitions from low to high, switch 81
connects to terminal A and current is drawn from the VCC
bus to charge the capacitor. On a high to low transition, the
switch connects to B; cu rrent is sourced by the capacitor as
it discharges into ground through S1. Note that the switch
is, in the ideal case, a "break before make" circuit, so that
no current is drawn from A to B as S1 changes state - a
common source of current consumption in early CMOS
logic.
Departures from ideality include the totem-pole effect: for
time intervals which are smaller than the transition time,
both the upper (PMOS) and lower (NMOS) transistors are
partially "on". Then, during both the low-to-high and
high-to-Iow transitions, there is a pulse of current drawn
from the VCC bus. This is in addition to the current pulse
required-and predicted by the model-for the charging of
Cs when making the low-to-high transition. Also, the
internal gates-those which precede the output gate-require
both totem-pole and charging currents (charging currents
for internal gates are much smaller than that required for the
output gate, as the source capacitance associated with
those gates is on the order of tens of femptofarads [1
femptofarad = 10- 15 farad]).
A decoupling capacitor is the VCC bus for the purpose of
supplying current during transitions. The inductance of a
VCC trace or plane precludes those sources from supplying
all of the rapidly-changing current required during a
transition. Between clock pulse transitions, a trace or plane
supplies recharge current to decoupling capacitors.
Recharging can take place over the much longer time of
one-half of the clock period.
A value of 0.1).1F will adequately decouple all known
AC/ACT glue logic and VLSI circuits (even heavily
loaded/fanned out), but the use of that relatively large value
should be resisted in order to maintain the highest possible
self-resonant frequency of the decoupling capacitor., Use
0.001 flF and 0.01 flF, not so much for reduced cost as for
the purpose of increasing the self-resonant frequency of
the decoupling capacitor.

7-18

Application Note 9102

56pF ~

56pF ~

560pF ~

560pF ~
Ch. I
Ch.:'

•
...

T1Pteoo!se

•

2.000 volt~/div
2.000 volt~/dlV
10.J ns/dlv

Oolta v

•

5.~00

Off,et

•

2.500

Off3et

•

=.500
1.600

Delay

volt!
volts
ns

volt.

FIGURE 8. WAVEFORMS FOR AC SHUNT TERMINATION

TABLE 7. RECEIVING END TERMINATION TECHNIQUES

TERMINATION

MAXIe

~c

J

o

1

5pF

1

--

6ZOC1
(667MHz*)

TERMINATION
DISSIPATION
Very Low:
p=VCC 2fCC1

PULSE
INTEGRITY
Improves with small
ZO,C1

(3.8mW)
Want LowZO

Series (Controlled ZO)

EC
1Cif C

NOTES
Transition times
increased.

Driver-limited

Very High:
VCC 2 (250mW)
2Z0

1

Good Reflected %
= 4.4Z0C1
rr-4.4ZOC1

Drive current

= VCC=(100mA)
Zo

Shunt (Controlled ZO)
0

o

R= Zo

T

~

1

1 (100 p

1

-6ZOC1
(33.3MHz, see text)

AC Shunt (Controlled ZO)

:b

Driver-Limited

Low to Moderate,
increasing with C1

Best with largest
possible value of

Must use low-ESL
C1 with short leads

P=VCC 2fC C1
(75mW, about same
as device)

C1 =1/6Z0fC
Intergrity improves
withC1

Want LowZO

Low

External diodes
Good with highcostly
speed Schotky
diodes or built-in
protection diodes of
some semiconductors

°1

Diode (Uncontrolled ZO)
• Examples are lor Zo = 50, Cl = 5pF, VCC = 5, IC = 30M Hz, Duty Cycle = 50%

7-19

App~ication

Vee

'

CMOS circuits. Two'-sided boards designed from an RF
standpoint coutd be used; ,but the low component density
associated with such boards is inconsistent with most
contemporary system design requirements.

Vee

t~

-£>1"

R2

Note, 9.102,

The "Best" Termination Technique: Series Resistor at
Driving End

R2

When loads do not require much OCcurrent, as with CMOS
inputs, the preferred termination technique for a single load
and large class of multiple distributed loads is a terminating
resistor at the driving end of the trace. The value of the
terminating resistor, RT, is ideally equal to the characteristic
impedance of the driven trace, ZO, as modified by any
distributed loading. The correction for distributed loading is
given in equation 1.

FIGURE 9. RESISTIVE TERMINATION IS USED IN MOST
STANDARD BUSES

Vee
~

Reduction of the value of a series terminating resistor from
RT = Zo'ieads to decreased propagation and transition
times, However, for even zero-length traces, reduction of
RT eventually leads to ringing. Although the internal diodes
in the input circuitry of Harris CMOS tend to limit ringing,
noise immunity problems can still occur.

*

FIGURE 10. EQUIVALENT CIRCUIT FOR CMOS OUTPUT

The Equivalent Series Inductance (ESL) of a
Decoupling Capacitor
The equivalent series inductance (ESL) of a decoupling
capacitor and the inductance of the leads/planes used to
connect the decoupling capacitor to a semiconductor
package should be as small as economics and manufacturing practicalities permit. This decreases both ringing and
emissions. It is shown in [5, pp. 3.9-7 through 3.9-10] that
maximum attenuation of noise on the power bus occurs at
the self-resonant frequency of the decoupling capacitor. To
have that attenuation occur at frequencies where ringing
and emissions suppression is otherwise difficult, (generally
35MHz to 90MHz) using a capacitor value chosen according to the previous section requires ESl's less than tOnH.
Surface-mount ("chip") capaCitors on a multilayer board
with both VCCimd ground planes are particularly desirable.
The ESL of a decoupling capacitor is at least as
important as its capaCitance. Above the self-resQnant
frequency of a decoupling capacitor which provides
filtering; that inductance should be as small as manufacturing techniques and economy permit.
Placement of Decoupling CapaCitor on a Board
A decoupling capaCitor should always be placed on that
end of the semiconductor package which points toward the
power entry point on aboard. One of the purposes of
decoupling is to minimize VCe: noise at thepbWer-entry
point, and the filtration implied by adecouplingcapacitor
should be between the semiconductorpackage.and the
power entry point.

ConclUSions and Recommendations
,Use Multilayer Boards
The Inductances aSSOCiated, with two-sided boards are
often too large for ,successful application of high speed

Increasing the value of the terminating resistor beyond Zo
tends to further enhance the smoothness of the pulse but
can lead to undesirable increases in propagation delays.
The resulting increased transition times tend to suppress
emissions.
For driving-end series termination with distributed loading
on lines 12 inches long, transition times at intermediate
loads are doubled relative to those at the end of the bus.
Longer buses lead to even greater increases in transition
times at intermediate bus points. Should this not be
tolerable, the alternative AC shunt termination discussed
below should be used.
An Alternative Termination Technique
In the above case and/or when a resistively-terminated bus
and/or heavy TIL loads are to be driven by CMOS gates,
AC shunt termination should be considered as an
alternative to putely resistive termination.
At least for the driven-end terminated case considered in
this report, AC shunt termination does not appear quite as
effictive as sending-end series termination in suppressing
'
ringing.
'When terminating high-speed traces, SIP resistors and
capaCitors 'should ,be avoided. The equivalent series
inductance (ESL) is too large In many applications. Discrete
SMO's are preferred to minimize ESL.
Minimize Power Bus Ringing to Minimize Interference
To minimize ringing on the power bus, -it is recommended
that CMOS devices ,which handle high-frequency periodic
signals be carefully decoupled from the power bus. Specifid
decoupling recommendations have been provided in this
'report.'
,

7-20

Application Note 9102
Bibliography
[1]

R.K. Keenan, FCC Emissions and Power Bus Noise (Second Edition), Pinellas Park, Florida: TKC, February 1988.

[2]

William R. Blood, Jr., MECL System Design Handbook (Fourth Edition, Rev. 1), Phoenix, Arizona: Motorola Inc., 1988.

[3]

RCNGE/Harris Semiconductor, GE Solid State Data Book (for) RCA Advanced CMOS Logic ICs, Somerville, N.J.: GE
Corporation, 1987.

[4]

J.D. Kraus, Electromagnetics (Third Edition), New York: McGraw Hill, 1984.

[5]

R.K. Keenan, Decoupling and Layout of Digital Printed Circuits, Pinellas Park, Florida: TKC, 1987.

[6]

R.K. Keenan, Digital Design for Interference Specifications, Pinellas Park, Florida: TKC, 1983.

[7]

H.H. Skilling, Electrical Engineering Circuits, New York: Wiley, 1958.

z

c

i=f3
--.....cc ""-cc
::.
.....
OW

a::

Harris Quality & Reliability
Introduction
Success in the integrated circuit industry means more than
simply meeting or exceeding the demands of today's
market. It also includes anticipating and accepting the
challenges of the future. It results from a process of
continuing improvement and evolution, with perfection as
the constant goal.
Harris Semiconductor's commitment to supply only top
value integrated circuits has made quality improvement a
mandate for every person in our work force - from circuit
designer to manufacturing operator, from hourly employee
to corporate executive. Price is no longer the only
determinant in marketplace ·competition. Quality, reliability,
and performance enjoy significantly increased importance
as measures of value in integrated circuits.

Quality organization is there to provide leadership and
assistance in the deployment of quality techniques, and to
monitor progress.

The Improvement Process

1

STAGEIV

I

d

PRODUCT
OPTIMIZATION

IMPACTON
PRO DUCT
QU ALITY

STAGE III
PROCESS
OPTIMIZATION
STAGE II
PROCESS
CONTROL

Quality in integrated circuits cannot be added on or
considered after the fact. It begins with the development of
capable process technology and product design. It
continues in manufacturing, through effective controls at
each process or step. It culminates in the delivery of
products which meet or exceed the expectations of the
customer.

STAGE I
PRODUCT
SCREENING
SOPHISTICATION OF
QUALITY TECHNOLOGY

FIGURE 1. STAGES OF STATISTICAL QUAUTY TECHNOLOGY

The Role of The Quality Organization
The emphasis on building quality into the design and
manufacturing processes of a product has resulted in a
significant refocus of the role of the Quality organization. c1n
addition to faCilitating the development of SPC and DOX
programs and working with manufacturing to establish
control charts, Quality professionals are involved in the
measurement of equipment capability, standardization of
inspection equipment and processes, procedures for
chemical controls, analysis of inspection data and feedback
to the manufacturing areas, coordination of efforts for
process and product improvement, optimization of
environmental or raw materials quality, and the
development of quality improvement programs with
vendors.
At critical manufacturing operations, process and product
quality is analyzed through random statistical sampling and
product monitors. The Quality organization's role is
changing from poliCing quality to leadership and
coordination of quality programs or procedures through
auditing, sampling, consulting, and managing Quality
Improvement projects.

Harris Semiconductor's quality methodology is evolving
through the stages shown in Figure 1. In 1981 we
embarked on a program to move beyond Stage I, and we
are currently in the transition from Stage II to Stage III, as
more and more of our people become involved in quality
activities. The traditional "quality" tasks of screening,
inspection, and testing are being replaced by more effective
and efficient methods, putting new tools into the hands of all
employees. Table 1 illustrates how our quality systems afe
changing to meet today's needs.

Harris Standard Flows
Harris Semiconductor offers a variety of standard product
flows which cover the myriad of application environmentsour customers experience. These flows run the gamut of.
low cost commercial parts to fully qualified JAN
microcircuits. All of these grades have one thing in
common. They result from meticulous attention to quality,
starting with design decisions made during 'product
development and ending with the .Iabeling of shipping
containers for delivery to our customers. The standard flows
offered are:

Commercial: Electrical performance guaranteed from
To support specific market requirements, or to ensure
OOCto +700 C
conformance to military or customer specifications, the
Quality organization still performs many of the conventionat
/883: Mil-Std-883 - compliant product: contact
quality functions (e.g., group testing for military products or
the factory or local Harris Sales Office
wafer lot acceptance). But, true to the philosophy that
for details on availability and specifications
quality is everyone's job, much of the traditional on-line.
measurement and control of quality characteristics is where Details of the individual process requirements are
it belongs - with the people who make the product. The contained in the flow charts on the following pages.

8-3

Harris Semiconductor Standard Processing Flows
COMMERCIAL
PROBE/DICE
PREPARATION
JAN CLASSB
HIGH/ROOM
TEMP
PROBE TEST

II

/883

VISUAL
INSPECTION
MODIFIED
MIL-STD-883
METHOD 2010
CONDITION B 50X
WITH QA INSPECT

VISUAL
INSPECTION
PER
MIL-STD-883
METHOD 2010,
CONDITION B,
WITH QA INSPECT

YES

ASSEMBLY (1 )

•

*

DIE ATTACH
CONTROL

OPERATION
QAMONITOR
SILVER GLASS DISPERSAL
MOUNT
SILVER GLASS BAKE

YES

SILVER GLASS CURE

YES

YES

SILVER GLASS FIRE

YES

YES

*

QA DIE ATTACH
CONTROL

WIRE BOND
WIRE BOND
CONTROL

*

QAWIREBOND
CONTROL

PRESEALCLEAN
PRESEAL INSPECT
ALL PRE-SEAL
OPERATIONS
IN CLASS 100
LAMINAR
FLOW

*I

QA PRESEAL INSPECT

2HOUR

YES
2 HOUR

YES
2 HOUR

AS APPLICABLE
YES

AS APPLICABLE
PER
MIL-STD-883
METHOD 2010,
CONDITIONB

YES

YES

WHEN REQUIRED

WHEN REQUIRED

PACKAGE SEALING

YES

YES

STABILIZATION BAKE

NO

YES

YES (5)

YES (50)
YES

GSI

II CSI I INSPECT

TEMPERATURE CYCLE
(CYCLES)

ADDITIONALLY
AVAILABLE

2 HOUR

CENTRIFUGE

YES

TIN PLATING/SOLDER DIP

NO

NO

*

YES

YES

QA LEAD FINISH
INSPECT

100% NONDESTRUCT
BOND PULL

YES

YES

GROSS LEAK TEST

AS APPLICABLE

YES

PIND TEST 100% 20G

PIND TEST 100% lOG

AS APPLICABLE

AS APPLICABLE

METHOD 2010
CONDITION A

FINE LEAK TEST

FRAME REMOVAL

NO

NO

LOAD SHIPPING TUBES

YES

YES

YES

YES

(1) Example for a PGA Package Part

8-4

Harris Semiconductor Standard Processing Flows (Continued)

~~CO~M~M~E~R~C~IA~L~~II~~~~/~88~3~~~
TEST

•

*
AC/DC SINGLE
INSERTION TEST
CAPABILITY;
HIGH/LOW TEMP

BURN-IN
QUALITY
CONFORMANCE
BY MIL-STD-883
METHOD 5005,
GROUPS A, B, C
AND D AS REQUIRED

I

-

OPERATION
QAMONITOR

ELECTRICAL TEST
SORTING OPERATION

f-*

-

IN HOUSE PACKAGE
MOISTURE MONITOR
CAPABILITY

-

COMPUTERIZED LOT
TRACEABILITY
MONITORING SYSTEM

'---

YES

NO

NO

QUAL SAMPLES

PREBURN-IN ELECTRICAL
TEST

NO

YES

BURN-IN (2)

NO

I

POST BURN-IN TEST

NO

160HOURS@
+1250 C,OR
PER
SLASH SHEET
YES

I

APPLY BURN-IN TEST

NO

YES

I

APPLY BURN-IN PDA
(AS APPLICABLE)

NO

YES

I

BRAND

YES

YES

EXTERNAL VISUAL
QUALITY
CONFORMANCE
INSPECTION

YES
GROUP A

YES
GROUPA,B;
C,D
(AS APPLICABLE)

IL-

FINAL DATA REVIEW

NO

YES

I

QAMONITOR

YES

SERIALIZE

h:
-

DELTAS PER
SLASH SHEET
REQUIREMENT
IF APPLICABLE

YES

f-*
I

PACKAGE & SHIP
OR STOCK
(2) Burn-in lest temperatures can be increased and time reduced per regression tables in MiI-Sld-S83, Method 1015

Advantages of Standard Flows
Wherever feasible, and in accordance with good value
engineering practice, the Ie user should specify device
grades based on one of the five standard Harris
manufacturing flows. These are more than adequate for the
overwhelming majority of applications and may be utilized
quite effectively if the user engineer bases designs on the
standard data sheet, military drawing or slash sheet (as
applicable) electrical limits.
Some of the more important advantages gained by using
standard as opposed to custom flows are as follows:
• Lower cost than the same or an equivalent flow executed
on a custom basis. This results from the higher efficiency
achieved with a constant product flow and the
elimination of such extra cost items as special fixturing,
test programs, additional handling and added
docu mentation.
• Faster delivery. The manufacturer often can supply many
items from inventory and, in any case, can establish and

maintain a better product flow when there is no need to
restructure process and/or test procedures.
• Increased confidence in the devices. A continUing flow of
a given product permits the manufacturer to mointor
trends which may bear on end-product performance or
reliability and to implement corrective action, if
necessary.
• Reduction of risk. Since each product is processed
independent of speCific customer orders, the
manufacturer absorbs production variability within its
scheduling framework without major impact on
deliveries. In a custom flow, a lot failure late in the
production cycle can result in significant delays in
delivery due to the required recycling time.
Despite the advantages of using standard flows, there are
cases where a special or custom flow is mandatory to meet
design or other requirements. In such cases, the Harris
Marketing groups stand ready to discuss individual
customer needs and, where Indicated, to accomodate
appropriate custom flows.

8-5

oa ~ ,

~:!
.... cc

- ...

cC:>
....
OW

a:

Measurement

service until calibration is performed. The Quality
organization performs periodic audits to assure proper
control in the using areas. Statistical procedures are used
where applicable in the calibration process.

Analytical Services La'boratory
Harris facilities, engineering, manufacturing, and p~oduct
assurance are supported by the Analytical Services
Laboratory. Organized into chemical or microbeam analysis
methodology, staff and instrumentation from both labs
cooperate in fully integrated approaches necessary to
complete analytical studies. The capabilities of each area
are shown below.

Field Return Product Analysis System
The purpose of this system is to enable Harris' Field Sales
and Quality operations to properly route, track and respond
to our customers' needs as they relate to product analysis.

SPECTROSCOPIC
METHODS: Colorimetry,
Optical
Emission, Ultraviolet Visible, Fourier Transform-Infrared,
Flame Atomic Absorption, Furnace Organic Carbon
Analyzer, Mass Spectrometer.
CHROMATOGRAPHIC METHODS:
Ion Chromatography.

Gas Chromatography,

THERMAL METHODS: Differential Scanning Colorimetry,
Thermogravimetric Analysis, Thermomechanical Analysis.
PHYSICAL
Rheometry.

METHODS:

,CHEMICAL METHODS:
Ion Electrodes.

Profilometry,

Microhardness,

Volumetric, Gravimetric, Specific

ELECTRON MICROSCOPE: Transmission Electron Microscopy, Scanning Electron Microscope.
X-RAY METHODS: Energy Dispersive X-ray Analysis
(SEM), Wavelength Dispersive X-ray Analysis (SEM),
X-ray Fluorescence Spectrometry, X-ray Diffraction
Spectrometry.
SURFACE ANALYSIS METHODS: Scanning Auger Microprobe, Electron Spectroscope/Chemical Analysis, Secondary Ion Mass Spectrometry, Ion Scattering Spectrometry,
Ion Microprobe.
The department also maintains ongoing working
arrangements with commercial, university, and equipment
manufacturers' technical service laboratories, and can
obtain any materials analysis in cases where instrumental
capabilities are not available in our own facility.
Calibration Laboratory
Another important resource in the product assurance
system is Harris Semiconductor's Calibration Lab. This area
is responsible for calibrating the electronic, electrical,
electro/mechanical, and optical equipment used in both the
production and engineering areas. The accuracy of
instruments used at Harris in calibration is traceable to the
National Bureau of Standards. The lab maintains a system
which conforms to the current revision of MIL-STD-45662,
"Calibration System Requirements."
Each instrument reqUiring calibration is assigned a
calibration interval based upon stability, purpose, and
degree of use. The equiprnent is labeled with an
identification tag on which is specified both the date of the
last calibration and of the next required calibration. The
Calibration Lab reports on a regular basis to each user
department. Equipment out of calibration is taken out of

The Product Failure Analysis Solution Team (PFAST)
consists of the group of people who must act together
to provide timeiy, accurate and meaningful results to
customers on units returned for analysis. This team includes
the salesman or applications engineer who gets the parts
from the customer, the PFAST controller who coordinates
the response, the Product or Test EngIneering people who
obtain characterization and/or test data, the analysts
who failure analyze the units, and the people who provide
the Ultimate corrective action. It is the coordinated effort of
this team, through the system described in this document
that will drive the Customer responsiveness and continuous
improvement that will keep Harris on the forefront of the
semiconductor business.
The system and procedures define the processing of
product being returned by· the customer for analysis
performed by Product Engineering, Reliability Failure
Analysis and/or Quality Engineering. This system is
designed for processing "sample" returns, not entire lot
returns or lot replacements.
The philosophy is that each site analyzes its own product.
This applies the local expertise to the solutions and helps
toward the goal of quick turn time.
Goals: quick, accurate response, uniform deliverable
(consistent quality) from each site, traceability:
The PFAST system is summarized in the following steps:
1) Customer calls the sales rep about the unit(s) to return.
2) Fill out PFAST Action Request - see the PFAST form in
this section. This form is all that is required to process a
Field Return of samples for failure analysis. This form
contains essential information necessary to perform root
cause analysis. (See Figure 2).
3) The units must be packaged in a manner that prevents
physical damage and prevents ESD. Send the units and
PFAST form to the appropriate PFAST controller. This
location can be determined at the field sales, office or rep
using "look-up" tables in the PFAST doc.ument.
4) The PFAsT controller will log ttie units and route them to
ATE testing for data log.
5) Test results will be reviewed and compared to customer
complaint anda decision will be made to route the failure
to the appropriate analytical group.
6) The customer will be contacted with the ATE test results
and interim findings on the analysis. This may relieve a
line down situation or provide a rapid disposition of
material. The customer contact is ,valuable in analytical
process to insure root cause is found.

8-6

7) A report will be written and sent directly to the customer
with copies to sales, rep, responsible individuals with
corrective actions and to the PFAST controller so that
the records will capture the closure of the cycle.
8) Each report will contain a feedback form (stamped and
preaddressed) so that the PFAST team can assess their
performance based on the customers assessment of
quality and cycle time.
9) The PFAST team objectives are to have a report in the
customers hands in 28 days, or 14 days based on
agreements. Interim results are given realtime.
Failure Analysis Laboratory
The Failure Analysis Laboratory's capabilities encompass
the isolation and identification of all failure modes/failure
mechanisms, preparing comprehensive technical reports,
and assigning appropriate corrective actions. Research vital
to understanding the basic physics of the failure is also
undertaken.

Failure analysis is a method of enhancing product reliability
and determining corrective action. It is the finaland crucial
step used to isolate potential reliability problems that may
have occurred during reliability stressing. Accurate analysis
results are imperative to assess effective corrective actions.
To ensure the integrity of the analysis, correlation of the
failure mechanism to the initial electrical failure is essential.
A general failure analysis procedure has been established
in accordance with the current revision of MIL-STD-883,
Section 5003. The analysis procedure was designed on the
premise that each step should provide information on the
failure without destroying information to be obtained from
subsequent steps. The exact steps for an analysis are
determined as the situation dictates. (See Figures 3 and 4).
Records are maintained by laboratory personnel and
contain data, the failure analyst's notes, and the formal
Product Analysis Report.

FIGURE 4. DESTRUCTIVE

FIGURE 3. NON-DESTRUCTIVE

o!I~
>-:::i
I- -

-.... '"<

<
::> ....
oUJ

a:

8-7

--.

1I1~6BBl§

Request #
Customer Analysis #

PFAST ACTION REQUEST
Date:

ORIGINATOR

CUSTOMER

No.
DEVICE TYPE/PART No.
No. SAMPLES RETURNED

LoCATION

LoCATION/PHONE

PURCHASE ORDER

No.

QUANTITY RECEIVED

THE COMPLETENESS AND TIMELY RESPONSE OF THE EVALUATION IS DIRECTLY RELATED TO THE COMPLETENESS
OF THE DATA PROVIDED. PLEASE PROVIDE ALL PERTINENT DATA. ATTACH ADDITIONAL SHEETS IF NECESSARY.

DETAILS OF REJECT

TYPE OF PROBLEM
1.

o

(Wbere appropriale serialize units and specify for each)

INCOMING INSPECTION
ScREEN
SAMPLE INSPECTION
No. TEsTED
No. OF REJECTS
ARE RESULTS REPRESENTATIVE OF PREVIOUS LOTS?
YES
NO
BRIEF DESCRIPTION OF EVALUATION
AND RESULTS ATTACHED
2.
IN PROCESS/MANUFACTURING FAILURE
BOARD CHEcKOUT
SYSTEM CHECKOUT
FAILED ON TuRN-ON
FAILED AFTER
HOURS OPERATION
WAS UNIT RETESTED UNDER INCOMING INSPECTION
CONDITIONS?
YES
NO
BRIEF DESCRIPTION OF HOW FAILURE WAS ISOLATED
TO COMPONENT ATTACHED
3.0 FIELD FAILURE
FAILED AFTER
HOURS OPERATION
EsTIMATED FAILURE RATE _ _% 'PER 1000 HOURS
END USER
LocATION
AMBIENT TEMPERATURE
C
MIN.
C
MAx.
C
RIlL. HUMIDITY
%
END USER FAILURE CORRESPONDENCE ATTACHED

--

o

o

o

TEsT CONDITIONS RELATING TO FAILURE
TEsTER USED (MFGRIMODEL)
TEsT TEMPERATURE
TEsT TiME:
CONTINUOUS TEsT
ONE SHOT (T = _ _ SEC)

o

0100%

o
o
o

o
o
o

--

o

0

o
o

DESCRIPTION OF ANY OBSERVED CONDITION TO
WHICH FAILURE APPEARS SENSITIVE:

o

1. 0 DC FAILURES

o OPENS 0 SHORTS 0 LEAKAGE 0 STRESS
o POWER DRAIN 0 INPUT LEVEL 0 OUTPUT LEVEL
o LIST OF FORCING CONDITIONS AND MEASURED

--

o

o

o

RESULTS FOR EACH PIN IS ATTACHED

o POWER -SUPPLY SEQUENCING ATTACHED
2.0

--

--

AC FAILURES
LIST FAIUNG CHARACTERISTICS

ADDRESS OF FAIUNG LocATION (IF APPUCABLE)

--

ATTACHED:

o

o LIST OF POWER SUPPLY AND DRIVER LEVELS
(Include pictures of waveforms).

o LIST OF OUTPUT LEVELS AND LOADING CONDITIONS
o INPUT AND OUTPUT TiMING DIAGRAMS
o DESCRIPTION OF PATTERNS USED

ACTION REQUESTED BY CUSTOMER

SPECIFIC ACTION REQUESTED
IMPACT OF FAILED UNITS ON CUSTOMER'S SITUATION:

---

CUSTOMER CONTACTS WITH SPECIFIC KNOWLEDGE OF REJECTS
NAME
POSITION
PHONE

3.0

4.0

(If not standard patterns, give very complete
description including address sequence).
PROM PROGRAMMING FAILURES
ADDRESS OF FAILURES
PROGRAMMER USED (MFGIMODEL/REV. No.)
PHYSICAUAssEMBLY RELATED FAILURES
SEE COMMENTS BELOW 0 SEE ATTACHED

o

Additional Comments:

FIGURE 2. PFAST ACTION REQUEST

8-8

Reliability

• Data base for determining FIT Rates and Failures Mode
trends used drive Continuous Improvement.

Reliability Assessment and Enhancement
At Harris Semiconductor, reliability is built into every
product by emphasizing quality throughout manufacturing.
This starts by ensuring the excellence of the design, layout,
and manufacturing process. The quality of the raw materials
and workmanship is monitored using statistical process
control (SPC) to preserve the reliability of the product. The
primary and ultimate goal of these efforts is to provide full
performance to the product specification throughout its
useful life. Product reliability is maintained through the
following sources: Qualifications, In-Line Reliability
Monitors, Failure Analys·is.
Qualifications
Qualifications at Harris de-emphasize the sole dependence
on production product which is only available late in the
development cycle. The focus is primarily on the use of test
vehicles to establish design ground rules for the product
and the process that will eliminate any wearout
mechanisms during the useful life of the product. However,
to comply with the military requirements concerning reliability, product qualifications are performed. (See Figure 5).
In-line Reliability Monitors
In-line reliability monitors provide immediate feedback to
manufacturing regarding the quality of workmanship,
quality of raw materials, and the ultimate reliability
implications. The rudimentary implementation of this
monitoring is the "First Line of Defense," which is a pass!
fail acceptance procedure based on control charts and
trend analysis. The second level of monitoring is referred to
as the "Early Warning System" and incorporates wafer level
reliability concepts for extensive diagnostic and
characterization capabilities of various components that
may impact the device reliability or stability. The quick
feedback from these schemes allows more accurate
correlation to process steps and corrective actions.

• Major source of reliability data for customers.
• Customers have used this data to qualify Harris
products.

Reliability Fundamentals
Reliability, by its nature, is a mixture of engineering and
probability statistics. This combination has derived a
vocabulary of terms essential for describing the reliability of
a device or system. Since reliability involves a measurement
of time, it is necessary to accelerate the failures which may
occur. This, then, introduces terms like "activation energy"
and "acceleration factor," which are needed to relate results
of stressing to normal operating conditions (see Table 1).
Also, to assess product reliability requires failures.
Therefore, only a statistical sample can be used to
determine the model of the failure distribution for the entire
population of product.
Failure Rate Calculations
Reliability data for products may be composed of
several different failure mechanisms and requires careful
combining of diverse failure rates into one comprehensive
failure rate: Calculating the failure rate is further complicated because failure mechanisms are thermally accelerated
at varying rates and thereby have differing accelerating factors. Additionally, this data is usually obtained a variety of
life tests at unique stress temperatures. The equation below
accounts for these considerations and then inserts a statistical factor to obtain the confidence interval for the failure
rate.
FIT=

K

1=1

xM

L

j=1

Product/Package Reliability Monitors

B=

Reliability of finished product is monitored extensively
under a program called Matrix I, II, III monitor. All major
technologies are monitored.

K=

'"' of distinct possible failure mechanisms
'"' of life tests being combined
'"' of failures for a given failure mechanism
1= 1, 2, ... B

Matrix 1- Has a higher sampling size and rate per week and
uses short duration test, usually less than 48 hours to assess day to day, week to week reliability. High volume types
are prevalent in this data. Stresses - Operating Life, Static
Life and HAST. TA = +125 0 C to +200o C
Matrix II - Longer duration test, much like requaliflcation.
The sample sizes are reduced in number and frequency,
yet meet or exceed the JEDEC Standard 29. Stresses
Operating Life, Storage, THB, Autoclave, Temp Cycle, and
Thermal Shock.
Matrix III - Package specific test. Tests Solderability, Lead
Fatigue,
Physical
Dimensions,
Brand
Adhesion,
Flammability, Bond Pull, Constant Acceleration, and
Hermeticity.
Data from these Monitor Stress Test provides the following
information:
• RoUtine reliability monitoring of products by die
technology and package styles.

(BL Xi

TOG) =

Total device hours of test time (un accelerated) for
Life Testj
.

AFij =

Acceleration factor for appropriate failure mechanism 1 1, 2, ... K

M=

Statistical factor for calculating the upper confidence limit (M is a function of the total number of
failures and an estimate ofthe standard deviation
of the failure rates)

=

In the failure rate calculation, Acceleration Factors (AFij) are
used to derate the failure rate from thermally accelerated Life
Test conditions to a failure rate indicative. of use temperatures. Though no standard!! exist, a temperature of +55 0 C
has been popular and allows some comparison of product
failure rates. All Harris Semiconductor Reliability Reports will
derate to +550 C at both the 60% and 95% confidence
intervals.

8-9

oII~
>-::::i

-.....cC-""cC

I- -

::> .....

OW

a:

RELIABILITY FOCUS

FLOW - PRODUCT DEVELOPMENT

I

PRODUCT DEFINITION REVIEW

I

• Assumes Process Development Required

I

CONCEPT REVIEW

I

• Evaluate Reliability Risks Factors
• Attain CommitmentforTestVehicle(T.V.) Development

I

DESIGN REVIEW PART 1

l-

• Review TestVehicle Development and Stress Test Plan
• Review Package Requirements
• Review Latent Failure'Mechanism History for Design Sensitivity and Elimination
• Review Ground Rules for Design and Elimination of Wearout Mechanisms
• Review Process Characterization, Ststistical Control & Capability which are Design
Considerations

I

DESIGN REVIEW PART 2

• Review Test Vehicle Stress Results

J

• -Review Device Modeling & Simulations
.- Review Process Variability & Producibility
• Define Wafer Reliability Monitor Vehicles, Application of Early Warning System

I

LAYOUT REVIEW PART 1

~

• Verify Wearout Mechanisms are Eliminated by Design & Process Control
(Test Vehicle + SPC)
• Evaluate Design of Chip to Package Risk Factors
• Review Ground Rule Checks (ORCs)
• Establish Reliability Test, Stress and Failure Analysis Capabilities. Project Failure Rate
Based on T.V. Oats.

I

LAYOUT REVIEW 2

I

EVALUATION REVIEW

+

I

• Review Burn-In Diagrams for Production and Qualification

I

• Review Product Characterization to Data Sheet, ESD, Latch-up & DPA Results &
Define Corrective Actions

• Review Overall Qualification Plan & Begin.Balance of Life Test

• Review of-Ufe Test Oats & Failure Mechanisms. Define Corrective Actions
• Utilize Ststistical-Designof Experiments (DOX) if Required to Adjust Process or DeSign
• Define Necessary Changes to Eliminate Any Systematic Failure Mechanism
• .tf Mature Process - Grant GeReric Release
'"

I

rI

NEW PRODUCT TRANSFER

MANUFACTURE

• Qualification Requirements Complete and Presented. Meet FIT Rate Requirements

I

• Review Infant Mortality (I.M.) Burn-in Results. If Greater Than 1 % at 1250 C
Determine I.M. Burn-in Requirements

J-

• Reliabiltiy Monitors:
~ Real Time Early Warning Wafer Level Reliability control
~

Real Time Reliability Control of Burn-in PDA with Control Charts

~

Add-On Life Testing: - Mil Std Group C & 0
- IndustriaVCommercial Life Testing

\

I
t-t

SHIPMENT

CONTINUOUS IMPROVEMENT

I
l-

• Trend Analysisof Reliability Performance Used to Develop Product Improvements
Special Studies

• High Quality and Reliability Products to Harris Customers

• Failure Analysis - Determine Assignable Cause of Failure
• Closed Loop Corrective Action Process
• Continuous Improvement Objectives In Product Reliability & Quality

FIGURE 5. NEW PROCESS PRODUCT DEVELOPMENT AND LIFE CYCLE

8-10

Acceleration Factors
The Acceleration Factors (AF) are determined from the
Arrhenius Equation. This equation is used to describe
physiochemical reaction rates and is an appropriate model
for expressing the thermal acceleration of semiconductor
failure mechanisms.
AF=

EXP

[~G
K '\ Tuse

AF =
Ea =
K

=

-__1_) ]

Both Tuse and Tstress (in degrees Kelvin) include the
internal temperature rise of the device and therefore
represent. the junction temperature. With the use of the
Arrhenius Equation, the thermal Activation Energy (Ea) term
is .a major influence on the result. This term is usually
empirically derived and can vary widely.

Tstress

Acceleration Factor
Thermal Activation Energy in eV from Table 8
'Boltzmann's Constant (8.62 x 10-5 eVfJK)

TABLE 1. FAILURE RATE PRIMER
GLOSSARY OF TERMS
TERMS/DEFINITION

UNITS/DESCRIPTION

FAILURE RATE)"

FIT - Failure In Time

For Semiconductors, usually expressed in FITs.

1 AT - 1 failure in 109 device hours.
Equivalent to 0.0001 %/1 000 hours
FITs =
x 109 xm
Failures

Represents useful life failure rate (which implies a .constant
failure rate).

*
::* Devices x * hours stress x AF

FITs are not applicable for infant mortality or wearout failure
rate expressions.

m- Factor to establish Confidence Interval
109 - Establishes in terms of ATs
AF - Acceleration Factor at temperature for a given failure
mechanism

MTTF - Mean Time To Failure

Mean Time is measured usually in hours or years.

For semiconductors, MTIF is the average ormean life expectancy
ofadevice.

1 Year = 8780 hours

If an exponential distribution is assumed then the mean time to
fail of the population will be when 83% of the parts have failed.

.' Wben working with a constant failure rate the MTIF can be
calculated by taking the reciprocal of the failure rate.
MTIF = 1/).. (exponential model)
Example: =10 ATs at +550 C
The MTIF is: MTIF = 1/).. = 0.1 x 109 hours
= 100M hours

CONFIDENCE INTERVAL (C. I.)
Establishes a Confidence Interval for failure rate predictions.
Usually the upper limit Is most significant in expressing failure
rates.

. Example:
"10 FITs@a95%C.I. @ 550 C· means only that you are 95%
certain the the FITs <10 at +550 C use conditions.

o/l~

~~
- <=
....
<
::. -

....

OW

II:

8-11

Activation Energy
To determillethe Activation Energy (Ea) ola mechanism
(see Table 2) you must run at least two (preferably inore)
teSts'ah:lifferent stresses (ternpetatur'e 'and/or Voltage): The
stresses will prOvidethe:tlme' to failure (Tf) for the
Jjol'ulatlonswhlch will allow the simultaneous solution for
the Activation Energy by putting the experimental results
into the following equations.
In

In

Then, by subtracting the two equations, the Activation
Energy becomes the only variable, as shown.

data on all factors necessary to calculate ana verifY the
reported ,failure rate (in FITs) using the methods"outlined in
t,hl,s primer."
"
'" '
" '
'

Qualification Procedures
New products are'r~liably'ilitrociucedto, maik~t

by th~,
proper use of design techniques and strict adherericeto
process layout ground rules. Each design is reviewed from
its concE1ption through early production to ensure
compliance to minimum failure rate stand'ards. Ongoing
monitoring of reliability performance,' is,' ,accomplished
through compliance to 883C and standard, Quality
Conforinancelnspection as defined In M'ethod '5005.

New process/prOduct'qualifications haile, tWo major
requirements Imposea. First is a check to verify the proper
use of process methodology, design techniques, and layout
ground rules. Second is a series of stress tests designed to
Ea = K* ((In(tf1) - In(tf2))/(1/T1 - 1/T2))
accelerate failure mechanisms and demonstrate the
The Activation Energy may be estimated by graphical reliability of Integrated circuits.
analysis plots. Plotting In time and In temperature then
provides a convenient nOI)1()gram that Ilolves(estlmates) the, From the earliest stages of a new prociuct's life, the ci~slgn
phase, through layout, and in every step of the manufactur~
Activ~tIOr:1 Energy.
'
ing~process; 'reliability Is an integral part of every Harris
Table 3 is a summary for the L7 process.
Semiconductor product. This kind of attention to detail
All Harris Reliability Reports from qualifications and Group "from the ground up", is the re,ason, why our customerll can
C1 (ali high temperature operati'm;), life tests) will provide the, expect the highest quality for any application.
TABLE 2. FAILURE MECHANISM
FAILURE
MECHANISM

ACTIVATION
':'NERQY

" ,', SCREI;NING AND,
TESTING METHODOLOGY

Oxide Dl;lfects

0.3-0.5eV

Hfgh temperatureoperilting life (HTOL) and
, voltage stress. Defect denSity ~st vehicles.

,Silicon
Defects (Bulk)

CONTROL METHODOLOGY

0.3-0.5eV" , HTOL & voltage stress screens.

Corrosion

0.45eV
"

Assembly
Defects
Electromigratlon
- AI Line
- Contact

Vendor Stetistical ,Quality ,Control programs, and '
Ststlstical Process Control on thermal prOCess9ll.

Highly accelerated stress tesing (HAST)'

Passivation dopant control, hermetic seal control,
improved mold compounds"and product handling.

Temperature cycling, temperature and
mechanical sho,ck, and environinental
stresSing.

Vendor Statistical Quality Control programs,'
Statlstcal' ProceSs Control of assembly p~ocesses
proper handling methods.

TestVehlcle characterizations at highly
elevated temperatures..

Design ground rules, wafer process statistical
process steps, photoresist, metals and
passivation

Mask FAB comparator; print checks, defect
density monitor in FAB, voltage stress test
ahdHTOL.

Cieani'oom control"clean mask"pel~lcIeS
Statistical Process Control or photoresistfetch processes.
"

,"

0.5-0.7eV

O.6eV:
0.geV

Mask Defecls/
Photoresist
Defects

0.7eV

Contamination

1.0eV

Statistical Process Control of oxide parameters,
defect density control, and voltage stress testing.

"

C-V stress at oxide/interconnect,-wafer
. FAB device stress test (EWS).and HTOL."

",'

Charge
Injection

HTOL & oxide characterization.

1.3eV

statistical Process cOntrol of C-V data, oxide! .
interconnect cleans,hlgh integrity glassivatlon
and clean assembly processes.
Design ground rules, wafer level Statistical
Process Control and critical dimensions for
oxides.

TABLE 3. HIGH TEMPERATURE OPERATING LIFE TEST SUMMARY

GENERIC
GROUP
C-105-5

GROUP NAME
Microprocessor
and Peripherals

PROCESS DESCRIPTION
SAJICMOSL7

8-12

QUANTITY

QUANTITY
FAIWRE

HOURS
@125 0 C

1452

0

5.72E+06

FAILURE
RATEFITa
@55 0 C60%CI
2

Harris High Reliability Product Specification Highlights
Harris Semiconductor is a leading supplier of high reliability
integrated circuits to the military and aerospace community
and takes pride in offering products tailored to the most
demanding applications requirements. Our Manufacturing
facilities are JAN-Certified to MIL-M-38510 and provide
JAN-qualified and MIL-STD-883 compliant products as
standard data book items. This DSP Data Book contains
detailed information on high-reliability integrated circuits
presently available from Harris Semiconductor.
The intent of the /883 data sheet is to provide to our
customers a clear understanding of the testing being
MIL-STD-883
performed
in
conformance
with
requirements. Additionally, it is our intent to provide the
most effective and comprehensive testing feasible.
Document Control
Harris has established each of the /883 data sheets as an
internally revised controlled document. Any product
revision or modification must be approved and signed-.off
throughout the manufacturing and engineering sections.
Harris has made every effort to ensure accuracy of the
information in this data book through quality control
methods. Harris reserves the right to make changes to the
products contained in this data book to improve
performance, reliability and producibility. Each data sheet
will use the printed date as the revision control
identification. Contact Harris for the latest available
specifications and performance data.

/883 Data Sheet Highlights
Each specific /883 data sheet documents the features,
description, pinouts, tested electrical parameters, test
circuits, burn-in circuits, die characteristics, packaging and
design information. The following are notes and
clarifications that will help in applying the information
provided in the data sheet.
Absolute Maximum Ratings: These ratings are provided
as maximum stress ratings and should be taken into
consideration during system design to prevent conditions
which may cause permanent damage to the device.
Operation of the device at or above the "Absolute Maximum
Ratings" is not intended, and extended exposure may affect
the device reliability.

Reliability Information: Each /883 data sheet contains
thermal information relating to the package and die. This
information is intended to be used in system design for
determining the expected device junction temperatures for
overall system reliability calculations.
Packaging: Harris utilizes MIL-M-38510, Appendix C for
packages used for /883 products. The mechanical
dimensions and materials used are shown for each
individual product to complete each data sheet as a self
contained document.
D.C. and A.C. Electrical Parameters: Tables 1 and 2
define the D.C. and A.C. Electrical Parameters that are
100% tested in production to guarantee compliance to
MIL-STD-883. The subgroups used are defined in
MIL-STD-883, Method 5005 and designated under the
provisions of Paragraph 1.2.1a. Test Conditions and Test
Circuits are provided for specific parameter testing.
Table 3 provides additional device limits that are
guaranteed by characterization of the device and are not
directly tested in production. Characterization takes place
at initial device design and after any major process or
design changes. The characterization data is on file and
available demonstrating the test limits established.
Table 4 provides a summary of the test requirements and
the applicable MIL-STD-883 subgroups.
Burn-In Circuits: The Burn-in circuits defined in the
individual data sheets are those used in the actual
production process. Burn-in is conducted per MIL-STD883, Method 101 5.
Design Information Sections: Harris provides an
additional Design Information Section in many of the data
sheets to assist in system application and design. This
information may be in the form of applications circuits,
typical device parameters, or additional device related user
information such as programming information. While this
information cannot be guaranteed, it is based on actual
characterization of the product and is representative of the
data sheet device.

O/l~
>--co
..IcC

.. =
cC-

::1..1

W
C a:

8-13

r----f-"-"~~.;-,HighR:eliabUity

Products,hlforrnation ......'-'. ;. .,~';"""',.....,-----,

HarEis'·. High ,Reliability Products are' all prodiJced in"
accordanoe" wit!1l military specifications and, standards,
primarily' MIL.';'M;,3851 0 (General Specifications for
Microoircuits)'cInd . MIL-STO-883 (Test Methods .and
Procedures for Microelectronics).
M]L-STO.,-883 contains test.methodsand proc~ures for
various .electrical, mechanic.al and,' environmental tests.as
well as requir.ementsfor screening; qualification and, quality
conformance. inspection.' Method 5004 of MIL-STO-883
lists the 100% screening tests which are required for each
qf t)1~.produ,c:t assural'1,~e, ~Iasses, d~fin~d;above.
Following the devic8,screening, samples' are removed from
the production lot(s) for Quality Conformance Inspection
testing. This testing Is divided .intofour inspection ~roups:
A,B, Gand O,whlch.areperformed at prescribed 'intervals
per MIL-M-3851 0 to assure:the processes are ·in,control·
and to ensure the continued quality level ·of the product
being produced.
,":,
Group A' electrical ilispection •..involves dynamic, static,
functional and switching.tests'at maximum, minimum and
room, operating· temperatures. Sample sizes' and specific
tests 'performed depem::li ;.upon ·the' 'particular pro,duct
assurance class chOsen., Eledtri!::ak test.· sampling': is
performed on all subgroups as defined in MIL-STO-883"
Method 50bS;' , .., . , . ,
.

GrollP"C is oriented,toward.die integrity and consists of,
operating life testing as defined· in MIL-STO.,,883;'Method
5005.:.
Group 0 enilironinentart~~ting is p~ovi,ded to ~eritY die and.
package reliability. Amoiig .. the,~roup.Dtes~; are leae:!
integrity,' ~ermeticity,tetnpe'rature'cycling, thElrmal. and'
rriec'h~nioefsh()~k, an~ !X'nsta~!aCceleratiori. "
MIL-M-38510: requires that Group A and Group B
inspection be Perf<;>rmea on each lot, while Group G
inspection must be dgneevE!ry 311'10riths anll Group P every
6fT1ontiis to ,be in .compliance wiJh MIL-:M-3~p10 JAN
rjlquir!lments. To ,limit the amo!;!n! ottesting, MIL -M-:3851 b
allows the multitude of micro· circuits to pe grolip.ed by
technology, commonly known as "generic families"'. Thus,
one group C performed will cover all parts included In that
generiq family, ,for three months.. For Group 0, whi9h is
package related, although there, are some restrictions, olle
Gr<,>up '0 p6rformed'on a 24;'pin ceramic'dual-in-'line
packaged part will bover all devices. in the same package
. . . ','
."
regardless' of the technology grpbp. '
..

"',

':'

"",'

"

For MIL-STD.,883 products, Groups A and B are required
oneliCh 10t,Groups G.and 0 are required eVery'52 weeks
by generic die, family and package fabricated:.and
manufactured from the same plant a!l·the ,die and .peck·age
represented. ".
.')

Group B inspection includes tests. for. marking
permimf;lnCy, .in~errial' 'visual and mechanical'cbrre«tness,
bondsftength, apd solderabutty.lt isinterided to' provide
assurance
the absence of lot::to-Iotfabricafior, . and
manufacturing variances. Group B tests are again defined". ,.
in test Met"'od 5005.

of

'ii:·

"

.",!i','

.'

8'-14

. . . - - - - - - - - - General Test Philosophy - - - - - - - - - - - ,
The general philosophy for test set development is to
supply test software that guarantees the, high performance
and quality of the products being designed and
manufactured by Harris. The general final test set includes a
guardbanded initial test program and a QA test program for
the quality test step. Characterization software is an
additional test program that parametrically measures and
records the performance of the device under test. This test
set is used to evaluate the performance of a product and to
determine the acceptability of non-standard Source Control
Drawings. BSPEC and RSPEC test programs are'custom
final test programs written to conform to customer
specifications.
The general test development strategy' is to develop
software using a "shell" programming technique which
creates standard' test program flows, and reduces test
development a~d execution tim'es. Statistically derived
guardbands are utilized in the "shell" programs to null out
test system variability. High performance hardware
interface designs are' incorporated for maximized test
effectiveness, and efficient fault graded vector sets are
utilized for functional and AC testing.
The initial step in generating the test set is the test vector
generation. The test ve,ctors are the'binary stimulus applied
to the device under test to functionally test the operation of
the product. The vectors are developed against a behavioral
model that is a software representation of the device
functio~ality. The output of the behavioral model can be
translated directly to ATE test vectors or prepared for CAD
simulation.
The philosophy' in the generation of' test vectors is to
develop efficient fault graded patterns with a goal of greater
than 90% fault coverage. There is no intent to generate a
worst case or best case noise vector set. The intent is to
maximize fault coverage through efficient vector use.
Generally only' one vector set will be required to enable
complete test cbversg,e within' a given test program.

Exceptions to this would be vector generation to test certain
identified critical AC speed paths or DC vectors for testing
VIHNIL ,parameters. These vector sets typically will not
increase fault.coverage and can not be substituted for fault
graded vector sets.
The ultimate goal for testing all /883 products is data sheet
complianc;:y, thoroughness"and quality of testing. By taking
this 'approach to test set generatiori, Harris is capable of
supplying high performance semiconductors of the highest
quality to the marketplace.

Non-Standard Product Offerings
Harris understandil the need for customer generated
SoUrce Control Drawings with non-:standard parameter
and/or screening requirements. A Customer Engineering
Departmllnt is responsible for efficiently expediting your
SCDs through a comprehensive review process. The
Customer Engineering Group compares your SCD to ,its
closest equivalent grade device type and works ciosely with
the Product Engineer, Manufacturing Engineer, Design
Engineer, or applicable individual to compare Harris'
screening ability against your ,non-stam;!ard requirement(s).
For product processed to non-standard requirements, a
unique part,number suffix is assign e\'!.
Harris shares theli1i1itary's objective to utilize standards
wherever possible. We recOmmend usihg our /883 data
sheet as the guideline for your SCD's. in instances where an
available military specification or Harris /883 datasheet Is
inappropriate, It is Harris' sincerest wish to work closely
with the buyer in establishing an acceptable procurement
document. For this reason, the customer is requesb3d to
contact the nearest 'Harris Sales Office or Represehiative
before finalizing the Source Control Drawing. Harris looks
forward to working with 'the customer prior to
implementation of the formal drawing so that both parties
may create a mutually acceptable procurement document

8-15

Ie Handling,Procedures
Harris, IC processes are designed to produce the most
rugged products on the market. However, no
semiconductor Is Imm1Jne fr.om'damage resulting from the
sudden application of many' thousands of volts of static
electricity. While the phenomenon of catastrophic failure of
devices containing MqS transl~tors or ~apacltors Is well
known, even bipolar circuits 9an be damaged by static
discharge, with alterEid electrical properties and diminished
reliability. None of ti,'ecommon IC interrial protection
networks operate quickly enough to positively prevent
damage.
'
It is suggested that all semiconductors be handled, tested,
and installed using standard "Mas hani:lling techniques" of
proper grounding of personnel ancf, equipment. Part$ and
subassemblies should not be in contact with untreated,
plastic bags or wrapping material. High impedance IC
inputs wjred to a P.C. connector should have Ii ,path to
ground on the card.
HANDLING RULES

Since the introduction 'of integrated circuits with MOS
structures and high quality junctions, a safe and effective
means of handling these devices has been of primary
importance. One method employed to protect gate' oxide
structures is to incorporate Input protection diodes directly
on the monolithic chip. However, there is no completely
foolproof system of chip input prot8¢ion I'; existence in the
indu$try. In addition, most compensation networks in linear
circuits are located at, high impedance nodes, where
protection networks would disturb normal circuit operation.
H static discharge occurs at sufficient magnitude (2kY or
more), some damage or degradation will usually occur. It
has been found that handling equipment l!nd personnel can
generate static potentials in exce$S of 10kV in a low
humidity environment. Thus,.. it becomes necessary for
additional measures to' be implemented to eliminate or
reduce static charge. It is evident, therefore, that proper
handling procedures or rules should be adopted.

---------,

Elimination or reduction
accomplished as follows:

of static

charge

can

be

• Use statlc-fnle work stations. Static-dissipative mats on
work benches and floor, connected to common point
ground through a 1MO resistor, help eliminate static
build-up and discharge. Do not use metallic surfaces.
• Grounp all handling equipment.
• Ground all handling personnel with a conductive bracelet
through 1MO to ground (the 1MO resistor will prevent
electroshock Injury to personnel). Transient product
personnel should wear grounding heel Straps whEin
conductive floorif\g is present
• Smocks and clothing of certain insulating materials
(notably nylon) should not be worn In areas where
devices are handled. These materials, highly dielectric In
nature, will hold, or ,aid In the generation of a static
charge. Where they cannot be eliminated" ,natural
materials, such as cotton should be used to minimize
charge generation capacity. Conductive smocks are also
available as an alternative.
• Control relative humidity to as high a level as practical.
50% is generally considered sufficient. (Operations
should cease If R.H. falls below 25%).
• Ionized air blowers reduce charge build-up in areas
where grounding is not possible or practical.
• Devices should be ,in conductive static-shielded
containers during all phases of transport. Leads may be
shorted by tubular metallic carriers, conductive foam, or
.foil.
• In automated handling equipment, the belts, chutes, or
other surfaces should be of conducting non-metal
n:taterial. If this is not possible, Ionized air blowers or
ionizing bars may be a good alternative.

8-16

ESO Handling Procedures
Har.ris has developed a static control program that enables
employees to detect problems generated by. static
electricity whether on site, In transit, or in the field.
Controlling the requirements, methods, materials, and
training for static protection of our products is ongoing and
updated with new developments in electrostatic prevention.
Harris has responded with controls and procedures as part
of dally operations to be followed in all areas.
The challenge is to insure all electrostatic control
procedures are followed throughout the system - from
manufacturing through end' use. Unprotected integrated
circuits can be destroyed or functionally altered by merely
passing them through the electrostatic field of something as
simple as Styrofoam'" or human contact
Measures of Protection and Prevention
When handling static sensitive devices, three standard
procedures must be followed:
1. Prior to any handling of static-sensitive components, the
individual must be properly grounded.
2. All static-sensitive components must be handled at
static safeguarded work stations.
3. Containers
and
packing
materials
that
are
static-protective must be used when transporting all
static-sensitive components.

Controlling electrically conductive Items can be
accomplished by bonding and grounding techniques. The
human body is considered a conductor of electricity and is
by far the greatest generator of static electricity. Personnel
handling ICs must use con- ductive wrist straps to ground
themselves. Simple body moves act like a variable
capacitor, and can create static charges. In addition,
conductive clothing is recommended for minimizing
electrostatic build up.
Static protective packaging prevents electric field from
influencing or damaging ICs. An effective static-protective
package exhibits three types of features:
1. Antistatic protection that prevents triboelectric or
frictional charging,
2. Dielectric protection that Insulates discharging, and
3. Shielding or Faraday cage protection that prevents
transient field penetration.
Harris uses only packaging that exhibits all three features.
Employees are required to adhere to tlie same
static-protective packaging techiques during handling and
shipment to assure device integrity is maintained.

Special handling equipment (static-safeguarded work
stations, conductive wrist straps, static-protected
packaging, ionized air blowers) should be used to reduce
damaging effects of electrostatic fields and charges.

Ionized air blowers aid in neutralizing charges on
nonconductors such as synthetic clothing, plastics, and
Styrofoam'" . The blowers are placed at the work,site and in
close proximity to the IC handling area, since
nonconduqors do not lose or drain charges using normal
.grounding techniques.

Static-safeguarded work station is an area that is free
from all damaging electricity, including people. To
accomplish this, static on conductors and nonconductors
must be controlled.

By using wrist straps, static-protected work stations and
static-protected containers, Harris product quality is
maintained throughout the product cycle.

CHAIR
WITH GND
(OPTIONAL)

oIlf:

.-. ...=

>.... cc
ccCfLU
a:

=. .

R

FIGURE 2. STATIC-SAFEGUARDED WOR!< STATION
NOTE 1. All electrical equipment on the conductivelable top must be hard grounded and isolated from the table lop.
2.: Earth g,ou'nd is not computer ground or RF ground or any other IImH8d ground;·

Styrofoam ~ is a trademark of Dow Chemical Corporation

8-17

Harris Semiconductor
-------------------------------------------------------------------------------------------------------------------------------

No. 52,

--------------------- - -_
- - ------- . - - ------------------- ---- - -- ----

Harris Digital

February 1989

ELECTROSTATIC DISCHARGE C.ONTROL
A GUIDE TO HANDLlN,G INTEGRATED CIRCUITS
This paper discusses methods and materials recommended
for protection of ICs against ESD damage or degradation
during manufacturing operations vulnerable to ESD exposure.Areas of concern include dice prep and handling, dice
and package inspection, packing, shipping, receiving,
testing, assembly and all operations where ICs are involved.
All integrated circuits are sensitive to' electrostatic discharge (ESD) to some degree. Since the introduction of
integrated, circuits with MOS structures and high quality
junctions, safe and effective. means of handling these devices have.been of primary importance.

If static discharge occurs at a sufficient magnitude, 2kV or
greater, some.damage or degradation will usually occur. It
has been found that handling eqUipment and personnel can
generate static potentials In excess of 10kVin a low humidity environment; thus it becomes necessary for additional
measures to be Implemented to eliminate or reduce static
charge. Avoiding any damage or degradation by ESD when
handling devices during the manufacturing flow Is therefore
essential.

ESD Protection and
Prevention Measures
One method employed to protect gate oxide structures is to
incorporate input protection diodes directly on the monolithic ch ip. However, there is no completely foolproof system of
chip Input protection in existence in the industry.
In areas where ICs are being handled, certain equipment
should be utilized to reduce the damaging effects of ESD.
Typically, equipment such as grounded workstations,
conductive'i.vriststraps, conductive floor mats, ionized air
blowers and co~ductlve packaging materials are included
in the IC handling environment. Any time an Individual intends to han'dle an IC, in any way, they must insure they
have been grQunded, to .eliminate"circuit~.amage.

In addition to. personnel grounding;'areas where work is being performed withlCs, should be equippedwith an ionized
air blower, Ionized air blowers force positive and negative
ions simultaneously over the work area so that· any
nonconductors that are near the work surface would ,have
their static charge neutralized before it would cause device
damage or degradation. .
Relative humidity in the work area should be maintained as
high as practical. When the work environment Is less than
40% RH, a static build-up condition can exist on
nonconductor!; allowing stored charges to remain near the
ICs causing possible static el~tricity discharge to ICa.
Integrated circuits that are being shipped or transported
require special handling and packaging materials to eliminate ESD damage. Dice or packaged devices should be in
conductive carriers during all phases of transport and handling. Leads of packaged' devices can be shorted by
tubular metalic carriers, conductive foam or foil.

Do's and Don'ts for.
Integrated Circuit Hail dling ,
Do's
Do keep paper; nonconductive plastic, plastic foams and
films or cardboard off the static controlled conductive
bench top. Placing devices,.Ioadedsticks or loaded burn-in
boards' on top of any of these materials effectively insulates
them from ground and defeats the purpose of the static controlled conductive surface.
Do keep hand creams and food away from static controlled
conductive work surfaces. If spilled on the bench top, these
'.' materials will contaminate and increase the resistivity of the
work area..
Do be especially carlilful when using soldering guns around
conductive work surfaces. Solder spills and heat from the
gun may melt' and damage the ,conductive mat.

Do check the grounded wrist strap connections daily. Make
Grounding personnel can, practically, be performed by two
certain they are snugly .fitted· before ~tarting!l{.ork with the
methods. First, grounded wrist straps which are usually
product.
made of a conductive material,such as Velostat or metal. A
resistor value of 1 megohm (1/2. watt); in series with the Do put on grounded wrist strap before touching; any destrap to ground completes a discharge path for ESD'when . vices, This drains off any static build-up from the operator..
the operator wears the strap in contact with the skin. Anoth- Do know the ESO caution symbols. "
er method Is to Insure direct phySical contact with a
Do remove devices or loaded sticks from. shielding bags
grounded, conductive work surface.
only when grounded vIa wriststrap at grounded work staThis consists of a conductive surface like VEllostat, covering tion. This also applies when .loading or removing devices
the work area. The surface is connected to a 1 megohm from the antistatic sticks or the loading on or removing from
the burn-in boards.
(1/2 watt) resistor In series with ground.
Copyright @ HarriS Corporation 1989

8-18

Tech Brief 52
Do wear grounded wrist straps in direct contact with the
bare skin - never over clothing.

driver circuits when not grounded. This also applies to
burn-in programming cards containing ICs.

Do use the same ESD control with empty burn-in boards as
with loaded boards if boards contain permanently mounted
ICs as part of driver circuits.

Don't unload stick on a metal bench top allowing rapid discharge of charged devices.

Do insure electrical test equipment and solder irons at an
ESD control station are grounded and only uninsulated metal hand tools be used. Ordinary plastic solder suckers and
other plastic assembly aids shall not be used.
Do use ionizing air blowers in static controlled areas when
the use of plastiC (nonconductive) materials cannot be
avoided.
Don'ts
Don't allow anyone not grounded to touch devices, loaded
sticks or loaded burn-in boards. To be grounded they must
be standing on a conductive floor mat with conductive heel
straps attached to footwear or must wear a grounded wrist
strap.
Don't touch the devices by the pins or leads unless
grounded since most ESD damage is done at these points.
Don't handle devices or loaded sticks during transport from
work station to work station unless protected by shielding
bags. These items must never be directly handled by anyone not grounded.
Don't use freon or chlorinated cleaners at a grounded work
area.
Don't wax grounded static controlled conductive floor and
bench top mats. This would allow build-up of an insulating
layer and thus defeating the purpose of a conductive work
surface.
Don't touch devices or loaded sticks or loaded burn-in
boards with clothing or textiles even though grounded wrist
strap is worn. This does not apply if conductive coats are
worn.
Don't allow personnel to be attached to hard ground. There
must always be 1 megohm series resistance (1/2 watt
between the person and the ground).
Don't touch edge connectors of loaded burn-in boards or
empty burn-in boards containing permanently mounted

Don't touch leads. Handle devices by their package even
though grounded.
Don't allow plastic "snow or peanut" polystyrene foam or
other high dielectric materials to come in contact with devices or loaded sticks or loaded burn-in boards.
Don't allow rubber/plastic floor mats in front of static controlled work benches.
Don't solvent-clean devices when loaded in antistatic sticks
since this will remove antistatic inner coating from sticks.
Don't use antistatic sticks for more than one throughput
process. Used sticks should not be reused unless recoated.

Recommended Maintenance
Procedures
Daily:
Perform visual inspection of ground wires and terminals
on floor mats, bench tops, and grounding receptacles to
ensure that proper electrical connections via 1 megohm
resistor (1/2 watt) exist.
Clean bench top mats with a soft cloth or paper towel
dampened with a mild solution-of detergent and water.
Weekly:
Damp mop conductive floor mats to remove any accumulated dirt layer which causes high resistivity.
Annually:
Replace nuclear elements for ionized air blowers.
Review ESD protection procedures and equipment for updating and adequacy.

Static Controlled Work Station
The figure below shows an example of·a work bench properly equipped to control electro-static discharge. Note that
the wrist strap Is connected to a 1 megohm resistor. This
resistor can be omitted in the setup. if the wrist strap has a
1 megohm assembled on the cable attached.
R

I

WRIST STRAP GROUND
LEAD IS ATTACHED TO
CONDUCTIVE BENCH TOP

...

.r->. CONDUCTIVE WRIST
STRAP

CONDUCTIVE BENCH TOP _

1/////////

ESD WARNING SYMBOlS '

R

L....r-....----~...,_J

r1 CONDUCTIVE FLOOR MAT

R
R = 1 MEGOHM

8-19

~~

=
c ....
....

a:

I

GROUND, I.e. COLD WATER
PIPE OR EQUIVALENT

~~
-cC _ca
....
cC

i

,,"

PACKAGING AND ORDERING INFORMATION
PAGE
PACKAGING AVAILABILITY... . ... ........... .. ......... .. . ... ... .. . .... ... ... ...... ..... .. ... ..

9-2

PACKAGE OUTLINES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-3

ORDERING INFORMATION .....................................................................

9-9

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z

c::I

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c::IZ

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sse

INDEX PIN

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9

10

11

L

L

.080
.120

.003 MIN
NOTE: All Dimensions Are Min ,Dimensions Are In Inches.
Max

T4

145 PIN GRID ARRAY (PGA)
1.560
1.590

SEATING PLANE
.120

14O

--------1

1B1~0 ------~

1.400

1.560
1.590

sse

.tJQlU;

.003 MIN

& INCREASE MAXIMUM LIMIT BY .003"' WHEN SOLDER DIP
OR TIN PLATE LEAD FINISH APPLIES.
2. ACTUAL STANDOFF' CONFIGURATION MAY VARY, STANDOFFS
SHOULD BE LOCATED ON THE PIN MATRIX DIAGONALS.
3. THERE MUST BE AN Al CORNER IDENTiFIER ON BOTH
TO? AND BOTTOM SURFACES. 10 TYPE IS OPTIONAL
AND MAY CONSIST OF NOTCHES. METALLIZED MARKINGS
OR OTHER FEATURES.

NOTE: All Dimensions Are Min . Dimensions Are In Inches.
Max

9-7

Package 0 utlines
Z1

-'---"-------'------'--~

CERAMIC QUAD FLATPACK

I 810
-,-

1,850

L..Ul"!

• 105

.320_
.360

1.167

MAX

,

.050

Bse

1

J

t

.012

MIN

~
1.1
1.1

L

'''--(

MIN

t-'

.070 _
.090

'



,SPEED

$,CREENING

-45;-55

G

C

-55

G

M

-55, -65, -75

J

C

-35,-45

G

C

-35,-45

G

M

-45,-60

J

C

-15, -25, -33

G

'c

-15, -25, -33

G

M

-15,-25

J

C

-20, -25, -30

G

C

,-20, -25 ..,,30

G

M

-20,-25

J

C

-20, -25, -30

G

C

-20, -25, -30

G

M

-20,-25

1883

a

M

-20,-25

1883

P

C

-33, -40,-SO

S

C

-33, -40, -50

1883

1883

1883

1883

"

HSP45102

HSP45106

HSP45116

HSP45240

HSP489Q1,

.",

J

C

-25, -33, -40

G

C

-25, -33, -40

G

M

-25,-33

G

C

-15, -25, -33

G

M

-15,":25

J

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-33, -40, -50

G

C

-33, -40, -50

G

M

-33,-40

J

C

-20',-30

G

C

-20,~30'

J

C

-20,':32

G

C

-20,-32'

G

M

-20,-27

J

C

-25,-30

TEMPERATURE

PACKAGE

SPEED

HSP9520/21

C

P,S

ISP9520/21

C

PX,SX

HSP48908

HSP9501

DEVICE TYPE

9-10

188'3

1883

1883

1883

SCREENING

[O)~-------t
SALES OFFICE INFORMATION
A complete and current listing of all Harris Sales, Representative and Distributor locations worldwide is available.
Please order the "Harris Sales Listing" from the Literature Center (see page i).

HARRIS HEADQUARTER LOCATIONS BY COUNTRY:
U.S. HEADQUARTERS
Harris Semiconductor
1301 Woody Burke Road
Melbourne, Florida 32902
TEL: (407) 724-3000

EUROPEAN HEADQUARTERS
Harris Semiconductor
Mercure Centre
Rue de la Fusse 100
1130 Brussels, Belgium
TEL: (32) 2-246-21.11

SOUTH ASIA
Harris Semiconductor H.K. Ltd
13/F Fourseas Building
208-212 Nathan Road
Tslmshatsui, Kowloon
Hong Kong
TEL: (852) 3-723-6339

NORTH ASIA
Harris K.K.
Shinjuku NS Bldg. Box 6153
2-4-1 Nishi-Shinjuku
Shinjuku-Ku, Tokyo 163 Japan
TEL: (81) 03-3345-8911

HARRIS TECHNICAL ASSISTANCE AVAILABILITY:
UNITED STATES
CALIFORNIA

Costa Mesa •.............. 714-433-0600
San Jose .................. 408-922-0977
Woodland Hills ............ 818-992-0686

FLORIDA

Melbourne ................ 407-724-3576

GEORGIA

Norcross .................. 404-246-4660

ILLINOIS

Itasca .................... 708-250-0070

MASSACHUSETTS

Burlington .•.............. 617-221-1850

NEW JERSEY

Mt. Laurel ................. 609-727-1909
Rahway ................... 201-381-4210

TEXAS

Dallas .................... 214-733-0800

FRANCE

Paris ..................... 33-1-346-54090

GERMANY

Munich ................... 49-8-963-8130

INTERNATIONAL

ITALY

Milano .................... 39-2-262-22127

JAPAN

Tokyo .................... 81-03-3345-8911

SWEDEN

Stockholm ................ 46-8-623-5220

U.K.

Camberley ................ 44-2-766-86886

.",
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10-1

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Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
Create Date                     : 2017:07:22 20:30:35-08:00
Modify Date                     : 2017:07:23 13:28:16-07:00
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Metadata Date                   : 2017:07:23 13:28:16-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:00403075-91fd-8a48-9c53-4665cc5ba400
Instance ID                     : uuid:33096035-fe2d-a64b-9771-c8d61a36ae67
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 323

EXIF Metadata provided by EXIF.tools

1991_Harris_Digital_Signal_Processing 1991 Harris Digital Signal Processing

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