1991_Hitachi_SRAM_Data_Book 1991 Hitachi SRAM Data Book

User Manual: 1991_Hitachi_SRAM_Data_Book

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SRAM
DATA BOOK

~HITACHI®

M12T014

When using this document, keep the following in mind:
I.

This document may, wholly or partialIy, be subject to change without
notice.

2.

AlI rights are reserved: No one is permitted to reproduce or duplicate, in
any form, the whole or part of this document without Hitachi's permission.

3.

Hitachi wiII not be held responsible for any damage to the user that may
result from accidents or any other reasons during operation of the user's
unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intelIectual property claims
or other problems that may result from applications based on the examples
described herein.
5.

No license is granted by implication or otherwise under any patents or
other rights of any third party or Hitachi, Ltd.

6.

MEDICAL APPLICATIONS: Hitachi's products are not authorized for
use in MEDICAL APPLICATIONS without the written consent of the
appropriate officer of Hitachi's sales company. Such use includes, but is
not limited to, use in life support systems. Buyers of Hitachi's products are
requested to notify the relevant Hitachi sales offices when planning to use
the products in MEDICAL APPLICATIONS.

March 1991

©Copyright 1991, Hitachi America, Ltd.

Printed in U.S.A.

.HITACHI®
SRAM DATA BOOK INDEX
Section

Introduction

MOS Static RAM

Cache Static RAM and
Fast SRAM Modules

MOS Pseudo Static RAM

ECLRAM

FIFO Memory
HITAcm SALES OFFICES

SECTION 6, PAGE 486

SRAM DATA BOOK
TABLE OF CONTENTS
Section 1
Page
Introduction ....................................................................................................................................................iii
QUICK REFERENCE GUiDE ...........................................................................................................................v
PACKAGE INFORMATION .............................................................................................................................1
RELIASILITY OF HITACHII.C. MEMORIES .................................................................................................12
QUALITY ASSURANCE OF I.C. MEMORIES ...............................................................................................20
OUTLINE OF TESTING METHOD ................................................................................................................26
APPLICATION ...............................................................................................................................................27
Section 2
MOS Static RAM
16K
4K x 4
HM6268 SERIES
16K x 1
HM6267 SERIES
64K

8K x 8
16K x 4

High Speed CMOS Static RAM ...................................36
High Speed CMOS Static RAM ...................................43

HM6264A SERIES
HM6288 SERIES
HM6788 SERIES
HM6788H SERIES
HM6788HA SERIES
HM6289 SERIES
HM6789 SERIES
HM6789H SERIES
HM6789HA SERIES
HM6287 SERIES
HM6287H SERIES
HM6787 SERIES
HM6787H SERIES
HM6787HA SERIES

Medium Speed CMOS Static RAM .............................50
High Speed CMOS Static RAM ...................................59
High Speed Hi-SiCMOS Static RAM ..........................67
High Speed Hi-SiCMOS Static RAM ..........................71
High Speed Hi-SiCMOS Static RAM .=.................... 75
High Speed CMOS Static RAM (with OE) .. = : ........... 80
High Speed Hi-SiCMOS Static RAM (with 00 ........... 91
High Speed Hi-SiCMOS Static RAM (with 00 ........... 98
High Speed Hi-SiCMOS Static RAM (with OE) ......... 105
High Speed CMOS Static RAM .................................113
High Speed CMOS Static RAM ................................. 120
High Speed Hi-SiCMOS Static RAM ........................ 129
High Speed Hi-SiCMOS Static RAM ........................ 134
High Speed Hi-SiCMOS Static RAM ........................ 139

HM62256 SERIES
HM62256A SERIES
HM62832H SERIES
HM62832UH SERIES
HM67832SH SERIES
HM6208H SERIES
HM6708 SERIES
HM6708A SERIES
HM6708SH SERIES
HM6709 SERIES
HM6709A SERIES
HM6709SH SERIES
HM6207H SERIES
HM6707 SERIES
HM6707A SERIES

Medium Speed CMOS Static RAM ........................... 144
Medium Speed CMOS Static RAM ........................... 152
High Speed CMOS Static RAM ................................. 160
High Speed CMOS Static RAM ................................. 166
High Speed Hi-SiCMOS Static RAM ........................ 173
High Speed CMOS Static RAM ................................. 181
High Speed Hi-SiCMOS Static RAM ........................ 187
High Speed Hi-SiCMOS Static RAM ........................ 188
High Speed Hi-SiCMOS Static RAM .........= .......... 193
High Speed Hi-SiCMOS Static RAM (with 00 ......... 201
High Speed Hi-SiCMOS Static RAM (with 00 ......... 202
High Speed Hi-SiCMOS Static RAM (with OE) ......... 209
High Speed CMOS Static RAM .................................217
High Speed Hi-SiCMOS Static RAM ........................223
High Speed Hi-SiCMOS Static RAM ........................224

288K 32K x 9

HM62932 SERIES
HM62D932 SERIES

High Speed CMOS Static RAM .................................229
High Speed CMOS Static RAM .................................237

1M

HM628128/HM6281281 SERIES
HM66204 SERIES
HM624256A SERIES
HM624257 SERIES
HM621100A SERIES

Medium Speed CMOS Static RAM ...........................245
High Speed CMOS Static RAM Module ................... 256
High Speed CMOS Static RAM ................................ 257
High Speed CMOS Static RAM ................................ 267
High Speed CMOS Static RAM .................................275

HM628512 SERIES
HM66205 SERIES
HM624100 SERIES
HM621400 SERIES

High Speed
High Speed
High Speed
High Speed

64K x 1

256K 32K x 8

64K x 4

256K x 1

128Kx8
256Kx4
1Mx 1

4M

512K x 8
1M x 4
4M x 1

•

CMOS Static
CMOS Static
CMOS Static
CMOS Static

RAM .................................281
RAM Module ...................288
RAM .................................295
RAM .................................302

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

Section 3
Cache Static RAM and Fast SRAM Modules
120K 8Kx16
HM62A168 SERIES

2-way Set Associative or ...........................................311
Direct Mapped Static Cache RAM

128K 8Kx18

HM62A188 SERIES

2-way Set Associative or ...........................................311
Direct Mapped Static Cache RAM

288K 32Kx9

HM62A932 SERIES

Synchronous Data Cache RAM ................................323

328K 8Kx20

HM62A2016 SERIES

R3000 MPU Cache RAM (two banks) .......................333

1M

128Kx8 HM62A8128 SERIES

Synchronous Cache SRAM .......................................346

1.2M

128Kx9 HM62A9128 SERIES

Synchronous Cache SRAM .......................................346

256K 16Kx 16 HS66S1616A SERIES

High Speed Static RAM Module ...............................355

2M

High Speed Static RAM Module ...............................365

256Kx8 HS66A2568A SERIES

Section 4
MOS Pseudo Static RAM
256K 32Kx8
HM65256S SERIES

High Speed Pseudo Static RAM ...............................375

1M

128Kx8 HM658128 SERIES
HM658128A SERIES

High Speed Pseudo Static RAM ...............................382
High Speed Pseudo Static RAM ...............................383

4M

512Kx8

HM658512 SERIES

High Speed Pseudo Static RAM ...............................395

HM10494 SERIES
HM10490 SERIES

Hi-SiCMOS 10K ECl Static RAM .............................404
Hi-SiCMOS 10K ECl Static RAM .............................408

256K 256Kx 1 HM10500 SERIES

Hi-SiCMOS 10K ECl Static RAM .............................412

64K

HM100494 SERIES

Hi-SiCMOS 100K ECl Static RAM ......................... ..417

HM100504 SERIES
HM100500 SERIES

Hi-SiCMOS 100K ECl Static RAM ...........................421
Hi-SiCMOS 100K ECl Static RAM .......................... .425

1M

256Kx4 HM100514 SERIES
1Mx1
HM100510 SERIES

Hi-SiCMOS 100K ECl Static RAM ......................... .430
Hi-SiCMOS 100K ECl Static RAM .......................... .434

64K

16Kx4
64Kx1

HM101494 SERIES
HM101490 SERIES

Hi-SiCMOS 101 K ECl Static RAM .......................... .438
Hi-SiCMOS 101 K ECl Static RAM .......................... .442

HM101504 SERIES
HM101500 SERIES

Hi-SiCMOS 101 K ECl Static RAM ......................... .446
Hi-SiCMOS 101 K ECl Static RAM ......................... .450

256Kx4 HM101514 SERIES
1Mx1
HM101510 SERIES

Hi-SiCMOS 101 K ECl Static RAM ......................... .454
Hi-SiCMOS 101 K ECl Static RAM ......................... .458

Section 5
ECLRAM
16Kx4
64K
64Kx1

16Kx4

256K 64Kx4
256Kx1

256K 64Kx4
256Kx1
1M

Section 6
FIFO Memory
18K 2Kx9

HM63921 SERIES

Parallel In-Out FIFO Memory .....................................465

36K

HM63941 SERIES

Parallel In-Out FIFO Memory .................................... .477

4Kx9

HITACHI SALES OFFiCES ........................................................................................................................486

.HITACHI
ii

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

Section 1
Introduction
• Quick Reference
to Hitachi I.e. Memories
• Package Information
• Reliability of
Hitachi I.e. Memories
• Quality Assurance of
I.e. Memory
• Outline of 1esting Method
• Application

.HITACHI®

QUICK REFERENCE GUIDE TO HITACHI MEMORIES
• MOSRAM
Mode

Total

Type No.

Process

Time

Supply

(word x bit)

(ns)

(ns)

Voltage

Power
Dissipation

(VI

(W)

Max

Max

HM6268-25

25

25

HM6268-35

35

35

45

45

HM6268L-25

25

25

HM6268L-35

35

35

HM6268L-45

45

45

35
45

35
45

55

55

HM6267L-35

35

35

HM6267L-45

45

45

HM6267L-55

55

55

HM6264A-10

100

100

HM6264A-12

120

120

HM6264A-15

150

150

HM6264AL-10

100

100

120

120

150

150

HM6264AL-10L

100

100

HM6264AL-12L

120

120

HM6264AL-15L

150

150

HM6288-25

25

25

HM6268-45

16Kb

Access
Time

Cycle

OrganizatIOn

HM6267-35

4K x 4

CMOS

HM6267-45
HM6267-55

16K x 1

HM6264AL-12
HM6264AL-15

Static

8K x 8
CMOS

HM6288-35

35

35

HM6288L-25

25

25

HM6288L-35

35

35

HM6788-25

16K x4

25

25

30

30

15

15

HM6788H-20

20

20

HM6788HA-12

12

12

HM6788-30
HM6788H-15

Bi-CMOS

HM6788HA-15

15

15

HM6788HA-20

20

20

HM6289-25

25

25

35
25

35
25

HM6289L-35

35

35

HM6789-25

25

25

16K x 4

30

30

(withOEI)

15

15

20

20

12

12

HM6289-35
HM6289L-25
64Kb

CMOS

HM6789-30
HM6789H-15
HM6789H-20

Bi-CMOS

HM6789HA-12
HM6789HA-15

15

15

HM6789HA-20

20

20

HM6287-45

45

45

HM6287-55

55

55

HM6287-70

70

70

HM6287L-45

45

45

HM6287L-55

55
70

55
70

HM6287L-70

CMOS

HM6287H-25

25

25

HM6287H-35

35

35

25

25

HM6287HL-35

35

35

HM6787-25

25

25

HM6787-30

30

30

HM6287HL-25

64K x 1

HM6787H-15
HM6787H-20

Bi-CMOS

HM6787HA- 12

15

15

20

20

12

12

HM6787HA- 15

15

15

HM6787HA-20

20

20

•

Package

Pin No

5~/0.25

20

0.1m/0.2

5p/0.2

OP

2.

22

2'
(SOJI

10m/0.23
22

0.3

2.

0.28
0.3

0.1m/0.3
22

10p/0.3

22

2.
(SOJ)

0.18

22

0.21

22

2.

0.3

36
36
36
36
36
43
43
43
43
43
43
50
50
50
50
50
50
50
50
50
59
59
59
59

•
•
•
•

(SOJ)

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

67
67
71
71
75
75
75

•

80

•
•

0.1m/0.3

10p/0.3

TFP

36

• •
• •
• •
• •
• •
• •
• •
•
•
•
•
•
•
•
•
•
•
•
•

0.1m/0.3

CP

•
•
•

0.28

0.23

FP

•
•
•
•
•
•
•
•
•
•
•

• •

10p/15m

+5

oG

•
• •

0.1m/15m

0.1m/0.3

Page

Only

O.1m/O.25

10p/15m

Maintenance

•
•
•
•

•
•
•
•

•
•
•
•
•
•
•
•
•

80
80
80

•
•
•

•

91
91
98
98
105
105
105

•

•
•
•
•
•

113
113
113
113
113
113
120
120
120
120

•
•
•
•

129
129
134
134
139
139
139

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

v

QUICK REFERENCE GUIDE - - - - - - - - - - - - - - - - - - - - - • MOSRAM
Mode

Total

Type No.

Process

Organization
(word x bit)

HM62256-8

Cycle

Time

Supp~

(ns)
Max

(ns)

Voltage

Max

(V)

85
100

HM62256-10
HM62256-12

120
150

HM62256-15
HM62226L-8

85

HM62256L-l0

100

HM62256L-12
HM62256L-15
HM62256L-l0SL
HM62256L-12SL

120
150
100

HM62256L-15SL

32Kx8
CMOS

HM62256A-8
HM62256A-l0
HM62256A-12
HM62256A-15
HM62226AL-8
HM62256AL-10
HM62256AL-12

HM62256AL-15SL
HM62832H-25
HM62832H-35
HM62832UH-15
256Kb HM62832UH-20
HM62832UHL-15
HM62832UHL-20
HM67832SH-l0
HM67832SH-12

Bi-CMOS

HM6208H-25
HM6208H-35
HM6208HL-25
HM6208HL-35
HM6708A-15

CMOS

HM6708A-20
HM6708A-25

HM6709A-15

64Kx4
Bi-CMOS

HM6709A-20
HM6709A-25
HM6709SH-l0

150

85
100
120
150

85
100

85
100

85
100
120

10jli40m

10jli40m

120
150

0.2m/40m

10jli40m

85
100
120

100
120
150

150

25
35
15

25
35
15

0.lm/0.3

20

20

15j1iO.55

15
20
10

15
20
10

12
25

12
25

35
25

35
25

0.lm/0.3

35
15

35
15
20

30jliO.3

15jliQ.4
+5

12
15

10
12
15

20
25

20
25

10
12

10
12

35
15
20

35
15
20
25

20jliO.3

20
15

20
15

20
15

HM62D932-20
HM62D932L-15

20
15

20
15

HM62D932L-20

20

20

CMOS

32Kx9

•
•
•

0.4

2'

•
•
•
•
•

•
•

0.45

15

20
15

HM62932L-15
288Kb HM62932L-20
HM62D932-15

•
•

28

0.lm/0.3

HM62932-15
HM62932-20

•

•

0.45

25

25
15

•
•
•
•
•
•
•
•
•
•
•
•

0.4

35
25

Bi-CMOS

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•

25

HM6707A-25

FP

•
•
•
•
•
•
•
•
•

•
•

0.45

35
25
256K xl

DP

0.4

25

Maintenance

CP

TFP

144
144
144
144
144
144
144
144
144
144
144
152
152
152
152

•

•
•
•
•

3'

•

152

•
•

•
•
•

•
•
•
•

_HITACHI
vi

152
152
152
152

•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

152
152
152

•

•

15j1iO.35

Page

Only

•
•
•
•
•
•
••

30jliO.3

HM6207H-35
HM6207HL-25

CMOS

28

150

HM6709SH-12
HM6207H-25

HM6207HL-35
HM6707A-15
HM6707A-20

Package

0.2m/40m

85
100
120
150

150

20
25
10

HM6708SH-l0
HM6708SH-12

Power
Dissipation
(W)
Pin No OG

150

100
120

85

HM62256AL-10SL
HM62256AL-12SL

85
100
120

120

120
150

HM62256AL-15
HM62256AL-8SL

Slalic

Access
Time

Hitachi America, Ltd . • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

160
160
166
166
166
166
173
173
181
181
181
181
188
188
188
193
193
202
202
202
209
209
217
217
217
217
224
224
224
229
229
229
229
237
237
237
237

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ QUICK REFERENCE GUIDE

• MOSRAM
Mode

Total

Type No.

Process

Organization

(word x bit)

1Mb

Static

4Mb

Static
RAM
Module

4Mb

HM628128-7
HM628128-8
HM628128-10
HM628128-12
HM628128L-7
HM628128L-8
HM628128L-l0
HM628128L-12
HM624256A-20
HM624256A-25
HM624256A-35
HM624256AL-20
HM624256AL-25
HM624256AL-35
HM624257-35
HM624257-45
HM624257L-35
HM624257L-45
HM621100A-20
HM621100A-25
HM621100A-35
HM621100AL-20
HM621100AL-25
HM621100AL-35
HM628512-5
HM628512-7
HM628512-8
HM628512-10
HM628512L-5
HM628512L-7
HM628512L-8
HM628512L-l0
HM628512L-5L
HM628512L-7L
HM628512L-8L
HM628512L-10L
HM6241 00-25
HM6241 00-30
HM624100-35
HM6241 00-45
HM624100L-30
HM624100L-35
HM624100L-45
HM621400-25
HM621400-30
HM621400-35
HM621400-45
HM621400L-30
HM621400L-35
HM621400L-45
HM66205L-85
HM66205L-l0
HM66205L-12

128K x 8

256K x 4

lMxl

CMOS

512K x 8

lMx4

4M x 1

512K x 8

Access
Time
(ns)
Max
70
85
100
120
70
85
100
120
20
25
35
20
25
35
35
45
35
45
20
25
35
20
25
35
55
70
85
100
55
70
85
100
55
70
85
100
25
30
35
45
30
35
45
25
30
35
45
30
35
45
85
100
120

Cycle
Time
(ns)
Max
70
85
100
120
70
85
100
120
20
25
35
20
25
35
35
45
35
45
20
25
35
20
25
35
55
70
85
100
55
70
85
100
55
70
85
100
25
30
35
45
30
35
45
25
30
35
45
30
35
45
85
100
120

Supply
Voltage
(V)

Power
Dissipation
(W)
Pin No DG

0.lm/?5m
32

10~/75m

28

Package

DP

FP

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•

•
•
•
•
•

32

•

•
•
•

•

+5

10j.i/75m

0.05/0.75

32

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
•
•
•
•

•
•
•
•
•

0.05/0.75

0.5m/0.?

40j.i/80m

CP

•
•

0.5m/0.?

32

Page

Only

0.lm/0.35

28

Maintenance

•
•
•

•
•

TFP

•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•

245
245
245
245
245
245
245
245
257
257
257
257
257
257
267
267
267
267
275
275
275
275
275
2?5
281
281
281
281
281
281
281
281
281
281
281
281
295
295
295
295
295
295
295
302
302
302
302
302
302
302
288
288
288

_HITACHI
Hitachi America, Ltd_ • Hitachi Plaza • 2000 Sierra Point Pkwy_ • Brisbane, CA 94005-1819 • (415) 589-8300

vii

QUICK REFERENCE GUIDE - - - - - - - - - - - - - - - - - - - - - • Cache Static RAM and Fast SRAM Modules
Mode

Total

120Kb

128Kb

Cache
Static
RAMs

268Kb

328Kb

1Mb
1.2Mb
Fast
SRAM
Module

256Kb
2Mb

Type No.

HM62A168-25
HM62A 168-30
HM62A 168-35
HM62A168B-25
HM62A168B-35
HM62A188-25
HM62A168-30
HM62A188-35
HM62A168B-25
HM62A1888-35
HM62A932-14
HM62A932-19
HM62A932-24
HM62A932-34
HM62A2016-17
HM62A2016-20
HM62A2016-25
HM62A2016-30
HM62A8128-20
HM62A9128-20
HB66B1616A-25
HB66B1616A-35
HB66A2568A-25
HB66A2568A-35

Process

CMOS

Access
Time
(word x bit)
(ns)
Max
25
8Kx 16
30
(2 way)
35
25
35
25
8Kx 18
30
(2 way)
35
25
35
14
32Kx9
19
24
34
17
8Kx20
20
(2 way)
25
30
128K x 8
30
128K x 9
30
16K x 16
25
(module)
35
256Kx8
25
(module)
35

Cycle
Time
(ns)
Max
25
30
35
25
35
25
30
35
25
35
20
25
30
40
17
20
25
30
20
20
25
35
25
35

Access
Time
(ns)
Max
100
120
150
200
100
120
150
200
80
100
120
80
100
120
80
100
120
80
100
120
80
100
120
80
100
120

Cycle
Time
(ns)
Max
160
190
235
310
160
190
235
310
130
160
190
130
160
190
130
160
190
130
160
190
130
160
190
130
160
190

Organization

Supply
Voltage

(VI

Power
Dissipation
(W)

Maintenance

Package

Page

Only
Pin No

1.1 (max)

52

TBD

44

1.1 (max)

52

25m/0.75

32

0.4m/1.2

36

0.8m/2.4

60

DG

DP

FP

CP

TFP

•
•
•
•
•
•
•
•
•
•
•
•
•
•

311
311
311
311
311
311
311
311
311
311
323
323
323
323
333
333
333
333
346
346
355
355
365
365

•
•

+5

•
•
•
•

• MOS Pseudo Static RAM
Mode

Pseudo
Stetic

Totel

Type No.

HM65256B-10
HM65256B-12
HM65256B-15
256Kb HM65256B-20
HM65256BL-10
HM65256BL-12
HM65256BL-15
HM65256BL-20
HM658128A-8
HM658128A-l0
HM658128A-12
HM658128AL-8
1Mb HM658128AL-10
HM658128AL-12
HM658128AL-8L
HM658128AL-10L
HM658128AL-12L
HM658512-8
HM658512-10
HM656512-12
HM658512L-8
4Mb HM658512L-l0
HM658512L-12
HM658512L-8L
HM658512L-l0L
HM658512L-12L

Process

Organization
(word x bit)

32Kx8

CMOS

128Kx8

512K x 8

Supply
Voltage

(VI

Power
Dissipation
(W)

2m/0.175

+5

Package
Pin No

28

32

DG

DP

FP

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•

•

•

CP

TFP

•
•
•
•
•

•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•

•
•
•
•

•
•
•
•
• •
• •
• •

_HITACHI
viii

Page

Only

0.35m/0.25

0.2m10.25

Maintenance

Hitachi America, Ltd . • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

375
375
375
375
375
375
375
375
383
383
383
383
383
383
383
383
383
395
395
395
395
395
395
395
395
395

- - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE
• ECLRAM
Mode

ECl
10K

ECl
lOOK

ECl
101K

Total

Type No.

HM10494-10
HM10494-12
64Kb HM10490-10
HM10490-12
256Kb HM10500-15
HM100494-10
64Kb HM100494-12
HMI 00504-1 0
256Kb HM100504-12
HM100500-18
HM100514-15
1Mb HM100510-15
HM101494-10
HM101494-12
64Kb HM101490-10
HM101490-12
HM101504-10
256Kb HM101504-12
HM101500-15
HM101514-15
1Mb HM101510-15

Process Organization
(word x bit)

16K x4
64Kx 1
256K xl
16K x4
Bi-CMOS

64Kx 4
256K xl
256K x 4
lMx 1
16Kx 4
64K x 1
64K x4
256K x 1
256K x 4
lMx 1

Access
Time
(ns)
Max
10
12
10
12
15
10
12
10
12
18
15
15
10
12
10
12
10
12
15
15
15

Cycle
Time Supply
(ns) Voltage
Max
(V)
10
12
10
-5.2
12
15
10
12
10
-4.5
12
18
15
15
10
12
10
12
-5.2
10
12
15
15
15

Access
Time
(ns)
Max
20
25
35
20
25
35

Cycle
Time
(ns)
Max
20
25
35
20
25
35

Power
Dissipation
(W)
Pin No OG
0.8

2.

0_57
0.52

2'

0.65

2.

0.5
0.5
0.8
0.7

2'
32

0.75

2.

0.57

22

0.5
0_5
0.8
0.7

2.

22

2.

Package

Maintenance

FG

CG

• •
• •

404
404
408
408
412
417
417
421
421
425
430
434
438
438
442
442
446
446
450
454
458

•
•

•
• •
• •
•
•
•
•
•
•
• •
• •
•
•

2.
32

2•

Page

Only

•
•

• •
•
•

• FIFO Memory
Mode

Total

18Kb
FIFO
36Kb

Type No.

HM63921-20
HM63921-25
HM63921-35
HM63941-20
HM63941-25
HM63941-35

Process Organization
(word x bit)

2Kx 9
CMOS
4Kx9

Supply
Voltage
(V)

+5

Power
Dissipation
(W)
Pin No OG

0.6
(max)

2.

Maintenance Page

Package

Only
OP

FP

CP

TFP

•
•
•
•
•

•

465
465
465
477
477
477

The package codes apply to the material as follows:
DP Dual In-line Package-Plastic
DG Dual In-line Package-Ceramic
FP
Flat Package/SOP (Dual = 2-sided; Quad_ = 4-sided)-Plastic
FG
Flat Package-Ceramic
TFP Thin SOP-Plastic
CG Chip Carrier (4-sided)-Ceramic
CP J-Iead Package (SOJ =2-sided; PLCC =4-sided)-Plastic

$

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

ix

Package Information

.HITACHI@

• PACKAGE INFORMATION
• Dual·ln·line Plastic

Unit: mm (inch) Scale 111

• Dp·22N

• Dp·20N

2S.40mlll.
(1.000m ... )

20

27.0I( 1.066)
27.90m••.( 1.091.....)
12
II

3~

o

~~9

(0.03S)

.u.I~..,..,

(O.osl)

•

~

Ii ~

~elii

Z.54±O.25
(0.100 t 0.010)

O.48f 0.1
(0.019 + 0.004)

e

• Dp·22NB

~!l
•.•

~I

7.62
(0.300)

o·. . . 'S·

: . Ni

O.4'±O.1

2.S4 ± 0.25

(0.019±O.OCM)

(0.100±0.010)

.e

• DP·24NC

27.9Om••. (I.IIH.....)

~d
=u:.:.
flU
.. I a

(O.OIS±O.OCM)

• DP·28

(0.100:t0.010)

• DP·28C

_HITACHI
2

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - PACKAGE INFORMATION
Unit: mm (inch) Scale 111

• Oual·in·line Plastic

~

·Op·28N

I
~::::::::~[J.~
-H- ..
~

'7.3!.~:;~!...)

.»U.-

• Op·28NA

7.62(0.

I

1.:10(0.0")

D,

~I"
O.•'tO.1

uetO,I5

(O.OllU.OIM)

(O.IOO±O.OIO)

• OP·32

I

s

41.9(1.650)
42.5m••. (1.613m••. )

"32

11

~

I

~

f:~~~~~~~::~J~!
.~ ~

(O.cM7)

M;-

(0.600)

_~~li~

Jl~O'I-~;S
(O.IOO±O.OIO)

(O.OIHO.OOC):1;~
N-

O'-IS"

S

Applicable ICs
DP-20N

HM6268P Series, HM6268LP Series, HM6267P Series, HM6267LP Series

DP-22N

HM6287P Series, HM6287LP Series

DP-22NB

HM6288P Series, HM6288LP Series, HM6788P Series, HM6788HP Series, HM6788HAP Series,
HM6287HP Series, HM6287HLP Series, HM6787P Series, HM6787HP Series, HM6787HAP Series,
HM6787HAJP Series

DP-24NC

HM6789P Series, HM6789HP Series, HM6789HAP Series, HM6208HP Series, HM6208HLP Series,
HM6708AP Series, HM6207HP Series, HM6207HLP Series, HM6707AP Series

DP-28

HM6264AP Series, HM6264ALP Series, HM6264ALP-L Series, HM62256P Series, HM62256LP Series,
HM62256LP-L Series, HM65256BP Series, HM65256BLP Series, HM62256AP Series, HM62256ALP Series,
HM62256ALP-SL Series

DP-28C

HM624256P Series, HM624256LP Series, HM624256AP Series, HM624256ALP Series, HM621100AP Series,
HM621100ALP Series

DP-28N

HM6264ASP Series, HM6264ALSP Series, HM6264ALSP-L Series, HM6709AP Series

DP-28NA

HM62832HP Series, HM62832UHP Series, HM67832SHP Series, HM63921P Series, HM63941P Series,
HM62256ASP Series, HM62256ALSP Series, HM62256ALSP-SL Series

DP-32

HM658128ALP Series, HM658128ALP-L Series, HM658128ADP Series, HM658128DP Series,
HM658128LP Series, HM658512LP Series, HM658512P Series, HM628128P Series, HM628128LP Series,
HM628128LP-SL Series, HM628512P Series, HM628512LP Series, HM628512LP-L Series

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

3

PACKAGE INFORMATION - - - - - - - - - - - - - - - - - - - - - - • CERDIP

Unit:

• DG·22N

~

mm (inch) Scale 1/1

• DG·24V

...............•...

,

.......,.'.:.:...

......•••.,....

.

7.62(0.300)

~~~
o.tu 0.1
(0.019 to.OM)

e

S

2.SH 0.2S
(0.1 00 ± 0.0 I0)

• DG·28N
~

71(1367)

II
~l

O.Ali'O.1
(0.019%0.004)

2.S4±O.2S
s
(O.IOO±o.oIO)

Applicable ICs
DG-22N

HMI0490 Series, HMIOl490 Series

DG-24V

HMI0500 Series, HMlOO500 Series

DG-28N

HMI0494 Series, HMl00494 Series, HM10I494 Series

_HITACHI
4

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - Package Information
• Flat Package

Unit: mm (inch) Scale 1%

• FP-28D

28

I,

18.3(0.72)
18.75max(0.75max)

'I

15

~J~
....
coe
x.

....

14

1

x E
E'"
",0

0.895
(0.035)

'0

N~

1
'j;j
o
o

~

~

N

~

'"N

0

• FG-28DB

+0.33

N~

""

.,

00
N

~

•
8

.~

00

00
II

.'"
a

~

0>

0

'"

~

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - Package Information
• Flat Package

Unit: mm (inch) Scale 11,4

• FG-32D

o.

Reference polnt

Applicable ICs
FP-28D

HM6264AFP Series, HM6264ALFP Series, HM6264ALFP-L Series

FP-28DA

HM6264AFP Series, HM6264ALFP Series, HM6264ALFP-L Series, HM62256FP-T Series,
HM62256LFP-T Series, HM62256LFP-SLT Series, HM65256BFP-T Series, HM65256BLFP-T Series,
HM62256AFP-T Series, HM62256ALFP-T Series, HM62256ALFP-SLT Series

FP-32D

HM628128FP Series, HM628128LFP Series, HM658128DFP Series, HM658128LFP Series,
HM658512LFP Series, HM658512DFP Series, HM65256BFP-T Series, HM65256BLFP-T Series,
HM62256AFP-T Series, HM62256ALFP-T Series, HM62256ALFP-SLT Series, HM628128LFP-SL Series,
HM628512FP Series, HM628512LFP Series, HM628512LFP-SL Series, HM658128ALFP Series,
HM658128ALFP-L Series, HM658128ADFP Series

FG-24A

HMlOO500F Series, HMI01500F Series

FG-28D

HMI0494F Series, HM100494F Series, HMI01494F Series

TFP-32DA

HM628128T Series, HM628128LT Series, HM62256A Series, HM62256AL Series

FG-28DA

HMI01510F Series, HMlOO510F Series

FPG-28DB

HM lOO504F Series

FG-32D

HM lOO514F Series, HM 101514F Series

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

9

PACKAGE INFORMATION - - - - - - - - - - - - - - - - - - - - - - Unit: mm (inch) Scale 1'h

• TSOP Packages
8.0(0.315)

• TFP·32D

• TFP·32DA

32

8.0(0.315)

O.20tO.10
(0.008tO.004)

~ft;;wow
e
Applicable ICs
TFP-32D

HM628128LT Series, HM628128LR Series

TFP-32DA

HM62256ALT Series, HM62256ALT-SL Series, HM658128ALT-L Series, HM658128ALT Series,
HM658128ADT Series
Unit: mm (inch) Scale 1 'h

• Leadless Chip Carrier
• CG·28B

Applicable ICs
15.35maK
(O.604maK)

....
KXD
~i
~~r

CG-28B

HMI00500CG Series,
HM 101500CG Series

EE

~~

m!!!U

I nnnn

nnnn I

Unit: mm (inch) Scale 1'h

• Flat Package (J·bend Leads)
• CP·24D

• CP·28D

15.63(0.615)
16.00ma"10.63ma,,)_
24
13

~8 ~~

cic:idc:S

D

... ~

t;! ~ ~+I

~

Jl 0.7410.029)

12

s

~

00.100.004

_HITACHI
10

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - PACKAGE INFORMATION
Unit: mm (inch) Scale 1'h

• Flat Package (J·bend Leads)
• Cp·28DN

• CP·32D

18.1710.715)

,

~T8:5"4riiii.IO;ijOinOxlJ

C::::::::Ju~
Jl
1

O,7410,02~!

• CP·32DN

~d8~'lli~~}~Kr
"

1

14

20.71
21.08max
32

17

0.43':::~ ~llfi
0.

• CP·44

1
~·1

28

40
0

~

~_~_~;ac;==~~

0.10

•

• CP·52

20.0"01'

C:~··I

!I

~!

~

~

21

.l.-.-.a-~

]J

,'Il
IOrs))

Applicable ICs
CP-24D

CP-28D
CP-28DN
CP-32D
CP-32DN
CP-44
CP-52

HM6288JP Series, HM6288UP Sseries, HM6289JP Series, HM6289UP Series, HM6789JP Series,
HM6789HJP Series, HM6789HAJP Series, HM6287HJP Series, HM6287HUP Series,
HM6787HJP Series, HM6287HAJP Series, HM6208HJP Series, HM6208HUP Series,
HM6708AJP Series, HM6207HJP Series, HM6207HUP Series, HM6207AJP Series
HM624256JP Series, HM624256UP Series, HM624256AJP Series, HM624256AUP Series,
HM621100AJP Series, HM621100AUP Series
HM62832HJP Series, HM62832UHJP Series, HM62832SHJP Series, HM6709AJP Series
HM624257JP Series, HM624257UP Series, HMI01504JP Series, HM62A8128JP Series, HM62A9128JP Series
HM624100JP Series, HM624100JLP Series, HM621400JP Series, HM621400JLP Series
HM62932JP Series, HM62932UP Series, HM62D932JP Series, HM62D932UP Series
HM67A932CP Series
HM62A168CP Series, HM62A188CP Series, HM62A2016CP Series

_HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

11

• RELIABILITY OF HITACHI IC MEMORIES
RELIABILITY CHARACTERISTICS FOR
SEMICONDUCTOR DEVICES
Hitachi semiconductor devices are designed,
manufactured and inspected so as to achieve a
high level of reliability. Accordingly, system reliability can be improved by combining highly reliable components along with proper environmental conditions. It is important to examine
semiconductor device characteristics in light of
their reli.ability.
• Semiconductor devices are essentially structure sensitive as seen in surface phenomenon.
Fabricating the device requires precise control
of a large number of process steps.
• Device reliability is partly governed by electrode materials and package materials, as well
as by the coordination of these materials with
the device materials.
• Devices employ thin-film and fine-processing
techniques for metallization and bonding. Fine
materials and thin film surfaces sometimes exhibit physically different characteristics from
the bulks.
• Semiconductor device technology advances
drastically: Many new devices have been developed using new processes over a short period of time. Thus, conventional device reliability data cannot be used in some cases.
• Semiconductor devices are characterized by
volume production. Therefore, variations
should be an important consideration.
• Initial and accidental failures are only considered to be semiconductor device failures
based on the fact that semiconductor devices
are essentially operable semipermanently.
However, wear failures caused by worn materials and migration should also be reviewed
when electrode and package materials are not
suited for particular environmental conditions.
• Component reliability may depend on device
mounting, conditions for use, and environment. Device reliability is affected by such factors as voltage, electric field strength, current
density, temperature, humidity, gas, dust,
mechanical stress, vibration, mechanical
shock, and radiation magnetic field strength.

•
12

WeII'OUtt.ilunreaion.
: Riliq failure rates (m> 1)

il------ ____ ~P!i:r~~~~~.~
""

Random failure relion

_____ :

: Constant failure rates (m =1)
Usefullonpvity

-

1m: WeibuU distribution
1 form parameter

,,

i

Time (.)

Figure 1 Typical failure rate curve

Device reliability is generally represented by the
failure rate. 'Failure' means that a device loses its
function, including intermittent degradation as
well as complete destruction.
Generally, the failure rate of electric components
and equipment is represented by the bathtub
curve shown in Figure 1. For semiconductor devices, the configuration parameter of the Wei bull
distribution is smaller than 1, which means an
initial failure type. Such devices ensure a long
lifetime unless extreme environmental stress is
applied. Therefore, initial and accidental failures
can become a problem for semiconductor devices. Semiconductor device reliability can be
physically represented as well as statistically.
Both aspects of failures have been thoroughly analyzed to establish a high level of reliability.

SEMICONDUCTOR FAILURE TYPES AND
THEIR MECHANISM
Semiconductor device failures are categorized as
disconnection, short-circuit, deterioration and
miscellaneous failures. These are summarized in
Table 1. Typical failure mechanisms are:
Surface Deterioration
The pn junction has a charge density of 10141020/cm 3. If charges exceeding the above density are accumulated on the pn junction surface,
particularly adjacent to a depletion layer, electric
characteristics of the junction tend to be easily
varied. Although the surface of such devices as
planar transistors is generally covered with a
Si02 film and is in an inactive state, the possibility
of deterioration caused by surface channels still
exists. Surface deterioration depends heavily on
applied temperature and voltage and is often handled by the reaction model.

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - Reliability of Hitachi IC Memories
Table 1 Failure Modes, Mechanisms and Related Causes

Failure modes

Failure mechanisms

Failure related causes

Withstanding voltage
reduced, Short, Leak
current increased, hFE
degraded, Threshold
voltage variation, Noise

Pin hole, Crack, Uneven
thickness, Contamination,
Surface inversion, Hot
carrier injected

Passivation

Surface oxide film,
Insulating film between
wires

Open, Short, Resistance
increased

Flaw, Void, Mechanical
damage,
Break due to uneven
surface, Non-ohmic
contact, Insufficient
adhesion strength,
Improver thickness,
Electromigration,
Corrosion

Metallization

Interconnection,
Contact, Through hole

Open, Short
Resistance increased

Bonding runout,
Compounds between
metals, Bonding position
mismatch, Bonding
damaged

Connection

Wire bonding,
Ball bonding

Open, Short

Disconnection,
Sagging, Short

Wire lead

Internal connection

Withstanding voltage
reduced, Short

Crystal defect,
Crystallized impurity,
Photo resist mismatching

Diffusion,
Junction

Junction diffusion,
Isolation

Open, Short, Unstable
operation, Thermal
resistance increased

Peeling, chip, Crack

Die bonding

Connection between die
and package

Short, Leak current
Increased, Open,
Corrosion disconnection,
Soldering failure

Integrity,
moisture ingress,
Impurity gas, High
temperature, Surface
contamination, Lead rust,
Lead bend, break

Package sealing

Packaging, Hermetic
Seal, Lead plating,
Hermetic package &
plastic package, Filler
gas

Short, Leak current
increased

Dirt, Conducting foreign
matter, Organic carbide

Foreign matter

Foreign matter in
package

Short, Open, Fusing

Electron destroyed

Input/output pin

Electrostatistics,
Excessive Voltage,
Surge

Soft error

Electron hole generated

Disturbance

ex particle

Leak current increased

Surface inversion

High electric field

@HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

13

Reliability of Hitachi

Ie Memories - - - - - - - - - - - - - - - - - - - - - - - - -

One example is surface deterioration caused by
hot carriers. Hot carriers are generated when
such devices as MaS dynamic RAMs are operated at a voltage near the minimum breakdown
voltage (BVDS) by raising fnternal voltage and
when a strong electric field is established near the
MaS device's drain resulting from reduced device geometry from 2/-tm to 0.8/-tm. Generated hot
carriers may affect surface boundary characteristics on a part of the gate oxide film, resulting in
degradation of threshold voltage (VTH) and
counter conductance (gm). Hitachi devices employ improved design and process techniques to
prevent these problems. However, as processes
becomes finer, surface deterioration may possibly become a serious problem.
Electrode-Related Failures

Electrode-related failures have become increasingly important as multi-layer wiring has become
more complicated. Noticeable failures include
electromigration and AI wiring corrosion in plastic
sealed packages.
ELECTROMIGRATION
This is a phenomenon in which metal atoms are
moved by a large current of about 106 A/cm 2 supplied to the metal. When ionized atoms collide
with the current of scattering electrons, an 'electron wind' is produced. This wind moves the metal
atoms in the opposite direction from the current
flow, which generates voids at a negative electrode, and hillock and whiskers at an opposite
one. The generated voids increase wiring resistance and cause excessive currents to flow in
some areas, leading to disconnection. The generated whiskers may cause shortcircuits in multimetal line.

Figure 2 Categorized AI corrosion mode

to an initial failure associated with manufacturing.
It is also verified that this type of failure can be
generated when the adhesion surface between
an element and resin is separated or when foreign
materials are attached to the element with human
saliva. Under a bias-applied, high-temperature,
high-humidity condition, c.orrosion is generated in
higher potential areas while in lower potential
areas, grain corrosion occurs. Once this failure
occurs in part of a device, the device can become
worn out in a relatively short time. This failure
proves to depend on the hydroscopic volume resistivity of sealed resin. The AI line corrosion
mechanism described above is summarized in
Figure 3.

MULTI-METAL LINE RELATED FAILURES
Major failures associated with multi-metal line include increased leak currents, shortcircuits
caused by a failed dielectric interlayer, and increased contact metal resistance and disconnection between metal wirings.
AL LINE CORROSION AND DISCONNECTION
When plastic encapsulated devices are subjected to high-temperatures, high-humidity or a
bias-applied condition, AI electrodes in devices
can cause corrosion or disconnection (Figure 2).
Under high-temperature and high-humidity, corrosion is randomly generated over the element
surface. However, after an extended period of
time, the corrosion has not significantly increased. Accordingly, this failure is possibly due

Figure 3 Plastic package cross section and AI corrosion
mechanism

~HITACHI
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- - - - - - - - - - - - - - - - - - - - - - - - Reliability of Hitachi
Bonding Related Failures
DEGRADATION CAUSED BY INTERMETALLIC
FORMATION
Bonding strength degradation and contact resistance increase are caused by compounds formed
in connections between Au wire and AI film. This
is the most serious problem in terms of reliability.
The compounds are formed rapidly during bonding and are increased through thermal treatment.
Consequently, Hitachi products are subjected to
a lower-temperature, shorter-period bonding
whenever possible.
WIRE CREEP
Wire creep is wire neck destruction in an Au ball
along an intergranular system occurring when a
plastic sealed device is subjected to a long-term
thermal cycling test. This failure results from increased crystal grains due to heat application
when forming a ball at the top of an Au wire, or
from an impurity introducing to the intergranular
system. Bonding under usual conditions with no
loop configuration failures does not cause this
failure unless a severe long-term thermal cycling
test is applied. Accordingly, wire creep is not a
problem in actual usage.
CHIP CRACK
With the increase in chip size associated with the
increased number of incorporated functions,
more problems can occur during assembly, such
as chip cracks during bonding. Bonding methods
include Au-silicon eutectic, soldering and Agpaste. Soldering and Ag-paste exhibit few chip
crack problems. For Au-silicon eutectic, in contrast, large stress is applied to a pellet due to its
strength and high temperature resistance for attachment, which may result in critical chip defects. Today, the chip destruction limit can be determined by finite-element analysis and by
distortion measurement using a fine accuracy
gauge. Ideally, Au-silicon eutectic should be
evenly applied over the entire surface. However,
this is difficult due to the existence of a silicon
oxide film on the silicon back surface. Therefore,
specifications for Au-silicon eutectic have been
established based on stress analysis and thermal
cycling test results.
REDUCED MAXIMUM POWER DISSIPATIONS
Heat fatigue due to thermal expansion coefficient
mismatch among different materials deteriorates
thermal resistance, resulting in decreased maximum power dissipations.

•

Ie Memories

Sealing Related Failures
Hermetically sealed packages, including metal,
glass, ceramic, and all other types, have the possibility of the following failures.
1. AI line corrosion on the chip surface due to
slight moisture and reaction between the different ionized materials.
2. Intermittent moving foreign metals short.
3. AI line corrosion due to extraneous H20
caused by hermetic failure.
Moving foreign matter, even if it is a non-active
solid, can be charged up within a cavity during
movement, thereby inducing parastic effects and
metal shorts. The foreign matter detection
method is specified by MIL-STD-883C, PIND
(Particle Impact Noise Detection) Test. The PIND
test consists of filtering a particle impact waveform (ultrasonic waveform), detecting it with a microphone and then amplifying it.
Disturbance
ELECTROSTATIC DISCHARGE
DESTRUCTION
Destruction caused by electrostastic discharge is
a problem common to semiconductor devices. A
recent report introduced three modes of this failure; the human body model, charged device
model and field induced model.
The human body is easily charged. A person just
walking across a carpet can be charged up to
15000 V. This voltage is high enough to destroy a
device. An equivalent circuit of the human body
model is shown in Fig. 4. The human body's capacitance Cb and resistance Rb are 100 to 200 pF
and 1000 to 2000n, respectively. Assuming a
body is charged with 2000V, the dissipated energy is obtained as follows: With a time constant
of 10-7 sec, the dissipated energy is 2 KW, which
is enough to destroy a small area of a chip.

Human Body Capacity
Human Body Resistance
Rtl- Device Resistance
11< - Resistance Between Device Bod Ground
C/o -

RJo -

E-

'21 CbV'

a

0.2

X

10-1 J

Figure 4 Equivalent circuit of human body m"odel

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

15

Reliability of Hitachi

Ie Memories - - - - - - - - - - - - - - - - - - - - - - - -

In the charged device model, charges are accumulated in a device, not a human body, and discharged through contact resistance during a short
time. The equivalent circuit of this model is shown
in Fig. 5. Device size and device position relative to
GND are important parameters in this model since
the model depends on device capacity.
In the field induced model, a device is left under a
strong electric field or is affected by neighboring
high voltage material. Since the capacitor of device or lead of device acts like an antenna, the
following cases will possibly cause destruction:
1) a device is incorporated into a high electric field
such as a CRT, 2) a device is left under a highfrequency electric field and 3) a device is moved
with a container charged at high voltage, such as
a tube.

Much effort should be made in designing circuits
to prevent latch-up. Latch-up triggering input or
output currents start to flow under the following
conditions:
V outVCC or Vout< GND for input level
Therefore, circuits should be designed so that no
forward current flows through the input protection
diodes or output parasitic diodes.

Soft errors
When a particles are generated from uranium or
thorium in a package the silicon surface of an LSI
chip, electron-hole pairs are formed which act as
noise to data lines and other floating modes,
causing temporary soft errors. This phenomenon
is shown in Fig. 6. Only electrons from among the
electron-hole pairs are only collected to a memory
cell. As a result, the cell changes from a state of
1 to 0, which is a soft error.
Hitachi devices have been subjected to simulation and irradiation tests to prevent soft errors. In
some cases, organic material, PIQ, is applied to
the surface of the device.

Figure 5 Equivalent circuit 01 charging model

LATCH-UP
Latch-up is a problem unique to CMOS devices.
This problem is a thyristor phenomenon caused
by a parasitic PNP or NPN transistor formed in the
CMOS configuration. Latch-up can occur when:
1) an accidental surge voltage exceeds the maximum rating, 2) there is a power supply ripple, 3)
an unregulated power supply and noise is applied
or 4) a device is operated from two sources having
different set-up voltages. These cases can cause
input or output current to flow in the opposite direction from usual flow, which triggers parasitic
thyristors. This results in excessive current flowing between a power supply and ground. This
phenomenon continues until the power is turned
off or the flowing current reduced to a certain
level. Once latch-up occurs in an operating device, the device will be destroyed.

a

Figure 6 Solt error caused by a particles in dynamic memory

~HITACHI
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- - - - - - - - - - - - - - - - - - - - - - - - - Reliability of Hitachi IC Memories
FINE GEOMETRY RELATED PROBLEMS
In response to higher integration requirements for
memories and microcomputers, lSI geometry
has been reduced in the way of 3 pm ---> 2 I'm --->
1.3 I'm ---> 0.8 I'm.

The problems associated with finer geometry are
shown in Table 2.

Table 2 Finer geometry related problems
Item
5V single supply
voltage

Problems
• Breakdown voltage of gate oxide films
• Si02 defects

Horizontal dimension
reduction

•
•
•
•
•
•
•

Vertical & horizontal
dimension reduction

Countermeasure
Oxide film formation process
improved
• Cleaning
• Oettering
• Screening
Surface passivation film improved
• Metallization improved
• Design/layout improved
• Process improved

Soft errors by ex particles
Al reliability reduced
CMOS latch up
Mask alignment margin reduced
Hot carriers
Higher breakdown voltage not permitted
Electrostatic discharge resistance reduced

RELIABILITY TEST DATA ON
Hi-BiCMOS MEMORY
Hi-BiCMOS memory is newly designed based on
the latest fine machining technologies which features the low electric consumption/high integrity
of CMOS and the high speed/high drivability

Use of low voltage examined
• Configuration improved
• Protection circuits enhanced

of bipolar. These devices can attain the high
speed of ECl and the low electric consumption of
CMOS. Input and output level supports both ECl
and TTL. Reliability test data with the HM10049015 (64k-words x 1-bit) and the HM6788P-25 (16kwords x 4-bits) are listed in Tables 3 and 4.

Table 3 Results of Hi-BiCMOS Memory Reliability Tests
Test item

Test
conditon

HMlOO490-15 (Cerdip)
Total test Failures
time

Samples

High-

temperature
pulse
operation

Hightemp.
storage

T.=125"C
VEE =-4·5V

T.=200"C

380

330

C.H.
3.8x 105

3.3x lOS

0

0

HM6788P-25 (Plastic)

Failure
rate

Test item

High
temperature
pulse
I.g
opera2.4x 10-6
tion
Moisture
endurance
3.0x1O-o

Pressure

cooker

Test
condition

Samples

Test test
time

Failures

T.=125"C
Vcc =5.0V

420

C.H.
4.2x 105

1'\

85"C 85%RH
5V

210

2.1 x loS

121 "CIOO%RH

80

0.16x 105

Remarks

Failure

rate

Ilh

4.8 x 10-6

*1
foreign
matter

4.8xI0-6

0

6.3xI0- 5

0

Table 4 Results of Hi-BiCMOS Memory Environmental Tests
Test item

Test condition

HM 100490-15 (Cerdip)

HM6788P-25 (Plastic)

Samples

Failure

Samples

Failure

-55·C - -150·C 100 cyles

180

0

180

0

Solderinl!; heat

250·C 10 seconds

22

0

22

0

Thermal shock

O·C - 100·C 10 cycles

50

0

50

0

Mechanical shock

15000, 0.5ms Three times each
for X, Y and Z

22

0

-

-

Variable frequency

100-200Hz, 200 Three times each
for X, Y and Z

22

0

-

-

200000, 1 minute, each
for X, Y and Z

22

0

-

-

Temperature cycling

Constant acceleration

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

17

Reliability of Hitachi IC Memories - - - - - - - - - - - - - - - - - - - - - - - - RELIABILITY TEST DATA ON MOS MEMORIES
The reliability test data on the HM62256 (32k-word x 8-bit) and the HM628128 (128K-word x 8-bit) are

listed in Tables 5 and 6.
Table 5 Results of MOS Memory Reliability Tests
HM628128FP (SOP)

HM62256FP (SOP)
Test item

Test condition

Total
test time

0
0
1*1

2.02x 10*5

0

High-

125°C/5.5V

3088

temperature

125°CI7V

455

pulse operation

150°CI7V

103

3.11 x 106
4.55x 105
1.00 X 105

Moisture
endurance

85°C/85%
RH7V

680

6.80x 105

Pressure

121°C!100%
RH

320

6.40 X 104

cooker

Failure
rate*
(l/hr.)

SampIes

Failures

Failure
rate*
(l/hr.)

SampIes

Total
total time

Failures

8.88x 10*7

1038
951

0
1*1

80

1.04 X 106
5.33 x 105
1.60x 105

8.86x 10*7

2.02X 10*6

0

5.75 X 10*6

1.35 X 10*6

127

2.54x 105

0

3.62x 10*6

3.16x 10*5

90

2.70x 104

0

3.41 X 10*5

3.79XIO*6

Remarks

*1
Foreignx2
*2 Leak X I

1*2

'Confidence level 60%

Table 6 Results of MOS Memory Environmental Tests
Test item

HM62256FP (SOP)

Test condition

Failure

Samples

Failure

482

0

105

0
0

-55°C to 150°C 500 cycles

Temperature cycling

HM628128FP (SOP)

Samples

Soldering heat

260°C 10 seconds

22

0

22

Thermal shock

-65°C to 150°C 15 cycles

76

0

77

0

Mechanical shock

1500G. 0.5ms

-

-

Variable frequency

100 to 2000 Hz, 20G

-

-

-

-

-

-

Constant acceleration

6000G

Figure 7 Time change in access time for Hi-BiCMOS memory
Example
Device name

HM100490

Test condition

Ta=125°C, VEE=-4.5V
all bit scanning

Failure criteria

tAA=15ns

Failure mechanism

Surface degradation

Example of time change in access time for Hi-BI CMOS memory

Tell Coaditiol

20

Results:
Access time is stabilized.

2. ,.,.

V,,= -4.5V
Ta=25"C

~

~\trlJ('

\hrchlnl PUlt'rn

-;;;

~llnlmum

15

-5

J
10

~

5

T

I

0

I

500

I

1,000

If

2,000

Tunt> 'hrl

~HITACHI
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Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - Reliability of Hitachi IC Memories
Figure 8 Time change in Vcc min and tAA for Hi-BiCMOS memory
Example

Example of time change in Vee min and tAA for Hi-Bi CMOS memory

Device name

HM6788P-25

Test condition

Ta=125°C, VCC=-5.0V
all bit scanning

Failure criteria

Vcc=4.5V, tAA=25ns

Failure mechanism

Surface degradation

5

~

4

~

.5 3

. 2 Test
Condition
>
V _
E

2

Maximum
cc - 5V
Average
ra=25'C
Minimum
0 Marching Pattern

Results:
Both ofVCC (min) and tAA are stabilized.

1

0

·30

!

2.000

500
1.000
Time (hr)

Test Condition
Same as above

25

~

c

~ 20

15
0

500

1.000
Time (hr)

2.000

Figure 9 Time change in Voo min and tRAC for MOS memory
Example

Example of time change in V DO min and tRAC for MOS

Device name

HM511000P

Test condition

Ta=125°C, VCC=-7V
all bit scanning

5

Failure criteria

Voo=4.5V,
LWOO=l.OV

4

Failure mechanism

Surface degradation

E3 ~
••
oJ 2

Results:
Access time (tAA) is stabilized and is within the
failure criteria.

Test Condition
Marching pattern
T.=2S'C

1

~

~

N=200pcs

f

Maximum
Aver ge
• a
Minimum

0
0

500

~

1,000

.

2,000

Time (hr)

110

Test Condition
Same as above

100

]110

Note: Test accuracy is O.2V, 2 ns.

JIIO
10

t

I.

0

500

I I

110

1.000

2,000

Time (hr)

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

19

• QUALITY ASSURANCE OF IC MEMORY
1. VIEWS ON QUALITY AND
RELIABI LITY
Hitachi basic views on Quality are to meet individual
users' purpose and their reQu ired quality level and
also to maintain the satisfied level for general ap·
plication. Hitachi has made efforts to assure the
standardized reliability of our IC memories in actual
usage. To meet users' requests and to cover expand·
ing application, Hitachi performs the followings;
(1) Establish the reliability in design at the stage of
new product development.
(2) Establish the quality at all steps in manufactur·
ing process.
(3) Intensify the inspection and the assurance of reo
liability of products.
(4) Improve the product quality based on market·
ing data.
Furthermore, to get higher quality and reliability,
we cooperate with our research laboratories.
With the views and methods mentioned above,
Hitachi makes the best efforts to meet the users' reo
quirements.

2. RELIABILITY DESIGN OF
SEMICONDUCTOR DEVICES
2.1 Reliability Target
Establishment of reliability target is important in
manufacturing and marketing as well as function
and price. It is not practical to determine the reo
liability target based on the failure rate under single
common test condition. So, the reliability target is
determined based on many factors such as each
characteristics of equipment, reliability target of
system, derating applied in design, operating condi·
tion and maintenance.

2.2 Reliability Design
Timely study and execution are essential to achieve
the reliability based on reliability targets. The main
items are the design standardization, device design
including process and structural design, design
review and reliability test.
(1) Design Standardization
Design standardization needs establishing design
rules and standardizing parts, material, and
process. When design rules are established on
circuit, cell, and layout design, critical items
about Quality and reliability should be ex·
amined. Therefore, in using standardized

process or material, even newly developed prod·
ucts would have high reliability, with the excep·
tion of special requirement on function.
(2) Device Design
It is important for device design to consider
total balance of process design, structure
design, circuit and layout design. Especially in
case of applying new process or new material,
we study the technology prior to development
of the device in detail.
(31 Reliability Test by Test Site
Test site is sometimes called Test Pattern. It is
useful method for evaluating reliability of
designing and processing !es with complicated
functions.
1. Purposes of Test Site are as foilows;
• Making clear about fundamental failure mode;
• Analysis of relation between failure mode and
manufacturing process condition.
• Analysis of failure mechanism.
• Establishment of ac point in manufacturing.
2. Effects of evaluation by Test Site are as follows;
• Common fundamental failure mode and
failure mechanism in devices can be evaluated.
• Factors dominating failure mode can be
picked up, and compared with the process
having been experienced in field.
• Able to analyze relation between failure
causes and manufacturing factors.
• Easy to ru n tests.
2.3 Design Review
Design review is a method to confirm systematically
whether or not design satisfies the performance
required including by users, follows the specified
ways, and whether or not the technical items
accumulated in test data and application data are
effectively applied.
In addition, from the standpoint of competition
with other products, the major purpose of design
review is to insure quality and reliability of the
product. In Hitachi, design review is performed
in designing new products and also in changing
products.
The followings are the items to consider at design
review.
(1) Descri be the products based on specified design
documents.
(2) Considering the documents from the standpoint
of each participant, plan and execute the sub·
program such as calculation, experiments and

~HITACHI
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- - - - - - - - - - - - - - - - - - - - - - - - - - - Q u a l i t y Assurance of

Ie

Memory

investigation if unclear matter is found.
(3) Determine the contents and methods of reliabil·
ity test based on design document and drawing.

3. QUALITY ASSURANCE SYSTEM OF
SEMICONDUCTOR DEVICES

(4) Check process ability of manufacturing line to

3.1 Activity of Quality Assurance

achieve design goal.
(5) Arrange the preparation for production.
(6) Plan and execute the sub-programs of design
changes proposed by individual specialists, for
tests, experiments and calculation to confirm the
design change.
(7) Refer to the past failure experiences with
similar devices, confirm the prevention against
them, and plan and execute the test program
for confirmation of them.
In Hitachi, these study and decision at design review
are made using the individual check lists according
to its objects.

The following items are the general views of overall
quality assurance in Hitachi;
(1) Problems is solved in each process so that even
the potential failure factors will be removed at
final stage of production.
(2) Feedback of information is made to insure
satisfied level of process ability.
As the result, we assure the reliability.

Step

Contents

I

Tarlf>1
Spet:I'lclIlIJn

t

11l·"Kn

II

TriAl

PrudUClIOn

Malt'rlal ..... Parts
Appro'l. I

11-

Characteristics of Material and

Paris
Appearance
LJimenslOn
Heat Resistance

Mec:han lea I
Electrical
O'hers

II

Purpose

Design Review

Characteristics Approval

11-

Electrical

Characleris! ies
Funct ton
V",ltagt'
Current

Temperature

Confirmation of
Characteristics and
Reliability of Materials
and Parts

Confirmation of Target
Spec. Mainly about
Electrical
Characteristics

Others

Appearance. Dimens Ion

II

Quality Approval (I)

II

Quality Approval (2)

IMus

,I

Product ion

Ir-HFigure'

Reliability Test
Life Test
Thermal Stress
Moisture Resistance
Mechanical Stress
Othe rs

Reliability Test

Confirmation of Quality
and Reliability in Design

Confirmation of Quality

Process Check same as

and Rei iability in Mass

Quality Approval (1)

Production

Flow Chert of Qualification

$HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

21

Quality Assurance of

Ie

Memory - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ __

3.2 Qualification
To assure the quality and reliability, the qualification tests are done at each stage of trial production
and mass production based on the reliability design
described in section 2.
The followings are the views on qualification in
Hitachi:
(1) From the standpoint of customers, qualify the
products objectively by a th ird party.
(2) Consider the failure experiences and data from

customers.
(3) Qualify every change in design and work.
(4) Qualify intensively on parts and materials and
process.
(5) Considering the process ability and factor of
manufacturing fluctuation, establish the control
points in mass production.
Considering the views mentioned above, qualifica·
tion shown in Fig. 1 is done.

Quality Control

Process

Method

Inspection on Material and

---

Parts for Semiconductor

Lot Sampling,
Confirmation of
Qua I ity Leve I

Devices
Manufacturing Equipment,

-

Environment, Sub-material,

-

-

Confirmation of
Quality Level

Worker Control

Inner Process

Lot Sampling,

Quality Control

Confirmation of
Quality Level

100% Inspection on

Testing,

Appearance and Electrical

Inspection

Characteristics
Sampling Inspection on
Lot Sampling

Appearance and Electrical
Characteristics

Confirmation of
Reliability Test

Quality Level, Lot
Sampling

r-----------,

I
I
I
I

Quality Information,
Claim
Field Experience
General Quality
Information

I
I

Feedback of
Information

IL.... _ _ _ _ _ _ _ _ _ _ ..J
Figura 2 Flow Chart of Quality Control in Manufacturing Process

.HITACHI
22

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Quality Assurance of IC Memory
3.3 Quality and Reliability Control in Mass Produc·
tion
To assure quality in mass production, quality is
controlled functionally by each department, mainly
by manufacturing department and quality assurance
department. The total function flow is shown in
Fig. 2.
3.3.1 Quality Control on Parts and Materials
With the tendency toward higher performance and
higher reliability of devices, quality control of parts
and materials becomes more important. The items
such as crystal, lead frame, fine wire for wire bond·
ing, package and materials required in manufacturing process like mask pattern and chemicals, are all
subject to inspection and control.
Besides qualification of parts and materials stated in
3.2, quality control of parts and materials is defined
in incoming inspection. Incoming inspection is performed based on its purchase specification, drawing
and mainly sampling test based on MIL-STO-1050.
The other activities for quality assurance are as
follows.
•

Table 1. Quality Control Check Points of Parts
and Material (example)
Material.
Parts

Important
Control Items
Appearance
Djm~nsion

Wafer

Mask

Sheet ResiUance
Defect Density
Crystal A x is
Appearance
Dimension

Fine

Gradation
Appearance

Point for Check

Damage and Contamma·
tion on Surface

Flatness
Resistance
Defect Numher'\

c-::---

--

~---

Defect Numbers. ScraH:h
Dimension Level

Resistoration

Wire for
Wire

Bonding

-

Dimension
Purity
Elongation Ratio
Appearanct"
DimensIOn

Uniformity of Gradation

C'ontamination, Scratl'h,
Bend. TWISt

Purity Le-vel
Mechanical Str_ength
Contamination, Scratch
Dimension Level

Processing
Frame

Accuracy

Plating

Bonda hil it y. Solderability
Heat Resistance
Character is' ics__
r--=----------Appearance
Contamination, Scrat("h
DimenSlun
DimenSIOn Level
Leak Resistance
Airtightness
Plating
Bond.bility. Solderability
Mountang
Heal Resistance
Character 1st ics
Electrical
Characteristin
Mechanical
Mechanical Strength

Mounting

Ceramic
Pac kage

Str~_

CompOSitIOn

Plastic

1-;----

Charadfrlsflo, of
Plastic Material

Electril:al
CharacteristiCS
Thermal
(,haracterl~tics

Molding
Performance
Mounting
Characlerislll:s

Molding Performance

(1) Technology Meeting with Vendors
(2) Approval and Guidance of Vendors
(3) Analysis and tests of physical chemistry.
The typical check points of parts and materials are
shown in Table 1.
3.3.2 Inner Process Quality Control
To control inner process quality is very significant
for quality assurance of devices. The quality
control of products in every stage of production is
explained below. Fig. 3 shows inner process quality
control.
(1) Quality Control of Products in Every Stage of
Production
Potential failure factors of devices should be removed in manufacturing process. Therefore, check
points are set up in each process so as not to move
the products with failure factors to the next
process. Especially, for high reliability devices,
manufacturing lines are rigidly selected in order to
control the quality in process. Additionally we per·
form rigid check per process or per lot, 100%
inspection in proper processes so as to remove
failure factors caused by manufacturing fluctuation,
and screenings depending on high temperature aging
or temperature cycling. Contents of controlling
quality under processing are as follows:
• Control of conditions of equipment and workers
and sampling test of uncompleted produsts.
• Proposal and execution of working improvement.
• Education of workers
• Maintenance and improvement of yield
• Picking up of quality problems and execution of
countermeasures toward them.
• Communication of quality information.
(2) Quality Control of Manufacturing Facilities and
Measuring Equipment
Manufacturing facilities have been developed with
the need of higher devices in performance and the
automated production. It is also important to de·
termine quality and reliability.
In Hitachi, automated manufacturing is promoted
to avoid manufacturing fluctuation, and the operation of high performance equipment is controlled to
function properly.
As for maintenance inspection for quality control,
daily and periodically inspections are performed
based on specification on every check point.
As for adjustment and maintenance of measuring
equ ipment, the past data and specifications are
clearly checked to keep and improve quality.

Mounting Characlerisllcs

~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

23

Quality Assurance of

Ie

Memory-------------------------

(3) Quality Control of Manufacturing Circumstances and Sub-material.
Quality and reliability of devices are affected
especially by manufacturing process. Therefore, we thoroughly control the manufacturing
circumstances such as temperature, humidity,
dust, and the sub-materials like gas or pure
water used in manufacturing process.

Dust control is essential to realize higher integration and higher reliability of devices. To
maintain and improve the clearness of manufacturing site, we take care buildings, facilities, airconditioning system, materials, clothes and
works. Moreover, we periodically check on
floating dust in the air, fallen dust or dirtiness
on floor.

Control Point

Proc...

Purpo•• of Control

Purchase 01 Material
Characteristics. Appearance

Waler

Assurance of Resistance

Oxidation

Surface Oxidation
Inspection on Surface
Oxidation
Photo Res ist

Scratch, Removal of Crystal
Delect Wafer

Appearance. Thickness 01
Oxide Film

Pinhole, Sc ratch

Dimension. Appearance

Dimension Level
Check 01 Photo Resist
Dillusion Status

Photo
Resist

Inspection on Photo Rosist
o PQC Leve I Check
Dillus ion

Dillusion Depth. Sheet
Resistance
Gate Width
Characteristics of Oxide Film
Breakdown Voltage

Dillus ion

Inspection on Dillusion
o PQC Leve I Check
Evaporation
Inspection on Evaporation
o PQC Level Check
Waler Inspection

Evaporation

Thickness of Vapor Film.
Scratch. Contamination

Waler

Thickness. VTH Characteristics
Electrical Characteristics

Control 01 Basic Parameters
(VTH. etc) Cleaness of surf ace.
Prior Check of V,H
Breakdown Voltage Check
Assurance of Standard
Thickness

Prevention of Crack.
Quality Assurance of Scribe

Inspection on Chip
Electrical Characteristics
Chip Scribe
Inspection on Chip
Appearance
<> PQC Lot Judgement

Chip

Assembling

Assembling

Appearance alter Chip
Bond ing
Appearance alter Wire
Bonding
Pull Strength. Compresion
Width. Shear Strength
Appearance alter Assembling

Quality Check 01 Chip
Bonding
Quality Check of Wire
Bonding
Prevention of Open and
Short

Sea ling

Sealing

Guarantee of Appearance
and Dimension

o PQC Level Check
Final Electrical Inspection
OFailure Analysis

Mark ing

Appearance alter Sealing
Outline. Dimension
Marking Strength
Analysis 01 Failures. Failure
Mode. Mechanism

Feedback of Analysis Inlormation

Appearance 01 Chip

Fra ...

o PQC

Leve I Check

Inspection alter
Assembling
<> PQC Lot Judgement
Package

Appearance Inspection
Sampling Inspection on
Products
Receiving
Shipment

Figure 3 Example of Inner Procea Quality Control

~HITACHI
24

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - Q u a l l t y Aaaurance of

3.3.3 Final Tests and Reliability Assurance
(1) Final Tests
Lot inspection is done by quality assurance
department for the product passed in 100% test
in final manufacturing process. Though 100%
of passed products is expected, sampling inspec·
tion is subjected to prevent mixture of failed
products by mistake.

Ie

Memory

The inspection is executed not only to confirm
that the products meet users' requirement, but
to consider potential factors. Our lot inspec·
tion is based on MIL·STD·105D.
(2) Reliability Assurance Tests
To assure reliability, the reliability tests are per·
formed periodically, and performed on each
manufacturing lot if user requires.

r------------ ---------------------,
I
I
I

.-----~----~

I

Failure Analysis

I

I

I
I

I

I

I
I

Countermeasure
Execution of
Countermeasure

I
I

I

I

I
I
I

I
I
I
I

Report

I
I

II

I
Quality Assurance Dept.

I

Follow-up and Confirmation
of Countermeasure Execution

I
IL ________________________________
Report

II
I

I
I
~

Sales Engineering Dept.

Reply

Customer

Fiflilre 4 Prac. . Flow Chart of Coping with Failure to a Customer

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300

25

• OUTLINE OF TESTING METHOD
1. INSPECTION METHOD

2. MARCHING PATTERN

Compared to conventional core memories, IC
memories contain all peripheral circuits, such as the
decoder circuit, write circuit and read circuit. As a
result, assembly and electrical inspection of ICs are
all performed by IC manufacturers. Consequently,
as the electrical inspection of IC memories are
becoming more systematic, conventional IC inspection facilities are becoming useless. This has led to
the development and introduction of a memory
tester with pattern generator to generate the inspection pattern of the memory IC at high speed. A
function test for such as TTL gates can be performed even by a simple DC parameter facility.
However, when the address input becomes multiplexed as in 16K, 64K and 256K memory, even the
generation of the function test pattern becomes a
serious problem.
In the memory IC inspection, its quality cannot be
judged by DC test on external pins only, because the
number of the element such as transistor which can
be judged in the DC test is only 1/1000 of all elements. The followings are the address patterns pro- .
posed to inspect whether the internal circuits are
functioning correctly.
(1) All "Low", All "High"
(2) Checker Flag
(3) Stripe Pattern
(4) Marching Pattern
(5) Galloping
(6) Waling
(7) Ping.Pong
Those are not all, but only representative ones.
There are the pattern to check the mutual interference of bits and the pattern for the maximum
power dissipation. Among the above mentioned
patterns, those of (1) to (4) are called N pattern,
which can check one sequence of N bit IC memory
with the several times of N patterns at most. Those
of (5) to (7) are called N1 pattern, which need
several times of N' patterns to check one sequence
of N bit IC memory. Serious problem arises in using
N' pattern in a large-capacity memory. For example, inspection of 16K memory with galloping
pattern takes a lot of time - about 30 minutes. (1),
(2) and (3) are rather simple and good methods,
however, they are not perfect to find any failure in
decoder circuits. Marching is the most simple and
necessary pattern to check the function of IC
memories.

The marching pattern, as its name indicates, is a pattern in which "1 "s march into all bits of "O"s. For
example, a simple addressing of 16 bit memory is
described below.
(1) Clear all bits . . . . . . . . . . . . . See Fig. 1 (a)
(2) Read "0" from Oth address and check that the
read data is "0". Hereafter, "Read" means
"checking and judging data"
(3) Write "1" on Oth address ....... See Fig. 1(b)
(4) Read "0" from 1st address.
(5) Write" 1" on 1st address.
(6) Read "0" from nth address.
(7) Write" 1" on nth address ...... See Fig. 1(c)
(8) Repeat (6) to (7) to the last address. Finally,
all data will be "1".
(9) After all data become "1", repeat from (2) to
(8) replacing "0" and "1".
In this method, 5N address patterns are necessary
for the N·bit memory.

•
26

a

b

c

Figure 1 Addressing method of for 16 bit memory in the
Marching pattern

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

• APPLICATION
1. Static RAM
1.1. Static RAM Memory Cell
The static RAM memory cell consists of flip·flops
organized as 4 NMOS transistors and 2 load resistors
as shown in figure 1-1. The data in the cell can be
retained as long as power is supplied, and read out
without being destroyed.
Word Line

R,

R,

Figure 1·1.

Static RAM Memo!\, Cell

1.2. Data Retention Mode and Battery Back-up
System
The data in RAM is destroyed at power off. How·
ever, CMOS static RAM has a data retention mode.
In this mode, power consumption at standby is extremely low and supply voltage can be reduced to
2 V. So, it enables a battery back-up system to
retain data during power failure.
Data Retention Mode: The important point in
designing a battery back-up system is the timing
relation between the memory power supply during
the change (ordinal source -+ battery) and the chip
select signal. If the timing for the change is missed,
the data in memory might be destroyed.
Figure 1-2. shows the timing for switching the
power supply. The following explains the technical
terms related to the data retention mode.
Data retention mode
V..,---"""",
V.. ~2.0V

ov _________________________
_
C5(CE)~ V.. -0.2V·
FIguN 1-2.

(time for chip select to data retention): The
minimum time needed to change from operating
mode to data retention mode. Normally 0 ns.
tR (Operation recovery time): The minimum time
needed to change from data retention mode to
operating mode. Normally, it is the same as the
cycle time of the memory.
VDR (data retention voltage): The voltage applied in
data retention mode. Normally, the minimum
supply voltage needed to retain memory data is 2 V.
I CCDR (data retention current): The current can·
sumption in data retention mode. It depends on
memory power supply voltage and ambient tem·
perature. It is specified at supply voltage (VDR) =
3.0V.
Battery Back-up System: battery back-up sequence
is described in the following:
1. External circuit detects failure of system power
supply.
2. External circuit changes RAM to standby mode.
3. External circuit separates RAM from system
power supply.
4. External circuit switches to Back-up power
supply.
tCDR

Timing for Bettery Back-up Application

Data retention mode: The period that the power
supply voltage is lower than the specified operation
voltage. During this period, memory must be kept in
non-select condition (e.g. CS = VOR - O.2V).

•

Memory Vee

System Vee

]

...

~g

U

Memory

1 - - + - - - - - - - - - eontrol pin

Figure 1·3.

Example of Battllrv Back-up SVIWm

The control circuit detects the power failure and
cuts off the power after switching memories to
standby mode. On recovery, it confirms power
supply and after some delay, returns memories to
operating mode. The memory control signals
depend on the types of memories used in the
system.
* Using memory with only one CS. NAND signal
between the control signal and chip select signal
should be connected to es. As the level of CS in
data retention mode must be higher than VDR O.2V, the power supply for this NAND gate must
either be shared with the memory power supply,
or be pulled up to the memory power supply.
* Using memory with two es. Basically, the
signals are the same as mentioned above. In
general use, two pins should be used for the
control signal and the chip select signal respec·

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300

27

~I~don-----------------------------------------------------------------

tively. CS, which can intercept current path of
other pins in the input buffers, is for control
lignallnput of dati retention mode.
• Using memory with ~ Ind CS. As CS select.
the chips It high level, it is better to use CS thin
CS _ control signll input for dltl retention
mode. As soon _ power down is detected,
signlls should be brought to low level. So I pull·

FI..... 1-4.

E_pIe of ......., B_-up SVItem CINIIIt

$
28

up to the memory power supply level is not
needed end circuit organization is simplified.
Figure 14 shows In example of I blttery back·up
system circuit. Hitachi recommends using CMOS
logic for gate G t in control circuit Ind memory
Vee. The low VCE transistor Qt is required to
switch regulating circuit from system power supply
to back·up power supply.

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------------------------------------------A~lcation

2. Pseudo-Static RAM
2.1 P,eudo·Static RAM Feature,
A new type of memory, pseudo·static RAM has been
developed to provide the advantages of dynamic
RAM (low cost, high density) and static RAM (easy
usage). Ie memory consists of memory cells for data
storage, and input/output circuits for interfacing to the
external circuits. PSRAM provides the memory cell
and peripheral circuits of DRAM and the external con·
trol circuits, which includes a part of the refresh con·
trol circuits not provided by dynamic RAM, and inter·
face circuits similar to that of static RAM, on a chip, as
shown in table 2·1. Address input is not multiplexed
and data input/output is byte·wide like standard static
RAM. With PSRAM x 8 organization, medium den·
sity memory system can be designed easily. PSRAM
provides address refresh, automatic refresh and self
refresh.
Figure 2·1 shows examples of system design using
PSRAM and DRAM. Using PSRAM, the circuits

,....

Data

P

U

~

Addres.

C
Status
BUIY

j

I

r ..... &
ConlrOl

l-

I....

(PSRAMI

Figure 2·1.

System Or••nlzltlon

Memory Array

----

CiTr+ Ic/c.nl

SRAM

Memory Cell

4 Tr + 2 R

Organization

xI,x4,x8

Address

PSRAM
x8

Single Address

Refresh
External Circuits

DRAM

I Tr + I C

Nor
Necessary

Da..

xl, x4
Multiplexed
Address

CE

~~~._t===:=::::J
CoJumn Address

Necessary

Simple':

~Complex

Figure 2·2.

interfacing CPU to DRAM can be drastically
reduced.
Figure 2·2 shows block diagram of pseudo static
RAM.
2.2. 1 Mbit Pseudo-Static RAM Function
Read/Writa Cycle: Figure 2·3 and figure 2-4 show
the timing chart for the read/write cycle of 1 Mbit
pseudo·static RAM HM658128. The HM658128

Block DI. . .m CPSAAMI

can perform 2 types of access in a read cycle, CE
access (Figure 2·3 (a)) and OE access figure 2·3 (b)).
It writes the data at the rising edge of WE (figure
2·4 (all or at the rising edge of CE (figure 2·4 (bll.
The CS" pin should be brought high when the ad·
dress is latched at the falling edge of"CE in the read/
write cycle. The HM658128 has no"O"E' specifica·
tion at the falling edge of
as it provides both "O"E'
pin and R"FSR pin.

rn:

rr

CS
Da..

--~==tD.;;-l
(.) Ci

Ieee••

(b)

OE access

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

29

A p p l l c 8 t i o n - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CS Stendby Mode: The HM658128 enters CS
standby mode for one cycle if CS turns to low
at the falling edge of CE (figure 2·5).

S......,

Address

•

:: ;;;;;:J Illllzzzf;;
Figu... 2-1.

cs

cs Standby . .

DI"
(.) Write.t the riStnB edp of WE

Figu... 2....

(b) Write It the ri.in. ecIp of

CE

Writ. Cycl.

Addres. Refresh: Address refresh mode performs
refresh by access to row address (AO - A8) 0 - 511
sequentially within 8 ms, as shown in figure 2·6 (in

distributed mode). In this mode, CS should be high
at falling edge of CEo

15#1

cs--~~--------~--~--------~--~~------~~--~---

ReI.....

R/W

Fi..... 2-6.

Add .... RtfreIh

Automatic Refresh: The HM658128 goes to auto·
matic refresh mode if RFSH falls while CE is high
and it is kept low for more than 180 ns.
It is not required to input the refresh address from

address pins AO - A8, as it is generated internally.
Figure 2·7 shows the timing chart for distributed
refresh. In automatic refresh mode, the timing for
onlyCE and RFSH are specified.

"
RFSH

18000"Refreoh<8p.

Fi..... 2·7.

Self Refresh: Self refresh mode performs refresh at
the internally determined interval. The HM658128
enters the mode when the internal refresh timer is

•
30

Aut~c

RtfreIh

enabled by keeping CE high and RFSH low for
more than 81lS (figure 2-8).

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

---------------------------------Appllcatlon
Second self refresh current increases at low supply
voltage.

Figu ... 2-8.

S)(l
[If

Self Ref ......

Foil

Considerations on Using HM658128: The following
should be considered when using the HM658128.
• Data retention. The HM658128 can retain the
data with a battery (but not for long time). The
HM658128L, low power version, offers typical
self-refresh or standby current of 100#lA.
A 1-Mbyte system (using eight HM658128Ls)
can retain the data for about 1.5 months with
battery of 100 mAh current. Vee = 5 V ± 10%
must be maintained for data retention.
• Power on. Start HM658128 operation by
executing more than eight initial cycles (dummy
cycles) more than 100 J.Js after power voltage
reaches 4.5 V - 5.5 V after power on.
• Bypass capacitor. Hitachi recommends inserting
1 bypass capacitor per RAM.
2.3 Pseudo-Static RAM Data Retention
PSRAM with self refresh retains data CE and OE
are fixed for more than defined period. The following explains considerations for PSRAM data retention.
First, PSRAM cannot retain the data at low supply
voltage.
They employ 1 MOS type memory cell as shown in
figure 2-9. The charge is stored on the capacitor C
as memory data. The data 1, written at low supply

Self Ref...h VoJ_

Figure 2-10. PSRAM Opeml", Vol. . .

PSRAM provides the voltage level detector circuit
to reduce self refresh current. However, it should
be noted that the circuit increases the current with
low supply voltage in self refresh (figure 2-11). Self
refresh current also increases at low temperature
(figure 2-12).

Fi...... 2-11. Self Refr. Current VI. Vo .....

Spee

O"C

r""''''''''''' .. '"

~

Word Line

Please use PSRAM within the recommended operation range (Vee more than 4.5 V, temperature more
than OOC) for data retention, especially using a
banery.

Figu ... 2-9. Memory Cell of PSAAM

voltage, cannot be read as 1 at high supply voltage.
Figure 2-10 indicates the operation voltage for self
refresh and subsequent read of PSRAM. If the data
is read out at more than 5 V of Vee, for example,
after self refresh is performed at Vee = 3.7 V, it is
destroyed.
PSRAM must be used at supply voltage from 4.5V
to 5.5V.

o

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

31

~Ic.don------------------------------------------

3. INSTRUCTIONS FOR USING MEMORY
DEVICES
3.1 Prevention of Electrostatic Discharge
As semiconductor memory designs are based on a
very fine pattern. they can be subject to malfunction or defects caused by static electricity. Though
the built-in protection circuits assure unaffected reliability in normal use. devices should be handled
according to the following instructions:
1. In transporting and storing memory devices. put
them in conductive magazine or put all pins of
each device into a conductive mat so that they
are kept at the same potential. Manufacturers
should give enough consideration to packing
when shipping their products.
2. When devices touch a human body in mounting
or inspection. the handler must be grounded. Do
not forget to insert a resistor (1 MO approx. is
desirable) in series to protect the handles from
electrical shock.
3. Keep the relative ambient humidity at about
50% in process.
4. For working clothes. cotton is preferrable to synthetic fabrics.
5. Use a soldering iron operating at low voltage (12
V or 24 V. if possible) with its tip grounded.
6. In transporting the board with memory devices
mounted on it. cover it with conductive sheets.
7. Use conductive sheets of high resistance (about
109 ohm/D) to protect devices from electrostatic
discharge. For. if dropped onto conductive materials like a metal sheet. devices may deteriorate
or even breakdown owing to sudden discharg
of the charge stored on the surface.
S. Never set the system to which memory devi'
are applied near anything that generates hl&. I
voltage (e.g. CRT Anode electrode. etc.).
3.2 Using CMOS Memories
As shown in figure 3-1. the input of a CMOS memory is connected to the gate of an inverter consisting of PMOS and NMOS transistor. Figure 3-2
shows the relationship between the input voltage
and current in this inverter. The top and bottom
transistors turn ON and make current flown when
the input voltage becomes intermediate level.
Therefore. it is necessary to keep the input voltage
below 0.2 V or above Vee - 0.2 V in order to minimize power consumption. The data sheet specifies
the stand-by current for both the cases of input
level with minimum V 1H and maximum V 1L and that
with 0.2V or Vee - 0.2 V. and the difference in
value is remarkably great. Some memory devices
are designed to cut off such current flow in standby
mode by the control of input signals. but it depends

•
32

_______________________

on device type. This should be confirmed in data
sheet for each device type.

Figure 3-1.

CMOS Inverter

5
Vcc=5.0V

I

\.

r-.....
123(56
Input Voltage

Figure 3-2.

Relationship between Input Voltage &.
Current In CMOS Inverter

Another problem particular to CMOS devices is
latch-up. Figure 3-3 shows the cross section of a
CMOS inverter and the structure of a parasitic bipolar transistor. The equivalent circuit of the parasitic
thyristor is shown in figure 3-4. When positive DC
current or pulse noise is applied (figure 3-4 (a)). TR3
is turned on owing to the bias voltage generated
between base and emitter. And trigger current
flows into GND through R~ the base resistance of
TR2. As a result. TR2 becomes conductive and current flows from power supply IVeel through the
base resistance of TR 1 (R N ). which puts TR 1 into
conduction. too. Then. as the base of TR2 is rebiased by collector current from TR 1. the closed
loop consisting of TR 1 and TR2 reacts. Thus current flows constantly between power supply (Vee)
and GND even without trigger current caused by
outside noise.
Latch-up can be caused by a negative pulse. too
(figure 3-4 (bbl). Most of semiconductor memory
manufacturers are trying to improve latch-up immunity of their products. Hitachi provides enough
guard band by applying diffusion layer around inputs and outputs. taking care not to connect input
to p + diffusion layer. Input voltage for 64 kbit static
RAM HM6264A. for example. is specified as follows:

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------------------------~Ic.~on

V 1H max 6.0 V
V 1L min 3.0 V

(not depending on Vee)
(pulse width = 50 ns)
-0.3 V (DC level)

Thus almost no consideration for latch-up is required in system design.

Pin

(a)

Figure 3-3.

(b)

Cross Section Structure of CMOS Inverter
Closed Loop

Pin

i--Vee---;
I
I

Rn:

Vee

Pin

e~

T ..

an

I

I
I

~-;-+--i.T.,:
I
I
I
I

Til ON

j
I
:
Til ON L ______ ..J

Till ON

(a) Thyristor Effect by
Positive Voltage

Figure 3-4.

I
(b) Thyristor Effect by

Neaative Voltage

Equivalent Circuit of Parasitic Thyristor

3.3 Noise Prevention
Noise in semiconductor memories is roughly classified into input signal noise and power supply noise.

3.3.1 Input Signal Noise
Input signal noise is caused by overshoot and undershoot. If either of them is out of recommended
DC operating conditions, normal operation is hindered, and voltage over absolute maximum rating
will break the device. In operating high speed system, special care is required to prevent input signal
noise.
The noise can be prevented by inserting a serial resistance of less than 50 ohm into each input or a
terminating resistance into the input line. Actually,
however, input signal noise can be simply reduced
by a stable power supply line, because it is often
caused by unstable reference voltage (GND level) .

•

3.3.2 Power Supply Notice
The power source noise can be classed as lowfrequency noise and high-frequency noise as
shown in figure 3-5. To assure stable memory operation, the peak-to-peak power supply voltage in the
presence of low-or high-frequency noise should be
held below 10 percent of its standard level.

Figure 3-5.

Power Source Noise

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

33

AppIicatlon,--------------------------------Devices like dynamic RAMs, which operate from
clock signals, or high speed CMOS static RAMs,
through which current flows during transition of
signals, consume high peak current. When a power
supply does not have enough capacity for the peak
current, voltage drops. And if the recovery rate of
the power supply synchronizes with its time constant, it may start oscillating. To reduce the influence of the peak current, a bypass capacitor of 0.1
- 0.01 p.F should be inserted near the device. The
following points must be considered in designing
pattern of the board:
For bypass capacitors, use titanium ceramic, or
tantalum capacitors which have better highfrequency characteristics.

* Bypass capacitors must be applied as near to the
*

*

power supply pin of memory devices as possible,
and inductance in the path from Vcc pin to Vss
pin through the bypass capacitor must be as little
as possible.
The line connected to the power supply on the
board should be as wide as possible.
It is preferrable for the power supply line to be at
right angles to devices selected at the same time,
less too much peak current should flow through
one power supply line at a time

*

Prefernd

Cs

=

J

Si~l

~::::;~~~~

-Faults1. Bypath Linea are too

Lon•.
2. Devices Selected at

f-:~~=~~ S~~M-:~rn({:e,
Vee

VSI Vee Vss Vcc Vss

~---v-----'

Data 1/0

Figure 3-6.

Examples of Power Supply Board Pattern

3.4 Address Input Waveform of Hi-BICMOS
Memory
Data stored in memory might be destructed in case
that Address Input of the HM6716, HM6719,
HM6787, HM6788 and HM6789 series becomes
floating and sticks at and around threshold voltage.
(e.g. CPU does Address Bus to off state in Figure 1.)
Consequently, the following three methods are recommended so as to preserve malfunction of memory device.
A:

Insert latch as shown in Figure 3-7 lest Address Input should become floating.

B:

Put CS into High while Address Input becomes
floating.
(Dotted line in Figure 3.8)
Insert Pull-up Resistor (R) to hold time constant of Rising Edge wave form of Address Input pin (tr = R x C) below 150 ns.

C:

Pull·uP

cpu

AesIstor

s:.
~ I
j I

Addr •••

a".

cs

Memory
Input

I

n-

II. __ JI

Control
I

L_________________ --.I
Figure 3-7

Addr•••
Input

__

~:
(

Stable operation can be assured if you have already
adopted the above three method (A, B, C), while if
you have any problem, please contact our sales
offices.

Write

I

I

\1.--

r------,
Floating

\

\

,
Read

Figure 3-8

~HITACHI
34

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

Section 2
MOS Static RAM

$HITACHI®

HM6268 Series
4096-word x 4-bit High Speed CMOS Static RAM
-FEATURES
•
•
•

Single 5V Supply and High Density 20 Pin Package.
High Speed: Fast Access Time 25/35/45ns (max.)
Low Power Standby: 100j.!IN tyPo 5J.1.W typ (L·version)
Active: 250mW typo
Completely Static Memory: No Clock or Timing
Strobe Required
Equal Access and Cycle Times
Directly TTL Compatible - All Inputs and Outputs
Capability of Battery Back Up Operation (L-version)

•
•
•
•

I

(Dp·20N)
' - -_ _ _
_ _.__ ---1I

.ORDERING INFORMATION
Type No.
HM6268p·25
HM6268p·35
HM6268p·45

25ns
35ns
45ns

IIM6268LP·25
HM6268LP·35
HM6268LP·45

25n5
35ns
45ns

.PlN ARRANGEMENT

Package

Access Time

300mil 20pin
Plastic DIP

.BLOCK DIAGRAM
-ref
Memory Array

-\'ss

ti~ Rnws

256

CnJumn~

l,o':=]£=r--l{=~~~==J~~~
e>--.-l-H:>--I
Cnlumni/O

I/O,

I/(l! o--.+l-H:>--I
1/()4~mTP~L

_ _...J

.ABSOLUTE MAXIMUM RATINGS
Symbol

Ratinl

Volta,_ on Any Pin Relative 10 Vss

VT

-0.5" 10 +7.0

V

Power Dissipation

p,

1.0

W

Operatln, Temperature

T.,.

+70

Storage Temperature

Til.

-5510 +125

·c
·c

T....

-1010 +85

·C

Item

Temperature under Bias
Note) _1. -3.5V for pulse

o 10

Unit

wldth~10ns.

eHITACHI
36

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6268 Seri••
• TRUTH TABLE
CS

WE

Mode

Vee Current

I/O Pin

H

X

Not Selected

ISB./sB'

HighZ

L

H

Read

Icc

Dout

Read Cycle

L

L

Write

Icc

Din

Write Cycle

Ref. Cycle
-

.RECOMMENDED OPERATING CONDITIONS (Ta=O to +70·C)
Parameter

Symbol

min

typ

max

Unit

Vee

4.5

5.0

5.5

V

Vss

0

0

0

V

V,H

2.2

-

-0.5*'

-

Supply Voltage
Input High (logic 1) Voltage

V/L

Input Low (logic 0) Voltage
Note) *1. -3.0V for pulse

wldth~

6.0

V

0.8

V

IOns .

• DC AND OPERATING CHARACTERISTICS (Vee = 5V ± 10%. VSS = OV. Tn = 0 to +70°C
I'arametcr

Min.

Typ."

Max.

Unit

-

-

2.0

p.A

CS = VIH . Vila = Vss to Vec

-

-

2.0

p.A

Icc

CS = VIL • [110 = OmA. min. cycle

-

50'3

90

rnA

[SH

CS = V IH • min. cycle

-

15

25

mA

CS '" Vcc -0.2V.
OV :5 VIN :5 0.2Y or Vec - 0.2V :5 VIN

-

0.D2

2.0

rnA

-

I'~~

50"

p.A

Symbol

Output Leakage Current

111./1
111.01

Operating Power Supply Current
Standby Power Supply Current

Input Leakage Current

Standby Power Supply Current

(I)

Test Condition
Vce = 5.5V.

[SHI

Yin =

VSS to Vce

Output Low Voltage

VOL

[OL = 8mA

-

-

0.4

V

Output High Voltage

VOH

[OH = -O.4mA

2.4

-

-

Y

Notes)

* 1. Typical limits are at Vcc=S.OV. To=

+-25·C and specified loading .

• 2. 'J'his characteristics is guaranteed only for L·version.
40mA typo for 45ns version .

*:t

• CAPACITANCE ( Ta= 25·C. f = l.OMHz)
min

max

Unit

Input Capacitance

CIN

VIN=OV

-

6

pF

Input/Output Capacitance

C,io

V,jo=OV

-

9

pF

Parameter

Symbol

Test Conditions

Note: This parameter IS sampled and not 100°11 tested .

• AC CHARACTERISTICS (Vcc=5V±10%. Ta=O to +70·C. unless otherwise noted.)

• AC Test Conditions
Input pulse levels: Vss to 3.0V
Input rise and fall times: Sns

Input and Output timing reference levels: 1.SV
Output load: See Figure
Output Load (8)
(for tHZ. tLZ. twz & tOW)

Output Load (A)
5V

5V

Dou!

2S5Q

Dou!

25SQ

30pF'

5pF'

• [ncluding scope and jig.

•

HITACHI

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

37

HMe288S.~---------------------------------------------------------

eREADCYCLE

Read Cycle Time
Address Access Time
Chip Select Access Time

HM6268·35

HM6268·25

Symbol

Parameter

min

max

min

HM6268·45

max

min

Unit

max

IRe

25

-

35

-

45

-

ns

IAA

-

25

-

35

-

45

ns

25

-

35

-

45

ns
ns

-

lAcs

Output Hold from Address Change

roH

5

-

5

-

5

-

Chip Selection to Output in Low Z

iLz· 1

10

-

10

-

10

-

ns

Chip Deselection to Output in High Z

IRz·'

0

15

0

20

0

20

ns

Chip Selection to Power Up Time

lPu

0

-

0

-

0

-

ns

Chip Deselection to Power Down Time

IPD

30

ns

Note)

-

25

-

25

-

* 1. Transllion IS measured ± 200mV (rom steady state voltage with Load (B).
This parameter is sampled and not 100% tested,

•

Timing Waveform of Read Cycle No. 1 (11,(21

Address

0..,

•

Timing Waveform of Read Cycle No. 2(1),(3)
CS

ILl
OOUI

Hilh Impedance

-2:::::J

.~~IP~'~~,~______________________
VccSuppiy

-/(';-----------

Current

50%

I ..

Notes: 1. WE is High for Read Cycle.
2. Device is continuously selected, CS =VIL.
3. Address Valid prior to or coincident with es·transition Low.
e WRITE CYCLE
Parameter

HM6268·25

Symbol

HM6268·35

HM6268·45

min

max

min

max

min

max

Unit

Write Cycle Time

Ave

25

-

35

-

45

-

ns

Chip Selection to End of Write

tow

20

-

30

-

40

-

ns

Address Valid to End of Write

lAw

20

-

30

-

40

-

ns

Address Setup Time

lAs

0

-

0

-

0

-

ns

Write Pulse Width

Avp

20

-

30

-

35

-

ns

Write Recovery Time

Av.

0

-

0

-

0

-

ns

Data Valid to End of Write

ID ..

12

-

20

-

20

-

ns

Data Hold Time

IDH

0

-

0

-

0

-

ns

Write Enabled to Output in High Z

Avz·}

0

8

0

10

0

15

ns

Output Active from End of Write

tow·}

0

-

0

-

0

-

ns

Note)_t. Transition is measured ± 200mV from steady state voltage with Load (8).
This parameter is sampled and not 100% tested,

•
38

HITACHI

Hitachi America,ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

------------------------------------------------------------HM8288S~

•

Timing Waveform of Write Cycle No.1 (WE Controlled)
m r - - - -_ _ _ _ _ _

~

lr--Address

1-_______ '01 -------1
~~~

~~~~~~~~

IAll"------ooI

---~--~h~I-----

1111'

-----I ~-----_+_---_

Din

*3
Doul

•

««««

III"~

Timing Waveform of Write Cycle No.2 (CS Controlled)

'we
Addre8$

".

,,,

/C.

Din

Hich

DOUI

Imped.nc~

(4)

Notes: 1. A write occurs during the overlap of a low CS and a low ft. (twp).
or WE going high to the end of write cycle.
2. tWR is measured from the earlier of
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs
must not be applied.
4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output
buffers remain in a high impedance state.
S. If ~ is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to
the outputs must not be applied to them.
6. Dout is the same phase of write data of this write cycle, if tWR Is long enough.

es

.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

39

HM8288SeriM--------------------------------------------------------.LOW Vee DATA RETENTION CHARACTERISTICS (O'C:it To:it70'C)
This characteristics guaranteed only for L·version.
Symbol

Parlmeler

V••

Vee lor Dall Relention

Tell Condilions

CS;;: Vcc-O.2V

v..<: Vcc-0.2V

Dill Relenlion Current

IceD.

Chip De•• leci 10 Dill Relenlion Time

ICD.

Operllion Recovery Time

to

Notes) *1. tu-Reu CYe'I_ Ti ....

or

Ov:o; V.. :O;O.2V

See retention waveform

min

Iyp

m..

Unil

2.0

-

-

V

-

30 .,
20- 3

pA

-

-

ns

-

ns

0

',1.'

-I

.2. Va -3,O\'
.3. Ye,-2.0V

eLOW Vee DATA RETENTION WAVEFORM

vcc--------.
uv---------

DATA RETENTION IIODE

--_!.!._--------~

_ _ _..J

"---------------------------------------------

OHITACHI
40

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

_________________________________________________________ HM8218 . . . .
IUPPL V CURRENT VS. AMBIENT
TEMPERATURE

IUPPLV CURRENT VS. IUPPLV
VOLTAGE
1.6

Ta c 25'C

Vcc=S.ov

•

•

I.

I.

2

0

../

~
..."....

V

./

2

J

-

01---

1.

-

i--

8

6

1M

5.0

4.75

•.5

5.5

5.25

•

0. 0

80

SuppI)o V~ Vcc (V)

ACCESS TIME VI. LOAO
.CAPACITANCE

ACCESS TIME VI. IUPPL V
VOLTAGE
1.3
T.=25"C

1.2

./

r--.. I--...
!

0.9

J

o.p
G.7

••5

--5.0

4,75

7

V

~

5.25

5.5

./
0.6

o

,/

./

100

S...... V __ V.., (V)

200

300

400

Lood c.,.dton.. C, (pF)

SUPPLY CURRENT VS.
FREOUENCV

ACCESS TIME VI.
AMBIENT TEMPERATURE

T(M)

I.3

50

100

.1

25

20

V..,=5.0V
I.2

I

j

I.

!

0.9

J

°V~

I.0

./'"

9

~
~

8

/

V

V

;7
../

"

7

0.9

0.7 0

O.5 0

80

10

20

30

50

Frequency J (MH,)

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300

41

HM8288S.iH----------------------------------------------------------INPUT LOW VOLTAGE VS. SUPPLY
VOLTAGE

INPUT HIGH VOLTAGE VS. SUPPLY
VOLTAGE
1.3

I.3

r.=25'C

r.=25·C
1.2

~

1

--- ---

1

~

1.1

~

,!
1.0

!

1
11

0.9

:;:

0.7

4.5

4.75

5.25

5.0

~

--- ---

~

0.8

0.7

5.5

4.5

5.25

5.0

4.75

Sup.I, Vol.... Veo (V J

5.5

Supply Voilaif!' Vee (V)

OUTPUT CURRENT VS. OUTPUT
VOLTAGE

OUTPUT CURRENT VS. OUTPUT
VOLTAGE
1.6

r.=25'C

r.=25·C

Vcc=5V

\

Vcc=SV

1.4

.1

j

I

\

\

0.6

/

1.2

~ 1.0

I>

\\

0.8

/

j
0.6

/

V

0.2
Output Vol....

VDH

0.6
Output Vol&qe

(V J

STANDBY CURRENT VS. AMBIENT
TEMPERATURE

VOL

0.8

(V)

STANDBY CURRENT VS. SUPPLY
VOLTAGE

10'"

Er:2~:V

.

.
/
10'"

o

V

./

~

V
20

/

/

/

ra=2S"C

CS=Veo -0.2V

4

40

60

60

o. 2
S....I,Vol_ Vee (V)

•
42

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM6267 S e r i e s - - - - - - - 16384-word x 1·bit High Speed CMOS Static RAM
• FEATURES
• High Speed: Fast Access Time 35/45/55ns (max.)
• Low Power Standby and Low Power Operation
Standby: 0.1 mW (typ.)I5SlW (typ.) (L·version).
Operation: 200mW (typ.)
• Single 5V Supply and High Density 20 Pin Package
• Completely Static Memory ...... No Clock or Timing Strobe
Required
• Equal Access and Cycle Time
• Directly TTL Compatible: All Input and Output
• Capability of Battery Back Up Operation (L·version)

(DP·20N)

• PIN ARRANGEMENT

• ORDERING INFORMATION
Type No.

Package

Access Time

HM6267p·35
HM6267P-45
HM6267P·55

35ns
45ns
55ns

HM6267LP·35
HM6267LP-45
HM6267LP·55

35ns
45ns
55ns

300 mi120 pin
Plactic DIP

• BLOCK DIAGRAM
.0\0

-Vee
A.

-t1;s

AI
A,

Helw

MUlllry.o\rray

Dt('odrf

l2Kx 12M

(Top View)

II<

Au
Au

0..

'::.'----1..----..--- 00..

--i1>----1----~(~·.I::,,"'~1

CS

Wi:

AI'

AI'

.~

.,,~

Ai

."-

.~

• ABSOLUTE MAXIMUM RATINGS

To.,

Rating
-0.5*2 to +7.0
1.0
o to +70

Storqe
Temperature

T.tg

-55 to +125

Storqe Temperature Under Bias

Tbitu

-10 to +85

Item
Voltage on Any Pin u
Power Dissipation
Operating Temperature

Notn)

Symbol

VT
Pr

Unit
V

W

·c
·c
·c

0 •• With reaped ot VSS.
°2. -3.SV for pull. width ~ 20n•.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

43

HM82878wIM--------------------------------------------_____________
• TRUTH TABLE

cs

WE

Mode

Vee Currenl

Doul Pin

H

)(

NOI . . Ieeled

I." 1. 11

Hilh-Z

Ref. Cyele

L

H

Read

fcc

Doul

Read Cyele

L

L

Write

fcc

Hilh-Z

Wrile Cycle

• RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to +70°C)
Item
Supply Voltage
Input Voltage
Note)

•

min
4.5
0
2.2

typ

-0.5. 1

-

Symbol

Vee
VSS

V,H
VIL

max
5.S
0
6.0
O.S

5.0
0

-

Unit
V
V
V
V

.1. -3.0V for pulse width ~ 20ns

DC AND OPERATING CHARACTERISTICS (Vee
Symbol

Item
Input Leakage Current

Ihol

Operating Power Supply Current

ICC

min

VCC=5.5V, VIN=VSS to Vee
CS=V/H, Vour=Vssto Vee

Unit

10

-

-

jl.A

-

-

10

jl.A

40

SO

mA

typ·l max

-

-

min

10

-

-

10

40

100

10

20

-

10

20

mA

2

-

0,02

2

mA

-

1°2

50°2

jl.A

ISB

CS=VIH, min cycle

-

-

0,02

ISBI

CS ~ Vee- 0.2V,
OV ~ VIN ~ 0.2V or
Vee-0.2V~VIN

1°2

50°2

-

0.4

-

-

0.4

V

-

2.4

-

-

V

CS=VIL,IourOmA,min.cycle

Stand by Power Supply Current

Output Voltage

HM626745155
typOl max

HM6267-35

Test Conditions

IILlI

Output Leakage Current

=SV ± 10%, Vss =OV, Ta =0 to +70°C)

VOL

IOL = SmA

-

VOH

IOH=-4mA

2.4

Notes) * 1. Typical Umts are at VCC =5V, Ta =25'C and specified loading.
*2. This characteristics is guaranteed only for L-version.

• CAPACITANCE (To
he..

SYlllbol

Input Capaeitenee

C,.

O"IPUI Capac itenee

Cour

Noa.l

•
•

=2S'C,f= IMHz)

nil

,,'llMler " ...,1...M

ItOI

typo

-

-

.-

Unil

5

pF

v..-OV

7

pF

Vour-OV

Condilions

JOIW6 ....ed,

AC CHARACTERISTICS (Vee
AC TEST CONDITIONS

=SV ±10%, To = 0 to +70°C, unless otherwise noted)

Input pulse levels: Vss to 3.0V
Input rise and fall times: 5ns
Input and Output timing reference levels: 1.5V
Output load: See Figure

Output Load A
+SV

Do ••

'lUg

~
I$$g

30.r'

• Including scope and jig.

•
44

Output Load B
a 10.)

(for "'z, hz, ,.,

+SV

Do ••

~
2SSg

108
"r'

• Including scope and jig.

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------------------------------------HMe2e7s.~

• Read Cycle
Item

Symbol

HM6267-35

HM6267-45

HM6267-55

min

max

min

max

min

-

max

Unit

Notes

I

Read Cycle Time

tRe

3S

45

-

55

-

ns

Address Access Time

tAA

-

35

-

45

-

S5

ns

Chip Select Access Time

'ACS

-

35

-

45

-

55

ns

Output Hold from Address Change

tOH

-

5

-

5

ns

Chip Selection to Output In Low Z

tLZ

5

-

5

-

5

-

ns

2,3,7

Chip Deselectio to Output In High Z

tHZ

0

30

0

30

0

30

ns

2,3,7

Chip Selectlo to Power Up Time

tpu

0

-

0

-

0

-

ns

Chip Deselectlon to Power Down Time

tPD

-

20

-

30

-

30

ns

5

eTIMING WAVEFORM OF READ CYCLE NO.1

Address

4) II)

'Re

=t:'M

*

• I

tOH

Data Out

Previous Data
Valid

Data Valid

eTIMING WAVEFORM OF READ CYCLE NO.2 4)

6)

Data Out

Data Valid

Vee Supply
Current
Notes)

I. All Read Cylce timing are referenced from last valid address to the fint transitioning address.
2. At any liven temperature and voltage condition, 'HZ max. is less than' LZ min. both for a given device and
from device to device.
3. Transition is measured t500mV from steady state volt. with specified loading in Load B.
4. WE is High for READ cycle.
5. Device is continuously selected, ~. V/L'
6. Addresses valid prior to or coincident with ~ transition low.
1. This parameter is sampled and not 100% tested.

• Write Cycle
Item

Symbol

HM6267-35

HM6261-4S

min

max

min

max

3S

45
40

Chip Selection to End of Write

tcw

30

-

Address Valid to End of Write

tAW

30

-

Write Cycle Time

twe

HM6267-55

Unit

min

max

-

55

-

ns

-

ns

40

-

SO
50

-

ns

-

ns

Address Setup Time

'AS

0

-

0

-

0

Write Pulse Width

twp

20

-

25

-

35

Notes
2

ns

Write Recovery Time

tWR

0

-

0

-

0

-

ns

Data Valid to End of Write

tDW

20

-

25

25

-

ns

Data Hold Time

tDH

0

-

0

-

0

-

ns

Write Enabled to Output in High Z

twz

0

20

0

25

0

2S

ns

3,4

Output Active from End of Write

tow

0

-

0

-

0

-

ns

3,4

.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

45

HM8287 S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - •

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE Controlled)

,.,
AIkIr...

,
,

.

,

.

.

0.1. In

Data Out

•

0.11

Und, f Iftl.J

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS Controlled)

~t;=-----------------'wc-----------------~~

Ad_
CS

=*I-~:~ '-A- S- - - - - - -

A-W-=.-=.-=.-=.-=.-=.-=.-=.-=.-=.-=.-=.-=.-=.:,--'-.-R-j''------

_ -I

-------~~-----'cw--------V--------------

r----------

-.---..J'DH

Din

High Impedance
Dout

Notes) 1.
2.
3.
4.

If~ goes high simultaneously with WE high, the output remains in a high impedance states.
AJI Write Cycle timin.. are referenced from the last valid 'address to the fust transitions address.
Tnmition is measured 1 sOOrn V from steady state voltaae with specified loading in Load B.
This puameter Is sampled and not 100% tested .

•
46

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 6 7 Series

.LOW V" DATA RETENTION CHARACTERISTICS (O'C:;Ta:;70'C)
This characteristics is guaranteed only for L·version.
Parameter

VD •

Data Retention Current

*I

v..~

Vee-O.2V ur

Unit

-

V

-

-

30'2
20'3

0

-

"H'1

-

-

OV~ V..~0.2V

see retention waveform

to

Ih-R .... eyrie Time.

max

-

leu

Operation Recovery Time
Notes)

typ

2.0

C"S~ Vee -0. 2V

IceDl.

Chip D••• I.ct to Doto R.tention Time

min

Telt Conditions

Symbol

Vee for Dati Retention

J'A
.s
ns

*2 VLC-J.O\'
*3. Vel -Z.OV

eLOW Vee DATA RETENTION WAVEFORM
DATA RETENTION NODE

v" _ _ _ _ _ _ _,1
4.5V---------

-------------------------

---------

CS _ _ _ _J

ov ____________________________________________ _

SUPPLY CURRENT VS. SUPPLY VOLTAGE

SUPPLY CURRENT VS. AMBIENT TEMPERATURE
1.6

6

V('('=5.0V

Tu=2S"C
1-'

1

./

2

~

j
i

1.0

0.1t

L.----'

J!

----

~

/'

1.2

.!;

1.0

j
1.

0.'

--I- --

r--

0.6

0.6

0.4

i

~

4.5

\.0

'.

1.5

0.4 0

110
Ambient Temperature Ttl (t: )

Supplv VoltaRP \'('c rVl

_HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

47

HMe287~-------------------------------------------------------

ACCESS TIME VS. AMBIENT TEMPERATURE

ACCESS TIME VS. SUPPLY VOLTAGE

l

:t

VcC'-s.ov

TII=2!1t'

.,

I.'

!
I

~

i

~

j

1.0

r--.

n.9

---- -

~

I.

~

I.

t---

.-'

I

~
~

n~
9

0..

0.1

n.7

".

-,

1.5

III

II

Ambienl TemperM"" Ta

SUPPLY CURRENT VS. FREQUENCY

ACCESS TIME VS. LOAD CAPACITANCE

..

-''''

I

.~

".,

ti6

J.'I

"

I

./

9

Z

-

"
n.
•

L---- I---

{t I

.... /

~

/"

7

V

1I.1l

II.6

100

200

II.

400

300

INPUT LOW VOLTAGE VS. SUPPLY VOLTAGE

,
"

5

In

15
Frequenc:vJIMH1.1

3

To-2S'C

ro=25'C

1.2

1.2

.I

I

.0

~

---

~

~9

~

f

I

~

0.9

.0

>

1

1

I.---

~

--

~

.8

o.7

4.5

4,75

5.0

5.25

.7
4.5

5.5

~25

4.75

U

SupoI, V.kqo Vcc (VI

Supply Vnlt. . Vtc (V)

$
48

:r>

Z.

20

INPUT HIGH VOLTAGE VS. SUPPLY VOLTAGE

.3

I!

.,/

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------------------------------------HM8287S.IM
OUTPUT CURRENT VS. OUTPUT VOLTAGE

OUTPUT CURRENT VS. OUTPUT VOLTAGE

.6

6

T,=25'C

1\

.4

1

I .0

j
1

0.8

~

o.6

/

2

V

.0

.R

/

.6

\

o. 4

J

4

\
\
\
\

.2

~

.!

V('('=5V

/

T,=25'C
Vcc=5V

1/

.4

0.2

0.6

0.'
Output VnIt. Vnt {VI

OutPUt VnllQl! VtJII' (V)

STANDBY CURRENT VS.
AMBIENT TEMPERATURE

STANDBY CURRENT VS. SUPPLY VOLTAGE

·

•

10'

Vrc=3V
CS=2.RV

2

·

0

/
./

V

•
6

/

·

w o

o.

'/

20

10

/"

./'

/

v

/

7

/

Ta=2St
ES.Vcc-O.2V

o. 2

60

Stq:.piy Vnltaae \'cc

Ambient Temperlluft T4 (t \

•

(V)

HITACHI

Hitachi America, ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

49

HM6264A Series - - - - - - - - - 8192-word x 8-bit High Speed CMOS Static RAM
• FEATURES
• Low Power Standby

•
•
•
•
•
•
•

Standby:
O.1mW (typ.)
10llW (typ.) L·/LL·version
Operating: 15mW/MHz (typ.)
100ns/120ns/150ns (max.)

Low Power Operation
Fast access Time
Single +5V Supply
Completely Static Memory ..... No clock or Timing Strobe Required
_Equal Access and Cycle Time
Common Data Input and Output. Three State Output
Directly TTL Compatible: All Input and Output
Capability of Battery Back Up Operation (L·/LL·version)

HM6264AP Series

(DP·28)
HM6264ASP Series

• ORDERING INFORMATION
Type No.

Access Time

HM6264AP·I0
HM6264AP·12
HM6264AP·lS

lOOns
l20ns
IS0ns

HM6264ALP·lO
HM6264ALP·12
HM6264ALP·lS

lOOns
120ns
IS0ns

HM6264ALP·I0L
HM6264ALP·12L
HM6264ALP·lSL

lOOns
l20ns
IS0ns

HM6264ASP'10
HM6264ASP·12
HM6264ASP-1S

lOOns
120ns
ISOns

HM6264ALSP·I0
HM6264ALSP-12
HM6264ALSp·lS

lOOns
120ns
lSOns

HM6264ALSp·I0L
HM6264ALSp·12L
HM6264ALSP·lSL

lOOns
l20ns
lSOns

HM6264AFP·I0
HM6264AFp·12
HM6264AFP'lS

lOOns
l20ns
lSOns

HM6264ALFp·lO
HM6264ALFP·12
HM6264ALFp·lS

lOOns
120ns
lSOns

HM6264ALFP·lOL
HM6264ALFp·12L
HM6264ALFp·lSL

lOOns
l20ns
lSOns

Package

600 mil 28 pin
Plastic DIP
(DP·28N)
HM6264AFP Series

300 mil 28 pin
Plastic DIP
(FP·28D/DA)

• PIN ARRANGEMENT

28 pin
Plastic SOP
(Note)

Note) T IS added to the end of the type no. for a SOP of 3.00 mm (max.)
thickness.

(TopViow)

_HITACHI
50

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 8 2 8 4 A Serl••
• BLOCK DIAGRAM
A"
A,

o--+::C;;:t:::::f--'

~VCf

A,

A,
Au
A,

...<,,

1.'11,

--oVss

MelOOn' Malrix
256 X 256

-~i-t>r--H~-

n_--;___.-___

~

iiE _ - - - - - - - '

• ABSOLUTE MAXIMUM RATINGS
Symbol
Item
Terminal Voltage· 1
VT
Power Dissipation
PT
Operating Temperature
Topr
Storage Temperature
Tit,
Storage Temperature (Under~Bias)
Tbltu
Notes) *1. With respect to Vss.
*2. -3.0V for pulse width;;:! SOns

Rating
~.S·2 to +7.0

1.0

Unit
V
W

oto +70

°c

-55 to +12S
-10 to +8S

°c

C

• TRUTH TABLE

\W

cs.

CS, O£

H

X

X

X

X

H
H
L
L

L
L
L
L

L
H
H
H
H

H
L
H
L

X

X

Mode
Not Selected
(Power Down)
Output Disabled
Read
Write

I/O Pin
High Z

VCCCurrent

High Z
High Z
Dout
Din
Din

ISBlsBI
ICC
ICC
ICC
ICC

Note

ISBlsBI

Read Cycle
Write Cycle (1)
Write Cycle (2)

X:HorL

• RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 III +700 q
hern
SlIrrly Vult"j:c
Input Vnllaj:c

Syrnbul
Vee
VSS

min
4.5
0

V/H

2.2

VI/.

~.3·1

typ

max

S.II
0

S.S
0
6.0
0.8

Unit
V
V
V
V

Note) *1. -3.0V for pulse width ~ SOns

•

HITACHI

Hitachi America, ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300

51

HM8284A . . . .-----------------------------------------------------------

=

• DC AND OPERATING CHARACTERISTICS (Vee SV ± 10%. Vss
Symbol
Item
Test Condition

=OV. Til = 0 to
min

+70°C)
typ*1 max

-

IlLJI

VIn=Vssto Vcc

-

Output Leakage Current

Ihol

m=VIHorCS2=VIL orlm=VIHor'W£=VIL.
VIIO=Vssto Vcc

-

Operating Power Supply Current

ICCDe

ffi =VIL. CS2= VIH.IIlo=OmA

-

7

Input

Leabae Current

".A

2

".A

IS
4S·'
SS··

mA

mA

ICCI

IIIO=OmA

-

30
30

ICC2

Cycle time· 1".8. duty· 100%, !rIO" OmA,
BI ~ 0.2V, CS2 ~ Vcc -O.2V
VIH ~ Vcc -o.2V, VIL ~ 0.2V

-

3

S

ISB

CSl"VIH or CS2=VIL

-

1

3

mA

0.G2

2

mA

-

Averqe Operatina Current

Min. cycle, duty=I00%, m=VIL. CS2=VIH

VOL

IOL=2.1mA

-

VOH

IOH=-1.0mA

2.4

Standby Power Supply Current
ISBI~

Output Voltage

BI~Vcc-o.2V, CS2~Vec-O.2V or
OV :ii OS2 :ii 0.2V, OV :ii Y'n

2*3 100*·

typ

max

-

S

-.

7

-

0.4

V

-

V

Unit
pF
pF

Note) This parameter is sampled and not t 00% tested.

• AC CHARACTERISTICS (Vee

= 5V±10%. Ta

= 0 to +70°CI

• AC TEST CONDITIONS

Input Pul.e Level.: O.BV 12.4V
Input Rise and Fall Time: 10ns
Input Timing Ref.rence Level: 1.5V
Output Timing Reference Level: 0.BV/2.0V
Output Timing Reference Level: HM6264A·l0 1.5V
HM6264A-12/15 0.BV/2.0V
Output Load: 1TTL Gate and CL (100pF) lincluding scope and jig)

$
52

p.A

SO*·

• CAPACITANCE (/= IMHz, Ta = ~5°(')
Symbol Test (,undition
Vin = OV
On
VIIO = OV
CliO

mA

2"4

Not•• ) .1. TyplCllllmltl are at YCC=5.0V, TII =25°C and .peclfled loadln,.
*2. YIL mln-o.3V
*3. lb.. charecterUticalslllarent••d only for L-venlon.
*4. 1bU charecterbtlc... lIIaranteed only for LL-venlon.
* 5. For 120na/150nl venlon.
*6. For 100ni venlon.

Item
Input Capacitance
Input/Output Capacitance

Unit

2

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

-------------------------------------------------------------HM8284AS.ia
•

READ CYCLE

HM6264A·10
HM6264A·12
HM6264A·15
Unit
min
max
min
max
min
max
Read Cycle Time
100
120
150
ns
tRC
Address Access Time
100
120
150
ns
tAA
100
120
150
ns
I
CST
tCOl
Chip Selection to Output
100
CS2
120
150
ns
tC02
Output Enable to Output Valid
50
60
70
ns
tOE
10
10
15
ns
Chip Selection to
CST
tLZl
Output in Low Z
10
10
15
CS2
ns
tLZ2
Output Enable to Output in Low Z
5
5
5
ns
tOLZ
35
40
0
0
50
ns
0
I CST
Chip Deselection to
tHZl
Output in High Z
0
35
40
I CS2
0
0
50
ns
tHZ2
Output Disable to Output in High Z
0
35
40
0
0
50
ns
tOHZ
Output Hold from Address Change
10
10
10
ns
tOH
..
Notes) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open CirCUit condition and are not referred
to output voltage levels.
2. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from
d device to device .
Item

Symbol

-

I
I
I

-

-

• READ CYCLE
~------------------tRC------------------~

Address
~----~------tAA------------~

CS 1

"\\:\\:\i:\\:\\:\\:\i:\i~--------- t COl ---------i
1------- tLZl-------i
~-------tC02'----~--~

CS2

~~~~~~~~~------~Z2-------

Dout--------------__________________________

~

Data Valid
Note) 1. WE is high for Read Cycle

$HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

53

HM8284ASeriH-------------------------------------------------------------• WRITE CYCLE
Item

HM6264A-IO
min
max
100
80
0
80
60
0
0
35
40
0
35
0
5

Symbol

Write Cycle Time
Chip Selection to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Enable to Output in High Z
Output Active from End of Write

twe
tew
'AS
tAW
twp
tWR
tWHZ
fDW
fDH
tOHZ
tow

HM6264A-12
min
max
120
85
0
85
70
0
0
40
40
0
0
40
5
-

HM6264A-15
min
max
ISO
100
0
100
90
0
0
50
50
0
0
50
5

-

-

• WRITE CYCLE 111 COE clock 1

~------------twc------------~

Address

CS2

Din-----------------<.

•
54

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

-----------------------------------------------------------HM8284ASeri..
• WRITE CYCLE 121 laE Low Fixl

'lIIe

)K

Address

/
\.
'Alii

\\\ f\\ \ X

'IIIR [4)

'elll [2)

,I

VIII 'III/JLLL

[6)

'elll [2)

~/III rillIi'

~~\ \ \

CS2

WE

'AS [3)

'IIIP [I)

\\ \3
I

,\\\\Ui
'OH

[S)

'111HZ

'0111
(7)

Dout

\\\\\\\\
///111/1

\

\

\

~

\

///II~

-I
I

Pin Name

C!
WE

Function
Address
InputjOutput
Chip Select
Write Enable

Vee
Vss

Power Supply
Ground

AO-A13

1/01-1/04

(I,_rl+H>-I

I o~ .......H+H>--I

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

59

HM8288&.I_i--------------------------------------------------------.ABSOLUTE MAXIMUM RAnNGS
lIem

Symbol

Rltine

Voltqe on Any Pin Relative to Vss

Vr

-O.S·'to +7.0

Unit
V

Power Dillipalion

p,

1.0

W

Operlli .. Temperature

T...

+70

·c

Stonle Temperature

T•••

-55 to +125

'C

Tetnperature under Bia.

T....

-10 to +85

'C

o to

Note: *1. Vr mm.= -2.0V for pulse wldth:llOns

.TRUTH TABLE
CS

WE

Mode

Vee Current

110 Pin

H

x

Standby

ISB,IsB'

HighZ

L

H

Read

Icc

Dout

Read'Cycie I, 2

L

L

Write

Ict

Din

Write Cycle I, 2

Ref. Cycle

.RECOMMENDED DC OPERAnNG CONDIOONS (Ta=O to +70'C)
Parameter

Symbol

min

typ

max

Vee

4.5

5.0

5.5

V

Vss

0

0

0

V

Supply Voltage

Unit

Input High (logic 1) Voltage

V,N

2.2

-

6.0

V

Input Low (logic 0) Voltage

VIL

-0.5*1

-

0.8

V

Note: 01.

V.. min.= -2.0Y for pulae width:liIOna

.DCANDOPERAnNGCHARACTERlSnCS (Ta=Oto +70'C, Vcc=5V±10%, Vss=OV)
Parameter

Symbol

Test Condition

min

typ·'
.-

max

Unit

2.0

JJA

Input Leakage Current

I ILl I

Vec=MAX. VIN=Vss to Vee

-

Output Leakage Current

IILo I

CS= VIN, V/lO= Vss to Vee

-

-

2.0

/JA

Operating Power Supply Current

Icc

CS= VIL,I/lo=OmA, min. cycle

-

60

120

mA

CS= VIH, min. cycle

-

15

30

rnA

Iu,02

CS~ Vee -0.2V

-

0.02

2.0

rnA

Iu,u

OVliO VIN =>0.2V or Vee -0.2V=> VIN

-

0.02

0.1

rnA

Standby Vee Current
Standby Vee Current 1

ISB

Output Low Voltage

VOL

IOL=8mA

-

-

0.4

V

Output High Voltage

VOH

IOH=-4.0mA

2.4

-

-

V

Test Conditions

min

max

Unit

Yi.=OV

-

6

pF

8

pF

..

Notes. 'I. TyPlca) hmlts are at Vcc-S.OV. Ta= +25C and specified loading.
• 2. P vonion

*3. LPvenion

.CAPACITANCE (Ta=25·C,/=1.0MHz)
Parameter

Symbol

Input Capacitance

Cift

Input/Output Capacitance

Clio

Vllo=OV

_.

Note: Thi. parameter ,......pled Ind not 100% teoted

•
60

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300

•

---------------------------------------------------------HMe288~

• AC CHARACTEIISTICS
• AC Test Conditions
Input pulse levels: OV to 3.0V
Input rise and fall times: 5ns

Input and Output timing reference levels: 1.5V
Output load: See Figure
5V

5V

Doot

Dout

255Q

255Q

Output LOid (A)
Output Load (8)
(for 'HZ. 'LZ. 'Wz.t tow)

.Includilll scope & ii ..

• READ CYCLE
Parameter

Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address ehallle
Chip Selection to Output in Low Z
Chip Deselection to Output in High Z
Chip Selection to Power Up Time
Chip Seselection to Power Down Time

tRC
tAA
'ACS
tOH
tLZ·
tHZ·
tpu

tPD

HM6288-25
min
max
25
25
25
3
5
0
12
0
25
-

-

-

HM6288-35
min
max
35
3S
35
5
5
0
20
0
30
-

Unit
ns
ns
ns
ns
ns
ns
ns
ns

• Transition is measured 1: 200mV from steady slate voltage with Load (8).
This parameter is sampled and not 100""0 tested.

• Timing Waveform of Read Cycle No.1 [1] [2]

'"

'"

'"

'"

ProvioUi
Data Valid

Data Valid

• nmlng Waveform of Read Cycle No.2 [1] [3]
10,

cs

\

!

1\

'.'"

'"

f\'XXXXX)K

Dou.

Hip Impedan,.

.,.

------------1«
('urrenl

I,.

A

'"
"I--

Da.. Valid

) Hilb
I.......nce

''''
50% "

50%

1\

Not..: I. WE is IIigh for Read Cycle.
2. Drvice is continuously Belected. CS= V,L.
3. Address Valid prior to or coincident with CS trankition low .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

61

HM8288Serie.------------------------------• WRITE CYCLE
Symbol

Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time

twe
tew
tAW
tAS
twp
tWR
tDW
tDH
tWZ·

Date Valid to End of Write
Data Hold Time
Write Enabled to Output in High Z
Output Active from End of Write

HM6288-25
min
max
25
20
20
0
20
0
-

12
0
0

-

S

-

tOW"

8

HM6288-35
max

min
35
30
30
0
30
0
20
0
0

S

-

-

10

-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

• Transition is measured ± 200m V from ~tead)' state voltage with Load (B).
This parameter is sampled and not 100')0 tested.

• Timing Waveform of Write Cycle No_1 (WE Controlled)

Address

Ic.

I,.
I"

ID.

Din

Data in Valid

Dout

•
62

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM6288 Serle.

e Timing Waveform of Write Cycle No.2 (CS Controlled)
twe

Address

t ••

--------'\j..~-

__ ~ _____vr--------1..,.*1

tD.

tD'

Data in Valid

Din

Hlch Impedance .4

Dout

Notes) 1. A write occurs during the overlap of a low CSand a low WE. (In)
2. tWit is measured from the earlier of CS or WE going high to the end of write cycle.
3. Ouring this period. 1/0 pins are in the output state $0 that the input signals of opposite phase to the
outputs must not be applied.
4.lf the CS low transition occurs simultaneously with the WE low transition or after the WE
transition, the output buffers remain in a high impedance state.
5. If CS is low during this period. 1/0 pins are in the output state after tow. Then the data input signals
of opposite phase to the outputs must not be applied to them.
6. Dout is the same phase of write data of this write cycle. if tWR is long enough.

eLow Vee Data Retention Characteristics (Ta=O to +70'C)

(This Characteristics is guaranteed only for L-version.)
Parameter

Vee for data retention

Symbol

Min

Typ

Max

Unit

VD.

2.0

-

-

V

CS;;;: Vee-0.2V

-Data retention current
Chip deselect to data
retention time

Test Conditions

IccD.

-

-

50"
35"

",A

tCDR

0

-

-

ns

I.

lae l )

-

-

ns

Vi,;;;: Vee -0.2V or
OV::O; Vi, :>0.2V

See retention waveform
Operation recovery time
NOTE: 1. IRe = Read cycle time
2. Vee=3.0V
3. Vee =2.0V

Low Vee Data Retention Waveform
Data Retention Mode

4.5V-------- ------------------------- ---------

cs ____

.J

w ____________________________________________ _

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

63

HM6288Serie.-------------------------------------------------------------SUPPLY CURRENT VS. AMBIENT TEMPERATURE

SUPPLY CURRENT VS. SUPPLY VOLTAGE

1.6

1.6

Ycc=5.0Y

Ta=25't
4

1.4

]

1

1.2

]

'~"

..
I
u

1.0
0.8
0.6

2

~

i!;

-----

u

-----

l.--"'

~

]

5.0

r--..

0.6

20

5.5

5.25

1.3

~

~

1.8

]

1. 2

1.6

~

--

1. 1

.;:

!

80

Ta=25't

~

:;

60

ACCESS TIME VS. LOAD CAPACITANCE

ACCESS TIME VS. SUPPLY VOLTAGE

i!;

40

Ambient Temperature Ta rC)

Supply Voltage Vee (V)

]

r--- r--

.. 0.8

I

4.75

1.0

1.0

r-- t--

O. 9

<

g

i!;

1.4

j

1.2

~

1.0

~

g

r---

~

<

".

-----

V

V

0.8

0.8

O. 74.5

4.75

5.0

50

5.5

5.25

100

150

200

Load Capacitance CdpF)

Supply Voltage Vee (VI

SUPPLY CURRENT VS. FREQUENCY

ACCESS TIME VS. AMBIENT TEMPERATURE
1.3

100

1. 1

50

33

25

20 T (n5)

Ycc=5.0Y
1.2

1.0

1

1.0

--

V-

l.----

0.9

I--'"

-

O. 9

I

0.8

20

40

60

V

O. 8

80

O. 7

L

V

V

"'"

./

0.6

10

20

30

40

50

Frequency f (MHz)

Ambient Temperature Ta ('C)

$HITACHI
64

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------HM8288
HIGH LEVEL INPUT VOLTAGE VS.
SUPPLY VOLTAGE

LOW LEVEL INPUT VOLTAGE VS.
SUPPLY VOLTAGE
1. 3

1.3

]

To=Z5'C

]

I.Z

...

§

1.1

~

:>

~

1.0

>
1$

0.9

0.

oS

]

--r--

~

5.0

4.75

~
:>

1. 1

10
>

1.0

j

0.9

5

j
:r:

0

4.5

I.Z

_

....
0.7

To=Z5'(;

...

§

0.8

~

5.Z5

0.8
0.7

5.5

------

4.5

4.75

OUTPUT CURRENT VS. OUTPUT VOLTAGE ( 1 )
1.6

i

]
~

.s

I.Z

u

!

1.0

j
8

0.8

z

]
~

:r:

j

Vcc=5V

~
is
3
"0

Ta=Z5'C
Vcc=5V
1.4

I.Z

!
~

/

1.0

~

0

0.8

]

\

~

0.6

....0

\

/

0.6

STANDBY CURRENT VS. AMBIENT TEMPERATURE

5

!

u

..,.c>.
~

1.0
0.5

~

V

/

/

]

/'

/

1.2

1

1.0

:

0.8

!

0.6

II

3

/

u

>.

.c

'l!

0.4

~

~

O.Z
0.1

o

0.8

(V)

1.4
Vcc=3V
CS=Z.8V

13
]

0.6
VOL

STANDBY CURRENT VS. SUPPLY VOLTAGE

10

]

0.4

Low Level Output Voltage

(V)

VOH

/

/

O.Z

Z
High Level Output Voltage

5.5

1.6

u

\

5.Z5

5.0

OUTPUT CURRENT VS. OUTPUT VOLTAGE(2)

To=Z5'(;

\

\

L---

Supply Voltage Vcc (V)

Supply Voltage Vee (V)

1.4

Serle.

/'

/

/

To=25'C
a=Vcc -O.2V

o
ZO

40

Ambient Temperature Ta

60

2

80

c'e)

Supply Voltage Vee (V)

.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

65

HM8288 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - STANDBY CURRENT VS. INPUT VOLTAGE
10

Ta=2S'C
Vcc=S.OV
cs-UV

8
6

]

1'\

4

j

j
o

\
~

3

Input Voltage

4

VI~

5

6

(V)

.HITACHI
66

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM6788 Series

- - - - - - - - - - Maintenance Only

16384·word x 4-bit High Speed Hi·BiCMOS Static RAM

Refer to HM6788HA Series

.FEATURES
• Super Fast Access Time: 25/30n5 (max.)
• Low power Operation
Operating: 230mW (typ). Standby: 10mW (typ)
• +5V Single Supply
• Completely Static Memory No Clock or Timing Strobe required
• Balanced Read and Write Cycle Time
• Fully TTL compatible Input and Output

•

(DP·22NBI

ORDERING INFORMATION
Type No.

Access Time

HM6788P-2S

2Sns

HM6788P-30

30ns

Package

.PlN ARRANGEMENT

300 mU22 pin
Plastic DIP

.BLOCK DIAGRAM

Azo---Dc::r-i
A,

--o\'cr

A.

Memory Matrix

A.o---C::C:::J

--<>Vss

128X512

A.

A."---P.....-.
A.

110.
1I0,n........J...J'-""~....J

r/o,n..........'-""~....J
1/0. 0t1H+l-D........-j

.ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Rating

Unit

Terminal Voltage to Vss pin

VT

-0.5to +7.0

V

Power Dissipation

PT

1.0

W

Operating Temperature

Top,

Oto +70

·C

Storage Temperature (with bias)

T.. ,(bias)

-10to+85

·C

Storage Temperature

T6f,

-55to +125

·C

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

67

HM8788S.. . ------------------------------------________________________
.TAUTH TABLE
CS

WE

Vee Current

Output Pin

H

x

Not selected

iSB, iSBI

HighZ

L

H

Read

icc, Icc I

Dout

Read Cycle (1) (2)

L

L

Write

icc, ieCl

Din

Write Cycle (I) (2)

Mode

Ref. Cycle

-

x: H orL

.RECOMMENDED DC OPERATING CONDITIONS (O'C:O; Ta;:;;; 70'C)
Symbol

Item
Supply Voltage

min

typ

max

Vce

4.5

5.0

5.5

Unit
V

Vss

0

0

0

V

Input High Voltage

V,H

2.2

-

6.0

V

Input Low Voltage

V/L

-0.5*1

-

O.S

V

Note) .1. -3.RV with 20ns pulse width .

• DC AND OPERATING CHARACTERISTICS ( Vee = 5V ± 10%. Ta=O'C to + 70'C)
min

typ

max

Unit

Input Leakage Current

Ihll

Vee=S.SV, V'N= Vss to Vee

-

-

2

,..A

Output Leakage Current

Ihol

CS= V'H, Vtlo= Vss to Vee

-

-

2

,..A

Opearating Power Supply Current

Icc

CS= VIL,ltlo=OmA

-

SO

mA

Average Operating Current

leel

Min. Cycle, Duty: 100%

mA

cs= V,.

-

120

ISB

-

30

mA

Item

Symbol

Standby Power Supply Current

Test Conditions

ISBI

CSOI Vee-O.ZV, V,.,:OO.ZVor V,.,;;: Vee-O.ZV

-

Output Low Voltage

VOL

Int.=SmA

-

Output High Voltage

VnH

inH=-4mA

2.4

-

10

mA

0.5

V

-

V

-AC CHARACTERISTICS (Vee = 5V ±10%, Til = 0 to +70°C, unless otherwise noted)
• AC Test Conditions
Input pulse levels: Vss to 3.0V
Input rise and fall time: 4ns

Input and Output reference levels: 1.5V
Output Load: See Figure
+5V

HV

25511

SpF'

.lndudi........... iil-

Output Load B

(tCHZ. tWHZ. tCLZ. tOW)

Output Load A

.HITACHI
68

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 8 Series

eREAD CYCLE
HM6788·25
Item

Unit
min

max

tHC

25

tAA

-

Chip Select Access Time

tACS

Chip Selection to Output in Low Z

iel.1..

2

0

Chip Deselection to Output in High Z

tCHZ. 2

0

10

Output Hold from Address Change

tOH

5

..

max
ns

25

-

25

Chip Selection to Power Up Time"

frc

0

Chip Deselection to Power Down Time"

t,.D

.-

20

tr

ns

30

ns
ns

0

12

ns

5

-

ns

0

ns

_..

150

.. _ ' - - - -

Notes) .1. This parameter is sampled and not 1fI0'J'1) tested.
*2. Transition h; measured ., 200m\' form steady statt~ voltage with Load (H).
:1. If t'l becomes more than 1:i(Jn~. then' is pm;!>ihility of function fail.

*

30

0

.-

rka~~' ..'unlal'l )'lIur m:Ufl',\1

min
30

Read Cycle Time
Address Access Time

Input Voltage Rise/Fall Time"

•

HM6788·30

Symbol

Thi~

30

ns

150

ns

parameter is sampled and not 100"" h'stt'd

HilHl'hi Sak~ [kpt. rl'gunting :-'PCl'IIil: - -..C("]

Vss

Memory Matrix

A.~_.J'<'"

128X512

A4~-J"'c"'"

A.<>--1::(J
A. ~--1~____J

YOlo-~;:J=====1f~==~c:ol:um:n~I/~O~~l=~
1102

<>-1ft1>~

1/03

--TT'TT"'''''''''

(Top View)

YO • .........J...I.J.J ..........J

Absolute Maximum Ratings
Item

Symbol

Rating

Unit

Terminal Voltage to Vss pin

Vr

-0.5 to +7.0

Power Dissipation

PT

1.0

Operating Temperature

T."

oto + 70

·C

Storage Temperature (with bias)

T.,,(bias)

-IOto +85

·C

Storage Temperature

Til,

-55to +125

·C

Note)

V

'W

The specifications of this device are subject to change without notice.
Please contact Hitachi's Sales Dept. regarding specifications .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005 .. 1819 • (415) 589.. 8300

71

HM6788H

Series

Truth Table
CS

WE

H

x

L

H

L

L

Mode

Vcc Current

I/O Pin

Iss,/sBI

HillhZ

Read

Icc,lccl

Data Out

Read Cycle (1). (2)

Write

Icc,lccl

Data In

Write Cycle (1). (2)

N at selected

Ref. Cycle

x: H orL

Recommended DC Operating Conditions (O'C:;;; Ta:;;; 70'C)
min

typ

max

Unit

Vee

4.5

5.0

5.5

V

Vss

0

0

V,.

2.2

VII.

-0.5*1

Symbol

Item
Supply Voltage
Input High Voltage
Input Low Voltage

V
6.0

V

0.8

V

Note) *1. -3.0V with IOns pulse width.

DC and Operating Characteristics ( Vcc=5V ± 10%, Ta=O'C to +70'Cl
Symbol

Item

Test Conditions

min

typ

max

Unit

Input Leakage Current

I ILl I

Vcc=5.5V, V'N= Vss to Vee

Output Leakage Current

Ihol

CS= V,., Vdo= Vss to Vee

10

IJA

Opearating Power Supply Current

Icc

CS= V/L, [, lo=OmA

100

mA

120

mA

30

mA

10

mA

0,4

V

pA

Iccl

Min. Cycle, Duty: 100% 11/0 =OmA

Is.

CS= V,.

ISBI

CS~

Output Low Voltage

VO"

IOI.=8mA

Output Hillh Voltage

Vo.

10.= -4mA

Average Operating Current
Standby Power Supply Current

AC Characteristic. (Vee

Vee-O.2V, V,.,:;;O.2Vor V,.,~ Vce-O.2V

2,4

V

=5V ±10%, T. = 0 to +70°C, unless otherwise noted)

• AC Test Conditions
Input pulse levels: Vss to 3.0V
Input rise and fall time~ 4ns

Input and Output reference lavels: 1.5V
Output Load: See Figure
+5V

+5V

Output
Output
ZSIII

300F'

1T

Output Load B

(tHZ, tLZ. tWZ. tOW)

Output Load A

•
72

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300

-------------------------------------------------------------HM6788H

S.iH

Read Cycle
Item

HM6788H-IS

Symbol

min
Read Cycle Time

HM6788H-20

max

min

IS

Unit

Note

max

20

ns

Address Access Time

IS

20

ns

Chip Select Access Time

IS

20

ns
ns

1,2

8

ns

1,2

Chip Selection to Output in Low Z

3

Chip Deselection to Output in High Z

o

Output Hold from Address Change

3

o

6

3

tOH

3

ns

Note) -1. This parameter is sampled and not 100% tested.
-2. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

• Timing waveform of Read Cycle No.1 *1 .. 2

Address
tOH

Data Out

Data Valid

Previous Data Valid

• Timing weveform of Read Cycle No. 2*1.*3
~--------------tRe

Data Out

Data Valid

High Impedance

Note) *1. WE = VIH
*2. CS= VIL
*3. Address valid prior to or coincident with ~ transition Low.

Write Cycle
Item

HM6788H-IS

Symbol

min
Write Cycle Time
Chip Selection to End of Write

twe
tew

max

IS

20

10

15

o

Address Setup Time

HM6788H-20
min

Unit

Note

ns

2

max
ns

o

ns

Address Valid to End of Write

10

15

ns

Write Pulse Width

10

15

ns

Write Recovery Time
Write Enable to OU.tput in High Z

ns

o

twz

Data Valid to End oi Write
Data Hold Time
Output Active from End of Write

tow

6

o

8

ns

9

10

ns

o
o

o

ns

o

ns

3,4

3,4

Note) 1.lf"CS goes high simultaneously with WE high, the output remains in a high impedance state.
2. All Write Cycle timings are referenced from the last valid address to the first transitioning address.
3. Transition is measured t200mV from steady state voltage with specified loading in Load B.
4. This parameter is sampled and not 100% tested.

$

HITACHI

Hitachi America, Ltd. * Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

73

HM6788H S.io------------------------------------------------------------• Timing w."form of Writ. Cycl. No.1 (WE Controlled)
~-----------twc-------------_.,

Address

~r""'I'''''''''''' '41111----- tow

---------+",...,.....,...,..-+-,.....,...,....,....,..

1+------ tAW -------+1.

High Impedance

Data In

tOH*6

Data Out

• Timing w.veform of Write Cycl, No.2

(es Controlled)

I------- twc - - - - - - - -

Address

~----

_ _ _- - - - - - : - _

~

tAB

-------"'"'\1+-- tcw - - _ . , , . - - - - - - - -

n\.!;:: tow -+ ~I~

Data In
Date Out

""""'""~XX!""ft"'7XX!""ft"'7XXX!""ft"'7X0""ft""7XX0""ft""7XXL Data Valid !6.~XX~XX,....,....,XX
High Impedance *4

Note)*I. A write occurs during the overlap ot a low ~ and a low WE. (twp)
*2. tWit is measured from the earlier ot CS or W! going high to the end of write cycle.
*3. During this period, 110 pins are in the output state so that the input signals o£ opposite
phase to the outputs must not be applied.
*4. It the ~ low transition occurs simultaneously with the WE low transition or after the
WE transition, the output buffers remain in a high impedance stete.
*S.I£ ~ is low during this period, 110 pins are in the output state. Then the data input
signa's oC opposite phase to the outputs must not be applied to them.
*6. Data Out is the same phase of write data of this write cycle.

Capacitance (Ta=2S'C,/=l.OMHz)
Item

Symbol

min

typ

max

Conditions

Input Capacitance

6.0

VIN=OV

Input/Output Capacitance

10

Vl/O-OV

Note) Thi. po,ameter i. umpled and not 100'" teated.

•
74

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300

HM6788HA Series

- - - - - - - - - - - - - - Preliminary

16384·Word x 4·Blt High Speed Static RAM
• FEATURES
• Super Fast
Access Time ........................ .12/15/20ns (max.)
• + 5V Single Supply
• Low Power Dissipation
(DC) Operating ..........................300mW (typ.)
• Completely Static Memory
No Clock or Timing Strobe Required
• Fully TTL Compatible-All Inputs and Outputs

• PIN ARRANGEMENT

• ORDERING INFORMATION

Type No.

Access Time

Package

12ns
ISns
20ns

300 mil 22 pin
Plastic DIP
(DP-22NB)

HM6788HAP-12
HM6788HAP-IS
HM6788HAP-20
• BLOCK DIAGRAM

A, c>-~rl""--'
A7o---"Gi:J
A, O---I~ Row
As
Decoder

(DP-22NB)

-oVcc
-oVss
Memory Matrix
128 X 512

AJ.0---I~
Aso--.........,~D

~ C>--~~===d ~===:r::::~....... .

1101 O - -........·f~ooooooI
1102 o--ffii..i~ooooooI
1103 0--..1'++-1>-1
1/04 o-..-Hiooi-H

Vee

Ao
AI

cs

AI3
AI2
All
Al0
A9
1101
1102
1103
1104

VSS

WE

A2

A3
A4
As
As
A7
As

(ThpView)

~o-+----_-d""'-l
WE~====~~~~

_______~

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

75

HM6788HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Symbol
Vr
Pr
Topr
Tst•
Tbias

Item
Voltage on Any Pin Relative to Vss
Power Dissipation
Operating Temperature
Storage Temperature
Temperature Under Bias

• RECOMMENDED DC OPERATING CONDITIONS (O·C

Ta

$

Symbol

Item

Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
.Pulse width s IOns, DC: -D.5V

Mode
Not Selected
Read
Write

• DC AND OPERATING CHARACTERISTICS (Vee
Item
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Average Operating Current
Standby Power Supply Current

Symbol

Standby Power Supply Current (1)

ISB!

Output Low Voltage
Output High Voltage

VOL
VOH

IIul
IILOI
Icc
Icc!
ISB

= 5V

Typ.
5.0
0.0

-

::I::

10%, T.

CS O!: Vee - 0.2V
VIN $ 0.2V or VIN
IOL = SmA
IOH = -4mA

O!:

Vee - 0.2V

Ref. Cycle

Read Cycle (1), (2)
Write Cycle (1), (2)

Min.

Typ.

-

-

-

-

-

-

2.4

Max.
2
10
100
120
30

Unit
p.A
p.A
rnA
rnA
rnA

10

rnA

0.4

V
V

-

• Input Rise and Fall Times: 4ns
• Output Reference Levels: 1.5V

+5V

+5V

4800

Dout

Unit
V
V
V
V

= O·C to 70·C, Vss = OV)

Test Condition
Vee = 5.5V, VIN = Vss to Vee
CS = VIH , VIIO = Vss to Vee
CS = VIL , 1110 , = OmA
Min. Cycle Duty: 100% 1110 = OrnA
CS = VIH

• AC TEST CONDITIONS
• Input Pulse Levels: Vss to 3.0V
• Input Timing Reference Levels: I.5V
• Output Load: See Figure

Max.
5.5
0.0
6.0
O.S

110 Pin
HighZ
Data Out
Data In

Vee Current
ISB,IsB!
Icc, ICC!
Icc, ICC!

Unit
V
W
·C
·C
·C

70·C)

Min.
4.5
0.0
2.2
-3.0*

Vee
Vss
VIH
VIL

Supply Voltage

• TRUTH TABLE
CS
WE
H
X
L
H
L
L

$

Rating
-0.5 to +7.0
1.0
Oto +70
-55 to + 125
-10 to +S5

Dout

2550

2550

4800
5 pF *

Output Load B
(for tHZ , tLz , twz , & tow)

Output'Load A
*Including scope and jig capacitance.

$
76

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 8 H A Series

• CAPACITANCE (T.

= 25°C, f = 1.0MHz)

Item
Input Capacitance
Input/Output Capacitance
NOTE:

Symbol
CIN

Max.
6.0
10.0

CliO

Unit
pF
pF

Conditions
VIN = OV
VIIO = OV

This parameter is sampled and not 100% tested.

• AC CHARACTERISTICS (Vcc = 5V ± 10%, Ta = O°C to 70°C, unless otherwise noted.)
• Read Cycle

Item

Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output in Low Z
Chip Deselection to Output in High Z

tRC
tAA
tACS
IoH
tLz
tHz

NOTES:

HM6788HA-12 HM6788HA-15 HM6788HA-20
Min.
Max. Min.
Max.
Min. Max.
12
15
20
12
15
20
12
15
20
4
4
4
3
5
5
0
6
0
6
0
8

Unit

Notes

ns
ns
ns
ns
ns
ns

-

1,2
1,2

1. This parameter is sampled and not 100% tested.
2. Transition is measured ± 200mV from steady state voltage with specified loading in Load B.

• Write Cycle

Item
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
NOTES:

HM6788HA-12 HM6788HA-15 HM6788HA-20
Unit
Min.
Max. Min. Max.
Min.
Max.
12
15
20
ns
8
10
15
ns
8
10
15
ns
0
0
0
ns
8
10
15
ns
0
0
0
ns
7
10
ns
6
0
0
0
ns
0
6
0
6
0
ns
8
3
3
3
ns
-

Symbol
twc

lew
tAW
tAS
twp
tWR
tow
tOH
twz

tow

Notes
2

3,4
3,4

1. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
2. All write cycle timings are referenced from the last valid address to the first transitioning address.
3. Transition is measured ± 200mV from steady state voltage with specified loading in Load B.
4. This parameter is sampled and not 100% tested .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

77

HM6788HA Series - - - - - - - - - - - - - - - - - • TIMING WAVEFORM
• Read Cycle (1) (1)(2)

Address
tOH

tOH

Data Out

Data Valid

Previous Data Valid

• Read Cycle (2) (1)(3)

tRC

cs

"'

//

'\..
tACS
tLZ

tHZ

Data Out
High Impedence

NOTES:

~ "-/

Data Valid

"/
High
Impedence

I. WE is High for READ cycle.
2. Device is continuously selected, CS = VIL
3. Address valid prior to or coincident with CS transition low.

~HITACHI
78

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - -... -.--.--------.--.. - - - - - - - - - - - - - - - HM6788HA Series
• Write Cycle (1)

(WE Controlled)

twc
Address
tcw

cs

WE

High Impedance

High Impedance
Data In

tOH(6)

Data Out
• Write Cycle (2)

(CS Controlled)

twc
Address

)K

tWR(2)

tAW

t'
) "-

lAS

I

cs

tcw

~

/£
twp(1)

WE
IDW

Data In

Data Valid

Data Out
NOTES:

High Impedance (4)

I. A write occurs during the overlap of a low CS and a low WE (twp).
2. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
3. During this period, lIO pins are in the output state so that the input signals of opposite phase to the outputs must not
be applied.
4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output
buffers remain in a high impedance state.
5. If CS is low during this period, lIO pins are in the output state. Then the data input signals of opposite phase to the
outputs must not be applied to them.
6. Dou. is the same phase of write data of this write cycle .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

79

HM6289 Series
16384·Word X 4·Blt High Speed CMOS Static RAM (with OE)
The Hitachi HM6289 is a high speed 64k static RAM organized
as 16-kword x 4-bit.lt realizes high speed access time (25/35/45 ns)
and low power consumption, employing CMOS process technology.
It is most advantageous for the field where high speed and high
density memory is required, such as the cache memory for main
frame or 32-bit MPU.
The HM6289, packaged in a 300-mil SOJ, is available for high
density mounting. Low power version retains the data with battery
back up.

HM6289 Series

(CP-24D)

Pin Arrangement
Features
High speed
Access time:
25135 ns (max)
High density 24-pin SOJ package
Low power
Active mode:
300 mW (typ)
Standby mode:
100 JlW (typ)
Single 5 V supply
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible: All inputs and outputs

AIO

Ordering Information
Type No.

HM6289JP-25
HM6289JP-35
HM6289UP-25
HM6289UP-35

Access Time
25 ns
35 ns

25ns
35 ns

(fop View)

Package
300-mil
24-pin
SOJ
(CP-24D)

Pin Description

Block Diagram
AZo---;
A30---;

- - 0 Vee

--0

-'40----1
A50----1~

A6o---\

MemOl')' M.trb.

121x512

v.s

Pin Name
AO-A13
1/01-1/04
CS

DE
WE
Vee
Vss

Function
Address
Input/output
Chip select
Output enable
Write enable
Power supply
Ground

A7 o---;I~_J
A.o----1~

1/020--.,..H-11>-I
1/03

o-t+++-r">

1/04 ~t++H:>-t

.HITACHI
80

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 9 Series

Function Table
CS
H
L
L
L
Note:

X·

OE

WE

x

x

L
H
H
L
L
L
HorL

Mode
Not selected
Read
Write
Write

VccCurrent
ISB,IsBI
Icc
Icc
Icc

Ref. Cycle

I/O pin
High-Z
Dout
Din
Din

Read cycle (1)-(3)
Write cycle (1)-(2)
Write cycle (3)-(6)

Absolute Maximum Ratings
Unit
V
W
·C
·C
·C

Value
-0.5"1 to +7.0
1.0
oto +70
-55 to +125
-10 to +85

Item
Symbol
Vin
Voltage on any pin relative to Vss
Power dissipation
Pr
Topr
Operating temperature range
Storage temperature range
T...
Storage temperature range under bias
Tbia.
Note: *\. Yin min = -2.0 V for pulse widlh S \0 ns.

Recommended DC Operating Conditions (Ta = 0 to +70°C)
Item
Supply voltage

Symbol
Vcc
Vss
Input high (logic 1) voltage Vm
Input low (logic 0) voltage
Va.
Note: *\. Va. min = -2.0 V for pulse width S IOns.

Min
4.5
0
2.2
-0.5. 1

Max
5.5
0
6.0
0.8

Typ
5.0
0

Unit
V
V
V
V

DC Characteristics (Ta =0 to +70°C, Vee =5 V ± 10%, vss =0 V)
Item
Input leakage current

Symbol
IILlI

Min

Typ·1

Max
2.0

Unit

2.0

~A

Output leakage current

IILaI

Operating Vcc current

Icc

60

120

mA

ISB
IsBI· z
IsBI· 3

15
0.02
0.02

30
2.0
0.1

mA
mA
mA

Standby Vcc current
Standby Vcc current (1)

Output low voltage
VOL
0.4
Output high voltage
VOH
2.4
Notes: *\. Typical limits are at Vee= 5.0 V, Ta = +25·e and specified loading.
*2. P-version
*3. LP-version

Test Conditions
Vee = Max
Yin = OV to Vcc
CS=Vm
VI/O=OVtoVee
CS = Va., 11/0 = 0 mA,
Min. cycle
CS = Vm, Min. cycle
CS~ Vcc- 0.2 V
OV S Yin S 0.2 V or
Vee- 0.2 V S Yin
IOL=8mA
IOH =-4.0 mA

~

V
V

Capacitance (Ta = 25°C, f = IMHz)
Item
Symbol
Min
Input capacitance
Cin
Ineul/ou!put caeacitance
CI/O
Note: This parameter is sampled and not 100% tested .

•

Typ

Max
6
8

Unit
pF
pF

Test Conditions
Yin =OV
VI/O-OV

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

81

HM628988rI8.----------------------------

AC Characteristics (Ta = 0 to +70°C, Vee = 5 V ± 10%, unless otherwise noted.)
T8.t Condition.
Input pulse levels:
Input rise and fall times:
Input and output timing reference I'llleis:
Output load:

Vssto 3.0 V

5 ns
1.5 V

See figures

Ouiput Load (A)

Oulplll Load (8)

(for IOIZ. ICLZ, 101lZ.
~+5V

~4800

L ~30pF*

Douto-.......- - t

2550

Dout

~

2550

IOLZ. IWIIZ &'IOW)

;8::
5pF*

~

Note:

* Including scope &. jig.

Read Cycle
HM6289-25
HM6289-35
Unit
Min
Max
Min
Max
Read cycle time
IRc
25
35
ns
Address access time
lAA
25
35
ns
Chip select access time
tACS
25
35
ns
tcLz° 1
5
5
ns
Chip selection to output in low-Z
Output enable to output valid
toB
12
15
ns
toLZO!
Output enable to output in low-Z
0
0
ns
talZ°!
Chip deselection to output in high-Z
20
0
12
0
ns
toHZO!
Chis disable to output in high-Z
10
0
10
0
ns
toH
Ou~ut hold from address change
3
5
ns
ns
lPU
0
0
Chi~ selection to ~wer up time
30
ChiE deselection to power down time !PO
25
ns
Note: .1. Ouiput transition is measured ±200 mV from steady state voltage with Load (B). This parameler is sampled and not 100%
tested.
Item

Symbol

•
82

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - HM6289 Series

Read Timing Waveform (1) "

----------------,

Addre..

Read Timing Waveform (2) "

.'2.'4

".wre••
I ..

Dool

D... Vllld

=-_====::::::::===-__---.J

__________.______
-=_=._=_===.

Read Timing Waveform (3) '1,'3,'4

.------=------------------------------------,
I".
I ..

Dout

Olta VaJld

HIIIt Imptodanr.t

'-----==-------------------_._._---_._---_._--------------'
Notes: *1.
*2.
*3.
*4.

WE is high for read cycle,
Device is continuously selected, CS =Vn..
Address valid prior to or coincident with CS transition low.
OE= Vn..

Write Cycle
HM6289-25
Max
Write cycle time
LWe
25
-------------Chip selection to end of write
lew
20
Address valid to end of write
20
tAW
Address setup time
tAS
0
LWp
Write pulse width
20
Write recovery time
LWR
0
------.
Output disable to output in high-Z'!
lOHZ
0
10
Write to output in high-Z'!
LWHZ
0
8
Data to write time overlap
IDw
12
Data hold from write time
IDH
0
Output active from end of write'!
tow
5
Item

Note:

*1.

Output transition is measured
tested.

Symbol

--Mii1-

HM6289-35
Min
Max
35
30
30
0
30
0
0
10
10
0
20
0
5

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

± 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100%

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

83

HM6289 Serl•• - - - - - - - - - - - - - - - - - - - - - - - - - - -

Write TIming Waveform (1) (OE =High, WE =Controlled)
hc

Addrn.

Ic.

I,.

.....

,

h.
Dia

IN

o.laVoIld

HIP I..,.....,..

Write Timing Waveform (2) (00 = High, CS = Controlled)
I ..

Ad......

1M

Ic.

es
I,.

' ..~.1

WE

Dio

xxxxx~

I ..

Dolo Volld

HIP I.pedon..

~HITACHI
84

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 9 Series

Write Timing Waveform (3) (OE = Clocked, WE = Controlled)
I

....... ~It

iii

---11\
II I V if

I\,

1\\\\\
I.

ii

Wi

\

\

\

\ 1\1

-

/11 IIIII

I,.

iJa-.-I

f---!!!V

' .... 1

\\\

/
l.f4,11'*.

~
0...

\l

r-

Hilhlftllll4lll.

Jl

~
I ••

I
D.

I.

I

(X~

n.. V,11d

;(X)

Write Timing Waveform (4) (OE = Clocked, CS = Controlled)

I,.
I,.

.....

,

to.
D.

O.... VIlId

Dout.

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, GA 94005-1819 • (415) 589-8300

85

HM6289 Serle. - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Write Timing Waveform (5) (OE = Low, WE = Controlled)

''''
Addrnl

".

I.,. ••

...
Dout

I...
Om

Write Timing Waveform (6) (OE

D.Vaiid

'l1li
.5

=Low, ~ =Controlled)

Acldrn.

0 ...

Om

Notes:

A write occurs during the overlap of a low CS and a low WE. (tWp)
tWR is measured from the earlier of CS or WE going high to the end of write cycle.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
If the (:Slow transition occurs simultaneously with theWE low transition or after the WE transition, the output buffers remain
in a high impedance state.
oS. If CS is low during this period, I/O pins are in the output state after tow. Then the data input signals of opposite phase to the
outputs must not be applied to them.
°6. Dout is the same phase of write data of this write cycle, if tWR is long enough.
°7. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in high
impedance state.

01
°2.
°3.
°4.

•
86

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6289 Series

Low Vee Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Item
Vcc for data retention
Data retention current

Symbol
VDR
IC--1
1/03 0-"-+-1+1'>--1
1/04 ~++I+I>--I

a~==~D

tlEO+----+-I::::lT'""l

AblOlute Maximum Ratings
Item

Symbol

Rating

Terminal Voltage to V88 Pin

VT

-0.5 to +7.0

V

Power Dissipation

PT

1.0

W

Operating Temperature Range
Storage Temperature Range under bias
Storage Temperature Range

Unit

o to +70

·C

T,,.(bias) -10 to +85

·C

Top,

(Top Vie,,)

-55 to+125 ·C

T,rg

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589·8300

91

HM8789 S.,I..

Recommended DC Operating Conditions (Ta = 0 to +70°C)
Item

Symbol

Supply Voltage

min

typ

max

VCC

4.S

S.O

S.S

V

VSS

0.0

0.0

0.0

V

Unit

Input High Voltage

VIH

2.2

6.0

V

Input Low Voltage

VIL

-o.S·'

O.S

V

Note) *1. -3.0V for pulse width

Function Table
OE
CS

~

20ns.

WE

H

HorL

Hor L

L

H

H

L

L

H

L

H

L

L

L

L

Mode

VcCCurrent

1/0 Pin

Not selected

ISB.ISBI

HighZ

Output Disabled

ICC. Icci

High Z

ICC.ICCI

Dout

ICC, Icci

Din

Write Cycle (1) (2) (3) (4)

ICC,ICCI

Din

Write Cycle (S) (6)

Read
Write

Ref. Cycle

Read Cycle (1) (2) (3)

DC and Operating Characteristics (Vcc =5V±1 0%, T.=O to +70°C)
Symbol

Item

min

typ

max

Test Conditions

Unit

= S.SV, VIN =VSS to VCC
CS =VIH or DE = VIH or WE ~ VIL
VI/O = VSS to VCC

IILlI

2

p.A

Output Leakage Current

IILOI

2

p.A

Operating Power Supply Current

Icc

100

mA

CS = VIL, 11/0 = OmA
Min.Cycle,Duty: 100%,11/0=OmA

Input Leakage Current

Average Operating Curren!

VCC

ICCI

120

mA

19B

30

mA

CS = VIH

10

mA

CS6; V CC - 0.2V
VIN ~ 0.2V or VIN 6; VCC - 0.2V

0.4

V

10L = SmA

V

10H = -4mA

Standby Power Supply Current
ISBI
Output Low Voltage

VOL

Output High Voltage

VOH

2.4

AC Test Conditions
• Input pulse levels .. . . . . . . . . . . . . . . . . .. Vss to 3.0V
• Input and Output reference levels . . . . . . . . . . . . . . 1.5 V
• Input rise and fall time . . . . . . . . . . . . . . . . . . . . . . 4 ns
• Output Load: See Figure
+5V

Dou.

D..,

• indudina:
"'........ ji.

Output Lood A

$
92

HITACHI

Hitachi America. Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 9 S.rl••

=2S o C,f= 1.0MHz)

Capacitance (T"
Item

Symbol

Input/Output Capacitance

ClIO

min

typ

max

Unit

8

pF

Test Conditions

--------------------~--------------~~----------------Imput Capacitance
CIN
6
pF
.... _---_._-

_

Note) This parameter is sampled and not 100% tested.

AC Charactaristics (V cc=SV±lO%, Ta=O to +70°C, unless otherwise noted.)
Read Cycle
.._---_._---Item

HM6789-25

Symbol

min

HM6789-30

max

min

max

ns

Read Cycle Time

tRC

Address Access Time

tAA

25

30

Chip Select Access Time

tACS

25

30

Chip Selection to Output in Low Z

tCLZ·1

0

Output Enable to Output Valid

tOE

0

Output Enable to Output in Low Z

tOLZ·1

0

Chip Deselection to Output in High Z

tCHZ·1

0

Output Hold from Address Change

tOH
tT*'

5

Input Voltage Rise/FaIl Time

30

25

0

ns

12

ns

ns

0

ns

5
150

150

ns

15

0
10

ns

ns

0
15

Unit

ns

Write Cycle
Item

Symbol

HM6789-25
min

max

HM6789-30
min

Unit

max

Write Cycle Time

twc

25

30

ns

Chip Selection to End of Write

tew

20

25

ns

Address Setup Time

tAS

0

0

ns

Address Valid to End of Write

tAW

20

25

ns

Write Pulse Width

twp

20

25

ns

------

Write Recovery Time

tWR

0

Write to Output in High Z

tWHZ·1

0

Data Valid to End of Write

tow

15

20

Data Hold Time

tOH

5

5

Output Disable to Output in Hihg Z

tOHZ·1

0

Output Active from End of Write

tOW·1

0

ns

0
10

10

0

0
0

12

ns
ns
ns

10

ns
ns

Notes) * 1. Transition is measured t200mV from steady state voltage with Load (D).
This parameter is sampled and not 100% tested.
*2. IftT becomes more than 150ns, there is possibility of function fail.
Please cnntact ynur nearest Hitachi Sales Dept. regarding specitication.

$

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

93

HM6789

Serl••

Timing Waveform
R..d Cycle 1,,'1

Addreal

1iE

l
*

'Re

~

·1

'"

Dout

Reed Cycle 12,'1. '2. '3

'"
Add....

'"

'"
Dout

Do.. Volid

Previovs Data Valid

Reed Cycle 13,'1. '3. '4

'eu

0 ....

""
Do.. Volid

Hiah 1m.........

Notes) *1. WE· VIH
*2. CS= VIL
_
*3. 
1/04 ~++f+-'I

>-1

a&:t===+;:::[)
nEO+----H--.g,

Absolute Maximum Ratings
Symbol

Rating

Terminal Voltage to fISS Pin

Item

VT

-0.5 to +7.0

V

Power Dissipation

PT

1.0

W

Operating Temperature Range
Storage Temperature Range under bias
Storage Temperature Range
Note)

Top,

(Top View)

o to +70 °c

T,tg(bias) -10 to +85

T,tg

Unit

-55 to +125

°c
°c

The specifications of this device are subject to change without notice.
Please contact Hitachi's Sales Dept. regarding specifications.

~HITACHI
98

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

I

----------------------------------------------------·---------------HM6789H
0 to +70°C)

Recommended DC Operating Conditions (Ta =
Item

min

typ

mal(

VCC

4.5

5.0

5.5

V

Vss

0.0

0.0

0.0

V

Symbol

---_.-

Supply Voltage
Input High Voltage
Input Low Voltage

Unit

VIH

2.2

6.0

V

VIL

-0.5. '

0.8

V

Note) "I. -3.0V for pulse width

~

S.ies

IOns.

Function Table
CS

CiE

WE

H

Hor L

H or L

L

H

H

L

L

H

L

H

L

L

L

L

Mode

Ref. Cycle

VccCurrent

1/0 Pin

Not selected

ISB.ISBI

High Z

Output Disabled

ICC. ICCI

High Z

ICC.ICCI

Data Out

ICC. ICCI

Data In

ICC. ICCI

Data Out

Read
Write

DC and Operating Characteristics (VCc=5V±10%,
Item

Symbol

Read Cycle (1) (2) (3)
Write Cycle (1) (2) (3) (4)
Write Cycle (5) (6)

Ta=O to +70°C)

min

typ

max

Test Conditions

Unit

Input Leakage Current

IILlI

2

/AA

Output Leakage Current

IILOI

10

/AA

=5.5V, VIN =VSS to VCC
CS =VIH or~ =VIH orWE= VIL.
VI/O = VSS to Vec
VCC

Operating Power Supply Current

ICE:

100

rnA

CS =

Average Operating Current

ICCI

120

mA

Min.Cycle,Duty: 10O%,II/0=OmA

ISB

30

rnA

CS

ISBI

10

mA

CS~ V CC - 0.2V
VIN ~ 0.2VorVIN ~ Vee -O.2V

0.4

V

10L

V

IOH

Standby Power Supply Current
Output Low Voltage

VOL

Output High Voltage

VOH

2.4

VIL. 11/0 = OmA

= VIH
=SmA
=-4mA

AC Telt Conditions
•
•

Input pulse levels . . • . . . • . . . . . . . . . . . . . Vss to 3.0V
Input and Output reference levels . . . . . . . • . . . . • • 1.5 V

•
•

Input rise and fall time . . . . . . . . . . • . . . • . . . • . . • 4 ns
Output Load; See Figure

Output

Output
255C

• includinc
lcope and iii

o••PU' Load B

Output I....oad A

(~~:;: :::~t!:;f

•

HITACHI

Hitachi America. Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300

99

HM6789H Seriel

Capacitance (Til = 2SoC,f= l.OMHz)
Item

Symbol

typ

min

Test Conditions

max

Unit

Imput Capacitance

CIN

6

pF

VIN = OV

InputlOutput Capacitance

CI/O

10

pF

VI/O= OV

Note) Thll parameter ISlampled and not. 00% tested.

AC Characteristics (V cC=SV±lO%, ra=O to +70°C, unless otherwise noted.)
Read Cycle
Item

Symbol

Read Cycle Time

tRC

Address Access Time
Chip Select Access Time

tAA

Chip Selection to Output In Low Z

tCLZ··

max

HM6789H·20
min
max

15
IS

tACS
tOE

Output Enable to Output In Low Z

tOLZ··

Chip Deselectlon to Output in HIJh Z

tCHZ·'
tOH

3
0
3
0

20

ns

20

ns
ns

12

3
0

12

6

3
0

8

nl
nl

3

3

Unit
ns

20

IS

Output Enable to Output Valid

Output Hold from Address Chanae

HM6789H·lS
min

ns
nl

Write Cycle
Item
Write Cycle Time

Symbol

HM6789H·lS
min
max

HM6789H·20
min

max

Unit

IS

20

ns

10
0

15
0

ns

10

15

ns

10

15

nl

Chip Selection to End of Write

twc
tew

Addr.ss Setup Time

tAS

Address VaUd to End of Write
Write Pulae Width

tAw
twp

Write Recovery Time

tWR

Write to Output In Hish Z

tWHZ··

0

Data Valid to·End of Write

tow

9

10

ns

Data Hold Time

tOH
tOHZ·1

0
0

0
0

ns

Output Disable to Output in High Z
Output Active from End of Write

nl

nl

0

6

6

tOW·1
Note) .1. Transition is measured :l:200mV from steady state voltllle with Load (B).
This parameter is sampled and not 100% tested.

$

0

0

8

8

nl

n.
nl

HITACHI

100 Hitachi America,. Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

----------------------------------------------------------------HM6789H S.ies
Timing Waveform
R..d Cycl.11,"
loe

Address

Data Out

Read Cycl. 12"', '2, '3

loe

Address
I ..

10.

Data Out

D... Vllid

Previolls Data Valid

Read Cycl. 13"" '3, '4

IHe

I",

Ie",

feu

Data Out

D... Vllid
Hilh Impedanee

Notes) 01. WE =VIH
*2. CS= VIL
*3. O!. VIL
04. Address valid prior to or coincident with CS transition Low .

•

HITACHI

Hitachi America, ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 101

HM6789H

8.1_-------------------------------------------------------------

Write Cycl. (1)

(OE =H. WE Controlled)

Address

_~_

~

-----1_""
Ie.

CS
I ••
I ..

,.,..1

WE
I ••

Data In

Dota Volid

nata Out

Write Cycl. (2)

cor - H. a Controlled)
I""

Address
I ..

WE

'"
Data In

!Iota VIIW

Data Out

•

HITACHI

102 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

----------------------------------------------------------HM6789H

S.~

Write Cycle(3)IOE ~ Clocbd,WE Controlled)
t ••

Address

-

OE

\V
/1\

\V

/1\

IIIIV7

\1\\ \

J

teo

Cs

\\\1\ \\

t ..

t.,..l

\\l\

WE

/

1/
10",.2

'OMI*Z

\J

Data Out

V-

Hioh ............

~

.11
t ••

Data In

Write Cycle (4)

High Impedance

\

;'111VIII/

tA.

t~

\

XII
jf\

D... Valid

t ..

\VX
/1\

High Impedance

(lSI - Clocked, Ci Controlled)

Address

t ••

Data In

Data Out

Dato Valid

Hioh ..........""

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 103

HM6789H

s... --------------------------------------------------------

Write Cyale 15) liSE • L, Vir CDII1I'oIled)
toe

Address
Ie.

10.

HiP I........

Data Out

I ••

.5

High Impedance

Data In

Write Cycle 18) Iii!' - L,

I ..

High Impedance

D... Valid

crControlled)

Address

WE

Data Out

High Impedance

Data In

Data Valid

Notes)· 1. A write occurs during the overlap (twp) of a low CS and a low ~.
*2. During this period, 1(0 pins are in the output state so that the input signals of opposite phase to the outputs
must not be applied.
• 3. Data Out is the same phase of write data of this write cycle.
·4. If theCS is low transition occurs after the WE low transition, output remain in a high impedance state.
• S. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to
the outputs must not be applied to them.
·6. If CS low transition occurs simultaneously with the
high transition or after the OE transition, output remain
in hi&h impedance state.

E)
• FEATURES
• Super Fast
Access Time ....................Add. 12115/20ns (max.)
c:5E 6/7/8ns (max.)
• Low Power Dissipation
(DC) Operating ..........................300mW (typ.)
• + 5V Single Supply
• Completely Static Memory
No Clock or Timing Strobe Required
• Fully TTL Compatible Input and Output

(DP-24NC)

• ORDERING INFORMATION
Access Time

Package

HM6789HAP-12
HM6789HAP-15
HM6789HAP-20

Type No.

12ns
15ns
20ns

300 mil 24 pin
Plastic DIP
(DP-24NC)

HM6789HAJP-12
HM6789HAJP-15
HM6789HAJP-20

12ns
15ns
20ns

300 mil 24 pin
Plastic SOJ
(CP-24D)

• BLOCK DIAGRAM
A8o---~~r-----'

r------------,-OVre

~

-o~

A. o-----l
Row
A5O-----~~ ~
A.o-----;A-.!
As 0-----;

Memory Matrix

(CP-24D)

• PIN ARRANGEMENT

Vee

Ao
AI

A13
A12
All
AIO
As

A2
Aa
AI,

128 X 512

As

o---~====! ~===~

A2
110, o---_-I~__I
1102 o---.-H-I~__I
IlOs o--.++I-1~__I

___

lI04~tmi?1_--.J

As
A7

NC

As
CS

1/01
1/02
1/03

~

1/04

VSS

WE
(lbp View)

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 105

HM6789HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Symbol

Rating

Voltage on Any Pin Relative to V SS

VT

-0.5 to +7.0

V

Power Dissipation

PT

1.0

W

Topr

Oto +70

°C

T st2(bi.s)
T stg

-10 to +S5

°C

-55 to +125

°C

Item

Operating Temperature Range
Storage Temperature Range (with bias)
Storage Temperature Range

Unit

• RECOMMENDED DC OPERATING CONDITIONS (O°C :5 T. :5 70°C)
Symbol

Min.

Typ.

Max.

Unit

Vee

4.5

5.0

5.5

V

0.0

0.0

0.0

V

Input High Voltage

Vss
VIH

2.2

6.0

V

Input Low Voltage

VIL*

-3.0

-

O.S

V

Item
Supply Voltage

*Pu]se width

S

IOns. DC: -O.5V

• TRUTH TABLE
CS

OE

WE

Mode

Vee Current

I/O Pin

Ref. Cycle

H

H orL

H orL

Not Selected

19B , ISBI

HighZ

-

L

H

H

Output Disabled

icC!

HighZ

-

L

L

H

Read

Icc, Icel

Data Out

Read Cycle (1) (2) (3)

L

H

L

lee,leel

Data In

Write Cycle (1) (2) (3) (4)

L

L

L

lee,leel

Data In

Write Cycle (5) (6)

Icc,

Write

• DC AND OPERATING CHARACTERISTICS (Vee
Item

= 5V

=10%, T. = O°C to 70°C, Vss = OV)

Symbol

Test Condition

Min.

Typ.

Max.

Unit

Input Leakage Current

IILlI

-

2

p.A

Output Leakage Current

IILOI

= 5.5V, VIN = Vss to Vee
CS = VIH or OE = VIH , WE = V IL
Vila = Vss to Vee
CS = V1L , 1110, = OrnA
Min. Cycle, Duty: 100%, 1110 = OrnA
CS = V1H

-

-

10

p.A

100

rnA

-

120

rnA

-

-

30

rnA

-

-

10

rnA

-

-

0.4

V

2.4

-

-

V

Operating Power Supply Current

Icc

Average Operating Current

icC!
ISB

Standby Power Supply Current
ISBI
Output Low Voltage

VOL
VOH

Output High Voltage

Vee

CS ;:: Vee - 0.2V
VIN :5 0.2Vor VIN ;:: Vee - 0.2V
10L
10H

= SmA
= -4rnA

-

• AC TEST CONDITIONS
• Input Pulse Levels: Vss to 3.0V
• Input and Output Reference Levels: 1.5V
200mV from steady level (Output Load B)

• Input Rise and Fall Time: 4ns
• Output Load: See Figure

=

+5V

+5V

DOU~

DOU~ 4800

4800

2550 L j5 PF

2550 L j 3 0 pF 0

O

Output Load B
(for IcHZ.IcLZ. 10HZ. Iou. twz & low)

Output Load A
*Including scope and jig capacitance.

$

HITACHI

106 Hitachi America. Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - HM6789HA Series
• TIMING WAVEFORM
• Read Cycle (1) (1)

Address

OE

cs
tCLZ

Data Out

Data Valid

High Impedance

• Read Cycle (2) (1)(2)(3)
RC

)K

Address

tAA
tOH

Data Out

)K

...

tOH

XXX) K

Previous Data Valid

X

Data Valid

• Read Cycle (3) (1) (3) (4)
tRC

cs

'\

K.

/

It'
tCHZ

tACS
~

tCLl

Data Out

NOTES:

KX>OK

Highimpedance

1.
2.
3.
4.

Data Valid

"-

/

WE = VIH
CS = VIL
OE = VIL
Address valid prior to or coincident with CS transition low.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 107

HM6789HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • CAPACITANCE (Ta = 25°C, f = 1.0MHz)

Item
Input Capacitance
Input/Output Capacitance
NOTE:

Symbol
CIN

Test Conditions
VIN = OV
VI/O = OV

CliO

Min.

Typ.

-

-

Max.
6
10

Unit
pF
pF

This parameter is sampled and not 100% tested .

• AC CHARACTERISTICS (Vcc = 5V ± 10%, Ta = O°C to 70°C, unless otherwise noted.)
• Read Cycle

Item

Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Selection to Output in Low Z
Output Enable to Output Valid
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Hold from Address Change

tRC
tAA
tACS
tCLZ

toE
tOLZ
leHZ
tOH

HM6789HA-12 HM6789HA-15 HM6789HA-20
Min.
Max.
Max.
Min.
Min. Max.
12
15
20
12
15
20
15
12
20
3
5
5
6
7
0
0
0
8
2
2
2
0
6
0
6
0
8
4
4
4

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns

1,2
1
1,2
1,2

-

• Write Cycle

Item
Write Cycle Time
Chip Selection to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data Valid to End of Write
Data Hold Time
Output Disable to Output in High Z
Output Active from End of Write
NOTES:

Symbol
twc
lew
tAS
tAW
twp
tWR
tWHZ
tDW
tDH
tOHZ
tow

HM6789HA-12 HM6789HA-15 HM6789HA-20
Min.
Max. Min.
Min.
Max.
Max.
12
15
20
8
10
15
0
0
0
10
15
8
10
8
15
0
0
0
6
0
6
0
8
0
7
10
6
0
0
0
1
6
1
6
1
8
3
3
3

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

-

I. Transition is measured ±200mV from steady state voltage with Load B.

2. This parameter is sampled and not 100% tested.

~HITACHI
108 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

-

1,2

1,2
1,2

- - - - - - - - - - - - - - - - - - - - - - - - - - - HM6789HA Series
• Write Cycle (1)

(OE

= H, WE Controlled)
twc

Address
tew

cs
twp(l)

WE
tow

Data In

tOH

Data Valid
High Impedance

Data Out

• Write Cycle (2)

(OE = H, ~ Controlled)

twc
Address
tew

cs
tWP(l)

WE

tow
Data In

Data Valid
High Impedance

Data Out

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 109

HM6789HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - • Write Cycle (3)

(OE = Clocked, WE Controlled)
twe

Address

OE
tew

cs
twp(1)

WE
tOLZ(2

High Impedance

Data Out

tow

Data In

tOH

...!:!H~i9!!!h..!!lm~p~e~d~a~nc~e:....__ _ _ _/\~--------slz\7'High ImpedancE:

• Write Cycle (4)

(aE = Clocked, CS Controlled)
twe

Address

OE
tew

cs
tWR

twp(1)

WE

Data In
Data Out

•

HITACHI

110 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6789HA Series
• Write Cycle (5)

(OE

= L, WE Controlled)

Address

cs
twp

(1)

WE
(2)

tOH

tow
High Impedance 14-='-Jo..l ,----...

Data Out

(3)

tDW

Data In

High Impedance

Data Valid

•

tDH
(5) High

Impedance

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 111

HM6789HA Serlea - - - - - - - - - - - - - - - - - - - - - - - - - - • Write Cycle (6)

('OE = L. ~ Controlled)

f
- ~: - - two

Address

cs

..

t"'".'

WE
High Impedance

Data Out

tow

Data In

NOTES:

High Impedance

tOH

Data Valid

1. A write occurs during the overlap (twp) ofa low CS and a low WE.
2. During this period, 110 pins are in the output state so that the input signals of opposite phaae to the outputs must not
be applied.
3. Dour is the same phase of write data of this write cycle.
4. If the CS low transition occurs after the WE low transition, output remain in a high impedance state.
S. If CS is low during this period, 1/0 pins are in the output state. Then, the data input signals of opposite phaae 10 the
outputs must not he applied 10 them.
6. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in
high impedance state.

$

HITACHI

11 2 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

HM6287 Series
65536·word x '·bit High Speed CMOS Static RAM

Maintenance Only
Refer to HM6287H Series

• FEATURES
•
•
•

High Speed: Fast Access Time 45/55/70ns (max.)
Single 5V Supply and High Density 22 Pin Package
Low Power Standby and Low Power Operation
Standby: 100",W (typ.)/10",W (typ.) (L·version)
Operation: 300mW (typ.)
• Completely Static Memory
No Clock or Timing Strobe Required
• Equal Access and Cycle Times
• Directly TTL Compatible: All Inputs and Output
• Capability of Battery Back Up Operation (L·version)

(DP·22N)
• PIN ARRANGEMENT

• ORDERING INFORMATION
Type No.
Access Time
HM6287P-4S
HM6287P·SS
HM6287P·70
HM6287LP-4S
HM6287LP·SS
HM6287LP·70

4Sns
SSns
70ns
4Sns
SSns
70ns

Package

300 mU22 pin
Plastic DIP

• BLOCK DIAGRAM
A.
A,
A"

Ro.

A"
A"
A"
A"

D••

nIV("

•

HITACHI

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 113

I

HM8287 Serl•• - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• TRUTH TABLE
CS

WE

Mode

H

X

Not Selected

L

H

Read

L

L

Write

Ref. Cycle

DoutPin

Vee Current

High Z

-

Icc

Dout

Read Cycle

Icc

High Z

Write Cycle

ISB,ISBI

• ABSOLUTE MAXIMUM RATINGS
Symbol

Item

Unit

Ratina

Voltage on Any Pin Relative to VSS

VT

-0.5·· to +7.0

V

Power Dissipation

PT

1.0

W

Operating Temperature

Topr
Tit,
TW.

o to +70

·C

-55 to +125
-10 to +S5

·C

Storage Temperature
Temperature Under Bias

·C

Note) *1. -3.SV for pulse width;;i! 20ns

=0 to +70°C)

• RECOMMENDED DC OPERATING CONDITIONS (T/I
Symbol

min

typ

max

Unit

Vee

4.5

5.0

5.5

V

YSS

0

0

0

V

VIH

2.2

6.0

V

VIL

-0.5··

O.S

V

Item
Supply Voltage
Input Voltage

-

Note) *1. -3.0V for pulse width ;;i! 20ns

• DC AND OPERATING CHARACTERISTICS (Vee = SV ± 10%, Vss = OV, Til = 0 to +70°C)
Item
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby Power Supply Current

I/u l
11£0 1

Vee = S.SV, Vin

-

= VIH, Vout = Vssto Vee
= VIL, lout =OmA, min. cycle
= VIH, min. cycle

ISB

CS
CS
CS

ISB1

CS ~ VCc-o.2V,
OV S; Vin ;§; 0.2V or Vee - 0.2V ;§; Vin

lee

min typ·· max
- 2.0
2.0
100
60
10
30
- 0.02 2.0
- 2.2 100.2

Test Conditions
= Vssto Vee

Symbol

-

10L = SmA
VOL
Output Voltage
10H= -4.0mA
VOH
Notes) ••• Typical bmlts are at VCC- S.OV, TII - 2S 0 C and speCIfied loadlnll·
.2. This characteristics is luaranteed only for L·veraion.

-

2.4

-

-

Unit
/loA
/loA
mA
mA
mA

/loA
V
V

0.4

-

• CAPACITANCE (f= IMHz, Til =2S0C)
Unit

Symbol

Test Conditions

min

typ

max

Input Capacitance

c'n

V'n=OV

-

5

pF

Output Capacitance

Cout

Vout=OV

-

-

7.5

pF

Item

Note) This parameter is sampled and not 100% tested.

$

HITACHI

114 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94Q05-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 8 2 8 7 Seri..

• AC CHARACTERISTICS (Vee =SV ±lO%, Ta

=0 to +70°C, unless otherwise noted)

• AC TEST CONDITIONS
Input Pulse Levels: Vss to 3.0V
Input Rise and Fall Times: 5ns
Input and Output Timing Reference Levels: 1.5V
Output Load: See Figure
Output Load B

Output Lo.d A
5V

.aoll

48011

.

00., 0---,.....--+

DOllt

2SS11

30.F

25S11

:q
SV

S.F·

$Includin, leope II: iii c.pacitance

• READ CYCLE
Item

Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output in Low Z
Chip Deselectlon to Output iii High Z
Chip Selection to Power Up Time
Chip Deselection to Power Down Time

tRC
tAA
tAC!
tOH
tLZ
tHZ
tpu
tPD

HM628HS
max
min
45
45
45
5
5
0
30
0
40

-

-

-

-

-

HM6287·55
min
max
55
55
55
5
5
0
30
0
40

-

-

-

-

HM6287·70
min
max
70
70
70
5
5
30
0
0
40

-

-

-

-

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns

1

2,3,7
2,3,7
7

7

• Timing Waveform of Read Cycle No.1 (4)(5)

..

F~--------,.(·---------o}_-i

Add ....

DoUI

=t-,,,.--'t-",
.
Dala Valid

• Timing Waveform of Read Cycle No. 2(4)(6)

DOUI

"'''J

Vee supply'I(x
- - • - - • - - _:- --,-,- - - - - - - - - - - current
_
50 '1
hll

Notes:

I. All Read Cycle timings are referenced from last valid address to the first transitioning address.
2. At any given temperature and voltage condition. tHZ max. is less than tLZ min. both for a given device
and from device to device.
3. Transition is measured tSOO mV from steady slate voltage with specified loading in Load B.
4. WE is high for READ Cycle.
S. Device is continuously selected, while CS = VIL.
6. Address valid prior to or coin.cidenl with CS transition low.
7. This parameter is sampled and nol 100% tasted .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 11 5

HMe287S~------------------------------------------------------------

• WRITE CYCLE
Symbol

Item
Write Cycle Time
Chip Selection to End of Write
Address Vatid to End of Write
AclcIress Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enabled to Output in High Z
Output Active from End of Write

HM628745
max
min
45
40
40
0
25
0
2S
0
0
25
0

HM6287·55
min
max
55
50
50
0
35
0
2S
0
0
25
0

-

twe
tew
tAW
lAS
twp
tWR
tDW
tDH
twz
tow

-

-

-

-

-

-

-

HM6287·70
min
max
70
55
55
0
40
0
30
0
0
30
0
-

-

-

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

2

• Timing Waveform of Writa Cycle No.1 (WE Controlled)
Itt'"

Addre••
leM'

\

-,.,-

Itu'

\\\

.1:::.'

Din

Dou.

-, ... -

tA'"

U'I" _ _

_ ~/)H

)l(Do.a in Valid)l(

i:--

-"1"-::1

'tllr

High Impedance

Da.a Undefined

• Timing Waveform of Write Cycle No.1 (CS Controlled)

..

''''C

,

"1

tA~__

It'It'

'\

.'---t.,.

1--""~Lu",

Din
Dout

Notes) I.
2.
3.
4.

.I,uH

X Da.. in Valid l(
1---'." :;J--J HiRh Impedance
(______
0 ... Undefined

If ~ goes high Simultaneously with W1i high, the output remains in a high impedance state.
All Write Cycle timings afe refefenced from the last vaUd address to the first transitioning address.
Transition is measured tSoomV from steady state voltage with specified loading in Load B.
This parameter is sampled and not 100% tested .

•

HITACHI

116 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

3,4
3,4

--------------------------------------------------------------HM8287 Sen.
• LOW Vee DATA RETENTION CHARACTERISTICS (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Test Condition

min.

typo

max.

~ VfP-&iV'or
Vif 2: CC-·

2.0

-

-

Unit
V

-

I

50*2

/l A

See retention waveform

0

-

-

-

-

ns
ns

Symbol

Parameter

VCC for Data Retention

VDR
lCCDR
tCDR
tR

Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Note) *1. tRC a Read Cycle Time

CS

o

::;-Vin :5:0.2V

tRC 1

*2. VCC=3.0V

•

LOW Vee DATA RETENTION WAVEFORM
Oal& Retention

Mode

vcc------"""\I

4.SV_________ --- -- ---- ----- - - -- - -- - ---

CS.. Vee -o.zv

Cs _ _ __
w ____________________________________________ _

SUPPLY CURRENT VI. SUPPLY VOLTAGE

SUPPLY CURRENT VI. AMBIENT TEMPERATURE
1.6

1.6

vcc-s.ov

r.=2S·C
1.4

j

0.8

1

~

~

~

1

~

1.2

4.75

5.0

1.0

j

0.8

j

0.6

--

f--

j

0.6

0.4
4.5

1;

5.25

5.5

20

40

60

80

Ambient Temperature Ta ('C)

Supply Voltale Vee (V)

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 117

HM8287Seri.. ------------------------------------------------------------

ACCESS TIME VL SUPPLY VOLTAGE

--r--

----

~ D.9

J

0.8

0.7

4.5

5.0

4.75

ACCESS TIME VI. AMBIENT TEMPERATURE

5.25

J

1.0

~

1

--"

~

j

D.9r-----t-----t-----t-----;

J o,gr-----t-----r-----t---~

5.5
Ambtent Temper.ture T.

Su••" Voltop Vee (V)

STANDBY CURRENT v•.
SUPPLY VOLTAGE

I.2

8

6

0.

STANDBY CURRENT VI.
AMBIENT TEMPERATURE

/

0

4~

V

/

rOc)

10

/

!£c=3V
CS=2.8V

/
,

V

T.=2S'C
~tV",-0.2V

L

V

,/'

.

0.2

Ambient T............ T. ('C)

S...... Vol.... Vee (V)

STANDBY CURRENT VL
INPUT VOLTAGE

SUPPLY CURRENT WI.
FREQUENCY
T( ..)

100

200

1.1

50

66

10

Ta=25'\:
Vee=5.0V

./

/';1"

/'

J

~

-

8
6

j

/

7

/
0.5 0

B=uv

2

10

15

c, I (MH.)

20

0

25

F.......

$

\

\

i'"

.........

HITACHI

11 8 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 8 2 8 7 Seri..
INPUT LOW VOLTAGE
SUPPLY VOLTAGE

INPUT HIGH VOLTAGEVI.
SUPPLY VOLTAGE

VI.

1.3

1.3

r.=25'C

r.=25·C

!

1.0

.s

0.9

J

G.8

-------

0.7
4.5

5.0

4.75

s...., Vol....

---0.7

5.5

5.25

4.5

5.25

5.0

4.75

s....., Vo!toae

Vee (V)

OUTPUT HIGH CURRENT VI.
OUTPUT HIGH VOLTAGE

5.5

Vee (V)

OUTPUT LOW CURRENT VI.
OUTPUT LOW VOLTAGE
1.6

3.0

T.=25*C
Vee=5V

\

2

\

\
1

j

4

\

o

----

~

~

0

\

/

/

/
V
r.=25'C
V.. =5V

V

\

0.4

Output HioIh V...... V.. (V)

o
0..... Low Vo!toae V"" (V)

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 11 9

HM6287H Series
65536-Word x 1-81t High Speed CMOS Static RAM
The Hitachi HM6287H is a high speed 64K static RAM organized
as 64·kword x 1·bit. It realizes high speed access time (25135 ns) and
low power consumption, employing CMOS process technology and
high speed circuit designing technology. It is most advantageous for
the field where high speed and high density memory is required,
such as the cache memory for main frame or 32·bii MPU. The
HM6287H packaged in a 300·mil plastic DIP and SOJ, is available
for high density mounting.
Low power version retains the data with battery back up.

Features
Single 5 V supply and high density 22·pin DIP and 24·pin SOJ
High speed: Fast access time 25/35 ns (max)
Low power
Operation: 300 mW (typ)
Standby: 100 I1W (typ)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TIL compatible: All inputs and outputs

Pin Arrangement

HM6287HP Series

(DP-22NB)
HM6287HIP Series

(CP-24D)

Pin Description
HM6287HJP Series

HM6287HP Series

AO
Al
A2
A3
A4
A5
A6
A7

Vee
Al5
Al4
Al3
Al2
All
AIO
A9

D~
V..

§M'

AS

'-----'

AO
Al
A2
A3
A4
A5
NC
A6
A7

Vee
Al5
Al4
Al3
Al2
NC
All
AIO
A9

D~~
V..

Pin Name
AO-A15
Din
Dout
WE

Vee
Vss

Function
Address
Input
Output
Chip select
Write enable
.Power supply
Ground

~~n

L.;.;;;.._~

ES

(Top View)

(Top View)

Ordering Information
Type No.
HM6287HP·25
HM6287HP-35
HM6287HLP-25
HM6287HLP-35
HM6287HIP-25
HM6287HJP-35
HM6287HUP-25
HM6287HLJP-35

Access Time
25ns
35 ns
25ns
35ns
25 ns
35ns
25ns
35ns

Package
300-mil
22-pin
plastic DIP
(DP-22NB)
300-mil
24-pin SOJ
(CP-24D)

.HITACHI
120 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 7 H Series

Block diagram
AD
Al

-Vee

AZ

-VIS

A3

Row

Memory Array

Decoder

128XSIZ

A4
AS
A6

L-~"""-Dout

Din

CS"

WE

Function Table
CS
H
L
L
Note:

WE

x
H
L

Mode
Standby
Read
Write

VccCurrent
IsR. IsRI
Icc
Icc

DOII,Pin
High-Z

Symbol
VT
PT
Topr
Tstg
Tbias

Value
-0.5'1 to +7.0
1.0
o to +70
-55 to +125
-10 to +85

~,

High-Z

Ref. Cycle
Read cycle 1.2
Write cycle 1.2

x:HorL

Absolute Maximum Ratings
Item
Voltage on any pin relative to Vss
Power dissipation
Operating temperature
Storage temperature
Storage temperature under bias
Note: .1. VT min =-2.0 V for pulse width S 10 ns

Unit
V
W
·C
·C
·C

Recommended DC Operating Conditions (Ta =0 to + 70°C)
Item

Symbol
Vcc
Supply voltage
Vss
Input high (logic I) voltage
VIII
Input low (logic 0) voltage
VII.
Note: .1. VII. min = -2.0 V for pulse width S IOns

Min
4.5
0
2.2
-0.5'1

•

Typ
5.0
0

Max
5.5
0
6.0
0.8

Unit
V
V
V
V

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 21

HM6287H Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

DC Characteristics (T8 =0 to +70°C, Vee =5 V ± 10%, Vss =0 V )
Item
Input leakage current

Symbol
I ILl I

Typ'l

Min

Max
2.0

Unit
Il A

2.0

I1A

Output leakage current

IILo I

Operating Vee current

Ice

60

120

rnA

Standby Vee current

ISB

15
0.02

30
2.0

rnA
rnA

Standby Vee current (1)

ISB!

Test Conditions
Vee = Max
Yin = Vss to Vee
CS =VOl
Vvo = Vss to Vee
CS =V0..
... _ 1 \ _ A

T~
.l.VU~

0.1'2
0.02'2
Output low voltage
VOL
0.4
Output high voltage
VOH
2.4
Notes: *\. Typical limits are at Vee = 5.0 V, Ta = 25°e and specified loading.
*2. This characteristics is guaranteed only for L-verslOn.

rnA
V
V

-

v

_!_

IlIn, 111111

- ..... 1 ...
"'y..."
....

CS = Vnt, min cycle
Cs ~ Vee- 0.2 V
oV ::; Yin ::; 0.2V or
Vee-0.2V::;Vin
1m. = 8 rnA
JOII = -4.0 rnA
--- -"------"-- -,. __ ._ ..

_-

Capacitance ( T8 = 25°C, f = 1.0 MHz )'!
Symbol
Item
Min
Input capacitance
Cin
Output capacitance
Cout
Note: *1. This parameter is sampled and not 100% tested.

Ty~_ _ _ _
M--:-a_x.

Unit
Test Conditions
--p-=F=---- Yin =0 V

6
8

pF

Yout= 0 Y

AC Characteristics ( T8 =0 to +70°C, Vee =5 V ± 10%, unless otherwise noted. )
Test Conditions
• Input pulse levels: Vss to 3.0V
• Input and Output timing reference levels: 1.5 V
• Input rise and fall times: 5 ns
• Output load: See figures
Output Load (A)

Output Load (B)

(for OI7~ t1.7, twz & tow)

+5V

410g

00"

~
USQ

Note:

00"
lOp"'*

~
2SSg

MOg
hF'

Including scope & jig

•

HITACHI

122 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300

HM6287H Series

Read Cycle
Symbol

Item
Read cycle time
Address access time
Chip select access time
Output hold from address change
Chip selection to output in low-Z
Chip deselection to output in high-Z
Chip selection to power up time
Chip deselection to power down time

IRc
lAA
lAcs

toH
lLZ' l
lHZ' l
lPU

lPD

HM6287H-25
Min
Max
25
25
25
3
5
0
12
0
25

HM6287H-35
Min
Max
35
35
35
5
5
0
20
0
30

Unit
ns
ns

ns
ns
ns
ns
ns
ns

Read Timing Waveform (1) '2, ·3.·S

Addr...

I. .

Dou.

PreviOVI
o..ta V.lid

Data Valid

Read Timing Waveform (2)'2,"
II

lASS

IU

Uall

It<

Vc(

5.,,1, CtI".' - - - - - - - - - - T.,.~.

Notes: *1.
*2.
*3.
*4.
*5.

V,lId

I"

\r-----------------V-

_ _ _ _ _-J. SO"

Transition is measured ±200 mV from steady state voltage wilh Load (8). This parameter is sampled and not 100 % tested.
WE is high for read cycle.
Device is continuously selected, CS Vn-.
Address valid prior to or coincident wilh CS transition low.
All read cycle timing are referenced from last valid address to Ihe first transitioning address .

=

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 123

HM6287H Serl••

WrlteCycle
Item
Write cycle time
Chip selection to end of write
Address valid to end of write
Address setup time

Symbol
twc

tcw
lAw
lAs

Writ.. mil ... width

tw~

Write recovery time
Data valid to end of write
Data hold time
Write enabled to output in high-Z
Output active from end of write

twR

----

£~---

.

-----

!Dw
!DH
twz· 1
tow· I

HM6287H-25
Min
Max
25
20
20
0
20
0
15
0
0
8
5

HM6287H-35
Min
Max
35
30
30
0
30
0
20
0
0
10
5

Unit
ns
ns
ns
ns
n!

ns
ns
ns
ns
ns

Write Timing Waveform (1) (WE controlled)

Address

Din

Dout

$

HITACHI

124 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 7 H Series

Write TImIng Waveform (2) (CS Controlled)
twe

Address

tew

Din
High Impedance"

Dout

Transition is measured ±200 mV from steady state volta~th Load (8). This parameter is sampled and nOl 100% tested.
A write occurs during the overlap of a low CS and a low WE (two)
twa is measured from the earlier of CS or WE going h~to the end of write cycle.
If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain
in • high impedance state.
*5. Dout is the same phase of write data of this write cycle, if twa is long enough.

Notes: *1.
*2.
*3.
*4.

Low Vee Data RetentIon CharacterIstIcs ( Ta = 0 to +70°C)
(This specification is guaranteed only for L-version.)
Item
Vee for data retention

Symbol
VDR

Min
2.0

Typ

Max

V

50'2
35'3

Data retention current

Chip deselect to data retention time

!cDR

Operation recovery time

IR

Unit

0

~A

Vin~Vcc-O.2Vor

o V :s Yin :s 0.2 V
ns
ns

IRC'I

Test Condition
cr~Vee-O.2 V

See retention waveform

=

Notes: *1. lac Read cycle time
*2. Vee =3.0 V
*3. Vee = 2.0 V

Low Vee Data Retention TImIng Waveform
Data Retention Mode
Vee

YD.
CS01;V D.-O.2V

~-----------------------------------

$

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 125

HM6287H Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Supply Current VI. Supply Voltage

----

Supply Current

v--- ---

Ambient Temperature

- --

r--

>.

1

VS.

t---

0.6

Vl

0.4

4.5

5.0

4.75

5.25

5.5

Access Time

Access Time

Supply Voltage

VS.

];

I

_1.1

0.9

~ 0.8

0.7

4.5

1.6

~

1.4

'"
~

.(

/'

1.2

.:s

"e

f=
'"'"~

---r-

f=

]

1.0

~

<

4.75

5.0

0.6

5.5

5.25

o

50

Supply Current

Vcc =5.0V

f=

~

]

0.8

100

1.1

1----

---

..--

---

100

150

200

Load Capacitance CL (pF)

13

0.9

/~

0.8

Access Time VI. Ambient Temperature

~

~

u

Supply Voltage Vee (V)

e"

Load Capacitance

§

=-{-- -- ---

~

.
.~

Z~_ rt~
"e

VS.

"0
'"'

Ta=25'C

•~ 1.2

1.0

80

60

1.8

13

g

40

20

Ambient Temperature Ta (0C)

Supply Voltage Vee (V)

.....

"0
'"'
i:l

1.0

~

09

50

~
]

U

0.7

>.

1

-

25

20 T (ns)

/
/'

0.8

~"

Frequency

33

/

~

-

VS.

""

/

V

V

0.6

Vl

o. 7

20

40

60

80

10

20

30

40

50

Frequency f (MHz)

Ambient Temperature Ta (0C)

.HITACHI
1 26 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 7 H Series
Input Low Voltage va. Supply Voltage

Input High Voltage

1.3

]

1

:t;'

:.;

1.2

.
>
II

~

~

1.0

I----

-

~

1.3

l---

To=25'C
1.2

E
0
6

1.1

>II

1.0

;;;

OIl

!'l

"0

>
..c:

0.9

j

0.9

~

---

~

V-

.e!l

w

5.

.5

::c

0.8

~

0.7
4.5

0.8

oS
4.75

5.0

5.25

5.5

4.75

Supply Voltage Vee (V)

5.0

5.25

5.5

Supply Voltage Vee (V)

Output Current VB. Output Voltage 111

Output Current

VS.

Output Voltage 121

1.6

]

To=25'C
Vcc=5V

;.; 1.4

11.

~

11.0

\

U O. S

~':I

\

0.6

/

\

So

8

T8=25'C
Vcc=5V

,

2

~

o. 4 1

2

3

4

0.2

Standby Current va. Ambient Temperature

1

V
/'

~

]

1.0

~

5~
o.

f

11

V

~

1.2

O

1.0

1

iii O.S

!

~
I@

40

/

~

0.6

60

0

SO

Ambient Temperature Ta (OC)

J

//

0.4

(I)

20

O.S

/
V

6

B o.2

o. 1
o

0.6

1.4

Vcc=3V
CS=2.SV
5

0.4

Standby Current va. Supply Voltage

10

]

L

/

/
V

Output Low Voltage VOL (V)

Output High Voltage VOH (V)

(I)

Supply Voltage

I:!

To=25'C

~ 1. 1

VB.

~

V

T8=25'C
cS=icc-O.2V-

345

6

Supply Voltage Vee (V)

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point.Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 127

HM&~HSar•• ----------------------------------------------------Standby Current va. Input VoIta"e
10

Ta=2S't
Vcc=S.OV
C§=4.8V _

J\

)
o

" 1\
2

~

3

4

5

6

Input Voltqe Vin (V)

•

HITACHI

128 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM6787 Series

Maintenance Only
Refer to HM6787HA Series

65536-word x '·bit High Speed Hi·BiCMOS Static RAM
• FEATURES
•
•
•
•
•
•
•
•

HM6787P Series

Super Fast Access Time: 25ns/30ns (max.)
Low Power Dissipation (DC):
Operating 180mW (typ)
High Driving Capability: IOL 16mA
+5V Single Supply
Completely Static Memory
No Clock or Timing Strobe Required
Balanced Read and Write Cycle Time
Fully TTL Compatible Input and Output
Skinny 22'pin Plastic Dip (300 mil) and 22-pin Chip Carrier

(DP-22NB)

• ORDERING INFORMATION
Type No.

Access Time

HM6787P-25
HM6787P-30

2Sns
30ns

Package
300 mil 22 pin
Plastic DIP

• PIN ARRANGEMENT
•

HM6787P Series

• BLOCK DIAGRAM

AIO<>---AII 0--- --ti=AISc>-~

Row
Decoder

--0

Vee

--0

Vss

Memory Matrix

128XSI2

,--I-__

C_O_lu_m_n_1/0
_ _-----1

~~

Cso~

WEe>-

~_

Doul

AS A7 A8 A2 A3 A4 AS AO AI
--------- - - - -

(Top View)

.ABSOLUTE MAXIMUM RATINGS
Item
Terminal Voltage to VSS Pin
Power Dissipation
Operati", Temperature Range
Storage Temperature RanKe

Symbol

VT
PT
Top,
TSIg

Rati",
-0.5 to +7.0
1.0
o to +70
-55 to +125

Unit
V
W

·c
C

.HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 129

I

HM8787Senn-----------------------------------------------------------• TRUTH TABLE
Output Pin

CS

WE

Mode

H

Not Selected

L

X
H

Read

lee

Dout

L

L

Write

lee

HighZ

Vee Current

min.

typo

max.

Unit

Vee

4.5

5.0

S.S

V

VSS

0

0

0

V

6.0

V

0.8

V

Symbol

Item
Supply Voltage
Input High Voltage

VIH

2.2

Input Low Voltage

VlL

-0.5"'

Note) "I. -3.0V for pulse width

~

HighZ

ISB.ISBJ

-

20n8.

• DC AND OPERATING CHARACTERISTICS (Vee = 5V±lO%, T.=O°Cto+70°C)
min.

typo

Input Leakage Current

IILl I

vee=s.sv. vlN-VSS to Vee

-

-

Output Leakage Current

11£01

~. V,H. VOUT= Vssto Vee

Operating Power Supply Current

lee

CS" V,L.1OUT"0mA

-

-

40

rnA
rnA

-

-

20

rnA

-

O.S

V

-

V

Item

Symbol

ISB

Standby Power Supply Current
ISBl

Output Low Voltage
Output High Voltage

Test Conditions

CS-V,H
CS~ Vee

-0.2V

VlN ~ 0.2V or VlN ~ Vee -0.2V

VOL

IOL-16mA

-

VOH

IOH=-4mA

2.4

• AC TEST CONDITIONS
Input pulse levels: Vss to 3.0V
Input rise and fall times: 4ns
Input timing reference levels: 1.5V
Output reference levels: 1.5V
Output load: See Figure

Out put Load A
+5V

(for

Unit
~A

2

2
100

Out put Load B
&
+5V

1HZ. ILZ. IWZ

48011

~A

lOW)

48011

Doulo--~-"",

Dout

25511

max.

0---.,..-.......
25511

• Including lCape and jig •

•

HITACHI

130 Hitachi America. ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300

HM6787 Series

• CAPACITANCE (Ta = 25°C,[= 1.0MHz)
Symbol

max

Unit

Input Capacitance

CIN

5.0

pF

VIN= OV

Output Capacitance

COUT

7.0

pF

VOUT=OV

Item

Conditions

Note) This parameter is sampled and not 100% tested.

• AC CHARACTERISTICS
•

(VCC= 5V±10%,

Ta =O°C to 70°C, unless otherwise noted.)

READ CYCLE

---------·-------r---------.·--H-M--6--78-7_-2S--r-- HM6787-30
Symbol
Item
min

•

max

Unit

Notes

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

2

WRITE CYCLE
Item
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write

Note: I.
2.
3.
4.

Symbol

twc
tcw
tAW
tAS
twp
tWR
tDW
tDB
twz
tow

HM6787·25
min.
max.
25
20
20
0
20
5
20
0
0
15
0
-

HM6787·30
.min.
max.
30
25
25
0
25
5
25
0
0
15
0
-

3,4
3,4

If CS goes high simultaneously with WE high, the output remains in a high impedance state.
AU Write Cycle timings are referenced from the last valid address to the first transitioning address.
Transition is measured ±200mV from steady state voltage with specified loading in Load B.
This parameter is sampled and not 100% tested.

~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94Q05·1819 • (415) 589·8300 131

HMI787s.m.----------------------------------------------___________
• TIMING WAVEFORM OF READ CYCLE NO. 11), 2)

Acldr...

__~I__----_'RC------*~-IAA

Data Out

Pre.iou. Data Val id

Data Valid

• TIMING WAVEFORM OF READ CYCLE NO. 21), 3)

lACS

ILZ

Data Out

Vcc Supply

Hip Impedanc.
Data Valid

Hip I"""".

--:------~~50%-------------------------~-~~~____

Current

Note: 1. WE II blah and Billow for READ cycle.
2. Addmael vaIicI prior to or coincident with B tranlition low.
3. Transition II measured :t200mV from steady ltate volta" with specifled loadilllin Load B.

$

HITACHI

132 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------------------IHM8787Seri..
• TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)
Iwe

Addr ...
lew

lAW
Iwp

loW

Data In

Data In Val id
IwZ

Data Out

Data Undefined

High Impedance

Note: 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

• TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)

Addr •••

Iwe

- ,"-

]~
lAS
lew

~I\.

J
tAW

two
twp

1/////

\. \. \. \. \. \. )~
low

)(

Data In

/OH

Data In Valid

~

j!\.

/wz

Olta Out

Data Undef ined

~

High Impedance

Note: 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

$HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 133

HM6787H Series

- - - - - - - - - Maintenance Only

86538-word x 1-bit High Speed Hi-BiCMOS Static RAM

Refer to HM6787HA Series

Features
• Super Fast Access Time: 15n5/20n5 (max.)
• Low Power Dissipation (DC):
Operating 210mW (typ)
• +5V Single Supply
• Compieteiy Static Memory
No Clock or Timing Strobe Required
• Balanced Read and Write Cycle Time
• Fully TTL Compatible Input and Output
(DP·22NB)

Ordering Information
Type No.

Access Time

HM6787HJP Series

Package

HM6787HP·lS
HM6787HP·20

lSns
20ns

300 mil 22 pin
Plastic DIP

HM6787HJP·lS
HM6787HJP·20

ISns
20ns

300 mil 24 pin
Plastic SOJ

Block Diagram
Vee

A.

--0

A,o--{-:O
A.o--{:O Row

A,

A. ~--,...

I

Decoder

--0

(CP·24D)

Vss

Memory Matrix
128X5l2

A,o--{XJ
A.

~~

I ::C==::;;;::;::::::::::;::;:;;;::::::::r~

Pin Arrangement
HM6787HP Series

HM6787HJP Series
AO
Al
A2

Vee
A15
A14

A3
A4

A13
A12

Ne
All
A10
A9
A8

A6
A7

Daul

WE

Din

V••

CS

(Top View)

•

Note)

The specifications of this device
are subject to change without
notice.
Please contact Hitachi's Sales
Dept. regarding specifications.

HITACHI

134 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

-------------------------------------------------------------HM6787H Swl_
Absolute Maximum Ratings
Item
Terminal Voltage to VSS Pin
Power Dissipation
Operatilll Temperature Range
Storage Temperature Range
Temperature under Bias

Symbol

Unit
V
W
·C
·C
·C

Ratilll
-0.5 to +7.0
1.0
oto +70
-S5 to +125
-10 to +8S

VT
PT
Top,
Tstg
Tblo.

Function Tabla
CS

WE

Mode

H

X

Not Selected

lsa.ISBI

Output Pin

L

H

Read

lee,leel

Hish Z
Dout

L

L

Write

lee.leel

High Z

Vee Current

Recommended DC Operating Conditions (OOe ~ Ta ~ ?O°C)
Item
Supply Voltage
Input High Voltage
Input Low Voltage

min.

typo

max.

Vee

4.S

5.0

S.5

V

VSS

0

0

0

V

VIH
V1L

2.2

6.0

V

-0.5·'

0.8

V

Symbol

Unit

Note) .\' -3.0V for pulse width;:l! IOns.

DC and Operating Charactaristics (Vee
Item
Input Leakage Current

Symbol

=5V± 10%. TI/ =oOe to +?O°C)
min.

IILl I

typo

mix.

Unit

2
10

/loA

Vee=S.5V. VIN-Vssto Vee

Test Conditions

Output Leakage Current

Ihol

Opera tin, Power Supply Current

Icc

100

/loA
rnA

C! .. V1H. VOUT· VSS to Vee
C!. VIL./oUT=OmA

Average Operatilll Current

ICCI
ISB

120
30

rnA
rnA

C!-V,H

ISBI

10

rnA

Output Low Voltage

VOL

0.4

V

10L'" 8mA

Output High Voltage

VOH

V

IOH" -4mA

Standby Power Supply Current

2.4

•

Min. Cycle. Duty: 100% IOUT=OmA

CS~Vee-0.2V
VIN~0.2Vor VIN~VCC-0.2V

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 135

HM6787H

SWiM-------------------------------------------------------------

AC Tast Conditions

Load A
+5V

OulpUI

Input pulse levels: Vss to 3.0V
Input rise and fall times: 4ns
Input timing reference levels: 1.5V
Output reference levels: 1.5V
Output load: See Figure

Oul pul

Load B

(for IHI, 1£1, IWI "

lOW)

+5V

480 Q
Dnulo--.....- -..
2550

Coal 0 - - " , , - - - ,

3OpF.

2550

• Includl"" lCape and 1111.

Capacitance (Til = 25°C.I= 1.OMHz)
Item
Input Capacitance
Output Capacitance

Symbol

max.

Unit

Conditions

CrN

6.0

pF

VINe OV

10.0

pF

VOUT-OV

COUT

Note) This parameter is sampled and not 100% tested.

AC Characteristics (VCC = 5VtlO%, Til = O°C to 70°C, unless otherwise noted.)
Read Cycle
Item

Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
uutput Hold from Address Change
Chip Selection to Output in Low Z
Chip Deselection to Output in High Z

IRC
tAA
tACS
lOB
tLZ
1HZ

HM6787H-15
max.
min.
15
15
15

3
3

3
3

0

HM6787H-20
min.
max.
20
20
20

6

0

8

Unit
ns
ns
ns
ns
ns
liS

Notes

1,2
1,2

Note: 1. This parameter is sampled and 100% tested.
2. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

Write Cvcle
Item
Write Cycle Time
Chip Selection to End of Write
Add"" Valid to End of Write
Address Setup Time
Write Pulae Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output In High Z
Output Active from End of Write

Symbol
twc
tcw
tAW
'AS
twp
tWR
tDW
tDH
twz
tow

HM6787H-15
min.
max.
15
10
10
0
10
3
12
0
0
6
0

HM6787H-20
min.
max.
20
15
15
0
15

3

IS
0
0
0

8

Unit

Notes

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

2

3,4
3,4

Note: 1. If~ goes high simultaneously with WE high, the output remains in a high Impedance state.
2. AU Write Cycle timings are referenced from the last valid address to the first tranlltlonlng addre ...
3. Transition Is measured ±200mV from steady state voltage with specified loading In Load B.
4. This parameter is sampled and not 100% tested.

•

HITACHI

1 36 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

-------------------------------------------------------------HM6787H S.iM
Timing Waveform of Read Cycle No. 11 ),

2)

IRe

Acldr •••

'"
lOH

Dat. Out

Dat. V.lid

Prnioul D.t. V.lid

Timing Waveform of Read Cycle No. 21),

3)

r-------------------.------------------.-,
IRe

I.CS

ILl

Dat. V.lid

D.t. Out

Note: 1. ft II hi8h and ~ Is low for READ cycle.
2. Addr..... valid prior to or colnclclent with B transition low.
3. Transition II meuured t200mV from steady state voltase with Ipeclfieclloadlnlln Load B.

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 137

HM6787H Sw~----------------------------------------------------------

Timing Waveform of Write Cycle No.1 (WE Controlled)
Iwe

Addr •••
lew

lAW
lAS
Iwp

loW

Data In

Data In Val id
IwZ

Data Out

Data Undefined

High Impedance

Note: 1. Transition is measured t200mV from steady state voltage with specified loading in Load B.

Timing Waveform of Write Cycle No.2 (CS Controlled)

Addre ..

--

we

'j

.J~

}~
lAS
lew

t

)
lAW

IWR

,

Iw p

\. \. \. \. \. \. ,~

'f/////
IOH

loW

)~

Dat. In

Data In Valid

~
.J

IwZ

Dat. Out

Data Undefined

High Impedance

Note: 1. TransitIon is measured t200mV from steady state voltage with specified loading in Load B.

•

HITACHI

138 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

HM6787HA S e r i e s - - - - - - - - - 65,536-Word x 1-Bit High Speed Static Random Access Memory
• FEATURES

• PACKAGE OUTLINE

• 65,536-Words x 1 bit organization
• 1.3 J.l1ll Hi-SiCMOS process
• Superfast
Access time 12/15/20 ns (max.)
• Low power dissipation
(DC) operating: 300mW (typ)
• +5V single supply
• Completely static memory
No clock or timing strobe required
• Fully TTL compatible input and output

,

• ORDERING INFORMATION
Type No.

Cycle Time

HM6787HAP-12
HM6787HAP-15
HM6787HAP-20
HM6787HAJP-12
HM6787HAJP-15
HM6787HAJP-20

12 ns
15 ns
20ns
12 ns
15 ns
20 ns

Package
300-mil, 22 pin
Plastic DIP
(DP-22NB)
300-mil, 24 pin
Plastic SOJ
(CP-24D)

(CP-24D)
• PIN ARRANGEMENT

HM6787HAP Series
Ao
AI
A2

• PIN DESCRIPTION
Pin Name
A{}-AI5

Function
Address Input

~

Din

Data Input

A4
As

DOUI

Data Output

WE

Write Enable

CS

Chip Select

VSS

Ground

Vee

Supply Voltage

Vcc
A1S
A14
A13
A12
An
Al0
A9
As
Din
CS

Ae
A7
Dout
WE
Vss

(Top View)
HM6787HAJP Series
Ao
AI
A2
A3
A4
As

Vcc
AIS
A14
A13
A12

NC

Att
AtD
Ag
As

NC

As
A7
Dout

WE

Din

VSS

CS
(Top View)

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 139

HM6787HA Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM

----0 Vee
----OVss

Memory Matrix
128 x 512

Row
Decoder

Din

Column 1/0

Dou!

Column Decoder

A12 A11 A10 A9 A14 A15 A1

AO A13

cs

WE

• TRUTH TABLE
Input
Output

Mode

X

HighZ

Not Selected

IS8,IS81

H

DOlit

Read

ICC, ICC!

HighZ

Write

ICC,ICCI

Unit

CS
H

WE

L
L

L

VCC Current

• ABSOLUTE MAXIMUM RATING
Symbol

Rating

Terminal Voltage to VSS Pin

VT

-0.5 to +7.0

V

Power Dissipation

PT

1.0

W

Item

Operating Temperature

__

·vp'

IJ to:- +70

'C

Tstg (bias)

-10 to +85

Tstg

-55 to +125

'C
'C

R~_!1ge

T~

Storage Temperature Range (with bias)
Storage Temperature Range

• RECOMMENDED DC OPERATING CONDITIONS (O°C
Item
Supply Voltage
Input High Voltage
Input Low Voltage

s T a S 70°C)

Symbol

Min

Typ

Max

Unit

VCC
VSS
VIH
VIL

4.5
0.0
2.2
-3.0 1

5.0
0.0
-

5.5
0.0
6.0
0.8

V
V
V
V

-

Notes 1. Pulse width \0 ns, DC; -0.5V

~HITACHI
140 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------------HM6787HASeries
• DC AND OPERATING CHARACTERISTICS (Vcc =5.0V ± 10%, Vss
Item

Symbol

Test Conditions

Input Leakage Current

I III I

Vee = S.SV, VIN = OV to Vee

Output Leakage Current

CS = VIH, VOUT= OV to Vee

Operating Power Supply Current

IIwl
lee

Average Operating Current

=OV, Ta =0 to +70°C)
Typ

Max

Unit

2
10

IlA
IlA

-

100

rnA

-

120

rnA

-

30

rnA

-

-

10

rnA

-

-

0.4

V

2.4

-

-

V

Min

-

IeC!

CS = VIL. IOUT= 0 rnA
Min. Cycle Duty: 100%,
IOUT=OmA

-

ISS

C~; = VIH, VIN= VIH or VIL

-

ISSI

CS <: Vee -O.2V, VIN ~ O.2V or
VlN<:Vee-O.2V

Standby Power Supply Current
Output Low Voltage

VOL

IOL=8mA

Output High Voltage

VOH

IOH =-4 rnA

• AC CHARACTERISTICS (VCC = 5V ± 10%, Ta =

ooe to +70°C)

• Read Cycle
Item

HM6787HA-12
Min
Max

Symbol

HM6787HA-15
Min
Max

HM6787HA-20
Min
Max

Unit

Read Cycle Time

tRe

12

-

IS

-

20

-

I1S

Address Access Time

tAA

12

-

IS

ns

tAeS

12

-

IS

-

20

Chip Select Access Time

-

20

ns

4

-

ns

S

-

ns

4

-

4

Chip Selection to Output in Low Z

tOH
tLz l ,2

3

-

S

Chip Deselection to Output in High Z

tHz l ,2

0

Output Hold from Address Change

6

-

0

6

0

8

ns

Notes I.This parameter is sampled and not 100% tested.
2. Transition is measured ±200mV from steady state voltage with specified loading in Load (B).

• Write Cycle
Item

HM6787HA-12

Symbol

Min

Max

HM6787HA-IS

HM6787HA-20

Min

Min

Max

Max

Unit

Write Cycle Time

twe l

12

-

IS

-

20

-

ns

Chip Selection to End of Write

tew

8

-

10

-

13

-

ns

Address Valid to End of Write

tAW

8

-

10

13

-

ns

Address Setup Time

tAS

0

0

0

-

ns

Write Pulse Width

twp

8

10

-

13

tWR

O.S

0.5

-

0.5

Write Recovery Time (CS)

tWRl

I

I

-

I

-

ns

Write Recovery Time (WE)

-

-

Data Valid to End of Write

tDW

7

-

8

-

10

-

ns

0

-

0

-

0

-

Write Enable to Output in High Z

tDH
twz2,3

Output Active from End of Write

tOw2,3

3

Data Hold Time

Notes I.
2.
3.
4.

0

6

0

-

3

6

-

0
3

8

-

ns
ns
ns
ns
ns

All Write Cycle timings are referenced from the last valid address to the first transitioning address
This parameter is sampled and not 100% tested.
Transition is measured ±200mV from steady state voltage with specified loading in Load (B).
If CS goes high simultaneously with WE high, the output remains in a high impedance state.

• Capacitance (Ta = 25°e f = 1 MHz)
Item

Symbol
Cin 1

Max

Unit

Input Capacitance

6

pF

Test Condition
VIN=OV

Output Capacitance

COUT l

10

pF

VOUT=OV

Notes 1. This parameter is sampled and not 100% tested .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 141

HM6787HASeries - - - - - - - - - - - - - - - - - - - - - - - - - - - •
•
•
•
•
•

AC TEST CONDITIONS
Input pulse levels: VSS to 3.0V
Input timing reference levels: 1.5V
Output load: See figure
Input rise and fall times: 4ns
Output reference levels: 1.5V

+5V

+5V

4800

Dout

4800

Dout

5 pF·

2550

2550

Output Load B (for tHZ. tLZ. twz & tow)

Output Load A

*including scope and jig capacitance

• TIMING WAVEFORMS
• Read Cycle -11, 2

Address
IOH

Data Out

Notes I.
2.

Previous Data Valid

Data Valid

WE is high and CS is low for read cycle.
Addresses valid prior to or coincident with CS transition low.

• Read Cycle -21, 2, 3
IRC

cs

~

~It'

I\lACS
ILZ

1HZ

Data Out
Highim pedence

~K

Data Valid

"-

./

High

Impedence
Notes I.
2.
3.

WE is high and CS is low for read cycle.
Address valid prior to or coincident with CS transition low.
Transition is measured ± 200 mV from steady state voltage with specified loading in Load (B) .

•

HITACHI

142 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

-----------------------------HM6787HASeries
• TIMING WAVEFORMS
• Write Cycle -11 (WE Controlled)

twc

)K

) K.

Address

'"'"'"

~"'''' ~

cs

tcw

~////////////h
tAW
tAS

tWR
twp

WE

~~ ~

/

tOH

tow
Data In Valid
twz

Data In
Data Out

NOTE:

ut Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z

•

o Input and Output timing reference levels: 1.5V
o Output load: 1TTL Gate and CI. (100pF)
(Including scope and jig)

tRC
tAA
tACS
tOE,
tOH
tCLZ
tOLZ
tCHZ
tOHZ

HM622S6·8
min.
max.
8S
85
85
45
5
10
5
0
30
30
0

-

-

HM622S6·12
max.
min.
120
120
120
60
10
10
5
40
0
40
0

HM622S6·10
min.
max.
100
100
100

-

10
10
5
0
0

-

-

SO

3S
35

-

HM622S6·1S
min.
max.
150
150
150
70
10
10

-

-

-

5

-

0
0

SO
SO

Timing Waveform of Read Cycle No. 1111
tRC

Address

V

\
J

\.

tAA

\ \ \ \ \ \ \ \ \\.

V

\\\\
Dout

•

It

tOLZ
tACS
tCLZ

///11111
tou

tOE

J

OOK

'////// '///
tOHZ
tcHZ

Data Valid

/\1'..

.IN

Timing Waveform of Read Cycle No. 2[1)(2)(4)
tRC

Address
tOH

tAA
tOH

Dout

Data Valid

•

HITACHI

146 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300

Unit
n.
ns
nl
ns
n.
ns
ns
ns
ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 2 5 6 Series
• Timing Waveform of Read Cycle No.

3(1) (3) (4)

ICHZ

lACS

ICLZ

Dout

Data Valid

Notes) I. W! is High for Read Cycle.
2. Device is continuously selected, CS = V/L.
3. Address Valid prior to or coincident with CS transition Low.
4. DE = VIL.

• Write Cycle
Symbol

Item
Write Cycle Time
Chip Selection to End oC Write
Address Valid to End oC Write
Addreu Set Up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold Crom Write Time
Output Disable to Output in High Z
Output Active Crom End oCWrite

twe
tew
tAW
tAS
twp
tWR
tWHZ
tDW
tDH
tOHZ
tow

HM62256·8
min.
max.
85
75
75
0
60
-

-

10

-

0
40
0
0
5

30

-

30

-

HM62256·12
min.
max.
120
85
8S
0
70
0
40
0

HM62256·10
min.
max.
100
80
80
0
60
0
0
3S
40
0
35
0
5
-

-

SO
0
0
5

40

-

HM62256·15
min.
max.

ISO
100
100
0
90
0
0
60
0
0
5

Unit

50

50

-

ns
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns

• Timing Waveform of Write Cycle No.1 (OE Clockl
WC

\ v---

\
J

Address

j

t--IWRW-

}L;i/
~\

1\\\\\\\

lew

I

j(/~//L/

1\\\\\

i---/AS-

lAW

\r-..\~\ 1\

J

10HZ (3)

Dout

~ ~

_\. .\.\.

~

V

Iwp (1)

_\. \. \.\.

1'/////////1

low

Din

/

/

\.\.

•

tOH

/J.X

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 147

HM62256 Series - - - - - - - - - - - - - - - - - - - - - - - - - - • Timing Waveform of Write Cycle No. 2(&1 IOE Low Fixed)
tll'C

Address

tew

tAli'
til'/'

(I)

tow
Dout
t[)W

tDIl

Din
Notes: I.
2.
3.
4.

S.
6.
7.
8.

A write occurs during the overlap (t~ of a low CS and a low WE.
is measured from the earlier of CS or
going high to the end of write cycle.
During thh period, I/O pins are in the output state. TheJ!lput signals out of phase must not be applied
low transition,
If the CS low transition occurs simultaneously with the WE low transition or after the
outputs remain in a high impedance state.
OI' is continuously low. (en: = Vn )
Dout is in the same phase of written data of this write cycle.
Dout is the read data of next address.
If CS is low during this period, 1/0 pins are in the output state. The input signals out of phase must not be
applied to [/0 Pins .

wr

I WR

wr

• LOW VCC DATA RETENTION CHARACTERISTICS (T" = 0 to +70°C)

(This characteristics is guaranteed only for L·and L-SL version)
Item

Vee for Date Retention

Symbol

Vee
Data Retention Current

ICCDR

Chip Deselect to Data Retention Time

tCDR

Operation Recovery Time

tR

Note)

•

min.

typo

max.

Unit

2.0

-

-

V

-

-

SO··
10· s

0

-

-

lis

tRC· '

-

-

ns

Test Conditions
CS ~ VCC -O.2V

VDR

=3.0V, CS?; 2.8V

OV~ Vln

See Retention Waveform

01. tRC = Read Cycle Time
°2. This characteristic is guaranteed only for L-verslon, 20"A max. at T" = 0 to 40· C.
°3. This characteristic is guaranteed only for L·SL version, 31lA max. at T" =0 to 40·C .

Low Vce Data Retention Waveform

Vee

DATA RETENTION MODE

VDR~2.0V

VDR

cs~

Vee-O.2V

CS-_J
Note)

OV------------------------------------------------------------

In Data Retention Mode, 'CS' controls the Address, WE, M, and Din Buffers. Vln for these Inputs can be In
high impedance state In data retention mode .

•

HITACHI

148 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589·8300

"A

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM62256 Series
SUPPLY CURRENTVLSUPPLY VOLTAGE 111

SUPPLY CURRENTva.AMBIENT TEMPERATURE 111
1.6

r.=25·C

Vcc=S.OV
1.4

L

2

0

/

V

·v

~

1.0

"

0.8

j
1

I"-

0.6

0.6

O. 4 4.50

- r---

t---

4.15

5.00

O. 4 0

5.50

5.25

Supply Voltqe Vee (V)

20

SUPPLY CURRENT va. SUPPL Y VOLTAGE (21

To

("C)

SUPPLY CURRENT va. AMBIENT TEMPERATURE (21
1.3

1.6

Vcc=5.0V

r.=25·C

1

1•4

11.2
J

80

60

Ambient Temp!!'rature

0

8~

----

~

V--

1.0

!

0.9

1o.

6

o.4 4.50

~

4.15

5.00

5.25

5.50

i--

-

8

o. 7 0

20

40

60

SUPPLY CURRENT va. SUPPL Y VOLTAGE (31

SUPPLY CURRENT va. AMBIENT TEMPERATURE (31

I.6

I. 3

Vcc =5.0V

r.=25·C
2

I. 4

L.

.2

.0

8,... / '

~

~

V

0-- - I

-

9

8

.6

0.4 4.50

80

Ambient Temperature To ("C)

Su.pply Voltage Vee (V)

4.75

5.00

5.25

5.50

Supply Voltage Vee (V)

•

.7

60
20
40
Ambient Temperature To COC)

80

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 149

HM62256 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ACCESS TIME.,., SUPPL Y VOLTAGE

ACCESS TIME.,., AMBIENT TEMPERATURE
I.3

1.3

Vee = S.OV

T.~25'C

2

---

I

-

1.0

~

1
~

I. I

~

t---

----t---

~ 0.9

...,

.:

I. 0

~

!

0.8

0.8

0.74.50

4.75

5.00
f

1.0

z

20

/
0. 4

60

80

STANDBY CURRENT.,., AMBIENT TEMPERATURE

~V

/

/
V

Vee =-= 5.0V

I

Ta=25'C

/

,

.

10-

o

SUPPLY CURRENT.,., FREQUENCY (READ)
1.2

150..

1

20

10 ns

/

~ 0.8

J

/

0.2

,

60

80

SUPPLY CURRENT.,., FREQUENCY (WRITE)

Iso..

85ns

,/

1

1. 0

~

8

1 o.

V

V ...

40

I. 2

12On.

1.0

0.4

V

Ambient Temperature Ttl (-C)

Supply Voltage Vee (V)

i
£ 0.6

.,./

/

/

O.2 2

!

40

Ambient Temperature To ('C)

10

1.4

1

o

V1

STANDBY CURRENT.,., SUPPLY VOLTAGE

1.2

O. 7

5.50

5.25

Supply Voltagl.' V"c

1

.,./

/

o.9

...,

,/

/

/'

/

i

/

.] o.6
T.=25'C
Vee"" 5.0V
4

/

2

/

V

85••

V

/

V

0

T.=25'C
Vc =5.0V

10

12

10

loJ...

IkOn.

Frequency f (MHz)

Frequency I (MHz 1

•

HITACHI

150 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

12

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM62256 Series
INPUT LOW VOLTAGE

VI.

SUPPLY VOLTAGE

INPUT HIGH VOLTAGE
SUPPLY VOLTAGE

1. 3

VI.

3
To 25'(;

Ta

2

-

1

Ii
:1

I. 0

..~

~

,.--

o.9

~

j
i

.!

~

i

..5

5.00
Supply

Vcr

4.50

(v I

1. 4

1\
\\

Q. 8

! o.

:z

1. 2

~

1. 0

~

T.·~25·C

Vee" S.OV

L

o.4

.4

~

T.~

25'C

Vee ·-·5.0V

L

I

o o. 6

\
Output HiRh Voltlf(e VDI,

5.50

/

j o. 8

6

5.25
1

J

1

\

1. 0

5.00

OUTPUT CURRENT •.
OUTPUT VOLTAGE

VI.

1. 4

<3

4.75

Supply Volta~1f" l'n 'V

1. 6

1. 2

~

~

O. 8

1.6

1'=
~

~

O. 7

5.50

5.25

Volta~

OUTPUT CURRENT
OUTPUT VOLTAGE

~

0

9

4.75

--

1. 1

O. 8

o.74.50

"2

25'C

2

V
0.2

0.4

0.6

0.8

Output Low Vohage VIII, IV)

(V)

ACCESS TIME •• LOAD CAPACITANCE
\.8

1.6

i

5

1.4

--

'=

~

1.2

j

.0

.8

0.6100

~

200

~

300

--400

500

Loed Capacitanee CL rpF )

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 51

HM62256A Series-----------Preliminary
32,768-Word x a-Bit High Speed CMOS Static RAM
• DESCRIPTION
The Hitachi HM62256A is a CMOS static RAM
organized 32k-word x 8-bit. It realizes higher performance and low power consumption by employing
0.8 11m HI-CMOS process technology. The device,
packaged in a 8 x 14 mm TSOP with thickness of
1.2 mm, 450-mil SOP (foot print pitch width), 600mil plastic DIP, or 300-mil plastic DIP, is available
for high density mounting. TSOP package is suitable
for cards, and reverse type TSOP is also provided. It
offers power standby power dissipation; therefore, it
is suitable for battery back up system .
• FEATURES
• High speed:
Fast access time 85/100/120/150 ns (max.)
• Low power
Standby: 10 I1W (typ.) (UL-SL version)
Operation: 40 mW (typ.) (f = 1 MHz)
• Single 5V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output: Three state output
• Directly TTL compatible: All inputs and outputs
• Capability of battery back up operation

(FP-28DA)

• ORDERING INFORMATION
Type No.
HM62256AP-8
HM62256AP-IO
HM62256AP-12
HM62256AP-15
HM62256ALP-8
HM62256ALP-IO
HM62256ALP-12
HM62256ALP-15
HM62256ALP-8SL
HM62256ALP-IOSL
HM62256ALP-12SL
HM62256ALP-15SL
HM62256ASP-8
HM62256ASP-IO
HM62256ASP-12
HM62256ASP-15
HM62256ALSP-8
HM62256ALSP-IO
HM62256ALSP-12
HM62256ALSP-15
HM62256ALSP-8SL
HM62256ALSP-IOSL
HM62256ALSP-12SL
HM62256ALSP-15SL
HM62256AFP-8T
HM62256AFP-IOT
HM62256AFP-12T
HM62256AFP-15T
HM62256ALFP-8T
HM62256ALFP-IOT
HM62256ALFP-12T
HM62256ALFP-15T
HM62256ALFP-8SLT
HM62256ALFP-IOSLT
HM62256ALFP-12SLT
HM62256ALFP-15SLT

Access Time
85 ns
lOOns
120 ns
150ns
85 ns
100 ns
120ns
150 ns
85 ns
lOOns
l20ns
150ns
85 ns
100 ns
l20ns
150ns
85 ns
lOOns
120ns
150ns
85 ns
lOOns
120ns
150ns
85 ns
lOOns
120ns
150ns
85 ns
lOOns
120ns
150ns
85 ns
100 ns
120ns
150ns

(TFP-32DA)

Package

6OO-mil
28-Pin
Plastic DIP
(DP-26)

iI TSOP SERiES
Type No.
HM62256ALT-8
HM62256ALT-1O
HM62256ALT-12
HM62256ALT -15
HM62256ALT -8SL
HM62256ALT -I OSL
HM62256ALT -12SL
HM62256ALT-15SL
HM62256ALR-8
HM62256ALR-1O
HM62256ALR-12
HM62256ALR-15
HM62256ALR-8SL
HM62256ALR- IOSL
HM62256ALR-12SL
HM62256ALR-15SL

300-mil
28-Pin
Plastic DIP
(DP-28NA)

450-mil
28-Pin
Plastic SOP
(FP-28DA)

$

Access Time
85 ns
lOOns
120ns
150ns
85 ns
lOOns
1200s
150 os
85 os
lOOns
120 os
150ns
85 ns
100 ns
120ns
150ns

Package

8mmx 14mm
32-Pin TSOP
(Nonnal Type)
(TFP-32DA)

8mmx 14mm
32-PioTSOP
(Reverse Type)
(TFP-32DAR)

HITACHI

152 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------------HM6~ASeries

• PIN ARRANGEMENT

HM62256AR Series

HM62256AP/AFP/ASP Series

28
27
26
25
24
23
22
21
20
19
18
17
16
15

A14
A12
A7

Ae
As

~
A3
A2
A1
Ao

1/00
1/01
1/02

Vss

2
3
4
5
6
7
8
9
10
11
12
13
14

Vcc
WE

A3

NC

16
15
14
13
12
11
10
9
8
7
6
5
4
3

fu.1

2

A 13

~

As

A5

NC

As

Ag

An

A7
A'2
A14

OE

Ys:&
WE
A'3
As
Ag

A 10

CS
1/0 7
1/06

OE

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

1

1/02

NC

PIg
PIg
A'3
WE
Vee
A'4
A'2
A7

As

As
NC

A4

As

Vss
1/03
1/04
1/05
I/0s
1/07

NC
CS

A,o

(Top View)
• PIN DESCRIPTION

HM62256AT Series

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1100
110,
1/02

Vss
Symbol

BE

NC
Ao

1/05

(Top View)

A"

A2
A,

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

AlO

CS
NC
1/07
I/0s
1/05
1/04
1/03

Function

Ao--AI4

Address

1/0()-1/07

Input/Output

CS

Chip Select

WE

Write Enable

OE

Output Enable

NC

No Connection

Vee

Power Supply

VSS

Ground

Vss
1/02
1/0,
1/00

Ao
NC
A,
A2

(Top View)

$

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 153

HM6~Series---------------------------------------------------------

• BLOCK DIAGRAM

I

AS
A4

0--

A3

0--

A11 0 - -

Ag

0--

As

0--

A12 0 - -

A7

0--

As

0--

--aVcc

~

I

--aVss

-

•

·
··
·

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

··
·
-

Row
Decoder

··

Memory Matrix
512 x 512

~
I

1/00

I
I
I
I
I
I
I
I
I
I
I

1/07

-.-

W
.

I

Input
Data
Control

•
•

•

I
I

I

..

Column Decoder

•

~

Column lID

r-!--

r~ ---------------~"l ~
6 A13
6 Al6 A2.6 Al0
6 A146

fo.{J

CS

':~I!'~~Q. f~~~~ ~_e_n_e!~!o!_

WE

ReadlWrite Control

·

··

I
I
I
I
I
I

I

I

•

HITACHI

1 54 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------HM62256ASeries
• FUNCTION TABLE
WE

CS

OE

Mode

Vee Current

X

H

X

Not Selected

ISS, Issl

110 Pin
High-Z

H

L

H

Output Disable

lee

High-Z

H

L

L

Read

lee

Dout

Read Cycle

Ref. Cycle
-

-

L

L

H

Write

lee

Din

Write Cycle (I)

L

L

L

Write

lee

Din

Write Cycle (2)

Note: X: H or L

• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Voltage on any pin relative to VSS

Value
-0.5*' to +7.0

VT

Power Dissipation

Unit
V

PT

1.0

W

Topr

o to +70

°C

Storage Temperature

Tsl'

-55 to +125

°C

Storage Temperature Under Bias

Tbias

-10 to +85

°C

Operating Temperature

Note: I. VT min = -3.0 V for pulse half-width::;; 50 ns

• RECOMMENDED DC OPERATION CONDITIONS CTa = 0 10 + 70°C)
Item

Symbol

Min.
4.5

Vee

Supply Voltage

Typ
5.0

Max.
5.5

Unit
V
V

Vss

0

0

0

Input High (Logic I) Voltage

VIH

2.2

5.0

V

Input Low (Logic 0) Voltage

VIL

·-0.5*1

-

0.8

V

Note: I. VIL min = -3.0 V for pulse half-width::;; 50 ns

• DC CHARACTERISTICS CTa =0 10 +70°C, Vcc =SV ± 10%, Vss =OV)
Item

Typl

Max.

Unit

Test Conditions

Input Leakage Current

IILI I

-

-

I

IlA

Yin = VSS to Vee

Output Leakage Current

Ilwl

-

-

I

IlA

CS = VSS orOE = VIH or
WE = VIL, VI/a = Vss to Vee

lee

-

8

15

rnA

CS = VIL, Others = VIHNIL, loul = 0 rnA

IeC!

-

40

70

rnA

Min Cycle, Duty = 100%, II/a = 0 rnA,
CS = VIL, Others = VIHNIL

Iee2

-

8

15

rnA

Cycle Time = IllS, II/a = 0 rnA,
CS = VIL, VIH = Vee, VIL = 0
CS=VIH

Symbol

Operating Vee Current

Iss
Standby Vee Current
ISSI
Output Low Voltage
Output High Voltage

VOL
VOH

Min.

-

0.5

3

rnA

-

2

rnA

-

0.D2
1*2

100*2

IlA

-

1*3

50"3

J.lA

-

-

0.4

V
V

2.4

-

Vin;;' OV, CS;;, Vee -O.2V
IOL=2.1 rnA
IOH=-1.0mA

Notes: I. Typical values are at Vee = 3.0V, Ta = +25°C and specified loading.
2. This characteristics is guaranteed only for L-version.
3. This characteristics is guaranteed only for L-SL version .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 155

HM~Series--------------------------------------------------------• CAPACITANCE (Ta = 25°C, f= I MHz.)*1
Item
Input Capacitance

Symbol

Input/Output Capacitance

Min

Cin

-

CliO

-

Typ

-

Test Conditions

Max
6

Unit
pF

Vin=OV

8

pF

VI/O=OV

Note: 1. This parameter is sampled and not 100% tested.

• AC CHARACTERISTICS (Ta

=0 to +70°C, V CC =SV ± 10%, unless otherwise noted.)

Test Conditions
•
•
•
•

Input pulse levels: 0.8V to 2.4V
Input rise and fall times: 5 ns
Input and output timing reference levels: 1.5V
Output load: 1 TTL Gate + CL (100 pF) (including scope &jig)

• READ CYCLE
Item

Symbol

Read cycle time

tRC
tAA

HM62256A-8
Min
85

-

Max

85
85

HM62256A-1O HM62256A-12 HM62256A-15
Max
Max
Min
Max
Min
Min
100
120
ISO
-

-

Address access time
Chip select access time
Output enable to output valid

tACS
tOE

-

45

-

Chip selection to output in low-Z

tcLZ

10

-

10

Output enable to output in low-Z
Chip deselection to output in high-Z

IoLZ

-

tcHz

5
0

30

5
0

Output disable to output in high-Z
Output hold from address change

10HZ
tCH

0
5

30

0

-

10

-

-

-

100
100

-

120
120

-

-

Unit

150
150

ns
ns

50

-

60

-

70

ns

-

10

10

5

-

ns
ns

35

0

40

5
0

-

0
10

40

0

50
50

ns

35

-

10

-

ns
ns

• READ TIMING WAVEFORM-3

Address

CS

tOLZ

Dout

Notes:

I. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referenced to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. WE is high for read cycle.

•

Note

ns

HITACHI

156 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

2
2
1,2
1,2

------------------------------HM62256ASeries
• WRITE CYCLE
Parameter
Write cycle time
Chip selection to end of write

Symbol
twc
tcw

HM62256A-8
Min
Max
85
75
-

HM62256A-1O HM62256A-12 HM62256A-15
Min
Max
Min
Max
Min
Max
120
150
100
80
85
100
0
80

-

60

-

Address setup time

tAS

0

-

Address valid to end of write
Write pulse width

tAw
twp

75
55

-

Write recovery time
WE to output in high-Z

tWR
tWHZ

0
0

Data to write time overlap

tow

-

Data hold from write time
Output active from end of write

tOH

40
0

-

0

tow

5

-

5

30

-

0
100

-

90

0
0

-

-

-

50
0

0
0
60

-

-

0

-

-

5

-

5

-

-

0
0
40

35
-

0
85
70

40

-

50

Unit

os
ns
ns
ns
ns
ns
ns
ns
ns
ns

Note

10

10

• WRITE TIMING WAVEFORM (1) (OE Clock)

twc

Address

_ _- J

OE

cs

tcw'2

*6

Dout

- - - d - -.. .~->kxXXX
tDW

Din

•

tOH

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300 157

HM6~OOASeries------~----------------------------------------------

• WRITE TIMING WAVEFORM (2) (OE Low Fixed)

twc

Address
tcW"2

cs
"6
.~______________~tA~w~__________-;~

WE
tWHZ "5

tow

.:---_~~I

'7

"8

Dout

Din

Notes:

1. A write occurs during the overlap (twp) of a loweS and a WE. A write begins at the later transition ofeS going low
or WE going low. A write ends at the earlier transition of es going high or WE going high. twp is measured from the
beginning of write to the end of write.
2. tew is measured from es going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the earlier of WE or es going high to the end of write cycle.
5. During this penod, I/U pins are in the output state so that the input signals of the opposite phase to the outputs must not
be applied.
6. If the es low transition occurs simultaneously with the WE low transition or after the WE transition, the output remain
in a high impedance state.
7. Dout is the same phase of the write data of this write cycle.
8. Dout is the read data of next address.
9. If es is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the
outputs must not be applied to them.
10. This parameter is sampled and not 100% tested .

•

HITACHI

158 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300

------------------------------HM62256ASeries
• LOW Vee DATA RETENTION CHARACTERISTICS (Ta =0 to +70 0c)

This characteristics is guaranteed only for UL-SL version.
Symbol

Min

Vee for Data Retention

VDR

2

Data Retention Current

IceDR

Item

Chip Deselect to Data Retention Time
Operation Recovery Time

Typ

-

Max

-

Unit

Test Conditions

V

CS;O> Vee -O.2V. Vin '" OV
Vee = 3.0V, Vin '" OV,
CS '" Vee -O.2V

-

0.5

10*2

!I A

-

0.5

10*2

teDR

0

-

-

!I A
ns

tR

5

-

-

ms

See Retention Waveform

• LOW Vee DATA RETENTION TIMING WAVEFORM

Data retention mode

Vee
4.5V

2.2V

VDR

CS

Notes:

CS?:Vee - O.2V
OV-----------------------------------------

I. 20!lA max at Ta =0 to +'IO°e. (only for L-version)
2. 3!1A max at Ta = 0 to +40°e. (only for L-SL version).
3. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention mode, Vin levels
(address, WE, OE, I/O) can be in the high impedance state .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300 1 59

HM62832H Series - - - - - - - - 32768-WORD x 8-BIT HIGH SPEED CMOS STATIC RAM
• FEATURES
•

High speed: Fast Access time 25135 ns (max.)

HM62832H-Low power
Standby: 300 mW (typical)
Active: 30 p.W (typical) (L.version)

• Single 5V supply

(OP·28NA)

• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output-Three stage output
• Directly TTL campatibla-AII inputs and outputs

• ORDERING INFORMATION
Part No.
HM62832HP-25
HM62832Hp·35
HM62832HIP-25
HM62832HIP-35

Access

Package

25 ns
35 ns

300 mil 28-pin
Plastic DIP
(Dp·28NA)

25 ns
35 ns

(CP-280N)

PIN ARRANGEMENT
Top View

300 mil 28-pin
Plastic SOl
(CP-28DN)

A141;;:
A12 ~
A7

Aa=
As=
A4
A3

=

A,

~

A2~
Ao~

1100
110,
1102
VSS

28

1
2
3
4
5
6
7
8
9
10

27
26
25
24

23
22
21
20
19
UI
17
16
15

= 11
=12
= 14'3

:::J Vee

we
5~A'3

=As
= A9

= oe
A"
A,o

5c§

~1107

= IfOe
= 1105
= 1104
1103

• PIN DESCRIPTION
Pin Name
Ao-AI4

•

Function
Address

1100-110,

[nput/Output

CS

Chip Select

WE

Write Enable

OE

Output Enable

Vee

Power Supply

Vss

Ground

HITACHI

160 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - HM62832H Series
• BLOCK DIAGRAM

A12
A14

AS
A13

Ai
A1t

AS
AS
A7

-I
I
I
I

X
Address
Buffer

-

~

~

~

~

I
I
I
I

Row
Decoder

~

I
I
I
I

S12XS12

I--

I

I

I

A
1100

Memory Array

I-I
I

VO
Buffer

1/07

r--

II

Column VO
Column Decoder

I

- -.-

II

Y Address Buffer

WE

I - -- I I

OE

cs

- --

AO A1 A2 A3 A10 A3 A4
~~

•

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 161

HM62832H Series ~--------------------------• ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Voltage on any Pin Relative to V55

VT

-O.S"1 to + 7.0

V

Power Dissipation

PT

1.0

W

Operating Thmperature

Item

Unit

Top,

oto +70

Storage Thmperature

T"g

-SS to + 125

·C
·C

Storage Temperature Under Bias

Tbias

-10 to +8S

·C

NOTE:

I. -2.S V (or pulse width

s

10 ns

• FUNCTION TABLE
CS

OE

WE

Mode

H

X

X

• Not Selected
Read

L

L

H

L

H

L

L

L

L

NOTE:

Write

Vee Current

110 Pin

158. 1581

HighZ

Ref. Cycle
Read Cycle(1) to (3)

Icc

Doul

Icc

Din

Write Cycle(l)

Icc

Din

Write Cycli:(2)

I.X:Ho,L

•

HITACHI

162 Hitachi America. Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 3 2 H Series
• DC CHARACTERISTICS for HM62832H (TA = 0 to +70·C, Vee = SV

:I:

10%, V 5S

=OV)

Symbol

Min.

Typ.'1

Max.

Input Leakage Current

IILlI

-

-

2

"A

Output Leakage Current

IILOI

-

-

2

"A

or WE .. VIL ,
Vila" VsslOVee

Operating Power Supply Current

Icc

-

60

120

rnA

Min. cycle, duty .. 100%,
CS = VIL,
1110 = o rnA

Standby Power Supply Current

15B

-

IS

30

rnA

CS = VIH

0.02

2

rnA

-

0.006

0.1

rnA

-

0.4

V

IoL = 8 rnA

-

V

10H = -4mA

Parameter

Standby Power Supply Current

15BI

Output Voltage
NOTE:

VOL

-

VOH

2.4

Unit

'lest Conditions

Note

Vln = Vss to Vee

CS .. VIH or OE .. VIH

CS

Vee - 0.2V,
Vin S 0.2 V,
or Vin, it: Vee - 0.2 V
it:

oV S

L-venion

I. Typical values are at Vee - S.O V, TA - +2'·C and specified loading.

• CAPACITANCE (Ta = 2S·C, f = IMHz)
Symbol

Min.

Typ.

Max.

Unit

Input Capacitance

Parameter

C in

-

-

6

pF

Vin

Input/Output Capacitance

CliO

-

-

10

pF

Vila

NOTE:

1\:st Conditions

= OV
= OV

I. This parameter is sampled and not KJOS lested.

• AC CHARACTERISTICS (Ta = 0 to +70·C, Vee = 5 V

:I:

10%, unless otherwise noted.)

Test Conditions
• Input and output timing reference levels: 1.5 V
• Output load: See Figures

• Input pulse levels: 0.0 V to 3.0 V
• Input rise and fall times: 5 ns

:q

Output Load (A)

Output Load (B)

(for teLZ' toLZ' teHZ' toHZ' tWHZ &

rq

+5~ao

Dout
255

NOTE:

tow)

+5:ao

Dout
255

30 pF'

5 pF'

·Including scope &. jil.

_HITAOHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 163

HM62832H Series - - - - - - - - - - - - - - - - - - - - - - - - - - • Read Cycle

Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold From Address Change
Chip Selection to Output in Low-Z
Output Enable to Output in Low-Z
Chip Deselection to Output in High-Z
Output Disable to Output in High-Z

Symbol
tRC
tAA
tACS
toE
toH
teLZ
toLZ
teHZ
toHZ

HM62832H-25
Min.
Max.
25
25
25
12
5
5
0
0
12
0
12

HM62832H-35
Min.
Max.
35
35
35
15
5
5
0
0
15
0
15

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

Read Cycle Timing (2) '1, '2,'4

Read Cycle Timing (1)'1

Read Cycle Timing (3) '1, '3, '4

~ ~~Da::=::::::-!_--~
NOTES:

.,.

WE is high for read cycle.

*2. Device is conlinuously selected.

CS co

VIL.

*3. Address should be valkl prior to or coincident with CS Ifansidon low.
*4.

OE =

VIL .

• Write Cycle

Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High-Z
Output Active From End of Write

Symbol
'WC
tew
tAW
tAS
twp
tWR
tWHZ
tDW
tDH
tOHZ
tow

$

HM62832H-25

HM62832H-35

iviiu.

:Max.

iviin.

iviax.

25
20
20
0
15
0
0
12
0
0
5

-

35
30
30
0
20
0
0
15
0
0
5

-

-

15
12

-

Unit

-

15

15
-

HITACHI

164 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 3 2 H Series
Write Cycle Timing (1)

(DE Clock)

...

Add,....

A

~'\:

...l!!!..j

0..-,:'...",,,'

...

0
(\.~

~

...

~""'II.
~
x

Din

;uo(

Write Cycle Timing (2) (OE Low Fixed)
two

...

Addres.

,,"'"l""

"l

...

.....

,

.,
•

...... ,''''..!::::1 .....,
~,

~

00".

~~

Din
NOTES:

"

.,. A write occurs during the overlap (CWp) ofa low CS and a low WE.
"2. IWR is measured from the earlier orcs or WE going high to the end of write cycle.
"3. During this period, 110 pins are in the output slate. The input signals out of phase must not be applied.
"'4. If the CS low transition occurs simultaneously with the WE low transition or aftcr the WE low transition. outputs remain in a high impedance state.
·5.

OE is continuously low. (DE "" V'L>.

"'6. Dout is in the same phase ofwrillcn data Oflhis write cycle.
*7. Doul is the read data of next address.
*8. If CS is low durin. this period. 1/0 pins are in the output stile. The input signals out of phase must not be applied to 1/0 pins.
"'9.

WE must be high during all address transitions excePI when device is deselected with CS .

• Low Vee Data Retention Characteristics (TA = 0 to
This characteristics is guaranteed only for L-version
Parameter

+ 70°C)

Symbol

Min.

Typ.

Max.

Unit

Vee for Data Retention

VOR

2.0

-

-

V

Data Retention Current

lecoR

-

I

50'2

p.A

Chip Deselect to Data Retention Time

!cOR

0
t RC 'I

-

-

ns

tRC

Operation Recovery Time
NOTES:

Test Conditions

Cs '"

Vce - 0.2 V,
V;n '" Vcc-0.2 Vor
o V :S V;n S 0.2 V

ns

.1. tRe :: read cycle time.
·2. Vee

= 3.0 V.

Low Vee Data Retention Timing Waveform

'" ."_n_~---:-·==-m~nmn
----------------- -~~~~------

----- --------

~:-----

----~~~~~~;;---

-----

------

~OV - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

_HITACHI
Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 165

HM62832UH S e r i e s - - - - - - - - 32,768-Word x a-Bit High Speed CMOS Static RAM
• FEATURES
• High speed
Access time 15/20 ns (max.)
• Lowpower
Standby: 15 JlW (typ.) (L-version)
Operation: 550/400 mW (typ.)
• Single 5V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output-Three state
output
• Directly TTL compatible-All inputs and outputs

(CP·28DN

• ORDERING INFORMATION
Type No.

Access Time

HM62832UHP·15
HM62832UHP·20
HM62832UHLP·15
HM62832UHLP·20
HM62832UHJP·15
HM62832UHJP·20
HM62832UHLJP·15
HM62832UHLJP·20

15 ns
20ns
15 ns
20 ns
15 ns
20ns
15 ns
20ns

Package

• PIN ARRANGEMENT
3oo·mil, 28 pin
Plastic DIP
(Dp·28NA)

HM62832UH Series
A14
A12

3oo·mil, 28 pin
Pla.tic SOJ
(Cp·28DN)

Vee

WE

A7

A13

Aa

Aa

As

Ag

~

• PIN DESCRIPTION

An

BE

As
Pin Name

Function

A2

A{}-AI4

Address

Al

1/0{}-I/07

Data Input/Output

CS

Chip Select

WE

Write Enable

OE

Output Enable

Vee

Power Supply

VSS

Ground

A10

as

Ao
1/00
1/01

1/07
1/06
1/05

1/02
vss ---.._ _ _ _....-

1/03

I/O.

(Top View)

•

HITACHI

166 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 3 2 U H Series
• BLOCK DIAGRAM
At.

_Vee

At3

~Vss

At2
Address
Buffer

As

Memory Array
512 x 512

Row

Decoder

A7

As
A5
A.
A3

.. ...

1/00
Column 1/0

1/0
Buffer

Column Decoder

1/07

L

WE

DE
Ao

CS

As Ato

At A2

•

A"

• FUNCTION TABLE
CS

OE

WE

Mode

Vee Current

I/O Pin

H

X

X

Standby

ISB,ISB'

High-Z

Ref. Cycle
-

L

L

H

Read

lee

Dout

Read Cycle I, 2. 3

L

H

L

Write

lee

Din

Write Cycle I

L

L

L

Write

lee

Din

Write Cycle 2

Note: X: H or L

• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Unit

Vee

-0.5*2 to +7.0

V

Voltage on any Pin Relative to VSS*'

VT

-0.5*2 to Vee +0.5

V

Power Dissipation

PT

1.0

W

Supply Voltage*'

Operating Temperature

Topr

oto +70

cC

Storage Temperature

Tstg

-55 to +125

Storage Temperature Under Bias

Tbias

-10 to +85

°C
cC

Notes I. With respect to VSS
2. Vee and VT min = -2.5V for pulse width ~ 10 ns

• RECOMMENDED DC OPERATING CONDITIONS (Ta =0 to +70°C)
Item

Symbol

Vee
Supply Voltage
VSS
I!IJlut High (Lo~c I) Voltage
VIH
Input Low (Lo~ic 0) Voltage
VIL
Note * I. VIL min = -2.0V for pulse width ~ 10 ns

•

Min

Typ

Max

Unit

4.5
0
2.2
-0.5*1

5.0
0

5.5
0
Vee +0.5
0.8

V
V
V
V

-

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300 167

HM62832UH Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • DC CHARACTERISTICS (Ta =0 to +70°C, Vcc
Symbol

Test Conditions

Typ*1

Max

Unit

IILlI

VCC = S.SV, VIN = VSS to VCC

-

-

2.0

!LA

IILOI
ICCI (-IS)*3
ICC2(-IS)
ICCI (-20)
ICC2 (-20)

CS = VIH, VI/O= VSS to VCC
Min. Cycle
2 x Min. Cycle"2
Min. Cycle
2 x Min. Cycle

-

-

-

13S
100
120
90

2.0
170
120
ISO
110

!LA
rnA
rnA
rnA
rnA

Item
Input Leakage Current
Output Leakage Current

Operating V CC Current

=5V ± 10%, Vss =OV)
Min

-

ISB (-IS)

CS = VIH. Min. Cycle

-

40

60

rnA

ISB (-20)

CS = VIH, Min. Cycle

-

30

SO

rnA

ISB I (L-version)

CS ? VCC -D.2V, OV"; Vin"; 0.2V
or VCC -D.2V"; Yin

-

O.oz

2.0

rnA

-

0.003

0.1

rnA

Output Low Voltage

VOL

IOL=8 rnA

-

-

0.4

V

Output High Voltage

VOH

IOH =-4.0 rnA

2.4

-

-

V

Standby VCC Current
Standby Vcc Current (I)

• CAPACITANCE (Ta =25°C, f
Item

= 1.0 MHz)* I

Symbol

Output Capacitance

Min

Cin

-

COUT

-

Input Capacitance

Typ

Max

Unit

6

pF

VIN=OV

10

pF

VI/O=OV

-

Test Conditions

Note * I. This parameter is sampled and not 100% tested.

• AC CHARACTERISTICS (Ta

•
•
•
•

=0 to +70°C, VCC 5V ± 10%, unless otherwise noted.)

Input pulse levels: VSS to 3.0V
Input rise and fall times: 4ns
Input and Output timing reference levels: 1.SV
Output load: See figures
Output Load (B)
tWHZ & tow)

Output load (A)

(for tCHZ.

+5V

Dout

=d

2550

m

4800
30pF'

Note: • Including scope & jig .

• READ CYCLE
Item

Symbol

Read Cycle Time

tRC

Address Access Time

tAA

HM62832UH-15

HM62832UH-20

Min
15
-

Min
20
-

Max
15

Max
-

Unit
ns

20

ns

20

ns

3

-

ns
ns

0

10
-

tACS
tCLZ'1

-

Output Enable to Output in Low-Z

tOE
tOLZ*)

Chip Deselection to Output in High-Z

tCHZ*)

0

7

0

10

ns

Chip Disable to Output in High-Z

tOHZ')

0

7

0

10

ns

Output Hold from Address Change

3

-

3

Chip Selection to Power Up Time

tOH
tpu

-

tPD

0
-

ns

Chip Deselection to Power Down Time

0
-

20

ns

Chip Select Access Time
Chip Selection to Output in Low-Z
Output Enable to Output Valid

3

15

8

0

-

-

15

-

_HITACHI
168 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

ns

ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 3 2 U H Series

• READ TIMING WAVEFORM (1) *1, *2

..
Address

tRC

..

..

tAA

OE
tOE
.. tOlZ

---

CS

tACS

..

tClZ

..

..

Dout

Address

Dout

cs

~"

,) It'

..

Dout

..

tACS
tClZ

--tpu

KXx)k

tCHZ ..

Data Valid

"

/

tpo

~~~r~~~PIY·· .. ··I~~······ .... ·· .. · ····},~OO-YO--------------~
ISB

Notes:

----

I. Transition is measured ± 200 mY from steady state voltage with Load (B). This parameter is sampled and not 100% tested.

2. WE is high for read cycle.
3. Device is continuOlL'ly selected. CS = YIL.
4. Address valid prior to or coincident with CS transition low
5. OE=YIL.

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300 169

HM62832UH Series - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ __

• WRITE CYCLE
Item

Symbol

Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write

twe
tew
tAW

Address Setup Time
Write Pulse Width

tAS
twp

Write Recovery Time
Output Disable to Output in High-Z*I
Write to Output in High-Z*I
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End ofWrite*1

HM62832UH-15

HM62832UH-20

Min
15
10
13

Min
20
12

0
10

tWR
tOHZ
tWHZ
tDW

0
0
0
8

tDH

0

tow

3

Max

-

-

Max

15
0
12
0

7
7

0
0
10

-

0
3

Unit

-

ns
ns

10
10

ns
ns

-

ns
ns

ns
ns
ns
ns

ns

• WRITE TIMING WAVEFORM (1)

Address

tow

Dout
tDW

Din

..

-----I
1/03 o---r-Hif-Cl--I Input
1/04 o---...H+H}--I Data

Column Decoder

Control

1/05

1/06

Column 1/0

o--rttH+f-Cl--I

W:. W:. W:. W:. W:. W:. W:.

:~~: :::::~~~tR~~~~=~.:.:
~':::At~bt~,;.~,.,~b3.:,.,b<4,.,~b2~
--,

-

cs

WE
OE

-

• TRUTH TABLE
Input

CS
H
L
L
L
L

WE
X
H
H

OE
X
H

L
L

H

L
L

Output

Mode

VCC Current

Ref. Cycle

HighZ
HighZ
Data Out
Data In
Data In

Not Selected
Output Disable
Read
Write
Write

ISB,ISB)
ICC, ICC)
ICC, ICC)
ICC, ICC)
ICC, ICC)

Read Cycle (1,2,3)
Write Cycle (1,2,3,4)
Write Cycle (5,6)

• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Voltage on any Pin Relative to VSS')
Power Dissipation
Operating Temperature Range
Storage Temperature Range (with bias)
Storage Temperature Range

Unit

Rating

,,,..,,.,
'"''

S
I V. oIt
'- upp.y
__age *)

VT

PT
Topr
Tstg(bias)
Tstg

- V . J LV T/.U

V

-0,5 to VCC +0.5
1.0
oto +70
-10 to +85
-55 to +125

V

W
°C
°C
°C

Notes I. With respect to VSS
Under the DC and AC specifications shown in the Tables, this device is tested under the minimum transverse air flow exceeding 500
linear feet per minute.

• RECOMMENDED DC OPERATING CONDITIONS (OOe S; Ta S; 70°C)
Item
Supply Voltage
Input High Voltage
Input Low Voltage
Note I. Pulse width 10 ns, DC: -O.5V

Symbol

Min

Typ

Max

Unit

VCC
VSS
VIH
VIL

4.5
0
2.2
-3.0 1

5.0
0.0

5.5
0.0
VCC+0.5
0.8

V
V
V
V

•

-

-

HITACHI

174 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 7 8 3 2 S H Series
• DC AND OPERATING CHARACTERISTICS (VCC = 5.0V ± 10%, VSS = OV, Ta = 0 to +70°C)
Symbol

Item

HM67832-10

Test Conditions

Min
Input Leakage Current
Output Leakage Current

Min

Unit

Max

iJA

Ilul

Vee = 5.5V, VIN = OV to Vee

-

2

-

2

IILOI

es = VIH orOE =, VIH. WE = VIL
VI/OOV to Vec

-

10

-

10

iJA

CS = VIL. 11/0 = a rnA
15 ns Cycle, !rIO = a rnA
CS = VIH. VIN = VIH or VIL
CS::> VCC -O.2V, VIN" 0.2V or
VIN::> Vee -O.2V

-

200
150
40

-

195

rnA

-

140
40

rnA
rnA

-

30

-

30

rnA

10L= 8 rnA
10H =-4 mA

-

0.4

-

0.4

2.4

-

2.4

-

V
V

Operating Power Supply Current

ICC

Average Operating Current

ICCI
ISB

Standby Power Supply Current
ISBI
Output Low Voltage
Output High Voltage

Max

HM67832-12

VOL
VOH

-

-

• AC CHARACTERISTICS (VCC = 5V ± 10%, Ta = O°C to 70°C unless otherwise noted.)
• Read Cycle
Item

Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Selection to Output in Low Z
Output Enable to Output Valid
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Hold from Address Change
Notes

I.
2.

HM67832UH-IO

HM67832UH-12

Min

Min
12

Max

10

-

tAA
tACS
tLZ I. 2

-

IO
10

tOE
tOLZ I.2

-

tRC

tHZ I . 2

-

3
0
0
3

5
-

5

-

4

Max

ns

12
12

ns

-

os

-

a
a

4
tOH
This parameter is sampled and not 100% tested.
Transition is measured ± 200 mV from steady state voltage with specified loading in Load (B).

Unit

-

6

ns
ns

-

ns

5

ns

-

ns

• Write Cycle
Item

Symbol

HM67832UH-IO
Max

Write Cycle Time

tWe'

Min
II

Chip Selection to End of Write
Address Valid to End of Write

tcw
tAW

8
10

-

Address Setup Time
Write Pulse Width

tAS
twp

0

-

8

Write Recovery Time

tWR

Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Disable to Output in High Z
I.
2.
3

-

Min
12

Max
-

Unit
ns

9
II

-

ns

-

ns

0
9

-

ns

-

-

ns

a

-

0

-

tow

6

-

6

-

ns
ns

tDH
twZ1. 3
tOIlZ2. 3

0
0
0

-

0
0
0

-

ns

6
6

ns
ns

5
6

tOW 2. 3
4
4
All Write Cycle timings are referenced from the last valid address to the first transitioning address.
This parameter is sampled and not 100% tested.
Transition is measured ± 200 mV from steady state voltage with specified loading in Load (B) .

Output Active from End of Write
Notes

-

HM67832UH-12

•

-

ns

HITACHI

Hitachi America, Ltd . • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300 175

HM67~HSeries--------------------------------------------------------

• CAPACITANCE (Ta = 25°C. f= 1 MHz.)
Item
Input Capacitance
Input/Output Capacitance

Symbol
Cin l

Max

Unit

6

pF

Test Condition
Vin=OV

CI/OI

10

pF

VI/O=OV

Note: I. This parameter is sampled and not 100% tested.

•
•
•
•
•
•

AC TEST CONDITIONS
Input pulse levels: VSS to 3.0V
Input timing reference levels: 1.5V
Output load: See figure
Input rise and fall times: 4ns
Output lreference levels: 1.5V
+5V

+5V

» 4800

4800
Output

Output

J.
30pF*

2550

2550

5pF*

7?7
Output Load (8)
(for tHZ, tLZ, tOHZ. tOLZ. twz. & tow)

777
Output Load (A)

.includes scope and jig capacitance

•

HITACHI

176 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM67832SH Series
• TIMING WAVEFORMS
• Read Cycle _11

.
Address

..

Data Out
High Impedance
Notes I.

WE = VIH.

• Read Cycle _21, 2, 3

RC

)K

)K

Address

tOH
Data Out

Notes I.
2.
3.

Previous Data Valid

tAA

::KX)()(

tOH
Data Valid

X

WE = VIH.
CS=VIL.
OE=VIL

• Read Cycle -31, 2, 3

't

tAC

'-y

t_AC_·~~:~~~~~::·thl=tLZ=:::;:;-----D-at-a-v:'~ ';d<

.. IAI

Data vali~

>K....,X,.....X........-X,....X
..........X.....X
.....

High Impedance
Data Out
Note

I.

A write occurs during the overlap of a low CS and a low WE (twP) .

•

HITACHI

178 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

--------------------------------------------------------HM67832SHSeries
• TIMING WAVEFORMS
• Write Cycle -3 1, 2 (OE = Clocked, WE Controlled)
twc
Address

tcw

twp

[1]

High Impedance

Data Out
tDW

High Impedance

Data Valid

Data In

High Impedance

Notes I. A write occurs during the overlap of a low CS and a low WE t(WP).
2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not
be applied.

• Write Cycle -41, 2 (OE = Clocked, CS Controlled)

..

twc

Address

Data In
Data Out
Notes I.
2.

High Impedance

A write occurs during the overlap of a low CS and a low WE (twP).
If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in a high
impedance state.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 179

HM67~HSeries-----------------------------------------------------

• TIMING WAVEFORMS
• Write Cycle -51, 2, 3, 4 (OE = L, WE Controlled)
wc

)K

)K

Address

I

tcw

}I/jj /,

\\\\\\\\\\\\l\'{
tAW

tWR

I

twp

tWR

" " " " " " " " " " " "/ "I/1

/////// /

Data In

/

/

[1]

1/

'1\\r-..
Data Out

'77777777

High Impedance

/

High Impedance

tWR
tWR

[2]

tOH

tow

/)K
"

X Data Vaidr

131

/

,,1/\'7\T
/~

"

[4]

)K"
/

High Impedance

Notes I. A write occurs during the overlap of a low CS and a low WE t(WP).
2. During this period, I/O pins are output state so that the input signals of opposite phase to the outputs must not
be applied.
3. Output data is the same phase of write data of this write cycle.
4. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs
must not be applied to them.

• Write Cycle -61, 2 (OE

Address

CS

= L, CS Controlled)
twc

1ft

tcw

tAW [.c

twp

[1]

WE
twz
High Impedance
Data Out

Data In

Notes I.
2.

High Impedance

<:t

tow

.. I~*
=XXXXXX

Data Valid

A write occurs during the overlap of a low CS and a low WE (twP).
If the CS low transition occurs after the WE low transition, output remain in a high impedance stale .

•

HITACHI

180 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

HM6208H Series
65536-Word x 4·BH High Speed CMOS Static RAM
The Hitachi HM6208H is a high speed 256k static RAM organized
as 64k-word x 4 bit. It realizes high speed access time (25/35) and
low power consumption, employing CMOS process technology and
high speed circuit designing technology. It is most advantageous
wherever high speed and high density memory is required, such as
the cache memory for main frame or 32-bit MPU.
The HM6208H is packaged in the industry standard 300-mil, 24
pin, plastic DIP. The HM6208H is also available in a 300-mil, 24 pin,
plastic SOJ package for high density mounting. The low power versions are ideal for battery backed systems.

IDP·24NC)

Features
• Single 5 V supply and high density 24-pin package
• High speed:
Access time 25/35 ns (max.)
• Low power
Active:
300 mW (typ.)
100 p.W (typ.)
Standby:
30 p.W (typ.) (L-version)
• Completely static operation requires
No clock or timing strobe
• Access and cycle times are equivalent
• All inputs and outputs TTL compatible
• Capability of battery back up operation (L-version)

ICp·24D)

Pin Arrangement

AO

)

V,ss

12

24

Vee:

Ordering Information
Access Time
25 os
35 os
25 os
35 us
25 os
35 os
25 os
35 os

Type No.
HM6208HP-25
HM6208HP-35
HM6208HLP-25
HM6208HLP-35
HM6208HJP-25
HM6208HJP-35
HM6208HJLP-25
HM6208HJLP-35

Package
300-mil
24-pio
plastic DIP
(DP-24NC)
300-mil
24-pio
plastic SOJ
(CP-24D)

Pin Description
Pin Name
Function
J\(f:A1s--Address -

I701~
CS
WE
Vee
Vss

Inpul/Vrr-O.2V

-

-

10

-

-

10

rnA

Output Low Voltage

VOL

IOL=8 rnA

-

-

0.4

-

-

0.4

V

Output High Voltage

VOH

IOH=-4 rnA

2.4

-

-

2.4

-

-

V

Standby Power Supply Current

• AC CHARACTERISTICS (Vcc=5 V ± 10%, Ta=O to +70°C, unless otherwise noted.)
• Read Cycle
Symbol

Item

HM6708A-15

HM6708A-20

HM6708A-25
Max.

Unit

Min.

Max.

Min.

Max.

Min.

tRe

15

-

20

-

25

-

ns

Address Access Time

tAA

-

15

-

25

ns

tAes

-

15

-

20

Chip Select Access Time

20

-

25

ns

-

5

-

5

-

ns

Chip Selection to Output in Low Z

toH
tLZ I),2)

4
4

-

5

-

5

-

ns

Chip Deselection to Output in High Z

tHZ I),2)

0

6

0

8

5

10

ns

Read Cycle Time

Output Hold from Address Change

NOTES:

1. This parameter is sampled and not 100% tested.
2. Transition is measured ±200 mV from steady state voltage with specified loading in Load(B) .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 89

HM6708A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Write Cycle
Item

Symbol

HM6708A-15

HM6708A-20

HM6708A-25

Min.

Max.

Min.

Max.

Min.

Max.

25

-

ns

20

-

ns

20

-

ns

0

-

0

-

ns

15

-

20

-

ns

0

ns

twei)

15

-

20

Chip Selection to End of Write

tcw

10

-

15

Address Valid to End of Write

tAW

10

15

tAs

0

-

Write Cycle Time

Address Setup Time

Unit

twp

10

Write Recovery Time

tWR

0

-

0

Data Valid to End of Write

tDW

8

10

-

12

0

0

-

0

-

Write Enable to Output in High Z

tDH
twz2),3)

-

0

6

0

8

0

10

ns

Output Active from End of Write

tow2),3)

0

-

0

-

0

-

ns

Write Pulse Width

Data Hold Time

NOTES:

I. All write cycle timings are referenced from the last valid address to the first transitioning address.
2. This parameter is sampled and not 100% tested.
3. Transition is measured ±200 mV from steady state voltage with specified loading in l.oad(B) .

• CAPACITANCE (Th=25°C, f=IMHz)
Item

Symbol
CIN 1)

Max.

Unit

Test Condition

Input Capacitance

6

pF

V1N=OV

Output Capacitance

CII0 1)

10

pF

Vila =0 V

NOTES:

I. This parameter is sampled and not 100% tested .

• AC TEST CONDITIONS
• Input pulse levels: V55 to 3.0 V
• Input timing reference levels: 1.5 V
• Output Load: See figure

• Input rise and fall times: 4ns
• Output reference levels: 1.5 V

+5V

+5V
Dout

Dout

2550

2550

4800
5 pF *

Output Load B
(for tHZ ' t LZ , twz &

Output Load A

low)

*Including scope and jig capacitance.

•

HITACHI

190 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

ns
ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM6708A Series
• TIMING WAVEFORM
• Read Cycle (1) (1) (2)

Address
tOH

Data Out

Previous Data Valid

Data Valid

• Read Cycle (2) (1) (3)

tAC

cs

~I\.

~

tHZ

tACS
tLZ

Data Out

NOTES:

V:XX'\V
I"'
.I"

Hi9h 1mpedance

It"

Data Valid

"' Hi9h

/

Impedance

I. WE is High for READ cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 191

HM6708A g e r l e 8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• Write Cycle (1) (WE Controiled)

twc

Address

cs
WE

Din
High Impedance

Dout

• Write Cycle (2) (CS Controiled)

twc

Address

)K

)K
tAW
tAS

i

cs

tWR'2

tcw

/IC

.

WE

Data In
High Impedance (2)
Dout
NOTES:

I. A write occurs during the overlap of a low CS and a low WE (twp).
2. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
3. During this period, 1/0 pins are in the output state so that the input signals of opposite phase to the outputs must not
be applied.
4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output
buffers remain in a high impedance state.
5. If CS is low during this period, 1/0 pins are in the output state. Then the data input signals of opposite phase to the
outputs must not be applied to them.
6. Output data is the same phase of write data of this write cycle.

_HITACHI
192 Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819. (415) 589-8300

HM6708SH Series - - - - - - - - - - P r e l i m i n a r y
65,536-words x 4-Bit High Speed Static Random Access Memory

,

• FEATURES
•
•
•
•
•
•
•
•

65,536-words x 4 bit organization
Directly TTL compatible input and output
0.8 ~ Hi-BiCMOS process
+5V single supply
Completely static memory
No clock or timing strobe required
Low power dissipation (DC) operating: 400mW typ
Super fast access time: 10/12ns (max)

Organization

Access Time

HM6708SHJP-to
HM6708SHJP-12 64k x4

• PIN ARRANGEMENT
HM6708SH Series

• ORDERING INFORMATION
Type No.

iCP-24D)

to ns
12 ns

Package

Ao

1

24

Vcc

2
3
4

23
22
21

A,S

300 mil 24 pin
Plastic SOJ
(CP-24D)

A,
A2
A3
~

5
6
7
8
9
10
11
12

20
19
18

• PIN DESCRIPTION
Pin Name

Function

Ao-AI5

Address Input

A5
A6
A7

1/01-1/04

Data Input/Output

As

WE

Write Enable

Ag

Chip Select

CS

VSS

Ground

VSS

Vee

Power Supply

NC

Not Connect

CS

A'4
A'3
A'2
A'1
A,o

17

liD,

16

1/02

15
14
13

1/03
1/04

WE

(Top View)

As
As
A7
A6
As
A4
A3
A2

Memory Matrix
256 X 1024

1/0,

Column 1/0

-aVec
-aVss

1/02
1/03
1/04
A'3 A'2 A11 A'0 A'4 A,S Ao A1

CS
WE

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 193

HM6708SH Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TRUTH TABLE
Input
Output

Mode

VCcCurrent

Ref. Cycle

X

HighZ

H

Dout
HighZ

Not Selected
Write "0"

ISB,ISBI
ICC,ICCI

Read Cycle (2), (3)

Write "I"

Icc,leel

Write Cycle (I), (2)

CS
H
L

WE

L

L

-

• ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage 1

Symbol

Voltage on any Pin Relative to VSS
Power Dissipation
Operating Temperature Range
Storage Temperature Range (with bias)
Storage Temperature Range
Note:

Unit

Rating
-0.5 to +7.0

Vee
Vt

V

-0.5 to Vee +0.5

V

1.0
o to +70

W

Pt
Tppr
Tstg (bias)

°c
°c
°c

-10 to +85
-55 to +125

Tstg

I. With respect to VSS.

Under the de and ac specifications shown ing the Tables, this device is tested under the minimum trasverse
air flow exceeding 500 linear feet per minute.

• RECOMMENDED DC OPERATING CONDITIONS (OOe S; T a S; 70°C)
Item

Symbol

Min.
4.5

Typ

Vee
VSS
VIH

0.0
2.2

0.0

Input High Voltage
Input Low Voltage

VIL

-3.0 1

Supply Voltage

5.0

Max.
5.5

Unit
V

0.0

-

Vee +0.5

V
V

-

0.8

V

Note: I. Pulse width IOns, DC: -0.5V

• DC AND OPERATING CHARACTERISTICS (VCC =S.OV ± 10%, VSS =OV, Ta =0 to + 70°C)
JO
Item

Symbol

12

Test Conditions

Unit
Min.

Typ.

Max.

Min.

Typ.

Max.

Input Leakage

i ILl I

Vee = 5.5V, VIN=OV to Vce

-

-

2

-

-

2

~

Output Leakage
Current

IILOI

CS =VIH or OE = VIH, WE =VIL
VIa = OV to Vee

-

-

10

-

-

10

~

Operating Power
Supply Current

ICC

CS = VIL. II/a = OmA

-

60

JOO

-

60

JOO

mA

Average Operating
Current

ICC I

15ns cycle, II/a = OmA

-

130

180

-

120

175

mA

ISB

CS = VIH, VIN =VIH or VIL

-

-

40

-

-

40

mA

ISBI

CS k

Data Valid

tOH

=:-kxxxxxxxx

High Impedance
Data Out
Note:

I. A write occurs during the overlap of a low CS and a low WE (twp).

Write Cycle -2 1

..

twc

Address
t AS 1..._---l~...I-----_t"'c.!.!w-----~

cs
[11

WE

/
tow

Data In

xxxxxxxxXXXXXXXX>k

..

Data Valid

I

tDH

:3kxxxxxxxxx

High Impedance
Data Out
Note:

I. A write occurs during the overlap of a low CS and a low WE (twp) .

•

HITACHI

198 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

-------------------------------------------------------HM67~HSeries

Write Cycle - 3 1, 2

.
Address

.

twc

'\/
/,

~~

f'\.

..

tcw

/111 /111111

\\\\\\\ ,\\\t

..

tAs

I
WE

[2]

I

tWR

[1]

twp

It

\\\

[2]

High Impedance

"

Data Out

Data In

..

tAw

L

/

'\.

tow

tOH J

I

I

/J!l

High Impedance

High Impedance

*X)

Data Valid

Notes: I. A write occurs during the overlap of a low CS and a low WE (twp).
2. During this period, I/O pins are in the output state so that the input state of
opposite phase to the outputs must not be applied.

Write Cycle - 4 1,2 (OE = Clocked CS Controlled)

twc
Address

)K

..... It'
/1'\.

..j~1 I I
/111111
..

tcw

\\\\\\\ ,\\\t

cs

.

I

WE

[2]

Data In

twp

I

tWR

[1]

lL

\\\

"

Data Out

Note:

tAW
tAS

[21

High Impedance

L

/
High Impedance

'\

tow

I

Vce-0.2 V

Output Low Voltage

VOl

101 =8 rnA

-

Output High Voltage

VOH

IOH=-4 rnA

2.4

CS=Vn , ImTT=O rnA
min. cycle, Duty: 100%,
ImTT=O rnA

2

-

10

Operating Power Supply Current

Vrr=5.5V, VIN=OVtoV ee
CS=V1H, VOTJT=O V to Vee

-

-

IILTI
IIwl

-

Unit

-

-

Input Leakage Current
Output Leakage Current

ISB

HM6707 A-20125

Min. Typ. Max. Min. Typ. Max.
2

• AC CHARACTERISTICS (Vee=5 V ± 10%, Ta=O°C to 70°C, unless otherwise noted.)
• Read Cycle
Item

Symbol

HM6707A-15

HM6707A-20

HM6707A-25

Min.

Max.

Min.

Max.

Min.

Max.

Unit

15

-

20

-

25

-

ns

-

15

-

20

-

25

ns

15

20

ns

4

4

-

ns

Chip Selection to Output in Low Z

-

Chip Deselection to Output in High Z

tH71 ),2)

0

6

5
5
0

25

tOH
tI71 ),2)

5
5
0

10

ns

Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change

NOTES:

hw
tAA
tA(",<:

8

ns

1. This parameter is sampled and not 100% tested.

2. Transition is measured ±2oo mY from steady state voltage with specified loading in Load(B) .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819· (415) 589·8300 225

HM6707A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Write Cycle
Item

Symbol

Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
NOTES:

twrl)
trw
tAW
tAS
twp
tWR
tDW
tDH
tWZ2),3)
tow2),3)

HM6707A-15
Max.

Min.
15
10
10
0
12
0
10
0
0
0

HM6707A-20
Min.
Max.
20
15
15
0
15
0
10
0
0
8
0

-

HM6707A-25
Min.
Max.

-

-

6

-

-

25
20
20
0
20
0
12
0
0
0

-

Unit

10

ns
ns
ns
ns
ns
ns
ns
ns
ns

-

ns

-

-

I. All write cycle timings are referenced from the last valid address to the first transitioning address.
2. This parameter is sampled and not 100% tested.
3. Transition is measured ±200 mY from steady state voltage with specified loading in Load(B) .

• CAPACITANCE (Th=25°C, f=IMHz)
Item
Input Capacitance

Symbol
CIN I )
COUTl)

Output Capacitance
NOTES:

Max.
6
10

Test Condition

Unit
pF
pF

VIN=OV
VOUT=OV

I. This parameter is sampled and not 100% tested .

• AC TEST CONDITIONS
• Input pulse levels: VSS to 3.0 V
• Input timing reference levels: 1.5 V
• Output Load: See figure

• Input rise and fall times: 4ns
• Output reference levels: 1.5 V

+5V

+5V
nnllt

l4800

-:~3DPF'

nnllt

l 4800

-~~5PF'
Output Load B
(for tHZ. Ill' twz &

Output Load A

low)

*Including scope and jig capacitance.

_HITACHI
226 Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300

- - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM6707A Series
• TIMING WAVEFORM
• Read Cycle (1)

(1)

Address
tOH

Data Out

Previous Data Valid

Data Valid

• Read Cycle (2) (2)

RC

cs

)/

~I'..
tACS
tLZ (3)

tHZ(3)

Data Out
High Impedence

NOTES:

KXXXXX) 1/
I"-

Data Valid

"
,/

High
Impedence

1. WE is high and CS is low for READ cycle.
2. Addresses valid prior to or coincident with CS transition low.
3. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 227

HM6707A Series - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ __
• Write Cycle (1)

(WE Controlled)

twc

)K

Address

'""""""~

cs

)K

tcw

E// / //////////fi
tAW
tAS

tWR
twp

WE

~~ t\..

;;
tOH

tow

)

Data In

I
Data Out

Data In Valid
twz

,-I

Data Undefined

)K
tow

.(1). (2)

/1 High Imped anee

V
1"\

1. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

NOTES:

2. If CS goes high simultaneously with WE high, the output remains in a high impedance state.

• Write Cycle (2)

Address

(CS Controlled)

+

_twc_>k"""----

tcw

cs

twp

WE
tow
Data In Valid

Data In

twz

~

Data Out
NOTES:

1. Transition is measured ±200mV from steady state voltage with specified loading in Load B.

•

HITACHI

228 Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

HM62932 Series

- - - - - - - - - - - - - - - - Preliminary

32,768-Word x 9-Bit High Speed CMOS Static Ram
• FEATURES
• High speed: fast access time 15/20 ns (max)
• Low Power
Standby: 15!1W (typ.) (L-version)
Operation: 350mW (typ.)
• Single 5V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output-Three
state output
• Directly TTL compatible-All inputs and outputs

(CP-32DN)

• PIN ARRANGEMENT
HM62932 Series

• ORDERING INFORMATION
Type No.
HM62932JP-15
HM62932JP-20
HM62932UP-15
HM62932UP-20

Access

Package

15 ns
20ns
15 ns
20ns

300 mil 32 pin
Plastic SOJ
(CP-32DN)

A'2

cs,
IIOg

I/o.
1/07
1/06
1/05

(Top View)

• PIN DESCRIPTION
Pin Name

Function

Ao--AI4

Address

VOJ-l/09

Data Input/Output

CSI

Chip Select I

CS2

Chip Select 2

WE

Write Enable

OE

Output Enable

Vee

Power Supply

VSS

Ground

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 229

HM6~Series----------------------------------------------------• BLOCK DIAGRAM

A14

......
1----

Vee

A13

......
1----

Vss

A12

Row
Address
Buffers

AS
A7

Memory Array
32Kx 9

Row
Decoder

A6

A5
A4
A3

1/01

I/O
Buffer

f--

Column I/O
Column Decoder

1/09

I

WE

L

I
Column Address Buffer

I

I

I

I

I

I

CS1
CS2

• FUNCTION TABLE

CSl

CS2

~

WE

Mode

Vee Current

H

X

X

X

Standby

ISB,ISBI

I/O Pin
High-Z

L

L

X

X

Standby

ICC

High-Z

-

L

H

H

H

Output Disable

ICC

High-Z

-

L

H

L

H

Read

ICC

Dout

Read Cycle 1,2,3

L

H

H

L

Write

ICC

Din

Write Cycle I

L

H

L

L

Write

ICC

Din

Write Cycle 2

Note:

Ref. Cycle

-

X: H or L

_HITACHI
230 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 9 3 2 Series
• ABSOLUTE MAXIMUM RATINGS
Hem

Symbol

Value

Vee

-0.5 2 + 7.0

Voltage on any pin relative to VSSI

VT

-0.5 2 to Vee + 0.5

V

Power Dissipation

PT

1.0

W

Supply Voltage I

Unit
V

Operating Temperature Range

Topr

oto +70

°C

Storage Temperature

Tstg

-55 to +125

°C

Storage Temperature Under Bias

Tbias

-10 to +85

°C

Note: I. With respect to VSS
2. Vee and VT min = -2.5V for pulse width IOns

• RECOMMENDED DC OPERATING CONDITIONS (Ta =0 to +70°C)
Item

Symbol

Min.

Typ

Max.

Unit

Vee

4.5

5.0

5.5

V

VSS

0

0

0

V

Input High (Logic I) Voltage

VIH

2.2

-

Vee+0.5

V

Input Low (Logic 0) Voltage

VIL

-0.5 1

-

0.8

V

Supply Voltage

Note:

I.VIL mm = -2.0V for pulse wtdth IOns.

• DC CHARACTERISTICS (Ta = 0 to +70°C, VCC = 5V ± 10%, VCC = OV)
Typl

Max.

Unit

Test Conditions

Input Leakage Current

IILlI

-

-

2.0

J.IA

Vee =5.5V., Yin = VSS to Vee

Output Leakage Current

IILOI

-

-

2.0

J.IA

Output Disable
VI/O = VSS to Vee

Operating Vee Current

ICC

-

70

TBD

mA

CSI =VlL
lout = 0 mA, min. cycle

Standby Vee Current

ISB

-

30

TBD

mA

CS 1 = VlH, min cycle

ISBl
(L-version)

-

0.02

2.0

mA

*2

-

0.003

0.1

VOL

-

Item

Symbol

Standby Vee Current (I)

Min.

-

0.4

V

IOL= 8 mA

2.4
Output High Voltage
VOH
Note:
I. Typtcal hmlts are at Vee = 5.0 V, Ta = 25°C and specified loadmg.
2. CSI Vee-O.2V, OV Yin 0.2V or Vee-O.2V Yin

V

IOH =-4.0 mA

Output Low Voltage

• CAPACITANCE (Ta = 25°C, f= 1.0 MHz)1
Max.

Unit

Input Capacitance

Cin

-

-

6

pF

Vin=OV

Output Capacitance

Cout

-

-

10

pF

VI/O=OV

Item

Symbol

Min

Typ.

Test Conditions

Note: I. This parameter is sampled and not 100% tested.5

. . . . ITACHI
Hitachi America, Ltd . • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 231

HM62932 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • AC CHARACTERISTICS (Ta

=0 to +70°C, VCC 5V ± 10%, unless otherwise noted.)

Test Conditions
• Input pulse levels: Vss to 3.0V
• Input rise and fall times: 4ns
• Input and Output timing reference levels: 1.SV
• Output load: See figures
+5V

+5V

4800
Dout

4800

C>----t---+

2550

Dout

30pF'

C>----t---+
5pF'

2550

Output Load (8)
(for t cHz, tCLZ, tWHZ & tow)

Output Load (A)
• Including scope & jig,

• READ CYCLE
Item

HM62932-15
Min
Max
15
-

HM62932-20
Min
Max
20
-

-

15

20

ns

15

-

20

!CO2
tCLZl l
tCLZ2 1

-

7

-

10

ns
ns

3
0

-

3
0

-

ns
ns

tOE

-

-

10

0
0

-

ns
ns

Symbol

Read Cycle Time

tRC

Address Access Time

tAA

Chip Select Access Time

tCOI

Chip Selection to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip deselection to Output in High-Z
Chip Disable to Output in High-Z
Output Hold from Address Change

tOLZ I
tCHZI, tCHZ2*1
tOHZ l
IOH

0
0
0
3

7

7
7

-

0
3

10
10
-

Unit
ns

ns
ns
ns

_HITACHI
232 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM62932 Series

• READ TIMING WAVEFORM (1)1,2

..

Address

RC

-----

==>K.

-~.----...

)K

Address Valid
tAA

------

"""""""""

/ / V///////
tC01
tCLZ1

tCHZ1

-...

////////////

:"'."'. f\. "'."'."'."'."'.'\ "tC02
tCHZ2

~g--

"""""""""""'\.'\.

DE

f-/ / V///////
tOE

High Impedance

tOHZ

-------

tOLZ

~

C)K

Dout

)C)-

Data Valid

• READ TIMING WAVEFORM (2)*2,*3,*5

Address

Address Valid
I~.'------------~

tOH I~.'--___
"-I

Dout

Data Valid

• READ TIMING WAVEFORM (3)*1, *2, *4, *5

CS1

r

CS2

.

tC01

•
~I I

Iv'

\ttC02
tCHZ2

tCLZ2

Dout
Notes:

tCHZ1

tCLZ1

High Impedance

kxxxxxx~---D-a--ta--Va-lid----tOH

Dout

..
..

RC

tALH

..

• READ TIMING WAVEFORM (3)1,2,4,

...

....

t Rc

. ..

tALE

tALL

..,

-'

ALE

..

Address

) (

tAHL

..

..

tAA

...

tCOl
tCLZl

////////////

..

.

.
)

Address Valid

,,"'''''''''''''''''''''''''

CS2

..

tASL

...

K:

,v" V//////

.
-I\.

tOHZl

.

'\.'\.'\.'\. ,,'\

t002
tOLZ2
tOLZ2

-:1/'

,,"'''''''''''''''''''''''''

tOHZ

tOLZ

Dout
Notes:

V//// / /

tOE

High Impedance

0<

t

Data Valid

---

I. Address inputs are latched on the falling edge of ALE. When ALE is high, the latch is transparent.
2. WE is high for read cycle.
3. CSI = VIL, CS2 = V(H, and OE VIL.
4. Transition is measured ± 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested .

=

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 241

HM62D932 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • WRITE CYCLE
Parameter

HM62D932-20

HM62D932-15

Symbol

Min

Max

Min

Max

Unit

Write Cycle Time

twe

15

-

20

-

ns

Chip Selection to End of Write

tew

10

-

12

-

ns

Address Valid to End of Write

tAW

13

-

15

-

ns

Address Setup Time

tAS

0

0

twP

10

12

-

ns

Write Pulse Width

-

Write Recovery Time

tWR

0

-

0

-

ns

Output Disable to Output in High-Z

tOHz4

0

7

0

10

ns

Write to Output in High-Z

tWHz4

0

7

0

10

ns

Data to Write Time Overlap

tDW

8

-

10

ns

Data Hold From Write Time

tDH

0

-

0

-

Output Active from End of Write

toWl

3

-

3

-

ns

Address Latch Enable High Time

tALH

5

6

tALL

5

Address Setup to Latch low

tASL

3

-

ns

Address Latch Enable Low Time
Address Hold to Latch Low

tAHL

3

-

-

ns

6
4
4

ns

ns

ns
ns

• WRITE TIMING WAVEFORM (1)1.2.3.4

...

.

ALE

.-

..,

...

tALL

..,

~I<-

.

tASL

Address

-----.-

we
tALH

)

......

tAHL

Address Valid

i'...

...

..

CS1

,,"''\.'\.'\.'\.'" I'\. '\. '\.

CS2

/ / / / / / // / /

- ..

tAW
tew

--,

>k
tWR

//////////

k- ' "' " ' "' " ' "' " ' "' "' " '\

'"'"'"'"

/ / / / / / V..,ftAS

WE

twp

'"'."'"~

~ ~'"
...

'\

..,//////////

tOHZ*S

Dout

." '" -" " "" " " " "

'//////// /

High Impedance

//

...

Din

--------------ct
•

tDW

.. ... ..

Data Valid

tDH

ixxxxx

HITACHI

242 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------------------------------HM62~Series

• WRITE TIMING WAVEFORM (2)1,2,3,4

..

....

twc

.. ..

tALH

tALL

-;

ALE

..

tASL

Address

) I.(r\..

...

tAHL

~ ,/
/ '\..

Address Valid

tWR

tcw

CS1

CS2

i~~\\\\ I\\\~

-;

IIIIIII VII}

~<;\ \
twp

tAS

\ ,\~

I

--,"""""""""""

tOH

tWHZ
*5

Dout

~

tow
*6

High Impedance

/LL/////LL//

tow

(b(

Din
Notes:

\ \\\\\\\\

tAW
~

WE

// 1///////

.

tOH

Data Valid

O(XXX
...

.1

\\\\\\/\J\
I I I I I I'\/Y

I. Address inputs are latched on the falling edge of ALE. When ALE is high, the latch is transparent.
2. Transition is measured ± 200 mV from high impedance voltage with Load (B). This parameter is sampled not 100% tested.
3. a write occurs during the overlap (twp) of a low CSI, a high CS2, and a low WE.
4. If the CS I low and CS2 high transition occurs simultaneously with WE low transitions or after
the WE transition, output remain in a high impedance state.
5. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
6. If CS I is low and CS2 is high during this period, I/O pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589-8300 243

HM62D932 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • LOW Vee DATA RETENTION CHARACTERISTICS (Ta =0 to +70°C)
This characteristic is guaranteed only for L-version.
Item
Vee for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Note:

Symbol

Min

VDR

20

Typ

-

Max

-

Unit
V
j.tA

-

2

teDR

0

-

-

ns

tR

5

-

-

ms

IeeDR

50"'

Test Condition
CS, Vee--{).2V,
Vin Vee --{).2V or
OV Vin 0.2V

I. Vee = 3.0V.

Data retention mode

Vee

2.2V

VOR
OV

-------------~~~~~~~--------------------

•

HITACHI

244 Hitachi America, ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

HM628128/HM6281281 Series
131,072-Word x a-Bit High Speed Hi-CMOS Static RAM
HM628128P Series

• DESCRIPTION
The Hitachi HM628128 is a CMOS static RAM organized 128k-word
x 8-bit. It realizes higher density, higher performance and low power
consumption by employing 0.8 I'm Hi-CMOS process technology. The
HM6281281 is available in industrial temperature range (-40 to
+85°C).
It offers low power standby power dissipation; therefore, it is suitable
for battery back-up systems. The device, packaged in a 8 x 20 mm
TSOP with a thickness of 1.2 mm, 525 mil SOP (460-mil body SOP) or
a 600-mil plastic DIP, is available for high density mounting.

(DP-32)
HM628128FP Series

• FEATURES
• High Speed: Fast access time ........ .70/85/100/120ns (max.)
• Low Power
Standby: ....................... 10 I'W (typ.) (L-version)
Operation: ..............................75 mW (typ.)
• Single 5V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output: Three state output
• Directly TIL compatible: All inputs and outputs
• Capability of battery back up operation (L & SL)
2 chip selection for battery back up.

(FP-32D)

Pin Description
Pin Name
AO-A16

IJOO-l/07
CSI
CS2

WE
OB
NC
Vee
Vss

Function
Address
Input/output
Chip select 1
Chip select 2
Write enable
Output enable
No connection
Power supply
Ground

(TFP-32DA)

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 245

HM628128/HM6281281 Series
• PIN ARRANGEMENT
(DP-32 & FP-32D)
NC
AI6
AI.
All

AI5
CSl

A7

All

Vee

W£
A8

AS

A.
Al
AZ
AI
AD
1/00
1/01
1/02
V..

A9
All

O£
10
II
12

AID

CSt
1/07
1/06
1/05
I/O.
1/03

13
I.
15
16

(Top View)

(TFP-32DA)
10E

Al1
A,
A,
A13

AlO

les 1
110,
110.

!WE

CS,

1/0 5

A"
Vee
NC

1/04
110,

0

A16
A14
A12
A,

Ao
A,
A,

A"
A,

A,

Vss
1/02
VO,
1/00

0

Ao
(TnpVlf"w)

(TFP-32DAR)
A,

A,
A,
A,

A,
A,
A,
A12
A14
A16
NC

Ao
1/00
110,
110,

0

Vee
A"
CS,
!WE

A13

A"
A"
Al1

Vss
I/O,
110,
110,
110.
1/07
ICS,
AlO
10E

0
(Top View)

•

HITACHI

246 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - HM628128/HM6281281 Series
Block Diagram

"13~-t-~~=I-1

AI5

"'6

Row
Decoder

Memor, Matrix

512XZ.048

1/00

1/07

C52 ()------I
C510-----I

WE

Timine Pulse Gen.
Read/Write Control

~--1-

____

~

____

~

~ ()---------------~

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005· 1819 • (415) 589·8300 247

HM628128/HM6281281 Series - - - - - - - - - - - - - - - - - - - - - - - - • ORDERING INFORMATION
Part No.
HM628128P-7
HM628128P-8
HM628128P-1O
HM628128P-12
HM628128LP-7
HM628l28LP-8
HM628128LP-IO
HM628128LP-12
HM628128FP-7
HM628128FP-8
HM628128FP-lO
HM628128FP-12
HM628128LFP-7
HM628l28LFP-8
HM628128LFP-IO
HM628128LFP-12

Access
70ns
85ns
lOOns
120ns
70ns
85ns
lOOns
120ns
70ns
85ns
lOOns
l20ns
70ns
85ns
lOOns
120ns

Package

600 mil
32 pin
Plastic
DIP

Access
70ns
85ns
lOOns
l20ns

HM628128LFP-7SL
HM628128LFP-8SL
HM628128LFP-IOSL
HM628128LFP-12SL

70ns
85ns
lOOns
120ns

Package
600 mil
32 pin
Plastic
DIP
(DP-32)

(DP-32)

525 mil
32 pin
Plastic
SOP

525 mil
32 pin
Plastic
SOP
(FP-32D)

(FP-32D)
• INDUSTRIAL TEMPERATURE SERIES

• TSOP SERIES
Type No.

Part No.
HM628128LP-7SL
HM628128LP-8SL
HM628128LP-IOSL
HM628128LP-12SL

Access Time

HM628128T-7
HM628128T -8
HM628128T-10
HM628128T -12

70 os
85 os
100 ns
120 os

HM628128LT-7
HM628128LT-8
HM628128LT-10
HM628128LT-12

70 os
85 os
100 ns
120 os

HM628128LT-7L
HM628128LT-8L
HM628128LT-IOL
HM628128LT -12L

70 os
85 os
100 os
120 os

HM628128R-7
HM628128R-8
HM628128R-1O
HM628128R-12

70 os
85 os
100 ns
120 os

H?-..f62812SLR 7
HM628128LR-8
HM628128LR-1O
HM628128LR-12

70 uS
85 ns
100 ns
120 os

HM628128LR-7L
HM628128LR-8L
HM628128LR-IOL
HM628128LR-12L

70 os
85 ns
100 os
120 os

Package

Type No.

8mmx20mm
32-PiD TSOP
(Nonnal Type)
(TFP-32DA)

Access Time

HM628128PI-8
HM628128PI-1O
HM628128PI-12

85 os
100 os
120 os

HM628128LPI-8
HM628128LPI-10
HM628128LPI-12

85 os
100 os
120 os

HM628128FPI-8
HM628128FPI-1O
HM628128FPI-12

85 ns
100 os
120 os

HM628128LFPI-8
HM628128LFPI-IO
HM628128LFPI-12

85 ns
100 os
120 os

Package
6OO-mil
32-PiD
Plastic DIP
(DP-32)

525-mil
32-PiD
Plastic SOP
(FP-32)

8mmx20mm
32-Pin TSOP
(Reverse
Type)
(TFP-32DAR)

Function Table
WE

x
x

CSt
H

CS2

DE
x
X

H
H

L

Output disable
Read
Write

H
H

x
L
L

L

L

H

H

L

L

H

L

Note:

Mode

x
L

H

Not selected

Vcc Current
ISB, IsOI
Iso, IsOI
Icc
Icc
Icc
Icc

DoutPin
High-Z
High-Z
High-Z
Dout
Din
Din

Ref. Cycle

Read cycle
Write cycle (1)
Write cycle (2)

x: H orL

•

HITACHI

248 Hitachi America, ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - HM628128/HM6281281 Series
Absolute Maximum Ratings
Symbol

Value

Voltage on any pin relative to Vss

VT

-0.5*! to +7.0

V

Power dissipation

PT

1.0

W

Topr

Oto +70

°C
°C

Storage temperature

Topr
T stg

-40 to +85
-55 to + 125

°C

Storage temperature under bias (HM628128 Series)

Tbias

-10 to +85

°C

Tbias

-40 to +85

°C

Item

Operating temperature (HM628128 Series)
Operating temperature (HM6281281 Series)

Storage temperature under bias (HM628128I Series)
Note:

Unit

*1. -3.0 V for pulse half-width S 30 ns

Recommended DC Operating Conditions
(Ta=O to +70°C, for HM628128 Series, Ta=-40° to +85°C for HM6281281 Series)
Parameter

Symbol
Vee
Vss
VIH

Supply voltage
Input high (logic 1) voltage
Input low (logic 0) voltage
Note:

Min
4.5
0
2.2
-0.3'1

VD..

Typ
5.0
0

Max
5.5
0
6.0
0.8

Unit

Note

V
V
V
V

*1. -3.0 V for pulse half-width S 30 os

DC Characteristics (Ta=O to +70°C, for HM628128 Series, Ta=-4O° to +85°C for HM6281281 Series,
Vee=5 V :t: 10%, Vss=OV)
Parameter
Input leakage current

Symbol Min.

Typ.*!

Test Conditions

-

-

Max.
2

Unit

Ilul

p.A

Output leakage current

IILOI

-

-

2

p.A

Operating power supply
current: DC

Ice

-

15

35
(45)

rnA

ICC!

-

45

70
(80)

rnA

lee2

-

15

Vin=Vss to Vee
CS1 =VIH or CS2=VIL,
OE=VIH or WE=VIL,
VIIO=VSS to Vee
CS1=VIL, CS2=VIH,
others=VIHIVIL
1110=0 rnA (HM6281281 Series)
Min. cycle, duty = 100%, CS1 =VIL, CS2=VIH,
others = VIHIVIL
1110=0 rnA (HM6281281 Series)
Cycle time = 1p'S,
duty = 100%,1110=0 rnA
CS1 sO.2V, CS20!! Vee -0.2V
VIHO!! Vee-0.2V, VILsO.2V
(HM6281281 Series)

ISB

-

1

3

rnA

CSI =VIH, CS2=VIH or CS2=VIL

-

0.02
2*2
2*3

2
100*2
50*3

rnA

VinO!! OV
CS10!! Vee -0.2V, CS20!! Vee -0.2V or
OVs CS2s 0.2 V

Operating Power supply
current

Standby Vee current: DC
Standby Vee
current (1): DC

ISB!

-

30
(40)

rnA

p.A

Output low voltage
0.4
0
101.=2.1 rnA
Output high voltage
V
IoR= -l.OrnA
VDH 2.4
Note: 1. TYpical values are at Vee=5.0V, Th= +25°C and specified loading.
2. This characteristics is guaranteed only for L-version.
3. This characteristics is guaranteed only for SL-version.

VoL

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 249

HM628128/HM6281281 Series - - - - - - - - - - - - - - - - - - - - - - - -

capacitance ( Ta =25°C, f =1.0 MHz )
Symbol
Cin
ClIO

Item
Input'capacitance
Input/output capacitance
Note:

Typ

Min

Max
8
10

Unit
pF
pF

Test Conditions
Yin =0 V
Vvo=OV

This parameter is sampled and not JOO% tested.

AC Characteristics (Ta=O to +70·C, for HM628128 Series, 'Th=-40to +85·C for HM628128I Series,
VCC=5 V :I:: 10%, unless otherwise noted)
Test Conditions
• Input pulse levels: 0.8 V to 2.4 V for HM628128 Series
0.5 Vto 2.5 V for HM6281281 Series
• Input rise and fall times: 5 ns

• Input and output timing reference levels: 1.5V
• Output load: 1 TIL Gate and CL (100pF)
(Including scope & jig)

Read Cycle
Item
Read cycle time
Address access time
Chip selection (CS1)
to output valid
Chip selection (CS2)
to output valid
Output enable (DE)
to output valid
Chip selection (CS 1)
to output in low-Z
Chip selection (CS2)
to output in low-Z
Output enable (OE)
to output in low-Z
Chip deselection (CS 1)
to output in high-Z
Chip deselection (CS2)
to output in high-Z
Output disable (OE)
to output in high-Z
Output hold from
address change

HM628l28I-8 HM628l28I-10 HM628128I-12
HM628128-8 HM628128-10 HM628128-12
Min Max
Min Max
Min Max
120
85
100
85
100
120
85
100
120

tCOI

HM628128-7
Min Max
70
70
70

!CO2

70

85

100

120

ns

toE

35

45

50

60

ns

Symbol
IRe

tAA

Unit

Note

ns
ns
ns

ILZI

10

10

10

10

ns

"'1. "'2,

1LZ2

10

10

10

10

ns

"'I, "'2,

to1.Z

5

5

5

5

ns

"'I, ·2.

blZl

0

25

0

30

0

35

0

45

ns

"1. "2,

blZ2

0

25

0

30

0

35

0

45

ns

"I, "2.

toHZ

0

25

0

30

0

35

0

45

ns

·1, ·2,

toil

10

10

10

10

ns

• HITACHI
250 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - HM628128/HM6281281 Series

Read Cycle Timing
t.e
Address

teol
CS2

to.
tOLl

Dout

NOles:

*\. 1HZ and 10HZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced

to output
voltage levels.
*2. At any given temperature and voltage condition, tllZ max is less than tLZ min both for a given device and from device to device.
*3. WE is high for read cycle.

Write Cycle

Parameter

Symbol

Write cycle time
Chip selection to
end of write
Address setup time
Address valid to
end of write
Write pulse width
Write recovery time

twc
tew

Write to output
inhigh-Z
Data to wri te time
overlap
Write hold from
write time
Output active from
end of write

HM628128I-8
HM628128-8
Min Max
85
75

HM628128-7
Min Max
70
60

HM628128I-IO
HM628128-10
Min Max
100
80

HM628128I-12
HM628128-12
Min Max
120
85

Unit

Note

ns
ns

0
60

0
75

0
80

0
85

ns
ns

55
5 (10)
10 (15)
0
30

60

twllZ

50
5
10
0

5 (10)
10 (15)
0
35

70
10 (15)
15 (15)
40
0

ns
ns
*12
ns *11 *12
ns
*10

tow

30

35

40

45

ns

IDH

0

0

0

0

ns

tow

5

5

5

5

ns

lAS

tAw

twp
twR

25

•

*10

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 251

HM828128/HM8281281 Series - - - - - - - - - - - - - - - - - -_ _ _ __

Wrne TImIng Waveform (1)

«m Clock)

CS2

Dout
Din

• HITACHI
252 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - HM628128/HM6281281 Series

Write TIming Wavefonn (2) (OE Low Fix)
t.e
Address

...,r

----:.)

---./
t cw • 2

\
CS2

.

'\ '\ .'\'\'\'\

'// / / / /

'LL / / / / / /
~
t ••

I

t

~'\'\

t AS ·)

..

~ ~'\'\'\'\'\'\
.,
to.

tWHZ
~::)

J

J

'I

d

Din

NOles:

to.

..L

Dout

I

t ••

tOH

J .,

.,

..---.. I~

JI~-

.,

'v'\J'.,.

'VY

01. A write occurs during the overlap of a low CS I, a high CS2 and a low wll". A write begins at the latest transition among CS I
loing low, CS2 going high and WE going low. A write ends at the earliest transition among CSI going high, CS2 going low
and WE going high. twp is measured from the beginning of write to the end of wrile.
*2. leW is measured from the laler of CSl going low or CS2 going high to the end of write.
°3, lAS is measured from the address valid to the beginning of write.
°4. tWR is measured from the earliest of CSI or WE going high or CS2 going low to the end of write cycle.
*5. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not
be applied.
°6.
°7.
oS.
°9.

IT CSI goes low simultaneously with WE going low or afler WE going low, the outputs remain in high impedance stale.
Dout is the same phase of the latest written data in this write cycle.
Dout is the read data of next address.
ITCSI is low and CS2 is high during this period, I/O pins are in the output state. Therefore, the input signals of the opposile
phase to the outputs must not be applied to them.
°10. This parameter is sampled and not 100% lested.
°11. This value is measured from CS2 going low to the end of write cycle.
*12. Parenthesis denote specification for HM6281281 Series only.

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 253

HM628128/HM6281281 Series - - - - - - - - - - - - - - - - - - - - - - - -

Low

Vee Data Retention Characteristics (Ta=O to

+70°C) for HM628128 Series,

Ta=-40 to +85°C for HM6281281 Series.

(This characteristics is guaranteed only for L & SL version.)
Parameter
Vee for data
retention

Data retention
current

Symbol

VDR

Min.

Typ.

-

2.0

Max.

V

CS1 2: Vee -0.2 V,
CS2 2: Vee -0.2 V
or 0 V s CS2 s 0.2 V
Yin 2: OV

15*14

p.A

Vee=3.0V, Yin 2: OV
CS1 2: Vee -0.2 V,
CS2 2: Vee -0.2 Vor
OV s CS2 s 2.0V

50*\3

IeeDR

Test Conditions*2

Unit

Chip deselect to
data retention time

teDR

0

-

-

ns

Operation recovery
time

tR

5*15

-

-

ms

See Retention
Waveform

Low Vee Data Retention Timing Waveform (1) (CST Controlled)

_~:::::=:1---Data Retention MOde---~=t=.~+-

____

~ -=Vcc-O.2V

" -----------------------------

•

HITACHI

254 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - HM628128/HM6281281 Series

Low Vee Data Retention Timing Waveform (2) (CS2 Controlled)

Vee

Data Retention Mode

4.5V

CS2

O.4V
OV

Note: 13.

*1: for L-version and 20 uA max. at Ta=O to 4Qoe
*2: for SL-version and 3uA max. at 111=0 to 40°C.
14. eS2 controls address buffer, WE buffer, eSl buffer and OE buffer and Din buffer. If eS2 controls data
retention mode, Yin levels (address, WE, OE, eSl, 110) can be in the high impedance state. IfeSI controls
data retention mode, eS2 must be eS2 2: Vee -0.2V or OV :s eS2 :s O.2V. The other input levels (address,
WE OE, 110) can be in the high impedance state.
15. Vee rise time must be more than 50ms when Vee rise time is less than 50ms, tR must be 50ms or more.

_HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589·8300 255

HM66204 Series - - - - - - - - - 131072-word x a-bit High Density CMOS Static RAM Module
The HM66204 module was designed for pinout and signal compatibility with the HM628128 128K
x 8 Monolithic Device.
This device is now obsolete and no longer in manufacture.
New designs should be based on the HM628128 Monolithic Device.

_HITACHI
256 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM624256A Series--------~-preliminary
262,144-Word x 4-Bit High Speed CMOS Static RAM
• DESCRIPTION
The Hitachi HM624256A is a high speed 1 M
Static RAM organized as 256-kword x 4-bit. It realizes high speed access time (20/25/35 ns) and low
power consumption, employing CMOS process
technology and high speed circuit designing technology. It is most advantageous for the field where
high speed and high density memory is required,
such as the cache memory for main frame or 32-bit
MPU.
The HM624256A, packaged in a 400 mil plastiC
SOJ is available for high density mounting .

(DP-28C)

• FEATURES
• Single 5V supply and high density 28-pin package
(DIP and SOJ)
• High speed
Access time: 20/25/35 ns (maximum)
• Low power dissipation
Active mode 350 mW (typical)
Standby mode 100 IlW (typical)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle time
• Directly TTL compatible
All inputs and outputs

(CP-28D)

• PIN ARRANGEMENT (DIP and SOJ)

• ORDERING INFORMATION
Type No.

Access Time

HM624256AP-20
HM624256AP-25
HM624256AP-35
HM624256ALP-20
HM624256ALP-25
HM624256ALP-35
HM624256A1P-20
HM624256A1P-25
HM624256A1P-35
HM624256AUP-20
HM624256AUP-25
HM624256AUP-35

20 ns
25 ns
35 ns
20 ns
25 ns
35 ns
20ns
25 ns
35 ns
20 ns
25 ns
35 ns

Package
400-mil
28-Pin
Plastic DIP
(DP-28C)

AO

Vcc
A17
A16
A15
A14
A13
A12

A1
A2
A3
A4
A5
A6
A7
As
Ag

A11

A10
CS
OE

Vss

'-L...!.:!.._ _ _--""--'~

NC
1/01
1/02
1/03
1/04
WE

(Top View)

400-mil
28-Pin
PlasticSOl
(CP-28D)

• PIN DESCRIPTION
Pin Name

Function

Ao-Al7

Address

1/00-1/04

Input/Output

CS

Chip Select

OE

Output Enable

WE

Write Enable

Vee

Power Supply

VSS

Ground

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 257

HM624256ASeries - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM

Ao
A1

o----L~:::::I

A2 o----fh:::::l

A3

, , - - Vcc

Row

~ o----fh:::::l Decoder

As
As

o----fh:::::l
o----fh:::::l
A7 o----fh:::::l

As

Memory Matrix
512 X 2048

,,--vss

O----+~:::::I

1/01

Column 1/0

1/02
1/03
1/04

CS 0------,-<1,

WE o---~~~r--------------------------------~
OE 0-------1

.HITACHI
258 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

---------------------------------------------------------HM624256ASeries
• FUNCTION TABLE
CS
H

OE
X

WE
X

Mode
Not Selected

VCC Current

I/O Pin
High-Z

Ref. Cycle

ISB,ISBI

L

L

H

Read

ICC

Dout

Read Cycle (1-3)

L

H

L

Write

ICC

Din

Write Cycle (I)

L

L

L

Write

ICC

Din

Write Cycle (2)

-

Note: X: H or L

• ABSOLUTE MAXIMUM RATINGS
Parameter

Symbol

Voltage on any pin relative to VSS

Vin

Value
-0.5*1 to +7.0

Unit
V

i'T

1.0

W

Topr

o to +70

Storage Temperature Range

Tstg

-55 to +125

°C
DC

Storage Temperature Range Under Bias

Tbias

-10 to +85

°C

Power Dissipation
Operating Temperature Range

Note: I. Vin min = -2.0 V for pulse width" 10 ns .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 259

HM624256ASeries - - - - - - - - - - - - - - - - - - - - - - - - - - • RECOMMENDED DC OPERATION CONDITIONS (Ta =0 to +70°C)
Parameter

Symbol

Min.
4.5

Vee

Supply Voltage

VSS

0

Input High (Logic I) Voltage

VIH

2.2

Input Low (Logic 0) Voltage

VIL

-0.5'1

Typ

Max.

5.0

5.5

Unit
V

0

V

0

-

6.0

V

0.8

V

Note: I. VIL min = -2.0 V for pulse width ~ 10 ns .

• DC CHARACTERISTICS (Ta= Oto +70°C, Vee = 5V± 10%, Vss =OV)
HM624256A-20
Parameter

HM624256A-25!35

Symbol
Min.

Typ'l

Max.

-

2.0

Output Leakage Current

IILOI

-

-

2.0

-

ICC

-

-

150

-

Output Low Voltage
Output High Voltage

ISB

-

ISBI*2
ISBI' 3

-

VOL
VOH

-

-

2.4

0.02

-

-

~A

Vee = Max
Vin = Vss to Vee

-

2.0

J,tA

CS =VIH
VI/O = VSS to Vee

-

120

rnA

CS = VIL, 11/0 = 0 rnA,
Min Cycle

-

-

Standby Power Supply
Current (1)

2.0

Max

I lui

Standby Power
Supply Current

Test Conditions

Typ'l

Input Leakage Current

Operating Power
Supply Current

Unit

Min

60

-

-

40

rnA

CS = VII-!, Min Cycle

2.0
100

-

0.2

rnA

CS ~ Vee -O.2V, OV ~ Vin
~ 0.2V or Vin ~ Vee -O.2V

0.4

-

-

2.0
100
0.4

V

IOL=8mA

-

2.4

-

-

V

IOH =-4 rnA

~A

Notes: I. Typical limits are at Vee = 5.0V, Ta = +25°C and specified loading.
2. P and JP version.
3. LP and UP version.

•

HITACHI

260 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

----------------------------HM624256ASeries
• CAPACITANCE (Ta = 25°C, f= I MHz.)
Parameter

Symbol

Input Capacitance

Min

Cin

Input/Output Capacitance

CI/O
Note: I. This parameter is sampled and not 100% tested .

Max

Unit

-

5

pF

Test Conditions
Vin=OV

-

10

pF

Vl/O=OV

• AC CHARACTERISTICS (Ta = 0 to +70°C, VCC = 5V ± 10%, unless otherwise noted.)
Test Conditions
•
•
•
•
•

Input pulse levels: OV to 3.0V
Input rise and fall times: 4 ns
Input timing reference levels: 1.5V
Output timing reference levels: 1.5V
Output load: See figures
+5V

+5V

4800

4800

Dout o--~---1

2550

Dout o--~---1

30pF·

2550

Output Load (A)
"Including scope & jig.

5pF·

Output Load (8)
(for tCHZ, tClZ, tWHZ & tow)

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 261

HM624256A Series

.READCVCLE
Parameter

Symbol

Read Cycle Time
tRC
Address Access Time
tAA
Chip Select Access Time
tACS
Chip Selection to Output in Low-Z
tCLZ"l
Output Enable to Output Valid
toE
Output Enable to Output in Low-Z
tOLZ'l
Chip Deselection to Output in High-Z
tcHZ'l
toHZ*j
Chip Disable to Output in High-Z
Output Hold from Adc\!,!:ss !=hange
toH
Chip Deselection to Power Up Time
tpu
Chip Deselection to Power DOwn Time
tPD

HM624256A-20
Min
Max
20
20
20
5
-

HM624256A-25
Min
25

Max

-

HM624256A-35
Max

-

Min
35

25
25

-

35
35

-

-

5

-

5

-

10

-

12

-

15

0

-

0

-

0

-

0
0

10
10

0

12
10

0
0

10

5

-

0
5

15

0

-

0

-

0

-

-

12

-

15

-

25

5

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

• READ TIMING WAV~FPRM (1) "1. "2
Address

OE

cs
Daut

_HITACHI
262 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300

----------------------------HM624256ASeries

• READ TIMING WAVEFORM (2) *2, *3, "5
tRC

1'~1J

Address

Dout

• READ TIMING WAVEFORM (3) *1, *2, *4, *5

cs
tCHZ

tcu
Data Valid

Dout
Vccsupply··
current

ICC·····~t50~%------------~
ISB

Notes:

1. Transition is measured ±200 mY from steady state voltage with Load (B). This parameter is sampled and not 100% tested.
2.
3.
4.
5.

WE is high for read cycle.
Device is continuously selected, CS = YIL.
•
Address valid prior to or coincident with CS transition low.
OE=YIL.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 263

HM624256A Series

• WRITE CYCLE
Parameter

Symbol

Write Cycle Time
Chip Selection to End of Write

twe

HM624256A-20
Min
20
14

Max

HM624256A-25

-

Min
25
17

16

-

20

-

Address Valid to Eod of Write

lew
tAW

Address Setup Time
Write Pulse Width

tAS
twp

0
14

-

0
17

Write RecoveI)' Time
Output Disable 10 OUtpUI io High-Z*I

tWR

0
0
0

-

0
0

12

-

0
15

0
0

-

0

-

0

Write to Output io High-Z*1

10HZ

tWHZ
tDW

Data to Write Time Overlap
Data Hold from Write Time
Output Active from Eod of Write *1

tDH
tow

10
13

Max

-

10
15

-

HM624256A-35
Min
35
25
30
0
'25
0
0
0
20
0
0

Max

Unit

-

ns

-

ns
ns

-

os

-

os

-

os
os

10
20

-

os
os
os
os

• WRITE TIMING WAVEFORM (1)
twe
Address

tew

'5

tOHZ"4

Dou!

Din

---(-(-((-~®K~-

•

~-:=m

HITACHI

264 Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------------HM624~ASeries

• WRITE TIMING WAVEFORM

(2)*6

Address

tcw

"4

OoUl

tow

tOH"g

Din

Notes:

1.
2.
3.
4.
5.
6.
7.
8.
9.

Transition is measured ±200 mY from high impedance voltage with Load (B). This parameter is sampled and not 100% tested.
A write occurs during the overlap (twp) of a low CS and a low WE.
twR is measured from the earlier of CS or WE going high to the end of write cycle.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, output remain in a high
impedance state.
OE is a continuously low (OE = YILl.
Dou! is the same phase of write data of this write cycle.
Dou! is the read data of next address.
If CS is low during the period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must
not be applied to them.

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 265

HM624256A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• LOW Vee DATA RETENTION CHARACTERISTICS (Ta = 0 to +70 0c)
This characteristic is guaranteed only for L-version.
Parameter

vce for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time

Symbol

Min

VDR

2.0

-

-

2

leeDR

Typ

Max

100*1

teDR

0

-

-

tR

5

-

-

Unit

Test Conditions

V

f.lA
ns
ms

CS ~ VCC --{).2V.
Vin ~ VCC --{).2V or
OV ~ Vin ~ 0.2V

Note: 1. Vee = 3.0V

• LOW Vee DATA RETENTION TIMING WAVEFORM
Data retention mode
Vce
4.5V
2.2V
V DR
CS~Vcc - O.2V

OV

---------------------------------------------

•

HITACHI

266 Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

HM624257 Series
262144·WORD x 4·81T HIGH SPEED CMOS STATIC RAM
The Hitachi HM624257 is a high speed 1M static RAM
organized as 256-kword " 4-bit. It realizes high speed access
time (35/45 ns) and low power consumption, employing the
advanced CMOS process technology and high speed circuit
designing technology. It is most advantageous for the field where
high speed and high density memory is required, such as the
cache memory for main frame or 32-bit MPU.
The HM624257, packaged in a 400-mil plastic SOJ is available
for high density mounting.

• FEATURES
• Single 5 V supply and high density 32-pin package (SOJ)
• High speed: Access time 35/45 ns (max.)
• Low power dissipation
Active mode: 350 mW (typ.)
Standby: 100 p.W (typ.)
• Completely static memory:
No clock or timing strobe required
• Equal access and cycle time

(CP-32D)

• Directly TTL compatible: All Inputs and outputs

• ORDERING INFORMATION
Type No.

Access Time

Package

HM624257JP-35
HM624257JP-45

35 ns
45 ns

HM624257UP-35
HM624257UP-45

35 n.
45 ns

400 mil
32-pin
Plastic SOJ
(CP-32D)

PIN ARRANGEMENT
Top View

• PIN DESCRIPTION
Pin Name
Ao-AI7
11-14
11-04
CS
WE
Vee
Vss

Function

Address
Data Input
Data Output
Chip Select
Write Enable
Power Supply
Ground

NC

Vee

Ao

AI7

AI

AI6

A2

A,S

A3

AI4

A4

AI3

As

AI2

As

All

A7

NC

As

It

As

12

Al0

01

14

02

13

03

~

04

VSS

~

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589-8300 267

HM624257 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - -

•

BLOCK DIAGRAM

AO
Al
A2
A3

A4

~V$S

Memory Arrray

Row

256X 1,024

Decoder
A5
A6
A7
AS

01
Input
Data

Control

04
A9

AlO All AI2 AI3 AI4 AI5 AI6 AI7

cs
WE~~

~~------------------------------------~

•

HITACHI

268 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - HM624257 Series

• ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Voltage on any Pin Relative to VSS

Item

Vin

-0.5'1 to +7.0

V

Power Dissipation

PT

1.0

W

Unit

-Operating Temperature Range

Topr

Oto +70

·C

Storage Temperature Range

Tst8

-55 to + 125

·C

Storage Temperature Range Under Bias

Tbias

-10 to +85

·C

* I. Vln min. = -2.0 V for pulse width :s 10 RS .

NOTE:

• FUNCTION TABLE
CS

WE

Mode

Vee Current

Doul Pin

H

X

Not Selected

Iss, Issl

High-Z

-

L

H

Read

Iec

Read CycleCl )-(2)

L

Write

Icc

Doul
High-Z

L
NOTE:

Ref. Cycle

Write Cycle' I )-(2)

x: HorL

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 269

HM624257 Series - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ __
• RECOMMENDED DC OPERATING CONDITIONS (T. = 0 to +70·C)
Item

Symbol

Min.

Typ.

Max.

Vee

4.5

5.0

5.5

V

Vss

0

0

0

V

Supply Voltage

Unit

Input High (lngic I) Voltage

V IH

2.2

-

6.0

V

Input Low (lngic 0) Voltage

V IL

-0.5*·

-

O.S

V

NOTE:

*'.

VII-min. = -2.0V for pulse widlh :s IOns .

• DC CHARACTERISTICS (T. = 0 to +70·C, Vee = 5 V ± 10%, Vss = 0 V)
Item

Symbol

Min.

Typ.*·

Max.

Unit

Ilul

-

-

2.0

p.A

Input Leakage Current

Test Conditions

Output Leakage Current

-

IILOI

-

10.0

p.A

= max.
= Vss to Vee

Vee

Yin
CS

= VIH
= Vss to Vee

Vila

= 0 mAo

Operating Power Supply Current

Ice

-

70

120

mA

CS = V IL • 1./0
min. cycle

Standby Power Supply Current

ISB

-

30

60

mA

'CS

= VIH • min. cycle

Standby Power Supply Current (I)

ISB•

-

0.02

2.0

mA

CS

i!: Vee-O.2V

Yin

i!: Vee-0.2V

Output Low Voltage

VOL

-

-

0.4

V

10L = SmA

Output High Voltage

VOH

2.4

-

-

V

10H

NOTE:

I. Typical limits are at Vee = 5.0 V. T.

• CAPACITANCE (T.
Item

oV :s Yin :s 0.2 V or

= -4.0mA

= +2S°C and specified loading .

= 2S·C, f = IMHz)
Symbol

Min.

Max.

Unit

Input Capacitance

Cin

-

6

pF

Yin = OV

Output Capacitance

Coo.

-

11

pF

Vou• =OV

NOTE:

Test Conditions

1. This parameter is sampled and nOC 100'1 tested.

•

HITACHI

270 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM624257 Series
• AC CHARACTERISTICS (T.

= 0 to +70°C, Vee = 5 V

± 10%, unless otherwise noted.)

Test Conditions
• Input and output timing reference levels: 1.5 V
• Output load: See Figures

• Input pulse levels: Vss to 3.0 V
• Input rise and fall times: 5 ns

Output Load (8)

Output Load (A)

(for IeHZ' IcLZ' tWHZ & low)

5V

5V

9

~

?

4801l

~ 481X1

Do.!

25~f

Ooul

3OpF'

,., 5pF'

25~ ~

7;r

NOTE:

7;'7'

"'Including scope & jig.

• Read Cycle
Item
Read Cycle Time

Symbol

HM624257-35
Min.

HM624257-45

Max.

Min.

Max.

Unit

tRe

35

-

45

-

ns

35

-

45

ns

tAA

-

Chip Select Access Time

tACS

-

35

-

45

ns

Output Hold From Address Change

tOH

5

5

tLz'1

5

5

-

ns

Chip Selection to Output in Low-Z

-

Chip Deselection to Output in High-Z

tHZ 'I

0

20

0

20

os

-

0

-

ns

-

30

ns

Address Access Time

Chip Selection to Power Up Time

tpu

0

Chip Deselection to Power Down Time

tpo

-

NOTE:

ns

I. Transition is meallured :i:: 200 mV from steady voltage wilh lllad (8).
Thili parameter is sampled and nol 100% tesled.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300 271

HM624257 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - Read Timing Waveform (1) ·1,·2
I"

...

I ••

nata Valid

!lout

Read Timing Waveform (2) ·1, ·3

I.,
I"

!lout

Hilh Impedance

HiP Impedance

I,"

Vee supply

I",

---------------+r----------------------------~
50%

eurrnnt
1••
NOTES:

"I.

WE is high for readcyc1e.

*2. Device is continuously selected, CS = VIL.
*3. Address valid prior to or coincident with

CS transition low.

• Write Cycle
Item

HM624257-35

Symbol

HM624257-45

Unit

Min.

Max.

Min.

Max.

-

ns

ns

twe

35

lew

30

-

45

Chip Selection to End of Write
Address Valid to End of Write

tAW

30

-

40

Address Setup Time

tAS

0

-

0

-

Write Pulse Width

twp

30

35

-

ns

Write Recovery Time

tWR

3

-

3

-

ns

Data Valid to End of Write

tDW

20

-

-

ns

O!!ta Hold Ti!!!e

tUH

3

-

3

-

ns

Write Enabled to Output in High-Z

twz"I

0

15

0

20

ns

Output Active From End of Write

tow" I

5

-

5

-

ns

Write Cycle Time

NOTE:

40

ns

ns

1. Transition is measured *200 mV from steady stale \'oltage with l..ood (8).
This parameter is sampled and not 100% tested.

•

HITACHI

272 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 4 2 5 7 Series
Write Timing Waveform (1) (WE Controlled)

I.,
Address

cs

Oin

Dout

Write Timing Waveform (2) (CS Controlled)
I",

Address

....

,....,

I"

I,.
I ..,.'·

I ••

Data in V,lid

Din

Oou.
NOTES:

*1, A write oc:curs during the overlap of a low CS and a low W!.
*2. IWR is measured from the earlier ofCS or WE going high to the end of write cycle.

*3, Iflhe CS low transition occurs simultaneously with the WE low transitions or after the WE transition. output buffers rell1lin in a hiBh impedance sille.
*4. DOUT is the same phase of write data of Ihis write cycle .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 273

HM624257 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • Low Vee Data Retention Characteristics (T. = 0 to +70°C)
Symbol

Min.

Typ.

Max.

Unit

Vcr; for Data Retention

Item

VDR

2

-

-

V

Data Retention Current

IccoR

-

2

100° 1

,.A

'cDR

0

-

tR

5

-

-

ns

Chip Deselect to Data Retention TIme
Operation Recovery TIme
NOTE:

01.

1at Conditions
CS 1!: Vcr;-0.2V,
Yin 1!: Vcr; - 0.2 V or
oV :S Vin :S 0.2 V

ms

vee • 3.0 v.

Low Vee Data Retention Timing Waveform

v.., _ _ _ _ _ _""\1
4.SV--------

- - - - - - - - - - - - - - ___________

---------

w ____________________________________________ _
cs-----'

_ HITACHI
274 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

HM621100A S e r i e s - - - - - - - - - - I P r e l i m i n a r y
1,048,576-Word x 1-Bit High Speed CMOS Static Ram
• DESCRIPTION
The HM6211 OOA is a high speed 1M Static RAM
organized as 1,048,576-word x 1-bit. It realizes high
speed access time (20/25/35 ns) and low power
consumption, employing CMOS process technology
and high speed circuit designing technology. It is
most advantageous for the field where high speed
and high density memory is required, such as the
cache memory for main frame or 32-bit MPU.
The HM621100A, packaged in a 400 mil plastic
SOJ is available for high density mounting.
• FEATURES
• Single 5V supply and
high density 28-pin package (DIP and SOJ)
• High speed
Access time 20 nS/25 ns/35 ns (maximum)
• Low power dissipation
Active mode 350 mW (typical)
Standby mode 100(lW (typical)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle time
• Directly TTL compatible
All inputs and outputs

(DP-28C)

(CP-28D)

• PIN ARRANGEMENT
HM621100A Series (DIP and SOJ)
Vee
A'9
A'B

A17
A16
A15

A'4

• ORDERING INFORMATION
Type No.
HM621100AP-20
HM621100AP-25
HM621100AP-35
HM621100ALP-20
HM621100ALP-25
HM621100ALP-35
HM621100AJP-20
HM621100AJP-25
HM62l100AlP-35
HM621100AUP-20
HM621100AUP-25
HM621100AUP-35

Access Time
20 ns
25 ns
35 ng
20ns
25 ns
35 ns
20ns
25 ns
35 ns
20 ns
25 ns
35 ns

NC

A'3
A'2

Package

A"

400-mil
28-pin
plastic DIP
(DP-28C)

DOUT

A10

WE

OrN

Vss -,._ _ _ _...J"- CS

(Top View)
400-mil
28-pin
plastic SOl
(CP-28D)

• PIN DESCRIPTION
Pin Name

Function

AO-AJ9

Address

DIN
DOUT

Input
Output

CS

Chip Select

WE

Write Enable

Vee

Power Supply

VSS

Ground

• HITACHI
Hitachi America, ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 275

HM621100ASeries - - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM

---aVec

Ao
A1
A2

---aVss

As

Memory Matrix

Row
Decoder

AI
As
As

256 X 1024

A7

Aa

Din

Column 1/0

Dout

Column Decoder

• FUNCTION TABLE
CS
H
L

WE
X

Mode
Not Selected

VccCurrent

Output Pin

ISB,ISB]

High-Z

H

Read

ICC

L

L

Write

ICC

Dout
High-Z

Ref. Cycle

Read Cycle
Write Cycle

Note: 1. X: H or L

• ABSOLUTE MAXIMUM RATINGS
Parameter

Symbol

Voltage on any pin relative to VSS

Value
...{l.5') to +7.0

Yin

Unit
V

i'T

1.0

W

Topr

o to +70

°C

Storage Temperature Range

Tstg

-55 to +125

°C

Storage Temperature Range Under Bias

Tbias

-IOta +85

°C

Powe:' Dissipation
Operating Temperature Range

Note: I. Yin min

=-2.0 V for pulse width ~ 10 ns.

• RECOMMENDED DC OPERATING CONDITIONS (Ta
Parameter

=0 to +70°C)

Symbol

Min.

Typ

Max.

Unit

VCC

4.5

5.0

5.5

V

VSS

0

0

0

V

Input High (Logic I) Voltage

VIH

-

6.0

V

lriput Low (Logic 0) Voltage

VIL

2.2
...{l.5']

-

0.8

V

Supply Voltage

Note:

I.

VIL mm = -2.0V for pulse Width ~ 10 ns .

•

HITACHI

276 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------------HM621100ASeries
• DC CHARACTERISTICS (Ta = 0 to +70°C, VCC = 5V ± 10%, VSS
HM62 II OOA-20
Parameter

Symbol
Min.

Typl

= OV)

HM621100A-25/35

Max.

Min.

Typ.1

Max.

Unit

Test Conditions

Input Leakage Current

Ilui

-

-

2.0

-

-

2.0

J.lA

Vee = Max., Vin = VSS to Vee

Output Leakage Current

IILOI

-

-

2.0

-

-

2.0

J.lA

CS=VIH
VI/O = VSS to Vce

lee

-

-

150

-

-

120

rnA

CS = VIL, II/O = 0 rnA,
Min. Cycle

Standby Power
Supply Current (l)

ISBI 2
ISBI 3

-

2.0
100

-

-

2.0
100

rnA

-

J.lA

CS = Vee -O.2V
OV $ Vin $ O.2V or
Vin;:: Vee -O.2V

Output Low Voltage

VOL

-

-

0.4

-

-

0.4

V

IOL=8mA

Output High Voltage

VOH

2.4

-

-

2.4

-

-

V

10H=-4mA

Operating Power
Supply Current

0.02

0.02

Notes: 1. Typical limits are at Vee = 5.0V, Ta = +25°C and specified loading.
2. P and lP version
3. LP and UP version

• CAPACITANCE (Ta = 25°C, f= I MHz)
Parameter

Symbol

Min

Max

Unit

Input Capacitance

Cin

-

6

pF

Vin =OV

Output Capacitance

Cout

-

IO

pF

Vout=OV

Test Conditions

Note: I. This parameter is sampled and not 100% tested .

• AC CHARACTERISTICS (Ta = 0 to +70°C, VCC = 5V ± 10%, unless otherwise noted.)

Test Conditions
•
•
•
•
•

Input pulse levels:
Input rise and fall times:
Input timing reference levels:
Output timing reference levels:
Output load:

0.6 Vto 2.4 V
4 ns
2.2 V and 0.8 V
2.0 V and 0.8 V
See Figures
+5V

+5V

4800

4800

Dout 0--r------4

2550

Dout 0--._----4

30pF'

2550

5pF'

Output Load (8)
(for tCHZ, tCl2. tWHZ & tow)

Output Load (A)
, Including scope & jig.

_HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 277

HM621100ASeries - - - - - - - - - - - - - - - - - - - - - - - - - - -

• READ CYCLE
Parameter

HM621100A
-20
Min
Max
20
20
20
5
0
10
5
0
12
-

Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Selection to Output in Low-Z
Chip Deselection to Output in High-Z
Output Hold from Address Change
Chip Selection to Powel/Up Time
Chip Deselection to Power Down Time

tRe
tAA
tACS
tLzl
tHZI
tOH
tpu
tPD

-

-

HM621100A
-25
Min
Max
25
25
25
5
0
12
5
0
15
-

-

HM621100A
-35
Min
Max
35
35
35
5
0
15
5
0
25
-

Unit
ns
ns
ns
ns
ns
ns
ns
ns

-

• READ TIMING WAVEFORM (1) 2.3

RC

/,

)(

Address

'\/
..

tM

tOH _

tOH

)kXXX~(

Dout

t

Data Valid

)(

• READ TIMING WAVEFORM (2) 2. 4
tRC

•

..

Dout

tACS

tLl

_I

-I~ ,r-----------------+----~

Hiph Impedence

Data Valid

..

;E---

~ . High Impod~

~:~r:~~PIY . . ···I~~ .... ···· ...... ·~ioo/.-.-----------------------------~
" ""

158

Notes: I. Transition is measured ±200 mY from high impedance voltage with Load (B). This parameter is sampled and not 100% tested.
2. WE is high for read cycle.
3. Device is continuously selected, CS =YIL
4. Address valid prior to or coincident with CS transition low .

•

HITACHI

278 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM621100ASeries

• WRITE CYCLE

Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write

Symbol
twc
tcw
tAW
tAS
twp
tWR
twz l
tDW
tDH
tow I

HM621100A
-20

HM621100A
-25

Min
20
14
16
0
14
0
0
12
0
0

Min
25
17
20
0
17
0
0
15
0
0

Max

-

-

-

12

-

-

Max

-

15

-

-

HM621100A
-35
Min
35
25
30
0
25
0
0
20
0
0

Unit

Max

-

-

-

20

-

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

• WRITE TIMING WAVEFORM (1) (WE Controlled)

Addresses

cs
WE

Din

Dout

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300 279

HM621100A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• WRITE TIMING WAVEFORM (2) (CS Controlled)
twc

X

~

Addresses

tAW
tAS

cs

\

.

t WR *3

.. V

tcw
tWp*2

\\\ \ \\\\'\'\\\

WE

.
~

Din

tow

..

V/ / / / / / / / /

III

tOH

Data In Valid

High Impedence *4

Dout

Notes: I. Transition is measured ±200 mV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested.
2. A write occurs during the overlap'of a low CS and a low WE.
.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in
a high impedance state.
5. Dout is the same phase of write data of this write cycle, if IWR is long enough.

• LOW Vce DATA RETENTION CHARACTERISTICS (Ta =0 to +70°C)
This characteristic is guaranteed only for L-version.
Item

Symbol

Min

Vee for Data Retention

VDR

2.0

Data Retention Current

IeeDR

Chip Deselect to
Data Retention Time
Operation Recovery Time
_.
..
- -Note:
vee = 5.U V.

-

Typ
-

2

teDR

0

tR

5

-

Max
100 1

Unit

Test Condition

V

IJA

-

ns

-

ms

CS <= Vee-O.2V
Yin <= Vee -0.2V or
OV ::; Yin ::; 0.2V

~

• LOW Vee DATA RETENTION TIMING WAVEFORM
Data retention mode

Vee

2.2V
VDR

OV

-------------~~Q~~~---------------------

•

HITACHI

280 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM628512 Series - - - - - - - - - - - P r e l i m i n a r y
524,288-Word x a-Bit High Speed CMOS Static RAM
• DESCRIPTION
The Hitachi HM628512 is a 4M-bit Static RAM
organized 512-kword x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.5 ~m Hi-CMOS process
technology. The device, packaged in a 525-mil SOP
(foot print pitch width) or 600-mil plastic DIP, is available for high density mounting. LP-version is suitable for battery back up system.
• FEATURES
• High speed
Fast Access time 55/70/85/100 ns (max.)
• Low power
Standby: 10 ~W (typ.) (UL-SL version)
Operation: 75 mW/MHz (typ.)
• Single 5V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output: Three state input
• Directly TTL compatible: All inputs and outputs
• Capacility of battery back up operation
(UL-SL version)

4'
(DP-32)

(FP-32D)

• PIN ARRANGEMENT
HM628512 Series

A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AD
1/00
1/01
1/02

• ORDERING INFORMATION
Type No.

Access Time

HM628512P-5
HM628512P-7
HM628512P-8
HM628512P-1O
HM6285I 2LP-5
HM6285I 2LP-7
HM6285I 2LP-8
HM6285l2LP-1O
HM6285l2LP-5SL
HM6285l2LP-7SL
HM6285I 2LP-8SL
HM628512LP-IOSL
HM628512FP-5
HM628512FP-7
HM628512FP-8
HM628512FP-1O
HM6285I 2LFP-5
HM628512LFP-7
HM628512LFP-8
HM628512LFP-1O
HM6285l2LFP-5SL
HM628512LFP-7SL
HM628512LFP-8SL
HM628512LFP-IOSL

55 ns
70ns
85 ns
lOOns
55 ns
70 ns
85 ns
100 ns
55 ns
70 ns
85 ns
lOOns
55 ns
70 ns
85 ns
lOOns
55 ns
70ns
85 ns
100 ns
55 ns
70 ns
85 ns
JOOns

Package

600-mil, 32 pin
Plastic DIP
(DP-32)

VSS

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Vee
A15
A17
WE
A13
A8
A9
A11
OE
AlO

CS

1/07
1/06
1/05

1/04
1/03

(Top View)
525-mil, 32 pin
Plastic SOP
(FP-32D)

• PIN DESCRIPTION
Symbol

Function

Ao-Al8

Address

1/00-1/07

Input/Output

CS

Chip Select

WE

Write Enable

OE

Output Enable

Vee

Power Supply

Vss

Ground

_HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 281

HM~12Series------------------------------------------------------

• BLOCK DIAGRAM
As o-+---c:1;::::;:=1

---aVec

All

---oVss

Ao
A1

Memory Matrix

1,024 x 4,096

A2
A3
A4
Ar
A12
A14

1/00

o--r-+-D.---1H'--'

1/07 a,-+-ii>1-t--i

6E 0 - - - - - - - - '

• FUNCTION TABLE
WE

CS

OE

Mode

VeeCurrem

X

H

X

Not Selected

ISH,ISHI

DoutPin
High-Z

H

L

H

Output Disable

ICC

High-Z

H

L

L

Read

ICC

Dout

Read Cycle

L

L

H

Write

ICC

Din

Write Cycle (I)

L

L

L

Write

ICC

Din

Write Cycle (2)

Ref. Cycle

-

Note: X: H or L

iii ABSOi..UTi: MAXiMUM RATiNGS
Item
Voltage on any Pin Relative to VSS
Power Dissipation

Value
-0.5*1 to +7.0

Symbol
VT

Unit
V

PT

1.0

W

Topr

oto +70

°C

Storage Temperature

Tstg

-55 to +125

°C

Storage Temperature Under Bias

Tbias

-10 to +85

°C

Operating Temperature

Notes I. -3.0V for pulse half-width :5 30 ns

• RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to +70°C)
Item

Symbol

Min

Typ

Max

Unit

Vee
VSS
VIH
VIL

4.5
0
2.2
-0.3*1

5.0
0

5.5
0
6.0
0.8

V
V
V
V

Supply Voltage
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage

-

Note *1. -3.0V for pulse half-width:5 3Ons.

• HITACHI
282 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------------HM6~12Series

• DC CHARACTERISTICS (Ta = 0 to +70°C, VCC = 5V ± 10%, VSS = OV)
Item
Input Leakage Current
Output Leakage Current

Typ*1

Symbol

Test Conditions
VIN = VSS to Vee

-

-

Max
2

Unit

IILl I
I[LOI

CS = VIH, OE = VIH or WE = VIL.
VI/O= VSS to Vee

-

-

2

JlA

-

15

35

rnA

-

55

90

rnA

-

15

30

rnA

-

I

3

rnA

0.02
2*2
2*3

2
100"2
50"3

rnA

Operating Power Supply
Current: DC

CS = VIL. Others = VIHNIL.
[l/o=OmA
---.Min. Cycle, Duty = 100%
CS = VIL. Others = VIHNIL
[l/o=OmA
Cycle Time = I Jls, Duty = 100%
[I/O = 0 rnA, CS::; 0.2V,
VIH ~ Vee -O.2V, VIL::; 0.2V

[ee
[eC!

Operating Power
Supply Current
[ee2
Standby Power Supply
Current: DC

[SB

Standby Power Supply
Current (I): DC

[SBI

Min

CS=VIH
Yin ~ OV, CS
Yin ~ OV, CS
Yin ~ OV, CS

~
~
~

Vee -O.2V
Vee -O.2V
Vee -O.2V

Output Low Voltage

-

-

0.4

Output High Voltage

2.4

-

-

VOL
IOL=2.1 rnA
VOH
10H=-I.OmA
..
Notes: I. TYPIcal values are at Vee = 5.0V, Ta = +25°C and speCIfIed loadmg.
2. This characteristics is guaranteed only for L-version.
3. This characteristics is guaranteed only for L-SL versior.

JlA

JlA
JlA
V
V

• CAPACITANCE (Ta = 25°C, f = 1.0 MHz)*1
Item

Symbol

Typ

Test Conditions

Max

Unit

Input Capacitance

Cio

-

8

pF

VIN=OV

Output Capacitance

CI/O

-

10

pF

VI/O=OV

Note *I. This parameter is sampled and not 100% tested.

• AC CHARACTERISTICS (Ta =0 to +70°C, VCC 5V ± 10%, unless otherwise noted.)

Test Conditions
•
•
•
•

Input pulse levels: 0.8V to 2.4V
Input rise and fall times: 5ns
Input and Output timing reference levels: 1.5V
Output load: 1 TTl gate + CL (100 pF) (including scope and jig)

• READ CYCLE
Item

Symbol

HM628512-5

HM6285 12-7

HM6285 12-8

Min
55

Min
70

Min
85

Max

-

Max

-

Max
-

HM6285 12-1 0
Min
100

Max

Unit

-

ns
ns

-

100
100

-

50

Note

Read Cycle Time

tRe

Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Selection to Output in Low-Z

tAA

-

55

-

70

-

85

-

teo
tOE

-

55
25

-

-

-

70
35

85
45

tLZ

5

-

10

-

10

-

10

-

ns

Output Enable to Output in Low-Z

tOLZ

5

-

5

-

5

-

5

-

ns

1,2,3

Chip Deselection to Output in High-Z

tHZ

0

20

0

25

0

30

0

35

ns

1,2,3

tOHZ
tOH

0
5

20

0
10

25

-

ns
ns

1,2,3

-

0
10

35

-

0
10

30

-

Output Disable to Output in High-Z
Output Hold from Address Change

-

•

-

ns
ns
1,2,3

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 283

HM628512Series - - - - - - - - - - - - - - - - - - - - - - - - - - -

• READ TIMING WAVEFORM*4

Address

..

tAA
teo

CS
tLZ
tOE

...

tOLZ

OE

Dout

Notes:

I. tHZ and tOHZ are defined as the time at which the outputs achieve and open circuit conditions and are not referenced to
output voltage levels.
2. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to
device.
3. This parameter is sampled and not 100% tested.
4. WE is high for read cycle.

•

HITACHI

284 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 8 5 1 2 Series
• WRITE CYCLE
Parameter

Symbol

HM6285 12-5

HM6285 12-7

HM628512-8

Min
70

Min
85

Write Cycle Time

twc
tcw

55

-

60

-

75

-

80

-

ns

Address setup Time

tAS

0

-

a

-

0

-

0

-

ns

Address Valid to End of Write

50

-

60

-

75

-

SO

-

ns

Write Pulse Width

tAW
twp

40

-

50

-

55

-

60

-

ns

Write Recovery Time

tWR

5

-

5

-

5

-

5

-

ns

tWHZ
tDW

0

0

0
35

a

35

ns

30

25
-

30

25

20
-

-

ns

Data Hold from Write Time

tDH

a

-

a

-

Output Active from End of Write

tow

5

-

5

-

Data to Write Time Overlap

Max
-

Max
-

Min
100

Unit

Chip Selection to End of Write

WE to Output in High-Z

Max
-

HM628512- IO

Min
55

Max
-

Note

ns

-

40

a

-

a

-

ns

5

-

5

-

ns

10

10

• WRITE TIMING WAVEFORM (1) (OE Clock)

..

--

Iwc

Address

IWR "4

lAW

OE
ICW"2

..

CS
*6
IAS"3

....

WE

IWp"1

-----

....

ICHZ"5

Dout

Din

d

•

tow
.. .....c:

IOH

~XXXX

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300 285

HM628512 Series

• WRITE TIMING WAVEFORM (2) (OE Low Fixed)

..

twc

Address
ICW· 2

-

ICH

..

....

low

..

·7

·s

Dout

Din

Notes:

----~

IDW

IDH

"->k»>®

I. A write occurs during the overlap (twp) of a low CS and a low WE. A write begins at the later transition of CS going low
or WE low. A write ends at the earlier transition of CS going high or WE going high. twp is measured from the beginning
of write to the end of write.
2. tew is measured from CS going low to the end of write.
3. tAS is measured from CS going low to the end of write.
4. tWR is measured from the earlier of WE or CS going high to the end of write cycle.
5. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be
applied.
6. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output remain in a
high impedance state.
7. Dou! is the same phase of write data of this write cycle.
8. Dout is the read data of next address.
9. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of opposite phase to the outputs
must not be applied to them.
10. This parameter is sampled and not 100% tested .

•

HITACHI

286 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------------HM628512 Series
• LOW Vee DATA RETENTION CHARACTERISTICS (Ta =0 to +70°C,)
This characteristics is guaranteed only for L/L-SL version
Item
Vee for Data Retention
Data Retention Current
Chip Select to Data Retention Time

Symbol

Min

VDR
IeeDR

2

Max

-

_.

I

-

I

0
5

teDR
tR

Operation Recovery Time

Typ

-

50*'
15*2

-

-

Unit

Test Condition

V

CS;;' Vee -O.2V, Vin;;' OV

I!A

Vee = 3.0V, Vin;;' OV
CS ;;, Vee -O.2V

I!A
ns
ms

See Retention Waveform

• LOW Vee DATA RETENTION TIMING WAVEFORM (CS Controlled)
tCDR

Data retention mode

Vee

4.5V
2.2V

VOR
CS
OV
Notes:

CS~Vee

I.
2.
3.

- O.2V

For L-version and 20 i-lA max. at T a = 0 to 40°C.
For SL-version and 3 I!A max. at Ta = 0 to 40°C.
CS controls address buffer, WE buffer, DE buffer, and Din buffer. In data retention mode, Yin levels (address, WE, DE,
I/O) can be in the high impedance state .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300 287

HM66205 Series
524,288·Word x 8·Blt High Density CMOS Static RAM Module
• PIN ARRANGEMENT

Description
The HM66205 is a high density 4M·bit static RAM module
consisting of 4 pieces HM628128LTS products (TSOP type 1M
static RAM) and a HD74ACT138FP equivalent product (SOP
type CMOS decoder logic).
An outline of the HM66205 is the standard 600 mil width 32
pin dual·inline package. Its pin arrangement is completely
compatible with the forthcoming 4M·bit monolithic static RAM.
The HM66205 offers the features of low power and high
speed by using high speed CMOS devices. And, the HM66205
makes high density mounting possible with no surface mount
technology.
These features make the HM66205 ideally suited for high
denSity, compact memory system.

Features
• High density 32 pin DIP
Mounting 4 pes. of 1M static RAM (TSOP;
HM628128LTS) and CMOS decoder logic (SOP;
HD74ACT138FP equivalent).
• Pin compatible with 4M monolithic static RAM
• High speed
Fast access time 85/1oo/12Ons (max!mum).
• Equal access and cycle time
• Completely static RAM
No clock or timing strobe required
• Low Power standby and low power operation
Standby: ..........................40 I'W (typical)
Operation: ........................80 mW (typical)
• Common data input and output, three state outputs
• Capable of battery backup operation
• Directly TTL compatible: All inputs and outputs

vcc

Ala
Ale
AI4
AI2
A7

AI5
AI7
~

AI3

As
As
A4
Aa

As
As
An
(5E

A2

AIO
i5§

AI
Ao
1101
1102

IIOs
1107

IIOe

IIOa

1105
1104

Vss
(TopViewj

• PIN DESCRIPTION
Pin Name
Ao-AII

Function
Address

1101-1/01

Inpul/OutpUl.

CS

ChipSelec1

WE

Write Enable

OE

Outpul Enable

Vee

Power Supply

Vss

Ground

• TYPE OF PRODUCTS
Part No.

HM662OSL-85
HM66205L-10
HM66205L·12

Access

Package

85 os
lOOns
120ns

600-mil
Module DIP

The 66205 module was designed for pinout and signal compatibility with the
forthcoming 512K)( 8 monolithic device •

•

HITACHI

288 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 6 2 0 S Series
• BLOCK DIAGRAM

AO-A16
A17
A18

0
0
0

A1

01
~

,---- A2

04

E1

Os
De

AO

0
.~

Vcc
1/01-1108
WE
OE

0

'6 T1

O:l

E2

07

E3

De

@\1cc

I
1

·2 Decoder

i5
>0
~

t- AO-A16

-

Cs1

-

-

t - AO-A16

.....

CS2
1/01-8

'1
RAM

WE

No.1

OE
AO-A16

Cs1
CS2
110 1-8
WE

DE

@ Vss

-

1/01-8
WE

......

OE
'--

.. _--·1
RAM
No.3
•••••• 1

CS1

1 - - CS2

'---

...... :
'1

:

RAM :

~.~'.~

:

AO-A16
CS1
CS2
VO 1-8
WE

DE

:··i· ....:
!RAM!
: No.4:

.........

'1. RAM No.1-No.4: HM628128 LTS
'2. CMOS Decoder: HD74ACT138FP

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 289

HM66205 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • MODE SELECTION

cs

WE

OE

I/O

Current

Not Selecled (Power Down)

H

X

X

High-Z

ISB.ls81

Read

L

H

L

0 ....

Icc

Read Cycle(lH3)

L

L

H

Din

Icc

Write Cyclell)

L

L

L

Din

Icc

Write Cycle(2)

Mode

Write
NOTE:

Note

X a Don', care (H or L).

• ABSOLUTE MAXIMUM RATINGS
Symbol

Rating

Vol. on Any Pin Relative to Vss

VT

-0.5 to +7.0

V

Power Dissipation

PT

1.0

W

'c
'c
'c

Item

Operating Thmperature Range

Topr

0-+70

Storage Thmperature Range

T",

-55 to +125

Storage Thmperature Range Under Bias

Tbia•

-10 - +8S

Unit

• ELECTRICAL CHARACTERISTICS
• Recommended DC Ope18tlng Conditions (TA = 0 to + 70'C)
Parameter

Symbol

Min.

Typ.

Max.

Vee

4.S

S.O

S.S

V

Vss

0

0

0

V

V/H

2.2

V

-0.5

-

6.0

VIL

0.8

V

Supply Voltage
Input Voltage

• DC CHARACTERISTICS (Vee = 5V

=10%. V

55

i

Unit

= OV. TA = 0 to +70°C)

Symbol

Min.

Typ.'1

Max.

Unit

Input Leakage Current

IILII

-

-

2

p.A

Output Leakage Current

IILOI

-

-

2

p.A

Operating Power Supply Current: DC

Icc

-

19

46

mA

CS = VIL. Others VIH/VIL• 11/0

Parameter

Test Conditions
Vin = Vss - Vee
"'('1

'--", -

.,

_~.,

VIH. vc -- VIH ur

...........

"Co ==

YIL.

VI/O = Vss - Vee

=0 mA

Average Operating Power
Supply Current (I)

Icel

-

48

89

mA

Min. Cycle. Duty = 100'.'
CS = VIL.IIIO = 0 mAo Other V/HNtL

Average Operating Power
Supply Current(2)

1cC2

-

16

36

mA

Cycle TIme = Ips. Duty = 100'.'.
11/0 = 0 mAo CS :5 0.2V.
V/H = Vee - 0.2V. VIL :5 0.2V

Standby Power Supply Current: DC

ISB

-

4

12

mA

CS = VIH

8

400

p.A

Vin

-

0.4

V

-

V

IoL = 2,\ mA
loa = -1.0mA

Standby Power Supply Current(!)

ISBI

-

Output Low Voltage

VOL

-

Output High Voltage

VOH

2.4

NOTE:

-

l!:

OV. CS = Vee - 0.2

I. Typical wi.... 0 . . .' Vee = S.OV. TA = +2s'e and specified loading.

•

HITACHI

290 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM66205 Series
• CAPACITANCE (TA = 25·C, f = IMHz)
Parameter

Symbol

Typ.

Max.

Unit

Test Conditions

Notes

Cinl

45

pF

Yin = OV

Ao-AI6' WE, OE

45

pF

Yin = OV

A17-A 18, CS

50

pF

Vila =OV

1I01-1I0s

Input Capacitance (2)

CinZ

-

Input/Output Capacitance

CliO

-

Input Capacitance(1)

NOTE:

This parameter is sampled and ROC tool. tesled .

• AC CHARACTERISTICS (TA = 0 to +70·C, Vee = 5V

:I:

10%, unless otherwise noted)

AC Test Conditions
Input pulse levels:
Input rise and faU times:
Input alld output timing reference level:
Output load:

0.8V to 2.4V
5 ns
1.5V
I TTL gate and CL - 100 pF (including scope and jig)

• Read Cycle
Parameter

Symbol

HM66205L-85
Min.

HM66205L-IO

Max.

Min.

85

85

HM66205L-12
Max.

Unit

Max.

Min.

100

-

120

-

ns

-

100

-

120

ns

85

-

100

-

120

ns

50

ns

Read Cycle Time

tRC

Address Access Time

tAA

Chip Select Access Time

tACS

-

Output Enable to Output Valid

toE

-

35

-

45

-

Chip Selection to Output in Low-Z

leu

10

-

10

-

ns

toLZ

5

-

5

-

10

Output Enable to Output in Low-Z

5

-

ns

Chip Deselection to Output in High-Z

leHZ

0

25

0

30

0

35

ns

Output Disable to Output in High-Z

toHz

0

20

0

30

0

35

ns

toH

10

-

10

-

10

-

ns

Output Hold From Address Change

• Read Cycle Timing (1) '1
1~"f-________t2.R",--C _ _ _ _ _ _

Address

OE

cs
Dout

•

HITACHI

Hitachi America,ltd .• Hitachi PIa2a· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 291

HM66205 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Read Cycle Timing (2) '1, 'Z, '4
tRC

~

1 .lxxx1

Address

tOH

Dout

X

Valid

• Read Cycle Timing (3) '1, '3, '4

cs

Valid

Dout

NOTES:

I.



WE is high for read 4:ycle.

2. Device is continuously selected.

cs == VIL.

Not Valid

3. Address shoold be valid prior to or coincident with CS transition Jow.
4.

Oil =

V,L.

• Write Cycle
Parameter

Symbol

HM66205L-85

HM66205L-10

HM66205L-12

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

twe

85

-

100

-

120

-

Chip Selection to End of Write

lew

75

-

90

-

100

-

Address Setup Time

tAS

0

-

!)

0

-

...

ns
ns

Address Valid to End of Write

tAw

75

-

90

-

100

-

ns

Write Pulse Width

twp

65

75

-

85

tWR

5

5

-

Hl

-

ns

Write Recovery

-

Write to Output in High-Z

tWHZ

0

30

0

35

0

40

ns

Data to Write Time Overlap

tDw

35

-

40

-

45

ns

Data Hold From Write Time

tDH

0

-

0

0

Output Active From End of Write

low

5

-

5

-

-

5

-

ns

_HITACHI
292 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

ns

ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 6 2 0 5 Series
• Write Cycle Timing (1) (OE Clock)

twe
Address

OE

tew·2

CS

WE

.
Dout

_______________________
Din

~--to-w--~-'-~v-a-lid--t-oH------*~X~X~

• Write Cycle Timing (2) ·5 (OE Low Fixed)

Address

tew· 2

CS
_---------'tA"'w"::--------i
WE

Dout

tow
Din
NOTES:

~

tOH

Valid
__________

I, A write occurs durinB the overlap (twp of a low CS and low WE.
2, IWR is measured from the earlier of CS or WE going high to the end of write cycle.

~~J



Not Valid

3. During this period. 110 pins are in the output state. The input signals our of phase must not be applied.

4. If the

cs low transition occurs simultaneously with the WE low transition or after the WE low transition. output remain in a high impedance stale.

5.

OE is continuously low. {OE" =

6.

DOIII

Vlt).

should be held in the phase of the written data during this write cycle.

7. DOUI is the read data of next address.
8. IfCs is low durinl this period. 1/0 pins are in the output state. The input signals which are opposite 10 the output level should not be applied to 1/0 pins.

_HITACHI
Hitachi America, ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 293

HM66205 Series - - - - - -

• Low Vee Date Retention Characterlatlc8 (TA = 0 to +70°C)
Parameter
Vcc

for Data Retention

Data Retention Current
Chip Deselect 10 Data Retention Time
Operation Recovery Time
NOT£:

Symbol

Min.

Typ.

Max.

Unit

VOR

2.0

-

-

V

ICCOR

-

4

200

p.A

IeOR

0

-

IR

IRC

-

-

ns
ns

'lest Conditions

CS 2: V1N, A17-A18 2: V 1N
CS 2: V1N, V 1N = OV
See Retention Waveform

I. IRe - Road Cycle TIme .

• Low Vee Data Retention Waveform
ICOR

CS'iii! Vcc-.2V

OV

---------------------------------------------------------

$

HITACHI

294 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM624100 Series - - - - - - - - - - P r e l i m i n a r y
1,048,576-Word x 4-Bit High Speed CMOS Static Ram
• FEATURES
• High Speed:
Fast access time 25/30/35/45 ns(max.) (P·version)
30/35/45 ns (max.) (LP-version)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle time
• TIL compatible-All inputs and outputs
• Thin plastic package for high density mounting

(CP·32D)
• PIN ARRANGEMENT

HM624100 Series
• ORDERING INFORMATION
Type No.

Access Time

Package

HM624100JP·25
HM624I 00JP·30
HM624100JP-35
HM624100JP-40

25 ns
30ns
35 ns
45 ns

400 mil 32-pin
SOJ

HM624100JLP-30
HM624100JLP-35
HM624 IOOJLP-45

30ns
35ns
45ns

HM624100P-25
HM624100P-30
HM624 IOOP-35
HM624100P-45

25ns
30ns
35ns
45ns

HM624100LP-30
HM624100LP-35
HM624100LP-45

30ns
35ns
45n5

(CP-32D)

32-pin
TSOP (II)

(Top View)
• PIN DESCRIPTION

•

Pin Name

Function

Ao-Al9

Address Input

1/01-1/04

Data Input/Output

CS

Chip Select

WE

Write Enable

OE

Output Enable

Vee

Power Supply

VSS

Ground

NC

No Connection

HITACHI

Hitachi America, ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589·8300 295

HM624100Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM

Aoo---i~=I

At ~-"A---'
~Vcc

A2 o--{&===I

~vss

A3~-"A---I

Memory Matrix

A4 ~-~....,.---.

Row
As ~-"A---I Decoder

1024 x 1024

A6 o--{&===I

A7 o--{&===I

As

CS

O--·C~::::J

o-----,-cr,

WEo--~:::::1l

DE

• FUNCTION TABLE
CS
H

OE

WE
X

Mode
Deselect

Vee Current
ISB,ISBI

I/O Pin
High-Z

Ref. Cycle

X

L

L

H

Read

ICC

Dout

Read Cycle I, 2, 3

L

H

L

Write

ICC

Din

Write Cycle I

L

L

L

Write

ICC

Din

Write Cycle 2

Unit

Note:

-

X: H or L

• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Voltage on any pin relative to VSS

VT

-0.5 1 to +7.0

V

Power Dissipation

PT

1.0

W

Operating Temperature

Topr

oto +70

°C

Storage Temperature

Tstg

-55 to +125

°C

Storage Temperature Under Bias

Tbias

-10 to +85

°C

Note: I. VT min = -2.0 V for pulse width ,;; IOns.

_HITACHI
296 Hitachi America, Ltd . • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 4 1 0 0 Series
• RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to +70°C)
Item

Symbol

Min.

Typ

Vee

4.5

5.0

Supply Voltage

Unit
V

0

V

VSS

0

Input High Voltage

VIH

2.2

-

6.0

V

Input Low Voltage

VIL

-0.5 1

-

0.8

V

Note:

I.

VIL mm = -2.0 V for pulse width

~

0

Max.
5.5

10 ns.

• DC CHARACTERISTICS (Ta =Oto+70°C, VCc=SV± 10%, VSs=OV)
HM624 lOOP
Item

Symbol

Min.

Typ

HM624 lOOLP

Max.

Min.

Typ

Unit

Test Conditions

Max.

Input Leakage Current

I III I

-

-

2.0

-

-

2.0

!LA

Vee = Max., Yin = VSS to Vee

Output Leakage Current

IILOI

-

-

2.0

-

-

2.0

!LA

CS =VIH
Vl/O = VSS to Vee

lee

-

-

150

-

-

140

rnA

CS = VIL, 11/0 = 0 rnA,
Cycle=25 ns. (P), 35 ns. (LP)

ISB

-

-

60

-

-

5

rnA

CS=VIH
eycle=25 ns. (P), 35 ns. (LP)

ISBI

-

-

10

-

-

0.1

rnA

o V ~ Yin ~O.2V or

VOL

-

-

0.4

-

-

0.4

V

IOL=8mA

VOH

2.4

-

-

2.4

-

-

V

IOH=-4mA

Operating Vee
Current

Standby VCC
Current

CS '" Vee -O.2V

Output Low Voltage

Yin '" Vee-O.2V

• CAPACITANCE (Ta = 25°C, f= I MHz)
Item

Symbol

Input Capacitance

Cin

Output Capacitance

ClIO

Min

-

Max

Unit

5

pF

Test Conditions
Vin=OV

10

pF

VI/O=OV

Note: 1. This parameter is sampled and not 100% tested.

• AC CHARACTERISTICS (Ta = 0 to +70°C, VCC = sv ± 10%, unless otherwise noted.)
Test Conditions

•
•
•
•

Input pulse levels: VSS to 3.0 V
Input rise and fall times: 4 ns
Input and Output timing reference levels: 1.5 V
Output load: See Figures

:q
+5V

Dout

2550

:q
+5V

480Q

480Q

Dout

30pF'

2550

5pF'

Output Load (6)
(for tOHZ. tell. tWHZ' tow)

Output Load (A)
* Including scope & jig .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy..• Brisbane, CA 94005-1819 • (415) 589-8300 297

HM624100 Series
• READ CYCLE

Item

Symbol

Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Selection to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Deselection to Output in High-Z
Chip Disable to Output in High-Z
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Deselection to Power Down Time

tRe
tAA
tACS
tCLZ 1
tOE
tOLZ 1
tCHZ)
tOHZ)
tOH
tpu
tPD

HM624 I 00-25
P
Min
25
-

5

-

Max

-

HM624100-30 HM624 100-35 HM624 100-45
P/LP
P/LP
P/L
Min
30

-

Min
35

-

30
30

-

5

-

-

13

-

-

0
0
0
5
0

-

0

-

20

-

30

-

20

25
25
10

-

-

0
0
0
5
0

0
0
0
5
0

-

-

20

10
10
-

-

Max

10
10

5

Max

-

Min
45

-

-

45
45

-

10

-

15
15
15

-

35
35

0
0
0

5

Unit

Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

20

15
15

-

• READ TIMING WAVEFORM (1) 1,2

Address

OE

cs

Dout

• READ TIMING WAVEFORM (2) 2, 3, 5

----,:I

Address

IRC

I

~

*=-

___t_~=tO-------'-H=i-!z-;J. -~~~~~_I.~_-_to-"

Dout
• READ TIMING WAVEFORM (3) 1,2,4,5

cs
Dout
Notes:

___________~::---:---=tA~~·1
~I:-__t_c_~____.~.

L Transition is measured ± 200 mV from steady state voltage with Load (B). This parameter is sampled not 100% tested.
2. WE is high for read cycle.
3. CS is low.
4. Address valid prior to or coincident with CS transition low.
5.0E=VIL.

• HITACHI
298 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM624100 Series
• WRITE CYCLE

Parameter

Symbol

Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Output Disable to Output in High-Z
Write to Output in High-ZI
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write

twe
tew
tAW
tAS
twp
tWR
tOHZ
tWHZ
tDW
tDH
tow

HM624 100-25
P
Min
Max
25
15
15
0
15
0
0
10
10
0
12
0
0
-

HM624100-30 H M624 I00-35 HM624 I00-45
P/L
P!LP
P!LP
Min
Max
Min
Max
Min Max
30
35
45
20
25
35
20
25
35
0
0
0
20
35
25
0
0
0
15
0
10
0
15
0
10
0
15
0
15
0
15
20
30
0
0
0
0
0
0
-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

• WRITE TIMING WAVEFORM (1)

twc
Address

tcw

WE

Dout

tow
Din

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 299

HM624100 Series
• WRITE TIMING WAVEFORM (2) 6

Address
tew

cs

WE
tow

Dout

Din
Notes: 1. Transition is measured ± 200 mY from high impedance voltage with Load (B). This parameter is sampled not 100% tested.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. IWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
5. If CS low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain a high
impedance state.
6. OE is continuously low. (OE = YILl
7. Dout is the same phase of write data of this write cycle.
8. Dout is the read data of next address.
9. If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must
not be applied.

_HITACHI
300 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 4 1 0 0 Series
• LOW Vee DATA RETENTION CHARACTERISTICS (Ta = 0 to +70°C)
This characteristic is guaranteed only for L-version.
Item
Vee for Data Retention

Symbol

Min

VDR

2.0

Data Retention Current
Chip Select to Data
Retention Time

leeDR

Opemtion Recovery Time
Note:

-

Typ

-

Max
-

100 1

Unit

Test Condition

V
~

teDR

0

-

-

ns

tR

5

-

-

ms

CS

~

Vee-O.2V,

Yin ~ Vee -0.2V or
OV ::; Yin ::; O.2V

Vee = 3.0 V.

• LOW Vee DATA RETENTION TIMING WAVEFORM
Data retention mode

Vee -------~

2.2V

CS ~VDR - O.2V

OV

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589·8300 301

HM621400 Series

--------------Preliminary

4,194,304-Word x 1-Bit High Speed CMOS Static RAM
• FEATURES
• High Speed:
Fast access time 25/30/35/45 ns(max.) (P-version)
30/35/45 ns(max.) (LP-version)
• Single 5V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• TTL compatible: All inputs and outputs
• Thin plastic package for high density mounting

HM621400JP-25
HM621400JP-30
HM621400JP-35
HM621400JP·45
HM621400JLp·30
HM621400JLp·35
HM621400JLP·45
HM621400P-25
HM621400p·30
HM621400p·35
HM621400P-45
HM621400LP·30
HM621400LP·35
HM621400LP-45

Access Time
25 ns
30ns
35 ns
45 ns
30ns
35 ns
45 ns
25 ns
30ns
35 ns
45 ns
30ns
35 ns
45 ns

• PIN ARRANGEMENT
HM621400 Series

• ORDERING INFORMATION
Type No.

(CP-32D)

Package

4OO-mil, 32 pin
SOJ
(Cp·32D)

32·pin
TSOP (II)

(Top View)

• PIN DESCRIPTION
Pin Name

Function

Ao-A21

Address Input

DIN

DoUT

•

T"\~

.. ~ l __ ....

J.Ja~a UlpU~

Data Output

CS

Chip Select

WE

Write Enable

OE

Output Enable

Vee

Power Supply

VSS

Ground

NC

No Connection

HITACHI

302 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 1 4 0 0 Series
• BLOCK DIAGRAM
AoO----i~:::::l

A10----GO

A2. o----r~:::::l
A:J 0-----1
A4 0-----1

Memory Matrix
1024 X 4096

Vee

A6 0 - - - - 1

Vss

AeO---L~

A70----I.::0
Aso----i~:::::l

As 0 - - - - 1

Din

0----1
Dout

Input
Data
Control

~

O - - ' ; l l_ _ _~

WE o---+-~

DE

• FUNCTION TABLE
CS
H

OE

WE

IS8,IS81

Dou! Pin
High-Z

Ref. Cycle

X

Mode
Deselect

Vee Current

X

L

L

H

Read

ICC

Dou!

Read Cycle I, 2, 3

L

H

L

Write

ICC

Din

Write Cycle I

L

L

L

Write

ICC

Din

Write Cycle 2

-

Note: X: H or L

• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Voltage on any Pin Relative to VSS
Power Dissipation

VT

Value
-0.5*1 to +7.0

PT

1.0

Operating Temperature

Topr

oto +70

Storage Temperature

Tstg
Tbias

-55 to +125
-10 to +85

Storage Temperature Under Bias

Unit
V
W
°C
°C
°C

Note I. VT min. = -2.0V for pulse width"; 10 ns

• RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to +70°C)
Item

Symbol

Vee
Supply Voltage
VSS
Input High Voltage
VIH
Input Low Voltage
VIL
Note I. VIL min. = -2.0V for pulse width"; IOns.

•

Min

Typ

Max

Unit

4.5
0
2.2
-0.5*1

5.0
0

5.5
0
6.0
0.8

V
V
V
V

-

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 303

HM621400 Series

• DC CHARACTERISTICS (Ta =Oto+70°C, Vcc = 5V± 10%, Vss =OV)
HM621400P
Item

HM621400LP

Symbol
Min

Typ Max Unit

Min Typ Max

Unit

Test Conditions

~

Vee = Max.
Yin = VSS to Vee

-

-

2.0

~

Vee = Max.
Yin = VSS to Vee

2.0

~

CS=VIH
VI/O = VSS to Vee

-

-

2.0

~

CS=VIH
VI/O = Vss to Vee

-

150

rnA

CS = VIL, 11/0 = 0 rnA
Cycle = 25 ns

-

-

140

rnA

CS=VIL.II/O=OmA
Cycle = 30 ns

-

-

60

rnA

CS=VIH,
Cycle = 25 ns

-

-

5

rnA

CS =VIH.
Cycle = 30 ns

ISBI

-

-

10

rnA

OV ::; Yin ::; 0.2V or

-

-

0.1

rnA

VOL

-

0.4

V

IOL=8mA

-

V

IOL= 8 rnA

2.4

-

V

IOH =-4 rnA

-

0.4

VOH

-

-

V

IOH=-4mA

Input Leakage Current

\ILl I

-

-

2.0

Output Leakage Current

IIWI

-

-

Operating Vee Current

ICC

-

ISB
Standby Vee Current

Test Conditions

CS~Vee...().2V

CS~Vee...().2V

Vin~Vee...().2V

Output Voltage

2.4

OV ::; Yin ::; 0.2V or
Yin ~ Vee ...().2V

• CAPACITANCE (T a = 25°C,-f = I MHz)
Item
Input Capacitance

Symbol

Input/Output Capacitance

Typ

Cin

-

CI/O

-

Test Conditions

Max

Unit

5
10

pF

VIN=OV

pF

VI/O=OV

Note I. This parameter is sampled and not 100% tested.

• AC CHARACTERISTICS (Ta = 0 to +70°C, VCC 5V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: VSS to 3.0V
• Input rise and fall times: 4ns
• Input and Output timing reference levels: Input 1.5V
Output 1.5V
• Output load: See Figures
Output Load (8)
(for tCHZt twHZ. tow, toLZ & tOHz)

Output load (A)

+5V

Dout

~

255n

+5V

4BOn

~

Dout

4BOn

,:q~

~30PF'

Note: * Including scope & jig .

• READ CYCLE
Item
Read Cycle Time
Address Access Time

Symbol

HM621400·25P HM621400·30P/LP HM6214OQ.35P/LP HM621400-45P/LP
Min
25

tRe
tAA

-

Max

25

Chip Select Access Time
Chip Selection to Output in Low-Z

tAeS
teLZ"]

Output Enable to Output Valid

tOE
tOU"]

-

10

0

-

ICHZ*]
tOHZ']

0
0
5
0

-

Output Enable to Output in Low-Z
Chip Deselection to Output in High-Z
Chip Disable to Output in High-Z
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Deselection to Power Down Time

5

tOH
tpu
tpo

•

25

-

Min
30

-

Max

30
30

Min
35

-

Max

-

Max

Unit

-

ns
ns

45

35

-

-

10

-

ns
ns

-

35

-

5

-

13

-

15

0

-

0

-

10
10

0
0

10
10

0
0

-

5
0

-

5

-

-

20

-

20

5

Min
45

45
20

ns

-

ns

15
15

0
0
0

15

5

-

0

-

ns
ns
ns

0

-

ns

-

30

-

30

ns

15

HITACHI

304 Hitachi"America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM621400 Series

I~----------------~~-----------~

• READ TIMING WAVEFORM (2)*2, *3, *5

~

Address

Dout

======l=:--~=tO-H=-lkJ--. I----% I~ k
tRC

• READ TIM illiG WAVEFORM (3)*1, *2, *4, *5

cs

Dout

Notes:

I.
2.
3.
4.

Transition is measured ±200 mV from steady state voltage with Load (8). This parameter is sampled and not 100% tested.
WE is high for read cycle.
CS is low.
Address valid prior to or coincident with CS transition low.

5. OE=VIL.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300 305

HM621400Series - - - - - - - - - - - - - - - - - - - - - - - - - - • WRITE CYCLE
Parameter

Symbol

Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address setup Time
Write Pulse Width
Write Recovery Time
Output Disable to Output in High·Z
Write to Output in High·Z
Data to Write Time Overlap
Data Hold from Write Time
Ouput Active from End of Write

twe
tew
tAW
tAS
tWP
tWR
10HZ'S
tWHZ·S
tDW
tDH
lOW

HM621400·25P HM621400·30P/LP HM621400-35P/LP HM621400-45P/LP
Min
25
15
15
0
15
0
0
0
12
0
0

Max

-

-

10
10

-

Min
30
20
20
0
20
0
0
0
15
0
0

Max

-

10
10

-

-

Min
35
25
25
0
25
5
0
0
20
0
0

Max

-

-

-

15
15

-

Min
45
35
35
0
35
0
0
0
30
0
0

Max

-

-

15
15

-

-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

• WRITE TIMING WAVEFORM (1) (WE Controlled)

twc
Address

cs
WE

Din

Dout

•

HITACHI

306 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589·8300

Note

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM621400 Series
• WRITE TIMING WAVEFORM (2) (CS Controlled)

twe

Address

~

)
tAs

OIl

~

cs

tew

OIl

\

~

/

tAW

tWR*2
tWp'1

,\\\\\\\\\\\

WE

..

~

Din

I
tow

I I I I I I I I I I II
tOH

~

~xx

--------

Data In Valid

High Impedence *3

Dout
Notes:

~

OIl

I. A write occurs during the overlap (twp) of a low CS and a low WE.
2. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
3. If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a
high impedance state.
4. Oout is the same phase of write data of this write cycle.
5. Transition is measured ± 200 m V from high impedance voltage with Load (B). This parameter is sampled and not 100% tested.

$

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 307

HM621400 Series - - - - - - - - - - - - - - - - - - - - - - - - - - • LOW Vee DATA RETENTION CHARACTERISTICS (Ta = 0 to +70°C)

This characteristics is guaranteed only for L-version.
Item
Vee for Data Retention
Data Retention Current
Chip Select to Data Retention Time
Operation Recovery Time
Note: I. Vee = 3.0V.

Symbol
VOR
IeeOR
lCOR
tR

Min
2.0

Typ

-

-

0
5

-

-

Max

100*1

-

Unit
V

f.IA
ns
ms

Test Conditions
CS ____

H_i""9_h-_Z

tAW is measured from the later of CALEN going high, or addresses AO-A II transition with CALEN high to the end of
write cycle
tAS is measured from the latest of CALEN going high, addresses AO-A II transition with CALEN high, or address A 12
transition to the beginning of write cycle.
tWR is measured from the earliest of CSO, CS I, CE, or WE going high to the earlier of CALEN going high, or address
A 12 transition.
A write occurs during the overlap of a low CSO or CS I, a low CE, and a low WE.
Transition is measured ±200 m V from steady state voltage with Load (B). This parameter is sampled and not 100% tested.
Dout is not the same phase of write data of this write cycle. Normal read cycle shall be used for write verify. This does not
apply to the HM62AI68B and HM62A188B.

_HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819. (415) 589-8300 321

HM62A168, HM62A188 Series - - - - - - - - - - - - - - - - - - - - - - • AIR FLOW REQUIREMENTS

6

I
I

I
I
I

I
I
I

I

Ta= 70°C:

_ __ _ _ __ _ _ _ _ __

5

_ ____________ IL _____________1I____________ _

I
I
I

I
I
I

I
I
I

I
I
I

I

4

- -- -- -- -- -- -- t - -- -- -- - - I
I

:

--r -------------:------------I
I
I

:

-------------1-

2

-------------~---

I
I
I
I
I
I

I

I

I

Ta= 55°C

I
I

33 MHz

25 Mhz

-----------l----~-------J--~----------

3

I
I
I
I
I
I

Memory cycle time
for 385/386 system

I

I

Minimum Air Flow
Requirement (m/s)

I
I
I

I

---------~---I

I
I
I
I
I
I

I
I

-------4-- ---------I

I

I

I
I

I
I

I

I

I
I
I

I
I
I

----~----------~-I
I

Ta = 40°C

I

I

I

I

----------

o
25

50

75

100

tRCOR twc (ns)

_HITACHI
322 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589-8300

HM62A932 Series

--------------Preliminary

32k x 9 Data Cache RAM
• DESCRIPTION
The Hitachi HM62A932 is a high speed 288-kbit
synchronous static cache RAM optimized for use in
secondary caches for 32-bit microprocessor
system. This RAM has a 32-kword x 9-bit organization for building a 32k x 32-bit cache data array,
with byte parity by using four of these chips. The
HM62A932 is available in a 44-pin PLCC for high
density mounting.
•
•
•
•
•
•
•

FEATURES
32-kword x 9-bit organization
Synchronous read and write
Internal burst read/write address counter
Self-timed write
Matches timing of 50 MHz 32-bit micro processor
Additional address strobe input for implementing
extended burst

(CP-44)
• PIN ARRANGEMENT
HM62A932 Series
ADSC
Al Al AfjJ

6
A2

• ORDERING INFORMATION
Type No.
HM62A932CP-14
HM62A932CP-19
HM62A932CP-24
HM62A932CP-34

Access Time

CPU Clock Rate

14ns
19ns
24ns
34 ns

50 MHz
40 MHz
33 MHz
25 MHz

Package
44-pin
PLCC

5

4

elK

A5SP
3

2

As

Vee A7

Ag Am

1 44 43 42 41 40

7

39

All

A3

8

38

A12

A4

9

37

A 13

As

10

36

A14

Vss

A;;

11

35

Vss

12

34

1/07

1/00 13

33

1/06

1/01

14

32

Vss

Vss

15

31

Vee

Vee

16

30

1(05

1/02 17

29

1/04

18 19 20 21 22 23 24 25 26 27 28
NC

1/03

Vss

Vr.r.

WE ~~Vss

CE

CSt

eso

Vss
1/°8

(Top View)

• PIN DESCRIPTION

•

Pin Name

Function

CLK

Clock Input

ADSP

Address Status Input from MPU

ADSC

Address Status Input from the Cache Controller

CSo, CSI

Complementary Chip Select Input

AO-A14

Base Address Input

ADV

Synchronous Address Advance Input

WE

Synchronolls Write Enable Input

OE

Asynchronous Data Output Enable Input

1/00-1/07. I/OS

Input/Output Data Pin

NC

No Connection

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 323

HM62A932 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM

OE

A14- Address
Register
A2-

I

---

.-

I,.I,.l,.I,.-

8-kword x 9-bit

A1 Burst
AO- Control

.=

-r

r----

-

Write Selector

+ ...-

.----'

ADSC-<::
ADSP -<::
ADV -<::
WE -<::
~CS1 -<::
CLK-

-

.tv

. . 1/00-1/08

n

•

Input Data
Register

II

J

Burst &
RDIWR
Timing Control

Read
Selector

I

T

_~

W.P.G

_HITACHI
324 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 A 9 3 2 Series
• FUNCTION TABLE
Table 1. Synchronous Operation
CSo

CSI

ADSP

ADSC

ADV

WE

CLK

I/O Pin

Function

X

H

X

X

X

X

~

L

X

X

X

X

X

~

High-Z
High-Z

Disable

~

Output

Latch Base Address Read Address

Input

Latch Base Address Sample Write Data
Start a Self-Timed Write

H

L

L

X

X

X

H

L

H

L

X

L

H

L

H

L

X

H

~

~

Disable

Output

Latch Base Address Read Access

~

H

L

H

H

L

L

Input

Sample Write Data Advance Burst Count
Start a Self-Timed Write

H

L

H

H

L

H

~

Output

Advance Burst Count Read Access

H

L

H

H

H

L

~

Input

H

L

H

H

H

H

~

Output

Start a Self-Timed Write
Read Access

X = Don't care, H = High, L = Low, High-Z = High Impedance

Table 2. Asynchronous Output Control (See Notes 2 and 3 Below)
OE

I/O Pin

L

Output

H

High-Z

Notes:

I. Two separate address strobe inputs are provided and both will load a new base address. ADSP, from the MPU will override
all other functions and cause a read access to the base address. ADSC, from the controller, is affected by WE if ADSP is
inactive, and ADSC will start either a read or write cycle to the base address.
2. The CSo and CS 1 inputs are sampled with the addresses when ADSP or ADSC is sampled active. Only if CSo and CS 1 are
sampled active will WE or OE affect the chip.
3. Any time WE is active when ADSP is inactive, a self-timed write will start.
4. During data read cycles, data is always presented asynchronously with clock after OE becomes low.
5. If the asynchrous OE signal is activated during a self-timed write cycle, I/O pins will be in High-Z state.
6. OE must not be driven by any controller when setting up for a write cycle, since the data collision would corrupt the write data.

•

HITACHI

Hitachi America, Ltd . • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819· (415) 589·8300 325

HM62A~Series---------------------------------------------------------

Pin Description

CLK

Clock input signal. It samples all of the input signals except OE.
Address status input signal from MPU. When activated. a new "base" address is latched and an internal read access is
performed. All other synchronous inputs are ignored when it is sampled active.
Address status input signal from the cache controller. When activated. a new "base" address is latched. Used during
extended burst. and write-back cases when the cache controller must tell the device what addresses to access.
Complementary chip select input signals. These are sampled along with the addresses when ADSP or ADSC is
sampled. For any read/write or data bus activity to occur. CSo must be sampled high and CS I must be sampled low.

AO.AI4

Base address input signals. They are sampled when ADSP or ADSC is active. Ao-AI4 may change after ADSP or
ADSC samples them. Al and AO are latched and modified by the internal burst counter which XORs the bits in a
certain burst order.
Address advance input signal. When ADV is sampled active. and ADSP and ADSC are both sampled inactive. ADV
will increment the burst counter prior to a read or write access. If ADV and WE are sampled active. the address will
be incremented before a self-timed write starts. If ADV is sampled active with WE inactive. the address will be
incremented before a read access starts.
Write enable input signal. When WE is sampled active and ADSP is sampled inactive. a self-timed write will start.
When WE is sampled inactive. a self-timed write will start. When WE is sampled inactive. a read access will start.
Active WE with ADSC active will cause a write to occur.
Asynchronous data output enable signal input. When active. the I/O pins will be driven will be driven with the read
data available inside chip. OE activated while an internal self-timed write is in progress will cause the I/O pins to
be High-Z. OE must be activated while an internal self-timed write is in progress will cause the I/O pins to be
High-Z. OE must be inactive with enough margin before a self-timed write is started to guarantee that no data bus
contention occurs.

1/00.1/08

Input/Output data pins .

• FUNCTIONAL DESCRIPTION
This cache RAM contains both data and address edge triggered latches to perform high speed synchronous accesses. These latches.
combined with internal self-timed write logic. allow the write decision to be postponed until it is known that a write must be done.
An internal burst address counter is provided to support burst read and burst write cycles. The counter sequences through the four
internal bytes on the rising edge of the clock when inpllt is. "ampled active. !f the device reaches end of the norma! burt:t sequence, the
counter will wrap-around to the initial base address.
The rules for handling the low order address bits during a burst sequence is shown here (the low order address bits):
Initial access:
Next burst access:
Next burst access:
Next burst access:
Next burst access:

Use base address provided with ADSC or ADSP
Invert only base address AO
Invert only base address A I
Invert only base address A I-AO
Wrap-around. use initial base address

•

HITACHI

326 Hitachi America, Ltd . • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 A 9 3 2 Series
• ABSOLUTE MAXIMUM RATINGS
Item

VT

Value
-D.5*1 to +7.0

Unit

Voltage on any pin relative to Vss

Symbol

Power Dissipation

PT

1.2

W

V

Operating Temperature Range

Topr

o to +70

°c

Storage Temperature Range

Tstg

-55 to +125

°c

Storage Temperature Range Under Bias

Tbias

-10 to +85

°c

Note: I. VT min = -2.5 V for pulse width

~

10 ns.

• RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to 70°C)
lfameter

Symbol

Min.

Typ

Max.

Vce

4.5

5.0

5.5

V

VSS

0

0

0

V

SIIpply Voltage

Unit

In put High (Logic I) Voltage

VIH

2.2

-

6.0

V

In put Low (Logic 0) Voltage

VIL

-D.5* I

-

0.8

V

Note:

I.

VIL mm = -2.0V for pulse width ~ 10 ns.

• DC CHARACTERISTICS (Ta = 0 to 70°C. Vee = 5V ± 10%, VSS = OV)
_.
P.arameter
Input Leakage Current

Min.

Typ*1

I ILl I

-

-

Max.
2

Output Leakage Current

IILOI

-

-

10

Il A

Output Disable
VI/O = VSS to Vee

Active Operating Power
Supply Current

ICC

-

-

TBD

mA

TBD
IOL=3.2 rnA
IOH=-2.0mA

_.

Symbol

Unit

Il A

O,.tput Low Voltage

VOL

-

-

0.4

V

Output High Voltage

VOH

2.4

-

-

V

Test Conditions
Vee =Max., Vin

=VSS to Vee

Note: I. Typical limits are at Vec = 5.0V, T. = +25°C and specified loading

• CAPACITANCE (Ta = 25°C, f = 1 MHz)*1
Max

Unit

Input Capacitance

Parameter

Symbol
Cin

Min
-

5

pF

Test Conditions
Vin=OV

Input/Output Capacitance

CI/O

-

10

pF

VI/O=OV

Note: I. This parameter is sampled and not 100% tested .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 327

HM62A932 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • AC CHARACTERISTICS (Vcc =5V ± 10%, Ta =0 to 70°C)
Test Conditions
•
•
•
•

Input and Output timing reference levels: 1.5V
Input pulse levels: VSS to 3V
Input rise and fall times: 3ns
Output load: See figures
5V

5V

11800

11800

Dout <>---1"---+

Dout <>---1"---+

5720

5720

Output Load (A)

Output Load (8)
(for tOLZ & tOHz)

, Including scope & jig.

Parameter

Symbol

HM62A932-14
Min
20
8
8
3
3
3
2
2
2
3
3
3
2
2
2

Max

HM62A932-19
Min
25
9.5
9.5
3
3
3
2
2
2
3
3
3
2
2
2

Read Cycle Time
teYC
Clock Pulse High
teH
Clock Pulse Low
teL
Address Setup Time
tAS
ADS Setup Time
tADSS
OU!i>Ut Select Setup Time
tess
Address Hold Time
tAH
ADS Hold Time
tADSH
Chip Select Hold Time
teSH
Input Data Setup Time
tDS
ADV SetupTime
tADVS
Write Enable Setup Time
tWES
Input Data Hold Time
tDH
ADV Hold Time
tADVH
Write Enable Hold Time
tWFli
Clock to Output Valid
14
teD
Output Enable Low to Output Valid
7
tOE
t012*1,*2
Output Enable Low to Output Low-Z
0
0
Read Data Hold After New Clock
3
3
toc
tOHZ*I,*2
Output Enable High to Output High-Z
7
System Clock Skew
I
tSKEW
50
40
Frequeocy
..
Notes: I. TranSItIon IS measured ± 200 mV from steady state voltage WIth Load (8).
2. This parameter is sampled and not 100% tested .

•

5pF'

Max

-

-

-

-

-

HM62A932-24
Min
30
II
II
5
5
5
3
3
3
5
5
5
3
3

Max

-

-

-

HM62A932-34
Mio
40
14
14
5
5
5
3
3
3
5
5
5
3
3

Max
-

-

-

-

-

-

-

,

-

,

19
8

-

24
9

-

34

-

0
3

-

0
3

10

-

-

-

8

-

9

-

I

-

I

-

33

\0
-

I

25

HITACHI

328 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

Uoit
os
ns
ns
os
os
ns
os
ns
ns
os
ns
ns
ns
ns

".

ns
os
ns
os
ns
ns
MHz

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 A 9 3 2 Series
• TIMING WAVEFORMS
(1) Read Cycle Followed by Burst with Wait State Added to Data C

leve
CLK

CS a

ADV

Data Out

A-Data from
B-Data from
C-Data from
D-Data from

Note:

Base ADDR
Base ADDR except Ao is now AO
Base ADDR except Al is now Al
Base ADDR except AO and Al are now AO and Al

I. If ADSP or ADSC goes low during a burst cycle, a new address will be loaded, and another burst cycle will be started .

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 329

HM6~~-------------------------------------------------(2) Write Cycle Followed by Burst Write with Wait State Added to Data C

elK

Data In

Data Out

o
A-Data to be written to Base ADDR
B-Data to be written to Base ADDR except AO is now AO
C-Data to be written to Base ADDR except A I is now AI
D-Data to be written to Base ADDR except AO and Al are now AO and Al
E-Data to be written to new Base ADDR loaded by ADSC

_HITACHI
330 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 A 9 3 2 Series
(3) Burst Mixed Read/Write Cycles

elK

tWES

tWEH

WE

ADV

OE

Data in

Data Out

RA-Data from Base ADDR
W A-Data to be written to Base ADDR
WB-Data to be written to Base ADDR except AO is now Ao
We-Data to be written to Base ADDR except AI is now AI
WD-Data to be writlen to Base ADDR except AO and Al are now Ao and AI
WE-Data to be written to new Base ADDR
WF-Data to be written to new Base ADDR except Ao is now Ao

.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 331

HM6~Series------------------------------------------------------

(4) Sequencial ADSPIADSC Cycles

elK

Data Out

--------4«
lA-Data from Base ADDRI
2A-Data from Base ADDR2
2B-Data from Base ADDR2 except Ao is now AO
2C-Data from Base ADDR2 except AI is now AI
2D-Data from Base ADDR2 except AO and AI are now Ao and AI

(5) System Clock Skew Requirements

ClK

Other
System
Clocks

For this synchronous memory to meet its system timing requirements, the system clock skew must not exceed the specified range.
Larger clock skews will require smaller c1ock-to-access times (tCO).

_HITACHI
332 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM62A2016 S e r i e S - - - - - - - - - - P r e l i m i n a r y
DuaI8,192-Word x 2O-Bit Static Cache Memory
• DESCRIPTION
The HM62A2016 is a high speed 327,680-bit
cache memory organized as two banks of 8,192
words by 20-bits. The device includes dual address
latches, dual chip select latches, data multiplexer
with multiple chip enables and output enables. It
can be used in a cache memory system adopting
Harvard architecture which requires separate
instruction and data storages.
• FEATURES
• High speed: up to 33 MHz operation
Address access time: 17/20/25/30 ns
Output enable access time: 7/7/8/8 ns
• Dual 8k x 20 memory arrays with data multiplexer
• Dual latches for address and chip select inputs
• Expandable both in width and depth
Two separate chip selects

(CP-S2)

• PIN ARRANGEMENT
HM62A20 16 Series
ALEA

A2 AJ AI. As Ai;;
A,
A()

vss
lID,

• 52-pin PLCC

vss

• ORDERING INFORMATION

1104
1/05

1/03

Access Time

HM62A2016CP-17
HM62A2016CP-20
HM62A2016CP-25
HM62A20 16CP-30

17 ns
20ns
25 ns
30 ns

Package
52-pin
PLCC
(CP-52)

A,o

A7 As As

All
~

A12

p

vss
1/019

1/00
1/02

Type No.

ALES

vee

~

1/018

~

vss

P

1/015

1/017

vee
1/016

1/014

1/06

1/013

vss

vss

1/07

1/0'2
1/08

vee

1/09

OEA vee WEB
CS
1011
WEA vss 6EB
CS 1/010

(Top View)

• PIN DESCRIPTION
Pin Name

Function

AO-AJ2

Address Inputs

ALEA,ALEB

Latch Enables

OEA,OEB

Output Enables

WEA,WEB

Write Enable

1/00-1/019

Data Inputs Outputs

CS,CS

Chip Selects

• HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 333

HM62A2016Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM
OEA----~

Latch Enable
Side A (ALEA)
Chip Select (CS)
Chip Select (CS)

WEA

:=+:::;::1
8k x 20 Array

Address Bus (Ao-A12)

Array A

13

i----n;.......... I - - _ Data Bus
1/00-1/019

MUX

Latch Enable
Side B (ALEB)

OEB _ _ _-....1

_HITACHI
334 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 A 2 0 1 6 Series
Signal Description
Signal Name

Pin Number

Signal Description

AO-AI2

3-9
46--51

Shared address inputs to both Memory Array A and Memory Array B. Current A(}-A 12
values are latched into Latch A or Latch B by the falling edge of ALEA or ALEB.

ALEA,ALEB

2,52

Latch enable inputs. When ALEA or ALEB is high, Latch A or Latch B is transparent
to address and chip select input values. The falling edge of ALEA and ALEB latches
current inputs at A(}-A 12 and current states of CS and CS. These latched values remain
applied to the respective memory arrays until ALEA or ALEB transition to a high state.

CS,CS

30,31

Active low and active high chip select inputs. The current states of CS and CS are
latched by the falling edge of ALEA and ALEB. When CS is low and CS is high read
and write access to both arrays is possible. CS should be grounded and CS should be
tied to Vee in applications where no device depth expansion takes place. See the
Depth Expansion Section for a detailed description of the chip select function.

24,29

Active low write enable inputs. WEA controls writing into Array A and WEB controls
writing into Array B. Both WEA and WEB must not be both low simultaneously.

25,28

Active low output enable inputs. OEA and OEB are used to control driving of stored
data from Array A or Array B onto the I/O lines during read operations. OEA and OEB
must not be both low simultaneously.

1/00,1/019

11-13,15-18
20--22,32-34,
36--39,42-44

Data inputs and outputs. These are three-state lines that provide data access to both
memory arrays.

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 335

HM62A2016 Series
• FUNCTION TABLE
CS

CS

ALEA

ALEB

WEA

WEB

OEA

OEB

L

X

X

*\
*1

X
X

X
X

X
X

X
X

H

H
L

*1
*1

Operation
Not Selected

I/O Status
Outputs High-Z

X

X

H

H

H

H

Not Selected
Data I/O's Disabled

Outputs High-Z
Outputs High-Z

H

L

H

X

H

H

L

H

Read from Array A
(Current Addresses)

Data Out

Read from Array A
(Latched Addresses)

Data Out

H

L

L

X

H

H

L

H

H

L

X

H

H

H

H

L

H

L

X

L

H

H

H

L

Read from Array B
(Current Addresses)
Read from Array B
(Latched Addresses)

L*2

Not Allowed in
Same Phase

Data In
Data In

H

L

X

X

X

X

L*2

Data Out
Data Out
-

H

L

H

X

L

H

H

H

Write to Array A
(Current Addresses)

H

L

L

X

L

H

H

H

Write to Array A
(Latched Addresses)

H

Not Allowed in
Same Phase

-

L*4

Not Allowed in
Same Phase

-

Data In
Data In

H
H

L
L

X
X

X
X

L*3
L*4

H
H

L*3
H

H

L

X

H

H

L

H

H

Write to Array B
(Current Addresses)

H

L

X

L

H

L

H

H

Write to Array B
(Latched Addresses)

H

Not Allowed in
Same Phase

-

Not Allowed in
Same Phase
Not Allowed in
Same Phase

-

H

L

X

X

H

L*4

L*4

H

L

X

X

H

L*3

H

L*3

H

L

X

X

L*5

L*5

X

X

-

X =Don't care, H =High, L =Low, High-Z = High Impedance
Notes: I. CS and CS values shown in the table must have propagated through transparent latches and meet specified chip select setup
times before a deselect operation can occur.
2. If data are read simultaneously from both arrays, an undefined data outputs. Specified AC and DC parameters are not
guaranteed in this state.

3. Simultaneous reading and writing of a single array or of both arrays is not permitted.
4. Simultaneous reading from one array while writing to the other array is not possible.
5. Simultaneous writing to both arrays is not permitted during normal R3000 based cache operation.

_HITACHI
336 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 A 2 0 1 6 Series
• FUNCTIONAL DESCRIPTION

The HM62A2016 is a highly-integrated memory
device with several performance-enhancing features
which allow direct interfacing to a MIPS R3000 or
R3000A RISC processor. Two independent address
latches, with fast setup times, are provided on-chip to
allow faster addressing of two 8k x 20 memory arrays,
Array A and Array B. Address inputs and data I/O lines
are shared between the two arrays.
Two sets of DE and WE inputs, coupled with an onboard multiplexer control read and write access to each of
the arrays. Integrating a 2: I output data multiplexer onchip reduces the problem of data bus contention that may
occur when using discrete SRAMs and multiplexers, and
allows easier synchronization of output enable signals.
OEA and DEB inputs directly control the driving of
stored data at the outputs of the HM62A2016 during read
operations. Fast (7 ns) output enable and disable times are
matched and permit data to be quickly taken off the data
bus as well as driven on. This high level of device feature
integration demonstrated by the HM62A2016 allows construction of a dual 32-kbyte cache memory subsystem by
combining only three devices together to reach the full
60-bit tag plus data width requirements of the MIPS
R3000(a) processor.
The HM62A2016 is designed to permit storage and
retrieval of tag address and cache data information to and
from the two memory arrays in a direct-mapped, split
data/instruction cache format. It is functionally compatible
to and meets all MIPS R3000(A) cache memory timing
requirements. The HM62A20 16 fully supports
"pipelined" reads and writes, as described below.
Valid addresses that appear at Ao-AI2 inputs are recognized by on-chip Latches A or B when they are transparent (i.e. when ALEA or ALEB inputs are high).
Current address input values are latched by the falling
edge of ALEA and ALEB.
For an R3000(A) to HM62A2016 cache interface,
addresses are latched during the first phase of a 2-phase
read operation cycle, and valid data appears at outputs
(l/Oo-I/O 19) during the second phase. These addresses
will remain latched and applied to Array A or Array B as
long as ALEA or ALEB remains low. Similarly, for a
write operation, valid addresses are also latched during the
first phase, while data is actually written into the
addressed location during the second phase.
These sequential reads occur in a pipe-lined manner,
where data or instructions are read from one array during
the same phase when addresses for a subsequent read
from the other array are latched. Similarly, alternating
consecutive writes to the two memory arrays are possible
as long as the minimum 2-phase write operation cycle is
met with correct timings.
A write operation to a memory array can occur in the
phase that immediately precedes or follows a read operation from the other array.
It is not possible to write to or read from both arrays at
the same time. Nor is it possible to do more than one read
or write per phase. It is not possible to read from or write

•

to the same array in consecutive phases because of the
minimum 2-phase read/write operation cycle requirements. See the Function Table for a detailed listing of prohibited operations, as well as legitimate read and write
modes.
Array A and B are interchangeable and can arbitrarily
be designated as for data or instruction storage.

Depth Expansion
Overview
Each HM62A2016 has a latched active high chip
select input (CS) as well as an active low input (CS).
Depth expansion is achieved by connecting address line
(AI3) into CS and CS inputs of two HM62A2016's and
grounding or tying to Vee the other remaining chip select
of each device, as shown in figure I. Corresponding (A or
B) control inputs (DE, WE, and ALE) of depth-expanded
HM62A2016's should be tied together.
The latched chip select function of the HM62A2016 is
designed to permit one array to be latched "on" (active for
read or write access) while the other corresponding array
of a different davice is turned "off".
Detailed Description
_
The current states of CS and CS are latched on-chip
by the falling edge of ALEA or ALEB. An "array select"
state (both CS = I and CS = 0), that passes through a
single transparent Latch (A or B) and meets tCSL timing,
will permit that particular array (A or B) to be active for
read and write access. An array in a selected state will
remain active as long as its ALE input remains low. If an
array select state is recognized by both transparent latches
(A and B), then both arrays for that HM62A2016 device
will be active.
A "deselect" state (either CS = 0 or CS = I) that propagates through a single transparent latch (A or B) and
meets the minimum specified chip select setup time will
disable both read and write access to that respective array
(Array A or Array B). If a deselecting input state passes
through both transparent latches A and B, then read and
write access to both arrays is disabled.
Example
An example of consecutive reads from two depthexpanded HM62A2016's is shown in Read Cycle No.2.
In the first phase, an instruction is read from the I-cache
of the "low RAM". At the beginning of this phase, A13
transitions from low to high and causes the selection of
the D-cache array of the "high RAM" for a read operation
in the following phase. This high A 13 state also deselects
the D-cache array of the "low RAM" for the following
phase.
Consecutive operations are possible because the latching of A 13 to select or deselect an array can occur in the
same phase as a read or write operation from another
array of a different HM62A2016.
As a further example, the timings for a depthexpanded store-load sequence are shown in Write Cycle
No.2 .

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 337

HM62A2016Series - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Data Bus

"Low RAM"

"High RAM"

HM62A2016

HM62A2016

IWR'
ICIK
IRO'

WEAB
ALEA I-Cache
OEA

OWR'
OCLK
ORO

WEB
ALEB lo-cachei
OEB

/

11'20

POO-OO19

Addr. Low
(Ao-A12) cs CS

~

Addresses
(Ao-A12) 1~

B

WEA
I-Cache ALEA
CEA
WEB

lo-cach~ ALEB
OEB
Addr. Low
(AO-A12) CS CS

l-

/

A13

Figure 1. 16k x 20 x 2 Cache SRAM from two 8K x 20 x 2 Cache SRAMs

•

HITACHI

338 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------------------------------HM~16Series

• ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage relative to Vss
Voltage on any pin relative to Vss
Power Dissipation

Symbol
Vee
Yin

Value
-0.5*1 to +7.0
-0.5'1 to Vee +0.3

Unit
V
V

PT

2.0

o to +70

W
°C

Storage Temperature Range

Topr
Tstg

-55 to +125

°C

Storage Temperature Range Under Bias

Tbias

-10 to +85

°C

Operating Temperature Range

Note: I. Yin min = -2.5 V for pulse width 10 ns.

• RECOMMENDED DC OPERATING CONDITIONS (Ta =0 to +70°C, exceeding minimum air flow requirement)
Parameter
Supply Voltage

Symbol
Vee

Min.
4.5

Typ
5.0

Max.
5.5

Unit
V

VSS
VJH

0
2.2
-0.5'1

0

0
Vee + 0.3

V

-

0.8

V

Input High (Logic I) Voltage

Input Low (Logic 0) Voltage
VIL
Note: I. VIL mtn = -2.0V for pulse width 10 ns.
2. The supply voltage with all Vee pins must he on the same level.
3. The supply voltage with all VSS pins must he on the same level.

V

• DC CHARACTERISTICS (Ta = 0 to 70°C, VCC = 5V ± 10%, VSS = OV, exceeding minimum air flow requirement)
Parameter
Input Leakage Current

Symbol

Min.

I III I

-

-

Max.
2.0

Unit
J.1A

IILOI

-

-

2.0

J.1A

lee

-

-

220

rnA

0.4
VOL
2.4
VOH
Note: I. Typical limits are at Vee = 5.0V, Ta = +25°C and specified loading

V
V

Output Leakage Current
Active Operating
Power Supply Current

Typ

Output Low Voltage
Output High Voltage

-

Test Conditions
Vee = Max., Yin = VSS to Vee
Output Disable
VI/O = VSS to Vee
Yin = VSS to Vee, Outputs Open
Load, lout = 0 rnA, !cycle = Min. Cycle,
CS VIL Max., CS = VIH Min.

=

IOL=8mA
IOH=-4mA

• CAPACITANCE (Ta = 25°C, f= I MHz.)"
Parameter
Input Capacitance
Input!Output Capacitance

Symbol
Cin

Min

-

CI/O
Note: I. This parameter is sampled and not 100% tested.

•

Max
5
10

Unit
pF

Test Conditions
Vin=OV

pF

VI/O=OV

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300 339

HM62A2016 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • AC CHARACTERISTICS (Vcc = 5V ± 10%, Ta = to 70°C, exceeding minimum air flow requirement)
Test Conditions
• Input and Output timing reference levels: 1.5V
• Input pulse levels: VSS to 3V
• Output load: See figures
+5V

+5V

4800

4800
1/0

1/0
50pF*

2550

5pF*

2550

Vss

Vss

Output Load (A)

Output Load (8)
(for tOL2 & tOHz)

*Including scope & jig .
• READ CYCLE
Parameter

Read Cycle Time

Frequency

33 MHz

25 MHz

20 MHz

16.67 MHz

Symbol

HM62A2016-17

HM62A2016-20

HM62A2016-25

HM62A2016-30

Min

Min

Address Valid to Output Valid
Chip Select Access Time
Output Enable Low to Output Valid

tAA
tACS'1

Output Enable Low to Output Low-Z

tOE
tOLZ

Output Enable High to Output High-Z

tOHZ

Output Hold from Latch Enable

tLOH

Address Setup to Latch Enable Low

tASL

Address Hold from Latch Enable Low
Chip Select Setup to Latch Enable Low

tAHL
tCSL*1

Chip Select Hold from Latch Enable Low

tCSH*t

Output Enable Separation Time
T

~

.. _ .... 11:_1.- .. _

&....aLt.••1I J

Note:

UgH lU

".1.1 .. _
1"\.UUJt:::'J~

Min
17
-

tRC

"'.'"
"ctilU

tosp
ILAV

I

Max

Min

Max

Max

Unit

Max

-

20

-

25

-

30

-

ns

17

-

17

-

7

-

7

25
25
8

-

-

-

30
30
8

ns

-

20
20

2
0
3
5
2
5
2
2

-

-

ns

I
0
3

-

5
2

-

-

5

-

2
2

-

.

.j

7
-

2
0
3
5
2
5
2
2

-

.j

-

7

-

I

j

8

-

2
0
3
5
2
5
2
2
3

ns
ns

8

ns

-

ns

-

ns

-

ns

-

ns

-

ns

I. Indicates depth expansion parameter only. These parameters apply for both CS and CS.

_HITACHI
340 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

ns

ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 A 2 0 1 6 Series
• WRITE CYCLE
Frequency
Parameter

Symbol

33 MHz

25 MHz

20 MHz

16.67 MHz

HM62A20 16-17

HM62A2016-20

HM62A2016-25

HM62A2016-30

Min
20

Write Cycle Time

twe

Min
17

Address Valid to End of Write

tAW

12

-

Data Valid to End of Write

IDS

6

tDH
twp
tew'l

0
10

Address Setup Time Before Write Start

tAS

0

Latch Enable Hold from End of Write

tWHL

0

Address Setup to Latch Enable Low

tASL

5

Address Hold from Latch Enable Low

tAHL
teSL*1

2

teSH*1

Data Hold from End of Write
Write Pulse Width
Chip Enable to End of Write

Chip Select Setup to Latch Enable Low
Chip Select Hold from Latch Enable Low

Max

12

Min
25

15

-

-

8

-

8

-

0

-

0

15
15

5

5

-

2

-

2

0
0
2
5

20

17
20
0
0
5
2

5
2

2
2
2
3
3
3
tLAY
I. Indicates depth expansion parameter only. These parameters apply for both CS and CS .

ReadIWrite Separation Time

tRWS

Latch High to Address Valid
Note:

Max

Max

-

Min
30

Max

-

2

-

-

3

-

25
10
0

-

22
25

0
0
5
2
5
2

Unit
ns
ns
ns
ns
ns

os
ns
os

os
ns
ns
ns
ns
ns

• TIMING WAVEFORMS

Read Cycle No.1 (CS = Low, CS, WEA, WEB = High)
Phase 1

Phase 2

Phase 1

Phase 2

tAC

tAC

tAC

tAC

Addresses
(AO-A12)

ALEA
(IClk)

ALEB

(DClk)

Data/Instruction

Out

OEA
(IRd')

OEB
(DRd')

Notes:

1. All timing parameters are measured with output Load A unless otherwise noted.
2. Read cycle time (tRe) refers to read operations with current addresses applied to a transparent (high) latch. Read timing
parameters are referenced from the last valid address to the first transition address.
3. Transition is measured ±200 mV from steady state voltage with output Load B for tOLZ and tOHZ
These parameters are sampled and not 100% tested .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 341

HM~16Series -------------------------------------------------------Read Cycle No.2 (WEA, WEB

=High) (Consecutive Reads from Two Depth-Expanded HM62A2016's)

Phase 1

.. ..
tCSL'

Phase 2

tCSH*

Phase 2
tCSL'

tCSL*

tCSH*

~--=-=-=---J~I--'

tCSL*

~---J~ tCSH*

CS • "Low RAM'
CS • "High RAM'
(A13)

Addresses
(Ao-A12)

Phase 1

(Data Address 0)

(Data Address 1)

ALEA
(IClk)

ALES
(DClk)

("Low Ram")

("High Ram")

("Low Ram")

("Low Ram")

Data/Instruction
Out

OEA
(I Rd')

OES
(DRd')

Note:

I. All other non depth-expansion parameters shown in Read Cycle No. I still apply, and are not shown for simplicity .

•

HITACHI

342 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

--------------------------------------------------------HM62A2016 Series
Write Cycle No.1 (CS

=Low, CS, WEA =High)
Store

Addresses
(AO-A12)

Load

Phase 1
twc

Phase 2
tRC

Phase 1
tRC

Phase 2
tRC

) QData Address aDVI\..

(!nstruction
Address 1)

) ~Data Address 1DVI\..

(!nstruction
Address 2)

tLAV

)

K

tASL
tAHL

ALEA
(IClk)

ALEB

-

(DClk)

Datall nstruction

}

.---l

V

1\

--

\

tLCH
tAA

l

~

--

)

tionO Out)

~

OEA

/

--

f'o r-"

1\

i++

tos

\
tAW

Notes:

/
tOHZ

-

f-

-~

toE

V

tosp

~

f-

..

tAA

'-

f-

tOH

twp

tAS
WEB

tOLZ

out)

r-

\

OEB
(DRd')

(DWr')

'r

~
tion lOut) OO~
K>O --

tOE
tRWS

J

~+-

\

--tOLZ

tLOH

tAHL

(OataO In)) i--

T

V

~

tASL

tWHL l:tLAt

tRWS
(I Rd')

/

/

\

V

I. All timing parameters are measured with output Load A unless otherwise noted.
2. Write cycle time refers to write operations with current addresses applied to a transparent (high) latch.
3. Transition is measured ± 200 m V from steady state voltage with output Load B for tOLZ and tOHZ. These parameters are
sampled and not 100% tested.

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589·8300 343

HM~16Series -------------------------------------------------------Write Cycle No.2 (WEA = High) (Store-Load Sequence of Two Depth-Expanded HM62A2016's)
Store
Phase 1
tCSL*

tCSH*

Load
Phase 1

Phase 2
tcSL*

tCSH*

ICSL*

ICSH*

Phase 2
ICSL*

tCSH*

~~li~c~----~.~~~~I~cr-----~.~I~~~~~~~~_+c-~~-1~I~

CS • "Low RAM*
CS • "High RAM*
(A13)

Addresses
(Ao-A12)

(Data Address 0)

(Data Address 1)

ALEA

(IClk)

ALEB

(DClk)

Data/Instruction
Bus

lACS'

DEA
(IRd')
Icw'

lACS'

DEB
(ORd*)

WEB
(DWr*)

Note:

\

I

t

I

I. All other non depth-expansion parameters shown in Write Cycle No. I still apply, and are not shown for simplicity.

_HITACHI
344 Hitachi America, ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------------HM~16Series

Air Flow Requirements

6

,
5

I

-----r - -- - - - - - -

I

I

I

I

"I - - - -,- - - - - - - "I - - - - - - -

r - - - - - -

,,
Minimum
Air Flow
Requirment

I

4

-----r---------

3

- - - - - r - - - - - - - - -

I

I

I

r------

,

Ta= 70 0 e
I

I

"I - - - -,- - - - - - - "I - - - - - - -

I

I

I

I

"I - - - -,- - - - - - - "I - - - - - - -

r - - - - - -

(ms)

,

2

,

,

- - -,- - - - - - - "I - - - - - - -

r - - - - - -

,

,,

25

30

-----"l-------r-----o

Ta

10

= 70 e
0

17

20
tRC or twc (ns)

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 345

HM62A9128/8128 Series

----------Preliminary

131,072-Word x 9(8)-Bit Synchronous Cache SRAM
• FEATURES
• For high speed cache memory applications
• Pipeline access capability with on-chip address,
strobe and 1/0 registers
• Organization: 128 kword x 9(8) bit
• SOJ: 32-pin
• TIL 1/0
• MAIN CHARACTERISTICS
Type No.
Clock Cycle Time
Clock to Data Valid
Power Dissipation

Spec.
20 ns (min)
10 ns (max)
788 mW (max)

• PIN ARRANGEMENT
Remarks

HM62A9128/8128 Series

elK
50 MHz

~--~~--~

A14

~

~s

AS

WE
A13

A4

As

~
~

~o
~1

As
• ORDERING INFORMATION
Type No.
HM62A9I 28JP-20
HM62A8128JP-20

Clock Cycle Time

Package

20ns
20 ns

32-pin SOl 400 mil.
(CP-32D)

vee

A15

Al

DE

~

~2

es

1/00
(NC)
I/O,

1/07

1/02
1/03

I/0s
1/05

vss

liDs

....:.:.r 1/04

~::...... ______

(Top View)

• PIN DESCRIPTION
Pin Name

Function

AO-A12

Address

1100--1108

Input/Output

WE

Write Enable

OE

Output Enable

CE

Chip Enable

CLK

Clock Input

Vee

Power Supply

VSS

Ground

NC

No Connection (for x 8)

_HITACHI
346 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - HM62A912818128 Series
• BLOCK DIAGRAM

LWE
LeE

A1S
A15
A14
A13
A12
A11
Am
As

:.::

-'
t)

I/0s
1/07

Cl

(I)

128 K x 9 (8)

Ul

SRAM

a::

A7
As
A5

u::

1/05

Q..

1/04

::::;
::!:

«

~

W
CIl

~

W
CIl

1/03

Z

"0

A4

I/0s

w

I

As

a::

1102
1/01

A3
A2

1100

A1
Ao

(NC)

:.::

-'
t)

0>

OE

(I)

a::

(I)

CE

..c

WE

en

LLOE

e

:.::
-'

t)

• FUNCTION TABLE
Truth Table
CE

OE

WE

Din

CLK

SRAMMode

Next Cycle DOll!

Ref. Cycle

H

X

X

X
X
X

".

Not Selected

High-Z

Read <;:ycle

".

Not Selected

High-Z

".

Read

Read Data

Read Cycle

Hjgh-Z
High-Z

Write <;:ycle

L

H

H

L

L

L

H

H
L

Data

".

Write

L

L

L

Data

".

Write

Note

Registers

I
I

Mode
Load

Register Output

".

LorH

I

Hold

Not Changed

CLK

Register Input

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 347

HM62A912818128 Series - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any pin relative to Vss
Operating Temperature Range
Storage Temperature Range (with Bias)
Storage Temperature

Symbol
VT

Value
-0.510 +7.0

Unit
V

Topr
Tstg (bias)

oto +70
-10 to +85

Tstg

-55 to +125

°c
°c
°c

• RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to +70°C)
Item

Min.
4.75

Typ
5.0

V/H

0
2.2

VIL

-0.5

Symbol
Vee
VSS

Supply Voltage
Input Voltage
Note: I. VIL mm =-2.0V for pulse wIdth::;; 10 ns.

Unit
V

0

Max.
5.25
0

-

6.0

V

-

0.8

V

Note

V
I

• DC CHARACTERISTICS (Ta =0 to +70°C, VCC =5V ± 5%, VSS =OV)
Item
Input Leakage Current
Output Leakage Current
Average Operating
Current
Standby Power
Supply Current
Output Low Voltage
Output High Voltage

Symbol
IIul
IILOI

Min.

Typ

-

-

Max.
2
10

Unit

-

Ieel

-

-

150

rnA

Test Conditions
Vee =5.25V, Yin =VSS to Vee
Dou! High-Z State VVO = VSS to Vee
Min. Cycle, CE = VIL
Duty: 100%, IVO = 0 rnA

ISB

-

-

50

rnA

Power Standby CLK ::;; VIL.
Min. Cycle

ISBI

-

-

5

rnA

Power Standby CLK::;; 0.2VVIL,
Yin, ::;;0.2V orVin;;:: Vee-O.2V

VOL
VOH

-

-

0.4

2.4

V
V

IOL=8.0mA
IOH=-4mA

-

J.lA
/!A

• CAPACITANCE (Ta = 25°C, f= 1.0 MHz)
Item
Input Capacitance
Input/Output Capacitance

Symbol
Cin
CVo

Min

Typ

-

-

Max
6

Unit
pF

Test Conditions
Vin=OV

-

-

10

pF

Vl/O=OV

Note: 1. This p~~meter is sa.rnp!ed and not! 00% tested .

•

HITACHI

348 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 2 A 9 1 2 8 / 8 1 2 8 Series

• AC CHARACTERISTICS (T a = 0 to +70°C, V CC = 5V ± 5%)

Test Conditions
•
•
•
•

Input pulse levels: VSS to 3.0V
Input rise and fall times: 2ns
Input and output timing reference levels: 1.SV
Output Load: See figure
+5V

+5V
480Q

480Q

Output o---- CS 2

Chip Select

WE

Write Enable

Vee

Power Supply (+ 5V)

Vss
NC

Non-connection

Ground

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 365

HB66A2568A Series - - - - - - - - - - - - - - - - - - - - - - - • BLOCK DIAGRAM

CS1
WE
ADD

CS2

T

II- -

I

1

ADD WE CS

ADD WE CS

M1

MO
DO
00

Din
Dout

D1
01

Din
Dout

II

II
ADD WE CS

ADD WE CS

M2

M3

Din
Dout

D2

02

D3
03

Din
Dout

...

II

II
ADD WE CS

ADD

M4
D4

Din
Dout

Q4

D5
05

II

ADD WE CS

06

-

ADD WE CS

M6

M7

Din
Dout

Vee

Vss

CS

Din
Dout

II
D6

WE
M5

Din
Dout

D7
07

: :::=

CO-C7 :

I

MO-M7

C.O.22IJF

•

MO~M7

•

: HM6207HJP

HITACHI

366 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HB66A2568A Series
• ABSOLUTE MAXIMUM RATINGS

Parameter
Voltage on Any Pin Relative to VSS
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Storage Temperature Range Under Bias
I.

NOTE:

Yin

min. = -2.5V for pulse width

:$

Symbol

Value

Yin
Pr
Top,
T stg
Tbias

-0.5(1) to +7.0

Unit
V
W

8.0
Oto +70
-55 to + 125
-10 to +85

'c
'c
'c

IOns.

• TRUTH TABLE

CS" CS2
H
L
L

WE
X
H
L

Mode
Not Selected
Read
Write

Vee Current
ISB,IsB ,

Dout Pin
High-Z

lee
lee

Dout
High-Z

Ref. Cycle
Read Cycle
Write Cycle

X means don't care.

NOTE:

• ELECTRICAL CHARACTERISTICS
• Recommended DC Operating Conditions (T. = 0 to 70'C)

Parameter

Symbol
Vee
Vss
VIH
VIL

Supply Voltage
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
NOTE:

I. VIL mla.

= -2.0V for pulse width

:$

= 0 to 70'C, Vee = 5V

± 10%, Vss

Test Condition
Vee = Max., Yin = Vss to Vee
CS" CS2 = VIH, VI/O = Vss to Vee

Operating Power Supply Current

Ice

CS" CS2 = VIL, 1110 = 0mA
Min. Cycle, Duty = 100%

Standby Power Supply Current

ISB

CS" CS 2 = VIH Min. Cycle

Standby Power Supply Current (I)

ISB '

Output High Voltage
Output Low Voltage

VOH
VOL

I. Typical limits are at Vee

Max.
5.5
0.0
6.0
0.8

-

ILl
ILO

NOTE:

Symbol

Typ.
5.0
0.0

Unit
V
V
V
V

IOns.

• DC ELECTRICAL CHARACTERISTICS (T.

Parameter
Input Leakage Current
Output Leakage Current

Min.
4.5
0.0
2.2
-0.5(1)

Min.
-10
-10

Typ.(l)

-

Max.
10
10

Unit
p.A
p.A

-

480

960

rnA

160

320

rnA

-

0.16

16

rnA

2.4
-

-

-

-

0.4

V
V

CS" CS2 = ~ Vee -0.2V
OV :S Yin :S 0.2V or
Yin ~ Vee -0.2V
IOH
IOL

= -4mA
= 8rnA

= OV)

-

= 5.0V, T. = +25°C and specified loading.

• CAPACITANCE (T. = 25'C, f = IMHz)(l)

Parameter
Input Capacitance (Address, WE)
Input Capacitance (CS)
Input Capacitance (Data in)
Output Capacitance (Data out)
NOTE:

Symbol
CII
CI2
CI3
Co

Test Conditions

Min.

Yin = OV
Yin = OV
Yin = OV
YOU! = OV

-

-

Max.
70
45
12
16

Unit
pF
pF
pF
pF

I. This parameter is sampled and not 100% tested .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 367

HB66A2568A Series - - - - - - - - - - - - - - - - - - - - - - - - - - • AC CHARACTERISTICS (T.

= O°C to 70°C, Vcc = 5V

• Test Conditions
• Input Pulse Levels: Vss to 3.0V
• Input and Output Timing Reference Levels: 1.5V

± 10%, unless otherwise noted.)

• Input Rise and Fall Times: 5ns
• Output Load: See Figures

+5V

+5V

Dout

4800

Dout

2550

2550

4800
5 pF *

Output Load B
(for tHZ , tLZ , twz & low)

Output Load A
·Including scope and jig capacitance.

• Read Cycle
Symbol

Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output in Low-Z
Chip Deselection to Output in High-Z
Chip Selection to Power Up Time
Chip Deselection to Power Down Time
NOTE:

tRC
tAA
tACS
toH
tLZ(l)
tHZ(l)
tpu
tpD

HB66A2568A-25
Min.
Max.
25
25
25
5
5
0
12
0
15

HB66A2568A-35
Min.
Max.
35
35
35
5
5
0
20
0
25
-

Unit

I. Transition is measured ± 200mV from steady state voltage with Load (B)
This parameter is sampled and not 100 % tested .

•

HITACHI

368 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

ns
ns
ns
ns
ns
ns
ns
ns

- - - - - - - - - - - - - - - - - - - - - - - - - - HB66A2568A Series
• Timing Waveform of Read Cycle (1) (1) (2)

Address
tOH

tOH

Dout

Data Valid

• Timing Waveform of Read Cycle (2) (1) (3)

RC

cs

i~

"'.!I\.
tACS

tHZ

tLZ

....

KXX) V

Dout

~

Vccsupply
current

tpD

.........................................
Icc

~

/

SO%~'"

It'SO%

Iss

NOTES:

I. WE is high for read cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.

•

HITACHI

Hitachi America, ltd.• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 369

HB66A2568A Series - - - - - - - - - - - - - - - - - - - - - - - - - - • Write Cycle

Parameter

Symbol

Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enabled to Output in High-Z
Output Active from End of Write
NOTE:

twc
lew
tAW
tAS
twp
tWR
tow
tOH
twz(l)
tow(2)

HB66A2568A-25
Min.
Max.
25
20
20
0
20
3
15
0
0
8
0
-

HB66A2568A-35
Min.
Max.
35
30
30
0
30
3
20
0
10
0
0
-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

I. Transition is measured ,., 200mV from high impedance voltage with Load (8).
This parameter is sampled and not 100% tested .

•

HITACHI

370 Hitachi America, Ltd .• Hitachi Plm. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HB66A2568A Series
• Timing Waveform of Write Cycle (1) (WE Controlled)

Address
tew

CS1,2
twp'l

WE

Din

Dout

High Impedance

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300 371

HB66A2568A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Timing Waveform of Write Cycle (2)

(CS Controlled)

twc
Address
tew

CS1,2
twp·1

WE
tow

Din
Dout

NOTES:

Data in valid
High Impedance '3

I. A write occurs during the overlap of a low CS and a low WE.
2. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
3. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output
buffers remain in a high impedance state.
4. Doul is the same phase of write data of this write cycle, if tWR is long enough .

•

HITACHI

372 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300

Section 4
MOS Pseudo Static RAM

.HITACHI®

HM66266B Series
32768-word X 8-bit High Speed Pseudo Static RAM
•
•
•

FEATURES
Single 5V (±10%)
High Speed
Access Time
CE Access Time . . . . . . . . . . . . . . . loo/120/150/2oons
Address Access Time ............... 50/60/75/100ns
(in Static Column Mode)
Cycle Time
Random ReadlWrite Cycle Time .... 160/190/235/310ns
Static Column Mode Cycle Time ...... 55/65/80/105n5
• Low Power
175mW typo Active.
• All inputs and outputs TTL compatible
• Static Column Mode Capability
• Non Multiplexed Address
• 256 Refresh Cycles (4ms)
• Refresh Functions
Address Refresh
Automatic Refresh
Self Refresh

HM6S2S6BP Series

HM6S2S6BFP Series

(FP-28DA)

• PIN ARRANGEMENT
•

ORDERING INFORMATION
Type No.
HM65256BP-10
HM65256BP-12
HM65256BP- I5
HM65256BP-20
HM65256BLP-10
HM65256BLP-12
HM65256BLP- I5
HM65256BLP-20
HM65256BFP-lOT
HM65256BFP-I2T
HM65256BFP- I5T
HM65256BFP-20T
HM65256BLFP-lOT
HM65256BLFP-12T
HM65256BLFP-I5T
HM65256BLFP-20T

Access Time
lOOns
1200s
I50ns
200ns
lOOns
120ns
I50ns
200ns
lOOns
1200s
I50ns
200ns
lOOns
1200s
I50ns
200ns

Package

600 mil 28 pin
Plastic DIP

28 pin
Plastic SOP

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 375

HM65256B S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• BLOCK DIAGRAM
Ao

o--ti:::f-i
Adch~u

Row

Latch

~cader

CotInol

v~o-~>4-~-~f7.I.:~;-l1~~~~~-~t_-.-_,
0. ..
I/O, O""·W>-+--f--I------l

a--~~~~~----------~

::==~=r:::.J

• TRUTH TABLE

•

mode

1/0 Pin

CE

OE

WE

L

L

H

LowZ

Read

L

x

L

High Z

Write

L

H

H

High Z

-

H

L

X

High Z

Refresh

H

H

x

High Z

Standby

ABSOLUTE MAXIMUM RATINGS

•

Rating

Symbol

Item

Unit

Terminal Voltage with Respect to V ss

VT

-1.0 to +7.0

V

Power Dissipation

PT

1.0

W

Operating Temperature

Topr

o to +70

·C

Storap:e Temperature

Tit,

-SSto+12S

·C

Storage Temperature Under Bias

Tbla,

-10 to +8S

·c

=0 to +70°C)

RECOMMENDED DC OPERATING CONDITIONS (Ta
Item
Supply Voltage

Input Voltage

Symbol

min.

typo

max.

unit

Vee
Vss
V/H
VIL

4.S

S.O

S.S

V

0

0

V

2.2

-

0

6.0

V

-O.S·l

-

0.8

V

Note) *1. VIL min = -3.0V for pulse width ~ IOns .

•

HITACHI

376 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 5 2 5 6 B Series

•

Parameter

Symbol

Operating Power
Supply Current

HM65256B Series HM65256BL Series

Test Conditions

min.

typo

1]/0 = OmA
teye::;: min.

-

35

ISBI

CE = VIH, OE = VIH

-

I

2

-

ISB2

CE> VCC-0.2V, OE> VCC-0.2V

-

-

-

-

ICCI

Standby Power
Supply Current

max. min.

max.

35

65

mA

I

2

mA

0.05

0.1

mA

-

65

Unit

typo

Operating Power Supply
ICC2
Current in Self Refresh Mode
ICC3

CE = V/H, OE = VIL

-

I

2

-

0.6

I

mA

CE? VCC-0.2V, OE~0.2V

-

-

-

-

50

100

I'A

Input Leakage
Current

1£1

VCC= 5.5V
Vin = VSS to VCC

-10

-

10

-10

-

10

I'A

1£0

OE= V/H
VI/O= Vssto Vec

-10

-

10

-10

-

10

I'A

VOL

10L = 2.1 mA

-

-

0.4

-

-

0.4

V

VOH

10H- -I mA

2.4

-

-

2.4

-

-

V

Output Leakage
Current
Output Voltage

•

=0 to +70°C , Vee =5V -+10%)

DC ELECTRICAL CHARACTERISTICS (Ta

CAPACITANCE
Item

Test Conditions

typo

max.

Unit

Input Capacitance

Symbol

Cin

Vin = OV

5

pF

Input/Output Capacitance

CI/O

VI/a = OV

-

7

pF

Note) This Parameter is sampled and not 100% tested.

•
•

=

AC CHARACTERISTICS (Ta = 0 to +70°C, Vee 5V ±10%)
AC Test Conditions
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . 2.4V, O.4V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . 5ns
Timing Measurement Level . . . . . . . . . . . . . . 2.2V,O.SV
Reference Level .
. ..... V OH = 2.0V, VOL = O.SV
Output Load . . . . . . . . . . . . . . . . . . 1 TTL and 100pF (including scope and jig)
Item

Symbol

HM65256B-IO
min.

max.

HM65256B-12
min.

Random Read or Write Cycle Time tRC
Static Column Mode Read or Write
tRSC
Cycle

160

-

190

55

-

65

Chip Enable Access Time

tCEA

Address Access Time

tAA

-

100

Output Enable Access Time

tOEA

-

Chip Disable to Output in High Z

tCHZ

40
25

Chip Enable to Output in Low Z

tCLZ

Output Enable to Output in Low Z

tOLZ

Output Disable to Output in High Z

tOHZ

Chip Enable Pulse Width

tCE
tp

Chip Enable Precharge Time

50

30
10

50
0

Address Set-up Time

tAS

Row Address Hold Time

tRAH

20

Column Address Hold Time

tCAH

100

Read Command Set-up Time
Read Command Hold Time

tRCS

0

tRCH

0

Output Enable Hold Time

tOHC

0

Output Enable to Chip Enable Delay
Time

tOCD

0

Outp~t

Hold Time from Column

Address

tOH

4m

-

-

5

-

Write Command Pulse Width

twp

25

Chip Enable to End of Write

tcw

100

Column Address Set-up Time

tASW

0

-

-

-

25

-

60
0
20
120
0
0

-

30

-

-

75
0
25
150
0
0

-

0

0

-

0

25
120
0

-

-

5
30
150
0

max.

40

30

150n

min.

105

60

0

5

~HITACHI

-

HM65256B-20
310

75

10

4m

150

35
25

-

-

120

-

120n

max.

80

50

10
25

min.
235

60

30

HM65256B-15

-

-

-

lOOn

-

max.

4m

10

-

-

100

-

30

-

-

ns

200

ns

100

ns

75

ns

35

ns
n.

ns

-

ns
35

200n

Unit

-

ns

4m

s

-

n.

-

ns

-

ns
ns

0

-

ns

0

-

ns

10

-

ns

0
200
0
0

-

ns
ns

-

ns
ns
ns
0
(to be contmued)

35

200

-

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 377

HM65256B S e r i e s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Symbol

Item
Column Address Hold Time after Write
Data Valid to End of Write
Data In Hold Time for Write
Output Active from End of Write
Write to Output in High Z
Transition Time (Rise and Fall)
Refresh Command Delay Time
Refresh Precharge Time
Refresh Command Pulse Width for
Au tomatic Refresh
Automatic Refresh Cycle Time
Refresh Command Pulse Width for Self
Refresh
Refresh Reset Time for Self Refresh
Refresh Period

IAHW
IDW
IDH
low
tWHZ
IT
IRFD
IFP

HM65256B-IO
min.
max.
0
20
0
5
25
3
50
50
30
-

min.

0
20
0
5

max.

-

-

25
50

3
60
30

-

HM65256B-15
min.
max.
0
25
0
5
30
3
50
75
30
-

HM65256B-20
Unit
min.
max.
0
ns
30
ns
0
ns
5
ns
35 ns
3
50 ns
100
ns
30
ns
-

-

80

10000

80

10000

80

10000

80

10000

ns

160

-

190

-

235

310

-

ns

10000

-

10000

-

10000

-

10000

-

ns

190

-

235

-

310

-

IFAP
IFC
IFAS

HM65256B-12

IFRS

160

tREF

-

4

-

4

-

4

-

4

ns
ms

Notes:
(I)

ICHZ,IOHZ and IWHZ are defined as the time at which the output achieves the open circuit conditions.

(2)

t CLZ,I OLZ and lOW are sampled under the condition of tT=5ns, and not 100% tested.

(3)
(4)
(5)

A write occurs during the overlap of a low CE and low WE.
If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high impedance state.
If input signals of opposite phase to the outputs are applied in write cycle, OE or WE must disable output buffers
prior to applying data to the device and data inputs must be floating prior to OE or WE turning on output buffers.
V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Also, transition times are meaSured between V IH and VIL'
An initial pause of I DOl's is required after power-up followed by a minimum of 8 initialization cycles .

(6)

(7)

•

TIMING WAVEFORMS

•

Read Cycle No.1 (CE controlled)
IHC

In:

CE----

Address~~~~ ~~~--,i r~~~~~~~~~~~~~~x_~~~~~~~~~7r~~,_
Ao-A,

Address
Ax - Al.l ---''-'''--><-.¥

1'--1+---------------------4 '(..;1L...l~1L...l~~"'-l"-.lJL..l~

leI./.

Dout------------------------------{

•

Valid
Data Out

HITACHI

378 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 5 2 5 6 B Series
•

Read Cycle No.2 (OE controlled)
IN(

CE----,j

Address

An-A; -L~~ ~++--~~~~~~~~~~~~~~~~~~~~~~~~~~

Address

A"-A14~~~J~_4~-------------------------------------------r--~~~~~~

leI./.

Dout----------------------------~

•

Valid

Data Out

Writ. Cycle No.1 (OE Clock)
CE-----,[

Address

An-A7

Address
All-All

WE---~---~ ~~~~~-------_tr_--

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 379

HM85258B
•

Series-----------------------------

Writ. Cycle No.2 19 1_ flxl

ICE

C'E----.l1

Address

A.-A .. ~~~~~----------------------------------------H_f~~~

OE---~~--------~-------_H-----IDW

Din--J------l-Mt========~
Dout _ _ _ _ _

...:..._..J~~~~~~~~~~--------------

• St.tlc Column Mode Reed Cvcle
IRe

CE _ _ _ _~
lAS

Address
A8-AU

r--------~le=-E---------1~='=P=~
'''AR

..u.tX;V'"~f__------....If.t_--""l'---.... "O£~ac\"o'/~

•

HITACHI

380 Hitachi America, Ltd. • Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 6 5 2 5 6 B Series
• Static Column Mode W~ite Cycle

CE - - - - I I

Address

'nI~J\..l~4=::::=========~;:::==::::===1_k

A8-A14~~~~-~---~------------_i}-------~r~~~

Din

•

--H+C~P-~~

Autom.tic R.fr. Cycl.

CE-----------J

~--~tR~F~D--~~------~tf~"C~------~~--~t~FC~--.
tf"P

•

tFAP

Self Refrllh Cycl.

_HITACHI
Hitachi America, Ltd.· Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 381

HM658128 Series
131,072-Word x 8-Bit High Speed Psuedo Static Ram

The HM658128 Series has been converted to the HM658128A Series .

•

HITACHI

382 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM658128A S e r i e s - - - - - - - - - 131,072-Word x a-Bit High Speed Pseudo Static RAM
• FEATURES
• Single 5V (±10%)
• High speed
Access time
CE access time: 80/100/120 ns
Cycle time
Random read/write cycle time: 130/160/190 ns
• Low power
250 mW typo Active
350 IlW typo Standby (L-version, LL-version)
• All inputs and outputs TIL compatible
• Package
32-pin dual-in-line plastic package
32-pin SOP package
32-pin TSOP package
• Non multiplexed address
• 512 refresh cycles (8ms)
• Refresh functions
LP/LLP-version: Address refresh, automatic
refresh, self refresh
DP-version: Address refresh, automatic refresh

(FP-32D)

(TFP-32D)

• ORDERING INFORMATION
Type No.
HM658128ALP-8L
HM658128ALP-IOL
HM658128ALP-12L
HM658 I 28ALP-8
HM658128ALP-1O
HM658128ALP-12
HM658128ADP-8
HM658128ADP-IO
HM658128ADP-12
HM658128ALFP-8L
HM658128ALFP-IOL
HM658 128ALFP-I 2L
HM658128ALFP-8
HM658128ALFP-IO
HM658128ALFP-12
HM658128ADFP-8
HM658128ADFP-IO
HM658128ADFP-12
HM658128ALT-8L
HM658128ALT-IOL
HM658128ALT-12L
HM658128ALT-8
HM658128ALT-IO
HM658128ALT-12
HM658128ADT-8
HM658128ADT-IO
HM658128ADT-12
HM658128ALR-8L
HM658128ALR-IOL
HM658128ALR-12L
HM658128ALR-8
HM658128ALR-IO
HM658128ALR-12
HM658128ADR-8
HM658128ADR-1O
HM658128ADR-12

Access Time
80 ns
100 ns
120 ns
80 ns
100 ns
120 ns
80 ns
lOOns
120 ns
80 ns
100 ns
120 ns
80 ns
100 ns
120 ns
80 ns
100 ns
120 ns
80 ns
100 ns
120 ns
80 ns
100 ns
120 ns
80 ns
100 ns
120ns
80 ns
100 ns
120 ns
80 ns
lOOns
120 ns
80 ns
100 ns
120 ns

Package

• PIN DESCRIPTION

600-mil
32-Pin
Plastic DIP Series
(DP-32)

525-mil
32-Pin
Plastic SOP Series
(FP-32D)

Pin Name

Function

AO-A16
1/00-1/0 7
RFSH
CE
OE
WE
CS
Vee
VSS

Address
Input/Output
Refresh
Chip Enable
Output Enable
Write Enable
Chip Select
Power Supply
Ground

8mm x 20mm
32-Pin
Plastic TOSP Series
(TFP-32D)

8mmx 20mm
32-Pin
Plastic TSOP Series
(TFP-32DR)

$

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 383

HM658128ASeries -------------------------------------------------------• PIN ARRANGEMENT

HM658128AP/AFP Series

HM658128AT Series

vee

RESH

A1S

~'0

32
31

DE
fup

30

CE

4

29

1/07

5

28

1I0e

6
7

1/04

A16
A14
A12

WE

a

27
26
25

A7

A13

9

24

A6

As

m

es

11
12
13
14
15 ______________________

Ag
A11
OE

AS

A4
A3
A2
A1

A10

AO

1/07
1/06
1/05
1/04
1/03

~

~1~6

(Top View)

HM658128AR Series
A4
~

A6
A7
A12
A14

o

32

~

31

A2

30

A,

29
28
27

Ao
1/00

I\lL

26
25

lID,
1/02
Vss

Vee

24
23
22

1/03
1/04
1/05

RFSH

A15

cs
WE
A'3
As
Ag
A11

21
20

1/06
1/07

18

CE
fu.o

'9

17

1/03
VSS
~

liD,
1100

AIJ
A1

A2.

~17~~

(Top View)

eE

1/00
1/01
1/02
VSS

22
21
20
19
18

1105

OE

(Top View)

.HITACHI
384 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589·8300

---------------------------------------------------------HM658128ASeries
• BLOCK DIAGRAM

r-

Ao~rI
•

II

• II
•

II

•

II
II
I

•

Address
Latch
Control

Row
Decoder

8~ '--

MEMORY MATRIX
(512 X 256) X 8

A

1/00
1/07

0-

'---

Input

"'1.h
'C..

I
-:0-

I

Column Decoder
Address Latch Control

L,~

- -.--; -~- -; -l./~

rAg

Refresh
Control
CE

CS

OE
WE

rA16
.....,

I

I

Timing Pulse Generator
Read Write Control

•

e::::--

Column I/O

I,Control
Data

1:L.

J

r

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 385

HM658128A Series
Pin Functions

Refresh

CE:

Chip Enable (Input)
_
CE is a basic clock. RAM is active when CE
is low, and is on standby when CE is high.

There are three refresh modes: address refresh, automatic refresh, and self refresh.

Ao-AI6:

Address Inputs (Input)
Ao-AS is a row address and A9-AI6 is a
column address. The entire address Ao-AI6
iE fetched into RAM by the falling edge of
CEo

WE:

Write Enable (Input)
_
RAM is in write mode when WE is low, and
is in read mode when WE is high. I/O data is
fetched into RAM by the rising edge of WE
or CE (earlier timing) and the data is written
into memory cells.

Data is refreshed by accessing all 5 I 2 row addresses
every 8 ms. A read is one method of accessing those
addresses. Each row address (each of the 5 I 2 addresses
AO-AS) must be reaQ.J!.t least once every 8 ms. In
address refresh mode, OE can remain high. In this case,
the I/O pins remain at high impedance, but the refresh is
done within RAM.

OE:

Output Enable (Input)
OE controls the output condition of the I/O
pins. The 1/0 pins are active when OE is low,
and are at high impedance when OE is high.

RFSH:

Refresh (Input)
__
RAM goes into refresh mode when RFSH
goes low in standby mode. (i.e., when CE is
high). There are two refresh modes
controlled by RFSH: automatic refresh and
self refresh.

CS:

Chip Select (Input)
RAM is active when CS is high. The CS
signal is fetched into RAM by the falling
edge of CE, and is held for one readlwrite
cycle.

(1) Address refresh

(2) Automatic refresh
Instead of address refresh, automatic refresh can be
used. RAM goes to automatic refresh mode if RFSH fall
while CE is high and it remains low for at least tFAP.
One automatic refresh cycle is executed by one low
pulse of RFSH. It is not necessary to input the refresh
address from outside since it is generated internally by
an on-chip address counter. 5 12 automatic refresh cycles
must be done every 8 ms.
(3) Self refr'esh
Self refresh mode is suitable for data retention by
battery. In standby mode, a self refresh starts automatically when RFSH stays low for more than 8 Its. Refresh
addresses are automatically specified by the on-chip
address counter, and the refresh period is determined by
the on-chip timer.
Automatic refresh and self refresh are distinguished
from each other by the width of the RFSH low pulse in
standby mode. If the RFSH low pulse is wider than 8 Its,
RAM enters self refresh mode; if the RFSH low pulse is
less than 8 Its, it is recognized as an automatic refresh
instruction.
Notes on Using the HM658128A
Since pseudo static RAM consists of dynamic circuits like DRAM, it is more noise-sensitive than conventional SRAM.

1/00-1/07: Input/Output (Input and Output)
These pins are data I/O pins.

(1) If a short CE pulse of a width less than tCE min is
applied to RAM, an in"omplete read occurs and stored

data may be destroyed. Make sure that CE low pulses of
less than tCE min are inhibited. Note that a IOns CE low
pulse may sometimes occur owing to the gate delay on
the board if the CE signal is generated by the decoding
of higher address signals on the board. Avoid these short
pulses.
(2) A short RFSH low pulse may cause an incomplete
refresh that will destroy data. Make sure that RFSH low
pulses of less than tFAP min are also inhibited.
(3) Start the HM658128A operating by executing at least
eight initial cycles (dummy cycles) at least 100 Its after
the power voltage reaches 4.5V-5.5V after power-on.

•

HITACHI

386 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------------HM~128ASeries

• FUNCTION TABLE

Note:

CE

CS at CE going Low

OE
L

l/OPin

H

RFSH
X

WE

L

H

Low-Z

Mode
Read

L

H

X

X

L

High-Z

Write

L

H

X

H

H

High-Z

L

L

X

X

X

High-Z

-

CS Standby

H

X

L

X

X

High-Z

Refresh

H

X

H

X

X

High-Z

Standby

I. X means don't care.

• ABSOLUTE MAXIMUM RATINGS
Item
Terminal Voltage with Respect to V SS

Symbol

Rating

VT

-1.0 to +7.0

Unit
V

PT

1.0

W

Topr

o to +70

°C

Storage Temperature

Tstg

-55 to +125

°C

Storage Temperature Under Bias

Tbias

-10 to +85

°C

Power Dissipation
Operating Temperature

• RECOMMENDED DC OPERATING CONDITIONS (T a = 0 to +70DC)
Item
Supply Voltage
Input Voltage

Symbol

Min.

Typ

Max.

Vcc

4.5

5.0

5.5

VSS
VIH

0

-

0
6.0

V

2.2

VIL

-D.5

-

0.8

V

0

Unit
V
V

Note: I. VIL min = -3.0 V for pulse width 10 ns.

• DC CHARACTERISTICS (Ta = ODe to +70 De, vCC = 5V ± 10%)
Parameter
Operating Power
Supply Current
Standby Power
Supply Current

Operating Power
Supply Current in
Self Refresh Mode

Symbol

Min.

Typ

Max.

Unit

Test Conditions

ICC!

-

50

85

rnA

11/0 = 0, leyc = 130 ns

ISSI

-

I

2

rnA

CE = VIH, RFSH = VIH

ISB2

-

100
70

200
100

J.1A

CE;:" VCC -D.2V,
RFSH ~ VCC -0.2V

ICC2

-

I

2

rnA

CE = VIH, RFSH = VIL

ICC3

-

100
70

200
100

J.1A

CE;:" VCC -D.2V,
RFSH $;-D.2V

Input Leakage
Current

ILl

-10

-

to

J.1A

Vcc= 5.5V,
Yin = VSS to Vce

Output Leakage
Current

ILO

-10

-

10

J.1A

OE=VIH,
VI/O = VSS to Vce

VOL

-

-

0.4

V

IOL = 2.1 rnA

VOH

2.4

-

-

V

IOH=-1 rnA

Output Voltage

•

Note

L-version

LL-version

L-version
LL-version
L-version

LL-version

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 387

HM658128ASeries - - - - - - - - - - - - - - - - - - - - - - - - - - - • CAPACITANCE
Item
Input Capacitance

Symbol

Typ

-

Cin

Input/Output Capacitance

CI/O
Note: 1. This parameter is sampled and not 100% tested.

Max

Unit

8

pF

Vin=OV

10

pF

VI/O=OV

• AC CHARACTERISTICS (T a = 0 to 70°C, VCC = 5V ± 10%)
AC Test Conditions
• Input pulse levels: 2.4V, O.4V
• Reference level: VOH
• Input rise and fall times: 5 ns
• Timing measurement level: 2.2V, 0.8V

Test Conditions

=2.0V, VOL =0.8V

• Output load: 1 TTL and 100 pF

•

HITACHI

388 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM658128A Series

Item

Symbol

Random Read or Write Cycle Time
Random Read Modify Write Cycle Time
Chip Enable Access Time
Output Enable Access Time
Chip Disable to Output in High-Z

tRC
tRWC

HM658128A-8
Min
130
190

Max

HM658128A-10
Max

HM658128A-I2

-

Min
160

-

220

-

80
30

-

100
30

-

-

Min
190
260

tCEA
tOEA

-

tCHZ

0
20

30

0

30

-

20

-

0
20

-

25

-

25

-

Chip Enable to Output in Low-Z

tCLZ

Output Disable to Output in High-Z
Output Enable to Output in Low-Z
Chip Enable Pulse Width

tOHZ
tOLZ
tCE

-

0
80 ns

-

10l's

-

0
100 ns

-

101'8

-

0
120 ns

Max
-

Unit
ns
ns

-

120
40

ns

35

ns

1,2

-

ns

30

ns

2
1,2

-

ns

2

ns

101'8

50

-

ns

-

-

-

ns

Address Hold Time
Read Command Set-up Time

tAH

30

-

0
30

60
0

-

tAS

40
0

-

Address Set-up Time

-

35

-

ns

tRCS

-

0

-

0

-

ns

Read Command Hold Time
RFSH Hold Time

tRCH
tRHC

0
0
15

0
15

-

-

ns

-

0
15

-

ns

Chip Select Set-up Time

0
30

0

-

ns

-

0
30

-

Chip Select Hold Time
Write Command Pulse Width

tcss
tCSH
twp

-

-

35

-

ns

30

-

30

-

-

ns

Chip Enable to End of Write
Data In to End of Write

tcw
tow

-

100
25

-

35
120

-

0

-

30
0

-

ns
ns
ns

5

-

5

Chip Enable Precharge Time

tp

Data In Hold Time for Write

tOH

80
25
0

Output Active from End of Write
Write to Output in High-Z

tow

5

Transition Time (Rise and Fall)

tWHZ
tT

Refresh Command Delay Time
Refresh Precharge Time

tRFO
tFP

Refresh Command Pulse Width
Refresh Command Pulse Width
for Automatic Refresh

tRP

-

-

25

3
40
40

50

3

-

50
40

-

81'S

tFAP

80 ns

Automatic Refresh Cycle Time

tFC

130

Refresh Command Pulse Width
for Self Refresh

81ls
-

-

-

-

-

ns

25

-

30

ns

50

3
60
40

50

ns

-

ns

-

ns

-

81'S

80ns

81ls

160

-

-

80ns

81ls

190

-

ns

tFAS

8

-

8

-

8

-

Ils

tRFS

130

-

160

-

190

-

ns

Refresh Period

tREF

-

Notes:

-

8

-

2
1,2

81ls

Refresh Reset Time from Self Refresh

8

Note

8

ms

512
cycle

I. tCHZ, tOHZ, and tWHZ define the time at which the output achieves the open circuit conditions under the condition of tT =5 ns
and not 100% tested.
2. tCHZ, tCLZ, tOHZ, tOLZ, tWHZ. and tow are sampled under the condition oftT = 5 ns and not 100% tested.
3. A write occurs during the overlap of a low CE and low WE. Write end is defined at the earlier of WE going high or CE going high.
4. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high impedance state.
5. During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied.
6. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between
VIH andVIL.
7. An initial pause of 1001's is required after power-up followed by a minimum of 8 initialization cycles.
8. 512 cycles of burst refresh or distributed automatic refresh must be executed within 151ls atier self refresh, in order to meet the
retresh specification of 8 ms and 512 cycle .

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 389

HM~128ASeries -------------------------------------------------------• READ CYCLE

CE

..
..

CS

Address
(AO-A16)

..

WE

OE

RFSH

..

telz
Valid Data Out

Dout

.HITACHI
390 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

---------------------------------------------------------HM658128ASeries
• WRITE CYCLE (OE Clock)

CE

CS

Address
(Ao-A16)
..

twp

..

WE

OE

RFSH

Din

Dout

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589·8300 391

HM658128ASeries -------------------------------------------------------• WRITE CYCLE (OE Low Fix)

..
CE

--------i

tess

1_ _

------------~te~E-----_~J;~=::::::~tp

tesH

CS

Address
(AO-A16)

WE

OE

RFSH

Din

Dout

_HITACHI
392 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM658128A Series

• READ-MODIFY-WRITE CYCLE

...c-------

tRe

~~-------

- - -----.--

CE

cs

Address
(AO-A1S)

WE

OE

tDW

Valid Data In

Din

Dout

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 393

HM658128A Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • AUTO REFRESH CYCLE

CE

RFSH

• SELF REFRESH CYCLE

• CS STANDBY MODE

..
CE
tcss

tCSH

CS

.HITACHI
394 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM658512 Series
524,288-Word x 8-Bit High Speed Pseudo Static RAM
Features
• Single 5 V (± 10%)
• High speed
Access time
CE access time ...................8011001120 ns
Cycle time
Random read/write cycle time ....... 130/160/190 ns
• Low power
Active:
Standby:

250 mW (typ.)
200 p.W (typ.)

• All inputs and outputs TIL compatible
• Package
32-pin dual-in·line plastic package
32·pin SOP package

(FP-32D)

• Non multiplexed address
• 2048 refresh cycles (32 ms)
• Refresh functions
ULULV·version .....................Address refresh
Automatic refresh
Self refresh
D·version .......................... Address refresh
Automatic refresh

• ORDERING INFORMATION
Type No.

Access Time

HM658512LP-8
HM658512LP-10
HM658512LP-12

80 ns
100 ns
120 ns

HM658512DP-8
HM658512Dp·10
HM658512DP-12

80 ns
100 ns
120 ns

HM658512LP-8L
HM658512LP-IOL
HM658512LP-12L

80 ns
100 ns
120 ns

HM658512LP-8LV
HM658512LP-IOLV
HM658512LP-12LV

80 ns
100 ns
120 ns

HM658512LFP-8
HM658512LFP-10
HM658512LFP-12

80 ns
100 ns
120 ns

HM658512DFP-8
HM658512DFP-10
HM658512DFP-12

80 ns
100 ns
120 ns

HM658512LFP-8L
HM658512LFP-IOL
HM658512LFP-12L

80 ns
100 ns
120 ns

HM658512LFP-8LV
HM658512LFP-IOLV
HM658512LFP-12LV

80 ns
100 ns
120 ns

• PIN ARRANGEMENT
A,e

Vee

A,e

A,s

A'4

A'7

A'2
A7

WE
A'3

Ae

Ae

As
A4

As

A3

A"
OEIRFSH

A2
A,

CE

A,o

1/07
110e
1/05
1/04
1/03

Ao

Package

1100
1/0,
1/02
Vss
(Top View)

600 mil
32 pin
Plastic DIP
(DP-32)

• PIN DESCRIPTION
Pin Name
Ao-AIB

Function
Address

1I0o-I/~

Input/Output

CE

Chip Enable

OE/RFSH

Output Enable/Refresh

WE

Write Enable

Vee

Power Supply

V ••

Ground

32 pin
Plastic SOP
(FP-32D)

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 395

HM658512 Series - - - - - - - - - - - - - - - - - - - - - - - - - - -

• BLOCK DIAGRAM

AO
Address
Latch

Row
Decoder

Control

A1 0 o--~:!:jl

Mllmory Matrix
(2048x256)x8

I

1/00 o--r-D+--+~~
V07 o-r-·I-r::>4--I---l---1

Pin Function.

Refresh

~: Chip Enable (Input)

There are Ihree refresh modes: address refresh, automalic refresh, and
self refresh.

CE is Lbasic clock. RAM is active when CE is low, and is on standby
when CE is high.

ArAII: Address Inputs (Input)

Ao-A 10 is a row address and A II-A II is a column address. The enlire
address Ao-AII is fetched into RAM by the falling edge of CE.

WE: Write EilabJe (Input)
RAM is in write mode when WE is low, and is in read mode when WE
is higt.. 1/0 d,iitl il!i fetched inio RAM: by the rising edge oi WE or l:t:
(earlier timing) and the data is written into memory cells.

0IJii'SiI: Output EnabielRefresh (Input)
This pin has lwo functions. Basically il works as OE when CE is low,
and as iFsii \llhen Cii is high (in stand.,.!?l mode). After a read or write
cycle finishes, refresh does notBlart ifCE goes high while OEIRFSH is
held lOw. In order to start a refresh in standby mode, OiiJRFSH musl go
high to reset lhe refresh circuits of the RAM. After the refresh circuits
are reset, the refresh stans when OiiJiFsii goes low.
IIOrllo,: Input/Output (Inputs lind Outputs)

These pins are data 110 pins.

•

(1) Address refresh
Data is refreshed by accessing all 2048 row addresses every 32 ms. A
read is one method of accessing those addresses. Bach row address
(2048 addresses of Ao~) musl be read alleul once every 32 MS. In
address refresh mode, OEIRFSH can remain high. In this cllse,the 110
pins remain at high impedance, but the refresh is done within RAM.
(2) Automatic refresh

Instead of address ~frGih, autoilNi,i, refresh 'au be used. RAM guc::~ w
automatic refresh mode if OEIRFSH falls while CE is high and it
remains low fur al ~~One automatic refresh cycle is executed by
one low pulse of OEIRFSH. It is not necessary to input the refresh
address from outside since it is generated internally by an on-chip
address counter. 2048 automatic refresh cycles must be done every
32 MS.
(3) Self refresh
Self refresh mode is suitable fur data retention by battery. In standby
mode, a self refresh starts automatically when OEIRFSH stays low fur
more than 8 JAIl. Refresh addresses are automatically specified by the
on-chip address counter, and the refresh period is determined by the
on-chip timer.

HITACHI

396 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM658512 Series
on the board if the CE signal is generated by the decoding of higher
address signals on the board. Avoid these short pulses.

Automatic refresh and self refresh are distinguished from each other by
the width of the OE/RFSH low pulse in standby mode. If the OE/RFSH
low pulse is wider than 8 /,s, RAM changes into self refresh mode; if
the OE/RFSH low pulse is less than 8 /'S, it is recognized as an
automatic refresh instruction.

(2) OE/RFSH works as refresh control in stand\ly mode. A short OEI
RFSH low pulse may cause an incomplete refresh that will destroy data.
Make sure that OE/RFSH low pulses of less than tPAP min. are also
inhibited.

Notes on Using the HM658512
(3) IoHc and IocD are the timing specs which distinguish the OE
function of OE/RFSH from the RFSH function. The IoHc and IocD
specs must be strictly maintained.

Since pseudo static RAM consists of dynamic circuits like DRAM, it is
more noise-sensitive than conventional SRAM.

(4) Start the HM658512 operating by executing at least eight initial
cycles (dummy cycles) at least 100 /,S after the power voltage reaches
4.5V -5.5V after power-on.

If a short CE pulse of a width less than icE min. is applied to
RAM, an incomplete read occurs and stored data may be destroyed.
Make sure that CE low pulses of less than tCE min. are inhibited. Note
that a 10 ns CE low pulse may sometimes occur owing to the gate delay
(I)

• FUNCTION TABLE

NOTE:

Mode

CE

OE/RFSH

WE

110 Pin

L

L

H

Low-Z

Read

L

X

L

High-Z

Write

L

H

H

High-Z

-

H

L

X

High-Z

Refresh

H

H

X

High-Z

Standby

I. X means don't care.

• ABSOLUTE MAXIMUM RATINGS
Symbol

Rating

Thrminal Voltage with Respect to Vss

VT

-1.0 to +7.0

V

Power Dissipation

PT

1.0

W

Item

Unit

Operating Temperature

Top,

Oto+70

·C

Storage Thmperature

Tsig

-55 to +125

·C

Storage Temperature Under Bias

Tbias

-10 to +85

·C

• RECOMMENDED DC OPERATING CONDITIONS (TA
Item
Supply Voltage

Input Voltage
NorES:

= O·C to

+ 70°C)

Symbol

Min.

Typ.

Max.

Vcc

4.5

5.0

5.5

Unit
V

Vss

0

0

0

V

V IH

2.4

-

6.0

V

VIL

-1.0'1

-

0.8

V

I. VIL min. = -3.0V for pulse width 30 ns.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 397

HM658512 Series - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ __

• DC CHARACTERISTICS (TA
Parameter

= O·C to +70·C, Vee = 5V

:i: 10%)

Symbol

Min.

Typ.

Max.

Unit

Icc I

-

-

75

rnA

1"0 = 0, Icyc = min.

IS81

-

I

2

rnA

CE = VIH , OE/RFSH = VIR, VIN 2: OV

20

200
100*2

"A

CE 2: Vcc -O.2V
OE/RFSH 2: Vcc -O.2V V'N 2: OV

Operating Power Supply Current
Standby Power Supply Current

lest Conditions

ISB2

-

ICC2

-

I

2

rnA

CE = VIH , OE/RFSH = VIL , VIN 2: OV

ICC3

-

70"'
40*2

200*'
100*2

,.A

CE 2: Vcc -O.2V
OE/RFsH :s 0.2V VIR. VIN 2: OV

Input Leakage Current

III

-10

Output Leakage Current

11.0

-10

Operating Power Supply
Current in Self Refresh Mnde

Output Voltage

NOTES:

-

10

,.A

Vcc = 5.5V, VIN = Vss to ¥cc

10

"A

OE = VIH, V"o = Vss to Vee

VOL

-

-

004

V

10L = 2.1 rnA

VOH

204

-

-

V

10H = -I rnA

I. Only for L-VersIOn.
2. Only for LLlLV-Version.

• CAPACITANCE
Symbol

Typ.

Max.

Unit

Input Capacitance

Item

Cin

S

pF

¥in = OV

Input/Output Capacitance

CliO

-

10

pF

¥1I0 = OV

NOTE:

Test Conditions

I. This parameter is sampled and not 100% tested.

• AC CHARACTERISTICS (TA

= 0 to 70·C, Vee = 5V

± 10%)

Test Conditions
Input pulse levels:
Input rise and fall times:
Timing measurement level:
Reference level:
Output load:

2AV,OAV
5 ns

2.2V,0.SV
VOH = 2.0V, VOL = O.SV
I TTL and 100 pF

.HITACHI
398 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM658512 Series
• AC CHARACTERISTICS (TA

= 0 to 70°C, Vee = 5V

Item

± 10%)
HM658512-8

HM658512-IO

HM658512-12

Min.

Max.

Min.

Max.

Min.

Symbol

Unit
Max.

tRC

130

-

160

-

190

-

Chip Enable Access Time

teEA

-

80

-

100

-

120

ns

Read-Modify-Write Cycle Time

tRWC

180

-

220

-

260

-

ns

Random Read Qr Write Cycle Time

Note

ns

Output Enable Access Time

toEA

-

30

-

40

-

50

ns

Chip Disable to Output in High-Z

teHz

0

25

0

25

0

30

ns

I

Chip Enable to Output in Low-Z

teLZ

20

-

20

-

20

-

ns

2

Output Disable to Output in High-Z

toHz

-

25

-

25

-

30

ns

I

Output Enable to Output in Low-Z

tOLZ

0

-

0

-

0

-

ns

2

Chip Enable Pulse Width

teE

80 ns

10l's

100 ns

10l's

120 ns

Chip Enable Pre-Charge Time

tp

40

-

50

-

60

-

ns

Address Setup Time

tAS

0

-

0

-

0

ns

Address Hold Time

tAH

20

-

25

-

30

-

Read Command Setup Time

tRCS

0

-

0

-

0

-

ns

tRCH

0

-

0

-

0

-

ns

Read Command Hold Time

10l's

ns

Write Command Pulse Width

twp

25

-

30

-

35

-

ns

Chip Enable to End of Write

tcw

80

100

120

ns

Chip Enable to Output Enable Delay Time

toco

0

-

0

-

Output Enaole Hold Time

toHC

15

-

15

-

15

-

Data in to End of Write

tow

20

-

25

-

30

-

ns

Data in Hold Time for Write

tOH

0

-

0

-

0

-

ns

Output Active From End of Write

tow

5

-

5

-

5

-

ns

2

tWHZ

-

20

-

25

-

30

ns

I

Transition Time (Rise and Fall)

tT

3

50

3

50

3

50

ns

Refresh Command Delay Time

!RFO

40

-

50

-

60

-

ns

tFP

40

-

40

-

40

-

ns

81'S

80 ns

81'S

80 ns

81'S

Write to Output in High-Z

Refresh Precharge Time

0

ns
ns

tFAP

80 ns

Automatic Refresh Cycle Time

tFe

130

-

160

-

190

-

ns

Refresh Command Pulse Width for Self Refresh

tFAS

8

-

8

-

8

-

I's

Refresh Reset Time From Self Refresh

tRFS

600

-

600

-

600

-

ns

Refresh Period

tREF

-

32

-

32

--

32

ms

Refresh Command Pulse Width for Automatic Refresh

NOTES:

2048 cycle

I. tcHZ. tOHZ and IWHZ are defined as the time at which the output achieves the open circuit coruhtlOn.
2. tCLZ. tOlZ and tow are sampled under the condition of tT "" 5 ns and not 100% tested.

CE and low WE.
CE low transition occurs simultaneously wilh or latter from the WE low transition. the output buffers remain in high impedance state.
S. In write cycle, DE or WE must disable output buffers prior to applying data to the device and at the end of write cycle data inputs must be Uuated prior to 5E or WE
3. A write occurs during the overlap of low

4. If the

turning on output buffeTS.
6. Transition time tT is measured between VIH (min.) and VIL (max.).
7. After power-up. pause for more than 100 JlS and ellecute at least 8 initialization cycles, preferably as 8 refresh cycles.

8. 2048 cycles of burst refresh or distributed automatic refresh must be executed within 15

itS

after self refresh, in order to meet the refresh

specification of 32 ms and 2048 cycle.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 399

HM658512 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORMS
• Read Cycle
teE

Address
AO to A18

WE

teEA
tOEA

~~ ~tOLZ

I__________________~~~~ ______
i(
Valid

_ _____________________

Dout

7"

• Write Cycle (1) (OE High)
_~ __ ~9._

teE

Address
AO to A18

WE

Din

~I

teLZ

~----------------~k~x~x-x~x~x-x-x~

Dout

• Write Cycle (2) (OE Low)
_ _ _ _ _ _ _ _ _ _ _ _ tRe

%

Address
AOtoA18

tp

::L

~~---------------------------------" ---~-~~I'---p::::=±=::;~
tew

Valid

Din
tWHZ

Dout

 Not Valid
$

HITACHI
400 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM658512 Series
• Automatic Refresh Cycle

CE

OEIRFSH

• Self Refresh Cycle

_

..t'

CE

OORFSH

'2?2:

::-k

tRFD

--../;
f..;"--l:'

/f

t FP

--

tFAS
_o--------'!:!:!"-----------

.....____________

• Read-Modify-Wrlte Cycle

_____~III·_.__--------~t~C~E-----------__-1

CE

Address
AD 10 AlB

tcw

tCEA
OEIRFSH
tOHC --f-l-+Din

tCLZ
Doul

• Low VCC Data Retention Characteristics 111=0 to 70°C. This characteristic is guaranteed only for LV-version.
Symbol

Item
Vee for data retention
Self refresh current

Min.

VDR

Typ.

4.0

IeeDR

Max.

Unit

5.5

V

50

p.A

Vee=4.0V
CE ;:: Vee -0.2 V
OE/RFSH :5 0.2 V
Vin;:: OV

100

p.A

Vee = 5.5 V
CE ;:: Vee -0.2 V
OE/RFSH :5 0.2 V
Vin;:: OV

Refresh setup time

tFS

0

ns

Operation recovery time

tFR

5

ms

•

Test Conditions

HITACHI

Hitachi America, ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 401

HM658512 Series - - - - - - - - - - - - - - - - - - - - - - - - - - • Low Vee Data Retention Timing Waveform

Data retention mode

Vee
4.5V

--------------V

BE
2.4V
O.BV

OORFSH
2.4V
O.BV

BE ~ Vee -0.2 V

---t7-...
OORFSH < 0.2 V
(Automatic Refresh)

Notes: 1. tR (rise time), tp (fall time) of power supply voltage must be smaller than 0.05 V/ms.
2. Keep CE ~ Vee -0.2 V during data retention mode.
3. Regarding tRPOo tpp, tpAS and tRPS' refer to AC characteristics .

•

HITACHI

402 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

Section 5
ECLRAM

.HITACHI®

HM10494 Series
16384-word x 4-blt Fully Decoded Random Access Memory
Description
The HM10494 is ECl 10K compatible, 16384-word by 4-bits
readlwrite random access memory developed for high speed systems
such as scratch pads and controllbuffer storage.

Features
•
•
•
•
•
•

16384-word x 4-bit organization
Fully compatible with 10K ECl level
Address access time: 10/12 ns (max)
Write pulse width:
6 ns (min)
low power dissipation: 800 mW (typ)
Output obtainable by wired-OR (open emitter)

Ordering Information
Type No.
HMI0494-1O
HMI0494-12
HMI0494F-1O
HMI0494F-12

Access Time
IOns
12 ns
10 ns
12 ns

(DG-28N)

Package
400 mil 28 pin Cerdip
(DG-28N)
28 pin Ceramic Flat
(FG-28D)

Function Table
Input
WE
x
L
L

Cs
H
L
L
L

Output

Din

x

L
L
L
Dout" I

L
H

x

H

Notes: x; Irrelevant

Mode
Not Selected
Write "0"
Write"l"
Read

"\; Read Out Noninvert

Pin Arrangement

Block Diagram
A7

AS

A9

AIO

All

AI2

OIl

AI3

DI2
DI3

NC

DI4

AI3

AO

DOl

AI2

Al

002

All

A2

AIO
Memory Cell Array
16384words X4bits

Vcc.o

v••

A4

D03

A9

AS

004

AS

A6

AO

A7

Al

A6

A2

AS

A3

A4

DII

001 DI2

D02 DI3

003 DI4

•

004

(Top View)

HITACHI

404 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM10494 Series

Absolute Maximum Ratings (Ta = 25°C)
Item
Supply Voltage
Input Voltage
Output Current
Storage Temperature
Storage Temperature
Note:

Symbol
VIlIl to Vee
Yin
lout
Tstg
Tstg (Bias)"1

Rating
+0.5 to-7.0
+0.5 toVIlIl
-30
-65 to +150
-55 to +125

Unit
V
V
mA
°C
°C

·1; Under Bias

Electrical Characteristics

DC Characteristics (VIlIl = -5.2V, RL = son to -2.0 V, Ta = 0 to +75°C. air flow exceeding 2 m/sec)
Item
Symbol Min(B) Typ Max (A) Unit
Test Conditions
-1000
-840
VOH
-810
-960
-900
-720
mV Yin = VillA or Vn.a
Output Voltage
-1870
-1665
VOL
-1850
-1650
-1830
-1625
-1020
VOHC
-980
-920
mV Yin = Villa or Vn.A
Output Threshold Voltage
-1645
VOLe
-1630
-1605
Guaranteed Input Voltage
-1145
-840
VIII
-1105
-810
High for All Inputs
-1045
-720
Input Voltage
mV
Guaranteed Input Voltage
-1870
-1490
Low for All Inputs'
Vn.
-1850
-1475
-1830
-1450
Vin= VillA
1111
220
Input Current
0.5
170
CS
In.
I1A Yin = Vn.8
-50
Others
All Inputs and Outputs
-180
Supply Current
mA Open
IIlIl
-180

O°C
+25°C
+75°C
O°C
+25°C
+75°C
O°C
+25°C
+75°C
O°C
+25°C
+75°C
O·C
+25°C
+75°C
O°C
+25°C
+75°C
oto +75°C
Oto +75°C
Ta=O°C
Ta=75°C

AC Characteristics (VBB = -5.2 V ± 5%, Ta = 0 to +75°C, air flow exceeding 2 m/sec)

Read Mode
Item

Symbol

Chip Select Access Time
Chip Select Recovery Time
Address Access Time

lAcs
IRes

lAA

HMI0494-10
Min Typ Max
6
6
10

•

HMI0494-12
Min Typ Max
8
8
12

Unit

Test Conditions

ns
ns
ns

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 405

HM10494 Serl••
WrHeMod.
Symbol

Item
Write Pulse Width
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Disable Time
Write Recovery Time

tw
twSD
lWHD

twSA
twHA
twscs
lWHCs

tws
twR

HMI0494-10
Min Typ Max
6
2
2
2
2
2
2
6
12

HMI0494-12
Min Typ Max
8
2
2
2
2
2
2
8
14

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

Test Conditions
twSA = twSA min

tw= tw min

Rise/Fail Time
Item
Output Rise Time
Output Fall Time

Symbol

Min

Typ
2
2

Max

Unit
ns
ns

Test Conditions

Min

Typ
3
5

Max

Unit
EF
pF

Test Conditions

tr

If

capacHance
Item
InEut Cl!Eacitance
Output Capacitance

Symbol
Cin
Cout

.HITACHI
406 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 1 0 4 9 4 Series

Test Circuit and Waveforms
Input Pulse

Loading Condition
Test Circuit
VccCGND)

81.7V

Dout

:

I

I ~ I

M.U.T.

H

t. ==

O.OlpF

b

82.0V

'f == 2.Ons typo

(Includes probe
and jil capacitance)

Read Mode

Address
I..

Dout

Dout

Write Mode

IV

SO%..Jf\

\ /

SO%)K

Address

----

----

Dm

/"\.

----,
50%)V\

----- ------

\ F----

"-- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _1 I

\.

'WHD

....

---- - - - - Dout

twscs

I.,.

~ \.50%

j

V
t'INA

I.

~
•

I."",

/

~O%

I ..

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 407

HM10490 Series
65536-Words x 1-Blt Fully Decoded Random Access Memory
• DESCRIPTION
The HM10490 is ECl 10K compatible, 65536-words by 1-bit read/
write random access memory developed for high speed syStems
such as scratch pads and control/butter storage.
•
•
•
•
•
•
•

FEATURES
65536 x 1 Bit Organization
Fully Compatible with 10K ECl Level
Address Access Time ....................... 10/12ns (max.)
Write Pulse Width ............................6/8ns (min.)
low Power Dissipation .......................570mW (typ.)
Output Obtainable by Wired-OR (Open Emitter)

(DG-22N)

• PIN ARRANGEMENT

• ORDERING INFORMATION

IOns
12ns

HMI0490-10
HMI0490-12

Vee

Dout

Package

Ao

Din

300 mil 22 pin Cerdip
(DG-22N)

Al

CS

A2

WE

A3

A15

A4
As

A14

AS

A12

A7

All

As
VEE

Ala

Access Time

Type No.

• BLOCK DIAGRAM

A13

A9

...

(Top View)

~

• FUNCTION TABLE

Q)

A6
A7
As
A9
A10

Input

Memory Cell Array
65536 words x 1 bit

1

CS WE

"0

~

I

Aa~cA-sE

!

1,.._--+-________---.

8:l

Din

RfN Circuit

~

Output

Mode

Din

H

X

X

L

Not Selected

L

L

L

L

Write "0"

L

L

H

L

Write "I"

L

I H I X I Dou,· I

NOTES:

Read

X = Irrelevant;
• = Read out noninvert

Dout

•

HITACHI

408 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM10490 Series
• ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Item
Supply Voltage
Input Voltage
Output Current
Storage Temperature

•

Rating

Unit

+0.5 to 97.0

V
V
rnA
°C

+0.5 to VEE
930

lout
Tstg

965 to +150
955 to + 125

T st.rbias) *

Storage Temperature

NOTE:

Symbol
VEE to Vcc
Vin

°C

= Under bias.

• DC CHARACTERISTICS (VEE = 95.2V, RL = 500 to 92.0V, Ta = 0 to +75°C, air flow exceeding 2m/sec.)
Item

Symbol

Min. (8) Typ. Max.(A) Unit

Test Condition

-

9840
9810

-

91665

91020
9980
9920

-

-

-

-

91645

-

91630
91605

O°C
+25°C
+75°C
O°C

91145
91105
91045

-

9nO

91870

-

91490

+25°C
+75°C
o to +75°C

91850
91830

-

-

-

91475
91450
220
170

p.A

-

rnA

O°C
+25°C

91000
9960

+75°C
O°C

9900
91870

VOL

+25°C
+75°C
O°C

91850
91830

VOHC

+25°C
+75°C
O°C

VOH
Output Voltage

Vin = V IHA or V ILB

Output Threshold Voltage

Vin = V1HB or VILA

+25°C
+75°C

VOLC

VIH

Guaranteed Input Voltage
High for All Inputs

Input Voltage
VIL
IIH
Input Current
Supply Current

Guaranteed Input Voltage
Low for All Inputs
Vin = VIHA

I CS
I Others

IlL

Vin = VILB

lEE

All Inputs and Outputs Open

• AC CHARACTERISTICS (VEE = 95.2V

'*' 5%, Ta =

o to

0°C,75°C

-

-

950
9140

mV

91650
91625

-

0.5

+75°C

9nO

mV

9840
9810

-

-

mV

0 to +75°C, air flow exceeding 2m/sec.)

1. Read Mode
Item
Chip Select Access Time
Chip Select Recovery Time
Address Access Time

Symbol

Thst Condition

tAcS
tRcS
tAA

HMI0490-10
Min. Typ.
-

-

-

-

HMI0490-12

Max. Min. Typ.
6
6
-

10

-

-

Max.
8
8
12

Unit
ns
ns
ns

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 409

HM10490 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2. Write Mode

Item
Write Pulse Width
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Disable Time
Write Recovery Time

Symbol
tw
tWSD
tWHD
tWSA
tWHA
twscs
tWHCS
tws
tWR

lest Condition
twsA = tWSA min.

tw

= twmin.

Min. Typ. Max. Min. Typ. Max. Unit
6
8
- - ns
2
2
- ns
2
2
- ns
2
2
- - ns
2
2
- - ns
2
2
- - ns
2
2
- - ns
6
8
ns
- 12
14
ns
- -

3. Rise/Fail Time

Item
Output Rise Time
Output Fall Time

Symbol
t,
tf

Test Condition

Symbol
Cin
Cout

Test Condition

Min.

-

Typ.
2
2

Max.

Typ.
3
5

Max.

-

-

Unit
ns
ns

4. Capacitance

Item
Input Capacitance
Output Capacitance

Min.

-

-

Unit
pF
pF

• TEST CIRCUIT AND WAVEFORMS
1. loading Condition

2. Input Pulse

90.9V

Vee (GNO)

91.7V

M.U.T.

92.0V

•

HITACHI

410 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - HM10490 Series
3. Read Mode

~_50_~_D--~tAA------------

------------------~

Dout

4. Write Mode

Address
Din

----- -----

--50%)

,. - - - - - - - - -

I(

" r\.

,---------------------~
tWSD

tWSA

Dout

--_.

/

I\.
tw

tWHCS
tWHCS

------ ------

/

twscs

~50%

tWR

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 411

HM10500 Series

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Preliminary

262,144 Words x 1-Bit Fully Decoded Random Access Memory
• DESCRIPTION
HM 10500-15 is ECl 10K compatible, 262,144-words x 1-bit, readl
write random access memory developed for high speed systems
such as main memories for super computers.

• FEATURES
•
•
•
•
•
•

262,144-words x 1-bit Organization
Fully Compatible with 10K ECl level
Address Access Time .......................... 15ns (max.)
Write Pulse Width ............................. 10ns (min.)
low Power Dissipation .......................520mW (typ.)
Output Obtainable by Wired-OR (Open Emitter)

(DG-24V)

• PIN ARRANGEMENT

• ORDERING INFORMATION
Type No.

Access Time

Package

15ns

300 mil 24 pin
Cerdip (DG-24V)

HM10500-15

• FUNCTION TABLE
Input

Output

Mode

X

L

Not Selected

L

L

L

Write "0"

L

L

H

L

Write" I"

L

H

X

D uut "

Read

CS

WE

Din

H

X

L

NOTES:

(Top View)

X = Irrelevant

*I

= Read Out Noninvert

•

HITACHI

412 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - HM10500 Series
• BLOCK DIAGRAM

Ao
AI
I
I

I
I
I

,

MEMORY
CELL ARRAY
256 X 1024

A,

CS
WE
D,

A,A. ----- Au

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 413

HM10500 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Absolute Maximum Ratings (Ta=2S°C)
Item

Symbol

Rating

Unit

Supply Voltage

+0.5 to -7.0

Input Voltage

+0.5 to VEE

V

-30

mA

Output Current
Storage Temperature
Storage Temperature

Tstg (Bias)'

V

-65 to+150

·C

-55 to+125

·C

• Under Bias

Electrical Characteristics
DC Characteristics (VEE=-S.2V, RL =son to -2.0V, Ta=O to +7SoC, air flow exceeding 2m/sec)
Item

Symbol

VOH
Output Voltage
VOL

VOHC

min (B)

typ

mix (A)

O·C

-960

-810

+25·C

-900

-720

"OIL

-1650

+25·C

-1830

-1625

+75·C

-1020

O·C

-980

+25·C
+75·C

Supply Current

VlnmVIHB or VILA

O·C
+25·C

-1605

+7S·C

-1145

-840

-1105

-810

-1045

-720

-1870

-1490

--1850

-1475

-1830

-1450

O·C
Guaranteed Input Voltage
High for All Inputs

+2S·C
+75·C

mV

O·C
Guaranteed Input Voltage
Low for All Inputs

+2SoC

220

Vln-VIHA

o to +75·C

170

CS

+75·C

jJA

-50
-180

lEE

mV

-1630

0.5
IlL

O·C

-1850

IIH
Input Current

Vln-VIHA or V ILB

-1665

VOLC

Input Voltage

+75·C
mV

-1870

-1645

V IH

Test Condition

-B40

-920

Output Threshold
Voltage

Unit

-1000

mA

-180

Others

Vln-VILB

All Inputs and Outputs Open,
Test Pin 12

o to +75·C
Ta-O·C
Ta-75·C

AC Characteristics (VEE=-S.2V±S%, Ta=O to +7SoC, air flow exceeding 2m/sec)
Read Mode
Item

Symbol

Chip Select Access Time
Chip Select Recovery Time
Address Access Time

typ

mix

Unit

t ACS

15

ns

t RCS

10

ns

tAA

15

ns

min

$

Test Condition

HITACHI

414 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

HM10500 Series

Write Mode
Item

Symbol

min

Unit

TtIIt Condition

Write Pulse Width

tw

10

n.

tWSA=2ns

Deta Setup Time

tWSD

2

ns

typ

mex

Data Hold Time

tWHD

3

ns

Address Setup Time

tWSA

2

ns

Address Hold Time

tWHA

3

ns

Chip Select Setup Time

twscs

Chip Select Hold Time
Write Disable Time

twHCS
tws

2
3

ns
ns

Write Recovery Time

tWR

10

ns

18

ns

max

Unit

tw ·10ns

Rise/FaD Time
Item

Symbol

Output Rise Time

tr
tf

Output Fall Time

min

typ

2

ns

2

ns

Test Condition

Capacitance
Symbol

Itlm
Input Capacitance
Output Capacitance

min

typ

max

Unit

C'n

3

pF

Cout

5

pF

TtIIt Condition

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 41 5

HM10500 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Test Circuit and Wavefonns
Input Pulse

Loading Condition

Dou!

,

M.U.T.

,
I
! I, I

,.--,
O.OIJ.tF

1

R,""SOC

C, ",3()PF
(Include:>" probe
:.nd ji~ capacitancc)

-2.0V

Read Mode
Add""

~'-~

---I~

_ _ _ _ _ _ __
IAA

E

uo"' _ _ _ _ _ _
Write Mode
509;

Add~u

___

Uf"

1\

~

________________

5...);(

~_-J

509;

~J

509;

' -______________________J

-5~\l/

509;

,~----l------

---1---1-..11 '... . ______________ ...1 1

~:....---+II--+--

\

5096V

~09fi
t"'SA

'-_,_._J
509;

Dout

IWHA

t ..Hes

509;

t ..so

.HITACHI
416 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM100494 Series
16384-word x 4·blt Fully Decoded Random Access Memory
Description
The HM100494 is ECl 100K compatible, 16384-word by 4-bits
readfWrite rendom access memory developed for high speed systems
such as scratch pads and controllbuffer storage.

Features
•
•
"
•
"
"

16384-word x 4-bit organization
Fully compatible with 100K ECl level
Address access time: 10/12 ns (max)
Write pulse width:
6 ns (min)
low power dissipation: 650 mW (typ)
Output obtainable by wired-OR (open emitter)

Ordering Information
Type No.
HMl00494-IO
HMlOO494-12
HMl00494F-1O
HMl00494F-12

(DG-28N)

Access Time
IO ns
12 ns
10 ns
12 ns

Package
400 mil 28-pin Cerdip
(DG-28N)
28-pin Ceramic Flat
(FG-28D)

Function Table
Input
WE
x
L
L
H

CS
H
L
L
L

Din
x
L
H
x

Noles: x; Irrelevant

Output

Mode

L
L
L
Dout"J

Not Selected
Write ''0''
Write "I"
Read

*1; Read Out Noninvert

Pin Arrangement

Block Diagram
A7

AS

A9

AIO

All

AI2

AI3

AO
Al
A2

Memory Cell Array
16384words x 4bitl

A3
A4

DII

cs

012

WE

013

NC

014

AI3

DOl

AI2

D02

All

Vee

AIO

V"".

V..

D03

A9

D04

AS

AO

A7

Al

A6

A2

AS

A3

A4

AS
A6

DII

DOl 012

D02 013

003 014

•

D04

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 417

HM100494 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Absolute Maximum Ratings (Ta =25°C)
Symbol
VEE to Vee
Yin
lout
Tstg
Tstg (Bias)I'

Item
Supply Voltage
Input Voltage
Output Current
Storage Temperature
Storage Temperature
Note:

Rating
+0.5 to -7.0
+0.5 to VEE
-30
-65 to +150
-55 to +125

Unit
V
V
mA
DC
DC

*1: Under Bias

Electrical Characteristics
DC Characteristics (VEE = -4.5 V, RL = 500 to -2.0 V, Ta = 0 to +85 DC, air flow exceeding 2 m/sec)
Max (A) Unit
Item
Symbol Min (B)
Test Condition
Typ
VOH
mV
-1025
-955
-880
Output Voltage
Yin = VillA or Vn..B
mV
VOL
-1810
-1715
-1620
mV
VOile
-1035
Output Threshold Voltage
Yin = VnlB or Vn..A
VOLC
-1610
mV
Guaranteed Input Voltage
mV
VIII
-1165
-880
Input Voltage
High/Low for All Inputs
mV
Vn..
-1810
-1475
1111
220
~A
Yin =VnlA
CS
Input Current
0.5
170
In..
~A
Yin =Vn..B
-50
Others
Supply Current
All Inputs and Outputs Open
IEB
-180
mA

AC Characteristics (VEE = -4.5 V ± 5%, Ta = 0 to +85°C, air flow exceeding 2 m/sec)
Read Mode
Item

Symbol

Chip Select Access Time
Chip Select Recovery Time
Address Access Time

lAes
IRcs

tM

HMl00494-1O
Min Typ Max
6
6
10

HMl00494-12
Min Typ Max
8
8
12

HM I 00494-1 0
Min Typ Max
6
2
2
2
2
2
2
6
12

HM100494-l2
Min Typ Max
8
2
2
2
2
2
2
8
14

Unit

Test Condition

ns
ns
ns

Write Mode
Item
Write Pulse Width
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Disable Time
Write Recovery Time

Symbol
tw
twSD
twllD
twSA
twHA
twscs
twHCS
tws
twR

Unit
ns
ns

Test Condition
twSA = twSA min

ns

ns
ns
ns
ns
ns
ns

tw= twmin

• HITACHI
418 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM100494 Ser.e.

Rlee/F••• TIme
Item
Output Rise Time
Output PaD Time

Symbol

Min

Typ

Max

2
2

tl'

If

Unit

Test Condition

JIJ
JIJ

C8p8Cbnce
Item
Input CIpaCiIlftCc
Output CapacillftCc

Symbol
Cin
Cout

Min

Typ

Max

3
S

Uriit

Test Condition

pF
pF

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589-8300 419

HM100494 Series - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ __

Test Circuit and Wavefonns
loading Condition

Input Pulse

Test Circuit

V.C~ "----:tw--_--J ;~-tWHCS--Dout

..

------~-r-~-~-~-----t~W=sc~s~--~~~--~--~---J 50%
tws

•

i------~R_~ _ _

HITACHI

424 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM100500 Series

--------------Preliminary

282,144·Word )( 1·Blt Fully Decoded Random Acce•• Memory
• DESCRIPTION
The HM100S00CG·18 is ECL 100K compatible, 262,144-word )(
1-bit, read/write random access memory developed for high speed
systems such as main memories for super computers.
•
•
•
•
•
•
•

FEATURES
262,144-Word )( 1-Bit Organization
Fully Compatible with 100K ECL Level
Address Access Time .......................... 18ns (max.)
Write Pulse Width .............................10ns (min.)
Low Power Dissipation .......................SOOmW (typ.)
Output Obtainable by Wired·OR (Open Emitter)

(FO-24A)

• ORDERING INFORMATION
Type No.

Access Time

HM 100500-18

18ns

HM 100500cO-18

18ns

HMI00500F-18

18ns

Package
24 pin CERDIP
(DO-24V)
28 pin LCC
(CO-28B)
24 pin Ceramic Flat
(FO-24A)

(DO-24V)

• FUNCTION TABLE
CS
H
L
L
L
NOTES:

Input
WE
X
L
L
H

Din
X
L
H
X

Output

Mode

L
L
L

Not Selected
Write "0"
Write "I"
Read

Dout" I

(CO-2gB)

X = Irrelevant
"I = Read Out Noninvert

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 425

HM100500 Series - - - - - - - - - - - - - - - - - - - - - - - - -

BLOCK DIAGRAM

Ao
A1

(/'J
(/'Ja:
Ww
a: O
0
0 0
0

A7

MEMORY
CELL ARRAY
255 X 1024

Dout

"fw
xo
SENSE AMP
and RIW
CONTROL

CS
WE
D1

AS Ag - - - - - An

•

HITACHI

426 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM100500 Series

Pin Arrangement

---(FG-24A)

(DG-24V)

Vee

Doul

All

~
~

Din

\kc:
Dout

Ao

Al
A2
A3
A-t

24
23
22
21
20
19
18
17
16
15
14
13

12
3 " index
4
5
6
7
8
II
10
11
12

A15

Ao

Al.

Din
~

A13
A12
Au
A'0
VEE

WE
A17
A16
A,S

All

A14

Aa
A7

A7

As

As

A'3
A12

A9

All

As

VEE
(Top View)

A'0

(Top View)

(CG-28B)
'~

An.",

I'.". V, ... l"'f'r II.

I J: :1:: ': IZI&: :11: :1Ii;
L .. L .... .1 L.J L..J L.J

r."H

AI
AI
A3
A4

X::
:0

::it

(~~
1ft:

--.r.:-:.

::it

"'7
1\16

AS
AI
A7
AI

T"J
:f'::
-joi::
iC

::n

N•.

Dr

AI4

::i!

lr..1

(1-1

m

AIS

"'3

flr,lflflflfl
III' 121 114' '15' II.' tni

A' ..... V.n AI. All All

(Top View)

.HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 427

HM100S00 S.rl •• - - - - - - - - - - - - - - - - - - - - - - - - -

Absolute Maximum Ratings (Ta. 2S 0 C)
Symbol
Item

Note:

Unit
V
V
mA
·C
·C

Ratilll
+0.5 to-7.0
+0.5 to VEl
-30
-65 to +150
-55 to +125

VEl toVcc
Yin
lout
.Tltl
Tstl (Bias)'\

Supply Voltale
Input Voltale
Output Current
Storlie Temperature
Storlie Temperature
.1; UnderBill

Electrical Characteristics
DC Characterlatlca (VEl =-4.5 V, RL =50n to -2.0 V, Ta =0 to +85·C, air flow exceeding 2 m/sec)
Item

Symbol
VOH
VOL
VOHC

Min (8)
-1025
-1810
-1035

Typ
-955
-1715

Max (A)
-880
-1620

Unit
mV
Output Voltage
mV
mV
Output Threshold Voltage -..,:.V,:::.O:.:;LC:..-~=:..-----~:-:-:---=.:~mV
-1610
mV
-880
-1165
Input Voltage
-1475
mV
-1810
VIL
220
IIH
!LA
170
Input Current
0.5
IlL
!LA
-50
Supply Current
-160
mA
lEE

Test Conditions
Yin = VIHA or VILa
Yin = V~IB or VILA
Ouaranteed Input Voltage
HigM..ow for All Inputs
Yin = VIHA
Yin = VILB

Others

A.ll Inputs and Outputs Open

AC Characteristics (VEE ~ -4.5 V ± 5%, Ta =0 to +85°C, air flow exceeding 2 m/sec)
Read Mode

Item
Chip Select Access Time
Chip Select Recovery Time
Address Access Time

Symbol
tACS
tRCS
tAA

Min

Typ

CO-IS Max
IS
18
IS

F-IS Max
IS
10
IS

Unit
ns
ns
ns

Test Conditions

Symbol
tw
tWSD
tWHD
tWSA
tWHA
twscs
tWHCS
tws
tWR

Min
10
2
3
2
3
2
3

Typ

CO-18 Max

F-18 Max

Unit
ns

Test Conditions
twsA=2 ns

Write Mode
Item
Write Pulse Width
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Disable Time
Write Recovery Time

15
21

10
21

ns
ns
ns
ns
ns
ns
ns

tw=

10 ns

.HITAOHI
428 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brlsbanll, CA 94005·1819· (415) 589·8300

HM100500 Series

Rise/Fail Time

Item

Symbol

OulpUt Rise Time
OulpUt Fall Time

Min

Typ
2
2

Max

Unit
ns
ns

Test Conditions

Min

Typ
3
S

Max

Unit

Test Conditions

1r

If

capacitance

Item

Symbol
Cin
Cout

Input Capacitance
Output Capacitance

I!F
pF

Test Circuit and Wavefonns
Loading Condition

Input Pulse

V"'(CND)

Dout
M.U.T.

-1.7V

I

I

I

1'----

~

I I, I
,--,

R,-5OII

·-2.0V

C'a3OpF(iftc ......
probe and ii,
capac illnce)

Read Mode
Addro••

~~ _~I
......

..
_ _ _ __

Dout_>E

Write Mode

5096

Add

....
----

j

i\.
~\/

/

~i\.

"J'\.

---- -,

Din

~----

~\/
-; \

~

~-------------~~
I

\

--- ----Do.I

Inc.

~

5096

.-.--!!"- I "

I ...

V

/
I.

I ...
t."a

L}~
I ..

•

------ ----

I

/(

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 429

HM1 00514 Series - - - - - - - - - - P r e l i m i n a r y
262,144·worc::ls x 4·blt Fully Decoded Random Access Memory
• DESCRIPTION

The HM1 00514 is ECL 100k compatible, 262,144words by 4-blts read/write random access memory
developed for high speed systems such as scratch
pads and controVbuffer storage.
(PO-32D)

• FEATURES

•
•
•
•
•
•

262,144 x 4-bit organization
Fully compatible with 100k ECL level
Address access time: 15 ns (max.)
Write pulse width: 9 ns (min.)
Low power dissipation: 800 mW (typ.)
Output obtainable by wired-OR (open emitter)

• PIN ARRANGEMENT

HM 100514 Series

• BLOCK DIAGRAM

~4
~s
A'6
~7

~3
~2
A"
~o

010

58

Doo

Ag
0,3
D03

Vee

VEE

VEE

Vee

Do,

D02

0"
WE

As

0,2

Ao
A,
A2

A7

Ae
As

A3 ---""'_ _ _....r- A4
(Top View)

• PIN DESCRIPTION

$

Pin Name

Function

Ao-A17

Address Input

DJo-DI3

Data Input

Doo-D03

Data Output

WE

Write Enable

CS

Chip Select

Vee

Ground

VEE

Supply Voltage

HITACHI

430 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 1 0 0 5 1 4 Series
• TRUTH TABLE
Input
CS
H
L

Notes:

WE
X
L

Output

Mode

Din
X

L

L

L

Not Selected
Write "0"

L

L

H

L

Write "I"

L

H

X

Dout *

Read

Unit

X: Irrelevant
*: Read Out Noninvert

• ABSOLUTE MAXIMUM RATING (T a = 25°C)
Symbol

Rating

VEE to Vee

+0.5 to-7.0

V

Yin

+0.5 to VEE

V

lout

-30

rnA

Tstg
Tstg (bias)'

-65 to +150

°C

-55 to +125

°C

Item
Supply Voltage
Input Voltage
Output Current
Storage Temperature
Storage Temperature
Note:

I. Under bias (VEE = 6.0V min.)

• ELECTRICAL CHARACTERISTICS
• DC Characteristics (VEE = -4.5V, RL = 50n to -2.0V, TC = 0 to +85 o C)2
Item
Output Voltage
Output Threshold Voltage

Symbol

Min (B)

Typ

Max (A)

Unit

VOH

-1025

-955

-880

mV

VOL

-1810

-1715

-1620

mV

VOHC

-1035

mV

-1610

mV

Vin = VIHB or VILA

VIH

-1165

-

-880

mV

VIL

-1810

-1475

mV

-

-

220

0.5

-

170

-50

-

-

IlA
IlA
IlA

Vin = VILB (Others)

-180

-

-

rnA

All Outputs Open

IIH
Input Current
IlL
Supply Current

-

_.

-

VOLC
Input Voltage

-

Test Condition
Vin = VIHA or VILB

lEE

Guaranteed Input Voltage
High/Low for All Inputs
Vin =VIHA
Vin = VILB (CS)

• AC CHARACTERISTICS (VEE = -4.5V ± 5%, Tc = 0 to +85°C)2
• Read Mode
Max

Unit

Chip Select Access Time

Item

Symbol
tACS

-

-

10

ns

Chip Select Recovery Time

tRCS

-

-

10

ns

Address Access Time

tAA

-

-

15

ns

Min

Typ

Test Condition

_HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 431

HM100514Series - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

• Write Mode
Item
Write Pulse Width
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Disable Time

Symbol
tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS
twS
tWR

Write Recovery Time

Min
9
2
2
2
2
2
2

Typ

-

-

-

-

-

-

-

-

-

-

-

-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

Max

-

15
17

Test Condition
tWSA = tWSA min

tW=twmin

• Rise/Fall Time
Item
Output Rise Time
Output Fall Time

Symbol
tr
tf

Min

Symbol
Cin
COUT

Min

Typ

Max

-

I

-

-

I

-

Unit
ns
ns

Test Condition

Unit
pF
pF

Test Condition

• Capacitance
Item
Input Capacitance
Output Capacitance

-

-

Typ
3
5

Max
-

• TEST CIRCUIT AND WAVEFORMS
• Loading Condition

• Input Pulse

Test Circuit

Vce (GND)

r

I ....

T

I

~
O.01~F

T

/77

VEE

Dout

-1.7V

!'icc
-2.0V

tr=tf=2.0ns typ

RL=50n
C L=30pF
(Includes probe
and jig capacitance)

_HITACHI
432 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 1 0 0 5 1 4 Series
• Read Mode

Addreq~5_00_YO_
Dout---------~

__:_tA-A------

Dout

• Write Mode

WE

t wsD

I'\.

/

t WSA

Dout

tw

tWHA
twHCS

------ -----twscs
tws

•

tWR

1

50 %

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 433

HM1 0051 0 Series - - - - - - - - - - P r e l i m i n a r y
1,048,576-words x 1-Bit Random Access Memory
• DESCRIPTION
The Hitachi HM1 0051 0 is ECl 1OOk compatible,
1,048,576 words by 1 bit read/write random access
memory developed for high speed systems .
• FEATURES
•
•
•
•
•
•
•

(FG-28DS)

1 ,048,576-words x 1 bit organization
Fully compatible with 100k ECl level
0.8 11m Hi-SiCMOS process
Address access time: 15 ns (max.)
Write pulse width: 9 ns (min.)
low power dissipation: 700 mW (typ.)
Output obtainable by wired-OR (open emitter)

• PIN ARRANGEMENT
HMlOO510 Series

• ORDERING INFORMATION
Type No.

Access Time

Package

15 ns

28 pin Ceramic Flat
(30 mil Lead Pitch)
(FG-28DB)

HM100510F-15

A15
A16

A14

A17

A12

A 18

A11
A10
A9

A13

A19

CS
Vee

VEE

Vee
Do

VEE

• PIN DESCRIPTION

DI

Pin Name

Function

Ao--Al9

Address Input

01

Data Input

DO

Data Output

WE

Write Enable

CS

Chip Select

Vee

Ground

VEE

Supply Voltage

WE

As

Ao

A7

A1
A2

A6
A5

A3

~
(TopYiew)

• BLOCK DIAGRAM

A5
As
A7
Ao
A1
A2
A1S
A17
A18

Q;
>

8>::
Q)

-0

0

u

Memory Cell Array
104856 words x 1 bits

Q)

a

X

WE
CS

R/W Circuit
Do

.HITACHI
434 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 1 0 0 5 1 0 Series
• FUNCTION TABLE
Input

Output

Mode

CS
H
L

WE
Xl

Din
Xl

L

L

L

L

Not Selected
Write "0"

L

L
H

H
Xl

L

Write "I"

Dout 2

Read

Rating
+0.5 to -7.0

Unit

+0.5 to VEE
-30
--65 to +150

V
rnA
°C

-55 to +125

°C

L

Notes:

I. Irrelevant
2. Read Out Noninvert

• ABSOLUTE MAXIMUM RATING (Ta = 2S°C)
Symbol

Item
Supply Voltage

VEE to VCC

Input Voltage

Vin

Output Current
Storage Temperature .

lout
Tstg
T stg (bias) I

Storage Temperature
Note:

V

I. Under bias (YEE = --6.0V min.)

• ELECTRICAL CHARACTERISTICS
• DC Characteristics (VEE = -4.SV, RL = son to -2.0V, TC
Item
Output Yoltage
Output Threshold Voltage

Symbol

Min (B)

Typ

Max (A)

Unit

YOH

-1025

-955

-880

mY

YOL

-1810
-1035

-1715

-1620

mY

YOHC

Supply Current

mY

-1165

-

-880

mY

-1810

-

-1475

mY

IJA
IJA
IJA

IlL

-

-

220

0.5

-

170

-50

-

-

-180

lEE

tACS

Chip Select Recovery Time

tRCS
tAA

Test Condition
Yin

= VIHA or YILB

Vin

= VIHB or YILA

Guaranteed Input Yoltage
High/Low for All Inputs
Yin = YIHA
Yin

= YILB (CS)

rnA

Yin = VILB (Others)
All Outputs Open

Max

Unit

Test Condition

10

liS

10
15

liS

± S%, Tc =0 to +8S°C)

Symbol

Chip Select Access Time
Address Access Time

mY

-1610

YIL

• AC CHARACTERISTICS (VEE =-4.SV
• Read Mode
Item

-

-

YIH
IIH

Input Current

-

-

YOLC
Input Yoltage

= 0 to +8S°C)

Min

Typ

-

-

-

•

liS

HITACHI

Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300 435

HM100510 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Write Mode
Item
Write Pulse Width

Symbol

Min

tw

9
3
3
3
3
3
3

Data Setup Time
Data Hold
Address Setup Time

tWSD
tWHD

Address Hold Time

rwHA
twSCS
tws
tWR

Write Recovery Time

ns

tWSA = tWSA min

-

-

os

-

-

-

ns
ns

-

-

ns

-

-

-

-

ns
ns

-

-

15

ns

-

-

18

ns

tWHCS

Write Disable Time

Test Condition

-

Max

-

tWSA

Chip Select Setup Time
Chip Select Hold Time

Unit

-

Typ

tw=twmin

• Rise/Fall Time
Item

Symbol

Output Rise Time
Output Fall Time

Min

Typ

-

tf
tf

Max

Unit

1.5

-

ns

1.5

-

os

Test Condition

• Capacitance
Item

Symbol

Input Capacitance
Output Capacitance

Min

Typ

-

Cin
COUT

3
5

-

Max
-

Unit
pF

-

pF

Test Condition

• INPUT PULSE

• AC TEST CONDITION

Vee (GND)

Dout
Ir = If = 2.0 ns typo

M.U.T.

RL

CL

:J;..
-2.0V

RL= 50 Q
CL=30pF
(includes probe and
jig capacitance)

•

HITACHI

436 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

------------------------------HM100510Series
• TIMING WAVEFORM
• Read

50%

Dout

Dout

• Write

Add'M'
Din

2=
:::;u

t--__

50%>]< , , "

-_-1
,;-_'- -_-_-_-_-_-_-_-__

f~_

50%), , ______________________ ,

-tWHD

WE

~t~ '\.

/r--_----;-tW_H_A _ _

.--_~tw~_~.~~--t~W~HC~S~---~

tWSA
Dout

50%

-------------------~~

50%

twscs

~----~~~-----~.-~-~ '----+--~---j

tws

•

tWR

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra POint Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 437

HM101494 Series
16384-Words x 4-BII Fully Decoded Random Access Memory
• DESCRIPTION
The HM101494 is ECL 100K compatible, 16384-words by 4·bits
readlwrite random access memory developed for high speed sys·
tems such as scratch pads and control/buffer storage.
•
•
•
•
•
•
•

FEATURES
16384 x 4 Bit Organization
Fully Compatible with 100K ECL Level
Address Access Time ...................... .10/12ns (max.)
Write Pulse Width ........................... .6/8ns (min.)
Low Power Dissipation .......................750mW (typ.)
Output Obtainable by Wired·OR (Open Emitter)

(FG-28D)

• ORDERING INFORMATION
Type No.

Access Time

Package

HMI01494·1O
HMI01494·12

IOns
12ns

400 mil 28 pin Cerdip
(DG-28N)

HMI01494F-1O
HMI01494F-12

IOns
12ns

28 pin Ceramic Flat
(FG-28D)

(DG-28N)
• PIN ARRANGEMENT

• BLOCK DIAGRAM

011

CS

012
013

WE
N/C

014

A13

001

A12

002

All

Vee
VeeA

Al0

Vee

003

As

004

As

AD

A7

Al

As
A5

A2
Aa

A4
(Top View)

WE

I"\..J~=-.,......=--r--='"""T"--=':::----'

CS

~~~~==~==~~~

• FUNCTION TABLE
Input

Output

Mode

X

L

Not Selected

L

L

Write "0"

L

H

L

Write "I"

H

X

Dout *

Read

CS

WE

Din

H

X

L

L

L
L

NOTES:

X = Irrelevant;
* = Read out noninvert

.HITACHI
438 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - HM101494 Series

• ABSOLUTE MAXIMUM RATINGS (T. - 25·C)
Item

NOTE8:

Rating
+0.5 to 97.0
+0.5 to VEE
930
965 to +150
955 to +125

Symbol
VEE to Vee
Vln

Supply Voltage
Input Voltage
Output Current
Storage 'lemperature
Storage 'lemperature

Iout

Til.
TItRCblall(\)

Unit
V
V
mA
·C
·C

1. Under bl...

2. Ceramic flat ... Te, Cerdip ... Ta.

• ELECTRICAL CHARACTERISTICS
• DC Chiracterlltici (VEE - -5.2V, RL - 500 to -2.0V(2), T. - 0 to +8S·C, air flow exceeding 2m/sec.(2),
Te - 0 to +85·C)

Item
Output Voltage
Output Threshold Voltage
Input Voltage
Input Current
Supply Current

Symbol
VOH
VOL
VOHe
VOle
VIH
VIL
IIH

Min.(B)
9102S
91810
9103S

'lest Condition
Vin - VIHA or VILB
Vin .. VIHB or VILA

9116S
91810

Guaranteed Input Voltage
High/Low for All Inputs

IlL

= VIHA
Vin = VILB

lEE

All Inputs and Outputs Open

-

Vin

I CS
I Others

O.S
9S0
91SO

Typ.
99SS
91715

-

Max.(A)
9880
91620

91610
9880
9147S
220
170

-

Unit
mV
mV
mV
mV
mV
mV

t£A.
t£A.
mA

• AC Characteristics (VEE = -S.2V :i: S%(2), T. = 0 to +8S·C, air flow exceeding 2m1sec.(2),
Te = 0 to +8S°C)
1. Read Mode

Item
Chip Select Access Time
Chip Select Recovery Time
Address Access Time

Symbol

'lest Condition

tACS
IRCS
tAA

HM 101494-12
HMI01494-10
Unit
Min. Typ. Max. Min. Typ. Max.
8
ns
6
- - ns
6
8
- - - - 10 - - 12 ns

2. Write Mode

Item
Write Pulse Width
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Disable Time
Write Recovery Time

Symbol
tw
tWSD
tWHD
twsA
tWHA
IwscS
tWHcS
tws
tWR

Test Condition
tWSA

tw

=tWSA min.

=twmin.

HM 101494-10
HM 101494-12
Unit
Min. Typ. Max. Min. Typ. Max.
6
8
- - ns
- 2
2
- - - ns
2
2
ns
- 2
2
- - ns
2
2
- - - ns
2
2
- - - ns
2
2
- - ns
6
8
ns
- 14
ns
12
-

-

$

-

- - -

-

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589-8300 439

HM101494 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3. Rise/Fall Time
Item

Symbol

Output Rise Time
Output Fall Time

Test Condition

tr
tf

Min.

Typ.

-

2
2

Min.

-

Max.
-

Unit
ns

-

ns

Typ.

Max.

5
3
3

-

Unit
pF

-

pF
pF

4. Capacitance
Item

Symbol

Input Capacitance

C in

Output Capacitance

C out

Test Condition
WE, CS, OIl, DJ2
Others

-

• TEST CIRCUIT AND WAVEFORMS

2. Input Pulse

1. Loading Condition

OO.9V - - - - - - ~-------,.

Vee (GND)

01.7V

M.U.T.

O. 01IlF T

/77

V

EE

02.0V

3. Read Mode

~-50-o/c-o~~----------I...
-------------------~
iAA

Dout

•

HITACHI

440 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - HM101494 Serle.
4. Write Mod.

Address

... _Din

.. _.- .. --,

'~

~

tWSD '

Dout

._._-- ------

1-· - _••••••

"

50%-1 , _____________________ J

t\

/
tw

tWSA

-...

I\..

tWHCS
tWHCS

/

twscs

50%

tWR

•

HITACHI

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300 441

HM101490 Series
65536-Words x 1-Bit Fully Decoded Random Access Memory
• DESCRIPTION
The HM101490 is ECL 100K compatible, 65536-words by 1-bit
read/write random access memory developed for high speed systems such as scratch pads and control/buffer storage.
•
•
•
•
•
•
•

FEATURES
65536 x 1 Bit Organization
Fully Compatible with 100K ECL Level
Address Access Time ....................... 10/12ns (max.)
Write Pulse Width ............................6/8ns (min.)
Low Power Dissipation .......................570mW (typ.)
Output Obtainable by Wired-OR (Open Emitter)

(DG-22N)

• PIN ARRANGEMENT

• ORDERING INFORMATION
Type No.
HMIOI490-IO
HMIOI490-12

vee

Doul

Access Time

Package

Ao

Din

IOns
12ns

300 mil 22 pin Cerdip
(DG-22N)

AI

CS

• BLOCK DIAGRAM

A2

WE

A3

AI5

A4

A14

A5

A13

Ae

A12

A7

All

As
VEE

Al0
A9

As

A6
A7
As

Ag
A10

(Top View)
Memory Cell Array
65536 words x 4 bits

• FUNCTION TABLE
Input
CS

Output

Mode
Not Selected

WE Din

All

H

X

X

L

A13

L

L

L

L

~~ 8=lL--__;..;.RNJ...;..-gr-ir_c_uit_ _---'

. ..

NOTES:

DinlDout

.

Write "0"

......

!!

X = Irrelevant;
• = Read out noninvert

.HITACHI
442 Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

~

••

- - - - - - - - . - - - - - - - - - - - - - - - - - - - - - - - HM101490 Series
• ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Item

Symbol

Supply Voltage
Input Voltage
Output Current
Storage Temperature
Storage Temperature

Rating
+0.5 to 87.0
+0.5 to 83.0
830
865 to +150
855 to +125

VEE to Vcc
Vin
lout
Tstg
Tstg(under bias)

Unit
V
V
rnA
°C
°C

• ELECTRICAL CHARACTERISTICS
• DC Characteristics (VEE
Item
Output Voltage
Output Threshold Voltage
Input Voltage

Input Current
Supply Current

= -5.2V. RL = 50n to -2.0V. Ta = 0 to
Symbol
VOH
VOL
VOHC
VOLC
VIH
V1L
IIH

+85°C. air flow exceeding 2m/sec.)

Test Condition
Vin

= VIHA or VILB

Vin

= VIHB or VILA

Guaranteed Input Voltage
High/Low for All Inputs
Vin = V1HA

= VILB

I CS

IlL

Vin

lEE

All Inputs and Outputs Open

I Others

Min.(B)
81025
81810
81035

Typ.
8955
8l7l5

-

-

-

-

81165
81810

-

-

-

0.5
850
8140

-

81610
8880
81475
220
170

-

-

p.A

-

-

rnA

-

Max.(A)
8880
81620

Unit
mV
mV
mV
mV
mV
mV
p.A

• AC Characteristics (VEE = -5.2V ± 5%, T. = 0 to +85°C;air flow exceeding 2m/sec.)
1. Read Mode
Item
Chip Select Access Time
Chip Select Recovery Time
Address Access Time

Symbol

Test Condition

tACS
tRCS
tAA

HMIOI490-10
HM 101490-\2
Unit
Min. Typ. Max. Min. Typ. Max.
6
8
ns
6
ns
8
10
\2
ns
- -

2. Write Mode
Item
Write Pulse Width
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Disable Time
Write Recovery Time

Symbol
tw
tWSD
tWHD
tWSA
tWHA
twscs
tWHCS
tws
tWR

Test Condition
tWSA = tWSA min.

tw = tw min.

HMI0l490-10
HM 101490-\2
Unit
Min. Typ. Max. Min. Typ. Max.
6
8
ns
2
2
ns
2
2
ns
2
2
ns
- - 2
2
- ns
2
2
ns
2
2
- ns
6
8
ns
- \2
ns
14
-

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 443

HM101490 Series - - - - - - - - - - - - - - - - - - - - - - - - - - -

3. Rill/Fail Time
Item
Output Rise Time
Output Fall Time

Symbol
tr
tf

Test Condition

Symbol
Cin
COUI

Test Condition

Min.

Typ.
2
2

Max.

Min.

Typ.

Max.

-

3

-

-

Unit
ns
ns

4. Capacitance

Item
Input Capacitance
Output Capacitance

5

Unit
pF
pF

• TEST CIRCUIT AND WAVEFORMS
1. loading Condition

2. Input Pulse

90.9V- - - - -

Vee (GND)

-rr------__..

91.7V

M.U.T.

92.0V

3. Read Mode

__-M----------

~~

-t"U70

1M

----------------~

Dout

•

HITACHI

444 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300

· - - - - - - - - - - - - - - - - HM101490 Series

4. Write Mode

Address
Din

----- -----

··So%)

~

, .............••.•....
twso

Dout

/

\.
tw

twSA

~
~

,. - -- - - - -- -

...

I\.

tYt'HCS
tYt'HCS

------ ------

~

/

twscs

50%

tWR

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 445

HM1 01504 Series - - - - - - - - - - I P r e l i m i n a r y
65,536-Words x 4-Blt Random Access Memory
• DESCRIPTION

The Hitachi HM1 01504 is ECL 100k compatible,
65,536 words by 4 bits read/write random access
memory developed for high speed systems such as
cache and controllbuffer storage.
•
•
•
•
•
•
•
•

FEATURES
65,536-words x 4 bit organization
Fully compatible with 100k ECL level
0.8 IlITl Hi-BiCMOS process
Address access time: 10/12 ns (max.)
Write pulse width: 7/9 ns (min.)
Low power dissipation: 500 mW (typ.)
Output obtainable by wired-OR (open emitter)

• PIN ARRANGEMENT

HMlO1504 Series
NC
0 10
0 11
0 12

• ORDERING INFORMATION
Type No.

HMIOI504F-1O
HMI01504F-12

013
000

Cycle Time

Package

10 ns
12 ns

400 mil 32 pin
Plastic SOl (CP-32D)

• PIN DESCRIPTION

0 01

Vee
Veeo
002

Pin Name

Function

Ao-A1S

Address Input

Dl

;5
"i:::
OJ

"C

0
OJ

u

Cl

X

WE

CS

.HITACHI
454 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H M 1 0 1 5 1 4 Series

• FUNCTION TABLE
Input
CS
H
L
L
L
Notes:

WE
Xl
L
L
H

Din

Output

Mode

Xl

L
L
L

Not Selected
Write "0"
Write "I"
Read

L
H
Xl

Dout 2

I. Irrelevant

2. Read Out Noninverl

• ABSOLUTE MAXIMUM RATING (Ta = 2S°C)
Item
Supply Voltage
Input Voltage
Output Current
Storage Temperature
Storage Temperature
Note:

Symbol
VEEtoVCC
Yin
lout
Tstg
Tstg (bias) I

Rating
+0.5 to-7.0
+0.5 to VEE
-30
-65 to +150
-55 to +125

Unit
V
V
rnA

°c
°c

I. Under bias (VEE = -Q.OV min.)

• ELECTRICAL CHARACTERISTICS

• DC Characteristics (VEE = -S.2V, RL = son to -2.0V, TC = 0 to +8S°C)
Item
Output Voltage

Min (B)

Symbol
VOH
VOL

Output Threshold Voltage
Input Voltage

VOHC
VOLC
VIH

-1165

VIL

-1810

Supply Current

0.5
-50
-200

ilL
lEE

Max (A)
-880
-1620

-

-

IlH
Input Current

Typ
-955
-1715

-1025
-1810
-1035

-

Unit
mV
mV

-1610

mV
mV

-880

mV

-1475

mV
j.lA

220
170

-

Test Condition
Yin = VIHA or VILB
Yin = VIHB or VILA
Guaranteed Input Voltage
High/Low for All Inputs

j.lA
j.lA
rnA

Vin=VIHA
Yin = VILB (CS)
Yin = VILB (OJhers)
All Outputs Open

Test Condition

• AC CHARACTERISTICS (VEE =-S.2V ± 5%, Tc = 0 to +85°C)
• Read Mode
Item

Symbol

Chip Select Access Time
Chip Select Recovery Time
Address Access Time

Min

-

tACS
tRCS
tAA

-

$

Typ

Max

Unit

-

10
10
15

ns
ns
ns

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300 455

HM101514 Series

• Write Mode
Item
Write Pulse Width
Data Setup Time
Data Hold
Address Setup Time
Address Hold Time
Chip Select Setup Time

Symbol

Min

Unit

Test Condition

tw

9

-

-

ns

tWSA = tWSA min

tWSD
tWHD
tWSA

3
3

-

-

-

-

3

-

-

ns
ns
ns

tw=twmin

3
3

-

-

ns

-

-

ns

-

-

-

-

15
18

tWHA
twSCS

Chip Select Hold Time

3

tWHCS
tws
tWR

Write Disable Time
Write Recovery Time

Typ

Max

ns
ns
ns

• Rise/Fall Time
Item
Output Rise Time

Symbol
tr

Min

-

Typ
1.5

Output Fall Time

If

-

1.5

-

Unit
ns

-

ns

Max

Test Condition

• Capacitance
Item
Input Capacitance

Symbol
Cin

Min

-

Typ
3

Output Capacitance

COUT

-

5

• AC TEST CONDITION

Max

-

Unit
pF
pF

Test Condition

• INPUT PULSE

Test Circuit

-0.9V-~----'
, 80%

VCC(GNO)

,

,

:

:

,

I

-1.7V

Doul

......, tr

,

tf ....~.

20%

M.U.T.

tr = tf = 2.0ns typ
0.Q1 ~F,J;..

VEE

-2.0V

RL=50n
CL=3OpF
(Includes probe and jig capacitance

•

HITACHI

456 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - H M 1 0 1 5 1 4 Series
• TIMING WAVEFORM
• Read

Dout

• Write

~

1
,.____l __;-________ .

Ad"'" ~_~?L_.
Din

50%',

,----------------------, '---T--~---l

WE
tWSD

Dout

........... -----_ ...

I\. 50%

/
tw

tWSA

tWHA
tWHCS

twscs
tws

tWR

1

50 %

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589-8300 457

HM101510 Series - - - - - - - - - - P r e l i m i n a r y
1,048,576-words x 1-Bit Random Access Memory
• DESCRIPTION
The Hitachi HM101510 is ECl 100k compatible,
1,048,576 words by 1 bit read/write random access
memory developed for high speed systems .

• FEATURES
•
•
•
•
•
•
•

1,048,576-words x 1 bit organization
Fully compatible with 100k ECl level
0.8 11m Hi-BiCMOS process
Address access time: 15 ns (max.)
Write pulse width: 9 ns (min.)
low power dissipation: 700 mW (typ.)
Output obtainable by wired-OR (open emitter)

• PIN ARRANGEMENT

HM101510 Series

A1S
A16
A17

• ORDERING INFORMATION
Type No.

Access Time

Package

15 ns

32 pin Ceramic Flat
(30 mil Lead Pitch)
(FG-28DB)

HM10151OF-15

Function

Ao-A19

Address Input

A12

A1S
A19

• PIN DESCRIPTION
Pin Name

A14

A13
A11

A10

CS

As

Vee

VEE

VEE

Vee

0,
WE

Do
As

OJ

Data Input

Ao

DO

Data Output

A1

A7
A6

WE

Write Enahle

A2

As

CS

Chip Select

A3

~

Vce

Ground

VEE

Supply Voltage

(Top View)

• BLOCK DIAGRAM

Memory Cell Array
104856 words

WE
CS

x 1 bits

RIW Circuit

~-----.--~~~~--.---~

Do
•

HITACHI

458 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300

-----------------------------HM101510Series

• FUNCTION TABLE
Input

Notes:

WE
Xl

Output

Mode

CS
H

Din
Xl

L

L

L

L

L

L

L

L

H

H
Xl

Dout2

Not Selected
Write "0"
Write "I"
Read

Rating
+0.5 to-7.0
+0.5 to VEE
-30
-65 to +150
-55 to +125

Unit
V
V
rnA
°C
°C

L

1. Irrelevant
2. Read Out Noninvert

• ABSOLUTE MAXIMUM RATING (Ta = 25°C)
Item
Supply Voltage
Input Voltage
Output Current
Storage Temperature
Storage Temperature
Note:

Symbol
VEE to VCC
Vin
lout
Tstg
Tstg (bias) I

I. Under bias (VEE = -6.0V min.)

• ELECTRICAL CHARACTERISTICS
• DC Characteristics (VEE = -5.2V, RL = 500 to -2.0V, TC = 0 to +85°C)
Item
Output Voltage

Min (B)

Symbol
VOH

-1025
-1810
-1035

VOL
Output Threshold V"ltage
Input Voltage

VOHC

-

VOLC
VIH

-1165

VIL

-1810

-

IIH
Input Current
Supply Current

0.5
-50
-180

IlL
lEE

Typ
-955

Max (A)
-880

Unit
mV

-1715

-1620

mV
mV
mV

-

-

-

-1610

Test Condition
Vin = VIHA or VILB
Vin = VIHB or VILA

-880
-1475

mV

220

J.lA

170

J.lA

-

J.lA
rnA

Vin=VIHA
Vin = VILB (CS)
Vin = VILB (Others)
All Outputs Open

Test Condition

mV

Guaranteed Input Voltage
High/Low for All Inputs

• AC CHARACTERISTICS (VEE = -5.2V ± 5%, Tc = 0 to +85°C)
• Read Mode
Item

Symbol

Chip Select Access Time
Chip Select Recovery Time
Address Access Time

tACS
tRCS
tAA

Min

-

-

Typ

Max

Unit

-

10
10
15

ns
ns
ns

.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 459

HM101510Series --------------------------------------------------------• Write Mode
Item
Write Pulse Width

Symbol

Min

tw

9
3
3
3
3
3
3

Data Setup Time

tWSD

Data Hold

twHD

Address Setup Time

tWSA

Address Hold Time

tWHA

Chip Select Setup Time

tWSCS

Chip Select Hold Time

tWHCS

Write Disable Time

tws

-

Write Recovery Time

tWR

-

Typ

Unit

Test Condition

-

Max

-

ns

tWSA = tWSA min

-

-

ns

-

-

ns

-

-

ns

-

-

ns

-

os

15

ns

18

os

ns
tw=twmin

• Rise/Fall Time
Item

Symbol

Output Rise Time

tr

Output Fall Time

tf

Min
-

Typ
1.5

-

1.5

Max
-

Unit

Test Condition

ns
os

• Capacitance
Item

Symbol

Input Capacitance

Cin

Output Capacitance

COUT

Min

Typ

-

3
5

• AC TEST CONDITION

Max
-

Unit

Test Condition

pF
pF

• INPUT PULSE

Vee (GND)

Doul
Ir = tf = 2.0 ns typo

M.U.T.

O.01~F

.,...

h

-2.0V

(include:; probe and
jig capacitance)

•

HITACHI

460 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

---------------------------------------------------------HM101510Series
• TIMING WAVEFORM

• Read

Dout

• Write

.......... ......... -

}- --------- ---------

----,

50%; , , - - - - - - - - - - - - - - - - - - -twHo-' ,

I

f... 50%

twso

Dout

...

/
tw

tWSA

tWHA
tWHCS

---- ...............
twscs
tws

•

tWR

1

50%

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 461

Section 6
FIFO Memory

.HITACHI®

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HM63921 Series

- - - - - - - - - - - - - - - Product Review

2K x 9-Bit CMOS Parallel In-Out FIFO Memory
• DESCRIPTION
The HM63921 is a First-In, First-Out memory that utilizes a high
performance static RAM array with internal algorithm that controls,
monitors and declares status of the memory by empty flag, full flag
and half-full flag, to prevent data overflow or underflow.
Expansion logic warrants unlimited expansion capability in width
and depth. Both read and write are independent from each other and
their corresponding pointers are designed to select the proper locations out of the entire array serially without address information to
load or unload data.
Data is toggled in and out of the device through the use of the write
enable (W) and read enable (R) pins. The device has a read/write
cycle time of 30/35/45ns. Organization of HM63921 provides a 9-bit
data bus. the ninth bit could be used for control or parity for error
checking at the option of the user. The HM63941 is fabricated using
the Hitachi CMOS 1.3micron technology. The device is available
in DIP.
•
•
•
•
•
•
•
•
•
•
•

FEATURES
First-In, First-Out Dual Port Memory
2k x 9 Organization
Low-Power CMOS 1.3micron Technology
Asynchronous and Simultaneous Read and Write
Fully Expandable in Depth and/or Width
Single 5V (± 10%) Power Supply
Empty and Full Warning Flags
Half-Full Flag
Access Time .................................20/25/35ns
Package ................. 300-mil 28-pin Plastic DIP Package

(OP-28NA)
• PIN ARRANGEMENT

Iii
Ds
D3
D2
D1
Do

vee
D4
D5
D6
D7

FLIRT
RS
EF
XO/HF

Xi
FF
00
01
02
03
Os

07
06
05
04
R

VSS

• ORDERING INFORMATION
Type Name

Access Time

Package

HM63921P-20
HM6392IP-25
HM6392IP-35

20ns
25ns
35ns

3OO-mil 28-pin
Plastic DIP
(DP-28NA)

(Top View)
• PIN DESCRIPTION
Pin Name

Function

Do-Os

Data Inputs

RS

Reset

W

Write Enable

R

Read Enable

FL

First Load

RT

Retransmit

XI

Expansion-In

XO

Expansion-Out

HF

Half-Full Flag

FF

Full Flag

EF

Empty Flag

Qo-Qs

Data Outputs

~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 465

HM63921 S e r i e S i - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• BLOCK DIAGRAM

00 01 02 03 04 05 06 07 08

W

Write
Pointer

Row
Decoder

Memory Array
2048X9

Row
Decoder

Read
Pointer

000102030405060708

Xi

XOtHF

•

HITACHI

466 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM63921 Series
• ABSOLUTE MAXIMUM RATINGS

Item
Terminal Voltage(l)
Power Dissipation
Operating Temperature
Storage Temperature
Storage Temperature Under Bias
NOTES:
I. Relative to Vss.
2. -3.5V for pulse width S IOns.

Symbol
VT

Rating
-0.5(2) to + 7.0
1.0
oto +70
-55 to + 125
-10 to +S5

PT
ToDr
T s!.
Tbias

Unit
V
W

·C
·C
·C

• Recommended DC Operating Conditions (T. = 0 to +70·C)

Symbol

Parameter
Supply Voltage
Input Voltage
NOTE:

Min.
4.5
0
2.2
-0.5(1)

Vee
Vss
V1H
V1L

Typ.
5.0
0

Max.
5.5
0
6.0
O.S

-

Unit
V
V
V
V

I. -3.0V for pulse width s IOns.

• DC CHARACTERISTICS (T. = O·C to +70·C, Vee = 5V ::I:: 10%)

Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current

Standby Power Supply Current
Output High Voltage
Output Low Voltage

Symbol
Test Conditions
Vee = 5.5V, Vin = OV - Vee
Ilui
R = V1H , YOU! = OV - Vee
IIwl
Icc I

Average Operating Current

ISBl
ISB2
VOH
VOL

R = W = RS = FLIRT = VIH
All inputs 2: Vee - 0.2V or s Vee
IOH = -4rnA
IOL = SrnA

Min.

Typ.

-

-

-

-

-20
-25
-35

-

-

-

Max.
2
2
120
110
100
10
1

2.4

-

-

-

-

0.4

Unit
pA

p.A
rnA
rnA
rnA
rnA
rnA
V
V

• CAPACITANCE (T. = 25·C, f = IMHz)

Symbol

Parameter
Input Capacitance
Output Capacitance
NOTE:

Test Conditions
Yin = OV
yOU! = OV

Cin
COU!

Typ.

-

-

Max.
6
10

Unit
pF
pF

I. This parameter is sampled and not 100% tested.

• AC CHARACTERISTICS (T.

= O·C to 70·C, Vee = 5 ::I::

10%)

• Test Conditions

• Input Pulse Levels: Vss to 3.0V
• Input and Output Timing Reference Level: 1.5V

• Input Rise and Fall Times: 5ns
• Output Load: See Figure

+5V

DOU~ 4800
2550 L j 3 0 pF •
Output Load
*lncIuding scope and jig.

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 467

HM63921 Series - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _-,-_ __
• Read Cycle
Parameter

Symbol

Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
Read Low to DB Low Z
Read High to DB High Z
Data Valid from Read High
Read Pulse Width After Empty Flag High
Write High to DB Low Z
(Read Data Flow Through Mode)
NOTE:

I.

tRLZ, tRHZ and twLZ are

tRC
tA
tRR
tRPW
tRLz(l)
tRHZ(l)
toH
tRPE
tWLZ(l)

HM63921-20
Min.
Max.
30
20
10
20
5
15
3
20
3

-

HM63921-25
Min.
Max.
35
25
10
25
5
15
3
25
3

-

HM63921-35
Min. Max.
45
35
10
35
5
20
3
35
3

-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

sampled and not 100% tested.

• Write Cycle
Parameter
Write Cycle Time
Write Recovery Time
Write Pulse Width
Data Setup Time
Data Hold Time
Effective Write Pulse Width After
Full Flag High

Symbol
twc
tWR
twpw

HM63921-20
Min.
Max.
30
10
20

tos
tOH

10
0

tWPF

20

-

HM63921-25
Min.
Max.
35
10
25
-

HM63921-35
Min. Max.
45
10
35

15
0

-

20
5

25

-

35

-

-

Unit
ns
ns
ns
ns
ns
ns

• ResetCycJe
Parameter
Reset Cycle Time
Reset Pulse Width

Symbol
tase
tRS

HM63921-20
Min. Max.
30
25
-

Reset Setup Time

tRSS

0

Reset R<:'-c.(IVerv Time

t-"-

!O

-

HM63921-25
Min.
Max.
35
25
0
!O

HM63921-35
Min. Max.
45
35
0
10

HM63921-25
Min. Max.
35
20
0
-

HM63921-35
Min. Max.
45
-

~

Unit
ns
ns
ns
ns

• Retransmit Cycle
Parameter
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Setup Time
Retransmit Recovery Time

Symbol
tRTC
tRT
tRTS
tRTR

HM63921-20
Min. Max.
30
20
0
10

~

-

10

-

35
0
10

-

-

_HITACHI
468 Hitachi America, ltd.• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300

Unit
ns
ns
os

ns

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM63921 Series
• Flag Timing

Parameter

Symbol

Reset to Empty Flag Low
Reset to Full Flag High
Reset to Half-Full Flag High

tEFL
tFFH

HM63921-20
Min.
Max.
20
20
-

tHFH

-

Read Low to Empty Flag Low

tREF

-

Read High to Full Flag High

tRFF

Write High to Empty Flag High
Write Low to Full Flag Low

tWEF
tWFF

Write Low to Half-Full Flag Low

tWHF

Read High to Half-Full Flag High

tRHF

-

HM63921-25
Min. Max.
25
25
-

HM63921-35
Min.
Max.
35

Unit

-

35

ns
ns

-

45

ns

-

35

ns

35

ns
ns
ns

30
20

-

35
25

20

-

25

20
20

-

-

35

-

25
25

-

30

-

35

-

35
45

30

-

35

-

45

ns
ns

• Expansion Timing

Parameter

Symbol

Expansion in Setup to Write or Read

tEFL

HM63921-20
Min.
Max.
15

tRFF

-

Expansion in Pulse Width

tWHF

10

Expansion Out High Delay From Clock

tREF

10

Expansion Out Low Delay From Clock

tRFF

10

Expansion in Recovery Time

•

15

-

HM63921-25
Min.
Max.
20

HM63921-35
Min.
Max.
30

Unit
ns

-

20

-

30

ns

10
10

-

10

-

ns

-

10

-

ns

10

-

IS

-

ns

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 469

HM63921 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - -

SIGNAL DESCRIPTIONS
Inputs
• Reset ('!!is)
The device is reset whenever '!!is input is taken to
low state, for minimum reset pulse width. When
device is reset, both read and write pointers are
set to the first location. A reset cycl!. is required
after power on. Both read enable (R) and write
enable fW) inputs must be in the high state durjng
reset. Empty ~ (EF) will go low and full flag (FF)
and half-full (HF) will go high during reset cycle.
• Write enable (iii)
_
Write cycle is initiated at the falling edge of W, if
the full flag (FF) is not set, provided that data setup and hold time requirements relative to the rising edge of 0N) are met. Data is stored in the device sequentially and independently of any simultaneous read operation. To inhibit further write operations and prevent internal data overflow full
flag (FF) will go low.
• Read enable (R)
_
Read cycle is initiated at the falling edge of R, if
the empty flag (EF) is not set. Data is accessed on
a first-in, first-out basis independently of ~multa­
neous write operation. As read enable (R) goes
high, all outputs will return to high impedance
state, till next read operation. After the last data
has been read from the FIFO, the empty flag (EF)
will go low, preventing further read operations with
0..!lli'ut kept in high impedance state. Empty flag
(EF) will go high during a valid write cycle (tWEF),
thereafter a valid read can start.
• First load/retransmit (FURT)
For depth expansion mode, this pin is grounded to
indicate that it is the first device, while this pin of
the rest of devices should connect to Vee for correct operation. In single device mode, this pin resets the read pOinter to the beginning of the FIFO
memory, therefore data can be reread from the
beginning. Both Rand W should be kept high
while RT i!ltaken low
• Expansion-in (Xi)
For single device mode expansi~n-in (Xi) is
grounded. Fo~ depth expansion mode,
expansion-in Qg) should be connected to
expansion-out (XO) of previous device.
• Data In (Do to Os)
Data inputs for 9-bit wide data.
Outputs
• Full Flag (FF)
The full flag (FF) will go low when FIFO is full,
inhibiting further write operations until one or
more read operations are completed or the FIFO
is reset.

tions, until one or more write operations are completed, or FIFO is set to. retransmit.
• Expansion-out (XC)/Half-full flag (HF)
This output has dual functionality depending how
it is used. In deJ!!t1 expansion configuration
expansion-o~ (XO) is connected to next
expansion-in (XI). The expansion-out (XC) Q!,.the
last FIFO is connected to the expansion-in (XI) of
the first FIFO. In this way the first FIFO indicates
the next FIFO that it will receive the next data. In
like manner, any FIFO which becomes full will indicate the next FIFO that it will receive the next data.
The second function of this output is in stand
alone and/or parallel expansion configurations to
indicate the system user that the FIFO is almost
full.
• Data outputs (00 to as)
Data outputs for 9-bit wide data. T~se outputs
are in high impedance state when R is in high
state.

VARIOUS OPERATIONS MODE
• Single device mode
_
If only one FIFO is used, the expansion-in (XI) pin
should be grounded.
• Width expansion mode
Width expansion by 9-bit increments may be
achieved when separately paralleling the data inputs and the data outputs. In this configuration
any flags of any device may be used. To avoid
output contention of the flags for short periods of
time, the flag outputs should not be wired together.
• Depth expansion mode
Multiple of FIFOs could provide multiple of 2k x 9
as (N) x (2k) by 9-bits wide, where N is the number of FIFOs connected in depth expansion
mode.
The following arrangement must be provided.
1. First load (FL) of the first F!FO should be connected to ground.
2. All other (FL) should be connected to Vee.
3. Connect the expansion-out (XO) of each FIFO
to e~nsion-in (Xi) of the..next FIFO serially
and XO of the last FIFO to XI of the first FIFO.
4. Connect all the empty flag (EF) t"Qgether to OR
gate and connect all the full flag (FF) together to
OR gate to obtain two separate valid empty flag
(EF) and full flag (FF) outputs.
5. (RT) and (AF) will not be available in this mode.
• Compound expansion mode
Combination of width and depth expansion
modes will provide larger FIFO arrays.

• Empty flag (EF) _
The empty flag (EF) will go low when the FIFO
becomes empty, inhibiting further read opera-

$ HITACHI
470 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - HM63921 Series

• TIMING WAVEFORM
• Read Cycle

aQ-Q8

Data out valid

Data out valid

• Write Cycle

twc
twpw

W

~K.

twpw

tWR

./ It'

"K.
tnJ..I~

tm:

( Data in valid ~

00-08

~

to!:

~

tnl-l

~ Data in valid ~

• Reset Cycle

R,W

tRSR

EF

FF

NOTES:

1.

W = R = VIH during reset.

2. tRse

= tRsT, IRSR.
•

HITACHI

Hitachi America, ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 471

HM63921 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Retransmit Cycle

FURT

tRTR

• Full-Flag Cycle

(From Last Write to First Read)
Last write

Additional reads

First Read

First Read

~

R

w
FF

• Empty-Flag Cycle

(From Last Read to First Write)
First Read

Last Read

First Read

00-08

•

HITACHI

472 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM63921 Series
• Half·Full Flag Cycle

Write=Read+ 1023

Write=Read+ 1024

Write .. Read+ 1023

"

I"tRHF

~

tWHF

"I\.

/

V

• Read Data Flow Through Mode

00-08

00-08

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 473

HM63921 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Write Data Flow Through Mode

FF

Data in valid

00-08

0D-08

• Expansion Out Cycle 1

w

Write to last
physical address ' ' '_ _ _~~
Read from last

~~~y_Si_Ca_l~a~dd~r~e)

I.""-l I.'''''}-

$

HITACHI

474 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM63921 Series
• Expansion Out Cycle 2 (Read Data Flow Through Mode)
Write to last physical address

w

----------------------~

,--------------------

• Expansion Out Cycle 3 (Write Data Flow Through Mode)
Read from last physical address

------------------------~

i----------------------

w

•

HITACHI

Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300 475

HM63921 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - - • Expansion In Cycle

tXOl

w
IxIS

•

Read from first
physical address

HITACHI

476 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300

HM63941 Series

- - - - - - - - - - - - - - - - Preliminary

4K x 9-Blt CMOS Parallel In-Out FIFO Memory
• DESCRIPTION
The HM63941 is a First-In, First-Out memory that utilizes a high
performance static RAM array with internal algorithm that controls,
monitors and declares status of the memory by empty flag, full flag
and almost-full flag, to prevent data overflow or underflow.
Expansion logic warrants unlimited expansion capability in width
and depth. Both read and write are independent from each other and
their corresponding pOinters are designed to select the proper locations out of the entire array serially without address Information to
load or unload data.
Data is toggled in and out of the device through the use of the write
enable (W) and read enable (Fi) pins. The device has a read/write
cycle time of 35/45/60ns. Organization of HM63941 provides a 9-bit
data bus. the ninth bit could be used for control or parity for error
checking at the option of the user. The HM63941 is fabricated using
the Hitachi CMOS 1.3micron technology. The device is available
in DIP.
•
•
•
•
•
•
•
•
•
•
•

FEATURES
First-In, First-Out Dual Port Memory
4k x 9 Organization
Low-Power CMOS 1.3micron Technology
Asynchronous and Simultaneous Read and Write
Fully Expandable in Depth and/or Width
Single 5V ('*' 10%) Power Supply
Empty and Full Warning Flags
Almost-Full Flag
Access Time .................................25/35/45ns
Package ..............................2S-pin DIP Package

(DP-28NA)

• PIN ARRANGEMENT

W
D8
D3
D2
D1
Do

Vee
D4
Ds
D6
D7
FURT
RS
EF
XO/AF

>IT
i=F
00
01
02
03
08

07
06
Os

04

R

Vss

• ORDERING INFORMATION
Type Name

Access Time

Package

HM63941P-25
HM63941P-35
HM63941P-45

25ns
35ns
45ns

28-pin Plastic DIP

(Top View)

• PIN DESCRIPTION
Pin Name
Do-Os
RS
W
R
FL
RT
XI
XO
AF
FF
EF
QO-Q8

Function
Data inputs
Reset
Write enable
Read enable
First load
Retransmit
Expansion-in
Expansion-out
Almost-full flag
FuJI flag
Empty flag
Data outputs

_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300 477

HM63941 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Symbol
VT

Item
Terminal Voltage(l)
Power Dissipation
Operating Temperature
Storage Temperature
Storage Temperature Under Bias
NOTES: 1. Relative to Vss.
2. -3.SV for pulse width :s IOns.

Rating
-0.5(2) to +7.0
1.0
Oto +70
-55 to +125
-10 to +85

PT

Topr
Tstg
Tbias

Unit
V
W
°C
°C
°C

• ELECTRICAL CHARACTERISTICS
• Recommended DC Operating Conditions (T. = 0 to +70°C)
Parameter

Symbol

Min.
4.5
0
2.0
-0.5(1)

Vee
Vss
VIH
VIL

Supply Voltage
Input Voltage

Typ.
5.0
0

Max.
5.5
0
6.0
0.8

-

-

Unit
V
V
V
V

1. -3.0V for pulse width :s IOns.

NOTE:

• DC CHARACTERISTICS (T.
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Curront
Standby Power Supply Current
Output High Voltage
Output Low Voltage

= O°C to +70°C, Vee = 5V

:i:

10%)

Test Conditions
Symbol
Vee
=
5.5V,
Yin = OV - Vee
Ilul
R = VIH , Vout = OV - Vee
IILOI
Average Operating Current
Ice I
Iccz R = W = RS = FLIRT = VIH
All Inputs O!: Vee - 0.2V or s Vee
ISB
VOH
IOH =-4mA
IoL = SmA
VOL

Min.

Typ.

-

-

-

-

Max.
2
2
80
10
1

2.4

-

0.4

-

Unit
p.A
p,A
mA
mA
mA
V
V

-

• CAPACITANCE (Ta = 25°C, f = IMHz)

I
I

Parameter
Input Capacitance
~

.

.

~

~

. - -- - -

!

UUlPUl \...IP""lIiUI"C::

• AC CHARACTERISTICS (T.

qn

I
I

ro

!

Symbol
....out

Test Conditions
Yin = OV
\T

"out

= O°C to 70°C, Vee = 5 :i:

:

n\1

Typ.

-

Max.
TBD

Unit
pF

-

'l'Rn

nP

...

10%)

• r,st CondItions
• Input Rise and Fall Times: 5ns
• Output Load: See Figure

• Input Pulse Levels: Vss to 3.0V
• Input and Output Timing Reference Level: 1.5V

+5V

4800

Dout

2550

L

30pF*
h7

Output Load
*Including scope and jig.

•

HITACHI

478 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300

-------------------------------------------------------------HM639~Series

• Read Cycle

Parameter
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
Read Low to DB Low Z
Read High to DB High Z
Data Valid from Read High

Symbol
tRC
tA
tRR
tRPW
tRLZ
tRHZ
toH

HM63941-25
Min.
Max.
35
25
10
25
5
15
5
-

HM63941-35
Min.
Max.
45
35
10
35
5
20
5
-

HM63941-45
Min.
Max.
60
45
15
45
10
25
5
-

HM63941-25
Min.
Max.
35
10
-

HM63941-35
Min.
Max.
45
10
-

HM63941-45
Min.
Max.
60
-

Unit
ns
ns
ns
ns
ns
ns
ns

• Write Cycle

Parameter
Write Cycle Time
Write Recovery Time

Symbol
twc

Write Pulse Width

tWR
twpw

20

--

35

Data Setup Time

tDS

15

-

20

-

tDH

0

-

0

-

Data Hold Time

Unit

15
45

-

ns
ns

-

ns

25

-

ns

5

-

ns

• Reset Cycle

Parameter
Reset Cycle Time
Reset Pulse Width
Reset Recovery Time

Symbol
tRsc
tRS
tRSR

HM63941-25
Max.
Min.
35
25
10
-

HM63941-35
Min.
Max.
45
35
10
-

HM63941-45
Min.
Max.
60
45
15
-

HM63941-25
Min.
Max.
35
20
:0
-

HM63941-35
Min.
Max.
45
35
10
-

HM63941-45
Min.
Max.
60
45
15
-

HM63941-25
Min.
Max.
30
25
25
25
25
30
30

HM63941-35
Min.
Max.
45
35
35
35
35
40
40

HM63941-45
Max.
Min.
60
45
45
45
45
55
55

Unit
ns
ns
ns

• Retransmit Cycle

Parameter
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time

Symbol
tRTC
tRT
tRTR

Unit
ns
ns
ns

• Flag Timing

Parameter
Reset to Empty Flag Low
Read Low to Empty Flag Low
Read High to Full Flag High
Write High to Empty Flag High
Write Low to Full Flag Low
Write Low to Almost-Full Low
Read High to Almost-Full High

Symbol
tEFL
tREF
tRFF
tWEF
tWFF
tWAF
tRAF

Unit
ns
ns
ns
ns
ns
ns
ns

.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 479

HM63941 Series - - - - - - - - - - - - - - - - - - - - - - - - - - - SIGNAL DESCRIPTIONS
Inputs
• Reset (RS)
_
The device is reset whenever RS input is taken to
low state, for minimum reset pulse width. When
device is reset, both read and write pointers are
set to the first location. A reset cycle is required
after power on. Both read enable (R) and write
enable (iN) inputs !!!.!:!st be in the high state dur.!!!g
reset. Empty flaliEF) will go low and full flag (FF)
and almost-full (AF) will go high during reset cycle.
• Write enable rN)
_
Write cycle i!lnitiated at the falling edge of W, if
the full flag (FF) is not set, provided that data setup and hold time requirements relative to the rising edge of (Vii) are met. Data is stored in the device sequentially and independently of any simultaneous read operation. To inhibit further write operations and prevent internal data overflow full
flag (l!J!') will go low.
• Read enable (R)
_
Read cycle is initiated at the falling edge of R, if
the empty flag (EF) is not set. Data is accessed on
a first-in, first-out basis independently of simultaneous write operation. As read enable (R) goes
high, all outputs will return to high impedance
state, till next read operation. After the last data
has been read from the FIFO, the empty flag (~)
will go low, preventing further read operations with
o..!;!!put kept in high impedance state. Empty flag
(EF) will go high during a valid write cycle (tWEF),
thereafter a valid read can start.
• First load/retransmit (f.'uR'f)
For depth expansion mode, this pin is grounded to
indicate that it is the first device, while this pin of
the rest of devices should connect to Vee for correct operation. In single device mode, this pin resets the read pOinter to the beginning of the FIFO
memory, therefor!. data £!n be reread from the
beginning. Both Rand W should be kept high
while RT is take!"! low.
• Expansion-in (Xi)
_
For single device mode expansion-in (XI) is
grounded. FOL- depth expansion mode,
expansion-in Qill should be connected to
expansion-out (XO) of previous device.
• Data In (Do to Os)
Data inputs for 9-bit wide data.
Outputs
• Full Flag (FF)
The full flag (FF) will go low when FIFO is full,
inhibiting further write operations until one or
more read operations are completed or the FIFO
is reset.
• Empty flag (EF) _
The empty flag (EF) will go low when the FIFO
becomes empty, inhibiting further read opera-

•

tions, until one or more write operations are completed, or FIFO is set to retransmit.
• Expansion-out (XO)/Almost-full flag (AF)
This output has dual functionality depending how
it is used. In deJ!!tl expansion configuration
expansion-out (XO) is connected to next
expansion-in (Xi). The expansion-out (XO) of the
last FIFO is connected to the expansion-in (Xi) of
the first FIFO. In this way the first FIFO indicates
the next FIFO that it will receive the next data. In
like manner, any FIFO which becomes full will indicate the next FIFO that it will receive the next data.
The second function of this output is in stand
alone and/or parallel expansion configurations to
indicate the system user that the FIFO is almost
full.
• Data outputs (00 to as)
Data outputs for 9-bit wide data. These outputs
are in high impedance state when R is in high
state.
VARIOUS OPERATIONS MODE
• Single device mode
If only one FIFO is used, the expansion-in (Xi) pin
should be grounded.
• Width expansion mode
Width expansion by 9-bit increments may be
achieved when separately paralleling the data inputs and the data outputs. In this configuration
any flags of any device may be used. To avoid
output contention of the flags for short periods of
time, the flag outputs should not be wired together.
• Depth expansion mode
Multiple of FIFOs could provide multiple of 4k x 9
as (N) x (4k) by 9-bits wide, where N is the number of FIFOs connected in depth expansion
mode.
The following arrangement must be provided.
1. First load (FL) of thl'l fir$f FIFO ShOtl!d be oo!"!nected to ground.
2. All other (FL) should be connected to Vee.
3. Connect the expansion-out (XC) of each FIFO
to e~nsion-in (XI) of theJ!ext FIFO serially
and XO of the last FIFO to XI of the first FIFO.
4. Connect all the empty flag (EF) t.Qgether to OR
gate and connect all the full flag (FF) together to
OR gate to obtain two separate valid empty flag
(EF) and full flag (f.'f.') outputs.
5. (RT) and (AF) will not be available in this mode.
• Compound expansion mode
Combination of width and depth expansion
modes will provide larger FIFO arrays.

HITACHI

480 Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM63941 Series
• TIMING WAVEFORM

• Read Cycle

00-08

Data out valid

Data out valid

• Write Cycle

we
twpw

w

tWR

.;Io!

I\.
tos

I'\.

tOH

KData in valid)

00-08

/ Data in valid:>

• Reset Cycle

RS

"-

/V

w

~

tRSR

tEFL

"'-

EF

NOTES:

I. W

2.

= R = VIH during reset.

tRSC

= tRST. tRSR.

•

HITACHI

Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 481

HM63941 Series - - - - - - - - - - - - - - - - - - - - - - - - • Retransmit Cycle

FURT

tRTR

• Full-Flag Cycle (From Last Write to First Read)
Last write

First Read

Additional reads

First Read

w

• Full-Flag Cycle (Effective Write Pulse Width After" High)

FF
W

.HITACHI
482 Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HM63941 Series
• Empty·Flag Cycle

(From Last Write to First Read)
First Read

First Write

Last Read

w

EF

Data Out

• Empty·Flag Cycle

(Effective Read Pulse Width After EF High)

w

" ~----/I~
1-

EF

• Almost·Full Flag Cycle

w

Write=Read+4079

Write=Read+4080

Write.. Read+4079

'\
I~RAF..

/
tWAF

~K

.. V

.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 483

NOTES

484

NOTES

485

Hitachi America, Ltd.
SEMICONDUCTOR & I.C. DIVISION
Hitachi America, Ltd.
Semiconductor & I.C. Division
Hitachi Plaza
2000 Sierra Point Parkway
Brisbane, CA 94005·1819
Telephone: 415·589·8300
Telex: 17·1581
Twx: 910·338·2103
FAX: 415·583·4207

REGIONAL OFFICES
TELECOM REGION

NORTHWEST REGION

SOUTHEAST REGION

Hitachi America, Ltd.
325 Columbia Turnpike
Suite 203
Florham Park, NJ 07932

Hitachi America, Ltd.
1900 McCarthy Boulevard
Suite 310
Milpitas, CA 95035

Hitachi America, Ltd.
401 Harrison Oaks Boulevard
Suite 100
Cary, NC 27513

201/514·2100

408/954·8100

919/677·0160

NORTHEAST REGION

SOUTH CENTRAL REGION

AUTOMOTIVE REGION

Hitachi America, Ltd.
77 South Bedford Street
Burlington, MA 01803

Hitachi America, Ltd.
Two Lincoln Centre, Suite 865
5420 LBJ Freeway
Dallas, TX 75240

Hitachi America, Ltd.
330 Town Center Drive
Suite 311
Dearborn, MI48126

214/991·4510

313/271·4410

617/229·2150

NORTH CENTRAL REGION
Hitachi America, Ltd.
500 Park Boulevard, Suite 415
Itasca, IL 60143
708/773·4864

SOUTHWEST REGION
Hitachi America, Ltd.
2030 Main Street
Suite 450
Irvine, CA 92714
714/553·8500

DISTRICT OFFICES
Hitachi America, Ltd.
3800 W. 80th Street, Suite 1050
Bloomington, MN 55431

Hitachi America, Ltd.
6161 Savoy Drive, Suite 850
Houston, TX 77036

Hitachi America, Ltd.
4901 N.W. 17th Way, Suite 302
Fort Lauderdale, FL 33309

612/896·3444

713/974·0534

305/491 ·6154

Hitachi America, Ltd.
21 Old Main Street, Suite 104
Fishkill, NY 12524

Hitachi (Canadian) Ltd.
320 March Road, Suite 602
Kanata, OntariO, Canada K2K 2E3

914/897·3000

613/591 ·1990

.HITACHI@
486

SRAM Data Book Errata
The following are corrections to the SRAM Data Book
(Order Number M12T014). Note the changes and
update accordingly.

•

HM658512 Series-Page 395
• 120 ns Access Time and 190 ns Cycle Time not
available
• LL and D versions no longer available
• Ordering Information revised.

•

HM658512 Series-Page 399
• AC Characteristics TableHM658512-12 Min.-Max. vertical column
removed.

Note: The following two pages illustrate the
technical data as it should appear.

~HITACHI®

HM658512 Series
524,28S·Word x 8·Bit High Speed Pseudo Static RAM
Features
• Single5V(± 10%)
• High speed
Access time

CE access time .........................801100 ns
Cycle time
Random read/write cycle time ............. 130/160 ns
• Lowpower
Active:
Standby:

250 mW (typ.)
200 "W (typ.)

• All inputs and outputs TTL compatible
• Package
32-pin dual-in-line plastic package

(FP-32D)

32-pin SOP package

• PIN ARRANGEMENT

• Non multiplexed address
• 2048 refresh cycles (32 ms)

A,B

Vee

• Refresh functions

A'6
A'4
A'2
A7

A,S
A17
WE

As

As

As
A4

Ag

A3

()E/RFSH

A2
Al
Ao

A'0
CE
1107

LlLV-version ........•..............Address refresh
Automatic refresh
Self refresh

• ORDERING INFORMATION
-_."---

Typl' No.

Access Time

Package

HM658512f.P X
HM6585121.P-IO

80 ns
100 ns

HM6585121.P-HI.V
HM6585121.P-IOLV

80 ns
100 ns

600 mil
32 pin
Plastic DIP
(OP-32)

HM6585121.FP-X
HM658512LFP-IO

80 ns
100 ns

HM658512LFP-XLV
HM658512LFP-IOLV

80 ns
lOOns

A'3

All

1/00

1l0a

1101

1/05
1104

1/02

1/03

Vss

32 pin
Plastic SOP
(FP-320)

(Top View)

• PIN DESCRIPTION

................
Ao-AI8

•

rum;uon

Address

1100 -1107

Input/Output

CE

Chip Enable

OE/RFSH

Output Enable/Refresh

WE

Write Enable

Vee

Power Supply

Vss

Ground

HITACHI

Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300 395

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HM658512 Series
• AC CHARACTERISTICS (TA

= 0 to 70 e. Vee = 5V
D

HM658512-8

HM658512-IO

Min.

Max.

Min.

Symbol

Item

Unit

Note

Max.

Random Read or Write Cycle Time

tRC

130

-

160

-

ns

Chip Enable Access Time

teEA

-

80

-

100

ns

Read-Modify-Write Cycle Time

tRwC

180

-

220

-

ns

Output Enable Access Time

toEA

-

30

-

40

ns

Chip Disable to Output in High-Z

teHZ

0

25

0

25

ns

I

Chip Enable to Output in Low-Z

teLz

20

-

20

-

ns

2

Output Disable to Output in High-Z

toHZ

-

25

-

25

ns

I

Output Enable to Output in Low-Z

tOLl.

0

-

0

-

ns

2

Chip Enable Pulse Width

10l's

teE

80 ns

10l's

100 ns

Chip Enable Pre-Charge Time

tp

40

-

50

-

Address Setup Time

tAS

0

-

0

-

ns

Address Hold Time

tAH

20

-

25

-

ns

Read Command Setup Time

tRes

0

-

0

-

ns

Read Command Hold Time

tRCH

0

-

0

-

ns

Write Command Pulse Width

twp

25

-

30

-

ns

Chip Enable to End of Write

tcw

80

-

100

-

ns

Chip Enable to Output Enable Delay Time

toeD

0

-

0

-

ns

-

15

-

ns

Output Enaole Hold Time

ns

tOHc

15

Data in to End of Write

tDW

20

-

25

-

ns

Data in Hold Time for Write

tDH

0

0

-

ns

Output Active From End of Write

tow

5

-

5

-

ns

2

Write to Output in High-Z

tWHZ

-

20

-

25

ns

I

Transition Time (Rise and Fall)

tT

3

50

3

50

ns

Refresh Command Delay Time

tRFD

40

-

50

-

ns

Refresh Precharge Time

tFP

40

-

40

-

ns

Refresh Command Pulse "Width for Automatic Refresh

tFAP

80 ns

8i'S

80 ns

81'S

Automatic Refresh Cycle Time

tFC

130

-

160

-

Refresh Command Pulse Width for Self Refresh

tFAS

8

-

8

-

600

-

600

-

-

32

-

32

Refresh Reset Time From Self Refresh

tRFS

Refresh Period
NOTES:

± 10%)

tREF

- -f--._ns
-- f - - - - - I's
-- - - - - ns
ms

2048 cycle

I. tCHZ. toHZ and tWHZ are defined as the lime al wh.ich the output achieves the open circuit condition.

2. 'ClZ. tOlZ and tow are sampled under the condition oftT = 5 ns and not 100% tested

CE and low WE.
CE low transition (l(.."Curs simultaneously with or Jailer from

3. A write occurs during the overlap of low
4. If the

S. In write cycle,

the WE 10Y0' transition. the output buffers remain

In

high impedance stale.

OE or WE must disable output blJffer~ prior 10 applying data 10 Ihe device and al the end of wrile cycle data inputs must be goated prior 10 DE or WE

turning on output buffers.
6. Transition lime IT is measured belween V,H (min.) and VIL (max.).
7. After power-up. pause for more than 100 jl!l and execute at least 8 initialization cycles. preferably as 8 refresh cyeles.

8. 2048 cycles of burst refresh or distributed automatic refresh must be executed within 15 IlS after self refresh. in order to meet the refresh
specification of 32 ms and 2048 cycle.

~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 399

Our Standards Set Standards

Hitachi America, Ltd.
Semiconductor & I.e. Division
Hitachi Plaza
2000 Sierra Point Parkway, Brisbane, CA 94005-1819
1-415-589-8300

1091/20M/GI/RD
Order Number: M12T014



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